1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "x86-isel"
16 #include "X86ISelLowering.h"
18 #include "X86InstrBuilder.h"
19 #include "X86TargetMachine.h"
20 #include "X86TargetObjectFile.h"
21 #include "Utils/X86ShuffleDecode.h"
22 #include "llvm/CallingConv.h"
23 #include "llvm/Constants.h"
24 #include "llvm/DerivedTypes.h"
25 #include "llvm/GlobalAlias.h"
26 #include "llvm/GlobalVariable.h"
27 #include "llvm/Function.h"
28 #include "llvm/Instructions.h"
29 #include "llvm/Intrinsics.h"
30 #include "llvm/LLVMContext.h"
31 #include "llvm/CodeGen/IntrinsicLowering.h"
32 #include "llvm/CodeGen/MachineFrameInfo.h"
33 #include "llvm/CodeGen/MachineFunction.h"
34 #include "llvm/CodeGen/MachineInstrBuilder.h"
35 #include "llvm/CodeGen/MachineJumpTableInfo.h"
36 #include "llvm/CodeGen/MachineModuleInfo.h"
37 #include "llvm/CodeGen/MachineRegisterInfo.h"
38 #include "llvm/MC/MCAsmInfo.h"
39 #include "llvm/MC/MCContext.h"
40 #include "llvm/MC/MCExpr.h"
41 #include "llvm/MC/MCSymbol.h"
42 #include "llvm/ADT/SmallSet.h"
43 #include "llvm/ADT/Statistic.h"
44 #include "llvm/ADT/StringExtras.h"
45 #include "llvm/ADT/VariadicFunction.h"
46 #include "llvm/Support/CallSite.h"
47 #include "llvm/Support/Debug.h"
48 #include "llvm/Support/ErrorHandling.h"
49 #include "llvm/Support/MathExtras.h"
50 #include "llvm/Target/TargetOptions.h"
55 STATISTIC(NumTailCalls, "Number of tail calls");
57 // Forward declarations.
58 static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
61 /// Generate a DAG to grab 128-bits from a vector > 128 bits. This
62 /// sets things up to match to an AVX VEXTRACTF128 instruction or a
63 /// simple subregister reference. Idx is an index in the 128 bits we
64 /// want. It need not be aligned to a 128-bit bounday. That makes
65 /// lowering EXTRACT_VECTOR_ELT operations easier.
66 static SDValue Extract128BitVector(SDValue Vec, unsigned IdxVal,
67 SelectionDAG &DAG, DebugLoc dl) {
68 EVT VT = Vec.getValueType();
69 assert(VT.is256BitVector() && "Unexpected vector size!");
70 EVT ElVT = VT.getVectorElementType();
71 unsigned Factor = VT.getSizeInBits()/128;
72 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT,
73 VT.getVectorNumElements()/Factor);
75 // Extract from UNDEF is UNDEF.
76 if (Vec.getOpcode() == ISD::UNDEF)
77 return DAG.getUNDEF(ResultVT);
79 // Extract the relevant 128 bits. Generate an EXTRACT_SUBVECTOR
80 // we can match to VEXTRACTF128.
81 unsigned ElemsPerChunk = 128 / ElVT.getSizeInBits();
83 // This is the index of the first element of the 128-bit chunk
85 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits()) / 128)
88 SDValue VecIdx = DAG.getConstant(NormalizedIdxVal, MVT::i32);
89 SDValue Result = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec,
95 /// Generate a DAG to put 128-bits into a vector > 128 bits. This
96 /// sets things up to match to an AVX VINSERTF128 instruction or a
97 /// simple superregister reference. Idx is an index in the 128 bits
98 /// we want. It need not be aligned to a 128-bit bounday. That makes
99 /// lowering INSERT_VECTOR_ELT operations easier.
100 static SDValue Insert128BitVector(SDValue Result, SDValue Vec,
101 unsigned IdxVal, SelectionDAG &DAG,
103 // Inserting UNDEF is Result
104 if (Vec.getOpcode() == ISD::UNDEF)
107 EVT VT = Vec.getValueType();
108 assert(VT.is128BitVector() && "Unexpected vector size!");
110 EVT ElVT = VT.getVectorElementType();
111 EVT ResultVT = Result.getValueType();
113 // Insert the relevant 128 bits.
114 unsigned ElemsPerChunk = 128/ElVT.getSizeInBits();
116 // This is the index of the first element of the 128-bit chunk
118 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits())/128)
121 SDValue VecIdx = DAG.getConstant(NormalizedIdxVal, MVT::i32);
122 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec,
126 /// Concat two 128-bit vectors into a 256 bit vector using VINSERTF128
127 /// instructions. This is used because creating CONCAT_VECTOR nodes of
128 /// BUILD_VECTORS returns a larger BUILD_VECTOR while we're trying to lower
129 /// large BUILD_VECTORS.
130 static SDValue Concat128BitVectors(SDValue V1, SDValue V2, EVT VT,
131 unsigned NumElems, SelectionDAG &DAG,
133 SDValue V = Insert128BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
134 return Insert128BitVector(V, V2, NumElems/2, DAG, dl);
137 static TargetLoweringObjectFile *createTLOF(X86TargetMachine &TM) {
138 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
139 bool is64Bit = Subtarget->is64Bit();
141 if (Subtarget->isTargetEnvMacho()) {
143 return new X86_64MachoTargetObjectFile();
144 return new TargetLoweringObjectFileMachO();
147 if (Subtarget->isTargetLinux())
148 return new X86LinuxTargetObjectFile();
149 if (Subtarget->isTargetELF())
150 return new TargetLoweringObjectFileELF();
151 if (Subtarget->isTargetCOFF() && !Subtarget->isTargetEnvMacho())
152 return new TargetLoweringObjectFileCOFF();
153 llvm_unreachable("unknown subtarget type");
156 X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
157 : TargetLowering(TM, createTLOF(TM)) {
158 Subtarget = &TM.getSubtarget<X86Subtarget>();
159 X86ScalarSSEf64 = Subtarget->hasSSE2();
160 X86ScalarSSEf32 = Subtarget->hasSSE1();
161 X86StackPtr = Subtarget->is64Bit() ? X86::RSP : X86::ESP;
163 RegInfo = TM.getRegisterInfo();
164 TD = getTargetData();
166 // Set up the TargetLowering object.
167 static const MVT IntVTs[] = { MVT::i8, MVT::i16, MVT::i32, MVT::i64 };
169 // X86 is weird, it always uses i8 for shift amounts and setcc results.
170 setBooleanContents(ZeroOrOneBooleanContent);
171 // X86-SSE is even stranger. It uses -1 or 0 for vector masks.
172 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
174 // For 64-bit since we have so many registers use the ILP scheduler, for
175 // 32-bit code use the register pressure specific scheduling.
176 // For Atom, always use ILP scheduling.
177 if (Subtarget->isAtom())
178 setSchedulingPreference(Sched::ILP);
179 else if (Subtarget->is64Bit())
180 setSchedulingPreference(Sched::ILP);
182 setSchedulingPreference(Sched::RegPressure);
183 setStackPointerRegisterToSaveRestore(X86StackPtr);
185 if (Subtarget->isTargetWindows() && !Subtarget->isTargetCygMing()) {
186 // Setup Windows compiler runtime calls.
187 setLibcallName(RTLIB::SDIV_I64, "_alldiv");
188 setLibcallName(RTLIB::UDIV_I64, "_aulldiv");
189 setLibcallName(RTLIB::SREM_I64, "_allrem");
190 setLibcallName(RTLIB::UREM_I64, "_aullrem");
191 setLibcallName(RTLIB::MUL_I64, "_allmul");
192 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall);
193 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall);
194 setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::X86_StdCall);
195 setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::X86_StdCall);
196 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::X86_StdCall);
198 // The _ftol2 runtime function has an unusual calling conv, which
199 // is modeled by a special pseudo-instruction.
200 setLibcallName(RTLIB::FPTOUINT_F64_I64, 0);
201 setLibcallName(RTLIB::FPTOUINT_F32_I64, 0);
202 setLibcallName(RTLIB::FPTOUINT_F64_I32, 0);
203 setLibcallName(RTLIB::FPTOUINT_F32_I32, 0);
206 if (Subtarget->isTargetDarwin()) {
207 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
208 setUseUnderscoreSetJmp(false);
209 setUseUnderscoreLongJmp(false);
210 } else if (Subtarget->isTargetMingw()) {
211 // MS runtime is weird: it exports _setjmp, but longjmp!
212 setUseUnderscoreSetJmp(true);
213 setUseUnderscoreLongJmp(false);
215 setUseUnderscoreSetJmp(true);
216 setUseUnderscoreLongJmp(true);
219 // Set up the register classes.
220 addRegisterClass(MVT::i8, &X86::GR8RegClass);
221 addRegisterClass(MVT::i16, &X86::GR16RegClass);
222 addRegisterClass(MVT::i32, &X86::GR32RegClass);
223 if (Subtarget->is64Bit())
224 addRegisterClass(MVT::i64, &X86::GR64RegClass);
226 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
228 // We don't accept any truncstore of integer registers.
229 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
230 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
231 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
232 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
233 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
234 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
236 // SETOEQ and SETUNE require checking two conditions.
237 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
238 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
239 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
240 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
241 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
242 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
244 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
246 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
247 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
248 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
250 if (Subtarget->is64Bit()) {
251 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
252 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
253 } else if (!TM.Options.UseSoftFloat) {
254 // We have an algorithm for SSE2->double, and we turn this into a
255 // 64-bit FILD followed by conditional FADD for other targets.
256 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
257 // We have an algorithm for SSE2, and we turn this into a 64-bit
258 // FILD for other targets.
259 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
262 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
264 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
265 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
267 if (!TM.Options.UseSoftFloat) {
268 // SSE has no i16 to fp conversion, only i32
269 if (X86ScalarSSEf32) {
270 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
271 // f32 and f64 cases are Legal, f80 case is not
272 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
274 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
275 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
278 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
279 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
282 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
283 // are Legal, f80 is custom lowered.
284 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
285 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
287 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
289 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
290 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
292 if (X86ScalarSSEf32) {
293 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
294 // f32 and f64 cases are Legal, f80 case is not
295 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
297 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
298 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
301 // Handle FP_TO_UINT by promoting the destination to a larger signed
303 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
304 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
305 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
307 if (Subtarget->is64Bit()) {
308 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
309 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
310 } else if (!TM.Options.UseSoftFloat) {
311 // Since AVX is a superset of SSE3, only check for SSE here.
312 if (Subtarget->hasSSE1() && !Subtarget->hasSSE3())
313 // Expand FP_TO_UINT into a select.
314 // FIXME: We would like to use a Custom expander here eventually to do
315 // the optimal thing for SSE vs. the default expansion in the legalizer.
316 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
318 // With SSE3 we can use fisttpll to convert to a signed i64; without
319 // SSE, we're stuck with a fistpll.
320 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
323 if (isTargetFTOL()) {
324 // Use the _ftol2 runtime function, which has a pseudo-instruction
325 // to handle its weird calling convention.
326 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Custom);
329 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
330 if (!X86ScalarSSEf64) {
331 setOperationAction(ISD::BITCAST , MVT::f32 , Expand);
332 setOperationAction(ISD::BITCAST , MVT::i32 , Expand);
333 if (Subtarget->is64Bit()) {
334 setOperationAction(ISD::BITCAST , MVT::f64 , Expand);
335 // Without SSE, i64->f64 goes through memory.
336 setOperationAction(ISD::BITCAST , MVT::i64 , Expand);
340 // Scalar integer divide and remainder are lowered to use operations that
341 // produce two results, to match the available instructions. This exposes
342 // the two-result form to trivial CSE, which is able to combine x/y and x%y
343 // into a single instruction.
345 // Scalar integer multiply-high is also lowered to use two-result
346 // operations, to match the available instructions. However, plain multiply
347 // (low) operations are left as Legal, as there are single-result
348 // instructions for this in x86. Using the two-result multiply instructions
349 // when both high and low results are needed must be arranged by dagcombine.
350 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
352 setOperationAction(ISD::MULHS, VT, Expand);
353 setOperationAction(ISD::MULHU, VT, Expand);
354 setOperationAction(ISD::SDIV, VT, Expand);
355 setOperationAction(ISD::UDIV, VT, Expand);
356 setOperationAction(ISD::SREM, VT, Expand);
357 setOperationAction(ISD::UREM, VT, Expand);
359 // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences.
360 setOperationAction(ISD::ADDC, VT, Custom);
361 setOperationAction(ISD::ADDE, VT, Custom);
362 setOperationAction(ISD::SUBC, VT, Custom);
363 setOperationAction(ISD::SUBE, VT, Custom);
366 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
367 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
368 setOperationAction(ISD::BR_CC , MVT::Other, Expand);
369 setOperationAction(ISD::SELECT_CC , MVT::Other, Expand);
370 if (Subtarget->is64Bit())
371 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
372 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
373 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
374 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
375 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
376 setOperationAction(ISD::FREM , MVT::f32 , Expand);
377 setOperationAction(ISD::FREM , MVT::f64 , Expand);
378 setOperationAction(ISD::FREM , MVT::f80 , Expand);
379 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
381 // Promote the i8 variants and force them on up to i32 which has a shorter
383 setOperationAction(ISD::CTTZ , MVT::i8 , Promote);
384 AddPromotedToType (ISD::CTTZ , MVT::i8 , MVT::i32);
385 setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i8 , Promote);
386 AddPromotedToType (ISD::CTTZ_ZERO_UNDEF , MVT::i8 , MVT::i32);
387 if (Subtarget->hasBMI()) {
388 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16 , Expand);
389 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32 , Expand);
390 if (Subtarget->is64Bit())
391 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
393 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
394 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
395 if (Subtarget->is64Bit())
396 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
399 if (Subtarget->hasLZCNT()) {
400 // When promoting the i8 variants, force them to i32 for a shorter
402 setOperationAction(ISD::CTLZ , MVT::i8 , Promote);
403 AddPromotedToType (ISD::CTLZ , MVT::i8 , MVT::i32);
404 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Promote);
405 AddPromotedToType (ISD::CTLZ_ZERO_UNDEF, MVT::i8 , MVT::i32);
406 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Expand);
407 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Expand);
408 if (Subtarget->is64Bit())
409 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
411 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
412 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
413 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
414 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Custom);
415 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Custom);
416 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Custom);
417 if (Subtarget->is64Bit()) {
418 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
419 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom);
423 if (Subtarget->hasPOPCNT()) {
424 setOperationAction(ISD::CTPOP , MVT::i8 , Promote);
426 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
427 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
428 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
429 if (Subtarget->is64Bit())
430 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
433 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
434 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
436 // These should be promoted to a larger select which is supported.
437 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
438 // X86 wants to expand cmov itself.
439 setOperationAction(ISD::SELECT , MVT::i8 , Custom);
440 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
441 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
442 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
443 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
444 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
445 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
446 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
447 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
448 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
449 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
450 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
451 if (Subtarget->is64Bit()) {
452 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
453 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
455 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
458 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
459 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
460 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
461 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
462 if (Subtarget->is64Bit())
463 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
464 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
465 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom);
466 if (Subtarget->is64Bit()) {
467 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
468 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
469 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
470 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
471 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom);
473 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
474 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
475 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
476 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
477 if (Subtarget->is64Bit()) {
478 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
479 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
480 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
483 if (Subtarget->hasSSE1())
484 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
486 setOperationAction(ISD::MEMBARRIER , MVT::Other, Custom);
487 setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom);
489 // On X86 and X86-64, atomic operations are lowered to locked instructions.
490 // Locked instructions, in turn, have implicit fence semantics (all memory
491 // operations are flushed before issuing the locked instruction, and they
492 // are not buffered), so we can fold away the common pattern of
493 // fence-atomic-fence.
494 setShouldFoldAtomicFences(true);
496 // Expand certain atomics
497 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
499 setOperationAction(ISD::ATOMIC_CMP_SWAP, VT, Custom);
500 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom);
501 setOperationAction(ISD::ATOMIC_STORE, VT, Custom);
504 if (!Subtarget->is64Bit()) {
505 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Custom);
506 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i64, Custom);
507 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom);
508 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i64, Custom);
509 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i64, Custom);
510 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i64, Custom);
511 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i64, Custom);
512 setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Custom);
515 if (Subtarget->hasCmpxchg16b()) {
516 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i128, Custom);
519 // FIXME - use subtarget debug flags
520 if (!Subtarget->isTargetDarwin() &&
521 !Subtarget->isTargetELF() &&
522 !Subtarget->isTargetCygMing()) {
523 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
526 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand);
527 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand);
528 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
529 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
530 if (Subtarget->is64Bit()) {
531 setExceptionPointerRegister(X86::RAX);
532 setExceptionSelectorRegister(X86::RDX);
534 setExceptionPointerRegister(X86::EAX);
535 setExceptionSelectorRegister(X86::EDX);
537 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
538 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
540 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
541 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
543 setOperationAction(ISD::TRAP, MVT::Other, Legal);
545 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
546 setOperationAction(ISD::VASTART , MVT::Other, Custom);
547 setOperationAction(ISD::VAEND , MVT::Other, Expand);
548 if (Subtarget->is64Bit()) {
549 setOperationAction(ISD::VAARG , MVT::Other, Custom);
550 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
552 setOperationAction(ISD::VAARG , MVT::Other, Expand);
553 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
556 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
557 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
559 if (Subtarget->isTargetCOFF() && !Subtarget->isTargetEnvMacho())
560 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ?
561 MVT::i64 : MVT::i32, Custom);
562 else if (TM.Options.EnableSegmentedStacks)
563 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ?
564 MVT::i64 : MVT::i32, Custom);
566 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ?
567 MVT::i64 : MVT::i32, Expand);
569 if (!TM.Options.UseSoftFloat && X86ScalarSSEf64) {
570 // f32 and f64 use SSE.
571 // Set up the FP register classes.
572 addRegisterClass(MVT::f32, &X86::FR32RegClass);
573 addRegisterClass(MVT::f64, &X86::FR64RegClass);
575 // Use ANDPD to simulate FABS.
576 setOperationAction(ISD::FABS , MVT::f64, Custom);
577 setOperationAction(ISD::FABS , MVT::f32, Custom);
579 // Use XORP to simulate FNEG.
580 setOperationAction(ISD::FNEG , MVT::f64, Custom);
581 setOperationAction(ISD::FNEG , MVT::f32, Custom);
583 // Use ANDPD and ORPD to simulate FCOPYSIGN.
584 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
585 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
587 // Lower this to FGETSIGNx86 plus an AND.
588 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom);
589 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom);
591 // We don't support sin/cos/fmod
592 setOperationAction(ISD::FSIN , MVT::f64, Expand);
593 setOperationAction(ISD::FCOS , MVT::f64, Expand);
594 setOperationAction(ISD::FSIN , MVT::f32, Expand);
595 setOperationAction(ISD::FCOS , MVT::f32, Expand);
597 // Expand FP immediates into loads from the stack, except for the special
599 addLegalFPImmediate(APFloat(+0.0)); // xorpd
600 addLegalFPImmediate(APFloat(+0.0f)); // xorps
601 } else if (!TM.Options.UseSoftFloat && X86ScalarSSEf32) {
602 // Use SSE for f32, x87 for f64.
603 // Set up the FP register classes.
604 addRegisterClass(MVT::f32, &X86::FR32RegClass);
605 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
607 // Use ANDPS to simulate FABS.
608 setOperationAction(ISD::FABS , MVT::f32, Custom);
610 // Use XORP to simulate FNEG.
611 setOperationAction(ISD::FNEG , MVT::f32, Custom);
613 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
615 // Use ANDPS and ORPS to simulate FCOPYSIGN.
616 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
617 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
619 // We don't support sin/cos/fmod
620 setOperationAction(ISD::FSIN , MVT::f32, Expand);
621 setOperationAction(ISD::FCOS , MVT::f32, Expand);
623 // Special cases we handle for FP constants.
624 addLegalFPImmediate(APFloat(+0.0f)); // xorps
625 addLegalFPImmediate(APFloat(+0.0)); // FLD0
626 addLegalFPImmediate(APFloat(+1.0)); // FLD1
627 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
628 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
630 if (!TM.Options.UnsafeFPMath) {
631 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
632 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
634 } else if (!TM.Options.UseSoftFloat) {
635 // f32 and f64 in x87.
636 // Set up the FP register classes.
637 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
638 addRegisterClass(MVT::f32, &X86::RFP32RegClass);
640 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
641 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
642 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
643 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
645 if (!TM.Options.UnsafeFPMath) {
646 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
647 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
649 addLegalFPImmediate(APFloat(+0.0)); // FLD0
650 addLegalFPImmediate(APFloat(+1.0)); // FLD1
651 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
652 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
653 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
654 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
655 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
656 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
659 // We don't support FMA.
660 setOperationAction(ISD::FMA, MVT::f64, Expand);
661 setOperationAction(ISD::FMA, MVT::f32, Expand);
663 // Long double always uses X87.
664 if (!TM.Options.UseSoftFloat) {
665 addRegisterClass(MVT::f80, &X86::RFP80RegClass);
666 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
667 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
669 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended);
670 addLegalFPImmediate(TmpFlt); // FLD0
672 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
675 APFloat TmpFlt2(+1.0);
676 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
678 addLegalFPImmediate(TmpFlt2); // FLD1
679 TmpFlt2.changeSign();
680 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
683 if (!TM.Options.UnsafeFPMath) {
684 setOperationAction(ISD::FSIN , MVT::f80 , Expand);
685 setOperationAction(ISD::FCOS , MVT::f80 , Expand);
688 setOperationAction(ISD::FFLOOR, MVT::f80, Expand);
689 setOperationAction(ISD::FCEIL, MVT::f80, Expand);
690 setOperationAction(ISD::FTRUNC, MVT::f80, Expand);
691 setOperationAction(ISD::FRINT, MVT::f80, Expand);
692 setOperationAction(ISD::FNEARBYINT, MVT::f80, Expand);
693 setOperationAction(ISD::FMA, MVT::f80, Expand);
696 // Always use a library call for pow.
697 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
698 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
699 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
701 setOperationAction(ISD::FLOG, MVT::f80, Expand);
702 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
703 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
704 setOperationAction(ISD::FEXP, MVT::f80, Expand);
705 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
707 // First set operation action for all vector types to either promote
708 // (for widening) or expand (for scalarization). Then we will selectively
709 // turn on ones that can be effectively codegen'd.
710 for (int VT = MVT::FIRST_VECTOR_VALUETYPE;
711 VT <= MVT::LAST_VECTOR_VALUETYPE; ++VT) {
712 setOperationAction(ISD::ADD , (MVT::SimpleValueType)VT, Expand);
713 setOperationAction(ISD::SUB , (MVT::SimpleValueType)VT, Expand);
714 setOperationAction(ISD::FADD, (MVT::SimpleValueType)VT, Expand);
715 setOperationAction(ISD::FNEG, (MVT::SimpleValueType)VT, Expand);
716 setOperationAction(ISD::FSUB, (MVT::SimpleValueType)VT, Expand);
717 setOperationAction(ISD::MUL , (MVT::SimpleValueType)VT, Expand);
718 setOperationAction(ISD::FMUL, (MVT::SimpleValueType)VT, Expand);
719 setOperationAction(ISD::SDIV, (MVT::SimpleValueType)VT, Expand);
720 setOperationAction(ISD::UDIV, (MVT::SimpleValueType)VT, Expand);
721 setOperationAction(ISD::FDIV, (MVT::SimpleValueType)VT, Expand);
722 setOperationAction(ISD::SREM, (MVT::SimpleValueType)VT, Expand);
723 setOperationAction(ISD::UREM, (MVT::SimpleValueType)VT, Expand);
724 setOperationAction(ISD::LOAD, (MVT::SimpleValueType)VT, Expand);
725 setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::SimpleValueType)VT, Expand);
726 setOperationAction(ISD::EXTRACT_VECTOR_ELT,(MVT::SimpleValueType)VT,Expand);
727 setOperationAction(ISD::INSERT_VECTOR_ELT,(MVT::SimpleValueType)VT, Expand);
728 setOperationAction(ISD::EXTRACT_SUBVECTOR,(MVT::SimpleValueType)VT,Expand);
729 setOperationAction(ISD::INSERT_SUBVECTOR,(MVT::SimpleValueType)VT,Expand);
730 setOperationAction(ISD::FABS, (MVT::SimpleValueType)VT, Expand);
731 setOperationAction(ISD::FSIN, (MVT::SimpleValueType)VT, Expand);
732 setOperationAction(ISD::FCOS, (MVT::SimpleValueType)VT, Expand);
733 setOperationAction(ISD::FREM, (MVT::SimpleValueType)VT, Expand);
734 setOperationAction(ISD::FMA, (MVT::SimpleValueType)VT, Expand);
735 setOperationAction(ISD::FPOWI, (MVT::SimpleValueType)VT, Expand);
736 setOperationAction(ISD::FSQRT, (MVT::SimpleValueType)VT, Expand);
737 setOperationAction(ISD::FCOPYSIGN, (MVT::SimpleValueType)VT, Expand);
738 setOperationAction(ISD::SMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
739 setOperationAction(ISD::UMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
740 setOperationAction(ISD::SDIVREM, (MVT::SimpleValueType)VT, Expand);
741 setOperationAction(ISD::UDIVREM, (MVT::SimpleValueType)VT, Expand);
742 setOperationAction(ISD::FPOW, (MVT::SimpleValueType)VT, Expand);
743 setOperationAction(ISD::CTPOP, (MVT::SimpleValueType)VT, Expand);
744 setOperationAction(ISD::CTTZ, (MVT::SimpleValueType)VT, Expand);
745 setOperationAction(ISD::CTTZ_ZERO_UNDEF, (MVT::SimpleValueType)VT, Expand);
746 setOperationAction(ISD::CTLZ, (MVT::SimpleValueType)VT, Expand);
747 setOperationAction(ISD::CTLZ_ZERO_UNDEF, (MVT::SimpleValueType)VT, Expand);
748 setOperationAction(ISD::SHL, (MVT::SimpleValueType)VT, Expand);
749 setOperationAction(ISD::SRA, (MVT::SimpleValueType)VT, Expand);
750 setOperationAction(ISD::SRL, (MVT::SimpleValueType)VT, Expand);
751 setOperationAction(ISD::ROTL, (MVT::SimpleValueType)VT, Expand);
752 setOperationAction(ISD::ROTR, (MVT::SimpleValueType)VT, Expand);
753 setOperationAction(ISD::BSWAP, (MVT::SimpleValueType)VT, Expand);
754 setOperationAction(ISD::SETCC, (MVT::SimpleValueType)VT, Expand);
755 setOperationAction(ISD::FLOG, (MVT::SimpleValueType)VT, Expand);
756 setOperationAction(ISD::FLOG2, (MVT::SimpleValueType)VT, Expand);
757 setOperationAction(ISD::FLOG10, (MVT::SimpleValueType)VT, Expand);
758 setOperationAction(ISD::FEXP, (MVT::SimpleValueType)VT, Expand);
759 setOperationAction(ISD::FEXP2, (MVT::SimpleValueType)VT, Expand);
760 setOperationAction(ISD::FP_TO_UINT, (MVT::SimpleValueType)VT, Expand);
761 setOperationAction(ISD::FP_TO_SINT, (MVT::SimpleValueType)VT, Expand);
762 setOperationAction(ISD::UINT_TO_FP, (MVT::SimpleValueType)VT, Expand);
763 setOperationAction(ISD::SINT_TO_FP, (MVT::SimpleValueType)VT, Expand);
764 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,Expand);
765 setOperationAction(ISD::TRUNCATE, (MVT::SimpleValueType)VT, Expand);
766 setOperationAction(ISD::SIGN_EXTEND, (MVT::SimpleValueType)VT, Expand);
767 setOperationAction(ISD::ZERO_EXTEND, (MVT::SimpleValueType)VT, Expand);
768 setOperationAction(ISD::ANY_EXTEND, (MVT::SimpleValueType)VT, Expand);
769 setOperationAction(ISD::VSELECT, (MVT::SimpleValueType)VT, Expand);
770 for (int InnerVT = MVT::FIRST_VECTOR_VALUETYPE;
771 InnerVT <= MVT::LAST_VECTOR_VALUETYPE; ++InnerVT)
772 setTruncStoreAction((MVT::SimpleValueType)VT,
773 (MVT::SimpleValueType)InnerVT, Expand);
774 setLoadExtAction(ISD::SEXTLOAD, (MVT::SimpleValueType)VT, Expand);
775 setLoadExtAction(ISD::ZEXTLOAD, (MVT::SimpleValueType)VT, Expand);
776 setLoadExtAction(ISD::EXTLOAD, (MVT::SimpleValueType)VT, Expand);
779 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
780 // with -msoft-float, disable use of MMX as well.
781 if (!TM.Options.UseSoftFloat && Subtarget->hasMMX()) {
782 addRegisterClass(MVT::x86mmx, &X86::VR64RegClass);
783 // No operations on x86mmx supported, everything uses intrinsics.
786 // MMX-sized vectors (other than x86mmx) are expected to be expanded
787 // into smaller operations.
788 setOperationAction(ISD::MULHS, MVT::v8i8, Expand);
789 setOperationAction(ISD::MULHS, MVT::v4i16, Expand);
790 setOperationAction(ISD::MULHS, MVT::v2i32, Expand);
791 setOperationAction(ISD::MULHS, MVT::v1i64, Expand);
792 setOperationAction(ISD::AND, MVT::v8i8, Expand);
793 setOperationAction(ISD::AND, MVT::v4i16, Expand);
794 setOperationAction(ISD::AND, MVT::v2i32, Expand);
795 setOperationAction(ISD::AND, MVT::v1i64, Expand);
796 setOperationAction(ISD::OR, MVT::v8i8, Expand);
797 setOperationAction(ISD::OR, MVT::v4i16, Expand);
798 setOperationAction(ISD::OR, MVT::v2i32, Expand);
799 setOperationAction(ISD::OR, MVT::v1i64, Expand);
800 setOperationAction(ISD::XOR, MVT::v8i8, Expand);
801 setOperationAction(ISD::XOR, MVT::v4i16, Expand);
802 setOperationAction(ISD::XOR, MVT::v2i32, Expand);
803 setOperationAction(ISD::XOR, MVT::v1i64, Expand);
804 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Expand);
805 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Expand);
806 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i32, Expand);
807 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Expand);
808 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand);
809 setOperationAction(ISD::SELECT, MVT::v8i8, Expand);
810 setOperationAction(ISD::SELECT, MVT::v4i16, Expand);
811 setOperationAction(ISD::SELECT, MVT::v2i32, Expand);
812 setOperationAction(ISD::SELECT, MVT::v1i64, Expand);
813 setOperationAction(ISD::BITCAST, MVT::v8i8, Expand);
814 setOperationAction(ISD::BITCAST, MVT::v4i16, Expand);
815 setOperationAction(ISD::BITCAST, MVT::v2i32, Expand);
816 setOperationAction(ISD::BITCAST, MVT::v1i64, Expand);
818 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE1()) {
819 addRegisterClass(MVT::v4f32, &X86::VR128RegClass);
821 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
822 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
823 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
824 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
825 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
826 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
827 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
828 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
829 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
830 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
831 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
834 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE2()) {
835 addRegisterClass(MVT::v2f64, &X86::VR128RegClass);
837 // FIXME: Unfortunately -soft-float and -no-implicit-float means XMM
838 // registers cannot be used even for integer operations.
839 addRegisterClass(MVT::v16i8, &X86::VR128RegClass);
840 addRegisterClass(MVT::v8i16, &X86::VR128RegClass);
841 addRegisterClass(MVT::v4i32, &X86::VR128RegClass);
842 addRegisterClass(MVT::v2i64, &X86::VR128RegClass);
844 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
845 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
846 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
847 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
848 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
849 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
850 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
851 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
852 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
853 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
854 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
855 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
856 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
857 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
858 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
859 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
861 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
862 setOperationAction(ISD::SETCC, MVT::v16i8, Custom);
863 setOperationAction(ISD::SETCC, MVT::v8i16, Custom);
864 setOperationAction(ISD::SETCC, MVT::v4i32, Custom);
866 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
867 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
868 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
869 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
870 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
872 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
873 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
874 MVT VT = (MVT::SimpleValueType)i;
875 // Do not attempt to custom lower non-power-of-2 vectors
876 if (!isPowerOf2_32(VT.getVectorNumElements()))
878 // Do not attempt to custom lower non-128-bit vectors
879 if (!VT.is128BitVector())
881 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
882 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
883 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
886 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
887 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
888 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
889 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
890 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
891 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
893 if (Subtarget->is64Bit()) {
894 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
895 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
898 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
899 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
900 MVT VT = (MVT::SimpleValueType)i;
902 // Do not attempt to promote non-128-bit vectors
903 if (!VT.is128BitVector())
906 setOperationAction(ISD::AND, VT, Promote);
907 AddPromotedToType (ISD::AND, VT, MVT::v2i64);
908 setOperationAction(ISD::OR, VT, Promote);
909 AddPromotedToType (ISD::OR, VT, MVT::v2i64);
910 setOperationAction(ISD::XOR, VT, Promote);
911 AddPromotedToType (ISD::XOR, VT, MVT::v2i64);
912 setOperationAction(ISD::LOAD, VT, Promote);
913 AddPromotedToType (ISD::LOAD, VT, MVT::v2i64);
914 setOperationAction(ISD::SELECT, VT, Promote);
915 AddPromotedToType (ISD::SELECT, VT, MVT::v2i64);
918 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
920 // Custom lower v2i64 and v2f64 selects.
921 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
922 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
923 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
924 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
926 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
927 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
930 if (Subtarget->hasSSE41()) {
931 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
932 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
933 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
934 setOperationAction(ISD::FRINT, MVT::f32, Legal);
935 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
936 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
937 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
938 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
939 setOperationAction(ISD::FRINT, MVT::f64, Legal);
940 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
942 // FIXME: Do we need to handle scalar-to-vector here?
943 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
945 setOperationAction(ISD::VSELECT, MVT::v2f64, Legal);
946 setOperationAction(ISD::VSELECT, MVT::v2i64, Legal);
947 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
948 setOperationAction(ISD::VSELECT, MVT::v4i32, Legal);
949 setOperationAction(ISD::VSELECT, MVT::v4f32, Legal);
951 // i8 and i16 vectors are custom , because the source register and source
952 // source memory operand types are not the same width. f32 vectors are
953 // custom since the immediate controlling the insert encodes additional
955 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
956 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
957 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
958 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
960 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
961 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
962 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
963 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
965 // FIXME: these should be Legal but thats only for the case where
966 // the index is constant. For now custom expand to deal with that.
967 if (Subtarget->is64Bit()) {
968 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
969 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
973 if (Subtarget->hasSSE2()) {
974 setOperationAction(ISD::SRL, MVT::v8i16, Custom);
975 setOperationAction(ISD::SRL, MVT::v16i8, Custom);
977 setOperationAction(ISD::SHL, MVT::v8i16, Custom);
978 setOperationAction(ISD::SHL, MVT::v16i8, Custom);
980 setOperationAction(ISD::SRA, MVT::v8i16, Custom);
981 setOperationAction(ISD::SRA, MVT::v16i8, Custom);
983 if (Subtarget->hasAVX2()) {
984 setOperationAction(ISD::SRL, MVT::v2i64, Legal);
985 setOperationAction(ISD::SRL, MVT::v4i32, Legal);
987 setOperationAction(ISD::SHL, MVT::v2i64, Legal);
988 setOperationAction(ISD::SHL, MVT::v4i32, Legal);
990 setOperationAction(ISD::SRA, MVT::v4i32, Legal);
992 setOperationAction(ISD::SRL, MVT::v2i64, Custom);
993 setOperationAction(ISD::SRL, MVT::v4i32, Custom);
995 setOperationAction(ISD::SHL, MVT::v2i64, Custom);
996 setOperationAction(ISD::SHL, MVT::v4i32, Custom);
998 setOperationAction(ISD::SRA, MVT::v4i32, Custom);
1002 if (!TM.Options.UseSoftFloat && Subtarget->hasAVX()) {
1003 addRegisterClass(MVT::v32i8, &X86::VR256RegClass);
1004 addRegisterClass(MVT::v16i16, &X86::VR256RegClass);
1005 addRegisterClass(MVT::v8i32, &X86::VR256RegClass);
1006 addRegisterClass(MVT::v8f32, &X86::VR256RegClass);
1007 addRegisterClass(MVT::v4i64, &X86::VR256RegClass);
1008 addRegisterClass(MVT::v4f64, &X86::VR256RegClass);
1010 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
1011 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
1012 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
1014 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
1015 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
1016 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
1017 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
1018 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
1019 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
1021 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
1022 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
1023 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
1024 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
1025 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
1026 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
1028 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
1029 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
1030 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal);
1032 setOperationAction(ISD::SRL, MVT::v16i16, Custom);
1033 setOperationAction(ISD::SRL, MVT::v32i8, Custom);
1035 setOperationAction(ISD::SHL, MVT::v16i16, Custom);
1036 setOperationAction(ISD::SHL, MVT::v32i8, Custom);
1038 setOperationAction(ISD::SRA, MVT::v16i16, Custom);
1039 setOperationAction(ISD::SRA, MVT::v32i8, Custom);
1041 setOperationAction(ISD::SETCC, MVT::v32i8, Custom);
1042 setOperationAction(ISD::SETCC, MVT::v16i16, Custom);
1043 setOperationAction(ISD::SETCC, MVT::v8i32, Custom);
1044 setOperationAction(ISD::SETCC, MVT::v4i64, Custom);
1046 setOperationAction(ISD::SELECT, MVT::v4f64, Custom);
1047 setOperationAction(ISD::SELECT, MVT::v4i64, Custom);
1048 setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
1050 setOperationAction(ISD::VSELECT, MVT::v4f64, Legal);
1051 setOperationAction(ISD::VSELECT, MVT::v4i64, Legal);
1052 setOperationAction(ISD::VSELECT, MVT::v8i32, Legal);
1053 setOperationAction(ISD::VSELECT, MVT::v8f32, Legal);
1055 if (Subtarget->hasFMA()) {
1056 setOperationAction(ISD::FMA, MVT::v8f32, Custom);
1057 setOperationAction(ISD::FMA, MVT::v4f64, Custom);
1058 setOperationAction(ISD::FMA, MVT::v4f32, Custom);
1059 setOperationAction(ISD::FMA, MVT::v2f64, Custom);
1060 setOperationAction(ISD::FMA, MVT::f32, Custom);
1061 setOperationAction(ISD::FMA, MVT::f64, Custom);
1064 if (Subtarget->hasAVX2()) {
1065 setOperationAction(ISD::ADD, MVT::v4i64, Legal);
1066 setOperationAction(ISD::ADD, MVT::v8i32, Legal);
1067 setOperationAction(ISD::ADD, MVT::v16i16, Legal);
1068 setOperationAction(ISD::ADD, MVT::v32i8, Legal);
1070 setOperationAction(ISD::SUB, MVT::v4i64, Legal);
1071 setOperationAction(ISD::SUB, MVT::v8i32, Legal);
1072 setOperationAction(ISD::SUB, MVT::v16i16, Legal);
1073 setOperationAction(ISD::SUB, MVT::v32i8, Legal);
1075 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1076 setOperationAction(ISD::MUL, MVT::v8i32, Legal);
1077 setOperationAction(ISD::MUL, MVT::v16i16, Legal);
1078 // Don't lower v32i8 because there is no 128-bit byte mul
1080 setOperationAction(ISD::VSELECT, MVT::v32i8, Legal);
1082 setOperationAction(ISD::SRL, MVT::v4i64, Legal);
1083 setOperationAction(ISD::SRL, MVT::v8i32, Legal);
1085 setOperationAction(ISD::SHL, MVT::v4i64, Legal);
1086 setOperationAction(ISD::SHL, MVT::v8i32, Legal);
1088 setOperationAction(ISD::SRA, MVT::v8i32, Legal);
1090 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
1091 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
1092 setOperationAction(ISD::ADD, MVT::v16i16, Custom);
1093 setOperationAction(ISD::ADD, MVT::v32i8, Custom);
1095 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
1096 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
1097 setOperationAction(ISD::SUB, MVT::v16i16, Custom);
1098 setOperationAction(ISD::SUB, MVT::v32i8, Custom);
1100 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1101 setOperationAction(ISD::MUL, MVT::v8i32, Custom);
1102 setOperationAction(ISD::MUL, MVT::v16i16, Custom);
1103 // Don't lower v32i8 because there is no 128-bit byte mul
1105 setOperationAction(ISD::SRL, MVT::v4i64, Custom);
1106 setOperationAction(ISD::SRL, MVT::v8i32, Custom);
1108 setOperationAction(ISD::SHL, MVT::v4i64, Custom);
1109 setOperationAction(ISD::SHL, MVT::v8i32, Custom);
1111 setOperationAction(ISD::SRA, MVT::v8i32, Custom);
1114 // Custom lower several nodes for 256-bit types.
1115 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
1116 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
1117 MVT VT = (MVT::SimpleValueType)i;
1119 // Extract subvector is special because the value type
1120 // (result) is 128-bit but the source is 256-bit wide.
1121 if (VT.is128BitVector())
1122 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1124 // Do not attempt to custom lower other non-256-bit vectors
1125 if (!VT.is256BitVector())
1128 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1129 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1130 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1131 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1132 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1133 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1134 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom);
1137 // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64.
1138 for (int i = MVT::v32i8; i != MVT::v4i64; ++i) {
1139 MVT VT = (MVT::SimpleValueType)i;
1141 // Do not attempt to promote non-256-bit vectors
1142 if (!VT.is256BitVector())
1145 setOperationAction(ISD::AND, VT, Promote);
1146 AddPromotedToType (ISD::AND, VT, MVT::v4i64);
1147 setOperationAction(ISD::OR, VT, Promote);
1148 AddPromotedToType (ISD::OR, VT, MVT::v4i64);
1149 setOperationAction(ISD::XOR, VT, Promote);
1150 AddPromotedToType (ISD::XOR, VT, MVT::v4i64);
1151 setOperationAction(ISD::LOAD, VT, Promote);
1152 AddPromotedToType (ISD::LOAD, VT, MVT::v4i64);
1153 setOperationAction(ISD::SELECT, VT, Promote);
1154 AddPromotedToType (ISD::SELECT, VT, MVT::v4i64);
1158 // SIGN_EXTEND_INREGs are evaluated by the extend type. Handle the expansion
1159 // of this type with custom code.
1160 for (int VT = MVT::FIRST_VECTOR_VALUETYPE;
1161 VT != MVT::LAST_VECTOR_VALUETYPE; VT++) {
1162 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,
1166 // We want to custom lower some of our intrinsics.
1167 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
1168 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
1171 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't
1172 // handle type legalization for these operations here.
1174 // FIXME: We really should do custom legalization for addition and
1175 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better
1176 // than generic legalization for 64-bit multiplication-with-overflow, though.
1177 for (unsigned i = 0, e = 3+Subtarget->is64Bit(); i != e; ++i) {
1178 // Add/Sub/Mul with overflow operations are custom lowered.
1180 setOperationAction(ISD::SADDO, VT, Custom);
1181 setOperationAction(ISD::UADDO, VT, Custom);
1182 setOperationAction(ISD::SSUBO, VT, Custom);
1183 setOperationAction(ISD::USUBO, VT, Custom);
1184 setOperationAction(ISD::SMULO, VT, Custom);
1185 setOperationAction(ISD::UMULO, VT, Custom);
1188 // There are no 8-bit 3-address imul/mul instructions
1189 setOperationAction(ISD::SMULO, MVT::i8, Expand);
1190 setOperationAction(ISD::UMULO, MVT::i8, Expand);
1192 if (!Subtarget->is64Bit()) {
1193 // These libcalls are not available in 32-bit.
1194 setLibcallName(RTLIB::SHL_I128, 0);
1195 setLibcallName(RTLIB::SRL_I128, 0);
1196 setLibcallName(RTLIB::SRA_I128, 0);
1199 // We have target-specific dag combine patterns for the following nodes:
1200 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
1201 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
1202 setTargetDAGCombine(ISD::VSELECT);
1203 setTargetDAGCombine(ISD::SELECT);
1204 setTargetDAGCombine(ISD::SHL);
1205 setTargetDAGCombine(ISD::SRA);
1206 setTargetDAGCombine(ISD::SRL);
1207 setTargetDAGCombine(ISD::OR);
1208 setTargetDAGCombine(ISD::AND);
1209 setTargetDAGCombine(ISD::ADD);
1210 setTargetDAGCombine(ISD::FADD);
1211 setTargetDAGCombine(ISD::FSUB);
1212 setTargetDAGCombine(ISD::FMA);
1213 setTargetDAGCombine(ISD::SUB);
1214 setTargetDAGCombine(ISD::LOAD);
1215 setTargetDAGCombine(ISD::STORE);
1216 setTargetDAGCombine(ISD::ZERO_EXTEND);
1217 setTargetDAGCombine(ISD::ANY_EXTEND);
1218 setTargetDAGCombine(ISD::SIGN_EXTEND);
1219 setTargetDAGCombine(ISD::TRUNCATE);
1220 setTargetDAGCombine(ISD::UINT_TO_FP);
1221 setTargetDAGCombine(ISD::SINT_TO_FP);
1222 setTargetDAGCombine(ISD::SETCC);
1223 setTargetDAGCombine(ISD::FP_TO_SINT);
1224 if (Subtarget->is64Bit())
1225 setTargetDAGCombine(ISD::MUL);
1226 setTargetDAGCombine(ISD::XOR);
1228 computeRegisterProperties();
1230 // On Darwin, -Os means optimize for size without hurting performance,
1231 // do not reduce the limit.
1232 maxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
1233 maxStoresPerMemsetOptSize = Subtarget->isTargetDarwin() ? 16 : 8;
1234 maxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores
1235 maxStoresPerMemcpyOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1236 maxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores
1237 maxStoresPerMemmoveOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1238 setPrefLoopAlignment(4); // 2^4 bytes.
1239 benefitFromCodePlacementOpt = true;
1241 // Predictable cmov don't hurt on atom because it's in-order.
1242 predictableSelectIsExpensive = !Subtarget->isAtom();
1244 setPrefFunctionAlignment(4); // 2^4 bytes.
1248 EVT X86TargetLowering::getSetCCResultType(EVT VT) const {
1249 if (!VT.isVector()) return MVT::i8;
1250 return VT.changeVectorElementTypeToInteger();
1254 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
1255 /// the desired ByVal argument alignment.
1256 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) {
1259 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1260 if (VTy->getBitWidth() == 128)
1262 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1263 unsigned EltAlign = 0;
1264 getMaxByValAlign(ATy->getElementType(), EltAlign);
1265 if (EltAlign > MaxAlign)
1266 MaxAlign = EltAlign;
1267 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
1268 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
1269 unsigned EltAlign = 0;
1270 getMaxByValAlign(STy->getElementType(i), EltAlign);
1271 if (EltAlign > MaxAlign)
1272 MaxAlign = EltAlign;
1279 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1280 /// function arguments in the caller parameter area. For X86, aggregates
1281 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
1282 /// are at 4-byte boundaries.
1283 unsigned X86TargetLowering::getByValTypeAlignment(Type *Ty) const {
1284 if (Subtarget->is64Bit()) {
1285 // Max of 8 and alignment of type.
1286 unsigned TyAlign = TD->getABITypeAlignment(Ty);
1293 if (Subtarget->hasSSE1())
1294 getMaxByValAlign(Ty, Align);
1298 /// getOptimalMemOpType - Returns the target specific optimal type for load
1299 /// and store operations as a result of memset, memcpy, and memmove
1300 /// lowering. If DstAlign is zero that means it's safe to destination
1301 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
1302 /// means there isn't a need to check it against alignment requirement,
1303 /// probably because the source does not need to be loaded. If
1304 /// 'IsZeroVal' is true, that means it's safe to return a
1305 /// non-scalar-integer type, e.g. empty string source, constant, or loaded
1306 /// from memory. 'MemcpyStrSrc' indicates whether the memcpy source is
1307 /// constant so it does not need to be loaded.
1308 /// It returns EVT::Other if the type should be determined using generic
1309 /// target-independent logic.
1311 X86TargetLowering::getOptimalMemOpType(uint64_t Size,
1312 unsigned DstAlign, unsigned SrcAlign,
1315 MachineFunction &MF) const {
1316 // FIXME: This turns off use of xmm stores for memset/memcpy on targets like
1317 // linux. This is because the stack realignment code can't handle certain
1318 // cases like PR2962. This should be removed when PR2962 is fixed.
1319 const Function *F = MF.getFunction();
1321 !F->hasFnAttr(Attribute::NoImplicitFloat)) {
1323 (Subtarget->isUnalignedMemAccessFast() ||
1324 ((DstAlign == 0 || DstAlign >= 16) &&
1325 (SrcAlign == 0 || SrcAlign >= 16))) &&
1326 Subtarget->getStackAlignment() >= 16) {
1327 if (Subtarget->getStackAlignment() >= 32) {
1328 if (Subtarget->hasAVX2())
1330 if (Subtarget->hasAVX())
1333 if (Subtarget->hasSSE2())
1335 if (Subtarget->hasSSE1())
1337 } else if (!MemcpyStrSrc && Size >= 8 &&
1338 !Subtarget->is64Bit() &&
1339 Subtarget->getStackAlignment() >= 8 &&
1340 Subtarget->hasSSE2()) {
1341 // Do not use f64 to lower memcpy if source is string constant. It's
1342 // better to use i32 to avoid the loads.
1346 if (Subtarget->is64Bit() && Size >= 8)
1351 /// getJumpTableEncoding - Return the entry encoding for a jump table in the
1352 /// current function. The returned value is a member of the
1353 /// MachineJumpTableInfo::JTEntryKind enum.
1354 unsigned X86TargetLowering::getJumpTableEncoding() const {
1355 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
1357 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1358 Subtarget->isPICStyleGOT())
1359 return MachineJumpTableInfo::EK_Custom32;
1361 // Otherwise, use the normal jump table encoding heuristics.
1362 return TargetLowering::getJumpTableEncoding();
1366 X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
1367 const MachineBasicBlock *MBB,
1368 unsigned uid,MCContext &Ctx) const{
1369 assert(getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1370 Subtarget->isPICStyleGOT());
1371 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
1373 return MCSymbolRefExpr::Create(MBB->getSymbol(),
1374 MCSymbolRefExpr::VK_GOTOFF, Ctx);
1377 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
1379 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
1380 SelectionDAG &DAG) const {
1381 if (!Subtarget->is64Bit())
1382 // This doesn't have DebugLoc associated with it, but is not really the
1383 // same as a Register.
1384 return DAG.getNode(X86ISD::GlobalBaseReg, DebugLoc(), getPointerTy());
1388 /// getPICJumpTableRelocBaseExpr - This returns the relocation base for the
1389 /// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an
1391 const MCExpr *X86TargetLowering::
1392 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
1393 MCContext &Ctx) const {
1394 // X86-64 uses RIP relative addressing based on the jump table label.
1395 if (Subtarget->isPICStyleRIPRel())
1396 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
1398 // Otherwise, the reference is relative to the PIC base.
1399 return MCSymbolRefExpr::Create(MF->getPICBaseSymbol(), Ctx);
1402 // FIXME: Why this routine is here? Move to RegInfo!
1403 std::pair<const TargetRegisterClass*, uint8_t>
1404 X86TargetLowering::findRepresentativeClass(EVT VT) const{
1405 const TargetRegisterClass *RRC = 0;
1407 switch (VT.getSimpleVT().SimpleTy) {
1409 return TargetLowering::findRepresentativeClass(VT);
1410 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
1411 RRC = Subtarget->is64Bit() ?
1412 (const TargetRegisterClass*)&X86::GR64RegClass :
1413 (const TargetRegisterClass*)&X86::GR32RegClass;
1416 RRC = &X86::VR64RegClass;
1418 case MVT::f32: case MVT::f64:
1419 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
1420 case MVT::v4f32: case MVT::v2f64:
1421 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32:
1423 RRC = &X86::VR128RegClass;
1426 return std::make_pair(RRC, Cost);
1429 bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace,
1430 unsigned &Offset) const {
1431 if (!Subtarget->isTargetLinux())
1434 if (Subtarget->is64Bit()) {
1435 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs:
1437 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
1450 //===----------------------------------------------------------------------===//
1451 // Return Value Calling Convention Implementation
1452 //===----------------------------------------------------------------------===//
1454 #include "X86GenCallingConv.inc"
1457 X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv,
1458 MachineFunction &MF, bool isVarArg,
1459 const SmallVectorImpl<ISD::OutputArg> &Outs,
1460 LLVMContext &Context) const {
1461 SmallVector<CCValAssign, 16> RVLocs;
1462 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
1464 return CCInfo.CheckReturn(Outs, RetCC_X86);
1468 X86TargetLowering::LowerReturn(SDValue Chain,
1469 CallingConv::ID CallConv, bool isVarArg,
1470 const SmallVectorImpl<ISD::OutputArg> &Outs,
1471 const SmallVectorImpl<SDValue> &OutVals,
1472 DebugLoc dl, SelectionDAG &DAG) const {
1473 MachineFunction &MF = DAG.getMachineFunction();
1474 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1476 SmallVector<CCValAssign, 16> RVLocs;
1477 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
1478 RVLocs, *DAG.getContext());
1479 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
1481 // Add the regs to the liveout set for the function.
1482 MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
1483 for (unsigned i = 0; i != RVLocs.size(); ++i)
1484 if (RVLocs[i].isRegLoc() && !MRI.isLiveOut(RVLocs[i].getLocReg()))
1485 MRI.addLiveOut(RVLocs[i].getLocReg());
1489 SmallVector<SDValue, 6> RetOps;
1490 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
1491 // Operand #1 = Bytes To Pop
1492 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(),
1495 // Copy the result values into the output registers.
1496 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1497 CCValAssign &VA = RVLocs[i];
1498 assert(VA.isRegLoc() && "Can only return in registers!");
1499 SDValue ValToCopy = OutVals[i];
1500 EVT ValVT = ValToCopy.getValueType();
1502 // Promote values to the appropriate types
1503 if (VA.getLocInfo() == CCValAssign::SExt)
1504 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy);
1505 else if (VA.getLocInfo() == CCValAssign::ZExt)
1506 ValToCopy = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ValToCopy);
1507 else if (VA.getLocInfo() == CCValAssign::AExt)
1508 ValToCopy = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ValToCopy);
1509 else if (VA.getLocInfo() == CCValAssign::BCvt)
1510 ValToCopy = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), ValToCopy);
1512 // If this is x86-64, and we disabled SSE, we can't return FP values,
1513 // or SSE or MMX vectors.
1514 if ((ValVT == MVT::f32 || ValVT == MVT::f64 ||
1515 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) &&
1516 (Subtarget->is64Bit() && !Subtarget->hasSSE1())) {
1517 report_fatal_error("SSE register return with SSE disabled");
1519 // Likewise we can't return F64 values with SSE1 only. gcc does so, but
1520 // llvm-gcc has never done it right and no one has noticed, so this
1521 // should be OK for now.
1522 if (ValVT == MVT::f64 &&
1523 (Subtarget->is64Bit() && !Subtarget->hasSSE2()))
1524 report_fatal_error("SSE2 register return with SSE2 disabled");
1526 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
1527 // the RET instruction and handled by the FP Stackifier.
1528 if (VA.getLocReg() == X86::ST0 ||
1529 VA.getLocReg() == X86::ST1) {
1530 // If this is a copy from an xmm register to ST(0), use an FPExtend to
1531 // change the value to the FP stack register class.
1532 if (isScalarFPTypeInSSEReg(VA.getValVT()))
1533 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
1534 RetOps.push_back(ValToCopy);
1535 // Don't emit a copytoreg.
1539 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
1540 // which is returned in RAX / RDX.
1541 if (Subtarget->is64Bit()) {
1542 if (ValVT == MVT::x86mmx) {
1543 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
1544 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ValToCopy);
1545 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
1547 // If we don't have SSE2 available, convert to v4f32 so the generated
1548 // register is legal.
1549 if (!Subtarget->hasSSE2())
1550 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32,ValToCopy);
1555 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
1556 Flag = Chain.getValue(1);
1559 // The x86-64 ABI for returning structs by value requires that we copy
1560 // the sret argument into %rax for the return. We saved the argument into
1561 // a virtual register in the entry block, so now we copy the value out
1563 if (Subtarget->is64Bit() &&
1564 DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
1565 MachineFunction &MF = DAG.getMachineFunction();
1566 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1567 unsigned Reg = FuncInfo->getSRetReturnReg();
1569 "SRetReturnReg should have been set in LowerFormalArguments().");
1570 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
1572 Chain = DAG.getCopyToReg(Chain, dl, X86::RAX, Val, Flag);
1573 Flag = Chain.getValue(1);
1575 // RAX now acts like a return value.
1576 MRI.addLiveOut(X86::RAX);
1579 RetOps[0] = Chain; // Update chain.
1581 // Add the flag if we have it.
1583 RetOps.push_back(Flag);
1585 return DAG.getNode(X86ISD::RET_FLAG, dl,
1586 MVT::Other, &RetOps[0], RetOps.size());
1589 bool X86TargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
1590 if (N->getNumValues() != 1)
1592 if (!N->hasNUsesOfValue(1, 0))
1595 SDValue TCChain = Chain;
1596 SDNode *Copy = *N->use_begin();
1597 if (Copy->getOpcode() == ISD::CopyToReg) {
1598 // If the copy has a glue operand, we conservatively assume it isn't safe to
1599 // perform a tail call.
1600 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
1602 TCChain = Copy->getOperand(0);
1603 } else if (Copy->getOpcode() != ISD::FP_EXTEND)
1606 bool HasRet = false;
1607 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
1609 if (UI->getOpcode() != X86ISD::RET_FLAG)
1622 X86TargetLowering::getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT,
1623 ISD::NodeType ExtendKind) const {
1625 // TODO: Is this also valid on 32-bit?
1626 if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND)
1627 ReturnMVT = MVT::i8;
1629 ReturnMVT = MVT::i32;
1631 EVT MinVT = getRegisterType(Context, ReturnMVT);
1632 return VT.bitsLT(MinVT) ? MinVT : VT;
1635 /// LowerCallResult - Lower the result values of a call into the
1636 /// appropriate copies out of appropriate physical registers.
1639 X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
1640 CallingConv::ID CallConv, bool isVarArg,
1641 const SmallVectorImpl<ISD::InputArg> &Ins,
1642 DebugLoc dl, SelectionDAG &DAG,
1643 SmallVectorImpl<SDValue> &InVals) const {
1645 // Assign locations to each value returned by this call.
1646 SmallVector<CCValAssign, 16> RVLocs;
1647 bool Is64Bit = Subtarget->is64Bit();
1648 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
1649 getTargetMachine(), RVLocs, *DAG.getContext());
1650 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
1652 // Copy all of the result registers out of their specified physreg.
1653 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1654 CCValAssign &VA = RVLocs[i];
1655 EVT CopyVT = VA.getValVT();
1657 // If this is x86-64, and we disabled SSE, we can't return FP values
1658 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
1659 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) {
1660 report_fatal_error("SSE register return with SSE disabled");
1665 // If this is a call to a function that returns an fp value on the floating
1666 // point stack, we must guarantee the value is popped from the stack, so
1667 // a CopyFromReg is not good enough - the copy instruction may be eliminated
1668 // if the return value is not used. We use the FpPOP_RETVAL instruction
1670 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1) {
1671 // If we prefer to use the value in xmm registers, copy it out as f80 and
1672 // use a truncate to move it from fp stack reg to xmm reg.
1673 if (isScalarFPTypeInSSEReg(VA.getValVT())) CopyVT = MVT::f80;
1674 SDValue Ops[] = { Chain, InFlag };
1675 Chain = SDValue(DAG.getMachineNode(X86::FpPOP_RETVAL, dl, CopyVT,
1676 MVT::Other, MVT::Glue, Ops, 2), 1);
1677 Val = Chain.getValue(0);
1679 // Round the f80 to the right size, which also moves it to the appropriate
1681 if (CopyVT != VA.getValVT())
1682 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
1683 // This truncation won't change the value.
1684 DAG.getIntPtrConstant(1));
1686 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
1687 CopyVT, InFlag).getValue(1);
1688 Val = Chain.getValue(0);
1690 InFlag = Chain.getValue(2);
1691 InVals.push_back(Val);
1698 //===----------------------------------------------------------------------===//
1699 // C & StdCall & Fast Calling Convention implementation
1700 //===----------------------------------------------------------------------===//
1701 // StdCall calling convention seems to be standard for many Windows' API
1702 // routines and around. It differs from C calling convention just a little:
1703 // callee should clean up the stack, not caller. Symbols should be also
1704 // decorated in some fancy way :) It doesn't support any vector arguments.
1705 // For info on fast calling convention see Fast Calling Convention (tail call)
1706 // implementation LowerX86_32FastCCCallTo.
1708 /// CallIsStructReturn - Determines whether a call uses struct return
1710 enum StructReturnType {
1715 static StructReturnType
1716 callIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
1718 return NotStructReturn;
1720 const ISD::ArgFlagsTy &Flags = Outs[0].Flags;
1721 if (!Flags.isSRet())
1722 return NotStructReturn;
1723 if (Flags.isInReg())
1724 return RegStructReturn;
1725 return StackStructReturn;
1728 /// ArgsAreStructReturn - Determines whether a function uses struct
1729 /// return semantics.
1730 static StructReturnType
1731 argsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
1733 return NotStructReturn;
1735 const ISD::ArgFlagsTy &Flags = Ins[0].Flags;
1736 if (!Flags.isSRet())
1737 return NotStructReturn;
1738 if (Flags.isInReg())
1739 return RegStructReturn;
1740 return StackStructReturn;
1743 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
1744 /// by "Src" to address "Dst" with size and alignment information specified by
1745 /// the specific parameter attribute. The copy will be passed as a byval
1746 /// function parameter.
1748 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
1749 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
1751 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
1753 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
1754 /*isVolatile*/false, /*AlwaysInline=*/true,
1755 MachinePointerInfo(), MachinePointerInfo());
1758 /// IsTailCallConvention - Return true if the calling convention is one that
1759 /// supports tail call optimization.
1760 static bool IsTailCallConvention(CallingConv::ID CC) {
1761 return (CC == CallingConv::Fast || CC == CallingConv::GHC);
1764 bool X86TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
1765 if (!CI->isTailCall() || getTargetMachine().Options.DisableTailCalls)
1769 CallingConv::ID CalleeCC = CS.getCallingConv();
1770 if (!IsTailCallConvention(CalleeCC) && CalleeCC != CallingConv::C)
1776 /// FuncIsMadeTailCallSafe - Return true if the function is being made into
1777 /// a tailcall target by changing its ABI.
1778 static bool FuncIsMadeTailCallSafe(CallingConv::ID CC,
1779 bool GuaranteedTailCallOpt) {
1780 return GuaranteedTailCallOpt && IsTailCallConvention(CC);
1784 X86TargetLowering::LowerMemArgument(SDValue Chain,
1785 CallingConv::ID CallConv,
1786 const SmallVectorImpl<ISD::InputArg> &Ins,
1787 DebugLoc dl, SelectionDAG &DAG,
1788 const CCValAssign &VA,
1789 MachineFrameInfo *MFI,
1791 // Create the nodes corresponding to a load from this parameter slot.
1792 ISD::ArgFlagsTy Flags = Ins[i].Flags;
1793 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(CallConv,
1794 getTargetMachine().Options.GuaranteedTailCallOpt);
1795 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
1798 // If value is passed by pointer we have address passed instead of the value
1800 if (VA.getLocInfo() == CCValAssign::Indirect)
1801 ValVT = VA.getLocVT();
1803 ValVT = VA.getValVT();
1805 // FIXME: For now, all byval parameter objects are marked mutable. This can be
1806 // changed with more analysis.
1807 // In case of tail call optimization mark all arguments mutable. Since they
1808 // could be overwritten by lowering of arguments in case of a tail call.
1809 if (Flags.isByVal()) {
1810 unsigned Bytes = Flags.getByValSize();
1811 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects.
1812 int FI = MFI->CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable);
1813 return DAG.getFrameIndex(FI, getPointerTy());
1815 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
1816 VA.getLocMemOffset(), isImmutable);
1817 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
1818 return DAG.getLoad(ValVT, dl, Chain, FIN,
1819 MachinePointerInfo::getFixedStack(FI),
1820 false, false, false, 0);
1825 X86TargetLowering::LowerFormalArguments(SDValue Chain,
1826 CallingConv::ID CallConv,
1828 const SmallVectorImpl<ISD::InputArg> &Ins,
1831 SmallVectorImpl<SDValue> &InVals)
1833 MachineFunction &MF = DAG.getMachineFunction();
1834 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1836 const Function* Fn = MF.getFunction();
1837 if (Fn->hasExternalLinkage() &&
1838 Subtarget->isTargetCygMing() &&
1839 Fn->getName() == "main")
1840 FuncInfo->setForceFramePointer(true);
1842 MachineFrameInfo *MFI = MF.getFrameInfo();
1843 bool Is64Bit = Subtarget->is64Bit();
1844 bool IsWindows = Subtarget->isTargetWindows();
1845 bool IsWin64 = Subtarget->isTargetWin64();
1847 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
1848 "Var args not supported with calling convention fastcc or ghc");
1850 // Assign locations to all of the incoming arguments.
1851 SmallVector<CCValAssign, 16> ArgLocs;
1852 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
1853 ArgLocs, *DAG.getContext());
1855 // Allocate shadow area for Win64
1857 CCInfo.AllocateStack(32, 8);
1860 CCInfo.AnalyzeFormalArguments(Ins, CC_X86);
1862 unsigned LastVal = ~0U;
1864 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1865 CCValAssign &VA = ArgLocs[i];
1866 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
1868 assert(VA.getValNo() != LastVal &&
1869 "Don't support value assigned to multiple locs yet");
1871 LastVal = VA.getValNo();
1873 if (VA.isRegLoc()) {
1874 EVT RegVT = VA.getLocVT();
1875 const TargetRegisterClass *RC;
1876 if (RegVT == MVT::i32)
1877 RC = &X86::GR32RegClass;
1878 else if (Is64Bit && RegVT == MVT::i64)
1879 RC = &X86::GR64RegClass;
1880 else if (RegVT == MVT::f32)
1881 RC = &X86::FR32RegClass;
1882 else if (RegVT == MVT::f64)
1883 RC = &X86::FR64RegClass;
1884 else if (RegVT.is256BitVector())
1885 RC = &X86::VR256RegClass;
1886 else if (RegVT.is128BitVector())
1887 RC = &X86::VR128RegClass;
1888 else if (RegVT == MVT::x86mmx)
1889 RC = &X86::VR64RegClass;
1891 llvm_unreachable("Unknown argument type!");
1893 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
1894 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
1896 // If this is an 8 or 16-bit value, it is really passed promoted to 32
1897 // bits. Insert an assert[sz]ext to capture this, then truncate to the
1899 if (VA.getLocInfo() == CCValAssign::SExt)
1900 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
1901 DAG.getValueType(VA.getValVT()));
1902 else if (VA.getLocInfo() == CCValAssign::ZExt)
1903 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
1904 DAG.getValueType(VA.getValVT()));
1905 else if (VA.getLocInfo() == CCValAssign::BCvt)
1906 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
1908 if (VA.isExtInLoc()) {
1909 // Handle MMX values passed in XMM regs.
1910 if (RegVT.isVector()) {
1911 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(),
1914 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
1917 assert(VA.isMemLoc());
1918 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
1921 // If value is passed via pointer - do a load.
1922 if (VA.getLocInfo() == CCValAssign::Indirect)
1923 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue,
1924 MachinePointerInfo(), false, false, false, 0);
1926 InVals.push_back(ArgValue);
1929 // The x86-64 ABI for returning structs by value requires that we copy
1930 // the sret argument into %rax for the return. Save the argument into
1931 // a virtual register so that we can access it from the return points.
1932 if (Is64Bit && MF.getFunction()->hasStructRetAttr()) {
1933 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1934 unsigned Reg = FuncInfo->getSRetReturnReg();
1936 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64));
1937 FuncInfo->setSRetReturnReg(Reg);
1939 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]);
1940 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
1943 unsigned StackSize = CCInfo.getNextStackOffset();
1944 // Align stack specially for tail calls.
1945 if (FuncIsMadeTailCallSafe(CallConv,
1946 MF.getTarget().Options.GuaranteedTailCallOpt))
1947 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
1949 // If the function takes variable number of arguments, make a frame index for
1950 // the start of the first vararg value... for expansion of llvm.va_start.
1952 if (Is64Bit || (CallConv != CallingConv::X86_FastCall &&
1953 CallConv != CallingConv::X86_ThisCall)) {
1954 FuncInfo->setVarArgsFrameIndex(MFI->CreateFixedObject(1, StackSize,true));
1957 unsigned TotalNumIntRegs = 0, TotalNumXMMRegs = 0;
1959 // FIXME: We should really autogenerate these arrays
1960 static const uint16_t GPR64ArgRegsWin64[] = {
1961 X86::RCX, X86::RDX, X86::R8, X86::R9
1963 static const uint16_t GPR64ArgRegs64Bit[] = {
1964 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
1966 static const uint16_t XMMArgRegs64Bit[] = {
1967 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
1968 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
1970 const uint16_t *GPR64ArgRegs;
1971 unsigned NumXMMRegs = 0;
1974 // The XMM registers which might contain var arg parameters are shadowed
1975 // in their paired GPR. So we only need to save the GPR to their home
1977 TotalNumIntRegs = 4;
1978 GPR64ArgRegs = GPR64ArgRegsWin64;
1980 TotalNumIntRegs = 6; TotalNumXMMRegs = 8;
1981 GPR64ArgRegs = GPR64ArgRegs64Bit;
1983 NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs64Bit,
1986 unsigned NumIntRegs = CCInfo.getFirstUnallocated(GPR64ArgRegs,
1989 bool NoImplicitFloatOps = Fn->hasFnAttr(Attribute::NoImplicitFloat);
1990 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) &&
1991 "SSE register cannot be used when SSE is disabled!");
1992 assert(!(NumXMMRegs && MF.getTarget().Options.UseSoftFloat &&
1993 NoImplicitFloatOps) &&
1994 "SSE register cannot be used when SSE is disabled!");
1995 if (MF.getTarget().Options.UseSoftFloat || NoImplicitFloatOps ||
1996 !Subtarget->hasSSE1())
1997 // Kernel mode asks for SSE to be disabled, so don't push them
1999 TotalNumXMMRegs = 0;
2002 const TargetFrameLowering &TFI = *getTargetMachine().getFrameLowering();
2003 // Get to the caller-allocated home save location. Add 8 to account
2004 // for the return address.
2005 int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
2006 FuncInfo->setRegSaveFrameIndex(
2007 MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false));
2008 // Fixup to set vararg frame on shadow area (4 x i64).
2010 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex());
2012 // For X86-64, if there are vararg parameters that are passed via
2013 // registers, then we must store them to their spots on the stack so
2014 // they may be loaded by deferencing the result of va_next.
2015 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8);
2016 FuncInfo->setVarArgsFPOffset(TotalNumIntRegs * 8 + NumXMMRegs * 16);
2017 FuncInfo->setRegSaveFrameIndex(
2018 MFI->CreateStackObject(TotalNumIntRegs * 8 + TotalNumXMMRegs * 16, 16,
2022 // Store the integer parameter registers.
2023 SmallVector<SDValue, 8> MemOps;
2024 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
2026 unsigned Offset = FuncInfo->getVarArgsGPOffset();
2027 for (; NumIntRegs != TotalNumIntRegs; ++NumIntRegs) {
2028 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN,
2029 DAG.getIntPtrConstant(Offset));
2030 unsigned VReg = MF.addLiveIn(GPR64ArgRegs[NumIntRegs],
2031 &X86::GR64RegClass);
2032 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
2034 DAG.getStore(Val.getValue(1), dl, Val, FIN,
2035 MachinePointerInfo::getFixedStack(
2036 FuncInfo->getRegSaveFrameIndex(), Offset),
2038 MemOps.push_back(Store);
2042 if (TotalNumXMMRegs != 0 && NumXMMRegs != TotalNumXMMRegs) {
2043 // Now store the XMM (fp + vector) parameter registers.
2044 SmallVector<SDValue, 11> SaveXMMOps;
2045 SaveXMMOps.push_back(Chain);
2047 unsigned AL = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
2048 SDValue ALVal = DAG.getCopyFromReg(DAG.getEntryNode(), dl, AL, MVT::i8);
2049 SaveXMMOps.push_back(ALVal);
2051 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2052 FuncInfo->getRegSaveFrameIndex()));
2053 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2054 FuncInfo->getVarArgsFPOffset()));
2056 for (; NumXMMRegs != TotalNumXMMRegs; ++NumXMMRegs) {
2057 unsigned VReg = MF.addLiveIn(XMMArgRegs64Bit[NumXMMRegs],
2058 &X86::VR128RegClass);
2059 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::v4f32);
2060 SaveXMMOps.push_back(Val);
2062 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
2064 &SaveXMMOps[0], SaveXMMOps.size()));
2067 if (!MemOps.empty())
2068 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2069 &MemOps[0], MemOps.size());
2073 // Some CCs need callee pop.
2074 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2075 MF.getTarget().Options.GuaranteedTailCallOpt)) {
2076 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything.
2078 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing.
2079 // If this is an sret function, the return should pop the hidden pointer.
2080 if (!Is64Bit && !IsTailCallConvention(CallConv) && !IsWindows &&
2081 argsAreStructReturn(Ins) == StackStructReturn)
2082 FuncInfo->setBytesToPopOnReturn(4);
2086 // RegSaveFrameIndex is X86-64 only.
2087 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
2088 if (CallConv == CallingConv::X86_FastCall ||
2089 CallConv == CallingConv::X86_ThisCall)
2090 // fastcc functions can't have varargs.
2091 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA);
2094 FuncInfo->setArgumentStackSize(StackSize);
2100 X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
2101 SDValue StackPtr, SDValue Arg,
2102 DebugLoc dl, SelectionDAG &DAG,
2103 const CCValAssign &VA,
2104 ISD::ArgFlagsTy Flags) const {
2105 unsigned LocMemOffset = VA.getLocMemOffset();
2106 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
2107 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
2108 if (Flags.isByVal())
2109 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
2111 return DAG.getStore(Chain, dl, Arg, PtrOff,
2112 MachinePointerInfo::getStack(LocMemOffset),
2116 /// EmitTailCallLoadRetAddr - Emit a load of return address if tail call
2117 /// optimization is performed and it is required.
2119 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
2120 SDValue &OutRetAddr, SDValue Chain,
2121 bool IsTailCall, bool Is64Bit,
2122 int FPDiff, DebugLoc dl) const {
2123 // Adjust the Return address stack slot.
2124 EVT VT = getPointerTy();
2125 OutRetAddr = getReturnAddressFrameIndex(DAG);
2127 // Load the "old" Return address.
2128 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(),
2129 false, false, false, 0);
2130 return SDValue(OutRetAddr.getNode(), 1);
2133 /// EmitTailCallStoreRetAddr - Emit a store of the return address if tail call
2134 /// optimization is performed and it is required (FPDiff!=0).
2136 EmitTailCallStoreRetAddr(SelectionDAG & DAG, MachineFunction &MF,
2137 SDValue Chain, SDValue RetAddrFrIdx,
2138 bool Is64Bit, int FPDiff, DebugLoc dl) {
2139 // Store the return address to the appropriate stack slot.
2140 if (!FPDiff) return Chain;
2141 // Calculate the new stack slot for the return address.
2142 int SlotSize = Is64Bit ? 8 : 4;
2143 int NewReturnAddrFI =
2144 MF.getFrameInfo()->CreateFixedObject(SlotSize, FPDiff-SlotSize, false);
2145 EVT VT = Is64Bit ? MVT::i64 : MVT::i32;
2146 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, VT);
2147 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
2148 MachinePointerInfo::getFixedStack(NewReturnAddrFI),
2154 X86TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
2155 SmallVectorImpl<SDValue> &InVals) const {
2156 SelectionDAG &DAG = CLI.DAG;
2157 DebugLoc &dl = CLI.DL;
2158 SmallVector<ISD::OutputArg, 32> &Outs = CLI.Outs;
2159 SmallVector<SDValue, 32> &OutVals = CLI.OutVals;
2160 SmallVector<ISD::InputArg, 32> &Ins = CLI.Ins;
2161 SDValue Chain = CLI.Chain;
2162 SDValue Callee = CLI.Callee;
2163 CallingConv::ID CallConv = CLI.CallConv;
2164 bool &isTailCall = CLI.IsTailCall;
2165 bool isVarArg = CLI.IsVarArg;
2167 MachineFunction &MF = DAG.getMachineFunction();
2168 bool Is64Bit = Subtarget->is64Bit();
2169 bool IsWin64 = Subtarget->isTargetWin64();
2170 bool IsWindows = Subtarget->isTargetWindows();
2171 StructReturnType SR = callIsStructReturn(Outs);
2172 bool IsSibcall = false;
2174 if (MF.getTarget().Options.DisableTailCalls)
2178 // Check if it's really possible to do a tail call.
2179 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
2180 isVarArg, SR != NotStructReturn,
2181 MF.getFunction()->hasStructRetAttr(),
2182 Outs, OutVals, Ins, DAG);
2184 // Sibcalls are automatically detected tailcalls which do not require
2186 if (!MF.getTarget().Options.GuaranteedTailCallOpt && isTailCall)
2193 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2194 "Var args not supported with calling convention fastcc or ghc");
2196 // Analyze operands of the call, assigning locations to each operand.
2197 SmallVector<CCValAssign, 16> ArgLocs;
2198 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
2199 ArgLocs, *DAG.getContext());
2201 // Allocate shadow area for Win64
2203 CCInfo.AllocateStack(32, 8);
2206 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2208 // Get a count of how many bytes are to be pushed on the stack.
2209 unsigned NumBytes = CCInfo.getNextStackOffset();
2211 // This is a sibcall. The memory operands are available in caller's
2212 // own caller's stack.
2214 else if (getTargetMachine().Options.GuaranteedTailCallOpt &&
2215 IsTailCallConvention(CallConv))
2216 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
2219 if (isTailCall && !IsSibcall) {
2220 // Lower arguments at fp - stackoffset + fpdiff.
2221 unsigned NumBytesCallerPushed =
2222 MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn();
2223 FPDiff = NumBytesCallerPushed - NumBytes;
2225 // Set the delta of movement of the returnaddr stackslot.
2226 // But only set if delta is greater than previous delta.
2227 if (FPDiff < (MF.getInfo<X86MachineFunctionInfo>()->getTCReturnAddrDelta()))
2228 MF.getInfo<X86MachineFunctionInfo>()->setTCReturnAddrDelta(FPDiff);
2232 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
2234 SDValue RetAddrFrIdx;
2235 // Load return address for tail calls.
2236 if (isTailCall && FPDiff)
2237 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall,
2238 Is64Bit, FPDiff, dl);
2240 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
2241 SmallVector<SDValue, 8> MemOpChains;
2244 // Walk the register/memloc assignments, inserting copies/loads. In the case
2245 // of tail call optimization arguments are handle later.
2246 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2247 CCValAssign &VA = ArgLocs[i];
2248 EVT RegVT = VA.getLocVT();
2249 SDValue Arg = OutVals[i];
2250 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2251 bool isByVal = Flags.isByVal();
2253 // Promote the value if needed.
2254 switch (VA.getLocInfo()) {
2255 default: llvm_unreachable("Unknown loc info!");
2256 case CCValAssign::Full: break;
2257 case CCValAssign::SExt:
2258 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
2260 case CCValAssign::ZExt:
2261 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
2263 case CCValAssign::AExt:
2264 if (RegVT.is128BitVector()) {
2265 // Special case: passing MMX values in XMM registers.
2266 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg);
2267 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
2268 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
2270 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
2272 case CCValAssign::BCvt:
2273 Arg = DAG.getNode(ISD::BITCAST, dl, RegVT, Arg);
2275 case CCValAssign::Indirect: {
2276 // Store the argument.
2277 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
2278 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
2279 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot,
2280 MachinePointerInfo::getFixedStack(FI),
2287 if (VA.isRegLoc()) {
2288 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2289 if (isVarArg && IsWin64) {
2290 // Win64 ABI requires argument XMM reg to be copied to the corresponding
2291 // shadow reg if callee is a varargs function.
2292 unsigned ShadowReg = 0;
2293 switch (VA.getLocReg()) {
2294 case X86::XMM0: ShadowReg = X86::RCX; break;
2295 case X86::XMM1: ShadowReg = X86::RDX; break;
2296 case X86::XMM2: ShadowReg = X86::R8; break;
2297 case X86::XMM3: ShadowReg = X86::R9; break;
2300 RegsToPass.push_back(std::make_pair(ShadowReg, Arg));
2302 } else if (!IsSibcall && (!isTailCall || isByVal)) {
2303 assert(VA.isMemLoc());
2304 if (StackPtr.getNode() == 0)
2305 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr, getPointerTy());
2306 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
2307 dl, DAG, VA, Flags));
2311 if (!MemOpChains.empty())
2312 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2313 &MemOpChains[0], MemOpChains.size());
2315 if (Subtarget->isPICStyleGOT()) {
2316 // ELF / PIC requires GOT in the EBX register before function calls via PLT
2319 RegsToPass.push_back(std::make_pair(unsigned(X86::EBX),
2320 DAG.getNode(X86ISD::GlobalBaseReg, DebugLoc(), getPointerTy())));
2322 // If we are tail calling and generating PIC/GOT style code load the
2323 // address of the callee into ECX. The value in ecx is used as target of
2324 // the tail jump. This is done to circumvent the ebx/callee-saved problem
2325 // for tail calls on PIC/GOT architectures. Normally we would just put the
2326 // address of GOT into ebx and then call target@PLT. But for tail calls
2327 // ebx would be restored (since ebx is callee saved) before jumping to the
2330 // Note: The actual moving to ECX is done further down.
2331 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
2332 if (G && !G->getGlobal()->hasHiddenVisibility() &&
2333 !G->getGlobal()->hasProtectedVisibility())
2334 Callee = LowerGlobalAddress(Callee, DAG);
2335 else if (isa<ExternalSymbolSDNode>(Callee))
2336 Callee = LowerExternalSymbol(Callee, DAG);
2340 if (Is64Bit && isVarArg && !IsWin64) {
2341 // From AMD64 ABI document:
2342 // For calls that may call functions that use varargs or stdargs
2343 // (prototype-less calls or calls to functions containing ellipsis (...) in
2344 // the declaration) %al is used as hidden argument to specify the number
2345 // of SSE registers used. The contents of %al do not need to match exactly
2346 // the number of registers, but must be an ubound on the number of SSE
2347 // registers used and is in the range 0 - 8 inclusive.
2349 // Count the number of XMM registers allocated.
2350 static const uint16_t XMMArgRegs[] = {
2351 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2352 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2354 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
2355 assert((Subtarget->hasSSE1() || !NumXMMRegs)
2356 && "SSE registers cannot be used when SSE is disabled");
2358 RegsToPass.push_back(std::make_pair(unsigned(X86::AL),
2359 DAG.getConstant(NumXMMRegs, MVT::i8)));
2362 // For tail calls lower the arguments to the 'real' stack slot.
2364 // Force all the incoming stack arguments to be loaded from the stack
2365 // before any new outgoing arguments are stored to the stack, because the
2366 // outgoing stack slots may alias the incoming argument stack slots, and
2367 // the alias isn't otherwise explicit. This is slightly more conservative
2368 // than necessary, because it means that each store effectively depends
2369 // on every argument instead of just those arguments it would clobber.
2370 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
2372 SmallVector<SDValue, 8> MemOpChains2;
2375 if (getTargetMachine().Options.GuaranteedTailCallOpt) {
2376 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2377 CCValAssign &VA = ArgLocs[i];
2380 assert(VA.isMemLoc());
2381 SDValue Arg = OutVals[i];
2382 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2383 // Create frame index.
2384 int32_t Offset = VA.getLocMemOffset()+FPDiff;
2385 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
2386 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
2387 FIN = DAG.getFrameIndex(FI, getPointerTy());
2389 if (Flags.isByVal()) {
2390 // Copy relative to framepointer.
2391 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset());
2392 if (StackPtr.getNode() == 0)
2393 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr,
2395 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source);
2397 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
2401 // Store relative to framepointer.
2402 MemOpChains2.push_back(
2403 DAG.getStore(ArgChain, dl, Arg, FIN,
2404 MachinePointerInfo::getFixedStack(FI),
2410 if (!MemOpChains2.empty())
2411 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2412 &MemOpChains2[0], MemOpChains2.size());
2414 // Store the return address to the appropriate stack slot.
2415 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx, Is64Bit,
2419 // Build a sequence of copy-to-reg nodes chained together with token chain
2420 // and flag operands which copy the outgoing args into registers.
2422 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2423 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
2424 RegsToPass[i].second, InFlag);
2425 InFlag = Chain.getValue(1);
2428 if (getTargetMachine().getCodeModel() == CodeModel::Large) {
2429 assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
2430 // In the 64-bit large code model, we have to make all calls
2431 // through a register, since the call instruction's 32-bit
2432 // pc-relative offset may not be large enough to hold the whole
2434 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2435 // If the callee is a GlobalAddress node (quite common, every direct call
2436 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
2439 // We should use extra load for direct calls to dllimported functions in
2441 const GlobalValue *GV = G->getGlobal();
2442 if (!GV->hasDLLImportLinkage()) {
2443 unsigned char OpFlags = 0;
2444 bool ExtraLoad = false;
2445 unsigned WrapperKind = ISD::DELETED_NODE;
2447 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
2448 // external symbols most go through the PLT in PIC mode. If the symbol
2449 // has hidden or protected visibility, or if it is static or local, then
2450 // we don't need to use the PLT - we can directly call it.
2451 if (Subtarget->isTargetELF() &&
2452 getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
2453 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
2454 OpFlags = X86II::MO_PLT;
2455 } else if (Subtarget->isPICStyleStubAny() &&
2456 (GV->isDeclaration() || GV->isWeakForLinker()) &&
2457 (!Subtarget->getTargetTriple().isMacOSX() ||
2458 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
2459 // PC-relative references to external symbols should go through $stub,
2460 // unless we're building with the leopard linker or later, which
2461 // automatically synthesizes these stubs.
2462 OpFlags = X86II::MO_DARWIN_STUB;
2463 } else if (Subtarget->isPICStyleRIPRel() &&
2464 isa<Function>(GV) &&
2465 cast<Function>(GV)->hasFnAttr(Attribute::NonLazyBind)) {
2466 // If the function is marked as non-lazy, generate an indirect call
2467 // which loads from the GOT directly. This avoids runtime overhead
2468 // at the cost of eager binding (and one extra byte of encoding).
2469 OpFlags = X86II::MO_GOTPCREL;
2470 WrapperKind = X86ISD::WrapperRIP;
2474 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(),
2475 G->getOffset(), OpFlags);
2477 // Add a wrapper if needed.
2478 if (WrapperKind != ISD::DELETED_NODE)
2479 Callee = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Callee);
2480 // Add extra indirection if needed.
2482 Callee = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Callee,
2483 MachinePointerInfo::getGOT(),
2484 false, false, false, 0);
2486 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
2487 unsigned char OpFlags = 0;
2489 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to
2490 // external symbols should go through the PLT.
2491 if (Subtarget->isTargetELF() &&
2492 getTargetMachine().getRelocationModel() == Reloc::PIC_) {
2493 OpFlags = X86II::MO_PLT;
2494 } else if (Subtarget->isPICStyleStubAny() &&
2495 (!Subtarget->getTargetTriple().isMacOSX() ||
2496 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
2497 // PC-relative references to external symbols should go through $stub,
2498 // unless we're building with the leopard linker or later, which
2499 // automatically synthesizes these stubs.
2500 OpFlags = X86II::MO_DARWIN_STUB;
2503 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(),
2507 // Returns a chain & a flag for retval copy to use.
2508 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
2509 SmallVector<SDValue, 8> Ops;
2511 if (!IsSibcall && isTailCall) {
2512 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
2513 DAG.getIntPtrConstant(0, true), InFlag);
2514 InFlag = Chain.getValue(1);
2517 Ops.push_back(Chain);
2518 Ops.push_back(Callee);
2521 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32));
2523 // Add argument registers to the end of the list so that they are known live
2525 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
2526 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
2527 RegsToPass[i].second.getValueType()));
2529 // Add a register mask operand representing the call-preserved registers.
2530 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
2531 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv);
2532 assert(Mask && "Missing call preserved mask for calling convention");
2533 Ops.push_back(DAG.getRegisterMask(Mask));
2535 if (InFlag.getNode())
2536 Ops.push_back(InFlag);
2540 //// If this is the first return lowered for this function, add the regs
2541 //// to the liveout set for the function.
2542 // This isn't right, although it's probably harmless on x86; liveouts
2543 // should be computed from returns not tail calls. Consider a void
2544 // function making a tail call to a function returning int.
2545 return DAG.getNode(X86ISD::TC_RETURN, dl,
2546 NodeTys, &Ops[0], Ops.size());
2549 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, &Ops[0], Ops.size());
2550 InFlag = Chain.getValue(1);
2552 // Create the CALLSEQ_END node.
2553 unsigned NumBytesForCalleeToPush;
2554 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2555 getTargetMachine().Options.GuaranteedTailCallOpt))
2556 NumBytesForCalleeToPush = NumBytes; // Callee pops everything
2557 else if (!Is64Bit && !IsTailCallConvention(CallConv) && !IsWindows &&
2558 SR == StackStructReturn)
2559 // If this is a call to a struct-return function, the callee
2560 // pops the hidden struct pointer, so we have to push it back.
2561 // This is common for Darwin/X86, Linux & Mingw32 targets.
2562 // For MSVC Win32 targets, the caller pops the hidden struct pointer.
2563 NumBytesForCalleeToPush = 4;
2565 NumBytesForCalleeToPush = 0; // Callee pops nothing.
2567 // Returns a flag for retval copy to use.
2569 Chain = DAG.getCALLSEQ_END(Chain,
2570 DAG.getIntPtrConstant(NumBytes, true),
2571 DAG.getIntPtrConstant(NumBytesForCalleeToPush,
2574 InFlag = Chain.getValue(1);
2577 // Handle result values, copying them out of physregs into vregs that we
2579 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
2580 Ins, dl, DAG, InVals);
2584 //===----------------------------------------------------------------------===//
2585 // Fast Calling Convention (tail call) implementation
2586 //===----------------------------------------------------------------------===//
2588 // Like std call, callee cleans arguments, convention except that ECX is
2589 // reserved for storing the tail called function address. Only 2 registers are
2590 // free for argument passing (inreg). Tail call optimization is performed
2592 // * tailcallopt is enabled
2593 // * caller/callee are fastcc
2594 // On X86_64 architecture with GOT-style position independent code only local
2595 // (within module) calls are supported at the moment.
2596 // To keep the stack aligned according to platform abi the function
2597 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
2598 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
2599 // If a tail called function callee has more arguments than the caller the
2600 // caller needs to make sure that there is room to move the RETADDR to. This is
2601 // achieved by reserving an area the size of the argument delta right after the
2602 // original REtADDR, but before the saved framepointer or the spilled registers
2603 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
2615 /// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned
2616 /// for a 16 byte align requirement.
2618 X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
2619 SelectionDAG& DAG) const {
2620 MachineFunction &MF = DAG.getMachineFunction();
2621 const TargetMachine &TM = MF.getTarget();
2622 const TargetFrameLowering &TFI = *TM.getFrameLowering();
2623 unsigned StackAlignment = TFI.getStackAlignment();
2624 uint64_t AlignMask = StackAlignment - 1;
2625 int64_t Offset = StackSize;
2626 uint64_t SlotSize = TD->getPointerSize();
2627 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
2628 // Number smaller than 12 so just add the difference.
2629 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
2631 // Mask out lower bits, add stackalignment once plus the 12 bytes.
2632 Offset = ((~AlignMask) & Offset) + StackAlignment +
2633 (StackAlignment-SlotSize);
2638 /// MatchingStackOffset - Return true if the given stack call argument is
2639 /// already available in the same position (relatively) of the caller's
2640 /// incoming argument stack.
2642 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
2643 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
2644 const X86InstrInfo *TII) {
2645 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
2647 if (Arg.getOpcode() == ISD::CopyFromReg) {
2648 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
2649 if (!TargetRegisterInfo::isVirtualRegister(VR))
2651 MachineInstr *Def = MRI->getVRegDef(VR);
2654 if (!Flags.isByVal()) {
2655 if (!TII->isLoadFromStackSlot(Def, FI))
2658 unsigned Opcode = Def->getOpcode();
2659 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r) &&
2660 Def->getOperand(1).isFI()) {
2661 FI = Def->getOperand(1).getIndex();
2662 Bytes = Flags.getByValSize();
2666 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
2667 if (Flags.isByVal())
2668 // ByVal argument is passed in as a pointer but it's now being
2669 // dereferenced. e.g.
2670 // define @foo(%struct.X* %A) {
2671 // tail call @bar(%struct.X* byval %A)
2674 SDValue Ptr = Ld->getBasePtr();
2675 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
2678 FI = FINode->getIndex();
2679 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) {
2680 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg);
2681 FI = FINode->getIndex();
2682 Bytes = Flags.getByValSize();
2686 assert(FI != INT_MAX);
2687 if (!MFI->isFixedObjectIndex(FI))
2689 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
2692 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
2693 /// for tail call optimization. Targets which want to do tail call
2694 /// optimization should implement this function.
2696 X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
2697 CallingConv::ID CalleeCC,
2699 bool isCalleeStructRet,
2700 bool isCallerStructRet,
2701 const SmallVectorImpl<ISD::OutputArg> &Outs,
2702 const SmallVectorImpl<SDValue> &OutVals,
2703 const SmallVectorImpl<ISD::InputArg> &Ins,
2704 SelectionDAG& DAG) const {
2705 if (!IsTailCallConvention(CalleeCC) &&
2706 CalleeCC != CallingConv::C)
2709 // If -tailcallopt is specified, make fastcc functions tail-callable.
2710 const MachineFunction &MF = DAG.getMachineFunction();
2711 const Function *CallerF = DAG.getMachineFunction().getFunction();
2712 CallingConv::ID CallerCC = CallerF->getCallingConv();
2713 bool CCMatch = CallerCC == CalleeCC;
2715 if (getTargetMachine().Options.GuaranteedTailCallOpt) {
2716 if (IsTailCallConvention(CalleeCC) && CCMatch)
2721 // Look for obvious safe cases to perform tail call optimization that do not
2722 // require ABI changes. This is what gcc calls sibcall.
2724 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
2725 // emit a special epilogue.
2726 if (RegInfo->needsStackRealignment(MF))
2729 // Also avoid sibcall optimization if either caller or callee uses struct
2730 // return semantics.
2731 if (isCalleeStructRet || isCallerStructRet)
2734 // An stdcall caller is expected to clean up its arguments; the callee
2735 // isn't going to do that.
2736 if (!CCMatch && CallerCC==CallingConv::X86_StdCall)
2739 // Do not sibcall optimize vararg calls unless all arguments are passed via
2741 if (isVarArg && !Outs.empty()) {
2743 // Optimizing for varargs on Win64 is unlikely to be safe without
2744 // additional testing.
2745 if (Subtarget->isTargetWin64())
2748 SmallVector<CCValAssign, 16> ArgLocs;
2749 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(),
2750 getTargetMachine(), ArgLocs, *DAG.getContext());
2752 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2753 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
2754 if (!ArgLocs[i].isRegLoc())
2758 // If the call result is in ST0 / ST1, it needs to be popped off the x87
2759 // stack. Therefore, if it's not used by the call it is not safe to optimize
2760 // this into a sibcall.
2761 bool Unused = false;
2762 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
2769 SmallVector<CCValAssign, 16> RVLocs;
2770 CCState CCInfo(CalleeCC, false, DAG.getMachineFunction(),
2771 getTargetMachine(), RVLocs, *DAG.getContext());
2772 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
2773 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
2774 CCValAssign &VA = RVLocs[i];
2775 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1)
2780 // If the calling conventions do not match, then we'd better make sure the
2781 // results are returned in the same way as what the caller expects.
2783 SmallVector<CCValAssign, 16> RVLocs1;
2784 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(),
2785 getTargetMachine(), RVLocs1, *DAG.getContext());
2786 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86);
2788 SmallVector<CCValAssign, 16> RVLocs2;
2789 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(),
2790 getTargetMachine(), RVLocs2, *DAG.getContext());
2791 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86);
2793 if (RVLocs1.size() != RVLocs2.size())
2795 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
2796 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
2798 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
2800 if (RVLocs1[i].isRegLoc()) {
2801 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
2804 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
2810 // If the callee takes no arguments then go on to check the results of the
2812 if (!Outs.empty()) {
2813 // Check if stack adjustment is needed. For now, do not do this if any
2814 // argument is passed on the stack.
2815 SmallVector<CCValAssign, 16> ArgLocs;
2816 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(),
2817 getTargetMachine(), ArgLocs, *DAG.getContext());
2819 // Allocate shadow area for Win64
2820 if (Subtarget->isTargetWin64()) {
2821 CCInfo.AllocateStack(32, 8);
2824 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2825 if (CCInfo.getNextStackOffset()) {
2826 MachineFunction &MF = DAG.getMachineFunction();
2827 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn())
2830 // Check if the arguments are already laid out in the right way as
2831 // the caller's fixed stack objects.
2832 MachineFrameInfo *MFI = MF.getFrameInfo();
2833 const MachineRegisterInfo *MRI = &MF.getRegInfo();
2834 const X86InstrInfo *TII =
2835 ((X86TargetMachine&)getTargetMachine()).getInstrInfo();
2836 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2837 CCValAssign &VA = ArgLocs[i];
2838 SDValue Arg = OutVals[i];
2839 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2840 if (VA.getLocInfo() == CCValAssign::Indirect)
2842 if (!VA.isRegLoc()) {
2843 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
2850 // If the tailcall address may be in a register, then make sure it's
2851 // possible to register allocate for it. In 32-bit, the call address can
2852 // only target EAX, EDX, or ECX since the tail call must be scheduled after
2853 // callee-saved registers are restored. These happen to be the same
2854 // registers used to pass 'inreg' arguments so watch out for those.
2855 if (!Subtarget->is64Bit() &&
2856 !isa<GlobalAddressSDNode>(Callee) &&
2857 !isa<ExternalSymbolSDNode>(Callee)) {
2858 unsigned NumInRegs = 0;
2859 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2860 CCValAssign &VA = ArgLocs[i];
2863 unsigned Reg = VA.getLocReg();
2866 case X86::EAX: case X86::EDX: case X86::ECX:
2867 if (++NumInRegs == 3)
2879 X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
2880 const TargetLibraryInfo *libInfo) const {
2881 return X86::createFastISel(funcInfo, libInfo);
2885 //===----------------------------------------------------------------------===//
2886 // Other Lowering Hooks
2887 //===----------------------------------------------------------------------===//
2889 static bool MayFoldLoad(SDValue Op) {
2890 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode());
2893 static bool MayFoldIntoStore(SDValue Op) {
2894 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin());
2897 static bool isTargetShuffle(unsigned Opcode) {
2899 default: return false;
2900 case X86ISD::PSHUFD:
2901 case X86ISD::PSHUFHW:
2902 case X86ISD::PSHUFLW:
2904 case X86ISD::PALIGN:
2905 case X86ISD::MOVLHPS:
2906 case X86ISD::MOVLHPD:
2907 case X86ISD::MOVHLPS:
2908 case X86ISD::MOVLPS:
2909 case X86ISD::MOVLPD:
2910 case X86ISD::MOVSHDUP:
2911 case X86ISD::MOVSLDUP:
2912 case X86ISD::MOVDDUP:
2915 case X86ISD::UNPCKL:
2916 case X86ISD::UNPCKH:
2917 case X86ISD::VPERMILP:
2918 case X86ISD::VPERM2X128:
2919 case X86ISD::VPERMI:
2924 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
2925 SDValue V1, SelectionDAG &DAG) {
2927 default: llvm_unreachable("Unknown x86 shuffle node");
2928 case X86ISD::MOVSHDUP:
2929 case X86ISD::MOVSLDUP:
2930 case X86ISD::MOVDDUP:
2931 return DAG.getNode(Opc, dl, VT, V1);
2935 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
2936 SDValue V1, unsigned TargetMask,
2937 SelectionDAG &DAG) {
2939 default: llvm_unreachable("Unknown x86 shuffle node");
2940 case X86ISD::PSHUFD:
2941 case X86ISD::PSHUFHW:
2942 case X86ISD::PSHUFLW:
2943 case X86ISD::VPERMILP:
2944 case X86ISD::VPERMI:
2945 return DAG.getNode(Opc, dl, VT, V1, DAG.getConstant(TargetMask, MVT::i8));
2949 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
2950 SDValue V1, SDValue V2, unsigned TargetMask,
2951 SelectionDAG &DAG) {
2953 default: llvm_unreachable("Unknown x86 shuffle node");
2954 case X86ISD::PALIGN:
2956 case X86ISD::VPERM2X128:
2957 return DAG.getNode(Opc, dl, VT, V1, V2,
2958 DAG.getConstant(TargetMask, MVT::i8));
2962 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
2963 SDValue V1, SDValue V2, SelectionDAG &DAG) {
2965 default: llvm_unreachable("Unknown x86 shuffle node");
2966 case X86ISD::MOVLHPS:
2967 case X86ISD::MOVLHPD:
2968 case X86ISD::MOVHLPS:
2969 case X86ISD::MOVLPS:
2970 case X86ISD::MOVLPD:
2973 case X86ISD::UNPCKL:
2974 case X86ISD::UNPCKH:
2975 return DAG.getNode(Opc, dl, VT, V1, V2);
2979 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
2980 MachineFunction &MF = DAG.getMachineFunction();
2981 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2982 int ReturnAddrIndex = FuncInfo->getRAIndex();
2984 if (ReturnAddrIndex == 0) {
2985 // Set up a frame object for the return address.
2986 uint64_t SlotSize = TD->getPointerSize();
2987 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize, -SlotSize,
2989 FuncInfo->setRAIndex(ReturnAddrIndex);
2992 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
2996 bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
2997 bool hasSymbolicDisplacement) {
2998 // Offset should fit into 32 bit immediate field.
2999 if (!isInt<32>(Offset))
3002 // If we don't have a symbolic displacement - we don't have any extra
3004 if (!hasSymbolicDisplacement)
3007 // FIXME: Some tweaks might be needed for medium code model.
3008 if (M != CodeModel::Small && M != CodeModel::Kernel)
3011 // For small code model we assume that latest object is 16MB before end of 31
3012 // bits boundary. We may also accept pretty large negative constants knowing
3013 // that all objects are in the positive half of address space.
3014 if (M == CodeModel::Small && Offset < 16*1024*1024)
3017 // For kernel code model we know that all object resist in the negative half
3018 // of 32bits address space. We may not accept negative offsets, since they may
3019 // be just off and we may accept pretty large positive ones.
3020 if (M == CodeModel::Kernel && Offset > 0)
3026 /// isCalleePop - Determines whether the callee is required to pop its
3027 /// own arguments. Callee pop is necessary to support tail calls.
3028 bool X86::isCalleePop(CallingConv::ID CallingConv,
3029 bool is64Bit, bool IsVarArg, bool TailCallOpt) {
3033 switch (CallingConv) {
3036 case CallingConv::X86_StdCall:
3038 case CallingConv::X86_FastCall:
3040 case CallingConv::X86_ThisCall:
3042 case CallingConv::Fast:
3044 case CallingConv::GHC:
3049 /// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86
3050 /// specific condition code, returning the condition code and the LHS/RHS of the
3051 /// comparison to make.
3052 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
3053 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
3055 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
3056 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
3057 // X > -1 -> X == 0, jump !sign.
3058 RHS = DAG.getConstant(0, RHS.getValueType());
3059 return X86::COND_NS;
3061 if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
3062 // X < 0 -> X == 0, jump on sign.
3065 if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
3067 RHS = DAG.getConstant(0, RHS.getValueType());
3068 return X86::COND_LE;
3072 switch (SetCCOpcode) {
3073 default: llvm_unreachable("Invalid integer condition!");
3074 case ISD::SETEQ: return X86::COND_E;
3075 case ISD::SETGT: return X86::COND_G;
3076 case ISD::SETGE: return X86::COND_GE;
3077 case ISD::SETLT: return X86::COND_L;
3078 case ISD::SETLE: return X86::COND_LE;
3079 case ISD::SETNE: return X86::COND_NE;
3080 case ISD::SETULT: return X86::COND_B;
3081 case ISD::SETUGT: return X86::COND_A;
3082 case ISD::SETULE: return X86::COND_BE;
3083 case ISD::SETUGE: return X86::COND_AE;
3087 // First determine if it is required or is profitable to flip the operands.
3089 // If LHS is a foldable load, but RHS is not, flip the condition.
3090 if (ISD::isNON_EXTLoad(LHS.getNode()) &&
3091 !ISD::isNON_EXTLoad(RHS.getNode())) {
3092 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
3093 std::swap(LHS, RHS);
3096 switch (SetCCOpcode) {
3102 std::swap(LHS, RHS);
3106 // On a floating point condition, the flags are set as follows:
3108 // 0 | 0 | 0 | X > Y
3109 // 0 | 0 | 1 | X < Y
3110 // 1 | 0 | 0 | X == Y
3111 // 1 | 1 | 1 | unordered
3112 switch (SetCCOpcode) {
3113 default: llvm_unreachable("Condcode should be pre-legalized away");
3115 case ISD::SETEQ: return X86::COND_E;
3116 case ISD::SETOLT: // flipped
3118 case ISD::SETGT: return X86::COND_A;
3119 case ISD::SETOLE: // flipped
3121 case ISD::SETGE: return X86::COND_AE;
3122 case ISD::SETUGT: // flipped
3124 case ISD::SETLT: return X86::COND_B;
3125 case ISD::SETUGE: // flipped
3127 case ISD::SETLE: return X86::COND_BE;
3129 case ISD::SETNE: return X86::COND_NE;
3130 case ISD::SETUO: return X86::COND_P;
3131 case ISD::SETO: return X86::COND_NP;
3133 case ISD::SETUNE: return X86::COND_INVALID;
3137 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
3138 /// code. Current x86 isa includes the following FP cmov instructions:
3139 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
3140 static bool hasFPCMov(unsigned X86CC) {
3156 /// isFPImmLegal - Returns true if the target can instruction select the
3157 /// specified FP immediate natively. If false, the legalizer will
3158 /// materialize the FP immediate as a load from a constant pool.
3159 bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
3160 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
3161 if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
3167 /// isUndefOrInRange - Return true if Val is undef or if its value falls within
3168 /// the specified range (L, H].
3169 static bool isUndefOrInRange(int Val, int Low, int Hi) {
3170 return (Val < 0) || (Val >= Low && Val < Hi);
3173 /// isUndefOrEqual - Val is either less than zero (undef) or equal to the
3174 /// specified value.
3175 static bool isUndefOrEqual(int Val, int CmpVal) {
3176 if (Val < 0 || Val == CmpVal)
3181 /// isSequentialOrUndefInRange - Return true if every element in Mask, beginning
3182 /// from position Pos and ending in Pos+Size, falls within the specified
3183 /// sequential range (L, L+Pos]. or is undef.
3184 static bool isSequentialOrUndefInRange(ArrayRef<int> Mask,
3185 unsigned Pos, unsigned Size, int Low) {
3186 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low)
3187 if (!isUndefOrEqual(Mask[i], Low))
3192 /// isPSHUFDMask - Return true if the node specifies a shuffle of elements that
3193 /// is suitable for input to PSHUFD or PSHUFW. That is, it doesn't reference
3194 /// the second operand.
3195 static bool isPSHUFDMask(ArrayRef<int> Mask, EVT VT) {
3196 if (VT == MVT::v4f32 || VT == MVT::v4i32 )
3197 return (Mask[0] < 4 && Mask[1] < 4 && Mask[2] < 4 && Mask[3] < 4);
3198 if (VT == MVT::v2f64 || VT == MVT::v2i64)
3199 return (Mask[0] < 2 && Mask[1] < 2);
3203 /// isPSHUFHWMask - Return true if the node specifies a shuffle of elements that
3204 /// is suitable for input to PSHUFHW.
3205 static bool isPSHUFHWMask(ArrayRef<int> Mask, EVT VT, bool HasAVX2) {
3206 if (VT != MVT::v8i16 && (!HasAVX2 || VT != MVT::v16i16))
3209 // Lower quadword copied in order or undef.
3210 if (!isSequentialOrUndefInRange(Mask, 0, 4, 0))
3213 // Upper quadword shuffled.
3214 for (unsigned i = 4; i != 8; ++i)
3215 if (!isUndefOrInRange(Mask[i], 4, 8))
3218 if (VT == MVT::v16i16) {
3219 // Lower quadword copied in order or undef.
3220 if (!isSequentialOrUndefInRange(Mask, 8, 4, 8))
3223 // Upper quadword shuffled.
3224 for (unsigned i = 12; i != 16; ++i)
3225 if (!isUndefOrInRange(Mask[i], 12, 16))
3232 /// isPSHUFLWMask - Return true if the node specifies a shuffle of elements that
3233 /// is suitable for input to PSHUFLW.
3234 static bool isPSHUFLWMask(ArrayRef<int> Mask, EVT VT, bool HasAVX2) {
3235 if (VT != MVT::v8i16 && (!HasAVX2 || VT != MVT::v16i16))
3238 // Upper quadword copied in order.
3239 if (!isSequentialOrUndefInRange(Mask, 4, 4, 4))
3242 // Lower quadword shuffled.
3243 for (unsigned i = 0; i != 4; ++i)
3244 if (!isUndefOrInRange(Mask[i], 0, 4))
3247 if (VT == MVT::v16i16) {
3248 // Upper quadword copied in order.
3249 if (!isSequentialOrUndefInRange(Mask, 12, 4, 12))
3252 // Lower quadword shuffled.
3253 for (unsigned i = 8; i != 12; ++i)
3254 if (!isUndefOrInRange(Mask[i], 8, 12))
3261 /// isPALIGNRMask - Return true if the node specifies a shuffle of elements that
3262 /// is suitable for input to PALIGNR.
3263 static bool isPALIGNRMask(ArrayRef<int> Mask, EVT VT,
3264 const X86Subtarget *Subtarget) {
3265 if ((VT.getSizeInBits() == 128 && !Subtarget->hasSSSE3()) ||
3266 (VT.getSizeInBits() == 256 && !Subtarget->hasAVX2()))
3269 unsigned NumElts = VT.getVectorNumElements();
3270 unsigned NumLanes = VT.getSizeInBits()/128;
3271 unsigned NumLaneElts = NumElts/NumLanes;
3273 // Do not handle 64-bit element shuffles with palignr.
3274 if (NumLaneElts == 2)
3277 for (unsigned l = 0; l != NumElts; l+=NumLaneElts) {
3279 for (i = 0; i != NumLaneElts; ++i) {
3284 // Lane is all undef, go to next lane
3285 if (i == NumLaneElts)
3288 int Start = Mask[i+l];
3290 // Make sure its in this lane in one of the sources
3291 if (!isUndefOrInRange(Start, l, l+NumLaneElts) &&
3292 !isUndefOrInRange(Start, l+NumElts, l+NumElts+NumLaneElts))
3295 // If not lane 0, then we must match lane 0
3296 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Start, Mask[i]+l))
3299 // Correct second source to be contiguous with first source
3300 if (Start >= (int)NumElts)
3301 Start -= NumElts - NumLaneElts;
3303 // Make sure we're shifting in the right direction.
3304 if (Start <= (int)(i+l))
3309 // Check the rest of the elements to see if they are consecutive.
3310 for (++i; i != NumLaneElts; ++i) {
3311 int Idx = Mask[i+l];
3313 // Make sure its in this lane
3314 if (!isUndefOrInRange(Idx, l, l+NumLaneElts) &&
3315 !isUndefOrInRange(Idx, l+NumElts, l+NumElts+NumLaneElts))
3318 // If not lane 0, then we must match lane 0
3319 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Idx, Mask[i]+l))
3322 if (Idx >= (int)NumElts)
3323 Idx -= NumElts - NumLaneElts;
3325 if (!isUndefOrEqual(Idx, Start+i))
3334 /// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming
3335 /// the two vector operands have swapped position.
3336 static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask,
3337 unsigned NumElems) {
3338 for (unsigned i = 0; i != NumElems; ++i) {
3342 else if (idx < (int)NumElems)
3343 Mask[i] = idx + NumElems;
3345 Mask[i] = idx - NumElems;
3349 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
3350 /// specifies a shuffle of elements that is suitable for input to 128/256-bit
3351 /// SHUFPS and SHUFPD. If Commuted is true, then it checks for sources to be
3352 /// reverse of what x86 shuffles want.
3353 static bool isSHUFPMask(ArrayRef<int> Mask, EVT VT, bool HasAVX,
3354 bool Commuted = false) {
3355 if (!HasAVX && VT.getSizeInBits() == 256)
3358 unsigned NumElems = VT.getVectorNumElements();
3359 unsigned NumLanes = VT.getSizeInBits()/128;
3360 unsigned NumLaneElems = NumElems/NumLanes;
3362 if (NumLaneElems != 2 && NumLaneElems != 4)
3365 // VSHUFPSY divides the resulting vector into 4 chunks.
3366 // The sources are also splitted into 4 chunks, and each destination
3367 // chunk must come from a different source chunk.
3369 // SRC1 => X7 X6 X5 X4 X3 X2 X1 X0
3370 // SRC2 => Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y9
3372 // DST => Y7..Y4, Y7..Y4, X7..X4, X7..X4,
3373 // Y3..Y0, Y3..Y0, X3..X0, X3..X0
3375 // VSHUFPDY divides the resulting vector into 4 chunks.
3376 // The sources are also splitted into 4 chunks, and each destination
3377 // chunk must come from a different source chunk.
3379 // SRC1 => X3 X2 X1 X0
3380 // SRC2 => Y3 Y2 Y1 Y0
3382 // DST => Y3..Y2, X3..X2, Y1..Y0, X1..X0
3384 unsigned HalfLaneElems = NumLaneElems/2;
3385 for (unsigned l = 0; l != NumElems; l += NumLaneElems) {
3386 for (unsigned i = 0; i != NumLaneElems; ++i) {
3387 int Idx = Mask[i+l];
3388 unsigned RngStart = l + ((Commuted == (i<HalfLaneElems)) ? NumElems : 0);
3389 if (!isUndefOrInRange(Idx, RngStart, RngStart+NumLaneElems))
3391 // For VSHUFPSY, the mask of the second half must be the same as the
3392 // first but with the appropriate offsets. This works in the same way as
3393 // VPERMILPS works with masks.
3394 if (NumElems != 8 || l == 0 || Mask[i] < 0)
3396 if (!isUndefOrEqual(Idx, Mask[i]+l))
3404 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
3405 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
3406 static bool isMOVHLPSMask(ArrayRef<int> Mask, EVT VT) {
3407 if (!VT.is128BitVector())
3410 unsigned NumElems = VT.getVectorNumElements();
3415 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3
3416 return isUndefOrEqual(Mask[0], 6) &&
3417 isUndefOrEqual(Mask[1], 7) &&
3418 isUndefOrEqual(Mask[2], 2) &&
3419 isUndefOrEqual(Mask[3], 3);
3422 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
3423 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
3425 static bool isMOVHLPS_v_undef_Mask(ArrayRef<int> Mask, EVT VT) {
3426 if (!VT.is128BitVector())
3429 unsigned NumElems = VT.getVectorNumElements();
3434 return isUndefOrEqual(Mask[0], 2) &&
3435 isUndefOrEqual(Mask[1], 3) &&
3436 isUndefOrEqual(Mask[2], 2) &&
3437 isUndefOrEqual(Mask[3], 3);
3440 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
3441 /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
3442 static bool isMOVLPMask(ArrayRef<int> Mask, EVT VT) {
3443 if (!VT.is128BitVector())
3446 unsigned NumElems = VT.getVectorNumElements();
3448 if (NumElems != 2 && NumElems != 4)
3451 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
3452 if (!isUndefOrEqual(Mask[i], i + NumElems))
3455 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i)
3456 if (!isUndefOrEqual(Mask[i], i))
3462 /// isMOVLHPSMask - Return true if the specified VECTOR_SHUFFLE operand
3463 /// specifies a shuffle of elements that is suitable for input to MOVLHPS.
3464 static bool isMOVLHPSMask(ArrayRef<int> Mask, EVT VT) {
3465 if (!VT.is128BitVector())
3468 unsigned NumElems = VT.getVectorNumElements();
3470 if (NumElems != 2 && NumElems != 4)
3473 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
3474 if (!isUndefOrEqual(Mask[i], i))
3477 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
3478 if (!isUndefOrEqual(Mask[i + e], i + NumElems))
3485 // Some special combinations that can be optimized.
3488 SDValue Compact8x32ShuffleNode(ShuffleVectorSDNode *SVOp,
3489 SelectionDAG &DAG) {
3490 EVT VT = SVOp->getValueType(0);
3491 DebugLoc dl = SVOp->getDebugLoc();
3493 if (VT != MVT::v8i32 && VT != MVT::v8f32)
3496 ArrayRef<int> Mask = SVOp->getMask();
3498 // These are the special masks that may be optimized.
3499 static const int MaskToOptimizeEven[] = {0, 8, 2, 10, 4, 12, 6, 14};
3500 static const int MaskToOptimizeOdd[] = {1, 9, 3, 11, 5, 13, 7, 15};
3501 bool MatchEvenMask = true;
3502 bool MatchOddMask = true;
3503 for (int i=0; i<8; ++i) {
3504 if (!isUndefOrEqual(Mask[i], MaskToOptimizeEven[i]))
3505 MatchEvenMask = false;
3506 if (!isUndefOrEqual(Mask[i], MaskToOptimizeOdd[i]))
3507 MatchOddMask = false;
3509 static const int CompactionMaskEven[] = {0, 2, -1, -1, 4, 6, -1, -1};
3510 static const int CompactionMaskOdd [] = {1, 3, -1, -1, 5, 7, -1, -1};
3512 const int *CompactionMask;
3514 CompactionMask = CompactionMaskEven;
3515 else if (MatchOddMask)
3516 CompactionMask = CompactionMaskOdd;
3520 SDValue UndefNode = DAG.getNode(ISD::UNDEF, dl, VT);
3522 SDValue Op0 = DAG.getVectorShuffle(VT, dl, SVOp->getOperand(0),
3523 UndefNode, CompactionMask);
3524 SDValue Op1 = DAG.getVectorShuffle(VT, dl, SVOp->getOperand(1),
3525 UndefNode, CompactionMask);
3526 static const int UnpackMask[] = {0, 8, 1, 9, 4, 12, 5, 13};
3527 return DAG.getVectorShuffle(VT, dl, Op0, Op1, UnpackMask);
3530 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
3531 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
3532 static bool isUNPCKLMask(ArrayRef<int> Mask, EVT VT,
3533 bool HasAVX2, bool V2IsSplat = false) {
3534 unsigned NumElts = VT.getVectorNumElements();
3536 assert((VT.is128BitVector() || VT.is256BitVector()) &&
3537 "Unsupported vector type for unpckh");
3539 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8 &&
3540 (!HasAVX2 || (NumElts != 16 && NumElts != 32)))
3543 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
3544 // independently on 128-bit lanes.
3545 unsigned NumLanes = VT.getSizeInBits()/128;
3546 unsigned NumLaneElts = NumElts/NumLanes;
3548 for (unsigned l = 0; l != NumLanes; ++l) {
3549 for (unsigned i = l*NumLaneElts, j = l*NumLaneElts;
3550 i != (l+1)*NumLaneElts;
3553 int BitI1 = Mask[i+1];
3554 if (!isUndefOrEqual(BitI, j))
3557 if (!isUndefOrEqual(BitI1, NumElts))
3560 if (!isUndefOrEqual(BitI1, j + NumElts))
3569 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
3570 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
3571 static bool isUNPCKHMask(ArrayRef<int> Mask, EVT VT,
3572 bool HasAVX2, bool V2IsSplat = false) {
3573 unsigned NumElts = VT.getVectorNumElements();
3575 assert((VT.is128BitVector() || VT.is256BitVector()) &&
3576 "Unsupported vector type for unpckh");
3578 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8 &&
3579 (!HasAVX2 || (NumElts != 16 && NumElts != 32)))
3582 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
3583 // independently on 128-bit lanes.
3584 unsigned NumLanes = VT.getSizeInBits()/128;
3585 unsigned NumLaneElts = NumElts/NumLanes;
3587 for (unsigned l = 0; l != NumLanes; ++l) {
3588 for (unsigned i = l*NumLaneElts, j = (l*NumLaneElts)+NumLaneElts/2;
3589 i != (l+1)*NumLaneElts; i += 2, ++j) {
3591 int BitI1 = Mask[i+1];
3592 if (!isUndefOrEqual(BitI, j))
3595 if (isUndefOrEqual(BitI1, NumElts))
3598 if (!isUndefOrEqual(BitI1, j+NumElts))
3606 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
3607 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
3609 static bool isUNPCKL_v_undef_Mask(ArrayRef<int> Mask, EVT VT,
3611 unsigned NumElts = VT.getVectorNumElements();
3613 assert((VT.is128BitVector() || VT.is256BitVector()) &&
3614 "Unsupported vector type for unpckh");
3616 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8 &&
3617 (!HasAVX2 || (NumElts != 16 && NumElts != 32)))
3620 // For 256-bit i64/f64, use MOVDDUPY instead, so reject the matching pattern
3621 // FIXME: Need a better way to get rid of this, there's no latency difference
3622 // between UNPCKLPD and MOVDDUP, the later should always be checked first and
3623 // the former later. We should also remove the "_undef" special mask.
3624 if (NumElts == 4 && VT.getSizeInBits() == 256)
3627 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
3628 // independently on 128-bit lanes.
3629 unsigned NumLanes = VT.getSizeInBits()/128;
3630 unsigned NumLaneElts = NumElts/NumLanes;
3632 for (unsigned l = 0; l != NumLanes; ++l) {
3633 for (unsigned i = l*NumLaneElts, j = l*NumLaneElts;
3634 i != (l+1)*NumLaneElts;
3637 int BitI1 = Mask[i+1];
3639 if (!isUndefOrEqual(BitI, j))
3641 if (!isUndefOrEqual(BitI1, j))
3649 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
3650 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
3652 static bool isUNPCKH_v_undef_Mask(ArrayRef<int> Mask, EVT VT, bool HasAVX2) {
3653 unsigned NumElts = VT.getVectorNumElements();
3655 assert((VT.is128BitVector() || VT.is256BitVector()) &&
3656 "Unsupported vector type for unpckh");
3658 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8 &&
3659 (!HasAVX2 || (NumElts != 16 && NumElts != 32)))
3662 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
3663 // independently on 128-bit lanes.
3664 unsigned NumLanes = VT.getSizeInBits()/128;
3665 unsigned NumLaneElts = NumElts/NumLanes;
3667 for (unsigned l = 0; l != NumLanes; ++l) {
3668 for (unsigned i = l*NumLaneElts, j = (l*NumLaneElts)+NumLaneElts/2;
3669 i != (l+1)*NumLaneElts; i += 2, ++j) {
3671 int BitI1 = Mask[i+1];
3672 if (!isUndefOrEqual(BitI, j))
3674 if (!isUndefOrEqual(BitI1, j))
3681 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
3682 /// specifies a shuffle of elements that is suitable for input to MOVSS,
3683 /// MOVSD, and MOVD, i.e. setting the lowest element.
3684 static bool isMOVLMask(ArrayRef<int> Mask, EVT VT) {
3685 if (VT.getVectorElementType().getSizeInBits() < 32)
3687 if (!VT.is128BitVector())
3690 unsigned NumElts = VT.getVectorNumElements();
3692 if (!isUndefOrEqual(Mask[0], NumElts))
3695 for (unsigned i = 1; i != NumElts; ++i)
3696 if (!isUndefOrEqual(Mask[i], i))
3702 /// isVPERM2X128Mask - Match 256-bit shuffles where the elements are considered
3703 /// as permutations between 128-bit chunks or halves. As an example: this
3705 /// vector_shuffle <4, 5, 6, 7, 12, 13, 14, 15>
3706 /// The first half comes from the second half of V1 and the second half from the
3707 /// the second half of V2.
3708 static bool isVPERM2X128Mask(ArrayRef<int> Mask, EVT VT, bool HasAVX) {
3709 if (!HasAVX || !VT.is256BitVector())
3712 // The shuffle result is divided into half A and half B. In total the two
3713 // sources have 4 halves, namely: C, D, E, F. The final values of A and
3714 // B must come from C, D, E or F.
3715 unsigned HalfSize = VT.getVectorNumElements()/2;
3716 bool MatchA = false, MatchB = false;
3718 // Check if A comes from one of C, D, E, F.
3719 for (unsigned Half = 0; Half != 4; ++Half) {
3720 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, Half*HalfSize)) {
3726 // Check if B comes from one of C, D, E, F.
3727 for (unsigned Half = 0; Half != 4; ++Half) {
3728 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, Half*HalfSize)) {
3734 return MatchA && MatchB;
3737 /// getShuffleVPERM2X128Immediate - Return the appropriate immediate to shuffle
3738 /// the specified VECTOR_MASK mask with VPERM2F128/VPERM2I128 instructions.
3739 static unsigned getShuffleVPERM2X128Immediate(ShuffleVectorSDNode *SVOp) {
3740 EVT VT = SVOp->getValueType(0);
3742 unsigned HalfSize = VT.getVectorNumElements()/2;
3744 unsigned FstHalf = 0, SndHalf = 0;
3745 for (unsigned i = 0; i < HalfSize; ++i) {
3746 if (SVOp->getMaskElt(i) > 0) {
3747 FstHalf = SVOp->getMaskElt(i)/HalfSize;
3751 for (unsigned i = HalfSize; i < HalfSize*2; ++i) {
3752 if (SVOp->getMaskElt(i) > 0) {
3753 SndHalf = SVOp->getMaskElt(i)/HalfSize;
3758 return (FstHalf | (SndHalf << 4));
3761 /// isVPERMILPMask - Return true if the specified VECTOR_SHUFFLE operand
3762 /// specifies a shuffle of elements that is suitable for input to VPERMILPD*.
3763 /// Note that VPERMIL mask matching is different depending whether theunderlying
3764 /// type is 32 or 64. In the VPERMILPS the high half of the mask should point
3765 /// to the same elements of the low, but to the higher half of the source.
3766 /// In VPERMILPD the two lanes could be shuffled independently of each other
3767 /// with the same restriction that lanes can't be crossed. Also handles PSHUFDY.
3768 static bool isVPERMILPMask(ArrayRef<int> Mask, EVT VT, bool HasAVX) {
3772 unsigned NumElts = VT.getVectorNumElements();
3773 // Only match 256-bit with 32/64-bit types
3774 if (VT.getSizeInBits() != 256 || (NumElts != 4 && NumElts != 8))
3777 unsigned NumLanes = VT.getSizeInBits()/128;
3778 unsigned LaneSize = NumElts/NumLanes;
3779 for (unsigned l = 0; l != NumElts; l += LaneSize) {
3780 for (unsigned i = 0; i != LaneSize; ++i) {
3781 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize))
3783 if (NumElts != 8 || l == 0)
3785 // VPERMILPS handling
3788 if (!isUndefOrEqual(Mask[i+l], Mask[i]+l))
3796 /// isCommutedMOVLMask - Returns true if the shuffle mask is except the reverse
3797 /// of what x86 movss want. X86 movs requires the lowest element to be lowest
3798 /// element of vector 2 and the other elements to come from vector 1 in order.
3799 static bool isCommutedMOVLMask(ArrayRef<int> Mask, EVT VT,
3800 bool V2IsSplat = false, bool V2IsUndef = false) {
3801 if (!VT.is128BitVector())
3804 unsigned NumOps = VT.getVectorNumElements();
3805 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16)
3808 if (!isUndefOrEqual(Mask[0], 0))
3811 for (unsigned i = 1; i != NumOps; ++i)
3812 if (!(isUndefOrEqual(Mask[i], i+NumOps) ||
3813 (V2IsUndef && isUndefOrInRange(Mask[i], NumOps, NumOps*2)) ||
3814 (V2IsSplat && isUndefOrEqual(Mask[i], NumOps))))
3820 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
3821 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
3822 /// Masks to match: <1, 1, 3, 3> or <1, 1, 3, 3, 5, 5, 7, 7>
3823 static bool isMOVSHDUPMask(ArrayRef<int> Mask, EVT VT,
3824 const X86Subtarget *Subtarget) {
3825 if (!Subtarget->hasSSE3())
3828 unsigned NumElems = VT.getVectorNumElements();
3830 if ((VT.getSizeInBits() == 128 && NumElems != 4) ||
3831 (VT.getSizeInBits() == 256 && NumElems != 8))
3834 // "i+1" is the value the indexed mask element must have
3835 for (unsigned i = 0; i != NumElems; i += 2)
3836 if (!isUndefOrEqual(Mask[i], i+1) ||
3837 !isUndefOrEqual(Mask[i+1], i+1))
3843 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
3844 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
3845 /// Masks to match: <0, 0, 2, 2> or <0, 0, 2, 2, 4, 4, 6, 6>
3846 static bool isMOVSLDUPMask(ArrayRef<int> Mask, EVT VT,
3847 const X86Subtarget *Subtarget) {
3848 if (!Subtarget->hasSSE3())
3851 unsigned NumElems = VT.getVectorNumElements();
3853 if ((VT.getSizeInBits() == 128 && NumElems != 4) ||
3854 (VT.getSizeInBits() == 256 && NumElems != 8))
3857 // "i" is the value the indexed mask element must have
3858 for (unsigned i = 0; i != NumElems; i += 2)
3859 if (!isUndefOrEqual(Mask[i], i) ||
3860 !isUndefOrEqual(Mask[i+1], i))
3866 /// isMOVDDUPYMask - Return true if the specified VECTOR_SHUFFLE operand
3867 /// specifies a shuffle of elements that is suitable for input to 256-bit
3868 /// version of MOVDDUP.
3869 static bool isMOVDDUPYMask(ArrayRef<int> Mask, EVT VT, bool HasAVX) {
3870 if (!HasAVX || !VT.is256BitVector())
3873 unsigned NumElts = VT.getVectorNumElements();
3877 for (unsigned i = 0; i != NumElts/2; ++i)
3878 if (!isUndefOrEqual(Mask[i], 0))
3880 for (unsigned i = NumElts/2; i != NumElts; ++i)
3881 if (!isUndefOrEqual(Mask[i], NumElts/2))
3886 /// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand
3887 /// specifies a shuffle of elements that is suitable for input to 128-bit
3888 /// version of MOVDDUP.
3889 static bool isMOVDDUPMask(ArrayRef<int> Mask, EVT VT) {
3890 if (!VT.is128BitVector())
3893 unsigned e = VT.getVectorNumElements() / 2;
3894 for (unsigned i = 0; i != e; ++i)
3895 if (!isUndefOrEqual(Mask[i], i))
3897 for (unsigned i = 0; i != e; ++i)
3898 if (!isUndefOrEqual(Mask[e+i], i))
3903 /// isVEXTRACTF128Index - Return true if the specified
3904 /// EXTRACT_SUBVECTOR operand specifies a vector extract that is
3905 /// suitable for input to VEXTRACTF128.
3906 bool X86::isVEXTRACTF128Index(SDNode *N) {
3907 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
3910 // The index should be aligned on a 128-bit boundary.
3912 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
3914 unsigned VL = N->getValueType(0).getVectorNumElements();
3915 unsigned VBits = N->getValueType(0).getSizeInBits();
3916 unsigned ElSize = VBits / VL;
3917 bool Result = (Index * ElSize) % 128 == 0;
3922 /// isVINSERTF128Index - Return true if the specified INSERT_SUBVECTOR
3923 /// operand specifies a subvector insert that is suitable for input to
3925 bool X86::isVINSERTF128Index(SDNode *N) {
3926 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
3929 // The index should be aligned on a 128-bit boundary.
3931 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
3933 unsigned VL = N->getValueType(0).getVectorNumElements();
3934 unsigned VBits = N->getValueType(0).getSizeInBits();
3935 unsigned ElSize = VBits / VL;
3936 bool Result = (Index * ElSize) % 128 == 0;
3941 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
3942 /// the specified VECTOR_SHUFFLE mask with PSHUF* and SHUFP* instructions.
3943 /// Handles 128-bit and 256-bit.
3944 static unsigned getShuffleSHUFImmediate(ShuffleVectorSDNode *N) {
3945 EVT VT = N->getValueType(0);
3947 assert((VT.is128BitVector() || VT.is256BitVector()) &&
3948 "Unsupported vector type for PSHUF/SHUFP");
3950 // Handle 128 and 256-bit vector lengths. AVX defines PSHUF/SHUFP to operate
3951 // independently on 128-bit lanes.
3952 unsigned NumElts = VT.getVectorNumElements();
3953 unsigned NumLanes = VT.getSizeInBits()/128;
3954 unsigned NumLaneElts = NumElts/NumLanes;
3956 assert((NumLaneElts == 2 || NumLaneElts == 4) &&
3957 "Only supports 2 or 4 elements per lane");
3959 unsigned Shift = (NumLaneElts == 4) ? 1 : 0;
3961 for (unsigned i = 0; i != NumElts; ++i) {
3962 int Elt = N->getMaskElt(i);
3963 if (Elt < 0) continue;
3964 Elt &= NumLaneElts - 1;
3965 unsigned ShAmt = (i << Shift) % 8;
3966 Mask |= Elt << ShAmt;
3972 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
3973 /// the specified VECTOR_SHUFFLE mask with the PSHUFHW instruction.
3974 static unsigned getShufflePSHUFHWImmediate(ShuffleVectorSDNode *N) {
3975 EVT VT = N->getValueType(0);
3977 assert((VT == MVT::v8i16 || VT == MVT::v16i16) &&
3978 "Unsupported vector type for PSHUFHW");
3980 unsigned NumElts = VT.getVectorNumElements();
3983 for (unsigned l = 0; l != NumElts; l += 8) {
3984 // 8 nodes per lane, but we only care about the last 4.
3985 for (unsigned i = 0; i < 4; ++i) {
3986 int Elt = N->getMaskElt(l+i+4);
3987 if (Elt < 0) continue;
3988 Elt &= 0x3; // only 2-bits.
3989 Mask |= Elt << (i * 2);
3996 /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
3997 /// the specified VECTOR_SHUFFLE mask with the PSHUFLW instruction.
3998 static unsigned getShufflePSHUFLWImmediate(ShuffleVectorSDNode *N) {
3999 EVT VT = N->getValueType(0);
4001 assert((VT == MVT::v8i16 || VT == MVT::v16i16) &&
4002 "Unsupported vector type for PSHUFHW");
4004 unsigned NumElts = VT.getVectorNumElements();
4007 for (unsigned l = 0; l != NumElts; l += 8) {
4008 // 8 nodes per lane, but we only care about the first 4.
4009 for (unsigned i = 0; i < 4; ++i) {
4010 int Elt = N->getMaskElt(l+i);
4011 if (Elt < 0) continue;
4012 Elt &= 0x3; // only 2-bits
4013 Mask |= Elt << (i * 2);
4020 /// getShufflePALIGNRImmediate - Return the appropriate immediate to shuffle
4021 /// the specified VECTOR_SHUFFLE mask with the PALIGNR instruction.
4022 static unsigned getShufflePALIGNRImmediate(ShuffleVectorSDNode *SVOp) {
4023 EVT VT = SVOp->getValueType(0);
4024 unsigned EltSize = VT.getVectorElementType().getSizeInBits() >> 3;
4026 unsigned NumElts = VT.getVectorNumElements();
4027 unsigned NumLanes = VT.getSizeInBits()/128;
4028 unsigned NumLaneElts = NumElts/NumLanes;
4032 for (i = 0; i != NumElts; ++i) {
4033 Val = SVOp->getMaskElt(i);
4037 if (Val >= (int)NumElts)
4038 Val -= NumElts - NumLaneElts;
4040 assert(Val - i > 0 && "PALIGNR imm should be positive");
4041 return (Val - i) * EltSize;
4044 /// getExtractVEXTRACTF128Immediate - Return the appropriate immediate
4045 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF128
4047 unsigned X86::getExtractVEXTRACTF128Immediate(SDNode *N) {
4048 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4049 llvm_unreachable("Illegal extract subvector for VEXTRACTF128");
4052 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4054 EVT VecVT = N->getOperand(0).getValueType();
4055 EVT ElVT = VecVT.getVectorElementType();
4057 unsigned NumElemsPerChunk = 128 / ElVT.getSizeInBits();
4058 return Index / NumElemsPerChunk;
4061 /// getInsertVINSERTF128Immediate - Return the appropriate immediate
4062 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF128
4064 unsigned X86::getInsertVINSERTF128Immediate(SDNode *N) {
4065 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4066 llvm_unreachable("Illegal insert subvector for VINSERTF128");
4069 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4071 EVT VecVT = N->getValueType(0);
4072 EVT ElVT = VecVT.getVectorElementType();
4074 unsigned NumElemsPerChunk = 128 / ElVT.getSizeInBits();
4075 return Index / NumElemsPerChunk;
4078 /// getShuffleCLImmediate - Return the appropriate immediate to shuffle
4079 /// the specified VECTOR_SHUFFLE mask with VPERMQ and VPERMPD instructions.
4080 /// Handles 256-bit.
4081 static unsigned getShuffleCLImmediate(ShuffleVectorSDNode *N) {
4082 EVT VT = N->getValueType(0);
4084 unsigned NumElts = VT.getVectorNumElements();
4086 assert((VT.is256BitVector() && NumElts == 4) &&
4087 "Unsupported vector type for VPERMQ/VPERMPD");
4090 for (unsigned i = 0; i != NumElts; ++i) {
4091 int Elt = N->getMaskElt(i);
4094 Mask |= Elt << (i*2);
4099 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
4101 bool X86::isZeroNode(SDValue Elt) {
4102 return ((isa<ConstantSDNode>(Elt) &&
4103 cast<ConstantSDNode>(Elt)->isNullValue()) ||
4104 (isa<ConstantFPSDNode>(Elt) &&
4105 cast<ConstantFPSDNode>(Elt)->getValueAPF().isPosZero()));
4108 /// CommuteVectorShuffle - Swap vector_shuffle operands as well as values in
4109 /// their permute mask.
4110 static SDValue CommuteVectorShuffle(ShuffleVectorSDNode *SVOp,
4111 SelectionDAG &DAG) {
4112 EVT VT = SVOp->getValueType(0);
4113 unsigned NumElems = VT.getVectorNumElements();
4114 SmallVector<int, 8> MaskVec;
4116 for (unsigned i = 0; i != NumElems; ++i) {
4117 int Idx = SVOp->getMaskElt(i);
4119 if (Idx < (int)NumElems)
4124 MaskVec.push_back(Idx);
4126 return DAG.getVectorShuffle(VT, SVOp->getDebugLoc(), SVOp->getOperand(1),
4127 SVOp->getOperand(0), &MaskVec[0]);
4130 /// ShouldXformToMOVHLPS - Return true if the node should be transformed to
4131 /// match movhlps. The lower half elements should come from upper half of
4132 /// V1 (and in order), and the upper half elements should come from the upper
4133 /// half of V2 (and in order).
4134 static bool ShouldXformToMOVHLPS(ArrayRef<int> Mask, EVT VT) {
4135 if (!VT.is128BitVector())
4137 if (VT.getVectorNumElements() != 4)
4139 for (unsigned i = 0, e = 2; i != e; ++i)
4140 if (!isUndefOrEqual(Mask[i], i+2))
4142 for (unsigned i = 2; i != 4; ++i)
4143 if (!isUndefOrEqual(Mask[i], i+4))
4148 /// isScalarLoadToVector - Returns true if the node is a scalar load that
4149 /// is promoted to a vector. It also returns the LoadSDNode by reference if
4151 static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = NULL) {
4152 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR)
4154 N = N->getOperand(0).getNode();
4155 if (!ISD::isNON_EXTLoad(N))
4158 *LD = cast<LoadSDNode>(N);
4162 // Test whether the given value is a vector value which will be legalized
4164 static bool WillBeConstantPoolLoad(SDNode *N) {
4165 if (N->getOpcode() != ISD::BUILD_VECTOR)
4168 // Check for any non-constant elements.
4169 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
4170 switch (N->getOperand(i).getNode()->getOpcode()) {
4172 case ISD::ConstantFP:
4179 // Vectors of all-zeros and all-ones are materialized with special
4180 // instructions rather than being loaded.
4181 return !ISD::isBuildVectorAllZeros(N) &&
4182 !ISD::isBuildVectorAllOnes(N);
4185 /// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to
4186 /// match movlp{s|d}. The lower half elements should come from lower half of
4187 /// V1 (and in order), and the upper half elements should come from the upper
4188 /// half of V2 (and in order). And since V1 will become the source of the
4189 /// MOVLP, it must be either a vector load or a scalar load to vector.
4190 static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2,
4191 ArrayRef<int> Mask, EVT VT) {
4192 if (!VT.is128BitVector())
4195 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1))
4197 // Is V2 is a vector load, don't do this transformation. We will try to use
4198 // load folding shufps op.
4199 if (ISD::isNON_EXTLoad(V2) || WillBeConstantPoolLoad(V2))
4202 unsigned NumElems = VT.getVectorNumElements();
4204 if (NumElems != 2 && NumElems != 4)
4206 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4207 if (!isUndefOrEqual(Mask[i], i))
4209 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i)
4210 if (!isUndefOrEqual(Mask[i], i+NumElems))
4215 /// isSplatVector - Returns true if N is a BUILD_VECTOR node whose elements are
4217 static bool isSplatVector(SDNode *N) {
4218 if (N->getOpcode() != ISD::BUILD_VECTOR)
4221 SDValue SplatValue = N->getOperand(0);
4222 for (unsigned i = 1, e = N->getNumOperands(); i != e; ++i)
4223 if (N->getOperand(i) != SplatValue)
4228 /// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
4229 /// to an zero vector.
4230 /// FIXME: move to dag combiner / method on ShuffleVectorSDNode
4231 static bool isZeroShuffle(ShuffleVectorSDNode *N) {
4232 SDValue V1 = N->getOperand(0);
4233 SDValue V2 = N->getOperand(1);
4234 unsigned NumElems = N->getValueType(0).getVectorNumElements();
4235 for (unsigned i = 0; i != NumElems; ++i) {
4236 int Idx = N->getMaskElt(i);
4237 if (Idx >= (int)NumElems) {
4238 unsigned Opc = V2.getOpcode();
4239 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode()))
4241 if (Opc != ISD::BUILD_VECTOR ||
4242 !X86::isZeroNode(V2.getOperand(Idx-NumElems)))
4244 } else if (Idx >= 0) {
4245 unsigned Opc = V1.getOpcode();
4246 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode()))
4248 if (Opc != ISD::BUILD_VECTOR ||
4249 !X86::isZeroNode(V1.getOperand(Idx)))
4256 /// getZeroVector - Returns a vector of specified type with all zero elements.
4258 static SDValue getZeroVector(EVT VT, const X86Subtarget *Subtarget,
4259 SelectionDAG &DAG, DebugLoc dl) {
4260 assert(VT.isVector() && "Expected a vector type");
4261 unsigned Size = VT.getSizeInBits();
4263 // Always build SSE zero vectors as <4 x i32> bitcasted
4264 // to their dest type. This ensures they get CSE'd.
4266 if (Size == 128) { // SSE
4267 if (Subtarget->hasSSE2()) { // SSE2
4268 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
4269 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4271 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
4272 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
4274 } else if (Size == 256) { // AVX
4275 if (Subtarget->hasAVX2()) { // AVX2
4276 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
4277 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4278 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops, 8);
4280 // 256-bit logic and arithmetic instructions in AVX are all
4281 // floating-point, no support for integer ops. Emit fp zeroed vectors.
4282 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
4283 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4284 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops, 8);
4287 llvm_unreachable("Unexpected vector type");
4289 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
4292 /// getOnesVector - Returns a vector of specified type with all bits set.
4293 /// Always build ones vectors as <4 x i32> or <8 x i32>. For 256-bit types with
4294 /// no AVX2 supprt, use two <4 x i32> inserted in a <8 x i32> appropriately.
4295 /// Then bitcast to their original type, ensuring they get CSE'd.
4296 static SDValue getOnesVector(EVT VT, bool HasAVX2, SelectionDAG &DAG,
4298 assert(VT.isVector() && "Expected a vector type");
4299 unsigned Size = VT.getSizeInBits();
4301 SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32);
4304 if (HasAVX2) { // AVX2
4305 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4306 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops, 8);
4308 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4309 Vec = Concat128BitVectors(Vec, Vec, MVT::v8i32, 8, DAG, dl);
4311 } else if (Size == 128) {
4312 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4314 llvm_unreachable("Unexpected vector type");
4316 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
4319 /// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements
4320 /// that point to V2 points to its first element.
4321 static void NormalizeMask(SmallVectorImpl<int> &Mask, unsigned NumElems) {
4322 for (unsigned i = 0; i != NumElems; ++i) {
4323 if (Mask[i] > (int)NumElems) {
4329 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
4330 /// operation of specified width.
4331 static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
4333 unsigned NumElems = VT.getVectorNumElements();
4334 SmallVector<int, 8> Mask;
4335 Mask.push_back(NumElems);
4336 for (unsigned i = 1; i != NumElems; ++i)
4338 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4341 /// getUnpackl - Returns a vector_shuffle node for an unpackl operation.
4342 static SDValue getUnpackl(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
4344 unsigned NumElems = VT.getVectorNumElements();
4345 SmallVector<int, 8> Mask;
4346 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
4348 Mask.push_back(i + NumElems);
4350 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4353 /// getUnpackh - Returns a vector_shuffle node for an unpackh operation.
4354 static SDValue getUnpackh(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
4356 unsigned NumElems = VT.getVectorNumElements();
4357 SmallVector<int, 8> Mask;
4358 for (unsigned i = 0, Half = NumElems/2; i != Half; ++i) {
4359 Mask.push_back(i + Half);
4360 Mask.push_back(i + NumElems + Half);
4362 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4365 // PromoteSplati8i16 - All i16 and i8 vector types can't be used directly by
4366 // a generic shuffle instruction because the target has no such instructions.
4367 // Generate shuffles which repeat i16 and i8 several times until they can be
4368 // represented by v4f32 and then be manipulated by target suported shuffles.
4369 static SDValue PromoteSplati8i16(SDValue V, SelectionDAG &DAG, int &EltNo) {
4370 EVT VT = V.getValueType();
4371 int NumElems = VT.getVectorNumElements();
4372 DebugLoc dl = V.getDebugLoc();
4374 while (NumElems > 4) {
4375 if (EltNo < NumElems/2) {
4376 V = getUnpackl(DAG, dl, VT, V, V);
4378 V = getUnpackh(DAG, dl, VT, V, V);
4379 EltNo -= NumElems/2;
4386 /// getLegalSplat - Generate a legal splat with supported x86 shuffles
4387 static SDValue getLegalSplat(SelectionDAG &DAG, SDValue V, int EltNo) {
4388 EVT VT = V.getValueType();
4389 DebugLoc dl = V.getDebugLoc();
4390 unsigned Size = VT.getSizeInBits();
4393 V = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V);
4394 int SplatMask[4] = { EltNo, EltNo, EltNo, EltNo };
4395 V = DAG.getVectorShuffle(MVT::v4f32, dl, V, DAG.getUNDEF(MVT::v4f32),
4397 } else if (Size == 256) {
4398 // To use VPERMILPS to splat scalars, the second half of indicies must
4399 // refer to the higher part, which is a duplication of the lower one,
4400 // because VPERMILPS can only handle in-lane permutations.
4401 int SplatMask[8] = { EltNo, EltNo, EltNo, EltNo,
4402 EltNo+4, EltNo+4, EltNo+4, EltNo+4 };
4404 V = DAG.getNode(ISD::BITCAST, dl, MVT::v8f32, V);
4405 V = DAG.getVectorShuffle(MVT::v8f32, dl, V, DAG.getUNDEF(MVT::v8f32),
4408 llvm_unreachable("Vector size not supported");
4410 return DAG.getNode(ISD::BITCAST, dl, VT, V);
4413 /// PromoteSplat - Splat is promoted to target supported vector shuffles.
4414 static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG) {
4415 EVT SrcVT = SV->getValueType(0);
4416 SDValue V1 = SV->getOperand(0);
4417 DebugLoc dl = SV->getDebugLoc();
4419 int EltNo = SV->getSplatIndex();
4420 int NumElems = SrcVT.getVectorNumElements();
4421 unsigned Size = SrcVT.getSizeInBits();
4423 assert(((Size == 128 && NumElems > 4) || Size == 256) &&
4424 "Unknown how to promote splat for type");
4426 // Extract the 128-bit part containing the splat element and update
4427 // the splat element index when it refers to the higher register.
4429 V1 = Extract128BitVector(V1, EltNo, DAG, dl);
4430 if (EltNo >= NumElems/2)
4431 EltNo -= NumElems/2;
4434 // All i16 and i8 vector types can't be used directly by a generic shuffle
4435 // instruction because the target has no such instruction. Generate shuffles
4436 // which repeat i16 and i8 several times until they fit in i32, and then can
4437 // be manipulated by target suported shuffles.
4438 EVT EltVT = SrcVT.getVectorElementType();
4439 if (EltVT == MVT::i8 || EltVT == MVT::i16)
4440 V1 = PromoteSplati8i16(V1, DAG, EltNo);
4442 // Recreate the 256-bit vector and place the same 128-bit vector
4443 // into the low and high part. This is necessary because we want
4444 // to use VPERM* to shuffle the vectors
4446 V1 = DAG.getNode(ISD::CONCAT_VECTORS, dl, SrcVT, V1, V1);
4449 return getLegalSplat(DAG, V1, EltNo);
4452 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
4453 /// vector of zero or undef vector. This produces a shuffle where the low
4454 /// element of V2 is swizzled into the zero/undef vector, landing at element
4455 /// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
4456 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
4458 const X86Subtarget *Subtarget,
4459 SelectionDAG &DAG) {
4460 EVT VT = V2.getValueType();
4462 ? getZeroVector(VT, Subtarget, DAG, V2.getDebugLoc()) : DAG.getUNDEF(VT);
4463 unsigned NumElems = VT.getVectorNumElements();
4464 SmallVector<int, 16> MaskVec;
4465 for (unsigned i = 0; i != NumElems; ++i)
4466 // If this is the insertion idx, put the low elt of V2 here.
4467 MaskVec.push_back(i == Idx ? NumElems : i);
4468 return DAG.getVectorShuffle(VT, V2.getDebugLoc(), V1, V2, &MaskVec[0]);
4471 /// getTargetShuffleMask - Calculates the shuffle mask corresponding to the
4472 /// target specific opcode. Returns true if the Mask could be calculated.
4473 /// Sets IsUnary to true if only uses one source.
4474 static bool getTargetShuffleMask(SDNode *N, MVT VT,
4475 SmallVectorImpl<int> &Mask, bool &IsUnary) {
4476 unsigned NumElems = VT.getVectorNumElements();
4480 switch(N->getOpcode()) {
4482 ImmN = N->getOperand(N->getNumOperands()-1);
4483 DecodeSHUFPMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4485 case X86ISD::UNPCKH:
4486 DecodeUNPCKHMask(VT, Mask);
4488 case X86ISD::UNPCKL:
4489 DecodeUNPCKLMask(VT, Mask);
4491 case X86ISD::MOVHLPS:
4492 DecodeMOVHLPSMask(NumElems, Mask);
4494 case X86ISD::MOVLHPS:
4495 DecodeMOVLHPSMask(NumElems, Mask);
4497 case X86ISD::PSHUFD:
4498 case X86ISD::VPERMILP:
4499 ImmN = N->getOperand(N->getNumOperands()-1);
4500 DecodePSHUFMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4503 case X86ISD::PSHUFHW:
4504 ImmN = N->getOperand(N->getNumOperands()-1);
4505 DecodePSHUFHWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4508 case X86ISD::PSHUFLW:
4509 ImmN = N->getOperand(N->getNumOperands()-1);
4510 DecodePSHUFLWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4513 case X86ISD::VPERMI:
4514 ImmN = N->getOperand(N->getNumOperands()-1);
4515 DecodeVPERMMask(cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4519 case X86ISD::MOVSD: {
4520 // The index 0 always comes from the first element of the second source,
4521 // this is why MOVSS and MOVSD are used in the first place. The other
4522 // elements come from the other positions of the first source vector
4523 Mask.push_back(NumElems);
4524 for (unsigned i = 1; i != NumElems; ++i) {
4529 case X86ISD::VPERM2X128:
4530 ImmN = N->getOperand(N->getNumOperands()-1);
4531 DecodeVPERM2X128Mask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4532 if (Mask.empty()) return false;
4534 case X86ISD::MOVDDUP:
4535 case X86ISD::MOVLHPD:
4536 case X86ISD::MOVLPD:
4537 case X86ISD::MOVLPS:
4538 case X86ISD::MOVSHDUP:
4539 case X86ISD::MOVSLDUP:
4540 case X86ISD::PALIGN:
4541 // Not yet implemented
4543 default: llvm_unreachable("unknown target shuffle node");
4549 /// getShuffleScalarElt - Returns the scalar element that will make up the ith
4550 /// element of the result of the vector shuffle.
4551 static SDValue getShuffleScalarElt(SDNode *N, unsigned Index, SelectionDAG &DAG,
4554 return SDValue(); // Limit search depth.
4556 SDValue V = SDValue(N, 0);
4557 EVT VT = V.getValueType();
4558 unsigned Opcode = V.getOpcode();
4560 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars.
4561 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) {
4562 int Elt = SV->getMaskElt(Index);
4565 return DAG.getUNDEF(VT.getVectorElementType());
4567 unsigned NumElems = VT.getVectorNumElements();
4568 SDValue NewV = (Elt < (int)NumElems) ? SV->getOperand(0)
4569 : SV->getOperand(1);
4570 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG, Depth+1);
4573 // Recurse into target specific vector shuffles to find scalars.
4574 if (isTargetShuffle(Opcode)) {
4575 MVT ShufVT = V.getValueType().getSimpleVT();
4576 unsigned NumElems = ShufVT.getVectorNumElements();
4577 SmallVector<int, 16> ShuffleMask;
4581 if (!getTargetShuffleMask(N, ShufVT, ShuffleMask, IsUnary))
4584 int Elt = ShuffleMask[Index];
4586 return DAG.getUNDEF(ShufVT.getVectorElementType());
4588 SDValue NewV = (Elt < (int)NumElems) ? N->getOperand(0)
4590 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG,
4594 // Actual nodes that may contain scalar elements
4595 if (Opcode == ISD::BITCAST) {
4596 V = V.getOperand(0);
4597 EVT SrcVT = V.getValueType();
4598 unsigned NumElems = VT.getVectorNumElements();
4600 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems)
4604 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR)
4605 return (Index == 0) ? V.getOperand(0)
4606 : DAG.getUNDEF(VT.getVectorElementType());
4608 if (V.getOpcode() == ISD::BUILD_VECTOR)
4609 return V.getOperand(Index);
4614 /// getNumOfConsecutiveZeros - Return the number of elements of a vector
4615 /// shuffle operation which come from a consecutively from a zero. The
4616 /// search can start in two different directions, from left or right.
4618 unsigned getNumOfConsecutiveZeros(ShuffleVectorSDNode *SVOp, unsigned NumElems,
4619 bool ZerosFromLeft, SelectionDAG &DAG) {
4621 for (i = 0; i != NumElems; ++i) {
4622 unsigned Index = ZerosFromLeft ? i : NumElems-i-1;
4623 SDValue Elt = getShuffleScalarElt(SVOp, Index, DAG, 0);
4624 if (!(Elt.getNode() &&
4625 (Elt.getOpcode() == ISD::UNDEF || X86::isZeroNode(Elt))))
4632 /// isShuffleMaskConsecutive - Check if the shuffle mask indicies [MaskI, MaskE)
4633 /// correspond consecutively to elements from one of the vector operands,
4634 /// starting from its index OpIdx. Also tell OpNum which source vector operand.
4636 bool isShuffleMaskConsecutive(ShuffleVectorSDNode *SVOp,
4637 unsigned MaskI, unsigned MaskE, unsigned OpIdx,
4638 unsigned NumElems, unsigned &OpNum) {
4639 bool SeenV1 = false;
4640 bool SeenV2 = false;
4642 for (unsigned i = MaskI; i != MaskE; ++i, ++OpIdx) {
4643 int Idx = SVOp->getMaskElt(i);
4644 // Ignore undef indicies
4648 if (Idx < (int)NumElems)
4653 // Only accept consecutive elements from the same vector
4654 if ((Idx % NumElems != OpIdx) || (SeenV1 && SeenV2))
4658 OpNum = SeenV1 ? 0 : 1;
4662 /// isVectorShiftRight - Returns true if the shuffle can be implemented as a
4663 /// logical left shift of a vector.
4664 static bool isVectorShiftRight(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
4665 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
4666 unsigned NumElems = SVOp->getValueType(0).getVectorNumElements();
4667 unsigned NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems,
4668 false /* check zeros from right */, DAG);
4674 // Considering the elements in the mask that are not consecutive zeros,
4675 // check if they consecutively come from only one of the source vectors.
4677 // V1 = {X, A, B, C} 0
4679 // vector_shuffle V1, V2 <1, 2, 3, X>
4681 if (!isShuffleMaskConsecutive(SVOp,
4682 0, // Mask Start Index
4683 NumElems-NumZeros, // Mask End Index(exclusive)
4684 NumZeros, // Where to start looking in the src vector
4685 NumElems, // Number of elements in vector
4686 OpSrc)) // Which source operand ?
4691 ShVal = SVOp->getOperand(OpSrc);
4695 /// isVectorShiftLeft - Returns true if the shuffle can be implemented as a
4696 /// logical left shift of a vector.
4697 static bool isVectorShiftLeft(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
4698 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
4699 unsigned NumElems = SVOp->getValueType(0).getVectorNumElements();
4700 unsigned NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems,
4701 true /* check zeros from left */, DAG);
4707 // Considering the elements in the mask that are not consecutive zeros,
4708 // check if they consecutively come from only one of the source vectors.
4710 // 0 { A, B, X, X } = V2
4712 // vector_shuffle V1, V2 <X, X, 4, 5>
4714 if (!isShuffleMaskConsecutive(SVOp,
4715 NumZeros, // Mask Start Index
4716 NumElems, // Mask End Index(exclusive)
4717 0, // Where to start looking in the src vector
4718 NumElems, // Number of elements in vector
4719 OpSrc)) // Which source operand ?
4724 ShVal = SVOp->getOperand(OpSrc);
4728 /// isVectorShift - Returns true if the shuffle can be implemented as a
4729 /// logical left or right shift of a vector.
4730 static bool isVectorShift(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
4731 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
4732 // Although the logic below support any bitwidth size, there are no
4733 // shift instructions which handle more than 128-bit vectors.
4734 if (!SVOp->getValueType(0).is128BitVector())
4737 if (isVectorShiftLeft(SVOp, DAG, isLeft, ShVal, ShAmt) ||
4738 isVectorShiftRight(SVOp, DAG, isLeft, ShVal, ShAmt))
4744 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
4746 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
4747 unsigned NumNonZero, unsigned NumZero,
4749 const X86Subtarget* Subtarget,
4750 const TargetLowering &TLI) {
4754 DebugLoc dl = Op.getDebugLoc();
4757 for (unsigned i = 0; i < 16; ++i) {
4758 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
4759 if (ThisIsNonZero && First) {
4761 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
4763 V = DAG.getUNDEF(MVT::v8i16);
4768 SDValue ThisElt(0, 0), LastElt(0, 0);
4769 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
4770 if (LastIsNonZero) {
4771 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
4772 MVT::i16, Op.getOperand(i-1));
4774 if (ThisIsNonZero) {
4775 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
4776 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
4777 ThisElt, DAG.getConstant(8, MVT::i8));
4779 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
4783 if (ThisElt.getNode())
4784 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
4785 DAG.getIntPtrConstant(i/2));
4789 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V);
4792 /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
4794 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
4795 unsigned NumNonZero, unsigned NumZero,
4797 const X86Subtarget* Subtarget,
4798 const TargetLowering &TLI) {
4802 DebugLoc dl = Op.getDebugLoc();
4805 for (unsigned i = 0; i < 8; ++i) {
4806 bool isNonZero = (NonZeros & (1 << i)) != 0;
4810 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
4812 V = DAG.getUNDEF(MVT::v8i16);
4815 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
4816 MVT::v8i16, V, Op.getOperand(i),
4817 DAG.getIntPtrConstant(i));
4824 /// getVShift - Return a vector logical shift node.
4826 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
4827 unsigned NumBits, SelectionDAG &DAG,
4828 const TargetLowering &TLI, DebugLoc dl) {
4829 assert(VT.is128BitVector() && "Unknown type for VShift");
4830 EVT ShVT = MVT::v2i64;
4831 unsigned Opc = isLeft ? X86ISD::VSHLDQ : X86ISD::VSRLDQ;
4832 SrcOp = DAG.getNode(ISD::BITCAST, dl, ShVT, SrcOp);
4833 return DAG.getNode(ISD::BITCAST, dl, VT,
4834 DAG.getNode(Opc, dl, ShVT, SrcOp,
4835 DAG.getConstant(NumBits,
4836 TLI.getShiftAmountTy(SrcOp.getValueType()))));
4840 X86TargetLowering::LowerAsSplatVectorLoad(SDValue SrcOp, EVT VT, DebugLoc dl,
4841 SelectionDAG &DAG) const {
4843 // Check if the scalar load can be widened into a vector load. And if
4844 // the address is "base + cst" see if the cst can be "absorbed" into
4845 // the shuffle mask.
4846 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) {
4847 SDValue Ptr = LD->getBasePtr();
4848 if (!ISD::isNormalLoad(LD) || LD->isVolatile())
4850 EVT PVT = LD->getValueType(0);
4851 if (PVT != MVT::i32 && PVT != MVT::f32)
4856 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) {
4857 FI = FINode->getIndex();
4859 } else if (DAG.isBaseWithConstantOffset(Ptr) &&
4860 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
4861 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
4862 Offset = Ptr.getConstantOperandVal(1);
4863 Ptr = Ptr.getOperand(0);
4868 // FIXME: 256-bit vector instructions don't require a strict alignment,
4869 // improve this code to support it better.
4870 unsigned RequiredAlign = VT.getSizeInBits()/8;
4871 SDValue Chain = LD->getChain();
4872 // Make sure the stack object alignment is at least 16 or 32.
4873 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
4874 if (DAG.InferPtrAlignment(Ptr) < RequiredAlign) {
4875 if (MFI->isFixedObjectIndex(FI)) {
4876 // Can't change the alignment. FIXME: It's possible to compute
4877 // the exact stack offset and reference FI + adjust offset instead.
4878 // If someone *really* cares about this. That's the way to implement it.
4881 MFI->setObjectAlignment(FI, RequiredAlign);
4885 // (Offset % 16 or 32) must be multiple of 4. Then address is then
4886 // Ptr + (Offset & ~15).
4889 if ((Offset % RequiredAlign) & 3)
4891 int64_t StartOffset = Offset & ~(RequiredAlign-1);
4893 Ptr = DAG.getNode(ISD::ADD, Ptr.getDebugLoc(), Ptr.getValueType(),
4894 Ptr,DAG.getConstant(StartOffset, Ptr.getValueType()));
4896 int EltNo = (Offset - StartOffset) >> 2;
4897 unsigned NumElems = VT.getVectorNumElements();
4899 EVT NVT = EVT::getVectorVT(*DAG.getContext(), PVT, NumElems);
4900 SDValue V1 = DAG.getLoad(NVT, dl, Chain, Ptr,
4901 LD->getPointerInfo().getWithOffset(StartOffset),
4902 false, false, false, 0);
4904 SmallVector<int, 8> Mask;
4905 for (unsigned i = 0; i != NumElems; ++i)
4906 Mask.push_back(EltNo);
4908 return DAG.getVectorShuffle(NVT, dl, V1, DAG.getUNDEF(NVT), &Mask[0]);
4914 /// EltsFromConsecutiveLoads - Given the initializing elements 'Elts' of a
4915 /// vector of type 'VT', see if the elements can be replaced by a single large
4916 /// load which has the same value as a build_vector whose operands are 'elts'.
4918 /// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a
4920 /// FIXME: we'd also like to handle the case where the last elements are zero
4921 /// rather than undef via VZEXT_LOAD, but we do not detect that case today.
4922 /// There's even a handy isZeroNode for that purpose.
4923 static SDValue EltsFromConsecutiveLoads(EVT VT, SmallVectorImpl<SDValue> &Elts,
4924 DebugLoc &DL, SelectionDAG &DAG) {
4925 EVT EltVT = VT.getVectorElementType();
4926 unsigned NumElems = Elts.size();
4928 LoadSDNode *LDBase = NULL;
4929 unsigned LastLoadedElt = -1U;
4931 // For each element in the initializer, see if we've found a load or an undef.
4932 // If we don't find an initial load element, or later load elements are
4933 // non-consecutive, bail out.
4934 for (unsigned i = 0; i < NumElems; ++i) {
4935 SDValue Elt = Elts[i];
4937 if (!Elt.getNode() ||
4938 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
4941 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
4943 LDBase = cast<LoadSDNode>(Elt.getNode());
4947 if (Elt.getOpcode() == ISD::UNDEF)
4950 LoadSDNode *LD = cast<LoadSDNode>(Elt);
4951 if (!DAG.isConsecutiveLoad(LD, LDBase, EltVT.getSizeInBits()/8, i))
4956 // If we have found an entire vector of loads and undefs, then return a large
4957 // load of the entire vector width starting at the base pointer. If we found
4958 // consecutive loads for the low half, generate a vzext_load node.
4959 if (LastLoadedElt == NumElems - 1) {
4960 if (DAG.InferPtrAlignment(LDBase->getBasePtr()) >= 16)
4961 return DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
4962 LDBase->getPointerInfo(),
4963 LDBase->isVolatile(), LDBase->isNonTemporal(),
4964 LDBase->isInvariant(), 0);
4965 return DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
4966 LDBase->getPointerInfo(),
4967 LDBase->isVolatile(), LDBase->isNonTemporal(),
4968 LDBase->isInvariant(), LDBase->getAlignment());
4970 if (NumElems == 4 && LastLoadedElt == 1 &&
4971 DAG.getTargetLoweringInfo().isTypeLegal(MVT::v2i64)) {
4972 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
4973 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() };
4975 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys, Ops, 2, MVT::i64,
4976 LDBase->getPointerInfo(),
4977 LDBase->getAlignment(),
4978 false/*isVolatile*/, true/*ReadMem*/,
4980 return DAG.getNode(ISD::BITCAST, DL, VT, ResNode);
4985 /// LowerVectorBroadcast - Attempt to use the vbroadcast instruction
4986 /// to generate a splat value for the following cases:
4987 /// 1. A splat BUILD_VECTOR which uses a single scalar load, or a constant.
4988 /// 2. A splat shuffle which uses a scalar_to_vector node which comes from
4989 /// a scalar load, or a constant.
4990 /// The VBROADCAST node is returned when a pattern is found,
4991 /// or SDValue() otherwise.
4993 X86TargetLowering::LowerVectorBroadcast(SDValue &Op, SelectionDAG &DAG) const {
4994 if (!Subtarget->hasAVX())
4997 EVT VT = Op.getValueType();
4998 DebugLoc dl = Op.getDebugLoc();
5000 assert((VT.is128BitVector() || VT.is256BitVector()) &&
5001 "Unsupported vector type for broadcast.");
5006 switch (Op.getOpcode()) {
5008 // Unknown pattern found.
5011 case ISD::BUILD_VECTOR: {
5012 // The BUILD_VECTOR node must be a splat.
5013 if (!isSplatVector(Op.getNode()))
5016 Ld = Op.getOperand(0);
5017 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
5018 Ld.getOpcode() == ISD::ConstantFP);
5020 // The suspected load node has several users. Make sure that all
5021 // of its users are from the BUILD_VECTOR node.
5022 // Constants may have multiple users.
5023 if (!ConstSplatVal && !Ld->hasNUsesOfValue(VT.getVectorNumElements(), 0))
5028 case ISD::VECTOR_SHUFFLE: {
5029 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
5031 // Shuffles must have a splat mask where the first element is
5033 if ((!SVOp->isSplat()) || SVOp->getMaskElt(0) != 0)
5036 SDValue Sc = Op.getOperand(0);
5037 if (Sc.getOpcode() != ISD::SCALAR_TO_VECTOR &&
5038 Sc.getOpcode() != ISD::BUILD_VECTOR) {
5040 if (!Subtarget->hasAVX2())
5043 // Use the register form of the broadcast instruction available on AVX2.
5044 if (VT.is256BitVector())
5045 Sc = Extract128BitVector(Sc, 0, DAG, dl);
5046 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Sc);
5049 Ld = Sc.getOperand(0);
5050 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
5051 Ld.getOpcode() == ISD::ConstantFP);
5053 // The scalar_to_vector node and the suspected
5054 // load node must have exactly one user.
5055 // Constants may have multiple users.
5056 if (!ConstSplatVal && (!Sc.hasOneUse() || !Ld.hasOneUse()))
5062 bool Is256 = VT.is256BitVector();
5064 // Handle the broadcasting a single constant scalar from the constant pool
5065 // into a vector. On Sandybridge it is still better to load a constant vector
5066 // from the constant pool and not to broadcast it from a scalar.
5067 if (ConstSplatVal && Subtarget->hasAVX2()) {
5068 EVT CVT = Ld.getValueType();
5069 assert(!CVT.isVector() && "Must not broadcast a vector type");
5070 unsigned ScalarSize = CVT.getSizeInBits();
5072 if (ScalarSize == 32 || (Is256 && ScalarSize == 64)) {
5073 const Constant *C = 0;
5074 if (ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Ld))
5075 C = CI->getConstantIntValue();
5076 else if (ConstantFPSDNode *CF = dyn_cast<ConstantFPSDNode>(Ld))
5077 C = CF->getConstantFPValue();
5079 assert(C && "Invalid constant type");
5081 SDValue CP = DAG.getConstantPool(C, getPointerTy());
5082 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
5083 Ld = DAG.getLoad(CVT, dl, DAG.getEntryNode(), CP,
5084 MachinePointerInfo::getConstantPool(),
5085 false, false, false, Alignment);
5087 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5091 bool IsLoad = ISD::isNormalLoad(Ld.getNode());
5092 unsigned ScalarSize = Ld.getValueType().getSizeInBits();
5094 // Handle AVX2 in-register broadcasts.
5095 if (!IsLoad && Subtarget->hasAVX2() &&
5096 (ScalarSize == 32 || (Is256 && ScalarSize == 64)))
5097 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5099 // The scalar source must be a normal load.
5103 if (ScalarSize == 32 || (Is256 && ScalarSize == 64))
5104 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5106 // The integer check is needed for the 64-bit into 128-bit so it doesn't match
5107 // double since there is no vbroadcastsd xmm
5108 if (Subtarget->hasAVX2() && Ld.getValueType().isInteger()) {
5109 if (ScalarSize == 8 || ScalarSize == 16 || ScalarSize == 64)
5110 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5113 // Unsupported broadcast.
5117 // LowerVectorFpExtend - Recognize the scalarized FP_EXTEND from v2f32 to v2f64
5118 // and convert it into X86ISD::VFPEXT due to the current ISD::FP_EXTEND has the
5119 // constraint of matching input/output vector elements.
5121 X86TargetLowering::LowerVectorFpExtend(SDValue &Op, SelectionDAG &DAG) const {
5122 DebugLoc DL = Op.getDebugLoc();
5123 SDNode *N = Op.getNode();
5124 EVT VT = Op.getValueType();
5125 unsigned NumElts = Op.getNumOperands();
5127 // Check supported types and sub-targets.
5129 // Only v2f32 -> v2f64 needs special handling.
5130 if (VT != MVT::v2f64 || !Subtarget->hasSSE2())
5135 SmallVector<int, 8> Mask;
5136 EVT SrcVT = MVT::Other;
5138 // Check the patterns could be translated into X86vfpext.
5139 for (unsigned i = 0; i < NumElts; ++i) {
5140 SDValue In = N->getOperand(i);
5141 unsigned Opcode = In.getOpcode();
5143 // Skip if the element is undefined.
5144 if (Opcode == ISD::UNDEF) {
5149 // Quit if one of the elements is not defined from 'fpext'.
5150 if (Opcode != ISD::FP_EXTEND)
5153 // Check how the source of 'fpext' is defined.
5154 SDValue L2In = In.getOperand(0);
5155 EVT L2InVT = L2In.getValueType();
5157 // Check the original type
5158 if (SrcVT == MVT::Other)
5160 else if (SrcVT != L2InVT) // Quit if non-homogenous typed.
5163 // Check whether the value being 'fpext'ed is extracted from the same
5165 Opcode = L2In.getOpcode();
5167 // Quit if it's not extracted with a constant index.
5168 if (Opcode != ISD::EXTRACT_VECTOR_ELT ||
5169 !isa<ConstantSDNode>(L2In.getOperand(1)))
5172 SDValue ExtractedFromVec = L2In.getOperand(0);
5174 if (VecIn.getNode() == 0) {
5175 VecIn = ExtractedFromVec;
5176 VecInVT = ExtractedFromVec.getValueType();
5177 } else if (VecIn != ExtractedFromVec) // Quit if built from more than 1 vec.
5180 Mask.push_back(cast<ConstantSDNode>(L2In.getOperand(1))->getZExtValue());
5183 // Quit if all operands of BUILD_VECTOR are undefined.
5184 if (!VecIn.getNode())
5187 // Fill the remaining mask as undef.
5188 for (unsigned i = NumElts; i < VecInVT.getVectorNumElements(); ++i)
5191 return DAG.getNode(X86ISD::VFPEXT, DL, VT,
5192 DAG.getVectorShuffle(VecInVT, DL,
5193 VecIn, DAG.getUNDEF(VecInVT),
5198 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
5199 DebugLoc dl = Op.getDebugLoc();
5201 EVT VT = Op.getValueType();
5202 EVT ExtVT = VT.getVectorElementType();
5203 unsigned NumElems = Op.getNumOperands();
5205 // Vectors containing all zeros can be matched by pxor and xorps later
5206 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
5207 // Canonicalize this to <4 x i32> to 1) ensure the zero vectors are CSE'd
5208 // and 2) ensure that i64 scalars are eliminated on x86-32 hosts.
5209 if (VT == MVT::v4i32 || VT == MVT::v8i32)
5212 return getZeroVector(VT, Subtarget, DAG, dl);
5215 // Vectors containing all ones can be matched by pcmpeqd on 128-bit width
5216 // vectors or broken into v4i32 operations on 256-bit vectors. AVX2 can use
5217 // vpcmpeqd on 256-bit vectors.
5218 if (ISD::isBuildVectorAllOnes(Op.getNode())) {
5219 if (VT == MVT::v4i32 || (VT == MVT::v8i32 && Subtarget->hasAVX2()))
5222 return getOnesVector(VT, Subtarget->hasAVX2(), DAG, dl);
5225 SDValue Broadcast = LowerVectorBroadcast(Op, DAG);
5226 if (Broadcast.getNode())
5229 SDValue FpExt = LowerVectorFpExtend(Op, DAG);
5230 if (FpExt.getNode())
5233 unsigned EVTBits = ExtVT.getSizeInBits();
5235 unsigned NumZero = 0;
5236 unsigned NumNonZero = 0;
5237 unsigned NonZeros = 0;
5238 bool IsAllConstants = true;
5239 SmallSet<SDValue, 8> Values;
5240 for (unsigned i = 0; i < NumElems; ++i) {
5241 SDValue Elt = Op.getOperand(i);
5242 if (Elt.getOpcode() == ISD::UNDEF)
5245 if (Elt.getOpcode() != ISD::Constant &&
5246 Elt.getOpcode() != ISD::ConstantFP)
5247 IsAllConstants = false;
5248 if (X86::isZeroNode(Elt))
5251 NonZeros |= (1 << i);
5256 // All undef vector. Return an UNDEF. All zero vectors were handled above.
5257 if (NumNonZero == 0)
5258 return DAG.getUNDEF(VT);
5260 // Special case for single non-zero, non-undef, element.
5261 if (NumNonZero == 1) {
5262 unsigned Idx = CountTrailingZeros_32(NonZeros);
5263 SDValue Item = Op.getOperand(Idx);
5265 // If this is an insertion of an i64 value on x86-32, and if the top bits of
5266 // the value are obviously zero, truncate the value to i32 and do the
5267 // insertion that way. Only do this if the value is non-constant or if the
5268 // value is a constant being inserted into element 0. It is cheaper to do
5269 // a constant pool load than it is to do a movd + shuffle.
5270 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
5271 (!IsAllConstants || Idx == 0)) {
5272 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
5274 assert(VT == MVT::v2i64 && "Expected an SSE value type!");
5275 EVT VecVT = MVT::v4i32;
5276 unsigned VecElts = 4;
5278 // Truncate the value (which may itself be a constant) to i32, and
5279 // convert it to a vector with movd (S2V+shuffle to zero extend).
5280 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
5281 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
5282 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
5284 // Now we have our 32-bit value zero extended in the low element of
5285 // a vector. If Idx != 0, swizzle it into place.
5287 SmallVector<int, 4> Mask;
5288 Mask.push_back(Idx);
5289 for (unsigned i = 1; i != VecElts; ++i)
5291 Item = DAG.getVectorShuffle(VecVT, dl, Item, DAG.getUNDEF(VecVT),
5294 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
5298 // If we have a constant or non-constant insertion into the low element of
5299 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
5300 // the rest of the elements. This will be matched as movd/movq/movss/movsd
5301 // depending on what the source datatype is.
5304 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5306 if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
5307 (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
5308 if (VT.is256BitVector()) {
5309 SDValue ZeroVec = getZeroVector(VT, Subtarget, DAG, dl);
5310 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, ZeroVec,
5311 Item, DAG.getIntPtrConstant(0));
5313 assert(VT.is128BitVector() && "Expected an SSE value type!");
5314 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5315 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
5316 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
5319 if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
5320 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
5321 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
5322 if (VT.is256BitVector()) {
5323 SDValue ZeroVec = getZeroVector(MVT::v8i32, Subtarget, DAG, dl);
5324 Item = Insert128BitVector(ZeroVec, Item, 0, DAG, dl);
5326 assert(VT.is128BitVector() && "Expected an SSE value type!");
5327 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
5329 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
5333 // Is it a vector logical left shift?
5334 if (NumElems == 2 && Idx == 1 &&
5335 X86::isZeroNode(Op.getOperand(0)) &&
5336 !X86::isZeroNode(Op.getOperand(1))) {
5337 unsigned NumBits = VT.getSizeInBits();
5338 return getVShift(true, VT,
5339 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
5340 VT, Op.getOperand(1)),
5341 NumBits/2, DAG, *this, dl);
5344 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
5347 // Otherwise, if this is a vector with i32 or f32 elements, and the element
5348 // is a non-constant being inserted into an element other than the low one,
5349 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
5350 // movd/movss) to move this into the low element, then shuffle it into
5352 if (EVTBits == 32) {
5353 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5355 // Turn it into a shuffle of zero and zero-extended scalar to vector.
5356 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0, Subtarget, DAG);
5357 SmallVector<int, 8> MaskVec;
5358 for (unsigned i = 0; i != NumElems; ++i)
5359 MaskVec.push_back(i == Idx ? 0 : 1);
5360 return DAG.getVectorShuffle(VT, dl, Item, DAG.getUNDEF(VT), &MaskVec[0]);
5364 // Splat is obviously ok. Let legalizer expand it to a shuffle.
5365 if (Values.size() == 1) {
5366 if (EVTBits == 32) {
5367 // Instead of a shuffle like this:
5368 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
5369 // Check if it's possible to issue this instead.
5370 // shuffle (vload ptr)), undef, <1, 1, 1, 1>
5371 unsigned Idx = CountTrailingZeros_32(NonZeros);
5372 SDValue Item = Op.getOperand(Idx);
5373 if (Op.getNode()->isOnlyUserOf(Item.getNode()))
5374 return LowerAsSplatVectorLoad(Item, VT, dl, DAG);
5379 // A vector full of immediates; various special cases are already
5380 // handled, so this is best done with a single constant-pool load.
5384 // For AVX-length vectors, build the individual 128-bit pieces and use
5385 // shuffles to put them in place.
5386 if (VT.is256BitVector()) {
5387 SmallVector<SDValue, 32> V;
5388 for (unsigned i = 0; i != NumElems; ++i)
5389 V.push_back(Op.getOperand(i));
5391 EVT HVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems/2);
5393 // Build both the lower and upper subvector.
5394 SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT, &V[0], NumElems/2);
5395 SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT, &V[NumElems / 2],
5398 // Recreate the wider vector with the lower and upper part.
5399 return Concat128BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
5402 // Let legalizer expand 2-wide build_vectors.
5403 if (EVTBits == 64) {
5404 if (NumNonZero == 1) {
5405 // One half is zero or undef.
5406 unsigned Idx = CountTrailingZeros_32(NonZeros);
5407 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
5408 Op.getOperand(Idx));
5409 return getShuffleVectorZeroOrUndef(V2, Idx, true, Subtarget, DAG);
5414 // If element VT is < 32 bits, convert it to inserts into a zero vector.
5415 if (EVTBits == 8 && NumElems == 16) {
5416 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
5418 if (V.getNode()) return V;
5421 if (EVTBits == 16 && NumElems == 8) {
5422 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
5424 if (V.getNode()) return V;
5427 // If element VT is == 32 bits, turn it into a number of shuffles.
5428 SmallVector<SDValue, 8> V(NumElems);
5429 if (NumElems == 4 && NumZero > 0) {
5430 for (unsigned i = 0; i < 4; ++i) {
5431 bool isZero = !(NonZeros & (1 << i));
5433 V[i] = getZeroVector(VT, Subtarget, DAG, dl);
5435 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
5438 for (unsigned i = 0; i < 2; ++i) {
5439 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
5442 V[i] = V[i*2]; // Must be a zero vector.
5445 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
5448 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
5451 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
5456 bool Reverse1 = (NonZeros & 0x3) == 2;
5457 bool Reverse2 = ((NonZeros & (0x3 << 2)) >> 2) == 2;
5461 static_cast<int>(Reverse2 ? NumElems+1 : NumElems),
5462 static_cast<int>(Reverse2 ? NumElems : NumElems+1)
5464 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
5467 if (Values.size() > 1 && VT.is128BitVector()) {
5468 // Check for a build vector of consecutive loads.
5469 for (unsigned i = 0; i < NumElems; ++i)
5470 V[i] = Op.getOperand(i);
5472 // Check for elements which are consecutive loads.
5473 SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG);
5477 // For SSE 4.1, use insertps to put the high elements into the low element.
5478 if (getSubtarget()->hasSSE41()) {
5480 if (Op.getOperand(0).getOpcode() != ISD::UNDEF)
5481 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0));
5483 Result = DAG.getUNDEF(VT);
5485 for (unsigned i = 1; i < NumElems; ++i) {
5486 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue;
5487 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result,
5488 Op.getOperand(i), DAG.getIntPtrConstant(i));
5493 // Otherwise, expand into a number of unpckl*, start by extending each of
5494 // our (non-undef) elements to the full vector width with the element in the
5495 // bottom slot of the vector (which generates no code for SSE).
5496 for (unsigned i = 0; i < NumElems; ++i) {
5497 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
5498 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
5500 V[i] = DAG.getUNDEF(VT);
5503 // Next, we iteratively mix elements, e.g. for v4f32:
5504 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
5505 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
5506 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
5507 unsigned EltStride = NumElems >> 1;
5508 while (EltStride != 0) {
5509 for (unsigned i = 0; i < EltStride; ++i) {
5510 // If V[i+EltStride] is undef and this is the first round of mixing,
5511 // then it is safe to just drop this shuffle: V[i] is already in the
5512 // right place, the one element (since it's the first round) being
5513 // inserted as undef can be dropped. This isn't safe for successive
5514 // rounds because they will permute elements within both vectors.
5515 if (V[i+EltStride].getOpcode() == ISD::UNDEF &&
5516 EltStride == NumElems/2)
5519 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]);
5528 // LowerAVXCONCAT_VECTORS - 256-bit AVX can use the vinsertf128 instruction
5529 // to create 256-bit vectors from two other 128-bit ones.
5530 static SDValue LowerAVXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
5531 DebugLoc dl = Op.getDebugLoc();
5532 EVT ResVT = Op.getValueType();
5534 assert(ResVT.is256BitVector() && "Value type must be 256-bit wide");
5536 SDValue V1 = Op.getOperand(0);
5537 SDValue V2 = Op.getOperand(1);
5538 unsigned NumElems = ResVT.getVectorNumElements();
5540 return Concat128BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
5544 X86TargetLowering::LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const {
5545 assert(Op.getNumOperands() == 2);
5547 // 256-bit AVX can use the vinsertf128 instruction to create 256-bit vectors
5548 // from two other 128-bit ones.
5549 return LowerAVXCONCAT_VECTORS(Op, DAG);
5552 // Try to lower a shuffle node into a simple blend instruction.
5553 static SDValue LowerVECTOR_SHUFFLEtoBlend(ShuffleVectorSDNode *SVOp,
5554 const X86Subtarget *Subtarget,
5555 SelectionDAG &DAG) {
5556 SDValue V1 = SVOp->getOperand(0);
5557 SDValue V2 = SVOp->getOperand(1);
5558 DebugLoc dl = SVOp->getDebugLoc();
5559 MVT VT = SVOp->getValueType(0).getSimpleVT();
5560 unsigned NumElems = VT.getVectorNumElements();
5562 if (!Subtarget->hasSSE41())
5568 switch (VT.SimpleTy) {
5569 default: return SDValue();
5571 ISDNo = X86ISD::BLENDPW;
5576 ISDNo = X86ISD::BLENDPS;
5581 ISDNo = X86ISD::BLENDPD;
5586 if (!Subtarget->hasAVX())
5588 ISDNo = X86ISD::BLENDPS;
5593 if (!Subtarget->hasAVX())
5595 ISDNo = X86ISD::BLENDPD;
5599 assert(ISDNo && "Invalid Op Number");
5601 unsigned MaskVals = 0;
5603 for (unsigned i = 0; i != NumElems; ++i) {
5604 int EltIdx = SVOp->getMaskElt(i);
5605 if (EltIdx == (int)i || EltIdx < 0)
5607 else if (EltIdx == (int)(i + NumElems))
5608 continue; // Bit is set to zero;
5613 V1 = DAG.getNode(ISD::BITCAST, dl, OpTy, V1);
5614 V2 = DAG.getNode(ISD::BITCAST, dl, OpTy, V2);
5615 SDValue Ret = DAG.getNode(ISDNo, dl, OpTy, V1, V2,
5616 DAG.getConstant(MaskVals, MVT::i32));
5617 return DAG.getNode(ISD::BITCAST, dl, VT, Ret);
5620 // v8i16 shuffles - Prefer shuffles in the following order:
5621 // 1. [all] pshuflw, pshufhw, optional move
5622 // 2. [ssse3] 1 x pshufb
5623 // 3. [ssse3] 2 x pshufb + 1 x por
5624 // 4. [all] mov + pshuflw + pshufhw + N x (pextrw + pinsrw)
5626 X86TargetLowering::LowerVECTOR_SHUFFLEv8i16(SDValue Op,
5627 SelectionDAG &DAG) const {
5628 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
5629 SDValue V1 = SVOp->getOperand(0);
5630 SDValue V2 = SVOp->getOperand(1);
5631 DebugLoc dl = SVOp->getDebugLoc();
5632 SmallVector<int, 8> MaskVals;
5634 // Determine if more than 1 of the words in each of the low and high quadwords
5635 // of the result come from the same quadword of one of the two inputs. Undef
5636 // mask values count as coming from any quadword, for better codegen.
5637 unsigned LoQuad[] = { 0, 0, 0, 0 };
5638 unsigned HiQuad[] = { 0, 0, 0, 0 };
5639 std::bitset<4> InputQuads;
5640 for (unsigned i = 0; i < 8; ++i) {
5641 unsigned *Quad = i < 4 ? LoQuad : HiQuad;
5642 int EltIdx = SVOp->getMaskElt(i);
5643 MaskVals.push_back(EltIdx);
5652 InputQuads.set(EltIdx / 4);
5655 int BestLoQuad = -1;
5656 unsigned MaxQuad = 1;
5657 for (unsigned i = 0; i < 4; ++i) {
5658 if (LoQuad[i] > MaxQuad) {
5660 MaxQuad = LoQuad[i];
5664 int BestHiQuad = -1;
5666 for (unsigned i = 0; i < 4; ++i) {
5667 if (HiQuad[i] > MaxQuad) {
5669 MaxQuad = HiQuad[i];
5673 // For SSSE3, If all 8 words of the result come from only 1 quadword of each
5674 // of the two input vectors, shuffle them into one input vector so only a
5675 // single pshufb instruction is necessary. If There are more than 2 input
5676 // quads, disable the next transformation since it does not help SSSE3.
5677 bool V1Used = InputQuads[0] || InputQuads[1];
5678 bool V2Used = InputQuads[2] || InputQuads[3];
5679 if (Subtarget->hasSSSE3()) {
5680 if (InputQuads.count() == 2 && V1Used && V2Used) {
5681 BestLoQuad = InputQuads[0] ? 0 : 1;
5682 BestHiQuad = InputQuads[2] ? 2 : 3;
5684 if (InputQuads.count() > 2) {
5690 // If BestLoQuad or BestHiQuad are set, shuffle the quads together and update
5691 // the shuffle mask. If a quad is scored as -1, that means that it contains
5692 // words from all 4 input quadwords.
5694 if (BestLoQuad >= 0 || BestHiQuad >= 0) {
5696 BestLoQuad < 0 ? 0 : BestLoQuad,
5697 BestHiQuad < 0 ? 1 : BestHiQuad
5699 NewV = DAG.getVectorShuffle(MVT::v2i64, dl,
5700 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V1),
5701 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V2), &MaskV[0]);
5702 NewV = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, NewV);
5704 // Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the
5705 // source words for the shuffle, to aid later transformations.
5706 bool AllWordsInNewV = true;
5707 bool InOrder[2] = { true, true };
5708 for (unsigned i = 0; i != 8; ++i) {
5709 int idx = MaskVals[i];
5711 InOrder[i/4] = false;
5712 if (idx < 0 || (idx/4) == BestLoQuad || (idx/4) == BestHiQuad)
5714 AllWordsInNewV = false;
5718 bool pshuflw = AllWordsInNewV, pshufhw = AllWordsInNewV;
5719 if (AllWordsInNewV) {
5720 for (int i = 0; i != 8; ++i) {
5721 int idx = MaskVals[i];
5724 idx = MaskVals[i] = (idx / 4) == BestLoQuad ? (idx & 3) : (idx & 3) + 4;
5725 if ((idx != i) && idx < 4)
5727 if ((idx != i) && idx > 3)
5736 // If we've eliminated the use of V2, and the new mask is a pshuflw or
5737 // pshufhw, that's as cheap as it gets. Return the new shuffle.
5738 if ((pshufhw && InOrder[0]) || (pshuflw && InOrder[1])) {
5739 unsigned Opc = pshufhw ? X86ISD::PSHUFHW : X86ISD::PSHUFLW;
5740 unsigned TargetMask = 0;
5741 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV,
5742 DAG.getUNDEF(MVT::v8i16), &MaskVals[0]);
5743 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
5744 TargetMask = pshufhw ? getShufflePSHUFHWImmediate(SVOp):
5745 getShufflePSHUFLWImmediate(SVOp);
5746 V1 = NewV.getOperand(0);
5747 return getTargetShuffleNode(Opc, dl, MVT::v8i16, V1, TargetMask, DAG);
5751 // If we have SSSE3, and all words of the result are from 1 input vector,
5752 // case 2 is generated, otherwise case 3 is generated. If no SSSE3
5753 // is present, fall back to case 4.
5754 if (Subtarget->hasSSSE3()) {
5755 SmallVector<SDValue,16> pshufbMask;
5757 // If we have elements from both input vectors, set the high bit of the
5758 // shuffle mask element to zero out elements that come from V2 in the V1
5759 // mask, and elements that come from V1 in the V2 mask, so that the two
5760 // results can be OR'd together.
5761 bool TwoInputs = V1Used && V2Used;
5762 for (unsigned i = 0; i != 8; ++i) {
5763 int EltIdx = MaskVals[i] * 2;
5764 int Idx0 = (TwoInputs && (EltIdx >= 16)) ? 0x80 : EltIdx;
5765 int Idx1 = (TwoInputs && (EltIdx >= 16)) ? 0x80 : EltIdx+1;
5766 pshufbMask.push_back(DAG.getConstant(Idx0, MVT::i8));
5767 pshufbMask.push_back(DAG.getConstant(Idx1, MVT::i8));
5769 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V1);
5770 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
5771 DAG.getNode(ISD::BUILD_VECTOR, dl,
5772 MVT::v16i8, &pshufbMask[0], 16));
5774 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
5776 // Calculate the shuffle mask for the second input, shuffle it, and
5777 // OR it with the first shuffled input.
5779 for (unsigned i = 0; i != 8; ++i) {
5780 int EltIdx = MaskVals[i] * 2;
5781 int Idx0 = (EltIdx < 16) ? 0x80 : EltIdx - 16;
5782 int Idx1 = (EltIdx < 16) ? 0x80 : EltIdx - 15;
5783 pshufbMask.push_back(DAG.getConstant(Idx0, MVT::i8));
5784 pshufbMask.push_back(DAG.getConstant(Idx1, MVT::i8));
5786 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V2);
5787 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
5788 DAG.getNode(ISD::BUILD_VECTOR, dl,
5789 MVT::v16i8, &pshufbMask[0], 16));
5790 V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
5791 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
5794 // If BestLoQuad >= 0, generate a pshuflw to put the low elements in order,
5795 // and update MaskVals with new element order.
5796 std::bitset<8> InOrder;
5797 if (BestLoQuad >= 0) {
5798 int MaskV[] = { -1, -1, -1, -1, 4, 5, 6, 7 };
5799 for (int i = 0; i != 4; ++i) {
5800 int idx = MaskVals[i];
5803 } else if ((idx / 4) == BestLoQuad) {
5808 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
5811 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSSE3()) {
5812 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
5813 NewV = getTargetShuffleNode(X86ISD::PSHUFLW, dl, MVT::v8i16,
5815 getShufflePSHUFLWImmediate(SVOp), DAG);
5819 // If BestHi >= 0, generate a pshufhw to put the high elements in order,
5820 // and update MaskVals with the new element order.
5821 if (BestHiQuad >= 0) {
5822 int MaskV[] = { 0, 1, 2, 3, -1, -1, -1, -1 };
5823 for (unsigned i = 4; i != 8; ++i) {
5824 int idx = MaskVals[i];
5827 } else if ((idx / 4) == BestHiQuad) {
5828 MaskV[i] = (idx & 3) + 4;
5832 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
5835 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSSE3()) {
5836 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
5837 NewV = getTargetShuffleNode(X86ISD::PSHUFHW, dl, MVT::v8i16,
5839 getShufflePSHUFHWImmediate(SVOp), DAG);
5843 // In case BestHi & BestLo were both -1, which means each quadword has a word
5844 // from each of the four input quadwords, calculate the InOrder bitvector now
5845 // before falling through to the insert/extract cleanup.
5846 if (BestLoQuad == -1 && BestHiQuad == -1) {
5848 for (int i = 0; i != 8; ++i)
5849 if (MaskVals[i] < 0 || MaskVals[i] == i)
5853 // The other elements are put in the right place using pextrw and pinsrw.
5854 for (unsigned i = 0; i != 8; ++i) {
5857 int EltIdx = MaskVals[i];
5860 SDValue ExtOp = (EltIdx < 8) ?
5861 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1,
5862 DAG.getIntPtrConstant(EltIdx)) :
5863 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2,
5864 DAG.getIntPtrConstant(EltIdx - 8));
5865 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp,
5866 DAG.getIntPtrConstant(i));
5871 // v16i8 shuffles - Prefer shuffles in the following order:
5872 // 1. [ssse3] 1 x pshufb
5873 // 2. [ssse3] 2 x pshufb + 1 x por
5874 // 3. [all] v8i16 shuffle + N x pextrw + rotate + pinsrw
5876 SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp,
5878 const X86TargetLowering &TLI) {
5879 SDValue V1 = SVOp->getOperand(0);
5880 SDValue V2 = SVOp->getOperand(1);
5881 DebugLoc dl = SVOp->getDebugLoc();
5882 ArrayRef<int> MaskVals = SVOp->getMask();
5884 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
5886 // If we have SSSE3, case 1 is generated when all result bytes come from
5887 // one of the inputs. Otherwise, case 2 is generated. If no SSSE3 is
5888 // present, fall back to case 3.
5890 // If SSSE3, use 1 pshufb instruction per vector with elements in the result.
5891 if (TLI.getSubtarget()->hasSSSE3()) {
5892 SmallVector<SDValue,16> pshufbMask;
5894 // If all result elements are from one input vector, then only translate
5895 // undef mask values to 0x80 (zero out result) in the pshufb mask.
5897 // Otherwise, we have elements from both input vectors, and must zero out
5898 // elements that come from V2 in the first mask, and V1 in the second mask
5899 // so that we can OR them together.
5900 for (unsigned i = 0; i != 16; ++i) {
5901 int EltIdx = MaskVals[i];
5902 if (EltIdx < 0 || EltIdx >= 16)
5904 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
5906 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
5907 DAG.getNode(ISD::BUILD_VECTOR, dl,
5908 MVT::v16i8, &pshufbMask[0], 16));
5912 // Calculate the shuffle mask for the second input, shuffle it, and
5913 // OR it with the first shuffled input.
5915 for (unsigned i = 0; i != 16; ++i) {
5916 int EltIdx = MaskVals[i];
5917 EltIdx = (EltIdx < 16) ? 0x80 : EltIdx - 16;
5918 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
5920 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
5921 DAG.getNode(ISD::BUILD_VECTOR, dl,
5922 MVT::v16i8, &pshufbMask[0], 16));
5923 return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
5926 // No SSSE3 - Calculate in place words and then fix all out of place words
5927 // With 0-16 extracts & inserts. Worst case is 16 bytes out of order from
5928 // the 16 different words that comprise the two doublequadword input vectors.
5929 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
5930 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V2);
5932 for (int i = 0; i != 8; ++i) {
5933 int Elt0 = MaskVals[i*2];
5934 int Elt1 = MaskVals[i*2+1];
5936 // This word of the result is all undef, skip it.
5937 if (Elt0 < 0 && Elt1 < 0)
5940 // This word of the result is already in the correct place, skip it.
5941 if ((Elt0 == i*2) && (Elt1 == i*2+1))
5944 SDValue Elt0Src = Elt0 < 16 ? V1 : V2;
5945 SDValue Elt1Src = Elt1 < 16 ? V1 : V2;
5948 // If Elt0 and Elt1 are defined, are consecutive, and can be load
5949 // using a single extract together, load it and store it.
5950 if ((Elt0 >= 0) && ((Elt0 + 1) == Elt1) && ((Elt0 & 1) == 0)) {
5951 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
5952 DAG.getIntPtrConstant(Elt1 / 2));
5953 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
5954 DAG.getIntPtrConstant(i));
5958 // If Elt1 is defined, extract it from the appropriate source. If the
5959 // source byte is not also odd, shift the extracted word left 8 bits
5960 // otherwise clear the bottom 8 bits if we need to do an or.
5962 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
5963 DAG.getIntPtrConstant(Elt1 / 2));
5964 if ((Elt1 & 1) == 0)
5965 InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt,
5967 TLI.getShiftAmountTy(InsElt.getValueType())));
5969 InsElt = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt,
5970 DAG.getConstant(0xFF00, MVT::i16));
5972 // If Elt0 is defined, extract it from the appropriate source. If the
5973 // source byte is not also even, shift the extracted word right 8 bits. If
5974 // Elt1 was also defined, OR the extracted values together before
5975 // inserting them in the result.
5977 SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16,
5978 Elt0Src, DAG.getIntPtrConstant(Elt0 / 2));
5979 if ((Elt0 & 1) != 0)
5980 InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0,
5982 TLI.getShiftAmountTy(InsElt0.getValueType())));
5984 InsElt0 = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt0,
5985 DAG.getConstant(0x00FF, MVT::i16));
5986 InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0)
5989 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
5990 DAG.getIntPtrConstant(i));
5992 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, NewV);
5995 /// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide
5996 /// ones, or rewriting v4i32 / v4f32 as 2 wide ones if possible. This can be
5997 /// done when every pair / quad of shuffle mask elements point to elements in
5998 /// the right sequence. e.g.
5999 /// vector_shuffle X, Y, <2, 3, | 10, 11, | 0, 1, | 14, 15>
6001 SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp,
6002 SelectionDAG &DAG, DebugLoc dl) {
6003 MVT VT = SVOp->getValueType(0).getSimpleVT();
6004 unsigned NumElems = VT.getVectorNumElements();
6007 switch (VT.SimpleTy) {
6008 default: llvm_unreachable("Unexpected!");
6009 case MVT::v4f32: NewVT = MVT::v2f64; Scale = 2; break;
6010 case MVT::v4i32: NewVT = MVT::v2i64; Scale = 2; break;
6011 case MVT::v8i16: NewVT = MVT::v4i32; Scale = 2; break;
6012 case MVT::v16i8: NewVT = MVT::v4i32; Scale = 4; break;
6013 case MVT::v16i16: NewVT = MVT::v8i32; Scale = 2; break;
6014 case MVT::v32i8: NewVT = MVT::v8i32; Scale = 4; break;
6017 SmallVector<int, 8> MaskVec;
6018 for (unsigned i = 0; i != NumElems; i += Scale) {
6020 for (unsigned j = 0; j != Scale; ++j) {
6021 int EltIdx = SVOp->getMaskElt(i+j);
6025 StartIdx = (EltIdx / Scale);
6026 if (EltIdx != (int)(StartIdx*Scale + j))
6029 MaskVec.push_back(StartIdx);
6032 SDValue V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(0));
6033 SDValue V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(1));
6034 return DAG.getVectorShuffle(NewVT, dl, V1, V2, &MaskVec[0]);
6037 /// getVZextMovL - Return a zero-extending vector move low node.
6039 static SDValue getVZextMovL(EVT VT, EVT OpVT,
6040 SDValue SrcOp, SelectionDAG &DAG,
6041 const X86Subtarget *Subtarget, DebugLoc dl) {
6042 if (VT == MVT::v2f64 || VT == MVT::v4f32) {
6043 LoadSDNode *LD = NULL;
6044 if (!isScalarLoadToVector(SrcOp.getNode(), &LD))
6045 LD = dyn_cast<LoadSDNode>(SrcOp);
6047 // movssrr and movsdrr do not clear top bits. Try to use movd, movq
6049 MVT ExtVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32;
6050 if ((ExtVT != MVT::i64 || Subtarget->is64Bit()) &&
6051 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR &&
6052 SrcOp.getOperand(0).getOpcode() == ISD::BITCAST &&
6053 SrcOp.getOperand(0).getOperand(0).getValueType() == ExtVT) {
6055 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32;
6056 return DAG.getNode(ISD::BITCAST, dl, VT,
6057 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
6058 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
6066 return DAG.getNode(ISD::BITCAST, dl, VT,
6067 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
6068 DAG.getNode(ISD::BITCAST, dl,
6072 /// LowerVECTOR_SHUFFLE_256 - Handle all 256-bit wide vectors shuffles
6073 /// which could not be matched by any known target speficic shuffle
6075 LowerVECTOR_SHUFFLE_256(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
6077 SDValue NewOp = Compact8x32ShuffleNode(SVOp, DAG);
6078 if (NewOp.getNode())
6081 EVT VT = SVOp->getValueType(0);
6083 unsigned NumElems = VT.getVectorNumElements();
6084 unsigned NumLaneElems = NumElems / 2;
6086 DebugLoc dl = SVOp->getDebugLoc();
6087 MVT EltVT = VT.getVectorElementType().getSimpleVT();
6088 EVT NVT = MVT::getVectorVT(EltVT, NumLaneElems);
6091 SmallVector<int, 16> Mask;
6092 for (unsigned l = 0; l < 2; ++l) {
6093 // Build a shuffle mask for the output, discovering on the fly which
6094 // input vectors to use as shuffle operands (recorded in InputUsed).
6095 // If building a suitable shuffle vector proves too hard, then bail
6096 // out with UseBuildVector set.
6097 bool UseBuildVector = false;
6098 int InputUsed[2] = { -1, -1 }; // Not yet discovered.
6099 unsigned LaneStart = l * NumLaneElems;
6100 for (unsigned i = 0; i != NumLaneElems; ++i) {
6101 // The mask element. This indexes into the input.
6102 int Idx = SVOp->getMaskElt(i+LaneStart);
6104 // the mask element does not index into any input vector.
6109 // The input vector this mask element indexes into.
6110 int Input = Idx / NumLaneElems;
6112 // Turn the index into an offset from the start of the input vector.
6113 Idx -= Input * NumLaneElems;
6115 // Find or create a shuffle vector operand to hold this input.
6117 for (OpNo = 0; OpNo < array_lengthof(InputUsed); ++OpNo) {
6118 if (InputUsed[OpNo] == Input)
6119 // This input vector is already an operand.
6121 if (InputUsed[OpNo] < 0) {
6122 // Create a new operand for this input vector.
6123 InputUsed[OpNo] = Input;
6128 if (OpNo >= array_lengthof(InputUsed)) {
6129 // More than two input vectors used! Give up on trying to create a
6130 // shuffle vector. Insert all elements into a BUILD_VECTOR instead.
6131 UseBuildVector = true;
6135 // Add the mask index for the new shuffle vector.
6136 Mask.push_back(Idx + OpNo * NumLaneElems);
6139 if (UseBuildVector) {
6140 SmallVector<SDValue, 16> SVOps;
6141 for (unsigned i = 0; i != NumLaneElems; ++i) {
6142 // The mask element. This indexes into the input.
6143 int Idx = SVOp->getMaskElt(i+LaneStart);
6145 SVOps.push_back(DAG.getUNDEF(EltVT));
6149 // The input vector this mask element indexes into.
6150 int Input = Idx / NumElems;
6152 // Turn the index into an offset from the start of the input vector.
6153 Idx -= Input * NumElems;
6155 // Extract the vector element by hand.
6156 SVOps.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
6157 SVOp->getOperand(Input),
6158 DAG.getIntPtrConstant(Idx)));
6161 // Construct the output using a BUILD_VECTOR.
6162 Output[l] = DAG.getNode(ISD::BUILD_VECTOR, dl, NVT, &SVOps[0],
6164 } else if (InputUsed[0] < 0) {
6165 // No input vectors were used! The result is undefined.
6166 Output[l] = DAG.getUNDEF(NVT);
6168 SDValue Op0 = Extract128BitVector(SVOp->getOperand(InputUsed[0] / 2),
6169 (InputUsed[0] % 2) * NumLaneElems,
6171 // If only one input was used, use an undefined vector for the other.
6172 SDValue Op1 = (InputUsed[1] < 0) ? DAG.getUNDEF(NVT) :
6173 Extract128BitVector(SVOp->getOperand(InputUsed[1] / 2),
6174 (InputUsed[1] % 2) * NumLaneElems, DAG, dl);
6175 // At least one input vector was used. Create a new shuffle vector.
6176 Output[l] = DAG.getVectorShuffle(NVT, dl, Op0, Op1, &Mask[0]);
6182 // Concatenate the result back
6183 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, Output[0], Output[1]);
6186 /// LowerVECTOR_SHUFFLE_128v4 - Handle all 128-bit wide vectors with
6187 /// 4 elements, and match them with several different shuffle types.
6189 LowerVECTOR_SHUFFLE_128v4(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
6190 SDValue V1 = SVOp->getOperand(0);
6191 SDValue V2 = SVOp->getOperand(1);
6192 DebugLoc dl = SVOp->getDebugLoc();
6193 EVT VT = SVOp->getValueType(0);
6195 assert(VT.is128BitVector() && "Unsupported vector size");
6197 std::pair<int, int> Locs[4];
6198 int Mask1[] = { -1, -1, -1, -1 };
6199 SmallVector<int, 8> PermMask(SVOp->getMask().begin(), SVOp->getMask().end());
6203 for (unsigned i = 0; i != 4; ++i) {
6204 int Idx = PermMask[i];
6206 Locs[i] = std::make_pair(-1, -1);
6208 assert(Idx < 8 && "Invalid VECTOR_SHUFFLE index!");
6210 Locs[i] = std::make_pair(0, NumLo);
6214 Locs[i] = std::make_pair(1, NumHi);
6216 Mask1[2+NumHi] = Idx;
6222 if (NumLo <= 2 && NumHi <= 2) {
6223 // If no more than two elements come from either vector. This can be
6224 // implemented with two shuffles. First shuffle gather the elements.
6225 // The second shuffle, which takes the first shuffle as both of its
6226 // vector operands, put the elements into the right order.
6227 V1 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
6229 int Mask2[] = { -1, -1, -1, -1 };
6231 for (unsigned i = 0; i != 4; ++i)
6232 if (Locs[i].first != -1) {
6233 unsigned Idx = (i < 2) ? 0 : 4;
6234 Idx += Locs[i].first * 2 + Locs[i].second;
6238 return DAG.getVectorShuffle(VT, dl, V1, V1, &Mask2[0]);
6241 if (NumLo == 3 || NumHi == 3) {
6242 // Otherwise, we must have three elements from one vector, call it X, and
6243 // one element from the other, call it Y. First, use a shufps to build an
6244 // intermediate vector with the one element from Y and the element from X
6245 // that will be in the same half in the final destination (the indexes don't
6246 // matter). Then, use a shufps to build the final vector, taking the half
6247 // containing the element from Y from the intermediate, and the other half
6250 // Normalize it so the 3 elements come from V1.
6251 CommuteVectorShuffleMask(PermMask, 4);
6255 // Find the element from V2.
6257 for (HiIndex = 0; HiIndex < 3; ++HiIndex) {
6258 int Val = PermMask[HiIndex];
6265 Mask1[0] = PermMask[HiIndex];
6267 Mask1[2] = PermMask[HiIndex^1];
6269 V2 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
6272 Mask1[0] = PermMask[0];
6273 Mask1[1] = PermMask[1];
6274 Mask1[2] = HiIndex & 1 ? 6 : 4;
6275 Mask1[3] = HiIndex & 1 ? 4 : 6;
6276 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
6279 Mask1[0] = HiIndex & 1 ? 2 : 0;
6280 Mask1[1] = HiIndex & 1 ? 0 : 2;
6281 Mask1[2] = PermMask[2];
6282 Mask1[3] = PermMask[3];
6287 return DAG.getVectorShuffle(VT, dl, V2, V1, &Mask1[0]);
6290 // Break it into (shuffle shuffle_hi, shuffle_lo).
6291 int LoMask[] = { -1, -1, -1, -1 };
6292 int HiMask[] = { -1, -1, -1, -1 };
6294 int *MaskPtr = LoMask;
6295 unsigned MaskIdx = 0;
6298 for (unsigned i = 0; i != 4; ++i) {
6305 int Idx = PermMask[i];
6307 Locs[i] = std::make_pair(-1, -1);
6308 } else if (Idx < 4) {
6309 Locs[i] = std::make_pair(MaskIdx, LoIdx);
6310 MaskPtr[LoIdx] = Idx;
6313 Locs[i] = std::make_pair(MaskIdx, HiIdx);
6314 MaskPtr[HiIdx] = Idx;
6319 SDValue LoShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &LoMask[0]);
6320 SDValue HiShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &HiMask[0]);
6321 int MaskOps[] = { -1, -1, -1, -1 };
6322 for (unsigned i = 0; i != 4; ++i)
6323 if (Locs[i].first != -1)
6324 MaskOps[i] = Locs[i].first * 4 + Locs[i].second;
6325 return DAG.getVectorShuffle(VT, dl, LoShuffle, HiShuffle, &MaskOps[0]);
6328 static bool MayFoldVectorLoad(SDValue V) {
6329 if (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
6330 V = V.getOperand(0);
6331 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR)
6332 V = V.getOperand(0);
6333 if (V.hasOneUse() && V.getOpcode() == ISD::BUILD_VECTOR &&
6334 V.getNumOperands() == 2 && V.getOperand(1).getOpcode() == ISD::UNDEF)
6335 // BUILD_VECTOR (load), undef
6336 V = V.getOperand(0);
6342 // FIXME: the version above should always be used. Since there's
6343 // a bug where several vector shuffles can't be folded because the
6344 // DAG is not updated during lowering and a node claims to have two
6345 // uses while it only has one, use this version, and let isel match
6346 // another instruction if the load really happens to have more than
6347 // one use. Remove this version after this bug get fixed.
6348 // rdar://8434668, PR8156
6349 static bool RelaxedMayFoldVectorLoad(SDValue V) {
6350 if (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
6351 V = V.getOperand(0);
6352 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR)
6353 V = V.getOperand(0);
6354 if (ISD::isNormalLoad(V.getNode()))
6360 SDValue getMOVDDup(SDValue &Op, DebugLoc &dl, SDValue V1, SelectionDAG &DAG) {
6361 EVT VT = Op.getValueType();
6363 // Canonizalize to v2f64.
6364 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, V1);
6365 return DAG.getNode(ISD::BITCAST, dl, VT,
6366 getTargetShuffleNode(X86ISD::MOVDDUP, dl, MVT::v2f64,
6371 SDValue getMOVLowToHigh(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG,
6373 SDValue V1 = Op.getOperand(0);
6374 SDValue V2 = Op.getOperand(1);
6375 EVT VT = Op.getValueType();
6377 assert(VT != MVT::v2i64 && "unsupported shuffle type");
6379 if (HasSSE2 && VT == MVT::v2f64)
6380 return getTargetShuffleNode(X86ISD::MOVLHPD, dl, VT, V1, V2, DAG);
6382 // v4f32 or v4i32: canonizalized to v4f32 (which is legal for SSE1)
6383 return DAG.getNode(ISD::BITCAST, dl, VT,
6384 getTargetShuffleNode(X86ISD::MOVLHPS, dl, MVT::v4f32,
6385 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V1),
6386 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V2), DAG));
6390 SDValue getMOVHighToLow(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG) {
6391 SDValue V1 = Op.getOperand(0);
6392 SDValue V2 = Op.getOperand(1);
6393 EVT VT = Op.getValueType();
6395 assert((VT == MVT::v4i32 || VT == MVT::v4f32) &&
6396 "unsupported shuffle type");
6398 if (V2.getOpcode() == ISD::UNDEF)
6402 return getTargetShuffleNode(X86ISD::MOVHLPS, dl, VT, V1, V2, DAG);
6406 SDValue getMOVLP(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG, bool HasSSE2) {
6407 SDValue V1 = Op.getOperand(0);
6408 SDValue V2 = Op.getOperand(1);
6409 EVT VT = Op.getValueType();
6410 unsigned NumElems = VT.getVectorNumElements();
6412 // Use MOVLPS and MOVLPD in case V1 or V2 are loads. During isel, the second
6413 // operand of these instructions is only memory, so check if there's a
6414 // potencial load folding here, otherwise use SHUFPS or MOVSD to match the
6416 bool CanFoldLoad = false;
6418 // Trivial case, when V2 comes from a load.
6419 if (MayFoldVectorLoad(V2))
6422 // When V1 is a load, it can be folded later into a store in isel, example:
6423 // (store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)), addr:$src1)
6425 // (MOVLPSmr addr:$src1, VR128:$src2)
6426 // So, recognize this potential and also use MOVLPS or MOVLPD
6427 else if (MayFoldVectorLoad(V1) && MayFoldIntoStore(Op))
6430 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6432 if (HasSSE2 && NumElems == 2)
6433 return getTargetShuffleNode(X86ISD::MOVLPD, dl, VT, V1, V2, DAG);
6436 // If we don't care about the second element, proceed to use movss.
6437 if (SVOp->getMaskElt(1) != -1)
6438 return getTargetShuffleNode(X86ISD::MOVLPS, dl, VT, V1, V2, DAG);
6441 // movl and movlp will both match v2i64, but v2i64 is never matched by
6442 // movl earlier because we make it strict to avoid messing with the movlp load
6443 // folding logic (see the code above getMOVLP call). Match it here then,
6444 // this is horrible, but will stay like this until we move all shuffle
6445 // matching to x86 specific nodes. Note that for the 1st condition all
6446 // types are matched with movsd.
6448 // FIXME: isMOVLMask should be checked and matched before getMOVLP,
6449 // as to remove this logic from here, as much as possible
6450 if (NumElems == 2 || !isMOVLMask(SVOp->getMask(), VT))
6451 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
6452 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
6455 assert(VT != MVT::v4i32 && "unsupported shuffle type");
6457 // Invert the operand order and use SHUFPS to match it.
6458 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V2, V1,
6459 getShuffleSHUFImmediate(SVOp), DAG);
6463 X86TargetLowering::NormalizeVectorShuffle(SDValue Op, SelectionDAG &DAG) const {
6464 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6465 EVT VT = Op.getValueType();
6466 DebugLoc dl = Op.getDebugLoc();
6467 SDValue V1 = Op.getOperand(0);
6468 SDValue V2 = Op.getOperand(1);
6470 if (isZeroShuffle(SVOp))
6471 return getZeroVector(VT, Subtarget, DAG, dl);
6473 // Handle splat operations
6474 if (SVOp->isSplat()) {
6475 unsigned NumElem = VT.getVectorNumElements();
6476 int Size = VT.getSizeInBits();
6478 // Use vbroadcast whenever the splat comes from a foldable load
6479 SDValue Broadcast = LowerVectorBroadcast(Op, DAG);
6480 if (Broadcast.getNode())
6483 // Handle splats by matching through known shuffle masks
6484 if ((Size == 128 && NumElem <= 4) ||
6485 (Size == 256 && NumElem < 8))
6488 // All remaning splats are promoted to target supported vector shuffles.
6489 return PromoteSplat(SVOp, DAG);
6492 // If the shuffle can be profitably rewritten as a narrower shuffle, then
6494 if (VT == MVT::v8i16 || VT == MVT::v16i8 ||
6495 VT == MVT::v16i16 || VT == MVT::v32i8) {
6496 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl);
6497 if (NewOp.getNode())
6498 return DAG.getNode(ISD::BITCAST, dl, VT, NewOp);
6499 } else if ((VT == MVT::v4i32 ||
6500 (VT == MVT::v4f32 && Subtarget->hasSSE2()))) {
6501 // FIXME: Figure out a cleaner way to do this.
6502 // Try to make use of movq to zero out the top part.
6503 if (ISD::isBuildVectorAllZeros(V2.getNode())) {
6504 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl);
6505 if (NewOp.getNode()) {
6506 EVT NewVT = NewOp.getValueType();
6507 if (isCommutedMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(),
6508 NewVT, true, false))
6509 return getVZextMovL(VT, NewVT, NewOp.getOperand(0),
6510 DAG, Subtarget, dl);
6512 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) {
6513 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl);
6514 if (NewOp.getNode()) {
6515 EVT NewVT = NewOp.getValueType();
6516 if (isMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(), NewVT))
6517 return getVZextMovL(VT, NewVT, NewOp.getOperand(1),
6518 DAG, Subtarget, dl);
6526 X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const {
6527 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6528 SDValue V1 = Op.getOperand(0);
6529 SDValue V2 = Op.getOperand(1);
6530 EVT VT = Op.getValueType();
6531 DebugLoc dl = Op.getDebugLoc();
6532 unsigned NumElems = VT.getVectorNumElements();
6533 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
6534 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
6535 bool V1IsSplat = false;
6536 bool V2IsSplat = false;
6537 bool HasSSE2 = Subtarget->hasSSE2();
6538 bool HasAVX = Subtarget->hasAVX();
6539 bool HasAVX2 = Subtarget->hasAVX2();
6540 MachineFunction &MF = DAG.getMachineFunction();
6541 bool OptForSize = MF.getFunction()->hasFnAttr(Attribute::OptimizeForSize);
6543 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
6545 if (V1IsUndef && V2IsUndef)
6546 return DAG.getUNDEF(VT);
6548 assert(!V1IsUndef && "Op 1 of shuffle should not be undef");
6550 // Vector shuffle lowering takes 3 steps:
6552 // 1) Normalize the input vectors. Here splats, zeroed vectors, profitable
6553 // narrowing and commutation of operands should be handled.
6554 // 2) Matching of shuffles with known shuffle masks to x86 target specific
6556 // 3) Rewriting of unmatched masks into new generic shuffle operations,
6557 // so the shuffle can be broken into other shuffles and the legalizer can
6558 // try the lowering again.
6560 // The general idea is that no vector_shuffle operation should be left to
6561 // be matched during isel, all of them must be converted to a target specific
6564 // Normalize the input vectors. Here splats, zeroed vectors, profitable
6565 // narrowing and commutation of operands should be handled. The actual code
6566 // doesn't include all of those, work in progress...
6567 SDValue NewOp = NormalizeVectorShuffle(Op, DAG);
6568 if (NewOp.getNode())
6571 SmallVector<int, 8> M(SVOp->getMask().begin(), SVOp->getMask().end());
6573 // NOTE: isPSHUFDMask can also match both masks below (unpckl_undef and
6574 // unpckh_undef). Only use pshufd if speed is more important than size.
6575 if (OptForSize && isUNPCKL_v_undef_Mask(M, VT, HasAVX2))
6576 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
6577 if (OptForSize && isUNPCKH_v_undef_Mask(M, VT, HasAVX2))
6578 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
6580 if (isMOVDDUPMask(M, VT) && Subtarget->hasSSE3() &&
6581 V2IsUndef && RelaxedMayFoldVectorLoad(V1))
6582 return getMOVDDup(Op, dl, V1, DAG);
6584 if (isMOVHLPS_v_undef_Mask(M, VT))
6585 return getMOVHighToLow(Op, dl, DAG);
6587 // Use to match splats
6588 if (HasSSE2 && isUNPCKHMask(M, VT, HasAVX2) && V2IsUndef &&
6589 (VT == MVT::v2f64 || VT == MVT::v2i64))
6590 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
6592 if (isPSHUFDMask(M, VT)) {
6593 // The actual implementation will match the mask in the if above and then
6594 // during isel it can match several different instructions, not only pshufd
6595 // as its name says, sad but true, emulate the behavior for now...
6596 if (isMOVDDUPMask(M, VT) && ((VT == MVT::v4f32 || VT == MVT::v2i64)))
6597 return getTargetShuffleNode(X86ISD::MOVLHPS, dl, VT, V1, V1, DAG);
6599 unsigned TargetMask = getShuffleSHUFImmediate(SVOp);
6601 if (HasAVX && (VT == MVT::v4f32 || VT == MVT::v2f64))
6602 return getTargetShuffleNode(X86ISD::VPERMILP, dl, VT, V1, TargetMask, DAG);
6604 if (HasSSE2 && (VT == MVT::v4f32 || VT == MVT::v4i32))
6605 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1, TargetMask, DAG);
6607 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V1,
6611 // Check if this can be converted into a logical shift.
6612 bool isLeft = false;
6615 bool isShift = HasSSE2 && isVectorShift(SVOp, DAG, isLeft, ShVal, ShAmt);
6616 if (isShift && ShVal.hasOneUse()) {
6617 // If the shifted value has multiple uses, it may be cheaper to use
6618 // v_set0 + movlhps or movhlps, etc.
6619 EVT EltVT = VT.getVectorElementType();
6620 ShAmt *= EltVT.getSizeInBits();
6621 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
6624 if (isMOVLMask(M, VT)) {
6625 if (ISD::isBuildVectorAllZeros(V1.getNode()))
6626 return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl);
6627 if (!isMOVLPMask(M, VT)) {
6628 if (HasSSE2 && (VT == MVT::v2i64 || VT == MVT::v2f64))
6629 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
6631 if (VT == MVT::v4i32 || VT == MVT::v4f32)
6632 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
6636 // FIXME: fold these into legal mask.
6637 if (isMOVLHPSMask(M, VT) && !isUNPCKLMask(M, VT, HasAVX2))
6638 return getMOVLowToHigh(Op, dl, DAG, HasSSE2);
6640 if (isMOVHLPSMask(M, VT))
6641 return getMOVHighToLow(Op, dl, DAG);
6643 if (V2IsUndef && isMOVSHDUPMask(M, VT, Subtarget))
6644 return getTargetShuffleNode(X86ISD::MOVSHDUP, dl, VT, V1, DAG);
6646 if (V2IsUndef && isMOVSLDUPMask(M, VT, Subtarget))
6647 return getTargetShuffleNode(X86ISD::MOVSLDUP, dl, VT, V1, DAG);
6649 if (isMOVLPMask(M, VT))
6650 return getMOVLP(Op, dl, DAG, HasSSE2);
6652 if (ShouldXformToMOVHLPS(M, VT) ||
6653 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), M, VT))
6654 return CommuteVectorShuffle(SVOp, DAG);
6657 // No better options. Use a vshldq / vsrldq.
6658 EVT EltVT = VT.getVectorElementType();
6659 ShAmt *= EltVT.getSizeInBits();
6660 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
6663 bool Commuted = false;
6664 // FIXME: This should also accept a bitcast of a splat? Be careful, not
6665 // 1,1,1,1 -> v8i16 though.
6666 V1IsSplat = isSplatVector(V1.getNode());
6667 V2IsSplat = isSplatVector(V2.getNode());
6669 // Canonicalize the splat or undef, if present, to be on the RHS.
6670 if (!V2IsUndef && V1IsSplat && !V2IsSplat) {
6671 CommuteVectorShuffleMask(M, NumElems);
6673 std::swap(V1IsSplat, V2IsSplat);
6677 if (isCommutedMOVLMask(M, VT, V2IsSplat, V2IsUndef)) {
6678 // Shuffling low element of v1 into undef, just return v1.
6681 // If V2 is a splat, the mask may be malformed such as <4,3,3,3>, which
6682 // the instruction selector will not match, so get a canonical MOVL with
6683 // swapped operands to undo the commute.
6684 return getMOVL(DAG, dl, VT, V2, V1);
6687 if (isUNPCKLMask(M, VT, HasAVX2))
6688 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
6690 if (isUNPCKHMask(M, VT, HasAVX2))
6691 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
6694 // Normalize mask so all entries that point to V2 points to its first
6695 // element then try to match unpck{h|l} again. If match, return a
6696 // new vector_shuffle with the corrected mask.p
6697 SmallVector<int, 8> NewMask(M.begin(), M.end());
6698 NormalizeMask(NewMask, NumElems);
6699 if (isUNPCKLMask(NewMask, VT, HasAVX2, true))
6700 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
6701 if (isUNPCKHMask(NewMask, VT, HasAVX2, true))
6702 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
6706 // Commute is back and try unpck* again.
6707 // FIXME: this seems wrong.
6708 CommuteVectorShuffleMask(M, NumElems);
6710 std::swap(V1IsSplat, V2IsSplat);
6713 if (isUNPCKLMask(M, VT, HasAVX2))
6714 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
6716 if (isUNPCKHMask(M, VT, HasAVX2))
6717 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
6720 // Normalize the node to match x86 shuffle ops if needed
6721 if (!V2IsUndef && (isSHUFPMask(M, VT, HasAVX, /* Commuted */ true)))
6722 return CommuteVectorShuffle(SVOp, DAG);
6724 // The checks below are all present in isShuffleMaskLegal, but they are
6725 // inlined here right now to enable us to directly emit target specific
6726 // nodes, and remove one by one until they don't return Op anymore.
6728 if (isPALIGNRMask(M, VT, Subtarget))
6729 return getTargetShuffleNode(X86ISD::PALIGN, dl, VT, V1, V2,
6730 getShufflePALIGNRImmediate(SVOp),
6733 if (ShuffleVectorSDNode::isSplatMask(&M[0], VT) &&
6734 SVOp->getSplatIndex() == 0 && V2IsUndef) {
6735 if (VT == MVT::v2f64 || VT == MVT::v2i64)
6736 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
6739 if (isPSHUFHWMask(M, VT, HasAVX2))
6740 return getTargetShuffleNode(X86ISD::PSHUFHW, dl, VT, V1,
6741 getShufflePSHUFHWImmediate(SVOp),
6744 if (isPSHUFLWMask(M, VT, HasAVX2))
6745 return getTargetShuffleNode(X86ISD::PSHUFLW, dl, VT, V1,
6746 getShufflePSHUFLWImmediate(SVOp),
6749 if (isSHUFPMask(M, VT, HasAVX))
6750 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V2,
6751 getShuffleSHUFImmediate(SVOp), DAG);
6753 if (isUNPCKL_v_undef_Mask(M, VT, HasAVX2))
6754 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
6755 if (isUNPCKH_v_undef_Mask(M, VT, HasAVX2))
6756 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
6758 //===--------------------------------------------------------------------===//
6759 // Generate target specific nodes for 128 or 256-bit shuffles only
6760 // supported in the AVX instruction set.
6763 // Handle VMOVDDUPY permutations
6764 if (V2IsUndef && isMOVDDUPYMask(M, VT, HasAVX))
6765 return getTargetShuffleNode(X86ISD::MOVDDUP, dl, VT, V1, DAG);
6767 // Handle VPERMILPS/D* permutations
6768 if (isVPERMILPMask(M, VT, HasAVX)) {
6769 if (HasAVX2 && VT == MVT::v8i32)
6770 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1,
6771 getShuffleSHUFImmediate(SVOp), DAG);
6772 return getTargetShuffleNode(X86ISD::VPERMILP, dl, VT, V1,
6773 getShuffleSHUFImmediate(SVOp), DAG);
6776 // Handle VPERM2F128/VPERM2I128 permutations
6777 if (isVPERM2X128Mask(M, VT, HasAVX))
6778 return getTargetShuffleNode(X86ISD::VPERM2X128, dl, VT, V1,
6779 V2, getShuffleVPERM2X128Immediate(SVOp), DAG);
6781 SDValue BlendOp = LowerVECTOR_SHUFFLEtoBlend(SVOp, Subtarget, DAG);
6782 if (BlendOp.getNode())
6785 if (V2IsUndef && HasAVX2 && (VT == MVT::v8i32 || VT == MVT::v8f32)) {
6786 SmallVector<SDValue, 8> permclMask;
6787 for (unsigned i = 0; i != 8; ++i) {
6788 permclMask.push_back(DAG.getConstant((M[i]>=0) ? M[i] : 0, MVT::i32));
6790 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32,
6792 // Bitcast is for VPERMPS since mask is v8i32 but node takes v8f32
6793 return DAG.getNode(X86ISD::VPERMV, dl, VT,
6794 DAG.getNode(ISD::BITCAST, dl, VT, Mask), V1);
6797 if (V2IsUndef && HasAVX2 && (VT == MVT::v4i64 || VT == MVT::v4f64))
6798 return getTargetShuffleNode(X86ISD::VPERMI, dl, VT, V1,
6799 getShuffleCLImmediate(SVOp), DAG);
6802 //===--------------------------------------------------------------------===//
6803 // Since no target specific shuffle was selected for this generic one,
6804 // lower it into other known shuffles. FIXME: this isn't true yet, but
6805 // this is the plan.
6808 // Handle v8i16 specifically since SSE can do byte extraction and insertion.
6809 if (VT == MVT::v8i16) {
6810 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(Op, DAG);
6811 if (NewOp.getNode())
6815 if (VT == MVT::v16i8) {
6816 SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(SVOp, DAG, *this);
6817 if (NewOp.getNode())
6821 // Handle all 128-bit wide vectors with 4 elements, and match them with
6822 // several different shuffle types.
6823 if (NumElems == 4 && VT.is128BitVector())
6824 return LowerVECTOR_SHUFFLE_128v4(SVOp, DAG);
6826 // Handle general 256-bit shuffles
6827 if (VT.is256BitVector())
6828 return LowerVECTOR_SHUFFLE_256(SVOp, DAG);
6834 X86TargetLowering::LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op,
6835 SelectionDAG &DAG) const {
6836 EVT VT = Op.getValueType();
6837 DebugLoc dl = Op.getDebugLoc();
6839 if (!Op.getOperand(0).getValueType().is128BitVector())
6842 if (VT.getSizeInBits() == 8) {
6843 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
6844 Op.getOperand(0), Op.getOperand(1));
6845 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
6846 DAG.getValueType(VT));
6847 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
6850 if (VT.getSizeInBits() == 16) {
6851 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
6852 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
6854 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
6855 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
6856 DAG.getNode(ISD::BITCAST, dl,
6860 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
6861 Op.getOperand(0), Op.getOperand(1));
6862 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
6863 DAG.getValueType(VT));
6864 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
6867 if (VT == MVT::f32) {
6868 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
6869 // the result back to FR32 register. It's only worth matching if the
6870 // result has a single use which is a store or a bitcast to i32. And in
6871 // the case of a store, it's not worth it if the index is a constant 0,
6872 // because a MOVSSmr can be used instead, which is smaller and faster.
6873 if (!Op.hasOneUse())
6875 SDNode *User = *Op.getNode()->use_begin();
6876 if ((User->getOpcode() != ISD::STORE ||
6877 (isa<ConstantSDNode>(Op.getOperand(1)) &&
6878 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
6879 (User->getOpcode() != ISD::BITCAST ||
6880 User->getValueType(0) != MVT::i32))
6882 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
6883 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32,
6886 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, Extract);
6889 if (VT == MVT::i32 || VT == MVT::i64) {
6890 // ExtractPS/pextrq works with constant index.
6891 if (isa<ConstantSDNode>(Op.getOperand(1)))
6899 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
6900 SelectionDAG &DAG) const {
6901 if (!isa<ConstantSDNode>(Op.getOperand(1)))
6904 SDValue Vec = Op.getOperand(0);
6905 EVT VecVT = Vec.getValueType();
6907 // If this is a 256-bit vector result, first extract the 128-bit vector and
6908 // then extract the element from the 128-bit vector.
6909 if (VecVT.is256BitVector()) {
6910 DebugLoc dl = Op.getNode()->getDebugLoc();
6911 unsigned NumElems = VecVT.getVectorNumElements();
6912 SDValue Idx = Op.getOperand(1);
6913 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
6915 // Get the 128-bit vector.
6916 Vec = Extract128BitVector(Vec, IdxVal, DAG, dl);
6918 if (IdxVal >= NumElems/2)
6919 IdxVal -= NumElems/2;
6920 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec,
6921 DAG.getConstant(IdxVal, MVT::i32));
6924 assert(VecVT.is128BitVector() && "Unexpected vector length");
6926 if (Subtarget->hasSSE41()) {
6927 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG);
6932 EVT VT = Op.getValueType();
6933 DebugLoc dl = Op.getDebugLoc();
6934 // TODO: handle v16i8.
6935 if (VT.getSizeInBits() == 16) {
6936 SDValue Vec = Op.getOperand(0);
6937 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
6939 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
6940 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
6941 DAG.getNode(ISD::BITCAST, dl,
6944 // Transform it so it match pextrw which produces a 32-bit result.
6945 EVT EltVT = MVT::i32;
6946 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
6947 Op.getOperand(0), Op.getOperand(1));
6948 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
6949 DAG.getValueType(VT));
6950 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
6953 if (VT.getSizeInBits() == 32) {
6954 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
6958 // SHUFPS the element to the lowest double word, then movss.
6959 int Mask[4] = { static_cast<int>(Idx), -1, -1, -1 };
6960 EVT VVT = Op.getOperand(0).getValueType();
6961 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
6962 DAG.getUNDEF(VVT), Mask);
6963 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
6964 DAG.getIntPtrConstant(0));
6967 if (VT.getSizeInBits() == 64) {
6968 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
6969 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
6970 // to match extract_elt for f64.
6971 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
6975 // UNPCKHPD the element to the lowest double word, then movsd.
6976 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
6977 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
6978 int Mask[2] = { 1, -1 };
6979 EVT VVT = Op.getOperand(0).getValueType();
6980 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
6981 DAG.getUNDEF(VVT), Mask);
6982 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
6983 DAG.getIntPtrConstant(0));
6990 X86TargetLowering::LowerINSERT_VECTOR_ELT_SSE4(SDValue Op,
6991 SelectionDAG &DAG) const {
6992 EVT VT = Op.getValueType();
6993 EVT EltVT = VT.getVectorElementType();
6994 DebugLoc dl = Op.getDebugLoc();
6996 SDValue N0 = Op.getOperand(0);
6997 SDValue N1 = Op.getOperand(1);
6998 SDValue N2 = Op.getOperand(2);
7000 if (!VT.is128BitVector())
7003 if ((EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) &&
7004 isa<ConstantSDNode>(N2)) {
7006 if (VT == MVT::v8i16)
7007 Opc = X86ISD::PINSRW;
7008 else if (VT == MVT::v16i8)
7009 Opc = X86ISD::PINSRB;
7011 Opc = X86ISD::PINSRB;
7013 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
7015 if (N1.getValueType() != MVT::i32)
7016 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
7017 if (N2.getValueType() != MVT::i32)
7018 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
7019 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
7022 if (EltVT == MVT::f32 && isa<ConstantSDNode>(N2)) {
7023 // Bits [7:6] of the constant are the source select. This will always be
7024 // zero here. The DAG Combiner may combine an extract_elt index into these
7025 // bits. For example (insert (extract, 3), 2) could be matched by putting
7026 // the '3' into bits [7:6] of X86ISD::INSERTPS.
7027 // Bits [5:4] of the constant are the destination select. This is the
7028 // value of the incoming immediate.
7029 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
7030 // combine either bitwise AND or insert of float 0.0 to set these bits.
7031 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue() << 4);
7032 // Create this as a scalar to vector..
7033 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
7034 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
7037 if ((EltVT == MVT::i32 || EltVT == MVT::i64) && isa<ConstantSDNode>(N2)) {
7038 // PINSR* works with constant index.
7045 X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const {
7046 EVT VT = Op.getValueType();
7047 EVT EltVT = VT.getVectorElementType();
7049 DebugLoc dl = Op.getDebugLoc();
7050 SDValue N0 = Op.getOperand(0);
7051 SDValue N1 = Op.getOperand(1);
7052 SDValue N2 = Op.getOperand(2);
7054 // If this is a 256-bit vector result, first extract the 128-bit vector,
7055 // insert the element into the extracted half and then place it back.
7056 if (VT.is256BitVector()) {
7057 if (!isa<ConstantSDNode>(N2))
7060 // Get the desired 128-bit vector half.
7061 unsigned NumElems = VT.getVectorNumElements();
7062 unsigned IdxVal = cast<ConstantSDNode>(N2)->getZExtValue();
7063 SDValue V = Extract128BitVector(N0, IdxVal, DAG, dl);
7065 // Insert the element into the desired half.
7066 bool Upper = IdxVal >= NumElems/2;
7067 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V, N1,
7068 DAG.getConstant(Upper ? IdxVal-NumElems/2 : IdxVal, MVT::i32));
7070 // Insert the changed part back to the 256-bit vector
7071 return Insert128BitVector(N0, V, IdxVal, DAG, dl);
7074 if (Subtarget->hasSSE41())
7075 return LowerINSERT_VECTOR_ELT_SSE4(Op, DAG);
7077 if (EltVT == MVT::i8)
7080 if (EltVT.getSizeInBits() == 16 && isa<ConstantSDNode>(N2)) {
7081 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
7082 // as its second argument.
7083 if (N1.getValueType() != MVT::i32)
7084 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
7085 if (N2.getValueType() != MVT::i32)
7086 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
7087 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);
7093 X86TargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const {
7094 LLVMContext *Context = DAG.getContext();
7095 DebugLoc dl = Op.getDebugLoc();
7096 EVT OpVT = Op.getValueType();
7098 // If this is a 256-bit vector result, first insert into a 128-bit
7099 // vector and then insert into the 256-bit vector.
7100 if (!OpVT.is128BitVector()) {
7101 // Insert into a 128-bit vector.
7102 EVT VT128 = EVT::getVectorVT(*Context,
7103 OpVT.getVectorElementType(),
7104 OpVT.getVectorNumElements() / 2);
7106 Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Op.getOperand(0));
7108 // Insert the 128-bit vector.
7109 return Insert128BitVector(DAG.getUNDEF(OpVT), Op, 0, DAG, dl);
7112 if (OpVT == MVT::v1i64 &&
7113 Op.getOperand(0).getValueType() == MVT::i64)
7114 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
7116 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
7117 assert(OpVT.is128BitVector() && "Expected an SSE type!");
7118 return DAG.getNode(ISD::BITCAST, dl, OpVT,
7119 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,AnyExt));
7122 // Lower a node with an EXTRACT_SUBVECTOR opcode. This may result in
7123 // a simple subregister reference or explicit instructions to grab
7124 // upper bits of a vector.
7126 X86TargetLowering::LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const {
7127 if (Subtarget->hasAVX()) {
7128 DebugLoc dl = Op.getNode()->getDebugLoc();
7129 SDValue Vec = Op.getNode()->getOperand(0);
7130 SDValue Idx = Op.getNode()->getOperand(1);
7132 if (Op.getNode()->getValueType(0).is128BitVector() &&
7133 Vec.getNode()->getValueType(0).is256BitVector() &&
7134 isa<ConstantSDNode>(Idx)) {
7135 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
7136 return Extract128BitVector(Vec, IdxVal, DAG, dl);
7142 // Lower a node with an INSERT_SUBVECTOR opcode. This may result in a
7143 // simple superregister reference or explicit instructions to insert
7144 // the upper bits of a vector.
7146 X86TargetLowering::LowerINSERT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const {
7147 if (Subtarget->hasAVX()) {
7148 DebugLoc dl = Op.getNode()->getDebugLoc();
7149 SDValue Vec = Op.getNode()->getOperand(0);
7150 SDValue SubVec = Op.getNode()->getOperand(1);
7151 SDValue Idx = Op.getNode()->getOperand(2);
7153 if (Op.getNode()->getValueType(0).is256BitVector() &&
7154 SubVec.getNode()->getValueType(0).is128BitVector() &&
7155 isa<ConstantSDNode>(Idx)) {
7156 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
7157 return Insert128BitVector(Vec, SubVec, IdxVal, DAG, dl);
7163 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
7164 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
7165 // one of the above mentioned nodes. It has to be wrapped because otherwise
7166 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
7167 // be used to form addressing mode. These wrapped nodes will be selected
7170 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
7171 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
7173 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
7175 unsigned char OpFlag = 0;
7176 unsigned WrapperKind = X86ISD::Wrapper;
7177 CodeModel::Model M = getTargetMachine().getCodeModel();
7179 if (Subtarget->isPICStyleRIPRel() &&
7180 (M == CodeModel::Small || M == CodeModel::Kernel))
7181 WrapperKind = X86ISD::WrapperRIP;
7182 else if (Subtarget->isPICStyleGOT())
7183 OpFlag = X86II::MO_GOTOFF;
7184 else if (Subtarget->isPICStyleStubPIC())
7185 OpFlag = X86II::MO_PIC_BASE_OFFSET;
7187 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(),
7189 CP->getOffset(), OpFlag);
7190 DebugLoc DL = CP->getDebugLoc();
7191 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
7192 // With PIC, the address is actually $g + Offset.
7194 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7195 DAG.getNode(X86ISD::GlobalBaseReg,
7196 DebugLoc(), getPointerTy()),
7203 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
7204 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
7206 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
7208 unsigned char OpFlag = 0;
7209 unsigned WrapperKind = X86ISD::Wrapper;
7210 CodeModel::Model M = getTargetMachine().getCodeModel();
7212 if (Subtarget->isPICStyleRIPRel() &&
7213 (M == CodeModel::Small || M == CodeModel::Kernel))
7214 WrapperKind = X86ISD::WrapperRIP;
7215 else if (Subtarget->isPICStyleGOT())
7216 OpFlag = X86II::MO_GOTOFF;
7217 else if (Subtarget->isPICStyleStubPIC())
7218 OpFlag = X86II::MO_PIC_BASE_OFFSET;
7220 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(),
7222 DebugLoc DL = JT->getDebugLoc();
7223 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
7225 // With PIC, the address is actually $g + Offset.
7227 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7228 DAG.getNode(X86ISD::GlobalBaseReg,
7229 DebugLoc(), getPointerTy()),
7236 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const {
7237 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
7239 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
7241 unsigned char OpFlag = 0;
7242 unsigned WrapperKind = X86ISD::Wrapper;
7243 CodeModel::Model M = getTargetMachine().getCodeModel();
7245 if (Subtarget->isPICStyleRIPRel() &&
7246 (M == CodeModel::Small || M == CodeModel::Kernel)) {
7247 if (Subtarget->isTargetDarwin() || Subtarget->isTargetELF())
7248 OpFlag = X86II::MO_GOTPCREL;
7249 WrapperKind = X86ISD::WrapperRIP;
7250 } else if (Subtarget->isPICStyleGOT()) {
7251 OpFlag = X86II::MO_GOT;
7252 } else if (Subtarget->isPICStyleStubPIC()) {
7253 OpFlag = X86II::MO_DARWIN_NONLAZY_PIC_BASE;
7254 } else if (Subtarget->isPICStyleStubNoDynamic()) {
7255 OpFlag = X86II::MO_DARWIN_NONLAZY;
7258 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag);
7260 DebugLoc DL = Op.getDebugLoc();
7261 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
7264 // With PIC, the address is actually $g + Offset.
7265 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
7266 !Subtarget->is64Bit()) {
7267 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7268 DAG.getNode(X86ISD::GlobalBaseReg,
7269 DebugLoc(), getPointerTy()),
7273 // For symbols that require a load from a stub to get the address, emit the
7275 if (isGlobalStubReference(OpFlag))
7276 Result = DAG.getLoad(getPointerTy(), DL, DAG.getEntryNode(), Result,
7277 MachinePointerInfo::getGOT(), false, false, false, 0);
7283 X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
7284 // Create the TargetBlockAddressAddress node.
7285 unsigned char OpFlags =
7286 Subtarget->ClassifyBlockAddressReference();
7287 CodeModel::Model M = getTargetMachine().getCodeModel();
7288 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
7289 DebugLoc dl = Op.getDebugLoc();
7290 SDValue Result = DAG.getBlockAddress(BA, getPointerTy(),
7291 /*isTarget=*/true, OpFlags);
7293 if (Subtarget->isPICStyleRIPRel() &&
7294 (M == CodeModel::Small || M == CodeModel::Kernel))
7295 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
7297 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
7299 // With PIC, the address is actually $g + Offset.
7300 if (isGlobalRelativeToPICBase(OpFlags)) {
7301 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
7302 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
7310 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, DebugLoc dl,
7312 SelectionDAG &DAG) const {
7313 // Create the TargetGlobalAddress node, folding in the constant
7314 // offset if it is legal.
7315 unsigned char OpFlags =
7316 Subtarget->ClassifyGlobalReference(GV, getTargetMachine());
7317 CodeModel::Model M = getTargetMachine().getCodeModel();
7319 if (OpFlags == X86II::MO_NO_FLAG &&
7320 X86::isOffsetSuitableForCodeModel(Offset, M)) {
7321 // A direct static reference to a global.
7322 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), Offset);
7325 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags);
7328 if (Subtarget->isPICStyleRIPRel() &&
7329 (M == CodeModel::Small || M == CodeModel::Kernel))
7330 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
7332 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
7334 // With PIC, the address is actually $g + Offset.
7335 if (isGlobalRelativeToPICBase(OpFlags)) {
7336 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
7337 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
7341 // For globals that require a load from a stub to get the address, emit the
7343 if (isGlobalStubReference(OpFlags))
7344 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result,
7345 MachinePointerInfo::getGOT(), false, false, false, 0);
7347 // If there was a non-zero offset that we didn't fold, create an explicit
7350 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result,
7351 DAG.getConstant(Offset, getPointerTy()));
7357 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
7358 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
7359 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
7360 return LowerGlobalAddress(GV, Op.getDebugLoc(), Offset, DAG);
7364 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
7365 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg,
7366 unsigned char OperandFlags, bool LocalDynamic = false) {
7367 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
7368 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
7369 DebugLoc dl = GA->getDebugLoc();
7370 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
7371 GA->getValueType(0),
7375 X86ISD::NodeType CallType = LocalDynamic ? X86ISD::TLSBASEADDR
7379 SDValue Ops[] = { Chain, TGA, *InFlag };
7380 Chain = DAG.getNode(CallType, dl, NodeTys, Ops, 3);
7382 SDValue Ops[] = { Chain, TGA };
7383 Chain = DAG.getNode(CallType, dl, NodeTys, Ops, 2);
7386 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
7387 MFI->setAdjustsStack(true);
7389 SDValue Flag = Chain.getValue(1);
7390 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
7393 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
7395 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
7398 DebugLoc dl = GA->getDebugLoc(); // ? function entry point might be better
7399 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
7400 DAG.getNode(X86ISD::GlobalBaseReg,
7401 DebugLoc(), PtrVT), InFlag);
7402 InFlag = Chain.getValue(1);
7404 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
7407 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
7409 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
7411 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, NULL, PtrVT,
7412 X86::RAX, X86II::MO_TLSGD);
7415 static SDValue LowerToTLSLocalDynamicModel(GlobalAddressSDNode *GA,
7419 DebugLoc dl = GA->getDebugLoc();
7421 // Get the start address of the TLS block for this module.
7422 X86MachineFunctionInfo* MFI = DAG.getMachineFunction()
7423 .getInfo<X86MachineFunctionInfo>();
7424 MFI->incNumLocalDynamicTLSAccesses();
7428 Base = GetTLSADDR(DAG, DAG.getEntryNode(), GA, NULL, PtrVT, X86::RAX,
7429 X86II::MO_TLSLD, /*LocalDynamic=*/true);
7432 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
7433 DAG.getNode(X86ISD::GlobalBaseReg, DebugLoc(), PtrVT), InFlag);
7434 InFlag = Chain.getValue(1);
7435 Base = GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX,
7436 X86II::MO_TLSLDM, /*LocalDynamic=*/true);
7439 // Note: the CleanupLocalDynamicTLSPass will remove redundant computations
7443 unsigned char OperandFlags = X86II::MO_DTPOFF;
7444 unsigned WrapperKind = X86ISD::Wrapper;
7445 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
7446 GA->getValueType(0),
7447 GA->getOffset(), OperandFlags);
7448 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
7450 // Add x@dtpoff with the base.
7451 return DAG.getNode(ISD::ADD, dl, PtrVT, Offset, Base);
7454 // Lower ISD::GlobalTLSAddress using the "initial exec" or "local exec" model.
7455 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
7456 const EVT PtrVT, TLSModel::Model model,
7457 bool is64Bit, bool isPIC) {
7458 DebugLoc dl = GA->getDebugLoc();
7460 // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit).
7461 Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(*DAG.getContext(),
7462 is64Bit ? 257 : 256));
7464 SDValue ThreadPointer = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
7465 DAG.getIntPtrConstant(0),
7466 MachinePointerInfo(Ptr),
7467 false, false, false, 0);
7469 unsigned char OperandFlags = 0;
7470 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
7472 unsigned WrapperKind = X86ISD::Wrapper;
7473 if (model == TLSModel::LocalExec) {
7474 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
7475 } else if (model == TLSModel::InitialExec) {
7477 OperandFlags = X86II::MO_GOTTPOFF;
7478 WrapperKind = X86ISD::WrapperRIP;
7480 OperandFlags = isPIC ? X86II::MO_GOTNTPOFF : X86II::MO_INDNTPOFF;
7483 llvm_unreachable("Unexpected model");
7486 // emit "addl x@ntpoff,%eax" (local exec)
7487 // or "addl x@indntpoff,%eax" (initial exec)
7488 // or "addl x@gotntpoff(%ebx) ,%eax" (initial exec, 32-bit pic)
7489 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
7490 GA->getValueType(0),
7491 GA->getOffset(), OperandFlags);
7492 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
7494 if (model == TLSModel::InitialExec) {
7495 if (isPIC && !is64Bit) {
7496 Offset = DAG.getNode(ISD::ADD, dl, PtrVT,
7497 DAG.getNode(X86ISD::GlobalBaseReg, DebugLoc(), PtrVT),
7501 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
7502 MachinePointerInfo::getGOT(), false, false, false,
7506 // The address of the thread local variable is the add of the thread
7507 // pointer with the offset of the variable.
7508 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
7512 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
7514 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
7515 const GlobalValue *GV = GA->getGlobal();
7517 if (Subtarget->isTargetELF()) {
7518 TLSModel::Model model = getTargetMachine().getTLSModel(GV);
7521 case TLSModel::GeneralDynamic:
7522 if (Subtarget->is64Bit())
7523 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy());
7524 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy());
7525 case TLSModel::LocalDynamic:
7526 return LowerToTLSLocalDynamicModel(GA, DAG, getPointerTy(),
7527 Subtarget->is64Bit());
7528 case TLSModel::InitialExec:
7529 case TLSModel::LocalExec:
7530 return LowerToTLSExecModel(GA, DAG, getPointerTy(), model,
7531 Subtarget->is64Bit(),
7532 getTargetMachine().getRelocationModel() == Reloc::PIC_);
7534 llvm_unreachable("Unknown TLS model.");
7537 if (Subtarget->isTargetDarwin()) {
7538 // Darwin only has one model of TLS. Lower to that.
7539 unsigned char OpFlag = 0;
7540 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ?
7541 X86ISD::WrapperRIP : X86ISD::Wrapper;
7543 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
7545 bool PIC32 = (getTargetMachine().getRelocationModel() == Reloc::PIC_) &&
7546 !Subtarget->is64Bit();
7548 OpFlag = X86II::MO_TLVP_PIC_BASE;
7550 OpFlag = X86II::MO_TLVP;
7551 DebugLoc DL = Op.getDebugLoc();
7552 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL,
7553 GA->getValueType(0),
7554 GA->getOffset(), OpFlag);
7555 SDValue Offset = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
7557 // With PIC32, the address is actually $g + Offset.
7559 Offset = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7560 DAG.getNode(X86ISD::GlobalBaseReg,
7561 DebugLoc(), getPointerTy()),
7564 // Lowering the machine isd will make sure everything is in the right
7566 SDValue Chain = DAG.getEntryNode();
7567 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
7568 SDValue Args[] = { Chain, Offset };
7569 Chain = DAG.getNode(X86ISD::TLSCALL, DL, NodeTys, Args, 2);
7571 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls.
7572 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
7573 MFI->setAdjustsStack(true);
7575 // And our return value (tls address) is in the standard call return value
7577 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
7578 return DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(),
7582 if (Subtarget->isTargetWindows()) {
7583 // Just use the implicit TLS architecture
7584 // Need to generate someting similar to:
7585 // mov rdx, qword [gs:abs 58H]; Load pointer to ThreadLocalStorage
7587 // mov ecx, dword [rel _tls_index]: Load index (from C runtime)
7588 // mov rcx, qword [rdx+rcx*8]
7589 // mov eax, .tls$:tlsvar
7590 // [rax+rcx] contains the address
7591 // Windows 64bit: gs:0x58
7592 // Windows 32bit: fs:__tls_array
7594 // If GV is an alias then use the aliasee for determining
7595 // thread-localness.
7596 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV))
7597 GV = GA->resolveAliasedGlobal(false);
7598 DebugLoc dl = GA->getDebugLoc();
7599 SDValue Chain = DAG.getEntryNode();
7601 // Get the Thread Pointer, which is %fs:__tls_array (32-bit) or
7602 // %gs:0x58 (64-bit).
7603 Value *Ptr = Constant::getNullValue(Subtarget->is64Bit()
7604 ? Type::getInt8PtrTy(*DAG.getContext(),
7606 : Type::getInt32PtrTy(*DAG.getContext(),
7609 SDValue ThreadPointer = DAG.getLoad(getPointerTy(), dl, Chain,
7610 Subtarget->is64Bit()
7611 ? DAG.getIntPtrConstant(0x58)
7612 : DAG.getExternalSymbol("_tls_array",
7614 MachinePointerInfo(Ptr),
7615 false, false, false, 0);
7617 // Load the _tls_index variable
7618 SDValue IDX = DAG.getExternalSymbol("_tls_index", getPointerTy());
7619 if (Subtarget->is64Bit())
7620 IDX = DAG.getExtLoad(ISD::ZEXTLOAD, dl, getPointerTy(), Chain,
7621 IDX, MachinePointerInfo(), MVT::i32,
7624 IDX = DAG.getLoad(getPointerTy(), dl, Chain, IDX, MachinePointerInfo(),
7625 false, false, false, 0);
7627 SDValue Scale = DAG.getConstant(Log2_64_Ceil(TD->getPointerSize()),
7629 IDX = DAG.getNode(ISD::SHL, dl, getPointerTy(), IDX, Scale);
7631 SDValue res = DAG.getNode(ISD::ADD, dl, getPointerTy(), ThreadPointer, IDX);
7632 res = DAG.getLoad(getPointerTy(), dl, Chain, res, MachinePointerInfo(),
7633 false, false, false, 0);
7635 // Get the offset of start of .tls section
7636 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
7637 GA->getValueType(0),
7638 GA->getOffset(), X86II::MO_SECREL);
7639 SDValue Offset = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), TGA);
7641 // The address of the thread local variable is the add of the thread
7642 // pointer with the offset of the variable.
7643 return DAG.getNode(ISD::ADD, dl, getPointerTy(), res, Offset);
7646 llvm_unreachable("TLS not implemented for this target.");
7650 /// LowerShiftParts - Lower SRA_PARTS and friends, which return two i32 values
7651 /// and take a 2 x i32 value to shift plus a shift amount.
7652 SDValue X86TargetLowering::LowerShiftParts(SDValue Op, SelectionDAG &DAG) const{
7653 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
7654 EVT VT = Op.getValueType();
7655 unsigned VTBits = VT.getSizeInBits();
7656 DebugLoc dl = Op.getDebugLoc();
7657 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
7658 SDValue ShOpLo = Op.getOperand(0);
7659 SDValue ShOpHi = Op.getOperand(1);
7660 SDValue ShAmt = Op.getOperand(2);
7661 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
7662 DAG.getConstant(VTBits - 1, MVT::i8))
7663 : DAG.getConstant(0, VT);
7666 if (Op.getOpcode() == ISD::SHL_PARTS) {
7667 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
7668 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
7670 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
7671 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, ShAmt);
7674 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
7675 DAG.getConstant(VTBits, MVT::i8));
7676 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
7677 AndNode, DAG.getConstant(0, MVT::i8));
7680 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8);
7681 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
7682 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
7684 if (Op.getOpcode() == ISD::SHL_PARTS) {
7685 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
7686 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
7688 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
7689 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
7692 SDValue Ops[2] = { Lo, Hi };
7693 return DAG.getMergeValues(Ops, 2, dl);
7696 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op,
7697 SelectionDAG &DAG) const {
7698 EVT SrcVT = Op.getOperand(0).getValueType();
7700 if (SrcVT.isVector())
7703 assert(SrcVT.getSimpleVT() <= MVT::i64 && SrcVT.getSimpleVT() >= MVT::i16 &&
7704 "Unknown SINT_TO_FP to lower!");
7706 // These are really Legal; return the operand so the caller accepts it as
7708 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
7710 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
7711 Subtarget->is64Bit()) {
7715 DebugLoc dl = Op.getDebugLoc();
7716 unsigned Size = SrcVT.getSizeInBits()/8;
7717 MachineFunction &MF = DAG.getMachineFunction();
7718 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false);
7719 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
7720 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
7722 MachinePointerInfo::getFixedStack(SSFI),
7724 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
7727 SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
7729 SelectionDAG &DAG) const {
7731 DebugLoc DL = Op.getDebugLoc();
7733 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
7735 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Glue);
7737 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
7739 unsigned ByteSize = SrcVT.getSizeInBits()/8;
7741 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(StackSlot);
7742 MachineMemOperand *MMO;
7744 int SSFI = FI->getIndex();
7746 DAG.getMachineFunction()
7747 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
7748 MachineMemOperand::MOLoad, ByteSize, ByteSize);
7750 MMO = cast<LoadSDNode>(StackSlot)->getMemOperand();
7751 StackSlot = StackSlot.getOperand(1);
7753 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) };
7754 SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG :
7756 Tys, Ops, array_lengthof(Ops),
7760 Chain = Result.getValue(1);
7761 SDValue InFlag = Result.getValue(2);
7763 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
7764 // shouldn't be necessary except that RFP cannot be live across
7765 // multiple blocks. When stackifier is fixed, they can be uncoupled.
7766 MachineFunction &MF = DAG.getMachineFunction();
7767 unsigned SSFISize = Op.getValueType().getSizeInBits()/8;
7768 int SSFI = MF.getFrameInfo()->CreateStackObject(SSFISize, SSFISize, false);
7769 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
7770 Tys = DAG.getVTList(MVT::Other);
7772 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag
7774 MachineMemOperand *MMO =
7775 DAG.getMachineFunction()
7776 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
7777 MachineMemOperand::MOStore, SSFISize, SSFISize);
7779 Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys,
7780 Ops, array_lengthof(Ops),
7781 Op.getValueType(), MMO);
7782 Result = DAG.getLoad(Op.getValueType(), DL, Chain, StackSlot,
7783 MachinePointerInfo::getFixedStack(SSFI),
7784 false, false, false, 0);
7790 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
7791 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op,
7792 SelectionDAG &DAG) const {
7793 // This algorithm is not obvious. Here it is what we're trying to output:
7796 punpckldq (c0), %xmm0 // c0: (uint4){ 0x43300000U, 0x45300000U, 0U, 0U }
7797 subpd (c1), %xmm0 // c1: (double2){ 0x1.0p52, 0x1.0p52 * 0x1.0p32 }
7801 pshufd $0x4e, %xmm0, %xmm1
7806 DebugLoc dl = Op.getDebugLoc();
7807 LLVMContext *Context = DAG.getContext();
7809 // Build some magic constants.
7810 const uint32_t CV0[] = { 0x43300000, 0x45300000, 0, 0 };
7811 Constant *C0 = ConstantDataVector::get(*Context, CV0);
7812 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16);
7814 SmallVector<Constant*,2> CV1;
7816 ConstantFP::get(*Context, APFloat(APInt(64, 0x4330000000000000ULL))));
7818 ConstantFP::get(*Context, APFloat(APInt(64, 0x4530000000000000ULL))));
7819 Constant *C1 = ConstantVector::get(CV1);
7820 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16);
7822 // Load the 64-bit value into an XMM register.
7823 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
7825 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
7826 MachinePointerInfo::getConstantPool(),
7827 false, false, false, 16);
7828 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32,
7829 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, XR1),
7832 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
7833 MachinePointerInfo::getConstantPool(),
7834 false, false, false, 16);
7835 SDValue XR2F = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Unpck1);
7836 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
7839 if (Subtarget->hasSSE3()) {
7840 // FIXME: The 'haddpd' instruction may be slower than 'movhlps + addsd'.
7841 Result = DAG.getNode(X86ISD::FHADD, dl, MVT::v2f64, Sub, Sub);
7843 SDValue S2F = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Sub);
7844 SDValue Shuffle = getTargetShuffleNode(X86ISD::PSHUFD, dl, MVT::v4i32,
7846 Result = DAG.getNode(ISD::FADD, dl, MVT::v2f64,
7847 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Shuffle),
7851 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Result,
7852 DAG.getIntPtrConstant(0));
7855 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
7856 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op,
7857 SelectionDAG &DAG) const {
7858 DebugLoc dl = Op.getDebugLoc();
7859 // FP constant to bias correct the final result.
7860 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
7863 // Load the 32-bit value into an XMM register.
7864 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
7867 // Zero out the upper parts of the register.
7868 Load = getShuffleVectorZeroOrUndef(Load, 0, true, Subtarget, DAG);
7870 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
7871 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Load),
7872 DAG.getIntPtrConstant(0));
7874 // Or the load with the bias.
7875 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64,
7876 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
7877 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
7879 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
7880 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
7881 MVT::v2f64, Bias)));
7882 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
7883 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or),
7884 DAG.getIntPtrConstant(0));
7886 // Subtract the bias.
7887 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
7889 // Handle final rounding.
7890 EVT DestVT = Op.getValueType();
7892 if (DestVT.bitsLT(MVT::f64))
7893 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
7894 DAG.getIntPtrConstant(0));
7895 if (DestVT.bitsGT(MVT::f64))
7896 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
7898 // Handle final rounding.
7902 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op,
7903 SelectionDAG &DAG) const {
7904 SDValue N0 = Op.getOperand(0);
7905 DebugLoc dl = Op.getDebugLoc();
7907 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't
7908 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
7909 // the optimization here.
7910 if (DAG.SignBitIsZero(N0))
7911 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
7913 EVT SrcVT = N0.getValueType();
7914 EVT DstVT = Op.getValueType();
7915 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64)
7916 return LowerUINT_TO_FP_i64(Op, DAG);
7917 if (SrcVT == MVT::i32 && X86ScalarSSEf64)
7918 return LowerUINT_TO_FP_i32(Op, DAG);
7919 if (Subtarget->is64Bit() && SrcVT == MVT::i64 && DstVT == MVT::f32)
7922 // Make a 64-bit buffer, and use it to build an FILD.
7923 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
7924 if (SrcVT == MVT::i32) {
7925 SDValue WordOff = DAG.getConstant(4, getPointerTy());
7926 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl,
7927 getPointerTy(), StackSlot, WordOff);
7928 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
7929 StackSlot, MachinePointerInfo(),
7931 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32),
7932 OffsetSlot, MachinePointerInfo(),
7934 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
7938 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP");
7939 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
7940 StackSlot, MachinePointerInfo(),
7942 // For i64 source, we need to add the appropriate power of 2 if the input
7943 // was negative. This is the same as the optimization in
7944 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here,
7945 // we must be careful to do the computation in x87 extended precision, not
7946 // in SSE. (The generic code can't know it's OK to do this, or how to.)
7947 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex();
7948 MachineMemOperand *MMO =
7949 DAG.getMachineFunction()
7950 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
7951 MachineMemOperand::MOLoad, 8, 8);
7953 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other);
7954 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) };
7955 SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops, 3,
7958 APInt FF(32, 0x5F800000ULL);
7960 // Check whether the sign bit is set.
7961 SDValue SignSet = DAG.getSetCC(dl, getSetCCResultType(MVT::i64),
7962 Op.getOperand(0), DAG.getConstant(0, MVT::i64),
7965 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
7966 SDValue FudgePtr = DAG.getConstantPool(
7967 ConstantInt::get(*DAG.getContext(), FF.zext(64)),
7970 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
7971 SDValue Zero = DAG.getIntPtrConstant(0);
7972 SDValue Four = DAG.getIntPtrConstant(4);
7973 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
7975 FudgePtr = DAG.getNode(ISD::ADD, dl, getPointerTy(), FudgePtr, Offset);
7977 // Load the value out, extending it from f32 to f80.
7978 // FIXME: Avoid the extend by constructing the right constant pool?
7979 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, MVT::f80, DAG.getEntryNode(),
7980 FudgePtr, MachinePointerInfo::getConstantPool(),
7981 MVT::f32, false, false, 4);
7982 // Extend everything to 80 bits to force it to be done on x87.
7983 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge);
7984 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add, DAG.getIntPtrConstant(0));
7987 std::pair<SDValue,SDValue> X86TargetLowering::
7988 FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG, bool IsSigned, bool IsReplace) const {
7989 DebugLoc DL = Op.getDebugLoc();
7991 EVT DstTy = Op.getValueType();
7993 if (!IsSigned && !isIntegerTypeFTOL(DstTy)) {
7994 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
7998 assert(DstTy.getSimpleVT() <= MVT::i64 &&
7999 DstTy.getSimpleVT() >= MVT::i16 &&
8000 "Unknown FP_TO_INT to lower!");
8002 // These are really Legal.
8003 if (DstTy == MVT::i32 &&
8004 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
8005 return std::make_pair(SDValue(), SDValue());
8006 if (Subtarget->is64Bit() &&
8007 DstTy == MVT::i64 &&
8008 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
8009 return std::make_pair(SDValue(), SDValue());
8011 // We lower FP->int64 either into FISTP64 followed by a load from a temporary
8012 // stack slot, or into the FTOL runtime function.
8013 MachineFunction &MF = DAG.getMachineFunction();
8014 unsigned MemSize = DstTy.getSizeInBits()/8;
8015 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
8016 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
8019 if (!IsSigned && isIntegerTypeFTOL(DstTy))
8020 Opc = X86ISD::WIN_FTOL;
8022 switch (DstTy.getSimpleVT().SimpleTy) {
8023 default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
8024 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
8025 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
8026 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
8029 SDValue Chain = DAG.getEntryNode();
8030 SDValue Value = Op.getOperand(0);
8031 EVT TheVT = Op.getOperand(0).getValueType();
8032 // FIXME This causes a redundant load/store if the SSE-class value is already
8033 // in memory, such as if it is on the callstack.
8034 if (isScalarFPTypeInSSEReg(TheVT)) {
8035 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
8036 Chain = DAG.getStore(Chain, DL, Value, StackSlot,
8037 MachinePointerInfo::getFixedStack(SSFI),
8039 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
8041 Chain, StackSlot, DAG.getValueType(TheVT)
8044 MachineMemOperand *MMO =
8045 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
8046 MachineMemOperand::MOLoad, MemSize, MemSize);
8047 Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops, 3,
8049 Chain = Value.getValue(1);
8050 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
8051 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
8054 MachineMemOperand *MMO =
8055 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
8056 MachineMemOperand::MOStore, MemSize, MemSize);
8058 if (Opc != X86ISD::WIN_FTOL) {
8059 // Build the FP_TO_INT*_IN_MEM
8060 SDValue Ops[] = { Chain, Value, StackSlot };
8061 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
8062 Ops, 3, DstTy, MMO);
8063 return std::make_pair(FIST, StackSlot);
8065 SDValue ftol = DAG.getNode(X86ISD::WIN_FTOL, DL,
8066 DAG.getVTList(MVT::Other, MVT::Glue),
8068 SDValue eax = DAG.getCopyFromReg(ftol, DL, X86::EAX,
8069 MVT::i32, ftol.getValue(1));
8070 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), DL, X86::EDX,
8071 MVT::i32, eax.getValue(2));
8072 SDValue Ops[] = { eax, edx };
8073 SDValue pair = IsReplace
8074 ? DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops, 2)
8075 : DAG.getMergeValues(Ops, 2, DL);
8076 return std::make_pair(pair, SDValue());
8080 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op,
8081 SelectionDAG &DAG) const {
8082 if (Op.getValueType().isVector())
8085 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
8086 /*IsSigned=*/ true, /*IsReplace=*/ false);
8087 SDValue FIST = Vals.first, StackSlot = Vals.second;
8088 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
8089 if (FIST.getNode() == 0) return Op;
8091 if (StackSlot.getNode())
8093 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(),
8094 FIST, StackSlot, MachinePointerInfo(),
8095 false, false, false, 0);
8097 // The node is the result.
8101 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op,
8102 SelectionDAG &DAG) const {
8103 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
8104 /*IsSigned=*/ false, /*IsReplace=*/ false);
8105 SDValue FIST = Vals.first, StackSlot = Vals.second;
8106 assert(FIST.getNode() && "Unexpected failure");
8108 if (StackSlot.getNode())
8110 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(),
8111 FIST, StackSlot, MachinePointerInfo(),
8112 false, false, false, 0);
8114 // The node is the result.
8118 SDValue X86TargetLowering::LowerFABS(SDValue Op,
8119 SelectionDAG &DAG) const {
8120 LLVMContext *Context = DAG.getContext();
8121 DebugLoc dl = Op.getDebugLoc();
8122 EVT VT = Op.getValueType();
8125 EltVT = VT.getVectorElementType();
8127 if (EltVT == MVT::f64) {
8128 C = ConstantVector::getSplat(2,
8129 ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63)))));
8131 C = ConstantVector::getSplat(4,
8132 ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31)))));
8134 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
8135 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
8136 MachinePointerInfo::getConstantPool(),
8137 false, false, false, 16);
8138 return DAG.getNode(X86ISD::FAND, dl, VT, Op.getOperand(0), Mask);
8141 SDValue X86TargetLowering::LowerFNEG(SDValue Op, SelectionDAG &DAG) const {
8142 LLVMContext *Context = DAG.getContext();
8143 DebugLoc dl = Op.getDebugLoc();
8144 EVT VT = Op.getValueType();
8146 unsigned NumElts = VT == MVT::f64 ? 2 : 4;
8147 if (VT.isVector()) {
8148 EltVT = VT.getVectorElementType();
8149 NumElts = VT.getVectorNumElements();
8152 if (EltVT == MVT::f64)
8153 C = ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63)));
8155 C = ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31)));
8156 C = ConstantVector::getSplat(NumElts, C);
8157 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
8158 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
8159 MachinePointerInfo::getConstantPool(),
8160 false, false, false, 16);
8161 if (VT.isVector()) {
8162 MVT XORVT = VT.is128BitVector() ? MVT::v2i64 : MVT::v4i64;
8163 return DAG.getNode(ISD::BITCAST, dl, VT,
8164 DAG.getNode(ISD::XOR, dl, XORVT,
8165 DAG.getNode(ISD::BITCAST, dl, XORVT,
8167 DAG.getNode(ISD::BITCAST, dl, XORVT, Mask)));
8170 return DAG.getNode(X86ISD::FXOR, dl, VT, Op.getOperand(0), Mask);
8173 SDValue X86TargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {
8174 LLVMContext *Context = DAG.getContext();
8175 SDValue Op0 = Op.getOperand(0);
8176 SDValue Op1 = Op.getOperand(1);
8177 DebugLoc dl = Op.getDebugLoc();
8178 EVT VT = Op.getValueType();
8179 EVT SrcVT = Op1.getValueType();
8181 // If second operand is smaller, extend it first.
8182 if (SrcVT.bitsLT(VT)) {
8183 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
8186 // And if it is bigger, shrink it first.
8187 if (SrcVT.bitsGT(VT)) {
8188 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1));
8192 // At this point the operands and the result should have the same
8193 // type, and that won't be f80 since that is not custom lowered.
8195 // First get the sign bit of second operand.
8196 SmallVector<Constant*,4> CV;
8197 if (SrcVT == MVT::f64) {
8198 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63))));
8199 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0))));
8201 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31))));
8202 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
8203 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
8204 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
8206 Constant *C = ConstantVector::get(CV);
8207 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
8208 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx,
8209 MachinePointerInfo::getConstantPool(),
8210 false, false, false, 16);
8211 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1);
8213 // Shift sign bit right or left if the two operands have different types.
8214 if (SrcVT.bitsGT(VT)) {
8215 // Op0 is MVT::f32, Op1 is MVT::f64.
8216 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, SignBit);
8217 SignBit = DAG.getNode(X86ISD::FSRL, dl, MVT::v2f64, SignBit,
8218 DAG.getConstant(32, MVT::i32));
8219 SignBit = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, SignBit);
8220 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, SignBit,
8221 DAG.getIntPtrConstant(0));
8224 // Clear first operand sign bit.
8226 if (VT == MVT::f64) {
8227 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63)))));
8228 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0))));
8230 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31)))));
8231 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
8232 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
8233 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
8235 C = ConstantVector::get(CV);
8236 CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
8237 SDValue Mask2 = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
8238 MachinePointerInfo::getConstantPool(),
8239 false, false, false, 16);
8240 SDValue Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Mask2);
8242 // Or the value with the sign bit.
8243 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit);
8246 SDValue X86TargetLowering::LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) const {
8247 SDValue N0 = Op.getOperand(0);
8248 DebugLoc dl = Op.getDebugLoc();
8249 EVT VT = Op.getValueType();
8251 // Lower ISD::FGETSIGN to (AND (X86ISD::FGETSIGNx86 ...) 1).
8252 SDValue xFGETSIGN = DAG.getNode(X86ISD::FGETSIGNx86, dl, VT, N0,
8253 DAG.getConstant(1, VT));
8254 return DAG.getNode(ISD::AND, dl, VT, xFGETSIGN, DAG.getConstant(1, VT));
8257 /// Emit nodes that will be selected as "test Op0,Op0", or something
8259 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC,
8260 SelectionDAG &DAG) const {
8261 DebugLoc dl = Op.getDebugLoc();
8263 // CF and OF aren't always set the way we want. Determine which
8264 // of these we need.
8265 bool NeedCF = false;
8266 bool NeedOF = false;
8269 case X86::COND_A: case X86::COND_AE:
8270 case X86::COND_B: case X86::COND_BE:
8273 case X86::COND_G: case X86::COND_GE:
8274 case X86::COND_L: case X86::COND_LE:
8275 case X86::COND_O: case X86::COND_NO:
8280 // See if we can use the EFLAGS value from the operand instead of
8281 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
8282 // we prove that the arithmetic won't overflow, we can't use OF or CF.
8283 if (Op.getResNo() != 0 || NeedOF || NeedCF)
8284 // Emit a CMP with 0, which is the TEST pattern.
8285 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
8286 DAG.getConstant(0, Op.getValueType()));
8288 unsigned Opcode = 0;
8289 unsigned NumOperands = 0;
8291 // Truncate operations may prevent the merge of the SETCC instruction
8292 // and the arithmetic intruction before it. Attempt to truncate the operands
8293 // of the arithmetic instruction and use a reduced bit-width instruction.
8294 bool NeedTruncation = false;
8295 SDValue ArithOp = Op;
8296 if (Op->getOpcode() == ISD::TRUNCATE && Op->hasOneUse()) {
8297 SDValue Arith = Op->getOperand(0);
8298 // Both the trunc and the arithmetic op need to have one user each.
8299 if (Arith->hasOneUse())
8300 switch (Arith.getOpcode()) {
8307 NeedTruncation = true;
8313 // NOTICE: In the code below we use ArithOp to hold the arithmetic operation
8314 // which may be the result of a CAST. We use the variable 'Op', which is the
8315 // non-casted variable when we check for possible users.
8316 switch (ArithOp.getOpcode()) {
8318 // Due to an isel shortcoming, be conservative if this add is likely to be
8319 // selected as part of a load-modify-store instruction. When the root node
8320 // in a match is a store, isel doesn't know how to remap non-chain non-flag
8321 // uses of other nodes in the match, such as the ADD in this case. This
8322 // leads to the ADD being left around and reselected, with the result being
8323 // two adds in the output. Alas, even if none our users are stores, that
8324 // doesn't prove we're O.K. Ergo, if we have any parents that aren't
8325 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require
8326 // climbing the DAG back to the root, and it doesn't seem to be worth the
8328 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
8329 UE = Op.getNode()->use_end(); UI != UE; ++UI)
8330 if (UI->getOpcode() != ISD::CopyToReg &&
8331 UI->getOpcode() != ISD::SETCC &&
8332 UI->getOpcode() != ISD::STORE)
8335 if (ConstantSDNode *C =
8336 dyn_cast<ConstantSDNode>(ArithOp.getNode()->getOperand(1))) {
8337 // An add of one will be selected as an INC.
8338 if (C->getAPIntValue() == 1) {
8339 Opcode = X86ISD::INC;
8344 // An add of negative one (subtract of one) will be selected as a DEC.
8345 if (C->getAPIntValue().isAllOnesValue()) {
8346 Opcode = X86ISD::DEC;
8352 // Otherwise use a regular EFLAGS-setting add.
8353 Opcode = X86ISD::ADD;
8357 // If the primary and result isn't used, don't bother using X86ISD::AND,
8358 // because a TEST instruction will be better.
8359 bool NonFlagUse = false;
8360 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
8361 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
8363 unsigned UOpNo = UI.getOperandNo();
8364 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
8365 // Look pass truncate.
8366 UOpNo = User->use_begin().getOperandNo();
8367 User = *User->use_begin();
8370 if (User->getOpcode() != ISD::BRCOND &&
8371 User->getOpcode() != ISD::SETCC &&
8372 !(User->getOpcode() == ISD::SELECT && UOpNo == 0)) {
8385 // Due to the ISEL shortcoming noted above, be conservative if this op is
8386 // likely to be selected as part of a load-modify-store instruction.
8387 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
8388 UE = Op.getNode()->use_end(); UI != UE; ++UI)
8389 if (UI->getOpcode() == ISD::STORE)
8392 // Otherwise use a regular EFLAGS-setting instruction.
8393 switch (ArithOp.getOpcode()) {
8394 default: llvm_unreachable("unexpected operator!");
8395 case ISD::SUB: Opcode = X86ISD::SUB; break;
8396 case ISD::OR: Opcode = X86ISD::OR; break;
8397 case ISD::XOR: Opcode = X86ISD::XOR; break;
8398 case ISD::AND: Opcode = X86ISD::AND; break;
8410 return SDValue(Op.getNode(), 1);
8416 // If we found that truncation is beneficial, perform the truncation and
8418 if (NeedTruncation) {
8419 EVT VT = Op.getValueType();
8420 SDValue WideVal = Op->getOperand(0);
8421 EVT WideVT = WideVal.getValueType();
8422 unsigned ConvertedOp = 0;
8423 // Use a target machine opcode to prevent further DAGCombine
8424 // optimizations that may separate the arithmetic operations
8425 // from the setcc node.
8426 switch (WideVal.getOpcode()) {
8428 case ISD::ADD: ConvertedOp = X86ISD::ADD; break;
8429 case ISD::SUB: ConvertedOp = X86ISD::SUB; break;
8430 case ISD::AND: ConvertedOp = X86ISD::AND; break;
8431 case ISD::OR: ConvertedOp = X86ISD::OR; break;
8432 case ISD::XOR: ConvertedOp = X86ISD::XOR; break;
8436 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
8437 if (TLI.isOperationLegal(WideVal.getOpcode(), WideVT)) {
8438 SDValue V0 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(0));
8439 SDValue V1 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(1));
8440 Op = DAG.getNode(ConvertedOp, dl, VT, V0, V1);
8446 // Emit a CMP with 0, which is the TEST pattern.
8447 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
8448 DAG.getConstant(0, Op.getValueType()));
8450 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
8451 SmallVector<SDValue, 4> Ops;
8452 for (unsigned i = 0; i != NumOperands; ++i)
8453 Ops.push_back(Op.getOperand(i));
8455 SDValue New = DAG.getNode(Opcode, dl, VTs, &Ops[0], NumOperands);
8456 DAG.ReplaceAllUsesWith(Op, New);
8457 return SDValue(New.getNode(), 1);
8460 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
8462 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
8463 SelectionDAG &DAG) const {
8464 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1))
8465 if (C->getAPIntValue() == 0)
8466 return EmitTest(Op0, X86CC, DAG);
8468 DebugLoc dl = Op0.getDebugLoc();
8469 if ((Op0.getValueType() == MVT::i8 || Op0.getValueType() == MVT::i16 ||
8470 Op0.getValueType() == MVT::i32 || Op0.getValueType() == MVT::i64)) {
8471 // Use SUB instead of CMP to enable CSE between SUB and CMP.
8472 SDVTList VTs = DAG.getVTList(Op0.getValueType(), MVT::i32);
8473 SDValue Sub = DAG.getNode(X86ISD::SUB, dl, VTs,
8475 return SDValue(Sub.getNode(), 1);
8477 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
8480 /// Convert a comparison if required by the subtarget.
8481 SDValue X86TargetLowering::ConvertCmpIfNecessary(SDValue Cmp,
8482 SelectionDAG &DAG) const {
8483 // If the subtarget does not support the FUCOMI instruction, floating-point
8484 // comparisons have to be converted.
8485 if (Subtarget->hasCMov() ||
8486 Cmp.getOpcode() != X86ISD::CMP ||
8487 !Cmp.getOperand(0).getValueType().isFloatingPoint() ||
8488 !Cmp.getOperand(1).getValueType().isFloatingPoint())
8491 // The instruction selector will select an FUCOM instruction instead of
8492 // FUCOMI, which writes the comparison result to FPSW instead of EFLAGS. Hence
8493 // build an SDNode sequence that transfers the result from FPSW into EFLAGS:
8494 // (X86sahf (trunc (srl (X86fp_stsw (trunc (X86cmp ...)), 8))))
8495 DebugLoc dl = Cmp.getDebugLoc();
8496 SDValue TruncFPSW = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, Cmp);
8497 SDValue FNStSW = DAG.getNode(X86ISD::FNSTSW16r, dl, MVT::i16, TruncFPSW);
8498 SDValue Srl = DAG.getNode(ISD::SRL, dl, MVT::i16, FNStSW,
8499 DAG.getConstant(8, MVT::i8));
8500 SDValue TruncSrl = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Srl);
8501 return DAG.getNode(X86ISD::SAHF, dl, MVT::i32, TruncSrl);
8504 /// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node
8505 /// if it's possible.
8506 SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC,
8507 DebugLoc dl, SelectionDAG &DAG) const {
8508 SDValue Op0 = And.getOperand(0);
8509 SDValue Op1 = And.getOperand(1);
8510 if (Op0.getOpcode() == ISD::TRUNCATE)
8511 Op0 = Op0.getOperand(0);
8512 if (Op1.getOpcode() == ISD::TRUNCATE)
8513 Op1 = Op1.getOperand(0);
8516 if (Op1.getOpcode() == ISD::SHL)
8517 std::swap(Op0, Op1);
8518 if (Op0.getOpcode() == ISD::SHL) {
8519 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0)))
8520 if (And00C->getZExtValue() == 1) {
8521 // If we looked past a truncate, check that it's only truncating away
8523 unsigned BitWidth = Op0.getValueSizeInBits();
8524 unsigned AndBitWidth = And.getValueSizeInBits();
8525 if (BitWidth > AndBitWidth) {
8527 DAG.ComputeMaskedBits(Op0, Zeros, Ones);
8528 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth)
8532 RHS = Op0.getOperand(1);
8534 } else if (Op1.getOpcode() == ISD::Constant) {
8535 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1);
8536 uint64_t AndRHSVal = AndRHS->getZExtValue();
8537 SDValue AndLHS = Op0;
8539 if (AndRHSVal == 1 && AndLHS.getOpcode() == ISD::SRL) {
8540 LHS = AndLHS.getOperand(0);
8541 RHS = AndLHS.getOperand(1);
8544 // Use BT if the immediate can't be encoded in a TEST instruction.
8545 if (!isUInt<32>(AndRHSVal) && isPowerOf2_64(AndRHSVal)) {
8547 RHS = DAG.getConstant(Log2_64_Ceil(AndRHSVal), LHS.getValueType());
8551 if (LHS.getNode()) {
8552 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT
8553 // instruction. Since the shift amount is in-range-or-undefined, we know
8554 // that doing a bittest on the i32 value is ok. We extend to i32 because
8555 // the encoding for the i16 version is larger than the i32 version.
8556 // Also promote i16 to i32 for performance / code size reason.
8557 if (LHS.getValueType() == MVT::i8 ||
8558 LHS.getValueType() == MVT::i16)
8559 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
8561 // If the operand types disagree, extend the shift amount to match. Since
8562 // BT ignores high bits (like shifts) we can use anyextend.
8563 if (LHS.getValueType() != RHS.getValueType())
8564 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
8566 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
8567 unsigned Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
8568 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
8569 DAG.getConstant(Cond, MVT::i8), BT);
8575 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
8577 if (Op.getValueType().isVector()) return LowerVSETCC(Op, DAG);
8579 assert(Op.getValueType() == MVT::i8 && "SetCC type must be 8-bit integer");
8580 SDValue Op0 = Op.getOperand(0);
8581 SDValue Op1 = Op.getOperand(1);
8582 DebugLoc dl = Op.getDebugLoc();
8583 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
8585 // Optimize to BT if possible.
8586 // Lower (X & (1 << N)) == 0 to BT(X, N).
8587 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
8588 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
8589 if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() &&
8590 Op1.getOpcode() == ISD::Constant &&
8591 cast<ConstantSDNode>(Op1)->isNullValue() &&
8592 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
8593 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG);
8594 if (NewSetCC.getNode())
8598 // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of
8600 if (Op1.getOpcode() == ISD::Constant &&
8601 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 ||
8602 cast<ConstantSDNode>(Op1)->isNullValue()) &&
8603 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
8605 // If the input is a setcc, then reuse the input setcc or use a new one with
8606 // the inverted condition.
8607 if (Op0.getOpcode() == X86ISD::SETCC) {
8608 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0);
8609 bool Invert = (CC == ISD::SETNE) ^
8610 cast<ConstantSDNode>(Op1)->isNullValue();
8611 if (!Invert) return Op0;
8613 CCode = X86::GetOppositeBranchCondition(CCode);
8614 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
8615 DAG.getConstant(CCode, MVT::i8), Op0.getOperand(1));
8619 bool isFP = Op1.getValueType().isFloatingPoint();
8620 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG);
8621 if (X86CC == X86::COND_INVALID)
8624 SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, DAG);
8625 EFLAGS = ConvertCmpIfNecessary(EFLAGS, DAG);
8626 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
8627 DAG.getConstant(X86CC, MVT::i8), EFLAGS);
8630 // Lower256IntVSETCC - Break a VSETCC 256-bit integer VSETCC into two new 128
8631 // ones, and then concatenate the result back.
8632 static SDValue Lower256IntVSETCC(SDValue Op, SelectionDAG &DAG) {
8633 EVT VT = Op.getValueType();
8635 assert(VT.is256BitVector() && Op.getOpcode() == ISD::SETCC &&
8636 "Unsupported value type for operation");
8638 unsigned NumElems = VT.getVectorNumElements();
8639 DebugLoc dl = Op.getDebugLoc();
8640 SDValue CC = Op.getOperand(2);
8642 // Extract the LHS vectors
8643 SDValue LHS = Op.getOperand(0);
8644 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
8645 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
8647 // Extract the RHS vectors
8648 SDValue RHS = Op.getOperand(1);
8649 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
8650 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
8652 // Issue the operation on the smaller types and concatenate the result back
8653 MVT EltVT = VT.getVectorElementType().getSimpleVT();
8654 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
8655 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
8656 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1, CC),
8657 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC));
8661 SDValue X86TargetLowering::LowerVSETCC(SDValue Op, SelectionDAG &DAG) const {
8663 SDValue Op0 = Op.getOperand(0);
8664 SDValue Op1 = Op.getOperand(1);
8665 SDValue CC = Op.getOperand(2);
8666 EVT VT = Op.getValueType();
8667 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
8668 bool isFP = Op.getOperand(1).getValueType().isFloatingPoint();
8669 DebugLoc dl = Op.getDebugLoc();
8673 EVT EltVT = Op0.getValueType().getVectorElementType();
8674 assert(EltVT == MVT::f32 || EltVT == MVT::f64);
8680 // SSE Condition code mapping:
8689 switch (SetCCOpcode) {
8690 default: llvm_unreachable("Unexpected SETCC condition");
8692 case ISD::SETEQ: SSECC = 0; break;
8694 case ISD::SETGT: Swap = true; // Fallthrough
8696 case ISD::SETOLT: SSECC = 1; break;
8698 case ISD::SETGE: Swap = true; // Fallthrough
8700 case ISD::SETOLE: SSECC = 2; break;
8701 case ISD::SETUO: SSECC = 3; break;
8703 case ISD::SETNE: SSECC = 4; break;
8704 case ISD::SETULE: Swap = true; // Fallthrough
8705 case ISD::SETUGE: SSECC = 5; break;
8706 case ISD::SETULT: Swap = true; // Fallthrough
8707 case ISD::SETUGT: SSECC = 6; break;
8708 case ISD::SETO: SSECC = 7; break;
8710 case ISD::SETONE: SSECC = 8; break;
8713 std::swap(Op0, Op1);
8715 // In the two special cases we can't handle, emit two comparisons.
8718 unsigned CombineOpc;
8719 if (SetCCOpcode == ISD::SETUEQ) {
8720 CC0 = 3; CC1 = 0; CombineOpc = ISD::OR;
8722 assert(SetCCOpcode == ISD::SETONE);
8723 CC0 = 7; CC1 = 4; CombineOpc = ISD::AND;
8726 SDValue Cmp0 = DAG.getNode(X86ISD::CMPP, dl, VT, Op0, Op1,
8727 DAG.getConstant(CC0, MVT::i8));
8728 SDValue Cmp1 = DAG.getNode(X86ISD::CMPP, dl, VT, Op0, Op1,
8729 DAG.getConstant(CC1, MVT::i8));
8730 return DAG.getNode(CombineOpc, dl, VT, Cmp0, Cmp1);
8732 // Handle all other FP comparisons here.
8733 return DAG.getNode(X86ISD::CMPP, dl, VT, Op0, Op1,
8734 DAG.getConstant(SSECC, MVT::i8));
8737 // Break 256-bit integer vector compare into smaller ones.
8738 if (VT.is256BitVector() && !Subtarget->hasAVX2())
8739 return Lower256IntVSETCC(Op, DAG);
8741 // We are handling one of the integer comparisons here. Since SSE only has
8742 // GT and EQ comparisons for integer, swapping operands and multiple
8743 // operations may be required for some comparisons.
8745 bool Swap = false, Invert = false, FlipSigns = false;
8747 switch (SetCCOpcode) {
8748 default: llvm_unreachable("Unexpected SETCC condition");
8749 case ISD::SETNE: Invert = true;
8750 case ISD::SETEQ: Opc = X86ISD::PCMPEQ; break;
8751 case ISD::SETLT: Swap = true;
8752 case ISD::SETGT: Opc = X86ISD::PCMPGT; break;
8753 case ISD::SETGE: Swap = true;
8754 case ISD::SETLE: Opc = X86ISD::PCMPGT; Invert = true; break;
8755 case ISD::SETULT: Swap = true;
8756 case ISD::SETUGT: Opc = X86ISD::PCMPGT; FlipSigns = true; break;
8757 case ISD::SETUGE: Swap = true;
8758 case ISD::SETULE: Opc = X86ISD::PCMPGT; FlipSigns = true; Invert = true; break;
8761 std::swap(Op0, Op1);
8763 // Check that the operation in question is available (most are plain SSE2,
8764 // but PCMPGTQ and PCMPEQQ have different requirements).
8765 if (VT == MVT::v2i64) {
8766 if (Opc == X86ISD::PCMPGT && !Subtarget->hasSSE42())
8768 if (Opc == X86ISD::PCMPEQ && !Subtarget->hasSSE41())
8772 // Since SSE has no unsigned integer comparisons, we need to flip the sign
8773 // bits of the inputs before performing those operations.
8775 EVT EltVT = VT.getVectorElementType();
8776 SDValue SignBit = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()),
8778 std::vector<SDValue> SignBits(VT.getVectorNumElements(), SignBit);
8779 SDValue SignVec = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &SignBits[0],
8781 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SignVec);
8782 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SignVec);
8785 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
8787 // If the logical-not of the result is required, perform that now.
8789 Result = DAG.getNOT(dl, Result, VT);
8794 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
8795 static bool isX86LogicalCmp(SDValue Op) {
8796 unsigned Opc = Op.getNode()->getOpcode();
8797 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI ||
8798 Opc == X86ISD::SAHF)
8800 if (Op.getResNo() == 1 &&
8801 (Opc == X86ISD::ADD ||
8802 Opc == X86ISD::SUB ||
8803 Opc == X86ISD::ADC ||
8804 Opc == X86ISD::SBB ||
8805 Opc == X86ISD::SMUL ||
8806 Opc == X86ISD::UMUL ||
8807 Opc == X86ISD::INC ||
8808 Opc == X86ISD::DEC ||
8809 Opc == X86ISD::OR ||
8810 Opc == X86ISD::XOR ||
8811 Opc == X86ISD::AND))
8814 if (Op.getResNo() == 2 && Opc == X86ISD::UMUL)
8820 static bool isZero(SDValue V) {
8821 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
8822 return C && C->isNullValue();
8825 static bool isAllOnes(SDValue V) {
8826 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
8827 return C && C->isAllOnesValue();
8830 static bool isTruncWithZeroHighBitsInput(SDValue V, SelectionDAG &DAG) {
8831 if (V.getOpcode() != ISD::TRUNCATE)
8834 SDValue VOp0 = V.getOperand(0);
8835 unsigned InBits = VOp0.getValueSizeInBits();
8836 unsigned Bits = V.getValueSizeInBits();
8837 return DAG.MaskedValueIsZero(VOp0, APInt::getHighBitsSet(InBits,InBits-Bits));
8840 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
8841 bool addTest = true;
8842 SDValue Cond = Op.getOperand(0);
8843 SDValue Op1 = Op.getOperand(1);
8844 SDValue Op2 = Op.getOperand(2);
8845 DebugLoc DL = Op.getDebugLoc();
8848 if (Cond.getOpcode() == ISD::SETCC) {
8849 SDValue NewCond = LowerSETCC(Cond, DAG);
8850 if (NewCond.getNode())
8854 // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y
8855 // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y
8856 // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y
8857 // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y
8858 if (Cond.getOpcode() == X86ISD::SETCC &&
8859 Cond.getOperand(1).getOpcode() == X86ISD::CMP &&
8860 isZero(Cond.getOperand(1).getOperand(1))) {
8861 SDValue Cmp = Cond.getOperand(1);
8863 unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue();
8865 if ((isAllOnes(Op1) || isAllOnes(Op2)) &&
8866 (CondCode == X86::COND_E || CondCode == X86::COND_NE)) {
8867 SDValue Y = isAllOnes(Op2) ? Op1 : Op2;
8869 SDValue CmpOp0 = Cmp.getOperand(0);
8870 // Apply further optimizations for special cases
8871 // (select (x != 0), -1, 0) -> neg & sbb
8872 // (select (x == 0), 0, -1) -> neg & sbb
8873 if (ConstantSDNode *YC = dyn_cast<ConstantSDNode>(Y))
8874 if (YC->isNullValue() &&
8875 (isAllOnes(Op1) == (CondCode == X86::COND_NE))) {
8876 SDVTList VTs = DAG.getVTList(CmpOp0.getValueType(), MVT::i32);
8877 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, VTs,
8878 DAG.getConstant(0, CmpOp0.getValueType()),
8880 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
8881 DAG.getConstant(X86::COND_B, MVT::i8),
8882 SDValue(Neg.getNode(), 1));
8886 Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32,
8887 CmpOp0, DAG.getConstant(1, CmpOp0.getValueType()));
8888 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
8890 SDValue Res = // Res = 0 or -1.
8891 DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
8892 DAG.getConstant(X86::COND_B, MVT::i8), Cmp);
8894 if (isAllOnes(Op1) != (CondCode == X86::COND_E))
8895 Res = DAG.getNOT(DL, Res, Res.getValueType());
8897 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2);
8898 if (N2C == 0 || !N2C->isNullValue())
8899 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y);
8904 // Look past (and (setcc_carry (cmp ...)), 1).
8905 if (Cond.getOpcode() == ISD::AND &&
8906 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
8907 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
8908 if (C && C->getAPIntValue() == 1)
8909 Cond = Cond.getOperand(0);
8912 // If condition flag is set by a X86ISD::CMP, then use it as the condition
8913 // setting operand in place of the X86ISD::SETCC.
8914 unsigned CondOpcode = Cond.getOpcode();
8915 if (CondOpcode == X86ISD::SETCC ||
8916 CondOpcode == X86ISD::SETCC_CARRY) {
8917 CC = Cond.getOperand(0);
8919 SDValue Cmp = Cond.getOperand(1);
8920 unsigned Opc = Cmp.getOpcode();
8921 EVT VT = Op.getValueType();
8923 bool IllegalFPCMov = false;
8924 if (VT.isFloatingPoint() && !VT.isVector() &&
8925 !isScalarFPTypeInSSEReg(VT)) // FPStack?
8926 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
8928 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
8929 Opc == X86ISD::BT) { // FIXME
8933 } else if (CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
8934 CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
8935 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
8936 Cond.getOperand(0).getValueType() != MVT::i8)) {
8937 SDValue LHS = Cond.getOperand(0);
8938 SDValue RHS = Cond.getOperand(1);
8942 switch (CondOpcode) {
8943 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
8944 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
8945 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
8946 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
8947 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
8948 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
8949 default: llvm_unreachable("unexpected overflowing operator");
8951 if (CondOpcode == ISD::UMULO)
8952 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
8955 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
8957 SDValue X86Op = DAG.getNode(X86Opcode, DL, VTs, LHS, RHS);
8959 if (CondOpcode == ISD::UMULO)
8960 Cond = X86Op.getValue(2);
8962 Cond = X86Op.getValue(1);
8964 CC = DAG.getConstant(X86Cond, MVT::i8);
8969 // Look pass the truncate if the high bits are known zero.
8970 if (isTruncWithZeroHighBitsInput(Cond, DAG))
8971 Cond = Cond.getOperand(0);
8973 // We know the result of AND is compared against zero. Try to match
8975 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
8976 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG);
8977 if (NewSetCC.getNode()) {
8978 CC = NewSetCC.getOperand(0);
8979 Cond = NewSetCC.getOperand(1);
8986 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
8987 Cond = EmitTest(Cond, X86::COND_NE, DAG);
8990 // a < b ? -1 : 0 -> RES = ~setcc_carry
8991 // a < b ? 0 : -1 -> RES = setcc_carry
8992 // a >= b ? -1 : 0 -> RES = setcc_carry
8993 // a >= b ? 0 : -1 -> RES = ~setcc_carry
8994 if (Cond.getOpcode() == X86ISD::SUB) {
8995 Cond = ConvertCmpIfNecessary(Cond, DAG);
8996 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue();
8998 if ((CondCode == X86::COND_AE || CondCode == X86::COND_B) &&
8999 (isAllOnes(Op1) || isAllOnes(Op2)) && (isZero(Op1) || isZero(Op2))) {
9000 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
9001 DAG.getConstant(X86::COND_B, MVT::i8), Cond);
9002 if (isAllOnes(Op1) != (CondCode == X86::COND_B))
9003 return DAG.getNOT(DL, Res, Res.getValueType());
9008 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
9009 // condition is true.
9010 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
9011 SDValue Ops[] = { Op2, Op1, CC, Cond };
9012 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops, array_lengthof(Ops));
9015 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
9016 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
9017 // from the AND / OR.
9018 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
9019 Opc = Op.getOpcode();
9020 if (Opc != ISD::OR && Opc != ISD::AND)
9022 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
9023 Op.getOperand(0).hasOneUse() &&
9024 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
9025 Op.getOperand(1).hasOneUse());
9028 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
9029 // 1 and that the SETCC node has a single use.
9030 static bool isXor1OfSetCC(SDValue Op) {
9031 if (Op.getOpcode() != ISD::XOR)
9033 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
9034 if (N1C && N1C->getAPIntValue() == 1) {
9035 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
9036 Op.getOperand(0).hasOneUse();
9041 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
9042 bool addTest = true;
9043 SDValue Chain = Op.getOperand(0);
9044 SDValue Cond = Op.getOperand(1);
9045 SDValue Dest = Op.getOperand(2);
9046 DebugLoc dl = Op.getDebugLoc();
9048 bool Inverted = false;
9050 if (Cond.getOpcode() == ISD::SETCC) {
9051 // Check for setcc([su]{add,sub,mul}o == 0).
9052 if (cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETEQ &&
9053 isa<ConstantSDNode>(Cond.getOperand(1)) &&
9054 cast<ConstantSDNode>(Cond.getOperand(1))->isNullValue() &&
9055 Cond.getOperand(0).getResNo() == 1 &&
9056 (Cond.getOperand(0).getOpcode() == ISD::SADDO ||
9057 Cond.getOperand(0).getOpcode() == ISD::UADDO ||
9058 Cond.getOperand(0).getOpcode() == ISD::SSUBO ||
9059 Cond.getOperand(0).getOpcode() == ISD::USUBO ||
9060 Cond.getOperand(0).getOpcode() == ISD::SMULO ||
9061 Cond.getOperand(0).getOpcode() == ISD::UMULO)) {
9063 Cond = Cond.getOperand(0);
9065 SDValue NewCond = LowerSETCC(Cond, DAG);
9066 if (NewCond.getNode())
9071 // FIXME: LowerXALUO doesn't handle these!!
9072 else if (Cond.getOpcode() == X86ISD::ADD ||
9073 Cond.getOpcode() == X86ISD::SUB ||
9074 Cond.getOpcode() == X86ISD::SMUL ||
9075 Cond.getOpcode() == X86ISD::UMUL)
9076 Cond = LowerXALUO(Cond, DAG);
9079 // Look pass (and (setcc_carry (cmp ...)), 1).
9080 if (Cond.getOpcode() == ISD::AND &&
9081 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
9082 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
9083 if (C && C->getAPIntValue() == 1)
9084 Cond = Cond.getOperand(0);
9087 // If condition flag is set by a X86ISD::CMP, then use it as the condition
9088 // setting operand in place of the X86ISD::SETCC.
9089 unsigned CondOpcode = Cond.getOpcode();
9090 if (CondOpcode == X86ISD::SETCC ||
9091 CondOpcode == X86ISD::SETCC_CARRY) {
9092 CC = Cond.getOperand(0);
9094 SDValue Cmp = Cond.getOperand(1);
9095 unsigned Opc = Cmp.getOpcode();
9096 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
9097 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
9101 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
9105 // These can only come from an arithmetic instruction with overflow,
9106 // e.g. SADDO, UADDO.
9107 Cond = Cond.getNode()->getOperand(1);
9113 CondOpcode = Cond.getOpcode();
9114 if (CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
9115 CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
9116 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
9117 Cond.getOperand(0).getValueType() != MVT::i8)) {
9118 SDValue LHS = Cond.getOperand(0);
9119 SDValue RHS = Cond.getOperand(1);
9123 switch (CondOpcode) {
9124 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
9125 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
9126 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
9127 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
9128 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
9129 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
9130 default: llvm_unreachable("unexpected overflowing operator");
9133 X86Cond = X86::GetOppositeBranchCondition((X86::CondCode)X86Cond);
9134 if (CondOpcode == ISD::UMULO)
9135 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
9138 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
9140 SDValue X86Op = DAG.getNode(X86Opcode, dl, VTs, LHS, RHS);
9142 if (CondOpcode == ISD::UMULO)
9143 Cond = X86Op.getValue(2);
9145 Cond = X86Op.getValue(1);
9147 CC = DAG.getConstant(X86Cond, MVT::i8);
9151 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
9152 SDValue Cmp = Cond.getOperand(0).getOperand(1);
9153 if (CondOpc == ISD::OR) {
9154 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
9155 // two branches instead of an explicit OR instruction with a
9157 if (Cmp == Cond.getOperand(1).getOperand(1) &&
9158 isX86LogicalCmp(Cmp)) {
9159 CC = Cond.getOperand(0).getOperand(0);
9160 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
9161 Chain, Dest, CC, Cmp);
9162 CC = Cond.getOperand(1).getOperand(0);
9166 } else { // ISD::AND
9167 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
9168 // two branches instead of an explicit AND instruction with a
9169 // separate test. However, we only do this if this block doesn't
9170 // have a fall-through edge, because this requires an explicit
9171 // jmp when the condition is false.
9172 if (Cmp == Cond.getOperand(1).getOperand(1) &&
9173 isX86LogicalCmp(Cmp) &&
9174 Op.getNode()->hasOneUse()) {
9175 X86::CondCode CCode =
9176 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
9177 CCode = X86::GetOppositeBranchCondition(CCode);
9178 CC = DAG.getConstant(CCode, MVT::i8);
9179 SDNode *User = *Op.getNode()->use_begin();
9180 // Look for an unconditional branch following this conditional branch.
9181 // We need this because we need to reverse the successors in order
9182 // to implement FCMP_OEQ.
9183 if (User->getOpcode() == ISD::BR) {
9184 SDValue FalseBB = User->getOperand(1);
9186 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
9187 assert(NewBR == User);
9191 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
9192 Chain, Dest, CC, Cmp);
9193 X86::CondCode CCode =
9194 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
9195 CCode = X86::GetOppositeBranchCondition(CCode);
9196 CC = DAG.getConstant(CCode, MVT::i8);
9202 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
9203 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
9204 // It should be transformed during dag combiner except when the condition
9205 // is set by a arithmetics with overflow node.
9206 X86::CondCode CCode =
9207 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
9208 CCode = X86::GetOppositeBranchCondition(CCode);
9209 CC = DAG.getConstant(CCode, MVT::i8);
9210 Cond = Cond.getOperand(0).getOperand(1);
9212 } else if (Cond.getOpcode() == ISD::SETCC &&
9213 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETOEQ) {
9214 // For FCMP_OEQ, we can emit
9215 // two branches instead of an explicit AND instruction with a
9216 // separate test. However, we only do this if this block doesn't
9217 // have a fall-through edge, because this requires an explicit
9218 // jmp when the condition is false.
9219 if (Op.getNode()->hasOneUse()) {
9220 SDNode *User = *Op.getNode()->use_begin();
9221 // Look for an unconditional branch following this conditional branch.
9222 // We need this because we need to reverse the successors in order
9223 // to implement FCMP_OEQ.
9224 if (User->getOpcode() == ISD::BR) {
9225 SDValue FalseBB = User->getOperand(1);
9227 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
9228 assert(NewBR == User);
9232 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
9233 Cond.getOperand(0), Cond.getOperand(1));
9234 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
9235 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
9236 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
9237 Chain, Dest, CC, Cmp);
9238 CC = DAG.getConstant(X86::COND_P, MVT::i8);
9243 } else if (Cond.getOpcode() == ISD::SETCC &&
9244 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETUNE) {
9245 // For FCMP_UNE, we can emit
9246 // two branches instead of an explicit AND instruction with a
9247 // separate test. However, we only do this if this block doesn't
9248 // have a fall-through edge, because this requires an explicit
9249 // jmp when the condition is false.
9250 if (Op.getNode()->hasOneUse()) {
9251 SDNode *User = *Op.getNode()->use_begin();
9252 // Look for an unconditional branch following this conditional branch.
9253 // We need this because we need to reverse the successors in order
9254 // to implement FCMP_UNE.
9255 if (User->getOpcode() == ISD::BR) {
9256 SDValue FalseBB = User->getOperand(1);
9258 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
9259 assert(NewBR == User);
9262 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
9263 Cond.getOperand(0), Cond.getOperand(1));
9264 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
9265 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
9266 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
9267 Chain, Dest, CC, Cmp);
9268 CC = DAG.getConstant(X86::COND_NP, MVT::i8);
9278 // Look pass the truncate if the high bits are known zero.
9279 if (isTruncWithZeroHighBitsInput(Cond, DAG))
9280 Cond = Cond.getOperand(0);
9282 // We know the result of AND is compared against zero. Try to match
9284 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
9285 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
9286 if (NewSetCC.getNode()) {
9287 CC = NewSetCC.getOperand(0);
9288 Cond = NewSetCC.getOperand(1);
9295 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
9296 Cond = EmitTest(Cond, X86::COND_NE, DAG);
9298 Cond = ConvertCmpIfNecessary(Cond, DAG);
9299 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
9300 Chain, Dest, CC, Cond);
9304 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
9305 // Calls to _alloca is needed to probe the stack when allocating more than 4k
9306 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
9307 // that the guard pages used by the OS virtual memory manager are allocated in
9308 // correct sequence.
9310 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
9311 SelectionDAG &DAG) const {
9312 assert((Subtarget->isTargetCygMing() || Subtarget->isTargetWindows() ||
9313 getTargetMachine().Options.EnableSegmentedStacks) &&
9314 "This should be used only on Windows targets or when segmented stacks "
9316 assert(!Subtarget->isTargetEnvMacho() && "Not implemented");
9317 DebugLoc dl = Op.getDebugLoc();
9320 SDValue Chain = Op.getOperand(0);
9321 SDValue Size = Op.getOperand(1);
9322 // FIXME: Ensure alignment here
9324 bool Is64Bit = Subtarget->is64Bit();
9325 EVT SPTy = Is64Bit ? MVT::i64 : MVT::i32;
9327 if (getTargetMachine().Options.EnableSegmentedStacks) {
9328 MachineFunction &MF = DAG.getMachineFunction();
9329 MachineRegisterInfo &MRI = MF.getRegInfo();
9332 // The 64 bit implementation of segmented stacks needs to clobber both r10
9333 // r11. This makes it impossible to use it along with nested parameters.
9334 const Function *F = MF.getFunction();
9336 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
9338 if (I->hasNestAttr())
9339 report_fatal_error("Cannot use segmented stacks with functions that "
9340 "have nested arguments.");
9343 const TargetRegisterClass *AddrRegClass =
9344 getRegClassFor(Subtarget->is64Bit() ? MVT::i64:MVT::i32);
9345 unsigned Vreg = MRI.createVirtualRegister(AddrRegClass);
9346 Chain = DAG.getCopyToReg(Chain, dl, Vreg, Size);
9347 SDValue Value = DAG.getNode(X86ISD::SEG_ALLOCA, dl, SPTy, Chain,
9348 DAG.getRegister(Vreg, SPTy));
9349 SDValue Ops1[2] = { Value, Chain };
9350 return DAG.getMergeValues(Ops1, 2, dl);
9353 unsigned Reg = (Subtarget->is64Bit() ? X86::RAX : X86::EAX);
9355 Chain = DAG.getCopyToReg(Chain, dl, Reg, Size, Flag);
9356 Flag = Chain.getValue(1);
9357 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
9359 Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag);
9360 Flag = Chain.getValue(1);
9362 Chain = DAG.getCopyFromReg(Chain, dl, X86StackPtr, SPTy).getValue(1);
9364 SDValue Ops1[2] = { Chain.getValue(0), Chain };
9365 return DAG.getMergeValues(Ops1, 2, dl);
9369 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
9370 MachineFunction &MF = DAG.getMachineFunction();
9371 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
9373 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
9374 DebugLoc DL = Op.getDebugLoc();
9376 if (!Subtarget->is64Bit() || Subtarget->isTargetWin64()) {
9377 // vastart just stores the address of the VarArgsFrameIndex slot into the
9378 // memory location argument.
9379 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
9381 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
9382 MachinePointerInfo(SV), false, false, 0);
9386 // gp_offset (0 - 6 * 8)
9387 // fp_offset (48 - 48 + 8 * 16)
9388 // overflow_arg_area (point to parameters coming in memory).
9390 SmallVector<SDValue, 8> MemOps;
9391 SDValue FIN = Op.getOperand(1);
9393 SDValue Store = DAG.getStore(Op.getOperand(0), DL,
9394 DAG.getConstant(FuncInfo->getVarArgsGPOffset(),
9396 FIN, MachinePointerInfo(SV), false, false, 0);
9397 MemOps.push_back(Store);
9400 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
9401 FIN, DAG.getIntPtrConstant(4));
9402 Store = DAG.getStore(Op.getOperand(0), DL,
9403 DAG.getConstant(FuncInfo->getVarArgsFPOffset(),
9405 FIN, MachinePointerInfo(SV, 4), false, false, 0);
9406 MemOps.push_back(Store);
9408 // Store ptr to overflow_arg_area
9409 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
9410 FIN, DAG.getIntPtrConstant(4));
9411 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
9413 Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN,
9414 MachinePointerInfo(SV, 8),
9416 MemOps.push_back(Store);
9418 // Store ptr to reg_save_area.
9419 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
9420 FIN, DAG.getIntPtrConstant(8));
9421 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
9423 Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN,
9424 MachinePointerInfo(SV, 16), false, false, 0);
9425 MemOps.push_back(Store);
9426 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
9427 &MemOps[0], MemOps.size());
9430 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
9431 assert(Subtarget->is64Bit() &&
9432 "LowerVAARG only handles 64-bit va_arg!");
9433 assert((Subtarget->isTargetLinux() ||
9434 Subtarget->isTargetDarwin()) &&
9435 "Unhandled target in LowerVAARG");
9436 assert(Op.getNode()->getNumOperands() == 4);
9437 SDValue Chain = Op.getOperand(0);
9438 SDValue SrcPtr = Op.getOperand(1);
9439 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
9440 unsigned Align = Op.getConstantOperandVal(3);
9441 DebugLoc dl = Op.getDebugLoc();
9443 EVT ArgVT = Op.getNode()->getValueType(0);
9444 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
9445 uint32_t ArgSize = getTargetData()->getTypeAllocSize(ArgTy);
9448 // Decide which area this value should be read from.
9449 // TODO: Implement the AMD64 ABI in its entirety. This simple
9450 // selection mechanism works only for the basic types.
9451 if (ArgVT == MVT::f80) {
9452 llvm_unreachable("va_arg for f80 not yet implemented");
9453 } else if (ArgVT.isFloatingPoint() && ArgSize <= 16 /*bytes*/) {
9454 ArgMode = 2; // Argument passed in XMM register. Use fp_offset.
9455 } else if (ArgVT.isInteger() && ArgSize <= 32 /*bytes*/) {
9456 ArgMode = 1; // Argument passed in GPR64 register(s). Use gp_offset.
9458 llvm_unreachable("Unhandled argument type in LowerVAARG");
9462 // Sanity Check: Make sure using fp_offset makes sense.
9463 assert(!getTargetMachine().Options.UseSoftFloat &&
9464 !(DAG.getMachineFunction()
9465 .getFunction()->hasFnAttr(Attribute::NoImplicitFloat)) &&
9466 Subtarget->hasSSE1());
9469 // Insert VAARG_64 node into the DAG
9470 // VAARG_64 returns two values: Variable Argument Address, Chain
9471 SmallVector<SDValue, 11> InstOps;
9472 InstOps.push_back(Chain);
9473 InstOps.push_back(SrcPtr);
9474 InstOps.push_back(DAG.getConstant(ArgSize, MVT::i32));
9475 InstOps.push_back(DAG.getConstant(ArgMode, MVT::i8));
9476 InstOps.push_back(DAG.getConstant(Align, MVT::i32));
9477 SDVTList VTs = DAG.getVTList(getPointerTy(), MVT::Other);
9478 SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl,
9479 VTs, &InstOps[0], InstOps.size(),
9481 MachinePointerInfo(SV),
9486 Chain = VAARG.getValue(1);
9488 // Load the next argument and return it
9489 return DAG.getLoad(ArgVT, dl,
9492 MachinePointerInfo(),
9493 false, false, false, 0);
9496 SDValue X86TargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG) const {
9497 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
9498 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
9499 SDValue Chain = Op.getOperand(0);
9500 SDValue DstPtr = Op.getOperand(1);
9501 SDValue SrcPtr = Op.getOperand(2);
9502 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
9503 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
9504 DebugLoc DL = Op.getDebugLoc();
9506 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr,
9507 DAG.getIntPtrConstant(24), 8, /*isVolatile*/false,
9509 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
9512 // getTargetVShiftNOde - Handle vector element shifts where the shift amount
9513 // may or may not be a constant. Takes immediate version of shift as input.
9514 static SDValue getTargetVShiftNode(unsigned Opc, DebugLoc dl, EVT VT,
9515 SDValue SrcOp, SDValue ShAmt,
9516 SelectionDAG &DAG) {
9517 assert(ShAmt.getValueType() == MVT::i32 && "ShAmt is not i32");
9519 if (isa<ConstantSDNode>(ShAmt)) {
9520 // Constant may be a TargetConstant. Use a regular constant.
9521 uint32_t ShiftAmt = cast<ConstantSDNode>(ShAmt)->getZExtValue();
9523 default: llvm_unreachable("Unknown target vector shift node");
9527 return DAG.getNode(Opc, dl, VT, SrcOp,
9528 DAG.getConstant(ShiftAmt, MVT::i32));
9532 // Change opcode to non-immediate version
9534 default: llvm_unreachable("Unknown target vector shift node");
9535 case X86ISD::VSHLI: Opc = X86ISD::VSHL; break;
9536 case X86ISD::VSRLI: Opc = X86ISD::VSRL; break;
9537 case X86ISD::VSRAI: Opc = X86ISD::VSRA; break;
9540 // Need to build a vector containing shift amount
9541 // Shift amount is 32-bits, but SSE instructions read 64-bit, so fill with 0
9544 ShOps[1] = DAG.getConstant(0, MVT::i32);
9545 ShOps[2] = ShOps[3] = DAG.getUNDEF(MVT::i32);
9546 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, &ShOps[0], 4);
9548 // The return type has to be a 128-bit type with the same element
9549 // type as the input type.
9550 MVT EltVT = VT.getVectorElementType().getSimpleVT();
9551 EVT ShVT = MVT::getVectorVT(EltVT, 128/EltVT.getSizeInBits());
9553 ShAmt = DAG.getNode(ISD::BITCAST, dl, ShVT, ShAmt);
9554 return DAG.getNode(Opc, dl, VT, SrcOp, ShAmt);
9558 X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const {
9559 DebugLoc dl = Op.getDebugLoc();
9560 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
9562 default: return SDValue(); // Don't custom lower most intrinsics.
9563 // Comparison intrinsics.
9564 case Intrinsic::x86_sse_comieq_ss:
9565 case Intrinsic::x86_sse_comilt_ss:
9566 case Intrinsic::x86_sse_comile_ss:
9567 case Intrinsic::x86_sse_comigt_ss:
9568 case Intrinsic::x86_sse_comige_ss:
9569 case Intrinsic::x86_sse_comineq_ss:
9570 case Intrinsic::x86_sse_ucomieq_ss:
9571 case Intrinsic::x86_sse_ucomilt_ss:
9572 case Intrinsic::x86_sse_ucomile_ss:
9573 case Intrinsic::x86_sse_ucomigt_ss:
9574 case Intrinsic::x86_sse_ucomige_ss:
9575 case Intrinsic::x86_sse_ucomineq_ss:
9576 case Intrinsic::x86_sse2_comieq_sd:
9577 case Intrinsic::x86_sse2_comilt_sd:
9578 case Intrinsic::x86_sse2_comile_sd:
9579 case Intrinsic::x86_sse2_comigt_sd:
9580 case Intrinsic::x86_sse2_comige_sd:
9581 case Intrinsic::x86_sse2_comineq_sd:
9582 case Intrinsic::x86_sse2_ucomieq_sd:
9583 case Intrinsic::x86_sse2_ucomilt_sd:
9584 case Intrinsic::x86_sse2_ucomile_sd:
9585 case Intrinsic::x86_sse2_ucomigt_sd:
9586 case Intrinsic::x86_sse2_ucomige_sd:
9587 case Intrinsic::x86_sse2_ucomineq_sd: {
9591 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
9592 case Intrinsic::x86_sse_comieq_ss:
9593 case Intrinsic::x86_sse2_comieq_sd:
9597 case Intrinsic::x86_sse_comilt_ss:
9598 case Intrinsic::x86_sse2_comilt_sd:
9602 case Intrinsic::x86_sse_comile_ss:
9603 case Intrinsic::x86_sse2_comile_sd:
9607 case Intrinsic::x86_sse_comigt_ss:
9608 case Intrinsic::x86_sse2_comigt_sd:
9612 case Intrinsic::x86_sse_comige_ss:
9613 case Intrinsic::x86_sse2_comige_sd:
9617 case Intrinsic::x86_sse_comineq_ss:
9618 case Intrinsic::x86_sse2_comineq_sd:
9622 case Intrinsic::x86_sse_ucomieq_ss:
9623 case Intrinsic::x86_sse2_ucomieq_sd:
9624 Opc = X86ISD::UCOMI;
9627 case Intrinsic::x86_sse_ucomilt_ss:
9628 case Intrinsic::x86_sse2_ucomilt_sd:
9629 Opc = X86ISD::UCOMI;
9632 case Intrinsic::x86_sse_ucomile_ss:
9633 case Intrinsic::x86_sse2_ucomile_sd:
9634 Opc = X86ISD::UCOMI;
9637 case Intrinsic::x86_sse_ucomigt_ss:
9638 case Intrinsic::x86_sse2_ucomigt_sd:
9639 Opc = X86ISD::UCOMI;
9642 case Intrinsic::x86_sse_ucomige_ss:
9643 case Intrinsic::x86_sse2_ucomige_sd:
9644 Opc = X86ISD::UCOMI;
9647 case Intrinsic::x86_sse_ucomineq_ss:
9648 case Intrinsic::x86_sse2_ucomineq_sd:
9649 Opc = X86ISD::UCOMI;
9654 SDValue LHS = Op.getOperand(1);
9655 SDValue RHS = Op.getOperand(2);
9656 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG);
9657 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!");
9658 SDValue Cond = DAG.getNode(Opc, dl, MVT::i32, LHS, RHS);
9659 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
9660 DAG.getConstant(X86CC, MVT::i8), Cond);
9661 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
9664 // Arithmetic intrinsics.
9665 case Intrinsic::x86_sse2_pmulu_dq:
9666 case Intrinsic::x86_avx2_pmulu_dq:
9667 return DAG.getNode(X86ISD::PMULUDQ, dl, Op.getValueType(),
9668 Op.getOperand(1), Op.getOperand(2));
9670 // SSE3/AVX horizontal add/sub intrinsics
9671 case Intrinsic::x86_sse3_hadd_ps:
9672 case Intrinsic::x86_sse3_hadd_pd:
9673 case Intrinsic::x86_avx_hadd_ps_256:
9674 case Intrinsic::x86_avx_hadd_pd_256:
9675 case Intrinsic::x86_sse3_hsub_ps:
9676 case Intrinsic::x86_sse3_hsub_pd:
9677 case Intrinsic::x86_avx_hsub_ps_256:
9678 case Intrinsic::x86_avx_hsub_pd_256:
9679 case Intrinsic::x86_ssse3_phadd_w_128:
9680 case Intrinsic::x86_ssse3_phadd_d_128:
9681 case Intrinsic::x86_avx2_phadd_w:
9682 case Intrinsic::x86_avx2_phadd_d:
9683 case Intrinsic::x86_ssse3_phsub_w_128:
9684 case Intrinsic::x86_ssse3_phsub_d_128:
9685 case Intrinsic::x86_avx2_phsub_w:
9686 case Intrinsic::x86_avx2_phsub_d: {
9689 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
9690 case Intrinsic::x86_sse3_hadd_ps:
9691 case Intrinsic::x86_sse3_hadd_pd:
9692 case Intrinsic::x86_avx_hadd_ps_256:
9693 case Intrinsic::x86_avx_hadd_pd_256:
9694 Opcode = X86ISD::FHADD;
9696 case Intrinsic::x86_sse3_hsub_ps:
9697 case Intrinsic::x86_sse3_hsub_pd:
9698 case Intrinsic::x86_avx_hsub_ps_256:
9699 case Intrinsic::x86_avx_hsub_pd_256:
9700 Opcode = X86ISD::FHSUB;
9702 case Intrinsic::x86_ssse3_phadd_w_128:
9703 case Intrinsic::x86_ssse3_phadd_d_128:
9704 case Intrinsic::x86_avx2_phadd_w:
9705 case Intrinsic::x86_avx2_phadd_d:
9706 Opcode = X86ISD::HADD;
9708 case Intrinsic::x86_ssse3_phsub_w_128:
9709 case Intrinsic::x86_ssse3_phsub_d_128:
9710 case Intrinsic::x86_avx2_phsub_w:
9711 case Intrinsic::x86_avx2_phsub_d:
9712 Opcode = X86ISD::HSUB;
9715 return DAG.getNode(Opcode, dl, Op.getValueType(),
9716 Op.getOperand(1), Op.getOperand(2));
9719 // AVX2 variable shift intrinsics
9720 case Intrinsic::x86_avx2_psllv_d:
9721 case Intrinsic::x86_avx2_psllv_q:
9722 case Intrinsic::x86_avx2_psllv_d_256:
9723 case Intrinsic::x86_avx2_psllv_q_256:
9724 case Intrinsic::x86_avx2_psrlv_d:
9725 case Intrinsic::x86_avx2_psrlv_q:
9726 case Intrinsic::x86_avx2_psrlv_d_256:
9727 case Intrinsic::x86_avx2_psrlv_q_256:
9728 case Intrinsic::x86_avx2_psrav_d:
9729 case Intrinsic::x86_avx2_psrav_d_256: {
9732 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
9733 case Intrinsic::x86_avx2_psllv_d:
9734 case Intrinsic::x86_avx2_psllv_q:
9735 case Intrinsic::x86_avx2_psllv_d_256:
9736 case Intrinsic::x86_avx2_psllv_q_256:
9739 case Intrinsic::x86_avx2_psrlv_d:
9740 case Intrinsic::x86_avx2_psrlv_q:
9741 case Intrinsic::x86_avx2_psrlv_d_256:
9742 case Intrinsic::x86_avx2_psrlv_q_256:
9745 case Intrinsic::x86_avx2_psrav_d:
9746 case Intrinsic::x86_avx2_psrav_d_256:
9750 return DAG.getNode(Opcode, dl, Op.getValueType(),
9751 Op.getOperand(1), Op.getOperand(2));
9754 case Intrinsic::x86_ssse3_pshuf_b_128:
9755 case Intrinsic::x86_avx2_pshuf_b:
9756 return DAG.getNode(X86ISD::PSHUFB, dl, Op.getValueType(),
9757 Op.getOperand(1), Op.getOperand(2));
9759 case Intrinsic::x86_ssse3_psign_b_128:
9760 case Intrinsic::x86_ssse3_psign_w_128:
9761 case Intrinsic::x86_ssse3_psign_d_128:
9762 case Intrinsic::x86_avx2_psign_b:
9763 case Intrinsic::x86_avx2_psign_w:
9764 case Intrinsic::x86_avx2_psign_d:
9765 return DAG.getNode(X86ISD::PSIGN, dl, Op.getValueType(),
9766 Op.getOperand(1), Op.getOperand(2));
9768 case Intrinsic::x86_sse41_insertps:
9769 return DAG.getNode(X86ISD::INSERTPS, dl, Op.getValueType(),
9770 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
9772 case Intrinsic::x86_avx_vperm2f128_ps_256:
9773 case Intrinsic::x86_avx_vperm2f128_pd_256:
9774 case Intrinsic::x86_avx_vperm2f128_si_256:
9775 case Intrinsic::x86_avx2_vperm2i128:
9776 return DAG.getNode(X86ISD::VPERM2X128, dl, Op.getValueType(),
9777 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
9779 case Intrinsic::x86_avx2_permd:
9780 case Intrinsic::x86_avx2_permps:
9781 // Operands intentionally swapped. Mask is last operand to intrinsic,
9782 // but second operand for node/intruction.
9783 return DAG.getNode(X86ISD::VPERMV, dl, Op.getValueType(),
9784 Op.getOperand(2), Op.getOperand(1));
9786 // ptest and testp intrinsics. The intrinsic these come from are designed to
9787 // return an integer value, not just an instruction so lower it to the ptest
9788 // or testp pattern and a setcc for the result.
9789 case Intrinsic::x86_sse41_ptestz:
9790 case Intrinsic::x86_sse41_ptestc:
9791 case Intrinsic::x86_sse41_ptestnzc:
9792 case Intrinsic::x86_avx_ptestz_256:
9793 case Intrinsic::x86_avx_ptestc_256:
9794 case Intrinsic::x86_avx_ptestnzc_256:
9795 case Intrinsic::x86_avx_vtestz_ps:
9796 case Intrinsic::x86_avx_vtestc_ps:
9797 case Intrinsic::x86_avx_vtestnzc_ps:
9798 case Intrinsic::x86_avx_vtestz_pd:
9799 case Intrinsic::x86_avx_vtestc_pd:
9800 case Intrinsic::x86_avx_vtestnzc_pd:
9801 case Intrinsic::x86_avx_vtestz_ps_256:
9802 case Intrinsic::x86_avx_vtestc_ps_256:
9803 case Intrinsic::x86_avx_vtestnzc_ps_256:
9804 case Intrinsic::x86_avx_vtestz_pd_256:
9805 case Intrinsic::x86_avx_vtestc_pd_256:
9806 case Intrinsic::x86_avx_vtestnzc_pd_256: {
9807 bool IsTestPacked = false;
9810 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
9811 case Intrinsic::x86_avx_vtestz_ps:
9812 case Intrinsic::x86_avx_vtestz_pd:
9813 case Intrinsic::x86_avx_vtestz_ps_256:
9814 case Intrinsic::x86_avx_vtestz_pd_256:
9815 IsTestPacked = true; // Fallthrough
9816 case Intrinsic::x86_sse41_ptestz:
9817 case Intrinsic::x86_avx_ptestz_256:
9819 X86CC = X86::COND_E;
9821 case Intrinsic::x86_avx_vtestc_ps:
9822 case Intrinsic::x86_avx_vtestc_pd:
9823 case Intrinsic::x86_avx_vtestc_ps_256:
9824 case Intrinsic::x86_avx_vtestc_pd_256:
9825 IsTestPacked = true; // Fallthrough
9826 case Intrinsic::x86_sse41_ptestc:
9827 case Intrinsic::x86_avx_ptestc_256:
9829 X86CC = X86::COND_B;
9831 case Intrinsic::x86_avx_vtestnzc_ps:
9832 case Intrinsic::x86_avx_vtestnzc_pd:
9833 case Intrinsic::x86_avx_vtestnzc_ps_256:
9834 case Intrinsic::x86_avx_vtestnzc_pd_256:
9835 IsTestPacked = true; // Fallthrough
9836 case Intrinsic::x86_sse41_ptestnzc:
9837 case Intrinsic::x86_avx_ptestnzc_256:
9839 X86CC = X86::COND_A;
9843 SDValue LHS = Op.getOperand(1);
9844 SDValue RHS = Op.getOperand(2);
9845 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST;
9846 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS);
9847 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
9848 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
9849 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
9852 // SSE/AVX shift intrinsics
9853 case Intrinsic::x86_sse2_psll_w:
9854 case Intrinsic::x86_sse2_psll_d:
9855 case Intrinsic::x86_sse2_psll_q:
9856 case Intrinsic::x86_avx2_psll_w:
9857 case Intrinsic::x86_avx2_psll_d:
9858 case Intrinsic::x86_avx2_psll_q:
9859 case Intrinsic::x86_sse2_psrl_w:
9860 case Intrinsic::x86_sse2_psrl_d:
9861 case Intrinsic::x86_sse2_psrl_q:
9862 case Intrinsic::x86_avx2_psrl_w:
9863 case Intrinsic::x86_avx2_psrl_d:
9864 case Intrinsic::x86_avx2_psrl_q:
9865 case Intrinsic::x86_sse2_psra_w:
9866 case Intrinsic::x86_sse2_psra_d:
9867 case Intrinsic::x86_avx2_psra_w:
9868 case Intrinsic::x86_avx2_psra_d: {
9871 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
9872 case Intrinsic::x86_sse2_psll_w:
9873 case Intrinsic::x86_sse2_psll_d:
9874 case Intrinsic::x86_sse2_psll_q:
9875 case Intrinsic::x86_avx2_psll_w:
9876 case Intrinsic::x86_avx2_psll_d:
9877 case Intrinsic::x86_avx2_psll_q:
9878 Opcode = X86ISD::VSHL;
9880 case Intrinsic::x86_sse2_psrl_w:
9881 case Intrinsic::x86_sse2_psrl_d:
9882 case Intrinsic::x86_sse2_psrl_q:
9883 case Intrinsic::x86_avx2_psrl_w:
9884 case Intrinsic::x86_avx2_psrl_d:
9885 case Intrinsic::x86_avx2_psrl_q:
9886 Opcode = X86ISD::VSRL;
9888 case Intrinsic::x86_sse2_psra_w:
9889 case Intrinsic::x86_sse2_psra_d:
9890 case Intrinsic::x86_avx2_psra_w:
9891 case Intrinsic::x86_avx2_psra_d:
9892 Opcode = X86ISD::VSRA;
9895 return DAG.getNode(Opcode, dl, Op.getValueType(),
9896 Op.getOperand(1), Op.getOperand(2));
9899 // SSE/AVX immediate shift intrinsics
9900 case Intrinsic::x86_sse2_pslli_w:
9901 case Intrinsic::x86_sse2_pslli_d:
9902 case Intrinsic::x86_sse2_pslli_q:
9903 case Intrinsic::x86_avx2_pslli_w:
9904 case Intrinsic::x86_avx2_pslli_d:
9905 case Intrinsic::x86_avx2_pslli_q:
9906 case Intrinsic::x86_sse2_psrli_w:
9907 case Intrinsic::x86_sse2_psrli_d:
9908 case Intrinsic::x86_sse2_psrli_q:
9909 case Intrinsic::x86_avx2_psrli_w:
9910 case Intrinsic::x86_avx2_psrli_d:
9911 case Intrinsic::x86_avx2_psrli_q:
9912 case Intrinsic::x86_sse2_psrai_w:
9913 case Intrinsic::x86_sse2_psrai_d:
9914 case Intrinsic::x86_avx2_psrai_w:
9915 case Intrinsic::x86_avx2_psrai_d: {
9918 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
9919 case Intrinsic::x86_sse2_pslli_w:
9920 case Intrinsic::x86_sse2_pslli_d:
9921 case Intrinsic::x86_sse2_pslli_q:
9922 case Intrinsic::x86_avx2_pslli_w:
9923 case Intrinsic::x86_avx2_pslli_d:
9924 case Intrinsic::x86_avx2_pslli_q:
9925 Opcode = X86ISD::VSHLI;
9927 case Intrinsic::x86_sse2_psrli_w:
9928 case Intrinsic::x86_sse2_psrli_d:
9929 case Intrinsic::x86_sse2_psrli_q:
9930 case Intrinsic::x86_avx2_psrli_w:
9931 case Intrinsic::x86_avx2_psrli_d:
9932 case Intrinsic::x86_avx2_psrli_q:
9933 Opcode = X86ISD::VSRLI;
9935 case Intrinsic::x86_sse2_psrai_w:
9936 case Intrinsic::x86_sse2_psrai_d:
9937 case Intrinsic::x86_avx2_psrai_w:
9938 case Intrinsic::x86_avx2_psrai_d:
9939 Opcode = X86ISD::VSRAI;
9942 return getTargetVShiftNode(Opcode, dl, Op.getValueType(),
9943 Op.getOperand(1), Op.getOperand(2), DAG);
9946 // Fix vector shift instructions where the last operand is a non-immediate
9948 case Intrinsic::x86_mmx_pslli_w:
9949 case Intrinsic::x86_mmx_pslli_d:
9950 case Intrinsic::x86_mmx_pslli_q:
9951 case Intrinsic::x86_mmx_psrli_w:
9952 case Intrinsic::x86_mmx_psrli_d:
9953 case Intrinsic::x86_mmx_psrli_q:
9954 case Intrinsic::x86_mmx_psrai_w:
9955 case Intrinsic::x86_mmx_psrai_d: {
9956 SDValue ShAmt = Op.getOperand(2);
9957 if (isa<ConstantSDNode>(ShAmt))
9962 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
9963 case Intrinsic::x86_mmx_pslli_w:
9964 NewIntNo = Intrinsic::x86_mmx_psll_w;
9966 case Intrinsic::x86_mmx_pslli_d:
9967 NewIntNo = Intrinsic::x86_mmx_psll_d;
9969 case Intrinsic::x86_mmx_pslli_q:
9970 NewIntNo = Intrinsic::x86_mmx_psll_q;
9972 case Intrinsic::x86_mmx_psrli_w:
9973 NewIntNo = Intrinsic::x86_mmx_psrl_w;
9975 case Intrinsic::x86_mmx_psrli_d:
9976 NewIntNo = Intrinsic::x86_mmx_psrl_d;
9978 case Intrinsic::x86_mmx_psrli_q:
9979 NewIntNo = Intrinsic::x86_mmx_psrl_q;
9981 case Intrinsic::x86_mmx_psrai_w:
9982 NewIntNo = Intrinsic::x86_mmx_psra_w;
9984 case Intrinsic::x86_mmx_psrai_d:
9985 NewIntNo = Intrinsic::x86_mmx_psra_d;
9989 // The vector shift intrinsics with scalars uses 32b shift amounts but
9990 // the sse2/mmx shift instructions reads 64 bits. Set the upper 32 bits
9992 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i32, ShAmt,
9993 DAG.getConstant(0, MVT::i32));
9994 // FIXME this must be lowered to get rid of the invalid type.
9996 EVT VT = Op.getValueType();
9997 ShAmt = DAG.getNode(ISD::BITCAST, dl, VT, ShAmt);
9998 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9999 DAG.getConstant(NewIntNo, MVT::i32),
10000 Op.getOperand(1), ShAmt);
10002 case Intrinsic::x86_sse42_pcmpistria128:
10003 case Intrinsic::x86_sse42_pcmpestria128:
10004 case Intrinsic::x86_sse42_pcmpistric128:
10005 case Intrinsic::x86_sse42_pcmpestric128:
10006 case Intrinsic::x86_sse42_pcmpistrio128:
10007 case Intrinsic::x86_sse42_pcmpestrio128:
10008 case Intrinsic::x86_sse42_pcmpistris128:
10009 case Intrinsic::x86_sse42_pcmpestris128:
10010 case Intrinsic::x86_sse42_pcmpistriz128:
10011 case Intrinsic::x86_sse42_pcmpestriz128: {
10015 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
10016 case Intrinsic::x86_sse42_pcmpistria128:
10017 Opcode = X86ISD::PCMPISTRI;
10018 X86CC = X86::COND_A;
10020 case Intrinsic::x86_sse42_pcmpestria128:
10021 Opcode = X86ISD::PCMPESTRI;
10022 X86CC = X86::COND_A;
10024 case Intrinsic::x86_sse42_pcmpistric128:
10025 Opcode = X86ISD::PCMPISTRI;
10026 X86CC = X86::COND_B;
10028 case Intrinsic::x86_sse42_pcmpestric128:
10029 Opcode = X86ISD::PCMPESTRI;
10030 X86CC = X86::COND_B;
10032 case Intrinsic::x86_sse42_pcmpistrio128:
10033 Opcode = X86ISD::PCMPISTRI;
10034 X86CC = X86::COND_O;
10036 case Intrinsic::x86_sse42_pcmpestrio128:
10037 Opcode = X86ISD::PCMPESTRI;
10038 X86CC = X86::COND_O;
10040 case Intrinsic::x86_sse42_pcmpistris128:
10041 Opcode = X86ISD::PCMPISTRI;
10042 X86CC = X86::COND_S;
10044 case Intrinsic::x86_sse42_pcmpestris128:
10045 Opcode = X86ISD::PCMPESTRI;
10046 X86CC = X86::COND_S;
10048 case Intrinsic::x86_sse42_pcmpistriz128:
10049 Opcode = X86ISD::PCMPISTRI;
10050 X86CC = X86::COND_E;
10052 case Intrinsic::x86_sse42_pcmpestriz128:
10053 Opcode = X86ISD::PCMPESTRI;
10054 X86CC = X86::COND_E;
10057 SmallVector<SDValue, 5> NewOps;
10058 NewOps.append(Op->op_begin()+1, Op->op_end());
10059 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
10060 SDValue PCMP = DAG.getNode(Opcode, dl, VTs, NewOps.data(), NewOps.size());
10061 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
10062 DAG.getConstant(X86CC, MVT::i8),
10063 SDValue(PCMP.getNode(), 1));
10064 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
10067 case Intrinsic::x86_sse42_pcmpistri128:
10068 case Intrinsic::x86_sse42_pcmpestri128: {
10070 if (IntNo == Intrinsic::x86_sse42_pcmpistri128)
10071 Opcode = X86ISD::PCMPISTRI;
10073 Opcode = X86ISD::PCMPESTRI;
10075 SmallVector<SDValue, 5> NewOps;
10076 NewOps.append(Op->op_begin()+1, Op->op_end());
10077 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
10078 return DAG.getNode(Opcode, dl, VTs, NewOps.data(), NewOps.size());
10080 case Intrinsic::x86_fma_vfmadd_ps:
10081 case Intrinsic::x86_fma_vfmadd_pd:
10082 case Intrinsic::x86_fma_vfmsub_ps:
10083 case Intrinsic::x86_fma_vfmsub_pd:
10084 case Intrinsic::x86_fma_vfnmadd_ps:
10085 case Intrinsic::x86_fma_vfnmadd_pd:
10086 case Intrinsic::x86_fma_vfnmsub_ps:
10087 case Intrinsic::x86_fma_vfnmsub_pd:
10088 case Intrinsic::x86_fma_vfmaddsub_ps:
10089 case Intrinsic::x86_fma_vfmaddsub_pd:
10090 case Intrinsic::x86_fma_vfmsubadd_ps:
10091 case Intrinsic::x86_fma_vfmsubadd_pd:
10092 case Intrinsic::x86_fma_vfmadd_ps_256:
10093 case Intrinsic::x86_fma_vfmadd_pd_256:
10094 case Intrinsic::x86_fma_vfmsub_ps_256:
10095 case Intrinsic::x86_fma_vfmsub_pd_256:
10096 case Intrinsic::x86_fma_vfnmadd_ps_256:
10097 case Intrinsic::x86_fma_vfnmadd_pd_256:
10098 case Intrinsic::x86_fma_vfnmsub_ps_256:
10099 case Intrinsic::x86_fma_vfnmsub_pd_256:
10100 case Intrinsic::x86_fma_vfmaddsub_ps_256:
10101 case Intrinsic::x86_fma_vfmaddsub_pd_256:
10102 case Intrinsic::x86_fma_vfmsubadd_ps_256:
10103 case Intrinsic::x86_fma_vfmsubadd_pd_256: {
10104 // Only lower intrinsics if FMA is enabled. FMA4 still uses patterns.
10105 if (!Subtarget->hasFMA())
10110 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
10111 case Intrinsic::x86_fma_vfmadd_ps:
10112 case Intrinsic::x86_fma_vfmadd_pd:
10113 case Intrinsic::x86_fma_vfmadd_ps_256:
10114 case Intrinsic::x86_fma_vfmadd_pd_256:
10115 Opc = X86ISD::FMADD;
10117 case Intrinsic::x86_fma_vfmsub_ps:
10118 case Intrinsic::x86_fma_vfmsub_pd:
10119 case Intrinsic::x86_fma_vfmsub_ps_256:
10120 case Intrinsic::x86_fma_vfmsub_pd_256:
10121 Opc = X86ISD::FMSUB;
10123 case Intrinsic::x86_fma_vfnmadd_ps:
10124 case Intrinsic::x86_fma_vfnmadd_pd:
10125 case Intrinsic::x86_fma_vfnmadd_ps_256:
10126 case Intrinsic::x86_fma_vfnmadd_pd_256:
10127 Opc = X86ISD::FNMADD;
10129 case Intrinsic::x86_fma_vfnmsub_ps:
10130 case Intrinsic::x86_fma_vfnmsub_pd:
10131 case Intrinsic::x86_fma_vfnmsub_ps_256:
10132 case Intrinsic::x86_fma_vfnmsub_pd_256:
10133 Opc = X86ISD::FNMSUB;
10135 case Intrinsic::x86_fma_vfmaddsub_ps:
10136 case Intrinsic::x86_fma_vfmaddsub_pd:
10137 case Intrinsic::x86_fma_vfmaddsub_ps_256:
10138 case Intrinsic::x86_fma_vfmaddsub_pd_256:
10139 Opc = X86ISD::FMADDSUB;
10141 case Intrinsic::x86_fma_vfmsubadd_ps:
10142 case Intrinsic::x86_fma_vfmsubadd_pd:
10143 case Intrinsic::x86_fma_vfmsubadd_ps_256:
10144 case Intrinsic::x86_fma_vfmsubadd_pd_256:
10145 Opc = X86ISD::FMSUBADD;
10149 return DAG.getNode(Opc, dl, Op.getValueType(), Op.getOperand(1),
10150 Op.getOperand(2), Op.getOperand(3));
10156 X86TargetLowering::LowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) const {
10157 DebugLoc dl = Op.getDebugLoc();
10158 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
10160 default: return SDValue(); // Don't custom lower most intrinsics.
10162 // RDRAND intrinsics.
10163 case Intrinsic::x86_rdrand_16:
10164 case Intrinsic::x86_rdrand_32:
10165 case Intrinsic::x86_rdrand_64: {
10166 // Emit the node with the right value type.
10167 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Glue, MVT::Other);
10168 SDValue Result = DAG.getNode(X86ISD::RDRAND, dl, VTs, Op.getOperand(0));
10170 // If the value returned by RDRAND was valid (CF=1), return 1. Otherwise
10171 // return the value from Rand, which is always 0, casted to i32.
10172 SDValue Ops[] = { DAG.getZExtOrTrunc(Result, dl, Op->getValueType(1)),
10173 DAG.getConstant(1, Op->getValueType(1)),
10174 DAG.getConstant(X86::COND_B, MVT::i32),
10175 SDValue(Result.getNode(), 1) };
10176 SDValue isValid = DAG.getNode(X86ISD::CMOV, dl,
10177 DAG.getVTList(Op->getValueType(1), MVT::Glue),
10180 // Return { result, isValid, chain }.
10181 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(), Result, isValid,
10182 SDValue(Result.getNode(), 2));
10187 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op,
10188 SelectionDAG &DAG) const {
10189 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
10190 MFI->setReturnAddressIsTaken(true);
10192 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
10193 DebugLoc dl = Op.getDebugLoc();
10196 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
10198 DAG.getConstant(TD->getPointerSize(),
10199 Subtarget->is64Bit() ? MVT::i64 : MVT::i32);
10200 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
10201 DAG.getNode(ISD::ADD, dl, getPointerTy(),
10202 FrameAddr, Offset),
10203 MachinePointerInfo(), false, false, false, 0);
10206 // Just load the return address.
10207 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
10208 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
10209 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
10212 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
10213 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
10214 MFI->setFrameAddressIsTaken(true);
10216 EVT VT = Op.getValueType();
10217 DebugLoc dl = Op.getDebugLoc(); // FIXME probably not meaningful
10218 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
10219 unsigned FrameReg = Subtarget->is64Bit() ? X86::RBP : X86::EBP;
10220 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
10222 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
10223 MachinePointerInfo(),
10224 false, false, false, 0);
10228 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
10229 SelectionDAG &DAG) const {
10230 return DAG.getIntPtrConstant(2*TD->getPointerSize());
10233 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
10234 SDValue Chain = Op.getOperand(0);
10235 SDValue Offset = Op.getOperand(1);
10236 SDValue Handler = Op.getOperand(2);
10237 DebugLoc dl = Op.getDebugLoc();
10239 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl,
10240 Subtarget->is64Bit() ? X86::RBP : X86::EBP,
10242 unsigned StoreAddrReg = (Subtarget->is64Bit() ? X86::RCX : X86::ECX);
10244 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), Frame,
10245 DAG.getIntPtrConstant(TD->getPointerSize()));
10246 StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), StoreAddr, Offset);
10247 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(),
10249 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
10251 return DAG.getNode(X86ISD::EH_RETURN, dl,
10253 Chain, DAG.getRegister(StoreAddrReg, getPointerTy()));
10256 SDValue X86TargetLowering::LowerADJUST_TRAMPOLINE(SDValue Op,
10257 SelectionDAG &DAG) const {
10258 return Op.getOperand(0);
10261 SDValue X86TargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
10262 SelectionDAG &DAG) const {
10263 SDValue Root = Op.getOperand(0);
10264 SDValue Trmp = Op.getOperand(1); // trampoline
10265 SDValue FPtr = Op.getOperand(2); // nested function
10266 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
10267 DebugLoc dl = Op.getDebugLoc();
10269 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
10271 if (Subtarget->is64Bit()) {
10272 SDValue OutChains[6];
10274 // Large code-model.
10275 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode.
10276 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode.
10278 const unsigned char N86R10 = X86_MC::getX86RegNum(X86::R10);
10279 const unsigned char N86R11 = X86_MC::getX86RegNum(X86::R11);
10281 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
10283 // Load the pointer to the nested function into R11.
10284 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
10285 SDValue Addr = Trmp;
10286 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
10287 Addr, MachinePointerInfo(TrmpAddr),
10290 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
10291 DAG.getConstant(2, MVT::i64));
10292 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr,
10293 MachinePointerInfo(TrmpAddr, 2),
10296 // Load the 'nest' parameter value into R10.
10297 // R10 is specified in X86CallingConv.td
10298 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
10299 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
10300 DAG.getConstant(10, MVT::i64));
10301 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
10302 Addr, MachinePointerInfo(TrmpAddr, 10),
10305 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
10306 DAG.getConstant(12, MVT::i64));
10307 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr,
10308 MachinePointerInfo(TrmpAddr, 12),
10311 // Jump to the nested function.
10312 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
10313 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
10314 DAG.getConstant(20, MVT::i64));
10315 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
10316 Addr, MachinePointerInfo(TrmpAddr, 20),
10319 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
10320 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
10321 DAG.getConstant(22, MVT::i64));
10322 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr,
10323 MachinePointerInfo(TrmpAddr, 22),
10326 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 6);
10328 const Function *Func =
10329 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
10330 CallingConv::ID CC = Func->getCallingConv();
10335 llvm_unreachable("Unsupported calling convention");
10336 case CallingConv::C:
10337 case CallingConv::X86_StdCall: {
10338 // Pass 'nest' parameter in ECX.
10339 // Must be kept in sync with X86CallingConv.td
10340 NestReg = X86::ECX;
10342 // Check that ECX wasn't needed by an 'inreg' parameter.
10343 FunctionType *FTy = Func->getFunctionType();
10344 const AttrListPtr &Attrs = Func->getAttributes();
10346 if (!Attrs.isEmpty() && !Func->isVarArg()) {
10347 unsigned InRegCount = 0;
10350 for (FunctionType::param_iterator I = FTy->param_begin(),
10351 E = FTy->param_end(); I != E; ++I, ++Idx)
10352 if (Attrs.paramHasAttr(Idx, Attribute::InReg))
10353 // FIXME: should only count parameters that are lowered to integers.
10354 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32;
10356 if (InRegCount > 2) {
10357 report_fatal_error("Nest register in use - reduce number of inreg"
10363 case CallingConv::X86_FastCall:
10364 case CallingConv::X86_ThisCall:
10365 case CallingConv::Fast:
10366 // Pass 'nest' parameter in EAX.
10367 // Must be kept in sync with X86CallingConv.td
10368 NestReg = X86::EAX;
10372 SDValue OutChains[4];
10373 SDValue Addr, Disp;
10375 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
10376 DAG.getConstant(10, MVT::i32));
10377 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
10379 // This is storing the opcode for MOV32ri.
10380 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte.
10381 const unsigned char N86Reg = X86_MC::getX86RegNum(NestReg);
10382 OutChains[0] = DAG.getStore(Root, dl,
10383 DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
10384 Trmp, MachinePointerInfo(TrmpAddr),
10387 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
10388 DAG.getConstant(1, MVT::i32));
10389 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr,
10390 MachinePointerInfo(TrmpAddr, 1),
10393 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode.
10394 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
10395 DAG.getConstant(5, MVT::i32));
10396 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr,
10397 MachinePointerInfo(TrmpAddr, 5),
10400 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
10401 DAG.getConstant(6, MVT::i32));
10402 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr,
10403 MachinePointerInfo(TrmpAddr, 6),
10406 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 4);
10410 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op,
10411 SelectionDAG &DAG) const {
10413 The rounding mode is in bits 11:10 of FPSR, and has the following
10415 00 Round to nearest
10420 FLT_ROUNDS, on the other hand, expects the following:
10427 To perform the conversion, we do:
10428 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
10431 MachineFunction &MF = DAG.getMachineFunction();
10432 const TargetMachine &TM = MF.getTarget();
10433 const TargetFrameLowering &TFI = *TM.getFrameLowering();
10434 unsigned StackAlignment = TFI.getStackAlignment();
10435 EVT VT = Op.getValueType();
10436 DebugLoc DL = Op.getDebugLoc();
10438 // Save FP Control Word to stack slot
10439 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false);
10440 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
10443 MachineMemOperand *MMO =
10444 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
10445 MachineMemOperand::MOStore, 2, 2);
10447 SDValue Ops[] = { DAG.getEntryNode(), StackSlot };
10448 SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL,
10449 DAG.getVTList(MVT::Other),
10450 Ops, 2, MVT::i16, MMO);
10452 // Load FP Control Word from stack slot
10453 SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot,
10454 MachinePointerInfo(), false, false, false, 0);
10456 // Transform as necessary
10458 DAG.getNode(ISD::SRL, DL, MVT::i16,
10459 DAG.getNode(ISD::AND, DL, MVT::i16,
10460 CWD, DAG.getConstant(0x800, MVT::i16)),
10461 DAG.getConstant(11, MVT::i8));
10463 DAG.getNode(ISD::SRL, DL, MVT::i16,
10464 DAG.getNode(ISD::AND, DL, MVT::i16,
10465 CWD, DAG.getConstant(0x400, MVT::i16)),
10466 DAG.getConstant(9, MVT::i8));
10469 DAG.getNode(ISD::AND, DL, MVT::i16,
10470 DAG.getNode(ISD::ADD, DL, MVT::i16,
10471 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2),
10472 DAG.getConstant(1, MVT::i16)),
10473 DAG.getConstant(3, MVT::i16));
10476 return DAG.getNode((VT.getSizeInBits() < 16 ?
10477 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal);
10480 SDValue X86TargetLowering::LowerCTLZ(SDValue Op, SelectionDAG &DAG) const {
10481 EVT VT = Op.getValueType();
10483 unsigned NumBits = VT.getSizeInBits();
10484 DebugLoc dl = Op.getDebugLoc();
10486 Op = Op.getOperand(0);
10487 if (VT == MVT::i8) {
10488 // Zero extend to i32 since there is not an i8 bsr.
10490 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
10493 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
10494 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
10495 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
10497 // If src is zero (i.e. bsr sets ZF), returns NumBits.
10500 DAG.getConstant(NumBits+NumBits-1, OpVT),
10501 DAG.getConstant(X86::COND_E, MVT::i8),
10504 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops, array_lengthof(Ops));
10506 // Finally xor with NumBits-1.
10507 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
10510 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
10514 SDValue X86TargetLowering::LowerCTLZ_ZERO_UNDEF(SDValue Op,
10515 SelectionDAG &DAG) const {
10516 EVT VT = Op.getValueType();
10518 unsigned NumBits = VT.getSizeInBits();
10519 DebugLoc dl = Op.getDebugLoc();
10521 Op = Op.getOperand(0);
10522 if (VT == MVT::i8) {
10523 // Zero extend to i32 since there is not an i8 bsr.
10525 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
10528 // Issue a bsr (scan bits in reverse).
10529 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
10530 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
10532 // And xor with NumBits-1.
10533 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
10536 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
10540 SDValue X86TargetLowering::LowerCTTZ(SDValue Op, SelectionDAG &DAG) const {
10541 EVT VT = Op.getValueType();
10542 unsigned NumBits = VT.getSizeInBits();
10543 DebugLoc dl = Op.getDebugLoc();
10544 Op = Op.getOperand(0);
10546 // Issue a bsf (scan bits forward) which also sets EFLAGS.
10547 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
10548 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op);
10550 // If src is zero (i.e. bsf sets ZF), returns NumBits.
10553 DAG.getConstant(NumBits, VT),
10554 DAG.getConstant(X86::COND_E, MVT::i8),
10557 return DAG.getNode(X86ISD::CMOV, dl, VT, Ops, array_lengthof(Ops));
10560 // Lower256IntArith - Break a 256-bit integer operation into two new 128-bit
10561 // ones, and then concatenate the result back.
10562 static SDValue Lower256IntArith(SDValue Op, SelectionDAG &DAG) {
10563 EVT VT = Op.getValueType();
10565 assert(VT.is256BitVector() && VT.isInteger() &&
10566 "Unsupported value type for operation");
10568 unsigned NumElems = VT.getVectorNumElements();
10569 DebugLoc dl = Op.getDebugLoc();
10571 // Extract the LHS vectors
10572 SDValue LHS = Op.getOperand(0);
10573 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
10574 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
10576 // Extract the RHS vectors
10577 SDValue RHS = Op.getOperand(1);
10578 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
10579 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
10581 MVT EltVT = VT.getVectorElementType().getSimpleVT();
10582 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
10584 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
10585 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1),
10586 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2));
10589 SDValue X86TargetLowering::LowerADD(SDValue Op, SelectionDAG &DAG) const {
10590 assert(Op.getValueType().is256BitVector() &&
10591 Op.getValueType().isInteger() &&
10592 "Only handle AVX 256-bit vector integer operation");
10593 return Lower256IntArith(Op, DAG);
10596 SDValue X86TargetLowering::LowerSUB(SDValue Op, SelectionDAG &DAG) const {
10597 assert(Op.getValueType().is256BitVector() &&
10598 Op.getValueType().isInteger() &&
10599 "Only handle AVX 256-bit vector integer operation");
10600 return Lower256IntArith(Op, DAG);
10603 SDValue X86TargetLowering::LowerMUL(SDValue Op, SelectionDAG &DAG) const {
10604 EVT VT = Op.getValueType();
10606 // Decompose 256-bit ops into smaller 128-bit ops.
10607 if (VT.is256BitVector() && !Subtarget->hasAVX2())
10608 return Lower256IntArith(Op, DAG);
10610 assert((VT == MVT::v2i64 || VT == MVT::v4i64) &&
10611 "Only know how to lower V2I64/V4I64 multiply");
10613 DebugLoc dl = Op.getDebugLoc();
10615 // Ahi = psrlqi(a, 32);
10616 // Bhi = psrlqi(b, 32);
10618 // AloBlo = pmuludq(a, b);
10619 // AloBhi = pmuludq(a, Bhi);
10620 // AhiBlo = pmuludq(Ahi, b);
10622 // AloBhi = psllqi(AloBhi, 32);
10623 // AhiBlo = psllqi(AhiBlo, 32);
10624 // return AloBlo + AloBhi + AhiBlo;
10626 SDValue A = Op.getOperand(0);
10627 SDValue B = Op.getOperand(1);
10629 SDValue ShAmt = DAG.getConstant(32, MVT::i32);
10631 SDValue Ahi = DAG.getNode(X86ISD::VSRLI, dl, VT, A, ShAmt);
10632 SDValue Bhi = DAG.getNode(X86ISD::VSRLI, dl, VT, B, ShAmt);
10634 // Bit cast to 32-bit vectors for MULUDQ
10635 EVT MulVT = (VT == MVT::v2i64) ? MVT::v4i32 : MVT::v8i32;
10636 A = DAG.getNode(ISD::BITCAST, dl, MulVT, A);
10637 B = DAG.getNode(ISD::BITCAST, dl, MulVT, B);
10638 Ahi = DAG.getNode(ISD::BITCAST, dl, MulVT, Ahi);
10639 Bhi = DAG.getNode(ISD::BITCAST, dl, MulVT, Bhi);
10641 SDValue AloBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, B);
10642 SDValue AloBhi = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, Bhi);
10643 SDValue AhiBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, Ahi, B);
10645 AloBhi = DAG.getNode(X86ISD::VSHLI, dl, VT, AloBhi, ShAmt);
10646 AhiBlo = DAG.getNode(X86ISD::VSHLI, dl, VT, AhiBlo, ShAmt);
10648 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
10649 return DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
10652 SDValue X86TargetLowering::LowerShift(SDValue Op, SelectionDAG &DAG) const {
10654 EVT VT = Op.getValueType();
10655 DebugLoc dl = Op.getDebugLoc();
10656 SDValue R = Op.getOperand(0);
10657 SDValue Amt = Op.getOperand(1);
10658 LLVMContext *Context = DAG.getContext();
10660 if (!Subtarget->hasSSE2())
10663 // Optimize shl/srl/sra with constant shift amount.
10664 if (isSplatVector(Amt.getNode())) {
10665 SDValue SclrAmt = Amt->getOperand(0);
10666 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(SclrAmt)) {
10667 uint64_t ShiftAmt = C->getZExtValue();
10669 if (VT == MVT::v2i64 || VT == MVT::v4i32 || VT == MVT::v8i16 ||
10670 (Subtarget->hasAVX2() &&
10671 (VT == MVT::v4i64 || VT == MVT::v8i32 || VT == MVT::v16i16))) {
10672 if (Op.getOpcode() == ISD::SHL)
10673 return DAG.getNode(X86ISD::VSHLI, dl, VT, R,
10674 DAG.getConstant(ShiftAmt, MVT::i32));
10675 if (Op.getOpcode() == ISD::SRL)
10676 return DAG.getNode(X86ISD::VSRLI, dl, VT, R,
10677 DAG.getConstant(ShiftAmt, MVT::i32));
10678 if (Op.getOpcode() == ISD::SRA && VT != MVT::v2i64 && VT != MVT::v4i64)
10679 return DAG.getNode(X86ISD::VSRAI, dl, VT, R,
10680 DAG.getConstant(ShiftAmt, MVT::i32));
10683 if (VT == MVT::v16i8) {
10684 if (Op.getOpcode() == ISD::SHL) {
10685 // Make a large shift.
10686 SDValue SHL = DAG.getNode(X86ISD::VSHLI, dl, MVT::v8i16, R,
10687 DAG.getConstant(ShiftAmt, MVT::i32));
10688 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
10689 // Zero out the rightmost bits.
10690 SmallVector<SDValue, 16> V(16,
10691 DAG.getConstant(uint8_t(-1U << ShiftAmt),
10693 return DAG.getNode(ISD::AND, dl, VT, SHL,
10694 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16));
10696 if (Op.getOpcode() == ISD::SRL) {
10697 // Make a large shift.
10698 SDValue SRL = DAG.getNode(X86ISD::VSRLI, dl, MVT::v8i16, R,
10699 DAG.getConstant(ShiftAmt, MVT::i32));
10700 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
10701 // Zero out the leftmost bits.
10702 SmallVector<SDValue, 16> V(16,
10703 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
10705 return DAG.getNode(ISD::AND, dl, VT, SRL,
10706 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16));
10708 if (Op.getOpcode() == ISD::SRA) {
10709 if (ShiftAmt == 7) {
10710 // R s>> 7 === R s< 0
10711 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
10712 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
10715 // R s>> a === ((R u>> a) ^ m) - m
10716 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
10717 SmallVector<SDValue, 16> V(16, DAG.getConstant(128 >> ShiftAmt,
10719 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16);
10720 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
10721 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
10724 llvm_unreachable("Unknown shift opcode.");
10727 if (Subtarget->hasAVX2() && VT == MVT::v32i8) {
10728 if (Op.getOpcode() == ISD::SHL) {
10729 // Make a large shift.
10730 SDValue SHL = DAG.getNode(X86ISD::VSHLI, dl, MVT::v16i16, R,
10731 DAG.getConstant(ShiftAmt, MVT::i32));
10732 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
10733 // Zero out the rightmost bits.
10734 SmallVector<SDValue, 32> V(32,
10735 DAG.getConstant(uint8_t(-1U << ShiftAmt),
10737 return DAG.getNode(ISD::AND, dl, VT, SHL,
10738 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32));
10740 if (Op.getOpcode() == ISD::SRL) {
10741 // Make a large shift.
10742 SDValue SRL = DAG.getNode(X86ISD::VSRLI, dl, MVT::v16i16, R,
10743 DAG.getConstant(ShiftAmt, MVT::i32));
10744 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
10745 // Zero out the leftmost bits.
10746 SmallVector<SDValue, 32> V(32,
10747 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
10749 return DAG.getNode(ISD::AND, dl, VT, SRL,
10750 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32));
10752 if (Op.getOpcode() == ISD::SRA) {
10753 if (ShiftAmt == 7) {
10754 // R s>> 7 === R s< 0
10755 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
10756 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
10759 // R s>> a === ((R u>> a) ^ m) - m
10760 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
10761 SmallVector<SDValue, 32> V(32, DAG.getConstant(128 >> ShiftAmt,
10763 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32);
10764 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
10765 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
10768 llvm_unreachable("Unknown shift opcode.");
10773 // Lower SHL with variable shift amount.
10774 if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) {
10775 Op = DAG.getNode(X86ISD::VSHLI, dl, VT, Op.getOperand(1),
10776 DAG.getConstant(23, MVT::i32));
10778 const uint32_t CV[] = { 0x3f800000U, 0x3f800000U, 0x3f800000U, 0x3f800000U};
10779 Constant *C = ConstantDataVector::get(*Context, CV);
10780 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
10781 SDValue Addend = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
10782 MachinePointerInfo::getConstantPool(),
10783 false, false, false, 16);
10785 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Addend);
10786 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, Op);
10787 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op);
10788 return DAG.getNode(ISD::MUL, dl, VT, Op, R);
10790 if (VT == MVT::v16i8 && Op->getOpcode() == ISD::SHL) {
10791 assert(Subtarget->hasSSE2() && "Need SSE2 for pslli/pcmpeq.");
10794 Op = DAG.getNode(X86ISD::VSHLI, dl, MVT::v8i16, Op.getOperand(1),
10795 DAG.getConstant(5, MVT::i32));
10796 Op = DAG.getNode(ISD::BITCAST, dl, VT, Op);
10798 // Turn 'a' into a mask suitable for VSELECT
10799 SDValue VSelM = DAG.getConstant(0x80, VT);
10800 SDValue OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
10801 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
10803 SDValue CM1 = DAG.getConstant(0x0f, VT);
10804 SDValue CM2 = DAG.getConstant(0x3f, VT);
10806 // r = VSELECT(r, psllw(r & (char16)15, 4), a);
10807 SDValue M = DAG.getNode(ISD::AND, dl, VT, R, CM1);
10808 M = getTargetVShiftNode(X86ISD::VSHLI, dl, MVT::v8i16, M,
10809 DAG.getConstant(4, MVT::i32), DAG);
10810 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
10811 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
10814 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
10815 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
10816 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
10818 // r = VSELECT(r, psllw(r & (char16)63, 2), a);
10819 M = DAG.getNode(ISD::AND, dl, VT, R, CM2);
10820 M = getTargetVShiftNode(X86ISD::VSHLI, dl, MVT::v8i16, M,
10821 DAG.getConstant(2, MVT::i32), DAG);
10822 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
10823 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
10826 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
10827 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
10828 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
10830 // return VSELECT(r, r+r, a);
10831 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel,
10832 DAG.getNode(ISD::ADD, dl, VT, R, R), R);
10836 // Decompose 256-bit shifts into smaller 128-bit shifts.
10837 if (VT.is256BitVector()) {
10838 unsigned NumElems = VT.getVectorNumElements();
10839 MVT EltVT = VT.getVectorElementType().getSimpleVT();
10840 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
10842 // Extract the two vectors
10843 SDValue V1 = Extract128BitVector(R, 0, DAG, dl);
10844 SDValue V2 = Extract128BitVector(R, NumElems/2, DAG, dl);
10846 // Recreate the shift amount vectors
10847 SDValue Amt1, Amt2;
10848 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
10849 // Constant shift amount
10850 SmallVector<SDValue, 4> Amt1Csts;
10851 SmallVector<SDValue, 4> Amt2Csts;
10852 for (unsigned i = 0; i != NumElems/2; ++i)
10853 Amt1Csts.push_back(Amt->getOperand(i));
10854 for (unsigned i = NumElems/2; i != NumElems; ++i)
10855 Amt2Csts.push_back(Amt->getOperand(i));
10857 Amt1 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT,
10858 &Amt1Csts[0], NumElems/2);
10859 Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT,
10860 &Amt2Csts[0], NumElems/2);
10862 // Variable shift amount
10863 Amt1 = Extract128BitVector(Amt, 0, DAG, dl);
10864 Amt2 = Extract128BitVector(Amt, NumElems/2, DAG, dl);
10867 // Issue new vector shifts for the smaller types
10868 V1 = DAG.getNode(Op.getOpcode(), dl, NewVT, V1, Amt1);
10869 V2 = DAG.getNode(Op.getOpcode(), dl, NewVT, V2, Amt2);
10871 // Concatenate the result back
10872 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, V1, V2);
10878 SDValue X86TargetLowering::LowerXALUO(SDValue Op, SelectionDAG &DAG) const {
10879 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
10880 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
10881 // looks for this combo and may remove the "setcc" instruction if the "setcc"
10882 // has only one use.
10883 SDNode *N = Op.getNode();
10884 SDValue LHS = N->getOperand(0);
10885 SDValue RHS = N->getOperand(1);
10886 unsigned BaseOp = 0;
10888 DebugLoc DL = Op.getDebugLoc();
10889 switch (Op.getOpcode()) {
10890 default: llvm_unreachable("Unknown ovf instruction!");
10892 // A subtract of one will be selected as a INC. Note that INC doesn't
10893 // set CF, so we can't do this for UADDO.
10894 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
10896 BaseOp = X86ISD::INC;
10897 Cond = X86::COND_O;
10900 BaseOp = X86ISD::ADD;
10901 Cond = X86::COND_O;
10904 BaseOp = X86ISD::ADD;
10905 Cond = X86::COND_B;
10908 // A subtract of one will be selected as a DEC. Note that DEC doesn't
10909 // set CF, so we can't do this for USUBO.
10910 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
10912 BaseOp = X86ISD::DEC;
10913 Cond = X86::COND_O;
10916 BaseOp = X86ISD::SUB;
10917 Cond = X86::COND_O;
10920 BaseOp = X86ISD::SUB;
10921 Cond = X86::COND_B;
10924 BaseOp = X86ISD::SMUL;
10925 Cond = X86::COND_O;
10927 case ISD::UMULO: { // i64, i8 = umulo lhs, rhs --> i64, i64, i32 umul lhs,rhs
10928 SDVTList VTs = DAG.getVTList(N->getValueType(0), N->getValueType(0),
10930 SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS);
10933 DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
10934 DAG.getConstant(X86::COND_O, MVT::i32),
10935 SDValue(Sum.getNode(), 2));
10937 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
10941 // Also sets EFLAGS.
10942 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
10943 SDValue Sum = DAG.getNode(BaseOp, DL, VTs, LHS, RHS);
10946 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1),
10947 DAG.getConstant(Cond, MVT::i32),
10948 SDValue(Sum.getNode(), 1));
10950 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
10953 SDValue X86TargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
10954 SelectionDAG &DAG) const {
10955 DebugLoc dl = Op.getDebugLoc();
10956 EVT ExtraVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
10957 EVT VT = Op.getValueType();
10959 if (!Subtarget->hasSSE2() || !VT.isVector())
10962 unsigned BitsDiff = VT.getScalarType().getSizeInBits() -
10963 ExtraVT.getScalarType().getSizeInBits();
10964 SDValue ShAmt = DAG.getConstant(BitsDiff, MVT::i32);
10966 switch (VT.getSimpleVT().SimpleTy) {
10967 default: return SDValue();
10970 if (!Subtarget->hasAVX())
10972 if (!Subtarget->hasAVX2()) {
10973 // needs to be split
10974 unsigned NumElems = VT.getVectorNumElements();
10976 // Extract the LHS vectors
10977 SDValue LHS = Op.getOperand(0);
10978 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
10979 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
10981 MVT EltVT = VT.getVectorElementType().getSimpleVT();
10982 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
10984 EVT ExtraEltVT = ExtraVT.getVectorElementType();
10985 unsigned ExtraNumElems = ExtraVT.getVectorNumElements();
10986 ExtraVT = EVT::getVectorVT(*DAG.getContext(), ExtraEltVT,
10988 SDValue Extra = DAG.getValueType(ExtraVT);
10990 LHS1 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, Extra);
10991 LHS2 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, Extra);
10993 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, LHS1, LHS2);;
10998 SDValue Tmp1 = getTargetVShiftNode(X86ISD::VSHLI, dl, VT,
10999 Op.getOperand(0), ShAmt, DAG);
11000 return getTargetVShiftNode(X86ISD::VSRAI, dl, VT, Tmp1, ShAmt, DAG);
11006 SDValue X86TargetLowering::LowerMEMBARRIER(SDValue Op, SelectionDAG &DAG) const{
11007 DebugLoc dl = Op.getDebugLoc();
11009 // Go ahead and emit the fence on x86-64 even if we asked for no-sse2.
11010 // There isn't any reason to disable it if the target processor supports it.
11011 if (!Subtarget->hasSSE2() && !Subtarget->is64Bit()) {
11012 SDValue Chain = Op.getOperand(0);
11013 SDValue Zero = DAG.getConstant(0, MVT::i32);
11015 DAG.getRegister(X86::ESP, MVT::i32), // Base
11016 DAG.getTargetConstant(1, MVT::i8), // Scale
11017 DAG.getRegister(0, MVT::i32), // Index
11018 DAG.getTargetConstant(0, MVT::i32), // Disp
11019 DAG.getRegister(0, MVT::i32), // Segment.
11024 DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops,
11025 array_lengthof(Ops));
11026 return SDValue(Res, 0);
11029 unsigned isDev = cast<ConstantSDNode>(Op.getOperand(5))->getZExtValue();
11031 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
11033 unsigned Op1 = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
11034 unsigned Op2 = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
11035 unsigned Op3 = cast<ConstantSDNode>(Op.getOperand(3))->getZExtValue();
11036 unsigned Op4 = cast<ConstantSDNode>(Op.getOperand(4))->getZExtValue();
11038 // def : Pat<(membarrier (i8 0), (i8 0), (i8 0), (i8 1), (i8 1)), (SFENCE)>;
11039 if (!Op1 && !Op2 && !Op3 && Op4)
11040 return DAG.getNode(X86ISD::SFENCE, dl, MVT::Other, Op.getOperand(0));
11042 // def : Pat<(membarrier (i8 1), (i8 0), (i8 0), (i8 0), (i8 1)), (LFENCE)>;
11043 if (Op1 && !Op2 && !Op3 && !Op4)
11044 return DAG.getNode(X86ISD::LFENCE, dl, MVT::Other, Op.getOperand(0));
11046 // def : Pat<(membarrier (i8 imm), (i8 imm), (i8 imm), (i8 imm), (i8 1)),
11048 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
11051 SDValue X86TargetLowering::LowerATOMIC_FENCE(SDValue Op,
11052 SelectionDAG &DAG) const {
11053 DebugLoc dl = Op.getDebugLoc();
11054 AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>(
11055 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue());
11056 SynchronizationScope FenceScope = static_cast<SynchronizationScope>(
11057 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
11059 // The only fence that needs an instruction is a sequentially-consistent
11060 // cross-thread fence.
11061 if (FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread) {
11062 // Use mfence if we have SSE2 or we're on x86-64 (even if we asked for
11063 // no-sse2). There isn't any reason to disable it if the target processor
11065 if (Subtarget->hasSSE2() || Subtarget->is64Bit())
11066 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
11068 SDValue Chain = Op.getOperand(0);
11069 SDValue Zero = DAG.getConstant(0, MVT::i32);
11071 DAG.getRegister(X86::ESP, MVT::i32), // Base
11072 DAG.getTargetConstant(1, MVT::i8), // Scale
11073 DAG.getRegister(0, MVT::i32), // Index
11074 DAG.getTargetConstant(0, MVT::i32), // Disp
11075 DAG.getRegister(0, MVT::i32), // Segment.
11080 DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops,
11081 array_lengthof(Ops));
11082 return SDValue(Res, 0);
11085 // MEMBARRIER is a compiler barrier; it codegens to a no-op.
11086 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
11090 SDValue X86TargetLowering::LowerCMP_SWAP(SDValue Op, SelectionDAG &DAG) const {
11091 EVT T = Op.getValueType();
11092 DebugLoc DL = Op.getDebugLoc();
11095 switch(T.getSimpleVT().SimpleTy) {
11096 default: llvm_unreachable("Invalid value type!");
11097 case MVT::i8: Reg = X86::AL; size = 1; break;
11098 case MVT::i16: Reg = X86::AX; size = 2; break;
11099 case MVT::i32: Reg = X86::EAX; size = 4; break;
11101 assert(Subtarget->is64Bit() && "Node not type legal!");
11102 Reg = X86::RAX; size = 8;
11105 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg,
11106 Op.getOperand(2), SDValue());
11107 SDValue Ops[] = { cpIn.getValue(0),
11110 DAG.getTargetConstant(size, MVT::i8),
11111 cpIn.getValue(1) };
11112 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
11113 MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand();
11114 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys,
11117 DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1));
11121 SDValue X86TargetLowering::LowerREADCYCLECOUNTER(SDValue Op,
11122 SelectionDAG &DAG) const {
11123 assert(Subtarget->is64Bit() && "Result not type legalized?");
11124 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
11125 SDValue TheChain = Op.getOperand(0);
11126 DebugLoc dl = Op.getDebugLoc();
11127 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
11128 SDValue rax = DAG.getCopyFromReg(rd, dl, X86::RAX, MVT::i64, rd.getValue(1));
11129 SDValue rdx = DAG.getCopyFromReg(rax.getValue(1), dl, X86::RDX, MVT::i64,
11131 SDValue Tmp = DAG.getNode(ISD::SHL, dl, MVT::i64, rdx,
11132 DAG.getConstant(32, MVT::i8));
11134 DAG.getNode(ISD::OR, dl, MVT::i64, rax, Tmp),
11137 return DAG.getMergeValues(Ops, 2, dl);
11140 SDValue X86TargetLowering::LowerBITCAST(SDValue Op,
11141 SelectionDAG &DAG) const {
11142 EVT SrcVT = Op.getOperand(0).getValueType();
11143 EVT DstVT = Op.getValueType();
11144 assert(Subtarget->is64Bit() && !Subtarget->hasSSE2() &&
11145 Subtarget->hasMMX() && "Unexpected custom BITCAST");
11146 assert((DstVT == MVT::i64 ||
11147 (DstVT.isVector() && DstVT.getSizeInBits()==64)) &&
11148 "Unexpected custom BITCAST");
11149 // i64 <=> MMX conversions are Legal.
11150 if (SrcVT==MVT::i64 && DstVT.isVector())
11152 if (DstVT==MVT::i64 && SrcVT.isVector())
11154 // MMX <=> MMX conversions are Legal.
11155 if (SrcVT.isVector() && DstVT.isVector())
11157 // All other conversions need to be expanded.
11161 SDValue X86TargetLowering::LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) const {
11162 SDNode *Node = Op.getNode();
11163 DebugLoc dl = Node->getDebugLoc();
11164 EVT T = Node->getValueType(0);
11165 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
11166 DAG.getConstant(0, T), Node->getOperand(2));
11167 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
11168 cast<AtomicSDNode>(Node)->getMemoryVT(),
11169 Node->getOperand(0),
11170 Node->getOperand(1), negOp,
11171 cast<AtomicSDNode>(Node)->getSrcValue(),
11172 cast<AtomicSDNode>(Node)->getAlignment(),
11173 cast<AtomicSDNode>(Node)->getOrdering(),
11174 cast<AtomicSDNode>(Node)->getSynchScope());
11177 static SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) {
11178 SDNode *Node = Op.getNode();
11179 DebugLoc dl = Node->getDebugLoc();
11180 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
11182 // Convert seq_cst store -> xchg
11183 // Convert wide store -> swap (-> cmpxchg8b/cmpxchg16b)
11184 // FIXME: On 32-bit, store -> fist or movq would be more efficient
11185 // (The only way to get a 16-byte store is cmpxchg16b)
11186 // FIXME: 16-byte ATOMIC_SWAP isn't actually hooked up at the moment.
11187 if (cast<AtomicSDNode>(Node)->getOrdering() == SequentiallyConsistent ||
11188 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
11189 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
11190 cast<AtomicSDNode>(Node)->getMemoryVT(),
11191 Node->getOperand(0),
11192 Node->getOperand(1), Node->getOperand(2),
11193 cast<AtomicSDNode>(Node)->getMemOperand(),
11194 cast<AtomicSDNode>(Node)->getOrdering(),
11195 cast<AtomicSDNode>(Node)->getSynchScope());
11196 return Swap.getValue(1);
11198 // Other atomic stores have a simple pattern.
11202 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
11203 EVT VT = Op.getNode()->getValueType(0);
11205 // Let legalize expand this if it isn't a legal type yet.
11206 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
11209 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
11212 bool ExtraOp = false;
11213 switch (Op.getOpcode()) {
11214 default: llvm_unreachable("Invalid code");
11215 case ISD::ADDC: Opc = X86ISD::ADD; break;
11216 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break;
11217 case ISD::SUBC: Opc = X86ISD::SUB; break;
11218 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break;
11222 return DAG.getNode(Opc, Op->getDebugLoc(), VTs, Op.getOperand(0),
11224 return DAG.getNode(Opc, Op->getDebugLoc(), VTs, Op.getOperand(0),
11225 Op.getOperand(1), Op.getOperand(2));
11228 /// LowerOperation - Provide custom lowering hooks for some operations.
11230 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
11231 switch (Op.getOpcode()) {
11232 default: llvm_unreachable("Should not custom lower this!");
11233 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op,DAG);
11234 case ISD::MEMBARRIER: return LowerMEMBARRIER(Op,DAG);
11235 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op,DAG);
11236 case ISD::ATOMIC_CMP_SWAP: return LowerCMP_SWAP(Op,DAG);
11237 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
11238 case ISD::ATOMIC_STORE: return LowerATOMIC_STORE(Op,DAG);
11239 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
11240 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
11241 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
11242 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
11243 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
11244 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op, DAG);
11245 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, DAG);
11246 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
11247 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
11248 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
11249 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
11250 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
11251 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
11252 case ISD::SHL_PARTS:
11253 case ISD::SRA_PARTS:
11254 case ISD::SRL_PARTS: return LowerShiftParts(Op, DAG);
11255 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
11256 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
11257 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
11258 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
11259 case ISD::FABS: return LowerFABS(Op, DAG);
11260 case ISD::FNEG: return LowerFNEG(Op, DAG);
11261 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
11262 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG);
11263 case ISD::SETCC: return LowerSETCC(Op, DAG);
11264 case ISD::SELECT: return LowerSELECT(Op, DAG);
11265 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
11266 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
11267 case ISD::VASTART: return LowerVASTART(Op, DAG);
11268 case ISD::VAARG: return LowerVAARG(Op, DAG);
11269 case ISD::VACOPY: return LowerVACOPY(Op, DAG);
11270 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
11271 case ISD::INTRINSIC_W_CHAIN: return LowerINTRINSIC_W_CHAIN(Op, DAG);
11272 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
11273 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
11274 case ISD::FRAME_TO_ARGS_OFFSET:
11275 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
11276 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
11277 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
11278 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
11279 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
11280 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
11281 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
11282 case ISD::CTLZ_ZERO_UNDEF: return LowerCTLZ_ZERO_UNDEF(Op, DAG);
11283 case ISD::CTTZ: return LowerCTTZ(Op, DAG);
11284 case ISD::MUL: return LowerMUL(Op, DAG);
11287 case ISD::SHL: return LowerShift(Op, DAG);
11293 case ISD::UMULO: return LowerXALUO(Op, DAG);
11294 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, DAG);
11295 case ISD::BITCAST: return LowerBITCAST(Op, DAG);
11299 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
11300 case ISD::ADD: return LowerADD(Op, DAG);
11301 case ISD::SUB: return LowerSUB(Op, DAG);
11305 static void ReplaceATOMIC_LOAD(SDNode *Node,
11306 SmallVectorImpl<SDValue> &Results,
11307 SelectionDAG &DAG) {
11308 DebugLoc dl = Node->getDebugLoc();
11309 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
11311 // Convert wide load -> cmpxchg8b/cmpxchg16b
11312 // FIXME: On 32-bit, load -> fild or movq would be more efficient
11313 // (The only way to get a 16-byte load is cmpxchg16b)
11314 // FIXME: 16-byte ATOMIC_CMP_SWAP isn't actually hooked up at the moment.
11315 SDValue Zero = DAG.getConstant(0, VT);
11316 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, dl, VT,
11317 Node->getOperand(0),
11318 Node->getOperand(1), Zero, Zero,
11319 cast<AtomicSDNode>(Node)->getMemOperand(),
11320 cast<AtomicSDNode>(Node)->getOrdering(),
11321 cast<AtomicSDNode>(Node)->getSynchScope());
11322 Results.push_back(Swap.getValue(0));
11323 Results.push_back(Swap.getValue(1));
11327 ReplaceATOMIC_BINARY_64(SDNode *Node, SmallVectorImpl<SDValue>&Results,
11328 SelectionDAG &DAG, unsigned NewOp) {
11329 DebugLoc dl = Node->getDebugLoc();
11330 assert (Node->getValueType(0) == MVT::i64 &&
11331 "Only know how to expand i64 atomics");
11333 SDValue Chain = Node->getOperand(0);
11334 SDValue In1 = Node->getOperand(1);
11335 SDValue In2L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
11336 Node->getOperand(2), DAG.getIntPtrConstant(0));
11337 SDValue In2H = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
11338 Node->getOperand(2), DAG.getIntPtrConstant(1));
11339 SDValue Ops[] = { Chain, In1, In2L, In2H };
11340 SDVTList Tys = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other);
11342 DAG.getMemIntrinsicNode(NewOp, dl, Tys, Ops, 4, MVT::i64,
11343 cast<MemSDNode>(Node)->getMemOperand());
11344 SDValue OpsF[] = { Result.getValue(0), Result.getValue(1)};
11345 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2));
11346 Results.push_back(Result.getValue(2));
11349 /// ReplaceNodeResults - Replace a node with an illegal result type
11350 /// with a new node built out of custom code.
11351 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
11352 SmallVectorImpl<SDValue>&Results,
11353 SelectionDAG &DAG) const {
11354 DebugLoc dl = N->getDebugLoc();
11355 switch (N->getOpcode()) {
11357 llvm_unreachable("Do not know how to custom type legalize this operation!");
11358 case ISD::SIGN_EXTEND_INREG:
11363 // We don't want to expand or promote these.
11365 case ISD::FP_TO_SINT:
11366 case ISD::FP_TO_UINT: {
11367 bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT;
11369 if (!IsSigned && !isIntegerTypeFTOL(SDValue(N, 0).getValueType()))
11372 std::pair<SDValue,SDValue> Vals =
11373 FP_TO_INTHelper(SDValue(N, 0), DAG, IsSigned, /*IsReplace=*/ true);
11374 SDValue FIST = Vals.first, StackSlot = Vals.second;
11375 if (FIST.getNode() != 0) {
11376 EVT VT = N->getValueType(0);
11377 // Return a load from the stack slot.
11378 if (StackSlot.getNode() != 0)
11379 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot,
11380 MachinePointerInfo(),
11381 false, false, false, 0));
11383 Results.push_back(FIST);
11387 case ISD::READCYCLECOUNTER: {
11388 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
11389 SDValue TheChain = N->getOperand(0);
11390 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
11391 SDValue eax = DAG.getCopyFromReg(rd, dl, X86::EAX, MVT::i32,
11393 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), dl, X86::EDX, MVT::i32,
11395 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
11396 SDValue Ops[] = { eax, edx };
11397 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Ops, 2));
11398 Results.push_back(edx.getValue(1));
11401 case ISD::ATOMIC_CMP_SWAP: {
11402 EVT T = N->getValueType(0);
11403 assert((T == MVT::i64 || T == MVT::i128) && "can only expand cmpxchg pair");
11404 bool Regs64bit = T == MVT::i128;
11405 EVT HalfT = Regs64bit ? MVT::i64 : MVT::i32;
11406 SDValue cpInL, cpInH;
11407 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
11408 DAG.getConstant(0, HalfT));
11409 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
11410 DAG.getConstant(1, HalfT));
11411 cpInL = DAG.getCopyToReg(N->getOperand(0), dl,
11412 Regs64bit ? X86::RAX : X86::EAX,
11414 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl,
11415 Regs64bit ? X86::RDX : X86::EDX,
11416 cpInH, cpInL.getValue(1));
11417 SDValue swapInL, swapInH;
11418 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
11419 DAG.getConstant(0, HalfT));
11420 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
11421 DAG.getConstant(1, HalfT));
11422 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl,
11423 Regs64bit ? X86::RBX : X86::EBX,
11424 swapInL, cpInH.getValue(1));
11425 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl,
11426 Regs64bit ? X86::RCX : X86::ECX,
11427 swapInH, swapInL.getValue(1));
11428 SDValue Ops[] = { swapInH.getValue(0),
11430 swapInH.getValue(1) };
11431 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
11432 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand();
11433 unsigned Opcode = Regs64bit ? X86ISD::LCMPXCHG16_DAG :
11434 X86ISD::LCMPXCHG8_DAG;
11435 SDValue Result = DAG.getMemIntrinsicNode(Opcode, dl, Tys,
11437 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl,
11438 Regs64bit ? X86::RAX : X86::EAX,
11439 HalfT, Result.getValue(1));
11440 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl,
11441 Regs64bit ? X86::RDX : X86::EDX,
11442 HalfT, cpOutL.getValue(2));
11443 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
11444 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, T, OpsF, 2));
11445 Results.push_back(cpOutH.getValue(1));
11448 case ISD::ATOMIC_LOAD_ADD:
11449 case ISD::ATOMIC_LOAD_AND:
11450 case ISD::ATOMIC_LOAD_NAND:
11451 case ISD::ATOMIC_LOAD_OR:
11452 case ISD::ATOMIC_LOAD_SUB:
11453 case ISD::ATOMIC_LOAD_XOR:
11454 case ISD::ATOMIC_SWAP: {
11456 switch (N->getOpcode()) {
11457 default: llvm_unreachable("Unexpected opcode");
11458 case ISD::ATOMIC_LOAD_ADD:
11459 Opc = X86ISD::ATOMADD64_DAG;
11461 case ISD::ATOMIC_LOAD_AND:
11462 Opc = X86ISD::ATOMAND64_DAG;
11464 case ISD::ATOMIC_LOAD_NAND:
11465 Opc = X86ISD::ATOMNAND64_DAG;
11467 case ISD::ATOMIC_LOAD_OR:
11468 Opc = X86ISD::ATOMOR64_DAG;
11470 case ISD::ATOMIC_LOAD_SUB:
11471 Opc = X86ISD::ATOMSUB64_DAG;
11473 case ISD::ATOMIC_LOAD_XOR:
11474 Opc = X86ISD::ATOMXOR64_DAG;
11476 case ISD::ATOMIC_SWAP:
11477 Opc = X86ISD::ATOMSWAP64_DAG;
11480 ReplaceATOMIC_BINARY_64(N, Results, DAG, Opc);
11483 case ISD::ATOMIC_LOAD:
11484 ReplaceATOMIC_LOAD(N, Results, DAG);
11488 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
11490 default: return NULL;
11491 case X86ISD::BSF: return "X86ISD::BSF";
11492 case X86ISD::BSR: return "X86ISD::BSR";
11493 case X86ISD::SHLD: return "X86ISD::SHLD";
11494 case X86ISD::SHRD: return "X86ISD::SHRD";
11495 case X86ISD::FAND: return "X86ISD::FAND";
11496 case X86ISD::FOR: return "X86ISD::FOR";
11497 case X86ISD::FXOR: return "X86ISD::FXOR";
11498 case X86ISD::FSRL: return "X86ISD::FSRL";
11499 case X86ISD::FILD: return "X86ISD::FILD";
11500 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
11501 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
11502 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
11503 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
11504 case X86ISD::FLD: return "X86ISD::FLD";
11505 case X86ISD::FST: return "X86ISD::FST";
11506 case X86ISD::CALL: return "X86ISD::CALL";
11507 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
11508 case X86ISD::BT: return "X86ISD::BT";
11509 case X86ISD::CMP: return "X86ISD::CMP";
11510 case X86ISD::COMI: return "X86ISD::COMI";
11511 case X86ISD::UCOMI: return "X86ISD::UCOMI";
11512 case X86ISD::SETCC: return "X86ISD::SETCC";
11513 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY";
11514 case X86ISD::FSETCCsd: return "X86ISD::FSETCCsd";
11515 case X86ISD::FSETCCss: return "X86ISD::FSETCCss";
11516 case X86ISD::CMOV: return "X86ISD::CMOV";
11517 case X86ISD::BRCOND: return "X86ISD::BRCOND";
11518 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
11519 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
11520 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
11521 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
11522 case X86ISD::Wrapper: return "X86ISD::Wrapper";
11523 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
11524 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
11525 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
11526 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
11527 case X86ISD::PINSRB: return "X86ISD::PINSRB";
11528 case X86ISD::PINSRW: return "X86ISD::PINSRW";
11529 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
11530 case X86ISD::ANDNP: return "X86ISD::ANDNP";
11531 case X86ISD::PSIGN: return "X86ISD::PSIGN";
11532 case X86ISD::BLENDV: return "X86ISD::BLENDV";
11533 case X86ISD::BLENDPW: return "X86ISD::BLENDPW";
11534 case X86ISD::BLENDPS: return "X86ISD::BLENDPS";
11535 case X86ISD::BLENDPD: return "X86ISD::BLENDPD";
11536 case X86ISD::HADD: return "X86ISD::HADD";
11537 case X86ISD::HSUB: return "X86ISD::HSUB";
11538 case X86ISD::FHADD: return "X86ISD::FHADD";
11539 case X86ISD::FHSUB: return "X86ISD::FHSUB";
11540 case X86ISD::FMAX: return "X86ISD::FMAX";
11541 case X86ISD::FMIN: return "X86ISD::FMIN";
11542 case X86ISD::FMAXC: return "X86ISD::FMAXC";
11543 case X86ISD::FMINC: return "X86ISD::FMINC";
11544 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
11545 case X86ISD::FRCP: return "X86ISD::FRCP";
11546 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
11547 case X86ISD::TLSBASEADDR: return "X86ISD::TLSBASEADDR";
11548 case X86ISD::TLSCALL: return "X86ISD::TLSCALL";
11549 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
11550 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
11551 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
11552 case X86ISD::FNSTSW16r: return "X86ISD::FNSTSW16r";
11553 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
11554 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
11555 case X86ISD::ATOMADD64_DAG: return "X86ISD::ATOMADD64_DAG";
11556 case X86ISD::ATOMSUB64_DAG: return "X86ISD::ATOMSUB64_DAG";
11557 case X86ISD::ATOMOR64_DAG: return "X86ISD::ATOMOR64_DAG";
11558 case X86ISD::ATOMXOR64_DAG: return "X86ISD::ATOMXOR64_DAG";
11559 case X86ISD::ATOMAND64_DAG: return "X86ISD::ATOMAND64_DAG";
11560 case X86ISD::ATOMNAND64_DAG: return "X86ISD::ATOMNAND64_DAG";
11561 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
11562 case X86ISD::VSEXT_MOVL: return "X86ISD::VSEXT_MOVL";
11563 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
11564 case X86ISD::VFPEXT: return "X86ISD::VFPEXT";
11565 case X86ISD::VSHLDQ: return "X86ISD::VSHLDQ";
11566 case X86ISD::VSRLDQ: return "X86ISD::VSRLDQ";
11567 case X86ISD::VSHL: return "X86ISD::VSHL";
11568 case X86ISD::VSRL: return "X86ISD::VSRL";
11569 case X86ISD::VSRA: return "X86ISD::VSRA";
11570 case X86ISD::VSHLI: return "X86ISD::VSHLI";
11571 case X86ISD::VSRLI: return "X86ISD::VSRLI";
11572 case X86ISD::VSRAI: return "X86ISD::VSRAI";
11573 case X86ISD::CMPP: return "X86ISD::CMPP";
11574 case X86ISD::PCMPEQ: return "X86ISD::PCMPEQ";
11575 case X86ISD::PCMPGT: return "X86ISD::PCMPGT";
11576 case X86ISD::ADD: return "X86ISD::ADD";
11577 case X86ISD::SUB: return "X86ISD::SUB";
11578 case X86ISD::ADC: return "X86ISD::ADC";
11579 case X86ISD::SBB: return "X86ISD::SBB";
11580 case X86ISD::SMUL: return "X86ISD::SMUL";
11581 case X86ISD::UMUL: return "X86ISD::UMUL";
11582 case X86ISD::INC: return "X86ISD::INC";
11583 case X86ISD::DEC: return "X86ISD::DEC";
11584 case X86ISD::OR: return "X86ISD::OR";
11585 case X86ISD::XOR: return "X86ISD::XOR";
11586 case X86ISD::AND: return "X86ISD::AND";
11587 case X86ISD::ANDN: return "X86ISD::ANDN";
11588 case X86ISD::BLSI: return "X86ISD::BLSI";
11589 case X86ISD::BLSMSK: return "X86ISD::BLSMSK";
11590 case X86ISD::BLSR: return "X86ISD::BLSR";
11591 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
11592 case X86ISD::PTEST: return "X86ISD::PTEST";
11593 case X86ISD::TESTP: return "X86ISD::TESTP";
11594 case X86ISD::PALIGN: return "X86ISD::PALIGN";
11595 case X86ISD::PSHUFD: return "X86ISD::PSHUFD";
11596 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW";
11597 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW";
11598 case X86ISD::SHUFP: return "X86ISD::SHUFP";
11599 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS";
11600 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD";
11601 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS";
11602 case X86ISD::MOVLPS: return "X86ISD::MOVLPS";
11603 case X86ISD::MOVLPD: return "X86ISD::MOVLPD";
11604 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP";
11605 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP";
11606 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP";
11607 case X86ISD::MOVSD: return "X86ISD::MOVSD";
11608 case X86ISD::MOVSS: return "X86ISD::MOVSS";
11609 case X86ISD::UNPCKL: return "X86ISD::UNPCKL";
11610 case X86ISD::UNPCKH: return "X86ISD::UNPCKH";
11611 case X86ISD::VBROADCAST: return "X86ISD::VBROADCAST";
11612 case X86ISD::VPERMILP: return "X86ISD::VPERMILP";
11613 case X86ISD::VPERM2X128: return "X86ISD::VPERM2X128";
11614 case X86ISD::VPERMV: return "X86ISD::VPERMV";
11615 case X86ISD::VPERMI: return "X86ISD::VPERMI";
11616 case X86ISD::PMULUDQ: return "X86ISD::PMULUDQ";
11617 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
11618 case X86ISD::VAARG_64: return "X86ISD::VAARG_64";
11619 case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA";
11620 case X86ISD::MEMBARRIER: return "X86ISD::MEMBARRIER";
11621 case X86ISD::SEG_ALLOCA: return "X86ISD::SEG_ALLOCA";
11622 case X86ISD::WIN_FTOL: return "X86ISD::WIN_FTOL";
11623 case X86ISD::SAHF: return "X86ISD::SAHF";
11624 case X86ISD::RDRAND: return "X86ISD::RDRAND";
11625 case X86ISD::FMADD: return "X86ISD::FMADD";
11626 case X86ISD::FMSUB: return "X86ISD::FMSUB";
11627 case X86ISD::FNMADD: return "X86ISD::FNMADD";
11628 case X86ISD::FNMSUB: return "X86ISD::FNMSUB";
11629 case X86ISD::FMADDSUB: return "X86ISD::FMADDSUB";
11630 case X86ISD::FMSUBADD: return "X86ISD::FMSUBADD";
11634 // isLegalAddressingMode - Return true if the addressing mode represented
11635 // by AM is legal for this target, for a load/store of the specified type.
11636 bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
11638 // X86 supports extremely general addressing modes.
11639 CodeModel::Model M = getTargetMachine().getCodeModel();
11640 Reloc::Model R = getTargetMachine().getRelocationModel();
11642 // X86 allows a sign-extended 32-bit immediate field as a displacement.
11643 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != NULL))
11648 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
11650 // If a reference to this global requires an extra load, we can't fold it.
11651 if (isGlobalStubReference(GVFlags))
11654 // If BaseGV requires a register for the PIC base, we cannot also have a
11655 // BaseReg specified.
11656 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
11659 // If lower 4G is not available, then we must use rip-relative addressing.
11660 if ((M != CodeModel::Small || R != Reloc::Static) &&
11661 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
11665 switch (AM.Scale) {
11671 // These scales always work.
11676 // These scales are formed with basereg+scalereg. Only accept if there is
11681 default: // Other stuff never works.
11689 bool X86TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
11690 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
11692 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
11693 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
11694 if (NumBits1 <= NumBits2)
11699 bool X86TargetLowering::isLegalICmpImmediate(int64_t Imm) const {
11700 return Imm == (int32_t)Imm;
11703 bool X86TargetLowering::isLegalAddImmediate(int64_t Imm) const {
11704 // Can also use sub to handle negated immediates.
11705 return Imm == (int32_t)Imm;
11708 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
11709 if (!VT1.isInteger() || !VT2.isInteger())
11711 unsigned NumBits1 = VT1.getSizeInBits();
11712 unsigned NumBits2 = VT2.getSizeInBits();
11713 if (NumBits1 <= NumBits2)
11718 bool X86TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
11719 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
11720 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit();
11723 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
11724 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
11725 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
11728 bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
11729 // i16 instructions are longer (0x66 prefix) and potentially slower.
11730 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
11733 /// isShuffleMaskLegal - Targets can use this to indicate that they only
11734 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
11735 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
11736 /// are assumed to be legal.
11738 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
11740 // Very little shuffling can be done for 64-bit vectors right now.
11741 if (VT.getSizeInBits() == 64)
11744 // FIXME: pshufb, blends, shifts.
11745 return (VT.getVectorNumElements() == 2 ||
11746 ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
11747 isMOVLMask(M, VT) ||
11748 isSHUFPMask(M, VT, Subtarget->hasAVX()) ||
11749 isPSHUFDMask(M, VT) ||
11750 isPSHUFHWMask(M, VT, Subtarget->hasAVX2()) ||
11751 isPSHUFLWMask(M, VT, Subtarget->hasAVX2()) ||
11752 isPALIGNRMask(M, VT, Subtarget) ||
11753 isUNPCKLMask(M, VT, Subtarget->hasAVX2()) ||
11754 isUNPCKHMask(M, VT, Subtarget->hasAVX2()) ||
11755 isUNPCKL_v_undef_Mask(M, VT, Subtarget->hasAVX2()) ||
11756 isUNPCKH_v_undef_Mask(M, VT, Subtarget->hasAVX2()));
11760 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
11762 unsigned NumElts = VT.getVectorNumElements();
11763 // FIXME: This collection of masks seems suspect.
11766 if (NumElts == 4 && VT.is128BitVector()) {
11767 return (isMOVLMask(Mask, VT) ||
11768 isCommutedMOVLMask(Mask, VT, true) ||
11769 isSHUFPMask(Mask, VT, Subtarget->hasAVX()) ||
11770 isSHUFPMask(Mask, VT, Subtarget->hasAVX(), /* Commuted */ true));
11775 //===----------------------------------------------------------------------===//
11776 // X86 Scheduler Hooks
11777 //===----------------------------------------------------------------------===//
11779 // private utility function
11780 MachineBasicBlock *
11781 X86TargetLowering::EmitAtomicBitwiseWithCustomInserter(MachineInstr *bInstr,
11782 MachineBasicBlock *MBB,
11789 const TargetRegisterClass *RC,
11790 bool Invert) const {
11791 // For the atomic bitwise operator, we generate
11794 // ld t1 = [bitinstr.addr]
11795 // op t2 = t1, [bitinstr.val]
11796 // not t3 = t2 (if Invert)
11798 // lcs dest = [bitinstr.addr], t3 [EAX is implicit]
11800 // fallthrough -->nextMBB
11801 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11802 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
11803 MachineFunction::iterator MBBIter = MBB;
11806 /// First build the CFG
11807 MachineFunction *F = MBB->getParent();
11808 MachineBasicBlock *thisMBB = MBB;
11809 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
11810 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
11811 F->insert(MBBIter, newMBB);
11812 F->insert(MBBIter, nextMBB);
11814 // Transfer the remainder of thisMBB and its successor edges to nextMBB.
11815 nextMBB->splice(nextMBB->begin(), thisMBB,
11816 llvm::next(MachineBasicBlock::iterator(bInstr)),
11818 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
11820 // Update thisMBB to fall through to newMBB
11821 thisMBB->addSuccessor(newMBB);
11823 // newMBB jumps to itself and fall through to nextMBB
11824 newMBB->addSuccessor(nextMBB);
11825 newMBB->addSuccessor(newMBB);
11827 // Insert instructions into newMBB based on incoming instruction
11828 assert(bInstr->getNumOperands() < X86::AddrNumOperands + 4 &&
11829 "unexpected number of operands");
11830 DebugLoc dl = bInstr->getDebugLoc();
11831 MachineOperand& destOper = bInstr->getOperand(0);
11832 MachineOperand* argOpers[2 + X86::AddrNumOperands];
11833 int numArgs = bInstr->getNumOperands() - 1;
11834 for (int i=0; i < numArgs; ++i)
11835 argOpers[i] = &bInstr->getOperand(i+1);
11837 // x86 address has 4 operands: base, index, scale, and displacement
11838 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3]
11839 int valArgIndx = lastAddrIndx + 1;
11841 unsigned t1 = F->getRegInfo().createVirtualRegister(RC);
11842 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(LoadOpc), t1);
11843 for (int i=0; i <= lastAddrIndx; ++i)
11844 (*MIB).addOperand(*argOpers[i]);
11846 unsigned t2 = F->getRegInfo().createVirtualRegister(RC);
11847 assert((argOpers[valArgIndx]->isReg() ||
11848 argOpers[valArgIndx]->isImm()) &&
11849 "invalid operand");
11850 if (argOpers[valArgIndx]->isReg())
11851 MIB = BuildMI(newMBB, dl, TII->get(regOpc), t2);
11853 MIB = BuildMI(newMBB, dl, TII->get(immOpc), t2);
11855 (*MIB).addOperand(*argOpers[valArgIndx]);
11857 unsigned t3 = F->getRegInfo().createVirtualRegister(RC);
11859 MIB = BuildMI(newMBB, dl, TII->get(notOpc), t3).addReg(t2);
11864 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), EAXreg);
11867 MIB = BuildMI(newMBB, dl, TII->get(CXchgOpc));
11868 for (int i=0; i <= lastAddrIndx; ++i)
11869 (*MIB).addOperand(*argOpers[i]);
11871 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand");
11872 (*MIB).setMemRefs(bInstr->memoperands_begin(),
11873 bInstr->memoperands_end());
11875 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), destOper.getReg());
11876 MIB.addReg(EAXreg);
11879 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB);
11881 bInstr->eraseFromParent(); // The pseudo instruction is gone now.
11885 // private utility function: 64 bit atomics on 32 bit host.
11886 MachineBasicBlock *
11887 X86TargetLowering::EmitAtomicBit6432WithCustomInserter(MachineInstr *bInstr,
11888 MachineBasicBlock *MBB,
11893 bool Invert) const {
11894 // For the atomic bitwise operator, we generate
11895 // thisMBB (instructions are in pairs, except cmpxchg8b)
11896 // ld t1,t2 = [bitinstr.addr]
11898 // out1, out2 = phi (thisMBB, t1/t2) (newMBB, t3/t4)
11899 // op t5, t6 <- out1, out2, [bitinstr.val]
11900 // (for SWAP, substitute: mov t5, t6 <- [bitinstr.val])
11901 // neg t7, t8 < t5, t6 (if Invert)
11902 // mov ECX, EBX <- t5, t6
11903 // mov EAX, EDX <- t1, t2
11904 // cmpxchg8b [bitinstr.addr] [EAX, EDX, EBX, ECX implicit]
11905 // mov t3, t4 <- EAX, EDX
11907 // result in out1, out2
11908 // fallthrough -->nextMBB
11910 const TargetRegisterClass *RC = &X86::GR32RegClass;
11911 const unsigned LoadOpc = X86::MOV32rm;
11912 const unsigned NotOpc = X86::NOT32r;
11913 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11914 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
11915 MachineFunction::iterator MBBIter = MBB;
11918 /// First build the CFG
11919 MachineFunction *F = MBB->getParent();
11920 MachineBasicBlock *thisMBB = MBB;
11921 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
11922 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
11923 F->insert(MBBIter, newMBB);
11924 F->insert(MBBIter, nextMBB);
11926 // Transfer the remainder of thisMBB and its successor edges to nextMBB.
11927 nextMBB->splice(nextMBB->begin(), thisMBB,
11928 llvm::next(MachineBasicBlock::iterator(bInstr)),
11930 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
11932 // Update thisMBB to fall through to newMBB
11933 thisMBB->addSuccessor(newMBB);
11935 // newMBB jumps to itself and fall through to nextMBB
11936 newMBB->addSuccessor(nextMBB);
11937 newMBB->addSuccessor(newMBB);
11939 DebugLoc dl = bInstr->getDebugLoc();
11940 // Insert instructions into newMBB based on incoming instruction
11941 // There are 8 "real" operands plus 9 implicit def/uses, ignored here.
11942 assert(bInstr->getNumOperands() < X86::AddrNumOperands + 14 &&
11943 "unexpected number of operands");
11944 MachineOperand& dest1Oper = bInstr->getOperand(0);
11945 MachineOperand& dest2Oper = bInstr->getOperand(1);
11946 MachineOperand* argOpers[2 + X86::AddrNumOperands];
11947 for (int i=0; i < 2 + X86::AddrNumOperands; ++i) {
11948 argOpers[i] = &bInstr->getOperand(i+2);
11950 // We use some of the operands multiple times, so conservatively just
11951 // clear any kill flags that might be present.
11952 if (argOpers[i]->isReg() && argOpers[i]->isUse())
11953 argOpers[i]->setIsKill(false);
11956 // x86 address has 5 operands: base, index, scale, displacement, and segment.
11957 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3]
11959 unsigned t1 = F->getRegInfo().createVirtualRegister(RC);
11960 MachineInstrBuilder MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t1);
11961 for (int i=0; i <= lastAddrIndx; ++i)
11962 (*MIB).addOperand(*argOpers[i]);
11963 unsigned t2 = F->getRegInfo().createVirtualRegister(RC);
11964 MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t2);
11965 // add 4 to displacement.
11966 for (int i=0; i <= lastAddrIndx-2; ++i)
11967 (*MIB).addOperand(*argOpers[i]);
11968 MachineOperand newOp3 = *(argOpers[3]);
11969 if (newOp3.isImm())
11970 newOp3.setImm(newOp3.getImm()+4);
11972 newOp3.setOffset(newOp3.getOffset()+4);
11973 (*MIB).addOperand(newOp3);
11974 (*MIB).addOperand(*argOpers[lastAddrIndx]);
11976 // t3/4 are defined later, at the bottom of the loop
11977 unsigned t3 = F->getRegInfo().createVirtualRegister(RC);
11978 unsigned t4 = F->getRegInfo().createVirtualRegister(RC);
11979 BuildMI(newMBB, dl, TII->get(X86::PHI), dest1Oper.getReg())
11980 .addReg(t1).addMBB(thisMBB).addReg(t3).addMBB(newMBB);
11981 BuildMI(newMBB, dl, TII->get(X86::PHI), dest2Oper.getReg())
11982 .addReg(t2).addMBB(thisMBB).addReg(t4).addMBB(newMBB);
11984 // The subsequent operations should be using the destination registers of
11985 // the PHI instructions.
11986 t1 = dest1Oper.getReg();
11987 t2 = dest2Oper.getReg();
11989 int valArgIndx = lastAddrIndx + 1;
11990 assert((argOpers[valArgIndx]->isReg() ||
11991 argOpers[valArgIndx]->isImm()) &&
11992 "invalid operand");
11993 unsigned t5 = F->getRegInfo().createVirtualRegister(RC);
11994 unsigned t6 = F->getRegInfo().createVirtualRegister(RC);
11995 if (argOpers[valArgIndx]->isReg())
11996 MIB = BuildMI(newMBB, dl, TII->get(regOpcL), t5);
11998 MIB = BuildMI(newMBB, dl, TII->get(immOpcL), t5);
11999 if (regOpcL != X86::MOV32rr)
12001 (*MIB).addOperand(*argOpers[valArgIndx]);
12002 assert(argOpers[valArgIndx + 1]->isReg() ==
12003 argOpers[valArgIndx]->isReg());
12004 assert(argOpers[valArgIndx + 1]->isImm() ==
12005 argOpers[valArgIndx]->isImm());
12006 if (argOpers[valArgIndx + 1]->isReg())
12007 MIB = BuildMI(newMBB, dl, TII->get(regOpcH), t6);
12009 MIB = BuildMI(newMBB, dl, TII->get(immOpcH), t6);
12010 if (regOpcH != X86::MOV32rr)
12012 (*MIB).addOperand(*argOpers[valArgIndx + 1]);
12016 t7 = F->getRegInfo().createVirtualRegister(RC);
12017 t8 = F->getRegInfo().createVirtualRegister(RC);
12018 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), t7).addReg(t5);
12019 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), t8).addReg(t6);
12025 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EAX);
12027 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EDX);
12030 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EBX);
12032 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::ECX);
12035 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG8B));
12036 for (int i=0; i <= lastAddrIndx; ++i)
12037 (*MIB).addOperand(*argOpers[i]);
12039 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand");
12040 (*MIB).setMemRefs(bInstr->memoperands_begin(),
12041 bInstr->memoperands_end());
12043 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t3);
12044 MIB.addReg(X86::EAX);
12045 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t4);
12046 MIB.addReg(X86::EDX);
12049 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB);
12051 bInstr->eraseFromParent(); // The pseudo instruction is gone now.
12055 // private utility function
12056 MachineBasicBlock *
12057 X86TargetLowering::EmitAtomicMinMaxWithCustomInserter(MachineInstr *mInstr,
12058 MachineBasicBlock *MBB,
12059 unsigned cmovOpc) const {
12060 // For the atomic min/max operator, we generate
12063 // ld t1 = [min/max.addr]
12064 // mov t2 = [min/max.val]
12066 // cmov[cond] t2 = t1
12068 // lcs dest = [bitinstr.addr], t2 [EAX is implicit]
12070 // fallthrough -->nextMBB
12072 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
12073 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
12074 MachineFunction::iterator MBBIter = MBB;
12077 /// First build the CFG
12078 MachineFunction *F = MBB->getParent();
12079 MachineBasicBlock *thisMBB = MBB;
12080 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
12081 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
12082 F->insert(MBBIter, newMBB);
12083 F->insert(MBBIter, nextMBB);
12085 // Transfer the remainder of thisMBB and its successor edges to nextMBB.
12086 nextMBB->splice(nextMBB->begin(), thisMBB,
12087 llvm::next(MachineBasicBlock::iterator(mInstr)),
12089 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
12091 // Update thisMBB to fall through to newMBB
12092 thisMBB->addSuccessor(newMBB);
12094 // newMBB jumps to newMBB and fall through to nextMBB
12095 newMBB->addSuccessor(nextMBB);
12096 newMBB->addSuccessor(newMBB);
12098 DebugLoc dl = mInstr->getDebugLoc();
12099 // Insert instructions into newMBB based on incoming instruction
12100 assert(mInstr->getNumOperands() < X86::AddrNumOperands + 4 &&
12101 "unexpected number of operands");
12102 MachineOperand& destOper = mInstr->getOperand(0);
12103 MachineOperand* argOpers[2 + X86::AddrNumOperands];
12104 int numArgs = mInstr->getNumOperands() - 1;
12105 for (int i=0; i < numArgs; ++i)
12106 argOpers[i] = &mInstr->getOperand(i+1);
12108 // x86 address has 4 operands: base, index, scale, and displacement
12109 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3]
12110 int valArgIndx = lastAddrIndx + 1;
12112 unsigned t1 = F->getRegInfo().createVirtualRegister(&X86::GR32RegClass);
12113 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rm), t1);
12114 for (int i=0; i <= lastAddrIndx; ++i)
12115 (*MIB).addOperand(*argOpers[i]);
12117 // We only support register and immediate values
12118 assert((argOpers[valArgIndx]->isReg() ||
12119 argOpers[valArgIndx]->isImm()) &&
12120 "invalid operand");
12122 unsigned t2 = F->getRegInfo().createVirtualRegister(&X86::GR32RegClass);
12123 if (argOpers[valArgIndx]->isReg())
12124 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t2);
12126 MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), t2);
12127 (*MIB).addOperand(*argOpers[valArgIndx]);
12129 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EAX);
12132 MIB = BuildMI(newMBB, dl, TII->get(X86::CMP32rr));
12137 unsigned t3 = F->getRegInfo().createVirtualRegister(&X86::GR32RegClass);
12138 MIB = BuildMI(newMBB, dl, TII->get(cmovOpc),t3);
12142 // Cmp and exchange if none has modified the memory location
12143 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG32));
12144 for (int i=0; i <= lastAddrIndx; ++i)
12145 (*MIB).addOperand(*argOpers[i]);
12147 assert(mInstr->hasOneMemOperand() && "Unexpected number of memoperand");
12148 (*MIB).setMemRefs(mInstr->memoperands_begin(),
12149 mInstr->memoperands_end());
12151 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), destOper.getReg());
12152 MIB.addReg(X86::EAX);
12155 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB);
12157 mInstr->eraseFromParent(); // The pseudo instruction is gone now.
12161 // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
12162 // or XMM0_V32I8 in AVX all of this code can be replaced with that
12163 // in the .td file.
12164 MachineBasicBlock *
12165 X86TargetLowering::EmitPCMP(MachineInstr *MI, MachineBasicBlock *BB,
12166 unsigned numArgs, bool memArg) const {
12167 assert(Subtarget->hasSSE42() &&
12168 "Target must have SSE4.2 or AVX features enabled");
12170 DebugLoc dl = MI->getDebugLoc();
12171 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
12173 if (!Subtarget->hasAVX()) {
12175 Opc = numArgs == 3 ? X86::PCMPISTRM128rm : X86::PCMPESTRM128rm;
12177 Opc = numArgs == 3 ? X86::PCMPISTRM128rr : X86::PCMPESTRM128rr;
12180 Opc = numArgs == 3 ? X86::VPCMPISTRM128rm : X86::VPCMPESTRM128rm;
12182 Opc = numArgs == 3 ? X86::VPCMPISTRM128rr : X86::VPCMPESTRM128rr;
12185 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
12186 for (unsigned i = 0; i < numArgs; ++i) {
12187 MachineOperand &Op = MI->getOperand(i+1);
12188 if (!(Op.isReg() && Op.isImplicit()))
12189 MIB.addOperand(Op);
12191 BuildMI(*BB, MI, dl,
12192 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
12193 .addReg(X86::XMM0);
12195 MI->eraseFromParent();
12199 MachineBasicBlock *
12200 X86TargetLowering::EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB) const {
12201 DebugLoc dl = MI->getDebugLoc();
12202 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
12204 // Address into RAX/EAX, other two args into ECX, EDX.
12205 unsigned MemOpc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
12206 unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
12207 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg);
12208 for (int i = 0; i < X86::AddrNumOperands; ++i)
12209 MIB.addOperand(MI->getOperand(i));
12211 unsigned ValOps = X86::AddrNumOperands;
12212 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
12213 .addReg(MI->getOperand(ValOps).getReg());
12214 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EDX)
12215 .addReg(MI->getOperand(ValOps+1).getReg());
12217 // The instruction doesn't actually take any operands though.
12218 BuildMI(*BB, MI, dl, TII->get(X86::MONITORrrr));
12220 MI->eraseFromParent(); // The pseudo is gone now.
12224 MachineBasicBlock *
12225 X86TargetLowering::EmitVAARG64WithCustomInserter(
12227 MachineBasicBlock *MBB) const {
12228 // Emit va_arg instruction on X86-64.
12230 // Operands to this pseudo-instruction:
12231 // 0 ) Output : destination address (reg)
12232 // 1-5) Input : va_list address (addr, i64mem)
12233 // 6 ) ArgSize : Size (in bytes) of vararg type
12234 // 7 ) ArgMode : 0=overflow only, 1=use gp_offset, 2=use fp_offset
12235 // 8 ) Align : Alignment of type
12236 // 9 ) EFLAGS (implicit-def)
12238 assert(MI->getNumOperands() == 10 && "VAARG_64 should have 10 operands!");
12239 assert(X86::AddrNumOperands == 5 && "VAARG_64 assumes 5 address operands");
12241 unsigned DestReg = MI->getOperand(0).getReg();
12242 MachineOperand &Base = MI->getOperand(1);
12243 MachineOperand &Scale = MI->getOperand(2);
12244 MachineOperand &Index = MI->getOperand(3);
12245 MachineOperand &Disp = MI->getOperand(4);
12246 MachineOperand &Segment = MI->getOperand(5);
12247 unsigned ArgSize = MI->getOperand(6).getImm();
12248 unsigned ArgMode = MI->getOperand(7).getImm();
12249 unsigned Align = MI->getOperand(8).getImm();
12251 // Memory Reference
12252 assert(MI->hasOneMemOperand() && "Expected VAARG_64 to have one memoperand");
12253 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
12254 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
12256 // Machine Information
12257 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
12258 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
12259 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64);
12260 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32);
12261 DebugLoc DL = MI->getDebugLoc();
12263 // struct va_list {
12266 // i64 overflow_area (address)
12267 // i64 reg_save_area (address)
12269 // sizeof(va_list) = 24
12270 // alignment(va_list) = 8
12272 unsigned TotalNumIntRegs = 6;
12273 unsigned TotalNumXMMRegs = 8;
12274 bool UseGPOffset = (ArgMode == 1);
12275 bool UseFPOffset = (ArgMode == 2);
12276 unsigned MaxOffset = TotalNumIntRegs * 8 +
12277 (UseFPOffset ? TotalNumXMMRegs * 16 : 0);
12279 /* Align ArgSize to a multiple of 8 */
12280 unsigned ArgSizeA8 = (ArgSize + 7) & ~7;
12281 bool NeedsAlign = (Align > 8);
12283 MachineBasicBlock *thisMBB = MBB;
12284 MachineBasicBlock *overflowMBB;
12285 MachineBasicBlock *offsetMBB;
12286 MachineBasicBlock *endMBB;
12288 unsigned OffsetDestReg = 0; // Argument address computed by offsetMBB
12289 unsigned OverflowDestReg = 0; // Argument address computed by overflowMBB
12290 unsigned OffsetReg = 0;
12292 if (!UseGPOffset && !UseFPOffset) {
12293 // If we only pull from the overflow region, we don't create a branch.
12294 // We don't need to alter control flow.
12295 OffsetDestReg = 0; // unused
12296 OverflowDestReg = DestReg;
12299 overflowMBB = thisMBB;
12302 // First emit code to check if gp_offset (or fp_offset) is below the bound.
12303 // If so, pull the argument from reg_save_area. (branch to offsetMBB)
12304 // If not, pull from overflow_area. (branch to overflowMBB)
12309 // offsetMBB overflowMBB
12314 // Registers for the PHI in endMBB
12315 OffsetDestReg = MRI.createVirtualRegister(AddrRegClass);
12316 OverflowDestReg = MRI.createVirtualRegister(AddrRegClass);
12318 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
12319 MachineFunction *MF = MBB->getParent();
12320 overflowMBB = MF->CreateMachineBasicBlock(LLVM_BB);
12321 offsetMBB = MF->CreateMachineBasicBlock(LLVM_BB);
12322 endMBB = MF->CreateMachineBasicBlock(LLVM_BB);
12324 MachineFunction::iterator MBBIter = MBB;
12327 // Insert the new basic blocks
12328 MF->insert(MBBIter, offsetMBB);
12329 MF->insert(MBBIter, overflowMBB);
12330 MF->insert(MBBIter, endMBB);
12332 // Transfer the remainder of MBB and its successor edges to endMBB.
12333 endMBB->splice(endMBB->begin(), thisMBB,
12334 llvm::next(MachineBasicBlock::iterator(MI)),
12336 endMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
12338 // Make offsetMBB and overflowMBB successors of thisMBB
12339 thisMBB->addSuccessor(offsetMBB);
12340 thisMBB->addSuccessor(overflowMBB);
12342 // endMBB is a successor of both offsetMBB and overflowMBB
12343 offsetMBB->addSuccessor(endMBB);
12344 overflowMBB->addSuccessor(endMBB);
12346 // Load the offset value into a register
12347 OffsetReg = MRI.createVirtualRegister(OffsetRegClass);
12348 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg)
12352 .addDisp(Disp, UseFPOffset ? 4 : 0)
12353 .addOperand(Segment)
12354 .setMemRefs(MMOBegin, MMOEnd);
12356 // Check if there is enough room left to pull this argument.
12357 BuildMI(thisMBB, DL, TII->get(X86::CMP32ri))
12359 .addImm(MaxOffset + 8 - ArgSizeA8);
12361 // Branch to "overflowMBB" if offset >= max
12362 // Fall through to "offsetMBB" otherwise
12363 BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE)))
12364 .addMBB(overflowMBB);
12367 // In offsetMBB, emit code to use the reg_save_area.
12369 assert(OffsetReg != 0);
12371 // Read the reg_save_area address.
12372 unsigned RegSaveReg = MRI.createVirtualRegister(AddrRegClass);
12373 BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg)
12378 .addOperand(Segment)
12379 .setMemRefs(MMOBegin, MMOEnd);
12381 // Zero-extend the offset
12382 unsigned OffsetReg64 = MRI.createVirtualRegister(AddrRegClass);
12383 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64)
12386 .addImm(X86::sub_32bit);
12388 // Add the offset to the reg_save_area to get the final address.
12389 BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg)
12390 .addReg(OffsetReg64)
12391 .addReg(RegSaveReg);
12393 // Compute the offset for the next argument
12394 unsigned NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass);
12395 BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg)
12397 .addImm(UseFPOffset ? 16 : 8);
12399 // Store it back into the va_list.
12400 BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr))
12404 .addDisp(Disp, UseFPOffset ? 4 : 0)
12405 .addOperand(Segment)
12406 .addReg(NextOffsetReg)
12407 .setMemRefs(MMOBegin, MMOEnd);
12410 BuildMI(offsetMBB, DL, TII->get(X86::JMP_4))
12415 // Emit code to use overflow area
12418 // Load the overflow_area address into a register.
12419 unsigned OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass);
12420 BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg)
12425 .addOperand(Segment)
12426 .setMemRefs(MMOBegin, MMOEnd);
12428 // If we need to align it, do so. Otherwise, just copy the address
12429 // to OverflowDestReg.
12431 // Align the overflow address
12432 assert((Align & (Align-1)) == 0 && "Alignment must be a power of 2");
12433 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass);
12435 // aligned_addr = (addr + (align-1)) & ~(align-1)
12436 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg)
12437 .addReg(OverflowAddrReg)
12440 BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg)
12442 .addImm(~(uint64_t)(Align-1));
12444 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg)
12445 .addReg(OverflowAddrReg);
12448 // Compute the next overflow address after this argument.
12449 // (the overflow address should be kept 8-byte aligned)
12450 unsigned NextAddrReg = MRI.createVirtualRegister(AddrRegClass);
12451 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg)
12452 .addReg(OverflowDestReg)
12453 .addImm(ArgSizeA8);
12455 // Store the new overflow address.
12456 BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr))
12461 .addOperand(Segment)
12462 .addReg(NextAddrReg)
12463 .setMemRefs(MMOBegin, MMOEnd);
12465 // If we branched, emit the PHI to the front of endMBB.
12467 BuildMI(*endMBB, endMBB->begin(), DL,
12468 TII->get(X86::PHI), DestReg)
12469 .addReg(OffsetDestReg).addMBB(offsetMBB)
12470 .addReg(OverflowDestReg).addMBB(overflowMBB);
12473 // Erase the pseudo instruction
12474 MI->eraseFromParent();
12479 MachineBasicBlock *
12480 X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
12482 MachineBasicBlock *MBB) const {
12483 // Emit code to save XMM registers to the stack. The ABI says that the
12484 // number of registers to save is given in %al, so it's theoretically
12485 // possible to do an indirect jump trick to avoid saving all of them,
12486 // however this code takes a simpler approach and just executes all
12487 // of the stores if %al is non-zero. It's less code, and it's probably
12488 // easier on the hardware branch predictor, and stores aren't all that
12489 // expensive anyway.
12491 // Create the new basic blocks. One block contains all the XMM stores,
12492 // and one block is the final destination regardless of whether any
12493 // stores were performed.
12494 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
12495 MachineFunction *F = MBB->getParent();
12496 MachineFunction::iterator MBBIter = MBB;
12498 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB);
12499 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB);
12500 F->insert(MBBIter, XMMSaveMBB);
12501 F->insert(MBBIter, EndMBB);
12503 // Transfer the remainder of MBB and its successor edges to EndMBB.
12504 EndMBB->splice(EndMBB->begin(), MBB,
12505 llvm::next(MachineBasicBlock::iterator(MI)),
12507 EndMBB->transferSuccessorsAndUpdatePHIs(MBB);
12509 // The original block will now fall through to the XMM save block.
12510 MBB->addSuccessor(XMMSaveMBB);
12511 // The XMMSaveMBB will fall through to the end block.
12512 XMMSaveMBB->addSuccessor(EndMBB);
12514 // Now add the instructions.
12515 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
12516 DebugLoc DL = MI->getDebugLoc();
12518 unsigned CountReg = MI->getOperand(0).getReg();
12519 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm();
12520 int64_t VarArgsFPOffset = MI->getOperand(2).getImm();
12522 if (!Subtarget->isTargetWin64()) {
12523 // If %al is 0, branch around the XMM save block.
12524 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
12525 BuildMI(MBB, DL, TII->get(X86::JE_4)).addMBB(EndMBB);
12526 MBB->addSuccessor(EndMBB);
12529 unsigned MOVOpc = Subtarget->hasAVX() ? X86::VMOVAPSmr : X86::MOVAPSmr;
12530 // In the XMM save block, save all the XMM argument registers.
12531 for (int i = 3, e = MI->getNumOperands(); i != e; ++i) {
12532 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
12533 MachineMemOperand *MMO =
12534 F->getMachineMemOperand(
12535 MachinePointerInfo::getFixedStack(RegSaveFrameIndex, Offset),
12536 MachineMemOperand::MOStore,
12537 /*Size=*/16, /*Align=*/16);
12538 BuildMI(XMMSaveMBB, DL, TII->get(MOVOpc))
12539 .addFrameIndex(RegSaveFrameIndex)
12540 .addImm(/*Scale=*/1)
12541 .addReg(/*IndexReg=*/0)
12542 .addImm(/*Disp=*/Offset)
12543 .addReg(/*Segment=*/0)
12544 .addReg(MI->getOperand(i).getReg())
12545 .addMemOperand(MMO);
12548 MI->eraseFromParent(); // The pseudo instruction is gone now.
12553 // The EFLAGS operand of SelectItr might be missing a kill marker
12554 // because there were multiple uses of EFLAGS, and ISel didn't know
12555 // which to mark. Figure out whether SelectItr should have had a
12556 // kill marker, and set it if it should. Returns the correct kill
12558 static bool checkAndUpdateEFLAGSKill(MachineBasicBlock::iterator SelectItr,
12559 MachineBasicBlock* BB,
12560 const TargetRegisterInfo* TRI) {
12561 // Scan forward through BB for a use/def of EFLAGS.
12562 MachineBasicBlock::iterator miI(llvm::next(SelectItr));
12563 for (MachineBasicBlock::iterator miE = BB->end(); miI != miE; ++miI) {
12564 const MachineInstr& mi = *miI;
12565 if (mi.readsRegister(X86::EFLAGS))
12567 if (mi.definesRegister(X86::EFLAGS))
12568 break; // Should have kill-flag - update below.
12571 // If we hit the end of the block, check whether EFLAGS is live into a
12573 if (miI == BB->end()) {
12574 for (MachineBasicBlock::succ_iterator sItr = BB->succ_begin(),
12575 sEnd = BB->succ_end();
12576 sItr != sEnd; ++sItr) {
12577 MachineBasicBlock* succ = *sItr;
12578 if (succ->isLiveIn(X86::EFLAGS))
12583 // We found a def, or hit the end of the basic block and EFLAGS wasn't live
12584 // out. SelectMI should have a kill flag on EFLAGS.
12585 SelectItr->addRegisterKilled(X86::EFLAGS, TRI);
12589 MachineBasicBlock *
12590 X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
12591 MachineBasicBlock *BB) const {
12592 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
12593 DebugLoc DL = MI->getDebugLoc();
12595 // To "insert" a SELECT_CC instruction, we actually have to insert the
12596 // diamond control-flow pattern. The incoming instruction knows the
12597 // destination vreg to set, the condition code register to branch on, the
12598 // true/false values to select between, and a branch opcode to use.
12599 const BasicBlock *LLVM_BB = BB->getBasicBlock();
12600 MachineFunction::iterator It = BB;
12606 // cmpTY ccX, r1, r2
12608 // fallthrough --> copy0MBB
12609 MachineBasicBlock *thisMBB = BB;
12610 MachineFunction *F = BB->getParent();
12611 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
12612 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
12613 F->insert(It, copy0MBB);
12614 F->insert(It, sinkMBB);
12616 // If the EFLAGS register isn't dead in the terminator, then claim that it's
12617 // live into the sink and copy blocks.
12618 const TargetRegisterInfo* TRI = getTargetMachine().getRegisterInfo();
12619 if (!MI->killsRegister(X86::EFLAGS) &&
12620 !checkAndUpdateEFLAGSKill(MI, BB, TRI)) {
12621 copy0MBB->addLiveIn(X86::EFLAGS);
12622 sinkMBB->addLiveIn(X86::EFLAGS);
12625 // Transfer the remainder of BB and its successor edges to sinkMBB.
12626 sinkMBB->splice(sinkMBB->begin(), BB,
12627 llvm::next(MachineBasicBlock::iterator(MI)),
12629 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
12631 // Add the true and fallthrough blocks as its successors.
12632 BB->addSuccessor(copy0MBB);
12633 BB->addSuccessor(sinkMBB);
12635 // Create the conditional branch instruction.
12637 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
12638 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
12641 // %FalseValue = ...
12642 // # fallthrough to sinkMBB
12643 copy0MBB->addSuccessor(sinkMBB);
12646 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
12648 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
12649 TII->get(X86::PHI), MI->getOperand(0).getReg())
12650 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
12651 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
12653 MI->eraseFromParent(); // The pseudo instruction is gone now.
12657 MachineBasicBlock *
12658 X86TargetLowering::EmitLoweredSegAlloca(MachineInstr *MI, MachineBasicBlock *BB,
12659 bool Is64Bit) const {
12660 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
12661 DebugLoc DL = MI->getDebugLoc();
12662 MachineFunction *MF = BB->getParent();
12663 const BasicBlock *LLVM_BB = BB->getBasicBlock();
12665 assert(getTargetMachine().Options.EnableSegmentedStacks);
12667 unsigned TlsReg = Is64Bit ? X86::FS : X86::GS;
12668 unsigned TlsOffset = Is64Bit ? 0x70 : 0x30;
12671 // ... [Till the alloca]
12672 // If stacklet is not large enough, jump to mallocMBB
12675 // Allocate by subtracting from RSP
12676 // Jump to continueMBB
12679 // Allocate by call to runtime
12683 // [rest of original BB]
12686 MachineBasicBlock *mallocMBB = MF->CreateMachineBasicBlock(LLVM_BB);
12687 MachineBasicBlock *bumpMBB = MF->CreateMachineBasicBlock(LLVM_BB);
12688 MachineBasicBlock *continueMBB = MF->CreateMachineBasicBlock(LLVM_BB);
12690 MachineRegisterInfo &MRI = MF->getRegInfo();
12691 const TargetRegisterClass *AddrRegClass =
12692 getRegClassFor(Is64Bit ? MVT::i64:MVT::i32);
12694 unsigned mallocPtrVReg = MRI.createVirtualRegister(AddrRegClass),
12695 bumpSPPtrVReg = MRI.createVirtualRegister(AddrRegClass),
12696 tmpSPVReg = MRI.createVirtualRegister(AddrRegClass),
12697 SPLimitVReg = MRI.createVirtualRegister(AddrRegClass),
12698 sizeVReg = MI->getOperand(1).getReg(),
12699 physSPReg = Is64Bit ? X86::RSP : X86::ESP;
12701 MachineFunction::iterator MBBIter = BB;
12704 MF->insert(MBBIter, bumpMBB);
12705 MF->insert(MBBIter, mallocMBB);
12706 MF->insert(MBBIter, continueMBB);
12708 continueMBB->splice(continueMBB->begin(), BB, llvm::next
12709 (MachineBasicBlock::iterator(MI)), BB->end());
12710 continueMBB->transferSuccessorsAndUpdatePHIs(BB);
12712 // Add code to the main basic block to check if the stack limit has been hit,
12713 // and if so, jump to mallocMBB otherwise to bumpMBB.
12714 BuildMI(BB, DL, TII->get(TargetOpcode::COPY), tmpSPVReg).addReg(physSPReg);
12715 BuildMI(BB, DL, TII->get(Is64Bit ? X86::SUB64rr:X86::SUB32rr), SPLimitVReg)
12716 .addReg(tmpSPVReg).addReg(sizeVReg);
12717 BuildMI(BB, DL, TII->get(Is64Bit ? X86::CMP64mr:X86::CMP32mr))
12718 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg)
12719 .addReg(SPLimitVReg);
12720 BuildMI(BB, DL, TII->get(X86::JG_4)).addMBB(mallocMBB);
12722 // bumpMBB simply decreases the stack pointer, since we know the current
12723 // stacklet has enough space.
12724 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), physSPReg)
12725 .addReg(SPLimitVReg);
12726 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), bumpSPPtrVReg)
12727 .addReg(SPLimitVReg);
12728 BuildMI(bumpMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
12730 // Calls into a routine in libgcc to allocate more space from the heap.
12731 const uint32_t *RegMask =
12732 getTargetMachine().getRegisterInfo()->getCallPreservedMask(CallingConv::C);
12734 BuildMI(mallocMBB, DL, TII->get(X86::MOV64rr), X86::RDI)
12736 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
12737 .addExternalSymbol("__morestack_allocate_stack_space")
12738 .addRegMask(RegMask)
12739 .addReg(X86::RDI, RegState::Implicit)
12740 .addReg(X86::RAX, RegState::ImplicitDefine);
12742 BuildMI(mallocMBB, DL, TII->get(X86::SUB32ri), physSPReg).addReg(physSPReg)
12744 BuildMI(mallocMBB, DL, TII->get(X86::PUSH32r)).addReg(sizeVReg);
12745 BuildMI(mallocMBB, DL, TII->get(X86::CALLpcrel32))
12746 .addExternalSymbol("__morestack_allocate_stack_space")
12747 .addRegMask(RegMask)
12748 .addReg(X86::EAX, RegState::ImplicitDefine);
12752 BuildMI(mallocMBB, DL, TII->get(X86::ADD32ri), physSPReg).addReg(physSPReg)
12755 BuildMI(mallocMBB, DL, TII->get(TargetOpcode::COPY), mallocPtrVReg)
12756 .addReg(Is64Bit ? X86::RAX : X86::EAX);
12757 BuildMI(mallocMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
12759 // Set up the CFG correctly.
12760 BB->addSuccessor(bumpMBB);
12761 BB->addSuccessor(mallocMBB);
12762 mallocMBB->addSuccessor(continueMBB);
12763 bumpMBB->addSuccessor(continueMBB);
12765 // Take care of the PHI nodes.
12766 BuildMI(*continueMBB, continueMBB->begin(), DL, TII->get(X86::PHI),
12767 MI->getOperand(0).getReg())
12768 .addReg(mallocPtrVReg).addMBB(mallocMBB)
12769 .addReg(bumpSPPtrVReg).addMBB(bumpMBB);
12771 // Delete the original pseudo instruction.
12772 MI->eraseFromParent();
12775 return continueMBB;
12778 MachineBasicBlock *
12779 X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI,
12780 MachineBasicBlock *BB) const {
12781 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
12782 DebugLoc DL = MI->getDebugLoc();
12784 assert(!Subtarget->isTargetEnvMacho());
12786 // The lowering is pretty easy: we're just emitting the call to _alloca. The
12787 // non-trivial part is impdef of ESP.
12789 if (Subtarget->isTargetWin64()) {
12790 if (Subtarget->isTargetCygMing()) {
12791 // ___chkstk(Mingw64):
12792 // Clobbers R10, R11, RAX and EFLAGS.
12794 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
12795 .addExternalSymbol("___chkstk")
12796 .addReg(X86::RAX, RegState::Implicit)
12797 .addReg(X86::RSP, RegState::Implicit)
12798 .addReg(X86::RAX, RegState::Define | RegState::Implicit)
12799 .addReg(X86::RSP, RegState::Define | RegState::Implicit)
12800 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
12802 // __chkstk(MSVCRT): does not update stack pointer.
12803 // Clobbers R10, R11 and EFLAGS.
12804 // FIXME: RAX(allocated size) might be reused and not killed.
12805 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
12806 .addExternalSymbol("__chkstk")
12807 .addReg(X86::RAX, RegState::Implicit)
12808 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
12809 // RAX has the offset to subtracted from RSP.
12810 BuildMI(*BB, MI, DL, TII->get(X86::SUB64rr), X86::RSP)
12815 const char *StackProbeSymbol =
12816 Subtarget->isTargetWindows() ? "_chkstk" : "_alloca";
12818 BuildMI(*BB, MI, DL, TII->get(X86::CALLpcrel32))
12819 .addExternalSymbol(StackProbeSymbol)
12820 .addReg(X86::EAX, RegState::Implicit)
12821 .addReg(X86::ESP, RegState::Implicit)
12822 .addReg(X86::EAX, RegState::Define | RegState::Implicit)
12823 .addReg(X86::ESP, RegState::Define | RegState::Implicit)
12824 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
12827 MI->eraseFromParent(); // The pseudo instruction is gone now.
12831 MachineBasicBlock *
12832 X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI,
12833 MachineBasicBlock *BB) const {
12834 // This is pretty easy. We're taking the value that we received from
12835 // our load from the relocation, sticking it in either RDI (x86-64)
12836 // or EAX and doing an indirect call. The return value will then
12837 // be in the normal return register.
12838 const X86InstrInfo *TII
12839 = static_cast<const X86InstrInfo*>(getTargetMachine().getInstrInfo());
12840 DebugLoc DL = MI->getDebugLoc();
12841 MachineFunction *F = BB->getParent();
12843 assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?");
12844 assert(MI->getOperand(3).isGlobal() && "This should be a global");
12846 // Get a register mask for the lowered call.
12847 // FIXME: The 32-bit calls have non-standard calling conventions. Use a
12848 // proper register mask.
12849 const uint32_t *RegMask =
12850 getTargetMachine().getRegisterInfo()->getCallPreservedMask(CallingConv::C);
12851 if (Subtarget->is64Bit()) {
12852 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
12853 TII->get(X86::MOV64rm), X86::RDI)
12855 .addImm(0).addReg(0)
12856 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
12857 MI->getOperand(3).getTargetFlags())
12859 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m));
12860 addDirectMem(MIB, X86::RDI);
12861 MIB.addReg(X86::RAX, RegState::ImplicitDefine).addRegMask(RegMask);
12862 } else if (getTargetMachine().getRelocationModel() != Reloc::PIC_) {
12863 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
12864 TII->get(X86::MOV32rm), X86::EAX)
12866 .addImm(0).addReg(0)
12867 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
12868 MI->getOperand(3).getTargetFlags())
12870 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
12871 addDirectMem(MIB, X86::EAX);
12872 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
12874 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
12875 TII->get(X86::MOV32rm), X86::EAX)
12876 .addReg(TII->getGlobalBaseReg(F))
12877 .addImm(0).addReg(0)
12878 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
12879 MI->getOperand(3).getTargetFlags())
12881 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
12882 addDirectMem(MIB, X86::EAX);
12883 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
12886 MI->eraseFromParent(); // The pseudo instruction is gone now.
12890 MachineBasicBlock *
12891 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
12892 MachineBasicBlock *BB) const {
12893 switch (MI->getOpcode()) {
12894 default: llvm_unreachable("Unexpected instr type to insert");
12895 case X86::TAILJMPd64:
12896 case X86::TAILJMPr64:
12897 case X86::TAILJMPm64:
12898 llvm_unreachable("TAILJMP64 would not be touched here.");
12899 case X86::TCRETURNdi64:
12900 case X86::TCRETURNri64:
12901 case X86::TCRETURNmi64:
12903 case X86::WIN_ALLOCA:
12904 return EmitLoweredWinAlloca(MI, BB);
12905 case X86::SEG_ALLOCA_32:
12906 return EmitLoweredSegAlloca(MI, BB, false);
12907 case X86::SEG_ALLOCA_64:
12908 return EmitLoweredSegAlloca(MI, BB, true);
12909 case X86::TLSCall_32:
12910 case X86::TLSCall_64:
12911 return EmitLoweredTLSCall(MI, BB);
12912 case X86::CMOV_GR8:
12913 case X86::CMOV_FR32:
12914 case X86::CMOV_FR64:
12915 case X86::CMOV_V4F32:
12916 case X86::CMOV_V2F64:
12917 case X86::CMOV_V2I64:
12918 case X86::CMOV_V8F32:
12919 case X86::CMOV_V4F64:
12920 case X86::CMOV_V4I64:
12921 case X86::CMOV_GR16:
12922 case X86::CMOV_GR32:
12923 case X86::CMOV_RFP32:
12924 case X86::CMOV_RFP64:
12925 case X86::CMOV_RFP80:
12926 return EmitLoweredSelect(MI, BB);
12928 case X86::FP32_TO_INT16_IN_MEM:
12929 case X86::FP32_TO_INT32_IN_MEM:
12930 case X86::FP32_TO_INT64_IN_MEM:
12931 case X86::FP64_TO_INT16_IN_MEM:
12932 case X86::FP64_TO_INT32_IN_MEM:
12933 case X86::FP64_TO_INT64_IN_MEM:
12934 case X86::FP80_TO_INT16_IN_MEM:
12935 case X86::FP80_TO_INT32_IN_MEM:
12936 case X86::FP80_TO_INT64_IN_MEM: {
12937 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
12938 DebugLoc DL = MI->getDebugLoc();
12940 // Change the floating point control register to use "round towards zero"
12941 // mode when truncating to an integer value.
12942 MachineFunction *F = BB->getParent();
12943 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false);
12944 addFrameReference(BuildMI(*BB, MI, DL,
12945 TII->get(X86::FNSTCW16m)), CWFrameIdx);
12947 // Load the old value of the high byte of the control word...
12949 F->getRegInfo().createVirtualRegister(&X86::GR16RegClass);
12950 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW),
12953 // Set the high part to be round to zero...
12954 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
12957 // Reload the modified control word now...
12958 addFrameReference(BuildMI(*BB, MI, DL,
12959 TII->get(X86::FLDCW16m)), CWFrameIdx);
12961 // Restore the memory image of control word to original value
12962 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
12965 // Get the X86 opcode to use.
12967 switch (MI->getOpcode()) {
12968 default: llvm_unreachable("illegal opcode!");
12969 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
12970 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
12971 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
12972 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
12973 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
12974 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
12975 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
12976 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
12977 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
12981 MachineOperand &Op = MI->getOperand(0);
12983 AM.BaseType = X86AddressMode::RegBase;
12984 AM.Base.Reg = Op.getReg();
12986 AM.BaseType = X86AddressMode::FrameIndexBase;
12987 AM.Base.FrameIndex = Op.getIndex();
12989 Op = MI->getOperand(1);
12991 AM.Scale = Op.getImm();
12992 Op = MI->getOperand(2);
12994 AM.IndexReg = Op.getImm();
12995 Op = MI->getOperand(3);
12996 if (Op.isGlobal()) {
12997 AM.GV = Op.getGlobal();
12999 AM.Disp = Op.getImm();
13001 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM)
13002 .addReg(MI->getOperand(X86::AddrNumOperands).getReg());
13004 // Reload the original control word now.
13005 addFrameReference(BuildMI(*BB, MI, DL,
13006 TII->get(X86::FLDCW16m)), CWFrameIdx);
13008 MI->eraseFromParent(); // The pseudo instruction is gone now.
13011 // String/text processing lowering.
13012 case X86::PCMPISTRM128REG:
13013 case X86::VPCMPISTRM128REG:
13014 case X86::PCMPISTRM128MEM:
13015 case X86::VPCMPISTRM128MEM:
13016 case X86::PCMPESTRM128REG:
13017 case X86::VPCMPESTRM128REG:
13018 case X86::PCMPESTRM128MEM:
13019 case X86::VPCMPESTRM128MEM: {
13022 switch (MI->getOpcode()) {
13023 default: llvm_unreachable("illegal opcode!");
13024 case X86::PCMPISTRM128REG:
13025 case X86::VPCMPISTRM128REG:
13026 NumArgs = 3; MemArg = false; break;
13027 case X86::PCMPISTRM128MEM:
13028 case X86::VPCMPISTRM128MEM:
13029 NumArgs = 3; MemArg = true; break;
13030 case X86::PCMPESTRM128REG:
13031 case X86::VPCMPESTRM128REG:
13032 NumArgs = 5; MemArg = false; break;
13033 case X86::PCMPESTRM128MEM:
13034 case X86::VPCMPESTRM128MEM:
13035 NumArgs = 5; MemArg = true; break;
13037 return EmitPCMP(MI, BB, NumArgs, MemArg);
13040 // Thread synchronization.
13042 return EmitMonitor(MI, BB);
13044 // Atomic Lowering.
13045 case X86::ATOMMIN32:
13046 case X86::ATOMMAX32:
13047 case X86::ATOMUMIN32:
13048 case X86::ATOMUMAX32:
13049 case X86::ATOMMIN16:
13050 case X86::ATOMMAX16:
13051 case X86::ATOMUMIN16:
13052 case X86::ATOMUMAX16:
13053 case X86::ATOMMIN64:
13054 case X86::ATOMMAX64:
13055 case X86::ATOMUMIN64:
13056 case X86::ATOMUMAX64: {
13058 switch (MI->getOpcode()) {
13059 default: llvm_unreachable("illegal opcode!");
13060 case X86::ATOMMIN32: Opc = X86::CMOVL32rr; break;
13061 case X86::ATOMMAX32: Opc = X86::CMOVG32rr; break;
13062 case X86::ATOMUMIN32: Opc = X86::CMOVB32rr; break;
13063 case X86::ATOMUMAX32: Opc = X86::CMOVA32rr; break;
13064 case X86::ATOMMIN16: Opc = X86::CMOVL16rr; break;
13065 case X86::ATOMMAX16: Opc = X86::CMOVG16rr; break;
13066 case X86::ATOMUMIN16: Opc = X86::CMOVB16rr; break;
13067 case X86::ATOMUMAX16: Opc = X86::CMOVA16rr; break;
13068 case X86::ATOMMIN64: Opc = X86::CMOVL64rr; break;
13069 case X86::ATOMMAX64: Opc = X86::CMOVG64rr; break;
13070 case X86::ATOMUMIN64: Opc = X86::CMOVB64rr; break;
13071 case X86::ATOMUMAX64: Opc = X86::CMOVA64rr; break;
13072 // FIXME: There are no CMOV8 instructions; MIN/MAX need some other way.
13074 return EmitAtomicMinMaxWithCustomInserter(MI, BB, Opc);
13077 case X86::ATOMAND32:
13078 case X86::ATOMOR32:
13079 case X86::ATOMXOR32:
13080 case X86::ATOMNAND32: {
13081 bool Invert = false;
13082 unsigned RegOpc, ImmOpc;
13083 switch (MI->getOpcode()) {
13084 default: llvm_unreachable("illegal opcode!");
13085 case X86::ATOMAND32:
13086 RegOpc = X86::AND32rr; ImmOpc = X86::AND32ri; break;
13087 case X86::ATOMOR32:
13088 RegOpc = X86::OR32rr; ImmOpc = X86::OR32ri; break;
13089 case X86::ATOMXOR32:
13090 RegOpc = X86::XOR32rr; ImmOpc = X86::XOR32ri; break;
13091 case X86::ATOMNAND32:
13092 RegOpc = X86::AND32rr; ImmOpc = X86::AND32ri; Invert = true; break;
13094 return EmitAtomicBitwiseWithCustomInserter(MI, BB, RegOpc, ImmOpc,
13095 X86::MOV32rm, X86::LCMPXCHG32,
13096 X86::NOT32r, X86::EAX,
13097 &X86::GR32RegClass, Invert);
13100 case X86::ATOMAND16:
13101 case X86::ATOMOR16:
13102 case X86::ATOMXOR16:
13103 case X86::ATOMNAND16: {
13104 bool Invert = false;
13105 unsigned RegOpc, ImmOpc;
13106 switch (MI->getOpcode()) {
13107 default: llvm_unreachable("illegal opcode!");
13108 case X86::ATOMAND16:
13109 RegOpc = X86::AND16rr; ImmOpc = X86::AND16ri; break;
13110 case X86::ATOMOR16:
13111 RegOpc = X86::OR16rr; ImmOpc = X86::OR16ri; break;
13112 case X86::ATOMXOR16:
13113 RegOpc = X86::XOR16rr; ImmOpc = X86::XOR16ri; break;
13114 case X86::ATOMNAND16:
13115 RegOpc = X86::AND16rr; ImmOpc = X86::AND16ri; Invert = true; break;
13117 return EmitAtomicBitwiseWithCustomInserter(MI, BB, RegOpc, ImmOpc,
13118 X86::MOV16rm, X86::LCMPXCHG16,
13119 X86::NOT16r, X86::AX,
13120 &X86::GR16RegClass, Invert);
13123 case X86::ATOMAND8:
13125 case X86::ATOMXOR8:
13126 case X86::ATOMNAND8: {
13127 bool Invert = false;
13128 unsigned RegOpc, ImmOpc;
13129 switch (MI->getOpcode()) {
13130 default: llvm_unreachable("illegal opcode!");
13131 case X86::ATOMAND8:
13132 RegOpc = X86::AND8rr; ImmOpc = X86::AND8ri; break;
13134 RegOpc = X86::OR8rr; ImmOpc = X86::OR8ri; break;
13135 case X86::ATOMXOR8:
13136 RegOpc = X86::XOR8rr; ImmOpc = X86::XOR8ri; break;
13137 case X86::ATOMNAND8:
13138 RegOpc = X86::AND8rr; ImmOpc = X86::AND8ri; Invert = true; break;
13140 return EmitAtomicBitwiseWithCustomInserter(MI, BB, RegOpc, ImmOpc,
13141 X86::MOV8rm, X86::LCMPXCHG8,
13142 X86::NOT8r, X86::AL,
13143 &X86::GR8RegClass, Invert);
13146 // This group is for 64-bit host.
13147 case X86::ATOMAND64:
13148 case X86::ATOMOR64:
13149 case X86::ATOMXOR64:
13150 case X86::ATOMNAND64: {
13151 bool Invert = false;
13152 unsigned RegOpc, ImmOpc;
13153 switch (MI->getOpcode()) {
13154 default: llvm_unreachable("illegal opcode!");
13155 case X86::ATOMAND64:
13156 RegOpc = X86::AND64rr; ImmOpc = X86::AND64ri32; break;
13157 case X86::ATOMOR64:
13158 RegOpc = X86::OR64rr; ImmOpc = X86::OR64ri32; break;
13159 case X86::ATOMXOR64:
13160 RegOpc = X86::XOR64rr; ImmOpc = X86::XOR64ri32; break;
13161 case X86::ATOMNAND64:
13162 RegOpc = X86::AND64rr; ImmOpc = X86::AND64ri32; Invert = true; break;
13164 return EmitAtomicBitwiseWithCustomInserter(MI, BB, RegOpc, ImmOpc,
13165 X86::MOV64rm, X86::LCMPXCHG64,
13166 X86::NOT64r, X86::RAX,
13167 &X86::GR64RegClass, Invert);
13170 // This group does 64-bit operations on a 32-bit host.
13171 case X86::ATOMAND6432:
13172 case X86::ATOMOR6432:
13173 case X86::ATOMXOR6432:
13174 case X86::ATOMNAND6432:
13175 case X86::ATOMADD6432:
13176 case X86::ATOMSUB6432:
13177 case X86::ATOMSWAP6432: {
13178 bool Invert = false;
13179 unsigned RegOpcL, RegOpcH, ImmOpcL, ImmOpcH;
13180 switch (MI->getOpcode()) {
13181 default: llvm_unreachable("illegal opcode!");
13182 case X86::ATOMAND6432:
13183 RegOpcL = RegOpcH = X86::AND32rr;
13184 ImmOpcL = ImmOpcH = X86::AND32ri;
13186 case X86::ATOMOR6432:
13187 RegOpcL = RegOpcH = X86::OR32rr;
13188 ImmOpcL = ImmOpcH = X86::OR32ri;
13190 case X86::ATOMXOR6432:
13191 RegOpcL = RegOpcH = X86::XOR32rr;
13192 ImmOpcL = ImmOpcH = X86::XOR32ri;
13194 case X86::ATOMNAND6432:
13195 RegOpcL = RegOpcH = X86::AND32rr;
13196 ImmOpcL = ImmOpcH = X86::AND32ri;
13199 case X86::ATOMADD6432:
13200 RegOpcL = X86::ADD32rr; RegOpcH = X86::ADC32rr;
13201 ImmOpcL = X86::ADD32ri; ImmOpcH = X86::ADC32ri;
13203 case X86::ATOMSUB6432:
13204 RegOpcL = X86::SUB32rr; RegOpcH = X86::SBB32rr;
13205 ImmOpcL = X86::SUB32ri; ImmOpcH = X86::SBB32ri;
13207 case X86::ATOMSWAP6432:
13208 RegOpcL = RegOpcH = X86::MOV32rr;
13209 ImmOpcL = ImmOpcH = X86::MOV32ri;
13212 return EmitAtomicBit6432WithCustomInserter(MI, BB, RegOpcL, RegOpcH,
13213 ImmOpcL, ImmOpcH, Invert);
13216 case X86::VASTART_SAVE_XMM_REGS:
13217 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
13219 case X86::VAARG_64:
13220 return EmitVAARG64WithCustomInserter(MI, BB);
13224 //===----------------------------------------------------------------------===//
13225 // X86 Optimization Hooks
13226 //===----------------------------------------------------------------------===//
13228 void X86TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
13231 const SelectionDAG &DAG,
13232 unsigned Depth) const {
13233 unsigned BitWidth = KnownZero.getBitWidth();
13234 unsigned Opc = Op.getOpcode();
13235 assert((Opc >= ISD::BUILTIN_OP_END ||
13236 Opc == ISD::INTRINSIC_WO_CHAIN ||
13237 Opc == ISD::INTRINSIC_W_CHAIN ||
13238 Opc == ISD::INTRINSIC_VOID) &&
13239 "Should use MaskedValueIsZero if you don't know whether Op"
13240 " is a target node!");
13242 KnownZero = KnownOne = APInt(BitWidth, 0); // Don't know anything.
13256 // These nodes' second result is a boolean.
13257 if (Op.getResNo() == 0)
13260 case X86ISD::SETCC:
13261 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1);
13263 case ISD::INTRINSIC_WO_CHAIN: {
13264 unsigned IntId = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
13265 unsigned NumLoBits = 0;
13268 case Intrinsic::x86_sse_movmsk_ps:
13269 case Intrinsic::x86_avx_movmsk_ps_256:
13270 case Intrinsic::x86_sse2_movmsk_pd:
13271 case Intrinsic::x86_avx_movmsk_pd_256:
13272 case Intrinsic::x86_mmx_pmovmskb:
13273 case Intrinsic::x86_sse2_pmovmskb_128:
13274 case Intrinsic::x86_avx2_pmovmskb: {
13275 // High bits of movmskp{s|d}, pmovmskb are known zero.
13277 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
13278 case Intrinsic::x86_sse_movmsk_ps: NumLoBits = 4; break;
13279 case Intrinsic::x86_avx_movmsk_ps_256: NumLoBits = 8; break;
13280 case Intrinsic::x86_sse2_movmsk_pd: NumLoBits = 2; break;
13281 case Intrinsic::x86_avx_movmsk_pd_256: NumLoBits = 4; break;
13282 case Intrinsic::x86_mmx_pmovmskb: NumLoBits = 8; break;
13283 case Intrinsic::x86_sse2_pmovmskb_128: NumLoBits = 16; break;
13284 case Intrinsic::x86_avx2_pmovmskb: NumLoBits = 32; break;
13286 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - NumLoBits);
13295 unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(SDValue Op,
13296 unsigned Depth) const {
13297 // SETCC_CARRY sets the dest to ~0 for true or 0 for false.
13298 if (Op.getOpcode() == X86ISD::SETCC_CARRY)
13299 return Op.getValueType().getScalarType().getSizeInBits();
13305 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
13306 /// node is a GlobalAddress + offset.
13307 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
13308 const GlobalValue* &GA,
13309 int64_t &Offset) const {
13310 if (N->getOpcode() == X86ISD::Wrapper) {
13311 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
13312 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
13313 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
13317 return TargetLowering::isGAPlusOffset(N, GA, Offset);
13320 /// isShuffleHigh128VectorInsertLow - Checks whether the shuffle node is the
13321 /// same as extracting the high 128-bit part of 256-bit vector and then
13322 /// inserting the result into the low part of a new 256-bit vector
13323 static bool isShuffleHigh128VectorInsertLow(ShuffleVectorSDNode *SVOp) {
13324 EVT VT = SVOp->getValueType(0);
13325 unsigned NumElems = VT.getVectorNumElements();
13327 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
13328 for (unsigned i = 0, j = NumElems/2; i != NumElems/2; ++i, ++j)
13329 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
13330 SVOp->getMaskElt(j) >= 0)
13336 /// isShuffleLow128VectorInsertHigh - Checks whether the shuffle node is the
13337 /// same as extracting the low 128-bit part of 256-bit vector and then
13338 /// inserting the result into the high part of a new 256-bit vector
13339 static bool isShuffleLow128VectorInsertHigh(ShuffleVectorSDNode *SVOp) {
13340 EVT VT = SVOp->getValueType(0);
13341 unsigned NumElems = VT.getVectorNumElements();
13343 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
13344 for (unsigned i = NumElems/2, j = 0; i != NumElems; ++i, ++j)
13345 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
13346 SVOp->getMaskElt(j) >= 0)
13352 /// PerformShuffleCombine256 - Performs shuffle combines for 256-bit vectors.
13353 static SDValue PerformShuffleCombine256(SDNode *N, SelectionDAG &DAG,
13354 TargetLowering::DAGCombinerInfo &DCI,
13355 const X86Subtarget* Subtarget) {
13356 DebugLoc dl = N->getDebugLoc();
13357 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
13358 SDValue V1 = SVOp->getOperand(0);
13359 SDValue V2 = SVOp->getOperand(1);
13360 EVT VT = SVOp->getValueType(0);
13361 unsigned NumElems = VT.getVectorNumElements();
13363 if (V1.getOpcode() == ISD::CONCAT_VECTORS &&
13364 V2.getOpcode() == ISD::CONCAT_VECTORS) {
13368 // V UNDEF BUILD_VECTOR UNDEF
13370 // CONCAT_VECTOR CONCAT_VECTOR
13373 // RESULT: V + zero extended
13375 if (V2.getOperand(0).getOpcode() != ISD::BUILD_VECTOR ||
13376 V2.getOperand(1).getOpcode() != ISD::UNDEF ||
13377 V1.getOperand(1).getOpcode() != ISD::UNDEF)
13380 if (!ISD::isBuildVectorAllZeros(V2.getOperand(0).getNode()))
13383 // To match the shuffle mask, the first half of the mask should
13384 // be exactly the first vector, and all the rest a splat with the
13385 // first element of the second one.
13386 for (unsigned i = 0; i != NumElems/2; ++i)
13387 if (!isUndefOrEqual(SVOp->getMaskElt(i), i) ||
13388 !isUndefOrEqual(SVOp->getMaskElt(i+NumElems/2), NumElems))
13391 // If V1 is coming from a vector load then just fold to a VZEXT_LOAD.
13392 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(V1.getOperand(0))) {
13393 if (Ld->hasNUsesOfValue(1, 0)) {
13394 SDVTList Tys = DAG.getVTList(MVT::v4i64, MVT::Other);
13395 SDValue Ops[] = { Ld->getChain(), Ld->getBasePtr() };
13397 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops, 2,
13399 Ld->getPointerInfo(),
13400 Ld->getAlignment(),
13401 false/*isVolatile*/, true/*ReadMem*/,
13402 false/*WriteMem*/);
13403 return DAG.getNode(ISD::BITCAST, dl, VT, ResNode);
13407 // Emit a zeroed vector and insert the desired subvector on its
13409 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
13410 SDValue InsV = Insert128BitVector(Zeros, V1.getOperand(0), 0, DAG, dl);
13411 return DCI.CombineTo(N, InsV);
13414 //===--------------------------------------------------------------------===//
13415 // Combine some shuffles into subvector extracts and inserts:
13418 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
13419 if (isShuffleHigh128VectorInsertLow(SVOp)) {
13420 SDValue V = Extract128BitVector(V1, NumElems/2, DAG, dl);
13421 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, 0, DAG, dl);
13422 return DCI.CombineTo(N, InsV);
13425 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
13426 if (isShuffleLow128VectorInsertHigh(SVOp)) {
13427 SDValue V = Extract128BitVector(V1, 0, DAG, dl);
13428 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, NumElems/2, DAG, dl);
13429 return DCI.CombineTo(N, InsV);
13435 /// PerformShuffleCombine - Performs several different shuffle combines.
13436 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
13437 TargetLowering::DAGCombinerInfo &DCI,
13438 const X86Subtarget *Subtarget) {
13439 DebugLoc dl = N->getDebugLoc();
13440 EVT VT = N->getValueType(0);
13442 // Don't create instructions with illegal types after legalize types has run.
13443 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13444 if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType()))
13447 // Combine 256-bit vector shuffles. This is only profitable when in AVX mode
13448 if (Subtarget->hasAVX() && VT.is256BitVector() &&
13449 N->getOpcode() == ISD::VECTOR_SHUFFLE)
13450 return PerformShuffleCombine256(N, DAG, DCI, Subtarget);
13452 // Only handle 128 wide vector from here on.
13453 if (!VT.is128BitVector())
13456 // Combine a vector_shuffle that is equal to build_vector load1, load2, load3,
13457 // load4, <0, 1, 2, 3> into a 128-bit load if the load addresses are
13458 // consecutive, non-overlapping, and in the right order.
13459 SmallVector<SDValue, 16> Elts;
13460 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
13461 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0));
13463 return EltsFromConsecutiveLoads(VT, Elts, dl, DAG);
13467 /// DCI, PerformTruncateCombine - Converts truncate operation to
13468 /// a sequence of vector shuffle operations.
13469 /// It is possible when we truncate 256-bit vector to 128-bit vector
13471 SDValue X86TargetLowering::PerformTruncateCombine(SDNode *N, SelectionDAG &DAG,
13472 DAGCombinerInfo &DCI) const {
13473 if (!DCI.isBeforeLegalizeOps())
13476 if (!Subtarget->hasAVX())
13479 EVT VT = N->getValueType(0);
13480 SDValue Op = N->getOperand(0);
13481 EVT OpVT = Op.getValueType();
13482 DebugLoc dl = N->getDebugLoc();
13484 if ((VT == MVT::v4i32) && (OpVT == MVT::v4i64)) {
13486 if (Subtarget->hasAVX2()) {
13487 // AVX2: v4i64 -> v4i32
13490 static const int ShufMask[] = {0, 2, 4, 6, -1, -1, -1, -1};
13492 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v8i32, Op);
13493 Op = DAG.getVectorShuffle(MVT::v8i32, dl, Op, DAG.getUNDEF(MVT::v8i32),
13496 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, Op,
13497 DAG.getIntPtrConstant(0));
13500 // AVX: v4i64 -> v4i32
13501 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v2i64, Op,
13502 DAG.getIntPtrConstant(0));
13504 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v2i64, Op,
13505 DAG.getIntPtrConstant(2));
13507 OpLo = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, OpLo);
13508 OpHi = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, OpHi);
13511 static const int ShufMask1[] = {0, 2, 0, 0};
13513 SDValue Undef = DAG.getUNDEF(VT);
13514 OpLo = DAG.getVectorShuffle(VT, dl, OpLo, Undef, ShufMask1);
13515 OpHi = DAG.getVectorShuffle(VT, dl, OpHi, Undef, ShufMask1);
13518 static const int ShufMask2[] = {0, 1, 4, 5};
13520 return DAG.getVectorShuffle(VT, dl, OpLo, OpHi, ShufMask2);
13523 if ((VT == MVT::v8i16) && (OpVT == MVT::v8i32)) {
13525 if (Subtarget->hasAVX2()) {
13526 // AVX2: v8i32 -> v8i16
13528 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v32i8, Op);
13531 SmallVector<SDValue,32> pshufbMask;
13532 for (unsigned i = 0; i < 2; ++i) {
13533 pshufbMask.push_back(DAG.getConstant(0x0, MVT::i8));
13534 pshufbMask.push_back(DAG.getConstant(0x1, MVT::i8));
13535 pshufbMask.push_back(DAG.getConstant(0x4, MVT::i8));
13536 pshufbMask.push_back(DAG.getConstant(0x5, MVT::i8));
13537 pshufbMask.push_back(DAG.getConstant(0x8, MVT::i8));
13538 pshufbMask.push_back(DAG.getConstant(0x9, MVT::i8));
13539 pshufbMask.push_back(DAG.getConstant(0xc, MVT::i8));
13540 pshufbMask.push_back(DAG.getConstant(0xd, MVT::i8));
13541 for (unsigned j = 0; j < 8; ++j)
13542 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
13544 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v32i8,
13545 &pshufbMask[0], 32);
13546 Op = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v32i8, Op, BV);
13548 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4i64, Op);
13550 static const int ShufMask[] = {0, 2, -1, -1};
13551 Op = DAG.getVectorShuffle(MVT::v4i64, dl, Op, DAG.getUNDEF(MVT::v4i64),
13554 Op = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v2i64, Op,
13555 DAG.getIntPtrConstant(0));
13557 return DAG.getNode(ISD::BITCAST, dl, VT, Op);
13560 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i32, Op,
13561 DAG.getIntPtrConstant(0));
13563 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i32, Op,
13564 DAG.getIntPtrConstant(4));
13566 OpLo = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpLo);
13567 OpHi = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpHi);
13570 static const int ShufMask1[] = {0, 1, 4, 5, 8, 9, 12, 13,
13571 -1, -1, -1, -1, -1, -1, -1, -1};
13573 SDValue Undef = DAG.getUNDEF(MVT::v16i8);
13574 OpLo = DAG.getVectorShuffle(MVT::v16i8, dl, OpLo, Undef, ShufMask1);
13575 OpHi = DAG.getVectorShuffle(MVT::v16i8, dl, OpHi, Undef, ShufMask1);
13577 OpLo = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, OpLo);
13578 OpHi = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, OpHi);
13581 static const int ShufMask2[] = {0, 1, 4, 5};
13583 SDValue res = DAG.getVectorShuffle(MVT::v4i32, dl, OpLo, OpHi, ShufMask2);
13584 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, res);
13590 /// XFormVExtractWithShuffleIntoLoad - Check if a vector extract from a target
13591 /// specific shuffle of a load can be folded into a single element load.
13592 /// Similar handling for VECTOR_SHUFFLE is performed by DAGCombiner, but
13593 /// shuffles have been customed lowered so we need to handle those here.
13594 static SDValue XFormVExtractWithShuffleIntoLoad(SDNode *N, SelectionDAG &DAG,
13595 TargetLowering::DAGCombinerInfo &DCI) {
13596 if (DCI.isBeforeLegalizeOps())
13599 SDValue InVec = N->getOperand(0);
13600 SDValue EltNo = N->getOperand(1);
13602 if (!isa<ConstantSDNode>(EltNo))
13605 EVT VT = InVec.getValueType();
13607 bool HasShuffleIntoBitcast = false;
13608 if (InVec.getOpcode() == ISD::BITCAST) {
13609 // Don't duplicate a load with other uses.
13610 if (!InVec.hasOneUse())
13612 EVT BCVT = InVec.getOperand(0).getValueType();
13613 if (BCVT.getVectorNumElements() != VT.getVectorNumElements())
13615 InVec = InVec.getOperand(0);
13616 HasShuffleIntoBitcast = true;
13619 if (!isTargetShuffle(InVec.getOpcode()))
13622 // Don't duplicate a load with other uses.
13623 if (!InVec.hasOneUse())
13626 SmallVector<int, 16> ShuffleMask;
13628 if (!getTargetShuffleMask(InVec.getNode(), VT.getSimpleVT(), ShuffleMask,
13632 // Select the input vector, guarding against out of range extract vector.
13633 unsigned NumElems = VT.getVectorNumElements();
13634 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
13635 int Idx = (Elt > (int)NumElems) ? -1 : ShuffleMask[Elt];
13636 SDValue LdNode = (Idx < (int)NumElems) ? InVec.getOperand(0)
13637 : InVec.getOperand(1);
13639 // If inputs to shuffle are the same for both ops, then allow 2 uses
13640 unsigned AllowedUses = InVec.getOperand(0) == InVec.getOperand(1) ? 2 : 1;
13642 if (LdNode.getOpcode() == ISD::BITCAST) {
13643 // Don't duplicate a load with other uses.
13644 if (!LdNode.getNode()->hasNUsesOfValue(AllowedUses, 0))
13647 AllowedUses = 1; // only allow 1 load use if we have a bitcast
13648 LdNode = LdNode.getOperand(0);
13651 if (!ISD::isNormalLoad(LdNode.getNode()))
13654 LoadSDNode *LN0 = cast<LoadSDNode>(LdNode);
13656 if (!LN0 ||!LN0->hasNUsesOfValue(AllowedUses, 0) || LN0->isVolatile())
13659 if (HasShuffleIntoBitcast) {
13660 // If there's a bitcast before the shuffle, check if the load type and
13661 // alignment is valid.
13662 unsigned Align = LN0->getAlignment();
13663 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13664 unsigned NewAlign = TLI.getTargetData()->
13665 getABITypeAlignment(VT.getTypeForEVT(*DAG.getContext()));
13667 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, VT))
13671 // All checks match so transform back to vector_shuffle so that DAG combiner
13672 // can finish the job
13673 DebugLoc dl = N->getDebugLoc();
13675 // Create shuffle node taking into account the case that its a unary shuffle
13676 SDValue Shuffle = (UnaryShuffle) ? DAG.getUNDEF(VT) : InVec.getOperand(1);
13677 Shuffle = DAG.getVectorShuffle(InVec.getValueType(), dl,
13678 InVec.getOperand(0), Shuffle,
13680 Shuffle = DAG.getNode(ISD::BITCAST, dl, VT, Shuffle);
13681 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, N->getValueType(0), Shuffle,
13685 /// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index
13686 /// generation and convert it from being a bunch of shuffles and extracts
13687 /// to a simple store and scalar loads to extract the elements.
13688 static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG,
13689 TargetLowering::DAGCombinerInfo &DCI) {
13690 SDValue NewOp = XFormVExtractWithShuffleIntoLoad(N, DAG, DCI);
13691 if (NewOp.getNode())
13694 SDValue InputVector = N->getOperand(0);
13696 // Only operate on vectors of 4 elements, where the alternative shuffling
13697 // gets to be more expensive.
13698 if (InputVector.getValueType() != MVT::v4i32)
13701 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a
13702 // single use which is a sign-extend or zero-extend, and all elements are
13704 SmallVector<SDNode *, 4> Uses;
13705 unsigned ExtractedElements = 0;
13706 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(),
13707 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) {
13708 if (UI.getUse().getResNo() != InputVector.getResNo())
13711 SDNode *Extract = *UI;
13712 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
13715 if (Extract->getValueType(0) != MVT::i32)
13717 if (!Extract->hasOneUse())
13719 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND &&
13720 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND)
13722 if (!isa<ConstantSDNode>(Extract->getOperand(1)))
13725 // Record which element was extracted.
13726 ExtractedElements |=
13727 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue();
13729 Uses.push_back(Extract);
13732 // If not all the elements were used, this may not be worthwhile.
13733 if (ExtractedElements != 15)
13736 // Ok, we've now decided to do the transformation.
13737 DebugLoc dl = InputVector.getDebugLoc();
13739 // Store the value to a temporary stack slot.
13740 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType());
13741 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr,
13742 MachinePointerInfo(), false, false, 0);
13744 // Replace each use (extract) with a load of the appropriate element.
13745 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(),
13746 UE = Uses.end(); UI != UE; ++UI) {
13747 SDNode *Extract = *UI;
13749 // cOMpute the element's address.
13750 SDValue Idx = Extract->getOperand(1);
13752 InputVector.getValueType().getVectorElementType().getSizeInBits()/8;
13753 uint64_t Offset = EltSize * cast<ConstantSDNode>(Idx)->getZExtValue();
13754 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13755 SDValue OffsetVal = DAG.getConstant(Offset, TLI.getPointerTy());
13757 SDValue ScalarAddr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(),
13758 StackPtr, OffsetVal);
13760 // Load the scalar.
13761 SDValue LoadScalar = DAG.getLoad(Extract->getValueType(0), dl, Ch,
13762 ScalarAddr, MachinePointerInfo(),
13763 false, false, false, 0);
13765 // Replace the exact with the load.
13766 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), LoadScalar);
13769 // The replacement was made in place; don't return anything.
13773 /// PerformSELECTCombine - Do target-specific dag combines on SELECT and VSELECT
13775 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
13776 TargetLowering::DAGCombinerInfo &DCI,
13777 const X86Subtarget *Subtarget) {
13778 DebugLoc DL = N->getDebugLoc();
13779 SDValue Cond = N->getOperand(0);
13780 // Get the LHS/RHS of the select.
13781 SDValue LHS = N->getOperand(1);
13782 SDValue RHS = N->getOperand(2);
13783 EVT VT = LHS.getValueType();
13785 // If we have SSE[12] support, try to form min/max nodes. SSE min/max
13786 // instructions match the semantics of the common C idiom x<y?x:y but not
13787 // x<=y?x:y, because of how they handle negative zero (which can be
13788 // ignored in unsafe-math mode).
13789 if (Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() &&
13790 VT != MVT::f80 && DAG.getTargetLoweringInfo().isTypeLegal(VT) &&
13791 (Subtarget->hasSSE2() ||
13792 (Subtarget->hasSSE1() && VT.getScalarType() == MVT::f32))) {
13793 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
13795 unsigned Opcode = 0;
13796 // Check for x CC y ? x : y.
13797 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
13798 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
13802 // Converting this to a min would handle NaNs incorrectly, and swapping
13803 // the operands would cause it to handle comparisons between positive
13804 // and negative zero incorrectly.
13805 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
13806 if (!DAG.getTarget().Options.UnsafeFPMath &&
13807 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
13809 std::swap(LHS, RHS);
13811 Opcode = X86ISD::FMIN;
13814 // Converting this to a min would handle comparisons between positive
13815 // and negative zero incorrectly.
13816 if (!DAG.getTarget().Options.UnsafeFPMath &&
13817 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
13819 Opcode = X86ISD::FMIN;
13822 // Converting this to a min would handle both negative zeros and NaNs
13823 // incorrectly, but we can swap the operands to fix both.
13824 std::swap(LHS, RHS);
13828 Opcode = X86ISD::FMIN;
13832 // Converting this to a max would handle comparisons between positive
13833 // and negative zero incorrectly.
13834 if (!DAG.getTarget().Options.UnsafeFPMath &&
13835 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
13837 Opcode = X86ISD::FMAX;
13840 // Converting this to a max would handle NaNs incorrectly, and swapping
13841 // the operands would cause it to handle comparisons between positive
13842 // and negative zero incorrectly.
13843 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
13844 if (!DAG.getTarget().Options.UnsafeFPMath &&
13845 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
13847 std::swap(LHS, RHS);
13849 Opcode = X86ISD::FMAX;
13852 // Converting this to a max would handle both negative zeros and NaNs
13853 // incorrectly, but we can swap the operands to fix both.
13854 std::swap(LHS, RHS);
13858 Opcode = X86ISD::FMAX;
13861 // Check for x CC y ? y : x -- a min/max with reversed arms.
13862 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
13863 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
13867 // Converting this to a min would handle comparisons between positive
13868 // and negative zero incorrectly, and swapping the operands would
13869 // cause it to handle NaNs incorrectly.
13870 if (!DAG.getTarget().Options.UnsafeFPMath &&
13871 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) {
13872 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
13874 std::swap(LHS, RHS);
13876 Opcode = X86ISD::FMIN;
13879 // Converting this to a min would handle NaNs incorrectly.
13880 if (!DAG.getTarget().Options.UnsafeFPMath &&
13881 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
13883 Opcode = X86ISD::FMIN;
13886 // Converting this to a min would handle both negative zeros and NaNs
13887 // incorrectly, but we can swap the operands to fix both.
13888 std::swap(LHS, RHS);
13892 Opcode = X86ISD::FMIN;
13896 // Converting this to a max would handle NaNs incorrectly.
13897 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
13899 Opcode = X86ISD::FMAX;
13902 // Converting this to a max would handle comparisons between positive
13903 // and negative zero incorrectly, and swapping the operands would
13904 // cause it to handle NaNs incorrectly.
13905 if (!DAG.getTarget().Options.UnsafeFPMath &&
13906 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) {
13907 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
13909 std::swap(LHS, RHS);
13911 Opcode = X86ISD::FMAX;
13914 // Converting this to a max would handle both negative zeros and NaNs
13915 // incorrectly, but we can swap the operands to fix both.
13916 std::swap(LHS, RHS);
13920 Opcode = X86ISD::FMAX;
13926 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
13929 // If this is a select between two integer constants, try to do some
13931 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
13932 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
13933 // Don't do this for crazy integer types.
13934 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
13935 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
13936 // so that TrueC (the true value) is larger than FalseC.
13937 bool NeedsCondInvert = false;
13939 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
13940 // Efficiently invertible.
13941 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
13942 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
13943 isa<ConstantSDNode>(Cond.getOperand(1))))) {
13944 NeedsCondInvert = true;
13945 std::swap(TrueC, FalseC);
13948 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
13949 if (FalseC->getAPIntValue() == 0 &&
13950 TrueC->getAPIntValue().isPowerOf2()) {
13951 if (NeedsCondInvert) // Invert the condition if needed.
13952 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
13953 DAG.getConstant(1, Cond.getValueType()));
13955 // Zero extend the condition if needed.
13956 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
13958 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
13959 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
13960 DAG.getConstant(ShAmt, MVT::i8));
13963 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
13964 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
13965 if (NeedsCondInvert) // Invert the condition if needed.
13966 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
13967 DAG.getConstant(1, Cond.getValueType()));
13969 // Zero extend the condition if needed.
13970 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
13971 FalseC->getValueType(0), Cond);
13972 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
13973 SDValue(FalseC, 0));
13976 // Optimize cases that will turn into an LEA instruction. This requires
13977 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
13978 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
13979 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
13980 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
13982 bool isFastMultiplier = false;
13984 switch ((unsigned char)Diff) {
13986 case 1: // result = add base, cond
13987 case 2: // result = lea base( , cond*2)
13988 case 3: // result = lea base(cond, cond*2)
13989 case 4: // result = lea base( , cond*4)
13990 case 5: // result = lea base(cond, cond*4)
13991 case 8: // result = lea base( , cond*8)
13992 case 9: // result = lea base(cond, cond*8)
13993 isFastMultiplier = true;
13998 if (isFastMultiplier) {
13999 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
14000 if (NeedsCondInvert) // Invert the condition if needed.
14001 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
14002 DAG.getConstant(1, Cond.getValueType()));
14004 // Zero extend the condition if needed.
14005 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
14007 // Scale the condition by the difference.
14009 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
14010 DAG.getConstant(Diff, Cond.getValueType()));
14012 // Add the base if non-zero.
14013 if (FalseC->getAPIntValue() != 0)
14014 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
14015 SDValue(FalseC, 0));
14022 // Canonicalize max and min:
14023 // (x > y) ? x : y -> (x >= y) ? x : y
14024 // (x < y) ? x : y -> (x <= y) ? x : y
14025 // This allows use of COND_S / COND_NS (see TranslateX86CC) which eliminates
14026 // the need for an extra compare
14027 // against zero. e.g.
14028 // (x - y) > 0 : (x - y) ? 0 -> (x - y) >= 0 : (x - y) ? 0
14030 // testl %edi, %edi
14032 // cmovgl %edi, %eax
14036 // cmovsl %eax, %edi
14037 if (N->getOpcode() == ISD::SELECT && Cond.getOpcode() == ISD::SETCC &&
14038 DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
14039 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
14040 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
14045 ISD::CondCode NewCC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGE;
14046 Cond = DAG.getSetCC(Cond.getDebugLoc(), Cond.getValueType(),
14047 Cond.getOperand(0), Cond.getOperand(1), NewCC);
14048 return DAG.getNode(ISD::SELECT, DL, VT, Cond, LHS, RHS);
14053 // If we know that this node is legal then we know that it is going to be
14054 // matched by one of the SSE/AVX BLEND instructions. These instructions only
14055 // depend on the highest bit in each word. Try to use SimplifyDemandedBits
14056 // to simplify previous instructions.
14057 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14058 if (N->getOpcode() == ISD::VSELECT && DCI.isBeforeLegalizeOps() &&
14059 !DCI.isBeforeLegalize() && TLI.isOperationLegal(ISD::VSELECT, VT)) {
14060 unsigned BitWidth = Cond.getValueType().getScalarType().getSizeInBits();
14062 // Don't optimize vector selects that map to mask-registers.
14066 assert(BitWidth >= 8 && BitWidth <= 64 && "Invalid mask size");
14067 APInt DemandedMask = APInt::getHighBitsSet(BitWidth, 1);
14069 APInt KnownZero, KnownOne;
14070 TargetLowering::TargetLoweringOpt TLO(DAG, DCI.isBeforeLegalize(),
14071 DCI.isBeforeLegalizeOps());
14072 if (TLO.ShrinkDemandedConstant(Cond, DemandedMask) ||
14073 TLI.SimplifyDemandedBits(Cond, DemandedMask, KnownZero, KnownOne, TLO))
14074 DCI.CommitTargetLoweringOpt(TLO);
14080 // Check whether a boolean test is testing a boolean value generated by
14081 // X86ISD::SETCC. If so, return the operand of that SETCC and proper condition
14084 // Simplify the following patterns:
14085 // (Op (CMP (SETCC Cond EFLAGS) 1) EQ) or
14086 // (Op (CMP (SETCC Cond EFLAGS) 0) NEQ)
14087 // to (Op EFLAGS Cond)
14089 // (Op (CMP (SETCC Cond EFLAGS) 0) EQ) or
14090 // (Op (CMP (SETCC Cond EFLAGS) 1) NEQ)
14091 // to (Op EFLAGS !Cond)
14093 // where Op could be BRCOND or CMOV.
14095 static SDValue BoolTestSetCCCombine(SDValue Cmp, X86::CondCode &CC) {
14096 // Quit if not CMP and SUB with its value result used.
14097 if (Cmp.getOpcode() != X86ISD::CMP &&
14098 (Cmp.getOpcode() != X86ISD::SUB || Cmp.getNode()->hasAnyUseOfValue(0)))
14101 // Quit if not used as a boolean value.
14102 if (CC != X86::COND_E && CC != X86::COND_NE)
14105 // Check CMP operands. One of them should be 0 or 1 and the other should be
14106 // an SetCC or extended from it.
14107 SDValue Op1 = Cmp.getOperand(0);
14108 SDValue Op2 = Cmp.getOperand(1);
14111 const ConstantSDNode* C = 0;
14112 bool needOppositeCond = (CC == X86::COND_E);
14114 if ((C = dyn_cast<ConstantSDNode>(Op1)))
14116 else if ((C = dyn_cast<ConstantSDNode>(Op2)))
14118 else // Quit if all operands are not constants.
14121 if (C->getZExtValue() == 1)
14122 needOppositeCond = !needOppositeCond;
14123 else if (C->getZExtValue() != 0)
14124 // Quit if the constant is neither 0 or 1.
14127 // Skip 'zext' node.
14128 if (SetCC.getOpcode() == ISD::ZERO_EXTEND)
14129 SetCC = SetCC.getOperand(0);
14131 // Quit if not SETCC.
14132 // FIXME: So far we only handle the boolean value generated from SETCC. If
14133 // there is other ways to generate boolean values, we need handle them here
14135 if (SetCC.getOpcode() != X86ISD::SETCC)
14138 // Set the condition code or opposite one if necessary.
14139 CC = X86::CondCode(SetCC.getConstantOperandVal(0));
14140 if (needOppositeCond)
14141 CC = X86::GetOppositeBranchCondition(CC);
14143 return SetCC.getOperand(1);
14146 static bool IsValidFCMOVCondition(X86::CondCode CC) {
14162 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
14163 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
14164 TargetLowering::DAGCombinerInfo &DCI) {
14165 DebugLoc DL = N->getDebugLoc();
14167 // If the flag operand isn't dead, don't touch this CMOV.
14168 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
14171 SDValue FalseOp = N->getOperand(0);
14172 SDValue TrueOp = N->getOperand(1);
14173 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
14174 SDValue Cond = N->getOperand(3);
14176 if (CC == X86::COND_E || CC == X86::COND_NE) {
14177 switch (Cond.getOpcode()) {
14181 // If operand of BSR / BSF are proven never zero, then ZF cannot be set.
14182 if (DAG.isKnownNeverZero(Cond.getOperand(0)))
14183 return (CC == X86::COND_E) ? FalseOp : TrueOp;
14189 Flags = BoolTestSetCCCombine(Cond, CC);
14190 if (Flags.getNode() &&
14191 // Extra check as FCMOV only supports a subset of X86 cond.
14192 (FalseOp.getValueType() != MVT::f80 || IsValidFCMOVCondition(CC))) {
14193 SDValue Ops[] = { FalseOp, TrueOp,
14194 DAG.getConstant(CC, MVT::i8), Flags };
14195 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList(),
14196 Ops, array_lengthof(Ops));
14199 // If this is a select between two integer constants, try to do some
14200 // optimizations. Note that the operands are ordered the opposite of SELECT
14202 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(TrueOp)) {
14203 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(FalseOp)) {
14204 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
14205 // larger than FalseC (the false value).
14206 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
14207 CC = X86::GetOppositeBranchCondition(CC);
14208 std::swap(TrueC, FalseC);
14211 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
14212 // This is efficient for any integer data type (including i8/i16) and
14214 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
14215 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
14216 DAG.getConstant(CC, MVT::i8), Cond);
14218 // Zero extend the condition if needed.
14219 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
14221 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
14222 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
14223 DAG.getConstant(ShAmt, MVT::i8));
14224 if (N->getNumValues() == 2) // Dead flag value?
14225 return DCI.CombineTo(N, Cond, SDValue());
14229 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
14230 // for any integer data type, including i8/i16.
14231 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
14232 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
14233 DAG.getConstant(CC, MVT::i8), Cond);
14235 // Zero extend the condition if needed.
14236 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
14237 FalseC->getValueType(0), Cond);
14238 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
14239 SDValue(FalseC, 0));
14241 if (N->getNumValues() == 2) // Dead flag value?
14242 return DCI.CombineTo(N, Cond, SDValue());
14246 // Optimize cases that will turn into an LEA instruction. This requires
14247 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
14248 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
14249 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
14250 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
14252 bool isFastMultiplier = false;
14254 switch ((unsigned char)Diff) {
14256 case 1: // result = add base, cond
14257 case 2: // result = lea base( , cond*2)
14258 case 3: // result = lea base(cond, cond*2)
14259 case 4: // result = lea base( , cond*4)
14260 case 5: // result = lea base(cond, cond*4)
14261 case 8: // result = lea base( , cond*8)
14262 case 9: // result = lea base(cond, cond*8)
14263 isFastMultiplier = true;
14268 if (isFastMultiplier) {
14269 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
14270 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
14271 DAG.getConstant(CC, MVT::i8), Cond);
14272 // Zero extend the condition if needed.
14273 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
14275 // Scale the condition by the difference.
14277 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
14278 DAG.getConstant(Diff, Cond.getValueType()));
14280 // Add the base if non-zero.
14281 if (FalseC->getAPIntValue() != 0)
14282 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
14283 SDValue(FalseC, 0));
14284 if (N->getNumValues() == 2) // Dead flag value?
14285 return DCI.CombineTo(N, Cond, SDValue());
14295 /// PerformMulCombine - Optimize a single multiply with constant into two
14296 /// in order to implement it with two cheaper instructions, e.g.
14297 /// LEA + SHL, LEA + LEA.
14298 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
14299 TargetLowering::DAGCombinerInfo &DCI) {
14300 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
14303 EVT VT = N->getValueType(0);
14304 if (VT != MVT::i64)
14307 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
14310 uint64_t MulAmt = C->getZExtValue();
14311 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
14314 uint64_t MulAmt1 = 0;
14315 uint64_t MulAmt2 = 0;
14316 if ((MulAmt % 9) == 0) {
14318 MulAmt2 = MulAmt / 9;
14319 } else if ((MulAmt % 5) == 0) {
14321 MulAmt2 = MulAmt / 5;
14322 } else if ((MulAmt % 3) == 0) {
14324 MulAmt2 = MulAmt / 3;
14327 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
14328 DebugLoc DL = N->getDebugLoc();
14330 if (isPowerOf2_64(MulAmt2) &&
14331 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
14332 // If second multiplifer is pow2, issue it first. We want the multiply by
14333 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
14335 std::swap(MulAmt1, MulAmt2);
14338 if (isPowerOf2_64(MulAmt1))
14339 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
14340 DAG.getConstant(Log2_64(MulAmt1), MVT::i8));
14342 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
14343 DAG.getConstant(MulAmt1, VT));
14345 if (isPowerOf2_64(MulAmt2))
14346 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
14347 DAG.getConstant(Log2_64(MulAmt2), MVT::i8));
14349 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
14350 DAG.getConstant(MulAmt2, VT));
14352 // Do not add new nodes to DAG combiner worklist.
14353 DCI.CombineTo(N, NewMul, false);
14358 static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) {
14359 SDValue N0 = N->getOperand(0);
14360 SDValue N1 = N->getOperand(1);
14361 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
14362 EVT VT = N0.getValueType();
14364 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2))
14365 // since the result of setcc_c is all zero's or all ones.
14366 if (VT.isInteger() && !VT.isVector() &&
14367 N1C && N0.getOpcode() == ISD::AND &&
14368 N0.getOperand(1).getOpcode() == ISD::Constant) {
14369 SDValue N00 = N0.getOperand(0);
14370 if (N00.getOpcode() == X86ISD::SETCC_CARRY ||
14371 ((N00.getOpcode() == ISD::ANY_EXTEND ||
14372 N00.getOpcode() == ISD::ZERO_EXTEND) &&
14373 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY)) {
14374 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
14375 APInt ShAmt = N1C->getAPIntValue();
14376 Mask = Mask.shl(ShAmt);
14378 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
14379 N00, DAG.getConstant(Mask, VT));
14384 // Hardware support for vector shifts is sparse which makes us scalarize the
14385 // vector operations in many cases. Also, on sandybridge ADD is faster than
14387 // (shl V, 1) -> add V,V
14388 if (isSplatVector(N1.getNode())) {
14389 assert(N0.getValueType().isVector() && "Invalid vector shift type");
14390 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1->getOperand(0));
14391 // We shift all of the values by one. In many cases we do not have
14392 // hardware support for this operation. This is better expressed as an ADD
14394 if (N1C && (1 == N1C->getZExtValue())) {
14395 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, N0);
14402 /// PerformShiftCombine - Transforms vector shift nodes to use vector shifts
14404 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
14405 TargetLowering::DAGCombinerInfo &DCI,
14406 const X86Subtarget *Subtarget) {
14407 EVT VT = N->getValueType(0);
14408 if (N->getOpcode() == ISD::SHL) {
14409 SDValue V = PerformSHLCombine(N, DAG);
14410 if (V.getNode()) return V;
14413 // On X86 with SSE2 support, we can transform this to a vector shift if
14414 // all elements are shifted by the same amount. We can't do this in legalize
14415 // because the a constant vector is typically transformed to a constant pool
14416 // so we have no knowledge of the shift amount.
14417 if (!Subtarget->hasSSE2())
14420 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16 &&
14421 (!Subtarget->hasAVX2() ||
14422 (VT != MVT::v4i64 && VT != MVT::v8i32 && VT != MVT::v16i16)))
14425 SDValue ShAmtOp = N->getOperand(1);
14426 EVT EltVT = VT.getVectorElementType();
14427 DebugLoc DL = N->getDebugLoc();
14428 SDValue BaseShAmt = SDValue();
14429 if (ShAmtOp.getOpcode() == ISD::BUILD_VECTOR) {
14430 unsigned NumElts = VT.getVectorNumElements();
14432 for (; i != NumElts; ++i) {
14433 SDValue Arg = ShAmtOp.getOperand(i);
14434 if (Arg.getOpcode() == ISD::UNDEF) continue;
14438 // Handle the case where the build_vector is all undef
14439 // FIXME: Should DAG allow this?
14443 for (; i != NumElts; ++i) {
14444 SDValue Arg = ShAmtOp.getOperand(i);
14445 if (Arg.getOpcode() == ISD::UNDEF) continue;
14446 if (Arg != BaseShAmt) {
14450 } else if (ShAmtOp.getOpcode() == ISD::VECTOR_SHUFFLE &&
14451 cast<ShuffleVectorSDNode>(ShAmtOp)->isSplat()) {
14452 SDValue InVec = ShAmtOp.getOperand(0);
14453 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
14454 unsigned NumElts = InVec.getValueType().getVectorNumElements();
14456 for (; i != NumElts; ++i) {
14457 SDValue Arg = InVec.getOperand(i);
14458 if (Arg.getOpcode() == ISD::UNDEF) continue;
14462 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
14463 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
14464 unsigned SplatIdx= cast<ShuffleVectorSDNode>(ShAmtOp)->getSplatIndex();
14465 if (C->getZExtValue() == SplatIdx)
14466 BaseShAmt = InVec.getOperand(1);
14469 if (BaseShAmt.getNode() == 0) {
14470 // Don't create instructions with illegal types after legalize
14472 if (!DAG.getTargetLoweringInfo().isTypeLegal(EltVT) &&
14473 !DCI.isBeforeLegalize())
14476 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, ShAmtOp,
14477 DAG.getIntPtrConstant(0));
14482 // The shift amount is an i32.
14483 if (EltVT.bitsGT(MVT::i32))
14484 BaseShAmt = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, BaseShAmt);
14485 else if (EltVT.bitsLT(MVT::i32))
14486 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, BaseShAmt);
14488 // The shift amount is identical so we can do a vector shift.
14489 SDValue ValOp = N->getOperand(0);
14490 switch (N->getOpcode()) {
14492 llvm_unreachable("Unknown shift opcode!");
14494 switch (VT.getSimpleVT().SimpleTy) {
14495 default: return SDValue();
14502 return getTargetVShiftNode(X86ISD::VSHLI, DL, VT, ValOp, BaseShAmt, DAG);
14505 switch (VT.getSimpleVT().SimpleTy) {
14506 default: return SDValue();
14511 return getTargetVShiftNode(X86ISD::VSRAI, DL, VT, ValOp, BaseShAmt, DAG);
14514 switch (VT.getSimpleVT().SimpleTy) {
14515 default: return SDValue();
14522 return getTargetVShiftNode(X86ISD::VSRLI, DL, VT, ValOp, BaseShAmt, DAG);
14528 // CMPEQCombine - Recognize the distinctive (AND (setcc ...) (setcc ..))
14529 // where both setccs reference the same FP CMP, and rewrite for CMPEQSS
14530 // and friends. Likewise for OR -> CMPNEQSS.
14531 static SDValue CMPEQCombine(SDNode *N, SelectionDAG &DAG,
14532 TargetLowering::DAGCombinerInfo &DCI,
14533 const X86Subtarget *Subtarget) {
14536 // SSE1 supports CMP{eq|ne}SS, and SSE2 added CMP{eq|ne}SD, but
14537 // we're requiring SSE2 for both.
14538 if (Subtarget->hasSSE2() && isAndOrOfSetCCs(SDValue(N, 0U), opcode)) {
14539 SDValue N0 = N->getOperand(0);
14540 SDValue N1 = N->getOperand(1);
14541 SDValue CMP0 = N0->getOperand(1);
14542 SDValue CMP1 = N1->getOperand(1);
14543 DebugLoc DL = N->getDebugLoc();
14545 // The SETCCs should both refer to the same CMP.
14546 if (CMP0.getOpcode() != X86ISD::CMP || CMP0 != CMP1)
14549 SDValue CMP00 = CMP0->getOperand(0);
14550 SDValue CMP01 = CMP0->getOperand(1);
14551 EVT VT = CMP00.getValueType();
14553 if (VT == MVT::f32 || VT == MVT::f64) {
14554 bool ExpectingFlags = false;
14555 // Check for any users that want flags:
14556 for (SDNode::use_iterator UI = N->use_begin(),
14558 !ExpectingFlags && UI != UE; ++UI)
14559 switch (UI->getOpcode()) {
14564 ExpectingFlags = true;
14566 case ISD::CopyToReg:
14567 case ISD::SIGN_EXTEND:
14568 case ISD::ZERO_EXTEND:
14569 case ISD::ANY_EXTEND:
14573 if (!ExpectingFlags) {
14574 enum X86::CondCode cc0 = (enum X86::CondCode)N0.getConstantOperandVal(0);
14575 enum X86::CondCode cc1 = (enum X86::CondCode)N1.getConstantOperandVal(0);
14577 if (cc1 == X86::COND_E || cc1 == X86::COND_NE) {
14578 X86::CondCode tmp = cc0;
14583 if ((cc0 == X86::COND_E && cc1 == X86::COND_NP) ||
14584 (cc0 == X86::COND_NE && cc1 == X86::COND_P)) {
14585 bool is64BitFP = (CMP00.getValueType() == MVT::f64);
14586 X86ISD::NodeType NTOperator = is64BitFP ?
14587 X86ISD::FSETCCsd : X86ISD::FSETCCss;
14588 // FIXME: need symbolic constants for these magic numbers.
14589 // See X86ATTInstPrinter.cpp:printSSECC().
14590 unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4;
14591 SDValue OnesOrZeroesF = DAG.getNode(NTOperator, DL, MVT::f32, CMP00, CMP01,
14592 DAG.getConstant(x86cc, MVT::i8));
14593 SDValue OnesOrZeroesI = DAG.getNode(ISD::BITCAST, DL, MVT::i32,
14595 SDValue ANDed = DAG.getNode(ISD::AND, DL, MVT::i32, OnesOrZeroesI,
14596 DAG.getConstant(1, MVT::i32));
14597 SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8, ANDed);
14598 return OneBitOfTruth;
14606 /// CanFoldXORWithAllOnes - Test whether the XOR operand is a AllOnes vector
14607 /// so it can be folded inside ANDNP.
14608 static bool CanFoldXORWithAllOnes(const SDNode *N) {
14609 EVT VT = N->getValueType(0);
14611 // Match direct AllOnes for 128 and 256-bit vectors
14612 if (ISD::isBuildVectorAllOnes(N))
14615 // Look through a bit convert.
14616 if (N->getOpcode() == ISD::BITCAST)
14617 N = N->getOperand(0).getNode();
14619 // Sometimes the operand may come from a insert_subvector building a 256-bit
14621 if (VT.is256BitVector() &&
14622 N->getOpcode() == ISD::INSERT_SUBVECTOR) {
14623 SDValue V1 = N->getOperand(0);
14624 SDValue V2 = N->getOperand(1);
14626 if (V1.getOpcode() == ISD::INSERT_SUBVECTOR &&
14627 V1.getOperand(0).getOpcode() == ISD::UNDEF &&
14628 ISD::isBuildVectorAllOnes(V1.getOperand(1).getNode()) &&
14629 ISD::isBuildVectorAllOnes(V2.getNode()))
14636 static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG,
14637 TargetLowering::DAGCombinerInfo &DCI,
14638 const X86Subtarget *Subtarget) {
14639 if (DCI.isBeforeLegalizeOps())
14642 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
14646 EVT VT = N->getValueType(0);
14648 // Create ANDN, BLSI, and BLSR instructions
14649 // BLSI is X & (-X)
14650 // BLSR is X & (X-1)
14651 if (Subtarget->hasBMI() && (VT == MVT::i32 || VT == MVT::i64)) {
14652 SDValue N0 = N->getOperand(0);
14653 SDValue N1 = N->getOperand(1);
14654 DebugLoc DL = N->getDebugLoc();
14656 // Check LHS for not
14657 if (N0.getOpcode() == ISD::XOR && isAllOnes(N0.getOperand(1)))
14658 return DAG.getNode(X86ISD::ANDN, DL, VT, N0.getOperand(0), N1);
14659 // Check RHS for not
14660 if (N1.getOpcode() == ISD::XOR && isAllOnes(N1.getOperand(1)))
14661 return DAG.getNode(X86ISD::ANDN, DL, VT, N1.getOperand(0), N0);
14663 // Check LHS for neg
14664 if (N0.getOpcode() == ISD::SUB && N0.getOperand(1) == N1 &&
14665 isZero(N0.getOperand(0)))
14666 return DAG.getNode(X86ISD::BLSI, DL, VT, N1);
14668 // Check RHS for neg
14669 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1) == N0 &&
14670 isZero(N1.getOperand(0)))
14671 return DAG.getNode(X86ISD::BLSI, DL, VT, N0);
14673 // Check LHS for X-1
14674 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1 &&
14675 isAllOnes(N0.getOperand(1)))
14676 return DAG.getNode(X86ISD::BLSR, DL, VT, N1);
14678 // Check RHS for X-1
14679 if (N1.getOpcode() == ISD::ADD && N1.getOperand(0) == N0 &&
14680 isAllOnes(N1.getOperand(1)))
14681 return DAG.getNode(X86ISD::BLSR, DL, VT, N0);
14686 // Want to form ANDNP nodes:
14687 // 1) In the hopes of then easily combining them with OR and AND nodes
14688 // to form PBLEND/PSIGN.
14689 // 2) To match ANDN packed intrinsics
14690 if (VT != MVT::v2i64 && VT != MVT::v4i64)
14693 SDValue N0 = N->getOperand(0);
14694 SDValue N1 = N->getOperand(1);
14695 DebugLoc DL = N->getDebugLoc();
14697 // Check LHS for vnot
14698 if (N0.getOpcode() == ISD::XOR &&
14699 //ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode()))
14700 CanFoldXORWithAllOnes(N0.getOperand(1).getNode()))
14701 return DAG.getNode(X86ISD::ANDNP, DL, VT, N0.getOperand(0), N1);
14703 // Check RHS for vnot
14704 if (N1.getOpcode() == ISD::XOR &&
14705 //ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode()))
14706 CanFoldXORWithAllOnes(N1.getOperand(1).getNode()))
14707 return DAG.getNode(X86ISD::ANDNP, DL, VT, N1.getOperand(0), N0);
14712 static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
14713 TargetLowering::DAGCombinerInfo &DCI,
14714 const X86Subtarget *Subtarget) {
14715 if (DCI.isBeforeLegalizeOps())
14718 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
14722 EVT VT = N->getValueType(0);
14724 SDValue N0 = N->getOperand(0);
14725 SDValue N1 = N->getOperand(1);
14727 // look for psign/blend
14728 if (VT == MVT::v2i64 || VT == MVT::v4i64) {
14729 if (!Subtarget->hasSSSE3() ||
14730 (VT == MVT::v4i64 && !Subtarget->hasAVX2()))
14733 // Canonicalize pandn to RHS
14734 if (N0.getOpcode() == X86ISD::ANDNP)
14736 // or (and (m, y), (pandn m, x))
14737 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::ANDNP) {
14738 SDValue Mask = N1.getOperand(0);
14739 SDValue X = N1.getOperand(1);
14741 if (N0.getOperand(0) == Mask)
14742 Y = N0.getOperand(1);
14743 if (N0.getOperand(1) == Mask)
14744 Y = N0.getOperand(0);
14746 // Check to see if the mask appeared in both the AND and ANDNP and
14750 // Validate that X, Y, and Mask are BIT_CONVERTS, and see through them.
14751 // Look through mask bitcast.
14752 if (Mask.getOpcode() == ISD::BITCAST)
14753 Mask = Mask.getOperand(0);
14754 if (X.getOpcode() == ISD::BITCAST)
14755 X = X.getOperand(0);
14756 if (Y.getOpcode() == ISD::BITCAST)
14757 Y = Y.getOperand(0);
14759 EVT MaskVT = Mask.getValueType();
14761 // Validate that the Mask operand is a vector sra node.
14762 // FIXME: what to do for bytes, since there is a psignb/pblendvb, but
14763 // there is no psrai.b
14764 if (Mask.getOpcode() != X86ISD::VSRAI)
14767 // Check that the SRA is all signbits.
14768 SDValue SraC = Mask.getOperand(1);
14769 unsigned SraAmt = cast<ConstantSDNode>(SraC)->getZExtValue();
14770 unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits();
14771 if ((SraAmt + 1) != EltBits)
14774 DebugLoc DL = N->getDebugLoc();
14776 // Now we know we at least have a plendvb with the mask val. See if
14777 // we can form a psignb/w/d.
14778 // psign = x.type == y.type == mask.type && y = sub(0, x);
14779 if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X &&
14780 ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) &&
14781 X.getValueType() == MaskVT && Y.getValueType() == MaskVT) {
14782 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
14783 "Unsupported VT for PSIGN");
14784 Mask = DAG.getNode(X86ISD::PSIGN, DL, MaskVT, X, Mask.getOperand(0));
14785 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
14787 // PBLENDVB only available on SSE 4.1
14788 if (!Subtarget->hasSSE41())
14791 EVT BlendVT = (VT == MVT::v4i64) ? MVT::v32i8 : MVT::v16i8;
14793 X = DAG.getNode(ISD::BITCAST, DL, BlendVT, X);
14794 Y = DAG.getNode(ISD::BITCAST, DL, BlendVT, Y);
14795 Mask = DAG.getNode(ISD::BITCAST, DL, BlendVT, Mask);
14796 Mask = DAG.getNode(ISD::VSELECT, DL, BlendVT, Mask, Y, X);
14797 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
14801 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64)
14804 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
14805 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
14807 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
14809 if (!N0.hasOneUse() || !N1.hasOneUse())
14812 SDValue ShAmt0 = N0.getOperand(1);
14813 if (ShAmt0.getValueType() != MVT::i8)
14815 SDValue ShAmt1 = N1.getOperand(1);
14816 if (ShAmt1.getValueType() != MVT::i8)
14818 if (ShAmt0.getOpcode() == ISD::TRUNCATE)
14819 ShAmt0 = ShAmt0.getOperand(0);
14820 if (ShAmt1.getOpcode() == ISD::TRUNCATE)
14821 ShAmt1 = ShAmt1.getOperand(0);
14823 DebugLoc DL = N->getDebugLoc();
14824 unsigned Opc = X86ISD::SHLD;
14825 SDValue Op0 = N0.getOperand(0);
14826 SDValue Op1 = N1.getOperand(0);
14827 if (ShAmt0.getOpcode() == ISD::SUB) {
14828 Opc = X86ISD::SHRD;
14829 std::swap(Op0, Op1);
14830 std::swap(ShAmt0, ShAmt1);
14833 unsigned Bits = VT.getSizeInBits();
14834 if (ShAmt1.getOpcode() == ISD::SUB) {
14835 SDValue Sum = ShAmt1.getOperand(0);
14836 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) {
14837 SDValue ShAmt1Op1 = ShAmt1.getOperand(1);
14838 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE)
14839 ShAmt1Op1 = ShAmt1Op1.getOperand(0);
14840 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0)
14841 return DAG.getNode(Opc, DL, VT,
14843 DAG.getNode(ISD::TRUNCATE, DL,
14846 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) {
14847 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0);
14849 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits)
14850 return DAG.getNode(Opc, DL, VT,
14851 N0.getOperand(0), N1.getOperand(0),
14852 DAG.getNode(ISD::TRUNCATE, DL,
14859 // Generate NEG and CMOV for integer abs.
14860 static SDValue performIntegerAbsCombine(SDNode *N, SelectionDAG &DAG) {
14861 EVT VT = N->getValueType(0);
14863 // Since X86 does not have CMOV for 8-bit integer, we don't convert
14864 // 8-bit integer abs to NEG and CMOV.
14865 if (VT.isInteger() && VT.getSizeInBits() == 8)
14868 SDValue N0 = N->getOperand(0);
14869 SDValue N1 = N->getOperand(1);
14870 DebugLoc DL = N->getDebugLoc();
14872 // Check pattern of XOR(ADD(X,Y), Y) where Y is SRA(X, size(X)-1)
14873 // and change it to SUB and CMOV.
14874 if (VT.isInteger() && N->getOpcode() == ISD::XOR &&
14875 N0.getOpcode() == ISD::ADD &&
14876 N0.getOperand(1) == N1 &&
14877 N1.getOpcode() == ISD::SRA &&
14878 N1.getOperand(0) == N0.getOperand(0))
14879 if (ConstantSDNode *Y1C = dyn_cast<ConstantSDNode>(N1.getOperand(1)))
14880 if (Y1C->getAPIntValue() == VT.getSizeInBits()-1) {
14881 // Generate SUB & CMOV.
14882 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, DAG.getVTList(VT, MVT::i32),
14883 DAG.getConstant(0, VT), N0.getOperand(0));
14885 SDValue Ops[] = { N0.getOperand(0), Neg,
14886 DAG.getConstant(X86::COND_GE, MVT::i8),
14887 SDValue(Neg.getNode(), 1) };
14888 return DAG.getNode(X86ISD::CMOV, DL, DAG.getVTList(VT, MVT::Glue),
14889 Ops, array_lengthof(Ops));
14894 // PerformXorCombine - Attempts to turn XOR nodes into BLSMSK nodes
14895 static SDValue PerformXorCombine(SDNode *N, SelectionDAG &DAG,
14896 TargetLowering::DAGCombinerInfo &DCI,
14897 const X86Subtarget *Subtarget) {
14898 if (DCI.isBeforeLegalizeOps())
14901 if (Subtarget->hasCMov()) {
14902 SDValue RV = performIntegerAbsCombine(N, DAG);
14907 // Try forming BMI if it is available.
14908 if (!Subtarget->hasBMI())
14911 EVT VT = N->getValueType(0);
14913 if (VT != MVT::i32 && VT != MVT::i64)
14916 assert(Subtarget->hasBMI() && "Creating BLSMSK requires BMI instructions");
14918 // Create BLSMSK instructions by finding X ^ (X-1)
14919 SDValue N0 = N->getOperand(0);
14920 SDValue N1 = N->getOperand(1);
14921 DebugLoc DL = N->getDebugLoc();
14923 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1 &&
14924 isAllOnes(N0.getOperand(1)))
14925 return DAG.getNode(X86ISD::BLSMSK, DL, VT, N1);
14927 if (N1.getOpcode() == ISD::ADD && N1.getOperand(0) == N0 &&
14928 isAllOnes(N1.getOperand(1)))
14929 return DAG.getNode(X86ISD::BLSMSK, DL, VT, N0);
14934 /// PerformLOADCombine - Do target-specific dag combines on LOAD nodes.
14935 static SDValue PerformLOADCombine(SDNode *N, SelectionDAG &DAG,
14936 TargetLowering::DAGCombinerInfo &DCI,
14937 const X86Subtarget *Subtarget) {
14938 LoadSDNode *Ld = cast<LoadSDNode>(N);
14939 EVT RegVT = Ld->getValueType(0);
14940 EVT MemVT = Ld->getMemoryVT();
14941 DebugLoc dl = Ld->getDebugLoc();
14942 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14944 ISD::LoadExtType Ext = Ld->getExtensionType();
14946 // If this is a vector EXT Load then attempt to optimize it using a
14947 // shuffle. We need SSE4 for the shuffles.
14948 // TODO: It is possible to support ZExt by zeroing the undef values
14949 // during the shuffle phase or after the shuffle.
14950 if (RegVT.isVector() && RegVT.isInteger() &&
14951 Ext == ISD::EXTLOAD && Subtarget->hasSSE41()) {
14952 assert(MemVT != RegVT && "Cannot extend to the same type");
14953 assert(MemVT.isVector() && "Must load a vector from memory");
14955 unsigned NumElems = RegVT.getVectorNumElements();
14956 unsigned RegSz = RegVT.getSizeInBits();
14957 unsigned MemSz = MemVT.getSizeInBits();
14958 assert(RegSz > MemSz && "Register size must be greater than the mem size");
14960 // All sizes must be a power of two.
14961 if (!isPowerOf2_32(RegSz * MemSz * NumElems))
14964 // Attempt to load the original value using scalar loads.
14965 // Find the largest scalar type that divides the total loaded size.
14966 MVT SclrLoadTy = MVT::i8;
14967 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
14968 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
14969 MVT Tp = (MVT::SimpleValueType)tp;
14970 if (TLI.isTypeLegal(Tp) && ((MemSz % Tp.getSizeInBits()) == 0)) {
14975 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
14976 if (TLI.isTypeLegal(MVT::f64) && SclrLoadTy.getSizeInBits() < 64 &&
14978 SclrLoadTy = MVT::f64;
14980 // Calculate the number of scalar loads that we need to perform
14981 // in order to load our vector from memory.
14982 unsigned NumLoads = MemSz / SclrLoadTy.getSizeInBits();
14984 // Represent our vector as a sequence of elements which are the
14985 // largest scalar that we can load.
14986 EVT LoadUnitVecVT = EVT::getVectorVT(*DAG.getContext(), SclrLoadTy,
14987 RegSz/SclrLoadTy.getSizeInBits());
14989 // Represent the data using the same element type that is stored in
14990 // memory. In practice, we ''widen'' MemVT.
14991 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
14992 RegSz/MemVT.getScalarType().getSizeInBits());
14994 assert(WideVecVT.getSizeInBits() == LoadUnitVecVT.getSizeInBits() &&
14995 "Invalid vector type");
14997 // We can't shuffle using an illegal type.
14998 if (!TLI.isTypeLegal(WideVecVT))
15001 SmallVector<SDValue, 8> Chains;
15002 SDValue Ptr = Ld->getBasePtr();
15003 SDValue Increment = DAG.getConstant(SclrLoadTy.getSizeInBits()/8,
15004 TLI.getPointerTy());
15005 SDValue Res = DAG.getUNDEF(LoadUnitVecVT);
15007 for (unsigned i = 0; i < NumLoads; ++i) {
15008 // Perform a single load.
15009 SDValue ScalarLoad = DAG.getLoad(SclrLoadTy, dl, Ld->getChain(),
15010 Ptr, Ld->getPointerInfo(),
15011 Ld->isVolatile(), Ld->isNonTemporal(),
15012 Ld->isInvariant(), Ld->getAlignment());
15013 Chains.push_back(ScalarLoad.getValue(1));
15014 // Create the first element type using SCALAR_TO_VECTOR in order to avoid
15015 // another round of DAGCombining.
15017 Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LoadUnitVecVT, ScalarLoad);
15019 Res = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, LoadUnitVecVT, Res,
15020 ScalarLoad, DAG.getIntPtrConstant(i));
15022 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
15025 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0],
15028 // Bitcast the loaded value to a vector of the original element type, in
15029 // the size of the target vector type.
15030 SDValue SlicedVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, Res);
15031 unsigned SizeRatio = RegSz/MemSz;
15033 // Redistribute the loaded elements into the different locations.
15034 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
15035 for (unsigned i = 0; i != NumElems; ++i)
15036 ShuffleVec[i*SizeRatio] = i;
15038 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec,
15039 DAG.getUNDEF(WideVecVT),
15042 // Bitcast to the requested type.
15043 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
15044 // Replace the original load with the new sequence
15045 // and return the new chain.
15046 return DCI.CombineTo(N, Shuff, TF, true);
15052 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
15053 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
15054 const X86Subtarget *Subtarget) {
15055 StoreSDNode *St = cast<StoreSDNode>(N);
15056 EVT VT = St->getValue().getValueType();
15057 EVT StVT = St->getMemoryVT();
15058 DebugLoc dl = St->getDebugLoc();
15059 SDValue StoredVal = St->getOperand(1);
15060 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
15062 // If we are saving a concatenation of two XMM registers, perform two stores.
15063 // On Sandy Bridge, 256-bit memory operations are executed by two
15064 // 128-bit ports. However, on Haswell it is better to issue a single 256-bit
15065 // memory operation.
15066 if (VT.is256BitVector() && !Subtarget->hasAVX2() &&
15067 StoredVal.getNode()->getOpcode() == ISD::CONCAT_VECTORS &&
15068 StoredVal.getNumOperands() == 2) {
15069 SDValue Value0 = StoredVal.getOperand(0);
15070 SDValue Value1 = StoredVal.getOperand(1);
15072 SDValue Stride = DAG.getConstant(16, TLI.getPointerTy());
15073 SDValue Ptr0 = St->getBasePtr();
15074 SDValue Ptr1 = DAG.getNode(ISD::ADD, dl, Ptr0.getValueType(), Ptr0, Stride);
15076 SDValue Ch0 = DAG.getStore(St->getChain(), dl, Value0, Ptr0,
15077 St->getPointerInfo(), St->isVolatile(),
15078 St->isNonTemporal(), St->getAlignment());
15079 SDValue Ch1 = DAG.getStore(St->getChain(), dl, Value1, Ptr1,
15080 St->getPointerInfo(), St->isVolatile(),
15081 St->isNonTemporal(), St->getAlignment());
15082 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ch0, Ch1);
15085 // Optimize trunc store (of multiple scalars) to shuffle and store.
15086 // First, pack all of the elements in one place. Next, store to memory
15087 // in fewer chunks.
15088 if (St->isTruncatingStore() && VT.isVector()) {
15089 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
15090 unsigned NumElems = VT.getVectorNumElements();
15091 assert(StVT != VT && "Cannot truncate to the same type");
15092 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
15093 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
15095 // From, To sizes and ElemCount must be pow of two
15096 if (!isPowerOf2_32(NumElems * FromSz * ToSz)) return SDValue();
15097 // We are going to use the original vector elt for storing.
15098 // Accumulated smaller vector elements must be a multiple of the store size.
15099 if (0 != (NumElems * FromSz) % ToSz) return SDValue();
15101 unsigned SizeRatio = FromSz / ToSz;
15103 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
15105 // Create a type on which we perform the shuffle
15106 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
15107 StVT.getScalarType(), NumElems*SizeRatio);
15109 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
15111 SDValue WideVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, St->getValue());
15112 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
15113 for (unsigned i = 0; i != NumElems; ++i)
15114 ShuffleVec[i] = i * SizeRatio;
15116 // Can't shuffle using an illegal type.
15117 if (!TLI.isTypeLegal(WideVecVT))
15120 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
15121 DAG.getUNDEF(WideVecVT),
15123 // At this point all of the data is stored at the bottom of the
15124 // register. We now need to save it to mem.
15126 // Find the largest store unit
15127 MVT StoreType = MVT::i8;
15128 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
15129 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
15130 MVT Tp = (MVT::SimpleValueType)tp;
15131 if (TLI.isTypeLegal(Tp) && Tp.getSizeInBits() <= NumElems * ToSz)
15135 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
15136 if (TLI.isTypeLegal(MVT::f64) && StoreType.getSizeInBits() < 64 &&
15137 (64 <= NumElems * ToSz))
15138 StoreType = MVT::f64;
15140 // Bitcast the original vector into a vector of store-size units
15141 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(),
15142 StoreType, VT.getSizeInBits()/StoreType.getSizeInBits());
15143 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits());
15144 SDValue ShuffWide = DAG.getNode(ISD::BITCAST, dl, StoreVecVT, Shuff);
15145 SmallVector<SDValue, 8> Chains;
15146 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits()/8,
15147 TLI.getPointerTy());
15148 SDValue Ptr = St->getBasePtr();
15150 // Perform one or more big stores into memory.
15151 for (unsigned i=0, e=(ToSz*NumElems)/StoreType.getSizeInBits(); i!=e; ++i) {
15152 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
15153 StoreType, ShuffWide,
15154 DAG.getIntPtrConstant(i));
15155 SDValue Ch = DAG.getStore(St->getChain(), dl, SubVec, Ptr,
15156 St->getPointerInfo(), St->isVolatile(),
15157 St->isNonTemporal(), St->getAlignment());
15158 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
15159 Chains.push_back(Ch);
15162 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0],
15167 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
15168 // the FP state in cases where an emms may be missing.
15169 // A preferable solution to the general problem is to figure out the right
15170 // places to insert EMMS. This qualifies as a quick hack.
15172 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
15173 if (VT.getSizeInBits() != 64)
15176 const Function *F = DAG.getMachineFunction().getFunction();
15177 bool NoImplicitFloatOps = F->hasFnAttr(Attribute::NoImplicitFloat);
15178 bool F64IsLegal = !DAG.getTarget().Options.UseSoftFloat && !NoImplicitFloatOps
15179 && Subtarget->hasSSE2();
15180 if ((VT.isVector() ||
15181 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
15182 isa<LoadSDNode>(St->getValue()) &&
15183 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
15184 St->getChain().hasOneUse() && !St->isVolatile()) {
15185 SDNode* LdVal = St->getValue().getNode();
15186 LoadSDNode *Ld = 0;
15187 int TokenFactorIndex = -1;
15188 SmallVector<SDValue, 8> Ops;
15189 SDNode* ChainVal = St->getChain().getNode();
15190 // Must be a store of a load. We currently handle two cases: the load
15191 // is a direct child, and it's under an intervening TokenFactor. It is
15192 // possible to dig deeper under nested TokenFactors.
15193 if (ChainVal == LdVal)
15194 Ld = cast<LoadSDNode>(St->getChain());
15195 else if (St->getValue().hasOneUse() &&
15196 ChainVal->getOpcode() == ISD::TokenFactor) {
15197 for (unsigned i = 0, e = ChainVal->getNumOperands(); i != e; ++i) {
15198 if (ChainVal->getOperand(i).getNode() == LdVal) {
15199 TokenFactorIndex = i;
15200 Ld = cast<LoadSDNode>(St->getValue());
15202 Ops.push_back(ChainVal->getOperand(i));
15206 if (!Ld || !ISD::isNormalLoad(Ld))
15209 // If this is not the MMX case, i.e. we are just turning i64 load/store
15210 // into f64 load/store, avoid the transformation if there are multiple
15211 // uses of the loaded value.
15212 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
15215 DebugLoc LdDL = Ld->getDebugLoc();
15216 DebugLoc StDL = N->getDebugLoc();
15217 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
15218 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
15220 if (Subtarget->is64Bit() || F64IsLegal) {
15221 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
15222 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(),
15223 Ld->getPointerInfo(), Ld->isVolatile(),
15224 Ld->isNonTemporal(), Ld->isInvariant(),
15225 Ld->getAlignment());
15226 SDValue NewChain = NewLd.getValue(1);
15227 if (TokenFactorIndex != -1) {
15228 Ops.push_back(NewChain);
15229 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
15232 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
15233 St->getPointerInfo(),
15234 St->isVolatile(), St->isNonTemporal(),
15235 St->getAlignment());
15238 // Otherwise, lower to two pairs of 32-bit loads / stores.
15239 SDValue LoAddr = Ld->getBasePtr();
15240 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
15241 DAG.getConstant(4, MVT::i32));
15243 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
15244 Ld->getPointerInfo(),
15245 Ld->isVolatile(), Ld->isNonTemporal(),
15246 Ld->isInvariant(), Ld->getAlignment());
15247 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
15248 Ld->getPointerInfo().getWithOffset(4),
15249 Ld->isVolatile(), Ld->isNonTemporal(),
15251 MinAlign(Ld->getAlignment(), 4));
15253 SDValue NewChain = LoLd.getValue(1);
15254 if (TokenFactorIndex != -1) {
15255 Ops.push_back(LoLd);
15256 Ops.push_back(HiLd);
15257 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
15261 LoAddr = St->getBasePtr();
15262 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
15263 DAG.getConstant(4, MVT::i32));
15265 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
15266 St->getPointerInfo(),
15267 St->isVolatile(), St->isNonTemporal(),
15268 St->getAlignment());
15269 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
15270 St->getPointerInfo().getWithOffset(4),
15272 St->isNonTemporal(),
15273 MinAlign(St->getAlignment(), 4));
15274 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
15279 /// isHorizontalBinOp - Return 'true' if this vector operation is "horizontal"
15280 /// and return the operands for the horizontal operation in LHS and RHS. A
15281 /// horizontal operation performs the binary operation on successive elements
15282 /// of its first operand, then on successive elements of its second operand,
15283 /// returning the resulting values in a vector. For example, if
15284 /// A = < float a0, float a1, float a2, float a3 >
15286 /// B = < float b0, float b1, float b2, float b3 >
15287 /// then the result of doing a horizontal operation on A and B is
15288 /// A horizontal-op B = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >.
15289 /// In short, LHS and RHS are inspected to see if LHS op RHS is of the form
15290 /// A horizontal-op B, for some already available A and B, and if so then LHS is
15291 /// set to A, RHS to B, and the routine returns 'true'.
15292 /// Note that the binary operation should have the property that if one of the
15293 /// operands is UNDEF then the result is UNDEF.
15294 static bool isHorizontalBinOp(SDValue &LHS, SDValue &RHS, bool IsCommutative) {
15295 // Look for the following pattern: if
15296 // A = < float a0, float a1, float a2, float a3 >
15297 // B = < float b0, float b1, float b2, float b3 >
15299 // LHS = VECTOR_SHUFFLE A, B, <0, 2, 4, 6>
15300 // RHS = VECTOR_SHUFFLE A, B, <1, 3, 5, 7>
15301 // then LHS op RHS = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >
15302 // which is A horizontal-op B.
15304 // At least one of the operands should be a vector shuffle.
15305 if (LHS.getOpcode() != ISD::VECTOR_SHUFFLE &&
15306 RHS.getOpcode() != ISD::VECTOR_SHUFFLE)
15309 EVT VT = LHS.getValueType();
15311 assert((VT.is128BitVector() || VT.is256BitVector()) &&
15312 "Unsupported vector type for horizontal add/sub");
15314 // Handle 128 and 256-bit vector lengths. AVX defines horizontal add/sub to
15315 // operate independently on 128-bit lanes.
15316 unsigned NumElts = VT.getVectorNumElements();
15317 unsigned NumLanes = VT.getSizeInBits()/128;
15318 unsigned NumLaneElts = NumElts / NumLanes;
15319 assert((NumLaneElts % 2 == 0) &&
15320 "Vector type should have an even number of elements in each lane");
15321 unsigned HalfLaneElts = NumLaneElts/2;
15323 // View LHS in the form
15324 // LHS = VECTOR_SHUFFLE A, B, LMask
15325 // If LHS is not a shuffle then pretend it is the shuffle
15326 // LHS = VECTOR_SHUFFLE LHS, undef, <0, 1, ..., N-1>
15327 // NOTE: in what follows a default initialized SDValue represents an UNDEF of
15330 SmallVector<int, 16> LMask(NumElts);
15331 if (LHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
15332 if (LHS.getOperand(0).getOpcode() != ISD::UNDEF)
15333 A = LHS.getOperand(0);
15334 if (LHS.getOperand(1).getOpcode() != ISD::UNDEF)
15335 B = LHS.getOperand(1);
15336 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(LHS.getNode())->getMask();
15337 std::copy(Mask.begin(), Mask.end(), LMask.begin());
15339 if (LHS.getOpcode() != ISD::UNDEF)
15341 for (unsigned i = 0; i != NumElts; ++i)
15345 // Likewise, view RHS in the form
15346 // RHS = VECTOR_SHUFFLE C, D, RMask
15348 SmallVector<int, 16> RMask(NumElts);
15349 if (RHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
15350 if (RHS.getOperand(0).getOpcode() != ISD::UNDEF)
15351 C = RHS.getOperand(0);
15352 if (RHS.getOperand(1).getOpcode() != ISD::UNDEF)
15353 D = RHS.getOperand(1);
15354 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(RHS.getNode())->getMask();
15355 std::copy(Mask.begin(), Mask.end(), RMask.begin());
15357 if (RHS.getOpcode() != ISD::UNDEF)
15359 for (unsigned i = 0; i != NumElts; ++i)
15363 // Check that the shuffles are both shuffling the same vectors.
15364 if (!(A == C && B == D) && !(A == D && B == C))
15367 // If everything is UNDEF then bail out: it would be better to fold to UNDEF.
15368 if (!A.getNode() && !B.getNode())
15371 // If A and B occur in reverse order in RHS, then "swap" them (which means
15372 // rewriting the mask).
15374 CommuteVectorShuffleMask(RMask, NumElts);
15376 // At this point LHS and RHS are equivalent to
15377 // LHS = VECTOR_SHUFFLE A, B, LMask
15378 // RHS = VECTOR_SHUFFLE A, B, RMask
15379 // Check that the masks correspond to performing a horizontal operation.
15380 for (unsigned i = 0; i != NumElts; ++i) {
15381 int LIdx = LMask[i], RIdx = RMask[i];
15383 // Ignore any UNDEF components.
15384 if (LIdx < 0 || RIdx < 0 ||
15385 (!A.getNode() && (LIdx < (int)NumElts || RIdx < (int)NumElts)) ||
15386 (!B.getNode() && (LIdx >= (int)NumElts || RIdx >= (int)NumElts)))
15389 // Check that successive elements are being operated on. If not, this is
15390 // not a horizontal operation.
15391 unsigned Src = (i/HalfLaneElts) % 2; // each lane is split between srcs
15392 unsigned LaneStart = (i/NumLaneElts) * NumLaneElts;
15393 int Index = 2*(i%HalfLaneElts) + NumElts*Src + LaneStart;
15394 if (!(LIdx == Index && RIdx == Index + 1) &&
15395 !(IsCommutative && LIdx == Index + 1 && RIdx == Index))
15399 LHS = A.getNode() ? A : B; // If A is 'UNDEF', use B for it.
15400 RHS = B.getNode() ? B : A; // If B is 'UNDEF', use A for it.
15404 /// PerformFADDCombine - Do target-specific dag combines on floating point adds.
15405 static SDValue PerformFADDCombine(SDNode *N, SelectionDAG &DAG,
15406 const X86Subtarget *Subtarget) {
15407 EVT VT = N->getValueType(0);
15408 SDValue LHS = N->getOperand(0);
15409 SDValue RHS = N->getOperand(1);
15411 // Try to synthesize horizontal adds from adds of shuffles.
15412 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
15413 (Subtarget->hasAVX() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
15414 isHorizontalBinOp(LHS, RHS, true))
15415 return DAG.getNode(X86ISD::FHADD, N->getDebugLoc(), VT, LHS, RHS);
15419 /// PerformFSUBCombine - Do target-specific dag combines on floating point subs.
15420 static SDValue PerformFSUBCombine(SDNode *N, SelectionDAG &DAG,
15421 const X86Subtarget *Subtarget) {
15422 EVT VT = N->getValueType(0);
15423 SDValue LHS = N->getOperand(0);
15424 SDValue RHS = N->getOperand(1);
15426 // Try to synthesize horizontal subs from subs of shuffles.
15427 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
15428 (Subtarget->hasAVX() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
15429 isHorizontalBinOp(LHS, RHS, false))
15430 return DAG.getNode(X86ISD::FHSUB, N->getDebugLoc(), VT, LHS, RHS);
15434 /// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and
15435 /// X86ISD::FXOR nodes.
15436 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
15437 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
15438 // F[X]OR(0.0, x) -> x
15439 // F[X]OR(x, 0.0) -> x
15440 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
15441 if (C->getValueAPF().isPosZero())
15442 return N->getOperand(1);
15443 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
15444 if (C->getValueAPF().isPosZero())
15445 return N->getOperand(0);
15449 /// PerformFMinFMaxCombine - Do target-specific dag combines on X86ISD::FMIN and
15450 /// X86ISD::FMAX nodes.
15451 static SDValue PerformFMinFMaxCombine(SDNode *N, SelectionDAG &DAG) {
15452 assert(N->getOpcode() == X86ISD::FMIN || N->getOpcode() == X86ISD::FMAX);
15454 // Only perform optimizations if UnsafeMath is used.
15455 if (!DAG.getTarget().Options.UnsafeFPMath)
15458 // If we run in unsafe-math mode, then convert the FMAX and FMIN nodes
15459 // into FMINC and MMAXC, which are Commutative operations.
15460 unsigned NewOp = 0;
15461 switch (N->getOpcode()) {
15462 default: llvm_unreachable("unknown opcode");
15463 case X86ISD::FMIN: NewOp = X86ISD::FMINC; break;
15464 case X86ISD::FMAX: NewOp = X86ISD::FMAXC; break;
15467 return DAG.getNode(NewOp, N->getDebugLoc(), N->getValueType(0),
15468 N->getOperand(0), N->getOperand(1));
15472 /// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes.
15473 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
15474 // FAND(0.0, x) -> 0.0
15475 // FAND(x, 0.0) -> 0.0
15476 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
15477 if (C->getValueAPF().isPosZero())
15478 return N->getOperand(0);
15479 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
15480 if (C->getValueAPF().isPosZero())
15481 return N->getOperand(1);
15485 static SDValue PerformBTCombine(SDNode *N,
15487 TargetLowering::DAGCombinerInfo &DCI) {
15488 // BT ignores high bits in the bit index operand.
15489 SDValue Op1 = N->getOperand(1);
15490 if (Op1.hasOneUse()) {
15491 unsigned BitWidth = Op1.getValueSizeInBits();
15492 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
15493 APInt KnownZero, KnownOne;
15494 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
15495 !DCI.isBeforeLegalizeOps());
15496 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
15497 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
15498 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
15499 DCI.CommitTargetLoweringOpt(TLO);
15504 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
15505 SDValue Op = N->getOperand(0);
15506 if (Op.getOpcode() == ISD::BITCAST)
15507 Op = Op.getOperand(0);
15508 EVT VT = N->getValueType(0), OpVT = Op.getValueType();
15509 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
15510 VT.getVectorElementType().getSizeInBits() ==
15511 OpVT.getVectorElementType().getSizeInBits()) {
15512 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), VT, Op);
15517 static SDValue PerformSExtCombine(SDNode *N, SelectionDAG &DAG,
15518 TargetLowering::DAGCombinerInfo &DCI,
15519 const X86Subtarget *Subtarget) {
15520 if (!DCI.isBeforeLegalizeOps())
15523 if (!Subtarget->hasAVX())
15526 EVT VT = N->getValueType(0);
15527 SDValue Op = N->getOperand(0);
15528 EVT OpVT = Op.getValueType();
15529 DebugLoc dl = N->getDebugLoc();
15531 if ((VT == MVT::v4i64 && OpVT == MVT::v4i32) ||
15532 (VT == MVT::v8i32 && OpVT == MVT::v8i16)) {
15534 if (Subtarget->hasAVX2())
15535 return DAG.getNode(X86ISD::VSEXT_MOVL, dl, VT, Op);
15537 // Optimize vectors in AVX mode
15538 // Sign extend v8i16 to v8i32 and
15541 // Divide input vector into two parts
15542 // for v4i32 the shuffle mask will be { 0, 1, -1, -1} {2, 3, -1, -1}
15543 // use vpmovsx instruction to extend v4i32 -> v2i64; v8i16 -> v4i32
15544 // concat the vectors to original VT
15546 unsigned NumElems = OpVT.getVectorNumElements();
15547 SDValue Undef = DAG.getUNDEF(OpVT);
15549 SmallVector<int,8> ShufMask1(NumElems, -1);
15550 for (unsigned i = 0; i != NumElems/2; ++i)
15553 SDValue OpLo = DAG.getVectorShuffle(OpVT, dl, Op, Undef, &ShufMask1[0]);
15555 SmallVector<int,8> ShufMask2(NumElems, -1);
15556 for (unsigned i = 0; i != NumElems/2; ++i)
15557 ShufMask2[i] = i + NumElems/2;
15559 SDValue OpHi = DAG.getVectorShuffle(OpVT, dl, Op, Undef, &ShufMask2[0]);
15561 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), VT.getScalarType(),
15562 VT.getVectorNumElements()/2);
15564 OpLo = DAG.getNode(X86ISD::VSEXT_MOVL, dl, HalfVT, OpLo);
15565 OpHi = DAG.getNode(X86ISD::VSEXT_MOVL, dl, HalfVT, OpHi);
15567 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
15572 static SDValue PerformFMACombine(SDNode *N, SelectionDAG &DAG,
15573 const X86Subtarget* Subtarget) {
15574 DebugLoc dl = N->getDebugLoc();
15575 EVT VT = N->getValueType(0);
15577 EVT ScalarVT = VT.getScalarType();
15578 if ((ScalarVT != MVT::f32 && ScalarVT != MVT::f64) || !Subtarget->hasFMA())
15581 SDValue A = N->getOperand(0);
15582 SDValue B = N->getOperand(1);
15583 SDValue C = N->getOperand(2);
15585 bool NegA = (A.getOpcode() == ISD::FNEG);
15586 bool NegB = (B.getOpcode() == ISD::FNEG);
15587 bool NegC = (C.getOpcode() == ISD::FNEG);
15589 // Negative multiplication when NegA xor NegB
15590 bool NegMul = (NegA != NegB);
15592 A = A.getOperand(0);
15594 B = B.getOperand(0);
15596 C = C.getOperand(0);
15600 Opcode = (!NegC)? X86ISD::FMADD : X86ISD::FMSUB;
15602 Opcode = (!NegC)? X86ISD::FNMADD : X86ISD::FNMSUB;
15603 return DAG.getNode(Opcode, dl, VT, A, B, C);
15606 static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG,
15607 TargetLowering::DAGCombinerInfo &DCI,
15608 const X86Subtarget *Subtarget) {
15609 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) ->
15610 // (and (i32 x86isd::setcc_carry), 1)
15611 // This eliminates the zext. This transformation is necessary because
15612 // ISD::SETCC is always legalized to i8.
15613 DebugLoc dl = N->getDebugLoc();
15614 SDValue N0 = N->getOperand(0);
15615 EVT VT = N->getValueType(0);
15616 EVT OpVT = N0.getValueType();
15618 if (N0.getOpcode() == ISD::AND &&
15620 N0.getOperand(0).hasOneUse()) {
15621 SDValue N00 = N0.getOperand(0);
15622 if (N00.getOpcode() != X86ISD::SETCC_CARRY)
15624 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
15625 if (!C || C->getZExtValue() != 1)
15627 return DAG.getNode(ISD::AND, dl, VT,
15628 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
15629 N00.getOperand(0), N00.getOperand(1)),
15630 DAG.getConstant(1, VT));
15633 // Optimize vectors in AVX mode:
15636 // Use vpunpcklwd for 4 lower elements v8i16 -> v4i32.
15637 // Use vpunpckhwd for 4 upper elements v8i16 -> v4i32.
15638 // Concat upper and lower parts.
15641 // Use vpunpckldq for 4 lower elements v4i32 -> v2i64.
15642 // Use vpunpckhdq for 4 upper elements v4i32 -> v2i64.
15643 // Concat upper and lower parts.
15645 if (!DCI.isBeforeLegalizeOps())
15648 if (!Subtarget->hasAVX())
15651 if (((VT == MVT::v8i32) && (OpVT == MVT::v8i16)) ||
15652 ((VT == MVT::v4i64) && (OpVT == MVT::v4i32))) {
15654 if (Subtarget->hasAVX2())
15655 return DAG.getNode(X86ISD::VZEXT_MOVL, dl, VT, N0);
15657 SDValue ZeroVec = getZeroVector(OpVT, Subtarget, DAG, dl);
15658 SDValue OpLo = getUnpackl(DAG, dl, OpVT, N0, ZeroVec);
15659 SDValue OpHi = getUnpackh(DAG, dl, OpVT, N0, ZeroVec);
15661 EVT HVT = EVT::getVectorVT(*DAG.getContext(), VT.getVectorElementType(),
15662 VT.getVectorNumElements()/2);
15664 OpLo = DAG.getNode(ISD::BITCAST, dl, HVT, OpLo);
15665 OpHi = DAG.getNode(ISD::BITCAST, dl, HVT, OpHi);
15667 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
15673 // Optimize x == -y --> x+y == 0
15674 // x != -y --> x+y != 0
15675 static SDValue PerformISDSETCCCombine(SDNode *N, SelectionDAG &DAG) {
15676 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
15677 SDValue LHS = N->getOperand(0);
15678 SDValue RHS = N->getOperand(1);
15680 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && LHS.getOpcode() == ISD::SUB)
15681 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(LHS.getOperand(0)))
15682 if (C->getAPIntValue() == 0 && LHS.hasOneUse()) {
15683 SDValue addV = DAG.getNode(ISD::ADD, N->getDebugLoc(),
15684 LHS.getValueType(), RHS, LHS.getOperand(1));
15685 return DAG.getSetCC(N->getDebugLoc(), N->getValueType(0),
15686 addV, DAG.getConstant(0, addV.getValueType()), CC);
15688 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && RHS.getOpcode() == ISD::SUB)
15689 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS.getOperand(0)))
15690 if (C->getAPIntValue() == 0 && RHS.hasOneUse()) {
15691 SDValue addV = DAG.getNode(ISD::ADD, N->getDebugLoc(),
15692 RHS.getValueType(), LHS, RHS.getOperand(1));
15693 return DAG.getSetCC(N->getDebugLoc(), N->getValueType(0),
15694 addV, DAG.getConstant(0, addV.getValueType()), CC);
15699 // Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT
15700 static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG) {
15701 DebugLoc DL = N->getDebugLoc();
15702 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(0));
15703 SDValue EFLAGS = N->getOperand(1);
15705 // Materialize "setb reg" as "sbb reg,reg", since it can be extended without
15706 // a zext and produces an all-ones bit which is more useful than 0/1 in some
15708 if (CC == X86::COND_B)
15709 return DAG.getNode(ISD::AND, DL, MVT::i8,
15710 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
15711 DAG.getConstant(CC, MVT::i8), EFLAGS),
15712 DAG.getConstant(1, MVT::i8));
15716 Flags = BoolTestSetCCCombine(EFLAGS, CC);
15717 if (Flags.getNode()) {
15718 SDValue Cond = DAG.getConstant(CC, MVT::i8);
15719 return DAG.getNode(X86ISD::SETCC, DL, N->getVTList(), Cond, Flags);
15725 // Optimize branch condition evaluation.
15727 static SDValue PerformBrCondCombine(SDNode *N, SelectionDAG &DAG,
15728 TargetLowering::DAGCombinerInfo &DCI,
15729 const X86Subtarget *Subtarget) {
15730 DebugLoc DL = N->getDebugLoc();
15731 SDValue Chain = N->getOperand(0);
15732 SDValue Dest = N->getOperand(1);
15733 SDValue EFLAGS = N->getOperand(3);
15734 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(2));
15738 Flags = BoolTestSetCCCombine(EFLAGS, CC);
15739 if (Flags.getNode()) {
15740 SDValue Cond = DAG.getConstant(CC, MVT::i8);
15741 return DAG.getNode(X86ISD::BRCOND, DL, N->getVTList(), Chain, Dest, Cond,
15748 static SDValue PerformUINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG) {
15749 SDValue Op0 = N->getOperand(0);
15750 EVT InVT = Op0->getValueType(0);
15752 // UINT_TO_FP(v4i8) -> SINT_TO_FP(ZEXT(v4i8 to v4i32))
15753 if (InVT == MVT::v8i8 || InVT == MVT::v4i8) {
15754 DebugLoc dl = N->getDebugLoc();
15755 MVT DstVT = InVT == MVT::v4i8 ? MVT::v4i32 : MVT::v8i32;
15756 SDValue P = DAG.getNode(ISD::ZERO_EXTEND, dl, DstVT, Op0);
15757 // Notice that we use SINT_TO_FP because we know that the high bits
15758 // are zero and SINT_TO_FP is better supported by the hardware.
15759 return DAG.getNode(ISD::SINT_TO_FP, dl, N->getValueType(0), P);
15765 static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
15766 const X86TargetLowering *XTLI) {
15767 SDValue Op0 = N->getOperand(0);
15768 EVT InVT = Op0->getValueType(0);
15770 // SINT_TO_FP(v4i8) -> SINT_TO_FP(SEXT(v4i8 to v4i32))
15771 if (InVT == MVT::v8i8 || InVT == MVT::v4i8) {
15772 DebugLoc dl = N->getDebugLoc();
15773 MVT DstVT = InVT == MVT::v4i8 ? MVT::v4i32 : MVT::v8i32;
15774 SDValue P = DAG.getNode(ISD::SIGN_EXTEND, dl, DstVT, Op0);
15775 return DAG.getNode(ISD::SINT_TO_FP, dl, N->getValueType(0), P);
15778 // Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have
15779 // a 32-bit target where SSE doesn't support i64->FP operations.
15780 if (Op0.getOpcode() == ISD::LOAD) {
15781 LoadSDNode *Ld = cast<LoadSDNode>(Op0.getNode());
15782 EVT VT = Ld->getValueType(0);
15783 if (!Ld->isVolatile() && !N->getValueType(0).isVector() &&
15784 ISD::isNON_EXTLoad(Op0.getNode()) && Op0.hasOneUse() &&
15785 !XTLI->getSubtarget()->is64Bit() &&
15786 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
15787 SDValue FILDChain = XTLI->BuildFILD(SDValue(N, 0), Ld->getValueType(0),
15788 Ld->getChain(), Op0, DAG);
15789 DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), FILDChain.getValue(1));
15796 static SDValue PerformFP_TO_SINTCombine(SDNode *N, SelectionDAG &DAG) {
15797 EVT VT = N->getValueType(0);
15799 // v4i8 = FP_TO_SINT() -> v4i8 = TRUNCATE (V4i32 = FP_TO_SINT()
15800 if (VT == MVT::v8i8 || VT == MVT::v4i8) {
15801 DebugLoc dl = N->getDebugLoc();
15802 MVT DstVT = VT == MVT::v4i8 ? MVT::v4i32 : MVT::v8i32;
15803 SDValue I = DAG.getNode(ISD::FP_TO_SINT, dl, DstVT, N->getOperand(0));
15804 return DAG.getNode(ISD::TRUNCATE, dl, VT, I);
15810 // Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS
15811 static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG,
15812 X86TargetLowering::DAGCombinerInfo &DCI) {
15813 // If the LHS and RHS of the ADC node are zero, then it can't overflow and
15814 // the result is either zero or one (depending on the input carry bit).
15815 // Strength reduce this down to a "set on carry" aka SETCC_CARRY&1.
15816 if (X86::isZeroNode(N->getOperand(0)) &&
15817 X86::isZeroNode(N->getOperand(1)) &&
15818 // We don't have a good way to replace an EFLAGS use, so only do this when
15820 SDValue(N, 1).use_empty()) {
15821 DebugLoc DL = N->getDebugLoc();
15822 EVT VT = N->getValueType(0);
15823 SDValue CarryOut = DAG.getConstant(0, N->getValueType(1));
15824 SDValue Res1 = DAG.getNode(ISD::AND, DL, VT,
15825 DAG.getNode(X86ISD::SETCC_CARRY, DL, VT,
15826 DAG.getConstant(X86::COND_B,MVT::i8),
15828 DAG.getConstant(1, VT));
15829 return DCI.CombineTo(N, Res1, CarryOut);
15835 // fold (add Y, (sete X, 0)) -> adc 0, Y
15836 // (add Y, (setne X, 0)) -> sbb -1, Y
15837 // (sub (sete X, 0), Y) -> sbb 0, Y
15838 // (sub (setne X, 0), Y) -> adc -1, Y
15839 static SDValue OptimizeConditionalInDecrement(SDNode *N, SelectionDAG &DAG) {
15840 DebugLoc DL = N->getDebugLoc();
15842 // Look through ZExts.
15843 SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0);
15844 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse())
15847 SDValue SetCC = Ext.getOperand(0);
15848 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse())
15851 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0);
15852 if (CC != X86::COND_E && CC != X86::COND_NE)
15855 SDValue Cmp = SetCC.getOperand(1);
15856 if (Cmp.getOpcode() != X86ISD::CMP || !Cmp.hasOneUse() ||
15857 !X86::isZeroNode(Cmp.getOperand(1)) ||
15858 !Cmp.getOperand(0).getValueType().isInteger())
15861 SDValue CmpOp0 = Cmp.getOperand(0);
15862 SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, CmpOp0,
15863 DAG.getConstant(1, CmpOp0.getValueType()));
15865 SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1);
15866 if (CC == X86::COND_NE)
15867 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB,
15868 DL, OtherVal.getValueType(), OtherVal,
15869 DAG.getConstant(-1ULL, OtherVal.getValueType()), NewCmp);
15870 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC,
15871 DL, OtherVal.getValueType(), OtherVal,
15872 DAG.getConstant(0, OtherVal.getValueType()), NewCmp);
15875 /// PerformADDCombine - Do target-specific dag combines on integer adds.
15876 static SDValue PerformAddCombine(SDNode *N, SelectionDAG &DAG,
15877 const X86Subtarget *Subtarget) {
15878 EVT VT = N->getValueType(0);
15879 SDValue Op0 = N->getOperand(0);
15880 SDValue Op1 = N->getOperand(1);
15882 // Try to synthesize horizontal adds from adds of shuffles.
15883 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
15884 (Subtarget->hasAVX2() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
15885 isHorizontalBinOp(Op0, Op1, true))
15886 return DAG.getNode(X86ISD::HADD, N->getDebugLoc(), VT, Op0, Op1);
15888 return OptimizeConditionalInDecrement(N, DAG);
15891 static SDValue PerformSubCombine(SDNode *N, SelectionDAG &DAG,
15892 const X86Subtarget *Subtarget) {
15893 SDValue Op0 = N->getOperand(0);
15894 SDValue Op1 = N->getOperand(1);
15896 // X86 can't encode an immediate LHS of a sub. See if we can push the
15897 // negation into a preceding instruction.
15898 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op0)) {
15899 // If the RHS of the sub is a XOR with one use and a constant, invert the
15900 // immediate. Then add one to the LHS of the sub so we can turn
15901 // X-Y -> X+~Y+1, saving one register.
15902 if (Op1->hasOneUse() && Op1.getOpcode() == ISD::XOR &&
15903 isa<ConstantSDNode>(Op1.getOperand(1))) {
15904 APInt XorC = cast<ConstantSDNode>(Op1.getOperand(1))->getAPIntValue();
15905 EVT VT = Op0.getValueType();
15906 SDValue NewXor = DAG.getNode(ISD::XOR, Op1.getDebugLoc(), VT,
15908 DAG.getConstant(~XorC, VT));
15909 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, NewXor,
15910 DAG.getConstant(C->getAPIntValue()+1, VT));
15914 // Try to synthesize horizontal adds from adds of shuffles.
15915 EVT VT = N->getValueType(0);
15916 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
15917 (Subtarget->hasAVX2() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
15918 isHorizontalBinOp(Op0, Op1, true))
15919 return DAG.getNode(X86ISD::HSUB, N->getDebugLoc(), VT, Op0, Op1);
15921 return OptimizeConditionalInDecrement(N, DAG);
15924 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
15925 DAGCombinerInfo &DCI) const {
15926 SelectionDAG &DAG = DCI.DAG;
15927 switch (N->getOpcode()) {
15929 case ISD::EXTRACT_VECTOR_ELT:
15930 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, DCI);
15932 case ISD::SELECT: return PerformSELECTCombine(N, DAG, DCI, Subtarget);
15933 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI);
15934 case ISD::ADD: return PerformAddCombine(N, DAG, Subtarget);
15935 case ISD::SUB: return PerformSubCombine(N, DAG, Subtarget);
15936 case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI);
15937 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
15940 case ISD::SRL: return PerformShiftCombine(N, DAG, DCI, Subtarget);
15941 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget);
15942 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget);
15943 case ISD::XOR: return PerformXorCombine(N, DAG, DCI, Subtarget);
15944 case ISD::LOAD: return PerformLOADCombine(N, DAG, DCI, Subtarget);
15945 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
15946 case ISD::UINT_TO_FP: return PerformUINT_TO_FPCombine(N, DAG);
15947 case ISD::SINT_TO_FP: return PerformSINT_TO_FPCombine(N, DAG, this);
15948 case ISD::FP_TO_SINT: return PerformFP_TO_SINTCombine(N, DAG);
15949 case ISD::FADD: return PerformFADDCombine(N, DAG, Subtarget);
15950 case ISD::FSUB: return PerformFSUBCombine(N, DAG, Subtarget);
15952 case X86ISD::FOR: return PerformFORCombine(N, DAG);
15954 case X86ISD::FMAX: return PerformFMinFMaxCombine(N, DAG);
15955 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
15956 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
15957 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
15958 case ISD::ANY_EXTEND:
15959 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG, DCI, Subtarget);
15960 case ISD::SIGN_EXTEND: return PerformSExtCombine(N, DAG, DCI, Subtarget);
15961 case ISD::TRUNCATE: return PerformTruncateCombine(N, DAG, DCI);
15962 case ISD::SETCC: return PerformISDSETCCCombine(N, DAG);
15963 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG);
15964 case X86ISD::BRCOND: return PerformBrCondCombine(N, DAG, DCI, Subtarget);
15965 case X86ISD::SHUFP: // Handle all target specific shuffles
15966 case X86ISD::PALIGN:
15967 case X86ISD::UNPCKH:
15968 case X86ISD::UNPCKL:
15969 case X86ISD::MOVHLPS:
15970 case X86ISD::MOVLHPS:
15971 case X86ISD::PSHUFD:
15972 case X86ISD::PSHUFHW:
15973 case X86ISD::PSHUFLW:
15974 case X86ISD::MOVSS:
15975 case X86ISD::MOVSD:
15976 case X86ISD::VPERMILP:
15977 case X86ISD::VPERM2X128:
15978 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget);
15979 case ISD::FMA: return PerformFMACombine(N, DAG, Subtarget);
15985 /// isTypeDesirableForOp - Return true if the target has native support for
15986 /// the specified value type and it is 'desirable' to use the type for the
15987 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
15988 /// instruction encodings are longer and some i16 instructions are slow.
15989 bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const {
15990 if (!isTypeLegal(VT))
15992 if (VT != MVT::i16)
15999 case ISD::SIGN_EXTEND:
16000 case ISD::ZERO_EXTEND:
16001 case ISD::ANY_EXTEND:
16014 /// IsDesirableToPromoteOp - This method query the target whether it is
16015 /// beneficial for dag combiner to promote the specified node. If true, it
16016 /// should return the desired promotion type by reference.
16017 bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
16018 EVT VT = Op.getValueType();
16019 if (VT != MVT::i16)
16022 bool Promote = false;
16023 bool Commute = false;
16024 switch (Op.getOpcode()) {
16027 LoadSDNode *LD = cast<LoadSDNode>(Op);
16028 // If the non-extending load has a single use and it's not live out, then it
16029 // might be folded.
16030 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&&
16031 Op.hasOneUse()*/) {
16032 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
16033 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
16034 // The only case where we'd want to promote LOAD (rather then it being
16035 // promoted as an operand is when it's only use is liveout.
16036 if (UI->getOpcode() != ISD::CopyToReg)
16043 case ISD::SIGN_EXTEND:
16044 case ISD::ZERO_EXTEND:
16045 case ISD::ANY_EXTEND:
16050 SDValue N0 = Op.getOperand(0);
16051 // Look out for (store (shl (load), x)).
16052 if (MayFoldLoad(N0) && MayFoldIntoStore(Op))
16065 SDValue N0 = Op.getOperand(0);
16066 SDValue N1 = Op.getOperand(1);
16067 if (!Commute && MayFoldLoad(N1))
16069 // Avoid disabling potential load folding opportunities.
16070 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op)))
16072 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op)))
16082 //===----------------------------------------------------------------------===//
16083 // X86 Inline Assembly Support
16084 //===----------------------------------------------------------------------===//
16087 // Helper to match a string separated by whitespace.
16088 bool matchAsmImpl(StringRef s, ArrayRef<const StringRef *> args) {
16089 s = s.substr(s.find_first_not_of(" \t")); // Skip leading whitespace.
16091 for (unsigned i = 0, e = args.size(); i != e; ++i) {
16092 StringRef piece(*args[i]);
16093 if (!s.startswith(piece)) // Check if the piece matches.
16096 s = s.substr(piece.size());
16097 StringRef::size_type pos = s.find_first_not_of(" \t");
16098 if (pos == 0) // We matched a prefix.
16106 const VariadicFunction1<bool, StringRef, StringRef, matchAsmImpl> matchAsm={};
16109 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
16110 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
16112 std::string AsmStr = IA->getAsmString();
16114 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
16115 if (!Ty || Ty->getBitWidth() % 16 != 0)
16118 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
16119 SmallVector<StringRef, 4> AsmPieces;
16120 SplitString(AsmStr, AsmPieces, ";\n");
16122 switch (AsmPieces.size()) {
16123 default: return false;
16125 // FIXME: this should verify that we are targeting a 486 or better. If not,
16126 // we will turn this bswap into something that will be lowered to logical
16127 // ops instead of emitting the bswap asm. For now, we don't support 486 or
16128 // lower so don't worry about this.
16130 if (matchAsm(AsmPieces[0], "bswap", "$0") ||
16131 matchAsm(AsmPieces[0], "bswapl", "$0") ||
16132 matchAsm(AsmPieces[0], "bswapq", "$0") ||
16133 matchAsm(AsmPieces[0], "bswap", "${0:q}") ||
16134 matchAsm(AsmPieces[0], "bswapl", "${0:q}") ||
16135 matchAsm(AsmPieces[0], "bswapq", "${0:q}")) {
16136 // No need to check constraints, nothing other than the equivalent of
16137 // "=r,0" would be valid here.
16138 return IntrinsicLowering::LowerToByteSwap(CI);
16141 // rorw $$8, ${0:w} --> llvm.bswap.i16
16142 if (CI->getType()->isIntegerTy(16) &&
16143 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
16144 (matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") ||
16145 matchAsm(AsmPieces[0], "rolw", "$$8,", "${0:w}"))) {
16147 const std::string &ConstraintsStr = IA->getConstraintString();
16148 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
16149 std::sort(AsmPieces.begin(), AsmPieces.end());
16150 if (AsmPieces.size() == 4 &&
16151 AsmPieces[0] == "~{cc}" &&
16152 AsmPieces[1] == "~{dirflag}" &&
16153 AsmPieces[2] == "~{flags}" &&
16154 AsmPieces[3] == "~{fpsr}")
16155 return IntrinsicLowering::LowerToByteSwap(CI);
16159 if (CI->getType()->isIntegerTy(32) &&
16160 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
16161 matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") &&
16162 matchAsm(AsmPieces[1], "rorl", "$$16,", "$0") &&
16163 matchAsm(AsmPieces[2], "rorw", "$$8,", "${0:w}")) {
16165 const std::string &ConstraintsStr = IA->getConstraintString();
16166 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
16167 std::sort(AsmPieces.begin(), AsmPieces.end());
16168 if (AsmPieces.size() == 4 &&
16169 AsmPieces[0] == "~{cc}" &&
16170 AsmPieces[1] == "~{dirflag}" &&
16171 AsmPieces[2] == "~{flags}" &&
16172 AsmPieces[3] == "~{fpsr}")
16173 return IntrinsicLowering::LowerToByteSwap(CI);
16176 if (CI->getType()->isIntegerTy(64)) {
16177 InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints();
16178 if (Constraints.size() >= 2 &&
16179 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
16180 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
16181 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
16182 if (matchAsm(AsmPieces[0], "bswap", "%eax") &&
16183 matchAsm(AsmPieces[1], "bswap", "%edx") &&
16184 matchAsm(AsmPieces[2], "xchgl", "%eax,", "%edx"))
16185 return IntrinsicLowering::LowerToByteSwap(CI);
16195 /// getConstraintType - Given a constraint letter, return the type of
16196 /// constraint it is for this target.
16197 X86TargetLowering::ConstraintType
16198 X86TargetLowering::getConstraintType(const std::string &Constraint) const {
16199 if (Constraint.size() == 1) {
16200 switch (Constraint[0]) {
16211 return C_RegisterClass;
16235 return TargetLowering::getConstraintType(Constraint);
16238 /// Examine constraint type and operand type and determine a weight value.
16239 /// This object must already have been set up with the operand type
16240 /// and the current alternative constraint selected.
16241 TargetLowering::ConstraintWeight
16242 X86TargetLowering::getSingleConstraintMatchWeight(
16243 AsmOperandInfo &info, const char *constraint) const {
16244 ConstraintWeight weight = CW_Invalid;
16245 Value *CallOperandVal = info.CallOperandVal;
16246 // If we don't have a value, we can't do a match,
16247 // but allow it at the lowest weight.
16248 if (CallOperandVal == NULL)
16250 Type *type = CallOperandVal->getType();
16251 // Look at the constraint type.
16252 switch (*constraint) {
16254 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
16265 if (CallOperandVal->getType()->isIntegerTy())
16266 weight = CW_SpecificReg;
16271 if (type->isFloatingPointTy())
16272 weight = CW_SpecificReg;
16275 if (type->isX86_MMXTy() && Subtarget->hasMMX())
16276 weight = CW_SpecificReg;
16280 if (((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasSSE1()) ||
16281 ((type->getPrimitiveSizeInBits() == 256) && Subtarget->hasAVX()))
16282 weight = CW_Register;
16285 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) {
16286 if (C->getZExtValue() <= 31)
16287 weight = CW_Constant;
16291 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
16292 if (C->getZExtValue() <= 63)
16293 weight = CW_Constant;
16297 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
16298 if ((C->getSExtValue() >= -0x80) && (C->getSExtValue() <= 0x7f))
16299 weight = CW_Constant;
16303 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
16304 if ((C->getZExtValue() == 0xff) || (C->getZExtValue() == 0xffff))
16305 weight = CW_Constant;
16309 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
16310 if (C->getZExtValue() <= 3)
16311 weight = CW_Constant;
16315 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
16316 if (C->getZExtValue() <= 0xff)
16317 weight = CW_Constant;
16322 if (dyn_cast<ConstantFP>(CallOperandVal)) {
16323 weight = CW_Constant;
16327 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
16328 if ((C->getSExtValue() >= -0x80000000LL) &&
16329 (C->getSExtValue() <= 0x7fffffffLL))
16330 weight = CW_Constant;
16334 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
16335 if (C->getZExtValue() <= 0xffffffff)
16336 weight = CW_Constant;
16343 /// LowerXConstraint - try to replace an X constraint, which matches anything,
16344 /// with another that has more specific requirements based on the type of the
16345 /// corresponding operand.
16346 const char *X86TargetLowering::
16347 LowerXConstraint(EVT ConstraintVT) const {
16348 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
16349 // 'f' like normal targets.
16350 if (ConstraintVT.isFloatingPoint()) {
16351 if (Subtarget->hasSSE2())
16353 if (Subtarget->hasSSE1())
16357 return TargetLowering::LowerXConstraint(ConstraintVT);
16360 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
16361 /// vector. If it is invalid, don't add anything to Ops.
16362 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
16363 std::string &Constraint,
16364 std::vector<SDValue>&Ops,
16365 SelectionDAG &DAG) const {
16366 SDValue Result(0, 0);
16368 // Only support length 1 constraints for now.
16369 if (Constraint.length() > 1) return;
16371 char ConstraintLetter = Constraint[0];
16372 switch (ConstraintLetter) {
16375 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
16376 if (C->getZExtValue() <= 31) {
16377 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
16383 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
16384 if (C->getZExtValue() <= 63) {
16385 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
16391 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
16392 if ((int8_t)C->getSExtValue() == C->getSExtValue()) {
16393 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
16399 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
16400 if (C->getZExtValue() <= 255) {
16401 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
16407 // 32-bit signed value
16408 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
16409 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
16410 C->getSExtValue())) {
16411 // Widen to 64 bits here to get it sign extended.
16412 Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64);
16415 // FIXME gcc accepts some relocatable values here too, but only in certain
16416 // memory models; it's complicated.
16421 // 32-bit unsigned value
16422 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
16423 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
16424 C->getZExtValue())) {
16425 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
16429 // FIXME gcc accepts some relocatable values here too, but only in certain
16430 // memory models; it's complicated.
16434 // Literal immediates are always ok.
16435 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
16436 // Widen to 64 bits here to get it sign extended.
16437 Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64);
16441 // In any sort of PIC mode addresses need to be computed at runtime by
16442 // adding in a register or some sort of table lookup. These can't
16443 // be used as immediates.
16444 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC())
16447 // If we are in non-pic codegen mode, we allow the address of a global (with
16448 // an optional displacement) to be used with 'i'.
16449 GlobalAddressSDNode *GA = 0;
16450 int64_t Offset = 0;
16452 // Match either (GA), (GA+C), (GA+C1+C2), etc.
16454 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
16455 Offset += GA->getOffset();
16457 } else if (Op.getOpcode() == ISD::ADD) {
16458 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
16459 Offset += C->getZExtValue();
16460 Op = Op.getOperand(0);
16463 } else if (Op.getOpcode() == ISD::SUB) {
16464 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
16465 Offset += -C->getZExtValue();
16466 Op = Op.getOperand(0);
16471 // Otherwise, this isn't something we can handle, reject it.
16475 const GlobalValue *GV = GA->getGlobal();
16476 // If we require an extra load to get this address, as in PIC mode, we
16477 // can't accept it.
16478 if (isGlobalStubReference(Subtarget->ClassifyGlobalReference(GV,
16479 getTargetMachine())))
16482 Result = DAG.getTargetGlobalAddress(GV, Op.getDebugLoc(),
16483 GA->getValueType(0), Offset);
16488 if (Result.getNode()) {
16489 Ops.push_back(Result);
16492 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
16495 std::pair<unsigned, const TargetRegisterClass*>
16496 X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
16498 // First, see if this is a constraint that directly corresponds to an LLVM
16500 if (Constraint.size() == 1) {
16501 // GCC Constraint Letters
16502 switch (Constraint[0]) {
16504 // TODO: Slight differences here in allocation order and leaving
16505 // RIP in the class. Do they matter any more here than they do
16506 // in the normal allocation?
16507 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
16508 if (Subtarget->is64Bit()) {
16509 if (VT == MVT::i32 || VT == MVT::f32)
16510 return std::make_pair(0U, &X86::GR32RegClass);
16511 if (VT == MVT::i16)
16512 return std::make_pair(0U, &X86::GR16RegClass);
16513 if (VT == MVT::i8 || VT == MVT::i1)
16514 return std::make_pair(0U, &X86::GR8RegClass);
16515 if (VT == MVT::i64 || VT == MVT::f64)
16516 return std::make_pair(0U, &X86::GR64RegClass);
16519 // 32-bit fallthrough
16520 case 'Q': // Q_REGS
16521 if (VT == MVT::i32 || VT == MVT::f32)
16522 return std::make_pair(0U, &X86::GR32_ABCDRegClass);
16523 if (VT == MVT::i16)
16524 return std::make_pair(0U, &X86::GR16_ABCDRegClass);
16525 if (VT == MVT::i8 || VT == MVT::i1)
16526 return std::make_pair(0U, &X86::GR8_ABCD_LRegClass);
16527 if (VT == MVT::i64)
16528 return std::make_pair(0U, &X86::GR64_ABCDRegClass);
16530 case 'r': // GENERAL_REGS
16531 case 'l': // INDEX_REGS
16532 if (VT == MVT::i8 || VT == MVT::i1)
16533 return std::make_pair(0U, &X86::GR8RegClass);
16534 if (VT == MVT::i16)
16535 return std::make_pair(0U, &X86::GR16RegClass);
16536 if (VT == MVT::i32 || VT == MVT::f32 || !Subtarget->is64Bit())
16537 return std::make_pair(0U, &X86::GR32RegClass);
16538 return std::make_pair(0U, &X86::GR64RegClass);
16539 case 'R': // LEGACY_REGS
16540 if (VT == MVT::i8 || VT == MVT::i1)
16541 return std::make_pair(0U, &X86::GR8_NOREXRegClass);
16542 if (VT == MVT::i16)
16543 return std::make_pair(0U, &X86::GR16_NOREXRegClass);
16544 if (VT == MVT::i32 || !Subtarget->is64Bit())
16545 return std::make_pair(0U, &X86::GR32_NOREXRegClass);
16546 return std::make_pair(0U, &X86::GR64_NOREXRegClass);
16547 case 'f': // FP Stack registers.
16548 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
16549 // value to the correct fpstack register class.
16550 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
16551 return std::make_pair(0U, &X86::RFP32RegClass);
16552 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
16553 return std::make_pair(0U, &X86::RFP64RegClass);
16554 return std::make_pair(0U, &X86::RFP80RegClass);
16555 case 'y': // MMX_REGS if MMX allowed.
16556 if (!Subtarget->hasMMX()) break;
16557 return std::make_pair(0U, &X86::VR64RegClass);
16558 case 'Y': // SSE_REGS if SSE2 allowed
16559 if (!Subtarget->hasSSE2()) break;
16561 case 'x': // SSE_REGS if SSE1 allowed or AVX_REGS if AVX allowed
16562 if (!Subtarget->hasSSE1()) break;
16564 switch (VT.getSimpleVT().SimpleTy) {
16566 // Scalar SSE types.
16569 return std::make_pair(0U, &X86::FR32RegClass);
16572 return std::make_pair(0U, &X86::FR64RegClass);
16580 return std::make_pair(0U, &X86::VR128RegClass);
16588 return std::make_pair(0U, &X86::VR256RegClass);
16594 // Use the default implementation in TargetLowering to convert the register
16595 // constraint into a member of a register class.
16596 std::pair<unsigned, const TargetRegisterClass*> Res;
16597 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
16599 // Not found as a standard register?
16600 if (Res.second == 0) {
16601 // Map st(0) -> st(7) -> ST0
16602 if (Constraint.size() == 7 && Constraint[0] == '{' &&
16603 tolower(Constraint[1]) == 's' &&
16604 tolower(Constraint[2]) == 't' &&
16605 Constraint[3] == '(' &&
16606 (Constraint[4] >= '0' && Constraint[4] <= '7') &&
16607 Constraint[5] == ')' &&
16608 Constraint[6] == '}') {
16610 Res.first = X86::ST0+Constraint[4]-'0';
16611 Res.second = &X86::RFP80RegClass;
16615 // GCC allows "st(0)" to be called just plain "st".
16616 if (StringRef("{st}").equals_lower(Constraint)) {
16617 Res.first = X86::ST0;
16618 Res.second = &X86::RFP80RegClass;
16623 if (StringRef("{flags}").equals_lower(Constraint)) {
16624 Res.first = X86::EFLAGS;
16625 Res.second = &X86::CCRRegClass;
16629 // 'A' means EAX + EDX.
16630 if (Constraint == "A") {
16631 Res.first = X86::EAX;
16632 Res.second = &X86::GR32_ADRegClass;
16638 // Otherwise, check to see if this is a register class of the wrong value
16639 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
16640 // turn into {ax},{dx}.
16641 if (Res.second->hasType(VT))
16642 return Res; // Correct type already, nothing to do.
16644 // All of the single-register GCC register classes map their values onto
16645 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
16646 // really want an 8-bit or 32-bit register, map to the appropriate register
16647 // class and return the appropriate register.
16648 if (Res.second == &X86::GR16RegClass) {
16649 if (VT == MVT::i8) {
16650 unsigned DestReg = 0;
16651 switch (Res.first) {
16653 case X86::AX: DestReg = X86::AL; break;
16654 case X86::DX: DestReg = X86::DL; break;
16655 case X86::CX: DestReg = X86::CL; break;
16656 case X86::BX: DestReg = X86::BL; break;
16659 Res.first = DestReg;
16660 Res.second = &X86::GR8RegClass;
16662 } else if (VT == MVT::i32) {
16663 unsigned DestReg = 0;
16664 switch (Res.first) {
16666 case X86::AX: DestReg = X86::EAX; break;
16667 case X86::DX: DestReg = X86::EDX; break;
16668 case X86::CX: DestReg = X86::ECX; break;
16669 case X86::BX: DestReg = X86::EBX; break;
16670 case X86::SI: DestReg = X86::ESI; break;
16671 case X86::DI: DestReg = X86::EDI; break;
16672 case X86::BP: DestReg = X86::EBP; break;
16673 case X86::SP: DestReg = X86::ESP; break;
16676 Res.first = DestReg;
16677 Res.second = &X86::GR32RegClass;
16679 } else if (VT == MVT::i64) {
16680 unsigned DestReg = 0;
16681 switch (Res.first) {
16683 case X86::AX: DestReg = X86::RAX; break;
16684 case X86::DX: DestReg = X86::RDX; break;
16685 case X86::CX: DestReg = X86::RCX; break;
16686 case X86::BX: DestReg = X86::RBX; break;
16687 case X86::SI: DestReg = X86::RSI; break;
16688 case X86::DI: DestReg = X86::RDI; break;
16689 case X86::BP: DestReg = X86::RBP; break;
16690 case X86::SP: DestReg = X86::RSP; break;
16693 Res.first = DestReg;
16694 Res.second = &X86::GR64RegClass;
16697 } else if (Res.second == &X86::FR32RegClass ||
16698 Res.second == &X86::FR64RegClass ||
16699 Res.second == &X86::VR128RegClass) {
16700 // Handle references to XMM physical registers that got mapped into the
16701 // wrong class. This can happen with constraints like {xmm0} where the
16702 // target independent register mapper will just pick the first match it can
16703 // find, ignoring the required type.
16705 if (VT == MVT::f32 || VT == MVT::i32)
16706 Res.second = &X86::FR32RegClass;
16707 else if (VT == MVT::f64 || VT == MVT::i64)
16708 Res.second = &X86::FR64RegClass;
16709 else if (X86::VR128RegClass.hasType(VT))
16710 Res.second = &X86::VR128RegClass;
16711 else if (X86::VR256RegClass.hasType(VT))
16712 Res.second = &X86::VR256RegClass;