1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #include "X86ISelLowering.h"
16 #include "Utils/X86ShuffleDecode.h"
17 #include "X86CallingConv.h"
18 #include "X86FrameLowering.h"
19 #include "X86InstrBuilder.h"
20 #include "X86MachineFunctionInfo.h"
21 #include "X86TargetMachine.h"
22 #include "X86TargetObjectFile.h"
23 #include "llvm/ADT/SmallBitVector.h"
24 #include "llvm/ADT/SmallSet.h"
25 #include "llvm/ADT/Statistic.h"
26 #include "llvm/ADT/StringExtras.h"
27 #include "llvm/ADT/StringSwitch.h"
28 #include "llvm/Analysis/LibCallSemantics.h"
29 #include "llvm/CodeGen/IntrinsicLowering.h"
30 #include "llvm/CodeGen/MachineFrameInfo.h"
31 #include "llvm/CodeGen/MachineFunction.h"
32 #include "llvm/CodeGen/MachineInstrBuilder.h"
33 #include "llvm/CodeGen/MachineJumpTableInfo.h"
34 #include "llvm/CodeGen/MachineModuleInfo.h"
35 #include "llvm/CodeGen/MachineRegisterInfo.h"
36 #include "llvm/CodeGen/WinEHFuncInfo.h"
37 #include "llvm/IR/CallSite.h"
38 #include "llvm/IR/CallingConv.h"
39 #include "llvm/IR/Constants.h"
40 #include "llvm/IR/DerivedTypes.h"
41 #include "llvm/IR/Function.h"
42 #include "llvm/IR/GlobalAlias.h"
43 #include "llvm/IR/GlobalVariable.h"
44 #include "llvm/IR/Instructions.h"
45 #include "llvm/IR/Intrinsics.h"
46 #include "llvm/MC/MCAsmInfo.h"
47 #include "llvm/MC/MCContext.h"
48 #include "llvm/MC/MCExpr.h"
49 #include "llvm/MC/MCSymbol.h"
50 #include "llvm/Support/CommandLine.h"
51 #include "llvm/Support/Debug.h"
52 #include "llvm/Support/ErrorHandling.h"
53 #include "llvm/Support/MathExtras.h"
54 #include "llvm/Target/TargetOptions.h"
55 #include "X86IntrinsicsInfo.h"
61 #define DEBUG_TYPE "x86-isel"
63 STATISTIC(NumTailCalls, "Number of tail calls");
65 static cl::opt<bool> ExperimentalVectorWideningLegalization(
66 "x86-experimental-vector-widening-legalization", cl::init(false),
67 cl::desc("Enable an experimental vector type legalization through widening "
68 "rather than promotion."),
71 X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
72 const X86Subtarget &STI)
73 : TargetLowering(TM), Subtarget(&STI) {
74 X86ScalarSSEf64 = Subtarget->hasSSE2();
75 X86ScalarSSEf32 = Subtarget->hasSSE1();
76 MVT PtrVT = MVT::getIntegerVT(8 * TM.getPointerSize());
78 // Set up the TargetLowering object.
80 // X86 is weird. It always uses i8 for shift amounts and setcc results.
81 setBooleanContents(ZeroOrOneBooleanContent);
82 // X86-SSE is even stranger. It uses -1 or 0 for vector masks.
83 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
85 // For 64-bit, since we have so many registers, use the ILP scheduler.
86 // For 32-bit, use the register pressure specific scheduling.
87 // For Atom, always use ILP scheduling.
88 if (Subtarget->isAtom())
89 setSchedulingPreference(Sched::ILP);
90 else if (Subtarget->is64Bit())
91 setSchedulingPreference(Sched::ILP);
93 setSchedulingPreference(Sched::RegPressure);
94 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
95 setStackPointerRegisterToSaveRestore(RegInfo->getStackRegister());
97 // Bypass expensive divides on Atom when compiling with O2.
98 if (TM.getOptLevel() >= CodeGenOpt::Default) {
99 if (Subtarget->hasSlowDivide32())
100 addBypassSlowDiv(32, 8);
101 if (Subtarget->hasSlowDivide64() && Subtarget->is64Bit())
102 addBypassSlowDiv(64, 16);
105 if (Subtarget->isTargetKnownWindowsMSVC()) {
106 // Setup Windows compiler runtime calls.
107 setLibcallName(RTLIB::SDIV_I64, "_alldiv");
108 setLibcallName(RTLIB::UDIV_I64, "_aulldiv");
109 setLibcallName(RTLIB::SREM_I64, "_allrem");
110 setLibcallName(RTLIB::UREM_I64, "_aullrem");
111 setLibcallName(RTLIB::MUL_I64, "_allmul");
112 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall);
113 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall);
114 setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::X86_StdCall);
115 setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::X86_StdCall);
116 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::X86_StdCall);
119 if (Subtarget->isTargetDarwin()) {
120 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
121 setUseUnderscoreSetJmp(false);
122 setUseUnderscoreLongJmp(false);
123 } else if (Subtarget->isTargetWindowsGNU()) {
124 // MS runtime is weird: it exports _setjmp, but longjmp!
125 setUseUnderscoreSetJmp(true);
126 setUseUnderscoreLongJmp(false);
128 setUseUnderscoreSetJmp(true);
129 setUseUnderscoreLongJmp(true);
132 // Set up the register classes.
133 addRegisterClass(MVT::i8, &X86::GR8RegClass);
134 addRegisterClass(MVT::i16, &X86::GR16RegClass);
135 addRegisterClass(MVT::i32, &X86::GR32RegClass);
136 if (Subtarget->is64Bit())
137 addRegisterClass(MVT::i64, &X86::GR64RegClass);
139 for (MVT VT : MVT::integer_valuetypes())
140 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
142 // We don't accept any truncstore of integer registers.
143 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
144 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
145 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
146 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
147 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
148 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
150 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
152 // SETOEQ and SETUNE require checking two conditions.
153 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
154 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
155 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
156 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
157 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
158 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
160 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
162 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
163 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
164 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
166 if (Subtarget->is64Bit()) {
167 if (!Subtarget->useSoftFloat() && Subtarget->hasAVX512())
168 // f32/f64 are legal, f80 is custom.
169 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
171 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
172 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
173 } else if (!Subtarget->useSoftFloat()) {
174 // We have an algorithm for SSE2->double, and we turn this into a
175 // 64-bit FILD followed by conditional FADD for other targets.
176 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
177 // We have an algorithm for SSE2, and we turn this into a 64-bit
178 // FILD or VCVTUSI2SS/SD for other targets.
179 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
182 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
184 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
185 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
187 if (!Subtarget->useSoftFloat()) {
188 // SSE has no i16 to fp conversion, only i32
189 if (X86ScalarSSEf32) {
190 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
191 // f32 and f64 cases are Legal, f80 case is not
192 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
194 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
195 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
198 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
199 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
202 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
204 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
205 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
207 if (!Subtarget->useSoftFloat()) {
208 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
209 // are Legal, f80 is custom lowered.
210 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
211 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
213 if (X86ScalarSSEf32) {
214 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
215 // f32 and f64 cases are Legal, f80 case is not
216 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
218 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
219 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
222 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
223 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Expand);
224 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Expand);
227 // Handle FP_TO_UINT by promoting the destination to a larger signed
229 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
230 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
231 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
233 if (Subtarget->is64Bit()) {
234 if (!Subtarget->useSoftFloat() && Subtarget->hasAVX512()) {
235 // FP_TO_UINT-i32/i64 is legal for f32/f64, but custom for f80.
236 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
237 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Custom);
239 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
240 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
242 } else if (!Subtarget->useSoftFloat()) {
243 // Since AVX is a superset of SSE3, only check for SSE here.
244 if (Subtarget->hasSSE1() && !Subtarget->hasSSE3())
245 // Expand FP_TO_UINT into a select.
246 // FIXME: We would like to use a Custom expander here eventually to do
247 // the optimal thing for SSE vs. the default expansion in the legalizer.
248 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
250 // With AVX512 we can use vcvts[ds]2usi for f32/f64->i32, f80 is custom.
251 // With SSE3 we can use fisttpll to convert to a signed i64; without
252 // SSE, we're stuck with a fistpll.
253 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
255 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Custom);
258 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
259 if (!X86ScalarSSEf64) {
260 setOperationAction(ISD::BITCAST , MVT::f32 , Expand);
261 setOperationAction(ISD::BITCAST , MVT::i32 , Expand);
262 if (Subtarget->is64Bit()) {
263 setOperationAction(ISD::BITCAST , MVT::f64 , Expand);
264 // Without SSE, i64->f64 goes through memory.
265 setOperationAction(ISD::BITCAST , MVT::i64 , Expand);
269 // Scalar integer divide and remainder are lowered to use operations that
270 // produce two results, to match the available instructions. This exposes
271 // the two-result form to trivial CSE, which is able to combine x/y and x%y
272 // into a single instruction.
274 // Scalar integer multiply-high is also lowered to use two-result
275 // operations, to match the available instructions. However, plain multiply
276 // (low) operations are left as Legal, as there are single-result
277 // instructions for this in x86. Using the two-result multiply instructions
278 // when both high and low results are needed must be arranged by dagcombine.
279 for (auto VT : { MVT::i8, MVT::i16, MVT::i32, MVT::i64 }) {
280 setOperationAction(ISD::MULHS, VT, Expand);
281 setOperationAction(ISD::MULHU, VT, Expand);
282 setOperationAction(ISD::SDIV, VT, Expand);
283 setOperationAction(ISD::UDIV, VT, Expand);
284 setOperationAction(ISD::SREM, VT, Expand);
285 setOperationAction(ISD::UREM, VT, Expand);
287 // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences.
288 setOperationAction(ISD::ADDC, VT, Custom);
289 setOperationAction(ISD::ADDE, VT, Custom);
290 setOperationAction(ISD::SUBC, VT, Custom);
291 setOperationAction(ISD::SUBE, VT, Custom);
294 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
295 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
296 setOperationAction(ISD::BR_CC , MVT::f32, Expand);
297 setOperationAction(ISD::BR_CC , MVT::f64, Expand);
298 setOperationAction(ISD::BR_CC , MVT::f80, Expand);
299 setOperationAction(ISD::BR_CC , MVT::i8, Expand);
300 setOperationAction(ISD::BR_CC , MVT::i16, Expand);
301 setOperationAction(ISD::BR_CC , MVT::i32, Expand);
302 setOperationAction(ISD::BR_CC , MVT::i64, Expand);
303 setOperationAction(ISD::SELECT_CC , MVT::f32, Expand);
304 setOperationAction(ISD::SELECT_CC , MVT::f64, Expand);
305 setOperationAction(ISD::SELECT_CC , MVT::f80, Expand);
306 setOperationAction(ISD::SELECT_CC , MVT::i8, Expand);
307 setOperationAction(ISD::SELECT_CC , MVT::i16, Expand);
308 setOperationAction(ISD::SELECT_CC , MVT::i32, Expand);
309 setOperationAction(ISD::SELECT_CC , MVT::i64, Expand);
310 if (Subtarget->is64Bit())
311 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
312 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
313 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
314 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
315 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
317 if (Subtarget->is32Bit() && Subtarget->isTargetKnownWindowsMSVC()) {
318 // On 32 bit MSVC, `fmodf(f32)` is not defined - only `fmod(f64)`
319 // is. We should promote the value to 64-bits to solve this.
320 // This is what the CRT headers do - `fmodf` is an inline header
321 // function casting to f64 and calling `fmod`.
322 setOperationAction(ISD::FREM , MVT::f32 , Promote);
324 setOperationAction(ISD::FREM , MVT::f32 , Expand);
327 setOperationAction(ISD::FREM , MVT::f64 , Expand);
328 setOperationAction(ISD::FREM , MVT::f80 , Expand);
329 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
331 // Promote the i8 variants and force them on up to i32 which has a shorter
333 setOperationAction(ISD::CTTZ , MVT::i8 , Promote);
334 AddPromotedToType (ISD::CTTZ , MVT::i8 , MVT::i32);
335 setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i8 , Promote);
336 AddPromotedToType (ISD::CTTZ_ZERO_UNDEF , MVT::i8 , MVT::i32);
337 if (Subtarget->hasBMI()) {
338 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16 , Expand);
339 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32 , Expand);
340 if (Subtarget->is64Bit())
341 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
343 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
344 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
345 if (Subtarget->is64Bit())
346 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
349 if (Subtarget->hasLZCNT()) {
350 // When promoting the i8 variants, force them to i32 for a shorter
352 setOperationAction(ISD::CTLZ , MVT::i8 , Promote);
353 AddPromotedToType (ISD::CTLZ , MVT::i8 , MVT::i32);
354 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Promote);
355 AddPromotedToType (ISD::CTLZ_ZERO_UNDEF, MVT::i8 , MVT::i32);
356 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Expand);
357 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Expand);
358 if (Subtarget->is64Bit())
359 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
361 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
362 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
363 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
364 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Custom);
365 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Custom);
366 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Custom);
367 if (Subtarget->is64Bit()) {
368 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
369 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom);
373 // Special handling for half-precision floating point conversions.
374 // If we don't have F16C support, then lower half float conversions
375 // into library calls.
376 if (Subtarget->useSoftFloat() || !Subtarget->hasF16C()) {
377 setOperationAction(ISD::FP16_TO_FP, MVT::f32, Expand);
378 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand);
381 // There's never any support for operations beyond MVT::f32.
382 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand);
383 setOperationAction(ISD::FP16_TO_FP, MVT::f80, Expand);
384 setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand);
385 setOperationAction(ISD::FP_TO_FP16, MVT::f80, Expand);
387 setLoadExtAction(ISD::EXTLOAD, MVT::f32, MVT::f16, Expand);
388 setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f16, Expand);
389 setLoadExtAction(ISD::EXTLOAD, MVT::f80, MVT::f16, Expand);
390 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
391 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
392 setTruncStoreAction(MVT::f80, MVT::f16, Expand);
394 if (Subtarget->hasPOPCNT()) {
395 setOperationAction(ISD::CTPOP , MVT::i8 , Promote);
397 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
398 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
399 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
400 if (Subtarget->is64Bit())
401 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
404 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
406 if (!Subtarget->hasMOVBE())
407 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
409 // These should be promoted to a larger select which is supported.
410 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
411 // X86 wants to expand cmov itself.
412 setOperationAction(ISD::SELECT , MVT::i8 , Custom);
413 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
414 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
415 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
416 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
417 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
418 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
419 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
420 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
421 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
422 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
423 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
424 setOperationAction(ISD::SETCCE , MVT::i8 , Custom);
425 setOperationAction(ISD::SETCCE , MVT::i16 , Custom);
426 setOperationAction(ISD::SETCCE , MVT::i32 , Custom);
427 if (Subtarget->is64Bit()) {
428 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
429 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
430 setOperationAction(ISD::SETCCE , MVT::i64 , Custom);
432 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
433 // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support
434 // SjLj exception handling but a light-weight setjmp/longjmp replacement to
435 // support continuation, user-level threading, and etc.. As a result, no
436 // other SjLj exception interfaces are implemented and please don't build
437 // your own exception handling based on them.
438 // LLVM/Clang supports zero-cost DWARF exception handling.
439 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
440 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
443 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
444 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
445 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
446 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
447 if (Subtarget->is64Bit())
448 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
449 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
450 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom);
451 if (Subtarget->is64Bit()) {
452 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
453 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
454 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
455 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
456 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom);
458 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
459 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
460 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
461 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
462 if (Subtarget->is64Bit()) {
463 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
464 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
465 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
468 if (Subtarget->hasSSE1())
469 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
471 setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom);
473 // Expand certain atomics
474 for (auto VT : { MVT::i8, MVT::i16, MVT::i32, MVT::i64 }) {
475 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, VT, Custom);
476 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom);
477 setOperationAction(ISD::ATOMIC_STORE, VT, Custom);
480 if (Subtarget->hasCmpxchg16b()) {
481 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, MVT::i128, Custom);
484 // FIXME - use subtarget debug flags
485 if (!Subtarget->isTargetDarwin() && !Subtarget->isTargetELF() &&
486 !Subtarget->isTargetCygMing() && !Subtarget->isTargetWin64()) {
487 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
490 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
491 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
493 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
494 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
496 setOperationAction(ISD::TRAP, MVT::Other, Legal);
497 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Legal);
499 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
500 setOperationAction(ISD::VASTART , MVT::Other, Custom);
501 setOperationAction(ISD::VAEND , MVT::Other, Expand);
502 if (Subtarget->is64Bit()) {
503 setOperationAction(ISD::VAARG , MVT::Other, Custom);
504 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
506 // TargetInfo::CharPtrBuiltinVaList
507 setOperationAction(ISD::VAARG , MVT::Other, Expand);
508 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
511 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
512 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
514 setOperationAction(ISD::DYNAMIC_STACKALLOC, PtrVT, Custom);
516 // GC_TRANSITION_START and GC_TRANSITION_END need custom lowering.
517 setOperationAction(ISD::GC_TRANSITION_START, MVT::Other, Custom);
518 setOperationAction(ISD::GC_TRANSITION_END, MVT::Other, Custom);
520 if (!Subtarget->useSoftFloat() && X86ScalarSSEf64) {
521 // f32 and f64 use SSE.
522 // Set up the FP register classes.
523 addRegisterClass(MVT::f32, &X86::FR32RegClass);
524 addRegisterClass(MVT::f64, &X86::FR64RegClass);
526 // Use ANDPD to simulate FABS.
527 setOperationAction(ISD::FABS , MVT::f64, Custom);
528 setOperationAction(ISD::FABS , MVT::f32, Custom);
530 // Use XORP to simulate FNEG.
531 setOperationAction(ISD::FNEG , MVT::f64, Custom);
532 setOperationAction(ISD::FNEG , MVT::f32, Custom);
534 // Use ANDPD and ORPD to simulate FCOPYSIGN.
535 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
536 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
538 // Lower this to FGETSIGNx86 plus an AND.
539 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom);
540 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom);
542 // We don't support sin/cos/fmod
543 setOperationAction(ISD::FSIN , MVT::f64, Expand);
544 setOperationAction(ISD::FCOS , MVT::f64, Expand);
545 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
546 setOperationAction(ISD::FSIN , MVT::f32, Expand);
547 setOperationAction(ISD::FCOS , MVT::f32, Expand);
548 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
550 // Expand FP immediates into loads from the stack, except for the special
552 addLegalFPImmediate(APFloat(+0.0)); // xorpd
553 addLegalFPImmediate(APFloat(+0.0f)); // xorps
554 } else if (!Subtarget->useSoftFloat() && X86ScalarSSEf32) {
555 // Use SSE for f32, x87 for f64.
556 // Set up the FP register classes.
557 addRegisterClass(MVT::f32, &X86::FR32RegClass);
558 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
560 // Use ANDPS to simulate FABS.
561 setOperationAction(ISD::FABS , MVT::f32, Custom);
563 // Use XORP to simulate FNEG.
564 setOperationAction(ISD::FNEG , MVT::f32, Custom);
566 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
568 // Use ANDPS and ORPS to simulate FCOPYSIGN.
569 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
570 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
572 // We don't support sin/cos/fmod
573 setOperationAction(ISD::FSIN , MVT::f32, Expand);
574 setOperationAction(ISD::FCOS , MVT::f32, Expand);
575 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
577 // Special cases we handle for FP constants.
578 addLegalFPImmediate(APFloat(+0.0f)); // xorps
579 addLegalFPImmediate(APFloat(+0.0)); // FLD0
580 addLegalFPImmediate(APFloat(+1.0)); // FLD1
581 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
582 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
584 if (!TM.Options.UnsafeFPMath) {
585 setOperationAction(ISD::FSIN , MVT::f64, Expand);
586 setOperationAction(ISD::FCOS , MVT::f64, Expand);
587 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
589 } else if (!Subtarget->useSoftFloat()) {
590 // f32 and f64 in x87.
591 // Set up the FP register classes.
592 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
593 addRegisterClass(MVT::f32, &X86::RFP32RegClass);
595 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
596 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
597 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
598 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
600 if (!TM.Options.UnsafeFPMath) {
601 setOperationAction(ISD::FSIN , MVT::f64, Expand);
602 setOperationAction(ISD::FSIN , MVT::f32, Expand);
603 setOperationAction(ISD::FCOS , MVT::f64, Expand);
604 setOperationAction(ISD::FCOS , MVT::f32, Expand);
605 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
606 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
608 addLegalFPImmediate(APFloat(+0.0)); // FLD0
609 addLegalFPImmediate(APFloat(+1.0)); // FLD1
610 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
611 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
612 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
613 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
614 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
615 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
618 // We don't support FMA.
619 setOperationAction(ISD::FMA, MVT::f64, Expand);
620 setOperationAction(ISD::FMA, MVT::f32, Expand);
622 // Long double always uses X87.
623 if (!Subtarget->useSoftFloat()) {
624 addRegisterClass(MVT::f80, &X86::RFP80RegClass);
625 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
626 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
628 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended);
629 addLegalFPImmediate(TmpFlt); // FLD0
631 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
634 APFloat TmpFlt2(+1.0);
635 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
637 addLegalFPImmediate(TmpFlt2); // FLD1
638 TmpFlt2.changeSign();
639 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
642 if (!TM.Options.UnsafeFPMath) {
643 setOperationAction(ISD::FSIN , MVT::f80, Expand);
644 setOperationAction(ISD::FCOS , MVT::f80, Expand);
645 setOperationAction(ISD::FSINCOS, MVT::f80, Expand);
648 setOperationAction(ISD::FFLOOR, MVT::f80, Expand);
649 setOperationAction(ISD::FCEIL, MVT::f80, Expand);
650 setOperationAction(ISD::FTRUNC, MVT::f80, Expand);
651 setOperationAction(ISD::FRINT, MVT::f80, Expand);
652 setOperationAction(ISD::FNEARBYINT, MVT::f80, Expand);
653 setOperationAction(ISD::FMA, MVT::f80, Expand);
656 // Always use a library call for pow.
657 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
658 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
659 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
661 setOperationAction(ISD::FLOG, MVT::f80, Expand);
662 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
663 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
664 setOperationAction(ISD::FEXP, MVT::f80, Expand);
665 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
666 setOperationAction(ISD::FMINNUM, MVT::f80, Expand);
667 setOperationAction(ISD::FMAXNUM, MVT::f80, Expand);
669 // First set operation action for all vector types to either promote
670 // (for widening) or expand (for scalarization). Then we will selectively
671 // turn on ones that can be effectively codegen'd.
672 for (MVT VT : MVT::vector_valuetypes()) {
673 setOperationAction(ISD::ADD , VT, Expand);
674 setOperationAction(ISD::SUB , VT, Expand);
675 setOperationAction(ISD::FADD, VT, Expand);
676 setOperationAction(ISD::FNEG, VT, Expand);
677 setOperationAction(ISD::FSUB, VT, Expand);
678 setOperationAction(ISD::MUL , VT, Expand);
679 setOperationAction(ISD::FMUL, VT, Expand);
680 setOperationAction(ISD::SDIV, VT, Expand);
681 setOperationAction(ISD::UDIV, VT, Expand);
682 setOperationAction(ISD::FDIV, VT, Expand);
683 setOperationAction(ISD::SREM, VT, Expand);
684 setOperationAction(ISD::UREM, VT, Expand);
685 setOperationAction(ISD::LOAD, VT, Expand);
686 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);
687 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT,Expand);
688 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
689 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT,Expand);
690 setOperationAction(ISD::INSERT_SUBVECTOR, VT,Expand);
691 setOperationAction(ISD::FABS, VT, Expand);
692 setOperationAction(ISD::FSIN, VT, Expand);
693 setOperationAction(ISD::FSINCOS, VT, Expand);
694 setOperationAction(ISD::FCOS, VT, Expand);
695 setOperationAction(ISD::FSINCOS, VT, Expand);
696 setOperationAction(ISD::FREM, VT, Expand);
697 setOperationAction(ISD::FMA, VT, Expand);
698 setOperationAction(ISD::FPOWI, VT, Expand);
699 setOperationAction(ISD::FSQRT, VT, Expand);
700 setOperationAction(ISD::FCOPYSIGN, VT, Expand);
701 setOperationAction(ISD::FFLOOR, VT, Expand);
702 setOperationAction(ISD::FCEIL, VT, Expand);
703 setOperationAction(ISD::FTRUNC, VT, Expand);
704 setOperationAction(ISD::FRINT, VT, Expand);
705 setOperationAction(ISD::FNEARBYINT, VT, Expand);
706 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
707 setOperationAction(ISD::MULHS, VT, Expand);
708 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
709 setOperationAction(ISD::MULHU, VT, Expand);
710 setOperationAction(ISD::SDIVREM, VT, Expand);
711 setOperationAction(ISD::UDIVREM, VT, Expand);
712 setOperationAction(ISD::FPOW, VT, Expand);
713 setOperationAction(ISD::CTPOP, VT, Expand);
714 setOperationAction(ISD::CTTZ, VT, Expand);
715 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
716 setOperationAction(ISD::CTLZ, VT, Expand);
717 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
718 setOperationAction(ISD::SHL, VT, Expand);
719 setOperationAction(ISD::SRA, VT, Expand);
720 setOperationAction(ISD::SRL, VT, Expand);
721 setOperationAction(ISD::ROTL, VT, Expand);
722 setOperationAction(ISD::ROTR, VT, Expand);
723 setOperationAction(ISD::BSWAP, VT, Expand);
724 setOperationAction(ISD::SETCC, VT, Expand);
725 setOperationAction(ISD::FLOG, VT, Expand);
726 setOperationAction(ISD::FLOG2, VT, Expand);
727 setOperationAction(ISD::FLOG10, VT, Expand);
728 setOperationAction(ISD::FEXP, VT, Expand);
729 setOperationAction(ISD::FEXP2, VT, Expand);
730 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
731 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
732 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
733 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
734 setOperationAction(ISD::SIGN_EXTEND_INREG, VT,Expand);
735 setOperationAction(ISD::TRUNCATE, VT, Expand);
736 setOperationAction(ISD::SIGN_EXTEND, VT, Expand);
737 setOperationAction(ISD::ZERO_EXTEND, VT, Expand);
738 setOperationAction(ISD::ANY_EXTEND, VT, Expand);
739 setOperationAction(ISD::VSELECT, VT, Expand);
740 setOperationAction(ISD::SELECT_CC, VT, Expand);
741 for (MVT InnerVT : MVT::vector_valuetypes()) {
742 setTruncStoreAction(InnerVT, VT, Expand);
744 setLoadExtAction(ISD::SEXTLOAD, InnerVT, VT, Expand);
745 setLoadExtAction(ISD::ZEXTLOAD, InnerVT, VT, Expand);
747 // N.b. ISD::EXTLOAD legality is basically ignored except for i1-like
748 // types, we have to deal with them whether we ask for Expansion or not.
749 // Setting Expand causes its own optimisation problems though, so leave
751 if (VT.getVectorElementType() == MVT::i1)
752 setLoadExtAction(ISD::EXTLOAD, InnerVT, VT, Expand);
754 // EXTLOAD for MVT::f16 vectors is not legal because f16 vectors are
755 // split/scalarized right now.
756 if (VT.getVectorElementType() == MVT::f16)
757 setLoadExtAction(ISD::EXTLOAD, InnerVT, VT, Expand);
761 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
762 // with -msoft-float, disable use of MMX as well.
763 if (!Subtarget->useSoftFloat() && Subtarget->hasMMX()) {
764 addRegisterClass(MVT::x86mmx, &X86::VR64RegClass);
765 // No operations on x86mmx supported, everything uses intrinsics.
768 // MMX-sized vectors (other than x86mmx) are expected to be expanded
769 // into smaller operations.
770 for (MVT MMXTy : {MVT::v8i8, MVT::v4i16, MVT::v2i32, MVT::v1i64}) {
771 setOperationAction(ISD::MULHS, MMXTy, Expand);
772 setOperationAction(ISD::AND, MMXTy, Expand);
773 setOperationAction(ISD::OR, MMXTy, Expand);
774 setOperationAction(ISD::XOR, MMXTy, Expand);
775 setOperationAction(ISD::SCALAR_TO_VECTOR, MMXTy, Expand);
776 setOperationAction(ISD::SELECT, MMXTy, Expand);
777 setOperationAction(ISD::BITCAST, MMXTy, Expand);
779 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand);
781 if (!Subtarget->useSoftFloat() && Subtarget->hasSSE1()) {
782 addRegisterClass(MVT::v4f32, &X86::VR128RegClass);
784 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
785 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
786 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
787 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
788 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
789 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
790 setOperationAction(ISD::FABS, MVT::v4f32, Custom);
791 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
792 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
793 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
794 setOperationAction(ISD::VSELECT, MVT::v4f32, Custom);
795 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
796 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
797 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Custom);
800 if (!Subtarget->useSoftFloat() && Subtarget->hasSSE2()) {
801 addRegisterClass(MVT::v2f64, &X86::VR128RegClass);
803 // FIXME: Unfortunately, -soft-float and -no-implicit-float mean XMM
804 // registers cannot be used even for integer operations.
805 addRegisterClass(MVT::v16i8, &X86::VR128RegClass);
806 addRegisterClass(MVT::v8i16, &X86::VR128RegClass);
807 addRegisterClass(MVT::v4i32, &X86::VR128RegClass);
808 addRegisterClass(MVT::v2i64, &X86::VR128RegClass);
810 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
811 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
812 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
813 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
814 setOperationAction(ISD::MUL, MVT::v16i8, Custom);
815 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
816 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
817 setOperationAction(ISD::UMUL_LOHI, MVT::v4i32, Custom);
818 setOperationAction(ISD::SMUL_LOHI, MVT::v4i32, Custom);
819 setOperationAction(ISD::MULHU, MVT::v8i16, Legal);
820 setOperationAction(ISD::MULHS, MVT::v8i16, Legal);
821 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
822 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
823 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
824 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
825 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
826 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
827 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
828 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
829 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
830 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
831 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
832 setOperationAction(ISD::FABS, MVT::v2f64, Custom);
834 setOperationAction(ISD::SMAX, MVT::v8i16, Legal);
835 setOperationAction(ISD::UMAX, MVT::v16i8, Legal);
836 setOperationAction(ISD::SMIN, MVT::v8i16, Legal);
837 setOperationAction(ISD::UMIN, MVT::v16i8, Legal);
839 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
840 setOperationAction(ISD::SETCC, MVT::v16i8, Custom);
841 setOperationAction(ISD::SETCC, MVT::v8i16, Custom);
842 setOperationAction(ISD::SETCC, MVT::v4i32, Custom);
844 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
845 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
846 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
847 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
848 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
850 setOperationAction(ISD::CTPOP, MVT::v16i8, Custom);
851 setOperationAction(ISD::CTPOP, MVT::v8i16, Custom);
852 setOperationAction(ISD::CTPOP, MVT::v4i32, Custom);
853 setOperationAction(ISD::CTPOP, MVT::v2i64, Custom);
855 setOperationAction(ISD::CTTZ, MVT::v16i8, Custom);
856 setOperationAction(ISD::CTTZ, MVT::v8i16, Custom);
857 setOperationAction(ISD::CTTZ, MVT::v4i32, Custom);
858 // ISD::CTTZ v2i64 - scalarization is faster.
859 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v16i8, Custom);
860 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v8i16, Custom);
861 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v4i32, Custom);
862 // ISD::CTTZ_ZERO_UNDEF v2i64 - scalarization is faster.
864 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
865 for (auto VT : { MVT::v16i8, MVT::v8i16, MVT::v4i32 }) {
866 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
867 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
868 setOperationAction(ISD::VSELECT, VT, Custom);
869 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
872 // We support custom legalizing of sext and anyext loads for specific
873 // memory vector types which we can load as a scalar (or sequence of
874 // scalars) and extend in-register to a legal 128-bit vector type. For sext
875 // loads these must work with a single scalar load.
876 for (MVT VT : MVT::integer_vector_valuetypes()) {
877 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v4i8, Custom);
878 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v4i16, Custom);
879 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v8i8, Custom);
880 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i8, Custom);
881 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i16, Custom);
882 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i32, Custom);
883 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4i8, Custom);
884 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4i16, Custom);
885 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v8i8, Custom);
888 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
889 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
890 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
891 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
892 setOperationAction(ISD::VSELECT, MVT::v2f64, Custom);
893 setOperationAction(ISD::VSELECT, MVT::v2i64, Custom);
894 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
895 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
897 if (Subtarget->is64Bit()) {
898 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
899 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
902 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
903 for (auto VT : { MVT::v16i8, MVT::v8i16, MVT::v4i32 }) {
904 setOperationAction(ISD::AND, VT, Promote);
905 AddPromotedToType (ISD::AND, VT, MVT::v2i64);
906 setOperationAction(ISD::OR, VT, Promote);
907 AddPromotedToType (ISD::OR, VT, MVT::v2i64);
908 setOperationAction(ISD::XOR, VT, Promote);
909 AddPromotedToType (ISD::XOR, VT, MVT::v2i64);
910 setOperationAction(ISD::LOAD, VT, Promote);
911 AddPromotedToType (ISD::LOAD, VT, MVT::v2i64);
912 setOperationAction(ISD::SELECT, VT, Promote);
913 AddPromotedToType (ISD::SELECT, VT, MVT::v2i64);
916 // Custom lower v2i64 and v2f64 selects.
917 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
918 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
919 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
920 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
922 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
923 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
925 setOperationAction(ISD::SINT_TO_FP, MVT::v2i32, Custom);
927 setOperationAction(ISD::UINT_TO_FP, MVT::v4i8, Custom);
928 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);
929 // As there is no 64-bit GPR available, we need build a special custom
930 // sequence to convert from v2i32 to v2f32.
931 if (!Subtarget->is64Bit())
932 setOperationAction(ISD::UINT_TO_FP, MVT::v2f32, Custom);
934 setOperationAction(ISD::FP_EXTEND, MVT::v2f32, Custom);
935 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Custom);
937 for (MVT VT : MVT::fp_vector_valuetypes())
938 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2f32, Legal);
940 setOperationAction(ISD::BITCAST, MVT::v2i32, Custom);
941 setOperationAction(ISD::BITCAST, MVT::v4i16, Custom);
942 setOperationAction(ISD::BITCAST, MVT::v8i8, Custom);
945 if (!Subtarget->useSoftFloat() && Subtarget->hasSSE41()) {
946 for (MVT RoundedTy : {MVT::f32, MVT::f64, MVT::v4f32, MVT::v2f64}) {
947 setOperationAction(ISD::FFLOOR, RoundedTy, Legal);
948 setOperationAction(ISD::FCEIL, RoundedTy, Legal);
949 setOperationAction(ISD::FTRUNC, RoundedTy, Legal);
950 setOperationAction(ISD::FRINT, RoundedTy, Legal);
951 setOperationAction(ISD::FNEARBYINT, RoundedTy, Legal);
954 setOperationAction(ISD::SMAX, MVT::v16i8, Legal);
955 setOperationAction(ISD::SMAX, MVT::v4i32, Legal);
956 setOperationAction(ISD::UMAX, MVT::v8i16, Legal);
957 setOperationAction(ISD::UMAX, MVT::v4i32, Legal);
958 setOperationAction(ISD::SMIN, MVT::v16i8, Legal);
959 setOperationAction(ISD::SMIN, MVT::v4i32, Legal);
960 setOperationAction(ISD::UMIN, MVT::v8i16, Legal);
961 setOperationAction(ISD::UMIN, MVT::v4i32, Legal);
963 // FIXME: Do we need to handle scalar-to-vector here?
964 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
966 // We directly match byte blends in the backend as they match the VSELECT
968 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
970 // SSE41 brings specific instructions for doing vector sign extend even in
971 // cases where we don't have SRA.
972 for (MVT VT : MVT::integer_vector_valuetypes()) {
973 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i8, Custom);
974 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i16, Custom);
975 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i32, Custom);
978 // SSE41 also has vector sign/zero extending loads, PMOV[SZ]X
979 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i16, MVT::v8i8, Legal);
980 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i32, MVT::v4i8, Legal);
981 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i64, MVT::v2i8, Legal);
982 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i32, MVT::v4i16, Legal);
983 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i64, MVT::v2i16, Legal);
984 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i64, MVT::v2i32, Legal);
986 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i16, MVT::v8i8, Legal);
987 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i32, MVT::v4i8, Legal);
988 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i64, MVT::v2i8, Legal);
989 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i32, MVT::v4i16, Legal);
990 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i64, MVT::v2i16, Legal);
991 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i64, MVT::v2i32, Legal);
993 // i8 and i16 vectors are custom because the source register and source
994 // source memory operand types are not the same width. f32 vectors are
995 // custom since the immediate controlling the insert encodes additional
997 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
998 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
999 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
1000 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
1002 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
1003 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
1004 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
1005 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
1007 // FIXME: these should be Legal, but that's only for the case where
1008 // the index is constant. For now custom expand to deal with that.
1009 if (Subtarget->is64Bit()) {
1010 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
1011 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
1015 if (Subtarget->hasSSE2()) {
1016 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v2i64, Custom);
1017 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v4i32, Custom);
1018 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v8i16, Custom);
1020 setOperationAction(ISD::SRL, MVT::v8i16, Custom);
1021 setOperationAction(ISD::SRL, MVT::v16i8, Custom);
1023 setOperationAction(ISD::SHL, MVT::v8i16, Custom);
1024 setOperationAction(ISD::SHL, MVT::v16i8, Custom);
1026 setOperationAction(ISD::SRA, MVT::v8i16, Custom);
1027 setOperationAction(ISD::SRA, MVT::v16i8, Custom);
1029 // In the customized shift lowering, the legal cases in AVX2 will be
1031 setOperationAction(ISD::SRL, MVT::v2i64, Custom);
1032 setOperationAction(ISD::SRL, MVT::v4i32, Custom);
1034 setOperationAction(ISD::SHL, MVT::v2i64, Custom);
1035 setOperationAction(ISD::SHL, MVT::v4i32, Custom);
1037 setOperationAction(ISD::SRA, MVT::v2i64, Custom);
1038 setOperationAction(ISD::SRA, MVT::v4i32, Custom);
1041 if (Subtarget->hasXOP()) {
1042 setOperationAction(ISD::ROTL, MVT::v16i8, Custom);
1043 setOperationAction(ISD::ROTL, MVT::v8i16, Custom);
1044 setOperationAction(ISD::ROTL, MVT::v4i32, Custom);
1045 setOperationAction(ISD::ROTL, MVT::v2i64, Custom);
1046 setOperationAction(ISD::ROTL, MVT::v32i8, Custom);
1047 setOperationAction(ISD::ROTL, MVT::v16i16, Custom);
1048 setOperationAction(ISD::ROTL, MVT::v8i32, Custom);
1049 setOperationAction(ISD::ROTL, MVT::v4i64, Custom);
1052 if (!Subtarget->useSoftFloat() && Subtarget->hasFp256()) {
1053 addRegisterClass(MVT::v32i8, &X86::VR256RegClass);
1054 addRegisterClass(MVT::v16i16, &X86::VR256RegClass);
1055 addRegisterClass(MVT::v8i32, &X86::VR256RegClass);
1056 addRegisterClass(MVT::v8f32, &X86::VR256RegClass);
1057 addRegisterClass(MVT::v4i64, &X86::VR256RegClass);
1058 addRegisterClass(MVT::v4f64, &X86::VR256RegClass);
1060 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
1061 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
1062 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
1064 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
1065 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
1066 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
1067 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
1068 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
1069 setOperationAction(ISD::FFLOOR, MVT::v8f32, Legal);
1070 setOperationAction(ISD::FCEIL, MVT::v8f32, Legal);
1071 setOperationAction(ISD::FTRUNC, MVT::v8f32, Legal);
1072 setOperationAction(ISD::FRINT, MVT::v8f32, Legal);
1073 setOperationAction(ISD::FNEARBYINT, MVT::v8f32, Legal);
1074 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
1075 setOperationAction(ISD::FABS, MVT::v8f32, Custom);
1077 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
1078 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
1079 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
1080 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
1081 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
1082 setOperationAction(ISD::FFLOOR, MVT::v4f64, Legal);
1083 setOperationAction(ISD::FCEIL, MVT::v4f64, Legal);
1084 setOperationAction(ISD::FTRUNC, MVT::v4f64, Legal);
1085 setOperationAction(ISD::FRINT, MVT::v4f64, Legal);
1086 setOperationAction(ISD::FNEARBYINT, MVT::v4f64, Legal);
1087 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
1088 setOperationAction(ISD::FABS, MVT::v4f64, Custom);
1090 // (fp_to_int:v8i16 (v8f32 ..)) requires the result type to be promoted
1091 // even though v8i16 is a legal type.
1092 setOperationAction(ISD::FP_TO_SINT, MVT::v8i16, Promote);
1093 setOperationAction(ISD::FP_TO_UINT, MVT::v8i16, Promote);
1094 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
1096 setOperationAction(ISD::SINT_TO_FP, MVT::v8i16, Promote);
1097 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
1098 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal);
1100 setOperationAction(ISD::UINT_TO_FP, MVT::v8i8, Custom);
1101 setOperationAction(ISD::UINT_TO_FP, MVT::v8i16, Custom);
1103 for (MVT VT : MVT::fp_vector_valuetypes())
1104 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4f32, Legal);
1106 setOperationAction(ISD::SRL, MVT::v16i16, Custom);
1107 setOperationAction(ISD::SRL, MVT::v32i8, Custom);
1109 setOperationAction(ISD::SHL, MVT::v16i16, Custom);
1110 setOperationAction(ISD::SHL, MVT::v32i8, Custom);
1112 setOperationAction(ISD::SRA, MVT::v16i16, Custom);
1113 setOperationAction(ISD::SRA, MVT::v32i8, Custom);
1115 setOperationAction(ISD::SETCC, MVT::v32i8, Custom);
1116 setOperationAction(ISD::SETCC, MVT::v16i16, Custom);
1117 setOperationAction(ISD::SETCC, MVT::v8i32, Custom);
1118 setOperationAction(ISD::SETCC, MVT::v4i64, Custom);
1120 setOperationAction(ISD::SELECT, MVT::v4f64, Custom);
1121 setOperationAction(ISD::SELECT, MVT::v4i64, Custom);
1122 setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
1124 setOperationAction(ISD::SIGN_EXTEND, MVT::v4i64, Custom);
1125 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i32, Custom);
1126 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1127 setOperationAction(ISD::ZERO_EXTEND, MVT::v4i64, Custom);
1128 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i32, Custom);
1129 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i16, Custom);
1130 setOperationAction(ISD::ANY_EXTEND, MVT::v4i64, Custom);
1131 setOperationAction(ISD::ANY_EXTEND, MVT::v8i32, Custom);
1132 setOperationAction(ISD::ANY_EXTEND, MVT::v16i16, Custom);
1133 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1134 setOperationAction(ISD::TRUNCATE, MVT::v8i16, Custom);
1135 setOperationAction(ISD::TRUNCATE, MVT::v4i32, Custom);
1137 setOperationAction(ISD::CTPOP, MVT::v32i8, Custom);
1138 setOperationAction(ISD::CTPOP, MVT::v16i16, Custom);
1139 setOperationAction(ISD::CTPOP, MVT::v8i32, Custom);
1140 setOperationAction(ISD::CTPOP, MVT::v4i64, Custom);
1142 setOperationAction(ISD::CTTZ, MVT::v32i8, Custom);
1143 setOperationAction(ISD::CTTZ, MVT::v16i16, Custom);
1144 setOperationAction(ISD::CTTZ, MVT::v8i32, Custom);
1145 setOperationAction(ISD::CTTZ, MVT::v4i64, Custom);
1146 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v32i8, Custom);
1147 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v16i16, Custom);
1148 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v8i32, Custom);
1149 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v4i64, Custom);
1151 if (Subtarget->hasFMA() || Subtarget->hasFMA4() || Subtarget->hasAVX512()) {
1152 setOperationAction(ISD::FMA, MVT::v8f32, Legal);
1153 setOperationAction(ISD::FMA, MVT::v4f64, Legal);
1154 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
1155 setOperationAction(ISD::FMA, MVT::v2f64, Legal);
1156 setOperationAction(ISD::FMA, MVT::f32, Legal);
1157 setOperationAction(ISD::FMA, MVT::f64, Legal);
1160 if (Subtarget->hasInt256()) {
1161 setOperationAction(ISD::ADD, MVT::v4i64, Legal);
1162 setOperationAction(ISD::ADD, MVT::v8i32, Legal);
1163 setOperationAction(ISD::ADD, MVT::v16i16, Legal);
1164 setOperationAction(ISD::ADD, MVT::v32i8, Legal);
1166 setOperationAction(ISD::SUB, MVT::v4i64, Legal);
1167 setOperationAction(ISD::SUB, MVT::v8i32, Legal);
1168 setOperationAction(ISD::SUB, MVT::v16i16, Legal);
1169 setOperationAction(ISD::SUB, MVT::v32i8, Legal);
1171 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1172 setOperationAction(ISD::MUL, MVT::v8i32, Legal);
1173 setOperationAction(ISD::MUL, MVT::v16i16, Legal);
1174 setOperationAction(ISD::MUL, MVT::v32i8, Custom);
1176 setOperationAction(ISD::UMUL_LOHI, MVT::v8i32, Custom);
1177 setOperationAction(ISD::SMUL_LOHI, MVT::v8i32, Custom);
1178 setOperationAction(ISD::MULHU, MVT::v16i16, Legal);
1179 setOperationAction(ISD::MULHS, MVT::v16i16, Legal);
1181 setOperationAction(ISD::SMAX, MVT::v32i8, Legal);
1182 setOperationAction(ISD::SMAX, MVT::v16i16, Legal);
1183 setOperationAction(ISD::SMAX, MVT::v8i32, Legal);
1184 setOperationAction(ISD::UMAX, MVT::v32i8, Legal);
1185 setOperationAction(ISD::UMAX, MVT::v16i16, Legal);
1186 setOperationAction(ISD::UMAX, MVT::v8i32, Legal);
1187 setOperationAction(ISD::SMIN, MVT::v32i8, Legal);
1188 setOperationAction(ISD::SMIN, MVT::v16i16, Legal);
1189 setOperationAction(ISD::SMIN, MVT::v8i32, Legal);
1190 setOperationAction(ISD::UMIN, MVT::v32i8, Legal);
1191 setOperationAction(ISD::UMIN, MVT::v16i16, Legal);
1192 setOperationAction(ISD::UMIN, MVT::v8i32, Legal);
1194 // The custom lowering for UINT_TO_FP for v8i32 becomes interesting
1195 // when we have a 256bit-wide blend with immediate.
1196 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Custom);
1198 // AVX2 also has wider vector sign/zero extending loads, VPMOV[SZ]X
1199 setLoadExtAction(ISD::SEXTLOAD, MVT::v16i16, MVT::v16i8, Legal);
1200 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i32, MVT::v8i8, Legal);
1201 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i64, MVT::v4i8, Legal);
1202 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i32, MVT::v8i16, Legal);
1203 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i64, MVT::v4i16, Legal);
1204 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i64, MVT::v4i32, Legal);
1206 setLoadExtAction(ISD::ZEXTLOAD, MVT::v16i16, MVT::v16i8, Legal);
1207 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i32, MVT::v8i8, Legal);
1208 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i64, MVT::v4i8, Legal);
1209 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i32, MVT::v8i16, Legal);
1210 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i64, MVT::v4i16, Legal);
1211 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i64, MVT::v4i32, Legal);
1213 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
1214 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
1215 setOperationAction(ISD::ADD, MVT::v16i16, Custom);
1216 setOperationAction(ISD::ADD, MVT::v32i8, Custom);
1218 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
1219 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
1220 setOperationAction(ISD::SUB, MVT::v16i16, Custom);
1221 setOperationAction(ISD::SUB, MVT::v32i8, Custom);
1223 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1224 setOperationAction(ISD::MUL, MVT::v8i32, Custom);
1225 setOperationAction(ISD::MUL, MVT::v16i16, Custom);
1226 setOperationAction(ISD::MUL, MVT::v32i8, Custom);
1228 setOperationAction(ISD::SMAX, MVT::v32i8, Custom);
1229 setOperationAction(ISD::SMAX, MVT::v16i16, Custom);
1230 setOperationAction(ISD::SMAX, MVT::v8i32, Custom);
1231 setOperationAction(ISD::UMAX, MVT::v32i8, Custom);
1232 setOperationAction(ISD::UMAX, MVT::v16i16, Custom);
1233 setOperationAction(ISD::UMAX, MVT::v8i32, Custom);
1234 setOperationAction(ISD::SMIN, MVT::v32i8, Custom);
1235 setOperationAction(ISD::SMIN, MVT::v16i16, Custom);
1236 setOperationAction(ISD::SMIN, MVT::v8i32, Custom);
1237 setOperationAction(ISD::UMIN, MVT::v32i8, Custom);
1238 setOperationAction(ISD::UMIN, MVT::v16i16, Custom);
1239 setOperationAction(ISD::UMIN, MVT::v8i32, Custom);
1242 // In the customized shift lowering, the legal cases in AVX2 will be
1244 setOperationAction(ISD::SRL, MVT::v4i64, Custom);
1245 setOperationAction(ISD::SRL, MVT::v8i32, Custom);
1247 setOperationAction(ISD::SHL, MVT::v4i64, Custom);
1248 setOperationAction(ISD::SHL, MVT::v8i32, Custom);
1250 setOperationAction(ISD::SRA, MVT::v4i64, Custom);
1251 setOperationAction(ISD::SRA, MVT::v8i32, Custom);
1253 // Custom lower several nodes for 256-bit types.
1254 for (MVT VT : MVT::vector_valuetypes()) {
1255 if (VT.getScalarSizeInBits() >= 32) {
1256 setOperationAction(ISD::MLOAD, VT, Legal);
1257 setOperationAction(ISD::MSTORE, VT, Legal);
1259 // Extract subvector is special because the value type
1260 // (result) is 128-bit but the source is 256-bit wide.
1261 if (VT.is128BitVector()) {
1262 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1264 // Do not attempt to custom lower other non-256-bit vectors
1265 if (!VT.is256BitVector())
1268 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1269 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1270 setOperationAction(ISD::VSELECT, VT, Custom);
1271 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1272 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1273 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1274 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1275 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom);
1278 if (Subtarget->hasInt256())
1279 setOperationAction(ISD::VSELECT, MVT::v32i8, Legal);
1281 // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64.
1282 for (auto VT : { MVT::v32i8, MVT::v16i16, MVT::v8i32 }) {
1283 setOperationAction(ISD::AND, VT, Promote);
1284 AddPromotedToType (ISD::AND, VT, MVT::v4i64);
1285 setOperationAction(ISD::OR, VT, Promote);
1286 AddPromotedToType (ISD::OR, VT, MVT::v4i64);
1287 setOperationAction(ISD::XOR, VT, Promote);
1288 AddPromotedToType (ISD::XOR, VT, MVT::v4i64);
1289 setOperationAction(ISD::LOAD, VT, Promote);
1290 AddPromotedToType (ISD::LOAD, VT, MVT::v4i64);
1291 setOperationAction(ISD::SELECT, VT, Promote);
1292 AddPromotedToType (ISD::SELECT, VT, MVT::v4i64);
1296 if (!Subtarget->useSoftFloat() && Subtarget->hasAVX512()) {
1297 addRegisterClass(MVT::v16i32, &X86::VR512RegClass);
1298 addRegisterClass(MVT::v16f32, &X86::VR512RegClass);
1299 addRegisterClass(MVT::v8i64, &X86::VR512RegClass);
1300 addRegisterClass(MVT::v8f64, &X86::VR512RegClass);
1302 addRegisterClass(MVT::i1, &X86::VK1RegClass);
1303 addRegisterClass(MVT::v8i1, &X86::VK8RegClass);
1304 addRegisterClass(MVT::v16i1, &X86::VK16RegClass);
1306 for (MVT VT : MVT::fp_vector_valuetypes())
1307 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v8f32, Legal);
1309 setLoadExtAction(ISD::ZEXTLOAD, MVT::v16i32, MVT::v16i8, Legal);
1310 setLoadExtAction(ISD::SEXTLOAD, MVT::v16i32, MVT::v16i8, Legal);
1311 setLoadExtAction(ISD::ZEXTLOAD, MVT::v16i32, MVT::v16i16, Legal);
1312 setLoadExtAction(ISD::SEXTLOAD, MVT::v16i32, MVT::v16i16, Legal);
1313 setLoadExtAction(ISD::ZEXTLOAD, MVT::v32i16, MVT::v32i8, Legal);
1314 setLoadExtAction(ISD::SEXTLOAD, MVT::v32i16, MVT::v32i8, Legal);
1315 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i64, MVT::v8i8, Legal);
1316 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i64, MVT::v8i8, Legal);
1317 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i64, MVT::v8i16, Legal);
1318 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i64, MVT::v8i16, Legal);
1319 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i64, MVT::v8i32, Legal);
1320 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i64, MVT::v8i32, Legal);
1322 setOperationAction(ISD::BR_CC, MVT::i1, Expand);
1323 setOperationAction(ISD::SETCC, MVT::i1, Custom);
1324 setOperationAction(ISD::SELECT_CC, MVT::i1, Expand);
1325 setOperationAction(ISD::XOR, MVT::i1, Legal);
1326 setOperationAction(ISD::OR, MVT::i1, Legal);
1327 setOperationAction(ISD::AND, MVT::i1, Legal);
1328 setOperationAction(ISD::SUB, MVT::i1, Custom);
1329 setOperationAction(ISD::ADD, MVT::i1, Custom);
1330 setOperationAction(ISD::MUL, MVT::i1, Custom);
1331 setOperationAction(ISD::LOAD, MVT::v16f32, Legal);
1332 setOperationAction(ISD::LOAD, MVT::v8f64, Legal);
1333 setOperationAction(ISD::LOAD, MVT::v8i64, Legal);
1334 setOperationAction(ISD::LOAD, MVT::v16i32, Legal);
1335 setOperationAction(ISD::LOAD, MVT::v16i1, Legal);
1337 setOperationAction(ISD::FADD, MVT::v16f32, Legal);
1338 setOperationAction(ISD::FSUB, MVT::v16f32, Legal);
1339 setOperationAction(ISD::FMUL, MVT::v16f32, Legal);
1340 setOperationAction(ISD::FDIV, MVT::v16f32, Legal);
1341 setOperationAction(ISD::FSQRT, MVT::v16f32, Legal);
1342 setOperationAction(ISD::FNEG, MVT::v16f32, Custom);
1344 setOperationAction(ISD::FADD, MVT::v8f64, Legal);
1345 setOperationAction(ISD::FSUB, MVT::v8f64, Legal);
1346 setOperationAction(ISD::FMUL, MVT::v8f64, Legal);
1347 setOperationAction(ISD::FDIV, MVT::v8f64, Legal);
1348 setOperationAction(ISD::FSQRT, MVT::v8f64, Legal);
1349 setOperationAction(ISD::FNEG, MVT::v8f64, Custom);
1350 setOperationAction(ISD::FMA, MVT::v8f64, Legal);
1351 setOperationAction(ISD::FMA, MVT::v16f32, Legal);
1353 setOperationAction(ISD::FP_TO_SINT, MVT::v16i32, Legal);
1354 setOperationAction(ISD::FP_TO_UINT, MVT::v16i32, Legal);
1355 setOperationAction(ISD::FP_TO_UINT, MVT::v8i32, Legal);
1356 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
1357 setOperationAction(ISD::SINT_TO_FP, MVT::v16i32, Legal);
1358 setOperationAction(ISD::SINT_TO_FP, MVT::v8i1, Custom);
1359 setOperationAction(ISD::SINT_TO_FP, MVT::v16i1, Custom);
1360 setOperationAction(ISD::SINT_TO_FP, MVT::v16i8, Promote);
1361 setOperationAction(ISD::SINT_TO_FP, MVT::v16i16, Promote);
1362 setOperationAction(ISD::UINT_TO_FP, MVT::v16i32, Legal);
1363 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Legal);
1364 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
1365 setOperationAction(ISD::UINT_TO_FP, MVT::v16i8, Custom);
1366 setOperationAction(ISD::UINT_TO_FP, MVT::v16i16, Custom);
1367 setOperationAction(ISD::FP_ROUND, MVT::v8f32, Legal);
1368 setOperationAction(ISD::FP_EXTEND, MVT::v8f32, Legal);
1370 setTruncStoreAction(MVT::v8i64, MVT::v8i8, Legal);
1371 setTruncStoreAction(MVT::v8i64, MVT::v8i16, Legal);
1372 setTruncStoreAction(MVT::v8i64, MVT::v8i32, Legal);
1373 setTruncStoreAction(MVT::v16i32, MVT::v16i8, Legal);
1374 setTruncStoreAction(MVT::v16i32, MVT::v16i16, Legal);
1375 if (Subtarget->hasVLX()){
1376 setTruncStoreAction(MVT::v4i64, MVT::v4i8, Legal);
1377 setTruncStoreAction(MVT::v4i64, MVT::v4i16, Legal);
1378 setTruncStoreAction(MVT::v4i64, MVT::v4i32, Legal);
1379 setTruncStoreAction(MVT::v8i32, MVT::v8i8, Legal);
1380 setTruncStoreAction(MVT::v8i32, MVT::v8i16, Legal);
1382 setTruncStoreAction(MVT::v2i64, MVT::v2i8, Legal);
1383 setTruncStoreAction(MVT::v2i64, MVT::v2i16, Legal);
1384 setTruncStoreAction(MVT::v2i64, MVT::v2i32, Legal);
1385 setTruncStoreAction(MVT::v4i32, MVT::v4i8, Legal);
1386 setTruncStoreAction(MVT::v4i32, MVT::v4i16, Legal);
1388 setOperationAction(ISD::TRUNCATE, MVT::i1, Custom);
1389 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1390 setOperationAction(ISD::TRUNCATE, MVT::v8i32, Custom);
1391 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i1, Custom);
1392 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i1, Custom);
1393 if (Subtarget->hasDQI()) {
1394 setOperationAction(ISD::TRUNCATE, MVT::v2i1, Custom);
1395 setOperationAction(ISD::TRUNCATE, MVT::v4i1, Custom);
1397 setOperationAction(ISD::SINT_TO_FP, MVT::v8i64, Legal);
1398 setOperationAction(ISD::UINT_TO_FP, MVT::v8i64, Legal);
1399 setOperationAction(ISD::FP_TO_SINT, MVT::v8i64, Legal);
1400 setOperationAction(ISD::FP_TO_UINT, MVT::v8i64, Legal);
1401 if (Subtarget->hasVLX()) {
1402 setOperationAction(ISD::SINT_TO_FP, MVT::v4i64, Legal);
1403 setOperationAction(ISD::SINT_TO_FP, MVT::v2i64, Legal);
1404 setOperationAction(ISD::UINT_TO_FP, MVT::v4i64, Legal);
1405 setOperationAction(ISD::UINT_TO_FP, MVT::v2i64, Legal);
1406 setOperationAction(ISD::FP_TO_SINT, MVT::v4i64, Legal);
1407 setOperationAction(ISD::FP_TO_SINT, MVT::v2i64, Legal);
1408 setOperationAction(ISD::FP_TO_UINT, MVT::v4i64, Legal);
1409 setOperationAction(ISD::FP_TO_UINT, MVT::v2i64, Legal);
1412 if (Subtarget->hasVLX()) {
1413 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
1414 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Legal);
1415 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
1416 setOperationAction(ISD::FP_TO_UINT, MVT::v8i32, Legal);
1417 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
1418 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
1419 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
1420 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
1422 setOperationAction(ISD::TRUNCATE, MVT::v8i1, Custom);
1423 setOperationAction(ISD::TRUNCATE, MVT::v16i1, Custom);
1424 setOperationAction(ISD::TRUNCATE, MVT::v16i16, Custom);
1425 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i32, Custom);
1426 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i64, Custom);
1427 setOperationAction(ISD::ANY_EXTEND, MVT::v16i32, Custom);
1428 setOperationAction(ISD::ANY_EXTEND, MVT::v8i64, Custom);
1429 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i32, Custom);
1430 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i64, Custom);
1431 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i8, Custom);
1432 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i16, Custom);
1433 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1434 if (Subtarget->hasDQI()) {
1435 setOperationAction(ISD::SIGN_EXTEND, MVT::v4i32, Custom);
1436 setOperationAction(ISD::SIGN_EXTEND, MVT::v2i64, Custom);
1438 setOperationAction(ISD::FFLOOR, MVT::v16f32, Legal);
1439 setOperationAction(ISD::FFLOOR, MVT::v8f64, Legal);
1440 setOperationAction(ISD::FCEIL, MVT::v16f32, Legal);
1441 setOperationAction(ISD::FCEIL, MVT::v8f64, Legal);
1442 setOperationAction(ISD::FTRUNC, MVT::v16f32, Legal);
1443 setOperationAction(ISD::FTRUNC, MVT::v8f64, Legal);
1444 setOperationAction(ISD::FRINT, MVT::v16f32, Legal);
1445 setOperationAction(ISD::FRINT, MVT::v8f64, Legal);
1446 setOperationAction(ISD::FNEARBYINT, MVT::v16f32, Legal);
1447 setOperationAction(ISD::FNEARBYINT, MVT::v8f64, Legal);
1449 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f64, Custom);
1450 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i64, Custom);
1451 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16f32, Custom);
1452 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i32, Custom);
1453 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i1, Custom);
1455 setOperationAction(ISD::SETCC, MVT::v16i1, Custom);
1456 setOperationAction(ISD::SETCC, MVT::v8i1, Custom);
1458 setOperationAction(ISD::MUL, MVT::v8i64, Custom);
1460 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i1, Custom);
1461 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i1, Custom);
1462 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i1, Custom);
1463 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i1, Custom);
1464 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i1, Custom);
1465 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i1, Custom);
1466 setOperationAction(ISD::SELECT, MVT::v8f64, Custom);
1467 setOperationAction(ISD::SELECT, MVT::v8i64, Custom);
1468 setOperationAction(ISD::SELECT, MVT::v16f32, Custom);
1469 setOperationAction(ISD::SELECT, MVT::v16i1, Custom);
1470 setOperationAction(ISD::SELECT, MVT::v8i1, Custom);
1472 setOperationAction(ISD::SMAX, MVT::v16i32, Legal);
1473 setOperationAction(ISD::SMAX, MVT::v8i64, Legal);
1474 setOperationAction(ISD::UMAX, MVT::v16i32, Legal);
1475 setOperationAction(ISD::UMAX, MVT::v8i64, Legal);
1476 setOperationAction(ISD::SMIN, MVT::v16i32, Legal);
1477 setOperationAction(ISD::SMIN, MVT::v8i64, Legal);
1478 setOperationAction(ISD::UMIN, MVT::v16i32, Legal);
1479 setOperationAction(ISD::UMIN, MVT::v8i64, Legal);
1481 setOperationAction(ISD::ADD, MVT::v8i64, Legal);
1482 setOperationAction(ISD::ADD, MVT::v16i32, Legal);
1484 setOperationAction(ISD::SUB, MVT::v8i64, Legal);
1485 setOperationAction(ISD::SUB, MVT::v16i32, Legal);
1487 setOperationAction(ISD::MUL, MVT::v16i32, Legal);
1489 setOperationAction(ISD::SRL, MVT::v8i64, Custom);
1490 setOperationAction(ISD::SRL, MVT::v16i32, Custom);
1492 setOperationAction(ISD::SHL, MVT::v8i64, Custom);
1493 setOperationAction(ISD::SHL, MVT::v16i32, Custom);
1495 setOperationAction(ISD::SRA, MVT::v8i64, Custom);
1496 setOperationAction(ISD::SRA, MVT::v16i32, Custom);
1498 setOperationAction(ISD::AND, MVT::v8i64, Legal);
1499 setOperationAction(ISD::OR, MVT::v8i64, Legal);
1500 setOperationAction(ISD::XOR, MVT::v8i64, Legal);
1501 setOperationAction(ISD::AND, MVT::v16i32, Legal);
1502 setOperationAction(ISD::OR, MVT::v16i32, Legal);
1503 setOperationAction(ISD::XOR, MVT::v16i32, Legal);
1505 if (Subtarget->hasCDI()) {
1506 setOperationAction(ISD::CTLZ, MVT::v8i64, Legal);
1507 setOperationAction(ISD::CTLZ, MVT::v16i32, Legal);
1508 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v8i64, Legal);
1509 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v16i32, Legal);
1511 setOperationAction(ISD::CTLZ, MVT::v8i16, Custom);
1512 setOperationAction(ISD::CTLZ, MVT::v16i8, Custom);
1513 setOperationAction(ISD::CTLZ, MVT::v16i16, Custom);
1514 setOperationAction(ISD::CTLZ, MVT::v32i8, Custom);
1515 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v8i16, Custom);
1516 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v16i8, Custom);
1517 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v16i16, Custom);
1518 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v32i8, Custom);
1520 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v8i64, Custom);
1521 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v16i32, Custom);
1523 if (Subtarget->hasVLX()) {
1524 setOperationAction(ISD::CTLZ, MVT::v4i64, Legal);
1525 setOperationAction(ISD::CTLZ, MVT::v8i32, Legal);
1526 setOperationAction(ISD::CTLZ, MVT::v2i64, Legal);
1527 setOperationAction(ISD::CTLZ, MVT::v4i32, Legal);
1528 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v4i64, Legal);
1529 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v8i32, Legal);
1530 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v2i64, Legal);
1531 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v4i32, Legal);
1533 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v4i64, Custom);
1534 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v8i32, Custom);
1535 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v2i64, Custom);
1536 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v4i32, Custom);
1538 setOperationAction(ISD::CTLZ, MVT::v4i64, Custom);
1539 setOperationAction(ISD::CTLZ, MVT::v8i32, Custom);
1540 setOperationAction(ISD::CTLZ, MVT::v2i64, Custom);
1541 setOperationAction(ISD::CTLZ, MVT::v4i32, Custom);
1542 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v4i64, Custom);
1543 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v8i32, Custom);
1544 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v2i64, Custom);
1545 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v4i32, Custom);
1547 } // Subtarget->hasCDI()
1549 if (Subtarget->hasDQI()) {
1550 setOperationAction(ISD::MUL, MVT::v2i64, Legal);
1551 setOperationAction(ISD::MUL, MVT::v4i64, Legal);
1552 setOperationAction(ISD::MUL, MVT::v8i64, Legal);
1554 // Custom lower several nodes.
1555 for (MVT VT : MVT::vector_valuetypes()) {
1556 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1558 setOperationAction(ISD::AND, VT, Legal);
1559 setOperationAction(ISD::OR, VT, Legal);
1560 setOperationAction(ISD::XOR, VT, Legal);
1562 if (EltSize >= 32 && VT.getSizeInBits() <= 512) {
1563 setOperationAction(ISD::MGATHER, VT, Custom);
1564 setOperationAction(ISD::MSCATTER, VT, Custom);
1566 // Extract subvector is special because the value type
1567 // (result) is 256/128-bit but the source is 512-bit wide.
1568 if (VT.is128BitVector() || VT.is256BitVector()) {
1569 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1571 if (VT.getVectorElementType() == MVT::i1)
1572 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal);
1574 // Do not attempt to custom lower other non-512-bit vectors
1575 if (!VT.is512BitVector())
1578 if (EltSize >= 32) {
1579 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1580 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1581 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1582 setOperationAction(ISD::VSELECT, VT, Legal);
1583 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1584 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1585 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1586 setOperationAction(ISD::MLOAD, VT, Legal);
1587 setOperationAction(ISD::MSTORE, VT, Legal);
1590 for (auto VT : { MVT::v64i8, MVT::v32i16, MVT::v16i32 }) {
1591 setOperationAction(ISD::SELECT, VT, Promote);
1592 AddPromotedToType (ISD::SELECT, VT, MVT::v8i64);
1596 if (!Subtarget->useSoftFloat() && Subtarget->hasBWI()) {
1597 addRegisterClass(MVT::v32i16, &X86::VR512RegClass);
1598 addRegisterClass(MVT::v64i8, &X86::VR512RegClass);
1600 addRegisterClass(MVT::v32i1, &X86::VK32RegClass);
1601 addRegisterClass(MVT::v64i1, &X86::VK64RegClass);
1603 setOperationAction(ISD::LOAD, MVT::v32i16, Legal);
1604 setOperationAction(ISD::LOAD, MVT::v64i8, Legal);
1605 setOperationAction(ISD::SETCC, MVT::v32i1, Custom);
1606 setOperationAction(ISD::SETCC, MVT::v64i1, Custom);
1607 setOperationAction(ISD::ADD, MVT::v32i16, Legal);
1608 setOperationAction(ISD::ADD, MVT::v64i8, Legal);
1609 setOperationAction(ISD::SUB, MVT::v32i16, Legal);
1610 setOperationAction(ISD::SUB, MVT::v64i8, Legal);
1611 setOperationAction(ISD::MUL, MVT::v32i16, Legal);
1612 setOperationAction(ISD::MULHS, MVT::v32i16, Legal);
1613 setOperationAction(ISD::MULHU, MVT::v32i16, Legal);
1614 setOperationAction(ISD::CONCAT_VECTORS, MVT::v32i1, Custom);
1615 setOperationAction(ISD::CONCAT_VECTORS, MVT::v64i1, Custom);
1616 setOperationAction(ISD::CONCAT_VECTORS, MVT::v32i16, Custom);
1617 setOperationAction(ISD::CONCAT_VECTORS, MVT::v64i8, Custom);
1618 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v32i1, Custom);
1619 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v64i1, Custom);
1620 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v32i16, Custom);
1621 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v64i8, Custom);
1622 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v32i16, Custom);
1623 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v64i8, Custom);
1624 setOperationAction(ISD::SELECT, MVT::v32i1, Custom);
1625 setOperationAction(ISD::SELECT, MVT::v64i1, Custom);
1626 setOperationAction(ISD::SIGN_EXTEND, MVT::v32i8, Custom);
1627 setOperationAction(ISD::ZERO_EXTEND, MVT::v32i8, Custom);
1628 setOperationAction(ISD::SIGN_EXTEND, MVT::v32i16, Custom);
1629 setOperationAction(ISD::ZERO_EXTEND, MVT::v32i16, Custom);
1630 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v32i16, Custom);
1631 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v64i8, Custom);
1632 setOperationAction(ISD::SIGN_EXTEND, MVT::v64i8, Custom);
1633 setOperationAction(ISD::ZERO_EXTEND, MVT::v64i8, Custom);
1634 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v32i1, Custom);
1635 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v64i1, Custom);
1636 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v32i16, Custom);
1637 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v64i8, Custom);
1638 setOperationAction(ISD::VSELECT, MVT::v32i16, Legal);
1639 setOperationAction(ISD::VSELECT, MVT::v64i8, Legal);
1640 setOperationAction(ISD::TRUNCATE, MVT::v32i1, Custom);
1641 setOperationAction(ISD::TRUNCATE, MVT::v64i1, Custom);
1642 setOperationAction(ISD::TRUNCATE, MVT::v32i8, Custom);
1643 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v32i1, Custom);
1644 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v64i1, Custom);
1646 setOperationAction(ISD::SMAX, MVT::v64i8, Legal);
1647 setOperationAction(ISD::SMAX, MVT::v32i16, Legal);
1648 setOperationAction(ISD::UMAX, MVT::v64i8, Legal);
1649 setOperationAction(ISD::UMAX, MVT::v32i16, Legal);
1650 setOperationAction(ISD::SMIN, MVT::v64i8, Legal);
1651 setOperationAction(ISD::SMIN, MVT::v32i16, Legal);
1652 setOperationAction(ISD::UMIN, MVT::v64i8, Legal);
1653 setOperationAction(ISD::UMIN, MVT::v32i16, Legal);
1655 setTruncStoreAction(MVT::v32i16, MVT::v32i8, Legal);
1656 setTruncStoreAction(MVT::v16i16, MVT::v16i8, Legal);
1657 if (Subtarget->hasVLX())
1658 setTruncStoreAction(MVT::v8i16, MVT::v8i8, Legal);
1660 if (Subtarget->hasCDI()) {
1661 setOperationAction(ISD::CTLZ, MVT::v32i16, Custom);
1662 setOperationAction(ISD::CTLZ, MVT::v64i8, Custom);
1663 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v32i16, Custom);
1664 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v64i8, Custom);
1667 for (auto VT : { MVT::v64i8, MVT::v32i16 }) {
1668 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1669 setOperationAction(ISD::VSELECT, VT, Legal);
1673 if (!Subtarget->useSoftFloat() && Subtarget->hasVLX()) {
1674 addRegisterClass(MVT::v4i1, &X86::VK4RegClass);
1675 addRegisterClass(MVT::v2i1, &X86::VK2RegClass);
1677 setOperationAction(ISD::SETCC, MVT::v4i1, Custom);
1678 setOperationAction(ISD::SETCC, MVT::v2i1, Custom);
1679 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i1, Custom);
1680 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i1, Custom);
1681 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v8i1, Custom);
1682 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v4i1, Custom);
1683 setOperationAction(ISD::SELECT, MVT::v4i1, Custom);
1684 setOperationAction(ISD::SELECT, MVT::v2i1, Custom);
1685 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i1, Custom);
1686 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i1, Custom);
1687 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i1, Custom);
1688 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i1, Custom);
1690 setOperationAction(ISD::AND, MVT::v8i32, Legal);
1691 setOperationAction(ISD::OR, MVT::v8i32, Legal);
1692 setOperationAction(ISD::XOR, MVT::v8i32, Legal);
1693 setOperationAction(ISD::AND, MVT::v4i32, Legal);
1694 setOperationAction(ISD::OR, MVT::v4i32, Legal);
1695 setOperationAction(ISD::XOR, MVT::v4i32, Legal);
1696 setOperationAction(ISD::SRA, MVT::v2i64, Custom);
1697 setOperationAction(ISD::SRA, MVT::v4i64, Custom);
1699 setOperationAction(ISD::SMAX, MVT::v2i64, Legal);
1700 setOperationAction(ISD::SMAX, MVT::v4i64, Legal);
1701 setOperationAction(ISD::UMAX, MVT::v2i64, Legal);
1702 setOperationAction(ISD::UMAX, MVT::v4i64, Legal);
1703 setOperationAction(ISD::SMIN, MVT::v2i64, Legal);
1704 setOperationAction(ISD::SMIN, MVT::v4i64, Legal);
1705 setOperationAction(ISD::UMIN, MVT::v2i64, Legal);
1706 setOperationAction(ISD::UMIN, MVT::v4i64, Legal);
1709 // We want to custom lower some of our intrinsics.
1710 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
1711 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
1712 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
1713 if (!Subtarget->is64Bit())
1714 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i64, Custom);
1716 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't
1717 // handle type legalization for these operations here.
1719 // FIXME: We really should do custom legalization for addition and
1720 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better
1721 // than generic legalization for 64-bit multiplication-with-overflow, though.
1722 for (auto VT : { MVT::i8, MVT::i16, MVT::i32, MVT::i64 }) {
1723 if (VT == MVT::i64 && !Subtarget->is64Bit())
1725 // Add/Sub/Mul with overflow operations are custom lowered.
1726 setOperationAction(ISD::SADDO, VT, Custom);
1727 setOperationAction(ISD::UADDO, VT, Custom);
1728 setOperationAction(ISD::SSUBO, VT, Custom);
1729 setOperationAction(ISD::USUBO, VT, Custom);
1730 setOperationAction(ISD::SMULO, VT, Custom);
1731 setOperationAction(ISD::UMULO, VT, Custom);
1734 if (!Subtarget->is64Bit()) {
1735 // These libcalls are not available in 32-bit.
1736 setLibcallName(RTLIB::SHL_I128, nullptr);
1737 setLibcallName(RTLIB::SRL_I128, nullptr);
1738 setLibcallName(RTLIB::SRA_I128, nullptr);
1741 // Combine sin / cos into one node or libcall if possible.
1742 if (Subtarget->hasSinCos()) {
1743 setLibcallName(RTLIB::SINCOS_F32, "sincosf");
1744 setLibcallName(RTLIB::SINCOS_F64, "sincos");
1745 if (Subtarget->isTargetDarwin()) {
1746 // For MacOSX, we don't want the normal expansion of a libcall to sincos.
1747 // We want to issue a libcall to __sincos_stret to avoid memory traffic.
1748 setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
1749 setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
1753 if (Subtarget->isTargetWin64()) {
1754 setOperationAction(ISD::SDIV, MVT::i128, Custom);
1755 setOperationAction(ISD::UDIV, MVT::i128, Custom);
1756 setOperationAction(ISD::SREM, MVT::i128, Custom);
1757 setOperationAction(ISD::UREM, MVT::i128, Custom);
1758 setOperationAction(ISD::SDIVREM, MVT::i128, Custom);
1759 setOperationAction(ISD::UDIVREM, MVT::i128, Custom);
1762 // We have target-specific dag combine patterns for the following nodes:
1763 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
1764 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
1765 setTargetDAGCombine(ISD::BITCAST);
1766 setTargetDAGCombine(ISD::VSELECT);
1767 setTargetDAGCombine(ISD::SELECT);
1768 setTargetDAGCombine(ISD::SHL);
1769 setTargetDAGCombine(ISD::SRA);
1770 setTargetDAGCombine(ISD::SRL);
1771 setTargetDAGCombine(ISD::OR);
1772 setTargetDAGCombine(ISD::AND);
1773 setTargetDAGCombine(ISD::ADD);
1774 setTargetDAGCombine(ISD::FADD);
1775 setTargetDAGCombine(ISD::FSUB);
1776 setTargetDAGCombine(ISD::FMA);
1777 setTargetDAGCombine(ISD::SUB);
1778 setTargetDAGCombine(ISD::LOAD);
1779 setTargetDAGCombine(ISD::MLOAD);
1780 setTargetDAGCombine(ISD::STORE);
1781 setTargetDAGCombine(ISD::MSTORE);
1782 setTargetDAGCombine(ISD::ZERO_EXTEND);
1783 setTargetDAGCombine(ISD::ANY_EXTEND);
1784 setTargetDAGCombine(ISD::SIGN_EXTEND);
1785 setTargetDAGCombine(ISD::SIGN_EXTEND_INREG);
1786 setTargetDAGCombine(ISD::SINT_TO_FP);
1787 setTargetDAGCombine(ISD::UINT_TO_FP);
1788 setTargetDAGCombine(ISD::SETCC);
1789 setTargetDAGCombine(ISD::BUILD_VECTOR);
1790 setTargetDAGCombine(ISD::MUL);
1791 setTargetDAGCombine(ISD::XOR);
1793 computeRegisterProperties(Subtarget->getRegisterInfo());
1795 MaxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
1796 MaxStoresPerMemsetOptSize = 8;
1797 MaxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores
1798 MaxStoresPerMemcpyOptSize = 4;
1799 MaxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores
1800 MaxStoresPerMemmoveOptSize = 4;
1801 setPrefLoopAlignment(4); // 2^4 bytes.
1803 // A predictable cmov does not hurt on an in-order CPU.
1804 // FIXME: Use a CPU attribute to trigger this, not a CPU model.
1805 PredictableSelectIsExpensive = !Subtarget->isAtom();
1806 EnableExtLdPromotion = true;
1807 setPrefFunctionAlignment(4); // 2^4 bytes.
1809 verifyIntrinsicTables();
1812 // This has so far only been implemented for 64-bit MachO.
1813 bool X86TargetLowering::useLoadStackGuardNode() const {
1814 return Subtarget->isTargetMachO() && Subtarget->is64Bit();
1817 TargetLoweringBase::LegalizeTypeAction
1818 X86TargetLowering::getPreferredVectorAction(EVT VT) const {
1819 if (ExperimentalVectorWideningLegalization &&
1820 VT.getVectorNumElements() != 1 &&
1821 VT.getVectorElementType().getSimpleVT() != MVT::i1)
1822 return TypeWidenVector;
1824 return TargetLoweringBase::getPreferredVectorAction(VT);
1827 EVT X86TargetLowering::getSetCCResultType(const DataLayout &DL, LLVMContext &,
1830 return Subtarget->hasAVX512() ? MVT::i1: MVT::i8;
1832 if (VT.isSimple()) {
1833 MVT VVT = VT.getSimpleVT();
1834 const unsigned NumElts = VVT.getVectorNumElements();
1835 const MVT EltVT = VVT.getVectorElementType();
1836 if (VVT.is512BitVector()) {
1837 if (Subtarget->hasAVX512())
1838 if (EltVT == MVT::i32 || EltVT == MVT::i64 ||
1839 EltVT == MVT::f32 || EltVT == MVT::f64)
1841 case 8: return MVT::v8i1;
1842 case 16: return MVT::v16i1;
1844 if (Subtarget->hasBWI())
1845 if (EltVT == MVT::i8 || EltVT == MVT::i16)
1847 case 32: return MVT::v32i1;
1848 case 64: return MVT::v64i1;
1852 if (VVT.is256BitVector() || VVT.is128BitVector()) {
1853 if (Subtarget->hasVLX())
1854 if (EltVT == MVT::i32 || EltVT == MVT::i64 ||
1855 EltVT == MVT::f32 || EltVT == MVT::f64)
1857 case 2: return MVT::v2i1;
1858 case 4: return MVT::v4i1;
1859 case 8: return MVT::v8i1;
1861 if (Subtarget->hasBWI() && Subtarget->hasVLX())
1862 if (EltVT == MVT::i8 || EltVT == MVT::i16)
1864 case 8: return MVT::v8i1;
1865 case 16: return MVT::v16i1;
1866 case 32: return MVT::v32i1;
1871 return VT.changeVectorElementTypeToInteger();
1874 /// Helper for getByValTypeAlignment to determine
1875 /// the desired ByVal argument alignment.
1876 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) {
1879 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1880 if (VTy->getBitWidth() == 128)
1882 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1883 unsigned EltAlign = 0;
1884 getMaxByValAlign(ATy->getElementType(), EltAlign);
1885 if (EltAlign > MaxAlign)
1886 MaxAlign = EltAlign;
1887 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
1888 for (auto *EltTy : STy->elements()) {
1889 unsigned EltAlign = 0;
1890 getMaxByValAlign(EltTy, EltAlign);
1891 if (EltAlign > MaxAlign)
1892 MaxAlign = EltAlign;
1899 /// Return the desired alignment for ByVal aggregate
1900 /// function arguments in the caller parameter area. For X86, aggregates
1901 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
1902 /// are at 4-byte boundaries.
1903 unsigned X86TargetLowering::getByValTypeAlignment(Type *Ty,
1904 const DataLayout &DL) const {
1905 if (Subtarget->is64Bit()) {
1906 // Max of 8 and alignment of type.
1907 unsigned TyAlign = DL.getABITypeAlignment(Ty);
1914 if (Subtarget->hasSSE1())
1915 getMaxByValAlign(Ty, Align);
1919 /// Returns the target specific optimal type for load
1920 /// and store operations as a result of memset, memcpy, and memmove
1921 /// lowering. If DstAlign is zero that means it's safe to destination
1922 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
1923 /// means there isn't a need to check it against alignment requirement,
1924 /// probably because the source does not need to be loaded. If 'IsMemset' is
1925 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
1926 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
1927 /// source is constant so it does not need to be loaded.
1928 /// It returns EVT::Other if the type should be determined using generic
1929 /// target-independent logic.
1931 X86TargetLowering::getOptimalMemOpType(uint64_t Size,
1932 unsigned DstAlign, unsigned SrcAlign,
1933 bool IsMemset, bool ZeroMemset,
1935 MachineFunction &MF) const {
1936 const Function *F = MF.getFunction();
1937 if ((!IsMemset || ZeroMemset) &&
1938 !F->hasFnAttribute(Attribute::NoImplicitFloat)) {
1940 (!Subtarget->isUnalignedMem16Slow() ||
1941 ((DstAlign == 0 || DstAlign >= 16) &&
1942 (SrcAlign == 0 || SrcAlign >= 16)))) {
1944 // FIXME: Check if unaligned 32-byte accesses are slow.
1945 if (Subtarget->hasInt256())
1947 if (Subtarget->hasFp256())
1950 if (Subtarget->hasSSE2())
1952 if (Subtarget->hasSSE1())
1954 } else if (!MemcpyStrSrc && Size >= 8 &&
1955 !Subtarget->is64Bit() &&
1956 Subtarget->hasSSE2()) {
1957 // Do not use f64 to lower memcpy if source is string constant. It's
1958 // better to use i32 to avoid the loads.
1962 // This is a compromise. If we reach here, unaligned accesses may be slow on
1963 // this target. However, creating smaller, aligned accesses could be even
1964 // slower and would certainly be a lot more code.
1965 if (Subtarget->is64Bit() && Size >= 8)
1970 bool X86TargetLowering::isSafeMemOpType(MVT VT) const {
1972 return X86ScalarSSEf32;
1973 else if (VT == MVT::f64)
1974 return X86ScalarSSEf64;
1979 X86TargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
1984 switch (VT.getSizeInBits()) {
1986 // 8-byte and under are always assumed to be fast.
1990 *Fast = !Subtarget->isUnalignedMem16Slow();
1993 *Fast = !Subtarget->isUnalignedMem32Slow();
1995 // TODO: What about AVX-512 (512-bit) accesses?
1998 // Misaligned accesses of any size are always allowed.
2002 /// Return the entry encoding for a jump table in the
2003 /// current function. The returned value is a member of the
2004 /// MachineJumpTableInfo::JTEntryKind enum.
2005 unsigned X86TargetLowering::getJumpTableEncoding() const {
2006 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
2008 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
2009 Subtarget->isPICStyleGOT())
2010 return MachineJumpTableInfo::EK_Custom32;
2012 // Otherwise, use the normal jump table encoding heuristics.
2013 return TargetLowering::getJumpTableEncoding();
2016 bool X86TargetLowering::useSoftFloat() const {
2017 return Subtarget->useSoftFloat();
2021 X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
2022 const MachineBasicBlock *MBB,
2023 unsigned uid,MCContext &Ctx) const{
2024 assert(MBB->getParent()->getTarget().getRelocationModel() == Reloc::PIC_ &&
2025 Subtarget->isPICStyleGOT());
2026 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
2028 return MCSymbolRefExpr::create(MBB->getSymbol(),
2029 MCSymbolRefExpr::VK_GOTOFF, Ctx);
2032 /// Returns relocation base for the given PIC jumptable.
2033 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
2034 SelectionDAG &DAG) const {
2035 if (!Subtarget->is64Bit())
2036 // This doesn't have SDLoc associated with it, but is not really the
2037 // same as a Register.
2038 return DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(),
2039 getPointerTy(DAG.getDataLayout()));
2043 /// This returns the relocation base for the given PIC jumptable,
2044 /// the same as getPICJumpTableRelocBase, but as an MCExpr.
2045 const MCExpr *X86TargetLowering::
2046 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
2047 MCContext &Ctx) const {
2048 // X86-64 uses RIP relative addressing based on the jump table label.
2049 if (Subtarget->isPICStyleRIPRel())
2050 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
2052 // Otherwise, the reference is relative to the PIC base.
2053 return MCSymbolRefExpr::create(MF->getPICBaseSymbol(), Ctx);
2056 std::pair<const TargetRegisterClass *, uint8_t>
2057 X86TargetLowering::findRepresentativeClass(const TargetRegisterInfo *TRI,
2059 const TargetRegisterClass *RRC = nullptr;
2061 switch (VT.SimpleTy) {
2063 return TargetLowering::findRepresentativeClass(TRI, VT);
2064 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
2065 RRC = Subtarget->is64Bit() ? &X86::GR64RegClass : &X86::GR32RegClass;
2068 RRC = &X86::VR64RegClass;
2070 case MVT::f32: case MVT::f64:
2071 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
2072 case MVT::v4f32: case MVT::v2f64:
2073 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32:
2075 RRC = &X86::VR128RegClass;
2078 return std::make_pair(RRC, Cost);
2081 bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace,
2082 unsigned &Offset) const {
2083 if (!Subtarget->isTargetLinux())
2086 if (Subtarget->is64Bit()) {
2087 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs:
2089 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
2101 Value *X86TargetLowering::getSafeStackPointerLocation(IRBuilder<> &IRB) const {
2102 if (!Subtarget->isTargetAndroid())
2103 return TargetLowering::getSafeStackPointerLocation(IRB);
2105 // Android provides a fixed TLS slot for the SafeStack pointer. See the
2106 // definition of TLS_SLOT_SAFESTACK in
2107 // https://android.googlesource.com/platform/bionic/+/master/libc/private/bionic_tls.h
2108 unsigned AddressSpace, Offset;
2109 if (Subtarget->is64Bit()) {
2110 // %fs:0x48, unless we're using a Kernel code model, in which case it's %gs:
2112 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
2122 return ConstantExpr::getIntToPtr(
2123 ConstantInt::get(Type::getInt32Ty(IRB.getContext()), Offset),
2124 Type::getInt8PtrTy(IRB.getContext())->getPointerTo(AddressSpace));
2127 bool X86TargetLowering::isNoopAddrSpaceCast(unsigned SrcAS,
2128 unsigned DestAS) const {
2129 assert(SrcAS != DestAS && "Expected different address spaces!");
2131 return SrcAS < 256 && DestAS < 256;
2134 //===----------------------------------------------------------------------===//
2135 // Return Value Calling Convention Implementation
2136 //===----------------------------------------------------------------------===//
2138 #include "X86GenCallingConv.inc"
2140 bool X86TargetLowering::CanLowerReturn(
2141 CallingConv::ID CallConv, MachineFunction &MF, bool isVarArg,
2142 const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context) const {
2143 SmallVector<CCValAssign, 16> RVLocs;
2144 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
2145 return CCInfo.CheckReturn(Outs, RetCC_X86);
2148 const MCPhysReg *X86TargetLowering::getScratchRegisters(CallingConv::ID) const {
2149 static const MCPhysReg ScratchRegs[] = { X86::R11, 0 };
2154 X86TargetLowering::LowerReturn(SDValue Chain,
2155 CallingConv::ID CallConv, bool isVarArg,
2156 const SmallVectorImpl<ISD::OutputArg> &Outs,
2157 const SmallVectorImpl<SDValue> &OutVals,
2158 SDLoc dl, SelectionDAG &DAG) const {
2159 MachineFunction &MF = DAG.getMachineFunction();
2160 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2162 SmallVector<CCValAssign, 16> RVLocs;
2163 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, *DAG.getContext());
2164 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
2167 SmallVector<SDValue, 6> RetOps;
2168 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
2169 // Operand #1 = Bytes To Pop
2170 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(), dl,
2173 // Copy the result values into the output registers.
2174 for (unsigned i = 0; i != RVLocs.size(); ++i) {
2175 CCValAssign &VA = RVLocs[i];
2176 assert(VA.isRegLoc() && "Can only return in registers!");
2177 SDValue ValToCopy = OutVals[i];
2178 EVT ValVT = ValToCopy.getValueType();
2180 // Promote values to the appropriate types.
2181 if (VA.getLocInfo() == CCValAssign::SExt)
2182 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy);
2183 else if (VA.getLocInfo() == CCValAssign::ZExt)
2184 ValToCopy = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ValToCopy);
2185 else if (VA.getLocInfo() == CCValAssign::AExt) {
2186 if (ValVT.isVector() && ValVT.getVectorElementType() == MVT::i1)
2187 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy);
2189 ValToCopy = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ValToCopy);
2191 else if (VA.getLocInfo() == CCValAssign::BCvt)
2192 ValToCopy = DAG.getBitcast(VA.getLocVT(), ValToCopy);
2194 assert(VA.getLocInfo() != CCValAssign::FPExt &&
2195 "Unexpected FP-extend for return value.");
2197 // If this is x86-64, and we disabled SSE, we can't return FP values,
2198 // or SSE or MMX vectors.
2199 if ((ValVT == MVT::f32 || ValVT == MVT::f64 ||
2200 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) &&
2201 (Subtarget->is64Bit() && !Subtarget->hasSSE1())) {
2202 report_fatal_error("SSE register return with SSE disabled");
2204 // Likewise we can't return F64 values with SSE1 only. gcc does so, but
2205 // llvm-gcc has never done it right and no one has noticed, so this
2206 // should be OK for now.
2207 if (ValVT == MVT::f64 &&
2208 (Subtarget->is64Bit() && !Subtarget->hasSSE2()))
2209 report_fatal_error("SSE2 register return with SSE2 disabled");
2211 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
2212 // the RET instruction and handled by the FP Stackifier.
2213 if (VA.getLocReg() == X86::FP0 ||
2214 VA.getLocReg() == X86::FP1) {
2215 // If this is a copy from an xmm register to ST(0), use an FPExtend to
2216 // change the value to the FP stack register class.
2217 if (isScalarFPTypeInSSEReg(VA.getValVT()))
2218 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
2219 RetOps.push_back(ValToCopy);
2220 // Don't emit a copytoreg.
2224 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
2225 // which is returned in RAX / RDX.
2226 if (Subtarget->is64Bit()) {
2227 if (ValVT == MVT::x86mmx) {
2228 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
2229 ValToCopy = DAG.getBitcast(MVT::i64, ValToCopy);
2230 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
2232 // If we don't have SSE2 available, convert to v4f32 so the generated
2233 // register is legal.
2234 if (!Subtarget->hasSSE2())
2235 ValToCopy = DAG.getBitcast(MVT::v4f32, ValToCopy);
2240 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
2241 Flag = Chain.getValue(1);
2242 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2245 // All x86 ABIs require that for returning structs by value we copy
2246 // the sret argument into %rax/%eax (depending on ABI) for the return.
2247 // We saved the argument into a virtual register in the entry block,
2248 // so now we copy the value out and into %rax/%eax.
2250 // Checking Function.hasStructRetAttr() here is insufficient because the IR
2251 // may not have an explicit sret argument. If FuncInfo.CanLowerReturn is
2252 // false, then an sret argument may be implicitly inserted in the SelDAG. In
2253 // either case FuncInfo->setSRetReturnReg() will have been called.
2254 if (unsigned SRetReg = FuncInfo->getSRetReturnReg()) {
2255 SDValue Val = DAG.getCopyFromReg(Chain, dl, SRetReg,
2256 getPointerTy(MF.getDataLayout()));
2259 = (Subtarget->is64Bit() && !Subtarget->isTarget64BitILP32()) ?
2260 X86::RAX : X86::EAX;
2261 Chain = DAG.getCopyToReg(Chain, dl, RetValReg, Val, Flag);
2262 Flag = Chain.getValue(1);
2264 // RAX/EAX now acts like a return value.
2266 DAG.getRegister(RetValReg, getPointerTy(DAG.getDataLayout())));
2269 RetOps[0] = Chain; // Update chain.
2271 // Add the flag if we have it.
2273 RetOps.push_back(Flag);
2275 return DAG.getNode(X86ISD::RET_FLAG, dl, MVT::Other, RetOps);
2278 bool X86TargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
2279 if (N->getNumValues() != 1)
2281 if (!N->hasNUsesOfValue(1, 0))
2284 SDValue TCChain = Chain;
2285 SDNode *Copy = *N->use_begin();
2286 if (Copy->getOpcode() == ISD::CopyToReg) {
2287 // If the copy has a glue operand, we conservatively assume it isn't safe to
2288 // perform a tail call.
2289 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
2291 TCChain = Copy->getOperand(0);
2292 } else if (Copy->getOpcode() != ISD::FP_EXTEND)
2295 bool HasRet = false;
2296 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
2298 if (UI->getOpcode() != X86ISD::RET_FLAG)
2300 // If we are returning more than one value, we can definitely
2301 // not make a tail call see PR19530
2302 if (UI->getNumOperands() > 4)
2304 if (UI->getNumOperands() == 4 &&
2305 UI->getOperand(UI->getNumOperands()-1).getValueType() != MVT::Glue)
2318 X86TargetLowering::getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT,
2319 ISD::NodeType ExtendKind) const {
2321 // TODO: Is this also valid on 32-bit?
2322 if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND)
2323 ReturnMVT = MVT::i8;
2325 ReturnMVT = MVT::i32;
2327 EVT MinVT = getRegisterType(Context, ReturnMVT);
2328 return VT.bitsLT(MinVT) ? MinVT : VT;
2331 /// Lower the result values of a call into the
2332 /// appropriate copies out of appropriate physical registers.
2335 X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
2336 CallingConv::ID CallConv, bool isVarArg,
2337 const SmallVectorImpl<ISD::InputArg> &Ins,
2338 SDLoc dl, SelectionDAG &DAG,
2339 SmallVectorImpl<SDValue> &InVals) const {
2341 // Assign locations to each value returned by this call.
2342 SmallVector<CCValAssign, 16> RVLocs;
2343 bool Is64Bit = Subtarget->is64Bit();
2344 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
2346 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
2348 // Copy all of the result registers out of their specified physreg.
2349 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
2350 CCValAssign &VA = RVLocs[i];
2351 EVT CopyVT = VA.getLocVT();
2353 // If this is x86-64, and we disabled SSE, we can't return FP values
2354 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
2355 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) {
2356 report_fatal_error("SSE register return with SSE disabled");
2359 // If we prefer to use the value in xmm registers, copy it out as f80 and
2360 // use a truncate to move it from fp stack reg to xmm reg.
2361 bool RoundAfterCopy = false;
2362 if ((VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1) &&
2363 isScalarFPTypeInSSEReg(VA.getValVT())) {
2365 RoundAfterCopy = (CopyVT != VA.getLocVT());
2368 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
2369 CopyVT, InFlag).getValue(1);
2370 SDValue Val = Chain.getValue(0);
2373 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
2374 // This truncation won't change the value.
2375 DAG.getIntPtrConstant(1, dl));
2377 if (VA.isExtInLoc() && VA.getValVT().getScalarType() == MVT::i1)
2378 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
2380 InFlag = Chain.getValue(2);
2381 InVals.push_back(Val);
2387 //===----------------------------------------------------------------------===//
2388 // C & StdCall & Fast Calling Convention implementation
2389 //===----------------------------------------------------------------------===//
2390 // StdCall calling convention seems to be standard for many Windows' API
2391 // routines and around. It differs from C calling convention just a little:
2392 // callee should clean up the stack, not caller. Symbols should be also
2393 // decorated in some fancy way :) It doesn't support any vector arguments.
2394 // For info on fast calling convention see Fast Calling Convention (tail call)
2395 // implementation LowerX86_32FastCCCallTo.
2397 /// CallIsStructReturn - Determines whether a call uses struct return
2399 enum StructReturnType {
2404 static StructReturnType
2405 callIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
2407 return NotStructReturn;
2409 const ISD::ArgFlagsTy &Flags = Outs[0].Flags;
2410 if (!Flags.isSRet())
2411 return NotStructReturn;
2412 if (Flags.isInReg())
2413 return RegStructReturn;
2414 return StackStructReturn;
2417 /// Determines whether a function uses struct return semantics.
2418 static StructReturnType
2419 argsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
2421 return NotStructReturn;
2423 const ISD::ArgFlagsTy &Flags = Ins[0].Flags;
2424 if (!Flags.isSRet())
2425 return NotStructReturn;
2426 if (Flags.isInReg())
2427 return RegStructReturn;
2428 return StackStructReturn;
2431 /// Make a copy of an aggregate at address specified by "Src" to address
2432 /// "Dst" with size and alignment information specified by the specific
2433 /// parameter attribute. The copy will be passed as a byval function parameter.
2435 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
2436 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
2438 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), dl, MVT::i32);
2440 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
2441 /*isVolatile*/false, /*AlwaysInline=*/true,
2442 /*isTailCall*/false,
2443 MachinePointerInfo(), MachinePointerInfo());
2446 /// Return true if the calling convention is one that we can guarantee TCO for.
2447 static bool canGuaranteeTCO(CallingConv::ID CC) {
2448 return (CC == CallingConv::Fast || CC == CallingConv::GHC ||
2449 CC == CallingConv::HiPE || CC == CallingConv::HHVM);
2452 /// Return true if we might ever do TCO for calls with this calling convention.
2453 static bool mayTailCallThisCC(CallingConv::ID CC) {
2455 // C calling conventions:
2456 case CallingConv::C:
2457 case CallingConv::X86_64_Win64:
2458 case CallingConv::X86_64_SysV:
2459 // Callee pop conventions:
2460 case CallingConv::X86_ThisCall:
2461 case CallingConv::X86_StdCall:
2462 case CallingConv::X86_VectorCall:
2463 case CallingConv::X86_FastCall:
2466 return canGuaranteeTCO(CC);
2470 /// Return true if the function is being made into a tailcall target by
2471 /// changing its ABI.
2472 static bool shouldGuaranteeTCO(CallingConv::ID CC, bool GuaranteedTailCallOpt) {
2473 return GuaranteedTailCallOpt && canGuaranteeTCO(CC);
2476 bool X86TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
2478 CI->getParent()->getParent()->getFnAttribute("disable-tail-calls");
2479 if (!CI->isTailCall() || Attr.getValueAsString() == "true")
2483 CallingConv::ID CalleeCC = CS.getCallingConv();
2484 if (!mayTailCallThisCC(CalleeCC))
2491 X86TargetLowering::LowerMemArgument(SDValue Chain,
2492 CallingConv::ID CallConv,
2493 const SmallVectorImpl<ISD::InputArg> &Ins,
2494 SDLoc dl, SelectionDAG &DAG,
2495 const CCValAssign &VA,
2496 MachineFrameInfo *MFI,
2498 // Create the nodes corresponding to a load from this parameter slot.
2499 ISD::ArgFlagsTy Flags = Ins[i].Flags;
2500 bool AlwaysUseMutable = shouldGuaranteeTCO(
2501 CallConv, DAG.getTarget().Options.GuaranteedTailCallOpt);
2502 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
2505 // If value is passed by pointer we have address passed instead of the value
2507 bool ExtendedInMem = VA.isExtInLoc() &&
2508 VA.getValVT().getScalarType() == MVT::i1;
2510 if (VA.getLocInfo() == CCValAssign::Indirect || ExtendedInMem)
2511 ValVT = VA.getLocVT();
2513 ValVT = VA.getValVT();
2515 // FIXME: For now, all byval parameter objects are marked mutable. This can be
2516 // changed with more analysis.
2517 // In case of tail call optimization mark all arguments mutable. Since they
2518 // could be overwritten by lowering of arguments in case of a tail call.
2519 if (Flags.isByVal()) {
2520 unsigned Bytes = Flags.getByValSize();
2521 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects.
2522 int FI = MFI->CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable);
2523 return DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
2525 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
2526 VA.getLocMemOffset(), isImmutable);
2527 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
2528 SDValue Val = DAG.getLoad(
2529 ValVT, dl, Chain, FIN,
2530 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI), false,
2532 return ExtendedInMem ?
2533 DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val) : Val;
2537 // FIXME: Get this from tablegen.
2538 static ArrayRef<MCPhysReg> get64BitArgumentGPRs(CallingConv::ID CallConv,
2539 const X86Subtarget *Subtarget) {
2540 assert(Subtarget->is64Bit());
2542 if (Subtarget->isCallingConvWin64(CallConv)) {
2543 static const MCPhysReg GPR64ArgRegsWin64[] = {
2544 X86::RCX, X86::RDX, X86::R8, X86::R9
2546 return makeArrayRef(std::begin(GPR64ArgRegsWin64), std::end(GPR64ArgRegsWin64));
2549 static const MCPhysReg GPR64ArgRegs64Bit[] = {
2550 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
2552 return makeArrayRef(std::begin(GPR64ArgRegs64Bit), std::end(GPR64ArgRegs64Bit));
2555 // FIXME: Get this from tablegen.
2556 static ArrayRef<MCPhysReg> get64BitArgumentXMMs(MachineFunction &MF,
2557 CallingConv::ID CallConv,
2558 const X86Subtarget *Subtarget) {
2559 assert(Subtarget->is64Bit());
2560 if (Subtarget->isCallingConvWin64(CallConv)) {
2561 // The XMM registers which might contain var arg parameters are shadowed
2562 // in their paired GPR. So we only need to save the GPR to their home
2564 // TODO: __vectorcall will change this.
2568 const Function *Fn = MF.getFunction();
2569 bool NoImplicitFloatOps = Fn->hasFnAttribute(Attribute::NoImplicitFloat);
2570 bool isSoftFloat = Subtarget->useSoftFloat();
2571 assert(!(isSoftFloat && NoImplicitFloatOps) &&
2572 "SSE register cannot be used when SSE is disabled!");
2573 if (isSoftFloat || NoImplicitFloatOps || !Subtarget->hasSSE1())
2574 // Kernel mode asks for SSE to be disabled, so there are no XMM argument
2578 static const MCPhysReg XMMArgRegs64Bit[] = {
2579 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2580 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2582 return makeArrayRef(std::begin(XMMArgRegs64Bit), std::end(XMMArgRegs64Bit));
2585 SDValue X86TargetLowering::LowerFormalArguments(
2586 SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
2587 const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc dl, SelectionDAG &DAG,
2588 SmallVectorImpl<SDValue> &InVals) const {
2589 MachineFunction &MF = DAG.getMachineFunction();
2590 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2591 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
2593 const Function* Fn = MF.getFunction();
2594 if (Fn->hasExternalLinkage() &&
2595 Subtarget->isTargetCygMing() &&
2596 Fn->getName() == "main")
2597 FuncInfo->setForceFramePointer(true);
2599 MachineFrameInfo *MFI = MF.getFrameInfo();
2600 bool Is64Bit = Subtarget->is64Bit();
2601 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2603 assert(!(isVarArg && canGuaranteeTCO(CallConv)) &&
2604 "Var args not supported with calling convention fastcc, ghc or hipe");
2606 // Assign locations to all of the incoming arguments.
2607 SmallVector<CCValAssign, 16> ArgLocs;
2608 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
2610 // Allocate shadow area for Win64
2612 CCInfo.AllocateStack(32, 8);
2614 CCInfo.AnalyzeFormalArguments(Ins, CC_X86);
2616 unsigned LastVal = ~0U;
2618 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2619 CCValAssign &VA = ArgLocs[i];
2620 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
2622 assert(VA.getValNo() != LastVal &&
2623 "Don't support value assigned to multiple locs yet");
2625 LastVal = VA.getValNo();
2627 if (VA.isRegLoc()) {
2628 EVT RegVT = VA.getLocVT();
2629 const TargetRegisterClass *RC;
2630 if (RegVT == MVT::i32)
2631 RC = &X86::GR32RegClass;
2632 else if (Is64Bit && RegVT == MVT::i64)
2633 RC = &X86::GR64RegClass;
2634 else if (RegVT == MVT::f32)
2635 RC = &X86::FR32RegClass;
2636 else if (RegVT == MVT::f64)
2637 RC = &X86::FR64RegClass;
2638 else if (RegVT.is512BitVector())
2639 RC = &X86::VR512RegClass;
2640 else if (RegVT.is256BitVector())
2641 RC = &X86::VR256RegClass;
2642 else if (RegVT.is128BitVector())
2643 RC = &X86::VR128RegClass;
2644 else if (RegVT == MVT::x86mmx)
2645 RC = &X86::VR64RegClass;
2646 else if (RegVT == MVT::i1)
2647 RC = &X86::VK1RegClass;
2648 else if (RegVT == MVT::v8i1)
2649 RC = &X86::VK8RegClass;
2650 else if (RegVT == MVT::v16i1)
2651 RC = &X86::VK16RegClass;
2652 else if (RegVT == MVT::v32i1)
2653 RC = &X86::VK32RegClass;
2654 else if (RegVT == MVT::v64i1)
2655 RC = &X86::VK64RegClass;
2657 llvm_unreachable("Unknown argument type!");
2659 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2660 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
2662 // If this is an 8 or 16-bit value, it is really passed promoted to 32
2663 // bits. Insert an assert[sz]ext to capture this, then truncate to the
2665 if (VA.getLocInfo() == CCValAssign::SExt)
2666 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
2667 DAG.getValueType(VA.getValVT()));
2668 else if (VA.getLocInfo() == CCValAssign::ZExt)
2669 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
2670 DAG.getValueType(VA.getValVT()));
2671 else if (VA.getLocInfo() == CCValAssign::BCvt)
2672 ArgValue = DAG.getBitcast(VA.getValVT(), ArgValue);
2674 if (VA.isExtInLoc()) {
2675 // Handle MMX values passed in XMM regs.
2676 if (RegVT.isVector() && VA.getValVT().getScalarType() != MVT::i1)
2677 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(), ArgValue);
2679 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
2682 assert(VA.isMemLoc());
2683 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
2686 // If value is passed via pointer - do a load.
2687 if (VA.getLocInfo() == CCValAssign::Indirect)
2688 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue,
2689 MachinePointerInfo(), false, false, false, 0);
2691 InVals.push_back(ArgValue);
2694 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2695 // All x86 ABIs require that for returning structs by value we copy the
2696 // sret argument into %rax/%eax (depending on ABI) for the return. Save
2697 // the argument into a virtual register so that we can access it from the
2699 if (Ins[i].Flags.isSRet()) {
2700 unsigned Reg = FuncInfo->getSRetReturnReg();
2702 MVT PtrTy = getPointerTy(DAG.getDataLayout());
2703 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(PtrTy));
2704 FuncInfo->setSRetReturnReg(Reg);
2706 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[i]);
2707 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
2712 unsigned StackSize = CCInfo.getNextStackOffset();
2713 // Align stack specially for tail calls.
2714 if (shouldGuaranteeTCO(CallConv,
2715 MF.getTarget().Options.GuaranteedTailCallOpt))
2716 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
2718 // If the function takes variable number of arguments, make a frame index for
2719 // the start of the first vararg value... for expansion of llvm.va_start. We
2720 // can skip this if there are no va_start calls.
2721 if (MFI->hasVAStart() &&
2722 (Is64Bit || (CallConv != CallingConv::X86_FastCall &&
2723 CallConv != CallingConv::X86_ThisCall))) {
2724 FuncInfo->setVarArgsFrameIndex(
2725 MFI->CreateFixedObject(1, StackSize, true));
2728 // Figure out if XMM registers are in use.
2729 assert(!(Subtarget->useSoftFloat() &&
2730 Fn->hasFnAttribute(Attribute::NoImplicitFloat)) &&
2731 "SSE register cannot be used when SSE is disabled!");
2733 // 64-bit calling conventions support varargs and register parameters, so we
2734 // have to do extra work to spill them in the prologue.
2735 if (Is64Bit && isVarArg && MFI->hasVAStart()) {
2736 // Find the first unallocated argument registers.
2737 ArrayRef<MCPhysReg> ArgGPRs = get64BitArgumentGPRs(CallConv, Subtarget);
2738 ArrayRef<MCPhysReg> ArgXMMs = get64BitArgumentXMMs(MF, CallConv, Subtarget);
2739 unsigned NumIntRegs = CCInfo.getFirstUnallocated(ArgGPRs);
2740 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(ArgXMMs);
2741 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) &&
2742 "SSE register cannot be used when SSE is disabled!");
2744 // Gather all the live in physical registers.
2745 SmallVector<SDValue, 6> LiveGPRs;
2746 SmallVector<SDValue, 8> LiveXMMRegs;
2748 for (MCPhysReg Reg : ArgGPRs.slice(NumIntRegs)) {
2749 unsigned GPR = MF.addLiveIn(Reg, &X86::GR64RegClass);
2751 DAG.getCopyFromReg(Chain, dl, GPR, MVT::i64));
2753 if (!ArgXMMs.empty()) {
2754 unsigned AL = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
2755 ALVal = DAG.getCopyFromReg(Chain, dl, AL, MVT::i8);
2756 for (MCPhysReg Reg : ArgXMMs.slice(NumXMMRegs)) {
2757 unsigned XMMReg = MF.addLiveIn(Reg, &X86::VR128RegClass);
2758 LiveXMMRegs.push_back(
2759 DAG.getCopyFromReg(Chain, dl, XMMReg, MVT::v4f32));
2764 // Get to the caller-allocated home save location. Add 8 to account
2765 // for the return address.
2766 int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
2767 FuncInfo->setRegSaveFrameIndex(
2768 MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false));
2769 // Fixup to set vararg frame on shadow area (4 x i64).
2771 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex());
2773 // For X86-64, if there are vararg parameters that are passed via
2774 // registers, then we must store them to their spots on the stack so
2775 // they may be loaded by deferencing the result of va_next.
2776 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8);
2777 FuncInfo->setVarArgsFPOffset(ArgGPRs.size() * 8 + NumXMMRegs * 16);
2778 FuncInfo->setRegSaveFrameIndex(MFI->CreateStackObject(
2779 ArgGPRs.size() * 8 + ArgXMMs.size() * 16, 16, false));
2782 // Store the integer parameter registers.
2783 SmallVector<SDValue, 8> MemOps;
2784 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
2785 getPointerTy(DAG.getDataLayout()));
2786 unsigned Offset = FuncInfo->getVarArgsGPOffset();
2787 for (SDValue Val : LiveGPRs) {
2788 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(DAG.getDataLayout()),
2789 RSFIN, DAG.getIntPtrConstant(Offset, dl));
2791 DAG.getStore(Val.getValue(1), dl, Val, FIN,
2792 MachinePointerInfo::getFixedStack(
2793 DAG.getMachineFunction(),
2794 FuncInfo->getRegSaveFrameIndex(), Offset),
2796 MemOps.push_back(Store);
2800 if (!ArgXMMs.empty() && NumXMMRegs != ArgXMMs.size()) {
2801 // Now store the XMM (fp + vector) parameter registers.
2802 SmallVector<SDValue, 12> SaveXMMOps;
2803 SaveXMMOps.push_back(Chain);
2804 SaveXMMOps.push_back(ALVal);
2805 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2806 FuncInfo->getRegSaveFrameIndex(), dl));
2807 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2808 FuncInfo->getVarArgsFPOffset(), dl));
2809 SaveXMMOps.insert(SaveXMMOps.end(), LiveXMMRegs.begin(),
2811 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
2812 MVT::Other, SaveXMMOps));
2815 if (!MemOps.empty())
2816 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
2819 if (isVarArg && MFI->hasMustTailInVarArgFunc()) {
2820 // Find the largest legal vector type.
2821 MVT VecVT = MVT::Other;
2822 // FIXME: Only some x86_32 calling conventions support AVX512.
2823 if (Subtarget->hasAVX512() &&
2824 (Is64Bit || (CallConv == CallingConv::X86_VectorCall ||
2825 CallConv == CallingConv::Intel_OCL_BI)))
2826 VecVT = MVT::v16f32;
2827 else if (Subtarget->hasAVX())
2829 else if (Subtarget->hasSSE2())
2832 // We forward some GPRs and some vector types.
2833 SmallVector<MVT, 2> RegParmTypes;
2834 MVT IntVT = Is64Bit ? MVT::i64 : MVT::i32;
2835 RegParmTypes.push_back(IntVT);
2836 if (VecVT != MVT::Other)
2837 RegParmTypes.push_back(VecVT);
2839 // Compute the set of forwarded registers. The rest are scratch.
2840 SmallVectorImpl<ForwardedRegister> &Forwards =
2841 FuncInfo->getForwardedMustTailRegParms();
2842 CCInfo.analyzeMustTailForwardedRegisters(Forwards, RegParmTypes, CC_X86);
2844 // Conservatively forward AL on x86_64, since it might be used for varargs.
2845 if (Is64Bit && !CCInfo.isAllocated(X86::AL)) {
2846 unsigned ALVReg = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
2847 Forwards.push_back(ForwardedRegister(ALVReg, X86::AL, MVT::i8));
2850 // Copy all forwards from physical to virtual registers.
2851 for (ForwardedRegister &F : Forwards) {
2852 // FIXME: Can we use a less constrained schedule?
2853 SDValue RegVal = DAG.getCopyFromReg(Chain, dl, F.VReg, F.VT);
2854 F.VReg = MF.getRegInfo().createVirtualRegister(getRegClassFor(F.VT));
2855 Chain = DAG.getCopyToReg(Chain, dl, F.VReg, RegVal);
2859 // Some CCs need callee pop.
2860 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2861 MF.getTarget().Options.GuaranteedTailCallOpt)) {
2862 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything.
2864 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing.
2865 // If this is an sret function, the return should pop the hidden pointer.
2866 if (!Is64Bit && !canGuaranteeTCO(CallConv) &&
2867 !Subtarget->getTargetTriple().isOSMSVCRT() &&
2868 argsAreStructReturn(Ins) == StackStructReturn)
2869 FuncInfo->setBytesToPopOnReturn(4);
2873 // RegSaveFrameIndex is X86-64 only.
2874 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
2875 if (CallConv == CallingConv::X86_FastCall ||
2876 CallConv == CallingConv::X86_ThisCall)
2877 // fastcc functions can't have varargs.
2878 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA);
2881 FuncInfo->setArgumentStackSize(StackSize);
2883 if (WinEHFuncInfo *EHInfo = MF.getWinEHFuncInfo()) {
2884 EHPersonality Personality = classifyEHPersonality(Fn->getPersonalityFn());
2885 if (Personality == EHPersonality::CoreCLR) {
2887 // TODO: Add a mechanism to frame lowering that will allow us to indicate
2888 // that we'd prefer this slot be allocated towards the bottom of the frame
2889 // (i.e. near the stack pointer after allocating the frame). Every
2890 // funclet needs a copy of this slot in its (mostly empty) frame, and the
2891 // offset from the bottom of this and each funclet's frame must be the
2892 // same, so the size of funclets' (mostly empty) frames is dictated by
2893 // how far this slot is from the bottom (since they allocate just enough
2894 // space to accomodate holding this slot at the correct offset).
2895 int PSPSymFI = MFI->CreateStackObject(8, 8, /*isSS=*/false);
2896 EHInfo->PSPSymFrameIdx = PSPSymFI;
2904 X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
2905 SDValue StackPtr, SDValue Arg,
2906 SDLoc dl, SelectionDAG &DAG,
2907 const CCValAssign &VA,
2908 ISD::ArgFlagsTy Flags) const {
2909 unsigned LocMemOffset = VA.getLocMemOffset();
2910 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset, dl);
2911 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(DAG.getDataLayout()),
2913 if (Flags.isByVal())
2914 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
2916 return DAG.getStore(
2917 Chain, dl, Arg, PtrOff,
2918 MachinePointerInfo::getStack(DAG.getMachineFunction(), LocMemOffset),
2922 /// Emit a load of return address if tail call
2923 /// optimization is performed and it is required.
2925 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
2926 SDValue &OutRetAddr, SDValue Chain,
2927 bool IsTailCall, bool Is64Bit,
2928 int FPDiff, SDLoc dl) const {
2929 // Adjust the Return address stack slot.
2930 EVT VT = getPointerTy(DAG.getDataLayout());
2931 OutRetAddr = getReturnAddressFrameIndex(DAG);
2933 // Load the "old" Return address.
2934 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(),
2935 false, false, false, 0);
2936 return SDValue(OutRetAddr.getNode(), 1);
2939 /// Emit a store of the return address if tail call
2940 /// optimization is performed and it is required (FPDiff!=0).
2941 static SDValue EmitTailCallStoreRetAddr(SelectionDAG &DAG, MachineFunction &MF,
2942 SDValue Chain, SDValue RetAddrFrIdx,
2943 EVT PtrVT, unsigned SlotSize,
2944 int FPDiff, SDLoc dl) {
2945 // Store the return address to the appropriate stack slot.
2946 if (!FPDiff) return Chain;
2947 // Calculate the new stack slot for the return address.
2948 int NewReturnAddrFI =
2949 MF.getFrameInfo()->CreateFixedObject(SlotSize, (int64_t)FPDiff - SlotSize,
2951 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, PtrVT);
2952 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
2953 MachinePointerInfo::getFixedStack(
2954 DAG.getMachineFunction(), NewReturnAddrFI),
2959 /// Returns a vector_shuffle mask for an movs{s|d}, movd
2960 /// operation of specified width.
2961 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
2963 unsigned NumElems = VT.getVectorNumElements();
2964 SmallVector<int, 8> Mask;
2965 Mask.push_back(NumElems);
2966 for (unsigned i = 1; i != NumElems; ++i)
2968 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
2972 X86TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
2973 SmallVectorImpl<SDValue> &InVals) const {
2974 SelectionDAG &DAG = CLI.DAG;
2976 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
2977 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
2978 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
2979 SDValue Chain = CLI.Chain;
2980 SDValue Callee = CLI.Callee;
2981 CallingConv::ID CallConv = CLI.CallConv;
2982 bool &isTailCall = CLI.IsTailCall;
2983 bool isVarArg = CLI.IsVarArg;
2985 MachineFunction &MF = DAG.getMachineFunction();
2986 bool Is64Bit = Subtarget->is64Bit();
2987 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2988 StructReturnType SR = callIsStructReturn(Outs);
2989 bool IsSibcall = false;
2990 X86MachineFunctionInfo *X86Info = MF.getInfo<X86MachineFunctionInfo>();
2991 auto Attr = MF.getFunction()->getFnAttribute("disable-tail-calls");
2993 if (Attr.getValueAsString() == "true")
2996 if (Subtarget->isPICStyleGOT() &&
2997 !MF.getTarget().Options.GuaranteedTailCallOpt) {
2998 // If we are using a GOT, disable tail calls to external symbols with
2999 // default visibility. Tail calling such a symbol requires using a GOT
3000 // relocation, which forces early binding of the symbol. This breaks code
3001 // that require lazy function symbol resolution. Using musttail or
3002 // GuaranteedTailCallOpt will override this.
3003 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
3004 if (!G || (!G->getGlobal()->hasLocalLinkage() &&
3005 G->getGlobal()->hasDefaultVisibility()))
3009 bool IsMustTail = CLI.CS && CLI.CS->isMustTailCall();
3011 // Force this to be a tail call. The verifier rules are enough to ensure
3012 // that we can lower this successfully without moving the return address
3015 } else if (isTailCall) {
3016 // Check if it's really possible to do a tail call.
3017 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
3018 isVarArg, SR != NotStructReturn,
3019 MF.getFunction()->hasStructRetAttr(), CLI.RetTy,
3020 Outs, OutVals, Ins, DAG);
3022 // Sibcalls are automatically detected tailcalls which do not require
3024 if (!MF.getTarget().Options.GuaranteedTailCallOpt && isTailCall)
3031 assert(!(isVarArg && canGuaranteeTCO(CallConv)) &&
3032 "Var args not supported with calling convention fastcc, ghc or hipe");
3034 // Analyze operands of the call, assigning locations to each operand.
3035 SmallVector<CCValAssign, 16> ArgLocs;
3036 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
3038 // Allocate shadow area for Win64
3040 CCInfo.AllocateStack(32, 8);
3042 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3044 // Get a count of how many bytes are to be pushed on the stack.
3045 unsigned NumBytes = CCInfo.getAlignedCallFrameSize();
3047 // This is a sibcall. The memory operands are available in caller's
3048 // own caller's stack.
3050 else if (MF.getTarget().Options.GuaranteedTailCallOpt &&
3051 canGuaranteeTCO(CallConv))
3052 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
3055 if (isTailCall && !IsSibcall && !IsMustTail) {
3056 // Lower arguments at fp - stackoffset + fpdiff.
3057 unsigned NumBytesCallerPushed = X86Info->getBytesToPopOnReturn();
3059 FPDiff = NumBytesCallerPushed - NumBytes;
3061 // Set the delta of movement of the returnaddr stackslot.
3062 // But only set if delta is greater than previous delta.
3063 if (FPDiff < X86Info->getTCReturnAddrDelta())
3064 X86Info->setTCReturnAddrDelta(FPDiff);
3067 unsigned NumBytesToPush = NumBytes;
3068 unsigned NumBytesToPop = NumBytes;
3070 // If we have an inalloca argument, all stack space has already been allocated
3071 // for us and be right at the top of the stack. We don't support multiple
3072 // arguments passed in memory when using inalloca.
3073 if (!Outs.empty() && Outs.back().Flags.isInAlloca()) {
3075 if (!ArgLocs.back().isMemLoc())
3076 report_fatal_error("cannot use inalloca attribute on a register "
3078 if (ArgLocs.back().getLocMemOffset() != 0)
3079 report_fatal_error("any parameter with the inalloca attribute must be "
3080 "the only memory argument");
3084 Chain = DAG.getCALLSEQ_START(
3085 Chain, DAG.getIntPtrConstant(NumBytesToPush, dl, true), dl);
3087 SDValue RetAddrFrIdx;
3088 // Load return address for tail calls.
3089 if (isTailCall && FPDiff)
3090 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall,
3091 Is64Bit, FPDiff, dl);
3093 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
3094 SmallVector<SDValue, 8> MemOpChains;
3097 // Walk the register/memloc assignments, inserting copies/loads. In the case
3098 // of tail call optimization arguments are handle later.
3099 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
3100 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3101 // Skip inalloca arguments, they have already been written.
3102 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3103 if (Flags.isInAlloca())
3106 CCValAssign &VA = ArgLocs[i];
3107 EVT RegVT = VA.getLocVT();
3108 SDValue Arg = OutVals[i];
3109 bool isByVal = Flags.isByVal();
3111 // Promote the value if needed.
3112 switch (VA.getLocInfo()) {
3113 default: llvm_unreachable("Unknown loc info!");
3114 case CCValAssign::Full: break;
3115 case CCValAssign::SExt:
3116 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
3118 case CCValAssign::ZExt:
3119 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
3121 case CCValAssign::AExt:
3122 if (Arg.getValueType().isVector() &&
3123 Arg.getValueType().getVectorElementType() == MVT::i1)
3124 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
3125 else if (RegVT.is128BitVector()) {
3126 // Special case: passing MMX values in XMM registers.
3127 Arg = DAG.getBitcast(MVT::i64, Arg);
3128 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
3129 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
3131 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
3133 case CCValAssign::BCvt:
3134 Arg = DAG.getBitcast(RegVT, Arg);
3136 case CCValAssign::Indirect: {
3137 // Store the argument.
3138 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
3139 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
3140 Chain = DAG.getStore(
3141 Chain, dl, Arg, SpillSlot,
3142 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI),
3149 if (VA.isRegLoc()) {
3150 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
3151 if (isVarArg && IsWin64) {
3152 // Win64 ABI requires argument XMM reg to be copied to the corresponding
3153 // shadow reg if callee is a varargs function.
3154 unsigned ShadowReg = 0;
3155 switch (VA.getLocReg()) {
3156 case X86::XMM0: ShadowReg = X86::RCX; break;
3157 case X86::XMM1: ShadowReg = X86::RDX; break;
3158 case X86::XMM2: ShadowReg = X86::R8; break;
3159 case X86::XMM3: ShadowReg = X86::R9; break;
3162 RegsToPass.push_back(std::make_pair(ShadowReg, Arg));
3164 } else if (!IsSibcall && (!isTailCall || isByVal)) {
3165 assert(VA.isMemLoc());
3166 if (!StackPtr.getNode())
3167 StackPtr = DAG.getCopyFromReg(Chain, dl, RegInfo->getStackRegister(),
3168 getPointerTy(DAG.getDataLayout()));
3169 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
3170 dl, DAG, VA, Flags));
3174 if (!MemOpChains.empty())
3175 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
3177 if (Subtarget->isPICStyleGOT()) {
3178 // ELF / PIC requires GOT in the EBX register before function calls via PLT
3181 RegsToPass.push_back(std::make_pair(
3182 unsigned(X86::EBX), DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(),
3183 getPointerTy(DAG.getDataLayout()))));
3185 // If we are tail calling and generating PIC/GOT style code load the
3186 // address of the callee into ECX. The value in ecx is used as target of
3187 // the tail jump. This is done to circumvent the ebx/callee-saved problem
3188 // for tail calls on PIC/GOT architectures. Normally we would just put the
3189 // address of GOT into ebx and then call target@PLT. But for tail calls
3190 // ebx would be restored (since ebx is callee saved) before jumping to the
3193 // Note: The actual moving to ECX is done further down.
3194 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
3195 if (G && !G->getGlobal()->hasLocalLinkage() &&
3196 G->getGlobal()->hasDefaultVisibility())
3197 Callee = LowerGlobalAddress(Callee, DAG);
3198 else if (isa<ExternalSymbolSDNode>(Callee))
3199 Callee = LowerExternalSymbol(Callee, DAG);
3203 if (Is64Bit && isVarArg && !IsWin64 && !IsMustTail) {
3204 // From AMD64 ABI document:
3205 // For calls that may call functions that use varargs or stdargs
3206 // (prototype-less calls or calls to functions containing ellipsis (...) in
3207 // the declaration) %al is used as hidden argument to specify the number
3208 // of SSE registers used. The contents of %al do not need to match exactly
3209 // the number of registers, but must be an ubound on the number of SSE
3210 // registers used and is in the range 0 - 8 inclusive.
3212 // Count the number of XMM registers allocated.
3213 static const MCPhysReg XMMArgRegs[] = {
3214 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
3215 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
3217 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs);
3218 assert((Subtarget->hasSSE1() || !NumXMMRegs)
3219 && "SSE registers cannot be used when SSE is disabled");
3221 RegsToPass.push_back(std::make_pair(unsigned(X86::AL),
3222 DAG.getConstant(NumXMMRegs, dl,
3226 if (isVarArg && IsMustTail) {
3227 const auto &Forwards = X86Info->getForwardedMustTailRegParms();
3228 for (const auto &F : Forwards) {
3229 SDValue Val = DAG.getCopyFromReg(Chain, dl, F.VReg, F.VT);
3230 RegsToPass.push_back(std::make_pair(unsigned(F.PReg), Val));
3234 // For tail calls lower the arguments to the 'real' stack slots. Sibcalls
3235 // don't need this because the eligibility check rejects calls that require
3236 // shuffling arguments passed in memory.
3237 if (!IsSibcall && isTailCall) {
3238 // Force all the incoming stack arguments to be loaded from the stack
3239 // before any new outgoing arguments are stored to the stack, because the
3240 // outgoing stack slots may alias the incoming argument stack slots, and
3241 // the alias isn't otherwise explicit. This is slightly more conservative
3242 // than necessary, because it means that each store effectively depends
3243 // on every argument instead of just those arguments it would clobber.
3244 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
3246 SmallVector<SDValue, 8> MemOpChains2;
3249 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3250 CCValAssign &VA = ArgLocs[i];
3253 assert(VA.isMemLoc());
3254 SDValue Arg = OutVals[i];
3255 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3256 // Skip inalloca arguments. They don't require any work.
3257 if (Flags.isInAlloca())
3259 // Create frame index.
3260 int32_t Offset = VA.getLocMemOffset()+FPDiff;
3261 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
3262 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
3263 FIN = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
3265 if (Flags.isByVal()) {
3266 // Copy relative to framepointer.
3267 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset(), dl);
3268 if (!StackPtr.getNode())
3269 StackPtr = DAG.getCopyFromReg(Chain, dl, RegInfo->getStackRegister(),
3270 getPointerTy(DAG.getDataLayout()));
3271 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(DAG.getDataLayout()),
3274 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
3278 // Store relative to framepointer.
3279 MemOpChains2.push_back(DAG.getStore(
3280 ArgChain, dl, Arg, FIN,
3281 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI),
3286 if (!MemOpChains2.empty())
3287 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains2);
3289 // Store the return address to the appropriate stack slot.
3290 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx,
3291 getPointerTy(DAG.getDataLayout()),
3292 RegInfo->getSlotSize(), FPDiff, dl);
3295 // Build a sequence of copy-to-reg nodes chained together with token chain
3296 // and flag operands which copy the outgoing args into registers.
3298 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
3299 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
3300 RegsToPass[i].second, InFlag);
3301 InFlag = Chain.getValue(1);
3304 if (DAG.getTarget().getCodeModel() == CodeModel::Large) {
3305 assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
3306 // In the 64-bit large code model, we have to make all calls
3307 // through a register, since the call instruction's 32-bit
3308 // pc-relative offset may not be large enough to hold the whole
3310 } else if (Callee->getOpcode() == ISD::GlobalAddress) {
3311 // If the callee is a GlobalAddress node (quite common, every direct call
3312 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
3314 GlobalAddressSDNode* G = cast<GlobalAddressSDNode>(Callee);
3316 // We should use extra load for direct calls to dllimported functions in
3318 const GlobalValue *GV = G->getGlobal();
3319 if (!GV->hasDLLImportStorageClass()) {
3320 unsigned char OpFlags = 0;
3321 bool ExtraLoad = false;
3322 unsigned WrapperKind = ISD::DELETED_NODE;
3324 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
3325 // external symbols most go through the PLT in PIC mode. If the symbol
3326 // has hidden or protected visibility, or if it is static or local, then
3327 // we don't need to use the PLT - we can directly call it.
3328 if (Subtarget->isTargetELF() &&
3329 DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
3330 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
3331 OpFlags = X86II::MO_PLT;
3332 } else if (Subtarget->isPICStyleStubAny() &&
3333 !GV->isStrongDefinitionForLinker() &&
3334 (!Subtarget->getTargetTriple().isMacOSX() ||
3335 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
3336 // PC-relative references to external symbols should go through $stub,
3337 // unless we're building with the leopard linker or later, which
3338 // automatically synthesizes these stubs.
3339 OpFlags = X86II::MO_DARWIN_STUB;
3340 } else if (Subtarget->isPICStyleRIPRel() && isa<Function>(GV) &&
3341 cast<Function>(GV)->hasFnAttribute(Attribute::NonLazyBind)) {
3342 // If the function is marked as non-lazy, generate an indirect call
3343 // which loads from the GOT directly. This avoids runtime overhead
3344 // at the cost of eager binding (and one extra byte of encoding).
3345 OpFlags = X86II::MO_GOTPCREL;
3346 WrapperKind = X86ISD::WrapperRIP;
3350 Callee = DAG.getTargetGlobalAddress(
3351 GV, dl, getPointerTy(DAG.getDataLayout()), G->getOffset(), OpFlags);
3353 // Add a wrapper if needed.
3354 if (WrapperKind != ISD::DELETED_NODE)
3355 Callee = DAG.getNode(X86ISD::WrapperRIP, dl,
3356 getPointerTy(DAG.getDataLayout()), Callee);
3357 // Add extra indirection if needed.
3359 Callee = DAG.getLoad(
3360 getPointerTy(DAG.getDataLayout()), dl, DAG.getEntryNode(), Callee,
3361 MachinePointerInfo::getGOT(DAG.getMachineFunction()), false, false,
3364 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
3365 unsigned char OpFlags = 0;
3367 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to
3368 // external symbols should go through the PLT.
3369 if (Subtarget->isTargetELF() &&
3370 DAG.getTarget().getRelocationModel() == Reloc::PIC_) {
3371 OpFlags = X86II::MO_PLT;
3372 } else if (Subtarget->isPICStyleStubAny() &&
3373 (!Subtarget->getTargetTriple().isMacOSX() ||
3374 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
3375 // PC-relative references to external symbols should go through $stub,
3376 // unless we're building with the leopard linker or later, which
3377 // automatically synthesizes these stubs.
3378 OpFlags = X86II::MO_DARWIN_STUB;
3381 Callee = DAG.getTargetExternalSymbol(
3382 S->getSymbol(), getPointerTy(DAG.getDataLayout()), OpFlags);
3383 } else if (Subtarget->isTarget64BitILP32() &&
3384 Callee->getValueType(0) == MVT::i32) {
3385 // Zero-extend the 32-bit Callee address into a 64-bit according to x32 ABI
3386 Callee = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, Callee);
3389 // Returns a chain & a flag for retval copy to use.
3390 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
3391 SmallVector<SDValue, 8> Ops;
3393 if (!IsSibcall && isTailCall) {
3394 Chain = DAG.getCALLSEQ_END(Chain,
3395 DAG.getIntPtrConstant(NumBytesToPop, dl, true),
3396 DAG.getIntPtrConstant(0, dl, true), InFlag, dl);
3397 InFlag = Chain.getValue(1);
3400 Ops.push_back(Chain);
3401 Ops.push_back(Callee);
3404 Ops.push_back(DAG.getConstant(FPDiff, dl, MVT::i32));
3406 // Add argument registers to the end of the list so that they are known live
3408 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
3409 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
3410 RegsToPass[i].second.getValueType()));
3412 // Add a register mask operand representing the call-preserved registers.
3413 const uint32_t *Mask = RegInfo->getCallPreservedMask(MF, CallConv);
3414 assert(Mask && "Missing call preserved mask for calling convention");
3416 // If this is an invoke in a 32-bit function using a funclet-based
3417 // personality, assume the function clobbers all registers. If an exception
3418 // is thrown, the runtime will not restore CSRs.
3419 // FIXME: Model this more precisely so that we can register allocate across
3420 // the normal edge and spill and fill across the exceptional edge.
3421 if (!Is64Bit && CLI.CS && CLI.CS->isInvoke()) {
3422 const Function *CallerFn = MF.getFunction();
3423 EHPersonality Pers =
3424 CallerFn->hasPersonalityFn()
3425 ? classifyEHPersonality(CallerFn->getPersonalityFn())
3426 : EHPersonality::Unknown;
3427 if (isFuncletEHPersonality(Pers))
3428 Mask = RegInfo->getNoPreservedMask();
3431 Ops.push_back(DAG.getRegisterMask(Mask));
3433 if (InFlag.getNode())
3434 Ops.push_back(InFlag);
3438 //// If this is the first return lowered for this function, add the regs
3439 //// to the liveout set for the function.
3440 // This isn't right, although it's probably harmless on x86; liveouts
3441 // should be computed from returns not tail calls. Consider a void
3442 // function making a tail call to a function returning int.
3443 MF.getFrameInfo()->setHasTailCall();
3444 return DAG.getNode(X86ISD::TC_RETURN, dl, NodeTys, Ops);
3447 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, Ops);
3448 InFlag = Chain.getValue(1);
3450 // Create the CALLSEQ_END node.
3451 unsigned NumBytesForCalleeToPop;
3452 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
3453 DAG.getTarget().Options.GuaranteedTailCallOpt))
3454 NumBytesForCalleeToPop = NumBytes; // Callee pops everything
3455 else if (!Is64Bit && !canGuaranteeTCO(CallConv) &&
3456 !Subtarget->getTargetTriple().isOSMSVCRT() &&
3457 SR == StackStructReturn)
3458 // If this is a call to a struct-return function, the callee
3459 // pops the hidden struct pointer, so we have to push it back.
3460 // This is common for Darwin/X86, Linux & Mingw32 targets.
3461 // For MSVC Win32 targets, the caller pops the hidden struct pointer.
3462 NumBytesForCalleeToPop = 4;
3464 NumBytesForCalleeToPop = 0; // Callee pops nothing.
3466 // Returns a flag for retval copy to use.
3468 Chain = DAG.getCALLSEQ_END(Chain,
3469 DAG.getIntPtrConstant(NumBytesToPop, dl, true),
3470 DAG.getIntPtrConstant(NumBytesForCalleeToPop, dl,
3473 InFlag = Chain.getValue(1);
3476 // Handle result values, copying them out of physregs into vregs that we
3478 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
3479 Ins, dl, DAG, InVals);
3482 //===----------------------------------------------------------------------===//
3483 // Fast Calling Convention (tail call) implementation
3484 //===----------------------------------------------------------------------===//
3486 // Like std call, callee cleans arguments, convention except that ECX is
3487 // reserved for storing the tail called function address. Only 2 registers are
3488 // free for argument passing (inreg). Tail call optimization is performed
3490 // * tailcallopt is enabled
3491 // * caller/callee are fastcc
3492 // On X86_64 architecture with GOT-style position independent code only local
3493 // (within module) calls are supported at the moment.
3494 // To keep the stack aligned according to platform abi the function
3495 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
3496 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
3497 // If a tail called function callee has more arguments than the caller the
3498 // caller needs to make sure that there is room to move the RETADDR to. This is
3499 // achieved by reserving an area the size of the argument delta right after the
3500 // original RETADDR, but before the saved framepointer or the spilled registers
3501 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
3513 /// Make the stack size align e.g 16n + 12 aligned for a 16-byte align
3516 X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
3517 SelectionDAG& DAG) const {
3518 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
3519 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
3520 unsigned StackAlignment = TFI.getStackAlignment();
3521 uint64_t AlignMask = StackAlignment - 1;
3522 int64_t Offset = StackSize;
3523 unsigned SlotSize = RegInfo->getSlotSize();
3524 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
3525 // Number smaller than 12 so just add the difference.
3526 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
3528 // Mask out lower bits, add stackalignment once plus the 12 bytes.
3529 Offset = ((~AlignMask) & Offset) + StackAlignment +
3530 (StackAlignment-SlotSize);
3535 /// Return true if the given stack call argument is already available in the
3536 /// same position (relatively) of the caller's incoming argument stack.
3538 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
3539 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
3540 const X86InstrInfo *TII) {
3541 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
3543 if (Arg.getOpcode() == ISD::CopyFromReg) {
3544 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
3545 if (!TargetRegisterInfo::isVirtualRegister(VR))
3547 MachineInstr *Def = MRI->getVRegDef(VR);
3550 if (!Flags.isByVal()) {
3551 if (!TII->isLoadFromStackSlot(Def, FI))
3554 unsigned Opcode = Def->getOpcode();
3555 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r ||
3556 Opcode == X86::LEA64_32r) &&
3557 Def->getOperand(1).isFI()) {
3558 FI = Def->getOperand(1).getIndex();
3559 Bytes = Flags.getByValSize();
3563 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
3564 if (Flags.isByVal())
3565 // ByVal argument is passed in as a pointer but it's now being
3566 // dereferenced. e.g.
3567 // define @foo(%struct.X* %A) {
3568 // tail call @bar(%struct.X* byval %A)
3571 SDValue Ptr = Ld->getBasePtr();
3572 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
3575 FI = FINode->getIndex();
3576 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) {
3577 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg);
3578 FI = FINode->getIndex();
3579 Bytes = Flags.getByValSize();
3583 assert(FI != INT_MAX);
3584 if (!MFI->isFixedObjectIndex(FI))
3586 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
3589 /// Check whether the call is eligible for tail call optimization. Targets
3590 /// that want to do tail call optimization should implement this function.
3591 bool X86TargetLowering::IsEligibleForTailCallOptimization(
3592 SDValue Callee, CallingConv::ID CalleeCC, bool isVarArg,
3593 bool isCalleeStructRet, bool isCallerStructRet, Type *RetTy,
3594 const SmallVectorImpl<ISD::OutputArg> &Outs,
3595 const SmallVectorImpl<SDValue> &OutVals,
3596 const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG &DAG) const {
3597 if (!mayTailCallThisCC(CalleeCC))
3600 // If -tailcallopt is specified, make fastcc functions tail-callable.
3601 MachineFunction &MF = DAG.getMachineFunction();
3602 const Function *CallerF = MF.getFunction();
3604 // If the function return type is x86_fp80 and the callee return type is not,
3605 // then the FP_EXTEND of the call result is not a nop. It's not safe to
3606 // perform a tailcall optimization here.
3607 if (CallerF->getReturnType()->isX86_FP80Ty() && !RetTy->isX86_FP80Ty())
3610 CallingConv::ID CallerCC = CallerF->getCallingConv();
3611 bool CCMatch = CallerCC == CalleeCC;
3612 bool IsCalleeWin64 = Subtarget->isCallingConvWin64(CalleeCC);
3613 bool IsCallerWin64 = Subtarget->isCallingConvWin64(CallerCC);
3615 // Win64 functions have extra shadow space for argument homing. Don't do the
3616 // sibcall if the caller and callee have mismatched expectations for this
3618 if (IsCalleeWin64 != IsCallerWin64)
3621 if (DAG.getTarget().Options.GuaranteedTailCallOpt) {
3622 if (canGuaranteeTCO(CalleeCC) && CCMatch)
3627 // Look for obvious safe cases to perform tail call optimization that do not
3628 // require ABI changes. This is what gcc calls sibcall.
3630 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
3631 // emit a special epilogue.
3632 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
3633 if (RegInfo->needsStackRealignment(MF))
3636 // Also avoid sibcall optimization if either caller or callee uses struct
3637 // return semantics.
3638 if (isCalleeStructRet || isCallerStructRet)
3641 // Do not sibcall optimize vararg calls unless all arguments are passed via
3643 if (isVarArg && !Outs.empty()) {
3644 // Optimizing for varargs on Win64 is unlikely to be safe without
3645 // additional testing.
3646 if (IsCalleeWin64 || IsCallerWin64)
3649 SmallVector<CCValAssign, 16> ArgLocs;
3650 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
3653 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3654 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
3655 if (!ArgLocs[i].isRegLoc())
3659 // If the call result is in ST0 / ST1, it needs to be popped off the x87
3660 // stack. Therefore, if it's not used by the call it is not safe to optimize
3661 // this into a sibcall.
3662 bool Unused = false;
3663 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
3670 SmallVector<CCValAssign, 16> RVLocs;
3671 CCState CCInfo(CalleeCC, false, DAG.getMachineFunction(), RVLocs,
3673 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
3674 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
3675 CCValAssign &VA = RVLocs[i];
3676 if (VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1)
3681 // If the calling conventions do not match, then we'd better make sure the
3682 // results are returned in the same way as what the caller expects.
3684 SmallVector<CCValAssign, 16> RVLocs1;
3685 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(), RVLocs1,
3687 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86);
3689 SmallVector<CCValAssign, 16> RVLocs2;
3690 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(), RVLocs2,
3692 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86);
3694 if (RVLocs1.size() != RVLocs2.size())
3696 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
3697 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
3699 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
3701 if (RVLocs1[i].isRegLoc()) {
3702 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
3705 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
3711 unsigned StackArgsSize = 0;
3713 // If the callee takes no arguments then go on to check the results of the
3715 if (!Outs.empty()) {
3716 // Check if stack adjustment is needed. For now, do not do this if any
3717 // argument is passed on the stack.
3718 SmallVector<CCValAssign, 16> ArgLocs;
3719 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
3722 // Allocate shadow area for Win64
3724 CCInfo.AllocateStack(32, 8);
3726 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3727 StackArgsSize = CCInfo.getNextStackOffset();
3729 if (CCInfo.getNextStackOffset()) {
3730 // Check if the arguments are already laid out in the right way as
3731 // the caller's fixed stack objects.
3732 MachineFrameInfo *MFI = MF.getFrameInfo();
3733 const MachineRegisterInfo *MRI = &MF.getRegInfo();
3734 const X86InstrInfo *TII = Subtarget->getInstrInfo();
3735 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3736 CCValAssign &VA = ArgLocs[i];
3737 SDValue Arg = OutVals[i];
3738 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3739 if (VA.getLocInfo() == CCValAssign::Indirect)
3741 if (!VA.isRegLoc()) {
3742 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
3749 // If the tailcall address may be in a register, then make sure it's
3750 // possible to register allocate for it. In 32-bit, the call address can
3751 // only target EAX, EDX, or ECX since the tail call must be scheduled after
3752 // callee-saved registers are restored. These happen to be the same
3753 // registers used to pass 'inreg' arguments so watch out for those.
3754 if (!Subtarget->is64Bit() &&
3755 ((!isa<GlobalAddressSDNode>(Callee) &&
3756 !isa<ExternalSymbolSDNode>(Callee)) ||
3757 DAG.getTarget().getRelocationModel() == Reloc::PIC_)) {
3758 unsigned NumInRegs = 0;
3759 // In PIC we need an extra register to formulate the address computation
3761 unsigned MaxInRegs =
3762 (DAG.getTarget().getRelocationModel() == Reloc::PIC_) ? 2 : 3;
3764 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3765 CCValAssign &VA = ArgLocs[i];
3768 unsigned Reg = VA.getLocReg();
3771 case X86::EAX: case X86::EDX: case X86::ECX:
3772 if (++NumInRegs == MaxInRegs)
3780 bool CalleeWillPop =
3781 X86::isCalleePop(CalleeCC, Subtarget->is64Bit(), isVarArg,
3782 MF.getTarget().Options.GuaranteedTailCallOpt);
3784 if (unsigned BytesToPop =
3785 MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn()) {
3786 // If we have bytes to pop, the callee must pop them.
3787 bool CalleePopMatches = CalleeWillPop && BytesToPop == StackArgsSize;
3788 if (!CalleePopMatches)
3790 } else if (CalleeWillPop && StackArgsSize > 0) {
3791 // If we don't have bytes to pop, make sure the callee doesn't pop any.
3799 X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
3800 const TargetLibraryInfo *libInfo) const {
3801 return X86::createFastISel(funcInfo, libInfo);
3804 //===----------------------------------------------------------------------===//
3805 // Other Lowering Hooks
3806 //===----------------------------------------------------------------------===//
3808 static bool MayFoldLoad(SDValue Op) {
3809 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode());
3812 static bool MayFoldIntoStore(SDValue Op) {
3813 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin());
3816 static bool isTargetShuffle(unsigned Opcode) {
3818 default: return false;
3819 case X86ISD::BLENDI:
3820 case X86ISD::PSHUFB:
3821 case X86ISD::PSHUFD:
3822 case X86ISD::PSHUFHW:
3823 case X86ISD::PSHUFLW:
3825 case X86ISD::PALIGNR:
3826 case X86ISD::MOVLHPS:
3827 case X86ISD::MOVLHPD:
3828 case X86ISD::MOVHLPS:
3829 case X86ISD::MOVLPS:
3830 case X86ISD::MOVLPD:
3831 case X86ISD::MOVSHDUP:
3832 case X86ISD::MOVSLDUP:
3833 case X86ISD::MOVDDUP:
3836 case X86ISD::UNPCKL:
3837 case X86ISD::UNPCKH:
3838 case X86ISD::VPERMILPI:
3839 case X86ISD::VPERM2X128:
3840 case X86ISD::VPERMI:
3841 case X86ISD::VPERMV:
3842 case X86ISD::VPERMV3:
3847 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, MVT VT,
3848 SDValue V1, unsigned TargetMask,
3849 SelectionDAG &DAG) {
3851 default: llvm_unreachable("Unknown x86 shuffle node");
3852 case X86ISD::PSHUFD:
3853 case X86ISD::PSHUFHW:
3854 case X86ISD::PSHUFLW:
3855 case X86ISD::VPERMILPI:
3856 case X86ISD::VPERMI:
3857 return DAG.getNode(Opc, dl, VT, V1,
3858 DAG.getConstant(TargetMask, dl, MVT::i8));
3862 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, MVT VT,
3863 SDValue V1, SDValue V2, SelectionDAG &DAG) {
3865 default: llvm_unreachable("Unknown x86 shuffle node");
3866 case X86ISD::MOVLHPS:
3867 case X86ISD::MOVLHPD:
3868 case X86ISD::MOVHLPS:
3869 case X86ISD::MOVLPS:
3870 case X86ISD::MOVLPD:
3873 case X86ISD::UNPCKL:
3874 case X86ISD::UNPCKH:
3875 return DAG.getNode(Opc, dl, VT, V1, V2);
3879 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
3880 MachineFunction &MF = DAG.getMachineFunction();
3881 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
3882 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
3883 int ReturnAddrIndex = FuncInfo->getRAIndex();
3885 if (ReturnAddrIndex == 0) {
3886 // Set up a frame object for the return address.
3887 unsigned SlotSize = RegInfo->getSlotSize();
3888 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize,
3891 FuncInfo->setRAIndex(ReturnAddrIndex);
3894 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy(DAG.getDataLayout()));
3897 bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
3898 bool hasSymbolicDisplacement) {
3899 // Offset should fit into 32 bit immediate field.
3900 if (!isInt<32>(Offset))
3903 // If we don't have a symbolic displacement - we don't have any extra
3905 if (!hasSymbolicDisplacement)
3908 // FIXME: Some tweaks might be needed for medium code model.
3909 if (M != CodeModel::Small && M != CodeModel::Kernel)
3912 // For small code model we assume that latest object is 16MB before end of 31
3913 // bits boundary. We may also accept pretty large negative constants knowing
3914 // that all objects are in the positive half of address space.
3915 if (M == CodeModel::Small && Offset < 16*1024*1024)
3918 // For kernel code model we know that all object resist in the negative half
3919 // of 32bits address space. We may not accept negative offsets, since they may
3920 // be just off and we may accept pretty large positive ones.
3921 if (M == CodeModel::Kernel && Offset >= 0)
3927 /// Determines whether the callee is required to pop its own arguments.
3928 /// Callee pop is necessary to support tail calls.
3929 bool X86::isCalleePop(CallingConv::ID CallingConv,
3930 bool is64Bit, bool IsVarArg, bool GuaranteeTCO) {
3931 // If GuaranteeTCO is true, we force some calls to be callee pop so that we
3932 // can guarantee TCO.
3933 if (!IsVarArg && shouldGuaranteeTCO(CallingConv, GuaranteeTCO))
3936 switch (CallingConv) {
3939 case CallingConv::X86_StdCall:
3940 case CallingConv::X86_FastCall:
3941 case CallingConv::X86_ThisCall:
3942 case CallingConv::X86_VectorCall:
3947 /// \brief Return true if the condition is an unsigned comparison operation.
3948 static bool isX86CCUnsigned(unsigned X86CC) {
3950 default: llvm_unreachable("Invalid integer condition!");
3951 case X86::COND_E: return true;
3952 case X86::COND_G: return false;
3953 case X86::COND_GE: return false;
3954 case X86::COND_L: return false;
3955 case X86::COND_LE: return false;
3956 case X86::COND_NE: return true;
3957 case X86::COND_B: return true;
3958 case X86::COND_A: return true;
3959 case X86::COND_BE: return true;
3960 case X86::COND_AE: return true;
3964 static X86::CondCode TranslateIntegerX86CC(ISD::CondCode SetCCOpcode) {
3965 switch (SetCCOpcode) {
3966 default: llvm_unreachable("Invalid integer condition!");
3967 case ISD::SETEQ: return X86::COND_E;
3968 case ISD::SETGT: return X86::COND_G;
3969 case ISD::SETGE: return X86::COND_GE;
3970 case ISD::SETLT: return X86::COND_L;
3971 case ISD::SETLE: return X86::COND_LE;
3972 case ISD::SETNE: return X86::COND_NE;
3973 case ISD::SETULT: return X86::COND_B;
3974 case ISD::SETUGT: return X86::COND_A;
3975 case ISD::SETULE: return X86::COND_BE;
3976 case ISD::SETUGE: return X86::COND_AE;
3980 /// Do a one-to-one translation of a ISD::CondCode to the X86-specific
3981 /// condition code, returning the condition code and the LHS/RHS of the
3982 /// comparison to make.
3983 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, SDLoc DL, bool isFP,
3984 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
3986 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
3987 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
3988 // X > -1 -> X == 0, jump !sign.
3989 RHS = DAG.getConstant(0, DL, RHS.getValueType());
3990 return X86::COND_NS;
3992 if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
3993 // X < 0 -> X == 0, jump on sign.
3996 if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
3998 RHS = DAG.getConstant(0, DL, RHS.getValueType());
3999 return X86::COND_LE;
4003 return TranslateIntegerX86CC(SetCCOpcode);
4006 // First determine if it is required or is profitable to flip the operands.
4008 // If LHS is a foldable load, but RHS is not, flip the condition.
4009 if (ISD::isNON_EXTLoad(LHS.getNode()) &&
4010 !ISD::isNON_EXTLoad(RHS.getNode())) {
4011 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
4012 std::swap(LHS, RHS);
4015 switch (SetCCOpcode) {
4021 std::swap(LHS, RHS);
4025 // On a floating point condition, the flags are set as follows:
4027 // 0 | 0 | 0 | X > Y
4028 // 0 | 0 | 1 | X < Y
4029 // 1 | 0 | 0 | X == Y
4030 // 1 | 1 | 1 | unordered
4031 switch (SetCCOpcode) {
4032 default: llvm_unreachable("Condcode should be pre-legalized away");
4034 case ISD::SETEQ: return X86::COND_E;
4035 case ISD::SETOLT: // flipped
4037 case ISD::SETGT: return X86::COND_A;
4038 case ISD::SETOLE: // flipped
4040 case ISD::SETGE: return X86::COND_AE;
4041 case ISD::SETUGT: // flipped
4043 case ISD::SETLT: return X86::COND_B;
4044 case ISD::SETUGE: // flipped
4046 case ISD::SETLE: return X86::COND_BE;
4048 case ISD::SETNE: return X86::COND_NE;
4049 case ISD::SETUO: return X86::COND_P;
4050 case ISD::SETO: return X86::COND_NP;
4052 case ISD::SETUNE: return X86::COND_INVALID;
4056 /// Is there a floating point cmov for the specific X86 condition code?
4057 /// Current x86 isa includes the following FP cmov instructions:
4058 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
4059 static bool hasFPCMov(unsigned X86CC) {
4075 /// Returns true if the target can instruction select the
4076 /// specified FP immediate natively. If false, the legalizer will
4077 /// materialize the FP immediate as a load from a constant pool.
4078 bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
4079 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
4080 if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
4086 bool X86TargetLowering::shouldReduceLoadWidth(SDNode *Load,
4087 ISD::LoadExtType ExtTy,
4089 // "ELF Handling for Thread-Local Storage" specifies that R_X86_64_GOTTPOFF
4090 // relocation target a movq or addq instruction: don't let the load shrink.
4091 SDValue BasePtr = cast<LoadSDNode>(Load)->getBasePtr();
4092 if (BasePtr.getOpcode() == X86ISD::WrapperRIP)
4093 if (const auto *GA = dyn_cast<GlobalAddressSDNode>(BasePtr.getOperand(0)))
4094 return GA->getTargetFlags() != X86II::MO_GOTTPOFF;
4098 /// \brief Returns true if it is beneficial to convert a load of a constant
4099 /// to just the constant itself.
4100 bool X86TargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
4102 assert(Ty->isIntegerTy());
4104 unsigned BitSize = Ty->getPrimitiveSizeInBits();
4105 if (BitSize == 0 || BitSize > 64)
4110 bool X86TargetLowering::isExtractSubvectorCheap(EVT ResVT,
4111 unsigned Index) const {
4112 if (!isOperationLegalOrCustom(ISD::EXTRACT_SUBVECTOR, ResVT))
4115 return (Index == 0 || Index == ResVT.getVectorNumElements());
4118 bool X86TargetLowering::isCheapToSpeculateCttz() const {
4119 // Speculate cttz only if we can directly use TZCNT.
4120 return Subtarget->hasBMI();
4123 bool X86TargetLowering::isCheapToSpeculateCtlz() const {
4124 // Speculate ctlz only if we can directly use LZCNT.
4125 return Subtarget->hasLZCNT();
4128 /// Return true if every element in Mask, beginning
4129 /// from position Pos and ending in Pos+Size is undef.
4130 static bool isUndefInRange(ArrayRef<int> Mask, unsigned Pos, unsigned Size) {
4131 for (unsigned i = Pos, e = Pos + Size; i != e; ++i)
4137 /// Return true if Val is undef or if its value falls within the
4138 /// specified range (L, H].
4139 static bool isUndefOrInRange(int Val, int Low, int Hi) {
4140 return (Val < 0) || (Val >= Low && Val < Hi);
4143 /// Val is either less than zero (undef) or equal to the specified value.
4144 static bool isUndefOrEqual(int Val, int CmpVal) {
4145 return (Val < 0 || Val == CmpVal);
4148 /// Return true if every element in Mask, beginning
4149 /// from position Pos and ending in Pos+Size, falls within the specified
4150 /// sequential range (Low, Low+Size]. or is undef.
4151 static bool isSequentialOrUndefInRange(ArrayRef<int> Mask,
4152 unsigned Pos, unsigned Size, int Low) {
4153 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low)
4154 if (!isUndefOrEqual(Mask[i], Low))
4159 /// Return true if the specified EXTRACT_SUBVECTOR operand specifies a vector
4160 /// extract that is suitable for instruction that extract 128 or 256 bit vectors
4161 static bool isVEXTRACTIndex(SDNode *N, unsigned vecWidth) {
4162 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4163 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4166 // The index should be aligned on a vecWidth-bit boundary.
4168 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4170 MVT VT = N->getSimpleValueType(0);
4171 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4172 bool Result = (Index * ElSize) % vecWidth == 0;
4177 /// Return true if the specified INSERT_SUBVECTOR
4178 /// operand specifies a subvector insert that is suitable for input to
4179 /// insertion of 128 or 256-bit subvectors
4180 static bool isVINSERTIndex(SDNode *N, unsigned vecWidth) {
4181 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4182 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4184 // The index should be aligned on a vecWidth-bit boundary.
4186 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4188 MVT VT = N->getSimpleValueType(0);
4189 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4190 bool Result = (Index * ElSize) % vecWidth == 0;
4195 bool X86::isVINSERT128Index(SDNode *N) {
4196 return isVINSERTIndex(N, 128);
4199 bool X86::isVINSERT256Index(SDNode *N) {
4200 return isVINSERTIndex(N, 256);
4203 bool X86::isVEXTRACT128Index(SDNode *N) {
4204 return isVEXTRACTIndex(N, 128);
4207 bool X86::isVEXTRACT256Index(SDNode *N) {
4208 return isVEXTRACTIndex(N, 256);
4211 static unsigned getExtractVEXTRACTImmediate(SDNode *N, unsigned vecWidth) {
4212 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4213 assert(isa<ConstantSDNode>(N->getOperand(1).getNode()) &&
4214 "Illegal extract subvector for VEXTRACT");
4217 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4219 MVT VecVT = N->getOperand(0).getSimpleValueType();
4220 MVT ElVT = VecVT.getVectorElementType();
4222 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4223 return Index / NumElemsPerChunk;
4226 static unsigned getInsertVINSERTImmediate(SDNode *N, unsigned vecWidth) {
4227 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4228 assert(isa<ConstantSDNode>(N->getOperand(2).getNode()) &&
4229 "Illegal insert subvector for VINSERT");
4232 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4234 MVT VecVT = N->getSimpleValueType(0);
4235 MVT ElVT = VecVT.getVectorElementType();
4237 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4238 return Index / NumElemsPerChunk;
4241 /// Return the appropriate immediate to extract the specified
4242 /// EXTRACT_SUBVECTOR index with VEXTRACTF128 and VINSERTI128 instructions.
4243 unsigned X86::getExtractVEXTRACT128Immediate(SDNode *N) {
4244 return getExtractVEXTRACTImmediate(N, 128);
4247 /// Return the appropriate immediate to extract the specified
4248 /// EXTRACT_SUBVECTOR index with VEXTRACTF64x4 and VINSERTI64x4 instructions.
4249 unsigned X86::getExtractVEXTRACT256Immediate(SDNode *N) {
4250 return getExtractVEXTRACTImmediate(N, 256);
4253 /// Return the appropriate immediate to insert at the specified
4254 /// INSERT_SUBVECTOR index with VINSERTF128 and VINSERTI128 instructions.
4255 unsigned X86::getInsertVINSERT128Immediate(SDNode *N) {
4256 return getInsertVINSERTImmediate(N, 128);
4259 /// Return the appropriate immediate to insert at the specified
4260 /// INSERT_SUBVECTOR index with VINSERTF46x4 and VINSERTI64x4 instructions.
4261 unsigned X86::getInsertVINSERT256Immediate(SDNode *N) {
4262 return getInsertVINSERTImmediate(N, 256);
4265 /// Returns true if V is a constant integer zero.
4266 static bool isZero(SDValue V) {
4267 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
4268 return C && C->isNullValue();
4271 /// Returns true if Elt is a constant zero or a floating point constant +0.0.
4272 bool X86::isZeroNode(SDValue Elt) {
4275 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Elt))
4276 return CFP->getValueAPF().isPosZero();
4280 // Build a vector of constants
4281 // Use an UNDEF node if MaskElt == -1.
4282 // Spilt 64-bit constants in the 32-bit mode.
4283 static SDValue getConstVector(ArrayRef<int> Values, MVT VT,
4285 SDLoc dl, bool IsMask = false) {
4287 SmallVector<SDValue, 32> Ops;
4290 MVT ConstVecVT = VT;
4291 unsigned NumElts = VT.getVectorNumElements();
4292 bool In64BitMode = DAG.getTargetLoweringInfo().isTypeLegal(MVT::i64);
4293 if (!In64BitMode && VT.getVectorElementType() == MVT::i64) {
4294 ConstVecVT = MVT::getVectorVT(MVT::i32, NumElts * 2);
4298 MVT EltVT = ConstVecVT.getVectorElementType();
4299 for (unsigned i = 0; i < NumElts; ++i) {
4300 bool IsUndef = Values[i] < 0 && IsMask;
4301 SDValue OpNode = IsUndef ? DAG.getUNDEF(EltVT) :
4302 DAG.getConstant(Values[i], dl, EltVT);
4303 Ops.push_back(OpNode);
4305 Ops.push_back(IsUndef ? DAG.getUNDEF(EltVT) :
4306 DAG.getConstant(0, dl, EltVT));
4308 SDValue ConstsNode = DAG.getNode(ISD::BUILD_VECTOR, dl, ConstVecVT, Ops);
4310 ConstsNode = DAG.getBitcast(VT, ConstsNode);
4314 /// Returns a vector of specified type with all zero elements.
4315 static SDValue getZeroVector(EVT VT, const X86Subtarget *Subtarget,
4316 SelectionDAG &DAG, SDLoc dl) {
4317 assert(VT.isVector() && "Expected a vector type");
4319 // Always build SSE zero vectors as <4 x i32> bitcasted
4320 // to their dest type. This ensures they get CSE'd.
4322 if (VT.is128BitVector()) { // SSE
4323 if (Subtarget->hasSSE2()) { // SSE2
4324 SDValue Cst = DAG.getConstant(0, dl, MVT::i32);
4325 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4327 SDValue Cst = DAG.getConstantFP(+0.0, dl, MVT::f32);
4328 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
4330 } else if (VT.is256BitVector()) { // AVX
4331 if (Subtarget->hasInt256()) { // AVX2
4332 SDValue Cst = DAG.getConstant(0, dl, MVT::i32);
4333 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4334 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
4336 // 256-bit logic and arithmetic instructions in AVX are all
4337 // floating-point, no support for integer ops. Emit fp zeroed vectors.
4338 SDValue Cst = DAG.getConstantFP(+0.0, dl, MVT::f32);
4339 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4340 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops);
4342 } else if (VT.is512BitVector()) { // AVX-512
4343 SDValue Cst = DAG.getConstant(0, dl, MVT::i32);
4344 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst,
4345 Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4346 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i32, Ops);
4347 } else if (VT.getVectorElementType() == MVT::i1) {
4349 assert((Subtarget->hasBWI() || VT.getVectorNumElements() <= 16)
4350 && "Unexpected vector type");
4351 assert((Subtarget->hasVLX() || VT.getVectorNumElements() >= 8)
4352 && "Unexpected vector type");
4353 SDValue Cst = DAG.getConstant(0, dl, MVT::i1);
4354 SmallVector<SDValue, 64> Ops(VT.getVectorNumElements(), Cst);
4355 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
4357 llvm_unreachable("Unexpected vector type");
4359 return DAG.getBitcast(VT, Vec);
4362 static SDValue ExtractSubVector(SDValue Vec, unsigned IdxVal,
4363 SelectionDAG &DAG, SDLoc dl,
4364 unsigned vectorWidth) {
4365 assert((vectorWidth == 128 || vectorWidth == 256) &&
4366 "Unsupported vector width");
4367 EVT VT = Vec.getValueType();
4368 EVT ElVT = VT.getVectorElementType();
4369 unsigned Factor = VT.getSizeInBits()/vectorWidth;
4370 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT,
4371 VT.getVectorNumElements()/Factor);
4373 // Extract from UNDEF is UNDEF.
4374 if (Vec.getOpcode() == ISD::UNDEF)
4375 return DAG.getUNDEF(ResultVT);
4377 // Extract the relevant vectorWidth bits. Generate an EXTRACT_SUBVECTOR
4378 unsigned ElemsPerChunk = vectorWidth / ElVT.getSizeInBits();
4379 assert(isPowerOf2_32(ElemsPerChunk) && "Elements per chunk not power of 2");
4381 // This is the index of the first element of the vectorWidth-bit chunk
4382 // we want. Since ElemsPerChunk is a power of 2 just need to clear bits.
4383 IdxVal &= ~(ElemsPerChunk - 1);
4385 // If the input is a buildvector just emit a smaller one.
4386 if (Vec.getOpcode() == ISD::BUILD_VECTOR)
4387 return DAG.getNode(ISD::BUILD_VECTOR, dl, ResultVT,
4388 makeArrayRef(Vec->op_begin() + IdxVal, ElemsPerChunk));
4390 SDValue VecIdx = DAG.getIntPtrConstant(IdxVal, dl);
4391 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec, VecIdx);
4394 /// Generate a DAG to grab 128-bits from a vector > 128 bits. This
4395 /// sets things up to match to an AVX VEXTRACTF128 / VEXTRACTI128
4396 /// or AVX-512 VEXTRACTF32x4 / VEXTRACTI32x4
4397 /// instructions or a simple subregister reference. Idx is an index in the
4398 /// 128 bits we want. It need not be aligned to a 128-bit boundary. That makes
4399 /// lowering EXTRACT_VECTOR_ELT operations easier.
4400 static SDValue Extract128BitVector(SDValue Vec, unsigned IdxVal,
4401 SelectionDAG &DAG, SDLoc dl) {
4402 assert((Vec.getValueType().is256BitVector() ||
4403 Vec.getValueType().is512BitVector()) && "Unexpected vector size!");
4404 return ExtractSubVector(Vec, IdxVal, DAG, dl, 128);
4407 /// Generate a DAG to grab 256-bits from a 512-bit vector.
4408 static SDValue Extract256BitVector(SDValue Vec, unsigned IdxVal,
4409 SelectionDAG &DAG, SDLoc dl) {
4410 assert(Vec.getValueType().is512BitVector() && "Unexpected vector size!");
4411 return ExtractSubVector(Vec, IdxVal, DAG, dl, 256);
4414 static SDValue InsertSubVector(SDValue Result, SDValue Vec,
4415 unsigned IdxVal, SelectionDAG &DAG,
4416 SDLoc dl, unsigned vectorWidth) {
4417 assert((vectorWidth == 128 || vectorWidth == 256) &&
4418 "Unsupported vector width");
4419 // Inserting UNDEF is Result
4420 if (Vec.getOpcode() == ISD::UNDEF)
4422 EVT VT = Vec.getValueType();
4423 EVT ElVT = VT.getVectorElementType();
4424 EVT ResultVT = Result.getValueType();
4426 // Insert the relevant vectorWidth bits.
4427 unsigned ElemsPerChunk = vectorWidth/ElVT.getSizeInBits();
4428 assert(isPowerOf2_32(ElemsPerChunk) && "Elements per chunk not power of 2");
4430 // This is the index of the first element of the vectorWidth-bit chunk
4431 // we want. Since ElemsPerChunk is a power of 2 just need to clear bits.
4432 IdxVal &= ~(ElemsPerChunk - 1);
4434 SDValue VecIdx = DAG.getIntPtrConstant(IdxVal, dl);
4435 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec, VecIdx);
4438 /// Generate a DAG to put 128-bits into a vector > 128 bits. This
4439 /// sets things up to match to an AVX VINSERTF128/VINSERTI128 or
4440 /// AVX-512 VINSERTF32x4/VINSERTI32x4 instructions or a
4441 /// simple superregister reference. Idx is an index in the 128 bits
4442 /// we want. It need not be aligned to a 128-bit boundary. That makes
4443 /// lowering INSERT_VECTOR_ELT operations easier.
4444 static SDValue Insert128BitVector(SDValue Result, SDValue Vec, unsigned IdxVal,
4445 SelectionDAG &DAG, SDLoc dl) {
4446 assert(Vec.getValueType().is128BitVector() && "Unexpected vector size!");
4448 // For insertion into the zero index (low half) of a 256-bit vector, it is
4449 // more efficient to generate a blend with immediate instead of an insert*128.
4450 // We are still creating an INSERT_SUBVECTOR below with an undef node to
4451 // extend the subvector to the size of the result vector. Make sure that
4452 // we are not recursing on that node by checking for undef here.
4453 if (IdxVal == 0 && Result.getValueType().is256BitVector() &&
4454 Result.getOpcode() != ISD::UNDEF) {
4455 EVT ResultVT = Result.getValueType();
4456 SDValue ZeroIndex = DAG.getIntPtrConstant(0, dl);
4457 SDValue Undef = DAG.getUNDEF(ResultVT);
4458 SDValue Vec256 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Undef,
4461 // The blend instruction, and therefore its mask, depend on the data type.
4462 MVT ScalarType = ResultVT.getVectorElementType().getSimpleVT();
4463 if (ScalarType.isFloatingPoint()) {
4464 // Choose either vblendps (float) or vblendpd (double).
4465 unsigned ScalarSize = ScalarType.getSizeInBits();
4466 assert((ScalarSize == 64 || ScalarSize == 32) && "Unknown float type");
4467 unsigned MaskVal = (ScalarSize == 64) ? 0x03 : 0x0f;
4468 SDValue Mask = DAG.getConstant(MaskVal, dl, MVT::i8);
4469 return DAG.getNode(X86ISD::BLENDI, dl, ResultVT, Result, Vec256, Mask);
4472 const X86Subtarget &Subtarget =
4473 static_cast<const X86Subtarget &>(DAG.getSubtarget());
4475 // AVX2 is needed for 256-bit integer blend support.
4476 // Integers must be cast to 32-bit because there is only vpblendd;
4477 // vpblendw can't be used for this because it has a handicapped mask.
4479 // If we don't have AVX2, then cast to float. Using a wrong domain blend
4480 // is still more efficient than using the wrong domain vinsertf128 that
4481 // will be created by InsertSubVector().
4482 MVT CastVT = Subtarget.hasAVX2() ? MVT::v8i32 : MVT::v8f32;
4484 SDValue Mask = DAG.getConstant(0x0f, dl, MVT::i8);
4485 Vec256 = DAG.getBitcast(CastVT, Vec256);
4486 Vec256 = DAG.getNode(X86ISD::BLENDI, dl, CastVT, Result, Vec256, Mask);
4487 return DAG.getBitcast(ResultVT, Vec256);
4490 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 128);
4493 static SDValue Insert256BitVector(SDValue Result, SDValue Vec, unsigned IdxVal,
4494 SelectionDAG &DAG, SDLoc dl) {
4495 assert(Vec.getValueType().is256BitVector() && "Unexpected vector size!");
4496 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 256);
4499 /// Insert i1-subvector to i1-vector.
4500 static SDValue Insert1BitVector(SDValue Op, SelectionDAG &DAG) {
4503 SDValue Vec = Op.getOperand(0);
4504 SDValue SubVec = Op.getOperand(1);
4505 SDValue Idx = Op.getOperand(2);
4507 if (!isa<ConstantSDNode>(Idx))
4510 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
4511 if (IdxVal == 0 && Vec.isUndef()) // the operation is legal
4514 MVT OpVT = Op.getSimpleValueType();
4515 MVT SubVecVT = SubVec.getSimpleValueType();
4516 unsigned NumElems = OpVT.getVectorNumElements();
4517 unsigned SubVecNumElems = SubVecVT.getVectorNumElements();
4519 assert(IdxVal + SubVecNumElems <= NumElems &&
4520 IdxVal % SubVecVT.getSizeInBits() == 0 &&
4521 "Unexpected index value in INSERT_SUBVECTOR");
4523 // There are 3 possible cases:
4524 // 1. Subvector should be inserted in the lower part (IdxVal == 0)
4525 // 2. Subvector should be inserted in the upper part
4526 // (IdxVal + SubVecNumElems == NumElems)
4527 // 3. Subvector should be inserted in the middle (for example v2i1
4528 // to v16i1, index 2)
4530 SDValue ZeroIdx = DAG.getIntPtrConstant(0, dl);
4531 SDValue Undef = DAG.getUNDEF(OpVT);
4532 SDValue WideSubVec =
4533 DAG.getNode(ISD::INSERT_SUBVECTOR, dl, OpVT, Undef, SubVec, ZeroIdx);
4535 return DAG.getNode(X86ISD::VSHLI, dl, OpVT, WideSubVec,
4536 DAG.getConstant(IdxVal, dl, MVT::i8));
4538 if (ISD::isBuildVectorAllZeros(Vec.getNode())) {
4539 unsigned ShiftLeft = NumElems - SubVecNumElems;
4540 unsigned ShiftRight = NumElems - SubVecNumElems - IdxVal;
4541 WideSubVec = DAG.getNode(X86ISD::VSHLI, dl, OpVT, WideSubVec,
4542 DAG.getConstant(ShiftLeft, dl, MVT::i8));
4543 return ShiftRight ? DAG.getNode(X86ISD::VSRLI, dl, OpVT, WideSubVec,
4544 DAG.getConstant(ShiftRight, dl, MVT::i8)) : WideSubVec;
4548 // Zero lower bits of the Vec
4549 SDValue ShiftBits = DAG.getConstant(SubVecNumElems, dl, MVT::i8);
4550 Vec = DAG.getNode(X86ISD::VSRLI, dl, OpVT, Vec, ShiftBits);
4551 Vec = DAG.getNode(X86ISD::VSHLI, dl, OpVT, Vec, ShiftBits);
4552 // Merge them together
4553 return DAG.getNode(ISD::OR, dl, OpVT, Vec, WideSubVec);
4556 // Simple case when we put subvector in the upper part
4557 if (IdxVal + SubVecNumElems == NumElems) {
4558 // Zero upper bits of the Vec
4559 WideSubVec = DAG.getNode(X86ISD::VSHLI, dl, OpVT, Vec,
4560 DAG.getConstant(IdxVal, dl, MVT::i8));
4561 SDValue ShiftBits = DAG.getConstant(SubVecNumElems, dl, MVT::i8);
4562 Vec = DAG.getNode(X86ISD::VSHLI, dl, OpVT, Vec, ShiftBits);
4563 Vec = DAG.getNode(X86ISD::VSRLI, dl, OpVT, Vec, ShiftBits);
4564 return DAG.getNode(ISD::OR, dl, OpVT, Vec, WideSubVec);
4566 // Subvector should be inserted in the middle - use shuffle
4567 SmallVector<int, 64> Mask;
4568 for (unsigned i = 0; i < NumElems; ++i)
4569 Mask.push_back(i >= IdxVal && i < IdxVal + SubVecNumElems ?
4571 return DAG.getVectorShuffle(OpVT, dl, WideSubVec, Vec, Mask);
4574 /// Concat two 128-bit vectors into a 256 bit vector using VINSERTF128
4575 /// instructions. This is used because creating CONCAT_VECTOR nodes of
4576 /// BUILD_VECTORS returns a larger BUILD_VECTOR while we're trying to lower
4577 /// large BUILD_VECTORS.
4578 static SDValue Concat128BitVectors(SDValue V1, SDValue V2, EVT VT,
4579 unsigned NumElems, SelectionDAG &DAG,
4581 SDValue V = Insert128BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
4582 return Insert128BitVector(V, V2, NumElems/2, DAG, dl);
4585 static SDValue Concat256BitVectors(SDValue V1, SDValue V2, EVT VT,
4586 unsigned NumElems, SelectionDAG &DAG,
4588 SDValue V = Insert256BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
4589 return Insert256BitVector(V, V2, NumElems/2, DAG, dl);
4592 /// Returns a vector of specified type with all bits set.
4593 /// Always build ones vectors as <4 x i32> or <8 x i32>. For 256-bit types with
4594 /// no AVX2 supprt, use two <4 x i32> inserted in a <8 x i32> appropriately.
4595 /// Then bitcast to their original type, ensuring they get CSE'd.
4596 static SDValue getOnesVector(EVT VT, const X86Subtarget *Subtarget,
4597 SelectionDAG &DAG, SDLoc dl) {
4598 assert(VT.isVector() && "Expected a vector type");
4600 SDValue Cst = DAG.getConstant(~0U, dl, MVT::i32);
4602 if (VT.is512BitVector()) {
4603 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst,
4604 Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4605 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i32, Ops);
4606 } else if (VT.is256BitVector()) {
4607 if (Subtarget->hasInt256()) { // AVX2
4608 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4609 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
4611 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4612 Vec = Concat128BitVectors(Vec, Vec, MVT::v8i32, 8, DAG, dl);
4614 } else if (VT.is128BitVector()) {
4615 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4617 llvm_unreachable("Unexpected vector type");
4619 return DAG.getBitcast(VT, Vec);
4622 /// Returns a vector_shuffle node for an unpackl operation.
4623 static SDValue getUnpackl(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
4625 unsigned NumElems = VT.getVectorNumElements();
4626 SmallVector<int, 8> Mask;
4627 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
4629 Mask.push_back(i + NumElems);
4631 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4634 /// Returns a vector_shuffle node for an unpackh operation.
4635 static SDValue getUnpackh(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
4637 unsigned NumElems = VT.getVectorNumElements();
4638 SmallVector<int, 8> Mask;
4639 for (unsigned i = 0, Half = NumElems/2; i != Half; ++i) {
4640 Mask.push_back(i + Half);
4641 Mask.push_back(i + NumElems + Half);
4643 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4646 /// Return a vector_shuffle of the specified vector of zero or undef vector.
4647 /// This produces a shuffle where the low element of V2 is swizzled into the
4648 /// zero/undef vector, landing at element Idx.
4649 /// This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
4650 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
4652 const X86Subtarget *Subtarget,
4653 SelectionDAG &DAG) {
4654 MVT VT = V2.getSimpleValueType();
4656 ? getZeroVector(VT, Subtarget, DAG, SDLoc(V2)) : DAG.getUNDEF(VT);
4657 unsigned NumElems = VT.getVectorNumElements();
4658 SmallVector<int, 16> MaskVec;
4659 for (unsigned i = 0; i != NumElems; ++i)
4660 // If this is the insertion idx, put the low elt of V2 here.
4661 MaskVec.push_back(i == Idx ? NumElems : i);
4662 return DAG.getVectorShuffle(VT, SDLoc(V2), V1, V2, &MaskVec[0]);
4665 /// Calculates the shuffle mask corresponding to the target-specific opcode.
4666 /// Returns true if the Mask could be calculated. Sets IsUnary to true if only
4667 /// uses one source. Note that this will set IsUnary for shuffles which use a
4668 /// single input multiple times, and in those cases it will
4669 /// adjust the mask to only have indices within that single input.
4670 /// FIXME: Add support for Decode*Mask functions that return SM_SentinelZero.
4671 static bool getTargetShuffleMask(SDNode *N, MVT VT,
4672 SmallVectorImpl<int> &Mask, bool &IsUnary) {
4673 unsigned NumElems = VT.getVectorNumElements();
4677 bool IsFakeUnary = false;
4678 switch(N->getOpcode()) {
4679 case X86ISD::BLENDI:
4680 ImmN = N->getOperand(N->getNumOperands()-1);
4681 DecodeBLENDMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4684 ImmN = N->getOperand(N->getNumOperands()-1);
4685 DecodeSHUFPMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4686 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4688 case X86ISD::UNPCKH:
4689 DecodeUNPCKHMask(VT, Mask);
4690 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4692 case X86ISD::UNPCKL:
4693 DecodeUNPCKLMask(VT, Mask);
4694 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4696 case X86ISD::MOVHLPS:
4697 DecodeMOVHLPSMask(NumElems, Mask);
4698 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4700 case X86ISD::MOVLHPS:
4701 DecodeMOVLHPSMask(NumElems, Mask);
4702 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4704 case X86ISD::PALIGNR:
4705 ImmN = N->getOperand(N->getNumOperands()-1);
4706 DecodePALIGNRMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4708 case X86ISD::PSHUFD:
4709 case X86ISD::VPERMILPI:
4710 ImmN = N->getOperand(N->getNumOperands()-1);
4711 DecodePSHUFMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4714 case X86ISD::PSHUFHW:
4715 ImmN = N->getOperand(N->getNumOperands()-1);
4716 DecodePSHUFHWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4719 case X86ISD::PSHUFLW:
4720 ImmN = N->getOperand(N->getNumOperands()-1);
4721 DecodePSHUFLWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4724 case X86ISD::PSHUFB: {
4726 SDValue MaskNode = N->getOperand(1);
4727 while (MaskNode->getOpcode() == ISD::BITCAST)
4728 MaskNode = MaskNode->getOperand(0);
4730 if (MaskNode->getOpcode() == ISD::BUILD_VECTOR) {
4731 // If we have a build-vector, then things are easy.
4732 MVT VT = MaskNode.getSimpleValueType();
4733 assert(VT.isVector() &&
4734 "Can't produce a non-vector with a build_vector!");
4735 if (!VT.isInteger())
4738 int NumBytesPerElement = VT.getVectorElementType().getSizeInBits() / 8;
4740 SmallVector<uint64_t, 32> RawMask;
4741 for (int i = 0, e = MaskNode->getNumOperands(); i < e; ++i) {
4742 SDValue Op = MaskNode->getOperand(i);
4743 if (Op->getOpcode() == ISD::UNDEF) {
4744 RawMask.push_back((uint64_t)SM_SentinelUndef);
4747 auto *CN = dyn_cast<ConstantSDNode>(Op.getNode());
4750 APInt MaskElement = CN->getAPIntValue();
4752 // We now have to decode the element which could be any integer size and
4753 // extract each byte of it.
4754 for (int j = 0; j < NumBytesPerElement; ++j) {
4755 // Note that this is x86 and so always little endian: the low byte is
4756 // the first byte of the mask.
4757 RawMask.push_back(MaskElement.getLoBits(8).getZExtValue());
4758 MaskElement = MaskElement.lshr(8);
4761 DecodePSHUFBMask(RawMask, Mask);
4765 auto *MaskLoad = dyn_cast<LoadSDNode>(MaskNode);
4769 SDValue Ptr = MaskLoad->getBasePtr();
4770 if (Ptr->getOpcode() == X86ISD::Wrapper ||
4771 Ptr->getOpcode() == X86ISD::WrapperRIP)
4772 Ptr = Ptr->getOperand(0);
4774 auto *MaskCP = dyn_cast<ConstantPoolSDNode>(Ptr);
4775 if (!MaskCP || MaskCP->isMachineConstantPoolEntry())
4778 if (auto *C = dyn_cast<Constant>(MaskCP->getConstVal())) {
4779 DecodePSHUFBMask(C, Mask);
4787 case X86ISD::VPERMI:
4788 ImmN = N->getOperand(N->getNumOperands()-1);
4789 DecodeVPERMMask(cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4794 DecodeScalarMoveMask(VT, /* IsLoad */ false, Mask);
4796 case X86ISD::VPERM2X128:
4797 ImmN = N->getOperand(N->getNumOperands()-1);
4798 DecodeVPERM2X128Mask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4799 if (Mask.empty()) return false;
4800 // Mask only contains negative index if an element is zero.
4801 if (std::any_of(Mask.begin(), Mask.end(),
4802 [](int M){ return M == SM_SentinelZero; }))
4805 case X86ISD::MOVSLDUP:
4806 DecodeMOVSLDUPMask(VT, Mask);
4809 case X86ISD::MOVSHDUP:
4810 DecodeMOVSHDUPMask(VT, Mask);
4813 case X86ISD::MOVDDUP:
4814 DecodeMOVDDUPMask(VT, Mask);
4817 case X86ISD::MOVLHPD:
4818 case X86ISD::MOVLPD:
4819 case X86ISD::MOVLPS:
4820 // Not yet implemented
4822 case X86ISD::VPERMV: {
4824 SDValue MaskNode = N->getOperand(0);
4825 while (MaskNode->getOpcode() == ISD::BITCAST)
4826 MaskNode = MaskNode->getOperand(0);
4828 unsigned MaskLoBits = Log2_64(VT.getVectorNumElements());
4829 SmallVector<uint64_t, 32> RawMask;
4830 if (MaskNode->getOpcode() == ISD::BUILD_VECTOR) {
4831 // If we have a build-vector, then things are easy.
4832 assert(MaskNode.getSimpleValueType().isInteger() &&
4833 MaskNode.getSimpleValueType().getVectorNumElements() ==
4834 VT.getVectorNumElements());
4836 for (unsigned i = 0; i < MaskNode->getNumOperands(); ++i) {
4837 SDValue Op = MaskNode->getOperand(i);
4838 if (Op->getOpcode() == ISD::UNDEF)
4839 RawMask.push_back((uint64_t)SM_SentinelUndef);
4840 else if (isa<ConstantSDNode>(Op)) {
4841 APInt MaskElement = cast<ConstantSDNode>(Op)->getAPIntValue();
4842 RawMask.push_back(MaskElement.getLoBits(MaskLoBits).getZExtValue());
4846 DecodeVPERMVMask(RawMask, Mask);
4849 if (MaskNode->getOpcode() == X86ISD::VBROADCAST) {
4850 unsigned NumEltsInMask = MaskNode->getNumOperands();
4851 MaskNode = MaskNode->getOperand(0);
4852 auto *CN = dyn_cast<ConstantSDNode>(MaskNode);
4854 APInt MaskEltValue = CN->getAPIntValue();
4855 for (unsigned i = 0; i < NumEltsInMask; ++i)
4856 RawMask.push_back(MaskEltValue.getLoBits(MaskLoBits).getZExtValue());
4857 DecodeVPERMVMask(RawMask, Mask);
4860 // It may be a scalar load
4863 auto *MaskLoad = dyn_cast<LoadSDNode>(MaskNode);
4867 SDValue Ptr = MaskLoad->getBasePtr();
4868 if (Ptr->getOpcode() == X86ISD::Wrapper ||
4869 Ptr->getOpcode() == X86ISD::WrapperRIP)
4870 Ptr = Ptr->getOperand(0);
4872 auto *MaskCP = dyn_cast<ConstantPoolSDNode>(Ptr);
4873 if (!MaskCP || MaskCP->isMachineConstantPoolEntry())
4876 auto *C = dyn_cast<Constant>(MaskCP->getConstVal());
4878 DecodeVPERMVMask(C, VT, Mask);
4885 case X86ISD::VPERMV3: {
4887 SDValue MaskNode = N->getOperand(1);
4888 while (MaskNode->getOpcode() == ISD::BITCAST)
4889 MaskNode = MaskNode->getOperand(1);
4891 if (MaskNode->getOpcode() == ISD::BUILD_VECTOR) {
4892 // If we have a build-vector, then things are easy.
4893 assert(MaskNode.getSimpleValueType().isInteger() &&
4894 MaskNode.getSimpleValueType().getVectorNumElements() ==
4895 VT.getVectorNumElements());
4897 SmallVector<uint64_t, 32> RawMask;
4898 unsigned MaskLoBits = Log2_64(VT.getVectorNumElements()*2);
4900 for (unsigned i = 0; i < MaskNode->getNumOperands(); ++i) {
4901 SDValue Op = MaskNode->getOperand(i);
4902 if (Op->getOpcode() == ISD::UNDEF)
4903 RawMask.push_back((uint64_t)SM_SentinelUndef);
4905 auto *CN = dyn_cast<ConstantSDNode>(Op.getNode());
4908 APInt MaskElement = CN->getAPIntValue();
4909 RawMask.push_back(MaskElement.getLoBits(MaskLoBits).getZExtValue());
4912 DecodeVPERMV3Mask(RawMask, Mask);
4916 auto *MaskLoad = dyn_cast<LoadSDNode>(MaskNode);
4920 SDValue Ptr = MaskLoad->getBasePtr();
4921 if (Ptr->getOpcode() == X86ISD::Wrapper ||
4922 Ptr->getOpcode() == X86ISD::WrapperRIP)
4923 Ptr = Ptr->getOperand(0);
4925 auto *MaskCP = dyn_cast<ConstantPoolSDNode>(Ptr);
4926 if (!MaskCP || MaskCP->isMachineConstantPoolEntry())
4929 auto *C = dyn_cast<Constant>(MaskCP->getConstVal());
4931 DecodeVPERMV3Mask(C, VT, Mask);
4938 default: llvm_unreachable("unknown target shuffle node");
4941 // If we have a fake unary shuffle, the shuffle mask is spread across two
4942 // inputs that are actually the same node. Re-map the mask to always point
4943 // into the first input.
4946 if (M >= (int)Mask.size())
4952 /// Returns the scalar element that will make up the ith
4953 /// element of the result of the vector shuffle.
4954 static SDValue getShuffleScalarElt(SDNode *N, unsigned Index, SelectionDAG &DAG,
4957 return SDValue(); // Limit search depth.
4959 SDValue V = SDValue(N, 0);
4960 EVT VT = V.getValueType();
4961 unsigned Opcode = V.getOpcode();
4963 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars.
4964 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) {
4965 int Elt = SV->getMaskElt(Index);
4968 return DAG.getUNDEF(VT.getVectorElementType());
4970 unsigned NumElems = VT.getVectorNumElements();
4971 SDValue NewV = (Elt < (int)NumElems) ? SV->getOperand(0)
4972 : SV->getOperand(1);
4973 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG, Depth+1);
4976 // Recurse into target specific vector shuffles to find scalars.
4977 if (isTargetShuffle(Opcode)) {
4978 MVT ShufVT = V.getSimpleValueType();
4979 unsigned NumElems = ShufVT.getVectorNumElements();
4980 SmallVector<int, 16> ShuffleMask;
4983 if (!getTargetShuffleMask(N, ShufVT, ShuffleMask, IsUnary))
4986 int Elt = ShuffleMask[Index];
4988 return DAG.getUNDEF(ShufVT.getVectorElementType());
4990 SDValue NewV = (Elt < (int)NumElems) ? N->getOperand(0)
4992 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG,
4996 // Actual nodes that may contain scalar elements
4997 if (Opcode == ISD::BITCAST) {
4998 V = V.getOperand(0);
4999 EVT SrcVT = V.getValueType();
5000 unsigned NumElems = VT.getVectorNumElements();
5002 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems)
5006 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR)
5007 return (Index == 0) ? V.getOperand(0)
5008 : DAG.getUNDEF(VT.getVectorElementType());
5010 if (V.getOpcode() == ISD::BUILD_VECTOR)
5011 return V.getOperand(Index);
5016 /// Custom lower build_vector of v16i8.
5017 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
5018 unsigned NumNonZero, unsigned NumZero,
5020 const X86Subtarget* Subtarget,
5021 const TargetLowering &TLI) {
5029 // SSE4.1 - use PINSRB to insert each byte directly.
5030 if (Subtarget->hasSSE41()) {
5031 for (unsigned i = 0; i < 16; ++i) {
5032 bool isNonZero = (NonZeros & (1 << i)) != 0;
5036 V = getZeroVector(MVT::v16i8, Subtarget, DAG, dl);
5038 V = DAG.getUNDEF(MVT::v16i8);
5041 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
5042 MVT::v16i8, V, Op.getOperand(i),
5043 DAG.getIntPtrConstant(i, dl));
5050 // Pre-SSE4.1 - merge byte pairs and insert with PINSRW.
5051 for (unsigned i = 0; i < 16; ++i) {
5052 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
5053 if (ThisIsNonZero && First) {
5055 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
5057 V = DAG.getUNDEF(MVT::v8i16);
5062 SDValue ThisElt, LastElt;
5063 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
5064 if (LastIsNonZero) {
5065 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
5066 MVT::i16, Op.getOperand(i-1));
5068 if (ThisIsNonZero) {
5069 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
5070 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
5071 ThisElt, DAG.getConstant(8, dl, MVT::i8));
5073 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
5077 if (ThisElt.getNode())
5078 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
5079 DAG.getIntPtrConstant(i/2, dl));
5083 return DAG.getBitcast(MVT::v16i8, V);
5086 /// Custom lower build_vector of v8i16.
5087 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
5088 unsigned NumNonZero, unsigned NumZero,
5090 const X86Subtarget* Subtarget,
5091 const TargetLowering &TLI) {
5098 for (unsigned i = 0; i < 8; ++i) {
5099 bool isNonZero = (NonZeros & (1 << i)) != 0;
5103 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
5105 V = DAG.getUNDEF(MVT::v8i16);
5108 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
5109 MVT::v8i16, V, Op.getOperand(i),
5110 DAG.getIntPtrConstant(i, dl));
5117 /// Custom lower build_vector of v4i32 or v4f32.
5118 static SDValue LowerBuildVectorv4x32(SDValue Op, SelectionDAG &DAG,
5119 const X86Subtarget *Subtarget,
5120 const TargetLowering &TLI) {
5121 // Find all zeroable elements.
5122 std::bitset<4> Zeroable;
5123 for (int i=0; i < 4; ++i) {
5124 SDValue Elt = Op->getOperand(i);
5125 Zeroable[i] = (Elt.getOpcode() == ISD::UNDEF || X86::isZeroNode(Elt));
5127 assert(Zeroable.size() - Zeroable.count() > 1 &&
5128 "We expect at least two non-zero elements!");
5130 // We only know how to deal with build_vector nodes where elements are either
5131 // zeroable or extract_vector_elt with constant index.
5132 SDValue FirstNonZero;
5133 unsigned FirstNonZeroIdx;
5134 for (unsigned i=0; i < 4; ++i) {
5137 SDValue Elt = Op->getOperand(i);
5138 if (Elt.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
5139 !isa<ConstantSDNode>(Elt.getOperand(1)))
5141 // Make sure that this node is extracting from a 128-bit vector.
5142 MVT VT = Elt.getOperand(0).getSimpleValueType();
5143 if (!VT.is128BitVector())
5145 if (!FirstNonZero.getNode()) {
5147 FirstNonZeroIdx = i;
5151 assert(FirstNonZero.getNode() && "Unexpected build vector of all zeros!");
5152 SDValue V1 = FirstNonZero.getOperand(0);
5153 MVT VT = V1.getSimpleValueType();
5155 // See if this build_vector can be lowered as a blend with zero.
5157 unsigned EltMaskIdx, EltIdx;
5159 for (EltIdx = 0; EltIdx < 4; ++EltIdx) {
5160 if (Zeroable[EltIdx]) {
5161 // The zero vector will be on the right hand side.
5162 Mask[EltIdx] = EltIdx+4;
5166 Elt = Op->getOperand(EltIdx);
5167 // By construction, Elt is a EXTRACT_VECTOR_ELT with constant index.
5168 EltMaskIdx = cast<ConstantSDNode>(Elt.getOperand(1))->getZExtValue();
5169 if (Elt.getOperand(0) != V1 || EltMaskIdx != EltIdx)
5171 Mask[EltIdx] = EltIdx;
5175 // Let the shuffle legalizer deal with blend operations.
5176 SDValue VZero = getZeroVector(VT, Subtarget, DAG, SDLoc(Op));
5177 if (V1.getSimpleValueType() != VT)
5178 V1 = DAG.getNode(ISD::BITCAST, SDLoc(V1), VT, V1);
5179 return DAG.getVectorShuffle(VT, SDLoc(V1), V1, VZero, &Mask[0]);
5182 // See if we can lower this build_vector to a INSERTPS.
5183 if (!Subtarget->hasSSE41())
5186 SDValue V2 = Elt.getOperand(0);
5187 if (Elt == FirstNonZero && EltIdx == FirstNonZeroIdx)
5190 bool CanFold = true;
5191 for (unsigned i = EltIdx + 1; i < 4 && CanFold; ++i) {
5195 SDValue Current = Op->getOperand(i);
5196 SDValue SrcVector = Current->getOperand(0);
5199 CanFold = SrcVector == V1 &&
5200 cast<ConstantSDNode>(Current.getOperand(1))->getZExtValue() == i;
5206 assert(V1.getNode() && "Expected at least two non-zero elements!");
5207 if (V1.getSimpleValueType() != MVT::v4f32)
5208 V1 = DAG.getNode(ISD::BITCAST, SDLoc(V1), MVT::v4f32, V1);
5209 if (V2.getSimpleValueType() != MVT::v4f32)
5210 V2 = DAG.getNode(ISD::BITCAST, SDLoc(V2), MVT::v4f32, V2);
5212 // Ok, we can emit an INSERTPS instruction.
5213 unsigned ZMask = Zeroable.to_ulong();
5215 unsigned InsertPSMask = EltMaskIdx << 6 | EltIdx << 4 | ZMask;
5216 assert((InsertPSMask & ~0xFFu) == 0 && "Invalid mask!");
5218 SDValue Result = DAG.getNode(X86ISD::INSERTPS, DL, MVT::v4f32, V1, V2,
5219 DAG.getIntPtrConstant(InsertPSMask, DL));
5220 return DAG.getBitcast(VT, Result);
5223 /// Return a vector logical shift node.
5224 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
5225 unsigned NumBits, SelectionDAG &DAG,
5226 const TargetLowering &TLI, SDLoc dl) {
5227 assert(VT.is128BitVector() && "Unknown type for VShift");
5228 MVT ShVT = MVT::v2i64;
5229 unsigned Opc = isLeft ? X86ISD::VSHLDQ : X86ISD::VSRLDQ;
5230 SrcOp = DAG.getBitcast(ShVT, SrcOp);
5231 MVT ScalarShiftTy = TLI.getScalarShiftAmountTy(DAG.getDataLayout(), VT);
5232 assert(NumBits % 8 == 0 && "Only support byte sized shifts");
5233 SDValue ShiftVal = DAG.getConstant(NumBits/8, dl, ScalarShiftTy);
5234 return DAG.getBitcast(VT, DAG.getNode(Opc, dl, ShVT, SrcOp, ShiftVal));
5238 LowerAsSplatVectorLoad(SDValue SrcOp, MVT VT, SDLoc dl, SelectionDAG &DAG) {
5240 // Check if the scalar load can be widened into a vector load. And if
5241 // the address is "base + cst" see if the cst can be "absorbed" into
5242 // the shuffle mask.
5243 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) {
5244 SDValue Ptr = LD->getBasePtr();
5245 if (!ISD::isNormalLoad(LD) || LD->isVolatile())
5247 EVT PVT = LD->getValueType(0);
5248 if (PVT != MVT::i32 && PVT != MVT::f32)
5253 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) {
5254 FI = FINode->getIndex();
5256 } else if (DAG.isBaseWithConstantOffset(Ptr) &&
5257 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
5258 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
5259 Offset = Ptr.getConstantOperandVal(1);
5260 Ptr = Ptr.getOperand(0);
5265 // FIXME: 256-bit vector instructions don't require a strict alignment,
5266 // improve this code to support it better.
5267 unsigned RequiredAlign = VT.getSizeInBits()/8;
5268 SDValue Chain = LD->getChain();
5269 // Make sure the stack object alignment is at least 16 or 32.
5270 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
5271 if (DAG.InferPtrAlignment(Ptr) < RequiredAlign) {
5272 if (MFI->isFixedObjectIndex(FI)) {
5273 // Can't change the alignment. FIXME: It's possible to compute
5274 // the exact stack offset and reference FI + adjust offset instead.
5275 // If someone *really* cares about this. That's the way to implement it.
5278 MFI->setObjectAlignment(FI, RequiredAlign);
5282 // (Offset % 16 or 32) must be multiple of 4. Then address is then
5283 // Ptr + (Offset & ~15).
5286 if ((Offset % RequiredAlign) & 3)
5288 int64_t StartOffset = Offset & ~int64_t(RequiredAlign - 1);
5291 Ptr = DAG.getNode(ISD::ADD, DL, Ptr.getValueType(), Ptr,
5292 DAG.getConstant(StartOffset, DL, Ptr.getValueType()));
5295 int EltNo = (Offset - StartOffset) >> 2;
5296 unsigned NumElems = VT.getVectorNumElements();
5298 EVT NVT = EVT::getVectorVT(*DAG.getContext(), PVT, NumElems);
5299 SDValue V1 = DAG.getLoad(NVT, dl, Chain, Ptr,
5300 LD->getPointerInfo().getWithOffset(StartOffset),
5301 false, false, false, 0);
5303 SmallVector<int, 8> Mask(NumElems, EltNo);
5305 return DAG.getVectorShuffle(NVT, dl, V1, DAG.getUNDEF(NVT), &Mask[0]);
5311 /// Given the initializing elements 'Elts' of a vector of type 'VT', see if the
5312 /// elements can be replaced by a single large load which has the same value as
5313 /// a build_vector or insert_subvector whose loaded operands are 'Elts'.
5315 /// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a
5317 /// FIXME: we'd also like to handle the case where the last elements are zero
5318 /// rather than undef via VZEXT_LOAD, but we do not detect that case today.
5319 /// There's even a handy isZeroNode for that purpose.
5320 static SDValue EltsFromConsecutiveLoads(EVT VT, ArrayRef<SDValue> Elts,
5321 SDLoc &DL, SelectionDAG &DAG,
5322 bool isAfterLegalize) {
5323 unsigned NumElems = Elts.size();
5325 LoadSDNode *LDBase = nullptr;
5326 unsigned LastLoadedElt = -1U;
5328 // For each element in the initializer, see if we've found a load or an undef.
5329 // If we don't find an initial load element, or later load elements are
5330 // non-consecutive, bail out.
5331 for (unsigned i = 0; i < NumElems; ++i) {
5332 SDValue Elt = Elts[i];
5333 // Look through a bitcast.
5334 if (Elt.getNode() && Elt.getOpcode() == ISD::BITCAST)
5335 Elt = Elt.getOperand(0);
5336 if (!Elt.getNode() ||
5337 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
5340 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
5342 LDBase = cast<LoadSDNode>(Elt.getNode());
5346 if (Elt.getOpcode() == ISD::UNDEF)
5349 LoadSDNode *LD = cast<LoadSDNode>(Elt);
5350 EVT LdVT = Elt.getValueType();
5351 // Each loaded element must be the correct fractional portion of the
5352 // requested vector load.
5353 if (LdVT.getSizeInBits() != VT.getSizeInBits() / NumElems)
5355 if (!DAG.isConsecutiveLoad(LD, LDBase, LdVT.getSizeInBits() / 8, i))
5360 // If we have found an entire vector of loads and undefs, then return a large
5361 // load of the entire vector width starting at the base pointer. If we found
5362 // consecutive loads for the low half, generate a vzext_load node.
5363 if (LastLoadedElt == NumElems - 1) {
5364 assert(LDBase && "Did not find base load for merging consecutive loads");
5365 EVT EltVT = LDBase->getValueType(0);
5366 // Ensure that the input vector size for the merged loads matches the
5367 // cumulative size of the input elements.
5368 if (VT.getSizeInBits() != EltVT.getSizeInBits() * NumElems)
5371 if (isAfterLegalize &&
5372 !DAG.getTargetLoweringInfo().isOperationLegal(ISD::LOAD, VT))
5375 SDValue NewLd = SDValue();
5377 NewLd = DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
5378 LDBase->getPointerInfo(), LDBase->isVolatile(),
5379 LDBase->isNonTemporal(), LDBase->isInvariant(),
5380 LDBase->getAlignment());
5382 if (LDBase->hasAnyUseOfValue(1)) {
5383 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
5385 SDValue(NewLd.getNode(), 1));
5386 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
5387 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
5388 SDValue(NewLd.getNode(), 1));
5394 //TODO: The code below fires only for for loading the low v2i32 / v2f32
5395 //of a v4i32 / v4f32. It's probably worth generalizing.
5396 EVT EltVT = VT.getVectorElementType();
5397 if (NumElems == 4 && LastLoadedElt == 1 && (EltVT.getSizeInBits() == 32) &&
5398 DAG.getTargetLoweringInfo().isTypeLegal(MVT::v2i64)) {
5399 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
5400 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() };
5402 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys, Ops, MVT::i64,
5403 LDBase->getPointerInfo(),
5404 LDBase->getAlignment(),
5405 false/*isVolatile*/, true/*ReadMem*/,
5408 // Make sure the newly-created LOAD is in the same position as LDBase in
5409 // terms of dependency. We create a TokenFactor for LDBase and ResNode, and
5410 // update uses of LDBase's output chain to use the TokenFactor.
5411 if (LDBase->hasAnyUseOfValue(1)) {
5412 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
5413 SDValue(LDBase, 1), SDValue(ResNode.getNode(), 1));
5414 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
5415 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
5416 SDValue(ResNode.getNode(), 1));
5419 return DAG.getBitcast(VT, ResNode);
5424 /// LowerVectorBroadcast - Attempt to use the vbroadcast instruction
5425 /// to generate a splat value for the following cases:
5426 /// 1. A splat BUILD_VECTOR which uses a single scalar load, or a constant.
5427 /// 2. A splat shuffle which uses a scalar_to_vector node which comes from
5428 /// a scalar load, or a constant.
5429 /// The VBROADCAST node is returned when a pattern is found,
5430 /// or SDValue() otherwise.
5431 static SDValue LowerVectorBroadcast(SDValue Op, const X86Subtarget* Subtarget,
5432 SelectionDAG &DAG) {
5433 // VBROADCAST requires AVX.
5434 // TODO: Splats could be generated for non-AVX CPUs using SSE
5435 // instructions, but there's less potential gain for only 128-bit vectors.
5436 if (!Subtarget->hasAVX())
5439 MVT VT = Op.getSimpleValueType();
5442 assert((VT.is128BitVector() || VT.is256BitVector() || VT.is512BitVector()) &&
5443 "Unsupported vector type for broadcast.");
5448 switch (Op.getOpcode()) {
5450 // Unknown pattern found.
5453 case ISD::BUILD_VECTOR: {
5454 auto *BVOp = cast<BuildVectorSDNode>(Op.getNode());
5455 BitVector UndefElements;
5456 SDValue Splat = BVOp->getSplatValue(&UndefElements);
5458 // We need a splat of a single value to use broadcast, and it doesn't
5459 // make any sense if the value is only in one element of the vector.
5460 if (!Splat || (VT.getVectorNumElements() - UndefElements.count()) <= 1)
5464 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
5465 Ld.getOpcode() == ISD::ConstantFP);
5467 // Make sure that all of the users of a non-constant load are from the
5468 // BUILD_VECTOR node.
5469 if (!ConstSplatVal && !BVOp->isOnlyUserOf(Ld.getNode()))
5474 case ISD::VECTOR_SHUFFLE: {
5475 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
5477 // Shuffles must have a splat mask where the first element is
5479 if ((!SVOp->isSplat()) || SVOp->getMaskElt(0) != 0)
5482 SDValue Sc = Op.getOperand(0);
5483 if (Sc.getOpcode() != ISD::SCALAR_TO_VECTOR &&
5484 Sc.getOpcode() != ISD::BUILD_VECTOR) {
5486 if (!Subtarget->hasInt256())
5489 // Use the register form of the broadcast instruction available on AVX2.
5490 if (VT.getSizeInBits() >= 256)
5491 Sc = Extract128BitVector(Sc, 0, DAG, dl);
5492 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Sc);
5495 Ld = Sc.getOperand(0);
5496 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
5497 Ld.getOpcode() == ISD::ConstantFP);
5499 // The scalar_to_vector node and the suspected
5500 // load node must have exactly one user.
5501 // Constants may have multiple users.
5503 // AVX-512 has register version of the broadcast
5504 bool hasRegVer = Subtarget->hasAVX512() && VT.is512BitVector() &&
5505 Ld.getValueType().getSizeInBits() >= 32;
5506 if (!ConstSplatVal && ((!Sc.hasOneUse() || !Ld.hasOneUse()) &&
5513 unsigned ScalarSize = Ld.getValueType().getSizeInBits();
5514 bool IsGE256 = (VT.getSizeInBits() >= 256);
5516 // When optimizing for size, generate up to 5 extra bytes for a broadcast
5517 // instruction to save 8 or more bytes of constant pool data.
5518 // TODO: If multiple splats are generated to load the same constant,
5519 // it may be detrimental to overall size. There needs to be a way to detect
5520 // that condition to know if this is truly a size win.
5521 bool OptForSize = DAG.getMachineFunction().getFunction()->optForSize();
5523 // Handle broadcasting a single constant scalar from the constant pool
5525 // On Sandybridge (no AVX2), it is still better to load a constant vector
5526 // from the constant pool and not to broadcast it from a scalar.
5527 // But override that restriction when optimizing for size.
5528 // TODO: Check if splatting is recommended for other AVX-capable CPUs.
5529 if (ConstSplatVal && (Subtarget->hasAVX2() || OptForSize)) {
5530 EVT CVT = Ld.getValueType();
5531 assert(!CVT.isVector() && "Must not broadcast a vector type");
5533 // Splat f32, i32, v4f64, v4i64 in all cases with AVX2.
5534 // For size optimization, also splat v2f64 and v2i64, and for size opt
5535 // with AVX2, also splat i8 and i16.
5536 // With pattern matching, the VBROADCAST node may become a VMOVDDUP.
5537 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64) ||
5538 (OptForSize && (ScalarSize == 64 || Subtarget->hasAVX2()))) {
5539 const Constant *C = nullptr;
5540 if (ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Ld))
5541 C = CI->getConstantIntValue();
5542 else if (ConstantFPSDNode *CF = dyn_cast<ConstantFPSDNode>(Ld))
5543 C = CF->getConstantFPValue();
5545 assert(C && "Invalid constant type");
5547 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5549 DAG.getConstantPool(C, TLI.getPointerTy(DAG.getDataLayout()));
5550 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
5552 CVT, dl, DAG.getEntryNode(), CP,
5553 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()), false,
5554 false, false, Alignment);
5556 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5560 bool IsLoad = ISD::isNormalLoad(Ld.getNode());
5562 // Handle AVX2 in-register broadcasts.
5563 if (!IsLoad && Subtarget->hasInt256() &&
5564 (ScalarSize == 32 || (IsGE256 && ScalarSize == 64)))
5565 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5567 // The scalar source must be a normal load.
5571 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64) ||
5572 (Subtarget->hasVLX() && ScalarSize == 64))
5573 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5575 // The integer check is needed for the 64-bit into 128-bit so it doesn't match
5576 // double since there is no vbroadcastsd xmm
5577 if (Subtarget->hasInt256() && Ld.getValueType().isInteger()) {
5578 if (ScalarSize == 8 || ScalarSize == 16 || ScalarSize == 64)
5579 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5582 // Unsupported broadcast.
5586 /// \brief For an EXTRACT_VECTOR_ELT with a constant index return the real
5587 /// underlying vector and index.
5589 /// Modifies \p ExtractedFromVec to the real vector and returns the real
5591 static int getUnderlyingExtractedFromVec(SDValue &ExtractedFromVec,
5593 int Idx = cast<ConstantSDNode>(ExtIdx)->getZExtValue();
5594 if (!isa<ShuffleVectorSDNode>(ExtractedFromVec))
5597 // For 256-bit vectors, LowerEXTRACT_VECTOR_ELT_SSE4 may have already
5599 // (extract_vector_elt (v8f32 %vreg1), Constant<6>)
5601 // (extract_vector_elt (vector_shuffle<2,u,u,u>
5602 // (extract_subvector (v8f32 %vreg0), Constant<4>),
5605 // In this case the vector is the extract_subvector expression and the index
5606 // is 2, as specified by the shuffle.
5607 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(ExtractedFromVec);
5608 SDValue ShuffleVec = SVOp->getOperand(0);
5609 MVT ShuffleVecVT = ShuffleVec.getSimpleValueType();
5610 assert(ShuffleVecVT.getVectorElementType() ==
5611 ExtractedFromVec.getSimpleValueType().getVectorElementType());
5613 int ShuffleIdx = SVOp->getMaskElt(Idx);
5614 if (isUndefOrInRange(ShuffleIdx, 0, ShuffleVecVT.getVectorNumElements())) {
5615 ExtractedFromVec = ShuffleVec;
5621 static SDValue buildFromShuffleMostly(SDValue Op, SelectionDAG &DAG) {
5622 MVT VT = Op.getSimpleValueType();
5624 // Skip if insert_vec_elt is not supported.
5625 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5626 if (!TLI.isOperationLegalOrCustom(ISD::INSERT_VECTOR_ELT, VT))
5630 unsigned NumElems = Op.getNumOperands();
5634 SmallVector<unsigned, 4> InsertIndices;
5635 SmallVector<int, 8> Mask(NumElems, -1);
5637 for (unsigned i = 0; i != NumElems; ++i) {
5638 unsigned Opc = Op.getOperand(i).getOpcode();
5640 if (Opc == ISD::UNDEF)
5643 if (Opc != ISD::EXTRACT_VECTOR_ELT) {
5644 // Quit if more than 1 elements need inserting.
5645 if (InsertIndices.size() > 1)
5648 InsertIndices.push_back(i);
5652 SDValue ExtractedFromVec = Op.getOperand(i).getOperand(0);
5653 SDValue ExtIdx = Op.getOperand(i).getOperand(1);
5654 // Quit if non-constant index.
5655 if (!isa<ConstantSDNode>(ExtIdx))
5657 int Idx = getUnderlyingExtractedFromVec(ExtractedFromVec, ExtIdx);
5659 // Quit if extracted from vector of different type.
5660 if (ExtractedFromVec.getValueType() != VT)
5663 if (!VecIn1.getNode())
5664 VecIn1 = ExtractedFromVec;
5665 else if (VecIn1 != ExtractedFromVec) {
5666 if (!VecIn2.getNode())
5667 VecIn2 = ExtractedFromVec;
5668 else if (VecIn2 != ExtractedFromVec)
5669 // Quit if more than 2 vectors to shuffle
5673 if (ExtractedFromVec == VecIn1)
5675 else if (ExtractedFromVec == VecIn2)
5676 Mask[i] = Idx + NumElems;
5679 if (!VecIn1.getNode())
5682 VecIn2 = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT);
5683 SDValue NV = DAG.getVectorShuffle(VT, DL, VecIn1, VecIn2, &Mask[0]);
5684 for (unsigned i = 0, e = InsertIndices.size(); i != e; ++i) {
5685 unsigned Idx = InsertIndices[i];
5686 NV = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VT, NV, Op.getOperand(Idx),
5687 DAG.getIntPtrConstant(Idx, DL));
5693 static SDValue ConvertI1VectorToInteger(SDValue Op, SelectionDAG &DAG) {
5694 assert(ISD::isBuildVectorOfConstantSDNodes(Op.getNode()) &&
5695 Op.getScalarValueSizeInBits() == 1 &&
5696 "Can not convert non-constant vector");
5697 uint64_t Immediate = 0;
5698 for (unsigned idx = 0, e = Op.getNumOperands(); idx < e; ++idx) {
5699 SDValue In = Op.getOperand(idx);
5700 if (In.getOpcode() != ISD::UNDEF)
5701 Immediate |= cast<ConstantSDNode>(In)->getZExtValue() << idx;
5705 MVT::getIntegerVT(std::max((int)Op.getValueType().getSizeInBits(), 8));
5706 return DAG.getConstant(Immediate, dl, VT);
5708 // Lower BUILD_VECTOR operation for v8i1 and v16i1 types.
5710 X86TargetLowering::LowerBUILD_VECTORvXi1(SDValue Op, SelectionDAG &DAG) const {
5712 MVT VT = Op.getSimpleValueType();
5713 assert((VT.getVectorElementType() == MVT::i1) &&
5714 "Unexpected type in LowerBUILD_VECTORvXi1!");
5717 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
5718 SDValue Cst = DAG.getTargetConstant(0, dl, MVT::i1);
5719 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
5720 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
5723 if (ISD::isBuildVectorAllOnes(Op.getNode())) {
5724 SDValue Cst = DAG.getTargetConstant(1, dl, MVT::i1);
5725 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
5726 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
5729 if (ISD::isBuildVectorOfConstantSDNodes(Op.getNode())) {
5730 SDValue Imm = ConvertI1VectorToInteger(Op, DAG);
5731 if (Imm.getValueSizeInBits() == VT.getSizeInBits())
5732 return DAG.getBitcast(VT, Imm);
5733 SDValue ExtVec = DAG.getBitcast(MVT::v8i1, Imm);
5734 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, ExtVec,
5735 DAG.getIntPtrConstant(0, dl));
5738 // Vector has one or more non-const elements
5739 uint64_t Immediate = 0;
5740 SmallVector<unsigned, 16> NonConstIdx;
5741 bool IsSplat = true;
5742 bool HasConstElts = false;
5744 for (unsigned idx = 0, e = Op.getNumOperands(); idx < e; ++idx) {
5745 SDValue In = Op.getOperand(idx);
5746 if (In.getOpcode() == ISD::UNDEF)
5748 if (!isa<ConstantSDNode>(In))
5749 NonConstIdx.push_back(idx);
5751 Immediate |= cast<ConstantSDNode>(In)->getZExtValue() << idx;
5752 HasConstElts = true;
5756 else if (In != Op.getOperand(SplatIdx))
5760 // for splat use " (select i1 splat_elt, all-ones, all-zeroes)"
5762 return DAG.getNode(ISD::SELECT, dl, VT, Op.getOperand(SplatIdx),
5763 DAG.getConstant(1, dl, VT),
5764 DAG.getConstant(0, dl, VT));
5766 // insert elements one by one
5770 MVT ImmVT = MVT::getIntegerVT(std::max((int)VT.getSizeInBits(), 8));
5771 Imm = DAG.getConstant(Immediate, dl, ImmVT);
5773 else if (HasConstElts)
5774 Imm = DAG.getConstant(0, dl, VT);
5776 Imm = DAG.getUNDEF(VT);
5777 if (Imm.getValueSizeInBits() == VT.getSizeInBits())
5778 DstVec = DAG.getBitcast(VT, Imm);
5780 SDValue ExtVec = DAG.getBitcast(MVT::v8i1, Imm);
5781 DstVec = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, ExtVec,
5782 DAG.getIntPtrConstant(0, dl));
5785 for (unsigned i = 0; i < NonConstIdx.size(); ++i) {
5786 unsigned InsertIdx = NonConstIdx[i];
5787 DstVec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, DstVec,
5788 Op.getOperand(InsertIdx),
5789 DAG.getIntPtrConstant(InsertIdx, dl));
5794 /// \brief Return true if \p N implements a horizontal binop and return the
5795 /// operands for the horizontal binop into V0 and V1.
5797 /// This is a helper function of LowerToHorizontalOp().
5798 /// This function checks that the build_vector \p N in input implements a
5799 /// horizontal operation. Parameter \p Opcode defines the kind of horizontal
5800 /// operation to match.
5801 /// For example, if \p Opcode is equal to ISD::ADD, then this function
5802 /// checks if \p N implements a horizontal arithmetic add; if instead \p Opcode
5803 /// is equal to ISD::SUB, then this function checks if this is a horizontal
5806 /// This function only analyzes elements of \p N whose indices are
5807 /// in range [BaseIdx, LastIdx).
5808 static bool isHorizontalBinOp(const BuildVectorSDNode *N, unsigned Opcode,
5810 unsigned BaseIdx, unsigned LastIdx,
5811 SDValue &V0, SDValue &V1) {
5812 EVT VT = N->getValueType(0);
5814 assert(BaseIdx * 2 <= LastIdx && "Invalid Indices in input!");
5815 assert(VT.isVector() && VT.getVectorNumElements() >= LastIdx &&
5816 "Invalid Vector in input!");
5818 bool IsCommutable = (Opcode == ISD::ADD || Opcode == ISD::FADD);
5819 bool CanFold = true;
5820 unsigned ExpectedVExtractIdx = BaseIdx;
5821 unsigned NumElts = LastIdx - BaseIdx;
5822 V0 = DAG.getUNDEF(VT);
5823 V1 = DAG.getUNDEF(VT);
5825 // Check if N implements a horizontal binop.
5826 for (unsigned i = 0, e = NumElts; i != e && CanFold; ++i) {
5827 SDValue Op = N->getOperand(i + BaseIdx);
5830 if (Op->getOpcode() == ISD::UNDEF) {
5831 // Update the expected vector extract index.
5832 if (i * 2 == NumElts)
5833 ExpectedVExtractIdx = BaseIdx;
5834 ExpectedVExtractIdx += 2;
5838 CanFold = Op->getOpcode() == Opcode && Op->hasOneUse();
5843 SDValue Op0 = Op.getOperand(0);
5844 SDValue Op1 = Op.getOperand(1);
5846 // Try to match the following pattern:
5847 // (BINOP (extract_vector_elt A, I), (extract_vector_elt A, I+1))
5848 CanFold = (Op0.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
5849 Op1.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
5850 Op0.getOperand(0) == Op1.getOperand(0) &&
5851 isa<ConstantSDNode>(Op0.getOperand(1)) &&
5852 isa<ConstantSDNode>(Op1.getOperand(1)));
5856 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
5857 unsigned I1 = cast<ConstantSDNode>(Op1.getOperand(1))->getZExtValue();
5859 if (i * 2 < NumElts) {
5860 if (V0.getOpcode() == ISD::UNDEF) {
5861 V0 = Op0.getOperand(0);
5862 if (V0.getValueType() != VT)
5866 if (V1.getOpcode() == ISD::UNDEF) {
5867 V1 = Op0.getOperand(0);
5868 if (V1.getValueType() != VT)
5871 if (i * 2 == NumElts)
5872 ExpectedVExtractIdx = BaseIdx;
5875 SDValue Expected = (i * 2 < NumElts) ? V0 : V1;
5876 if (I0 == ExpectedVExtractIdx)
5877 CanFold = I1 == I0 + 1 && Op0.getOperand(0) == Expected;
5878 else if (IsCommutable && I1 == ExpectedVExtractIdx) {
5879 // Try to match the following dag sequence:
5880 // (BINOP (extract_vector_elt A, I+1), (extract_vector_elt A, I))
5881 CanFold = I0 == I1 + 1 && Op1.getOperand(0) == Expected;
5885 ExpectedVExtractIdx += 2;
5891 /// \brief Emit a sequence of two 128-bit horizontal add/sub followed by
5892 /// a concat_vector.
5894 /// This is a helper function of LowerToHorizontalOp().
5895 /// This function expects two 256-bit vectors called V0 and V1.
5896 /// At first, each vector is split into two separate 128-bit vectors.
5897 /// Then, the resulting 128-bit vectors are used to implement two
5898 /// horizontal binary operations.
5900 /// The kind of horizontal binary operation is defined by \p X86Opcode.
5902 /// \p Mode specifies how the 128-bit parts of V0 and V1 are passed in input to
5903 /// the two new horizontal binop.
5904 /// When Mode is set, the first horizontal binop dag node would take as input
5905 /// the lower 128-bit of V0 and the upper 128-bit of V0. The second
5906 /// horizontal binop dag node would take as input the lower 128-bit of V1
5907 /// and the upper 128-bit of V1.
5909 /// HADD V0_LO, V0_HI
5910 /// HADD V1_LO, V1_HI
5912 /// Otherwise, the first horizontal binop dag node takes as input the lower
5913 /// 128-bit of V0 and the lower 128-bit of V1, and the second horizontal binop
5914 /// dag node takes the upper 128-bit of V0 and the upper 128-bit of V1.
5916 /// HADD V0_LO, V1_LO
5917 /// HADD V0_HI, V1_HI
5919 /// If \p isUndefLO is set, then the algorithm propagates UNDEF to the lower
5920 /// 128-bits of the result. If \p isUndefHI is set, then UNDEF is propagated to
5921 /// the upper 128-bits of the result.
5922 static SDValue ExpandHorizontalBinOp(const SDValue &V0, const SDValue &V1,
5923 SDLoc DL, SelectionDAG &DAG,
5924 unsigned X86Opcode, bool Mode,
5925 bool isUndefLO, bool isUndefHI) {
5926 EVT VT = V0.getValueType();
5927 assert(VT.is256BitVector() && VT == V1.getValueType() &&
5928 "Invalid nodes in input!");
5930 unsigned NumElts = VT.getVectorNumElements();
5931 SDValue V0_LO = Extract128BitVector(V0, 0, DAG, DL);
5932 SDValue V0_HI = Extract128BitVector(V0, NumElts/2, DAG, DL);
5933 SDValue V1_LO = Extract128BitVector(V1, 0, DAG, DL);
5934 SDValue V1_HI = Extract128BitVector(V1, NumElts/2, DAG, DL);
5935 EVT NewVT = V0_LO.getValueType();
5937 SDValue LO = DAG.getUNDEF(NewVT);
5938 SDValue HI = DAG.getUNDEF(NewVT);
5941 // Don't emit a horizontal binop if the result is expected to be UNDEF.
5942 if (!isUndefLO && V0->getOpcode() != ISD::UNDEF)
5943 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V0_HI);
5944 if (!isUndefHI && V1->getOpcode() != ISD::UNDEF)
5945 HI = DAG.getNode(X86Opcode, DL, NewVT, V1_LO, V1_HI);
5947 // Don't emit a horizontal binop if the result is expected to be UNDEF.
5948 if (!isUndefLO && (V0_LO->getOpcode() != ISD::UNDEF ||
5949 V1_LO->getOpcode() != ISD::UNDEF))
5950 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V1_LO);
5952 if (!isUndefHI && (V0_HI->getOpcode() != ISD::UNDEF ||
5953 V1_HI->getOpcode() != ISD::UNDEF))
5954 HI = DAG.getNode(X86Opcode, DL, NewVT, V0_HI, V1_HI);
5957 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LO, HI);
5960 /// Try to fold a build_vector that performs an 'addsub' to an X86ISD::ADDSUB
5962 static SDValue LowerToAddSub(const BuildVectorSDNode *BV,
5963 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
5964 MVT VT = BV->getSimpleValueType(0);
5965 if ((!Subtarget->hasSSE3() || (VT != MVT::v4f32 && VT != MVT::v2f64)) &&
5966 (!Subtarget->hasAVX() || (VT != MVT::v8f32 && VT != MVT::v4f64)))
5970 unsigned NumElts = VT.getVectorNumElements();
5971 SDValue InVec0 = DAG.getUNDEF(VT);
5972 SDValue InVec1 = DAG.getUNDEF(VT);
5974 assert((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v4f32 ||
5975 VT == MVT::v2f64) && "build_vector with an invalid type found!");
5977 // Odd-numbered elements in the input build vector are obtained from
5978 // adding two integer/float elements.
5979 // Even-numbered elements in the input build vector are obtained from
5980 // subtracting two integer/float elements.
5981 unsigned ExpectedOpcode = ISD::FSUB;
5982 unsigned NextExpectedOpcode = ISD::FADD;
5983 bool AddFound = false;
5984 bool SubFound = false;
5986 for (unsigned i = 0, e = NumElts; i != e; ++i) {
5987 SDValue Op = BV->getOperand(i);
5989 // Skip 'undef' values.
5990 unsigned Opcode = Op.getOpcode();
5991 if (Opcode == ISD::UNDEF) {
5992 std::swap(ExpectedOpcode, NextExpectedOpcode);
5996 // Early exit if we found an unexpected opcode.
5997 if (Opcode != ExpectedOpcode)
6000 SDValue Op0 = Op.getOperand(0);
6001 SDValue Op1 = Op.getOperand(1);
6003 // Try to match the following pattern:
6004 // (BINOP (extract_vector_elt A, i), (extract_vector_elt B, i))
6005 // Early exit if we cannot match that sequence.
6006 if (Op0.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
6007 Op1.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
6008 !isa<ConstantSDNode>(Op0.getOperand(1)) ||
6009 !isa<ConstantSDNode>(Op1.getOperand(1)) ||
6010 Op0.getOperand(1) != Op1.getOperand(1))
6013 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
6017 // We found a valid add/sub node. Update the information accordingly.
6023 // Update InVec0 and InVec1.
6024 if (InVec0.getOpcode() == ISD::UNDEF) {
6025 InVec0 = Op0.getOperand(0);
6026 if (InVec0.getSimpleValueType() != VT)
6029 if (InVec1.getOpcode() == ISD::UNDEF) {
6030 InVec1 = Op1.getOperand(0);
6031 if (InVec1.getSimpleValueType() != VT)
6035 // Make sure that operands in input to each add/sub node always
6036 // come from a same pair of vectors.
6037 if (InVec0 != Op0.getOperand(0)) {
6038 if (ExpectedOpcode == ISD::FSUB)
6041 // FADD is commutable. Try to commute the operands
6042 // and then test again.
6043 std::swap(Op0, Op1);
6044 if (InVec0 != Op0.getOperand(0))
6048 if (InVec1 != Op1.getOperand(0))
6051 // Update the pair of expected opcodes.
6052 std::swap(ExpectedOpcode, NextExpectedOpcode);
6055 // Don't try to fold this build_vector into an ADDSUB if the inputs are undef.
6056 if (AddFound && SubFound && InVec0.getOpcode() != ISD::UNDEF &&
6057 InVec1.getOpcode() != ISD::UNDEF)
6058 return DAG.getNode(X86ISD::ADDSUB, DL, VT, InVec0, InVec1);
6063 /// Lower BUILD_VECTOR to a horizontal add/sub operation if possible.
6064 static SDValue LowerToHorizontalOp(const BuildVectorSDNode *BV,
6065 const X86Subtarget *Subtarget,
6066 SelectionDAG &DAG) {
6067 MVT VT = BV->getSimpleValueType(0);
6068 unsigned NumElts = VT.getVectorNumElements();
6069 unsigned NumUndefsLO = 0;
6070 unsigned NumUndefsHI = 0;
6071 unsigned Half = NumElts/2;
6073 // Count the number of UNDEF operands in the build_vector in input.
6074 for (unsigned i = 0, e = Half; i != e; ++i)
6075 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
6078 for (unsigned i = Half, e = NumElts; i != e; ++i)
6079 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
6082 // Early exit if this is either a build_vector of all UNDEFs or all the
6083 // operands but one are UNDEF.
6084 if (NumUndefsLO + NumUndefsHI + 1 >= NumElts)
6088 SDValue InVec0, InVec1;
6089 if ((VT == MVT::v4f32 || VT == MVT::v2f64) && Subtarget->hasSSE3()) {
6090 // Try to match an SSE3 float HADD/HSUB.
6091 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
6092 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
6094 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
6095 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
6096 } else if ((VT == MVT::v4i32 || VT == MVT::v8i16) && Subtarget->hasSSSE3()) {
6097 // Try to match an SSSE3 integer HADD/HSUB.
6098 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
6099 return DAG.getNode(X86ISD::HADD, DL, VT, InVec0, InVec1);
6101 if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
6102 return DAG.getNode(X86ISD::HSUB, DL, VT, InVec0, InVec1);
6105 if (!Subtarget->hasAVX())
6108 if ((VT == MVT::v8f32 || VT == MVT::v4f64)) {
6109 // Try to match an AVX horizontal add/sub of packed single/double
6110 // precision floating point values from 256-bit vectors.
6111 SDValue InVec2, InVec3;
6112 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, Half, InVec0, InVec1) &&
6113 isHorizontalBinOp(BV, ISD::FADD, DAG, Half, NumElts, InVec2, InVec3) &&
6114 ((InVec0.getOpcode() == ISD::UNDEF ||
6115 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6116 ((InVec1.getOpcode() == ISD::UNDEF ||
6117 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6118 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
6120 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, Half, InVec0, InVec1) &&
6121 isHorizontalBinOp(BV, ISD::FSUB, DAG, Half, NumElts, InVec2, InVec3) &&
6122 ((InVec0.getOpcode() == ISD::UNDEF ||
6123 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6124 ((InVec1.getOpcode() == ISD::UNDEF ||
6125 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6126 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
6127 } else if (VT == MVT::v8i32 || VT == MVT::v16i16) {
6128 // Try to match an AVX2 horizontal add/sub of signed integers.
6129 SDValue InVec2, InVec3;
6131 bool CanFold = true;
6133 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, Half, InVec0, InVec1) &&
6134 isHorizontalBinOp(BV, ISD::ADD, DAG, Half, NumElts, InVec2, InVec3) &&
6135 ((InVec0.getOpcode() == ISD::UNDEF ||
6136 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6137 ((InVec1.getOpcode() == ISD::UNDEF ||
6138 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6139 X86Opcode = X86ISD::HADD;
6140 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, Half, InVec0, InVec1) &&
6141 isHorizontalBinOp(BV, ISD::SUB, DAG, Half, NumElts, InVec2, InVec3) &&
6142 ((InVec0.getOpcode() == ISD::UNDEF ||
6143 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6144 ((InVec1.getOpcode() == ISD::UNDEF ||
6145 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6146 X86Opcode = X86ISD::HSUB;
6151 // Fold this build_vector into a single horizontal add/sub.
6152 // Do this only if the target has AVX2.
6153 if (Subtarget->hasAVX2())
6154 return DAG.getNode(X86Opcode, DL, VT, InVec0, InVec1);
6156 // Do not try to expand this build_vector into a pair of horizontal
6157 // add/sub if we can emit a pair of scalar add/sub.
6158 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
6161 // Convert this build_vector into a pair of horizontal binop followed by
6163 bool isUndefLO = NumUndefsLO == Half;
6164 bool isUndefHI = NumUndefsHI == Half;
6165 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, false,
6166 isUndefLO, isUndefHI);
6170 if ((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v8i32 ||
6171 VT == MVT::v16i16) && Subtarget->hasAVX()) {
6173 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
6174 X86Opcode = X86ISD::HADD;
6175 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
6176 X86Opcode = X86ISD::HSUB;
6177 else if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
6178 X86Opcode = X86ISD::FHADD;
6179 else if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
6180 X86Opcode = X86ISD::FHSUB;
6184 // Don't try to expand this build_vector into a pair of horizontal add/sub
6185 // if we can simply emit a pair of scalar add/sub.
6186 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
6189 // Convert this build_vector into two horizontal add/sub followed by
6191 bool isUndefLO = NumUndefsLO == Half;
6192 bool isUndefHI = NumUndefsHI == Half;
6193 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, true,
6194 isUndefLO, isUndefHI);
6201 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
6204 MVT VT = Op.getSimpleValueType();
6205 MVT ExtVT = VT.getVectorElementType();
6206 unsigned NumElems = Op.getNumOperands();
6208 // Generate vectors for predicate vectors.
6209 if (VT.getVectorElementType() == MVT::i1 && Subtarget->hasAVX512())
6210 return LowerBUILD_VECTORvXi1(Op, DAG);
6212 // Vectors containing all zeros can be matched by pxor and xorps later
6213 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
6214 // Canonicalize this to <4 x i32> to 1) ensure the zero vectors are CSE'd
6215 // and 2) ensure that i64 scalars are eliminated on x86-32 hosts.
6216 if (VT == MVT::v4i32 || VT == MVT::v8i32 || VT == MVT::v16i32)
6219 return getZeroVector(VT, Subtarget, DAG, dl);
6222 // Vectors containing all ones can be matched by pcmpeqd on 128-bit width
6223 // vectors or broken into v4i32 operations on 256-bit vectors. AVX2 can use
6224 // vpcmpeqd on 256-bit vectors.
6225 if (Subtarget->hasSSE2() && ISD::isBuildVectorAllOnes(Op.getNode())) {
6226 if (VT == MVT::v4i32 || (VT == MVT::v8i32 && Subtarget->hasInt256()))
6229 if (!VT.is512BitVector())
6230 return getOnesVector(VT, Subtarget, DAG, dl);
6233 BuildVectorSDNode *BV = cast<BuildVectorSDNode>(Op.getNode());
6234 if (SDValue AddSub = LowerToAddSub(BV, Subtarget, DAG))
6236 if (SDValue HorizontalOp = LowerToHorizontalOp(BV, Subtarget, DAG))
6237 return HorizontalOp;
6238 if (SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG))
6241 unsigned EVTBits = ExtVT.getSizeInBits();
6243 unsigned NumZero = 0;
6244 unsigned NumNonZero = 0;
6245 unsigned NonZeros = 0;
6246 bool IsAllConstants = true;
6247 SmallSet<SDValue, 8> Values;
6248 for (unsigned i = 0; i < NumElems; ++i) {
6249 SDValue Elt = Op.getOperand(i);
6250 if (Elt.getOpcode() == ISD::UNDEF)
6253 if (Elt.getOpcode() != ISD::Constant &&
6254 Elt.getOpcode() != ISD::ConstantFP)
6255 IsAllConstants = false;
6256 if (X86::isZeroNode(Elt))
6259 NonZeros |= (1 << i);
6264 // All undef vector. Return an UNDEF. All zero vectors were handled above.
6265 if (NumNonZero == 0)
6266 return DAG.getUNDEF(VT);
6268 // Special case for single non-zero, non-undef, element.
6269 if (NumNonZero == 1) {
6270 unsigned Idx = countTrailingZeros(NonZeros);
6271 SDValue Item = Op.getOperand(Idx);
6273 // If this is an insertion of an i64 value on x86-32, and if the top bits of
6274 // the value are obviously zero, truncate the value to i32 and do the
6275 // insertion that way. Only do this if the value is non-constant or if the
6276 // value is a constant being inserted into element 0. It is cheaper to do
6277 // a constant pool load than it is to do a movd + shuffle.
6278 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
6279 (!IsAllConstants || Idx == 0)) {
6280 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
6282 assert(VT == MVT::v2i64 && "Expected an SSE value type!");
6283 MVT VecVT = MVT::v4i32;
6285 // Truncate the value (which may itself be a constant) to i32, and
6286 // convert it to a vector with movd (S2V+shuffle to zero extend).
6287 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
6288 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
6289 return DAG.getBitcast(VT, getShuffleVectorZeroOrUndef(
6290 Item, Idx * 2, true, Subtarget, DAG));
6294 // If we have a constant or non-constant insertion into the low element of
6295 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
6296 // the rest of the elements. This will be matched as movd/movq/movss/movsd
6297 // depending on what the source datatype is.
6300 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6302 if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
6303 (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
6304 if (VT.is512BitVector()) {
6305 SDValue ZeroVec = getZeroVector(VT, Subtarget, DAG, dl);
6306 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, ZeroVec,
6307 Item, DAG.getIntPtrConstant(0, dl));
6309 assert((VT.is128BitVector() || VT.is256BitVector()) &&
6310 "Expected an SSE value type!");
6311 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6312 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
6313 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6316 // We can't directly insert an i8 or i16 into a vector, so zero extend
6318 if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
6319 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
6320 if (VT.is256BitVector()) {
6321 if (Subtarget->hasAVX()) {
6322 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v8i32, Item);
6323 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6325 // Without AVX, we need to extend to a 128-bit vector and then
6326 // insert into the 256-bit vector.
6327 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
6328 SDValue ZeroVec = getZeroVector(MVT::v8i32, Subtarget, DAG, dl);
6329 Item = Insert128BitVector(ZeroVec, Item, 0, DAG, dl);
6332 assert(VT.is128BitVector() && "Expected an SSE value type!");
6333 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
6334 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6336 return DAG.getBitcast(VT, Item);
6340 // Is it a vector logical left shift?
6341 if (NumElems == 2 && Idx == 1 &&
6342 X86::isZeroNode(Op.getOperand(0)) &&
6343 !X86::isZeroNode(Op.getOperand(1))) {
6344 unsigned NumBits = VT.getSizeInBits();
6345 return getVShift(true, VT,
6346 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
6347 VT, Op.getOperand(1)),
6348 NumBits/2, DAG, *this, dl);
6351 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
6354 // Otherwise, if this is a vector with i32 or f32 elements, and the element
6355 // is a non-constant being inserted into an element other than the low one,
6356 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
6357 // movd/movss) to move this into the low element, then shuffle it into
6359 if (EVTBits == 32) {
6360 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6361 return getShuffleVectorZeroOrUndef(Item, Idx, NumZero > 0, Subtarget, DAG);
6365 // Splat is obviously ok. Let legalizer expand it to a shuffle.
6366 if (Values.size() == 1) {
6367 if (EVTBits == 32) {
6368 // Instead of a shuffle like this:
6369 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
6370 // Check if it's possible to issue this instead.
6371 // shuffle (vload ptr)), undef, <1, 1, 1, 1>
6372 unsigned Idx = countTrailingZeros(NonZeros);
6373 SDValue Item = Op.getOperand(Idx);
6374 if (Op.getNode()->isOnlyUserOf(Item.getNode()))
6375 return LowerAsSplatVectorLoad(Item, VT, dl, DAG);
6380 // A vector full of immediates; various special cases are already
6381 // handled, so this is best done with a single constant-pool load.
6385 // For AVX-length vectors, see if we can use a vector load to get all of the
6386 // elements, otherwise build the individual 128-bit pieces and use
6387 // shuffles to put them in place.
6388 if (VT.is256BitVector() || VT.is512BitVector()) {
6389 SmallVector<SDValue, 64> V(Op->op_begin(), Op->op_begin() + NumElems);
6391 // Check for a build vector of consecutive loads.
6392 if (SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG, false))
6395 EVT HVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems/2);
6397 // Build both the lower and upper subvector.
6398 SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
6399 makeArrayRef(&V[0], NumElems/2));
6400 SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
6401 makeArrayRef(&V[NumElems / 2], NumElems/2));
6403 // Recreate the wider vector with the lower and upper part.
6404 if (VT.is256BitVector())
6405 return Concat128BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
6406 return Concat256BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
6409 // Let legalizer expand 2-wide build_vectors.
6410 if (EVTBits == 64) {
6411 if (NumNonZero == 1) {
6412 // One half is zero or undef.
6413 unsigned Idx = countTrailingZeros(NonZeros);
6414 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
6415 Op.getOperand(Idx));
6416 return getShuffleVectorZeroOrUndef(V2, Idx, true, Subtarget, DAG);
6421 // If element VT is < 32 bits, convert it to inserts into a zero vector.
6422 if (EVTBits == 8 && NumElems == 16)
6423 if (SDValue V = LowerBuildVectorv16i8(Op, NonZeros, NumNonZero, NumZero,
6424 DAG, Subtarget, *this))
6427 if (EVTBits == 16 && NumElems == 8)
6428 if (SDValue V = LowerBuildVectorv8i16(Op, NonZeros, NumNonZero, NumZero,
6429 DAG, Subtarget, *this))
6432 // If element VT is == 32 bits and has 4 elems, try to generate an INSERTPS
6433 if (EVTBits == 32 && NumElems == 4)
6434 if (SDValue V = LowerBuildVectorv4x32(Op, DAG, Subtarget, *this))
6437 // If element VT is == 32 bits, turn it into a number of shuffles.
6438 SmallVector<SDValue, 8> V(NumElems);
6439 if (NumElems == 4 && NumZero > 0) {
6440 for (unsigned i = 0; i < 4; ++i) {
6441 bool isZero = !(NonZeros & (1 << i));
6443 V[i] = getZeroVector(VT, Subtarget, DAG, dl);
6445 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
6448 for (unsigned i = 0; i < 2; ++i) {
6449 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
6452 V[i] = V[i*2]; // Must be a zero vector.
6455 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
6458 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
6461 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
6466 bool Reverse1 = (NonZeros & 0x3) == 2;
6467 bool Reverse2 = ((NonZeros & (0x3 << 2)) >> 2) == 2;
6471 static_cast<int>(Reverse2 ? NumElems+1 : NumElems),
6472 static_cast<int>(Reverse2 ? NumElems : NumElems+1)
6474 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
6477 if (Values.size() > 1 && VT.is128BitVector()) {
6478 // Check for a build vector of consecutive loads.
6479 for (unsigned i = 0; i < NumElems; ++i)
6480 V[i] = Op.getOperand(i);
6482 // Check for elements which are consecutive loads.
6483 if (SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG, false))
6486 // Check for a build vector from mostly shuffle plus few inserting.
6487 if (SDValue Sh = buildFromShuffleMostly(Op, DAG))
6490 // For SSE 4.1, use insertps to put the high elements into the low element.
6491 if (Subtarget->hasSSE41()) {
6493 if (Op.getOperand(0).getOpcode() != ISD::UNDEF)
6494 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0));
6496 Result = DAG.getUNDEF(VT);
6498 for (unsigned i = 1; i < NumElems; ++i) {
6499 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue;
6500 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result,
6501 Op.getOperand(i), DAG.getIntPtrConstant(i, dl));
6506 // Otherwise, expand into a number of unpckl*, start by extending each of
6507 // our (non-undef) elements to the full vector width with the element in the
6508 // bottom slot of the vector (which generates no code for SSE).
6509 for (unsigned i = 0; i < NumElems; ++i) {
6510 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
6511 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
6513 V[i] = DAG.getUNDEF(VT);
6516 // Next, we iteratively mix elements, e.g. for v4f32:
6517 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
6518 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
6519 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
6520 unsigned EltStride = NumElems >> 1;
6521 while (EltStride != 0) {
6522 for (unsigned i = 0; i < EltStride; ++i) {
6523 // If V[i+EltStride] is undef and this is the first round of mixing,
6524 // then it is safe to just drop this shuffle: V[i] is already in the
6525 // right place, the one element (since it's the first round) being
6526 // inserted as undef can be dropped. This isn't safe for successive
6527 // rounds because they will permute elements within both vectors.
6528 if (V[i+EltStride].getOpcode() == ISD::UNDEF &&
6529 EltStride == NumElems/2)
6532 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]);
6541 // 256-bit AVX can use the vinsertf128 instruction
6542 // to create 256-bit vectors from two other 128-bit ones.
6543 static SDValue LowerAVXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
6545 MVT ResVT = Op.getSimpleValueType();
6547 assert((ResVT.is256BitVector() ||
6548 ResVT.is512BitVector()) && "Value type must be 256-/512-bit wide");
6550 SDValue V1 = Op.getOperand(0);
6551 SDValue V2 = Op.getOperand(1);
6552 unsigned NumElems = ResVT.getVectorNumElements();
6553 if (ResVT.is256BitVector())
6554 return Concat128BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
6556 if (Op.getNumOperands() == 4) {
6557 MVT HalfVT = MVT::getVectorVT(ResVT.getVectorElementType(),
6558 ResVT.getVectorNumElements()/2);
6559 SDValue V3 = Op.getOperand(2);
6560 SDValue V4 = Op.getOperand(3);
6561 return Concat256BitVectors(Concat128BitVectors(V1, V2, HalfVT, NumElems/2, DAG, dl),
6562 Concat128BitVectors(V3, V4, HalfVT, NumElems/2, DAG, dl), ResVT, NumElems, DAG, dl);
6564 return Concat256BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
6567 static SDValue LowerCONCAT_VECTORSvXi1(SDValue Op,
6568 const X86Subtarget *Subtarget,
6569 SelectionDAG & DAG) {
6571 MVT ResVT = Op.getSimpleValueType();
6572 unsigned NumOfOperands = Op.getNumOperands();
6574 assert(isPowerOf2_32(NumOfOperands) &&
6575 "Unexpected number of operands in CONCAT_VECTORS");
6577 SDValue Undef = DAG.getUNDEF(ResVT);
6578 if (NumOfOperands > 2) {
6579 // Specialize the cases when all, or all but one, of the operands are undef.
6580 unsigned NumOfDefinedOps = 0;
6582 for (unsigned i = 0; i < NumOfOperands; i++)
6583 if (!Op.getOperand(i).isUndef()) {
6587 if (NumOfDefinedOps == 0)
6589 if (NumOfDefinedOps == 1) {
6590 unsigned SubVecNumElts =
6591 Op.getOperand(OpIdx).getValueType().getVectorNumElements();
6592 SDValue IdxVal = DAG.getIntPtrConstant(SubVecNumElts * OpIdx, dl);
6593 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, Undef,
6594 Op.getOperand(OpIdx), IdxVal);
6597 MVT HalfVT = MVT::getVectorVT(ResVT.getVectorElementType(),
6598 ResVT.getVectorNumElements()/2);
6599 SmallVector<SDValue, 2> Ops;
6600 for (unsigned i = 0; i < NumOfOperands/2; i++)
6601 Ops.push_back(Op.getOperand(i));
6602 SDValue Lo = DAG.getNode(ISD::CONCAT_VECTORS, dl, HalfVT, Ops);
6604 for (unsigned i = NumOfOperands/2; i < NumOfOperands; i++)
6605 Ops.push_back(Op.getOperand(i));
6606 SDValue Hi = DAG.getNode(ISD::CONCAT_VECTORS, dl, HalfVT, Ops);
6607 return DAG.getNode(ISD::CONCAT_VECTORS, dl, ResVT, Lo, Hi);
6611 SDValue V1 = Op.getOperand(0);
6612 SDValue V2 = Op.getOperand(1);
6613 unsigned NumElems = ResVT.getVectorNumElements();
6614 assert(V1.getValueType() == V2.getValueType() &&
6615 V1.getValueType().getVectorNumElements() == NumElems/2 &&
6616 "Unexpected operands in CONCAT_VECTORS");
6618 if (ResVT.getSizeInBits() >= 16)
6619 return Op; // The operation is legal with KUNPCK
6621 bool IsZeroV1 = ISD::isBuildVectorAllZeros(V1.getNode());
6622 bool IsZeroV2 = ISD::isBuildVectorAllZeros(V2.getNode());
6623 SDValue ZeroVec = getZeroVector(ResVT, Subtarget, DAG, dl);
6624 if (IsZeroV1 && IsZeroV2)
6627 SDValue ZeroIdx = DAG.getIntPtrConstant(0, dl);
6629 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, Undef, V1, ZeroIdx);
6631 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, ZeroVec, V1, ZeroIdx);
6633 SDValue IdxVal = DAG.getIntPtrConstant(NumElems/2, dl);
6635 V2 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, Undef, V2, IdxVal);
6638 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, ZeroVec, V2, IdxVal);
6640 V1 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, Undef, V1, ZeroIdx);
6641 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, V1, V2, IdxVal);
6644 static SDValue LowerCONCAT_VECTORS(SDValue Op,
6645 const X86Subtarget *Subtarget,
6646 SelectionDAG &DAG) {
6647 MVT VT = Op.getSimpleValueType();
6648 if (VT.getVectorElementType() == MVT::i1)
6649 return LowerCONCAT_VECTORSvXi1(Op, Subtarget, DAG);
6651 assert((VT.is256BitVector() && Op.getNumOperands() == 2) ||
6652 (VT.is512BitVector() && (Op.getNumOperands() == 2 ||
6653 Op.getNumOperands() == 4)));
6655 // AVX can use the vinsertf128 instruction to create 256-bit vectors
6656 // from two other 128-bit ones.
6658 // 512-bit vector may contain 2 256-bit vectors or 4 128-bit vectors
6659 return LowerAVXCONCAT_VECTORS(Op, DAG);
6662 //===----------------------------------------------------------------------===//
6663 // Vector shuffle lowering
6665 // This is an experimental code path for lowering vector shuffles on x86. It is
6666 // designed to handle arbitrary vector shuffles and blends, gracefully
6667 // degrading performance as necessary. It works hard to recognize idiomatic
6668 // shuffles and lower them to optimal instruction patterns without leaving
6669 // a framework that allows reasonably efficient handling of all vector shuffle
6671 //===----------------------------------------------------------------------===//
6673 /// \brief Tiny helper function to identify a no-op mask.
6675 /// This is a somewhat boring predicate function. It checks whether the mask
6676 /// array input, which is assumed to be a single-input shuffle mask of the kind
6677 /// used by the X86 shuffle instructions (not a fully general
6678 /// ShuffleVectorSDNode mask) requires any shuffles to occur. Both undef and an
6679 /// in-place shuffle are 'no-op's.
6680 static bool isNoopShuffleMask(ArrayRef<int> Mask) {
6681 for (int i = 0, Size = Mask.size(); i < Size; ++i)
6682 if (Mask[i] != -1 && Mask[i] != i)
6687 /// \brief Helper function to classify a mask as a single-input mask.
6689 /// This isn't a generic single-input test because in the vector shuffle
6690 /// lowering we canonicalize single inputs to be the first input operand. This
6691 /// means we can more quickly test for a single input by only checking whether
6692 /// an input from the second operand exists. We also assume that the size of
6693 /// mask corresponds to the size of the input vectors which isn't true in the
6694 /// fully general case.
6695 static bool isSingleInputShuffleMask(ArrayRef<int> Mask) {
6697 if (M >= (int)Mask.size())
6702 /// \brief Test whether there are elements crossing 128-bit lanes in this
6705 /// X86 divides up its shuffles into in-lane and cross-lane shuffle operations
6706 /// and we routinely test for these.
6707 static bool is128BitLaneCrossingShuffleMask(MVT VT, ArrayRef<int> Mask) {
6708 int LaneSize = 128 / VT.getScalarSizeInBits();
6709 int Size = Mask.size();
6710 for (int i = 0; i < Size; ++i)
6711 if (Mask[i] >= 0 && (Mask[i] % Size) / LaneSize != i / LaneSize)
6716 /// \brief Test whether a shuffle mask is equivalent within each 128-bit lane.
6718 /// This checks a shuffle mask to see if it is performing the same
6719 /// 128-bit lane-relative shuffle in each 128-bit lane. This trivially implies
6720 /// that it is also not lane-crossing. It may however involve a blend from the
6721 /// same lane of a second vector.
6723 /// The specific repeated shuffle mask is populated in \p RepeatedMask, as it is
6724 /// non-trivial to compute in the face of undef lanes. The representation is
6725 /// *not* suitable for use with existing 128-bit shuffles as it will contain
6726 /// entries from both V1 and V2 inputs to the wider mask.
6728 is128BitLaneRepeatedShuffleMask(MVT VT, ArrayRef<int> Mask,
6729 SmallVectorImpl<int> &RepeatedMask) {
6730 int LaneSize = 128 / VT.getScalarSizeInBits();
6731 RepeatedMask.resize(LaneSize, -1);
6732 int Size = Mask.size();
6733 for (int i = 0; i < Size; ++i) {
6736 if ((Mask[i] % Size) / LaneSize != i / LaneSize)
6737 // This entry crosses lanes, so there is no way to model this shuffle.
6740 // Ok, handle the in-lane shuffles by detecting if and when they repeat.
6741 if (RepeatedMask[i % LaneSize] == -1)
6742 // This is the first non-undef entry in this slot of a 128-bit lane.
6743 RepeatedMask[i % LaneSize] =
6744 Mask[i] < Size ? Mask[i] % LaneSize : Mask[i] % LaneSize + Size;
6745 else if (RepeatedMask[i % LaneSize] + (i / LaneSize) * LaneSize != Mask[i])
6746 // Found a mismatch with the repeated mask.
6752 /// \brief Checks whether a shuffle mask is equivalent to an explicit list of
6755 /// This is a fast way to test a shuffle mask against a fixed pattern:
6757 /// if (isShuffleEquivalent(Mask, 3, 2, {1, 0})) { ... }
6759 /// It returns true if the mask is exactly as wide as the argument list, and
6760 /// each element of the mask is either -1 (signifying undef) or the value given
6761 /// in the argument.
6762 static bool isShuffleEquivalent(SDValue V1, SDValue V2, ArrayRef<int> Mask,
6763 ArrayRef<int> ExpectedMask) {
6764 if (Mask.size() != ExpectedMask.size())
6767 int Size = Mask.size();
6769 // If the values are build vectors, we can look through them to find
6770 // equivalent inputs that make the shuffles equivalent.
6771 auto *BV1 = dyn_cast<BuildVectorSDNode>(V1);
6772 auto *BV2 = dyn_cast<BuildVectorSDNode>(V2);
6774 for (int i = 0; i < Size; ++i)
6775 if (Mask[i] != -1 && Mask[i] != ExpectedMask[i]) {
6776 auto *MaskBV = Mask[i] < Size ? BV1 : BV2;
6777 auto *ExpectedBV = ExpectedMask[i] < Size ? BV1 : BV2;
6778 if (!MaskBV || !ExpectedBV ||
6779 MaskBV->getOperand(Mask[i] % Size) !=
6780 ExpectedBV->getOperand(ExpectedMask[i] % Size))
6787 /// \brief Get a 4-lane 8-bit shuffle immediate for a mask.
6789 /// This helper function produces an 8-bit shuffle immediate corresponding to
6790 /// the ubiquitous shuffle encoding scheme used in x86 instructions for
6791 /// shuffling 4 lanes. It can be used with most of the PSHUF instructions for
6794 /// NB: We rely heavily on "undef" masks preserving the input lane.
6795 static SDValue getV4X86ShuffleImm8ForMask(ArrayRef<int> Mask, SDLoc DL,
6796 SelectionDAG &DAG) {
6797 assert(Mask.size() == 4 && "Only 4-lane shuffle masks");
6798 assert(Mask[0] >= -1 && Mask[0] < 4 && "Out of bound mask element!");
6799 assert(Mask[1] >= -1 && Mask[1] < 4 && "Out of bound mask element!");
6800 assert(Mask[2] >= -1 && Mask[2] < 4 && "Out of bound mask element!");
6801 assert(Mask[3] >= -1 && Mask[3] < 4 && "Out of bound mask element!");
6804 Imm |= (Mask[0] == -1 ? 0 : Mask[0]) << 0;
6805 Imm |= (Mask[1] == -1 ? 1 : Mask[1]) << 2;
6806 Imm |= (Mask[2] == -1 ? 2 : Mask[2]) << 4;
6807 Imm |= (Mask[3] == -1 ? 3 : Mask[3]) << 6;
6808 return DAG.getConstant(Imm, DL, MVT::i8);
6811 /// \brief Compute whether each element of a shuffle is zeroable.
6813 /// A "zeroable" vector shuffle element is one which can be lowered to zero.
6814 /// Either it is an undef element in the shuffle mask, the element of the input
6815 /// referenced is undef, or the element of the input referenced is known to be
6816 /// zero. Many x86 shuffles can zero lanes cheaply and we often want to handle
6817 /// as many lanes with this technique as possible to simplify the remaining
6819 static SmallBitVector computeZeroableShuffleElements(ArrayRef<int> Mask,
6820 SDValue V1, SDValue V2) {
6821 SmallBitVector Zeroable(Mask.size(), false);
6823 while (V1.getOpcode() == ISD::BITCAST)
6824 V1 = V1->getOperand(0);
6825 while (V2.getOpcode() == ISD::BITCAST)
6826 V2 = V2->getOperand(0);
6828 bool V1IsZero = ISD::isBuildVectorAllZeros(V1.getNode());
6829 bool V2IsZero = ISD::isBuildVectorAllZeros(V2.getNode());
6831 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6833 // Handle the easy cases.
6834 if (M < 0 || (M >= 0 && M < Size && V1IsZero) || (M >= Size && V2IsZero)) {
6839 // If this is an index into a build_vector node (which has the same number
6840 // of elements), dig out the input value and use it.
6841 SDValue V = M < Size ? V1 : V2;
6842 if (V.getOpcode() != ISD::BUILD_VECTOR || Size != (int)V.getNumOperands())
6845 SDValue Input = V.getOperand(M % Size);
6846 // The UNDEF opcode check really should be dead code here, but not quite
6847 // worth asserting on (it isn't invalid, just unexpected).
6848 if (Input.getOpcode() == ISD::UNDEF || X86::isZeroNode(Input))
6855 // X86 has dedicated unpack instructions that can handle specific blend
6856 // operations: UNPCKH and UNPCKL.
6857 static SDValue lowerVectorShuffleWithUNPCK(SDLoc DL, MVT VT, ArrayRef<int> Mask,
6858 SDValue V1, SDValue V2,
6859 SelectionDAG &DAG) {
6860 int NumElts = VT.getVectorNumElements();
6861 int NumEltsInLane = 128 / VT.getScalarSizeInBits();
6862 SmallVector<int, 8> Unpckl;
6863 SmallVector<int, 8> Unpckh;
6865 for (int i = 0; i < NumElts; ++i) {
6866 unsigned LaneStart = (i / NumEltsInLane) * NumEltsInLane;
6867 int LoPos = (i % NumEltsInLane) / 2 + LaneStart + NumElts * (i % 2);
6868 int HiPos = LoPos + NumEltsInLane / 2;
6869 Unpckl.push_back(LoPos);
6870 Unpckh.push_back(HiPos);
6873 if (isShuffleEquivalent(V1, V2, Mask, Unpckl))
6874 return DAG.getNode(X86ISD::UNPCKL, DL, VT, V1, V2);
6875 if (isShuffleEquivalent(V1, V2, Mask, Unpckh))
6876 return DAG.getNode(X86ISD::UNPCKH, DL, VT, V1, V2);
6878 // Commute and try again.
6879 ShuffleVectorSDNode::commuteMask(Unpckl);
6880 if (isShuffleEquivalent(V1, V2, Mask, Unpckl))
6881 return DAG.getNode(X86ISD::UNPCKL, DL, VT, V2, V1);
6883 ShuffleVectorSDNode::commuteMask(Unpckh);
6884 if (isShuffleEquivalent(V1, V2, Mask, Unpckh))
6885 return DAG.getNode(X86ISD::UNPCKH, DL, VT, V2, V1);
6890 /// \brief Try to emit a bitmask instruction for a shuffle.
6892 /// This handles cases where we can model a blend exactly as a bitmask due to
6893 /// one of the inputs being zeroable.
6894 static SDValue lowerVectorShuffleAsBitMask(SDLoc DL, MVT VT, SDValue V1,
6895 SDValue V2, ArrayRef<int> Mask,
6896 SelectionDAG &DAG) {
6897 MVT EltVT = VT.getVectorElementType();
6898 int NumEltBits = EltVT.getSizeInBits();
6899 MVT IntEltVT = MVT::getIntegerVT(NumEltBits);
6900 SDValue Zero = DAG.getConstant(0, DL, IntEltVT);
6901 SDValue AllOnes = DAG.getConstant(APInt::getAllOnesValue(NumEltBits), DL,
6903 if (EltVT.isFloatingPoint()) {
6904 Zero = DAG.getBitcast(EltVT, Zero);
6905 AllOnes = DAG.getBitcast(EltVT, AllOnes);
6907 SmallVector<SDValue, 16> VMaskOps(Mask.size(), Zero);
6908 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
6910 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6913 if (Mask[i] % Size != i)
6914 return SDValue(); // Not a blend.
6916 V = Mask[i] < Size ? V1 : V2;
6917 else if (V != (Mask[i] < Size ? V1 : V2))
6918 return SDValue(); // Can only let one input through the mask.
6920 VMaskOps[i] = AllOnes;
6923 return SDValue(); // No non-zeroable elements!
6925 SDValue VMask = DAG.getNode(ISD::BUILD_VECTOR, DL, VT, VMaskOps);
6926 V = DAG.getNode(VT.isFloatingPoint()
6927 ? (unsigned) X86ISD::FAND : (unsigned) ISD::AND,
6932 /// \brief Try to emit a blend instruction for a shuffle using bit math.
6934 /// This is used as a fallback approach when first class blend instructions are
6935 /// unavailable. Currently it is only suitable for integer vectors, but could
6936 /// be generalized for floating point vectors if desirable.
6937 static SDValue lowerVectorShuffleAsBitBlend(SDLoc DL, MVT VT, SDValue V1,
6938 SDValue V2, ArrayRef<int> Mask,
6939 SelectionDAG &DAG) {
6940 assert(VT.isInteger() && "Only supports integer vector types!");
6941 MVT EltVT = VT.getVectorElementType();
6942 int NumEltBits = EltVT.getSizeInBits();
6943 SDValue Zero = DAG.getConstant(0, DL, EltVT);
6944 SDValue AllOnes = DAG.getConstant(APInt::getAllOnesValue(NumEltBits), DL,
6946 SmallVector<SDValue, 16> MaskOps;
6947 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6948 if (Mask[i] != -1 && Mask[i] != i && Mask[i] != i + Size)
6949 return SDValue(); // Shuffled input!
6950 MaskOps.push_back(Mask[i] < Size ? AllOnes : Zero);
6953 SDValue V1Mask = DAG.getNode(ISD::BUILD_VECTOR, DL, VT, MaskOps);
6954 V1 = DAG.getNode(ISD::AND, DL, VT, V1, V1Mask);
6955 // We have to cast V2 around.
6956 MVT MaskVT = MVT::getVectorVT(MVT::i64, VT.getSizeInBits() / 64);
6957 V2 = DAG.getBitcast(VT, DAG.getNode(X86ISD::ANDNP, DL, MaskVT,
6958 DAG.getBitcast(MaskVT, V1Mask),
6959 DAG.getBitcast(MaskVT, V2)));
6960 return DAG.getNode(ISD::OR, DL, VT, V1, V2);
6963 /// \brief Try to emit a blend instruction for a shuffle.
6965 /// This doesn't do any checks for the availability of instructions for blending
6966 /// these values. It relies on the availability of the X86ISD::BLENDI pattern to
6967 /// be matched in the backend with the type given. What it does check for is
6968 /// that the shuffle mask is a blend, or convertible into a blend with zero.
6969 static SDValue lowerVectorShuffleAsBlend(SDLoc DL, MVT VT, SDValue V1,
6970 SDValue V2, ArrayRef<int> Original,
6971 const X86Subtarget *Subtarget,
6972 SelectionDAG &DAG) {
6973 bool V1IsZero = ISD::isBuildVectorAllZeros(V1.getNode());
6974 bool V2IsZero = ISD::isBuildVectorAllZeros(V2.getNode());
6975 SmallVector<int, 8> Mask(Original.begin(), Original.end());
6976 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
6977 bool ForceV1Zero = false, ForceV2Zero = false;
6979 // Attempt to generate the binary blend mask. If an input is zero then
6980 // we can use any lane.
6981 // TODO: generalize the zero matching to any scalar like isShuffleEquivalent.
6982 unsigned BlendMask = 0;
6983 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6989 if (M == i + Size) {
6990 BlendMask |= 1u << i;
7001 BlendMask |= 1u << i;
7006 return SDValue(); // Shuffled input!
7009 // Create a REAL zero vector - ISD::isBuildVectorAllZeros allows UNDEFs.
7011 V1 = getZeroVector(VT, Subtarget, DAG, DL);
7013 V2 = getZeroVector(VT, Subtarget, DAG, DL);
7015 auto ScaleBlendMask = [](unsigned BlendMask, int Size, int Scale) {
7016 unsigned ScaledMask = 0;
7017 for (int i = 0; i != Size; ++i)
7018 if (BlendMask & (1u << i))
7019 for (int j = 0; j != Scale; ++j)
7020 ScaledMask |= 1u << (i * Scale + j);
7024 switch (VT.SimpleTy) {
7029 return DAG.getNode(X86ISD::BLENDI, DL, VT, V1, V2,
7030 DAG.getConstant(BlendMask, DL, MVT::i8));
7034 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
7038 // If we have AVX2 it is faster to use VPBLENDD when the shuffle fits into
7039 // that instruction.
7040 if (Subtarget->hasAVX2()) {
7041 // Scale the blend by the number of 32-bit dwords per element.
7042 int Scale = VT.getScalarSizeInBits() / 32;
7043 BlendMask = ScaleBlendMask(BlendMask, Mask.size(), Scale);
7044 MVT BlendVT = VT.getSizeInBits() > 128 ? MVT::v8i32 : MVT::v4i32;
7045 V1 = DAG.getBitcast(BlendVT, V1);
7046 V2 = DAG.getBitcast(BlendVT, V2);
7047 return DAG.getBitcast(
7048 VT, DAG.getNode(X86ISD::BLENDI, DL, BlendVT, V1, V2,
7049 DAG.getConstant(BlendMask, DL, MVT::i8)));
7053 // For integer shuffles we need to expand the mask and cast the inputs to
7054 // v8i16s prior to blending.
7055 int Scale = 8 / VT.getVectorNumElements();
7056 BlendMask = ScaleBlendMask(BlendMask, Mask.size(), Scale);
7057 V1 = DAG.getBitcast(MVT::v8i16, V1);
7058 V2 = DAG.getBitcast(MVT::v8i16, V2);
7059 return DAG.getBitcast(VT,
7060 DAG.getNode(X86ISD::BLENDI, DL, MVT::v8i16, V1, V2,
7061 DAG.getConstant(BlendMask, DL, MVT::i8)));
7065 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
7066 SmallVector<int, 8> RepeatedMask;
7067 if (is128BitLaneRepeatedShuffleMask(MVT::v16i16, Mask, RepeatedMask)) {
7068 // We can lower these with PBLENDW which is mirrored across 128-bit lanes.
7069 assert(RepeatedMask.size() == 8 && "Repeated mask size doesn't match!");
7071 for (int i = 0; i < 8; ++i)
7072 if (RepeatedMask[i] >= 16)
7073 BlendMask |= 1u << i;
7074 return DAG.getNode(X86ISD::BLENDI, DL, MVT::v16i16, V1, V2,
7075 DAG.getConstant(BlendMask, DL, MVT::i8));
7081 assert((VT.is128BitVector() || Subtarget->hasAVX2()) &&
7082 "256-bit byte-blends require AVX2 support!");
7084 // Attempt to lower to a bitmask if we can. VPAND is faster than VPBLENDVB.
7085 if (SDValue Masked = lowerVectorShuffleAsBitMask(DL, VT, V1, V2, Mask, DAG))
7088 // Scale the blend by the number of bytes per element.
7089 int Scale = VT.getScalarSizeInBits() / 8;
7091 // This form of blend is always done on bytes. Compute the byte vector
7093 MVT BlendVT = MVT::getVectorVT(MVT::i8, VT.getSizeInBits() / 8);
7095 // Compute the VSELECT mask. Note that VSELECT is really confusing in the
7096 // mix of LLVM's code generator and the x86 backend. We tell the code
7097 // generator that boolean values in the elements of an x86 vector register
7098 // are -1 for true and 0 for false. We then use the LLVM semantics of 'true'
7099 // mapping a select to operand #1, and 'false' mapping to operand #2. The
7100 // reality in x86 is that vector masks (pre-AVX-512) use only the high bit
7101 // of the element (the remaining are ignored) and 0 in that high bit would
7102 // mean operand #1 while 1 in the high bit would mean operand #2. So while
7103 // the LLVM model for boolean values in vector elements gets the relevant
7104 // bit set, it is set backwards and over constrained relative to x86's
7106 SmallVector<SDValue, 32> VSELECTMask;
7107 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7108 for (int j = 0; j < Scale; ++j)
7109 VSELECTMask.push_back(
7110 Mask[i] < 0 ? DAG.getUNDEF(MVT::i8)
7111 : DAG.getConstant(Mask[i] < Size ? -1 : 0, DL,
7114 V1 = DAG.getBitcast(BlendVT, V1);
7115 V2 = DAG.getBitcast(BlendVT, V2);
7116 return DAG.getBitcast(VT, DAG.getNode(ISD::VSELECT, DL, BlendVT,
7117 DAG.getNode(ISD::BUILD_VECTOR, DL,
7118 BlendVT, VSELECTMask),
7123 llvm_unreachable("Not a supported integer vector type!");
7127 /// \brief Try to lower as a blend of elements from two inputs followed by
7128 /// a single-input permutation.
7130 /// This matches the pattern where we can blend elements from two inputs and
7131 /// then reduce the shuffle to a single-input permutation.
7132 static SDValue lowerVectorShuffleAsBlendAndPermute(SDLoc DL, MVT VT, SDValue V1,
7135 SelectionDAG &DAG) {
7136 // We build up the blend mask while checking whether a blend is a viable way
7137 // to reduce the shuffle.
7138 SmallVector<int, 32> BlendMask(Mask.size(), -1);
7139 SmallVector<int, 32> PermuteMask(Mask.size(), -1);
7141 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
7145 assert(Mask[i] < Size * 2 && "Shuffle input is out of bounds.");
7147 if (BlendMask[Mask[i] % Size] == -1)
7148 BlendMask[Mask[i] % Size] = Mask[i];
7149 else if (BlendMask[Mask[i] % Size] != Mask[i])
7150 return SDValue(); // Can't blend in the needed input!
7152 PermuteMask[i] = Mask[i] % Size;
7155 SDValue V = DAG.getVectorShuffle(VT, DL, V1, V2, BlendMask);
7156 return DAG.getVectorShuffle(VT, DL, V, DAG.getUNDEF(VT), PermuteMask);
7159 /// \brief Generic routine to decompose a shuffle and blend into indepndent
7160 /// blends and permutes.
7162 /// This matches the extremely common pattern for handling combined
7163 /// shuffle+blend operations on newer X86 ISAs where we have very fast blend
7164 /// operations. It will try to pick the best arrangement of shuffles and
7166 static SDValue lowerVectorShuffleAsDecomposedShuffleBlend(SDLoc DL, MVT VT,
7170 SelectionDAG &DAG) {
7171 // Shuffle the input elements into the desired positions in V1 and V2 and
7172 // blend them together.
7173 SmallVector<int, 32> V1Mask(Mask.size(), -1);
7174 SmallVector<int, 32> V2Mask(Mask.size(), -1);
7175 SmallVector<int, 32> BlendMask(Mask.size(), -1);
7176 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7177 if (Mask[i] >= 0 && Mask[i] < Size) {
7178 V1Mask[i] = Mask[i];
7180 } else if (Mask[i] >= Size) {
7181 V2Mask[i] = Mask[i] - Size;
7182 BlendMask[i] = i + Size;
7185 // Try to lower with the simpler initial blend strategy unless one of the
7186 // input shuffles would be a no-op. We prefer to shuffle inputs as the
7187 // shuffle may be able to fold with a load or other benefit. However, when
7188 // we'll have to do 2x as many shuffles in order to achieve this, blending
7189 // first is a better strategy.
7190 if (!isNoopShuffleMask(V1Mask) && !isNoopShuffleMask(V2Mask))
7191 if (SDValue BlendPerm =
7192 lowerVectorShuffleAsBlendAndPermute(DL, VT, V1, V2, Mask, DAG))
7195 V1 = DAG.getVectorShuffle(VT, DL, V1, DAG.getUNDEF(VT), V1Mask);
7196 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Mask);
7197 return DAG.getVectorShuffle(VT, DL, V1, V2, BlendMask);
7200 /// \brief Try to lower a vector shuffle as a byte rotation.
7202 /// SSSE3 has a generic PALIGNR instruction in x86 that will do an arbitrary
7203 /// byte-rotation of the concatenation of two vectors; pre-SSSE3 can use
7204 /// a PSRLDQ/PSLLDQ/POR pattern to get a similar effect. This routine will
7205 /// try to generically lower a vector shuffle through such an pattern. It
7206 /// does not check for the profitability of lowering either as PALIGNR or
7207 /// PSRLDQ/PSLLDQ/POR, only whether the mask is valid to lower in that form.
7208 /// This matches shuffle vectors that look like:
7210 /// v8i16 [11, 12, 13, 14, 15, 0, 1, 2]
7212 /// Essentially it concatenates V1 and V2, shifts right by some number of
7213 /// elements, and takes the low elements as the result. Note that while this is
7214 /// specified as a *right shift* because x86 is little-endian, it is a *left
7215 /// rotate* of the vector lanes.
7216 static SDValue lowerVectorShuffleAsByteRotate(SDLoc DL, MVT VT, SDValue V1,
7219 const X86Subtarget *Subtarget,
7220 SelectionDAG &DAG) {
7221 assert(!isNoopShuffleMask(Mask) && "We shouldn't lower no-op shuffles!");
7223 int NumElts = Mask.size();
7224 int NumLanes = VT.getSizeInBits() / 128;
7225 int NumLaneElts = NumElts / NumLanes;
7227 // We need to detect various ways of spelling a rotation:
7228 // [11, 12, 13, 14, 15, 0, 1, 2]
7229 // [-1, 12, 13, 14, -1, -1, 1, -1]
7230 // [-1, -1, -1, -1, -1, -1, 1, 2]
7231 // [ 3, 4, 5, 6, 7, 8, 9, 10]
7232 // [-1, 4, 5, 6, -1, -1, 9, -1]
7233 // [-1, 4, 5, 6, -1, -1, -1, -1]
7236 for (int l = 0; l < NumElts; l += NumLaneElts) {
7237 for (int i = 0; i < NumLaneElts; ++i) {
7238 if (Mask[l + i] == -1)
7240 assert(Mask[l + i] >= 0 && "Only -1 is a valid negative mask element!");
7242 // Get the mod-Size index and lane correct it.
7243 int LaneIdx = (Mask[l + i] % NumElts) - l;
7244 // Make sure it was in this lane.
7245 if (LaneIdx < 0 || LaneIdx >= NumLaneElts)
7248 // Determine where a rotated vector would have started.
7249 int StartIdx = i - LaneIdx;
7251 // The identity rotation isn't interesting, stop.
7254 // If we found the tail of a vector the rotation must be the missing
7255 // front. If we found the head of a vector, it must be how much of the
7257 int CandidateRotation = StartIdx < 0 ? -StartIdx : NumLaneElts - StartIdx;
7260 Rotation = CandidateRotation;
7261 else if (Rotation != CandidateRotation)
7262 // The rotations don't match, so we can't match this mask.
7265 // Compute which value this mask is pointing at.
7266 SDValue MaskV = Mask[l + i] < NumElts ? V1 : V2;
7268 // Compute which of the two target values this index should be assigned
7269 // to. This reflects whether the high elements are remaining or the low
7270 // elements are remaining.
7271 SDValue &TargetV = StartIdx < 0 ? Hi : Lo;
7273 // Either set up this value if we've not encountered it before, or check
7274 // that it remains consistent.
7277 else if (TargetV != MaskV)
7278 // This may be a rotation, but it pulls from the inputs in some
7279 // unsupported interleaving.
7284 // Check that we successfully analyzed the mask, and normalize the results.
7285 assert(Rotation != 0 && "Failed to locate a viable rotation!");
7286 assert((Lo || Hi) && "Failed to find a rotated input vector!");
7292 // The actual rotate instruction rotates bytes, so we need to scale the
7293 // rotation based on how many bytes are in the vector lane.
7294 int Scale = 16 / NumLaneElts;
7296 // SSSE3 targets can use the palignr instruction.
7297 if (Subtarget->hasSSSE3()) {
7298 // Cast the inputs to i8 vector of correct length to match PALIGNR.
7299 MVT AlignVT = MVT::getVectorVT(MVT::i8, 16 * NumLanes);
7300 Lo = DAG.getBitcast(AlignVT, Lo);
7301 Hi = DAG.getBitcast(AlignVT, Hi);
7303 return DAG.getBitcast(
7304 VT, DAG.getNode(X86ISD::PALIGNR, DL, AlignVT, Lo, Hi,
7305 DAG.getConstant(Rotation * Scale, DL, MVT::i8)));
7308 assert(VT.is128BitVector() &&
7309 "Rotate-based lowering only supports 128-bit lowering!");
7310 assert(Mask.size() <= 16 &&
7311 "Can shuffle at most 16 bytes in a 128-bit vector!");
7313 // Default SSE2 implementation
7314 int LoByteShift = 16 - Rotation * Scale;
7315 int HiByteShift = Rotation * Scale;
7317 // Cast the inputs to v2i64 to match PSLLDQ/PSRLDQ.
7318 Lo = DAG.getBitcast(MVT::v2i64, Lo);
7319 Hi = DAG.getBitcast(MVT::v2i64, Hi);
7321 SDValue LoShift = DAG.getNode(X86ISD::VSHLDQ, DL, MVT::v2i64, Lo,
7322 DAG.getConstant(LoByteShift, DL, MVT::i8));
7323 SDValue HiShift = DAG.getNode(X86ISD::VSRLDQ, DL, MVT::v2i64, Hi,
7324 DAG.getConstant(HiByteShift, DL, MVT::i8));
7325 return DAG.getBitcast(VT,
7326 DAG.getNode(ISD::OR, DL, MVT::v2i64, LoShift, HiShift));
7329 /// \brief Try to lower a vector shuffle as a bit shift (shifts in zeros).
7331 /// Attempts to match a shuffle mask against the PSLL(W/D/Q/DQ) and
7332 /// PSRL(W/D/Q/DQ) SSE2 and AVX2 logical bit-shift instructions. The function
7333 /// matches elements from one of the input vectors shuffled to the left or
7334 /// right with zeroable elements 'shifted in'. It handles both the strictly
7335 /// bit-wise element shifts and the byte shift across an entire 128-bit double
7338 /// PSHL : (little-endian) left bit shift.
7339 /// [ zz, 0, zz, 2 ]
7340 /// [ -1, 4, zz, -1 ]
7341 /// PSRL : (little-endian) right bit shift.
7343 /// [ -1, -1, 7, zz]
7344 /// PSLLDQ : (little-endian) left byte shift
7345 /// [ zz, 0, 1, 2, 3, 4, 5, 6]
7346 /// [ zz, zz, -1, -1, 2, 3, 4, -1]
7347 /// [ zz, zz, zz, zz, zz, zz, -1, 1]
7348 /// PSRLDQ : (little-endian) right byte shift
7349 /// [ 5, 6, 7, zz, zz, zz, zz, zz]
7350 /// [ -1, 5, 6, 7, zz, zz, zz, zz]
7351 /// [ 1, 2, -1, -1, -1, -1, zz, zz]
7352 static SDValue lowerVectorShuffleAsShift(SDLoc DL, MVT VT, SDValue V1,
7353 SDValue V2, ArrayRef<int> Mask,
7354 SelectionDAG &DAG) {
7355 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7357 int Size = Mask.size();
7358 assert(Size == (int)VT.getVectorNumElements() && "Unexpected mask size");
7360 auto CheckZeros = [&](int Shift, int Scale, bool Left) {
7361 for (int i = 0; i < Size; i += Scale)
7362 for (int j = 0; j < Shift; ++j)
7363 if (!Zeroable[i + j + (Left ? 0 : (Scale - Shift))])
7369 auto MatchShift = [&](int Shift, int Scale, bool Left, SDValue V) {
7370 for (int i = 0; i != Size; i += Scale) {
7371 unsigned Pos = Left ? i + Shift : i;
7372 unsigned Low = Left ? i : i + Shift;
7373 unsigned Len = Scale - Shift;
7374 if (!isSequentialOrUndefInRange(Mask, Pos, Len,
7375 Low + (V == V1 ? 0 : Size)))
7379 int ShiftEltBits = VT.getScalarSizeInBits() * Scale;
7380 bool ByteShift = ShiftEltBits > 64;
7381 unsigned OpCode = Left ? (ByteShift ? X86ISD::VSHLDQ : X86ISD::VSHLI)
7382 : (ByteShift ? X86ISD::VSRLDQ : X86ISD::VSRLI);
7383 int ShiftAmt = Shift * VT.getScalarSizeInBits() / (ByteShift ? 8 : 1);
7385 // Normalize the scale for byte shifts to still produce an i64 element
7387 Scale = ByteShift ? Scale / 2 : Scale;
7389 // We need to round trip through the appropriate type for the shift.
7390 MVT ShiftSVT = MVT::getIntegerVT(VT.getScalarSizeInBits() * Scale);
7391 MVT ShiftVT = MVT::getVectorVT(ShiftSVT, Size / Scale);
7392 assert(DAG.getTargetLoweringInfo().isTypeLegal(ShiftVT) &&
7393 "Illegal integer vector type");
7394 V = DAG.getBitcast(ShiftVT, V);
7396 V = DAG.getNode(OpCode, DL, ShiftVT, V,
7397 DAG.getConstant(ShiftAmt, DL, MVT::i8));
7398 return DAG.getBitcast(VT, V);
7401 // SSE/AVX supports logical shifts up to 64-bit integers - so we can just
7402 // keep doubling the size of the integer elements up to that. We can
7403 // then shift the elements of the integer vector by whole multiples of
7404 // their width within the elements of the larger integer vector. Test each
7405 // multiple to see if we can find a match with the moved element indices
7406 // and that the shifted in elements are all zeroable.
7407 for (int Scale = 2; Scale * VT.getScalarSizeInBits() <= 128; Scale *= 2)
7408 for (int Shift = 1; Shift != Scale; ++Shift)
7409 for (bool Left : {true, false})
7410 if (CheckZeros(Shift, Scale, Left))
7411 for (SDValue V : {V1, V2})
7412 if (SDValue Match = MatchShift(Shift, Scale, Left, V))
7419 /// \brief Try to lower a vector shuffle using SSE4a EXTRQ/INSERTQ.
7420 static SDValue lowerVectorShuffleWithSSE4A(SDLoc DL, MVT VT, SDValue V1,
7421 SDValue V2, ArrayRef<int> Mask,
7422 SelectionDAG &DAG) {
7423 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7424 assert(!Zeroable.all() && "Fully zeroable shuffle mask");
7426 int Size = Mask.size();
7427 int HalfSize = Size / 2;
7428 assert(Size == (int)VT.getVectorNumElements() && "Unexpected mask size");
7430 // Upper half must be undefined.
7431 if (!isUndefInRange(Mask, HalfSize, HalfSize))
7434 // EXTRQ: Extract Len elements from lower half of source, starting at Idx.
7435 // Remainder of lower half result is zero and upper half is all undef.
7436 auto LowerAsEXTRQ = [&]() {
7437 // Determine the extraction length from the part of the
7438 // lower half that isn't zeroable.
7440 for (; Len > 0; --Len)
7441 if (!Zeroable[Len - 1])
7443 assert(Len > 0 && "Zeroable shuffle mask");
7445 // Attempt to match first Len sequential elements from the lower half.
7448 for (int i = 0; i != Len; ++i) {
7452 SDValue &V = (M < Size ? V1 : V2);
7455 // The extracted elements must start at a valid index and all mask
7456 // elements must be in the lower half.
7457 if (i > M || M >= HalfSize)
7460 if (Idx < 0 || (Src == V && Idx == (M - i))) {
7471 assert((Idx + Len) <= HalfSize && "Illegal extraction mask");
7472 int BitLen = (Len * VT.getScalarSizeInBits()) & 0x3f;
7473 int BitIdx = (Idx * VT.getScalarSizeInBits()) & 0x3f;
7474 return DAG.getNode(X86ISD::EXTRQI, DL, VT, Src,
7475 DAG.getConstant(BitLen, DL, MVT::i8),
7476 DAG.getConstant(BitIdx, DL, MVT::i8));
7479 if (SDValue ExtrQ = LowerAsEXTRQ())
7482 // INSERTQ: Extract lowest Len elements from lower half of second source and
7483 // insert over first source, starting at Idx.
7484 // { A[0], .., A[Idx-1], B[0], .., B[Len-1], A[Idx+Len], .., UNDEF, ... }
7485 auto LowerAsInsertQ = [&]() {
7486 for (int Idx = 0; Idx != HalfSize; ++Idx) {
7489 // Attempt to match first source from mask before insertion point.
7490 if (isUndefInRange(Mask, 0, Idx)) {
7492 } else if (isSequentialOrUndefInRange(Mask, 0, Idx, 0)) {
7494 } else if (isSequentialOrUndefInRange(Mask, 0, Idx, Size)) {
7500 // Extend the extraction length looking to match both the insertion of
7501 // the second source and the remaining elements of the first.
7502 for (int Hi = Idx + 1; Hi <= HalfSize; ++Hi) {
7507 if (isSequentialOrUndefInRange(Mask, Idx, Len, 0)) {
7509 } else if (isSequentialOrUndefInRange(Mask, Idx, Len, Size)) {
7515 // Match the remaining elements of the lower half.
7516 if (isUndefInRange(Mask, Hi, HalfSize - Hi)) {
7518 } else if ((!Base || (Base == V1)) &&
7519 isSequentialOrUndefInRange(Mask, Hi, HalfSize - Hi, Hi)) {
7521 } else if ((!Base || (Base == V2)) &&
7522 isSequentialOrUndefInRange(Mask, Hi, HalfSize - Hi,
7529 // We may not have a base (first source) - this can safely be undefined.
7531 Base = DAG.getUNDEF(VT);
7533 int BitLen = (Len * VT.getScalarSizeInBits()) & 0x3f;
7534 int BitIdx = (Idx * VT.getScalarSizeInBits()) & 0x3f;
7535 return DAG.getNode(X86ISD::INSERTQI, DL, VT, Base, Insert,
7536 DAG.getConstant(BitLen, DL, MVT::i8),
7537 DAG.getConstant(BitIdx, DL, MVT::i8));
7544 if (SDValue InsertQ = LowerAsInsertQ())
7550 /// \brief Lower a vector shuffle as a zero or any extension.
7552 /// Given a specific number of elements, element bit width, and extension
7553 /// stride, produce either a zero or any extension based on the available
7554 /// features of the subtarget. The extended elements are consecutive and
7555 /// begin and can start from an offseted element index in the input; to
7556 /// avoid excess shuffling the offset must either being in the bottom lane
7557 /// or at the start of a higher lane. All extended elements must be from
7559 static SDValue lowerVectorShuffleAsSpecificZeroOrAnyExtend(
7560 SDLoc DL, MVT VT, int Scale, int Offset, bool AnyExt, SDValue InputV,
7561 ArrayRef<int> Mask, const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7562 assert(Scale > 1 && "Need a scale to extend.");
7563 int EltBits = VT.getScalarSizeInBits();
7564 int NumElements = VT.getVectorNumElements();
7565 int NumEltsPerLane = 128 / EltBits;
7566 int OffsetLane = Offset / NumEltsPerLane;
7567 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
7568 "Only 8, 16, and 32 bit elements can be extended.");
7569 assert(Scale * EltBits <= 64 && "Cannot zero extend past 64 bits.");
7570 assert(0 <= Offset && "Extension offset must be positive.");
7571 assert((Offset < NumEltsPerLane || Offset % NumEltsPerLane == 0) &&
7572 "Extension offset must be in the first lane or start an upper lane.");
7574 // Check that an index is in same lane as the base offset.
7575 auto SafeOffset = [&](int Idx) {
7576 return OffsetLane == (Idx / NumEltsPerLane);
7579 // Shift along an input so that the offset base moves to the first element.
7580 auto ShuffleOffset = [&](SDValue V) {
7584 SmallVector<int, 8> ShMask((unsigned)NumElements, -1);
7585 for (int i = 0; i * Scale < NumElements; ++i) {
7586 int SrcIdx = i + Offset;
7587 ShMask[i] = SafeOffset(SrcIdx) ? SrcIdx : -1;
7589 return DAG.getVectorShuffle(VT, DL, V, DAG.getUNDEF(VT), ShMask);
7592 // Found a valid zext mask! Try various lowering strategies based on the
7593 // input type and available ISA extensions.
7594 if (Subtarget->hasSSE41()) {
7595 // Not worth offseting 128-bit vectors if scale == 2, a pattern using
7596 // PUNPCK will catch this in a later shuffle match.
7597 if (Offset && Scale == 2 && VT.is128BitVector())
7599 MVT ExtVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits * Scale),
7600 NumElements / Scale);
7601 InputV = DAG.getNode(X86ISD::VZEXT, DL, ExtVT, ShuffleOffset(InputV));
7602 return DAG.getBitcast(VT, InputV);
7605 assert(VT.is128BitVector() && "Only 128-bit vectors can be extended.");
7607 // For any extends we can cheat for larger element sizes and use shuffle
7608 // instructions that can fold with a load and/or copy.
7609 if (AnyExt && EltBits == 32) {
7610 int PSHUFDMask[4] = {Offset, -1, SafeOffset(Offset + 1) ? Offset + 1 : -1,
7612 return DAG.getBitcast(
7613 VT, DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
7614 DAG.getBitcast(MVT::v4i32, InputV),
7615 getV4X86ShuffleImm8ForMask(PSHUFDMask, DL, DAG)));
7617 if (AnyExt && EltBits == 16 && Scale > 2) {
7618 int PSHUFDMask[4] = {Offset / 2, -1,
7619 SafeOffset(Offset + 1) ? (Offset + 1) / 2 : -1, -1};
7620 InputV = DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
7621 DAG.getBitcast(MVT::v4i32, InputV),
7622 getV4X86ShuffleImm8ForMask(PSHUFDMask, DL, DAG));
7623 int PSHUFWMask[4] = {1, -1, -1, -1};
7624 unsigned OddEvenOp = (Offset & 1 ? X86ISD::PSHUFLW : X86ISD::PSHUFHW);
7625 return DAG.getBitcast(
7626 VT, DAG.getNode(OddEvenOp, DL, MVT::v8i16,
7627 DAG.getBitcast(MVT::v8i16, InputV),
7628 getV4X86ShuffleImm8ForMask(PSHUFWMask, DL, DAG)));
7631 // The SSE4A EXTRQ instruction can efficiently extend the first 2 lanes
7633 if ((Scale * EltBits) == 64 && EltBits < 32 && Subtarget->hasSSE4A()) {
7634 assert(NumElements == (int)Mask.size() && "Unexpected shuffle mask size!");
7635 assert(VT.is128BitVector() && "Unexpected vector width!");
7637 int LoIdx = Offset * EltBits;
7638 SDValue Lo = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64,
7639 DAG.getNode(X86ISD::EXTRQI, DL, VT, InputV,
7640 DAG.getConstant(EltBits, DL, MVT::i8),
7641 DAG.getConstant(LoIdx, DL, MVT::i8)));
7643 if (isUndefInRange(Mask, NumElements / 2, NumElements / 2) ||
7644 !SafeOffset(Offset + 1))
7645 return DAG.getNode(ISD::BITCAST, DL, VT, Lo);
7647 int HiIdx = (Offset + 1) * EltBits;
7648 SDValue Hi = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64,
7649 DAG.getNode(X86ISD::EXTRQI, DL, VT, InputV,
7650 DAG.getConstant(EltBits, DL, MVT::i8),
7651 DAG.getConstant(HiIdx, DL, MVT::i8)));
7652 return DAG.getNode(ISD::BITCAST, DL, VT,
7653 DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2i64, Lo, Hi));
7656 // If this would require more than 2 unpack instructions to expand, use
7657 // pshufb when available. We can only use more than 2 unpack instructions
7658 // when zero extending i8 elements which also makes it easier to use pshufb.
7659 if (Scale > 4 && EltBits == 8 && Subtarget->hasSSSE3()) {
7660 assert(NumElements == 16 && "Unexpected byte vector width!");
7661 SDValue PSHUFBMask[16];
7662 for (int i = 0; i < 16; ++i) {
7663 int Idx = Offset + (i / Scale);
7664 PSHUFBMask[i] = DAG.getConstant(
7665 (i % Scale == 0 && SafeOffset(Idx)) ? Idx : 0x80, DL, MVT::i8);
7667 InputV = DAG.getBitcast(MVT::v16i8, InputV);
7668 return DAG.getBitcast(VT,
7669 DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, InputV,
7670 DAG.getNode(ISD::BUILD_VECTOR, DL,
7671 MVT::v16i8, PSHUFBMask)));
7674 // If we are extending from an offset, ensure we start on a boundary that
7675 // we can unpack from.
7676 int AlignToUnpack = Offset % (NumElements / Scale);
7677 if (AlignToUnpack) {
7678 SmallVector<int, 8> ShMask((unsigned)NumElements, -1);
7679 for (int i = AlignToUnpack; i < NumElements; ++i)
7680 ShMask[i - AlignToUnpack] = i;
7681 InputV = DAG.getVectorShuffle(VT, DL, InputV, DAG.getUNDEF(VT), ShMask);
7682 Offset -= AlignToUnpack;
7685 // Otherwise emit a sequence of unpacks.
7687 unsigned UnpackLoHi = X86ISD::UNPCKL;
7688 if (Offset >= (NumElements / 2)) {
7689 UnpackLoHi = X86ISD::UNPCKH;
7690 Offset -= (NumElements / 2);
7693 MVT InputVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits), NumElements);
7694 SDValue Ext = AnyExt ? DAG.getUNDEF(InputVT)
7695 : getZeroVector(InputVT, Subtarget, DAG, DL);
7696 InputV = DAG.getBitcast(InputVT, InputV);
7697 InputV = DAG.getNode(UnpackLoHi, DL, InputVT, InputV, Ext);
7701 } while (Scale > 1);
7702 return DAG.getBitcast(VT, InputV);
7705 /// \brief Try to lower a vector shuffle as a zero extension on any microarch.
7707 /// This routine will try to do everything in its power to cleverly lower
7708 /// a shuffle which happens to match the pattern of a zero extend. It doesn't
7709 /// check for the profitability of this lowering, it tries to aggressively
7710 /// match this pattern. It will use all of the micro-architectural details it
7711 /// can to emit an efficient lowering. It handles both blends with all-zero
7712 /// inputs to explicitly zero-extend and undef-lanes (sometimes undef due to
7713 /// masking out later).
7715 /// The reason we have dedicated lowering for zext-style shuffles is that they
7716 /// are both incredibly common and often quite performance sensitive.
7717 static SDValue lowerVectorShuffleAsZeroOrAnyExtend(
7718 SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
7719 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7720 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7722 int Bits = VT.getSizeInBits();
7723 int NumLanes = Bits / 128;
7724 int NumElements = VT.getVectorNumElements();
7725 int NumEltsPerLane = NumElements / NumLanes;
7726 assert(VT.getScalarSizeInBits() <= 32 &&
7727 "Exceeds 32-bit integer zero extension limit");
7728 assert((int)Mask.size() == NumElements && "Unexpected shuffle mask size");
7730 // Define a helper function to check a particular ext-scale and lower to it if
7732 auto Lower = [&](int Scale) -> SDValue {
7737 for (int i = 0; i < NumElements; ++i) {
7740 continue; // Valid anywhere but doesn't tell us anything.
7741 if (i % Scale != 0) {
7742 // Each of the extended elements need to be zeroable.
7746 // We no longer are in the anyext case.
7751 // Each of the base elements needs to be consecutive indices into the
7752 // same input vector.
7753 SDValue V = M < NumElements ? V1 : V2;
7754 M = M % NumElements;
7757 Offset = M - (i / Scale);
7758 } else if (InputV != V)
7759 return SDValue(); // Flip-flopping inputs.
7761 // Offset must start in the lowest 128-bit lane or at the start of an
7763 // FIXME: Is it ever worth allowing a negative base offset?
7764 if (!((0 <= Offset && Offset < NumEltsPerLane) ||
7765 (Offset % NumEltsPerLane) == 0))
7768 // If we are offsetting, all referenced entries must come from the same
7770 if (Offset && (Offset / NumEltsPerLane) != (M / NumEltsPerLane))
7773 if ((M % NumElements) != (Offset + (i / Scale)))
7774 return SDValue(); // Non-consecutive strided elements.
7778 // If we fail to find an input, we have a zero-shuffle which should always
7779 // have already been handled.
7780 // FIXME: Maybe handle this here in case during blending we end up with one?
7784 // If we are offsetting, don't extend if we only match a single input, we
7785 // can always do better by using a basic PSHUF or PUNPCK.
7786 if (Offset != 0 && Matches < 2)
7789 return lowerVectorShuffleAsSpecificZeroOrAnyExtend(
7790 DL, VT, Scale, Offset, AnyExt, InputV, Mask, Subtarget, DAG);
7793 // The widest scale possible for extending is to a 64-bit integer.
7794 assert(Bits % 64 == 0 &&
7795 "The number of bits in a vector must be divisible by 64 on x86!");
7796 int NumExtElements = Bits / 64;
7798 // Each iteration, try extending the elements half as much, but into twice as
7800 for (; NumExtElements < NumElements; NumExtElements *= 2) {
7801 assert(NumElements % NumExtElements == 0 &&
7802 "The input vector size must be divisible by the extended size.");
7803 if (SDValue V = Lower(NumElements / NumExtElements))
7807 // General extends failed, but 128-bit vectors may be able to use MOVQ.
7811 // Returns one of the source operands if the shuffle can be reduced to a
7812 // MOVQ, copying the lower 64-bits and zero-extending to the upper 64-bits.
7813 auto CanZExtLowHalf = [&]() {
7814 for (int i = NumElements / 2; i != NumElements; ++i)
7817 if (isSequentialOrUndefInRange(Mask, 0, NumElements / 2, 0))
7819 if (isSequentialOrUndefInRange(Mask, 0, NumElements / 2, NumElements))
7824 if (SDValue V = CanZExtLowHalf()) {
7825 V = DAG.getBitcast(MVT::v2i64, V);
7826 V = DAG.getNode(X86ISD::VZEXT_MOVL, DL, MVT::v2i64, V);
7827 return DAG.getBitcast(VT, V);
7830 // No viable ext lowering found.
7834 /// \brief Try to get a scalar value for a specific element of a vector.
7836 /// Looks through BUILD_VECTOR and SCALAR_TO_VECTOR nodes to find a scalar.
7837 static SDValue getScalarValueForVectorElement(SDValue V, int Idx,
7838 SelectionDAG &DAG) {
7839 MVT VT = V.getSimpleValueType();
7840 MVT EltVT = VT.getVectorElementType();
7841 while (V.getOpcode() == ISD::BITCAST)
7842 V = V.getOperand(0);
7843 // If the bitcasts shift the element size, we can't extract an equivalent
7845 MVT NewVT = V.getSimpleValueType();
7846 if (!NewVT.isVector() || NewVT.getScalarSizeInBits() != VT.getScalarSizeInBits())
7849 if (V.getOpcode() == ISD::BUILD_VECTOR ||
7850 (Idx == 0 && V.getOpcode() == ISD::SCALAR_TO_VECTOR)) {
7851 // Ensure the scalar operand is the same size as the destination.
7852 // FIXME: Add support for scalar truncation where possible.
7853 SDValue S = V.getOperand(Idx);
7854 if (EltVT.getSizeInBits() == S.getSimpleValueType().getSizeInBits())
7855 return DAG.getNode(ISD::BITCAST, SDLoc(V), EltVT, S);
7861 /// \brief Helper to test for a load that can be folded with x86 shuffles.
7863 /// This is particularly important because the set of instructions varies
7864 /// significantly based on whether the operand is a load or not.
7865 static bool isShuffleFoldableLoad(SDValue V) {
7866 while (V.getOpcode() == ISD::BITCAST)
7867 V = V.getOperand(0);
7869 return ISD::isNON_EXTLoad(V.getNode());
7872 /// \brief Try to lower insertion of a single element into a zero vector.
7874 /// This is a common pattern that we have especially efficient patterns to lower
7875 /// across all subtarget feature sets.
7876 static SDValue lowerVectorShuffleAsElementInsertion(
7877 SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
7878 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7879 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7881 MVT EltVT = VT.getVectorElementType();
7883 int V2Index = std::find_if(Mask.begin(), Mask.end(),
7884 [&Mask](int M) { return M >= (int)Mask.size(); }) -
7886 bool IsV1Zeroable = true;
7887 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7888 if (i != V2Index && !Zeroable[i]) {
7889 IsV1Zeroable = false;
7893 // Check for a single input from a SCALAR_TO_VECTOR node.
7894 // FIXME: All of this should be canonicalized into INSERT_VECTOR_ELT and
7895 // all the smarts here sunk into that routine. However, the current
7896 // lowering of BUILD_VECTOR makes that nearly impossible until the old
7897 // vector shuffle lowering is dead.
7898 SDValue V2S = getScalarValueForVectorElement(V2, Mask[V2Index] - Mask.size(),
7900 if (V2S && DAG.getTargetLoweringInfo().isTypeLegal(V2S.getValueType())) {
7901 // We need to zext the scalar if it is smaller than an i32.
7902 V2S = DAG.getBitcast(EltVT, V2S);
7903 if (EltVT == MVT::i8 || EltVT == MVT::i16) {
7904 // Using zext to expand a narrow element won't work for non-zero
7909 // Zero-extend directly to i32.
7911 V2S = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, V2S);
7913 V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, ExtVT, V2S);
7914 } else if (Mask[V2Index] != (int)Mask.size() || EltVT == MVT::i8 ||
7915 EltVT == MVT::i16) {
7916 // Either not inserting from the low element of the input or the input
7917 // element size is too small to use VZEXT_MOVL to clear the high bits.
7921 if (!IsV1Zeroable) {
7922 // If V1 can't be treated as a zero vector we have fewer options to lower
7923 // this. We can't support integer vectors or non-zero targets cheaply, and
7924 // the V1 elements can't be permuted in any way.
7925 assert(VT == ExtVT && "Cannot change extended type when non-zeroable!");
7926 if (!VT.isFloatingPoint() || V2Index != 0)
7928 SmallVector<int, 8> V1Mask(Mask.begin(), Mask.end());
7929 V1Mask[V2Index] = -1;
7930 if (!isNoopShuffleMask(V1Mask))
7932 // This is essentially a special case blend operation, but if we have
7933 // general purpose blend operations, they are always faster. Bail and let
7934 // the rest of the lowering handle these as blends.
7935 if (Subtarget->hasSSE41())
7938 // Otherwise, use MOVSD or MOVSS.
7939 assert((EltVT == MVT::f32 || EltVT == MVT::f64) &&
7940 "Only two types of floating point element types to handle!");
7941 return DAG.getNode(EltVT == MVT::f32 ? X86ISD::MOVSS : X86ISD::MOVSD, DL,
7945 // This lowering only works for the low element with floating point vectors.
7946 if (VT.isFloatingPoint() && V2Index != 0)
7949 V2 = DAG.getNode(X86ISD::VZEXT_MOVL, DL, ExtVT, V2);
7951 V2 = DAG.getBitcast(VT, V2);
7954 // If we have 4 or fewer lanes we can cheaply shuffle the element into
7955 // the desired position. Otherwise it is more efficient to do a vector
7956 // shift left. We know that we can do a vector shift left because all
7957 // the inputs are zero.
7958 if (VT.isFloatingPoint() || VT.getVectorNumElements() <= 4) {
7959 SmallVector<int, 4> V2Shuffle(Mask.size(), 1);
7960 V2Shuffle[V2Index] = 0;
7961 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Shuffle);
7963 V2 = DAG.getBitcast(MVT::v2i64, V2);
7965 X86ISD::VSHLDQ, DL, MVT::v2i64, V2,
7966 DAG.getConstant(V2Index * EltVT.getSizeInBits() / 8, DL,
7967 DAG.getTargetLoweringInfo().getScalarShiftAmountTy(
7968 DAG.getDataLayout(), VT)));
7969 V2 = DAG.getBitcast(VT, V2);
7975 /// \brief Try to lower broadcast of a single - truncated - integer element,
7976 /// coming from a scalar_to_vector/build_vector node \p V0 with larger elements.
7978 /// This assumes we have AVX2.
7979 static SDValue lowerVectorShuffleAsTruncBroadcast(SDLoc DL, MVT VT, SDValue V0,
7981 const X86Subtarget *Subtarget,
7982 SelectionDAG &DAG) {
7983 assert(Subtarget->hasAVX2() &&
7984 "We can only lower integer broadcasts with AVX2!");
7986 EVT EltVT = VT.getVectorElementType();
7987 EVT V0VT = V0.getValueType();
7989 assert(VT.isInteger() && "Unexpected non-integer trunc broadcast!");
7990 assert(V0VT.isVector() && "Unexpected non-vector vector-sized value!");
7992 EVT V0EltVT = V0VT.getVectorElementType();
7993 if (!V0EltVT.isInteger())
7996 const unsigned EltSize = EltVT.getSizeInBits();
7997 const unsigned V0EltSize = V0EltVT.getSizeInBits();
7999 // This is only a truncation if the original element type is larger.
8000 if (V0EltSize <= EltSize)
8003 assert(((V0EltSize % EltSize) == 0) &&
8004 "Scalar type sizes must all be powers of 2 on x86!");
8006 const unsigned V0Opc = V0.getOpcode();
8007 const unsigned Scale = V0EltSize / EltSize;
8008 const unsigned V0BroadcastIdx = BroadcastIdx / Scale;
8010 if ((V0Opc != ISD::SCALAR_TO_VECTOR || V0BroadcastIdx != 0) &&
8011 V0Opc != ISD::BUILD_VECTOR)
8014 SDValue Scalar = V0.getOperand(V0BroadcastIdx);
8016 // If we're extracting non-least-significant bits, shift so we can truncate.
8017 // Hopefully, we can fold away the trunc/srl/load into the broadcast.
8018 // Even if we can't (and !isShuffleFoldableLoad(Scalar)), prefer
8019 // vpbroadcast+vmovd+shr to vpshufb(m)+vmovd.
8020 if (const int OffsetIdx = BroadcastIdx % Scale)
8021 Scalar = DAG.getNode(ISD::SRL, DL, Scalar.getValueType(), Scalar,
8022 DAG.getConstant(OffsetIdx * EltSize, DL, Scalar.getValueType()));
8024 return DAG.getNode(X86ISD::VBROADCAST, DL, VT,
8025 DAG.getNode(ISD::TRUNCATE, DL, EltVT, Scalar));
8028 /// \brief Try to lower broadcast of a single element.
8030 /// For convenience, this code also bundles all of the subtarget feature set
8031 /// filtering. While a little annoying to re-dispatch on type here, there isn't
8032 /// a convenient way to factor it out.
8033 static SDValue lowerVectorShuffleAsBroadcast(SDLoc DL, MVT VT, SDValue V,
8035 const X86Subtarget *Subtarget,
8036 SelectionDAG &DAG) {
8037 if (!Subtarget->hasAVX())
8039 if (VT.isInteger() && !Subtarget->hasAVX2())
8042 // Check that the mask is a broadcast.
8043 int BroadcastIdx = -1;
8045 if (M >= 0 && BroadcastIdx == -1)
8047 else if (M >= 0 && M != BroadcastIdx)
8050 assert(BroadcastIdx < (int)Mask.size() && "We only expect to be called with "
8051 "a sorted mask where the broadcast "
8054 // Go up the chain of (vector) values to find a scalar load that we can
8055 // combine with the broadcast.
8057 switch (V.getOpcode()) {
8058 case ISD::CONCAT_VECTORS: {
8059 int OperandSize = Mask.size() / V.getNumOperands();
8060 V = V.getOperand(BroadcastIdx / OperandSize);
8061 BroadcastIdx %= OperandSize;
8065 case ISD::INSERT_SUBVECTOR: {
8066 SDValue VOuter = V.getOperand(0), VInner = V.getOperand(1);
8067 auto ConstantIdx = dyn_cast<ConstantSDNode>(V.getOperand(2));
8071 int BeginIdx = (int)ConstantIdx->getZExtValue();
8073 BeginIdx + (int)VInner.getSimpleValueType().getVectorNumElements();
8074 if (BroadcastIdx >= BeginIdx && BroadcastIdx < EndIdx) {
8075 BroadcastIdx -= BeginIdx;
8086 // Check if this is a broadcast of a scalar. We special case lowering
8087 // for scalars so that we can more effectively fold with loads.
8088 // First, look through bitcast: if the original value has a larger element
8089 // type than the shuffle, the broadcast element is in essence truncated.
8090 // Make that explicit to ease folding.
8091 if (V.getOpcode() == ISD::BITCAST && VT.isInteger())
8092 if (SDValue TruncBroadcast = lowerVectorShuffleAsTruncBroadcast(
8093 DL, VT, V.getOperand(0), BroadcastIdx, Subtarget, DAG))
8094 return TruncBroadcast;
8096 // Also check the simpler case, where we can directly reuse the scalar.
8097 if (V.getOpcode() == ISD::BUILD_VECTOR ||
8098 (V.getOpcode() == ISD::SCALAR_TO_VECTOR && BroadcastIdx == 0)) {
8099 V = V.getOperand(BroadcastIdx);
8101 // If the scalar isn't a load, we can't broadcast from it in AVX1.
8102 // Only AVX2 has register broadcasts.
8103 if (!Subtarget->hasAVX2() && !isShuffleFoldableLoad(V))
8105 } else if (BroadcastIdx != 0 || !Subtarget->hasAVX2()) {
8106 // We can't broadcast from a vector register without AVX2, and we can only
8107 // broadcast from the zero-element of a vector register.
8111 return DAG.getNode(X86ISD::VBROADCAST, DL, VT, V);
8114 // Check for whether we can use INSERTPS to perform the shuffle. We only use
8115 // INSERTPS when the V1 elements are already in the correct locations
8116 // because otherwise we can just always use two SHUFPS instructions which
8117 // are much smaller to encode than a SHUFPS and an INSERTPS. We can also
8118 // perform INSERTPS if a single V1 element is out of place and all V2
8119 // elements are zeroable.
8120 static SDValue lowerVectorShuffleAsInsertPS(SDValue Op, SDValue V1, SDValue V2,
8122 SelectionDAG &DAG) {
8123 assert(Op.getSimpleValueType() == MVT::v4f32 && "Bad shuffle type!");
8124 assert(V1.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
8125 assert(V2.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
8126 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
8128 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
8131 int V1DstIndex = -1;
8132 int V2DstIndex = -1;
8133 bool V1UsedInPlace = false;
8135 for (int i = 0; i < 4; ++i) {
8136 // Synthesize a zero mask from the zeroable elements (includes undefs).
8142 // Flag if we use any V1 inputs in place.
8144 V1UsedInPlace = true;
8148 // We can only insert a single non-zeroable element.
8149 if (V1DstIndex != -1 || V2DstIndex != -1)
8153 // V1 input out of place for insertion.
8156 // V2 input for insertion.
8161 // Don't bother if we have no (non-zeroable) element for insertion.
8162 if (V1DstIndex == -1 && V2DstIndex == -1)
8165 // Determine element insertion src/dst indices. The src index is from the
8166 // start of the inserted vector, not the start of the concatenated vector.
8167 unsigned V2SrcIndex = 0;
8168 if (V1DstIndex != -1) {
8169 // If we have a V1 input out of place, we use V1 as the V2 element insertion
8170 // and don't use the original V2 at all.
8171 V2SrcIndex = Mask[V1DstIndex];
8172 V2DstIndex = V1DstIndex;
8175 V2SrcIndex = Mask[V2DstIndex] - 4;
8178 // If no V1 inputs are used in place, then the result is created only from
8179 // the zero mask and the V2 insertion - so remove V1 dependency.
8181 V1 = DAG.getUNDEF(MVT::v4f32);
8183 unsigned InsertPSMask = V2SrcIndex << 6 | V2DstIndex << 4 | ZMask;
8184 assert((InsertPSMask & ~0xFFu) == 0 && "Invalid mask!");
8186 // Insert the V2 element into the desired position.
8188 return DAG.getNode(X86ISD::INSERTPS, DL, MVT::v4f32, V1, V2,
8189 DAG.getConstant(InsertPSMask, DL, MVT::i8));
8192 /// \brief Try to lower a shuffle as a permute of the inputs followed by an
8193 /// UNPCK instruction.
8195 /// This specifically targets cases where we end up with alternating between
8196 /// the two inputs, and so can permute them into something that feeds a single
8197 /// UNPCK instruction. Note that this routine only targets integer vectors
8198 /// because for floating point vectors we have a generalized SHUFPS lowering
8199 /// strategy that handles everything that doesn't *exactly* match an unpack,
8200 /// making this clever lowering unnecessary.
8201 static SDValue lowerVectorShuffleAsPermuteAndUnpack(SDLoc DL, MVT VT,
8202 SDValue V1, SDValue V2,
8204 SelectionDAG &DAG) {
8205 assert(!VT.isFloatingPoint() &&
8206 "This routine only supports integer vectors.");
8207 assert(!isSingleInputShuffleMask(Mask) &&
8208 "This routine should only be used when blending two inputs.");
8209 assert(Mask.size() >= 2 && "Single element masks are invalid.");
8211 int Size = Mask.size();
8213 int NumLoInputs = std::count_if(Mask.begin(), Mask.end(), [Size](int M) {
8214 return M >= 0 && M % Size < Size / 2;
8216 int NumHiInputs = std::count_if(
8217 Mask.begin(), Mask.end(), [Size](int M) { return M % Size >= Size / 2; });
8219 bool UnpackLo = NumLoInputs >= NumHiInputs;
8221 auto TryUnpack = [&](MVT UnpackVT, int Scale) {
8222 SmallVector<int, 32> V1Mask(Mask.size(), -1);
8223 SmallVector<int, 32> V2Mask(Mask.size(), -1);
8225 for (int i = 0; i < Size; ++i) {
8229 // Each element of the unpack contains Scale elements from this mask.
8230 int UnpackIdx = i / Scale;
8232 // We only handle the case where V1 feeds the first slots of the unpack.
8233 // We rely on canonicalization to ensure this is the case.
8234 if ((UnpackIdx % 2 == 0) != (Mask[i] < Size))
8237 // Setup the mask for this input. The indexing is tricky as we have to
8238 // handle the unpack stride.
8239 SmallVectorImpl<int> &VMask = (UnpackIdx % 2 == 0) ? V1Mask : V2Mask;
8240 VMask[(UnpackIdx / 2) * Scale + i % Scale + (UnpackLo ? 0 : Size / 2)] =
8244 // If we will have to shuffle both inputs to use the unpack, check whether
8245 // we can just unpack first and shuffle the result. If so, skip this unpack.
8246 if ((NumLoInputs == 0 || NumHiInputs == 0) && !isNoopShuffleMask(V1Mask) &&
8247 !isNoopShuffleMask(V2Mask))
8250 // Shuffle the inputs into place.
8251 V1 = DAG.getVectorShuffle(VT, DL, V1, DAG.getUNDEF(VT), V1Mask);
8252 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Mask);
8254 // Cast the inputs to the type we will use to unpack them.
8255 V1 = DAG.getBitcast(UnpackVT, V1);
8256 V2 = DAG.getBitcast(UnpackVT, V2);
8258 // Unpack the inputs and cast the result back to the desired type.
8259 return DAG.getBitcast(
8260 VT, DAG.getNode(UnpackLo ? X86ISD::UNPCKL : X86ISD::UNPCKH, DL,
8264 // We try each unpack from the largest to the smallest to try and find one
8265 // that fits this mask.
8266 int OrigNumElements = VT.getVectorNumElements();
8267 int OrigScalarSize = VT.getScalarSizeInBits();
8268 for (int ScalarSize = 64; ScalarSize >= OrigScalarSize; ScalarSize /= 2) {
8269 int Scale = ScalarSize / OrigScalarSize;
8270 int NumElements = OrigNumElements / Scale;
8271 MVT UnpackVT = MVT::getVectorVT(MVT::getIntegerVT(ScalarSize), NumElements);
8272 if (SDValue Unpack = TryUnpack(UnpackVT, Scale))
8276 // If none of the unpack-rooted lowerings worked (or were profitable) try an
8278 if (NumLoInputs == 0 || NumHiInputs == 0) {
8279 assert((NumLoInputs > 0 || NumHiInputs > 0) &&
8280 "We have to have *some* inputs!");
8281 int HalfOffset = NumLoInputs == 0 ? Size / 2 : 0;
8283 // FIXME: We could consider the total complexity of the permute of each
8284 // possible unpacking. Or at the least we should consider how many
8285 // half-crossings are created.
8286 // FIXME: We could consider commuting the unpacks.
8288 SmallVector<int, 32> PermMask;
8289 PermMask.assign(Size, -1);
8290 for (int i = 0; i < Size; ++i) {
8294 assert(Mask[i] % Size >= HalfOffset && "Found input from wrong half!");
8297 2 * ((Mask[i] % Size) - HalfOffset) + (Mask[i] < Size ? 0 : 1);
8299 return DAG.getVectorShuffle(
8300 VT, DL, DAG.getNode(NumLoInputs == 0 ? X86ISD::UNPCKH : X86ISD::UNPCKL,
8302 DAG.getUNDEF(VT), PermMask);
8308 /// \brief Handle lowering of 2-lane 64-bit floating point shuffles.
8310 /// This is the basis function for the 2-lane 64-bit shuffles as we have full
8311 /// support for floating point shuffles but not integer shuffles. These
8312 /// instructions will incur a domain crossing penalty on some chips though so
8313 /// it is better to avoid lowering through this for integer vectors where
8315 static SDValue lowerV2F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8316 const X86Subtarget *Subtarget,
8317 SelectionDAG &DAG) {
8319 assert(Op.getSimpleValueType() == MVT::v2f64 && "Bad shuffle type!");
8320 assert(V1.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
8321 assert(V2.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
8322 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8323 ArrayRef<int> Mask = SVOp->getMask();
8324 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
8326 if (isSingleInputShuffleMask(Mask)) {
8327 // Use low duplicate instructions for masks that match their pattern.
8328 if (Subtarget->hasSSE3())
8329 if (isShuffleEquivalent(V1, V2, Mask, {0, 0}))
8330 return DAG.getNode(X86ISD::MOVDDUP, DL, MVT::v2f64, V1);
8332 // Straight shuffle of a single input vector. Simulate this by using the
8333 // single input as both of the "inputs" to this instruction..
8334 unsigned SHUFPDMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1);
8336 if (Subtarget->hasAVX()) {
8337 // If we have AVX, we can use VPERMILPS which will allow folding a load
8338 // into the shuffle.
8339 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v2f64, V1,
8340 DAG.getConstant(SHUFPDMask, DL, MVT::i8));
8343 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v2f64, V1, V1,
8344 DAG.getConstant(SHUFPDMask, DL, MVT::i8));
8346 assert(Mask[0] >= 0 && Mask[0] < 2 && "Non-canonicalized blend!");
8347 assert(Mask[1] >= 2 && "Non-canonicalized blend!");
8349 // If we have a single input, insert that into V1 if we can do so cheaply.
8350 if ((Mask[0] >= 2) + (Mask[1] >= 2) == 1) {
8351 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8352 DL, MVT::v2f64, V1, V2, Mask, Subtarget, DAG))
8354 // Try inverting the insertion since for v2 masks it is easy to do and we
8355 // can't reliably sort the mask one way or the other.
8356 int InverseMask[2] = {Mask[0] < 0 ? -1 : (Mask[0] ^ 2),
8357 Mask[1] < 0 ? -1 : (Mask[1] ^ 2)};
8358 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8359 DL, MVT::v2f64, V2, V1, InverseMask, Subtarget, DAG))
8363 // Try to use one of the special instruction patterns to handle two common
8364 // blend patterns if a zero-blend above didn't work.
8365 if (isShuffleEquivalent(V1, V2, Mask, {0, 3}) ||
8366 isShuffleEquivalent(V1, V2, Mask, {1, 3}))
8367 if (SDValue V1S = getScalarValueForVectorElement(V1, Mask[0], DAG))
8368 // We can either use a special instruction to load over the low double or
8369 // to move just the low double.
8371 isShuffleFoldableLoad(V1S) ? X86ISD::MOVLPD : X86ISD::MOVSD,
8373 DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2f64, V1S));
8375 if (Subtarget->hasSSE41())
8376 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v2f64, V1, V2, Mask,
8380 // Use dedicated unpack instructions for masks that match their pattern.
8382 lowerVectorShuffleWithUNPCK(DL, MVT::v2f64, Mask, V1, V2, DAG))
8385 unsigned SHUFPDMask = (Mask[0] == 1) | (((Mask[1] - 2) == 1) << 1);
8386 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v2f64, V1, V2,
8387 DAG.getConstant(SHUFPDMask, DL, MVT::i8));
8390 /// \brief Handle lowering of 2-lane 64-bit integer shuffles.
8392 /// Tries to lower a 2-lane 64-bit shuffle using shuffle operations provided by
8393 /// the integer unit to minimize domain crossing penalties. However, for blends
8394 /// it falls back to the floating point shuffle operation with appropriate bit
8396 static SDValue lowerV2I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8397 const X86Subtarget *Subtarget,
8398 SelectionDAG &DAG) {
8400 assert(Op.getSimpleValueType() == MVT::v2i64 && "Bad shuffle type!");
8401 assert(V1.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
8402 assert(V2.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
8403 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8404 ArrayRef<int> Mask = SVOp->getMask();
8405 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
8407 if (isSingleInputShuffleMask(Mask)) {
8408 // Check for being able to broadcast a single element.
8409 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v2i64, V1,
8410 Mask, Subtarget, DAG))
8413 // Straight shuffle of a single input vector. For everything from SSE2
8414 // onward this has a single fast instruction with no scary immediates.
8415 // We have to map the mask as it is actually a v4i32 shuffle instruction.
8416 V1 = DAG.getBitcast(MVT::v4i32, V1);
8417 int WidenedMask[4] = {
8418 std::max(Mask[0], 0) * 2, std::max(Mask[0], 0) * 2 + 1,
8419 std::max(Mask[1], 0) * 2, std::max(Mask[1], 0) * 2 + 1};
8420 return DAG.getBitcast(
8422 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V1,
8423 getV4X86ShuffleImm8ForMask(WidenedMask, DL, DAG)));
8425 assert(Mask[0] != -1 && "No undef lanes in multi-input v2 shuffles!");
8426 assert(Mask[1] != -1 && "No undef lanes in multi-input v2 shuffles!");
8427 assert(Mask[0] < 2 && "We sort V1 to be the first input.");
8428 assert(Mask[1] >= 2 && "We sort V2 to be the second input.");
8430 // If we have a blend of two PACKUS operations an the blend aligns with the
8431 // low and half halves, we can just merge the PACKUS operations. This is
8432 // particularly important as it lets us merge shuffles that this routine itself
8434 auto GetPackNode = [](SDValue V) {
8435 while (V.getOpcode() == ISD::BITCAST)
8436 V = V.getOperand(0);
8438 return V.getOpcode() == X86ISD::PACKUS ? V : SDValue();
8440 if (SDValue V1Pack = GetPackNode(V1))
8441 if (SDValue V2Pack = GetPackNode(V2))
8442 return DAG.getBitcast(MVT::v2i64,
8443 DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8,
8444 Mask[0] == 0 ? V1Pack.getOperand(0)
8445 : V1Pack.getOperand(1),
8446 Mask[1] == 2 ? V2Pack.getOperand(0)
8447 : V2Pack.getOperand(1)));
8449 // Try to use shift instructions.
8451 lowerVectorShuffleAsShift(DL, MVT::v2i64, V1, V2, Mask, DAG))
8454 // When loading a scalar and then shuffling it into a vector we can often do
8455 // the insertion cheaply.
8456 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8457 DL, MVT::v2i64, V1, V2, Mask, Subtarget, DAG))
8459 // Try inverting the insertion since for v2 masks it is easy to do and we
8460 // can't reliably sort the mask one way or the other.
8461 int InverseMask[2] = {Mask[0] ^ 2, Mask[1] ^ 2};
8462 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8463 DL, MVT::v2i64, V2, V1, InverseMask, Subtarget, DAG))
8466 // We have different paths for blend lowering, but they all must use the
8467 // *exact* same predicate.
8468 bool IsBlendSupported = Subtarget->hasSSE41();
8469 if (IsBlendSupported)
8470 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v2i64, V1, V2, Mask,
8474 // Use dedicated unpack instructions for masks that match their pattern.
8476 lowerVectorShuffleWithUNPCK(DL, MVT::v2i64, Mask, V1, V2, DAG))
8479 // Try to use byte rotation instructions.
8480 // Its more profitable for pre-SSSE3 to use shuffles/unpacks.
8481 if (Subtarget->hasSSSE3())
8482 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8483 DL, MVT::v2i64, V1, V2, Mask, Subtarget, DAG))
8486 // If we have direct support for blends, we should lower by decomposing into
8487 // a permute. That will be faster than the domain cross.
8488 if (IsBlendSupported)
8489 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v2i64, V1, V2,
8492 // We implement this with SHUFPD which is pretty lame because it will likely
8493 // incur 2 cycles of stall for integer vectors on Nehalem and older chips.
8494 // However, all the alternatives are still more cycles and newer chips don't
8495 // have this problem. It would be really nice if x86 had better shuffles here.
8496 V1 = DAG.getBitcast(MVT::v2f64, V1);
8497 V2 = DAG.getBitcast(MVT::v2f64, V2);
8498 return DAG.getBitcast(MVT::v2i64,
8499 DAG.getVectorShuffle(MVT::v2f64, DL, V1, V2, Mask));
8502 /// \brief Test whether this can be lowered with a single SHUFPS instruction.
8504 /// This is used to disable more specialized lowerings when the shufps lowering
8505 /// will happen to be efficient.
8506 static bool isSingleSHUFPSMask(ArrayRef<int> Mask) {
8507 // This routine only handles 128-bit shufps.
8508 assert(Mask.size() == 4 && "Unsupported mask size!");
8510 // To lower with a single SHUFPS we need to have the low half and high half
8511 // each requiring a single input.
8512 if (Mask[0] != -1 && Mask[1] != -1 && (Mask[0] < 4) != (Mask[1] < 4))
8514 if (Mask[2] != -1 && Mask[3] != -1 && (Mask[2] < 4) != (Mask[3] < 4))
8520 /// \brief Lower a vector shuffle using the SHUFPS instruction.
8522 /// This is a helper routine dedicated to lowering vector shuffles using SHUFPS.
8523 /// It makes no assumptions about whether this is the *best* lowering, it simply
8525 static SDValue lowerVectorShuffleWithSHUFPS(SDLoc DL, MVT VT,
8526 ArrayRef<int> Mask, SDValue V1,
8527 SDValue V2, SelectionDAG &DAG) {
8528 SDValue LowV = V1, HighV = V2;
8529 int NewMask[4] = {Mask[0], Mask[1], Mask[2], Mask[3]};
8532 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
8534 if (NumV2Elements == 1) {
8536 std::find_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; }) -
8539 // Compute the index adjacent to V2Index and in the same half by toggling
8541 int V2AdjIndex = V2Index ^ 1;
8543 if (Mask[V2AdjIndex] == -1) {
8544 // Handles all the cases where we have a single V2 element and an undef.
8545 // This will only ever happen in the high lanes because we commute the
8546 // vector otherwise.
8548 std::swap(LowV, HighV);
8549 NewMask[V2Index] -= 4;
8551 // Handle the case where the V2 element ends up adjacent to a V1 element.
8552 // To make this work, blend them together as the first step.
8553 int V1Index = V2AdjIndex;
8554 int BlendMask[4] = {Mask[V2Index] - 4, 0, Mask[V1Index], 0};
8555 V2 = DAG.getNode(X86ISD::SHUFP, DL, VT, V2, V1,
8556 getV4X86ShuffleImm8ForMask(BlendMask, DL, DAG));
8558 // Now proceed to reconstruct the final blend as we have the necessary
8559 // high or low half formed.
8566 NewMask[V1Index] = 2; // We put the V1 element in V2[2].
8567 NewMask[V2Index] = 0; // We shifted the V2 element into V2[0].
8569 } else if (NumV2Elements == 2) {
8570 if (Mask[0] < 4 && Mask[1] < 4) {
8571 // Handle the easy case where we have V1 in the low lanes and V2 in the
8575 } else if (Mask[2] < 4 && Mask[3] < 4) {
8576 // We also handle the reversed case because this utility may get called
8577 // when we detect a SHUFPS pattern but can't easily commute the shuffle to
8578 // arrange things in the right direction.
8584 // We have a mixture of V1 and V2 in both low and high lanes. Rather than
8585 // trying to place elements directly, just blend them and set up the final
8586 // shuffle to place them.
8588 // The first two blend mask elements are for V1, the second two are for
8590 int BlendMask[4] = {Mask[0] < 4 ? Mask[0] : Mask[1],
8591 Mask[2] < 4 ? Mask[2] : Mask[3],
8592 (Mask[0] >= 4 ? Mask[0] : Mask[1]) - 4,
8593 (Mask[2] >= 4 ? Mask[2] : Mask[3]) - 4};
8594 V1 = DAG.getNode(X86ISD::SHUFP, DL, VT, V1, V2,
8595 getV4X86ShuffleImm8ForMask(BlendMask, DL, DAG));
8597 // Now we do a normal shuffle of V1 by giving V1 as both operands to
8600 NewMask[0] = Mask[0] < 4 ? 0 : 2;
8601 NewMask[1] = Mask[0] < 4 ? 2 : 0;
8602 NewMask[2] = Mask[2] < 4 ? 1 : 3;
8603 NewMask[3] = Mask[2] < 4 ? 3 : 1;
8606 return DAG.getNode(X86ISD::SHUFP, DL, VT, LowV, HighV,
8607 getV4X86ShuffleImm8ForMask(NewMask, DL, DAG));
8610 /// \brief Lower 4-lane 32-bit floating point shuffles.
8612 /// Uses instructions exclusively from the floating point unit to minimize
8613 /// domain crossing penalties, as these are sufficient to implement all v4f32
8615 static SDValue lowerV4F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8616 const X86Subtarget *Subtarget,
8617 SelectionDAG &DAG) {
8619 assert(Op.getSimpleValueType() == MVT::v4f32 && "Bad shuffle type!");
8620 assert(V1.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
8621 assert(V2.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
8622 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8623 ArrayRef<int> Mask = SVOp->getMask();
8624 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
8627 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
8629 if (NumV2Elements == 0) {
8630 // Check for being able to broadcast a single element.
8631 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v4f32, V1,
8632 Mask, Subtarget, DAG))
8635 // Use even/odd duplicate instructions for masks that match their pattern.
8636 if (Subtarget->hasSSE3()) {
8637 if (isShuffleEquivalent(V1, V2, Mask, {0, 0, 2, 2}))
8638 return DAG.getNode(X86ISD::MOVSLDUP, DL, MVT::v4f32, V1);
8639 if (isShuffleEquivalent(V1, V2, Mask, {1, 1, 3, 3}))
8640 return DAG.getNode(X86ISD::MOVSHDUP, DL, MVT::v4f32, V1);
8643 if (Subtarget->hasAVX()) {
8644 // If we have AVX, we can use VPERMILPS which will allow folding a load
8645 // into the shuffle.
8646 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v4f32, V1,
8647 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
8650 // Otherwise, use a straight shuffle of a single input vector. We pass the
8651 // input vector to both operands to simulate this with a SHUFPS.
8652 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f32, V1, V1,
8653 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
8656 // There are special ways we can lower some single-element blends. However, we
8657 // have custom ways we can lower more complex single-element blends below that
8658 // we defer to if both this and BLENDPS fail to match, so restrict this to
8659 // when the V2 input is targeting element 0 of the mask -- that is the fast
8661 if (NumV2Elements == 1 && Mask[0] >= 4)
8662 if (SDValue V = lowerVectorShuffleAsElementInsertion(DL, MVT::v4f32, V1, V2,
8663 Mask, Subtarget, DAG))
8666 if (Subtarget->hasSSE41()) {
8667 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4f32, V1, V2, Mask,
8671 // Use INSERTPS if we can complete the shuffle efficiently.
8672 if (SDValue V = lowerVectorShuffleAsInsertPS(Op, V1, V2, Mask, DAG))
8675 if (!isSingleSHUFPSMask(Mask))
8676 if (SDValue BlendPerm = lowerVectorShuffleAsBlendAndPermute(
8677 DL, MVT::v4f32, V1, V2, Mask, DAG))
8681 // Use dedicated unpack instructions for masks that match their pattern.
8683 lowerVectorShuffleWithUNPCK(DL, MVT::v4f32, Mask, V1, V2, DAG))
8686 // Otherwise fall back to a SHUFPS lowering strategy.
8687 return lowerVectorShuffleWithSHUFPS(DL, MVT::v4f32, Mask, V1, V2, DAG);
8690 /// \brief Lower 4-lane i32 vector shuffles.
8692 /// We try to handle these with integer-domain shuffles where we can, but for
8693 /// blends we use the floating point domain blend instructions.
8694 static SDValue lowerV4I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8695 const X86Subtarget *Subtarget,
8696 SelectionDAG &DAG) {
8698 assert(Op.getSimpleValueType() == MVT::v4i32 && "Bad shuffle type!");
8699 assert(V1.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
8700 assert(V2.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
8701 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8702 ArrayRef<int> Mask = SVOp->getMask();
8703 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
8705 // Whenever we can lower this as a zext, that instruction is strictly faster
8706 // than any alternative. It also allows us to fold memory operands into the
8707 // shuffle in many cases.
8708 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v4i32, V1, V2,
8709 Mask, Subtarget, DAG))
8713 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
8715 if (NumV2Elements == 0) {
8716 // Check for being able to broadcast a single element.
8717 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v4i32, V1,
8718 Mask, Subtarget, DAG))
8721 // Straight shuffle of a single input vector. For everything from SSE2
8722 // onward this has a single fast instruction with no scary immediates.
8723 // We coerce the shuffle pattern to be compatible with UNPCK instructions
8724 // but we aren't actually going to use the UNPCK instruction because doing
8725 // so prevents folding a load into this instruction or making a copy.
8726 const int UnpackLoMask[] = {0, 0, 1, 1};
8727 const int UnpackHiMask[] = {2, 2, 3, 3};
8728 if (isShuffleEquivalent(V1, V2, Mask, {0, 0, 1, 1}))
8729 Mask = UnpackLoMask;
8730 else if (isShuffleEquivalent(V1, V2, Mask, {2, 2, 3, 3}))
8731 Mask = UnpackHiMask;
8733 return DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V1,
8734 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
8737 // Try to use shift instructions.
8739 lowerVectorShuffleAsShift(DL, MVT::v4i32, V1, V2, Mask, DAG))
8742 // There are special ways we can lower some single-element blends.
8743 if (NumV2Elements == 1)
8744 if (SDValue V = lowerVectorShuffleAsElementInsertion(DL, MVT::v4i32, V1, V2,
8745 Mask, Subtarget, DAG))
8748 // We have different paths for blend lowering, but they all must use the
8749 // *exact* same predicate.
8750 bool IsBlendSupported = Subtarget->hasSSE41();
8751 if (IsBlendSupported)
8752 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4i32, V1, V2, Mask,
8756 if (SDValue Masked =
8757 lowerVectorShuffleAsBitMask(DL, MVT::v4i32, V1, V2, Mask, DAG))
8760 // Use dedicated unpack instructions for masks that match their pattern.
8762 lowerVectorShuffleWithUNPCK(DL, MVT::v4i32, Mask, V1, V2, DAG))
8765 // Try to use byte rotation instructions.
8766 // Its more profitable for pre-SSSE3 to use shuffles/unpacks.
8767 if (Subtarget->hasSSSE3())
8768 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8769 DL, MVT::v4i32, V1, V2, Mask, Subtarget, DAG))
8772 // If we have direct support for blends, we should lower by decomposing into
8773 // a permute. That will be faster than the domain cross.
8774 if (IsBlendSupported)
8775 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4i32, V1, V2,
8778 // Try to lower by permuting the inputs into an unpack instruction.
8779 if (SDValue Unpack = lowerVectorShuffleAsPermuteAndUnpack(DL, MVT::v4i32, V1,
8783 // We implement this with SHUFPS because it can blend from two vectors.
8784 // Because we're going to eventually use SHUFPS, we use SHUFPS even to build
8785 // up the inputs, bypassing domain shift penalties that we would encur if we
8786 // directly used PSHUFD on Nehalem and older. For newer chips, this isn't
8788 return DAG.getBitcast(
8790 DAG.getVectorShuffle(MVT::v4f32, DL, DAG.getBitcast(MVT::v4f32, V1),
8791 DAG.getBitcast(MVT::v4f32, V2), Mask));
8794 /// \brief Lowering of single-input v8i16 shuffles is the cornerstone of SSE2
8795 /// shuffle lowering, and the most complex part.
8797 /// The lowering strategy is to try to form pairs of input lanes which are
8798 /// targeted at the same half of the final vector, and then use a dword shuffle
8799 /// to place them onto the right half, and finally unpack the paired lanes into
8800 /// their final position.
8802 /// The exact breakdown of how to form these dword pairs and align them on the
8803 /// correct sides is really tricky. See the comments within the function for
8804 /// more of the details.
8806 /// This code also handles repeated 128-bit lanes of v8i16 shuffles, but each
8807 /// lane must shuffle the *exact* same way. In fact, you must pass a v8 Mask to
8808 /// this routine for it to work correctly. To shuffle a 256-bit or 512-bit i16
8809 /// vector, form the analogous 128-bit 8-element Mask.
8810 static SDValue lowerV8I16GeneralSingleInputVectorShuffle(
8811 SDLoc DL, MVT VT, SDValue V, MutableArrayRef<int> Mask,
8812 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
8813 assert(VT.getVectorElementType() == MVT::i16 && "Bad input type!");
8814 MVT PSHUFDVT = MVT::getVectorVT(MVT::i32, VT.getVectorNumElements() / 2);
8816 assert(Mask.size() == 8 && "Shuffle mask length doen't match!");
8817 MutableArrayRef<int> LoMask = Mask.slice(0, 4);
8818 MutableArrayRef<int> HiMask = Mask.slice(4, 4);
8820 SmallVector<int, 4> LoInputs;
8821 std::copy_if(LoMask.begin(), LoMask.end(), std::back_inserter(LoInputs),
8822 [](int M) { return M >= 0; });
8823 std::sort(LoInputs.begin(), LoInputs.end());
8824 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()), LoInputs.end());
8825 SmallVector<int, 4> HiInputs;
8826 std::copy_if(HiMask.begin(), HiMask.end(), std::back_inserter(HiInputs),
8827 [](int M) { return M >= 0; });
8828 std::sort(HiInputs.begin(), HiInputs.end());
8829 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()), HiInputs.end());
8831 std::lower_bound(LoInputs.begin(), LoInputs.end(), 4) - LoInputs.begin();
8832 int NumHToL = LoInputs.size() - NumLToL;
8834 std::lower_bound(HiInputs.begin(), HiInputs.end(), 4) - HiInputs.begin();
8835 int NumHToH = HiInputs.size() - NumLToH;
8836 MutableArrayRef<int> LToLInputs(LoInputs.data(), NumLToL);
8837 MutableArrayRef<int> LToHInputs(HiInputs.data(), NumLToH);
8838 MutableArrayRef<int> HToLInputs(LoInputs.data() + NumLToL, NumHToL);
8839 MutableArrayRef<int> HToHInputs(HiInputs.data() + NumLToH, NumHToH);
8841 // Simplify the 1-into-3 and 3-into-1 cases with a single pshufd. For all
8842 // such inputs we can swap two of the dwords across the half mark and end up
8843 // with <=2 inputs to each half in each half. Once there, we can fall through
8844 // to the generic code below. For example:
8846 // Input: [a, b, c, d, e, f, g, h] -PSHUFD[0,2,1,3]-> [a, b, e, f, c, d, g, h]
8847 // Mask: [0, 1, 2, 7, 4, 5, 6, 3] -----------------> [0, 1, 4, 7, 2, 3, 6, 5]
8849 // However in some very rare cases we have a 1-into-3 or 3-into-1 on one half
8850 // and an existing 2-into-2 on the other half. In this case we may have to
8851 // pre-shuffle the 2-into-2 half to avoid turning it into a 3-into-1 or
8852 // 1-into-3 which could cause us to cycle endlessly fixing each side in turn.
8853 // Fortunately, we don't have to handle anything but a 2-into-2 pattern
8854 // because any other situation (including a 3-into-1 or 1-into-3 in the other
8855 // half than the one we target for fixing) will be fixed when we re-enter this
8856 // path. We will also combine away any sequence of PSHUFD instructions that
8857 // result into a single instruction. Here is an example of the tricky case:
8859 // Input: [a, b, c, d, e, f, g, h] -PSHUFD[0,2,1,3]-> [a, b, e, f, c, d, g, h]
8860 // Mask: [3, 7, 1, 0, 2, 7, 3, 5] -THIS-IS-BAD!!!!-> [5, 7, 1, 0, 4, 7, 5, 3]
8862 // This now has a 1-into-3 in the high half! Instead, we do two shuffles:
8864 // Input: [a, b, c, d, e, f, g, h] PSHUFHW[0,2,1,3]-> [a, b, c, d, e, g, f, h]
8865 // Mask: [3, 7, 1, 0, 2, 7, 3, 5] -----------------> [3, 7, 1, 0, 2, 7, 3, 6]
8867 // Input: [a, b, c, d, e, g, f, h] -PSHUFD[0,2,1,3]-> [a, b, e, g, c, d, f, h]
8868 // Mask: [3, 7, 1, 0, 2, 7, 3, 6] -----------------> [5, 7, 1, 0, 4, 7, 5, 6]
8870 // The result is fine to be handled by the generic logic.
8871 auto balanceSides = [&](ArrayRef<int> AToAInputs, ArrayRef<int> BToAInputs,
8872 ArrayRef<int> BToBInputs, ArrayRef<int> AToBInputs,
8873 int AOffset, int BOffset) {
8874 assert((AToAInputs.size() == 3 || AToAInputs.size() == 1) &&
8875 "Must call this with A having 3 or 1 inputs from the A half.");
8876 assert((BToAInputs.size() == 1 || BToAInputs.size() == 3) &&
8877 "Must call this with B having 1 or 3 inputs from the B half.");
8878 assert(AToAInputs.size() + BToAInputs.size() == 4 &&
8879 "Must call this with either 3:1 or 1:3 inputs (summing to 4).");
8881 bool ThreeAInputs = AToAInputs.size() == 3;
8883 // Compute the index of dword with only one word among the three inputs in
8884 // a half by taking the sum of the half with three inputs and subtracting
8885 // the sum of the actual three inputs. The difference is the remaining
8888 int &TripleDWord = ThreeAInputs ? ADWord : BDWord;
8889 int &OneInputDWord = ThreeAInputs ? BDWord : ADWord;
8890 int TripleInputOffset = ThreeAInputs ? AOffset : BOffset;
8891 ArrayRef<int> TripleInputs = ThreeAInputs ? AToAInputs : BToAInputs;
8892 int OneInput = ThreeAInputs ? BToAInputs[0] : AToAInputs[0];
8893 int TripleInputSum = 0 + 1 + 2 + 3 + (4 * TripleInputOffset);
8894 int TripleNonInputIdx =
8895 TripleInputSum - std::accumulate(TripleInputs.begin(), TripleInputs.end(), 0);
8896 TripleDWord = TripleNonInputIdx / 2;
8898 // We use xor with one to compute the adjacent DWord to whichever one the
8900 OneInputDWord = (OneInput / 2) ^ 1;
8902 // Check for one tricky case: We're fixing a 3<-1 or a 1<-3 shuffle for AToA
8903 // and BToA inputs. If there is also such a problem with the BToB and AToB
8904 // inputs, we don't try to fix it necessarily -- we'll recurse and see it in
8905 // the next pass. However, if we have a 2<-2 in the BToB and AToB inputs, it
8906 // is essential that we don't *create* a 3<-1 as then we might oscillate.
8907 if (BToBInputs.size() == 2 && AToBInputs.size() == 2) {
8908 // Compute how many inputs will be flipped by swapping these DWords. We
8910 // to balance this to ensure we don't form a 3-1 shuffle in the other
8912 int NumFlippedAToBInputs =
8913 std::count(AToBInputs.begin(), AToBInputs.end(), 2 * ADWord) +
8914 std::count(AToBInputs.begin(), AToBInputs.end(), 2 * ADWord + 1);
8915 int NumFlippedBToBInputs =
8916 std::count(BToBInputs.begin(), BToBInputs.end(), 2 * BDWord) +
8917 std::count(BToBInputs.begin(), BToBInputs.end(), 2 * BDWord + 1);
8918 if ((NumFlippedAToBInputs == 1 &&
8919 (NumFlippedBToBInputs == 0 || NumFlippedBToBInputs == 2)) ||
8920 (NumFlippedBToBInputs == 1 &&
8921 (NumFlippedAToBInputs == 0 || NumFlippedAToBInputs == 2))) {
8922 // We choose whether to fix the A half or B half based on whether that
8923 // half has zero flipped inputs. At zero, we may not be able to fix it
8924 // with that half. We also bias towards fixing the B half because that
8925 // will more commonly be the high half, and we have to bias one way.
8926 auto FixFlippedInputs = [&V, &DL, &Mask, &DAG](int PinnedIdx, int DWord,
8927 ArrayRef<int> Inputs) {
8928 int FixIdx = PinnedIdx ^ 1; // The adjacent slot to the pinned slot.
8929 bool IsFixIdxInput = std::find(Inputs.begin(), Inputs.end(),
8930 PinnedIdx ^ 1) != Inputs.end();
8931 // Determine whether the free index is in the flipped dword or the
8932 // unflipped dword based on where the pinned index is. We use this bit
8933 // in an xor to conditionally select the adjacent dword.
8934 int FixFreeIdx = 2 * (DWord ^ (PinnedIdx / 2 == DWord));
8935 bool IsFixFreeIdxInput = std::find(Inputs.begin(), Inputs.end(),
8936 FixFreeIdx) != Inputs.end();
8937 if (IsFixIdxInput == IsFixFreeIdxInput)
8939 IsFixFreeIdxInput = std::find(Inputs.begin(), Inputs.end(),
8940 FixFreeIdx) != Inputs.end();
8941 assert(IsFixIdxInput != IsFixFreeIdxInput &&
8942 "We need to be changing the number of flipped inputs!");
8943 int PSHUFHalfMask[] = {0, 1, 2, 3};
8944 std::swap(PSHUFHalfMask[FixFreeIdx % 4], PSHUFHalfMask[FixIdx % 4]);
8945 V = DAG.getNode(FixIdx < 4 ? X86ISD::PSHUFLW : X86ISD::PSHUFHW, DL,
8947 getV4X86ShuffleImm8ForMask(PSHUFHalfMask, DL, DAG));
8950 if (M != -1 && M == FixIdx)
8952 else if (M != -1 && M == FixFreeIdx)
8955 if (NumFlippedBToBInputs != 0) {
8957 BToAInputs.size() == 3 ? TripleNonInputIdx : OneInput;
8958 FixFlippedInputs(BPinnedIdx, BDWord, BToBInputs);
8960 assert(NumFlippedAToBInputs != 0 && "Impossible given predicates!");
8961 int APinnedIdx = ThreeAInputs ? TripleNonInputIdx : OneInput;
8962 FixFlippedInputs(APinnedIdx, ADWord, AToBInputs);
8967 int PSHUFDMask[] = {0, 1, 2, 3};
8968 PSHUFDMask[ADWord] = BDWord;
8969 PSHUFDMask[BDWord] = ADWord;
8972 DAG.getNode(X86ISD::PSHUFD, DL, PSHUFDVT, DAG.getBitcast(PSHUFDVT, V),
8973 getV4X86ShuffleImm8ForMask(PSHUFDMask, DL, DAG)));
8975 // Adjust the mask to match the new locations of A and B.
8977 if (M != -1 && M/2 == ADWord)
8978 M = 2 * BDWord + M % 2;
8979 else if (M != -1 && M/2 == BDWord)
8980 M = 2 * ADWord + M % 2;
8982 // Recurse back into this routine to re-compute state now that this isn't
8983 // a 3 and 1 problem.
8984 return lowerV8I16GeneralSingleInputVectorShuffle(DL, VT, V, Mask, Subtarget,
8987 if ((NumLToL == 3 && NumHToL == 1) || (NumLToL == 1 && NumHToL == 3))
8988 return balanceSides(LToLInputs, HToLInputs, HToHInputs, LToHInputs, 0, 4);
8989 else if ((NumHToH == 3 && NumLToH == 1) || (NumHToH == 1 && NumLToH == 3))
8990 return balanceSides(HToHInputs, LToHInputs, LToLInputs, HToLInputs, 4, 0);
8992 // At this point there are at most two inputs to the low and high halves from
8993 // each half. That means the inputs can always be grouped into dwords and
8994 // those dwords can then be moved to the correct half with a dword shuffle.
8995 // We use at most one low and one high word shuffle to collect these paired
8996 // inputs into dwords, and finally a dword shuffle to place them.
8997 int PSHUFLMask[4] = {-1, -1, -1, -1};
8998 int PSHUFHMask[4] = {-1, -1, -1, -1};
8999 int PSHUFDMask[4] = {-1, -1, -1, -1};
9001 // First fix the masks for all the inputs that are staying in their
9002 // original halves. This will then dictate the targets of the cross-half
9004 auto fixInPlaceInputs =
9005 [&PSHUFDMask](ArrayRef<int> InPlaceInputs, ArrayRef<int> IncomingInputs,
9006 MutableArrayRef<int> SourceHalfMask,
9007 MutableArrayRef<int> HalfMask, int HalfOffset) {
9008 if (InPlaceInputs.empty())
9010 if (InPlaceInputs.size() == 1) {
9011 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
9012 InPlaceInputs[0] - HalfOffset;
9013 PSHUFDMask[InPlaceInputs[0] / 2] = InPlaceInputs[0] / 2;
9016 if (IncomingInputs.empty()) {
9017 // Just fix all of the in place inputs.
9018 for (int Input : InPlaceInputs) {
9019 SourceHalfMask[Input - HalfOffset] = Input - HalfOffset;
9020 PSHUFDMask[Input / 2] = Input / 2;
9025 assert(InPlaceInputs.size() == 2 && "Cannot handle 3 or 4 inputs!");
9026 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
9027 InPlaceInputs[0] - HalfOffset;
9028 // Put the second input next to the first so that they are packed into
9029 // a dword. We find the adjacent index by toggling the low bit.
9030 int AdjIndex = InPlaceInputs[0] ^ 1;
9031 SourceHalfMask[AdjIndex - HalfOffset] = InPlaceInputs[1] - HalfOffset;
9032 std::replace(HalfMask.begin(), HalfMask.end(), InPlaceInputs[1], AdjIndex);
9033 PSHUFDMask[AdjIndex / 2] = AdjIndex / 2;
9035 fixInPlaceInputs(LToLInputs, HToLInputs, PSHUFLMask, LoMask, 0);
9036 fixInPlaceInputs(HToHInputs, LToHInputs, PSHUFHMask, HiMask, 4);
9038 // Now gather the cross-half inputs and place them into a free dword of
9039 // their target half.
9040 // FIXME: This operation could almost certainly be simplified dramatically to
9041 // look more like the 3-1 fixing operation.
9042 auto moveInputsToRightHalf = [&PSHUFDMask](
9043 MutableArrayRef<int> IncomingInputs, ArrayRef<int> ExistingInputs,
9044 MutableArrayRef<int> SourceHalfMask, MutableArrayRef<int> HalfMask,
9045 MutableArrayRef<int> FinalSourceHalfMask, int SourceOffset,
9047 auto isWordClobbered = [](ArrayRef<int> SourceHalfMask, int Word) {
9048 return SourceHalfMask[Word] != -1 && SourceHalfMask[Word] != Word;
9050 auto isDWordClobbered = [&isWordClobbered](ArrayRef<int> SourceHalfMask,
9052 int LowWord = Word & ~1;
9053 int HighWord = Word | 1;
9054 return isWordClobbered(SourceHalfMask, LowWord) ||
9055 isWordClobbered(SourceHalfMask, HighWord);
9058 if (IncomingInputs.empty())
9061 if (ExistingInputs.empty()) {
9062 // Map any dwords with inputs from them into the right half.
9063 for (int Input : IncomingInputs) {
9064 // If the source half mask maps over the inputs, turn those into
9065 // swaps and use the swapped lane.
9066 if (isWordClobbered(SourceHalfMask, Input - SourceOffset)) {
9067 if (SourceHalfMask[SourceHalfMask[Input - SourceOffset]] == -1) {
9068 SourceHalfMask[SourceHalfMask[Input - SourceOffset]] =
9069 Input - SourceOffset;
9070 // We have to swap the uses in our half mask in one sweep.
9071 for (int &M : HalfMask)
9072 if (M == SourceHalfMask[Input - SourceOffset] + SourceOffset)
9074 else if (M == Input)
9075 M = SourceHalfMask[Input - SourceOffset] + SourceOffset;
9077 assert(SourceHalfMask[SourceHalfMask[Input - SourceOffset]] ==
9078 Input - SourceOffset &&
9079 "Previous placement doesn't match!");
9081 // Note that this correctly re-maps both when we do a swap and when
9082 // we observe the other side of the swap above. We rely on that to
9083 // avoid swapping the members of the input list directly.
9084 Input = SourceHalfMask[Input - SourceOffset] + SourceOffset;
9087 // Map the input's dword into the correct half.
9088 if (PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] == -1)
9089 PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] = Input / 2;
9091 assert(PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] ==
9093 "Previous placement doesn't match!");
9096 // And just directly shift any other-half mask elements to be same-half
9097 // as we will have mirrored the dword containing the element into the
9098 // same position within that half.
9099 for (int &M : HalfMask)
9100 if (M >= SourceOffset && M < SourceOffset + 4) {
9101 M = M - SourceOffset + DestOffset;
9102 assert(M >= 0 && "This should never wrap below zero!");
9107 // Ensure we have the input in a viable dword of its current half. This
9108 // is particularly tricky because the original position may be clobbered
9109 // by inputs being moved and *staying* in that half.
9110 if (IncomingInputs.size() == 1) {
9111 if (isWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
9112 int InputFixed = std::find(std::begin(SourceHalfMask),
9113 std::end(SourceHalfMask), -1) -
9114 std::begin(SourceHalfMask) + SourceOffset;
9115 SourceHalfMask[InputFixed - SourceOffset] =
9116 IncomingInputs[0] - SourceOffset;
9117 std::replace(HalfMask.begin(), HalfMask.end(), IncomingInputs[0],
9119 IncomingInputs[0] = InputFixed;
9121 } else if (IncomingInputs.size() == 2) {
9122 if (IncomingInputs[0] / 2 != IncomingInputs[1] / 2 ||
9123 isDWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
9124 // We have two non-adjacent or clobbered inputs we need to extract from
9125 // the source half. To do this, we need to map them into some adjacent
9126 // dword slot in the source mask.
9127 int InputsFixed[2] = {IncomingInputs[0] - SourceOffset,
9128 IncomingInputs[1] - SourceOffset};
9130 // If there is a free slot in the source half mask adjacent to one of
9131 // the inputs, place the other input in it. We use (Index XOR 1) to
9132 // compute an adjacent index.
9133 if (!isWordClobbered(SourceHalfMask, InputsFixed[0]) &&
9134 SourceHalfMask[InputsFixed[0] ^ 1] == -1) {
9135 SourceHalfMask[InputsFixed[0]] = InputsFixed[0];
9136 SourceHalfMask[InputsFixed[0] ^ 1] = InputsFixed[1];
9137 InputsFixed[1] = InputsFixed[0] ^ 1;
9138 } else if (!isWordClobbered(SourceHalfMask, InputsFixed[1]) &&
9139 SourceHalfMask[InputsFixed[1] ^ 1] == -1) {
9140 SourceHalfMask[InputsFixed[1]] = InputsFixed[1];
9141 SourceHalfMask[InputsFixed[1] ^ 1] = InputsFixed[0];
9142 InputsFixed[0] = InputsFixed[1] ^ 1;
9143 } else if (SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1)] == -1 &&
9144 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1) + 1] == -1) {
9145 // The two inputs are in the same DWord but it is clobbered and the
9146 // adjacent DWord isn't used at all. Move both inputs to the free
9148 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1)] = InputsFixed[0];
9149 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1) + 1] = InputsFixed[1];
9150 InputsFixed[0] = 2 * ((InputsFixed[0] / 2) ^ 1);
9151 InputsFixed[1] = 2 * ((InputsFixed[0] / 2) ^ 1) + 1;
9153 // The only way we hit this point is if there is no clobbering
9154 // (because there are no off-half inputs to this half) and there is no
9155 // free slot adjacent to one of the inputs. In this case, we have to
9156 // swap an input with a non-input.
9157 for (int i = 0; i < 4; ++i)
9158 assert((SourceHalfMask[i] == -1 || SourceHalfMask[i] == i) &&
9159 "We can't handle any clobbers here!");
9160 assert(InputsFixed[1] != (InputsFixed[0] ^ 1) &&
9161 "Cannot have adjacent inputs here!");
9163 SourceHalfMask[InputsFixed[0] ^ 1] = InputsFixed[1];
9164 SourceHalfMask[InputsFixed[1]] = InputsFixed[0] ^ 1;
9166 // We also have to update the final source mask in this case because
9167 // it may need to undo the above swap.
9168 for (int &M : FinalSourceHalfMask)
9169 if (M == (InputsFixed[0] ^ 1) + SourceOffset)
9170 M = InputsFixed[1] + SourceOffset;
9171 else if (M == InputsFixed[1] + SourceOffset)
9172 M = (InputsFixed[0] ^ 1) + SourceOffset;
9174 InputsFixed[1] = InputsFixed[0] ^ 1;
9177 // Point everything at the fixed inputs.
9178 for (int &M : HalfMask)
9179 if (M == IncomingInputs[0])
9180 M = InputsFixed[0] + SourceOffset;
9181 else if (M == IncomingInputs[1])
9182 M = InputsFixed[1] + SourceOffset;
9184 IncomingInputs[0] = InputsFixed[0] + SourceOffset;
9185 IncomingInputs[1] = InputsFixed[1] + SourceOffset;
9188 llvm_unreachable("Unhandled input size!");
9191 // Now hoist the DWord down to the right half.
9192 int FreeDWord = (PSHUFDMask[DestOffset / 2] == -1 ? 0 : 1) + DestOffset / 2;
9193 assert(PSHUFDMask[FreeDWord] == -1 && "DWord not free");
9194 PSHUFDMask[FreeDWord] = IncomingInputs[0] / 2;
9195 for (int &M : HalfMask)
9196 for (int Input : IncomingInputs)
9198 M = FreeDWord * 2 + Input % 2;
9200 moveInputsToRightHalf(HToLInputs, LToLInputs, PSHUFHMask, LoMask, HiMask,
9201 /*SourceOffset*/ 4, /*DestOffset*/ 0);
9202 moveInputsToRightHalf(LToHInputs, HToHInputs, PSHUFLMask, HiMask, LoMask,
9203 /*SourceOffset*/ 0, /*DestOffset*/ 4);
9205 // Now enact all the shuffles we've computed to move the inputs into their
9207 if (!isNoopShuffleMask(PSHUFLMask))
9208 V = DAG.getNode(X86ISD::PSHUFLW, DL, VT, V,
9209 getV4X86ShuffleImm8ForMask(PSHUFLMask, DL, DAG));
9210 if (!isNoopShuffleMask(PSHUFHMask))
9211 V = DAG.getNode(X86ISD::PSHUFHW, DL, VT, V,
9212 getV4X86ShuffleImm8ForMask(PSHUFHMask, DL, DAG));
9213 if (!isNoopShuffleMask(PSHUFDMask))
9216 DAG.getNode(X86ISD::PSHUFD, DL, PSHUFDVT, DAG.getBitcast(PSHUFDVT, V),
9217 getV4X86ShuffleImm8ForMask(PSHUFDMask, DL, DAG)));
9219 // At this point, each half should contain all its inputs, and we can then
9220 // just shuffle them into their final position.
9221 assert(std::count_if(LoMask.begin(), LoMask.end(),
9222 [](int M) { return M >= 4; }) == 0 &&
9223 "Failed to lift all the high half inputs to the low mask!");
9224 assert(std::count_if(HiMask.begin(), HiMask.end(),
9225 [](int M) { return M >= 0 && M < 4; }) == 0 &&
9226 "Failed to lift all the low half inputs to the high mask!");
9228 // Do a half shuffle for the low mask.
9229 if (!isNoopShuffleMask(LoMask))
9230 V = DAG.getNode(X86ISD::PSHUFLW, DL, VT, V,
9231 getV4X86ShuffleImm8ForMask(LoMask, DL, DAG));
9233 // Do a half shuffle with the high mask after shifting its values down.
9234 for (int &M : HiMask)
9237 if (!isNoopShuffleMask(HiMask))
9238 V = DAG.getNode(X86ISD::PSHUFHW, DL, VT, V,
9239 getV4X86ShuffleImm8ForMask(HiMask, DL, DAG));
9244 /// \brief Helper to form a PSHUFB-based shuffle+blend.
9245 static SDValue lowerVectorShuffleAsPSHUFB(SDLoc DL, MVT VT, SDValue V1,
9246 SDValue V2, ArrayRef<int> Mask,
9247 SelectionDAG &DAG, bool &V1InUse,
9249 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
9255 int Size = Mask.size();
9256 int Scale = 16 / Size;
9257 for (int i = 0; i < 16; ++i) {
9258 if (Mask[i / Scale] == -1) {
9259 V1Mask[i] = V2Mask[i] = DAG.getUNDEF(MVT::i8);
9261 const int ZeroMask = 0x80;
9262 int V1Idx = Mask[i / Scale] < Size ? Mask[i / Scale] * Scale + i % Scale
9264 int V2Idx = Mask[i / Scale] < Size
9266 : (Mask[i / Scale] - Size) * Scale + i % Scale;
9267 if (Zeroable[i / Scale])
9268 V1Idx = V2Idx = ZeroMask;
9269 V1Mask[i] = DAG.getConstant(V1Idx, DL, MVT::i8);
9270 V2Mask[i] = DAG.getConstant(V2Idx, DL, MVT::i8);
9271 V1InUse |= (ZeroMask != V1Idx);
9272 V2InUse |= (ZeroMask != V2Idx);
9277 V1 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8,
9278 DAG.getBitcast(MVT::v16i8, V1),
9279 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V1Mask));
9281 V2 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8,
9282 DAG.getBitcast(MVT::v16i8, V2),
9283 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V2Mask));
9285 // If we need shuffled inputs from both, blend the two.
9287 if (V1InUse && V2InUse)
9288 V = DAG.getNode(ISD::OR, DL, MVT::v16i8, V1, V2);
9290 V = V1InUse ? V1 : V2;
9292 // Cast the result back to the correct type.
9293 return DAG.getBitcast(VT, V);
9296 /// \brief Generic lowering of 8-lane i16 shuffles.
9298 /// This handles both single-input shuffles and combined shuffle/blends with
9299 /// two inputs. The single input shuffles are immediately delegated to
9300 /// a dedicated lowering routine.
9302 /// The blends are lowered in one of three fundamental ways. If there are few
9303 /// enough inputs, it delegates to a basic UNPCK-based strategy. If the shuffle
9304 /// of the input is significantly cheaper when lowered as an interleaving of
9305 /// the two inputs, try to interleave them. Otherwise, blend the low and high
9306 /// halves of the inputs separately (making them have relatively few inputs)
9307 /// and then concatenate them.
9308 static SDValue lowerV8I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9309 const X86Subtarget *Subtarget,
9310 SelectionDAG &DAG) {
9312 assert(Op.getSimpleValueType() == MVT::v8i16 && "Bad shuffle type!");
9313 assert(V1.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
9314 assert(V2.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
9315 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9316 ArrayRef<int> OrigMask = SVOp->getMask();
9317 int MaskStorage[8] = {OrigMask[0], OrigMask[1], OrigMask[2], OrigMask[3],
9318 OrigMask[4], OrigMask[5], OrigMask[6], OrigMask[7]};
9319 MutableArrayRef<int> Mask(MaskStorage);
9321 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
9323 // Whenever we can lower this as a zext, that instruction is strictly faster
9324 // than any alternative.
9325 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(
9326 DL, MVT::v8i16, V1, V2, OrigMask, Subtarget, DAG))
9329 auto isV1 = [](int M) { return M >= 0 && M < 8; };
9331 auto isV2 = [](int M) { return M >= 8; };
9333 int NumV2Inputs = std::count_if(Mask.begin(), Mask.end(), isV2);
9335 if (NumV2Inputs == 0) {
9336 // Check for being able to broadcast a single element.
9337 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v8i16, V1,
9338 Mask, Subtarget, DAG))
9341 // Try to use shift instructions.
9343 lowerVectorShuffleAsShift(DL, MVT::v8i16, V1, V1, Mask, DAG))
9346 // Use dedicated unpack instructions for masks that match their pattern.
9348 lowerVectorShuffleWithUNPCK(DL, MVT::v8i16, Mask, V1, V2, DAG))
9351 // Try to use byte rotation instructions.
9352 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(DL, MVT::v8i16, V1, V1,
9353 Mask, Subtarget, DAG))
9356 return lowerV8I16GeneralSingleInputVectorShuffle(DL, MVT::v8i16, V1, Mask,
9360 assert(std::any_of(Mask.begin(), Mask.end(), isV1) &&
9361 "All single-input shuffles should be canonicalized to be V1-input "
9364 // Try to use shift instructions.
9366 lowerVectorShuffleAsShift(DL, MVT::v8i16, V1, V2, Mask, DAG))
9369 // See if we can use SSE4A Extraction / Insertion.
9370 if (Subtarget->hasSSE4A())
9371 if (SDValue V = lowerVectorShuffleWithSSE4A(DL, MVT::v8i16, V1, V2, Mask, DAG))
9374 // There are special ways we can lower some single-element blends.
9375 if (NumV2Inputs == 1)
9376 if (SDValue V = lowerVectorShuffleAsElementInsertion(DL, MVT::v8i16, V1, V2,
9377 Mask, Subtarget, DAG))
9380 // We have different paths for blend lowering, but they all must use the
9381 // *exact* same predicate.
9382 bool IsBlendSupported = Subtarget->hasSSE41();
9383 if (IsBlendSupported)
9384 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8i16, V1, V2, Mask,
9388 if (SDValue Masked =
9389 lowerVectorShuffleAsBitMask(DL, MVT::v8i16, V1, V2, Mask, DAG))
9392 // Use dedicated unpack instructions for masks that match their pattern.
9394 lowerVectorShuffleWithUNPCK(DL, MVT::v8i16, Mask, V1, V2, DAG))
9397 // Try to use byte rotation instructions.
9398 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
9399 DL, MVT::v8i16, V1, V2, Mask, Subtarget, DAG))
9402 if (SDValue BitBlend =
9403 lowerVectorShuffleAsBitBlend(DL, MVT::v8i16, V1, V2, Mask, DAG))
9406 if (SDValue Unpack = lowerVectorShuffleAsPermuteAndUnpack(DL, MVT::v8i16, V1,
9410 // If we can't directly blend but can use PSHUFB, that will be better as it
9411 // can both shuffle and set up the inefficient blend.
9412 if (!IsBlendSupported && Subtarget->hasSSSE3()) {
9413 bool V1InUse, V2InUse;
9414 return lowerVectorShuffleAsPSHUFB(DL, MVT::v8i16, V1, V2, Mask, DAG,
9418 // We can always bit-blend if we have to so the fallback strategy is to
9419 // decompose into single-input permutes and blends.
9420 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8i16, V1, V2,
9424 /// \brief Check whether a compaction lowering can be done by dropping even
9425 /// elements and compute how many times even elements must be dropped.
9427 /// This handles shuffles which take every Nth element where N is a power of
9428 /// two. Example shuffle masks:
9430 /// N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 0, 2, 4, 6, 8, 10, 12, 14
9431 /// N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30
9432 /// N = 2: 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12
9433 /// N = 2: 0, 4, 8, 12, 16, 20, 24, 28, 0, 4, 8, 12, 16, 20, 24, 28
9434 /// N = 3: 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8
9435 /// N = 3: 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24
9437 /// Any of these lanes can of course be undef.
9439 /// This routine only supports N <= 3.
9440 /// FIXME: Evaluate whether either AVX or AVX-512 have any opportunities here
9443 /// \returns N above, or the number of times even elements must be dropped if
9444 /// there is such a number. Otherwise returns zero.
9445 static int canLowerByDroppingEvenElements(ArrayRef<int> Mask) {
9446 // Figure out whether we're looping over two inputs or just one.
9447 bool IsSingleInput = isSingleInputShuffleMask(Mask);
9449 // The modulus for the shuffle vector entries is based on whether this is
9450 // a single input or not.
9451 int ShuffleModulus = Mask.size() * (IsSingleInput ? 1 : 2);
9452 assert(isPowerOf2_32((uint32_t)ShuffleModulus) &&
9453 "We should only be called with masks with a power-of-2 size!");
9455 uint64_t ModMask = (uint64_t)ShuffleModulus - 1;
9457 // We track whether the input is viable for all power-of-2 strides 2^1, 2^2,
9458 // and 2^3 simultaneously. This is because we may have ambiguity with
9459 // partially undef inputs.
9460 bool ViableForN[3] = {true, true, true};
9462 for (int i = 0, e = Mask.size(); i < e; ++i) {
9463 // Ignore undef lanes, we'll optimistically collapse them to the pattern we
9468 bool IsAnyViable = false;
9469 for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
9470 if (ViableForN[j]) {
9473 // The shuffle mask must be equal to (i * 2^N) % M.
9474 if ((uint64_t)Mask[i] == (((uint64_t)i << N) & ModMask))
9477 ViableForN[j] = false;
9479 // Early exit if we exhaust the possible powers of two.
9484 for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
9488 // Return 0 as there is no viable power of two.
9492 /// \brief Generic lowering of v16i8 shuffles.
9494 /// This is a hybrid strategy to lower v16i8 vectors. It first attempts to
9495 /// detect any complexity reducing interleaving. If that doesn't help, it uses
9496 /// UNPCK to spread the i8 elements across two i16-element vectors, and uses
9497 /// the existing lowering for v8i16 blends on each half, finally PACK-ing them
9499 static SDValue lowerV16I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9500 const X86Subtarget *Subtarget,
9501 SelectionDAG &DAG) {
9503 assert(Op.getSimpleValueType() == MVT::v16i8 && "Bad shuffle type!");
9504 assert(V1.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
9505 assert(V2.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
9506 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9507 ArrayRef<int> Mask = SVOp->getMask();
9508 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
9510 // Try to use shift instructions.
9512 lowerVectorShuffleAsShift(DL, MVT::v16i8, V1, V2, Mask, DAG))
9515 // Try to use byte rotation instructions.
9516 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
9517 DL, MVT::v16i8, V1, V2, Mask, Subtarget, DAG))
9520 // Try to use a zext lowering.
9521 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(
9522 DL, MVT::v16i8, V1, V2, Mask, Subtarget, DAG))
9525 // See if we can use SSE4A Extraction / Insertion.
9526 if (Subtarget->hasSSE4A())
9527 if (SDValue V = lowerVectorShuffleWithSSE4A(DL, MVT::v16i8, V1, V2, Mask, DAG))
9531 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 16; });
9533 // For single-input shuffles, there are some nicer lowering tricks we can use.
9534 if (NumV2Elements == 0) {
9535 // Check for being able to broadcast a single element.
9536 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v16i8, V1,
9537 Mask, Subtarget, DAG))
9540 // Check whether we can widen this to an i16 shuffle by duplicating bytes.
9541 // Notably, this handles splat and partial-splat shuffles more efficiently.
9542 // However, it only makes sense if the pre-duplication shuffle simplifies
9543 // things significantly. Currently, this means we need to be able to
9544 // express the pre-duplication shuffle as an i16 shuffle.
9546 // FIXME: We should check for other patterns which can be widened into an
9547 // i16 shuffle as well.
9548 auto canWidenViaDuplication = [](ArrayRef<int> Mask) {
9549 for (int i = 0; i < 16; i += 2)
9550 if (Mask[i] != -1 && Mask[i + 1] != -1 && Mask[i] != Mask[i + 1])
9555 auto tryToWidenViaDuplication = [&]() -> SDValue {
9556 if (!canWidenViaDuplication(Mask))
9558 SmallVector<int, 4> LoInputs;
9559 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(LoInputs),
9560 [](int M) { return M >= 0 && M < 8; });
9561 std::sort(LoInputs.begin(), LoInputs.end());
9562 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()),
9564 SmallVector<int, 4> HiInputs;
9565 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(HiInputs),
9566 [](int M) { return M >= 8; });
9567 std::sort(HiInputs.begin(), HiInputs.end());
9568 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()),
9571 bool TargetLo = LoInputs.size() >= HiInputs.size();
9572 ArrayRef<int> InPlaceInputs = TargetLo ? LoInputs : HiInputs;
9573 ArrayRef<int> MovingInputs = TargetLo ? HiInputs : LoInputs;
9575 int PreDupI16Shuffle[] = {-1, -1, -1, -1, -1, -1, -1, -1};
9576 SmallDenseMap<int, int, 8> LaneMap;
9577 for (int I : InPlaceInputs) {
9578 PreDupI16Shuffle[I/2] = I/2;
9581 int j = TargetLo ? 0 : 4, je = j + 4;
9582 for (int i = 0, ie = MovingInputs.size(); i < ie; ++i) {
9583 // Check if j is already a shuffle of this input. This happens when
9584 // there are two adjacent bytes after we move the low one.
9585 if (PreDupI16Shuffle[j] != MovingInputs[i] / 2) {
9586 // If we haven't yet mapped the input, search for a slot into which
9588 while (j < je && PreDupI16Shuffle[j] != -1)
9592 // We can't place the inputs into a single half with a simple i16 shuffle, so bail.
9595 // Map this input with the i16 shuffle.
9596 PreDupI16Shuffle[j] = MovingInputs[i] / 2;
9599 // Update the lane map based on the mapping we ended up with.
9600 LaneMap[MovingInputs[i]] = 2 * j + MovingInputs[i] % 2;
9602 V1 = DAG.getBitcast(
9604 DAG.getVectorShuffle(MVT::v8i16, DL, DAG.getBitcast(MVT::v8i16, V1),
9605 DAG.getUNDEF(MVT::v8i16), PreDupI16Shuffle));
9607 // Unpack the bytes to form the i16s that will be shuffled into place.
9608 V1 = DAG.getNode(TargetLo ? X86ISD::UNPCKL : X86ISD::UNPCKH, DL,
9609 MVT::v16i8, V1, V1);
9611 int PostDupI16Shuffle[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9612 for (int i = 0; i < 16; ++i)
9613 if (Mask[i] != -1) {
9614 int MappedMask = LaneMap[Mask[i]] - (TargetLo ? 0 : 8);
9615 assert(MappedMask < 8 && "Invalid v8 shuffle mask!");
9616 if (PostDupI16Shuffle[i / 2] == -1)
9617 PostDupI16Shuffle[i / 2] = MappedMask;
9619 assert(PostDupI16Shuffle[i / 2] == MappedMask &&
9620 "Conflicting entrties in the original shuffle!");
9622 return DAG.getBitcast(
9624 DAG.getVectorShuffle(MVT::v8i16, DL, DAG.getBitcast(MVT::v8i16, V1),
9625 DAG.getUNDEF(MVT::v8i16), PostDupI16Shuffle));
9627 if (SDValue V = tryToWidenViaDuplication())
9631 if (SDValue Masked =
9632 lowerVectorShuffleAsBitMask(DL, MVT::v16i8, V1, V2, Mask, DAG))
9635 // Use dedicated unpack instructions for masks that match their pattern.
9637 lowerVectorShuffleWithUNPCK(DL, MVT::v16i8, Mask, V1, V2, DAG))
9640 // Check for SSSE3 which lets us lower all v16i8 shuffles much more directly
9641 // with PSHUFB. It is important to do this before we attempt to generate any
9642 // blends but after all of the single-input lowerings. If the single input
9643 // lowerings can find an instruction sequence that is faster than a PSHUFB, we
9644 // want to preserve that and we can DAG combine any longer sequences into
9645 // a PSHUFB in the end. But once we start blending from multiple inputs,
9646 // the complexity of DAG combining bad patterns back into PSHUFB is too high,
9647 // and there are *very* few patterns that would actually be faster than the
9648 // PSHUFB approach because of its ability to zero lanes.
9650 // FIXME: The only exceptions to the above are blends which are exact
9651 // interleavings with direct instructions supporting them. We currently don't
9652 // handle those well here.
9653 if (Subtarget->hasSSSE3()) {
9654 bool V1InUse = false;
9655 bool V2InUse = false;
9657 SDValue PSHUFB = lowerVectorShuffleAsPSHUFB(DL, MVT::v16i8, V1, V2, Mask,
9658 DAG, V1InUse, V2InUse);
9660 // If both V1 and V2 are in use and we can use a direct blend or an unpack,
9661 // do so. This avoids using them to handle blends-with-zero which is
9662 // important as a single pshufb is significantly faster for that.
9663 if (V1InUse && V2InUse) {
9664 if (Subtarget->hasSSE41())
9665 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v16i8, V1, V2,
9666 Mask, Subtarget, DAG))
9669 // We can use an unpack to do the blending rather than an or in some
9670 // cases. Even though the or may be (very minorly) more efficient, we
9671 // preference this lowering because there are common cases where part of
9672 // the complexity of the shuffles goes away when we do the final blend as
9674 // FIXME: It might be worth trying to detect if the unpack-feeding
9675 // shuffles will both be pshufb, in which case we shouldn't bother with
9677 if (SDValue Unpack = lowerVectorShuffleAsPermuteAndUnpack(
9678 DL, MVT::v16i8, V1, V2, Mask, DAG))
9685 // There are special ways we can lower some single-element blends.
9686 if (NumV2Elements == 1)
9687 if (SDValue V = lowerVectorShuffleAsElementInsertion(DL, MVT::v16i8, V1, V2,
9688 Mask, Subtarget, DAG))
9691 if (SDValue BitBlend =
9692 lowerVectorShuffleAsBitBlend(DL, MVT::v16i8, V1, V2, Mask, DAG))
9695 // Check whether a compaction lowering can be done. This handles shuffles
9696 // which take every Nth element for some even N. See the helper function for
9699 // We special case these as they can be particularly efficiently handled with
9700 // the PACKUSB instruction on x86 and they show up in common patterns of
9701 // rearranging bytes to truncate wide elements.
9702 if (int NumEvenDrops = canLowerByDroppingEvenElements(Mask)) {
9703 // NumEvenDrops is the power of two stride of the elements. Another way of
9704 // thinking about it is that we need to drop the even elements this many
9705 // times to get the original input.
9706 bool IsSingleInput = isSingleInputShuffleMask(Mask);
9708 // First we need to zero all the dropped bytes.
9709 assert(NumEvenDrops <= 3 &&
9710 "No support for dropping even elements more than 3 times.");
9711 // We use the mask type to pick which bytes are preserved based on how many
9712 // elements are dropped.
9713 MVT MaskVTs[] = { MVT::v8i16, MVT::v4i32, MVT::v2i64 };
9714 SDValue ByteClearMask = DAG.getBitcast(
9715 MVT::v16i8, DAG.getConstant(0xFF, DL, MaskVTs[NumEvenDrops - 1]));
9716 V1 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V1, ByteClearMask);
9718 V2 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V2, ByteClearMask);
9720 // Now pack things back together.
9721 V1 = DAG.getBitcast(MVT::v8i16, V1);
9722 V2 = IsSingleInput ? V1 : DAG.getBitcast(MVT::v8i16, V2);
9723 SDValue Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, V1, V2);
9724 for (int i = 1; i < NumEvenDrops; ++i) {
9725 Result = DAG.getBitcast(MVT::v8i16, Result);
9726 Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, Result, Result);
9732 // Handle multi-input cases by blending single-input shuffles.
9733 if (NumV2Elements > 0)
9734 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v16i8, V1, V2,
9737 // The fallback path for single-input shuffles widens this into two v8i16
9738 // vectors with unpacks, shuffles those, and then pulls them back together
9742 int LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9743 int HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9744 for (int i = 0; i < 16; ++i)
9746 (i < 8 ? LoBlendMask[i] : HiBlendMask[i % 8]) = Mask[i];
9748 SDValue Zero = getZeroVector(MVT::v8i16, Subtarget, DAG, DL);
9750 SDValue VLoHalf, VHiHalf;
9751 // Check if any of the odd lanes in the v16i8 are used. If not, we can mask
9752 // them out and avoid using UNPCK{L,H} to extract the elements of V as
9754 if (std::none_of(std::begin(LoBlendMask), std::end(LoBlendMask),
9755 [](int M) { return M >= 0 && M % 2 == 1; }) &&
9756 std::none_of(std::begin(HiBlendMask), std::end(HiBlendMask),
9757 [](int M) { return M >= 0 && M % 2 == 1; })) {
9758 // Use a mask to drop the high bytes.
9759 VLoHalf = DAG.getBitcast(MVT::v8i16, V);
9760 VLoHalf = DAG.getNode(ISD::AND, DL, MVT::v8i16, VLoHalf,
9761 DAG.getConstant(0x00FF, DL, MVT::v8i16));
9763 // This will be a single vector shuffle instead of a blend so nuke VHiHalf.
9764 VHiHalf = DAG.getUNDEF(MVT::v8i16);
9766 // Squash the masks to point directly into VLoHalf.
9767 for (int &M : LoBlendMask)
9770 for (int &M : HiBlendMask)
9774 // Otherwise just unpack the low half of V into VLoHalf and the high half into
9775 // VHiHalf so that we can blend them as i16s.
9776 VLoHalf = DAG.getBitcast(
9777 MVT::v8i16, DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i8, V, Zero));
9778 VHiHalf = DAG.getBitcast(
9779 MVT::v8i16, DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i8, V, Zero));
9782 SDValue LoV = DAG.getVectorShuffle(MVT::v8i16, DL, VLoHalf, VHiHalf, LoBlendMask);
9783 SDValue HiV = DAG.getVectorShuffle(MVT::v8i16, DL, VLoHalf, VHiHalf, HiBlendMask);
9785 return DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, LoV, HiV);
9788 /// \brief Dispatching routine to lower various 128-bit x86 vector shuffles.
9790 /// This routine breaks down the specific type of 128-bit shuffle and
9791 /// dispatches to the lowering routines accordingly.
9792 static SDValue lower128BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9793 MVT VT, const X86Subtarget *Subtarget,
9794 SelectionDAG &DAG) {
9795 switch (VT.SimpleTy) {
9797 return lowerV2I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9799 return lowerV2F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9801 return lowerV4I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9803 return lowerV4F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9805 return lowerV8I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
9807 return lowerV16I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
9810 llvm_unreachable("Unimplemented!");
9814 /// \brief Helper function to test whether a shuffle mask could be
9815 /// simplified by widening the elements being shuffled.
9817 /// Appends the mask for wider elements in WidenedMask if valid. Otherwise
9818 /// leaves it in an unspecified state.
9820 /// NOTE: This must handle normal vector shuffle masks and *target* vector
9821 /// shuffle masks. The latter have the special property of a '-2' representing
9822 /// a zero-ed lane of a vector.
9823 static bool canWidenShuffleElements(ArrayRef<int> Mask,
9824 SmallVectorImpl<int> &WidenedMask) {
9825 for (int i = 0, Size = Mask.size(); i < Size; i += 2) {
9826 // If both elements are undef, its trivial.
9827 if (Mask[i] == SM_SentinelUndef && Mask[i + 1] == SM_SentinelUndef) {
9828 WidenedMask.push_back(SM_SentinelUndef);
9832 // Check for an undef mask and a mask value properly aligned to fit with
9833 // a pair of values. If we find such a case, use the non-undef mask's value.
9834 if (Mask[i] == SM_SentinelUndef && Mask[i + 1] >= 0 && Mask[i + 1] % 2 == 1) {
9835 WidenedMask.push_back(Mask[i + 1] / 2);
9838 if (Mask[i + 1] == SM_SentinelUndef && Mask[i] >= 0 && Mask[i] % 2 == 0) {
9839 WidenedMask.push_back(Mask[i] / 2);
9843 // When zeroing, we need to spread the zeroing across both lanes to widen.
9844 if (Mask[i] == SM_SentinelZero || Mask[i + 1] == SM_SentinelZero) {
9845 if ((Mask[i] == SM_SentinelZero || Mask[i] == SM_SentinelUndef) &&
9846 (Mask[i + 1] == SM_SentinelZero || Mask[i + 1] == SM_SentinelUndef)) {
9847 WidenedMask.push_back(SM_SentinelZero);
9853 // Finally check if the two mask values are adjacent and aligned with
9855 if (Mask[i] != SM_SentinelUndef && Mask[i] % 2 == 0 && Mask[i] + 1 == Mask[i + 1]) {
9856 WidenedMask.push_back(Mask[i] / 2);
9860 // Otherwise we can't safely widen the elements used in this shuffle.
9863 assert(WidenedMask.size() == Mask.size() / 2 &&
9864 "Incorrect size of mask after widening the elements!");
9869 /// \brief Generic routine to split vector shuffle into half-sized shuffles.
9871 /// This routine just extracts two subvectors, shuffles them independently, and
9872 /// then concatenates them back together. This should work effectively with all
9873 /// AVX vector shuffle types.
9874 static SDValue splitAndLowerVectorShuffle(SDLoc DL, MVT VT, SDValue V1,
9875 SDValue V2, ArrayRef<int> Mask,
9876 SelectionDAG &DAG) {
9877 assert(VT.getSizeInBits() >= 256 &&
9878 "Only for 256-bit or wider vector shuffles!");
9879 assert(V1.getSimpleValueType() == VT && "Bad operand type!");
9880 assert(V2.getSimpleValueType() == VT && "Bad operand type!");
9882 ArrayRef<int> LoMask = Mask.slice(0, Mask.size() / 2);
9883 ArrayRef<int> HiMask = Mask.slice(Mask.size() / 2);
9885 int NumElements = VT.getVectorNumElements();
9886 int SplitNumElements = NumElements / 2;
9887 MVT ScalarVT = VT.getVectorElementType();
9888 MVT SplitVT = MVT::getVectorVT(ScalarVT, NumElements / 2);
9890 // Rather than splitting build-vectors, just build two narrower build
9891 // vectors. This helps shuffling with splats and zeros.
9892 auto SplitVector = [&](SDValue V) {
9893 while (V.getOpcode() == ISD::BITCAST)
9894 V = V->getOperand(0);
9896 MVT OrigVT = V.getSimpleValueType();
9897 int OrigNumElements = OrigVT.getVectorNumElements();
9898 int OrigSplitNumElements = OrigNumElements / 2;
9899 MVT OrigScalarVT = OrigVT.getVectorElementType();
9900 MVT OrigSplitVT = MVT::getVectorVT(OrigScalarVT, OrigNumElements / 2);
9904 auto *BV = dyn_cast<BuildVectorSDNode>(V);
9906 LoV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, OrigSplitVT, V,
9907 DAG.getIntPtrConstant(0, DL));
9908 HiV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, OrigSplitVT, V,
9909 DAG.getIntPtrConstant(OrigSplitNumElements, DL));
9912 SmallVector<SDValue, 16> LoOps, HiOps;
9913 for (int i = 0; i < OrigSplitNumElements; ++i) {
9914 LoOps.push_back(BV->getOperand(i));
9915 HiOps.push_back(BV->getOperand(i + OrigSplitNumElements));
9917 LoV = DAG.getNode(ISD::BUILD_VECTOR, DL, OrigSplitVT, LoOps);
9918 HiV = DAG.getNode(ISD::BUILD_VECTOR, DL, OrigSplitVT, HiOps);
9920 return std::make_pair(DAG.getBitcast(SplitVT, LoV),
9921 DAG.getBitcast(SplitVT, HiV));
9924 SDValue LoV1, HiV1, LoV2, HiV2;
9925 std::tie(LoV1, HiV1) = SplitVector(V1);
9926 std::tie(LoV2, HiV2) = SplitVector(V2);
9928 // Now create two 4-way blends of these half-width vectors.
9929 auto HalfBlend = [&](ArrayRef<int> HalfMask) {
9930 bool UseLoV1 = false, UseHiV1 = false, UseLoV2 = false, UseHiV2 = false;
9931 SmallVector<int, 32> V1BlendMask, V2BlendMask, BlendMask;
9932 for (int i = 0; i < SplitNumElements; ++i) {
9933 int M = HalfMask[i];
9934 if (M >= NumElements) {
9935 if (M >= NumElements + SplitNumElements)
9939 V2BlendMask.push_back(M - NumElements);
9940 V1BlendMask.push_back(-1);
9941 BlendMask.push_back(SplitNumElements + i);
9942 } else if (M >= 0) {
9943 if (M >= SplitNumElements)
9947 V2BlendMask.push_back(-1);
9948 V1BlendMask.push_back(M);
9949 BlendMask.push_back(i);
9951 V2BlendMask.push_back(-1);
9952 V1BlendMask.push_back(-1);
9953 BlendMask.push_back(-1);
9957 // Because the lowering happens after all combining takes place, we need to
9958 // manually combine these blend masks as much as possible so that we create
9959 // a minimal number of high-level vector shuffle nodes.
9961 // First try just blending the halves of V1 or V2.
9962 if (!UseLoV1 && !UseHiV1 && !UseLoV2 && !UseHiV2)
9963 return DAG.getUNDEF(SplitVT);
9964 if (!UseLoV2 && !UseHiV2)
9965 return DAG.getVectorShuffle(SplitVT, DL, LoV1, HiV1, V1BlendMask);
9966 if (!UseLoV1 && !UseHiV1)
9967 return DAG.getVectorShuffle(SplitVT, DL, LoV2, HiV2, V2BlendMask);
9969 SDValue V1Blend, V2Blend;
9970 if (UseLoV1 && UseHiV1) {
9972 DAG.getVectorShuffle(SplitVT, DL, LoV1, HiV1, V1BlendMask);
9974 // We only use half of V1 so map the usage down into the final blend mask.
9975 V1Blend = UseLoV1 ? LoV1 : HiV1;
9976 for (int i = 0; i < SplitNumElements; ++i)
9977 if (BlendMask[i] >= 0 && BlendMask[i] < SplitNumElements)
9978 BlendMask[i] = V1BlendMask[i] - (UseLoV1 ? 0 : SplitNumElements);
9980 if (UseLoV2 && UseHiV2) {
9982 DAG.getVectorShuffle(SplitVT, DL, LoV2, HiV2, V2BlendMask);
9984 // We only use half of V2 so map the usage down into the final blend mask.
9985 V2Blend = UseLoV2 ? LoV2 : HiV2;
9986 for (int i = 0; i < SplitNumElements; ++i)
9987 if (BlendMask[i] >= SplitNumElements)
9988 BlendMask[i] = V2BlendMask[i] + (UseLoV2 ? SplitNumElements : 0);
9990 return DAG.getVectorShuffle(SplitVT, DL, V1Blend, V2Blend, BlendMask);
9992 SDValue Lo = HalfBlend(LoMask);
9993 SDValue Hi = HalfBlend(HiMask);
9994 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Lo, Hi);
9997 /// \brief Either split a vector in halves or decompose the shuffles and the
10000 /// This is provided as a good fallback for many lowerings of non-single-input
10001 /// shuffles with more than one 128-bit lane. In those cases, we want to select
10002 /// between splitting the shuffle into 128-bit components and stitching those
10003 /// back together vs. extracting the single-input shuffles and blending those
10005 static SDValue lowerVectorShuffleAsSplitOrBlend(SDLoc DL, MVT VT, SDValue V1,
10006 SDValue V2, ArrayRef<int> Mask,
10007 SelectionDAG &DAG) {
10008 assert(!isSingleInputShuffleMask(Mask) && "This routine must not be used to "
10009 "lower single-input shuffles as it "
10010 "could then recurse on itself.");
10011 int Size = Mask.size();
10013 // If this can be modeled as a broadcast of two elements followed by a blend,
10014 // prefer that lowering. This is especially important because broadcasts can
10015 // often fold with memory operands.
10016 auto DoBothBroadcast = [&] {
10017 int V1BroadcastIdx = -1, V2BroadcastIdx = -1;
10020 if (V2BroadcastIdx == -1)
10021 V2BroadcastIdx = M - Size;
10022 else if (M - Size != V2BroadcastIdx)
10024 } else if (M >= 0) {
10025 if (V1BroadcastIdx == -1)
10026 V1BroadcastIdx = M;
10027 else if (M != V1BroadcastIdx)
10032 if (DoBothBroadcast())
10033 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask,
10036 // If the inputs all stem from a single 128-bit lane of each input, then we
10037 // split them rather than blending because the split will decompose to
10038 // unusually few instructions.
10039 int LaneCount = VT.getSizeInBits() / 128;
10040 int LaneSize = Size / LaneCount;
10041 SmallBitVector LaneInputs[2];
10042 LaneInputs[0].resize(LaneCount, false);
10043 LaneInputs[1].resize(LaneCount, false);
10044 for (int i = 0; i < Size; ++i)
10046 LaneInputs[Mask[i] / Size][(Mask[i] % Size) / LaneSize] = true;
10047 if (LaneInputs[0].count() <= 1 && LaneInputs[1].count() <= 1)
10048 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
10050 // Otherwise, just fall back to decomposed shuffles and a blend. This requires
10051 // that the decomposed single-input shuffles don't end up here.
10052 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask, DAG);
10055 /// \brief Lower a vector shuffle crossing multiple 128-bit lanes as
10056 /// a permutation and blend of those lanes.
10058 /// This essentially blends the out-of-lane inputs to each lane into the lane
10059 /// from a permuted copy of the vector. This lowering strategy results in four
10060 /// instructions in the worst case for a single-input cross lane shuffle which
10061 /// is lower than any other fully general cross-lane shuffle strategy I'm aware
10062 /// of. Special cases for each particular shuffle pattern should be handled
10063 /// prior to trying this lowering.
10064 static SDValue lowerVectorShuffleAsLanePermuteAndBlend(SDLoc DL, MVT VT,
10065 SDValue V1, SDValue V2,
10066 ArrayRef<int> Mask,
10067 SelectionDAG &DAG) {
10068 // FIXME: This should probably be generalized for 512-bit vectors as well.
10069 assert(VT.is256BitVector() && "Only for 256-bit vector shuffles!");
10070 int LaneSize = Mask.size() / 2;
10072 // If there are only inputs from one 128-bit lane, splitting will in fact be
10073 // less expensive. The flags track whether the given lane contains an element
10074 // that crosses to another lane.
10075 bool LaneCrossing[2] = {false, false};
10076 for (int i = 0, Size = Mask.size(); i < Size; ++i)
10077 if (Mask[i] >= 0 && (Mask[i] % Size) / LaneSize != i / LaneSize)
10078 LaneCrossing[(Mask[i] % Size) / LaneSize] = true;
10079 if (!LaneCrossing[0] || !LaneCrossing[1])
10080 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
10082 if (isSingleInputShuffleMask(Mask)) {
10083 SmallVector<int, 32> FlippedBlendMask;
10084 for (int i = 0, Size = Mask.size(); i < Size; ++i)
10085 FlippedBlendMask.push_back(
10086 Mask[i] < 0 ? -1 : (((Mask[i] % Size) / LaneSize == i / LaneSize)
10088 : Mask[i] % LaneSize +
10089 (i / LaneSize) * LaneSize + Size));
10091 // Flip the vector, and blend the results which should now be in-lane. The
10092 // VPERM2X128 mask uses the low 2 bits for the low source and bits 4 and
10093 // 5 for the high source. The value 3 selects the high half of source 2 and
10094 // the value 2 selects the low half of source 2. We only use source 2 to
10095 // allow folding it into a memory operand.
10096 unsigned PERMMask = 3 | 2 << 4;
10097 SDValue Flipped = DAG.getNode(X86ISD::VPERM2X128, DL, VT, DAG.getUNDEF(VT),
10098 V1, DAG.getConstant(PERMMask, DL, MVT::i8));
10099 return DAG.getVectorShuffle(VT, DL, V1, Flipped, FlippedBlendMask);
10102 // This now reduces to two single-input shuffles of V1 and V2 which at worst
10103 // will be handled by the above logic and a blend of the results, much like
10104 // other patterns in AVX.
10105 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask, DAG);
10108 /// \brief Handle lowering 2-lane 128-bit shuffles.
10109 static SDValue lowerV2X128VectorShuffle(SDLoc DL, MVT VT, SDValue V1,
10110 SDValue V2, ArrayRef<int> Mask,
10111 const X86Subtarget *Subtarget,
10112 SelectionDAG &DAG) {
10113 // TODO: If minimizing size and one of the inputs is a zero vector and the
10114 // the zero vector has only one use, we could use a VPERM2X128 to save the
10115 // instruction bytes needed to explicitly generate the zero vector.
10117 // Blends are faster and handle all the non-lane-crossing cases.
10118 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, VT, V1, V2, Mask,
10122 bool IsV1Zero = ISD::isBuildVectorAllZeros(V1.getNode());
10123 bool IsV2Zero = ISD::isBuildVectorAllZeros(V2.getNode());
10125 // If either input operand is a zero vector, use VPERM2X128 because its mask
10126 // allows us to replace the zero input with an implicit zero.
10127 if (!IsV1Zero && !IsV2Zero) {
10128 // Check for patterns which can be matched with a single insert of a 128-bit
10130 bool OnlyUsesV1 = isShuffleEquivalent(V1, V2, Mask, {0, 1, 0, 1});
10131 if (OnlyUsesV1 || isShuffleEquivalent(V1, V2, Mask, {0, 1, 4, 5})) {
10132 MVT SubVT = MVT::getVectorVT(VT.getVectorElementType(),
10133 VT.getVectorNumElements() / 2);
10134 SDValue LoV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT, V1,
10135 DAG.getIntPtrConstant(0, DL));
10136 SDValue HiV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT,
10137 OnlyUsesV1 ? V1 : V2,
10138 DAG.getIntPtrConstant(0, DL));
10139 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LoV, HiV);
10143 // Otherwise form a 128-bit permutation. After accounting for undefs,
10144 // convert the 64-bit shuffle mask selection values into 128-bit
10145 // selection bits by dividing the indexes by 2 and shifting into positions
10146 // defined by a vperm2*128 instruction's immediate control byte.
10148 // The immediate permute control byte looks like this:
10149 // [1:0] - select 128 bits from sources for low half of destination
10151 // [3] - zero low half of destination
10152 // [5:4] - select 128 bits from sources for high half of destination
10154 // [7] - zero high half of destination
10156 int MaskLO = Mask[0];
10157 if (MaskLO == SM_SentinelUndef)
10158 MaskLO = Mask[1] == SM_SentinelUndef ? 0 : Mask[1];
10160 int MaskHI = Mask[2];
10161 if (MaskHI == SM_SentinelUndef)
10162 MaskHI = Mask[3] == SM_SentinelUndef ? 0 : Mask[3];
10164 unsigned PermMask = MaskLO / 2 | (MaskHI / 2) << 4;
10166 // If either input is a zero vector, replace it with an undef input.
10167 // Shuffle mask values < 4 are selecting elements of V1.
10168 // Shuffle mask values >= 4 are selecting elements of V2.
10169 // Adjust each half of the permute mask by clearing the half that was
10170 // selecting the zero vector and setting the zero mask bit.
10172 V1 = DAG.getUNDEF(VT);
10174 PermMask = (PermMask & 0xf0) | 0x08;
10176 PermMask = (PermMask & 0x0f) | 0x80;
10179 V2 = DAG.getUNDEF(VT);
10181 PermMask = (PermMask & 0xf0) | 0x08;
10183 PermMask = (PermMask & 0x0f) | 0x80;
10186 return DAG.getNode(X86ISD::VPERM2X128, DL, VT, V1, V2,
10187 DAG.getConstant(PermMask, DL, MVT::i8));
10190 /// \brief Lower a vector shuffle by first fixing the 128-bit lanes and then
10191 /// shuffling each lane.
10193 /// This will only succeed when the result of fixing the 128-bit lanes results
10194 /// in a single-input non-lane-crossing shuffle with a repeating shuffle mask in
10195 /// each 128-bit lanes. This handles many cases where we can quickly blend away
10196 /// the lane crosses early and then use simpler shuffles within each lane.
10198 /// FIXME: It might be worthwhile at some point to support this without
10199 /// requiring the 128-bit lane-relative shuffles to be repeating, but currently
10200 /// in x86 only floating point has interesting non-repeating shuffles, and even
10201 /// those are still *marginally* more expensive.
10202 static SDValue lowerVectorShuffleByMerging128BitLanes(
10203 SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
10204 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
10205 assert(!isSingleInputShuffleMask(Mask) &&
10206 "This is only useful with multiple inputs.");
10208 int Size = Mask.size();
10209 int LaneSize = 128 / VT.getScalarSizeInBits();
10210 int NumLanes = Size / LaneSize;
10211 assert(NumLanes > 1 && "Only handles 256-bit and wider shuffles.");
10213 // See if we can build a hypothetical 128-bit lane-fixing shuffle mask. Also
10214 // check whether the in-128-bit lane shuffles share a repeating pattern.
10215 SmallVector<int, 4> Lanes;
10216 Lanes.resize(NumLanes, -1);
10217 SmallVector<int, 4> InLaneMask;
10218 InLaneMask.resize(LaneSize, -1);
10219 for (int i = 0; i < Size; ++i) {
10223 int j = i / LaneSize;
10225 if (Lanes[j] < 0) {
10226 // First entry we've seen for this lane.
10227 Lanes[j] = Mask[i] / LaneSize;
10228 } else if (Lanes[j] != Mask[i] / LaneSize) {
10229 // This doesn't match the lane selected previously!
10233 // Check that within each lane we have a consistent shuffle mask.
10234 int k = i % LaneSize;
10235 if (InLaneMask[k] < 0) {
10236 InLaneMask[k] = Mask[i] % LaneSize;
10237 } else if (InLaneMask[k] != Mask[i] % LaneSize) {
10238 // This doesn't fit a repeating in-lane mask.
10243 // First shuffle the lanes into place.
10244 MVT LaneVT = MVT::getVectorVT(VT.isFloatingPoint() ? MVT::f64 : MVT::i64,
10245 VT.getSizeInBits() / 64);
10246 SmallVector<int, 8> LaneMask;
10247 LaneMask.resize(NumLanes * 2, -1);
10248 for (int i = 0; i < NumLanes; ++i)
10249 if (Lanes[i] >= 0) {
10250 LaneMask[2 * i + 0] = 2*Lanes[i] + 0;
10251 LaneMask[2 * i + 1] = 2*Lanes[i] + 1;
10254 V1 = DAG.getBitcast(LaneVT, V1);
10255 V2 = DAG.getBitcast(LaneVT, V2);
10256 SDValue LaneShuffle = DAG.getVectorShuffle(LaneVT, DL, V1, V2, LaneMask);
10258 // Cast it back to the type we actually want.
10259 LaneShuffle = DAG.getBitcast(VT, LaneShuffle);
10261 // Now do a simple shuffle that isn't lane crossing.
10262 SmallVector<int, 8> NewMask;
10263 NewMask.resize(Size, -1);
10264 for (int i = 0; i < Size; ++i)
10266 NewMask[i] = (i / LaneSize) * LaneSize + Mask[i] % LaneSize;
10267 assert(!is128BitLaneCrossingShuffleMask(VT, NewMask) &&
10268 "Must not introduce lane crosses at this point!");
10270 return DAG.getVectorShuffle(VT, DL, LaneShuffle, DAG.getUNDEF(VT), NewMask);
10273 /// \brief Test whether the specified input (0 or 1) is in-place blended by the
10276 /// This returns true if the elements from a particular input are already in the
10277 /// slot required by the given mask and require no permutation.
10278 static bool isShuffleMaskInputInPlace(int Input, ArrayRef<int> Mask) {
10279 assert((Input == 0 || Input == 1) && "Only two inputs to shuffles.");
10280 int Size = Mask.size();
10281 for (int i = 0; i < Size; ++i)
10282 if (Mask[i] >= 0 && Mask[i] / Size == Input && Mask[i] % Size != i)
10288 static SDValue lowerVectorShuffleWithSHUFPD(SDLoc DL, MVT VT,
10289 ArrayRef<int> Mask, SDValue V1,
10290 SDValue V2, SelectionDAG &DAG) {
10292 // Mask for V8F64: 0/1, 8/9, 2/3, 10/11, 4/5, ..
10293 // Mask for V4F64; 0/1, 4/5, 2/3, 6/7..
10294 assert(VT.getScalarSizeInBits() == 64 && "Unexpected data type for VSHUFPD");
10295 int NumElts = VT.getVectorNumElements();
10296 bool ShufpdMask = true;
10297 bool CommutableMask = true;
10298 unsigned Immediate = 0;
10299 for (int i = 0; i < NumElts; ++i) {
10302 int Val = (i & 6) + NumElts * (i & 1);
10303 int CommutVal = (i & 0xe) + NumElts * ((i & 1)^1);
10304 if (Mask[i] < Val || Mask[i] > Val + 1)
10305 ShufpdMask = false;
10306 if (Mask[i] < CommutVal || Mask[i] > CommutVal + 1)
10307 CommutableMask = false;
10308 Immediate |= (Mask[i] % 2) << i;
10311 return DAG.getNode(X86ISD::SHUFP, DL, VT, V1, V2,
10312 DAG.getConstant(Immediate, DL, MVT::i8));
10313 if (CommutableMask)
10314 return DAG.getNode(X86ISD::SHUFP, DL, VT, V2, V1,
10315 DAG.getConstant(Immediate, DL, MVT::i8));
10319 /// \brief Handle lowering of 4-lane 64-bit floating point shuffles.
10321 /// Also ends up handling lowering of 4-lane 64-bit integer shuffles when AVX2
10322 /// isn't available.
10323 static SDValue lowerV4F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10324 const X86Subtarget *Subtarget,
10325 SelectionDAG &DAG) {
10327 assert(V1.getSimpleValueType() == MVT::v4f64 && "Bad operand type!");
10328 assert(V2.getSimpleValueType() == MVT::v4f64 && "Bad operand type!");
10329 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10330 ArrayRef<int> Mask = SVOp->getMask();
10331 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
10333 SmallVector<int, 4> WidenedMask;
10334 if (canWidenShuffleElements(Mask, WidenedMask))
10335 return lowerV2X128VectorShuffle(DL, MVT::v4f64, V1, V2, Mask, Subtarget,
10338 if (isSingleInputShuffleMask(Mask)) {
10339 // Check for being able to broadcast a single element.
10340 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v4f64, V1,
10341 Mask, Subtarget, DAG))
10344 // Use low duplicate instructions for masks that match their pattern.
10345 if (isShuffleEquivalent(V1, V2, Mask, {0, 0, 2, 2}))
10346 return DAG.getNode(X86ISD::MOVDDUP, DL, MVT::v4f64, V1);
10348 if (!is128BitLaneCrossingShuffleMask(MVT::v4f64, Mask)) {
10349 // Non-half-crossing single input shuffles can be lowerid with an
10350 // interleaved permutation.
10351 unsigned VPERMILPMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1) |
10352 ((Mask[2] == 3) << 2) | ((Mask[3] == 3) << 3);
10353 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v4f64, V1,
10354 DAG.getConstant(VPERMILPMask, DL, MVT::i8));
10357 // With AVX2 we have direct support for this permutation.
10358 if (Subtarget->hasAVX2())
10359 return DAG.getNode(X86ISD::VPERMI, DL, MVT::v4f64, V1,
10360 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
10362 // Otherwise, fall back.
10363 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v4f64, V1, V2, Mask,
10367 // Use dedicated unpack instructions for masks that match their pattern.
10369 lowerVectorShuffleWithUNPCK(DL, MVT::v4f64, Mask, V1, V2, DAG))
10372 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4f64, V1, V2, Mask,
10376 // Check if the blend happens to exactly fit that of SHUFPD.
10378 lowerVectorShuffleWithSHUFPD(DL, MVT::v4f64, Mask, V1, V2, DAG))
10381 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10382 // shuffle. However, if we have AVX2 and either inputs are already in place,
10383 // we will be able to shuffle even across lanes the other input in a single
10384 // instruction so skip this pattern.
10385 if (!(Subtarget->hasAVX2() && (isShuffleMaskInputInPlace(0, Mask) ||
10386 isShuffleMaskInputInPlace(1, Mask))))
10387 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10388 DL, MVT::v4f64, V1, V2, Mask, Subtarget, DAG))
10391 // If we have AVX2 then we always want to lower with a blend because an v4 we
10392 // can fully permute the elements.
10393 if (Subtarget->hasAVX2())
10394 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4f64, V1, V2,
10397 // Otherwise fall back on generic lowering.
10398 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v4f64, V1, V2, Mask, DAG);
10401 /// \brief Handle lowering of 4-lane 64-bit integer shuffles.
10403 /// This routine is only called when we have AVX2 and thus a reasonable
10404 /// instruction set for v4i64 shuffling..
10405 static SDValue lowerV4I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10406 const X86Subtarget *Subtarget,
10407 SelectionDAG &DAG) {
10409 assert(V1.getSimpleValueType() == MVT::v4i64 && "Bad operand type!");
10410 assert(V2.getSimpleValueType() == MVT::v4i64 && "Bad operand type!");
10411 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10412 ArrayRef<int> Mask = SVOp->getMask();
10413 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
10414 assert(Subtarget->hasAVX2() && "We can only lower v4i64 with AVX2!");
10416 SmallVector<int, 4> WidenedMask;
10417 if (canWidenShuffleElements(Mask, WidenedMask))
10418 return lowerV2X128VectorShuffle(DL, MVT::v4i64, V1, V2, Mask, Subtarget,
10421 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4i64, V1, V2, Mask,
10425 // Check for being able to broadcast a single element.
10426 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v4i64, V1,
10427 Mask, Subtarget, DAG))
10430 // When the shuffle is mirrored between the 128-bit lanes of the unit, we can
10431 // use lower latency instructions that will operate on both 128-bit lanes.
10432 SmallVector<int, 2> RepeatedMask;
10433 if (is128BitLaneRepeatedShuffleMask(MVT::v4i64, Mask, RepeatedMask)) {
10434 if (isSingleInputShuffleMask(Mask)) {
10435 int PSHUFDMask[] = {-1, -1, -1, -1};
10436 for (int i = 0; i < 2; ++i)
10437 if (RepeatedMask[i] >= 0) {
10438 PSHUFDMask[2 * i] = 2 * RepeatedMask[i];
10439 PSHUFDMask[2 * i + 1] = 2 * RepeatedMask[i] + 1;
10441 return DAG.getBitcast(
10443 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v8i32,
10444 DAG.getBitcast(MVT::v8i32, V1),
10445 getV4X86ShuffleImm8ForMask(PSHUFDMask, DL, DAG)));
10449 // AVX2 provides a direct instruction for permuting a single input across
10451 if (isSingleInputShuffleMask(Mask))
10452 return DAG.getNode(X86ISD::VPERMI, DL, MVT::v4i64, V1,
10453 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
10455 // Try to use shift instructions.
10456 if (SDValue Shift =
10457 lowerVectorShuffleAsShift(DL, MVT::v4i64, V1, V2, Mask, DAG))
10460 // Use dedicated unpack instructions for masks that match their pattern.
10462 lowerVectorShuffleWithUNPCK(DL, MVT::v4i64, Mask, V1, V2, DAG))
10465 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10466 // shuffle. However, if we have AVX2 and either inputs are already in place,
10467 // we will be able to shuffle even across lanes the other input in a single
10468 // instruction so skip this pattern.
10469 if (!(Subtarget->hasAVX2() && (isShuffleMaskInputInPlace(0, Mask) ||
10470 isShuffleMaskInputInPlace(1, Mask))))
10471 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10472 DL, MVT::v4i64, V1, V2, Mask, Subtarget, DAG))
10475 // Otherwise fall back on generic blend lowering.
10476 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4i64, V1, V2,
10480 /// \brief Handle lowering of 8-lane 32-bit floating point shuffles.
10482 /// Also ends up handling lowering of 8-lane 32-bit integer shuffles when AVX2
10483 /// isn't available.
10484 static SDValue lowerV8F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10485 const X86Subtarget *Subtarget,
10486 SelectionDAG &DAG) {
10488 assert(V1.getSimpleValueType() == MVT::v8f32 && "Bad operand type!");
10489 assert(V2.getSimpleValueType() == MVT::v8f32 && "Bad operand type!");
10490 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10491 ArrayRef<int> Mask = SVOp->getMask();
10492 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10494 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8f32, V1, V2, Mask,
10498 // Check for being able to broadcast a single element.
10499 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v8f32, V1,
10500 Mask, Subtarget, DAG))
10503 // If the shuffle mask is repeated in each 128-bit lane, we have many more
10504 // options to efficiently lower the shuffle.
10505 SmallVector<int, 4> RepeatedMask;
10506 if (is128BitLaneRepeatedShuffleMask(MVT::v8f32, Mask, RepeatedMask)) {
10507 assert(RepeatedMask.size() == 4 &&
10508 "Repeated masks must be half the mask width!");
10510 // Use even/odd duplicate instructions for masks that match their pattern.
10511 if (isShuffleEquivalent(V1, V2, Mask, {0, 0, 2, 2, 4, 4, 6, 6}))
10512 return DAG.getNode(X86ISD::MOVSLDUP, DL, MVT::v8f32, V1);
10513 if (isShuffleEquivalent(V1, V2, Mask, {1, 1, 3, 3, 5, 5, 7, 7}))
10514 return DAG.getNode(X86ISD::MOVSHDUP, DL, MVT::v8f32, V1);
10516 if (isSingleInputShuffleMask(Mask))
10517 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v8f32, V1,
10518 getV4X86ShuffleImm8ForMask(RepeatedMask, DL, DAG));
10520 // Use dedicated unpack instructions for masks that match their pattern.
10522 lowerVectorShuffleWithUNPCK(DL, MVT::v8f32, Mask, V1, V2, DAG))
10525 // Otherwise, fall back to a SHUFPS sequence. Here it is important that we
10526 // have already handled any direct blends. We also need to squash the
10527 // repeated mask into a simulated v4f32 mask.
10528 for (int i = 0; i < 4; ++i)
10529 if (RepeatedMask[i] >= 8)
10530 RepeatedMask[i] -= 4;
10531 return lowerVectorShuffleWithSHUFPS(DL, MVT::v8f32, RepeatedMask, V1, V2, DAG);
10534 // If we have a single input shuffle with different shuffle patterns in the
10535 // two 128-bit lanes use the variable mask to VPERMILPS.
10536 if (isSingleInputShuffleMask(Mask)) {
10537 SDValue VPermMask[8];
10538 for (int i = 0; i < 8; ++i)
10539 VPermMask[i] = Mask[i] < 0 ? DAG.getUNDEF(MVT::i32)
10540 : DAG.getConstant(Mask[i], DL, MVT::i32);
10541 if (!is128BitLaneCrossingShuffleMask(MVT::v8f32, Mask))
10542 return DAG.getNode(
10543 X86ISD::VPERMILPV, DL, MVT::v8f32, V1,
10544 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i32, VPermMask));
10546 if (Subtarget->hasAVX2())
10547 return DAG.getNode(
10548 X86ISD::VPERMV, DL, MVT::v8f32,
10549 DAG.getBitcast(MVT::v8f32, DAG.getNode(ISD::BUILD_VECTOR, DL,
10550 MVT::v8i32, VPermMask)),
10553 // Otherwise, fall back.
10554 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v8f32, V1, V2, Mask,
10558 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10560 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10561 DL, MVT::v8f32, V1, V2, Mask, Subtarget, DAG))
10564 // If we have AVX2 then we always want to lower with a blend because at v8 we
10565 // can fully permute the elements.
10566 if (Subtarget->hasAVX2())
10567 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8f32, V1, V2,
10570 // Otherwise fall back on generic lowering.
10571 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v8f32, V1, V2, Mask, DAG);
10574 /// \brief Handle lowering of 8-lane 32-bit integer shuffles.
10576 /// This routine is only called when we have AVX2 and thus a reasonable
10577 /// instruction set for v8i32 shuffling..
10578 static SDValue lowerV8I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10579 const X86Subtarget *Subtarget,
10580 SelectionDAG &DAG) {
10582 assert(V1.getSimpleValueType() == MVT::v8i32 && "Bad operand type!");
10583 assert(V2.getSimpleValueType() == MVT::v8i32 && "Bad operand type!");
10584 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10585 ArrayRef<int> Mask = SVOp->getMask();
10586 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10587 assert(Subtarget->hasAVX2() && "We can only lower v8i32 with AVX2!");
10589 // Whenever we can lower this as a zext, that instruction is strictly faster
10590 // than any alternative. It also allows us to fold memory operands into the
10591 // shuffle in many cases.
10592 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v8i32, V1, V2,
10593 Mask, Subtarget, DAG))
10596 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8i32, V1, V2, Mask,
10600 // Check for being able to broadcast a single element.
10601 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v8i32, V1,
10602 Mask, Subtarget, DAG))
10605 // If the shuffle mask is repeated in each 128-bit lane we can use more
10606 // efficient instructions that mirror the shuffles across the two 128-bit
10608 SmallVector<int, 4> RepeatedMask;
10609 if (is128BitLaneRepeatedShuffleMask(MVT::v8i32, Mask, RepeatedMask)) {
10610 assert(RepeatedMask.size() == 4 && "Unexpected repeated mask size!");
10611 if (isSingleInputShuffleMask(Mask))
10612 return DAG.getNode(X86ISD::PSHUFD, DL, MVT::v8i32, V1,
10613 getV4X86ShuffleImm8ForMask(RepeatedMask, DL, DAG));
10615 // Use dedicated unpack instructions for masks that match their pattern.
10617 lowerVectorShuffleWithUNPCK(DL, MVT::v8i32, Mask, V1, V2, DAG))
10621 // Try to use shift instructions.
10622 if (SDValue Shift =
10623 lowerVectorShuffleAsShift(DL, MVT::v8i32, V1, V2, Mask, DAG))
10626 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
10627 DL, MVT::v8i32, V1, V2, Mask, Subtarget, DAG))
10630 // If the shuffle patterns aren't repeated but it is a single input, directly
10631 // generate a cross-lane VPERMD instruction.
10632 if (isSingleInputShuffleMask(Mask)) {
10633 SDValue VPermMask[8];
10634 for (int i = 0; i < 8; ++i)
10635 VPermMask[i] = Mask[i] < 0 ? DAG.getUNDEF(MVT::i32)
10636 : DAG.getConstant(Mask[i], DL, MVT::i32);
10637 return DAG.getNode(
10638 X86ISD::VPERMV, DL, MVT::v8i32,
10639 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i32, VPermMask), V1);
10642 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10644 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10645 DL, MVT::v8i32, V1, V2, Mask, Subtarget, DAG))
10648 // Otherwise fall back on generic blend lowering.
10649 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8i32, V1, V2,
10653 /// \brief Handle lowering of 16-lane 16-bit integer shuffles.
10655 /// This routine is only called when we have AVX2 and thus a reasonable
10656 /// instruction set for v16i16 shuffling..
10657 static SDValue lowerV16I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10658 const X86Subtarget *Subtarget,
10659 SelectionDAG &DAG) {
10661 assert(V1.getSimpleValueType() == MVT::v16i16 && "Bad operand type!");
10662 assert(V2.getSimpleValueType() == MVT::v16i16 && "Bad operand type!");
10663 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10664 ArrayRef<int> Mask = SVOp->getMask();
10665 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
10666 assert(Subtarget->hasAVX2() && "We can only lower v16i16 with AVX2!");
10668 // Whenever we can lower this as a zext, that instruction is strictly faster
10669 // than any alternative. It also allows us to fold memory operands into the
10670 // shuffle in many cases.
10671 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v16i16, V1, V2,
10672 Mask, Subtarget, DAG))
10675 // Check for being able to broadcast a single element.
10676 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v16i16, V1,
10677 Mask, Subtarget, DAG))
10680 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v16i16, V1, V2, Mask,
10684 // Use dedicated unpack instructions for masks that match their pattern.
10686 lowerVectorShuffleWithUNPCK(DL, MVT::v16i16, Mask, V1, V2, DAG))
10689 // Try to use shift instructions.
10690 if (SDValue Shift =
10691 lowerVectorShuffleAsShift(DL, MVT::v16i16, V1, V2, Mask, DAG))
10694 // Try to use byte rotation instructions.
10695 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
10696 DL, MVT::v16i16, V1, V2, Mask, Subtarget, DAG))
10699 if (isSingleInputShuffleMask(Mask)) {
10700 // There are no generalized cross-lane shuffle operations available on i16
10702 if (is128BitLaneCrossingShuffleMask(MVT::v16i16, Mask))
10703 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v16i16, V1, V2,
10706 SmallVector<int, 8> RepeatedMask;
10707 if (is128BitLaneRepeatedShuffleMask(MVT::v16i16, Mask, RepeatedMask)) {
10708 // As this is a single-input shuffle, the repeated mask should be
10709 // a strictly valid v8i16 mask that we can pass through to the v8i16
10710 // lowering to handle even the v16 case.
10711 return lowerV8I16GeneralSingleInputVectorShuffle(
10712 DL, MVT::v16i16, V1, RepeatedMask, Subtarget, DAG);
10715 SDValue PSHUFBMask[32];
10716 for (int i = 0; i < 16; ++i) {
10717 if (Mask[i] == -1) {
10718 PSHUFBMask[2 * i] = PSHUFBMask[2 * i + 1] = DAG.getUNDEF(MVT::i8);
10722 int M = i < 8 ? Mask[i] : Mask[i] - 8;
10723 assert(M >= 0 && M < 8 && "Invalid single-input mask!");
10724 PSHUFBMask[2 * i] = DAG.getConstant(2 * M, DL, MVT::i8);
10725 PSHUFBMask[2 * i + 1] = DAG.getConstant(2 * M + 1, DL, MVT::i8);
10727 return DAG.getBitcast(MVT::v16i16,
10728 DAG.getNode(X86ISD::PSHUFB, DL, MVT::v32i8,
10729 DAG.getBitcast(MVT::v32i8, V1),
10730 DAG.getNode(ISD::BUILD_VECTOR, DL,
10731 MVT::v32i8, PSHUFBMask)));
10734 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10736 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10737 DL, MVT::v16i16, V1, V2, Mask, Subtarget, DAG))
10740 // Otherwise fall back on generic lowering.
10741 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v16i16, V1, V2, Mask, DAG);
10744 /// \brief Handle lowering of 32-lane 8-bit integer shuffles.
10746 /// This routine is only called when we have AVX2 and thus a reasonable
10747 /// instruction set for v32i8 shuffling..
10748 static SDValue lowerV32I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10749 const X86Subtarget *Subtarget,
10750 SelectionDAG &DAG) {
10752 assert(V1.getSimpleValueType() == MVT::v32i8 && "Bad operand type!");
10753 assert(V2.getSimpleValueType() == MVT::v32i8 && "Bad operand type!");
10754 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10755 ArrayRef<int> Mask = SVOp->getMask();
10756 assert(Mask.size() == 32 && "Unexpected mask size for v32 shuffle!");
10757 assert(Subtarget->hasAVX2() && "We can only lower v32i8 with AVX2!");
10759 // Whenever we can lower this as a zext, that instruction is strictly faster
10760 // than any alternative. It also allows us to fold memory operands into the
10761 // shuffle in many cases.
10762 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v32i8, V1, V2,
10763 Mask, Subtarget, DAG))
10766 // Check for being able to broadcast a single element.
10767 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v32i8, V1,
10768 Mask, Subtarget, DAG))
10771 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v32i8, V1, V2, Mask,
10775 // Use dedicated unpack instructions for masks that match their pattern.
10777 lowerVectorShuffleWithUNPCK(DL, MVT::v32i8, Mask, V1, V2, DAG))
10780 // Try to use shift instructions.
10781 if (SDValue Shift =
10782 lowerVectorShuffleAsShift(DL, MVT::v32i8, V1, V2, Mask, DAG))
10785 // Try to use byte rotation instructions.
10786 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
10787 DL, MVT::v32i8, V1, V2, Mask, Subtarget, DAG))
10790 if (isSingleInputShuffleMask(Mask)) {
10791 // There are no generalized cross-lane shuffle operations available on i8
10793 if (is128BitLaneCrossingShuffleMask(MVT::v32i8, Mask))
10794 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v32i8, V1, V2,
10797 SDValue PSHUFBMask[32];
10798 for (int i = 0; i < 32; ++i)
10801 ? DAG.getUNDEF(MVT::i8)
10802 : DAG.getConstant(Mask[i] < 16 ? Mask[i] : Mask[i] - 16, DL,
10805 return DAG.getNode(
10806 X86ISD::PSHUFB, DL, MVT::v32i8, V1,
10807 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, PSHUFBMask));
10810 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10812 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10813 DL, MVT::v32i8, V1, V2, Mask, Subtarget, DAG))
10816 // Otherwise fall back on generic lowering.
10817 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v32i8, V1, V2, Mask, DAG);
10820 /// \brief High-level routine to lower various 256-bit x86 vector shuffles.
10822 /// This routine either breaks down the specific type of a 256-bit x86 vector
10823 /// shuffle or splits it into two 128-bit shuffles and fuses the results back
10824 /// together based on the available instructions.
10825 static SDValue lower256BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10826 MVT VT, const X86Subtarget *Subtarget,
10827 SelectionDAG &DAG) {
10829 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10830 ArrayRef<int> Mask = SVOp->getMask();
10832 // If we have a single input to the zero element, insert that into V1 if we
10833 // can do so cheaply.
10834 int NumElts = VT.getVectorNumElements();
10835 int NumV2Elements = std::count_if(Mask.begin(), Mask.end(), [NumElts](int M) {
10836 return M >= NumElts;
10839 if (NumV2Elements == 1 && Mask[0] >= NumElts)
10840 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
10841 DL, VT, V1, V2, Mask, Subtarget, DAG))
10844 // There is a really nice hard cut-over between AVX1 and AVX2 that means we
10845 // can check for those subtargets here and avoid much of the subtarget
10846 // querying in the per-vector-type lowering routines. With AVX1 we have
10847 // essentially *zero* ability to manipulate a 256-bit vector with integer
10848 // types. Since we'll use floating point types there eventually, just
10849 // immediately cast everything to a float and operate entirely in that domain.
10850 if (VT.isInteger() && !Subtarget->hasAVX2()) {
10851 int ElementBits = VT.getScalarSizeInBits();
10852 if (ElementBits < 32)
10853 // No floating point type available, decompose into 128-bit vectors.
10854 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
10856 MVT FpVT = MVT::getVectorVT(MVT::getFloatingPointVT(ElementBits),
10857 VT.getVectorNumElements());
10858 V1 = DAG.getBitcast(FpVT, V1);
10859 V2 = DAG.getBitcast(FpVT, V2);
10860 return DAG.getBitcast(VT, DAG.getVectorShuffle(FpVT, DL, V1, V2, Mask));
10863 switch (VT.SimpleTy) {
10865 return lowerV4F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10867 return lowerV4I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10869 return lowerV8F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10871 return lowerV8I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10873 return lowerV16I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
10875 return lowerV32I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
10878 llvm_unreachable("Not a valid 256-bit x86 vector type!");
10882 /// \brief Try to lower a vector shuffle as a 128-bit shuffles.
10883 static SDValue lowerV4X128VectorShuffle(SDLoc DL, MVT VT,
10884 ArrayRef<int> Mask,
10885 SDValue V1, SDValue V2,
10886 SelectionDAG &DAG) {
10887 assert(VT.getScalarSizeInBits() == 64 &&
10888 "Unexpected element type size for 128bit shuffle.");
10890 // To handle 256 bit vector requires VLX and most probably
10891 // function lowerV2X128VectorShuffle() is better solution.
10892 assert(VT.is512BitVector() && "Unexpected vector size for 128bit shuffle.");
10894 SmallVector<int, 4> WidenedMask;
10895 if (!canWidenShuffleElements(Mask, WidenedMask))
10898 // Form a 128-bit permutation.
10899 // Convert the 64-bit shuffle mask selection values into 128-bit selection
10900 // bits defined by a vshuf64x2 instruction's immediate control byte.
10901 unsigned PermMask = 0, Imm = 0;
10902 unsigned ControlBitsNum = WidenedMask.size() / 2;
10904 for (int i = 0, Size = WidenedMask.size(); i < Size; ++i) {
10905 if (WidenedMask[i] == SM_SentinelZero)
10908 // Use first element in place of undef mask.
10909 Imm = (WidenedMask[i] == SM_SentinelUndef) ? 0 : WidenedMask[i];
10910 PermMask |= (Imm % WidenedMask.size()) << (i * ControlBitsNum);
10913 return DAG.getNode(X86ISD::SHUF128, DL, VT, V1, V2,
10914 DAG.getConstant(PermMask, DL, MVT::i8));
10917 static SDValue lowerVectorShuffleWithPERMV(SDLoc DL, MVT VT,
10918 ArrayRef<int> Mask, SDValue V1,
10919 SDValue V2, SelectionDAG &DAG) {
10921 assert(VT.getScalarSizeInBits() >= 16 && "Unexpected data type for PERMV");
10923 MVT MaskEltVT = MVT::getIntegerVT(VT.getScalarSizeInBits());
10924 MVT MaskVecVT = MVT::getVectorVT(MaskEltVT, VT.getVectorNumElements());
10926 SDValue MaskNode = getConstVector(Mask, MaskVecVT, DAG, DL, true);
10927 if (isSingleInputShuffleMask(Mask))
10928 return DAG.getNode(X86ISD::VPERMV, DL, VT, MaskNode, V1);
10930 return DAG.getNode(X86ISD::VPERMV3, DL, VT, V1, MaskNode, V2);
10933 /// \brief Handle lowering of 8-lane 64-bit floating point shuffles.
10934 static SDValue lowerV8F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10935 const X86Subtarget *Subtarget,
10936 SelectionDAG &DAG) {
10938 assert(V1.getSimpleValueType() == MVT::v8f64 && "Bad operand type!");
10939 assert(V2.getSimpleValueType() == MVT::v8f64 && "Bad operand type!");
10940 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10941 ArrayRef<int> Mask = SVOp->getMask();
10942 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10944 if (SDValue Shuf128 =
10945 lowerV4X128VectorShuffle(DL, MVT::v8f64, Mask, V1, V2, DAG))
10948 if (SDValue Unpck =
10949 lowerVectorShuffleWithUNPCK(DL, MVT::v8f64, Mask, V1, V2, DAG))
10952 return lowerVectorShuffleWithPERMV(DL, MVT::v8f64, Mask, V1, V2, DAG);
10955 /// \brief Handle lowering of 16-lane 32-bit floating point shuffles.
10956 static SDValue lowerV16F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10957 const X86Subtarget *Subtarget,
10958 SelectionDAG &DAG) {
10960 assert(V1.getSimpleValueType() == MVT::v16f32 && "Bad operand type!");
10961 assert(V2.getSimpleValueType() == MVT::v16f32 && "Bad operand type!");
10962 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10963 ArrayRef<int> Mask = SVOp->getMask();
10964 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
10966 if (SDValue Unpck =
10967 lowerVectorShuffleWithUNPCK(DL, MVT::v16f32, Mask, V1, V2, DAG))
10970 return lowerVectorShuffleWithPERMV(DL, MVT::v16f32, Mask, V1, V2, DAG);
10973 /// \brief Handle lowering of 8-lane 64-bit integer shuffles.
10974 static SDValue lowerV8I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10975 const X86Subtarget *Subtarget,
10976 SelectionDAG &DAG) {
10978 assert(V1.getSimpleValueType() == MVT::v8i64 && "Bad operand type!");
10979 assert(V2.getSimpleValueType() == MVT::v8i64 && "Bad operand type!");
10980 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10981 ArrayRef<int> Mask = SVOp->getMask();
10982 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10984 if (SDValue Shuf128 =
10985 lowerV4X128VectorShuffle(DL, MVT::v8i64, Mask, V1, V2, DAG))
10988 if (SDValue Unpck =
10989 lowerVectorShuffleWithUNPCK(DL, MVT::v8i64, Mask, V1, V2, DAG))
10992 return lowerVectorShuffleWithPERMV(DL, MVT::v8i64, Mask, V1, V2, DAG);
10995 /// \brief Handle lowering of 16-lane 32-bit integer shuffles.
10996 static SDValue lowerV16I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10997 const X86Subtarget *Subtarget,
10998 SelectionDAG &DAG) {
11000 assert(V1.getSimpleValueType() == MVT::v16i32 && "Bad operand type!");
11001 assert(V2.getSimpleValueType() == MVT::v16i32 && "Bad operand type!");
11002 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11003 ArrayRef<int> Mask = SVOp->getMask();
11004 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
11006 if (SDValue Unpck =
11007 lowerVectorShuffleWithUNPCK(DL, MVT::v16i32, Mask, V1, V2, DAG))
11010 return lowerVectorShuffleWithPERMV(DL, MVT::v16i32, Mask, V1, V2, DAG);
11013 /// \brief Handle lowering of 32-lane 16-bit integer shuffles.
11014 static SDValue lowerV32I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
11015 const X86Subtarget *Subtarget,
11016 SelectionDAG &DAG) {
11018 assert(V1.getSimpleValueType() == MVT::v32i16 && "Bad operand type!");
11019 assert(V2.getSimpleValueType() == MVT::v32i16 && "Bad operand type!");
11020 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11021 ArrayRef<int> Mask = SVOp->getMask();
11022 assert(Mask.size() == 32 && "Unexpected mask size for v32 shuffle!");
11023 assert(Subtarget->hasBWI() && "We can only lower v32i16 with AVX-512-BWI!");
11025 return lowerVectorShuffleWithPERMV(DL, MVT::v32i16, Mask, V1, V2, DAG);
11028 /// \brief Handle lowering of 64-lane 8-bit integer shuffles.
11029 static SDValue lowerV64I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
11030 const X86Subtarget *Subtarget,
11031 SelectionDAG &DAG) {
11033 assert(V1.getSimpleValueType() == MVT::v64i8 && "Bad operand type!");
11034 assert(V2.getSimpleValueType() == MVT::v64i8 && "Bad operand type!");
11035 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11036 ArrayRef<int> Mask = SVOp->getMask();
11037 assert(Mask.size() == 64 && "Unexpected mask size for v64 shuffle!");
11038 assert(Subtarget->hasBWI() && "We can only lower v64i8 with AVX-512-BWI!");
11040 // FIXME: Implement direct support for this type!
11041 return splitAndLowerVectorShuffle(DL, MVT::v64i8, V1, V2, Mask, DAG);
11044 /// \brief High-level routine to lower various 512-bit x86 vector shuffles.
11046 /// This routine either breaks down the specific type of a 512-bit x86 vector
11047 /// shuffle or splits it into two 256-bit shuffles and fuses the results back
11048 /// together based on the available instructions.
11049 static SDValue lower512BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
11050 MVT VT, const X86Subtarget *Subtarget,
11051 SelectionDAG &DAG) {
11053 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11054 ArrayRef<int> Mask = SVOp->getMask();
11055 assert(Subtarget->hasAVX512() &&
11056 "Cannot lower 512-bit vectors w/ basic ISA!");
11058 // Check for being able to broadcast a single element.
11059 if (SDValue Broadcast =
11060 lowerVectorShuffleAsBroadcast(DL, VT, V1, Mask, Subtarget, DAG))
11063 // Dispatch to each element type for lowering. If we don't have supprot for
11064 // specific element type shuffles at 512 bits, immediately split them and
11065 // lower them. Each lowering routine of a given type is allowed to assume that
11066 // the requisite ISA extensions for that element type are available.
11067 switch (VT.SimpleTy) {
11069 return lowerV8F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
11071 return lowerV16F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
11073 return lowerV8I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
11075 return lowerV16I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
11077 if (Subtarget->hasBWI())
11078 return lowerV32I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
11081 if (Subtarget->hasBWI())
11082 return lowerV64I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
11086 llvm_unreachable("Not a valid 512-bit x86 vector type!");
11089 // Otherwise fall back on splitting.
11090 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
11093 // Lower vXi1 vector shuffles.
11094 // There is no a dedicated instruction on AVX-512 that shuffles the masks.
11095 // The only way to shuffle bits is to sign-extend the mask vector to SIMD
11096 // vector, shuffle and then truncate it back.
11097 static SDValue lower1BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
11098 MVT VT, const X86Subtarget *Subtarget,
11099 SelectionDAG &DAG) {
11101 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11102 ArrayRef<int> Mask = SVOp->getMask();
11103 assert(Subtarget->hasAVX512() &&
11104 "Cannot lower 512-bit vectors w/o basic ISA!");
11106 switch (VT.SimpleTy) {
11108 llvm_unreachable("Expected a vector of i1 elements");
11110 ExtVT = MVT::v2i64;
11113 ExtVT = MVT::v4i32;
11116 ExtVT = MVT::v8i64; // Take 512-bit type, more shuffles on KNL
11119 ExtVT = MVT::v16i32;
11122 ExtVT = MVT::v32i16;
11125 ExtVT = MVT::v64i8;
11129 if (ISD::isBuildVectorAllZeros(V1.getNode()))
11130 V1 = getZeroVector(ExtVT, Subtarget, DAG, DL);
11131 else if (ISD::isBuildVectorAllOnes(V1.getNode()))
11132 V1 = getOnesVector(ExtVT, Subtarget, DAG, DL);
11134 V1 = DAG.getNode(ISD::SIGN_EXTEND, DL, ExtVT, V1);
11137 V2 = DAG.getUNDEF(ExtVT);
11138 else if (ISD::isBuildVectorAllZeros(V2.getNode()))
11139 V2 = getZeroVector(ExtVT, Subtarget, DAG, DL);
11140 else if (ISD::isBuildVectorAllOnes(V2.getNode()))
11141 V2 = getOnesVector(ExtVT, Subtarget, DAG, DL);
11143 V2 = DAG.getNode(ISD::SIGN_EXTEND, DL, ExtVT, V2);
11144 return DAG.getNode(ISD::TRUNCATE, DL, VT,
11145 DAG.getVectorShuffle(ExtVT, DL, V1, V2, Mask));
11147 /// \brief Top-level lowering for x86 vector shuffles.
11149 /// This handles decomposition, canonicalization, and lowering of all x86
11150 /// vector shuffles. Most of the specific lowering strategies are encapsulated
11151 /// above in helper routines. The canonicalization attempts to widen shuffles
11152 /// to involve fewer lanes of wider elements, consolidate symmetric patterns
11153 /// s.t. only one of the two inputs needs to be tested, etc.
11154 static SDValue lowerVectorShuffle(SDValue Op, const X86Subtarget *Subtarget,
11155 SelectionDAG &DAG) {
11156 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11157 ArrayRef<int> Mask = SVOp->getMask();
11158 SDValue V1 = Op.getOperand(0);
11159 SDValue V2 = Op.getOperand(1);
11160 MVT VT = Op.getSimpleValueType();
11161 int NumElements = VT.getVectorNumElements();
11163 bool Is1BitVector = (VT.getVectorElementType() == MVT::i1);
11165 assert((VT.getSizeInBits() != 64 || Is1BitVector) &&
11166 "Can't lower MMX shuffles");
11168 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
11169 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
11170 if (V1IsUndef && V2IsUndef)
11171 return DAG.getUNDEF(VT);
11173 // When we create a shuffle node we put the UNDEF node to second operand,
11174 // but in some cases the first operand may be transformed to UNDEF.
11175 // In this case we should just commute the node.
11177 return DAG.getCommutedVectorShuffle(*SVOp);
11179 // Check for non-undef masks pointing at an undef vector and make the masks
11180 // undef as well. This makes it easier to match the shuffle based solely on
11184 if (M >= NumElements) {
11185 SmallVector<int, 8> NewMask(Mask.begin(), Mask.end());
11186 for (int &M : NewMask)
11187 if (M >= NumElements)
11189 return DAG.getVectorShuffle(VT, dl, V1, V2, NewMask);
11192 // We actually see shuffles that are entirely re-arrangements of a set of
11193 // zero inputs. This mostly happens while decomposing complex shuffles into
11194 // simple ones. Directly lower these as a buildvector of zeros.
11195 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
11196 if (Zeroable.all())
11197 return getZeroVector(VT, Subtarget, DAG, dl);
11199 // Try to collapse shuffles into using a vector type with fewer elements but
11200 // wider element types. We cap this to not form integers or floating point
11201 // elements wider than 64 bits, but it might be interesting to form i128
11202 // integers to handle flipping the low and high halves of AVX 256-bit vectors.
11203 SmallVector<int, 16> WidenedMask;
11204 if (VT.getScalarSizeInBits() < 64 && !Is1BitVector &&
11205 canWidenShuffleElements(Mask, WidenedMask)) {
11206 MVT NewEltVT = VT.isFloatingPoint()
11207 ? MVT::getFloatingPointVT(VT.getScalarSizeInBits() * 2)
11208 : MVT::getIntegerVT(VT.getScalarSizeInBits() * 2);
11209 MVT NewVT = MVT::getVectorVT(NewEltVT, VT.getVectorNumElements() / 2);
11210 // Make sure that the new vector type is legal. For example, v2f64 isn't
11212 if (DAG.getTargetLoweringInfo().isTypeLegal(NewVT)) {
11213 V1 = DAG.getBitcast(NewVT, V1);
11214 V2 = DAG.getBitcast(NewVT, V2);
11215 return DAG.getBitcast(
11216 VT, DAG.getVectorShuffle(NewVT, dl, V1, V2, WidenedMask));
11220 int NumV1Elements = 0, NumUndefElements = 0, NumV2Elements = 0;
11221 for (int M : SVOp->getMask())
11223 ++NumUndefElements;
11224 else if (M < NumElements)
11229 // Commute the shuffle as needed such that more elements come from V1 than
11230 // V2. This allows us to match the shuffle pattern strictly on how many
11231 // elements come from V1 without handling the symmetric cases.
11232 if (NumV2Elements > NumV1Elements)
11233 return DAG.getCommutedVectorShuffle(*SVOp);
11235 // When the number of V1 and V2 elements are the same, try to minimize the
11236 // number of uses of V2 in the low half of the vector. When that is tied,
11237 // ensure that the sum of indices for V1 is equal to or lower than the sum
11238 // indices for V2. When those are equal, try to ensure that the number of odd
11239 // indices for V1 is lower than the number of odd indices for V2.
11240 if (NumV1Elements == NumV2Elements) {
11241 int LowV1Elements = 0, LowV2Elements = 0;
11242 for (int M : SVOp->getMask().slice(0, NumElements / 2))
11243 if (M >= NumElements)
11247 if (LowV2Elements > LowV1Elements) {
11248 return DAG.getCommutedVectorShuffle(*SVOp);
11249 } else if (LowV2Elements == LowV1Elements) {
11250 int SumV1Indices = 0, SumV2Indices = 0;
11251 for (int i = 0, Size = SVOp->getMask().size(); i < Size; ++i)
11252 if (SVOp->getMask()[i] >= NumElements)
11254 else if (SVOp->getMask()[i] >= 0)
11256 if (SumV2Indices < SumV1Indices) {
11257 return DAG.getCommutedVectorShuffle(*SVOp);
11258 } else if (SumV2Indices == SumV1Indices) {
11259 int NumV1OddIndices = 0, NumV2OddIndices = 0;
11260 for (int i = 0, Size = SVOp->getMask().size(); i < Size; ++i)
11261 if (SVOp->getMask()[i] >= NumElements)
11262 NumV2OddIndices += i % 2;
11263 else if (SVOp->getMask()[i] >= 0)
11264 NumV1OddIndices += i % 2;
11265 if (NumV2OddIndices < NumV1OddIndices)
11266 return DAG.getCommutedVectorShuffle(*SVOp);
11271 // For each vector width, delegate to a specialized lowering routine.
11272 if (VT.is128BitVector())
11273 return lower128BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
11275 if (VT.is256BitVector())
11276 return lower256BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
11278 if (VT.is512BitVector())
11279 return lower512BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
11282 return lower1BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
11283 llvm_unreachable("Unimplemented!");
11286 // This function assumes its argument is a BUILD_VECTOR of constants or
11287 // undef SDNodes. i.e: ISD::isBuildVectorOfConstantSDNodes(BuildVector) is
11289 static bool BUILD_VECTORtoBlendMask(BuildVectorSDNode *BuildVector,
11290 unsigned &MaskValue) {
11292 unsigned NumElems = BuildVector->getNumOperands();
11294 // There are 2 lanes if (NumElems > 8), and 1 lane otherwise.
11295 // We don't handle the >2 lanes case right now.
11296 unsigned NumLanes = (NumElems - 1) / 8 + 1;
11300 unsigned NumElemsInLane = NumElems / NumLanes;
11302 // Blend for v16i16 should be symmetric for the both lanes.
11303 for (unsigned i = 0; i < NumElemsInLane; ++i) {
11304 SDValue EltCond = BuildVector->getOperand(i);
11305 SDValue SndLaneEltCond =
11306 (NumLanes == 2) ? BuildVector->getOperand(i + NumElemsInLane) : EltCond;
11308 int Lane1Cond = -1, Lane2Cond = -1;
11309 if (isa<ConstantSDNode>(EltCond))
11310 Lane1Cond = !isZero(EltCond);
11311 if (isa<ConstantSDNode>(SndLaneEltCond))
11312 Lane2Cond = !isZero(SndLaneEltCond);
11314 unsigned LaneMask = 0;
11315 if (Lane1Cond == Lane2Cond || Lane2Cond < 0)
11316 // Lane1Cond != 0, means we want the first argument.
11317 // Lane1Cond == 0, means we want the second argument.
11318 // The encoding of this argument is 0 for the first argument, 1
11319 // for the second. Therefore, invert the condition.
11320 LaneMask = !Lane1Cond << i;
11321 else if (Lane1Cond < 0)
11322 LaneMask = !Lane2Cond << i;
11326 MaskValue |= LaneMask;
11328 MaskValue |= LaneMask << NumElemsInLane;
11333 /// \brief Try to lower a VSELECT instruction to a vector shuffle.
11334 static SDValue lowerVSELECTtoVectorShuffle(SDValue Op,
11335 const X86Subtarget *Subtarget,
11336 SelectionDAG &DAG) {
11337 SDValue Cond = Op.getOperand(0);
11338 SDValue LHS = Op.getOperand(1);
11339 SDValue RHS = Op.getOperand(2);
11341 MVT VT = Op.getSimpleValueType();
11343 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
11345 auto *CondBV = cast<BuildVectorSDNode>(Cond);
11347 // Only non-legal VSELECTs reach this lowering, convert those into generic
11348 // shuffles and re-use the shuffle lowering path for blends.
11349 SmallVector<int, 32> Mask;
11350 for (int i = 0, Size = VT.getVectorNumElements(); i < Size; ++i) {
11351 SDValue CondElt = CondBV->getOperand(i);
11353 isa<ConstantSDNode>(CondElt) ? i + (isZero(CondElt) ? Size : 0) : -1);
11355 return DAG.getVectorShuffle(VT, dl, LHS, RHS, Mask);
11358 SDValue X86TargetLowering::LowerVSELECT(SDValue Op, SelectionDAG &DAG) const {
11359 // A vselect where all conditions and data are constants can be optimized into
11360 // a single vector load by SelectionDAGLegalize::ExpandBUILD_VECTOR().
11361 if (ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(0).getNode()) &&
11362 ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(1).getNode()) &&
11363 ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(2).getNode()))
11366 // Try to lower this to a blend-style vector shuffle. This can handle all
11367 // constant condition cases.
11368 if (SDValue BlendOp = lowerVSELECTtoVectorShuffle(Op, Subtarget, DAG))
11371 // Variable blends are only legal from SSE4.1 onward.
11372 if (!Subtarget->hasSSE41())
11375 // Only some types will be legal on some subtargets. If we can emit a legal
11376 // VSELECT-matching blend, return Op, and but if we need to expand, return
11378 switch (Op.getSimpleValueType().SimpleTy) {
11380 // Most of the vector types have blends past SSE4.1.
11384 // The byte blends for AVX vectors were introduced only in AVX2.
11385 if (Subtarget->hasAVX2())
11392 // AVX-512 BWI and VLX features support VSELECT with i16 elements.
11393 if (Subtarget->hasBWI() && Subtarget->hasVLX())
11396 // FIXME: We should custom lower this by fixing the condition and using i8
11402 static SDValue LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) {
11403 MVT VT = Op.getSimpleValueType();
11406 if (!Op.getOperand(0).getSimpleValueType().is128BitVector())
11409 if (VT.getSizeInBits() == 8) {
11410 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
11411 Op.getOperand(0), Op.getOperand(1));
11412 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
11413 DAG.getValueType(VT));
11414 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
11417 if (VT.getSizeInBits() == 16) {
11418 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
11419 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
11421 return DAG.getNode(
11422 ISD::TRUNCATE, dl, MVT::i16,
11423 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
11424 DAG.getBitcast(MVT::v4i32, Op.getOperand(0)),
11425 Op.getOperand(1)));
11426 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
11427 Op.getOperand(0), Op.getOperand(1));
11428 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
11429 DAG.getValueType(VT));
11430 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
11433 if (VT == MVT::f32) {
11434 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
11435 // the result back to FR32 register. It's only worth matching if the
11436 // result has a single use which is a store or a bitcast to i32. And in
11437 // the case of a store, it's not worth it if the index is a constant 0,
11438 // because a MOVSSmr can be used instead, which is smaller and faster.
11439 if (!Op.hasOneUse())
11441 SDNode *User = *Op.getNode()->use_begin();
11442 if ((User->getOpcode() != ISD::STORE ||
11443 (isa<ConstantSDNode>(Op.getOperand(1)) &&
11444 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
11445 (User->getOpcode() != ISD::BITCAST ||
11446 User->getValueType(0) != MVT::i32))
11448 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
11449 DAG.getBitcast(MVT::v4i32, Op.getOperand(0)),
11451 return DAG.getBitcast(MVT::f32, Extract);
11454 if (VT == MVT::i32 || VT == MVT::i64) {
11455 // ExtractPS/pextrq works with constant index.
11456 if (isa<ConstantSDNode>(Op.getOperand(1)))
11462 /// Extract one bit from mask vector, like v16i1 or v8i1.
11463 /// AVX-512 feature.
11465 X86TargetLowering::ExtractBitFromMaskVector(SDValue Op, SelectionDAG &DAG) const {
11466 SDValue Vec = Op.getOperand(0);
11468 MVT VecVT = Vec.getSimpleValueType();
11469 SDValue Idx = Op.getOperand(1);
11470 MVT EltVT = Op.getSimpleValueType();
11472 assert((EltVT == MVT::i1) && "Unexpected operands in ExtractBitFromMaskVector");
11473 assert((VecVT.getVectorNumElements() <= 16 || Subtarget->hasBWI()) &&
11474 "Unexpected vector type in ExtractBitFromMaskVector");
11476 // variable index can't be handled in mask registers,
11477 // extend vector to VR512
11478 if (!isa<ConstantSDNode>(Idx)) {
11479 MVT ExtVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
11480 SDValue Ext = DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVT, Vec);
11481 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
11482 ExtVT.getVectorElementType(), Ext, Idx);
11483 return DAG.getNode(ISD::TRUNCATE, dl, EltVT, Elt);
11486 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
11487 const TargetRegisterClass* rc = getRegClassFor(VecVT);
11488 if (!Subtarget->hasDQI() && (VecVT.getVectorNumElements() <= 8))
11489 rc = getRegClassFor(MVT::v16i1);
11490 unsigned MaxSift = rc->getSize()*8 - 1;
11491 Vec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, Vec,
11492 DAG.getConstant(MaxSift - IdxVal, dl, MVT::i8));
11493 Vec = DAG.getNode(X86ISD::VSRLI, dl, VecVT, Vec,
11494 DAG.getConstant(MaxSift, dl, MVT::i8));
11495 return DAG.getNode(X86ISD::VEXTRACT, dl, MVT::i1, Vec,
11496 DAG.getIntPtrConstant(0, dl));
11500 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
11501 SelectionDAG &DAG) const {
11503 SDValue Vec = Op.getOperand(0);
11504 MVT VecVT = Vec.getSimpleValueType();
11505 SDValue Idx = Op.getOperand(1);
11507 if (Op.getSimpleValueType() == MVT::i1)
11508 return ExtractBitFromMaskVector(Op, DAG);
11510 if (!isa<ConstantSDNode>(Idx)) {
11511 if (VecVT.is512BitVector() ||
11512 (VecVT.is256BitVector() && Subtarget->hasInt256() &&
11513 VecVT.getVectorElementType().getSizeInBits() == 32)) {
11516 MVT::getIntegerVT(VecVT.getVectorElementType().getSizeInBits());
11517 MVT MaskVT = MVT::getVectorVT(MaskEltVT, VecVT.getSizeInBits() /
11518 MaskEltVT.getSizeInBits());
11520 Idx = DAG.getZExtOrTrunc(Idx, dl, MaskEltVT);
11521 auto PtrVT = getPointerTy(DAG.getDataLayout());
11522 SDValue Mask = DAG.getNode(X86ISD::VINSERT, dl, MaskVT,
11523 getZeroVector(MaskVT, Subtarget, DAG, dl), Idx,
11524 DAG.getConstant(0, dl, PtrVT));
11525 SDValue Perm = DAG.getNode(X86ISD::VPERMV, dl, VecVT, Mask, Vec);
11526 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Perm,
11527 DAG.getConstant(0, dl, PtrVT));
11532 // If this is a 256-bit vector result, first extract the 128-bit vector and
11533 // then extract the element from the 128-bit vector.
11534 if (VecVT.is256BitVector() || VecVT.is512BitVector()) {
11536 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
11537 // Get the 128-bit vector.
11538 Vec = Extract128BitVector(Vec, IdxVal, DAG, dl);
11539 MVT EltVT = VecVT.getVectorElementType();
11541 unsigned ElemsPerChunk = 128 / EltVT.getSizeInBits();
11542 assert(isPowerOf2_32(ElemsPerChunk) && "Elements per chunk not power of 2");
11544 // Find IdxVal modulo ElemsPerChunk. Since ElemsPerChunk is a power of 2
11545 // this can be done with a mask.
11546 IdxVal &= ElemsPerChunk - 1;
11547 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec,
11548 DAG.getConstant(IdxVal, dl, MVT::i32));
11551 assert(VecVT.is128BitVector() && "Unexpected vector length");
11553 if (Subtarget->hasSSE41())
11554 if (SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG))
11557 MVT VT = Op.getSimpleValueType();
11558 // TODO: handle v16i8.
11559 if (VT.getSizeInBits() == 16) {
11560 SDValue Vec = Op.getOperand(0);
11561 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
11563 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
11564 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
11565 DAG.getBitcast(MVT::v4i32, Vec),
11566 Op.getOperand(1)));
11567 // Transform it so it match pextrw which produces a 32-bit result.
11568 MVT EltVT = MVT::i32;
11569 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
11570 Op.getOperand(0), Op.getOperand(1));
11571 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
11572 DAG.getValueType(VT));
11573 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
11576 if (VT.getSizeInBits() == 32) {
11577 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
11581 // SHUFPS the element to the lowest double word, then movss.
11582 int Mask[4] = { static_cast<int>(Idx), -1, -1, -1 };
11583 MVT VVT = Op.getOperand(0).getSimpleValueType();
11584 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
11585 DAG.getUNDEF(VVT), Mask);
11586 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
11587 DAG.getIntPtrConstant(0, dl));
11590 if (VT.getSizeInBits() == 64) {
11591 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
11592 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
11593 // to match extract_elt for f64.
11594 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
11598 // UNPCKHPD the element to the lowest double word, then movsd.
11599 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
11600 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
11601 int Mask[2] = { 1, -1 };
11602 MVT VVT = Op.getOperand(0).getSimpleValueType();
11603 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
11604 DAG.getUNDEF(VVT), Mask);
11605 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
11606 DAG.getIntPtrConstant(0, dl));
11612 /// Insert one bit to mask vector, like v16i1 or v8i1.
11613 /// AVX-512 feature.
11615 X86TargetLowering::InsertBitToMaskVector(SDValue Op, SelectionDAG &DAG) const {
11617 SDValue Vec = Op.getOperand(0);
11618 SDValue Elt = Op.getOperand(1);
11619 SDValue Idx = Op.getOperand(2);
11620 MVT VecVT = Vec.getSimpleValueType();
11622 if (!isa<ConstantSDNode>(Idx)) {
11623 // Non constant index. Extend source and destination,
11624 // insert element and then truncate the result.
11625 MVT ExtVecVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
11626 MVT ExtEltVT = (VecVT == MVT::v8i1 ? MVT::i64 : MVT::i32);
11627 SDValue ExtOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ExtVecVT,
11628 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVecVT, Vec),
11629 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtEltVT, Elt), Idx);
11630 return DAG.getNode(ISD::TRUNCATE, dl, VecVT, ExtOp);
11633 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
11634 SDValue EltInVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Elt);
11636 EltInVec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, EltInVec,
11637 DAG.getConstant(IdxVal, dl, MVT::i8));
11638 if (Vec.getOpcode() == ISD::UNDEF)
11640 return DAG.getNode(ISD::OR, dl, VecVT, Vec, EltInVec);
11643 SDValue X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op,
11644 SelectionDAG &DAG) const {
11645 MVT VT = Op.getSimpleValueType();
11646 MVT EltVT = VT.getVectorElementType();
11648 if (EltVT == MVT::i1)
11649 return InsertBitToMaskVector(Op, DAG);
11652 SDValue N0 = Op.getOperand(0);
11653 SDValue N1 = Op.getOperand(1);
11654 SDValue N2 = Op.getOperand(2);
11655 if (!isa<ConstantSDNode>(N2))
11657 auto *N2C = cast<ConstantSDNode>(N2);
11658 unsigned IdxVal = N2C->getZExtValue();
11660 // If the vector is wider than 128 bits, extract the 128-bit subvector, insert
11661 // into that, and then insert the subvector back into the result.
11662 if (VT.is256BitVector() || VT.is512BitVector()) {
11663 // With a 256-bit vector, we can insert into the zero element efficiently
11664 // using a blend if we have AVX or AVX2 and the right data type.
11665 if (VT.is256BitVector() && IdxVal == 0) {
11666 // TODO: It is worthwhile to cast integer to floating point and back
11667 // and incur a domain crossing penalty if that's what we'll end up
11668 // doing anyway after extracting to a 128-bit vector.
11669 if ((Subtarget->hasAVX() && (EltVT == MVT::f64 || EltVT == MVT::f32)) ||
11670 (Subtarget->hasAVX2() && EltVT == MVT::i32)) {
11671 SDValue N1Vec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, N1);
11672 N2 = DAG.getIntPtrConstant(1, dl);
11673 return DAG.getNode(X86ISD::BLENDI, dl, VT, N0, N1Vec, N2);
11677 // Get the desired 128-bit vector chunk.
11678 SDValue V = Extract128BitVector(N0, IdxVal, DAG, dl);
11680 // Insert the element into the desired chunk.
11681 unsigned NumEltsIn128 = 128 / EltVT.getSizeInBits();
11682 assert(isPowerOf2_32(NumEltsIn128));
11683 // Since NumEltsIn128 is a power of 2 we can use mask instead of modulo.
11684 unsigned IdxIn128 = IdxVal & (NumEltsIn128 - 1);
11686 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V, N1,
11687 DAG.getConstant(IdxIn128, dl, MVT::i32));
11689 // Insert the changed part back into the bigger vector
11690 return Insert128BitVector(N0, V, IdxVal, DAG, dl);
11692 assert(VT.is128BitVector() && "Only 128-bit vector types should be left!");
11694 if (Subtarget->hasSSE41()) {
11695 if (EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) {
11697 if (VT == MVT::v8i16) {
11698 Opc = X86ISD::PINSRW;
11700 assert(VT == MVT::v16i8);
11701 Opc = X86ISD::PINSRB;
11704 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
11706 if (N1.getValueType() != MVT::i32)
11707 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
11708 if (N2.getValueType() != MVT::i32)
11709 N2 = DAG.getIntPtrConstant(IdxVal, dl);
11710 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
11713 if (EltVT == MVT::f32) {
11714 // Bits [7:6] of the constant are the source select. This will always be
11715 // zero here. The DAG Combiner may combine an extract_elt index into
11716 // these bits. For example (insert (extract, 3), 2) could be matched by
11717 // putting the '3' into bits [7:6] of X86ISD::INSERTPS.
11718 // Bits [5:4] of the constant are the destination select. This is the
11719 // value of the incoming immediate.
11720 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
11721 // combine either bitwise AND or insert of float 0.0 to set these bits.
11723 bool MinSize = DAG.getMachineFunction().getFunction()->optForMinSize();
11724 if (IdxVal == 0 && (!MinSize || !MayFoldLoad(N1))) {
11725 // If this is an insertion of 32-bits into the low 32-bits of
11726 // a vector, we prefer to generate a blend with immediate rather
11727 // than an insertps. Blends are simpler operations in hardware and so
11728 // will always have equal or better performance than insertps.
11729 // But if optimizing for size and there's a load folding opportunity,
11730 // generate insertps because blendps does not have a 32-bit memory
11732 N2 = DAG.getIntPtrConstant(1, dl);
11733 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
11734 return DAG.getNode(X86ISD::BLENDI, dl, VT, N0, N1, N2);
11736 N2 = DAG.getIntPtrConstant(IdxVal << 4, dl);
11737 // Create this as a scalar to vector..
11738 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
11739 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
11742 if (EltVT == MVT::i32 || EltVT == MVT::i64) {
11743 // PINSR* works with constant index.
11748 if (EltVT == MVT::i8)
11751 if (EltVT.getSizeInBits() == 16) {
11752 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
11753 // as its second argument.
11754 if (N1.getValueType() != MVT::i32)
11755 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
11756 if (N2.getValueType() != MVT::i32)
11757 N2 = DAG.getIntPtrConstant(IdxVal, dl);
11758 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);
11763 static SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) {
11765 MVT OpVT = Op.getSimpleValueType();
11767 // If this is a 256-bit vector result, first insert into a 128-bit
11768 // vector and then insert into the 256-bit vector.
11769 if (!OpVT.is128BitVector()) {
11770 // Insert into a 128-bit vector.
11771 unsigned SizeFactor = OpVT.getSizeInBits()/128;
11772 MVT VT128 = MVT::getVectorVT(OpVT.getVectorElementType(),
11773 OpVT.getVectorNumElements() / SizeFactor);
11775 Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Op.getOperand(0));
11777 // Insert the 128-bit vector.
11778 return Insert128BitVector(DAG.getUNDEF(OpVT), Op, 0, DAG, dl);
11781 if (OpVT == MVT::v1i64 &&
11782 Op.getOperand(0).getValueType() == MVT::i64)
11783 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
11785 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
11786 assert(OpVT.is128BitVector() && "Expected an SSE type!");
11787 return DAG.getBitcast(
11788 OpVT, DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, AnyExt));
11791 // Lower a node with an EXTRACT_SUBVECTOR opcode. This may result in
11792 // a simple subregister reference or explicit instructions to grab
11793 // upper bits of a vector.
11794 static SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
11795 SelectionDAG &DAG) {
11797 SDValue In = Op.getOperand(0);
11798 SDValue Idx = Op.getOperand(1);
11799 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
11800 MVT ResVT = Op.getSimpleValueType();
11801 MVT InVT = In.getSimpleValueType();
11803 if (Subtarget->hasFp256()) {
11804 if (ResVT.is128BitVector() &&
11805 (InVT.is256BitVector() || InVT.is512BitVector()) &&
11806 isa<ConstantSDNode>(Idx)) {
11807 return Extract128BitVector(In, IdxVal, DAG, dl);
11809 if (ResVT.is256BitVector() && InVT.is512BitVector() &&
11810 isa<ConstantSDNode>(Idx)) {
11811 return Extract256BitVector(In, IdxVal, DAG, dl);
11817 // Lower a node with an INSERT_SUBVECTOR opcode. This may result in a
11818 // simple superregister reference or explicit instructions to insert
11819 // the upper bits of a vector.
11820 static SDValue LowerINSERT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
11821 SelectionDAG &DAG) {
11822 if (!Subtarget->hasAVX())
11826 SDValue Vec = Op.getOperand(0);
11827 SDValue SubVec = Op.getOperand(1);
11828 SDValue Idx = Op.getOperand(2);
11830 if (!isa<ConstantSDNode>(Idx))
11833 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
11834 MVT OpVT = Op.getSimpleValueType();
11835 MVT SubVecVT = SubVec.getSimpleValueType();
11837 // Fold two 16-byte subvector loads into one 32-byte load:
11838 // (insert_subvector (insert_subvector undef, (load addr), 0),
11839 // (load addr + 16), Elts/2)
11841 if ((IdxVal == OpVT.getVectorNumElements() / 2) &&
11842 Vec.getOpcode() == ISD::INSERT_SUBVECTOR &&
11843 OpVT.is256BitVector() && SubVecVT.is128BitVector()) {
11844 auto *Idx2 = dyn_cast<ConstantSDNode>(Vec.getOperand(2));
11845 if (Idx2 && Idx2->getZExtValue() == 0) {
11846 SDValue SubVec2 = Vec.getOperand(1);
11847 // If needed, look through a bitcast to get to the load.
11848 if (SubVec2.getNode() && SubVec2.getOpcode() == ISD::BITCAST)
11849 SubVec2 = SubVec2.getOperand(0);
11851 if (auto *FirstLd = dyn_cast<LoadSDNode>(SubVec2)) {
11853 unsigned Alignment = FirstLd->getAlignment();
11854 unsigned AS = FirstLd->getAddressSpace();
11855 const X86TargetLowering *TLI = Subtarget->getTargetLowering();
11856 if (TLI->allowsMemoryAccess(*DAG.getContext(), DAG.getDataLayout(),
11857 OpVT, AS, Alignment, &Fast) && Fast) {
11858 SDValue Ops[] = { SubVec2, SubVec };
11859 if (SDValue Ld = EltsFromConsecutiveLoads(OpVT, Ops, dl, DAG, false))
11866 if ((OpVT.is256BitVector() || OpVT.is512BitVector()) &&
11867 SubVecVT.is128BitVector())
11868 return Insert128BitVector(Vec, SubVec, IdxVal, DAG, dl);
11870 if (OpVT.is512BitVector() && SubVecVT.is256BitVector())
11871 return Insert256BitVector(Vec, SubVec, IdxVal, DAG, dl);
11873 if (OpVT.getVectorElementType() == MVT::i1)
11874 return Insert1BitVector(Op, DAG);
11879 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
11880 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
11881 // one of the above mentioned nodes. It has to be wrapped because otherwise
11882 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
11883 // be used to form addressing mode. These wrapped nodes will be selected
11886 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
11887 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
11889 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
11890 // global base reg.
11891 unsigned char OpFlag = 0;
11892 unsigned WrapperKind = X86ISD::Wrapper;
11893 CodeModel::Model M = DAG.getTarget().getCodeModel();
11895 if (Subtarget->isPICStyleRIPRel() &&
11896 (M == CodeModel::Small || M == CodeModel::Kernel))
11897 WrapperKind = X86ISD::WrapperRIP;
11898 else if (Subtarget->isPICStyleGOT())
11899 OpFlag = X86II::MO_GOTOFF;
11900 else if (Subtarget->isPICStyleStubPIC())
11901 OpFlag = X86II::MO_PIC_BASE_OFFSET;
11903 auto PtrVT = getPointerTy(DAG.getDataLayout());
11904 SDValue Result = DAG.getTargetConstantPool(
11905 CP->getConstVal(), PtrVT, CP->getAlignment(), CP->getOffset(), OpFlag);
11907 Result = DAG.getNode(WrapperKind, DL, PtrVT, Result);
11908 // With PIC, the address is actually $g + Offset.
11911 DAG.getNode(ISD::ADD, DL, PtrVT,
11912 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), Result);
11918 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
11919 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
11921 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
11922 // global base reg.
11923 unsigned char OpFlag = 0;
11924 unsigned WrapperKind = X86ISD::Wrapper;
11925 CodeModel::Model M = DAG.getTarget().getCodeModel();
11927 if (Subtarget->isPICStyleRIPRel() &&
11928 (M == CodeModel::Small || M == CodeModel::Kernel))
11929 WrapperKind = X86ISD::WrapperRIP;
11930 else if (Subtarget->isPICStyleGOT())
11931 OpFlag = X86II::MO_GOTOFF;
11932 else if (Subtarget->isPICStyleStubPIC())
11933 OpFlag = X86II::MO_PIC_BASE_OFFSET;
11935 auto PtrVT = getPointerTy(DAG.getDataLayout());
11936 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, OpFlag);
11938 Result = DAG.getNode(WrapperKind, DL, PtrVT, Result);
11940 // With PIC, the address is actually $g + Offset.
11943 DAG.getNode(ISD::ADD, DL, PtrVT,
11944 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), Result);
11950 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const {
11951 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
11953 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
11954 // global base reg.
11955 unsigned char OpFlag = 0;
11956 unsigned WrapperKind = X86ISD::Wrapper;
11957 CodeModel::Model M = DAG.getTarget().getCodeModel();
11959 if (Subtarget->isPICStyleRIPRel() &&
11960 (M == CodeModel::Small || M == CodeModel::Kernel)) {
11961 if (Subtarget->isTargetDarwin() || Subtarget->isTargetELF())
11962 OpFlag = X86II::MO_GOTPCREL;
11963 WrapperKind = X86ISD::WrapperRIP;
11964 } else if (Subtarget->isPICStyleGOT()) {
11965 OpFlag = X86II::MO_GOT;
11966 } else if (Subtarget->isPICStyleStubPIC()) {
11967 OpFlag = X86II::MO_DARWIN_NONLAZY_PIC_BASE;
11968 } else if (Subtarget->isPICStyleStubNoDynamic()) {
11969 OpFlag = X86II::MO_DARWIN_NONLAZY;
11972 auto PtrVT = getPointerTy(DAG.getDataLayout());
11973 SDValue Result = DAG.getTargetExternalSymbol(Sym, PtrVT, OpFlag);
11976 Result = DAG.getNode(WrapperKind, DL, PtrVT, Result);
11978 // With PIC, the address is actually $g + Offset.
11979 if (DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
11980 !Subtarget->is64Bit()) {
11982 DAG.getNode(ISD::ADD, DL, PtrVT,
11983 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), Result);
11986 // For symbols that require a load from a stub to get the address, emit the
11988 if (isGlobalStubReference(OpFlag))
11989 Result = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), Result,
11990 MachinePointerInfo::getGOT(DAG.getMachineFunction()),
11991 false, false, false, 0);
11997 X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
11998 // Create the TargetBlockAddressAddress node.
11999 unsigned char OpFlags =
12000 Subtarget->ClassifyBlockAddressReference();
12001 CodeModel::Model M = DAG.getTarget().getCodeModel();
12002 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
12003 int64_t Offset = cast<BlockAddressSDNode>(Op)->getOffset();
12005 auto PtrVT = getPointerTy(DAG.getDataLayout());
12006 SDValue Result = DAG.getTargetBlockAddress(BA, PtrVT, Offset, OpFlags);
12008 if (Subtarget->isPICStyleRIPRel() &&
12009 (M == CodeModel::Small || M == CodeModel::Kernel))
12010 Result = DAG.getNode(X86ISD::WrapperRIP, dl, PtrVT, Result);
12012 Result = DAG.getNode(X86ISD::Wrapper, dl, PtrVT, Result);
12014 // With PIC, the address is actually $g + Offset.
12015 if (isGlobalRelativeToPICBase(OpFlags)) {
12016 Result = DAG.getNode(ISD::ADD, dl, PtrVT,
12017 DAG.getNode(X86ISD::GlobalBaseReg, dl, PtrVT), Result);
12024 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, SDLoc dl,
12025 int64_t Offset, SelectionDAG &DAG) const {
12026 // Create the TargetGlobalAddress node, folding in the constant
12027 // offset if it is legal.
12028 unsigned char OpFlags =
12029 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget());
12030 CodeModel::Model M = DAG.getTarget().getCodeModel();
12031 auto PtrVT = getPointerTy(DAG.getDataLayout());
12033 if (OpFlags == X86II::MO_NO_FLAG &&
12034 X86::isOffsetSuitableForCodeModel(Offset, M)) {
12035 // A direct static reference to a global.
12036 Result = DAG.getTargetGlobalAddress(GV, dl, PtrVT, Offset);
12039 Result = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, OpFlags);
12042 if (Subtarget->isPICStyleRIPRel() &&
12043 (M == CodeModel::Small || M == CodeModel::Kernel))
12044 Result = DAG.getNode(X86ISD::WrapperRIP, dl, PtrVT, Result);
12046 Result = DAG.getNode(X86ISD::Wrapper, dl, PtrVT, Result);
12048 // With PIC, the address is actually $g + Offset.
12049 if (isGlobalRelativeToPICBase(OpFlags)) {
12050 Result = DAG.getNode(ISD::ADD, dl, PtrVT,
12051 DAG.getNode(X86ISD::GlobalBaseReg, dl, PtrVT), Result);
12054 // For globals that require a load from a stub to get the address, emit the
12056 if (isGlobalStubReference(OpFlags))
12057 Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Result,
12058 MachinePointerInfo::getGOT(DAG.getMachineFunction()),
12059 false, false, false, 0);
12061 // If there was a non-zero offset that we didn't fold, create an explicit
12062 // addition for it.
12064 Result = DAG.getNode(ISD::ADD, dl, PtrVT, Result,
12065 DAG.getConstant(Offset, dl, PtrVT));
12071 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
12072 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
12073 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
12074 return LowerGlobalAddress(GV, SDLoc(Op), Offset, DAG);
12078 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
12079 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg,
12080 unsigned char OperandFlags, bool LocalDynamic = false) {
12081 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
12082 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
12084 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
12085 GA->getValueType(0),
12089 X86ISD::NodeType CallType = LocalDynamic ? X86ISD::TLSBASEADDR
12093 SDValue Ops[] = { Chain, TGA, *InFlag };
12094 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
12096 SDValue Ops[] = { Chain, TGA };
12097 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
12100 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
12101 MFI->setAdjustsStack(true);
12102 MFI->setHasCalls(true);
12104 SDValue Flag = Chain.getValue(1);
12105 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
12108 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
12110 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
12113 SDLoc dl(GA); // ? function entry point might be better
12114 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
12115 DAG.getNode(X86ISD::GlobalBaseReg,
12116 SDLoc(), PtrVT), InFlag);
12117 InFlag = Chain.getValue(1);
12119 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
12122 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
12124 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
12126 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT,
12127 X86::RAX, X86II::MO_TLSGD);
12130 static SDValue LowerToTLSLocalDynamicModel(GlobalAddressSDNode *GA,
12136 // Get the start address of the TLS block for this module.
12137 X86MachineFunctionInfo* MFI = DAG.getMachineFunction()
12138 .getInfo<X86MachineFunctionInfo>();
12139 MFI->incNumLocalDynamicTLSAccesses();
12143 Base = GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT, X86::RAX,
12144 X86II::MO_TLSLD, /*LocalDynamic=*/true);
12147 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
12148 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), InFlag);
12149 InFlag = Chain.getValue(1);
12150 Base = GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX,
12151 X86II::MO_TLSLDM, /*LocalDynamic=*/true);
12154 // Note: the CleanupLocalDynamicTLSPass will remove redundant computations
12158 unsigned char OperandFlags = X86II::MO_DTPOFF;
12159 unsigned WrapperKind = X86ISD::Wrapper;
12160 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
12161 GA->getValueType(0),
12162 GA->getOffset(), OperandFlags);
12163 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
12165 // Add x@dtpoff with the base.
12166 return DAG.getNode(ISD::ADD, dl, PtrVT, Offset, Base);
12169 // Lower ISD::GlobalTLSAddress using the "initial exec" or "local exec" model.
12170 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
12171 const EVT PtrVT, TLSModel::Model model,
12172 bool is64Bit, bool isPIC) {
12175 // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit).
12176 Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(*DAG.getContext(),
12177 is64Bit ? 257 : 256));
12179 SDValue ThreadPointer =
12180 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), DAG.getIntPtrConstant(0, dl),
12181 MachinePointerInfo(Ptr), false, false, false, 0);
12183 unsigned char OperandFlags = 0;
12184 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
12186 unsigned WrapperKind = X86ISD::Wrapper;
12187 if (model == TLSModel::LocalExec) {
12188 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
12189 } else if (model == TLSModel::InitialExec) {
12191 OperandFlags = X86II::MO_GOTTPOFF;
12192 WrapperKind = X86ISD::WrapperRIP;
12194 OperandFlags = isPIC ? X86II::MO_GOTNTPOFF : X86II::MO_INDNTPOFF;
12197 llvm_unreachable("Unexpected model");
12200 // emit "addl x@ntpoff,%eax" (local exec)
12201 // or "addl x@indntpoff,%eax" (initial exec)
12202 // or "addl x@gotntpoff(%ebx) ,%eax" (initial exec, 32-bit pic)
12204 DAG.getTargetGlobalAddress(GA->getGlobal(), dl, GA->getValueType(0),
12205 GA->getOffset(), OperandFlags);
12206 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
12208 if (model == TLSModel::InitialExec) {
12209 if (isPIC && !is64Bit) {
12210 Offset = DAG.getNode(ISD::ADD, dl, PtrVT,
12211 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT),
12215 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
12216 MachinePointerInfo::getGOT(DAG.getMachineFunction()),
12217 false, false, false, 0);
12220 // The address of the thread local variable is the add of the thread
12221 // pointer with the offset of the variable.
12222 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
12226 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
12228 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
12229 const GlobalValue *GV = GA->getGlobal();
12230 auto PtrVT = getPointerTy(DAG.getDataLayout());
12232 if (Subtarget->isTargetELF()) {
12233 if (DAG.getTarget().Options.EmulatedTLS)
12234 return LowerToTLSEmulatedModel(GA, DAG);
12235 TLSModel::Model model = DAG.getTarget().getTLSModel(GV);
12237 case TLSModel::GeneralDynamic:
12238 if (Subtarget->is64Bit())
12239 return LowerToTLSGeneralDynamicModel64(GA, DAG, PtrVT);
12240 return LowerToTLSGeneralDynamicModel32(GA, DAG, PtrVT);
12241 case TLSModel::LocalDynamic:
12242 return LowerToTLSLocalDynamicModel(GA, DAG, PtrVT,
12243 Subtarget->is64Bit());
12244 case TLSModel::InitialExec:
12245 case TLSModel::LocalExec:
12246 return LowerToTLSExecModel(GA, DAG, PtrVT, model, Subtarget->is64Bit(),
12247 DAG.getTarget().getRelocationModel() ==
12250 llvm_unreachable("Unknown TLS model.");
12253 if (Subtarget->isTargetDarwin()) {
12254 // Darwin only has one model of TLS. Lower to that.
12255 unsigned char OpFlag = 0;
12256 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ?
12257 X86ISD::WrapperRIP : X86ISD::Wrapper;
12259 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
12260 // global base reg.
12261 bool PIC32 = (DAG.getTarget().getRelocationModel() == Reloc::PIC_) &&
12262 !Subtarget->is64Bit();
12264 OpFlag = X86II::MO_TLVP_PIC_BASE;
12266 OpFlag = X86II::MO_TLVP;
12268 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL,
12269 GA->getValueType(0),
12270 GA->getOffset(), OpFlag);
12271 SDValue Offset = DAG.getNode(WrapperKind, DL, PtrVT, Result);
12273 // With PIC32, the address is actually $g + Offset.
12275 Offset = DAG.getNode(ISD::ADD, DL, PtrVT,
12276 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT),
12279 // Lowering the machine isd will make sure everything is in the right
12281 SDValue Chain = DAG.getEntryNode();
12282 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
12283 SDValue Args[] = { Chain, Offset };
12284 Chain = DAG.getNode(X86ISD::TLSCALL, DL, NodeTys, Args);
12286 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls.
12287 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
12288 MFI->setAdjustsStack(true);
12290 // And our return value (tls address) is in the standard call return value
12292 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
12293 return DAG.getCopyFromReg(Chain, DL, Reg, PtrVT, Chain.getValue(1));
12296 if (Subtarget->isTargetKnownWindowsMSVC() ||
12297 Subtarget->isTargetWindowsGNU()) {
12298 // Just use the implicit TLS architecture
12299 // Need to generate someting similar to:
12300 // mov rdx, qword [gs:abs 58H]; Load pointer to ThreadLocalStorage
12302 // mov ecx, dword [rel _tls_index]: Load index (from C runtime)
12303 // mov rcx, qword [rdx+rcx*8]
12304 // mov eax, .tls$:tlsvar
12305 // [rax+rcx] contains the address
12306 // Windows 64bit: gs:0x58
12307 // Windows 32bit: fs:__tls_array
12310 SDValue Chain = DAG.getEntryNode();
12312 // Get the Thread Pointer, which is %fs:__tls_array (32-bit) or
12313 // %gs:0x58 (64-bit). On MinGW, __tls_array is not available, so directly
12314 // use its literal value of 0x2C.
12315 Value *Ptr = Constant::getNullValue(Subtarget->is64Bit()
12316 ? Type::getInt8PtrTy(*DAG.getContext(),
12318 : Type::getInt32PtrTy(*DAG.getContext(),
12321 SDValue TlsArray = Subtarget->is64Bit()
12322 ? DAG.getIntPtrConstant(0x58, dl)
12323 : (Subtarget->isTargetWindowsGNU()
12324 ? DAG.getIntPtrConstant(0x2C, dl)
12325 : DAG.getExternalSymbol("_tls_array", PtrVT));
12327 SDValue ThreadPointer =
12328 DAG.getLoad(PtrVT, dl, Chain, TlsArray, MachinePointerInfo(Ptr), false,
12332 if (GV->getThreadLocalMode() == GlobalVariable::LocalExecTLSModel) {
12333 res = ThreadPointer;
12335 // Load the _tls_index variable
12336 SDValue IDX = DAG.getExternalSymbol("_tls_index", PtrVT);
12337 if (Subtarget->is64Bit())
12338 IDX = DAG.getExtLoad(ISD::ZEXTLOAD, dl, PtrVT, Chain, IDX,
12339 MachinePointerInfo(), MVT::i32, false, false,
12342 IDX = DAG.getLoad(PtrVT, dl, Chain, IDX, MachinePointerInfo(), false,
12345 auto &DL = DAG.getDataLayout();
12347 DAG.getConstant(Log2_64_Ceil(DL.getPointerSize()), dl, PtrVT);
12348 IDX = DAG.getNode(ISD::SHL, dl, PtrVT, IDX, Scale);
12350 res = DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, IDX);
12353 res = DAG.getLoad(PtrVT, dl, Chain, res, MachinePointerInfo(), false, false,
12356 // Get the offset of start of .tls section
12357 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
12358 GA->getValueType(0),
12359 GA->getOffset(), X86II::MO_SECREL);
12360 SDValue Offset = DAG.getNode(X86ISD::Wrapper, dl, PtrVT, TGA);
12362 // The address of the thread local variable is the add of the thread
12363 // pointer with the offset of the variable.
12364 return DAG.getNode(ISD::ADD, dl, PtrVT, res, Offset);
12367 llvm_unreachable("TLS not implemented for this target.");
12370 /// LowerShiftParts - Lower SRA_PARTS and friends, which return two i32 values
12371 /// and take a 2 x i32 value to shift plus a shift amount.
12372 static SDValue LowerShiftParts(SDValue Op, SelectionDAG &DAG) {
12373 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
12374 MVT VT = Op.getSimpleValueType();
12375 unsigned VTBits = VT.getSizeInBits();
12377 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
12378 SDValue ShOpLo = Op.getOperand(0);
12379 SDValue ShOpHi = Op.getOperand(1);
12380 SDValue ShAmt = Op.getOperand(2);
12381 // X86ISD::SHLD and X86ISD::SHRD have defined overflow behavior but the
12382 // generic ISD nodes haven't. Insert an AND to be safe, it's optimized away
12384 SDValue SafeShAmt = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
12385 DAG.getConstant(VTBits - 1, dl, MVT::i8));
12386 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
12387 DAG.getConstant(VTBits - 1, dl, MVT::i8))
12388 : DAG.getConstant(0, dl, VT);
12390 SDValue Tmp2, Tmp3;
12391 if (Op.getOpcode() == ISD::SHL_PARTS) {
12392 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
12393 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, SafeShAmt);
12395 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
12396 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, SafeShAmt);
12399 // If the shift amount is larger or equal than the width of a part we can't
12400 // rely on the results of shld/shrd. Insert a test and select the appropriate
12401 // values for large shift amounts.
12402 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
12403 DAG.getConstant(VTBits, dl, MVT::i8));
12404 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
12405 AndNode, DAG.getConstant(0, dl, MVT::i8));
12408 SDValue CC = DAG.getConstant(X86::COND_NE, dl, MVT::i8);
12409 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
12410 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
12412 if (Op.getOpcode() == ISD::SHL_PARTS) {
12413 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
12414 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
12416 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
12417 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
12420 SDValue Ops[2] = { Lo, Hi };
12421 return DAG.getMergeValues(Ops, dl);
12424 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op,
12425 SelectionDAG &DAG) const {
12426 SDValue Src = Op.getOperand(0);
12427 MVT SrcVT = Src.getSimpleValueType();
12428 MVT VT = Op.getSimpleValueType();
12431 if (SrcVT.isVector()) {
12432 if (SrcVT == MVT::v2i32 && VT == MVT::v2f64) {
12433 return DAG.getNode(X86ISD::CVTDQ2PD, dl, VT,
12434 DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v4i32, Src,
12435 DAG.getUNDEF(SrcVT)));
12437 if (SrcVT.getVectorElementType() == MVT::i1) {
12438 MVT IntegerVT = MVT::getVectorVT(MVT::i32, SrcVT.getVectorNumElements());
12439 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
12440 DAG.getNode(ISD::SIGN_EXTEND, dl, IntegerVT, Src));
12445 assert(SrcVT <= MVT::i64 && SrcVT >= MVT::i16 &&
12446 "Unknown SINT_TO_FP to lower!");
12448 // These are really Legal; return the operand so the caller accepts it as
12450 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
12452 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
12453 Subtarget->is64Bit()) {
12457 unsigned Size = SrcVT.getSizeInBits()/8;
12458 MachineFunction &MF = DAG.getMachineFunction();
12459 auto PtrVT = getPointerTy(MF.getDataLayout());
12460 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false);
12461 SDValue StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
12462 SDValue Chain = DAG.getStore(
12463 DAG.getEntryNode(), dl, Op.getOperand(0), StackSlot,
12464 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SSFI), false,
12466 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
12469 SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
12471 SelectionDAG &DAG) const {
12475 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
12477 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Glue);
12479 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
12481 unsigned ByteSize = SrcVT.getSizeInBits()/8;
12483 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(StackSlot);
12484 MachineMemOperand *MMO;
12486 int SSFI = FI->getIndex();
12487 MMO = DAG.getMachineFunction().getMachineMemOperand(
12488 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SSFI),
12489 MachineMemOperand::MOLoad, ByteSize, ByteSize);
12491 MMO = cast<LoadSDNode>(StackSlot)->getMemOperand();
12492 StackSlot = StackSlot.getOperand(1);
12494 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) };
12495 SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG :
12497 Tys, Ops, SrcVT, MMO);
12500 Chain = Result.getValue(1);
12501 SDValue InFlag = Result.getValue(2);
12503 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
12504 // shouldn't be necessary except that RFP cannot be live across
12505 // multiple blocks. When stackifier is fixed, they can be uncoupled.
12506 MachineFunction &MF = DAG.getMachineFunction();
12507 unsigned SSFISize = Op.getValueType().getSizeInBits()/8;
12508 int SSFI = MF.getFrameInfo()->CreateStackObject(SSFISize, SSFISize, false);
12509 auto PtrVT = getPointerTy(MF.getDataLayout());
12510 SDValue StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
12511 Tys = DAG.getVTList(MVT::Other);
12513 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag
12515 MachineMemOperand *MMO = DAG.getMachineFunction().getMachineMemOperand(
12516 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SSFI),
12517 MachineMemOperand::MOStore, SSFISize, SSFISize);
12519 Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys,
12520 Ops, Op.getValueType(), MMO);
12521 Result = DAG.getLoad(
12522 Op.getValueType(), DL, Chain, StackSlot,
12523 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SSFI),
12524 false, false, false, 0);
12530 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
12531 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op,
12532 SelectionDAG &DAG) const {
12533 // This algorithm is not obvious. Here it is what we're trying to output:
12536 punpckldq (c0), %xmm0 // c0: (uint4){ 0x43300000U, 0x45300000U, 0U, 0U }
12537 subpd (c1), %xmm0 // c1: (double2){ 0x1.0p52, 0x1.0p52 * 0x1.0p32 }
12539 haddpd %xmm0, %xmm0
12541 pshufd $0x4e, %xmm0, %xmm1
12547 LLVMContext *Context = DAG.getContext();
12549 // Build some magic constants.
12550 static const uint32_t CV0[] = { 0x43300000, 0x45300000, 0, 0 };
12551 Constant *C0 = ConstantDataVector::get(*Context, CV0);
12552 auto PtrVT = getPointerTy(DAG.getDataLayout());
12553 SDValue CPIdx0 = DAG.getConstantPool(C0, PtrVT, 16);
12555 SmallVector<Constant*,2> CV1;
12557 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
12558 APInt(64, 0x4330000000000000ULL))));
12560 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
12561 APInt(64, 0x4530000000000000ULL))));
12562 Constant *C1 = ConstantVector::get(CV1);
12563 SDValue CPIdx1 = DAG.getConstantPool(C1, PtrVT, 16);
12565 // Load the 64-bit value into an XMM register.
12566 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
12569 DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
12570 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()),
12571 false, false, false, 16);
12573 getUnpackl(DAG, dl, MVT::v4i32, DAG.getBitcast(MVT::v4i32, XR1), CLod0);
12576 DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
12577 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()),
12578 false, false, false, 16);
12579 SDValue XR2F = DAG.getBitcast(MVT::v2f64, Unpck1);
12580 // TODO: Are there any fast-math-flags to propagate here?
12581 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
12584 if (Subtarget->hasSSE3()) {
12585 // FIXME: The 'haddpd' instruction may be slower than 'movhlps + addsd'.
12586 Result = DAG.getNode(X86ISD::FHADD, dl, MVT::v2f64, Sub, Sub);
12588 SDValue S2F = DAG.getBitcast(MVT::v4i32, Sub);
12589 SDValue Shuffle = getTargetShuffleNode(X86ISD::PSHUFD, dl, MVT::v4i32,
12591 Result = DAG.getNode(ISD::FADD, dl, MVT::v2f64,
12592 DAG.getBitcast(MVT::v2f64, Shuffle), Sub);
12595 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Result,
12596 DAG.getIntPtrConstant(0, dl));
12599 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
12600 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op,
12601 SelectionDAG &DAG) const {
12603 // FP constant to bias correct the final result.
12604 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL), dl,
12607 // Load the 32-bit value into an XMM register.
12608 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
12611 // Zero out the upper parts of the register.
12612 Load = getShuffleVectorZeroOrUndef(Load, 0, true, Subtarget, DAG);
12614 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
12615 DAG.getBitcast(MVT::v2f64, Load),
12616 DAG.getIntPtrConstant(0, dl));
12618 // Or the load with the bias.
12619 SDValue Or = DAG.getNode(
12620 ISD::OR, dl, MVT::v2i64,
12621 DAG.getBitcast(MVT::v2i64,
12622 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, Load)),
12623 DAG.getBitcast(MVT::v2i64,
12624 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, Bias)));
12626 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
12627 DAG.getBitcast(MVT::v2f64, Or), DAG.getIntPtrConstant(0, dl));
12629 // Subtract the bias.
12630 // TODO: Are there any fast-math-flags to propagate here?
12631 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
12633 // Handle final rounding.
12634 MVT DestVT = Op.getSimpleValueType();
12636 if (DestVT.bitsLT(MVT::f64))
12637 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
12638 DAG.getIntPtrConstant(0, dl));
12639 if (DestVT.bitsGT(MVT::f64))
12640 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
12642 // Handle final rounding.
12646 static SDValue lowerUINT_TO_FP_vXi32(SDValue Op, SelectionDAG &DAG,
12647 const X86Subtarget &Subtarget) {
12648 // The algorithm is the following:
12649 // #ifdef __SSE4_1__
12650 // uint4 lo = _mm_blend_epi16( v, (uint4) 0x4b000000, 0xaa);
12651 // uint4 hi = _mm_blend_epi16( _mm_srli_epi32(v,16),
12652 // (uint4) 0x53000000, 0xaa);
12654 // uint4 lo = (v & (uint4) 0xffff) | (uint4) 0x4b000000;
12655 // uint4 hi = (v >> 16) | (uint4) 0x53000000;
12657 // float4 fhi = (float4) hi - (0x1.0p39f + 0x1.0p23f);
12658 // return (float4) lo + fhi;
12660 // We shouldn't use it when unsafe-fp-math is enabled though: we might later
12661 // reassociate the two FADDs, and if we do that, the algorithm fails
12662 // spectacularly (PR24512).
12663 // FIXME: If we ever have some kind of Machine FMF, this should be marked
12664 // as non-fast and always be enabled. Why isn't SDAG FMF enough? Because
12665 // there's also the MachineCombiner reassociations happening on Machine IR.
12666 if (DAG.getTarget().Options.UnsafeFPMath)
12670 SDValue V = Op->getOperand(0);
12671 MVT VecIntVT = V.getSimpleValueType();
12672 bool Is128 = VecIntVT == MVT::v4i32;
12673 MVT VecFloatVT = Is128 ? MVT::v4f32 : MVT::v8f32;
12674 // If we convert to something else than the supported type, e.g., to v4f64,
12676 if (VecFloatVT != Op->getSimpleValueType(0))
12679 unsigned NumElts = VecIntVT.getVectorNumElements();
12680 assert((VecIntVT == MVT::v4i32 || VecIntVT == MVT::v8i32) &&
12681 "Unsupported custom type");
12682 assert(NumElts <= 8 && "The size of the constant array must be fixed");
12684 // In the #idef/#else code, we have in common:
12685 // - The vector of constants:
12691 // Create the splat vector for 0x4b000000.
12692 SDValue CstLow = DAG.getConstant(0x4b000000, DL, MVT::i32);
12693 SDValue CstLowArray[] = {CstLow, CstLow, CstLow, CstLow,
12694 CstLow, CstLow, CstLow, CstLow};
12695 SDValue VecCstLow = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
12696 makeArrayRef(&CstLowArray[0], NumElts));
12697 // Create the splat vector for 0x53000000.
12698 SDValue CstHigh = DAG.getConstant(0x53000000, DL, MVT::i32);
12699 SDValue CstHighArray[] = {CstHigh, CstHigh, CstHigh, CstHigh,
12700 CstHigh, CstHigh, CstHigh, CstHigh};
12701 SDValue VecCstHigh = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
12702 makeArrayRef(&CstHighArray[0], NumElts));
12704 // Create the right shift.
12705 SDValue CstShift = DAG.getConstant(16, DL, MVT::i32);
12706 SDValue CstShiftArray[] = {CstShift, CstShift, CstShift, CstShift,
12707 CstShift, CstShift, CstShift, CstShift};
12708 SDValue VecCstShift = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
12709 makeArrayRef(&CstShiftArray[0], NumElts));
12710 SDValue HighShift = DAG.getNode(ISD::SRL, DL, VecIntVT, V, VecCstShift);
12713 if (Subtarget.hasSSE41()) {
12714 MVT VecI16VT = Is128 ? MVT::v8i16 : MVT::v16i16;
12715 // uint4 lo = _mm_blend_epi16( v, (uint4) 0x4b000000, 0xaa);
12716 SDValue VecCstLowBitcast = DAG.getBitcast(VecI16VT, VecCstLow);
12717 SDValue VecBitcast = DAG.getBitcast(VecI16VT, V);
12718 // Low will be bitcasted right away, so do not bother bitcasting back to its
12720 Low = DAG.getNode(X86ISD::BLENDI, DL, VecI16VT, VecBitcast,
12721 VecCstLowBitcast, DAG.getConstant(0xaa, DL, MVT::i32));
12722 // uint4 hi = _mm_blend_epi16( _mm_srli_epi32(v,16),
12723 // (uint4) 0x53000000, 0xaa);
12724 SDValue VecCstHighBitcast = DAG.getBitcast(VecI16VT, VecCstHigh);
12725 SDValue VecShiftBitcast = DAG.getBitcast(VecI16VT, HighShift);
12726 // High will be bitcasted right away, so do not bother bitcasting back to
12727 // its original type.
12728 High = DAG.getNode(X86ISD::BLENDI, DL, VecI16VT, VecShiftBitcast,
12729 VecCstHighBitcast, DAG.getConstant(0xaa, DL, MVT::i32));
12731 SDValue CstMask = DAG.getConstant(0xffff, DL, MVT::i32);
12732 SDValue VecCstMask = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT, CstMask,
12733 CstMask, CstMask, CstMask);
12734 // uint4 lo = (v & (uint4) 0xffff) | (uint4) 0x4b000000;
12735 SDValue LowAnd = DAG.getNode(ISD::AND, DL, VecIntVT, V, VecCstMask);
12736 Low = DAG.getNode(ISD::OR, DL, VecIntVT, LowAnd, VecCstLow);
12738 // uint4 hi = (v >> 16) | (uint4) 0x53000000;
12739 High = DAG.getNode(ISD::OR, DL, VecIntVT, HighShift, VecCstHigh);
12742 // Create the vector constant for -(0x1.0p39f + 0x1.0p23f).
12743 SDValue CstFAdd = DAG.getConstantFP(
12744 APFloat(APFloat::IEEEsingle, APInt(32, 0xD3000080)), DL, MVT::f32);
12745 SDValue CstFAddArray[] = {CstFAdd, CstFAdd, CstFAdd, CstFAdd,
12746 CstFAdd, CstFAdd, CstFAdd, CstFAdd};
12747 SDValue VecCstFAdd = DAG.getNode(ISD::BUILD_VECTOR, DL, VecFloatVT,
12748 makeArrayRef(&CstFAddArray[0], NumElts));
12750 // float4 fhi = (float4) hi - (0x1.0p39f + 0x1.0p23f);
12751 SDValue HighBitcast = DAG.getBitcast(VecFloatVT, High);
12752 // TODO: Are there any fast-math-flags to propagate here?
12754 DAG.getNode(ISD::FADD, DL, VecFloatVT, HighBitcast, VecCstFAdd);
12755 // return (float4) lo + fhi;
12756 SDValue LowBitcast = DAG.getBitcast(VecFloatVT, Low);
12757 return DAG.getNode(ISD::FADD, DL, VecFloatVT, LowBitcast, FHigh);
12760 SDValue X86TargetLowering::lowerUINT_TO_FP_vec(SDValue Op,
12761 SelectionDAG &DAG) const {
12762 SDValue N0 = Op.getOperand(0);
12763 MVT SVT = N0.getSimpleValueType();
12766 switch (SVT.SimpleTy) {
12768 llvm_unreachable("Custom UINT_TO_FP is not supported!");
12773 MVT NVT = MVT::getVectorVT(MVT::i32, SVT.getVectorNumElements());
12774 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
12775 DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, N0));
12779 return lowerUINT_TO_FP_vXi32(Op, DAG, *Subtarget);
12782 assert(Subtarget->hasAVX512());
12783 return DAG.getNode(ISD::UINT_TO_FP, dl, Op.getValueType(),
12784 DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v16i32, N0));
12788 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op,
12789 SelectionDAG &DAG) const {
12790 SDValue N0 = Op.getOperand(0);
12792 auto PtrVT = getPointerTy(DAG.getDataLayout());
12794 if (Op.getSimpleValueType().isVector())
12795 return lowerUINT_TO_FP_vec(Op, DAG);
12797 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't
12798 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
12799 // the optimization here.
12800 if (DAG.SignBitIsZero(N0))
12801 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
12803 MVT SrcVT = N0.getSimpleValueType();
12804 MVT DstVT = Op.getSimpleValueType();
12806 if (Subtarget->hasAVX512() && isScalarFPTypeInSSEReg(DstVT) &&
12807 (SrcVT == MVT::i32 || (SrcVT == MVT::i64 && Subtarget->is64Bit()))) {
12808 // Conversions from unsigned i32 to f32/f64 are legal,
12809 // using VCVTUSI2SS/SD. Same for i64 in 64-bit mode.
12813 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64)
12814 return LowerUINT_TO_FP_i64(Op, DAG);
12815 if (SrcVT == MVT::i32 && X86ScalarSSEf64)
12816 return LowerUINT_TO_FP_i32(Op, DAG);
12817 if (Subtarget->is64Bit() && SrcVT == MVT::i64 && DstVT == MVT::f32)
12820 // Make a 64-bit buffer, and use it to build an FILD.
12821 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
12822 if (SrcVT == MVT::i32) {
12823 SDValue WordOff = DAG.getConstant(4, dl, PtrVT);
12824 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl, PtrVT, StackSlot, WordOff);
12825 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
12826 StackSlot, MachinePointerInfo(),
12828 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, dl, MVT::i32),
12829 OffsetSlot, MachinePointerInfo(),
12831 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
12835 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP");
12836 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
12837 StackSlot, MachinePointerInfo(),
12839 // For i64 source, we need to add the appropriate power of 2 if the input
12840 // was negative. This is the same as the optimization in
12841 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here,
12842 // we must be careful to do the computation in x87 extended precision, not
12843 // in SSE. (The generic code can't know it's OK to do this, or how to.)
12844 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex();
12845 MachineMemOperand *MMO = DAG.getMachineFunction().getMachineMemOperand(
12846 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SSFI),
12847 MachineMemOperand::MOLoad, 8, 8);
12849 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other);
12850 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) };
12851 SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops,
12854 APInt FF(32, 0x5F800000ULL);
12856 // Check whether the sign bit is set.
12857 SDValue SignSet = DAG.getSetCC(
12858 dl, getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), MVT::i64),
12859 Op.getOperand(0), DAG.getConstant(0, dl, MVT::i64), ISD::SETLT);
12861 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
12862 SDValue FudgePtr = DAG.getConstantPool(
12863 ConstantInt::get(*DAG.getContext(), FF.zext(64)), PtrVT);
12865 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
12866 SDValue Zero = DAG.getIntPtrConstant(0, dl);
12867 SDValue Four = DAG.getIntPtrConstant(4, dl);
12868 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
12870 FudgePtr = DAG.getNode(ISD::ADD, dl, PtrVT, FudgePtr, Offset);
12872 // Load the value out, extending it from f32 to f80.
12873 // FIXME: Avoid the extend by constructing the right constant pool?
12874 SDValue Fudge = DAG.getExtLoad(
12875 ISD::EXTLOAD, dl, MVT::f80, DAG.getEntryNode(), FudgePtr,
12876 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()), MVT::f32,
12877 false, false, false, 4);
12878 // Extend everything to 80 bits to force it to be done on x87.
12879 // TODO: Are there any fast-math-flags to propagate here?
12880 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge);
12881 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add,
12882 DAG.getIntPtrConstant(0, dl));
12885 // If the given FP_TO_SINT (IsSigned) or FP_TO_UINT (!IsSigned) operation
12886 // is legal, or has an fp128 or f16 source (which needs to be promoted to f32),
12887 // just return an <SDValue(), SDValue()> pair.
12888 // Otherwise it is assumed to be a conversion from one of f32, f64 or f80
12889 // to i16, i32 or i64, and we lower it to a legal sequence.
12890 // If lowered to the final integer result we return a <result, SDValue()> pair.
12891 // Otherwise we lower it to a sequence ending with a FIST, return a
12892 // <FIST, StackSlot> pair, and the caller is responsible for loading
12893 // the final integer result from StackSlot.
12894 std::pair<SDValue,SDValue>
12895 X86TargetLowering::FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG,
12896 bool IsSigned, bool IsReplace) const {
12899 EVT DstTy = Op.getValueType();
12900 EVT TheVT = Op.getOperand(0).getValueType();
12901 auto PtrVT = getPointerTy(DAG.getDataLayout());
12903 if (TheVT != MVT::f32 && TheVT != MVT::f64 && TheVT != MVT::f80) {
12904 // f16 must be promoted before using the lowering in this routine.
12905 // fp128 does not use this lowering.
12906 return std::make_pair(SDValue(), SDValue());
12909 // If using FIST to compute an unsigned i64, we'll need some fixup
12910 // to handle values above the maximum signed i64. A FIST is always
12911 // used for the 32-bit subtarget, but also for f80 on a 64-bit target.
12912 bool UnsignedFixup = !IsSigned &&
12913 DstTy == MVT::i64 &&
12914 (!Subtarget->is64Bit() ||
12915 !isScalarFPTypeInSSEReg(TheVT));
12917 if (!IsSigned && DstTy != MVT::i64 && !Subtarget->hasAVX512()) {
12918 // Replace the fp-to-uint32 operation with an fp-to-sint64 FIST.
12919 // The low 32 bits of the fist result will have the correct uint32 result.
12920 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
12924 assert(DstTy.getSimpleVT() <= MVT::i64 &&
12925 DstTy.getSimpleVT() >= MVT::i16 &&
12926 "Unknown FP_TO_INT to lower!");
12928 // These are really Legal.
12929 if (DstTy == MVT::i32 &&
12930 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
12931 return std::make_pair(SDValue(), SDValue());
12932 if (Subtarget->is64Bit() &&
12933 DstTy == MVT::i64 &&
12934 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
12935 return std::make_pair(SDValue(), SDValue());
12937 // We lower FP->int64 into FISTP64 followed by a load from a temporary
12939 MachineFunction &MF = DAG.getMachineFunction();
12940 unsigned MemSize = DstTy.getSizeInBits()/8;
12941 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
12942 SDValue StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
12945 switch (DstTy.getSimpleVT().SimpleTy) {
12946 default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
12947 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
12948 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
12949 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
12952 SDValue Chain = DAG.getEntryNode();
12953 SDValue Value = Op.getOperand(0);
12954 SDValue Adjust; // 0x0 or 0x80000000, for result sign bit adjustment.
12956 if (UnsignedFixup) {
12958 // Conversion to unsigned i64 is implemented with a select,
12959 // depending on whether the source value fits in the range
12960 // of a signed i64. Let Thresh be the FP equivalent of
12961 // 0x8000000000000000ULL.
12963 // Adjust i32 = (Value < Thresh) ? 0 : 0x80000000;
12964 // FistSrc = (Value < Thresh) ? Value : (Value - Thresh);
12965 // Fist-to-mem64 FistSrc
12966 // Add 0 or 0x800...0ULL to the 64-bit result, which is equivalent
12967 // to XOR'ing the high 32 bits with Adjust.
12969 // Being a power of 2, Thresh is exactly representable in all FP formats.
12970 // For X87 we'd like to use the smallest FP type for this constant, but
12971 // for DAG type consistency we have to match the FP operand type.
12973 APFloat Thresh(APFloat::IEEEsingle, APInt(32, 0x5f000000));
12974 LLVM_ATTRIBUTE_UNUSED APFloat::opStatus Status = APFloat::opOK;
12975 bool LosesInfo = false;
12976 if (TheVT == MVT::f64)
12977 // The rounding mode is irrelevant as the conversion should be exact.
12978 Status = Thresh.convert(APFloat::IEEEdouble, APFloat::rmNearestTiesToEven,
12980 else if (TheVT == MVT::f80)
12981 Status = Thresh.convert(APFloat::x87DoubleExtended,
12982 APFloat::rmNearestTiesToEven, &LosesInfo);
12984 assert(Status == APFloat::opOK && !LosesInfo &&
12985 "FP conversion should have been exact");
12987 SDValue ThreshVal = DAG.getConstantFP(Thresh, DL, TheVT);
12989 SDValue Cmp = DAG.getSetCC(DL,
12990 getSetCCResultType(DAG.getDataLayout(),
12991 *DAG.getContext(), TheVT),
12992 Value, ThreshVal, ISD::SETLT);
12993 Adjust = DAG.getSelect(DL, MVT::i32, Cmp,
12994 DAG.getConstant(0, DL, MVT::i32),
12995 DAG.getConstant(0x80000000, DL, MVT::i32));
12996 SDValue Sub = DAG.getNode(ISD::FSUB, DL, TheVT, Value, ThreshVal);
12997 Cmp = DAG.getSetCC(DL, getSetCCResultType(DAG.getDataLayout(),
12998 *DAG.getContext(), TheVT),
12999 Value, ThreshVal, ISD::SETLT);
13000 Value = DAG.getSelect(DL, TheVT, Cmp, Value, Sub);
13003 // FIXME This causes a redundant load/store if the SSE-class value is already
13004 // in memory, such as if it is on the callstack.
13005 if (isScalarFPTypeInSSEReg(TheVT)) {
13006 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
13007 Chain = DAG.getStore(Chain, DL, Value, StackSlot,
13008 MachinePointerInfo::getFixedStack(MF, SSFI), false,
13010 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
13012 Chain, StackSlot, DAG.getValueType(TheVT)
13015 MachineMemOperand *MMO =
13016 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(MF, SSFI),
13017 MachineMemOperand::MOLoad, MemSize, MemSize);
13018 Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops, DstTy, MMO);
13019 Chain = Value.getValue(1);
13020 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
13021 StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
13024 MachineMemOperand *MMO =
13025 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(MF, SSFI),
13026 MachineMemOperand::MOStore, MemSize, MemSize);
13028 if (UnsignedFixup) {
13030 // Insert the FIST, load its result as two i32's,
13031 // and XOR the high i32 with Adjust.
13033 SDValue FistOps[] = { Chain, Value, StackSlot };
13034 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
13035 FistOps, DstTy, MMO);
13037 SDValue Low32 = DAG.getLoad(MVT::i32, DL, FIST, StackSlot,
13038 MachinePointerInfo(),
13039 false, false, false, 0);
13040 SDValue HighAddr = DAG.getNode(ISD::ADD, DL, PtrVT, StackSlot,
13041 DAG.getConstant(4, DL, PtrVT));
13043 SDValue High32 = DAG.getLoad(MVT::i32, DL, FIST, HighAddr,
13044 MachinePointerInfo(),
13045 false, false, false, 0);
13046 High32 = DAG.getNode(ISD::XOR, DL, MVT::i32, High32, Adjust);
13048 if (Subtarget->is64Bit()) {
13049 // Join High32 and Low32 into a 64-bit result.
13050 // (High32 << 32) | Low32
13051 Low32 = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64, Low32);
13052 High32 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, High32);
13053 High32 = DAG.getNode(ISD::SHL, DL, MVT::i64, High32,
13054 DAG.getConstant(32, DL, MVT::i8));
13055 SDValue Result = DAG.getNode(ISD::OR, DL, MVT::i64, High32, Low32);
13056 return std::make_pair(Result, SDValue());
13059 SDValue ResultOps[] = { Low32, High32 };
13061 SDValue pair = IsReplace
13062 ? DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, ResultOps)
13063 : DAG.getMergeValues(ResultOps, DL);
13064 return std::make_pair(pair, SDValue());
13066 // Build the FP_TO_INT*_IN_MEM
13067 SDValue Ops[] = { Chain, Value, StackSlot };
13068 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
13070 return std::make_pair(FIST, StackSlot);
13074 static SDValue LowerAVXExtend(SDValue Op, SelectionDAG &DAG,
13075 const X86Subtarget *Subtarget) {
13076 MVT VT = Op->getSimpleValueType(0);
13077 SDValue In = Op->getOperand(0);
13078 MVT InVT = In.getSimpleValueType();
13081 if (VT.is512BitVector() || InVT.getVectorElementType() == MVT::i1)
13082 return DAG.getNode(ISD::ZERO_EXTEND, dl, VT, In);
13084 // Optimize vectors in AVX mode:
13087 // Use vpunpcklwd for 4 lower elements v8i16 -> v4i32.
13088 // Use vpunpckhwd for 4 upper elements v8i16 -> v4i32.
13089 // Concat upper and lower parts.
13092 // Use vpunpckldq for 4 lower elements v4i32 -> v2i64.
13093 // Use vpunpckhdq for 4 upper elements v4i32 -> v2i64.
13094 // Concat upper and lower parts.
13097 if (((VT != MVT::v16i16) || (InVT != MVT::v16i8)) &&
13098 ((VT != MVT::v8i32) || (InVT != MVT::v8i16)) &&
13099 ((VT != MVT::v4i64) || (InVT != MVT::v4i32)))
13102 if (Subtarget->hasInt256())
13103 return DAG.getNode(X86ISD::VZEXT, dl, VT, In);
13105 SDValue ZeroVec = getZeroVector(InVT, Subtarget, DAG, dl);
13106 SDValue Undef = DAG.getUNDEF(InVT);
13107 bool NeedZero = Op.getOpcode() == ISD::ZERO_EXTEND;
13108 SDValue OpLo = getUnpackl(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
13109 SDValue OpHi = getUnpackh(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
13111 MVT HVT = MVT::getVectorVT(VT.getVectorElementType(),
13112 VT.getVectorNumElements()/2);
13114 OpLo = DAG.getBitcast(HVT, OpLo);
13115 OpHi = DAG.getBitcast(HVT, OpHi);
13117 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
13120 static SDValue LowerZERO_EXTEND_AVX512(SDValue Op,
13121 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
13122 MVT VT = Op->getSimpleValueType(0);
13123 SDValue In = Op->getOperand(0);
13124 MVT InVT = In.getSimpleValueType();
13126 unsigned int NumElts = VT.getVectorNumElements();
13127 if (NumElts != 8 && NumElts != 16 && !Subtarget->hasBWI())
13130 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1)
13131 return DAG.getNode(X86ISD::VZEXT, DL, VT, In);
13133 assert(InVT.getVectorElementType() == MVT::i1);
13134 MVT ExtVT = NumElts == 8 ? MVT::v8i64 : MVT::v16i32;
13136 DAG.getConstant(APInt(ExtVT.getScalarSizeInBits(), 1), DL, ExtVT);
13138 DAG.getConstant(APInt::getNullValue(ExtVT.getScalarSizeInBits()), DL, ExtVT);
13140 SDValue V = DAG.getNode(ISD::VSELECT, DL, ExtVT, In, One, Zero);
13141 if (VT.is512BitVector())
13143 return DAG.getNode(X86ISD::VTRUNC, DL, VT, V);
13146 static SDValue LowerANY_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
13147 SelectionDAG &DAG) {
13148 if (Subtarget->hasFp256())
13149 if (SDValue Res = LowerAVXExtend(Op, DAG, Subtarget))
13155 static SDValue LowerZERO_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
13156 SelectionDAG &DAG) {
13158 MVT VT = Op.getSimpleValueType();
13159 SDValue In = Op.getOperand(0);
13160 MVT SVT = In.getSimpleValueType();
13162 if (VT.is512BitVector() || SVT.getVectorElementType() == MVT::i1)
13163 return LowerZERO_EXTEND_AVX512(Op, Subtarget, DAG);
13165 if (Subtarget->hasFp256())
13166 if (SDValue Res = LowerAVXExtend(Op, DAG, Subtarget))
13169 assert(!VT.is256BitVector() || !SVT.is128BitVector() ||
13170 VT.getVectorNumElements() != SVT.getVectorNumElements());
13174 SDValue X86TargetLowering::LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const {
13176 MVT VT = Op.getSimpleValueType();
13177 SDValue In = Op.getOperand(0);
13178 MVT InVT = In.getSimpleValueType();
13180 if (VT == MVT::i1) {
13181 assert((InVT.isInteger() && (InVT.getSizeInBits() <= 64)) &&
13182 "Invalid scalar TRUNCATE operation");
13183 if (InVT.getSizeInBits() >= 32)
13185 In = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, In);
13186 return DAG.getNode(ISD::TRUNCATE, DL, VT, In);
13188 assert(VT.getVectorNumElements() == InVT.getVectorNumElements() &&
13189 "Invalid TRUNCATE operation");
13191 // move vector to mask - truncate solution for SKX
13192 if (VT.getVectorElementType() == MVT::i1) {
13193 if (InVT.is512BitVector() && InVT.getScalarSizeInBits() <= 16 &&
13194 Subtarget->hasBWI())
13195 return Op; // legal, will go to VPMOVB2M, VPMOVW2M
13196 if ((InVT.is256BitVector() || InVT.is128BitVector())
13197 && InVT.getScalarSizeInBits() <= 16 &&
13198 Subtarget->hasBWI() && Subtarget->hasVLX())
13199 return Op; // legal, will go to VPMOVB2M, VPMOVW2M
13200 if (InVT.is512BitVector() && InVT.getScalarSizeInBits() >= 32 &&
13201 Subtarget->hasDQI())
13202 return Op; // legal, will go to VPMOVD2M, VPMOVQ2M
13203 if ((InVT.is256BitVector() || InVT.is128BitVector())
13204 && InVT.getScalarSizeInBits() >= 32 &&
13205 Subtarget->hasDQI() && Subtarget->hasVLX())
13206 return Op; // legal, will go to VPMOVB2M, VPMOVQ2M
13209 if (VT.getVectorElementType() == MVT::i1) {
13210 assert(VT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
13211 unsigned NumElts = InVT.getVectorNumElements();
13212 assert ((NumElts == 8 || NumElts == 16) && "Unexpected vector type");
13213 if (InVT.getSizeInBits() < 512) {
13214 MVT ExtVT = (NumElts == 16)? MVT::v16i32 : MVT::v8i64;
13215 In = DAG.getNode(ISD::SIGN_EXTEND, DL, ExtVT, In);
13220 DAG.getConstant(APInt::getSignBit(InVT.getScalarSizeInBits()), DL, InVT);
13221 SDValue And = DAG.getNode(ISD::AND, DL, InVT, OneV, In);
13222 return DAG.getNode(X86ISD::TESTM, DL, VT, And, And);
13225 // vpmovqb/w/d, vpmovdb/w, vpmovwb
13226 if (Subtarget->hasAVX512()) {
13227 // word to byte only under BWI
13228 if (InVT == MVT::v16i16 && !Subtarget->hasBWI()) // v16i16 -> v16i8
13229 return DAG.getNode(X86ISD::VTRUNC, DL, VT,
13230 DAG.getNode(X86ISD::VSEXT, DL, MVT::v16i32, In));
13231 return DAG.getNode(X86ISD::VTRUNC, DL, VT, In);
13233 if ((VT == MVT::v4i32) && (InVT == MVT::v4i64)) {
13234 // On AVX2, v4i64 -> v4i32 becomes VPERMD.
13235 if (Subtarget->hasInt256()) {
13236 static const int ShufMask[] = {0, 2, 4, 6, -1, -1, -1, -1};
13237 In = DAG.getBitcast(MVT::v8i32, In);
13238 In = DAG.getVectorShuffle(MVT::v8i32, DL, In, DAG.getUNDEF(MVT::v8i32),
13240 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, In,
13241 DAG.getIntPtrConstant(0, DL));
13244 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
13245 DAG.getIntPtrConstant(0, DL));
13246 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
13247 DAG.getIntPtrConstant(2, DL));
13248 OpLo = DAG.getBitcast(MVT::v4i32, OpLo);
13249 OpHi = DAG.getBitcast(MVT::v4i32, OpHi);
13250 static const int ShufMask[] = {0, 2, 4, 6};
13251 return DAG.getVectorShuffle(VT, DL, OpLo, OpHi, ShufMask);
13254 if ((VT == MVT::v8i16) && (InVT == MVT::v8i32)) {
13255 // On AVX2, v8i32 -> v8i16 becomed PSHUFB.
13256 if (Subtarget->hasInt256()) {
13257 In = DAG.getBitcast(MVT::v32i8, In);
13259 SmallVector<SDValue,32> pshufbMask;
13260 for (unsigned i = 0; i < 2; ++i) {
13261 pshufbMask.push_back(DAG.getConstant(0x0, DL, MVT::i8));
13262 pshufbMask.push_back(DAG.getConstant(0x1, DL, MVT::i8));
13263 pshufbMask.push_back(DAG.getConstant(0x4, DL, MVT::i8));
13264 pshufbMask.push_back(DAG.getConstant(0x5, DL, MVT::i8));
13265 pshufbMask.push_back(DAG.getConstant(0x8, DL, MVT::i8));
13266 pshufbMask.push_back(DAG.getConstant(0x9, DL, MVT::i8));
13267 pshufbMask.push_back(DAG.getConstant(0xc, DL, MVT::i8));
13268 pshufbMask.push_back(DAG.getConstant(0xd, DL, MVT::i8));
13269 for (unsigned j = 0; j < 8; ++j)
13270 pshufbMask.push_back(DAG.getConstant(0x80, DL, MVT::i8));
13272 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, pshufbMask);
13273 In = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v32i8, In, BV);
13274 In = DAG.getBitcast(MVT::v4i64, In);
13276 static const int ShufMask[] = {0, 2, -1, -1};
13277 In = DAG.getVectorShuffle(MVT::v4i64, DL, In, DAG.getUNDEF(MVT::v4i64),
13279 In = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
13280 DAG.getIntPtrConstant(0, DL));
13281 return DAG.getBitcast(VT, In);
13284 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
13285 DAG.getIntPtrConstant(0, DL));
13287 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
13288 DAG.getIntPtrConstant(4, DL));
13290 OpLo = DAG.getBitcast(MVT::v16i8, OpLo);
13291 OpHi = DAG.getBitcast(MVT::v16i8, OpHi);
13293 // The PSHUFB mask:
13294 static const int ShufMask1[] = {0, 1, 4, 5, 8, 9, 12, 13,
13295 -1, -1, -1, -1, -1, -1, -1, -1};
13297 SDValue Undef = DAG.getUNDEF(MVT::v16i8);
13298 OpLo = DAG.getVectorShuffle(MVT::v16i8, DL, OpLo, Undef, ShufMask1);
13299 OpHi = DAG.getVectorShuffle(MVT::v16i8, DL, OpHi, Undef, ShufMask1);
13301 OpLo = DAG.getBitcast(MVT::v4i32, OpLo);
13302 OpHi = DAG.getBitcast(MVT::v4i32, OpHi);
13304 // The MOVLHPS Mask:
13305 static const int ShufMask2[] = {0, 1, 4, 5};
13306 SDValue res = DAG.getVectorShuffle(MVT::v4i32, DL, OpLo, OpHi, ShufMask2);
13307 return DAG.getBitcast(MVT::v8i16, res);
13310 // Handle truncation of V256 to V128 using shuffles.
13311 if (!VT.is128BitVector() || !InVT.is256BitVector())
13314 assert(Subtarget->hasFp256() && "256-bit vector without AVX!");
13316 unsigned NumElems = VT.getVectorNumElements();
13317 MVT NVT = MVT::getVectorVT(VT.getVectorElementType(), NumElems * 2);
13319 SmallVector<int, 16> MaskVec(NumElems * 2, -1);
13320 // Prepare truncation shuffle mask
13321 for (unsigned i = 0; i != NumElems; ++i)
13322 MaskVec[i] = i * 2;
13323 SDValue V = DAG.getVectorShuffle(NVT, DL, DAG.getBitcast(NVT, In),
13324 DAG.getUNDEF(NVT), &MaskVec[0]);
13325 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, V,
13326 DAG.getIntPtrConstant(0, DL));
13329 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op,
13330 SelectionDAG &DAG) const {
13331 assert(!Op.getSimpleValueType().isVector());
13333 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
13334 /*IsSigned=*/ true, /*IsReplace=*/ false);
13335 SDValue FIST = Vals.first, StackSlot = Vals.second;
13336 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
13337 if (!FIST.getNode())
13340 if (StackSlot.getNode())
13341 // Load the result.
13342 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
13343 FIST, StackSlot, MachinePointerInfo(),
13344 false, false, false, 0);
13346 // The node is the result.
13350 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op,
13351 SelectionDAG &DAG) const {
13352 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
13353 /*IsSigned=*/ false, /*IsReplace=*/ false);
13354 SDValue FIST = Vals.first, StackSlot = Vals.second;
13355 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
13356 if (!FIST.getNode())
13359 if (StackSlot.getNode())
13360 // Load the result.
13361 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
13362 FIST, StackSlot, MachinePointerInfo(),
13363 false, false, false, 0);
13365 // The node is the result.
13369 static SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) {
13371 MVT VT = Op.getSimpleValueType();
13372 SDValue In = Op.getOperand(0);
13373 MVT SVT = In.getSimpleValueType();
13375 assert(SVT == MVT::v2f32 && "Only customize MVT::v2f32 type legalization!");
13377 return DAG.getNode(X86ISD::VFPEXT, DL, VT,
13378 DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v4f32,
13379 In, DAG.getUNDEF(SVT)));
13382 /// The only differences between FABS and FNEG are the mask and the logic op.
13383 /// FNEG also has a folding opportunity for FNEG(FABS(x)).
13384 static SDValue LowerFABSorFNEG(SDValue Op, SelectionDAG &DAG) {
13385 assert((Op.getOpcode() == ISD::FABS || Op.getOpcode() == ISD::FNEG) &&
13386 "Wrong opcode for lowering FABS or FNEG.");
13388 bool IsFABS = (Op.getOpcode() == ISD::FABS);
13390 // If this is a FABS and it has an FNEG user, bail out to fold the combination
13391 // into an FNABS. We'll lower the FABS after that if it is still in use.
13393 for (SDNode *User : Op->uses())
13394 if (User->getOpcode() == ISD::FNEG)
13398 MVT VT = Op.getSimpleValueType();
13400 // FIXME: Use function attribute "OptimizeForSize" and/or CodeGenOpt::Level to
13401 // decide if we should generate a 16-byte constant mask when we only need 4 or
13402 // 8 bytes for the scalar case.
13408 if (VT.isVector()) {
13410 EltVT = VT.getVectorElementType();
13411 NumElts = VT.getVectorNumElements();
13413 // There are no scalar bitwise logical SSE/AVX instructions, so we
13414 // generate a 16-byte vector constant and logic op even for the scalar case.
13415 // Using a 16-byte mask allows folding the load of the mask with
13416 // the logic op, so it can save (~4 bytes) on code size.
13417 LogicVT = (VT == MVT::f64) ? MVT::v2f64 : MVT::v4f32;
13419 NumElts = (VT == MVT::f64) ? 2 : 4;
13422 unsigned EltBits = EltVT.getSizeInBits();
13423 LLVMContext *Context = DAG.getContext();
13424 // For FABS, mask is 0x7f...; for FNEG, mask is 0x80...
13426 IsFABS ? APInt::getSignedMaxValue(EltBits) : APInt::getSignBit(EltBits);
13427 Constant *C = ConstantInt::get(*Context, MaskElt);
13428 C = ConstantVector::getSplat(NumElts, C);
13429 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13430 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy(DAG.getDataLayout()));
13431 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
13433 DAG.getLoad(LogicVT, dl, DAG.getEntryNode(), CPIdx,
13434 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()),
13435 false, false, false, Alignment);
13437 SDValue Op0 = Op.getOperand(0);
13438 bool IsFNABS = !IsFABS && (Op0.getOpcode() == ISD::FABS);
13440 IsFABS ? X86ISD::FAND : IsFNABS ? X86ISD::FOR : X86ISD::FXOR;
13441 SDValue Operand = IsFNABS ? Op0.getOperand(0) : Op0;
13444 return DAG.getNode(LogicOp, dl, LogicVT, Operand, Mask);
13446 // For the scalar case extend to a 128-bit vector, perform the logic op,
13447 // and extract the scalar result back out.
13448 Operand = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LogicVT, Operand);
13449 SDValue LogicNode = DAG.getNode(LogicOp, dl, LogicVT, Operand, Mask);
13450 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, LogicNode,
13451 DAG.getIntPtrConstant(0, dl));
13454 static SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) {
13455 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13456 LLVMContext *Context = DAG.getContext();
13457 SDValue Op0 = Op.getOperand(0);
13458 SDValue Op1 = Op.getOperand(1);
13460 MVT VT = Op.getSimpleValueType();
13461 MVT SrcVT = Op1.getSimpleValueType();
13463 // If second operand is smaller, extend it first.
13464 if (SrcVT.bitsLT(VT)) {
13465 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
13468 // And if it is bigger, shrink it first.
13469 if (SrcVT.bitsGT(VT)) {
13470 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1, dl));
13474 // At this point the operands and the result should have the same
13475 // type, and that won't be f80 since that is not custom lowered.
13477 const fltSemantics &Sem =
13478 VT == MVT::f64 ? APFloat::IEEEdouble : APFloat::IEEEsingle;
13479 const unsigned SizeInBits = VT.getSizeInBits();
13481 SmallVector<Constant *, 4> CV(
13482 VT == MVT::f64 ? 2 : 4,
13483 ConstantFP::get(*Context, APFloat(Sem, APInt(SizeInBits, 0))));
13485 // First, clear all bits but the sign bit from the second operand (sign).
13486 CV[0] = ConstantFP::get(*Context,
13487 APFloat(Sem, APInt::getHighBitsSet(SizeInBits, 1)));
13488 Constant *C = ConstantVector::get(CV);
13489 auto PtrVT = TLI.getPointerTy(DAG.getDataLayout());
13490 SDValue CPIdx = DAG.getConstantPool(C, PtrVT, 16);
13492 // Perform all logic operations as 16-byte vectors because there are no
13493 // scalar FP logic instructions in SSE. This allows load folding of the
13494 // constants into the logic instructions.
13495 MVT LogicVT = (VT == MVT::f64) ? MVT::v2f64 : MVT::v4f32;
13497 DAG.getLoad(LogicVT, dl, DAG.getEntryNode(), CPIdx,
13498 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()),
13499 false, false, false, 16);
13500 Op1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LogicVT, Op1);
13501 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, LogicVT, Op1, Mask1);
13503 // Next, clear the sign bit from the first operand (magnitude).
13504 // If it's a constant, we can clear it here.
13505 if (ConstantFPSDNode *Op0CN = dyn_cast<ConstantFPSDNode>(Op0)) {
13506 APFloat APF = Op0CN->getValueAPF();
13507 // If the magnitude is a positive zero, the sign bit alone is enough.
13508 if (APF.isPosZero())
13509 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SrcVT, SignBit,
13510 DAG.getIntPtrConstant(0, dl));
13512 CV[0] = ConstantFP::get(*Context, APF);
13514 CV[0] = ConstantFP::get(
13516 APFloat(Sem, APInt::getLowBitsSet(SizeInBits, SizeInBits - 1)));
13518 C = ConstantVector::get(CV);
13519 CPIdx = DAG.getConstantPool(C, PtrVT, 16);
13521 DAG.getLoad(LogicVT, dl, DAG.getEntryNode(), CPIdx,
13522 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()),
13523 false, false, false, 16);
13524 // If the magnitude operand wasn't a constant, we need to AND out the sign.
13525 if (!isa<ConstantFPSDNode>(Op0)) {
13526 Op0 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LogicVT, Op0);
13527 Val = DAG.getNode(X86ISD::FAND, dl, LogicVT, Op0, Val);
13529 // OR the magnitude value with the sign bit.
13530 Val = DAG.getNode(X86ISD::FOR, dl, LogicVT, Val, SignBit);
13531 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SrcVT, Val,
13532 DAG.getIntPtrConstant(0, dl));
13535 static SDValue LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) {
13536 SDValue N0 = Op.getOperand(0);
13538 MVT VT = Op.getSimpleValueType();
13540 // Lower ISD::FGETSIGN to (AND (X86ISD::FGETSIGNx86 ...) 1).
13541 SDValue xFGETSIGN = DAG.getNode(X86ISD::FGETSIGNx86, dl, VT, N0,
13542 DAG.getConstant(1, dl, VT));
13543 return DAG.getNode(ISD::AND, dl, VT, xFGETSIGN, DAG.getConstant(1, dl, VT));
13546 // Check whether an OR'd tree is PTEST-able.
13547 static SDValue LowerVectorAllZeroTest(SDValue Op, const X86Subtarget *Subtarget,
13548 SelectionDAG &DAG) {
13549 assert(Op.getOpcode() == ISD::OR && "Only check OR'd tree.");
13551 if (!Subtarget->hasSSE41())
13554 if (!Op->hasOneUse())
13557 SDNode *N = Op.getNode();
13560 SmallVector<SDValue, 8> Opnds;
13561 DenseMap<SDValue, unsigned> VecInMap;
13562 SmallVector<SDValue, 8> VecIns;
13563 EVT VT = MVT::Other;
13565 // Recognize a special case where a vector is casted into wide integer to
13567 Opnds.push_back(N->getOperand(0));
13568 Opnds.push_back(N->getOperand(1));
13570 for (unsigned Slot = 0, e = Opnds.size(); Slot < e; ++Slot) {
13571 SmallVectorImpl<SDValue>::const_iterator I = Opnds.begin() + Slot;
13572 // BFS traverse all OR'd operands.
13573 if (I->getOpcode() == ISD::OR) {
13574 Opnds.push_back(I->getOperand(0));
13575 Opnds.push_back(I->getOperand(1));
13576 // Re-evaluate the number of nodes to be traversed.
13577 e += 2; // 2 more nodes (LHS and RHS) are pushed.
13581 // Quit if a non-EXTRACT_VECTOR_ELT
13582 if (I->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
13585 // Quit if without a constant index.
13586 SDValue Idx = I->getOperand(1);
13587 if (!isa<ConstantSDNode>(Idx))
13590 SDValue ExtractedFromVec = I->getOperand(0);
13591 DenseMap<SDValue, unsigned>::iterator M = VecInMap.find(ExtractedFromVec);
13592 if (M == VecInMap.end()) {
13593 VT = ExtractedFromVec.getValueType();
13594 // Quit if not 128/256-bit vector.
13595 if (!VT.is128BitVector() && !VT.is256BitVector())
13597 // Quit if not the same type.
13598 if (VecInMap.begin() != VecInMap.end() &&
13599 VT != VecInMap.begin()->first.getValueType())
13601 M = VecInMap.insert(std::make_pair(ExtractedFromVec, 0)).first;
13602 VecIns.push_back(ExtractedFromVec);
13604 M->second |= 1U << cast<ConstantSDNode>(Idx)->getZExtValue();
13607 assert((VT.is128BitVector() || VT.is256BitVector()) &&
13608 "Not extracted from 128-/256-bit vector.");
13610 unsigned FullMask = (1U << VT.getVectorNumElements()) - 1U;
13612 for (DenseMap<SDValue, unsigned>::const_iterator
13613 I = VecInMap.begin(), E = VecInMap.end(); I != E; ++I) {
13614 // Quit if not all elements are used.
13615 if (I->second != FullMask)
13619 MVT TestVT = VT.is128BitVector() ? MVT::v2i64 : MVT::v4i64;
13621 // Cast all vectors into TestVT for PTEST.
13622 for (unsigned i = 0, e = VecIns.size(); i < e; ++i)
13623 VecIns[i] = DAG.getBitcast(TestVT, VecIns[i]);
13625 // If more than one full vectors are evaluated, OR them first before PTEST.
13626 for (unsigned Slot = 0, e = VecIns.size(); e - Slot > 1; Slot += 2, e += 1) {
13627 // Each iteration will OR 2 nodes and append the result until there is only
13628 // 1 node left, i.e. the final OR'd value of all vectors.
13629 SDValue LHS = VecIns[Slot];
13630 SDValue RHS = VecIns[Slot + 1];
13631 VecIns.push_back(DAG.getNode(ISD::OR, DL, TestVT, LHS, RHS));
13634 return DAG.getNode(X86ISD::PTEST, DL, MVT::i32,
13635 VecIns.back(), VecIns.back());
13638 /// \brief return true if \c Op has a use that doesn't just read flags.
13639 static bool hasNonFlagsUse(SDValue Op) {
13640 for (SDNode::use_iterator UI = Op->use_begin(), UE = Op->use_end(); UI != UE;
13642 SDNode *User = *UI;
13643 unsigned UOpNo = UI.getOperandNo();
13644 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
13645 // Look pass truncate.
13646 UOpNo = User->use_begin().getOperandNo();
13647 User = *User->use_begin();
13650 if (User->getOpcode() != ISD::BRCOND && User->getOpcode() != ISD::SETCC &&
13651 !(User->getOpcode() == ISD::SELECT && UOpNo == 0))
13657 /// Emit nodes that will be selected as "test Op0,Op0", or something
13659 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC, SDLoc dl,
13660 SelectionDAG &DAG) const {
13661 if (Op.getValueType() == MVT::i1) {
13662 SDValue ExtOp = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i8, Op);
13663 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, ExtOp,
13664 DAG.getConstant(0, dl, MVT::i8));
13666 // CF and OF aren't always set the way we want. Determine which
13667 // of these we need.
13668 bool NeedCF = false;
13669 bool NeedOF = false;
13672 case X86::COND_A: case X86::COND_AE:
13673 case X86::COND_B: case X86::COND_BE:
13676 case X86::COND_G: case X86::COND_GE:
13677 case X86::COND_L: case X86::COND_LE:
13678 case X86::COND_O: case X86::COND_NO: {
13679 // Check if we really need to set the
13680 // Overflow flag. If NoSignedWrap is present
13681 // that is not actually needed.
13682 switch (Op->getOpcode()) {
13687 const auto *BinNode = cast<BinaryWithFlagsSDNode>(Op.getNode());
13688 if (BinNode->Flags.hasNoSignedWrap())
13698 // See if we can use the EFLAGS value from the operand instead of
13699 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
13700 // we prove that the arithmetic won't overflow, we can't use OF or CF.
13701 if (Op.getResNo() != 0 || NeedOF || NeedCF) {
13702 // Emit a CMP with 0, which is the TEST pattern.
13703 //if (Op.getValueType() == MVT::i1)
13704 // return DAG.getNode(X86ISD::CMP, dl, MVT::i1, Op,
13705 // DAG.getConstant(0, MVT::i1));
13706 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
13707 DAG.getConstant(0, dl, Op.getValueType()));
13709 unsigned Opcode = 0;
13710 unsigned NumOperands = 0;
13712 // Truncate operations may prevent the merge of the SETCC instruction
13713 // and the arithmetic instruction before it. Attempt to truncate the operands
13714 // of the arithmetic instruction and use a reduced bit-width instruction.
13715 bool NeedTruncation = false;
13716 SDValue ArithOp = Op;
13717 if (Op->getOpcode() == ISD::TRUNCATE && Op->hasOneUse()) {
13718 SDValue Arith = Op->getOperand(0);
13719 // Both the trunc and the arithmetic op need to have one user each.
13720 if (Arith->hasOneUse())
13721 switch (Arith.getOpcode()) {
13728 NeedTruncation = true;
13734 // NOTICE: In the code below we use ArithOp to hold the arithmetic operation
13735 // which may be the result of a CAST. We use the variable 'Op', which is the
13736 // non-casted variable when we check for possible users.
13737 switch (ArithOp.getOpcode()) {
13739 // Due to an isel shortcoming, be conservative if this add is likely to be
13740 // selected as part of a load-modify-store instruction. When the root node
13741 // in a match is a store, isel doesn't know how to remap non-chain non-flag
13742 // uses of other nodes in the match, such as the ADD in this case. This
13743 // leads to the ADD being left around and reselected, with the result being
13744 // two adds in the output. Alas, even if none our users are stores, that
13745 // doesn't prove we're O.K. Ergo, if we have any parents that aren't
13746 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require
13747 // climbing the DAG back to the root, and it doesn't seem to be worth the
13749 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
13750 UE = Op.getNode()->use_end(); UI != UE; ++UI)
13751 if (UI->getOpcode() != ISD::CopyToReg &&
13752 UI->getOpcode() != ISD::SETCC &&
13753 UI->getOpcode() != ISD::STORE)
13756 if (ConstantSDNode *C =
13757 dyn_cast<ConstantSDNode>(ArithOp.getNode()->getOperand(1))) {
13758 // An add of one will be selected as an INC.
13759 if (C->getAPIntValue() == 1 && !Subtarget->slowIncDec()) {
13760 Opcode = X86ISD::INC;
13765 // An add of negative one (subtract of one) will be selected as a DEC.
13766 if (C->getAPIntValue().isAllOnesValue() && !Subtarget->slowIncDec()) {
13767 Opcode = X86ISD::DEC;
13773 // Otherwise use a regular EFLAGS-setting add.
13774 Opcode = X86ISD::ADD;
13779 // If we have a constant logical shift that's only used in a comparison
13780 // against zero turn it into an equivalent AND. This allows turning it into
13781 // a TEST instruction later.
13782 if ((X86CC == X86::COND_E || X86CC == X86::COND_NE) && Op->hasOneUse() &&
13783 isa<ConstantSDNode>(Op->getOperand(1)) && !hasNonFlagsUse(Op)) {
13784 EVT VT = Op.getValueType();
13785 unsigned BitWidth = VT.getSizeInBits();
13786 unsigned ShAmt = Op->getConstantOperandVal(1);
13787 if (ShAmt >= BitWidth) // Avoid undefined shifts.
13789 APInt Mask = ArithOp.getOpcode() == ISD::SRL
13790 ? APInt::getHighBitsSet(BitWidth, BitWidth - ShAmt)
13791 : APInt::getLowBitsSet(BitWidth, BitWidth - ShAmt);
13792 if (!Mask.isSignedIntN(32)) // Avoid large immediates.
13794 SDValue New = DAG.getNode(ISD::AND, dl, VT, Op->getOperand(0),
13795 DAG.getConstant(Mask, dl, VT));
13796 DAG.ReplaceAllUsesWith(Op, New);
13802 // If the primary and result isn't used, don't bother using X86ISD::AND,
13803 // because a TEST instruction will be better.
13804 if (!hasNonFlagsUse(Op))
13810 // Due to the ISEL shortcoming noted above, be conservative if this op is
13811 // likely to be selected as part of a load-modify-store instruction.
13812 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
13813 UE = Op.getNode()->use_end(); UI != UE; ++UI)
13814 if (UI->getOpcode() == ISD::STORE)
13817 // Otherwise use a regular EFLAGS-setting instruction.
13818 switch (ArithOp.getOpcode()) {
13819 default: llvm_unreachable("unexpected operator!");
13820 case ISD::SUB: Opcode = X86ISD::SUB; break;
13821 case ISD::XOR: Opcode = X86ISD::XOR; break;
13822 case ISD::AND: Opcode = X86ISD::AND; break;
13824 if (!NeedTruncation && (X86CC == X86::COND_E || X86CC == X86::COND_NE)) {
13825 SDValue EFLAGS = LowerVectorAllZeroTest(Op, Subtarget, DAG);
13826 if (EFLAGS.getNode())
13829 Opcode = X86ISD::OR;
13843 return SDValue(Op.getNode(), 1);
13849 // If we found that truncation is beneficial, perform the truncation and
13851 if (NeedTruncation) {
13852 EVT VT = Op.getValueType();
13853 SDValue WideVal = Op->getOperand(0);
13854 EVT WideVT = WideVal.getValueType();
13855 unsigned ConvertedOp = 0;
13856 // Use a target machine opcode to prevent further DAGCombine
13857 // optimizations that may separate the arithmetic operations
13858 // from the setcc node.
13859 switch (WideVal.getOpcode()) {
13861 case ISD::ADD: ConvertedOp = X86ISD::ADD; break;
13862 case ISD::SUB: ConvertedOp = X86ISD::SUB; break;
13863 case ISD::AND: ConvertedOp = X86ISD::AND; break;
13864 case ISD::OR: ConvertedOp = X86ISD::OR; break;
13865 case ISD::XOR: ConvertedOp = X86ISD::XOR; break;
13869 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13870 if (TLI.isOperationLegal(WideVal.getOpcode(), WideVT)) {
13871 SDValue V0 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(0));
13872 SDValue V1 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(1));
13873 Op = DAG.getNode(ConvertedOp, dl, VT, V0, V1);
13879 // Emit a CMP with 0, which is the TEST pattern.
13880 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
13881 DAG.getConstant(0, dl, Op.getValueType()));
13883 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
13884 SmallVector<SDValue, 4> Ops(Op->op_begin(), Op->op_begin() + NumOperands);
13886 SDValue New = DAG.getNode(Opcode, dl, VTs, Ops);
13887 DAG.ReplaceAllUsesWith(Op, New);
13888 return SDValue(New.getNode(), 1);
13891 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
13893 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
13894 SDLoc dl, SelectionDAG &DAG) const {
13895 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1)) {
13896 if (C->getAPIntValue() == 0)
13897 return EmitTest(Op0, X86CC, dl, DAG);
13899 assert(Op0.getValueType() != MVT::i1 &&
13900 "Unexpected comparison operation for MVT::i1 operands");
13903 if ((Op0.getValueType() == MVT::i8 || Op0.getValueType() == MVT::i16 ||
13904 Op0.getValueType() == MVT::i32 || Op0.getValueType() == MVT::i64)) {
13905 // Do the comparison at i32 if it's smaller, besides the Atom case.
13906 // This avoids subregister aliasing issues. Keep the smaller reference
13907 // if we're optimizing for size, however, as that'll allow better folding
13908 // of memory operations.
13909 if (Op0.getValueType() != MVT::i32 && Op0.getValueType() != MVT::i64 &&
13910 !DAG.getMachineFunction().getFunction()->optForMinSize() &&
13911 !Subtarget->isAtom()) {
13912 unsigned ExtendOp =
13913 isX86CCUnsigned(X86CC) ? ISD::ZERO_EXTEND : ISD::SIGN_EXTEND;
13914 Op0 = DAG.getNode(ExtendOp, dl, MVT::i32, Op0);
13915 Op1 = DAG.getNode(ExtendOp, dl, MVT::i32, Op1);
13917 // Use SUB instead of CMP to enable CSE between SUB and CMP.
13918 SDVTList VTs = DAG.getVTList(Op0.getValueType(), MVT::i32);
13919 SDValue Sub = DAG.getNode(X86ISD::SUB, dl, VTs,
13921 return SDValue(Sub.getNode(), 1);
13923 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
13926 /// Convert a comparison if required by the subtarget.
13927 SDValue X86TargetLowering::ConvertCmpIfNecessary(SDValue Cmp,
13928 SelectionDAG &DAG) const {
13929 // If the subtarget does not support the FUCOMI instruction, floating-point
13930 // comparisons have to be converted.
13931 if (Subtarget->hasCMov() ||
13932 Cmp.getOpcode() != X86ISD::CMP ||
13933 !Cmp.getOperand(0).getValueType().isFloatingPoint() ||
13934 !Cmp.getOperand(1).getValueType().isFloatingPoint())
13937 // The instruction selector will select an FUCOM instruction instead of
13938 // FUCOMI, which writes the comparison result to FPSW instead of EFLAGS. Hence
13939 // build an SDNode sequence that transfers the result from FPSW into EFLAGS:
13940 // (X86sahf (trunc (srl (X86fp_stsw (trunc (X86cmp ...)), 8))))
13942 SDValue TruncFPSW = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, Cmp);
13943 SDValue FNStSW = DAG.getNode(X86ISD::FNSTSW16r, dl, MVT::i16, TruncFPSW);
13944 SDValue Srl = DAG.getNode(ISD::SRL, dl, MVT::i16, FNStSW,
13945 DAG.getConstant(8, dl, MVT::i8));
13946 SDValue TruncSrl = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Srl);
13947 return DAG.getNode(X86ISD::SAHF, dl, MVT::i32, TruncSrl);
13950 /// The minimum architected relative accuracy is 2^-12. We need one
13951 /// Newton-Raphson step to have a good float result (24 bits of precision).
13952 SDValue X86TargetLowering::getRsqrtEstimate(SDValue Op,
13953 DAGCombinerInfo &DCI,
13954 unsigned &RefinementSteps,
13955 bool &UseOneConstNR) const {
13956 EVT VT = Op.getValueType();
13957 const char *RecipOp;
13959 // SSE1 has rsqrtss and rsqrtps. AVX adds a 256-bit variant for rsqrtps.
13960 // TODO: Add support for AVX512 (v16f32).
13961 // It is likely not profitable to do this for f64 because a double-precision
13962 // rsqrt estimate with refinement on x86 prior to FMA requires at least 16
13963 // instructions: convert to single, rsqrtss, convert back to double, refine
13964 // (3 steps = at least 13 insts). If an 'rsqrtsd' variant was added to the ISA
13965 // along with FMA, this could be a throughput win.
13966 if (VT == MVT::f32 && Subtarget->hasSSE1())
13968 else if ((VT == MVT::v4f32 && Subtarget->hasSSE1()) ||
13969 (VT == MVT::v8f32 && Subtarget->hasAVX()))
13970 RecipOp = "vec-sqrtf";
13974 TargetRecip Recips = DCI.DAG.getTarget().Options.Reciprocals;
13975 if (!Recips.isEnabled(RecipOp))
13978 RefinementSteps = Recips.getRefinementSteps(RecipOp);
13979 UseOneConstNR = false;
13980 return DCI.DAG.getNode(X86ISD::FRSQRT, SDLoc(Op), VT, Op);
13983 /// The minimum architected relative accuracy is 2^-12. We need one
13984 /// Newton-Raphson step to have a good float result (24 bits of precision).
13985 SDValue X86TargetLowering::getRecipEstimate(SDValue Op,
13986 DAGCombinerInfo &DCI,
13987 unsigned &RefinementSteps) const {
13988 EVT VT = Op.getValueType();
13989 const char *RecipOp;
13991 // SSE1 has rcpss and rcpps. AVX adds a 256-bit variant for rcpps.
13992 // TODO: Add support for AVX512 (v16f32).
13993 // It is likely not profitable to do this for f64 because a double-precision
13994 // reciprocal estimate with refinement on x86 prior to FMA requires
13995 // 15 instructions: convert to single, rcpss, convert back to double, refine
13996 // (3 steps = 12 insts). If an 'rcpsd' variant was added to the ISA
13997 // along with FMA, this could be a throughput win.
13998 if (VT == MVT::f32 && Subtarget->hasSSE1())
14000 else if ((VT == MVT::v4f32 && Subtarget->hasSSE1()) ||
14001 (VT == MVT::v8f32 && Subtarget->hasAVX()))
14002 RecipOp = "vec-divf";
14006 TargetRecip Recips = DCI.DAG.getTarget().Options.Reciprocals;
14007 if (!Recips.isEnabled(RecipOp))
14010 RefinementSteps = Recips.getRefinementSteps(RecipOp);
14011 return DCI.DAG.getNode(X86ISD::FRCP, SDLoc(Op), VT, Op);
14014 /// If we have at least two divisions that use the same divisor, convert to
14015 /// multplication by a reciprocal. This may need to be adjusted for a given
14016 /// CPU if a division's cost is not at least twice the cost of a multiplication.
14017 /// This is because we still need one division to calculate the reciprocal and
14018 /// then we need two multiplies by that reciprocal as replacements for the
14019 /// original divisions.
14020 unsigned X86TargetLowering::combineRepeatedFPDivisors() const {
14024 static bool isAllOnes(SDValue V) {
14025 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
14026 return C && C->isAllOnesValue();
14029 /// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node
14030 /// if it's possible.
14031 SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC,
14032 SDLoc dl, SelectionDAG &DAG) const {
14033 SDValue Op0 = And.getOperand(0);
14034 SDValue Op1 = And.getOperand(1);
14035 if (Op0.getOpcode() == ISD::TRUNCATE)
14036 Op0 = Op0.getOperand(0);
14037 if (Op1.getOpcode() == ISD::TRUNCATE)
14038 Op1 = Op1.getOperand(0);
14041 if (Op1.getOpcode() == ISD::SHL)
14042 std::swap(Op0, Op1);
14043 if (Op0.getOpcode() == ISD::SHL) {
14044 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0)))
14045 if (And00C->getZExtValue() == 1) {
14046 // If we looked past a truncate, check that it's only truncating away
14048 unsigned BitWidth = Op0.getValueSizeInBits();
14049 unsigned AndBitWidth = And.getValueSizeInBits();
14050 if (BitWidth > AndBitWidth) {
14052 DAG.computeKnownBits(Op0, Zeros, Ones);
14053 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth)
14057 RHS = Op0.getOperand(1);
14059 } else if (Op1.getOpcode() == ISD::Constant) {
14060 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1);
14061 uint64_t AndRHSVal = AndRHS->getZExtValue();
14062 SDValue AndLHS = Op0;
14064 if (AndRHSVal == 1 && AndLHS.getOpcode() == ISD::SRL) {
14065 LHS = AndLHS.getOperand(0);
14066 RHS = AndLHS.getOperand(1);
14069 // Use BT if the immediate can't be encoded in a TEST instruction.
14070 if (!isUInt<32>(AndRHSVal) && isPowerOf2_64(AndRHSVal)) {
14072 RHS = DAG.getConstant(Log2_64_Ceil(AndRHSVal), dl, LHS.getValueType());
14076 if (LHS.getNode()) {
14077 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT
14078 // instruction. Since the shift amount is in-range-or-undefined, we know
14079 // that doing a bittest on the i32 value is ok. We extend to i32 because
14080 // the encoding for the i16 version is larger than the i32 version.
14081 // Also promote i16 to i32 for performance / code size reason.
14082 if (LHS.getValueType() == MVT::i8 ||
14083 LHS.getValueType() == MVT::i16)
14084 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
14086 // If the operand types disagree, extend the shift amount to match. Since
14087 // BT ignores high bits (like shifts) we can use anyextend.
14088 if (LHS.getValueType() != RHS.getValueType())
14089 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
14091 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
14092 X86::CondCode Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
14093 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
14094 DAG.getConstant(Cond, dl, MVT::i8), BT);
14100 /// \brief - Turns an ISD::CondCode into a value suitable for SSE floating point
14102 static int translateX86FSETCC(ISD::CondCode SetCCOpcode, SDValue &Op0,
14107 // SSE Condition code mapping:
14116 switch (SetCCOpcode) {
14117 default: llvm_unreachable("Unexpected SETCC condition");
14119 case ISD::SETEQ: SSECC = 0; break;
14121 case ISD::SETGT: Swap = true; // Fallthrough
14123 case ISD::SETOLT: SSECC = 1; break;
14125 case ISD::SETGE: Swap = true; // Fallthrough
14127 case ISD::SETOLE: SSECC = 2; break;
14128 case ISD::SETUO: SSECC = 3; break;
14130 case ISD::SETNE: SSECC = 4; break;
14131 case ISD::SETULE: Swap = true; // Fallthrough
14132 case ISD::SETUGE: SSECC = 5; break;
14133 case ISD::SETULT: Swap = true; // Fallthrough
14134 case ISD::SETUGT: SSECC = 6; break;
14135 case ISD::SETO: SSECC = 7; break;
14137 case ISD::SETONE: SSECC = 8; break;
14140 std::swap(Op0, Op1);
14145 // Lower256IntVSETCC - Break a VSETCC 256-bit integer VSETCC into two new 128
14146 // ones, and then concatenate the result back.
14147 static SDValue Lower256IntVSETCC(SDValue Op, SelectionDAG &DAG) {
14148 MVT VT = Op.getSimpleValueType();
14150 assert(VT.is256BitVector() && Op.getOpcode() == ISD::SETCC &&
14151 "Unsupported value type for operation");
14153 unsigned NumElems = VT.getVectorNumElements();
14155 SDValue CC = Op.getOperand(2);
14157 // Extract the LHS vectors
14158 SDValue LHS = Op.getOperand(0);
14159 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
14160 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
14162 // Extract the RHS vectors
14163 SDValue RHS = Op.getOperand(1);
14164 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
14165 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
14167 // Issue the operation on the smaller types and concatenate the result back
14168 MVT EltVT = VT.getVectorElementType();
14169 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
14170 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
14171 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1, CC),
14172 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC));
14175 static SDValue LowerBoolVSETCC_AVX512(SDValue Op, SelectionDAG &DAG) {
14176 SDValue Op0 = Op.getOperand(0);
14177 SDValue Op1 = Op.getOperand(1);
14178 SDValue CC = Op.getOperand(2);
14179 MVT VT = Op.getSimpleValueType();
14182 assert(Op0.getSimpleValueType().getVectorElementType() == MVT::i1 &&
14183 "Unexpected type for boolean compare operation");
14184 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
14185 SDValue NotOp0 = DAG.getNode(ISD::XOR, dl, VT, Op0,
14186 DAG.getConstant(-1, dl, VT));
14187 SDValue NotOp1 = DAG.getNode(ISD::XOR, dl, VT, Op1,
14188 DAG.getConstant(-1, dl, VT));
14189 switch (SetCCOpcode) {
14190 default: llvm_unreachable("Unexpected SETCC condition");
14192 // (x == y) -> ~(x ^ y)
14193 return DAG.getNode(ISD::XOR, dl, VT,
14194 DAG.getNode(ISD::XOR, dl, VT, Op0, Op1),
14195 DAG.getConstant(-1, dl, VT));
14197 // (x != y) -> (x ^ y)
14198 return DAG.getNode(ISD::XOR, dl, VT, Op0, Op1);
14201 // (x > y) -> (x & ~y)
14202 return DAG.getNode(ISD::AND, dl, VT, Op0, NotOp1);
14205 // (x < y) -> (~x & y)
14206 return DAG.getNode(ISD::AND, dl, VT, NotOp0, Op1);
14209 // (x <= y) -> (~x | y)
14210 return DAG.getNode(ISD::OR, dl, VT, NotOp0, Op1);
14213 // (x >=y) -> (x | ~y)
14214 return DAG.getNode(ISD::OR, dl, VT, Op0, NotOp1);
14218 static SDValue LowerIntVSETCC_AVX512(SDValue Op, SelectionDAG &DAG,
14219 const X86Subtarget *Subtarget) {
14220 SDValue Op0 = Op.getOperand(0);
14221 SDValue Op1 = Op.getOperand(1);
14222 SDValue CC = Op.getOperand(2);
14223 MVT VT = Op.getSimpleValueType();
14226 assert(Op0.getSimpleValueType().getVectorElementType().getSizeInBits() >= 8 &&
14227 Op.getSimpleValueType().getVectorElementType() == MVT::i1 &&
14228 "Cannot set masked compare for this operation");
14230 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
14232 bool Unsigned = false;
14235 switch (SetCCOpcode) {
14236 default: llvm_unreachable("Unexpected SETCC condition");
14237 case ISD::SETNE: SSECC = 4; break;
14238 case ISD::SETEQ: Opc = X86ISD::PCMPEQM; break;
14239 case ISD::SETUGT: SSECC = 6; Unsigned = true; break;
14240 case ISD::SETLT: Swap = true; //fall-through
14241 case ISD::SETGT: Opc = X86ISD::PCMPGTM; break;
14242 case ISD::SETULT: SSECC = 1; Unsigned = true; break;
14243 case ISD::SETUGE: SSECC = 5; Unsigned = true; break; //NLT
14244 case ISD::SETGE: Swap = true; SSECC = 2; break; // LE + swap
14245 case ISD::SETULE: Unsigned = true; //fall-through
14246 case ISD::SETLE: SSECC = 2; break;
14250 std::swap(Op0, Op1);
14252 return DAG.getNode(Opc, dl, VT, Op0, Op1);
14253 Opc = Unsigned ? X86ISD::CMPMU: X86ISD::CMPM;
14254 return DAG.getNode(Opc, dl, VT, Op0, Op1,
14255 DAG.getConstant(SSECC, dl, MVT::i8));
14258 /// \brief Try to turn a VSETULT into a VSETULE by modifying its second
14259 /// operand \p Op1. If non-trivial (for example because it's not constant)
14260 /// return an empty value.
14261 static SDValue ChangeVSETULTtoVSETULE(SDLoc dl, SDValue Op1, SelectionDAG &DAG)
14263 BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(Op1.getNode());
14267 MVT VT = Op1.getSimpleValueType();
14268 MVT EVT = VT.getVectorElementType();
14269 unsigned n = VT.getVectorNumElements();
14270 SmallVector<SDValue, 8> ULTOp1;
14272 for (unsigned i = 0; i < n; ++i) {
14273 ConstantSDNode *Elt = dyn_cast<ConstantSDNode>(BV->getOperand(i));
14274 if (!Elt || Elt->isOpaque() || Elt->getSimpleValueType(0) != EVT)
14277 // Avoid underflow.
14278 APInt Val = Elt->getAPIntValue();
14282 ULTOp1.push_back(DAG.getConstant(Val - 1, dl, EVT));
14285 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, ULTOp1);
14288 static SDValue LowerVSETCC(SDValue Op, const X86Subtarget *Subtarget,
14289 SelectionDAG &DAG) {
14290 SDValue Op0 = Op.getOperand(0);
14291 SDValue Op1 = Op.getOperand(1);
14292 SDValue CC = Op.getOperand(2);
14293 MVT VT = Op.getSimpleValueType();
14294 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
14295 bool isFP = Op.getOperand(1).getSimpleValueType().isFloatingPoint();
14300 MVT EltVT = Op0.getSimpleValueType().getVectorElementType();
14301 assert(EltVT == MVT::f32 || EltVT == MVT::f64);
14304 unsigned SSECC = translateX86FSETCC(SetCCOpcode, Op0, Op1);
14305 unsigned Opc = X86ISD::CMPP;
14306 if (Subtarget->hasAVX512() && VT.getVectorElementType() == MVT::i1) {
14307 assert(VT.getVectorNumElements() <= 16);
14308 Opc = X86ISD::CMPM;
14310 // In the two special cases we can't handle, emit two comparisons.
14313 unsigned CombineOpc;
14314 if (SetCCOpcode == ISD::SETUEQ) {
14315 CC0 = 3; CC1 = 0; CombineOpc = ISD::OR;
14317 assert(SetCCOpcode == ISD::SETONE);
14318 CC0 = 7; CC1 = 4; CombineOpc = ISD::AND;
14321 SDValue Cmp0 = DAG.getNode(Opc, dl, VT, Op0, Op1,
14322 DAG.getConstant(CC0, dl, MVT::i8));
14323 SDValue Cmp1 = DAG.getNode(Opc, dl, VT, Op0, Op1,
14324 DAG.getConstant(CC1, dl, MVT::i8));
14325 return DAG.getNode(CombineOpc, dl, VT, Cmp0, Cmp1);
14327 // Handle all other FP comparisons here.
14328 return DAG.getNode(Opc, dl, VT, Op0, Op1,
14329 DAG.getConstant(SSECC, dl, MVT::i8));
14332 MVT VTOp0 = Op0.getSimpleValueType();
14333 assert(VTOp0 == Op1.getSimpleValueType() &&
14334 "Expected operands with same type!");
14335 assert(VT.getVectorNumElements() == VTOp0.getVectorNumElements() &&
14336 "Invalid number of packed elements for source and destination!");
14338 if (VT.is128BitVector() && VTOp0.is256BitVector()) {
14339 // On non-AVX512 targets, a vector of MVT::i1 is promoted by the type
14340 // legalizer to a wider vector type. In the case of 'vsetcc' nodes, the
14341 // legalizer firstly checks if the first operand in input to the setcc has
14342 // a legal type. If so, then it promotes the return type to that same type.
14343 // Otherwise, the return type is promoted to the 'next legal type' which,
14344 // for a vector of MVT::i1 is always a 128-bit integer vector type.
14346 // We reach this code only if the following two conditions are met:
14347 // 1. Both return type and operand type have been promoted to wider types
14348 // by the type legalizer.
14349 // 2. The original operand type has been promoted to a 256-bit vector.
14351 // Note that condition 2. only applies for AVX targets.
14352 SDValue NewOp = DAG.getSetCC(dl, VTOp0, Op0, Op1, SetCCOpcode);
14353 return DAG.getZExtOrTrunc(NewOp, dl, VT);
14356 // The non-AVX512 code below works under the assumption that source and
14357 // destination types are the same.
14358 assert((Subtarget->hasAVX512() || (VT == VTOp0)) &&
14359 "Value types for source and destination must be the same!");
14361 // Break 256-bit integer vector compare into smaller ones.
14362 if (VT.is256BitVector() && !Subtarget->hasInt256())
14363 return Lower256IntVSETCC(Op, DAG);
14365 MVT OpVT = Op1.getSimpleValueType();
14366 if (OpVT.getVectorElementType() == MVT::i1)
14367 return LowerBoolVSETCC_AVX512(Op, DAG);
14369 bool MaskResult = (VT.getVectorElementType() == MVT::i1);
14370 if (Subtarget->hasAVX512()) {
14371 if (Op1.getSimpleValueType().is512BitVector() ||
14372 (Subtarget->hasBWI() && Subtarget->hasVLX()) ||
14373 (MaskResult && OpVT.getVectorElementType().getSizeInBits() >= 32))
14374 return LowerIntVSETCC_AVX512(Op, DAG, Subtarget);
14376 // In AVX-512 architecture setcc returns mask with i1 elements,
14377 // But there is no compare instruction for i8 and i16 elements in KNL.
14378 // We are not talking about 512-bit operands in this case, these
14379 // types are illegal.
14381 (OpVT.getVectorElementType().getSizeInBits() < 32 &&
14382 OpVT.getVectorElementType().getSizeInBits() >= 8))
14383 return DAG.getNode(ISD::TRUNCATE, dl, VT,
14384 DAG.getNode(ISD::SETCC, dl, OpVT, Op0, Op1, CC));
14387 // Lower using XOP integer comparisons.
14388 if ((VT == MVT::v16i8 || VT == MVT::v8i16 ||
14389 VT == MVT::v4i32 || VT == MVT::v2i64) && Subtarget->hasXOP()) {
14390 // Translate compare code to XOP PCOM compare mode.
14391 unsigned CmpMode = 0;
14392 switch (SetCCOpcode) {
14393 default: llvm_unreachable("Unexpected SETCC condition");
14395 case ISD::SETLT: CmpMode = 0x00; break;
14397 case ISD::SETLE: CmpMode = 0x01; break;
14399 case ISD::SETGT: CmpMode = 0x02; break;
14401 case ISD::SETGE: CmpMode = 0x03; break;
14402 case ISD::SETEQ: CmpMode = 0x04; break;
14403 case ISD::SETNE: CmpMode = 0x05; break;
14406 // Are we comparing unsigned or signed integers?
14407 unsigned Opc = ISD::isUnsignedIntSetCC(SetCCOpcode)
14408 ? X86ISD::VPCOMU : X86ISD::VPCOM;
14410 return DAG.getNode(Opc, dl, VT, Op0, Op1,
14411 DAG.getConstant(CmpMode, dl, MVT::i8));
14414 // We are handling one of the integer comparisons here. Since SSE only has
14415 // GT and EQ comparisons for integer, swapping operands and multiple
14416 // operations may be required for some comparisons.
14418 bool Swap = false, Invert = false, FlipSigns = false, MinMax = false;
14419 bool Subus = false;
14421 switch (SetCCOpcode) {
14422 default: llvm_unreachable("Unexpected SETCC condition");
14423 case ISD::SETNE: Invert = true;
14424 case ISD::SETEQ: Opc = X86ISD::PCMPEQ; break;
14425 case ISD::SETLT: Swap = true;
14426 case ISD::SETGT: Opc = X86ISD::PCMPGT; break;
14427 case ISD::SETGE: Swap = true;
14428 case ISD::SETLE: Opc = X86ISD::PCMPGT;
14429 Invert = true; break;
14430 case ISD::SETULT: Swap = true;
14431 case ISD::SETUGT: Opc = X86ISD::PCMPGT;
14432 FlipSigns = true; break;
14433 case ISD::SETUGE: Swap = true;
14434 case ISD::SETULE: Opc = X86ISD::PCMPGT;
14435 FlipSigns = true; Invert = true; break;
14438 // Special case: Use min/max operations for SETULE/SETUGE
14439 MVT VET = VT.getVectorElementType();
14441 (Subtarget->hasSSE41() && (VET >= MVT::i8 && VET <= MVT::i32))
14442 || (Subtarget->hasSSE2() && (VET == MVT::i8));
14445 switch (SetCCOpcode) {
14447 case ISD::SETULE: Opc = ISD::UMIN; MinMax = true; break;
14448 case ISD::SETUGE: Opc = ISD::UMAX; MinMax = true; break;
14451 if (MinMax) { Swap = false; Invert = false; FlipSigns = false; }
14454 bool hasSubus = Subtarget->hasSSE2() && (VET == MVT::i8 || VET == MVT::i16);
14455 if (!MinMax && hasSubus) {
14456 // As another special case, use PSUBUS[BW] when it's profitable. E.g. for
14458 // t = psubus Op0, Op1
14459 // pcmpeq t, <0..0>
14460 switch (SetCCOpcode) {
14462 case ISD::SETULT: {
14463 // If the comparison is against a constant we can turn this into a
14464 // setule. With psubus, setule does not require a swap. This is
14465 // beneficial because the constant in the register is no longer
14466 // destructed as the destination so it can be hoisted out of a loop.
14467 // Only do this pre-AVX since vpcmp* is no longer destructive.
14468 if (Subtarget->hasAVX())
14470 SDValue ULEOp1 = ChangeVSETULTtoVSETULE(dl, Op1, DAG);
14471 if (ULEOp1.getNode()) {
14473 Subus = true; Invert = false; Swap = false;
14477 // Psubus is better than flip-sign because it requires no inversion.
14478 case ISD::SETUGE: Subus = true; Invert = false; Swap = true; break;
14479 case ISD::SETULE: Subus = true; Invert = false; Swap = false; break;
14483 Opc = X86ISD::SUBUS;
14489 std::swap(Op0, Op1);
14491 // Check that the operation in question is available (most are plain SSE2,
14492 // but PCMPGTQ and PCMPEQQ have different requirements).
14493 if (VT == MVT::v2i64) {
14494 if (Opc == X86ISD::PCMPGT && !Subtarget->hasSSE42()) {
14495 assert(Subtarget->hasSSE2() && "Don't know how to lower!");
14497 // First cast everything to the right type.
14498 Op0 = DAG.getBitcast(MVT::v4i32, Op0);
14499 Op1 = DAG.getBitcast(MVT::v4i32, Op1);
14501 // Since SSE has no unsigned integer comparisons, we need to flip the sign
14502 // bits of the inputs before performing those operations. The lower
14503 // compare is always unsigned.
14506 SB = DAG.getConstant(0x80000000U, dl, MVT::v4i32);
14508 SDValue Sign = DAG.getConstant(0x80000000U, dl, MVT::i32);
14509 SDValue Zero = DAG.getConstant(0x00000000U, dl, MVT::i32);
14510 SB = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
14511 Sign, Zero, Sign, Zero);
14513 Op0 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op0, SB);
14514 Op1 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op1, SB);
14516 // Emulate PCMPGTQ with (hi1 > hi2) | ((hi1 == hi2) & (lo1 > lo2))
14517 SDValue GT = DAG.getNode(X86ISD::PCMPGT, dl, MVT::v4i32, Op0, Op1);
14518 SDValue EQ = DAG.getNode(X86ISD::PCMPEQ, dl, MVT::v4i32, Op0, Op1);
14520 // Create masks for only the low parts/high parts of the 64 bit integers.
14521 static const int MaskHi[] = { 1, 1, 3, 3 };
14522 static const int MaskLo[] = { 0, 0, 2, 2 };
14523 SDValue EQHi = DAG.getVectorShuffle(MVT::v4i32, dl, EQ, EQ, MaskHi);
14524 SDValue GTLo = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskLo);
14525 SDValue GTHi = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskHi);
14527 SDValue Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, EQHi, GTLo);
14528 Result = DAG.getNode(ISD::OR, dl, MVT::v4i32, Result, GTHi);
14531 Result = DAG.getNOT(dl, Result, MVT::v4i32);
14533 return DAG.getBitcast(VT, Result);
14536 if (Opc == X86ISD::PCMPEQ && !Subtarget->hasSSE41()) {
14537 // If pcmpeqq is missing but pcmpeqd is available synthesize pcmpeqq with
14538 // pcmpeqd + pshufd + pand.
14539 assert(Subtarget->hasSSE2() && !FlipSigns && "Don't know how to lower!");
14541 // First cast everything to the right type.
14542 Op0 = DAG.getBitcast(MVT::v4i32, Op0);
14543 Op1 = DAG.getBitcast(MVT::v4i32, Op1);
14546 SDValue Result = DAG.getNode(Opc, dl, MVT::v4i32, Op0, Op1);
14548 // Make sure the lower and upper halves are both all-ones.
14549 static const int Mask[] = { 1, 0, 3, 2 };
14550 SDValue Shuf = DAG.getVectorShuffle(MVT::v4i32, dl, Result, Result, Mask);
14551 Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, Result, Shuf);
14554 Result = DAG.getNOT(dl, Result, MVT::v4i32);
14556 return DAG.getBitcast(VT, Result);
14560 // Since SSE has no unsigned integer comparisons, we need to flip the sign
14561 // bits of the inputs before performing those operations.
14563 MVT EltVT = VT.getVectorElementType();
14564 SDValue SB = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()), dl,
14566 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SB);
14567 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SB);
14570 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
14572 // If the logical-not of the result is required, perform that now.
14574 Result = DAG.getNOT(dl, Result, VT);
14577 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Op0, Result);
14580 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Result,
14581 getZeroVector(VT, Subtarget, DAG, dl));
14586 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
14588 MVT VT = Op.getSimpleValueType();
14590 if (VT.isVector()) return LowerVSETCC(Op, Subtarget, DAG);
14592 assert(((!Subtarget->hasAVX512() && VT == MVT::i8) || (VT == MVT::i1))
14593 && "SetCC type must be 8-bit or 1-bit integer");
14594 SDValue Op0 = Op.getOperand(0);
14595 SDValue Op1 = Op.getOperand(1);
14597 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
14599 // Optimize to BT if possible.
14600 // Lower (X & (1 << N)) == 0 to BT(X, N).
14601 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
14602 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
14603 if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() &&
14604 Op1.getOpcode() == ISD::Constant &&
14605 cast<ConstantSDNode>(Op1)->isNullValue() &&
14606 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
14607 if (SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG)) {
14609 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, NewSetCC);
14614 // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of
14616 if (Op1.getOpcode() == ISD::Constant &&
14617 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 ||
14618 cast<ConstantSDNode>(Op1)->isNullValue()) &&
14619 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
14621 // If the input is a setcc, then reuse the input setcc or use a new one with
14622 // the inverted condition.
14623 if (Op0.getOpcode() == X86ISD::SETCC) {
14624 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0);
14625 bool Invert = (CC == ISD::SETNE) ^
14626 cast<ConstantSDNode>(Op1)->isNullValue();
14630 CCode = X86::GetOppositeBranchCondition(CCode);
14631 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
14632 DAG.getConstant(CCode, dl, MVT::i8),
14633 Op0.getOperand(1));
14635 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
14639 if ((Op0.getValueType() == MVT::i1) && (Op1.getOpcode() == ISD::Constant) &&
14640 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1) &&
14641 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
14643 ISD::CondCode NewCC = ISD::getSetCCInverse(CC, true);
14644 return DAG.getSetCC(dl, VT, Op0, DAG.getConstant(0, dl, MVT::i1), NewCC);
14647 bool isFP = Op1.getSimpleValueType().isFloatingPoint();
14648 unsigned X86CC = TranslateX86CC(CC, dl, isFP, Op0, Op1, DAG);
14649 if (X86CC == X86::COND_INVALID)
14652 SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, dl, DAG);
14653 EFLAGS = ConvertCmpIfNecessary(EFLAGS, DAG);
14654 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
14655 DAG.getConstant(X86CC, dl, MVT::i8), EFLAGS);
14657 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
14661 SDValue X86TargetLowering::LowerSETCCE(SDValue Op, SelectionDAG &DAG) const {
14662 SDValue LHS = Op.getOperand(0);
14663 SDValue RHS = Op.getOperand(1);
14664 SDValue Carry = Op.getOperand(2);
14665 SDValue Cond = Op.getOperand(3);
14668 assert(LHS.getSimpleValueType().isInteger() && "SETCCE is integer only.");
14669 X86::CondCode CC = TranslateIntegerX86CC(cast<CondCodeSDNode>(Cond)->get());
14671 assert(Carry.getOpcode() != ISD::CARRY_FALSE);
14672 SDVTList VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
14673 SDValue Cmp = DAG.getNode(X86ISD::SBB, DL, VTs, LHS, RHS, Carry);
14674 return DAG.getNode(X86ISD::SETCC, DL, Op.getValueType(),
14675 DAG.getConstant(CC, DL, MVT::i8), Cmp.getValue(1));
14678 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
14679 static bool isX86LogicalCmp(SDValue Op) {
14680 unsigned Opc = Op.getNode()->getOpcode();
14681 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI ||
14682 Opc == X86ISD::SAHF)
14684 if (Op.getResNo() == 1 &&
14685 (Opc == X86ISD::ADD ||
14686 Opc == X86ISD::SUB ||
14687 Opc == X86ISD::ADC ||
14688 Opc == X86ISD::SBB ||
14689 Opc == X86ISD::SMUL ||
14690 Opc == X86ISD::UMUL ||
14691 Opc == X86ISD::INC ||
14692 Opc == X86ISD::DEC ||
14693 Opc == X86ISD::OR ||
14694 Opc == X86ISD::XOR ||
14695 Opc == X86ISD::AND))
14698 if (Op.getResNo() == 2 && Opc == X86ISD::UMUL)
14704 static bool isTruncWithZeroHighBitsInput(SDValue V, SelectionDAG &DAG) {
14705 if (V.getOpcode() != ISD::TRUNCATE)
14708 SDValue VOp0 = V.getOperand(0);
14709 unsigned InBits = VOp0.getValueSizeInBits();
14710 unsigned Bits = V.getValueSizeInBits();
14711 return DAG.MaskedValueIsZero(VOp0, APInt::getHighBitsSet(InBits,InBits-Bits));
14714 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
14715 bool addTest = true;
14716 SDValue Cond = Op.getOperand(0);
14717 SDValue Op1 = Op.getOperand(1);
14718 SDValue Op2 = Op.getOperand(2);
14720 MVT VT = Op1.getSimpleValueType();
14723 // Lower FP selects into a CMP/AND/ANDN/OR sequence when the necessary SSE ops
14724 // are available or VBLENDV if AVX is available.
14725 // Otherwise FP cmovs get lowered into a less efficient branch sequence later.
14726 if (Cond.getOpcode() == ISD::SETCC &&
14727 ((Subtarget->hasSSE2() && (VT == MVT::f32 || VT == MVT::f64)) ||
14728 (Subtarget->hasSSE1() && VT == MVT::f32)) &&
14729 VT == Cond.getOperand(0).getSimpleValueType() && Cond->hasOneUse()) {
14730 SDValue CondOp0 = Cond.getOperand(0), CondOp1 = Cond.getOperand(1);
14731 int SSECC = translateX86FSETCC(
14732 cast<CondCodeSDNode>(Cond.getOperand(2))->get(), CondOp0, CondOp1);
14735 if (Subtarget->hasAVX512()) {
14736 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CondOp0, CondOp1,
14737 DAG.getConstant(SSECC, DL, MVT::i8));
14738 return DAG.getNode(X86ISD::SELECT, DL, VT, Cmp, Op1, Op2);
14741 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, VT, CondOp0, CondOp1,
14742 DAG.getConstant(SSECC, DL, MVT::i8));
14744 // If we have AVX, we can use a variable vector select (VBLENDV) instead
14745 // of 3 logic instructions for size savings and potentially speed.
14746 // Unfortunately, there is no scalar form of VBLENDV.
14748 // If either operand is a constant, don't try this. We can expect to
14749 // optimize away at least one of the logic instructions later in that
14750 // case, so that sequence would be faster than a variable blend.
14752 // BLENDV was introduced with SSE 4.1, but the 2 register form implicitly
14753 // uses XMM0 as the selection register. That may need just as many
14754 // instructions as the AND/ANDN/OR sequence due to register moves, so
14757 if (Subtarget->hasAVX() &&
14758 !isa<ConstantFPSDNode>(Op1) && !isa<ConstantFPSDNode>(Op2)) {
14760 // Convert to vectors, do a VSELECT, and convert back to scalar.
14761 // All of the conversions should be optimized away.
14763 MVT VecVT = VT == MVT::f32 ? MVT::v4f32 : MVT::v2f64;
14764 SDValue VOp1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VecVT, Op1);
14765 SDValue VOp2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VecVT, Op2);
14766 SDValue VCmp = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VecVT, Cmp);
14768 MVT VCmpVT = VT == MVT::f32 ? MVT::v4i32 : MVT::v2i64;
14769 VCmp = DAG.getBitcast(VCmpVT, VCmp);
14771 SDValue VSel = DAG.getNode(ISD::VSELECT, DL, VecVT, VCmp, VOp1, VOp2);
14773 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT,
14774 VSel, DAG.getIntPtrConstant(0, DL));
14776 SDValue AndN = DAG.getNode(X86ISD::FANDN, DL, VT, Cmp, Op2);
14777 SDValue And = DAG.getNode(X86ISD::FAND, DL, VT, Cmp, Op1);
14778 return DAG.getNode(X86ISD::FOR, DL, VT, AndN, And);
14782 if (VT.isVector() && VT.getVectorElementType() == MVT::i1) {
14784 if (ISD::isBuildVectorOfConstantSDNodes(Op1.getNode()))
14785 Op1Scalar = ConvertI1VectorToInteger(Op1, DAG);
14786 else if (Op1.getOpcode() == ISD::BITCAST && Op1.getOperand(0))
14787 Op1Scalar = Op1.getOperand(0);
14789 if (ISD::isBuildVectorOfConstantSDNodes(Op2.getNode()))
14790 Op2Scalar = ConvertI1VectorToInteger(Op2, DAG);
14791 else if (Op2.getOpcode() == ISD::BITCAST && Op2.getOperand(0))
14792 Op2Scalar = Op2.getOperand(0);
14793 if (Op1Scalar.getNode() && Op2Scalar.getNode()) {
14794 SDValue newSelect = DAG.getNode(ISD::SELECT, DL,
14795 Op1Scalar.getValueType(),
14796 Cond, Op1Scalar, Op2Scalar);
14797 if (newSelect.getValueSizeInBits() == VT.getSizeInBits())
14798 return DAG.getBitcast(VT, newSelect);
14799 SDValue ExtVec = DAG.getBitcast(MVT::v8i1, newSelect);
14800 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, ExtVec,
14801 DAG.getIntPtrConstant(0, DL));
14805 if (VT == MVT::v4i1 || VT == MVT::v2i1) {
14806 SDValue zeroConst = DAG.getIntPtrConstant(0, DL);
14807 Op1 = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, MVT::v8i1,
14808 DAG.getUNDEF(MVT::v8i1), Op1, zeroConst);
14809 Op2 = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, MVT::v8i1,
14810 DAG.getUNDEF(MVT::v8i1), Op2, zeroConst);
14811 SDValue newSelect = DAG.getNode(ISD::SELECT, DL, MVT::v8i1,
14813 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, newSelect, zeroConst);
14816 if (Cond.getOpcode() == ISD::SETCC) {
14817 SDValue NewCond = LowerSETCC(Cond, DAG);
14818 if (NewCond.getNode())
14822 // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y
14823 // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y
14824 // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y
14825 // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y
14826 if (Cond.getOpcode() == X86ISD::SETCC &&
14827 Cond.getOperand(1).getOpcode() == X86ISD::CMP &&
14828 isZero(Cond.getOperand(1).getOperand(1))) {
14829 SDValue Cmp = Cond.getOperand(1);
14831 unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue();
14833 if ((isAllOnes(Op1) || isAllOnes(Op2)) &&
14834 (CondCode == X86::COND_E || CondCode == X86::COND_NE)) {
14835 SDValue Y = isAllOnes(Op2) ? Op1 : Op2;
14837 SDValue CmpOp0 = Cmp.getOperand(0);
14838 // Apply further optimizations for special cases
14839 // (select (x != 0), -1, 0) -> neg & sbb
14840 // (select (x == 0), 0, -1) -> neg & sbb
14841 if (ConstantSDNode *YC = dyn_cast<ConstantSDNode>(Y))
14842 if (YC->isNullValue() &&
14843 (isAllOnes(Op1) == (CondCode == X86::COND_NE))) {
14844 SDVTList VTs = DAG.getVTList(CmpOp0.getValueType(), MVT::i32);
14845 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, VTs,
14846 DAG.getConstant(0, DL,
14847 CmpOp0.getValueType()),
14849 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
14850 DAG.getConstant(X86::COND_B, DL, MVT::i8),
14851 SDValue(Neg.getNode(), 1));
14855 Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32,
14856 CmpOp0, DAG.getConstant(1, DL, CmpOp0.getValueType()));
14857 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
14859 SDValue Res = // Res = 0 or -1.
14860 DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
14861 DAG.getConstant(X86::COND_B, DL, MVT::i8), Cmp);
14863 if (isAllOnes(Op1) != (CondCode == X86::COND_E))
14864 Res = DAG.getNOT(DL, Res, Res.getValueType());
14866 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2);
14867 if (!N2C || !N2C->isNullValue())
14868 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y);
14873 // Look past (and (setcc_carry (cmp ...)), 1).
14874 if (Cond.getOpcode() == ISD::AND &&
14875 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
14876 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
14877 if (C && C->getAPIntValue() == 1)
14878 Cond = Cond.getOperand(0);
14881 // If condition flag is set by a X86ISD::CMP, then use it as the condition
14882 // setting operand in place of the X86ISD::SETCC.
14883 unsigned CondOpcode = Cond.getOpcode();
14884 if (CondOpcode == X86ISD::SETCC ||
14885 CondOpcode == X86ISD::SETCC_CARRY) {
14886 CC = Cond.getOperand(0);
14888 SDValue Cmp = Cond.getOperand(1);
14889 unsigned Opc = Cmp.getOpcode();
14890 MVT VT = Op.getSimpleValueType();
14892 bool IllegalFPCMov = false;
14893 if (VT.isFloatingPoint() && !VT.isVector() &&
14894 !isScalarFPTypeInSSEReg(VT)) // FPStack?
14895 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
14897 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
14898 Opc == X86ISD::BT) { // FIXME
14902 } else if (CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
14903 CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
14904 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
14905 Cond.getOperand(0).getValueType() != MVT::i8)) {
14906 SDValue LHS = Cond.getOperand(0);
14907 SDValue RHS = Cond.getOperand(1);
14908 unsigned X86Opcode;
14911 switch (CondOpcode) {
14912 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
14913 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
14914 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
14915 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
14916 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
14917 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
14918 default: llvm_unreachable("unexpected overflowing operator");
14920 if (CondOpcode == ISD::UMULO)
14921 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
14924 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
14926 SDValue X86Op = DAG.getNode(X86Opcode, DL, VTs, LHS, RHS);
14928 if (CondOpcode == ISD::UMULO)
14929 Cond = X86Op.getValue(2);
14931 Cond = X86Op.getValue(1);
14933 CC = DAG.getConstant(X86Cond, DL, MVT::i8);
14938 // Look past the truncate if the high bits are known zero.
14939 if (isTruncWithZeroHighBitsInput(Cond, DAG))
14940 Cond = Cond.getOperand(0);
14942 // We know the result of AND is compared against zero. Try to match
14944 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
14945 if (SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG)) {
14946 CC = NewSetCC.getOperand(0);
14947 Cond = NewSetCC.getOperand(1);
14954 CC = DAG.getConstant(X86::COND_NE, DL, MVT::i8);
14955 Cond = EmitTest(Cond, X86::COND_NE, DL, DAG);
14958 // a < b ? -1 : 0 -> RES = ~setcc_carry
14959 // a < b ? 0 : -1 -> RES = setcc_carry
14960 // a >= b ? -1 : 0 -> RES = setcc_carry
14961 // a >= b ? 0 : -1 -> RES = ~setcc_carry
14962 if (Cond.getOpcode() == X86ISD::SUB) {
14963 Cond = ConvertCmpIfNecessary(Cond, DAG);
14964 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue();
14966 if ((CondCode == X86::COND_AE || CondCode == X86::COND_B) &&
14967 (isAllOnes(Op1) || isAllOnes(Op2)) && (isZero(Op1) || isZero(Op2))) {
14968 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
14969 DAG.getConstant(X86::COND_B, DL, MVT::i8),
14971 if (isAllOnes(Op1) != (CondCode == X86::COND_B))
14972 return DAG.getNOT(DL, Res, Res.getValueType());
14977 // X86 doesn't have an i8 cmov. If both operands are the result of a truncate
14978 // widen the cmov and push the truncate through. This avoids introducing a new
14979 // branch during isel and doesn't add any extensions.
14980 if (Op.getValueType() == MVT::i8 &&
14981 Op1.getOpcode() == ISD::TRUNCATE && Op2.getOpcode() == ISD::TRUNCATE) {
14982 SDValue T1 = Op1.getOperand(0), T2 = Op2.getOperand(0);
14983 if (T1.getValueType() == T2.getValueType() &&
14984 // Blacklist CopyFromReg to avoid partial register stalls.
14985 T1.getOpcode() != ISD::CopyFromReg && T2.getOpcode()!=ISD::CopyFromReg){
14986 SDVTList VTs = DAG.getVTList(T1.getValueType(), MVT::Glue);
14987 SDValue Cmov = DAG.getNode(X86ISD::CMOV, DL, VTs, T2, T1, CC, Cond);
14988 return DAG.getNode(ISD::TRUNCATE, DL, Op.getValueType(), Cmov);
14992 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
14993 // condition is true.
14994 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
14995 SDValue Ops[] = { Op2, Op1, CC, Cond };
14996 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops);
14999 static SDValue LowerSIGN_EXTEND_AVX512(SDValue Op,
15000 const X86Subtarget *Subtarget,
15001 SelectionDAG &DAG) {
15002 MVT VT = Op->getSimpleValueType(0);
15003 SDValue In = Op->getOperand(0);
15004 MVT InVT = In.getSimpleValueType();
15005 MVT VTElt = VT.getVectorElementType();
15006 MVT InVTElt = InVT.getVectorElementType();
15010 if ((InVTElt == MVT::i1) &&
15011 (((Subtarget->hasBWI() && Subtarget->hasVLX() &&
15012 VT.getSizeInBits() <= 256 && VTElt.getSizeInBits() <= 16)) ||
15014 ((Subtarget->hasBWI() && VT.is512BitVector() &&
15015 VTElt.getSizeInBits() <= 16)) ||
15017 ((Subtarget->hasDQI() && Subtarget->hasVLX() &&
15018 VT.getSizeInBits() <= 256 && VTElt.getSizeInBits() >= 32)) ||
15020 ((Subtarget->hasDQI() && VT.is512BitVector() &&
15021 VTElt.getSizeInBits() >= 32))))
15022 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
15024 unsigned int NumElts = VT.getVectorNumElements();
15026 if (NumElts != 8 && NumElts != 16 && !Subtarget->hasBWI())
15029 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1) {
15030 if (In.getOpcode() == X86ISD::VSEXT || In.getOpcode() == X86ISD::VZEXT)
15031 return DAG.getNode(In.getOpcode(), dl, VT, In.getOperand(0));
15032 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
15035 assert (InVT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
15036 MVT ExtVT = NumElts == 8 ? MVT::v8i64 : MVT::v16i32;
15038 DAG.getConstant(APInt::getAllOnesValue(ExtVT.getScalarSizeInBits()), dl,
15041 DAG.getConstant(APInt::getNullValue(ExtVT.getScalarSizeInBits()), dl, ExtVT);
15043 SDValue V = DAG.getNode(ISD::VSELECT, dl, ExtVT, In, NegOne, Zero);
15044 if (VT.is512BitVector())
15046 return DAG.getNode(X86ISD::VTRUNC, dl, VT, V);
15049 static SDValue LowerSIGN_EXTEND_VECTOR_INREG(SDValue Op,
15050 const X86Subtarget *Subtarget,
15051 SelectionDAG &DAG) {
15052 SDValue In = Op->getOperand(0);
15053 MVT VT = Op->getSimpleValueType(0);
15054 MVT InVT = In.getSimpleValueType();
15055 assert(VT.getSizeInBits() == InVT.getSizeInBits());
15057 MVT InSVT = InVT.getVectorElementType();
15058 assert(VT.getVectorElementType().getSizeInBits() > InSVT.getSizeInBits());
15060 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16)
15062 if (InSVT != MVT::i32 && InSVT != MVT::i16 && InSVT != MVT::i8)
15067 // SSE41 targets can use the pmovsx* instructions directly.
15068 if (Subtarget->hasSSE41())
15069 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
15071 // pre-SSE41 targets unpack lower lanes and then sign-extend using SRAI.
15075 // As SRAI is only available on i16/i32 types, we expand only up to i32
15076 // and handle i64 separately.
15077 while (CurrVT != VT && CurrVT.getVectorElementType() != MVT::i32) {
15078 Curr = DAG.getNode(X86ISD::UNPCKL, dl, CurrVT, DAG.getUNDEF(CurrVT), Curr);
15079 MVT CurrSVT = MVT::getIntegerVT(CurrVT.getScalarSizeInBits() * 2);
15080 CurrVT = MVT::getVectorVT(CurrSVT, CurrVT.getVectorNumElements() / 2);
15081 Curr = DAG.getBitcast(CurrVT, Curr);
15084 SDValue SignExt = Curr;
15085 if (CurrVT != InVT) {
15086 unsigned SignExtShift =
15087 CurrVT.getVectorElementType().getSizeInBits() - InSVT.getSizeInBits();
15088 SignExt = DAG.getNode(X86ISD::VSRAI, dl, CurrVT, Curr,
15089 DAG.getConstant(SignExtShift, dl, MVT::i8));
15095 if (VT == MVT::v2i64 && CurrVT == MVT::v4i32) {
15096 SDValue Sign = DAG.getNode(X86ISD::VSRAI, dl, CurrVT, Curr,
15097 DAG.getConstant(31, dl, MVT::i8));
15098 SDValue Ext = DAG.getVectorShuffle(CurrVT, dl, SignExt, Sign, {0, 4, 1, 5});
15099 return DAG.getBitcast(VT, Ext);
15105 static SDValue LowerSIGN_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
15106 SelectionDAG &DAG) {
15107 MVT VT = Op->getSimpleValueType(0);
15108 SDValue In = Op->getOperand(0);
15109 MVT InVT = In.getSimpleValueType();
15112 if (VT.is512BitVector() || InVT.getVectorElementType() == MVT::i1)
15113 return LowerSIGN_EXTEND_AVX512(Op, Subtarget, DAG);
15115 if ((VT != MVT::v4i64 || InVT != MVT::v4i32) &&
15116 (VT != MVT::v8i32 || InVT != MVT::v8i16) &&
15117 (VT != MVT::v16i16 || InVT != MVT::v16i8))
15120 if (Subtarget->hasInt256())
15121 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
15123 // Optimize vectors in AVX mode
15124 // Sign extend v8i16 to v8i32 and
15127 // Divide input vector into two parts
15128 // for v4i32 the shuffle mask will be { 0, 1, -1, -1} {2, 3, -1, -1}
15129 // use vpmovsx instruction to extend v4i32 -> v2i64; v8i16 -> v4i32
15130 // concat the vectors to original VT
15132 unsigned NumElems = InVT.getVectorNumElements();
15133 SDValue Undef = DAG.getUNDEF(InVT);
15135 SmallVector<int,8> ShufMask1(NumElems, -1);
15136 for (unsigned i = 0; i != NumElems/2; ++i)
15139 SDValue OpLo = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask1[0]);
15141 SmallVector<int,8> ShufMask2(NumElems, -1);
15142 for (unsigned i = 0; i != NumElems/2; ++i)
15143 ShufMask2[i] = i + NumElems/2;
15145 SDValue OpHi = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask2[0]);
15147 MVT HalfVT = MVT::getVectorVT(VT.getVectorElementType(),
15148 VT.getVectorNumElements()/2);
15150 OpLo = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpLo);
15151 OpHi = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpHi);
15153 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
15156 // Lower vector extended loads using a shuffle. If SSSE3 is not available we
15157 // may emit an illegal shuffle but the expansion is still better than scalar
15158 // code. We generate X86ISD::VSEXT for SEXTLOADs if it's available, otherwise
15159 // we'll emit a shuffle and a arithmetic shift.
15160 // FIXME: Is the expansion actually better than scalar code? It doesn't seem so.
15161 // TODO: It is possible to support ZExt by zeroing the undef values during
15162 // the shuffle phase or after the shuffle.
15163 static SDValue LowerExtendedLoad(SDValue Op, const X86Subtarget *Subtarget,
15164 SelectionDAG &DAG) {
15165 MVT RegVT = Op.getSimpleValueType();
15166 assert(RegVT.isVector() && "We only custom lower vector sext loads.");
15167 assert(RegVT.isInteger() &&
15168 "We only custom lower integer vector sext loads.");
15170 // Nothing useful we can do without SSE2 shuffles.
15171 assert(Subtarget->hasSSE2() && "We only custom lower sext loads with SSE2.");
15173 LoadSDNode *Ld = cast<LoadSDNode>(Op.getNode());
15175 EVT MemVT = Ld->getMemoryVT();
15176 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
15177 unsigned RegSz = RegVT.getSizeInBits();
15179 ISD::LoadExtType Ext = Ld->getExtensionType();
15181 assert((Ext == ISD::EXTLOAD || Ext == ISD::SEXTLOAD)
15182 && "Only anyext and sext are currently implemented.");
15183 assert(MemVT != RegVT && "Cannot extend to the same type");
15184 assert(MemVT.isVector() && "Must load a vector from memory");
15186 unsigned NumElems = RegVT.getVectorNumElements();
15187 unsigned MemSz = MemVT.getSizeInBits();
15188 assert(RegSz > MemSz && "Register size must be greater than the mem size");
15190 if (Ext == ISD::SEXTLOAD && RegSz == 256 && !Subtarget->hasInt256()) {
15191 // The only way in which we have a legal 256-bit vector result but not the
15192 // integer 256-bit operations needed to directly lower a sextload is if we
15193 // have AVX1 but not AVX2. In that case, we can always emit a sextload to
15194 // a 128-bit vector and a normal sign_extend to 256-bits that should get
15195 // correctly legalized. We do this late to allow the canonical form of
15196 // sextload to persist throughout the rest of the DAG combiner -- it wants
15197 // to fold together any extensions it can, and so will fuse a sign_extend
15198 // of an sextload into a sextload targeting a wider value.
15200 if (MemSz == 128) {
15201 // Just switch this to a normal load.
15202 assert(TLI.isTypeLegal(MemVT) && "If the memory type is a 128-bit type, "
15203 "it must be a legal 128-bit vector "
15205 Load = DAG.getLoad(MemVT, dl, Ld->getChain(), Ld->getBasePtr(),
15206 Ld->getPointerInfo(), Ld->isVolatile(), Ld->isNonTemporal(),
15207 Ld->isInvariant(), Ld->getAlignment());
15209 assert(MemSz < 128 &&
15210 "Can't extend a type wider than 128 bits to a 256 bit vector!");
15211 // Do an sext load to a 128-bit vector type. We want to use the same
15212 // number of elements, but elements half as wide. This will end up being
15213 // recursively lowered by this routine, but will succeed as we definitely
15214 // have all the necessary features if we're using AVX1.
15216 EVT::getIntegerVT(*DAG.getContext(), RegVT.getScalarSizeInBits() / 2);
15217 EVT HalfVecVT = EVT::getVectorVT(*DAG.getContext(), HalfEltVT, NumElems);
15219 DAG.getExtLoad(Ext, dl, HalfVecVT, Ld->getChain(), Ld->getBasePtr(),
15220 Ld->getPointerInfo(), MemVT, Ld->isVolatile(),
15221 Ld->isNonTemporal(), Ld->isInvariant(),
15222 Ld->getAlignment());
15225 // Replace chain users with the new chain.
15226 assert(Load->getNumValues() == 2 && "Loads must carry a chain!");
15227 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), Load.getValue(1));
15229 // Finally, do a normal sign-extend to the desired register.
15230 return DAG.getSExtOrTrunc(Load, dl, RegVT);
15233 // All sizes must be a power of two.
15234 assert(isPowerOf2_32(RegSz * MemSz * NumElems) &&
15235 "Non-power-of-two elements are not custom lowered!");
15237 // Attempt to load the original value using scalar loads.
15238 // Find the largest scalar type that divides the total loaded size.
15239 MVT SclrLoadTy = MVT::i8;
15240 for (MVT Tp : MVT::integer_valuetypes()) {
15241 if (TLI.isTypeLegal(Tp) && ((MemSz % Tp.getSizeInBits()) == 0)) {
15246 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
15247 if (TLI.isTypeLegal(MVT::f64) && SclrLoadTy.getSizeInBits() < 64 &&
15249 SclrLoadTy = MVT::f64;
15251 // Calculate the number of scalar loads that we need to perform
15252 // in order to load our vector from memory.
15253 unsigned NumLoads = MemSz / SclrLoadTy.getSizeInBits();
15255 assert((Ext != ISD::SEXTLOAD || NumLoads == 1) &&
15256 "Can only lower sext loads with a single scalar load!");
15258 unsigned loadRegZize = RegSz;
15259 if (Ext == ISD::SEXTLOAD && RegSz >= 256)
15262 // Represent our vector as a sequence of elements which are the
15263 // largest scalar that we can load.
15264 EVT LoadUnitVecVT = EVT::getVectorVT(
15265 *DAG.getContext(), SclrLoadTy, loadRegZize / SclrLoadTy.getSizeInBits());
15267 // Represent the data using the same element type that is stored in
15268 // memory. In practice, we ''widen'' MemVT.
15270 EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
15271 loadRegZize / MemVT.getScalarSizeInBits());
15273 assert(WideVecVT.getSizeInBits() == LoadUnitVecVT.getSizeInBits() &&
15274 "Invalid vector type");
15276 // We can't shuffle using an illegal type.
15277 assert(TLI.isTypeLegal(WideVecVT) &&
15278 "We only lower types that form legal widened vector types");
15280 SmallVector<SDValue, 8> Chains;
15281 SDValue Ptr = Ld->getBasePtr();
15282 SDValue Increment = DAG.getConstant(SclrLoadTy.getSizeInBits() / 8, dl,
15283 TLI.getPointerTy(DAG.getDataLayout()));
15284 SDValue Res = DAG.getUNDEF(LoadUnitVecVT);
15286 for (unsigned i = 0; i < NumLoads; ++i) {
15287 // Perform a single load.
15288 SDValue ScalarLoad =
15289 DAG.getLoad(SclrLoadTy, dl, Ld->getChain(), Ptr, Ld->getPointerInfo(),
15290 Ld->isVolatile(), Ld->isNonTemporal(), Ld->isInvariant(),
15291 Ld->getAlignment());
15292 Chains.push_back(ScalarLoad.getValue(1));
15293 // Create the first element type using SCALAR_TO_VECTOR in order to avoid
15294 // another round of DAGCombining.
15296 Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LoadUnitVecVT, ScalarLoad);
15298 Res = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, LoadUnitVecVT, Res,
15299 ScalarLoad, DAG.getIntPtrConstant(i, dl));
15301 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
15304 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
15306 // Bitcast the loaded value to a vector of the original element type, in
15307 // the size of the target vector type.
15308 SDValue SlicedVec = DAG.getBitcast(WideVecVT, Res);
15309 unsigned SizeRatio = RegSz / MemSz;
15311 if (Ext == ISD::SEXTLOAD) {
15312 // If we have SSE4.1, we can directly emit a VSEXT node.
15313 if (Subtarget->hasSSE41()) {
15314 SDValue Sext = DAG.getNode(X86ISD::VSEXT, dl, RegVT, SlicedVec);
15315 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
15319 // Otherwise we'll use SIGN_EXTEND_VECTOR_INREG to sign extend the lowest
15321 assert(TLI.isOperationLegalOrCustom(ISD::SIGN_EXTEND_VECTOR_INREG, RegVT) &&
15322 "We can't implement a sext load without SIGN_EXTEND_VECTOR_INREG!");
15324 SDValue Shuff = DAG.getSignExtendVectorInReg(SlicedVec, dl, RegVT);
15325 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
15329 // Redistribute the loaded elements into the different locations.
15330 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
15331 for (unsigned i = 0; i != NumElems; ++i)
15332 ShuffleVec[i * SizeRatio] = i;
15334 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec,
15335 DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
15337 // Bitcast to the requested type.
15338 Shuff = DAG.getBitcast(RegVT, Shuff);
15339 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
15343 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
15344 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
15345 // from the AND / OR.
15346 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
15347 Opc = Op.getOpcode();
15348 if (Opc != ISD::OR && Opc != ISD::AND)
15350 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
15351 Op.getOperand(0).hasOneUse() &&
15352 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
15353 Op.getOperand(1).hasOneUse());
15356 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
15357 // 1 and that the SETCC node has a single use.
15358 static bool isXor1OfSetCC(SDValue Op) {
15359 if (Op.getOpcode() != ISD::XOR)
15361 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
15362 if (N1C && N1C->getAPIntValue() == 1) {
15363 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
15364 Op.getOperand(0).hasOneUse();
15369 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
15370 bool addTest = true;
15371 SDValue Chain = Op.getOperand(0);
15372 SDValue Cond = Op.getOperand(1);
15373 SDValue Dest = Op.getOperand(2);
15376 bool Inverted = false;
15378 if (Cond.getOpcode() == ISD::SETCC) {
15379 // Check for setcc([su]{add,sub,mul}o == 0).
15380 if (cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETEQ &&
15381 isa<ConstantSDNode>(Cond.getOperand(1)) &&
15382 cast<ConstantSDNode>(Cond.getOperand(1))->isNullValue() &&
15383 Cond.getOperand(0).getResNo() == 1 &&
15384 (Cond.getOperand(0).getOpcode() == ISD::SADDO ||
15385 Cond.getOperand(0).getOpcode() == ISD::UADDO ||
15386 Cond.getOperand(0).getOpcode() == ISD::SSUBO ||
15387 Cond.getOperand(0).getOpcode() == ISD::USUBO ||
15388 Cond.getOperand(0).getOpcode() == ISD::SMULO ||
15389 Cond.getOperand(0).getOpcode() == ISD::UMULO)) {
15391 Cond = Cond.getOperand(0);
15393 SDValue NewCond = LowerSETCC(Cond, DAG);
15394 if (NewCond.getNode())
15399 // FIXME: LowerXALUO doesn't handle these!!
15400 else if (Cond.getOpcode() == X86ISD::ADD ||
15401 Cond.getOpcode() == X86ISD::SUB ||
15402 Cond.getOpcode() == X86ISD::SMUL ||
15403 Cond.getOpcode() == X86ISD::UMUL)
15404 Cond = LowerXALUO(Cond, DAG);
15407 // Look pass (and (setcc_carry (cmp ...)), 1).
15408 if (Cond.getOpcode() == ISD::AND &&
15409 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
15410 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
15411 if (C && C->getAPIntValue() == 1)
15412 Cond = Cond.getOperand(0);
15415 // If condition flag is set by a X86ISD::CMP, then use it as the condition
15416 // setting operand in place of the X86ISD::SETCC.
15417 unsigned CondOpcode = Cond.getOpcode();
15418 if (CondOpcode == X86ISD::SETCC ||
15419 CondOpcode == X86ISD::SETCC_CARRY) {
15420 CC = Cond.getOperand(0);
15422 SDValue Cmp = Cond.getOperand(1);
15423 unsigned Opc = Cmp.getOpcode();
15424 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
15425 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
15429 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
15433 // These can only come from an arithmetic instruction with overflow,
15434 // e.g. SADDO, UADDO.
15435 Cond = Cond.getNode()->getOperand(1);
15441 CondOpcode = Cond.getOpcode();
15442 if (CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
15443 CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
15444 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
15445 Cond.getOperand(0).getValueType() != MVT::i8)) {
15446 SDValue LHS = Cond.getOperand(0);
15447 SDValue RHS = Cond.getOperand(1);
15448 unsigned X86Opcode;
15451 // Keep this in sync with LowerXALUO, otherwise we might create redundant
15452 // instructions that can't be removed afterwards (i.e. X86ISD::ADD and
15454 switch (CondOpcode) {
15455 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
15457 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
15459 X86Opcode = X86ISD::INC; X86Cond = X86::COND_O;
15462 X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
15463 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
15465 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
15467 X86Opcode = X86ISD::DEC; X86Cond = X86::COND_O;
15470 X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
15471 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
15472 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
15473 default: llvm_unreachable("unexpected overflowing operator");
15476 X86Cond = X86::GetOppositeBranchCondition((X86::CondCode)X86Cond);
15477 if (CondOpcode == ISD::UMULO)
15478 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
15481 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
15483 SDValue X86Op = DAG.getNode(X86Opcode, dl, VTs, LHS, RHS);
15485 if (CondOpcode == ISD::UMULO)
15486 Cond = X86Op.getValue(2);
15488 Cond = X86Op.getValue(1);
15490 CC = DAG.getConstant(X86Cond, dl, MVT::i8);
15494 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
15495 SDValue Cmp = Cond.getOperand(0).getOperand(1);
15496 if (CondOpc == ISD::OR) {
15497 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
15498 // two branches instead of an explicit OR instruction with a
15500 if (Cmp == Cond.getOperand(1).getOperand(1) &&
15501 isX86LogicalCmp(Cmp)) {
15502 CC = Cond.getOperand(0).getOperand(0);
15503 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15504 Chain, Dest, CC, Cmp);
15505 CC = Cond.getOperand(1).getOperand(0);
15509 } else { // ISD::AND
15510 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
15511 // two branches instead of an explicit AND instruction with a
15512 // separate test. However, we only do this if this block doesn't
15513 // have a fall-through edge, because this requires an explicit
15514 // jmp when the condition is false.
15515 if (Cmp == Cond.getOperand(1).getOperand(1) &&
15516 isX86LogicalCmp(Cmp) &&
15517 Op.getNode()->hasOneUse()) {
15518 X86::CondCode CCode =
15519 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
15520 CCode = X86::GetOppositeBranchCondition(CCode);
15521 CC = DAG.getConstant(CCode, dl, MVT::i8);
15522 SDNode *User = *Op.getNode()->use_begin();
15523 // Look for an unconditional branch following this conditional branch.
15524 // We need this because we need to reverse the successors in order
15525 // to implement FCMP_OEQ.
15526 if (User->getOpcode() == ISD::BR) {
15527 SDValue FalseBB = User->getOperand(1);
15529 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
15530 assert(NewBR == User);
15534 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15535 Chain, Dest, CC, Cmp);
15536 X86::CondCode CCode =
15537 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
15538 CCode = X86::GetOppositeBranchCondition(CCode);
15539 CC = DAG.getConstant(CCode, dl, MVT::i8);
15545 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
15546 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
15547 // It should be transformed during dag combiner except when the condition
15548 // is set by a arithmetics with overflow node.
15549 X86::CondCode CCode =
15550 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
15551 CCode = X86::GetOppositeBranchCondition(CCode);
15552 CC = DAG.getConstant(CCode, dl, MVT::i8);
15553 Cond = Cond.getOperand(0).getOperand(1);
15555 } else if (Cond.getOpcode() == ISD::SETCC &&
15556 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETOEQ) {
15557 // For FCMP_OEQ, we can emit
15558 // two branches instead of an explicit AND instruction with a
15559 // separate test. However, we only do this if this block doesn't
15560 // have a fall-through edge, because this requires an explicit
15561 // jmp when the condition is false.
15562 if (Op.getNode()->hasOneUse()) {
15563 SDNode *User = *Op.getNode()->use_begin();
15564 // Look for an unconditional branch following this conditional branch.
15565 // We need this because we need to reverse the successors in order
15566 // to implement FCMP_OEQ.
15567 if (User->getOpcode() == ISD::BR) {
15568 SDValue FalseBB = User->getOperand(1);
15570 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
15571 assert(NewBR == User);
15575 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
15576 Cond.getOperand(0), Cond.getOperand(1));
15577 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
15578 CC = DAG.getConstant(X86::COND_NE, dl, MVT::i8);
15579 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15580 Chain, Dest, CC, Cmp);
15581 CC = DAG.getConstant(X86::COND_P, dl, MVT::i8);
15586 } else if (Cond.getOpcode() == ISD::SETCC &&
15587 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETUNE) {
15588 // For FCMP_UNE, we can emit
15589 // two branches instead of an explicit AND instruction with a
15590 // separate test. However, we only do this if this block doesn't
15591 // have a fall-through edge, because this requires an explicit
15592 // jmp when the condition is false.
15593 if (Op.getNode()->hasOneUse()) {
15594 SDNode *User = *Op.getNode()->use_begin();
15595 // Look for an unconditional branch following this conditional branch.
15596 // We need this because we need to reverse the successors in order
15597 // to implement FCMP_UNE.
15598 if (User->getOpcode() == ISD::BR) {
15599 SDValue FalseBB = User->getOperand(1);
15601 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
15602 assert(NewBR == User);
15605 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
15606 Cond.getOperand(0), Cond.getOperand(1));
15607 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
15608 CC = DAG.getConstant(X86::COND_NE, dl, MVT::i8);
15609 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15610 Chain, Dest, CC, Cmp);
15611 CC = DAG.getConstant(X86::COND_NP, dl, MVT::i8);
15621 // Look pass the truncate if the high bits are known zero.
15622 if (isTruncWithZeroHighBitsInput(Cond, DAG))
15623 Cond = Cond.getOperand(0);
15625 // We know the result of AND is compared against zero. Try to match
15627 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
15628 if (SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG)) {
15629 CC = NewSetCC.getOperand(0);
15630 Cond = NewSetCC.getOperand(1);
15637 X86::CondCode X86Cond = Inverted ? X86::COND_E : X86::COND_NE;
15638 CC = DAG.getConstant(X86Cond, dl, MVT::i8);
15639 Cond = EmitTest(Cond, X86Cond, dl, DAG);
15641 Cond = ConvertCmpIfNecessary(Cond, DAG);
15642 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15643 Chain, Dest, CC, Cond);
15646 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
15647 // Calls to _alloca are needed to probe the stack when allocating more than 4k
15648 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
15649 // that the guard pages used by the OS virtual memory manager are allocated in
15650 // correct sequence.
15652 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
15653 SelectionDAG &DAG) const {
15654 MachineFunction &MF = DAG.getMachineFunction();
15655 bool SplitStack = MF.shouldSplitStack();
15656 bool Lower = (Subtarget->isOSWindows() && !Subtarget->isTargetMachO()) ||
15661 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
15662 SDNode* Node = Op.getNode();
15664 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
15665 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
15666 " not tell us which reg is the stack pointer!");
15667 EVT VT = Node->getValueType(0);
15668 SDValue Tmp1 = SDValue(Node, 0);
15669 SDValue Tmp2 = SDValue(Node, 1);
15670 SDValue Tmp3 = Node->getOperand(2);
15671 SDValue Chain = Tmp1.getOperand(0);
15673 // Chain the dynamic stack allocation so that it doesn't modify the stack
15674 // pointer when other instructions are using the stack.
15675 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, dl, true),
15678 SDValue Size = Tmp2.getOperand(1);
15679 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT);
15680 Chain = SP.getValue(1);
15681 unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue();
15682 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
15683 unsigned StackAlign = TFI.getStackAlignment();
15684 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value
15685 if (Align > StackAlign)
15686 Tmp1 = DAG.getNode(ISD::AND, dl, VT, Tmp1,
15687 DAG.getConstant(-(uint64_t)Align, dl, VT));
15688 Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); // Output chain
15690 Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, dl, true),
15691 DAG.getIntPtrConstant(0, dl, true), SDValue(),
15694 SDValue Ops[2] = { Tmp1, Tmp2 };
15695 return DAG.getMergeValues(Ops, dl);
15699 SDValue Chain = Op.getOperand(0);
15700 SDValue Size = Op.getOperand(1);
15701 unsigned Align = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
15702 EVT VT = Op.getNode()->getValueType(0);
15704 bool Is64Bit = Subtarget->is64Bit();
15705 MVT SPTy = getPointerTy(DAG.getDataLayout());
15708 MachineRegisterInfo &MRI = MF.getRegInfo();
15711 // The 64 bit implementation of segmented stacks needs to clobber both r10
15712 // r11. This makes it impossible to use it along with nested parameters.
15713 const Function *F = MF.getFunction();
15715 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
15717 if (I->hasNestAttr())
15718 report_fatal_error("Cannot use segmented stacks with functions that "
15719 "have nested arguments.");
15722 const TargetRegisterClass *AddrRegClass = getRegClassFor(SPTy);
15723 unsigned Vreg = MRI.createVirtualRegister(AddrRegClass);
15724 Chain = DAG.getCopyToReg(Chain, dl, Vreg, Size);
15725 SDValue Value = DAG.getNode(X86ISD::SEG_ALLOCA, dl, SPTy, Chain,
15726 DAG.getRegister(Vreg, SPTy));
15727 SDValue Ops1[2] = { Value, Chain };
15728 return DAG.getMergeValues(Ops1, dl);
15731 const unsigned Reg = (Subtarget->isTarget64BitLP64() ? X86::RAX : X86::EAX);
15733 Chain = DAG.getCopyToReg(Chain, dl, Reg, Size, Flag);
15734 Flag = Chain.getValue(1);
15735 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
15737 Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag);
15739 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
15740 unsigned SPReg = RegInfo->getStackRegister();
15741 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, SPTy);
15742 Chain = SP.getValue(1);
15745 SP = DAG.getNode(ISD::AND, dl, VT, SP.getValue(0),
15746 DAG.getConstant(-(uint64_t)Align, dl, VT));
15747 Chain = DAG.getCopyToReg(Chain, dl, SPReg, SP);
15750 SDValue Ops1[2] = { SP, Chain };
15751 return DAG.getMergeValues(Ops1, dl);
15755 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
15756 MachineFunction &MF = DAG.getMachineFunction();
15757 auto PtrVT = getPointerTy(MF.getDataLayout());
15758 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
15760 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
15763 if (!Subtarget->is64Bit() ||
15764 Subtarget->isCallingConvWin64(MF.getFunction()->getCallingConv())) {
15765 // vastart just stores the address of the VarArgsFrameIndex slot into the
15766 // memory location argument.
15767 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
15768 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
15769 MachinePointerInfo(SV), false, false, 0);
15773 // gp_offset (0 - 6 * 8)
15774 // fp_offset (48 - 48 + 8 * 16)
15775 // overflow_arg_area (point to parameters coming in memory).
15777 SmallVector<SDValue, 8> MemOps;
15778 SDValue FIN = Op.getOperand(1);
15780 SDValue Store = DAG.getStore(Op.getOperand(0), DL,
15781 DAG.getConstant(FuncInfo->getVarArgsGPOffset(),
15783 FIN, MachinePointerInfo(SV), false, false, 0);
15784 MemOps.push_back(Store);
15787 FIN = DAG.getNode(ISD::ADD, DL, PtrVT, FIN, DAG.getIntPtrConstant(4, DL));
15788 Store = DAG.getStore(Op.getOperand(0), DL,
15789 DAG.getConstant(FuncInfo->getVarArgsFPOffset(), DL,
15791 FIN, MachinePointerInfo(SV, 4), false, false, 0);
15792 MemOps.push_back(Store);
15794 // Store ptr to overflow_arg_area
15795 FIN = DAG.getNode(ISD::ADD, DL, PtrVT, FIN, DAG.getIntPtrConstant(4, DL));
15796 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
15797 Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN,
15798 MachinePointerInfo(SV, 8),
15800 MemOps.push_back(Store);
15802 // Store ptr to reg_save_area.
15803 FIN = DAG.getNode(ISD::ADD, DL, PtrVT, FIN, DAG.getIntPtrConstant(
15804 Subtarget->isTarget64BitLP64() ? 8 : 4, DL));
15805 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(), PtrVT);
15806 Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN, MachinePointerInfo(
15807 SV, Subtarget->isTarget64BitLP64() ? 16 : 12), false, false, 0);
15808 MemOps.push_back(Store);
15809 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps);
15812 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
15813 assert(Subtarget->is64Bit() &&
15814 "LowerVAARG only handles 64-bit va_arg!");
15815 assert(Op.getNode()->getNumOperands() == 4);
15817 MachineFunction &MF = DAG.getMachineFunction();
15818 if (Subtarget->isCallingConvWin64(MF.getFunction()->getCallingConv()))
15819 // The Win64 ABI uses char* instead of a structure.
15820 return DAG.expandVAArg(Op.getNode());
15822 SDValue Chain = Op.getOperand(0);
15823 SDValue SrcPtr = Op.getOperand(1);
15824 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
15825 unsigned Align = Op.getConstantOperandVal(3);
15828 EVT ArgVT = Op.getNode()->getValueType(0);
15829 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
15830 uint32_t ArgSize = DAG.getDataLayout().getTypeAllocSize(ArgTy);
15833 // Decide which area this value should be read from.
15834 // TODO: Implement the AMD64 ABI in its entirety. This simple
15835 // selection mechanism works only for the basic types.
15836 if (ArgVT == MVT::f80) {
15837 llvm_unreachable("va_arg for f80 not yet implemented");
15838 } else if (ArgVT.isFloatingPoint() && ArgSize <= 16 /*bytes*/) {
15839 ArgMode = 2; // Argument passed in XMM register. Use fp_offset.
15840 } else if (ArgVT.isInteger() && ArgSize <= 32 /*bytes*/) {
15841 ArgMode = 1; // Argument passed in GPR64 register(s). Use gp_offset.
15843 llvm_unreachable("Unhandled argument type in LowerVAARG");
15846 if (ArgMode == 2) {
15847 // Sanity Check: Make sure using fp_offset makes sense.
15848 assert(!Subtarget->useSoftFloat() &&
15849 !(MF.getFunction()->hasFnAttribute(Attribute::NoImplicitFloat)) &&
15850 Subtarget->hasSSE1());
15853 // Insert VAARG_64 node into the DAG
15854 // VAARG_64 returns two values: Variable Argument Address, Chain
15855 SDValue InstOps[] = {Chain, SrcPtr, DAG.getConstant(ArgSize, dl, MVT::i32),
15856 DAG.getConstant(ArgMode, dl, MVT::i8),
15857 DAG.getConstant(Align, dl, MVT::i32)};
15858 SDVTList VTs = DAG.getVTList(getPointerTy(DAG.getDataLayout()), MVT::Other);
15859 SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl,
15860 VTs, InstOps, MVT::i64,
15861 MachinePointerInfo(SV),
15863 /*Volatile=*/false,
15865 /*WriteMem=*/true);
15866 Chain = VAARG.getValue(1);
15868 // Load the next argument and return it
15869 return DAG.getLoad(ArgVT, dl,
15872 MachinePointerInfo(),
15873 false, false, false, 0);
15876 static SDValue LowerVACOPY(SDValue Op, const X86Subtarget *Subtarget,
15877 SelectionDAG &DAG) {
15878 // X86-64 va_list is a struct { i32, i32, i8*, i8* }, except on Windows,
15879 // where a va_list is still an i8*.
15880 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
15881 if (Subtarget->isCallingConvWin64(
15882 DAG.getMachineFunction().getFunction()->getCallingConv()))
15883 // Probably a Win64 va_copy.
15884 return DAG.expandVACopy(Op.getNode());
15886 SDValue Chain = Op.getOperand(0);
15887 SDValue DstPtr = Op.getOperand(1);
15888 SDValue SrcPtr = Op.getOperand(2);
15889 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
15890 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
15893 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr,
15894 DAG.getIntPtrConstant(24, DL), 8, /*isVolatile*/false,
15896 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
15899 // getTargetVShiftByConstNode - Handle vector element shifts where the shift
15900 // amount is a constant. Takes immediate version of shift as input.
15901 static SDValue getTargetVShiftByConstNode(unsigned Opc, SDLoc dl, MVT VT,
15902 SDValue SrcOp, uint64_t ShiftAmt,
15903 SelectionDAG &DAG) {
15904 MVT ElementType = VT.getVectorElementType();
15906 // Fold this packed shift into its first operand if ShiftAmt is 0.
15910 // Check for ShiftAmt >= element width
15911 if (ShiftAmt >= ElementType.getSizeInBits()) {
15912 if (Opc == X86ISD::VSRAI)
15913 ShiftAmt = ElementType.getSizeInBits() - 1;
15915 return DAG.getConstant(0, dl, VT);
15918 assert((Opc == X86ISD::VSHLI || Opc == X86ISD::VSRLI || Opc == X86ISD::VSRAI)
15919 && "Unknown target vector shift-by-constant node");
15921 // Fold this packed vector shift into a build vector if SrcOp is a
15922 // vector of Constants or UNDEFs, and SrcOp valuetype is the same as VT.
15923 if (VT == SrcOp.getSimpleValueType() &&
15924 ISD::isBuildVectorOfConstantSDNodes(SrcOp.getNode())) {
15925 SmallVector<SDValue, 8> Elts;
15926 unsigned NumElts = SrcOp->getNumOperands();
15927 ConstantSDNode *ND;
15930 default: llvm_unreachable(nullptr);
15931 case X86ISD::VSHLI:
15932 for (unsigned i=0; i!=NumElts; ++i) {
15933 SDValue CurrentOp = SrcOp->getOperand(i);
15934 if (CurrentOp->getOpcode() == ISD::UNDEF) {
15935 Elts.push_back(CurrentOp);
15938 ND = cast<ConstantSDNode>(CurrentOp);
15939 const APInt &C = ND->getAPIntValue();
15940 Elts.push_back(DAG.getConstant(C.shl(ShiftAmt), dl, ElementType));
15943 case X86ISD::VSRLI:
15944 for (unsigned i=0; i!=NumElts; ++i) {
15945 SDValue CurrentOp = SrcOp->getOperand(i);
15946 if (CurrentOp->getOpcode() == ISD::UNDEF) {
15947 Elts.push_back(CurrentOp);
15950 ND = cast<ConstantSDNode>(CurrentOp);
15951 const APInt &C = ND->getAPIntValue();
15952 Elts.push_back(DAG.getConstant(C.lshr(ShiftAmt), dl, ElementType));
15955 case X86ISD::VSRAI:
15956 for (unsigned i=0; i!=NumElts; ++i) {
15957 SDValue CurrentOp = SrcOp->getOperand(i);
15958 if (CurrentOp->getOpcode() == ISD::UNDEF) {
15959 Elts.push_back(CurrentOp);
15962 ND = cast<ConstantSDNode>(CurrentOp);
15963 const APInt &C = ND->getAPIntValue();
15964 Elts.push_back(DAG.getConstant(C.ashr(ShiftAmt), dl, ElementType));
15969 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
15972 return DAG.getNode(Opc, dl, VT, SrcOp,
15973 DAG.getConstant(ShiftAmt, dl, MVT::i8));
15976 // getTargetVShiftNode - Handle vector element shifts where the shift amount
15977 // may or may not be a constant. Takes immediate version of shift as input.
15978 static SDValue getTargetVShiftNode(unsigned Opc, SDLoc dl, MVT VT,
15979 SDValue SrcOp, SDValue ShAmt,
15980 SelectionDAG &DAG) {
15981 MVT SVT = ShAmt.getSimpleValueType();
15982 assert((SVT == MVT::i32 || SVT == MVT::i64) && "Unexpected value type!");
15984 // Catch shift-by-constant.
15985 if (ConstantSDNode *CShAmt = dyn_cast<ConstantSDNode>(ShAmt))
15986 return getTargetVShiftByConstNode(Opc, dl, VT, SrcOp,
15987 CShAmt->getZExtValue(), DAG);
15989 // Change opcode to non-immediate version
15991 default: llvm_unreachable("Unknown target vector shift node");
15992 case X86ISD::VSHLI: Opc = X86ISD::VSHL; break;
15993 case X86ISD::VSRLI: Opc = X86ISD::VSRL; break;
15994 case X86ISD::VSRAI: Opc = X86ISD::VSRA; break;
15997 const X86Subtarget &Subtarget =
15998 static_cast<const X86Subtarget &>(DAG.getSubtarget());
15999 if (Subtarget.hasSSE41() && ShAmt.getOpcode() == ISD::ZERO_EXTEND &&
16000 ShAmt.getOperand(0).getSimpleValueType() == MVT::i16) {
16001 // Let the shuffle legalizer expand this shift amount node.
16002 SDValue Op0 = ShAmt.getOperand(0);
16003 Op0 = DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(Op0), MVT::v8i16, Op0);
16004 ShAmt = getShuffleVectorZeroOrUndef(Op0, 0, true, &Subtarget, DAG);
16006 // Need to build a vector containing shift amount.
16007 // SSE/AVX packed shifts only use the lower 64-bit of the shift count.
16008 SmallVector<SDValue, 4> ShOps;
16009 ShOps.push_back(ShAmt);
16010 if (SVT == MVT::i32) {
16011 ShOps.push_back(DAG.getConstant(0, dl, SVT));
16012 ShOps.push_back(DAG.getUNDEF(SVT));
16014 ShOps.push_back(DAG.getUNDEF(SVT));
16016 MVT BVT = SVT == MVT::i32 ? MVT::v4i32 : MVT::v2i64;
16017 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, BVT, ShOps);
16020 // The return type has to be a 128-bit type with the same element
16021 // type as the input type.
16022 MVT EltVT = VT.getVectorElementType();
16023 MVT ShVT = MVT::getVectorVT(EltVT, 128/EltVT.getSizeInBits());
16025 ShAmt = DAG.getBitcast(ShVT, ShAmt);
16026 return DAG.getNode(Opc, dl, VT, SrcOp, ShAmt);
16029 /// \brief Return (and \p Op, \p Mask) for compare instructions or
16030 /// (vselect \p Mask, \p Op, \p PreservedSrc) for others along with the
16031 /// necessary casting or extending for \p Mask when lowering masking intrinsics
16032 static SDValue getVectorMaskingNode(SDValue Op, SDValue Mask,
16033 SDValue PreservedSrc,
16034 const X86Subtarget *Subtarget,
16035 SelectionDAG &DAG) {
16036 MVT VT = Op.getSimpleValueType();
16037 MVT MaskVT = MVT::getVectorVT(MVT::i1, VT.getVectorNumElements());
16039 unsigned OpcodeSelect = ISD::VSELECT;
16042 if (isAllOnes(Mask))
16045 if (MaskVT.bitsGT(Mask.getSimpleValueType())) {
16046 MVT newMaskVT = MVT::getIntegerVT(MaskVT.getSizeInBits());
16047 VMask = DAG.getBitcast(MaskVT,
16048 DAG.getNode(ISD::ANY_EXTEND, dl, newMaskVT, Mask));
16050 MVT BitcastVT = MVT::getVectorVT(MVT::i1,
16051 Mask.getSimpleValueType().getSizeInBits());
16052 // In case when MaskVT equals v2i1 or v4i1, low 2 or 4 elements
16053 // are extracted by EXTRACT_SUBVECTOR.
16054 VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
16055 DAG.getBitcast(BitcastVT, Mask),
16056 DAG.getIntPtrConstant(0, dl));
16059 switch (Op.getOpcode()) {
16061 case X86ISD::PCMPEQM:
16062 case X86ISD::PCMPGTM:
16064 case X86ISD::CMPMU:
16065 return DAG.getNode(ISD::AND, dl, VT, Op, VMask);
16066 case X86ISD::VFPCLASS:
16067 return DAG.getNode(ISD::OR, dl, VT, Op, VMask);
16068 case X86ISD::VTRUNC:
16069 case X86ISD::VTRUNCS:
16070 case X86ISD::VTRUNCUS:
16071 // We can't use ISD::VSELECT here because it is not always "Legal"
16072 // for the destination type. For example vpmovqb require only AVX512
16073 // and vselect that can operate on byte element type require BWI
16074 OpcodeSelect = X86ISD::SELECT;
16077 if (PreservedSrc.getOpcode() == ISD::UNDEF)
16078 PreservedSrc = getZeroVector(VT, Subtarget, DAG, dl);
16079 return DAG.getNode(OpcodeSelect, dl, VT, VMask, Op, PreservedSrc);
16082 /// \brief Creates an SDNode for a predicated scalar operation.
16083 /// \returns (X86vselect \p Mask, \p Op, \p PreservedSrc).
16084 /// The mask is coming as MVT::i8 and it should be truncated
16085 /// to MVT::i1 while lowering masking intrinsics.
16086 /// The main difference between ScalarMaskingNode and VectorMaskingNode is using
16087 /// "X86select" instead of "vselect". We just can't create the "vselect" node
16088 /// for a scalar instruction.
16089 static SDValue getScalarMaskingNode(SDValue Op, SDValue Mask,
16090 SDValue PreservedSrc,
16091 const X86Subtarget *Subtarget,
16092 SelectionDAG &DAG) {
16093 if (isAllOnes(Mask))
16096 MVT VT = Op.getSimpleValueType();
16098 // The mask should be of type MVT::i1
16099 SDValue IMask = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, Mask);
16101 if (Op.getOpcode() == X86ISD::FSETCC)
16102 return DAG.getNode(ISD::AND, dl, VT, Op, IMask);
16103 if (Op.getOpcode() == X86ISD::VFPCLASS)
16104 return DAG.getNode(ISD::OR, dl, VT, Op, IMask);
16106 if (PreservedSrc.getOpcode() == ISD::UNDEF)
16107 PreservedSrc = getZeroVector(VT, Subtarget, DAG, dl);
16108 return DAG.getNode(X86ISD::SELECT, dl, VT, IMask, Op, PreservedSrc);
16111 static int getSEHRegistrationNodeSize(const Function *Fn) {
16112 if (!Fn->hasPersonalityFn())
16113 report_fatal_error(
16114 "querying registration node size for function without personality");
16115 // The RegNodeSize is 6 32-bit words for SEH and 4 for C++ EH. See
16116 // WinEHStatePass for the full struct definition.
16117 switch (classifyEHPersonality(Fn->getPersonalityFn())) {
16118 case EHPersonality::MSVC_X86SEH: return 24;
16119 case EHPersonality::MSVC_CXX: return 16;
16122 report_fatal_error("can only recover FP for MSVC EH personality functions");
16125 /// When the 32-bit MSVC runtime transfers control to us, either to an outlined
16126 /// function or when returning to a parent frame after catching an exception, we
16127 /// recover the parent frame pointer by doing arithmetic on the incoming EBP.
16128 /// Here's the math:
16129 /// RegNodeBase = EntryEBP - RegNodeSize
16130 /// ParentFP = RegNodeBase - RegNodeFrameOffset
16131 /// Subtracting RegNodeSize takes us to the offset of the registration node, and
16132 /// subtracting the offset (negative on x86) takes us back to the parent FP.
16133 static SDValue recoverFramePointer(SelectionDAG &DAG, const Function *Fn,
16134 SDValue EntryEBP) {
16135 MachineFunction &MF = DAG.getMachineFunction();
16138 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
16139 MVT PtrVT = TLI.getPointerTy(DAG.getDataLayout());
16141 // It's possible that the parent function no longer has a personality function
16142 // if the exceptional code was optimized away, in which case we just return
16143 // the incoming EBP.
16144 if (!Fn->hasPersonalityFn())
16147 int RegNodeSize = getSEHRegistrationNodeSize(Fn);
16149 // Get an MCSymbol that will ultimately resolve to the frame offset of the EH
16151 MCSymbol *OffsetSym =
16152 MF.getMMI().getContext().getOrCreateParentFrameOffsetSymbol(
16153 GlobalValue::getRealLinkageName(Fn->getName()));
16154 SDValue OffsetSymVal = DAG.getMCSymbol(OffsetSym, PtrVT);
16155 SDValue RegNodeFrameOffset =
16156 DAG.getNode(ISD::LOCAL_RECOVER, dl, PtrVT, OffsetSymVal);
16158 // RegNodeBase = EntryEBP - RegNodeSize
16159 // ParentFP = RegNodeBase - RegNodeFrameOffset
16160 SDValue RegNodeBase = DAG.getNode(ISD::SUB, dl, PtrVT, EntryEBP,
16161 DAG.getConstant(RegNodeSize, dl, PtrVT));
16162 return DAG.getNode(ISD::SUB, dl, PtrVT, RegNodeBase, RegNodeFrameOffset);
16165 static SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
16166 SelectionDAG &DAG) {
16168 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
16169 MVT VT = Op.getSimpleValueType();
16170 const IntrinsicData* IntrData = getIntrinsicWithoutChain(IntNo);
16172 switch(IntrData->Type) {
16173 case INTR_TYPE_1OP:
16174 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1));
16175 case INTR_TYPE_2OP:
16176 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
16178 case INTR_TYPE_2OP_IMM8:
16179 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
16180 DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op.getOperand(2)));
16181 case INTR_TYPE_3OP:
16182 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
16183 Op.getOperand(2), Op.getOperand(3));
16184 case INTR_TYPE_4OP:
16185 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
16186 Op.getOperand(2), Op.getOperand(3), Op.getOperand(4));
16187 case INTR_TYPE_1OP_MASK_RM: {
16188 SDValue Src = Op.getOperand(1);
16189 SDValue PassThru = Op.getOperand(2);
16190 SDValue Mask = Op.getOperand(3);
16191 SDValue RoundingMode;
16192 // We allways add rounding mode to the Node.
16193 // If the rounding mode is not specified, we add the
16194 // "current direction" mode.
16195 if (Op.getNumOperands() == 4)
16197 DAG.getConstant(X86::STATIC_ROUNDING::CUR_DIRECTION, dl, MVT::i32);
16199 RoundingMode = Op.getOperand(4);
16200 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1;
16201 if (IntrWithRoundingModeOpcode != 0)
16202 if (cast<ConstantSDNode>(RoundingMode)->getZExtValue() !=
16203 X86::STATIC_ROUNDING::CUR_DIRECTION)
16204 return getVectorMaskingNode(DAG.getNode(IntrWithRoundingModeOpcode,
16205 dl, Op.getValueType(), Src, RoundingMode),
16206 Mask, PassThru, Subtarget, DAG);
16207 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src,
16209 Mask, PassThru, Subtarget, DAG);
16211 case INTR_TYPE_1OP_MASK: {
16212 SDValue Src = Op.getOperand(1);
16213 SDValue PassThru = Op.getOperand(2);
16214 SDValue Mask = Op.getOperand(3);
16215 // We add rounding mode to the Node when
16216 // - RM Opcode is specified and
16217 // - RM is not "current direction".
16218 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1;
16219 if (IntrWithRoundingModeOpcode != 0) {
16220 SDValue Rnd = Op.getOperand(4);
16221 unsigned Round = cast<ConstantSDNode>(Rnd)->getZExtValue();
16222 if (Round != X86::STATIC_ROUNDING::CUR_DIRECTION) {
16223 return getVectorMaskingNode(DAG.getNode(IntrWithRoundingModeOpcode,
16224 dl, Op.getValueType(),
16226 Mask, PassThru, Subtarget, DAG);
16229 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src),
16230 Mask, PassThru, Subtarget, DAG);
16232 case INTR_TYPE_SCALAR_MASK: {
16233 SDValue Src1 = Op.getOperand(1);
16234 SDValue Src2 = Op.getOperand(2);
16235 SDValue passThru = Op.getOperand(3);
16236 SDValue Mask = Op.getOperand(4);
16237 return getScalarMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src1, Src2),
16238 Mask, passThru, Subtarget, DAG);
16240 case INTR_TYPE_SCALAR_MASK_RM: {
16241 SDValue Src1 = Op.getOperand(1);
16242 SDValue Src2 = Op.getOperand(2);
16243 SDValue Src0 = Op.getOperand(3);
16244 SDValue Mask = Op.getOperand(4);
16245 // There are 2 kinds of intrinsics in this group:
16246 // (1) With suppress-all-exceptions (sae) or rounding mode- 6 operands
16247 // (2) With rounding mode and sae - 7 operands.
16248 if (Op.getNumOperands() == 6) {
16249 SDValue Sae = Op.getOperand(5);
16250 unsigned Opc = IntrData->Opc1 ? IntrData->Opc1 : IntrData->Opc0;
16251 return getScalarMaskingNode(DAG.getNode(Opc, dl, VT, Src1, Src2,
16253 Mask, Src0, Subtarget, DAG);
16255 assert(Op.getNumOperands() == 7 && "Unexpected intrinsic form");
16256 SDValue RoundingMode = Op.getOperand(5);
16257 SDValue Sae = Op.getOperand(6);
16258 return getScalarMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src1, Src2,
16259 RoundingMode, Sae),
16260 Mask, Src0, Subtarget, DAG);
16262 case INTR_TYPE_2OP_MASK:
16263 case INTR_TYPE_2OP_IMM8_MASK: {
16264 SDValue Src1 = Op.getOperand(1);
16265 SDValue Src2 = Op.getOperand(2);
16266 SDValue PassThru = Op.getOperand(3);
16267 SDValue Mask = Op.getOperand(4);
16269 if (IntrData->Type == INTR_TYPE_2OP_IMM8_MASK)
16270 Src2 = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Src2);
16272 // We specify 2 possible opcodes for intrinsics with rounding modes.
16273 // First, we check if the intrinsic may have non-default rounding mode,
16274 // (IntrData->Opc1 != 0), then we check the rounding mode operand.
16275 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1;
16276 if (IntrWithRoundingModeOpcode != 0) {
16277 SDValue Rnd = Op.getOperand(5);
16278 unsigned Round = cast<ConstantSDNode>(Rnd)->getZExtValue();
16279 if (Round != X86::STATIC_ROUNDING::CUR_DIRECTION) {
16280 return getVectorMaskingNode(DAG.getNode(IntrWithRoundingModeOpcode,
16281 dl, Op.getValueType(),
16283 Mask, PassThru, Subtarget, DAG);
16286 // TODO: Intrinsics should have fast-math-flags to propagate.
16287 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT,Src1,Src2),
16288 Mask, PassThru, Subtarget, DAG);
16290 case INTR_TYPE_2OP_MASK_RM: {
16291 SDValue Src1 = Op.getOperand(1);
16292 SDValue Src2 = Op.getOperand(2);
16293 SDValue PassThru = Op.getOperand(3);
16294 SDValue Mask = Op.getOperand(4);
16295 // We specify 2 possible modes for intrinsics, with/without rounding
16297 // First, we check if the intrinsic have rounding mode (6 operands),
16298 // if not, we set rounding mode to "current".
16300 if (Op.getNumOperands() == 6)
16301 Rnd = Op.getOperand(5);
16303 Rnd = DAG.getConstant(X86::STATIC_ROUNDING::CUR_DIRECTION, dl, MVT::i32);
16304 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT,
16306 Mask, PassThru, Subtarget, DAG);
16308 case INTR_TYPE_3OP_SCALAR_MASK_RM: {
16309 SDValue Src1 = Op.getOperand(1);
16310 SDValue Src2 = Op.getOperand(2);
16311 SDValue Src3 = Op.getOperand(3);
16312 SDValue PassThru = Op.getOperand(4);
16313 SDValue Mask = Op.getOperand(5);
16314 SDValue Sae = Op.getOperand(6);
16316 return getScalarMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src1,
16318 Mask, PassThru, Subtarget, DAG);
16320 case INTR_TYPE_3OP_MASK_RM: {
16321 SDValue Src1 = Op.getOperand(1);
16322 SDValue Src2 = Op.getOperand(2);
16323 SDValue Imm = Op.getOperand(3);
16324 SDValue PassThru = Op.getOperand(4);
16325 SDValue Mask = Op.getOperand(5);
16326 // We specify 2 possible modes for intrinsics, with/without rounding
16328 // First, we check if the intrinsic have rounding mode (7 operands),
16329 // if not, we set rounding mode to "current".
16331 if (Op.getNumOperands() == 7)
16332 Rnd = Op.getOperand(6);
16334 Rnd = DAG.getConstant(X86::STATIC_ROUNDING::CUR_DIRECTION, dl, MVT::i32);
16335 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT,
16336 Src1, Src2, Imm, Rnd),
16337 Mask, PassThru, Subtarget, DAG);
16339 case INTR_TYPE_3OP_IMM8_MASK:
16340 case INTR_TYPE_3OP_MASK:
16341 case INSERT_SUBVEC: {
16342 SDValue Src1 = Op.getOperand(1);
16343 SDValue Src2 = Op.getOperand(2);
16344 SDValue Src3 = Op.getOperand(3);
16345 SDValue PassThru = Op.getOperand(4);
16346 SDValue Mask = Op.getOperand(5);
16348 if (IntrData->Type == INTR_TYPE_3OP_IMM8_MASK)
16349 Src3 = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Src3);
16350 else if (IntrData->Type == INSERT_SUBVEC) {
16351 // imm should be adapted to ISD::INSERT_SUBVECTOR behavior
16352 assert(isa<ConstantSDNode>(Src3) && "Expected a ConstantSDNode here!");
16353 unsigned Imm = cast<ConstantSDNode>(Src3)->getZExtValue();
16354 Imm *= Src2.getSimpleValueType().getVectorNumElements();
16355 Src3 = DAG.getTargetConstant(Imm, dl, MVT::i32);
16358 // We specify 2 possible opcodes for intrinsics with rounding modes.
16359 // First, we check if the intrinsic may have non-default rounding mode,
16360 // (IntrData->Opc1 != 0), then we check the rounding mode operand.
16361 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1;
16362 if (IntrWithRoundingModeOpcode != 0) {
16363 SDValue Rnd = Op.getOperand(6);
16364 unsigned Round = cast<ConstantSDNode>(Rnd)->getZExtValue();
16365 if (Round != X86::STATIC_ROUNDING::CUR_DIRECTION) {
16366 return getVectorMaskingNode(DAG.getNode(IntrWithRoundingModeOpcode,
16367 dl, Op.getValueType(),
16368 Src1, Src2, Src3, Rnd),
16369 Mask, PassThru, Subtarget, DAG);
16372 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT,
16374 Mask, PassThru, Subtarget, DAG);
16376 case VPERM_3OP_MASKZ:
16377 case VPERM_3OP_MASK:
16380 case FMA_OP_MASK: {
16381 SDValue Src1 = Op.getOperand(1);
16382 SDValue Src2 = Op.getOperand(2);
16383 SDValue Src3 = Op.getOperand(3);
16384 SDValue Mask = Op.getOperand(4);
16385 MVT VT = Op.getSimpleValueType();
16386 SDValue PassThru = SDValue();
16388 // set PassThru element
16389 if (IntrData->Type == VPERM_3OP_MASKZ || IntrData->Type == FMA_OP_MASKZ)
16390 PassThru = getZeroVector(VT, Subtarget, DAG, dl);
16391 else if (IntrData->Type == FMA_OP_MASK3)
16396 // We specify 2 possible opcodes for intrinsics with rounding modes.
16397 // First, we check if the intrinsic may have non-default rounding mode,
16398 // (IntrData->Opc1 != 0), then we check the rounding mode operand.
16399 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1;
16400 if (IntrWithRoundingModeOpcode != 0) {
16401 SDValue Rnd = Op.getOperand(5);
16402 if (cast<ConstantSDNode>(Rnd)->getZExtValue() !=
16403 X86::STATIC_ROUNDING::CUR_DIRECTION)
16404 return getVectorMaskingNode(DAG.getNode(IntrWithRoundingModeOpcode,
16405 dl, Op.getValueType(),
16406 Src1, Src2, Src3, Rnd),
16407 Mask, PassThru, Subtarget, DAG);
16409 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0,
16410 dl, Op.getValueType(),
16412 Mask, PassThru, Subtarget, DAG);
16414 case TERLOG_OP_MASK:
16415 case TERLOG_OP_MASKZ: {
16416 SDValue Src1 = Op.getOperand(1);
16417 SDValue Src2 = Op.getOperand(2);
16418 SDValue Src3 = Op.getOperand(3);
16419 SDValue Src4 = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op.getOperand(4));
16420 SDValue Mask = Op.getOperand(5);
16421 MVT VT = Op.getSimpleValueType();
16422 SDValue PassThru = Src1;
16423 // Set PassThru element.
16424 if (IntrData->Type == TERLOG_OP_MASKZ)
16425 PassThru = getZeroVector(VT, Subtarget, DAG, dl);
16427 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT,
16428 Src1, Src2, Src3, Src4),
16429 Mask, PassThru, Subtarget, DAG);
16432 // FPclass intrinsics with mask
16433 SDValue Src1 = Op.getOperand(1);
16434 MVT VT = Src1.getSimpleValueType();
16435 MVT MaskVT = MVT::getVectorVT(MVT::i1, VT.getVectorNumElements());
16436 SDValue Imm = Op.getOperand(2);
16437 SDValue Mask = Op.getOperand(3);
16438 MVT BitcastVT = MVT::getVectorVT(MVT::i1,
16439 Mask.getSimpleValueType().getSizeInBits());
16440 SDValue FPclass = DAG.getNode(IntrData->Opc0, dl, MaskVT, Src1, Imm);
16441 SDValue FPclassMask = getVectorMaskingNode(FPclass, Mask,
16442 DAG.getTargetConstant(0, dl, MaskVT),
16444 SDValue Res = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, BitcastVT,
16445 DAG.getUNDEF(BitcastVT), FPclassMask,
16446 DAG.getIntPtrConstant(0, dl));
16447 return DAG.getBitcast(Op.getValueType(), Res);
16450 SDValue Src1 = Op.getOperand(1);
16451 SDValue Imm = Op.getOperand(2);
16452 SDValue Mask = Op.getOperand(3);
16453 SDValue FPclass = DAG.getNode(IntrData->Opc0, dl, MVT::i1, Src1, Imm);
16454 SDValue FPclassMask = getScalarMaskingNode(FPclass, Mask,
16455 DAG.getTargetConstant(0, dl, MVT::i1), Subtarget, DAG);
16456 return DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i8, FPclassMask);
16459 case CMP_MASK_CC: {
16460 // Comparison intrinsics with masks.
16461 // Example of transformation:
16462 // (i8 (int_x86_avx512_mask_pcmpeq_q_128
16463 // (v2i64 %a), (v2i64 %b), (i8 %mask))) ->
16465 // (v8i1 (insert_subvector undef,
16466 // (v2i1 (and (PCMPEQM %a, %b),
16467 // (extract_subvector
16468 // (v8i1 (bitcast %mask)), 0))), 0))))
16469 MVT VT = Op.getOperand(1).getSimpleValueType();
16470 MVT MaskVT = MVT::getVectorVT(MVT::i1, VT.getVectorNumElements());
16471 SDValue Mask = Op.getOperand((IntrData->Type == CMP_MASK_CC) ? 4 : 3);
16472 MVT BitcastVT = MVT::getVectorVT(MVT::i1,
16473 Mask.getSimpleValueType().getSizeInBits());
16475 if (IntrData->Type == CMP_MASK_CC) {
16476 SDValue CC = Op.getOperand(3);
16477 CC = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, CC);
16478 // We specify 2 possible opcodes for intrinsics with rounding modes.
16479 // First, we check if the intrinsic may have non-default rounding mode,
16480 // (IntrData->Opc1 != 0), then we check the rounding mode operand.
16481 if (IntrData->Opc1 != 0) {
16482 SDValue Rnd = Op.getOperand(5);
16483 if (cast<ConstantSDNode>(Rnd)->getZExtValue() !=
16484 X86::STATIC_ROUNDING::CUR_DIRECTION)
16485 Cmp = DAG.getNode(IntrData->Opc1, dl, MaskVT, Op.getOperand(1),
16486 Op.getOperand(2), CC, Rnd);
16488 //default rounding mode
16490 Cmp = DAG.getNode(IntrData->Opc0, dl, MaskVT, Op.getOperand(1),
16491 Op.getOperand(2), CC);
16494 assert(IntrData->Type == CMP_MASK && "Unexpected intrinsic type!");
16495 Cmp = DAG.getNode(IntrData->Opc0, dl, MaskVT, Op.getOperand(1),
16498 SDValue CmpMask = getVectorMaskingNode(Cmp, Mask,
16499 DAG.getTargetConstant(0, dl,
16502 SDValue Res = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, BitcastVT,
16503 DAG.getUNDEF(BitcastVT), CmpMask,
16504 DAG.getIntPtrConstant(0, dl));
16505 return DAG.getBitcast(Op.getValueType(), Res);
16507 case CMP_MASK_SCALAR_CC: {
16508 SDValue Src1 = Op.getOperand(1);
16509 SDValue Src2 = Op.getOperand(2);
16510 SDValue CC = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op.getOperand(3));
16511 SDValue Mask = Op.getOperand(4);
16514 if (IntrData->Opc1 != 0) {
16515 SDValue Rnd = Op.getOperand(5);
16516 if (cast<ConstantSDNode>(Rnd)->getZExtValue() !=
16517 X86::STATIC_ROUNDING::CUR_DIRECTION)
16518 Cmp = DAG.getNode(IntrData->Opc1, dl, MVT::i1, Src1, Src2, CC, Rnd);
16520 //default rounding mode
16522 Cmp = DAG.getNode(IntrData->Opc0, dl, MVT::i1, Src1, Src2, CC);
16524 SDValue CmpMask = getScalarMaskingNode(Cmp, Mask,
16525 DAG.getTargetConstant(0, dl,
16529 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::i8,
16530 DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i8, CmpMask),
16531 DAG.getValueType(MVT::i1));
16533 case COMI: { // Comparison intrinsics
16534 ISD::CondCode CC = (ISD::CondCode)IntrData->Opc1;
16535 SDValue LHS = Op.getOperand(1);
16536 SDValue RHS = Op.getOperand(2);
16537 unsigned X86CC = TranslateX86CC(CC, dl, true, LHS, RHS, DAG);
16538 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!");
16539 SDValue Cond = DAG.getNode(IntrData->Opc0, dl, MVT::i32, LHS, RHS);
16540 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
16541 DAG.getConstant(X86CC, dl, MVT::i8), Cond);
16542 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
16545 return getTargetVShiftNode(IntrData->Opc0, dl, Op.getSimpleValueType(),
16546 Op.getOperand(1), Op.getOperand(2), DAG);
16548 return getVectorMaskingNode(getTargetVShiftNode(IntrData->Opc0, dl,
16549 Op.getSimpleValueType(),
16551 Op.getOperand(2), DAG),
16552 Op.getOperand(4), Op.getOperand(3), Subtarget,
16554 case COMPRESS_EXPAND_IN_REG: {
16555 SDValue Mask = Op.getOperand(3);
16556 SDValue DataToCompress = Op.getOperand(1);
16557 SDValue PassThru = Op.getOperand(2);
16558 if (isAllOnes(Mask)) // return data as is
16559 return Op.getOperand(1);
16561 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT,
16563 Mask, PassThru, Subtarget, DAG);
16566 SDValue Mask = Op.getOperand(1);
16567 MVT MaskVT = MVT::getVectorVT(MVT::i1, Mask.getSimpleValueType().getSizeInBits());
16568 Mask = DAG.getBitcast(MaskVT, Mask);
16569 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Mask);
16572 SDValue Mask = Op.getOperand(3);
16573 MVT VT = Op.getSimpleValueType();
16574 MVT MaskVT = MVT::getVectorVT(MVT::i1, VT.getVectorNumElements());
16575 MVT BitcastVT = MVT::getVectorVT(MVT::i1,
16576 Mask.getSimpleValueType().getSizeInBits());
16578 SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
16579 DAG.getBitcast(BitcastVT, Mask),
16580 DAG.getIntPtrConstant(0, dl));
16581 return DAG.getNode(IntrData->Opc0, dl, VT, VMask, Op.getOperand(1),
16590 default: return SDValue(); // Don't custom lower most intrinsics.
16592 case Intrinsic::x86_avx2_permd:
16593 case Intrinsic::x86_avx2_permps:
16594 // Operands intentionally swapped. Mask is last operand to intrinsic,
16595 // but second operand for node/instruction.
16596 return DAG.getNode(X86ISD::VPERMV, dl, Op.getValueType(),
16597 Op.getOperand(2), Op.getOperand(1));
16599 // ptest and testp intrinsics. The intrinsic these come from are designed to
16600 // return an integer value, not just an instruction so lower it to the ptest
16601 // or testp pattern and a setcc for the result.
16602 case Intrinsic::x86_sse41_ptestz:
16603 case Intrinsic::x86_sse41_ptestc:
16604 case Intrinsic::x86_sse41_ptestnzc:
16605 case Intrinsic::x86_avx_ptestz_256:
16606 case Intrinsic::x86_avx_ptestc_256:
16607 case Intrinsic::x86_avx_ptestnzc_256:
16608 case Intrinsic::x86_avx_vtestz_ps:
16609 case Intrinsic::x86_avx_vtestc_ps:
16610 case Intrinsic::x86_avx_vtestnzc_ps:
16611 case Intrinsic::x86_avx_vtestz_pd:
16612 case Intrinsic::x86_avx_vtestc_pd:
16613 case Intrinsic::x86_avx_vtestnzc_pd:
16614 case Intrinsic::x86_avx_vtestz_ps_256:
16615 case Intrinsic::x86_avx_vtestc_ps_256:
16616 case Intrinsic::x86_avx_vtestnzc_ps_256:
16617 case Intrinsic::x86_avx_vtestz_pd_256:
16618 case Intrinsic::x86_avx_vtestc_pd_256:
16619 case Intrinsic::x86_avx_vtestnzc_pd_256: {
16620 bool IsTestPacked = false;
16623 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
16624 case Intrinsic::x86_avx_vtestz_ps:
16625 case Intrinsic::x86_avx_vtestz_pd:
16626 case Intrinsic::x86_avx_vtestz_ps_256:
16627 case Intrinsic::x86_avx_vtestz_pd_256:
16628 IsTestPacked = true; // Fallthrough
16629 case Intrinsic::x86_sse41_ptestz:
16630 case Intrinsic::x86_avx_ptestz_256:
16632 X86CC = X86::COND_E;
16634 case Intrinsic::x86_avx_vtestc_ps:
16635 case Intrinsic::x86_avx_vtestc_pd:
16636 case Intrinsic::x86_avx_vtestc_ps_256:
16637 case Intrinsic::x86_avx_vtestc_pd_256:
16638 IsTestPacked = true; // Fallthrough
16639 case Intrinsic::x86_sse41_ptestc:
16640 case Intrinsic::x86_avx_ptestc_256:
16642 X86CC = X86::COND_B;
16644 case Intrinsic::x86_avx_vtestnzc_ps:
16645 case Intrinsic::x86_avx_vtestnzc_pd:
16646 case Intrinsic::x86_avx_vtestnzc_ps_256:
16647 case Intrinsic::x86_avx_vtestnzc_pd_256:
16648 IsTestPacked = true; // Fallthrough
16649 case Intrinsic::x86_sse41_ptestnzc:
16650 case Intrinsic::x86_avx_ptestnzc_256:
16652 X86CC = X86::COND_A;
16656 SDValue LHS = Op.getOperand(1);
16657 SDValue RHS = Op.getOperand(2);
16658 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST;
16659 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS);
16660 SDValue CC = DAG.getConstant(X86CC, dl, MVT::i8);
16661 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
16662 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
16664 case Intrinsic::x86_avx512_kortestz_w:
16665 case Intrinsic::x86_avx512_kortestc_w: {
16666 unsigned X86CC = (IntNo == Intrinsic::x86_avx512_kortestz_w)? X86::COND_E: X86::COND_B;
16667 SDValue LHS = DAG.getBitcast(MVT::v16i1, Op.getOperand(1));
16668 SDValue RHS = DAG.getBitcast(MVT::v16i1, Op.getOperand(2));
16669 SDValue CC = DAG.getConstant(X86CC, dl, MVT::i8);
16670 SDValue Test = DAG.getNode(X86ISD::KORTEST, dl, MVT::i32, LHS, RHS);
16671 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i1, CC, Test);
16672 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
16675 case Intrinsic::x86_sse42_pcmpistria128:
16676 case Intrinsic::x86_sse42_pcmpestria128:
16677 case Intrinsic::x86_sse42_pcmpistric128:
16678 case Intrinsic::x86_sse42_pcmpestric128:
16679 case Intrinsic::x86_sse42_pcmpistrio128:
16680 case Intrinsic::x86_sse42_pcmpestrio128:
16681 case Intrinsic::x86_sse42_pcmpistris128:
16682 case Intrinsic::x86_sse42_pcmpestris128:
16683 case Intrinsic::x86_sse42_pcmpistriz128:
16684 case Intrinsic::x86_sse42_pcmpestriz128: {
16688 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
16689 case Intrinsic::x86_sse42_pcmpistria128:
16690 Opcode = X86ISD::PCMPISTRI;
16691 X86CC = X86::COND_A;
16693 case Intrinsic::x86_sse42_pcmpestria128:
16694 Opcode = X86ISD::PCMPESTRI;
16695 X86CC = X86::COND_A;
16697 case Intrinsic::x86_sse42_pcmpistric128:
16698 Opcode = X86ISD::PCMPISTRI;
16699 X86CC = X86::COND_B;
16701 case Intrinsic::x86_sse42_pcmpestric128:
16702 Opcode = X86ISD::PCMPESTRI;
16703 X86CC = X86::COND_B;
16705 case Intrinsic::x86_sse42_pcmpistrio128:
16706 Opcode = X86ISD::PCMPISTRI;
16707 X86CC = X86::COND_O;
16709 case Intrinsic::x86_sse42_pcmpestrio128:
16710 Opcode = X86ISD::PCMPESTRI;
16711 X86CC = X86::COND_O;
16713 case Intrinsic::x86_sse42_pcmpistris128:
16714 Opcode = X86ISD::PCMPISTRI;
16715 X86CC = X86::COND_S;
16717 case Intrinsic::x86_sse42_pcmpestris128:
16718 Opcode = X86ISD::PCMPESTRI;
16719 X86CC = X86::COND_S;
16721 case Intrinsic::x86_sse42_pcmpistriz128:
16722 Opcode = X86ISD::PCMPISTRI;
16723 X86CC = X86::COND_E;
16725 case Intrinsic::x86_sse42_pcmpestriz128:
16726 Opcode = X86ISD::PCMPESTRI;
16727 X86CC = X86::COND_E;
16730 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
16731 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
16732 SDValue PCMP = DAG.getNode(Opcode, dl, VTs, NewOps);
16733 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
16734 DAG.getConstant(X86CC, dl, MVT::i8),
16735 SDValue(PCMP.getNode(), 1));
16736 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
16739 case Intrinsic::x86_sse42_pcmpistri128:
16740 case Intrinsic::x86_sse42_pcmpestri128: {
16742 if (IntNo == Intrinsic::x86_sse42_pcmpistri128)
16743 Opcode = X86ISD::PCMPISTRI;
16745 Opcode = X86ISD::PCMPESTRI;
16747 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
16748 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
16749 return DAG.getNode(Opcode, dl, VTs, NewOps);
16752 case Intrinsic::x86_seh_lsda: {
16753 // Compute the symbol for the LSDA. We know it'll get emitted later.
16754 MachineFunction &MF = DAG.getMachineFunction();
16755 SDValue Op1 = Op.getOperand(1);
16756 auto *Fn = cast<Function>(cast<GlobalAddressSDNode>(Op1)->getGlobal());
16757 MCSymbol *LSDASym = MF.getMMI().getContext().getOrCreateLSDASymbol(
16758 GlobalValue::getRealLinkageName(Fn->getName()));
16760 // Generate a simple absolute symbol reference. This intrinsic is only
16761 // supported on 32-bit Windows, which isn't PIC.
16762 SDValue Result = DAG.getMCSymbol(LSDASym, VT);
16763 return DAG.getNode(X86ISD::Wrapper, dl, VT, Result);
16766 case Intrinsic::x86_seh_recoverfp: {
16767 SDValue FnOp = Op.getOperand(1);
16768 SDValue IncomingFPOp = Op.getOperand(2);
16769 GlobalAddressSDNode *GSD = dyn_cast<GlobalAddressSDNode>(FnOp);
16770 auto *Fn = dyn_cast_or_null<Function>(GSD ? GSD->getGlobal() : nullptr);
16772 report_fatal_error(
16773 "llvm.x86.seh.recoverfp must take a function as the first argument");
16774 return recoverFramePointer(DAG, Fn, IncomingFPOp);
16777 case Intrinsic::localaddress: {
16778 // Returns one of the stack, base, or frame pointer registers, depending on
16779 // which is used to reference local variables.
16780 MachineFunction &MF = DAG.getMachineFunction();
16781 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
16783 if (RegInfo->hasBasePointer(MF))
16784 Reg = RegInfo->getBaseRegister();
16785 else // This function handles the SP or FP case.
16786 Reg = RegInfo->getPtrSizedFrameRegister(MF);
16787 return DAG.getCopyFromReg(DAG.getEntryNode(), dl, Reg, VT);
16792 static SDValue getGatherNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
16793 SDValue Src, SDValue Mask, SDValue Base,
16794 SDValue Index, SDValue ScaleOp, SDValue Chain,
16795 const X86Subtarget * Subtarget) {
16797 auto *C = cast<ConstantSDNode>(ScaleOp);
16798 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), dl, MVT::i8);
16799 MVT MaskVT = MVT::getVectorVT(MVT::i1,
16800 Index.getSimpleValueType().getVectorNumElements());
16802 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
16804 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), dl, MaskVT);
16806 MVT BitcastVT = MVT::getVectorVT(MVT::i1,
16807 Mask.getSimpleValueType().getSizeInBits());
16809 // In case when MaskVT equals v2i1 or v4i1, low 2 or 4 elements
16810 // are extracted by EXTRACT_SUBVECTOR.
16811 MaskInReg = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
16812 DAG.getBitcast(BitcastVT, Mask),
16813 DAG.getIntPtrConstant(0, dl));
16815 SDVTList VTs = DAG.getVTList(Op.getValueType(), MaskVT, MVT::Other);
16816 SDValue Disp = DAG.getTargetConstant(0, dl, MVT::i32);
16817 SDValue Segment = DAG.getRegister(0, MVT::i32);
16818 if (Src.getOpcode() == ISD::UNDEF)
16819 Src = getZeroVector(Op.getValueType(), Subtarget, DAG, dl);
16820 SDValue Ops[] = {Src, MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
16821 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
16822 SDValue RetOps[] = { SDValue(Res, 0), SDValue(Res, 2) };
16823 return DAG.getMergeValues(RetOps, dl);
16826 static SDValue getScatterNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
16827 SDValue Src, SDValue Mask, SDValue Base,
16828 SDValue Index, SDValue ScaleOp, SDValue Chain) {
16830 auto *C = cast<ConstantSDNode>(ScaleOp);
16831 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), dl, MVT::i8);
16832 SDValue Disp = DAG.getTargetConstant(0, dl, MVT::i32);
16833 SDValue Segment = DAG.getRegister(0, MVT::i32);
16834 MVT MaskVT = MVT::getVectorVT(MVT::i1,
16835 Index.getSimpleValueType().getVectorNumElements());
16837 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
16839 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), dl, MaskVT);
16841 MVT BitcastVT = MVT::getVectorVT(MVT::i1,
16842 Mask.getSimpleValueType().getSizeInBits());
16844 // In case when MaskVT equals v2i1 or v4i1, low 2 or 4 elements
16845 // are extracted by EXTRACT_SUBVECTOR.
16846 MaskInReg = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
16847 DAG.getBitcast(BitcastVT, Mask),
16848 DAG.getIntPtrConstant(0, dl));
16850 SDVTList VTs = DAG.getVTList(MaskVT, MVT::Other);
16851 SDValue Ops[] = {Base, Scale, Index, Disp, Segment, MaskInReg, Src, Chain};
16852 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
16853 return SDValue(Res, 1);
16856 static SDValue getPrefetchNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
16857 SDValue Mask, SDValue Base, SDValue Index,
16858 SDValue ScaleOp, SDValue Chain) {
16860 auto *C = cast<ConstantSDNode>(ScaleOp);
16861 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), dl, MVT::i8);
16862 SDValue Disp = DAG.getTargetConstant(0, dl, MVT::i32);
16863 SDValue Segment = DAG.getRegister(0, MVT::i32);
16865 MVT::getVectorVT(MVT::i1, Index.getSimpleValueType().getVectorNumElements());
16867 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
16869 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), dl, MaskVT);
16871 MaskInReg = DAG.getBitcast(MaskVT, Mask);
16872 //SDVTList VTs = DAG.getVTList(MVT::Other);
16873 SDValue Ops[] = {MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
16874 SDNode *Res = DAG.getMachineNode(Opc, dl, MVT::Other, Ops);
16875 return SDValue(Res, 0);
16878 // getReadPerformanceCounter - Handles the lowering of builtin intrinsics that
16879 // read performance monitor counters (x86_rdpmc).
16880 static void getReadPerformanceCounter(SDNode *N, SDLoc DL,
16881 SelectionDAG &DAG, const X86Subtarget *Subtarget,
16882 SmallVectorImpl<SDValue> &Results) {
16883 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
16884 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
16887 // The ECX register is used to select the index of the performance counter
16889 SDValue Chain = DAG.getCopyToReg(N->getOperand(0), DL, X86::ECX,
16891 SDValue rd = DAG.getNode(X86ISD::RDPMC_DAG, DL, Tys, Chain);
16893 // Reads the content of a 64-bit performance counter and returns it in the
16894 // registers EDX:EAX.
16895 if (Subtarget->is64Bit()) {
16896 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
16897 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
16900 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
16901 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
16904 Chain = HI.getValue(1);
16906 if (Subtarget->is64Bit()) {
16907 // The EAX register is loaded with the low-order 32 bits. The EDX register
16908 // is loaded with the supported high-order bits of the counter.
16909 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
16910 DAG.getConstant(32, DL, MVT::i8));
16911 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
16912 Results.push_back(Chain);
16916 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
16917 SDValue Ops[] = { LO, HI };
16918 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
16919 Results.push_back(Pair);
16920 Results.push_back(Chain);
16923 // getReadTimeStampCounter - Handles the lowering of builtin intrinsics that
16924 // read the time stamp counter (x86_rdtsc and x86_rdtscp). This function is
16925 // also used to custom lower READCYCLECOUNTER nodes.
16926 static void getReadTimeStampCounter(SDNode *N, SDLoc DL, unsigned Opcode,
16927 SelectionDAG &DAG, const X86Subtarget *Subtarget,
16928 SmallVectorImpl<SDValue> &Results) {
16929 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
16930 SDValue rd = DAG.getNode(Opcode, DL, Tys, N->getOperand(0));
16933 // The processor's time-stamp counter (a 64-bit MSR) is stored into the
16934 // EDX:EAX registers. EDX is loaded with the high-order 32 bits of the MSR
16935 // and the EAX register is loaded with the low-order 32 bits.
16936 if (Subtarget->is64Bit()) {
16937 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
16938 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
16941 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
16942 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
16945 SDValue Chain = HI.getValue(1);
16947 if (Opcode == X86ISD::RDTSCP_DAG) {
16948 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
16950 // Instruction RDTSCP loads the IA32:TSC_AUX_MSR (address C000_0103H) into
16951 // the ECX register. Add 'ecx' explicitly to the chain.
16952 SDValue ecx = DAG.getCopyFromReg(Chain, DL, X86::ECX, MVT::i32,
16954 // Explicitly store the content of ECX at the location passed in input
16955 // to the 'rdtscp' intrinsic.
16956 Chain = DAG.getStore(ecx.getValue(1), DL, ecx, N->getOperand(2),
16957 MachinePointerInfo(), false, false, 0);
16960 if (Subtarget->is64Bit()) {
16961 // The EDX register is loaded with the high-order 32 bits of the MSR, and
16962 // the EAX register is loaded with the low-order 32 bits.
16963 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
16964 DAG.getConstant(32, DL, MVT::i8));
16965 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
16966 Results.push_back(Chain);
16970 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
16971 SDValue Ops[] = { LO, HI };
16972 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
16973 Results.push_back(Pair);
16974 Results.push_back(Chain);
16977 static SDValue LowerREADCYCLECOUNTER(SDValue Op, const X86Subtarget *Subtarget,
16978 SelectionDAG &DAG) {
16979 SmallVector<SDValue, 2> Results;
16981 getReadTimeStampCounter(Op.getNode(), DL, X86ISD::RDTSC_DAG, DAG, Subtarget,
16983 return DAG.getMergeValues(Results, DL);
16986 static SDValue LowerSEHRESTOREFRAME(SDValue Op, const X86Subtarget *Subtarget,
16987 SelectionDAG &DAG) {
16988 MachineFunction &MF = DAG.getMachineFunction();
16989 const Function *Fn = MF.getFunction();
16991 SDValue Chain = Op.getOperand(0);
16993 assert(Subtarget->getFrameLowering()->hasFP(MF) &&
16994 "using llvm.x86.seh.restoreframe requires a frame pointer");
16996 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
16997 MVT VT = TLI.getPointerTy(DAG.getDataLayout());
16999 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
17000 unsigned FrameReg =
17001 RegInfo->getPtrSizedFrameRegister(DAG.getMachineFunction());
17002 unsigned SPReg = RegInfo->getStackRegister();
17003 unsigned SlotSize = RegInfo->getSlotSize();
17005 // Get incoming EBP.
17006 SDValue IncomingEBP =
17007 DAG.getCopyFromReg(Chain, dl, FrameReg, VT);
17009 // SP is saved in the first field of every registration node, so load
17010 // [EBP-RegNodeSize] into SP.
17011 int RegNodeSize = getSEHRegistrationNodeSize(Fn);
17012 SDValue SPAddr = DAG.getNode(ISD::ADD, dl, VT, IncomingEBP,
17013 DAG.getConstant(-RegNodeSize, dl, VT));
17015 DAG.getLoad(VT, dl, Chain, SPAddr, MachinePointerInfo(), false, false,
17016 false, VT.getScalarSizeInBits() / 8);
17017 Chain = DAG.getCopyToReg(Chain, dl, SPReg, NewSP);
17019 if (!RegInfo->needsStackRealignment(MF)) {
17020 // Adjust EBP to point back to the original frame position.
17021 SDValue NewFP = recoverFramePointer(DAG, Fn, IncomingEBP);
17022 Chain = DAG.getCopyToReg(Chain, dl, FrameReg, NewFP);
17024 assert(RegInfo->hasBasePointer(MF) &&
17025 "functions with Win32 EH must use frame or base pointer register");
17027 // Reload the base pointer (ESI) with the adjusted incoming EBP.
17028 SDValue NewBP = recoverFramePointer(DAG, Fn, IncomingEBP);
17029 Chain = DAG.getCopyToReg(Chain, dl, RegInfo->getBaseRegister(), NewBP);
17031 // Reload the spilled EBP value, now that the stack and base pointers are
17033 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
17034 X86FI->setHasSEHFramePtrSave(true);
17035 int FI = MF.getFrameInfo()->CreateSpillStackObject(SlotSize, SlotSize);
17036 X86FI->setSEHFramePtrSaveIndex(FI);
17037 SDValue NewFP = DAG.getLoad(VT, dl, Chain, DAG.getFrameIndex(FI, VT),
17038 MachinePointerInfo(), false, false, false,
17039 VT.getScalarSizeInBits() / 8);
17040 Chain = DAG.getCopyToReg(NewFP, dl, FrameReg, NewFP);
17046 static SDValue MarkEHRegistrationNode(SDValue Op, SelectionDAG &DAG) {
17047 MachineFunction &MF = DAG.getMachineFunction();
17048 SDValue Chain = Op.getOperand(0);
17049 SDValue RegNode = Op.getOperand(2);
17050 WinEHFuncInfo *EHInfo = MF.getWinEHFuncInfo();
17052 report_fatal_error("EH registrations only live in functions using WinEH");
17054 // Cast the operand to an alloca, and remember the frame index.
17055 auto *FINode = dyn_cast<FrameIndexSDNode>(RegNode);
17057 report_fatal_error("llvm.x86.seh.ehregnode expects a static alloca");
17058 EHInfo->EHRegNodeFrameIndex = FINode->getIndex();
17060 // Return the chain operand without making any DAG nodes.
17064 /// \brief Lower intrinsics for TRUNCATE_TO_MEM case
17065 /// return truncate Store/MaskedStore Node
17066 static SDValue LowerINTRINSIC_TRUNCATE_TO_MEM(const SDValue & Op,
17070 SDValue Mask = Op.getOperand(4);
17071 SDValue DataToTruncate = Op.getOperand(3);
17072 SDValue Addr = Op.getOperand(2);
17073 SDValue Chain = Op.getOperand(0);
17075 MVT VT = DataToTruncate.getSimpleValueType();
17076 MVT SVT = MVT::getVectorVT(ElementType, VT.getVectorNumElements());
17078 if (isAllOnes(Mask)) // return just a truncate store
17079 return DAG.getTruncStore(Chain, dl, DataToTruncate, Addr,
17080 MachinePointerInfo(), SVT, false, false,
17081 SVT.getScalarSizeInBits()/8);
17083 MVT MaskVT = MVT::getVectorVT(MVT::i1, VT.getVectorNumElements());
17084 MVT BitcastVT = MVT::getVectorVT(MVT::i1,
17085 Mask.getSimpleValueType().getSizeInBits());
17086 // In case when MaskVT equals v2i1 or v4i1, low 2 or 4 elements
17087 // are extracted by EXTRACT_SUBVECTOR.
17088 SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
17089 DAG.getBitcast(BitcastVT, Mask),
17090 DAG.getIntPtrConstant(0, dl));
17092 MachineMemOperand *MMO = DAG.getMachineFunction().
17093 getMachineMemOperand(MachinePointerInfo(),
17094 MachineMemOperand::MOStore, SVT.getStoreSize(),
17095 SVT.getScalarSizeInBits()/8);
17097 return DAG.getMaskedStore(Chain, dl, DataToTruncate, Addr,
17098 VMask, SVT, MMO, true);
17101 static SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
17102 SelectionDAG &DAG) {
17103 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
17105 const IntrinsicData* IntrData = getIntrinsicWithChain(IntNo);
17107 if (IntNo == llvm::Intrinsic::x86_seh_restoreframe)
17108 return LowerSEHRESTOREFRAME(Op, Subtarget, DAG);
17109 else if (IntNo == llvm::Intrinsic::x86_seh_ehregnode)
17110 return MarkEHRegistrationNode(Op, DAG);
17115 switch(IntrData->Type) {
17116 default: llvm_unreachable("Unknown Intrinsic Type");
17119 // Emit the node with the right value type.
17120 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Glue, MVT::Other);
17121 SDValue Result = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(0));
17123 // If the value returned by RDRAND/RDSEED was valid (CF=1), return 1.
17124 // Otherwise return the value from Rand, which is always 0, casted to i32.
17125 SDValue Ops[] = { DAG.getZExtOrTrunc(Result, dl, Op->getValueType(1)),
17126 DAG.getConstant(1, dl, Op->getValueType(1)),
17127 DAG.getConstant(X86::COND_B, dl, MVT::i32),
17128 SDValue(Result.getNode(), 1) };
17129 SDValue isValid = DAG.getNode(X86ISD::CMOV, dl,
17130 DAG.getVTList(Op->getValueType(1), MVT::Glue),
17133 // Return { result, isValid, chain }.
17134 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(), Result, isValid,
17135 SDValue(Result.getNode(), 2));
17138 //gather(v1, mask, index, base, scale);
17139 SDValue Chain = Op.getOperand(0);
17140 SDValue Src = Op.getOperand(2);
17141 SDValue Base = Op.getOperand(3);
17142 SDValue Index = Op.getOperand(4);
17143 SDValue Mask = Op.getOperand(5);
17144 SDValue Scale = Op.getOperand(6);
17145 return getGatherNode(IntrData->Opc0, Op, DAG, Src, Mask, Base, Index, Scale,
17149 //scatter(base, mask, index, v1, scale);
17150 SDValue Chain = Op.getOperand(0);
17151 SDValue Base = Op.getOperand(2);
17152 SDValue Mask = Op.getOperand(3);
17153 SDValue Index = Op.getOperand(4);
17154 SDValue Src = Op.getOperand(5);
17155 SDValue Scale = Op.getOperand(6);
17156 return getScatterNode(IntrData->Opc0, Op, DAG, Src, Mask, Base, Index,
17160 SDValue Hint = Op.getOperand(6);
17161 unsigned HintVal = cast<ConstantSDNode>(Hint)->getZExtValue();
17162 assert(HintVal < 2 && "Wrong prefetch hint in intrinsic: should be 0 or 1");
17163 unsigned Opcode = (HintVal ? IntrData->Opc1 : IntrData->Opc0);
17164 SDValue Chain = Op.getOperand(0);
17165 SDValue Mask = Op.getOperand(2);
17166 SDValue Index = Op.getOperand(3);
17167 SDValue Base = Op.getOperand(4);
17168 SDValue Scale = Op.getOperand(5);
17169 return getPrefetchNode(Opcode, Op, DAG, Mask, Base, Index, Scale, Chain);
17171 // Read Time Stamp Counter (RDTSC) and Processor ID (RDTSCP).
17173 SmallVector<SDValue, 2> Results;
17174 getReadTimeStampCounter(Op.getNode(), dl, IntrData->Opc0, DAG, Subtarget,
17176 return DAG.getMergeValues(Results, dl);
17178 // Read Performance Monitoring Counters.
17180 SmallVector<SDValue, 2> Results;
17181 getReadPerformanceCounter(Op.getNode(), dl, DAG, Subtarget, Results);
17182 return DAG.getMergeValues(Results, dl);
17184 // XTEST intrinsics.
17186 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
17187 SDValue InTrans = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(0));
17188 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
17189 DAG.getConstant(X86::COND_NE, dl, MVT::i8),
17191 SDValue Ret = DAG.getNode(ISD::ZERO_EXTEND, dl, Op->getValueType(0), SetCC);
17192 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(),
17193 Ret, SDValue(InTrans.getNode(), 1));
17197 SmallVector<SDValue, 2> Results;
17198 SDVTList CFVTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
17199 SDVTList VTs = DAG.getVTList(Op.getOperand(3)->getValueType(0), MVT::Other);
17200 SDValue GenCF = DAG.getNode(X86ISD::ADD, dl, CFVTs, Op.getOperand(2),
17201 DAG.getConstant(-1, dl, MVT::i8));
17202 SDValue Res = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(3),
17203 Op.getOperand(4), GenCF.getValue(1));
17204 SDValue Store = DAG.getStore(Op.getOperand(0), dl, Res.getValue(0),
17205 Op.getOperand(5), MachinePointerInfo(),
17207 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
17208 DAG.getConstant(X86::COND_B, dl, MVT::i8),
17210 Results.push_back(SetCC);
17211 Results.push_back(Store);
17212 return DAG.getMergeValues(Results, dl);
17214 case COMPRESS_TO_MEM: {
17216 SDValue Mask = Op.getOperand(4);
17217 SDValue DataToCompress = Op.getOperand(3);
17218 SDValue Addr = Op.getOperand(2);
17219 SDValue Chain = Op.getOperand(0);
17221 MVT VT = DataToCompress.getSimpleValueType();
17222 if (isAllOnes(Mask)) // return just a store
17223 return DAG.getStore(Chain, dl, DataToCompress, Addr,
17224 MachinePointerInfo(), false, false,
17225 VT.getScalarSizeInBits()/8);
17227 SDValue Compressed =
17228 getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, DataToCompress),
17229 Mask, DAG.getUNDEF(VT), Subtarget, DAG);
17230 return DAG.getStore(Chain, dl, Compressed, Addr,
17231 MachinePointerInfo(), false, false,
17232 VT.getScalarSizeInBits()/8);
17234 case TRUNCATE_TO_MEM_VI8:
17235 return LowerINTRINSIC_TRUNCATE_TO_MEM(Op, DAG, MVT::i8);
17236 case TRUNCATE_TO_MEM_VI16:
17237 return LowerINTRINSIC_TRUNCATE_TO_MEM(Op, DAG, MVT::i16);
17238 case TRUNCATE_TO_MEM_VI32:
17239 return LowerINTRINSIC_TRUNCATE_TO_MEM(Op, DAG, MVT::i32);
17240 case EXPAND_FROM_MEM: {
17242 SDValue Mask = Op.getOperand(4);
17243 SDValue PassThru = Op.getOperand(3);
17244 SDValue Addr = Op.getOperand(2);
17245 SDValue Chain = Op.getOperand(0);
17246 MVT VT = Op.getSimpleValueType();
17248 if (isAllOnes(Mask)) // return just a load
17249 return DAG.getLoad(VT, dl, Chain, Addr, MachinePointerInfo(), false, false,
17250 false, VT.getScalarSizeInBits()/8);
17252 SDValue DataToExpand = DAG.getLoad(VT, dl, Chain, Addr, MachinePointerInfo(),
17253 false, false, false,
17254 VT.getScalarSizeInBits()/8);
17256 SDValue Results[] = {
17257 getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, DataToExpand),
17258 Mask, PassThru, Subtarget, DAG), Chain};
17259 return DAG.getMergeValues(Results, dl);
17264 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op,
17265 SelectionDAG &DAG) const {
17266 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
17267 MFI->setReturnAddressIsTaken(true);
17269 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
17272 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
17274 EVT PtrVT = getPointerTy(DAG.getDataLayout());
17277 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
17278 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
17279 SDValue Offset = DAG.getConstant(RegInfo->getSlotSize(), dl, PtrVT);
17280 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
17281 DAG.getNode(ISD::ADD, dl, PtrVT,
17282 FrameAddr, Offset),
17283 MachinePointerInfo(), false, false, false, 0);
17286 // Just load the return address.
17287 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
17288 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
17289 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
17292 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
17293 MachineFunction &MF = DAG.getMachineFunction();
17294 MachineFrameInfo *MFI = MF.getFrameInfo();
17295 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
17296 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
17297 EVT VT = Op.getValueType();
17299 MFI->setFrameAddressIsTaken(true);
17301 if (MF.getTarget().getMCAsmInfo()->usesWindowsCFI()) {
17302 // Depth > 0 makes no sense on targets which use Windows unwind codes. It
17303 // is not possible to crawl up the stack without looking at the unwind codes
17305 int FrameAddrIndex = FuncInfo->getFAIndex();
17306 if (!FrameAddrIndex) {
17307 // Set up a frame object for the return address.
17308 unsigned SlotSize = RegInfo->getSlotSize();
17309 FrameAddrIndex = MF.getFrameInfo()->CreateFixedObject(
17310 SlotSize, /*Offset=*/0, /*IsImmutable=*/false);
17311 FuncInfo->setFAIndex(FrameAddrIndex);
17313 return DAG.getFrameIndex(FrameAddrIndex, VT);
17316 unsigned FrameReg =
17317 RegInfo->getPtrSizedFrameRegister(DAG.getMachineFunction());
17318 SDLoc dl(Op); // FIXME probably not meaningful
17319 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
17320 assert(((FrameReg == X86::RBP && VT == MVT::i64) ||
17321 (FrameReg == X86::EBP && VT == MVT::i32)) &&
17322 "Invalid Frame Register!");
17323 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
17325 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
17326 MachinePointerInfo(),
17327 false, false, false, 0);
17331 // FIXME? Maybe this could be a TableGen attribute on some registers and
17332 // this table could be generated automatically from RegInfo.
17333 unsigned X86TargetLowering::getRegisterByName(const char* RegName, EVT VT,
17334 SelectionDAG &DAG) const {
17335 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
17336 const MachineFunction &MF = DAG.getMachineFunction();
17338 unsigned Reg = StringSwitch<unsigned>(RegName)
17339 .Case("esp", X86::ESP)
17340 .Case("rsp", X86::RSP)
17341 .Case("ebp", X86::EBP)
17342 .Case("rbp", X86::RBP)
17345 if (Reg == X86::EBP || Reg == X86::RBP) {
17346 if (!TFI.hasFP(MF))
17347 report_fatal_error("register " + StringRef(RegName) +
17348 " is allocatable: function has no frame pointer");
17351 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
17352 unsigned FrameReg =
17353 RegInfo->getPtrSizedFrameRegister(DAG.getMachineFunction());
17354 assert((FrameReg == X86::EBP || FrameReg == X86::RBP) &&
17355 "Invalid Frame Register!");
17363 report_fatal_error("Invalid register name global variable");
17366 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
17367 SelectionDAG &DAG) const {
17368 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
17369 return DAG.getIntPtrConstant(2 * RegInfo->getSlotSize(), SDLoc(Op));
17372 unsigned X86TargetLowering::getExceptionPointerRegister(
17373 const Constant *PersonalityFn) const {
17374 if (classifyEHPersonality(PersonalityFn) == EHPersonality::CoreCLR)
17375 return Subtarget->isTarget64BitLP64() ? X86::RDX : X86::EDX;
17377 return Subtarget->isTarget64BitLP64() ? X86::RAX : X86::EAX;
17380 unsigned X86TargetLowering::getExceptionSelectorRegister(
17381 const Constant *PersonalityFn) const {
17382 // Funclet personalities don't use selectors (the runtime does the selection).
17383 assert(!isFuncletEHPersonality(classifyEHPersonality(PersonalityFn)));
17384 return Subtarget->isTarget64BitLP64() ? X86::RDX : X86::EDX;
17387 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
17388 SDValue Chain = Op.getOperand(0);
17389 SDValue Offset = Op.getOperand(1);
17390 SDValue Handler = Op.getOperand(2);
17393 EVT PtrVT = getPointerTy(DAG.getDataLayout());
17394 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
17395 unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction());
17396 assert(((FrameReg == X86::RBP && PtrVT == MVT::i64) ||
17397 (FrameReg == X86::EBP && PtrVT == MVT::i32)) &&
17398 "Invalid Frame Register!");
17399 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, PtrVT);
17400 unsigned StoreAddrReg = (PtrVT == MVT::i64) ? X86::RCX : X86::ECX;
17402 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, Frame,
17403 DAG.getIntPtrConstant(RegInfo->getSlotSize(),
17405 StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, StoreAddr, Offset);
17406 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(),
17408 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
17410 return DAG.getNode(X86ISD::EH_RETURN, dl, MVT::Other, Chain,
17411 DAG.getRegister(StoreAddrReg, PtrVT));
17414 SDValue X86TargetLowering::lowerEH_SJLJ_SETJMP(SDValue Op,
17415 SelectionDAG &DAG) const {
17417 return DAG.getNode(X86ISD::EH_SJLJ_SETJMP, DL,
17418 DAG.getVTList(MVT::i32, MVT::Other),
17419 Op.getOperand(0), Op.getOperand(1));
17422 SDValue X86TargetLowering::lowerEH_SJLJ_LONGJMP(SDValue Op,
17423 SelectionDAG &DAG) const {
17425 return DAG.getNode(X86ISD::EH_SJLJ_LONGJMP, DL, MVT::Other,
17426 Op.getOperand(0), Op.getOperand(1));
17429 static SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) {
17430 return Op.getOperand(0);
17433 SDValue X86TargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
17434 SelectionDAG &DAG) const {
17435 SDValue Root = Op.getOperand(0);
17436 SDValue Trmp = Op.getOperand(1); // trampoline
17437 SDValue FPtr = Op.getOperand(2); // nested function
17438 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
17441 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
17442 const TargetRegisterInfo *TRI = Subtarget->getRegisterInfo();
17444 if (Subtarget->is64Bit()) {
17445 SDValue OutChains[6];
17447 // Large code-model.
17448 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode.
17449 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode.
17451 const unsigned char N86R10 = TRI->getEncodingValue(X86::R10) & 0x7;
17452 const unsigned char N86R11 = TRI->getEncodingValue(X86::R11) & 0x7;
17454 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
17456 // Load the pointer to the nested function into R11.
17457 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
17458 SDValue Addr = Trmp;
17459 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, dl, MVT::i16),
17460 Addr, MachinePointerInfo(TrmpAddr),
17463 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17464 DAG.getConstant(2, dl, MVT::i64));
17465 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr,
17466 MachinePointerInfo(TrmpAddr, 2),
17469 // Load the 'nest' parameter value into R10.
17470 // R10 is specified in X86CallingConv.td
17471 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
17472 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17473 DAG.getConstant(10, dl, MVT::i64));
17474 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, dl, MVT::i16),
17475 Addr, MachinePointerInfo(TrmpAddr, 10),
17478 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17479 DAG.getConstant(12, dl, MVT::i64));
17480 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr,
17481 MachinePointerInfo(TrmpAddr, 12),
17484 // Jump to the nested function.
17485 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
17486 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17487 DAG.getConstant(20, dl, MVT::i64));
17488 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, dl, MVT::i16),
17489 Addr, MachinePointerInfo(TrmpAddr, 20),
17492 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
17493 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17494 DAG.getConstant(22, dl, MVT::i64));
17495 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, dl, MVT::i8),
17496 Addr, MachinePointerInfo(TrmpAddr, 22),
17499 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
17501 const Function *Func =
17502 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
17503 CallingConv::ID CC = Func->getCallingConv();
17508 llvm_unreachable("Unsupported calling convention");
17509 case CallingConv::C:
17510 case CallingConv::X86_StdCall: {
17511 // Pass 'nest' parameter in ECX.
17512 // Must be kept in sync with X86CallingConv.td
17513 NestReg = X86::ECX;
17515 // Check that ECX wasn't needed by an 'inreg' parameter.
17516 FunctionType *FTy = Func->getFunctionType();
17517 const AttributeSet &Attrs = Func->getAttributes();
17519 if (!Attrs.isEmpty() && !Func->isVarArg()) {
17520 unsigned InRegCount = 0;
17523 for (FunctionType::param_iterator I = FTy->param_begin(),
17524 E = FTy->param_end(); I != E; ++I, ++Idx)
17525 if (Attrs.hasAttribute(Idx, Attribute::InReg)) {
17526 auto &DL = DAG.getDataLayout();
17527 // FIXME: should only count parameters that are lowered to integers.
17528 InRegCount += (DL.getTypeSizeInBits(*I) + 31) / 32;
17531 if (InRegCount > 2) {
17532 report_fatal_error("Nest register in use - reduce number of inreg"
17538 case CallingConv::X86_FastCall:
17539 case CallingConv::X86_ThisCall:
17540 case CallingConv::Fast:
17541 // Pass 'nest' parameter in EAX.
17542 // Must be kept in sync with X86CallingConv.td
17543 NestReg = X86::EAX;
17547 SDValue OutChains[4];
17548 SDValue Addr, Disp;
17550 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17551 DAG.getConstant(10, dl, MVT::i32));
17552 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
17554 // This is storing the opcode for MOV32ri.
17555 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte.
17556 const unsigned char N86Reg = TRI->getEncodingValue(NestReg) & 0x7;
17557 OutChains[0] = DAG.getStore(Root, dl,
17558 DAG.getConstant(MOV32ri|N86Reg, dl, MVT::i8),
17559 Trmp, MachinePointerInfo(TrmpAddr),
17562 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17563 DAG.getConstant(1, dl, MVT::i32));
17564 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr,
17565 MachinePointerInfo(TrmpAddr, 1),
17568 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode.
17569 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17570 DAG.getConstant(5, dl, MVT::i32));
17571 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, dl, MVT::i8),
17572 Addr, MachinePointerInfo(TrmpAddr, 5),
17575 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17576 DAG.getConstant(6, dl, MVT::i32));
17577 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr,
17578 MachinePointerInfo(TrmpAddr, 6),
17581 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
17585 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op,
17586 SelectionDAG &DAG) const {
17588 The rounding mode is in bits 11:10 of FPSR, and has the following
17590 00 Round to nearest
17595 FLT_ROUNDS, on the other hand, expects the following:
17602 To perform the conversion, we do:
17603 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
17606 MachineFunction &MF = DAG.getMachineFunction();
17607 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
17608 unsigned StackAlignment = TFI.getStackAlignment();
17609 MVT VT = Op.getSimpleValueType();
17612 // Save FP Control Word to stack slot
17613 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false);
17614 SDValue StackSlot =
17615 DAG.getFrameIndex(SSFI, getPointerTy(DAG.getDataLayout()));
17617 MachineMemOperand *MMO =
17618 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(MF, SSFI),
17619 MachineMemOperand::MOStore, 2, 2);
17621 SDValue Ops[] = { DAG.getEntryNode(), StackSlot };
17622 SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL,
17623 DAG.getVTList(MVT::Other),
17624 Ops, MVT::i16, MMO);
17626 // Load FP Control Word from stack slot
17627 SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot,
17628 MachinePointerInfo(), false, false, false, 0);
17630 // Transform as necessary
17632 DAG.getNode(ISD::SRL, DL, MVT::i16,
17633 DAG.getNode(ISD::AND, DL, MVT::i16,
17634 CWD, DAG.getConstant(0x800, DL, MVT::i16)),
17635 DAG.getConstant(11, DL, MVT::i8));
17637 DAG.getNode(ISD::SRL, DL, MVT::i16,
17638 DAG.getNode(ISD::AND, DL, MVT::i16,
17639 CWD, DAG.getConstant(0x400, DL, MVT::i16)),
17640 DAG.getConstant(9, DL, MVT::i8));
17643 DAG.getNode(ISD::AND, DL, MVT::i16,
17644 DAG.getNode(ISD::ADD, DL, MVT::i16,
17645 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2),
17646 DAG.getConstant(1, DL, MVT::i16)),
17647 DAG.getConstant(3, DL, MVT::i16));
17649 return DAG.getNode((VT.getSizeInBits() < 16 ?
17650 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal);
17653 /// \brief Lower a vector CTLZ using native supported vector CTLZ instruction.
17655 // 1. i32/i64 128/256-bit vector (native support require VLX) are expended
17656 // to 512-bit vector.
17657 // 2. i8/i16 vector implemented using dword LZCNT vector instruction
17658 // ( sub(trunc(lzcnt(zext32(x)))) ). In case zext32(x) is illegal,
17659 // split the vector, perform operation on it's Lo a Hi part and
17660 // concatenate the results.
17661 static SDValue LowerVectorCTLZ_AVX512(SDValue Op, SelectionDAG &DAG) {
17663 MVT VT = Op.getSimpleValueType();
17664 MVT EltVT = VT.getVectorElementType();
17665 unsigned NumElems = VT.getVectorNumElements();
17667 if (EltVT == MVT::i64 || EltVT == MVT::i32) {
17668 // Extend to 512 bit vector.
17669 assert((VT.is256BitVector() || VT.is128BitVector()) &&
17670 "Unsupported value type for operation");
17672 MVT NewVT = MVT::getVectorVT(EltVT, 512 / VT.getScalarSizeInBits());
17673 SDValue Vec512 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, NewVT,
17674 DAG.getUNDEF(NewVT),
17676 DAG.getIntPtrConstant(0, dl));
17677 SDValue CtlzNode = DAG.getNode(ISD::CTLZ, dl, NewVT, Vec512);
17679 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, CtlzNode,
17680 DAG.getIntPtrConstant(0, dl));
17683 assert((EltVT == MVT::i8 || EltVT == MVT::i16) &&
17684 "Unsupported element type");
17686 if (16 < NumElems) {
17687 // Split vector, it's Lo and Hi parts will be handled in next iteration.
17689 std::tie(Lo, Hi) = DAG.SplitVector(Op.getOperand(0), dl);
17690 MVT OutVT = MVT::getVectorVT(EltVT, NumElems/2);
17692 Lo = DAG.getNode(Op.getOpcode(), dl, OutVT, Lo);
17693 Hi = DAG.getNode(Op.getOpcode(), dl, OutVT, Hi);
17695 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, Lo, Hi);
17698 MVT NewVT = MVT::getVectorVT(MVT::i32, NumElems);
17700 assert((NewVT.is256BitVector() || NewVT.is512BitVector()) &&
17701 "Unsupported value type for operation");
17703 // Use native supported vector instruction vplzcntd.
17704 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, NewVT, Op.getOperand(0));
17705 SDValue CtlzNode = DAG.getNode(ISD::CTLZ, dl, NewVT, Op);
17706 SDValue TruncNode = DAG.getNode(ISD::TRUNCATE, dl, VT, CtlzNode);
17707 SDValue Delta = DAG.getConstant(32 - EltVT.getSizeInBits(), dl, VT);
17709 return DAG.getNode(ISD::SUB, dl, VT, TruncNode, Delta);
17712 static SDValue LowerCTLZ(SDValue Op, const X86Subtarget *Subtarget,
17713 SelectionDAG &DAG) {
17714 MVT VT = Op.getSimpleValueType();
17716 unsigned NumBits = VT.getSizeInBits();
17719 if (VT.isVector() && Subtarget->hasAVX512())
17720 return LowerVectorCTLZ_AVX512(Op, DAG);
17722 Op = Op.getOperand(0);
17723 if (VT == MVT::i8) {
17724 // Zero extend to i32 since there is not an i8 bsr.
17726 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
17729 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
17730 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
17731 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
17733 // If src is zero (i.e. bsr sets ZF), returns NumBits.
17736 DAG.getConstant(NumBits + NumBits - 1, dl, OpVT),
17737 DAG.getConstant(X86::COND_E, dl, MVT::i8),
17740 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops);
17742 // Finally xor with NumBits-1.
17743 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op,
17744 DAG.getConstant(NumBits - 1, dl, OpVT));
17747 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
17751 static SDValue LowerCTLZ_ZERO_UNDEF(SDValue Op, const X86Subtarget *Subtarget,
17752 SelectionDAG &DAG) {
17753 MVT VT = Op.getSimpleValueType();
17755 unsigned NumBits = VT.getSizeInBits();
17758 if (VT.isVector() && Subtarget->hasAVX512())
17759 return LowerVectorCTLZ_AVX512(Op, DAG);
17761 Op = Op.getOperand(0);
17762 if (VT == MVT::i8) {
17763 // Zero extend to i32 since there is not an i8 bsr.
17765 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
17768 // Issue a bsr (scan bits in reverse).
17769 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
17770 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
17772 // And xor with NumBits-1.
17773 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op,
17774 DAG.getConstant(NumBits - 1, dl, OpVT));
17777 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
17781 static SDValue LowerCTTZ(SDValue Op, SelectionDAG &DAG) {
17782 MVT VT = Op.getSimpleValueType();
17783 unsigned NumBits = VT.getScalarSizeInBits();
17786 if (VT.isVector()) {
17787 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
17789 SDValue N0 = Op.getOperand(0);
17790 SDValue Zero = DAG.getConstant(0, dl, VT);
17792 // lsb(x) = (x & -x)
17793 SDValue LSB = DAG.getNode(ISD::AND, dl, VT, N0,
17794 DAG.getNode(ISD::SUB, dl, VT, Zero, N0));
17796 // cttz_undef(x) = (width - 1) - ctlz(lsb)
17797 if (Op.getOpcode() == ISD::CTTZ_ZERO_UNDEF &&
17798 TLI.isOperationLegal(ISD::CTLZ, VT)) {
17799 SDValue WidthMinusOne = DAG.getConstant(NumBits - 1, dl, VT);
17800 return DAG.getNode(ISD::SUB, dl, VT, WidthMinusOne,
17801 DAG.getNode(ISD::CTLZ, dl, VT, LSB));
17804 // cttz(x) = ctpop(lsb - 1)
17805 SDValue One = DAG.getConstant(1, dl, VT);
17806 return DAG.getNode(ISD::CTPOP, dl, VT,
17807 DAG.getNode(ISD::SUB, dl, VT, LSB, One));
17810 assert(Op.getOpcode() == ISD::CTTZ &&
17811 "Only scalar CTTZ requires custom lowering");
17813 // Issue a bsf (scan bits forward) which also sets EFLAGS.
17814 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
17815 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op.getOperand(0));
17817 // If src is zero (i.e. bsf sets ZF), returns NumBits.
17820 DAG.getConstant(NumBits, dl, VT),
17821 DAG.getConstant(X86::COND_E, dl, MVT::i8),
17824 return DAG.getNode(X86ISD::CMOV, dl, VT, Ops);
17827 // Lower256IntArith - Break a 256-bit integer operation into two new 128-bit
17828 // ones, and then concatenate the result back.
17829 static SDValue Lower256IntArith(SDValue Op, SelectionDAG &DAG) {
17830 MVT VT = Op.getSimpleValueType();
17832 assert(VT.is256BitVector() && VT.isInteger() &&
17833 "Unsupported value type for operation");
17835 unsigned NumElems = VT.getVectorNumElements();
17838 // Extract the LHS vectors
17839 SDValue LHS = Op.getOperand(0);
17840 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
17841 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
17843 // Extract the RHS vectors
17844 SDValue RHS = Op.getOperand(1);
17845 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
17846 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
17848 MVT EltVT = VT.getVectorElementType();
17849 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
17851 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
17852 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1),
17853 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2));
17856 static SDValue LowerADD(SDValue Op, SelectionDAG &DAG) {
17857 if (Op.getValueType() == MVT::i1)
17858 return DAG.getNode(ISD::XOR, SDLoc(Op), Op.getValueType(),
17859 Op.getOperand(0), Op.getOperand(1));
17860 assert(Op.getSimpleValueType().is256BitVector() &&
17861 Op.getSimpleValueType().isInteger() &&
17862 "Only handle AVX 256-bit vector integer operation");
17863 return Lower256IntArith(Op, DAG);
17866 static SDValue LowerSUB(SDValue Op, SelectionDAG &DAG) {
17867 if (Op.getValueType() == MVT::i1)
17868 return DAG.getNode(ISD::XOR, SDLoc(Op), Op.getValueType(),
17869 Op.getOperand(0), Op.getOperand(1));
17870 assert(Op.getSimpleValueType().is256BitVector() &&
17871 Op.getSimpleValueType().isInteger() &&
17872 "Only handle AVX 256-bit vector integer operation");
17873 return Lower256IntArith(Op, DAG);
17876 static SDValue LowerMINMAX(SDValue Op, SelectionDAG &DAG) {
17877 assert(Op.getSimpleValueType().is256BitVector() &&
17878 Op.getSimpleValueType().isInteger() &&
17879 "Only handle AVX 256-bit vector integer operation");
17880 return Lower256IntArith(Op, DAG);
17883 static SDValue LowerMUL(SDValue Op, const X86Subtarget *Subtarget,
17884 SelectionDAG &DAG) {
17886 MVT VT = Op.getSimpleValueType();
17889 return DAG.getNode(ISD::AND, dl, VT, Op.getOperand(0), Op.getOperand(1));
17891 // Decompose 256-bit ops into smaller 128-bit ops.
17892 if (VT.is256BitVector() && !Subtarget->hasInt256())
17893 return Lower256IntArith(Op, DAG);
17895 SDValue A = Op.getOperand(0);
17896 SDValue B = Op.getOperand(1);
17898 // Lower v16i8/v32i8 mul as promotion to v8i16/v16i16 vector
17899 // pairs, multiply and truncate.
17900 if (VT == MVT::v16i8 || VT == MVT::v32i8) {
17901 if (Subtarget->hasInt256()) {
17902 if (VT == MVT::v32i8) {
17903 MVT SubVT = MVT::getVectorVT(MVT::i8, VT.getVectorNumElements() / 2);
17904 SDValue Lo = DAG.getIntPtrConstant(0, dl);
17905 SDValue Hi = DAG.getIntPtrConstant(VT.getVectorNumElements() / 2, dl);
17906 SDValue ALo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, A, Lo);
17907 SDValue BLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, B, Lo);
17908 SDValue AHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, A, Hi);
17909 SDValue BHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, B, Hi);
17910 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
17911 DAG.getNode(ISD::MUL, dl, SubVT, ALo, BLo),
17912 DAG.getNode(ISD::MUL, dl, SubVT, AHi, BHi));
17915 MVT ExVT = MVT::getVectorVT(MVT::i16, VT.getVectorNumElements());
17916 return DAG.getNode(
17917 ISD::TRUNCATE, dl, VT,
17918 DAG.getNode(ISD::MUL, dl, ExVT,
17919 DAG.getNode(ISD::SIGN_EXTEND, dl, ExVT, A),
17920 DAG.getNode(ISD::SIGN_EXTEND, dl, ExVT, B)));
17923 assert(VT == MVT::v16i8 &&
17924 "Pre-AVX2 support only supports v16i8 multiplication");
17925 MVT ExVT = MVT::v8i16;
17927 // Extract the lo parts and sign extend to i16
17929 if (Subtarget->hasSSE41()) {
17930 ALo = DAG.getNode(X86ISD::VSEXT, dl, ExVT, A);
17931 BLo = DAG.getNode(X86ISD::VSEXT, dl, ExVT, B);
17933 const int ShufMask[] = {-1, 0, -1, 1, -1, 2, -1, 3,
17934 -1, 4, -1, 5, -1, 6, -1, 7};
17935 ALo = DAG.getVectorShuffle(VT, dl, A, A, ShufMask);
17936 BLo = DAG.getVectorShuffle(VT, dl, B, B, ShufMask);
17937 ALo = DAG.getBitcast(ExVT, ALo);
17938 BLo = DAG.getBitcast(ExVT, BLo);
17939 ALo = DAG.getNode(ISD::SRA, dl, ExVT, ALo, DAG.getConstant(8, dl, ExVT));
17940 BLo = DAG.getNode(ISD::SRA, dl, ExVT, BLo, DAG.getConstant(8, dl, ExVT));
17943 // Extract the hi parts and sign extend to i16
17945 if (Subtarget->hasSSE41()) {
17946 const int ShufMask[] = {8, 9, 10, 11, 12, 13, 14, 15,
17947 -1, -1, -1, -1, -1, -1, -1, -1};
17948 AHi = DAG.getVectorShuffle(VT, dl, A, A, ShufMask);
17949 BHi = DAG.getVectorShuffle(VT, dl, B, B, ShufMask);
17950 AHi = DAG.getNode(X86ISD::VSEXT, dl, ExVT, AHi);
17951 BHi = DAG.getNode(X86ISD::VSEXT, dl, ExVT, BHi);
17953 const int ShufMask[] = {-1, 8, -1, 9, -1, 10, -1, 11,
17954 -1, 12, -1, 13, -1, 14, -1, 15};
17955 AHi = DAG.getVectorShuffle(VT, dl, A, A, ShufMask);
17956 BHi = DAG.getVectorShuffle(VT, dl, B, B, ShufMask);
17957 AHi = DAG.getBitcast(ExVT, AHi);
17958 BHi = DAG.getBitcast(ExVT, BHi);
17959 AHi = DAG.getNode(ISD::SRA, dl, ExVT, AHi, DAG.getConstant(8, dl, ExVT));
17960 BHi = DAG.getNode(ISD::SRA, dl, ExVT, BHi, DAG.getConstant(8, dl, ExVT));
17963 // Multiply, mask the lower 8bits of the lo/hi results and pack
17964 SDValue RLo = DAG.getNode(ISD::MUL, dl, ExVT, ALo, BLo);
17965 SDValue RHi = DAG.getNode(ISD::MUL, dl, ExVT, AHi, BHi);
17966 RLo = DAG.getNode(ISD::AND, dl, ExVT, RLo, DAG.getConstant(255, dl, ExVT));
17967 RHi = DAG.getNode(ISD::AND, dl, ExVT, RHi, DAG.getConstant(255, dl, ExVT));
17968 return DAG.getNode(X86ISD::PACKUS, dl, VT, RLo, RHi);
17971 // Lower v4i32 mul as 2x shuffle, 2x pmuludq, 2x shuffle.
17972 if (VT == MVT::v4i32) {
17973 assert(Subtarget->hasSSE2() && !Subtarget->hasSSE41() &&
17974 "Should not custom lower when pmuldq is available!");
17976 // Extract the odd parts.
17977 static const int UnpackMask[] = { 1, -1, 3, -1 };
17978 SDValue Aodds = DAG.getVectorShuffle(VT, dl, A, A, UnpackMask);
17979 SDValue Bodds = DAG.getVectorShuffle(VT, dl, B, B, UnpackMask);
17981 // Multiply the even parts.
17982 SDValue Evens = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, A, B);
17983 // Now multiply odd parts.
17984 SDValue Odds = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, Aodds, Bodds);
17986 Evens = DAG.getBitcast(VT, Evens);
17987 Odds = DAG.getBitcast(VT, Odds);
17989 // Merge the two vectors back together with a shuffle. This expands into 2
17991 static const int ShufMask[] = { 0, 4, 2, 6 };
17992 return DAG.getVectorShuffle(VT, dl, Evens, Odds, ShufMask);
17995 assert((VT == MVT::v2i64 || VT == MVT::v4i64 || VT == MVT::v8i64) &&
17996 "Only know how to lower V2I64/V4I64/V8I64 multiply");
17998 // Ahi = psrlqi(a, 32);
17999 // Bhi = psrlqi(b, 32);
18001 // AloBlo = pmuludq(a, b);
18002 // AloBhi = pmuludq(a, Bhi);
18003 // AhiBlo = pmuludq(Ahi, b);
18005 // AloBhi = psllqi(AloBhi, 32);
18006 // AhiBlo = psllqi(AhiBlo, 32);
18007 // return AloBlo + AloBhi + AhiBlo;
18009 SDValue Ahi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, A, 32, DAG);
18010 SDValue Bhi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, B, 32, DAG);
18012 SDValue AhiBlo = Ahi;
18013 SDValue AloBhi = Bhi;
18014 // Bit cast to 32-bit vectors for MULUDQ
18015 MVT MulVT = (VT == MVT::v2i64) ? MVT::v4i32 :
18016 (VT == MVT::v4i64) ? MVT::v8i32 : MVT::v16i32;
18017 A = DAG.getBitcast(MulVT, A);
18018 B = DAG.getBitcast(MulVT, B);
18019 Ahi = DAG.getBitcast(MulVT, Ahi);
18020 Bhi = DAG.getBitcast(MulVT, Bhi);
18022 SDValue AloBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, B);
18023 // After shifting right const values the result may be all-zero.
18024 if (!ISD::isBuildVectorAllZeros(Ahi.getNode())) {
18025 AhiBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, Ahi, B);
18026 AhiBlo = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AhiBlo, 32, DAG);
18028 if (!ISD::isBuildVectorAllZeros(Bhi.getNode())) {
18029 AloBhi = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, Bhi);
18030 AloBhi = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AloBhi, 32, DAG);
18033 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
18034 return DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
18037 SDValue X86TargetLowering::LowerWin64_i128OP(SDValue Op, SelectionDAG &DAG) const {
18038 assert(Subtarget->isTargetWin64() && "Unexpected target");
18039 EVT VT = Op.getValueType();
18040 assert(VT.isInteger() && VT.getSizeInBits() == 128 &&
18041 "Unexpected return type for lowering");
18045 switch (Op->getOpcode()) {
18046 default: llvm_unreachable("Unexpected request for libcall!");
18047 case ISD::SDIV: isSigned = true; LC = RTLIB::SDIV_I128; break;
18048 case ISD::UDIV: isSigned = false; LC = RTLIB::UDIV_I128; break;
18049 case ISD::SREM: isSigned = true; LC = RTLIB::SREM_I128; break;
18050 case ISD::UREM: isSigned = false; LC = RTLIB::UREM_I128; break;
18051 case ISD::SDIVREM: isSigned = true; LC = RTLIB::SDIVREM_I128; break;
18052 case ISD::UDIVREM: isSigned = false; LC = RTLIB::UDIVREM_I128; break;
18056 SDValue InChain = DAG.getEntryNode();
18058 TargetLowering::ArgListTy Args;
18059 TargetLowering::ArgListEntry Entry;
18060 for (unsigned i = 0, e = Op->getNumOperands(); i != e; ++i) {
18061 EVT ArgVT = Op->getOperand(i).getValueType();
18062 assert(ArgVT.isInteger() && ArgVT.getSizeInBits() == 128 &&
18063 "Unexpected argument type for lowering");
18064 SDValue StackPtr = DAG.CreateStackTemporary(ArgVT, 16);
18065 Entry.Node = StackPtr;
18066 InChain = DAG.getStore(InChain, dl, Op->getOperand(i), StackPtr, MachinePointerInfo(),
18068 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
18069 Entry.Ty = PointerType::get(ArgTy,0);
18070 Entry.isSExt = false;
18071 Entry.isZExt = false;
18072 Args.push_back(Entry);
18075 SDValue Callee = DAG.getExternalSymbol(getLibcallName(LC),
18076 getPointerTy(DAG.getDataLayout()));
18078 TargetLowering::CallLoweringInfo CLI(DAG);
18079 CLI.setDebugLoc(dl).setChain(InChain)
18080 .setCallee(getLibcallCallingConv(LC),
18081 static_cast<EVT>(MVT::v2i64).getTypeForEVT(*DAG.getContext()),
18082 Callee, std::move(Args), 0)
18083 .setInRegister().setSExtResult(isSigned).setZExtResult(!isSigned);
18085 std::pair<SDValue, SDValue> CallInfo = LowerCallTo(CLI);
18086 return DAG.getBitcast(VT, CallInfo.first);
18089 static SDValue LowerMUL_LOHI(SDValue Op, const X86Subtarget *Subtarget,
18090 SelectionDAG &DAG) {
18091 SDValue Op0 = Op.getOperand(0), Op1 = Op.getOperand(1);
18092 MVT VT = Op0.getSimpleValueType();
18095 assert((VT == MVT::v4i32 && Subtarget->hasSSE2()) ||
18096 (VT == MVT::v8i32 && Subtarget->hasInt256()));
18098 // PMULxD operations multiply each even value (starting at 0) of LHS with
18099 // the related value of RHS and produce a widen result.
18100 // E.g., PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
18101 // => <2 x i64> <ae|cg>
18103 // In other word, to have all the results, we need to perform two PMULxD:
18104 // 1. one with the even values.
18105 // 2. one with the odd values.
18106 // To achieve #2, with need to place the odd values at an even position.
18108 // Place the odd value at an even position (basically, shift all values 1
18109 // step to the left):
18110 const int Mask[] = {1, -1, 3, -1, 5, -1, 7, -1};
18111 // <a|b|c|d> => <b|undef|d|undef>
18112 SDValue Odd0 = DAG.getVectorShuffle(VT, dl, Op0, Op0, Mask);
18113 // <e|f|g|h> => <f|undef|h|undef>
18114 SDValue Odd1 = DAG.getVectorShuffle(VT, dl, Op1, Op1, Mask);
18116 // Emit two multiplies, one for the lower 2 ints and one for the higher 2
18118 MVT MulVT = VT == MVT::v4i32 ? MVT::v2i64 : MVT::v4i64;
18119 bool IsSigned = Op->getOpcode() == ISD::SMUL_LOHI;
18121 (!IsSigned || !Subtarget->hasSSE41()) ? X86ISD::PMULUDQ : X86ISD::PMULDQ;
18122 // PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
18123 // => <2 x i64> <ae|cg>
18124 SDValue Mul1 = DAG.getBitcast(VT, DAG.getNode(Opcode, dl, MulVT, Op0, Op1));
18125 // PMULUDQ <4 x i32> <b|undef|d|undef>, <4 x i32> <f|undef|h|undef>
18126 // => <2 x i64> <bf|dh>
18127 SDValue Mul2 = DAG.getBitcast(VT, DAG.getNode(Opcode, dl, MulVT, Odd0, Odd1));
18129 // Shuffle it back into the right order.
18130 SDValue Highs, Lows;
18131 if (VT == MVT::v8i32) {
18132 const int HighMask[] = {1, 9, 3, 11, 5, 13, 7, 15};
18133 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
18134 const int LowMask[] = {0, 8, 2, 10, 4, 12, 6, 14};
18135 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
18137 const int HighMask[] = {1, 5, 3, 7};
18138 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
18139 const int LowMask[] = {0, 4, 2, 6};
18140 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
18143 // If we have a signed multiply but no PMULDQ fix up the high parts of a
18144 // unsigned multiply.
18145 if (IsSigned && !Subtarget->hasSSE41()) {
18146 SDValue ShAmt = DAG.getConstant(
18148 DAG.getTargetLoweringInfo().getShiftAmountTy(VT, DAG.getDataLayout()));
18149 SDValue T1 = DAG.getNode(ISD::AND, dl, VT,
18150 DAG.getNode(ISD::SRA, dl, VT, Op0, ShAmt), Op1);
18151 SDValue T2 = DAG.getNode(ISD::AND, dl, VT,
18152 DAG.getNode(ISD::SRA, dl, VT, Op1, ShAmt), Op0);
18154 SDValue Fixup = DAG.getNode(ISD::ADD, dl, VT, T1, T2);
18155 Highs = DAG.getNode(ISD::SUB, dl, VT, Highs, Fixup);
18158 // The first result of MUL_LOHI is actually the low value, followed by the
18160 SDValue Ops[] = {Lows, Highs};
18161 return DAG.getMergeValues(Ops, dl);
18164 // Return true if the required (according to Opcode) shift-imm form is natively
18165 // supported by the Subtarget
18166 static bool SupportedVectorShiftWithImm(MVT VT, const X86Subtarget *Subtarget,
18168 if (VT.getScalarSizeInBits() < 16)
18171 if (VT.is512BitVector() &&
18172 (VT.getScalarSizeInBits() > 16 || Subtarget->hasBWI()))
18175 bool LShift = VT.is128BitVector() ||
18176 (VT.is256BitVector() && Subtarget->hasInt256());
18178 bool AShift = LShift && (Subtarget->hasVLX() ||
18179 (VT != MVT::v2i64 && VT != MVT::v4i64));
18180 return (Opcode == ISD::SRA) ? AShift : LShift;
18183 // The shift amount is a variable, but it is the same for all vector lanes.
18184 // These instructions are defined together with shift-immediate.
18186 bool SupportedVectorShiftWithBaseAmnt(MVT VT, const X86Subtarget *Subtarget,
18188 return SupportedVectorShiftWithImm(VT, Subtarget, Opcode);
18191 // Return true if the required (according to Opcode) variable-shift form is
18192 // natively supported by the Subtarget
18193 static bool SupportedVectorVarShift(MVT VT, const X86Subtarget *Subtarget,
18196 if (!Subtarget->hasInt256() || VT.getScalarSizeInBits() < 16)
18199 // vXi16 supported only on AVX-512, BWI
18200 if (VT.getScalarSizeInBits() == 16 && !Subtarget->hasBWI())
18203 if (VT.is512BitVector() || Subtarget->hasVLX())
18206 bool LShift = VT.is128BitVector() || VT.is256BitVector();
18207 bool AShift = LShift && VT != MVT::v2i64 && VT != MVT::v4i64;
18208 return (Opcode == ISD::SRA) ? AShift : LShift;
18211 static SDValue LowerScalarImmediateShift(SDValue Op, SelectionDAG &DAG,
18212 const X86Subtarget *Subtarget) {
18213 MVT VT = Op.getSimpleValueType();
18215 SDValue R = Op.getOperand(0);
18216 SDValue Amt = Op.getOperand(1);
18218 unsigned X86Opc = (Op.getOpcode() == ISD::SHL) ? X86ISD::VSHLI :
18219 (Op.getOpcode() == ISD::SRL) ? X86ISD::VSRLI : X86ISD::VSRAI;
18221 auto ArithmeticShiftRight64 = [&](uint64_t ShiftAmt) {
18222 assert((VT == MVT::v2i64 || VT == MVT::v4i64) && "Unexpected SRA type");
18223 MVT ExVT = MVT::getVectorVT(MVT::i32, VT.getVectorNumElements() * 2);
18224 SDValue Ex = DAG.getBitcast(ExVT, R);
18226 if (ShiftAmt >= 32) {
18227 // Splat sign to upper i32 dst, and SRA upper i32 src to lower i32.
18229 getTargetVShiftByConstNode(X86ISD::VSRAI, dl, ExVT, Ex, 31, DAG);
18230 SDValue Lower = getTargetVShiftByConstNode(X86ISD::VSRAI, dl, ExVT, Ex,
18231 ShiftAmt - 32, DAG);
18232 if (VT == MVT::v2i64)
18233 Ex = DAG.getVectorShuffle(ExVT, dl, Upper, Lower, {5, 1, 7, 3});
18234 if (VT == MVT::v4i64)
18235 Ex = DAG.getVectorShuffle(ExVT, dl, Upper, Lower,
18236 {9, 1, 11, 3, 13, 5, 15, 7});
18238 // SRA upper i32, SHL whole i64 and select lower i32.
18239 SDValue Upper = getTargetVShiftByConstNode(X86ISD::VSRAI, dl, ExVT, Ex,
18242 getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, R, ShiftAmt, DAG);
18243 Lower = DAG.getBitcast(ExVT, Lower);
18244 if (VT == MVT::v2i64)
18245 Ex = DAG.getVectorShuffle(ExVT, dl, Upper, Lower, {4, 1, 6, 3});
18246 if (VT == MVT::v4i64)
18247 Ex = DAG.getVectorShuffle(ExVT, dl, Upper, Lower,
18248 {8, 1, 10, 3, 12, 5, 14, 7});
18250 return DAG.getBitcast(VT, Ex);
18253 // Optimize shl/srl/sra with constant shift amount.
18254 if (auto *BVAmt = dyn_cast<BuildVectorSDNode>(Amt)) {
18255 if (auto *ShiftConst = BVAmt->getConstantSplatNode()) {
18256 uint64_t ShiftAmt = ShiftConst->getZExtValue();
18258 if (SupportedVectorShiftWithImm(VT, Subtarget, Op.getOpcode()))
18259 return getTargetVShiftByConstNode(X86Opc, dl, VT, R, ShiftAmt, DAG);
18261 // i64 SRA needs to be performed as partial shifts.
18262 if ((VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64)) &&
18263 Op.getOpcode() == ISD::SRA && !Subtarget->hasXOP())
18264 return ArithmeticShiftRight64(ShiftAmt);
18266 if (VT == MVT::v16i8 || (Subtarget->hasInt256() && VT == MVT::v32i8)) {
18267 unsigned NumElts = VT.getVectorNumElements();
18268 MVT ShiftVT = MVT::getVectorVT(MVT::i16, NumElts / 2);
18270 // Simple i8 add case
18271 if (Op.getOpcode() == ISD::SHL && ShiftAmt == 1)
18272 return DAG.getNode(ISD::ADD, dl, VT, R, R);
18274 // ashr(R, 7) === cmp_slt(R, 0)
18275 if (Op.getOpcode() == ISD::SRA && ShiftAmt == 7) {
18276 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
18277 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
18280 // XOP can shift v16i8 directly instead of as shift v8i16 + mask.
18281 if (VT == MVT::v16i8 && Subtarget->hasXOP())
18284 if (Op.getOpcode() == ISD::SHL) {
18285 // Make a large shift.
18286 SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, ShiftVT,
18288 SHL = DAG.getBitcast(VT, SHL);
18289 // Zero out the rightmost bits.
18290 SmallVector<SDValue, 32> V(
18291 NumElts, DAG.getConstant(uint8_t(-1U << ShiftAmt), dl, MVT::i8));
18292 return DAG.getNode(ISD::AND, dl, VT, SHL,
18293 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
18295 if (Op.getOpcode() == ISD::SRL) {
18296 // Make a large shift.
18297 SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, ShiftVT,
18299 SRL = DAG.getBitcast(VT, SRL);
18300 // Zero out the leftmost bits.
18301 SmallVector<SDValue, 32> V(
18302 NumElts, DAG.getConstant(uint8_t(-1U) >> ShiftAmt, dl, MVT::i8));
18303 return DAG.getNode(ISD::AND, dl, VT, SRL,
18304 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
18306 if (Op.getOpcode() == ISD::SRA) {
18307 // ashr(R, Amt) === sub(xor(lshr(R, Amt), Mask), Mask)
18308 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
18309 SmallVector<SDValue, 32> V(NumElts,
18310 DAG.getConstant(128 >> ShiftAmt, dl,
18312 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V);
18313 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
18314 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
18317 llvm_unreachable("Unknown shift opcode.");
18322 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
18323 if (!Subtarget->is64Bit() && !Subtarget->hasXOP() &&
18324 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64))) {
18326 // Peek through any splat that was introduced for i64 shift vectorization.
18327 int SplatIndex = -1;
18328 if (ShuffleVectorSDNode *SVN = dyn_cast<ShuffleVectorSDNode>(Amt.getNode()))
18329 if (SVN->isSplat()) {
18330 SplatIndex = SVN->getSplatIndex();
18331 Amt = Amt.getOperand(0);
18332 assert(SplatIndex < (int)VT.getVectorNumElements() &&
18333 "Splat shuffle referencing second operand");
18336 if (Amt.getOpcode() != ISD::BITCAST ||
18337 Amt.getOperand(0).getOpcode() != ISD::BUILD_VECTOR)
18340 Amt = Amt.getOperand(0);
18341 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
18342 VT.getVectorNumElements();
18343 unsigned RatioInLog2 = Log2_32_Ceil(Ratio);
18344 uint64_t ShiftAmt = 0;
18345 unsigned BaseOp = (SplatIndex < 0 ? 0 : SplatIndex * Ratio);
18346 for (unsigned i = 0; i != Ratio; ++i) {
18347 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Amt.getOperand(i + BaseOp));
18351 ShiftAmt |= C->getZExtValue() << (i * (1 << (6 - RatioInLog2)));
18354 // Check remaining shift amounts (if not a splat).
18355 if (SplatIndex < 0) {
18356 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
18357 uint64_t ShAmt = 0;
18358 for (unsigned j = 0; j != Ratio; ++j) {
18359 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Amt.getOperand(i + j));
18363 ShAmt |= C->getZExtValue() << (j * (1 << (6 - RatioInLog2)));
18365 if (ShAmt != ShiftAmt)
18370 if (SupportedVectorShiftWithImm(VT, Subtarget, Op.getOpcode()))
18371 return getTargetVShiftByConstNode(X86Opc, dl, VT, R, ShiftAmt, DAG);
18373 if (Op.getOpcode() == ISD::SRA)
18374 return ArithmeticShiftRight64(ShiftAmt);
18380 static SDValue LowerScalarVariableShift(SDValue Op, SelectionDAG &DAG,
18381 const X86Subtarget* Subtarget) {
18382 MVT VT = Op.getSimpleValueType();
18384 SDValue R = Op.getOperand(0);
18385 SDValue Amt = Op.getOperand(1);
18387 unsigned X86OpcI = (Op.getOpcode() == ISD::SHL) ? X86ISD::VSHLI :
18388 (Op.getOpcode() == ISD::SRL) ? X86ISD::VSRLI : X86ISD::VSRAI;
18390 unsigned X86OpcV = (Op.getOpcode() == ISD::SHL) ? X86ISD::VSHL :
18391 (Op.getOpcode() == ISD::SRL) ? X86ISD::VSRL : X86ISD::VSRA;
18393 if (SupportedVectorShiftWithBaseAmnt(VT, Subtarget, Op.getOpcode())) {
18395 MVT EltVT = VT.getVectorElementType();
18397 if (BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(Amt)) {
18398 // Check if this build_vector node is doing a splat.
18399 // If so, then set BaseShAmt equal to the splat value.
18400 BaseShAmt = BV->getSplatValue();
18401 if (BaseShAmt && BaseShAmt.getOpcode() == ISD::UNDEF)
18402 BaseShAmt = SDValue();
18404 if (Amt.getOpcode() == ISD::EXTRACT_SUBVECTOR)
18405 Amt = Amt.getOperand(0);
18407 ShuffleVectorSDNode *SVN = dyn_cast<ShuffleVectorSDNode>(Amt);
18408 if (SVN && SVN->isSplat()) {
18409 unsigned SplatIdx = (unsigned)SVN->getSplatIndex();
18410 SDValue InVec = Amt.getOperand(0);
18411 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
18412 assert((SplatIdx < InVec.getSimpleValueType().getVectorNumElements()) &&
18413 "Unexpected shuffle index found!");
18414 BaseShAmt = InVec.getOperand(SplatIdx);
18415 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
18416 if (ConstantSDNode *C =
18417 dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
18418 if (C->getZExtValue() == SplatIdx)
18419 BaseShAmt = InVec.getOperand(1);
18424 // Avoid introducing an extract element from a shuffle.
18425 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InVec,
18426 DAG.getIntPtrConstant(SplatIdx, dl));
18430 if (BaseShAmt.getNode()) {
18431 assert(EltVT.bitsLE(MVT::i64) && "Unexpected element type!");
18432 if (EltVT != MVT::i64 && EltVT.bitsGT(MVT::i32))
18433 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, BaseShAmt);
18434 else if (EltVT.bitsLT(MVT::i32))
18435 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, BaseShAmt);
18437 return getTargetVShiftNode(X86OpcI, dl, VT, R, BaseShAmt, DAG);
18441 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
18442 if (!Subtarget->is64Bit() && VT == MVT::v2i64 &&
18443 Amt.getOpcode() == ISD::BITCAST &&
18444 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
18445 Amt = Amt.getOperand(0);
18446 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
18447 VT.getVectorNumElements();
18448 std::vector<SDValue> Vals(Ratio);
18449 for (unsigned i = 0; i != Ratio; ++i)
18450 Vals[i] = Amt.getOperand(i);
18451 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
18452 for (unsigned j = 0; j != Ratio; ++j)
18453 if (Vals[j] != Amt.getOperand(i + j))
18457 if (SupportedVectorShiftWithBaseAmnt(VT, Subtarget, Op.getOpcode()))
18458 return DAG.getNode(X86OpcV, dl, VT, R, Op.getOperand(1));
18463 static SDValue LowerShift(SDValue Op, const X86Subtarget* Subtarget,
18464 SelectionDAG &DAG) {
18465 MVT VT = Op.getSimpleValueType();
18467 SDValue R = Op.getOperand(0);
18468 SDValue Amt = Op.getOperand(1);
18470 assert(VT.isVector() && "Custom lowering only for vector shifts!");
18471 assert(Subtarget->hasSSE2() && "Only custom lower when we have SSE2!");
18473 if (SDValue V = LowerScalarImmediateShift(Op, DAG, Subtarget))
18476 if (SDValue V = LowerScalarVariableShift(Op, DAG, Subtarget))
18479 if (SupportedVectorVarShift(VT, Subtarget, Op.getOpcode()))
18482 // XOP has 128-bit variable logical/arithmetic shifts.
18483 // +ve/-ve Amt = shift left/right.
18484 if (Subtarget->hasXOP() &&
18485 (VT == MVT::v2i64 || VT == MVT::v4i32 ||
18486 VT == MVT::v8i16 || VT == MVT::v16i8)) {
18487 if (Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SRA) {
18488 SDValue Zero = getZeroVector(VT, Subtarget, DAG, dl);
18489 Amt = DAG.getNode(ISD::SUB, dl, VT, Zero, Amt);
18491 if (Op.getOpcode() == ISD::SHL || Op.getOpcode() == ISD::SRL)
18492 return DAG.getNode(X86ISD::VPSHL, dl, VT, R, Amt);
18493 if (Op.getOpcode() == ISD::SRA)
18494 return DAG.getNode(X86ISD::VPSHA, dl, VT, R, Amt);
18497 // 2i64 vector logical shifts can efficiently avoid scalarization - do the
18498 // shifts per-lane and then shuffle the partial results back together.
18499 if (VT == MVT::v2i64 && Op.getOpcode() != ISD::SRA) {
18500 // Splat the shift amounts so the scalar shifts above will catch it.
18501 SDValue Amt0 = DAG.getVectorShuffle(VT, dl, Amt, Amt, {0, 0});
18502 SDValue Amt1 = DAG.getVectorShuffle(VT, dl, Amt, Amt, {1, 1});
18503 SDValue R0 = DAG.getNode(Op->getOpcode(), dl, VT, R, Amt0);
18504 SDValue R1 = DAG.getNode(Op->getOpcode(), dl, VT, R, Amt1);
18505 return DAG.getVectorShuffle(VT, dl, R0, R1, {0, 3});
18508 // i64 vector arithmetic shift can be emulated with the transform:
18509 // M = lshr(SIGN_BIT, Amt)
18510 // ashr(R, Amt) === sub(xor(lshr(R, Amt), M), M)
18511 if ((VT == MVT::v2i64 || (VT == MVT::v4i64 && Subtarget->hasInt256())) &&
18512 Op.getOpcode() == ISD::SRA) {
18513 SDValue S = DAG.getConstant(APInt::getSignBit(64), dl, VT);
18514 SDValue M = DAG.getNode(ISD::SRL, dl, VT, S, Amt);
18515 R = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
18516 R = DAG.getNode(ISD::XOR, dl, VT, R, M);
18517 R = DAG.getNode(ISD::SUB, dl, VT, R, M);
18521 // If possible, lower this packed shift into a vector multiply instead of
18522 // expanding it into a sequence of scalar shifts.
18523 // Do this only if the vector shift count is a constant build_vector.
18524 if (Op.getOpcode() == ISD::SHL &&
18525 (VT == MVT::v8i16 || VT == MVT::v4i32 ||
18526 (Subtarget->hasInt256() && VT == MVT::v16i16)) &&
18527 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
18528 SmallVector<SDValue, 8> Elts;
18529 MVT SVT = VT.getVectorElementType();
18530 unsigned SVTBits = SVT.getSizeInBits();
18531 APInt One(SVTBits, 1);
18532 unsigned NumElems = VT.getVectorNumElements();
18534 for (unsigned i=0; i !=NumElems; ++i) {
18535 SDValue Op = Amt->getOperand(i);
18536 if (Op->getOpcode() == ISD::UNDEF) {
18537 Elts.push_back(Op);
18541 ConstantSDNode *ND = cast<ConstantSDNode>(Op);
18542 APInt C(SVTBits, ND->getAPIntValue().getZExtValue());
18543 uint64_t ShAmt = C.getZExtValue();
18544 if (ShAmt >= SVTBits) {
18545 Elts.push_back(DAG.getUNDEF(SVT));
18548 Elts.push_back(DAG.getConstant(One.shl(ShAmt), dl, SVT));
18550 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
18551 return DAG.getNode(ISD::MUL, dl, VT, R, BV);
18554 // Lower SHL with variable shift amount.
18555 if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) {
18556 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(23, dl, VT));
18558 Op = DAG.getNode(ISD::ADD, dl, VT, Op,
18559 DAG.getConstant(0x3f800000U, dl, VT));
18560 Op = DAG.getBitcast(MVT::v4f32, Op);
18561 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op);
18562 return DAG.getNode(ISD::MUL, dl, VT, Op, R);
18565 // If possible, lower this shift as a sequence of two shifts by
18566 // constant plus a MOVSS/MOVSD instead of scalarizing it.
18568 // (v4i32 (srl A, (build_vector < X, Y, Y, Y>)))
18570 // Could be rewritten as:
18571 // (v4i32 (MOVSS (srl A, <Y,Y,Y,Y>), (srl A, <X,X,X,X>)))
18573 // The advantage is that the two shifts from the example would be
18574 // lowered as X86ISD::VSRLI nodes. This would be cheaper than scalarizing
18575 // the vector shift into four scalar shifts plus four pairs of vector
18577 if ((VT == MVT::v8i16 || VT == MVT::v4i32) &&
18578 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
18579 unsigned TargetOpcode = X86ISD::MOVSS;
18580 bool CanBeSimplified;
18581 // The splat value for the first packed shift (the 'X' from the example).
18582 SDValue Amt1 = Amt->getOperand(0);
18583 // The splat value for the second packed shift (the 'Y' from the example).
18584 SDValue Amt2 = (VT == MVT::v4i32) ? Amt->getOperand(1) :
18585 Amt->getOperand(2);
18587 // See if it is possible to replace this node with a sequence of
18588 // two shifts followed by a MOVSS/MOVSD
18589 if (VT == MVT::v4i32) {
18590 // Check if it is legal to use a MOVSS.
18591 CanBeSimplified = Amt2 == Amt->getOperand(2) &&
18592 Amt2 == Amt->getOperand(3);
18593 if (!CanBeSimplified) {
18594 // Otherwise, check if we can still simplify this node using a MOVSD.
18595 CanBeSimplified = Amt1 == Amt->getOperand(1) &&
18596 Amt->getOperand(2) == Amt->getOperand(3);
18597 TargetOpcode = X86ISD::MOVSD;
18598 Amt2 = Amt->getOperand(2);
18601 // Do similar checks for the case where the machine value type
18603 CanBeSimplified = Amt1 == Amt->getOperand(1);
18604 for (unsigned i=3; i != 8 && CanBeSimplified; ++i)
18605 CanBeSimplified = Amt2 == Amt->getOperand(i);
18607 if (!CanBeSimplified) {
18608 TargetOpcode = X86ISD::MOVSD;
18609 CanBeSimplified = true;
18610 Amt2 = Amt->getOperand(4);
18611 for (unsigned i=0; i != 4 && CanBeSimplified; ++i)
18612 CanBeSimplified = Amt1 == Amt->getOperand(i);
18613 for (unsigned j=4; j != 8 && CanBeSimplified; ++j)
18614 CanBeSimplified = Amt2 == Amt->getOperand(j);
18618 if (CanBeSimplified && isa<ConstantSDNode>(Amt1) &&
18619 isa<ConstantSDNode>(Amt2)) {
18620 // Replace this node with two shifts followed by a MOVSS/MOVSD.
18621 MVT CastVT = MVT::v4i32;
18623 DAG.getConstant(cast<ConstantSDNode>(Amt1)->getAPIntValue(), dl, VT);
18624 SDValue Shift1 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat1);
18626 DAG.getConstant(cast<ConstantSDNode>(Amt2)->getAPIntValue(), dl, VT);
18627 SDValue Shift2 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat2);
18628 if (TargetOpcode == X86ISD::MOVSD)
18629 CastVT = MVT::v2i64;
18630 SDValue BitCast1 = DAG.getBitcast(CastVT, Shift1);
18631 SDValue BitCast2 = DAG.getBitcast(CastVT, Shift2);
18632 SDValue Result = getTargetShuffleNode(TargetOpcode, dl, CastVT, BitCast2,
18634 return DAG.getBitcast(VT, Result);
18638 // v4i32 Non Uniform Shifts.
18639 // If the shift amount is constant we can shift each lane using the SSE2
18640 // immediate shifts, else we need to zero-extend each lane to the lower i64
18641 // and shift using the SSE2 variable shifts.
18642 // The separate results can then be blended together.
18643 if (VT == MVT::v4i32) {
18644 unsigned Opc = Op.getOpcode();
18645 SDValue Amt0, Amt1, Amt2, Amt3;
18646 if (ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
18647 Amt0 = DAG.getVectorShuffle(VT, dl, Amt, DAG.getUNDEF(VT), {0, 0, 0, 0});
18648 Amt1 = DAG.getVectorShuffle(VT, dl, Amt, DAG.getUNDEF(VT), {1, 1, 1, 1});
18649 Amt2 = DAG.getVectorShuffle(VT, dl, Amt, DAG.getUNDEF(VT), {2, 2, 2, 2});
18650 Amt3 = DAG.getVectorShuffle(VT, dl, Amt, DAG.getUNDEF(VT), {3, 3, 3, 3});
18652 // ISD::SHL is handled above but we include it here for completeness.
18655 llvm_unreachable("Unknown target vector shift node");
18657 Opc = X86ISD::VSHL;
18660 Opc = X86ISD::VSRL;
18663 Opc = X86ISD::VSRA;
18666 // The SSE2 shifts use the lower i64 as the same shift amount for
18667 // all lanes and the upper i64 is ignored. These shuffle masks
18668 // optimally zero-extend each lanes on SSE2/SSE41/AVX targets.
18669 SDValue Z = getZeroVector(VT, Subtarget, DAG, dl);
18670 Amt0 = DAG.getVectorShuffle(VT, dl, Amt, Z, {0, 4, -1, -1});
18671 Amt1 = DAG.getVectorShuffle(VT, dl, Amt, Z, {1, 5, -1, -1});
18672 Amt2 = DAG.getVectorShuffle(VT, dl, Amt, Z, {2, 6, -1, -1});
18673 Amt3 = DAG.getVectorShuffle(VT, dl, Amt, Z, {3, 7, -1, -1});
18676 SDValue R0 = DAG.getNode(Opc, dl, VT, R, Amt0);
18677 SDValue R1 = DAG.getNode(Opc, dl, VT, R, Amt1);
18678 SDValue R2 = DAG.getNode(Opc, dl, VT, R, Amt2);
18679 SDValue R3 = DAG.getNode(Opc, dl, VT, R, Amt3);
18680 SDValue R02 = DAG.getVectorShuffle(VT, dl, R0, R2, {0, -1, 6, -1});
18681 SDValue R13 = DAG.getVectorShuffle(VT, dl, R1, R3, {-1, 1, -1, 7});
18682 return DAG.getVectorShuffle(VT, dl, R02, R13, {0, 5, 2, 7});
18685 if (VT == MVT::v16i8 ||
18686 (VT == MVT::v32i8 && Subtarget->hasInt256() && !Subtarget->hasXOP())) {
18687 MVT ExtVT = MVT::getVectorVT(MVT::i16, VT.getVectorNumElements() / 2);
18688 unsigned ShiftOpcode = Op->getOpcode();
18690 auto SignBitSelect = [&](MVT SelVT, SDValue Sel, SDValue V0, SDValue V1) {
18691 // On SSE41 targets we make use of the fact that VSELECT lowers
18692 // to PBLENDVB which selects bytes based just on the sign bit.
18693 if (Subtarget->hasSSE41()) {
18694 V0 = DAG.getBitcast(VT, V0);
18695 V1 = DAG.getBitcast(VT, V1);
18696 Sel = DAG.getBitcast(VT, Sel);
18697 return DAG.getBitcast(SelVT,
18698 DAG.getNode(ISD::VSELECT, dl, VT, Sel, V0, V1));
18700 // On pre-SSE41 targets we test for the sign bit by comparing to
18701 // zero - a negative value will set all bits of the lanes to true
18702 // and VSELECT uses that in its OR(AND(V0,C),AND(V1,~C)) lowering.
18703 SDValue Z = getZeroVector(SelVT, Subtarget, DAG, dl);
18704 SDValue C = DAG.getNode(X86ISD::PCMPGT, dl, SelVT, Z, Sel);
18705 return DAG.getNode(ISD::VSELECT, dl, SelVT, C, V0, V1);
18708 // Turn 'a' into a mask suitable for VSELECT: a = a << 5;
18709 // We can safely do this using i16 shifts as we're only interested in
18710 // the 3 lower bits of each byte.
18711 Amt = DAG.getBitcast(ExtVT, Amt);
18712 Amt = DAG.getNode(ISD::SHL, dl, ExtVT, Amt, DAG.getConstant(5, dl, ExtVT));
18713 Amt = DAG.getBitcast(VT, Amt);
18715 if (Op->getOpcode() == ISD::SHL || Op->getOpcode() == ISD::SRL) {
18716 // r = VSELECT(r, shift(r, 4), a);
18718 DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(4, dl, VT));
18719 R = SignBitSelect(VT, Amt, M, R);
18722 Amt = DAG.getNode(ISD::ADD, dl, VT, Amt, Amt);
18724 // r = VSELECT(r, shift(r, 2), a);
18725 M = DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(2, dl, VT));
18726 R = SignBitSelect(VT, Amt, M, R);
18729 Amt = DAG.getNode(ISD::ADD, dl, VT, Amt, Amt);
18731 // return VSELECT(r, shift(r, 1), a);
18732 M = DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(1, dl, VT));
18733 R = SignBitSelect(VT, Amt, M, R);
18737 if (Op->getOpcode() == ISD::SRA) {
18738 // For SRA we need to unpack each byte to the higher byte of a i16 vector
18739 // so we can correctly sign extend. We don't care what happens to the
18741 SDValue ALo = DAG.getNode(X86ISD::UNPCKL, dl, VT, DAG.getUNDEF(VT), Amt);
18742 SDValue AHi = DAG.getNode(X86ISD::UNPCKH, dl, VT, DAG.getUNDEF(VT), Amt);
18743 SDValue RLo = DAG.getNode(X86ISD::UNPCKL, dl, VT, DAG.getUNDEF(VT), R);
18744 SDValue RHi = DAG.getNode(X86ISD::UNPCKH, dl, VT, DAG.getUNDEF(VT), R);
18745 ALo = DAG.getBitcast(ExtVT, ALo);
18746 AHi = DAG.getBitcast(ExtVT, AHi);
18747 RLo = DAG.getBitcast(ExtVT, RLo);
18748 RHi = DAG.getBitcast(ExtVT, RHi);
18750 // r = VSELECT(r, shift(r, 4), a);
18751 SDValue MLo = DAG.getNode(ShiftOpcode, dl, ExtVT, RLo,
18752 DAG.getConstant(4, dl, ExtVT));
18753 SDValue MHi = DAG.getNode(ShiftOpcode, dl, ExtVT, RHi,
18754 DAG.getConstant(4, dl, ExtVT));
18755 RLo = SignBitSelect(ExtVT, ALo, MLo, RLo);
18756 RHi = SignBitSelect(ExtVT, AHi, MHi, RHi);
18759 ALo = DAG.getNode(ISD::ADD, dl, ExtVT, ALo, ALo);
18760 AHi = DAG.getNode(ISD::ADD, dl, ExtVT, AHi, AHi);
18762 // r = VSELECT(r, shift(r, 2), a);
18763 MLo = DAG.getNode(ShiftOpcode, dl, ExtVT, RLo,
18764 DAG.getConstant(2, dl, ExtVT));
18765 MHi = DAG.getNode(ShiftOpcode, dl, ExtVT, RHi,
18766 DAG.getConstant(2, dl, ExtVT));
18767 RLo = SignBitSelect(ExtVT, ALo, MLo, RLo);
18768 RHi = SignBitSelect(ExtVT, AHi, MHi, RHi);
18771 ALo = DAG.getNode(ISD::ADD, dl, ExtVT, ALo, ALo);
18772 AHi = DAG.getNode(ISD::ADD, dl, ExtVT, AHi, AHi);
18774 // r = VSELECT(r, shift(r, 1), a);
18775 MLo = DAG.getNode(ShiftOpcode, dl, ExtVT, RLo,
18776 DAG.getConstant(1, dl, ExtVT));
18777 MHi = DAG.getNode(ShiftOpcode, dl, ExtVT, RHi,
18778 DAG.getConstant(1, dl, ExtVT));
18779 RLo = SignBitSelect(ExtVT, ALo, MLo, RLo);
18780 RHi = SignBitSelect(ExtVT, AHi, MHi, RHi);
18782 // Logical shift the result back to the lower byte, leaving a zero upper
18784 // meaning that we can safely pack with PACKUSWB.
18786 DAG.getNode(ISD::SRL, dl, ExtVT, RLo, DAG.getConstant(8, dl, ExtVT));
18788 DAG.getNode(ISD::SRL, dl, ExtVT, RHi, DAG.getConstant(8, dl, ExtVT));
18789 return DAG.getNode(X86ISD::PACKUS, dl, VT, RLo, RHi);
18793 // It's worth extending once and using the v8i32 shifts for 16-bit types, but
18794 // the extra overheads to get from v16i8 to v8i32 make the existing SSE
18795 // solution better.
18796 if (Subtarget->hasInt256() && VT == MVT::v8i16) {
18797 MVT ExtVT = MVT::v8i32;
18799 Op.getOpcode() == ISD::SRA ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
18800 R = DAG.getNode(ExtOpc, dl, ExtVT, R);
18801 Amt = DAG.getNode(ISD::ANY_EXTEND, dl, ExtVT, Amt);
18802 return DAG.getNode(ISD::TRUNCATE, dl, VT,
18803 DAG.getNode(Op.getOpcode(), dl, ExtVT, R, Amt));
18806 if (Subtarget->hasInt256() && !Subtarget->hasXOP() && VT == MVT::v16i16) {
18807 MVT ExtVT = MVT::v8i32;
18808 SDValue Z = getZeroVector(VT, Subtarget, DAG, dl);
18809 SDValue ALo = DAG.getNode(X86ISD::UNPCKL, dl, VT, Amt, Z);
18810 SDValue AHi = DAG.getNode(X86ISD::UNPCKH, dl, VT, Amt, Z);
18811 SDValue RLo = DAG.getNode(X86ISD::UNPCKL, dl, VT, R, R);
18812 SDValue RHi = DAG.getNode(X86ISD::UNPCKH, dl, VT, R, R);
18813 ALo = DAG.getBitcast(ExtVT, ALo);
18814 AHi = DAG.getBitcast(ExtVT, AHi);
18815 RLo = DAG.getBitcast(ExtVT, RLo);
18816 RHi = DAG.getBitcast(ExtVT, RHi);
18817 SDValue Lo = DAG.getNode(Op.getOpcode(), dl, ExtVT, RLo, ALo);
18818 SDValue Hi = DAG.getNode(Op.getOpcode(), dl, ExtVT, RHi, AHi);
18819 Lo = DAG.getNode(ISD::SRL, dl, ExtVT, Lo, DAG.getConstant(16, dl, ExtVT));
18820 Hi = DAG.getNode(ISD::SRL, dl, ExtVT, Hi, DAG.getConstant(16, dl, ExtVT));
18821 return DAG.getNode(X86ISD::PACKUS, dl, VT, Lo, Hi);
18824 if (VT == MVT::v8i16) {
18825 unsigned ShiftOpcode = Op->getOpcode();
18827 auto SignBitSelect = [&](SDValue Sel, SDValue V0, SDValue V1) {
18828 // On SSE41 targets we make use of the fact that VSELECT lowers
18829 // to PBLENDVB which selects bytes based just on the sign bit.
18830 if (Subtarget->hasSSE41()) {
18831 MVT ExtVT = MVT::getVectorVT(MVT::i8, VT.getVectorNumElements() * 2);
18832 V0 = DAG.getBitcast(ExtVT, V0);
18833 V1 = DAG.getBitcast(ExtVT, V1);
18834 Sel = DAG.getBitcast(ExtVT, Sel);
18835 return DAG.getBitcast(
18836 VT, DAG.getNode(ISD::VSELECT, dl, ExtVT, Sel, V0, V1));
18838 // On pre-SSE41 targets we splat the sign bit - a negative value will
18839 // set all bits of the lanes to true and VSELECT uses that in
18840 // its OR(AND(V0,C),AND(V1,~C)) lowering.
18842 DAG.getNode(ISD::SRA, dl, VT, Sel, DAG.getConstant(15, dl, VT));
18843 return DAG.getNode(ISD::VSELECT, dl, VT, C, V0, V1);
18846 // Turn 'a' into a mask suitable for VSELECT: a = a << 12;
18847 if (Subtarget->hasSSE41()) {
18848 // On SSE41 targets we need to replicate the shift mask in both
18849 // bytes for PBLENDVB.
18852 DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(4, dl, VT)),
18853 DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(12, dl, VT)));
18855 Amt = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(12, dl, VT));
18858 // r = VSELECT(r, shift(r, 8), a);
18859 SDValue M = DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(8, dl, VT));
18860 R = SignBitSelect(Amt, M, R);
18863 Amt = DAG.getNode(ISD::ADD, dl, VT, Amt, Amt);
18865 // r = VSELECT(r, shift(r, 4), a);
18866 M = DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(4, dl, VT));
18867 R = SignBitSelect(Amt, M, R);
18870 Amt = DAG.getNode(ISD::ADD, dl, VT, Amt, Amt);
18872 // r = VSELECT(r, shift(r, 2), a);
18873 M = DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(2, dl, VT));
18874 R = SignBitSelect(Amt, M, R);
18877 Amt = DAG.getNode(ISD::ADD, dl, VT, Amt, Amt);
18879 // return VSELECT(r, shift(r, 1), a);
18880 M = DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(1, dl, VT));
18881 R = SignBitSelect(Amt, M, R);
18885 // Decompose 256-bit shifts into smaller 128-bit shifts.
18886 if (VT.is256BitVector()) {
18887 unsigned NumElems = VT.getVectorNumElements();
18888 MVT EltVT = VT.getVectorElementType();
18889 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
18891 // Extract the two vectors
18892 SDValue V1 = Extract128BitVector(R, 0, DAG, dl);
18893 SDValue V2 = Extract128BitVector(R, NumElems/2, DAG, dl);
18895 // Recreate the shift amount vectors
18896 SDValue Amt1, Amt2;
18897 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
18898 // Constant shift amount
18899 SmallVector<SDValue, 8> Ops(Amt->op_begin(), Amt->op_begin() + NumElems);
18900 ArrayRef<SDValue> Amt1Csts = makeArrayRef(Ops).slice(0, NumElems / 2);
18901 ArrayRef<SDValue> Amt2Csts = makeArrayRef(Ops).slice(NumElems / 2);
18903 Amt1 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt1Csts);
18904 Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt2Csts);
18906 // Variable shift amount
18907 Amt1 = Extract128BitVector(Amt, 0, DAG, dl);
18908 Amt2 = Extract128BitVector(Amt, NumElems/2, DAG, dl);
18911 // Issue new vector shifts for the smaller types
18912 V1 = DAG.getNode(Op.getOpcode(), dl, NewVT, V1, Amt1);
18913 V2 = DAG.getNode(Op.getOpcode(), dl, NewVT, V2, Amt2);
18915 // Concatenate the result back
18916 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, V1, V2);
18922 static SDValue LowerRotate(SDValue Op, const X86Subtarget *Subtarget,
18923 SelectionDAG &DAG) {
18924 MVT VT = Op.getSimpleValueType();
18926 SDValue R = Op.getOperand(0);
18927 SDValue Amt = Op.getOperand(1);
18929 assert(VT.isVector() && "Custom lowering only for vector rotates!");
18930 assert(Subtarget->hasXOP() && "XOP support required for vector rotates!");
18931 assert((Op.getOpcode() == ISD::ROTL) && "Only ROTL supported");
18933 // XOP has 128-bit vector variable + immediate rotates.
18934 // +ve/-ve Amt = rotate left/right.
18936 // Split 256-bit integers.
18937 if (VT.is256BitVector())
18938 return Lower256IntArith(Op, DAG);
18940 assert(VT.is128BitVector() && "Only rotate 128-bit vectors!");
18942 // Attempt to rotate by immediate.
18943 if (auto *BVAmt = dyn_cast<BuildVectorSDNode>(Amt)) {
18944 if (auto *RotateConst = BVAmt->getConstantSplatNode()) {
18945 uint64_t RotateAmt = RotateConst->getAPIntValue().getZExtValue();
18946 assert(RotateAmt < VT.getScalarSizeInBits() && "Rotation out of range");
18947 return DAG.getNode(X86ISD::VPROTI, DL, VT, R,
18948 DAG.getConstant(RotateAmt, DL, MVT::i8));
18952 // Use general rotate by variable (per-element).
18953 return DAG.getNode(X86ISD::VPROT, DL, VT, R, Amt);
18956 static SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) {
18957 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
18958 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
18959 // looks for this combo and may remove the "setcc" instruction if the "setcc"
18960 // has only one use.
18961 SDNode *N = Op.getNode();
18962 SDValue LHS = N->getOperand(0);
18963 SDValue RHS = N->getOperand(1);
18964 unsigned BaseOp = 0;
18967 switch (Op.getOpcode()) {
18968 default: llvm_unreachable("Unknown ovf instruction!");
18970 // A subtract of one will be selected as a INC. Note that INC doesn't
18971 // set CF, so we can't do this for UADDO.
18972 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
18974 BaseOp = X86ISD::INC;
18975 Cond = X86::COND_O;
18978 BaseOp = X86ISD::ADD;
18979 Cond = X86::COND_O;
18982 BaseOp = X86ISD::ADD;
18983 Cond = X86::COND_B;
18986 // A subtract of one will be selected as a DEC. Note that DEC doesn't
18987 // set CF, so we can't do this for USUBO.
18988 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
18990 BaseOp = X86ISD::DEC;
18991 Cond = X86::COND_O;
18994 BaseOp = X86ISD::SUB;
18995 Cond = X86::COND_O;
18998 BaseOp = X86ISD::SUB;
18999 Cond = X86::COND_B;
19002 BaseOp = N->getValueType(0) == MVT::i8 ? X86ISD::SMUL8 : X86ISD::SMUL;
19003 Cond = X86::COND_O;
19005 case ISD::UMULO: { // i64, i8 = umulo lhs, rhs --> i64, i64, i32 umul lhs,rhs
19006 if (N->getValueType(0) == MVT::i8) {
19007 BaseOp = X86ISD::UMUL8;
19008 Cond = X86::COND_O;
19011 SDVTList VTs = DAG.getVTList(N->getValueType(0), N->getValueType(0),
19013 SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS);
19016 DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
19017 DAG.getConstant(X86::COND_O, DL, MVT::i32),
19018 SDValue(Sum.getNode(), 2));
19020 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
19024 // Also sets EFLAGS.
19025 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
19026 SDValue Sum = DAG.getNode(BaseOp, DL, VTs, LHS, RHS);
19029 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1),
19030 DAG.getConstant(Cond, DL, MVT::i32),
19031 SDValue(Sum.getNode(), 1));
19033 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
19036 /// Returns true if the operand type is exactly twice the native width, and
19037 /// the corresponding cmpxchg8b or cmpxchg16b instruction is available.
19038 /// Used to know whether to use cmpxchg8/16b when expanding atomic operations
19039 /// (otherwise we leave them alone to become __sync_fetch_and_... calls).
19040 bool X86TargetLowering::needsCmpXchgNb(Type *MemType) const {
19041 unsigned OpWidth = MemType->getPrimitiveSizeInBits();
19044 return !Subtarget->is64Bit(); // FIXME this should be Subtarget.hasCmpxchg8b
19045 else if (OpWidth == 128)
19046 return Subtarget->hasCmpxchg16b();
19051 bool X86TargetLowering::shouldExpandAtomicStoreInIR(StoreInst *SI) const {
19052 return needsCmpXchgNb(SI->getValueOperand()->getType());
19055 // Note: this turns large loads into lock cmpxchg8b/16b.
19056 // FIXME: On 32 bits x86, fild/movq might be faster than lock cmpxchg8b.
19057 TargetLowering::AtomicExpansionKind
19058 X86TargetLowering::shouldExpandAtomicLoadInIR(LoadInst *LI) const {
19059 auto PTy = cast<PointerType>(LI->getPointerOperand()->getType());
19060 return needsCmpXchgNb(PTy->getElementType()) ? AtomicExpansionKind::CmpXChg
19061 : AtomicExpansionKind::None;
19064 TargetLowering::AtomicExpansionKind
19065 X86TargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const {
19066 unsigned NativeWidth = Subtarget->is64Bit() ? 64 : 32;
19067 Type *MemType = AI->getType();
19069 // If the operand is too big, we must see if cmpxchg8/16b is available
19070 // and default to library calls otherwise.
19071 if (MemType->getPrimitiveSizeInBits() > NativeWidth) {
19072 return needsCmpXchgNb(MemType) ? AtomicExpansionKind::CmpXChg
19073 : AtomicExpansionKind::None;
19076 AtomicRMWInst::BinOp Op = AI->getOperation();
19079 llvm_unreachable("Unknown atomic operation");
19080 case AtomicRMWInst::Xchg:
19081 case AtomicRMWInst::Add:
19082 case AtomicRMWInst::Sub:
19083 // It's better to use xadd, xsub or xchg for these in all cases.
19084 return AtomicExpansionKind::None;
19085 case AtomicRMWInst::Or:
19086 case AtomicRMWInst::And:
19087 case AtomicRMWInst::Xor:
19088 // If the atomicrmw's result isn't actually used, we can just add a "lock"
19089 // prefix to a normal instruction for these operations.
19090 return !AI->use_empty() ? AtomicExpansionKind::CmpXChg
19091 : AtomicExpansionKind::None;
19092 case AtomicRMWInst::Nand:
19093 case AtomicRMWInst::Max:
19094 case AtomicRMWInst::Min:
19095 case AtomicRMWInst::UMax:
19096 case AtomicRMWInst::UMin:
19097 // These always require a non-trivial set of data operations on x86. We must
19098 // use a cmpxchg loop.
19099 return AtomicExpansionKind::CmpXChg;
19103 static bool hasMFENCE(const X86Subtarget& Subtarget) {
19104 // Use mfence if we have SSE2 or we're on x86-64 (even if we asked for
19105 // no-sse2). There isn't any reason to disable it if the target processor
19107 return Subtarget.hasSSE2() || Subtarget.is64Bit();
19111 X86TargetLowering::lowerIdempotentRMWIntoFencedLoad(AtomicRMWInst *AI) const {
19112 unsigned NativeWidth = Subtarget->is64Bit() ? 64 : 32;
19113 Type *MemType = AI->getType();
19114 // Accesses larger than the native width are turned into cmpxchg/libcalls, so
19115 // there is no benefit in turning such RMWs into loads, and it is actually
19116 // harmful as it introduces a mfence.
19117 if (MemType->getPrimitiveSizeInBits() > NativeWidth)
19120 auto Builder = IRBuilder<>(AI);
19121 Module *M = Builder.GetInsertBlock()->getParent()->getParent();
19122 auto SynchScope = AI->getSynchScope();
19123 // We must restrict the ordering to avoid generating loads with Release or
19124 // ReleaseAcquire orderings.
19125 auto Order = AtomicCmpXchgInst::getStrongestFailureOrdering(AI->getOrdering());
19126 auto Ptr = AI->getPointerOperand();
19128 // Before the load we need a fence. Here is an example lifted from
19129 // http://www.hpl.hp.com/techreports/2012/HPL-2012-68.pdf showing why a fence
19132 // x.store(1, relaxed);
19133 // r1 = y.fetch_add(0, release);
19135 // y.fetch_add(42, acquire);
19136 // r2 = x.load(relaxed);
19137 // r1 = r2 = 0 is impossible, but becomes possible if the idempotent rmw is
19138 // lowered to just a load without a fence. A mfence flushes the store buffer,
19139 // making the optimization clearly correct.
19140 // FIXME: it is required if isAtLeastRelease(Order) but it is not clear
19141 // otherwise, we might be able to be more aggressive on relaxed idempotent
19142 // rmw. In practice, they do not look useful, so we don't try to be
19143 // especially clever.
19144 if (SynchScope == SingleThread)
19145 // FIXME: we could just insert an X86ISD::MEMBARRIER here, except we are at
19146 // the IR level, so we must wrap it in an intrinsic.
19149 if (!hasMFENCE(*Subtarget))
19150 // FIXME: it might make sense to use a locked operation here but on a
19151 // different cache-line to prevent cache-line bouncing. In practice it
19152 // is probably a small win, and x86 processors without mfence are rare
19153 // enough that we do not bother.
19157 llvm::Intrinsic::getDeclaration(M, Intrinsic::x86_sse2_mfence);
19158 Builder.CreateCall(MFence, {});
19160 // Finally we can emit the atomic load.
19161 LoadInst *Loaded = Builder.CreateAlignedLoad(Ptr,
19162 AI->getType()->getPrimitiveSizeInBits());
19163 Loaded->setAtomic(Order, SynchScope);
19164 AI->replaceAllUsesWith(Loaded);
19165 AI->eraseFromParent();
19169 static SDValue LowerATOMIC_FENCE(SDValue Op, const X86Subtarget *Subtarget,
19170 SelectionDAG &DAG) {
19172 AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>(
19173 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue());
19174 SynchronizationScope FenceScope = static_cast<SynchronizationScope>(
19175 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
19177 // The only fence that needs an instruction is a sequentially-consistent
19178 // cross-thread fence.
19179 if (FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread) {
19180 if (hasMFENCE(*Subtarget))
19181 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
19183 SDValue Chain = Op.getOperand(0);
19184 SDValue Zero = DAG.getConstant(0, dl, MVT::i32);
19186 DAG.getRegister(X86::ESP, MVT::i32), // Base
19187 DAG.getTargetConstant(1, dl, MVT::i8), // Scale
19188 DAG.getRegister(0, MVT::i32), // Index
19189 DAG.getTargetConstant(0, dl, MVT::i32), // Disp
19190 DAG.getRegister(0, MVT::i32), // Segment.
19194 SDNode *Res = DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops);
19195 return SDValue(Res, 0);
19198 // MEMBARRIER is a compiler barrier; it codegens to a no-op.
19199 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
19202 static SDValue LowerCMP_SWAP(SDValue Op, const X86Subtarget *Subtarget,
19203 SelectionDAG &DAG) {
19204 MVT T = Op.getSimpleValueType();
19208 switch(T.SimpleTy) {
19209 default: llvm_unreachable("Invalid value type!");
19210 case MVT::i8: Reg = X86::AL; size = 1; break;
19211 case MVT::i16: Reg = X86::AX; size = 2; break;
19212 case MVT::i32: Reg = X86::EAX; size = 4; break;
19214 assert(Subtarget->is64Bit() && "Node not type legal!");
19215 Reg = X86::RAX; size = 8;
19218 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg,
19219 Op.getOperand(2), SDValue());
19220 SDValue Ops[] = { cpIn.getValue(0),
19223 DAG.getTargetConstant(size, DL, MVT::i8),
19224 cpIn.getValue(1) };
19225 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
19226 MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand();
19227 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys,
19231 DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1));
19232 SDValue EFLAGS = DAG.getCopyFromReg(cpOut.getValue(1), DL, X86::EFLAGS,
19233 MVT::i32, cpOut.getValue(2));
19234 SDValue Success = DAG.getNode(X86ISD::SETCC, DL, Op->getValueType(1),
19235 DAG.getConstant(X86::COND_E, DL, MVT::i8),
19238 DAG.ReplaceAllUsesOfValueWith(Op.getValue(0), cpOut);
19239 DAG.ReplaceAllUsesOfValueWith(Op.getValue(1), Success);
19240 DAG.ReplaceAllUsesOfValueWith(Op.getValue(2), EFLAGS.getValue(1));
19244 static SDValue LowerBITCAST(SDValue Op, const X86Subtarget *Subtarget,
19245 SelectionDAG &DAG) {
19246 MVT SrcVT = Op.getOperand(0).getSimpleValueType();
19247 MVT DstVT = Op.getSimpleValueType();
19249 if (SrcVT == MVT::v2i32 || SrcVT == MVT::v4i16 || SrcVT == MVT::v8i8) {
19250 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
19251 if (DstVT != MVT::f64)
19252 // This conversion needs to be expanded.
19255 SDValue InVec = Op->getOperand(0);
19257 unsigned NumElts = SrcVT.getVectorNumElements();
19258 MVT SVT = SrcVT.getVectorElementType();
19260 // Widen the vector in input in the case of MVT::v2i32.
19261 // Example: from MVT::v2i32 to MVT::v4i32.
19262 SmallVector<SDValue, 16> Elts;
19263 for (unsigned i = 0, e = NumElts; i != e; ++i)
19264 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT, InVec,
19265 DAG.getIntPtrConstant(i, dl)));
19267 // Explicitly mark the extra elements as Undef.
19268 Elts.append(NumElts, DAG.getUNDEF(SVT));
19270 EVT NewVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
19271 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Elts);
19272 SDValue ToV2F64 = DAG.getBitcast(MVT::v2f64, BV);
19273 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, ToV2F64,
19274 DAG.getIntPtrConstant(0, dl));
19277 assert(Subtarget->is64Bit() && !Subtarget->hasSSE2() &&
19278 Subtarget->hasMMX() && "Unexpected custom BITCAST");
19279 assert((DstVT == MVT::i64 ||
19280 (DstVT.isVector() && DstVT.getSizeInBits()==64)) &&
19281 "Unexpected custom BITCAST");
19282 // i64 <=> MMX conversions are Legal.
19283 if (SrcVT==MVT::i64 && DstVT.isVector())
19285 if (DstVT==MVT::i64 && SrcVT.isVector())
19287 // MMX <=> MMX conversions are Legal.
19288 if (SrcVT.isVector() && DstVT.isVector())
19290 // All other conversions need to be expanded.
19294 /// Compute the horizontal sum of bytes in V for the elements of VT.
19296 /// Requires V to be a byte vector and VT to be an integer vector type with
19297 /// wider elements than V's type. The width of the elements of VT determines
19298 /// how many bytes of V are summed horizontally to produce each element of the
19300 static SDValue LowerHorizontalByteSum(SDValue V, MVT VT,
19301 const X86Subtarget *Subtarget,
19302 SelectionDAG &DAG) {
19304 MVT ByteVecVT = V.getSimpleValueType();
19305 MVT EltVT = VT.getVectorElementType();
19306 int NumElts = VT.getVectorNumElements();
19307 assert(ByteVecVT.getVectorElementType() == MVT::i8 &&
19308 "Expected value to have byte element type.");
19309 assert(EltVT != MVT::i8 &&
19310 "Horizontal byte sum only makes sense for wider elements!");
19311 unsigned VecSize = VT.getSizeInBits();
19312 assert(ByteVecVT.getSizeInBits() == VecSize && "Cannot change vector size!");
19314 // PSADBW instruction horizontally add all bytes and leave the result in i64
19315 // chunks, thus directly computes the pop count for v2i64 and v4i64.
19316 if (EltVT == MVT::i64) {
19317 SDValue Zeros = getZeroVector(ByteVecVT, Subtarget, DAG, DL);
19318 V = DAG.getNode(X86ISD::PSADBW, DL, ByteVecVT, V, Zeros);
19319 return DAG.getBitcast(VT, V);
19322 if (EltVT == MVT::i32) {
19323 // We unpack the low half and high half into i32s interleaved with zeros so
19324 // that we can use PSADBW to horizontally sum them. The most useful part of
19325 // this is that it lines up the results of two PSADBW instructions to be
19326 // two v2i64 vectors which concatenated are the 4 population counts. We can
19327 // then use PACKUSWB to shrink and concatenate them into a v4i32 again.
19328 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, DL);
19329 SDValue Low = DAG.getNode(X86ISD::UNPCKL, DL, VT, V, Zeros);
19330 SDValue High = DAG.getNode(X86ISD::UNPCKH, DL, VT, V, Zeros);
19332 // Do the horizontal sums into two v2i64s.
19333 Zeros = getZeroVector(ByteVecVT, Subtarget, DAG, DL);
19334 Low = DAG.getNode(X86ISD::PSADBW, DL, ByteVecVT,
19335 DAG.getBitcast(ByteVecVT, Low), Zeros);
19336 High = DAG.getNode(X86ISD::PSADBW, DL, ByteVecVT,
19337 DAG.getBitcast(ByteVecVT, High), Zeros);
19339 // Merge them together.
19340 MVT ShortVecVT = MVT::getVectorVT(MVT::i16, VecSize / 16);
19341 V = DAG.getNode(X86ISD::PACKUS, DL, ByteVecVT,
19342 DAG.getBitcast(ShortVecVT, Low),
19343 DAG.getBitcast(ShortVecVT, High));
19345 return DAG.getBitcast(VT, V);
19348 // The only element type left is i16.
19349 assert(EltVT == MVT::i16 && "Unknown how to handle type");
19351 // To obtain pop count for each i16 element starting from the pop count for
19352 // i8 elements, shift the i16s left by 8, sum as i8s, and then shift as i16s
19353 // right by 8. It is important to shift as i16s as i8 vector shift isn't
19354 // directly supported.
19355 SmallVector<SDValue, 16> Shifters(NumElts, DAG.getConstant(8, DL, EltVT));
19356 SDValue Shifter = DAG.getNode(ISD::BUILD_VECTOR, DL, VT, Shifters);
19357 SDValue Shl = DAG.getNode(ISD::SHL, DL, VT, DAG.getBitcast(VT, V), Shifter);
19358 V = DAG.getNode(ISD::ADD, DL, ByteVecVT, DAG.getBitcast(ByteVecVT, Shl),
19359 DAG.getBitcast(ByteVecVT, V));
19360 return DAG.getNode(ISD::SRL, DL, VT, DAG.getBitcast(VT, V), Shifter);
19363 static SDValue LowerVectorCTPOPInRegLUT(SDValue Op, SDLoc DL,
19364 const X86Subtarget *Subtarget,
19365 SelectionDAG &DAG) {
19366 MVT VT = Op.getSimpleValueType();
19367 MVT EltVT = VT.getVectorElementType();
19368 unsigned VecSize = VT.getSizeInBits();
19370 // Implement a lookup table in register by using an algorithm based on:
19371 // http://wm.ite.pl/articles/sse-popcount.html
19373 // The general idea is that every lower byte nibble in the input vector is an
19374 // index into a in-register pre-computed pop count table. We then split up the
19375 // input vector in two new ones: (1) a vector with only the shifted-right
19376 // higher nibbles for each byte and (2) a vector with the lower nibbles (and
19377 // masked out higher ones) for each byte. PSHUB is used separately with both
19378 // to index the in-register table. Next, both are added and the result is a
19379 // i8 vector where each element contains the pop count for input byte.
19381 // To obtain the pop count for elements != i8, we follow up with the same
19382 // approach and use additional tricks as described below.
19384 const int LUT[16] = {/* 0 */ 0, /* 1 */ 1, /* 2 */ 1, /* 3 */ 2,
19385 /* 4 */ 1, /* 5 */ 2, /* 6 */ 2, /* 7 */ 3,
19386 /* 8 */ 1, /* 9 */ 2, /* a */ 2, /* b */ 3,
19387 /* c */ 2, /* d */ 3, /* e */ 3, /* f */ 4};
19389 int NumByteElts = VecSize / 8;
19390 MVT ByteVecVT = MVT::getVectorVT(MVT::i8, NumByteElts);
19391 SDValue In = DAG.getBitcast(ByteVecVT, Op);
19392 SmallVector<SDValue, 16> LUTVec;
19393 for (int i = 0; i < NumByteElts; ++i)
19394 LUTVec.push_back(DAG.getConstant(LUT[i % 16], DL, MVT::i8));
19395 SDValue InRegLUT = DAG.getNode(ISD::BUILD_VECTOR, DL, ByteVecVT, LUTVec);
19396 SmallVector<SDValue, 16> Mask0F(NumByteElts,
19397 DAG.getConstant(0x0F, DL, MVT::i8));
19398 SDValue M0F = DAG.getNode(ISD::BUILD_VECTOR, DL, ByteVecVT, Mask0F);
19401 SmallVector<SDValue, 16> Four(NumByteElts, DAG.getConstant(4, DL, MVT::i8));
19402 SDValue FourV = DAG.getNode(ISD::BUILD_VECTOR, DL, ByteVecVT, Four);
19403 SDValue HighNibbles = DAG.getNode(ISD::SRL, DL, ByteVecVT, In, FourV);
19406 SDValue LowNibbles = DAG.getNode(ISD::AND, DL, ByteVecVT, In, M0F);
19408 // The input vector is used as the shuffle mask that index elements into the
19409 // LUT. After counting low and high nibbles, add the vector to obtain the
19410 // final pop count per i8 element.
19411 SDValue HighPopCnt =
19412 DAG.getNode(X86ISD::PSHUFB, DL, ByteVecVT, InRegLUT, HighNibbles);
19413 SDValue LowPopCnt =
19414 DAG.getNode(X86ISD::PSHUFB, DL, ByteVecVT, InRegLUT, LowNibbles);
19415 SDValue PopCnt = DAG.getNode(ISD::ADD, DL, ByteVecVT, HighPopCnt, LowPopCnt);
19417 if (EltVT == MVT::i8)
19420 return LowerHorizontalByteSum(PopCnt, VT, Subtarget, DAG);
19423 static SDValue LowerVectorCTPOPBitmath(SDValue Op, SDLoc DL,
19424 const X86Subtarget *Subtarget,
19425 SelectionDAG &DAG) {
19426 MVT VT = Op.getSimpleValueType();
19427 assert(VT.is128BitVector() &&
19428 "Only 128-bit vector bitmath lowering supported.");
19430 int VecSize = VT.getSizeInBits();
19431 MVT EltVT = VT.getVectorElementType();
19432 int Len = EltVT.getSizeInBits();
19434 // This is the vectorized version of the "best" algorithm from
19435 // http://graphics.stanford.edu/~seander/bithacks.html#CountBitsSetParallel
19436 // with a minor tweak to use a series of adds + shifts instead of vector
19437 // multiplications. Implemented for all integer vector types. We only use
19438 // this when we don't have SSSE3 which allows a LUT-based lowering that is
19439 // much faster, even faster than using native popcnt instructions.
19441 auto GetShift = [&](unsigned OpCode, SDValue V, int Shifter) {
19442 MVT VT = V.getSimpleValueType();
19443 SmallVector<SDValue, 32> Shifters(
19444 VT.getVectorNumElements(),
19445 DAG.getConstant(Shifter, DL, VT.getVectorElementType()));
19446 return DAG.getNode(OpCode, DL, VT, V,
19447 DAG.getNode(ISD::BUILD_VECTOR, DL, VT, Shifters));
19449 auto GetMask = [&](SDValue V, APInt Mask) {
19450 MVT VT = V.getSimpleValueType();
19451 SmallVector<SDValue, 32> Masks(
19452 VT.getVectorNumElements(),
19453 DAG.getConstant(Mask, DL, VT.getVectorElementType()));
19454 return DAG.getNode(ISD::AND, DL, VT, V,
19455 DAG.getNode(ISD::BUILD_VECTOR, DL, VT, Masks));
19458 // We don't want to incur the implicit masks required to SRL vNi8 vectors on
19459 // x86, so set the SRL type to have elements at least i16 wide. This is
19460 // correct because all of our SRLs are followed immediately by a mask anyways
19461 // that handles any bits that sneak into the high bits of the byte elements.
19462 MVT SrlVT = Len > 8 ? VT : MVT::getVectorVT(MVT::i16, VecSize / 16);
19466 // v = v - ((v >> 1) & 0x55555555...)
19468 DAG.getBitcast(VT, GetShift(ISD::SRL, DAG.getBitcast(SrlVT, V), 1));
19469 SDValue And = GetMask(Srl, APInt::getSplat(Len, APInt(8, 0x55)));
19470 V = DAG.getNode(ISD::SUB, DL, VT, V, And);
19472 // v = (v & 0x33333333...) + ((v >> 2) & 0x33333333...)
19473 SDValue AndLHS = GetMask(V, APInt::getSplat(Len, APInt(8, 0x33)));
19474 Srl = DAG.getBitcast(VT, GetShift(ISD::SRL, DAG.getBitcast(SrlVT, V), 2));
19475 SDValue AndRHS = GetMask(Srl, APInt::getSplat(Len, APInt(8, 0x33)));
19476 V = DAG.getNode(ISD::ADD, DL, VT, AndLHS, AndRHS);
19478 // v = (v + (v >> 4)) & 0x0F0F0F0F...
19479 Srl = DAG.getBitcast(VT, GetShift(ISD::SRL, DAG.getBitcast(SrlVT, V), 4));
19480 SDValue Add = DAG.getNode(ISD::ADD, DL, VT, V, Srl);
19481 V = GetMask(Add, APInt::getSplat(Len, APInt(8, 0x0F)));
19483 // At this point, V contains the byte-wise population count, and we are
19484 // merely doing a horizontal sum if necessary to get the wider element
19486 if (EltVT == MVT::i8)
19489 return LowerHorizontalByteSum(
19490 DAG.getBitcast(MVT::getVectorVT(MVT::i8, VecSize / 8), V), VT, Subtarget,
19494 static SDValue LowerVectorCTPOP(SDValue Op, const X86Subtarget *Subtarget,
19495 SelectionDAG &DAG) {
19496 MVT VT = Op.getSimpleValueType();
19497 // FIXME: Need to add AVX-512 support here!
19498 assert((VT.is256BitVector() || VT.is128BitVector()) &&
19499 "Unknown CTPOP type to handle");
19500 SDLoc DL(Op.getNode());
19501 SDValue Op0 = Op.getOperand(0);
19503 if (!Subtarget->hasSSSE3()) {
19504 // We can't use the fast LUT approach, so fall back on vectorized bitmath.
19505 assert(VT.is128BitVector() && "Only 128-bit vectors supported in SSE!");
19506 return LowerVectorCTPOPBitmath(Op0, DL, Subtarget, DAG);
19509 if (VT.is256BitVector() && !Subtarget->hasInt256()) {
19510 unsigned NumElems = VT.getVectorNumElements();
19512 // Extract each 128-bit vector, compute pop count and concat the result.
19513 SDValue LHS = Extract128BitVector(Op0, 0, DAG, DL);
19514 SDValue RHS = Extract128BitVector(Op0, NumElems/2, DAG, DL);
19516 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT,
19517 LowerVectorCTPOPInRegLUT(LHS, DL, Subtarget, DAG),
19518 LowerVectorCTPOPInRegLUT(RHS, DL, Subtarget, DAG));
19521 return LowerVectorCTPOPInRegLUT(Op0, DL, Subtarget, DAG);
19524 static SDValue LowerCTPOP(SDValue Op, const X86Subtarget *Subtarget,
19525 SelectionDAG &DAG) {
19526 assert(Op.getSimpleValueType().isVector() &&
19527 "We only do custom lowering for vector population count.");
19528 return LowerVectorCTPOP(Op, Subtarget, DAG);
19531 static SDValue LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) {
19532 SDNode *Node = Op.getNode();
19534 EVT T = Node->getValueType(0);
19535 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
19536 DAG.getConstant(0, dl, T), Node->getOperand(2));
19537 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
19538 cast<AtomicSDNode>(Node)->getMemoryVT(),
19539 Node->getOperand(0),
19540 Node->getOperand(1), negOp,
19541 cast<AtomicSDNode>(Node)->getMemOperand(),
19542 cast<AtomicSDNode>(Node)->getOrdering(),
19543 cast<AtomicSDNode>(Node)->getSynchScope());
19546 static SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) {
19547 SDNode *Node = Op.getNode();
19549 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
19551 // Convert seq_cst store -> xchg
19552 // Convert wide store -> swap (-> cmpxchg8b/cmpxchg16b)
19553 // FIXME: On 32-bit, store -> fist or movq would be more efficient
19554 // (The only way to get a 16-byte store is cmpxchg16b)
19555 // FIXME: 16-byte ATOMIC_SWAP isn't actually hooked up at the moment.
19556 if (cast<AtomicSDNode>(Node)->getOrdering() == SequentiallyConsistent ||
19557 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
19558 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
19559 cast<AtomicSDNode>(Node)->getMemoryVT(),
19560 Node->getOperand(0),
19561 Node->getOperand(1), Node->getOperand(2),
19562 cast<AtomicSDNode>(Node)->getMemOperand(),
19563 cast<AtomicSDNode>(Node)->getOrdering(),
19564 cast<AtomicSDNode>(Node)->getSynchScope());
19565 return Swap.getValue(1);
19567 // Other atomic stores have a simple pattern.
19571 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
19572 MVT VT = Op.getNode()->getSimpleValueType(0);
19574 // Let legalize expand this if it isn't a legal type yet.
19575 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
19578 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
19581 bool ExtraOp = false;
19582 switch (Op.getOpcode()) {
19583 default: llvm_unreachable("Invalid code");
19584 case ISD::ADDC: Opc = X86ISD::ADD; break;
19585 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break;
19586 case ISD::SUBC: Opc = X86ISD::SUB; break;
19587 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break;
19591 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
19593 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
19594 Op.getOperand(1), Op.getOperand(2));
19597 static SDValue LowerFSINCOS(SDValue Op, const X86Subtarget *Subtarget,
19598 SelectionDAG &DAG) {
19599 assert(Subtarget->isTargetDarwin() && Subtarget->is64Bit());
19601 // For MacOSX, we want to call an alternative entry point: __sincos_stret,
19602 // which returns the values as { float, float } (in XMM0) or
19603 // { double, double } (which is returned in XMM0, XMM1).
19605 SDValue Arg = Op.getOperand(0);
19606 EVT ArgVT = Arg.getValueType();
19607 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
19609 TargetLowering::ArgListTy Args;
19610 TargetLowering::ArgListEntry Entry;
19614 Entry.isSExt = false;
19615 Entry.isZExt = false;
19616 Args.push_back(Entry);
19618 bool isF64 = ArgVT == MVT::f64;
19619 // Only optimize x86_64 for now. i386 is a bit messy. For f32,
19620 // the small struct {f32, f32} is returned in (eax, edx). For f64,
19621 // the results are returned via SRet in memory.
19622 const char *LibcallName = isF64 ? "__sincos_stret" : "__sincosf_stret";
19623 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
19625 DAG.getExternalSymbol(LibcallName, TLI.getPointerTy(DAG.getDataLayout()));
19627 Type *RetTy = isF64
19628 ? (Type*)StructType::get(ArgTy, ArgTy, nullptr)
19629 : (Type*)VectorType::get(ArgTy, 4);
19631 TargetLowering::CallLoweringInfo CLI(DAG);
19632 CLI.setDebugLoc(dl).setChain(DAG.getEntryNode())
19633 .setCallee(CallingConv::C, RetTy, Callee, std::move(Args), 0);
19635 std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI);
19638 // Returned in xmm0 and xmm1.
19639 return CallResult.first;
19641 // Returned in bits 0:31 and 32:64 xmm0.
19642 SDValue SinVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
19643 CallResult.first, DAG.getIntPtrConstant(0, dl));
19644 SDValue CosVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
19645 CallResult.first, DAG.getIntPtrConstant(1, dl));
19646 SDVTList Tys = DAG.getVTList(ArgVT, ArgVT);
19647 return DAG.getNode(ISD::MERGE_VALUES, dl, Tys, SinVal, CosVal);
19650 static SDValue LowerMSCATTER(SDValue Op, const X86Subtarget *Subtarget,
19651 SelectionDAG &DAG) {
19652 assert(Subtarget->hasAVX512() &&
19653 "MGATHER/MSCATTER are supported on AVX-512 arch only");
19655 MaskedScatterSDNode *N = cast<MaskedScatterSDNode>(Op.getNode());
19656 MVT VT = N->getValue().getSimpleValueType();
19657 assert(VT.getScalarSizeInBits() >= 32 && "Unsupported scatter op");
19660 // X86 scatter kills mask register, so its type should be added to
19661 // the list of return values
19662 if (N->getNumValues() == 1) {
19663 SDValue Index = N->getIndex();
19664 if (!Subtarget->hasVLX() && !VT.is512BitVector() &&
19665 !Index.getSimpleValueType().is512BitVector())
19666 Index = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i64, Index);
19668 SDVTList VTs = DAG.getVTList(N->getMask().getValueType(), MVT::Other);
19669 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), N->getOperand(2),
19670 N->getOperand(3), Index };
19672 SDValue NewScatter = DAG.getMaskedScatter(VTs, VT, dl, Ops, N->getMemOperand());
19673 DAG.ReplaceAllUsesWith(Op, SDValue(NewScatter.getNode(), 1));
19674 return SDValue(NewScatter.getNode(), 0);
19679 static SDValue LowerMGATHER(SDValue Op, const X86Subtarget *Subtarget,
19680 SelectionDAG &DAG) {
19681 assert(Subtarget->hasAVX512() &&
19682 "MGATHER/MSCATTER are supported on AVX-512 arch only");
19684 MaskedGatherSDNode *N = cast<MaskedGatherSDNode>(Op.getNode());
19685 MVT VT = Op.getSimpleValueType();
19686 assert(VT.getScalarSizeInBits() >= 32 && "Unsupported gather op");
19689 SDValue Index = N->getIndex();
19690 if (!Subtarget->hasVLX() && !VT.is512BitVector() &&
19691 !Index.getSimpleValueType().is512BitVector()) {
19692 Index = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i64, Index);
19693 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), N->getOperand(2),
19694 N->getOperand(3), Index };
19695 DAG.UpdateNodeOperands(N, Ops);
19700 SDValue X86TargetLowering::LowerGC_TRANSITION_START(SDValue Op,
19701 SelectionDAG &DAG) const {
19702 // TODO: Eventually, the lowering of these nodes should be informed by or
19703 // deferred to the GC strategy for the function in which they appear. For
19704 // now, however, they must be lowered to something. Since they are logically
19705 // no-ops in the case of a null GC strategy (or a GC strategy which does not
19706 // require special handling for these nodes), lower them as literal NOOPs for
19708 SmallVector<SDValue, 2> Ops;
19710 Ops.push_back(Op.getOperand(0));
19711 if (Op->getGluedNode())
19712 Ops.push_back(Op->getOperand(Op->getNumOperands() - 1));
19715 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
19716 SDValue NOOP(DAG.getMachineNode(X86::NOOP, SDLoc(Op), VTs, Ops), 0);
19721 SDValue X86TargetLowering::LowerGC_TRANSITION_END(SDValue Op,
19722 SelectionDAG &DAG) const {
19723 // TODO: Eventually, the lowering of these nodes should be informed by or
19724 // deferred to the GC strategy for the function in which they appear. For
19725 // now, however, they must be lowered to something. Since they are logically
19726 // no-ops in the case of a null GC strategy (or a GC strategy which does not
19727 // require special handling for these nodes), lower them as literal NOOPs for
19729 SmallVector<SDValue, 2> Ops;
19731 Ops.push_back(Op.getOperand(0));
19732 if (Op->getGluedNode())
19733 Ops.push_back(Op->getOperand(Op->getNumOperands() - 1));
19736 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
19737 SDValue NOOP(DAG.getMachineNode(X86::NOOP, SDLoc(Op), VTs, Ops), 0);
19742 /// LowerOperation - Provide custom lowering hooks for some operations.
19744 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
19745 switch (Op.getOpcode()) {
19746 default: llvm_unreachable("Should not custom lower this!");
19747 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, Subtarget, DAG);
19748 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS:
19749 return LowerCMP_SWAP(Op, Subtarget, DAG);
19750 case ISD::CTPOP: return LowerCTPOP(Op, Subtarget, DAG);
19751 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
19752 case ISD::ATOMIC_STORE: return LowerATOMIC_STORE(Op,DAG);
19753 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
19754 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, Subtarget, DAG);
19755 case ISD::VECTOR_SHUFFLE: return lowerVectorShuffle(Op, Subtarget, DAG);
19756 case ISD::VSELECT: return LowerVSELECT(Op, DAG);
19757 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
19758 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
19759 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op,Subtarget,DAG);
19760 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, Subtarget,DAG);
19761 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
19762 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
19763 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
19764 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
19765 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
19766 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
19767 case ISD::SHL_PARTS:
19768 case ISD::SRA_PARTS:
19769 case ISD::SRL_PARTS: return LowerShiftParts(Op, DAG);
19770 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
19771 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
19772 case ISD::TRUNCATE: return LowerTRUNCATE(Op, DAG);
19773 case ISD::ZERO_EXTEND: return LowerZERO_EXTEND(Op, Subtarget, DAG);
19774 case ISD::SIGN_EXTEND: return LowerSIGN_EXTEND(Op, Subtarget, DAG);
19775 case ISD::ANY_EXTEND: return LowerANY_EXTEND(Op, Subtarget, DAG);
19776 case ISD::SIGN_EXTEND_VECTOR_INREG:
19777 return LowerSIGN_EXTEND_VECTOR_INREG(Op, Subtarget, DAG);
19778 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
19779 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
19780 case ISD::FP_EXTEND: return LowerFP_EXTEND(Op, DAG);
19781 case ISD::LOAD: return LowerExtendedLoad(Op, Subtarget, DAG);
19783 case ISD::FNEG: return LowerFABSorFNEG(Op, DAG);
19784 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
19785 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG);
19786 case ISD::SETCC: return LowerSETCC(Op, DAG);
19787 case ISD::SETCCE: return LowerSETCCE(Op, DAG);
19788 case ISD::SELECT: return LowerSELECT(Op, DAG);
19789 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
19790 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
19791 case ISD::VASTART: return LowerVASTART(Op, DAG);
19792 case ISD::VAARG: return LowerVAARG(Op, DAG);
19793 case ISD::VACOPY: return LowerVACOPY(Op, Subtarget, DAG);
19794 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, Subtarget, DAG);
19795 case ISD::INTRINSIC_VOID:
19796 case ISD::INTRINSIC_W_CHAIN: return LowerINTRINSIC_W_CHAIN(Op, Subtarget, DAG);
19797 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
19798 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
19799 case ISD::FRAME_TO_ARGS_OFFSET:
19800 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
19801 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
19802 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
19803 case ISD::EH_SJLJ_SETJMP: return lowerEH_SJLJ_SETJMP(Op, DAG);
19804 case ISD::EH_SJLJ_LONGJMP: return lowerEH_SJLJ_LONGJMP(Op, DAG);
19805 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
19806 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
19807 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
19808 case ISD::CTLZ: return LowerCTLZ(Op, Subtarget, DAG);
19809 case ISD::CTLZ_ZERO_UNDEF: return LowerCTLZ_ZERO_UNDEF(Op, Subtarget, DAG);
19811 case ISD::CTTZ_ZERO_UNDEF: return LowerCTTZ(Op, DAG);
19812 case ISD::MUL: return LowerMUL(Op, Subtarget, DAG);
19813 case ISD::UMUL_LOHI:
19814 case ISD::SMUL_LOHI: return LowerMUL_LOHI(Op, Subtarget, DAG);
19815 case ISD::ROTL: return LowerRotate(Op, Subtarget, DAG);
19818 case ISD::SHL: return LowerShift(Op, Subtarget, DAG);
19824 case ISD::UMULO: return LowerXALUO(Op, DAG);
19825 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, Subtarget,DAG);
19826 case ISD::BITCAST: return LowerBITCAST(Op, Subtarget, DAG);
19830 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
19831 case ISD::ADD: return LowerADD(Op, DAG);
19832 case ISD::SUB: return LowerSUB(Op, DAG);
19836 case ISD::UMIN: return LowerMINMAX(Op, DAG);
19837 case ISD::FSINCOS: return LowerFSINCOS(Op, Subtarget, DAG);
19838 case ISD::MGATHER: return LowerMGATHER(Op, Subtarget, DAG);
19839 case ISD::MSCATTER: return LowerMSCATTER(Op, Subtarget, DAG);
19840 case ISD::GC_TRANSITION_START:
19841 return LowerGC_TRANSITION_START(Op, DAG);
19842 case ISD::GC_TRANSITION_END: return LowerGC_TRANSITION_END(Op, DAG);
19846 /// ReplaceNodeResults - Replace a node with an illegal result type
19847 /// with a new node built out of custom code.
19848 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
19849 SmallVectorImpl<SDValue>&Results,
19850 SelectionDAG &DAG) const {
19852 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
19853 switch (N->getOpcode()) {
19855 llvm_unreachable("Do not know how to custom type legalize this operation!");
19856 // We might have generated v2f32 FMIN/FMAX operations. Widen them to v4f32.
19857 case X86ISD::FMINC:
19859 case X86ISD::FMAXC:
19860 case X86ISD::FMAX: {
19861 EVT VT = N->getValueType(0);
19862 assert(VT == MVT::v2f32 && "Unexpected type (!= v2f32) on FMIN/FMAX.");
19863 SDValue UNDEF = DAG.getUNDEF(VT);
19864 SDValue LHS = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v4f32,
19865 N->getOperand(0), UNDEF);
19866 SDValue RHS = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v4f32,
19867 N->getOperand(1), UNDEF);
19868 Results.push_back(DAG.getNode(N->getOpcode(), dl, MVT::v4f32, LHS, RHS));
19871 case ISD::SIGN_EXTEND_INREG:
19876 // We don't want to expand or promote these.
19883 case ISD::UDIVREM: {
19884 SDValue V = LowerWin64_i128OP(SDValue(N,0), DAG);
19885 Results.push_back(V);
19888 case ISD::FP_TO_SINT:
19889 case ISD::FP_TO_UINT: {
19890 bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT;
19892 std::pair<SDValue,SDValue> Vals =
19893 FP_TO_INTHelper(SDValue(N, 0), DAG, IsSigned, /*IsReplace=*/ true);
19894 SDValue FIST = Vals.first, StackSlot = Vals.second;
19895 if (FIST.getNode()) {
19896 EVT VT = N->getValueType(0);
19897 // Return a load from the stack slot.
19898 if (StackSlot.getNode())
19899 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot,
19900 MachinePointerInfo(),
19901 false, false, false, 0));
19903 Results.push_back(FIST);
19907 case ISD::UINT_TO_FP: {
19908 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
19909 if (N->getOperand(0).getValueType() != MVT::v2i32 ||
19910 N->getValueType(0) != MVT::v2f32)
19912 SDValue ZExtIn = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v2i64,
19914 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL), dl,
19916 SDValue VBias = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2f64, Bias, Bias);
19917 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64, ZExtIn,
19918 DAG.getBitcast(MVT::v2i64, VBias));
19919 Or = DAG.getBitcast(MVT::v2f64, Or);
19920 // TODO: Are there any fast-math-flags to propagate here?
19921 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, Or, VBias);
19922 Results.push_back(DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, Sub));
19925 case ISD::FP_ROUND: {
19926 if (!TLI.isTypeLegal(N->getOperand(0).getValueType()))
19928 SDValue V = DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, N->getOperand(0));
19929 Results.push_back(V);
19932 case ISD::FP_EXTEND: {
19933 // Right now, only MVT::v2f32 has OperationAction for FP_EXTEND.
19934 // No other ValueType for FP_EXTEND should reach this point.
19935 assert(N->getValueType(0) == MVT::v2f32 &&
19936 "Do not know how to legalize this Node");
19939 case ISD::INTRINSIC_W_CHAIN: {
19940 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
19942 default : llvm_unreachable("Do not know how to custom type "
19943 "legalize this intrinsic operation!");
19944 case Intrinsic::x86_rdtsc:
19945 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
19947 case Intrinsic::x86_rdtscp:
19948 return getReadTimeStampCounter(N, dl, X86ISD::RDTSCP_DAG, DAG, Subtarget,
19950 case Intrinsic::x86_rdpmc:
19951 return getReadPerformanceCounter(N, dl, DAG, Subtarget, Results);
19954 case ISD::READCYCLECOUNTER: {
19955 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
19958 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS: {
19959 EVT T = N->getValueType(0);
19960 assert((T == MVT::i64 || T == MVT::i128) && "can only expand cmpxchg pair");
19961 bool Regs64bit = T == MVT::i128;
19962 MVT HalfT = Regs64bit ? MVT::i64 : MVT::i32;
19963 SDValue cpInL, cpInH;
19964 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
19965 DAG.getConstant(0, dl, HalfT));
19966 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
19967 DAG.getConstant(1, dl, HalfT));
19968 cpInL = DAG.getCopyToReg(N->getOperand(0), dl,
19969 Regs64bit ? X86::RAX : X86::EAX,
19971 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl,
19972 Regs64bit ? X86::RDX : X86::EDX,
19973 cpInH, cpInL.getValue(1));
19974 SDValue swapInL, swapInH;
19975 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
19976 DAG.getConstant(0, dl, HalfT));
19977 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
19978 DAG.getConstant(1, dl, HalfT));
19979 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl,
19980 Regs64bit ? X86::RBX : X86::EBX,
19981 swapInL, cpInH.getValue(1));
19982 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl,
19983 Regs64bit ? X86::RCX : X86::ECX,
19984 swapInH, swapInL.getValue(1));
19985 SDValue Ops[] = { swapInH.getValue(0),
19987 swapInH.getValue(1) };
19988 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
19989 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand();
19990 unsigned Opcode = Regs64bit ? X86ISD::LCMPXCHG16_DAG :
19991 X86ISD::LCMPXCHG8_DAG;
19992 SDValue Result = DAG.getMemIntrinsicNode(Opcode, dl, Tys, Ops, T, MMO);
19993 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl,
19994 Regs64bit ? X86::RAX : X86::EAX,
19995 HalfT, Result.getValue(1));
19996 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl,
19997 Regs64bit ? X86::RDX : X86::EDX,
19998 HalfT, cpOutL.getValue(2));
19999 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
20001 SDValue EFLAGS = DAG.getCopyFromReg(cpOutH.getValue(1), dl, X86::EFLAGS,
20002 MVT::i32, cpOutH.getValue(2));
20004 DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
20005 DAG.getConstant(X86::COND_E, dl, MVT::i8), EFLAGS);
20006 Success = DAG.getZExtOrTrunc(Success, dl, N->getValueType(1));
20008 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, T, OpsF));
20009 Results.push_back(Success);
20010 Results.push_back(EFLAGS.getValue(1));
20013 case ISD::ATOMIC_SWAP:
20014 case ISD::ATOMIC_LOAD_ADD:
20015 case ISD::ATOMIC_LOAD_SUB:
20016 case ISD::ATOMIC_LOAD_AND:
20017 case ISD::ATOMIC_LOAD_OR:
20018 case ISD::ATOMIC_LOAD_XOR:
20019 case ISD::ATOMIC_LOAD_NAND:
20020 case ISD::ATOMIC_LOAD_MIN:
20021 case ISD::ATOMIC_LOAD_MAX:
20022 case ISD::ATOMIC_LOAD_UMIN:
20023 case ISD::ATOMIC_LOAD_UMAX:
20024 case ISD::ATOMIC_LOAD: {
20025 // Delegate to generic TypeLegalization. Situations we can really handle
20026 // should have already been dealt with by AtomicExpandPass.cpp.
20029 case ISD::BITCAST: {
20030 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
20031 EVT DstVT = N->getValueType(0);
20032 EVT SrcVT = N->getOperand(0)->getValueType(0);
20034 if (SrcVT != MVT::f64 ||
20035 (DstVT != MVT::v2i32 && DstVT != MVT::v4i16 && DstVT != MVT::v8i8))
20038 unsigned NumElts = DstVT.getVectorNumElements();
20039 EVT SVT = DstVT.getVectorElementType();
20040 EVT WiderVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
20041 SDValue Expanded = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
20042 MVT::v2f64, N->getOperand(0));
20043 SDValue ToVecInt = DAG.getBitcast(WiderVT, Expanded);
20045 if (ExperimentalVectorWideningLegalization) {
20046 // If we are legalizing vectors by widening, we already have the desired
20047 // legal vector type, just return it.
20048 Results.push_back(ToVecInt);
20052 SmallVector<SDValue, 8> Elts;
20053 for (unsigned i = 0, e = NumElts; i != e; ++i)
20054 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT,
20055 ToVecInt, DAG.getIntPtrConstant(i, dl)));
20057 Results.push_back(DAG.getNode(ISD::BUILD_VECTOR, dl, DstVT, Elts));
20062 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
20063 switch ((X86ISD::NodeType)Opcode) {
20064 case X86ISD::FIRST_NUMBER: break;
20065 case X86ISD::BSF: return "X86ISD::BSF";
20066 case X86ISD::BSR: return "X86ISD::BSR";
20067 case X86ISD::SHLD: return "X86ISD::SHLD";
20068 case X86ISD::SHRD: return "X86ISD::SHRD";
20069 case X86ISD::FAND: return "X86ISD::FAND";
20070 case X86ISD::FANDN: return "X86ISD::FANDN";
20071 case X86ISD::FOR: return "X86ISD::FOR";
20072 case X86ISD::FXOR: return "X86ISD::FXOR";
20073 case X86ISD::FILD: return "X86ISD::FILD";
20074 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
20075 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
20076 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
20077 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
20078 case X86ISD::FLD: return "X86ISD::FLD";
20079 case X86ISD::FST: return "X86ISD::FST";
20080 case X86ISD::CALL: return "X86ISD::CALL";
20081 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
20082 case X86ISD::RDTSCP_DAG: return "X86ISD::RDTSCP_DAG";
20083 case X86ISD::RDPMC_DAG: return "X86ISD::RDPMC_DAG";
20084 case X86ISD::BT: return "X86ISD::BT";
20085 case X86ISD::CMP: return "X86ISD::CMP";
20086 case X86ISD::COMI: return "X86ISD::COMI";
20087 case X86ISD::UCOMI: return "X86ISD::UCOMI";
20088 case X86ISD::CMPM: return "X86ISD::CMPM";
20089 case X86ISD::CMPMU: return "X86ISD::CMPMU";
20090 case X86ISD::CMPM_RND: return "X86ISD::CMPM_RND";
20091 case X86ISD::SETCC: return "X86ISD::SETCC";
20092 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY";
20093 case X86ISD::FSETCC: return "X86ISD::FSETCC";
20094 case X86ISD::FGETSIGNx86: return "X86ISD::FGETSIGNx86";
20095 case X86ISD::CMOV: return "X86ISD::CMOV";
20096 case X86ISD::BRCOND: return "X86ISD::BRCOND";
20097 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
20098 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
20099 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
20100 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
20101 case X86ISD::Wrapper: return "X86ISD::Wrapper";
20102 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
20103 case X86ISD::MOVDQ2Q: return "X86ISD::MOVDQ2Q";
20104 case X86ISD::MMX_MOVD2W: return "X86ISD::MMX_MOVD2W";
20105 case X86ISD::MMX_MOVW2D: return "X86ISD::MMX_MOVW2D";
20106 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
20107 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
20108 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
20109 case X86ISD::PINSRB: return "X86ISD::PINSRB";
20110 case X86ISD::PINSRW: return "X86ISD::PINSRW";
20111 case X86ISD::MMX_PINSRW: return "X86ISD::MMX_PINSRW";
20112 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
20113 case X86ISD::ANDNP: return "X86ISD::ANDNP";
20114 case X86ISD::PSIGN: return "X86ISD::PSIGN";
20115 case X86ISD::BLENDI: return "X86ISD::BLENDI";
20116 case X86ISD::SHRUNKBLEND: return "X86ISD::SHRUNKBLEND";
20117 case X86ISD::ADDUS: return "X86ISD::ADDUS";
20118 case X86ISD::SUBUS: return "X86ISD::SUBUS";
20119 case X86ISD::HADD: return "X86ISD::HADD";
20120 case X86ISD::HSUB: return "X86ISD::HSUB";
20121 case X86ISD::FHADD: return "X86ISD::FHADD";
20122 case X86ISD::FHSUB: return "X86ISD::FHSUB";
20123 case X86ISD::ABS: return "X86ISD::ABS";
20124 case X86ISD::CONFLICT: return "X86ISD::CONFLICT";
20125 case X86ISD::FMAX: return "X86ISD::FMAX";
20126 case X86ISD::FMAX_RND: return "X86ISD::FMAX_RND";
20127 case X86ISD::FMIN: return "X86ISD::FMIN";
20128 case X86ISD::FMIN_RND: return "X86ISD::FMIN_RND";
20129 case X86ISD::FMAXC: return "X86ISD::FMAXC";
20130 case X86ISD::FMINC: return "X86ISD::FMINC";
20131 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
20132 case X86ISD::FRCP: return "X86ISD::FRCP";
20133 case X86ISD::EXTRQI: return "X86ISD::EXTRQI";
20134 case X86ISD::INSERTQI: return "X86ISD::INSERTQI";
20135 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
20136 case X86ISD::TLSBASEADDR: return "X86ISD::TLSBASEADDR";
20137 case X86ISD::TLSCALL: return "X86ISD::TLSCALL";
20138 case X86ISD::EH_SJLJ_SETJMP: return "X86ISD::EH_SJLJ_SETJMP";
20139 case X86ISD::EH_SJLJ_LONGJMP: return "X86ISD::EH_SJLJ_LONGJMP";
20140 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
20141 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
20142 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
20143 case X86ISD::FNSTSW16r: return "X86ISD::FNSTSW16r";
20144 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
20145 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
20146 case X86ISD::LCMPXCHG16_DAG: return "X86ISD::LCMPXCHG16_DAG";
20147 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
20148 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
20149 case X86ISD::VZEXT: return "X86ISD::VZEXT";
20150 case X86ISD::VSEXT: return "X86ISD::VSEXT";
20151 case X86ISD::VTRUNC: return "X86ISD::VTRUNC";
20152 case X86ISD::VTRUNCS: return "X86ISD::VTRUNCS";
20153 case X86ISD::VTRUNCUS: return "X86ISD::VTRUNCUS";
20154 case X86ISD::VINSERT: return "X86ISD::VINSERT";
20155 case X86ISD::VFPEXT: return "X86ISD::VFPEXT";
20156 case X86ISD::VFPROUND: return "X86ISD::VFPROUND";
20157 case X86ISD::CVTDQ2PD: return "X86ISD::CVTDQ2PD";
20158 case X86ISD::CVTUDQ2PD: return "X86ISD::CVTUDQ2PD";
20159 case X86ISD::VSHLDQ: return "X86ISD::VSHLDQ";
20160 case X86ISD::VSRLDQ: return "X86ISD::VSRLDQ";
20161 case X86ISD::VSHL: return "X86ISD::VSHL";
20162 case X86ISD::VSRL: return "X86ISD::VSRL";
20163 case X86ISD::VSRA: return "X86ISD::VSRA";
20164 case X86ISD::VSHLI: return "X86ISD::VSHLI";
20165 case X86ISD::VSRLI: return "X86ISD::VSRLI";
20166 case X86ISD::VSRAI: return "X86ISD::VSRAI";
20167 case X86ISD::CMPP: return "X86ISD::CMPP";
20168 case X86ISD::PCMPEQ: return "X86ISD::PCMPEQ";
20169 case X86ISD::PCMPGT: return "X86ISD::PCMPGT";
20170 case X86ISD::PCMPEQM: return "X86ISD::PCMPEQM";
20171 case X86ISD::PCMPGTM: return "X86ISD::PCMPGTM";
20172 case X86ISD::ADD: return "X86ISD::ADD";
20173 case X86ISD::SUB: return "X86ISD::SUB";
20174 case X86ISD::ADC: return "X86ISD::ADC";
20175 case X86ISD::SBB: return "X86ISD::SBB";
20176 case X86ISD::SMUL: return "X86ISD::SMUL";
20177 case X86ISD::UMUL: return "X86ISD::UMUL";
20178 case X86ISD::SMUL8: return "X86ISD::SMUL8";
20179 case X86ISD::UMUL8: return "X86ISD::UMUL8";
20180 case X86ISD::SDIVREM8_SEXT_HREG: return "X86ISD::SDIVREM8_SEXT_HREG";
20181 case X86ISD::UDIVREM8_ZEXT_HREG: return "X86ISD::UDIVREM8_ZEXT_HREG";
20182 case X86ISD::INC: return "X86ISD::INC";
20183 case X86ISD::DEC: return "X86ISD::DEC";
20184 case X86ISD::OR: return "X86ISD::OR";
20185 case X86ISD::XOR: return "X86ISD::XOR";
20186 case X86ISD::AND: return "X86ISD::AND";
20187 case X86ISD::BEXTR: return "X86ISD::BEXTR";
20188 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
20189 case X86ISD::PTEST: return "X86ISD::PTEST";
20190 case X86ISD::TESTP: return "X86ISD::TESTP";
20191 case X86ISD::TESTM: return "X86ISD::TESTM";
20192 case X86ISD::TESTNM: return "X86ISD::TESTNM";
20193 case X86ISD::KORTEST: return "X86ISD::KORTEST";
20194 case X86ISD::KTEST: return "X86ISD::KTEST";
20195 case X86ISD::PACKSS: return "X86ISD::PACKSS";
20196 case X86ISD::PACKUS: return "X86ISD::PACKUS";
20197 case X86ISD::PALIGNR: return "X86ISD::PALIGNR";
20198 case X86ISD::VALIGN: return "X86ISD::VALIGN";
20199 case X86ISD::PSHUFD: return "X86ISD::PSHUFD";
20200 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW";
20201 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW";
20202 case X86ISD::SHUFP: return "X86ISD::SHUFP";
20203 case X86ISD::SHUF128: return "X86ISD::SHUF128";
20204 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS";
20205 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD";
20206 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS";
20207 case X86ISD::MOVLPS: return "X86ISD::MOVLPS";
20208 case X86ISD::MOVLPD: return "X86ISD::MOVLPD";
20209 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP";
20210 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP";
20211 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP";
20212 case X86ISD::MOVSD: return "X86ISD::MOVSD";
20213 case X86ISD::MOVSS: return "X86ISD::MOVSS";
20214 case X86ISD::UNPCKL: return "X86ISD::UNPCKL";
20215 case X86ISD::UNPCKH: return "X86ISD::UNPCKH";
20216 case X86ISD::VBROADCAST: return "X86ISD::VBROADCAST";
20217 case X86ISD::VBROADCASTM: return "X86ISD::VBROADCASTM";
20218 case X86ISD::SUBV_BROADCAST: return "X86ISD::SUBV_BROADCAST";
20219 case X86ISD::VEXTRACT: return "X86ISD::VEXTRACT";
20220 case X86ISD::VPERMILPV: return "X86ISD::VPERMILPV";
20221 case X86ISD::VPERMILPI: return "X86ISD::VPERMILPI";
20222 case X86ISD::VPERM2X128: return "X86ISD::VPERM2X128";
20223 case X86ISD::VPERMV: return "X86ISD::VPERMV";
20224 case X86ISD::VPERMV3: return "X86ISD::VPERMV3";
20225 case X86ISD::VPERMIV3: return "X86ISD::VPERMIV3";
20226 case X86ISD::VPERMI: return "X86ISD::VPERMI";
20227 case X86ISD::VPTERNLOG: return "X86ISD::VPTERNLOG";
20228 case X86ISD::VFIXUPIMM: return "X86ISD::VFIXUPIMM";
20229 case X86ISD::VRANGE: return "X86ISD::VRANGE";
20230 case X86ISD::PMULUDQ: return "X86ISD::PMULUDQ";
20231 case X86ISD::PMULDQ: return "X86ISD::PMULDQ";
20232 case X86ISD::PSADBW: return "X86ISD::PSADBW";
20233 case X86ISD::DBPSADBW: return "X86ISD::DBPSADBW";
20234 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
20235 case X86ISD::VAARG_64: return "X86ISD::VAARG_64";
20236 case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA";
20237 case X86ISD::MEMBARRIER: return "X86ISD::MEMBARRIER";
20238 case X86ISD::MFENCE: return "X86ISD::MFENCE";
20239 case X86ISD::SFENCE: return "X86ISD::SFENCE";
20240 case X86ISD::LFENCE: return "X86ISD::LFENCE";
20241 case X86ISD::SEG_ALLOCA: return "X86ISD::SEG_ALLOCA";
20242 case X86ISD::SAHF: return "X86ISD::SAHF";
20243 case X86ISD::RDRAND: return "X86ISD::RDRAND";
20244 case X86ISD::RDSEED: return "X86ISD::RDSEED";
20245 case X86ISD::VPMADDUBSW: return "X86ISD::VPMADDUBSW";
20246 case X86ISD::VPMADDWD: return "X86ISD::VPMADDWD";
20247 case X86ISD::VPROT: return "X86ISD::VPROT";
20248 case X86ISD::VPROTI: return "X86ISD::VPROTI";
20249 case X86ISD::VPSHA: return "X86ISD::VPSHA";
20250 case X86ISD::VPSHL: return "X86ISD::VPSHL";
20251 case X86ISD::VPCOM: return "X86ISD::VPCOM";
20252 case X86ISD::VPCOMU: return "X86ISD::VPCOMU";
20253 case X86ISD::FMADD: return "X86ISD::FMADD";
20254 case X86ISD::FMSUB: return "X86ISD::FMSUB";
20255 case X86ISD::FNMADD: return "X86ISD::FNMADD";
20256 case X86ISD::FNMSUB: return "X86ISD::FNMSUB";
20257 case X86ISD::FMADDSUB: return "X86ISD::FMADDSUB";
20258 case X86ISD::FMSUBADD: return "X86ISD::FMSUBADD";
20259 case X86ISD::FMADD_RND: return "X86ISD::FMADD_RND";
20260 case X86ISD::FNMADD_RND: return "X86ISD::FNMADD_RND";
20261 case X86ISD::FMSUB_RND: return "X86ISD::FMSUB_RND";
20262 case X86ISD::FNMSUB_RND: return "X86ISD::FNMSUB_RND";
20263 case X86ISD::FMADDSUB_RND: return "X86ISD::FMADDSUB_RND";
20264 case X86ISD::FMSUBADD_RND: return "X86ISD::FMSUBADD_RND";
20265 case X86ISD::VRNDSCALE: return "X86ISD::VRNDSCALE";
20266 case X86ISD::VREDUCE: return "X86ISD::VREDUCE";
20267 case X86ISD::VGETMANT: return "X86ISD::VGETMANT";
20268 case X86ISD::PCMPESTRI: return "X86ISD::PCMPESTRI";
20269 case X86ISD::PCMPISTRI: return "X86ISD::PCMPISTRI";
20270 case X86ISD::XTEST: return "X86ISD::XTEST";
20271 case X86ISD::COMPRESS: return "X86ISD::COMPRESS";
20272 case X86ISD::EXPAND: return "X86ISD::EXPAND";
20273 case X86ISD::SELECT: return "X86ISD::SELECT";
20274 case X86ISD::ADDSUB: return "X86ISD::ADDSUB";
20275 case X86ISD::RCP28: return "X86ISD::RCP28";
20276 case X86ISD::EXP2: return "X86ISD::EXP2";
20277 case X86ISD::RSQRT28: return "X86ISD::RSQRT28";
20278 case X86ISD::FADD_RND: return "X86ISD::FADD_RND";
20279 case X86ISD::FSUB_RND: return "X86ISD::FSUB_RND";
20280 case X86ISD::FMUL_RND: return "X86ISD::FMUL_RND";
20281 case X86ISD::FDIV_RND: return "X86ISD::FDIV_RND";
20282 case X86ISD::FSQRT_RND: return "X86ISD::FSQRT_RND";
20283 case X86ISD::FGETEXP_RND: return "X86ISD::FGETEXP_RND";
20284 case X86ISD::SCALEF: return "X86ISD::SCALEF";
20285 case X86ISD::ADDS: return "X86ISD::ADDS";
20286 case X86ISD::SUBS: return "X86ISD::SUBS";
20287 case X86ISD::AVG: return "X86ISD::AVG";
20288 case X86ISD::MULHRS: return "X86ISD::MULHRS";
20289 case X86ISD::SINT_TO_FP_RND: return "X86ISD::SINT_TO_FP_RND";
20290 case X86ISD::UINT_TO_FP_RND: return "X86ISD::UINT_TO_FP_RND";
20291 case X86ISD::FP_TO_SINT_RND: return "X86ISD::FP_TO_SINT_RND";
20292 case X86ISD::FP_TO_UINT_RND: return "X86ISD::FP_TO_UINT_RND";
20293 case X86ISD::VFPCLASS: return "X86ISD::VFPCLASS";
20298 // isLegalAddressingMode - Return true if the addressing mode represented
20299 // by AM is legal for this target, for a load/store of the specified type.
20300 bool X86TargetLowering::isLegalAddressingMode(const DataLayout &DL,
20301 const AddrMode &AM, Type *Ty,
20302 unsigned AS) const {
20303 // X86 supports extremely general addressing modes.
20304 CodeModel::Model M = getTargetMachine().getCodeModel();
20305 Reloc::Model R = getTargetMachine().getRelocationModel();
20307 // X86 allows a sign-extended 32-bit immediate field as a displacement.
20308 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != nullptr))
20313 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
20315 // If a reference to this global requires an extra load, we can't fold it.
20316 if (isGlobalStubReference(GVFlags))
20319 // If BaseGV requires a register for the PIC base, we cannot also have a
20320 // BaseReg specified.
20321 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
20324 // If lower 4G is not available, then we must use rip-relative addressing.
20325 if ((M != CodeModel::Small || R != Reloc::Static) &&
20326 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
20330 switch (AM.Scale) {
20336 // These scales always work.
20341 // These scales are formed with basereg+scalereg. Only accept if there is
20346 default: // Other stuff never works.
20353 bool X86TargetLowering::isVectorShiftByScalarCheap(Type *Ty) const {
20354 unsigned Bits = Ty->getScalarSizeInBits();
20356 // 8-bit shifts are always expensive, but versions with a scalar amount aren't
20357 // particularly cheaper than those without.
20361 // On AVX2 there are new vpsllv[dq] instructions (and other shifts), that make
20362 // variable shifts just as cheap as scalar ones.
20363 if (Subtarget->hasInt256() && (Bits == 32 || Bits == 64))
20366 // Otherwise, it's significantly cheaper to shift by a scalar amount than by a
20367 // fully general vector.
20371 bool X86TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
20372 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
20374 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
20375 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
20376 return NumBits1 > NumBits2;
20379 bool X86TargetLowering::allowTruncateForTailCall(Type *Ty1, Type *Ty2) const {
20380 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
20383 if (!isTypeLegal(EVT::getEVT(Ty1)))
20386 assert(Ty1->getPrimitiveSizeInBits() <= 64 && "i128 is probably not a noop");
20388 // Assuming the caller doesn't have a zeroext or signext return parameter,
20389 // truncation all the way down to i1 is valid.
20393 bool X86TargetLowering::isLegalICmpImmediate(int64_t Imm) const {
20394 return isInt<32>(Imm);
20397 bool X86TargetLowering::isLegalAddImmediate(int64_t Imm) const {
20398 // Can also use sub to handle negated immediates.
20399 return isInt<32>(Imm);
20402 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
20403 if (!VT1.isInteger() || !VT2.isInteger())
20405 unsigned NumBits1 = VT1.getSizeInBits();
20406 unsigned NumBits2 = VT2.getSizeInBits();
20407 return NumBits1 > NumBits2;
20410 bool X86TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
20411 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
20412 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit();
20415 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
20416 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
20417 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
20420 bool X86TargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
20421 EVT VT1 = Val.getValueType();
20422 if (isZExtFree(VT1, VT2))
20425 if (Val.getOpcode() != ISD::LOAD)
20428 if (!VT1.isSimple() || !VT1.isInteger() ||
20429 !VT2.isSimple() || !VT2.isInteger())
20432 switch (VT1.getSimpleVT().SimpleTy) {
20437 // X86 has 8, 16, and 32-bit zero-extending loads.
20444 bool X86TargetLowering::isVectorLoadExtDesirable(SDValue) const { return true; }
20447 X86TargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
20448 if (!(Subtarget->hasFMA() || Subtarget->hasFMA4() || Subtarget->hasAVX512()))
20451 VT = VT.getScalarType();
20453 if (!VT.isSimple())
20456 switch (VT.getSimpleVT().SimpleTy) {
20467 bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
20468 // i16 instructions are longer (0x66 prefix) and potentially slower.
20469 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
20472 /// isShuffleMaskLegal - Targets can use this to indicate that they only
20473 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
20474 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
20475 /// are assumed to be legal.
20477 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
20479 if (!VT.isSimple())
20482 // Not for i1 vectors
20483 if (VT.getSimpleVT().getScalarType() == MVT::i1)
20486 // Very little shuffling can be done for 64-bit vectors right now.
20487 if (VT.getSimpleVT().getSizeInBits() == 64)
20490 // We only care that the types being shuffled are legal. The lowering can
20491 // handle any possible shuffle mask that results.
20492 return isTypeLegal(VT.getSimpleVT());
20496 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
20498 // Just delegate to the generic legality, clear masks aren't special.
20499 return isShuffleMaskLegal(Mask, VT);
20502 //===----------------------------------------------------------------------===//
20503 // X86 Scheduler Hooks
20504 //===----------------------------------------------------------------------===//
20506 /// Utility function to emit xbegin specifying the start of an RTM region.
20507 static MachineBasicBlock *EmitXBegin(MachineInstr *MI, MachineBasicBlock *MBB,
20508 const TargetInstrInfo *TII) {
20509 DebugLoc DL = MI->getDebugLoc();
20511 const BasicBlock *BB = MBB->getBasicBlock();
20512 MachineFunction::iterator I = ++MBB->getIterator();
20514 // For the v = xbegin(), we generate
20525 MachineBasicBlock *thisMBB = MBB;
20526 MachineFunction *MF = MBB->getParent();
20527 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
20528 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
20529 MF->insert(I, mainMBB);
20530 MF->insert(I, sinkMBB);
20532 // Transfer the remainder of BB and its successor edges to sinkMBB.
20533 sinkMBB->splice(sinkMBB->begin(), MBB,
20534 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
20535 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
20539 // # fallthrough to mainMBB
20540 // # abortion to sinkMBB
20541 BuildMI(thisMBB, DL, TII->get(X86::XBEGIN_4)).addMBB(sinkMBB);
20542 thisMBB->addSuccessor(mainMBB);
20543 thisMBB->addSuccessor(sinkMBB);
20547 BuildMI(mainMBB, DL, TII->get(X86::MOV32ri), X86::EAX).addImm(-1);
20548 mainMBB->addSuccessor(sinkMBB);
20551 // EAX is live into the sinkMBB
20552 sinkMBB->addLiveIn(X86::EAX);
20553 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
20554 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
20557 MI->eraseFromParent();
20561 // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
20562 // or XMM0_V32I8 in AVX all of this code can be replaced with that
20563 // in the .td file.
20564 static MachineBasicBlock *EmitPCMPSTRM(MachineInstr *MI, MachineBasicBlock *BB,
20565 const TargetInstrInfo *TII) {
20567 switch (MI->getOpcode()) {
20568 default: llvm_unreachable("illegal opcode!");
20569 case X86::PCMPISTRM128REG: Opc = X86::PCMPISTRM128rr; break;
20570 case X86::VPCMPISTRM128REG: Opc = X86::VPCMPISTRM128rr; break;
20571 case X86::PCMPISTRM128MEM: Opc = X86::PCMPISTRM128rm; break;
20572 case X86::VPCMPISTRM128MEM: Opc = X86::VPCMPISTRM128rm; break;
20573 case X86::PCMPESTRM128REG: Opc = X86::PCMPESTRM128rr; break;
20574 case X86::VPCMPESTRM128REG: Opc = X86::VPCMPESTRM128rr; break;
20575 case X86::PCMPESTRM128MEM: Opc = X86::PCMPESTRM128rm; break;
20576 case X86::VPCMPESTRM128MEM: Opc = X86::VPCMPESTRM128rm; break;
20579 DebugLoc dl = MI->getDebugLoc();
20580 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
20582 unsigned NumArgs = MI->getNumOperands();
20583 for (unsigned i = 1; i < NumArgs; ++i) {
20584 MachineOperand &Op = MI->getOperand(i);
20585 if (!(Op.isReg() && Op.isImplicit()))
20586 MIB.addOperand(Op);
20588 if (MI->hasOneMemOperand())
20589 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
20591 BuildMI(*BB, MI, dl,
20592 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
20593 .addReg(X86::XMM0);
20595 MI->eraseFromParent();
20599 // FIXME: Custom handling because TableGen doesn't support multiple implicit
20600 // defs in an instruction pattern
20601 static MachineBasicBlock *EmitPCMPSTRI(MachineInstr *MI, MachineBasicBlock *BB,
20602 const TargetInstrInfo *TII) {
20604 switch (MI->getOpcode()) {
20605 default: llvm_unreachable("illegal opcode!");
20606 case X86::PCMPISTRIREG: Opc = X86::PCMPISTRIrr; break;
20607 case X86::VPCMPISTRIREG: Opc = X86::VPCMPISTRIrr; break;
20608 case X86::PCMPISTRIMEM: Opc = X86::PCMPISTRIrm; break;
20609 case X86::VPCMPISTRIMEM: Opc = X86::VPCMPISTRIrm; break;
20610 case X86::PCMPESTRIREG: Opc = X86::PCMPESTRIrr; break;
20611 case X86::VPCMPESTRIREG: Opc = X86::VPCMPESTRIrr; break;
20612 case X86::PCMPESTRIMEM: Opc = X86::PCMPESTRIrm; break;
20613 case X86::VPCMPESTRIMEM: Opc = X86::VPCMPESTRIrm; break;
20616 DebugLoc dl = MI->getDebugLoc();
20617 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
20619 unsigned NumArgs = MI->getNumOperands(); // remove the results
20620 for (unsigned i = 1; i < NumArgs; ++i) {
20621 MachineOperand &Op = MI->getOperand(i);
20622 if (!(Op.isReg() && Op.isImplicit()))
20623 MIB.addOperand(Op);
20625 if (MI->hasOneMemOperand())
20626 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
20628 BuildMI(*BB, MI, dl,
20629 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
20632 MI->eraseFromParent();
20636 static MachineBasicBlock *EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB,
20637 const X86Subtarget *Subtarget) {
20638 DebugLoc dl = MI->getDebugLoc();
20639 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
20640 // Address into RAX/EAX, other two args into ECX, EDX.
20641 unsigned MemOpc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
20642 unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
20643 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg);
20644 for (int i = 0; i < X86::AddrNumOperands; ++i)
20645 MIB.addOperand(MI->getOperand(i));
20647 unsigned ValOps = X86::AddrNumOperands;
20648 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
20649 .addReg(MI->getOperand(ValOps).getReg());
20650 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EDX)
20651 .addReg(MI->getOperand(ValOps+1).getReg());
20653 // The instruction doesn't actually take any operands though.
20654 BuildMI(*BB, MI, dl, TII->get(X86::MONITORrrr));
20656 MI->eraseFromParent(); // The pseudo is gone now.
20660 MachineBasicBlock *
20661 X86TargetLowering::EmitVAARG64WithCustomInserter(MachineInstr *MI,
20662 MachineBasicBlock *MBB) const {
20663 // Emit va_arg instruction on X86-64.
20665 // Operands to this pseudo-instruction:
20666 // 0 ) Output : destination address (reg)
20667 // 1-5) Input : va_list address (addr, i64mem)
20668 // 6 ) ArgSize : Size (in bytes) of vararg type
20669 // 7 ) ArgMode : 0=overflow only, 1=use gp_offset, 2=use fp_offset
20670 // 8 ) Align : Alignment of type
20671 // 9 ) EFLAGS (implicit-def)
20673 assert(MI->getNumOperands() == 10 && "VAARG_64 should have 10 operands!");
20674 static_assert(X86::AddrNumOperands == 5,
20675 "VAARG_64 assumes 5 address operands");
20677 unsigned DestReg = MI->getOperand(0).getReg();
20678 MachineOperand &Base = MI->getOperand(1);
20679 MachineOperand &Scale = MI->getOperand(2);
20680 MachineOperand &Index = MI->getOperand(3);
20681 MachineOperand &Disp = MI->getOperand(4);
20682 MachineOperand &Segment = MI->getOperand(5);
20683 unsigned ArgSize = MI->getOperand(6).getImm();
20684 unsigned ArgMode = MI->getOperand(7).getImm();
20685 unsigned Align = MI->getOperand(8).getImm();
20687 // Memory Reference
20688 assert(MI->hasOneMemOperand() && "Expected VAARG_64 to have one memoperand");
20689 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
20690 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
20692 // Machine Information
20693 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
20694 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
20695 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64);
20696 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32);
20697 DebugLoc DL = MI->getDebugLoc();
20699 // struct va_list {
20702 // i64 overflow_area (address)
20703 // i64 reg_save_area (address)
20705 // sizeof(va_list) = 24
20706 // alignment(va_list) = 8
20708 unsigned TotalNumIntRegs = 6;
20709 unsigned TotalNumXMMRegs = 8;
20710 bool UseGPOffset = (ArgMode == 1);
20711 bool UseFPOffset = (ArgMode == 2);
20712 unsigned MaxOffset = TotalNumIntRegs * 8 +
20713 (UseFPOffset ? TotalNumXMMRegs * 16 : 0);
20715 /* Align ArgSize to a multiple of 8 */
20716 unsigned ArgSizeA8 = (ArgSize + 7) & ~7;
20717 bool NeedsAlign = (Align > 8);
20719 MachineBasicBlock *thisMBB = MBB;
20720 MachineBasicBlock *overflowMBB;
20721 MachineBasicBlock *offsetMBB;
20722 MachineBasicBlock *endMBB;
20724 unsigned OffsetDestReg = 0; // Argument address computed by offsetMBB
20725 unsigned OverflowDestReg = 0; // Argument address computed by overflowMBB
20726 unsigned OffsetReg = 0;
20728 if (!UseGPOffset && !UseFPOffset) {
20729 // If we only pull from the overflow region, we don't create a branch.
20730 // We don't need to alter control flow.
20731 OffsetDestReg = 0; // unused
20732 OverflowDestReg = DestReg;
20734 offsetMBB = nullptr;
20735 overflowMBB = thisMBB;
20738 // First emit code to check if gp_offset (or fp_offset) is below the bound.
20739 // If so, pull the argument from reg_save_area. (branch to offsetMBB)
20740 // If not, pull from overflow_area. (branch to overflowMBB)
20745 // offsetMBB overflowMBB
20750 // Registers for the PHI in endMBB
20751 OffsetDestReg = MRI.createVirtualRegister(AddrRegClass);
20752 OverflowDestReg = MRI.createVirtualRegister(AddrRegClass);
20754 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
20755 MachineFunction *MF = MBB->getParent();
20756 overflowMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20757 offsetMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20758 endMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20760 MachineFunction::iterator MBBIter = ++MBB->getIterator();
20762 // Insert the new basic blocks
20763 MF->insert(MBBIter, offsetMBB);
20764 MF->insert(MBBIter, overflowMBB);
20765 MF->insert(MBBIter, endMBB);
20767 // Transfer the remainder of MBB and its successor edges to endMBB.
20768 endMBB->splice(endMBB->begin(), thisMBB,
20769 std::next(MachineBasicBlock::iterator(MI)), thisMBB->end());
20770 endMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
20772 // Make offsetMBB and overflowMBB successors of thisMBB
20773 thisMBB->addSuccessor(offsetMBB);
20774 thisMBB->addSuccessor(overflowMBB);
20776 // endMBB is a successor of both offsetMBB and overflowMBB
20777 offsetMBB->addSuccessor(endMBB);
20778 overflowMBB->addSuccessor(endMBB);
20780 // Load the offset value into a register
20781 OffsetReg = MRI.createVirtualRegister(OffsetRegClass);
20782 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg)
20786 .addDisp(Disp, UseFPOffset ? 4 : 0)
20787 .addOperand(Segment)
20788 .setMemRefs(MMOBegin, MMOEnd);
20790 // Check if there is enough room left to pull this argument.
20791 BuildMI(thisMBB, DL, TII->get(X86::CMP32ri))
20793 .addImm(MaxOffset + 8 - ArgSizeA8);
20795 // Branch to "overflowMBB" if offset >= max
20796 // Fall through to "offsetMBB" otherwise
20797 BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE)))
20798 .addMBB(overflowMBB);
20801 // In offsetMBB, emit code to use the reg_save_area.
20803 assert(OffsetReg != 0);
20805 // Read the reg_save_area address.
20806 unsigned RegSaveReg = MRI.createVirtualRegister(AddrRegClass);
20807 BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg)
20812 .addOperand(Segment)
20813 .setMemRefs(MMOBegin, MMOEnd);
20815 // Zero-extend the offset
20816 unsigned OffsetReg64 = MRI.createVirtualRegister(AddrRegClass);
20817 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64)
20820 .addImm(X86::sub_32bit);
20822 // Add the offset to the reg_save_area to get the final address.
20823 BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg)
20824 .addReg(OffsetReg64)
20825 .addReg(RegSaveReg);
20827 // Compute the offset for the next argument
20828 unsigned NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass);
20829 BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg)
20831 .addImm(UseFPOffset ? 16 : 8);
20833 // Store it back into the va_list.
20834 BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr))
20838 .addDisp(Disp, UseFPOffset ? 4 : 0)
20839 .addOperand(Segment)
20840 .addReg(NextOffsetReg)
20841 .setMemRefs(MMOBegin, MMOEnd);
20844 BuildMI(offsetMBB, DL, TII->get(X86::JMP_1))
20849 // Emit code to use overflow area
20852 // Load the overflow_area address into a register.
20853 unsigned OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass);
20854 BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg)
20859 .addOperand(Segment)
20860 .setMemRefs(MMOBegin, MMOEnd);
20862 // If we need to align it, do so. Otherwise, just copy the address
20863 // to OverflowDestReg.
20865 // Align the overflow address
20866 assert((Align & (Align-1)) == 0 && "Alignment must be a power of 2");
20867 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass);
20869 // aligned_addr = (addr + (align-1)) & ~(align-1)
20870 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg)
20871 .addReg(OverflowAddrReg)
20874 BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg)
20876 .addImm(~(uint64_t)(Align-1));
20878 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg)
20879 .addReg(OverflowAddrReg);
20882 // Compute the next overflow address after this argument.
20883 // (the overflow address should be kept 8-byte aligned)
20884 unsigned NextAddrReg = MRI.createVirtualRegister(AddrRegClass);
20885 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg)
20886 .addReg(OverflowDestReg)
20887 .addImm(ArgSizeA8);
20889 // Store the new overflow address.
20890 BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr))
20895 .addOperand(Segment)
20896 .addReg(NextAddrReg)
20897 .setMemRefs(MMOBegin, MMOEnd);
20899 // If we branched, emit the PHI to the front of endMBB.
20901 BuildMI(*endMBB, endMBB->begin(), DL,
20902 TII->get(X86::PHI), DestReg)
20903 .addReg(OffsetDestReg).addMBB(offsetMBB)
20904 .addReg(OverflowDestReg).addMBB(overflowMBB);
20907 // Erase the pseudo instruction
20908 MI->eraseFromParent();
20913 MachineBasicBlock *
20914 X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
20916 MachineBasicBlock *MBB) const {
20917 // Emit code to save XMM registers to the stack. The ABI says that the
20918 // number of registers to save is given in %al, so it's theoretically
20919 // possible to do an indirect jump trick to avoid saving all of them,
20920 // however this code takes a simpler approach and just executes all
20921 // of the stores if %al is non-zero. It's less code, and it's probably
20922 // easier on the hardware branch predictor, and stores aren't all that
20923 // expensive anyway.
20925 // Create the new basic blocks. One block contains all the XMM stores,
20926 // and one block is the final destination regardless of whether any
20927 // stores were performed.
20928 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
20929 MachineFunction *F = MBB->getParent();
20930 MachineFunction::iterator MBBIter = ++MBB->getIterator();
20931 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB);
20932 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB);
20933 F->insert(MBBIter, XMMSaveMBB);
20934 F->insert(MBBIter, EndMBB);
20936 // Transfer the remainder of MBB and its successor edges to EndMBB.
20937 EndMBB->splice(EndMBB->begin(), MBB,
20938 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
20939 EndMBB->transferSuccessorsAndUpdatePHIs(MBB);
20941 // The original block will now fall through to the XMM save block.
20942 MBB->addSuccessor(XMMSaveMBB);
20943 // The XMMSaveMBB will fall through to the end block.
20944 XMMSaveMBB->addSuccessor(EndMBB);
20946 // Now add the instructions.
20947 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
20948 DebugLoc DL = MI->getDebugLoc();
20950 unsigned CountReg = MI->getOperand(0).getReg();
20951 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm();
20952 int64_t VarArgsFPOffset = MI->getOperand(2).getImm();
20954 if (!Subtarget->isCallingConvWin64(F->getFunction()->getCallingConv())) {
20955 // If %al is 0, branch around the XMM save block.
20956 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
20957 BuildMI(MBB, DL, TII->get(X86::JE_1)).addMBB(EndMBB);
20958 MBB->addSuccessor(EndMBB);
20961 // Make sure the last operand is EFLAGS, which gets clobbered by the branch
20962 // that was just emitted, but clearly shouldn't be "saved".
20963 assert((MI->getNumOperands() <= 3 ||
20964 !MI->getOperand(MI->getNumOperands() - 1).isReg() ||
20965 MI->getOperand(MI->getNumOperands() - 1).getReg() == X86::EFLAGS)
20966 && "Expected last argument to be EFLAGS");
20967 unsigned MOVOpc = Subtarget->hasFp256() ? X86::VMOVAPSmr : X86::MOVAPSmr;
20968 // In the XMM save block, save all the XMM argument registers.
20969 for (int i = 3, e = MI->getNumOperands() - 1; i != e; ++i) {
20970 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
20971 MachineMemOperand *MMO = F->getMachineMemOperand(
20972 MachinePointerInfo::getFixedStack(*F, RegSaveFrameIndex, Offset),
20973 MachineMemOperand::MOStore,
20974 /*Size=*/16, /*Align=*/16);
20975 BuildMI(XMMSaveMBB, DL, TII->get(MOVOpc))
20976 .addFrameIndex(RegSaveFrameIndex)
20977 .addImm(/*Scale=*/1)
20978 .addReg(/*IndexReg=*/0)
20979 .addImm(/*Disp=*/Offset)
20980 .addReg(/*Segment=*/0)
20981 .addReg(MI->getOperand(i).getReg())
20982 .addMemOperand(MMO);
20985 MI->eraseFromParent(); // The pseudo instruction is gone now.
20990 // The EFLAGS operand of SelectItr might be missing a kill marker
20991 // because there were multiple uses of EFLAGS, and ISel didn't know
20992 // which to mark. Figure out whether SelectItr should have had a
20993 // kill marker, and set it if it should. Returns the correct kill
20995 static bool checkAndUpdateEFLAGSKill(MachineBasicBlock::iterator SelectItr,
20996 MachineBasicBlock* BB,
20997 const TargetRegisterInfo* TRI) {
20998 // Scan forward through BB for a use/def of EFLAGS.
20999 MachineBasicBlock::iterator miI(std::next(SelectItr));
21000 for (MachineBasicBlock::iterator miE = BB->end(); miI != miE; ++miI) {
21001 const MachineInstr& mi = *miI;
21002 if (mi.readsRegister(X86::EFLAGS))
21004 if (mi.definesRegister(X86::EFLAGS))
21005 break; // Should have kill-flag - update below.
21008 // If we hit the end of the block, check whether EFLAGS is live into a
21010 if (miI == BB->end()) {
21011 for (MachineBasicBlock::succ_iterator sItr = BB->succ_begin(),
21012 sEnd = BB->succ_end();
21013 sItr != sEnd; ++sItr) {
21014 MachineBasicBlock* succ = *sItr;
21015 if (succ->isLiveIn(X86::EFLAGS))
21020 // We found a def, or hit the end of the basic block and EFLAGS wasn't live
21021 // out. SelectMI should have a kill flag on EFLAGS.
21022 SelectItr->addRegisterKilled(X86::EFLAGS, TRI);
21026 // Return true if it is OK for this CMOV pseudo-opcode to be cascaded
21027 // together with other CMOV pseudo-opcodes into a single basic-block with
21028 // conditional jump around it.
21029 static bool isCMOVPseudo(MachineInstr *MI) {
21030 switch (MI->getOpcode()) {
21031 case X86::CMOV_FR32:
21032 case X86::CMOV_FR64:
21033 case X86::CMOV_GR8:
21034 case X86::CMOV_GR16:
21035 case X86::CMOV_GR32:
21036 case X86::CMOV_RFP32:
21037 case X86::CMOV_RFP64:
21038 case X86::CMOV_RFP80:
21039 case X86::CMOV_V2F64:
21040 case X86::CMOV_V2I64:
21041 case X86::CMOV_V4F32:
21042 case X86::CMOV_V4F64:
21043 case X86::CMOV_V4I64:
21044 case X86::CMOV_V16F32:
21045 case X86::CMOV_V8F32:
21046 case X86::CMOV_V8F64:
21047 case X86::CMOV_V8I64:
21048 case X86::CMOV_V8I1:
21049 case X86::CMOV_V16I1:
21050 case X86::CMOV_V32I1:
21051 case X86::CMOV_V64I1:
21059 MachineBasicBlock *
21060 X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
21061 MachineBasicBlock *BB) const {
21062 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
21063 DebugLoc DL = MI->getDebugLoc();
21065 // To "insert" a SELECT_CC instruction, we actually have to insert the
21066 // diamond control-flow pattern. The incoming instruction knows the
21067 // destination vreg to set, the condition code register to branch on, the
21068 // true/false values to select between, and a branch opcode to use.
21069 const BasicBlock *LLVM_BB = BB->getBasicBlock();
21070 MachineFunction::iterator It = ++BB->getIterator();
21075 // cmpTY ccX, r1, r2
21077 // fallthrough --> copy0MBB
21078 MachineBasicBlock *thisMBB = BB;
21079 MachineFunction *F = BB->getParent();
21081 // This code lowers all pseudo-CMOV instructions. Generally it lowers these
21082 // as described above, by inserting a BB, and then making a PHI at the join
21083 // point to select the true and false operands of the CMOV in the PHI.
21085 // The code also handles two different cases of multiple CMOV opcodes
21089 // In this case, there are multiple CMOVs in a row, all which are based on
21090 // the same condition setting (or the exact opposite condition setting).
21091 // In this case we can lower all the CMOVs using a single inserted BB, and
21092 // then make a number of PHIs at the join point to model the CMOVs. The only
21093 // trickiness here, is that in a case like:
21095 // t2 = CMOV cond1 t1, f1
21096 // t3 = CMOV cond1 t2, f2
21098 // when rewriting this into PHIs, we have to perform some renaming on the
21099 // temps since you cannot have a PHI operand refer to a PHI result earlier
21100 // in the same block. The "simple" but wrong lowering would be:
21102 // t2 = PHI t1(BB1), f1(BB2)
21103 // t3 = PHI t2(BB1), f2(BB2)
21105 // but clearly t2 is not defined in BB1, so that is incorrect. The proper
21106 // renaming is to note that on the path through BB1, t2 is really just a
21107 // copy of t1, and do that renaming, properly generating:
21109 // t2 = PHI t1(BB1), f1(BB2)
21110 // t3 = PHI t1(BB1), f2(BB2)
21112 // Case 2, we lower cascaded CMOVs such as
21114 // (CMOV (CMOV F, T, cc1), T, cc2)
21116 // to two successives branches. For that, we look for another CMOV as the
21117 // following instruction.
21119 // Without this, we would add a PHI between the two jumps, which ends up
21120 // creating a few copies all around. For instance, for
21122 // (sitofp (zext (fcmp une)))
21124 // we would generate:
21126 // ucomiss %xmm1, %xmm0
21127 // movss <1.0f>, %xmm0
21128 // movaps %xmm0, %xmm1
21130 // xorps %xmm1, %xmm1
21133 // movaps %xmm1, %xmm0
21137 // because this custom-inserter would have generated:
21149 // A: X = ...; Y = ...
21151 // C: Z = PHI [X, A], [Y, B]
21153 // E: PHI [X, C], [Z, D]
21155 // If we lower both CMOVs in a single step, we can instead generate:
21167 // A: X = ...; Y = ...
21169 // E: PHI [X, A], [X, C], [Y, D]
21171 // Which, in our sitofp/fcmp example, gives us something like:
21173 // ucomiss %xmm1, %xmm0
21174 // movss <1.0f>, %xmm0
21177 // xorps %xmm0, %xmm0
21181 MachineInstr *CascadedCMOV = nullptr;
21182 MachineInstr *LastCMOV = MI;
21183 X86::CondCode CC = X86::CondCode(MI->getOperand(3).getImm());
21184 X86::CondCode OppCC = X86::GetOppositeBranchCondition(CC);
21185 MachineBasicBlock::iterator NextMIIt =
21186 std::next(MachineBasicBlock::iterator(MI));
21188 // Check for case 1, where there are multiple CMOVs with the same condition
21189 // first. Of the two cases of multiple CMOV lowerings, case 1 reduces the
21190 // number of jumps the most.
21192 if (isCMOVPseudo(MI)) {
21193 // See if we have a string of CMOVS with the same condition.
21194 while (NextMIIt != BB->end() &&
21195 isCMOVPseudo(NextMIIt) &&
21196 (NextMIIt->getOperand(3).getImm() == CC ||
21197 NextMIIt->getOperand(3).getImm() == OppCC)) {
21198 LastCMOV = &*NextMIIt;
21203 // This checks for case 2, but only do this if we didn't already find
21204 // case 1, as indicated by LastCMOV == MI.
21205 if (LastCMOV == MI &&
21206 NextMIIt != BB->end() && NextMIIt->getOpcode() == MI->getOpcode() &&
21207 NextMIIt->getOperand(2).getReg() == MI->getOperand(2).getReg() &&
21208 NextMIIt->getOperand(1).getReg() == MI->getOperand(0).getReg()) {
21209 CascadedCMOV = &*NextMIIt;
21212 MachineBasicBlock *jcc1MBB = nullptr;
21214 // If we have a cascaded CMOV, we lower it to two successive branches to
21215 // the same block. EFLAGS is used by both, so mark it as live in the second.
21216 if (CascadedCMOV) {
21217 jcc1MBB = F->CreateMachineBasicBlock(LLVM_BB);
21218 F->insert(It, jcc1MBB);
21219 jcc1MBB->addLiveIn(X86::EFLAGS);
21222 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
21223 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
21224 F->insert(It, copy0MBB);
21225 F->insert(It, sinkMBB);
21227 // If the EFLAGS register isn't dead in the terminator, then claim that it's
21228 // live into the sink and copy blocks.
21229 const TargetRegisterInfo *TRI = Subtarget->getRegisterInfo();
21231 MachineInstr *LastEFLAGSUser = CascadedCMOV ? CascadedCMOV : LastCMOV;
21232 if (!LastEFLAGSUser->killsRegister(X86::EFLAGS) &&
21233 !checkAndUpdateEFLAGSKill(LastEFLAGSUser, BB, TRI)) {
21234 copy0MBB->addLiveIn(X86::EFLAGS);
21235 sinkMBB->addLiveIn(X86::EFLAGS);
21238 // Transfer the remainder of BB and its successor edges to sinkMBB.
21239 sinkMBB->splice(sinkMBB->begin(), BB,
21240 std::next(MachineBasicBlock::iterator(LastCMOV)), BB->end());
21241 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
21243 // Add the true and fallthrough blocks as its successors.
21244 if (CascadedCMOV) {
21245 // The fallthrough block may be jcc1MBB, if we have a cascaded CMOV.
21246 BB->addSuccessor(jcc1MBB);
21248 // In that case, jcc1MBB will itself fallthrough the copy0MBB, and
21249 // jump to the sinkMBB.
21250 jcc1MBB->addSuccessor(copy0MBB);
21251 jcc1MBB->addSuccessor(sinkMBB);
21253 BB->addSuccessor(copy0MBB);
21256 // The true block target of the first (or only) branch is always sinkMBB.
21257 BB->addSuccessor(sinkMBB);
21259 // Create the conditional branch instruction.
21260 unsigned Opc = X86::GetCondBranchFromCond(CC);
21261 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
21263 if (CascadedCMOV) {
21264 unsigned Opc2 = X86::GetCondBranchFromCond(
21265 (X86::CondCode)CascadedCMOV->getOperand(3).getImm());
21266 BuildMI(jcc1MBB, DL, TII->get(Opc2)).addMBB(sinkMBB);
21270 // %FalseValue = ...
21271 // # fallthrough to sinkMBB
21272 copy0MBB->addSuccessor(sinkMBB);
21275 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
21277 MachineBasicBlock::iterator MIItBegin = MachineBasicBlock::iterator(MI);
21278 MachineBasicBlock::iterator MIItEnd =
21279 std::next(MachineBasicBlock::iterator(LastCMOV));
21280 MachineBasicBlock::iterator SinkInsertionPoint = sinkMBB->begin();
21281 DenseMap<unsigned, std::pair<unsigned, unsigned>> RegRewriteTable;
21282 MachineInstrBuilder MIB;
21284 // As we are creating the PHIs, we have to be careful if there is more than
21285 // one. Later CMOVs may reference the results of earlier CMOVs, but later
21286 // PHIs have to reference the individual true/false inputs from earlier PHIs.
21287 // That also means that PHI construction must work forward from earlier to
21288 // later, and that the code must maintain a mapping from earlier PHI's
21289 // destination registers, and the registers that went into the PHI.
21291 for (MachineBasicBlock::iterator MIIt = MIItBegin; MIIt != MIItEnd; ++MIIt) {
21292 unsigned DestReg = MIIt->getOperand(0).getReg();
21293 unsigned Op1Reg = MIIt->getOperand(1).getReg();
21294 unsigned Op2Reg = MIIt->getOperand(2).getReg();
21296 // If this CMOV we are generating is the opposite condition from
21297 // the jump we generated, then we have to swap the operands for the
21298 // PHI that is going to be generated.
21299 if (MIIt->getOperand(3).getImm() == OppCC)
21300 std::swap(Op1Reg, Op2Reg);
21302 if (RegRewriteTable.find(Op1Reg) != RegRewriteTable.end())
21303 Op1Reg = RegRewriteTable[Op1Reg].first;
21305 if (RegRewriteTable.find(Op2Reg) != RegRewriteTable.end())
21306 Op2Reg = RegRewriteTable[Op2Reg].second;
21308 MIB = BuildMI(*sinkMBB, SinkInsertionPoint, DL,
21309 TII->get(X86::PHI), DestReg)
21310 .addReg(Op1Reg).addMBB(copy0MBB)
21311 .addReg(Op2Reg).addMBB(thisMBB);
21313 // Add this PHI to the rewrite table.
21314 RegRewriteTable[DestReg] = std::make_pair(Op1Reg, Op2Reg);
21317 // If we have a cascaded CMOV, the second Jcc provides the same incoming
21318 // value as the first Jcc (the True operand of the SELECT_CC/CMOV nodes).
21319 if (CascadedCMOV) {
21320 MIB.addReg(MI->getOperand(2).getReg()).addMBB(jcc1MBB);
21321 // Copy the PHI result to the register defined by the second CMOV.
21322 BuildMI(*sinkMBB, std::next(MachineBasicBlock::iterator(MIB.getInstr())),
21323 DL, TII->get(TargetOpcode::COPY),
21324 CascadedCMOV->getOperand(0).getReg())
21325 .addReg(MI->getOperand(0).getReg());
21326 CascadedCMOV->eraseFromParent();
21329 // Now remove the CMOV(s).
21330 for (MachineBasicBlock::iterator MIIt = MIItBegin; MIIt != MIItEnd; )
21331 (MIIt++)->eraseFromParent();
21336 MachineBasicBlock *
21337 X86TargetLowering::EmitLoweredAtomicFP(MachineInstr *MI,
21338 MachineBasicBlock *BB) const {
21339 // Combine the following atomic floating-point modification pattern:
21340 // a.store(reg OP a.load(acquire), release)
21341 // Transform them into:
21342 // OPss (%gpr), %xmm
21343 // movss %xmm, (%gpr)
21344 // Or sd equivalent for 64-bit operations.
21346 switch (MI->getOpcode()) {
21347 default: llvm_unreachable("unexpected instr type for EmitLoweredAtomicFP");
21348 case X86::RELEASE_FADD32mr: MOp = X86::MOVSSmr; FOp = X86::ADDSSrm; break;
21349 case X86::RELEASE_FADD64mr: MOp = X86::MOVSDmr; FOp = X86::ADDSDrm; break;
21351 const X86InstrInfo *TII = Subtarget->getInstrInfo();
21352 DebugLoc DL = MI->getDebugLoc();
21353 MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
21354 MachineOperand MSrc = MI->getOperand(0);
21355 unsigned VSrc = MI->getOperand(5).getReg();
21356 const MachineOperand &Disp = MI->getOperand(3);
21357 MachineOperand ZeroDisp = MachineOperand::CreateImm(0);
21358 bool hasDisp = Disp.isGlobal() || Disp.isImm();
21359 if (hasDisp && MSrc.isReg())
21360 MSrc.setIsKill(false);
21361 MachineInstrBuilder MIM = BuildMI(*BB, MI, DL, TII->get(MOp))
21362 .addOperand(/*Base=*/MSrc)
21363 .addImm(/*Scale=*/1)
21364 .addReg(/*Index=*/0)
21365 .addDisp(hasDisp ? Disp : ZeroDisp, /*off=*/0)
21367 MachineInstr *MIO = BuildMI(*BB, (MachineInstr *)MIM, DL, TII->get(FOp),
21368 MRI.createVirtualRegister(MRI.getRegClass(VSrc)))
21370 .addOperand(/*Base=*/MSrc)
21371 .addImm(/*Scale=*/1)
21372 .addReg(/*Index=*/0)
21373 .addDisp(hasDisp ? Disp : ZeroDisp, /*off=*/0)
21374 .addReg(/*Segment=*/0);
21375 MIM.addReg(MIO->getOperand(0).getReg(), RegState::Kill);
21376 MI->eraseFromParent(); // The pseudo instruction is gone now.
21380 MachineBasicBlock *
21381 X86TargetLowering::EmitLoweredSegAlloca(MachineInstr *MI,
21382 MachineBasicBlock *BB) const {
21383 MachineFunction *MF = BB->getParent();
21384 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
21385 DebugLoc DL = MI->getDebugLoc();
21386 const BasicBlock *LLVM_BB = BB->getBasicBlock();
21388 assert(MF->shouldSplitStack());
21390 const bool Is64Bit = Subtarget->is64Bit();
21391 const bool IsLP64 = Subtarget->isTarget64BitLP64();
21393 const unsigned TlsReg = Is64Bit ? X86::FS : X86::GS;
21394 const unsigned TlsOffset = IsLP64 ? 0x70 : Is64Bit ? 0x40 : 0x30;
21397 // ... [Till the alloca]
21398 // If stacklet is not large enough, jump to mallocMBB
21401 // Allocate by subtracting from RSP
21402 // Jump to continueMBB
21405 // Allocate by call to runtime
21409 // [rest of original BB]
21412 MachineBasicBlock *mallocMBB = MF->CreateMachineBasicBlock(LLVM_BB);
21413 MachineBasicBlock *bumpMBB = MF->CreateMachineBasicBlock(LLVM_BB);
21414 MachineBasicBlock *continueMBB = MF->CreateMachineBasicBlock(LLVM_BB);
21416 MachineRegisterInfo &MRI = MF->getRegInfo();
21417 const TargetRegisterClass *AddrRegClass =
21418 getRegClassFor(getPointerTy(MF->getDataLayout()));
21420 unsigned mallocPtrVReg = MRI.createVirtualRegister(AddrRegClass),
21421 bumpSPPtrVReg = MRI.createVirtualRegister(AddrRegClass),
21422 tmpSPVReg = MRI.createVirtualRegister(AddrRegClass),
21423 SPLimitVReg = MRI.createVirtualRegister(AddrRegClass),
21424 sizeVReg = MI->getOperand(1).getReg(),
21425 physSPReg = IsLP64 || Subtarget->isTargetNaCl64() ? X86::RSP : X86::ESP;
21427 MachineFunction::iterator MBBIter = ++BB->getIterator();
21429 MF->insert(MBBIter, bumpMBB);
21430 MF->insert(MBBIter, mallocMBB);
21431 MF->insert(MBBIter, continueMBB);
21433 continueMBB->splice(continueMBB->begin(), BB,
21434 std::next(MachineBasicBlock::iterator(MI)), BB->end());
21435 continueMBB->transferSuccessorsAndUpdatePHIs(BB);
21437 // Add code to the main basic block to check if the stack limit has been hit,
21438 // and if so, jump to mallocMBB otherwise to bumpMBB.
21439 BuildMI(BB, DL, TII->get(TargetOpcode::COPY), tmpSPVReg).addReg(physSPReg);
21440 BuildMI(BB, DL, TII->get(IsLP64 ? X86::SUB64rr:X86::SUB32rr), SPLimitVReg)
21441 .addReg(tmpSPVReg).addReg(sizeVReg);
21442 BuildMI(BB, DL, TII->get(IsLP64 ? X86::CMP64mr:X86::CMP32mr))
21443 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg)
21444 .addReg(SPLimitVReg);
21445 BuildMI(BB, DL, TII->get(X86::JG_1)).addMBB(mallocMBB);
21447 // bumpMBB simply decreases the stack pointer, since we know the current
21448 // stacklet has enough space.
21449 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), physSPReg)
21450 .addReg(SPLimitVReg);
21451 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), bumpSPPtrVReg)
21452 .addReg(SPLimitVReg);
21453 BuildMI(bumpMBB, DL, TII->get(X86::JMP_1)).addMBB(continueMBB);
21455 // Calls into a routine in libgcc to allocate more space from the heap.
21456 const uint32_t *RegMask =
21457 Subtarget->getRegisterInfo()->getCallPreservedMask(*MF, CallingConv::C);
21459 BuildMI(mallocMBB, DL, TII->get(X86::MOV64rr), X86::RDI)
21461 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
21462 .addExternalSymbol("__morestack_allocate_stack_space")
21463 .addRegMask(RegMask)
21464 .addReg(X86::RDI, RegState::Implicit)
21465 .addReg(X86::RAX, RegState::ImplicitDefine);
21466 } else if (Is64Bit) {
21467 BuildMI(mallocMBB, DL, TII->get(X86::MOV32rr), X86::EDI)
21469 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
21470 .addExternalSymbol("__morestack_allocate_stack_space")
21471 .addRegMask(RegMask)
21472 .addReg(X86::EDI, RegState::Implicit)
21473 .addReg(X86::EAX, RegState::ImplicitDefine);
21475 BuildMI(mallocMBB, DL, TII->get(X86::SUB32ri), physSPReg).addReg(physSPReg)
21477 BuildMI(mallocMBB, DL, TII->get(X86::PUSH32r)).addReg(sizeVReg);
21478 BuildMI(mallocMBB, DL, TII->get(X86::CALLpcrel32))
21479 .addExternalSymbol("__morestack_allocate_stack_space")
21480 .addRegMask(RegMask)
21481 .addReg(X86::EAX, RegState::ImplicitDefine);
21485 BuildMI(mallocMBB, DL, TII->get(X86::ADD32ri), physSPReg).addReg(physSPReg)
21488 BuildMI(mallocMBB, DL, TII->get(TargetOpcode::COPY), mallocPtrVReg)
21489 .addReg(IsLP64 ? X86::RAX : X86::EAX);
21490 BuildMI(mallocMBB, DL, TII->get(X86::JMP_1)).addMBB(continueMBB);
21492 // Set up the CFG correctly.
21493 BB->addSuccessor(bumpMBB);
21494 BB->addSuccessor(mallocMBB);
21495 mallocMBB->addSuccessor(continueMBB);
21496 bumpMBB->addSuccessor(continueMBB);
21498 // Take care of the PHI nodes.
21499 BuildMI(*continueMBB, continueMBB->begin(), DL, TII->get(X86::PHI),
21500 MI->getOperand(0).getReg())
21501 .addReg(mallocPtrVReg).addMBB(mallocMBB)
21502 .addReg(bumpSPPtrVReg).addMBB(bumpMBB);
21504 // Delete the original pseudo instruction.
21505 MI->eraseFromParent();
21508 return continueMBB;
21511 MachineBasicBlock *
21512 X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI,
21513 MachineBasicBlock *BB) const {
21514 assert(!Subtarget->isTargetMachO());
21515 DebugLoc DL = MI->getDebugLoc();
21516 MachineInstr *ResumeMI = Subtarget->getFrameLowering()->emitStackProbe(
21517 *BB->getParent(), *BB, MI, DL, false);
21518 MachineBasicBlock *ResumeBB = ResumeMI->getParent();
21519 MI->eraseFromParent(); // The pseudo instruction is gone now.
21523 MachineBasicBlock *
21524 X86TargetLowering::EmitLoweredCatchRet(MachineInstr *MI,
21525 MachineBasicBlock *BB) const {
21526 MachineFunction *MF = BB->getParent();
21527 const TargetInstrInfo &TII = *Subtarget->getInstrInfo();
21528 MachineBasicBlock *TargetMBB = MI->getOperand(0).getMBB();
21529 DebugLoc DL = MI->getDebugLoc();
21531 assert(!isAsynchronousEHPersonality(
21532 classifyEHPersonality(MF->getFunction()->getPersonalityFn())) &&
21533 "SEH does not use catchret!");
21535 // Only 32-bit EH needs to worry about manually restoring stack pointers.
21536 if (!Subtarget->is32Bit())
21539 // C++ EH creates a new target block to hold the restore code, and wires up
21540 // the new block to the return destination with a normal JMP_4.
21541 MachineBasicBlock *RestoreMBB =
21542 MF->CreateMachineBasicBlock(BB->getBasicBlock());
21543 assert(BB->succ_size() == 1);
21544 MF->insert(std::next(BB->getIterator()), RestoreMBB);
21545 RestoreMBB->transferSuccessorsAndUpdatePHIs(BB);
21546 BB->addSuccessor(RestoreMBB);
21547 MI->getOperand(0).setMBB(RestoreMBB);
21549 auto RestoreMBBI = RestoreMBB->begin();
21550 BuildMI(*RestoreMBB, RestoreMBBI, DL, TII.get(X86::EH_RESTORE));
21551 BuildMI(*RestoreMBB, RestoreMBBI, DL, TII.get(X86::JMP_4)).addMBB(TargetMBB);
21555 MachineBasicBlock *
21556 X86TargetLowering::EmitLoweredCatchPad(MachineInstr *MI,
21557 MachineBasicBlock *BB) const {
21558 MachineFunction *MF = BB->getParent();
21559 const Constant *PerFn = MF->getFunction()->getPersonalityFn();
21560 bool IsSEH = isAsynchronousEHPersonality(classifyEHPersonality(PerFn));
21561 // Only 32-bit SEH requires special handling for catchpad.
21562 if (IsSEH && Subtarget->is32Bit()) {
21563 const TargetInstrInfo &TII = *Subtarget->getInstrInfo();
21564 DebugLoc DL = MI->getDebugLoc();
21565 BuildMI(*BB, MI, DL, TII.get(X86::EH_RESTORE));
21567 MI->eraseFromParent();
21571 MachineBasicBlock *
21572 X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI,
21573 MachineBasicBlock *BB) const {
21574 // This is pretty easy. We're taking the value that we received from
21575 // our load from the relocation, sticking it in either RDI (x86-64)
21576 // or EAX and doing an indirect call. The return value will then
21577 // be in the normal return register.
21578 MachineFunction *F = BB->getParent();
21579 const X86InstrInfo *TII = Subtarget->getInstrInfo();
21580 DebugLoc DL = MI->getDebugLoc();
21582 assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?");
21583 assert(MI->getOperand(3).isGlobal() && "This should be a global");
21585 // Get a register mask for the lowered call.
21586 // FIXME: The 32-bit calls have non-standard calling conventions. Use a
21587 // proper register mask.
21588 const uint32_t *RegMask =
21589 Subtarget->is64Bit() ?
21590 Subtarget->getRegisterInfo()->getDarwinTLSCallPreservedMask() :
21591 Subtarget->getRegisterInfo()->getCallPreservedMask(*F, CallingConv::C);
21592 if (Subtarget->is64Bit()) {
21593 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
21594 TII->get(X86::MOV64rm), X86::RDI)
21596 .addImm(0).addReg(0)
21597 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
21598 MI->getOperand(3).getTargetFlags())
21600 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m));
21601 addDirectMem(MIB, X86::RDI);
21602 MIB.addReg(X86::RAX, RegState::ImplicitDefine).addRegMask(RegMask);
21603 } else if (F->getTarget().getRelocationModel() != Reloc::PIC_) {
21604 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
21605 TII->get(X86::MOV32rm), X86::EAX)
21607 .addImm(0).addReg(0)
21608 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
21609 MI->getOperand(3).getTargetFlags())
21611 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
21612 addDirectMem(MIB, X86::EAX);
21613 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
21615 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
21616 TII->get(X86::MOV32rm), X86::EAX)
21617 .addReg(TII->getGlobalBaseReg(F))
21618 .addImm(0).addReg(0)
21619 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
21620 MI->getOperand(3).getTargetFlags())
21622 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
21623 addDirectMem(MIB, X86::EAX);
21624 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
21627 MI->eraseFromParent(); // The pseudo instruction is gone now.
21631 MachineBasicBlock *
21632 X86TargetLowering::emitEHSjLjSetJmp(MachineInstr *MI,
21633 MachineBasicBlock *MBB) const {
21634 DebugLoc DL = MI->getDebugLoc();
21635 MachineFunction *MF = MBB->getParent();
21636 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
21637 MachineRegisterInfo &MRI = MF->getRegInfo();
21639 const BasicBlock *BB = MBB->getBasicBlock();
21640 MachineFunction::iterator I = ++MBB->getIterator();
21642 // Memory Reference
21643 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
21644 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
21647 unsigned MemOpndSlot = 0;
21649 unsigned CurOp = 0;
21651 DstReg = MI->getOperand(CurOp++).getReg();
21652 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
21653 assert(RC->hasType(MVT::i32) && "Invalid destination!");
21654 unsigned mainDstReg = MRI.createVirtualRegister(RC);
21655 unsigned restoreDstReg = MRI.createVirtualRegister(RC);
21657 MemOpndSlot = CurOp;
21659 MVT PVT = getPointerTy(MF->getDataLayout());
21660 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
21661 "Invalid Pointer Size!");
21663 // For v = setjmp(buf), we generate
21666 // buf[LabelOffset] = restoreMBB <-- takes address of restoreMBB
21667 // SjLjSetup restoreMBB
21673 // v = phi(main, restore)
21676 // if base pointer being used, load it from frame
21679 MachineBasicBlock *thisMBB = MBB;
21680 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
21681 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
21682 MachineBasicBlock *restoreMBB = MF->CreateMachineBasicBlock(BB);
21683 MF->insert(I, mainMBB);
21684 MF->insert(I, sinkMBB);
21685 MF->push_back(restoreMBB);
21686 restoreMBB->setHasAddressTaken();
21688 MachineInstrBuilder MIB;
21690 // Transfer the remainder of BB and its successor edges to sinkMBB.
21691 sinkMBB->splice(sinkMBB->begin(), MBB,
21692 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
21693 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
21696 unsigned PtrStoreOpc = 0;
21697 unsigned LabelReg = 0;
21698 const int64_t LabelOffset = 1 * PVT.getStoreSize();
21699 Reloc::Model RM = MF->getTarget().getRelocationModel();
21700 bool UseImmLabel = (MF->getTarget().getCodeModel() == CodeModel::Small) &&
21701 (RM == Reloc::Static || RM == Reloc::DynamicNoPIC);
21703 // Prepare IP either in reg or imm.
21704 if (!UseImmLabel) {
21705 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mr : X86::MOV32mr;
21706 const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
21707 LabelReg = MRI.createVirtualRegister(PtrRC);
21708 if (Subtarget->is64Bit()) {
21709 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA64r), LabelReg)
21713 .addMBB(restoreMBB)
21716 const X86InstrInfo *XII = static_cast<const X86InstrInfo*>(TII);
21717 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA32r), LabelReg)
21718 .addReg(XII->getGlobalBaseReg(MF))
21721 .addMBB(restoreMBB, Subtarget->ClassifyBlockAddressReference())
21725 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mi32 : X86::MOV32mi;
21727 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PtrStoreOpc));
21728 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
21729 if (i == X86::AddrDisp)
21730 MIB.addDisp(MI->getOperand(MemOpndSlot + i), LabelOffset);
21732 MIB.addOperand(MI->getOperand(MemOpndSlot + i));
21735 MIB.addReg(LabelReg);
21737 MIB.addMBB(restoreMBB);
21738 MIB.setMemRefs(MMOBegin, MMOEnd);
21740 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::EH_SjLj_Setup))
21741 .addMBB(restoreMBB);
21743 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
21744 MIB.addRegMask(RegInfo->getNoPreservedMask());
21745 thisMBB->addSuccessor(mainMBB);
21746 thisMBB->addSuccessor(restoreMBB);
21750 BuildMI(mainMBB, DL, TII->get(X86::MOV32r0), mainDstReg);
21751 mainMBB->addSuccessor(sinkMBB);
21754 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
21755 TII->get(X86::PHI), DstReg)
21756 .addReg(mainDstReg).addMBB(mainMBB)
21757 .addReg(restoreDstReg).addMBB(restoreMBB);
21760 if (RegInfo->hasBasePointer(*MF)) {
21761 const bool Uses64BitFramePtr =
21762 Subtarget->isTarget64BitLP64() || Subtarget->isTargetNaCl64();
21763 X86MachineFunctionInfo *X86FI = MF->getInfo<X86MachineFunctionInfo>();
21764 X86FI->setRestoreBasePointer(MF);
21765 unsigned FramePtr = RegInfo->getFrameRegister(*MF);
21766 unsigned BasePtr = RegInfo->getBaseRegister();
21767 unsigned Opm = Uses64BitFramePtr ? X86::MOV64rm : X86::MOV32rm;
21768 addRegOffset(BuildMI(restoreMBB, DL, TII->get(Opm), BasePtr),
21769 FramePtr, true, X86FI->getRestoreBasePointerOffset())
21770 .setMIFlag(MachineInstr::FrameSetup);
21772 BuildMI(restoreMBB, DL, TII->get(X86::MOV32ri), restoreDstReg).addImm(1);
21773 BuildMI(restoreMBB, DL, TII->get(X86::JMP_1)).addMBB(sinkMBB);
21774 restoreMBB->addSuccessor(sinkMBB);
21776 MI->eraseFromParent();
21780 MachineBasicBlock *
21781 X86TargetLowering::emitEHSjLjLongJmp(MachineInstr *MI,
21782 MachineBasicBlock *MBB) const {
21783 DebugLoc DL = MI->getDebugLoc();
21784 MachineFunction *MF = MBB->getParent();
21785 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
21786 MachineRegisterInfo &MRI = MF->getRegInfo();
21788 // Memory Reference
21789 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
21790 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
21792 MVT PVT = getPointerTy(MF->getDataLayout());
21793 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
21794 "Invalid Pointer Size!");
21796 const TargetRegisterClass *RC =
21797 (PVT == MVT::i64) ? &X86::GR64RegClass : &X86::GR32RegClass;
21798 unsigned Tmp = MRI.createVirtualRegister(RC);
21799 // Since FP is only updated here but NOT referenced, it's treated as GPR.
21800 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
21801 unsigned FP = (PVT == MVT::i64) ? X86::RBP : X86::EBP;
21802 unsigned SP = RegInfo->getStackRegister();
21804 MachineInstrBuilder MIB;
21806 const int64_t LabelOffset = 1 * PVT.getStoreSize();
21807 const int64_t SPOffset = 2 * PVT.getStoreSize();
21809 unsigned PtrLoadOpc = (PVT == MVT::i64) ? X86::MOV64rm : X86::MOV32rm;
21810 unsigned IJmpOpc = (PVT == MVT::i64) ? X86::JMP64r : X86::JMP32r;
21813 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), FP);
21814 for (unsigned i = 0; i < X86::AddrNumOperands; ++i)
21815 MIB.addOperand(MI->getOperand(i));
21816 MIB.setMemRefs(MMOBegin, MMOEnd);
21818 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), Tmp);
21819 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
21820 if (i == X86::AddrDisp)
21821 MIB.addDisp(MI->getOperand(i), LabelOffset);
21823 MIB.addOperand(MI->getOperand(i));
21825 MIB.setMemRefs(MMOBegin, MMOEnd);
21827 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), SP);
21828 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
21829 if (i == X86::AddrDisp)
21830 MIB.addDisp(MI->getOperand(i), SPOffset);
21832 MIB.addOperand(MI->getOperand(i));
21834 MIB.setMemRefs(MMOBegin, MMOEnd);
21836 BuildMI(*MBB, MI, DL, TII->get(IJmpOpc)).addReg(Tmp);
21838 MI->eraseFromParent();
21842 // Replace 213-type (isel default) FMA3 instructions with 231-type for
21843 // accumulator loops. Writing back to the accumulator allows the coalescer
21844 // to remove extra copies in the loop.
21845 // FIXME: Do this on AVX512. We don't support 231 variants yet (PR23937).
21846 MachineBasicBlock *
21847 X86TargetLowering::emitFMA3Instr(MachineInstr *MI,
21848 MachineBasicBlock *MBB) const {
21849 MachineOperand &AddendOp = MI->getOperand(3);
21851 // Bail out early if the addend isn't a register - we can't switch these.
21852 if (!AddendOp.isReg())
21855 MachineFunction &MF = *MBB->getParent();
21856 MachineRegisterInfo &MRI = MF.getRegInfo();
21858 // Check whether the addend is defined by a PHI:
21859 assert(MRI.hasOneDef(AddendOp.getReg()) && "Multiple defs in SSA?");
21860 MachineInstr &AddendDef = *MRI.def_instr_begin(AddendOp.getReg());
21861 if (!AddendDef.isPHI())
21864 // Look for the following pattern:
21866 // %addend = phi [%entry, 0], [%loop, %result]
21868 // %result<tied1> = FMA213 %m2<tied0>, %m1, %addend
21872 // %addend = phi [%entry, 0], [%loop, %result]
21874 // %result<tied1> = FMA231 %addend<tied0>, %m1, %m2
21876 for (unsigned i = 1, e = AddendDef.getNumOperands(); i < e; i += 2) {
21877 assert(AddendDef.getOperand(i).isReg());
21878 MachineOperand PHISrcOp = AddendDef.getOperand(i);
21879 MachineInstr &PHISrcInst = *MRI.def_instr_begin(PHISrcOp.getReg());
21880 if (&PHISrcInst == MI) {
21881 // Found a matching instruction.
21882 unsigned NewFMAOpc = 0;
21883 switch (MI->getOpcode()) {
21884 case X86::VFMADDPDr213r: NewFMAOpc = X86::VFMADDPDr231r; break;
21885 case X86::VFMADDPSr213r: NewFMAOpc = X86::VFMADDPSr231r; break;
21886 case X86::VFMADDSDr213r: NewFMAOpc = X86::VFMADDSDr231r; break;
21887 case X86::VFMADDSSr213r: NewFMAOpc = X86::VFMADDSSr231r; break;
21888 case X86::VFMSUBPDr213r: NewFMAOpc = X86::VFMSUBPDr231r; break;
21889 case X86::VFMSUBPSr213r: NewFMAOpc = X86::VFMSUBPSr231r; break;
21890 case X86::VFMSUBSDr213r: NewFMAOpc = X86::VFMSUBSDr231r; break;
21891 case X86::VFMSUBSSr213r: NewFMAOpc = X86::VFMSUBSSr231r; break;
21892 case X86::VFNMADDPDr213r: NewFMAOpc = X86::VFNMADDPDr231r; break;
21893 case X86::VFNMADDPSr213r: NewFMAOpc = X86::VFNMADDPSr231r; break;
21894 case X86::VFNMADDSDr213r: NewFMAOpc = X86::VFNMADDSDr231r; break;
21895 case X86::VFNMADDSSr213r: NewFMAOpc = X86::VFNMADDSSr231r; break;
21896 case X86::VFNMSUBPDr213r: NewFMAOpc = X86::VFNMSUBPDr231r; break;
21897 case X86::VFNMSUBPSr213r: NewFMAOpc = X86::VFNMSUBPSr231r; break;
21898 case X86::VFNMSUBSDr213r: NewFMAOpc = X86::VFNMSUBSDr231r; break;
21899 case X86::VFNMSUBSSr213r: NewFMAOpc = X86::VFNMSUBSSr231r; break;
21900 case X86::VFMADDSUBPDr213r: NewFMAOpc = X86::VFMADDSUBPDr231r; break;
21901 case X86::VFMADDSUBPSr213r: NewFMAOpc = X86::VFMADDSUBPSr231r; break;
21902 case X86::VFMSUBADDPDr213r: NewFMAOpc = X86::VFMSUBADDPDr231r; break;
21903 case X86::VFMSUBADDPSr213r: NewFMAOpc = X86::VFMSUBADDPSr231r; break;
21905 case X86::VFMADDPDr213rY: NewFMAOpc = X86::VFMADDPDr231rY; break;
21906 case X86::VFMADDPSr213rY: NewFMAOpc = X86::VFMADDPSr231rY; break;
21907 case X86::VFMSUBPDr213rY: NewFMAOpc = X86::VFMSUBPDr231rY; break;
21908 case X86::VFMSUBPSr213rY: NewFMAOpc = X86::VFMSUBPSr231rY; break;
21909 case X86::VFNMADDPDr213rY: NewFMAOpc = X86::VFNMADDPDr231rY; break;
21910 case X86::VFNMADDPSr213rY: NewFMAOpc = X86::VFNMADDPSr231rY; break;
21911 case X86::VFNMSUBPDr213rY: NewFMAOpc = X86::VFNMSUBPDr231rY; break;
21912 case X86::VFNMSUBPSr213rY: NewFMAOpc = X86::VFNMSUBPSr231rY; break;
21913 case X86::VFMADDSUBPDr213rY: NewFMAOpc = X86::VFMADDSUBPDr231rY; break;
21914 case X86::VFMADDSUBPSr213rY: NewFMAOpc = X86::VFMADDSUBPSr231rY; break;
21915 case X86::VFMSUBADDPDr213rY: NewFMAOpc = X86::VFMSUBADDPDr231rY; break;
21916 case X86::VFMSUBADDPSr213rY: NewFMAOpc = X86::VFMSUBADDPSr231rY; break;
21917 default: llvm_unreachable("Unrecognized FMA variant.");
21920 const TargetInstrInfo &TII = *Subtarget->getInstrInfo();
21921 MachineInstrBuilder MIB =
21922 BuildMI(MF, MI->getDebugLoc(), TII.get(NewFMAOpc))
21923 .addOperand(MI->getOperand(0))
21924 .addOperand(MI->getOperand(3))
21925 .addOperand(MI->getOperand(2))
21926 .addOperand(MI->getOperand(1));
21927 MBB->insert(MachineBasicBlock::iterator(MI), MIB);
21928 MI->eraseFromParent();
21935 MachineBasicBlock *
21936 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
21937 MachineBasicBlock *BB) const {
21938 switch (MI->getOpcode()) {
21939 default: llvm_unreachable("Unexpected instr type to insert");
21940 case X86::TAILJMPd64:
21941 case X86::TAILJMPr64:
21942 case X86::TAILJMPm64:
21943 case X86::TAILJMPd64_REX:
21944 case X86::TAILJMPr64_REX:
21945 case X86::TAILJMPm64_REX:
21946 llvm_unreachable("TAILJMP64 would not be touched here.");
21947 case X86::TCRETURNdi64:
21948 case X86::TCRETURNri64:
21949 case X86::TCRETURNmi64:
21951 case X86::WIN_ALLOCA:
21952 return EmitLoweredWinAlloca(MI, BB);
21953 case X86::CATCHRET:
21954 return EmitLoweredCatchRet(MI, BB);
21955 case X86::CATCHPAD:
21956 return EmitLoweredCatchPad(MI, BB);
21957 case X86::SEG_ALLOCA_32:
21958 case X86::SEG_ALLOCA_64:
21959 return EmitLoweredSegAlloca(MI, BB);
21960 case X86::TLSCall_32:
21961 case X86::TLSCall_64:
21962 return EmitLoweredTLSCall(MI, BB);
21963 case X86::CMOV_FR32:
21964 case X86::CMOV_FR64:
21965 case X86::CMOV_GR8:
21966 case X86::CMOV_GR16:
21967 case X86::CMOV_GR32:
21968 case X86::CMOV_RFP32:
21969 case X86::CMOV_RFP64:
21970 case X86::CMOV_RFP80:
21971 case X86::CMOV_V2F64:
21972 case X86::CMOV_V2I64:
21973 case X86::CMOV_V4F32:
21974 case X86::CMOV_V4F64:
21975 case X86::CMOV_V4I64:
21976 case X86::CMOV_V16F32:
21977 case X86::CMOV_V8F32:
21978 case X86::CMOV_V8F64:
21979 case X86::CMOV_V8I64:
21980 case X86::CMOV_V8I1:
21981 case X86::CMOV_V16I1:
21982 case X86::CMOV_V32I1:
21983 case X86::CMOV_V64I1:
21984 return EmitLoweredSelect(MI, BB);
21986 case X86::RELEASE_FADD32mr:
21987 case X86::RELEASE_FADD64mr:
21988 return EmitLoweredAtomicFP(MI, BB);
21990 case X86::FP32_TO_INT16_IN_MEM:
21991 case X86::FP32_TO_INT32_IN_MEM:
21992 case X86::FP32_TO_INT64_IN_MEM:
21993 case X86::FP64_TO_INT16_IN_MEM:
21994 case X86::FP64_TO_INT32_IN_MEM:
21995 case X86::FP64_TO_INT64_IN_MEM:
21996 case X86::FP80_TO_INT16_IN_MEM:
21997 case X86::FP80_TO_INT32_IN_MEM:
21998 case X86::FP80_TO_INT64_IN_MEM: {
21999 MachineFunction *F = BB->getParent();
22000 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
22001 DebugLoc DL = MI->getDebugLoc();
22003 // Change the floating point control register to use "round towards zero"
22004 // mode when truncating to an integer value.
22005 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false);
22006 addFrameReference(BuildMI(*BB, MI, DL,
22007 TII->get(X86::FNSTCW16m)), CWFrameIdx);
22009 // Load the old value of the high byte of the control word...
22011 F->getRegInfo().createVirtualRegister(&X86::GR16RegClass);
22012 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW),
22015 // Set the high part to be round to zero...
22016 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
22019 // Reload the modified control word now...
22020 addFrameReference(BuildMI(*BB, MI, DL,
22021 TII->get(X86::FLDCW16m)), CWFrameIdx);
22023 // Restore the memory image of control word to original value
22024 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
22027 // Get the X86 opcode to use.
22029 switch (MI->getOpcode()) {
22030 default: llvm_unreachable("illegal opcode!");
22031 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
22032 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
22033 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
22034 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
22035 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
22036 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
22037 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
22038 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
22039 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
22043 MachineOperand &Op = MI->getOperand(0);
22045 AM.BaseType = X86AddressMode::RegBase;
22046 AM.Base.Reg = Op.getReg();
22048 AM.BaseType = X86AddressMode::FrameIndexBase;
22049 AM.Base.FrameIndex = Op.getIndex();
22051 Op = MI->getOperand(1);
22053 AM.Scale = Op.getImm();
22054 Op = MI->getOperand(2);
22056 AM.IndexReg = Op.getImm();
22057 Op = MI->getOperand(3);
22058 if (Op.isGlobal()) {
22059 AM.GV = Op.getGlobal();
22061 AM.Disp = Op.getImm();
22063 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM)
22064 .addReg(MI->getOperand(X86::AddrNumOperands).getReg());
22066 // Reload the original control word now.
22067 addFrameReference(BuildMI(*BB, MI, DL,
22068 TII->get(X86::FLDCW16m)), CWFrameIdx);
22070 MI->eraseFromParent(); // The pseudo instruction is gone now.
22073 // String/text processing lowering.
22074 case X86::PCMPISTRM128REG:
22075 case X86::VPCMPISTRM128REG:
22076 case X86::PCMPISTRM128MEM:
22077 case X86::VPCMPISTRM128MEM:
22078 case X86::PCMPESTRM128REG:
22079 case X86::VPCMPESTRM128REG:
22080 case X86::PCMPESTRM128MEM:
22081 case X86::VPCMPESTRM128MEM:
22082 assert(Subtarget->hasSSE42() &&
22083 "Target must have SSE4.2 or AVX features enabled");
22084 return EmitPCMPSTRM(MI, BB, Subtarget->getInstrInfo());
22086 // String/text processing lowering.
22087 case X86::PCMPISTRIREG:
22088 case X86::VPCMPISTRIREG:
22089 case X86::PCMPISTRIMEM:
22090 case X86::VPCMPISTRIMEM:
22091 case X86::PCMPESTRIREG:
22092 case X86::VPCMPESTRIREG:
22093 case X86::PCMPESTRIMEM:
22094 case X86::VPCMPESTRIMEM:
22095 assert(Subtarget->hasSSE42() &&
22096 "Target must have SSE4.2 or AVX features enabled");
22097 return EmitPCMPSTRI(MI, BB, Subtarget->getInstrInfo());
22099 // Thread synchronization.
22101 return EmitMonitor(MI, BB, Subtarget);
22105 return EmitXBegin(MI, BB, Subtarget->getInstrInfo());
22107 case X86::VASTART_SAVE_XMM_REGS:
22108 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
22110 case X86::VAARG_64:
22111 return EmitVAARG64WithCustomInserter(MI, BB);
22113 case X86::EH_SjLj_SetJmp32:
22114 case X86::EH_SjLj_SetJmp64:
22115 return emitEHSjLjSetJmp(MI, BB);
22117 case X86::EH_SjLj_LongJmp32:
22118 case X86::EH_SjLj_LongJmp64:
22119 return emitEHSjLjLongJmp(MI, BB);
22121 case TargetOpcode::STATEPOINT:
22122 // As an implementation detail, STATEPOINT shares the STACKMAP format at
22123 // this point in the process. We diverge later.
22124 return emitPatchPoint(MI, BB);
22126 case TargetOpcode::STACKMAP:
22127 case TargetOpcode::PATCHPOINT:
22128 return emitPatchPoint(MI, BB);
22130 case X86::VFMADDPDr213r:
22131 case X86::VFMADDPSr213r:
22132 case X86::VFMADDSDr213r:
22133 case X86::VFMADDSSr213r:
22134 case X86::VFMSUBPDr213r:
22135 case X86::VFMSUBPSr213r:
22136 case X86::VFMSUBSDr213r:
22137 case X86::VFMSUBSSr213r:
22138 case X86::VFNMADDPDr213r:
22139 case X86::VFNMADDPSr213r:
22140 case X86::VFNMADDSDr213r:
22141 case X86::VFNMADDSSr213r:
22142 case X86::VFNMSUBPDr213r:
22143 case X86::VFNMSUBPSr213r:
22144 case X86::VFNMSUBSDr213r:
22145 case X86::VFNMSUBSSr213r:
22146 case X86::VFMADDSUBPDr213r:
22147 case X86::VFMADDSUBPSr213r:
22148 case X86::VFMSUBADDPDr213r:
22149 case X86::VFMSUBADDPSr213r:
22150 case X86::VFMADDPDr213rY:
22151 case X86::VFMADDPSr213rY:
22152 case X86::VFMSUBPDr213rY:
22153 case X86::VFMSUBPSr213rY:
22154 case X86::VFNMADDPDr213rY:
22155 case X86::VFNMADDPSr213rY:
22156 case X86::VFNMSUBPDr213rY:
22157 case X86::VFNMSUBPSr213rY:
22158 case X86::VFMADDSUBPDr213rY:
22159 case X86::VFMADDSUBPSr213rY:
22160 case X86::VFMSUBADDPDr213rY:
22161 case X86::VFMSUBADDPSr213rY:
22162 return emitFMA3Instr(MI, BB);
22166 //===----------------------------------------------------------------------===//
22167 // X86 Optimization Hooks
22168 //===----------------------------------------------------------------------===//
22170 void X86TargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
22173 const SelectionDAG &DAG,
22174 unsigned Depth) const {
22175 unsigned BitWidth = KnownZero.getBitWidth();
22176 unsigned Opc = Op.getOpcode();
22177 assert((Opc >= ISD::BUILTIN_OP_END ||
22178 Opc == ISD::INTRINSIC_WO_CHAIN ||
22179 Opc == ISD::INTRINSIC_W_CHAIN ||
22180 Opc == ISD::INTRINSIC_VOID) &&
22181 "Should use MaskedValueIsZero if you don't know whether Op"
22182 " is a target node!");
22184 KnownZero = KnownOne = APInt(BitWidth, 0); // Don't know anything.
22198 // These nodes' second result is a boolean.
22199 if (Op.getResNo() == 0)
22202 case X86ISD::SETCC:
22203 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1);
22205 case ISD::INTRINSIC_WO_CHAIN: {
22206 unsigned IntId = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
22207 unsigned NumLoBits = 0;
22210 case Intrinsic::x86_sse_movmsk_ps:
22211 case Intrinsic::x86_avx_movmsk_ps_256:
22212 case Intrinsic::x86_sse2_movmsk_pd:
22213 case Intrinsic::x86_avx_movmsk_pd_256:
22214 case Intrinsic::x86_mmx_pmovmskb:
22215 case Intrinsic::x86_sse2_pmovmskb_128:
22216 case Intrinsic::x86_avx2_pmovmskb: {
22217 // High bits of movmskp{s|d}, pmovmskb are known zero.
22219 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
22220 case Intrinsic::x86_sse_movmsk_ps: NumLoBits = 4; break;
22221 case Intrinsic::x86_avx_movmsk_ps_256: NumLoBits = 8; break;
22222 case Intrinsic::x86_sse2_movmsk_pd: NumLoBits = 2; break;
22223 case Intrinsic::x86_avx_movmsk_pd_256: NumLoBits = 4; break;
22224 case Intrinsic::x86_mmx_pmovmskb: NumLoBits = 8; break;
22225 case Intrinsic::x86_sse2_pmovmskb_128: NumLoBits = 16; break;
22226 case Intrinsic::x86_avx2_pmovmskb: NumLoBits = 32; break;
22228 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - NumLoBits);
22237 unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(
22239 const SelectionDAG &,
22240 unsigned Depth) const {
22241 // SETCC_CARRY sets the dest to ~0 for true or 0 for false.
22242 if (Op.getOpcode() == X86ISD::SETCC_CARRY)
22243 return Op.getValueType().getScalarSizeInBits();
22249 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
22250 /// node is a GlobalAddress + offset.
22251 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
22252 const GlobalValue* &GA,
22253 int64_t &Offset) const {
22254 if (N->getOpcode() == X86ISD::Wrapper) {
22255 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
22256 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
22257 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
22261 return TargetLowering::isGAPlusOffset(N, GA, Offset);
22264 /// isShuffleHigh128VectorInsertLow - Checks whether the shuffle node is the
22265 /// same as extracting the high 128-bit part of 256-bit vector and then
22266 /// inserting the result into the low part of a new 256-bit vector
22267 static bool isShuffleHigh128VectorInsertLow(ShuffleVectorSDNode *SVOp) {
22268 EVT VT = SVOp->getValueType(0);
22269 unsigned NumElems = VT.getVectorNumElements();
22271 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
22272 for (unsigned i = 0, j = NumElems/2; i != NumElems/2; ++i, ++j)
22273 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
22274 SVOp->getMaskElt(j) >= 0)
22280 /// isShuffleLow128VectorInsertHigh - Checks whether the shuffle node is the
22281 /// same as extracting the low 128-bit part of 256-bit vector and then
22282 /// inserting the result into the high part of a new 256-bit vector
22283 static bool isShuffleLow128VectorInsertHigh(ShuffleVectorSDNode *SVOp) {
22284 EVT VT = SVOp->getValueType(0);
22285 unsigned NumElems = VT.getVectorNumElements();
22287 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
22288 for (unsigned i = NumElems/2, j = 0; i != NumElems; ++i, ++j)
22289 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
22290 SVOp->getMaskElt(j) >= 0)
22296 /// PerformShuffleCombine256 - Performs shuffle combines for 256-bit vectors.
22297 static SDValue PerformShuffleCombine256(SDNode *N, SelectionDAG &DAG,
22298 TargetLowering::DAGCombinerInfo &DCI,
22299 const X86Subtarget* Subtarget) {
22301 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
22302 SDValue V1 = SVOp->getOperand(0);
22303 SDValue V2 = SVOp->getOperand(1);
22304 EVT VT = SVOp->getValueType(0);
22305 unsigned NumElems = VT.getVectorNumElements();
22307 if (V1.getOpcode() == ISD::CONCAT_VECTORS &&
22308 V2.getOpcode() == ISD::CONCAT_VECTORS) {
22312 // V UNDEF BUILD_VECTOR UNDEF
22314 // CONCAT_VECTOR CONCAT_VECTOR
22317 // RESULT: V + zero extended
22319 if (V2.getOperand(0).getOpcode() != ISD::BUILD_VECTOR ||
22320 V2.getOperand(1).getOpcode() != ISD::UNDEF ||
22321 V1.getOperand(1).getOpcode() != ISD::UNDEF)
22324 if (!ISD::isBuildVectorAllZeros(V2.getOperand(0).getNode()))
22327 // To match the shuffle mask, the first half of the mask should
22328 // be exactly the first vector, and all the rest a splat with the
22329 // first element of the second one.
22330 for (unsigned i = 0; i != NumElems/2; ++i)
22331 if (!isUndefOrEqual(SVOp->getMaskElt(i), i) ||
22332 !isUndefOrEqual(SVOp->getMaskElt(i+NumElems/2), NumElems))
22335 // If V1 is coming from a vector load then just fold to a VZEXT_LOAD.
22336 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(V1.getOperand(0))) {
22337 if (Ld->hasNUsesOfValue(1, 0)) {
22338 SDVTList Tys = DAG.getVTList(MVT::v4i64, MVT::Other);
22339 SDValue Ops[] = { Ld->getChain(), Ld->getBasePtr() };
22341 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops,
22343 Ld->getPointerInfo(),
22344 Ld->getAlignment(),
22345 false/*isVolatile*/, true/*ReadMem*/,
22346 false/*WriteMem*/);
22348 // Make sure the newly-created LOAD is in the same position as Ld in
22349 // terms of dependency. We create a TokenFactor for Ld and ResNode,
22350 // and update uses of Ld's output chain to use the TokenFactor.
22351 if (Ld->hasAnyUseOfValue(1)) {
22352 SDValue NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
22353 SDValue(Ld, 1), SDValue(ResNode.getNode(), 1));
22354 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), NewChain);
22355 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(Ld, 1),
22356 SDValue(ResNode.getNode(), 1));
22359 return DAG.getBitcast(VT, ResNode);
22363 // Emit a zeroed vector and insert the desired subvector on its
22365 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
22366 SDValue InsV = Insert128BitVector(Zeros, V1.getOperand(0), 0, DAG, dl);
22367 return DCI.CombineTo(N, InsV);
22370 //===--------------------------------------------------------------------===//
22371 // Combine some shuffles into subvector extracts and inserts:
22374 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
22375 if (isShuffleHigh128VectorInsertLow(SVOp)) {
22376 SDValue V = Extract128BitVector(V1, NumElems/2, DAG, dl);
22377 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, 0, DAG, dl);
22378 return DCI.CombineTo(N, InsV);
22381 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
22382 if (isShuffleLow128VectorInsertHigh(SVOp)) {
22383 SDValue V = Extract128BitVector(V1, 0, DAG, dl);
22384 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, NumElems/2, DAG, dl);
22385 return DCI.CombineTo(N, InsV);
22391 /// \brief Combine an arbitrary chain of shuffles into a single instruction if
22394 /// This is the leaf of the recursive combinine below. When we have found some
22395 /// chain of single-use x86 shuffle instructions and accumulated the combined
22396 /// shuffle mask represented by them, this will try to pattern match that mask
22397 /// into either a single instruction if there is a special purpose instruction
22398 /// for this operation, or into a PSHUFB instruction which is a fully general
22399 /// instruction but should only be used to replace chains over a certain depth.
22400 static bool combineX86ShuffleChain(SDValue Op, SDValue Root, ArrayRef<int> Mask,
22401 int Depth, bool HasPSHUFB, SelectionDAG &DAG,
22402 TargetLowering::DAGCombinerInfo &DCI,
22403 const X86Subtarget *Subtarget) {
22404 assert(!Mask.empty() && "Cannot combine an empty shuffle mask!");
22406 // Find the operand that enters the chain. Note that multiple uses are OK
22407 // here, we're not going to remove the operand we find.
22408 SDValue Input = Op.getOperand(0);
22409 while (Input.getOpcode() == ISD::BITCAST)
22410 Input = Input.getOperand(0);
22412 MVT VT = Input.getSimpleValueType();
22413 MVT RootVT = Root.getSimpleValueType();
22416 if (Mask.size() == 1) {
22417 int Index = Mask[0];
22418 assert((Index >= 0 || Index == SM_SentinelUndef ||
22419 Index == SM_SentinelZero) &&
22420 "Invalid shuffle index found!");
22422 // We may end up with an accumulated mask of size 1 as a result of
22423 // widening of shuffle operands (see function canWidenShuffleElements).
22424 // If the only shuffle index is equal to SM_SentinelZero then propagate
22425 // a zero vector. Otherwise, the combine shuffle mask is a no-op shuffle
22426 // mask, and therefore the entire chain of shuffles can be folded away.
22427 if (Index == SM_SentinelZero)
22428 DCI.CombineTo(Root.getNode(), getZeroVector(RootVT, Subtarget, DAG, DL));
22430 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Input),
22435 // Use the float domain if the operand type is a floating point type.
22436 bool FloatDomain = VT.isFloatingPoint();
22438 // For floating point shuffles, we don't have free copies in the shuffle
22439 // instructions or the ability to load as part of the instruction, so
22440 // canonicalize their shuffles to UNPCK or MOV variants.
22442 // Note that even with AVX we prefer the PSHUFD form of shuffle for integer
22443 // vectors because it can have a load folded into it that UNPCK cannot. This
22444 // doesn't preclude something switching to the shorter encoding post-RA.
22446 // FIXME: Should teach these routines about AVX vector widths.
22447 if (FloatDomain && VT.is128BitVector()) {
22448 if (Mask.equals({0, 0}) || Mask.equals({1, 1})) {
22449 bool Lo = Mask.equals({0, 0});
22452 // Check if we have SSE3 which will let us use MOVDDUP. That instruction
22453 // is no slower than UNPCKLPD but has the option to fold the input operand
22454 // into even an unaligned memory load.
22455 if (Lo && Subtarget->hasSSE3()) {
22456 Shuffle = X86ISD::MOVDDUP;
22457 ShuffleVT = MVT::v2f64;
22459 // We have MOVLHPS and MOVHLPS throughout SSE and they encode smaller
22460 // than the UNPCK variants.
22461 Shuffle = Lo ? X86ISD::MOVLHPS : X86ISD::MOVHLPS;
22462 ShuffleVT = MVT::v4f32;
22464 if (Depth == 1 && Root->getOpcode() == Shuffle)
22465 return false; // Nothing to do!
22466 Op = DAG.getBitcast(ShuffleVT, Input);
22467 DCI.AddToWorklist(Op.getNode());
22468 if (Shuffle == X86ISD::MOVDDUP)
22469 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op);
22471 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
22472 DCI.AddToWorklist(Op.getNode());
22473 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Op),
22477 if (Subtarget->hasSSE3() &&
22478 (Mask.equals({0, 0, 2, 2}) || Mask.equals({1, 1, 3, 3}))) {
22479 bool Lo = Mask.equals({0, 0, 2, 2});
22480 unsigned Shuffle = Lo ? X86ISD::MOVSLDUP : X86ISD::MOVSHDUP;
22481 MVT ShuffleVT = MVT::v4f32;
22482 if (Depth == 1 && Root->getOpcode() == Shuffle)
22483 return false; // Nothing to do!
22484 Op = DAG.getBitcast(ShuffleVT, Input);
22485 DCI.AddToWorklist(Op.getNode());
22486 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op);
22487 DCI.AddToWorklist(Op.getNode());
22488 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Op),
22492 if (Mask.equals({0, 0, 1, 1}) || Mask.equals({2, 2, 3, 3})) {
22493 bool Lo = Mask.equals({0, 0, 1, 1});
22494 unsigned Shuffle = Lo ? X86ISD::UNPCKL : X86ISD::UNPCKH;
22495 MVT ShuffleVT = MVT::v4f32;
22496 if (Depth == 1 && Root->getOpcode() == Shuffle)
22497 return false; // Nothing to do!
22498 Op = DAG.getBitcast(ShuffleVT, Input);
22499 DCI.AddToWorklist(Op.getNode());
22500 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
22501 DCI.AddToWorklist(Op.getNode());
22502 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Op),
22508 // We always canonicalize the 8 x i16 and 16 x i8 shuffles into their UNPCK
22509 // variants as none of these have single-instruction variants that are
22510 // superior to the UNPCK formulation.
22511 if (!FloatDomain && VT.is128BitVector() &&
22512 (Mask.equals({0, 0, 1, 1, 2, 2, 3, 3}) ||
22513 Mask.equals({4, 4, 5, 5, 6, 6, 7, 7}) ||
22514 Mask.equals({0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7}) ||
22516 {8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}))) {
22517 bool Lo = Mask[0] == 0;
22518 unsigned Shuffle = Lo ? X86ISD::UNPCKL : X86ISD::UNPCKH;
22519 if (Depth == 1 && Root->getOpcode() == Shuffle)
22520 return false; // Nothing to do!
22522 switch (Mask.size()) {
22524 ShuffleVT = MVT::v8i16;
22527 ShuffleVT = MVT::v16i8;
22530 llvm_unreachable("Impossible mask size!");
22532 Op = DAG.getBitcast(ShuffleVT, Input);
22533 DCI.AddToWorklist(Op.getNode());
22534 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
22535 DCI.AddToWorklist(Op.getNode());
22536 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Op),
22541 // Don't try to re-form single instruction chains under any circumstances now
22542 // that we've done encoding canonicalization for them.
22546 // If we have 3 or more shuffle instructions or a chain involving PSHUFB, we
22547 // can replace them with a single PSHUFB instruction profitably. Intel's
22548 // manuals suggest only using PSHUFB if doing so replacing 5 instructions, but
22549 // in practice PSHUFB tends to be *very* fast so we're more aggressive.
22550 if ((Depth >= 3 || HasPSHUFB) && Subtarget->hasSSSE3()) {
22551 SmallVector<SDValue, 16> PSHUFBMask;
22552 int NumBytes = VT.getSizeInBits() / 8;
22553 int Ratio = NumBytes / Mask.size();
22554 for (int i = 0; i < NumBytes; ++i) {
22555 if (Mask[i / Ratio] == SM_SentinelUndef) {
22556 PSHUFBMask.push_back(DAG.getUNDEF(MVT::i8));
22559 int M = Mask[i / Ratio] != SM_SentinelZero
22560 ? Ratio * Mask[i / Ratio] + i % Ratio
22562 PSHUFBMask.push_back(DAG.getConstant(M, DL, MVT::i8));
22564 MVT ByteVT = MVT::getVectorVT(MVT::i8, NumBytes);
22565 Op = DAG.getBitcast(ByteVT, Input);
22566 DCI.AddToWorklist(Op.getNode());
22567 SDValue PSHUFBMaskOp =
22568 DAG.getNode(ISD::BUILD_VECTOR, DL, ByteVT, PSHUFBMask);
22569 DCI.AddToWorklist(PSHUFBMaskOp.getNode());
22570 Op = DAG.getNode(X86ISD::PSHUFB, DL, ByteVT, Op, PSHUFBMaskOp);
22571 DCI.AddToWorklist(Op.getNode());
22572 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Op),
22577 // Failed to find any combines.
22581 /// \brief Fully generic combining of x86 shuffle instructions.
22583 /// This should be the last combine run over the x86 shuffle instructions. Once
22584 /// they have been fully optimized, this will recursively consider all chains
22585 /// of single-use shuffle instructions, build a generic model of the cumulative
22586 /// shuffle operation, and check for simpler instructions which implement this
22587 /// operation. We use this primarily for two purposes:
22589 /// 1) Collapse generic shuffles to specialized single instructions when
22590 /// equivalent. In most cases, this is just an encoding size win, but
22591 /// sometimes we will collapse multiple generic shuffles into a single
22592 /// special-purpose shuffle.
22593 /// 2) Look for sequences of shuffle instructions with 3 or more total
22594 /// instructions, and replace them with the slightly more expensive SSSE3
22595 /// PSHUFB instruction if available. We do this as the last combining step
22596 /// to ensure we avoid using PSHUFB if we can implement the shuffle with
22597 /// a suitable short sequence of other instructions. The PHUFB will either
22598 /// use a register or have to read from memory and so is slightly (but only
22599 /// slightly) more expensive than the other shuffle instructions.
22601 /// Because this is inherently a quadratic operation (for each shuffle in
22602 /// a chain, we recurse up the chain), the depth is limited to 8 instructions.
22603 /// This should never be an issue in practice as the shuffle lowering doesn't
22604 /// produce sequences of more than 8 instructions.
22606 /// FIXME: We will currently miss some cases where the redundant shuffling
22607 /// would simplify under the threshold for PSHUFB formation because of
22608 /// combine-ordering. To fix this, we should do the redundant instruction
22609 /// combining in this recursive walk.
22610 static bool combineX86ShufflesRecursively(SDValue Op, SDValue Root,
22611 ArrayRef<int> RootMask,
22612 int Depth, bool HasPSHUFB,
22614 TargetLowering::DAGCombinerInfo &DCI,
22615 const X86Subtarget *Subtarget) {
22616 // Bound the depth of our recursive combine because this is ultimately
22617 // quadratic in nature.
22621 // Directly rip through bitcasts to find the underlying operand.
22622 while (Op.getOpcode() == ISD::BITCAST && Op.getOperand(0).hasOneUse())
22623 Op = Op.getOperand(0);
22625 MVT VT = Op.getSimpleValueType();
22626 if (!VT.isVector())
22627 return false; // Bail if we hit a non-vector.
22629 assert(Root.getSimpleValueType().isVector() &&
22630 "Shuffles operate on vector types!");
22631 assert(VT.getSizeInBits() == Root.getSimpleValueType().getSizeInBits() &&
22632 "Can only combine shuffles of the same vector register size.");
22634 if (!isTargetShuffle(Op.getOpcode()))
22636 SmallVector<int, 16> OpMask;
22638 bool HaveMask = getTargetShuffleMask(Op.getNode(), VT, OpMask, IsUnary);
22639 // We only can combine unary shuffles which we can decode the mask for.
22640 if (!HaveMask || !IsUnary)
22643 assert(VT.getVectorNumElements() == OpMask.size() &&
22644 "Different mask size from vector size!");
22645 assert(((RootMask.size() > OpMask.size() &&
22646 RootMask.size() % OpMask.size() == 0) ||
22647 (OpMask.size() > RootMask.size() &&
22648 OpMask.size() % RootMask.size() == 0) ||
22649 OpMask.size() == RootMask.size()) &&
22650 "The smaller number of elements must divide the larger.");
22651 int RootRatio = std::max<int>(1, OpMask.size() / RootMask.size());
22652 int OpRatio = std::max<int>(1, RootMask.size() / OpMask.size());
22653 assert(((RootRatio == 1 && OpRatio == 1) ||
22654 (RootRatio == 1) != (OpRatio == 1)) &&
22655 "Must not have a ratio for both incoming and op masks!");
22657 SmallVector<int, 16> Mask;
22658 Mask.reserve(std::max(OpMask.size(), RootMask.size()));
22660 // Merge this shuffle operation's mask into our accumulated mask. Note that
22661 // this shuffle's mask will be the first applied to the input, followed by the
22662 // root mask to get us all the way to the root value arrangement. The reason
22663 // for this order is that we are recursing up the operation chain.
22664 for (int i = 0, e = std::max(OpMask.size(), RootMask.size()); i < e; ++i) {
22665 int RootIdx = i / RootRatio;
22666 if (RootMask[RootIdx] < 0) {
22667 // This is a zero or undef lane, we're done.
22668 Mask.push_back(RootMask[RootIdx]);
22672 int RootMaskedIdx = RootMask[RootIdx] * RootRatio + i % RootRatio;
22673 int OpIdx = RootMaskedIdx / OpRatio;
22674 if (OpMask[OpIdx] < 0) {
22675 // The incoming lanes are zero or undef, it doesn't matter which ones we
22677 Mask.push_back(OpMask[OpIdx]);
22681 // Ok, we have non-zero lanes, map them through.
22682 Mask.push_back(OpMask[OpIdx] * OpRatio +
22683 RootMaskedIdx % OpRatio);
22686 // See if we can recurse into the operand to combine more things.
22687 switch (Op.getOpcode()) {
22688 case X86ISD::PSHUFB:
22690 case X86ISD::PSHUFD:
22691 case X86ISD::PSHUFHW:
22692 case X86ISD::PSHUFLW:
22693 if (Op.getOperand(0).hasOneUse() &&
22694 combineX86ShufflesRecursively(Op.getOperand(0), Root, Mask, Depth + 1,
22695 HasPSHUFB, DAG, DCI, Subtarget))
22699 case X86ISD::UNPCKL:
22700 case X86ISD::UNPCKH:
22701 assert(Op.getOperand(0) == Op.getOperand(1) &&
22702 "We only combine unary shuffles!");
22703 // We can't check for single use, we have to check that this shuffle is the
22705 if (Op->isOnlyUserOf(Op.getOperand(0).getNode()) &&
22706 combineX86ShufflesRecursively(Op.getOperand(0), Root, Mask, Depth + 1,
22707 HasPSHUFB, DAG, DCI, Subtarget))
22712 // Minor canonicalization of the accumulated shuffle mask to make it easier
22713 // to match below. All this does is detect masks with squential pairs of
22714 // elements, and shrink them to the half-width mask. It does this in a loop
22715 // so it will reduce the size of the mask to the minimal width mask which
22716 // performs an equivalent shuffle.
22717 SmallVector<int, 16> WidenedMask;
22718 while (Mask.size() > 1 && canWidenShuffleElements(Mask, WidenedMask)) {
22719 Mask = std::move(WidenedMask);
22720 WidenedMask.clear();
22723 return combineX86ShuffleChain(Op, Root, Mask, Depth, HasPSHUFB, DAG, DCI,
22727 /// \brief Get the PSHUF-style mask from PSHUF node.
22729 /// This is a very minor wrapper around getTargetShuffleMask to easy forming v4
22730 /// PSHUF-style masks that can be reused with such instructions.
22731 static SmallVector<int, 4> getPSHUFShuffleMask(SDValue N) {
22732 MVT VT = N.getSimpleValueType();
22733 SmallVector<int, 4> Mask;
22735 bool HaveMask = getTargetShuffleMask(N.getNode(), VT, Mask, IsUnary);
22739 // If we have more than 128-bits, only the low 128-bits of shuffle mask
22740 // matter. Check that the upper masks are repeats and remove them.
22741 if (VT.getSizeInBits() > 128) {
22742 int LaneElts = 128 / VT.getScalarSizeInBits();
22744 for (int i = 1, NumLanes = VT.getSizeInBits() / 128; i < NumLanes; ++i)
22745 for (int j = 0; j < LaneElts; ++j)
22746 assert(Mask[j] == Mask[i * LaneElts + j] - (LaneElts * i) &&
22747 "Mask doesn't repeat in high 128-bit lanes!");
22749 Mask.resize(LaneElts);
22752 switch (N.getOpcode()) {
22753 case X86ISD::PSHUFD:
22755 case X86ISD::PSHUFLW:
22758 case X86ISD::PSHUFHW:
22759 Mask.erase(Mask.begin(), Mask.begin() + 4);
22760 for (int &M : Mask)
22764 llvm_unreachable("No valid shuffle instruction found!");
22768 /// \brief Search for a combinable shuffle across a chain ending in pshufd.
22770 /// We walk up the chain and look for a combinable shuffle, skipping over
22771 /// shuffles that we could hoist this shuffle's transformation past without
22772 /// altering anything.
22774 combineRedundantDWordShuffle(SDValue N, MutableArrayRef<int> Mask,
22776 TargetLowering::DAGCombinerInfo &DCI) {
22777 assert(N.getOpcode() == X86ISD::PSHUFD &&
22778 "Called with something other than an x86 128-bit half shuffle!");
22781 // Walk up a single-use chain looking for a combinable shuffle. Keep a stack
22782 // of the shuffles in the chain so that we can form a fresh chain to replace
22784 SmallVector<SDValue, 8> Chain;
22785 SDValue V = N.getOperand(0);
22786 for (; V.hasOneUse(); V = V.getOperand(0)) {
22787 switch (V.getOpcode()) {
22789 return SDValue(); // Nothing combined!
22792 // Skip bitcasts as we always know the type for the target specific
22796 case X86ISD::PSHUFD:
22797 // Found another dword shuffle.
22800 case X86ISD::PSHUFLW:
22801 // Check that the low words (being shuffled) are the identity in the
22802 // dword shuffle, and the high words are self-contained.
22803 if (Mask[0] != 0 || Mask[1] != 1 ||
22804 !(Mask[2] >= 2 && Mask[2] < 4 && Mask[3] >= 2 && Mask[3] < 4))
22807 Chain.push_back(V);
22810 case X86ISD::PSHUFHW:
22811 // Check that the high words (being shuffled) are the identity in the
22812 // dword shuffle, and the low words are self-contained.
22813 if (Mask[2] != 2 || Mask[3] != 3 ||
22814 !(Mask[0] >= 0 && Mask[0] < 2 && Mask[1] >= 0 && Mask[1] < 2))
22817 Chain.push_back(V);
22820 case X86ISD::UNPCKL:
22821 case X86ISD::UNPCKH:
22822 // For either i8 -> i16 or i16 -> i32 unpacks, we can combine a dword
22823 // shuffle into a preceding word shuffle.
22824 if (V.getSimpleValueType().getVectorElementType() != MVT::i8 &&
22825 V.getSimpleValueType().getVectorElementType() != MVT::i16)
22828 // Search for a half-shuffle which we can combine with.
22829 unsigned CombineOp =
22830 V.getOpcode() == X86ISD::UNPCKL ? X86ISD::PSHUFLW : X86ISD::PSHUFHW;
22831 if (V.getOperand(0) != V.getOperand(1) ||
22832 !V->isOnlyUserOf(V.getOperand(0).getNode()))
22834 Chain.push_back(V);
22835 V = V.getOperand(0);
22837 switch (V.getOpcode()) {
22839 return SDValue(); // Nothing to combine.
22841 case X86ISD::PSHUFLW:
22842 case X86ISD::PSHUFHW:
22843 if (V.getOpcode() == CombineOp)
22846 Chain.push_back(V);
22850 V = V.getOperand(0);
22854 } while (V.hasOneUse());
22857 // Break out of the loop if we break out of the switch.
22861 if (!V.hasOneUse())
22862 // We fell out of the loop without finding a viable combining instruction.
22865 // Merge this node's mask and our incoming mask.
22866 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
22867 for (int &M : Mask)
22869 V = DAG.getNode(V.getOpcode(), DL, V.getValueType(), V.getOperand(0),
22870 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
22872 // Rebuild the chain around this new shuffle.
22873 while (!Chain.empty()) {
22874 SDValue W = Chain.pop_back_val();
22876 if (V.getValueType() != W.getOperand(0).getValueType())
22877 V = DAG.getBitcast(W.getOperand(0).getValueType(), V);
22879 switch (W.getOpcode()) {
22881 llvm_unreachable("Only PSHUF and UNPCK instructions get here!");
22883 case X86ISD::UNPCKL:
22884 case X86ISD::UNPCKH:
22885 V = DAG.getNode(W.getOpcode(), DL, W.getValueType(), V, V);
22888 case X86ISD::PSHUFD:
22889 case X86ISD::PSHUFLW:
22890 case X86ISD::PSHUFHW:
22891 V = DAG.getNode(W.getOpcode(), DL, W.getValueType(), V, W.getOperand(1));
22895 if (V.getValueType() != N.getValueType())
22896 V = DAG.getBitcast(N.getValueType(), V);
22898 // Return the new chain to replace N.
22902 /// \brief Search for a combinable shuffle across a chain ending in pshuflw or
22905 /// We walk up the chain, skipping shuffles of the other half and looking
22906 /// through shuffles which switch halves trying to find a shuffle of the same
22907 /// pair of dwords.
22908 static bool combineRedundantHalfShuffle(SDValue N, MutableArrayRef<int> Mask,
22910 TargetLowering::DAGCombinerInfo &DCI) {
22912 (N.getOpcode() == X86ISD::PSHUFLW || N.getOpcode() == X86ISD::PSHUFHW) &&
22913 "Called with something other than an x86 128-bit half shuffle!");
22915 unsigned CombineOpcode = N.getOpcode();
22917 // Walk up a single-use chain looking for a combinable shuffle.
22918 SDValue V = N.getOperand(0);
22919 for (; V.hasOneUse(); V = V.getOperand(0)) {
22920 switch (V.getOpcode()) {
22922 return false; // Nothing combined!
22925 // Skip bitcasts as we always know the type for the target specific
22929 case X86ISD::PSHUFLW:
22930 case X86ISD::PSHUFHW:
22931 if (V.getOpcode() == CombineOpcode)
22934 // Other-half shuffles are no-ops.
22937 // Break out of the loop if we break out of the switch.
22941 if (!V.hasOneUse())
22942 // We fell out of the loop without finding a viable combining instruction.
22945 // Combine away the bottom node as its shuffle will be accumulated into
22946 // a preceding shuffle.
22947 DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
22949 // Record the old value.
22952 // Merge this node's mask and our incoming mask (adjusted to account for all
22953 // the pshufd instructions encountered).
22954 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
22955 for (int &M : Mask)
22957 V = DAG.getNode(V.getOpcode(), DL, MVT::v8i16, V.getOperand(0),
22958 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
22960 // Check that the shuffles didn't cancel each other out. If not, we need to
22961 // combine to the new one.
22963 // Replace the combinable shuffle with the combined one, updating all users
22964 // so that we re-evaluate the chain here.
22965 DCI.CombineTo(Old.getNode(), V, /*AddTo*/ true);
22970 /// \brief Try to combine x86 target specific shuffles.
22971 static SDValue PerformTargetShuffleCombine(SDValue N, SelectionDAG &DAG,
22972 TargetLowering::DAGCombinerInfo &DCI,
22973 const X86Subtarget *Subtarget) {
22975 MVT VT = N.getSimpleValueType();
22976 SmallVector<int, 4> Mask;
22978 switch (N.getOpcode()) {
22979 case X86ISD::PSHUFD:
22980 case X86ISD::PSHUFLW:
22981 case X86ISD::PSHUFHW:
22982 Mask = getPSHUFShuffleMask(N);
22983 assert(Mask.size() == 4);
22985 case X86ISD::UNPCKL: {
22986 // Combine X86ISD::UNPCKL and ISD::VECTOR_SHUFFLE into X86ISD::UNPCKH, in
22987 // which X86ISD::UNPCKL has a ISD::UNDEF operand, and ISD::VECTOR_SHUFFLE
22988 // moves upper half elements into the lower half part. For example:
22990 // t2: v16i8 = vector_shuffle<8,9,10,11,12,13,14,15,u,u,u,u,u,u,u,u> t1,
22992 // t3: v16i8 = X86ISD::UNPCKL undef:v16i8, t2
22994 // will be combined to:
22996 // t3: v16i8 = X86ISD::UNPCKH undef:v16i8, t1
22998 // This is only for 128-bit vectors. From SSE4.1 onward this combine may not
22999 // happen due to advanced instructions.
23000 if (!VT.is128BitVector())
23003 auto Op0 = N.getOperand(0);
23004 auto Op1 = N.getOperand(1);
23005 if (Op0.getOpcode() == ISD::UNDEF &&
23006 Op1.getNode()->getOpcode() == ISD::VECTOR_SHUFFLE) {
23007 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(Op1.getNode())->getMask();
23009 unsigned NumElts = VT.getVectorNumElements();
23010 SmallVector<int, 8> ExpectedMask(NumElts, -1);
23011 std::iota(ExpectedMask.begin(), ExpectedMask.begin() + NumElts / 2,
23014 auto ShufOp = Op1.getOperand(0);
23015 if (isShuffleEquivalent(Op1, ShufOp, Mask, ExpectedMask))
23016 return DAG.getNode(X86ISD::UNPCKH, DL, VT, N.getOperand(0), ShufOp);
23024 // Nuke no-op shuffles that show up after combining.
23025 if (isNoopShuffleMask(Mask))
23026 return DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
23028 // Look for simplifications involving one or two shuffle instructions.
23029 SDValue V = N.getOperand(0);
23030 switch (N.getOpcode()) {
23033 case X86ISD::PSHUFLW:
23034 case X86ISD::PSHUFHW:
23035 assert(VT.getVectorElementType() == MVT::i16 && "Bad word shuffle type!");
23037 if (combineRedundantHalfShuffle(N, Mask, DAG, DCI))
23038 return SDValue(); // We combined away this shuffle, so we're done.
23040 // See if this reduces to a PSHUFD which is no more expensive and can
23041 // combine with more operations. Note that it has to at least flip the
23042 // dwords as otherwise it would have been removed as a no-op.
23043 if (makeArrayRef(Mask).equals({2, 3, 0, 1})) {
23044 int DMask[] = {0, 1, 2, 3};
23045 int DOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 2;
23046 DMask[DOffset + 0] = DOffset + 1;
23047 DMask[DOffset + 1] = DOffset + 0;
23048 MVT DVT = MVT::getVectorVT(MVT::i32, VT.getVectorNumElements() / 2);
23049 V = DAG.getBitcast(DVT, V);
23050 DCI.AddToWorklist(V.getNode());
23051 V = DAG.getNode(X86ISD::PSHUFD, DL, DVT, V,
23052 getV4X86ShuffleImm8ForMask(DMask, DL, DAG));
23053 DCI.AddToWorklist(V.getNode());
23054 return DAG.getBitcast(VT, V);
23057 // Look for shuffle patterns which can be implemented as a single unpack.
23058 // FIXME: This doesn't handle the location of the PSHUFD generically, and
23059 // only works when we have a PSHUFD followed by two half-shuffles.
23060 if (Mask[0] == Mask[1] && Mask[2] == Mask[3] &&
23061 (V.getOpcode() == X86ISD::PSHUFLW ||
23062 V.getOpcode() == X86ISD::PSHUFHW) &&
23063 V.getOpcode() != N.getOpcode() &&
23065 SDValue D = V.getOperand(0);
23066 while (D.getOpcode() == ISD::BITCAST && D.hasOneUse())
23067 D = D.getOperand(0);
23068 if (D.getOpcode() == X86ISD::PSHUFD && D.hasOneUse()) {
23069 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
23070 SmallVector<int, 4> DMask = getPSHUFShuffleMask(D);
23071 int NOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
23072 int VOffset = V.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
23074 for (int i = 0; i < 4; ++i) {
23075 WordMask[i + NOffset] = Mask[i] + NOffset;
23076 WordMask[i + VOffset] = VMask[i] + VOffset;
23078 // Map the word mask through the DWord mask.
23080 for (int i = 0; i < 8; ++i)
23081 MappedMask[i] = 2 * DMask[WordMask[i] / 2] + WordMask[i] % 2;
23082 if (makeArrayRef(MappedMask).equals({0, 0, 1, 1, 2, 2, 3, 3}) ||
23083 makeArrayRef(MappedMask).equals({4, 4, 5, 5, 6, 6, 7, 7})) {
23084 // We can replace all three shuffles with an unpack.
23085 V = DAG.getBitcast(VT, D.getOperand(0));
23086 DCI.AddToWorklist(V.getNode());
23087 return DAG.getNode(MappedMask[0] == 0 ? X86ISD::UNPCKL
23096 case X86ISD::PSHUFD:
23097 if (SDValue NewN = combineRedundantDWordShuffle(N, Mask, DAG, DCI))
23106 /// \brief Try to combine a shuffle into a target-specific add-sub node.
23108 /// We combine this directly on the abstract vector shuffle nodes so it is
23109 /// easier to generically match. We also insert dummy vector shuffle nodes for
23110 /// the operands which explicitly discard the lanes which are unused by this
23111 /// operation to try to flow through the rest of the combiner the fact that
23112 /// they're unused.
23113 static SDValue combineShuffleToAddSub(SDNode *N, SelectionDAG &DAG) {
23115 EVT VT = N->getValueType(0);
23117 // We only handle target-independent shuffles.
23118 // FIXME: It would be easy and harmless to use the target shuffle mask
23119 // extraction tool to support more.
23120 if (N->getOpcode() != ISD::VECTOR_SHUFFLE)
23123 auto *SVN = cast<ShuffleVectorSDNode>(N);
23124 ArrayRef<int> Mask = SVN->getMask();
23125 SDValue V1 = N->getOperand(0);
23126 SDValue V2 = N->getOperand(1);
23128 // We require the first shuffle operand to be the SUB node, and the second to
23129 // be the ADD node.
23130 // FIXME: We should support the commuted patterns.
23131 if (V1->getOpcode() != ISD::FSUB || V2->getOpcode() != ISD::FADD)
23134 // If there are other uses of these operations we can't fold them.
23135 if (!V1->hasOneUse() || !V2->hasOneUse())
23138 // Ensure that both operations have the same operands. Note that we can
23139 // commute the FADD operands.
23140 SDValue LHS = V1->getOperand(0), RHS = V1->getOperand(1);
23141 if ((V2->getOperand(0) != LHS || V2->getOperand(1) != RHS) &&
23142 (V2->getOperand(0) != RHS || V2->getOperand(1) != LHS))
23145 // We're looking for blends between FADD and FSUB nodes. We insist on these
23146 // nodes being lined up in a specific expected pattern.
23147 if (!(isShuffleEquivalent(V1, V2, Mask, {0, 3}) ||
23148 isShuffleEquivalent(V1, V2, Mask, {0, 5, 2, 7}) ||
23149 isShuffleEquivalent(V1, V2, Mask, {0, 9, 2, 11, 4, 13, 6, 15})))
23152 // Only specific types are legal at this point, assert so we notice if and
23153 // when these change.
23154 assert((VT == MVT::v4f32 || VT == MVT::v2f64 || VT == MVT::v8f32 ||
23155 VT == MVT::v4f64) &&
23156 "Unknown vector type encountered!");
23158 return DAG.getNode(X86ISD::ADDSUB, DL, VT, LHS, RHS);
23161 /// PerformShuffleCombine - Performs several different shuffle combines.
23162 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
23163 TargetLowering::DAGCombinerInfo &DCI,
23164 const X86Subtarget *Subtarget) {
23166 SDValue N0 = N->getOperand(0);
23167 SDValue N1 = N->getOperand(1);
23168 EVT VT = N->getValueType(0);
23170 // Don't create instructions with illegal types after legalize types has run.
23171 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23172 if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType()))
23175 // If we have legalized the vector types, look for blends of FADD and FSUB
23176 // nodes that we can fuse into an ADDSUB node.
23177 if (TLI.isTypeLegal(VT) && Subtarget->hasSSE3())
23178 if (SDValue AddSub = combineShuffleToAddSub(N, DAG))
23181 // Combine 256-bit vector shuffles. This is only profitable when in AVX mode
23182 if (Subtarget->hasFp256() && VT.is256BitVector() &&
23183 N->getOpcode() == ISD::VECTOR_SHUFFLE)
23184 return PerformShuffleCombine256(N, DAG, DCI, Subtarget);
23186 // During Type Legalization, when promoting illegal vector types,
23187 // the backend might introduce new shuffle dag nodes and bitcasts.
23189 // This code performs the following transformation:
23190 // fold: (shuffle (bitcast (BINOP A, B)), Undef, <Mask>) ->
23191 // (shuffle (BINOP (bitcast A), (bitcast B)), Undef, <Mask>)
23193 // We do this only if both the bitcast and the BINOP dag nodes have
23194 // one use. Also, perform this transformation only if the new binary
23195 // operation is legal. This is to avoid introducing dag nodes that
23196 // potentially need to be further expanded (or custom lowered) into a
23197 // less optimal sequence of dag nodes.
23198 if (!DCI.isBeforeLegalize() && DCI.isBeforeLegalizeOps() &&
23199 N1.getOpcode() == ISD::UNDEF && N0.hasOneUse() &&
23200 N0.getOpcode() == ISD::BITCAST) {
23201 SDValue BC0 = N0.getOperand(0);
23202 EVT SVT = BC0.getValueType();
23203 unsigned Opcode = BC0.getOpcode();
23204 unsigned NumElts = VT.getVectorNumElements();
23206 if (BC0.hasOneUse() && SVT.isVector() &&
23207 SVT.getVectorNumElements() * 2 == NumElts &&
23208 TLI.isOperationLegal(Opcode, VT)) {
23209 bool CanFold = false;
23221 unsigned SVTNumElts = SVT.getVectorNumElements();
23222 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
23223 for (unsigned i = 0, e = SVTNumElts; i != e && CanFold; ++i)
23224 CanFold = SVOp->getMaskElt(i) == (int)(i * 2);
23225 for (unsigned i = SVTNumElts, e = NumElts; i != e && CanFold; ++i)
23226 CanFold = SVOp->getMaskElt(i) < 0;
23229 SDValue BC00 = DAG.getBitcast(VT, BC0.getOperand(0));
23230 SDValue BC01 = DAG.getBitcast(VT, BC0.getOperand(1));
23231 SDValue NewBinOp = DAG.getNode(BC0.getOpcode(), dl, VT, BC00, BC01);
23232 return DAG.getVectorShuffle(VT, dl, NewBinOp, N1, &SVOp->getMask()[0]);
23237 // Combine a vector_shuffle that is equal to build_vector load1, load2, load3,
23238 // load4, <0, 1, 2, 3> into a 128-bit load if the load addresses are
23239 // consecutive, non-overlapping, and in the right order.
23240 SmallVector<SDValue, 16> Elts;
23241 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
23242 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0));
23244 if (SDValue LD = EltsFromConsecutiveLoads(VT, Elts, dl, DAG, true))
23247 if (isTargetShuffle(N->getOpcode())) {
23249 PerformTargetShuffleCombine(SDValue(N, 0), DAG, DCI, Subtarget);
23250 if (Shuffle.getNode())
23253 // Try recursively combining arbitrary sequences of x86 shuffle
23254 // instructions into higher-order shuffles. We do this after combining
23255 // specific PSHUF instruction sequences into their minimal form so that we
23256 // can evaluate how many specialized shuffle instructions are involved in
23257 // a particular chain.
23258 SmallVector<int, 1> NonceMask; // Just a placeholder.
23259 NonceMask.push_back(0);
23260 if (combineX86ShufflesRecursively(SDValue(N, 0), SDValue(N, 0), NonceMask,
23261 /*Depth*/ 1, /*HasPSHUFB*/ false, DAG,
23263 return SDValue(); // This routine will use CombineTo to replace N.
23269 /// XFormVExtractWithShuffleIntoLoad - Check if a vector extract from a target
23270 /// specific shuffle of a load can be folded into a single element load.
23271 /// Similar handling for VECTOR_SHUFFLE is performed by DAGCombiner, but
23272 /// shuffles have been custom lowered so we need to handle those here.
23273 static SDValue XFormVExtractWithShuffleIntoLoad(SDNode *N, SelectionDAG &DAG,
23274 TargetLowering::DAGCombinerInfo &DCI) {
23275 if (DCI.isBeforeLegalizeOps())
23278 SDValue InVec = N->getOperand(0);
23279 SDValue EltNo = N->getOperand(1);
23281 if (!isa<ConstantSDNode>(EltNo))
23284 EVT OriginalVT = InVec.getValueType();
23286 if (InVec.getOpcode() == ISD::BITCAST) {
23287 // Don't duplicate a load with other uses.
23288 if (!InVec.hasOneUse())
23290 EVT BCVT = InVec.getOperand(0).getValueType();
23291 if (!BCVT.isVector() ||
23292 BCVT.getVectorNumElements() != OriginalVT.getVectorNumElements())
23294 InVec = InVec.getOperand(0);
23297 EVT CurrentVT = InVec.getValueType();
23299 if (!isTargetShuffle(InVec.getOpcode()))
23302 // Don't duplicate a load with other uses.
23303 if (!InVec.hasOneUse())
23306 SmallVector<int, 16> ShuffleMask;
23308 if (!getTargetShuffleMask(InVec.getNode(), CurrentVT.getSimpleVT(),
23309 ShuffleMask, UnaryShuffle))
23312 // Select the input vector, guarding against out of range extract vector.
23313 unsigned NumElems = CurrentVT.getVectorNumElements();
23314 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
23315 int Idx = (Elt > (int)NumElems) ? -1 : ShuffleMask[Elt];
23316 SDValue LdNode = (Idx < (int)NumElems) ? InVec.getOperand(0)
23317 : InVec.getOperand(1);
23319 // If inputs to shuffle are the same for both ops, then allow 2 uses
23320 unsigned AllowedUses = InVec.getNumOperands() > 1 &&
23321 InVec.getOperand(0) == InVec.getOperand(1) ? 2 : 1;
23323 if (LdNode.getOpcode() == ISD::BITCAST) {
23324 // Don't duplicate a load with other uses.
23325 if (!LdNode.getNode()->hasNUsesOfValue(AllowedUses, 0))
23328 AllowedUses = 1; // only allow 1 load use if we have a bitcast
23329 LdNode = LdNode.getOperand(0);
23332 if (!ISD::isNormalLoad(LdNode.getNode()))
23335 LoadSDNode *LN0 = cast<LoadSDNode>(LdNode);
23337 if (!LN0 ||!LN0->hasNUsesOfValue(AllowedUses, 0) || LN0->isVolatile())
23340 EVT EltVT = N->getValueType(0);
23341 // If there's a bitcast before the shuffle, check if the load type and
23342 // alignment is valid.
23343 unsigned Align = LN0->getAlignment();
23344 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23345 unsigned NewAlign = DAG.getDataLayout().getABITypeAlignment(
23346 EltVT.getTypeForEVT(*DAG.getContext()));
23348 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, EltVT))
23351 // All checks match so transform back to vector_shuffle so that DAG combiner
23352 // can finish the job
23355 // Create shuffle node taking into account the case that its a unary shuffle
23356 SDValue Shuffle = (UnaryShuffle) ? DAG.getUNDEF(CurrentVT)
23357 : InVec.getOperand(1);
23358 Shuffle = DAG.getVectorShuffle(CurrentVT, dl,
23359 InVec.getOperand(0), Shuffle,
23361 Shuffle = DAG.getBitcast(OriginalVT, Shuffle);
23362 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, N->getValueType(0), Shuffle,
23366 static SDValue PerformBITCASTCombine(SDNode *N, SelectionDAG &DAG,
23367 const X86Subtarget *Subtarget) {
23368 SDValue N0 = N->getOperand(0);
23369 EVT VT = N->getValueType(0);
23371 // Detect bitcasts between i32 to x86mmx low word. Since MMX types are
23372 // special and don't usually play with other vector types, it's better to
23373 // handle them early to be sure we emit efficient code by avoiding
23374 // store-load conversions.
23375 if (VT == MVT::x86mmx && N0.getOpcode() == ISD::BUILD_VECTOR &&
23376 N0.getValueType() == MVT::v2i32 &&
23377 isa<ConstantSDNode>(N0.getOperand(1))) {
23378 SDValue N00 = N0->getOperand(0);
23379 if (N0.getConstantOperandVal(1) == 0 && N00.getValueType() == MVT::i32)
23380 return DAG.getNode(X86ISD::MMX_MOVW2D, SDLoc(N00), VT, N00);
23383 // Convert a bitcasted integer logic operation that has one bitcasted
23384 // floating-point operand and one constant operand into a floating-point
23385 // logic operation. This may create a load of the constant, but that is
23386 // cheaper than materializing the constant in an integer register and
23387 // transferring it to an SSE register or transferring the SSE operand to
23388 // integer register and back.
23390 switch (N0.getOpcode()) {
23391 case ISD::AND: FPOpcode = X86ISD::FAND; break;
23392 case ISD::OR: FPOpcode = X86ISD::FOR; break;
23393 case ISD::XOR: FPOpcode = X86ISD::FXOR; break;
23394 default: return SDValue();
23396 if (((Subtarget->hasSSE1() && VT == MVT::f32) ||
23397 (Subtarget->hasSSE2() && VT == MVT::f64)) &&
23398 isa<ConstantSDNode>(N0.getOperand(1)) &&
23399 N0.getOperand(0).getOpcode() == ISD::BITCAST &&
23400 N0.getOperand(0).getOperand(0).getValueType() == VT) {
23401 SDValue N000 = N0.getOperand(0).getOperand(0);
23402 SDValue FPConst = DAG.getBitcast(VT, N0.getOperand(1));
23403 return DAG.getNode(FPOpcode, SDLoc(N0), VT, N000, FPConst);
23409 /// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index
23410 /// generation and convert it from being a bunch of shuffles and extracts
23411 /// into a somewhat faster sequence. For i686, the best sequence is apparently
23412 /// storing the value and loading scalars back, while for x64 we should
23413 /// use 64-bit extracts and shifts.
23414 static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG,
23415 TargetLowering::DAGCombinerInfo &DCI) {
23416 if (SDValue NewOp = XFormVExtractWithShuffleIntoLoad(N, DAG, DCI))
23419 SDValue InputVector = N->getOperand(0);
23420 SDLoc dl(InputVector);
23421 // Detect mmx to i32 conversion through a v2i32 elt extract.
23422 if (InputVector.getOpcode() == ISD::BITCAST && InputVector.hasOneUse() &&
23423 N->getValueType(0) == MVT::i32 &&
23424 InputVector.getValueType() == MVT::v2i32) {
23426 // The bitcast source is a direct mmx result.
23427 SDValue MMXSrc = InputVector.getNode()->getOperand(0);
23428 if (MMXSrc.getValueType() == MVT::x86mmx)
23429 return DAG.getNode(X86ISD::MMX_MOVD2W, SDLoc(InputVector),
23430 N->getValueType(0),
23431 InputVector.getNode()->getOperand(0));
23433 // The mmx is indirect: (i64 extract_elt (v1i64 bitcast (x86mmx ...))).
23434 if (MMXSrc.getOpcode() == ISD::EXTRACT_VECTOR_ELT && MMXSrc.hasOneUse() &&
23435 MMXSrc.getValueType() == MVT::i64) {
23436 SDValue MMXSrcOp = MMXSrc.getOperand(0);
23437 if (MMXSrcOp.hasOneUse() && MMXSrcOp.getOpcode() == ISD::BITCAST &&
23438 MMXSrcOp.getValueType() == MVT::v1i64 &&
23439 MMXSrcOp.getOperand(0).getValueType() == MVT::x86mmx)
23440 return DAG.getNode(X86ISD::MMX_MOVD2W, SDLoc(InputVector),
23441 N->getValueType(0), MMXSrcOp.getOperand(0));
23445 EVT VT = N->getValueType(0);
23447 if (VT == MVT::i1 && isa<ConstantSDNode>(N->getOperand(1)) &&
23448 InputVector.getOpcode() == ISD::BITCAST &&
23449 isa<ConstantSDNode>(InputVector.getOperand(0))) {
23450 uint64_t ExtractedElt =
23451 cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
23452 uint64_t InputValue =
23453 cast<ConstantSDNode>(InputVector.getOperand(0))->getZExtValue();
23454 uint64_t Res = (InputValue >> ExtractedElt) & 1;
23455 return DAG.getConstant(Res, dl, MVT::i1);
23457 // Only operate on vectors of 4 elements, where the alternative shuffling
23458 // gets to be more expensive.
23459 if (InputVector.getValueType() != MVT::v4i32)
23462 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a
23463 // single use which is a sign-extend or zero-extend, and all elements are
23465 SmallVector<SDNode *, 4> Uses;
23466 unsigned ExtractedElements = 0;
23467 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(),
23468 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) {
23469 if (UI.getUse().getResNo() != InputVector.getResNo())
23472 SDNode *Extract = *UI;
23473 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
23476 if (Extract->getValueType(0) != MVT::i32)
23478 if (!Extract->hasOneUse())
23480 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND &&
23481 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND)
23483 if (!isa<ConstantSDNode>(Extract->getOperand(1)))
23486 // Record which element was extracted.
23487 ExtractedElements |=
23488 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue();
23490 Uses.push_back(Extract);
23493 // If not all the elements were used, this may not be worthwhile.
23494 if (ExtractedElements != 15)
23497 // Ok, we've now decided to do the transformation.
23498 // If 64-bit shifts are legal, use the extract-shift sequence,
23499 // otherwise bounce the vector off the cache.
23500 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23503 if (TLI.isOperationLegal(ISD::SRA, MVT::i64)) {
23504 SDValue Cst = DAG.getBitcast(MVT::v2i64, InputVector);
23505 auto &DL = DAG.getDataLayout();
23506 EVT VecIdxTy = DAG.getTargetLoweringInfo().getVectorIdxTy(DL);
23507 SDValue BottomHalf = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64, Cst,
23508 DAG.getConstant(0, dl, VecIdxTy));
23509 SDValue TopHalf = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64, Cst,
23510 DAG.getConstant(1, dl, VecIdxTy));
23512 SDValue ShAmt = DAG.getConstant(
23513 32, dl, DAG.getTargetLoweringInfo().getShiftAmountTy(MVT::i64, DL));
23514 Vals[0] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, BottomHalf);
23515 Vals[1] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32,
23516 DAG.getNode(ISD::SRA, dl, MVT::i64, BottomHalf, ShAmt));
23517 Vals[2] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, TopHalf);
23518 Vals[3] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32,
23519 DAG.getNode(ISD::SRA, dl, MVT::i64, TopHalf, ShAmt));
23521 // Store the value to a temporary stack slot.
23522 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType());
23523 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr,
23524 MachinePointerInfo(), false, false, 0);
23526 EVT ElementType = InputVector.getValueType().getVectorElementType();
23527 unsigned EltSize = ElementType.getSizeInBits() / 8;
23529 // Replace each use (extract) with a load of the appropriate element.
23530 for (unsigned i = 0; i < 4; ++i) {
23531 uint64_t Offset = EltSize * i;
23532 auto PtrVT = TLI.getPointerTy(DAG.getDataLayout());
23533 SDValue OffsetVal = DAG.getConstant(Offset, dl, PtrVT);
23535 SDValue ScalarAddr =
23536 DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, OffsetVal);
23538 // Load the scalar.
23539 Vals[i] = DAG.getLoad(ElementType, dl, Ch,
23540 ScalarAddr, MachinePointerInfo(),
23541 false, false, false, 0);
23546 // Replace the extracts
23547 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(),
23548 UE = Uses.end(); UI != UE; ++UI) {
23549 SDNode *Extract = *UI;
23551 SDValue Idx = Extract->getOperand(1);
23552 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
23553 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), Vals[IdxVal]);
23556 // The replacement was made in place; don't return anything.
23561 transformVSELECTtoBlendVECTOR_SHUFFLE(SDNode *N, SelectionDAG &DAG,
23562 const X86Subtarget *Subtarget) {
23564 SDValue Cond = N->getOperand(0);
23565 SDValue LHS = N->getOperand(1);
23566 SDValue RHS = N->getOperand(2);
23568 if (Cond.getOpcode() == ISD::SIGN_EXTEND) {
23569 SDValue CondSrc = Cond->getOperand(0);
23570 if (CondSrc->getOpcode() == ISD::SIGN_EXTEND_INREG)
23571 Cond = CondSrc->getOperand(0);
23574 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
23577 // A vselect where all conditions and data are constants can be optimized into
23578 // a single vector load by SelectionDAGLegalize::ExpandBUILD_VECTOR().
23579 if (ISD::isBuildVectorOfConstantSDNodes(LHS.getNode()) &&
23580 ISD::isBuildVectorOfConstantSDNodes(RHS.getNode()))
23583 unsigned MaskValue = 0;
23584 if (!BUILD_VECTORtoBlendMask(cast<BuildVectorSDNode>(Cond), MaskValue))
23587 MVT VT = N->getSimpleValueType(0);
23588 unsigned NumElems = VT.getVectorNumElements();
23589 SmallVector<int, 8> ShuffleMask(NumElems, -1);
23590 for (unsigned i = 0; i < NumElems; ++i) {
23591 // Be sure we emit undef where we can.
23592 if (Cond.getOperand(i)->getOpcode() == ISD::UNDEF)
23593 ShuffleMask[i] = -1;
23595 ShuffleMask[i] = i + NumElems * ((MaskValue >> i) & 1);
23598 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23599 if (!TLI.isShuffleMaskLegal(ShuffleMask, VT))
23601 return DAG.getVectorShuffle(VT, dl, LHS, RHS, &ShuffleMask[0]);
23604 /// PerformSELECTCombine - Do target-specific dag combines on SELECT and VSELECT
23606 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
23607 TargetLowering::DAGCombinerInfo &DCI,
23608 const X86Subtarget *Subtarget) {
23610 SDValue Cond = N->getOperand(0);
23611 // Get the LHS/RHS of the select.
23612 SDValue LHS = N->getOperand(1);
23613 SDValue RHS = N->getOperand(2);
23614 EVT VT = LHS.getValueType();
23615 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23617 // If we have SSE[12] support, try to form min/max nodes. SSE min/max
23618 // instructions match the semantics of the common C idiom x<y?x:y but not
23619 // x<=y?x:y, because of how they handle negative zero (which can be
23620 // ignored in unsafe-math mode).
23621 // We also try to create v2f32 min/max nodes, which we later widen to v4f32.
23622 if (Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() &&
23623 VT != MVT::f80 && (TLI.isTypeLegal(VT) || VT == MVT::v2f32) &&
23624 (Subtarget->hasSSE2() ||
23625 (Subtarget->hasSSE1() && VT.getScalarType() == MVT::f32))) {
23626 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
23628 unsigned Opcode = 0;
23629 // Check for x CC y ? x : y.
23630 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
23631 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
23635 // Converting this to a min would handle NaNs incorrectly, and swapping
23636 // the operands would cause it to handle comparisons between positive
23637 // and negative zero incorrectly.
23638 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
23639 if (!DAG.getTarget().Options.UnsafeFPMath &&
23640 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
23642 std::swap(LHS, RHS);
23644 Opcode = X86ISD::FMIN;
23647 // Converting this to a min would handle comparisons between positive
23648 // and negative zero incorrectly.
23649 if (!DAG.getTarget().Options.UnsafeFPMath &&
23650 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
23652 Opcode = X86ISD::FMIN;
23655 // Converting this to a min would handle both negative zeros and NaNs
23656 // incorrectly, but we can swap the operands to fix both.
23657 std::swap(LHS, RHS);
23661 Opcode = X86ISD::FMIN;
23665 // Converting this to a max would handle comparisons between positive
23666 // and negative zero incorrectly.
23667 if (!DAG.getTarget().Options.UnsafeFPMath &&
23668 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
23670 Opcode = X86ISD::FMAX;
23673 // Converting this to a max would handle NaNs incorrectly, and swapping
23674 // the operands would cause it to handle comparisons between positive
23675 // and negative zero incorrectly.
23676 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
23677 if (!DAG.getTarget().Options.UnsafeFPMath &&
23678 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
23680 std::swap(LHS, RHS);
23682 Opcode = X86ISD::FMAX;
23685 // Converting this to a max would handle both negative zeros and NaNs
23686 // incorrectly, but we can swap the operands to fix both.
23687 std::swap(LHS, RHS);
23691 Opcode = X86ISD::FMAX;
23694 // Check for x CC y ? y : x -- a min/max with reversed arms.
23695 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
23696 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
23700 // Converting this to a min would handle comparisons between positive
23701 // and negative zero incorrectly, and swapping the operands would
23702 // cause it to handle NaNs incorrectly.
23703 if (!DAG.getTarget().Options.UnsafeFPMath &&
23704 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) {
23705 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
23707 std::swap(LHS, RHS);
23709 Opcode = X86ISD::FMIN;
23712 // Converting this to a min would handle NaNs incorrectly.
23713 if (!DAG.getTarget().Options.UnsafeFPMath &&
23714 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
23716 Opcode = X86ISD::FMIN;
23719 // Converting this to a min would handle both negative zeros and NaNs
23720 // incorrectly, but we can swap the operands to fix both.
23721 std::swap(LHS, RHS);
23725 Opcode = X86ISD::FMIN;
23729 // Converting this to a max would handle NaNs incorrectly.
23730 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
23732 Opcode = X86ISD::FMAX;
23735 // Converting this to a max would handle comparisons between positive
23736 // and negative zero incorrectly, and swapping the operands would
23737 // cause it to handle NaNs incorrectly.
23738 if (!DAG.getTarget().Options.UnsafeFPMath &&
23739 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) {
23740 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
23742 std::swap(LHS, RHS);
23744 Opcode = X86ISD::FMAX;
23747 // Converting this to a max would handle both negative zeros and NaNs
23748 // incorrectly, but we can swap the operands to fix both.
23749 std::swap(LHS, RHS);
23753 Opcode = X86ISD::FMAX;
23759 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
23762 EVT CondVT = Cond.getValueType();
23763 if (Subtarget->hasAVX512() && VT.isVector() && CondVT.isVector() &&
23764 CondVT.getVectorElementType() == MVT::i1) {
23765 // v16i8 (select v16i1, v16i8, v16i8) does not have a proper
23766 // lowering on KNL. In this case we convert it to
23767 // v16i8 (select v16i8, v16i8, v16i8) and use AVX instruction.
23768 // The same situation for all 128 and 256-bit vectors of i8 and i16.
23769 // Since SKX these selects have a proper lowering.
23770 EVT OpVT = LHS.getValueType();
23771 if ((OpVT.is128BitVector() || OpVT.is256BitVector()) &&
23772 (OpVT.getVectorElementType() == MVT::i8 ||
23773 OpVT.getVectorElementType() == MVT::i16) &&
23774 !(Subtarget->hasBWI() && Subtarget->hasVLX())) {
23775 Cond = DAG.getNode(ISD::SIGN_EXTEND, DL, OpVT, Cond);
23776 DCI.AddToWorklist(Cond.getNode());
23777 return DAG.getNode(N->getOpcode(), DL, OpVT, Cond, LHS, RHS);
23780 // If this is a select between two integer constants, try to do some
23782 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
23783 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
23784 // Don't do this for crazy integer types.
23785 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
23786 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
23787 // so that TrueC (the true value) is larger than FalseC.
23788 bool NeedsCondInvert = false;
23790 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
23791 // Efficiently invertible.
23792 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
23793 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
23794 isa<ConstantSDNode>(Cond.getOperand(1))))) {
23795 NeedsCondInvert = true;
23796 std::swap(TrueC, FalseC);
23799 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
23800 if (FalseC->getAPIntValue() == 0 &&
23801 TrueC->getAPIntValue().isPowerOf2()) {
23802 if (NeedsCondInvert) // Invert the condition if needed.
23803 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
23804 DAG.getConstant(1, DL, Cond.getValueType()));
23806 // Zero extend the condition if needed.
23807 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
23809 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
23810 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
23811 DAG.getConstant(ShAmt, DL, MVT::i8));
23814 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
23815 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
23816 if (NeedsCondInvert) // Invert the condition if needed.
23817 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
23818 DAG.getConstant(1, DL, Cond.getValueType()));
23820 // Zero extend the condition if needed.
23821 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
23822 FalseC->getValueType(0), Cond);
23823 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
23824 SDValue(FalseC, 0));
23827 // Optimize cases that will turn into an LEA instruction. This requires
23828 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
23829 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
23830 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
23831 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
23833 bool isFastMultiplier = false;
23835 switch ((unsigned char)Diff) {
23837 case 1: // result = add base, cond
23838 case 2: // result = lea base( , cond*2)
23839 case 3: // result = lea base(cond, cond*2)
23840 case 4: // result = lea base( , cond*4)
23841 case 5: // result = lea base(cond, cond*4)
23842 case 8: // result = lea base( , cond*8)
23843 case 9: // result = lea base(cond, cond*8)
23844 isFastMultiplier = true;
23849 if (isFastMultiplier) {
23850 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
23851 if (NeedsCondInvert) // Invert the condition if needed.
23852 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
23853 DAG.getConstant(1, DL, Cond.getValueType()));
23855 // Zero extend the condition if needed.
23856 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
23858 // Scale the condition by the difference.
23860 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
23861 DAG.getConstant(Diff, DL,
23862 Cond.getValueType()));
23864 // Add the base if non-zero.
23865 if (FalseC->getAPIntValue() != 0)
23866 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
23867 SDValue(FalseC, 0));
23874 // Canonicalize max and min:
23875 // (x > y) ? x : y -> (x >= y) ? x : y
23876 // (x < y) ? x : y -> (x <= y) ? x : y
23877 // This allows use of COND_S / COND_NS (see TranslateX86CC) which eliminates
23878 // the need for an extra compare
23879 // against zero. e.g.
23880 // (x - y) > 0 : (x - y) ? 0 -> (x - y) >= 0 : (x - y) ? 0
23882 // testl %edi, %edi
23884 // cmovgl %edi, %eax
23888 // cmovsl %eax, %edi
23889 if (N->getOpcode() == ISD::SELECT && Cond.getOpcode() == ISD::SETCC &&
23890 DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
23891 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
23892 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
23897 ISD::CondCode NewCC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGE;
23898 Cond = DAG.getSetCC(SDLoc(Cond), Cond.getValueType(),
23899 Cond.getOperand(0), Cond.getOperand(1), NewCC);
23900 return DAG.getNode(ISD::SELECT, DL, VT, Cond, LHS, RHS);
23905 // Early exit check
23906 if (!TLI.isTypeLegal(VT))
23909 // Match VSELECTs into subs with unsigned saturation.
23910 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC &&
23911 // psubus is available in SSE2 and AVX2 for i8 and i16 vectors.
23912 ((Subtarget->hasSSE2() && (VT == MVT::v16i8 || VT == MVT::v8i16)) ||
23913 (Subtarget->hasAVX2() && (VT == MVT::v32i8 || VT == MVT::v16i16)))) {
23914 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
23916 // Check if one of the arms of the VSELECT is a zero vector. If it's on the
23917 // left side invert the predicate to simplify logic below.
23919 if (ISD::isBuildVectorAllZeros(LHS.getNode())) {
23921 CC = ISD::getSetCCInverse(CC, true);
23922 } else if (ISD::isBuildVectorAllZeros(RHS.getNode())) {
23926 if (Other.getNode() && Other->getNumOperands() == 2 &&
23927 DAG.isEqualTo(Other->getOperand(0), Cond.getOperand(0))) {
23928 SDValue OpLHS = Other->getOperand(0), OpRHS = Other->getOperand(1);
23929 SDValue CondRHS = Cond->getOperand(1);
23931 // Look for a general sub with unsigned saturation first.
23932 // x >= y ? x-y : 0 --> subus x, y
23933 // x > y ? x-y : 0 --> subus x, y
23934 if ((CC == ISD::SETUGE || CC == ISD::SETUGT) &&
23935 Other->getOpcode() == ISD::SUB && DAG.isEqualTo(OpRHS, CondRHS))
23936 return DAG.getNode(X86ISD::SUBUS, DL, VT, OpLHS, OpRHS);
23938 if (auto *OpRHSBV = dyn_cast<BuildVectorSDNode>(OpRHS))
23939 if (auto *OpRHSConst = OpRHSBV->getConstantSplatNode()) {
23940 if (auto *CondRHSBV = dyn_cast<BuildVectorSDNode>(CondRHS))
23941 if (auto *CondRHSConst = CondRHSBV->getConstantSplatNode())
23942 // If the RHS is a constant we have to reverse the const
23943 // canonicalization.
23944 // x > C-1 ? x+-C : 0 --> subus x, C
23945 if (CC == ISD::SETUGT && Other->getOpcode() == ISD::ADD &&
23946 CondRHSConst->getAPIntValue() ==
23947 (-OpRHSConst->getAPIntValue() - 1))
23948 return DAG.getNode(
23949 X86ISD::SUBUS, DL, VT, OpLHS,
23950 DAG.getConstant(-OpRHSConst->getAPIntValue(), DL, VT));
23952 // Another special case: If C was a sign bit, the sub has been
23953 // canonicalized into a xor.
23954 // FIXME: Would it be better to use computeKnownBits to determine
23955 // whether it's safe to decanonicalize the xor?
23956 // x s< 0 ? x^C : 0 --> subus x, C
23957 if (CC == ISD::SETLT && Other->getOpcode() == ISD::XOR &&
23958 ISD::isBuildVectorAllZeros(CondRHS.getNode()) &&
23959 OpRHSConst->getAPIntValue().isSignBit())
23960 // Note that we have to rebuild the RHS constant here to ensure we
23961 // don't rely on particular values of undef lanes.
23962 return DAG.getNode(
23963 X86ISD::SUBUS, DL, VT, OpLHS,
23964 DAG.getConstant(OpRHSConst->getAPIntValue(), DL, VT));
23969 // Simplify vector selection if condition value type matches vselect
23971 if (N->getOpcode() == ISD::VSELECT && CondVT == VT) {
23972 assert(Cond.getValueType().isVector() &&
23973 "vector select expects a vector selector!");
23975 bool TValIsAllOnes = ISD::isBuildVectorAllOnes(LHS.getNode());
23976 bool FValIsAllZeros = ISD::isBuildVectorAllZeros(RHS.getNode());
23978 // Try invert the condition if true value is not all 1s and false value
23980 if (!TValIsAllOnes && !FValIsAllZeros &&
23981 // Check if the selector will be produced by CMPP*/PCMP*
23982 Cond.getOpcode() == ISD::SETCC &&
23983 // Check if SETCC has already been promoted
23984 TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT) ==
23986 bool TValIsAllZeros = ISD::isBuildVectorAllZeros(LHS.getNode());
23987 bool FValIsAllOnes = ISD::isBuildVectorAllOnes(RHS.getNode());
23989 if (TValIsAllZeros || FValIsAllOnes) {
23990 SDValue CC = Cond.getOperand(2);
23991 ISD::CondCode NewCC =
23992 ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
23993 Cond.getOperand(0).getValueType().isInteger());
23994 Cond = DAG.getSetCC(DL, CondVT, Cond.getOperand(0), Cond.getOperand(1), NewCC);
23995 std::swap(LHS, RHS);
23996 TValIsAllOnes = FValIsAllOnes;
23997 FValIsAllZeros = TValIsAllZeros;
24001 if (TValIsAllOnes || FValIsAllZeros) {
24004 if (TValIsAllOnes && FValIsAllZeros)
24006 else if (TValIsAllOnes)
24008 DAG.getNode(ISD::OR, DL, CondVT, Cond, DAG.getBitcast(CondVT, RHS));
24009 else if (FValIsAllZeros)
24010 Ret = DAG.getNode(ISD::AND, DL, CondVT, Cond,
24011 DAG.getBitcast(CondVT, LHS));
24013 return DAG.getBitcast(VT, Ret);
24017 // We should generate an X86ISD::BLENDI from a vselect if its argument
24018 // is a sign_extend_inreg of an any_extend of a BUILD_VECTOR of
24019 // constants. This specific pattern gets generated when we split a
24020 // selector for a 512 bit vector in a machine without AVX512 (but with
24021 // 256-bit vectors), during legalization:
24023 // (vselect (sign_extend (any_extend (BUILD_VECTOR)) i1) LHS RHS)
24025 // Iff we find this pattern and the build_vectors are built from
24026 // constants, we translate the vselect into a shuffle_vector that we
24027 // know will be matched by LowerVECTOR_SHUFFLEtoBlend.
24028 if ((N->getOpcode() == ISD::VSELECT ||
24029 N->getOpcode() == X86ISD::SHRUNKBLEND) &&
24030 !DCI.isBeforeLegalize() && !VT.is512BitVector()) {
24031 SDValue Shuffle = transformVSELECTtoBlendVECTOR_SHUFFLE(N, DAG, Subtarget);
24032 if (Shuffle.getNode())
24036 // If this is a *dynamic* select (non-constant condition) and we can match
24037 // this node with one of the variable blend instructions, restructure the
24038 // condition so that the blends can use the high bit of each element and use
24039 // SimplifyDemandedBits to simplify the condition operand.
24040 if (N->getOpcode() == ISD::VSELECT && DCI.isBeforeLegalizeOps() &&
24041 !DCI.isBeforeLegalize() &&
24042 !ISD::isBuildVectorOfConstantSDNodes(Cond.getNode())) {
24043 unsigned BitWidth = Cond.getValueType().getScalarSizeInBits();
24045 // Don't optimize vector selects that map to mask-registers.
24049 // We can only handle the cases where VSELECT is directly legal on the
24050 // subtarget. We custom lower VSELECT nodes with constant conditions and
24051 // this makes it hard to see whether a dynamic VSELECT will correctly
24052 // lower, so we both check the operation's status and explicitly handle the
24053 // cases where a *dynamic* blend will fail even though a constant-condition
24054 // blend could be custom lowered.
24055 // FIXME: We should find a better way to handle this class of problems.
24056 // Potentially, we should combine constant-condition vselect nodes
24057 // pre-legalization into shuffles and not mark as many types as custom
24059 if (!TLI.isOperationLegalOrCustom(ISD::VSELECT, VT))
24061 // FIXME: We don't support i16-element blends currently. We could and
24062 // should support them by making *all* the bits in the condition be set
24063 // rather than just the high bit and using an i8-element blend.
24064 if (VT.getVectorElementType() == MVT::i16)
24066 // Dynamic blending was only available from SSE4.1 onward.
24067 if (VT.is128BitVector() && !Subtarget->hasSSE41())
24069 // Byte blends are only available in AVX2
24070 if (VT == MVT::v32i8 && !Subtarget->hasAVX2())
24073 assert(BitWidth >= 8 && BitWidth <= 64 && "Invalid mask size");
24074 APInt DemandedMask = APInt::getHighBitsSet(BitWidth, 1);
24076 APInt KnownZero, KnownOne;
24077 TargetLowering::TargetLoweringOpt TLO(DAG, DCI.isBeforeLegalize(),
24078 DCI.isBeforeLegalizeOps());
24079 if (TLO.ShrinkDemandedConstant(Cond, DemandedMask) ||
24080 TLI.SimplifyDemandedBits(Cond, DemandedMask, KnownZero, KnownOne,
24082 // If we changed the computation somewhere in the DAG, this change
24083 // will affect all users of Cond.
24084 // Make sure it is fine and update all the nodes so that we do not
24085 // use the generic VSELECT anymore. Otherwise, we may perform
24086 // wrong optimizations as we messed up with the actual expectation
24087 // for the vector boolean values.
24088 if (Cond != TLO.Old) {
24089 // Check all uses of that condition operand to check whether it will be
24090 // consumed by non-BLEND instructions, which may depend on all bits are
24092 for (SDNode::use_iterator I = Cond->use_begin(), E = Cond->use_end();
24094 if (I->getOpcode() != ISD::VSELECT)
24095 // TODO: Add other opcodes eventually lowered into BLEND.
24098 // Update all the users of the condition, before committing the change,
24099 // so that the VSELECT optimizations that expect the correct vector
24100 // boolean value will not be triggered.
24101 for (SDNode::use_iterator I = Cond->use_begin(), E = Cond->use_end();
24103 DAG.ReplaceAllUsesOfValueWith(
24105 DAG.getNode(X86ISD::SHRUNKBLEND, SDLoc(*I), I->getValueType(0),
24106 Cond, I->getOperand(1), I->getOperand(2)));
24107 DCI.CommitTargetLoweringOpt(TLO);
24110 // At this point, only Cond is changed. Change the condition
24111 // just for N to keep the opportunity to optimize all other
24112 // users their own way.
24113 DAG.ReplaceAllUsesOfValueWith(
24115 DAG.getNode(X86ISD::SHRUNKBLEND, SDLoc(N), N->getValueType(0),
24116 TLO.New, N->getOperand(1), N->getOperand(2)));
24124 // Check whether a boolean test is testing a boolean value generated by
24125 // X86ISD::SETCC. If so, return the operand of that SETCC and proper condition
24128 // Simplify the following patterns:
24129 // (Op (CMP (SETCC Cond EFLAGS) 1) EQ) or
24130 // (Op (CMP (SETCC Cond EFLAGS) 0) NEQ)
24131 // to (Op EFLAGS Cond)
24133 // (Op (CMP (SETCC Cond EFLAGS) 0) EQ) or
24134 // (Op (CMP (SETCC Cond EFLAGS) 1) NEQ)
24135 // to (Op EFLAGS !Cond)
24137 // where Op could be BRCOND or CMOV.
24139 static SDValue checkBoolTestSetCCCombine(SDValue Cmp, X86::CondCode &CC) {
24140 // Quit if not CMP and SUB with its value result used.
24141 if (Cmp.getOpcode() != X86ISD::CMP &&
24142 (Cmp.getOpcode() != X86ISD::SUB || Cmp.getNode()->hasAnyUseOfValue(0)))
24145 // Quit if not used as a boolean value.
24146 if (CC != X86::COND_E && CC != X86::COND_NE)
24149 // Check CMP operands. One of them should be 0 or 1 and the other should be
24150 // an SetCC or extended from it.
24151 SDValue Op1 = Cmp.getOperand(0);
24152 SDValue Op2 = Cmp.getOperand(1);
24155 const ConstantSDNode* C = nullptr;
24156 bool needOppositeCond = (CC == X86::COND_E);
24157 bool checkAgainstTrue = false; // Is it a comparison against 1?
24159 if ((C = dyn_cast<ConstantSDNode>(Op1)))
24161 else if ((C = dyn_cast<ConstantSDNode>(Op2)))
24163 else // Quit if all operands are not constants.
24166 if (C->getZExtValue() == 1) {
24167 needOppositeCond = !needOppositeCond;
24168 checkAgainstTrue = true;
24169 } else if (C->getZExtValue() != 0)
24170 // Quit if the constant is neither 0 or 1.
24173 bool truncatedToBoolWithAnd = false;
24174 // Skip (zext $x), (trunc $x), or (and $x, 1) node.
24175 while (SetCC.getOpcode() == ISD::ZERO_EXTEND ||
24176 SetCC.getOpcode() == ISD::TRUNCATE ||
24177 SetCC.getOpcode() == ISD::AND) {
24178 if (SetCC.getOpcode() == ISD::AND) {
24180 ConstantSDNode *CS;
24181 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(0))) &&
24182 CS->getZExtValue() == 1)
24184 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(1))) &&
24185 CS->getZExtValue() == 1)
24189 SetCC = SetCC.getOperand(OpIdx);
24190 truncatedToBoolWithAnd = true;
24192 SetCC = SetCC.getOperand(0);
24195 switch (SetCC.getOpcode()) {
24196 case X86ISD::SETCC_CARRY:
24197 // Since SETCC_CARRY gives output based on R = CF ? ~0 : 0, it's unsafe to
24198 // simplify it if the result of SETCC_CARRY is not canonicalized to 0 or 1,
24199 // i.e. it's a comparison against true but the result of SETCC_CARRY is not
24200 // truncated to i1 using 'and'.
24201 if (checkAgainstTrue && !truncatedToBoolWithAnd)
24203 assert(X86::CondCode(SetCC.getConstantOperandVal(0)) == X86::COND_B &&
24204 "Invalid use of SETCC_CARRY!");
24206 case X86ISD::SETCC:
24207 // Set the condition code or opposite one if necessary.
24208 CC = X86::CondCode(SetCC.getConstantOperandVal(0));
24209 if (needOppositeCond)
24210 CC = X86::GetOppositeBranchCondition(CC);
24211 return SetCC.getOperand(1);
24212 case X86ISD::CMOV: {
24213 // Check whether false/true value has canonical one, i.e. 0 or 1.
24214 ConstantSDNode *FVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(0));
24215 ConstantSDNode *TVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(1));
24216 // Quit if true value is not a constant.
24219 // Quit if false value is not a constant.
24221 SDValue Op = SetCC.getOperand(0);
24222 // Skip 'zext' or 'trunc' node.
24223 if (Op.getOpcode() == ISD::ZERO_EXTEND ||
24224 Op.getOpcode() == ISD::TRUNCATE)
24225 Op = Op.getOperand(0);
24226 // A special case for rdrand/rdseed, where 0 is set if false cond is
24228 if ((Op.getOpcode() != X86ISD::RDRAND &&
24229 Op.getOpcode() != X86ISD::RDSEED) || Op.getResNo() != 0)
24232 // Quit if false value is not the constant 0 or 1.
24233 bool FValIsFalse = true;
24234 if (FVal && FVal->getZExtValue() != 0) {
24235 if (FVal->getZExtValue() != 1)
24237 // If FVal is 1, opposite cond is needed.
24238 needOppositeCond = !needOppositeCond;
24239 FValIsFalse = false;
24241 // Quit if TVal is not the constant opposite of FVal.
24242 if (FValIsFalse && TVal->getZExtValue() != 1)
24244 if (!FValIsFalse && TVal->getZExtValue() != 0)
24246 CC = X86::CondCode(SetCC.getConstantOperandVal(2));
24247 if (needOppositeCond)
24248 CC = X86::GetOppositeBranchCondition(CC);
24249 return SetCC.getOperand(3);
24256 /// Check whether Cond is an AND/OR of SETCCs off of the same EFLAGS.
24258 /// (X86or (X86setcc) (X86setcc))
24259 /// (X86cmp (and (X86setcc) (X86setcc)), 0)
24260 static bool checkBoolTestAndOrSetCCCombine(SDValue Cond, X86::CondCode &CC0,
24261 X86::CondCode &CC1, SDValue &Flags,
24263 if (Cond->getOpcode() == X86ISD::CMP) {
24264 ConstantSDNode *CondOp1C = dyn_cast<ConstantSDNode>(Cond->getOperand(1));
24265 if (!CondOp1C || !CondOp1C->isNullValue())
24268 Cond = Cond->getOperand(0);
24273 SDValue SetCC0, SetCC1;
24274 switch (Cond->getOpcode()) {
24275 default: return false;
24282 SetCC0 = Cond->getOperand(0);
24283 SetCC1 = Cond->getOperand(1);
24287 // Make sure we have SETCC nodes, using the same flags value.
24288 if (SetCC0.getOpcode() != X86ISD::SETCC ||
24289 SetCC1.getOpcode() != X86ISD::SETCC ||
24290 SetCC0->getOperand(1) != SetCC1->getOperand(1))
24293 CC0 = (X86::CondCode)SetCC0->getConstantOperandVal(0);
24294 CC1 = (X86::CondCode)SetCC1->getConstantOperandVal(0);
24295 Flags = SetCC0->getOperand(1);
24299 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
24300 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
24301 TargetLowering::DAGCombinerInfo &DCI,
24302 const X86Subtarget *Subtarget) {
24305 // If the flag operand isn't dead, don't touch this CMOV.
24306 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
24309 SDValue FalseOp = N->getOperand(0);
24310 SDValue TrueOp = N->getOperand(1);
24311 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
24312 SDValue Cond = N->getOperand(3);
24314 if (CC == X86::COND_E || CC == X86::COND_NE) {
24315 switch (Cond.getOpcode()) {
24319 // If operand of BSR / BSF are proven never zero, then ZF cannot be set.
24320 if (DAG.isKnownNeverZero(Cond.getOperand(0)))
24321 return (CC == X86::COND_E) ? FalseOp : TrueOp;
24327 Flags = checkBoolTestSetCCCombine(Cond, CC);
24328 if (Flags.getNode() &&
24329 // Extra check as FCMOV only supports a subset of X86 cond.
24330 (FalseOp.getValueType() != MVT::f80 || hasFPCMov(CC))) {
24331 SDValue Ops[] = { FalseOp, TrueOp,
24332 DAG.getConstant(CC, DL, MVT::i8), Flags };
24333 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), Ops);
24336 // If this is a select between two integer constants, try to do some
24337 // optimizations. Note that the operands are ordered the opposite of SELECT
24339 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(TrueOp)) {
24340 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(FalseOp)) {
24341 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
24342 // larger than FalseC (the false value).
24343 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
24344 CC = X86::GetOppositeBranchCondition(CC);
24345 std::swap(TrueC, FalseC);
24346 std::swap(TrueOp, FalseOp);
24349 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
24350 // This is efficient for any integer data type (including i8/i16) and
24352 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
24353 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
24354 DAG.getConstant(CC, DL, MVT::i8), Cond);
24356 // Zero extend the condition if needed.
24357 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
24359 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
24360 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
24361 DAG.getConstant(ShAmt, DL, MVT::i8));
24362 if (N->getNumValues() == 2) // Dead flag value?
24363 return DCI.CombineTo(N, Cond, SDValue());
24367 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
24368 // for any integer data type, including i8/i16.
24369 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
24370 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
24371 DAG.getConstant(CC, DL, MVT::i8), Cond);
24373 // Zero extend the condition if needed.
24374 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
24375 FalseC->getValueType(0), Cond);
24376 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
24377 SDValue(FalseC, 0));
24379 if (N->getNumValues() == 2) // Dead flag value?
24380 return DCI.CombineTo(N, Cond, SDValue());
24384 // Optimize cases that will turn into an LEA instruction. This requires
24385 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
24386 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
24387 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
24388 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
24390 bool isFastMultiplier = false;
24392 switch ((unsigned char)Diff) {
24394 case 1: // result = add base, cond
24395 case 2: // result = lea base( , cond*2)
24396 case 3: // result = lea base(cond, cond*2)
24397 case 4: // result = lea base( , cond*4)
24398 case 5: // result = lea base(cond, cond*4)
24399 case 8: // result = lea base( , cond*8)
24400 case 9: // result = lea base(cond, cond*8)
24401 isFastMultiplier = true;
24406 if (isFastMultiplier) {
24407 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
24408 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
24409 DAG.getConstant(CC, DL, MVT::i8), Cond);
24410 // Zero extend the condition if needed.
24411 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
24413 // Scale the condition by the difference.
24415 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
24416 DAG.getConstant(Diff, DL, Cond.getValueType()));
24418 // Add the base if non-zero.
24419 if (FalseC->getAPIntValue() != 0)
24420 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
24421 SDValue(FalseC, 0));
24422 if (N->getNumValues() == 2) // Dead flag value?
24423 return DCI.CombineTo(N, Cond, SDValue());
24430 // Handle these cases:
24431 // (select (x != c), e, c) -> select (x != c), e, x),
24432 // (select (x == c), c, e) -> select (x == c), x, e)
24433 // where the c is an integer constant, and the "select" is the combination
24434 // of CMOV and CMP.
24436 // The rationale for this change is that the conditional-move from a constant
24437 // needs two instructions, however, conditional-move from a register needs
24438 // only one instruction.
24440 // CAVEAT: By replacing a constant with a symbolic value, it may obscure
24441 // some instruction-combining opportunities. This opt needs to be
24442 // postponed as late as possible.
24444 if (!DCI.isBeforeLegalize() && !DCI.isBeforeLegalizeOps()) {
24445 // the DCI.xxxx conditions are provided to postpone the optimization as
24446 // late as possible.
24448 ConstantSDNode *CmpAgainst = nullptr;
24449 if ((Cond.getOpcode() == X86ISD::CMP || Cond.getOpcode() == X86ISD::SUB) &&
24450 (CmpAgainst = dyn_cast<ConstantSDNode>(Cond.getOperand(1))) &&
24451 !isa<ConstantSDNode>(Cond.getOperand(0))) {
24453 if (CC == X86::COND_NE &&
24454 CmpAgainst == dyn_cast<ConstantSDNode>(FalseOp)) {
24455 CC = X86::GetOppositeBranchCondition(CC);
24456 std::swap(TrueOp, FalseOp);
24459 if (CC == X86::COND_E &&
24460 CmpAgainst == dyn_cast<ConstantSDNode>(TrueOp)) {
24461 SDValue Ops[] = { FalseOp, Cond.getOperand(0),
24462 DAG.getConstant(CC, DL, MVT::i8), Cond };
24463 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList (), Ops);
24468 // Fold and/or of setcc's to double CMOV:
24469 // (CMOV F, T, ((cc1 | cc2) != 0)) -> (CMOV (CMOV F, T, cc1), T, cc2)
24470 // (CMOV F, T, ((cc1 & cc2) != 0)) -> (CMOV (CMOV T, F, !cc1), F, !cc2)
24472 // This combine lets us generate:
24473 // cmovcc1 (jcc1 if we don't have CMOV)
24479 // cmovne (jne if we don't have CMOV)
24480 // When we can't use the CMOV instruction, it might increase branch
24482 // When we can use CMOV, or when there is no mispredict, this improves
24483 // throughput and reduces register pressure.
24485 if (CC == X86::COND_NE) {
24487 X86::CondCode CC0, CC1;
24489 if (checkBoolTestAndOrSetCCCombine(Cond, CC0, CC1, Flags, isAndSetCC)) {
24491 std::swap(FalseOp, TrueOp);
24492 CC0 = X86::GetOppositeBranchCondition(CC0);
24493 CC1 = X86::GetOppositeBranchCondition(CC1);
24496 SDValue LOps[] = {FalseOp, TrueOp, DAG.getConstant(CC0, DL, MVT::i8),
24498 SDValue LCMOV = DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), LOps);
24499 SDValue Ops[] = {LCMOV, TrueOp, DAG.getConstant(CC1, DL, MVT::i8), Flags};
24500 SDValue CMOV = DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), Ops);
24501 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), SDValue(CMOV.getNode(), 1));
24509 /// PerformMulCombine - Optimize a single multiply with constant into two
24510 /// in order to implement it with two cheaper instructions, e.g.
24511 /// LEA + SHL, LEA + LEA.
24512 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
24513 TargetLowering::DAGCombinerInfo &DCI) {
24514 // An imul is usually smaller than the alternative sequence.
24515 if (DAG.getMachineFunction().getFunction()->optForMinSize())
24518 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
24521 EVT VT = N->getValueType(0);
24522 if (VT != MVT::i64 && VT != MVT::i32)
24525 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
24528 uint64_t MulAmt = C->getZExtValue();
24529 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
24532 uint64_t MulAmt1 = 0;
24533 uint64_t MulAmt2 = 0;
24534 if ((MulAmt % 9) == 0) {
24536 MulAmt2 = MulAmt / 9;
24537 } else if ((MulAmt % 5) == 0) {
24539 MulAmt2 = MulAmt / 5;
24540 } else if ((MulAmt % 3) == 0) {
24542 MulAmt2 = MulAmt / 3;
24545 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
24548 if (isPowerOf2_64(MulAmt2) &&
24549 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
24550 // If second multiplifer is pow2, issue it first. We want the multiply by
24551 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
24553 std::swap(MulAmt1, MulAmt2);
24556 if (isPowerOf2_64(MulAmt1))
24557 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
24558 DAG.getConstant(Log2_64(MulAmt1), DL, MVT::i8));
24560 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
24561 DAG.getConstant(MulAmt1, DL, VT));
24563 if (isPowerOf2_64(MulAmt2))
24564 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
24565 DAG.getConstant(Log2_64(MulAmt2), DL, MVT::i8));
24567 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
24568 DAG.getConstant(MulAmt2, DL, VT));
24570 // Do not add new nodes to DAG combiner worklist.
24571 DCI.CombineTo(N, NewMul, false);
24576 static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) {
24577 SDValue N0 = N->getOperand(0);
24578 SDValue N1 = N->getOperand(1);
24579 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
24580 EVT VT = N0.getValueType();
24582 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2))
24583 // since the result of setcc_c is all zero's or all ones.
24584 if (VT.isInteger() && !VT.isVector() &&
24585 N1C && N0.getOpcode() == ISD::AND &&
24586 N0.getOperand(1).getOpcode() == ISD::Constant) {
24587 SDValue N00 = N0.getOperand(0);
24588 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
24589 APInt ShAmt = N1C->getAPIntValue();
24590 Mask = Mask.shl(ShAmt);
24591 bool MaskOK = false;
24592 // We can handle cases concerning bit-widening nodes containing setcc_c if
24593 // we carefully interrogate the mask to make sure we are semantics
24595 // The transform is not safe if the result of C1 << C2 exceeds the bitwidth
24596 // of the underlying setcc_c operation if the setcc_c was zero extended.
24597 // Consider the following example:
24598 // zext(setcc_c) -> i32 0x0000FFFF
24599 // c1 -> i32 0x0000FFFF
24600 // c2 -> i32 0x00000001
24601 // (shl (and (setcc_c), c1), c2) -> i32 0x0001FFFE
24602 // (and setcc_c, (c1 << c2)) -> i32 0x0000FFFE
24603 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
24605 } else if (N00.getOpcode() == ISD::SIGN_EXTEND &&
24606 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
24608 } else if ((N00.getOpcode() == ISD::ZERO_EXTEND ||
24609 N00.getOpcode() == ISD::ANY_EXTEND) &&
24610 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
24611 MaskOK = Mask.isIntN(N00.getOperand(0).getValueSizeInBits());
24613 if (MaskOK && Mask != 0) {
24615 return DAG.getNode(ISD::AND, DL, VT, N00, DAG.getConstant(Mask, DL, VT));
24619 // Hardware support for vector shifts is sparse which makes us scalarize the
24620 // vector operations in many cases. Also, on sandybridge ADD is faster than
24622 // (shl V, 1) -> add V,V
24623 if (auto *N1BV = dyn_cast<BuildVectorSDNode>(N1))
24624 if (auto *N1SplatC = N1BV->getConstantSplatNode()) {
24625 assert(N0.getValueType().isVector() && "Invalid vector shift type");
24626 // We shift all of the values by one. In many cases we do not have
24627 // hardware support for this operation. This is better expressed as an ADD
24629 if (N1SplatC->getAPIntValue() == 1)
24630 return DAG.getNode(ISD::ADD, SDLoc(N), VT, N0, N0);
24636 /// \brief Returns a vector of 0s if the node in input is a vector logical
24637 /// shift by a constant amount which is known to be bigger than or equal
24638 /// to the vector element size in bits.
24639 static SDValue performShiftToAllZeros(SDNode *N, SelectionDAG &DAG,
24640 const X86Subtarget *Subtarget) {
24641 EVT VT = N->getValueType(0);
24643 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16 &&
24644 (!Subtarget->hasInt256() ||
24645 (VT != MVT::v4i64 && VT != MVT::v8i32 && VT != MVT::v16i16)))
24648 SDValue Amt = N->getOperand(1);
24650 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Amt))
24651 if (auto *AmtSplat = AmtBV->getConstantSplatNode()) {
24652 APInt ShiftAmt = AmtSplat->getAPIntValue();
24653 unsigned MaxAmount =
24654 VT.getSimpleVT().getVectorElementType().getSizeInBits();
24656 // SSE2/AVX2 logical shifts always return a vector of 0s
24657 // if the shift amount is bigger than or equal to
24658 // the element size. The constant shift amount will be
24659 // encoded as a 8-bit immediate.
24660 if (ShiftAmt.trunc(8).uge(MaxAmount))
24661 return getZeroVector(VT, Subtarget, DAG, DL);
24667 /// PerformShiftCombine - Combine shifts.
24668 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
24669 TargetLowering::DAGCombinerInfo &DCI,
24670 const X86Subtarget *Subtarget) {
24671 if (N->getOpcode() == ISD::SHL)
24672 if (SDValue V = PerformSHLCombine(N, DAG))
24675 // Try to fold this logical shift into a zero vector.
24676 if (N->getOpcode() != ISD::SRA)
24677 if (SDValue V = performShiftToAllZeros(N, DAG, Subtarget))
24683 // CMPEQCombine - Recognize the distinctive (AND (setcc ...) (setcc ..))
24684 // where both setccs reference the same FP CMP, and rewrite for CMPEQSS
24685 // and friends. Likewise for OR -> CMPNEQSS.
24686 static SDValue CMPEQCombine(SDNode *N, SelectionDAG &DAG,
24687 TargetLowering::DAGCombinerInfo &DCI,
24688 const X86Subtarget *Subtarget) {
24691 // SSE1 supports CMP{eq|ne}SS, and SSE2 added CMP{eq|ne}SD, but
24692 // we're requiring SSE2 for both.
24693 if (Subtarget->hasSSE2() && isAndOrOfSetCCs(SDValue(N, 0U), opcode)) {
24694 SDValue N0 = N->getOperand(0);
24695 SDValue N1 = N->getOperand(1);
24696 SDValue CMP0 = N0->getOperand(1);
24697 SDValue CMP1 = N1->getOperand(1);
24700 // The SETCCs should both refer to the same CMP.
24701 if (CMP0.getOpcode() != X86ISD::CMP || CMP0 != CMP1)
24704 SDValue CMP00 = CMP0->getOperand(0);
24705 SDValue CMP01 = CMP0->getOperand(1);
24706 EVT VT = CMP00.getValueType();
24708 if (VT == MVT::f32 || VT == MVT::f64) {
24709 bool ExpectingFlags = false;
24710 // Check for any users that want flags:
24711 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
24712 !ExpectingFlags && UI != UE; ++UI)
24713 switch (UI->getOpcode()) {
24718 ExpectingFlags = true;
24720 case ISD::CopyToReg:
24721 case ISD::SIGN_EXTEND:
24722 case ISD::ZERO_EXTEND:
24723 case ISD::ANY_EXTEND:
24727 if (!ExpectingFlags) {
24728 enum X86::CondCode cc0 = (enum X86::CondCode)N0.getConstantOperandVal(0);
24729 enum X86::CondCode cc1 = (enum X86::CondCode)N1.getConstantOperandVal(0);
24731 if (cc1 == X86::COND_E || cc1 == X86::COND_NE) {
24732 X86::CondCode tmp = cc0;
24737 if ((cc0 == X86::COND_E && cc1 == X86::COND_NP) ||
24738 (cc0 == X86::COND_NE && cc1 == X86::COND_P)) {
24739 // FIXME: need symbolic constants for these magic numbers.
24740 // See X86ATTInstPrinter.cpp:printSSECC().
24741 unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4;
24742 if (Subtarget->hasAVX512()) {
24743 SDValue FSetCC = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CMP00,
24745 DAG.getConstant(x86cc, DL, MVT::i8));
24746 if (N->getValueType(0) != MVT::i1)
24747 return DAG.getNode(ISD::ZERO_EXTEND, DL, N->getValueType(0),
24751 SDValue OnesOrZeroesF = DAG.getNode(X86ISD::FSETCC, DL,
24752 CMP00.getValueType(), CMP00, CMP01,
24753 DAG.getConstant(x86cc, DL,
24756 bool is64BitFP = (CMP00.getValueType() == MVT::f64);
24757 MVT IntVT = is64BitFP ? MVT::i64 : MVT::i32;
24759 if (is64BitFP && !Subtarget->is64Bit()) {
24760 // On a 32-bit target, we cannot bitcast the 64-bit float to a
24761 // 64-bit integer, since that's not a legal type. Since
24762 // OnesOrZeroesF is all ones of all zeroes, we don't need all the
24763 // bits, but can do this little dance to extract the lowest 32 bits
24764 // and work with those going forward.
24765 SDValue Vector64 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2f64,
24767 SDValue Vector32 = DAG.getBitcast(MVT::v4f32, Vector64);
24768 OnesOrZeroesF = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32,
24769 Vector32, DAG.getIntPtrConstant(0, DL));
24773 SDValue OnesOrZeroesI = DAG.getBitcast(IntVT, OnesOrZeroesF);
24774 SDValue ANDed = DAG.getNode(ISD::AND, DL, IntVT, OnesOrZeroesI,
24775 DAG.getConstant(1, DL, IntVT));
24776 SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8,
24778 return OneBitOfTruth;
24786 /// CanFoldXORWithAllOnes - Test whether the XOR operand is a AllOnes vector
24787 /// so it can be folded inside ANDNP.
24788 static bool CanFoldXORWithAllOnes(const SDNode *N) {
24789 EVT VT = N->getValueType(0);
24791 // Match direct AllOnes for 128 and 256-bit vectors
24792 if (ISD::isBuildVectorAllOnes(N))
24795 // Look through a bit convert.
24796 if (N->getOpcode() == ISD::BITCAST)
24797 N = N->getOperand(0).getNode();
24799 // Sometimes the operand may come from a insert_subvector building a 256-bit
24801 if (VT.is256BitVector() &&
24802 N->getOpcode() == ISD::INSERT_SUBVECTOR) {
24803 SDValue V1 = N->getOperand(0);
24804 SDValue V2 = N->getOperand(1);
24806 if (V1.getOpcode() == ISD::INSERT_SUBVECTOR &&
24807 V1.getOperand(0).getOpcode() == ISD::UNDEF &&
24808 ISD::isBuildVectorAllOnes(V1.getOperand(1).getNode()) &&
24809 ISD::isBuildVectorAllOnes(V2.getNode()))
24816 // On AVX/AVX2 the type v8i1 is legalized to v8i16, which is an XMM sized
24817 // register. In most cases we actually compare or select YMM-sized registers
24818 // and mixing the two types creates horrible code. This method optimizes
24819 // some of the transition sequences.
24820 static SDValue WidenMaskArithmetic(SDNode *N, SelectionDAG &DAG,
24821 TargetLowering::DAGCombinerInfo &DCI,
24822 const X86Subtarget *Subtarget) {
24823 EVT VT = N->getValueType(0);
24824 if (!VT.is256BitVector())
24827 assert((N->getOpcode() == ISD::ANY_EXTEND ||
24828 N->getOpcode() == ISD::ZERO_EXTEND ||
24829 N->getOpcode() == ISD::SIGN_EXTEND) && "Invalid Node");
24831 SDValue Narrow = N->getOperand(0);
24832 EVT NarrowVT = Narrow->getValueType(0);
24833 if (!NarrowVT.is128BitVector())
24836 if (Narrow->getOpcode() != ISD::XOR &&
24837 Narrow->getOpcode() != ISD::AND &&
24838 Narrow->getOpcode() != ISD::OR)
24841 SDValue N0 = Narrow->getOperand(0);
24842 SDValue N1 = Narrow->getOperand(1);
24845 // The Left side has to be a trunc.
24846 if (N0.getOpcode() != ISD::TRUNCATE)
24849 // The type of the truncated inputs.
24850 EVT WideVT = N0->getOperand(0)->getValueType(0);
24854 // The right side has to be a 'trunc' or a constant vector.
24855 bool RHSTrunc = N1.getOpcode() == ISD::TRUNCATE;
24856 ConstantSDNode *RHSConstSplat = nullptr;
24857 if (auto *RHSBV = dyn_cast<BuildVectorSDNode>(N1))
24858 RHSConstSplat = RHSBV->getConstantSplatNode();
24859 if (!RHSTrunc && !RHSConstSplat)
24862 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
24864 if (!TLI.isOperationLegalOrPromote(Narrow->getOpcode(), WideVT))
24867 // Set N0 and N1 to hold the inputs to the new wide operation.
24868 N0 = N0->getOperand(0);
24869 if (RHSConstSplat) {
24870 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, WideVT.getVectorElementType(),
24871 SDValue(RHSConstSplat, 0));
24872 SmallVector<SDValue, 8> C(WideVT.getVectorNumElements(), N1);
24873 N1 = DAG.getNode(ISD::BUILD_VECTOR, DL, WideVT, C);
24874 } else if (RHSTrunc) {
24875 N1 = N1->getOperand(0);
24878 // Generate the wide operation.
24879 SDValue Op = DAG.getNode(Narrow->getOpcode(), DL, WideVT, N0, N1);
24880 unsigned Opcode = N->getOpcode();
24882 case ISD::ANY_EXTEND:
24884 case ISD::ZERO_EXTEND: {
24885 unsigned InBits = NarrowVT.getScalarSizeInBits();
24886 APInt Mask = APInt::getAllOnesValue(InBits);
24887 Mask = Mask.zext(VT.getScalarSizeInBits());
24888 return DAG.getNode(ISD::AND, DL, VT,
24889 Op, DAG.getConstant(Mask, DL, VT));
24891 case ISD::SIGN_EXTEND:
24892 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT,
24893 Op, DAG.getValueType(NarrowVT));
24895 llvm_unreachable("Unexpected opcode");
24899 static SDValue VectorZextCombine(SDNode *N, SelectionDAG &DAG,
24900 TargetLowering::DAGCombinerInfo &DCI,
24901 const X86Subtarget *Subtarget) {
24902 SDValue N0 = N->getOperand(0);
24903 SDValue N1 = N->getOperand(1);
24906 // A vector zext_in_reg may be represented as a shuffle,
24907 // feeding into a bitcast (this represents anyext) feeding into
24908 // an and with a mask.
24909 // We'd like to try to combine that into a shuffle with zero
24910 // plus a bitcast, removing the and.
24911 if (N0.getOpcode() != ISD::BITCAST ||
24912 N0.getOperand(0).getOpcode() != ISD::VECTOR_SHUFFLE)
24915 // The other side of the AND should be a splat of 2^C, where C
24916 // is the number of bits in the source type.
24917 if (N1.getOpcode() == ISD::BITCAST)
24918 N1 = N1.getOperand(0);
24919 if (N1.getOpcode() != ISD::BUILD_VECTOR)
24921 BuildVectorSDNode *Vector = cast<BuildVectorSDNode>(N1);
24923 ShuffleVectorSDNode *Shuffle = cast<ShuffleVectorSDNode>(N0.getOperand(0));
24924 EVT SrcType = Shuffle->getValueType(0);
24926 // We expect a single-source shuffle
24927 if (Shuffle->getOperand(1)->getOpcode() != ISD::UNDEF)
24930 unsigned SrcSize = SrcType.getScalarSizeInBits();
24932 APInt SplatValue, SplatUndef;
24933 unsigned SplatBitSize;
24935 if (!Vector->isConstantSplat(SplatValue, SplatUndef,
24936 SplatBitSize, HasAnyUndefs))
24939 unsigned ResSize = N1.getValueType().getScalarSizeInBits();
24940 // Make sure the splat matches the mask we expect
24941 if (SplatBitSize > ResSize ||
24942 (SplatValue + 1).exactLogBase2() != (int)SrcSize)
24945 // Make sure the input and output size make sense
24946 if (SrcSize >= ResSize || ResSize % SrcSize)
24949 // We expect a shuffle of the form <0, u, u, u, 1, u, u, u...>
24950 // The number of u's between each two values depends on the ratio between
24951 // the source and dest type.
24952 unsigned ZextRatio = ResSize / SrcSize;
24953 bool IsZext = true;
24954 for (unsigned i = 0; i < SrcType.getVectorNumElements(); ++i) {
24955 if (i % ZextRatio) {
24956 if (Shuffle->getMaskElt(i) > 0) {
24962 if (Shuffle->getMaskElt(i) != (int)(i / ZextRatio)) {
24963 // Expected element number
24973 // Ok, perform the transformation - replace the shuffle with
24974 // a shuffle of the form <0, k, k, k, 1, k, k, k> with zero
24975 // (instead of undef) where the k elements come from the zero vector.
24976 SmallVector<int, 8> Mask;
24977 unsigned NumElems = SrcType.getVectorNumElements();
24978 for (unsigned i = 0; i < NumElems; ++i)
24980 Mask.push_back(NumElems);
24982 Mask.push_back(i / ZextRatio);
24984 SDValue NewShuffle = DAG.getVectorShuffle(Shuffle->getValueType(0), DL,
24985 Shuffle->getOperand(0), DAG.getConstant(0, DL, SrcType), Mask);
24986 return DAG.getBitcast(N0.getValueType(), NewShuffle);
24989 /// If both input operands of a logic op are being cast from floating point
24990 /// types, try to convert this into a floating point logic node to avoid
24991 /// unnecessary moves from SSE to integer registers.
24992 static SDValue convertIntLogicToFPLogic(SDNode *N, SelectionDAG &DAG,
24993 const X86Subtarget *Subtarget) {
24994 unsigned FPOpcode = ISD::DELETED_NODE;
24995 if (N->getOpcode() == ISD::AND)
24996 FPOpcode = X86ISD::FAND;
24997 else if (N->getOpcode() == ISD::OR)
24998 FPOpcode = X86ISD::FOR;
24999 else if (N->getOpcode() == ISD::XOR)
25000 FPOpcode = X86ISD::FXOR;
25002 assert(FPOpcode != ISD::DELETED_NODE &&
25003 "Unexpected input node for FP logic conversion");
25005 EVT VT = N->getValueType(0);
25006 SDValue N0 = N->getOperand(0);
25007 SDValue N1 = N->getOperand(1);
25009 if (N0.getOpcode() == ISD::BITCAST && N1.getOpcode() == ISD::BITCAST &&
25010 ((Subtarget->hasSSE1() && VT == MVT::i32) ||
25011 (Subtarget->hasSSE2() && VT == MVT::i64))) {
25012 SDValue N00 = N0.getOperand(0);
25013 SDValue N10 = N1.getOperand(0);
25014 EVT N00Type = N00.getValueType();
25015 EVT N10Type = N10.getValueType();
25016 if (N00Type.isFloatingPoint() && N10Type.isFloatingPoint()) {
25017 SDValue FPLogic = DAG.getNode(FPOpcode, DL, N00Type, N00, N10);
25018 return DAG.getBitcast(VT, FPLogic);
25024 static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG,
25025 TargetLowering::DAGCombinerInfo &DCI,
25026 const X86Subtarget *Subtarget) {
25027 if (DCI.isBeforeLegalizeOps())
25030 if (SDValue Zext = VectorZextCombine(N, DAG, DCI, Subtarget))
25033 if (SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget))
25036 if (SDValue FPLogic = convertIntLogicToFPLogic(N, DAG, Subtarget))
25039 EVT VT = N->getValueType(0);
25040 SDValue N0 = N->getOperand(0);
25041 SDValue N1 = N->getOperand(1);
25044 // Create BEXTR instructions
25045 // BEXTR is ((X >> imm) & (2**size-1))
25046 if (VT == MVT::i32 || VT == MVT::i64) {
25047 // Check for BEXTR.
25048 if ((Subtarget->hasBMI() || Subtarget->hasTBM()) &&
25049 (N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::SRL)) {
25050 ConstantSDNode *MaskNode = dyn_cast<ConstantSDNode>(N1);
25051 ConstantSDNode *ShiftNode = dyn_cast<ConstantSDNode>(N0.getOperand(1));
25052 if (MaskNode && ShiftNode) {
25053 uint64_t Mask = MaskNode->getZExtValue();
25054 uint64_t Shift = ShiftNode->getZExtValue();
25055 if (isMask_64(Mask)) {
25056 uint64_t MaskSize = countPopulation(Mask);
25057 if (Shift + MaskSize <= VT.getSizeInBits())
25058 return DAG.getNode(X86ISD::BEXTR, DL, VT, N0.getOperand(0),
25059 DAG.getConstant(Shift | (MaskSize << 8), DL,
25068 // Want to form ANDNP nodes:
25069 // 1) In the hopes of then easily combining them with OR and AND nodes
25070 // to form PBLEND/PSIGN.
25071 // 2) To match ANDN packed intrinsics
25072 if (VT != MVT::v2i64 && VT != MVT::v4i64)
25075 // Check LHS for vnot
25076 if (N0.getOpcode() == ISD::XOR &&
25077 //ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode()))
25078 CanFoldXORWithAllOnes(N0.getOperand(1).getNode()))
25079 return DAG.getNode(X86ISD::ANDNP, DL, VT, N0.getOperand(0), N1);
25081 // Check RHS for vnot
25082 if (N1.getOpcode() == ISD::XOR &&
25083 //ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode()))
25084 CanFoldXORWithAllOnes(N1.getOperand(1).getNode()))
25085 return DAG.getNode(X86ISD::ANDNP, DL, VT, N1.getOperand(0), N0);
25090 static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
25091 TargetLowering::DAGCombinerInfo &DCI,
25092 const X86Subtarget *Subtarget) {
25093 if (DCI.isBeforeLegalizeOps())
25096 if (SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget))
25099 if (SDValue FPLogic = convertIntLogicToFPLogic(N, DAG, Subtarget))
25102 SDValue N0 = N->getOperand(0);
25103 SDValue N1 = N->getOperand(1);
25104 EVT VT = N->getValueType(0);
25106 // look for psign/blend
25107 if (VT == MVT::v2i64 || VT == MVT::v4i64) {
25108 if (!Subtarget->hasSSSE3() ||
25109 (VT == MVT::v4i64 && !Subtarget->hasInt256()))
25112 // Canonicalize pandn to RHS
25113 if (N0.getOpcode() == X86ISD::ANDNP)
25115 // or (and (m, y), (pandn m, x))
25116 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::ANDNP) {
25117 SDValue Mask = N1.getOperand(0);
25118 SDValue X = N1.getOperand(1);
25120 if (N0.getOperand(0) == Mask)
25121 Y = N0.getOperand(1);
25122 if (N0.getOperand(1) == Mask)
25123 Y = N0.getOperand(0);
25125 // Check to see if the mask appeared in both the AND and ANDNP and
25129 // Validate that X, Y, and Mask are BIT_CONVERTS, and see through them.
25130 // Look through mask bitcast.
25131 if (Mask.getOpcode() == ISD::BITCAST)
25132 Mask = Mask.getOperand(0);
25133 if (X.getOpcode() == ISD::BITCAST)
25134 X = X.getOperand(0);
25135 if (Y.getOpcode() == ISD::BITCAST)
25136 Y = Y.getOperand(0);
25138 EVT MaskVT = Mask.getValueType();
25140 // Validate that the Mask operand is a vector sra node.
25141 // FIXME: what to do for bytes, since there is a psignb/pblendvb, but
25142 // there is no psrai.b
25143 unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits();
25144 unsigned SraAmt = ~0;
25145 if (Mask.getOpcode() == ISD::SRA) {
25146 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Mask.getOperand(1)))
25147 if (auto *AmtConst = AmtBV->getConstantSplatNode())
25148 SraAmt = AmtConst->getZExtValue();
25149 } else if (Mask.getOpcode() == X86ISD::VSRAI) {
25150 SDValue SraC = Mask.getOperand(1);
25151 SraAmt = cast<ConstantSDNode>(SraC)->getZExtValue();
25153 if ((SraAmt + 1) != EltBits)
25158 // Now we know we at least have a plendvb with the mask val. See if
25159 // we can form a psignb/w/d.
25160 // psign = x.type == y.type == mask.type && y = sub(0, x);
25161 if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X &&
25162 ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) &&
25163 X.getValueType() == MaskVT && Y.getValueType() == MaskVT) {
25164 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
25165 "Unsupported VT for PSIGN");
25166 Mask = DAG.getNode(X86ISD::PSIGN, DL, MaskVT, X, Mask.getOperand(0));
25167 return DAG.getBitcast(VT, Mask);
25169 // PBLENDVB only available on SSE 4.1
25170 if (!Subtarget->hasSSE41())
25173 MVT BlendVT = (VT == MVT::v4i64) ? MVT::v32i8 : MVT::v16i8;
25175 X = DAG.getBitcast(BlendVT, X);
25176 Y = DAG.getBitcast(BlendVT, Y);
25177 Mask = DAG.getBitcast(BlendVT, Mask);
25178 Mask = DAG.getNode(ISD::VSELECT, DL, BlendVT, Mask, Y, X);
25179 return DAG.getBitcast(VT, Mask);
25183 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64)
25186 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
25187 bool OptForSize = DAG.getMachineFunction().getFunction()->optForSize();
25189 // SHLD/SHRD instructions have lower register pressure, but on some
25190 // platforms they have higher latency than the equivalent
25191 // series of shifts/or that would otherwise be generated.
25192 // Don't fold (or (x << c) | (y >> (64 - c))) if SHLD/SHRD instructions
25193 // have higher latencies and we are not optimizing for size.
25194 if (!OptForSize && Subtarget->isSHLDSlow())
25197 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
25199 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
25201 if (!N0.hasOneUse() || !N1.hasOneUse())
25204 SDValue ShAmt0 = N0.getOperand(1);
25205 if (ShAmt0.getValueType() != MVT::i8)
25207 SDValue ShAmt1 = N1.getOperand(1);
25208 if (ShAmt1.getValueType() != MVT::i8)
25210 if (ShAmt0.getOpcode() == ISD::TRUNCATE)
25211 ShAmt0 = ShAmt0.getOperand(0);
25212 if (ShAmt1.getOpcode() == ISD::TRUNCATE)
25213 ShAmt1 = ShAmt1.getOperand(0);
25216 unsigned Opc = X86ISD::SHLD;
25217 SDValue Op0 = N0.getOperand(0);
25218 SDValue Op1 = N1.getOperand(0);
25219 if (ShAmt0.getOpcode() == ISD::SUB) {
25220 Opc = X86ISD::SHRD;
25221 std::swap(Op0, Op1);
25222 std::swap(ShAmt0, ShAmt1);
25225 unsigned Bits = VT.getSizeInBits();
25226 if (ShAmt1.getOpcode() == ISD::SUB) {
25227 SDValue Sum = ShAmt1.getOperand(0);
25228 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) {
25229 SDValue ShAmt1Op1 = ShAmt1.getOperand(1);
25230 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE)
25231 ShAmt1Op1 = ShAmt1Op1.getOperand(0);
25232 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0)
25233 return DAG.getNode(Opc, DL, VT,
25235 DAG.getNode(ISD::TRUNCATE, DL,
25238 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) {
25239 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0);
25241 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits)
25242 return DAG.getNode(Opc, DL, VT,
25243 N0.getOperand(0), N1.getOperand(0),
25244 DAG.getNode(ISD::TRUNCATE, DL,
25251 // Generate NEG and CMOV for integer abs.
25252 static SDValue performIntegerAbsCombine(SDNode *N, SelectionDAG &DAG) {
25253 EVT VT = N->getValueType(0);
25255 // Since X86 does not have CMOV for 8-bit integer, we don't convert
25256 // 8-bit integer abs to NEG and CMOV.
25257 if (VT.isInteger() && VT.getSizeInBits() == 8)
25260 SDValue N0 = N->getOperand(0);
25261 SDValue N1 = N->getOperand(1);
25264 // Check pattern of XOR(ADD(X,Y), Y) where Y is SRA(X, size(X)-1)
25265 // and change it to SUB and CMOV.
25266 if (VT.isInteger() && N->getOpcode() == ISD::XOR &&
25267 N0.getOpcode() == ISD::ADD &&
25268 N0.getOperand(1) == N1 &&
25269 N1.getOpcode() == ISD::SRA &&
25270 N1.getOperand(0) == N0.getOperand(0))
25271 if (ConstantSDNode *Y1C = dyn_cast<ConstantSDNode>(N1.getOperand(1)))
25272 if (Y1C->getAPIntValue() == VT.getSizeInBits()-1) {
25273 // Generate SUB & CMOV.
25274 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, DAG.getVTList(VT, MVT::i32),
25275 DAG.getConstant(0, DL, VT), N0.getOperand(0));
25277 SDValue Ops[] = { N0.getOperand(0), Neg,
25278 DAG.getConstant(X86::COND_GE, DL, MVT::i8),
25279 SDValue(Neg.getNode(), 1) };
25280 return DAG.getNode(X86ISD::CMOV, DL, DAG.getVTList(VT, MVT::Glue), Ops);
25285 // Try to turn tests against the signbit in the form of:
25286 // XOR(TRUNCATE(SRL(X, size(X)-1)), 1)
25289 static SDValue foldXorTruncShiftIntoCmp(SDNode *N, SelectionDAG &DAG) {
25290 // This is only worth doing if the output type is i8.
25291 if (N->getValueType(0) != MVT::i8)
25294 SDValue N0 = N->getOperand(0);
25295 SDValue N1 = N->getOperand(1);
25297 // We should be performing an xor against a truncated shift.
25298 if (N0.getOpcode() != ISD::TRUNCATE || !N0.hasOneUse())
25301 // Make sure we are performing an xor against one.
25302 if (!isa<ConstantSDNode>(N1) || !cast<ConstantSDNode>(N1)->isOne())
25305 // SetCC on x86 zero extends so only act on this if it's a logical shift.
25306 SDValue Shift = N0.getOperand(0);
25307 if (Shift.getOpcode() != ISD::SRL || !Shift.hasOneUse())
25310 // Make sure we are truncating from one of i16, i32 or i64.
25311 EVT ShiftTy = Shift.getValueType();
25312 if (ShiftTy != MVT::i16 && ShiftTy != MVT::i32 && ShiftTy != MVT::i64)
25315 // Make sure the shift amount extracts the sign bit.
25316 if (!isa<ConstantSDNode>(Shift.getOperand(1)) ||
25317 Shift.getConstantOperandVal(1) != ShiftTy.getSizeInBits() - 1)
25320 // Create a greater-than comparison against -1.
25321 // N.B. Using SETGE against 0 works but we want a canonical looking
25322 // comparison, using SETGT matches up with what TranslateX86CC.
25324 SDValue ShiftOp = Shift.getOperand(0);
25325 EVT ShiftOpTy = ShiftOp.getValueType();
25326 SDValue Cond = DAG.getSetCC(DL, MVT::i8, ShiftOp,
25327 DAG.getConstant(-1, DL, ShiftOpTy), ISD::SETGT);
25331 static SDValue PerformXorCombine(SDNode *N, SelectionDAG &DAG,
25332 TargetLowering::DAGCombinerInfo &DCI,
25333 const X86Subtarget *Subtarget) {
25334 if (DCI.isBeforeLegalizeOps())
25337 if (SDValue RV = foldXorTruncShiftIntoCmp(N, DAG))
25340 if (Subtarget->hasCMov())
25341 if (SDValue RV = performIntegerAbsCombine(N, DAG))
25344 if (SDValue FPLogic = convertIntLogicToFPLogic(N, DAG, Subtarget))
25350 /// PerformLOADCombine - Do target-specific dag combines on LOAD nodes.
25351 static SDValue PerformLOADCombine(SDNode *N, SelectionDAG &DAG,
25352 TargetLowering::DAGCombinerInfo &DCI,
25353 const X86Subtarget *Subtarget) {
25354 LoadSDNode *Ld = cast<LoadSDNode>(N);
25355 EVT RegVT = Ld->getValueType(0);
25356 EVT MemVT = Ld->getMemoryVT();
25358 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
25360 // For chips with slow 32-byte unaligned loads, break the 32-byte operation
25361 // into two 16-byte operations.
25362 ISD::LoadExtType Ext = Ld->getExtensionType();
25364 unsigned AddressSpace = Ld->getAddressSpace();
25365 unsigned Alignment = Ld->getAlignment();
25366 if (RegVT.is256BitVector() && !DCI.isBeforeLegalizeOps() &&
25367 Ext == ISD::NON_EXTLOAD &&
25368 TLI.allowsMemoryAccess(*DAG.getContext(), DAG.getDataLayout(), RegVT,
25369 AddressSpace, Alignment, &Fast) && !Fast) {
25370 unsigned NumElems = RegVT.getVectorNumElements();
25374 SDValue Ptr = Ld->getBasePtr();
25375 SDValue Increment =
25376 DAG.getConstant(16, dl, TLI.getPointerTy(DAG.getDataLayout()));
25378 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
25380 SDValue Load1 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
25381 Ld->getPointerInfo(), Ld->isVolatile(),
25382 Ld->isNonTemporal(), Ld->isInvariant(),
25384 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
25385 SDValue Load2 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
25386 Ld->getPointerInfo(), Ld->isVolatile(),
25387 Ld->isNonTemporal(), Ld->isInvariant(),
25388 std::min(16U, Alignment));
25389 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
25391 Load2.getValue(1));
25393 SDValue NewVec = DAG.getUNDEF(RegVT);
25394 NewVec = Insert128BitVector(NewVec, Load1, 0, DAG, dl);
25395 NewVec = Insert128BitVector(NewVec, Load2, NumElems/2, DAG, dl);
25396 return DCI.CombineTo(N, NewVec, TF, true);
25402 /// PerformMLOADCombine - Resolve extending loads
25403 static SDValue PerformMLOADCombine(SDNode *N, SelectionDAG &DAG,
25404 TargetLowering::DAGCombinerInfo &DCI,
25405 const X86Subtarget *Subtarget) {
25406 MaskedLoadSDNode *Mld = cast<MaskedLoadSDNode>(N);
25407 if (Mld->getExtensionType() != ISD::SEXTLOAD)
25410 EVT VT = Mld->getValueType(0);
25411 unsigned NumElems = VT.getVectorNumElements();
25412 EVT LdVT = Mld->getMemoryVT();
25415 assert(LdVT != VT && "Cannot extend to the same type");
25416 unsigned ToSz = VT.getVectorElementType().getSizeInBits();
25417 unsigned FromSz = LdVT.getVectorElementType().getSizeInBits();
25418 // From, To sizes and ElemCount must be pow of two
25419 assert (isPowerOf2_32(NumElems * FromSz * ToSz) &&
25420 "Unexpected size for extending masked load");
25422 unsigned SizeRatio = ToSz / FromSz;
25423 assert(SizeRatio * NumElems * FromSz == VT.getSizeInBits());
25425 // Create a type on which we perform the shuffle
25426 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
25427 LdVT.getScalarType(), NumElems*SizeRatio);
25428 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
25430 // Convert Src0 value
25431 SDValue WideSrc0 = DAG.getBitcast(WideVecVT, Mld->getSrc0());
25432 if (Mld->getSrc0().getOpcode() != ISD::UNDEF) {
25433 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
25434 for (unsigned i = 0; i != NumElems; ++i)
25435 ShuffleVec[i] = i * SizeRatio;
25437 // Can't shuffle using an illegal type.
25438 assert(DAG.getTargetLoweringInfo().isTypeLegal(WideVecVT) &&
25439 "WideVecVT should be legal");
25440 WideSrc0 = DAG.getVectorShuffle(WideVecVT, dl, WideSrc0,
25441 DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
25443 // Prepare the new mask
25445 SDValue Mask = Mld->getMask();
25446 if (Mask.getValueType() == VT) {
25447 // Mask and original value have the same type
25448 NewMask = DAG.getBitcast(WideVecVT, Mask);
25449 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
25450 for (unsigned i = 0; i != NumElems; ++i)
25451 ShuffleVec[i] = i * SizeRatio;
25452 for (unsigned i = NumElems; i != NumElems*SizeRatio; ++i)
25453 ShuffleVec[i] = NumElems*SizeRatio;
25454 NewMask = DAG.getVectorShuffle(WideVecVT, dl, NewMask,
25455 DAG.getConstant(0, dl, WideVecVT),
25459 assert(Mask.getValueType().getVectorElementType() == MVT::i1);
25460 unsigned WidenNumElts = NumElems*SizeRatio;
25461 unsigned MaskNumElts = VT.getVectorNumElements();
25462 EVT NewMaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
25465 unsigned NumConcat = WidenNumElts / MaskNumElts;
25466 SmallVector<SDValue, 16> Ops(NumConcat);
25467 SDValue ZeroVal = DAG.getConstant(0, dl, Mask.getValueType());
25469 for (unsigned i = 1; i != NumConcat; ++i)
25472 NewMask = DAG.getNode(ISD::CONCAT_VECTORS, dl, NewMaskVT, Ops);
25475 SDValue WideLd = DAG.getMaskedLoad(WideVecVT, dl, Mld->getChain(),
25476 Mld->getBasePtr(), NewMask, WideSrc0,
25477 Mld->getMemoryVT(), Mld->getMemOperand(),
25479 SDValue NewVec = DAG.getNode(X86ISD::VSEXT, dl, VT, WideLd);
25480 return DCI.CombineTo(N, NewVec, WideLd.getValue(1), true);
25482 /// PerformMSTORECombine - Resolve truncating stores
25483 static SDValue PerformMSTORECombine(SDNode *N, SelectionDAG &DAG,
25484 const X86Subtarget *Subtarget) {
25485 MaskedStoreSDNode *Mst = cast<MaskedStoreSDNode>(N);
25486 if (!Mst->isTruncatingStore())
25489 EVT VT = Mst->getValue().getValueType();
25490 unsigned NumElems = VT.getVectorNumElements();
25491 EVT StVT = Mst->getMemoryVT();
25494 assert(StVT != VT && "Cannot truncate to the same type");
25495 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
25496 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
25498 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
25500 // The truncating store is legal in some cases. For example
25501 // vpmovqb, vpmovqw, vpmovqd, vpmovdb, vpmovdw
25502 // are designated for truncate store.
25503 // In this case we don't need any further transformations.
25504 if (TLI.isTruncStoreLegal(VT, StVT))
25507 // From, To sizes and ElemCount must be pow of two
25508 assert (isPowerOf2_32(NumElems * FromSz * ToSz) &&
25509 "Unexpected size for truncating masked store");
25510 // We are going to use the original vector elt for storing.
25511 // Accumulated smaller vector elements must be a multiple of the store size.
25512 assert (((NumElems * FromSz) % ToSz) == 0 &&
25513 "Unexpected ratio for truncating masked store");
25515 unsigned SizeRatio = FromSz / ToSz;
25516 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
25518 // Create a type on which we perform the shuffle
25519 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
25520 StVT.getScalarType(), NumElems*SizeRatio);
25522 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
25524 SDValue WideVec = DAG.getBitcast(WideVecVT, Mst->getValue());
25525 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
25526 for (unsigned i = 0; i != NumElems; ++i)
25527 ShuffleVec[i] = i * SizeRatio;
25529 // Can't shuffle using an illegal type.
25530 assert(DAG.getTargetLoweringInfo().isTypeLegal(WideVecVT) &&
25531 "WideVecVT should be legal");
25533 SDValue TruncatedVal = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
25534 DAG.getUNDEF(WideVecVT),
25538 SDValue Mask = Mst->getMask();
25539 if (Mask.getValueType() == VT) {
25540 // Mask and original value have the same type
25541 NewMask = DAG.getBitcast(WideVecVT, Mask);
25542 for (unsigned i = 0; i != NumElems; ++i)
25543 ShuffleVec[i] = i * SizeRatio;
25544 for (unsigned i = NumElems; i != NumElems*SizeRatio; ++i)
25545 ShuffleVec[i] = NumElems*SizeRatio;
25546 NewMask = DAG.getVectorShuffle(WideVecVT, dl, NewMask,
25547 DAG.getConstant(0, dl, WideVecVT),
25551 assert(Mask.getValueType().getVectorElementType() == MVT::i1);
25552 unsigned WidenNumElts = NumElems*SizeRatio;
25553 unsigned MaskNumElts = VT.getVectorNumElements();
25554 EVT NewMaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
25557 unsigned NumConcat = WidenNumElts / MaskNumElts;
25558 SmallVector<SDValue, 16> Ops(NumConcat);
25559 SDValue ZeroVal = DAG.getConstant(0, dl, Mask.getValueType());
25561 for (unsigned i = 1; i != NumConcat; ++i)
25564 NewMask = DAG.getNode(ISD::CONCAT_VECTORS, dl, NewMaskVT, Ops);
25567 return DAG.getMaskedStore(Mst->getChain(), dl, TruncatedVal, Mst->getBasePtr(),
25568 NewMask, StVT, Mst->getMemOperand(), false);
25570 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
25571 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
25572 const X86Subtarget *Subtarget) {
25573 StoreSDNode *St = cast<StoreSDNode>(N);
25574 EVT VT = St->getValue().getValueType();
25575 EVT StVT = St->getMemoryVT();
25577 SDValue StoredVal = St->getOperand(1);
25578 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
25580 // If we are saving a concatenation of two XMM registers and 32-byte stores
25581 // are slow, such as on Sandy Bridge, perform two 16-byte stores.
25583 unsigned AddressSpace = St->getAddressSpace();
25584 unsigned Alignment = St->getAlignment();
25585 if (VT.is256BitVector() && StVT == VT &&
25586 TLI.allowsMemoryAccess(*DAG.getContext(), DAG.getDataLayout(), VT,
25587 AddressSpace, Alignment, &Fast) && !Fast) {
25588 unsigned NumElems = VT.getVectorNumElements();
25592 SDValue Value0 = Extract128BitVector(StoredVal, 0, DAG, dl);
25593 SDValue Value1 = Extract128BitVector(StoredVal, NumElems/2, DAG, dl);
25596 DAG.getConstant(16, dl, TLI.getPointerTy(DAG.getDataLayout()));
25597 SDValue Ptr0 = St->getBasePtr();
25598 SDValue Ptr1 = DAG.getNode(ISD::ADD, dl, Ptr0.getValueType(), Ptr0, Stride);
25600 SDValue Ch0 = DAG.getStore(St->getChain(), dl, Value0, Ptr0,
25601 St->getPointerInfo(), St->isVolatile(),
25602 St->isNonTemporal(), Alignment);
25603 SDValue Ch1 = DAG.getStore(St->getChain(), dl, Value1, Ptr1,
25604 St->getPointerInfo(), St->isVolatile(),
25605 St->isNonTemporal(),
25606 std::min(16U, Alignment));
25607 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ch0, Ch1);
25610 // Optimize trunc store (of multiple scalars) to shuffle and store.
25611 // First, pack all of the elements in one place. Next, store to memory
25612 // in fewer chunks.
25613 if (St->isTruncatingStore() && VT.isVector()) {
25614 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
25615 unsigned NumElems = VT.getVectorNumElements();
25616 assert(StVT != VT && "Cannot truncate to the same type");
25617 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
25618 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
25620 // The truncating store is legal in some cases. For example
25621 // vpmovqb, vpmovqw, vpmovqd, vpmovdb, vpmovdw
25622 // are designated for truncate store.
25623 // In this case we don't need any further transformations.
25624 if (TLI.isTruncStoreLegal(VT, StVT))
25627 // From, To sizes and ElemCount must be pow of two
25628 if (!isPowerOf2_32(NumElems * FromSz * ToSz)) return SDValue();
25629 // We are going to use the original vector elt for storing.
25630 // Accumulated smaller vector elements must be a multiple of the store size.
25631 if (0 != (NumElems * FromSz) % ToSz) return SDValue();
25633 unsigned SizeRatio = FromSz / ToSz;
25635 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
25637 // Create a type on which we perform the shuffle
25638 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
25639 StVT.getScalarType(), NumElems*SizeRatio);
25641 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
25643 SDValue WideVec = DAG.getBitcast(WideVecVT, St->getValue());
25644 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
25645 for (unsigned i = 0; i != NumElems; ++i)
25646 ShuffleVec[i] = i * SizeRatio;
25648 // Can't shuffle using an illegal type.
25649 if (!TLI.isTypeLegal(WideVecVT))
25652 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
25653 DAG.getUNDEF(WideVecVT),
25655 // At this point all of the data is stored at the bottom of the
25656 // register. We now need to save it to mem.
25658 // Find the largest store unit
25659 MVT StoreType = MVT::i8;
25660 for (MVT Tp : MVT::integer_valuetypes()) {
25661 if (TLI.isTypeLegal(Tp) && Tp.getSizeInBits() <= NumElems * ToSz)
25665 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
25666 if (TLI.isTypeLegal(MVT::f64) && StoreType.getSizeInBits() < 64 &&
25667 (64 <= NumElems * ToSz))
25668 StoreType = MVT::f64;
25670 // Bitcast the original vector into a vector of store-size units
25671 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(),
25672 StoreType, VT.getSizeInBits()/StoreType.getSizeInBits());
25673 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits());
25674 SDValue ShuffWide = DAG.getBitcast(StoreVecVT, Shuff);
25675 SmallVector<SDValue, 8> Chains;
25676 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits() / 8, dl,
25677 TLI.getPointerTy(DAG.getDataLayout()));
25678 SDValue Ptr = St->getBasePtr();
25680 // Perform one or more big stores into memory.
25681 for (unsigned i=0, e=(ToSz*NumElems)/StoreType.getSizeInBits(); i!=e; ++i) {
25682 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
25683 StoreType, ShuffWide,
25684 DAG.getIntPtrConstant(i, dl));
25685 SDValue Ch = DAG.getStore(St->getChain(), dl, SubVec, Ptr,
25686 St->getPointerInfo(), St->isVolatile(),
25687 St->isNonTemporal(), St->getAlignment());
25688 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
25689 Chains.push_back(Ch);
25692 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
25695 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
25696 // the FP state in cases where an emms may be missing.
25697 // A preferable solution to the general problem is to figure out the right
25698 // places to insert EMMS. This qualifies as a quick hack.
25700 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
25701 if (VT.getSizeInBits() != 64)
25704 const Function *F = DAG.getMachineFunction().getFunction();
25705 bool NoImplicitFloatOps = F->hasFnAttribute(Attribute::NoImplicitFloat);
25707 !Subtarget->useSoftFloat() && !NoImplicitFloatOps && Subtarget->hasSSE2();
25708 if ((VT.isVector() ||
25709 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
25710 isa<LoadSDNode>(St->getValue()) &&
25711 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
25712 St->getChain().hasOneUse() && !St->isVolatile()) {
25713 SDNode* LdVal = St->getValue().getNode();
25714 LoadSDNode *Ld = nullptr;
25715 int TokenFactorIndex = -1;
25716 SmallVector<SDValue, 8> Ops;
25717 SDNode* ChainVal = St->getChain().getNode();
25718 // Must be a store of a load. We currently handle two cases: the load
25719 // is a direct child, and it's under an intervening TokenFactor. It is
25720 // possible to dig deeper under nested TokenFactors.
25721 if (ChainVal == LdVal)
25722 Ld = cast<LoadSDNode>(St->getChain());
25723 else if (St->getValue().hasOneUse() &&
25724 ChainVal->getOpcode() == ISD::TokenFactor) {
25725 for (unsigned i = 0, e = ChainVal->getNumOperands(); i != e; ++i) {
25726 if (ChainVal->getOperand(i).getNode() == LdVal) {
25727 TokenFactorIndex = i;
25728 Ld = cast<LoadSDNode>(St->getValue());
25730 Ops.push_back(ChainVal->getOperand(i));
25734 if (!Ld || !ISD::isNormalLoad(Ld))
25737 // If this is not the MMX case, i.e. we are just turning i64 load/store
25738 // into f64 load/store, avoid the transformation if there are multiple
25739 // uses of the loaded value.
25740 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
25745 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
25746 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
25748 if (Subtarget->is64Bit() || F64IsLegal) {
25749 MVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
25750 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(),
25751 Ld->getPointerInfo(), Ld->isVolatile(),
25752 Ld->isNonTemporal(), Ld->isInvariant(),
25753 Ld->getAlignment());
25754 SDValue NewChain = NewLd.getValue(1);
25755 if (TokenFactorIndex != -1) {
25756 Ops.push_back(NewChain);
25757 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
25759 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
25760 St->getPointerInfo(),
25761 St->isVolatile(), St->isNonTemporal(),
25762 St->getAlignment());
25765 // Otherwise, lower to two pairs of 32-bit loads / stores.
25766 SDValue LoAddr = Ld->getBasePtr();
25767 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
25768 DAG.getConstant(4, LdDL, MVT::i32));
25770 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
25771 Ld->getPointerInfo(),
25772 Ld->isVolatile(), Ld->isNonTemporal(),
25773 Ld->isInvariant(), Ld->getAlignment());
25774 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
25775 Ld->getPointerInfo().getWithOffset(4),
25776 Ld->isVolatile(), Ld->isNonTemporal(),
25778 MinAlign(Ld->getAlignment(), 4));
25780 SDValue NewChain = LoLd.getValue(1);
25781 if (TokenFactorIndex != -1) {
25782 Ops.push_back(LoLd);
25783 Ops.push_back(HiLd);
25784 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
25787 LoAddr = St->getBasePtr();
25788 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
25789 DAG.getConstant(4, StDL, MVT::i32));
25791 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
25792 St->getPointerInfo(),
25793 St->isVolatile(), St->isNonTemporal(),
25794 St->getAlignment());
25795 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
25796 St->getPointerInfo().getWithOffset(4),
25798 St->isNonTemporal(),
25799 MinAlign(St->getAlignment(), 4));
25800 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
25803 // This is similar to the above case, but here we handle a scalar 64-bit
25804 // integer store that is extracted from a vector on a 32-bit target.
25805 // If we have SSE2, then we can treat it like a floating-point double
25806 // to get past legalization. The execution dependencies fixup pass will
25807 // choose the optimal machine instruction for the store if this really is
25808 // an integer or v2f32 rather than an f64.
25809 if (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit() &&
25810 St->getOperand(1).getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
25811 SDValue OldExtract = St->getOperand(1);
25812 SDValue ExtOp0 = OldExtract.getOperand(0);
25813 unsigned VecSize = ExtOp0.getValueSizeInBits();
25814 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), MVT::f64, VecSize / 64);
25815 SDValue BitCast = DAG.getBitcast(VecVT, ExtOp0);
25816 SDValue NewExtract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
25817 BitCast, OldExtract.getOperand(1));
25818 return DAG.getStore(St->getChain(), dl, NewExtract, St->getBasePtr(),
25819 St->getPointerInfo(), St->isVolatile(),
25820 St->isNonTemporal(), St->getAlignment());
25826 /// Return 'true' if this vector operation is "horizontal"
25827 /// and return the operands for the horizontal operation in LHS and RHS. A
25828 /// horizontal operation performs the binary operation on successive elements
25829 /// of its first operand, then on successive elements of its second operand,
25830 /// returning the resulting values in a vector. For example, if
25831 /// A = < float a0, float a1, float a2, float a3 >
25833 /// B = < float b0, float b1, float b2, float b3 >
25834 /// then the result of doing a horizontal operation on A and B is
25835 /// A horizontal-op B = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >.
25836 /// In short, LHS and RHS are inspected to see if LHS op RHS is of the form
25837 /// A horizontal-op B, for some already available A and B, and if so then LHS is
25838 /// set to A, RHS to B, and the routine returns 'true'.
25839 /// Note that the binary operation should have the property that if one of the
25840 /// operands is UNDEF then the result is UNDEF.
25841 static bool isHorizontalBinOp(SDValue &LHS, SDValue &RHS, bool IsCommutative) {
25842 // Look for the following pattern: if
25843 // A = < float a0, float a1, float a2, float a3 >
25844 // B = < float b0, float b1, float b2, float b3 >
25846 // LHS = VECTOR_SHUFFLE A, B, <0, 2, 4, 6>
25847 // RHS = VECTOR_SHUFFLE A, B, <1, 3, 5, 7>
25848 // then LHS op RHS = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >
25849 // which is A horizontal-op B.
25851 // At least one of the operands should be a vector shuffle.
25852 if (LHS.getOpcode() != ISD::VECTOR_SHUFFLE &&
25853 RHS.getOpcode() != ISD::VECTOR_SHUFFLE)
25856 MVT VT = LHS.getSimpleValueType();
25858 assert((VT.is128BitVector() || VT.is256BitVector()) &&
25859 "Unsupported vector type for horizontal add/sub");
25861 // Handle 128 and 256-bit vector lengths. AVX defines horizontal add/sub to
25862 // operate independently on 128-bit lanes.
25863 unsigned NumElts = VT.getVectorNumElements();
25864 unsigned NumLanes = VT.getSizeInBits()/128;
25865 unsigned NumLaneElts = NumElts / NumLanes;
25866 assert((NumLaneElts % 2 == 0) &&
25867 "Vector type should have an even number of elements in each lane");
25868 unsigned HalfLaneElts = NumLaneElts/2;
25870 // View LHS in the form
25871 // LHS = VECTOR_SHUFFLE A, B, LMask
25872 // If LHS is not a shuffle then pretend it is the shuffle
25873 // LHS = VECTOR_SHUFFLE LHS, undef, <0, 1, ..., N-1>
25874 // NOTE: in what follows a default initialized SDValue represents an UNDEF of
25877 SmallVector<int, 16> LMask(NumElts);
25878 if (LHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
25879 if (LHS.getOperand(0).getOpcode() != ISD::UNDEF)
25880 A = LHS.getOperand(0);
25881 if (LHS.getOperand(1).getOpcode() != ISD::UNDEF)
25882 B = LHS.getOperand(1);
25883 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(LHS.getNode())->getMask();
25884 std::copy(Mask.begin(), Mask.end(), LMask.begin());
25886 if (LHS.getOpcode() != ISD::UNDEF)
25888 for (unsigned i = 0; i != NumElts; ++i)
25892 // Likewise, view RHS in the form
25893 // RHS = VECTOR_SHUFFLE C, D, RMask
25895 SmallVector<int, 16> RMask(NumElts);
25896 if (RHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
25897 if (RHS.getOperand(0).getOpcode() != ISD::UNDEF)
25898 C = RHS.getOperand(0);
25899 if (RHS.getOperand(1).getOpcode() != ISD::UNDEF)
25900 D = RHS.getOperand(1);
25901 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(RHS.getNode())->getMask();
25902 std::copy(Mask.begin(), Mask.end(), RMask.begin());
25904 if (RHS.getOpcode() != ISD::UNDEF)
25906 for (unsigned i = 0; i != NumElts; ++i)
25910 // Check that the shuffles are both shuffling the same vectors.
25911 if (!(A == C && B == D) && !(A == D && B == C))
25914 // If everything is UNDEF then bail out: it would be better to fold to UNDEF.
25915 if (!A.getNode() && !B.getNode())
25918 // If A and B occur in reverse order in RHS, then "swap" them (which means
25919 // rewriting the mask).
25921 ShuffleVectorSDNode::commuteMask(RMask);
25923 // At this point LHS and RHS are equivalent to
25924 // LHS = VECTOR_SHUFFLE A, B, LMask
25925 // RHS = VECTOR_SHUFFLE A, B, RMask
25926 // Check that the masks correspond to performing a horizontal operation.
25927 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
25928 for (unsigned i = 0; i != NumLaneElts; ++i) {
25929 int LIdx = LMask[i+l], RIdx = RMask[i+l];
25931 // Ignore any UNDEF components.
25932 if (LIdx < 0 || RIdx < 0 ||
25933 (!A.getNode() && (LIdx < (int)NumElts || RIdx < (int)NumElts)) ||
25934 (!B.getNode() && (LIdx >= (int)NumElts || RIdx >= (int)NumElts)))
25937 // Check that successive elements are being operated on. If not, this is
25938 // not a horizontal operation.
25939 unsigned Src = (i/HalfLaneElts); // each lane is split between srcs
25940 int Index = 2*(i%HalfLaneElts) + NumElts*Src + l;
25941 if (!(LIdx == Index && RIdx == Index + 1) &&
25942 !(IsCommutative && LIdx == Index + 1 && RIdx == Index))
25947 LHS = A.getNode() ? A : B; // If A is 'UNDEF', use B for it.
25948 RHS = B.getNode() ? B : A; // If B is 'UNDEF', use A for it.
25952 /// Do target-specific dag combines on floating point adds.
25953 static SDValue PerformFADDCombine(SDNode *N, SelectionDAG &DAG,
25954 const X86Subtarget *Subtarget) {
25955 EVT VT = N->getValueType(0);
25956 SDValue LHS = N->getOperand(0);
25957 SDValue RHS = N->getOperand(1);
25959 // Try to synthesize horizontal adds from adds of shuffles.
25960 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
25961 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
25962 isHorizontalBinOp(LHS, RHS, true))
25963 return DAG.getNode(X86ISD::FHADD, SDLoc(N), VT, LHS, RHS);
25967 /// Do target-specific dag combines on floating point subs.
25968 static SDValue PerformFSUBCombine(SDNode *N, SelectionDAG &DAG,
25969 const X86Subtarget *Subtarget) {
25970 EVT VT = N->getValueType(0);
25971 SDValue LHS = N->getOperand(0);
25972 SDValue RHS = N->getOperand(1);
25974 // Try to synthesize horizontal subs from subs of shuffles.
25975 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
25976 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
25977 isHorizontalBinOp(LHS, RHS, false))
25978 return DAG.getNode(X86ISD::FHSUB, SDLoc(N), VT, LHS, RHS);
25982 /// Do target-specific dag combines on X86ISD::FOR and X86ISD::FXOR nodes.
25983 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG,
25984 const X86Subtarget *Subtarget) {
25985 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
25987 // F[X]OR(0.0, x) -> x
25988 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
25989 if (C->getValueAPF().isPosZero())
25990 return N->getOperand(1);
25992 // F[X]OR(x, 0.0) -> x
25993 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
25994 if (C->getValueAPF().isPosZero())
25995 return N->getOperand(0);
25997 EVT VT = N->getValueType(0);
25998 if (VT.is512BitVector() && !Subtarget->hasDQI()) {
26000 MVT IntScalar = MVT::getIntegerVT(VT.getScalarSizeInBits());
26001 MVT IntVT = MVT::getVectorVT(IntScalar, VT.getVectorNumElements());
26003 SDValue Op0 = DAG.getNode(ISD::BITCAST, dl, IntVT, N->getOperand(0));
26004 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, IntVT, N->getOperand(1));
26005 unsigned IntOpcode = (N->getOpcode() == X86ISD::FOR) ? ISD::OR : ISD::XOR;
26006 SDValue IntOp = DAG.getNode(IntOpcode, dl, IntVT, Op0, Op1);
26007 return DAG.getNode(ISD::BITCAST, dl, VT, IntOp);
26012 /// Do target-specific dag combines on X86ISD::FMIN and X86ISD::FMAX nodes.
26013 static SDValue PerformFMinFMaxCombine(SDNode *N, SelectionDAG &DAG) {
26014 assert(N->getOpcode() == X86ISD::FMIN || N->getOpcode() == X86ISD::FMAX);
26016 // Only perform optimizations if UnsafeMath is used.
26017 if (!DAG.getTarget().Options.UnsafeFPMath)
26020 // If we run in unsafe-math mode, then convert the FMAX and FMIN nodes
26021 // into FMINC and FMAXC, which are Commutative operations.
26022 unsigned NewOp = 0;
26023 switch (N->getOpcode()) {
26024 default: llvm_unreachable("unknown opcode");
26025 case X86ISD::FMIN: NewOp = X86ISD::FMINC; break;
26026 case X86ISD::FMAX: NewOp = X86ISD::FMAXC; break;
26029 return DAG.getNode(NewOp, SDLoc(N), N->getValueType(0),
26030 N->getOperand(0), N->getOperand(1));
26033 /// Do target-specific dag combines on X86ISD::FAND nodes.
26034 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
26035 // FAND(0.0, x) -> 0.0
26036 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
26037 if (C->getValueAPF().isPosZero())
26038 return N->getOperand(0);
26040 // FAND(x, 0.0) -> 0.0
26041 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
26042 if (C->getValueAPF().isPosZero())
26043 return N->getOperand(1);
26048 /// Do target-specific dag combines on X86ISD::FANDN nodes
26049 static SDValue PerformFANDNCombine(SDNode *N, SelectionDAG &DAG) {
26050 // FANDN(0.0, x) -> x
26051 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
26052 if (C->getValueAPF().isPosZero())
26053 return N->getOperand(1);
26055 // FANDN(x, 0.0) -> 0.0
26056 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
26057 if (C->getValueAPF().isPosZero())
26058 return N->getOperand(1);
26063 static SDValue PerformBTCombine(SDNode *N,
26065 TargetLowering::DAGCombinerInfo &DCI) {
26066 // BT ignores high bits in the bit index operand.
26067 SDValue Op1 = N->getOperand(1);
26068 if (Op1.hasOneUse()) {
26069 unsigned BitWidth = Op1.getValueSizeInBits();
26070 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
26071 APInt KnownZero, KnownOne;
26072 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
26073 !DCI.isBeforeLegalizeOps());
26074 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
26075 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
26076 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
26077 DCI.CommitTargetLoweringOpt(TLO);
26082 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
26083 SDValue Op = N->getOperand(0);
26084 if (Op.getOpcode() == ISD::BITCAST)
26085 Op = Op.getOperand(0);
26086 EVT VT = N->getValueType(0), OpVT = Op.getValueType();
26087 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
26088 VT.getVectorElementType().getSizeInBits() ==
26089 OpVT.getVectorElementType().getSizeInBits()) {
26090 return DAG.getNode(ISD::BITCAST, SDLoc(N), VT, Op);
26095 static SDValue PerformSIGN_EXTEND_INREGCombine(SDNode *N, SelectionDAG &DAG,
26096 const X86Subtarget *Subtarget) {
26097 EVT VT = N->getValueType(0);
26098 if (!VT.isVector())
26101 SDValue N0 = N->getOperand(0);
26102 SDValue N1 = N->getOperand(1);
26103 EVT ExtraVT = cast<VTSDNode>(N1)->getVT();
26106 // The SIGN_EXTEND_INREG to v4i64 is expensive operation on the
26107 // both SSE and AVX2 since there is no sign-extended shift right
26108 // operation on a vector with 64-bit elements.
26109 //(sext_in_reg (v4i64 anyext (v4i32 x )), ExtraVT) ->
26110 // (v4i64 sext (v4i32 sext_in_reg (v4i32 x , ExtraVT)))
26111 if (VT == MVT::v4i64 && (N0.getOpcode() == ISD::ANY_EXTEND ||
26112 N0.getOpcode() == ISD::SIGN_EXTEND)) {
26113 SDValue N00 = N0.getOperand(0);
26115 // EXTLOAD has a better solution on AVX2,
26116 // it may be replaced with X86ISD::VSEXT node.
26117 if (N00.getOpcode() == ISD::LOAD && Subtarget->hasInt256())
26118 if (!ISD::isNormalLoad(N00.getNode()))
26121 if (N00.getValueType() == MVT::v4i32 && ExtraVT.getSizeInBits() < 128) {
26122 SDValue Tmp = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v4i32,
26124 return DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i64, Tmp);
26130 /// sext(add_nsw(x, C)) --> add(sext(x), C_sext)
26131 /// Promoting a sign extension ahead of an 'add nsw' exposes opportunities
26132 /// to combine math ops, use an LEA, or use a complex addressing mode. This can
26133 /// eliminate extend, add, and shift instructions.
26134 static SDValue promoteSextBeforeAddNSW(SDNode *Sext, SelectionDAG &DAG,
26135 const X86Subtarget *Subtarget) {
26136 // TODO: This should be valid for other integer types.
26137 EVT VT = Sext->getValueType(0);
26138 if (VT != MVT::i64)
26141 // We need an 'add nsw' feeding into the 'sext'.
26142 SDValue Add = Sext->getOperand(0);
26143 if (Add.getOpcode() != ISD::ADD || !Add->getFlags()->hasNoSignedWrap())
26146 // Having a constant operand to the 'add' ensures that we are not increasing
26147 // the instruction count because the constant is extended for free below.
26148 // A constant operand can also become the displacement field of an LEA.
26149 auto *AddOp1 = dyn_cast<ConstantSDNode>(Add.getOperand(1));
26153 // Don't make the 'add' bigger if there's no hope of combining it with some
26154 // other 'add' or 'shl' instruction.
26155 // TODO: It may be profitable to generate simpler LEA instructions in place
26156 // of single 'add' instructions, but the cost model for selecting an LEA
26157 // currently has a high threshold.
26158 bool HasLEAPotential = false;
26159 for (auto *User : Sext->uses()) {
26160 if (User->getOpcode() == ISD::ADD || User->getOpcode() == ISD::SHL) {
26161 HasLEAPotential = true;
26165 if (!HasLEAPotential)
26168 // Everything looks good, so pull the 'sext' ahead of the 'add'.
26169 int64_t AddConstant = AddOp1->getSExtValue();
26170 SDValue AddOp0 = Add.getOperand(0);
26171 SDValue NewSext = DAG.getNode(ISD::SIGN_EXTEND, SDLoc(Sext), VT, AddOp0);
26172 SDValue NewConstant = DAG.getConstant(AddConstant, SDLoc(Add), VT);
26174 // The wider add is guaranteed to not wrap because both operands are
26177 Flags.setNoSignedWrap(true);
26178 return DAG.getNode(ISD::ADD, SDLoc(Add), VT, NewSext, NewConstant, &Flags);
26181 static SDValue PerformSExtCombine(SDNode *N, SelectionDAG &DAG,
26182 TargetLowering::DAGCombinerInfo &DCI,
26183 const X86Subtarget *Subtarget) {
26184 SDValue N0 = N->getOperand(0);
26185 EVT VT = N->getValueType(0);
26186 EVT SVT = VT.getScalarType();
26187 EVT InVT = N0.getValueType();
26188 EVT InSVT = InVT.getScalarType();
26191 // (i8,i32 sext (sdivrem (i8 x, i8 y)) ->
26192 // (i8,i32 (sdivrem_sext_hreg (i8 x, i8 y)
26193 // This exposes the sext to the sdivrem lowering, so that it directly extends
26194 // from AH (which we otherwise need to do contortions to access).
26195 if (N0.getOpcode() == ISD::SDIVREM && N0.getResNo() == 1 &&
26196 InVT == MVT::i8 && VT == MVT::i32) {
26197 SDVTList NodeTys = DAG.getVTList(MVT::i8, VT);
26198 SDValue R = DAG.getNode(X86ISD::SDIVREM8_SEXT_HREG, DL, NodeTys,
26199 N0.getOperand(0), N0.getOperand(1));
26200 DAG.ReplaceAllUsesOfValueWith(N0.getValue(0), R.getValue(0));
26201 return R.getValue(1);
26204 if (!DCI.isBeforeLegalizeOps()) {
26205 if (InVT == MVT::i1) {
26206 SDValue Zero = DAG.getConstant(0, DL, VT);
26208 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), DL, VT);
26209 return DAG.getNode(ISD::SELECT, DL, VT, N0, AllOnes, Zero);
26214 if (VT.isVector() && Subtarget->hasSSE2()) {
26215 auto ExtendVecSize = [&DAG](SDLoc DL, SDValue N, unsigned Size) {
26216 EVT InVT = N.getValueType();
26217 EVT OutVT = EVT::getVectorVT(*DAG.getContext(), InVT.getScalarType(),
26218 Size / InVT.getScalarSizeInBits());
26219 SmallVector<SDValue, 8> Opnds(Size / InVT.getSizeInBits(),
26220 DAG.getUNDEF(InVT));
26222 return DAG.getNode(ISD::CONCAT_VECTORS, DL, OutVT, Opnds);
26225 // If target-size is less than 128-bits, extend to a type that would extend
26226 // to 128 bits, extend that and extract the original target vector.
26227 if (VT.getSizeInBits() < 128 && !(128 % VT.getSizeInBits()) &&
26228 (SVT == MVT::i64 || SVT == MVT::i32 || SVT == MVT::i16) &&
26229 (InSVT == MVT::i32 || InSVT == MVT::i16 || InSVT == MVT::i8)) {
26230 unsigned Scale = 128 / VT.getSizeInBits();
26232 EVT::getVectorVT(*DAG.getContext(), SVT, 128 / SVT.getSizeInBits());
26233 SDValue Ex = ExtendVecSize(DL, N0, Scale * InVT.getSizeInBits());
26234 SDValue SExt = DAG.getNode(ISD::SIGN_EXTEND, DL, ExVT, Ex);
26235 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, SExt,
26236 DAG.getIntPtrConstant(0, DL));
26239 // If target-size is 128-bits, then convert to ISD::SIGN_EXTEND_VECTOR_INREG
26240 // which ensures lowering to X86ISD::VSEXT (pmovsx*).
26241 if (VT.getSizeInBits() == 128 &&
26242 (SVT == MVT::i64 || SVT == MVT::i32 || SVT == MVT::i16) &&
26243 (InSVT == MVT::i32 || InSVT == MVT::i16 || InSVT == MVT::i8)) {
26244 SDValue ExOp = ExtendVecSize(DL, N0, 128);
26245 return DAG.getSignExtendVectorInReg(ExOp, DL, VT);
26248 // On pre-AVX2 targets, split into 128-bit nodes of
26249 // ISD::SIGN_EXTEND_VECTOR_INREG.
26250 if (!Subtarget->hasInt256() && !(VT.getSizeInBits() % 128) &&
26251 (SVT == MVT::i64 || SVT == MVT::i32 || SVT == MVT::i16) &&
26252 (InSVT == MVT::i32 || InSVT == MVT::i16 || InSVT == MVT::i8)) {
26253 unsigned NumVecs = VT.getSizeInBits() / 128;
26254 unsigned NumSubElts = 128 / SVT.getSizeInBits();
26255 EVT SubVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumSubElts);
26256 EVT InSubVT = EVT::getVectorVT(*DAG.getContext(), InSVT, NumSubElts);
26258 SmallVector<SDValue, 8> Opnds;
26259 for (unsigned i = 0, Offset = 0; i != NumVecs;
26260 ++i, Offset += NumSubElts) {
26261 SDValue SrcVec = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InSubVT, N0,
26262 DAG.getIntPtrConstant(Offset, DL));
26263 SrcVec = ExtendVecSize(DL, SrcVec, 128);
26264 SrcVec = DAG.getSignExtendVectorInReg(SrcVec, DL, SubVT);
26265 Opnds.push_back(SrcVec);
26267 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Opnds);
26271 if (Subtarget->hasAVX() && VT.is256BitVector())
26272 if (SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget))
26275 if (SDValue NewAdd = promoteSextBeforeAddNSW(N, DAG, Subtarget))
26281 static SDValue PerformFMACombine(SDNode *N, SelectionDAG &DAG,
26282 const X86Subtarget* Subtarget) {
26284 EVT VT = N->getValueType(0);
26286 // Let legalize expand this if it isn't a legal type yet.
26287 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
26290 EVT ScalarVT = VT.getScalarType();
26291 if ((ScalarVT != MVT::f32 && ScalarVT != MVT::f64) ||
26292 (!Subtarget->hasFMA() && !Subtarget->hasFMA4() &&
26293 !Subtarget->hasAVX512()))
26296 SDValue A = N->getOperand(0);
26297 SDValue B = N->getOperand(1);
26298 SDValue C = N->getOperand(2);
26300 bool NegA = (A.getOpcode() == ISD::FNEG);
26301 bool NegB = (B.getOpcode() == ISD::FNEG);
26302 bool NegC = (C.getOpcode() == ISD::FNEG);
26304 // Negative multiplication when NegA xor NegB
26305 bool NegMul = (NegA != NegB);
26307 A = A.getOperand(0);
26309 B = B.getOperand(0);
26311 C = C.getOperand(0);
26315 Opcode = (!NegC) ? X86ISD::FMADD : X86ISD::FMSUB;
26317 Opcode = (!NegC) ? X86ISD::FNMADD : X86ISD::FNMSUB;
26319 return DAG.getNode(Opcode, dl, VT, A, B, C);
26322 static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG,
26323 TargetLowering::DAGCombinerInfo &DCI,
26324 const X86Subtarget *Subtarget) {
26325 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) ->
26326 // (and (i32 x86isd::setcc_carry), 1)
26327 // This eliminates the zext. This transformation is necessary because
26328 // ISD::SETCC is always legalized to i8.
26330 SDValue N0 = N->getOperand(0);
26331 EVT VT = N->getValueType(0);
26333 if (N0.getOpcode() == ISD::AND &&
26335 N0.getOperand(0).hasOneUse()) {
26336 SDValue N00 = N0.getOperand(0);
26337 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
26338 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
26339 if (!C || C->getZExtValue() != 1)
26341 return DAG.getNode(ISD::AND, dl, VT,
26342 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
26343 N00.getOperand(0), N00.getOperand(1)),
26344 DAG.getConstant(1, dl, VT));
26348 if (N0.getOpcode() == ISD::TRUNCATE &&
26350 N0.getOperand(0).hasOneUse()) {
26351 SDValue N00 = N0.getOperand(0);
26352 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
26353 return DAG.getNode(ISD::AND, dl, VT,
26354 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
26355 N00.getOperand(0), N00.getOperand(1)),
26356 DAG.getConstant(1, dl, VT));
26360 if (VT.is256BitVector())
26361 if (SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget))
26364 // (i8,i32 zext (udivrem (i8 x, i8 y)) ->
26365 // (i8,i32 (udivrem_zext_hreg (i8 x, i8 y)
26366 // This exposes the zext to the udivrem lowering, so that it directly extends
26367 // from AH (which we otherwise need to do contortions to access).
26368 if (N0.getOpcode() == ISD::UDIVREM &&
26369 N0.getResNo() == 1 && N0.getValueType() == MVT::i8 &&
26370 (VT == MVT::i32 || VT == MVT::i64)) {
26371 SDVTList NodeTys = DAG.getVTList(MVT::i8, VT);
26372 SDValue R = DAG.getNode(X86ISD::UDIVREM8_ZEXT_HREG, dl, NodeTys,
26373 N0.getOperand(0), N0.getOperand(1));
26374 DAG.ReplaceAllUsesOfValueWith(N0.getValue(0), R.getValue(0));
26375 return R.getValue(1);
26381 // Optimize x == -y --> x+y == 0
26382 // x != -y --> x+y != 0
26383 static SDValue PerformISDSETCCCombine(SDNode *N, SelectionDAG &DAG,
26384 const X86Subtarget* Subtarget) {
26385 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
26386 SDValue LHS = N->getOperand(0);
26387 SDValue RHS = N->getOperand(1);
26388 EVT VT = N->getValueType(0);
26391 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && LHS.getOpcode() == ISD::SUB)
26392 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(LHS.getOperand(0)))
26393 if (C->getAPIntValue() == 0 && LHS.hasOneUse()) {
26394 SDValue addV = DAG.getNode(ISD::ADD, DL, LHS.getValueType(), RHS,
26395 LHS.getOperand(1));
26396 return DAG.getSetCC(DL, N->getValueType(0), addV,
26397 DAG.getConstant(0, DL, addV.getValueType()), CC);
26399 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && RHS.getOpcode() == ISD::SUB)
26400 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS.getOperand(0)))
26401 if (C->getAPIntValue() == 0 && RHS.hasOneUse()) {
26402 SDValue addV = DAG.getNode(ISD::ADD, DL, RHS.getValueType(), LHS,
26403 RHS.getOperand(1));
26404 return DAG.getSetCC(DL, N->getValueType(0), addV,
26405 DAG.getConstant(0, DL, addV.getValueType()), CC);
26408 if (VT.getScalarType() == MVT::i1 &&
26409 (CC == ISD::SETNE || CC == ISD::SETEQ || ISD::isSignedIntSetCC(CC))) {
26411 (LHS.getOpcode() == ISD::SIGN_EXTEND) &&
26412 (LHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
26413 bool IsVZero1 = ISD::isBuildVectorAllZeros(RHS.getNode());
26415 if (!IsSEXT0 || !IsVZero1) {
26416 // Swap the operands and update the condition code.
26417 std::swap(LHS, RHS);
26418 CC = ISD::getSetCCSwappedOperands(CC);
26420 IsSEXT0 = (LHS.getOpcode() == ISD::SIGN_EXTEND) &&
26421 (LHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
26422 IsVZero1 = ISD::isBuildVectorAllZeros(RHS.getNode());
26425 if (IsSEXT0 && IsVZero1) {
26426 assert(VT == LHS.getOperand(0).getValueType() &&
26427 "Uexpected operand type");
26428 if (CC == ISD::SETGT)
26429 return DAG.getConstant(0, DL, VT);
26430 if (CC == ISD::SETLE)
26431 return DAG.getConstant(1, DL, VT);
26432 if (CC == ISD::SETEQ || CC == ISD::SETGE)
26433 return DAG.getNOT(DL, LHS.getOperand(0), VT);
26435 assert((CC == ISD::SETNE || CC == ISD::SETLT) &&
26436 "Unexpected condition code!");
26437 return LHS.getOperand(0);
26444 static SDValue PerformBLENDICombine(SDNode *N, SelectionDAG &DAG) {
26445 SDValue V0 = N->getOperand(0);
26446 SDValue V1 = N->getOperand(1);
26448 EVT VT = N->getValueType(0);
26450 // Canonicalize a v2f64 blend with a mask of 2 by swapping the vector
26451 // operands and changing the mask to 1. This saves us a bunch of
26452 // pattern-matching possibilities related to scalar math ops in SSE/AVX.
26453 // x86InstrInfo knows how to commute this back after instruction selection
26454 // if it would help register allocation.
26456 // TODO: If optimizing for size or a processor that doesn't suffer from
26457 // partial register update stalls, this should be transformed into a MOVSD
26458 // instruction because a MOVSD is 1-2 bytes smaller than a BLENDPD.
26460 if (VT == MVT::v2f64)
26461 if (auto *Mask = dyn_cast<ConstantSDNode>(N->getOperand(2)))
26462 if (Mask->getZExtValue() == 2 && !isShuffleFoldableLoad(V0)) {
26463 SDValue NewMask = DAG.getConstant(1, DL, MVT::i8);
26464 return DAG.getNode(X86ISD::BLENDI, DL, VT, V1, V0, NewMask);
26470 // Helper function of PerformSETCCCombine. It is to materialize "setb reg"
26471 // as "sbb reg,reg", since it can be extended without zext and produces
26472 // an all-ones bit which is more useful than 0/1 in some cases.
26473 static SDValue MaterializeSETB(SDLoc DL, SDValue EFLAGS, SelectionDAG &DAG,
26476 return DAG.getNode(ISD::AND, DL, VT,
26477 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
26478 DAG.getConstant(X86::COND_B, DL, MVT::i8),
26480 DAG.getConstant(1, DL, VT));
26481 assert (VT == MVT::i1 && "Unexpected type for SECCC node");
26482 return DAG.getNode(ISD::TRUNCATE, DL, MVT::i1,
26483 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
26484 DAG.getConstant(X86::COND_B, DL, MVT::i8),
26488 // Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT
26489 static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG,
26490 TargetLowering::DAGCombinerInfo &DCI,
26491 const X86Subtarget *Subtarget) {
26493 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(0));
26494 SDValue EFLAGS = N->getOperand(1);
26496 if (CC == X86::COND_A) {
26497 // Try to convert COND_A into COND_B in an attempt to facilitate
26498 // materializing "setb reg".
26500 // Do not flip "e > c", where "c" is a constant, because Cmp instruction
26501 // cannot take an immediate as its first operand.
26503 if (EFLAGS.getOpcode() == X86ISD::SUB && EFLAGS.hasOneUse() &&
26504 EFLAGS.getValueType().isInteger() &&
26505 !isa<ConstantSDNode>(EFLAGS.getOperand(1))) {
26506 SDValue NewSub = DAG.getNode(X86ISD::SUB, SDLoc(EFLAGS),
26507 EFLAGS.getNode()->getVTList(),
26508 EFLAGS.getOperand(1), EFLAGS.getOperand(0));
26509 SDValue NewEFLAGS = SDValue(NewSub.getNode(), EFLAGS.getResNo());
26510 return MaterializeSETB(DL, NewEFLAGS, DAG, N->getSimpleValueType(0));
26514 // Materialize "setb reg" as "sbb reg,reg", since it can be extended without
26515 // a zext and produces an all-ones bit which is more useful than 0/1 in some
26517 if (CC == X86::COND_B)
26518 return MaterializeSETB(DL, EFLAGS, DAG, N->getSimpleValueType(0));
26520 if (SDValue Flags = checkBoolTestSetCCCombine(EFLAGS, CC)) {
26521 SDValue Cond = DAG.getConstant(CC, DL, MVT::i8);
26522 return DAG.getNode(X86ISD::SETCC, DL, N->getVTList(), Cond, Flags);
26528 // Optimize branch condition evaluation.
26530 static SDValue PerformBrCondCombine(SDNode *N, SelectionDAG &DAG,
26531 TargetLowering::DAGCombinerInfo &DCI,
26532 const X86Subtarget *Subtarget) {
26534 SDValue Chain = N->getOperand(0);
26535 SDValue Dest = N->getOperand(1);
26536 SDValue EFLAGS = N->getOperand(3);
26537 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(2));
26539 if (SDValue Flags = checkBoolTestSetCCCombine(EFLAGS, CC)) {
26540 SDValue Cond = DAG.getConstant(CC, DL, MVT::i8);
26541 return DAG.getNode(X86ISD::BRCOND, DL, N->getVTList(), Chain, Dest, Cond,
26548 static SDValue performVectorCompareAndMaskUnaryOpCombine(SDNode *N,
26549 SelectionDAG &DAG) {
26550 // Take advantage of vector comparisons producing 0 or -1 in each lane to
26551 // optimize away operation when it's from a constant.
26553 // The general transformation is:
26554 // UNARYOP(AND(VECTOR_CMP(x,y), constant)) -->
26555 // AND(VECTOR_CMP(x,y), constant2)
26556 // constant2 = UNARYOP(constant)
26558 // Early exit if this isn't a vector operation, the operand of the
26559 // unary operation isn't a bitwise AND, or if the sizes of the operations
26560 // aren't the same.
26561 EVT VT = N->getValueType(0);
26562 if (!VT.isVector() || N->getOperand(0)->getOpcode() != ISD::AND ||
26563 N->getOperand(0)->getOperand(0)->getOpcode() != ISD::SETCC ||
26564 VT.getSizeInBits() != N->getOperand(0)->getValueType(0).getSizeInBits())
26567 // Now check that the other operand of the AND is a constant. We could
26568 // make the transformation for non-constant splats as well, but it's unclear
26569 // that would be a benefit as it would not eliminate any operations, just
26570 // perform one more step in scalar code before moving to the vector unit.
26571 if (BuildVectorSDNode *BV =
26572 dyn_cast<BuildVectorSDNode>(N->getOperand(0)->getOperand(1))) {
26573 // Bail out if the vector isn't a constant.
26574 if (!BV->isConstant())
26577 // Everything checks out. Build up the new and improved node.
26579 EVT IntVT = BV->getValueType(0);
26580 // Create a new constant of the appropriate type for the transformed
26582 SDValue SourceConst = DAG.getNode(N->getOpcode(), DL, VT, SDValue(BV, 0));
26583 // The AND node needs bitcasts to/from an integer vector type around it.
26584 SDValue MaskConst = DAG.getBitcast(IntVT, SourceConst);
26585 SDValue NewAnd = DAG.getNode(ISD::AND, DL, IntVT,
26586 N->getOperand(0)->getOperand(0), MaskConst);
26587 SDValue Res = DAG.getBitcast(VT, NewAnd);
26594 static SDValue PerformUINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
26595 const X86Subtarget *Subtarget) {
26596 SDValue Op0 = N->getOperand(0);
26597 EVT VT = N->getValueType(0);
26598 EVT InVT = Op0.getValueType();
26599 EVT InSVT = InVT.getScalarType();
26600 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
26602 // UINT_TO_FP(vXi8) -> SINT_TO_FP(ZEXT(vXi8 to vXi32))
26603 // UINT_TO_FP(vXi16) -> SINT_TO_FP(ZEXT(vXi16 to vXi32))
26604 if (InVT.isVector() && (InSVT == MVT::i8 || InSVT == MVT::i16)) {
26606 EVT DstVT = EVT::getVectorVT(*DAG.getContext(), MVT::i32,
26607 InVT.getVectorNumElements());
26608 SDValue P = DAG.getNode(ISD::ZERO_EXTEND, dl, DstVT, Op0);
26610 if (TLI.isOperationLegal(ISD::UINT_TO_FP, DstVT))
26611 return DAG.getNode(ISD::UINT_TO_FP, dl, VT, P);
26613 return DAG.getNode(ISD::SINT_TO_FP, dl, VT, P);
26619 static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
26620 const X86Subtarget *Subtarget) {
26621 // First try to optimize away the conversion entirely when it's
26622 // conditionally from a constant. Vectors only.
26623 if (SDValue Res = performVectorCompareAndMaskUnaryOpCombine(N, DAG))
26626 // Now move on to more general possibilities.
26627 SDValue Op0 = N->getOperand(0);
26628 EVT VT = N->getValueType(0);
26629 EVT InVT = Op0.getValueType();
26630 EVT InSVT = InVT.getScalarType();
26632 // SINT_TO_FP(vXi8) -> SINT_TO_FP(SEXT(vXi8 to vXi32))
26633 // SINT_TO_FP(vXi16) -> SINT_TO_FP(SEXT(vXi16 to vXi32))
26634 if (InVT.isVector() && (InSVT == MVT::i8 || InSVT == MVT::i16)) {
26636 EVT DstVT = EVT::getVectorVT(*DAG.getContext(), MVT::i32,
26637 InVT.getVectorNumElements());
26638 SDValue P = DAG.getNode(ISD::SIGN_EXTEND, dl, DstVT, Op0);
26639 return DAG.getNode(ISD::SINT_TO_FP, dl, VT, P);
26642 // Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have
26643 // a 32-bit target where SSE doesn't support i64->FP operations.
26644 if (!Subtarget->useSoftFloat() && Op0.getOpcode() == ISD::LOAD) {
26645 LoadSDNode *Ld = cast<LoadSDNode>(Op0.getNode());
26646 EVT LdVT = Ld->getValueType(0);
26648 // This transformation is not supported if the result type is f16
26649 if (VT == MVT::f16)
26652 if (!Ld->isVolatile() && !VT.isVector() &&
26653 ISD::isNON_EXTLoad(Op0.getNode()) && Op0.hasOneUse() &&
26654 !Subtarget->is64Bit() && LdVT == MVT::i64) {
26655 SDValue FILDChain = Subtarget->getTargetLowering()->BuildFILD(
26656 SDValue(N, 0), LdVT, Ld->getChain(), Op0, DAG);
26657 DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), FILDChain.getValue(1));
26664 // Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS
26665 static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG,
26666 X86TargetLowering::DAGCombinerInfo &DCI) {
26667 // If the LHS and RHS of the ADC node are zero, then it can't overflow and
26668 // the result is either zero or one (depending on the input carry bit).
26669 // Strength reduce this down to a "set on carry" aka SETCC_CARRY&1.
26670 if (X86::isZeroNode(N->getOperand(0)) &&
26671 X86::isZeroNode(N->getOperand(1)) &&
26672 // We don't have a good way to replace an EFLAGS use, so only do this when
26674 SDValue(N, 1).use_empty()) {
26676 EVT VT = N->getValueType(0);
26677 SDValue CarryOut = DAG.getConstant(0, DL, N->getValueType(1));
26678 SDValue Res1 = DAG.getNode(ISD::AND, DL, VT,
26679 DAG.getNode(X86ISD::SETCC_CARRY, DL, VT,
26680 DAG.getConstant(X86::COND_B, DL,
26683 DAG.getConstant(1, DL, VT));
26684 return DCI.CombineTo(N, Res1, CarryOut);
26690 // fold (add Y, (sete X, 0)) -> adc 0, Y
26691 // (add Y, (setne X, 0)) -> sbb -1, Y
26692 // (sub (sete X, 0), Y) -> sbb 0, Y
26693 // (sub (setne X, 0), Y) -> adc -1, Y
26694 static SDValue OptimizeConditionalInDecrement(SDNode *N, SelectionDAG &DAG) {
26697 // Look through ZExts.
26698 SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0);
26699 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse())
26702 SDValue SetCC = Ext.getOperand(0);
26703 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse())
26706 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0);
26707 if (CC != X86::COND_E && CC != X86::COND_NE)
26710 SDValue Cmp = SetCC.getOperand(1);
26711 if (Cmp.getOpcode() != X86ISD::CMP || !Cmp.hasOneUse() ||
26712 !X86::isZeroNode(Cmp.getOperand(1)) ||
26713 !Cmp.getOperand(0).getValueType().isInteger())
26716 SDValue CmpOp0 = Cmp.getOperand(0);
26717 SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, CmpOp0,
26718 DAG.getConstant(1, DL, CmpOp0.getValueType()));
26720 SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1);
26721 if (CC == X86::COND_NE)
26722 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB,
26723 DL, OtherVal.getValueType(), OtherVal,
26724 DAG.getConstant(-1ULL, DL, OtherVal.getValueType()),
26726 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC,
26727 DL, OtherVal.getValueType(), OtherVal,
26728 DAG.getConstant(0, DL, OtherVal.getValueType()), NewCmp);
26731 /// PerformADDCombine - Do target-specific dag combines on integer adds.
26732 static SDValue PerformAddCombine(SDNode *N, SelectionDAG &DAG,
26733 const X86Subtarget *Subtarget) {
26734 EVT VT = N->getValueType(0);
26735 SDValue Op0 = N->getOperand(0);
26736 SDValue Op1 = N->getOperand(1);
26738 // Try to synthesize horizontal adds from adds of shuffles.
26739 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
26740 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
26741 isHorizontalBinOp(Op0, Op1, true))
26742 return DAG.getNode(X86ISD::HADD, SDLoc(N), VT, Op0, Op1);
26744 return OptimizeConditionalInDecrement(N, DAG);
26747 static SDValue PerformSubCombine(SDNode *N, SelectionDAG &DAG,
26748 const X86Subtarget *Subtarget) {
26749 SDValue Op0 = N->getOperand(0);
26750 SDValue Op1 = N->getOperand(1);
26752 // X86 can't encode an immediate LHS of a sub. See if we can push the
26753 // negation into a preceding instruction.
26754 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op0)) {
26755 // If the RHS of the sub is a XOR with one use and a constant, invert the
26756 // immediate. Then add one to the LHS of the sub so we can turn
26757 // X-Y -> X+~Y+1, saving one register.
26758 if (Op1->hasOneUse() && Op1.getOpcode() == ISD::XOR &&
26759 isa<ConstantSDNode>(Op1.getOperand(1))) {
26760 APInt XorC = cast<ConstantSDNode>(Op1.getOperand(1))->getAPIntValue();
26761 EVT VT = Op0.getValueType();
26762 SDValue NewXor = DAG.getNode(ISD::XOR, SDLoc(Op1), VT,
26764 DAG.getConstant(~XorC, SDLoc(Op1), VT));
26765 return DAG.getNode(ISD::ADD, SDLoc(N), VT, NewXor,
26766 DAG.getConstant(C->getAPIntValue() + 1, SDLoc(N), VT));
26770 // Try to synthesize horizontal adds from adds of shuffles.
26771 EVT VT = N->getValueType(0);
26772 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
26773 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
26774 isHorizontalBinOp(Op0, Op1, true))
26775 return DAG.getNode(X86ISD::HSUB, SDLoc(N), VT, Op0, Op1);
26777 return OptimizeConditionalInDecrement(N, DAG);
26780 /// performVZEXTCombine - Performs build vector combines
26781 static SDValue performVZEXTCombine(SDNode *N, SelectionDAG &DAG,
26782 TargetLowering::DAGCombinerInfo &DCI,
26783 const X86Subtarget *Subtarget) {
26785 MVT VT = N->getSimpleValueType(0);
26786 SDValue Op = N->getOperand(0);
26787 MVT OpVT = Op.getSimpleValueType();
26788 MVT OpEltVT = OpVT.getVectorElementType();
26789 unsigned InputBits = OpEltVT.getSizeInBits() * VT.getVectorNumElements();
26791 // (vzext (bitcast (vzext (x)) -> (vzext x)
26793 while (V.getOpcode() == ISD::BITCAST)
26794 V = V.getOperand(0);
26796 if (V != Op && V.getOpcode() == X86ISD::VZEXT) {
26797 MVT InnerVT = V.getSimpleValueType();
26798 MVT InnerEltVT = InnerVT.getVectorElementType();
26800 // If the element sizes match exactly, we can just do one larger vzext. This
26801 // is always an exact type match as vzext operates on integer types.
26802 if (OpEltVT == InnerEltVT) {
26803 assert(OpVT == InnerVT && "Types must match for vzext!");
26804 return DAG.getNode(X86ISD::VZEXT, DL, VT, V.getOperand(0));
26807 // The only other way we can combine them is if only a single element of the
26808 // inner vzext is used in the input to the outer vzext.
26809 if (InnerEltVT.getSizeInBits() < InputBits)
26812 // In this case, the inner vzext is completely dead because we're going to
26813 // only look at bits inside of the low element. Just do the outer vzext on
26814 // a bitcast of the input to the inner.
26815 return DAG.getNode(X86ISD::VZEXT, DL, VT, DAG.getBitcast(OpVT, V));
26818 // Check if we can bypass extracting and re-inserting an element of an input
26819 // vector. Essentially:
26820 // (bitcast (sclr2vec (ext_vec_elt x))) -> (bitcast x)
26821 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR &&
26822 V.getOperand(0).getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
26823 V.getOperand(0).getSimpleValueType().getSizeInBits() == InputBits) {
26824 SDValue ExtractedV = V.getOperand(0);
26825 SDValue OrigV = ExtractedV.getOperand(0);
26826 if (auto *ExtractIdx = dyn_cast<ConstantSDNode>(ExtractedV.getOperand(1)))
26827 if (ExtractIdx->getZExtValue() == 0) {
26828 MVT OrigVT = OrigV.getSimpleValueType();
26829 // Extract a subvector if necessary...
26830 if (OrigVT.getSizeInBits() > OpVT.getSizeInBits()) {
26831 int Ratio = OrigVT.getSizeInBits() / OpVT.getSizeInBits();
26832 OrigVT = MVT::getVectorVT(OrigVT.getVectorElementType(),
26833 OrigVT.getVectorNumElements() / Ratio);
26834 OrigV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, OrigVT, OrigV,
26835 DAG.getIntPtrConstant(0, DL));
26837 Op = DAG.getBitcast(OpVT, OrigV);
26838 return DAG.getNode(X86ISD::VZEXT, DL, VT, Op);
26845 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
26846 DAGCombinerInfo &DCI) const {
26847 SelectionDAG &DAG = DCI.DAG;
26848 switch (N->getOpcode()) {
26850 case ISD::EXTRACT_VECTOR_ELT:
26851 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, DCI);
26854 case X86ISD::SHRUNKBLEND:
26855 return PerformSELECTCombine(N, DAG, DCI, Subtarget);
26856 case ISD::BITCAST: return PerformBITCASTCombine(N, DAG, Subtarget);
26857 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI, Subtarget);
26858 case ISD::ADD: return PerformAddCombine(N, DAG, Subtarget);
26859 case ISD::SUB: return PerformSubCombine(N, DAG, Subtarget);
26860 case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI);
26861 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
26864 case ISD::SRL: return PerformShiftCombine(N, DAG, DCI, Subtarget);
26865 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget);
26866 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget);
26867 case ISD::XOR: return PerformXorCombine(N, DAG, DCI, Subtarget);
26868 case ISD::LOAD: return PerformLOADCombine(N, DAG, DCI, Subtarget);
26869 case ISD::MLOAD: return PerformMLOADCombine(N, DAG, DCI, Subtarget);
26870 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
26871 case ISD::MSTORE: return PerformMSTORECombine(N, DAG, Subtarget);
26872 case ISD::SINT_TO_FP: return PerformSINT_TO_FPCombine(N, DAG, Subtarget);
26873 case ISD::UINT_TO_FP: return PerformUINT_TO_FPCombine(N, DAG, Subtarget);
26874 case ISD::FADD: return PerformFADDCombine(N, DAG, Subtarget);
26875 case ISD::FSUB: return PerformFSUBCombine(N, DAG, Subtarget);
26877 case X86ISD::FOR: return PerformFORCombine(N, DAG, Subtarget);
26879 case X86ISD::FMAX: return PerformFMinFMaxCombine(N, DAG);
26880 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
26881 case X86ISD::FANDN: return PerformFANDNCombine(N, DAG);
26882 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
26883 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
26884 case ISD::ANY_EXTEND:
26885 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG, DCI, Subtarget);
26886 case ISD::SIGN_EXTEND: return PerformSExtCombine(N, DAG, DCI, Subtarget);
26887 case ISD::SIGN_EXTEND_INREG:
26888 return PerformSIGN_EXTEND_INREGCombine(N, DAG, Subtarget);
26889 case ISD::SETCC: return PerformISDSETCCCombine(N, DAG, Subtarget);
26890 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG, DCI, Subtarget);
26891 case X86ISD::BRCOND: return PerformBrCondCombine(N, DAG, DCI, Subtarget);
26892 case X86ISD::VZEXT: return performVZEXTCombine(N, DAG, DCI, Subtarget);
26893 case X86ISD::SHUFP: // Handle all target specific shuffles
26894 case X86ISD::PALIGNR:
26895 case X86ISD::UNPCKH:
26896 case X86ISD::UNPCKL:
26897 case X86ISD::MOVHLPS:
26898 case X86ISD::MOVLHPS:
26899 case X86ISD::PSHUFB:
26900 case X86ISD::PSHUFD:
26901 case X86ISD::PSHUFHW:
26902 case X86ISD::PSHUFLW:
26903 case X86ISD::MOVSS:
26904 case X86ISD::MOVSD:
26905 case X86ISD::VPERMILPI:
26906 case X86ISD::VPERM2X128:
26907 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget);
26908 case ISD::FMA: return PerformFMACombine(N, DAG, Subtarget);
26909 case X86ISD::BLENDI: return PerformBLENDICombine(N, DAG);
26915 /// isTypeDesirableForOp - Return true if the target has native support for
26916 /// the specified value type and it is 'desirable' to use the type for the
26917 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
26918 /// instruction encodings are longer and some i16 instructions are slow.
26919 bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const {
26920 if (!isTypeLegal(VT))
26922 if (VT != MVT::i16)
26929 case ISD::SIGN_EXTEND:
26930 case ISD::ZERO_EXTEND:
26931 case ISD::ANY_EXTEND:
26944 /// IsDesirableToPromoteOp - This method query the target whether it is
26945 /// beneficial for dag combiner to promote the specified node. If true, it
26946 /// should return the desired promotion type by reference.
26947 bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
26948 EVT VT = Op.getValueType();
26949 if (VT != MVT::i16)
26952 bool Promote = false;
26953 bool Commute = false;
26954 switch (Op.getOpcode()) {
26957 LoadSDNode *LD = cast<LoadSDNode>(Op);
26958 // If the non-extending load has a single use and it's not live out, then it
26959 // might be folded.
26960 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&&
26961 Op.hasOneUse()*/) {
26962 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
26963 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
26964 // The only case where we'd want to promote LOAD (rather then it being
26965 // promoted as an operand is when it's only use is liveout.
26966 if (UI->getOpcode() != ISD::CopyToReg)
26973 case ISD::SIGN_EXTEND:
26974 case ISD::ZERO_EXTEND:
26975 case ISD::ANY_EXTEND:
26980 SDValue N0 = Op.getOperand(0);
26981 // Look out for (store (shl (load), x)).
26982 if (MayFoldLoad(N0) && MayFoldIntoStore(Op))
26995 SDValue N0 = Op.getOperand(0);
26996 SDValue N1 = Op.getOperand(1);
26997 if (!Commute && MayFoldLoad(N1))
26999 // Avoid disabling potential load folding opportunities.
27000 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op)))
27002 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op)))
27012 //===----------------------------------------------------------------------===//
27013 // X86 Inline Assembly Support
27014 //===----------------------------------------------------------------------===//
27016 // Helper to match a string separated by whitespace.
27017 static bool matchAsm(StringRef S, ArrayRef<const char *> Pieces) {
27018 S = S.substr(S.find_first_not_of(" \t")); // Skip leading whitespace.
27020 for (StringRef Piece : Pieces) {
27021 if (!S.startswith(Piece)) // Check if the piece matches.
27024 S = S.substr(Piece.size());
27025 StringRef::size_type Pos = S.find_first_not_of(" \t");
27026 if (Pos == 0) // We matched a prefix.
27035 static bool clobbersFlagRegisters(const SmallVector<StringRef, 4> &AsmPieces) {
27037 if (AsmPieces.size() == 3 || AsmPieces.size() == 4) {
27038 if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{cc}") &&
27039 std::count(AsmPieces.begin(), AsmPieces.end(), "~{flags}") &&
27040 std::count(AsmPieces.begin(), AsmPieces.end(), "~{fpsr}")) {
27042 if (AsmPieces.size() == 3)
27044 else if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{dirflag}"))
27051 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
27052 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
27054 std::string AsmStr = IA->getAsmString();
27056 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
27057 if (!Ty || Ty->getBitWidth() % 16 != 0)
27060 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
27061 SmallVector<StringRef, 4> AsmPieces;
27062 SplitString(AsmStr, AsmPieces, ";\n");
27064 switch (AsmPieces.size()) {
27065 default: return false;
27067 // FIXME: this should verify that we are targeting a 486 or better. If not,
27068 // we will turn this bswap into something that will be lowered to logical
27069 // ops instead of emitting the bswap asm. For now, we don't support 486 or
27070 // lower so don't worry about this.
27072 if (matchAsm(AsmPieces[0], {"bswap", "$0"}) ||
27073 matchAsm(AsmPieces[0], {"bswapl", "$0"}) ||
27074 matchAsm(AsmPieces[0], {"bswapq", "$0"}) ||
27075 matchAsm(AsmPieces[0], {"bswap", "${0:q}"}) ||
27076 matchAsm(AsmPieces[0], {"bswapl", "${0:q}"}) ||
27077 matchAsm(AsmPieces[0], {"bswapq", "${0:q}"})) {
27078 // No need to check constraints, nothing other than the equivalent of
27079 // "=r,0" would be valid here.
27080 return IntrinsicLowering::LowerToByteSwap(CI);
27083 // rorw $$8, ${0:w} --> llvm.bswap.i16
27084 if (CI->getType()->isIntegerTy(16) &&
27085 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
27086 (matchAsm(AsmPieces[0], {"rorw", "$$8,", "${0:w}"}) ||
27087 matchAsm(AsmPieces[0], {"rolw", "$$8,", "${0:w}"}))) {
27089 StringRef ConstraintsStr = IA->getConstraintString();
27090 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
27091 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
27092 if (clobbersFlagRegisters(AsmPieces))
27093 return IntrinsicLowering::LowerToByteSwap(CI);
27097 if (CI->getType()->isIntegerTy(32) &&
27098 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
27099 matchAsm(AsmPieces[0], {"rorw", "$$8,", "${0:w}"}) &&
27100 matchAsm(AsmPieces[1], {"rorl", "$$16,", "$0"}) &&
27101 matchAsm(AsmPieces[2], {"rorw", "$$8,", "${0:w}"})) {
27103 StringRef ConstraintsStr = IA->getConstraintString();
27104 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
27105 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
27106 if (clobbersFlagRegisters(AsmPieces))
27107 return IntrinsicLowering::LowerToByteSwap(CI);
27110 if (CI->getType()->isIntegerTy(64)) {
27111 InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints();
27112 if (Constraints.size() >= 2 &&
27113 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
27114 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
27115 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
27116 if (matchAsm(AsmPieces[0], {"bswap", "%eax"}) &&
27117 matchAsm(AsmPieces[1], {"bswap", "%edx"}) &&
27118 matchAsm(AsmPieces[2], {"xchgl", "%eax,", "%edx"}))
27119 return IntrinsicLowering::LowerToByteSwap(CI);
27127 /// getConstraintType - Given a constraint letter, return the type of
27128 /// constraint it is for this target.
27129 X86TargetLowering::ConstraintType
27130 X86TargetLowering::getConstraintType(StringRef Constraint) const {
27131 if (Constraint.size() == 1) {
27132 switch (Constraint[0]) {
27143 return C_RegisterClass;
27167 return TargetLowering::getConstraintType(Constraint);
27170 /// Examine constraint type and operand type and determine a weight value.
27171 /// This object must already have been set up with the operand type
27172 /// and the current alternative constraint selected.
27173 TargetLowering::ConstraintWeight
27174 X86TargetLowering::getSingleConstraintMatchWeight(
27175 AsmOperandInfo &info, const char *constraint) const {
27176 ConstraintWeight weight = CW_Invalid;
27177 Value *CallOperandVal = info.CallOperandVal;
27178 // If we don't have a value, we can't do a match,
27179 // but allow it at the lowest weight.
27180 if (!CallOperandVal)
27182 Type *type = CallOperandVal->getType();
27183 // Look at the constraint type.
27184 switch (*constraint) {
27186 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
27197 if (CallOperandVal->getType()->isIntegerTy())
27198 weight = CW_SpecificReg;
27203 if (type->isFloatingPointTy())
27204 weight = CW_SpecificReg;
27207 if (type->isX86_MMXTy() && Subtarget->hasMMX())
27208 weight = CW_SpecificReg;
27212 if (((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasSSE1()) ||
27213 ((type->getPrimitiveSizeInBits() == 256) && Subtarget->hasFp256()))
27214 weight = CW_Register;
27217 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) {
27218 if (C->getZExtValue() <= 31)
27219 weight = CW_Constant;
27223 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
27224 if (C->getZExtValue() <= 63)
27225 weight = CW_Constant;
27229 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
27230 if ((C->getSExtValue() >= -0x80) && (C->getSExtValue() <= 0x7f))
27231 weight = CW_Constant;
27235 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
27236 if ((C->getZExtValue() == 0xff) || (C->getZExtValue() == 0xffff))
27237 weight = CW_Constant;
27241 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
27242 if (C->getZExtValue() <= 3)
27243 weight = CW_Constant;
27247 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
27248 if (C->getZExtValue() <= 0xff)
27249 weight = CW_Constant;
27254 if (isa<ConstantFP>(CallOperandVal)) {
27255 weight = CW_Constant;
27259 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
27260 if ((C->getSExtValue() >= -0x80000000LL) &&
27261 (C->getSExtValue() <= 0x7fffffffLL))
27262 weight = CW_Constant;
27266 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
27267 if (C->getZExtValue() <= 0xffffffff)
27268 weight = CW_Constant;
27275 /// LowerXConstraint - try to replace an X constraint, which matches anything,
27276 /// with another that has more specific requirements based on the type of the
27277 /// corresponding operand.
27278 const char *X86TargetLowering::
27279 LowerXConstraint(EVT ConstraintVT) const {
27280 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
27281 // 'f' like normal targets.
27282 if (ConstraintVT.isFloatingPoint()) {
27283 if (Subtarget->hasSSE2())
27285 if (Subtarget->hasSSE1())
27289 return TargetLowering::LowerXConstraint(ConstraintVT);
27292 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
27293 /// vector. If it is invalid, don't add anything to Ops.
27294 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
27295 std::string &Constraint,
27296 std::vector<SDValue>&Ops,
27297 SelectionDAG &DAG) const {
27300 // Only support length 1 constraints for now.
27301 if (Constraint.length() > 1) return;
27303 char ConstraintLetter = Constraint[0];
27304 switch (ConstraintLetter) {
27307 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
27308 if (C->getZExtValue() <= 31) {
27309 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
27310 Op.getValueType());
27316 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
27317 if (C->getZExtValue() <= 63) {
27318 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
27319 Op.getValueType());
27325 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
27326 if (isInt<8>(C->getSExtValue())) {
27327 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
27328 Op.getValueType());
27334 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
27335 if (C->getZExtValue() == 0xff || C->getZExtValue() == 0xffff ||
27336 (Subtarget->is64Bit() && C->getZExtValue() == 0xffffffff)) {
27337 Result = DAG.getTargetConstant(C->getSExtValue(), SDLoc(Op),
27338 Op.getValueType());
27344 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
27345 if (C->getZExtValue() <= 3) {
27346 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
27347 Op.getValueType());
27353 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
27354 if (C->getZExtValue() <= 255) {
27355 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
27356 Op.getValueType());
27362 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
27363 if (C->getZExtValue() <= 127) {
27364 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
27365 Op.getValueType());
27371 // 32-bit signed value
27372 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
27373 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
27374 C->getSExtValue())) {
27375 // Widen to 64 bits here to get it sign extended.
27376 Result = DAG.getTargetConstant(C->getSExtValue(), SDLoc(Op), MVT::i64);
27379 // FIXME gcc accepts some relocatable values here too, but only in certain
27380 // memory models; it's complicated.
27385 // 32-bit unsigned value
27386 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
27387 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
27388 C->getZExtValue())) {
27389 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
27390 Op.getValueType());
27394 // FIXME gcc accepts some relocatable values here too, but only in certain
27395 // memory models; it's complicated.
27399 // Literal immediates are always ok.
27400 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
27401 // Widen to 64 bits here to get it sign extended.
27402 Result = DAG.getTargetConstant(CST->getSExtValue(), SDLoc(Op), MVT::i64);
27406 // In any sort of PIC mode addresses need to be computed at runtime by
27407 // adding in a register or some sort of table lookup. These can't
27408 // be used as immediates.
27409 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC())
27412 // If we are in non-pic codegen mode, we allow the address of a global (with
27413 // an optional displacement) to be used with 'i'.
27414 GlobalAddressSDNode *GA = nullptr;
27415 int64_t Offset = 0;
27417 // Match either (GA), (GA+C), (GA+C1+C2), etc.
27419 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
27420 Offset += GA->getOffset();
27422 } else if (Op.getOpcode() == ISD::ADD) {
27423 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
27424 Offset += C->getZExtValue();
27425 Op = Op.getOperand(0);
27428 } else if (Op.getOpcode() == ISD::SUB) {
27429 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
27430 Offset += -C->getZExtValue();
27431 Op = Op.getOperand(0);
27436 // Otherwise, this isn't something we can handle, reject it.
27440 const GlobalValue *GV = GA->getGlobal();
27441 // If we require an extra load to get this address, as in PIC mode, we
27442 // can't accept it.
27443 if (isGlobalStubReference(
27444 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget())))
27447 Result = DAG.getTargetGlobalAddress(GV, SDLoc(Op),
27448 GA->getValueType(0), Offset);
27453 if (Result.getNode()) {
27454 Ops.push_back(Result);
27457 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
27460 std::pair<unsigned, const TargetRegisterClass *>
27461 X86TargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
27462 StringRef Constraint,
27464 // First, see if this is a constraint that directly corresponds to an LLVM
27466 if (Constraint.size() == 1) {
27467 // GCC Constraint Letters
27468 switch (Constraint[0]) {
27470 // TODO: Slight differences here in allocation order and leaving
27471 // RIP in the class. Do they matter any more here than they do
27472 // in the normal allocation?
27473 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
27474 if (Subtarget->is64Bit()) {
27475 if (VT == MVT::i32 || VT == MVT::f32)
27476 return std::make_pair(0U, &X86::GR32RegClass);
27477 if (VT == MVT::i16)
27478 return std::make_pair(0U, &X86::GR16RegClass);
27479 if (VT == MVT::i8 || VT == MVT::i1)
27480 return std::make_pair(0U, &X86::GR8RegClass);
27481 if (VT == MVT::i64 || VT == MVT::f64)
27482 return std::make_pair(0U, &X86::GR64RegClass);
27485 // 32-bit fallthrough
27486 case 'Q': // Q_REGS
27487 if (VT == MVT::i32 || VT == MVT::f32)
27488 return std::make_pair(0U, &X86::GR32_ABCDRegClass);
27489 if (VT == MVT::i16)
27490 return std::make_pair(0U, &X86::GR16_ABCDRegClass);
27491 if (VT == MVT::i8 || VT == MVT::i1)
27492 return std::make_pair(0U, &X86::GR8_ABCD_LRegClass);
27493 if (VT == MVT::i64)
27494 return std::make_pair(0U, &X86::GR64_ABCDRegClass);
27496 case 'r': // GENERAL_REGS
27497 case 'l': // INDEX_REGS
27498 if (VT == MVT::i8 || VT == MVT::i1)
27499 return std::make_pair(0U, &X86::GR8RegClass);
27500 if (VT == MVT::i16)
27501 return std::make_pair(0U, &X86::GR16RegClass);
27502 if (VT == MVT::i32 || VT == MVT::f32 || !Subtarget->is64Bit())
27503 return std::make_pair(0U, &X86::GR32RegClass);
27504 return std::make_pair(0U, &X86::GR64RegClass);
27505 case 'R': // LEGACY_REGS
27506 if (VT == MVT::i8 || VT == MVT::i1)
27507 return std::make_pair(0U, &X86::GR8_NOREXRegClass);
27508 if (VT == MVT::i16)
27509 return std::make_pair(0U, &X86::GR16_NOREXRegClass);
27510 if (VT == MVT::i32 || !Subtarget->is64Bit())
27511 return std::make_pair(0U, &X86::GR32_NOREXRegClass);
27512 return std::make_pair(0U, &X86::GR64_NOREXRegClass);
27513 case 'f': // FP Stack registers.
27514 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
27515 // value to the correct fpstack register class.
27516 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
27517 return std::make_pair(0U, &X86::RFP32RegClass);
27518 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
27519 return std::make_pair(0U, &X86::RFP64RegClass);
27520 return std::make_pair(0U, &X86::RFP80RegClass);
27521 case 'y': // MMX_REGS if MMX allowed.
27522 if (!Subtarget->hasMMX()) break;
27523 return std::make_pair(0U, &X86::VR64RegClass);
27524 case 'Y': // SSE_REGS if SSE2 allowed
27525 if (!Subtarget->hasSSE2()) break;
27527 case 'x': // SSE_REGS if SSE1 allowed or AVX_REGS if AVX allowed
27528 if (!Subtarget->hasSSE1()) break;
27530 switch (VT.SimpleTy) {
27532 // Scalar SSE types.
27535 return std::make_pair(0U, &X86::FR32RegClass);
27538 return std::make_pair(0U, &X86::FR64RegClass);
27546 return std::make_pair(0U, &X86::VR128RegClass);
27554 return std::make_pair(0U, &X86::VR256RegClass);
27559 return std::make_pair(0U, &X86::VR512RegClass);
27565 // Use the default implementation in TargetLowering to convert the register
27566 // constraint into a member of a register class.
27567 std::pair<unsigned, const TargetRegisterClass*> Res;
27568 Res = TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
27570 // Not found as a standard register?
27572 // Map st(0) -> st(7) -> ST0
27573 if (Constraint.size() == 7 && Constraint[0] == '{' &&
27574 tolower(Constraint[1]) == 's' &&
27575 tolower(Constraint[2]) == 't' &&
27576 Constraint[3] == '(' &&
27577 (Constraint[4] >= '0' && Constraint[4] <= '7') &&
27578 Constraint[5] == ')' &&
27579 Constraint[6] == '}') {
27581 Res.first = X86::FP0+Constraint[4]-'0';
27582 Res.second = &X86::RFP80RegClass;
27586 // GCC allows "st(0)" to be called just plain "st".
27587 if (StringRef("{st}").equals_lower(Constraint)) {
27588 Res.first = X86::FP0;
27589 Res.second = &X86::RFP80RegClass;
27594 if (StringRef("{flags}").equals_lower(Constraint)) {
27595 Res.first = X86::EFLAGS;
27596 Res.second = &X86::CCRRegClass;
27600 // 'A' means EAX + EDX.
27601 if (Constraint == "A") {
27602 Res.first = X86::EAX;
27603 Res.second = &X86::GR32_ADRegClass;
27609 // Otherwise, check to see if this is a register class of the wrong value
27610 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
27611 // turn into {ax},{dx}.
27612 // MVT::Other is used to specify clobber names.
27613 if (Res.second->hasType(VT) || VT == MVT::Other)
27614 return Res; // Correct type already, nothing to do.
27616 // Get a matching integer of the correct size. i.e. "ax" with MVT::32 should
27617 // return "eax". This should even work for things like getting 64bit integer
27618 // registers when given an f64 type.
27619 const TargetRegisterClass *Class = Res.second;
27620 if (Class == &X86::GR8RegClass || Class == &X86::GR16RegClass ||
27621 Class == &X86::GR32RegClass || Class == &X86::GR64RegClass) {
27622 unsigned Size = VT.getSizeInBits();
27623 MVT::SimpleValueType SimpleTy = Size == 1 || Size == 8 ? MVT::i8
27624 : Size == 16 ? MVT::i16
27625 : Size == 32 ? MVT::i32
27626 : Size == 64 ? MVT::i64
27628 unsigned DestReg = getX86SubSuperRegisterOrZero(Res.first, SimpleTy);
27630 Res.first = DestReg;
27631 Res.second = SimpleTy == MVT::i8 ? &X86::GR8RegClass
27632 : SimpleTy == MVT::i16 ? &X86::GR16RegClass
27633 : SimpleTy == MVT::i32 ? &X86::GR32RegClass
27634 : &X86::GR64RegClass;
27635 assert(Res.second->contains(Res.first) && "Register in register class");
27637 // No register found/type mismatch.
27639 Res.second = nullptr;
27641 } else if (Class == &X86::FR32RegClass || Class == &X86::FR64RegClass ||
27642 Class == &X86::VR128RegClass || Class == &X86::VR256RegClass ||
27643 Class == &X86::FR32XRegClass || Class == &X86::FR64XRegClass ||
27644 Class == &X86::VR128XRegClass || Class == &X86::VR256XRegClass ||
27645 Class == &X86::VR512RegClass) {
27646 // Handle references to XMM physical registers that got mapped into the
27647 // wrong class. This can happen with constraints like {xmm0} where the
27648 // target independent register mapper will just pick the first match it can
27649 // find, ignoring the required type.
27651 if (VT == MVT::f32 || VT == MVT::i32)
27652 Res.second = &X86::FR32RegClass;
27653 else if (VT == MVT::f64 || VT == MVT::i64)
27654 Res.second = &X86::FR64RegClass;
27655 else if (X86::VR128RegClass.hasType(VT))
27656 Res.second = &X86::VR128RegClass;
27657 else if (X86::VR256RegClass.hasType(VT))
27658 Res.second = &X86::VR256RegClass;
27659 else if (X86::VR512RegClass.hasType(VT))
27660 Res.second = &X86::VR512RegClass;
27662 // Type mismatch and not a clobber: Return an error;
27664 Res.second = nullptr;
27671 int X86TargetLowering::getScalingFactorCost(const DataLayout &DL,
27672 const AddrMode &AM, Type *Ty,
27673 unsigned AS) const {
27674 // Scaling factors are not free at all.
27675 // An indexed folded instruction, i.e., inst (reg1, reg2, scale),
27676 // will take 2 allocations in the out of order engine instead of 1
27677 // for plain addressing mode, i.e. inst (reg1).
27679 // vaddps (%rsi,%drx), %ymm0, %ymm1
27680 // Requires two allocations (one for the load, one for the computation)
27682 // vaddps (%rsi), %ymm0, %ymm1
27683 // Requires just 1 allocation, i.e., freeing allocations for other operations
27684 // and having less micro operations to execute.
27686 // For some X86 architectures, this is even worse because for instance for
27687 // stores, the complex addressing mode forces the instruction to use the
27688 // "load" ports instead of the dedicated "store" port.
27689 // E.g., on Haswell:
27690 // vmovaps %ymm1, (%r8, %rdi) can use port 2 or 3.
27691 // vmovaps %ymm1, (%r8) can use port 2, 3, or 7.
27692 if (isLegalAddressingMode(DL, AM, Ty, AS))
27693 // Scale represents reg2 * scale, thus account for 1
27694 // as soon as we use a second register.
27695 return AM.Scale != 0;
27699 bool X86TargetLowering::isIntDivCheap(EVT VT, AttributeSet Attr) const {
27700 // Integer division on x86 is expensive. However, when aggressively optimizing
27701 // for code size, we prefer to use a div instruction, as it is usually smaller
27702 // than the alternative sequence.
27703 // The exception to this is vector division. Since x86 doesn't have vector
27704 // integer division, leaving the division as-is is a loss even in terms of
27705 // size, because it will have to be scalarized, while the alternative code
27706 // sequence can be performed in vector form.
27707 bool OptSize = Attr.hasAttribute(AttributeSet::FunctionIndex,
27708 Attribute::MinSize);
27709 return OptSize && !VT.isVector();
27712 void X86TargetLowering::markInRegArguments(SelectionDAG &DAG,
27713 TargetLowering::ArgListTy& Args) const {
27714 // The MCU psABI requires some arguments to be passed in-register.
27715 // For regular calls, the inreg arguments are marked by the front-end.
27716 // However, for compiler generated library calls, we have to patch this
27718 if (!Subtarget->isTargetMCU() || !Args.size())
27721 unsigned FreeRegs = 3;
27722 for (auto &Arg : Args) {
27723 // For library functions, we do not expect any fancy types.
27724 unsigned Size = DAG.getDataLayout().getTypeSizeInBits(Arg.Ty);
27725 unsigned SizeInRegs = (Size + 31) / 32;
27726 if (SizeInRegs > 2 || SizeInRegs > FreeRegs)
27729 Arg.isInReg = true;
27730 FreeRegs -= SizeInRegs;