1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "x86-isel"
16 #include "X86ISelLowering.h"
17 #include "Utils/X86ShuffleDecode.h"
19 #include "X86InstrBuilder.h"
20 #include "X86TargetMachine.h"
21 #include "X86TargetObjectFile.h"
22 #include "llvm/ADT/SmallSet.h"
23 #include "llvm/ADT/Statistic.h"
24 #include "llvm/ADT/StringExtras.h"
25 #include "llvm/ADT/VariadicFunction.h"
26 #include "llvm/CodeGen/IntrinsicLowering.h"
27 #include "llvm/CodeGen/MachineFrameInfo.h"
28 #include "llvm/CodeGen/MachineFunction.h"
29 #include "llvm/CodeGen/MachineInstrBuilder.h"
30 #include "llvm/CodeGen/MachineJumpTableInfo.h"
31 #include "llvm/CodeGen/MachineModuleInfo.h"
32 #include "llvm/CodeGen/MachineRegisterInfo.h"
33 #include "llvm/IR/CallingConv.h"
34 #include "llvm/IR/Constants.h"
35 #include "llvm/IR/DerivedTypes.h"
36 #include "llvm/IR/Function.h"
37 #include "llvm/IR/GlobalAlias.h"
38 #include "llvm/IR/GlobalVariable.h"
39 #include "llvm/IR/Instructions.h"
40 #include "llvm/IR/Intrinsics.h"
41 #include "llvm/IR/LLVMContext.h"
42 #include "llvm/MC/MCAsmInfo.h"
43 #include "llvm/MC/MCContext.h"
44 #include "llvm/MC/MCExpr.h"
45 #include "llvm/MC/MCSymbol.h"
46 #include "llvm/Support/CallSite.h"
47 #include "llvm/Support/Debug.h"
48 #include "llvm/Support/ErrorHandling.h"
49 #include "llvm/Support/MathExtras.h"
50 #include "llvm/Target/TargetOptions.h"
55 STATISTIC(NumTailCalls, "Number of tail calls");
57 // Forward declarations.
58 static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
61 /// Generate a DAG to grab 128-bits from a vector > 128 bits. This
62 /// sets things up to match to an AVX VEXTRACTF128 instruction or a
63 /// simple subregister reference. Idx is an index in the 128 bits we
64 /// want. It need not be aligned to a 128-bit bounday. That makes
65 /// lowering EXTRACT_VECTOR_ELT operations easier.
66 static SDValue Extract128BitVector(SDValue Vec, unsigned IdxVal,
67 SelectionDAG &DAG, DebugLoc dl) {
68 EVT VT = Vec.getValueType();
69 assert(VT.is256BitVector() && "Unexpected vector size!");
70 EVT ElVT = VT.getVectorElementType();
71 unsigned Factor = VT.getSizeInBits()/128;
72 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT,
73 VT.getVectorNumElements()/Factor);
75 // Extract from UNDEF is UNDEF.
76 if (Vec.getOpcode() == ISD::UNDEF)
77 return DAG.getUNDEF(ResultVT);
79 // Extract the relevant 128 bits. Generate an EXTRACT_SUBVECTOR
80 // we can match to VEXTRACTF128.
81 unsigned ElemsPerChunk = 128 / ElVT.getSizeInBits();
83 // This is the index of the first element of the 128-bit chunk
85 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits()) / 128)
88 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal);
89 SDValue Result = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec,
95 /// Generate a DAG to put 128-bits into a vector > 128 bits. This
96 /// sets things up to match to an AVX VINSERTF128 instruction or a
97 /// simple superregister reference. Idx is an index in the 128 bits
98 /// we want. It need not be aligned to a 128-bit bounday. That makes
99 /// lowering INSERT_VECTOR_ELT operations easier.
100 static SDValue Insert128BitVector(SDValue Result, SDValue Vec,
101 unsigned IdxVal, SelectionDAG &DAG,
103 // Inserting UNDEF is Result
104 if (Vec.getOpcode() == ISD::UNDEF)
107 EVT VT = Vec.getValueType();
108 assert(VT.is128BitVector() && "Unexpected vector size!");
110 EVT ElVT = VT.getVectorElementType();
111 EVT ResultVT = Result.getValueType();
113 // Insert the relevant 128 bits.
114 unsigned ElemsPerChunk = 128/ElVT.getSizeInBits();
116 // This is the index of the first element of the 128-bit chunk
118 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits())/128)
121 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal);
122 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec,
126 /// Concat two 128-bit vectors into a 256 bit vector using VINSERTF128
127 /// instructions. This is used because creating CONCAT_VECTOR nodes of
128 /// BUILD_VECTORS returns a larger BUILD_VECTOR while we're trying to lower
129 /// large BUILD_VECTORS.
130 static SDValue Concat128BitVectors(SDValue V1, SDValue V2, EVT VT,
131 unsigned NumElems, SelectionDAG &DAG,
133 SDValue V = Insert128BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
134 return Insert128BitVector(V, V2, NumElems/2, DAG, dl);
137 static TargetLoweringObjectFile *createTLOF(X86TargetMachine &TM) {
138 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
139 bool is64Bit = Subtarget->is64Bit();
141 if (Subtarget->isTargetEnvMacho()) {
143 return new X86_64MachoTargetObjectFile();
144 return new TargetLoweringObjectFileMachO();
147 if (Subtarget->isTargetLinux())
148 return new X86LinuxTargetObjectFile();
149 if (Subtarget->isTargetELF())
150 return new TargetLoweringObjectFileELF();
151 if (Subtarget->isTargetCOFF() && !Subtarget->isTargetEnvMacho())
152 return new TargetLoweringObjectFileCOFF();
153 llvm_unreachable("unknown subtarget type");
156 X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
157 : TargetLowering(TM, createTLOF(TM)) {
158 Subtarget = &TM.getSubtarget<X86Subtarget>();
159 X86ScalarSSEf64 = Subtarget->hasSSE2();
160 X86ScalarSSEf32 = Subtarget->hasSSE1();
162 RegInfo = TM.getRegisterInfo();
163 TD = getDataLayout();
165 // Set up the TargetLowering object.
166 static const MVT IntVTs[] = { MVT::i8, MVT::i16, MVT::i32, MVT::i64 };
168 // X86 is weird, it always uses i8 for shift amounts and setcc results.
169 setBooleanContents(ZeroOrOneBooleanContent);
170 // X86-SSE is even stranger. It uses -1 or 0 for vector masks.
171 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
173 // For 64-bit since we have so many registers use the ILP scheduler, for
174 // 32-bit code use the register pressure specific scheduling.
175 // For Atom, always use ILP scheduling.
176 if (Subtarget->isAtom())
177 setSchedulingPreference(Sched::ILP);
178 else if (Subtarget->is64Bit())
179 setSchedulingPreference(Sched::ILP);
181 setSchedulingPreference(Sched::RegPressure);
182 setStackPointerRegisterToSaveRestore(RegInfo->getStackRegister());
184 // Bypass i32 with i8 on Atom when compiling with O2
185 if (Subtarget->hasSlowDivide() && TM.getOptLevel() >= CodeGenOpt::Default)
186 addBypassSlowDiv(32, 8);
188 if (Subtarget->isTargetWindows() && !Subtarget->isTargetCygMing()) {
189 // Setup Windows compiler runtime calls.
190 setLibcallName(RTLIB::SDIV_I64, "_alldiv");
191 setLibcallName(RTLIB::UDIV_I64, "_aulldiv");
192 setLibcallName(RTLIB::SREM_I64, "_allrem");
193 setLibcallName(RTLIB::UREM_I64, "_aullrem");
194 setLibcallName(RTLIB::MUL_I64, "_allmul");
195 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall);
196 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall);
197 setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::X86_StdCall);
198 setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::X86_StdCall);
199 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::X86_StdCall);
201 // The _ftol2 runtime function has an unusual calling conv, which
202 // is modeled by a special pseudo-instruction.
203 setLibcallName(RTLIB::FPTOUINT_F64_I64, 0);
204 setLibcallName(RTLIB::FPTOUINT_F32_I64, 0);
205 setLibcallName(RTLIB::FPTOUINT_F64_I32, 0);
206 setLibcallName(RTLIB::FPTOUINT_F32_I32, 0);
209 if (Subtarget->isTargetDarwin()) {
210 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
211 setUseUnderscoreSetJmp(false);
212 setUseUnderscoreLongJmp(false);
213 } else if (Subtarget->isTargetMingw()) {
214 // MS runtime is weird: it exports _setjmp, but longjmp!
215 setUseUnderscoreSetJmp(true);
216 setUseUnderscoreLongJmp(false);
218 setUseUnderscoreSetJmp(true);
219 setUseUnderscoreLongJmp(true);
222 // Set up the register classes.
223 addRegisterClass(MVT::i8, &X86::GR8RegClass);
224 addRegisterClass(MVT::i16, &X86::GR16RegClass);
225 addRegisterClass(MVT::i32, &X86::GR32RegClass);
226 if (Subtarget->is64Bit())
227 addRegisterClass(MVT::i64, &X86::GR64RegClass);
229 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
231 // We don't accept any truncstore of integer registers.
232 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
233 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
234 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
235 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
236 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
237 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
239 // SETOEQ and SETUNE require checking two conditions.
240 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
241 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
242 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
243 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
244 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
245 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
247 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
249 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
250 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
251 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
253 if (Subtarget->is64Bit()) {
254 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
255 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
256 } else if (!TM.Options.UseSoftFloat) {
257 // We have an algorithm for SSE2->double, and we turn this into a
258 // 64-bit FILD followed by conditional FADD for other targets.
259 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
260 // We have an algorithm for SSE2, and we turn this into a 64-bit
261 // FILD for other targets.
262 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
265 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
267 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
268 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
270 if (!TM.Options.UseSoftFloat) {
271 // SSE has no i16 to fp conversion, only i32
272 if (X86ScalarSSEf32) {
273 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
274 // f32 and f64 cases are Legal, f80 case is not
275 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
277 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
278 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
281 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
282 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
285 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
286 // are Legal, f80 is custom lowered.
287 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
288 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
290 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
292 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
293 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
295 if (X86ScalarSSEf32) {
296 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
297 // f32 and f64 cases are Legal, f80 case is not
298 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
300 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
301 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
304 // Handle FP_TO_UINT by promoting the destination to a larger signed
306 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
307 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
308 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
310 if (Subtarget->is64Bit()) {
311 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
312 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
313 } else if (!TM.Options.UseSoftFloat) {
314 // Since AVX is a superset of SSE3, only check for SSE here.
315 if (Subtarget->hasSSE1() && !Subtarget->hasSSE3())
316 // Expand FP_TO_UINT into a select.
317 // FIXME: We would like to use a Custom expander here eventually to do
318 // the optimal thing for SSE vs. the default expansion in the legalizer.
319 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
321 // With SSE3 we can use fisttpll to convert to a signed i64; without
322 // SSE, we're stuck with a fistpll.
323 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
326 if (isTargetFTOL()) {
327 // Use the _ftol2 runtime function, which has a pseudo-instruction
328 // to handle its weird calling convention.
329 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Custom);
332 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
333 if (!X86ScalarSSEf64) {
334 setOperationAction(ISD::BITCAST , MVT::f32 , Expand);
335 setOperationAction(ISD::BITCAST , MVT::i32 , Expand);
336 if (Subtarget->is64Bit()) {
337 setOperationAction(ISD::BITCAST , MVT::f64 , Expand);
338 // Without SSE, i64->f64 goes through memory.
339 setOperationAction(ISD::BITCAST , MVT::i64 , Expand);
343 // Scalar integer divide and remainder are lowered to use operations that
344 // produce two results, to match the available instructions. This exposes
345 // the two-result form to trivial CSE, which is able to combine x/y and x%y
346 // into a single instruction.
348 // Scalar integer multiply-high is also lowered to use two-result
349 // operations, to match the available instructions. However, plain multiply
350 // (low) operations are left as Legal, as there are single-result
351 // instructions for this in x86. Using the two-result multiply instructions
352 // when both high and low results are needed must be arranged by dagcombine.
353 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
355 setOperationAction(ISD::MULHS, VT, Expand);
356 setOperationAction(ISD::MULHU, VT, Expand);
357 setOperationAction(ISD::SDIV, VT, Expand);
358 setOperationAction(ISD::UDIV, VT, Expand);
359 setOperationAction(ISD::SREM, VT, Expand);
360 setOperationAction(ISD::UREM, VT, Expand);
362 // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences.
363 setOperationAction(ISD::ADDC, VT, Custom);
364 setOperationAction(ISD::ADDE, VT, Custom);
365 setOperationAction(ISD::SUBC, VT, Custom);
366 setOperationAction(ISD::SUBE, VT, Custom);
369 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
370 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
371 setOperationAction(ISD::BR_CC , MVT::Other, Expand);
372 setOperationAction(ISD::SELECT_CC , MVT::Other, Expand);
373 if (Subtarget->is64Bit())
374 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
375 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
376 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
377 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
378 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
379 setOperationAction(ISD::FREM , MVT::f32 , Expand);
380 setOperationAction(ISD::FREM , MVT::f64 , Expand);
381 setOperationAction(ISD::FREM , MVT::f80 , Expand);
382 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
384 // Promote the i8 variants and force them on up to i32 which has a shorter
386 setOperationAction(ISD::CTTZ , MVT::i8 , Promote);
387 AddPromotedToType (ISD::CTTZ , MVT::i8 , MVT::i32);
388 setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i8 , Promote);
389 AddPromotedToType (ISD::CTTZ_ZERO_UNDEF , MVT::i8 , MVT::i32);
390 if (Subtarget->hasBMI()) {
391 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16 , Expand);
392 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32 , Expand);
393 if (Subtarget->is64Bit())
394 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
396 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
397 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
398 if (Subtarget->is64Bit())
399 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
402 if (Subtarget->hasLZCNT()) {
403 // When promoting the i8 variants, force them to i32 for a shorter
405 setOperationAction(ISD::CTLZ , MVT::i8 , Promote);
406 AddPromotedToType (ISD::CTLZ , MVT::i8 , MVT::i32);
407 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Promote);
408 AddPromotedToType (ISD::CTLZ_ZERO_UNDEF, MVT::i8 , MVT::i32);
409 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Expand);
410 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Expand);
411 if (Subtarget->is64Bit())
412 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
414 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
415 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
416 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
417 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Custom);
418 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Custom);
419 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Custom);
420 if (Subtarget->is64Bit()) {
421 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
422 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom);
426 if (Subtarget->hasPOPCNT()) {
427 setOperationAction(ISD::CTPOP , MVT::i8 , Promote);
429 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
430 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
431 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
432 if (Subtarget->is64Bit())
433 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
436 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
437 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
439 // These should be promoted to a larger select which is supported.
440 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
441 // X86 wants to expand cmov itself.
442 setOperationAction(ISD::SELECT , MVT::i8 , Custom);
443 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
444 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
445 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
446 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
447 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
448 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
449 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
450 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
451 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
452 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
453 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
454 if (Subtarget->is64Bit()) {
455 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
456 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
458 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
459 // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intened to support
460 // SjLj exception handling but a light-weight setjmp/longjmp replacement to
461 // support continuation, user-level threading, and etc.. As a result, no
462 // other SjLj exception interfaces are implemented and please don't build
463 // your own exception handling based on them.
464 // LLVM/Clang supports zero-cost DWARF exception handling.
465 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
466 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
469 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
470 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
471 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
472 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
473 if (Subtarget->is64Bit())
474 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
475 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
476 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom);
477 if (Subtarget->is64Bit()) {
478 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
479 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
480 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
481 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
482 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom);
484 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
485 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
486 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
487 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
488 if (Subtarget->is64Bit()) {
489 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
490 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
491 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
494 if (Subtarget->hasSSE1())
495 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
497 setOperationAction(ISD::MEMBARRIER , MVT::Other, Custom);
498 setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom);
500 // On X86 and X86-64, atomic operations are lowered to locked instructions.
501 // Locked instructions, in turn, have implicit fence semantics (all memory
502 // operations are flushed before issuing the locked instruction, and they
503 // are not buffered), so we can fold away the common pattern of
504 // fence-atomic-fence.
505 setShouldFoldAtomicFences(true);
507 // Expand certain atomics
508 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
510 setOperationAction(ISD::ATOMIC_CMP_SWAP, VT, Custom);
511 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom);
512 setOperationAction(ISD::ATOMIC_STORE, VT, Custom);
515 if (!Subtarget->is64Bit()) {
516 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Custom);
517 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i64, Custom);
518 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom);
519 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i64, Custom);
520 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i64, Custom);
521 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i64, Custom);
522 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i64, Custom);
523 setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Custom);
524 setOperationAction(ISD::ATOMIC_LOAD_MAX, MVT::i64, Custom);
525 setOperationAction(ISD::ATOMIC_LOAD_MIN, MVT::i64, Custom);
526 setOperationAction(ISD::ATOMIC_LOAD_UMAX, MVT::i64, Custom);
527 setOperationAction(ISD::ATOMIC_LOAD_UMIN, MVT::i64, Custom);
530 if (Subtarget->hasCmpxchg16b()) {
531 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i128, Custom);
534 // FIXME - use subtarget debug flags
535 if (!Subtarget->isTargetDarwin() &&
536 !Subtarget->isTargetELF() &&
537 !Subtarget->isTargetCygMing()) {
538 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
541 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand);
542 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand);
543 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
544 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
545 if (Subtarget->is64Bit()) {
546 setExceptionPointerRegister(X86::RAX);
547 setExceptionSelectorRegister(X86::RDX);
549 setExceptionPointerRegister(X86::EAX);
550 setExceptionSelectorRegister(X86::EDX);
552 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
553 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
555 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
556 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
558 setOperationAction(ISD::TRAP, MVT::Other, Legal);
559 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Legal);
561 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
562 setOperationAction(ISD::VASTART , MVT::Other, Custom);
563 setOperationAction(ISD::VAEND , MVT::Other, Expand);
564 if (Subtarget->is64Bit()) {
565 setOperationAction(ISD::VAARG , MVT::Other, Custom);
566 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
568 setOperationAction(ISD::VAARG , MVT::Other, Expand);
569 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
572 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
573 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
575 if (Subtarget->isTargetCOFF() && !Subtarget->isTargetEnvMacho())
576 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ?
577 MVT::i64 : MVT::i32, Custom);
578 else if (TM.Options.EnableSegmentedStacks)
579 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ?
580 MVT::i64 : MVT::i32, Custom);
582 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ?
583 MVT::i64 : MVT::i32, Expand);
585 if (!TM.Options.UseSoftFloat && X86ScalarSSEf64) {
586 // f32 and f64 use SSE.
587 // Set up the FP register classes.
588 addRegisterClass(MVT::f32, &X86::FR32RegClass);
589 addRegisterClass(MVT::f64, &X86::FR64RegClass);
591 // Use ANDPD to simulate FABS.
592 setOperationAction(ISD::FABS , MVT::f64, Custom);
593 setOperationAction(ISD::FABS , MVT::f32, Custom);
595 // Use XORP to simulate FNEG.
596 setOperationAction(ISD::FNEG , MVT::f64, Custom);
597 setOperationAction(ISD::FNEG , MVT::f32, Custom);
599 // Use ANDPD and ORPD to simulate FCOPYSIGN.
600 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
601 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
603 // Lower this to FGETSIGNx86 plus an AND.
604 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom);
605 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom);
607 // We don't support sin/cos/fmod
608 setOperationAction(ISD::FSIN , MVT::f64, Expand);
609 setOperationAction(ISD::FCOS , MVT::f64, Expand);
610 setOperationAction(ISD::FSIN , MVT::f32, Expand);
611 setOperationAction(ISD::FCOS , MVT::f32, Expand);
613 // Expand FP immediates into loads from the stack, except for the special
615 addLegalFPImmediate(APFloat(+0.0)); // xorpd
616 addLegalFPImmediate(APFloat(+0.0f)); // xorps
617 } else if (!TM.Options.UseSoftFloat && X86ScalarSSEf32) {
618 // Use SSE for f32, x87 for f64.
619 // Set up the FP register classes.
620 addRegisterClass(MVT::f32, &X86::FR32RegClass);
621 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
623 // Use ANDPS to simulate FABS.
624 setOperationAction(ISD::FABS , MVT::f32, Custom);
626 // Use XORP to simulate FNEG.
627 setOperationAction(ISD::FNEG , MVT::f32, Custom);
629 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
631 // Use ANDPS and ORPS to simulate FCOPYSIGN.
632 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
633 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
635 // We don't support sin/cos/fmod
636 setOperationAction(ISD::FSIN , MVT::f32, Expand);
637 setOperationAction(ISD::FCOS , MVT::f32, Expand);
639 // Special cases we handle for FP constants.
640 addLegalFPImmediate(APFloat(+0.0f)); // xorps
641 addLegalFPImmediate(APFloat(+0.0)); // FLD0
642 addLegalFPImmediate(APFloat(+1.0)); // FLD1
643 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
644 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
646 if (!TM.Options.UnsafeFPMath) {
647 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
648 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
650 } else if (!TM.Options.UseSoftFloat) {
651 // f32 and f64 in x87.
652 // Set up the FP register classes.
653 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
654 addRegisterClass(MVT::f32, &X86::RFP32RegClass);
656 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
657 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
658 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
659 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
661 if (!TM.Options.UnsafeFPMath) {
662 setOperationAction(ISD::FSIN , MVT::f32 , Expand);
663 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
664 setOperationAction(ISD::FCOS , MVT::f32 , Expand);
665 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
667 addLegalFPImmediate(APFloat(+0.0)); // FLD0
668 addLegalFPImmediate(APFloat(+1.0)); // FLD1
669 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
670 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
671 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
672 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
673 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
674 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
677 // We don't support FMA.
678 setOperationAction(ISD::FMA, MVT::f64, Expand);
679 setOperationAction(ISD::FMA, MVT::f32, Expand);
681 // Long double always uses X87.
682 if (!TM.Options.UseSoftFloat) {
683 addRegisterClass(MVT::f80, &X86::RFP80RegClass);
684 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
685 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
687 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended);
688 addLegalFPImmediate(TmpFlt); // FLD0
690 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
693 APFloat TmpFlt2(+1.0);
694 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
696 addLegalFPImmediate(TmpFlt2); // FLD1
697 TmpFlt2.changeSign();
698 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
701 if (!TM.Options.UnsafeFPMath) {
702 setOperationAction(ISD::FSIN , MVT::f80 , Expand);
703 setOperationAction(ISD::FCOS , MVT::f80 , Expand);
706 setOperationAction(ISD::FFLOOR, MVT::f80, Expand);
707 setOperationAction(ISD::FCEIL, MVT::f80, Expand);
708 setOperationAction(ISD::FTRUNC, MVT::f80, Expand);
709 setOperationAction(ISD::FRINT, MVT::f80, Expand);
710 setOperationAction(ISD::FNEARBYINT, MVT::f80, Expand);
711 setOperationAction(ISD::FMA, MVT::f80, Expand);
714 // Always use a library call for pow.
715 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
716 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
717 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
719 setOperationAction(ISD::FLOG, MVT::f80, Expand);
720 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
721 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
722 setOperationAction(ISD::FEXP, MVT::f80, Expand);
723 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
725 // First set operation action for all vector types to either promote
726 // (for widening) or expand (for scalarization). Then we will selectively
727 // turn on ones that can be effectively codegen'd.
728 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
729 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
730 MVT VT = (MVT::SimpleValueType)i;
731 setOperationAction(ISD::ADD , VT, Expand);
732 setOperationAction(ISD::SUB , VT, Expand);
733 setOperationAction(ISD::FADD, VT, Expand);
734 setOperationAction(ISD::FNEG, VT, Expand);
735 setOperationAction(ISD::FSUB, VT, Expand);
736 setOperationAction(ISD::MUL , VT, Expand);
737 setOperationAction(ISD::FMUL, VT, Expand);
738 setOperationAction(ISD::SDIV, VT, Expand);
739 setOperationAction(ISD::UDIV, VT, Expand);
740 setOperationAction(ISD::FDIV, VT, Expand);
741 setOperationAction(ISD::SREM, VT, Expand);
742 setOperationAction(ISD::UREM, VT, Expand);
743 setOperationAction(ISD::LOAD, VT, Expand);
744 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);
745 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT,Expand);
746 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
747 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT,Expand);
748 setOperationAction(ISD::INSERT_SUBVECTOR, VT,Expand);
749 setOperationAction(ISD::FABS, VT, Expand);
750 setOperationAction(ISD::FSIN, VT, Expand);
751 setOperationAction(ISD::FCOS, VT, Expand);
752 setOperationAction(ISD::FREM, VT, Expand);
753 setOperationAction(ISD::FMA, VT, Expand);
754 setOperationAction(ISD::FPOWI, VT, Expand);
755 setOperationAction(ISD::FSQRT, VT, Expand);
756 setOperationAction(ISD::FCOPYSIGN, VT, Expand);
757 setOperationAction(ISD::FFLOOR, VT, Expand);
758 setOperationAction(ISD::FCEIL, VT, Expand);
759 setOperationAction(ISD::FTRUNC, VT, Expand);
760 setOperationAction(ISD::FRINT, VT, Expand);
761 setOperationAction(ISD::FNEARBYINT, VT, Expand);
762 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
763 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
764 setOperationAction(ISD::SDIVREM, VT, Expand);
765 setOperationAction(ISD::UDIVREM, VT, Expand);
766 setOperationAction(ISD::FPOW, VT, Expand);
767 setOperationAction(ISD::CTPOP, VT, Expand);
768 setOperationAction(ISD::CTTZ, VT, Expand);
769 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
770 setOperationAction(ISD::CTLZ, VT, Expand);
771 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
772 setOperationAction(ISD::SHL, VT, Expand);
773 setOperationAction(ISD::SRA, VT, Expand);
774 setOperationAction(ISD::SRL, VT, Expand);
775 setOperationAction(ISD::ROTL, VT, Expand);
776 setOperationAction(ISD::ROTR, VT, Expand);
777 setOperationAction(ISD::BSWAP, VT, Expand);
778 setOperationAction(ISD::SETCC, VT, Expand);
779 setOperationAction(ISD::FLOG, VT, Expand);
780 setOperationAction(ISD::FLOG2, VT, Expand);
781 setOperationAction(ISD::FLOG10, VT, Expand);
782 setOperationAction(ISD::FEXP, VT, Expand);
783 setOperationAction(ISD::FEXP2, VT, Expand);
784 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
785 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
786 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
787 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
788 setOperationAction(ISD::SIGN_EXTEND_INREG, VT,Expand);
789 setOperationAction(ISD::TRUNCATE, VT, Expand);
790 setOperationAction(ISD::SIGN_EXTEND, VT, Expand);
791 setOperationAction(ISD::ZERO_EXTEND, VT, Expand);
792 setOperationAction(ISD::ANY_EXTEND, VT, Expand);
793 setOperationAction(ISD::VSELECT, VT, Expand);
794 for (int InnerVT = MVT::FIRST_VECTOR_VALUETYPE;
795 InnerVT <= MVT::LAST_VECTOR_VALUETYPE; ++InnerVT)
796 setTruncStoreAction(VT,
797 (MVT::SimpleValueType)InnerVT, Expand);
798 setLoadExtAction(ISD::SEXTLOAD, VT, Expand);
799 setLoadExtAction(ISD::ZEXTLOAD, VT, Expand);
800 setLoadExtAction(ISD::EXTLOAD, VT, Expand);
803 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
804 // with -msoft-float, disable use of MMX as well.
805 if (!TM.Options.UseSoftFloat && Subtarget->hasMMX()) {
806 addRegisterClass(MVT::x86mmx, &X86::VR64RegClass);
807 // No operations on x86mmx supported, everything uses intrinsics.
810 // MMX-sized vectors (other than x86mmx) are expected to be expanded
811 // into smaller operations.
812 setOperationAction(ISD::MULHS, MVT::v8i8, Expand);
813 setOperationAction(ISD::MULHS, MVT::v4i16, Expand);
814 setOperationAction(ISD::MULHS, MVT::v2i32, Expand);
815 setOperationAction(ISD::MULHS, MVT::v1i64, Expand);
816 setOperationAction(ISD::AND, MVT::v8i8, Expand);
817 setOperationAction(ISD::AND, MVT::v4i16, Expand);
818 setOperationAction(ISD::AND, MVT::v2i32, Expand);
819 setOperationAction(ISD::AND, MVT::v1i64, Expand);
820 setOperationAction(ISD::OR, MVT::v8i8, Expand);
821 setOperationAction(ISD::OR, MVT::v4i16, Expand);
822 setOperationAction(ISD::OR, MVT::v2i32, Expand);
823 setOperationAction(ISD::OR, MVT::v1i64, Expand);
824 setOperationAction(ISD::XOR, MVT::v8i8, Expand);
825 setOperationAction(ISD::XOR, MVT::v4i16, Expand);
826 setOperationAction(ISD::XOR, MVT::v2i32, Expand);
827 setOperationAction(ISD::XOR, MVT::v1i64, Expand);
828 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Expand);
829 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Expand);
830 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i32, Expand);
831 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Expand);
832 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand);
833 setOperationAction(ISD::SELECT, MVT::v8i8, Expand);
834 setOperationAction(ISD::SELECT, MVT::v4i16, Expand);
835 setOperationAction(ISD::SELECT, MVT::v2i32, Expand);
836 setOperationAction(ISD::SELECT, MVT::v1i64, Expand);
837 setOperationAction(ISD::BITCAST, MVT::v8i8, Expand);
838 setOperationAction(ISD::BITCAST, MVT::v4i16, Expand);
839 setOperationAction(ISD::BITCAST, MVT::v2i32, Expand);
840 setOperationAction(ISD::BITCAST, MVT::v1i64, Expand);
842 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE1()) {
843 addRegisterClass(MVT::v4f32, &X86::VR128RegClass);
845 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
846 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
847 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
848 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
849 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
850 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
851 setOperationAction(ISD::FABS, MVT::v4f32, Custom);
852 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
853 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
854 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
855 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
856 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
859 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE2()) {
860 addRegisterClass(MVT::v2f64, &X86::VR128RegClass);
862 // FIXME: Unfortunately -soft-float and -no-implicit-float means XMM
863 // registers cannot be used even for integer operations.
864 addRegisterClass(MVT::v16i8, &X86::VR128RegClass);
865 addRegisterClass(MVT::v8i16, &X86::VR128RegClass);
866 addRegisterClass(MVT::v4i32, &X86::VR128RegClass);
867 addRegisterClass(MVT::v2i64, &X86::VR128RegClass);
869 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
870 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
871 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
872 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
873 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
874 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
875 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
876 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
877 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
878 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
879 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
880 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
881 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
882 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
883 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
884 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
885 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
886 setOperationAction(ISD::FABS, MVT::v2f64, Custom);
888 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
889 setOperationAction(ISD::SETCC, MVT::v16i8, Custom);
890 setOperationAction(ISD::SETCC, MVT::v8i16, Custom);
891 setOperationAction(ISD::SETCC, MVT::v4i32, Custom);
893 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
894 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
895 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
896 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
897 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
899 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
900 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
901 MVT VT = (MVT::SimpleValueType)i;
902 // Do not attempt to custom lower non-power-of-2 vectors
903 if (!isPowerOf2_32(VT.getVectorNumElements()))
905 // Do not attempt to custom lower non-128-bit vectors
906 if (!VT.is128BitVector())
908 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
909 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
910 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
913 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
914 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
915 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
916 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
917 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
918 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
920 if (Subtarget->is64Bit()) {
921 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
922 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
925 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
926 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
927 MVT VT = (MVT::SimpleValueType)i;
929 // Do not attempt to promote non-128-bit vectors
930 if (!VT.is128BitVector())
933 setOperationAction(ISD::AND, VT, Promote);
934 AddPromotedToType (ISD::AND, VT, MVT::v2i64);
935 setOperationAction(ISD::OR, VT, Promote);
936 AddPromotedToType (ISD::OR, VT, MVT::v2i64);
937 setOperationAction(ISD::XOR, VT, Promote);
938 AddPromotedToType (ISD::XOR, VT, MVT::v2i64);
939 setOperationAction(ISD::LOAD, VT, Promote);
940 AddPromotedToType (ISD::LOAD, VT, MVT::v2i64);
941 setOperationAction(ISD::SELECT, VT, Promote);
942 AddPromotedToType (ISD::SELECT, VT, MVT::v2i64);
945 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
947 // Custom lower v2i64 and v2f64 selects.
948 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
949 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
950 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
951 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
953 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
954 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
956 setOperationAction(ISD::UINT_TO_FP, MVT::v4i8, Custom);
957 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);
958 // As there is no 64-bit GPR available, we need build a special custom
959 // sequence to convert from v2i32 to v2f32.
960 if (!Subtarget->is64Bit())
961 setOperationAction(ISD::UINT_TO_FP, MVT::v2f32, Custom);
963 setOperationAction(ISD::FP_EXTEND, MVT::v2f32, Custom);
964 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Custom);
966 setLoadExtAction(ISD::EXTLOAD, MVT::v2f32, Legal);
969 if (Subtarget->hasSSE41()) {
970 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
971 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
972 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
973 setOperationAction(ISD::FRINT, MVT::f32, Legal);
974 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
975 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
976 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
977 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
978 setOperationAction(ISD::FRINT, MVT::f64, Legal);
979 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
981 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal);
982 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal);
983 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal);
984 setOperationAction(ISD::FRINT, MVT::v4f32, Legal);
985 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal);
986 setOperationAction(ISD::FFLOOR, MVT::v2f64, Legal);
987 setOperationAction(ISD::FCEIL, MVT::v2f64, Legal);
988 setOperationAction(ISD::FTRUNC, MVT::v2f64, Legal);
989 setOperationAction(ISD::FRINT, MVT::v2f64, Legal);
990 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Legal);
992 // FIXME: Do we need to handle scalar-to-vector here?
993 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
995 setOperationAction(ISD::VSELECT, MVT::v2f64, Legal);
996 setOperationAction(ISD::VSELECT, MVT::v2i64, Legal);
997 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
998 setOperationAction(ISD::VSELECT, MVT::v4i32, Legal);
999 setOperationAction(ISD::VSELECT, MVT::v4f32, Legal);
1001 // i8 and i16 vectors are custom , because the source register and source
1002 // source memory operand types are not the same width. f32 vectors are
1003 // custom since the immediate controlling the insert encodes additional
1005 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
1006 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
1007 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
1008 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
1010 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
1011 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
1012 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
1013 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
1015 // FIXME: these should be Legal but thats only for the case where
1016 // the index is constant. For now custom expand to deal with that.
1017 if (Subtarget->is64Bit()) {
1018 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
1019 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
1023 if (Subtarget->hasSSE2()) {
1024 setOperationAction(ISD::SRL, MVT::v8i16, Custom);
1025 setOperationAction(ISD::SRL, MVT::v16i8, Custom);
1027 setOperationAction(ISD::SHL, MVT::v8i16, Custom);
1028 setOperationAction(ISD::SHL, MVT::v16i8, Custom);
1030 setOperationAction(ISD::SRA, MVT::v8i16, Custom);
1031 setOperationAction(ISD::SRA, MVT::v16i8, Custom);
1033 if (Subtarget->hasInt256()) {
1034 setOperationAction(ISD::SRL, MVT::v2i64, Legal);
1035 setOperationAction(ISD::SRL, MVT::v4i32, Legal);
1037 setOperationAction(ISD::SHL, MVT::v2i64, Legal);
1038 setOperationAction(ISD::SHL, MVT::v4i32, Legal);
1040 setOperationAction(ISD::SRA, MVT::v4i32, Legal);
1042 setOperationAction(ISD::SRL, MVT::v2i64, Custom);
1043 setOperationAction(ISD::SRL, MVT::v4i32, Custom);
1045 setOperationAction(ISD::SHL, MVT::v2i64, Custom);
1046 setOperationAction(ISD::SHL, MVT::v4i32, Custom);
1048 setOperationAction(ISD::SRA, MVT::v4i32, Custom);
1050 setOperationAction(ISD::SDIV, MVT::v8i16, Custom);
1051 setOperationAction(ISD::SDIV, MVT::v4i32, Custom);
1054 if (!TM.Options.UseSoftFloat && Subtarget->hasFp256()) {
1055 addRegisterClass(MVT::v32i8, &X86::VR256RegClass);
1056 addRegisterClass(MVT::v16i16, &X86::VR256RegClass);
1057 addRegisterClass(MVT::v8i32, &X86::VR256RegClass);
1058 addRegisterClass(MVT::v8f32, &X86::VR256RegClass);
1059 addRegisterClass(MVT::v4i64, &X86::VR256RegClass);
1060 addRegisterClass(MVT::v4f64, &X86::VR256RegClass);
1062 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
1063 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
1064 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
1066 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
1067 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
1068 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
1069 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
1070 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
1071 setOperationAction(ISD::FFLOOR, MVT::v8f32, Legal);
1072 setOperationAction(ISD::FCEIL, MVT::v8f32, Legal);
1073 setOperationAction(ISD::FTRUNC, MVT::v8f32, Legal);
1074 setOperationAction(ISD::FRINT, MVT::v8f32, Legal);
1075 setOperationAction(ISD::FNEARBYINT, MVT::v8f32, Legal);
1076 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
1077 setOperationAction(ISD::FABS, MVT::v8f32, Custom);
1079 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
1080 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
1081 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
1082 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
1083 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
1084 setOperationAction(ISD::FFLOOR, MVT::v4f64, Legal);
1085 setOperationAction(ISD::FCEIL, MVT::v4f64, Legal);
1086 setOperationAction(ISD::FTRUNC, MVT::v4f64, Legal);
1087 setOperationAction(ISD::FRINT, MVT::v4f64, Legal);
1088 setOperationAction(ISD::FNEARBYINT, MVT::v4f64, Legal);
1089 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
1090 setOperationAction(ISD::FABS, MVT::v4f64, Custom);
1092 setOperationAction(ISD::TRUNCATE, MVT::v8i16, Custom);
1093 setOperationAction(ISD::TRUNCATE, MVT::v4i32, Custom);
1095 setOperationAction(ISD::FP_TO_SINT, MVT::v8i16, Custom);
1097 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
1098 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
1099 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal);
1101 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i32, Custom);
1102 setOperationAction(ISD::UINT_TO_FP, MVT::v8i8, Custom);
1103 setOperationAction(ISD::UINT_TO_FP, MVT::v8i16, Custom);
1105 setLoadExtAction(ISD::EXTLOAD, MVT::v4f32, Legal);
1107 setOperationAction(ISD::SRL, MVT::v16i16, Custom);
1108 setOperationAction(ISD::SRL, MVT::v32i8, Custom);
1110 setOperationAction(ISD::SHL, MVT::v16i16, Custom);
1111 setOperationAction(ISD::SHL, MVT::v32i8, Custom);
1113 setOperationAction(ISD::SRA, MVT::v16i16, Custom);
1114 setOperationAction(ISD::SRA, MVT::v32i8, Custom);
1116 setOperationAction(ISD::SDIV, MVT::v16i16, Custom);
1118 setOperationAction(ISD::SETCC, MVT::v32i8, Custom);
1119 setOperationAction(ISD::SETCC, MVT::v16i16, Custom);
1120 setOperationAction(ISD::SETCC, MVT::v8i32, Custom);
1121 setOperationAction(ISD::SETCC, MVT::v4i64, Custom);
1123 setOperationAction(ISD::SELECT, MVT::v4f64, Custom);
1124 setOperationAction(ISD::SELECT, MVT::v4i64, Custom);
1125 setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
1127 setOperationAction(ISD::VSELECT, MVT::v4f64, Legal);
1128 setOperationAction(ISD::VSELECT, MVT::v4i64, Legal);
1129 setOperationAction(ISD::VSELECT, MVT::v8i32, Legal);
1130 setOperationAction(ISD::VSELECT, MVT::v8f32, Legal);
1132 setOperationAction(ISD::SIGN_EXTEND, MVT::v4i64, Custom);
1133 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i32, Custom);
1134 setOperationAction(ISD::ZERO_EXTEND, MVT::v4i64, Custom);
1135 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i32, Custom);
1136 setOperationAction(ISD::ANY_EXTEND, MVT::v4i64, Custom);
1137 setOperationAction(ISD::ANY_EXTEND, MVT::v8i32, Custom);
1139 if (Subtarget->hasFMA() || Subtarget->hasFMA4()) {
1140 setOperationAction(ISD::FMA, MVT::v8f32, Legal);
1141 setOperationAction(ISD::FMA, MVT::v4f64, Legal);
1142 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
1143 setOperationAction(ISD::FMA, MVT::v2f64, Legal);
1144 setOperationAction(ISD::FMA, MVT::f32, Legal);
1145 setOperationAction(ISD::FMA, MVT::f64, Legal);
1148 if (Subtarget->hasInt256()) {
1149 setOperationAction(ISD::ADD, MVT::v4i64, Legal);
1150 setOperationAction(ISD::ADD, MVT::v8i32, Legal);
1151 setOperationAction(ISD::ADD, MVT::v16i16, Legal);
1152 setOperationAction(ISD::ADD, MVT::v32i8, Legal);
1154 setOperationAction(ISD::SUB, MVT::v4i64, Legal);
1155 setOperationAction(ISD::SUB, MVT::v8i32, Legal);
1156 setOperationAction(ISD::SUB, MVT::v16i16, Legal);
1157 setOperationAction(ISD::SUB, MVT::v32i8, Legal);
1159 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1160 setOperationAction(ISD::MUL, MVT::v8i32, Legal);
1161 setOperationAction(ISD::MUL, MVT::v16i16, Legal);
1162 // Don't lower v32i8 because there is no 128-bit byte mul
1164 setOperationAction(ISD::VSELECT, MVT::v32i8, Legal);
1166 setOperationAction(ISD::SRL, MVT::v4i64, Legal);
1167 setOperationAction(ISD::SRL, MVT::v8i32, Legal);
1169 setOperationAction(ISD::SHL, MVT::v4i64, Legal);
1170 setOperationAction(ISD::SHL, MVT::v8i32, Legal);
1172 setOperationAction(ISD::SRA, MVT::v8i32, Legal);
1174 setOperationAction(ISD::SDIV, MVT::v8i32, Custom);
1176 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
1177 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
1178 setOperationAction(ISD::ADD, MVT::v16i16, Custom);
1179 setOperationAction(ISD::ADD, MVT::v32i8, Custom);
1181 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
1182 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
1183 setOperationAction(ISD::SUB, MVT::v16i16, Custom);
1184 setOperationAction(ISD::SUB, MVT::v32i8, Custom);
1186 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1187 setOperationAction(ISD::MUL, MVT::v8i32, Custom);
1188 setOperationAction(ISD::MUL, MVT::v16i16, Custom);
1189 // Don't lower v32i8 because there is no 128-bit byte mul
1191 setOperationAction(ISD::SRL, MVT::v4i64, Custom);
1192 setOperationAction(ISD::SRL, MVT::v8i32, Custom);
1194 setOperationAction(ISD::SHL, MVT::v4i64, Custom);
1195 setOperationAction(ISD::SHL, MVT::v8i32, Custom);
1197 setOperationAction(ISD::SRA, MVT::v8i32, Custom);
1200 // Custom lower several nodes for 256-bit types.
1201 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
1202 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
1203 MVT VT = (MVT::SimpleValueType)i;
1205 // Extract subvector is special because the value type
1206 // (result) is 128-bit but the source is 256-bit wide.
1207 if (VT.is128BitVector())
1208 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1210 // Do not attempt to custom lower other non-256-bit vectors
1211 if (!VT.is256BitVector())
1214 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1215 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1216 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1217 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1218 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1219 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1220 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom);
1223 // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64.
1224 for (int i = MVT::v32i8; i != MVT::v4i64; ++i) {
1225 MVT VT = (MVT::SimpleValueType)i;
1227 // Do not attempt to promote non-256-bit vectors
1228 if (!VT.is256BitVector())
1231 setOperationAction(ISD::AND, VT, Promote);
1232 AddPromotedToType (ISD::AND, VT, MVT::v4i64);
1233 setOperationAction(ISD::OR, VT, Promote);
1234 AddPromotedToType (ISD::OR, VT, MVT::v4i64);
1235 setOperationAction(ISD::XOR, VT, Promote);
1236 AddPromotedToType (ISD::XOR, VT, MVT::v4i64);
1237 setOperationAction(ISD::LOAD, VT, Promote);
1238 AddPromotedToType (ISD::LOAD, VT, MVT::v4i64);
1239 setOperationAction(ISD::SELECT, VT, Promote);
1240 AddPromotedToType (ISD::SELECT, VT, MVT::v4i64);
1244 // SIGN_EXTEND_INREGs are evaluated by the extend type. Handle the expansion
1245 // of this type with custom code.
1246 for (int VT = MVT::FIRST_VECTOR_VALUETYPE;
1247 VT != MVT::LAST_VECTOR_VALUETYPE; VT++) {
1248 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,
1252 // We want to custom lower some of our intrinsics.
1253 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
1254 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
1256 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't
1257 // handle type legalization for these operations here.
1259 // FIXME: We really should do custom legalization for addition and
1260 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better
1261 // than generic legalization for 64-bit multiplication-with-overflow, though.
1262 for (unsigned i = 0, e = 3+Subtarget->is64Bit(); i != e; ++i) {
1263 // Add/Sub/Mul with overflow operations are custom lowered.
1265 setOperationAction(ISD::SADDO, VT, Custom);
1266 setOperationAction(ISD::UADDO, VT, Custom);
1267 setOperationAction(ISD::SSUBO, VT, Custom);
1268 setOperationAction(ISD::USUBO, VT, Custom);
1269 setOperationAction(ISD::SMULO, VT, Custom);
1270 setOperationAction(ISD::UMULO, VT, Custom);
1273 // There are no 8-bit 3-address imul/mul instructions
1274 setOperationAction(ISD::SMULO, MVT::i8, Expand);
1275 setOperationAction(ISD::UMULO, MVT::i8, Expand);
1277 if (!Subtarget->is64Bit()) {
1278 // These libcalls are not available in 32-bit.
1279 setLibcallName(RTLIB::SHL_I128, 0);
1280 setLibcallName(RTLIB::SRL_I128, 0);
1281 setLibcallName(RTLIB::SRA_I128, 0);
1284 // We have target-specific dag combine patterns for the following nodes:
1285 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
1286 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
1287 setTargetDAGCombine(ISD::VSELECT);
1288 setTargetDAGCombine(ISD::SELECT);
1289 setTargetDAGCombine(ISD::SHL);
1290 setTargetDAGCombine(ISD::SRA);
1291 setTargetDAGCombine(ISD::SRL);
1292 setTargetDAGCombine(ISD::OR);
1293 setTargetDAGCombine(ISD::AND);
1294 setTargetDAGCombine(ISD::ADD);
1295 setTargetDAGCombine(ISD::FADD);
1296 setTargetDAGCombine(ISD::FSUB);
1297 setTargetDAGCombine(ISD::FMA);
1298 setTargetDAGCombine(ISD::SUB);
1299 setTargetDAGCombine(ISD::LOAD);
1300 setTargetDAGCombine(ISD::STORE);
1301 setTargetDAGCombine(ISD::ZERO_EXTEND);
1302 setTargetDAGCombine(ISD::ANY_EXTEND);
1303 setTargetDAGCombine(ISD::SIGN_EXTEND);
1304 setTargetDAGCombine(ISD::TRUNCATE);
1305 setTargetDAGCombine(ISD::SINT_TO_FP);
1306 setTargetDAGCombine(ISD::SETCC);
1307 if (Subtarget->is64Bit())
1308 setTargetDAGCombine(ISD::MUL);
1309 setTargetDAGCombine(ISD::XOR);
1311 computeRegisterProperties();
1313 // On Darwin, -Os means optimize for size without hurting performance,
1314 // do not reduce the limit.
1315 maxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
1316 maxStoresPerMemsetOptSize = Subtarget->isTargetDarwin() ? 16 : 8;
1317 maxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores
1318 maxStoresPerMemcpyOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1319 maxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores
1320 maxStoresPerMemmoveOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1321 setPrefLoopAlignment(4); // 2^4 bytes.
1322 benefitFromCodePlacementOpt = true;
1324 // Predictable cmov don't hurt on atom because it's in-order.
1325 predictableSelectIsExpensive = !Subtarget->isAtom();
1327 setPrefFunctionAlignment(4); // 2^4 bytes.
1330 EVT X86TargetLowering::getSetCCResultType(EVT VT) const {
1331 if (!VT.isVector()) return MVT::i8;
1332 return VT.changeVectorElementTypeToInteger();
1335 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
1336 /// the desired ByVal argument alignment.
1337 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) {
1340 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1341 if (VTy->getBitWidth() == 128)
1343 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1344 unsigned EltAlign = 0;
1345 getMaxByValAlign(ATy->getElementType(), EltAlign);
1346 if (EltAlign > MaxAlign)
1347 MaxAlign = EltAlign;
1348 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
1349 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
1350 unsigned EltAlign = 0;
1351 getMaxByValAlign(STy->getElementType(i), EltAlign);
1352 if (EltAlign > MaxAlign)
1353 MaxAlign = EltAlign;
1360 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1361 /// function arguments in the caller parameter area. For X86, aggregates
1362 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
1363 /// are at 4-byte boundaries.
1364 unsigned X86TargetLowering::getByValTypeAlignment(Type *Ty) const {
1365 if (Subtarget->is64Bit()) {
1366 // Max of 8 and alignment of type.
1367 unsigned TyAlign = TD->getABITypeAlignment(Ty);
1374 if (Subtarget->hasSSE1())
1375 getMaxByValAlign(Ty, Align);
1379 /// getOptimalMemOpType - Returns the target specific optimal type for load
1380 /// and store operations as a result of memset, memcpy, and memmove
1381 /// lowering. If DstAlign is zero that means it's safe to destination
1382 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
1383 /// means there isn't a need to check it against alignment requirement,
1384 /// probably because the source does not need to be loaded. If 'IsMemset' is
1385 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
1386 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
1387 /// source is constant so it does not need to be loaded.
1388 /// It returns EVT::Other if the type should be determined using generic
1389 /// target-independent logic.
1391 X86TargetLowering::getOptimalMemOpType(uint64_t Size,
1392 unsigned DstAlign, unsigned SrcAlign,
1393 bool IsMemset, bool ZeroMemset,
1395 MachineFunction &MF) const {
1396 const Function *F = MF.getFunction();
1397 if ((!IsMemset || ZeroMemset) &&
1398 !F->getAttributes().hasAttribute(AttributeSet::FunctionIndex,
1399 Attribute::NoImplicitFloat)) {
1401 (Subtarget->isUnalignedMemAccessFast() ||
1402 ((DstAlign == 0 || DstAlign >= 16) &&
1403 (SrcAlign == 0 || SrcAlign >= 16)))) {
1405 if (Subtarget->hasInt256())
1407 if (Subtarget->hasFp256())
1410 if (Subtarget->hasSSE2())
1412 if (Subtarget->hasSSE1())
1414 } else if (!MemcpyStrSrc && Size >= 8 &&
1415 !Subtarget->is64Bit() &&
1416 Subtarget->hasSSE2()) {
1417 // Do not use f64 to lower memcpy if source is string constant. It's
1418 // better to use i32 to avoid the loads.
1422 if (Subtarget->is64Bit() && Size >= 8)
1427 bool X86TargetLowering::isSafeMemOpType(MVT VT) const {
1429 return X86ScalarSSEf32;
1430 else if (VT == MVT::f64)
1431 return X86ScalarSSEf64;
1436 X86TargetLowering::allowsUnalignedMemoryAccesses(EVT VT, bool *Fast) const {
1438 *Fast = Subtarget->isUnalignedMemAccessFast();
1442 /// getJumpTableEncoding - Return the entry encoding for a jump table in the
1443 /// current function. The returned value is a member of the
1444 /// MachineJumpTableInfo::JTEntryKind enum.
1445 unsigned X86TargetLowering::getJumpTableEncoding() const {
1446 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
1448 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1449 Subtarget->isPICStyleGOT())
1450 return MachineJumpTableInfo::EK_Custom32;
1452 // Otherwise, use the normal jump table encoding heuristics.
1453 return TargetLowering::getJumpTableEncoding();
1457 X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
1458 const MachineBasicBlock *MBB,
1459 unsigned uid,MCContext &Ctx) const{
1460 assert(getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1461 Subtarget->isPICStyleGOT());
1462 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
1464 return MCSymbolRefExpr::Create(MBB->getSymbol(),
1465 MCSymbolRefExpr::VK_GOTOFF, Ctx);
1468 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
1470 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
1471 SelectionDAG &DAG) const {
1472 if (!Subtarget->is64Bit())
1473 // This doesn't have DebugLoc associated with it, but is not really the
1474 // same as a Register.
1475 return DAG.getNode(X86ISD::GlobalBaseReg, DebugLoc(), getPointerTy());
1479 /// getPICJumpTableRelocBaseExpr - This returns the relocation base for the
1480 /// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an
1482 const MCExpr *X86TargetLowering::
1483 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
1484 MCContext &Ctx) const {
1485 // X86-64 uses RIP relative addressing based on the jump table label.
1486 if (Subtarget->isPICStyleRIPRel())
1487 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
1489 // Otherwise, the reference is relative to the PIC base.
1490 return MCSymbolRefExpr::Create(MF->getPICBaseSymbol(), Ctx);
1493 // FIXME: Why this routine is here? Move to RegInfo!
1494 std::pair<const TargetRegisterClass*, uint8_t>
1495 X86TargetLowering::findRepresentativeClass(MVT VT) const{
1496 const TargetRegisterClass *RRC = 0;
1498 switch (VT.SimpleTy) {
1500 return TargetLowering::findRepresentativeClass(VT);
1501 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
1502 RRC = Subtarget->is64Bit() ?
1503 (const TargetRegisterClass*)&X86::GR64RegClass :
1504 (const TargetRegisterClass*)&X86::GR32RegClass;
1507 RRC = &X86::VR64RegClass;
1509 case MVT::f32: case MVT::f64:
1510 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
1511 case MVT::v4f32: case MVT::v2f64:
1512 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32:
1514 RRC = &X86::VR128RegClass;
1517 return std::make_pair(RRC, Cost);
1520 bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace,
1521 unsigned &Offset) const {
1522 if (!Subtarget->isTargetLinux())
1525 if (Subtarget->is64Bit()) {
1526 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs:
1528 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
1540 //===----------------------------------------------------------------------===//
1541 // Return Value Calling Convention Implementation
1542 //===----------------------------------------------------------------------===//
1544 #include "X86GenCallingConv.inc"
1547 X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv,
1548 MachineFunction &MF, bool isVarArg,
1549 const SmallVectorImpl<ISD::OutputArg> &Outs,
1550 LLVMContext &Context) const {
1551 SmallVector<CCValAssign, 16> RVLocs;
1552 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
1554 return CCInfo.CheckReturn(Outs, RetCC_X86);
1558 X86TargetLowering::LowerReturn(SDValue Chain,
1559 CallingConv::ID CallConv, bool isVarArg,
1560 const SmallVectorImpl<ISD::OutputArg> &Outs,
1561 const SmallVectorImpl<SDValue> &OutVals,
1562 DebugLoc dl, SelectionDAG &DAG) const {
1563 MachineFunction &MF = DAG.getMachineFunction();
1564 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1566 SmallVector<CCValAssign, 16> RVLocs;
1567 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
1568 RVLocs, *DAG.getContext());
1569 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
1571 // Add the regs to the liveout set for the function.
1572 MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
1573 for (unsigned i = 0; i != RVLocs.size(); ++i)
1574 if (RVLocs[i].isRegLoc() && !MRI.isLiveOut(RVLocs[i].getLocReg()))
1575 MRI.addLiveOut(RVLocs[i].getLocReg());
1579 SmallVector<SDValue, 6> RetOps;
1580 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
1581 // Operand #1 = Bytes To Pop
1582 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(),
1585 // Copy the result values into the output registers.
1586 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1587 CCValAssign &VA = RVLocs[i];
1588 assert(VA.isRegLoc() && "Can only return in registers!");
1589 SDValue ValToCopy = OutVals[i];
1590 EVT ValVT = ValToCopy.getValueType();
1592 // Promote values to the appropriate types
1593 if (VA.getLocInfo() == CCValAssign::SExt)
1594 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy);
1595 else if (VA.getLocInfo() == CCValAssign::ZExt)
1596 ValToCopy = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ValToCopy);
1597 else if (VA.getLocInfo() == CCValAssign::AExt)
1598 ValToCopy = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ValToCopy);
1599 else if (VA.getLocInfo() == CCValAssign::BCvt)
1600 ValToCopy = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), ValToCopy);
1602 // If this is x86-64, and we disabled SSE, we can't return FP values,
1603 // or SSE or MMX vectors.
1604 if ((ValVT == MVT::f32 || ValVT == MVT::f64 ||
1605 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) &&
1606 (Subtarget->is64Bit() && !Subtarget->hasSSE1())) {
1607 report_fatal_error("SSE register return with SSE disabled");
1609 // Likewise we can't return F64 values with SSE1 only. gcc does so, but
1610 // llvm-gcc has never done it right and no one has noticed, so this
1611 // should be OK for now.
1612 if (ValVT == MVT::f64 &&
1613 (Subtarget->is64Bit() && !Subtarget->hasSSE2()))
1614 report_fatal_error("SSE2 register return with SSE2 disabled");
1616 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
1617 // the RET instruction and handled by the FP Stackifier.
1618 if (VA.getLocReg() == X86::ST0 ||
1619 VA.getLocReg() == X86::ST1) {
1620 // If this is a copy from an xmm register to ST(0), use an FPExtend to
1621 // change the value to the FP stack register class.
1622 if (isScalarFPTypeInSSEReg(VA.getValVT()))
1623 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
1624 RetOps.push_back(ValToCopy);
1625 // Don't emit a copytoreg.
1629 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
1630 // which is returned in RAX / RDX.
1631 if (Subtarget->is64Bit()) {
1632 if (ValVT == MVT::x86mmx) {
1633 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
1634 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ValToCopy);
1635 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
1637 // If we don't have SSE2 available, convert to v4f32 so the generated
1638 // register is legal.
1639 if (!Subtarget->hasSSE2())
1640 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32,ValToCopy);
1645 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
1646 Flag = Chain.getValue(1);
1649 // The x86-64 ABI for returning structs by value requires that we copy
1650 // the sret argument into %rax for the return. We saved the argument into
1651 // a virtual register in the entry block, so now we copy the value out
1653 if (Subtarget->is64Bit() &&
1654 DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
1655 MachineFunction &MF = DAG.getMachineFunction();
1656 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1657 unsigned Reg = FuncInfo->getSRetReturnReg();
1659 "SRetReturnReg should have been set in LowerFormalArguments().");
1660 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
1662 Chain = DAG.getCopyToReg(Chain, dl, X86::RAX, Val, Flag);
1663 Flag = Chain.getValue(1);
1665 // RAX now acts like a return value.
1666 MRI.addLiveOut(X86::RAX);
1669 RetOps[0] = Chain; // Update chain.
1671 // Add the flag if we have it.
1673 RetOps.push_back(Flag);
1675 return DAG.getNode(X86ISD::RET_FLAG, dl,
1676 MVT::Other, &RetOps[0], RetOps.size());
1679 bool X86TargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
1680 if (N->getNumValues() != 1)
1682 if (!N->hasNUsesOfValue(1, 0))
1685 SDValue TCChain = Chain;
1686 SDNode *Copy = *N->use_begin();
1687 if (Copy->getOpcode() == ISD::CopyToReg) {
1688 // If the copy has a glue operand, we conservatively assume it isn't safe to
1689 // perform a tail call.
1690 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
1692 TCChain = Copy->getOperand(0);
1693 } else if (Copy->getOpcode() != ISD::FP_EXTEND)
1696 bool HasRet = false;
1697 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
1699 if (UI->getOpcode() != X86ISD::RET_FLAG)
1712 X86TargetLowering::getTypeForExtArgOrReturn(MVT VT,
1713 ISD::NodeType ExtendKind) const {
1715 // TODO: Is this also valid on 32-bit?
1716 if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND)
1717 ReturnMVT = MVT::i8;
1719 ReturnMVT = MVT::i32;
1721 MVT MinVT = getRegisterType(ReturnMVT);
1722 return VT.bitsLT(MinVT) ? MinVT : VT;
1725 /// LowerCallResult - Lower the result values of a call into the
1726 /// appropriate copies out of appropriate physical registers.
1729 X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
1730 CallingConv::ID CallConv, bool isVarArg,
1731 const SmallVectorImpl<ISD::InputArg> &Ins,
1732 DebugLoc dl, SelectionDAG &DAG,
1733 SmallVectorImpl<SDValue> &InVals) const {
1735 // Assign locations to each value returned by this call.
1736 SmallVector<CCValAssign, 16> RVLocs;
1737 bool Is64Bit = Subtarget->is64Bit();
1738 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
1739 getTargetMachine(), RVLocs, *DAG.getContext());
1740 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
1742 // Copy all of the result registers out of their specified physreg.
1743 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
1744 CCValAssign &VA = RVLocs[i];
1745 EVT CopyVT = VA.getValVT();
1747 // If this is x86-64, and we disabled SSE, we can't return FP values
1748 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
1749 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) {
1750 report_fatal_error("SSE register return with SSE disabled");
1755 // If this is a call to a function that returns an fp value on the floating
1756 // point stack, we must guarantee the value is popped from the stack, so
1757 // a CopyFromReg is not good enough - the copy instruction may be eliminated
1758 // if the return value is not used. We use the FpPOP_RETVAL instruction
1760 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1) {
1761 // If we prefer to use the value in xmm registers, copy it out as f80 and
1762 // use a truncate to move it from fp stack reg to xmm reg.
1763 if (isScalarFPTypeInSSEReg(VA.getValVT())) CopyVT = MVT::f80;
1764 SDValue Ops[] = { Chain, InFlag };
1765 Chain = SDValue(DAG.getMachineNode(X86::FpPOP_RETVAL, dl, CopyVT,
1766 MVT::Other, MVT::Glue, Ops, 2), 1);
1767 Val = Chain.getValue(0);
1769 // Round the f80 to the right size, which also moves it to the appropriate
1771 if (CopyVT != VA.getValVT())
1772 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
1773 // This truncation won't change the value.
1774 DAG.getIntPtrConstant(1));
1776 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
1777 CopyVT, InFlag).getValue(1);
1778 Val = Chain.getValue(0);
1780 InFlag = Chain.getValue(2);
1781 InVals.push_back(Val);
1787 //===----------------------------------------------------------------------===//
1788 // C & StdCall & Fast Calling Convention implementation
1789 //===----------------------------------------------------------------------===//
1790 // StdCall calling convention seems to be standard for many Windows' API
1791 // routines and around. It differs from C calling convention just a little:
1792 // callee should clean up the stack, not caller. Symbols should be also
1793 // decorated in some fancy way :) It doesn't support any vector arguments.
1794 // For info on fast calling convention see Fast Calling Convention (tail call)
1795 // implementation LowerX86_32FastCCCallTo.
1797 /// CallIsStructReturn - Determines whether a call uses struct return
1799 enum StructReturnType {
1804 static StructReturnType
1805 callIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
1807 return NotStructReturn;
1809 const ISD::ArgFlagsTy &Flags = Outs[0].Flags;
1810 if (!Flags.isSRet())
1811 return NotStructReturn;
1812 if (Flags.isInReg())
1813 return RegStructReturn;
1814 return StackStructReturn;
1817 /// ArgsAreStructReturn - Determines whether a function uses struct
1818 /// return semantics.
1819 static StructReturnType
1820 argsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
1822 return NotStructReturn;
1824 const ISD::ArgFlagsTy &Flags = Ins[0].Flags;
1825 if (!Flags.isSRet())
1826 return NotStructReturn;
1827 if (Flags.isInReg())
1828 return RegStructReturn;
1829 return StackStructReturn;
1832 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
1833 /// by "Src" to address "Dst" with size and alignment information specified by
1834 /// the specific parameter attribute. The copy will be passed as a byval
1835 /// function parameter.
1837 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
1838 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
1840 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
1842 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
1843 /*isVolatile*/false, /*AlwaysInline=*/true,
1844 MachinePointerInfo(), MachinePointerInfo());
1847 /// IsTailCallConvention - Return true if the calling convention is one that
1848 /// supports tail call optimization.
1849 static bool IsTailCallConvention(CallingConv::ID CC) {
1850 return (CC == CallingConv::Fast || CC == CallingConv::GHC ||
1851 CC == CallingConv::HiPE);
1854 bool X86TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
1855 if (!CI->isTailCall() || getTargetMachine().Options.DisableTailCalls)
1859 CallingConv::ID CalleeCC = CS.getCallingConv();
1860 if (!IsTailCallConvention(CalleeCC) && CalleeCC != CallingConv::C)
1866 /// FuncIsMadeTailCallSafe - Return true if the function is being made into
1867 /// a tailcall target by changing its ABI.
1868 static bool FuncIsMadeTailCallSafe(CallingConv::ID CC,
1869 bool GuaranteedTailCallOpt) {
1870 return GuaranteedTailCallOpt && IsTailCallConvention(CC);
1874 X86TargetLowering::LowerMemArgument(SDValue Chain,
1875 CallingConv::ID CallConv,
1876 const SmallVectorImpl<ISD::InputArg> &Ins,
1877 DebugLoc dl, SelectionDAG &DAG,
1878 const CCValAssign &VA,
1879 MachineFrameInfo *MFI,
1881 // Create the nodes corresponding to a load from this parameter slot.
1882 ISD::ArgFlagsTy Flags = Ins[i].Flags;
1883 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(CallConv,
1884 getTargetMachine().Options.GuaranteedTailCallOpt);
1885 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
1888 // If value is passed by pointer we have address passed instead of the value
1890 if (VA.getLocInfo() == CCValAssign::Indirect)
1891 ValVT = VA.getLocVT();
1893 ValVT = VA.getValVT();
1895 // FIXME: For now, all byval parameter objects are marked mutable. This can be
1896 // changed with more analysis.
1897 // In case of tail call optimization mark all arguments mutable. Since they
1898 // could be overwritten by lowering of arguments in case of a tail call.
1899 if (Flags.isByVal()) {
1900 unsigned Bytes = Flags.getByValSize();
1901 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects.
1902 int FI = MFI->CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable);
1903 return DAG.getFrameIndex(FI, getPointerTy());
1905 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
1906 VA.getLocMemOffset(), isImmutable);
1907 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
1908 return DAG.getLoad(ValVT, dl, Chain, FIN,
1909 MachinePointerInfo::getFixedStack(FI),
1910 false, false, false, 0);
1915 X86TargetLowering::LowerFormalArguments(SDValue Chain,
1916 CallingConv::ID CallConv,
1918 const SmallVectorImpl<ISD::InputArg> &Ins,
1921 SmallVectorImpl<SDValue> &InVals)
1923 MachineFunction &MF = DAG.getMachineFunction();
1924 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1926 const Function* Fn = MF.getFunction();
1927 if (Fn->hasExternalLinkage() &&
1928 Subtarget->isTargetCygMing() &&
1929 Fn->getName() == "main")
1930 FuncInfo->setForceFramePointer(true);
1932 MachineFrameInfo *MFI = MF.getFrameInfo();
1933 bool Is64Bit = Subtarget->is64Bit();
1934 bool IsWindows = Subtarget->isTargetWindows();
1935 bool IsWin64 = Subtarget->isTargetWin64();
1937 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
1938 "Var args not supported with calling convention fastcc, ghc or hipe");
1940 // Assign locations to all of the incoming arguments.
1941 SmallVector<CCValAssign, 16> ArgLocs;
1942 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
1943 ArgLocs, *DAG.getContext());
1945 // Allocate shadow area for Win64
1947 CCInfo.AllocateStack(32, 8);
1950 CCInfo.AnalyzeFormalArguments(Ins, CC_X86);
1952 unsigned LastVal = ~0U;
1954 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1955 CCValAssign &VA = ArgLocs[i];
1956 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
1958 assert(VA.getValNo() != LastVal &&
1959 "Don't support value assigned to multiple locs yet");
1961 LastVal = VA.getValNo();
1963 if (VA.isRegLoc()) {
1964 EVT RegVT = VA.getLocVT();
1965 const TargetRegisterClass *RC;
1966 if (RegVT == MVT::i32)
1967 RC = &X86::GR32RegClass;
1968 else if (Is64Bit && RegVT == MVT::i64)
1969 RC = &X86::GR64RegClass;
1970 else if (RegVT == MVT::f32)
1971 RC = &X86::FR32RegClass;
1972 else if (RegVT == MVT::f64)
1973 RC = &X86::FR64RegClass;
1974 else if (RegVT.is256BitVector())
1975 RC = &X86::VR256RegClass;
1976 else if (RegVT.is128BitVector())
1977 RC = &X86::VR128RegClass;
1978 else if (RegVT == MVT::x86mmx)
1979 RC = &X86::VR64RegClass;
1981 llvm_unreachable("Unknown argument type!");
1983 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
1984 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
1986 // If this is an 8 or 16-bit value, it is really passed promoted to 32
1987 // bits. Insert an assert[sz]ext to capture this, then truncate to the
1989 if (VA.getLocInfo() == CCValAssign::SExt)
1990 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
1991 DAG.getValueType(VA.getValVT()));
1992 else if (VA.getLocInfo() == CCValAssign::ZExt)
1993 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
1994 DAG.getValueType(VA.getValVT()));
1995 else if (VA.getLocInfo() == CCValAssign::BCvt)
1996 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
1998 if (VA.isExtInLoc()) {
1999 // Handle MMX values passed in XMM regs.
2000 if (RegVT.isVector())
2001 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(), ArgValue);
2003 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
2006 assert(VA.isMemLoc());
2007 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
2010 // If value is passed via pointer - do a load.
2011 if (VA.getLocInfo() == CCValAssign::Indirect)
2012 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue,
2013 MachinePointerInfo(), false, false, false, 0);
2015 InVals.push_back(ArgValue);
2018 // The x86-64 ABI for returning structs by value requires that we copy
2019 // the sret argument into %rax for the return. Save the argument into
2020 // a virtual register so that we can access it from the return points.
2021 if (Is64Bit && MF.getFunction()->hasStructRetAttr()) {
2022 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2023 unsigned Reg = FuncInfo->getSRetReturnReg();
2025 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64));
2026 FuncInfo->setSRetReturnReg(Reg);
2028 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]);
2029 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
2032 unsigned StackSize = CCInfo.getNextStackOffset();
2033 // Align stack specially for tail calls.
2034 if (FuncIsMadeTailCallSafe(CallConv,
2035 MF.getTarget().Options.GuaranteedTailCallOpt))
2036 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
2038 // If the function takes variable number of arguments, make a frame index for
2039 // the start of the first vararg value... for expansion of llvm.va_start.
2041 if (Is64Bit || (CallConv != CallingConv::X86_FastCall &&
2042 CallConv != CallingConv::X86_ThisCall)) {
2043 FuncInfo->setVarArgsFrameIndex(MFI->CreateFixedObject(1, StackSize,true));
2046 unsigned TotalNumIntRegs = 0, TotalNumXMMRegs = 0;
2048 // FIXME: We should really autogenerate these arrays
2049 static const uint16_t GPR64ArgRegsWin64[] = {
2050 X86::RCX, X86::RDX, X86::R8, X86::R9
2052 static const uint16_t GPR64ArgRegs64Bit[] = {
2053 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
2055 static const uint16_t XMMArgRegs64Bit[] = {
2056 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2057 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2059 const uint16_t *GPR64ArgRegs;
2060 unsigned NumXMMRegs = 0;
2063 // The XMM registers which might contain var arg parameters are shadowed
2064 // in their paired GPR. So we only need to save the GPR to their home
2066 TotalNumIntRegs = 4;
2067 GPR64ArgRegs = GPR64ArgRegsWin64;
2069 TotalNumIntRegs = 6; TotalNumXMMRegs = 8;
2070 GPR64ArgRegs = GPR64ArgRegs64Bit;
2072 NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs64Bit,
2075 unsigned NumIntRegs = CCInfo.getFirstUnallocated(GPR64ArgRegs,
2078 bool NoImplicitFloatOps = Fn->getAttributes().
2079 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoImplicitFloat);
2080 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) &&
2081 "SSE register cannot be used when SSE is disabled!");
2082 assert(!(NumXMMRegs && MF.getTarget().Options.UseSoftFloat &&
2083 NoImplicitFloatOps) &&
2084 "SSE register cannot be used when SSE is disabled!");
2085 if (MF.getTarget().Options.UseSoftFloat || NoImplicitFloatOps ||
2086 !Subtarget->hasSSE1())
2087 // Kernel mode asks for SSE to be disabled, so don't push them
2089 TotalNumXMMRegs = 0;
2092 const TargetFrameLowering &TFI = *getTargetMachine().getFrameLowering();
2093 // Get to the caller-allocated home save location. Add 8 to account
2094 // for the return address.
2095 int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
2096 FuncInfo->setRegSaveFrameIndex(
2097 MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false));
2098 // Fixup to set vararg frame on shadow area (4 x i64).
2100 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex());
2102 // For X86-64, if there are vararg parameters that are passed via
2103 // registers, then we must store them to their spots on the stack so
2104 // they may be loaded by deferencing the result of va_next.
2105 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8);
2106 FuncInfo->setVarArgsFPOffset(TotalNumIntRegs * 8 + NumXMMRegs * 16);
2107 FuncInfo->setRegSaveFrameIndex(
2108 MFI->CreateStackObject(TotalNumIntRegs * 8 + TotalNumXMMRegs * 16, 16,
2112 // Store the integer parameter registers.
2113 SmallVector<SDValue, 8> MemOps;
2114 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
2116 unsigned Offset = FuncInfo->getVarArgsGPOffset();
2117 for (; NumIntRegs != TotalNumIntRegs; ++NumIntRegs) {
2118 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN,
2119 DAG.getIntPtrConstant(Offset));
2120 unsigned VReg = MF.addLiveIn(GPR64ArgRegs[NumIntRegs],
2121 &X86::GR64RegClass);
2122 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
2124 DAG.getStore(Val.getValue(1), dl, Val, FIN,
2125 MachinePointerInfo::getFixedStack(
2126 FuncInfo->getRegSaveFrameIndex(), Offset),
2128 MemOps.push_back(Store);
2132 if (TotalNumXMMRegs != 0 && NumXMMRegs != TotalNumXMMRegs) {
2133 // Now store the XMM (fp + vector) parameter registers.
2134 SmallVector<SDValue, 11> SaveXMMOps;
2135 SaveXMMOps.push_back(Chain);
2137 unsigned AL = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
2138 SDValue ALVal = DAG.getCopyFromReg(DAG.getEntryNode(), dl, AL, MVT::i8);
2139 SaveXMMOps.push_back(ALVal);
2141 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2142 FuncInfo->getRegSaveFrameIndex()));
2143 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2144 FuncInfo->getVarArgsFPOffset()));
2146 for (; NumXMMRegs != TotalNumXMMRegs; ++NumXMMRegs) {
2147 unsigned VReg = MF.addLiveIn(XMMArgRegs64Bit[NumXMMRegs],
2148 &X86::VR128RegClass);
2149 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::v4f32);
2150 SaveXMMOps.push_back(Val);
2152 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
2154 &SaveXMMOps[0], SaveXMMOps.size()));
2157 if (!MemOps.empty())
2158 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2159 &MemOps[0], MemOps.size());
2163 // Some CCs need callee pop.
2164 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2165 MF.getTarget().Options.GuaranteedTailCallOpt)) {
2166 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything.
2168 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing.
2169 // If this is an sret function, the return should pop the hidden pointer.
2170 if (!Is64Bit && !IsTailCallConvention(CallConv) && !IsWindows &&
2171 argsAreStructReturn(Ins) == StackStructReturn)
2172 FuncInfo->setBytesToPopOnReturn(4);
2176 // RegSaveFrameIndex is X86-64 only.
2177 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
2178 if (CallConv == CallingConv::X86_FastCall ||
2179 CallConv == CallingConv::X86_ThisCall)
2180 // fastcc functions can't have varargs.
2181 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA);
2184 FuncInfo->setArgumentStackSize(StackSize);
2190 X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
2191 SDValue StackPtr, SDValue Arg,
2192 DebugLoc dl, SelectionDAG &DAG,
2193 const CCValAssign &VA,
2194 ISD::ArgFlagsTy Flags) const {
2195 unsigned LocMemOffset = VA.getLocMemOffset();
2196 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
2197 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
2198 if (Flags.isByVal())
2199 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
2201 return DAG.getStore(Chain, dl, Arg, PtrOff,
2202 MachinePointerInfo::getStack(LocMemOffset),
2206 /// EmitTailCallLoadRetAddr - Emit a load of return address if tail call
2207 /// optimization is performed and it is required.
2209 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
2210 SDValue &OutRetAddr, SDValue Chain,
2211 bool IsTailCall, bool Is64Bit,
2212 int FPDiff, DebugLoc dl) const {
2213 // Adjust the Return address stack slot.
2214 EVT VT = getPointerTy();
2215 OutRetAddr = getReturnAddressFrameIndex(DAG);
2217 // Load the "old" Return address.
2218 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(),
2219 false, false, false, 0);
2220 return SDValue(OutRetAddr.getNode(), 1);
2223 /// EmitTailCallStoreRetAddr - Emit a store of the return address if tail call
2224 /// optimization is performed and it is required (FPDiff!=0).
2226 EmitTailCallStoreRetAddr(SelectionDAG & DAG, MachineFunction &MF,
2227 SDValue Chain, SDValue RetAddrFrIdx, EVT PtrVT,
2228 unsigned SlotSize, int FPDiff, DebugLoc dl) {
2229 // Store the return address to the appropriate stack slot.
2230 if (!FPDiff) return Chain;
2231 // Calculate the new stack slot for the return address.
2232 int NewReturnAddrFI =
2233 MF.getFrameInfo()->CreateFixedObject(SlotSize, FPDiff-SlotSize, false);
2234 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, PtrVT);
2235 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
2236 MachinePointerInfo::getFixedStack(NewReturnAddrFI),
2242 X86TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
2243 SmallVectorImpl<SDValue> &InVals) const {
2244 SelectionDAG &DAG = CLI.DAG;
2245 DebugLoc &dl = CLI.DL;
2246 SmallVector<ISD::OutputArg, 32> &Outs = CLI.Outs;
2247 SmallVector<SDValue, 32> &OutVals = CLI.OutVals;
2248 SmallVector<ISD::InputArg, 32> &Ins = CLI.Ins;
2249 SDValue Chain = CLI.Chain;
2250 SDValue Callee = CLI.Callee;
2251 CallingConv::ID CallConv = CLI.CallConv;
2252 bool &isTailCall = CLI.IsTailCall;
2253 bool isVarArg = CLI.IsVarArg;
2255 MachineFunction &MF = DAG.getMachineFunction();
2256 bool Is64Bit = Subtarget->is64Bit();
2257 bool IsWin64 = Subtarget->isTargetWin64();
2258 bool IsWindows = Subtarget->isTargetWindows();
2259 StructReturnType SR = callIsStructReturn(Outs);
2260 bool IsSibcall = false;
2262 if (MF.getTarget().Options.DisableTailCalls)
2266 // Check if it's really possible to do a tail call.
2267 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
2268 isVarArg, SR != NotStructReturn,
2269 MF.getFunction()->hasStructRetAttr(), CLI.RetTy,
2270 Outs, OutVals, Ins, DAG);
2272 // Sibcalls are automatically detected tailcalls which do not require
2274 if (!MF.getTarget().Options.GuaranteedTailCallOpt && isTailCall)
2281 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2282 "Var args not supported with calling convention fastcc, ghc or hipe");
2284 // Analyze operands of the call, assigning locations to each operand.
2285 SmallVector<CCValAssign, 16> ArgLocs;
2286 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
2287 ArgLocs, *DAG.getContext());
2289 // Allocate shadow area for Win64
2291 CCInfo.AllocateStack(32, 8);
2294 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2296 // Get a count of how many bytes are to be pushed on the stack.
2297 unsigned NumBytes = CCInfo.getNextStackOffset();
2299 // This is a sibcall. The memory operands are available in caller's
2300 // own caller's stack.
2302 else if (getTargetMachine().Options.GuaranteedTailCallOpt &&
2303 IsTailCallConvention(CallConv))
2304 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
2307 if (isTailCall && !IsSibcall) {
2308 // Lower arguments at fp - stackoffset + fpdiff.
2309 X86MachineFunctionInfo *X86Info = MF.getInfo<X86MachineFunctionInfo>();
2310 unsigned NumBytesCallerPushed = X86Info->getBytesToPopOnReturn();
2312 FPDiff = NumBytesCallerPushed - NumBytes;
2314 // Set the delta of movement of the returnaddr stackslot.
2315 // But only set if delta is greater than previous delta.
2316 if (FPDiff < X86Info->getTCReturnAddrDelta())
2317 X86Info->setTCReturnAddrDelta(FPDiff);
2321 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
2323 SDValue RetAddrFrIdx;
2324 // Load return address for tail calls.
2325 if (isTailCall && FPDiff)
2326 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall,
2327 Is64Bit, FPDiff, dl);
2329 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
2330 SmallVector<SDValue, 8> MemOpChains;
2333 // Walk the register/memloc assignments, inserting copies/loads. In the case
2334 // of tail call optimization arguments are handle later.
2335 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2336 CCValAssign &VA = ArgLocs[i];
2337 EVT RegVT = VA.getLocVT();
2338 SDValue Arg = OutVals[i];
2339 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2340 bool isByVal = Flags.isByVal();
2342 // Promote the value if needed.
2343 switch (VA.getLocInfo()) {
2344 default: llvm_unreachable("Unknown loc info!");
2345 case CCValAssign::Full: break;
2346 case CCValAssign::SExt:
2347 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
2349 case CCValAssign::ZExt:
2350 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
2352 case CCValAssign::AExt:
2353 if (RegVT.is128BitVector()) {
2354 // Special case: passing MMX values in XMM registers.
2355 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg);
2356 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
2357 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
2359 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
2361 case CCValAssign::BCvt:
2362 Arg = DAG.getNode(ISD::BITCAST, dl, RegVT, Arg);
2364 case CCValAssign::Indirect: {
2365 // Store the argument.
2366 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
2367 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
2368 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot,
2369 MachinePointerInfo::getFixedStack(FI),
2376 if (VA.isRegLoc()) {
2377 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2378 if (isVarArg && IsWin64) {
2379 // Win64 ABI requires argument XMM reg to be copied to the corresponding
2380 // shadow reg if callee is a varargs function.
2381 unsigned ShadowReg = 0;
2382 switch (VA.getLocReg()) {
2383 case X86::XMM0: ShadowReg = X86::RCX; break;
2384 case X86::XMM1: ShadowReg = X86::RDX; break;
2385 case X86::XMM2: ShadowReg = X86::R8; break;
2386 case X86::XMM3: ShadowReg = X86::R9; break;
2389 RegsToPass.push_back(std::make_pair(ShadowReg, Arg));
2391 } else if (!IsSibcall && (!isTailCall || isByVal)) {
2392 assert(VA.isMemLoc());
2393 if (StackPtr.getNode() == 0)
2394 StackPtr = DAG.getCopyFromReg(Chain, dl, RegInfo->getStackRegister(),
2396 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
2397 dl, DAG, VA, Flags));
2401 if (!MemOpChains.empty())
2402 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2403 &MemOpChains[0], MemOpChains.size());
2405 if (Subtarget->isPICStyleGOT()) {
2406 // ELF / PIC requires GOT in the EBX register before function calls via PLT
2409 RegsToPass.push_back(std::make_pair(unsigned(X86::EBX),
2410 DAG.getNode(X86ISD::GlobalBaseReg, DebugLoc(), getPointerTy())));
2412 // If we are tail calling and generating PIC/GOT style code load the
2413 // address of the callee into ECX. The value in ecx is used as target of
2414 // the tail jump. This is done to circumvent the ebx/callee-saved problem
2415 // for tail calls on PIC/GOT architectures. Normally we would just put the
2416 // address of GOT into ebx and then call target@PLT. But for tail calls
2417 // ebx would be restored (since ebx is callee saved) before jumping to the
2420 // Note: The actual moving to ECX is done further down.
2421 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
2422 if (G && !G->getGlobal()->hasHiddenVisibility() &&
2423 !G->getGlobal()->hasProtectedVisibility())
2424 Callee = LowerGlobalAddress(Callee, DAG);
2425 else if (isa<ExternalSymbolSDNode>(Callee))
2426 Callee = LowerExternalSymbol(Callee, DAG);
2430 if (Is64Bit && isVarArg && !IsWin64) {
2431 // From AMD64 ABI document:
2432 // For calls that may call functions that use varargs or stdargs
2433 // (prototype-less calls or calls to functions containing ellipsis (...) in
2434 // the declaration) %al is used as hidden argument to specify the number
2435 // of SSE registers used. The contents of %al do not need to match exactly
2436 // the number of registers, but must be an ubound on the number of SSE
2437 // registers used and is in the range 0 - 8 inclusive.
2439 // Count the number of XMM registers allocated.
2440 static const uint16_t XMMArgRegs[] = {
2441 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2442 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2444 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
2445 assert((Subtarget->hasSSE1() || !NumXMMRegs)
2446 && "SSE registers cannot be used when SSE is disabled");
2448 RegsToPass.push_back(std::make_pair(unsigned(X86::AL),
2449 DAG.getConstant(NumXMMRegs, MVT::i8)));
2452 // For tail calls lower the arguments to the 'real' stack slot.
2454 // Force all the incoming stack arguments to be loaded from the stack
2455 // before any new outgoing arguments are stored to the stack, because the
2456 // outgoing stack slots may alias the incoming argument stack slots, and
2457 // the alias isn't otherwise explicit. This is slightly more conservative
2458 // than necessary, because it means that each store effectively depends
2459 // on every argument instead of just those arguments it would clobber.
2460 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
2462 SmallVector<SDValue, 8> MemOpChains2;
2465 if (getTargetMachine().Options.GuaranteedTailCallOpt) {
2466 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2467 CCValAssign &VA = ArgLocs[i];
2470 assert(VA.isMemLoc());
2471 SDValue Arg = OutVals[i];
2472 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2473 // Create frame index.
2474 int32_t Offset = VA.getLocMemOffset()+FPDiff;
2475 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
2476 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
2477 FIN = DAG.getFrameIndex(FI, getPointerTy());
2479 if (Flags.isByVal()) {
2480 // Copy relative to framepointer.
2481 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset());
2482 if (StackPtr.getNode() == 0)
2483 StackPtr = DAG.getCopyFromReg(Chain, dl,
2484 RegInfo->getStackRegister(),
2486 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source);
2488 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
2492 // Store relative to framepointer.
2493 MemOpChains2.push_back(
2494 DAG.getStore(ArgChain, dl, Arg, FIN,
2495 MachinePointerInfo::getFixedStack(FI),
2501 if (!MemOpChains2.empty())
2502 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2503 &MemOpChains2[0], MemOpChains2.size());
2505 // Store the return address to the appropriate stack slot.
2506 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx,
2507 getPointerTy(), RegInfo->getSlotSize(),
2511 // Build a sequence of copy-to-reg nodes chained together with token chain
2512 // and flag operands which copy the outgoing args into registers.
2514 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2515 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
2516 RegsToPass[i].second, InFlag);
2517 InFlag = Chain.getValue(1);
2520 if (getTargetMachine().getCodeModel() == CodeModel::Large) {
2521 assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
2522 // In the 64-bit large code model, we have to make all calls
2523 // through a register, since the call instruction's 32-bit
2524 // pc-relative offset may not be large enough to hold the whole
2526 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2527 // If the callee is a GlobalAddress node (quite common, every direct call
2528 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
2531 // We should use extra load for direct calls to dllimported functions in
2533 const GlobalValue *GV = G->getGlobal();
2534 if (!GV->hasDLLImportLinkage()) {
2535 unsigned char OpFlags = 0;
2536 bool ExtraLoad = false;
2537 unsigned WrapperKind = ISD::DELETED_NODE;
2539 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
2540 // external symbols most go through the PLT in PIC mode. If the symbol
2541 // has hidden or protected visibility, or if it is static or local, then
2542 // we don't need to use the PLT - we can directly call it.
2543 if (Subtarget->isTargetELF() &&
2544 getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
2545 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
2546 OpFlags = X86II::MO_PLT;
2547 } else if (Subtarget->isPICStyleStubAny() &&
2548 (GV->isDeclaration() || GV->isWeakForLinker()) &&
2549 (!Subtarget->getTargetTriple().isMacOSX() ||
2550 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
2551 // PC-relative references to external symbols should go through $stub,
2552 // unless we're building with the leopard linker or later, which
2553 // automatically synthesizes these stubs.
2554 OpFlags = X86II::MO_DARWIN_STUB;
2555 } else if (Subtarget->isPICStyleRIPRel() &&
2556 isa<Function>(GV) &&
2557 cast<Function>(GV)->getAttributes().
2558 hasAttribute(AttributeSet::FunctionIndex,
2559 Attribute::NonLazyBind)) {
2560 // If the function is marked as non-lazy, generate an indirect call
2561 // which loads from the GOT directly. This avoids runtime overhead
2562 // at the cost of eager binding (and one extra byte of encoding).
2563 OpFlags = X86II::MO_GOTPCREL;
2564 WrapperKind = X86ISD::WrapperRIP;
2568 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(),
2569 G->getOffset(), OpFlags);
2571 // Add a wrapper if needed.
2572 if (WrapperKind != ISD::DELETED_NODE)
2573 Callee = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Callee);
2574 // Add extra indirection if needed.
2576 Callee = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Callee,
2577 MachinePointerInfo::getGOT(),
2578 false, false, false, 0);
2580 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
2581 unsigned char OpFlags = 0;
2583 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to
2584 // external symbols should go through the PLT.
2585 if (Subtarget->isTargetELF() &&
2586 getTargetMachine().getRelocationModel() == Reloc::PIC_) {
2587 OpFlags = X86II::MO_PLT;
2588 } else if (Subtarget->isPICStyleStubAny() &&
2589 (!Subtarget->getTargetTriple().isMacOSX() ||
2590 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
2591 // PC-relative references to external symbols should go through $stub,
2592 // unless we're building with the leopard linker or later, which
2593 // automatically synthesizes these stubs.
2594 OpFlags = X86II::MO_DARWIN_STUB;
2597 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(),
2601 // Returns a chain & a flag for retval copy to use.
2602 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
2603 SmallVector<SDValue, 8> Ops;
2605 if (!IsSibcall && isTailCall) {
2606 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
2607 DAG.getIntPtrConstant(0, true), InFlag);
2608 InFlag = Chain.getValue(1);
2611 Ops.push_back(Chain);
2612 Ops.push_back(Callee);
2615 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32));
2617 // Add argument registers to the end of the list so that they are known live
2619 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
2620 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
2621 RegsToPass[i].second.getValueType()));
2623 // Add a register mask operand representing the call-preserved registers.
2624 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
2625 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv);
2626 assert(Mask && "Missing call preserved mask for calling convention");
2627 Ops.push_back(DAG.getRegisterMask(Mask));
2629 if (InFlag.getNode())
2630 Ops.push_back(InFlag);
2634 //// If this is the first return lowered for this function, add the regs
2635 //// to the liveout set for the function.
2636 // This isn't right, although it's probably harmless on x86; liveouts
2637 // should be computed from returns not tail calls. Consider a void
2638 // function making a tail call to a function returning int.
2639 return DAG.getNode(X86ISD::TC_RETURN, dl,
2640 NodeTys, &Ops[0], Ops.size());
2643 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, &Ops[0], Ops.size());
2644 InFlag = Chain.getValue(1);
2646 // Create the CALLSEQ_END node.
2647 unsigned NumBytesForCalleeToPush;
2648 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2649 getTargetMachine().Options.GuaranteedTailCallOpt))
2650 NumBytesForCalleeToPush = NumBytes; // Callee pops everything
2651 else if (!Is64Bit && !IsTailCallConvention(CallConv) && !IsWindows &&
2652 SR == StackStructReturn)
2653 // If this is a call to a struct-return function, the callee
2654 // pops the hidden struct pointer, so we have to push it back.
2655 // This is common for Darwin/X86, Linux & Mingw32 targets.
2656 // For MSVC Win32 targets, the caller pops the hidden struct pointer.
2657 NumBytesForCalleeToPush = 4;
2659 NumBytesForCalleeToPush = 0; // Callee pops nothing.
2661 // Returns a flag for retval copy to use.
2663 Chain = DAG.getCALLSEQ_END(Chain,
2664 DAG.getIntPtrConstant(NumBytes, true),
2665 DAG.getIntPtrConstant(NumBytesForCalleeToPush,
2668 InFlag = Chain.getValue(1);
2671 // Handle result values, copying them out of physregs into vregs that we
2673 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
2674 Ins, dl, DAG, InVals);
2677 //===----------------------------------------------------------------------===//
2678 // Fast Calling Convention (tail call) implementation
2679 //===----------------------------------------------------------------------===//
2681 // Like std call, callee cleans arguments, convention except that ECX is
2682 // reserved for storing the tail called function address. Only 2 registers are
2683 // free for argument passing (inreg). Tail call optimization is performed
2685 // * tailcallopt is enabled
2686 // * caller/callee are fastcc
2687 // On X86_64 architecture with GOT-style position independent code only local
2688 // (within module) calls are supported at the moment.
2689 // To keep the stack aligned according to platform abi the function
2690 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
2691 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
2692 // If a tail called function callee has more arguments than the caller the
2693 // caller needs to make sure that there is room to move the RETADDR to. This is
2694 // achieved by reserving an area the size of the argument delta right after the
2695 // original REtADDR, but before the saved framepointer or the spilled registers
2696 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
2708 /// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned
2709 /// for a 16 byte align requirement.
2711 X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
2712 SelectionDAG& DAG) const {
2713 MachineFunction &MF = DAG.getMachineFunction();
2714 const TargetMachine &TM = MF.getTarget();
2715 const TargetFrameLowering &TFI = *TM.getFrameLowering();
2716 unsigned StackAlignment = TFI.getStackAlignment();
2717 uint64_t AlignMask = StackAlignment - 1;
2718 int64_t Offset = StackSize;
2719 unsigned SlotSize = RegInfo->getSlotSize();
2720 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
2721 // Number smaller than 12 so just add the difference.
2722 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
2724 // Mask out lower bits, add stackalignment once plus the 12 bytes.
2725 Offset = ((~AlignMask) & Offset) + StackAlignment +
2726 (StackAlignment-SlotSize);
2731 /// MatchingStackOffset - Return true if the given stack call argument is
2732 /// already available in the same position (relatively) of the caller's
2733 /// incoming argument stack.
2735 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
2736 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
2737 const X86InstrInfo *TII) {
2738 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
2740 if (Arg.getOpcode() == ISD::CopyFromReg) {
2741 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
2742 if (!TargetRegisterInfo::isVirtualRegister(VR))
2744 MachineInstr *Def = MRI->getVRegDef(VR);
2747 if (!Flags.isByVal()) {
2748 if (!TII->isLoadFromStackSlot(Def, FI))
2751 unsigned Opcode = Def->getOpcode();
2752 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r) &&
2753 Def->getOperand(1).isFI()) {
2754 FI = Def->getOperand(1).getIndex();
2755 Bytes = Flags.getByValSize();
2759 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
2760 if (Flags.isByVal())
2761 // ByVal argument is passed in as a pointer but it's now being
2762 // dereferenced. e.g.
2763 // define @foo(%struct.X* %A) {
2764 // tail call @bar(%struct.X* byval %A)
2767 SDValue Ptr = Ld->getBasePtr();
2768 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
2771 FI = FINode->getIndex();
2772 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) {
2773 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg);
2774 FI = FINode->getIndex();
2775 Bytes = Flags.getByValSize();
2779 assert(FI != INT_MAX);
2780 if (!MFI->isFixedObjectIndex(FI))
2782 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
2785 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
2786 /// for tail call optimization. Targets which want to do tail call
2787 /// optimization should implement this function.
2789 X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
2790 CallingConv::ID CalleeCC,
2792 bool isCalleeStructRet,
2793 bool isCallerStructRet,
2795 const SmallVectorImpl<ISD::OutputArg> &Outs,
2796 const SmallVectorImpl<SDValue> &OutVals,
2797 const SmallVectorImpl<ISD::InputArg> &Ins,
2798 SelectionDAG& DAG) const {
2799 if (!IsTailCallConvention(CalleeCC) &&
2800 CalleeCC != CallingConv::C)
2803 // If -tailcallopt is specified, make fastcc functions tail-callable.
2804 const MachineFunction &MF = DAG.getMachineFunction();
2805 const Function *CallerF = DAG.getMachineFunction().getFunction();
2807 // If the function return type is x86_fp80 and the callee return type is not,
2808 // then the FP_EXTEND of the call result is not a nop. It's not safe to
2809 // perform a tailcall optimization here.
2810 if (CallerF->getReturnType()->isX86_FP80Ty() && !RetTy->isX86_FP80Ty())
2813 CallingConv::ID CallerCC = CallerF->getCallingConv();
2814 bool CCMatch = CallerCC == CalleeCC;
2816 if (getTargetMachine().Options.GuaranteedTailCallOpt) {
2817 if (IsTailCallConvention(CalleeCC) && CCMatch)
2822 // Look for obvious safe cases to perform tail call optimization that do not
2823 // require ABI changes. This is what gcc calls sibcall.
2825 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
2826 // emit a special epilogue.
2827 if (RegInfo->needsStackRealignment(MF))
2830 // Also avoid sibcall optimization if either caller or callee uses struct
2831 // return semantics.
2832 if (isCalleeStructRet || isCallerStructRet)
2835 // An stdcall caller is expected to clean up its arguments; the callee
2836 // isn't going to do that.
2837 if (!CCMatch && CallerCC==CallingConv::X86_StdCall)
2840 // Do not sibcall optimize vararg calls unless all arguments are passed via
2842 if (isVarArg && !Outs.empty()) {
2844 // Optimizing for varargs on Win64 is unlikely to be safe without
2845 // additional testing.
2846 if (Subtarget->isTargetWin64())
2849 SmallVector<CCValAssign, 16> ArgLocs;
2850 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(),
2851 getTargetMachine(), ArgLocs, *DAG.getContext());
2853 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2854 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
2855 if (!ArgLocs[i].isRegLoc())
2859 // If the call result is in ST0 / ST1, it needs to be popped off the x87
2860 // stack. Therefore, if it's not used by the call it is not safe to optimize
2861 // this into a sibcall.
2862 bool Unused = false;
2863 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
2870 SmallVector<CCValAssign, 16> RVLocs;
2871 CCState CCInfo(CalleeCC, false, DAG.getMachineFunction(),
2872 getTargetMachine(), RVLocs, *DAG.getContext());
2873 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
2874 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
2875 CCValAssign &VA = RVLocs[i];
2876 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1)
2881 // If the calling conventions do not match, then we'd better make sure the
2882 // results are returned in the same way as what the caller expects.
2884 SmallVector<CCValAssign, 16> RVLocs1;
2885 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(),
2886 getTargetMachine(), RVLocs1, *DAG.getContext());
2887 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86);
2889 SmallVector<CCValAssign, 16> RVLocs2;
2890 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(),
2891 getTargetMachine(), RVLocs2, *DAG.getContext());
2892 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86);
2894 if (RVLocs1.size() != RVLocs2.size())
2896 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
2897 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
2899 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
2901 if (RVLocs1[i].isRegLoc()) {
2902 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
2905 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
2911 // If the callee takes no arguments then go on to check the results of the
2913 if (!Outs.empty()) {
2914 // Check if stack adjustment is needed. For now, do not do this if any
2915 // argument is passed on the stack.
2916 SmallVector<CCValAssign, 16> ArgLocs;
2917 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(),
2918 getTargetMachine(), ArgLocs, *DAG.getContext());
2920 // Allocate shadow area for Win64
2921 if (Subtarget->isTargetWin64()) {
2922 CCInfo.AllocateStack(32, 8);
2925 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2926 if (CCInfo.getNextStackOffset()) {
2927 MachineFunction &MF = DAG.getMachineFunction();
2928 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn())
2931 // Check if the arguments are already laid out in the right way as
2932 // the caller's fixed stack objects.
2933 MachineFrameInfo *MFI = MF.getFrameInfo();
2934 const MachineRegisterInfo *MRI = &MF.getRegInfo();
2935 const X86InstrInfo *TII =
2936 ((const X86TargetMachine&)getTargetMachine()).getInstrInfo();
2937 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2938 CCValAssign &VA = ArgLocs[i];
2939 SDValue Arg = OutVals[i];
2940 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2941 if (VA.getLocInfo() == CCValAssign::Indirect)
2943 if (!VA.isRegLoc()) {
2944 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
2951 // If the tailcall address may be in a register, then make sure it's
2952 // possible to register allocate for it. In 32-bit, the call address can
2953 // only target EAX, EDX, or ECX since the tail call must be scheduled after
2954 // callee-saved registers are restored. These happen to be the same
2955 // registers used to pass 'inreg' arguments so watch out for those.
2956 if (!Subtarget->is64Bit() &&
2957 !isa<GlobalAddressSDNode>(Callee) &&
2958 !isa<ExternalSymbolSDNode>(Callee)) {
2959 unsigned NumInRegs = 0;
2960 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2961 CCValAssign &VA = ArgLocs[i];
2964 unsigned Reg = VA.getLocReg();
2967 case X86::EAX: case X86::EDX: case X86::ECX:
2968 if (++NumInRegs == 3)
2980 X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
2981 const TargetLibraryInfo *libInfo) const {
2982 return X86::createFastISel(funcInfo, libInfo);
2985 //===----------------------------------------------------------------------===//
2986 // Other Lowering Hooks
2987 //===----------------------------------------------------------------------===//
2989 static bool MayFoldLoad(SDValue Op) {
2990 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode());
2993 static bool MayFoldIntoStore(SDValue Op) {
2994 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin());
2997 static bool isTargetShuffle(unsigned Opcode) {
2999 default: return false;
3000 case X86ISD::PSHUFD:
3001 case X86ISD::PSHUFHW:
3002 case X86ISD::PSHUFLW:
3004 case X86ISD::PALIGN:
3005 case X86ISD::MOVLHPS:
3006 case X86ISD::MOVLHPD:
3007 case X86ISD::MOVHLPS:
3008 case X86ISD::MOVLPS:
3009 case X86ISD::MOVLPD:
3010 case X86ISD::MOVSHDUP:
3011 case X86ISD::MOVSLDUP:
3012 case X86ISD::MOVDDUP:
3015 case X86ISD::UNPCKL:
3016 case X86ISD::UNPCKH:
3017 case X86ISD::VPERMILP:
3018 case X86ISD::VPERM2X128:
3019 case X86ISD::VPERMI:
3024 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
3025 SDValue V1, SelectionDAG &DAG) {
3027 default: llvm_unreachable("Unknown x86 shuffle node");
3028 case X86ISD::MOVSHDUP:
3029 case X86ISD::MOVSLDUP:
3030 case X86ISD::MOVDDUP:
3031 return DAG.getNode(Opc, dl, VT, V1);
3035 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
3036 SDValue V1, unsigned TargetMask,
3037 SelectionDAG &DAG) {
3039 default: llvm_unreachable("Unknown x86 shuffle node");
3040 case X86ISD::PSHUFD:
3041 case X86ISD::PSHUFHW:
3042 case X86ISD::PSHUFLW:
3043 case X86ISD::VPERMILP:
3044 case X86ISD::VPERMI:
3045 return DAG.getNode(Opc, dl, VT, V1, DAG.getConstant(TargetMask, MVT::i8));
3049 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
3050 SDValue V1, SDValue V2, unsigned TargetMask,
3051 SelectionDAG &DAG) {
3053 default: llvm_unreachable("Unknown x86 shuffle node");
3054 case X86ISD::PALIGN:
3056 case X86ISD::VPERM2X128:
3057 return DAG.getNode(Opc, dl, VT, V1, V2,
3058 DAG.getConstant(TargetMask, MVT::i8));
3062 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
3063 SDValue V1, SDValue V2, SelectionDAG &DAG) {
3065 default: llvm_unreachable("Unknown x86 shuffle node");
3066 case X86ISD::MOVLHPS:
3067 case X86ISD::MOVLHPD:
3068 case X86ISD::MOVHLPS:
3069 case X86ISD::MOVLPS:
3070 case X86ISD::MOVLPD:
3073 case X86ISD::UNPCKL:
3074 case X86ISD::UNPCKH:
3075 return DAG.getNode(Opc, dl, VT, V1, V2);
3079 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
3080 MachineFunction &MF = DAG.getMachineFunction();
3081 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
3082 int ReturnAddrIndex = FuncInfo->getRAIndex();
3084 if (ReturnAddrIndex == 0) {
3085 // Set up a frame object for the return address.
3086 unsigned SlotSize = RegInfo->getSlotSize();
3087 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize, -SlotSize,
3089 FuncInfo->setRAIndex(ReturnAddrIndex);
3092 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
3095 bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
3096 bool hasSymbolicDisplacement) {
3097 // Offset should fit into 32 bit immediate field.
3098 if (!isInt<32>(Offset))
3101 // If we don't have a symbolic displacement - we don't have any extra
3103 if (!hasSymbolicDisplacement)
3106 // FIXME: Some tweaks might be needed for medium code model.
3107 if (M != CodeModel::Small && M != CodeModel::Kernel)
3110 // For small code model we assume that latest object is 16MB before end of 31
3111 // bits boundary. We may also accept pretty large negative constants knowing
3112 // that all objects are in the positive half of address space.
3113 if (M == CodeModel::Small && Offset < 16*1024*1024)
3116 // For kernel code model we know that all object resist in the negative half
3117 // of 32bits address space. We may not accept negative offsets, since they may
3118 // be just off and we may accept pretty large positive ones.
3119 if (M == CodeModel::Kernel && Offset > 0)
3125 /// isCalleePop - Determines whether the callee is required to pop its
3126 /// own arguments. Callee pop is necessary to support tail calls.
3127 bool X86::isCalleePop(CallingConv::ID CallingConv,
3128 bool is64Bit, bool IsVarArg, bool TailCallOpt) {
3132 switch (CallingConv) {
3135 case CallingConv::X86_StdCall:
3137 case CallingConv::X86_FastCall:
3139 case CallingConv::X86_ThisCall:
3141 case CallingConv::Fast:
3143 case CallingConv::GHC:
3145 case CallingConv::HiPE:
3150 /// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86
3151 /// specific condition code, returning the condition code and the LHS/RHS of the
3152 /// comparison to make.
3153 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
3154 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
3156 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
3157 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
3158 // X > -1 -> X == 0, jump !sign.
3159 RHS = DAG.getConstant(0, RHS.getValueType());
3160 return X86::COND_NS;
3162 if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
3163 // X < 0 -> X == 0, jump on sign.
3166 if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
3168 RHS = DAG.getConstant(0, RHS.getValueType());
3169 return X86::COND_LE;
3173 switch (SetCCOpcode) {
3174 default: llvm_unreachable("Invalid integer condition!");
3175 case ISD::SETEQ: return X86::COND_E;
3176 case ISD::SETGT: return X86::COND_G;
3177 case ISD::SETGE: return X86::COND_GE;
3178 case ISD::SETLT: return X86::COND_L;
3179 case ISD::SETLE: return X86::COND_LE;
3180 case ISD::SETNE: return X86::COND_NE;
3181 case ISD::SETULT: return X86::COND_B;
3182 case ISD::SETUGT: return X86::COND_A;
3183 case ISD::SETULE: return X86::COND_BE;
3184 case ISD::SETUGE: return X86::COND_AE;
3188 // First determine if it is required or is profitable to flip the operands.
3190 // If LHS is a foldable load, but RHS is not, flip the condition.
3191 if (ISD::isNON_EXTLoad(LHS.getNode()) &&
3192 !ISD::isNON_EXTLoad(RHS.getNode())) {
3193 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
3194 std::swap(LHS, RHS);
3197 switch (SetCCOpcode) {
3203 std::swap(LHS, RHS);
3207 // On a floating point condition, the flags are set as follows:
3209 // 0 | 0 | 0 | X > Y
3210 // 0 | 0 | 1 | X < Y
3211 // 1 | 0 | 0 | X == Y
3212 // 1 | 1 | 1 | unordered
3213 switch (SetCCOpcode) {
3214 default: llvm_unreachable("Condcode should be pre-legalized away");
3216 case ISD::SETEQ: return X86::COND_E;
3217 case ISD::SETOLT: // flipped
3219 case ISD::SETGT: return X86::COND_A;
3220 case ISD::SETOLE: // flipped
3222 case ISD::SETGE: return X86::COND_AE;
3223 case ISD::SETUGT: // flipped
3225 case ISD::SETLT: return X86::COND_B;
3226 case ISD::SETUGE: // flipped
3228 case ISD::SETLE: return X86::COND_BE;
3230 case ISD::SETNE: return X86::COND_NE;
3231 case ISD::SETUO: return X86::COND_P;
3232 case ISD::SETO: return X86::COND_NP;
3234 case ISD::SETUNE: return X86::COND_INVALID;
3238 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
3239 /// code. Current x86 isa includes the following FP cmov instructions:
3240 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
3241 static bool hasFPCMov(unsigned X86CC) {
3257 /// isFPImmLegal - Returns true if the target can instruction select the
3258 /// specified FP immediate natively. If false, the legalizer will
3259 /// materialize the FP immediate as a load from a constant pool.
3260 bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
3261 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
3262 if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
3268 /// isUndefOrInRange - Return true if Val is undef or if its value falls within
3269 /// the specified range (L, H].
3270 static bool isUndefOrInRange(int Val, int Low, int Hi) {
3271 return (Val < 0) || (Val >= Low && Val < Hi);
3274 /// isUndefOrEqual - Val is either less than zero (undef) or equal to the
3275 /// specified value.
3276 static bool isUndefOrEqual(int Val, int CmpVal) {
3277 return (Val < 0 || Val == CmpVal);
3280 /// isSequentialOrUndefInRange - Return true if every element in Mask, beginning
3281 /// from position Pos and ending in Pos+Size, falls within the specified
3282 /// sequential range (L, L+Pos]. or is undef.
3283 static bool isSequentialOrUndefInRange(ArrayRef<int> Mask,
3284 unsigned Pos, unsigned Size, int Low) {
3285 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low)
3286 if (!isUndefOrEqual(Mask[i], Low))
3291 /// isPSHUFDMask - Return true if the node specifies a shuffle of elements that
3292 /// is suitable for input to PSHUFD or PSHUFW. That is, it doesn't reference
3293 /// the second operand.
3294 static bool isPSHUFDMask(ArrayRef<int> Mask, EVT VT) {
3295 if (VT == MVT::v4f32 || VT == MVT::v4i32 )
3296 return (Mask[0] < 4 && Mask[1] < 4 && Mask[2] < 4 && Mask[3] < 4);
3297 if (VT == MVT::v2f64 || VT == MVT::v2i64)
3298 return (Mask[0] < 2 && Mask[1] < 2);
3302 /// isPSHUFHWMask - Return true if the node specifies a shuffle of elements that
3303 /// is suitable for input to PSHUFHW.
3304 static bool isPSHUFHWMask(ArrayRef<int> Mask, EVT VT, bool HasInt256) {
3305 if (VT != MVT::v8i16 && (!HasInt256 || VT != MVT::v16i16))
3308 // Lower quadword copied in order or undef.
3309 if (!isSequentialOrUndefInRange(Mask, 0, 4, 0))
3312 // Upper quadword shuffled.
3313 for (unsigned i = 4; i != 8; ++i)
3314 if (!isUndefOrInRange(Mask[i], 4, 8))
3317 if (VT == MVT::v16i16) {
3318 // Lower quadword copied in order or undef.
3319 if (!isSequentialOrUndefInRange(Mask, 8, 4, 8))
3322 // Upper quadword shuffled.
3323 for (unsigned i = 12; i != 16; ++i)
3324 if (!isUndefOrInRange(Mask[i], 12, 16))
3331 /// isPSHUFLWMask - Return true if the node specifies a shuffle of elements that
3332 /// is suitable for input to PSHUFLW.
3333 static bool isPSHUFLWMask(ArrayRef<int> Mask, EVT VT, bool HasInt256) {
3334 if (VT != MVT::v8i16 && (!HasInt256 || VT != MVT::v16i16))
3337 // Upper quadword copied in order.
3338 if (!isSequentialOrUndefInRange(Mask, 4, 4, 4))
3341 // Lower quadword shuffled.
3342 for (unsigned i = 0; i != 4; ++i)
3343 if (!isUndefOrInRange(Mask[i], 0, 4))
3346 if (VT == MVT::v16i16) {
3347 // Upper quadword copied in order.
3348 if (!isSequentialOrUndefInRange(Mask, 12, 4, 12))
3351 // Lower quadword shuffled.
3352 for (unsigned i = 8; i != 12; ++i)
3353 if (!isUndefOrInRange(Mask[i], 8, 12))
3360 /// isPALIGNRMask - Return true if the node specifies a shuffle of elements that
3361 /// is suitable for input to PALIGNR.
3362 static bool isPALIGNRMask(ArrayRef<int> Mask, EVT VT,
3363 const X86Subtarget *Subtarget) {
3364 if ((VT.is128BitVector() && !Subtarget->hasSSSE3()) ||
3365 (VT.is256BitVector() && !Subtarget->hasInt256()))
3368 unsigned NumElts = VT.getVectorNumElements();
3369 unsigned NumLanes = VT.getSizeInBits()/128;
3370 unsigned NumLaneElts = NumElts/NumLanes;
3372 // Do not handle 64-bit element shuffles with palignr.
3373 if (NumLaneElts == 2)
3376 for (unsigned l = 0; l != NumElts; l+=NumLaneElts) {
3378 for (i = 0; i != NumLaneElts; ++i) {
3383 // Lane is all undef, go to next lane
3384 if (i == NumLaneElts)
3387 int Start = Mask[i+l];
3389 // Make sure its in this lane in one of the sources
3390 if (!isUndefOrInRange(Start, l, l+NumLaneElts) &&
3391 !isUndefOrInRange(Start, l+NumElts, l+NumElts+NumLaneElts))
3394 // If not lane 0, then we must match lane 0
3395 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Start, Mask[i]+l))
3398 // Correct second source to be contiguous with first source
3399 if (Start >= (int)NumElts)
3400 Start -= NumElts - NumLaneElts;
3402 // Make sure we're shifting in the right direction.
3403 if (Start <= (int)(i+l))
3408 // Check the rest of the elements to see if they are consecutive.
3409 for (++i; i != NumLaneElts; ++i) {
3410 int Idx = Mask[i+l];
3412 // Make sure its in this lane
3413 if (!isUndefOrInRange(Idx, l, l+NumLaneElts) &&
3414 !isUndefOrInRange(Idx, l+NumElts, l+NumElts+NumLaneElts))
3417 // If not lane 0, then we must match lane 0
3418 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Idx, Mask[i]+l))
3421 if (Idx >= (int)NumElts)
3422 Idx -= NumElts - NumLaneElts;
3424 if (!isUndefOrEqual(Idx, Start+i))
3433 /// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming
3434 /// the two vector operands have swapped position.
3435 static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask,
3436 unsigned NumElems) {
3437 for (unsigned i = 0; i != NumElems; ++i) {
3441 else if (idx < (int)NumElems)
3442 Mask[i] = idx + NumElems;
3444 Mask[i] = idx - NumElems;
3448 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
3449 /// specifies a shuffle of elements that is suitable for input to 128/256-bit
3450 /// SHUFPS and SHUFPD. If Commuted is true, then it checks for sources to be
3451 /// reverse of what x86 shuffles want.
3452 static bool isSHUFPMask(ArrayRef<int> Mask, EVT VT, bool HasFp256,
3453 bool Commuted = false) {
3454 if (!HasFp256 && VT.is256BitVector())
3457 unsigned NumElems = VT.getVectorNumElements();
3458 unsigned NumLanes = VT.getSizeInBits()/128;
3459 unsigned NumLaneElems = NumElems/NumLanes;
3461 if (NumLaneElems != 2 && NumLaneElems != 4)
3464 // VSHUFPSY divides the resulting vector into 4 chunks.
3465 // The sources are also splitted into 4 chunks, and each destination
3466 // chunk must come from a different source chunk.
3468 // SRC1 => X7 X6 X5 X4 X3 X2 X1 X0
3469 // SRC2 => Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y9
3471 // DST => Y7..Y4, Y7..Y4, X7..X4, X7..X4,
3472 // Y3..Y0, Y3..Y0, X3..X0, X3..X0
3474 // VSHUFPDY divides the resulting vector into 4 chunks.
3475 // The sources are also splitted into 4 chunks, and each destination
3476 // chunk must come from a different source chunk.
3478 // SRC1 => X3 X2 X1 X0
3479 // SRC2 => Y3 Y2 Y1 Y0
3481 // DST => Y3..Y2, X3..X2, Y1..Y0, X1..X0
3483 unsigned HalfLaneElems = NumLaneElems/2;
3484 for (unsigned l = 0; l != NumElems; l += NumLaneElems) {
3485 for (unsigned i = 0; i != NumLaneElems; ++i) {
3486 int Idx = Mask[i+l];
3487 unsigned RngStart = l + ((Commuted == (i<HalfLaneElems)) ? NumElems : 0);
3488 if (!isUndefOrInRange(Idx, RngStart, RngStart+NumLaneElems))
3490 // For VSHUFPSY, the mask of the second half must be the same as the
3491 // first but with the appropriate offsets. This works in the same way as
3492 // VPERMILPS works with masks.
3493 if (NumElems != 8 || l == 0 || Mask[i] < 0)
3495 if (!isUndefOrEqual(Idx, Mask[i]+l))
3503 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
3504 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
3505 static bool isMOVHLPSMask(ArrayRef<int> Mask, EVT VT) {
3506 if (!VT.is128BitVector())
3509 unsigned NumElems = VT.getVectorNumElements();
3514 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3
3515 return isUndefOrEqual(Mask[0], 6) &&
3516 isUndefOrEqual(Mask[1], 7) &&
3517 isUndefOrEqual(Mask[2], 2) &&
3518 isUndefOrEqual(Mask[3], 3);
3521 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
3522 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
3524 static bool isMOVHLPS_v_undef_Mask(ArrayRef<int> Mask, EVT VT) {
3525 if (!VT.is128BitVector())
3528 unsigned NumElems = VT.getVectorNumElements();
3533 return isUndefOrEqual(Mask[0], 2) &&
3534 isUndefOrEqual(Mask[1], 3) &&
3535 isUndefOrEqual(Mask[2], 2) &&
3536 isUndefOrEqual(Mask[3], 3);
3539 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
3540 /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
3541 static bool isMOVLPMask(ArrayRef<int> Mask, EVT VT) {
3542 if (!VT.is128BitVector())
3545 unsigned NumElems = VT.getVectorNumElements();
3547 if (NumElems != 2 && NumElems != 4)
3550 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
3551 if (!isUndefOrEqual(Mask[i], i + NumElems))
3554 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i)
3555 if (!isUndefOrEqual(Mask[i], i))
3561 /// isMOVLHPSMask - Return true if the specified VECTOR_SHUFFLE operand
3562 /// specifies a shuffle of elements that is suitable for input to MOVLHPS.
3563 static bool isMOVLHPSMask(ArrayRef<int> Mask, EVT VT) {
3564 if (!VT.is128BitVector())
3567 unsigned NumElems = VT.getVectorNumElements();
3569 if (NumElems != 2 && NumElems != 4)
3572 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
3573 if (!isUndefOrEqual(Mask[i], i))
3576 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
3577 if (!isUndefOrEqual(Mask[i + e], i + NumElems))
3584 // Some special combinations that can be optimized.
3587 SDValue Compact8x32ShuffleNode(ShuffleVectorSDNode *SVOp,
3588 SelectionDAG &DAG) {
3589 EVT VT = SVOp->getValueType(0);
3590 DebugLoc dl = SVOp->getDebugLoc();
3592 if (VT != MVT::v8i32 && VT != MVT::v8f32)
3595 ArrayRef<int> Mask = SVOp->getMask();
3597 // These are the special masks that may be optimized.
3598 static const int MaskToOptimizeEven[] = {0, 8, 2, 10, 4, 12, 6, 14};
3599 static const int MaskToOptimizeOdd[] = {1, 9, 3, 11, 5, 13, 7, 15};
3600 bool MatchEvenMask = true;
3601 bool MatchOddMask = true;
3602 for (int i=0; i<8; ++i) {
3603 if (!isUndefOrEqual(Mask[i], MaskToOptimizeEven[i]))
3604 MatchEvenMask = false;
3605 if (!isUndefOrEqual(Mask[i], MaskToOptimizeOdd[i]))
3606 MatchOddMask = false;
3609 if (!MatchEvenMask && !MatchOddMask)
3612 SDValue UndefNode = DAG.getNode(ISD::UNDEF, dl, VT);
3614 SDValue Op0 = SVOp->getOperand(0);
3615 SDValue Op1 = SVOp->getOperand(1);
3617 if (MatchEvenMask) {
3618 // Shift the second operand right to 32 bits.
3619 static const int ShiftRightMask[] = {-1, 0, -1, 2, -1, 4, -1, 6 };
3620 Op1 = DAG.getVectorShuffle(VT, dl, Op1, UndefNode, ShiftRightMask);
3622 // Shift the first operand left to 32 bits.
3623 static const int ShiftLeftMask[] = {1, -1, 3, -1, 5, -1, 7, -1 };
3624 Op0 = DAG.getVectorShuffle(VT, dl, Op0, UndefNode, ShiftLeftMask);
3626 static const int BlendMask[] = {0, 9, 2, 11, 4, 13, 6, 15};
3627 return DAG.getVectorShuffle(VT, dl, Op0, Op1, BlendMask);
3630 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
3631 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
3632 static bool isUNPCKLMask(ArrayRef<int> Mask, EVT VT,
3633 bool HasInt256, bool V2IsSplat = false) {
3634 unsigned NumElts = VT.getVectorNumElements();
3636 assert((VT.is128BitVector() || VT.is256BitVector()) &&
3637 "Unsupported vector type for unpckh");
3639 if (VT.is256BitVector() && NumElts != 4 && NumElts != 8 &&
3640 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
3643 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
3644 // independently on 128-bit lanes.
3645 unsigned NumLanes = VT.getSizeInBits()/128;
3646 unsigned NumLaneElts = NumElts/NumLanes;
3648 for (unsigned l = 0; l != NumLanes; ++l) {
3649 for (unsigned i = l*NumLaneElts, j = l*NumLaneElts;
3650 i != (l+1)*NumLaneElts;
3653 int BitI1 = Mask[i+1];
3654 if (!isUndefOrEqual(BitI, j))
3657 if (!isUndefOrEqual(BitI1, NumElts))
3660 if (!isUndefOrEqual(BitI1, j + NumElts))
3669 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
3670 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
3671 static bool isUNPCKHMask(ArrayRef<int> Mask, EVT VT,
3672 bool HasInt256, bool V2IsSplat = false) {
3673 unsigned NumElts = VT.getVectorNumElements();
3675 assert((VT.is128BitVector() || VT.is256BitVector()) &&
3676 "Unsupported vector type for unpckh");
3678 if (VT.is256BitVector() && NumElts != 4 && NumElts != 8 &&
3679 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
3682 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
3683 // independently on 128-bit lanes.
3684 unsigned NumLanes = VT.getSizeInBits()/128;
3685 unsigned NumLaneElts = NumElts/NumLanes;
3687 for (unsigned l = 0; l != NumLanes; ++l) {
3688 for (unsigned i = l*NumLaneElts, j = (l*NumLaneElts)+NumLaneElts/2;
3689 i != (l+1)*NumLaneElts; i += 2, ++j) {
3691 int BitI1 = Mask[i+1];
3692 if (!isUndefOrEqual(BitI, j))
3695 if (isUndefOrEqual(BitI1, NumElts))
3698 if (!isUndefOrEqual(BitI1, j+NumElts))
3706 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
3707 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
3709 static bool isUNPCKL_v_undef_Mask(ArrayRef<int> Mask, EVT VT, bool HasInt256) {
3710 unsigned NumElts = VT.getVectorNumElements();
3711 bool Is256BitVec = VT.is256BitVector();
3713 assert((VT.is128BitVector() || VT.is256BitVector()) &&
3714 "Unsupported vector type for unpckh");
3716 if (Is256BitVec && NumElts != 4 && NumElts != 8 &&
3717 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
3720 // For 256-bit i64/f64, use MOVDDUPY instead, so reject the matching pattern
3721 // FIXME: Need a better way to get rid of this, there's no latency difference
3722 // between UNPCKLPD and MOVDDUP, the later should always be checked first and
3723 // the former later. We should also remove the "_undef" special mask.
3724 if (NumElts == 4 && Is256BitVec)
3727 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
3728 // independently on 128-bit lanes.
3729 unsigned NumLanes = VT.getSizeInBits()/128;
3730 unsigned NumLaneElts = NumElts/NumLanes;
3732 for (unsigned l = 0; l != NumLanes; ++l) {
3733 for (unsigned i = l*NumLaneElts, j = l*NumLaneElts;
3734 i != (l+1)*NumLaneElts;
3737 int BitI1 = Mask[i+1];
3739 if (!isUndefOrEqual(BitI, j))
3741 if (!isUndefOrEqual(BitI1, j))
3749 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
3750 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
3752 static bool isUNPCKH_v_undef_Mask(ArrayRef<int> Mask, EVT VT, bool HasInt256) {
3753 unsigned NumElts = VT.getVectorNumElements();
3755 assert((VT.is128BitVector() || VT.is256BitVector()) &&
3756 "Unsupported vector type for unpckh");
3758 if (VT.is256BitVector() && NumElts != 4 && NumElts != 8 &&
3759 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
3762 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
3763 // independently on 128-bit lanes.
3764 unsigned NumLanes = VT.getSizeInBits()/128;
3765 unsigned NumLaneElts = NumElts/NumLanes;
3767 for (unsigned l = 0; l != NumLanes; ++l) {
3768 for (unsigned i = l*NumLaneElts, j = (l*NumLaneElts)+NumLaneElts/2;
3769 i != (l+1)*NumLaneElts; i += 2, ++j) {
3771 int BitI1 = Mask[i+1];
3772 if (!isUndefOrEqual(BitI, j))
3774 if (!isUndefOrEqual(BitI1, j))
3781 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
3782 /// specifies a shuffle of elements that is suitable for input to MOVSS,
3783 /// MOVSD, and MOVD, i.e. setting the lowest element.
3784 static bool isMOVLMask(ArrayRef<int> Mask, EVT VT) {
3785 if (VT.getVectorElementType().getSizeInBits() < 32)
3787 if (!VT.is128BitVector())
3790 unsigned NumElts = VT.getVectorNumElements();
3792 if (!isUndefOrEqual(Mask[0], NumElts))
3795 for (unsigned i = 1; i != NumElts; ++i)
3796 if (!isUndefOrEqual(Mask[i], i))
3802 /// isVPERM2X128Mask - Match 256-bit shuffles where the elements are considered
3803 /// as permutations between 128-bit chunks or halves. As an example: this
3805 /// vector_shuffle <4, 5, 6, 7, 12, 13, 14, 15>
3806 /// The first half comes from the second half of V1 and the second half from the
3807 /// the second half of V2.
3808 static bool isVPERM2X128Mask(ArrayRef<int> Mask, EVT VT, bool HasFp256) {
3809 if (!HasFp256 || !VT.is256BitVector())
3812 // The shuffle result is divided into half A and half B. In total the two
3813 // sources have 4 halves, namely: C, D, E, F. The final values of A and
3814 // B must come from C, D, E or F.
3815 unsigned HalfSize = VT.getVectorNumElements()/2;
3816 bool MatchA = false, MatchB = false;
3818 // Check if A comes from one of C, D, E, F.
3819 for (unsigned Half = 0; Half != 4; ++Half) {
3820 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, Half*HalfSize)) {
3826 // Check if B comes from one of C, D, E, F.
3827 for (unsigned Half = 0; Half != 4; ++Half) {
3828 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, Half*HalfSize)) {
3834 return MatchA && MatchB;
3837 /// getShuffleVPERM2X128Immediate - Return the appropriate immediate to shuffle
3838 /// the specified VECTOR_MASK mask with VPERM2F128/VPERM2I128 instructions.
3839 static unsigned getShuffleVPERM2X128Immediate(ShuffleVectorSDNode *SVOp) {
3840 EVT VT = SVOp->getValueType(0);
3842 unsigned HalfSize = VT.getVectorNumElements()/2;
3844 unsigned FstHalf = 0, SndHalf = 0;
3845 for (unsigned i = 0; i < HalfSize; ++i) {
3846 if (SVOp->getMaskElt(i) > 0) {
3847 FstHalf = SVOp->getMaskElt(i)/HalfSize;
3851 for (unsigned i = HalfSize; i < HalfSize*2; ++i) {
3852 if (SVOp->getMaskElt(i) > 0) {
3853 SndHalf = SVOp->getMaskElt(i)/HalfSize;
3858 return (FstHalf | (SndHalf << 4));
3861 /// isVPERMILPMask - Return true if the specified VECTOR_SHUFFLE operand
3862 /// specifies a shuffle of elements that is suitable for input to VPERMILPD*.
3863 /// Note that VPERMIL mask matching is different depending whether theunderlying
3864 /// type is 32 or 64. In the VPERMILPS the high half of the mask should point
3865 /// to the same elements of the low, but to the higher half of the source.
3866 /// In VPERMILPD the two lanes could be shuffled independently of each other
3867 /// with the same restriction that lanes can't be crossed. Also handles PSHUFDY.
3868 static bool isVPERMILPMask(ArrayRef<int> Mask, EVT VT, bool HasFp256) {
3872 unsigned NumElts = VT.getVectorNumElements();
3873 // Only match 256-bit with 32/64-bit types
3874 if (!VT.is256BitVector() || (NumElts != 4 && NumElts != 8))
3877 unsigned NumLanes = VT.getSizeInBits()/128;
3878 unsigned LaneSize = NumElts/NumLanes;
3879 for (unsigned l = 0; l != NumElts; l += LaneSize) {
3880 for (unsigned i = 0; i != LaneSize; ++i) {
3881 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize))
3883 if (NumElts != 8 || l == 0)
3885 // VPERMILPS handling
3888 if (!isUndefOrEqual(Mask[i+l], Mask[i]+l))
3896 /// isCommutedMOVLMask - Returns true if the shuffle mask is except the reverse
3897 /// of what x86 movss want. X86 movs requires the lowest element to be lowest
3898 /// element of vector 2 and the other elements to come from vector 1 in order.
3899 static bool isCommutedMOVLMask(ArrayRef<int> Mask, EVT VT,
3900 bool V2IsSplat = false, bool V2IsUndef = false) {
3901 if (!VT.is128BitVector())
3904 unsigned NumOps = VT.getVectorNumElements();
3905 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16)
3908 if (!isUndefOrEqual(Mask[0], 0))
3911 for (unsigned i = 1; i != NumOps; ++i)
3912 if (!(isUndefOrEqual(Mask[i], i+NumOps) ||
3913 (V2IsUndef && isUndefOrInRange(Mask[i], NumOps, NumOps*2)) ||
3914 (V2IsSplat && isUndefOrEqual(Mask[i], NumOps))))
3920 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
3921 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
3922 /// Masks to match: <1, 1, 3, 3> or <1, 1, 3, 3, 5, 5, 7, 7>
3923 static bool isMOVSHDUPMask(ArrayRef<int> Mask, EVT VT,
3924 const X86Subtarget *Subtarget) {
3925 if (!Subtarget->hasSSE3())
3928 unsigned NumElems = VT.getVectorNumElements();
3930 if ((VT.is128BitVector() && NumElems != 4) ||
3931 (VT.is256BitVector() && NumElems != 8))
3934 // "i+1" is the value the indexed mask element must have
3935 for (unsigned i = 0; i != NumElems; i += 2)
3936 if (!isUndefOrEqual(Mask[i], i+1) ||
3937 !isUndefOrEqual(Mask[i+1], i+1))
3943 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
3944 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
3945 /// Masks to match: <0, 0, 2, 2> or <0, 0, 2, 2, 4, 4, 6, 6>
3946 static bool isMOVSLDUPMask(ArrayRef<int> Mask, EVT VT,
3947 const X86Subtarget *Subtarget) {
3948 if (!Subtarget->hasSSE3())
3951 unsigned NumElems = VT.getVectorNumElements();
3953 if ((VT.is128BitVector() && NumElems != 4) ||
3954 (VT.is256BitVector() && NumElems != 8))
3957 // "i" is the value the indexed mask element must have
3958 for (unsigned i = 0; i != NumElems; i += 2)
3959 if (!isUndefOrEqual(Mask[i], i) ||
3960 !isUndefOrEqual(Mask[i+1], i))
3966 /// isMOVDDUPYMask - Return true if the specified VECTOR_SHUFFLE operand
3967 /// specifies a shuffle of elements that is suitable for input to 256-bit
3968 /// version of MOVDDUP.
3969 static bool isMOVDDUPYMask(ArrayRef<int> Mask, EVT VT, bool HasFp256) {
3970 if (!HasFp256 || !VT.is256BitVector())
3973 unsigned NumElts = VT.getVectorNumElements();
3977 for (unsigned i = 0; i != NumElts/2; ++i)
3978 if (!isUndefOrEqual(Mask[i], 0))
3980 for (unsigned i = NumElts/2; i != NumElts; ++i)
3981 if (!isUndefOrEqual(Mask[i], NumElts/2))
3986 /// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand
3987 /// specifies a shuffle of elements that is suitable for input to 128-bit
3988 /// version of MOVDDUP.
3989 static bool isMOVDDUPMask(ArrayRef<int> Mask, EVT VT) {
3990 if (!VT.is128BitVector())
3993 unsigned e = VT.getVectorNumElements() / 2;
3994 for (unsigned i = 0; i != e; ++i)
3995 if (!isUndefOrEqual(Mask[i], i))
3997 for (unsigned i = 0; i != e; ++i)
3998 if (!isUndefOrEqual(Mask[e+i], i))
4003 /// isVEXTRACTF128Index - Return true if the specified
4004 /// EXTRACT_SUBVECTOR operand specifies a vector extract that is
4005 /// suitable for input to VEXTRACTF128.
4006 bool X86::isVEXTRACTF128Index(SDNode *N) {
4007 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4010 // The index should be aligned on a 128-bit boundary.
4012 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4014 MVT VT = N->getValueType(0).getSimpleVT();
4015 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4016 bool Result = (Index * ElSize) % 128 == 0;
4021 /// isVINSERTF128Index - Return true if the specified INSERT_SUBVECTOR
4022 /// operand specifies a subvector insert that is suitable for input to
4024 bool X86::isVINSERTF128Index(SDNode *N) {
4025 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4028 // The index should be aligned on a 128-bit boundary.
4030 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4032 MVT VT = N->getValueType(0).getSimpleVT();
4033 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4034 bool Result = (Index * ElSize) % 128 == 0;
4039 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
4040 /// the specified VECTOR_SHUFFLE mask with PSHUF* and SHUFP* instructions.
4041 /// Handles 128-bit and 256-bit.
4042 static unsigned getShuffleSHUFImmediate(ShuffleVectorSDNode *N) {
4043 EVT VT = N->getValueType(0);
4045 assert((VT.is128BitVector() || VT.is256BitVector()) &&
4046 "Unsupported vector type for PSHUF/SHUFP");
4048 // Handle 128 and 256-bit vector lengths. AVX defines PSHUF/SHUFP to operate
4049 // independently on 128-bit lanes.
4050 unsigned NumElts = VT.getVectorNumElements();
4051 unsigned NumLanes = VT.getSizeInBits()/128;
4052 unsigned NumLaneElts = NumElts/NumLanes;
4054 assert((NumLaneElts == 2 || NumLaneElts == 4) &&
4055 "Only supports 2 or 4 elements per lane");
4057 unsigned Shift = (NumLaneElts == 4) ? 1 : 0;
4059 for (unsigned i = 0; i != NumElts; ++i) {
4060 int Elt = N->getMaskElt(i);
4061 if (Elt < 0) continue;
4062 Elt &= NumLaneElts - 1;
4063 unsigned ShAmt = (i << Shift) % 8;
4064 Mask |= Elt << ShAmt;
4070 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
4071 /// the specified VECTOR_SHUFFLE mask with the PSHUFHW instruction.
4072 static unsigned getShufflePSHUFHWImmediate(ShuffleVectorSDNode *N) {
4073 EVT VT = N->getValueType(0);
4075 assert((VT == MVT::v8i16 || VT == MVT::v16i16) &&
4076 "Unsupported vector type for PSHUFHW");
4078 unsigned NumElts = VT.getVectorNumElements();
4081 for (unsigned l = 0; l != NumElts; l += 8) {
4082 // 8 nodes per lane, but we only care about the last 4.
4083 for (unsigned i = 0; i < 4; ++i) {
4084 int Elt = N->getMaskElt(l+i+4);
4085 if (Elt < 0) continue;
4086 Elt &= 0x3; // only 2-bits.
4087 Mask |= Elt << (i * 2);
4094 /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
4095 /// the specified VECTOR_SHUFFLE mask with the PSHUFLW instruction.
4096 static unsigned getShufflePSHUFLWImmediate(ShuffleVectorSDNode *N) {
4097 EVT VT = N->getValueType(0);
4099 assert((VT == MVT::v8i16 || VT == MVT::v16i16) &&
4100 "Unsupported vector type for PSHUFHW");
4102 unsigned NumElts = VT.getVectorNumElements();
4105 for (unsigned l = 0; l != NumElts; l += 8) {
4106 // 8 nodes per lane, but we only care about the first 4.
4107 for (unsigned i = 0; i < 4; ++i) {
4108 int Elt = N->getMaskElt(l+i);
4109 if (Elt < 0) continue;
4110 Elt &= 0x3; // only 2-bits
4111 Mask |= Elt << (i * 2);
4118 /// getShufflePALIGNRImmediate - Return the appropriate immediate to shuffle
4119 /// the specified VECTOR_SHUFFLE mask with the PALIGNR instruction.
4120 static unsigned getShufflePALIGNRImmediate(ShuffleVectorSDNode *SVOp) {
4121 EVT VT = SVOp->getValueType(0);
4122 unsigned EltSize = VT.getVectorElementType().getSizeInBits() >> 3;
4124 unsigned NumElts = VT.getVectorNumElements();
4125 unsigned NumLanes = VT.getSizeInBits()/128;
4126 unsigned NumLaneElts = NumElts/NumLanes;
4130 for (i = 0; i != NumElts; ++i) {
4131 Val = SVOp->getMaskElt(i);
4135 if (Val >= (int)NumElts)
4136 Val -= NumElts - NumLaneElts;
4138 assert(Val - i > 0 && "PALIGNR imm should be positive");
4139 return (Val - i) * EltSize;
4142 /// getExtractVEXTRACTF128Immediate - Return the appropriate immediate
4143 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF128
4145 unsigned X86::getExtractVEXTRACTF128Immediate(SDNode *N) {
4146 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4147 llvm_unreachable("Illegal extract subvector for VEXTRACTF128");
4150 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4152 EVT VecVT = N->getOperand(0).getValueType();
4153 EVT ElVT = VecVT.getVectorElementType();
4155 unsigned NumElemsPerChunk = 128 / ElVT.getSizeInBits();
4156 return Index / NumElemsPerChunk;
4159 /// getInsertVINSERTF128Immediate - Return the appropriate immediate
4160 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF128
4162 unsigned X86::getInsertVINSERTF128Immediate(SDNode *N) {
4163 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4164 llvm_unreachable("Illegal insert subvector for VINSERTF128");
4167 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4169 EVT VecVT = N->getValueType(0);
4170 EVT ElVT = VecVT.getVectorElementType();
4172 unsigned NumElemsPerChunk = 128 / ElVT.getSizeInBits();
4173 return Index / NumElemsPerChunk;
4176 /// getShuffleCLImmediate - Return the appropriate immediate to shuffle
4177 /// the specified VECTOR_SHUFFLE mask with VPERMQ and VPERMPD instructions.
4178 /// Handles 256-bit.
4179 static unsigned getShuffleCLImmediate(ShuffleVectorSDNode *N) {
4180 EVT VT = N->getValueType(0);
4182 unsigned NumElts = VT.getVectorNumElements();
4184 assert((VT.is256BitVector() && NumElts == 4) &&
4185 "Unsupported vector type for VPERMQ/VPERMPD");
4188 for (unsigned i = 0; i != NumElts; ++i) {
4189 int Elt = N->getMaskElt(i);
4192 Mask |= Elt << (i*2);
4197 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
4199 bool X86::isZeroNode(SDValue Elt) {
4200 return ((isa<ConstantSDNode>(Elt) &&
4201 cast<ConstantSDNode>(Elt)->isNullValue()) ||
4202 (isa<ConstantFPSDNode>(Elt) &&
4203 cast<ConstantFPSDNode>(Elt)->getValueAPF().isPosZero()));
4206 /// CommuteVectorShuffle - Swap vector_shuffle operands as well as values in
4207 /// their permute mask.
4208 static SDValue CommuteVectorShuffle(ShuffleVectorSDNode *SVOp,
4209 SelectionDAG &DAG) {
4210 EVT VT = SVOp->getValueType(0);
4211 unsigned NumElems = VT.getVectorNumElements();
4212 SmallVector<int, 8> MaskVec;
4214 for (unsigned i = 0; i != NumElems; ++i) {
4215 int Idx = SVOp->getMaskElt(i);
4217 if (Idx < (int)NumElems)
4222 MaskVec.push_back(Idx);
4224 return DAG.getVectorShuffle(VT, SVOp->getDebugLoc(), SVOp->getOperand(1),
4225 SVOp->getOperand(0), &MaskVec[0]);
4228 /// ShouldXformToMOVHLPS - Return true if the node should be transformed to
4229 /// match movhlps. The lower half elements should come from upper half of
4230 /// V1 (and in order), and the upper half elements should come from the upper
4231 /// half of V2 (and in order).
4232 static bool ShouldXformToMOVHLPS(ArrayRef<int> Mask, EVT VT) {
4233 if (!VT.is128BitVector())
4235 if (VT.getVectorNumElements() != 4)
4237 for (unsigned i = 0, e = 2; i != e; ++i)
4238 if (!isUndefOrEqual(Mask[i], i+2))
4240 for (unsigned i = 2; i != 4; ++i)
4241 if (!isUndefOrEqual(Mask[i], i+4))
4246 /// isScalarLoadToVector - Returns true if the node is a scalar load that
4247 /// is promoted to a vector. It also returns the LoadSDNode by reference if
4249 static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = NULL) {
4250 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR)
4252 N = N->getOperand(0).getNode();
4253 if (!ISD::isNON_EXTLoad(N))
4256 *LD = cast<LoadSDNode>(N);
4260 // Test whether the given value is a vector value which will be legalized
4262 static bool WillBeConstantPoolLoad(SDNode *N) {
4263 if (N->getOpcode() != ISD::BUILD_VECTOR)
4266 // Check for any non-constant elements.
4267 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
4268 switch (N->getOperand(i).getNode()->getOpcode()) {
4270 case ISD::ConstantFP:
4277 // Vectors of all-zeros and all-ones are materialized with special
4278 // instructions rather than being loaded.
4279 return !ISD::isBuildVectorAllZeros(N) &&
4280 !ISD::isBuildVectorAllOnes(N);
4283 /// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to
4284 /// match movlp{s|d}. The lower half elements should come from lower half of
4285 /// V1 (and in order), and the upper half elements should come from the upper
4286 /// half of V2 (and in order). And since V1 will become the source of the
4287 /// MOVLP, it must be either a vector load or a scalar load to vector.
4288 static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2,
4289 ArrayRef<int> Mask, EVT VT) {
4290 if (!VT.is128BitVector())
4293 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1))
4295 // Is V2 is a vector load, don't do this transformation. We will try to use
4296 // load folding shufps op.
4297 if (ISD::isNON_EXTLoad(V2) || WillBeConstantPoolLoad(V2))
4300 unsigned NumElems = VT.getVectorNumElements();
4302 if (NumElems != 2 && NumElems != 4)
4304 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4305 if (!isUndefOrEqual(Mask[i], i))
4307 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i)
4308 if (!isUndefOrEqual(Mask[i], i+NumElems))
4313 /// isSplatVector - Returns true if N is a BUILD_VECTOR node whose elements are
4315 static bool isSplatVector(SDNode *N) {
4316 if (N->getOpcode() != ISD::BUILD_VECTOR)
4319 SDValue SplatValue = N->getOperand(0);
4320 for (unsigned i = 1, e = N->getNumOperands(); i != e; ++i)
4321 if (N->getOperand(i) != SplatValue)
4326 /// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
4327 /// to an zero vector.
4328 /// FIXME: move to dag combiner / method on ShuffleVectorSDNode
4329 static bool isZeroShuffle(ShuffleVectorSDNode *N) {
4330 SDValue V1 = N->getOperand(0);
4331 SDValue V2 = N->getOperand(1);
4332 unsigned NumElems = N->getValueType(0).getVectorNumElements();
4333 for (unsigned i = 0; i != NumElems; ++i) {
4334 int Idx = N->getMaskElt(i);
4335 if (Idx >= (int)NumElems) {
4336 unsigned Opc = V2.getOpcode();
4337 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode()))
4339 if (Opc != ISD::BUILD_VECTOR ||
4340 !X86::isZeroNode(V2.getOperand(Idx-NumElems)))
4342 } else if (Idx >= 0) {
4343 unsigned Opc = V1.getOpcode();
4344 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode()))
4346 if (Opc != ISD::BUILD_VECTOR ||
4347 !X86::isZeroNode(V1.getOperand(Idx)))
4354 /// getZeroVector - Returns a vector of specified type with all zero elements.
4356 static SDValue getZeroVector(EVT VT, const X86Subtarget *Subtarget,
4357 SelectionDAG &DAG, DebugLoc dl) {
4358 assert(VT.isVector() && "Expected a vector type");
4360 // Always build SSE zero vectors as <4 x i32> bitcasted
4361 // to their dest type. This ensures they get CSE'd.
4363 if (VT.is128BitVector()) { // SSE
4364 if (Subtarget->hasSSE2()) { // SSE2
4365 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
4366 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4368 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
4369 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
4371 } else if (VT.is256BitVector()) { // AVX
4372 if (Subtarget->hasInt256()) { // AVX2
4373 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
4374 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4375 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops, 8);
4377 // 256-bit logic and arithmetic instructions in AVX are all
4378 // floating-point, no support for integer ops. Emit fp zeroed vectors.
4379 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
4380 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4381 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops, 8);
4384 llvm_unreachable("Unexpected vector type");
4386 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
4389 /// getOnesVector - Returns a vector of specified type with all bits set.
4390 /// Always build ones vectors as <4 x i32> or <8 x i32>. For 256-bit types with
4391 /// no AVX2 supprt, use two <4 x i32> inserted in a <8 x i32> appropriately.
4392 /// Then bitcast to their original type, ensuring they get CSE'd.
4393 static SDValue getOnesVector(EVT VT, bool HasInt256, SelectionDAG &DAG,
4395 assert(VT.isVector() && "Expected a vector type");
4397 SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32);
4399 if (VT.is256BitVector()) {
4400 if (HasInt256) { // AVX2
4401 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4402 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops, 8);
4404 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4405 Vec = Concat128BitVectors(Vec, Vec, MVT::v8i32, 8, DAG, dl);
4407 } else if (VT.is128BitVector()) {
4408 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4410 llvm_unreachable("Unexpected vector type");
4412 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
4415 /// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements
4416 /// that point to V2 points to its first element.
4417 static void NormalizeMask(SmallVectorImpl<int> &Mask, unsigned NumElems) {
4418 for (unsigned i = 0; i != NumElems; ++i) {
4419 if (Mask[i] > (int)NumElems) {
4425 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
4426 /// operation of specified width.
4427 static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
4429 unsigned NumElems = VT.getVectorNumElements();
4430 SmallVector<int, 8> Mask;
4431 Mask.push_back(NumElems);
4432 for (unsigned i = 1; i != NumElems; ++i)
4434 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4437 /// getUnpackl - Returns a vector_shuffle node for an unpackl operation.
4438 static SDValue getUnpackl(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
4440 unsigned NumElems = VT.getVectorNumElements();
4441 SmallVector<int, 8> Mask;
4442 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
4444 Mask.push_back(i + NumElems);
4446 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4449 /// getUnpackh - Returns a vector_shuffle node for an unpackh operation.
4450 static SDValue getUnpackh(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
4452 unsigned NumElems = VT.getVectorNumElements();
4453 SmallVector<int, 8> Mask;
4454 for (unsigned i = 0, Half = NumElems/2; i != Half; ++i) {
4455 Mask.push_back(i + Half);
4456 Mask.push_back(i + NumElems + Half);
4458 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4461 // PromoteSplati8i16 - All i16 and i8 vector types can't be used directly by
4462 // a generic shuffle instruction because the target has no such instructions.
4463 // Generate shuffles which repeat i16 and i8 several times until they can be
4464 // represented by v4f32 and then be manipulated by target suported shuffles.
4465 static SDValue PromoteSplati8i16(SDValue V, SelectionDAG &DAG, int &EltNo) {
4466 EVT VT = V.getValueType();
4467 int NumElems = VT.getVectorNumElements();
4468 DebugLoc dl = V.getDebugLoc();
4470 while (NumElems > 4) {
4471 if (EltNo < NumElems/2) {
4472 V = getUnpackl(DAG, dl, VT, V, V);
4474 V = getUnpackh(DAG, dl, VT, V, V);
4475 EltNo -= NumElems/2;
4482 /// getLegalSplat - Generate a legal splat with supported x86 shuffles
4483 static SDValue getLegalSplat(SelectionDAG &DAG, SDValue V, int EltNo) {
4484 EVT VT = V.getValueType();
4485 DebugLoc dl = V.getDebugLoc();
4487 if (VT.is128BitVector()) {
4488 V = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V);
4489 int SplatMask[4] = { EltNo, EltNo, EltNo, EltNo };
4490 V = DAG.getVectorShuffle(MVT::v4f32, dl, V, DAG.getUNDEF(MVT::v4f32),
4492 } else if (VT.is256BitVector()) {
4493 // To use VPERMILPS to splat scalars, the second half of indicies must
4494 // refer to the higher part, which is a duplication of the lower one,
4495 // because VPERMILPS can only handle in-lane permutations.
4496 int SplatMask[8] = { EltNo, EltNo, EltNo, EltNo,
4497 EltNo+4, EltNo+4, EltNo+4, EltNo+4 };
4499 V = DAG.getNode(ISD::BITCAST, dl, MVT::v8f32, V);
4500 V = DAG.getVectorShuffle(MVT::v8f32, dl, V, DAG.getUNDEF(MVT::v8f32),
4503 llvm_unreachable("Vector size not supported");
4505 return DAG.getNode(ISD::BITCAST, dl, VT, V);
4508 /// PromoteSplat - Splat is promoted to target supported vector shuffles.
4509 static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG) {
4510 EVT SrcVT = SV->getValueType(0);
4511 SDValue V1 = SV->getOperand(0);
4512 DebugLoc dl = SV->getDebugLoc();
4514 int EltNo = SV->getSplatIndex();
4515 int NumElems = SrcVT.getVectorNumElements();
4516 bool Is256BitVec = SrcVT.is256BitVector();
4518 assert(((SrcVT.is128BitVector() && NumElems > 4) || Is256BitVec) &&
4519 "Unknown how to promote splat for type");
4521 // Extract the 128-bit part containing the splat element and update
4522 // the splat element index when it refers to the higher register.
4524 V1 = Extract128BitVector(V1, EltNo, DAG, dl);
4525 if (EltNo >= NumElems/2)
4526 EltNo -= NumElems/2;
4529 // All i16 and i8 vector types can't be used directly by a generic shuffle
4530 // instruction because the target has no such instruction. Generate shuffles
4531 // which repeat i16 and i8 several times until they fit in i32, and then can
4532 // be manipulated by target suported shuffles.
4533 EVT EltVT = SrcVT.getVectorElementType();
4534 if (EltVT == MVT::i8 || EltVT == MVT::i16)
4535 V1 = PromoteSplati8i16(V1, DAG, EltNo);
4537 // Recreate the 256-bit vector and place the same 128-bit vector
4538 // into the low and high part. This is necessary because we want
4539 // to use VPERM* to shuffle the vectors
4541 V1 = DAG.getNode(ISD::CONCAT_VECTORS, dl, SrcVT, V1, V1);
4544 return getLegalSplat(DAG, V1, EltNo);
4547 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
4548 /// vector of zero or undef vector. This produces a shuffle where the low
4549 /// element of V2 is swizzled into the zero/undef vector, landing at element
4550 /// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
4551 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
4553 const X86Subtarget *Subtarget,
4554 SelectionDAG &DAG) {
4555 EVT VT = V2.getValueType();
4557 ? getZeroVector(VT, Subtarget, DAG, V2.getDebugLoc()) : DAG.getUNDEF(VT);
4558 unsigned NumElems = VT.getVectorNumElements();
4559 SmallVector<int, 16> MaskVec;
4560 for (unsigned i = 0; i != NumElems; ++i)
4561 // If this is the insertion idx, put the low elt of V2 here.
4562 MaskVec.push_back(i == Idx ? NumElems : i);
4563 return DAG.getVectorShuffle(VT, V2.getDebugLoc(), V1, V2, &MaskVec[0]);
4566 /// getTargetShuffleMask - Calculates the shuffle mask corresponding to the
4567 /// target specific opcode. Returns true if the Mask could be calculated.
4568 /// Sets IsUnary to true if only uses one source.
4569 static bool getTargetShuffleMask(SDNode *N, MVT VT,
4570 SmallVectorImpl<int> &Mask, bool &IsUnary) {
4571 unsigned NumElems = VT.getVectorNumElements();
4575 switch(N->getOpcode()) {
4577 ImmN = N->getOperand(N->getNumOperands()-1);
4578 DecodeSHUFPMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4580 case X86ISD::UNPCKH:
4581 DecodeUNPCKHMask(VT, Mask);
4583 case X86ISD::UNPCKL:
4584 DecodeUNPCKLMask(VT, Mask);
4586 case X86ISD::MOVHLPS:
4587 DecodeMOVHLPSMask(NumElems, Mask);
4589 case X86ISD::MOVLHPS:
4590 DecodeMOVLHPSMask(NumElems, Mask);
4592 case X86ISD::PSHUFD:
4593 case X86ISD::VPERMILP:
4594 ImmN = N->getOperand(N->getNumOperands()-1);
4595 DecodePSHUFMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4598 case X86ISD::PSHUFHW:
4599 ImmN = N->getOperand(N->getNumOperands()-1);
4600 DecodePSHUFHWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4603 case X86ISD::PSHUFLW:
4604 ImmN = N->getOperand(N->getNumOperands()-1);
4605 DecodePSHUFLWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4608 case X86ISD::VPERMI:
4609 ImmN = N->getOperand(N->getNumOperands()-1);
4610 DecodeVPERMMask(cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4614 case X86ISD::MOVSD: {
4615 // The index 0 always comes from the first element of the second source,
4616 // this is why MOVSS and MOVSD are used in the first place. The other
4617 // elements come from the other positions of the first source vector
4618 Mask.push_back(NumElems);
4619 for (unsigned i = 1; i != NumElems; ++i) {
4624 case X86ISD::VPERM2X128:
4625 ImmN = N->getOperand(N->getNumOperands()-1);
4626 DecodeVPERM2X128Mask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4627 if (Mask.empty()) return false;
4629 case X86ISD::MOVDDUP:
4630 case X86ISD::MOVLHPD:
4631 case X86ISD::MOVLPD:
4632 case X86ISD::MOVLPS:
4633 case X86ISD::MOVSHDUP:
4634 case X86ISD::MOVSLDUP:
4635 case X86ISD::PALIGN:
4636 // Not yet implemented
4638 default: llvm_unreachable("unknown target shuffle node");
4644 /// getShuffleScalarElt - Returns the scalar element that will make up the ith
4645 /// element of the result of the vector shuffle.
4646 static SDValue getShuffleScalarElt(SDNode *N, unsigned Index, SelectionDAG &DAG,
4649 return SDValue(); // Limit search depth.
4651 SDValue V = SDValue(N, 0);
4652 EVT VT = V.getValueType();
4653 unsigned Opcode = V.getOpcode();
4655 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars.
4656 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) {
4657 int Elt = SV->getMaskElt(Index);
4660 return DAG.getUNDEF(VT.getVectorElementType());
4662 unsigned NumElems = VT.getVectorNumElements();
4663 SDValue NewV = (Elt < (int)NumElems) ? SV->getOperand(0)
4664 : SV->getOperand(1);
4665 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG, Depth+1);
4668 // Recurse into target specific vector shuffles to find scalars.
4669 if (isTargetShuffle(Opcode)) {
4670 MVT ShufVT = V.getValueType().getSimpleVT();
4671 unsigned NumElems = ShufVT.getVectorNumElements();
4672 SmallVector<int, 16> ShuffleMask;
4675 if (!getTargetShuffleMask(N, ShufVT, ShuffleMask, IsUnary))
4678 int Elt = ShuffleMask[Index];
4680 return DAG.getUNDEF(ShufVT.getVectorElementType());
4682 SDValue NewV = (Elt < (int)NumElems) ? N->getOperand(0)
4684 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG,
4688 // Actual nodes that may contain scalar elements
4689 if (Opcode == ISD::BITCAST) {
4690 V = V.getOperand(0);
4691 EVT SrcVT = V.getValueType();
4692 unsigned NumElems = VT.getVectorNumElements();
4694 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems)
4698 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR)
4699 return (Index == 0) ? V.getOperand(0)
4700 : DAG.getUNDEF(VT.getVectorElementType());
4702 if (V.getOpcode() == ISD::BUILD_VECTOR)
4703 return V.getOperand(Index);
4708 /// getNumOfConsecutiveZeros - Return the number of elements of a vector
4709 /// shuffle operation which come from a consecutively from a zero. The
4710 /// search can start in two different directions, from left or right.
4712 unsigned getNumOfConsecutiveZeros(ShuffleVectorSDNode *SVOp, unsigned NumElems,
4713 bool ZerosFromLeft, SelectionDAG &DAG) {
4715 for (i = 0; i != NumElems; ++i) {
4716 unsigned Index = ZerosFromLeft ? i : NumElems-i-1;
4717 SDValue Elt = getShuffleScalarElt(SVOp, Index, DAG, 0);
4718 if (!(Elt.getNode() &&
4719 (Elt.getOpcode() == ISD::UNDEF || X86::isZeroNode(Elt))))
4726 /// isShuffleMaskConsecutive - Check if the shuffle mask indicies [MaskI, MaskE)
4727 /// correspond consecutively to elements from one of the vector operands,
4728 /// starting from its index OpIdx. Also tell OpNum which source vector operand.
4730 bool isShuffleMaskConsecutive(ShuffleVectorSDNode *SVOp,
4731 unsigned MaskI, unsigned MaskE, unsigned OpIdx,
4732 unsigned NumElems, unsigned &OpNum) {
4733 bool SeenV1 = false;
4734 bool SeenV2 = false;
4736 for (unsigned i = MaskI; i != MaskE; ++i, ++OpIdx) {
4737 int Idx = SVOp->getMaskElt(i);
4738 // Ignore undef indicies
4742 if (Idx < (int)NumElems)
4747 // Only accept consecutive elements from the same vector
4748 if ((Idx % NumElems != OpIdx) || (SeenV1 && SeenV2))
4752 OpNum = SeenV1 ? 0 : 1;
4756 /// isVectorShiftRight - Returns true if the shuffle can be implemented as a
4757 /// logical left shift of a vector.
4758 static bool isVectorShiftRight(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
4759 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
4760 unsigned NumElems = SVOp->getValueType(0).getVectorNumElements();
4761 unsigned NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems,
4762 false /* check zeros from right */, DAG);
4768 // Considering the elements in the mask that are not consecutive zeros,
4769 // check if they consecutively come from only one of the source vectors.
4771 // V1 = {X, A, B, C} 0
4773 // vector_shuffle V1, V2 <1, 2, 3, X>
4775 if (!isShuffleMaskConsecutive(SVOp,
4776 0, // Mask Start Index
4777 NumElems-NumZeros, // Mask End Index(exclusive)
4778 NumZeros, // Where to start looking in the src vector
4779 NumElems, // Number of elements in vector
4780 OpSrc)) // Which source operand ?
4785 ShVal = SVOp->getOperand(OpSrc);
4789 /// isVectorShiftLeft - Returns true if the shuffle can be implemented as a
4790 /// logical left shift of a vector.
4791 static bool isVectorShiftLeft(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
4792 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
4793 unsigned NumElems = SVOp->getValueType(0).getVectorNumElements();
4794 unsigned NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems,
4795 true /* check zeros from left */, DAG);
4801 // Considering the elements in the mask that are not consecutive zeros,
4802 // check if they consecutively come from only one of the source vectors.
4804 // 0 { A, B, X, X } = V2
4806 // vector_shuffle V1, V2 <X, X, 4, 5>
4808 if (!isShuffleMaskConsecutive(SVOp,
4809 NumZeros, // Mask Start Index
4810 NumElems, // Mask End Index(exclusive)
4811 0, // Where to start looking in the src vector
4812 NumElems, // Number of elements in vector
4813 OpSrc)) // Which source operand ?
4818 ShVal = SVOp->getOperand(OpSrc);
4822 /// isVectorShift - Returns true if the shuffle can be implemented as a
4823 /// logical left or right shift of a vector.
4824 static bool isVectorShift(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
4825 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
4826 // Although the logic below support any bitwidth size, there are no
4827 // shift instructions which handle more than 128-bit vectors.
4828 if (!SVOp->getValueType(0).is128BitVector())
4831 if (isVectorShiftLeft(SVOp, DAG, isLeft, ShVal, ShAmt) ||
4832 isVectorShiftRight(SVOp, DAG, isLeft, ShVal, ShAmt))
4838 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
4840 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
4841 unsigned NumNonZero, unsigned NumZero,
4843 const X86Subtarget* Subtarget,
4844 const TargetLowering &TLI) {
4848 DebugLoc dl = Op.getDebugLoc();
4851 for (unsigned i = 0; i < 16; ++i) {
4852 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
4853 if (ThisIsNonZero && First) {
4855 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
4857 V = DAG.getUNDEF(MVT::v8i16);
4862 SDValue ThisElt(0, 0), LastElt(0, 0);
4863 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
4864 if (LastIsNonZero) {
4865 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
4866 MVT::i16, Op.getOperand(i-1));
4868 if (ThisIsNonZero) {
4869 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
4870 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
4871 ThisElt, DAG.getConstant(8, MVT::i8));
4873 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
4877 if (ThisElt.getNode())
4878 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
4879 DAG.getIntPtrConstant(i/2));
4883 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V);
4886 /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
4888 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
4889 unsigned NumNonZero, unsigned NumZero,
4891 const X86Subtarget* Subtarget,
4892 const TargetLowering &TLI) {
4896 DebugLoc dl = Op.getDebugLoc();
4899 for (unsigned i = 0; i < 8; ++i) {
4900 bool isNonZero = (NonZeros & (1 << i)) != 0;
4904 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
4906 V = DAG.getUNDEF(MVT::v8i16);
4909 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
4910 MVT::v8i16, V, Op.getOperand(i),
4911 DAG.getIntPtrConstant(i));
4918 /// getVShift - Return a vector logical shift node.
4920 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
4921 unsigned NumBits, SelectionDAG &DAG,
4922 const TargetLowering &TLI, DebugLoc dl) {
4923 assert(VT.is128BitVector() && "Unknown type for VShift");
4924 EVT ShVT = MVT::v2i64;
4925 unsigned Opc = isLeft ? X86ISD::VSHLDQ : X86ISD::VSRLDQ;
4926 SrcOp = DAG.getNode(ISD::BITCAST, dl, ShVT, SrcOp);
4927 return DAG.getNode(ISD::BITCAST, dl, VT,
4928 DAG.getNode(Opc, dl, ShVT, SrcOp,
4929 DAG.getConstant(NumBits,
4930 TLI.getShiftAmountTy(SrcOp.getValueType()))));
4934 X86TargetLowering::LowerAsSplatVectorLoad(SDValue SrcOp, EVT VT, DebugLoc dl,
4935 SelectionDAG &DAG) const {
4937 // Check if the scalar load can be widened into a vector load. And if
4938 // the address is "base + cst" see if the cst can be "absorbed" into
4939 // the shuffle mask.
4940 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) {
4941 SDValue Ptr = LD->getBasePtr();
4942 if (!ISD::isNormalLoad(LD) || LD->isVolatile())
4944 EVT PVT = LD->getValueType(0);
4945 if (PVT != MVT::i32 && PVT != MVT::f32)
4950 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) {
4951 FI = FINode->getIndex();
4953 } else if (DAG.isBaseWithConstantOffset(Ptr) &&
4954 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
4955 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
4956 Offset = Ptr.getConstantOperandVal(1);
4957 Ptr = Ptr.getOperand(0);
4962 // FIXME: 256-bit vector instructions don't require a strict alignment,
4963 // improve this code to support it better.
4964 unsigned RequiredAlign = VT.getSizeInBits()/8;
4965 SDValue Chain = LD->getChain();
4966 // Make sure the stack object alignment is at least 16 or 32.
4967 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
4968 if (DAG.InferPtrAlignment(Ptr) < RequiredAlign) {
4969 if (MFI->isFixedObjectIndex(FI)) {
4970 // Can't change the alignment. FIXME: It's possible to compute
4971 // the exact stack offset and reference FI + adjust offset instead.
4972 // If someone *really* cares about this. That's the way to implement it.
4975 MFI->setObjectAlignment(FI, RequiredAlign);
4979 // (Offset % 16 or 32) must be multiple of 4. Then address is then
4980 // Ptr + (Offset & ~15).
4983 if ((Offset % RequiredAlign) & 3)
4985 int64_t StartOffset = Offset & ~(RequiredAlign-1);
4987 Ptr = DAG.getNode(ISD::ADD, Ptr.getDebugLoc(), Ptr.getValueType(),
4988 Ptr,DAG.getConstant(StartOffset, Ptr.getValueType()));
4990 int EltNo = (Offset - StartOffset) >> 2;
4991 unsigned NumElems = VT.getVectorNumElements();
4993 EVT NVT = EVT::getVectorVT(*DAG.getContext(), PVT, NumElems);
4994 SDValue V1 = DAG.getLoad(NVT, dl, Chain, Ptr,
4995 LD->getPointerInfo().getWithOffset(StartOffset),
4996 false, false, false, 0);
4998 SmallVector<int, 8> Mask;
4999 for (unsigned i = 0; i != NumElems; ++i)
5000 Mask.push_back(EltNo);
5002 return DAG.getVectorShuffle(NVT, dl, V1, DAG.getUNDEF(NVT), &Mask[0]);
5008 /// EltsFromConsecutiveLoads - Given the initializing elements 'Elts' of a
5009 /// vector of type 'VT', see if the elements can be replaced by a single large
5010 /// load which has the same value as a build_vector whose operands are 'elts'.
5012 /// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a
5014 /// FIXME: we'd also like to handle the case where the last elements are zero
5015 /// rather than undef via VZEXT_LOAD, but we do not detect that case today.
5016 /// There's even a handy isZeroNode for that purpose.
5017 static SDValue EltsFromConsecutiveLoads(EVT VT, SmallVectorImpl<SDValue> &Elts,
5018 DebugLoc &DL, SelectionDAG &DAG) {
5019 EVT EltVT = VT.getVectorElementType();
5020 unsigned NumElems = Elts.size();
5022 LoadSDNode *LDBase = NULL;
5023 unsigned LastLoadedElt = -1U;
5025 // For each element in the initializer, see if we've found a load or an undef.
5026 // If we don't find an initial load element, or later load elements are
5027 // non-consecutive, bail out.
5028 for (unsigned i = 0; i < NumElems; ++i) {
5029 SDValue Elt = Elts[i];
5031 if (!Elt.getNode() ||
5032 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
5035 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
5037 LDBase = cast<LoadSDNode>(Elt.getNode());
5041 if (Elt.getOpcode() == ISD::UNDEF)
5044 LoadSDNode *LD = cast<LoadSDNode>(Elt);
5045 if (!DAG.isConsecutiveLoad(LD, LDBase, EltVT.getSizeInBits()/8, i))
5050 // If we have found an entire vector of loads and undefs, then return a large
5051 // load of the entire vector width starting at the base pointer. If we found
5052 // consecutive loads for the low half, generate a vzext_load node.
5053 if (LastLoadedElt == NumElems - 1) {
5054 if (DAG.InferPtrAlignment(LDBase->getBasePtr()) >= 16)
5055 return DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
5056 LDBase->getPointerInfo(),
5057 LDBase->isVolatile(), LDBase->isNonTemporal(),
5058 LDBase->isInvariant(), 0);
5059 return DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
5060 LDBase->getPointerInfo(),
5061 LDBase->isVolatile(), LDBase->isNonTemporal(),
5062 LDBase->isInvariant(), LDBase->getAlignment());
5064 if (NumElems == 4 && LastLoadedElt == 1 &&
5065 DAG.getTargetLoweringInfo().isTypeLegal(MVT::v2i64)) {
5066 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
5067 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() };
5069 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys, Ops, 2, MVT::i64,
5070 LDBase->getPointerInfo(),
5071 LDBase->getAlignment(),
5072 false/*isVolatile*/, true/*ReadMem*/,
5075 // Make sure the newly-created LOAD is in the same position as LDBase in
5076 // terms of dependency. We create a TokenFactor for LDBase and ResNode, and
5077 // update uses of LDBase's output chain to use the TokenFactor.
5078 if (LDBase->hasAnyUseOfValue(1)) {
5079 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
5080 SDValue(LDBase, 1), SDValue(ResNode.getNode(), 1));
5081 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
5082 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
5083 SDValue(ResNode.getNode(), 1));
5086 return DAG.getNode(ISD::BITCAST, DL, VT, ResNode);
5091 /// LowerVectorBroadcast - Attempt to use the vbroadcast instruction
5092 /// to generate a splat value for the following cases:
5093 /// 1. A splat BUILD_VECTOR which uses a single scalar load, or a constant.
5094 /// 2. A splat shuffle which uses a scalar_to_vector node which comes from
5095 /// a scalar load, or a constant.
5096 /// The VBROADCAST node is returned when a pattern is found,
5097 /// or SDValue() otherwise.
5099 X86TargetLowering::LowerVectorBroadcast(SDValue Op, SelectionDAG &DAG) const {
5100 if (!Subtarget->hasFp256())
5103 EVT VT = Op.getValueType();
5104 DebugLoc dl = Op.getDebugLoc();
5106 assert((VT.is128BitVector() || VT.is256BitVector()) &&
5107 "Unsupported vector type for broadcast.");
5112 switch (Op.getOpcode()) {
5114 // Unknown pattern found.
5117 case ISD::BUILD_VECTOR: {
5118 // The BUILD_VECTOR node must be a splat.
5119 if (!isSplatVector(Op.getNode()))
5122 Ld = Op.getOperand(0);
5123 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
5124 Ld.getOpcode() == ISD::ConstantFP);
5126 // The suspected load node has several users. Make sure that all
5127 // of its users are from the BUILD_VECTOR node.
5128 // Constants may have multiple users.
5129 if (!ConstSplatVal && !Ld->hasNUsesOfValue(VT.getVectorNumElements(), 0))
5134 case ISD::VECTOR_SHUFFLE: {
5135 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
5137 // Shuffles must have a splat mask where the first element is
5139 if ((!SVOp->isSplat()) || SVOp->getMaskElt(0) != 0)
5142 SDValue Sc = Op.getOperand(0);
5143 if (Sc.getOpcode() != ISD::SCALAR_TO_VECTOR &&
5144 Sc.getOpcode() != ISD::BUILD_VECTOR) {
5146 if (!Subtarget->hasInt256())
5149 // Use the register form of the broadcast instruction available on AVX2.
5150 if (VT.is256BitVector())
5151 Sc = Extract128BitVector(Sc, 0, DAG, dl);
5152 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Sc);
5155 Ld = Sc.getOperand(0);
5156 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
5157 Ld.getOpcode() == ISD::ConstantFP);
5159 // The scalar_to_vector node and the suspected
5160 // load node must have exactly one user.
5161 // Constants may have multiple users.
5162 if (!ConstSplatVal && (!Sc.hasOneUse() || !Ld.hasOneUse()))
5168 bool Is256 = VT.is256BitVector();
5170 // Handle the broadcasting a single constant scalar from the constant pool
5171 // into a vector. On Sandybridge it is still better to load a constant vector
5172 // from the constant pool and not to broadcast it from a scalar.
5173 if (ConstSplatVal && Subtarget->hasInt256()) {
5174 EVT CVT = Ld.getValueType();
5175 assert(!CVT.isVector() && "Must not broadcast a vector type");
5176 unsigned ScalarSize = CVT.getSizeInBits();
5178 if (ScalarSize == 32 || (Is256 && ScalarSize == 64)) {
5179 const Constant *C = 0;
5180 if (ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Ld))
5181 C = CI->getConstantIntValue();
5182 else if (ConstantFPSDNode *CF = dyn_cast<ConstantFPSDNode>(Ld))
5183 C = CF->getConstantFPValue();
5185 assert(C && "Invalid constant type");
5187 SDValue CP = DAG.getConstantPool(C, getPointerTy());
5188 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
5189 Ld = DAG.getLoad(CVT, dl, DAG.getEntryNode(), CP,
5190 MachinePointerInfo::getConstantPool(),
5191 false, false, false, Alignment);
5193 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5197 bool IsLoad = ISD::isNormalLoad(Ld.getNode());
5198 unsigned ScalarSize = Ld.getValueType().getSizeInBits();
5200 // Handle AVX2 in-register broadcasts.
5201 if (!IsLoad && Subtarget->hasInt256() &&
5202 (ScalarSize == 32 || (Is256 && ScalarSize == 64)))
5203 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5205 // The scalar source must be a normal load.
5209 if (ScalarSize == 32 || (Is256 && ScalarSize == 64))
5210 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5212 // The integer check is needed for the 64-bit into 128-bit so it doesn't match
5213 // double since there is no vbroadcastsd xmm
5214 if (Subtarget->hasInt256() && Ld.getValueType().isInteger()) {
5215 if (ScalarSize == 8 || ScalarSize == 16 || ScalarSize == 64)
5216 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5219 // Unsupported broadcast.
5224 X86TargetLowering::buildFromShuffleMostly(SDValue Op, SelectionDAG &DAG) const {
5225 EVT VT = Op.getValueType();
5227 // Skip if insert_vec_elt is not supported.
5228 if (!isOperationLegalOrCustom(ISD::INSERT_VECTOR_ELT, VT))
5231 DebugLoc DL = Op.getDebugLoc();
5232 unsigned NumElems = Op.getNumOperands();
5236 SmallVector<unsigned, 4> InsertIndices;
5237 SmallVector<int, 8> Mask(NumElems, -1);
5239 for (unsigned i = 0; i != NumElems; ++i) {
5240 unsigned Opc = Op.getOperand(i).getOpcode();
5242 if (Opc == ISD::UNDEF)
5245 if (Opc != ISD::EXTRACT_VECTOR_ELT) {
5246 // Quit if more than 1 elements need inserting.
5247 if (InsertIndices.size() > 1)
5250 InsertIndices.push_back(i);
5254 SDValue ExtractedFromVec = Op.getOperand(i).getOperand(0);
5255 SDValue ExtIdx = Op.getOperand(i).getOperand(1);
5257 // Quit if extracted from vector of different type.
5258 if (ExtractedFromVec.getValueType() != VT)
5261 // Quit if non-constant index.
5262 if (!isa<ConstantSDNode>(ExtIdx))
5265 if (VecIn1.getNode() == 0)
5266 VecIn1 = ExtractedFromVec;
5267 else if (VecIn1 != ExtractedFromVec) {
5268 if (VecIn2.getNode() == 0)
5269 VecIn2 = ExtractedFromVec;
5270 else if (VecIn2 != ExtractedFromVec)
5271 // Quit if more than 2 vectors to shuffle
5275 unsigned Idx = cast<ConstantSDNode>(ExtIdx)->getZExtValue();
5277 if (ExtractedFromVec == VecIn1)
5279 else if (ExtractedFromVec == VecIn2)
5280 Mask[i] = Idx + NumElems;
5283 if (VecIn1.getNode() == 0)
5286 VecIn2 = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT);
5287 SDValue NV = DAG.getVectorShuffle(VT, DL, VecIn1, VecIn2, &Mask[0]);
5288 for (unsigned i = 0, e = InsertIndices.size(); i != e; ++i) {
5289 unsigned Idx = InsertIndices[i];
5290 NV = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VT, NV, Op.getOperand(Idx),
5291 DAG.getIntPtrConstant(Idx));
5298 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
5299 DebugLoc dl = Op.getDebugLoc();
5301 EVT VT = Op.getValueType();
5302 EVT ExtVT = VT.getVectorElementType();
5303 unsigned NumElems = Op.getNumOperands();
5305 // Vectors containing all zeros can be matched by pxor and xorps later
5306 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
5307 // Canonicalize this to <4 x i32> to 1) ensure the zero vectors are CSE'd
5308 // and 2) ensure that i64 scalars are eliminated on x86-32 hosts.
5309 if (VT == MVT::v4i32 || VT == MVT::v8i32)
5312 return getZeroVector(VT, Subtarget, DAG, dl);
5315 // Vectors containing all ones can be matched by pcmpeqd on 128-bit width
5316 // vectors or broken into v4i32 operations on 256-bit vectors. AVX2 can use
5317 // vpcmpeqd on 256-bit vectors.
5318 if (ISD::isBuildVectorAllOnes(Op.getNode())) {
5319 if (VT == MVT::v4i32 || (VT == MVT::v8i32 && Subtarget->hasInt256()))
5322 return getOnesVector(VT, Subtarget->hasInt256(), DAG, dl);
5325 SDValue Broadcast = LowerVectorBroadcast(Op, DAG);
5326 if (Broadcast.getNode())
5329 unsigned EVTBits = ExtVT.getSizeInBits();
5331 unsigned NumZero = 0;
5332 unsigned NumNonZero = 0;
5333 unsigned NonZeros = 0;
5334 bool IsAllConstants = true;
5335 SmallSet<SDValue, 8> Values;
5336 for (unsigned i = 0; i < NumElems; ++i) {
5337 SDValue Elt = Op.getOperand(i);
5338 if (Elt.getOpcode() == ISD::UNDEF)
5341 if (Elt.getOpcode() != ISD::Constant &&
5342 Elt.getOpcode() != ISD::ConstantFP)
5343 IsAllConstants = false;
5344 if (X86::isZeroNode(Elt))
5347 NonZeros |= (1 << i);
5352 // All undef vector. Return an UNDEF. All zero vectors were handled above.
5353 if (NumNonZero == 0)
5354 return DAG.getUNDEF(VT);
5356 // Special case for single non-zero, non-undef, element.
5357 if (NumNonZero == 1) {
5358 unsigned Idx = CountTrailingZeros_32(NonZeros);
5359 SDValue Item = Op.getOperand(Idx);
5361 // If this is an insertion of an i64 value on x86-32, and if the top bits of
5362 // the value are obviously zero, truncate the value to i32 and do the
5363 // insertion that way. Only do this if the value is non-constant or if the
5364 // value is a constant being inserted into element 0. It is cheaper to do
5365 // a constant pool load than it is to do a movd + shuffle.
5366 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
5367 (!IsAllConstants || Idx == 0)) {
5368 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
5370 assert(VT == MVT::v2i64 && "Expected an SSE value type!");
5371 EVT VecVT = MVT::v4i32;
5372 unsigned VecElts = 4;
5374 // Truncate the value (which may itself be a constant) to i32, and
5375 // convert it to a vector with movd (S2V+shuffle to zero extend).
5376 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
5377 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
5378 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
5380 // Now we have our 32-bit value zero extended in the low element of
5381 // a vector. If Idx != 0, swizzle it into place.
5383 SmallVector<int, 4> Mask;
5384 Mask.push_back(Idx);
5385 for (unsigned i = 1; i != VecElts; ++i)
5387 Item = DAG.getVectorShuffle(VecVT, dl, Item, DAG.getUNDEF(VecVT),
5390 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
5394 // If we have a constant or non-constant insertion into the low element of
5395 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
5396 // the rest of the elements. This will be matched as movd/movq/movss/movsd
5397 // depending on what the source datatype is.
5400 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5402 if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
5403 (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
5404 if (VT.is256BitVector()) {
5405 SDValue ZeroVec = getZeroVector(VT, Subtarget, DAG, dl);
5406 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, ZeroVec,
5407 Item, DAG.getIntPtrConstant(0));
5409 assert(VT.is128BitVector() && "Expected an SSE value type!");
5410 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5411 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
5412 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
5415 if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
5416 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
5417 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
5418 if (VT.is256BitVector()) {
5419 SDValue ZeroVec = getZeroVector(MVT::v8i32, Subtarget, DAG, dl);
5420 Item = Insert128BitVector(ZeroVec, Item, 0, DAG, dl);
5422 assert(VT.is128BitVector() && "Expected an SSE value type!");
5423 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
5425 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
5429 // Is it a vector logical left shift?
5430 if (NumElems == 2 && Idx == 1 &&
5431 X86::isZeroNode(Op.getOperand(0)) &&
5432 !X86::isZeroNode(Op.getOperand(1))) {
5433 unsigned NumBits = VT.getSizeInBits();
5434 return getVShift(true, VT,
5435 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
5436 VT, Op.getOperand(1)),
5437 NumBits/2, DAG, *this, dl);
5440 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
5443 // Otherwise, if this is a vector with i32 or f32 elements, and the element
5444 // is a non-constant being inserted into an element other than the low one,
5445 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
5446 // movd/movss) to move this into the low element, then shuffle it into
5448 if (EVTBits == 32) {
5449 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5451 // Turn it into a shuffle of zero and zero-extended scalar to vector.
5452 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0, Subtarget, DAG);
5453 SmallVector<int, 8> MaskVec;
5454 for (unsigned i = 0; i != NumElems; ++i)
5455 MaskVec.push_back(i == Idx ? 0 : 1);
5456 return DAG.getVectorShuffle(VT, dl, Item, DAG.getUNDEF(VT), &MaskVec[0]);
5460 // Splat is obviously ok. Let legalizer expand it to a shuffle.
5461 if (Values.size() == 1) {
5462 if (EVTBits == 32) {
5463 // Instead of a shuffle like this:
5464 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
5465 // Check if it's possible to issue this instead.
5466 // shuffle (vload ptr)), undef, <1, 1, 1, 1>
5467 unsigned Idx = CountTrailingZeros_32(NonZeros);
5468 SDValue Item = Op.getOperand(Idx);
5469 if (Op.getNode()->isOnlyUserOf(Item.getNode()))
5470 return LowerAsSplatVectorLoad(Item, VT, dl, DAG);
5475 // A vector full of immediates; various special cases are already
5476 // handled, so this is best done with a single constant-pool load.
5480 // For AVX-length vectors, build the individual 128-bit pieces and use
5481 // shuffles to put them in place.
5482 if (VT.is256BitVector()) {
5483 SmallVector<SDValue, 32> V;
5484 for (unsigned i = 0; i != NumElems; ++i)
5485 V.push_back(Op.getOperand(i));
5487 EVT HVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems/2);
5489 // Build both the lower and upper subvector.
5490 SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT, &V[0], NumElems/2);
5491 SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT, &V[NumElems / 2],
5494 // Recreate the wider vector with the lower and upper part.
5495 return Concat128BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
5498 // Let legalizer expand 2-wide build_vectors.
5499 if (EVTBits == 64) {
5500 if (NumNonZero == 1) {
5501 // One half is zero or undef.
5502 unsigned Idx = CountTrailingZeros_32(NonZeros);
5503 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
5504 Op.getOperand(Idx));
5505 return getShuffleVectorZeroOrUndef(V2, Idx, true, Subtarget, DAG);
5510 // If element VT is < 32 bits, convert it to inserts into a zero vector.
5511 if (EVTBits == 8 && NumElems == 16) {
5512 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
5514 if (V.getNode()) return V;
5517 if (EVTBits == 16 && NumElems == 8) {
5518 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
5520 if (V.getNode()) return V;
5523 // If element VT is == 32 bits, turn it into a number of shuffles.
5524 SmallVector<SDValue, 8> V(NumElems);
5525 if (NumElems == 4 && NumZero > 0) {
5526 for (unsigned i = 0; i < 4; ++i) {
5527 bool isZero = !(NonZeros & (1 << i));
5529 V[i] = getZeroVector(VT, Subtarget, DAG, dl);
5531 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
5534 for (unsigned i = 0; i < 2; ++i) {
5535 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
5538 V[i] = V[i*2]; // Must be a zero vector.
5541 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
5544 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
5547 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
5552 bool Reverse1 = (NonZeros & 0x3) == 2;
5553 bool Reverse2 = ((NonZeros & (0x3 << 2)) >> 2) == 2;
5557 static_cast<int>(Reverse2 ? NumElems+1 : NumElems),
5558 static_cast<int>(Reverse2 ? NumElems : NumElems+1)
5560 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
5563 if (Values.size() > 1 && VT.is128BitVector()) {
5564 // Check for a build vector of consecutive loads.
5565 for (unsigned i = 0; i < NumElems; ++i)
5566 V[i] = Op.getOperand(i);
5568 // Check for elements which are consecutive loads.
5569 SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG);
5573 // Check for a build vector from mostly shuffle plus few inserting.
5574 SDValue Sh = buildFromShuffleMostly(Op, DAG);
5578 // For SSE 4.1, use insertps to put the high elements into the low element.
5579 if (getSubtarget()->hasSSE41()) {
5581 if (Op.getOperand(0).getOpcode() != ISD::UNDEF)
5582 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0));
5584 Result = DAG.getUNDEF(VT);
5586 for (unsigned i = 1; i < NumElems; ++i) {
5587 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue;
5588 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result,
5589 Op.getOperand(i), DAG.getIntPtrConstant(i));
5594 // Otherwise, expand into a number of unpckl*, start by extending each of
5595 // our (non-undef) elements to the full vector width with the element in the
5596 // bottom slot of the vector (which generates no code for SSE).
5597 for (unsigned i = 0; i < NumElems; ++i) {
5598 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
5599 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
5601 V[i] = DAG.getUNDEF(VT);
5604 // Next, we iteratively mix elements, e.g. for v4f32:
5605 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
5606 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
5607 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
5608 unsigned EltStride = NumElems >> 1;
5609 while (EltStride != 0) {
5610 for (unsigned i = 0; i < EltStride; ++i) {
5611 // If V[i+EltStride] is undef and this is the first round of mixing,
5612 // then it is safe to just drop this shuffle: V[i] is already in the
5613 // right place, the one element (since it's the first round) being
5614 // inserted as undef can be dropped. This isn't safe for successive
5615 // rounds because they will permute elements within both vectors.
5616 if (V[i+EltStride].getOpcode() == ISD::UNDEF &&
5617 EltStride == NumElems/2)
5620 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]);
5629 // LowerAVXCONCAT_VECTORS - 256-bit AVX can use the vinsertf128 instruction
5630 // to create 256-bit vectors from two other 128-bit ones.
5631 static SDValue LowerAVXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
5632 DebugLoc dl = Op.getDebugLoc();
5633 EVT ResVT = Op.getValueType();
5635 assert(ResVT.is256BitVector() && "Value type must be 256-bit wide");
5637 SDValue V1 = Op.getOperand(0);
5638 SDValue V2 = Op.getOperand(1);
5639 unsigned NumElems = ResVT.getVectorNumElements();
5641 return Concat128BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
5644 static SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
5645 assert(Op.getNumOperands() == 2);
5647 // 256-bit AVX can use the vinsertf128 instruction to create 256-bit vectors
5648 // from two other 128-bit ones.
5649 return LowerAVXCONCAT_VECTORS(Op, DAG);
5652 // Try to lower a shuffle node into a simple blend instruction.
5654 LowerVECTOR_SHUFFLEtoBlend(ShuffleVectorSDNode *SVOp,
5655 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
5656 SDValue V1 = SVOp->getOperand(0);
5657 SDValue V2 = SVOp->getOperand(1);
5658 DebugLoc dl = SVOp->getDebugLoc();
5659 EVT VT = SVOp->getValueType(0);
5660 EVT EltVT = VT.getVectorElementType();
5661 unsigned NumElems = VT.getVectorNumElements();
5663 if (!Subtarget->hasSSE41() || EltVT == MVT::i8)
5665 if (!Subtarget->hasInt256() && VT == MVT::v16i16)
5668 // Check the mask for BLEND and build the value.
5669 unsigned MaskValue = 0;
5670 // There are 2 lanes if (NumElems > 8), and 1 lane otherwise.
5671 unsigned NumLanes = (NumElems-1)/8 + 1;
5672 unsigned NumElemsInLane = NumElems / NumLanes;
5674 // Blend for v16i16 should be symetric for the both lanes.
5675 for (unsigned i = 0; i < NumElemsInLane; ++i) {
5677 int SndLaneEltIdx = (NumLanes == 2) ?
5678 SVOp->getMaskElt(i + NumElemsInLane) : -1;
5679 int EltIdx = SVOp->getMaskElt(i);
5681 if ((EltIdx == -1 || EltIdx == (int)i) &&
5682 (SndLaneEltIdx == -1 || SndLaneEltIdx == (int)(i + NumElemsInLane)))
5685 if (((unsigned)EltIdx == (i + NumElems)) &&
5686 (SndLaneEltIdx == -1 ||
5687 (unsigned)SndLaneEltIdx == i + NumElems + NumElemsInLane))
5688 MaskValue |= (1<<i);
5693 // Convert i32 vectors to floating point if it is not AVX2.
5694 // AVX2 introduced VPBLENDD instruction for 128 and 256-bit vectors.
5696 if (EltVT == MVT::i64 || (EltVT == MVT::i32 && !Subtarget->hasInt256())) {
5697 BlendVT = EVT::getVectorVT(*DAG.getContext(),
5698 EVT::getFloatingPointVT(EltVT.getSizeInBits()),
5700 V1 = DAG.getNode(ISD::BITCAST, dl, VT, V1);
5701 V2 = DAG.getNode(ISD::BITCAST, dl, VT, V2);
5704 SDValue Ret = DAG.getNode(X86ISD::BLENDI, dl, BlendVT, V1, V2,
5705 DAG.getConstant(MaskValue, MVT::i32));
5706 return DAG.getNode(ISD::BITCAST, dl, VT, Ret);
5709 // v8i16 shuffles - Prefer shuffles in the following order:
5710 // 1. [all] pshuflw, pshufhw, optional move
5711 // 2. [ssse3] 1 x pshufb
5712 // 3. [ssse3] 2 x pshufb + 1 x por
5713 // 4. [all] mov + pshuflw + pshufhw + N x (pextrw + pinsrw)
5715 LowerVECTOR_SHUFFLEv8i16(SDValue Op, const X86Subtarget *Subtarget,
5716 SelectionDAG &DAG) {
5717 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
5718 SDValue V1 = SVOp->getOperand(0);
5719 SDValue V2 = SVOp->getOperand(1);
5720 DebugLoc dl = SVOp->getDebugLoc();
5721 SmallVector<int, 8> MaskVals;
5723 // Determine if more than 1 of the words in each of the low and high quadwords
5724 // of the result come from the same quadword of one of the two inputs. Undef
5725 // mask values count as coming from any quadword, for better codegen.
5726 unsigned LoQuad[] = { 0, 0, 0, 0 };
5727 unsigned HiQuad[] = { 0, 0, 0, 0 };
5728 std::bitset<4> InputQuads;
5729 for (unsigned i = 0; i < 8; ++i) {
5730 unsigned *Quad = i < 4 ? LoQuad : HiQuad;
5731 int EltIdx = SVOp->getMaskElt(i);
5732 MaskVals.push_back(EltIdx);
5741 InputQuads.set(EltIdx / 4);
5744 int BestLoQuad = -1;
5745 unsigned MaxQuad = 1;
5746 for (unsigned i = 0; i < 4; ++i) {
5747 if (LoQuad[i] > MaxQuad) {
5749 MaxQuad = LoQuad[i];
5753 int BestHiQuad = -1;
5755 for (unsigned i = 0; i < 4; ++i) {
5756 if (HiQuad[i] > MaxQuad) {
5758 MaxQuad = HiQuad[i];
5762 // For SSSE3, If all 8 words of the result come from only 1 quadword of each
5763 // of the two input vectors, shuffle them into one input vector so only a
5764 // single pshufb instruction is necessary. If There are more than 2 input
5765 // quads, disable the next transformation since it does not help SSSE3.
5766 bool V1Used = InputQuads[0] || InputQuads[1];
5767 bool V2Used = InputQuads[2] || InputQuads[3];
5768 if (Subtarget->hasSSSE3()) {
5769 if (InputQuads.count() == 2 && V1Used && V2Used) {
5770 BestLoQuad = InputQuads[0] ? 0 : 1;
5771 BestHiQuad = InputQuads[2] ? 2 : 3;
5773 if (InputQuads.count() > 2) {
5779 // If BestLoQuad or BestHiQuad are set, shuffle the quads together and update
5780 // the shuffle mask. If a quad is scored as -1, that means that it contains
5781 // words from all 4 input quadwords.
5783 if (BestLoQuad >= 0 || BestHiQuad >= 0) {
5785 BestLoQuad < 0 ? 0 : BestLoQuad,
5786 BestHiQuad < 0 ? 1 : BestHiQuad
5788 NewV = DAG.getVectorShuffle(MVT::v2i64, dl,
5789 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V1),
5790 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V2), &MaskV[0]);
5791 NewV = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, NewV);
5793 // Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the
5794 // source words for the shuffle, to aid later transformations.
5795 bool AllWordsInNewV = true;
5796 bool InOrder[2] = { true, true };
5797 for (unsigned i = 0; i != 8; ++i) {
5798 int idx = MaskVals[i];
5800 InOrder[i/4] = false;
5801 if (idx < 0 || (idx/4) == BestLoQuad || (idx/4) == BestHiQuad)
5803 AllWordsInNewV = false;
5807 bool pshuflw = AllWordsInNewV, pshufhw = AllWordsInNewV;
5808 if (AllWordsInNewV) {
5809 for (int i = 0; i != 8; ++i) {
5810 int idx = MaskVals[i];
5813 idx = MaskVals[i] = (idx / 4) == BestLoQuad ? (idx & 3) : (idx & 3) + 4;
5814 if ((idx != i) && idx < 4)
5816 if ((idx != i) && idx > 3)
5825 // If we've eliminated the use of V2, and the new mask is a pshuflw or
5826 // pshufhw, that's as cheap as it gets. Return the new shuffle.
5827 if ((pshufhw && InOrder[0]) || (pshuflw && InOrder[1])) {
5828 unsigned Opc = pshufhw ? X86ISD::PSHUFHW : X86ISD::PSHUFLW;
5829 unsigned TargetMask = 0;
5830 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV,
5831 DAG.getUNDEF(MVT::v8i16), &MaskVals[0]);
5832 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
5833 TargetMask = pshufhw ? getShufflePSHUFHWImmediate(SVOp):
5834 getShufflePSHUFLWImmediate(SVOp);
5835 V1 = NewV.getOperand(0);
5836 return getTargetShuffleNode(Opc, dl, MVT::v8i16, V1, TargetMask, DAG);
5840 // If we have SSSE3, and all words of the result are from 1 input vector,
5841 // case 2 is generated, otherwise case 3 is generated. If no SSSE3
5842 // is present, fall back to case 4.
5843 if (Subtarget->hasSSSE3()) {
5844 SmallVector<SDValue,16> pshufbMask;
5846 // If we have elements from both input vectors, set the high bit of the
5847 // shuffle mask element to zero out elements that come from V2 in the V1
5848 // mask, and elements that come from V1 in the V2 mask, so that the two
5849 // results can be OR'd together.
5850 bool TwoInputs = V1Used && V2Used;
5851 for (unsigned i = 0; i != 8; ++i) {
5852 int EltIdx = MaskVals[i] * 2;
5853 int Idx0 = (TwoInputs && (EltIdx >= 16)) ? 0x80 : EltIdx;
5854 int Idx1 = (TwoInputs && (EltIdx >= 16)) ? 0x80 : EltIdx+1;
5855 pshufbMask.push_back(DAG.getConstant(Idx0, MVT::i8));
5856 pshufbMask.push_back(DAG.getConstant(Idx1, MVT::i8));
5858 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V1);
5859 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
5860 DAG.getNode(ISD::BUILD_VECTOR, dl,
5861 MVT::v16i8, &pshufbMask[0], 16));
5863 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
5865 // Calculate the shuffle mask for the second input, shuffle it, and
5866 // OR it with the first shuffled input.
5868 for (unsigned i = 0; i != 8; ++i) {
5869 int EltIdx = MaskVals[i] * 2;
5870 int Idx0 = (EltIdx < 16) ? 0x80 : EltIdx - 16;
5871 int Idx1 = (EltIdx < 16) ? 0x80 : EltIdx - 15;
5872 pshufbMask.push_back(DAG.getConstant(Idx0, MVT::i8));
5873 pshufbMask.push_back(DAG.getConstant(Idx1, MVT::i8));
5875 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V2);
5876 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
5877 DAG.getNode(ISD::BUILD_VECTOR, dl,
5878 MVT::v16i8, &pshufbMask[0], 16));
5879 V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
5880 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
5883 // If BestLoQuad >= 0, generate a pshuflw to put the low elements in order,
5884 // and update MaskVals with new element order.
5885 std::bitset<8> InOrder;
5886 if (BestLoQuad >= 0) {
5887 int MaskV[] = { -1, -1, -1, -1, 4, 5, 6, 7 };
5888 for (int i = 0; i != 4; ++i) {
5889 int idx = MaskVals[i];
5892 } else if ((idx / 4) == BestLoQuad) {
5897 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
5900 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSSE3()) {
5901 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
5902 NewV = getTargetShuffleNode(X86ISD::PSHUFLW, dl, MVT::v8i16,
5904 getShufflePSHUFLWImmediate(SVOp), DAG);
5908 // If BestHi >= 0, generate a pshufhw to put the high elements in order,
5909 // and update MaskVals with the new element order.
5910 if (BestHiQuad >= 0) {
5911 int MaskV[] = { 0, 1, 2, 3, -1, -1, -1, -1 };
5912 for (unsigned i = 4; i != 8; ++i) {
5913 int idx = MaskVals[i];
5916 } else if ((idx / 4) == BestHiQuad) {
5917 MaskV[i] = (idx & 3) + 4;
5921 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
5924 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSSE3()) {
5925 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
5926 NewV = getTargetShuffleNode(X86ISD::PSHUFHW, dl, MVT::v8i16,
5928 getShufflePSHUFHWImmediate(SVOp), DAG);
5932 // In case BestHi & BestLo were both -1, which means each quadword has a word
5933 // from each of the four input quadwords, calculate the InOrder bitvector now
5934 // before falling through to the insert/extract cleanup.
5935 if (BestLoQuad == -1 && BestHiQuad == -1) {
5937 for (int i = 0; i != 8; ++i)
5938 if (MaskVals[i] < 0 || MaskVals[i] == i)
5942 // The other elements are put in the right place using pextrw and pinsrw.
5943 for (unsigned i = 0; i != 8; ++i) {
5946 int EltIdx = MaskVals[i];
5949 SDValue ExtOp = (EltIdx < 8) ?
5950 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1,
5951 DAG.getIntPtrConstant(EltIdx)) :
5952 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2,
5953 DAG.getIntPtrConstant(EltIdx - 8));
5954 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp,
5955 DAG.getIntPtrConstant(i));
5960 // v16i8 shuffles - Prefer shuffles in the following order:
5961 // 1. [ssse3] 1 x pshufb
5962 // 2. [ssse3] 2 x pshufb + 1 x por
5963 // 3. [all] v8i16 shuffle + N x pextrw + rotate + pinsrw
5965 SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp,
5967 const X86TargetLowering &TLI) {
5968 SDValue V1 = SVOp->getOperand(0);
5969 SDValue V2 = SVOp->getOperand(1);
5970 DebugLoc dl = SVOp->getDebugLoc();
5971 ArrayRef<int> MaskVals = SVOp->getMask();
5973 // If we have SSSE3, case 1 is generated when all result bytes come from
5974 // one of the inputs. Otherwise, case 2 is generated. If no SSSE3 is
5975 // present, fall back to case 3.
5977 // If SSSE3, use 1 pshufb instruction per vector with elements in the result.
5978 if (TLI.getSubtarget()->hasSSSE3()) {
5979 SmallVector<SDValue,16> pshufbMask;
5981 // If all result elements are from one input vector, then only translate
5982 // undef mask values to 0x80 (zero out result) in the pshufb mask.
5984 // Otherwise, we have elements from both input vectors, and must zero out
5985 // elements that come from V2 in the first mask, and V1 in the second mask
5986 // so that we can OR them together.
5987 for (unsigned i = 0; i != 16; ++i) {
5988 int EltIdx = MaskVals[i];
5989 if (EltIdx < 0 || EltIdx >= 16)
5991 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
5993 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
5994 DAG.getNode(ISD::BUILD_VECTOR, dl,
5995 MVT::v16i8, &pshufbMask[0], 16));
5997 // As PSHUFB will zero elements with negative indices, it's safe to ignore
5998 // the 2nd operand if it's undefined or zero.
5999 if (V2.getOpcode() == ISD::UNDEF ||
6000 ISD::isBuildVectorAllZeros(V2.getNode()))
6003 // Calculate the shuffle mask for the second input, shuffle it, and
6004 // OR it with the first shuffled input.
6006 for (unsigned i = 0; i != 16; ++i) {
6007 int EltIdx = MaskVals[i];
6008 EltIdx = (EltIdx < 16) ? 0x80 : EltIdx - 16;
6009 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
6011 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
6012 DAG.getNode(ISD::BUILD_VECTOR, dl,
6013 MVT::v16i8, &pshufbMask[0], 16));
6014 return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
6017 // No SSSE3 - Calculate in place words and then fix all out of place words
6018 // With 0-16 extracts & inserts. Worst case is 16 bytes out of order from
6019 // the 16 different words that comprise the two doublequadword input vectors.
6020 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
6021 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V2);
6023 for (int i = 0; i != 8; ++i) {
6024 int Elt0 = MaskVals[i*2];
6025 int Elt1 = MaskVals[i*2+1];
6027 // This word of the result is all undef, skip it.
6028 if (Elt0 < 0 && Elt1 < 0)
6031 // This word of the result is already in the correct place, skip it.
6032 if ((Elt0 == i*2) && (Elt1 == i*2+1))
6035 SDValue Elt0Src = Elt0 < 16 ? V1 : V2;
6036 SDValue Elt1Src = Elt1 < 16 ? V1 : V2;
6039 // If Elt0 and Elt1 are defined, are consecutive, and can be load
6040 // using a single extract together, load it and store it.
6041 if ((Elt0 >= 0) && ((Elt0 + 1) == Elt1) && ((Elt0 & 1) == 0)) {
6042 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
6043 DAG.getIntPtrConstant(Elt1 / 2));
6044 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
6045 DAG.getIntPtrConstant(i));
6049 // If Elt1 is defined, extract it from the appropriate source. If the
6050 // source byte is not also odd, shift the extracted word left 8 bits
6051 // otherwise clear the bottom 8 bits if we need to do an or.
6053 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
6054 DAG.getIntPtrConstant(Elt1 / 2));
6055 if ((Elt1 & 1) == 0)
6056 InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt,
6058 TLI.getShiftAmountTy(InsElt.getValueType())));
6060 InsElt = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt,
6061 DAG.getConstant(0xFF00, MVT::i16));
6063 // If Elt0 is defined, extract it from the appropriate source. If the
6064 // source byte is not also even, shift the extracted word right 8 bits. If
6065 // Elt1 was also defined, OR the extracted values together before
6066 // inserting them in the result.
6068 SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16,
6069 Elt0Src, DAG.getIntPtrConstant(Elt0 / 2));
6070 if ((Elt0 & 1) != 0)
6071 InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0,
6073 TLI.getShiftAmountTy(InsElt0.getValueType())));
6075 InsElt0 = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt0,
6076 DAG.getConstant(0x00FF, MVT::i16));
6077 InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0)
6080 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
6081 DAG.getIntPtrConstant(i));
6083 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, NewV);
6086 // v32i8 shuffles - Translate to VPSHUFB if possible.
6088 SDValue LowerVECTOR_SHUFFLEv32i8(ShuffleVectorSDNode *SVOp,
6089 const X86Subtarget *Subtarget,
6090 SelectionDAG &DAG) {
6091 EVT VT = SVOp->getValueType(0);
6092 SDValue V1 = SVOp->getOperand(0);
6093 SDValue V2 = SVOp->getOperand(1);
6094 DebugLoc dl = SVOp->getDebugLoc();
6095 SmallVector<int, 32> MaskVals(SVOp->getMask().begin(), SVOp->getMask().end());
6097 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
6098 bool V1IsAllZero = ISD::isBuildVectorAllZeros(V1.getNode());
6099 bool V2IsAllZero = ISD::isBuildVectorAllZeros(V2.getNode());
6101 // VPSHUFB may be generated if
6102 // (1) one of input vector is undefined or zeroinitializer.
6103 // The mask value 0x80 puts 0 in the corresponding slot of the vector.
6104 // And (2) the mask indexes don't cross the 128-bit lane.
6105 if (VT != MVT::v32i8 || !Subtarget->hasInt256() ||
6106 (!V2IsUndef && !V2IsAllZero && !V1IsAllZero))
6109 if (V1IsAllZero && !V2IsAllZero) {
6110 CommuteVectorShuffleMask(MaskVals, 32);
6113 SmallVector<SDValue, 32> pshufbMask;
6114 for (unsigned i = 0; i != 32; i++) {
6115 int EltIdx = MaskVals[i];
6116 if (EltIdx < 0 || EltIdx >= 32)
6119 if ((EltIdx >= 16 && i < 16) || (EltIdx < 16 && i >= 16))
6120 // Cross lane is not allowed.
6124 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
6126 return DAG.getNode(X86ISD::PSHUFB, dl, MVT::v32i8, V1,
6127 DAG.getNode(ISD::BUILD_VECTOR, dl,
6128 MVT::v32i8, &pshufbMask[0], 32));
6131 /// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide
6132 /// ones, or rewriting v4i32 / v4f32 as 2 wide ones if possible. This can be
6133 /// done when every pair / quad of shuffle mask elements point to elements in
6134 /// the right sequence. e.g.
6135 /// vector_shuffle X, Y, <2, 3, | 10, 11, | 0, 1, | 14, 15>
6137 SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp,
6138 SelectionDAG &DAG, DebugLoc dl) {
6139 MVT VT = SVOp->getValueType(0).getSimpleVT();
6140 unsigned NumElems = VT.getVectorNumElements();
6143 switch (VT.SimpleTy) {
6144 default: llvm_unreachable("Unexpected!");
6145 case MVT::v4f32: NewVT = MVT::v2f64; Scale = 2; break;
6146 case MVT::v4i32: NewVT = MVT::v2i64; Scale = 2; break;
6147 case MVT::v8i16: NewVT = MVT::v4i32; Scale = 2; break;
6148 case MVT::v16i8: NewVT = MVT::v4i32; Scale = 4; break;
6149 case MVT::v16i16: NewVT = MVT::v8i32; Scale = 2; break;
6150 case MVT::v32i8: NewVT = MVT::v8i32; Scale = 4; break;
6153 SmallVector<int, 8> MaskVec;
6154 for (unsigned i = 0; i != NumElems; i += Scale) {
6156 for (unsigned j = 0; j != Scale; ++j) {
6157 int EltIdx = SVOp->getMaskElt(i+j);
6161 StartIdx = (EltIdx / Scale);
6162 if (EltIdx != (int)(StartIdx*Scale + j))
6165 MaskVec.push_back(StartIdx);
6168 SDValue V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(0));
6169 SDValue V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(1));
6170 return DAG.getVectorShuffle(NewVT, dl, V1, V2, &MaskVec[0]);
6173 /// getVZextMovL - Return a zero-extending vector move low node.
6175 static SDValue getVZextMovL(EVT VT, EVT OpVT,
6176 SDValue SrcOp, SelectionDAG &DAG,
6177 const X86Subtarget *Subtarget, DebugLoc dl) {
6178 if (VT == MVT::v2f64 || VT == MVT::v4f32) {
6179 LoadSDNode *LD = NULL;
6180 if (!isScalarLoadToVector(SrcOp.getNode(), &LD))
6181 LD = dyn_cast<LoadSDNode>(SrcOp);
6183 // movssrr and movsdrr do not clear top bits. Try to use movd, movq
6185 MVT ExtVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32;
6186 if ((ExtVT != MVT::i64 || Subtarget->is64Bit()) &&
6187 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR &&
6188 SrcOp.getOperand(0).getOpcode() == ISD::BITCAST &&
6189 SrcOp.getOperand(0).getOperand(0).getValueType() == ExtVT) {
6191 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32;
6192 return DAG.getNode(ISD::BITCAST, dl, VT,
6193 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
6194 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
6202 return DAG.getNode(ISD::BITCAST, dl, VT,
6203 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
6204 DAG.getNode(ISD::BITCAST, dl,
6208 /// LowerVECTOR_SHUFFLE_256 - Handle all 256-bit wide vectors shuffles
6209 /// which could not be matched by any known target speficic shuffle
6211 LowerVECTOR_SHUFFLE_256(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
6213 SDValue NewOp = Compact8x32ShuffleNode(SVOp, DAG);
6214 if (NewOp.getNode())
6217 EVT VT = SVOp->getValueType(0);
6219 unsigned NumElems = VT.getVectorNumElements();
6220 unsigned NumLaneElems = NumElems / 2;
6222 DebugLoc dl = SVOp->getDebugLoc();
6223 MVT EltVT = VT.getVectorElementType().getSimpleVT();
6224 EVT NVT = MVT::getVectorVT(EltVT, NumLaneElems);
6227 SmallVector<int, 16> Mask;
6228 for (unsigned l = 0; l < 2; ++l) {
6229 // Build a shuffle mask for the output, discovering on the fly which
6230 // input vectors to use as shuffle operands (recorded in InputUsed).
6231 // If building a suitable shuffle vector proves too hard, then bail
6232 // out with UseBuildVector set.
6233 bool UseBuildVector = false;
6234 int InputUsed[2] = { -1, -1 }; // Not yet discovered.
6235 unsigned LaneStart = l * NumLaneElems;
6236 for (unsigned i = 0; i != NumLaneElems; ++i) {
6237 // The mask element. This indexes into the input.
6238 int Idx = SVOp->getMaskElt(i+LaneStart);
6240 // the mask element does not index into any input vector.
6245 // The input vector this mask element indexes into.
6246 int Input = Idx / NumLaneElems;
6248 // Turn the index into an offset from the start of the input vector.
6249 Idx -= Input * NumLaneElems;
6251 // Find or create a shuffle vector operand to hold this input.
6253 for (OpNo = 0; OpNo < array_lengthof(InputUsed); ++OpNo) {
6254 if (InputUsed[OpNo] == Input)
6255 // This input vector is already an operand.
6257 if (InputUsed[OpNo] < 0) {
6258 // Create a new operand for this input vector.
6259 InputUsed[OpNo] = Input;
6264 if (OpNo >= array_lengthof(InputUsed)) {
6265 // More than two input vectors used! Give up on trying to create a
6266 // shuffle vector. Insert all elements into a BUILD_VECTOR instead.
6267 UseBuildVector = true;
6271 // Add the mask index for the new shuffle vector.
6272 Mask.push_back(Idx + OpNo * NumLaneElems);
6275 if (UseBuildVector) {
6276 SmallVector<SDValue, 16> SVOps;
6277 for (unsigned i = 0; i != NumLaneElems; ++i) {
6278 // The mask element. This indexes into the input.
6279 int Idx = SVOp->getMaskElt(i+LaneStart);
6281 SVOps.push_back(DAG.getUNDEF(EltVT));
6285 // The input vector this mask element indexes into.
6286 int Input = Idx / NumElems;
6288 // Turn the index into an offset from the start of the input vector.
6289 Idx -= Input * NumElems;
6291 // Extract the vector element by hand.
6292 SVOps.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
6293 SVOp->getOperand(Input),
6294 DAG.getIntPtrConstant(Idx)));
6297 // Construct the output using a BUILD_VECTOR.
6298 Output[l] = DAG.getNode(ISD::BUILD_VECTOR, dl, NVT, &SVOps[0],
6300 } else if (InputUsed[0] < 0) {
6301 // No input vectors were used! The result is undefined.
6302 Output[l] = DAG.getUNDEF(NVT);
6304 SDValue Op0 = Extract128BitVector(SVOp->getOperand(InputUsed[0] / 2),
6305 (InputUsed[0] % 2) * NumLaneElems,
6307 // If only one input was used, use an undefined vector for the other.
6308 SDValue Op1 = (InputUsed[1] < 0) ? DAG.getUNDEF(NVT) :
6309 Extract128BitVector(SVOp->getOperand(InputUsed[1] / 2),
6310 (InputUsed[1] % 2) * NumLaneElems, DAG, dl);
6311 // At least one input vector was used. Create a new shuffle vector.
6312 Output[l] = DAG.getVectorShuffle(NVT, dl, Op0, Op1, &Mask[0]);
6318 // Concatenate the result back
6319 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, Output[0], Output[1]);
6322 /// LowerVECTOR_SHUFFLE_128v4 - Handle all 128-bit wide vectors with
6323 /// 4 elements, and match them with several different shuffle types.
6325 LowerVECTOR_SHUFFLE_128v4(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
6326 SDValue V1 = SVOp->getOperand(0);
6327 SDValue V2 = SVOp->getOperand(1);
6328 DebugLoc dl = SVOp->getDebugLoc();
6329 EVT VT = SVOp->getValueType(0);
6331 assert(VT.is128BitVector() && "Unsupported vector size");
6333 std::pair<int, int> Locs[4];
6334 int Mask1[] = { -1, -1, -1, -1 };
6335 SmallVector<int, 8> PermMask(SVOp->getMask().begin(), SVOp->getMask().end());
6339 for (unsigned i = 0; i != 4; ++i) {
6340 int Idx = PermMask[i];
6342 Locs[i] = std::make_pair(-1, -1);
6344 assert(Idx < 8 && "Invalid VECTOR_SHUFFLE index!");
6346 Locs[i] = std::make_pair(0, NumLo);
6350 Locs[i] = std::make_pair(1, NumHi);
6352 Mask1[2+NumHi] = Idx;
6358 if (NumLo <= 2 && NumHi <= 2) {
6359 // If no more than two elements come from either vector. This can be
6360 // implemented with two shuffles. First shuffle gather the elements.
6361 // The second shuffle, which takes the first shuffle as both of its
6362 // vector operands, put the elements into the right order.
6363 V1 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
6365 int Mask2[] = { -1, -1, -1, -1 };
6367 for (unsigned i = 0; i != 4; ++i)
6368 if (Locs[i].first != -1) {
6369 unsigned Idx = (i < 2) ? 0 : 4;
6370 Idx += Locs[i].first * 2 + Locs[i].second;
6374 return DAG.getVectorShuffle(VT, dl, V1, V1, &Mask2[0]);
6377 if (NumLo == 3 || NumHi == 3) {
6378 // Otherwise, we must have three elements from one vector, call it X, and
6379 // one element from the other, call it Y. First, use a shufps to build an
6380 // intermediate vector with the one element from Y and the element from X
6381 // that will be in the same half in the final destination (the indexes don't
6382 // matter). Then, use a shufps to build the final vector, taking the half
6383 // containing the element from Y from the intermediate, and the other half
6386 // Normalize it so the 3 elements come from V1.
6387 CommuteVectorShuffleMask(PermMask, 4);
6391 // Find the element from V2.
6393 for (HiIndex = 0; HiIndex < 3; ++HiIndex) {
6394 int Val = PermMask[HiIndex];
6401 Mask1[0] = PermMask[HiIndex];
6403 Mask1[2] = PermMask[HiIndex^1];
6405 V2 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
6408 Mask1[0] = PermMask[0];
6409 Mask1[1] = PermMask[1];
6410 Mask1[2] = HiIndex & 1 ? 6 : 4;
6411 Mask1[3] = HiIndex & 1 ? 4 : 6;
6412 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
6415 Mask1[0] = HiIndex & 1 ? 2 : 0;
6416 Mask1[1] = HiIndex & 1 ? 0 : 2;
6417 Mask1[2] = PermMask[2];
6418 Mask1[3] = PermMask[3];
6423 return DAG.getVectorShuffle(VT, dl, V2, V1, &Mask1[0]);
6426 // Break it into (shuffle shuffle_hi, shuffle_lo).
6427 int LoMask[] = { -1, -1, -1, -1 };
6428 int HiMask[] = { -1, -1, -1, -1 };
6430 int *MaskPtr = LoMask;
6431 unsigned MaskIdx = 0;
6434 for (unsigned i = 0; i != 4; ++i) {
6441 int Idx = PermMask[i];
6443 Locs[i] = std::make_pair(-1, -1);
6444 } else if (Idx < 4) {
6445 Locs[i] = std::make_pair(MaskIdx, LoIdx);
6446 MaskPtr[LoIdx] = Idx;
6449 Locs[i] = std::make_pair(MaskIdx, HiIdx);
6450 MaskPtr[HiIdx] = Idx;
6455 SDValue LoShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &LoMask[0]);
6456 SDValue HiShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &HiMask[0]);
6457 int MaskOps[] = { -1, -1, -1, -1 };
6458 for (unsigned i = 0; i != 4; ++i)
6459 if (Locs[i].first != -1)
6460 MaskOps[i] = Locs[i].first * 4 + Locs[i].second;
6461 return DAG.getVectorShuffle(VT, dl, LoShuffle, HiShuffle, &MaskOps[0]);
6464 static bool MayFoldVectorLoad(SDValue V) {
6465 while (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
6466 V = V.getOperand(0);
6468 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR)
6469 V = V.getOperand(0);
6470 if (V.hasOneUse() && V.getOpcode() == ISD::BUILD_VECTOR &&
6471 V.getNumOperands() == 2 && V.getOperand(1).getOpcode() == ISD::UNDEF)
6472 // BUILD_VECTOR (load), undef
6473 V = V.getOperand(0);
6475 return MayFoldLoad(V);
6479 SDValue getMOVDDup(SDValue &Op, DebugLoc &dl, SDValue V1, SelectionDAG &DAG) {
6480 EVT VT = Op.getValueType();
6482 // Canonizalize to v2f64.
6483 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, V1);
6484 return DAG.getNode(ISD::BITCAST, dl, VT,
6485 getTargetShuffleNode(X86ISD::MOVDDUP, dl, MVT::v2f64,
6490 SDValue getMOVLowToHigh(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG,
6492 SDValue V1 = Op.getOperand(0);
6493 SDValue V2 = Op.getOperand(1);
6494 EVT VT = Op.getValueType();
6496 assert(VT != MVT::v2i64 && "unsupported shuffle type");
6498 if (HasSSE2 && VT == MVT::v2f64)
6499 return getTargetShuffleNode(X86ISD::MOVLHPD, dl, VT, V1, V2, DAG);
6501 // v4f32 or v4i32: canonizalized to v4f32 (which is legal for SSE1)
6502 return DAG.getNode(ISD::BITCAST, dl, VT,
6503 getTargetShuffleNode(X86ISD::MOVLHPS, dl, MVT::v4f32,
6504 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V1),
6505 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V2), DAG));
6509 SDValue getMOVHighToLow(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG) {
6510 SDValue V1 = Op.getOperand(0);
6511 SDValue V2 = Op.getOperand(1);
6512 EVT VT = Op.getValueType();
6514 assert((VT == MVT::v4i32 || VT == MVT::v4f32) &&
6515 "unsupported shuffle type");
6517 if (V2.getOpcode() == ISD::UNDEF)
6521 return getTargetShuffleNode(X86ISD::MOVHLPS, dl, VT, V1, V2, DAG);
6525 SDValue getMOVLP(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG, bool HasSSE2) {
6526 SDValue V1 = Op.getOperand(0);
6527 SDValue V2 = Op.getOperand(1);
6528 EVT VT = Op.getValueType();
6529 unsigned NumElems = VT.getVectorNumElements();
6531 // Use MOVLPS and MOVLPD in case V1 or V2 are loads. During isel, the second
6532 // operand of these instructions is only memory, so check if there's a
6533 // potencial load folding here, otherwise use SHUFPS or MOVSD to match the
6535 bool CanFoldLoad = false;
6537 // Trivial case, when V2 comes from a load.
6538 if (MayFoldVectorLoad(V2))
6541 // When V1 is a load, it can be folded later into a store in isel, example:
6542 // (store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)), addr:$src1)
6544 // (MOVLPSmr addr:$src1, VR128:$src2)
6545 // So, recognize this potential and also use MOVLPS or MOVLPD
6546 else if (MayFoldVectorLoad(V1) && MayFoldIntoStore(Op))
6549 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6551 if (HasSSE2 && NumElems == 2)
6552 return getTargetShuffleNode(X86ISD::MOVLPD, dl, VT, V1, V2, DAG);
6555 // If we don't care about the second element, proceed to use movss.
6556 if (SVOp->getMaskElt(1) != -1)
6557 return getTargetShuffleNode(X86ISD::MOVLPS, dl, VT, V1, V2, DAG);
6560 // movl and movlp will both match v2i64, but v2i64 is never matched by
6561 // movl earlier because we make it strict to avoid messing with the movlp load
6562 // folding logic (see the code above getMOVLP call). Match it here then,
6563 // this is horrible, but will stay like this until we move all shuffle
6564 // matching to x86 specific nodes. Note that for the 1st condition all
6565 // types are matched with movsd.
6567 // FIXME: isMOVLMask should be checked and matched before getMOVLP,
6568 // as to remove this logic from here, as much as possible
6569 if (NumElems == 2 || !isMOVLMask(SVOp->getMask(), VT))
6570 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
6571 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
6574 assert(VT != MVT::v4i32 && "unsupported shuffle type");
6576 // Invert the operand order and use SHUFPS to match it.
6577 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V2, V1,
6578 getShuffleSHUFImmediate(SVOp), DAG);
6581 // Reduce a vector shuffle to zext.
6583 X86TargetLowering::lowerVectorIntExtend(SDValue Op, SelectionDAG &DAG) const {
6584 // PMOVZX is only available from SSE41.
6585 if (!Subtarget->hasSSE41())
6588 EVT VT = Op.getValueType();
6590 // Only AVX2 support 256-bit vector integer extending.
6591 if (!Subtarget->hasInt256() && VT.is256BitVector())
6594 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6595 DebugLoc DL = Op.getDebugLoc();
6596 SDValue V1 = Op.getOperand(0);
6597 SDValue V2 = Op.getOperand(1);
6598 unsigned NumElems = VT.getVectorNumElements();
6600 // Extending is an unary operation and the element type of the source vector
6601 // won't be equal to or larger than i64.
6602 if (V2.getOpcode() != ISD::UNDEF || !VT.isInteger() ||
6603 VT.getVectorElementType() == MVT::i64)
6606 // Find the expansion ratio, e.g. expanding from i8 to i32 has a ratio of 4.
6607 unsigned Shift = 1; // Start from 2, i.e. 1 << 1.
6608 while ((1U << Shift) < NumElems) {
6609 if (SVOp->getMaskElt(1U << Shift) == 1)
6612 // The maximal ratio is 8, i.e. from i8 to i64.
6617 // Check the shuffle mask.
6618 unsigned Mask = (1U << Shift) - 1;
6619 for (unsigned i = 0; i != NumElems; ++i) {
6620 int EltIdx = SVOp->getMaskElt(i);
6621 if ((i & Mask) != 0 && EltIdx != -1)
6623 if ((i & Mask) == 0 && (unsigned)EltIdx != (i >> Shift))
6627 unsigned NBits = VT.getVectorElementType().getSizeInBits() << Shift;
6628 EVT NeVT = EVT::getIntegerVT(*DAG.getContext(), NBits);
6629 EVT NVT = EVT::getVectorVT(*DAG.getContext(), NeVT, NumElems >> Shift);
6631 if (!isTypeLegal(NVT))
6634 // Simplify the operand as it's prepared to be fed into shuffle.
6635 unsigned SignificantBits = NVT.getSizeInBits() >> Shift;
6636 if (V1.getOpcode() == ISD::BITCAST &&
6637 V1.getOperand(0).getOpcode() == ISD::SCALAR_TO_VECTOR &&
6638 V1.getOperand(0).getOperand(0).getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
6640 .getOperand(0).getValueType().getSizeInBits() == SignificantBits) {
6641 // (bitcast (sclr2vec (ext_vec_elt x))) -> (bitcast x)
6642 SDValue V = V1.getOperand(0).getOperand(0).getOperand(0);
6643 ConstantSDNode *CIdx =
6644 dyn_cast<ConstantSDNode>(V1.getOperand(0).getOperand(0).getOperand(1));
6645 // If it's foldable, i.e. normal load with single use, we will let code
6646 // selection to fold it. Otherwise, we will short the conversion sequence.
6647 if (CIdx && CIdx->getZExtValue() == 0 &&
6648 (!ISD::isNormalLoad(V.getNode()) || !V.hasOneUse()))
6649 V1 = DAG.getNode(ISD::BITCAST, DL, V1.getValueType(), V);
6652 return DAG.getNode(ISD::BITCAST, DL, VT,
6653 DAG.getNode(X86ISD::VZEXT, DL, NVT, V1));
6657 X86TargetLowering::NormalizeVectorShuffle(SDValue Op, SelectionDAG &DAG) const {
6658 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6659 EVT VT = Op.getValueType();
6660 DebugLoc dl = Op.getDebugLoc();
6661 SDValue V1 = Op.getOperand(0);
6662 SDValue V2 = Op.getOperand(1);
6664 if (isZeroShuffle(SVOp))
6665 return getZeroVector(VT, Subtarget, DAG, dl);
6667 // Handle splat operations
6668 if (SVOp->isSplat()) {
6669 unsigned NumElem = VT.getVectorNumElements();
6671 // Use vbroadcast whenever the splat comes from a foldable load
6672 SDValue Broadcast = LowerVectorBroadcast(Op, DAG);
6673 if (Broadcast.getNode())
6676 // Handle splats by matching through known shuffle masks
6677 if ((VT.is128BitVector() && NumElem <= 4) ||
6678 (VT.is256BitVector() && NumElem <= 8))
6681 // All remaning splats are promoted to target supported vector shuffles.
6682 return PromoteSplat(SVOp, DAG);
6685 // Check integer expanding shuffles.
6686 SDValue NewOp = lowerVectorIntExtend(Op, DAG);
6687 if (NewOp.getNode())
6690 // If the shuffle can be profitably rewritten as a narrower shuffle, then
6692 if (VT == MVT::v8i16 || VT == MVT::v16i8 ||
6693 VT == MVT::v16i16 || VT == MVT::v32i8) {
6694 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl);
6695 if (NewOp.getNode())
6696 return DAG.getNode(ISD::BITCAST, dl, VT, NewOp);
6697 } else if ((VT == MVT::v4i32 ||
6698 (VT == MVT::v4f32 && Subtarget->hasSSE2()))) {
6699 // FIXME: Figure out a cleaner way to do this.
6700 // Try to make use of movq to zero out the top part.
6701 if (ISD::isBuildVectorAllZeros(V2.getNode())) {
6702 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl);
6703 if (NewOp.getNode()) {
6704 EVT NewVT = NewOp.getValueType();
6705 if (isCommutedMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(),
6706 NewVT, true, false))
6707 return getVZextMovL(VT, NewVT, NewOp.getOperand(0),
6708 DAG, Subtarget, dl);
6710 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) {
6711 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl);
6712 if (NewOp.getNode()) {
6713 EVT NewVT = NewOp.getValueType();
6714 if (isMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(), NewVT))
6715 return getVZextMovL(VT, NewVT, NewOp.getOperand(1),
6716 DAG, Subtarget, dl);
6724 X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const {
6725 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6726 SDValue V1 = Op.getOperand(0);
6727 SDValue V2 = Op.getOperand(1);
6728 EVT VT = Op.getValueType();
6729 DebugLoc dl = Op.getDebugLoc();
6730 unsigned NumElems = VT.getVectorNumElements();
6731 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
6732 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
6733 bool V1IsSplat = false;
6734 bool V2IsSplat = false;
6735 bool HasSSE2 = Subtarget->hasSSE2();
6736 bool HasFp256 = Subtarget->hasFp256();
6737 bool HasInt256 = Subtarget->hasInt256();
6738 MachineFunction &MF = DAG.getMachineFunction();
6739 bool OptForSize = MF.getFunction()->getAttributes().
6740 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
6742 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
6744 if (V1IsUndef && V2IsUndef)
6745 return DAG.getUNDEF(VT);
6747 assert(!V1IsUndef && "Op 1 of shuffle should not be undef");
6749 // Vector shuffle lowering takes 3 steps:
6751 // 1) Normalize the input vectors. Here splats, zeroed vectors, profitable
6752 // narrowing and commutation of operands should be handled.
6753 // 2) Matching of shuffles with known shuffle masks to x86 target specific
6755 // 3) Rewriting of unmatched masks into new generic shuffle operations,
6756 // so the shuffle can be broken into other shuffles and the legalizer can
6757 // try the lowering again.
6759 // The general idea is that no vector_shuffle operation should be left to
6760 // be matched during isel, all of them must be converted to a target specific
6763 // Normalize the input vectors. Here splats, zeroed vectors, profitable
6764 // narrowing and commutation of operands should be handled. The actual code
6765 // doesn't include all of those, work in progress...
6766 SDValue NewOp = NormalizeVectorShuffle(Op, DAG);
6767 if (NewOp.getNode())
6770 SmallVector<int, 8> M(SVOp->getMask().begin(), SVOp->getMask().end());
6772 // NOTE: isPSHUFDMask can also match both masks below (unpckl_undef and
6773 // unpckh_undef). Only use pshufd if speed is more important than size.
6774 if (OptForSize && isUNPCKL_v_undef_Mask(M, VT, HasInt256))
6775 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
6776 if (OptForSize && isUNPCKH_v_undef_Mask(M, VT, HasInt256))
6777 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
6779 if (isMOVDDUPMask(M, VT) && Subtarget->hasSSE3() &&
6780 V2IsUndef && MayFoldVectorLoad(V1))
6781 return getMOVDDup(Op, dl, V1, DAG);
6783 if (isMOVHLPS_v_undef_Mask(M, VT))
6784 return getMOVHighToLow(Op, dl, DAG);
6786 // Use to match splats
6787 if (HasSSE2 && isUNPCKHMask(M, VT, HasInt256) && V2IsUndef &&
6788 (VT == MVT::v2f64 || VT == MVT::v2i64))
6789 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
6791 if (isPSHUFDMask(M, VT)) {
6792 // The actual implementation will match the mask in the if above and then
6793 // during isel it can match several different instructions, not only pshufd
6794 // as its name says, sad but true, emulate the behavior for now...
6795 if (isMOVDDUPMask(M, VT) && ((VT == MVT::v4f32 || VT == MVT::v2i64)))
6796 return getTargetShuffleNode(X86ISD::MOVLHPS, dl, VT, V1, V1, DAG);
6798 unsigned TargetMask = getShuffleSHUFImmediate(SVOp);
6800 if (HasSSE2 && (VT == MVT::v4f32 || VT == MVT::v4i32))
6801 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1, TargetMask, DAG);
6803 if (HasFp256 && (VT == MVT::v4f32 || VT == MVT::v2f64))
6804 return getTargetShuffleNode(X86ISD::VPERMILP, dl, VT, V1, TargetMask,
6807 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V1,
6811 // Check if this can be converted into a logical shift.
6812 bool isLeft = false;
6815 bool isShift = HasSSE2 && isVectorShift(SVOp, DAG, isLeft, ShVal, ShAmt);
6816 if (isShift && ShVal.hasOneUse()) {
6817 // If the shifted value has multiple uses, it may be cheaper to use
6818 // v_set0 + movlhps or movhlps, etc.
6819 EVT EltVT = VT.getVectorElementType();
6820 ShAmt *= EltVT.getSizeInBits();
6821 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
6824 if (isMOVLMask(M, VT)) {
6825 if (ISD::isBuildVectorAllZeros(V1.getNode()))
6826 return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl);
6827 if (!isMOVLPMask(M, VT)) {
6828 if (HasSSE2 && (VT == MVT::v2i64 || VT == MVT::v2f64))
6829 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
6831 if (VT == MVT::v4i32 || VT == MVT::v4f32)
6832 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
6836 // FIXME: fold these into legal mask.
6837 if (isMOVLHPSMask(M, VT) && !isUNPCKLMask(M, VT, HasInt256))
6838 return getMOVLowToHigh(Op, dl, DAG, HasSSE2);
6840 if (isMOVHLPSMask(M, VT))
6841 return getMOVHighToLow(Op, dl, DAG);
6843 if (V2IsUndef && isMOVSHDUPMask(M, VT, Subtarget))
6844 return getTargetShuffleNode(X86ISD::MOVSHDUP, dl, VT, V1, DAG);
6846 if (V2IsUndef && isMOVSLDUPMask(M, VT, Subtarget))
6847 return getTargetShuffleNode(X86ISD::MOVSLDUP, dl, VT, V1, DAG);
6849 if (isMOVLPMask(M, VT))
6850 return getMOVLP(Op, dl, DAG, HasSSE2);
6852 if (ShouldXformToMOVHLPS(M, VT) ||
6853 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), M, VT))
6854 return CommuteVectorShuffle(SVOp, DAG);
6857 // No better options. Use a vshldq / vsrldq.
6858 EVT EltVT = VT.getVectorElementType();
6859 ShAmt *= EltVT.getSizeInBits();
6860 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
6863 bool Commuted = false;
6864 // FIXME: This should also accept a bitcast of a splat? Be careful, not
6865 // 1,1,1,1 -> v8i16 though.
6866 V1IsSplat = isSplatVector(V1.getNode());
6867 V2IsSplat = isSplatVector(V2.getNode());
6869 // Canonicalize the splat or undef, if present, to be on the RHS.
6870 if (!V2IsUndef && V1IsSplat && !V2IsSplat) {
6871 CommuteVectorShuffleMask(M, NumElems);
6873 std::swap(V1IsSplat, V2IsSplat);
6877 if (isCommutedMOVLMask(M, VT, V2IsSplat, V2IsUndef)) {
6878 // Shuffling low element of v1 into undef, just return v1.
6881 // If V2 is a splat, the mask may be malformed such as <4,3,3,3>, which
6882 // the instruction selector will not match, so get a canonical MOVL with
6883 // swapped operands to undo the commute.
6884 return getMOVL(DAG, dl, VT, V2, V1);
6887 if (isUNPCKLMask(M, VT, HasInt256))
6888 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
6890 if (isUNPCKHMask(M, VT, HasInt256))
6891 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
6894 // Normalize mask so all entries that point to V2 points to its first
6895 // element then try to match unpck{h|l} again. If match, return a
6896 // new vector_shuffle with the corrected mask.p
6897 SmallVector<int, 8> NewMask(M.begin(), M.end());
6898 NormalizeMask(NewMask, NumElems);
6899 if (isUNPCKLMask(NewMask, VT, HasInt256, true))
6900 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
6901 if (isUNPCKHMask(NewMask, VT, HasInt256, true))
6902 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
6906 // Commute is back and try unpck* again.
6907 // FIXME: this seems wrong.
6908 CommuteVectorShuffleMask(M, NumElems);
6910 std::swap(V1IsSplat, V2IsSplat);
6913 if (isUNPCKLMask(M, VT, HasInt256))
6914 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
6916 if (isUNPCKHMask(M, VT, HasInt256))
6917 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
6920 // Normalize the node to match x86 shuffle ops if needed
6921 if (!V2IsUndef && (isSHUFPMask(M, VT, HasFp256, /* Commuted */ true)))
6922 return CommuteVectorShuffle(SVOp, DAG);
6924 // The checks below are all present in isShuffleMaskLegal, but they are
6925 // inlined here right now to enable us to directly emit target specific
6926 // nodes, and remove one by one until they don't return Op anymore.
6928 if (isPALIGNRMask(M, VT, Subtarget))
6929 return getTargetShuffleNode(X86ISD::PALIGN, dl, VT, V1, V2,
6930 getShufflePALIGNRImmediate(SVOp),
6933 if (ShuffleVectorSDNode::isSplatMask(&M[0], VT) &&
6934 SVOp->getSplatIndex() == 0 && V2IsUndef) {
6935 if (VT == MVT::v2f64 || VT == MVT::v2i64)
6936 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
6939 if (isPSHUFHWMask(M, VT, HasInt256))
6940 return getTargetShuffleNode(X86ISD::PSHUFHW, dl, VT, V1,
6941 getShufflePSHUFHWImmediate(SVOp),
6944 if (isPSHUFLWMask(M, VT, HasInt256))
6945 return getTargetShuffleNode(X86ISD::PSHUFLW, dl, VT, V1,
6946 getShufflePSHUFLWImmediate(SVOp),
6949 if (isSHUFPMask(M, VT, HasFp256))
6950 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V2,
6951 getShuffleSHUFImmediate(SVOp), DAG);
6953 if (isUNPCKL_v_undef_Mask(M, VT, HasInt256))
6954 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
6955 if (isUNPCKH_v_undef_Mask(M, VT, HasInt256))
6956 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
6958 //===--------------------------------------------------------------------===//
6959 // Generate target specific nodes for 128 or 256-bit shuffles only
6960 // supported in the AVX instruction set.
6963 // Handle VMOVDDUPY permutations
6964 if (V2IsUndef && isMOVDDUPYMask(M, VT, HasFp256))
6965 return getTargetShuffleNode(X86ISD::MOVDDUP, dl, VT, V1, DAG);
6967 // Handle VPERMILPS/D* permutations
6968 if (isVPERMILPMask(M, VT, HasFp256)) {
6969 if (HasInt256 && VT == MVT::v8i32)
6970 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1,
6971 getShuffleSHUFImmediate(SVOp), DAG);
6972 return getTargetShuffleNode(X86ISD::VPERMILP, dl, VT, V1,
6973 getShuffleSHUFImmediate(SVOp), DAG);
6976 // Handle VPERM2F128/VPERM2I128 permutations
6977 if (isVPERM2X128Mask(M, VT, HasFp256))
6978 return getTargetShuffleNode(X86ISD::VPERM2X128, dl, VT, V1,
6979 V2, getShuffleVPERM2X128Immediate(SVOp), DAG);
6981 SDValue BlendOp = LowerVECTOR_SHUFFLEtoBlend(SVOp, Subtarget, DAG);
6982 if (BlendOp.getNode())
6985 if (V2IsUndef && HasInt256 && (VT == MVT::v8i32 || VT == MVT::v8f32)) {
6986 SmallVector<SDValue, 8> permclMask;
6987 for (unsigned i = 0; i != 8; ++i) {
6988 permclMask.push_back(DAG.getConstant((M[i]>=0) ? M[i] : 0, MVT::i32));
6990 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32,
6992 // Bitcast is for VPERMPS since mask is v8i32 but node takes v8f32
6993 return DAG.getNode(X86ISD::VPERMV, dl, VT,
6994 DAG.getNode(ISD::BITCAST, dl, VT, Mask), V1);
6997 if (V2IsUndef && HasInt256 && (VT == MVT::v4i64 || VT == MVT::v4f64))
6998 return getTargetShuffleNode(X86ISD::VPERMI, dl, VT, V1,
6999 getShuffleCLImmediate(SVOp), DAG);
7001 //===--------------------------------------------------------------------===//
7002 // Since no target specific shuffle was selected for this generic one,
7003 // lower it into other known shuffles. FIXME: this isn't true yet, but
7004 // this is the plan.
7007 // Handle v8i16 specifically since SSE can do byte extraction and insertion.
7008 if (VT == MVT::v8i16) {
7009 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(Op, Subtarget, DAG);
7010 if (NewOp.getNode())
7014 if (VT == MVT::v16i8) {
7015 SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(SVOp, DAG, *this);
7016 if (NewOp.getNode())
7020 if (VT == MVT::v32i8) {
7021 SDValue NewOp = LowerVECTOR_SHUFFLEv32i8(SVOp, Subtarget, DAG);
7022 if (NewOp.getNode())
7026 // Handle all 128-bit wide vectors with 4 elements, and match them with
7027 // several different shuffle types.
7028 if (NumElems == 4 && VT.is128BitVector())
7029 return LowerVECTOR_SHUFFLE_128v4(SVOp, DAG);
7031 // Handle general 256-bit shuffles
7032 if (VT.is256BitVector())
7033 return LowerVECTOR_SHUFFLE_256(SVOp, DAG);
7039 X86TargetLowering::LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op,
7040 SelectionDAG &DAG) const {
7041 EVT VT = Op.getValueType();
7042 DebugLoc dl = Op.getDebugLoc();
7044 if (!Op.getOperand(0).getValueType().is128BitVector())
7047 if (VT.getSizeInBits() == 8) {
7048 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
7049 Op.getOperand(0), Op.getOperand(1));
7050 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
7051 DAG.getValueType(VT));
7052 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
7055 if (VT.getSizeInBits() == 16) {
7056 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
7057 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
7059 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
7060 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
7061 DAG.getNode(ISD::BITCAST, dl,
7065 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
7066 Op.getOperand(0), Op.getOperand(1));
7067 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
7068 DAG.getValueType(VT));
7069 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
7072 if (VT == MVT::f32) {
7073 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
7074 // the result back to FR32 register. It's only worth matching if the
7075 // result has a single use which is a store or a bitcast to i32. And in
7076 // the case of a store, it's not worth it if the index is a constant 0,
7077 // because a MOVSSmr can be used instead, which is smaller and faster.
7078 if (!Op.hasOneUse())
7080 SDNode *User = *Op.getNode()->use_begin();
7081 if ((User->getOpcode() != ISD::STORE ||
7082 (isa<ConstantSDNode>(Op.getOperand(1)) &&
7083 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
7084 (User->getOpcode() != ISD::BITCAST ||
7085 User->getValueType(0) != MVT::i32))
7087 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
7088 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32,
7091 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, Extract);
7094 if (VT == MVT::i32 || VT == MVT::i64) {
7095 // ExtractPS/pextrq works with constant index.
7096 if (isa<ConstantSDNode>(Op.getOperand(1)))
7103 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
7104 SelectionDAG &DAG) const {
7105 if (!isa<ConstantSDNode>(Op.getOperand(1)))
7108 SDValue Vec = Op.getOperand(0);
7109 EVT VecVT = Vec.getValueType();
7111 // If this is a 256-bit vector result, first extract the 128-bit vector and
7112 // then extract the element from the 128-bit vector.
7113 if (VecVT.is256BitVector()) {
7114 DebugLoc dl = Op.getNode()->getDebugLoc();
7115 unsigned NumElems = VecVT.getVectorNumElements();
7116 SDValue Idx = Op.getOperand(1);
7117 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
7119 // Get the 128-bit vector.
7120 Vec = Extract128BitVector(Vec, IdxVal, DAG, dl);
7122 if (IdxVal >= NumElems/2)
7123 IdxVal -= NumElems/2;
7124 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec,
7125 DAG.getConstant(IdxVal, MVT::i32));
7128 assert(VecVT.is128BitVector() && "Unexpected vector length");
7130 if (Subtarget->hasSSE41()) {
7131 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG);
7136 EVT VT = Op.getValueType();
7137 DebugLoc dl = Op.getDebugLoc();
7138 // TODO: handle v16i8.
7139 if (VT.getSizeInBits() == 16) {
7140 SDValue Vec = Op.getOperand(0);
7141 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
7143 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
7144 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
7145 DAG.getNode(ISD::BITCAST, dl,
7148 // Transform it so it match pextrw which produces a 32-bit result.
7149 EVT EltVT = MVT::i32;
7150 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
7151 Op.getOperand(0), Op.getOperand(1));
7152 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
7153 DAG.getValueType(VT));
7154 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
7157 if (VT.getSizeInBits() == 32) {
7158 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
7162 // SHUFPS the element to the lowest double word, then movss.
7163 int Mask[4] = { static_cast<int>(Idx), -1, -1, -1 };
7164 EVT VVT = Op.getOperand(0).getValueType();
7165 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
7166 DAG.getUNDEF(VVT), Mask);
7167 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
7168 DAG.getIntPtrConstant(0));
7171 if (VT.getSizeInBits() == 64) {
7172 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
7173 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
7174 // to match extract_elt for f64.
7175 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
7179 // UNPCKHPD the element to the lowest double word, then movsd.
7180 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
7181 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
7182 int Mask[2] = { 1, -1 };
7183 EVT VVT = Op.getOperand(0).getValueType();
7184 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
7185 DAG.getUNDEF(VVT), Mask);
7186 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
7187 DAG.getIntPtrConstant(0));
7194 X86TargetLowering::LowerINSERT_VECTOR_ELT_SSE4(SDValue Op,
7195 SelectionDAG &DAG) const {
7196 EVT VT = Op.getValueType();
7197 EVT EltVT = VT.getVectorElementType();
7198 DebugLoc dl = Op.getDebugLoc();
7200 SDValue N0 = Op.getOperand(0);
7201 SDValue N1 = Op.getOperand(1);
7202 SDValue N2 = Op.getOperand(2);
7204 if (!VT.is128BitVector())
7207 if ((EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) &&
7208 isa<ConstantSDNode>(N2)) {
7210 if (VT == MVT::v8i16)
7211 Opc = X86ISD::PINSRW;
7212 else if (VT == MVT::v16i8)
7213 Opc = X86ISD::PINSRB;
7215 Opc = X86ISD::PINSRB;
7217 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
7219 if (N1.getValueType() != MVT::i32)
7220 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
7221 if (N2.getValueType() != MVT::i32)
7222 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
7223 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
7226 if (EltVT == MVT::f32 && isa<ConstantSDNode>(N2)) {
7227 // Bits [7:6] of the constant are the source select. This will always be
7228 // zero here. The DAG Combiner may combine an extract_elt index into these
7229 // bits. For example (insert (extract, 3), 2) could be matched by putting
7230 // the '3' into bits [7:6] of X86ISD::INSERTPS.
7231 // Bits [5:4] of the constant are the destination select. This is the
7232 // value of the incoming immediate.
7233 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
7234 // combine either bitwise AND or insert of float 0.0 to set these bits.
7235 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue() << 4);
7236 // Create this as a scalar to vector..
7237 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
7238 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
7241 if ((EltVT == MVT::i32 || EltVT == MVT::i64) && isa<ConstantSDNode>(N2)) {
7242 // PINSR* works with constant index.
7249 X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const {
7250 EVT VT = Op.getValueType();
7251 EVT EltVT = VT.getVectorElementType();
7253 DebugLoc dl = Op.getDebugLoc();
7254 SDValue N0 = Op.getOperand(0);
7255 SDValue N1 = Op.getOperand(1);
7256 SDValue N2 = Op.getOperand(2);
7258 // If this is a 256-bit vector result, first extract the 128-bit vector,
7259 // insert the element into the extracted half and then place it back.
7260 if (VT.is256BitVector()) {
7261 if (!isa<ConstantSDNode>(N2))
7264 // Get the desired 128-bit vector half.
7265 unsigned NumElems = VT.getVectorNumElements();
7266 unsigned IdxVal = cast<ConstantSDNode>(N2)->getZExtValue();
7267 SDValue V = Extract128BitVector(N0, IdxVal, DAG, dl);
7269 // Insert the element into the desired half.
7270 bool Upper = IdxVal >= NumElems/2;
7271 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V, N1,
7272 DAG.getConstant(Upper ? IdxVal-NumElems/2 : IdxVal, MVT::i32));
7274 // Insert the changed part back to the 256-bit vector
7275 return Insert128BitVector(N0, V, IdxVal, DAG, dl);
7278 if (Subtarget->hasSSE41())
7279 return LowerINSERT_VECTOR_ELT_SSE4(Op, DAG);
7281 if (EltVT == MVT::i8)
7284 if (EltVT.getSizeInBits() == 16 && isa<ConstantSDNode>(N2)) {
7285 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
7286 // as its second argument.
7287 if (N1.getValueType() != MVT::i32)
7288 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
7289 if (N2.getValueType() != MVT::i32)
7290 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
7291 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);
7296 static SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) {
7297 LLVMContext *Context = DAG.getContext();
7298 DebugLoc dl = Op.getDebugLoc();
7299 EVT OpVT = Op.getValueType();
7301 // If this is a 256-bit vector result, first insert into a 128-bit
7302 // vector and then insert into the 256-bit vector.
7303 if (!OpVT.is128BitVector()) {
7304 // Insert into a 128-bit vector.
7305 EVT VT128 = EVT::getVectorVT(*Context,
7306 OpVT.getVectorElementType(),
7307 OpVT.getVectorNumElements() / 2);
7309 Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Op.getOperand(0));
7311 // Insert the 128-bit vector.
7312 return Insert128BitVector(DAG.getUNDEF(OpVT), Op, 0, DAG, dl);
7315 if (OpVT == MVT::v1i64 &&
7316 Op.getOperand(0).getValueType() == MVT::i64)
7317 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
7319 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
7320 assert(OpVT.is128BitVector() && "Expected an SSE type!");
7321 return DAG.getNode(ISD::BITCAST, dl, OpVT,
7322 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,AnyExt));
7325 // Lower a node with an EXTRACT_SUBVECTOR opcode. This may result in
7326 // a simple subregister reference or explicit instructions to grab
7327 // upper bits of a vector.
7328 static SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
7329 SelectionDAG &DAG) {
7330 if (Subtarget->hasFp256()) {
7331 DebugLoc dl = Op.getNode()->getDebugLoc();
7332 SDValue Vec = Op.getNode()->getOperand(0);
7333 SDValue Idx = Op.getNode()->getOperand(1);
7335 if (Op.getNode()->getValueType(0).is128BitVector() &&
7336 Vec.getNode()->getValueType(0).is256BitVector() &&
7337 isa<ConstantSDNode>(Idx)) {
7338 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
7339 return Extract128BitVector(Vec, IdxVal, DAG, dl);
7345 // Lower a node with an INSERT_SUBVECTOR opcode. This may result in a
7346 // simple superregister reference or explicit instructions to insert
7347 // the upper bits of a vector.
7348 static SDValue LowerINSERT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
7349 SelectionDAG &DAG) {
7350 if (Subtarget->hasFp256()) {
7351 DebugLoc dl = Op.getNode()->getDebugLoc();
7352 SDValue Vec = Op.getNode()->getOperand(0);
7353 SDValue SubVec = Op.getNode()->getOperand(1);
7354 SDValue Idx = Op.getNode()->getOperand(2);
7356 if (Op.getNode()->getValueType(0).is256BitVector() &&
7357 SubVec.getNode()->getValueType(0).is128BitVector() &&
7358 isa<ConstantSDNode>(Idx)) {
7359 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
7360 return Insert128BitVector(Vec, SubVec, IdxVal, DAG, dl);
7366 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
7367 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
7368 // one of the above mentioned nodes. It has to be wrapped because otherwise
7369 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
7370 // be used to form addressing mode. These wrapped nodes will be selected
7373 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
7374 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
7376 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
7378 unsigned char OpFlag = 0;
7379 unsigned WrapperKind = X86ISD::Wrapper;
7380 CodeModel::Model M = getTargetMachine().getCodeModel();
7382 if (Subtarget->isPICStyleRIPRel() &&
7383 (M == CodeModel::Small || M == CodeModel::Kernel))
7384 WrapperKind = X86ISD::WrapperRIP;
7385 else if (Subtarget->isPICStyleGOT())
7386 OpFlag = X86II::MO_GOTOFF;
7387 else if (Subtarget->isPICStyleStubPIC())
7388 OpFlag = X86II::MO_PIC_BASE_OFFSET;
7390 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(),
7392 CP->getOffset(), OpFlag);
7393 DebugLoc DL = CP->getDebugLoc();
7394 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
7395 // With PIC, the address is actually $g + Offset.
7397 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7398 DAG.getNode(X86ISD::GlobalBaseReg,
7399 DebugLoc(), getPointerTy()),
7406 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
7407 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
7409 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
7411 unsigned char OpFlag = 0;
7412 unsigned WrapperKind = X86ISD::Wrapper;
7413 CodeModel::Model M = getTargetMachine().getCodeModel();
7415 if (Subtarget->isPICStyleRIPRel() &&
7416 (M == CodeModel::Small || M == CodeModel::Kernel))
7417 WrapperKind = X86ISD::WrapperRIP;
7418 else if (Subtarget->isPICStyleGOT())
7419 OpFlag = X86II::MO_GOTOFF;
7420 else if (Subtarget->isPICStyleStubPIC())
7421 OpFlag = X86II::MO_PIC_BASE_OFFSET;
7423 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(),
7425 DebugLoc DL = JT->getDebugLoc();
7426 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
7428 // With PIC, the address is actually $g + Offset.
7430 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7431 DAG.getNode(X86ISD::GlobalBaseReg,
7432 DebugLoc(), getPointerTy()),
7439 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const {
7440 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
7442 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
7444 unsigned char OpFlag = 0;
7445 unsigned WrapperKind = X86ISD::Wrapper;
7446 CodeModel::Model M = getTargetMachine().getCodeModel();
7448 if (Subtarget->isPICStyleRIPRel() &&
7449 (M == CodeModel::Small || M == CodeModel::Kernel)) {
7450 if (Subtarget->isTargetDarwin() || Subtarget->isTargetELF())
7451 OpFlag = X86II::MO_GOTPCREL;
7452 WrapperKind = X86ISD::WrapperRIP;
7453 } else if (Subtarget->isPICStyleGOT()) {
7454 OpFlag = X86II::MO_GOT;
7455 } else if (Subtarget->isPICStyleStubPIC()) {
7456 OpFlag = X86II::MO_DARWIN_NONLAZY_PIC_BASE;
7457 } else if (Subtarget->isPICStyleStubNoDynamic()) {
7458 OpFlag = X86II::MO_DARWIN_NONLAZY;
7461 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag);
7463 DebugLoc DL = Op.getDebugLoc();
7464 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
7466 // With PIC, the address is actually $g + Offset.
7467 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
7468 !Subtarget->is64Bit()) {
7469 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7470 DAG.getNode(X86ISD::GlobalBaseReg,
7471 DebugLoc(), getPointerTy()),
7475 // For symbols that require a load from a stub to get the address, emit the
7477 if (isGlobalStubReference(OpFlag))
7478 Result = DAG.getLoad(getPointerTy(), DL, DAG.getEntryNode(), Result,
7479 MachinePointerInfo::getGOT(), false, false, false, 0);
7485 X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
7486 // Create the TargetBlockAddressAddress node.
7487 unsigned char OpFlags =
7488 Subtarget->ClassifyBlockAddressReference();
7489 CodeModel::Model M = getTargetMachine().getCodeModel();
7490 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
7491 int64_t Offset = cast<BlockAddressSDNode>(Op)->getOffset();
7492 DebugLoc dl = Op.getDebugLoc();
7493 SDValue Result = DAG.getTargetBlockAddress(BA, getPointerTy(), Offset,
7496 if (Subtarget->isPICStyleRIPRel() &&
7497 (M == CodeModel::Small || M == CodeModel::Kernel))
7498 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
7500 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
7502 // With PIC, the address is actually $g + Offset.
7503 if (isGlobalRelativeToPICBase(OpFlags)) {
7504 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
7505 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
7513 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, DebugLoc dl,
7515 SelectionDAG &DAG) const {
7516 // Create the TargetGlobalAddress node, folding in the constant
7517 // offset if it is legal.
7518 unsigned char OpFlags =
7519 Subtarget->ClassifyGlobalReference(GV, getTargetMachine());
7520 CodeModel::Model M = getTargetMachine().getCodeModel();
7522 if (OpFlags == X86II::MO_NO_FLAG &&
7523 X86::isOffsetSuitableForCodeModel(Offset, M)) {
7524 // A direct static reference to a global.
7525 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), Offset);
7528 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags);
7531 if (Subtarget->isPICStyleRIPRel() &&
7532 (M == CodeModel::Small || M == CodeModel::Kernel))
7533 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
7535 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
7537 // With PIC, the address is actually $g + Offset.
7538 if (isGlobalRelativeToPICBase(OpFlags)) {
7539 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
7540 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
7544 // For globals that require a load from a stub to get the address, emit the
7546 if (isGlobalStubReference(OpFlags))
7547 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result,
7548 MachinePointerInfo::getGOT(), false, false, false, 0);
7550 // If there was a non-zero offset that we didn't fold, create an explicit
7553 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result,
7554 DAG.getConstant(Offset, getPointerTy()));
7560 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
7561 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
7562 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
7563 return LowerGlobalAddress(GV, Op.getDebugLoc(), Offset, DAG);
7567 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
7568 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg,
7569 unsigned char OperandFlags, bool LocalDynamic = false) {
7570 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
7571 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
7572 DebugLoc dl = GA->getDebugLoc();
7573 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
7574 GA->getValueType(0),
7578 X86ISD::NodeType CallType = LocalDynamic ? X86ISD::TLSBASEADDR
7582 SDValue Ops[] = { Chain, TGA, *InFlag };
7583 Chain = DAG.getNode(CallType, dl, NodeTys, Ops, 3);
7585 SDValue Ops[] = { Chain, TGA };
7586 Chain = DAG.getNode(CallType, dl, NodeTys, Ops, 2);
7589 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
7590 MFI->setAdjustsStack(true);
7592 SDValue Flag = Chain.getValue(1);
7593 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
7596 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
7598 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
7601 DebugLoc dl = GA->getDebugLoc(); // ? function entry point might be better
7602 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
7603 DAG.getNode(X86ISD::GlobalBaseReg,
7604 DebugLoc(), PtrVT), InFlag);
7605 InFlag = Chain.getValue(1);
7607 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
7610 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
7612 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
7614 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, NULL, PtrVT,
7615 X86::RAX, X86II::MO_TLSGD);
7618 static SDValue LowerToTLSLocalDynamicModel(GlobalAddressSDNode *GA,
7622 DebugLoc dl = GA->getDebugLoc();
7624 // Get the start address of the TLS block for this module.
7625 X86MachineFunctionInfo* MFI = DAG.getMachineFunction()
7626 .getInfo<X86MachineFunctionInfo>();
7627 MFI->incNumLocalDynamicTLSAccesses();
7631 Base = GetTLSADDR(DAG, DAG.getEntryNode(), GA, NULL, PtrVT, X86::RAX,
7632 X86II::MO_TLSLD, /*LocalDynamic=*/true);
7635 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
7636 DAG.getNode(X86ISD::GlobalBaseReg, DebugLoc(), PtrVT), InFlag);
7637 InFlag = Chain.getValue(1);
7638 Base = GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX,
7639 X86II::MO_TLSLDM, /*LocalDynamic=*/true);
7642 // Note: the CleanupLocalDynamicTLSPass will remove redundant computations
7646 unsigned char OperandFlags = X86II::MO_DTPOFF;
7647 unsigned WrapperKind = X86ISD::Wrapper;
7648 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
7649 GA->getValueType(0),
7650 GA->getOffset(), OperandFlags);
7651 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
7653 // Add x@dtpoff with the base.
7654 return DAG.getNode(ISD::ADD, dl, PtrVT, Offset, Base);
7657 // Lower ISD::GlobalTLSAddress using the "initial exec" or "local exec" model.
7658 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
7659 const EVT PtrVT, TLSModel::Model model,
7660 bool is64Bit, bool isPIC) {
7661 DebugLoc dl = GA->getDebugLoc();
7663 // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit).
7664 Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(*DAG.getContext(),
7665 is64Bit ? 257 : 256));
7667 SDValue ThreadPointer = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
7668 DAG.getIntPtrConstant(0),
7669 MachinePointerInfo(Ptr),
7670 false, false, false, 0);
7672 unsigned char OperandFlags = 0;
7673 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
7675 unsigned WrapperKind = X86ISD::Wrapper;
7676 if (model == TLSModel::LocalExec) {
7677 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
7678 } else if (model == TLSModel::InitialExec) {
7680 OperandFlags = X86II::MO_GOTTPOFF;
7681 WrapperKind = X86ISD::WrapperRIP;
7683 OperandFlags = isPIC ? X86II::MO_GOTNTPOFF : X86II::MO_INDNTPOFF;
7686 llvm_unreachable("Unexpected model");
7689 // emit "addl x@ntpoff,%eax" (local exec)
7690 // or "addl x@indntpoff,%eax" (initial exec)
7691 // or "addl x@gotntpoff(%ebx) ,%eax" (initial exec, 32-bit pic)
7692 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
7693 GA->getValueType(0),
7694 GA->getOffset(), OperandFlags);
7695 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
7697 if (model == TLSModel::InitialExec) {
7698 if (isPIC && !is64Bit) {
7699 Offset = DAG.getNode(ISD::ADD, dl, PtrVT,
7700 DAG.getNode(X86ISD::GlobalBaseReg, DebugLoc(), PtrVT),
7704 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
7705 MachinePointerInfo::getGOT(), false, false, false,
7709 // The address of the thread local variable is the add of the thread
7710 // pointer with the offset of the variable.
7711 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
7715 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
7717 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
7718 const GlobalValue *GV = GA->getGlobal();
7720 if (Subtarget->isTargetELF()) {
7721 TLSModel::Model model = getTargetMachine().getTLSModel(GV);
7724 case TLSModel::GeneralDynamic:
7725 if (Subtarget->is64Bit())
7726 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy());
7727 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy());
7728 case TLSModel::LocalDynamic:
7729 return LowerToTLSLocalDynamicModel(GA, DAG, getPointerTy(),
7730 Subtarget->is64Bit());
7731 case TLSModel::InitialExec:
7732 case TLSModel::LocalExec:
7733 return LowerToTLSExecModel(GA, DAG, getPointerTy(), model,
7734 Subtarget->is64Bit(),
7735 getTargetMachine().getRelocationModel() == Reloc::PIC_);
7737 llvm_unreachable("Unknown TLS model.");
7740 if (Subtarget->isTargetDarwin()) {
7741 // Darwin only has one model of TLS. Lower to that.
7742 unsigned char OpFlag = 0;
7743 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ?
7744 X86ISD::WrapperRIP : X86ISD::Wrapper;
7746 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
7748 bool PIC32 = (getTargetMachine().getRelocationModel() == Reloc::PIC_) &&
7749 !Subtarget->is64Bit();
7751 OpFlag = X86II::MO_TLVP_PIC_BASE;
7753 OpFlag = X86II::MO_TLVP;
7754 DebugLoc DL = Op.getDebugLoc();
7755 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL,
7756 GA->getValueType(0),
7757 GA->getOffset(), OpFlag);
7758 SDValue Offset = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
7760 // With PIC32, the address is actually $g + Offset.
7762 Offset = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7763 DAG.getNode(X86ISD::GlobalBaseReg,
7764 DebugLoc(), getPointerTy()),
7767 // Lowering the machine isd will make sure everything is in the right
7769 SDValue Chain = DAG.getEntryNode();
7770 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
7771 SDValue Args[] = { Chain, Offset };
7772 Chain = DAG.getNode(X86ISD::TLSCALL, DL, NodeTys, Args, 2);
7774 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls.
7775 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
7776 MFI->setAdjustsStack(true);
7778 // And our return value (tls address) is in the standard call return value
7780 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
7781 return DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(),
7785 if (Subtarget->isTargetWindows()) {
7786 // Just use the implicit TLS architecture
7787 // Need to generate someting similar to:
7788 // mov rdx, qword [gs:abs 58H]; Load pointer to ThreadLocalStorage
7790 // mov ecx, dword [rel _tls_index]: Load index (from C runtime)
7791 // mov rcx, qword [rdx+rcx*8]
7792 // mov eax, .tls$:tlsvar
7793 // [rax+rcx] contains the address
7794 // Windows 64bit: gs:0x58
7795 // Windows 32bit: fs:__tls_array
7797 // If GV is an alias then use the aliasee for determining
7798 // thread-localness.
7799 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV))
7800 GV = GA->resolveAliasedGlobal(false);
7801 DebugLoc dl = GA->getDebugLoc();
7802 SDValue Chain = DAG.getEntryNode();
7804 // Get the Thread Pointer, which is %fs:__tls_array (32-bit) or
7805 // %gs:0x58 (64-bit).
7806 Value *Ptr = Constant::getNullValue(Subtarget->is64Bit()
7807 ? Type::getInt8PtrTy(*DAG.getContext(),
7809 : Type::getInt32PtrTy(*DAG.getContext(),
7812 SDValue ThreadPointer = DAG.getLoad(getPointerTy(), dl, Chain,
7813 Subtarget->is64Bit()
7814 ? DAG.getIntPtrConstant(0x58)
7815 : DAG.getExternalSymbol("_tls_array",
7817 MachinePointerInfo(Ptr),
7818 false, false, false, 0);
7820 // Load the _tls_index variable
7821 SDValue IDX = DAG.getExternalSymbol("_tls_index", getPointerTy());
7822 if (Subtarget->is64Bit())
7823 IDX = DAG.getExtLoad(ISD::ZEXTLOAD, dl, getPointerTy(), Chain,
7824 IDX, MachinePointerInfo(), MVT::i32,
7827 IDX = DAG.getLoad(getPointerTy(), dl, Chain, IDX, MachinePointerInfo(),
7828 false, false, false, 0);
7830 SDValue Scale = DAG.getConstant(Log2_64_Ceil(TD->getPointerSize()),
7832 IDX = DAG.getNode(ISD::SHL, dl, getPointerTy(), IDX, Scale);
7834 SDValue res = DAG.getNode(ISD::ADD, dl, getPointerTy(), ThreadPointer, IDX);
7835 res = DAG.getLoad(getPointerTy(), dl, Chain, res, MachinePointerInfo(),
7836 false, false, false, 0);
7838 // Get the offset of start of .tls section
7839 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
7840 GA->getValueType(0),
7841 GA->getOffset(), X86II::MO_SECREL);
7842 SDValue Offset = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), TGA);
7844 // The address of the thread local variable is the add of the thread
7845 // pointer with the offset of the variable.
7846 return DAG.getNode(ISD::ADD, dl, getPointerTy(), res, Offset);
7849 llvm_unreachable("TLS not implemented for this target.");
7852 /// LowerShiftParts - Lower SRA_PARTS and friends, which return two i32 values
7853 /// and take a 2 x i32 value to shift plus a shift amount.
7854 SDValue X86TargetLowering::LowerShiftParts(SDValue Op, SelectionDAG &DAG) const{
7855 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
7856 EVT VT = Op.getValueType();
7857 unsigned VTBits = VT.getSizeInBits();
7858 DebugLoc dl = Op.getDebugLoc();
7859 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
7860 SDValue ShOpLo = Op.getOperand(0);
7861 SDValue ShOpHi = Op.getOperand(1);
7862 SDValue ShAmt = Op.getOperand(2);
7863 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
7864 DAG.getConstant(VTBits - 1, MVT::i8))
7865 : DAG.getConstant(0, VT);
7868 if (Op.getOpcode() == ISD::SHL_PARTS) {
7869 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
7870 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
7872 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
7873 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, ShAmt);
7876 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
7877 DAG.getConstant(VTBits, MVT::i8));
7878 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
7879 AndNode, DAG.getConstant(0, MVT::i8));
7882 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8);
7883 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
7884 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
7886 if (Op.getOpcode() == ISD::SHL_PARTS) {
7887 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
7888 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
7890 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
7891 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
7894 SDValue Ops[2] = { Lo, Hi };
7895 return DAG.getMergeValues(Ops, 2, dl);
7898 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op,
7899 SelectionDAG &DAG) const {
7900 EVT SrcVT = Op.getOperand(0).getValueType();
7902 if (SrcVT.isVector())
7905 assert(SrcVT.getSimpleVT() <= MVT::i64 && SrcVT.getSimpleVT() >= MVT::i16 &&
7906 "Unknown SINT_TO_FP to lower!");
7908 // These are really Legal; return the operand so the caller accepts it as
7910 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
7912 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
7913 Subtarget->is64Bit()) {
7917 DebugLoc dl = Op.getDebugLoc();
7918 unsigned Size = SrcVT.getSizeInBits()/8;
7919 MachineFunction &MF = DAG.getMachineFunction();
7920 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false);
7921 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
7922 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
7924 MachinePointerInfo::getFixedStack(SSFI),
7926 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
7929 SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
7931 SelectionDAG &DAG) const {
7933 DebugLoc DL = Op.getDebugLoc();
7935 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
7937 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Glue);
7939 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
7941 unsigned ByteSize = SrcVT.getSizeInBits()/8;
7943 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(StackSlot);
7944 MachineMemOperand *MMO;
7946 int SSFI = FI->getIndex();
7948 DAG.getMachineFunction()
7949 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
7950 MachineMemOperand::MOLoad, ByteSize, ByteSize);
7952 MMO = cast<LoadSDNode>(StackSlot)->getMemOperand();
7953 StackSlot = StackSlot.getOperand(1);
7955 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) };
7956 SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG :
7958 Tys, Ops, array_lengthof(Ops),
7962 Chain = Result.getValue(1);
7963 SDValue InFlag = Result.getValue(2);
7965 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
7966 // shouldn't be necessary except that RFP cannot be live across
7967 // multiple blocks. When stackifier is fixed, they can be uncoupled.
7968 MachineFunction &MF = DAG.getMachineFunction();
7969 unsigned SSFISize = Op.getValueType().getSizeInBits()/8;
7970 int SSFI = MF.getFrameInfo()->CreateStackObject(SSFISize, SSFISize, false);
7971 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
7972 Tys = DAG.getVTList(MVT::Other);
7974 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag
7976 MachineMemOperand *MMO =
7977 DAG.getMachineFunction()
7978 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
7979 MachineMemOperand::MOStore, SSFISize, SSFISize);
7981 Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys,
7982 Ops, array_lengthof(Ops),
7983 Op.getValueType(), MMO);
7984 Result = DAG.getLoad(Op.getValueType(), DL, Chain, StackSlot,
7985 MachinePointerInfo::getFixedStack(SSFI),
7986 false, false, false, 0);
7992 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
7993 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op,
7994 SelectionDAG &DAG) const {
7995 // This algorithm is not obvious. Here it is what we're trying to output:
7998 punpckldq (c0), %xmm0 // c0: (uint4){ 0x43300000U, 0x45300000U, 0U, 0U }
7999 subpd (c1), %xmm0 // c1: (double2){ 0x1.0p52, 0x1.0p52 * 0x1.0p32 }
8003 pshufd $0x4e, %xmm0, %xmm1
8008 DebugLoc dl = Op.getDebugLoc();
8009 LLVMContext *Context = DAG.getContext();
8011 // Build some magic constants.
8012 const uint32_t CV0[] = { 0x43300000, 0x45300000, 0, 0 };
8013 Constant *C0 = ConstantDataVector::get(*Context, CV0);
8014 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16);
8016 SmallVector<Constant*,2> CV1;
8018 ConstantFP::get(*Context, APFloat(APInt(64, 0x4330000000000000ULL))));
8020 ConstantFP::get(*Context, APFloat(APInt(64, 0x4530000000000000ULL))));
8021 Constant *C1 = ConstantVector::get(CV1);
8022 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16);
8024 // Load the 64-bit value into an XMM register.
8025 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
8027 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
8028 MachinePointerInfo::getConstantPool(),
8029 false, false, false, 16);
8030 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32,
8031 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, XR1),
8034 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
8035 MachinePointerInfo::getConstantPool(),
8036 false, false, false, 16);
8037 SDValue XR2F = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Unpck1);
8038 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
8041 if (Subtarget->hasSSE3()) {
8042 // FIXME: The 'haddpd' instruction may be slower than 'movhlps + addsd'.
8043 Result = DAG.getNode(X86ISD::FHADD, dl, MVT::v2f64, Sub, Sub);
8045 SDValue S2F = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Sub);
8046 SDValue Shuffle = getTargetShuffleNode(X86ISD::PSHUFD, dl, MVT::v4i32,
8048 Result = DAG.getNode(ISD::FADD, dl, MVT::v2f64,
8049 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Shuffle),
8053 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Result,
8054 DAG.getIntPtrConstant(0));
8057 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
8058 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op,
8059 SelectionDAG &DAG) const {
8060 DebugLoc dl = Op.getDebugLoc();
8061 // FP constant to bias correct the final result.
8062 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
8065 // Load the 32-bit value into an XMM register.
8066 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
8069 // Zero out the upper parts of the register.
8070 Load = getShuffleVectorZeroOrUndef(Load, 0, true, Subtarget, DAG);
8072 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
8073 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Load),
8074 DAG.getIntPtrConstant(0));
8076 // Or the load with the bias.
8077 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64,
8078 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
8079 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
8081 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
8082 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
8083 MVT::v2f64, Bias)));
8084 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
8085 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or),
8086 DAG.getIntPtrConstant(0));
8088 // Subtract the bias.
8089 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
8091 // Handle final rounding.
8092 EVT DestVT = Op.getValueType();
8094 if (DestVT.bitsLT(MVT::f64))
8095 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
8096 DAG.getIntPtrConstant(0));
8097 if (DestVT.bitsGT(MVT::f64))
8098 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
8100 // Handle final rounding.
8104 SDValue X86TargetLowering::lowerUINT_TO_FP_vec(SDValue Op,
8105 SelectionDAG &DAG) const {
8106 SDValue N0 = Op.getOperand(0);
8107 EVT SVT = N0.getValueType();
8108 DebugLoc dl = Op.getDebugLoc();
8110 assert((SVT == MVT::v4i8 || SVT == MVT::v4i16 ||
8111 SVT == MVT::v8i8 || SVT == MVT::v8i16) &&
8112 "Custom UINT_TO_FP is not supported!");
8114 EVT NVT = EVT::getVectorVT(*DAG.getContext(), MVT::i32, SVT.getVectorNumElements());
8115 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
8116 DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, N0));
8119 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op,
8120 SelectionDAG &DAG) const {
8121 SDValue N0 = Op.getOperand(0);
8122 DebugLoc dl = Op.getDebugLoc();
8124 if (Op.getValueType().isVector())
8125 return lowerUINT_TO_FP_vec(Op, DAG);
8127 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't
8128 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
8129 // the optimization here.
8130 if (DAG.SignBitIsZero(N0))
8131 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
8133 EVT SrcVT = N0.getValueType();
8134 EVT DstVT = Op.getValueType();
8135 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64)
8136 return LowerUINT_TO_FP_i64(Op, DAG);
8137 if (SrcVT == MVT::i32 && X86ScalarSSEf64)
8138 return LowerUINT_TO_FP_i32(Op, DAG);
8139 if (Subtarget->is64Bit() && SrcVT == MVT::i64 && DstVT == MVT::f32)
8142 // Make a 64-bit buffer, and use it to build an FILD.
8143 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
8144 if (SrcVT == MVT::i32) {
8145 SDValue WordOff = DAG.getConstant(4, getPointerTy());
8146 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl,
8147 getPointerTy(), StackSlot, WordOff);
8148 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
8149 StackSlot, MachinePointerInfo(),
8151 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32),
8152 OffsetSlot, MachinePointerInfo(),
8154 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
8158 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP");
8159 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
8160 StackSlot, MachinePointerInfo(),
8162 // For i64 source, we need to add the appropriate power of 2 if the input
8163 // was negative. This is the same as the optimization in
8164 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here,
8165 // we must be careful to do the computation in x87 extended precision, not
8166 // in SSE. (The generic code can't know it's OK to do this, or how to.)
8167 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex();
8168 MachineMemOperand *MMO =
8169 DAG.getMachineFunction()
8170 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
8171 MachineMemOperand::MOLoad, 8, 8);
8173 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other);
8174 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) };
8175 SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops, 3,
8178 APInt FF(32, 0x5F800000ULL);
8180 // Check whether the sign bit is set.
8181 SDValue SignSet = DAG.getSetCC(dl, getSetCCResultType(MVT::i64),
8182 Op.getOperand(0), DAG.getConstant(0, MVT::i64),
8185 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
8186 SDValue FudgePtr = DAG.getConstantPool(
8187 ConstantInt::get(*DAG.getContext(), FF.zext(64)),
8190 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
8191 SDValue Zero = DAG.getIntPtrConstant(0);
8192 SDValue Four = DAG.getIntPtrConstant(4);
8193 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
8195 FudgePtr = DAG.getNode(ISD::ADD, dl, getPointerTy(), FudgePtr, Offset);
8197 // Load the value out, extending it from f32 to f80.
8198 // FIXME: Avoid the extend by constructing the right constant pool?
8199 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, MVT::f80, DAG.getEntryNode(),
8200 FudgePtr, MachinePointerInfo::getConstantPool(),
8201 MVT::f32, false, false, 4);
8202 // Extend everything to 80 bits to force it to be done on x87.
8203 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge);
8204 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add, DAG.getIntPtrConstant(0));
8207 std::pair<SDValue,SDValue> X86TargetLowering::
8208 FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG, bool IsSigned, bool IsReplace) const {
8209 DebugLoc DL = Op.getDebugLoc();
8211 EVT DstTy = Op.getValueType();
8213 if (!IsSigned && !isIntegerTypeFTOL(DstTy)) {
8214 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
8218 assert(DstTy.getSimpleVT() <= MVT::i64 &&
8219 DstTy.getSimpleVT() >= MVT::i16 &&
8220 "Unknown FP_TO_INT to lower!");
8222 // These are really Legal.
8223 if (DstTy == MVT::i32 &&
8224 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
8225 return std::make_pair(SDValue(), SDValue());
8226 if (Subtarget->is64Bit() &&
8227 DstTy == MVT::i64 &&
8228 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
8229 return std::make_pair(SDValue(), SDValue());
8231 // We lower FP->int64 either into FISTP64 followed by a load from a temporary
8232 // stack slot, or into the FTOL runtime function.
8233 MachineFunction &MF = DAG.getMachineFunction();
8234 unsigned MemSize = DstTy.getSizeInBits()/8;
8235 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
8236 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
8239 if (!IsSigned && isIntegerTypeFTOL(DstTy))
8240 Opc = X86ISD::WIN_FTOL;
8242 switch (DstTy.getSimpleVT().SimpleTy) {
8243 default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
8244 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
8245 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
8246 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
8249 SDValue Chain = DAG.getEntryNode();
8250 SDValue Value = Op.getOperand(0);
8251 EVT TheVT = Op.getOperand(0).getValueType();
8252 // FIXME This causes a redundant load/store if the SSE-class value is already
8253 // in memory, such as if it is on the callstack.
8254 if (isScalarFPTypeInSSEReg(TheVT)) {
8255 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
8256 Chain = DAG.getStore(Chain, DL, Value, StackSlot,
8257 MachinePointerInfo::getFixedStack(SSFI),
8259 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
8261 Chain, StackSlot, DAG.getValueType(TheVT)
8264 MachineMemOperand *MMO =
8265 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
8266 MachineMemOperand::MOLoad, MemSize, MemSize);
8267 Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops, 3,
8269 Chain = Value.getValue(1);
8270 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
8271 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
8274 MachineMemOperand *MMO =
8275 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
8276 MachineMemOperand::MOStore, MemSize, MemSize);
8278 if (Opc != X86ISD::WIN_FTOL) {
8279 // Build the FP_TO_INT*_IN_MEM
8280 SDValue Ops[] = { Chain, Value, StackSlot };
8281 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
8282 Ops, 3, DstTy, MMO);
8283 return std::make_pair(FIST, StackSlot);
8285 SDValue ftol = DAG.getNode(X86ISD::WIN_FTOL, DL,
8286 DAG.getVTList(MVT::Other, MVT::Glue),
8288 SDValue eax = DAG.getCopyFromReg(ftol, DL, X86::EAX,
8289 MVT::i32, ftol.getValue(1));
8290 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), DL, X86::EDX,
8291 MVT::i32, eax.getValue(2));
8292 SDValue Ops[] = { eax, edx };
8293 SDValue pair = IsReplace
8294 ? DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops, 2)
8295 : DAG.getMergeValues(Ops, 2, DL);
8296 return std::make_pair(pair, SDValue());
8300 static SDValue LowerAVXExtend(SDValue Op, SelectionDAG &DAG,
8301 const X86Subtarget *Subtarget) {
8302 EVT VT = Op->getValueType(0);
8303 SDValue In = Op->getOperand(0);
8304 EVT InVT = In.getValueType();
8305 DebugLoc dl = Op->getDebugLoc();
8307 // Optimize vectors in AVX mode:
8310 // Use vpunpcklwd for 4 lower elements v8i16 -> v4i32.
8311 // Use vpunpckhwd for 4 upper elements v8i16 -> v4i32.
8312 // Concat upper and lower parts.
8315 // Use vpunpckldq for 4 lower elements v4i32 -> v2i64.
8316 // Use vpunpckhdq for 4 upper elements v4i32 -> v2i64.
8317 // Concat upper and lower parts.
8320 if (((VT != MVT::v8i32) || (InVT != MVT::v8i16)) &&
8321 ((VT != MVT::v4i64) || (InVT != MVT::v4i32)))
8324 if (Subtarget->hasInt256())
8325 return DAG.getNode(X86ISD::VZEXT_MOVL, dl, VT, In);
8327 SDValue ZeroVec = getZeroVector(InVT, Subtarget, DAG, dl);
8328 SDValue Undef = DAG.getUNDEF(InVT);
8329 bool NeedZero = Op.getOpcode() == ISD::ZERO_EXTEND;
8330 SDValue OpLo = getUnpackl(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
8331 SDValue OpHi = getUnpackh(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
8333 EVT HVT = EVT::getVectorVT(*DAG.getContext(), VT.getVectorElementType(),
8334 VT.getVectorNumElements()/2);
8336 OpLo = DAG.getNode(ISD::BITCAST, dl, HVT, OpLo);
8337 OpHi = DAG.getNode(ISD::BITCAST, dl, HVT, OpHi);
8339 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
8342 SDValue X86TargetLowering::LowerANY_EXTEND(SDValue Op,
8343 SelectionDAG &DAG) const {
8344 if (Subtarget->hasFp256()) {
8345 SDValue Res = LowerAVXExtend(Op, DAG, Subtarget);
8352 SDValue X86TargetLowering::LowerZERO_EXTEND(SDValue Op,
8353 SelectionDAG &DAG) const {
8354 DebugLoc DL = Op.getDebugLoc();
8355 EVT VT = Op.getValueType();
8356 SDValue In = Op.getOperand(0);
8357 EVT SVT = In.getValueType();
8359 if (Subtarget->hasFp256()) {
8360 SDValue Res = LowerAVXExtend(Op, DAG, Subtarget);
8365 if (!VT.is256BitVector() || !SVT.is128BitVector() ||
8366 VT.getVectorNumElements() != SVT.getVectorNumElements())
8369 assert(Subtarget->hasFp256() && "256-bit vector is observed without AVX!");
8371 // AVX2 has better support of integer extending.
8372 if (Subtarget->hasInt256())
8373 return DAG.getNode(X86ISD::VZEXT, DL, VT, In);
8375 SDValue Lo = DAG.getNode(X86ISD::VZEXT, DL, MVT::v4i32, In);
8376 static const int Mask[] = {4, 5, 6, 7, -1, -1, -1, -1};
8377 SDValue Hi = DAG.getNode(X86ISD::VZEXT, DL, MVT::v4i32,
8378 DAG.getVectorShuffle(MVT::v8i16, DL, In,
8379 DAG.getUNDEF(MVT::v8i16),
8382 return DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v8i32, Lo, Hi);
8385 SDValue X86TargetLowering::lowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const {
8386 DebugLoc DL = Op.getDebugLoc();
8387 EVT VT = Op.getValueType();
8388 SDValue In = Op.getOperand(0);
8389 EVT SVT = In.getValueType();
8391 if ((VT == MVT::v4i32) && (SVT == MVT::v4i64)) {
8392 // On AVX2, v4i64 -> v4i32 becomes VPERMD.
8393 if (Subtarget->hasInt256()) {
8394 static const int ShufMask[] = {0, 2, 4, 6, -1, -1, -1, -1};
8395 In = DAG.getNode(ISD::BITCAST, DL, MVT::v8i32, In);
8396 In = DAG.getVectorShuffle(MVT::v8i32, DL, In, DAG.getUNDEF(MVT::v8i32),
8398 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, In,
8399 DAG.getIntPtrConstant(0));
8402 // On AVX, v4i64 -> v4i32 becomes a sequence that uses PSHUFD and MOVLHPS.
8403 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
8404 DAG.getIntPtrConstant(0));
8405 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
8406 DAG.getIntPtrConstant(2));
8408 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo);
8409 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi);
8412 static const int ShufMask1[] = {0, 2, 0, 0};
8413 SDValue Undef = DAG.getUNDEF(VT);
8414 OpLo = DAG.getVectorShuffle(VT, DL, OpLo, Undef, ShufMask1);
8415 OpHi = DAG.getVectorShuffle(VT, DL, OpHi, Undef, ShufMask1);
8417 // The MOVLHPS mask:
8418 static const int ShufMask2[] = {0, 1, 4, 5};
8419 return DAG.getVectorShuffle(VT, DL, OpLo, OpHi, ShufMask2);
8422 if ((VT == MVT::v8i16) && (SVT == MVT::v8i32)) {
8423 // On AVX2, v8i32 -> v8i16 becomed PSHUFB.
8424 if (Subtarget->hasInt256()) {
8425 In = DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, In);
8427 SmallVector<SDValue,32> pshufbMask;
8428 for (unsigned i = 0; i < 2; ++i) {
8429 pshufbMask.push_back(DAG.getConstant(0x0, MVT::i8));
8430 pshufbMask.push_back(DAG.getConstant(0x1, MVT::i8));
8431 pshufbMask.push_back(DAG.getConstant(0x4, MVT::i8));
8432 pshufbMask.push_back(DAG.getConstant(0x5, MVT::i8));
8433 pshufbMask.push_back(DAG.getConstant(0x8, MVT::i8));
8434 pshufbMask.push_back(DAG.getConstant(0x9, MVT::i8));
8435 pshufbMask.push_back(DAG.getConstant(0xc, MVT::i8));
8436 pshufbMask.push_back(DAG.getConstant(0xd, MVT::i8));
8437 for (unsigned j = 0; j < 8; ++j)
8438 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
8440 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8,
8441 &pshufbMask[0], 32);
8442 In = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v32i8, In, BV);
8443 In = DAG.getNode(ISD::BITCAST, DL, MVT::v4i64, In);
8445 static const int ShufMask[] = {0, 2, -1, -1};
8446 In = DAG.getVectorShuffle(MVT::v4i64, DL, In, DAG.getUNDEF(MVT::v4i64),
8448 In = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
8449 DAG.getIntPtrConstant(0));
8450 return DAG.getNode(ISD::BITCAST, DL, VT, In);
8453 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
8454 DAG.getIntPtrConstant(0));
8456 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
8457 DAG.getIntPtrConstant(4));
8459 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpLo);
8460 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpHi);
8463 static const int ShufMask1[] = {0, 1, 4, 5, 8, 9, 12, 13,
8464 -1, -1, -1, -1, -1, -1, -1, -1};
8466 SDValue Undef = DAG.getUNDEF(MVT::v16i8);
8467 OpLo = DAG.getVectorShuffle(MVT::v16i8, DL, OpLo, Undef, ShufMask1);
8468 OpHi = DAG.getVectorShuffle(MVT::v16i8, DL, OpHi, Undef, ShufMask1);
8470 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo);
8471 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi);
8473 // The MOVLHPS Mask:
8474 static const int ShufMask2[] = {0, 1, 4, 5};
8475 SDValue res = DAG.getVectorShuffle(MVT::v4i32, DL, OpLo, OpHi, ShufMask2);
8476 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, res);
8479 // Handle truncation of V256 to V128 using shuffles.
8480 if (!VT.is128BitVector() || !SVT.is256BitVector())
8483 assert(VT.getVectorNumElements() != SVT.getVectorNumElements() &&
8485 assert(Subtarget->hasFp256() && "256-bit vector without AVX!");
8487 unsigned NumElems = VT.getVectorNumElements();
8488 EVT NVT = EVT::getVectorVT(*DAG.getContext(), VT.getVectorElementType(),
8491 SmallVector<int, 16> MaskVec(NumElems * 2, -1);
8492 // Prepare truncation shuffle mask
8493 for (unsigned i = 0; i != NumElems; ++i)
8495 SDValue V = DAG.getVectorShuffle(NVT, DL,
8496 DAG.getNode(ISD::BITCAST, DL, NVT, In),
8497 DAG.getUNDEF(NVT), &MaskVec[0]);
8498 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, V,
8499 DAG.getIntPtrConstant(0));
8502 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op,
8503 SelectionDAG &DAG) const {
8504 if (Op.getValueType().isVector()) {
8505 if (Op.getValueType() == MVT::v8i16)
8506 return DAG.getNode(ISD::TRUNCATE, Op.getDebugLoc(), Op.getValueType(),
8507 DAG.getNode(ISD::FP_TO_SINT, Op.getDebugLoc(),
8508 MVT::v8i32, Op.getOperand(0)));
8512 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
8513 /*IsSigned=*/ true, /*IsReplace=*/ false);
8514 SDValue FIST = Vals.first, StackSlot = Vals.second;
8515 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
8516 if (FIST.getNode() == 0) return Op;
8518 if (StackSlot.getNode())
8520 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(),
8521 FIST, StackSlot, MachinePointerInfo(),
8522 false, false, false, 0);
8524 // The node is the result.
8528 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op,
8529 SelectionDAG &DAG) const {
8530 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
8531 /*IsSigned=*/ false, /*IsReplace=*/ false);
8532 SDValue FIST = Vals.first, StackSlot = Vals.second;
8533 assert(FIST.getNode() && "Unexpected failure");
8535 if (StackSlot.getNode())
8537 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(),
8538 FIST, StackSlot, MachinePointerInfo(),
8539 false, false, false, 0);
8541 // The node is the result.
8545 SDValue X86TargetLowering::lowerFP_EXTEND(SDValue Op,
8546 SelectionDAG &DAG) const {
8547 DebugLoc DL = Op.getDebugLoc();
8548 EVT VT = Op.getValueType();
8549 SDValue In = Op.getOperand(0);
8550 EVT SVT = In.getValueType();
8552 assert(SVT == MVT::v2f32 && "Only customize MVT::v2f32 type legalization!");
8554 return DAG.getNode(X86ISD::VFPEXT, DL, VT,
8555 DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v4f32,
8556 In, DAG.getUNDEF(SVT)));
8559 SDValue X86TargetLowering::LowerFABS(SDValue Op, SelectionDAG &DAG) const {
8560 LLVMContext *Context = DAG.getContext();
8561 DebugLoc dl = Op.getDebugLoc();
8562 EVT VT = Op.getValueType();
8564 unsigned NumElts = VT == MVT::f64 ? 2 : 4;
8565 if (VT.isVector()) {
8566 EltVT = VT.getVectorElementType();
8567 NumElts = VT.getVectorNumElements();
8570 if (EltVT == MVT::f64)
8571 C = ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63))));
8573 C = ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31))));
8574 C = ConstantVector::getSplat(NumElts, C);
8575 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy());
8576 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
8577 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
8578 MachinePointerInfo::getConstantPool(),
8579 false, false, false, Alignment);
8580 if (VT.isVector()) {
8581 MVT ANDVT = VT.is128BitVector() ? MVT::v2i64 : MVT::v4i64;
8582 return DAG.getNode(ISD::BITCAST, dl, VT,
8583 DAG.getNode(ISD::AND, dl, ANDVT,
8584 DAG.getNode(ISD::BITCAST, dl, ANDVT,
8586 DAG.getNode(ISD::BITCAST, dl, ANDVT, Mask)));
8588 return DAG.getNode(X86ISD::FAND, dl, VT, Op.getOperand(0), Mask);
8591 SDValue X86TargetLowering::LowerFNEG(SDValue Op, SelectionDAG &DAG) const {
8592 LLVMContext *Context = DAG.getContext();
8593 DebugLoc dl = Op.getDebugLoc();
8594 EVT VT = Op.getValueType();
8596 unsigned NumElts = VT == MVT::f64 ? 2 : 4;
8597 if (VT.isVector()) {
8598 EltVT = VT.getVectorElementType();
8599 NumElts = VT.getVectorNumElements();
8602 if (EltVT == MVT::f64)
8603 C = ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63)));
8605 C = ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31)));
8606 C = ConstantVector::getSplat(NumElts, C);
8607 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy());
8608 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
8609 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
8610 MachinePointerInfo::getConstantPool(),
8611 false, false, false, Alignment);
8612 if (VT.isVector()) {
8613 MVT XORVT = VT.is128BitVector() ? MVT::v2i64 : MVT::v4i64;
8614 return DAG.getNode(ISD::BITCAST, dl, VT,
8615 DAG.getNode(ISD::XOR, dl, XORVT,
8616 DAG.getNode(ISD::BITCAST, dl, XORVT,
8618 DAG.getNode(ISD::BITCAST, dl, XORVT, Mask)));
8621 return DAG.getNode(X86ISD::FXOR, dl, VT, Op.getOperand(0), Mask);
8624 SDValue X86TargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {
8625 LLVMContext *Context = DAG.getContext();
8626 SDValue Op0 = Op.getOperand(0);
8627 SDValue Op1 = Op.getOperand(1);
8628 DebugLoc dl = Op.getDebugLoc();
8629 EVT VT = Op.getValueType();
8630 EVT SrcVT = Op1.getValueType();
8632 // If second operand is smaller, extend it first.
8633 if (SrcVT.bitsLT(VT)) {
8634 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
8637 // And if it is bigger, shrink it first.
8638 if (SrcVT.bitsGT(VT)) {
8639 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1));
8643 // At this point the operands and the result should have the same
8644 // type, and that won't be f80 since that is not custom lowered.
8646 // First get the sign bit of second operand.
8647 SmallVector<Constant*,4> CV;
8648 if (SrcVT == MVT::f64) {
8649 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63))));
8650 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0))));
8652 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31))));
8653 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
8654 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
8655 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
8657 Constant *C = ConstantVector::get(CV);
8658 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
8659 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx,
8660 MachinePointerInfo::getConstantPool(),
8661 false, false, false, 16);
8662 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1);
8664 // Shift sign bit right or left if the two operands have different types.
8665 if (SrcVT.bitsGT(VT)) {
8666 // Op0 is MVT::f32, Op1 is MVT::f64.
8667 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, SignBit);
8668 SignBit = DAG.getNode(X86ISD::FSRL, dl, MVT::v2f64, SignBit,
8669 DAG.getConstant(32, MVT::i32));
8670 SignBit = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, SignBit);
8671 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, SignBit,
8672 DAG.getIntPtrConstant(0));
8675 // Clear first operand sign bit.
8677 if (VT == MVT::f64) {
8678 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63)))));
8679 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0))));
8681 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31)))));
8682 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
8683 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
8684 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
8686 C = ConstantVector::get(CV);
8687 CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
8688 SDValue Mask2 = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
8689 MachinePointerInfo::getConstantPool(),
8690 false, false, false, 16);
8691 SDValue Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Mask2);
8693 // Or the value with the sign bit.
8694 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit);
8697 static SDValue LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) {
8698 SDValue N0 = Op.getOperand(0);
8699 DebugLoc dl = Op.getDebugLoc();
8700 EVT VT = Op.getValueType();
8702 // Lower ISD::FGETSIGN to (AND (X86ISD::FGETSIGNx86 ...) 1).
8703 SDValue xFGETSIGN = DAG.getNode(X86ISD::FGETSIGNx86, dl, VT, N0,
8704 DAG.getConstant(1, VT));
8705 return DAG.getNode(ISD::AND, dl, VT, xFGETSIGN, DAG.getConstant(1, VT));
8708 // LowerVectorAllZeroTest - Check whether an OR'd tree is PTEST-able.
8710 SDValue X86TargetLowering::LowerVectorAllZeroTest(SDValue Op, SelectionDAG &DAG) const {
8711 assert(Op.getOpcode() == ISD::OR && "Only check OR'd tree.");
8713 if (!Subtarget->hasSSE41())
8716 if (!Op->hasOneUse())
8719 SDNode *N = Op.getNode();
8720 DebugLoc DL = N->getDebugLoc();
8722 SmallVector<SDValue, 8> Opnds;
8723 DenseMap<SDValue, unsigned> VecInMap;
8724 EVT VT = MVT::Other;
8726 // Recognize a special case where a vector is casted into wide integer to
8728 Opnds.push_back(N->getOperand(0));
8729 Opnds.push_back(N->getOperand(1));
8731 for (unsigned Slot = 0, e = Opnds.size(); Slot < e; ++Slot) {
8732 SmallVector<SDValue, 8>::const_iterator I = Opnds.begin() + Slot;
8733 // BFS traverse all OR'd operands.
8734 if (I->getOpcode() == ISD::OR) {
8735 Opnds.push_back(I->getOperand(0));
8736 Opnds.push_back(I->getOperand(1));
8737 // Re-evaluate the number of nodes to be traversed.
8738 e += 2; // 2 more nodes (LHS and RHS) are pushed.
8742 // Quit if a non-EXTRACT_VECTOR_ELT
8743 if (I->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
8746 // Quit if without a constant index.
8747 SDValue Idx = I->getOperand(1);
8748 if (!isa<ConstantSDNode>(Idx))
8751 SDValue ExtractedFromVec = I->getOperand(0);
8752 DenseMap<SDValue, unsigned>::iterator M = VecInMap.find(ExtractedFromVec);
8753 if (M == VecInMap.end()) {
8754 VT = ExtractedFromVec.getValueType();
8755 // Quit if not 128/256-bit vector.
8756 if (!VT.is128BitVector() && !VT.is256BitVector())
8758 // Quit if not the same type.
8759 if (VecInMap.begin() != VecInMap.end() &&
8760 VT != VecInMap.begin()->first.getValueType())
8762 M = VecInMap.insert(std::make_pair(ExtractedFromVec, 0)).first;
8764 M->second |= 1U << cast<ConstantSDNode>(Idx)->getZExtValue();
8767 assert((VT.is128BitVector() || VT.is256BitVector()) &&
8768 "Not extracted from 128-/256-bit vector.");
8770 unsigned FullMask = (1U << VT.getVectorNumElements()) - 1U;
8771 SmallVector<SDValue, 8> VecIns;
8773 for (DenseMap<SDValue, unsigned>::const_iterator
8774 I = VecInMap.begin(), E = VecInMap.end(); I != E; ++I) {
8775 // Quit if not all elements are used.
8776 if (I->second != FullMask)
8778 VecIns.push_back(I->first);
8781 EVT TestVT = VT.is128BitVector() ? MVT::v2i64 : MVT::v4i64;
8783 // Cast all vectors into TestVT for PTEST.
8784 for (unsigned i = 0, e = VecIns.size(); i < e; ++i)
8785 VecIns[i] = DAG.getNode(ISD::BITCAST, DL, TestVT, VecIns[i]);
8787 // If more than one full vectors are evaluated, OR them first before PTEST.
8788 for (unsigned Slot = 0, e = VecIns.size(); e - Slot > 1; Slot += 2, e += 1) {
8789 // Each iteration will OR 2 nodes and append the result until there is only
8790 // 1 node left, i.e. the final OR'd value of all vectors.
8791 SDValue LHS = VecIns[Slot];
8792 SDValue RHS = VecIns[Slot + 1];
8793 VecIns.push_back(DAG.getNode(ISD::OR, DL, TestVT, LHS, RHS));
8796 return DAG.getNode(X86ISD::PTEST, DL, MVT::i32,
8797 VecIns.back(), VecIns.back());
8800 /// Emit nodes that will be selected as "test Op0,Op0", or something
8802 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC,
8803 SelectionDAG &DAG) const {
8804 DebugLoc dl = Op.getDebugLoc();
8806 // CF and OF aren't always set the way we want. Determine which
8807 // of these we need.
8808 bool NeedCF = false;
8809 bool NeedOF = false;
8812 case X86::COND_A: case X86::COND_AE:
8813 case X86::COND_B: case X86::COND_BE:
8816 case X86::COND_G: case X86::COND_GE:
8817 case X86::COND_L: case X86::COND_LE:
8818 case X86::COND_O: case X86::COND_NO:
8823 // See if we can use the EFLAGS value from the operand instead of
8824 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
8825 // we prove that the arithmetic won't overflow, we can't use OF or CF.
8826 if (Op.getResNo() != 0 || NeedOF || NeedCF)
8827 // Emit a CMP with 0, which is the TEST pattern.
8828 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
8829 DAG.getConstant(0, Op.getValueType()));
8831 unsigned Opcode = 0;
8832 unsigned NumOperands = 0;
8834 // Truncate operations may prevent the merge of the SETCC instruction
8835 // and the arithmetic intruction before it. Attempt to truncate the operands
8836 // of the arithmetic instruction and use a reduced bit-width instruction.
8837 bool NeedTruncation = false;
8838 SDValue ArithOp = Op;
8839 if (Op->getOpcode() == ISD::TRUNCATE && Op->hasOneUse()) {
8840 SDValue Arith = Op->getOperand(0);
8841 // Both the trunc and the arithmetic op need to have one user each.
8842 if (Arith->hasOneUse())
8843 switch (Arith.getOpcode()) {
8850 NeedTruncation = true;
8856 // NOTICE: In the code below we use ArithOp to hold the arithmetic operation
8857 // which may be the result of a CAST. We use the variable 'Op', which is the
8858 // non-casted variable when we check for possible users.
8859 switch (ArithOp.getOpcode()) {
8861 // Due to an isel shortcoming, be conservative if this add is likely to be
8862 // selected as part of a load-modify-store instruction. When the root node
8863 // in a match is a store, isel doesn't know how to remap non-chain non-flag
8864 // uses of other nodes in the match, such as the ADD in this case. This
8865 // leads to the ADD being left around and reselected, with the result being
8866 // two adds in the output. Alas, even if none our users are stores, that
8867 // doesn't prove we're O.K. Ergo, if we have any parents that aren't
8868 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require
8869 // climbing the DAG back to the root, and it doesn't seem to be worth the
8871 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
8872 UE = Op.getNode()->use_end(); UI != UE; ++UI)
8873 if (UI->getOpcode() != ISD::CopyToReg &&
8874 UI->getOpcode() != ISD::SETCC &&
8875 UI->getOpcode() != ISD::STORE)
8878 if (ConstantSDNode *C =
8879 dyn_cast<ConstantSDNode>(ArithOp.getNode()->getOperand(1))) {
8880 // An add of one will be selected as an INC.
8881 if (C->getAPIntValue() == 1) {
8882 Opcode = X86ISD::INC;
8887 // An add of negative one (subtract of one) will be selected as a DEC.
8888 if (C->getAPIntValue().isAllOnesValue()) {
8889 Opcode = X86ISD::DEC;
8895 // Otherwise use a regular EFLAGS-setting add.
8896 Opcode = X86ISD::ADD;
8900 // If the primary and result isn't used, don't bother using X86ISD::AND,
8901 // because a TEST instruction will be better.
8902 bool NonFlagUse = false;
8903 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
8904 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
8906 unsigned UOpNo = UI.getOperandNo();
8907 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
8908 // Look pass truncate.
8909 UOpNo = User->use_begin().getOperandNo();
8910 User = *User->use_begin();
8913 if (User->getOpcode() != ISD::BRCOND &&
8914 User->getOpcode() != ISD::SETCC &&
8915 !(User->getOpcode() == ISD::SELECT && UOpNo == 0)) {
8928 // Due to the ISEL shortcoming noted above, be conservative if this op is
8929 // likely to be selected as part of a load-modify-store instruction.
8930 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
8931 UE = Op.getNode()->use_end(); UI != UE; ++UI)
8932 if (UI->getOpcode() == ISD::STORE)
8935 // Otherwise use a regular EFLAGS-setting instruction.
8936 switch (ArithOp.getOpcode()) {
8937 default: llvm_unreachable("unexpected operator!");
8938 case ISD::SUB: Opcode = X86ISD::SUB; break;
8939 case ISD::XOR: Opcode = X86ISD::XOR; break;
8940 case ISD::AND: Opcode = X86ISD::AND; break;
8942 if (!NeedTruncation && (X86CC == X86::COND_E || X86CC == X86::COND_NE)) {
8943 SDValue EFLAGS = LowerVectorAllZeroTest(Op, DAG);
8944 if (EFLAGS.getNode())
8947 Opcode = X86ISD::OR;
8961 return SDValue(Op.getNode(), 1);
8967 // If we found that truncation is beneficial, perform the truncation and
8969 if (NeedTruncation) {
8970 EVT VT = Op.getValueType();
8971 SDValue WideVal = Op->getOperand(0);
8972 EVT WideVT = WideVal.getValueType();
8973 unsigned ConvertedOp = 0;
8974 // Use a target machine opcode to prevent further DAGCombine
8975 // optimizations that may separate the arithmetic operations
8976 // from the setcc node.
8977 switch (WideVal.getOpcode()) {
8979 case ISD::ADD: ConvertedOp = X86ISD::ADD; break;
8980 case ISD::SUB: ConvertedOp = X86ISD::SUB; break;
8981 case ISD::AND: ConvertedOp = X86ISD::AND; break;
8982 case ISD::OR: ConvertedOp = X86ISD::OR; break;
8983 case ISD::XOR: ConvertedOp = X86ISD::XOR; break;
8987 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
8988 if (TLI.isOperationLegal(WideVal.getOpcode(), WideVT)) {
8989 SDValue V0 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(0));
8990 SDValue V1 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(1));
8991 Op = DAG.getNode(ConvertedOp, dl, VT, V0, V1);
8997 // Emit a CMP with 0, which is the TEST pattern.
8998 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
8999 DAG.getConstant(0, Op.getValueType()));
9001 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
9002 SmallVector<SDValue, 4> Ops;
9003 for (unsigned i = 0; i != NumOperands; ++i)
9004 Ops.push_back(Op.getOperand(i));
9006 SDValue New = DAG.getNode(Opcode, dl, VTs, &Ops[0], NumOperands);
9007 DAG.ReplaceAllUsesWith(Op, New);
9008 return SDValue(New.getNode(), 1);
9011 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
9013 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
9014 SelectionDAG &DAG) const {
9015 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1))
9016 if (C->getAPIntValue() == 0)
9017 return EmitTest(Op0, X86CC, DAG);
9019 DebugLoc dl = Op0.getDebugLoc();
9020 if ((Op0.getValueType() == MVT::i8 || Op0.getValueType() == MVT::i16 ||
9021 Op0.getValueType() == MVT::i32 || Op0.getValueType() == MVT::i64)) {
9022 // Use SUB instead of CMP to enable CSE between SUB and CMP.
9023 SDVTList VTs = DAG.getVTList(Op0.getValueType(), MVT::i32);
9024 SDValue Sub = DAG.getNode(X86ISD::SUB, dl, VTs,
9026 return SDValue(Sub.getNode(), 1);
9028 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
9031 /// Convert a comparison if required by the subtarget.
9032 SDValue X86TargetLowering::ConvertCmpIfNecessary(SDValue Cmp,
9033 SelectionDAG &DAG) const {
9034 // If the subtarget does not support the FUCOMI instruction, floating-point
9035 // comparisons have to be converted.
9036 if (Subtarget->hasCMov() ||
9037 Cmp.getOpcode() != X86ISD::CMP ||
9038 !Cmp.getOperand(0).getValueType().isFloatingPoint() ||
9039 !Cmp.getOperand(1).getValueType().isFloatingPoint())
9042 // The instruction selector will select an FUCOM instruction instead of
9043 // FUCOMI, which writes the comparison result to FPSW instead of EFLAGS. Hence
9044 // build an SDNode sequence that transfers the result from FPSW into EFLAGS:
9045 // (X86sahf (trunc (srl (X86fp_stsw (trunc (X86cmp ...)), 8))))
9046 DebugLoc dl = Cmp.getDebugLoc();
9047 SDValue TruncFPSW = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, Cmp);
9048 SDValue FNStSW = DAG.getNode(X86ISD::FNSTSW16r, dl, MVT::i16, TruncFPSW);
9049 SDValue Srl = DAG.getNode(ISD::SRL, dl, MVT::i16, FNStSW,
9050 DAG.getConstant(8, MVT::i8));
9051 SDValue TruncSrl = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Srl);
9052 return DAG.getNode(X86ISD::SAHF, dl, MVT::i32, TruncSrl);
9055 static bool isAllOnes(SDValue V) {
9056 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
9057 return C && C->isAllOnesValue();
9060 /// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node
9061 /// if it's possible.
9062 SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC,
9063 DebugLoc dl, SelectionDAG &DAG) const {
9064 SDValue Op0 = And.getOperand(0);
9065 SDValue Op1 = And.getOperand(1);
9066 if (Op0.getOpcode() == ISD::TRUNCATE)
9067 Op0 = Op0.getOperand(0);
9068 if (Op1.getOpcode() == ISD::TRUNCATE)
9069 Op1 = Op1.getOperand(0);
9072 if (Op1.getOpcode() == ISD::SHL)
9073 std::swap(Op0, Op1);
9074 if (Op0.getOpcode() == ISD::SHL) {
9075 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0)))
9076 if (And00C->getZExtValue() == 1) {
9077 // If we looked past a truncate, check that it's only truncating away
9079 unsigned BitWidth = Op0.getValueSizeInBits();
9080 unsigned AndBitWidth = And.getValueSizeInBits();
9081 if (BitWidth > AndBitWidth) {
9083 DAG.ComputeMaskedBits(Op0, Zeros, Ones);
9084 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth)
9088 RHS = Op0.getOperand(1);
9090 } else if (Op1.getOpcode() == ISD::Constant) {
9091 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1);
9092 uint64_t AndRHSVal = AndRHS->getZExtValue();
9093 SDValue AndLHS = Op0;
9095 if (AndRHSVal == 1 && AndLHS.getOpcode() == ISD::SRL) {
9096 LHS = AndLHS.getOperand(0);
9097 RHS = AndLHS.getOperand(1);
9100 // Use BT if the immediate can't be encoded in a TEST instruction.
9101 if (!isUInt<32>(AndRHSVal) && isPowerOf2_64(AndRHSVal)) {
9103 RHS = DAG.getConstant(Log2_64_Ceil(AndRHSVal), LHS.getValueType());
9107 if (LHS.getNode()) {
9108 // If the LHS is of the form (x ^ -1) then replace the LHS with x and flip
9109 // the condition code later.
9110 bool Invert = false;
9111 if (LHS.getOpcode() == ISD::XOR && isAllOnes(LHS.getOperand(1))) {
9113 LHS = LHS.getOperand(0);
9116 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT
9117 // instruction. Since the shift amount is in-range-or-undefined, we know
9118 // that doing a bittest on the i32 value is ok. We extend to i32 because
9119 // the encoding for the i16 version is larger than the i32 version.
9120 // Also promote i16 to i32 for performance / code size reason.
9121 if (LHS.getValueType() == MVT::i8 ||
9122 LHS.getValueType() == MVT::i16)
9123 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
9125 // If the operand types disagree, extend the shift amount to match. Since
9126 // BT ignores high bits (like shifts) we can use anyextend.
9127 if (LHS.getValueType() != RHS.getValueType())
9128 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
9130 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
9131 X86::CondCode Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
9132 // Flip the condition if the LHS was a not instruction
9134 Cond = X86::GetOppositeBranchCondition(Cond);
9135 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
9136 DAG.getConstant(Cond, MVT::i8), BT);
9142 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
9144 if (Op.getValueType().isVector()) return LowerVSETCC(Op, DAG);
9146 assert(Op.getValueType() == MVT::i8 && "SetCC type must be 8-bit integer");
9147 SDValue Op0 = Op.getOperand(0);
9148 SDValue Op1 = Op.getOperand(1);
9149 DebugLoc dl = Op.getDebugLoc();
9150 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
9152 // Optimize to BT if possible.
9153 // Lower (X & (1 << N)) == 0 to BT(X, N).
9154 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
9155 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
9156 if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() &&
9157 Op1.getOpcode() == ISD::Constant &&
9158 cast<ConstantSDNode>(Op1)->isNullValue() &&
9159 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
9160 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG);
9161 if (NewSetCC.getNode())
9165 // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of
9167 if (Op1.getOpcode() == ISD::Constant &&
9168 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 ||
9169 cast<ConstantSDNode>(Op1)->isNullValue()) &&
9170 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
9172 // If the input is a setcc, then reuse the input setcc or use a new one with
9173 // the inverted condition.
9174 if (Op0.getOpcode() == X86ISD::SETCC) {
9175 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0);
9176 bool Invert = (CC == ISD::SETNE) ^
9177 cast<ConstantSDNode>(Op1)->isNullValue();
9178 if (!Invert) return Op0;
9180 CCode = X86::GetOppositeBranchCondition(CCode);
9181 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
9182 DAG.getConstant(CCode, MVT::i8), Op0.getOperand(1));
9186 bool isFP = Op1.getValueType().isFloatingPoint();
9187 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG);
9188 if (X86CC == X86::COND_INVALID)
9191 SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, DAG);
9192 EFLAGS = ConvertCmpIfNecessary(EFLAGS, DAG);
9193 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
9194 DAG.getConstant(X86CC, MVT::i8), EFLAGS);
9197 // Lower256IntVSETCC - Break a VSETCC 256-bit integer VSETCC into two new 128
9198 // ones, and then concatenate the result back.
9199 static SDValue Lower256IntVSETCC(SDValue Op, SelectionDAG &DAG) {
9200 EVT VT = Op.getValueType();
9202 assert(VT.is256BitVector() && Op.getOpcode() == ISD::SETCC &&
9203 "Unsupported value type for operation");
9205 unsigned NumElems = VT.getVectorNumElements();
9206 DebugLoc dl = Op.getDebugLoc();
9207 SDValue CC = Op.getOperand(2);
9209 // Extract the LHS vectors
9210 SDValue LHS = Op.getOperand(0);
9211 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
9212 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
9214 // Extract the RHS vectors
9215 SDValue RHS = Op.getOperand(1);
9216 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
9217 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
9219 // Issue the operation on the smaller types and concatenate the result back
9220 MVT EltVT = VT.getVectorElementType().getSimpleVT();
9221 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
9222 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
9223 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1, CC),
9224 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC));
9227 SDValue X86TargetLowering::LowerVSETCC(SDValue Op, SelectionDAG &DAG) const {
9229 SDValue Op0 = Op.getOperand(0);
9230 SDValue Op1 = Op.getOperand(1);
9231 SDValue CC = Op.getOperand(2);
9232 EVT VT = Op.getValueType();
9233 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
9234 bool isFP = Op.getOperand(1).getValueType().isFloatingPoint();
9235 DebugLoc dl = Op.getDebugLoc();
9239 EVT EltVT = Op0.getValueType().getVectorElementType();
9240 assert(EltVT == MVT::f32 || EltVT == MVT::f64);
9246 // SSE Condition code mapping:
9255 switch (SetCCOpcode) {
9256 default: llvm_unreachable("Unexpected SETCC condition");
9258 case ISD::SETEQ: SSECC = 0; break;
9260 case ISD::SETGT: Swap = true; // Fallthrough
9262 case ISD::SETOLT: SSECC = 1; break;
9264 case ISD::SETGE: Swap = true; // Fallthrough
9266 case ISD::SETOLE: SSECC = 2; break;
9267 case ISD::SETUO: SSECC = 3; break;
9269 case ISD::SETNE: SSECC = 4; break;
9270 case ISD::SETULE: Swap = true; // Fallthrough
9271 case ISD::SETUGE: SSECC = 5; break;
9272 case ISD::SETULT: Swap = true; // Fallthrough
9273 case ISD::SETUGT: SSECC = 6; break;
9274 case ISD::SETO: SSECC = 7; break;
9276 case ISD::SETONE: SSECC = 8; break;
9279 std::swap(Op0, Op1);
9281 // In the two special cases we can't handle, emit two comparisons.
9284 unsigned CombineOpc;
9285 if (SetCCOpcode == ISD::SETUEQ) {
9286 CC0 = 3; CC1 = 0; CombineOpc = ISD::OR;
9288 assert(SetCCOpcode == ISD::SETONE);
9289 CC0 = 7; CC1 = 4; CombineOpc = ISD::AND;
9292 SDValue Cmp0 = DAG.getNode(X86ISD::CMPP, dl, VT, Op0, Op1,
9293 DAG.getConstant(CC0, MVT::i8));
9294 SDValue Cmp1 = DAG.getNode(X86ISD::CMPP, dl, VT, Op0, Op1,
9295 DAG.getConstant(CC1, MVT::i8));
9296 return DAG.getNode(CombineOpc, dl, VT, Cmp0, Cmp1);
9298 // Handle all other FP comparisons here.
9299 return DAG.getNode(X86ISD::CMPP, dl, VT, Op0, Op1,
9300 DAG.getConstant(SSECC, MVT::i8));
9303 // Break 256-bit integer vector compare into smaller ones.
9304 if (VT.is256BitVector() && !Subtarget->hasInt256())
9305 return Lower256IntVSETCC(Op, DAG);
9307 // We are handling one of the integer comparisons here. Since SSE only has
9308 // GT and EQ comparisons for integer, swapping operands and multiple
9309 // operations may be required for some comparisons.
9311 bool Swap = false, Invert = false, FlipSigns = false;
9313 switch (SetCCOpcode) {
9314 default: llvm_unreachable("Unexpected SETCC condition");
9315 case ISD::SETNE: Invert = true;
9316 case ISD::SETEQ: Opc = X86ISD::PCMPEQ; break;
9317 case ISD::SETLT: Swap = true;
9318 case ISD::SETGT: Opc = X86ISD::PCMPGT; break;
9319 case ISD::SETGE: Swap = true;
9320 case ISD::SETLE: Opc = X86ISD::PCMPGT; Invert = true; break;
9321 case ISD::SETULT: Swap = true;
9322 case ISD::SETUGT: Opc = X86ISD::PCMPGT; FlipSigns = true; break;
9323 case ISD::SETUGE: Swap = true;
9324 case ISD::SETULE: Opc = X86ISD::PCMPGT; FlipSigns = true; Invert = true; break;
9327 std::swap(Op0, Op1);
9329 // Check that the operation in question is available (most are plain SSE2,
9330 // but PCMPGTQ and PCMPEQQ have different requirements).
9331 if (VT == MVT::v2i64) {
9332 if (Opc == X86ISD::PCMPGT && !Subtarget->hasSSE42())
9334 if (Opc == X86ISD::PCMPEQ && !Subtarget->hasSSE41()) {
9335 // If pcmpeqq is missing but pcmpeqd is available synthesize pcmpeqq with
9336 // pcmpeqd + pshufd + pand.
9337 assert(Subtarget->hasSSE2() && !FlipSigns && "Don't know how to lower!");
9339 // First cast everything to the right type,
9340 Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0);
9341 Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1);
9344 SDValue Result = DAG.getNode(Opc, dl, MVT::v4i32, Op0, Op1);
9346 // Make sure the lower and upper halves are both all-ones.
9347 const int Mask[] = { 1, 0, 3, 2 };
9348 SDValue Shuf = DAG.getVectorShuffle(MVT::v4i32, dl, Result, Result, Mask);
9349 Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, Result, Shuf);
9352 Result = DAG.getNOT(dl, Result, MVT::v4i32);
9354 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
9358 // Since SSE has no unsigned integer comparisons, we need to flip the sign
9359 // bits of the inputs before performing those operations.
9361 EVT EltVT = VT.getVectorElementType();
9362 SDValue SignBit = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()),
9364 std::vector<SDValue> SignBits(VT.getVectorNumElements(), SignBit);
9365 SDValue SignVec = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &SignBits[0],
9367 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SignVec);
9368 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SignVec);
9371 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
9373 // If the logical-not of the result is required, perform that now.
9375 Result = DAG.getNOT(dl, Result, VT);
9380 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
9381 static bool isX86LogicalCmp(SDValue Op) {
9382 unsigned Opc = Op.getNode()->getOpcode();
9383 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI ||
9384 Opc == X86ISD::SAHF)
9386 if (Op.getResNo() == 1 &&
9387 (Opc == X86ISD::ADD ||
9388 Opc == X86ISD::SUB ||
9389 Opc == X86ISD::ADC ||
9390 Opc == X86ISD::SBB ||
9391 Opc == X86ISD::SMUL ||
9392 Opc == X86ISD::UMUL ||
9393 Opc == X86ISD::INC ||
9394 Opc == X86ISD::DEC ||
9395 Opc == X86ISD::OR ||
9396 Opc == X86ISD::XOR ||
9397 Opc == X86ISD::AND))
9400 if (Op.getResNo() == 2 && Opc == X86ISD::UMUL)
9406 static bool isZero(SDValue V) {
9407 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
9408 return C && C->isNullValue();
9411 static bool isTruncWithZeroHighBitsInput(SDValue V, SelectionDAG &DAG) {
9412 if (V.getOpcode() != ISD::TRUNCATE)
9415 SDValue VOp0 = V.getOperand(0);
9416 unsigned InBits = VOp0.getValueSizeInBits();
9417 unsigned Bits = V.getValueSizeInBits();
9418 return DAG.MaskedValueIsZero(VOp0, APInt::getHighBitsSet(InBits,InBits-Bits));
9421 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
9422 bool addTest = true;
9423 SDValue Cond = Op.getOperand(0);
9424 SDValue Op1 = Op.getOperand(1);
9425 SDValue Op2 = Op.getOperand(2);
9426 DebugLoc DL = Op.getDebugLoc();
9429 if (Cond.getOpcode() == ISD::SETCC) {
9430 SDValue NewCond = LowerSETCC(Cond, DAG);
9431 if (NewCond.getNode())
9435 // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y
9436 // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y
9437 // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y
9438 // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y
9439 if (Cond.getOpcode() == X86ISD::SETCC &&
9440 Cond.getOperand(1).getOpcode() == X86ISD::CMP &&
9441 isZero(Cond.getOperand(1).getOperand(1))) {
9442 SDValue Cmp = Cond.getOperand(1);
9444 unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue();
9446 if ((isAllOnes(Op1) || isAllOnes(Op2)) &&
9447 (CondCode == X86::COND_E || CondCode == X86::COND_NE)) {
9448 SDValue Y = isAllOnes(Op2) ? Op1 : Op2;
9450 SDValue CmpOp0 = Cmp.getOperand(0);
9451 // Apply further optimizations for special cases
9452 // (select (x != 0), -1, 0) -> neg & sbb
9453 // (select (x == 0), 0, -1) -> neg & sbb
9454 if (ConstantSDNode *YC = dyn_cast<ConstantSDNode>(Y))
9455 if (YC->isNullValue() &&
9456 (isAllOnes(Op1) == (CondCode == X86::COND_NE))) {
9457 SDVTList VTs = DAG.getVTList(CmpOp0.getValueType(), MVT::i32);
9458 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, VTs,
9459 DAG.getConstant(0, CmpOp0.getValueType()),
9461 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
9462 DAG.getConstant(X86::COND_B, MVT::i8),
9463 SDValue(Neg.getNode(), 1));
9467 Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32,
9468 CmpOp0, DAG.getConstant(1, CmpOp0.getValueType()));
9469 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
9471 SDValue Res = // Res = 0 or -1.
9472 DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
9473 DAG.getConstant(X86::COND_B, MVT::i8), Cmp);
9475 if (isAllOnes(Op1) != (CondCode == X86::COND_E))
9476 Res = DAG.getNOT(DL, Res, Res.getValueType());
9478 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2);
9479 if (N2C == 0 || !N2C->isNullValue())
9480 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y);
9485 // Look past (and (setcc_carry (cmp ...)), 1).
9486 if (Cond.getOpcode() == ISD::AND &&
9487 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
9488 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
9489 if (C && C->getAPIntValue() == 1)
9490 Cond = Cond.getOperand(0);
9493 // If condition flag is set by a X86ISD::CMP, then use it as the condition
9494 // setting operand in place of the X86ISD::SETCC.
9495 unsigned CondOpcode = Cond.getOpcode();
9496 if (CondOpcode == X86ISD::SETCC ||
9497 CondOpcode == X86ISD::SETCC_CARRY) {
9498 CC = Cond.getOperand(0);
9500 SDValue Cmp = Cond.getOperand(1);
9501 unsigned Opc = Cmp.getOpcode();
9502 EVT VT = Op.getValueType();
9504 bool IllegalFPCMov = false;
9505 if (VT.isFloatingPoint() && !VT.isVector() &&
9506 !isScalarFPTypeInSSEReg(VT)) // FPStack?
9507 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
9509 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
9510 Opc == X86ISD::BT) { // FIXME
9514 } else if (CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
9515 CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
9516 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
9517 Cond.getOperand(0).getValueType() != MVT::i8)) {
9518 SDValue LHS = Cond.getOperand(0);
9519 SDValue RHS = Cond.getOperand(1);
9523 switch (CondOpcode) {
9524 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
9525 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
9526 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
9527 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
9528 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
9529 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
9530 default: llvm_unreachable("unexpected overflowing operator");
9532 if (CondOpcode == ISD::UMULO)
9533 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
9536 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
9538 SDValue X86Op = DAG.getNode(X86Opcode, DL, VTs, LHS, RHS);
9540 if (CondOpcode == ISD::UMULO)
9541 Cond = X86Op.getValue(2);
9543 Cond = X86Op.getValue(1);
9545 CC = DAG.getConstant(X86Cond, MVT::i8);
9550 // Look pass the truncate if the high bits are known zero.
9551 if (isTruncWithZeroHighBitsInput(Cond, DAG))
9552 Cond = Cond.getOperand(0);
9554 // We know the result of AND is compared against zero. Try to match
9556 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
9557 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG);
9558 if (NewSetCC.getNode()) {
9559 CC = NewSetCC.getOperand(0);
9560 Cond = NewSetCC.getOperand(1);
9567 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
9568 Cond = EmitTest(Cond, X86::COND_NE, DAG);
9571 // a < b ? -1 : 0 -> RES = ~setcc_carry
9572 // a < b ? 0 : -1 -> RES = setcc_carry
9573 // a >= b ? -1 : 0 -> RES = setcc_carry
9574 // a >= b ? 0 : -1 -> RES = ~setcc_carry
9575 if (Cond.getOpcode() == X86ISD::SUB) {
9576 Cond = ConvertCmpIfNecessary(Cond, DAG);
9577 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue();
9579 if ((CondCode == X86::COND_AE || CondCode == X86::COND_B) &&
9580 (isAllOnes(Op1) || isAllOnes(Op2)) && (isZero(Op1) || isZero(Op2))) {
9581 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
9582 DAG.getConstant(X86::COND_B, MVT::i8), Cond);
9583 if (isAllOnes(Op1) != (CondCode == X86::COND_B))
9584 return DAG.getNOT(DL, Res, Res.getValueType());
9589 // X86 doesn't have an i8 cmov. If both operands are the result of a truncate
9590 // widen the cmov and push the truncate through. This avoids introducing a new
9591 // branch during isel and doesn't add any extensions.
9592 if (Op.getValueType() == MVT::i8 &&
9593 Op1.getOpcode() == ISD::TRUNCATE && Op2.getOpcode() == ISD::TRUNCATE) {
9594 SDValue T1 = Op1.getOperand(0), T2 = Op2.getOperand(0);
9595 if (T1.getValueType() == T2.getValueType() &&
9596 // Blacklist CopyFromReg to avoid partial register stalls.
9597 T1.getOpcode() != ISD::CopyFromReg && T2.getOpcode()!=ISD::CopyFromReg){
9598 SDVTList VTs = DAG.getVTList(T1.getValueType(), MVT::Glue);
9599 SDValue Cmov = DAG.getNode(X86ISD::CMOV, DL, VTs, T2, T1, CC, Cond);
9600 return DAG.getNode(ISD::TRUNCATE, DL, Op.getValueType(), Cmov);
9604 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
9605 // condition is true.
9606 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
9607 SDValue Ops[] = { Op2, Op1, CC, Cond };
9608 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops, array_lengthof(Ops));
9611 SDValue X86TargetLowering::LowerSIGN_EXTEND(SDValue Op,
9612 SelectionDAG &DAG) const {
9613 EVT VT = Op->getValueType(0);
9614 SDValue In = Op->getOperand(0);
9615 EVT InVT = In.getValueType();
9616 DebugLoc dl = Op->getDebugLoc();
9618 if ((VT != MVT::v4i64 || InVT != MVT::v4i32) &&
9619 (VT != MVT::v8i32 || InVT != MVT::v8i16))
9622 if (Subtarget->hasInt256())
9623 return DAG.getNode(X86ISD::VSEXT_MOVL, dl, VT, In);
9625 // Optimize vectors in AVX mode
9626 // Sign extend v8i16 to v8i32 and
9629 // Divide input vector into two parts
9630 // for v4i32 the shuffle mask will be { 0, 1, -1, -1} {2, 3, -1, -1}
9631 // use vpmovsx instruction to extend v4i32 -> v2i64; v8i16 -> v4i32
9632 // concat the vectors to original VT
9634 unsigned NumElems = InVT.getVectorNumElements();
9635 SDValue Undef = DAG.getUNDEF(InVT);
9637 SmallVector<int,8> ShufMask1(NumElems, -1);
9638 for (unsigned i = 0; i != NumElems/2; ++i)
9641 SDValue OpLo = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask1[0]);
9643 SmallVector<int,8> ShufMask2(NumElems, -1);
9644 for (unsigned i = 0; i != NumElems/2; ++i)
9645 ShufMask2[i] = i + NumElems/2;
9647 SDValue OpHi = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask2[0]);
9649 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), VT.getScalarType(),
9650 VT.getVectorNumElements()/2);
9652 OpLo = DAG.getNode(X86ISD::VSEXT_MOVL, dl, HalfVT, OpLo);
9653 OpHi = DAG.getNode(X86ISD::VSEXT_MOVL, dl, HalfVT, OpHi);
9655 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
9658 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
9659 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
9660 // from the AND / OR.
9661 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
9662 Opc = Op.getOpcode();
9663 if (Opc != ISD::OR && Opc != ISD::AND)
9665 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
9666 Op.getOperand(0).hasOneUse() &&
9667 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
9668 Op.getOperand(1).hasOneUse());
9671 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
9672 // 1 and that the SETCC node has a single use.
9673 static bool isXor1OfSetCC(SDValue Op) {
9674 if (Op.getOpcode() != ISD::XOR)
9676 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
9677 if (N1C && N1C->getAPIntValue() == 1) {
9678 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
9679 Op.getOperand(0).hasOneUse();
9684 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
9685 bool addTest = true;
9686 SDValue Chain = Op.getOperand(0);
9687 SDValue Cond = Op.getOperand(1);
9688 SDValue Dest = Op.getOperand(2);
9689 DebugLoc dl = Op.getDebugLoc();
9691 bool Inverted = false;
9693 if (Cond.getOpcode() == ISD::SETCC) {
9694 // Check for setcc([su]{add,sub,mul}o == 0).
9695 if (cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETEQ &&
9696 isa<ConstantSDNode>(Cond.getOperand(1)) &&
9697 cast<ConstantSDNode>(Cond.getOperand(1))->isNullValue() &&
9698 Cond.getOperand(0).getResNo() == 1 &&
9699 (Cond.getOperand(0).getOpcode() == ISD::SADDO ||
9700 Cond.getOperand(0).getOpcode() == ISD::UADDO ||
9701 Cond.getOperand(0).getOpcode() == ISD::SSUBO ||
9702 Cond.getOperand(0).getOpcode() == ISD::USUBO ||
9703 Cond.getOperand(0).getOpcode() == ISD::SMULO ||
9704 Cond.getOperand(0).getOpcode() == ISD::UMULO)) {
9706 Cond = Cond.getOperand(0);
9708 SDValue NewCond = LowerSETCC(Cond, DAG);
9709 if (NewCond.getNode())
9714 // FIXME: LowerXALUO doesn't handle these!!
9715 else if (Cond.getOpcode() == X86ISD::ADD ||
9716 Cond.getOpcode() == X86ISD::SUB ||
9717 Cond.getOpcode() == X86ISD::SMUL ||
9718 Cond.getOpcode() == X86ISD::UMUL)
9719 Cond = LowerXALUO(Cond, DAG);
9722 // Look pass (and (setcc_carry (cmp ...)), 1).
9723 if (Cond.getOpcode() == ISD::AND &&
9724 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
9725 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
9726 if (C && C->getAPIntValue() == 1)
9727 Cond = Cond.getOperand(0);
9730 // If condition flag is set by a X86ISD::CMP, then use it as the condition
9731 // setting operand in place of the X86ISD::SETCC.
9732 unsigned CondOpcode = Cond.getOpcode();
9733 if (CondOpcode == X86ISD::SETCC ||
9734 CondOpcode == X86ISD::SETCC_CARRY) {
9735 CC = Cond.getOperand(0);
9737 SDValue Cmp = Cond.getOperand(1);
9738 unsigned Opc = Cmp.getOpcode();
9739 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
9740 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
9744 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
9748 // These can only come from an arithmetic instruction with overflow,
9749 // e.g. SADDO, UADDO.
9750 Cond = Cond.getNode()->getOperand(1);
9756 CondOpcode = Cond.getOpcode();
9757 if (CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
9758 CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
9759 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
9760 Cond.getOperand(0).getValueType() != MVT::i8)) {
9761 SDValue LHS = Cond.getOperand(0);
9762 SDValue RHS = Cond.getOperand(1);
9766 switch (CondOpcode) {
9767 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
9768 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
9769 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
9770 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
9771 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
9772 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
9773 default: llvm_unreachable("unexpected overflowing operator");
9776 X86Cond = X86::GetOppositeBranchCondition((X86::CondCode)X86Cond);
9777 if (CondOpcode == ISD::UMULO)
9778 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
9781 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
9783 SDValue X86Op = DAG.getNode(X86Opcode, dl, VTs, LHS, RHS);
9785 if (CondOpcode == ISD::UMULO)
9786 Cond = X86Op.getValue(2);
9788 Cond = X86Op.getValue(1);
9790 CC = DAG.getConstant(X86Cond, MVT::i8);
9794 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
9795 SDValue Cmp = Cond.getOperand(0).getOperand(1);
9796 if (CondOpc == ISD::OR) {
9797 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
9798 // two branches instead of an explicit OR instruction with a
9800 if (Cmp == Cond.getOperand(1).getOperand(1) &&
9801 isX86LogicalCmp(Cmp)) {
9802 CC = Cond.getOperand(0).getOperand(0);
9803 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
9804 Chain, Dest, CC, Cmp);
9805 CC = Cond.getOperand(1).getOperand(0);
9809 } else { // ISD::AND
9810 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
9811 // two branches instead of an explicit AND instruction with a
9812 // separate test. However, we only do this if this block doesn't
9813 // have a fall-through edge, because this requires an explicit
9814 // jmp when the condition is false.
9815 if (Cmp == Cond.getOperand(1).getOperand(1) &&
9816 isX86LogicalCmp(Cmp) &&
9817 Op.getNode()->hasOneUse()) {
9818 X86::CondCode CCode =
9819 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
9820 CCode = X86::GetOppositeBranchCondition(CCode);
9821 CC = DAG.getConstant(CCode, MVT::i8);
9822 SDNode *User = *Op.getNode()->use_begin();
9823 // Look for an unconditional branch following this conditional branch.
9824 // We need this because we need to reverse the successors in order
9825 // to implement FCMP_OEQ.
9826 if (User->getOpcode() == ISD::BR) {
9827 SDValue FalseBB = User->getOperand(1);
9829 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
9830 assert(NewBR == User);
9834 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
9835 Chain, Dest, CC, Cmp);
9836 X86::CondCode CCode =
9837 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
9838 CCode = X86::GetOppositeBranchCondition(CCode);
9839 CC = DAG.getConstant(CCode, MVT::i8);
9845 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
9846 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
9847 // It should be transformed during dag combiner except when the condition
9848 // is set by a arithmetics with overflow node.
9849 X86::CondCode CCode =
9850 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
9851 CCode = X86::GetOppositeBranchCondition(CCode);
9852 CC = DAG.getConstant(CCode, MVT::i8);
9853 Cond = Cond.getOperand(0).getOperand(1);
9855 } else if (Cond.getOpcode() == ISD::SETCC &&
9856 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETOEQ) {
9857 // For FCMP_OEQ, we can emit
9858 // two branches instead of an explicit AND instruction with a
9859 // separate test. However, we only do this if this block doesn't
9860 // have a fall-through edge, because this requires an explicit
9861 // jmp when the condition is false.
9862 if (Op.getNode()->hasOneUse()) {
9863 SDNode *User = *Op.getNode()->use_begin();
9864 // Look for an unconditional branch following this conditional branch.
9865 // We need this because we need to reverse the successors in order
9866 // to implement FCMP_OEQ.
9867 if (User->getOpcode() == ISD::BR) {
9868 SDValue FalseBB = User->getOperand(1);
9870 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
9871 assert(NewBR == User);
9875 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
9876 Cond.getOperand(0), Cond.getOperand(1));
9877 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
9878 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
9879 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
9880 Chain, Dest, CC, Cmp);
9881 CC = DAG.getConstant(X86::COND_P, MVT::i8);
9886 } else if (Cond.getOpcode() == ISD::SETCC &&
9887 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETUNE) {
9888 // For FCMP_UNE, we can emit
9889 // two branches instead of an explicit AND instruction with a
9890 // separate test. However, we only do this if this block doesn't
9891 // have a fall-through edge, because this requires an explicit
9892 // jmp when the condition is false.
9893 if (Op.getNode()->hasOneUse()) {
9894 SDNode *User = *Op.getNode()->use_begin();
9895 // Look for an unconditional branch following this conditional branch.
9896 // We need this because we need to reverse the successors in order
9897 // to implement FCMP_UNE.
9898 if (User->getOpcode() == ISD::BR) {
9899 SDValue FalseBB = User->getOperand(1);
9901 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
9902 assert(NewBR == User);
9905 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
9906 Cond.getOperand(0), Cond.getOperand(1));
9907 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
9908 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
9909 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
9910 Chain, Dest, CC, Cmp);
9911 CC = DAG.getConstant(X86::COND_NP, MVT::i8);
9921 // Look pass the truncate if the high bits are known zero.
9922 if (isTruncWithZeroHighBitsInput(Cond, DAG))
9923 Cond = Cond.getOperand(0);
9925 // We know the result of AND is compared against zero. Try to match
9927 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
9928 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
9929 if (NewSetCC.getNode()) {
9930 CC = NewSetCC.getOperand(0);
9931 Cond = NewSetCC.getOperand(1);
9938 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
9939 Cond = EmitTest(Cond, X86::COND_NE, DAG);
9941 Cond = ConvertCmpIfNecessary(Cond, DAG);
9942 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
9943 Chain, Dest, CC, Cond);
9946 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
9947 // Calls to _alloca is needed to probe the stack when allocating more than 4k
9948 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
9949 // that the guard pages used by the OS virtual memory manager are allocated in
9950 // correct sequence.
9952 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
9953 SelectionDAG &DAG) const {
9954 assert((Subtarget->isTargetCygMing() || Subtarget->isTargetWindows() ||
9955 getTargetMachine().Options.EnableSegmentedStacks) &&
9956 "This should be used only on Windows targets or when segmented stacks "
9958 assert(!Subtarget->isTargetEnvMacho() && "Not implemented");
9959 DebugLoc dl = Op.getDebugLoc();
9962 SDValue Chain = Op.getOperand(0);
9963 SDValue Size = Op.getOperand(1);
9964 // FIXME: Ensure alignment here
9966 bool Is64Bit = Subtarget->is64Bit();
9967 EVT SPTy = Is64Bit ? MVT::i64 : MVT::i32;
9969 if (getTargetMachine().Options.EnableSegmentedStacks) {
9970 MachineFunction &MF = DAG.getMachineFunction();
9971 MachineRegisterInfo &MRI = MF.getRegInfo();
9974 // The 64 bit implementation of segmented stacks needs to clobber both r10
9975 // r11. This makes it impossible to use it along with nested parameters.
9976 const Function *F = MF.getFunction();
9978 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
9980 if (I->hasNestAttr())
9981 report_fatal_error("Cannot use segmented stacks with functions that "
9982 "have nested arguments.");
9985 const TargetRegisterClass *AddrRegClass =
9986 getRegClassFor(Subtarget->is64Bit() ? MVT::i64:MVT::i32);
9987 unsigned Vreg = MRI.createVirtualRegister(AddrRegClass);
9988 Chain = DAG.getCopyToReg(Chain, dl, Vreg, Size);
9989 SDValue Value = DAG.getNode(X86ISD::SEG_ALLOCA, dl, SPTy, Chain,
9990 DAG.getRegister(Vreg, SPTy));
9991 SDValue Ops1[2] = { Value, Chain };
9992 return DAG.getMergeValues(Ops1, 2, dl);
9995 unsigned Reg = (Subtarget->is64Bit() ? X86::RAX : X86::EAX);
9997 Chain = DAG.getCopyToReg(Chain, dl, Reg, Size, Flag);
9998 Flag = Chain.getValue(1);
9999 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
10001 Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag);
10002 Flag = Chain.getValue(1);
10004 Chain = DAG.getCopyFromReg(Chain, dl, RegInfo->getStackRegister(),
10007 SDValue Ops1[2] = { Chain.getValue(0), Chain };
10008 return DAG.getMergeValues(Ops1, 2, dl);
10012 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
10013 MachineFunction &MF = DAG.getMachineFunction();
10014 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
10016 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
10017 DebugLoc DL = Op.getDebugLoc();
10019 if (!Subtarget->is64Bit() || Subtarget->isTargetWin64()) {
10020 // vastart just stores the address of the VarArgsFrameIndex slot into the
10021 // memory location argument.
10022 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
10024 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
10025 MachinePointerInfo(SV), false, false, 0);
10029 // gp_offset (0 - 6 * 8)
10030 // fp_offset (48 - 48 + 8 * 16)
10031 // overflow_arg_area (point to parameters coming in memory).
10033 SmallVector<SDValue, 8> MemOps;
10034 SDValue FIN = Op.getOperand(1);
10036 SDValue Store = DAG.getStore(Op.getOperand(0), DL,
10037 DAG.getConstant(FuncInfo->getVarArgsGPOffset(),
10039 FIN, MachinePointerInfo(SV), false, false, 0);
10040 MemOps.push_back(Store);
10043 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
10044 FIN, DAG.getIntPtrConstant(4));
10045 Store = DAG.getStore(Op.getOperand(0), DL,
10046 DAG.getConstant(FuncInfo->getVarArgsFPOffset(),
10048 FIN, MachinePointerInfo(SV, 4), false, false, 0);
10049 MemOps.push_back(Store);
10051 // Store ptr to overflow_arg_area
10052 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
10053 FIN, DAG.getIntPtrConstant(4));
10054 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
10056 Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN,
10057 MachinePointerInfo(SV, 8),
10059 MemOps.push_back(Store);
10061 // Store ptr to reg_save_area.
10062 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
10063 FIN, DAG.getIntPtrConstant(8));
10064 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
10066 Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN,
10067 MachinePointerInfo(SV, 16), false, false, 0);
10068 MemOps.push_back(Store);
10069 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
10070 &MemOps[0], MemOps.size());
10073 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
10074 assert(Subtarget->is64Bit() &&
10075 "LowerVAARG only handles 64-bit va_arg!");
10076 assert((Subtarget->isTargetLinux() ||
10077 Subtarget->isTargetDarwin()) &&
10078 "Unhandled target in LowerVAARG");
10079 assert(Op.getNode()->getNumOperands() == 4);
10080 SDValue Chain = Op.getOperand(0);
10081 SDValue SrcPtr = Op.getOperand(1);
10082 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
10083 unsigned Align = Op.getConstantOperandVal(3);
10084 DebugLoc dl = Op.getDebugLoc();
10086 EVT ArgVT = Op.getNode()->getValueType(0);
10087 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
10088 uint32_t ArgSize = getDataLayout()->getTypeAllocSize(ArgTy);
10091 // Decide which area this value should be read from.
10092 // TODO: Implement the AMD64 ABI in its entirety. This simple
10093 // selection mechanism works only for the basic types.
10094 if (ArgVT == MVT::f80) {
10095 llvm_unreachable("va_arg for f80 not yet implemented");
10096 } else if (ArgVT.isFloatingPoint() && ArgSize <= 16 /*bytes*/) {
10097 ArgMode = 2; // Argument passed in XMM register. Use fp_offset.
10098 } else if (ArgVT.isInteger() && ArgSize <= 32 /*bytes*/) {
10099 ArgMode = 1; // Argument passed in GPR64 register(s). Use gp_offset.
10101 llvm_unreachable("Unhandled argument type in LowerVAARG");
10104 if (ArgMode == 2) {
10105 // Sanity Check: Make sure using fp_offset makes sense.
10106 assert(!getTargetMachine().Options.UseSoftFloat &&
10107 !(DAG.getMachineFunction()
10108 .getFunction()->getAttributes()
10109 .hasAttribute(AttributeSet::FunctionIndex,
10110 Attribute::NoImplicitFloat)) &&
10111 Subtarget->hasSSE1());
10114 // Insert VAARG_64 node into the DAG
10115 // VAARG_64 returns two values: Variable Argument Address, Chain
10116 SmallVector<SDValue, 11> InstOps;
10117 InstOps.push_back(Chain);
10118 InstOps.push_back(SrcPtr);
10119 InstOps.push_back(DAG.getConstant(ArgSize, MVT::i32));
10120 InstOps.push_back(DAG.getConstant(ArgMode, MVT::i8));
10121 InstOps.push_back(DAG.getConstant(Align, MVT::i32));
10122 SDVTList VTs = DAG.getVTList(getPointerTy(), MVT::Other);
10123 SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl,
10124 VTs, &InstOps[0], InstOps.size(),
10126 MachinePointerInfo(SV),
10128 /*Volatile=*/false,
10130 /*WriteMem=*/true);
10131 Chain = VAARG.getValue(1);
10133 // Load the next argument and return it
10134 return DAG.getLoad(ArgVT, dl,
10137 MachinePointerInfo(),
10138 false, false, false, 0);
10141 static SDValue LowerVACOPY(SDValue Op, const X86Subtarget *Subtarget,
10142 SelectionDAG &DAG) {
10143 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
10144 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
10145 SDValue Chain = Op.getOperand(0);
10146 SDValue DstPtr = Op.getOperand(1);
10147 SDValue SrcPtr = Op.getOperand(2);
10148 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
10149 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
10150 DebugLoc DL = Op.getDebugLoc();
10152 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr,
10153 DAG.getIntPtrConstant(24), 8, /*isVolatile*/false,
10155 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
10158 // getTargetVShiftNOde - Handle vector element shifts where the shift amount
10159 // may or may not be a constant. Takes immediate version of shift as input.
10160 static SDValue getTargetVShiftNode(unsigned Opc, DebugLoc dl, EVT VT,
10161 SDValue SrcOp, SDValue ShAmt,
10162 SelectionDAG &DAG) {
10163 assert(ShAmt.getValueType() == MVT::i32 && "ShAmt is not i32");
10165 if (isa<ConstantSDNode>(ShAmt)) {
10166 // Constant may be a TargetConstant. Use a regular constant.
10167 uint32_t ShiftAmt = cast<ConstantSDNode>(ShAmt)->getZExtValue();
10169 default: llvm_unreachable("Unknown target vector shift node");
10170 case X86ISD::VSHLI:
10171 case X86ISD::VSRLI:
10172 case X86ISD::VSRAI:
10173 return DAG.getNode(Opc, dl, VT, SrcOp,
10174 DAG.getConstant(ShiftAmt, MVT::i32));
10178 // Change opcode to non-immediate version
10180 default: llvm_unreachable("Unknown target vector shift node");
10181 case X86ISD::VSHLI: Opc = X86ISD::VSHL; break;
10182 case X86ISD::VSRLI: Opc = X86ISD::VSRL; break;
10183 case X86ISD::VSRAI: Opc = X86ISD::VSRA; break;
10186 // Need to build a vector containing shift amount
10187 // Shift amount is 32-bits, but SSE instructions read 64-bit, so fill with 0
10190 ShOps[1] = DAG.getConstant(0, MVT::i32);
10191 ShOps[2] = ShOps[3] = DAG.getUNDEF(MVT::i32);
10192 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, &ShOps[0], 4);
10194 // The return type has to be a 128-bit type with the same element
10195 // type as the input type.
10196 MVT EltVT = VT.getVectorElementType().getSimpleVT();
10197 EVT ShVT = MVT::getVectorVT(EltVT, 128/EltVT.getSizeInBits());
10199 ShAmt = DAG.getNode(ISD::BITCAST, dl, ShVT, ShAmt);
10200 return DAG.getNode(Opc, dl, VT, SrcOp, ShAmt);
10203 static SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) {
10204 DebugLoc dl = Op.getDebugLoc();
10205 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
10207 default: return SDValue(); // Don't custom lower most intrinsics.
10208 // Comparison intrinsics.
10209 case Intrinsic::x86_sse_comieq_ss:
10210 case Intrinsic::x86_sse_comilt_ss:
10211 case Intrinsic::x86_sse_comile_ss:
10212 case Intrinsic::x86_sse_comigt_ss:
10213 case Intrinsic::x86_sse_comige_ss:
10214 case Intrinsic::x86_sse_comineq_ss:
10215 case Intrinsic::x86_sse_ucomieq_ss:
10216 case Intrinsic::x86_sse_ucomilt_ss:
10217 case Intrinsic::x86_sse_ucomile_ss:
10218 case Intrinsic::x86_sse_ucomigt_ss:
10219 case Intrinsic::x86_sse_ucomige_ss:
10220 case Intrinsic::x86_sse_ucomineq_ss:
10221 case Intrinsic::x86_sse2_comieq_sd:
10222 case Intrinsic::x86_sse2_comilt_sd:
10223 case Intrinsic::x86_sse2_comile_sd:
10224 case Intrinsic::x86_sse2_comigt_sd:
10225 case Intrinsic::x86_sse2_comige_sd:
10226 case Intrinsic::x86_sse2_comineq_sd:
10227 case Intrinsic::x86_sse2_ucomieq_sd:
10228 case Intrinsic::x86_sse2_ucomilt_sd:
10229 case Intrinsic::x86_sse2_ucomile_sd:
10230 case Intrinsic::x86_sse2_ucomigt_sd:
10231 case Intrinsic::x86_sse2_ucomige_sd:
10232 case Intrinsic::x86_sse2_ucomineq_sd: {
10236 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
10237 case Intrinsic::x86_sse_comieq_ss:
10238 case Intrinsic::x86_sse2_comieq_sd:
10239 Opc = X86ISD::COMI;
10242 case Intrinsic::x86_sse_comilt_ss:
10243 case Intrinsic::x86_sse2_comilt_sd:
10244 Opc = X86ISD::COMI;
10247 case Intrinsic::x86_sse_comile_ss:
10248 case Intrinsic::x86_sse2_comile_sd:
10249 Opc = X86ISD::COMI;
10252 case Intrinsic::x86_sse_comigt_ss:
10253 case Intrinsic::x86_sse2_comigt_sd:
10254 Opc = X86ISD::COMI;
10257 case Intrinsic::x86_sse_comige_ss:
10258 case Intrinsic::x86_sse2_comige_sd:
10259 Opc = X86ISD::COMI;
10262 case Intrinsic::x86_sse_comineq_ss:
10263 case Intrinsic::x86_sse2_comineq_sd:
10264 Opc = X86ISD::COMI;
10267 case Intrinsic::x86_sse_ucomieq_ss:
10268 case Intrinsic::x86_sse2_ucomieq_sd:
10269 Opc = X86ISD::UCOMI;
10272 case Intrinsic::x86_sse_ucomilt_ss:
10273 case Intrinsic::x86_sse2_ucomilt_sd:
10274 Opc = X86ISD::UCOMI;
10277 case Intrinsic::x86_sse_ucomile_ss:
10278 case Intrinsic::x86_sse2_ucomile_sd:
10279 Opc = X86ISD::UCOMI;
10282 case Intrinsic::x86_sse_ucomigt_ss:
10283 case Intrinsic::x86_sse2_ucomigt_sd:
10284 Opc = X86ISD::UCOMI;
10287 case Intrinsic::x86_sse_ucomige_ss:
10288 case Intrinsic::x86_sse2_ucomige_sd:
10289 Opc = X86ISD::UCOMI;
10292 case Intrinsic::x86_sse_ucomineq_ss:
10293 case Intrinsic::x86_sse2_ucomineq_sd:
10294 Opc = X86ISD::UCOMI;
10299 SDValue LHS = Op.getOperand(1);
10300 SDValue RHS = Op.getOperand(2);
10301 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG);
10302 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!");
10303 SDValue Cond = DAG.getNode(Opc, dl, MVT::i32, LHS, RHS);
10304 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
10305 DAG.getConstant(X86CC, MVT::i8), Cond);
10306 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
10309 // Arithmetic intrinsics.
10310 case Intrinsic::x86_sse2_pmulu_dq:
10311 case Intrinsic::x86_avx2_pmulu_dq:
10312 return DAG.getNode(X86ISD::PMULUDQ, dl, Op.getValueType(),
10313 Op.getOperand(1), Op.getOperand(2));
10315 // SSE2/AVX2 sub with unsigned saturation intrinsics
10316 case Intrinsic::x86_sse2_psubus_b:
10317 case Intrinsic::x86_sse2_psubus_w:
10318 case Intrinsic::x86_avx2_psubus_b:
10319 case Intrinsic::x86_avx2_psubus_w:
10320 return DAG.getNode(X86ISD::SUBUS, dl, Op.getValueType(),
10321 Op.getOperand(1), Op.getOperand(2));
10323 // SSE3/AVX horizontal add/sub intrinsics
10324 case Intrinsic::x86_sse3_hadd_ps:
10325 case Intrinsic::x86_sse3_hadd_pd:
10326 case Intrinsic::x86_avx_hadd_ps_256:
10327 case Intrinsic::x86_avx_hadd_pd_256:
10328 case Intrinsic::x86_sse3_hsub_ps:
10329 case Intrinsic::x86_sse3_hsub_pd:
10330 case Intrinsic::x86_avx_hsub_ps_256:
10331 case Intrinsic::x86_avx_hsub_pd_256:
10332 case Intrinsic::x86_ssse3_phadd_w_128:
10333 case Intrinsic::x86_ssse3_phadd_d_128:
10334 case Intrinsic::x86_avx2_phadd_w:
10335 case Intrinsic::x86_avx2_phadd_d:
10336 case Intrinsic::x86_ssse3_phsub_w_128:
10337 case Intrinsic::x86_ssse3_phsub_d_128:
10338 case Intrinsic::x86_avx2_phsub_w:
10339 case Intrinsic::x86_avx2_phsub_d: {
10342 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
10343 case Intrinsic::x86_sse3_hadd_ps:
10344 case Intrinsic::x86_sse3_hadd_pd:
10345 case Intrinsic::x86_avx_hadd_ps_256:
10346 case Intrinsic::x86_avx_hadd_pd_256:
10347 Opcode = X86ISD::FHADD;
10349 case Intrinsic::x86_sse3_hsub_ps:
10350 case Intrinsic::x86_sse3_hsub_pd:
10351 case Intrinsic::x86_avx_hsub_ps_256:
10352 case Intrinsic::x86_avx_hsub_pd_256:
10353 Opcode = X86ISD::FHSUB;
10355 case Intrinsic::x86_ssse3_phadd_w_128:
10356 case Intrinsic::x86_ssse3_phadd_d_128:
10357 case Intrinsic::x86_avx2_phadd_w:
10358 case Intrinsic::x86_avx2_phadd_d:
10359 Opcode = X86ISD::HADD;
10361 case Intrinsic::x86_ssse3_phsub_w_128:
10362 case Intrinsic::x86_ssse3_phsub_d_128:
10363 case Intrinsic::x86_avx2_phsub_w:
10364 case Intrinsic::x86_avx2_phsub_d:
10365 Opcode = X86ISD::HSUB;
10368 return DAG.getNode(Opcode, dl, Op.getValueType(),
10369 Op.getOperand(1), Op.getOperand(2));
10372 // SSE2/SSE41/AVX2 integer max/min intrinsics.
10373 case Intrinsic::x86_sse2_pmaxu_b:
10374 case Intrinsic::x86_sse41_pmaxuw:
10375 case Intrinsic::x86_sse41_pmaxud:
10376 case Intrinsic::x86_avx2_pmaxu_b:
10377 case Intrinsic::x86_avx2_pmaxu_w:
10378 case Intrinsic::x86_avx2_pmaxu_d:
10379 case Intrinsic::x86_sse2_pminu_b:
10380 case Intrinsic::x86_sse41_pminuw:
10381 case Intrinsic::x86_sse41_pminud:
10382 case Intrinsic::x86_avx2_pminu_b:
10383 case Intrinsic::x86_avx2_pminu_w:
10384 case Intrinsic::x86_avx2_pminu_d:
10385 case Intrinsic::x86_sse41_pmaxsb:
10386 case Intrinsic::x86_sse2_pmaxs_w:
10387 case Intrinsic::x86_sse41_pmaxsd:
10388 case Intrinsic::x86_avx2_pmaxs_b:
10389 case Intrinsic::x86_avx2_pmaxs_w:
10390 case Intrinsic::x86_avx2_pmaxs_d:
10391 case Intrinsic::x86_sse41_pminsb:
10392 case Intrinsic::x86_sse2_pmins_w:
10393 case Intrinsic::x86_sse41_pminsd:
10394 case Intrinsic::x86_avx2_pmins_b:
10395 case Intrinsic::x86_avx2_pmins_w:
10396 case Intrinsic::x86_avx2_pmins_d: {
10399 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
10400 case Intrinsic::x86_sse2_pmaxu_b:
10401 case Intrinsic::x86_sse41_pmaxuw:
10402 case Intrinsic::x86_sse41_pmaxud:
10403 case Intrinsic::x86_avx2_pmaxu_b:
10404 case Intrinsic::x86_avx2_pmaxu_w:
10405 case Intrinsic::x86_avx2_pmaxu_d:
10406 Opcode = X86ISD::UMAX;
10408 case Intrinsic::x86_sse2_pminu_b:
10409 case Intrinsic::x86_sse41_pminuw:
10410 case Intrinsic::x86_sse41_pminud:
10411 case Intrinsic::x86_avx2_pminu_b:
10412 case Intrinsic::x86_avx2_pminu_w:
10413 case Intrinsic::x86_avx2_pminu_d:
10414 Opcode = X86ISD::UMIN;
10416 case Intrinsic::x86_sse41_pmaxsb:
10417 case Intrinsic::x86_sse2_pmaxs_w:
10418 case Intrinsic::x86_sse41_pmaxsd:
10419 case Intrinsic::x86_avx2_pmaxs_b:
10420 case Intrinsic::x86_avx2_pmaxs_w:
10421 case Intrinsic::x86_avx2_pmaxs_d:
10422 Opcode = X86ISD::SMAX;
10424 case Intrinsic::x86_sse41_pminsb:
10425 case Intrinsic::x86_sse2_pmins_w:
10426 case Intrinsic::x86_sse41_pminsd:
10427 case Intrinsic::x86_avx2_pmins_b:
10428 case Intrinsic::x86_avx2_pmins_w:
10429 case Intrinsic::x86_avx2_pmins_d:
10430 Opcode = X86ISD::SMIN;
10433 return DAG.getNode(Opcode, dl, Op.getValueType(),
10434 Op.getOperand(1), Op.getOperand(2));
10437 // SSE/SSE2/AVX floating point max/min intrinsics.
10438 case Intrinsic::x86_sse_max_ps:
10439 case Intrinsic::x86_sse2_max_pd:
10440 case Intrinsic::x86_avx_max_ps_256:
10441 case Intrinsic::x86_avx_max_pd_256:
10442 case Intrinsic::x86_sse_min_ps:
10443 case Intrinsic::x86_sse2_min_pd:
10444 case Intrinsic::x86_avx_min_ps_256:
10445 case Intrinsic::x86_avx_min_pd_256: {
10448 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
10449 case Intrinsic::x86_sse_max_ps:
10450 case Intrinsic::x86_sse2_max_pd:
10451 case Intrinsic::x86_avx_max_ps_256:
10452 case Intrinsic::x86_avx_max_pd_256:
10453 Opcode = X86ISD::FMAX;
10455 case Intrinsic::x86_sse_min_ps:
10456 case Intrinsic::x86_sse2_min_pd:
10457 case Intrinsic::x86_avx_min_ps_256:
10458 case Intrinsic::x86_avx_min_pd_256:
10459 Opcode = X86ISD::FMIN;
10462 return DAG.getNode(Opcode, dl, Op.getValueType(),
10463 Op.getOperand(1), Op.getOperand(2));
10466 // AVX2 variable shift intrinsics
10467 case Intrinsic::x86_avx2_psllv_d:
10468 case Intrinsic::x86_avx2_psllv_q:
10469 case Intrinsic::x86_avx2_psllv_d_256:
10470 case Intrinsic::x86_avx2_psllv_q_256:
10471 case Intrinsic::x86_avx2_psrlv_d:
10472 case Intrinsic::x86_avx2_psrlv_q:
10473 case Intrinsic::x86_avx2_psrlv_d_256:
10474 case Intrinsic::x86_avx2_psrlv_q_256:
10475 case Intrinsic::x86_avx2_psrav_d:
10476 case Intrinsic::x86_avx2_psrav_d_256: {
10479 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
10480 case Intrinsic::x86_avx2_psllv_d:
10481 case Intrinsic::x86_avx2_psllv_q:
10482 case Intrinsic::x86_avx2_psllv_d_256:
10483 case Intrinsic::x86_avx2_psllv_q_256:
10486 case Intrinsic::x86_avx2_psrlv_d:
10487 case Intrinsic::x86_avx2_psrlv_q:
10488 case Intrinsic::x86_avx2_psrlv_d_256:
10489 case Intrinsic::x86_avx2_psrlv_q_256:
10492 case Intrinsic::x86_avx2_psrav_d:
10493 case Intrinsic::x86_avx2_psrav_d_256:
10497 return DAG.getNode(Opcode, dl, Op.getValueType(),
10498 Op.getOperand(1), Op.getOperand(2));
10501 case Intrinsic::x86_ssse3_pshuf_b_128:
10502 case Intrinsic::x86_avx2_pshuf_b:
10503 return DAG.getNode(X86ISD::PSHUFB, dl, Op.getValueType(),
10504 Op.getOperand(1), Op.getOperand(2));
10506 case Intrinsic::x86_ssse3_psign_b_128:
10507 case Intrinsic::x86_ssse3_psign_w_128:
10508 case Intrinsic::x86_ssse3_psign_d_128:
10509 case Intrinsic::x86_avx2_psign_b:
10510 case Intrinsic::x86_avx2_psign_w:
10511 case Intrinsic::x86_avx2_psign_d:
10512 return DAG.getNode(X86ISD::PSIGN, dl, Op.getValueType(),
10513 Op.getOperand(1), Op.getOperand(2));
10515 case Intrinsic::x86_sse41_insertps:
10516 return DAG.getNode(X86ISD::INSERTPS, dl, Op.getValueType(),
10517 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
10519 case Intrinsic::x86_avx_vperm2f128_ps_256:
10520 case Intrinsic::x86_avx_vperm2f128_pd_256:
10521 case Intrinsic::x86_avx_vperm2f128_si_256:
10522 case Intrinsic::x86_avx2_vperm2i128:
10523 return DAG.getNode(X86ISD::VPERM2X128, dl, Op.getValueType(),
10524 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
10526 case Intrinsic::x86_avx2_permd:
10527 case Intrinsic::x86_avx2_permps:
10528 // Operands intentionally swapped. Mask is last operand to intrinsic,
10529 // but second operand for node/intruction.
10530 return DAG.getNode(X86ISD::VPERMV, dl, Op.getValueType(),
10531 Op.getOperand(2), Op.getOperand(1));
10533 case Intrinsic::x86_sse_sqrt_ps:
10534 case Intrinsic::x86_sse2_sqrt_pd:
10535 case Intrinsic::x86_avx_sqrt_ps_256:
10536 case Intrinsic::x86_avx_sqrt_pd_256:
10537 return DAG.getNode(ISD::FSQRT, dl, Op.getValueType(), Op.getOperand(1));
10539 // ptest and testp intrinsics. The intrinsic these come from are designed to
10540 // return an integer value, not just an instruction so lower it to the ptest
10541 // or testp pattern and a setcc for the result.
10542 case Intrinsic::x86_sse41_ptestz:
10543 case Intrinsic::x86_sse41_ptestc:
10544 case Intrinsic::x86_sse41_ptestnzc:
10545 case Intrinsic::x86_avx_ptestz_256:
10546 case Intrinsic::x86_avx_ptestc_256:
10547 case Intrinsic::x86_avx_ptestnzc_256:
10548 case Intrinsic::x86_avx_vtestz_ps:
10549 case Intrinsic::x86_avx_vtestc_ps:
10550 case Intrinsic::x86_avx_vtestnzc_ps:
10551 case Intrinsic::x86_avx_vtestz_pd:
10552 case Intrinsic::x86_avx_vtestc_pd:
10553 case Intrinsic::x86_avx_vtestnzc_pd:
10554 case Intrinsic::x86_avx_vtestz_ps_256:
10555 case Intrinsic::x86_avx_vtestc_ps_256:
10556 case Intrinsic::x86_avx_vtestnzc_ps_256:
10557 case Intrinsic::x86_avx_vtestz_pd_256:
10558 case Intrinsic::x86_avx_vtestc_pd_256:
10559 case Intrinsic::x86_avx_vtestnzc_pd_256: {
10560 bool IsTestPacked = false;
10563 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
10564 case Intrinsic::x86_avx_vtestz_ps:
10565 case Intrinsic::x86_avx_vtestz_pd:
10566 case Intrinsic::x86_avx_vtestz_ps_256:
10567 case Intrinsic::x86_avx_vtestz_pd_256:
10568 IsTestPacked = true; // Fallthrough
10569 case Intrinsic::x86_sse41_ptestz:
10570 case Intrinsic::x86_avx_ptestz_256:
10572 X86CC = X86::COND_E;
10574 case Intrinsic::x86_avx_vtestc_ps:
10575 case Intrinsic::x86_avx_vtestc_pd:
10576 case Intrinsic::x86_avx_vtestc_ps_256:
10577 case Intrinsic::x86_avx_vtestc_pd_256:
10578 IsTestPacked = true; // Fallthrough
10579 case Intrinsic::x86_sse41_ptestc:
10580 case Intrinsic::x86_avx_ptestc_256:
10582 X86CC = X86::COND_B;
10584 case Intrinsic::x86_avx_vtestnzc_ps:
10585 case Intrinsic::x86_avx_vtestnzc_pd:
10586 case Intrinsic::x86_avx_vtestnzc_ps_256:
10587 case Intrinsic::x86_avx_vtestnzc_pd_256:
10588 IsTestPacked = true; // Fallthrough
10589 case Intrinsic::x86_sse41_ptestnzc:
10590 case Intrinsic::x86_avx_ptestnzc_256:
10592 X86CC = X86::COND_A;
10596 SDValue LHS = Op.getOperand(1);
10597 SDValue RHS = Op.getOperand(2);
10598 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST;
10599 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS);
10600 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
10601 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
10602 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
10605 // SSE/AVX shift intrinsics
10606 case Intrinsic::x86_sse2_psll_w:
10607 case Intrinsic::x86_sse2_psll_d:
10608 case Intrinsic::x86_sse2_psll_q:
10609 case Intrinsic::x86_avx2_psll_w:
10610 case Intrinsic::x86_avx2_psll_d:
10611 case Intrinsic::x86_avx2_psll_q:
10612 case Intrinsic::x86_sse2_psrl_w:
10613 case Intrinsic::x86_sse2_psrl_d:
10614 case Intrinsic::x86_sse2_psrl_q:
10615 case Intrinsic::x86_avx2_psrl_w:
10616 case Intrinsic::x86_avx2_psrl_d:
10617 case Intrinsic::x86_avx2_psrl_q:
10618 case Intrinsic::x86_sse2_psra_w:
10619 case Intrinsic::x86_sse2_psra_d:
10620 case Intrinsic::x86_avx2_psra_w:
10621 case Intrinsic::x86_avx2_psra_d: {
10624 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
10625 case Intrinsic::x86_sse2_psll_w:
10626 case Intrinsic::x86_sse2_psll_d:
10627 case Intrinsic::x86_sse2_psll_q:
10628 case Intrinsic::x86_avx2_psll_w:
10629 case Intrinsic::x86_avx2_psll_d:
10630 case Intrinsic::x86_avx2_psll_q:
10631 Opcode = X86ISD::VSHL;
10633 case Intrinsic::x86_sse2_psrl_w:
10634 case Intrinsic::x86_sse2_psrl_d:
10635 case Intrinsic::x86_sse2_psrl_q:
10636 case Intrinsic::x86_avx2_psrl_w:
10637 case Intrinsic::x86_avx2_psrl_d:
10638 case Intrinsic::x86_avx2_psrl_q:
10639 Opcode = X86ISD::VSRL;
10641 case Intrinsic::x86_sse2_psra_w:
10642 case Intrinsic::x86_sse2_psra_d:
10643 case Intrinsic::x86_avx2_psra_w:
10644 case Intrinsic::x86_avx2_psra_d:
10645 Opcode = X86ISD::VSRA;
10648 return DAG.getNode(Opcode, dl, Op.getValueType(),
10649 Op.getOperand(1), Op.getOperand(2));
10652 // SSE/AVX immediate shift intrinsics
10653 case Intrinsic::x86_sse2_pslli_w:
10654 case Intrinsic::x86_sse2_pslli_d:
10655 case Intrinsic::x86_sse2_pslli_q:
10656 case Intrinsic::x86_avx2_pslli_w:
10657 case Intrinsic::x86_avx2_pslli_d:
10658 case Intrinsic::x86_avx2_pslli_q:
10659 case Intrinsic::x86_sse2_psrli_w:
10660 case Intrinsic::x86_sse2_psrli_d:
10661 case Intrinsic::x86_sse2_psrli_q:
10662 case Intrinsic::x86_avx2_psrli_w:
10663 case Intrinsic::x86_avx2_psrli_d:
10664 case Intrinsic::x86_avx2_psrli_q:
10665 case Intrinsic::x86_sse2_psrai_w:
10666 case Intrinsic::x86_sse2_psrai_d:
10667 case Intrinsic::x86_avx2_psrai_w:
10668 case Intrinsic::x86_avx2_psrai_d: {
10671 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
10672 case Intrinsic::x86_sse2_pslli_w:
10673 case Intrinsic::x86_sse2_pslli_d:
10674 case Intrinsic::x86_sse2_pslli_q:
10675 case Intrinsic::x86_avx2_pslli_w:
10676 case Intrinsic::x86_avx2_pslli_d:
10677 case Intrinsic::x86_avx2_pslli_q:
10678 Opcode = X86ISD::VSHLI;
10680 case Intrinsic::x86_sse2_psrli_w:
10681 case Intrinsic::x86_sse2_psrli_d:
10682 case Intrinsic::x86_sse2_psrli_q:
10683 case Intrinsic::x86_avx2_psrli_w:
10684 case Intrinsic::x86_avx2_psrli_d:
10685 case Intrinsic::x86_avx2_psrli_q:
10686 Opcode = X86ISD::VSRLI;
10688 case Intrinsic::x86_sse2_psrai_w:
10689 case Intrinsic::x86_sse2_psrai_d:
10690 case Intrinsic::x86_avx2_psrai_w:
10691 case Intrinsic::x86_avx2_psrai_d:
10692 Opcode = X86ISD::VSRAI;
10695 return getTargetVShiftNode(Opcode, dl, Op.getValueType(),
10696 Op.getOperand(1), Op.getOperand(2), DAG);
10699 case Intrinsic::x86_sse42_pcmpistria128:
10700 case Intrinsic::x86_sse42_pcmpestria128:
10701 case Intrinsic::x86_sse42_pcmpistric128:
10702 case Intrinsic::x86_sse42_pcmpestric128:
10703 case Intrinsic::x86_sse42_pcmpistrio128:
10704 case Intrinsic::x86_sse42_pcmpestrio128:
10705 case Intrinsic::x86_sse42_pcmpistris128:
10706 case Intrinsic::x86_sse42_pcmpestris128:
10707 case Intrinsic::x86_sse42_pcmpistriz128:
10708 case Intrinsic::x86_sse42_pcmpestriz128: {
10712 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
10713 case Intrinsic::x86_sse42_pcmpistria128:
10714 Opcode = X86ISD::PCMPISTRI;
10715 X86CC = X86::COND_A;
10717 case Intrinsic::x86_sse42_pcmpestria128:
10718 Opcode = X86ISD::PCMPESTRI;
10719 X86CC = X86::COND_A;
10721 case Intrinsic::x86_sse42_pcmpistric128:
10722 Opcode = X86ISD::PCMPISTRI;
10723 X86CC = X86::COND_B;
10725 case Intrinsic::x86_sse42_pcmpestric128:
10726 Opcode = X86ISD::PCMPESTRI;
10727 X86CC = X86::COND_B;
10729 case Intrinsic::x86_sse42_pcmpistrio128:
10730 Opcode = X86ISD::PCMPISTRI;
10731 X86CC = X86::COND_O;
10733 case Intrinsic::x86_sse42_pcmpestrio128:
10734 Opcode = X86ISD::PCMPESTRI;
10735 X86CC = X86::COND_O;
10737 case Intrinsic::x86_sse42_pcmpistris128:
10738 Opcode = X86ISD::PCMPISTRI;
10739 X86CC = X86::COND_S;
10741 case Intrinsic::x86_sse42_pcmpestris128:
10742 Opcode = X86ISD::PCMPESTRI;
10743 X86CC = X86::COND_S;
10745 case Intrinsic::x86_sse42_pcmpistriz128:
10746 Opcode = X86ISD::PCMPISTRI;
10747 X86CC = X86::COND_E;
10749 case Intrinsic::x86_sse42_pcmpestriz128:
10750 Opcode = X86ISD::PCMPESTRI;
10751 X86CC = X86::COND_E;
10754 SmallVector<SDValue, 5> NewOps;
10755 NewOps.append(Op->op_begin()+1, Op->op_end());
10756 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
10757 SDValue PCMP = DAG.getNode(Opcode, dl, VTs, NewOps.data(), NewOps.size());
10758 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
10759 DAG.getConstant(X86CC, MVT::i8),
10760 SDValue(PCMP.getNode(), 1));
10761 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
10764 case Intrinsic::x86_sse42_pcmpistri128:
10765 case Intrinsic::x86_sse42_pcmpestri128: {
10767 if (IntNo == Intrinsic::x86_sse42_pcmpistri128)
10768 Opcode = X86ISD::PCMPISTRI;
10770 Opcode = X86ISD::PCMPESTRI;
10772 SmallVector<SDValue, 5> NewOps;
10773 NewOps.append(Op->op_begin()+1, Op->op_end());
10774 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
10775 return DAG.getNode(Opcode, dl, VTs, NewOps.data(), NewOps.size());
10777 case Intrinsic::x86_fma_vfmadd_ps:
10778 case Intrinsic::x86_fma_vfmadd_pd:
10779 case Intrinsic::x86_fma_vfmsub_ps:
10780 case Intrinsic::x86_fma_vfmsub_pd:
10781 case Intrinsic::x86_fma_vfnmadd_ps:
10782 case Intrinsic::x86_fma_vfnmadd_pd:
10783 case Intrinsic::x86_fma_vfnmsub_ps:
10784 case Intrinsic::x86_fma_vfnmsub_pd:
10785 case Intrinsic::x86_fma_vfmaddsub_ps:
10786 case Intrinsic::x86_fma_vfmaddsub_pd:
10787 case Intrinsic::x86_fma_vfmsubadd_ps:
10788 case Intrinsic::x86_fma_vfmsubadd_pd:
10789 case Intrinsic::x86_fma_vfmadd_ps_256:
10790 case Intrinsic::x86_fma_vfmadd_pd_256:
10791 case Intrinsic::x86_fma_vfmsub_ps_256:
10792 case Intrinsic::x86_fma_vfmsub_pd_256:
10793 case Intrinsic::x86_fma_vfnmadd_ps_256:
10794 case Intrinsic::x86_fma_vfnmadd_pd_256:
10795 case Intrinsic::x86_fma_vfnmsub_ps_256:
10796 case Intrinsic::x86_fma_vfnmsub_pd_256:
10797 case Intrinsic::x86_fma_vfmaddsub_ps_256:
10798 case Intrinsic::x86_fma_vfmaddsub_pd_256:
10799 case Intrinsic::x86_fma_vfmsubadd_ps_256:
10800 case Intrinsic::x86_fma_vfmsubadd_pd_256: {
10803 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
10804 case Intrinsic::x86_fma_vfmadd_ps:
10805 case Intrinsic::x86_fma_vfmadd_pd:
10806 case Intrinsic::x86_fma_vfmadd_ps_256:
10807 case Intrinsic::x86_fma_vfmadd_pd_256:
10808 Opc = X86ISD::FMADD;
10810 case Intrinsic::x86_fma_vfmsub_ps:
10811 case Intrinsic::x86_fma_vfmsub_pd:
10812 case Intrinsic::x86_fma_vfmsub_ps_256:
10813 case Intrinsic::x86_fma_vfmsub_pd_256:
10814 Opc = X86ISD::FMSUB;
10816 case Intrinsic::x86_fma_vfnmadd_ps:
10817 case Intrinsic::x86_fma_vfnmadd_pd:
10818 case Intrinsic::x86_fma_vfnmadd_ps_256:
10819 case Intrinsic::x86_fma_vfnmadd_pd_256:
10820 Opc = X86ISD::FNMADD;
10822 case Intrinsic::x86_fma_vfnmsub_ps:
10823 case Intrinsic::x86_fma_vfnmsub_pd:
10824 case Intrinsic::x86_fma_vfnmsub_ps_256:
10825 case Intrinsic::x86_fma_vfnmsub_pd_256:
10826 Opc = X86ISD::FNMSUB;
10828 case Intrinsic::x86_fma_vfmaddsub_ps:
10829 case Intrinsic::x86_fma_vfmaddsub_pd:
10830 case Intrinsic::x86_fma_vfmaddsub_ps_256:
10831 case Intrinsic::x86_fma_vfmaddsub_pd_256:
10832 Opc = X86ISD::FMADDSUB;
10834 case Intrinsic::x86_fma_vfmsubadd_ps:
10835 case Intrinsic::x86_fma_vfmsubadd_pd:
10836 case Intrinsic::x86_fma_vfmsubadd_ps_256:
10837 case Intrinsic::x86_fma_vfmsubadd_pd_256:
10838 Opc = X86ISD::FMSUBADD;
10842 return DAG.getNode(Opc, dl, Op.getValueType(), Op.getOperand(1),
10843 Op.getOperand(2), Op.getOperand(3));
10848 static SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) {
10849 DebugLoc dl = Op.getDebugLoc();
10850 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
10852 default: return SDValue(); // Don't custom lower most intrinsics.
10854 // RDRAND intrinsics.
10855 case Intrinsic::x86_rdrand_16:
10856 case Intrinsic::x86_rdrand_32:
10857 case Intrinsic::x86_rdrand_64: {
10858 // Emit the node with the right value type.
10859 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Glue, MVT::Other);
10860 SDValue Result = DAG.getNode(X86ISD::RDRAND, dl, VTs, Op.getOperand(0));
10862 // If the value returned by RDRAND was valid (CF=1), return 1. Otherwise
10863 // return the value from Rand, which is always 0, casted to i32.
10864 SDValue Ops[] = { DAG.getZExtOrTrunc(Result, dl, Op->getValueType(1)),
10865 DAG.getConstant(1, Op->getValueType(1)),
10866 DAG.getConstant(X86::COND_B, MVT::i32),
10867 SDValue(Result.getNode(), 1) };
10868 SDValue isValid = DAG.getNode(X86ISD::CMOV, dl,
10869 DAG.getVTList(Op->getValueType(1), MVT::Glue),
10872 // Return { result, isValid, chain }.
10873 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(), Result, isValid,
10874 SDValue(Result.getNode(), 2));
10879 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op,
10880 SelectionDAG &DAG) const {
10881 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
10882 MFI->setReturnAddressIsTaken(true);
10884 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
10885 DebugLoc dl = Op.getDebugLoc();
10886 EVT PtrVT = getPointerTy();
10889 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
10891 DAG.getConstant(RegInfo->getSlotSize(), PtrVT);
10892 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
10893 DAG.getNode(ISD::ADD, dl, PtrVT,
10894 FrameAddr, Offset),
10895 MachinePointerInfo(), false, false, false, 0);
10898 // Just load the return address.
10899 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
10900 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
10901 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
10904 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
10905 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
10906 MFI->setFrameAddressIsTaken(true);
10908 EVT VT = Op.getValueType();
10909 DebugLoc dl = Op.getDebugLoc(); // FIXME probably not meaningful
10910 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
10911 unsigned FrameReg = Subtarget->is64Bit() ? X86::RBP : X86::EBP;
10912 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
10914 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
10915 MachinePointerInfo(),
10916 false, false, false, 0);
10920 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
10921 SelectionDAG &DAG) const {
10922 return DAG.getIntPtrConstant(2 * RegInfo->getSlotSize());
10925 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
10926 SDValue Chain = Op.getOperand(0);
10927 SDValue Offset = Op.getOperand(1);
10928 SDValue Handler = Op.getOperand(2);
10929 DebugLoc dl = Op.getDebugLoc();
10931 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl,
10932 Subtarget->is64Bit() ? X86::RBP : X86::EBP,
10934 unsigned StoreAddrReg = (Subtarget->is64Bit() ? X86::RCX : X86::ECX);
10936 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), Frame,
10937 DAG.getIntPtrConstant(RegInfo->getSlotSize()));
10938 StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), StoreAddr, Offset);
10939 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(),
10941 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
10943 return DAG.getNode(X86ISD::EH_RETURN, dl,
10945 Chain, DAG.getRegister(StoreAddrReg, getPointerTy()));
10948 SDValue X86TargetLowering::lowerEH_SJLJ_SETJMP(SDValue Op,
10949 SelectionDAG &DAG) const {
10950 DebugLoc DL = Op.getDebugLoc();
10951 return DAG.getNode(X86ISD::EH_SJLJ_SETJMP, DL,
10952 DAG.getVTList(MVT::i32, MVT::Other),
10953 Op.getOperand(0), Op.getOperand(1));
10956 SDValue X86TargetLowering::lowerEH_SJLJ_LONGJMP(SDValue Op,
10957 SelectionDAG &DAG) const {
10958 DebugLoc DL = Op.getDebugLoc();
10959 return DAG.getNode(X86ISD::EH_SJLJ_LONGJMP, DL, MVT::Other,
10960 Op.getOperand(0), Op.getOperand(1));
10963 static SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) {
10964 return Op.getOperand(0);
10967 SDValue X86TargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
10968 SelectionDAG &DAG) const {
10969 SDValue Root = Op.getOperand(0);
10970 SDValue Trmp = Op.getOperand(1); // trampoline
10971 SDValue FPtr = Op.getOperand(2); // nested function
10972 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
10973 DebugLoc dl = Op.getDebugLoc();
10975 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
10976 const TargetRegisterInfo* TRI = getTargetMachine().getRegisterInfo();
10978 if (Subtarget->is64Bit()) {
10979 SDValue OutChains[6];
10981 // Large code-model.
10982 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode.
10983 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode.
10985 const unsigned char N86R10 = TRI->getEncodingValue(X86::R10) & 0x7;
10986 const unsigned char N86R11 = TRI->getEncodingValue(X86::R11) & 0x7;
10988 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
10990 // Load the pointer to the nested function into R11.
10991 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
10992 SDValue Addr = Trmp;
10993 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
10994 Addr, MachinePointerInfo(TrmpAddr),
10997 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
10998 DAG.getConstant(2, MVT::i64));
10999 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr,
11000 MachinePointerInfo(TrmpAddr, 2),
11003 // Load the 'nest' parameter value into R10.
11004 // R10 is specified in X86CallingConv.td
11005 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
11006 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
11007 DAG.getConstant(10, MVT::i64));
11008 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
11009 Addr, MachinePointerInfo(TrmpAddr, 10),
11012 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
11013 DAG.getConstant(12, MVT::i64));
11014 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr,
11015 MachinePointerInfo(TrmpAddr, 12),
11018 // Jump to the nested function.
11019 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
11020 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
11021 DAG.getConstant(20, MVT::i64));
11022 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
11023 Addr, MachinePointerInfo(TrmpAddr, 20),
11026 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
11027 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
11028 DAG.getConstant(22, MVT::i64));
11029 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr,
11030 MachinePointerInfo(TrmpAddr, 22),
11033 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 6);
11035 const Function *Func =
11036 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
11037 CallingConv::ID CC = Func->getCallingConv();
11042 llvm_unreachable("Unsupported calling convention");
11043 case CallingConv::C:
11044 case CallingConv::X86_StdCall: {
11045 // Pass 'nest' parameter in ECX.
11046 // Must be kept in sync with X86CallingConv.td
11047 NestReg = X86::ECX;
11049 // Check that ECX wasn't needed by an 'inreg' parameter.
11050 FunctionType *FTy = Func->getFunctionType();
11051 const AttributeSet &Attrs = Func->getAttributes();
11053 if (!Attrs.isEmpty() && !Func->isVarArg()) {
11054 unsigned InRegCount = 0;
11057 for (FunctionType::param_iterator I = FTy->param_begin(),
11058 E = FTy->param_end(); I != E; ++I, ++Idx)
11059 if (Attrs.hasAttribute(Idx, Attribute::InReg))
11060 // FIXME: should only count parameters that are lowered to integers.
11061 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32;
11063 if (InRegCount > 2) {
11064 report_fatal_error("Nest register in use - reduce number of inreg"
11070 case CallingConv::X86_FastCall:
11071 case CallingConv::X86_ThisCall:
11072 case CallingConv::Fast:
11073 // Pass 'nest' parameter in EAX.
11074 // Must be kept in sync with X86CallingConv.td
11075 NestReg = X86::EAX;
11079 SDValue OutChains[4];
11080 SDValue Addr, Disp;
11082 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
11083 DAG.getConstant(10, MVT::i32));
11084 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
11086 // This is storing the opcode for MOV32ri.
11087 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte.
11088 const unsigned char N86Reg = TRI->getEncodingValue(NestReg) & 0x7;
11089 OutChains[0] = DAG.getStore(Root, dl,
11090 DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
11091 Trmp, MachinePointerInfo(TrmpAddr),
11094 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
11095 DAG.getConstant(1, MVT::i32));
11096 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr,
11097 MachinePointerInfo(TrmpAddr, 1),
11100 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode.
11101 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
11102 DAG.getConstant(5, MVT::i32));
11103 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr,
11104 MachinePointerInfo(TrmpAddr, 5),
11107 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
11108 DAG.getConstant(6, MVT::i32));
11109 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr,
11110 MachinePointerInfo(TrmpAddr, 6),
11113 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 4);
11117 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op,
11118 SelectionDAG &DAG) const {
11120 The rounding mode is in bits 11:10 of FPSR, and has the following
11122 00 Round to nearest
11127 FLT_ROUNDS, on the other hand, expects the following:
11134 To perform the conversion, we do:
11135 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
11138 MachineFunction &MF = DAG.getMachineFunction();
11139 const TargetMachine &TM = MF.getTarget();
11140 const TargetFrameLowering &TFI = *TM.getFrameLowering();
11141 unsigned StackAlignment = TFI.getStackAlignment();
11142 EVT VT = Op.getValueType();
11143 DebugLoc DL = Op.getDebugLoc();
11145 // Save FP Control Word to stack slot
11146 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false);
11147 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
11149 MachineMemOperand *MMO =
11150 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
11151 MachineMemOperand::MOStore, 2, 2);
11153 SDValue Ops[] = { DAG.getEntryNode(), StackSlot };
11154 SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL,
11155 DAG.getVTList(MVT::Other),
11156 Ops, 2, MVT::i16, MMO);
11158 // Load FP Control Word from stack slot
11159 SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot,
11160 MachinePointerInfo(), false, false, false, 0);
11162 // Transform as necessary
11164 DAG.getNode(ISD::SRL, DL, MVT::i16,
11165 DAG.getNode(ISD::AND, DL, MVT::i16,
11166 CWD, DAG.getConstant(0x800, MVT::i16)),
11167 DAG.getConstant(11, MVT::i8));
11169 DAG.getNode(ISD::SRL, DL, MVT::i16,
11170 DAG.getNode(ISD::AND, DL, MVT::i16,
11171 CWD, DAG.getConstant(0x400, MVT::i16)),
11172 DAG.getConstant(9, MVT::i8));
11175 DAG.getNode(ISD::AND, DL, MVT::i16,
11176 DAG.getNode(ISD::ADD, DL, MVT::i16,
11177 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2),
11178 DAG.getConstant(1, MVT::i16)),
11179 DAG.getConstant(3, MVT::i16));
11181 return DAG.getNode((VT.getSizeInBits() < 16 ?
11182 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal);
11185 static SDValue LowerCTLZ(SDValue Op, SelectionDAG &DAG) {
11186 EVT VT = Op.getValueType();
11188 unsigned NumBits = VT.getSizeInBits();
11189 DebugLoc dl = Op.getDebugLoc();
11191 Op = Op.getOperand(0);
11192 if (VT == MVT::i8) {
11193 // Zero extend to i32 since there is not an i8 bsr.
11195 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
11198 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
11199 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
11200 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
11202 // If src is zero (i.e. bsr sets ZF), returns NumBits.
11205 DAG.getConstant(NumBits+NumBits-1, OpVT),
11206 DAG.getConstant(X86::COND_E, MVT::i8),
11209 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops, array_lengthof(Ops));
11211 // Finally xor with NumBits-1.
11212 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
11215 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
11219 static SDValue LowerCTLZ_ZERO_UNDEF(SDValue Op, SelectionDAG &DAG) {
11220 EVT VT = Op.getValueType();
11222 unsigned NumBits = VT.getSizeInBits();
11223 DebugLoc dl = Op.getDebugLoc();
11225 Op = Op.getOperand(0);
11226 if (VT == MVT::i8) {
11227 // Zero extend to i32 since there is not an i8 bsr.
11229 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
11232 // Issue a bsr (scan bits in reverse).
11233 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
11234 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
11236 // And xor with NumBits-1.
11237 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
11240 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
11244 static SDValue LowerCTTZ(SDValue Op, SelectionDAG &DAG) {
11245 EVT VT = Op.getValueType();
11246 unsigned NumBits = VT.getSizeInBits();
11247 DebugLoc dl = Op.getDebugLoc();
11248 Op = Op.getOperand(0);
11250 // Issue a bsf (scan bits forward) which also sets EFLAGS.
11251 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
11252 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op);
11254 // If src is zero (i.e. bsf sets ZF), returns NumBits.
11257 DAG.getConstant(NumBits, VT),
11258 DAG.getConstant(X86::COND_E, MVT::i8),
11261 return DAG.getNode(X86ISD::CMOV, dl, VT, Ops, array_lengthof(Ops));
11264 // Lower256IntArith - Break a 256-bit integer operation into two new 128-bit
11265 // ones, and then concatenate the result back.
11266 static SDValue Lower256IntArith(SDValue Op, SelectionDAG &DAG) {
11267 EVT VT = Op.getValueType();
11269 assert(VT.is256BitVector() && VT.isInteger() &&
11270 "Unsupported value type for operation");
11272 unsigned NumElems = VT.getVectorNumElements();
11273 DebugLoc dl = Op.getDebugLoc();
11275 // Extract the LHS vectors
11276 SDValue LHS = Op.getOperand(0);
11277 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
11278 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
11280 // Extract the RHS vectors
11281 SDValue RHS = Op.getOperand(1);
11282 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
11283 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
11285 MVT EltVT = VT.getVectorElementType().getSimpleVT();
11286 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
11288 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
11289 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1),
11290 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2));
11293 static SDValue LowerADD(SDValue Op, SelectionDAG &DAG) {
11294 assert(Op.getValueType().is256BitVector() &&
11295 Op.getValueType().isInteger() &&
11296 "Only handle AVX 256-bit vector integer operation");
11297 return Lower256IntArith(Op, DAG);
11300 static SDValue LowerSUB(SDValue Op, SelectionDAG &DAG) {
11301 assert(Op.getValueType().is256BitVector() &&
11302 Op.getValueType().isInteger() &&
11303 "Only handle AVX 256-bit vector integer operation");
11304 return Lower256IntArith(Op, DAG);
11307 static SDValue LowerMUL(SDValue Op, const X86Subtarget *Subtarget,
11308 SelectionDAG &DAG) {
11309 DebugLoc dl = Op.getDebugLoc();
11310 EVT VT = Op.getValueType();
11312 // Decompose 256-bit ops into smaller 128-bit ops.
11313 if (VT.is256BitVector() && !Subtarget->hasInt256())
11314 return Lower256IntArith(Op, DAG);
11316 SDValue A = Op.getOperand(0);
11317 SDValue B = Op.getOperand(1);
11319 // Lower v4i32 mul as 2x shuffle, 2x pmuludq, 2x shuffle.
11320 if (VT == MVT::v4i32) {
11321 assert(Subtarget->hasSSE2() && !Subtarget->hasSSE41() &&
11322 "Should not custom lower when pmuldq is available!");
11324 // Extract the odd parts.
11325 const int UnpackMask[] = { 1, -1, 3, -1 };
11326 SDValue Aodds = DAG.getVectorShuffle(VT, dl, A, A, UnpackMask);
11327 SDValue Bodds = DAG.getVectorShuffle(VT, dl, B, B, UnpackMask);
11329 // Multiply the even parts.
11330 SDValue Evens = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, A, B);
11331 // Now multiply odd parts.
11332 SDValue Odds = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, Aodds, Bodds);
11334 Evens = DAG.getNode(ISD::BITCAST, dl, VT, Evens);
11335 Odds = DAG.getNode(ISD::BITCAST, dl, VT, Odds);
11337 // Merge the two vectors back together with a shuffle. This expands into 2
11339 const int ShufMask[] = { 0, 4, 2, 6 };
11340 return DAG.getVectorShuffle(VT, dl, Evens, Odds, ShufMask);
11343 assert((VT == MVT::v2i64 || VT == MVT::v4i64) &&
11344 "Only know how to lower V2I64/V4I64 multiply");
11346 // Ahi = psrlqi(a, 32);
11347 // Bhi = psrlqi(b, 32);
11349 // AloBlo = pmuludq(a, b);
11350 // AloBhi = pmuludq(a, Bhi);
11351 // AhiBlo = pmuludq(Ahi, b);
11353 // AloBhi = psllqi(AloBhi, 32);
11354 // AhiBlo = psllqi(AhiBlo, 32);
11355 // return AloBlo + AloBhi + AhiBlo;
11357 SDValue ShAmt = DAG.getConstant(32, MVT::i32);
11359 SDValue Ahi = DAG.getNode(X86ISD::VSRLI, dl, VT, A, ShAmt);
11360 SDValue Bhi = DAG.getNode(X86ISD::VSRLI, dl, VT, B, ShAmt);
11362 // Bit cast to 32-bit vectors for MULUDQ
11363 EVT MulVT = (VT == MVT::v2i64) ? MVT::v4i32 : MVT::v8i32;
11364 A = DAG.getNode(ISD::BITCAST, dl, MulVT, A);
11365 B = DAG.getNode(ISD::BITCAST, dl, MulVT, B);
11366 Ahi = DAG.getNode(ISD::BITCAST, dl, MulVT, Ahi);
11367 Bhi = DAG.getNode(ISD::BITCAST, dl, MulVT, Bhi);
11369 SDValue AloBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, B);
11370 SDValue AloBhi = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, Bhi);
11371 SDValue AhiBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, Ahi, B);
11373 AloBhi = DAG.getNode(X86ISD::VSHLI, dl, VT, AloBhi, ShAmt);
11374 AhiBlo = DAG.getNode(X86ISD::VSHLI, dl, VT, AhiBlo, ShAmt);
11376 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
11377 return DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
11380 SDValue X86TargetLowering::LowerSDIV(SDValue Op, SelectionDAG &DAG) const {
11381 EVT VT = Op.getValueType();
11382 EVT EltTy = VT.getVectorElementType();
11383 unsigned NumElts = VT.getVectorNumElements();
11384 SDValue N0 = Op.getOperand(0);
11385 DebugLoc dl = Op.getDebugLoc();
11387 // Lower sdiv X, pow2-const.
11388 BuildVectorSDNode *C = dyn_cast<BuildVectorSDNode>(Op.getOperand(1));
11392 APInt SplatValue, SplatUndef;
11393 unsigned MinSplatBits;
11395 if (!C->isConstantSplat(SplatValue, SplatUndef, MinSplatBits, HasAnyUndefs))
11398 if ((SplatValue != 0) &&
11399 (SplatValue.isPowerOf2() || (-SplatValue).isPowerOf2())) {
11400 unsigned lg2 = SplatValue.countTrailingZeros();
11401 // Splat the sign bit.
11402 SDValue Sz = DAG.getConstant(EltTy.getSizeInBits()-1, MVT::i32);
11403 SDValue SGN = getTargetVShiftNode(X86ISD::VSRAI, dl, VT, N0, Sz, DAG);
11404 // Add (N0 < 0) ? abs2 - 1 : 0;
11405 SDValue Amt = DAG.getConstant(EltTy.getSizeInBits() - lg2, MVT::i32);
11406 SDValue SRL = getTargetVShiftNode(X86ISD::VSRLI, dl, VT, SGN, Amt, DAG);
11407 SDValue ADD = DAG.getNode(ISD::ADD, dl, VT, N0, SRL);
11408 SDValue Lg2Amt = DAG.getConstant(lg2, MVT::i32);
11409 SDValue SRA = getTargetVShiftNode(X86ISD::VSRAI, dl, VT, ADD, Lg2Amt, DAG);
11411 // If we're dividing by a positive value, we're done. Otherwise, we must
11412 // negate the result.
11413 if (SplatValue.isNonNegative())
11416 SmallVector<SDValue, 16> V(NumElts, DAG.getConstant(0, EltTy));
11417 SDValue Zero = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], NumElts);
11418 return DAG.getNode(ISD::SUB, dl, VT, Zero, SRA);
11423 SDValue X86TargetLowering::LowerShift(SDValue Op, SelectionDAG &DAG) const {
11425 EVT VT = Op.getValueType();
11426 DebugLoc dl = Op.getDebugLoc();
11427 SDValue R = Op.getOperand(0);
11428 SDValue Amt = Op.getOperand(1);
11429 LLVMContext *Context = DAG.getContext();
11431 if (!Subtarget->hasSSE2())
11434 // Optimize shl/srl/sra with constant shift amount.
11435 if (isSplatVector(Amt.getNode())) {
11436 SDValue SclrAmt = Amt->getOperand(0);
11437 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(SclrAmt)) {
11438 uint64_t ShiftAmt = C->getZExtValue();
11440 if (VT == MVT::v2i64 || VT == MVT::v4i32 || VT == MVT::v8i16 ||
11441 (Subtarget->hasInt256() &&
11442 (VT == MVT::v4i64 || VT == MVT::v8i32 || VT == MVT::v16i16))) {
11443 if (Op.getOpcode() == ISD::SHL)
11444 return DAG.getNode(X86ISD::VSHLI, dl, VT, R,
11445 DAG.getConstant(ShiftAmt, MVT::i32));
11446 if (Op.getOpcode() == ISD::SRL)
11447 return DAG.getNode(X86ISD::VSRLI, dl, VT, R,
11448 DAG.getConstant(ShiftAmt, MVT::i32));
11449 if (Op.getOpcode() == ISD::SRA && VT != MVT::v2i64 && VT != MVT::v4i64)
11450 return DAG.getNode(X86ISD::VSRAI, dl, VT, R,
11451 DAG.getConstant(ShiftAmt, MVT::i32));
11454 if (VT == MVT::v16i8) {
11455 if (Op.getOpcode() == ISD::SHL) {
11456 // Make a large shift.
11457 SDValue SHL = DAG.getNode(X86ISD::VSHLI, dl, MVT::v8i16, R,
11458 DAG.getConstant(ShiftAmt, MVT::i32));
11459 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
11460 // Zero out the rightmost bits.
11461 SmallVector<SDValue, 16> V(16,
11462 DAG.getConstant(uint8_t(-1U << ShiftAmt),
11464 return DAG.getNode(ISD::AND, dl, VT, SHL,
11465 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16));
11467 if (Op.getOpcode() == ISD::SRL) {
11468 // Make a large shift.
11469 SDValue SRL = DAG.getNode(X86ISD::VSRLI, dl, MVT::v8i16, R,
11470 DAG.getConstant(ShiftAmt, MVT::i32));
11471 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
11472 // Zero out the leftmost bits.
11473 SmallVector<SDValue, 16> V(16,
11474 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
11476 return DAG.getNode(ISD::AND, dl, VT, SRL,
11477 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16));
11479 if (Op.getOpcode() == ISD::SRA) {
11480 if (ShiftAmt == 7) {
11481 // R s>> 7 === R s< 0
11482 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
11483 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
11486 // R s>> a === ((R u>> a) ^ m) - m
11487 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
11488 SmallVector<SDValue, 16> V(16, DAG.getConstant(128 >> ShiftAmt,
11490 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16);
11491 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
11492 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
11495 llvm_unreachable("Unknown shift opcode.");
11498 if (Subtarget->hasInt256() && VT == MVT::v32i8) {
11499 if (Op.getOpcode() == ISD::SHL) {
11500 // Make a large shift.
11501 SDValue SHL = DAG.getNode(X86ISD::VSHLI, dl, MVT::v16i16, R,
11502 DAG.getConstant(ShiftAmt, MVT::i32));
11503 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
11504 // Zero out the rightmost bits.
11505 SmallVector<SDValue, 32> V(32,
11506 DAG.getConstant(uint8_t(-1U << ShiftAmt),
11508 return DAG.getNode(ISD::AND, dl, VT, SHL,
11509 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32));
11511 if (Op.getOpcode() == ISD::SRL) {
11512 // Make a large shift.
11513 SDValue SRL = DAG.getNode(X86ISD::VSRLI, dl, MVT::v16i16, R,
11514 DAG.getConstant(ShiftAmt, MVT::i32));
11515 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
11516 // Zero out the leftmost bits.
11517 SmallVector<SDValue, 32> V(32,
11518 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
11520 return DAG.getNode(ISD::AND, dl, VT, SRL,
11521 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32));
11523 if (Op.getOpcode() == ISD::SRA) {
11524 if (ShiftAmt == 7) {
11525 // R s>> 7 === R s< 0
11526 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
11527 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
11530 // R s>> a === ((R u>> a) ^ m) - m
11531 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
11532 SmallVector<SDValue, 32> V(32, DAG.getConstant(128 >> ShiftAmt,
11534 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32);
11535 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
11536 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
11539 llvm_unreachable("Unknown shift opcode.");
11544 // Lower SHL with variable shift amount.
11545 if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) {
11546 Op = DAG.getNode(X86ISD::VSHLI, dl, VT, Op.getOperand(1),
11547 DAG.getConstant(23, MVT::i32));
11549 const uint32_t CV[] = { 0x3f800000U, 0x3f800000U, 0x3f800000U, 0x3f800000U};
11550 Constant *C = ConstantDataVector::get(*Context, CV);
11551 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
11552 SDValue Addend = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
11553 MachinePointerInfo::getConstantPool(),
11554 false, false, false, 16);
11556 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Addend);
11557 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, Op);
11558 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op);
11559 return DAG.getNode(ISD::MUL, dl, VT, Op, R);
11561 if (VT == MVT::v16i8 && Op->getOpcode() == ISD::SHL) {
11562 assert(Subtarget->hasSSE2() && "Need SSE2 for pslli/pcmpeq.");
11565 Op = DAG.getNode(X86ISD::VSHLI, dl, MVT::v8i16, Op.getOperand(1),
11566 DAG.getConstant(5, MVT::i32));
11567 Op = DAG.getNode(ISD::BITCAST, dl, VT, Op);
11569 // Turn 'a' into a mask suitable for VSELECT
11570 SDValue VSelM = DAG.getConstant(0x80, VT);
11571 SDValue OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
11572 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
11574 SDValue CM1 = DAG.getConstant(0x0f, VT);
11575 SDValue CM2 = DAG.getConstant(0x3f, VT);
11577 // r = VSELECT(r, psllw(r & (char16)15, 4), a);
11578 SDValue M = DAG.getNode(ISD::AND, dl, VT, R, CM1);
11579 M = getTargetVShiftNode(X86ISD::VSHLI, dl, MVT::v8i16, M,
11580 DAG.getConstant(4, MVT::i32), DAG);
11581 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
11582 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
11585 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
11586 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
11587 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
11589 // r = VSELECT(r, psllw(r & (char16)63, 2), a);
11590 M = DAG.getNode(ISD::AND, dl, VT, R, CM2);
11591 M = getTargetVShiftNode(X86ISD::VSHLI, dl, MVT::v8i16, M,
11592 DAG.getConstant(2, MVT::i32), DAG);
11593 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
11594 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
11597 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
11598 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
11599 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
11601 // return VSELECT(r, r+r, a);
11602 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel,
11603 DAG.getNode(ISD::ADD, dl, VT, R, R), R);
11607 // Decompose 256-bit shifts into smaller 128-bit shifts.
11608 if (VT.is256BitVector()) {
11609 unsigned NumElems = VT.getVectorNumElements();
11610 MVT EltVT = VT.getVectorElementType().getSimpleVT();
11611 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
11613 // Extract the two vectors
11614 SDValue V1 = Extract128BitVector(R, 0, DAG, dl);
11615 SDValue V2 = Extract128BitVector(R, NumElems/2, DAG, dl);
11617 // Recreate the shift amount vectors
11618 SDValue Amt1, Amt2;
11619 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
11620 // Constant shift amount
11621 SmallVector<SDValue, 4> Amt1Csts;
11622 SmallVector<SDValue, 4> Amt2Csts;
11623 for (unsigned i = 0; i != NumElems/2; ++i)
11624 Amt1Csts.push_back(Amt->getOperand(i));
11625 for (unsigned i = NumElems/2; i != NumElems; ++i)
11626 Amt2Csts.push_back(Amt->getOperand(i));
11628 Amt1 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT,
11629 &Amt1Csts[0], NumElems/2);
11630 Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT,
11631 &Amt2Csts[0], NumElems/2);
11633 // Variable shift amount
11634 Amt1 = Extract128BitVector(Amt, 0, DAG, dl);
11635 Amt2 = Extract128BitVector(Amt, NumElems/2, DAG, dl);
11638 // Issue new vector shifts for the smaller types
11639 V1 = DAG.getNode(Op.getOpcode(), dl, NewVT, V1, Amt1);
11640 V2 = DAG.getNode(Op.getOpcode(), dl, NewVT, V2, Amt2);
11642 // Concatenate the result back
11643 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, V1, V2);
11649 static SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) {
11650 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
11651 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
11652 // looks for this combo and may remove the "setcc" instruction if the "setcc"
11653 // has only one use.
11654 SDNode *N = Op.getNode();
11655 SDValue LHS = N->getOperand(0);
11656 SDValue RHS = N->getOperand(1);
11657 unsigned BaseOp = 0;
11659 DebugLoc DL = Op.getDebugLoc();
11660 switch (Op.getOpcode()) {
11661 default: llvm_unreachable("Unknown ovf instruction!");
11663 // A subtract of one will be selected as a INC. Note that INC doesn't
11664 // set CF, so we can't do this for UADDO.
11665 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
11667 BaseOp = X86ISD::INC;
11668 Cond = X86::COND_O;
11671 BaseOp = X86ISD::ADD;
11672 Cond = X86::COND_O;
11675 BaseOp = X86ISD::ADD;
11676 Cond = X86::COND_B;
11679 // A subtract of one will be selected as a DEC. Note that DEC doesn't
11680 // set CF, so we can't do this for USUBO.
11681 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
11683 BaseOp = X86ISD::DEC;
11684 Cond = X86::COND_O;
11687 BaseOp = X86ISD::SUB;
11688 Cond = X86::COND_O;
11691 BaseOp = X86ISD::SUB;
11692 Cond = X86::COND_B;
11695 BaseOp = X86ISD::SMUL;
11696 Cond = X86::COND_O;
11698 case ISD::UMULO: { // i64, i8 = umulo lhs, rhs --> i64, i64, i32 umul lhs,rhs
11699 SDVTList VTs = DAG.getVTList(N->getValueType(0), N->getValueType(0),
11701 SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS);
11704 DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
11705 DAG.getConstant(X86::COND_O, MVT::i32),
11706 SDValue(Sum.getNode(), 2));
11708 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
11712 // Also sets EFLAGS.
11713 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
11714 SDValue Sum = DAG.getNode(BaseOp, DL, VTs, LHS, RHS);
11717 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1),
11718 DAG.getConstant(Cond, MVT::i32),
11719 SDValue(Sum.getNode(), 1));
11721 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
11724 SDValue X86TargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
11725 SelectionDAG &DAG) const {
11726 DebugLoc dl = Op.getDebugLoc();
11727 EVT ExtraVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
11728 EVT VT = Op.getValueType();
11730 if (!Subtarget->hasSSE2() || !VT.isVector())
11733 unsigned BitsDiff = VT.getScalarType().getSizeInBits() -
11734 ExtraVT.getScalarType().getSizeInBits();
11735 SDValue ShAmt = DAG.getConstant(BitsDiff, MVT::i32);
11737 switch (VT.getSimpleVT().SimpleTy) {
11738 default: return SDValue();
11741 if (!Subtarget->hasFp256())
11743 if (!Subtarget->hasInt256()) {
11744 // needs to be split
11745 unsigned NumElems = VT.getVectorNumElements();
11747 // Extract the LHS vectors
11748 SDValue LHS = Op.getOperand(0);
11749 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
11750 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
11752 MVT EltVT = VT.getVectorElementType().getSimpleVT();
11753 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
11755 EVT ExtraEltVT = ExtraVT.getVectorElementType();
11756 unsigned ExtraNumElems = ExtraVT.getVectorNumElements();
11757 ExtraVT = EVT::getVectorVT(*DAG.getContext(), ExtraEltVT,
11759 SDValue Extra = DAG.getValueType(ExtraVT);
11761 LHS1 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, Extra);
11762 LHS2 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, Extra);
11764 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, LHS1, LHS2);
11769 SDValue Tmp1 = getTargetVShiftNode(X86ISD::VSHLI, dl, VT,
11770 Op.getOperand(0), ShAmt, DAG);
11771 return getTargetVShiftNode(X86ISD::VSRAI, dl, VT, Tmp1, ShAmt, DAG);
11776 static SDValue LowerMEMBARRIER(SDValue Op, const X86Subtarget *Subtarget,
11777 SelectionDAG &DAG) {
11778 DebugLoc dl = Op.getDebugLoc();
11780 // Go ahead and emit the fence on x86-64 even if we asked for no-sse2.
11781 // There isn't any reason to disable it if the target processor supports it.
11782 if (!Subtarget->hasSSE2() && !Subtarget->is64Bit()) {
11783 SDValue Chain = Op.getOperand(0);
11784 SDValue Zero = DAG.getConstant(0, MVT::i32);
11786 DAG.getRegister(X86::ESP, MVT::i32), // Base
11787 DAG.getTargetConstant(1, MVT::i8), // Scale
11788 DAG.getRegister(0, MVT::i32), // Index
11789 DAG.getTargetConstant(0, MVT::i32), // Disp
11790 DAG.getRegister(0, MVT::i32), // Segment.
11795 DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops,
11796 array_lengthof(Ops));
11797 return SDValue(Res, 0);
11800 unsigned isDev = cast<ConstantSDNode>(Op.getOperand(5))->getZExtValue();
11802 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
11804 unsigned Op1 = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
11805 unsigned Op2 = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
11806 unsigned Op3 = cast<ConstantSDNode>(Op.getOperand(3))->getZExtValue();
11807 unsigned Op4 = cast<ConstantSDNode>(Op.getOperand(4))->getZExtValue();
11809 // def : Pat<(membarrier (i8 0), (i8 0), (i8 0), (i8 1), (i8 1)), (SFENCE)>;
11810 if (!Op1 && !Op2 && !Op3 && Op4)
11811 return DAG.getNode(X86ISD::SFENCE, dl, MVT::Other, Op.getOperand(0));
11813 // def : Pat<(membarrier (i8 1), (i8 0), (i8 0), (i8 0), (i8 1)), (LFENCE)>;
11814 if (Op1 && !Op2 && !Op3 && !Op4)
11815 return DAG.getNode(X86ISD::LFENCE, dl, MVT::Other, Op.getOperand(0));
11817 // def : Pat<(membarrier (i8 imm), (i8 imm), (i8 imm), (i8 imm), (i8 1)),
11819 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
11822 static SDValue LowerATOMIC_FENCE(SDValue Op, const X86Subtarget *Subtarget,
11823 SelectionDAG &DAG) {
11824 DebugLoc dl = Op.getDebugLoc();
11825 AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>(
11826 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue());
11827 SynchronizationScope FenceScope = static_cast<SynchronizationScope>(
11828 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
11830 // The only fence that needs an instruction is a sequentially-consistent
11831 // cross-thread fence.
11832 if (FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread) {
11833 // Use mfence if we have SSE2 or we're on x86-64 (even if we asked for
11834 // no-sse2). There isn't any reason to disable it if the target processor
11836 if (Subtarget->hasSSE2() || Subtarget->is64Bit())
11837 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
11839 SDValue Chain = Op.getOperand(0);
11840 SDValue Zero = DAG.getConstant(0, MVT::i32);
11842 DAG.getRegister(X86::ESP, MVT::i32), // Base
11843 DAG.getTargetConstant(1, MVT::i8), // Scale
11844 DAG.getRegister(0, MVT::i32), // Index
11845 DAG.getTargetConstant(0, MVT::i32), // Disp
11846 DAG.getRegister(0, MVT::i32), // Segment.
11851 DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops,
11852 array_lengthof(Ops));
11853 return SDValue(Res, 0);
11856 // MEMBARRIER is a compiler barrier; it codegens to a no-op.
11857 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
11860 static SDValue LowerCMP_SWAP(SDValue Op, const X86Subtarget *Subtarget,
11861 SelectionDAG &DAG) {
11862 EVT T = Op.getValueType();
11863 DebugLoc DL = Op.getDebugLoc();
11866 switch(T.getSimpleVT().SimpleTy) {
11867 default: llvm_unreachable("Invalid value type!");
11868 case MVT::i8: Reg = X86::AL; size = 1; break;
11869 case MVT::i16: Reg = X86::AX; size = 2; break;
11870 case MVT::i32: Reg = X86::EAX; size = 4; break;
11872 assert(Subtarget->is64Bit() && "Node not type legal!");
11873 Reg = X86::RAX; size = 8;
11876 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg,
11877 Op.getOperand(2), SDValue());
11878 SDValue Ops[] = { cpIn.getValue(0),
11881 DAG.getTargetConstant(size, MVT::i8),
11882 cpIn.getValue(1) };
11883 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
11884 MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand();
11885 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys,
11888 DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1));
11892 static SDValue LowerREADCYCLECOUNTER(SDValue Op, const X86Subtarget *Subtarget,
11893 SelectionDAG &DAG) {
11894 assert(Subtarget->is64Bit() && "Result not type legalized?");
11895 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
11896 SDValue TheChain = Op.getOperand(0);
11897 DebugLoc dl = Op.getDebugLoc();
11898 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
11899 SDValue rax = DAG.getCopyFromReg(rd, dl, X86::RAX, MVT::i64, rd.getValue(1));
11900 SDValue rdx = DAG.getCopyFromReg(rax.getValue(1), dl, X86::RDX, MVT::i64,
11902 SDValue Tmp = DAG.getNode(ISD::SHL, dl, MVT::i64, rdx,
11903 DAG.getConstant(32, MVT::i8));
11905 DAG.getNode(ISD::OR, dl, MVT::i64, rax, Tmp),
11908 return DAG.getMergeValues(Ops, 2, dl);
11911 SDValue X86TargetLowering::LowerBITCAST(SDValue Op, SelectionDAG &DAG) const {
11912 EVT SrcVT = Op.getOperand(0).getValueType();
11913 EVT DstVT = Op.getValueType();
11914 assert(Subtarget->is64Bit() && !Subtarget->hasSSE2() &&
11915 Subtarget->hasMMX() && "Unexpected custom BITCAST");
11916 assert((DstVT == MVT::i64 ||
11917 (DstVT.isVector() && DstVT.getSizeInBits()==64)) &&
11918 "Unexpected custom BITCAST");
11919 // i64 <=> MMX conversions are Legal.
11920 if (SrcVT==MVT::i64 && DstVT.isVector())
11922 if (DstVT==MVT::i64 && SrcVT.isVector())
11924 // MMX <=> MMX conversions are Legal.
11925 if (SrcVT.isVector() && DstVT.isVector())
11927 // All other conversions need to be expanded.
11931 static SDValue LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) {
11932 SDNode *Node = Op.getNode();
11933 DebugLoc dl = Node->getDebugLoc();
11934 EVT T = Node->getValueType(0);
11935 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
11936 DAG.getConstant(0, T), Node->getOperand(2));
11937 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
11938 cast<AtomicSDNode>(Node)->getMemoryVT(),
11939 Node->getOperand(0),
11940 Node->getOperand(1), negOp,
11941 cast<AtomicSDNode>(Node)->getSrcValue(),
11942 cast<AtomicSDNode>(Node)->getAlignment(),
11943 cast<AtomicSDNode>(Node)->getOrdering(),
11944 cast<AtomicSDNode>(Node)->getSynchScope());
11947 static SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) {
11948 SDNode *Node = Op.getNode();
11949 DebugLoc dl = Node->getDebugLoc();
11950 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
11952 // Convert seq_cst store -> xchg
11953 // Convert wide store -> swap (-> cmpxchg8b/cmpxchg16b)
11954 // FIXME: On 32-bit, store -> fist or movq would be more efficient
11955 // (The only way to get a 16-byte store is cmpxchg16b)
11956 // FIXME: 16-byte ATOMIC_SWAP isn't actually hooked up at the moment.
11957 if (cast<AtomicSDNode>(Node)->getOrdering() == SequentiallyConsistent ||
11958 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
11959 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
11960 cast<AtomicSDNode>(Node)->getMemoryVT(),
11961 Node->getOperand(0),
11962 Node->getOperand(1), Node->getOperand(2),
11963 cast<AtomicSDNode>(Node)->getMemOperand(),
11964 cast<AtomicSDNode>(Node)->getOrdering(),
11965 cast<AtomicSDNode>(Node)->getSynchScope());
11966 return Swap.getValue(1);
11968 // Other atomic stores have a simple pattern.
11972 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
11973 EVT VT = Op.getNode()->getValueType(0);
11975 // Let legalize expand this if it isn't a legal type yet.
11976 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
11979 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
11982 bool ExtraOp = false;
11983 switch (Op.getOpcode()) {
11984 default: llvm_unreachable("Invalid code");
11985 case ISD::ADDC: Opc = X86ISD::ADD; break;
11986 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break;
11987 case ISD::SUBC: Opc = X86ISD::SUB; break;
11988 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break;
11992 return DAG.getNode(Opc, Op->getDebugLoc(), VTs, Op.getOperand(0),
11994 return DAG.getNode(Opc, Op->getDebugLoc(), VTs, Op.getOperand(0),
11995 Op.getOperand(1), Op.getOperand(2));
11998 /// LowerOperation - Provide custom lowering hooks for some operations.
12000 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
12001 switch (Op.getOpcode()) {
12002 default: llvm_unreachable("Should not custom lower this!");
12003 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op,DAG);
12004 case ISD::MEMBARRIER: return LowerMEMBARRIER(Op, Subtarget, DAG);
12005 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, Subtarget, DAG);
12006 case ISD::ATOMIC_CMP_SWAP: return LowerCMP_SWAP(Op, Subtarget, DAG);
12007 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
12008 case ISD::ATOMIC_STORE: return LowerATOMIC_STORE(Op,DAG);
12009 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
12010 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
12011 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
12012 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
12013 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
12014 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op,Subtarget,DAG);
12015 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, Subtarget,DAG);
12016 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
12017 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
12018 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
12019 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
12020 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
12021 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
12022 case ISD::SHL_PARTS:
12023 case ISD::SRA_PARTS:
12024 case ISD::SRL_PARTS: return LowerShiftParts(Op, DAG);
12025 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
12026 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
12027 case ISD::TRUNCATE: return lowerTRUNCATE(Op, DAG);
12028 case ISD::ZERO_EXTEND: return LowerZERO_EXTEND(Op, DAG);
12029 case ISD::SIGN_EXTEND: return LowerSIGN_EXTEND(Op, DAG);
12030 case ISD::ANY_EXTEND: return LowerANY_EXTEND(Op, DAG);
12031 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
12032 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
12033 case ISD::FP_EXTEND: return lowerFP_EXTEND(Op, DAG);
12034 case ISD::FABS: return LowerFABS(Op, DAG);
12035 case ISD::FNEG: return LowerFNEG(Op, DAG);
12036 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
12037 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG);
12038 case ISD::SETCC: return LowerSETCC(Op, DAG);
12039 case ISD::SELECT: return LowerSELECT(Op, DAG);
12040 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
12041 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
12042 case ISD::VASTART: return LowerVASTART(Op, DAG);
12043 case ISD::VAARG: return LowerVAARG(Op, DAG);
12044 case ISD::VACOPY: return LowerVACOPY(Op, Subtarget, DAG);
12045 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
12046 case ISD::INTRINSIC_W_CHAIN: return LowerINTRINSIC_W_CHAIN(Op, DAG);
12047 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
12048 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
12049 case ISD::FRAME_TO_ARGS_OFFSET:
12050 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
12051 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
12052 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
12053 case ISD::EH_SJLJ_SETJMP: return lowerEH_SJLJ_SETJMP(Op, DAG);
12054 case ISD::EH_SJLJ_LONGJMP: return lowerEH_SJLJ_LONGJMP(Op, DAG);
12055 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
12056 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
12057 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
12058 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
12059 case ISD::CTLZ_ZERO_UNDEF: return LowerCTLZ_ZERO_UNDEF(Op, DAG);
12060 case ISD::CTTZ: return LowerCTTZ(Op, DAG);
12061 case ISD::MUL: return LowerMUL(Op, Subtarget, DAG);
12064 case ISD::SHL: return LowerShift(Op, DAG);
12070 case ISD::UMULO: return LowerXALUO(Op, DAG);
12071 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, Subtarget,DAG);
12072 case ISD::BITCAST: return LowerBITCAST(Op, DAG);
12076 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
12077 case ISD::ADD: return LowerADD(Op, DAG);
12078 case ISD::SUB: return LowerSUB(Op, DAG);
12079 case ISD::SDIV: return LowerSDIV(Op, DAG);
12083 static void ReplaceATOMIC_LOAD(SDNode *Node,
12084 SmallVectorImpl<SDValue> &Results,
12085 SelectionDAG &DAG) {
12086 DebugLoc dl = Node->getDebugLoc();
12087 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
12089 // Convert wide load -> cmpxchg8b/cmpxchg16b
12090 // FIXME: On 32-bit, load -> fild or movq would be more efficient
12091 // (The only way to get a 16-byte load is cmpxchg16b)
12092 // FIXME: 16-byte ATOMIC_CMP_SWAP isn't actually hooked up at the moment.
12093 SDValue Zero = DAG.getConstant(0, VT);
12094 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, dl, VT,
12095 Node->getOperand(0),
12096 Node->getOperand(1), Zero, Zero,
12097 cast<AtomicSDNode>(Node)->getMemOperand(),
12098 cast<AtomicSDNode>(Node)->getOrdering(),
12099 cast<AtomicSDNode>(Node)->getSynchScope());
12100 Results.push_back(Swap.getValue(0));
12101 Results.push_back(Swap.getValue(1));
12105 ReplaceATOMIC_BINARY_64(SDNode *Node, SmallVectorImpl<SDValue>&Results,
12106 SelectionDAG &DAG, unsigned NewOp) {
12107 DebugLoc dl = Node->getDebugLoc();
12108 assert (Node->getValueType(0) == MVT::i64 &&
12109 "Only know how to expand i64 atomics");
12111 SDValue Chain = Node->getOperand(0);
12112 SDValue In1 = Node->getOperand(1);
12113 SDValue In2L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
12114 Node->getOperand(2), DAG.getIntPtrConstant(0));
12115 SDValue In2H = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
12116 Node->getOperand(2), DAG.getIntPtrConstant(1));
12117 SDValue Ops[] = { Chain, In1, In2L, In2H };
12118 SDVTList Tys = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other);
12120 DAG.getMemIntrinsicNode(NewOp, dl, Tys, Ops, 4, MVT::i64,
12121 cast<MemSDNode>(Node)->getMemOperand());
12122 SDValue OpsF[] = { Result.getValue(0), Result.getValue(1)};
12123 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2));
12124 Results.push_back(Result.getValue(2));
12127 /// ReplaceNodeResults - Replace a node with an illegal result type
12128 /// with a new node built out of custom code.
12129 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
12130 SmallVectorImpl<SDValue>&Results,
12131 SelectionDAG &DAG) const {
12132 DebugLoc dl = N->getDebugLoc();
12133 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
12134 switch (N->getOpcode()) {
12136 llvm_unreachable("Do not know how to custom type legalize this operation!");
12137 case ISD::SIGN_EXTEND_INREG:
12142 // We don't want to expand or promote these.
12144 case ISD::FP_TO_SINT:
12145 case ISD::FP_TO_UINT: {
12146 bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT;
12148 if (!IsSigned && !isIntegerTypeFTOL(SDValue(N, 0).getValueType()))
12151 std::pair<SDValue,SDValue> Vals =
12152 FP_TO_INTHelper(SDValue(N, 0), DAG, IsSigned, /*IsReplace=*/ true);
12153 SDValue FIST = Vals.first, StackSlot = Vals.second;
12154 if (FIST.getNode() != 0) {
12155 EVT VT = N->getValueType(0);
12156 // Return a load from the stack slot.
12157 if (StackSlot.getNode() != 0)
12158 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot,
12159 MachinePointerInfo(),
12160 false, false, false, 0));
12162 Results.push_back(FIST);
12166 case ISD::UINT_TO_FP: {
12167 if (N->getOperand(0).getValueType() != MVT::v2i32 &&
12168 N->getValueType(0) != MVT::v2f32)
12170 SDValue ZExtIn = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v2i64,
12172 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
12174 SDValue VBias = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2f64, Bias, Bias);
12175 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64, ZExtIn,
12176 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, VBias));
12177 Or = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or);
12178 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, Or, VBias);
12179 Results.push_back(DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, Sub));
12182 case ISD::FP_ROUND: {
12183 if (!TLI.isTypeLegal(N->getOperand(0).getValueType()))
12185 SDValue V = DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, N->getOperand(0));
12186 Results.push_back(V);
12189 case ISD::READCYCLECOUNTER: {
12190 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
12191 SDValue TheChain = N->getOperand(0);
12192 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
12193 SDValue eax = DAG.getCopyFromReg(rd, dl, X86::EAX, MVT::i32,
12195 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), dl, X86::EDX, MVT::i32,
12197 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
12198 SDValue Ops[] = { eax, edx };
12199 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Ops, 2));
12200 Results.push_back(edx.getValue(1));
12203 case ISD::ATOMIC_CMP_SWAP: {
12204 EVT T = N->getValueType(0);
12205 assert((T == MVT::i64 || T == MVT::i128) && "can only expand cmpxchg pair");
12206 bool Regs64bit = T == MVT::i128;
12207 EVT HalfT = Regs64bit ? MVT::i64 : MVT::i32;
12208 SDValue cpInL, cpInH;
12209 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
12210 DAG.getConstant(0, HalfT));
12211 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
12212 DAG.getConstant(1, HalfT));
12213 cpInL = DAG.getCopyToReg(N->getOperand(0), dl,
12214 Regs64bit ? X86::RAX : X86::EAX,
12216 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl,
12217 Regs64bit ? X86::RDX : X86::EDX,
12218 cpInH, cpInL.getValue(1));
12219 SDValue swapInL, swapInH;
12220 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
12221 DAG.getConstant(0, HalfT));
12222 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
12223 DAG.getConstant(1, HalfT));
12224 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl,
12225 Regs64bit ? X86::RBX : X86::EBX,
12226 swapInL, cpInH.getValue(1));
12227 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl,
12228 Regs64bit ? X86::RCX : X86::ECX,
12229 swapInH, swapInL.getValue(1));
12230 SDValue Ops[] = { swapInH.getValue(0),
12232 swapInH.getValue(1) };
12233 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
12234 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand();
12235 unsigned Opcode = Regs64bit ? X86ISD::LCMPXCHG16_DAG :
12236 X86ISD::LCMPXCHG8_DAG;
12237 SDValue Result = DAG.getMemIntrinsicNode(Opcode, dl, Tys,
12239 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl,
12240 Regs64bit ? X86::RAX : X86::EAX,
12241 HalfT, Result.getValue(1));
12242 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl,
12243 Regs64bit ? X86::RDX : X86::EDX,
12244 HalfT, cpOutL.getValue(2));
12245 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
12246 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, T, OpsF, 2));
12247 Results.push_back(cpOutH.getValue(1));
12250 case ISD::ATOMIC_LOAD_ADD:
12251 case ISD::ATOMIC_LOAD_AND:
12252 case ISD::ATOMIC_LOAD_NAND:
12253 case ISD::ATOMIC_LOAD_OR:
12254 case ISD::ATOMIC_LOAD_SUB:
12255 case ISD::ATOMIC_LOAD_XOR:
12256 case ISD::ATOMIC_LOAD_MAX:
12257 case ISD::ATOMIC_LOAD_MIN:
12258 case ISD::ATOMIC_LOAD_UMAX:
12259 case ISD::ATOMIC_LOAD_UMIN:
12260 case ISD::ATOMIC_SWAP: {
12262 switch (N->getOpcode()) {
12263 default: llvm_unreachable("Unexpected opcode");
12264 case ISD::ATOMIC_LOAD_ADD:
12265 Opc = X86ISD::ATOMADD64_DAG;
12267 case ISD::ATOMIC_LOAD_AND:
12268 Opc = X86ISD::ATOMAND64_DAG;
12270 case ISD::ATOMIC_LOAD_NAND:
12271 Opc = X86ISD::ATOMNAND64_DAG;
12273 case ISD::ATOMIC_LOAD_OR:
12274 Opc = X86ISD::ATOMOR64_DAG;
12276 case ISD::ATOMIC_LOAD_SUB:
12277 Opc = X86ISD::ATOMSUB64_DAG;
12279 case ISD::ATOMIC_LOAD_XOR:
12280 Opc = X86ISD::ATOMXOR64_DAG;
12282 case ISD::ATOMIC_LOAD_MAX:
12283 Opc = X86ISD::ATOMMAX64_DAG;
12285 case ISD::ATOMIC_LOAD_MIN:
12286 Opc = X86ISD::ATOMMIN64_DAG;
12288 case ISD::ATOMIC_LOAD_UMAX:
12289 Opc = X86ISD::ATOMUMAX64_DAG;
12291 case ISD::ATOMIC_LOAD_UMIN:
12292 Opc = X86ISD::ATOMUMIN64_DAG;
12294 case ISD::ATOMIC_SWAP:
12295 Opc = X86ISD::ATOMSWAP64_DAG;
12298 ReplaceATOMIC_BINARY_64(N, Results, DAG, Opc);
12301 case ISD::ATOMIC_LOAD:
12302 ReplaceATOMIC_LOAD(N, Results, DAG);
12306 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
12308 default: return NULL;
12309 case X86ISD::BSF: return "X86ISD::BSF";
12310 case X86ISD::BSR: return "X86ISD::BSR";
12311 case X86ISD::SHLD: return "X86ISD::SHLD";
12312 case X86ISD::SHRD: return "X86ISD::SHRD";
12313 case X86ISD::FAND: return "X86ISD::FAND";
12314 case X86ISD::FOR: return "X86ISD::FOR";
12315 case X86ISD::FXOR: return "X86ISD::FXOR";
12316 case X86ISD::FSRL: return "X86ISD::FSRL";
12317 case X86ISD::FILD: return "X86ISD::FILD";
12318 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
12319 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
12320 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
12321 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
12322 case X86ISD::FLD: return "X86ISD::FLD";
12323 case X86ISD::FST: return "X86ISD::FST";
12324 case X86ISD::CALL: return "X86ISD::CALL";
12325 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
12326 case X86ISD::BT: return "X86ISD::BT";
12327 case X86ISD::CMP: return "X86ISD::CMP";
12328 case X86ISD::COMI: return "X86ISD::COMI";
12329 case X86ISD::UCOMI: return "X86ISD::UCOMI";
12330 case X86ISD::SETCC: return "X86ISD::SETCC";
12331 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY";
12332 case X86ISD::FSETCCsd: return "X86ISD::FSETCCsd";
12333 case X86ISD::FSETCCss: return "X86ISD::FSETCCss";
12334 case X86ISD::CMOV: return "X86ISD::CMOV";
12335 case X86ISD::BRCOND: return "X86ISD::BRCOND";
12336 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
12337 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
12338 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
12339 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
12340 case X86ISD::Wrapper: return "X86ISD::Wrapper";
12341 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
12342 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
12343 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
12344 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
12345 case X86ISD::PINSRB: return "X86ISD::PINSRB";
12346 case X86ISD::PINSRW: return "X86ISD::PINSRW";
12347 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
12348 case X86ISD::ANDNP: return "X86ISD::ANDNP";
12349 case X86ISD::PSIGN: return "X86ISD::PSIGN";
12350 case X86ISD::BLENDV: return "X86ISD::BLENDV";
12351 case X86ISD::BLENDI: return "X86ISD::BLENDI";
12352 case X86ISD::SUBUS: return "X86ISD::SUBUS";
12353 case X86ISD::HADD: return "X86ISD::HADD";
12354 case X86ISD::HSUB: return "X86ISD::HSUB";
12355 case X86ISD::FHADD: return "X86ISD::FHADD";
12356 case X86ISD::FHSUB: return "X86ISD::FHSUB";
12357 case X86ISD::UMAX: return "X86ISD::UMAX";
12358 case X86ISD::UMIN: return "X86ISD::UMIN";
12359 case X86ISD::SMAX: return "X86ISD::SMAX";
12360 case X86ISD::SMIN: return "X86ISD::SMIN";
12361 case X86ISD::FMAX: return "X86ISD::FMAX";
12362 case X86ISD::FMIN: return "X86ISD::FMIN";
12363 case X86ISD::FMAXC: return "X86ISD::FMAXC";
12364 case X86ISD::FMINC: return "X86ISD::FMINC";
12365 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
12366 case X86ISD::FRCP: return "X86ISD::FRCP";
12367 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
12368 case X86ISD::TLSBASEADDR: return "X86ISD::TLSBASEADDR";
12369 case X86ISD::TLSCALL: return "X86ISD::TLSCALL";
12370 case X86ISD::EH_SJLJ_SETJMP: return "X86ISD::EH_SJLJ_SETJMP";
12371 case X86ISD::EH_SJLJ_LONGJMP: return "X86ISD::EH_SJLJ_LONGJMP";
12372 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
12373 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
12374 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
12375 case X86ISD::FNSTSW16r: return "X86ISD::FNSTSW16r";
12376 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
12377 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
12378 case X86ISD::ATOMADD64_DAG: return "X86ISD::ATOMADD64_DAG";
12379 case X86ISD::ATOMSUB64_DAG: return "X86ISD::ATOMSUB64_DAG";
12380 case X86ISD::ATOMOR64_DAG: return "X86ISD::ATOMOR64_DAG";
12381 case X86ISD::ATOMXOR64_DAG: return "X86ISD::ATOMXOR64_DAG";
12382 case X86ISD::ATOMAND64_DAG: return "X86ISD::ATOMAND64_DAG";
12383 case X86ISD::ATOMNAND64_DAG: return "X86ISD::ATOMNAND64_DAG";
12384 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
12385 case X86ISD::VSEXT_MOVL: return "X86ISD::VSEXT_MOVL";
12386 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
12387 case X86ISD::VZEXT: return "X86ISD::VZEXT";
12388 case X86ISD::VSEXT: return "X86ISD::VSEXT";
12389 case X86ISD::VFPEXT: return "X86ISD::VFPEXT";
12390 case X86ISD::VFPROUND: return "X86ISD::VFPROUND";
12391 case X86ISD::VSHLDQ: return "X86ISD::VSHLDQ";
12392 case X86ISD::VSRLDQ: return "X86ISD::VSRLDQ";
12393 case X86ISD::VSHL: return "X86ISD::VSHL";
12394 case X86ISD::VSRL: return "X86ISD::VSRL";
12395 case X86ISD::VSRA: return "X86ISD::VSRA";
12396 case X86ISD::VSHLI: return "X86ISD::VSHLI";
12397 case X86ISD::VSRLI: return "X86ISD::VSRLI";
12398 case X86ISD::VSRAI: return "X86ISD::VSRAI";
12399 case X86ISD::CMPP: return "X86ISD::CMPP";
12400 case X86ISD::PCMPEQ: return "X86ISD::PCMPEQ";
12401 case X86ISD::PCMPGT: return "X86ISD::PCMPGT";
12402 case X86ISD::ADD: return "X86ISD::ADD";
12403 case X86ISD::SUB: return "X86ISD::SUB";
12404 case X86ISD::ADC: return "X86ISD::ADC";
12405 case X86ISD::SBB: return "X86ISD::SBB";
12406 case X86ISD::SMUL: return "X86ISD::SMUL";
12407 case X86ISD::UMUL: return "X86ISD::UMUL";
12408 case X86ISD::INC: return "X86ISD::INC";
12409 case X86ISD::DEC: return "X86ISD::DEC";
12410 case X86ISD::OR: return "X86ISD::OR";
12411 case X86ISD::XOR: return "X86ISD::XOR";
12412 case X86ISD::AND: return "X86ISD::AND";
12413 case X86ISD::BLSI: return "X86ISD::BLSI";
12414 case X86ISD::BLSMSK: return "X86ISD::BLSMSK";
12415 case X86ISD::BLSR: return "X86ISD::BLSR";
12416 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
12417 case X86ISD::PTEST: return "X86ISD::PTEST";
12418 case X86ISD::TESTP: return "X86ISD::TESTP";
12419 case X86ISD::PALIGN: return "X86ISD::PALIGN";
12420 case X86ISD::PSHUFD: return "X86ISD::PSHUFD";
12421 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW";
12422 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW";
12423 case X86ISD::SHUFP: return "X86ISD::SHUFP";
12424 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS";
12425 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD";
12426 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS";
12427 case X86ISD::MOVLPS: return "X86ISD::MOVLPS";
12428 case X86ISD::MOVLPD: return "X86ISD::MOVLPD";
12429 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP";
12430 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP";
12431 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP";
12432 case X86ISD::MOVSD: return "X86ISD::MOVSD";
12433 case X86ISD::MOVSS: return "X86ISD::MOVSS";
12434 case X86ISD::UNPCKL: return "X86ISD::UNPCKL";
12435 case X86ISD::UNPCKH: return "X86ISD::UNPCKH";
12436 case X86ISD::VBROADCAST: return "X86ISD::VBROADCAST";
12437 case X86ISD::VPERMILP: return "X86ISD::VPERMILP";
12438 case X86ISD::VPERM2X128: return "X86ISD::VPERM2X128";
12439 case X86ISD::VPERMV: return "X86ISD::VPERMV";
12440 case X86ISD::VPERMI: return "X86ISD::VPERMI";
12441 case X86ISD::PMULUDQ: return "X86ISD::PMULUDQ";
12442 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
12443 case X86ISD::VAARG_64: return "X86ISD::VAARG_64";
12444 case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA";
12445 case X86ISD::MEMBARRIER: return "X86ISD::MEMBARRIER";
12446 case X86ISD::SEG_ALLOCA: return "X86ISD::SEG_ALLOCA";
12447 case X86ISD::WIN_FTOL: return "X86ISD::WIN_FTOL";
12448 case X86ISD::SAHF: return "X86ISD::SAHF";
12449 case X86ISD::RDRAND: return "X86ISD::RDRAND";
12450 case X86ISD::FMADD: return "X86ISD::FMADD";
12451 case X86ISD::FMSUB: return "X86ISD::FMSUB";
12452 case X86ISD::FNMADD: return "X86ISD::FNMADD";
12453 case X86ISD::FNMSUB: return "X86ISD::FNMSUB";
12454 case X86ISD::FMADDSUB: return "X86ISD::FMADDSUB";
12455 case X86ISD::FMSUBADD: return "X86ISD::FMSUBADD";
12456 case X86ISD::PCMPESTRI: return "X86ISD::PCMPESTRI";
12457 case X86ISD::PCMPISTRI: return "X86ISD::PCMPISTRI";
12461 // isLegalAddressingMode - Return true if the addressing mode represented
12462 // by AM is legal for this target, for a load/store of the specified type.
12463 bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
12465 // X86 supports extremely general addressing modes.
12466 CodeModel::Model M = getTargetMachine().getCodeModel();
12467 Reloc::Model R = getTargetMachine().getRelocationModel();
12469 // X86 allows a sign-extended 32-bit immediate field as a displacement.
12470 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != NULL))
12475 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
12477 // If a reference to this global requires an extra load, we can't fold it.
12478 if (isGlobalStubReference(GVFlags))
12481 // If BaseGV requires a register for the PIC base, we cannot also have a
12482 // BaseReg specified.
12483 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
12486 // If lower 4G is not available, then we must use rip-relative addressing.
12487 if ((M != CodeModel::Small || R != Reloc::Static) &&
12488 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
12492 switch (AM.Scale) {
12498 // These scales always work.
12503 // These scales are formed with basereg+scalereg. Only accept if there is
12508 default: // Other stuff never works.
12515 bool X86TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
12516 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
12518 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
12519 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
12520 return NumBits1 > NumBits2;
12523 bool X86TargetLowering::isLegalICmpImmediate(int64_t Imm) const {
12524 return isInt<32>(Imm);
12527 bool X86TargetLowering::isLegalAddImmediate(int64_t Imm) const {
12528 // Can also use sub to handle negated immediates.
12529 return isInt<32>(Imm);
12532 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
12533 if (!VT1.isInteger() || !VT2.isInteger())
12535 unsigned NumBits1 = VT1.getSizeInBits();
12536 unsigned NumBits2 = VT2.getSizeInBits();
12537 return NumBits1 > NumBits2;
12540 bool X86TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
12541 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
12542 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit();
12545 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
12546 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
12547 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
12550 bool X86TargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
12551 EVT VT1 = Val.getValueType();
12552 if (isZExtFree(VT1, VT2))
12555 if (Val.getOpcode() != ISD::LOAD)
12558 if (!VT1.isSimple() || !VT1.isInteger() ||
12559 !VT2.isSimple() || !VT2.isInteger())
12562 switch (VT1.getSimpleVT().SimpleTy) {
12567 // X86 has 8, 16, and 32-bit zero-extending loads.
12574 bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
12575 // i16 instructions are longer (0x66 prefix) and potentially slower.
12576 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
12579 /// isShuffleMaskLegal - Targets can use this to indicate that they only
12580 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
12581 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
12582 /// are assumed to be legal.
12584 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
12586 // Very little shuffling can be done for 64-bit vectors right now.
12587 if (VT.getSizeInBits() == 64)
12590 // FIXME: pshufb, blends, shifts.
12591 return (VT.getVectorNumElements() == 2 ||
12592 ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
12593 isMOVLMask(M, VT) ||
12594 isSHUFPMask(M, VT, Subtarget->hasFp256()) ||
12595 isPSHUFDMask(M, VT) ||
12596 isPSHUFHWMask(M, VT, Subtarget->hasInt256()) ||
12597 isPSHUFLWMask(M, VT, Subtarget->hasInt256()) ||
12598 isPALIGNRMask(M, VT, Subtarget) ||
12599 isUNPCKLMask(M, VT, Subtarget->hasInt256()) ||
12600 isUNPCKHMask(M, VT, Subtarget->hasInt256()) ||
12601 isUNPCKL_v_undef_Mask(M, VT, Subtarget->hasInt256()) ||
12602 isUNPCKH_v_undef_Mask(M, VT, Subtarget->hasInt256()));
12606 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
12608 unsigned NumElts = VT.getVectorNumElements();
12609 // FIXME: This collection of masks seems suspect.
12612 if (NumElts == 4 && VT.is128BitVector()) {
12613 return (isMOVLMask(Mask, VT) ||
12614 isCommutedMOVLMask(Mask, VT, true) ||
12615 isSHUFPMask(Mask, VT, Subtarget->hasFp256()) ||
12616 isSHUFPMask(Mask, VT, Subtarget->hasFp256(), /* Commuted */ true));
12621 //===----------------------------------------------------------------------===//
12622 // X86 Scheduler Hooks
12623 //===----------------------------------------------------------------------===//
12625 /// Utility function to emit xbegin specifying the start of an RTM region.
12626 static MachineBasicBlock *EmitXBegin(MachineInstr *MI, MachineBasicBlock *MBB,
12627 const TargetInstrInfo *TII) {
12628 DebugLoc DL = MI->getDebugLoc();
12630 const BasicBlock *BB = MBB->getBasicBlock();
12631 MachineFunction::iterator I = MBB;
12634 // For the v = xbegin(), we generate
12645 MachineBasicBlock *thisMBB = MBB;
12646 MachineFunction *MF = MBB->getParent();
12647 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
12648 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
12649 MF->insert(I, mainMBB);
12650 MF->insert(I, sinkMBB);
12652 // Transfer the remainder of BB and its successor edges to sinkMBB.
12653 sinkMBB->splice(sinkMBB->begin(), MBB,
12654 llvm::next(MachineBasicBlock::iterator(MI)), MBB->end());
12655 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
12659 // # fallthrough to mainMBB
12660 // # abortion to sinkMBB
12661 BuildMI(thisMBB, DL, TII->get(X86::XBEGIN_4)).addMBB(sinkMBB);
12662 thisMBB->addSuccessor(mainMBB);
12663 thisMBB->addSuccessor(sinkMBB);
12667 BuildMI(mainMBB, DL, TII->get(X86::MOV32ri), X86::EAX).addImm(-1);
12668 mainMBB->addSuccessor(sinkMBB);
12671 // EAX is live into the sinkMBB
12672 sinkMBB->addLiveIn(X86::EAX);
12673 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
12674 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
12677 MI->eraseFromParent();
12681 // Get CMPXCHG opcode for the specified data type.
12682 static unsigned getCmpXChgOpcode(EVT VT) {
12683 switch (VT.getSimpleVT().SimpleTy) {
12684 case MVT::i8: return X86::LCMPXCHG8;
12685 case MVT::i16: return X86::LCMPXCHG16;
12686 case MVT::i32: return X86::LCMPXCHG32;
12687 case MVT::i64: return X86::LCMPXCHG64;
12691 llvm_unreachable("Invalid operand size!");
12694 // Get LOAD opcode for the specified data type.
12695 static unsigned getLoadOpcode(EVT VT) {
12696 switch (VT.getSimpleVT().SimpleTy) {
12697 case MVT::i8: return X86::MOV8rm;
12698 case MVT::i16: return X86::MOV16rm;
12699 case MVT::i32: return X86::MOV32rm;
12700 case MVT::i64: return X86::MOV64rm;
12704 llvm_unreachable("Invalid operand size!");
12707 // Get opcode of the non-atomic one from the specified atomic instruction.
12708 static unsigned getNonAtomicOpcode(unsigned Opc) {
12710 case X86::ATOMAND8: return X86::AND8rr;
12711 case X86::ATOMAND16: return X86::AND16rr;
12712 case X86::ATOMAND32: return X86::AND32rr;
12713 case X86::ATOMAND64: return X86::AND64rr;
12714 case X86::ATOMOR8: return X86::OR8rr;
12715 case X86::ATOMOR16: return X86::OR16rr;
12716 case X86::ATOMOR32: return X86::OR32rr;
12717 case X86::ATOMOR64: return X86::OR64rr;
12718 case X86::ATOMXOR8: return X86::XOR8rr;
12719 case X86::ATOMXOR16: return X86::XOR16rr;
12720 case X86::ATOMXOR32: return X86::XOR32rr;
12721 case X86::ATOMXOR64: return X86::XOR64rr;
12723 llvm_unreachable("Unhandled atomic-load-op opcode!");
12726 // Get opcode of the non-atomic one from the specified atomic instruction with
12728 static unsigned getNonAtomicOpcodeWithExtraOpc(unsigned Opc,
12729 unsigned &ExtraOpc) {
12731 case X86::ATOMNAND8: ExtraOpc = X86::NOT8r; return X86::AND8rr;
12732 case X86::ATOMNAND16: ExtraOpc = X86::NOT16r; return X86::AND16rr;
12733 case X86::ATOMNAND32: ExtraOpc = X86::NOT32r; return X86::AND32rr;
12734 case X86::ATOMNAND64: ExtraOpc = X86::NOT64r; return X86::AND64rr;
12735 case X86::ATOMMAX8: ExtraOpc = X86::CMP8rr; return X86::CMOVL32rr;
12736 case X86::ATOMMAX16: ExtraOpc = X86::CMP16rr; return X86::CMOVL16rr;
12737 case X86::ATOMMAX32: ExtraOpc = X86::CMP32rr; return X86::CMOVL32rr;
12738 case X86::ATOMMAX64: ExtraOpc = X86::CMP64rr; return X86::CMOVL64rr;
12739 case X86::ATOMMIN8: ExtraOpc = X86::CMP8rr; return X86::CMOVG32rr;
12740 case X86::ATOMMIN16: ExtraOpc = X86::CMP16rr; return X86::CMOVG16rr;
12741 case X86::ATOMMIN32: ExtraOpc = X86::CMP32rr; return X86::CMOVG32rr;
12742 case X86::ATOMMIN64: ExtraOpc = X86::CMP64rr; return X86::CMOVG64rr;
12743 case X86::ATOMUMAX8: ExtraOpc = X86::CMP8rr; return X86::CMOVB32rr;
12744 case X86::ATOMUMAX16: ExtraOpc = X86::CMP16rr; return X86::CMOVB16rr;
12745 case X86::ATOMUMAX32: ExtraOpc = X86::CMP32rr; return X86::CMOVB32rr;
12746 case X86::ATOMUMAX64: ExtraOpc = X86::CMP64rr; return X86::CMOVB64rr;
12747 case X86::ATOMUMIN8: ExtraOpc = X86::CMP8rr; return X86::CMOVA32rr;
12748 case X86::ATOMUMIN16: ExtraOpc = X86::CMP16rr; return X86::CMOVA16rr;
12749 case X86::ATOMUMIN32: ExtraOpc = X86::CMP32rr; return X86::CMOVA32rr;
12750 case X86::ATOMUMIN64: ExtraOpc = X86::CMP64rr; return X86::CMOVA64rr;
12752 llvm_unreachable("Unhandled atomic-load-op opcode!");
12755 // Get opcode of the non-atomic one from the specified atomic instruction for
12756 // 64-bit data type on 32-bit target.
12757 static unsigned getNonAtomic6432Opcode(unsigned Opc, unsigned &HiOpc) {
12759 case X86::ATOMAND6432: HiOpc = X86::AND32rr; return X86::AND32rr;
12760 case X86::ATOMOR6432: HiOpc = X86::OR32rr; return X86::OR32rr;
12761 case X86::ATOMXOR6432: HiOpc = X86::XOR32rr; return X86::XOR32rr;
12762 case X86::ATOMADD6432: HiOpc = X86::ADC32rr; return X86::ADD32rr;
12763 case X86::ATOMSUB6432: HiOpc = X86::SBB32rr; return X86::SUB32rr;
12764 case X86::ATOMSWAP6432: HiOpc = X86::MOV32rr; return X86::MOV32rr;
12765 case X86::ATOMMAX6432: HiOpc = X86::SETLr; return X86::SETLr;
12766 case X86::ATOMMIN6432: HiOpc = X86::SETGr; return X86::SETGr;
12767 case X86::ATOMUMAX6432: HiOpc = X86::SETBr; return X86::SETBr;
12768 case X86::ATOMUMIN6432: HiOpc = X86::SETAr; return X86::SETAr;
12770 llvm_unreachable("Unhandled atomic-load-op opcode!");
12773 // Get opcode of the non-atomic one from the specified atomic instruction for
12774 // 64-bit data type on 32-bit target with extra opcode.
12775 static unsigned getNonAtomic6432OpcodeWithExtraOpc(unsigned Opc,
12777 unsigned &ExtraOpc) {
12779 case X86::ATOMNAND6432:
12780 ExtraOpc = X86::NOT32r;
12781 HiOpc = X86::AND32rr;
12782 return X86::AND32rr;
12784 llvm_unreachable("Unhandled atomic-load-op opcode!");
12787 // Get pseudo CMOV opcode from the specified data type.
12788 static unsigned getPseudoCMOVOpc(EVT VT) {
12789 switch (VT.getSimpleVT().SimpleTy) {
12790 case MVT::i8: return X86::CMOV_GR8;
12791 case MVT::i16: return X86::CMOV_GR16;
12792 case MVT::i32: return X86::CMOV_GR32;
12796 llvm_unreachable("Unknown CMOV opcode!");
12799 // EmitAtomicLoadArith - emit the code sequence for pseudo atomic instructions.
12800 // They will be translated into a spin-loop or compare-exchange loop from
12803 // dst = atomic-fetch-op MI.addr, MI.val
12809 // EAX = LOAD MI.addr
12811 // t1 = OP MI.val, EAX
12812 // LCMPXCHG [MI.addr], t1, [EAX is implicitly used & defined]
12817 MachineBasicBlock *
12818 X86TargetLowering::EmitAtomicLoadArith(MachineInstr *MI,
12819 MachineBasicBlock *MBB) const {
12820 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
12821 DebugLoc DL = MI->getDebugLoc();
12823 MachineFunction *MF = MBB->getParent();
12824 MachineRegisterInfo &MRI = MF->getRegInfo();
12826 const BasicBlock *BB = MBB->getBasicBlock();
12827 MachineFunction::iterator I = MBB;
12830 assert(MI->getNumOperands() <= X86::AddrNumOperands + 2 &&
12831 "Unexpected number of operands");
12833 assert(MI->hasOneMemOperand() &&
12834 "Expected atomic-load-op to have one memoperand");
12836 // Memory Reference
12837 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
12838 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
12840 unsigned DstReg, SrcReg;
12841 unsigned MemOpndSlot;
12843 unsigned CurOp = 0;
12845 DstReg = MI->getOperand(CurOp++).getReg();
12846 MemOpndSlot = CurOp;
12847 CurOp += X86::AddrNumOperands;
12848 SrcReg = MI->getOperand(CurOp++).getReg();
12850 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
12851 MVT::SimpleValueType VT = *RC->vt_begin();
12852 unsigned AccPhyReg = getX86SubSuperRegister(X86::EAX, VT);
12854 unsigned LCMPXCHGOpc = getCmpXChgOpcode(VT);
12855 unsigned LOADOpc = getLoadOpcode(VT);
12857 // For the atomic load-arith operator, we generate
12860 // EAX = LOAD [MI.addr]
12862 // t1 = OP MI.val, EAX
12863 // LCMPXCHG [MI.addr], t1, [EAX is implicitly used & defined]
12867 MachineBasicBlock *thisMBB = MBB;
12868 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
12869 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
12870 MF->insert(I, mainMBB);
12871 MF->insert(I, sinkMBB);
12873 MachineInstrBuilder MIB;
12875 // Transfer the remainder of BB and its successor edges to sinkMBB.
12876 sinkMBB->splice(sinkMBB->begin(), MBB,
12877 llvm::next(MachineBasicBlock::iterator(MI)), MBB->end());
12878 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
12881 MIB = BuildMI(thisMBB, DL, TII->get(LOADOpc), AccPhyReg);
12882 for (unsigned i = 0; i < X86::AddrNumOperands; ++i)
12883 MIB.addOperand(MI->getOperand(MemOpndSlot + i));
12884 MIB.setMemRefs(MMOBegin, MMOEnd);
12886 thisMBB->addSuccessor(mainMBB);
12889 MachineBasicBlock *origMainMBB = mainMBB;
12890 mainMBB->addLiveIn(AccPhyReg);
12892 // Copy AccPhyReg as it is used more than once.
12893 unsigned AccReg = MRI.createVirtualRegister(RC);
12894 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), AccReg)
12895 .addReg(AccPhyReg);
12897 unsigned t1 = MRI.createVirtualRegister(RC);
12898 unsigned Opc = MI->getOpcode();
12901 llvm_unreachable("Unhandled atomic-load-op opcode!");
12902 case X86::ATOMAND8:
12903 case X86::ATOMAND16:
12904 case X86::ATOMAND32:
12905 case X86::ATOMAND64:
12907 case X86::ATOMOR16:
12908 case X86::ATOMOR32:
12909 case X86::ATOMOR64:
12910 case X86::ATOMXOR8:
12911 case X86::ATOMXOR16:
12912 case X86::ATOMXOR32:
12913 case X86::ATOMXOR64: {
12914 unsigned ARITHOpc = getNonAtomicOpcode(Opc);
12915 BuildMI(mainMBB, DL, TII->get(ARITHOpc), t1).addReg(SrcReg)
12919 case X86::ATOMNAND8:
12920 case X86::ATOMNAND16:
12921 case X86::ATOMNAND32:
12922 case X86::ATOMNAND64: {
12923 unsigned t2 = MRI.createVirtualRegister(RC);
12925 unsigned ANDOpc = getNonAtomicOpcodeWithExtraOpc(Opc, NOTOpc);
12926 BuildMI(mainMBB, DL, TII->get(ANDOpc), t2).addReg(SrcReg)
12928 BuildMI(mainMBB, DL, TII->get(NOTOpc), t1).addReg(t2);
12931 case X86::ATOMMAX8:
12932 case X86::ATOMMAX16:
12933 case X86::ATOMMAX32:
12934 case X86::ATOMMAX64:
12935 case X86::ATOMMIN8:
12936 case X86::ATOMMIN16:
12937 case X86::ATOMMIN32:
12938 case X86::ATOMMIN64:
12939 case X86::ATOMUMAX8:
12940 case X86::ATOMUMAX16:
12941 case X86::ATOMUMAX32:
12942 case X86::ATOMUMAX64:
12943 case X86::ATOMUMIN8:
12944 case X86::ATOMUMIN16:
12945 case X86::ATOMUMIN32:
12946 case X86::ATOMUMIN64: {
12948 unsigned CMOVOpc = getNonAtomicOpcodeWithExtraOpc(Opc, CMPOpc);
12950 BuildMI(mainMBB, DL, TII->get(CMPOpc))
12954 if (Subtarget->hasCMov()) {
12955 if (VT != MVT::i8) {
12957 BuildMI(mainMBB, DL, TII->get(CMOVOpc), t1)
12961 // Promote i8 to i32 to use CMOV32
12962 const TargetRegisterClass *RC32 = getRegClassFor(MVT::i32);
12963 unsigned SrcReg32 = MRI.createVirtualRegister(RC32);
12964 unsigned AccReg32 = MRI.createVirtualRegister(RC32);
12965 unsigned t2 = MRI.createVirtualRegister(RC32);
12967 unsigned Undef = MRI.createVirtualRegister(RC32);
12968 BuildMI(mainMBB, DL, TII->get(TargetOpcode::IMPLICIT_DEF), Undef);
12970 BuildMI(mainMBB, DL, TII->get(TargetOpcode::INSERT_SUBREG), SrcReg32)
12973 .addImm(X86::sub_8bit);
12974 BuildMI(mainMBB, DL, TII->get(TargetOpcode::INSERT_SUBREG), AccReg32)
12977 .addImm(X86::sub_8bit);
12979 BuildMI(mainMBB, DL, TII->get(CMOVOpc), t2)
12983 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), t1)
12984 .addReg(t2, 0, X86::sub_8bit);
12987 // Use pseudo select and lower them.
12988 assert((VT == MVT::i8 || VT == MVT::i16 || VT == MVT::i32) &&
12989 "Invalid atomic-load-op transformation!");
12990 unsigned SelOpc = getPseudoCMOVOpc(VT);
12991 X86::CondCode CC = X86::getCondFromCMovOpc(CMOVOpc);
12992 assert(CC != X86::COND_INVALID && "Invalid atomic-load-op transformation!");
12993 MIB = BuildMI(mainMBB, DL, TII->get(SelOpc), t1)
12994 .addReg(SrcReg).addReg(AccReg)
12996 mainMBB = EmitLoweredSelect(MIB, mainMBB);
13002 // Copy AccPhyReg back from virtual register.
13003 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), AccPhyReg)
13006 MIB = BuildMI(mainMBB, DL, TII->get(LCMPXCHGOpc));
13007 for (unsigned i = 0; i < X86::AddrNumOperands; ++i)
13008 MIB.addOperand(MI->getOperand(MemOpndSlot + i));
13010 MIB.setMemRefs(MMOBegin, MMOEnd);
13012 BuildMI(mainMBB, DL, TII->get(X86::JNE_4)).addMBB(origMainMBB);
13014 mainMBB->addSuccessor(origMainMBB);
13015 mainMBB->addSuccessor(sinkMBB);
13018 sinkMBB->addLiveIn(AccPhyReg);
13020 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
13021 TII->get(TargetOpcode::COPY), DstReg)
13022 .addReg(AccPhyReg);
13024 MI->eraseFromParent();
13028 // EmitAtomicLoadArith6432 - emit the code sequence for pseudo atomic
13029 // instructions. They will be translated into a spin-loop or compare-exchange
13033 // dst = atomic-fetch-op MI.addr, MI.val
13039 // EAX = LOAD [MI.addr + 0]
13040 // EDX = LOAD [MI.addr + 4]
13042 // EBX = OP MI.val.lo, EAX
13043 // ECX = OP MI.val.hi, EDX
13044 // LCMPXCHG8B [MI.addr], [ECX:EBX & EDX:EAX are implicitly used and EDX:EAX is implicitly defined]
13049 MachineBasicBlock *
13050 X86TargetLowering::EmitAtomicLoadArith6432(MachineInstr *MI,
13051 MachineBasicBlock *MBB) const {
13052 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
13053 DebugLoc DL = MI->getDebugLoc();
13055 MachineFunction *MF = MBB->getParent();
13056 MachineRegisterInfo &MRI = MF->getRegInfo();
13058 const BasicBlock *BB = MBB->getBasicBlock();
13059 MachineFunction::iterator I = MBB;
13062 assert(MI->getNumOperands() <= X86::AddrNumOperands + 4 &&
13063 "Unexpected number of operands");
13065 assert(MI->hasOneMemOperand() &&
13066 "Expected atomic-load-op32 to have one memoperand");
13068 // Memory Reference
13069 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
13070 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
13072 unsigned DstLoReg, DstHiReg;
13073 unsigned SrcLoReg, SrcHiReg;
13074 unsigned MemOpndSlot;
13076 unsigned CurOp = 0;
13078 DstLoReg = MI->getOperand(CurOp++).getReg();
13079 DstHiReg = MI->getOperand(CurOp++).getReg();
13080 MemOpndSlot = CurOp;
13081 CurOp += X86::AddrNumOperands;
13082 SrcLoReg = MI->getOperand(CurOp++).getReg();
13083 SrcHiReg = MI->getOperand(CurOp++).getReg();
13085 const TargetRegisterClass *RC = &X86::GR32RegClass;
13086 const TargetRegisterClass *RC8 = &X86::GR8RegClass;
13088 unsigned LCMPXCHGOpc = X86::LCMPXCHG8B;
13089 unsigned LOADOpc = X86::MOV32rm;
13091 // For the atomic load-arith operator, we generate
13094 // EAX = LOAD [MI.addr + 0]
13095 // EDX = LOAD [MI.addr + 4]
13097 // EBX = OP MI.vallo, EAX
13098 // ECX = OP MI.valhi, EDX
13099 // LCMPXCHG8B [MI.addr], [ECX:EBX & EDX:EAX are implicitly used and EDX:EAX is implicitly defined]
13103 MachineBasicBlock *thisMBB = MBB;
13104 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
13105 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
13106 MF->insert(I, mainMBB);
13107 MF->insert(I, sinkMBB);
13109 MachineInstrBuilder MIB;
13111 // Transfer the remainder of BB and its successor edges to sinkMBB.
13112 sinkMBB->splice(sinkMBB->begin(), MBB,
13113 llvm::next(MachineBasicBlock::iterator(MI)), MBB->end());
13114 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
13118 MIB = BuildMI(thisMBB, DL, TII->get(LOADOpc), X86::EAX);
13119 for (unsigned i = 0; i < X86::AddrNumOperands; ++i)
13120 MIB.addOperand(MI->getOperand(MemOpndSlot + i));
13121 MIB.setMemRefs(MMOBegin, MMOEnd);
13123 MIB = BuildMI(thisMBB, DL, TII->get(LOADOpc), X86::EDX);
13124 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
13125 if (i == X86::AddrDisp)
13126 MIB.addDisp(MI->getOperand(MemOpndSlot + i), 4); // 4 == sizeof(i32)
13128 MIB.addOperand(MI->getOperand(MemOpndSlot + i));
13130 MIB.setMemRefs(MMOBegin, MMOEnd);
13132 thisMBB->addSuccessor(mainMBB);
13135 MachineBasicBlock *origMainMBB = mainMBB;
13136 mainMBB->addLiveIn(X86::EAX);
13137 mainMBB->addLiveIn(X86::EDX);
13139 // Copy EDX:EAX as they are used more than once.
13140 unsigned LoReg = MRI.createVirtualRegister(RC);
13141 unsigned HiReg = MRI.createVirtualRegister(RC);
13142 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), LoReg).addReg(X86::EAX);
13143 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), HiReg).addReg(X86::EDX);
13145 unsigned t1L = MRI.createVirtualRegister(RC);
13146 unsigned t1H = MRI.createVirtualRegister(RC);
13148 unsigned Opc = MI->getOpcode();
13151 llvm_unreachable("Unhandled atomic-load-op6432 opcode!");
13152 case X86::ATOMAND6432:
13153 case X86::ATOMOR6432:
13154 case X86::ATOMXOR6432:
13155 case X86::ATOMADD6432:
13156 case X86::ATOMSUB6432: {
13158 unsigned LoOpc = getNonAtomic6432Opcode(Opc, HiOpc);
13159 BuildMI(mainMBB, DL, TII->get(LoOpc), t1L).addReg(LoReg).addReg(SrcLoReg);
13160 BuildMI(mainMBB, DL, TII->get(HiOpc), t1H).addReg(HiReg).addReg(SrcHiReg);
13163 case X86::ATOMNAND6432: {
13164 unsigned HiOpc, NOTOpc;
13165 unsigned LoOpc = getNonAtomic6432OpcodeWithExtraOpc(Opc, HiOpc, NOTOpc);
13166 unsigned t2L = MRI.createVirtualRegister(RC);
13167 unsigned t2H = MRI.createVirtualRegister(RC);
13168 BuildMI(mainMBB, DL, TII->get(LoOpc), t2L).addReg(SrcLoReg).addReg(LoReg);
13169 BuildMI(mainMBB, DL, TII->get(HiOpc), t2H).addReg(SrcHiReg).addReg(HiReg);
13170 BuildMI(mainMBB, DL, TII->get(NOTOpc), t1L).addReg(t2L);
13171 BuildMI(mainMBB, DL, TII->get(NOTOpc), t1H).addReg(t2H);
13174 case X86::ATOMMAX6432:
13175 case X86::ATOMMIN6432:
13176 case X86::ATOMUMAX6432:
13177 case X86::ATOMUMIN6432: {
13179 unsigned LoOpc = getNonAtomic6432Opcode(Opc, HiOpc);
13180 unsigned cL = MRI.createVirtualRegister(RC8);
13181 unsigned cH = MRI.createVirtualRegister(RC8);
13182 unsigned cL32 = MRI.createVirtualRegister(RC);
13183 unsigned cH32 = MRI.createVirtualRegister(RC);
13184 unsigned cc = MRI.createVirtualRegister(RC);
13185 // cl := cmp src_lo, lo
13186 BuildMI(mainMBB, DL, TII->get(X86::CMP32rr))
13187 .addReg(SrcLoReg).addReg(LoReg);
13188 BuildMI(mainMBB, DL, TII->get(LoOpc), cL);
13189 BuildMI(mainMBB, DL, TII->get(X86::MOVZX32rr8), cL32).addReg(cL);
13190 // ch := cmp src_hi, hi
13191 BuildMI(mainMBB, DL, TII->get(X86::CMP32rr))
13192 .addReg(SrcHiReg).addReg(HiReg);
13193 BuildMI(mainMBB, DL, TII->get(HiOpc), cH);
13194 BuildMI(mainMBB, DL, TII->get(X86::MOVZX32rr8), cH32).addReg(cH);
13195 // cc := if (src_hi == hi) ? cl : ch;
13196 if (Subtarget->hasCMov()) {
13197 BuildMI(mainMBB, DL, TII->get(X86::CMOVE32rr), cc)
13198 .addReg(cH32).addReg(cL32);
13200 MIB = BuildMI(mainMBB, DL, TII->get(X86::CMOV_GR32), cc)
13201 .addReg(cH32).addReg(cL32)
13202 .addImm(X86::COND_E);
13203 mainMBB = EmitLoweredSelect(MIB, mainMBB);
13205 BuildMI(mainMBB, DL, TII->get(X86::TEST32rr)).addReg(cc).addReg(cc);
13206 if (Subtarget->hasCMov()) {
13207 BuildMI(mainMBB, DL, TII->get(X86::CMOVNE32rr), t1L)
13208 .addReg(SrcLoReg).addReg(LoReg);
13209 BuildMI(mainMBB, DL, TII->get(X86::CMOVNE32rr), t1H)
13210 .addReg(SrcHiReg).addReg(HiReg);
13212 MIB = BuildMI(mainMBB, DL, TII->get(X86::CMOV_GR32), t1L)
13213 .addReg(SrcLoReg).addReg(LoReg)
13214 .addImm(X86::COND_NE);
13215 mainMBB = EmitLoweredSelect(MIB, mainMBB);
13216 MIB = BuildMI(mainMBB, DL, TII->get(X86::CMOV_GR32), t1H)
13217 .addReg(SrcHiReg).addReg(HiReg)
13218 .addImm(X86::COND_NE);
13219 mainMBB = EmitLoweredSelect(MIB, mainMBB);
13223 case X86::ATOMSWAP6432: {
13225 unsigned LoOpc = getNonAtomic6432Opcode(Opc, HiOpc);
13226 BuildMI(mainMBB, DL, TII->get(LoOpc), t1L).addReg(SrcLoReg);
13227 BuildMI(mainMBB, DL, TII->get(HiOpc), t1H).addReg(SrcHiReg);
13232 // Copy EDX:EAX back from HiReg:LoReg
13233 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), X86::EAX).addReg(LoReg);
13234 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), X86::EDX).addReg(HiReg);
13235 // Copy ECX:EBX from t1H:t1L
13236 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), X86::EBX).addReg(t1L);
13237 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), X86::ECX).addReg(t1H);
13239 MIB = BuildMI(mainMBB, DL, TII->get(LCMPXCHGOpc));
13240 for (unsigned i = 0; i < X86::AddrNumOperands; ++i)
13241 MIB.addOperand(MI->getOperand(MemOpndSlot + i));
13242 MIB.setMemRefs(MMOBegin, MMOEnd);
13244 BuildMI(mainMBB, DL, TII->get(X86::JNE_4)).addMBB(origMainMBB);
13246 mainMBB->addSuccessor(origMainMBB);
13247 mainMBB->addSuccessor(sinkMBB);
13250 sinkMBB->addLiveIn(X86::EAX);
13251 sinkMBB->addLiveIn(X86::EDX);
13253 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
13254 TII->get(TargetOpcode::COPY), DstLoReg)
13256 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
13257 TII->get(TargetOpcode::COPY), DstHiReg)
13260 MI->eraseFromParent();
13264 // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
13265 // or XMM0_V32I8 in AVX all of this code can be replaced with that
13266 // in the .td file.
13267 static MachineBasicBlock *EmitPCMPSTRM(MachineInstr *MI, MachineBasicBlock *BB,
13268 const TargetInstrInfo *TII) {
13270 switch (MI->getOpcode()) {
13271 default: llvm_unreachable("illegal opcode!");
13272 case X86::PCMPISTRM128REG: Opc = X86::PCMPISTRM128rr; break;
13273 case X86::VPCMPISTRM128REG: Opc = X86::VPCMPISTRM128rr; break;
13274 case X86::PCMPISTRM128MEM: Opc = X86::PCMPISTRM128rm; break;
13275 case X86::VPCMPISTRM128MEM: Opc = X86::VPCMPISTRM128rm; break;
13276 case X86::PCMPESTRM128REG: Opc = X86::PCMPESTRM128rr; break;
13277 case X86::VPCMPESTRM128REG: Opc = X86::VPCMPESTRM128rr; break;
13278 case X86::PCMPESTRM128MEM: Opc = X86::PCMPESTRM128rm; break;
13279 case X86::VPCMPESTRM128MEM: Opc = X86::VPCMPESTRM128rm; break;
13282 DebugLoc dl = MI->getDebugLoc();
13283 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
13285 unsigned NumArgs = MI->getNumOperands();
13286 for (unsigned i = 1; i < NumArgs; ++i) {
13287 MachineOperand &Op = MI->getOperand(i);
13288 if (!(Op.isReg() && Op.isImplicit()))
13289 MIB.addOperand(Op);
13291 if (MI->hasOneMemOperand())
13292 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
13294 BuildMI(*BB, MI, dl,
13295 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
13296 .addReg(X86::XMM0);
13298 MI->eraseFromParent();
13302 // FIXME: Custom handling because TableGen doesn't support multiple implicit
13303 // defs in an instruction pattern
13304 static MachineBasicBlock *EmitPCMPSTRI(MachineInstr *MI, MachineBasicBlock *BB,
13305 const TargetInstrInfo *TII) {
13307 switch (MI->getOpcode()) {
13308 default: llvm_unreachable("illegal opcode!");
13309 case X86::PCMPISTRIREG: Opc = X86::PCMPISTRIrr; break;
13310 case X86::VPCMPISTRIREG: Opc = X86::VPCMPISTRIrr; break;
13311 case X86::PCMPISTRIMEM: Opc = X86::PCMPISTRIrm; break;
13312 case X86::VPCMPISTRIMEM: Opc = X86::VPCMPISTRIrm; break;
13313 case X86::PCMPESTRIREG: Opc = X86::PCMPESTRIrr; break;
13314 case X86::VPCMPESTRIREG: Opc = X86::VPCMPESTRIrr; break;
13315 case X86::PCMPESTRIMEM: Opc = X86::PCMPESTRIrm; break;
13316 case X86::VPCMPESTRIMEM: Opc = X86::VPCMPESTRIrm; break;
13319 DebugLoc dl = MI->getDebugLoc();
13320 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
13322 unsigned NumArgs = MI->getNumOperands(); // remove the results
13323 for (unsigned i = 1; i < NumArgs; ++i) {
13324 MachineOperand &Op = MI->getOperand(i);
13325 if (!(Op.isReg() && Op.isImplicit()))
13326 MIB.addOperand(Op);
13328 if (MI->hasOneMemOperand())
13329 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
13331 BuildMI(*BB, MI, dl,
13332 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
13335 MI->eraseFromParent();
13339 static MachineBasicBlock * EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB,
13340 const TargetInstrInfo *TII,
13341 const X86Subtarget* Subtarget) {
13342 DebugLoc dl = MI->getDebugLoc();
13344 // Address into RAX/EAX, other two args into ECX, EDX.
13345 unsigned MemOpc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
13346 unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
13347 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg);
13348 for (int i = 0; i < X86::AddrNumOperands; ++i)
13349 MIB.addOperand(MI->getOperand(i));
13351 unsigned ValOps = X86::AddrNumOperands;
13352 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
13353 .addReg(MI->getOperand(ValOps).getReg());
13354 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EDX)
13355 .addReg(MI->getOperand(ValOps+1).getReg());
13357 // The instruction doesn't actually take any operands though.
13358 BuildMI(*BB, MI, dl, TII->get(X86::MONITORrrr));
13360 MI->eraseFromParent(); // The pseudo is gone now.
13364 MachineBasicBlock *
13365 X86TargetLowering::EmitVAARG64WithCustomInserter(
13367 MachineBasicBlock *MBB) const {
13368 // Emit va_arg instruction on X86-64.
13370 // Operands to this pseudo-instruction:
13371 // 0 ) Output : destination address (reg)
13372 // 1-5) Input : va_list address (addr, i64mem)
13373 // 6 ) ArgSize : Size (in bytes) of vararg type
13374 // 7 ) ArgMode : 0=overflow only, 1=use gp_offset, 2=use fp_offset
13375 // 8 ) Align : Alignment of type
13376 // 9 ) EFLAGS (implicit-def)
13378 assert(MI->getNumOperands() == 10 && "VAARG_64 should have 10 operands!");
13379 assert(X86::AddrNumOperands == 5 && "VAARG_64 assumes 5 address operands");
13381 unsigned DestReg = MI->getOperand(0).getReg();
13382 MachineOperand &Base = MI->getOperand(1);
13383 MachineOperand &Scale = MI->getOperand(2);
13384 MachineOperand &Index = MI->getOperand(3);
13385 MachineOperand &Disp = MI->getOperand(4);
13386 MachineOperand &Segment = MI->getOperand(5);
13387 unsigned ArgSize = MI->getOperand(6).getImm();
13388 unsigned ArgMode = MI->getOperand(7).getImm();
13389 unsigned Align = MI->getOperand(8).getImm();
13391 // Memory Reference
13392 assert(MI->hasOneMemOperand() && "Expected VAARG_64 to have one memoperand");
13393 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
13394 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
13396 // Machine Information
13397 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
13398 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
13399 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64);
13400 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32);
13401 DebugLoc DL = MI->getDebugLoc();
13403 // struct va_list {
13406 // i64 overflow_area (address)
13407 // i64 reg_save_area (address)
13409 // sizeof(va_list) = 24
13410 // alignment(va_list) = 8
13412 unsigned TotalNumIntRegs = 6;
13413 unsigned TotalNumXMMRegs = 8;
13414 bool UseGPOffset = (ArgMode == 1);
13415 bool UseFPOffset = (ArgMode == 2);
13416 unsigned MaxOffset = TotalNumIntRegs * 8 +
13417 (UseFPOffset ? TotalNumXMMRegs * 16 : 0);
13419 /* Align ArgSize to a multiple of 8 */
13420 unsigned ArgSizeA8 = (ArgSize + 7) & ~7;
13421 bool NeedsAlign = (Align > 8);
13423 MachineBasicBlock *thisMBB = MBB;
13424 MachineBasicBlock *overflowMBB;
13425 MachineBasicBlock *offsetMBB;
13426 MachineBasicBlock *endMBB;
13428 unsigned OffsetDestReg = 0; // Argument address computed by offsetMBB
13429 unsigned OverflowDestReg = 0; // Argument address computed by overflowMBB
13430 unsigned OffsetReg = 0;
13432 if (!UseGPOffset && !UseFPOffset) {
13433 // If we only pull from the overflow region, we don't create a branch.
13434 // We don't need to alter control flow.
13435 OffsetDestReg = 0; // unused
13436 OverflowDestReg = DestReg;
13439 overflowMBB = thisMBB;
13442 // First emit code to check if gp_offset (or fp_offset) is below the bound.
13443 // If so, pull the argument from reg_save_area. (branch to offsetMBB)
13444 // If not, pull from overflow_area. (branch to overflowMBB)
13449 // offsetMBB overflowMBB
13454 // Registers for the PHI in endMBB
13455 OffsetDestReg = MRI.createVirtualRegister(AddrRegClass);
13456 OverflowDestReg = MRI.createVirtualRegister(AddrRegClass);
13458 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
13459 MachineFunction *MF = MBB->getParent();
13460 overflowMBB = MF->CreateMachineBasicBlock(LLVM_BB);
13461 offsetMBB = MF->CreateMachineBasicBlock(LLVM_BB);
13462 endMBB = MF->CreateMachineBasicBlock(LLVM_BB);
13464 MachineFunction::iterator MBBIter = MBB;
13467 // Insert the new basic blocks
13468 MF->insert(MBBIter, offsetMBB);
13469 MF->insert(MBBIter, overflowMBB);
13470 MF->insert(MBBIter, endMBB);
13472 // Transfer the remainder of MBB and its successor edges to endMBB.
13473 endMBB->splice(endMBB->begin(), thisMBB,
13474 llvm::next(MachineBasicBlock::iterator(MI)),
13476 endMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
13478 // Make offsetMBB and overflowMBB successors of thisMBB
13479 thisMBB->addSuccessor(offsetMBB);
13480 thisMBB->addSuccessor(overflowMBB);
13482 // endMBB is a successor of both offsetMBB and overflowMBB
13483 offsetMBB->addSuccessor(endMBB);
13484 overflowMBB->addSuccessor(endMBB);
13486 // Load the offset value into a register
13487 OffsetReg = MRI.createVirtualRegister(OffsetRegClass);
13488 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg)
13492 .addDisp(Disp, UseFPOffset ? 4 : 0)
13493 .addOperand(Segment)
13494 .setMemRefs(MMOBegin, MMOEnd);
13496 // Check if there is enough room left to pull this argument.
13497 BuildMI(thisMBB, DL, TII->get(X86::CMP32ri))
13499 .addImm(MaxOffset + 8 - ArgSizeA8);
13501 // Branch to "overflowMBB" if offset >= max
13502 // Fall through to "offsetMBB" otherwise
13503 BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE)))
13504 .addMBB(overflowMBB);
13507 // In offsetMBB, emit code to use the reg_save_area.
13509 assert(OffsetReg != 0);
13511 // Read the reg_save_area address.
13512 unsigned RegSaveReg = MRI.createVirtualRegister(AddrRegClass);
13513 BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg)
13518 .addOperand(Segment)
13519 .setMemRefs(MMOBegin, MMOEnd);
13521 // Zero-extend the offset
13522 unsigned OffsetReg64 = MRI.createVirtualRegister(AddrRegClass);
13523 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64)
13526 .addImm(X86::sub_32bit);
13528 // Add the offset to the reg_save_area to get the final address.
13529 BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg)
13530 .addReg(OffsetReg64)
13531 .addReg(RegSaveReg);
13533 // Compute the offset for the next argument
13534 unsigned NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass);
13535 BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg)
13537 .addImm(UseFPOffset ? 16 : 8);
13539 // Store it back into the va_list.
13540 BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr))
13544 .addDisp(Disp, UseFPOffset ? 4 : 0)
13545 .addOperand(Segment)
13546 .addReg(NextOffsetReg)
13547 .setMemRefs(MMOBegin, MMOEnd);
13550 BuildMI(offsetMBB, DL, TII->get(X86::JMP_4))
13555 // Emit code to use overflow area
13558 // Load the overflow_area address into a register.
13559 unsigned OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass);
13560 BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg)
13565 .addOperand(Segment)
13566 .setMemRefs(MMOBegin, MMOEnd);
13568 // If we need to align it, do so. Otherwise, just copy the address
13569 // to OverflowDestReg.
13571 // Align the overflow address
13572 assert((Align & (Align-1)) == 0 && "Alignment must be a power of 2");
13573 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass);
13575 // aligned_addr = (addr + (align-1)) & ~(align-1)
13576 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg)
13577 .addReg(OverflowAddrReg)
13580 BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg)
13582 .addImm(~(uint64_t)(Align-1));
13584 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg)
13585 .addReg(OverflowAddrReg);
13588 // Compute the next overflow address after this argument.
13589 // (the overflow address should be kept 8-byte aligned)
13590 unsigned NextAddrReg = MRI.createVirtualRegister(AddrRegClass);
13591 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg)
13592 .addReg(OverflowDestReg)
13593 .addImm(ArgSizeA8);
13595 // Store the new overflow address.
13596 BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr))
13601 .addOperand(Segment)
13602 .addReg(NextAddrReg)
13603 .setMemRefs(MMOBegin, MMOEnd);
13605 // If we branched, emit the PHI to the front of endMBB.
13607 BuildMI(*endMBB, endMBB->begin(), DL,
13608 TII->get(X86::PHI), DestReg)
13609 .addReg(OffsetDestReg).addMBB(offsetMBB)
13610 .addReg(OverflowDestReg).addMBB(overflowMBB);
13613 // Erase the pseudo instruction
13614 MI->eraseFromParent();
13619 MachineBasicBlock *
13620 X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
13622 MachineBasicBlock *MBB) const {
13623 // Emit code to save XMM registers to the stack. The ABI says that the
13624 // number of registers to save is given in %al, so it's theoretically
13625 // possible to do an indirect jump trick to avoid saving all of them,
13626 // however this code takes a simpler approach and just executes all
13627 // of the stores if %al is non-zero. It's less code, and it's probably
13628 // easier on the hardware branch predictor, and stores aren't all that
13629 // expensive anyway.
13631 // Create the new basic blocks. One block contains all the XMM stores,
13632 // and one block is the final destination regardless of whether any
13633 // stores were performed.
13634 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
13635 MachineFunction *F = MBB->getParent();
13636 MachineFunction::iterator MBBIter = MBB;
13638 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB);
13639 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB);
13640 F->insert(MBBIter, XMMSaveMBB);
13641 F->insert(MBBIter, EndMBB);
13643 // Transfer the remainder of MBB and its successor edges to EndMBB.
13644 EndMBB->splice(EndMBB->begin(), MBB,
13645 llvm::next(MachineBasicBlock::iterator(MI)),
13647 EndMBB->transferSuccessorsAndUpdatePHIs(MBB);
13649 // The original block will now fall through to the XMM save block.
13650 MBB->addSuccessor(XMMSaveMBB);
13651 // The XMMSaveMBB will fall through to the end block.
13652 XMMSaveMBB->addSuccessor(EndMBB);
13654 // Now add the instructions.
13655 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
13656 DebugLoc DL = MI->getDebugLoc();
13658 unsigned CountReg = MI->getOperand(0).getReg();
13659 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm();
13660 int64_t VarArgsFPOffset = MI->getOperand(2).getImm();
13662 if (!Subtarget->isTargetWin64()) {
13663 // If %al is 0, branch around the XMM save block.
13664 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
13665 BuildMI(MBB, DL, TII->get(X86::JE_4)).addMBB(EndMBB);
13666 MBB->addSuccessor(EndMBB);
13669 unsigned MOVOpc = Subtarget->hasFp256() ? X86::VMOVAPSmr : X86::MOVAPSmr;
13670 // In the XMM save block, save all the XMM argument registers.
13671 for (int i = 3, e = MI->getNumOperands(); i != e; ++i) {
13672 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
13673 MachineMemOperand *MMO =
13674 F->getMachineMemOperand(
13675 MachinePointerInfo::getFixedStack(RegSaveFrameIndex, Offset),
13676 MachineMemOperand::MOStore,
13677 /*Size=*/16, /*Align=*/16);
13678 BuildMI(XMMSaveMBB, DL, TII->get(MOVOpc))
13679 .addFrameIndex(RegSaveFrameIndex)
13680 .addImm(/*Scale=*/1)
13681 .addReg(/*IndexReg=*/0)
13682 .addImm(/*Disp=*/Offset)
13683 .addReg(/*Segment=*/0)
13684 .addReg(MI->getOperand(i).getReg())
13685 .addMemOperand(MMO);
13688 MI->eraseFromParent(); // The pseudo instruction is gone now.
13693 // The EFLAGS operand of SelectItr might be missing a kill marker
13694 // because there were multiple uses of EFLAGS, and ISel didn't know
13695 // which to mark. Figure out whether SelectItr should have had a
13696 // kill marker, and set it if it should. Returns the correct kill
13698 static bool checkAndUpdateEFLAGSKill(MachineBasicBlock::iterator SelectItr,
13699 MachineBasicBlock* BB,
13700 const TargetRegisterInfo* TRI) {
13701 // Scan forward through BB for a use/def of EFLAGS.
13702 MachineBasicBlock::iterator miI(llvm::next(SelectItr));
13703 for (MachineBasicBlock::iterator miE = BB->end(); miI != miE; ++miI) {
13704 const MachineInstr& mi = *miI;
13705 if (mi.readsRegister(X86::EFLAGS))
13707 if (mi.definesRegister(X86::EFLAGS))
13708 break; // Should have kill-flag - update below.
13711 // If we hit the end of the block, check whether EFLAGS is live into a
13713 if (miI == BB->end()) {
13714 for (MachineBasicBlock::succ_iterator sItr = BB->succ_begin(),
13715 sEnd = BB->succ_end();
13716 sItr != sEnd; ++sItr) {
13717 MachineBasicBlock* succ = *sItr;
13718 if (succ->isLiveIn(X86::EFLAGS))
13723 // We found a def, or hit the end of the basic block and EFLAGS wasn't live
13724 // out. SelectMI should have a kill flag on EFLAGS.
13725 SelectItr->addRegisterKilled(X86::EFLAGS, TRI);
13729 MachineBasicBlock *
13730 X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
13731 MachineBasicBlock *BB) const {
13732 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
13733 DebugLoc DL = MI->getDebugLoc();
13735 // To "insert" a SELECT_CC instruction, we actually have to insert the
13736 // diamond control-flow pattern. The incoming instruction knows the
13737 // destination vreg to set, the condition code register to branch on, the
13738 // true/false values to select between, and a branch opcode to use.
13739 const BasicBlock *LLVM_BB = BB->getBasicBlock();
13740 MachineFunction::iterator It = BB;
13746 // cmpTY ccX, r1, r2
13748 // fallthrough --> copy0MBB
13749 MachineBasicBlock *thisMBB = BB;
13750 MachineFunction *F = BB->getParent();
13751 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
13752 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
13753 F->insert(It, copy0MBB);
13754 F->insert(It, sinkMBB);
13756 // If the EFLAGS register isn't dead in the terminator, then claim that it's
13757 // live into the sink and copy blocks.
13758 const TargetRegisterInfo* TRI = getTargetMachine().getRegisterInfo();
13759 if (!MI->killsRegister(X86::EFLAGS) &&
13760 !checkAndUpdateEFLAGSKill(MI, BB, TRI)) {
13761 copy0MBB->addLiveIn(X86::EFLAGS);
13762 sinkMBB->addLiveIn(X86::EFLAGS);
13765 // Transfer the remainder of BB and its successor edges to sinkMBB.
13766 sinkMBB->splice(sinkMBB->begin(), BB,
13767 llvm::next(MachineBasicBlock::iterator(MI)),
13769 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
13771 // Add the true and fallthrough blocks as its successors.
13772 BB->addSuccessor(copy0MBB);
13773 BB->addSuccessor(sinkMBB);
13775 // Create the conditional branch instruction.
13777 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
13778 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
13781 // %FalseValue = ...
13782 // # fallthrough to sinkMBB
13783 copy0MBB->addSuccessor(sinkMBB);
13786 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
13788 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
13789 TII->get(X86::PHI), MI->getOperand(0).getReg())
13790 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
13791 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
13793 MI->eraseFromParent(); // The pseudo instruction is gone now.
13797 MachineBasicBlock *
13798 X86TargetLowering::EmitLoweredSegAlloca(MachineInstr *MI, MachineBasicBlock *BB,
13799 bool Is64Bit) const {
13800 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
13801 DebugLoc DL = MI->getDebugLoc();
13802 MachineFunction *MF = BB->getParent();
13803 const BasicBlock *LLVM_BB = BB->getBasicBlock();
13805 assert(getTargetMachine().Options.EnableSegmentedStacks);
13807 unsigned TlsReg = Is64Bit ? X86::FS : X86::GS;
13808 unsigned TlsOffset = Is64Bit ? 0x70 : 0x30;
13811 // ... [Till the alloca]
13812 // If stacklet is not large enough, jump to mallocMBB
13815 // Allocate by subtracting from RSP
13816 // Jump to continueMBB
13819 // Allocate by call to runtime
13823 // [rest of original BB]
13826 MachineBasicBlock *mallocMBB = MF->CreateMachineBasicBlock(LLVM_BB);
13827 MachineBasicBlock *bumpMBB = MF->CreateMachineBasicBlock(LLVM_BB);
13828 MachineBasicBlock *continueMBB = MF->CreateMachineBasicBlock(LLVM_BB);
13830 MachineRegisterInfo &MRI = MF->getRegInfo();
13831 const TargetRegisterClass *AddrRegClass =
13832 getRegClassFor(Is64Bit ? MVT::i64:MVT::i32);
13834 unsigned mallocPtrVReg = MRI.createVirtualRegister(AddrRegClass),
13835 bumpSPPtrVReg = MRI.createVirtualRegister(AddrRegClass),
13836 tmpSPVReg = MRI.createVirtualRegister(AddrRegClass),
13837 SPLimitVReg = MRI.createVirtualRegister(AddrRegClass),
13838 sizeVReg = MI->getOperand(1).getReg(),
13839 physSPReg = Is64Bit ? X86::RSP : X86::ESP;
13841 MachineFunction::iterator MBBIter = BB;
13844 MF->insert(MBBIter, bumpMBB);
13845 MF->insert(MBBIter, mallocMBB);
13846 MF->insert(MBBIter, continueMBB);
13848 continueMBB->splice(continueMBB->begin(), BB, llvm::next
13849 (MachineBasicBlock::iterator(MI)), BB->end());
13850 continueMBB->transferSuccessorsAndUpdatePHIs(BB);
13852 // Add code to the main basic block to check if the stack limit has been hit,
13853 // and if so, jump to mallocMBB otherwise to bumpMBB.
13854 BuildMI(BB, DL, TII->get(TargetOpcode::COPY), tmpSPVReg).addReg(physSPReg);
13855 BuildMI(BB, DL, TII->get(Is64Bit ? X86::SUB64rr:X86::SUB32rr), SPLimitVReg)
13856 .addReg(tmpSPVReg).addReg(sizeVReg);
13857 BuildMI(BB, DL, TII->get(Is64Bit ? X86::CMP64mr:X86::CMP32mr))
13858 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg)
13859 .addReg(SPLimitVReg);
13860 BuildMI(BB, DL, TII->get(X86::JG_4)).addMBB(mallocMBB);
13862 // bumpMBB simply decreases the stack pointer, since we know the current
13863 // stacklet has enough space.
13864 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), physSPReg)
13865 .addReg(SPLimitVReg);
13866 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), bumpSPPtrVReg)
13867 .addReg(SPLimitVReg);
13868 BuildMI(bumpMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
13870 // Calls into a routine in libgcc to allocate more space from the heap.
13871 const uint32_t *RegMask =
13872 getTargetMachine().getRegisterInfo()->getCallPreservedMask(CallingConv::C);
13874 BuildMI(mallocMBB, DL, TII->get(X86::MOV64rr), X86::RDI)
13876 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
13877 .addExternalSymbol("__morestack_allocate_stack_space")
13878 .addRegMask(RegMask)
13879 .addReg(X86::RDI, RegState::Implicit)
13880 .addReg(X86::RAX, RegState::ImplicitDefine);
13882 BuildMI(mallocMBB, DL, TII->get(X86::SUB32ri), physSPReg).addReg(physSPReg)
13884 BuildMI(mallocMBB, DL, TII->get(X86::PUSH32r)).addReg(sizeVReg);
13885 BuildMI(mallocMBB, DL, TII->get(X86::CALLpcrel32))
13886 .addExternalSymbol("__morestack_allocate_stack_space")
13887 .addRegMask(RegMask)
13888 .addReg(X86::EAX, RegState::ImplicitDefine);
13892 BuildMI(mallocMBB, DL, TII->get(X86::ADD32ri), physSPReg).addReg(physSPReg)
13895 BuildMI(mallocMBB, DL, TII->get(TargetOpcode::COPY), mallocPtrVReg)
13896 .addReg(Is64Bit ? X86::RAX : X86::EAX);
13897 BuildMI(mallocMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
13899 // Set up the CFG correctly.
13900 BB->addSuccessor(bumpMBB);
13901 BB->addSuccessor(mallocMBB);
13902 mallocMBB->addSuccessor(continueMBB);
13903 bumpMBB->addSuccessor(continueMBB);
13905 // Take care of the PHI nodes.
13906 BuildMI(*continueMBB, continueMBB->begin(), DL, TII->get(X86::PHI),
13907 MI->getOperand(0).getReg())
13908 .addReg(mallocPtrVReg).addMBB(mallocMBB)
13909 .addReg(bumpSPPtrVReg).addMBB(bumpMBB);
13911 // Delete the original pseudo instruction.
13912 MI->eraseFromParent();
13915 return continueMBB;
13918 MachineBasicBlock *
13919 X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI,
13920 MachineBasicBlock *BB) const {
13921 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
13922 DebugLoc DL = MI->getDebugLoc();
13924 assert(!Subtarget->isTargetEnvMacho());
13926 // The lowering is pretty easy: we're just emitting the call to _alloca. The
13927 // non-trivial part is impdef of ESP.
13929 if (Subtarget->isTargetWin64()) {
13930 if (Subtarget->isTargetCygMing()) {
13931 // ___chkstk(Mingw64):
13932 // Clobbers R10, R11, RAX and EFLAGS.
13934 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
13935 .addExternalSymbol("___chkstk")
13936 .addReg(X86::RAX, RegState::Implicit)
13937 .addReg(X86::RSP, RegState::Implicit)
13938 .addReg(X86::RAX, RegState::Define | RegState::Implicit)
13939 .addReg(X86::RSP, RegState::Define | RegState::Implicit)
13940 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
13942 // __chkstk(MSVCRT): does not update stack pointer.
13943 // Clobbers R10, R11 and EFLAGS.
13944 // FIXME: RAX(allocated size) might be reused and not killed.
13945 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
13946 .addExternalSymbol("__chkstk")
13947 .addReg(X86::RAX, RegState::Implicit)
13948 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
13949 // RAX has the offset to subtracted from RSP.
13950 BuildMI(*BB, MI, DL, TII->get(X86::SUB64rr), X86::RSP)
13955 const char *StackProbeSymbol =
13956 Subtarget->isTargetWindows() ? "_chkstk" : "_alloca";
13958 BuildMI(*BB, MI, DL, TII->get(X86::CALLpcrel32))
13959 .addExternalSymbol(StackProbeSymbol)
13960 .addReg(X86::EAX, RegState::Implicit)
13961 .addReg(X86::ESP, RegState::Implicit)
13962 .addReg(X86::EAX, RegState::Define | RegState::Implicit)
13963 .addReg(X86::ESP, RegState::Define | RegState::Implicit)
13964 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
13967 MI->eraseFromParent(); // The pseudo instruction is gone now.
13971 MachineBasicBlock *
13972 X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI,
13973 MachineBasicBlock *BB) const {
13974 // This is pretty easy. We're taking the value that we received from
13975 // our load from the relocation, sticking it in either RDI (x86-64)
13976 // or EAX and doing an indirect call. The return value will then
13977 // be in the normal return register.
13978 const X86InstrInfo *TII
13979 = static_cast<const X86InstrInfo*>(getTargetMachine().getInstrInfo());
13980 DebugLoc DL = MI->getDebugLoc();
13981 MachineFunction *F = BB->getParent();
13983 assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?");
13984 assert(MI->getOperand(3).isGlobal() && "This should be a global");
13986 // Get a register mask for the lowered call.
13987 // FIXME: The 32-bit calls have non-standard calling conventions. Use a
13988 // proper register mask.
13989 const uint32_t *RegMask =
13990 getTargetMachine().getRegisterInfo()->getCallPreservedMask(CallingConv::C);
13991 if (Subtarget->is64Bit()) {
13992 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
13993 TII->get(X86::MOV64rm), X86::RDI)
13995 .addImm(0).addReg(0)
13996 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
13997 MI->getOperand(3).getTargetFlags())
13999 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m));
14000 addDirectMem(MIB, X86::RDI);
14001 MIB.addReg(X86::RAX, RegState::ImplicitDefine).addRegMask(RegMask);
14002 } else if (getTargetMachine().getRelocationModel() != Reloc::PIC_) {
14003 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
14004 TII->get(X86::MOV32rm), X86::EAX)
14006 .addImm(0).addReg(0)
14007 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
14008 MI->getOperand(3).getTargetFlags())
14010 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
14011 addDirectMem(MIB, X86::EAX);
14012 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
14014 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
14015 TII->get(X86::MOV32rm), X86::EAX)
14016 .addReg(TII->getGlobalBaseReg(F))
14017 .addImm(0).addReg(0)
14018 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
14019 MI->getOperand(3).getTargetFlags())
14021 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
14022 addDirectMem(MIB, X86::EAX);
14023 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
14026 MI->eraseFromParent(); // The pseudo instruction is gone now.
14030 MachineBasicBlock *
14031 X86TargetLowering::emitEHSjLjSetJmp(MachineInstr *MI,
14032 MachineBasicBlock *MBB) const {
14033 DebugLoc DL = MI->getDebugLoc();
14034 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
14036 MachineFunction *MF = MBB->getParent();
14037 MachineRegisterInfo &MRI = MF->getRegInfo();
14039 const BasicBlock *BB = MBB->getBasicBlock();
14040 MachineFunction::iterator I = MBB;
14043 // Memory Reference
14044 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
14045 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
14048 unsigned MemOpndSlot = 0;
14050 unsigned CurOp = 0;
14052 DstReg = MI->getOperand(CurOp++).getReg();
14053 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
14054 assert(RC->hasType(MVT::i32) && "Invalid destination!");
14055 unsigned mainDstReg = MRI.createVirtualRegister(RC);
14056 unsigned restoreDstReg = MRI.createVirtualRegister(RC);
14058 MemOpndSlot = CurOp;
14060 MVT PVT = getPointerTy();
14061 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
14062 "Invalid Pointer Size!");
14064 // For v = setjmp(buf), we generate
14067 // buf[LabelOffset] = restoreMBB
14068 // SjLjSetup restoreMBB
14074 // v = phi(main, restore)
14079 MachineBasicBlock *thisMBB = MBB;
14080 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
14081 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
14082 MachineBasicBlock *restoreMBB = MF->CreateMachineBasicBlock(BB);
14083 MF->insert(I, mainMBB);
14084 MF->insert(I, sinkMBB);
14085 MF->push_back(restoreMBB);
14087 MachineInstrBuilder MIB;
14089 // Transfer the remainder of BB and its successor edges to sinkMBB.
14090 sinkMBB->splice(sinkMBB->begin(), MBB,
14091 llvm::next(MachineBasicBlock::iterator(MI)), MBB->end());
14092 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
14095 unsigned PtrStoreOpc = 0;
14096 unsigned LabelReg = 0;
14097 const int64_t LabelOffset = 1 * PVT.getStoreSize();
14098 Reloc::Model RM = getTargetMachine().getRelocationModel();
14099 bool UseImmLabel = (getTargetMachine().getCodeModel() == CodeModel::Small) &&
14100 (RM == Reloc::Static || RM == Reloc::DynamicNoPIC);
14102 // Prepare IP either in reg or imm.
14103 if (!UseImmLabel) {
14104 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mr : X86::MOV32mr;
14105 const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
14106 LabelReg = MRI.createVirtualRegister(PtrRC);
14107 if (Subtarget->is64Bit()) {
14108 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA64r), LabelReg)
14112 .addMBB(restoreMBB)
14115 const X86InstrInfo *XII = static_cast<const X86InstrInfo*>(TII);
14116 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA32r), LabelReg)
14117 .addReg(XII->getGlobalBaseReg(MF))
14120 .addMBB(restoreMBB, Subtarget->ClassifyBlockAddressReference())
14124 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mi32 : X86::MOV32mi;
14126 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PtrStoreOpc));
14127 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
14128 if (i == X86::AddrDisp)
14129 MIB.addDisp(MI->getOperand(MemOpndSlot + i), LabelOffset);
14131 MIB.addOperand(MI->getOperand(MemOpndSlot + i));
14134 MIB.addReg(LabelReg);
14136 MIB.addMBB(restoreMBB);
14137 MIB.setMemRefs(MMOBegin, MMOEnd);
14139 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::EH_SjLj_Setup))
14140 .addMBB(restoreMBB);
14141 MIB.addRegMask(RegInfo->getNoPreservedMask());
14142 thisMBB->addSuccessor(mainMBB);
14143 thisMBB->addSuccessor(restoreMBB);
14147 BuildMI(mainMBB, DL, TII->get(X86::MOV32r0), mainDstReg);
14148 mainMBB->addSuccessor(sinkMBB);
14151 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
14152 TII->get(X86::PHI), DstReg)
14153 .addReg(mainDstReg).addMBB(mainMBB)
14154 .addReg(restoreDstReg).addMBB(restoreMBB);
14157 BuildMI(restoreMBB, DL, TII->get(X86::MOV32ri), restoreDstReg).addImm(1);
14158 BuildMI(restoreMBB, DL, TII->get(X86::JMP_4)).addMBB(sinkMBB);
14159 restoreMBB->addSuccessor(sinkMBB);
14161 MI->eraseFromParent();
14165 MachineBasicBlock *
14166 X86TargetLowering::emitEHSjLjLongJmp(MachineInstr *MI,
14167 MachineBasicBlock *MBB) const {
14168 DebugLoc DL = MI->getDebugLoc();
14169 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
14171 MachineFunction *MF = MBB->getParent();
14172 MachineRegisterInfo &MRI = MF->getRegInfo();
14174 // Memory Reference
14175 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
14176 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
14178 MVT PVT = getPointerTy();
14179 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
14180 "Invalid Pointer Size!");
14182 const TargetRegisterClass *RC =
14183 (PVT == MVT::i64) ? &X86::GR64RegClass : &X86::GR32RegClass;
14184 unsigned Tmp = MRI.createVirtualRegister(RC);
14185 // Since FP is only updated here but NOT referenced, it's treated as GPR.
14186 unsigned FP = (PVT == MVT::i64) ? X86::RBP : X86::EBP;
14187 unsigned SP = RegInfo->getStackRegister();
14189 MachineInstrBuilder MIB;
14191 const int64_t LabelOffset = 1 * PVT.getStoreSize();
14192 const int64_t SPOffset = 2 * PVT.getStoreSize();
14194 unsigned PtrLoadOpc = (PVT == MVT::i64) ? X86::MOV64rm : X86::MOV32rm;
14195 unsigned IJmpOpc = (PVT == MVT::i64) ? X86::JMP64r : X86::JMP32r;
14198 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), FP);
14199 for (unsigned i = 0; i < X86::AddrNumOperands; ++i)
14200 MIB.addOperand(MI->getOperand(i));
14201 MIB.setMemRefs(MMOBegin, MMOEnd);
14203 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), Tmp);
14204 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
14205 if (i == X86::AddrDisp)
14206 MIB.addDisp(MI->getOperand(i), LabelOffset);
14208 MIB.addOperand(MI->getOperand(i));
14210 MIB.setMemRefs(MMOBegin, MMOEnd);
14212 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), SP);
14213 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
14214 if (i == X86::AddrDisp)
14215 MIB.addDisp(MI->getOperand(i), SPOffset);
14217 MIB.addOperand(MI->getOperand(i));
14219 MIB.setMemRefs(MMOBegin, MMOEnd);
14221 BuildMI(*MBB, MI, DL, TII->get(IJmpOpc)).addReg(Tmp);
14223 MI->eraseFromParent();
14227 MachineBasicBlock *
14228 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
14229 MachineBasicBlock *BB) const {
14230 switch (MI->getOpcode()) {
14231 default: llvm_unreachable("Unexpected instr type to insert");
14232 case X86::TAILJMPd64:
14233 case X86::TAILJMPr64:
14234 case X86::TAILJMPm64:
14235 llvm_unreachable("TAILJMP64 would not be touched here.");
14236 case X86::TCRETURNdi64:
14237 case X86::TCRETURNri64:
14238 case X86::TCRETURNmi64:
14240 case X86::WIN_ALLOCA:
14241 return EmitLoweredWinAlloca(MI, BB);
14242 case X86::SEG_ALLOCA_32:
14243 return EmitLoweredSegAlloca(MI, BB, false);
14244 case X86::SEG_ALLOCA_64:
14245 return EmitLoweredSegAlloca(MI, BB, true);
14246 case X86::TLSCall_32:
14247 case X86::TLSCall_64:
14248 return EmitLoweredTLSCall(MI, BB);
14249 case X86::CMOV_GR8:
14250 case X86::CMOV_FR32:
14251 case X86::CMOV_FR64:
14252 case X86::CMOV_V4F32:
14253 case X86::CMOV_V2F64:
14254 case X86::CMOV_V2I64:
14255 case X86::CMOV_V8F32:
14256 case X86::CMOV_V4F64:
14257 case X86::CMOV_V4I64:
14258 case X86::CMOV_GR16:
14259 case X86::CMOV_GR32:
14260 case X86::CMOV_RFP32:
14261 case X86::CMOV_RFP64:
14262 case X86::CMOV_RFP80:
14263 return EmitLoweredSelect(MI, BB);
14265 case X86::FP32_TO_INT16_IN_MEM:
14266 case X86::FP32_TO_INT32_IN_MEM:
14267 case X86::FP32_TO_INT64_IN_MEM:
14268 case X86::FP64_TO_INT16_IN_MEM:
14269 case X86::FP64_TO_INT32_IN_MEM:
14270 case X86::FP64_TO_INT64_IN_MEM:
14271 case X86::FP80_TO_INT16_IN_MEM:
14272 case X86::FP80_TO_INT32_IN_MEM:
14273 case X86::FP80_TO_INT64_IN_MEM: {
14274 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
14275 DebugLoc DL = MI->getDebugLoc();
14277 // Change the floating point control register to use "round towards zero"
14278 // mode when truncating to an integer value.
14279 MachineFunction *F = BB->getParent();
14280 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false);
14281 addFrameReference(BuildMI(*BB, MI, DL,
14282 TII->get(X86::FNSTCW16m)), CWFrameIdx);
14284 // Load the old value of the high byte of the control word...
14286 F->getRegInfo().createVirtualRegister(&X86::GR16RegClass);
14287 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW),
14290 // Set the high part to be round to zero...
14291 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
14294 // Reload the modified control word now...
14295 addFrameReference(BuildMI(*BB, MI, DL,
14296 TII->get(X86::FLDCW16m)), CWFrameIdx);
14298 // Restore the memory image of control word to original value
14299 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
14302 // Get the X86 opcode to use.
14304 switch (MI->getOpcode()) {
14305 default: llvm_unreachable("illegal opcode!");
14306 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
14307 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
14308 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
14309 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
14310 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
14311 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
14312 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
14313 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
14314 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
14318 MachineOperand &Op = MI->getOperand(0);
14320 AM.BaseType = X86AddressMode::RegBase;
14321 AM.Base.Reg = Op.getReg();
14323 AM.BaseType = X86AddressMode::FrameIndexBase;
14324 AM.Base.FrameIndex = Op.getIndex();
14326 Op = MI->getOperand(1);
14328 AM.Scale = Op.getImm();
14329 Op = MI->getOperand(2);
14331 AM.IndexReg = Op.getImm();
14332 Op = MI->getOperand(3);
14333 if (Op.isGlobal()) {
14334 AM.GV = Op.getGlobal();
14336 AM.Disp = Op.getImm();
14338 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM)
14339 .addReg(MI->getOperand(X86::AddrNumOperands).getReg());
14341 // Reload the original control word now.
14342 addFrameReference(BuildMI(*BB, MI, DL,
14343 TII->get(X86::FLDCW16m)), CWFrameIdx);
14345 MI->eraseFromParent(); // The pseudo instruction is gone now.
14348 // String/text processing lowering.
14349 case X86::PCMPISTRM128REG:
14350 case X86::VPCMPISTRM128REG:
14351 case X86::PCMPISTRM128MEM:
14352 case X86::VPCMPISTRM128MEM:
14353 case X86::PCMPESTRM128REG:
14354 case X86::VPCMPESTRM128REG:
14355 case X86::PCMPESTRM128MEM:
14356 case X86::VPCMPESTRM128MEM:
14357 assert(Subtarget->hasSSE42() &&
14358 "Target must have SSE4.2 or AVX features enabled");
14359 return EmitPCMPSTRM(MI, BB, getTargetMachine().getInstrInfo());
14361 // String/text processing lowering.
14362 case X86::PCMPISTRIREG:
14363 case X86::VPCMPISTRIREG:
14364 case X86::PCMPISTRIMEM:
14365 case X86::VPCMPISTRIMEM:
14366 case X86::PCMPESTRIREG:
14367 case X86::VPCMPESTRIREG:
14368 case X86::PCMPESTRIMEM:
14369 case X86::VPCMPESTRIMEM:
14370 assert(Subtarget->hasSSE42() &&
14371 "Target must have SSE4.2 or AVX features enabled");
14372 return EmitPCMPSTRI(MI, BB, getTargetMachine().getInstrInfo());
14374 // Thread synchronization.
14376 return EmitMonitor(MI, BB, getTargetMachine().getInstrInfo(), Subtarget);
14380 return EmitXBegin(MI, BB, getTargetMachine().getInstrInfo());
14382 // Atomic Lowering.
14383 case X86::ATOMAND8:
14384 case X86::ATOMAND16:
14385 case X86::ATOMAND32:
14386 case X86::ATOMAND64:
14389 case X86::ATOMOR16:
14390 case X86::ATOMOR32:
14391 case X86::ATOMOR64:
14393 case X86::ATOMXOR16:
14394 case X86::ATOMXOR8:
14395 case X86::ATOMXOR32:
14396 case X86::ATOMXOR64:
14398 case X86::ATOMNAND8:
14399 case X86::ATOMNAND16:
14400 case X86::ATOMNAND32:
14401 case X86::ATOMNAND64:
14403 case X86::ATOMMAX8:
14404 case X86::ATOMMAX16:
14405 case X86::ATOMMAX32:
14406 case X86::ATOMMAX64:
14408 case X86::ATOMMIN8:
14409 case X86::ATOMMIN16:
14410 case X86::ATOMMIN32:
14411 case X86::ATOMMIN64:
14413 case X86::ATOMUMAX8:
14414 case X86::ATOMUMAX16:
14415 case X86::ATOMUMAX32:
14416 case X86::ATOMUMAX64:
14418 case X86::ATOMUMIN8:
14419 case X86::ATOMUMIN16:
14420 case X86::ATOMUMIN32:
14421 case X86::ATOMUMIN64:
14422 return EmitAtomicLoadArith(MI, BB);
14424 // This group does 64-bit operations on a 32-bit host.
14425 case X86::ATOMAND6432:
14426 case X86::ATOMOR6432:
14427 case X86::ATOMXOR6432:
14428 case X86::ATOMNAND6432:
14429 case X86::ATOMADD6432:
14430 case X86::ATOMSUB6432:
14431 case X86::ATOMMAX6432:
14432 case X86::ATOMMIN6432:
14433 case X86::ATOMUMAX6432:
14434 case X86::ATOMUMIN6432:
14435 case X86::ATOMSWAP6432:
14436 return EmitAtomicLoadArith6432(MI, BB);
14438 case X86::VASTART_SAVE_XMM_REGS:
14439 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
14441 case X86::VAARG_64:
14442 return EmitVAARG64WithCustomInserter(MI, BB);
14444 case X86::EH_SjLj_SetJmp32:
14445 case X86::EH_SjLj_SetJmp64:
14446 return emitEHSjLjSetJmp(MI, BB);
14448 case X86::EH_SjLj_LongJmp32:
14449 case X86::EH_SjLj_LongJmp64:
14450 return emitEHSjLjLongJmp(MI, BB);
14454 //===----------------------------------------------------------------------===//
14455 // X86 Optimization Hooks
14456 //===----------------------------------------------------------------------===//
14458 void X86TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
14461 const SelectionDAG &DAG,
14462 unsigned Depth) const {
14463 unsigned BitWidth = KnownZero.getBitWidth();
14464 unsigned Opc = Op.getOpcode();
14465 assert((Opc >= ISD::BUILTIN_OP_END ||
14466 Opc == ISD::INTRINSIC_WO_CHAIN ||
14467 Opc == ISD::INTRINSIC_W_CHAIN ||
14468 Opc == ISD::INTRINSIC_VOID) &&
14469 "Should use MaskedValueIsZero if you don't know whether Op"
14470 " is a target node!");
14472 KnownZero = KnownOne = APInt(BitWidth, 0); // Don't know anything.
14486 // These nodes' second result is a boolean.
14487 if (Op.getResNo() == 0)
14490 case X86ISD::SETCC:
14491 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1);
14493 case ISD::INTRINSIC_WO_CHAIN: {
14494 unsigned IntId = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
14495 unsigned NumLoBits = 0;
14498 case Intrinsic::x86_sse_movmsk_ps:
14499 case Intrinsic::x86_avx_movmsk_ps_256:
14500 case Intrinsic::x86_sse2_movmsk_pd:
14501 case Intrinsic::x86_avx_movmsk_pd_256:
14502 case Intrinsic::x86_mmx_pmovmskb:
14503 case Intrinsic::x86_sse2_pmovmskb_128:
14504 case Intrinsic::x86_avx2_pmovmskb: {
14505 // High bits of movmskp{s|d}, pmovmskb are known zero.
14507 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
14508 case Intrinsic::x86_sse_movmsk_ps: NumLoBits = 4; break;
14509 case Intrinsic::x86_avx_movmsk_ps_256: NumLoBits = 8; break;
14510 case Intrinsic::x86_sse2_movmsk_pd: NumLoBits = 2; break;
14511 case Intrinsic::x86_avx_movmsk_pd_256: NumLoBits = 4; break;
14512 case Intrinsic::x86_mmx_pmovmskb: NumLoBits = 8; break;
14513 case Intrinsic::x86_sse2_pmovmskb_128: NumLoBits = 16; break;
14514 case Intrinsic::x86_avx2_pmovmskb: NumLoBits = 32; break;
14516 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - NumLoBits);
14525 unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(SDValue Op,
14526 unsigned Depth) const {
14527 // SETCC_CARRY sets the dest to ~0 for true or 0 for false.
14528 if (Op.getOpcode() == X86ISD::SETCC_CARRY)
14529 return Op.getValueType().getScalarType().getSizeInBits();
14535 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
14536 /// node is a GlobalAddress + offset.
14537 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
14538 const GlobalValue* &GA,
14539 int64_t &Offset) const {
14540 if (N->getOpcode() == X86ISD::Wrapper) {
14541 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
14542 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
14543 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
14547 return TargetLowering::isGAPlusOffset(N, GA, Offset);
14550 /// isShuffleHigh128VectorInsertLow - Checks whether the shuffle node is the
14551 /// same as extracting the high 128-bit part of 256-bit vector and then
14552 /// inserting the result into the low part of a new 256-bit vector
14553 static bool isShuffleHigh128VectorInsertLow(ShuffleVectorSDNode *SVOp) {
14554 EVT VT = SVOp->getValueType(0);
14555 unsigned NumElems = VT.getVectorNumElements();
14557 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
14558 for (unsigned i = 0, j = NumElems/2; i != NumElems/2; ++i, ++j)
14559 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
14560 SVOp->getMaskElt(j) >= 0)
14566 /// isShuffleLow128VectorInsertHigh - Checks whether the shuffle node is the
14567 /// same as extracting the low 128-bit part of 256-bit vector and then
14568 /// inserting the result into the high part of a new 256-bit vector
14569 static bool isShuffleLow128VectorInsertHigh(ShuffleVectorSDNode *SVOp) {
14570 EVT VT = SVOp->getValueType(0);
14571 unsigned NumElems = VT.getVectorNumElements();
14573 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
14574 for (unsigned i = NumElems/2, j = 0; i != NumElems; ++i, ++j)
14575 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
14576 SVOp->getMaskElt(j) >= 0)
14582 /// PerformShuffleCombine256 - Performs shuffle combines for 256-bit vectors.
14583 static SDValue PerformShuffleCombine256(SDNode *N, SelectionDAG &DAG,
14584 TargetLowering::DAGCombinerInfo &DCI,
14585 const X86Subtarget* Subtarget) {
14586 DebugLoc dl = N->getDebugLoc();
14587 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
14588 SDValue V1 = SVOp->getOperand(0);
14589 SDValue V2 = SVOp->getOperand(1);
14590 EVT VT = SVOp->getValueType(0);
14591 unsigned NumElems = VT.getVectorNumElements();
14593 if (V1.getOpcode() == ISD::CONCAT_VECTORS &&
14594 V2.getOpcode() == ISD::CONCAT_VECTORS) {
14598 // V UNDEF BUILD_VECTOR UNDEF
14600 // CONCAT_VECTOR CONCAT_VECTOR
14603 // RESULT: V + zero extended
14605 if (V2.getOperand(0).getOpcode() != ISD::BUILD_VECTOR ||
14606 V2.getOperand(1).getOpcode() != ISD::UNDEF ||
14607 V1.getOperand(1).getOpcode() != ISD::UNDEF)
14610 if (!ISD::isBuildVectorAllZeros(V2.getOperand(0).getNode()))
14613 // To match the shuffle mask, the first half of the mask should
14614 // be exactly the first vector, and all the rest a splat with the
14615 // first element of the second one.
14616 for (unsigned i = 0; i != NumElems/2; ++i)
14617 if (!isUndefOrEqual(SVOp->getMaskElt(i), i) ||
14618 !isUndefOrEqual(SVOp->getMaskElt(i+NumElems/2), NumElems))
14621 // If V1 is coming from a vector load then just fold to a VZEXT_LOAD.
14622 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(V1.getOperand(0))) {
14623 if (Ld->hasNUsesOfValue(1, 0)) {
14624 SDVTList Tys = DAG.getVTList(MVT::v4i64, MVT::Other);
14625 SDValue Ops[] = { Ld->getChain(), Ld->getBasePtr() };
14627 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops, 2,
14629 Ld->getPointerInfo(),
14630 Ld->getAlignment(),
14631 false/*isVolatile*/, true/*ReadMem*/,
14632 false/*WriteMem*/);
14634 // Make sure the newly-created LOAD is in the same position as Ld in
14635 // terms of dependency. We create a TokenFactor for Ld and ResNode,
14636 // and update uses of Ld's output chain to use the TokenFactor.
14637 if (Ld->hasAnyUseOfValue(1)) {
14638 SDValue NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
14639 SDValue(Ld, 1), SDValue(ResNode.getNode(), 1));
14640 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), NewChain);
14641 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(Ld, 1),
14642 SDValue(ResNode.getNode(), 1));
14645 return DAG.getNode(ISD::BITCAST, dl, VT, ResNode);
14649 // Emit a zeroed vector and insert the desired subvector on its
14651 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
14652 SDValue InsV = Insert128BitVector(Zeros, V1.getOperand(0), 0, DAG, dl);
14653 return DCI.CombineTo(N, InsV);
14656 //===--------------------------------------------------------------------===//
14657 // Combine some shuffles into subvector extracts and inserts:
14660 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
14661 if (isShuffleHigh128VectorInsertLow(SVOp)) {
14662 SDValue V = Extract128BitVector(V1, NumElems/2, DAG, dl);
14663 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, 0, DAG, dl);
14664 return DCI.CombineTo(N, InsV);
14667 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
14668 if (isShuffleLow128VectorInsertHigh(SVOp)) {
14669 SDValue V = Extract128BitVector(V1, 0, DAG, dl);
14670 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, NumElems/2, DAG, dl);
14671 return DCI.CombineTo(N, InsV);
14677 /// PerformShuffleCombine - Performs several different shuffle combines.
14678 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
14679 TargetLowering::DAGCombinerInfo &DCI,
14680 const X86Subtarget *Subtarget) {
14681 DebugLoc dl = N->getDebugLoc();
14682 EVT VT = N->getValueType(0);
14684 // Don't create instructions with illegal types after legalize types has run.
14685 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14686 if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType()))
14689 // Combine 256-bit vector shuffles. This is only profitable when in AVX mode
14690 if (Subtarget->hasFp256() && VT.is256BitVector() &&
14691 N->getOpcode() == ISD::VECTOR_SHUFFLE)
14692 return PerformShuffleCombine256(N, DAG, DCI, Subtarget);
14694 // Only handle 128 wide vector from here on.
14695 if (!VT.is128BitVector())
14698 // Combine a vector_shuffle that is equal to build_vector load1, load2, load3,
14699 // load4, <0, 1, 2, 3> into a 128-bit load if the load addresses are
14700 // consecutive, non-overlapping, and in the right order.
14701 SmallVector<SDValue, 16> Elts;
14702 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
14703 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0));
14705 return EltsFromConsecutiveLoads(VT, Elts, dl, DAG);
14708 /// PerformTruncateCombine - Converts truncate operation to
14709 /// a sequence of vector shuffle operations.
14710 /// It is possible when we truncate 256-bit vector to 128-bit vector
14711 static SDValue PerformTruncateCombine(SDNode *N, SelectionDAG &DAG,
14712 TargetLowering::DAGCombinerInfo &DCI,
14713 const X86Subtarget *Subtarget) {
14717 /// XFormVExtractWithShuffleIntoLoad - Check if a vector extract from a target
14718 /// specific shuffle of a load can be folded into a single element load.
14719 /// Similar handling for VECTOR_SHUFFLE is performed by DAGCombiner, but
14720 /// shuffles have been customed lowered so we need to handle those here.
14721 static SDValue XFormVExtractWithShuffleIntoLoad(SDNode *N, SelectionDAG &DAG,
14722 TargetLowering::DAGCombinerInfo &DCI) {
14723 if (DCI.isBeforeLegalizeOps())
14726 SDValue InVec = N->getOperand(0);
14727 SDValue EltNo = N->getOperand(1);
14729 if (!isa<ConstantSDNode>(EltNo))
14732 EVT VT = InVec.getValueType();
14734 bool HasShuffleIntoBitcast = false;
14735 if (InVec.getOpcode() == ISD::BITCAST) {
14736 // Don't duplicate a load with other uses.
14737 if (!InVec.hasOneUse())
14739 EVT BCVT = InVec.getOperand(0).getValueType();
14740 if (BCVT.getVectorNumElements() != VT.getVectorNumElements())
14742 InVec = InVec.getOperand(0);
14743 HasShuffleIntoBitcast = true;
14746 if (!isTargetShuffle(InVec.getOpcode()))
14749 // Don't duplicate a load with other uses.
14750 if (!InVec.hasOneUse())
14753 SmallVector<int, 16> ShuffleMask;
14755 if (!getTargetShuffleMask(InVec.getNode(), VT.getSimpleVT(), ShuffleMask,
14759 // Select the input vector, guarding against out of range extract vector.
14760 unsigned NumElems = VT.getVectorNumElements();
14761 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
14762 int Idx = (Elt > (int)NumElems) ? -1 : ShuffleMask[Elt];
14763 SDValue LdNode = (Idx < (int)NumElems) ? InVec.getOperand(0)
14764 : InVec.getOperand(1);
14766 // If inputs to shuffle are the same for both ops, then allow 2 uses
14767 unsigned AllowedUses = InVec.getOperand(0) == InVec.getOperand(1) ? 2 : 1;
14769 if (LdNode.getOpcode() == ISD::BITCAST) {
14770 // Don't duplicate a load with other uses.
14771 if (!LdNode.getNode()->hasNUsesOfValue(AllowedUses, 0))
14774 AllowedUses = 1; // only allow 1 load use if we have a bitcast
14775 LdNode = LdNode.getOperand(0);
14778 if (!ISD::isNormalLoad(LdNode.getNode()))
14781 LoadSDNode *LN0 = cast<LoadSDNode>(LdNode);
14783 if (!LN0 ||!LN0->hasNUsesOfValue(AllowedUses, 0) || LN0->isVolatile())
14786 if (HasShuffleIntoBitcast) {
14787 // If there's a bitcast before the shuffle, check if the load type and
14788 // alignment is valid.
14789 unsigned Align = LN0->getAlignment();
14790 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14791 unsigned NewAlign = TLI.getDataLayout()->
14792 getABITypeAlignment(VT.getTypeForEVT(*DAG.getContext()));
14794 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, VT))
14798 // All checks match so transform back to vector_shuffle so that DAG combiner
14799 // can finish the job
14800 DebugLoc dl = N->getDebugLoc();
14802 // Create shuffle node taking into account the case that its a unary shuffle
14803 SDValue Shuffle = (UnaryShuffle) ? DAG.getUNDEF(VT) : InVec.getOperand(1);
14804 Shuffle = DAG.getVectorShuffle(InVec.getValueType(), dl,
14805 InVec.getOperand(0), Shuffle,
14807 Shuffle = DAG.getNode(ISD::BITCAST, dl, VT, Shuffle);
14808 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, N->getValueType(0), Shuffle,
14812 /// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index
14813 /// generation and convert it from being a bunch of shuffles and extracts
14814 /// to a simple store and scalar loads to extract the elements.
14815 static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG,
14816 TargetLowering::DAGCombinerInfo &DCI) {
14817 SDValue NewOp = XFormVExtractWithShuffleIntoLoad(N, DAG, DCI);
14818 if (NewOp.getNode())
14821 SDValue InputVector = N->getOperand(0);
14822 // Detect whether we are trying to convert from mmx to i32 and the bitcast
14823 // from mmx to v2i32 has a single usage.
14824 if (InputVector.getNode()->getOpcode() == llvm::ISD::BITCAST &&
14825 InputVector.getNode()->getOperand(0).getValueType() == MVT::x86mmx &&
14826 InputVector.hasOneUse() && N->getValueType(0) == MVT::i32)
14827 return DAG.getNode(X86ISD::MMX_MOVD2W, InputVector.getDebugLoc(),
14828 N->getValueType(0),
14829 InputVector.getNode()->getOperand(0));
14831 // Only operate on vectors of 4 elements, where the alternative shuffling
14832 // gets to be more expensive.
14833 if (InputVector.getValueType() != MVT::v4i32)
14836 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a
14837 // single use which is a sign-extend or zero-extend, and all elements are
14839 SmallVector<SDNode *, 4> Uses;
14840 unsigned ExtractedElements = 0;
14841 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(),
14842 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) {
14843 if (UI.getUse().getResNo() != InputVector.getResNo())
14846 SDNode *Extract = *UI;
14847 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
14850 if (Extract->getValueType(0) != MVT::i32)
14852 if (!Extract->hasOneUse())
14854 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND &&
14855 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND)
14857 if (!isa<ConstantSDNode>(Extract->getOperand(1)))
14860 // Record which element was extracted.
14861 ExtractedElements |=
14862 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue();
14864 Uses.push_back(Extract);
14867 // If not all the elements were used, this may not be worthwhile.
14868 if (ExtractedElements != 15)
14871 // Ok, we've now decided to do the transformation.
14872 DebugLoc dl = InputVector.getDebugLoc();
14874 // Store the value to a temporary stack slot.
14875 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType());
14876 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr,
14877 MachinePointerInfo(), false, false, 0);
14879 // Replace each use (extract) with a load of the appropriate element.
14880 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(),
14881 UE = Uses.end(); UI != UE; ++UI) {
14882 SDNode *Extract = *UI;
14884 // cOMpute the element's address.
14885 SDValue Idx = Extract->getOperand(1);
14887 InputVector.getValueType().getVectorElementType().getSizeInBits()/8;
14888 uint64_t Offset = EltSize * cast<ConstantSDNode>(Idx)->getZExtValue();
14889 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14890 SDValue OffsetVal = DAG.getConstant(Offset, TLI.getPointerTy());
14892 SDValue ScalarAddr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(),
14893 StackPtr, OffsetVal);
14895 // Load the scalar.
14896 SDValue LoadScalar = DAG.getLoad(Extract->getValueType(0), dl, Ch,
14897 ScalarAddr, MachinePointerInfo(),
14898 false, false, false, 0);
14900 // Replace the exact with the load.
14901 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), LoadScalar);
14904 // The replacement was made in place; don't return anything.
14908 /// \brief Matches a VSELECT onto min/max or return 0 if the node doesn't match.
14909 static unsigned matchIntegerMINMAX(SDValue Cond, EVT VT, SDValue LHS,
14910 SDValue RHS, SelectionDAG &DAG,
14911 const X86Subtarget *Subtarget) {
14912 if (!VT.isVector())
14915 switch (VT.getSimpleVT().SimpleTy) {
14920 if (!Subtarget->hasAVX2())
14925 if (!Subtarget->hasSSE2())
14929 // SSE2 has only a small subset of the operations.
14930 bool hasUnsigned = Subtarget->hasSSE41() ||
14931 (Subtarget->hasSSE2() && VT == MVT::v16i8);
14932 bool hasSigned = Subtarget->hasSSE41() ||
14933 (Subtarget->hasSSE2() && VT == MVT::v8i16);
14935 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
14937 // Check for x CC y ? x : y.
14938 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
14939 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
14944 return hasUnsigned ? X86ISD::UMIN : 0;
14947 return hasUnsigned ? X86ISD::UMAX : 0;
14950 return hasSigned ? X86ISD::SMIN : 0;
14953 return hasSigned ? X86ISD::SMAX : 0;
14955 // Check for x CC y ? y : x -- a min/max with reversed arms.
14956 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
14957 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
14962 return hasUnsigned ? X86ISD::UMAX : 0;
14965 return hasUnsigned ? X86ISD::UMIN : 0;
14968 return hasSigned ? X86ISD::SMAX : 0;
14971 return hasSigned ? X86ISD::SMIN : 0;
14978 /// PerformSELECTCombine - Do target-specific dag combines on SELECT and VSELECT
14980 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
14981 TargetLowering::DAGCombinerInfo &DCI,
14982 const X86Subtarget *Subtarget) {
14983 DebugLoc DL = N->getDebugLoc();
14984 SDValue Cond = N->getOperand(0);
14985 // Get the LHS/RHS of the select.
14986 SDValue LHS = N->getOperand(1);
14987 SDValue RHS = N->getOperand(2);
14988 EVT VT = LHS.getValueType();
14990 // If we have SSE[12] support, try to form min/max nodes. SSE min/max
14991 // instructions match the semantics of the common C idiom x<y?x:y but not
14992 // x<=y?x:y, because of how they handle negative zero (which can be
14993 // ignored in unsafe-math mode).
14994 if (Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() &&
14995 VT != MVT::f80 && DAG.getTargetLoweringInfo().isTypeLegal(VT) &&
14996 (Subtarget->hasSSE2() ||
14997 (Subtarget->hasSSE1() && VT.getScalarType() == MVT::f32))) {
14998 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
15000 unsigned Opcode = 0;
15001 // Check for x CC y ? x : y.
15002 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
15003 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
15007 // Converting this to a min would handle NaNs incorrectly, and swapping
15008 // the operands would cause it to handle comparisons between positive
15009 // and negative zero incorrectly.
15010 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
15011 if (!DAG.getTarget().Options.UnsafeFPMath &&
15012 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
15014 std::swap(LHS, RHS);
15016 Opcode = X86ISD::FMIN;
15019 // Converting this to a min would handle comparisons between positive
15020 // and negative zero incorrectly.
15021 if (!DAG.getTarget().Options.UnsafeFPMath &&
15022 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
15024 Opcode = X86ISD::FMIN;
15027 // Converting this to a min would handle both negative zeros and NaNs
15028 // incorrectly, but we can swap the operands to fix both.
15029 std::swap(LHS, RHS);
15033 Opcode = X86ISD::FMIN;
15037 // Converting this to a max would handle comparisons between positive
15038 // and negative zero incorrectly.
15039 if (!DAG.getTarget().Options.UnsafeFPMath &&
15040 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
15042 Opcode = X86ISD::FMAX;
15045 // Converting this to a max would handle NaNs incorrectly, and swapping
15046 // the operands would cause it to handle comparisons between positive
15047 // and negative zero incorrectly.
15048 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
15049 if (!DAG.getTarget().Options.UnsafeFPMath &&
15050 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
15052 std::swap(LHS, RHS);
15054 Opcode = X86ISD::FMAX;
15057 // Converting this to a max would handle both negative zeros and NaNs
15058 // incorrectly, but we can swap the operands to fix both.
15059 std::swap(LHS, RHS);
15063 Opcode = X86ISD::FMAX;
15066 // Check for x CC y ? y : x -- a min/max with reversed arms.
15067 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
15068 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
15072 // Converting this to a min would handle comparisons between positive
15073 // and negative zero incorrectly, and swapping the operands would
15074 // cause it to handle NaNs incorrectly.
15075 if (!DAG.getTarget().Options.UnsafeFPMath &&
15076 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) {
15077 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
15079 std::swap(LHS, RHS);
15081 Opcode = X86ISD::FMIN;
15084 // Converting this to a min would handle NaNs incorrectly.
15085 if (!DAG.getTarget().Options.UnsafeFPMath &&
15086 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
15088 Opcode = X86ISD::FMIN;
15091 // Converting this to a min would handle both negative zeros and NaNs
15092 // incorrectly, but we can swap the operands to fix both.
15093 std::swap(LHS, RHS);
15097 Opcode = X86ISD::FMIN;
15101 // Converting this to a max would handle NaNs incorrectly.
15102 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
15104 Opcode = X86ISD::FMAX;
15107 // Converting this to a max would handle comparisons between positive
15108 // and negative zero incorrectly, and swapping the operands would
15109 // cause it to handle NaNs incorrectly.
15110 if (!DAG.getTarget().Options.UnsafeFPMath &&
15111 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) {
15112 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
15114 std::swap(LHS, RHS);
15116 Opcode = X86ISD::FMAX;
15119 // Converting this to a max would handle both negative zeros and NaNs
15120 // incorrectly, but we can swap the operands to fix both.
15121 std::swap(LHS, RHS);
15125 Opcode = X86ISD::FMAX;
15131 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
15134 // If this is a select between two integer constants, try to do some
15136 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
15137 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
15138 // Don't do this for crazy integer types.
15139 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
15140 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
15141 // so that TrueC (the true value) is larger than FalseC.
15142 bool NeedsCondInvert = false;
15144 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
15145 // Efficiently invertible.
15146 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
15147 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
15148 isa<ConstantSDNode>(Cond.getOperand(1))))) {
15149 NeedsCondInvert = true;
15150 std::swap(TrueC, FalseC);
15153 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
15154 if (FalseC->getAPIntValue() == 0 &&
15155 TrueC->getAPIntValue().isPowerOf2()) {
15156 if (NeedsCondInvert) // Invert the condition if needed.
15157 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
15158 DAG.getConstant(1, Cond.getValueType()));
15160 // Zero extend the condition if needed.
15161 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
15163 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
15164 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
15165 DAG.getConstant(ShAmt, MVT::i8));
15168 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
15169 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
15170 if (NeedsCondInvert) // Invert the condition if needed.
15171 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
15172 DAG.getConstant(1, Cond.getValueType()));
15174 // Zero extend the condition if needed.
15175 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
15176 FalseC->getValueType(0), Cond);
15177 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
15178 SDValue(FalseC, 0));
15181 // Optimize cases that will turn into an LEA instruction. This requires
15182 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
15183 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
15184 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
15185 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
15187 bool isFastMultiplier = false;
15189 switch ((unsigned char)Diff) {
15191 case 1: // result = add base, cond
15192 case 2: // result = lea base( , cond*2)
15193 case 3: // result = lea base(cond, cond*2)
15194 case 4: // result = lea base( , cond*4)
15195 case 5: // result = lea base(cond, cond*4)
15196 case 8: // result = lea base( , cond*8)
15197 case 9: // result = lea base(cond, cond*8)
15198 isFastMultiplier = true;
15203 if (isFastMultiplier) {
15204 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
15205 if (NeedsCondInvert) // Invert the condition if needed.
15206 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
15207 DAG.getConstant(1, Cond.getValueType()));
15209 // Zero extend the condition if needed.
15210 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
15212 // Scale the condition by the difference.
15214 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
15215 DAG.getConstant(Diff, Cond.getValueType()));
15217 // Add the base if non-zero.
15218 if (FalseC->getAPIntValue() != 0)
15219 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
15220 SDValue(FalseC, 0));
15227 // Canonicalize max and min:
15228 // (x > y) ? x : y -> (x >= y) ? x : y
15229 // (x < y) ? x : y -> (x <= y) ? x : y
15230 // This allows use of COND_S / COND_NS (see TranslateX86CC) which eliminates
15231 // the need for an extra compare
15232 // against zero. e.g.
15233 // (x - y) > 0 : (x - y) ? 0 -> (x - y) >= 0 : (x - y) ? 0
15235 // testl %edi, %edi
15237 // cmovgl %edi, %eax
15241 // cmovsl %eax, %edi
15242 if (N->getOpcode() == ISD::SELECT && Cond.getOpcode() == ISD::SETCC &&
15243 DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
15244 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
15245 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
15250 ISD::CondCode NewCC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGE;
15251 Cond = DAG.getSetCC(Cond.getDebugLoc(), Cond.getValueType(),
15252 Cond.getOperand(0), Cond.getOperand(1), NewCC);
15253 return DAG.getNode(ISD::SELECT, DL, VT, Cond, LHS, RHS);
15258 // Match VSELECTs into subs with unsigned saturation.
15259 if (!DCI.isBeforeLegalize() &&
15260 N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC &&
15261 // psubus is available in SSE2 and AVX2 for i8 and i16 vectors.
15262 ((Subtarget->hasSSE2() && (VT == MVT::v16i8 || VT == MVT::v8i16)) ||
15263 (Subtarget->hasAVX2() && (VT == MVT::v32i8 || VT == MVT::v16i16)))) {
15264 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
15266 // Check if one of the arms of the VSELECT is a zero vector. If it's on the
15267 // left side invert the predicate to simplify logic below.
15269 if (ISD::isBuildVectorAllZeros(LHS.getNode())) {
15271 CC = ISD::getSetCCInverse(CC, true);
15272 } else if (ISD::isBuildVectorAllZeros(RHS.getNode())) {
15276 if (Other.getNode() && Other->getNumOperands() == 2 &&
15277 DAG.isEqualTo(Other->getOperand(0), Cond.getOperand(0))) {
15278 SDValue OpLHS = Other->getOperand(0), OpRHS = Other->getOperand(1);
15279 SDValue CondRHS = Cond->getOperand(1);
15281 // Look for a general sub with unsigned saturation first.
15282 // x >= y ? x-y : 0 --> subus x, y
15283 // x > y ? x-y : 0 --> subus x, y
15284 if ((CC == ISD::SETUGE || CC == ISD::SETUGT) &&
15285 Other->getOpcode() == ISD::SUB && DAG.isEqualTo(OpRHS, CondRHS))
15286 return DAG.getNode(X86ISD::SUBUS, DL, VT, OpLHS, OpRHS);
15288 // If the RHS is a constant we have to reverse the const canonicalization.
15289 // x > C-1 ? x+-C : 0 --> subus x, C
15290 if (CC == ISD::SETUGT && Other->getOpcode() == ISD::ADD &&
15291 isSplatVector(CondRHS.getNode()) && isSplatVector(OpRHS.getNode())) {
15292 APInt A = cast<ConstantSDNode>(OpRHS.getOperand(0))->getAPIntValue();
15293 if (CondRHS.getConstantOperandVal(0) == -A-1) {
15294 SmallVector<SDValue, 32> V(VT.getVectorNumElements(),
15295 DAG.getConstant(-A, VT.getScalarType()));
15296 return DAG.getNode(X86ISD::SUBUS, DL, VT, OpLHS,
15297 DAG.getNode(ISD::BUILD_VECTOR, DL, VT,
15298 V.data(), V.size()));
15302 // Another special case: If C was a sign bit, the sub has been
15303 // canonicalized into a xor.
15304 // FIXME: Would it be better to use ComputeMaskedBits to determine whether
15305 // it's safe to decanonicalize the xor?
15306 // x s< 0 ? x^C : 0 --> subus x, C
15307 if (CC == ISD::SETLT && Other->getOpcode() == ISD::XOR &&
15308 ISD::isBuildVectorAllZeros(CondRHS.getNode()) &&
15309 isSplatVector(OpRHS.getNode())) {
15310 APInt A = cast<ConstantSDNode>(OpRHS.getOperand(0))->getAPIntValue();
15312 return DAG.getNode(X86ISD::SUBUS, DL, VT, OpLHS, OpRHS);
15317 // Try to match a min/max vector operation.
15318 if (!DCI.isBeforeLegalize() &&
15319 N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC)
15320 if (unsigned Op = matchIntegerMINMAX(Cond, VT, LHS, RHS, DAG, Subtarget))
15321 return DAG.getNode(Op, DL, N->getValueType(0), LHS, RHS);
15323 // If we know that this node is legal then we know that it is going to be
15324 // matched by one of the SSE/AVX BLEND instructions. These instructions only
15325 // depend on the highest bit in each word. Try to use SimplifyDemandedBits
15326 // to simplify previous instructions.
15327 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
15328 if (N->getOpcode() == ISD::VSELECT && DCI.isBeforeLegalizeOps() &&
15329 !DCI.isBeforeLegalize() && TLI.isOperationLegal(ISD::VSELECT, VT)) {
15330 unsigned BitWidth = Cond.getValueType().getScalarType().getSizeInBits();
15332 // Don't optimize vector selects that map to mask-registers.
15336 assert(BitWidth >= 8 && BitWidth <= 64 && "Invalid mask size");
15337 APInt DemandedMask = APInt::getHighBitsSet(BitWidth, 1);
15339 APInt KnownZero, KnownOne;
15340 TargetLowering::TargetLoweringOpt TLO(DAG, DCI.isBeforeLegalize(),
15341 DCI.isBeforeLegalizeOps());
15342 if (TLO.ShrinkDemandedConstant(Cond, DemandedMask) ||
15343 TLI.SimplifyDemandedBits(Cond, DemandedMask, KnownZero, KnownOne, TLO))
15344 DCI.CommitTargetLoweringOpt(TLO);
15350 // Check whether a boolean test is testing a boolean value generated by
15351 // X86ISD::SETCC. If so, return the operand of that SETCC and proper condition
15354 // Simplify the following patterns:
15355 // (Op (CMP (SETCC Cond EFLAGS) 1) EQ) or
15356 // (Op (CMP (SETCC Cond EFLAGS) 0) NEQ)
15357 // to (Op EFLAGS Cond)
15359 // (Op (CMP (SETCC Cond EFLAGS) 0) EQ) or
15360 // (Op (CMP (SETCC Cond EFLAGS) 1) NEQ)
15361 // to (Op EFLAGS !Cond)
15363 // where Op could be BRCOND or CMOV.
15365 static SDValue checkBoolTestSetCCCombine(SDValue Cmp, X86::CondCode &CC) {
15366 // Quit if not CMP and SUB with its value result used.
15367 if (Cmp.getOpcode() != X86ISD::CMP &&
15368 (Cmp.getOpcode() != X86ISD::SUB || Cmp.getNode()->hasAnyUseOfValue(0)))
15371 // Quit if not used as a boolean value.
15372 if (CC != X86::COND_E && CC != X86::COND_NE)
15375 // Check CMP operands. One of them should be 0 or 1 and the other should be
15376 // an SetCC or extended from it.
15377 SDValue Op1 = Cmp.getOperand(0);
15378 SDValue Op2 = Cmp.getOperand(1);
15381 const ConstantSDNode* C = 0;
15382 bool needOppositeCond = (CC == X86::COND_E);
15384 if ((C = dyn_cast<ConstantSDNode>(Op1)))
15386 else if ((C = dyn_cast<ConstantSDNode>(Op2)))
15388 else // Quit if all operands are not constants.
15391 if (C->getZExtValue() == 1)
15392 needOppositeCond = !needOppositeCond;
15393 else if (C->getZExtValue() != 0)
15394 // Quit if the constant is neither 0 or 1.
15397 // Skip 'zext' node.
15398 if (SetCC.getOpcode() == ISD::ZERO_EXTEND)
15399 SetCC = SetCC.getOperand(0);
15401 switch (SetCC.getOpcode()) {
15402 case X86ISD::SETCC:
15403 // Set the condition code or opposite one if necessary.
15404 CC = X86::CondCode(SetCC.getConstantOperandVal(0));
15405 if (needOppositeCond)
15406 CC = X86::GetOppositeBranchCondition(CC);
15407 return SetCC.getOperand(1);
15408 case X86ISD::CMOV: {
15409 // Check whether false/true value has canonical one, i.e. 0 or 1.
15410 ConstantSDNode *FVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(0));
15411 ConstantSDNode *TVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(1));
15412 // Quit if true value is not a constant.
15415 // Quit if false value is not a constant.
15417 // A special case for rdrand, where 0 is set if false cond is found.
15418 SDValue Op = SetCC.getOperand(0);
15419 if (Op.getOpcode() != X86ISD::RDRAND)
15422 // Quit if false value is not the constant 0 or 1.
15423 bool FValIsFalse = true;
15424 if (FVal && FVal->getZExtValue() != 0) {
15425 if (FVal->getZExtValue() != 1)
15427 // If FVal is 1, opposite cond is needed.
15428 needOppositeCond = !needOppositeCond;
15429 FValIsFalse = false;
15431 // Quit if TVal is not the constant opposite of FVal.
15432 if (FValIsFalse && TVal->getZExtValue() != 1)
15434 if (!FValIsFalse && TVal->getZExtValue() != 0)
15436 CC = X86::CondCode(SetCC.getConstantOperandVal(2));
15437 if (needOppositeCond)
15438 CC = X86::GetOppositeBranchCondition(CC);
15439 return SetCC.getOperand(3);
15446 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
15447 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
15448 TargetLowering::DAGCombinerInfo &DCI,
15449 const X86Subtarget *Subtarget) {
15450 DebugLoc DL = N->getDebugLoc();
15452 // If the flag operand isn't dead, don't touch this CMOV.
15453 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
15456 SDValue FalseOp = N->getOperand(0);
15457 SDValue TrueOp = N->getOperand(1);
15458 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
15459 SDValue Cond = N->getOperand(3);
15461 if (CC == X86::COND_E || CC == X86::COND_NE) {
15462 switch (Cond.getOpcode()) {
15466 // If operand of BSR / BSF are proven never zero, then ZF cannot be set.
15467 if (DAG.isKnownNeverZero(Cond.getOperand(0)))
15468 return (CC == X86::COND_E) ? FalseOp : TrueOp;
15474 Flags = checkBoolTestSetCCCombine(Cond, CC);
15475 if (Flags.getNode() &&
15476 // Extra check as FCMOV only supports a subset of X86 cond.
15477 (FalseOp.getValueType() != MVT::f80 || hasFPCMov(CC))) {
15478 SDValue Ops[] = { FalseOp, TrueOp,
15479 DAG.getConstant(CC, MVT::i8), Flags };
15480 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList(),
15481 Ops, array_lengthof(Ops));
15484 // If this is a select between two integer constants, try to do some
15485 // optimizations. Note that the operands are ordered the opposite of SELECT
15487 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(TrueOp)) {
15488 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(FalseOp)) {
15489 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
15490 // larger than FalseC (the false value).
15491 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
15492 CC = X86::GetOppositeBranchCondition(CC);
15493 std::swap(TrueC, FalseC);
15494 std::swap(TrueOp, FalseOp);
15497 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
15498 // This is efficient for any integer data type (including i8/i16) and
15500 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
15501 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
15502 DAG.getConstant(CC, MVT::i8), Cond);
15504 // Zero extend the condition if needed.
15505 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
15507 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
15508 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
15509 DAG.getConstant(ShAmt, MVT::i8));
15510 if (N->getNumValues() == 2) // Dead flag value?
15511 return DCI.CombineTo(N, Cond, SDValue());
15515 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
15516 // for any integer data type, including i8/i16.
15517 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
15518 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
15519 DAG.getConstant(CC, MVT::i8), Cond);
15521 // Zero extend the condition if needed.
15522 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
15523 FalseC->getValueType(0), Cond);
15524 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
15525 SDValue(FalseC, 0));
15527 if (N->getNumValues() == 2) // Dead flag value?
15528 return DCI.CombineTo(N, Cond, SDValue());
15532 // Optimize cases that will turn into an LEA instruction. This requires
15533 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
15534 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
15535 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
15536 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
15538 bool isFastMultiplier = false;
15540 switch ((unsigned char)Diff) {
15542 case 1: // result = add base, cond
15543 case 2: // result = lea base( , cond*2)
15544 case 3: // result = lea base(cond, cond*2)
15545 case 4: // result = lea base( , cond*4)
15546 case 5: // result = lea base(cond, cond*4)
15547 case 8: // result = lea base( , cond*8)
15548 case 9: // result = lea base(cond, cond*8)
15549 isFastMultiplier = true;
15554 if (isFastMultiplier) {
15555 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
15556 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
15557 DAG.getConstant(CC, MVT::i8), Cond);
15558 // Zero extend the condition if needed.
15559 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
15561 // Scale the condition by the difference.
15563 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
15564 DAG.getConstant(Diff, Cond.getValueType()));
15566 // Add the base if non-zero.
15567 if (FalseC->getAPIntValue() != 0)
15568 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
15569 SDValue(FalseC, 0));
15570 if (N->getNumValues() == 2) // Dead flag value?
15571 return DCI.CombineTo(N, Cond, SDValue());
15578 // Handle these cases:
15579 // (select (x != c), e, c) -> select (x != c), e, x),
15580 // (select (x == c), c, e) -> select (x == c), x, e)
15581 // where the c is an integer constant, and the "select" is the combination
15582 // of CMOV and CMP.
15584 // The rationale for this change is that the conditional-move from a constant
15585 // needs two instructions, however, conditional-move from a register needs
15586 // only one instruction.
15588 // CAVEAT: By replacing a constant with a symbolic value, it may obscure
15589 // some instruction-combining opportunities. This opt needs to be
15590 // postponed as late as possible.
15592 if (!DCI.isBeforeLegalize() && !DCI.isBeforeLegalizeOps()) {
15593 // the DCI.xxxx conditions are provided to postpone the optimization as
15594 // late as possible.
15596 ConstantSDNode *CmpAgainst = 0;
15597 if ((Cond.getOpcode() == X86ISD::CMP || Cond.getOpcode() == X86ISD::SUB) &&
15598 (CmpAgainst = dyn_cast<ConstantSDNode>(Cond.getOperand(1))) &&
15599 dyn_cast<ConstantSDNode>(Cond.getOperand(0)) == 0) {
15601 if (CC == X86::COND_NE &&
15602 CmpAgainst == dyn_cast<ConstantSDNode>(FalseOp)) {
15603 CC = X86::GetOppositeBranchCondition(CC);
15604 std::swap(TrueOp, FalseOp);
15607 if (CC == X86::COND_E &&
15608 CmpAgainst == dyn_cast<ConstantSDNode>(TrueOp)) {
15609 SDValue Ops[] = { FalseOp, Cond.getOperand(0),
15610 DAG.getConstant(CC, MVT::i8), Cond };
15611 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList (), Ops,
15612 array_lengthof(Ops));
15620 /// PerformMulCombine - Optimize a single multiply with constant into two
15621 /// in order to implement it with two cheaper instructions, e.g.
15622 /// LEA + SHL, LEA + LEA.
15623 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
15624 TargetLowering::DAGCombinerInfo &DCI) {
15625 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
15628 EVT VT = N->getValueType(0);
15629 if (VT != MVT::i64)
15632 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
15635 uint64_t MulAmt = C->getZExtValue();
15636 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
15639 uint64_t MulAmt1 = 0;
15640 uint64_t MulAmt2 = 0;
15641 if ((MulAmt % 9) == 0) {
15643 MulAmt2 = MulAmt / 9;
15644 } else if ((MulAmt % 5) == 0) {
15646 MulAmt2 = MulAmt / 5;
15647 } else if ((MulAmt % 3) == 0) {
15649 MulAmt2 = MulAmt / 3;
15652 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
15653 DebugLoc DL = N->getDebugLoc();
15655 if (isPowerOf2_64(MulAmt2) &&
15656 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
15657 // If second multiplifer is pow2, issue it first. We want the multiply by
15658 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
15660 std::swap(MulAmt1, MulAmt2);
15663 if (isPowerOf2_64(MulAmt1))
15664 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
15665 DAG.getConstant(Log2_64(MulAmt1), MVT::i8));
15667 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
15668 DAG.getConstant(MulAmt1, VT));
15670 if (isPowerOf2_64(MulAmt2))
15671 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
15672 DAG.getConstant(Log2_64(MulAmt2), MVT::i8));
15674 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
15675 DAG.getConstant(MulAmt2, VT));
15677 // Do not add new nodes to DAG combiner worklist.
15678 DCI.CombineTo(N, NewMul, false);
15683 static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) {
15684 SDValue N0 = N->getOperand(0);
15685 SDValue N1 = N->getOperand(1);
15686 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
15687 EVT VT = N0.getValueType();
15689 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2))
15690 // since the result of setcc_c is all zero's or all ones.
15691 if (VT.isInteger() && !VT.isVector() &&
15692 N1C && N0.getOpcode() == ISD::AND &&
15693 N0.getOperand(1).getOpcode() == ISD::Constant) {
15694 SDValue N00 = N0.getOperand(0);
15695 if (N00.getOpcode() == X86ISD::SETCC_CARRY ||
15696 ((N00.getOpcode() == ISD::ANY_EXTEND ||
15697 N00.getOpcode() == ISD::ZERO_EXTEND) &&
15698 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY)) {
15699 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
15700 APInt ShAmt = N1C->getAPIntValue();
15701 Mask = Mask.shl(ShAmt);
15703 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
15704 N00, DAG.getConstant(Mask, VT));
15708 // Hardware support for vector shifts is sparse which makes us scalarize the
15709 // vector operations in many cases. Also, on sandybridge ADD is faster than
15711 // (shl V, 1) -> add V,V
15712 if (isSplatVector(N1.getNode())) {
15713 assert(N0.getValueType().isVector() && "Invalid vector shift type");
15714 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1->getOperand(0));
15715 // We shift all of the values by one. In many cases we do not have
15716 // hardware support for this operation. This is better expressed as an ADD
15718 if (N1C && (1 == N1C->getZExtValue())) {
15719 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, N0);
15726 /// PerformShiftCombine - Transforms vector shift nodes to use vector shifts
15728 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
15729 TargetLowering::DAGCombinerInfo &DCI,
15730 const X86Subtarget *Subtarget) {
15731 EVT VT = N->getValueType(0);
15732 if (N->getOpcode() == ISD::SHL) {
15733 SDValue V = PerformSHLCombine(N, DAG);
15734 if (V.getNode()) return V;
15737 // On X86 with SSE2 support, we can transform this to a vector shift if
15738 // all elements are shifted by the same amount. We can't do this in legalize
15739 // because the a constant vector is typically transformed to a constant pool
15740 // so we have no knowledge of the shift amount.
15741 if (!Subtarget->hasSSE2())
15744 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16 &&
15745 (!Subtarget->hasInt256() ||
15746 (VT != MVT::v4i64 && VT != MVT::v8i32 && VT != MVT::v16i16)))
15749 SDValue ShAmtOp = N->getOperand(1);
15750 EVT EltVT = VT.getVectorElementType();
15751 DebugLoc DL = N->getDebugLoc();
15752 SDValue BaseShAmt = SDValue();
15753 if (ShAmtOp.getOpcode() == ISD::BUILD_VECTOR) {
15754 unsigned NumElts = VT.getVectorNumElements();
15756 for (; i != NumElts; ++i) {
15757 SDValue Arg = ShAmtOp.getOperand(i);
15758 if (Arg.getOpcode() == ISD::UNDEF) continue;
15762 // Handle the case where the build_vector is all undef
15763 // FIXME: Should DAG allow this?
15767 for (; i != NumElts; ++i) {
15768 SDValue Arg = ShAmtOp.getOperand(i);
15769 if (Arg.getOpcode() == ISD::UNDEF) continue;
15770 if (Arg != BaseShAmt) {
15774 } else if (ShAmtOp.getOpcode() == ISD::VECTOR_SHUFFLE &&
15775 cast<ShuffleVectorSDNode>(ShAmtOp)->isSplat()) {
15776 SDValue InVec = ShAmtOp.getOperand(0);
15777 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
15778 unsigned NumElts = InVec.getValueType().getVectorNumElements();
15780 for (; i != NumElts; ++i) {
15781 SDValue Arg = InVec.getOperand(i);
15782 if (Arg.getOpcode() == ISD::UNDEF) continue;
15786 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
15787 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
15788 unsigned SplatIdx= cast<ShuffleVectorSDNode>(ShAmtOp)->getSplatIndex();
15789 if (C->getZExtValue() == SplatIdx)
15790 BaseShAmt = InVec.getOperand(1);
15793 if (BaseShAmt.getNode() == 0) {
15794 // Don't create instructions with illegal types after legalize
15796 if (!DAG.getTargetLoweringInfo().isTypeLegal(EltVT) &&
15797 !DCI.isBeforeLegalize())
15800 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, ShAmtOp,
15801 DAG.getIntPtrConstant(0));
15806 // The shift amount is an i32.
15807 if (EltVT.bitsGT(MVT::i32))
15808 BaseShAmt = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, BaseShAmt);
15809 else if (EltVT.bitsLT(MVT::i32))
15810 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, BaseShAmt);
15812 // The shift amount is identical so we can do a vector shift.
15813 SDValue ValOp = N->getOperand(0);
15814 switch (N->getOpcode()) {
15816 llvm_unreachable("Unknown shift opcode!");
15818 switch (VT.getSimpleVT().SimpleTy) {
15819 default: return SDValue();
15826 return getTargetVShiftNode(X86ISD::VSHLI, DL, VT, ValOp, BaseShAmt, DAG);
15829 switch (VT.getSimpleVT().SimpleTy) {
15830 default: return SDValue();
15835 return getTargetVShiftNode(X86ISD::VSRAI, DL, VT, ValOp, BaseShAmt, DAG);
15838 switch (VT.getSimpleVT().SimpleTy) {
15839 default: return SDValue();
15846 return getTargetVShiftNode(X86ISD::VSRLI, DL, VT, ValOp, BaseShAmt, DAG);
15851 // CMPEQCombine - Recognize the distinctive (AND (setcc ...) (setcc ..))
15852 // where both setccs reference the same FP CMP, and rewrite for CMPEQSS
15853 // and friends. Likewise for OR -> CMPNEQSS.
15854 static SDValue CMPEQCombine(SDNode *N, SelectionDAG &DAG,
15855 TargetLowering::DAGCombinerInfo &DCI,
15856 const X86Subtarget *Subtarget) {
15859 // SSE1 supports CMP{eq|ne}SS, and SSE2 added CMP{eq|ne}SD, but
15860 // we're requiring SSE2 for both.
15861 if (Subtarget->hasSSE2() && isAndOrOfSetCCs(SDValue(N, 0U), opcode)) {
15862 SDValue N0 = N->getOperand(0);
15863 SDValue N1 = N->getOperand(1);
15864 SDValue CMP0 = N0->getOperand(1);
15865 SDValue CMP1 = N1->getOperand(1);
15866 DebugLoc DL = N->getDebugLoc();
15868 // The SETCCs should both refer to the same CMP.
15869 if (CMP0.getOpcode() != X86ISD::CMP || CMP0 != CMP1)
15872 SDValue CMP00 = CMP0->getOperand(0);
15873 SDValue CMP01 = CMP0->getOperand(1);
15874 EVT VT = CMP00.getValueType();
15876 if (VT == MVT::f32 || VT == MVT::f64) {
15877 bool ExpectingFlags = false;
15878 // Check for any users that want flags:
15879 for (SDNode::use_iterator UI = N->use_begin(),
15881 !ExpectingFlags && UI != UE; ++UI)
15882 switch (UI->getOpcode()) {
15887 ExpectingFlags = true;
15889 case ISD::CopyToReg:
15890 case ISD::SIGN_EXTEND:
15891 case ISD::ZERO_EXTEND:
15892 case ISD::ANY_EXTEND:
15896 if (!ExpectingFlags) {
15897 enum X86::CondCode cc0 = (enum X86::CondCode)N0.getConstantOperandVal(0);
15898 enum X86::CondCode cc1 = (enum X86::CondCode)N1.getConstantOperandVal(0);
15900 if (cc1 == X86::COND_E || cc1 == X86::COND_NE) {
15901 X86::CondCode tmp = cc0;
15906 if ((cc0 == X86::COND_E && cc1 == X86::COND_NP) ||
15907 (cc0 == X86::COND_NE && cc1 == X86::COND_P)) {
15908 bool is64BitFP = (CMP00.getValueType() == MVT::f64);
15909 X86ISD::NodeType NTOperator = is64BitFP ?
15910 X86ISD::FSETCCsd : X86ISD::FSETCCss;
15911 // FIXME: need symbolic constants for these magic numbers.
15912 // See X86ATTInstPrinter.cpp:printSSECC().
15913 unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4;
15914 SDValue OnesOrZeroesF = DAG.getNode(NTOperator, DL, MVT::f32, CMP00, CMP01,
15915 DAG.getConstant(x86cc, MVT::i8));
15916 SDValue OnesOrZeroesI = DAG.getNode(ISD::BITCAST, DL, MVT::i32,
15918 SDValue ANDed = DAG.getNode(ISD::AND, DL, MVT::i32, OnesOrZeroesI,
15919 DAG.getConstant(1, MVT::i32));
15920 SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8, ANDed);
15921 return OneBitOfTruth;
15929 /// CanFoldXORWithAllOnes - Test whether the XOR operand is a AllOnes vector
15930 /// so it can be folded inside ANDNP.
15931 static bool CanFoldXORWithAllOnes(const SDNode *N) {
15932 EVT VT = N->getValueType(0);
15934 // Match direct AllOnes for 128 and 256-bit vectors
15935 if (ISD::isBuildVectorAllOnes(N))
15938 // Look through a bit convert.
15939 if (N->getOpcode() == ISD::BITCAST)
15940 N = N->getOperand(0).getNode();
15942 // Sometimes the operand may come from a insert_subvector building a 256-bit
15944 if (VT.is256BitVector() &&
15945 N->getOpcode() == ISD::INSERT_SUBVECTOR) {
15946 SDValue V1 = N->getOperand(0);
15947 SDValue V2 = N->getOperand(1);
15949 if (V1.getOpcode() == ISD::INSERT_SUBVECTOR &&
15950 V1.getOperand(0).getOpcode() == ISD::UNDEF &&
15951 ISD::isBuildVectorAllOnes(V1.getOperand(1).getNode()) &&
15952 ISD::isBuildVectorAllOnes(V2.getNode()))
15959 // On AVX/AVX2 the type v8i1 is legalized to v8i16, which is an XMM sized
15960 // register. In most cases we actually compare or select YMM-sized registers
15961 // and mixing the two types creates horrible code. This method optimizes
15962 // some of the transition sequences.
15963 static SDValue WidenMaskArithmetic(SDNode *N, SelectionDAG &DAG,
15964 TargetLowering::DAGCombinerInfo &DCI,
15965 const X86Subtarget *Subtarget) {
15966 EVT VT = N->getValueType(0);
15967 if (!VT.is256BitVector())
15970 assert((N->getOpcode() == ISD::ANY_EXTEND ||
15971 N->getOpcode() == ISD::ZERO_EXTEND ||
15972 N->getOpcode() == ISD::SIGN_EXTEND) && "Invalid Node");
15974 SDValue Narrow = N->getOperand(0);
15975 EVT NarrowVT = Narrow->getValueType(0);
15976 if (!NarrowVT.is128BitVector())
15979 if (Narrow->getOpcode() != ISD::XOR &&
15980 Narrow->getOpcode() != ISD::AND &&
15981 Narrow->getOpcode() != ISD::OR)
15984 SDValue N0 = Narrow->getOperand(0);
15985 SDValue N1 = Narrow->getOperand(1);
15986 DebugLoc DL = Narrow->getDebugLoc();
15988 // The Left side has to be a trunc.
15989 if (N0.getOpcode() != ISD::TRUNCATE)
15992 // The type of the truncated inputs.
15993 EVT WideVT = N0->getOperand(0)->getValueType(0);
15997 // The right side has to be a 'trunc' or a constant vector.
15998 bool RHSTrunc = N1.getOpcode() == ISD::TRUNCATE;
15999 bool RHSConst = (isSplatVector(N1.getNode()) &&
16000 isa<ConstantSDNode>(N1->getOperand(0)));
16001 if (!RHSTrunc && !RHSConst)
16004 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
16006 if (!TLI.isOperationLegalOrPromote(Narrow->getOpcode(), WideVT))
16009 // Set N0 and N1 to hold the inputs to the new wide operation.
16010 N0 = N0->getOperand(0);
16012 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, WideVT.getScalarType(),
16013 N1->getOperand(0));
16014 SmallVector<SDValue, 8> C(WideVT.getVectorNumElements(), N1);
16015 N1 = DAG.getNode(ISD::BUILD_VECTOR, DL, WideVT, &C[0], C.size());
16016 } else if (RHSTrunc) {
16017 N1 = N1->getOperand(0);
16020 // Generate the wide operation.
16021 SDValue Op = DAG.getNode(Narrow->getOpcode(), DL, WideVT, N0, N1);
16022 unsigned Opcode = N->getOpcode();
16024 case ISD::ANY_EXTEND:
16026 case ISD::ZERO_EXTEND: {
16027 unsigned InBits = NarrowVT.getScalarType().getSizeInBits();
16028 APInt Mask = APInt::getAllOnesValue(InBits);
16029 Mask = Mask.zext(VT.getScalarType().getSizeInBits());
16030 return DAG.getNode(ISD::AND, DL, VT,
16031 Op, DAG.getConstant(Mask, VT));
16033 case ISD::SIGN_EXTEND:
16034 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT,
16035 Op, DAG.getValueType(NarrowVT));
16037 llvm_unreachable("Unexpected opcode");
16041 static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG,
16042 TargetLowering::DAGCombinerInfo &DCI,
16043 const X86Subtarget *Subtarget) {
16044 EVT VT = N->getValueType(0);
16045 if (DCI.isBeforeLegalizeOps())
16048 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
16052 // Create BLSI, and BLSR instructions
16053 // BLSI is X & (-X)
16054 // BLSR is X & (X-1)
16055 if (Subtarget->hasBMI() && (VT == MVT::i32 || VT == MVT::i64)) {
16056 SDValue N0 = N->getOperand(0);
16057 SDValue N1 = N->getOperand(1);
16058 DebugLoc DL = N->getDebugLoc();
16060 // Check LHS for neg
16061 if (N0.getOpcode() == ISD::SUB && N0.getOperand(1) == N1 &&
16062 isZero(N0.getOperand(0)))
16063 return DAG.getNode(X86ISD::BLSI, DL, VT, N1);
16065 // Check RHS for neg
16066 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1) == N0 &&
16067 isZero(N1.getOperand(0)))
16068 return DAG.getNode(X86ISD::BLSI, DL, VT, N0);
16070 // Check LHS for X-1
16071 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1 &&
16072 isAllOnes(N0.getOperand(1)))
16073 return DAG.getNode(X86ISD::BLSR, DL, VT, N1);
16075 // Check RHS for X-1
16076 if (N1.getOpcode() == ISD::ADD && N1.getOperand(0) == N0 &&
16077 isAllOnes(N1.getOperand(1)))
16078 return DAG.getNode(X86ISD::BLSR, DL, VT, N0);
16083 // Want to form ANDNP nodes:
16084 // 1) In the hopes of then easily combining them with OR and AND nodes
16085 // to form PBLEND/PSIGN.
16086 // 2) To match ANDN packed intrinsics
16087 if (VT != MVT::v2i64 && VT != MVT::v4i64)
16090 SDValue N0 = N->getOperand(0);
16091 SDValue N1 = N->getOperand(1);
16092 DebugLoc DL = N->getDebugLoc();
16094 // Check LHS for vnot
16095 if (N0.getOpcode() == ISD::XOR &&
16096 //ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode()))
16097 CanFoldXORWithAllOnes(N0.getOperand(1).getNode()))
16098 return DAG.getNode(X86ISD::ANDNP, DL, VT, N0.getOperand(0), N1);
16100 // Check RHS for vnot
16101 if (N1.getOpcode() == ISD::XOR &&
16102 //ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode()))
16103 CanFoldXORWithAllOnes(N1.getOperand(1).getNode()))
16104 return DAG.getNode(X86ISD::ANDNP, DL, VT, N1.getOperand(0), N0);
16109 static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
16110 TargetLowering::DAGCombinerInfo &DCI,
16111 const X86Subtarget *Subtarget) {
16112 EVT VT = N->getValueType(0);
16113 if (DCI.isBeforeLegalizeOps())
16116 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
16120 SDValue N0 = N->getOperand(0);
16121 SDValue N1 = N->getOperand(1);
16123 // look for psign/blend
16124 if (VT == MVT::v2i64 || VT == MVT::v4i64) {
16125 if (!Subtarget->hasSSSE3() ||
16126 (VT == MVT::v4i64 && !Subtarget->hasInt256()))
16129 // Canonicalize pandn to RHS
16130 if (N0.getOpcode() == X86ISD::ANDNP)
16132 // or (and (m, y), (pandn m, x))
16133 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::ANDNP) {
16134 SDValue Mask = N1.getOperand(0);
16135 SDValue X = N1.getOperand(1);
16137 if (N0.getOperand(0) == Mask)
16138 Y = N0.getOperand(1);
16139 if (N0.getOperand(1) == Mask)
16140 Y = N0.getOperand(0);
16142 // Check to see if the mask appeared in both the AND and ANDNP and
16146 // Validate that X, Y, and Mask are BIT_CONVERTS, and see through them.
16147 // Look through mask bitcast.
16148 if (Mask.getOpcode() == ISD::BITCAST)
16149 Mask = Mask.getOperand(0);
16150 if (X.getOpcode() == ISD::BITCAST)
16151 X = X.getOperand(0);
16152 if (Y.getOpcode() == ISD::BITCAST)
16153 Y = Y.getOperand(0);
16155 EVT MaskVT = Mask.getValueType();
16157 // Validate that the Mask operand is a vector sra node.
16158 // FIXME: what to do for bytes, since there is a psignb/pblendvb, but
16159 // there is no psrai.b
16160 if (Mask.getOpcode() != X86ISD::VSRAI)
16163 // Check that the SRA is all signbits.
16164 SDValue SraC = Mask.getOperand(1);
16165 unsigned SraAmt = cast<ConstantSDNode>(SraC)->getZExtValue();
16166 unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits();
16167 if ((SraAmt + 1) != EltBits)
16170 DebugLoc DL = N->getDebugLoc();
16172 // We are going to replace the AND, OR, NAND with either BLEND
16173 // or PSIGN, which only look at the MSB. The VSRAI instruction
16174 // does not affect the highest bit, so we can get rid of it.
16175 Mask = Mask.getOperand(0);
16177 // Now we know we at least have a plendvb with the mask val. See if
16178 // we can form a psignb/w/d.
16179 // psign = x.type == y.type == mask.type && y = sub(0, x);
16180 if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X &&
16181 ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) &&
16182 X.getValueType() == MaskVT && Y.getValueType() == MaskVT) {
16183 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
16184 "Unsupported VT for PSIGN");
16185 Mask = DAG.getNode(X86ISD::PSIGN, DL, MaskVT, X, Mask);
16186 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
16188 // PBLENDVB only available on SSE 4.1
16189 if (!Subtarget->hasSSE41())
16192 EVT BlendVT = (VT == MVT::v4i64) ? MVT::v32i8 : MVT::v16i8;
16194 X = DAG.getNode(ISD::BITCAST, DL, BlendVT, X);
16195 Y = DAG.getNode(ISD::BITCAST, DL, BlendVT, Y);
16196 Mask = DAG.getNode(ISD::BITCAST, DL, BlendVT, Mask);
16197 Mask = DAG.getNode(ISD::VSELECT, DL, BlendVT, Mask, Y, X);
16198 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
16202 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64)
16205 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
16206 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
16208 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
16210 if (!N0.hasOneUse() || !N1.hasOneUse())
16213 SDValue ShAmt0 = N0.getOperand(1);
16214 if (ShAmt0.getValueType() != MVT::i8)
16216 SDValue ShAmt1 = N1.getOperand(1);
16217 if (ShAmt1.getValueType() != MVT::i8)
16219 if (ShAmt0.getOpcode() == ISD::TRUNCATE)
16220 ShAmt0 = ShAmt0.getOperand(0);
16221 if (ShAmt1.getOpcode() == ISD::TRUNCATE)
16222 ShAmt1 = ShAmt1.getOperand(0);
16224 DebugLoc DL = N->getDebugLoc();
16225 unsigned Opc = X86ISD::SHLD;
16226 SDValue Op0 = N0.getOperand(0);
16227 SDValue Op1 = N1.getOperand(0);
16228 if (ShAmt0.getOpcode() == ISD::SUB) {
16229 Opc = X86ISD::SHRD;
16230 std::swap(Op0, Op1);
16231 std::swap(ShAmt0, ShAmt1);
16234 unsigned Bits = VT.getSizeInBits();
16235 if (ShAmt1.getOpcode() == ISD::SUB) {
16236 SDValue Sum = ShAmt1.getOperand(0);
16237 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) {
16238 SDValue ShAmt1Op1 = ShAmt1.getOperand(1);
16239 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE)
16240 ShAmt1Op1 = ShAmt1Op1.getOperand(0);
16241 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0)
16242 return DAG.getNode(Opc, DL, VT,
16244 DAG.getNode(ISD::TRUNCATE, DL,
16247 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) {
16248 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0);
16250 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits)
16251 return DAG.getNode(Opc, DL, VT,
16252 N0.getOperand(0), N1.getOperand(0),
16253 DAG.getNode(ISD::TRUNCATE, DL,
16260 // Generate NEG and CMOV for integer abs.
16261 static SDValue performIntegerAbsCombine(SDNode *N, SelectionDAG &DAG) {
16262 EVT VT = N->getValueType(0);
16264 // Since X86 does not have CMOV for 8-bit integer, we don't convert
16265 // 8-bit integer abs to NEG and CMOV.
16266 if (VT.isInteger() && VT.getSizeInBits() == 8)
16269 SDValue N0 = N->getOperand(0);
16270 SDValue N1 = N->getOperand(1);
16271 DebugLoc DL = N->getDebugLoc();
16273 // Check pattern of XOR(ADD(X,Y), Y) where Y is SRA(X, size(X)-1)
16274 // and change it to SUB and CMOV.
16275 if (VT.isInteger() && N->getOpcode() == ISD::XOR &&
16276 N0.getOpcode() == ISD::ADD &&
16277 N0.getOperand(1) == N1 &&
16278 N1.getOpcode() == ISD::SRA &&
16279 N1.getOperand(0) == N0.getOperand(0))
16280 if (ConstantSDNode *Y1C = dyn_cast<ConstantSDNode>(N1.getOperand(1)))
16281 if (Y1C->getAPIntValue() == VT.getSizeInBits()-1) {
16282 // Generate SUB & CMOV.
16283 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, DAG.getVTList(VT, MVT::i32),
16284 DAG.getConstant(0, VT), N0.getOperand(0));
16286 SDValue Ops[] = { N0.getOperand(0), Neg,
16287 DAG.getConstant(X86::COND_GE, MVT::i8),
16288 SDValue(Neg.getNode(), 1) };
16289 return DAG.getNode(X86ISD::CMOV, DL, DAG.getVTList(VT, MVT::Glue),
16290 Ops, array_lengthof(Ops));
16295 // PerformXorCombine - Attempts to turn XOR nodes into BLSMSK nodes
16296 static SDValue PerformXorCombine(SDNode *N, SelectionDAG &DAG,
16297 TargetLowering::DAGCombinerInfo &DCI,
16298 const X86Subtarget *Subtarget) {
16299 EVT VT = N->getValueType(0);
16300 if (DCI.isBeforeLegalizeOps())
16303 if (Subtarget->hasCMov()) {
16304 SDValue RV = performIntegerAbsCombine(N, DAG);
16309 // Try forming BMI if it is available.
16310 if (!Subtarget->hasBMI())
16313 if (VT != MVT::i32 && VT != MVT::i64)
16316 assert(Subtarget->hasBMI() && "Creating BLSMSK requires BMI instructions");
16318 // Create BLSMSK instructions by finding X ^ (X-1)
16319 SDValue N0 = N->getOperand(0);
16320 SDValue N1 = N->getOperand(1);
16321 DebugLoc DL = N->getDebugLoc();
16323 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1 &&
16324 isAllOnes(N0.getOperand(1)))
16325 return DAG.getNode(X86ISD::BLSMSK, DL, VT, N1);
16327 if (N1.getOpcode() == ISD::ADD && N1.getOperand(0) == N0 &&
16328 isAllOnes(N1.getOperand(1)))
16329 return DAG.getNode(X86ISD::BLSMSK, DL, VT, N0);
16334 /// PerformLOADCombine - Do target-specific dag combines on LOAD nodes.
16335 static SDValue PerformLOADCombine(SDNode *N, SelectionDAG &DAG,
16336 TargetLowering::DAGCombinerInfo &DCI,
16337 const X86Subtarget *Subtarget) {
16338 LoadSDNode *Ld = cast<LoadSDNode>(N);
16339 EVT RegVT = Ld->getValueType(0);
16340 EVT MemVT = Ld->getMemoryVT();
16341 DebugLoc dl = Ld->getDebugLoc();
16342 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
16344 ISD::LoadExtType Ext = Ld->getExtensionType();
16346 // If this is a vector EXT Load then attempt to optimize it using a
16347 // shuffle. If SSSE3 is not available we may emit an illegal shuffle but the
16348 // expansion is still better than scalar code.
16349 // We generate X86ISD::VSEXT for SEXTLOADs if it's available, otherwise we'll
16350 // emit a shuffle and a arithmetic shift.
16351 // TODO: It is possible to support ZExt by zeroing the undef values
16352 // during the shuffle phase or after the shuffle.
16353 if (RegVT.isVector() && RegVT.isInteger() && Subtarget->hasSSE2() &&
16354 (Ext == ISD::EXTLOAD || Ext == ISD::SEXTLOAD)) {
16355 assert(MemVT != RegVT && "Cannot extend to the same type");
16356 assert(MemVT.isVector() && "Must load a vector from memory");
16358 unsigned NumElems = RegVT.getVectorNumElements();
16359 unsigned RegSz = RegVT.getSizeInBits();
16360 unsigned MemSz = MemVT.getSizeInBits();
16361 assert(RegSz > MemSz && "Register size must be greater than the mem size");
16363 if (Ext == ISD::SEXTLOAD && RegSz == 256 && !Subtarget->hasInt256())
16366 // All sizes must be a power of two.
16367 if (!isPowerOf2_32(RegSz * MemSz * NumElems))
16370 // Attempt to load the original value using scalar loads.
16371 // Find the largest scalar type that divides the total loaded size.
16372 MVT SclrLoadTy = MVT::i8;
16373 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
16374 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
16375 MVT Tp = (MVT::SimpleValueType)tp;
16376 if (TLI.isTypeLegal(Tp) && ((MemSz % Tp.getSizeInBits()) == 0)) {
16381 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
16382 if (TLI.isTypeLegal(MVT::f64) && SclrLoadTy.getSizeInBits() < 64 &&
16384 SclrLoadTy = MVT::f64;
16386 // Calculate the number of scalar loads that we need to perform
16387 // in order to load our vector from memory.
16388 unsigned NumLoads = MemSz / SclrLoadTy.getSizeInBits();
16389 if (Ext == ISD::SEXTLOAD && NumLoads > 1)
16392 unsigned loadRegZize = RegSz;
16393 if (Ext == ISD::SEXTLOAD && RegSz == 256)
16396 // Represent our vector as a sequence of elements which are the
16397 // largest scalar that we can load.
16398 EVT LoadUnitVecVT = EVT::getVectorVT(*DAG.getContext(), SclrLoadTy,
16399 loadRegZize/SclrLoadTy.getSizeInBits());
16401 // Represent the data using the same element type that is stored in
16402 // memory. In practice, we ''widen'' MemVT.
16404 EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
16405 loadRegZize/MemVT.getScalarType().getSizeInBits());
16407 assert(WideVecVT.getSizeInBits() == LoadUnitVecVT.getSizeInBits() &&
16408 "Invalid vector type");
16410 // We can't shuffle using an illegal type.
16411 if (!TLI.isTypeLegal(WideVecVT))
16414 SmallVector<SDValue, 8> Chains;
16415 SDValue Ptr = Ld->getBasePtr();
16416 SDValue Increment = DAG.getConstant(SclrLoadTy.getSizeInBits()/8,
16417 TLI.getPointerTy());
16418 SDValue Res = DAG.getUNDEF(LoadUnitVecVT);
16420 for (unsigned i = 0; i < NumLoads; ++i) {
16421 // Perform a single load.
16422 SDValue ScalarLoad = DAG.getLoad(SclrLoadTy, dl, Ld->getChain(),
16423 Ptr, Ld->getPointerInfo(),
16424 Ld->isVolatile(), Ld->isNonTemporal(),
16425 Ld->isInvariant(), Ld->getAlignment());
16426 Chains.push_back(ScalarLoad.getValue(1));
16427 // Create the first element type using SCALAR_TO_VECTOR in order to avoid
16428 // another round of DAGCombining.
16430 Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LoadUnitVecVT, ScalarLoad);
16432 Res = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, LoadUnitVecVT, Res,
16433 ScalarLoad, DAG.getIntPtrConstant(i));
16435 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
16438 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0],
16441 // Bitcast the loaded value to a vector of the original element type, in
16442 // the size of the target vector type.
16443 SDValue SlicedVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, Res);
16444 unsigned SizeRatio = RegSz/MemSz;
16446 if (Ext == ISD::SEXTLOAD) {
16447 // If we have SSE4.1 we can directly emit a VSEXT node.
16448 if (Subtarget->hasSSE41()) {
16449 SDValue Sext = DAG.getNode(X86ISD::VSEXT, dl, RegVT, SlicedVec);
16450 return DCI.CombineTo(N, Sext, TF, true);
16453 // Otherwise we'll shuffle the small elements in the high bits of the
16454 // larger type and perform an arithmetic shift. If the shift is not legal
16455 // it's better to scalarize.
16456 if (!TLI.isOperationLegalOrCustom(ISD::SRA, RegVT))
16459 // Redistribute the loaded elements into the different locations.
16460 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
16461 for (unsigned i = 0; i != NumElems; ++i)
16462 ShuffleVec[i*SizeRatio + SizeRatio-1] = i;
16464 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec,
16465 DAG.getUNDEF(WideVecVT),
16468 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
16470 // Build the arithmetic shift.
16471 unsigned Amt = RegVT.getVectorElementType().getSizeInBits() -
16472 MemVT.getVectorElementType().getSizeInBits();
16473 SmallVector<SDValue, 8> C(NumElems,
16474 DAG.getConstant(Amt, RegVT.getScalarType()));
16475 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, RegVT, &C[0], C.size());
16476 Shuff = DAG.getNode(ISD::SRA, dl, RegVT, Shuff, BV);
16478 return DCI.CombineTo(N, Shuff, TF, true);
16481 // Redistribute the loaded elements into the different locations.
16482 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
16483 for (unsigned i = 0; i != NumElems; ++i)
16484 ShuffleVec[i*SizeRatio] = i;
16486 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec,
16487 DAG.getUNDEF(WideVecVT),
16490 // Bitcast to the requested type.
16491 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
16492 // Replace the original load with the new sequence
16493 // and return the new chain.
16494 return DCI.CombineTo(N, Shuff, TF, true);
16500 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
16501 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
16502 const X86Subtarget *Subtarget) {
16503 StoreSDNode *St = cast<StoreSDNode>(N);
16504 EVT VT = St->getValue().getValueType();
16505 EVT StVT = St->getMemoryVT();
16506 DebugLoc dl = St->getDebugLoc();
16507 SDValue StoredVal = St->getOperand(1);
16508 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
16510 // If we are saving a concatenation of two XMM registers, perform two stores.
16511 // On Sandy Bridge, 256-bit memory operations are executed by two
16512 // 128-bit ports. However, on Haswell it is better to issue a single 256-bit
16513 // memory operation.
16514 if (VT.is256BitVector() && !Subtarget->hasInt256() &&
16515 StoredVal.getNode()->getOpcode() == ISD::CONCAT_VECTORS &&
16516 StoredVal.getNumOperands() == 2) {
16517 SDValue Value0 = StoredVal.getOperand(0);
16518 SDValue Value1 = StoredVal.getOperand(1);
16520 SDValue Stride = DAG.getConstant(16, TLI.getPointerTy());
16521 SDValue Ptr0 = St->getBasePtr();
16522 SDValue Ptr1 = DAG.getNode(ISD::ADD, dl, Ptr0.getValueType(), Ptr0, Stride);
16524 SDValue Ch0 = DAG.getStore(St->getChain(), dl, Value0, Ptr0,
16525 St->getPointerInfo(), St->isVolatile(),
16526 St->isNonTemporal(), St->getAlignment());
16527 SDValue Ch1 = DAG.getStore(St->getChain(), dl, Value1, Ptr1,
16528 St->getPointerInfo(), St->isVolatile(),
16529 St->isNonTemporal(), St->getAlignment());
16530 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ch0, Ch1);
16533 // Optimize trunc store (of multiple scalars) to shuffle and store.
16534 // First, pack all of the elements in one place. Next, store to memory
16535 // in fewer chunks.
16536 if (St->isTruncatingStore() && VT.isVector()) {
16537 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
16538 unsigned NumElems = VT.getVectorNumElements();
16539 assert(StVT != VT && "Cannot truncate to the same type");
16540 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
16541 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
16543 // From, To sizes and ElemCount must be pow of two
16544 if (!isPowerOf2_32(NumElems * FromSz * ToSz)) return SDValue();
16545 // We are going to use the original vector elt for storing.
16546 // Accumulated smaller vector elements must be a multiple of the store size.
16547 if (0 != (NumElems * FromSz) % ToSz) return SDValue();
16549 unsigned SizeRatio = FromSz / ToSz;
16551 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
16553 // Create a type on which we perform the shuffle
16554 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
16555 StVT.getScalarType(), NumElems*SizeRatio);
16557 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
16559 SDValue WideVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, St->getValue());
16560 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
16561 for (unsigned i = 0; i != NumElems; ++i)
16562 ShuffleVec[i] = i * SizeRatio;
16564 // Can't shuffle using an illegal type.
16565 if (!TLI.isTypeLegal(WideVecVT))
16568 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
16569 DAG.getUNDEF(WideVecVT),
16571 // At this point all of the data is stored at the bottom of the
16572 // register. We now need to save it to mem.
16574 // Find the largest store unit
16575 MVT StoreType = MVT::i8;
16576 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
16577 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
16578 MVT Tp = (MVT::SimpleValueType)tp;
16579 if (TLI.isTypeLegal(Tp) && Tp.getSizeInBits() <= NumElems * ToSz)
16583 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
16584 if (TLI.isTypeLegal(MVT::f64) && StoreType.getSizeInBits() < 64 &&
16585 (64 <= NumElems * ToSz))
16586 StoreType = MVT::f64;
16588 // Bitcast the original vector into a vector of store-size units
16589 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(),
16590 StoreType, VT.getSizeInBits()/StoreType.getSizeInBits());
16591 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits());
16592 SDValue ShuffWide = DAG.getNode(ISD::BITCAST, dl, StoreVecVT, Shuff);
16593 SmallVector<SDValue, 8> Chains;
16594 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits()/8,
16595 TLI.getPointerTy());
16596 SDValue Ptr = St->getBasePtr();
16598 // Perform one or more big stores into memory.
16599 for (unsigned i=0, e=(ToSz*NumElems)/StoreType.getSizeInBits(); i!=e; ++i) {
16600 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
16601 StoreType, ShuffWide,
16602 DAG.getIntPtrConstant(i));
16603 SDValue Ch = DAG.getStore(St->getChain(), dl, SubVec, Ptr,
16604 St->getPointerInfo(), St->isVolatile(),
16605 St->isNonTemporal(), St->getAlignment());
16606 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
16607 Chains.push_back(Ch);
16610 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0],
16614 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
16615 // the FP state in cases where an emms may be missing.
16616 // A preferable solution to the general problem is to figure out the right
16617 // places to insert EMMS. This qualifies as a quick hack.
16619 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
16620 if (VT.getSizeInBits() != 64)
16623 const Function *F = DAG.getMachineFunction().getFunction();
16624 bool NoImplicitFloatOps = F->getAttributes().
16625 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoImplicitFloat);
16626 bool F64IsLegal = !DAG.getTarget().Options.UseSoftFloat && !NoImplicitFloatOps
16627 && Subtarget->hasSSE2();
16628 if ((VT.isVector() ||
16629 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
16630 isa<LoadSDNode>(St->getValue()) &&
16631 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
16632 St->getChain().hasOneUse() && !St->isVolatile()) {
16633 SDNode* LdVal = St->getValue().getNode();
16634 LoadSDNode *Ld = 0;
16635 int TokenFactorIndex = -1;
16636 SmallVector<SDValue, 8> Ops;
16637 SDNode* ChainVal = St->getChain().getNode();
16638 // Must be a store of a load. We currently handle two cases: the load
16639 // is a direct child, and it's under an intervening TokenFactor. It is
16640 // possible to dig deeper under nested TokenFactors.
16641 if (ChainVal == LdVal)
16642 Ld = cast<LoadSDNode>(St->getChain());
16643 else if (St->getValue().hasOneUse() &&
16644 ChainVal->getOpcode() == ISD::TokenFactor) {
16645 for (unsigned i = 0, e = ChainVal->getNumOperands(); i != e; ++i) {
16646 if (ChainVal->getOperand(i).getNode() == LdVal) {
16647 TokenFactorIndex = i;
16648 Ld = cast<LoadSDNode>(St->getValue());
16650 Ops.push_back(ChainVal->getOperand(i));
16654 if (!Ld || !ISD::isNormalLoad(Ld))
16657 // If this is not the MMX case, i.e. we are just turning i64 load/store
16658 // into f64 load/store, avoid the transformation if there are multiple
16659 // uses of the loaded value.
16660 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
16663 DebugLoc LdDL = Ld->getDebugLoc();
16664 DebugLoc StDL = N->getDebugLoc();
16665 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
16666 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
16668 if (Subtarget->is64Bit() || F64IsLegal) {
16669 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
16670 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(),
16671 Ld->getPointerInfo(), Ld->isVolatile(),
16672 Ld->isNonTemporal(), Ld->isInvariant(),
16673 Ld->getAlignment());
16674 SDValue NewChain = NewLd.getValue(1);
16675 if (TokenFactorIndex != -1) {
16676 Ops.push_back(NewChain);
16677 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
16680 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
16681 St->getPointerInfo(),
16682 St->isVolatile(), St->isNonTemporal(),
16683 St->getAlignment());
16686 // Otherwise, lower to two pairs of 32-bit loads / stores.
16687 SDValue LoAddr = Ld->getBasePtr();
16688 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
16689 DAG.getConstant(4, MVT::i32));
16691 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
16692 Ld->getPointerInfo(),
16693 Ld->isVolatile(), Ld->isNonTemporal(),
16694 Ld->isInvariant(), Ld->getAlignment());
16695 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
16696 Ld->getPointerInfo().getWithOffset(4),
16697 Ld->isVolatile(), Ld->isNonTemporal(),
16699 MinAlign(Ld->getAlignment(), 4));
16701 SDValue NewChain = LoLd.getValue(1);
16702 if (TokenFactorIndex != -1) {
16703 Ops.push_back(LoLd);
16704 Ops.push_back(HiLd);
16705 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
16709 LoAddr = St->getBasePtr();
16710 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
16711 DAG.getConstant(4, MVT::i32));
16713 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
16714 St->getPointerInfo(),
16715 St->isVolatile(), St->isNonTemporal(),
16716 St->getAlignment());
16717 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
16718 St->getPointerInfo().getWithOffset(4),
16720 St->isNonTemporal(),
16721 MinAlign(St->getAlignment(), 4));
16722 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
16727 /// isHorizontalBinOp - Return 'true' if this vector operation is "horizontal"
16728 /// and return the operands for the horizontal operation in LHS and RHS. A
16729 /// horizontal operation performs the binary operation on successive elements
16730 /// of its first operand, then on successive elements of its second operand,
16731 /// returning the resulting values in a vector. For example, if
16732 /// A = < float a0, float a1, float a2, float a3 >
16734 /// B = < float b0, float b1, float b2, float b3 >
16735 /// then the result of doing a horizontal operation on A and B is
16736 /// A horizontal-op B = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >.
16737 /// In short, LHS and RHS are inspected to see if LHS op RHS is of the form
16738 /// A horizontal-op B, for some already available A and B, and if so then LHS is
16739 /// set to A, RHS to B, and the routine returns 'true'.
16740 /// Note that the binary operation should have the property that if one of the
16741 /// operands is UNDEF then the result is UNDEF.
16742 static bool isHorizontalBinOp(SDValue &LHS, SDValue &RHS, bool IsCommutative) {
16743 // Look for the following pattern: if
16744 // A = < float a0, float a1, float a2, float a3 >
16745 // B = < float b0, float b1, float b2, float b3 >
16747 // LHS = VECTOR_SHUFFLE A, B, <0, 2, 4, 6>
16748 // RHS = VECTOR_SHUFFLE A, B, <1, 3, 5, 7>
16749 // then LHS op RHS = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >
16750 // which is A horizontal-op B.
16752 // At least one of the operands should be a vector shuffle.
16753 if (LHS.getOpcode() != ISD::VECTOR_SHUFFLE &&
16754 RHS.getOpcode() != ISD::VECTOR_SHUFFLE)
16757 EVT VT = LHS.getValueType();
16759 assert((VT.is128BitVector() || VT.is256BitVector()) &&
16760 "Unsupported vector type for horizontal add/sub");
16762 // Handle 128 and 256-bit vector lengths. AVX defines horizontal add/sub to
16763 // operate independently on 128-bit lanes.
16764 unsigned NumElts = VT.getVectorNumElements();
16765 unsigned NumLanes = VT.getSizeInBits()/128;
16766 unsigned NumLaneElts = NumElts / NumLanes;
16767 assert((NumLaneElts % 2 == 0) &&
16768 "Vector type should have an even number of elements in each lane");
16769 unsigned HalfLaneElts = NumLaneElts/2;
16771 // View LHS in the form
16772 // LHS = VECTOR_SHUFFLE A, B, LMask
16773 // If LHS is not a shuffle then pretend it is the shuffle
16774 // LHS = VECTOR_SHUFFLE LHS, undef, <0, 1, ..., N-1>
16775 // NOTE: in what follows a default initialized SDValue represents an UNDEF of
16778 SmallVector<int, 16> LMask(NumElts);
16779 if (LHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
16780 if (LHS.getOperand(0).getOpcode() != ISD::UNDEF)
16781 A = LHS.getOperand(0);
16782 if (LHS.getOperand(1).getOpcode() != ISD::UNDEF)
16783 B = LHS.getOperand(1);
16784 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(LHS.getNode())->getMask();
16785 std::copy(Mask.begin(), Mask.end(), LMask.begin());
16787 if (LHS.getOpcode() != ISD::UNDEF)
16789 for (unsigned i = 0; i != NumElts; ++i)
16793 // Likewise, view RHS in the form
16794 // RHS = VECTOR_SHUFFLE C, D, RMask
16796 SmallVector<int, 16> RMask(NumElts);
16797 if (RHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
16798 if (RHS.getOperand(0).getOpcode() != ISD::UNDEF)
16799 C = RHS.getOperand(0);
16800 if (RHS.getOperand(1).getOpcode() != ISD::UNDEF)
16801 D = RHS.getOperand(1);
16802 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(RHS.getNode())->getMask();
16803 std::copy(Mask.begin(), Mask.end(), RMask.begin());
16805 if (RHS.getOpcode() != ISD::UNDEF)
16807 for (unsigned i = 0; i != NumElts; ++i)
16811 // Check that the shuffles are both shuffling the same vectors.
16812 if (!(A == C && B == D) && !(A == D && B == C))
16815 // If everything is UNDEF then bail out: it would be better to fold to UNDEF.
16816 if (!A.getNode() && !B.getNode())
16819 // If A and B occur in reverse order in RHS, then "swap" them (which means
16820 // rewriting the mask).
16822 CommuteVectorShuffleMask(RMask, NumElts);
16824 // At this point LHS and RHS are equivalent to
16825 // LHS = VECTOR_SHUFFLE A, B, LMask
16826 // RHS = VECTOR_SHUFFLE A, B, RMask
16827 // Check that the masks correspond to performing a horizontal operation.
16828 for (unsigned i = 0; i != NumElts; ++i) {
16829 int LIdx = LMask[i], RIdx = RMask[i];
16831 // Ignore any UNDEF components.
16832 if (LIdx < 0 || RIdx < 0 ||
16833 (!A.getNode() && (LIdx < (int)NumElts || RIdx < (int)NumElts)) ||
16834 (!B.getNode() && (LIdx >= (int)NumElts || RIdx >= (int)NumElts)))
16837 // Check that successive elements are being operated on. If not, this is
16838 // not a horizontal operation.
16839 unsigned Src = (i/HalfLaneElts) % 2; // each lane is split between srcs
16840 unsigned LaneStart = (i/NumLaneElts) * NumLaneElts;
16841 int Index = 2*(i%HalfLaneElts) + NumElts*Src + LaneStart;
16842 if (!(LIdx == Index && RIdx == Index + 1) &&
16843 !(IsCommutative && LIdx == Index + 1 && RIdx == Index))
16847 LHS = A.getNode() ? A : B; // If A is 'UNDEF', use B for it.
16848 RHS = B.getNode() ? B : A; // If B is 'UNDEF', use A for it.
16852 /// PerformFADDCombine - Do target-specific dag combines on floating point adds.
16853 static SDValue PerformFADDCombine(SDNode *N, SelectionDAG &DAG,
16854 const X86Subtarget *Subtarget) {
16855 EVT VT = N->getValueType(0);
16856 SDValue LHS = N->getOperand(0);
16857 SDValue RHS = N->getOperand(1);
16859 // Try to synthesize horizontal adds from adds of shuffles.
16860 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
16861 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
16862 isHorizontalBinOp(LHS, RHS, true))
16863 return DAG.getNode(X86ISD::FHADD, N->getDebugLoc(), VT, LHS, RHS);
16867 /// PerformFSUBCombine - Do target-specific dag combines on floating point subs.
16868 static SDValue PerformFSUBCombine(SDNode *N, SelectionDAG &DAG,
16869 const X86Subtarget *Subtarget) {
16870 EVT VT = N->getValueType(0);
16871 SDValue LHS = N->getOperand(0);
16872 SDValue RHS = N->getOperand(1);
16874 // Try to synthesize horizontal subs from subs of shuffles.
16875 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
16876 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
16877 isHorizontalBinOp(LHS, RHS, false))
16878 return DAG.getNode(X86ISD::FHSUB, N->getDebugLoc(), VT, LHS, RHS);
16882 /// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and
16883 /// X86ISD::FXOR nodes.
16884 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
16885 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
16886 // F[X]OR(0.0, x) -> x
16887 // F[X]OR(x, 0.0) -> x
16888 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
16889 if (C->getValueAPF().isPosZero())
16890 return N->getOperand(1);
16891 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
16892 if (C->getValueAPF().isPosZero())
16893 return N->getOperand(0);
16897 /// PerformFMinFMaxCombine - Do target-specific dag combines on X86ISD::FMIN and
16898 /// X86ISD::FMAX nodes.
16899 static SDValue PerformFMinFMaxCombine(SDNode *N, SelectionDAG &DAG) {
16900 assert(N->getOpcode() == X86ISD::FMIN || N->getOpcode() == X86ISD::FMAX);
16902 // Only perform optimizations if UnsafeMath is used.
16903 if (!DAG.getTarget().Options.UnsafeFPMath)
16906 // If we run in unsafe-math mode, then convert the FMAX and FMIN nodes
16907 // into FMINC and FMAXC, which are Commutative operations.
16908 unsigned NewOp = 0;
16909 switch (N->getOpcode()) {
16910 default: llvm_unreachable("unknown opcode");
16911 case X86ISD::FMIN: NewOp = X86ISD::FMINC; break;
16912 case X86ISD::FMAX: NewOp = X86ISD::FMAXC; break;
16915 return DAG.getNode(NewOp, N->getDebugLoc(), N->getValueType(0),
16916 N->getOperand(0), N->getOperand(1));
16919 /// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes.
16920 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
16921 // FAND(0.0, x) -> 0.0
16922 // FAND(x, 0.0) -> 0.0
16923 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
16924 if (C->getValueAPF().isPosZero())
16925 return N->getOperand(0);
16926 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
16927 if (C->getValueAPF().isPosZero())
16928 return N->getOperand(1);
16932 static SDValue PerformBTCombine(SDNode *N,
16934 TargetLowering::DAGCombinerInfo &DCI) {
16935 // BT ignores high bits in the bit index operand.
16936 SDValue Op1 = N->getOperand(1);
16937 if (Op1.hasOneUse()) {
16938 unsigned BitWidth = Op1.getValueSizeInBits();
16939 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
16940 APInt KnownZero, KnownOne;
16941 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
16942 !DCI.isBeforeLegalizeOps());
16943 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
16944 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
16945 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
16946 DCI.CommitTargetLoweringOpt(TLO);
16951 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
16952 SDValue Op = N->getOperand(0);
16953 if (Op.getOpcode() == ISD::BITCAST)
16954 Op = Op.getOperand(0);
16955 EVT VT = N->getValueType(0), OpVT = Op.getValueType();
16956 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
16957 VT.getVectorElementType().getSizeInBits() ==
16958 OpVT.getVectorElementType().getSizeInBits()) {
16959 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), VT, Op);
16964 static SDValue PerformSExtCombine(SDNode *N, SelectionDAG &DAG,
16965 TargetLowering::DAGCombinerInfo &DCI,
16966 const X86Subtarget *Subtarget) {
16967 EVT VT = N->getValueType(0);
16969 if (!VT.isVector())
16972 SDValue In = N->getOperand(0);
16973 EVT InVT = In.getValueType();
16974 DebugLoc dl = N->getDebugLoc();
16975 unsigned ExtendedEltSize = VT.getVectorElementType().getSizeInBits();
16977 // Split SIGN_EXTEND operation to use vmovsx instruction when possible
16978 if (InVT == MVT::v8i8) {
16979 if (ExtendedEltSize > 16 && !Subtarget->hasInt256())
16980 In = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i16, In);
16981 if (ExtendedEltSize > 32)
16982 In = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i32, In);
16983 return DAG.getNode(ISD::SIGN_EXTEND, dl, VT, In);
16986 if ((InVT == MVT::v4i8 || InVT == MVT::v4i16) &&
16987 ExtendedEltSize > 32 && !Subtarget->hasInt256()) {
16988 In = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i32, In);
16989 return DAG.getNode(ISD::SIGN_EXTEND, dl, VT, In);
16992 if (!DCI.isBeforeLegalizeOps())
16995 if (!Subtarget->hasFp256())
16998 if (VT.is256BitVector()) {
16999 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget);
17007 static SDValue PerformFMACombine(SDNode *N, SelectionDAG &DAG,
17008 const X86Subtarget* Subtarget) {
17009 DebugLoc dl = N->getDebugLoc();
17010 EVT VT = N->getValueType(0);
17012 // Let legalize expand this if it isn't a legal type yet.
17013 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
17016 EVT ScalarVT = VT.getScalarType();
17017 if ((ScalarVT != MVT::f32 && ScalarVT != MVT::f64) ||
17018 (!Subtarget->hasFMA() && !Subtarget->hasFMA4()))
17021 SDValue A = N->getOperand(0);
17022 SDValue B = N->getOperand(1);
17023 SDValue C = N->getOperand(2);
17025 bool NegA = (A.getOpcode() == ISD::FNEG);
17026 bool NegB = (B.getOpcode() == ISD::FNEG);
17027 bool NegC = (C.getOpcode() == ISD::FNEG);
17029 // Negative multiplication when NegA xor NegB
17030 bool NegMul = (NegA != NegB);
17032 A = A.getOperand(0);
17034 B = B.getOperand(0);
17036 C = C.getOperand(0);
17040 Opcode = (!NegC) ? X86ISD::FMADD : X86ISD::FMSUB;
17042 Opcode = (!NegC) ? X86ISD::FNMADD : X86ISD::FNMSUB;
17044 return DAG.getNode(Opcode, dl, VT, A, B, C);
17047 static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG,
17048 TargetLowering::DAGCombinerInfo &DCI,
17049 const X86Subtarget *Subtarget) {
17050 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) ->
17051 // (and (i32 x86isd::setcc_carry), 1)
17052 // This eliminates the zext. This transformation is necessary because
17053 // ISD::SETCC is always legalized to i8.
17054 DebugLoc dl = N->getDebugLoc();
17055 SDValue N0 = N->getOperand(0);
17056 EVT VT = N->getValueType(0);
17058 if (N0.getOpcode() == ISD::AND &&
17060 N0.getOperand(0).hasOneUse()) {
17061 SDValue N00 = N0.getOperand(0);
17062 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
17063 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
17064 if (!C || C->getZExtValue() != 1)
17066 return DAG.getNode(ISD::AND, dl, VT,
17067 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
17068 N00.getOperand(0), N00.getOperand(1)),
17069 DAG.getConstant(1, VT));
17073 if (VT.is256BitVector()) {
17074 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget);
17082 // Optimize x == -y --> x+y == 0
17083 // x != -y --> x+y != 0
17084 static SDValue PerformISDSETCCCombine(SDNode *N, SelectionDAG &DAG) {
17085 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
17086 SDValue LHS = N->getOperand(0);
17087 SDValue RHS = N->getOperand(1);
17089 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && LHS.getOpcode() == ISD::SUB)
17090 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(LHS.getOperand(0)))
17091 if (C->getAPIntValue() == 0 && LHS.hasOneUse()) {
17092 SDValue addV = DAG.getNode(ISD::ADD, N->getDebugLoc(),
17093 LHS.getValueType(), RHS, LHS.getOperand(1));
17094 return DAG.getSetCC(N->getDebugLoc(), N->getValueType(0),
17095 addV, DAG.getConstant(0, addV.getValueType()), CC);
17097 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && RHS.getOpcode() == ISD::SUB)
17098 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS.getOperand(0)))
17099 if (C->getAPIntValue() == 0 && RHS.hasOneUse()) {
17100 SDValue addV = DAG.getNode(ISD::ADD, N->getDebugLoc(),
17101 RHS.getValueType(), LHS, RHS.getOperand(1));
17102 return DAG.getSetCC(N->getDebugLoc(), N->getValueType(0),
17103 addV, DAG.getConstant(0, addV.getValueType()), CC);
17108 // Helper function of PerformSETCCCombine. It is to materialize "setb reg"
17109 // as "sbb reg,reg", since it can be extended without zext and produces
17110 // an all-ones bit which is more useful than 0/1 in some cases.
17111 static SDValue MaterializeSETB(DebugLoc DL, SDValue EFLAGS, SelectionDAG &DAG) {
17112 return DAG.getNode(ISD::AND, DL, MVT::i8,
17113 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
17114 DAG.getConstant(X86::COND_B, MVT::i8), EFLAGS),
17115 DAG.getConstant(1, MVT::i8));
17118 // Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT
17119 static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG,
17120 TargetLowering::DAGCombinerInfo &DCI,
17121 const X86Subtarget *Subtarget) {
17122 DebugLoc DL = N->getDebugLoc();
17123 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(0));
17124 SDValue EFLAGS = N->getOperand(1);
17126 if (CC == X86::COND_A) {
17127 // Try to convert COND_A into COND_B in an attempt to facilitate
17128 // materializing "setb reg".
17130 // Do not flip "e > c", where "c" is a constant, because Cmp instruction
17131 // cannot take an immediate as its first operand.
17133 if (EFLAGS.getOpcode() == X86ISD::SUB && EFLAGS.hasOneUse() &&
17134 EFLAGS.getValueType().isInteger() &&
17135 !isa<ConstantSDNode>(EFLAGS.getOperand(1))) {
17136 SDValue NewSub = DAG.getNode(X86ISD::SUB, EFLAGS.getDebugLoc(),
17137 EFLAGS.getNode()->getVTList(),
17138 EFLAGS.getOperand(1), EFLAGS.getOperand(0));
17139 SDValue NewEFLAGS = SDValue(NewSub.getNode(), EFLAGS.getResNo());
17140 return MaterializeSETB(DL, NewEFLAGS, DAG);
17144 // Materialize "setb reg" as "sbb reg,reg", since it can be extended without
17145 // a zext and produces an all-ones bit which is more useful than 0/1 in some
17147 if (CC == X86::COND_B)
17148 return MaterializeSETB(DL, EFLAGS, DAG);
17152 Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
17153 if (Flags.getNode()) {
17154 SDValue Cond = DAG.getConstant(CC, MVT::i8);
17155 return DAG.getNode(X86ISD::SETCC, DL, N->getVTList(), Cond, Flags);
17161 // Optimize branch condition evaluation.
17163 static SDValue PerformBrCondCombine(SDNode *N, SelectionDAG &DAG,
17164 TargetLowering::DAGCombinerInfo &DCI,
17165 const X86Subtarget *Subtarget) {
17166 DebugLoc DL = N->getDebugLoc();
17167 SDValue Chain = N->getOperand(0);
17168 SDValue Dest = N->getOperand(1);
17169 SDValue EFLAGS = N->getOperand(3);
17170 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(2));
17174 Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
17175 if (Flags.getNode()) {
17176 SDValue Cond = DAG.getConstant(CC, MVT::i8);
17177 return DAG.getNode(X86ISD::BRCOND, DL, N->getVTList(), Chain, Dest, Cond,
17184 static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
17185 const X86TargetLowering *XTLI) {
17186 SDValue Op0 = N->getOperand(0);
17187 EVT InVT = Op0->getValueType(0);
17189 // SINT_TO_FP(v4i8) -> SINT_TO_FP(SEXT(v4i8 to v4i32))
17190 if (InVT == MVT::v8i8 || InVT == MVT::v4i8) {
17191 DebugLoc dl = N->getDebugLoc();
17192 MVT DstVT = InVT == MVT::v4i8 ? MVT::v4i32 : MVT::v8i32;
17193 SDValue P = DAG.getNode(ISD::SIGN_EXTEND, dl, DstVT, Op0);
17194 return DAG.getNode(ISD::SINT_TO_FP, dl, N->getValueType(0), P);
17197 // Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have
17198 // a 32-bit target where SSE doesn't support i64->FP operations.
17199 if (Op0.getOpcode() == ISD::LOAD) {
17200 LoadSDNode *Ld = cast<LoadSDNode>(Op0.getNode());
17201 EVT VT = Ld->getValueType(0);
17202 if (!Ld->isVolatile() && !N->getValueType(0).isVector() &&
17203 ISD::isNON_EXTLoad(Op0.getNode()) && Op0.hasOneUse() &&
17204 !XTLI->getSubtarget()->is64Bit() &&
17205 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
17206 SDValue FILDChain = XTLI->BuildFILD(SDValue(N, 0), Ld->getValueType(0),
17207 Ld->getChain(), Op0, DAG);
17208 DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), FILDChain.getValue(1));
17215 // Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS
17216 static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG,
17217 X86TargetLowering::DAGCombinerInfo &DCI) {
17218 // If the LHS and RHS of the ADC node are zero, then it can't overflow and
17219 // the result is either zero or one (depending on the input carry bit).
17220 // Strength reduce this down to a "set on carry" aka SETCC_CARRY&1.
17221 if (X86::isZeroNode(N->getOperand(0)) &&
17222 X86::isZeroNode(N->getOperand(1)) &&
17223 // We don't have a good way to replace an EFLAGS use, so only do this when
17225 SDValue(N, 1).use_empty()) {
17226 DebugLoc DL = N->getDebugLoc();
17227 EVT VT = N->getValueType(0);
17228 SDValue CarryOut = DAG.getConstant(0, N->getValueType(1));
17229 SDValue Res1 = DAG.getNode(ISD::AND, DL, VT,
17230 DAG.getNode(X86ISD::SETCC_CARRY, DL, VT,
17231 DAG.getConstant(X86::COND_B,MVT::i8),
17233 DAG.getConstant(1, VT));
17234 return DCI.CombineTo(N, Res1, CarryOut);
17240 // fold (add Y, (sete X, 0)) -> adc 0, Y
17241 // (add Y, (setne X, 0)) -> sbb -1, Y
17242 // (sub (sete X, 0), Y) -> sbb 0, Y
17243 // (sub (setne X, 0), Y) -> adc -1, Y
17244 static SDValue OptimizeConditionalInDecrement(SDNode *N, SelectionDAG &DAG) {
17245 DebugLoc DL = N->getDebugLoc();
17247 // Look through ZExts.
17248 SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0);
17249 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse())
17252 SDValue SetCC = Ext.getOperand(0);
17253 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse())
17256 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0);
17257 if (CC != X86::COND_E && CC != X86::COND_NE)
17260 SDValue Cmp = SetCC.getOperand(1);
17261 if (Cmp.getOpcode() != X86ISD::CMP || !Cmp.hasOneUse() ||
17262 !X86::isZeroNode(Cmp.getOperand(1)) ||
17263 !Cmp.getOperand(0).getValueType().isInteger())
17266 SDValue CmpOp0 = Cmp.getOperand(0);
17267 SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, CmpOp0,
17268 DAG.getConstant(1, CmpOp0.getValueType()));
17270 SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1);
17271 if (CC == X86::COND_NE)
17272 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB,
17273 DL, OtherVal.getValueType(), OtherVal,
17274 DAG.getConstant(-1ULL, OtherVal.getValueType()), NewCmp);
17275 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC,
17276 DL, OtherVal.getValueType(), OtherVal,
17277 DAG.getConstant(0, OtherVal.getValueType()), NewCmp);
17280 /// PerformADDCombine - Do target-specific dag combines on integer adds.
17281 static SDValue PerformAddCombine(SDNode *N, SelectionDAG &DAG,
17282 const X86Subtarget *Subtarget) {
17283 EVT VT = N->getValueType(0);
17284 SDValue Op0 = N->getOperand(0);
17285 SDValue Op1 = N->getOperand(1);
17287 // Try to synthesize horizontal adds from adds of shuffles.
17288 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
17289 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
17290 isHorizontalBinOp(Op0, Op1, true))
17291 return DAG.getNode(X86ISD::HADD, N->getDebugLoc(), VT, Op0, Op1);
17293 return OptimizeConditionalInDecrement(N, DAG);
17296 static SDValue PerformSubCombine(SDNode *N, SelectionDAG &DAG,
17297 const X86Subtarget *Subtarget) {
17298 SDValue Op0 = N->getOperand(0);
17299 SDValue Op1 = N->getOperand(1);
17301 // X86 can't encode an immediate LHS of a sub. See if we can push the
17302 // negation into a preceding instruction.
17303 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op0)) {
17304 // If the RHS of the sub is a XOR with one use and a constant, invert the
17305 // immediate. Then add one to the LHS of the sub so we can turn
17306 // X-Y -> X+~Y+1, saving one register.
17307 if (Op1->hasOneUse() && Op1.getOpcode() == ISD::XOR &&
17308 isa<ConstantSDNode>(Op1.getOperand(1))) {
17309 APInt XorC = cast<ConstantSDNode>(Op1.getOperand(1))->getAPIntValue();
17310 EVT VT = Op0.getValueType();
17311 SDValue NewXor = DAG.getNode(ISD::XOR, Op1.getDebugLoc(), VT,
17313 DAG.getConstant(~XorC, VT));
17314 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, NewXor,
17315 DAG.getConstant(C->getAPIntValue()+1, VT));
17319 // Try to synthesize horizontal adds from adds of shuffles.
17320 EVT VT = N->getValueType(0);
17321 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
17322 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
17323 isHorizontalBinOp(Op0, Op1, true))
17324 return DAG.getNode(X86ISD::HSUB, N->getDebugLoc(), VT, Op0, Op1);
17326 return OptimizeConditionalInDecrement(N, DAG);
17329 /// performVZEXTCombine - Performs build vector combines
17330 static SDValue performVZEXTCombine(SDNode *N, SelectionDAG &DAG,
17331 TargetLowering::DAGCombinerInfo &DCI,
17332 const X86Subtarget *Subtarget) {
17333 // (vzext (bitcast (vzext (x)) -> (vzext x)
17334 SDValue In = N->getOperand(0);
17335 while (In.getOpcode() == ISD::BITCAST)
17336 In = In.getOperand(0);
17338 if (In.getOpcode() != X86ISD::VZEXT)
17341 return DAG.getNode(X86ISD::VZEXT, N->getDebugLoc(), N->getValueType(0), In.getOperand(0));
17344 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
17345 DAGCombinerInfo &DCI) const {
17346 SelectionDAG &DAG = DCI.DAG;
17347 switch (N->getOpcode()) {
17349 case ISD::EXTRACT_VECTOR_ELT:
17350 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, DCI);
17352 case ISD::SELECT: return PerformSELECTCombine(N, DAG, DCI, Subtarget);
17353 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI, Subtarget);
17354 case ISD::ADD: return PerformAddCombine(N, DAG, Subtarget);
17355 case ISD::SUB: return PerformSubCombine(N, DAG, Subtarget);
17356 case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI);
17357 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
17360 case ISD::SRL: return PerformShiftCombine(N, DAG, DCI, Subtarget);
17361 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget);
17362 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget);
17363 case ISD::XOR: return PerformXorCombine(N, DAG, DCI, Subtarget);
17364 case ISD::LOAD: return PerformLOADCombine(N, DAG, DCI, Subtarget);
17365 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
17366 case ISD::SINT_TO_FP: return PerformSINT_TO_FPCombine(N, DAG, this);
17367 case ISD::FADD: return PerformFADDCombine(N, DAG, Subtarget);
17368 case ISD::FSUB: return PerformFSUBCombine(N, DAG, Subtarget);
17370 case X86ISD::FOR: return PerformFORCombine(N, DAG);
17372 case X86ISD::FMAX: return PerformFMinFMaxCombine(N, DAG);
17373 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
17374 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
17375 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
17376 case ISD::ANY_EXTEND:
17377 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG, DCI, Subtarget);
17378 case ISD::SIGN_EXTEND: return PerformSExtCombine(N, DAG, DCI, Subtarget);
17379 case ISD::TRUNCATE: return PerformTruncateCombine(N, DAG,DCI,Subtarget);
17380 case ISD::SETCC: return PerformISDSETCCCombine(N, DAG);
17381 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG, DCI, Subtarget);
17382 case X86ISD::BRCOND: return PerformBrCondCombine(N, DAG, DCI, Subtarget);
17383 case X86ISD::VZEXT: return performVZEXTCombine(N, DAG, DCI, Subtarget);
17384 case X86ISD::SHUFP: // Handle all target specific shuffles
17385 case X86ISD::PALIGN:
17386 case X86ISD::UNPCKH:
17387 case X86ISD::UNPCKL:
17388 case X86ISD::MOVHLPS:
17389 case X86ISD::MOVLHPS:
17390 case X86ISD::PSHUFD:
17391 case X86ISD::PSHUFHW:
17392 case X86ISD::PSHUFLW:
17393 case X86ISD::MOVSS:
17394 case X86ISD::MOVSD:
17395 case X86ISD::VPERMILP:
17396 case X86ISD::VPERM2X128:
17397 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget);
17398 case ISD::FMA: return PerformFMACombine(N, DAG, Subtarget);
17404 /// isTypeDesirableForOp - Return true if the target has native support for
17405 /// the specified value type and it is 'desirable' to use the type for the
17406 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
17407 /// instruction encodings are longer and some i16 instructions are slow.
17408 bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const {
17409 if (!isTypeLegal(VT))
17411 if (VT != MVT::i16)
17418 case ISD::SIGN_EXTEND:
17419 case ISD::ZERO_EXTEND:
17420 case ISD::ANY_EXTEND:
17433 /// IsDesirableToPromoteOp - This method query the target whether it is
17434 /// beneficial for dag combiner to promote the specified node. If true, it
17435 /// should return the desired promotion type by reference.
17436 bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
17437 EVT VT = Op.getValueType();
17438 if (VT != MVT::i16)
17441 bool Promote = false;
17442 bool Commute = false;
17443 switch (Op.getOpcode()) {
17446 LoadSDNode *LD = cast<LoadSDNode>(Op);
17447 // If the non-extending load has a single use and it's not live out, then it
17448 // might be folded.
17449 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&&
17450 Op.hasOneUse()*/) {
17451 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
17452 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
17453 // The only case where we'd want to promote LOAD (rather then it being
17454 // promoted as an operand is when it's only use is liveout.
17455 if (UI->getOpcode() != ISD::CopyToReg)
17462 case ISD::SIGN_EXTEND:
17463 case ISD::ZERO_EXTEND:
17464 case ISD::ANY_EXTEND:
17469 SDValue N0 = Op.getOperand(0);
17470 // Look out for (store (shl (load), x)).
17471 if (MayFoldLoad(N0) && MayFoldIntoStore(Op))
17484 SDValue N0 = Op.getOperand(0);
17485 SDValue N1 = Op.getOperand(1);
17486 if (!Commute && MayFoldLoad(N1))
17488 // Avoid disabling potential load folding opportunities.
17489 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op)))
17491 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op)))
17501 //===----------------------------------------------------------------------===//
17502 // X86 Inline Assembly Support
17503 //===----------------------------------------------------------------------===//
17506 // Helper to match a string separated by whitespace.
17507 bool matchAsmImpl(StringRef s, ArrayRef<const StringRef *> args) {
17508 s = s.substr(s.find_first_not_of(" \t")); // Skip leading whitespace.
17510 for (unsigned i = 0, e = args.size(); i != e; ++i) {
17511 StringRef piece(*args[i]);
17512 if (!s.startswith(piece)) // Check if the piece matches.
17515 s = s.substr(piece.size());
17516 StringRef::size_type pos = s.find_first_not_of(" \t");
17517 if (pos == 0) // We matched a prefix.
17525 const VariadicFunction1<bool, StringRef, StringRef, matchAsmImpl> matchAsm={};
17528 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
17529 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
17531 std::string AsmStr = IA->getAsmString();
17533 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
17534 if (!Ty || Ty->getBitWidth() % 16 != 0)
17537 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
17538 SmallVector<StringRef, 4> AsmPieces;
17539 SplitString(AsmStr, AsmPieces, ";\n");
17541 switch (AsmPieces.size()) {
17542 default: return false;
17544 // FIXME: this should verify that we are targeting a 486 or better. If not,
17545 // we will turn this bswap into something that will be lowered to logical
17546 // ops instead of emitting the bswap asm. For now, we don't support 486 or
17547 // lower so don't worry about this.
17549 if (matchAsm(AsmPieces[0], "bswap", "$0") ||
17550 matchAsm(AsmPieces[0], "bswapl", "$0") ||
17551 matchAsm(AsmPieces[0], "bswapq", "$0") ||
17552 matchAsm(AsmPieces[0], "bswap", "${0:q}") ||
17553 matchAsm(AsmPieces[0], "bswapl", "${0:q}") ||
17554 matchAsm(AsmPieces[0], "bswapq", "${0:q}")) {
17555 // No need to check constraints, nothing other than the equivalent of
17556 // "=r,0" would be valid here.
17557 return IntrinsicLowering::LowerToByteSwap(CI);
17560 // rorw $$8, ${0:w} --> llvm.bswap.i16
17561 if (CI->getType()->isIntegerTy(16) &&
17562 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
17563 (matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") ||
17564 matchAsm(AsmPieces[0], "rolw", "$$8,", "${0:w}"))) {
17566 const std::string &ConstraintsStr = IA->getConstraintString();
17567 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
17568 std::sort(AsmPieces.begin(), AsmPieces.end());
17569 if (AsmPieces.size() == 4 &&
17570 AsmPieces[0] == "~{cc}" &&
17571 AsmPieces[1] == "~{dirflag}" &&
17572 AsmPieces[2] == "~{flags}" &&
17573 AsmPieces[3] == "~{fpsr}")
17574 return IntrinsicLowering::LowerToByteSwap(CI);
17578 if (CI->getType()->isIntegerTy(32) &&
17579 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
17580 matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") &&
17581 matchAsm(AsmPieces[1], "rorl", "$$16,", "$0") &&
17582 matchAsm(AsmPieces[2], "rorw", "$$8,", "${0:w}")) {
17584 const std::string &ConstraintsStr = IA->getConstraintString();
17585 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
17586 std::sort(AsmPieces.begin(), AsmPieces.end());
17587 if (AsmPieces.size() == 4 &&
17588 AsmPieces[0] == "~{cc}" &&
17589 AsmPieces[1] == "~{dirflag}" &&
17590 AsmPieces[2] == "~{flags}" &&
17591 AsmPieces[3] == "~{fpsr}")
17592 return IntrinsicLowering::LowerToByteSwap(CI);
17595 if (CI->getType()->isIntegerTy(64)) {
17596 InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints();
17597 if (Constraints.size() >= 2 &&
17598 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
17599 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
17600 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
17601 if (matchAsm(AsmPieces[0], "bswap", "%eax") &&
17602 matchAsm(AsmPieces[1], "bswap", "%edx") &&
17603 matchAsm(AsmPieces[2], "xchgl", "%eax,", "%edx"))
17604 return IntrinsicLowering::LowerToByteSwap(CI);
17612 /// getConstraintType - Given a constraint letter, return the type of
17613 /// constraint it is for this target.
17614 X86TargetLowering::ConstraintType
17615 X86TargetLowering::getConstraintType(const std::string &Constraint) const {
17616 if (Constraint.size() == 1) {
17617 switch (Constraint[0]) {
17628 return C_RegisterClass;
17652 return TargetLowering::getConstraintType(Constraint);
17655 /// Examine constraint type and operand type and determine a weight value.
17656 /// This object must already have been set up with the operand type
17657 /// and the current alternative constraint selected.
17658 TargetLowering::ConstraintWeight
17659 X86TargetLowering::getSingleConstraintMatchWeight(
17660 AsmOperandInfo &info, const char *constraint) const {
17661 ConstraintWeight weight = CW_Invalid;
17662 Value *CallOperandVal = info.CallOperandVal;
17663 // If we don't have a value, we can't do a match,
17664 // but allow it at the lowest weight.
17665 if (CallOperandVal == NULL)
17667 Type *type = CallOperandVal->getType();
17668 // Look at the constraint type.
17669 switch (*constraint) {
17671 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
17682 if (CallOperandVal->getType()->isIntegerTy())
17683 weight = CW_SpecificReg;
17688 if (type->isFloatingPointTy())
17689 weight = CW_SpecificReg;
17692 if (type->isX86_MMXTy() && Subtarget->hasMMX())
17693 weight = CW_SpecificReg;
17697 if (((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasSSE1()) ||
17698 ((type->getPrimitiveSizeInBits() == 256) && Subtarget->hasFp256()))
17699 weight = CW_Register;
17702 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) {
17703 if (C->getZExtValue() <= 31)
17704 weight = CW_Constant;
17708 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
17709 if (C->getZExtValue() <= 63)
17710 weight = CW_Constant;
17714 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
17715 if ((C->getSExtValue() >= -0x80) && (C->getSExtValue() <= 0x7f))
17716 weight = CW_Constant;
17720 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
17721 if ((C->getZExtValue() == 0xff) || (C->getZExtValue() == 0xffff))
17722 weight = CW_Constant;
17726 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
17727 if (C->getZExtValue() <= 3)
17728 weight = CW_Constant;
17732 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
17733 if (C->getZExtValue() <= 0xff)
17734 weight = CW_Constant;
17739 if (dyn_cast<ConstantFP>(CallOperandVal)) {
17740 weight = CW_Constant;
17744 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
17745 if ((C->getSExtValue() >= -0x80000000LL) &&
17746 (C->getSExtValue() <= 0x7fffffffLL))
17747 weight = CW_Constant;
17751 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
17752 if (C->getZExtValue() <= 0xffffffff)
17753 weight = CW_Constant;
17760 /// LowerXConstraint - try to replace an X constraint, which matches anything,
17761 /// with another that has more specific requirements based on the type of the
17762 /// corresponding operand.
17763 const char *X86TargetLowering::
17764 LowerXConstraint(EVT ConstraintVT) const {
17765 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
17766 // 'f' like normal targets.
17767 if (ConstraintVT.isFloatingPoint()) {
17768 if (Subtarget->hasSSE2())
17770 if (Subtarget->hasSSE1())
17774 return TargetLowering::LowerXConstraint(ConstraintVT);
17777 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
17778 /// vector. If it is invalid, don't add anything to Ops.
17779 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
17780 std::string &Constraint,
17781 std::vector<SDValue>&Ops,
17782 SelectionDAG &DAG) const {
17783 SDValue Result(0, 0);
17785 // Only support length 1 constraints for now.
17786 if (Constraint.length() > 1) return;
17788 char ConstraintLetter = Constraint[0];
17789 switch (ConstraintLetter) {
17792 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
17793 if (C->getZExtValue() <= 31) {
17794 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
17800 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
17801 if (C->getZExtValue() <= 63) {
17802 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
17808 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
17809 if (isInt<8>(C->getSExtValue())) {
17810 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
17816 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
17817 if (C->getZExtValue() <= 255) {
17818 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
17824 // 32-bit signed value
17825 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
17826 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
17827 C->getSExtValue())) {
17828 // Widen to 64 bits here to get it sign extended.
17829 Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64);
17832 // FIXME gcc accepts some relocatable values here too, but only in certain
17833 // memory models; it's complicated.
17838 // 32-bit unsigned value
17839 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
17840 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
17841 C->getZExtValue())) {
17842 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
17846 // FIXME gcc accepts some relocatable values here too, but only in certain
17847 // memory models; it's complicated.
17851 // Literal immediates are always ok.
17852 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
17853 // Widen to 64 bits here to get it sign extended.
17854 Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64);
17858 // In any sort of PIC mode addresses need to be computed at runtime by
17859 // adding in a register or some sort of table lookup. These can't
17860 // be used as immediates.
17861 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC())
17864 // If we are in non-pic codegen mode, we allow the address of a global (with
17865 // an optional displacement) to be used with 'i'.
17866 GlobalAddressSDNode *GA = 0;
17867 int64_t Offset = 0;
17869 // Match either (GA), (GA+C), (GA+C1+C2), etc.
17871 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
17872 Offset += GA->getOffset();
17874 } else if (Op.getOpcode() == ISD::ADD) {
17875 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
17876 Offset += C->getZExtValue();
17877 Op = Op.getOperand(0);
17880 } else if (Op.getOpcode() == ISD::SUB) {
17881 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
17882 Offset += -C->getZExtValue();
17883 Op = Op.getOperand(0);
17888 // Otherwise, this isn't something we can handle, reject it.
17892 const GlobalValue *GV = GA->getGlobal();
17893 // If we require an extra load to get this address, as in PIC mode, we
17894 // can't accept it.
17895 if (isGlobalStubReference(Subtarget->ClassifyGlobalReference(GV,
17896 getTargetMachine())))
17899 Result = DAG.getTargetGlobalAddress(GV, Op.getDebugLoc(),
17900 GA->getValueType(0), Offset);
17905 if (Result.getNode()) {
17906 Ops.push_back(Result);
17909 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
17912 std::pair<unsigned, const TargetRegisterClass*>
17913 X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
17915 // First, see if this is a constraint that directly corresponds to an LLVM
17917 if (Constraint.size() == 1) {
17918 // GCC Constraint Letters
17919 switch (Constraint[0]) {
17921 // TODO: Slight differences here in allocation order and leaving
17922 // RIP in the class. Do they matter any more here than they do
17923 // in the normal allocation?
17924 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
17925 if (Subtarget->is64Bit()) {
17926 if (VT == MVT::i32 || VT == MVT::f32)
17927 return std::make_pair(0U, &X86::GR32RegClass);
17928 if (VT == MVT::i16)
17929 return std::make_pair(0U, &X86::GR16RegClass);
17930 if (VT == MVT::i8 || VT == MVT::i1)
17931 return std::make_pair(0U, &X86::GR8RegClass);
17932 if (VT == MVT::i64 || VT == MVT::f64)
17933 return std::make_pair(0U, &X86::GR64RegClass);
17936 // 32-bit fallthrough
17937 case 'Q': // Q_REGS
17938 if (VT == MVT::i32 || VT == MVT::f32)
17939 return std::make_pair(0U, &X86::GR32_ABCDRegClass);
17940 if (VT == MVT::i16)
17941 return std::make_pair(0U, &X86::GR16_ABCDRegClass);
17942 if (VT == MVT::i8 || VT == MVT::i1)
17943 return std::make_pair(0U, &X86::GR8_ABCD_LRegClass);
17944 if (VT == MVT::i64)
17945 return std::make_pair(0U, &X86::GR64_ABCDRegClass);
17947 case 'r': // GENERAL_REGS
17948 case 'l': // INDEX_REGS
17949 if (VT == MVT::i8 || VT == MVT::i1)
17950 return std::make_pair(0U, &X86::GR8RegClass);
17951 if (VT == MVT::i16)
17952 return std::make_pair(0U, &X86::GR16RegClass);
17953 if (VT == MVT::i32 || VT == MVT::f32 || !Subtarget->is64Bit())
17954 return std::make_pair(0U, &X86::GR32RegClass);
17955 return std::make_pair(0U, &X86::GR64RegClass);
17956 case 'R': // LEGACY_REGS
17957 if (VT == MVT::i8 || VT == MVT::i1)
17958 return std::make_pair(0U, &X86::GR8_NOREXRegClass);
17959 if (VT == MVT::i16)
17960 return std::make_pair(0U, &X86::GR16_NOREXRegClass);
17961 if (VT == MVT::i32 || !Subtarget->is64Bit())
17962 return std::make_pair(0U, &X86::GR32_NOREXRegClass);
17963 return std::make_pair(0U, &X86::GR64_NOREXRegClass);
17964 case 'f': // FP Stack registers.
17965 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
17966 // value to the correct fpstack register class.
17967 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
17968 return std::make_pair(0U, &X86::RFP32RegClass);
17969 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
17970 return std::make_pair(0U, &X86::RFP64RegClass);
17971 return std::make_pair(0U, &X86::RFP80RegClass);
17972 case 'y': // MMX_REGS if MMX allowed.
17973 if (!Subtarget->hasMMX()) break;
17974 return std::make_pair(0U, &X86::VR64RegClass);
17975 case 'Y': // SSE_REGS if SSE2 allowed
17976 if (!Subtarget->hasSSE2()) break;
17978 case 'x': // SSE_REGS if SSE1 allowed or AVX_REGS if AVX allowed
17979 if (!Subtarget->hasSSE1()) break;
17981 switch (VT.getSimpleVT().SimpleTy) {
17983 // Scalar SSE types.
17986 return std::make_pair(0U, &X86::FR32RegClass);
17989 return std::make_pair(0U, &X86::FR64RegClass);
17997 return std::make_pair(0U, &X86::VR128RegClass);
18005 return std::make_pair(0U, &X86::VR256RegClass);
18011 // Use the default implementation in TargetLowering to convert the register
18012 // constraint into a member of a register class.
18013 std::pair<unsigned, const TargetRegisterClass*> Res;
18014 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
18016 // Not found as a standard register?
18017 if (Res.second == 0) {
18018 // Map st(0) -> st(7) -> ST0
18019 if (Constraint.size() == 7 && Constraint[0] == '{' &&
18020 tolower(Constraint[1]) == 's' &&
18021 tolower(Constraint[2]) == 't' &&
18022 Constraint[3] == '(' &&
18023 (Constraint[4] >= '0' && Constraint[4] <= '7') &&
18024 Constraint[5] == ')' &&
18025 Constraint[6] == '}') {
18027 Res.first = X86::ST0+Constraint[4]-'0';
18028 Res.second = &X86::RFP80RegClass;
18032 // GCC allows "st(0)" to be called just plain "st".
18033 if (StringRef("{st}").equals_lower(Constraint)) {
18034 Res.first = X86::ST0;
18035 Res.second = &X86::RFP80RegClass;
18040 if (StringRef("{flags}").equals_lower(Constraint)) {
18041 Res.first = X86::EFLAGS;
18042 Res.second = &X86::CCRRegClass;
18046 // 'A' means EAX + EDX.
18047 if (Constraint == "A") {
18048 Res.first = X86::EAX;
18049 Res.second = &X86::GR32_ADRegClass;
18055 // Otherwise, check to see if this is a register class of the wrong value
18056 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
18057 // turn into {ax},{dx}.
18058 if (Res.second->hasType(VT))
18059 return Res; // Correct type already, nothing to do.
18061 // All of the single-register GCC register classes map their values onto
18062 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
18063 // really want an 8-bit or 32-bit register, map to the appropriate register
18064 // class and return the appropriate register.
18065 if (Res.second == &X86::GR16RegClass) {
18066 if (VT == MVT::i8) {
18067 unsigned DestReg = 0;
18068 switch (Res.first) {
18070 case X86::AX: DestReg = X86::AL; break;
18071 case X86::DX: DestReg = X86::DL; break;
18072 case X86::CX: DestReg = X86::CL; break;
18073 case X86::BX: DestReg = X86::BL; break;
18076 Res.first = DestReg;
18077 Res.second = &X86::GR8RegClass;
18079 } else if (VT == MVT::i32) {
18080 unsigned DestReg = 0;
18081 switch (Res.first) {
18083 case X86::AX: DestReg = X86::EAX; break;
18084 case X86::DX: DestReg = X86::EDX; break;
18085 case X86::CX: DestReg = X86::ECX; break;
18086 case X86::BX: DestReg = X86::EBX; break;
18087 case X86::SI: DestReg = X86::ESI; break;
18088 case X86::DI: DestReg = X86::EDI; break;
18089 case X86::BP: DestReg = X86::EBP; break;
18090 case X86::SP: DestReg = X86::ESP; break;
18093 Res.first = DestReg;
18094 Res.second = &X86::GR32RegClass;
18096 } else if (VT == MVT::i64) {
18097 unsigned DestReg = 0;
18098 switch (Res.first) {
18100 case X86::AX: DestReg = X86::RAX; break;
18101 case X86::DX: DestReg = X86::RDX; break;
18102 case X86::CX: DestReg = X86::RCX; break;
18103 case X86::BX: DestReg = X86::RBX; break;
18104 case X86::SI: DestReg = X86::RSI; break;
18105 case X86::DI: DestReg = X86::RDI; break;
18106 case X86::BP: DestReg = X86::RBP; break;
18107 case X86::SP: DestReg = X86::RSP; break;
18110 Res.first = DestReg;
18111 Res.second = &X86::GR64RegClass;
18114 } else if (Res.second == &X86::FR32RegClass ||
18115 Res.second == &X86::FR64RegClass ||
18116 Res.second == &X86::VR128RegClass) {
18117 // Handle references to XMM physical registers that got mapped into the
18118 // wrong class. This can happen with constraints like {xmm0} where the
18119 // target independent register mapper will just pick the first match it can
18120 // find, ignoring the required type.
18122 if (VT == MVT::f32 || VT == MVT::i32)
18123 Res.second = &X86::FR32RegClass;
18124 else if (VT == MVT::f64 || VT == MVT::i64)
18125 Res.second = &X86::FR64RegClass;
18126 else if (X86::VR128RegClass.hasType(VT))
18127 Res.second = &X86::VR128RegClass;
18128 else if (X86::VR256RegClass.hasType(VT))
18129 Res.second = &X86::VR256RegClass;