1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
16 #include "X86InstrBuilder.h"
17 #include "X86ISelLowering.h"
18 #include "X86MachineFunctionInfo.h"
19 #include "X86TargetMachine.h"
20 #include "llvm/CallingConv.h"
21 #include "llvm/Constants.h"
22 #include "llvm/DerivedTypes.h"
23 #include "llvm/GlobalVariable.h"
24 #include "llvm/Function.h"
25 #include "llvm/Intrinsics.h"
26 #include "llvm/ADT/BitVector.h"
27 #include "llvm/ADT/VectorExtras.h"
28 #include "llvm/CodeGen/CallingConvLower.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineFunction.h"
31 #include "llvm/CodeGen/MachineInstrBuilder.h"
32 #include "llvm/CodeGen/MachineModuleInfo.h"
33 #include "llvm/CodeGen/MachineRegisterInfo.h"
34 #include "llvm/CodeGen/PseudoSourceValue.h"
35 #include "llvm/CodeGen/SelectionDAG.h"
36 #include "llvm/Support/MathExtras.h"
37 #include "llvm/Support/Debug.h"
38 #include "llvm/Target/TargetOptions.h"
39 #include "llvm/ADT/SmallSet.h"
40 #include "llvm/ADT/StringExtras.h"
41 #include "llvm/Support/CommandLine.h"
45 DisableMMX("disable-mmx", cl::Hidden, cl::desc("Disable use of MMX"));
47 // Forward declarations.
48 static SDValue getMOVLMask(unsigned NumElems, SelectionDAG &DAG, DebugLoc dl);
50 X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
51 : TargetLowering(TM) {
52 Subtarget = &TM.getSubtarget<X86Subtarget>();
53 X86ScalarSSEf64 = Subtarget->hasSSE2();
54 X86ScalarSSEf32 = Subtarget->hasSSE1();
55 X86StackPtr = Subtarget->is64Bit() ? X86::RSP : X86::ESP;
59 RegInfo = TM.getRegisterInfo();
62 // Set up the TargetLowering object.
64 // X86 is weird, it always uses i8 for shift amounts and setcc results.
65 setShiftAmountType(MVT::i8);
66 setBooleanContents(ZeroOrOneBooleanContent);
67 setSchedulingPreference(SchedulingForRegPressure);
68 setShiftAmountFlavor(Mask); // shl X, 32 == shl X, 0
69 setStackPointerRegisterToSaveRestore(X86StackPtr);
71 if (Subtarget->isTargetDarwin()) {
72 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
73 setUseUnderscoreSetJmp(false);
74 setUseUnderscoreLongJmp(false);
75 } else if (Subtarget->isTargetMingw()) {
76 // MS runtime is weird: it exports _setjmp, but longjmp!
77 setUseUnderscoreSetJmp(true);
78 setUseUnderscoreLongJmp(false);
80 setUseUnderscoreSetJmp(true);
81 setUseUnderscoreLongJmp(true);
84 // Set up the register classes.
85 addRegisterClass(MVT::i8, X86::GR8RegisterClass);
86 addRegisterClass(MVT::i16, X86::GR16RegisterClass);
87 addRegisterClass(MVT::i32, X86::GR32RegisterClass);
88 if (Subtarget->is64Bit())
89 addRegisterClass(MVT::i64, X86::GR64RegisterClass);
91 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
93 // We don't accept any truncstore of integer registers.
94 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
95 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
96 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
97 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
98 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
99 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
101 // SETOEQ and SETUNE require checking two conditions.
102 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
103 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
104 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
105 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
106 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
107 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
109 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
111 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
112 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
113 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
115 if (Subtarget->is64Bit()) {
116 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Expand);
117 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
119 if (X86ScalarSSEf64) {
120 // We have an impenetrably clever algorithm for ui64->double only.
121 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
123 // We have faster algorithm for ui32->single only.
124 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
126 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
129 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
131 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
132 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
133 // SSE has no i16 to fp conversion, only i32
134 if (X86ScalarSSEf32) {
135 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
136 // f32 and f64 cases are Legal, f80 case is not
137 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
139 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
140 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
143 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
144 // are Legal, f80 is custom lowered.
145 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
146 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
148 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
150 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
151 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
153 if (X86ScalarSSEf32) {
154 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
155 // f32 and f64 cases are Legal, f80 case is not
156 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
158 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
159 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
162 // Handle FP_TO_UINT by promoting the destination to a larger signed
164 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
165 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
166 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
168 if (Subtarget->is64Bit()) {
169 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
170 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
172 if (X86ScalarSSEf32 && !Subtarget->hasSSE3())
173 // Expand FP_TO_UINT into a select.
174 // FIXME: We would like to use a Custom expander here eventually to do
175 // the optimal thing for SSE vs. the default expansion in the legalizer.
176 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
178 // With SSE3 we can use fisttpll to convert to a signed i64.
179 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
182 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
183 if (!X86ScalarSSEf64) {
184 setOperationAction(ISD::BIT_CONVERT , MVT::f32 , Expand);
185 setOperationAction(ISD::BIT_CONVERT , MVT::i32 , Expand);
188 // Scalar integer divide and remainder are lowered to use operations that
189 // produce two results, to match the available instructions. This exposes
190 // the two-result form to trivial CSE, which is able to combine x/y and x%y
191 // into a single instruction.
193 // Scalar integer multiply-high is also lowered to use two-result
194 // operations, to match the available instructions. However, plain multiply
195 // (low) operations are left as Legal, as there are single-result
196 // instructions for this in x86. Using the two-result multiply instructions
197 // when both high and low results are needed must be arranged by dagcombine.
198 setOperationAction(ISD::MULHS , MVT::i8 , Expand);
199 setOperationAction(ISD::MULHU , MVT::i8 , Expand);
200 setOperationAction(ISD::SDIV , MVT::i8 , Expand);
201 setOperationAction(ISD::UDIV , MVT::i8 , Expand);
202 setOperationAction(ISD::SREM , MVT::i8 , Expand);
203 setOperationAction(ISD::UREM , MVT::i8 , Expand);
204 setOperationAction(ISD::MULHS , MVT::i16 , Expand);
205 setOperationAction(ISD::MULHU , MVT::i16 , Expand);
206 setOperationAction(ISD::SDIV , MVT::i16 , Expand);
207 setOperationAction(ISD::UDIV , MVT::i16 , Expand);
208 setOperationAction(ISD::SREM , MVT::i16 , Expand);
209 setOperationAction(ISD::UREM , MVT::i16 , Expand);
210 setOperationAction(ISD::MULHS , MVT::i32 , Expand);
211 setOperationAction(ISD::MULHU , MVT::i32 , Expand);
212 setOperationAction(ISD::SDIV , MVT::i32 , Expand);
213 setOperationAction(ISD::UDIV , MVT::i32 , Expand);
214 setOperationAction(ISD::SREM , MVT::i32 , Expand);
215 setOperationAction(ISD::UREM , MVT::i32 , Expand);
216 setOperationAction(ISD::MULHS , MVT::i64 , Expand);
217 setOperationAction(ISD::MULHU , MVT::i64 , Expand);
218 setOperationAction(ISD::SDIV , MVT::i64 , Expand);
219 setOperationAction(ISD::UDIV , MVT::i64 , Expand);
220 setOperationAction(ISD::SREM , MVT::i64 , Expand);
221 setOperationAction(ISD::UREM , MVT::i64 , Expand);
223 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
224 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
225 setOperationAction(ISD::BR_CC , MVT::Other, Expand);
226 setOperationAction(ISD::SELECT_CC , MVT::Other, Expand);
227 if (Subtarget->is64Bit())
228 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
229 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
230 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
231 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
232 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
233 setOperationAction(ISD::FREM , MVT::f32 , Expand);
234 setOperationAction(ISD::FREM , MVT::f64 , Expand);
235 setOperationAction(ISD::FREM , MVT::f80 , Expand);
236 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
238 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
239 setOperationAction(ISD::CTTZ , MVT::i8 , Custom);
240 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
241 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
242 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
243 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
244 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
245 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
246 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
247 if (Subtarget->is64Bit()) {
248 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
249 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
250 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
253 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
254 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
256 // These should be promoted to a larger select which is supported.
257 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
258 setOperationAction(ISD::SELECT , MVT::i8 , Promote);
259 // X86 wants to expand cmov itself.
260 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
261 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
262 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
263 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
264 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
265 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
266 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
267 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
268 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
269 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
270 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
271 if (Subtarget->is64Bit()) {
272 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
273 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
275 // X86 ret instruction may pop stack.
276 setOperationAction(ISD::RET , MVT::Other, Custom);
277 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
280 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
281 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
282 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
283 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
284 if (Subtarget->is64Bit())
285 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
286 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
287 if (Subtarget->is64Bit()) {
288 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
289 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
290 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
291 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
293 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
294 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
295 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
296 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
297 if (Subtarget->is64Bit()) {
298 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
299 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
300 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
303 if (Subtarget->hasSSE1())
304 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
306 if (!Subtarget->hasSSE2())
307 setOperationAction(ISD::MEMBARRIER , MVT::Other, Expand);
309 // Expand certain atomics
310 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i8, Custom);
311 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i16, Custom);
312 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Custom);
313 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i64, Custom);
315 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i8, Custom);
316 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i16, Custom);
317 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i32, Custom);
318 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom);
320 if (!Subtarget->is64Bit()) {
321 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i64, Custom);
322 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom);
323 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i64, Custom);
324 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i64, Custom);
325 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i64, Custom);
326 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i64, Custom);
327 setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Custom);
330 // Use the default ISD::DBG_STOPPOINT, ISD::DECLARE expansion.
331 setOperationAction(ISD::DBG_STOPPOINT, MVT::Other, Expand);
332 // FIXME - use subtarget debug flags
333 if (!Subtarget->isTargetDarwin() &&
334 !Subtarget->isTargetELF() &&
335 !Subtarget->isTargetCygMing()) {
336 setOperationAction(ISD::DBG_LABEL, MVT::Other, Expand);
337 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
340 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand);
341 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand);
342 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
343 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
344 if (Subtarget->is64Bit()) {
345 setExceptionPointerRegister(X86::RAX);
346 setExceptionSelectorRegister(X86::RDX);
348 setExceptionPointerRegister(X86::EAX);
349 setExceptionSelectorRegister(X86::EDX);
351 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
352 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
354 setOperationAction(ISD::TRAMPOLINE, MVT::Other, Custom);
356 setOperationAction(ISD::TRAP, MVT::Other, Legal);
358 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
359 setOperationAction(ISD::VASTART , MVT::Other, Custom);
360 setOperationAction(ISD::VAEND , MVT::Other, Expand);
361 if (Subtarget->is64Bit()) {
362 setOperationAction(ISD::VAARG , MVT::Other, Custom);
363 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
365 setOperationAction(ISD::VAARG , MVT::Other, Expand);
366 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
369 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
370 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
371 if (Subtarget->is64Bit())
372 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand);
373 if (Subtarget->isTargetCygMing())
374 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom);
376 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
378 if (!UseSoftFloat && X86ScalarSSEf64) {
379 // f32 and f64 use SSE.
380 // Set up the FP register classes.
381 addRegisterClass(MVT::f32, X86::FR32RegisterClass);
382 addRegisterClass(MVT::f64, X86::FR64RegisterClass);
384 // Use ANDPD to simulate FABS.
385 setOperationAction(ISD::FABS , MVT::f64, Custom);
386 setOperationAction(ISD::FABS , MVT::f32, Custom);
388 // Use XORP to simulate FNEG.
389 setOperationAction(ISD::FNEG , MVT::f64, Custom);
390 setOperationAction(ISD::FNEG , MVT::f32, Custom);
392 // Use ANDPD and ORPD to simulate FCOPYSIGN.
393 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
394 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
396 // We don't support sin/cos/fmod
397 setOperationAction(ISD::FSIN , MVT::f64, Expand);
398 setOperationAction(ISD::FCOS , MVT::f64, Expand);
399 setOperationAction(ISD::FSIN , MVT::f32, Expand);
400 setOperationAction(ISD::FCOS , MVT::f32, Expand);
402 // Expand FP immediates into loads from the stack, except for the special
404 addLegalFPImmediate(APFloat(+0.0)); // xorpd
405 addLegalFPImmediate(APFloat(+0.0f)); // xorps
407 // Floating truncations from f80 and extensions to f80 go through memory.
408 // If optimizing, we lie about this though and handle it in
409 // InstructionSelectPreprocess so that dagcombine2 can hack on these.
411 setConvertAction(MVT::f32, MVT::f80, Expand);
412 setConvertAction(MVT::f64, MVT::f80, Expand);
413 setConvertAction(MVT::f80, MVT::f32, Expand);
414 setConvertAction(MVT::f80, MVT::f64, Expand);
416 } else if (!UseSoftFloat && X86ScalarSSEf32) {
417 // Use SSE for f32, x87 for f64.
418 // Set up the FP register classes.
419 addRegisterClass(MVT::f32, X86::FR32RegisterClass);
420 addRegisterClass(MVT::f64, X86::RFP64RegisterClass);
422 // Use ANDPS to simulate FABS.
423 setOperationAction(ISD::FABS , MVT::f32, Custom);
425 // Use XORP to simulate FNEG.
426 setOperationAction(ISD::FNEG , MVT::f32, Custom);
428 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
430 // Use ANDPS and ORPS to simulate FCOPYSIGN.
431 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
432 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
434 // We don't support sin/cos/fmod
435 setOperationAction(ISD::FSIN , MVT::f32, Expand);
436 setOperationAction(ISD::FCOS , MVT::f32, Expand);
438 // Special cases we handle for FP constants.
439 addLegalFPImmediate(APFloat(+0.0f)); // xorps
440 addLegalFPImmediate(APFloat(+0.0)); // FLD0
441 addLegalFPImmediate(APFloat(+1.0)); // FLD1
442 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
443 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
445 // SSE <-> X87 conversions go through memory. If optimizing, we lie about
446 // this though and handle it in InstructionSelectPreprocess so that
447 // dagcombine2 can hack on these.
449 setConvertAction(MVT::f32, MVT::f64, Expand);
450 setConvertAction(MVT::f32, MVT::f80, Expand);
451 setConvertAction(MVT::f80, MVT::f32, Expand);
452 setConvertAction(MVT::f64, MVT::f32, Expand);
453 // And x87->x87 truncations also.
454 setConvertAction(MVT::f80, MVT::f64, Expand);
458 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
459 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
461 } else if (!UseSoftFloat) {
462 // f32 and f64 in x87.
463 // Set up the FP register classes.
464 addRegisterClass(MVT::f64, X86::RFP64RegisterClass);
465 addRegisterClass(MVT::f32, X86::RFP32RegisterClass);
467 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
468 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
469 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
470 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
472 // Floating truncations go through memory. If optimizing, we lie about
473 // this though and handle it in InstructionSelectPreprocess so that
474 // dagcombine2 can hack on these.
476 setConvertAction(MVT::f80, MVT::f32, Expand);
477 setConvertAction(MVT::f64, MVT::f32, Expand);
478 setConvertAction(MVT::f80, MVT::f64, Expand);
482 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
483 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
485 addLegalFPImmediate(APFloat(+0.0)); // FLD0
486 addLegalFPImmediate(APFloat(+1.0)); // FLD1
487 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
488 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
489 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
490 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
491 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
492 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
495 // Long double always uses X87.
497 addRegisterClass(MVT::f80, X86::RFP80RegisterClass);
498 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
499 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
502 APFloat TmpFlt(+0.0);
503 TmpFlt.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
505 addLegalFPImmediate(TmpFlt); // FLD0
507 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
508 APFloat TmpFlt2(+1.0);
509 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
511 addLegalFPImmediate(TmpFlt2); // FLD1
512 TmpFlt2.changeSign();
513 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
517 setOperationAction(ISD::FSIN , MVT::f80 , Expand);
518 setOperationAction(ISD::FCOS , MVT::f80 , Expand);
522 // Always use a library call for pow.
523 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
524 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
525 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
527 setOperationAction(ISD::FLOG, MVT::f80, Expand);
528 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
529 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
530 setOperationAction(ISD::FEXP, MVT::f80, Expand);
531 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
533 // First set operation action for all vector types to either promote
534 // (for widening) or expand (for scalarization). Then we will selectively
535 // turn on ones that can be effectively codegen'd.
536 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
537 VT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) {
538 setOperationAction(ISD::ADD , (MVT::SimpleValueType)VT, Expand);
539 setOperationAction(ISD::SUB , (MVT::SimpleValueType)VT, Expand);
540 setOperationAction(ISD::FADD, (MVT::SimpleValueType)VT, Expand);
541 setOperationAction(ISD::FNEG, (MVT::SimpleValueType)VT, Expand);
542 setOperationAction(ISD::FSUB, (MVT::SimpleValueType)VT, Expand);
543 setOperationAction(ISD::MUL , (MVT::SimpleValueType)VT, Expand);
544 setOperationAction(ISD::FMUL, (MVT::SimpleValueType)VT, Expand);
545 setOperationAction(ISD::SDIV, (MVT::SimpleValueType)VT, Expand);
546 setOperationAction(ISD::UDIV, (MVT::SimpleValueType)VT, Expand);
547 setOperationAction(ISD::FDIV, (MVT::SimpleValueType)VT, Expand);
548 setOperationAction(ISD::SREM, (MVT::SimpleValueType)VT, Expand);
549 setOperationAction(ISD::UREM, (MVT::SimpleValueType)VT, Expand);
550 setOperationAction(ISD::LOAD, (MVT::SimpleValueType)VT, Expand);
551 setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::SimpleValueType)VT, Expand);
552 setOperationAction(ISD::EXTRACT_VECTOR_ELT,(MVT::SimpleValueType)VT,Expand);
553 setOperationAction(ISD::INSERT_VECTOR_ELT,(MVT::SimpleValueType)VT, Expand);
554 setOperationAction(ISD::FABS, (MVT::SimpleValueType)VT, Expand);
555 setOperationAction(ISD::FSIN, (MVT::SimpleValueType)VT, Expand);
556 setOperationAction(ISD::FCOS, (MVT::SimpleValueType)VT, Expand);
557 setOperationAction(ISD::FREM, (MVT::SimpleValueType)VT, Expand);
558 setOperationAction(ISD::FPOWI, (MVT::SimpleValueType)VT, Expand);
559 setOperationAction(ISD::FSQRT, (MVT::SimpleValueType)VT, Expand);
560 setOperationAction(ISD::FCOPYSIGN, (MVT::SimpleValueType)VT, Expand);
561 setOperationAction(ISD::SMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
562 setOperationAction(ISD::UMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
563 setOperationAction(ISD::SDIVREM, (MVT::SimpleValueType)VT, Expand);
564 setOperationAction(ISD::UDIVREM, (MVT::SimpleValueType)VT, Expand);
565 setOperationAction(ISD::FPOW, (MVT::SimpleValueType)VT, Expand);
566 setOperationAction(ISD::CTPOP, (MVT::SimpleValueType)VT, Expand);
567 setOperationAction(ISD::CTTZ, (MVT::SimpleValueType)VT, Expand);
568 setOperationAction(ISD::CTLZ, (MVT::SimpleValueType)VT, Expand);
569 setOperationAction(ISD::SHL, (MVT::SimpleValueType)VT, Expand);
570 setOperationAction(ISD::SRA, (MVT::SimpleValueType)VT, Expand);
571 setOperationAction(ISD::SRL, (MVT::SimpleValueType)VT, Expand);
572 setOperationAction(ISD::ROTL, (MVT::SimpleValueType)VT, Expand);
573 setOperationAction(ISD::ROTR, (MVT::SimpleValueType)VT, Expand);
574 setOperationAction(ISD::BSWAP, (MVT::SimpleValueType)VT, Expand);
575 setOperationAction(ISD::VSETCC, (MVT::SimpleValueType)VT, Expand);
576 setOperationAction(ISD::FLOG, (MVT::SimpleValueType)VT, Expand);
577 setOperationAction(ISD::FLOG2, (MVT::SimpleValueType)VT, Expand);
578 setOperationAction(ISD::FLOG10, (MVT::SimpleValueType)VT, Expand);
579 setOperationAction(ISD::FEXP, (MVT::SimpleValueType)VT, Expand);
580 setOperationAction(ISD::FEXP2, (MVT::SimpleValueType)VT, Expand);
583 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
584 // with -msoft-float, disable use of MMX as well.
585 if (!UseSoftFloat && !DisableMMX && Subtarget->hasMMX()) {
586 addRegisterClass(MVT::v8i8, X86::VR64RegisterClass);
587 addRegisterClass(MVT::v4i16, X86::VR64RegisterClass);
588 addRegisterClass(MVT::v2i32, X86::VR64RegisterClass);
589 addRegisterClass(MVT::v2f32, X86::VR64RegisterClass);
590 addRegisterClass(MVT::v1i64, X86::VR64RegisterClass);
592 setOperationAction(ISD::ADD, MVT::v8i8, Legal);
593 setOperationAction(ISD::ADD, MVT::v4i16, Legal);
594 setOperationAction(ISD::ADD, MVT::v2i32, Legal);
595 setOperationAction(ISD::ADD, MVT::v1i64, Legal);
597 setOperationAction(ISD::SUB, MVT::v8i8, Legal);
598 setOperationAction(ISD::SUB, MVT::v4i16, Legal);
599 setOperationAction(ISD::SUB, MVT::v2i32, Legal);
600 setOperationAction(ISD::SUB, MVT::v1i64, Legal);
602 setOperationAction(ISD::MULHS, MVT::v4i16, Legal);
603 setOperationAction(ISD::MUL, MVT::v4i16, Legal);
605 setOperationAction(ISD::AND, MVT::v8i8, Promote);
606 AddPromotedToType (ISD::AND, MVT::v8i8, MVT::v1i64);
607 setOperationAction(ISD::AND, MVT::v4i16, Promote);
608 AddPromotedToType (ISD::AND, MVT::v4i16, MVT::v1i64);
609 setOperationAction(ISD::AND, MVT::v2i32, Promote);
610 AddPromotedToType (ISD::AND, MVT::v2i32, MVT::v1i64);
611 setOperationAction(ISD::AND, MVT::v1i64, Legal);
613 setOperationAction(ISD::OR, MVT::v8i8, Promote);
614 AddPromotedToType (ISD::OR, MVT::v8i8, MVT::v1i64);
615 setOperationAction(ISD::OR, MVT::v4i16, Promote);
616 AddPromotedToType (ISD::OR, MVT::v4i16, MVT::v1i64);
617 setOperationAction(ISD::OR, MVT::v2i32, Promote);
618 AddPromotedToType (ISD::OR, MVT::v2i32, MVT::v1i64);
619 setOperationAction(ISD::OR, MVT::v1i64, Legal);
621 setOperationAction(ISD::XOR, MVT::v8i8, Promote);
622 AddPromotedToType (ISD::XOR, MVT::v8i8, MVT::v1i64);
623 setOperationAction(ISD::XOR, MVT::v4i16, Promote);
624 AddPromotedToType (ISD::XOR, MVT::v4i16, MVT::v1i64);
625 setOperationAction(ISD::XOR, MVT::v2i32, Promote);
626 AddPromotedToType (ISD::XOR, MVT::v2i32, MVT::v1i64);
627 setOperationAction(ISD::XOR, MVT::v1i64, Legal);
629 setOperationAction(ISD::LOAD, MVT::v8i8, Promote);
630 AddPromotedToType (ISD::LOAD, MVT::v8i8, MVT::v1i64);
631 setOperationAction(ISD::LOAD, MVT::v4i16, Promote);
632 AddPromotedToType (ISD::LOAD, MVT::v4i16, MVT::v1i64);
633 setOperationAction(ISD::LOAD, MVT::v2i32, Promote);
634 AddPromotedToType (ISD::LOAD, MVT::v2i32, MVT::v1i64);
635 setOperationAction(ISD::LOAD, MVT::v2f32, Promote);
636 AddPromotedToType (ISD::LOAD, MVT::v2f32, MVT::v1i64);
637 setOperationAction(ISD::LOAD, MVT::v1i64, Legal);
639 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i8, Custom);
640 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i16, Custom);
641 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i32, Custom);
642 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f32, Custom);
643 setOperationAction(ISD::BUILD_VECTOR, MVT::v1i64, Custom);
645 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i8, Custom);
646 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i16, Custom);
647 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i32, Custom);
648 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v1i64, Custom);
650 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2f32, Custom);
651 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Custom);
652 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Custom);
653 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Custom);
655 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i16, Custom);
657 setTruncStoreAction(MVT::v8i16, MVT::v8i8, Expand);
658 setOperationAction(ISD::TRUNCATE, MVT::v8i8, Expand);
659 setOperationAction(ISD::SELECT, MVT::v8i8, Promote);
660 setOperationAction(ISD::SELECT, MVT::v4i16, Promote);
661 setOperationAction(ISD::SELECT, MVT::v2i32, Promote);
662 setOperationAction(ISD::SELECT, MVT::v1i64, Custom);
665 if (!UseSoftFloat && Subtarget->hasSSE1()) {
666 addRegisterClass(MVT::v4f32, X86::VR128RegisterClass);
668 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
669 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
670 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
671 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
672 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
673 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
674 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
675 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
676 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
677 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
678 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
679 setOperationAction(ISD::VSETCC, MVT::v4f32, Custom);
682 if (!UseSoftFloat && Subtarget->hasSSE2()) {
683 addRegisterClass(MVT::v2f64, X86::VR128RegisterClass);
685 // FIXME: Unfortunately -soft-float means XMM registers cannot be used even
686 // for integer operations.
687 addRegisterClass(MVT::v16i8, X86::VR128RegisterClass);
688 addRegisterClass(MVT::v8i16, X86::VR128RegisterClass);
689 addRegisterClass(MVT::v4i32, X86::VR128RegisterClass);
690 addRegisterClass(MVT::v2i64, X86::VR128RegisterClass);
692 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
693 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
694 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
695 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
696 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
697 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
698 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
699 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
700 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
701 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
702 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
703 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
704 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
705 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
706 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
707 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
709 setOperationAction(ISD::VSETCC, MVT::v2f64, Custom);
710 setOperationAction(ISD::VSETCC, MVT::v16i8, Custom);
711 setOperationAction(ISD::VSETCC, MVT::v8i16, Custom);
712 setOperationAction(ISD::VSETCC, MVT::v4i32, Custom);
714 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
715 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
716 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
717 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
718 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
720 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
721 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; ++i) {
722 MVT VT = (MVT::SimpleValueType)i;
723 // Do not attempt to custom lower non-power-of-2 vectors
724 if (!isPowerOf2_32(VT.getVectorNumElements()))
726 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
727 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
728 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
730 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
731 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
732 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
733 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
734 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
735 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
736 if (Subtarget->is64Bit()) {
737 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
738 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
741 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
742 for (unsigned VT = (unsigned)MVT::v16i8; VT != (unsigned)MVT::v2i64; VT++) {
743 setOperationAction(ISD::AND, (MVT::SimpleValueType)VT, Promote);
744 AddPromotedToType (ISD::AND, (MVT::SimpleValueType)VT, MVT::v2i64);
745 setOperationAction(ISD::OR, (MVT::SimpleValueType)VT, Promote);
746 AddPromotedToType (ISD::OR, (MVT::SimpleValueType)VT, MVT::v2i64);
747 setOperationAction(ISD::XOR, (MVT::SimpleValueType)VT, Promote);
748 AddPromotedToType (ISD::XOR, (MVT::SimpleValueType)VT, MVT::v2i64);
749 setOperationAction(ISD::LOAD, (MVT::SimpleValueType)VT, Promote);
750 AddPromotedToType (ISD::LOAD, (MVT::SimpleValueType)VT, MVT::v2i64);
751 setOperationAction(ISD::SELECT, (MVT::SimpleValueType)VT, Promote);
752 AddPromotedToType (ISD::SELECT, (MVT::SimpleValueType)VT, MVT::v2i64);
755 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
757 // Custom lower v2i64 and v2f64 selects.
758 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
759 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
760 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
761 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
765 if (Subtarget->hasSSE41()) {
766 // FIXME: Do we need to handle scalar-to-vector here?
767 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
769 // i8 and i16 vectors are custom , because the source register and source
770 // source memory operand types are not the same width. f32 vectors are
771 // custom since the immediate controlling the insert encodes additional
773 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
774 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
775 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
776 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
778 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
779 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
780 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
781 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
783 if (Subtarget->is64Bit()) {
784 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Legal);
785 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Legal);
789 if (Subtarget->hasSSE42()) {
790 setOperationAction(ISD::VSETCC, MVT::v2i64, Custom);
793 // We want to custom lower some of our intrinsics.
794 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
796 // Add/Sub/Mul with overflow operations are custom lowered.
797 setOperationAction(ISD::SADDO, MVT::i32, Custom);
798 setOperationAction(ISD::SADDO, MVT::i64, Custom);
799 setOperationAction(ISD::UADDO, MVT::i32, Custom);
800 setOperationAction(ISD::UADDO, MVT::i64, Custom);
801 setOperationAction(ISD::SSUBO, MVT::i32, Custom);
802 setOperationAction(ISD::SSUBO, MVT::i64, Custom);
803 setOperationAction(ISD::USUBO, MVT::i32, Custom);
804 setOperationAction(ISD::USUBO, MVT::i64, Custom);
805 setOperationAction(ISD::SMULO, MVT::i32, Custom);
806 setOperationAction(ISD::SMULO, MVT::i64, Custom);
807 setOperationAction(ISD::UMULO, MVT::i32, Custom);
808 setOperationAction(ISD::UMULO, MVT::i64, Custom);
810 // We have target-specific dag combine patterns for the following nodes:
811 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
812 setTargetDAGCombine(ISD::BUILD_VECTOR);
813 setTargetDAGCombine(ISD::SELECT);
814 setTargetDAGCombine(ISD::SHL);
815 setTargetDAGCombine(ISD::SRA);
816 setTargetDAGCombine(ISD::SRL);
817 setTargetDAGCombine(ISD::STORE);
819 computeRegisterProperties();
821 // FIXME: These should be based on subtarget info. Plus, the values should
822 // be smaller when we are in optimizing for size mode.
823 maxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
824 maxStoresPerMemcpy = 16; // For @llvm.memcpy -> sequence of stores
825 maxStoresPerMemmove = 3; // For @llvm.memmove -> sequence of stores
826 allowUnalignedMemoryAccesses = true; // x86 supports it!
827 setPrefLoopAlignment(16);
831 MVT X86TargetLowering::getSetCCResultType(MVT VT) const {
836 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
837 /// the desired ByVal argument alignment.
838 static void getMaxByValAlign(const Type *Ty, unsigned &MaxAlign) {
841 if (const VectorType *VTy = dyn_cast<VectorType>(Ty)) {
842 if (VTy->getBitWidth() == 128)
844 } else if (const ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
845 unsigned EltAlign = 0;
846 getMaxByValAlign(ATy->getElementType(), EltAlign);
847 if (EltAlign > MaxAlign)
849 } else if (const StructType *STy = dyn_cast<StructType>(Ty)) {
850 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
851 unsigned EltAlign = 0;
852 getMaxByValAlign(STy->getElementType(i), EltAlign);
853 if (EltAlign > MaxAlign)
862 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
863 /// function arguments in the caller parameter area. For X86, aggregates
864 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
865 /// are at 4-byte boundaries.
866 unsigned X86TargetLowering::getByValTypeAlignment(const Type *Ty) const {
867 if (Subtarget->is64Bit()) {
868 // Max of 8 and alignment of type.
869 unsigned TyAlign = TD->getABITypeAlignment(Ty);
876 if (Subtarget->hasSSE1())
877 getMaxByValAlign(Ty, Align);
881 /// getOptimalMemOpType - Returns the target specific optimal type for load
882 /// and store operations as a result of memset, memcpy, and memmove
883 /// lowering. It returns MVT::iAny if SelectionDAG should be responsible for
886 X86TargetLowering::getOptimalMemOpType(uint64_t Size, unsigned Align,
887 bool isSrcConst, bool isSrcStr) const {
888 // FIXME: This turns off use of xmm stores for memset/memcpy on targets like
889 // linux. This is because the stack realignment code can't handle certain
890 // cases like PR2962. This should be removed when PR2962 is fixed.
891 if (Subtarget->getStackAlignment() >= 16) {
892 if ((isSrcConst || isSrcStr) && Subtarget->hasSSE2() && Size >= 16)
894 if ((isSrcConst || isSrcStr) && Subtarget->hasSSE1() && Size >= 16)
897 if (Subtarget->is64Bit() && Size >= 8)
903 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
905 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
906 SelectionDAG &DAG) const {
907 if (usesGlobalOffsetTable())
908 return DAG.getGLOBAL_OFFSET_TABLE(getPointerTy());
909 if (!Subtarget->isPICStyleRIPRel())
910 // This doesn't have DebugLoc associated with it, but is not really the
911 // same as a Register.
912 return DAG.getNode(X86ISD::GlobalBaseReg, DebugLoc::getUnknownLoc(),
917 //===----------------------------------------------------------------------===//
918 // Return Value Calling Convention Implementation
919 //===----------------------------------------------------------------------===//
921 #include "X86GenCallingConv.inc"
923 /// LowerRET - Lower an ISD::RET node.
924 SDValue X86TargetLowering::LowerRET(SDValue Op, SelectionDAG &DAG) {
925 DebugLoc dl = Op.getDebugLoc();
926 assert((Op.getNumOperands() & 1) == 1 && "ISD::RET should have odd # args");
928 SmallVector<CCValAssign, 16> RVLocs;
929 unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv();
930 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
931 CCState CCInfo(CC, isVarArg, getTargetMachine(), RVLocs);
932 CCInfo.AnalyzeReturn(Op.getNode(), RetCC_X86);
934 // If this is the first return lowered for this function, add the regs to the
935 // liveout set for the function.
936 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
937 for (unsigned i = 0; i != RVLocs.size(); ++i)
938 if (RVLocs[i].isRegLoc())
939 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
941 SDValue Chain = Op.getOperand(0);
943 // Handle tail call return.
944 Chain = GetPossiblePreceedingTailCall(Chain, X86ISD::TAILCALL);
945 if (Chain.getOpcode() == X86ISD::TAILCALL) {
946 SDValue TailCall = Chain;
947 SDValue TargetAddress = TailCall.getOperand(1);
948 SDValue StackAdjustment = TailCall.getOperand(2);
949 assert(((TargetAddress.getOpcode() == ISD::Register &&
950 (cast<RegisterSDNode>(TargetAddress)->getReg() == X86::EAX ||
951 cast<RegisterSDNode>(TargetAddress)->getReg() == X86::R9)) ||
952 TargetAddress.getOpcode() == ISD::TargetExternalSymbol ||
953 TargetAddress.getOpcode() == ISD::TargetGlobalAddress) &&
954 "Expecting an global address, external symbol, or register");
955 assert(StackAdjustment.getOpcode() == ISD::Constant &&
956 "Expecting a const value");
958 SmallVector<SDValue,8> Operands;
959 Operands.push_back(Chain.getOperand(0));
960 Operands.push_back(TargetAddress);
961 Operands.push_back(StackAdjustment);
962 // Copy registers used by the call. Last operand is a flag so it is not
964 for (unsigned i=3; i < TailCall.getNumOperands()-1; i++) {
965 Operands.push_back(Chain.getOperand(i));
967 return DAG.getNode(X86ISD::TC_RETURN, dl, MVT::Other, &Operands[0],
974 SmallVector<SDValue, 6> RetOps;
975 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
976 // Operand #1 = Bytes To Pop
977 RetOps.push_back(DAG.getConstant(getBytesToPopOnReturn(), MVT::i16));
979 // Copy the result values into the output registers.
980 for (unsigned i = 0; i != RVLocs.size(); ++i) {
981 CCValAssign &VA = RVLocs[i];
982 assert(VA.isRegLoc() && "Can only return in registers!");
983 SDValue ValToCopy = Op.getOperand(i*2+1);
985 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
986 // the RET instruction and handled by the FP Stackifier.
987 if (VA.getLocReg() == X86::ST0 ||
988 VA.getLocReg() == X86::ST1) {
989 // If this is a copy from an xmm register to ST(0), use an FPExtend to
990 // change the value to the FP stack register class.
991 if (isScalarFPTypeInSSEReg(VA.getValVT()))
992 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
993 RetOps.push_back(ValToCopy);
994 // Don't emit a copytoreg.
998 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
999 // which is returned in RAX / RDX.
1000 if (Subtarget->is64Bit()) {
1001 MVT ValVT = ValToCopy.getValueType();
1002 if (ValVT.isVector() && ValVT.getSizeInBits() == 64) {
1003 ValToCopy = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i64, ValToCopy);
1004 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1)
1005 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, ValToCopy);
1009 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
1010 Flag = Chain.getValue(1);
1013 // The x86-64 ABI for returning structs by value requires that we copy
1014 // the sret argument into %rax for the return. We saved the argument into
1015 // a virtual register in the entry block, so now we copy the value out
1017 if (Subtarget->is64Bit() &&
1018 DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
1019 MachineFunction &MF = DAG.getMachineFunction();
1020 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1021 unsigned Reg = FuncInfo->getSRetReturnReg();
1023 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64));
1024 FuncInfo->setSRetReturnReg(Reg);
1026 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
1028 Chain = DAG.getCopyToReg(Chain, dl, X86::RAX, Val, Flag);
1029 Flag = Chain.getValue(1);
1032 RetOps[0] = Chain; // Update chain.
1034 // Add the flag if we have it.
1036 RetOps.push_back(Flag);
1038 return DAG.getNode(X86ISD::RET_FLAG, dl,
1039 MVT::Other, &RetOps[0], RetOps.size());
1043 /// LowerCallResult - Lower the result values of an ISD::CALL into the
1044 /// appropriate copies out of appropriate physical registers. This assumes that
1045 /// Chain/InFlag are the input chain/flag to use, and that TheCall is the call
1046 /// being lowered. The returns a SDNode with the same number of values as the
1048 SDNode *X86TargetLowering::
1049 LowerCallResult(SDValue Chain, SDValue InFlag, CallSDNode *TheCall,
1050 unsigned CallingConv, SelectionDAG &DAG) {
1052 DebugLoc dl = TheCall->getDebugLoc();
1053 // Assign locations to each value returned by this call.
1054 SmallVector<CCValAssign, 16> RVLocs;
1055 bool isVarArg = TheCall->isVarArg();
1056 bool Is64Bit = Subtarget->is64Bit();
1057 CCState CCInfo(CallingConv, isVarArg, getTargetMachine(), RVLocs);
1058 CCInfo.AnalyzeCallResult(TheCall, RetCC_X86);
1060 SmallVector<SDValue, 8> ResultVals;
1062 // Copy all of the result registers out of their specified physreg.
1063 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1064 CCValAssign &VA = RVLocs[i];
1065 MVT CopyVT = VA.getValVT();
1067 // If this is x86-64, and we disabled SSE, we can't return FP values
1068 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
1069 ((Is64Bit || TheCall->isInreg()) && !Subtarget->hasSSE1())) {
1070 cerr << "SSE register return with SSE disabled\n";
1074 // If this is a call to a function that returns an fp value on the floating
1075 // point stack, but where we prefer to use the value in xmm registers, copy
1076 // it out as F80 and use a truncate to move it from fp stack reg to xmm reg.
1077 if ((VA.getLocReg() == X86::ST0 ||
1078 VA.getLocReg() == X86::ST1) &&
1079 isScalarFPTypeInSSEReg(VA.getValVT())) {
1084 if (Is64Bit && CopyVT.isVector() && CopyVT.getSizeInBits() == 64) {
1085 // For x86-64, MMX values are returned in XMM0 / XMM1 except for v1i64.
1086 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
1087 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
1088 MVT::v2i64, InFlag).getValue(1);
1089 Val = Chain.getValue(0);
1090 Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64,
1091 Val, DAG.getConstant(0, MVT::i64));
1093 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
1094 MVT::i64, InFlag).getValue(1);
1095 Val = Chain.getValue(0);
1097 Val = DAG.getNode(ISD::BIT_CONVERT, dl, CopyVT, Val);
1099 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
1100 CopyVT, InFlag).getValue(1);
1101 Val = Chain.getValue(0);
1103 InFlag = Chain.getValue(2);
1105 if (CopyVT != VA.getValVT()) {
1106 // Round the F80 the right size, which also moves to the appropriate xmm
1108 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
1109 // This truncation won't change the value.
1110 DAG.getIntPtrConstant(1));
1113 ResultVals.push_back(Val);
1116 // Merge everything together with a MERGE_VALUES node.
1117 ResultVals.push_back(Chain);
1118 return DAG.getNode(ISD::MERGE_VALUES, dl, TheCall->getVTList(),
1119 &ResultVals[0], ResultVals.size()).getNode();
1123 //===----------------------------------------------------------------------===//
1124 // C & StdCall & Fast Calling Convention implementation
1125 //===----------------------------------------------------------------------===//
1126 // StdCall calling convention seems to be standard for many Windows' API
1127 // routines and around. It differs from C calling convention just a little:
1128 // callee should clean up the stack, not caller. Symbols should be also
1129 // decorated in some fancy way :) It doesn't support any vector arguments.
1130 // For info on fast calling convention see Fast Calling Convention (tail call)
1131 // implementation LowerX86_32FastCCCallTo.
1133 /// AddLiveIn - This helper function adds the specified physical register to the
1134 /// MachineFunction as a live in value. It also creates a corresponding virtual
1135 /// register for it.
1136 static unsigned AddLiveIn(MachineFunction &MF, unsigned PReg,
1137 const TargetRegisterClass *RC) {
1138 assert(RC->contains(PReg) && "Not the correct regclass!");
1139 unsigned VReg = MF.getRegInfo().createVirtualRegister(RC);
1140 MF.getRegInfo().addLiveIn(PReg, VReg);
1144 /// CallIsStructReturn - Determines whether a CALL node uses struct return
1146 static bool CallIsStructReturn(CallSDNode *TheCall) {
1147 unsigned NumOps = TheCall->getNumArgs();
1151 return TheCall->getArgFlags(0).isSRet();
1154 /// ArgsAreStructReturn - Determines whether a FORMAL_ARGUMENTS node uses struct
1155 /// return semantics.
1156 static bool ArgsAreStructReturn(SDValue Op) {
1157 unsigned NumArgs = Op.getNode()->getNumValues() - 1;
1161 return cast<ARG_FLAGSSDNode>(Op.getOperand(3))->getArgFlags().isSRet();
1164 /// IsCalleePop - Determines whether a CALL or FORMAL_ARGUMENTS node requires
1165 /// the callee to pop its own arguments. Callee pop is necessary to support tail
1167 bool X86TargetLowering::IsCalleePop(bool IsVarArg, unsigned CallingConv) {
1171 switch (CallingConv) {
1174 case CallingConv::X86_StdCall:
1175 return !Subtarget->is64Bit();
1176 case CallingConv::X86_FastCall:
1177 return !Subtarget->is64Bit();
1178 case CallingConv::Fast:
1179 return PerformTailCallOpt;
1183 /// CCAssignFnForNode - Selects the correct CCAssignFn for a the
1184 /// given CallingConvention value.
1185 CCAssignFn *X86TargetLowering::CCAssignFnForNode(unsigned CC) const {
1186 if (Subtarget->is64Bit()) {
1187 if (Subtarget->isTargetWin64())
1188 return CC_X86_Win64_C;
1189 else if (CC == CallingConv::Fast && PerformTailCallOpt)
1190 return CC_X86_64_TailCall;
1195 if (CC == CallingConv::X86_FastCall)
1196 return CC_X86_32_FastCall;
1197 else if (CC == CallingConv::Fast)
1198 return CC_X86_32_FastCC;
1203 /// NameDecorationForFORMAL_ARGUMENTS - Selects the appropriate decoration to
1204 /// apply to a MachineFunction containing a given FORMAL_ARGUMENTS node.
1206 X86TargetLowering::NameDecorationForFORMAL_ARGUMENTS(SDValue Op) {
1207 unsigned CC = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
1208 if (CC == CallingConv::X86_FastCall)
1210 else if (CC == CallingConv::X86_StdCall)
1216 /// CallRequiresGOTInRegister - Check whether the call requires the GOT pointer
1217 /// in a register before calling.
1218 bool X86TargetLowering::CallRequiresGOTPtrInReg(bool Is64Bit, bool IsTailCall) {
1219 return !IsTailCall && !Is64Bit &&
1220 getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1221 Subtarget->isPICStyleGOT();
1224 /// CallRequiresFnAddressInReg - Check whether the call requires the function
1225 /// address to be loaded in a register.
1227 X86TargetLowering::CallRequiresFnAddressInReg(bool Is64Bit, bool IsTailCall) {
1228 return !Is64Bit && IsTailCall &&
1229 getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1230 Subtarget->isPICStyleGOT();
1233 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
1234 /// by "Src" to address "Dst" with size and alignment information specified by
1235 /// the specific parameter attribute. The copy will be passed as a byval
1236 /// function parameter.
1238 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
1239 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
1241 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
1242 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
1243 /*AlwaysInline=*/true, NULL, 0, NULL, 0);
1246 SDValue X86TargetLowering::LowerMemArgument(SDValue Op, SelectionDAG &DAG,
1247 const CCValAssign &VA,
1248 MachineFrameInfo *MFI,
1250 SDValue Root, unsigned i) {
1251 // Create the nodes corresponding to a load from this parameter slot.
1252 ISD::ArgFlagsTy Flags =
1253 cast<ARG_FLAGSSDNode>(Op.getOperand(3 + i))->getArgFlags();
1254 bool AlwaysUseMutable = (CC==CallingConv::Fast) && PerformTailCallOpt;
1255 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
1257 // FIXME: For now, all byval parameter objects are marked mutable. This can be
1258 // changed with more analysis.
1259 // In case of tail call optimization mark all arguments mutable. Since they
1260 // could be overwritten by lowering of arguments in case of a tail call.
1261 int FI = MFI->CreateFixedObject(VA.getValVT().getSizeInBits()/8,
1262 VA.getLocMemOffset(), isImmutable);
1263 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
1264 if (Flags.isByVal())
1266 return DAG.getLoad(VA.getValVT(), Op.getDebugLoc(), Root, FIN,
1267 PseudoSourceValue::getFixedStack(FI), 0);
1271 X86TargetLowering::LowerFORMAL_ARGUMENTS(SDValue Op, SelectionDAG &DAG) {
1272 MachineFunction &MF = DAG.getMachineFunction();
1273 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1274 DebugLoc dl = Op.getDebugLoc();
1276 const Function* Fn = MF.getFunction();
1277 if (Fn->hasExternalLinkage() &&
1278 Subtarget->isTargetCygMing() &&
1279 Fn->getName() == "main")
1280 FuncInfo->setForceFramePointer(true);
1282 // Decorate the function name.
1283 FuncInfo->setDecorationStyle(NameDecorationForFORMAL_ARGUMENTS(Op));
1285 MachineFrameInfo *MFI = MF.getFrameInfo();
1286 SDValue Root = Op.getOperand(0);
1287 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue() != 0;
1288 unsigned CC = MF.getFunction()->getCallingConv();
1289 bool Is64Bit = Subtarget->is64Bit();
1290 bool IsWin64 = Subtarget->isTargetWin64();
1292 assert(!(isVarArg && CC == CallingConv::Fast) &&
1293 "Var args not supported with calling convention fastcc");
1295 // Assign locations to all of the incoming arguments.
1296 SmallVector<CCValAssign, 16> ArgLocs;
1297 CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs);
1298 CCInfo.AnalyzeFormalArguments(Op.getNode(), CCAssignFnForNode(CC));
1300 SmallVector<SDValue, 8> ArgValues;
1301 unsigned LastVal = ~0U;
1302 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1303 CCValAssign &VA = ArgLocs[i];
1304 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
1306 assert(VA.getValNo() != LastVal &&
1307 "Don't support value assigned to multiple locs yet");
1308 LastVal = VA.getValNo();
1310 if (VA.isRegLoc()) {
1311 MVT RegVT = VA.getLocVT();
1312 TargetRegisterClass *RC = NULL;
1313 if (RegVT == MVT::i32)
1314 RC = X86::GR32RegisterClass;
1315 else if (Is64Bit && RegVT == MVT::i64)
1316 RC = X86::GR64RegisterClass;
1317 else if (RegVT == MVT::f32)
1318 RC = X86::FR32RegisterClass;
1319 else if (RegVT == MVT::f64)
1320 RC = X86::FR64RegisterClass;
1321 else if (RegVT.isVector() && RegVT.getSizeInBits() == 128)
1322 RC = X86::VR128RegisterClass;
1323 else if (RegVT.isVector()) {
1324 assert(RegVT.getSizeInBits() == 64);
1326 RC = X86::VR64RegisterClass; // MMX values are passed in MMXs.
1328 // Darwin calling convention passes MMX values in either GPRs or
1329 // XMMs in x86-64. Other targets pass them in memory.
1330 if (RegVT != MVT::v1i64 && Subtarget->hasSSE2()) {
1331 RC = X86::VR128RegisterClass; // MMX values are passed in XMMs.
1334 RC = X86::GR64RegisterClass; // v1i64 values are passed in GPRs.
1339 assert(0 && "Unknown argument type!");
1342 unsigned Reg = AddLiveIn(DAG.getMachineFunction(), VA.getLocReg(), RC);
1343 SDValue ArgValue = DAG.getCopyFromReg(Root, dl, Reg, RegVT);
1345 // If this is an 8 or 16-bit value, it is really passed promoted to 32
1346 // bits. Insert an assert[sz]ext to capture this, then truncate to the
1348 if (VA.getLocInfo() == CCValAssign::SExt)
1349 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
1350 DAG.getValueType(VA.getValVT()));
1351 else if (VA.getLocInfo() == CCValAssign::ZExt)
1352 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
1353 DAG.getValueType(VA.getValVT()));
1355 if (VA.getLocInfo() != CCValAssign::Full)
1356 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
1358 // Handle MMX values passed in GPRs.
1359 if (Is64Bit && RegVT != VA.getLocVT()) {
1360 if (RegVT.getSizeInBits() == 64 && RC == X86::GR64RegisterClass)
1361 ArgValue = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getLocVT(), ArgValue);
1362 else if (RC == X86::VR128RegisterClass) {
1363 ArgValue = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64,
1364 ArgValue, DAG.getConstant(0, MVT::i64));
1365 ArgValue = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getLocVT(), ArgValue);
1369 ArgValues.push_back(ArgValue);
1371 assert(VA.isMemLoc());
1372 ArgValues.push_back(LowerMemArgument(Op, DAG, VA, MFI, CC, Root, i));
1376 // The x86-64 ABI for returning structs by value requires that we copy
1377 // the sret argument into %rax for the return. Save the argument into
1378 // a virtual register so that we can access it from the return points.
1379 if (Is64Bit && DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
1380 MachineFunction &MF = DAG.getMachineFunction();
1381 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1382 unsigned Reg = FuncInfo->getSRetReturnReg();
1384 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64));
1385 FuncInfo->setSRetReturnReg(Reg);
1387 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, ArgValues[0]);
1388 Root = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Root);
1391 unsigned StackSize = CCInfo.getNextStackOffset();
1392 // align stack specially for tail calls
1393 if (PerformTailCallOpt && CC == CallingConv::Fast)
1394 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
1396 // If the function takes variable number of arguments, make a frame index for
1397 // the start of the first vararg value... for expansion of llvm.va_start.
1399 if (Is64Bit || CC != CallingConv::X86_FastCall) {
1400 VarArgsFrameIndex = MFI->CreateFixedObject(1, StackSize);
1403 unsigned TotalNumIntRegs = 0, TotalNumXMMRegs = 0;
1405 // FIXME: We should really autogenerate these arrays
1406 static const unsigned GPR64ArgRegsWin64[] = {
1407 X86::RCX, X86::RDX, X86::R8, X86::R9
1409 static const unsigned XMMArgRegsWin64[] = {
1410 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
1412 static const unsigned GPR64ArgRegs64Bit[] = {
1413 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
1415 static const unsigned XMMArgRegs64Bit[] = {
1416 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
1417 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
1419 const unsigned *GPR64ArgRegs, *XMMArgRegs;
1422 TotalNumIntRegs = 4; TotalNumXMMRegs = 4;
1423 GPR64ArgRegs = GPR64ArgRegsWin64;
1424 XMMArgRegs = XMMArgRegsWin64;
1426 TotalNumIntRegs = 6; TotalNumXMMRegs = 8;
1427 GPR64ArgRegs = GPR64ArgRegs64Bit;
1428 XMMArgRegs = XMMArgRegs64Bit;
1430 unsigned NumIntRegs = CCInfo.getFirstUnallocated(GPR64ArgRegs,
1432 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs,
1435 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) &&
1436 "SSE register cannot be used when SSE is disabled!");
1437 assert(!(NumXMMRegs && UseSoftFloat) &&
1438 "SSE register cannot be used when SSE is disabled!");
1439 if (UseSoftFloat || !Subtarget->hasSSE1()) {
1440 // Kernel mode asks for SSE to be disabled, so don't push them
1442 TotalNumXMMRegs = 0;
1444 // For X86-64, if there are vararg parameters that are passed via
1445 // registers, then we must store them to their spots on the stack so they
1446 // may be loaded by deferencing the result of va_next.
1447 VarArgsGPOffset = NumIntRegs * 8;
1448 VarArgsFPOffset = TotalNumIntRegs * 8 + NumXMMRegs * 16;
1449 RegSaveFrameIndex = MFI->CreateStackObject(TotalNumIntRegs * 8 +
1450 TotalNumXMMRegs * 16, 16);
1452 // Store the integer parameter registers.
1453 SmallVector<SDValue, 8> MemOps;
1454 SDValue RSFIN = DAG.getFrameIndex(RegSaveFrameIndex, getPointerTy());
1455 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN,
1456 DAG.getIntPtrConstant(VarArgsGPOffset));
1457 for (; NumIntRegs != TotalNumIntRegs; ++NumIntRegs) {
1458 unsigned VReg = AddLiveIn(MF, GPR64ArgRegs[NumIntRegs],
1459 X86::GR64RegisterClass);
1460 SDValue Val = DAG.getCopyFromReg(Root, dl, VReg, MVT::i64);
1462 DAG.getStore(Val.getValue(1), dl, Val, FIN,
1463 PseudoSourceValue::getFixedStack(RegSaveFrameIndex), 0);
1464 MemOps.push_back(Store);
1465 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), FIN,
1466 DAG.getIntPtrConstant(8));
1469 // Now store the XMM (fp + vector) parameter registers.
1470 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN,
1471 DAG.getIntPtrConstant(VarArgsFPOffset));
1472 for (; NumXMMRegs != TotalNumXMMRegs; ++NumXMMRegs) {
1473 unsigned VReg = AddLiveIn(MF, XMMArgRegs[NumXMMRegs],
1474 X86::VR128RegisterClass);
1475 SDValue Val = DAG.getCopyFromReg(Root, dl, VReg, MVT::v4f32);
1477 DAG.getStore(Val.getValue(1), dl, Val, FIN,
1478 PseudoSourceValue::getFixedStack(RegSaveFrameIndex), 0);
1479 MemOps.push_back(Store);
1480 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), FIN,
1481 DAG.getIntPtrConstant(16));
1483 if (!MemOps.empty())
1484 Root = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1485 &MemOps[0], MemOps.size());
1489 ArgValues.push_back(Root);
1491 // Some CCs need callee pop.
1492 if (IsCalleePop(isVarArg, CC)) {
1493 BytesToPopOnReturn = StackSize; // Callee pops everything.
1494 BytesCallerReserves = 0;
1496 BytesToPopOnReturn = 0; // Callee pops nothing.
1497 // If this is an sret function, the return should pop the hidden pointer.
1498 if (!Is64Bit && CC != CallingConv::Fast && ArgsAreStructReturn(Op))
1499 BytesToPopOnReturn = 4;
1500 BytesCallerReserves = StackSize;
1504 RegSaveFrameIndex = 0xAAAAAAA; // RegSaveFrameIndex is X86-64 only.
1505 if (CC == CallingConv::X86_FastCall)
1506 VarArgsFrameIndex = 0xAAAAAAA; // fastcc functions can't have varargs.
1509 FuncInfo->setBytesToPopOnReturn(BytesToPopOnReturn);
1511 // Return the new list of results.
1512 return DAG.getNode(ISD::MERGE_VALUES, dl, Op.getNode()->getVTList(),
1513 &ArgValues[0], ArgValues.size()).getValue(Op.getResNo());
1517 X86TargetLowering::LowerMemOpCallTo(CallSDNode *TheCall, SelectionDAG &DAG,
1518 const SDValue &StackPtr,
1519 const CCValAssign &VA,
1521 SDValue Arg, ISD::ArgFlagsTy Flags) {
1522 DebugLoc dl = TheCall->getDebugLoc();
1523 unsigned LocMemOffset = VA.getLocMemOffset();
1524 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
1525 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
1526 if (Flags.isByVal()) {
1527 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
1529 return DAG.getStore(Chain, dl, Arg, PtrOff,
1530 PseudoSourceValue::getStack(), LocMemOffset);
1533 /// EmitTailCallLoadRetAddr - Emit a load of return address if tail call
1534 /// optimization is performed and it is required.
1536 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
1537 SDValue &OutRetAddr,
1543 if (!IsTailCall || FPDiff==0) return Chain;
1545 // Adjust the Return address stack slot.
1546 MVT VT = getPointerTy();
1547 OutRetAddr = getReturnAddressFrameIndex(DAG);
1549 // Load the "old" Return address.
1550 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, NULL, 0);
1551 return SDValue(OutRetAddr.getNode(), 1);
1554 /// EmitTailCallStoreRetAddr - Emit a store of the return adress if tail call
1555 /// optimization is performed and it is required (FPDiff!=0).
1557 EmitTailCallStoreRetAddr(SelectionDAG & DAG, MachineFunction &MF,
1558 SDValue Chain, SDValue RetAddrFrIdx,
1559 bool Is64Bit, int FPDiff, DebugLoc dl) {
1560 // Store the return address to the appropriate stack slot.
1561 if (!FPDiff) return Chain;
1562 // Calculate the new stack slot for the return address.
1563 int SlotSize = Is64Bit ? 8 : 4;
1564 int NewReturnAddrFI =
1565 MF.getFrameInfo()->CreateFixedObject(SlotSize, FPDiff-SlotSize);
1566 MVT VT = Is64Bit ? MVT::i64 : MVT::i32;
1567 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, VT);
1568 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
1569 PseudoSourceValue::getFixedStack(NewReturnAddrFI), 0);
1573 SDValue X86TargetLowering::LowerCALL(SDValue Op, SelectionDAG &DAG) {
1574 MachineFunction &MF = DAG.getMachineFunction();
1575 CallSDNode *TheCall = cast<CallSDNode>(Op.getNode());
1576 SDValue Chain = TheCall->getChain();
1577 unsigned CC = TheCall->getCallingConv();
1578 bool isVarArg = TheCall->isVarArg();
1579 bool IsTailCall = TheCall->isTailCall() &&
1580 CC == CallingConv::Fast && PerformTailCallOpt;
1581 SDValue Callee = TheCall->getCallee();
1582 bool Is64Bit = Subtarget->is64Bit();
1583 bool IsStructRet = CallIsStructReturn(TheCall);
1584 DebugLoc dl = TheCall->getDebugLoc();
1586 assert(!(isVarArg && CC == CallingConv::Fast) &&
1587 "Var args not supported with calling convention fastcc");
1589 // Analyze operands of the call, assigning locations to each operand.
1590 SmallVector<CCValAssign, 16> ArgLocs;
1591 CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs);
1592 CCInfo.AnalyzeCallOperands(TheCall, CCAssignFnForNode(CC));
1594 // Get a count of how many bytes are to be pushed on the stack.
1595 unsigned NumBytes = CCInfo.getNextStackOffset();
1596 if (PerformTailCallOpt && CC == CallingConv::Fast)
1597 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
1601 // Lower arguments at fp - stackoffset + fpdiff.
1602 unsigned NumBytesCallerPushed =
1603 MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn();
1604 FPDiff = NumBytesCallerPushed - NumBytes;
1606 // Set the delta of movement of the returnaddr stackslot.
1607 // But only set if delta is greater than previous delta.
1608 if (FPDiff < (MF.getInfo<X86MachineFunctionInfo>()->getTCReturnAddrDelta()))
1609 MF.getInfo<X86MachineFunctionInfo>()->setTCReturnAddrDelta(FPDiff);
1612 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
1614 SDValue RetAddrFrIdx;
1615 // Load return adress for tail calls.
1616 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, IsTailCall, Is64Bit,
1619 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
1620 SmallVector<SDValue, 8> MemOpChains;
1623 // Walk the register/memloc assignments, inserting copies/loads. In the case
1624 // of tail call optimization arguments are handle later.
1625 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1626 CCValAssign &VA = ArgLocs[i];
1627 SDValue Arg = TheCall->getArg(i);
1628 ISD::ArgFlagsTy Flags = TheCall->getArgFlags(i);
1629 bool isByVal = Flags.isByVal();
1631 // Promote the value if needed.
1632 switch (VA.getLocInfo()) {
1633 default: assert(0 && "Unknown loc info!");
1634 case CCValAssign::Full: break;
1635 case CCValAssign::SExt:
1636 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
1638 case CCValAssign::ZExt:
1639 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
1641 case CCValAssign::AExt:
1642 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
1646 if (VA.isRegLoc()) {
1648 MVT RegVT = VA.getLocVT();
1649 if (RegVT.isVector() && RegVT.getSizeInBits() == 64)
1650 switch (VA.getLocReg()) {
1653 case X86::RDI: case X86::RSI: case X86::RDX: case X86::RCX:
1655 // Special case: passing MMX values in GPR registers.
1656 Arg = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i64, Arg);
1659 case X86::XMM0: case X86::XMM1: case X86::XMM2: case X86::XMM3:
1660 case X86::XMM4: case X86::XMM5: case X86::XMM6: case X86::XMM7: {
1661 // Special case: passing MMX values in XMM registers.
1662 Arg = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i64, Arg);
1663 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
1664 Arg = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, MVT::v2i64,
1665 DAG.getUNDEF(MVT::v2i64), Arg,
1666 getMOVLMask(2, DAG, dl));
1671 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
1673 if (!IsTailCall || (IsTailCall && isByVal)) {
1674 assert(VA.isMemLoc());
1675 if (StackPtr.getNode() == 0)
1676 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr, getPointerTy());
1678 MemOpChains.push_back(LowerMemOpCallTo(TheCall, DAG, StackPtr, VA,
1679 Chain, Arg, Flags));
1684 if (!MemOpChains.empty())
1685 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1686 &MemOpChains[0], MemOpChains.size());
1688 // Build a sequence of copy-to-reg nodes chained together with token chain
1689 // and flag operands which copy the outgoing args into registers.
1691 // Tail call byval lowering might overwrite argument registers so in case of
1692 // tail call optimization the copies to registers are lowered later.
1694 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1695 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
1696 RegsToPass[i].second, InFlag);
1697 InFlag = Chain.getValue(1);
1700 // ELF / PIC requires GOT in the EBX register before function calls via PLT
1702 if (CallRequiresGOTPtrInReg(Is64Bit, IsTailCall)) {
1703 Chain = DAG.getCopyToReg(Chain, dl, X86::EBX,
1704 DAG.getNode(X86ISD::GlobalBaseReg,
1705 DebugLoc::getUnknownLoc(),
1708 InFlag = Chain.getValue(1);
1710 // If we are tail calling and generating PIC/GOT style code load the address
1711 // of the callee into ecx. The value in ecx is used as target of the tail
1712 // jump. This is done to circumvent the ebx/callee-saved problem for tail
1713 // calls on PIC/GOT architectures. Normally we would just put the address of
1714 // GOT into ebx and then call target@PLT. But for tail callss ebx would be
1715 // restored (since ebx is callee saved) before jumping to the target@PLT.
1716 if (CallRequiresFnAddressInReg(Is64Bit, IsTailCall)) {
1717 // Note: The actual moving to ecx is done further down.
1718 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
1719 if (G && !G->getGlobal()->hasHiddenVisibility() &&
1720 !G->getGlobal()->hasProtectedVisibility())
1721 Callee = LowerGlobalAddress(Callee, DAG);
1722 else if (isa<ExternalSymbolSDNode>(Callee))
1723 Callee = LowerExternalSymbol(Callee,DAG);
1726 if (Is64Bit && isVarArg) {
1727 // From AMD64 ABI document:
1728 // For calls that may call functions that use varargs or stdargs
1729 // (prototype-less calls or calls to functions containing ellipsis (...) in
1730 // the declaration) %al is used as hidden argument to specify the number
1731 // of SSE registers used. The contents of %al do not need to match exactly
1732 // the number of registers, but must be an ubound on the number of SSE
1733 // registers used and is in the range 0 - 8 inclusive.
1735 // FIXME: Verify this on Win64
1736 // Count the number of XMM registers allocated.
1737 static const unsigned XMMArgRegs[] = {
1738 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
1739 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
1741 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
1742 assert((Subtarget->hasSSE1() || !NumXMMRegs)
1743 && "SSE registers cannot be used when SSE is disabled");
1745 Chain = DAG.getCopyToReg(Chain, dl, X86::AL,
1746 DAG.getConstant(NumXMMRegs, MVT::i8), InFlag);
1747 InFlag = Chain.getValue(1);
1751 // For tail calls lower the arguments to the 'real' stack slot.
1753 SmallVector<SDValue, 8> MemOpChains2;
1756 // Do not flag preceeding copytoreg stuff together with the following stuff.
1758 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1759 CCValAssign &VA = ArgLocs[i];
1760 if (!VA.isRegLoc()) {
1761 assert(VA.isMemLoc());
1762 SDValue Arg = TheCall->getArg(i);
1763 ISD::ArgFlagsTy Flags = TheCall->getArgFlags(i);
1764 // Create frame index.
1765 int32_t Offset = VA.getLocMemOffset()+FPDiff;
1766 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
1767 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset);
1768 FIN = DAG.getFrameIndex(FI, getPointerTy());
1770 if (Flags.isByVal()) {
1771 // Copy relative to framepointer.
1772 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset());
1773 if (StackPtr.getNode() == 0)
1774 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr,
1776 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source);
1778 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN, Chain,
1781 // Store relative to framepointer.
1782 MemOpChains2.push_back(
1783 DAG.getStore(Chain, dl, Arg, FIN,
1784 PseudoSourceValue::getFixedStack(FI), 0));
1789 if (!MemOpChains2.empty())
1790 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1791 &MemOpChains2[0], MemOpChains2.size());
1793 // Copy arguments to their registers.
1794 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1795 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
1796 RegsToPass[i].second, InFlag);
1797 InFlag = Chain.getValue(1);
1801 // Store the return address to the appropriate stack slot.
1802 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx, Is64Bit,
1806 // If the callee is a GlobalAddress node (quite common, every direct call is)
1807 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
1808 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1809 // We should use extra load for direct calls to dllimported functions in
1811 if (!Subtarget->GVRequiresExtraLoad(G->getGlobal(),
1812 getTargetMachine(), true))
1813 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), getPointerTy(),
1815 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
1816 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy());
1817 } else if (IsTailCall) {
1818 unsigned Opc = Is64Bit ? X86::R9 : X86::EAX;
1820 Chain = DAG.getCopyToReg(Chain, dl,
1821 DAG.getRegister(Opc, getPointerTy()),
1823 Callee = DAG.getRegister(Opc, getPointerTy());
1824 // Add register as live out.
1825 DAG.getMachineFunction().getRegInfo().addLiveOut(Opc);
1828 // Returns a chain & a flag for retval copy to use.
1829 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
1830 SmallVector<SDValue, 8> Ops;
1833 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
1834 DAG.getIntPtrConstant(0, true), InFlag);
1835 InFlag = Chain.getValue(1);
1837 // Returns a chain & a flag for retval copy to use.
1838 NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
1842 Ops.push_back(Chain);
1843 Ops.push_back(Callee);
1846 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32));
1848 // Add argument registers to the end of the list so that they are known live
1850 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
1851 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
1852 RegsToPass[i].second.getValueType()));
1854 // Add an implicit use GOT pointer in EBX.
1855 if (!IsTailCall && !Is64Bit &&
1856 getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1857 Subtarget->isPICStyleGOT())
1858 Ops.push_back(DAG.getRegister(X86::EBX, getPointerTy()));
1860 // Add an implicit use of AL for x86 vararg functions.
1861 if (Is64Bit && isVarArg)
1862 Ops.push_back(DAG.getRegister(X86::AL, MVT::i8));
1864 if (InFlag.getNode())
1865 Ops.push_back(InFlag);
1868 assert(InFlag.getNode() &&
1869 "Flag must be set. Depend on flag being set in LowerRET");
1870 Chain = DAG.getNode(X86ISD::TAILCALL, dl,
1871 TheCall->getVTList(), &Ops[0], Ops.size());
1873 return SDValue(Chain.getNode(), Op.getResNo());
1876 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, &Ops[0], Ops.size());
1877 InFlag = Chain.getValue(1);
1879 // Create the CALLSEQ_END node.
1880 unsigned NumBytesForCalleeToPush;
1881 if (IsCalleePop(isVarArg, CC))
1882 NumBytesForCalleeToPush = NumBytes; // Callee pops everything
1883 else if (!Is64Bit && CC != CallingConv::Fast && IsStructRet)
1884 // If this is is a call to a struct-return function, the callee
1885 // pops the hidden struct pointer, so we have to push it back.
1886 // This is common for Darwin/X86, Linux & Mingw32 targets.
1887 NumBytesForCalleeToPush = 4;
1889 NumBytesForCalleeToPush = 0; // Callee pops nothing.
1891 // Returns a flag for retval copy to use.
1892 Chain = DAG.getCALLSEQ_END(Chain,
1893 DAG.getIntPtrConstant(NumBytes, true),
1894 DAG.getIntPtrConstant(NumBytesForCalleeToPush,
1897 InFlag = Chain.getValue(1);
1899 // Handle result values, copying them out of physregs into vregs that we
1901 return SDValue(LowerCallResult(Chain, InFlag, TheCall, CC, DAG),
1906 //===----------------------------------------------------------------------===//
1907 // Fast Calling Convention (tail call) implementation
1908 //===----------------------------------------------------------------------===//
1910 // Like std call, callee cleans arguments, convention except that ECX is
1911 // reserved for storing the tail called function address. Only 2 registers are
1912 // free for argument passing (inreg). Tail call optimization is performed
1914 // * tailcallopt is enabled
1915 // * caller/callee are fastcc
1916 // On X86_64 architecture with GOT-style position independent code only local
1917 // (within module) calls are supported at the moment.
1918 // To keep the stack aligned according to platform abi the function
1919 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
1920 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
1921 // If a tail called function callee has more arguments than the caller the
1922 // caller needs to make sure that there is room to move the RETADDR to. This is
1923 // achieved by reserving an area the size of the argument delta right after the
1924 // original REtADDR, but before the saved framepointer or the spilled registers
1925 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
1937 /// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned
1938 /// for a 16 byte align requirement.
1939 unsigned X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
1940 SelectionDAG& DAG) {
1941 MachineFunction &MF = DAG.getMachineFunction();
1942 const TargetMachine &TM = MF.getTarget();
1943 const TargetFrameInfo &TFI = *TM.getFrameInfo();
1944 unsigned StackAlignment = TFI.getStackAlignment();
1945 uint64_t AlignMask = StackAlignment - 1;
1946 int64_t Offset = StackSize;
1947 uint64_t SlotSize = TD->getPointerSize();
1948 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
1949 // Number smaller than 12 so just add the difference.
1950 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
1952 // Mask out lower bits, add stackalignment once plus the 12 bytes.
1953 Offset = ((~AlignMask) & Offset) + StackAlignment +
1954 (StackAlignment-SlotSize);
1959 /// IsEligibleForTailCallElimination - Check to see whether the next instruction
1960 /// following the call is a return. A function is eligible if caller/callee
1961 /// calling conventions match, currently only fastcc supports tail calls, and
1962 /// the function CALL is immediatly followed by a RET.
1963 bool X86TargetLowering::IsEligibleForTailCallOptimization(CallSDNode *TheCall,
1965 SelectionDAG& DAG) const {
1966 if (!PerformTailCallOpt)
1969 if (CheckTailCallReturnConstraints(TheCall, Ret)) {
1970 MachineFunction &MF = DAG.getMachineFunction();
1971 unsigned CallerCC = MF.getFunction()->getCallingConv();
1972 unsigned CalleeCC= TheCall->getCallingConv();
1973 if (CalleeCC == CallingConv::Fast && CallerCC == CalleeCC) {
1974 SDValue Callee = TheCall->getCallee();
1975 // On x86/32Bit PIC/GOT tail calls are supported.
1976 if (getTargetMachine().getRelocationModel() != Reloc::PIC_ ||
1977 !Subtarget->isPICStyleGOT()|| !Subtarget->is64Bit())
1980 // Can only do local tail calls (in same module, hidden or protected) on
1981 // x86_64 PIC/GOT at the moment.
1982 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
1983 return G->getGlobal()->hasHiddenVisibility()
1984 || G->getGlobal()->hasProtectedVisibility();
1992 X86TargetLowering::createFastISel(MachineFunction &mf,
1993 MachineModuleInfo *mmo,
1995 DenseMap<const Value *, unsigned> &vm,
1996 DenseMap<const BasicBlock *,
1997 MachineBasicBlock *> &bm,
1998 DenseMap<const AllocaInst *, int> &am
2000 , SmallSet<Instruction*, 8> &cil
2003 return X86::createFastISel(mf, mmo, dw, vm, bm, am
2011 //===----------------------------------------------------------------------===//
2012 // Other Lowering Hooks
2013 //===----------------------------------------------------------------------===//
2016 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) {
2017 MachineFunction &MF = DAG.getMachineFunction();
2018 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2019 int ReturnAddrIndex = FuncInfo->getRAIndex();
2021 if (ReturnAddrIndex == 0) {
2022 // Set up a frame object for the return address.
2023 uint64_t SlotSize = TD->getPointerSize();
2024 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize, -SlotSize);
2025 FuncInfo->setRAIndex(ReturnAddrIndex);
2028 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
2032 /// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86
2033 /// specific condition code, returning the condition code and the LHS/RHS of the
2034 /// comparison to make.
2035 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
2036 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
2038 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
2039 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
2040 // X > -1 -> X == 0, jump !sign.
2041 RHS = DAG.getConstant(0, RHS.getValueType());
2042 return X86::COND_NS;
2043 } else if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
2044 // X < 0 -> X == 0, jump on sign.
2046 } else if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
2048 RHS = DAG.getConstant(0, RHS.getValueType());
2049 return X86::COND_LE;
2053 switch (SetCCOpcode) {
2054 default: assert(0 && "Invalid integer condition!");
2055 case ISD::SETEQ: return X86::COND_E;
2056 case ISD::SETGT: return X86::COND_G;
2057 case ISD::SETGE: return X86::COND_GE;
2058 case ISD::SETLT: return X86::COND_L;
2059 case ISD::SETLE: return X86::COND_LE;
2060 case ISD::SETNE: return X86::COND_NE;
2061 case ISD::SETULT: return X86::COND_B;
2062 case ISD::SETUGT: return X86::COND_A;
2063 case ISD::SETULE: return X86::COND_BE;
2064 case ISD::SETUGE: return X86::COND_AE;
2068 // First determine if it is required or is profitable to flip the operands.
2070 // If LHS is a foldable load, but RHS is not, flip the condition.
2071 if ((ISD::isNON_EXTLoad(LHS.getNode()) && LHS.hasOneUse()) &&
2072 !(ISD::isNON_EXTLoad(RHS.getNode()) && RHS.hasOneUse())) {
2073 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
2074 std::swap(LHS, RHS);
2077 switch (SetCCOpcode) {
2083 std::swap(LHS, RHS);
2087 // On a floating point condition, the flags are set as follows:
2089 // 0 | 0 | 0 | X > Y
2090 // 0 | 0 | 1 | X < Y
2091 // 1 | 0 | 0 | X == Y
2092 // 1 | 1 | 1 | unordered
2093 switch (SetCCOpcode) {
2094 default: assert(0 && "Condcode should be pre-legalized away");
2096 case ISD::SETEQ: return X86::COND_E;
2097 case ISD::SETOLT: // flipped
2099 case ISD::SETGT: return X86::COND_A;
2100 case ISD::SETOLE: // flipped
2102 case ISD::SETGE: return X86::COND_AE;
2103 case ISD::SETUGT: // flipped
2105 case ISD::SETLT: return X86::COND_B;
2106 case ISD::SETUGE: // flipped
2108 case ISD::SETLE: return X86::COND_BE;
2110 case ISD::SETNE: return X86::COND_NE;
2111 case ISD::SETUO: return X86::COND_P;
2112 case ISD::SETO: return X86::COND_NP;
2116 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
2117 /// code. Current x86 isa includes the following FP cmov instructions:
2118 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
2119 static bool hasFPCMov(unsigned X86CC) {
2135 /// isUndefOrInRange - Op is either an undef node or a ConstantSDNode. Return
2136 /// true if Op is undef or if its value falls within the specified range (L, H].
2137 static bool isUndefOrInRange(SDValue Op, unsigned Low, unsigned Hi) {
2138 if (Op.getOpcode() == ISD::UNDEF)
2141 unsigned Val = cast<ConstantSDNode>(Op)->getZExtValue();
2142 return (Val >= Low && Val < Hi);
2145 /// isUndefOrEqual - Op is either an undef node or a ConstantSDNode. Return
2146 /// true if Op is undef or if its value equal to the specified value.
2147 static bool isUndefOrEqual(SDValue Op, unsigned Val) {
2148 if (Op.getOpcode() == ISD::UNDEF)
2150 return cast<ConstantSDNode>(Op)->getZExtValue() == Val;
2153 /// isPSHUFDMask - Return true if the specified VECTOR_SHUFFLE operand
2154 /// specifies a shuffle of elements that is suitable for input to PSHUFD.
2155 bool X86::isPSHUFDMask(SDNode *N) {
2156 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2158 if (N->getNumOperands() != 2 && N->getNumOperands() != 4)
2161 // Check if the value doesn't reference the second vector.
2162 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
2163 SDValue Arg = N->getOperand(i);
2164 if (Arg.getOpcode() == ISD::UNDEF) continue;
2165 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2166 if (cast<ConstantSDNode>(Arg)->getZExtValue() >= e)
2173 /// isPSHUFHWMask - Return true if the specified VECTOR_SHUFFLE operand
2174 /// specifies a shuffle of elements that is suitable for input to PSHUFHW.
2175 bool X86::isPSHUFHWMask(SDNode *N) {
2176 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2178 if (N->getNumOperands() != 8)
2181 // Lower quadword copied in order.
2182 for (unsigned i = 0; i != 4; ++i) {
2183 SDValue Arg = N->getOperand(i);
2184 if (Arg.getOpcode() == ISD::UNDEF) continue;
2185 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2186 if (cast<ConstantSDNode>(Arg)->getZExtValue() != i)
2190 // Upper quadword shuffled.
2191 for (unsigned i = 4; i != 8; ++i) {
2192 SDValue Arg = N->getOperand(i);
2193 if (Arg.getOpcode() == ISD::UNDEF) continue;
2194 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2195 unsigned Val = cast<ConstantSDNode>(Arg)->getZExtValue();
2196 if (Val < 4 || Val > 7)
2203 /// isPSHUFLWMask - Return true if the specified VECTOR_SHUFFLE operand
2204 /// specifies a shuffle of elements that is suitable for input to PSHUFLW.
2205 bool X86::isPSHUFLWMask(SDNode *N) {
2206 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2208 if (N->getNumOperands() != 8)
2211 // Upper quadword copied in order.
2212 for (unsigned i = 4; i != 8; ++i)
2213 if (!isUndefOrEqual(N->getOperand(i), i))
2216 // Lower quadword shuffled.
2217 for (unsigned i = 0; i != 4; ++i)
2218 if (!isUndefOrInRange(N->getOperand(i), 0, 4))
2224 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
2225 /// specifies a shuffle of elements that is suitable for input to SHUFP*.
2226 template<class SDOperand>
2227 static bool isSHUFPMask(SDOperand *Elems, unsigned NumElems) {
2228 if (NumElems != 2 && NumElems != 4) return false;
2230 unsigned Half = NumElems / 2;
2231 for (unsigned i = 0; i < Half; ++i)
2232 if (!isUndefOrInRange(Elems[i], 0, NumElems))
2234 for (unsigned i = Half; i < NumElems; ++i)
2235 if (!isUndefOrInRange(Elems[i], NumElems, NumElems*2))
2241 bool X86::isSHUFPMask(SDNode *N) {
2242 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2243 return ::isSHUFPMask(N->op_begin(), N->getNumOperands());
2246 /// isCommutedSHUFP - Returns true if the shuffle mask is exactly
2247 /// the reverse of what x86 shuffles want. x86 shuffles requires the lower
2248 /// half elements to come from vector 1 (which would equal the dest.) and
2249 /// the upper half to come from vector 2.
2250 template<class SDOperand>
2251 static bool isCommutedSHUFP(SDOperand *Ops, unsigned NumOps) {
2252 if (NumOps != 2 && NumOps != 4) return false;
2254 unsigned Half = NumOps / 2;
2255 for (unsigned i = 0; i < Half; ++i)
2256 if (!isUndefOrInRange(Ops[i], NumOps, NumOps*2))
2258 for (unsigned i = Half; i < NumOps; ++i)
2259 if (!isUndefOrInRange(Ops[i], 0, NumOps))
2264 static bool isCommutedSHUFP(SDNode *N) {
2265 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2266 return isCommutedSHUFP(N->op_begin(), N->getNumOperands());
2269 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
2270 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
2271 bool X86::isMOVHLPSMask(SDNode *N) {
2272 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2274 if (N->getNumOperands() != 4)
2277 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3
2278 return isUndefOrEqual(N->getOperand(0), 6) &&
2279 isUndefOrEqual(N->getOperand(1), 7) &&
2280 isUndefOrEqual(N->getOperand(2), 2) &&
2281 isUndefOrEqual(N->getOperand(3), 3);
2284 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
2285 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
2287 bool X86::isMOVHLPS_v_undef_Mask(SDNode *N) {
2288 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2290 if (N->getNumOperands() != 4)
2293 // Expect bit0 == 2, bit1 == 3, bit2 == 2, bit3 == 3
2294 return isUndefOrEqual(N->getOperand(0), 2) &&
2295 isUndefOrEqual(N->getOperand(1), 3) &&
2296 isUndefOrEqual(N->getOperand(2), 2) &&
2297 isUndefOrEqual(N->getOperand(3), 3);
2300 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
2301 /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
2302 bool X86::isMOVLPMask(SDNode *N) {
2303 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2305 unsigned NumElems = N->getNumOperands();
2306 if (NumElems != 2 && NumElems != 4)
2309 for (unsigned i = 0; i < NumElems/2; ++i)
2310 if (!isUndefOrEqual(N->getOperand(i), i + NumElems))
2313 for (unsigned i = NumElems/2; i < NumElems; ++i)
2314 if (!isUndefOrEqual(N->getOperand(i), i))
2320 /// isMOVHPMask - Return true if the specified VECTOR_SHUFFLE operand
2321 /// specifies a shuffle of elements that is suitable for input to MOVHP{S|D}
2323 bool X86::isMOVHPMask(SDNode *N) {
2324 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2326 unsigned NumElems = N->getNumOperands();
2327 if (NumElems != 2 && NumElems != 4)
2330 for (unsigned i = 0; i < NumElems/2; ++i)
2331 if (!isUndefOrEqual(N->getOperand(i), i))
2334 for (unsigned i = 0; i < NumElems/2; ++i) {
2335 SDValue Arg = N->getOperand(i + NumElems/2);
2336 if (!isUndefOrEqual(Arg, i + NumElems))
2343 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
2344 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
2345 template<class SDOperand>
2346 bool static isUNPCKLMask(SDOperand *Elts, unsigned NumElts,
2347 bool V2IsSplat = false) {
2348 if (NumElts != 2 && NumElts != 4 && NumElts != 8 && NumElts != 16)
2351 for (unsigned i = 0, j = 0; i != NumElts; i += 2, ++j) {
2352 SDValue BitI = Elts[i];
2353 SDValue BitI1 = Elts[i+1];
2354 if (!isUndefOrEqual(BitI, j))
2357 if (!isUndefOrEqual(BitI1, NumElts))
2360 if (!isUndefOrEqual(BitI1, j + NumElts))
2368 bool X86::isUNPCKLMask(SDNode *N, bool V2IsSplat) {
2369 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2370 return ::isUNPCKLMask(N->op_begin(), N->getNumOperands(), V2IsSplat);
2373 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
2374 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
2375 template<class SDOperand>
2376 bool static isUNPCKHMask(SDOperand *Elts, unsigned NumElts,
2377 bool V2IsSplat = false) {
2378 if (NumElts != 2 && NumElts != 4 && NumElts != 8 && NumElts != 16)
2381 for (unsigned i = 0, j = 0; i != NumElts; i += 2, ++j) {
2382 SDValue BitI = Elts[i];
2383 SDValue BitI1 = Elts[i+1];
2384 if (!isUndefOrEqual(BitI, j + NumElts/2))
2387 if (isUndefOrEqual(BitI1, NumElts))
2390 if (!isUndefOrEqual(BitI1, j + NumElts/2 + NumElts))
2398 bool X86::isUNPCKHMask(SDNode *N, bool V2IsSplat) {
2399 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2400 return ::isUNPCKHMask(N->op_begin(), N->getNumOperands(), V2IsSplat);
2403 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
2404 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
2406 bool X86::isUNPCKL_v_undef_Mask(SDNode *N) {
2407 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2409 unsigned NumElems = N->getNumOperands();
2410 if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16)
2413 for (unsigned i = 0, j = 0; i != NumElems; i += 2, ++j) {
2414 SDValue BitI = N->getOperand(i);
2415 SDValue BitI1 = N->getOperand(i+1);
2417 if (!isUndefOrEqual(BitI, j))
2419 if (!isUndefOrEqual(BitI1, j))
2426 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
2427 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
2429 bool X86::isUNPCKH_v_undef_Mask(SDNode *N) {
2430 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2432 unsigned NumElems = N->getNumOperands();
2433 if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16)
2436 for (unsigned i = 0, j = NumElems / 2; i != NumElems; i += 2, ++j) {
2437 SDValue BitI = N->getOperand(i);
2438 SDValue BitI1 = N->getOperand(i + 1);
2440 if (!isUndefOrEqual(BitI, j))
2442 if (!isUndefOrEqual(BitI1, j))
2449 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
2450 /// specifies a shuffle of elements that is suitable for input to MOVSS,
2451 /// MOVSD, and MOVD, i.e. setting the lowest element.
2452 template<class SDOperand>
2453 static bool isMOVLMask(SDOperand *Elts, unsigned NumElts) {
2454 if (NumElts != 2 && NumElts != 4)
2457 if (!isUndefOrEqual(Elts[0], NumElts))
2460 for (unsigned i = 1; i < NumElts; ++i) {
2461 if (!isUndefOrEqual(Elts[i], i))
2468 bool X86::isMOVLMask(SDNode *N) {
2469 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2470 return ::isMOVLMask(N->op_begin(), N->getNumOperands());
2473 /// isCommutedMOVL - Returns true if the shuffle mask is except the reverse
2474 /// of what x86 movss want. X86 movs requires the lowest element to be lowest
2475 /// element of vector 2 and the other elements to come from vector 1 in order.
2476 template<class SDOperand>
2477 static bool isCommutedMOVL(SDOperand *Ops, unsigned NumOps,
2478 bool V2IsSplat = false,
2479 bool V2IsUndef = false) {
2480 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16)
2483 if (!isUndefOrEqual(Ops[0], 0))
2486 for (unsigned i = 1; i < NumOps; ++i) {
2487 SDValue Arg = Ops[i];
2488 if (!(isUndefOrEqual(Arg, i+NumOps) ||
2489 (V2IsUndef && isUndefOrInRange(Arg, NumOps, NumOps*2)) ||
2490 (V2IsSplat && isUndefOrEqual(Arg, NumOps))))
2497 static bool isCommutedMOVL(SDNode *N, bool V2IsSplat = false,
2498 bool V2IsUndef = false) {
2499 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2500 return isCommutedMOVL(N->op_begin(), N->getNumOperands(),
2501 V2IsSplat, V2IsUndef);
2504 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
2505 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
2506 bool X86::isMOVSHDUPMask(SDNode *N) {
2507 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2509 if (N->getNumOperands() != 4)
2512 // Expect 1, 1, 3, 3
2513 for (unsigned i = 0; i < 2; ++i) {
2514 SDValue Arg = N->getOperand(i);
2515 if (Arg.getOpcode() == ISD::UNDEF) continue;
2516 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2517 unsigned Val = cast<ConstantSDNode>(Arg)->getZExtValue();
2518 if (Val != 1) return false;
2522 for (unsigned i = 2; i < 4; ++i) {
2523 SDValue Arg = N->getOperand(i);
2524 if (Arg.getOpcode() == ISD::UNDEF) continue;
2525 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2526 unsigned Val = cast<ConstantSDNode>(Arg)->getZExtValue();
2527 if (Val != 3) return false;
2531 // Don't use movshdup if it can be done with a shufps.
2535 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
2536 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
2537 bool X86::isMOVSLDUPMask(SDNode *N) {
2538 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2540 if (N->getNumOperands() != 4)
2543 // Expect 0, 0, 2, 2
2544 for (unsigned i = 0; i < 2; ++i) {
2545 SDValue Arg = N->getOperand(i);
2546 if (Arg.getOpcode() == ISD::UNDEF) continue;
2547 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2548 unsigned Val = cast<ConstantSDNode>(Arg)->getZExtValue();
2549 if (Val != 0) return false;
2553 for (unsigned i = 2; i < 4; ++i) {
2554 SDValue Arg = N->getOperand(i);
2555 if (Arg.getOpcode() == ISD::UNDEF) continue;
2556 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2557 unsigned Val = cast<ConstantSDNode>(Arg)->getZExtValue();
2558 if (Val != 2) return false;
2562 // Don't use movshdup if it can be done with a shufps.
2566 /// isIdentityMask - Return true if the specified VECTOR_SHUFFLE operand
2567 /// specifies a identity operation on the LHS or RHS.
2568 static bool isIdentityMask(SDNode *N, bool RHS = false) {
2569 unsigned NumElems = N->getNumOperands();
2570 for (unsigned i = 0; i < NumElems; ++i)
2571 if (!isUndefOrEqual(N->getOperand(i), i + (RHS ? NumElems : 0)))
2576 /// isSplatMask - Return true if the specified VECTOR_SHUFFLE operand specifies
2577 /// a splat of a single element.
2578 static bool isSplatMask(SDNode *N) {
2579 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2581 // This is a splat operation if each element of the permute is the same, and
2582 // if the value doesn't reference the second vector.
2583 unsigned NumElems = N->getNumOperands();
2584 SDValue ElementBase;
2586 for (; i != NumElems; ++i) {
2587 SDValue Elt = N->getOperand(i);
2588 if (isa<ConstantSDNode>(Elt)) {
2594 if (!ElementBase.getNode())
2597 for (; i != NumElems; ++i) {
2598 SDValue Arg = N->getOperand(i);
2599 if (Arg.getOpcode() == ISD::UNDEF) continue;
2600 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2601 if (Arg != ElementBase) return false;
2604 // Make sure it is a splat of the first vector operand.
2605 return cast<ConstantSDNode>(ElementBase)->getZExtValue() < NumElems;
2608 /// getSplatMaskEltNo - Given a splat mask, return the index to the element
2609 /// we want to splat.
2610 static SDValue getSplatMaskEltNo(SDNode *N) {
2611 assert(isSplatMask(N) && "Not a splat mask");
2612 unsigned NumElems = N->getNumOperands();
2613 SDValue ElementBase;
2615 for (; i != NumElems; ++i) {
2616 SDValue Elt = N->getOperand(i);
2617 if (isa<ConstantSDNode>(Elt))
2620 assert(0 && " No splat value found!");
2625 /// isSplatMask - Return true if the specified VECTOR_SHUFFLE operand specifies
2626 /// a splat of a single element and it's a 2 or 4 element mask.
2627 bool X86::isSplatMask(SDNode *N) {
2628 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2630 // We can only splat 64-bit, and 32-bit quantities with a single instruction.
2631 if (N->getNumOperands() != 4 && N->getNumOperands() != 2)
2633 return ::isSplatMask(N);
2636 /// isSplatLoMask - Return true if the specified VECTOR_SHUFFLE operand
2637 /// specifies a splat of zero element.
2638 bool X86::isSplatLoMask(SDNode *N) {
2639 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2641 for (unsigned i = 0, e = N->getNumOperands(); i < e; ++i)
2642 if (!isUndefOrEqual(N->getOperand(i), 0))
2647 /// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand
2648 /// specifies a shuffle of elements that is suitable for input to MOVDDUP.
2649 bool X86::isMOVDDUPMask(SDNode *N) {
2650 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2652 unsigned e = N->getNumOperands() / 2;
2653 for (unsigned i = 0; i < e; ++i)
2654 if (!isUndefOrEqual(N->getOperand(i), i))
2656 for (unsigned i = 0; i < e; ++i)
2657 if (!isUndefOrEqual(N->getOperand(e+i), i))
2662 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
2663 /// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUF* and SHUFP*
2665 unsigned X86::getShuffleSHUFImmediate(SDNode *N) {
2666 unsigned NumOperands = N->getNumOperands();
2667 unsigned Shift = (NumOperands == 4) ? 2 : 1;
2669 for (unsigned i = 0; i < NumOperands; ++i) {
2671 SDValue Arg = N->getOperand(NumOperands-i-1);
2672 if (Arg.getOpcode() != ISD::UNDEF)
2673 Val = cast<ConstantSDNode>(Arg)->getZExtValue();
2674 if (Val >= NumOperands) Val -= NumOperands;
2676 if (i != NumOperands - 1)
2683 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
2684 /// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUFHW
2686 unsigned X86::getShufflePSHUFHWImmediate(SDNode *N) {
2688 // 8 nodes, but we only care about the last 4.
2689 for (unsigned i = 7; i >= 4; --i) {
2691 SDValue Arg = N->getOperand(i);
2692 if (Arg.getOpcode() != ISD::UNDEF) {
2693 Val = cast<ConstantSDNode>(Arg)->getZExtValue();
2703 /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
2704 /// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUFLW
2706 unsigned X86::getShufflePSHUFLWImmediate(SDNode *N) {
2708 // 8 nodes, but we only care about the first 4.
2709 for (int i = 3; i >= 0; --i) {
2711 SDValue Arg = N->getOperand(i);
2712 if (Arg.getOpcode() != ISD::UNDEF)
2713 Val = cast<ConstantSDNode>(Arg)->getZExtValue();
2722 /// CommuteVectorShuffle - Swap vector_shuffle operands as well as
2723 /// values in ther permute mask.
2724 static SDValue CommuteVectorShuffle(SDValue Op, SDValue &V1,
2725 SDValue &V2, SDValue &Mask,
2726 SelectionDAG &DAG) {
2727 MVT VT = Op.getValueType();
2728 MVT MaskVT = Mask.getValueType();
2729 MVT EltVT = MaskVT.getVectorElementType();
2730 unsigned NumElems = Mask.getNumOperands();
2731 SmallVector<SDValue, 8> MaskVec;
2732 DebugLoc dl = Op.getDebugLoc();
2734 for (unsigned i = 0; i != NumElems; ++i) {
2735 SDValue Arg = Mask.getOperand(i);
2736 if (Arg.getOpcode() == ISD::UNDEF) {
2737 MaskVec.push_back(DAG.getUNDEF(EltVT));
2740 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2741 unsigned Val = cast<ConstantSDNode>(Arg)->getZExtValue();
2743 MaskVec.push_back(DAG.getConstant(Val + NumElems, EltVT));
2745 MaskVec.push_back(DAG.getConstant(Val - NumElems, EltVT));
2749 Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVT, &MaskVec[0], NumElems);
2750 return DAG.getNode(ISD::VECTOR_SHUFFLE, dl, VT, V1, V2, Mask);
2753 /// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming
2754 /// the two vector operands have swapped position.
2756 SDValue CommuteVectorShuffleMask(SDValue Mask, SelectionDAG &DAG, DebugLoc dl) {
2757 MVT MaskVT = Mask.getValueType();
2758 MVT EltVT = MaskVT.getVectorElementType();
2759 unsigned NumElems = Mask.getNumOperands();
2760 SmallVector<SDValue, 8> MaskVec;
2761 for (unsigned i = 0; i != NumElems; ++i) {
2762 SDValue Arg = Mask.getOperand(i);
2763 if (Arg.getOpcode() == ISD::UNDEF) {
2764 MaskVec.push_back(DAG.getUNDEF(EltVT));
2767 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2768 unsigned Val = cast<ConstantSDNode>(Arg)->getZExtValue();
2770 MaskVec.push_back(DAG.getConstant(Val + NumElems, EltVT));
2772 MaskVec.push_back(DAG.getConstant(Val - NumElems, EltVT));
2774 return DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVT, &MaskVec[0], NumElems);
2778 /// ShouldXformToMOVHLPS - Return true if the node should be transformed to
2779 /// match movhlps. The lower half elements should come from upper half of
2780 /// V1 (and in order), and the upper half elements should come from the upper
2781 /// half of V2 (and in order).
2782 static bool ShouldXformToMOVHLPS(SDNode *Mask) {
2783 unsigned NumElems = Mask->getNumOperands();
2786 for (unsigned i = 0, e = 2; i != e; ++i)
2787 if (!isUndefOrEqual(Mask->getOperand(i), i+2))
2789 for (unsigned i = 2; i != 4; ++i)
2790 if (!isUndefOrEqual(Mask->getOperand(i), i+4))
2795 /// isScalarLoadToVector - Returns true if the node is a scalar load that
2796 /// is promoted to a vector. It also returns the LoadSDNode by reference if
2798 static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = NULL) {
2799 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR)
2801 N = N->getOperand(0).getNode();
2802 if (!ISD::isNON_EXTLoad(N))
2805 *LD = cast<LoadSDNode>(N);
2809 /// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to
2810 /// match movlp{s|d}. The lower half elements should come from lower half of
2811 /// V1 (and in order), and the upper half elements should come from the upper
2812 /// half of V2 (and in order). And since V1 will become the source of the
2813 /// MOVLP, it must be either a vector load or a scalar load to vector.
2814 static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2, SDNode *Mask) {
2815 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1))
2817 // Is V2 is a vector load, don't do this transformation. We will try to use
2818 // load folding shufps op.
2819 if (ISD::isNON_EXTLoad(V2))
2822 unsigned NumElems = Mask->getNumOperands();
2823 if (NumElems != 2 && NumElems != 4)
2825 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
2826 if (!isUndefOrEqual(Mask->getOperand(i), i))
2828 for (unsigned i = NumElems/2; i != NumElems; ++i)
2829 if (!isUndefOrEqual(Mask->getOperand(i), i+NumElems))
2834 /// isSplatVector - Returns true if N is a BUILD_VECTOR node whose elements are
2836 static bool isSplatVector(SDNode *N) {
2837 if (N->getOpcode() != ISD::BUILD_VECTOR)
2840 SDValue SplatValue = N->getOperand(0);
2841 for (unsigned i = 1, e = N->getNumOperands(); i != e; ++i)
2842 if (N->getOperand(i) != SplatValue)
2847 /// isUndefShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
2849 static bool isUndefShuffle(SDNode *N) {
2850 if (N->getOpcode() != ISD::VECTOR_SHUFFLE)
2853 SDValue V1 = N->getOperand(0);
2854 SDValue V2 = N->getOperand(1);
2855 SDValue Mask = N->getOperand(2);
2856 unsigned NumElems = Mask.getNumOperands();
2857 for (unsigned i = 0; i != NumElems; ++i) {
2858 SDValue Arg = Mask.getOperand(i);
2859 if (Arg.getOpcode() != ISD::UNDEF) {
2860 unsigned Val = cast<ConstantSDNode>(Arg)->getZExtValue();
2861 if (Val < NumElems && V1.getOpcode() != ISD::UNDEF)
2863 else if (Val >= NumElems && V2.getOpcode() != ISD::UNDEF)
2870 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
2872 static inline bool isZeroNode(SDValue Elt) {
2873 return ((isa<ConstantSDNode>(Elt) &&
2874 cast<ConstantSDNode>(Elt)->getZExtValue() == 0) ||
2875 (isa<ConstantFPSDNode>(Elt) &&
2876 cast<ConstantFPSDNode>(Elt)->getValueAPF().isPosZero()));
2879 /// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
2880 /// to an zero vector.
2881 static bool isZeroShuffle(SDNode *N) {
2882 if (N->getOpcode() != ISD::VECTOR_SHUFFLE)
2885 SDValue V1 = N->getOperand(0);
2886 SDValue V2 = N->getOperand(1);
2887 SDValue Mask = N->getOperand(2);
2888 unsigned NumElems = Mask.getNumOperands();
2889 for (unsigned i = 0; i != NumElems; ++i) {
2890 SDValue Arg = Mask.getOperand(i);
2891 if (Arg.getOpcode() == ISD::UNDEF)
2894 unsigned Idx = cast<ConstantSDNode>(Arg)->getZExtValue();
2895 if (Idx < NumElems) {
2896 unsigned Opc = V1.getNode()->getOpcode();
2897 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode()))
2899 if (Opc != ISD::BUILD_VECTOR ||
2900 !isZeroNode(V1.getNode()->getOperand(Idx)))
2902 } else if (Idx >= NumElems) {
2903 unsigned Opc = V2.getNode()->getOpcode();
2904 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode()))
2906 if (Opc != ISD::BUILD_VECTOR ||
2907 !isZeroNode(V2.getNode()->getOperand(Idx - NumElems)))
2914 /// getZeroVector - Returns a vector of specified type with all zero elements.
2916 static SDValue getZeroVector(MVT VT, bool HasSSE2, SelectionDAG &DAG,
2918 assert(VT.isVector() && "Expected a vector type");
2920 // Always build zero vectors as <4 x i32> or <2 x i32> bitcasted to their dest
2921 // type. This ensures they get CSE'd.
2923 if (VT.getSizeInBits() == 64) { // MMX
2924 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
2925 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i32, Cst, Cst);
2926 } else if (HasSSE2) { // SSE2
2927 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
2928 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
2930 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
2931 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
2933 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vec);
2936 /// getOnesVector - Returns a vector of specified type with all bits set.
2938 static SDValue getOnesVector(MVT VT, SelectionDAG &DAG, DebugLoc dl) {
2939 assert(VT.isVector() && "Expected a vector type");
2941 // Always build ones vectors as <4 x i32> or <2 x i32> bitcasted to their dest
2942 // type. This ensures they get CSE'd.
2943 SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32);
2945 if (VT.getSizeInBits() == 64) // MMX
2946 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i32, Cst, Cst);
2948 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
2949 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vec);
2953 /// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements
2954 /// that point to V2 points to its first element.
2955 static SDValue NormalizeMask(SDValue Mask, SelectionDAG &DAG) {
2956 assert(Mask.getOpcode() == ISD::BUILD_VECTOR);
2958 bool Changed = false;
2959 SmallVector<SDValue, 8> MaskVec;
2960 unsigned NumElems = Mask.getNumOperands();
2961 for (unsigned i = 0; i != NumElems; ++i) {
2962 SDValue Arg = Mask.getOperand(i);
2963 if (Arg.getOpcode() != ISD::UNDEF) {
2964 unsigned Val = cast<ConstantSDNode>(Arg)->getZExtValue();
2965 if (Val > NumElems) {
2966 Arg = DAG.getConstant(NumElems, Arg.getValueType());
2970 MaskVec.push_back(Arg);
2974 Mask = DAG.getNode(ISD::BUILD_VECTOR, Mask.getDebugLoc(),
2975 Mask.getValueType(),
2976 &MaskVec[0], MaskVec.size());
2980 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
2981 /// operation of specified width.
2982 static SDValue getMOVLMask(unsigned NumElems, SelectionDAG &DAG, DebugLoc dl) {
2983 MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems);
2984 MVT BaseVT = MaskVT.getVectorElementType();
2986 SmallVector<SDValue, 8> MaskVec;
2987 MaskVec.push_back(DAG.getConstant(NumElems, BaseVT));
2988 for (unsigned i = 1; i != NumElems; ++i)
2989 MaskVec.push_back(DAG.getConstant(i, BaseVT));
2990 return DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVT,
2991 &MaskVec[0], MaskVec.size());
2994 /// getUnpacklMask - Returns a vector_shuffle mask for an unpackl operation
2995 /// of specified width.
2996 static SDValue getUnpacklMask(unsigned NumElems, SelectionDAG &DAG,
2998 MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems);
2999 MVT BaseVT = MaskVT.getVectorElementType();
3000 SmallVector<SDValue, 8> MaskVec;
3001 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
3002 MaskVec.push_back(DAG.getConstant(i, BaseVT));
3003 MaskVec.push_back(DAG.getConstant(i + NumElems, BaseVT));
3005 return DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVT,
3006 &MaskVec[0], MaskVec.size());
3009 /// getUnpackhMask - Returns a vector_shuffle mask for an unpackh operation
3010 /// of specified width.
3011 static SDValue getUnpackhMask(unsigned NumElems, SelectionDAG &DAG,
3013 MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems);
3014 MVT BaseVT = MaskVT.getVectorElementType();
3015 unsigned Half = NumElems/2;
3016 SmallVector<SDValue, 8> MaskVec;
3017 for (unsigned i = 0; i != Half; ++i) {
3018 MaskVec.push_back(DAG.getConstant(i + Half, BaseVT));
3019 MaskVec.push_back(DAG.getConstant(i + NumElems + Half, BaseVT));
3021 return DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVT,
3022 &MaskVec[0], MaskVec.size());
3025 /// getSwapEltZeroMask - Returns a vector_shuffle mask for a shuffle that swaps
3026 /// element #0 of a vector with the specified index, leaving the rest of the
3027 /// elements in place.
3028 static SDValue getSwapEltZeroMask(unsigned NumElems, unsigned DestElt,
3029 SelectionDAG &DAG, DebugLoc dl) {
3030 MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems);
3031 MVT BaseVT = MaskVT.getVectorElementType();
3032 SmallVector<SDValue, 8> MaskVec;
3033 // Element #0 of the result gets the elt we are replacing.
3034 MaskVec.push_back(DAG.getConstant(DestElt, BaseVT));
3035 for (unsigned i = 1; i != NumElems; ++i)
3036 MaskVec.push_back(DAG.getConstant(i == DestElt ? 0 : i, BaseVT));
3037 return DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVT,
3038 &MaskVec[0], MaskVec.size());
3041 /// PromoteSplat - Promote a splat of v4f32, v8i16 or v16i8 to v4i32.
3042 static SDValue PromoteSplat(SDValue Op, SelectionDAG &DAG, bool HasSSE2) {
3043 MVT PVT = HasSSE2 ? MVT::v4i32 : MVT::v4f32;
3044 MVT VT = Op.getValueType();
3047 SDValue V1 = Op.getOperand(0);
3048 SDValue Mask = Op.getOperand(2);
3049 unsigned MaskNumElems = Mask.getNumOperands();
3050 unsigned NumElems = MaskNumElems;
3051 DebugLoc dl = Op.getDebugLoc();
3052 // Special handling of v4f32 -> v4i32.
3053 if (VT != MVT::v4f32) {
3054 // Find which element we want to splat.
3055 SDNode* EltNoNode = getSplatMaskEltNo(Mask.getNode()).getNode();
3056 unsigned EltNo = cast<ConstantSDNode>(EltNoNode)->getZExtValue();
3057 // unpack elements to the correct location
3058 while (NumElems > 4) {
3059 if (EltNo < NumElems/2) {
3060 Mask = getUnpacklMask(MaskNumElems, DAG, dl);
3062 Mask = getUnpackhMask(MaskNumElems, DAG, dl);
3063 EltNo -= NumElems/2;
3065 V1 = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, VT, V1, V1, Mask);
3068 SDValue Cst = DAG.getConstant(EltNo, MVT::i32);
3069 Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
3072 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, PVT, V1);
3073 SDValue Shuffle = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, PVT, V1,
3074 DAG.getUNDEF(PVT), Mask);
3075 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Shuffle);
3078 /// isVectorLoad - Returns true if the node is a vector load, a scalar
3079 /// load that's promoted to vector, or a load bitcasted.
3080 static bool isVectorLoad(SDValue Op) {
3081 assert(Op.getValueType().isVector() && "Expected a vector type");
3082 if (Op.getOpcode() == ISD::SCALAR_TO_VECTOR ||
3083 Op.getOpcode() == ISD::BIT_CONVERT) {
3084 return isa<LoadSDNode>(Op.getOperand(0));
3086 return isa<LoadSDNode>(Op);
3090 /// CanonicalizeMovddup - Cannonicalize movddup shuffle to v2f64.
3092 static SDValue CanonicalizeMovddup(SDValue Op, SDValue V1, SDValue Mask,
3093 SelectionDAG &DAG, bool HasSSE3) {
3094 // If we have sse3 and shuffle has more than one use or input is a load, then
3095 // use movddup. Otherwise, use movlhps.
3096 bool UseMovddup = HasSSE3 && (!Op.hasOneUse() || isVectorLoad(V1));
3097 MVT PVT = UseMovddup ? MVT::v2f64 : MVT::v4f32;
3098 MVT VT = Op.getValueType();
3101 DebugLoc dl = Op.getDebugLoc();
3102 unsigned NumElems = PVT.getVectorNumElements();
3103 if (NumElems == 2) {
3104 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
3105 Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i32, Cst, Cst);
3107 assert(NumElems == 4);
3108 SDValue Cst0 = DAG.getTargetConstant(0, MVT::i32);
3109 SDValue Cst1 = DAG.getTargetConstant(1, MVT::i32);
3110 Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
3111 Cst0, Cst1, Cst0, Cst1);
3114 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, PVT, V1);
3115 SDValue Shuffle = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, PVT, V1,
3116 DAG.getUNDEF(PVT), Mask);
3117 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Shuffle);
3120 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
3121 /// vector of zero or undef vector. This produces a shuffle where the low
3122 /// element of V2 is swizzled into the zero/undef vector, landing at element
3123 /// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
3124 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
3125 bool isZero, bool HasSSE2,
3126 SelectionDAG &DAG) {
3127 DebugLoc dl = V2.getDebugLoc();
3128 MVT VT = V2.getValueType();
3130 ? getZeroVector(VT, HasSSE2, DAG, dl) : DAG.getUNDEF(VT);
3131 unsigned NumElems = V2.getValueType().getVectorNumElements();
3132 MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems);
3133 MVT EVT = MaskVT.getVectorElementType();
3134 SmallVector<SDValue, 16> MaskVec;
3135 for (unsigned i = 0; i != NumElems; ++i)
3136 if (i == Idx) // If this is the insertion idx, put the low elt of V2 here.
3137 MaskVec.push_back(DAG.getConstant(NumElems, EVT));
3139 MaskVec.push_back(DAG.getConstant(i, EVT));
3140 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVT,
3141 &MaskVec[0], MaskVec.size());
3142 return DAG.getNode(ISD::VECTOR_SHUFFLE, dl, VT, V1, V2, Mask);
3145 /// getNumOfConsecutiveZeros - Return the number of elements in a result of
3146 /// a shuffle that is zero.
3148 unsigned getNumOfConsecutiveZeros(SDValue Op, SDValue Mask,
3149 unsigned NumElems, bool Low,
3150 SelectionDAG &DAG) {
3151 unsigned NumZeros = 0;
3152 for (unsigned i = 0; i < NumElems; ++i) {
3153 unsigned Index = Low ? i : NumElems-i-1;
3154 SDValue Idx = Mask.getOperand(Index);
3155 if (Idx.getOpcode() == ISD::UNDEF) {
3159 SDValue Elt = DAG.getShuffleScalarElt(Op.getNode(), Index);
3160 if (Elt.getNode() && isZeroNode(Elt))
3168 /// isVectorShift - Returns true if the shuffle can be implemented as a
3169 /// logical left or right shift of a vector.
3170 static bool isVectorShift(SDValue Op, SDValue Mask, SelectionDAG &DAG,
3171 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
3172 unsigned NumElems = Mask.getNumOperands();
3175 unsigned NumZeros= getNumOfConsecutiveZeros(Op, Mask, NumElems, true, DAG);
3178 NumZeros = getNumOfConsecutiveZeros(Op, Mask, NumElems, false, DAG);
3183 bool SeenV1 = false;
3184 bool SeenV2 = false;
3185 for (unsigned i = NumZeros; i < NumElems; ++i) {
3186 unsigned Val = isLeft ? (i - NumZeros) : i;
3187 SDValue Idx = Mask.getOperand(isLeft ? i : (i - NumZeros));
3188 if (Idx.getOpcode() == ISD::UNDEF)
3190 unsigned Index = cast<ConstantSDNode>(Idx)->getZExtValue();
3191 if (Index < NumElems)
3200 if (SeenV1 && SeenV2)
3203 ShVal = SeenV1 ? Op.getOperand(0) : Op.getOperand(1);
3209 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
3211 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
3212 unsigned NumNonZero, unsigned NumZero,
3213 SelectionDAG &DAG, TargetLowering &TLI) {
3217 DebugLoc dl = Op.getDebugLoc();
3220 for (unsigned i = 0; i < 16; ++i) {
3221 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
3222 if (ThisIsNonZero && First) {
3224 V = getZeroVector(MVT::v8i16, true, DAG, dl);
3226 V = DAG.getUNDEF(MVT::v8i16);
3231 SDValue ThisElt(0, 0), LastElt(0, 0);
3232 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
3233 if (LastIsNonZero) {
3234 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
3235 MVT::i16, Op.getOperand(i-1));
3237 if (ThisIsNonZero) {
3238 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
3239 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
3240 ThisElt, DAG.getConstant(8, MVT::i8));
3242 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
3246 if (ThisElt.getNode())
3247 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
3248 DAG.getIntPtrConstant(i/2));
3252 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, V);
3255 /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
3257 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
3258 unsigned NumNonZero, unsigned NumZero,
3259 SelectionDAG &DAG, TargetLowering &TLI) {
3263 DebugLoc dl = Op.getDebugLoc();
3266 for (unsigned i = 0; i < 8; ++i) {
3267 bool isNonZero = (NonZeros & (1 << i)) != 0;
3271 V = getZeroVector(MVT::v8i16, true, DAG, dl);
3273 V = DAG.getUNDEF(MVT::v8i16);
3276 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
3277 MVT::v8i16, V, Op.getOperand(i),
3278 DAG.getIntPtrConstant(i));
3285 /// getVShift - Return a vector logical shift node.
3287 static SDValue getVShift(bool isLeft, MVT VT, SDValue SrcOp,
3288 unsigned NumBits, SelectionDAG &DAG,
3289 const TargetLowering &TLI, DebugLoc dl) {
3290 bool isMMX = VT.getSizeInBits() == 64;
3291 MVT ShVT = isMMX ? MVT::v1i64 : MVT::v2i64;
3292 unsigned Opc = isLeft ? X86ISD::VSHL : X86ISD::VSRL;
3293 SrcOp = DAG.getNode(ISD::BIT_CONVERT, dl, ShVT, SrcOp);
3294 return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
3295 DAG.getNode(Opc, dl, ShVT, SrcOp,
3296 DAG.getConstant(NumBits, TLI.getShiftAmountTy())));
3300 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) {
3301 DebugLoc dl = Op.getDebugLoc();
3302 // All zero's are handled with pxor, all one's are handled with pcmpeqd.
3303 if (ISD::isBuildVectorAllZeros(Op.getNode())
3304 || ISD::isBuildVectorAllOnes(Op.getNode())) {
3305 // Canonicalize this to either <4 x i32> or <2 x i32> (SSE vs MMX) to
3306 // 1) ensure the zero vectors are CSE'd, and 2) ensure that i64 scalars are
3307 // eliminated on x86-32 hosts.
3308 if (Op.getValueType() == MVT::v4i32 || Op.getValueType() == MVT::v2i32)
3311 if (ISD::isBuildVectorAllOnes(Op.getNode()))
3312 return getOnesVector(Op.getValueType(), DAG, dl);
3313 return getZeroVector(Op.getValueType(), Subtarget->hasSSE2(), DAG, dl);
3316 MVT VT = Op.getValueType();
3317 MVT EVT = VT.getVectorElementType();
3318 unsigned EVTBits = EVT.getSizeInBits();
3320 unsigned NumElems = Op.getNumOperands();
3321 unsigned NumZero = 0;
3322 unsigned NumNonZero = 0;
3323 unsigned NonZeros = 0;
3324 bool IsAllConstants = true;
3325 SmallSet<SDValue, 8> Values;
3326 for (unsigned i = 0; i < NumElems; ++i) {
3327 SDValue Elt = Op.getOperand(i);
3328 if (Elt.getOpcode() == ISD::UNDEF)
3331 if (Elt.getOpcode() != ISD::Constant &&
3332 Elt.getOpcode() != ISD::ConstantFP)
3333 IsAllConstants = false;
3334 if (isZeroNode(Elt))
3337 NonZeros |= (1 << i);
3342 if (NumNonZero == 0) {
3343 // All undef vector. Return an UNDEF. All zero vectors were handled above.
3344 return DAG.getUNDEF(VT);
3347 // Special case for single non-zero, non-undef, element.
3348 if (NumNonZero == 1 && NumElems <= 4) {
3349 unsigned Idx = CountTrailingZeros_32(NonZeros);
3350 SDValue Item = Op.getOperand(Idx);
3352 // If this is an insertion of an i64 value on x86-32, and if the top bits of
3353 // the value are obviously zero, truncate the value to i32 and do the
3354 // insertion that way. Only do this if the value is non-constant or if the
3355 // value is a constant being inserted into element 0. It is cheaper to do
3356 // a constant pool load than it is to do a movd + shuffle.
3357 if (EVT == MVT::i64 && !Subtarget->is64Bit() &&
3358 (!IsAllConstants || Idx == 0)) {
3359 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
3360 // Handle MMX and SSE both.
3361 MVT VecVT = VT == MVT::v2i64 ? MVT::v4i32 : MVT::v2i32;
3362 unsigned VecElts = VT == MVT::v2i64 ? 4 : 2;
3364 // Truncate the value (which may itself be a constant) to i32, and
3365 // convert it to a vector with movd (S2V+shuffle to zero extend).
3366 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
3367 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
3368 Item = getShuffleVectorZeroOrUndef(Item, 0, true,
3369 Subtarget->hasSSE2(), DAG);
3371 // Now we have our 32-bit value zero extended in the low element of
3372 // a vector. If Idx != 0, swizzle it into place.
3375 Item, DAG.getUNDEF(Item.getValueType()),
3376 getSwapEltZeroMask(VecElts, Idx, DAG, dl)
3378 Item = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, VecVT, Ops, 3);
3380 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Item);
3384 // If we have a constant or non-constant insertion into the low element of
3385 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
3386 // the rest of the elements. This will be matched as movd/movq/movss/movsd
3387 // depending on what the source datatype is. Because we can only get here
3388 // when NumElems <= 4, this only needs to handle i32/f32/i64/f64.
3390 // Don't do this for i64 values on x86-32.
3391 (EVT != MVT::i64 || Subtarget->is64Bit())) {
3392 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
3393 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
3394 return getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0,
3395 Subtarget->hasSSE2(), DAG);
3398 // Is it a vector logical left shift?
3399 if (NumElems == 2 && Idx == 1 &&
3400 isZeroNode(Op.getOperand(0)) && !isZeroNode(Op.getOperand(1))) {
3401 unsigned NumBits = VT.getSizeInBits();
3402 return getVShift(true, VT,
3403 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
3404 VT, Op.getOperand(1)),
3405 NumBits/2, DAG, *this, dl);
3408 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
3411 // Otherwise, if this is a vector with i32 or f32 elements, and the element
3412 // is a non-constant being inserted into an element other than the low one,
3413 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
3414 // movd/movss) to move this into the low element, then shuffle it into
3416 if (EVTBits == 32) {
3417 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
3419 // Turn it into a shuffle of zero and zero-extended scalar to vector.
3420 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0,
3421 Subtarget->hasSSE2(), DAG);
3422 MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems);
3423 MVT MaskEVT = MaskVT.getVectorElementType();
3424 SmallVector<SDValue, 8> MaskVec;
3425 for (unsigned i = 0; i < NumElems; i++)
3426 MaskVec.push_back(DAG.getConstant((i == Idx) ? 0 : 1, MaskEVT));
3427 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVT,
3428 &MaskVec[0], MaskVec.size());
3429 return DAG.getNode(ISD::VECTOR_SHUFFLE, dl, VT, Item,
3430 DAG.getUNDEF(VT), Mask);
3434 // Splat is obviously ok. Let legalizer expand it to a shuffle.
3435 if (Values.size() == 1)
3438 // A vector full of immediates; various special cases are already
3439 // handled, so this is best done with a single constant-pool load.
3443 // Let legalizer expand 2-wide build_vectors.
3444 if (EVTBits == 64) {
3445 if (NumNonZero == 1) {
3446 // One half is zero or undef.
3447 unsigned Idx = CountTrailingZeros_32(NonZeros);
3448 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
3449 Op.getOperand(Idx));
3450 return getShuffleVectorZeroOrUndef(V2, Idx, true,
3451 Subtarget->hasSSE2(), DAG);
3456 // If element VT is < 32 bits, convert it to inserts into a zero vector.
3457 if (EVTBits == 8 && NumElems == 16) {
3458 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
3460 if (V.getNode()) return V;
3463 if (EVTBits == 16 && NumElems == 8) {
3464 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
3466 if (V.getNode()) return V;
3469 // If element VT is == 32 bits, turn it into a number of shuffles.
3470 SmallVector<SDValue, 8> V;
3472 if (NumElems == 4 && NumZero > 0) {
3473 for (unsigned i = 0; i < 4; ++i) {
3474 bool isZero = !(NonZeros & (1 << i));
3476 V[i] = getZeroVector(VT, Subtarget->hasSSE2(), DAG, dl);
3478 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
3481 for (unsigned i = 0; i < 2; ++i) {
3482 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
3485 V[i] = V[i*2]; // Must be a zero vector.
3488 V[i] = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, VT, V[i*2+1], V[i*2],
3489 getMOVLMask(NumElems, DAG, dl));
3492 V[i] = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, VT, V[i*2], V[i*2+1],
3493 getMOVLMask(NumElems, DAG, dl));
3496 V[i] = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, VT, V[i*2], V[i*2+1],
3497 getUnpacklMask(NumElems, DAG, dl));
3502 MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems);
3503 MVT EVT = MaskVT.getVectorElementType();
3504 SmallVector<SDValue, 8> MaskVec;
3505 bool Reverse = (NonZeros & 0x3) == 2;
3506 for (unsigned i = 0; i < 2; ++i)
3508 MaskVec.push_back(DAG.getConstant(1-i, EVT));
3510 MaskVec.push_back(DAG.getConstant(i, EVT));
3511 Reverse = ((NonZeros & (0x3 << 2)) >> 2) == 2;
3512 for (unsigned i = 0; i < 2; ++i)
3514 MaskVec.push_back(DAG.getConstant(1-i+NumElems, EVT));
3516 MaskVec.push_back(DAG.getConstant(i+NumElems, EVT));
3517 SDValue ShufMask = DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVT,
3518 &MaskVec[0], MaskVec.size());
3519 return DAG.getNode(ISD::VECTOR_SHUFFLE, dl, VT, V[0], V[1], ShufMask);
3522 if (Values.size() > 2) {
3523 // Expand into a number of unpckl*.
3525 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
3526 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
3527 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
3528 SDValue UnpckMask = getUnpacklMask(NumElems, DAG, dl);
3529 for (unsigned i = 0; i < NumElems; ++i)
3530 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
3532 while (NumElems != 0) {
3533 for (unsigned i = 0; i < NumElems; ++i)
3534 V[i] = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, VT, V[i], V[i + NumElems],
3544 // v8i16 shuffles - Prefer shuffles in the following order:
3545 // 1. [all] pshuflw, pshufhw, optional move
3546 // 2. [ssse3] 1 x pshufb
3547 // 3. [ssse3] 2 x pshufb + 1 x por
3548 // 4. [all] mov + pshuflw + pshufhw + N x (pextrw + pinsrw)
3550 SDValue LowerVECTOR_SHUFFLEv8i16(SDValue V1, SDValue V2,
3551 SDValue PermMask, SelectionDAG &DAG,
3552 X86TargetLowering &TLI, DebugLoc dl) {
3553 SmallVector<SDValue, 8> MaskElts(PermMask.getNode()->op_begin(),
3554 PermMask.getNode()->op_end());
3555 SmallVector<int, 8> MaskVals;
3557 // Determine if more than 1 of the words in each of the low and high quadwords
3558 // of the result come from the same quadword of one of the two inputs. Undef
3559 // mask values count as coming from any quadword, for better codegen.
3560 SmallVector<unsigned, 4> LoQuad(4);
3561 SmallVector<unsigned, 4> HiQuad(4);
3562 BitVector InputQuads(4);
3563 for (unsigned i = 0; i < 8; ++i) {
3564 SmallVectorImpl<unsigned> &Quad = i < 4 ? LoQuad : HiQuad;
3565 SDValue Elt = MaskElts[i];
3566 int EltIdx = Elt.getOpcode() == ISD::UNDEF ? -1 :
3567 cast<ConstantSDNode>(Elt)->getZExtValue();
3568 MaskVals.push_back(EltIdx);
3577 InputQuads.set(EltIdx / 4);
3580 int BestLoQuad = -1;
3581 unsigned MaxQuad = 1;
3582 for (unsigned i = 0; i < 4; ++i) {
3583 if (LoQuad[i] > MaxQuad) {
3585 MaxQuad = LoQuad[i];
3589 int BestHiQuad = -1;
3591 for (unsigned i = 0; i < 4; ++i) {
3592 if (HiQuad[i] > MaxQuad) {
3594 MaxQuad = HiQuad[i];
3598 // For SSSE3, If all 8 words of the result come from only 1 quadword of each
3599 // of the two input vectors, shuffle them into one input vector so only a
3600 // single pshufb instruction is necessary. If There are more than 2 input
3601 // quads, disable the next transformation since it does not help SSSE3.
3602 bool V1Used = InputQuads[0] || InputQuads[1];
3603 bool V2Used = InputQuads[2] || InputQuads[3];
3604 if (TLI.getSubtarget()->hasSSSE3()) {
3605 if (InputQuads.count() == 2 && V1Used && V2Used) {
3606 BestLoQuad = InputQuads.find_first();
3607 BestHiQuad = InputQuads.find_next(BestLoQuad);
3609 if (InputQuads.count() > 2) {
3615 // If BestLoQuad or BestHiQuad are set, shuffle the quads together and update
3616 // the shuffle mask. If a quad is scored as -1, that means that it contains
3617 // words from all 4 input quadwords.
3619 if (BestLoQuad >= 0 || BestHiQuad >= 0) {
3620 SmallVector<SDValue,8> MaskV;
3621 MaskV.push_back(DAG.getConstant(BestLoQuad < 0 ? 0 : BestLoQuad, MVT::i64));
3622 MaskV.push_back(DAG.getConstant(BestHiQuad < 0 ? 1 : BestHiQuad, MVT::i64));
3623 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i64, &MaskV[0], 2);
3625 NewV = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, MVT::v2i64,
3626 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64, V1),
3627 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64, V2), Mask);
3628 NewV = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, NewV);
3630 // Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the
3631 // source words for the shuffle, to aid later transformations.
3632 bool AllWordsInNewV = true;
3633 for (unsigned i = 0; i != 8; ++i) {
3634 int idx = MaskVals[i];
3635 if (idx < 0 || (idx/4) == BestLoQuad || (idx/4) == BestHiQuad)
3637 AllWordsInNewV = false;
3641 bool pshuflw = AllWordsInNewV, pshufhw = AllWordsInNewV;
3642 if (AllWordsInNewV) {
3643 for (int i = 0; i != 8; ++i) {
3644 int idx = MaskVals[i];
3647 idx = MaskVals[i] = (idx / 4) == BestLoQuad ? (idx & 3) : (idx & 3) + 4;
3648 if ((idx != i) && idx < 4)
3650 if ((idx != i) && idx > 3)
3659 // If we've eliminated the use of V2, and the new mask is a pshuflw or
3660 // pshufhw, that's as cheap as it gets. Return the new shuffle.
3661 if (pshufhw || pshuflw) {
3663 for (unsigned i = 0; i != 8; ++i)
3664 MaskV.push_back((MaskVals[i] < 0) ? DAG.getUNDEF(MVT::i16)
3665 : DAG.getConstant(MaskVals[i],
3667 return DAG.getNode(ISD::VECTOR_SHUFFLE, dl, MVT::v8i16, NewV,
3668 DAG.getUNDEF(MVT::v8i16),
3669 DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i16,
3674 // If we have SSSE3, and all words of the result are from 1 input vector,
3675 // case 2 is generated, otherwise case 3 is generated. If no SSSE3
3676 // is present, fall back to case 4.
3677 if (TLI.getSubtarget()->hasSSSE3()) {
3678 SmallVector<SDValue,16> pshufbMask;
3680 // If we have elements from both input vectors, set the high bit of the
3681 // shuffle mask element to zero out elements that come from V2 in the V1
3682 // mask, and elements that come from V1 in the V2 mask, so that the two
3683 // results can be OR'd together.
3684 bool TwoInputs = V1Used && V2Used;
3685 for (unsigned i = 0; i != 8; ++i) {
3686 int EltIdx = MaskVals[i] * 2;
3687 if (TwoInputs && (EltIdx >= 16)) {
3688 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
3689 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
3692 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
3693 pshufbMask.push_back(DAG.getConstant(EltIdx+1, MVT::i8));
3695 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, V1);
3696 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
3697 DAG.getNode(ISD::BUILD_VECTOR, dl,
3698 MVT::v16i8, &pshufbMask[0], 16));
3700 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, V1);
3702 // Calculate the shuffle mask for the second input, shuffle it, and
3703 // OR it with the first shuffled input.
3705 for (unsigned i = 0; i != 8; ++i) {
3706 int EltIdx = MaskVals[i] * 2;
3708 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
3709 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
3712 pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8));
3713 pshufbMask.push_back(DAG.getConstant(EltIdx - 15, MVT::i8));
3715 V2 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, V2);
3716 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
3717 DAG.getNode(ISD::BUILD_VECTOR, dl,
3718 MVT::v16i8, &pshufbMask[0], 16));
3719 V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
3720 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, V1);
3723 // If BestLoQuad >= 0, generate a pshuflw to put the low elements in order,
3724 // and update MaskVals with new element order.
3725 BitVector InOrder(8);
3726 if (BestLoQuad >= 0) {
3727 SmallVector<SDValue, 8> MaskV;
3728 for (int i = 0; i != 4; ++i) {
3729 int idx = MaskVals[i];
3731 MaskV.push_back(DAG.getUNDEF(MVT::i16));
3733 } else if ((idx / 4) == BestLoQuad) {
3734 MaskV.push_back(DAG.getConstant(idx & 3, MVT::i16));
3737 MaskV.push_back(DAG.getUNDEF(MVT::i16));
3740 for (unsigned i = 4; i != 8; ++i)
3741 MaskV.push_back(DAG.getConstant(i, MVT::i16));
3742 NewV = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, MVT::v8i16, NewV,
3743 DAG.getUNDEF(MVT::v8i16),
3744 DAG.getNode(ISD::BUILD_VECTOR, dl,
3745 MVT::v8i16, &MaskV[0], 8));
3748 // If BestHi >= 0, generate a pshufhw to put the high elements in order,
3749 // and update MaskVals with the new element order.
3750 if (BestHiQuad >= 0) {
3751 SmallVector<SDValue, 8> MaskV;
3752 for (unsigned i = 0; i != 4; ++i)
3753 MaskV.push_back(DAG.getConstant(i, MVT::i16));
3754 for (unsigned i = 4; i != 8; ++i) {
3755 int idx = MaskVals[i];
3757 MaskV.push_back(DAG.getUNDEF(MVT::i16));
3759 } else if ((idx / 4) == BestHiQuad) {
3760 MaskV.push_back(DAG.getConstant((idx & 3) + 4, MVT::i16));
3763 MaskV.push_back(DAG.getUNDEF(MVT::i16));
3766 NewV = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, MVT::v8i16, NewV,
3767 DAG.getUNDEF(MVT::v8i16),
3768 DAG.getNode(ISD::BUILD_VECTOR, dl,
3769 MVT::v8i16, &MaskV[0], 8));
3772 // In case BestHi & BestLo were both -1, which means each quadword has a word
3773 // from each of the four input quadwords, calculate the InOrder bitvector now
3774 // before falling through to the insert/extract cleanup.
3775 if (BestLoQuad == -1 && BestHiQuad == -1) {
3777 for (int i = 0; i != 8; ++i)
3778 if (MaskVals[i] < 0 || MaskVals[i] == i)
3782 // The other elements are put in the right place using pextrw and pinsrw.
3783 for (unsigned i = 0; i != 8; ++i) {
3786 int EltIdx = MaskVals[i];
3789 SDValue ExtOp = (EltIdx < 8)
3790 ? DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1,
3791 DAG.getIntPtrConstant(EltIdx))
3792 : DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2,
3793 DAG.getIntPtrConstant(EltIdx - 8));
3794 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp,
3795 DAG.getIntPtrConstant(i));
3800 // v16i8 shuffles - Prefer shuffles in the following order:
3801 // 1. [ssse3] 1 x pshufb
3802 // 2. [ssse3] 2 x pshufb + 1 x por
3803 // 3. [all] v8i16 shuffle + N x pextrw + rotate + pinsrw
3805 SDValue LowerVECTOR_SHUFFLEv16i8(SDValue V1, SDValue V2,
3806 SDValue PermMask, SelectionDAG &DAG,
3807 X86TargetLowering &TLI, DebugLoc dl) {
3808 SmallVector<SDValue, 16> MaskElts(PermMask.getNode()->op_begin(),
3809 PermMask.getNode()->op_end());
3810 SmallVector<int, 16> MaskVals;
3812 // If we have SSSE3, case 1 is generated when all result bytes come from
3813 // one of the inputs. Otherwise, case 2 is generated. If no SSSE3 is
3814 // present, fall back to case 3.
3815 // FIXME: kill V2Only once shuffles are canonizalized by getNode.
3818 for (unsigned i = 0; i < 16; ++i) {
3819 SDValue Elt = MaskElts[i];
3820 int EltIdx = Elt.getOpcode() == ISD::UNDEF ? -1 :
3821 cast<ConstantSDNode>(Elt)->getZExtValue();
3822 MaskVals.push_back(EltIdx);
3831 // If SSSE3, use 1 pshufb instruction per vector with elements in the result.
3832 if (TLI.getSubtarget()->hasSSSE3()) {
3833 SmallVector<SDValue,16> pshufbMask;
3835 // If all result elements are from one input vector, then only translate
3836 // undef mask values to 0x80 (zero out result) in the pshufb mask.
3838 // Otherwise, we have elements from both input vectors, and must zero out
3839 // elements that come from V2 in the first mask, and V1 in the second mask
3840 // so that we can OR them together.
3841 bool TwoInputs = !(V1Only || V2Only);
3842 for (unsigned i = 0; i != 16; ++i) {
3843 int EltIdx = MaskVals[i];
3844 if (EltIdx < 0 || (TwoInputs && EltIdx >= 16)) {
3845 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
3848 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
3850 // If all the elements are from V2, assign it to V1 and return after
3851 // building the first pshufb.
3854 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
3855 DAG.getNode(ISD::BUILD_VECTOR, dl,
3856 MVT::v16i8, &pshufbMask[0], 16));
3860 // Calculate the shuffle mask for the second input, shuffle it, and
3861 // OR it with the first shuffled input.
3863 for (unsigned i = 0; i != 16; ++i) {
3864 int EltIdx = MaskVals[i];
3866 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
3869 pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8));
3871 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
3872 DAG.getNode(ISD::BUILD_VECTOR, dl,
3873 MVT::v16i8, &pshufbMask[0], 16));
3874 return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
3877 // No SSSE3 - Calculate in place words and then fix all out of place words
3878 // With 0-16 extracts & inserts. Worst case is 16 bytes out of order from
3879 // the 16 different words that comprise the two doublequadword input vectors.
3880 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, V1);
3881 V2 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, V2);
3882 SDValue NewV = V2Only ? V2 : V1;
3883 for (int i = 0; i != 8; ++i) {
3884 int Elt0 = MaskVals[i*2];
3885 int Elt1 = MaskVals[i*2+1];
3887 // This word of the result is all undef, skip it.
3888 if (Elt0 < 0 && Elt1 < 0)
3891 // This word of the result is already in the correct place, skip it.
3892 if (V1Only && (Elt0 == i*2) && (Elt1 == i*2+1))
3894 if (V2Only && (Elt0 == i*2+16) && (Elt1 == i*2+17))
3897 SDValue Elt0Src = Elt0 < 16 ? V1 : V2;
3898 SDValue Elt1Src = Elt1 < 16 ? V1 : V2;
3901 // If Elt1 is defined, extract it from the appropriate source. If the
3902 // source byte is not also odd, shift the extracted word left 8 bits.
3904 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
3905 DAG.getIntPtrConstant(Elt1 / 2));
3906 if ((Elt1 & 1) == 0)
3907 InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt,
3908 DAG.getConstant(8, TLI.getShiftAmountTy()));
3910 // If Elt0 is defined, extract it from the appropriate source. If the
3911 // source byte is not also even, shift the extracted word right 8 bits. If
3912 // Elt1 was also defined, OR the extracted values together before
3913 // inserting them in the result.
3915 SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16,
3916 Elt0Src, DAG.getIntPtrConstant(Elt0 / 2));
3917 if ((Elt0 & 1) != 0)
3918 InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0,
3919 DAG.getConstant(8, TLI.getShiftAmountTy()));
3920 InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0)
3923 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
3924 DAG.getIntPtrConstant(i));
3926 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, NewV);
3929 /// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide
3930 /// ones, or rewriting v4i32 / v2f32 as 2 wide ones if possible. This can be
3931 /// done when every pair / quad of shuffle mask elements point to elements in
3932 /// the right sequence. e.g.
3933 /// vector_shuffle <>, <>, < 3, 4, | 10, 11, | 0, 1, | 14, 15>
3935 SDValue RewriteAsNarrowerShuffle(SDValue V1, SDValue V2,
3937 SDValue PermMask, SelectionDAG &DAG,
3938 TargetLowering &TLI, DebugLoc dl) {
3939 unsigned NumElems = PermMask.getNumOperands();
3940 unsigned NewWidth = (NumElems == 4) ? 2 : 4;
3941 MVT MaskVT = MVT::getIntVectorWithNumElements(NewWidth);
3942 MVT MaskEltVT = MaskVT.getVectorElementType();
3944 switch (VT.getSimpleVT()) {
3945 default: assert(false && "Unexpected!");
3946 case MVT::v4f32: NewVT = MVT::v2f64; break;
3947 case MVT::v4i32: NewVT = MVT::v2i64; break;
3948 case MVT::v8i16: NewVT = MVT::v4i32; break;
3949 case MVT::v16i8: NewVT = MVT::v4i32; break;
3952 if (NewWidth == 2) {
3958 unsigned Scale = NumElems / NewWidth;
3959 SmallVector<SDValue, 8> MaskVec;
3960 for (unsigned i = 0; i < NumElems; i += Scale) {
3961 unsigned StartIdx = ~0U;
3962 for (unsigned j = 0; j < Scale; ++j) {
3963 SDValue Elt = PermMask.getOperand(i+j);
3964 if (Elt.getOpcode() == ISD::UNDEF)
3966 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getZExtValue();
3967 if (StartIdx == ~0U)
3968 StartIdx = EltIdx - (EltIdx % Scale);
3969 if (EltIdx != StartIdx + j)
3972 if (StartIdx == ~0U)
3973 MaskVec.push_back(DAG.getUNDEF(MaskEltVT));
3975 MaskVec.push_back(DAG.getConstant(StartIdx / Scale, MaskEltVT));
3978 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, NewVT, V1);
3979 V2 = DAG.getNode(ISD::BIT_CONVERT, dl, NewVT, V2);
3980 return DAG.getNode(ISD::VECTOR_SHUFFLE, dl, NewVT, V1, V2,
3981 DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVT,
3982 &MaskVec[0], MaskVec.size()));
3985 /// getVZextMovL - Return a zero-extending vector move low node.
3987 static SDValue getVZextMovL(MVT VT, MVT OpVT,
3988 SDValue SrcOp, SelectionDAG &DAG,
3989 const X86Subtarget *Subtarget, DebugLoc dl) {
3990 if (VT == MVT::v2f64 || VT == MVT::v4f32) {
3991 LoadSDNode *LD = NULL;
3992 if (!isScalarLoadToVector(SrcOp.getNode(), &LD))
3993 LD = dyn_cast<LoadSDNode>(SrcOp);
3995 // movssrr and movsdrr do not clear top bits. Try to use movd, movq
3997 MVT EVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32;
3998 if ((EVT != MVT::i64 || Subtarget->is64Bit()) &&
3999 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR &&
4000 SrcOp.getOperand(0).getOpcode() == ISD::BIT_CONVERT &&
4001 SrcOp.getOperand(0).getOperand(0).getValueType() == EVT) {
4003 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32;
4004 return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
4005 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
4006 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
4014 return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
4015 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
4016 DAG.getNode(ISD::BIT_CONVERT, dl,
4020 /// LowerVECTOR_SHUFFLE_4wide - Handle all 4 wide cases with a number of
4023 LowerVECTOR_SHUFFLE_4wide(SDValue V1, SDValue V2,
4024 SDValue PermMask, MVT VT, SelectionDAG &DAG,
4026 MVT MaskVT = PermMask.getValueType();
4027 MVT MaskEVT = MaskVT.getVectorElementType();
4028 SmallVector<std::pair<int, int>, 8> Locs;
4030 SmallVector<SDValue, 8> Mask1(4, DAG.getUNDEF(MaskEVT));
4033 for (unsigned i = 0; i != 4; ++i) {
4034 SDValue Elt = PermMask.getOperand(i);
4035 if (Elt.getOpcode() == ISD::UNDEF) {
4036 Locs[i] = std::make_pair(-1, -1);
4038 unsigned Val = cast<ConstantSDNode>(Elt)->getZExtValue();
4039 assert(Val < 8 && "Invalid VECTOR_SHUFFLE index!");
4041 Locs[i] = std::make_pair(0, NumLo);
4045 Locs[i] = std::make_pair(1, NumHi);
4047 Mask1[2+NumHi] = Elt;
4053 if (NumLo <= 2 && NumHi <= 2) {
4054 // If no more than two elements come from either vector. This can be
4055 // implemented with two shuffles. First shuffle gather the elements.
4056 // The second shuffle, which takes the first shuffle as both of its
4057 // vector operands, put the elements into the right order.
4058 V1 = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, VT, V1, V2,
4059 DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVT,
4060 &Mask1[0], Mask1.size()));
4062 SmallVector<SDValue, 8> Mask2(4, DAG.getUNDEF(MaskEVT));
4063 for (unsigned i = 0; i != 4; ++i) {
4064 if (Locs[i].first == -1)
4067 unsigned Idx = (i < 2) ? 0 : 4;
4068 Idx += Locs[i].first * 2 + Locs[i].second;
4069 Mask2[i] = DAG.getConstant(Idx, MaskEVT);
4073 return DAG.getNode(ISD::VECTOR_SHUFFLE, dl, VT, V1, V1,
4074 DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVT,
4075 &Mask2[0], Mask2.size()));
4076 } else if (NumLo == 3 || NumHi == 3) {
4077 // Otherwise, we must have three elements from one vector, call it X, and
4078 // one element from the other, call it Y. First, use a shufps to build an
4079 // intermediate vector with the one element from Y and the element from X
4080 // that will be in the same half in the final destination (the indexes don't
4081 // matter). Then, use a shufps to build the final vector, taking the half
4082 // containing the element from Y from the intermediate, and the other half
4085 // Normalize it so the 3 elements come from V1.
4086 PermMask = CommuteVectorShuffleMask(PermMask, DAG, dl);
4090 // Find the element from V2.
4092 for (HiIndex = 0; HiIndex < 3; ++HiIndex) {
4093 SDValue Elt = PermMask.getOperand(HiIndex);
4094 if (Elt.getOpcode() == ISD::UNDEF)
4096 unsigned Val = cast<ConstantSDNode>(Elt)->getZExtValue();
4101 Mask1[0] = PermMask.getOperand(HiIndex);
4102 Mask1[1] = DAG.getUNDEF(MaskEVT);
4103 Mask1[2] = PermMask.getOperand(HiIndex^1);
4104 Mask1[3] = DAG.getUNDEF(MaskEVT);
4105 V2 = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, VT, V1, V2,
4106 DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVT, &Mask1[0], 4));
4109 Mask1[0] = PermMask.getOperand(0);
4110 Mask1[1] = PermMask.getOperand(1);
4111 Mask1[2] = DAG.getConstant(HiIndex & 1 ? 6 : 4, MaskEVT);
4112 Mask1[3] = DAG.getConstant(HiIndex & 1 ? 4 : 6, MaskEVT);
4113 return DAG.getNode(ISD::VECTOR_SHUFFLE, dl, VT, V1, V2,
4114 DAG.getNode(ISD::BUILD_VECTOR, dl,
4115 MaskVT, &Mask1[0], 4));
4117 Mask1[0] = DAG.getConstant(HiIndex & 1 ? 2 : 0, MaskEVT);
4118 Mask1[1] = DAG.getConstant(HiIndex & 1 ? 0 : 2, MaskEVT);
4119 Mask1[2] = PermMask.getOperand(2);
4120 Mask1[3] = PermMask.getOperand(3);
4121 if (Mask1[2].getOpcode() != ISD::UNDEF)
4123 DAG.getConstant(cast<ConstantSDNode>(Mask1[2])->getZExtValue()+4,
4125 if (Mask1[3].getOpcode() != ISD::UNDEF)
4127 DAG.getConstant(cast<ConstantSDNode>(Mask1[3])->getZExtValue()+4,
4129 return DAG.getNode(ISD::VECTOR_SHUFFLE, dl, VT, V2, V1,
4130 DAG.getNode(ISD::BUILD_VECTOR, dl,
4131 MaskVT, &Mask1[0], 4));
4135 // Break it into (shuffle shuffle_hi, shuffle_lo).
4137 SmallVector<SDValue,8> LoMask(4, DAG.getUNDEF(MaskEVT));
4138 SmallVector<SDValue,8> HiMask(4, DAG.getUNDEF(MaskEVT));
4139 SmallVector<SDValue,8> *MaskPtr = &LoMask;
4140 unsigned MaskIdx = 0;
4143 for (unsigned i = 0; i != 4; ++i) {
4150 SDValue Elt = PermMask.getOperand(i);
4151 if (Elt.getOpcode() == ISD::UNDEF) {
4152 Locs[i] = std::make_pair(-1, -1);
4153 } else if (cast<ConstantSDNode>(Elt)->getZExtValue() < 4) {
4154 Locs[i] = std::make_pair(MaskIdx, LoIdx);
4155 (*MaskPtr)[LoIdx] = Elt;
4158 Locs[i] = std::make_pair(MaskIdx, HiIdx);
4159 (*MaskPtr)[HiIdx] = Elt;
4164 SDValue LoShuffle = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, VT, V1, V2,
4165 DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVT,
4166 &LoMask[0], LoMask.size()));
4167 SDValue HiShuffle = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, VT, V1, V2,
4168 DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVT,
4169 &HiMask[0], HiMask.size()));
4170 SmallVector<SDValue, 8> MaskOps;
4171 for (unsigned i = 0; i != 4; ++i) {
4172 if (Locs[i].first == -1) {
4173 MaskOps.push_back(DAG.getUNDEF(MaskEVT));
4175 unsigned Idx = Locs[i].first * 4 + Locs[i].second;
4176 MaskOps.push_back(DAG.getConstant(Idx, MaskEVT));
4179 return DAG.getNode(ISD::VECTOR_SHUFFLE, dl, VT, LoShuffle, HiShuffle,
4180 DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVT,
4181 &MaskOps[0], MaskOps.size()));
4185 X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) {
4186 SDValue V1 = Op.getOperand(0);
4187 SDValue V2 = Op.getOperand(1);
4188 SDValue PermMask = Op.getOperand(2);
4189 MVT VT = Op.getValueType();
4190 DebugLoc dl = Op.getDebugLoc();
4191 unsigned NumElems = PermMask.getNumOperands();
4192 bool isMMX = VT.getSizeInBits() == 64;
4193 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
4194 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
4195 bool V1IsSplat = false;
4196 bool V2IsSplat = false;
4198 // FIXME: Check for legal shuffle and return?
4200 if (isUndefShuffle(Op.getNode()))
4201 return DAG.getUNDEF(VT);
4203 if (isZeroShuffle(Op.getNode()))
4204 return getZeroVector(VT, Subtarget->hasSSE2(), DAG, dl);
4206 if (isIdentityMask(PermMask.getNode()))
4208 else if (isIdentityMask(PermMask.getNode(), true))
4211 // Canonicalize movddup shuffles.
4212 if (V2IsUndef && Subtarget->hasSSE2() &&
4213 VT.getSizeInBits() == 128 &&
4214 X86::isMOVDDUPMask(PermMask.getNode()))
4215 return CanonicalizeMovddup(Op, V1, PermMask, DAG, Subtarget->hasSSE3());
4217 if (isSplatMask(PermMask.getNode())) {
4218 if (isMMX || NumElems < 4) return Op;
4219 // Promote it to a v4{if}32 splat.
4220 return PromoteSplat(Op, DAG, Subtarget->hasSSE2());
4223 // If the shuffle can be profitably rewritten as a narrower shuffle, then
4225 if (VT == MVT::v8i16 || VT == MVT::v16i8) {
4226 SDValue NewOp= RewriteAsNarrowerShuffle(V1, V2, VT, PermMask, DAG,
4228 if (NewOp.getNode())
4229 return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
4230 LowerVECTOR_SHUFFLE(NewOp, DAG));
4231 } else if ((VT == MVT::v4i32 || (VT == MVT::v4f32 && Subtarget->hasSSE2()))) {
4232 // FIXME: Figure out a cleaner way to do this.
4233 // Try to make use of movq to zero out the top part.
4234 if (ISD::isBuildVectorAllZeros(V2.getNode())) {
4235 SDValue NewOp = RewriteAsNarrowerShuffle(V1, V2, VT, PermMask,
4237 if (NewOp.getNode()) {
4238 SDValue NewV1 = NewOp.getOperand(0);
4239 SDValue NewV2 = NewOp.getOperand(1);
4240 SDValue NewMask = NewOp.getOperand(2);
4241 if (isCommutedMOVL(NewMask.getNode(), true, false)) {
4242 NewOp = CommuteVectorShuffle(NewOp, NewV1, NewV2, NewMask, DAG);
4243 return getVZextMovL(VT, NewOp.getValueType(), NewV2, DAG, Subtarget,
4247 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) {
4248 SDValue NewOp= RewriteAsNarrowerShuffle(V1, V2, VT, PermMask,
4250 if (NewOp.getNode() && X86::isMOVLMask(NewOp.getOperand(2).getNode()))
4251 return getVZextMovL(VT, NewOp.getValueType(), NewOp.getOperand(1),
4252 DAG, Subtarget, dl);
4256 // Check if this can be converted into a logical shift.
4257 bool isLeft = false;
4260 bool isShift = isVectorShift(Op, PermMask, DAG, isLeft, ShVal, ShAmt);
4261 if (isShift && ShVal.hasOneUse()) {
4262 // If the shifted value has multiple uses, it may be cheaper to use
4263 // v_set0 + movlhps or movhlps, etc.
4264 MVT EVT = VT.getVectorElementType();
4265 ShAmt *= EVT.getSizeInBits();
4266 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
4269 if (X86::isMOVLMask(PermMask.getNode())) {
4272 if (ISD::isBuildVectorAllZeros(V1.getNode()))
4273 return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl);
4278 if (!isMMX && (X86::isMOVSHDUPMask(PermMask.getNode()) ||
4279 X86::isMOVSLDUPMask(PermMask.getNode()) ||
4280 X86::isMOVHLPSMask(PermMask.getNode()) ||
4281 X86::isMOVHPMask(PermMask.getNode()) ||
4282 X86::isMOVLPMask(PermMask.getNode())))
4285 if (ShouldXformToMOVHLPS(PermMask.getNode()) ||
4286 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), PermMask.getNode()))
4287 return CommuteVectorShuffle(Op, V1, V2, PermMask, DAG);
4290 // No better options. Use a vshl / vsrl.
4291 MVT EVT = VT.getVectorElementType();
4292 ShAmt *= EVT.getSizeInBits();
4293 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
4296 bool Commuted = false;
4297 // FIXME: This should also accept a bitcast of a splat? Be careful, not
4298 // 1,1,1,1 -> v8i16 though.
4299 V1IsSplat = isSplatVector(V1.getNode());
4300 V2IsSplat = isSplatVector(V2.getNode());
4302 // Canonicalize the splat or undef, if present, to be on the RHS.
4303 if ((V1IsSplat || V1IsUndef) && !(V2IsSplat || V2IsUndef)) {
4304 Op = CommuteVectorShuffle(Op, V1, V2, PermMask, DAG);
4305 std::swap(V1IsSplat, V2IsSplat);
4306 std::swap(V1IsUndef, V2IsUndef);
4310 // FIXME: Figure out a cleaner way to do this.
4311 if (isCommutedMOVL(PermMask.getNode(), V2IsSplat, V2IsUndef)) {
4312 if (V2IsUndef) return V1;
4313 Op = CommuteVectorShuffle(Op, V1, V2, PermMask, DAG);
4315 // V2 is a splat, so the mask may be malformed. That is, it may point
4316 // to any V2 element. The instruction selectior won't like this. Get
4317 // a corrected mask and commute to form a proper MOVS{S|D}.
4318 SDValue NewMask = getMOVLMask(NumElems, DAG, dl);
4319 if (NewMask.getNode() != PermMask.getNode())
4320 Op = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, VT, V1, V2, NewMask);
4325 if (X86::isUNPCKL_v_undef_Mask(PermMask.getNode()) ||
4326 X86::isUNPCKH_v_undef_Mask(PermMask.getNode()) ||
4327 X86::isUNPCKLMask(PermMask.getNode()) ||
4328 X86::isUNPCKHMask(PermMask.getNode()))
4332 // Normalize mask so all entries that point to V2 points to its first
4333 // element then try to match unpck{h|l} again. If match, return a
4334 // new vector_shuffle with the corrected mask.
4335 SDValue NewMask = NormalizeMask(PermMask, DAG);
4336 if (NewMask.getNode() != PermMask.getNode()) {
4337 if (X86::isUNPCKLMask(NewMask.getNode(), true)) {
4338 SDValue NewMask = getUnpacklMask(NumElems, DAG, dl);
4339 return DAG.getNode(ISD::VECTOR_SHUFFLE, dl, VT, V1, V2, NewMask);
4340 } else if (X86::isUNPCKHMask(NewMask.getNode(), true)) {
4341 SDValue NewMask = getUnpackhMask(NumElems, DAG, dl);
4342 return DAG.getNode(ISD::VECTOR_SHUFFLE, dl, VT, V1, V2, NewMask);
4347 // Normalize the node to match x86 shuffle ops if needed
4348 if (V2.getOpcode() != ISD::UNDEF && isCommutedSHUFP(PermMask.getNode()))
4349 Op = CommuteVectorShuffle(Op, V1, V2, PermMask, DAG);
4352 // Commute is back and try unpck* again.
4353 Op = CommuteVectorShuffle(Op, V1, V2, PermMask, DAG);
4354 if (X86::isUNPCKL_v_undef_Mask(PermMask.getNode()) ||
4355 X86::isUNPCKH_v_undef_Mask(PermMask.getNode()) ||
4356 X86::isUNPCKLMask(PermMask.getNode()) ||
4357 X86::isUNPCKHMask(PermMask.getNode()))
4361 // FIXME: for mmx, bitcast v2i32 to v4i16 for shuffle.
4362 // Try PSHUF* first, then SHUFP*.
4363 // MMX doesn't have PSHUFD but it does have PSHUFW. While it's theoretically
4364 // possible to shuffle a v2i32 using PSHUFW, that's not yet implemented.
4365 if (isMMX && NumElems == 4 && X86::isPSHUFDMask(PermMask.getNode())) {
4366 if (V2.getOpcode() != ISD::UNDEF)
4367 return DAG.getNode(ISD::VECTOR_SHUFFLE, dl, VT, V1,
4368 DAG.getUNDEF(VT), PermMask);
4373 if (Subtarget->hasSSE2() &&
4374 (X86::isPSHUFDMask(PermMask.getNode()) ||
4375 X86::isPSHUFHWMask(PermMask.getNode()) ||
4376 X86::isPSHUFLWMask(PermMask.getNode()))) {
4378 if (VT == MVT::v4f32) {
4380 Op = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, RVT,
4381 DAG.getNode(ISD::BIT_CONVERT, dl, RVT, V1),
4382 DAG.getUNDEF(RVT), PermMask);
4383 } else if (V2.getOpcode() != ISD::UNDEF)
4384 Op = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, RVT, V1,
4385 DAG.getUNDEF(RVT), PermMask);
4387 Op = DAG.getNode(ISD::BIT_CONVERT, dl, VT, Op);
4391 // Binary or unary shufps.
4392 if (X86::isSHUFPMask(PermMask.getNode()) ||
4393 (V2.getOpcode() == ISD::UNDEF && X86::isPSHUFDMask(PermMask.getNode())))
4397 // Handle v8i16 specifically since SSE can do byte extraction and insertion.
4398 if (VT == MVT::v8i16) {
4399 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(V1, V2, PermMask, DAG, *this, dl);
4400 if (NewOp.getNode())
4404 if (VT == MVT::v16i8) {
4405 SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(V1, V2, PermMask, DAG, *this, dl);
4406 if (NewOp.getNode())
4410 // Handle all 4 wide cases with a number of shuffles except for MMX.
4411 if (NumElems == 4 && !isMMX)
4412 return LowerVECTOR_SHUFFLE_4wide(V1, V2, PermMask, VT, DAG, dl);
4418 X86TargetLowering::LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op,
4419 SelectionDAG &DAG) {
4420 MVT VT = Op.getValueType();
4421 DebugLoc dl = Op.getDebugLoc();
4422 if (VT.getSizeInBits() == 8) {
4423 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
4424 Op.getOperand(0), Op.getOperand(1));
4425 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
4426 DAG.getValueType(VT));
4427 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
4428 } else if (VT.getSizeInBits() == 16) {
4429 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
4430 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
4432 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
4433 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
4434 DAG.getNode(ISD::BIT_CONVERT, dl,
4438 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
4439 Op.getOperand(0), Op.getOperand(1));
4440 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
4441 DAG.getValueType(VT));
4442 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
4443 } else if (VT == MVT::f32) {
4444 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
4445 // the result back to FR32 register. It's only worth matching if the
4446 // result has a single use which is a store or a bitcast to i32. And in
4447 // the case of a store, it's not worth it if the index is a constant 0,
4448 // because a MOVSSmr can be used instead, which is smaller and faster.
4449 if (!Op.hasOneUse())
4451 SDNode *User = *Op.getNode()->use_begin();
4452 if ((User->getOpcode() != ISD::STORE ||
4453 (isa<ConstantSDNode>(Op.getOperand(1)) &&
4454 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
4455 (User->getOpcode() != ISD::BIT_CONVERT ||
4456 User->getValueType(0) != MVT::i32))
4458 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
4459 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v4i32,
4462 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, Extract);
4463 } else if (VT == MVT::i32) {
4464 // ExtractPS works with constant index.
4465 if (isa<ConstantSDNode>(Op.getOperand(1)))
4473 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) {
4474 if (!isa<ConstantSDNode>(Op.getOperand(1)))
4477 if (Subtarget->hasSSE41()) {
4478 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG);
4483 MVT VT = Op.getValueType();
4484 DebugLoc dl = Op.getDebugLoc();
4485 // TODO: handle v16i8.
4486 if (VT.getSizeInBits() == 16) {
4487 SDValue Vec = Op.getOperand(0);
4488 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
4490 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
4491 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
4492 DAG.getNode(ISD::BIT_CONVERT, dl,
4495 // Transform it so it match pextrw which produces a 32-bit result.
4496 MVT EVT = (MVT::SimpleValueType)(VT.getSimpleVT()+1);
4497 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EVT,
4498 Op.getOperand(0), Op.getOperand(1));
4499 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EVT, Extract,
4500 DAG.getValueType(VT));
4501 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
4502 } else if (VT.getSizeInBits() == 32) {
4503 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
4506 // SHUFPS the element to the lowest double word, then movss.
4507 MVT MaskVT = MVT::getIntVectorWithNumElements(4);
4508 SmallVector<SDValue, 8> IdxVec;
4510 push_back(DAG.getConstant(Idx, MaskVT.getVectorElementType()));
4512 push_back(DAG.getUNDEF(MaskVT.getVectorElementType()));
4514 push_back(DAG.getUNDEF(MaskVT.getVectorElementType()));
4516 push_back(DAG.getUNDEF(MaskVT.getVectorElementType()));
4517 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVT,
4518 &IdxVec[0], IdxVec.size());
4519 SDValue Vec = Op.getOperand(0);
4520 Vec = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, Vec.getValueType(),
4521 Vec, DAG.getUNDEF(Vec.getValueType()), Mask);
4522 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
4523 DAG.getIntPtrConstant(0));
4524 } else if (VT.getSizeInBits() == 64) {
4525 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
4526 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
4527 // to match extract_elt for f64.
4528 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
4532 // UNPCKHPD the element to the lowest double word, then movsd.
4533 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
4534 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
4535 MVT MaskVT = MVT::getIntVectorWithNumElements(2);
4536 SmallVector<SDValue, 8> IdxVec;
4537 IdxVec.push_back(DAG.getConstant(1, MaskVT.getVectorElementType()));
4539 push_back(DAG.getUNDEF(MaskVT.getVectorElementType()));
4540 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVT,
4541 &IdxVec[0], IdxVec.size());
4542 SDValue Vec = Op.getOperand(0);
4543 Vec = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, Vec.getValueType(),
4544 Vec, DAG.getUNDEF(Vec.getValueType()),
4546 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
4547 DAG.getIntPtrConstant(0));
4554 X86TargetLowering::LowerINSERT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG){
4555 MVT VT = Op.getValueType();
4556 MVT EVT = VT.getVectorElementType();
4557 DebugLoc dl = Op.getDebugLoc();
4559 SDValue N0 = Op.getOperand(0);
4560 SDValue N1 = Op.getOperand(1);
4561 SDValue N2 = Op.getOperand(2);
4563 if ((EVT.getSizeInBits() == 8 || EVT.getSizeInBits() == 16) &&
4564 isa<ConstantSDNode>(N2)) {
4565 unsigned Opc = (EVT.getSizeInBits() == 8) ? X86ISD::PINSRB
4567 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
4569 if (N1.getValueType() != MVT::i32)
4570 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
4571 if (N2.getValueType() != MVT::i32)
4572 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
4573 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
4574 } else if (EVT == MVT::f32 && isa<ConstantSDNode>(N2)) {
4575 // Bits [7:6] of the constant are the source select. This will always be
4576 // zero here. The DAG Combiner may combine an extract_elt index into these
4577 // bits. For example (insert (extract, 3), 2) could be matched by putting
4578 // the '3' into bits [7:6] of X86ISD::INSERTPS.
4579 // Bits [5:4] of the constant are the destination select. This is the
4580 // value of the incoming immediate.
4581 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
4582 // combine either bitwise AND or insert of float 0.0 to set these bits.
4583 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue() << 4);
4584 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
4585 } else if (EVT == MVT::i32) {
4586 // InsertPS works with constant index.
4587 if (isa<ConstantSDNode>(N2))
4594 X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) {
4595 MVT VT = Op.getValueType();
4596 MVT EVT = VT.getVectorElementType();
4598 if (Subtarget->hasSSE41())
4599 return LowerINSERT_VECTOR_ELT_SSE4(Op, DAG);
4604 DebugLoc dl = Op.getDebugLoc();
4605 SDValue N0 = Op.getOperand(0);
4606 SDValue N1 = Op.getOperand(1);
4607 SDValue N2 = Op.getOperand(2);
4609 if (EVT.getSizeInBits() == 16) {
4610 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
4611 // as its second argument.
4612 if (N1.getValueType() != MVT::i32)
4613 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
4614 if (N2.getValueType() != MVT::i32)
4615 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
4616 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);
4622 X86TargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) {
4623 DebugLoc dl = Op.getDebugLoc();
4624 if (Op.getValueType() == MVT::v2f32)
4625 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f32,
4626 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i32,
4627 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32,
4628 Op.getOperand(0))));
4630 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
4631 MVT VT = MVT::v2i32;
4632 switch (Op.getValueType().getSimpleVT()) {
4639 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(),
4640 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, AnyExt));
4643 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
4644 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
4645 // one of the above mentioned nodes. It has to be wrapped because otherwise
4646 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
4647 // be used to form addressing mode. These wrapped nodes will be selected
4650 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) {
4651 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
4652 // FIXME there isn't really any debug info here, should come from the parent
4653 DebugLoc dl = CP->getDebugLoc();
4654 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(),
4656 CP->getAlignment());
4657 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
4658 // With PIC, the address is actually $g + Offset.
4659 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
4660 !Subtarget->isPICStyleRIPRel()) {
4661 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
4662 DAG.getNode(X86ISD::GlobalBaseReg,
4663 DebugLoc::getUnknownLoc(),
4672 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, DebugLoc dl,
4674 SelectionDAG &DAG) const {
4675 bool IsPic = getTargetMachine().getRelocationModel() == Reloc::PIC_;
4676 bool ExtraLoadRequired =
4677 Subtarget->GVRequiresExtraLoad(GV, getTargetMachine(), false);
4679 // Create the TargetGlobalAddress node, folding in the constant
4680 // offset if it is legal.
4682 if (!IsPic && !ExtraLoadRequired && isInt32(Offset)) {
4683 Result = DAG.getTargetGlobalAddress(GV, getPointerTy(), Offset);
4686 Result = DAG.getTargetGlobalAddress(GV, getPointerTy(), 0);
4687 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
4689 // With PIC, the address is actually $g + Offset.
4690 if (IsPic && !Subtarget->isPICStyleRIPRel()) {
4691 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
4692 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
4696 // For Darwin & Mingw32, external and weak symbols are indirect, so we want to
4697 // load the value at address GV, not the value of GV itself. This means that
4698 // the GlobalAddress must be in the base or index register of the address, not
4699 // the GV offset field. Platform check is inside GVRequiresExtraLoad() call
4700 // The same applies for external symbols during PIC codegen
4701 if (ExtraLoadRequired)
4702 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result,
4703 PseudoSourceValue::getGOT(), 0);
4705 // If there was a non-zero offset that we didn't fold, create an explicit
4708 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result,
4709 DAG.getConstant(Offset, getPointerTy()));
4715 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) {
4716 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
4717 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
4718 return LowerGlobalAddress(GV, Op.getDebugLoc(), Offset, DAG);
4721 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
4723 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
4726 DebugLoc dl = GA->getDebugLoc(); // ? function entry point might be better
4727 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
4728 DAG.getNode(X86ISD::GlobalBaseReg,
4729 DebugLoc::getUnknownLoc(),
4731 InFlag = Chain.getValue(1);
4733 // emit leal symbol@TLSGD(,%ebx,1), %eax
4734 SDVTList NodeTys = DAG.getVTList(PtrVT, MVT::Other, MVT::Flag);
4735 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(),
4736 GA->getValueType(0),
4738 SDValue Ops[] = { Chain, TGA, InFlag };
4739 SDValue Result = DAG.getNode(X86ISD::TLSADDR, dl, NodeTys, Ops, 3);
4740 InFlag = Result.getValue(2);
4741 Chain = Result.getValue(1);
4743 // call ___tls_get_addr. This function receives its argument in
4744 // the register EAX.
4745 Chain = DAG.getCopyToReg(Chain, dl, X86::EAX, Result, InFlag);
4746 InFlag = Chain.getValue(1);
4748 NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
4749 SDValue Ops1[] = { Chain,
4750 DAG.getTargetExternalSymbol("___tls_get_addr",
4752 DAG.getRegister(X86::EAX, PtrVT),
4753 DAG.getRegister(X86::EBX, PtrVT),
4755 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, Ops1, 5);
4756 InFlag = Chain.getValue(1);
4758 return DAG.getCopyFromReg(Chain, dl, X86::EAX, PtrVT, InFlag);
4761 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
4763 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
4765 SDValue InFlag, Chain;
4766 DebugLoc dl = GA->getDebugLoc(); // ? function entry point might be better
4768 // emit leaq symbol@TLSGD(%rip), %rdi
4769 SDVTList NodeTys = DAG.getVTList(PtrVT, MVT::Other, MVT::Flag);
4770 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(),
4771 GA->getValueType(0),
4773 SDValue Ops[] = { DAG.getEntryNode(), TGA};
4774 SDValue Result = DAG.getNode(X86ISD::TLSADDR, dl, NodeTys, Ops, 2);
4775 Chain = Result.getValue(1);
4776 InFlag = Result.getValue(2);
4778 // call __tls_get_addr. This function receives its argument in
4779 // the register RDI.
4780 Chain = DAG.getCopyToReg(Chain, dl, X86::RDI, Result, InFlag);
4781 InFlag = Chain.getValue(1);
4783 NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
4784 SDValue Ops1[] = { Chain,
4785 DAG.getTargetExternalSymbol("__tls_get_addr",
4787 DAG.getRegister(X86::RDI, PtrVT),
4789 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, Ops1, 4);
4790 InFlag = Chain.getValue(1);
4792 return DAG.getCopyFromReg(Chain, dl, X86::RAX, PtrVT, InFlag);
4795 // Lower ISD::GlobalTLSAddress using the "initial exec" (for no-pic) or
4796 // "local exec" model.
4797 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
4798 const MVT PtrVT, TLSModel::Model model) {
4799 DebugLoc dl = GA->getDebugLoc();
4800 // Get the Thread Pointer
4801 SDValue ThreadPointer = DAG.getNode(X86ISD::THREAD_POINTER,
4802 DebugLoc::getUnknownLoc(), PtrVT);
4803 // emit "addl x@ntpoff,%eax" (local exec) or "addl x@indntpoff,%eax" (initial
4805 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(),
4806 GA->getValueType(0),
4808 SDValue Offset = DAG.getNode(X86ISD::Wrapper, dl, PtrVT, TGA);
4810 if (model == TLSModel::InitialExec)
4811 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
4812 PseudoSourceValue::getGOT(), 0);
4814 // The address of the thread local variable is the add of the thread
4815 // pointer with the offset of the variable.
4816 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
4820 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) {
4821 // TODO: implement the "local dynamic" model
4822 // TODO: implement the "initial exec"model for pic executables
4823 assert(Subtarget->isTargetELF() &&
4824 "TLS not implemented for non-ELF targets");
4825 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
4826 GlobalValue *GV = GA->getGlobal();
4827 TLSModel::Model model =
4828 getTLSModel (GV, getTargetMachine().getRelocationModel());
4829 if (Subtarget->is64Bit()) {
4831 case TLSModel::GeneralDynamic:
4832 case TLSModel::LocalDynamic: // not implemented
4833 case TLSModel::InitialExec: // not implemented
4834 case TLSModel::LocalExec: // not implemented
4835 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy());
4837 assert (0 && "Unknown TLS model");
4841 case TLSModel::GeneralDynamic:
4842 case TLSModel::LocalDynamic: // not implemented
4843 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy());
4845 case TLSModel::InitialExec:
4846 case TLSModel::LocalExec:
4847 return LowerToTLSExecModel(GA, DAG, getPointerTy(), model);
4849 assert (0 && "Unknown TLS model");
4855 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) {
4856 // FIXME there isn't really any debug info here
4857 DebugLoc dl = Op.getDebugLoc();
4858 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
4859 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy());
4860 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
4861 // With PIC, the address is actually $g + Offset.
4862 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
4863 !Subtarget->isPICStyleRIPRel()) {
4864 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
4865 DAG.getNode(X86ISD::GlobalBaseReg,
4866 DebugLoc::getUnknownLoc(),
4874 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) {
4875 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
4876 // FIXME there isn't really any debug into here
4877 DebugLoc dl = JT->getDebugLoc();
4878 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy());
4879 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
4880 // With PIC, the address is actually $g + Offset.
4881 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
4882 !Subtarget->isPICStyleRIPRel()) {
4883 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
4884 DAG.getNode(X86ISD::GlobalBaseReg,
4885 DebugLoc::getUnknownLoc(),
4893 /// LowerShift - Lower SRA_PARTS and friends, which return two i32 values and
4894 /// take a 2 x i32 value to shift plus a shift amount.
4895 SDValue X86TargetLowering::LowerShift(SDValue Op, SelectionDAG &DAG) {
4896 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
4897 MVT VT = Op.getValueType();
4898 unsigned VTBits = VT.getSizeInBits();
4899 DebugLoc dl = Op.getDebugLoc();
4900 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
4901 SDValue ShOpLo = Op.getOperand(0);
4902 SDValue ShOpHi = Op.getOperand(1);
4903 SDValue ShAmt = Op.getOperand(2);
4904 SDValue Tmp1 = isSRA ?
4905 DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
4906 DAG.getConstant(VTBits - 1, MVT::i8)) :
4907 DAG.getConstant(0, VT);
4910 if (Op.getOpcode() == ISD::SHL_PARTS) {
4911 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
4912 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
4914 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
4915 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, ShAmt);
4918 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
4919 DAG.getConstant(VTBits, MVT::i8));
4920 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, VT,
4921 AndNode, DAG.getConstant(0, MVT::i8));
4924 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8);
4925 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
4926 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
4928 if (Op.getOpcode() == ISD::SHL_PARTS) {
4929 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
4930 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
4932 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
4933 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
4936 SDValue Ops[2] = { Lo, Hi };
4937 return DAG.getMergeValues(Ops, 2, dl);
4940 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
4941 MVT SrcVT = Op.getOperand(0).getValueType();
4942 assert(SrcVT.getSimpleVT() <= MVT::i64 && SrcVT.getSimpleVT() >= MVT::i16 &&
4943 "Unknown SINT_TO_FP to lower!");
4945 // These are really Legal; caller falls through into that case.
4946 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
4948 if (SrcVT == MVT::i64 && Op.getValueType() != MVT::f80 &&
4949 Subtarget->is64Bit())
4952 DebugLoc dl = Op.getDebugLoc();
4953 unsigned Size = SrcVT.getSizeInBits()/8;
4954 MachineFunction &MF = DAG.getMachineFunction();
4955 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size);
4956 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
4957 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
4959 PseudoSourceValue::getFixedStack(SSFI), 0);
4963 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
4965 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Flag);
4967 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
4968 SmallVector<SDValue, 8> Ops;
4969 Ops.push_back(Chain);
4970 Ops.push_back(StackSlot);
4971 Ops.push_back(DAG.getValueType(SrcVT));
4972 SDValue Result = DAG.getNode(useSSE ? X86ISD::FILD_FLAG : X86ISD::FILD, dl,
4973 Tys, &Ops[0], Ops.size());
4976 Chain = Result.getValue(1);
4977 SDValue InFlag = Result.getValue(2);
4979 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
4980 // shouldn't be necessary except that RFP cannot be live across
4981 // multiple blocks. When stackifier is fixed, they can be uncoupled.
4982 MachineFunction &MF = DAG.getMachineFunction();
4983 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8);
4984 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
4985 Tys = DAG.getVTList(MVT::Other);
4986 SmallVector<SDValue, 8> Ops;
4987 Ops.push_back(Chain);
4988 Ops.push_back(Result);
4989 Ops.push_back(StackSlot);
4990 Ops.push_back(DAG.getValueType(Op.getValueType()));
4991 Ops.push_back(InFlag);
4992 Chain = DAG.getNode(X86ISD::FST, dl, Tys, &Ops[0], Ops.size());
4993 Result = DAG.getLoad(Op.getValueType(), dl, Chain, StackSlot,
4994 PseudoSourceValue::getFixedStack(SSFI), 0);
5000 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
5001 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op, SelectionDAG &DAG) {
5002 // This algorithm is not obvious. Here it is in C code, more or less:
5004 double uint64_to_double( uint32_t hi, uint32_t lo ) {
5005 static const __m128i exp = { 0x4330000045300000ULL, 0 };
5006 static const __m128d bias = { 0x1.0p84, 0x1.0p52 };
5008 // Copy ints to xmm registers.
5009 __m128i xh = _mm_cvtsi32_si128( hi );
5010 __m128i xl = _mm_cvtsi32_si128( lo );
5012 // Combine into low half of a single xmm register.
5013 __m128i x = _mm_unpacklo_epi32( xh, xl );
5017 // Merge in appropriate exponents to give the integer bits the right
5019 x = _mm_unpacklo_epi32( x, exp );
5021 // Subtract away the biases to deal with the IEEE-754 double precision
5023 d = _mm_sub_pd( (__m128d) x, bias );
5025 // All conversions up to here are exact. The correctly rounded result is
5026 // calculated using the current rounding mode using the following
5028 d = _mm_add_sd( d, _mm_unpackhi_pd( d, d ) );
5029 _mm_store_sd( &sd, d ); // Because we are returning doubles in XMM, this
5030 // store doesn't really need to be here (except
5031 // maybe to zero the other double)
5036 DebugLoc dl = Op.getDebugLoc();
5038 // Build some magic constants.
5039 std::vector<Constant*> CV0;
5040 CV0.push_back(ConstantInt::get(APInt(32, 0x45300000)));
5041 CV0.push_back(ConstantInt::get(APInt(32, 0x43300000)));
5042 CV0.push_back(ConstantInt::get(APInt(32, 0)));
5043 CV0.push_back(ConstantInt::get(APInt(32, 0)));
5044 Constant *C0 = ConstantVector::get(CV0);
5045 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 4);
5047 std::vector<Constant*> CV1;
5048 CV1.push_back(ConstantFP::get(APFloat(APInt(64, 0x4530000000000000ULL))));
5049 CV1.push_back(ConstantFP::get(APFloat(APInt(64, 0x4330000000000000ULL))));
5050 Constant *C1 = ConstantVector::get(CV1);
5051 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 4);
5053 SmallVector<SDValue, 4> MaskVec;
5054 MaskVec.push_back(DAG.getConstant(0, MVT::i32));
5055 MaskVec.push_back(DAG.getConstant(4, MVT::i32));
5056 MaskVec.push_back(DAG.getConstant(1, MVT::i32));
5057 MaskVec.push_back(DAG.getConstant(5, MVT::i32));
5058 SDValue UnpcklMask = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
5059 &MaskVec[0], MaskVec.size());
5060 SmallVector<SDValue, 4> MaskVec2;
5061 MaskVec2.push_back(DAG.getConstant(1, MVT::i32));
5062 MaskVec2.push_back(DAG.getConstant(0, MVT::i32));
5063 SDValue ShufMask = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i32,
5064 &MaskVec2[0], MaskVec2.size());
5066 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
5067 DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
5069 DAG.getIntPtrConstant(1)));
5070 SDValue XR2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
5071 DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
5073 DAG.getIntPtrConstant(0)));
5074 SDValue Unpck1 = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, MVT::v4i32,
5075 XR1, XR2, UnpcklMask);
5076 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
5077 PseudoSourceValue::getConstantPool(), 0,
5079 SDValue Unpck2 = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, MVT::v4i32,
5080 Unpck1, CLod0, UnpcklMask);
5081 SDValue XR2F = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f64, Unpck2);
5082 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
5083 PseudoSourceValue::getConstantPool(), 0,
5085 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
5087 // Add the halves; easiest way is to swap them into another reg first.
5088 SDValue Shuf = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, MVT::v2f64,
5089 Sub, Sub, ShufMask);
5090 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::v2f64, Shuf, Sub);
5091 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Add,
5092 DAG.getIntPtrConstant(0));
5095 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
5096 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op, SelectionDAG &DAG) {
5097 DebugLoc dl = Op.getDebugLoc();
5098 // FP constant to bias correct the final result.
5099 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
5102 // Load the 32-bit value into an XMM register.
5103 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
5104 DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
5106 DAG.getIntPtrConstant(0)));
5108 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
5109 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f64, Load),
5110 DAG.getIntPtrConstant(0));
5112 // Or the load with the bias.
5113 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64,
5114 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64,
5115 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
5117 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64,
5118 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
5119 MVT::v2f64, Bias)));
5120 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
5121 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f64, Or),
5122 DAG.getIntPtrConstant(0));
5124 // Subtract the bias.
5125 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
5127 // Handle final rounding.
5128 MVT DestVT = Op.getValueType();
5130 if (DestVT.bitsLT(MVT::f64)) {
5131 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
5132 DAG.getIntPtrConstant(0));
5133 } else if (DestVT.bitsGT(MVT::f64)) {
5134 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
5137 // Handle final rounding.
5141 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
5142 SDValue N0 = Op.getOperand(0);
5143 DebugLoc dl = Op.getDebugLoc();
5145 // Now not UINT_TO_FP is legal (it's marked custom), dag combiner won't
5146 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
5147 // the optimization here.
5148 if (DAG.SignBitIsZero(N0))
5149 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
5151 MVT SrcVT = N0.getValueType();
5152 if (SrcVT == MVT::i64) {
5153 // We only handle SSE2 f64 target here; caller can handle the rest.
5154 if (Op.getValueType() != MVT::f64 || !X86ScalarSSEf64)
5157 return LowerUINT_TO_FP_i64(Op, DAG);
5158 } else if (SrcVT == MVT::i32) {
5159 return LowerUINT_TO_FP_i32(Op, DAG);
5162 assert(0 && "Unknown UINT_TO_FP to lower!");
5166 std::pair<SDValue,SDValue> X86TargetLowering::
5167 FP_TO_SINTHelper(SDValue Op, SelectionDAG &DAG) {
5168 DebugLoc dl = Op.getDebugLoc();
5169 assert(Op.getValueType().getSimpleVT() <= MVT::i64 &&
5170 Op.getValueType().getSimpleVT() >= MVT::i16 &&
5171 "Unknown FP_TO_SINT to lower!");
5173 // These are really Legal.
5174 if (Op.getValueType() == MVT::i32 &&
5175 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
5176 return std::make_pair(SDValue(), SDValue());
5177 if (Subtarget->is64Bit() &&
5178 Op.getValueType() == MVT::i64 &&
5179 Op.getOperand(0).getValueType() != MVT::f80)
5180 return std::make_pair(SDValue(), SDValue());
5182 // We lower FP->sint64 into FISTP64, followed by a load, all to a temporary
5184 MachineFunction &MF = DAG.getMachineFunction();
5185 unsigned MemSize = Op.getValueType().getSizeInBits()/8;
5186 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize);
5187 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
5189 switch (Op.getValueType().getSimpleVT()) {
5190 default: assert(0 && "Invalid FP_TO_SINT to lower!");
5191 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
5192 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
5193 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
5196 SDValue Chain = DAG.getEntryNode();
5197 SDValue Value = Op.getOperand(0);
5198 if (isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType())) {
5199 assert(Op.getValueType() == MVT::i64 && "Invalid FP_TO_SINT to lower!");
5200 Chain = DAG.getStore(Chain, dl, Value, StackSlot,
5201 PseudoSourceValue::getFixedStack(SSFI), 0);
5202 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
5204 Chain, StackSlot, DAG.getValueType(Op.getOperand(0).getValueType())
5206 Value = DAG.getNode(X86ISD::FLD, dl, Tys, Ops, 3);
5207 Chain = Value.getValue(1);
5208 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize);
5209 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
5212 // Build the FP_TO_INT*_IN_MEM
5213 SDValue Ops[] = { Chain, Value, StackSlot };
5214 SDValue FIST = DAG.getNode(Opc, dl, MVT::Other, Ops, 3);
5216 return std::make_pair(FIST, StackSlot);
5219 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) {
5220 std::pair<SDValue,SDValue> Vals = FP_TO_SINTHelper(Op, DAG);
5221 SDValue FIST = Vals.first, StackSlot = Vals.second;
5222 if (FIST.getNode() == 0) return SDValue();
5225 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(),
5226 FIST, StackSlot, NULL, 0);
5229 SDValue X86TargetLowering::LowerFABS(SDValue Op, SelectionDAG &DAG) {
5230 DebugLoc dl = Op.getDebugLoc();
5231 MVT VT = Op.getValueType();
5234 EltVT = VT.getVectorElementType();
5235 std::vector<Constant*> CV;
5236 if (EltVT == MVT::f64) {
5237 Constant *C = ConstantFP::get(APFloat(APInt(64, ~(1ULL << 63))));
5241 Constant *C = ConstantFP::get(APFloat(APInt(32, ~(1U << 31))));
5247 Constant *C = ConstantVector::get(CV);
5248 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 4);
5249 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
5250 PseudoSourceValue::getConstantPool(), 0,
5252 return DAG.getNode(X86ISD::FAND, dl, VT, Op.getOperand(0), Mask);
5255 SDValue X86TargetLowering::LowerFNEG(SDValue Op, SelectionDAG &DAG) {
5256 DebugLoc dl = Op.getDebugLoc();
5257 MVT VT = Op.getValueType();
5259 unsigned EltNum = 1;
5260 if (VT.isVector()) {
5261 EltVT = VT.getVectorElementType();
5262 EltNum = VT.getVectorNumElements();
5264 std::vector<Constant*> CV;
5265 if (EltVT == MVT::f64) {
5266 Constant *C = ConstantFP::get(APFloat(APInt(64, 1ULL << 63)));
5270 Constant *C = ConstantFP::get(APFloat(APInt(32, 1U << 31)));
5276 Constant *C = ConstantVector::get(CV);
5277 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 4);
5278 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
5279 PseudoSourceValue::getConstantPool(), 0,
5281 if (VT.isVector()) {
5282 return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
5283 DAG.getNode(ISD::XOR, dl, MVT::v2i64,
5284 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64,
5286 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64, Mask)));
5288 return DAG.getNode(X86ISD::FXOR, dl, VT, Op.getOperand(0), Mask);
5292 SDValue X86TargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) {
5293 SDValue Op0 = Op.getOperand(0);
5294 SDValue Op1 = Op.getOperand(1);
5295 DebugLoc dl = Op.getDebugLoc();
5296 MVT VT = Op.getValueType();
5297 MVT SrcVT = Op1.getValueType();
5299 // If second operand is smaller, extend it first.
5300 if (SrcVT.bitsLT(VT)) {
5301 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
5304 // And if it is bigger, shrink it first.
5305 if (SrcVT.bitsGT(VT)) {
5306 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1));
5310 // At this point the operands and the result should have the same
5311 // type, and that won't be f80 since that is not custom lowered.
5313 // First get the sign bit of second operand.
5314 std::vector<Constant*> CV;
5315 if (SrcVT == MVT::f64) {
5316 CV.push_back(ConstantFP::get(APFloat(APInt(64, 1ULL << 63))));
5317 CV.push_back(ConstantFP::get(APFloat(APInt(64, 0))));
5319 CV.push_back(ConstantFP::get(APFloat(APInt(32, 1U << 31))));
5320 CV.push_back(ConstantFP::get(APFloat(APInt(32, 0))));
5321 CV.push_back(ConstantFP::get(APFloat(APInt(32, 0))));
5322 CV.push_back(ConstantFP::get(APFloat(APInt(32, 0))));
5324 Constant *C = ConstantVector::get(CV);
5325 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 4);
5326 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx,
5327 PseudoSourceValue::getConstantPool(), 0,
5329 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1);
5331 // Shift sign bit right or left if the two operands have different types.
5332 if (SrcVT.bitsGT(VT)) {
5333 // Op0 is MVT::f32, Op1 is MVT::f64.
5334 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, SignBit);
5335 SignBit = DAG.getNode(X86ISD::FSRL, dl, MVT::v2f64, SignBit,
5336 DAG.getConstant(32, MVT::i32));
5337 SignBit = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v4f32, SignBit);
5338 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, SignBit,
5339 DAG.getIntPtrConstant(0));
5342 // Clear first operand sign bit.
5344 if (VT == MVT::f64) {
5345 CV.push_back(ConstantFP::get(APFloat(APInt(64, ~(1ULL << 63)))));
5346 CV.push_back(ConstantFP::get(APFloat(APInt(64, 0))));
5348 CV.push_back(ConstantFP::get(APFloat(APInt(32, ~(1U << 31)))));
5349 CV.push_back(ConstantFP::get(APFloat(APInt(32, 0))));
5350 CV.push_back(ConstantFP::get(APFloat(APInt(32, 0))));
5351 CV.push_back(ConstantFP::get(APFloat(APInt(32, 0))));
5353 C = ConstantVector::get(CV);
5354 CPIdx = DAG.getConstantPool(C, getPointerTy(), 4);
5355 SDValue Mask2 = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
5356 PseudoSourceValue::getConstantPool(), 0,
5358 SDValue Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Mask2);
5360 // Or the value with the sign bit.
5361 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit);
5364 /// Emit nodes that will be selected as "test Op0,Op0", or something
5366 SDValue X86TargetLowering::EmitTest(SDValue Op, SelectionDAG &DAG) {
5367 DebugLoc dl = Op.getDebugLoc();
5369 // See if we can use the EFLAGS value from the operand instead of
5370 // doing a separate TEST.
5371 if (Op.getResNo() == 0) {
5372 unsigned Opcode = 0;
5373 switch (Op.getNode()->getOpcode()) {
5375 // Due to an isel shortcoming, be conservative if this add is likely to
5376 // be selected as part of a load-modify-store instruction. When the root
5377 // node in a match is a store, isel doesn't know how to remap non-chain
5378 // non-flag uses of other nodes in the match, such as the ADD in this
5379 // case. This leads to the ADD being left around and reselected, with
5380 // the result being two adds in the output.
5381 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
5382 UE = Op.getNode()->use_end(); UI != UE; ++UI)
5383 if (UI->getOpcode() == ISD::STORE)
5385 if (ConstantSDNode *C =
5386 dyn_cast<ConstantSDNode>(Op.getNode()->getOperand(1))) {
5387 // An add of one will be selected as an INC.
5388 if (C->getAPIntValue() == 1) {
5389 Opcode = X86ISD::INC;
5392 // An add of negative one (subtract of one) will be selected as a DEC.
5393 if (C->getAPIntValue().isAllOnesValue()) {
5394 Opcode = X86ISD::DEC;
5398 // Otherwise use a regular EFLAGS-setting add.
5399 Opcode = X86ISD::ADD;
5402 // Due to the ISEL shortcoming noted above, be conservative if this sub is
5403 // likely to be selected as part of a load-modify-store instruction.
5404 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
5405 UE = Op.getNode()->use_end(); UI != UE; ++UI)
5406 if (UI->getOpcode() == ISD::STORE)
5408 // Otherwise use a regular EFLAGS-setting sub.
5409 Opcode = X86ISD::SUB;
5415 return SDValue(Op.getNode(), 1);
5421 const MVT *VTs = DAG.getNodeValueTypes(Op.getValueType(), MVT::i32);
5422 SmallVector<SDValue, 4> Ops;
5423 for (unsigned i = 0, e = Op.getNumOperands(); i != e; ++i)
5424 Ops.push_back(Op.getOperand(i));
5425 SDValue New = DAG.getNode(Opcode, dl, VTs, 2, &Ops[0], Ops.size());
5426 DAG.ReplaceAllUsesWith(Op, New);
5427 return SDValue(New.getNode(), 1);
5431 // Otherwise just emit a CMP with 0, which is the TEST pattern.
5432 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
5433 DAG.getConstant(0, Op.getValueType()));
5436 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
5438 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, SelectionDAG &DAG) {
5439 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1))
5440 if (C->getAPIntValue() == 0)
5441 return EmitTest(Op0, DAG);
5443 DebugLoc dl = Op0.getDebugLoc();
5444 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
5447 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) {
5448 assert(Op.getValueType() == MVT::i8 && "SetCC type must be 8-bit integer");
5449 SDValue Op0 = Op.getOperand(0);
5450 SDValue Op1 = Op.getOperand(1);
5451 DebugLoc dl = Op.getDebugLoc();
5452 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
5454 // Lower (X & (1 << N)) == 0 to BT(X, N).
5455 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
5456 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
5457 if (Op0.getOpcode() == ISD::AND &&
5459 Op1.getOpcode() == ISD::Constant &&
5460 cast<ConstantSDNode>(Op1)->getZExtValue() == 0 &&
5461 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
5463 if (Op0.getOperand(1).getOpcode() == ISD::SHL) {
5464 if (ConstantSDNode *Op010C =
5465 dyn_cast<ConstantSDNode>(Op0.getOperand(1).getOperand(0)))
5466 if (Op010C->getZExtValue() == 1) {
5467 LHS = Op0.getOperand(0);
5468 RHS = Op0.getOperand(1).getOperand(1);
5470 } else if (Op0.getOperand(0).getOpcode() == ISD::SHL) {
5471 if (ConstantSDNode *Op000C =
5472 dyn_cast<ConstantSDNode>(Op0.getOperand(0).getOperand(0)))
5473 if (Op000C->getZExtValue() == 1) {
5474 LHS = Op0.getOperand(1);
5475 RHS = Op0.getOperand(0).getOperand(1);
5477 } else if (Op0.getOperand(1).getOpcode() == ISD::Constant) {
5478 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op0.getOperand(1));
5479 SDValue AndLHS = Op0.getOperand(0);
5480 if (AndRHS->getZExtValue() == 1 && AndLHS.getOpcode() == ISD::SRL) {
5481 LHS = AndLHS.getOperand(0);
5482 RHS = AndLHS.getOperand(1);
5486 if (LHS.getNode()) {
5487 // If LHS is i8, promote it to i16 with any_extend. There is no i8 BT
5488 // instruction. Since the shift amount is in-range-or-undefined, we know
5489 // that doing a bittest on the i16 value is ok. We extend to i32 because
5490 // the encoding for the i16 version is larger than the i32 version.
5491 if (LHS.getValueType() == MVT::i8)
5492 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
5494 // If the operand types disagree, extend the shift amount to match. Since
5495 // BT ignores high bits (like shifts) we can use anyextend.
5496 if (LHS.getValueType() != RHS.getValueType())
5497 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
5499 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
5500 unsigned Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
5501 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
5502 DAG.getConstant(Cond, MVT::i8), BT);
5506 bool isFP = Op.getOperand(1).getValueType().isFloatingPoint();
5507 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG);
5509 SDValue Cond = EmitCmp(Op0, Op1, DAG);
5510 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
5511 DAG.getConstant(X86CC, MVT::i8), Cond);
5514 SDValue X86TargetLowering::LowerVSETCC(SDValue Op, SelectionDAG &DAG) {
5516 SDValue Op0 = Op.getOperand(0);
5517 SDValue Op1 = Op.getOperand(1);
5518 SDValue CC = Op.getOperand(2);
5519 MVT VT = Op.getValueType();
5520 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
5521 bool isFP = Op.getOperand(1).getValueType().isFloatingPoint();
5522 DebugLoc dl = Op.getDebugLoc();
5526 MVT VT0 = Op0.getValueType();
5527 assert(VT0 == MVT::v4f32 || VT0 == MVT::v2f64);
5528 unsigned Opc = VT0 == MVT::v4f32 ? X86ISD::CMPPS : X86ISD::CMPPD;
5531 switch (SetCCOpcode) {
5534 case ISD::SETEQ: SSECC = 0; break;
5536 case ISD::SETGT: Swap = true; // Fallthrough
5538 case ISD::SETOLT: SSECC = 1; break;
5540 case ISD::SETGE: Swap = true; // Fallthrough
5542 case ISD::SETOLE: SSECC = 2; break;
5543 case ISD::SETUO: SSECC = 3; break;
5545 case ISD::SETNE: SSECC = 4; break;
5546 case ISD::SETULE: Swap = true;
5547 case ISD::SETUGE: SSECC = 5; break;
5548 case ISD::SETULT: Swap = true;
5549 case ISD::SETUGT: SSECC = 6; break;
5550 case ISD::SETO: SSECC = 7; break;
5553 std::swap(Op0, Op1);
5555 // In the two special cases we can't handle, emit two comparisons.
5557 if (SetCCOpcode == ISD::SETUEQ) {
5559 UNORD = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(3, MVT::i8));
5560 EQ = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(0, MVT::i8));
5561 return DAG.getNode(ISD::OR, dl, VT, UNORD, EQ);
5563 else if (SetCCOpcode == ISD::SETONE) {
5565 ORD = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(7, MVT::i8));
5566 NEQ = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(4, MVT::i8));
5567 return DAG.getNode(ISD::AND, dl, VT, ORD, NEQ);
5569 assert(0 && "Illegal FP comparison");
5571 // Handle all other FP comparisons here.
5572 return DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(SSECC, MVT::i8));
5575 // We are handling one of the integer comparisons here. Since SSE only has
5576 // GT and EQ comparisons for integer, swapping operands and multiple
5577 // operations may be required for some comparisons.
5578 unsigned Opc = 0, EQOpc = 0, GTOpc = 0;
5579 bool Swap = false, Invert = false, FlipSigns = false;
5581 switch (VT.getSimpleVT()) {
5583 case MVT::v16i8: EQOpc = X86ISD::PCMPEQB; GTOpc = X86ISD::PCMPGTB; break;
5584 case MVT::v8i16: EQOpc = X86ISD::PCMPEQW; GTOpc = X86ISD::PCMPGTW; break;
5585 case MVT::v4i32: EQOpc = X86ISD::PCMPEQD; GTOpc = X86ISD::PCMPGTD; break;
5586 case MVT::v2i64: EQOpc = X86ISD::PCMPEQQ; GTOpc = X86ISD::PCMPGTQ; break;
5589 switch (SetCCOpcode) {
5591 case ISD::SETNE: Invert = true;
5592 case ISD::SETEQ: Opc = EQOpc; break;
5593 case ISD::SETLT: Swap = true;
5594 case ISD::SETGT: Opc = GTOpc; break;
5595 case ISD::SETGE: Swap = true;
5596 case ISD::SETLE: Opc = GTOpc; Invert = true; break;
5597 case ISD::SETULT: Swap = true;
5598 case ISD::SETUGT: Opc = GTOpc; FlipSigns = true; break;
5599 case ISD::SETUGE: Swap = true;
5600 case ISD::SETULE: Opc = GTOpc; FlipSigns = true; Invert = true; break;
5603 std::swap(Op0, Op1);
5605 // Since SSE has no unsigned integer comparisons, we need to flip the sign
5606 // bits of the inputs before performing those operations.
5608 MVT EltVT = VT.getVectorElementType();
5609 SDValue SignBit = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()),
5611 std::vector<SDValue> SignBits(VT.getVectorNumElements(), SignBit);
5612 SDValue SignVec = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &SignBits[0],
5614 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SignVec);
5615 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SignVec);
5618 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
5620 // If the logical-not of the result is required, perform that now.
5622 Result = DAG.getNOT(dl, Result, VT);
5627 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
5628 static bool isX86LogicalCmp(SDValue Op) {
5629 unsigned Opc = Op.getNode()->getOpcode();
5630 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI)
5632 if (Op.getResNo() == 1 &&
5633 (Opc == X86ISD::ADD ||
5634 Opc == X86ISD::SUB ||
5635 Opc == X86ISD::SMUL ||
5636 Opc == X86ISD::UMUL ||
5637 Opc == X86ISD::INC ||
5638 Opc == X86ISD::DEC))
5644 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) {
5645 bool addTest = true;
5646 SDValue Cond = Op.getOperand(0);
5647 DebugLoc dl = Op.getDebugLoc();
5650 if (Cond.getOpcode() == ISD::SETCC)
5651 Cond = LowerSETCC(Cond, DAG);
5653 // If condition flag is set by a X86ISD::CMP, then use it as the condition
5654 // setting operand in place of the X86ISD::SETCC.
5655 if (Cond.getOpcode() == X86ISD::SETCC) {
5656 CC = Cond.getOperand(0);
5658 SDValue Cmp = Cond.getOperand(1);
5659 unsigned Opc = Cmp.getOpcode();
5660 MVT VT = Op.getValueType();
5662 bool IllegalFPCMov = false;
5663 if (VT.isFloatingPoint() && !VT.isVector() &&
5664 !isScalarFPTypeInSSEReg(VT)) // FPStack?
5665 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
5667 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) || Opc == X86ISD::BT) { // FIXME
5674 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
5675 Cond = EmitTest(Cond, DAG);
5678 const MVT *VTs = DAG.getNodeValueTypes(Op.getValueType(),
5680 SmallVector<SDValue, 4> Ops;
5681 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
5682 // condition is true.
5683 Ops.push_back(Op.getOperand(2));
5684 Ops.push_back(Op.getOperand(1));
5686 Ops.push_back(Cond);
5687 return DAG.getNode(X86ISD::CMOV, dl, VTs, 2, &Ops[0], Ops.size());
5690 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
5691 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
5692 // from the AND / OR.
5693 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
5694 Opc = Op.getOpcode();
5695 if (Opc != ISD::OR && Opc != ISD::AND)
5697 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
5698 Op.getOperand(0).hasOneUse() &&
5699 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
5700 Op.getOperand(1).hasOneUse());
5703 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
5704 // 1 and that the SETCC node has a single use.
5705 static bool isXor1OfSetCC(SDValue Op) {
5706 if (Op.getOpcode() != ISD::XOR)
5708 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
5709 if (N1C && N1C->getAPIntValue() == 1) {
5710 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
5711 Op.getOperand(0).hasOneUse();
5716 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) {
5717 bool addTest = true;
5718 SDValue Chain = Op.getOperand(0);
5719 SDValue Cond = Op.getOperand(1);
5720 SDValue Dest = Op.getOperand(2);
5721 DebugLoc dl = Op.getDebugLoc();
5724 if (Cond.getOpcode() == ISD::SETCC)
5725 Cond = LowerSETCC(Cond, DAG);
5727 // FIXME: LowerXALUO doesn't handle these!!
5728 else if (Cond.getOpcode() == X86ISD::ADD ||
5729 Cond.getOpcode() == X86ISD::SUB ||
5730 Cond.getOpcode() == X86ISD::SMUL ||
5731 Cond.getOpcode() == X86ISD::UMUL)
5732 Cond = LowerXALUO(Cond, DAG);
5735 // If condition flag is set by a X86ISD::CMP, then use it as the condition
5736 // setting operand in place of the X86ISD::SETCC.
5737 if (Cond.getOpcode() == X86ISD::SETCC) {
5738 CC = Cond.getOperand(0);
5740 SDValue Cmp = Cond.getOperand(1);
5741 unsigned Opc = Cmp.getOpcode();
5742 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
5743 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
5747 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
5751 // These can only come from an arithmetic instruction with overflow,
5752 // e.g. SADDO, UADDO.
5753 Cond = Cond.getNode()->getOperand(1);
5760 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
5761 SDValue Cmp = Cond.getOperand(0).getOperand(1);
5762 if (CondOpc == ISD::OR) {
5763 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
5764 // two branches instead of an explicit OR instruction with a
5766 if (Cmp == Cond.getOperand(1).getOperand(1) &&
5767 isX86LogicalCmp(Cmp)) {
5768 CC = Cond.getOperand(0).getOperand(0);
5769 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
5770 Chain, Dest, CC, Cmp);
5771 CC = Cond.getOperand(1).getOperand(0);
5775 } else { // ISD::AND
5776 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
5777 // two branches instead of an explicit AND instruction with a
5778 // separate test. However, we only do this if this block doesn't
5779 // have a fall-through edge, because this requires an explicit
5780 // jmp when the condition is false.
5781 if (Cmp == Cond.getOperand(1).getOperand(1) &&
5782 isX86LogicalCmp(Cmp) &&
5783 Op.getNode()->hasOneUse()) {
5784 X86::CondCode CCode =
5785 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
5786 CCode = X86::GetOppositeBranchCondition(CCode);
5787 CC = DAG.getConstant(CCode, MVT::i8);
5788 SDValue User = SDValue(*Op.getNode()->use_begin(), 0);
5789 // Look for an unconditional branch following this conditional branch.
5790 // We need this because we need to reverse the successors in order
5791 // to implement FCMP_OEQ.
5792 if (User.getOpcode() == ISD::BR) {
5793 SDValue FalseBB = User.getOperand(1);
5795 DAG.UpdateNodeOperands(User, User.getOperand(0), Dest);
5796 assert(NewBR == User);
5799 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
5800 Chain, Dest, CC, Cmp);
5801 X86::CondCode CCode =
5802 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
5803 CCode = X86::GetOppositeBranchCondition(CCode);
5804 CC = DAG.getConstant(CCode, MVT::i8);
5810 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
5811 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
5812 // It should be transformed during dag combiner except when the condition
5813 // is set by a arithmetics with overflow node.
5814 X86::CondCode CCode =
5815 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
5816 CCode = X86::GetOppositeBranchCondition(CCode);
5817 CC = DAG.getConstant(CCode, MVT::i8);
5818 Cond = Cond.getOperand(0).getOperand(1);
5824 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
5825 Cond = EmitTest(Cond, DAG);
5827 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
5828 Chain, Dest, CC, Cond);
5832 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
5833 // Calls to _alloca is needed to probe the stack when allocating more than 4k
5834 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
5835 // that the guard pages used by the OS virtual memory manager are allocated in
5836 // correct sequence.
5838 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
5839 SelectionDAG &DAG) {
5840 assert(Subtarget->isTargetCygMing() &&
5841 "This should be used only on Cygwin/Mingw targets");
5842 DebugLoc dl = Op.getDebugLoc();
5845 SDValue Chain = Op.getOperand(0);
5846 SDValue Size = Op.getOperand(1);
5847 // FIXME: Ensure alignment here
5851 MVT IntPtr = getPointerTy();
5852 MVT SPTy = Subtarget->is64Bit() ? MVT::i64 : MVT::i32;
5854 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true));
5856 Chain = DAG.getCopyToReg(Chain, dl, X86::EAX, Size, Flag);
5857 Flag = Chain.getValue(1);
5859 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
5860 SDValue Ops[] = { Chain,
5861 DAG.getTargetExternalSymbol("_alloca", IntPtr),
5862 DAG.getRegister(X86::EAX, IntPtr),
5863 DAG.getRegister(X86StackPtr, SPTy),
5865 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, Ops, 5);
5866 Flag = Chain.getValue(1);
5868 Chain = DAG.getCALLSEQ_END(Chain,
5869 DAG.getIntPtrConstant(0, true),
5870 DAG.getIntPtrConstant(0, true),
5873 Chain = DAG.getCopyFromReg(Chain, dl, X86StackPtr, SPTy).getValue(1);
5875 SDValue Ops1[2] = { Chain.getValue(0), Chain };
5876 return DAG.getMergeValues(Ops1, 2, dl);
5880 X86TargetLowering::EmitTargetCodeForMemset(SelectionDAG &DAG, DebugLoc dl,
5882 SDValue Dst, SDValue Src,
5883 SDValue Size, unsigned Align,
5885 uint64_t DstSVOff) {
5886 ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size);
5888 // If not DWORD aligned or size is more than the threshold, call the library.
5889 // The libc version is likely to be faster for these cases. It can use the
5890 // address value and run time information about the CPU.
5891 if ((Align & 3) != 0 ||
5893 ConstantSize->getZExtValue() >
5894 getSubtarget()->getMaxInlineSizeThreshold()) {
5895 SDValue InFlag(0, 0);
5897 // Check to see if there is a specialized entry-point for memory zeroing.
5898 ConstantSDNode *V = dyn_cast<ConstantSDNode>(Src);
5900 if (const char *bzeroEntry = V &&
5901 V->isNullValue() ? Subtarget->getBZeroEntry() : 0) {
5902 MVT IntPtr = getPointerTy();
5903 const Type *IntPtrTy = TD->getIntPtrType();
5904 TargetLowering::ArgListTy Args;
5905 TargetLowering::ArgListEntry Entry;
5907 Entry.Ty = IntPtrTy;
5908 Args.push_back(Entry);
5910 Args.push_back(Entry);
5911 std::pair<SDValue,SDValue> CallResult =
5912 LowerCallTo(Chain, Type::VoidTy, false, false, false, false,
5913 CallingConv::C, false,
5914 DAG.getExternalSymbol(bzeroEntry, IntPtr), Args, DAG, dl);
5915 return CallResult.second;
5918 // Otherwise have the target-independent code call memset.
5922 uint64_t SizeVal = ConstantSize->getZExtValue();
5923 SDValue InFlag(0, 0);
5926 ConstantSDNode *ValC = dyn_cast<ConstantSDNode>(Src);
5927 unsigned BytesLeft = 0;
5928 bool TwoRepStos = false;
5931 uint64_t Val = ValC->getZExtValue() & 255;
5933 // If the value is a constant, then we can potentially use larger sets.
5934 switch (Align & 3) {
5935 case 2: // WORD aligned
5938 Val = (Val << 8) | Val;
5940 case 0: // DWORD aligned
5943 Val = (Val << 8) | Val;
5944 Val = (Val << 16) | Val;
5945 if (Subtarget->is64Bit() && ((Align & 0x7) == 0)) { // QWORD aligned
5948 Val = (Val << 32) | Val;
5951 default: // Byte aligned
5954 Count = DAG.getIntPtrConstant(SizeVal);
5958 if (AVT.bitsGT(MVT::i8)) {
5959 unsigned UBytes = AVT.getSizeInBits() / 8;
5960 Count = DAG.getIntPtrConstant(SizeVal / UBytes);
5961 BytesLeft = SizeVal % UBytes;
5964 Chain = DAG.getCopyToReg(Chain, dl, ValReg, DAG.getConstant(Val, AVT),
5966 InFlag = Chain.getValue(1);
5969 Count = DAG.getIntPtrConstant(SizeVal);
5970 Chain = DAG.getCopyToReg(Chain, dl, X86::AL, Src, InFlag);
5971 InFlag = Chain.getValue(1);
5974 Chain = DAG.getCopyToReg(Chain, dl, Subtarget->is64Bit() ? X86::RCX :
5977 InFlag = Chain.getValue(1);
5978 Chain = DAG.getCopyToReg(Chain, dl, Subtarget->is64Bit() ? X86::RDI :
5981 InFlag = Chain.getValue(1);
5983 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
5984 SmallVector<SDValue, 8> Ops;
5985 Ops.push_back(Chain);
5986 Ops.push_back(DAG.getValueType(AVT));
5987 Ops.push_back(InFlag);
5988 Chain = DAG.getNode(X86ISD::REP_STOS, dl, Tys, &Ops[0], Ops.size());
5991 InFlag = Chain.getValue(1);
5993 MVT CVT = Count.getValueType();
5994 SDValue Left = DAG.getNode(ISD::AND, dl, CVT, Count,
5995 DAG.getConstant((AVT == MVT::i64) ? 7 : 3, CVT));
5996 Chain = DAG.getCopyToReg(Chain, dl, (CVT == MVT::i64) ? X86::RCX :
5999 InFlag = Chain.getValue(1);
6000 Tys = DAG.getVTList(MVT::Other, MVT::Flag);
6002 Ops.push_back(Chain);
6003 Ops.push_back(DAG.getValueType(MVT::i8));
6004 Ops.push_back(InFlag);
6005 Chain = DAG.getNode(X86ISD::REP_STOS, dl, Tys, &Ops[0], Ops.size());
6006 } else if (BytesLeft) {
6007 // Handle the last 1 - 7 bytes.
6008 unsigned Offset = SizeVal - BytesLeft;
6009 MVT AddrVT = Dst.getValueType();
6010 MVT SizeVT = Size.getValueType();
6012 Chain = DAG.getMemset(Chain, dl,
6013 DAG.getNode(ISD::ADD, dl, AddrVT, Dst,
6014 DAG.getConstant(Offset, AddrVT)),
6016 DAG.getConstant(BytesLeft, SizeVT),
6017 Align, DstSV, DstSVOff + Offset);
6020 // TODO: Use a Tokenfactor, as in memcpy, instead of a single chain.
6025 X86TargetLowering::EmitTargetCodeForMemcpy(SelectionDAG &DAG, DebugLoc dl,
6026 SDValue Chain, SDValue Dst, SDValue Src,
6027 SDValue Size, unsigned Align,
6029 const Value *DstSV, uint64_t DstSVOff,
6030 const Value *SrcSV, uint64_t SrcSVOff) {
6031 // This requires the copy size to be a constant, preferrably
6032 // within a subtarget-specific limit.
6033 ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size);
6036 uint64_t SizeVal = ConstantSize->getZExtValue();
6037 if (!AlwaysInline && SizeVal > getSubtarget()->getMaxInlineSizeThreshold())
6040 /// If not DWORD aligned, call the library.
6041 if ((Align & 3) != 0)
6046 if (Subtarget->is64Bit() && ((Align & 0x7) == 0)) // QWORD aligned
6049 unsigned UBytes = AVT.getSizeInBits() / 8;
6050 unsigned CountVal = SizeVal / UBytes;
6051 SDValue Count = DAG.getIntPtrConstant(CountVal);
6052 unsigned BytesLeft = SizeVal % UBytes;
6054 SDValue InFlag(0, 0);
6055 Chain = DAG.getCopyToReg(Chain, dl, Subtarget->is64Bit() ? X86::RCX :
6058 InFlag = Chain.getValue(1);
6059 Chain = DAG.getCopyToReg(Chain, dl, Subtarget->is64Bit() ? X86::RDI :
6062 InFlag = Chain.getValue(1);
6063 Chain = DAG.getCopyToReg(Chain, dl, Subtarget->is64Bit() ? X86::RSI :
6066 InFlag = Chain.getValue(1);
6068 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
6069 SmallVector<SDValue, 8> Ops;
6070 Ops.push_back(Chain);
6071 Ops.push_back(DAG.getValueType(AVT));
6072 Ops.push_back(InFlag);
6073 SDValue RepMovs = DAG.getNode(X86ISD::REP_MOVS, dl, Tys, &Ops[0], Ops.size());
6075 SmallVector<SDValue, 4> Results;
6076 Results.push_back(RepMovs);
6078 // Handle the last 1 - 7 bytes.
6079 unsigned Offset = SizeVal - BytesLeft;
6080 MVT DstVT = Dst.getValueType();
6081 MVT SrcVT = Src.getValueType();
6082 MVT SizeVT = Size.getValueType();
6083 Results.push_back(DAG.getMemcpy(Chain, dl,
6084 DAG.getNode(ISD::ADD, dl, DstVT, Dst,
6085 DAG.getConstant(Offset, DstVT)),
6086 DAG.getNode(ISD::ADD, dl, SrcVT, Src,
6087 DAG.getConstant(Offset, SrcVT)),
6088 DAG.getConstant(BytesLeft, SizeVT),
6089 Align, AlwaysInline,
6090 DstSV, DstSVOff + Offset,
6091 SrcSV, SrcSVOff + Offset));
6094 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
6095 &Results[0], Results.size());
6098 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) {
6099 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
6100 DebugLoc dl = Op.getDebugLoc();
6102 if (!Subtarget->is64Bit()) {
6103 // vastart just stores the address of the VarArgsFrameIndex slot into the
6104 // memory location argument.
6105 SDValue FR = DAG.getFrameIndex(VarArgsFrameIndex, getPointerTy());
6106 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1), SV, 0);
6110 // gp_offset (0 - 6 * 8)
6111 // fp_offset (48 - 48 + 8 * 16)
6112 // overflow_arg_area (point to parameters coming in memory).
6114 SmallVector<SDValue, 8> MemOps;
6115 SDValue FIN = Op.getOperand(1);
6117 SDValue Store = DAG.getStore(Op.getOperand(0), dl,
6118 DAG.getConstant(VarArgsGPOffset, MVT::i32),
6120 MemOps.push_back(Store);
6123 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(),
6124 FIN, DAG.getIntPtrConstant(4));
6125 Store = DAG.getStore(Op.getOperand(0), dl,
6126 DAG.getConstant(VarArgsFPOffset, MVT::i32),
6128 MemOps.push_back(Store);
6130 // Store ptr to overflow_arg_area
6131 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(),
6132 FIN, DAG.getIntPtrConstant(4));
6133 SDValue OVFIN = DAG.getFrameIndex(VarArgsFrameIndex, getPointerTy());
6134 Store = DAG.getStore(Op.getOperand(0), dl, OVFIN, FIN, SV, 0);
6135 MemOps.push_back(Store);
6137 // Store ptr to reg_save_area.
6138 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(),
6139 FIN, DAG.getIntPtrConstant(8));
6140 SDValue RSFIN = DAG.getFrameIndex(RegSaveFrameIndex, getPointerTy());
6141 Store = DAG.getStore(Op.getOperand(0), dl, RSFIN, FIN, SV, 0);
6142 MemOps.push_back(Store);
6143 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
6144 &MemOps[0], MemOps.size());
6147 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) {
6148 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
6149 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_arg!");
6150 SDValue Chain = Op.getOperand(0);
6151 SDValue SrcPtr = Op.getOperand(1);
6152 SDValue SrcSV = Op.getOperand(2);
6154 assert(0 && "VAArgInst is not yet implemented for x86-64!");
6159 SDValue X86TargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG) {
6160 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
6161 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
6162 SDValue Chain = Op.getOperand(0);
6163 SDValue DstPtr = Op.getOperand(1);
6164 SDValue SrcPtr = Op.getOperand(2);
6165 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
6166 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
6167 DebugLoc dl = Op.getDebugLoc();
6169 return DAG.getMemcpy(Chain, dl, DstPtr, SrcPtr,
6170 DAG.getIntPtrConstant(24), 8, false,
6171 DstSV, 0, SrcSV, 0);
6175 X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) {
6176 DebugLoc dl = Op.getDebugLoc();
6177 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
6179 default: return SDValue(); // Don't custom lower most intrinsics.
6180 // Comparison intrinsics.
6181 case Intrinsic::x86_sse_comieq_ss:
6182 case Intrinsic::x86_sse_comilt_ss:
6183 case Intrinsic::x86_sse_comile_ss:
6184 case Intrinsic::x86_sse_comigt_ss:
6185 case Intrinsic::x86_sse_comige_ss:
6186 case Intrinsic::x86_sse_comineq_ss:
6187 case Intrinsic::x86_sse_ucomieq_ss:
6188 case Intrinsic::x86_sse_ucomilt_ss:
6189 case Intrinsic::x86_sse_ucomile_ss:
6190 case Intrinsic::x86_sse_ucomigt_ss:
6191 case Intrinsic::x86_sse_ucomige_ss:
6192 case Intrinsic::x86_sse_ucomineq_ss:
6193 case Intrinsic::x86_sse2_comieq_sd:
6194 case Intrinsic::x86_sse2_comilt_sd:
6195 case Intrinsic::x86_sse2_comile_sd:
6196 case Intrinsic::x86_sse2_comigt_sd:
6197 case Intrinsic::x86_sse2_comige_sd:
6198 case Intrinsic::x86_sse2_comineq_sd:
6199 case Intrinsic::x86_sse2_ucomieq_sd:
6200 case Intrinsic::x86_sse2_ucomilt_sd:
6201 case Intrinsic::x86_sse2_ucomile_sd:
6202 case Intrinsic::x86_sse2_ucomigt_sd:
6203 case Intrinsic::x86_sse2_ucomige_sd:
6204 case Intrinsic::x86_sse2_ucomineq_sd: {
6206 ISD::CondCode CC = ISD::SETCC_INVALID;
6209 case Intrinsic::x86_sse_comieq_ss:
6210 case Intrinsic::x86_sse2_comieq_sd:
6214 case Intrinsic::x86_sse_comilt_ss:
6215 case Intrinsic::x86_sse2_comilt_sd:
6219 case Intrinsic::x86_sse_comile_ss:
6220 case Intrinsic::x86_sse2_comile_sd:
6224 case Intrinsic::x86_sse_comigt_ss:
6225 case Intrinsic::x86_sse2_comigt_sd:
6229 case Intrinsic::x86_sse_comige_ss:
6230 case Intrinsic::x86_sse2_comige_sd:
6234 case Intrinsic::x86_sse_comineq_ss:
6235 case Intrinsic::x86_sse2_comineq_sd:
6239 case Intrinsic::x86_sse_ucomieq_ss:
6240 case Intrinsic::x86_sse2_ucomieq_sd:
6241 Opc = X86ISD::UCOMI;
6244 case Intrinsic::x86_sse_ucomilt_ss:
6245 case Intrinsic::x86_sse2_ucomilt_sd:
6246 Opc = X86ISD::UCOMI;
6249 case Intrinsic::x86_sse_ucomile_ss:
6250 case Intrinsic::x86_sse2_ucomile_sd:
6251 Opc = X86ISD::UCOMI;
6254 case Intrinsic::x86_sse_ucomigt_ss:
6255 case Intrinsic::x86_sse2_ucomigt_sd:
6256 Opc = X86ISD::UCOMI;
6259 case Intrinsic::x86_sse_ucomige_ss:
6260 case Intrinsic::x86_sse2_ucomige_sd:
6261 Opc = X86ISD::UCOMI;
6264 case Intrinsic::x86_sse_ucomineq_ss:
6265 case Intrinsic::x86_sse2_ucomineq_sd:
6266 Opc = X86ISD::UCOMI;
6271 SDValue LHS = Op.getOperand(1);
6272 SDValue RHS = Op.getOperand(2);
6273 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG);
6274 SDValue Cond = DAG.getNode(Opc, dl, MVT::i32, LHS, RHS);
6275 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
6276 DAG.getConstant(X86CC, MVT::i8), Cond);
6277 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
6280 // Fix vector shift instructions where the last operand is a non-immediate
6282 case Intrinsic::x86_sse2_pslli_w:
6283 case Intrinsic::x86_sse2_pslli_d:
6284 case Intrinsic::x86_sse2_pslli_q:
6285 case Intrinsic::x86_sse2_psrli_w:
6286 case Intrinsic::x86_sse2_psrli_d:
6287 case Intrinsic::x86_sse2_psrli_q:
6288 case Intrinsic::x86_sse2_psrai_w:
6289 case Intrinsic::x86_sse2_psrai_d:
6290 case Intrinsic::x86_mmx_pslli_w:
6291 case Intrinsic::x86_mmx_pslli_d:
6292 case Intrinsic::x86_mmx_pslli_q:
6293 case Intrinsic::x86_mmx_psrli_w:
6294 case Intrinsic::x86_mmx_psrli_d:
6295 case Intrinsic::x86_mmx_psrli_q:
6296 case Intrinsic::x86_mmx_psrai_w:
6297 case Intrinsic::x86_mmx_psrai_d: {
6298 SDValue ShAmt = Op.getOperand(2);
6299 if (isa<ConstantSDNode>(ShAmt))
6302 unsigned NewIntNo = 0;
6303 MVT ShAmtVT = MVT::v4i32;
6305 case Intrinsic::x86_sse2_pslli_w:
6306 NewIntNo = Intrinsic::x86_sse2_psll_w;
6308 case Intrinsic::x86_sse2_pslli_d:
6309 NewIntNo = Intrinsic::x86_sse2_psll_d;
6311 case Intrinsic::x86_sse2_pslli_q:
6312 NewIntNo = Intrinsic::x86_sse2_psll_q;
6314 case Intrinsic::x86_sse2_psrli_w:
6315 NewIntNo = Intrinsic::x86_sse2_psrl_w;
6317 case Intrinsic::x86_sse2_psrli_d:
6318 NewIntNo = Intrinsic::x86_sse2_psrl_d;
6320 case Intrinsic::x86_sse2_psrli_q:
6321 NewIntNo = Intrinsic::x86_sse2_psrl_q;
6323 case Intrinsic::x86_sse2_psrai_w:
6324 NewIntNo = Intrinsic::x86_sse2_psra_w;
6326 case Intrinsic::x86_sse2_psrai_d:
6327 NewIntNo = Intrinsic::x86_sse2_psra_d;
6330 ShAmtVT = MVT::v2i32;
6332 case Intrinsic::x86_mmx_pslli_w:
6333 NewIntNo = Intrinsic::x86_mmx_psll_w;
6335 case Intrinsic::x86_mmx_pslli_d:
6336 NewIntNo = Intrinsic::x86_mmx_psll_d;
6338 case Intrinsic::x86_mmx_pslli_q:
6339 NewIntNo = Intrinsic::x86_mmx_psll_q;
6341 case Intrinsic::x86_mmx_psrli_w:
6342 NewIntNo = Intrinsic::x86_mmx_psrl_w;
6344 case Intrinsic::x86_mmx_psrli_d:
6345 NewIntNo = Intrinsic::x86_mmx_psrl_d;
6347 case Intrinsic::x86_mmx_psrli_q:
6348 NewIntNo = Intrinsic::x86_mmx_psrl_q;
6350 case Intrinsic::x86_mmx_psrai_w:
6351 NewIntNo = Intrinsic::x86_mmx_psra_w;
6353 case Intrinsic::x86_mmx_psrai_d:
6354 NewIntNo = Intrinsic::x86_mmx_psra_d;
6356 default: abort(); // Can't reach here.
6361 MVT VT = Op.getValueType();
6362 ShAmt = DAG.getNode(ISD::BIT_CONVERT, dl, VT,
6363 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, ShAmtVT, ShAmt));
6364 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
6365 DAG.getConstant(NewIntNo, MVT::i32),
6366 Op.getOperand(1), ShAmt);
6371 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) {
6372 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
6373 DebugLoc dl = Op.getDebugLoc();
6376 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
6378 DAG.getConstant(TD->getPointerSize(),
6379 Subtarget->is64Bit() ? MVT::i64 : MVT::i32);
6380 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
6381 DAG.getNode(ISD::ADD, dl, getPointerTy(),
6386 // Just load the return address.
6387 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
6388 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
6389 RetAddrFI, NULL, 0);
6392 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) {
6393 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
6394 MFI->setFrameAddressIsTaken(true);
6395 MVT VT = Op.getValueType();
6396 DebugLoc dl = Op.getDebugLoc(); // FIXME probably not meaningful
6397 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
6398 unsigned FrameReg = Subtarget->is64Bit() ? X86::RBP : X86::EBP;
6399 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
6401 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr, NULL, 0);
6405 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
6406 SelectionDAG &DAG) {
6407 return DAG.getIntPtrConstant(2*TD->getPointerSize());
6410 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG)
6412 MachineFunction &MF = DAG.getMachineFunction();
6413 SDValue Chain = Op.getOperand(0);
6414 SDValue Offset = Op.getOperand(1);
6415 SDValue Handler = Op.getOperand(2);
6416 DebugLoc dl = Op.getDebugLoc();
6418 SDValue Frame = DAG.getRegister(Subtarget->is64Bit() ? X86::RBP : X86::EBP,
6420 unsigned StoreAddrReg = (Subtarget->is64Bit() ? X86::RCX : X86::ECX);
6422 SDValue StoreAddr = DAG.getNode(ISD::SUB, dl, getPointerTy(), Frame,
6423 DAG.getIntPtrConstant(-TD->getPointerSize()));
6424 StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), StoreAddr, Offset);
6425 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, NULL, 0);
6426 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
6427 MF.getRegInfo().addLiveOut(StoreAddrReg);
6429 return DAG.getNode(X86ISD::EH_RETURN, dl,
6431 Chain, DAG.getRegister(StoreAddrReg, getPointerTy()));
6434 SDValue X86TargetLowering::LowerTRAMPOLINE(SDValue Op,
6435 SelectionDAG &DAG) {
6436 SDValue Root = Op.getOperand(0);
6437 SDValue Trmp = Op.getOperand(1); // trampoline
6438 SDValue FPtr = Op.getOperand(2); // nested function
6439 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
6440 DebugLoc dl = Op.getDebugLoc();
6442 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
6444 const X86InstrInfo *TII =
6445 ((X86TargetMachine&)getTargetMachine()).getInstrInfo();
6447 if (Subtarget->is64Bit()) {
6448 SDValue OutChains[6];
6450 // Large code-model.
6452 const unsigned char JMP64r = TII->getBaseOpcodeFor(X86::JMP64r);
6453 const unsigned char MOV64ri = TII->getBaseOpcodeFor(X86::MOV64ri);
6455 const unsigned char N86R10 = RegInfo->getX86RegNum(X86::R10);
6456 const unsigned char N86R11 = RegInfo->getX86RegNum(X86::R11);
6458 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
6460 // Load the pointer to the nested function into R11.
6461 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
6462 SDValue Addr = Trmp;
6463 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
6466 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
6467 DAG.getConstant(2, MVT::i64));
6468 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr, TrmpAddr, 2, false, 2);
6470 // Load the 'nest' parameter value into R10.
6471 // R10 is specified in X86CallingConv.td
6472 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
6473 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
6474 DAG.getConstant(10, MVT::i64));
6475 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
6476 Addr, TrmpAddr, 10);
6478 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
6479 DAG.getConstant(12, MVT::i64));
6480 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr, TrmpAddr, 12, false, 2);
6482 // Jump to the nested function.
6483 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
6484 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
6485 DAG.getConstant(20, MVT::i64));
6486 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
6487 Addr, TrmpAddr, 20);
6489 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
6490 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
6491 DAG.getConstant(22, MVT::i64));
6492 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr,
6496 { Trmp, DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 6) };
6497 return DAG.getMergeValues(Ops, 2, dl);
6499 const Function *Func =
6500 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
6501 unsigned CC = Func->getCallingConv();
6506 assert(0 && "Unsupported calling convention");
6507 case CallingConv::C:
6508 case CallingConv::X86_StdCall: {
6509 // Pass 'nest' parameter in ECX.
6510 // Must be kept in sync with X86CallingConv.td
6513 // Check that ECX wasn't needed by an 'inreg' parameter.
6514 const FunctionType *FTy = Func->getFunctionType();
6515 const AttrListPtr &Attrs = Func->getAttributes();
6517 if (!Attrs.isEmpty() && !Func->isVarArg()) {
6518 unsigned InRegCount = 0;
6521 for (FunctionType::param_iterator I = FTy->param_begin(),
6522 E = FTy->param_end(); I != E; ++I, ++Idx)
6523 if (Attrs.paramHasAttr(Idx, Attribute::InReg))
6524 // FIXME: should only count parameters that are lowered to integers.
6525 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32;
6527 if (InRegCount > 2) {
6528 cerr << "Nest register in use - reduce number of inreg parameters!\n";
6534 case CallingConv::X86_FastCall:
6535 case CallingConv::Fast:
6536 // Pass 'nest' parameter in EAX.
6537 // Must be kept in sync with X86CallingConv.td
6542 SDValue OutChains[4];
6545 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
6546 DAG.getConstant(10, MVT::i32));
6547 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
6549 const unsigned char MOV32ri = TII->getBaseOpcodeFor(X86::MOV32ri);
6550 const unsigned char N86Reg = RegInfo->getX86RegNum(NestReg);
6551 OutChains[0] = DAG.getStore(Root, dl,
6552 DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
6555 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
6556 DAG.getConstant(1, MVT::i32));
6557 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr, TrmpAddr, 1, false, 1);
6559 const unsigned char JMP = TII->getBaseOpcodeFor(X86::JMP);
6560 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
6561 DAG.getConstant(5, MVT::i32));
6562 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr,
6563 TrmpAddr, 5, false, 1);
6565 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
6566 DAG.getConstant(6, MVT::i32));
6567 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr, TrmpAddr, 6, false, 1);
6570 { Trmp, DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 4) };
6571 return DAG.getMergeValues(Ops, 2, dl);
6575 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) {
6577 The rounding mode is in bits 11:10 of FPSR, and has the following
6584 FLT_ROUNDS, on the other hand, expects the following:
6591 To perform the conversion, we do:
6592 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
6595 MachineFunction &MF = DAG.getMachineFunction();
6596 const TargetMachine &TM = MF.getTarget();
6597 const TargetFrameInfo &TFI = *TM.getFrameInfo();
6598 unsigned StackAlignment = TFI.getStackAlignment();
6599 MVT VT = Op.getValueType();
6600 DebugLoc dl = Op.getDebugLoc();
6602 // Save FP Control Word to stack slot
6603 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment);
6604 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
6606 SDValue Chain = DAG.getNode(X86ISD::FNSTCW16m, dl, MVT::Other,
6607 DAG.getEntryNode(), StackSlot);
6609 // Load FP Control Word from stack slot
6610 SDValue CWD = DAG.getLoad(MVT::i16, dl, Chain, StackSlot, NULL, 0);
6612 // Transform as necessary
6614 DAG.getNode(ISD::SRL, dl, MVT::i16,
6615 DAG.getNode(ISD::AND, dl, MVT::i16,
6616 CWD, DAG.getConstant(0x800, MVT::i16)),
6617 DAG.getConstant(11, MVT::i8));
6619 DAG.getNode(ISD::SRL, dl, MVT::i16,
6620 DAG.getNode(ISD::AND, dl, MVT::i16,
6621 CWD, DAG.getConstant(0x400, MVT::i16)),
6622 DAG.getConstant(9, MVT::i8));
6625 DAG.getNode(ISD::AND, dl, MVT::i16,
6626 DAG.getNode(ISD::ADD, dl, MVT::i16,
6627 DAG.getNode(ISD::OR, dl, MVT::i16, CWD1, CWD2),
6628 DAG.getConstant(1, MVT::i16)),
6629 DAG.getConstant(3, MVT::i16));
6632 return DAG.getNode((VT.getSizeInBits() < 16 ?
6633 ISD::TRUNCATE : ISD::ZERO_EXTEND), dl, VT, RetVal);
6636 SDValue X86TargetLowering::LowerCTLZ(SDValue Op, SelectionDAG &DAG) {
6637 MVT VT = Op.getValueType();
6639 unsigned NumBits = VT.getSizeInBits();
6640 DebugLoc dl = Op.getDebugLoc();
6642 Op = Op.getOperand(0);
6643 if (VT == MVT::i8) {
6644 // Zero extend to i32 since there is not an i8 bsr.
6646 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
6649 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
6650 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
6651 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
6653 // If src is zero (i.e. bsr sets ZF), returns NumBits.
6654 SmallVector<SDValue, 4> Ops;
6656 Ops.push_back(DAG.getConstant(NumBits+NumBits-1, OpVT));
6657 Ops.push_back(DAG.getConstant(X86::COND_E, MVT::i8));
6658 Ops.push_back(Op.getValue(1));
6659 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, &Ops[0], 4);
6661 // Finally xor with NumBits-1.
6662 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
6665 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
6669 SDValue X86TargetLowering::LowerCTTZ(SDValue Op, SelectionDAG &DAG) {
6670 MVT VT = Op.getValueType();
6672 unsigned NumBits = VT.getSizeInBits();
6673 DebugLoc dl = Op.getDebugLoc();
6675 Op = Op.getOperand(0);
6676 if (VT == MVT::i8) {
6678 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
6681 // Issue a bsf (scan bits forward) which also sets EFLAGS.
6682 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
6683 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op);
6685 // If src is zero (i.e. bsf sets ZF), returns NumBits.
6686 SmallVector<SDValue, 4> Ops;
6688 Ops.push_back(DAG.getConstant(NumBits, OpVT));
6689 Ops.push_back(DAG.getConstant(X86::COND_E, MVT::i8));
6690 Ops.push_back(Op.getValue(1));
6691 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, &Ops[0], 4);
6694 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
6698 SDValue X86TargetLowering::LowerMUL_V2I64(SDValue Op, SelectionDAG &DAG) {
6699 MVT VT = Op.getValueType();
6700 assert(VT == MVT::v2i64 && "Only know how to lower V2I64 multiply");
6701 DebugLoc dl = Op.getDebugLoc();
6703 // ulong2 Ahi = __builtin_ia32_psrlqi128( a, 32);
6704 // ulong2 Bhi = __builtin_ia32_psrlqi128( b, 32);
6705 // ulong2 AloBlo = __builtin_ia32_pmuludq128( a, b );
6706 // ulong2 AloBhi = __builtin_ia32_pmuludq128( a, Bhi );
6707 // ulong2 AhiBlo = __builtin_ia32_pmuludq128( Ahi, b );
6709 // AloBhi = __builtin_ia32_psllqi128( AloBhi, 32 );
6710 // AhiBlo = __builtin_ia32_psllqi128( AhiBlo, 32 );
6711 // return AloBlo + AloBhi + AhiBlo;
6713 SDValue A = Op.getOperand(0);
6714 SDValue B = Op.getOperand(1);
6716 SDValue Ahi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
6717 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32),
6718 A, DAG.getConstant(32, MVT::i32));
6719 SDValue Bhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
6720 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32),
6721 B, DAG.getConstant(32, MVT::i32));
6722 SDValue AloBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
6723 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32),
6725 SDValue AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
6726 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32),
6728 SDValue AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
6729 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32),
6731 AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
6732 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32),
6733 AloBhi, DAG.getConstant(32, MVT::i32));
6734 AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
6735 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32),
6736 AhiBlo, DAG.getConstant(32, MVT::i32));
6737 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
6738 Res = DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
6743 SDValue X86TargetLowering::LowerXALUO(SDValue Op, SelectionDAG &DAG) {
6744 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
6745 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
6746 // looks for this combo and may remove the "setcc" instruction if the "setcc"
6747 // has only one use.
6748 SDNode *N = Op.getNode();
6749 SDValue LHS = N->getOperand(0);
6750 SDValue RHS = N->getOperand(1);
6751 unsigned BaseOp = 0;
6753 DebugLoc dl = Op.getDebugLoc();
6755 switch (Op.getOpcode()) {
6756 default: assert(0 && "Unknown ovf instruction!");
6758 // A subtract of one will be selected as a INC. Note that INC doesn't
6759 // set CF, so we can't do this for UADDO.
6760 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op))
6761 if (C->getAPIntValue() == 1) {
6762 BaseOp = X86ISD::INC;
6766 BaseOp = X86ISD::ADD;
6770 BaseOp = X86ISD::ADD;
6774 // A subtract of one will be selected as a DEC. Note that DEC doesn't
6775 // set CF, so we can't do this for USUBO.
6776 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op))
6777 if (C->getAPIntValue() == 1) {
6778 BaseOp = X86ISD::DEC;
6782 BaseOp = X86ISD::SUB;
6786 BaseOp = X86ISD::SUB;
6790 BaseOp = X86ISD::SMUL;
6794 BaseOp = X86ISD::UMUL;
6799 // Also sets EFLAGS.
6800 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
6801 SDValue Sum = DAG.getNode(BaseOp, dl, VTs, LHS, RHS);
6804 DAG.getNode(X86ISD::SETCC, dl, N->getValueType(1),
6805 DAG.getConstant(Cond, MVT::i32), SDValue(Sum.getNode(), 1));
6807 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), SetCC);
6811 SDValue X86TargetLowering::LowerCMP_SWAP(SDValue Op, SelectionDAG &DAG) {
6812 MVT T = Op.getValueType();
6813 DebugLoc dl = Op.getDebugLoc();
6816 switch(T.getSimpleVT()) {
6818 assert(false && "Invalid value type!");
6819 case MVT::i8: Reg = X86::AL; size = 1; break;
6820 case MVT::i16: Reg = X86::AX; size = 2; break;
6821 case MVT::i32: Reg = X86::EAX; size = 4; break;
6823 assert(Subtarget->is64Bit() && "Node not type legal!");
6824 Reg = X86::RAX; size = 8;
6827 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), dl, Reg,
6828 Op.getOperand(2), SDValue());
6829 SDValue Ops[] = { cpIn.getValue(0),
6832 DAG.getTargetConstant(size, MVT::i8),
6834 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
6835 SDValue Result = DAG.getNode(X86ISD::LCMPXCHG_DAG, dl, Tys, Ops, 5);
6837 DAG.getCopyFromReg(Result.getValue(0), dl, Reg, T, Result.getValue(1));
6841 SDValue X86TargetLowering::LowerREADCYCLECOUNTER(SDValue Op,
6842 SelectionDAG &DAG) {
6843 assert(Subtarget->is64Bit() && "Result not type legalized?");
6844 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
6845 SDValue TheChain = Op.getOperand(0);
6846 DebugLoc dl = Op.getDebugLoc();
6847 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
6848 SDValue rax = DAG.getCopyFromReg(rd, dl, X86::RAX, MVT::i64, rd.getValue(1));
6849 SDValue rdx = DAG.getCopyFromReg(rax.getValue(1), dl, X86::RDX, MVT::i64,
6851 SDValue Tmp = DAG.getNode(ISD::SHL, dl, MVT::i64, rdx,
6852 DAG.getConstant(32, MVT::i8));
6854 DAG.getNode(ISD::OR, dl, MVT::i64, rax, Tmp),
6857 return DAG.getMergeValues(Ops, 2, dl);
6860 SDValue X86TargetLowering::LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) {
6861 SDNode *Node = Op.getNode();
6862 DebugLoc dl = Node->getDebugLoc();
6863 MVT T = Node->getValueType(0);
6864 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
6865 DAG.getConstant(0, T), Node->getOperand(2));
6866 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
6867 cast<AtomicSDNode>(Node)->getMemoryVT(),
6868 Node->getOperand(0),
6869 Node->getOperand(1), negOp,
6870 cast<AtomicSDNode>(Node)->getSrcValue(),
6871 cast<AtomicSDNode>(Node)->getAlignment());
6874 /// LowerOperation - Provide custom lowering hooks for some operations.
6876 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
6877 switch (Op.getOpcode()) {
6878 default: assert(0 && "Should not custom lower this!");
6879 case ISD::ATOMIC_CMP_SWAP: return LowerCMP_SWAP(Op,DAG);
6880 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
6881 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
6882 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
6883 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
6884 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
6885 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
6886 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
6887 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
6888 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
6889 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
6890 case ISD::SHL_PARTS:
6891 case ISD::SRA_PARTS:
6892 case ISD::SRL_PARTS: return LowerShift(Op, DAG);
6893 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
6894 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
6895 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
6896 case ISD::FABS: return LowerFABS(Op, DAG);
6897 case ISD::FNEG: return LowerFNEG(Op, DAG);
6898 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
6899 case ISD::SETCC: return LowerSETCC(Op, DAG);
6900 case ISD::VSETCC: return LowerVSETCC(Op, DAG);
6901 case ISD::SELECT: return LowerSELECT(Op, DAG);
6902 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
6903 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
6904 case ISD::CALL: return LowerCALL(Op, DAG);
6905 case ISD::RET: return LowerRET(Op, DAG);
6906 case ISD::FORMAL_ARGUMENTS: return LowerFORMAL_ARGUMENTS(Op, DAG);
6907 case ISD::VASTART: return LowerVASTART(Op, DAG);
6908 case ISD::VAARG: return LowerVAARG(Op, DAG);
6909 case ISD::VACOPY: return LowerVACOPY(Op, DAG);
6910 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
6911 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
6912 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
6913 case ISD::FRAME_TO_ARGS_OFFSET:
6914 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
6915 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
6916 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
6917 case ISD::TRAMPOLINE: return LowerTRAMPOLINE(Op, DAG);
6918 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
6919 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
6920 case ISD::CTTZ: return LowerCTTZ(Op, DAG);
6921 case ISD::MUL: return LowerMUL_V2I64(Op, DAG);
6927 case ISD::UMULO: return LowerXALUO(Op, DAG);
6928 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, DAG);
6932 void X86TargetLowering::
6933 ReplaceATOMIC_BINARY_64(SDNode *Node, SmallVectorImpl<SDValue>&Results,
6934 SelectionDAG &DAG, unsigned NewOp) {
6935 MVT T = Node->getValueType(0);
6936 DebugLoc dl = Node->getDebugLoc();
6937 assert (T == MVT::i64 && "Only know how to expand i64 atomics");
6939 SDValue Chain = Node->getOperand(0);
6940 SDValue In1 = Node->getOperand(1);
6941 SDValue In2L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
6942 Node->getOperand(2), DAG.getIntPtrConstant(0));
6943 SDValue In2H = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
6944 Node->getOperand(2), DAG.getIntPtrConstant(1));
6945 // This is a generalized SDNode, not an AtomicSDNode, so it doesn't
6946 // have a MemOperand. Pass the info through as a normal operand.
6947 SDValue LSI = DAG.getMemOperand(cast<MemSDNode>(Node)->getMemOperand());
6948 SDValue Ops[] = { Chain, In1, In2L, In2H, LSI };
6949 SDVTList Tys = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other);
6950 SDValue Result = DAG.getNode(NewOp, dl, Tys, Ops, 5);
6951 SDValue OpsF[] = { Result.getValue(0), Result.getValue(1)};
6952 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2));
6953 Results.push_back(Result.getValue(2));
6956 /// ReplaceNodeResults - Replace a node with an illegal result type
6957 /// with a new node built out of custom code.
6958 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
6959 SmallVectorImpl<SDValue>&Results,
6960 SelectionDAG &DAG) {
6961 DebugLoc dl = N->getDebugLoc();
6962 switch (N->getOpcode()) {
6964 assert(false && "Do not know how to custom type legalize this operation!");
6966 case ISD::FP_TO_SINT: {
6967 std::pair<SDValue,SDValue> Vals = FP_TO_SINTHelper(SDValue(N, 0), DAG);
6968 SDValue FIST = Vals.first, StackSlot = Vals.second;
6969 if (FIST.getNode() != 0) {
6970 MVT VT = N->getValueType(0);
6971 // Return a load from the stack slot.
6972 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot, NULL, 0));
6976 case ISD::READCYCLECOUNTER: {
6977 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
6978 SDValue TheChain = N->getOperand(0);
6979 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
6980 SDValue eax = DAG.getCopyFromReg(rd, dl, X86::EAX, MVT::i32,
6982 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), dl, X86::EDX, MVT::i32,
6984 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
6985 SDValue Ops[] = { eax, edx };
6986 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Ops, 2));
6987 Results.push_back(edx.getValue(1));
6990 case ISD::ATOMIC_CMP_SWAP: {
6991 MVT T = N->getValueType(0);
6992 assert (T == MVT::i64 && "Only know how to expand i64 Cmp and Swap");
6993 SDValue cpInL, cpInH;
6994 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(2),
6995 DAG.getConstant(0, MVT::i32));
6996 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(2),
6997 DAG.getConstant(1, MVT::i32));
6998 cpInL = DAG.getCopyToReg(N->getOperand(0), dl, X86::EAX, cpInL, SDValue());
6999 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl, X86::EDX, cpInH,
7001 SDValue swapInL, swapInH;
7002 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(3),
7003 DAG.getConstant(0, MVT::i32));
7004 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(3),
7005 DAG.getConstant(1, MVT::i32));
7006 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl, X86::EBX, swapInL,
7008 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl, X86::ECX, swapInH,
7009 swapInL.getValue(1));
7010 SDValue Ops[] = { swapInH.getValue(0),
7012 swapInH.getValue(1) };
7013 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
7014 SDValue Result = DAG.getNode(X86ISD::LCMPXCHG8_DAG, dl, Tys, Ops, 3);
7015 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl, X86::EAX,
7016 MVT::i32, Result.getValue(1));
7017 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl, X86::EDX,
7018 MVT::i32, cpOutL.getValue(2));
7019 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
7020 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2));
7021 Results.push_back(cpOutH.getValue(1));
7024 case ISD::ATOMIC_LOAD_ADD:
7025 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMADD64_DAG);
7027 case ISD::ATOMIC_LOAD_AND:
7028 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMAND64_DAG);
7030 case ISD::ATOMIC_LOAD_NAND:
7031 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMNAND64_DAG);
7033 case ISD::ATOMIC_LOAD_OR:
7034 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMOR64_DAG);
7036 case ISD::ATOMIC_LOAD_SUB:
7037 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSUB64_DAG);
7039 case ISD::ATOMIC_LOAD_XOR:
7040 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMXOR64_DAG);
7042 case ISD::ATOMIC_SWAP:
7043 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSWAP64_DAG);
7048 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
7050 default: return NULL;
7051 case X86ISD::BSF: return "X86ISD::BSF";
7052 case X86ISD::BSR: return "X86ISD::BSR";
7053 case X86ISD::SHLD: return "X86ISD::SHLD";
7054 case X86ISD::SHRD: return "X86ISD::SHRD";
7055 case X86ISD::FAND: return "X86ISD::FAND";
7056 case X86ISD::FOR: return "X86ISD::FOR";
7057 case X86ISD::FXOR: return "X86ISD::FXOR";
7058 case X86ISD::FSRL: return "X86ISD::FSRL";
7059 case X86ISD::FILD: return "X86ISD::FILD";
7060 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
7061 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
7062 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
7063 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
7064 case X86ISD::FLD: return "X86ISD::FLD";
7065 case X86ISD::FST: return "X86ISD::FST";
7066 case X86ISD::CALL: return "X86ISD::CALL";
7067 case X86ISD::TAILCALL: return "X86ISD::TAILCALL";
7068 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
7069 case X86ISD::BT: return "X86ISD::BT";
7070 case X86ISD::CMP: return "X86ISD::CMP";
7071 case X86ISD::COMI: return "X86ISD::COMI";
7072 case X86ISD::UCOMI: return "X86ISD::UCOMI";
7073 case X86ISD::SETCC: return "X86ISD::SETCC";
7074 case X86ISD::CMOV: return "X86ISD::CMOV";
7075 case X86ISD::BRCOND: return "X86ISD::BRCOND";
7076 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
7077 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
7078 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
7079 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
7080 case X86ISD::Wrapper: return "X86ISD::Wrapper";
7081 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
7082 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
7083 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
7084 case X86ISD::PINSRB: return "X86ISD::PINSRB";
7085 case X86ISD::PINSRW: return "X86ISD::PINSRW";
7086 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
7087 case X86ISD::FMAX: return "X86ISD::FMAX";
7088 case X86ISD::FMIN: return "X86ISD::FMIN";
7089 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
7090 case X86ISD::FRCP: return "X86ISD::FRCP";
7091 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
7092 case X86ISD::THREAD_POINTER: return "X86ISD::THREAD_POINTER";
7093 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
7094 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
7095 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
7096 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
7097 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
7098 case X86ISD::ATOMADD64_DAG: return "X86ISD::ATOMADD64_DAG";
7099 case X86ISD::ATOMSUB64_DAG: return "X86ISD::ATOMSUB64_DAG";
7100 case X86ISD::ATOMOR64_DAG: return "X86ISD::ATOMOR64_DAG";
7101 case X86ISD::ATOMXOR64_DAG: return "X86ISD::ATOMXOR64_DAG";
7102 case X86ISD::ATOMAND64_DAG: return "X86ISD::ATOMAND64_DAG";
7103 case X86ISD::ATOMNAND64_DAG: return "X86ISD::ATOMNAND64_DAG";
7104 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
7105 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
7106 case X86ISD::VSHL: return "X86ISD::VSHL";
7107 case X86ISD::VSRL: return "X86ISD::VSRL";
7108 case X86ISD::CMPPD: return "X86ISD::CMPPD";
7109 case X86ISD::CMPPS: return "X86ISD::CMPPS";
7110 case X86ISD::PCMPEQB: return "X86ISD::PCMPEQB";
7111 case X86ISD::PCMPEQW: return "X86ISD::PCMPEQW";
7112 case X86ISD::PCMPEQD: return "X86ISD::PCMPEQD";
7113 case X86ISD::PCMPEQQ: return "X86ISD::PCMPEQQ";
7114 case X86ISD::PCMPGTB: return "X86ISD::PCMPGTB";
7115 case X86ISD::PCMPGTW: return "X86ISD::PCMPGTW";
7116 case X86ISD::PCMPGTD: return "X86ISD::PCMPGTD";
7117 case X86ISD::PCMPGTQ: return "X86ISD::PCMPGTQ";
7118 case X86ISD::ADD: return "X86ISD::ADD";
7119 case X86ISD::SUB: return "X86ISD::SUB";
7120 case X86ISD::SMUL: return "X86ISD::SMUL";
7121 case X86ISD::UMUL: return "X86ISD::UMUL";
7122 case X86ISD::INC: return "X86ISD::INC";
7123 case X86ISD::DEC: return "X86ISD::DEC";
7127 // isLegalAddressingMode - Return true if the addressing mode represented
7128 // by AM is legal for this target, for a load/store of the specified type.
7129 bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
7130 const Type *Ty) const {
7131 // X86 supports extremely general addressing modes.
7133 // X86 allows a sign-extended 32-bit immediate field as a displacement.
7134 if (AM.BaseOffs <= -(1LL << 32) || AM.BaseOffs >= (1LL << 32)-1)
7138 // We can only fold this if we don't need an extra load.
7139 if (Subtarget->GVRequiresExtraLoad(AM.BaseGV, getTargetMachine(), false))
7141 // If BaseGV requires a register, we cannot also have a BaseReg.
7142 if (Subtarget->GVRequiresRegister(AM.BaseGV, getTargetMachine(), false) &&
7146 // X86-64 only supports addr of globals in small code model.
7147 if (Subtarget->is64Bit()) {
7148 if (getTargetMachine().getCodeModel() != CodeModel::Small)
7150 // If lower 4G is not available, then we must use rip-relative addressing.
7151 if (AM.BaseOffs || AM.Scale > 1)
7162 // These scales always work.
7167 // These scales are formed with basereg+scalereg. Only accept if there is
7172 default: // Other stuff never works.
7180 bool X86TargetLowering::isTruncateFree(const Type *Ty1, const Type *Ty2) const {
7181 if (!Ty1->isInteger() || !Ty2->isInteger())
7183 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
7184 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
7185 if (NumBits1 <= NumBits2)
7187 return Subtarget->is64Bit() || NumBits1 < 64;
7190 bool X86TargetLowering::isTruncateFree(MVT VT1, MVT VT2) const {
7191 if (!VT1.isInteger() || !VT2.isInteger())
7193 unsigned NumBits1 = VT1.getSizeInBits();
7194 unsigned NumBits2 = VT2.getSizeInBits();
7195 if (NumBits1 <= NumBits2)
7197 return Subtarget->is64Bit() || NumBits1 < 64;
7200 /// isShuffleMaskLegal - Targets can use this to indicate that they only
7201 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
7202 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
7203 /// are assumed to be legal.
7205 X86TargetLowering::isShuffleMaskLegal(SDValue Mask, MVT VT) const {
7206 // Only do shuffles on 128-bit vector types for now.
7207 // FIXME: pshufb, blends
7208 if (VT.getSizeInBits() == 64) return false;
7209 return (Mask.getNode()->getNumOperands() <= 4 ||
7210 isIdentityMask(Mask.getNode()) ||
7211 isIdentityMask(Mask.getNode(), true) ||
7212 isSplatMask(Mask.getNode()) ||
7213 X86::isPSHUFHWMask(Mask.getNode()) ||
7214 X86::isPSHUFLWMask(Mask.getNode()) ||
7215 X86::isUNPCKLMask(Mask.getNode()) ||
7216 X86::isUNPCKHMask(Mask.getNode()) ||
7217 X86::isUNPCKL_v_undef_Mask(Mask.getNode()) ||
7218 X86::isUNPCKH_v_undef_Mask(Mask.getNode()));
7222 X86TargetLowering::isVectorClearMaskLegal(const std::vector<SDValue> &BVOps,
7223 MVT EVT, SelectionDAG &DAG) const {
7224 unsigned NumElts = BVOps.size();
7225 // Only do shuffles on 128-bit vector types for now.
7226 if (EVT.getSizeInBits() * NumElts == 64) return false;
7227 if (NumElts == 2) return true;
7229 return (isMOVLMask(&BVOps[0], 4) ||
7230 isCommutedMOVL(&BVOps[0], 4, true) ||
7231 isSHUFPMask(&BVOps[0], 4) ||
7232 isCommutedSHUFP(&BVOps[0], 4));
7237 //===----------------------------------------------------------------------===//
7238 // X86 Scheduler Hooks
7239 //===----------------------------------------------------------------------===//
7241 // private utility function
7243 X86TargetLowering::EmitAtomicBitwiseWithCustomInserter(MachineInstr *bInstr,
7244 MachineBasicBlock *MBB,
7252 TargetRegisterClass *RC,
7253 bool invSrc) const {
7254 // For the atomic bitwise operator, we generate
7257 // ld t1 = [bitinstr.addr]
7258 // op t2 = t1, [bitinstr.val]
7260 // lcs dest = [bitinstr.addr], t2 [EAX is implicit]
7262 // fallthrough -->nextMBB
7263 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
7264 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
7265 MachineFunction::iterator MBBIter = MBB;
7268 /// First build the CFG
7269 MachineFunction *F = MBB->getParent();
7270 MachineBasicBlock *thisMBB = MBB;
7271 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
7272 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
7273 F->insert(MBBIter, newMBB);
7274 F->insert(MBBIter, nextMBB);
7276 // Move all successors to thisMBB to nextMBB
7277 nextMBB->transferSuccessors(thisMBB);
7279 // Update thisMBB to fall through to newMBB
7280 thisMBB->addSuccessor(newMBB);
7282 // newMBB jumps to itself and fall through to nextMBB
7283 newMBB->addSuccessor(nextMBB);
7284 newMBB->addSuccessor(newMBB);
7286 // Insert instructions into newMBB based on incoming instruction
7287 assert(bInstr->getNumOperands() < 8 && "unexpected number of operands");
7288 DebugLoc dl = bInstr->getDebugLoc();
7289 MachineOperand& destOper = bInstr->getOperand(0);
7290 MachineOperand* argOpers[6];
7291 int numArgs = bInstr->getNumOperands() - 1;
7292 for (int i=0; i < numArgs; ++i)
7293 argOpers[i] = &bInstr->getOperand(i+1);
7295 // x86 address has 4 operands: base, index, scale, and displacement
7296 int lastAddrIndx = 3; // [0,3]
7299 unsigned t1 = F->getRegInfo().createVirtualRegister(RC);
7300 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(LoadOpc), t1);
7301 for (int i=0; i <= lastAddrIndx; ++i)
7302 (*MIB).addOperand(*argOpers[i]);
7304 unsigned tt = F->getRegInfo().createVirtualRegister(RC);
7306 MIB = BuildMI(newMBB, dl, TII->get(notOpc), tt).addReg(t1);
7311 unsigned t2 = F->getRegInfo().createVirtualRegister(RC);
7312 assert((argOpers[valArgIndx]->isReg() ||
7313 argOpers[valArgIndx]->isImm()) &&
7315 if (argOpers[valArgIndx]->isReg())
7316 MIB = BuildMI(newMBB, dl, TII->get(regOpc), t2);
7318 MIB = BuildMI(newMBB, dl, TII->get(immOpc), t2);
7320 (*MIB).addOperand(*argOpers[valArgIndx]);
7322 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), EAXreg);
7325 MIB = BuildMI(newMBB, dl, TII->get(CXchgOpc));
7326 for (int i=0; i <= lastAddrIndx; ++i)
7327 (*MIB).addOperand(*argOpers[i]);
7329 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand");
7330 (*MIB).addMemOperand(*F, *bInstr->memoperands_begin());
7332 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), destOper.getReg());
7336 BuildMI(newMBB, dl, TII->get(X86::JNE)).addMBB(newMBB);
7338 F->DeleteMachineInstr(bInstr); // The pseudo instruction is gone now.
7342 // private utility function: 64 bit atomics on 32 bit host.
7344 X86TargetLowering::EmitAtomicBit6432WithCustomInserter(MachineInstr *bInstr,
7345 MachineBasicBlock *MBB,
7350 bool invSrc) const {
7351 // For the atomic bitwise operator, we generate
7352 // thisMBB (instructions are in pairs, except cmpxchg8b)
7353 // ld t1,t2 = [bitinstr.addr]
7355 // out1, out2 = phi (thisMBB, t1/t2) (newMBB, t3/t4)
7356 // op t5, t6 <- out1, out2, [bitinstr.val]
7357 // (for SWAP, substitute: mov t5, t6 <- [bitinstr.val])
7358 // mov ECX, EBX <- t5, t6
7359 // mov EAX, EDX <- t1, t2
7360 // cmpxchg8b [bitinstr.addr] [EAX, EDX, EBX, ECX implicit]
7361 // mov t3, t4 <- EAX, EDX
7363 // result in out1, out2
7364 // fallthrough -->nextMBB
7366 const TargetRegisterClass *RC = X86::GR32RegisterClass;
7367 const unsigned LoadOpc = X86::MOV32rm;
7368 const unsigned copyOpc = X86::MOV32rr;
7369 const unsigned NotOpc = X86::NOT32r;
7370 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
7371 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
7372 MachineFunction::iterator MBBIter = MBB;
7375 /// First build the CFG
7376 MachineFunction *F = MBB->getParent();
7377 MachineBasicBlock *thisMBB = MBB;
7378 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
7379 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
7380 F->insert(MBBIter, newMBB);
7381 F->insert(MBBIter, nextMBB);
7383 // Move all successors to thisMBB to nextMBB
7384 nextMBB->transferSuccessors(thisMBB);
7386 // Update thisMBB to fall through to newMBB
7387 thisMBB->addSuccessor(newMBB);
7389 // newMBB jumps to itself and fall through to nextMBB
7390 newMBB->addSuccessor(nextMBB);
7391 newMBB->addSuccessor(newMBB);
7393 DebugLoc dl = bInstr->getDebugLoc();
7394 // Insert instructions into newMBB based on incoming instruction
7395 // There are 8 "real" operands plus 9 implicit def/uses, ignored here.
7396 assert(bInstr->getNumOperands() < 18 && "unexpected number of operands");
7397 MachineOperand& dest1Oper = bInstr->getOperand(0);
7398 MachineOperand& dest2Oper = bInstr->getOperand(1);
7399 MachineOperand* argOpers[6];
7400 for (int i=0; i < 6; ++i)
7401 argOpers[i] = &bInstr->getOperand(i+2);
7403 // x86 address has 4 operands: base, index, scale, and displacement
7404 int lastAddrIndx = 3; // [0,3]
7406 unsigned t1 = F->getRegInfo().createVirtualRegister(RC);
7407 MachineInstrBuilder MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t1);
7408 for (int i=0; i <= lastAddrIndx; ++i)
7409 (*MIB).addOperand(*argOpers[i]);
7410 unsigned t2 = F->getRegInfo().createVirtualRegister(RC);
7411 MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t2);
7412 // add 4 to displacement.
7413 for (int i=0; i <= lastAddrIndx-1; ++i)
7414 (*MIB).addOperand(*argOpers[i]);
7415 MachineOperand newOp3 = *(argOpers[3]);
7417 newOp3.setImm(newOp3.getImm()+4);
7419 newOp3.setOffset(newOp3.getOffset()+4);
7420 (*MIB).addOperand(newOp3);
7422 // t3/4 are defined later, at the bottom of the loop
7423 unsigned t3 = F->getRegInfo().createVirtualRegister(RC);
7424 unsigned t4 = F->getRegInfo().createVirtualRegister(RC);
7425 BuildMI(newMBB, dl, TII->get(X86::PHI), dest1Oper.getReg())
7426 .addReg(t1).addMBB(thisMBB).addReg(t3).addMBB(newMBB);
7427 BuildMI(newMBB, dl, TII->get(X86::PHI), dest2Oper.getReg())
7428 .addReg(t2).addMBB(thisMBB).addReg(t4).addMBB(newMBB);
7430 unsigned tt1 = F->getRegInfo().createVirtualRegister(RC);
7431 unsigned tt2 = F->getRegInfo().createVirtualRegister(RC);
7433 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), tt1).addReg(t1);
7434 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), tt2).addReg(t2);
7440 assert((argOpers[4]->isReg() || argOpers[4]->isImm()) &&
7442 unsigned t5 = F->getRegInfo().createVirtualRegister(RC);
7443 unsigned t6 = F->getRegInfo().createVirtualRegister(RC);
7444 if (argOpers[4]->isReg())
7445 MIB = BuildMI(newMBB, dl, TII->get(regOpcL), t5);
7447 MIB = BuildMI(newMBB, dl, TII->get(immOpcL), t5);
7448 if (regOpcL != X86::MOV32rr)
7450 (*MIB).addOperand(*argOpers[4]);
7451 assert(argOpers[5]->isReg() == argOpers[4]->isReg());
7452 assert(argOpers[5]->isImm() == argOpers[4]->isImm());
7453 if (argOpers[5]->isReg())
7454 MIB = BuildMI(newMBB, dl, TII->get(regOpcH), t6);
7456 MIB = BuildMI(newMBB, dl, TII->get(immOpcH), t6);
7457 if (regOpcH != X86::MOV32rr)
7459 (*MIB).addOperand(*argOpers[5]);
7461 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), X86::EAX);
7463 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), X86::EDX);
7466 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), X86::EBX);
7468 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), X86::ECX);
7471 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG8B));
7472 for (int i=0; i <= lastAddrIndx; ++i)
7473 (*MIB).addOperand(*argOpers[i]);
7475 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand");
7476 (*MIB).addMemOperand(*F, *bInstr->memoperands_begin());
7478 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), t3);
7479 MIB.addReg(X86::EAX);
7480 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), t4);
7481 MIB.addReg(X86::EDX);
7484 BuildMI(newMBB, dl, TII->get(X86::JNE)).addMBB(newMBB);
7486 F->DeleteMachineInstr(bInstr); // The pseudo instruction is gone now.
7490 // private utility function
7492 X86TargetLowering::EmitAtomicMinMaxWithCustomInserter(MachineInstr *mInstr,
7493 MachineBasicBlock *MBB,
7494 unsigned cmovOpc) const {
7495 // For the atomic min/max operator, we generate
7498 // ld t1 = [min/max.addr]
7499 // mov t2 = [min/max.val]
7501 // cmov[cond] t2 = t1
7503 // lcs dest = [bitinstr.addr], t2 [EAX is implicit]
7505 // fallthrough -->nextMBB
7507 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
7508 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
7509 MachineFunction::iterator MBBIter = MBB;
7512 /// First build the CFG
7513 MachineFunction *F = MBB->getParent();
7514 MachineBasicBlock *thisMBB = MBB;
7515 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
7516 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
7517 F->insert(MBBIter, newMBB);
7518 F->insert(MBBIter, nextMBB);
7520 // Move all successors to thisMBB to nextMBB
7521 nextMBB->transferSuccessors(thisMBB);
7523 // Update thisMBB to fall through to newMBB
7524 thisMBB->addSuccessor(newMBB);
7526 // newMBB jumps to newMBB and fall through to nextMBB
7527 newMBB->addSuccessor(nextMBB);
7528 newMBB->addSuccessor(newMBB);
7530 DebugLoc dl = mInstr->getDebugLoc();
7531 // Insert instructions into newMBB based on incoming instruction
7532 assert(mInstr->getNumOperands() < 8 && "unexpected number of operands");
7533 MachineOperand& destOper = mInstr->getOperand(0);
7534 MachineOperand* argOpers[6];
7535 int numArgs = mInstr->getNumOperands() - 1;
7536 for (int i=0; i < numArgs; ++i)
7537 argOpers[i] = &mInstr->getOperand(i+1);
7539 // x86 address has 4 operands: base, index, scale, and displacement
7540 int lastAddrIndx = 3; // [0,3]
7543 unsigned t1 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
7544 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rm), t1);
7545 for (int i=0; i <= lastAddrIndx; ++i)
7546 (*MIB).addOperand(*argOpers[i]);
7548 // We only support register and immediate values
7549 assert((argOpers[valArgIndx]->isReg() ||
7550 argOpers[valArgIndx]->isImm()) &&
7553 unsigned t2 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
7554 if (argOpers[valArgIndx]->isReg())
7555 MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), t2);
7557 MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), t2);
7558 (*MIB).addOperand(*argOpers[valArgIndx]);
7560 MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), X86::EAX);
7563 MIB = BuildMI(newMBB, dl, TII->get(X86::CMP32rr));
7568 unsigned t3 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
7569 MIB = BuildMI(newMBB, dl, TII->get(cmovOpc),t3);
7573 // Cmp and exchange if none has modified the memory location
7574 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG32));
7575 for (int i=0; i <= lastAddrIndx; ++i)
7576 (*MIB).addOperand(*argOpers[i]);
7578 assert(mInstr->hasOneMemOperand() && "Unexpected number of memoperand");
7579 (*MIB).addMemOperand(*F, *mInstr->memoperands_begin());
7581 MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), destOper.getReg());
7582 MIB.addReg(X86::EAX);
7585 BuildMI(newMBB, dl, TII->get(X86::JNE)).addMBB(newMBB);
7587 F->DeleteMachineInstr(mInstr); // The pseudo instruction is gone now.
7593 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
7594 MachineBasicBlock *BB) const {
7595 DebugLoc dl = MI->getDebugLoc();
7596 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
7597 switch (MI->getOpcode()) {
7598 default: assert(false && "Unexpected instr type to insert");
7599 case X86::CMOV_V1I64:
7600 case X86::CMOV_FR32:
7601 case X86::CMOV_FR64:
7602 case X86::CMOV_V4F32:
7603 case X86::CMOV_V2F64:
7604 case X86::CMOV_V2I64: {
7605 // To "insert" a SELECT_CC instruction, we actually have to insert the
7606 // diamond control-flow pattern. The incoming instruction knows the
7607 // destination vreg to set, the condition code register to branch on, the
7608 // true/false values to select between, and a branch opcode to use.
7609 const BasicBlock *LLVM_BB = BB->getBasicBlock();
7610 MachineFunction::iterator It = BB;
7616 // cmpTY ccX, r1, r2
7618 // fallthrough --> copy0MBB
7619 MachineBasicBlock *thisMBB = BB;
7620 MachineFunction *F = BB->getParent();
7621 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
7622 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
7624 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
7625 BuildMI(BB, dl, TII->get(Opc)).addMBB(sinkMBB);
7626 F->insert(It, copy0MBB);
7627 F->insert(It, sinkMBB);
7628 // Update machine-CFG edges by transferring all successors of the current
7629 // block to the new block which will contain the Phi node for the select.
7630 sinkMBB->transferSuccessors(BB);
7632 // Add the true and fallthrough blocks as its successors.
7633 BB->addSuccessor(copy0MBB);
7634 BB->addSuccessor(sinkMBB);
7637 // %FalseValue = ...
7638 // # fallthrough to sinkMBB
7641 // Update machine-CFG edges
7642 BB->addSuccessor(sinkMBB);
7645 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
7648 BuildMI(BB, dl, TII->get(X86::PHI), MI->getOperand(0).getReg())
7649 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
7650 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
7652 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
7656 case X86::FP32_TO_INT16_IN_MEM:
7657 case X86::FP32_TO_INT32_IN_MEM:
7658 case X86::FP32_TO_INT64_IN_MEM:
7659 case X86::FP64_TO_INT16_IN_MEM:
7660 case X86::FP64_TO_INT32_IN_MEM:
7661 case X86::FP64_TO_INT64_IN_MEM:
7662 case X86::FP80_TO_INT16_IN_MEM:
7663 case X86::FP80_TO_INT32_IN_MEM:
7664 case X86::FP80_TO_INT64_IN_MEM: {
7665 // Change the floating point control register to use "round towards zero"
7666 // mode when truncating to an integer value.
7667 MachineFunction *F = BB->getParent();
7668 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2);
7669 addFrameReference(BuildMI(BB, dl, TII->get(X86::FNSTCW16m)), CWFrameIdx);
7671 // Load the old value of the high byte of the control word...
7673 F->getRegInfo().createVirtualRegister(X86::GR16RegisterClass);
7674 addFrameReference(BuildMI(BB, dl, TII->get(X86::MOV16rm), OldCW),
7677 // Set the high part to be round to zero...
7678 addFrameReference(BuildMI(BB, dl, TII->get(X86::MOV16mi)), CWFrameIdx)
7681 // Reload the modified control word now...
7682 addFrameReference(BuildMI(BB, dl, TII->get(X86::FLDCW16m)), CWFrameIdx);
7684 // Restore the memory image of control word to original value
7685 addFrameReference(BuildMI(BB, dl, TII->get(X86::MOV16mr)), CWFrameIdx)
7688 // Get the X86 opcode to use.
7690 switch (MI->getOpcode()) {
7691 default: assert(0 && "illegal opcode!");
7692 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
7693 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
7694 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
7695 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
7696 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
7697 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
7698 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
7699 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
7700 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
7704 MachineOperand &Op = MI->getOperand(0);
7706 AM.BaseType = X86AddressMode::RegBase;
7707 AM.Base.Reg = Op.getReg();
7709 AM.BaseType = X86AddressMode::FrameIndexBase;
7710 AM.Base.FrameIndex = Op.getIndex();
7712 Op = MI->getOperand(1);
7714 AM.Scale = Op.getImm();
7715 Op = MI->getOperand(2);
7717 AM.IndexReg = Op.getImm();
7718 Op = MI->getOperand(3);
7719 if (Op.isGlobal()) {
7720 AM.GV = Op.getGlobal();
7722 AM.Disp = Op.getImm();
7724 addFullAddress(BuildMI(BB, dl, TII->get(Opc)), AM)
7725 .addReg(MI->getOperand(4).getReg());
7727 // Reload the original control word now.
7728 addFrameReference(BuildMI(BB, dl, TII->get(X86::FLDCW16m)), CWFrameIdx);
7730 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
7733 case X86::ATOMAND32:
7734 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr,
7735 X86::AND32ri, X86::MOV32rm,
7736 X86::LCMPXCHG32, X86::MOV32rr,
7737 X86::NOT32r, X86::EAX,
7738 X86::GR32RegisterClass);
7740 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR32rr,
7741 X86::OR32ri, X86::MOV32rm,
7742 X86::LCMPXCHG32, X86::MOV32rr,
7743 X86::NOT32r, X86::EAX,
7744 X86::GR32RegisterClass);
7745 case X86::ATOMXOR32:
7746 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR32rr,
7747 X86::XOR32ri, X86::MOV32rm,
7748 X86::LCMPXCHG32, X86::MOV32rr,
7749 X86::NOT32r, X86::EAX,
7750 X86::GR32RegisterClass);
7751 case X86::ATOMNAND32:
7752 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr,
7753 X86::AND32ri, X86::MOV32rm,
7754 X86::LCMPXCHG32, X86::MOV32rr,
7755 X86::NOT32r, X86::EAX,
7756 X86::GR32RegisterClass, true);
7757 case X86::ATOMMIN32:
7758 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL32rr);
7759 case X86::ATOMMAX32:
7760 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG32rr);
7761 case X86::ATOMUMIN32:
7762 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB32rr);
7763 case X86::ATOMUMAX32:
7764 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA32rr);
7766 case X86::ATOMAND16:
7767 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr,
7768 X86::AND16ri, X86::MOV16rm,
7769 X86::LCMPXCHG16, X86::MOV16rr,
7770 X86::NOT16r, X86::AX,
7771 X86::GR16RegisterClass);
7773 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR16rr,
7774 X86::OR16ri, X86::MOV16rm,
7775 X86::LCMPXCHG16, X86::MOV16rr,
7776 X86::NOT16r, X86::AX,
7777 X86::GR16RegisterClass);
7778 case X86::ATOMXOR16:
7779 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR16rr,
7780 X86::XOR16ri, X86::MOV16rm,
7781 X86::LCMPXCHG16, X86::MOV16rr,
7782 X86::NOT16r, X86::AX,
7783 X86::GR16RegisterClass);
7784 case X86::ATOMNAND16:
7785 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr,
7786 X86::AND16ri, X86::MOV16rm,
7787 X86::LCMPXCHG16, X86::MOV16rr,
7788 X86::NOT16r, X86::AX,
7789 X86::GR16RegisterClass, true);
7790 case X86::ATOMMIN16:
7791 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL16rr);
7792 case X86::ATOMMAX16:
7793 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG16rr);
7794 case X86::ATOMUMIN16:
7795 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB16rr);
7796 case X86::ATOMUMAX16:
7797 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA16rr);
7800 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr,
7801 X86::AND8ri, X86::MOV8rm,
7802 X86::LCMPXCHG8, X86::MOV8rr,
7803 X86::NOT8r, X86::AL,
7804 X86::GR8RegisterClass);
7806 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR8rr,
7807 X86::OR8ri, X86::MOV8rm,
7808 X86::LCMPXCHG8, X86::MOV8rr,
7809 X86::NOT8r, X86::AL,
7810 X86::GR8RegisterClass);
7812 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR8rr,
7813 X86::XOR8ri, X86::MOV8rm,
7814 X86::LCMPXCHG8, X86::MOV8rr,
7815 X86::NOT8r, X86::AL,
7816 X86::GR8RegisterClass);
7817 case X86::ATOMNAND8:
7818 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr,
7819 X86::AND8ri, X86::MOV8rm,
7820 X86::LCMPXCHG8, X86::MOV8rr,
7821 X86::NOT8r, X86::AL,
7822 X86::GR8RegisterClass, true);
7823 // FIXME: There are no CMOV8 instructions; MIN/MAX need some other way.
7824 // This group is for 64-bit host.
7825 case X86::ATOMAND64:
7826 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr,
7827 X86::AND64ri32, X86::MOV64rm,
7828 X86::LCMPXCHG64, X86::MOV64rr,
7829 X86::NOT64r, X86::RAX,
7830 X86::GR64RegisterClass);
7832 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR64rr,
7833 X86::OR64ri32, X86::MOV64rm,
7834 X86::LCMPXCHG64, X86::MOV64rr,
7835 X86::NOT64r, X86::RAX,
7836 X86::GR64RegisterClass);
7837 case X86::ATOMXOR64:
7838 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR64rr,
7839 X86::XOR64ri32, X86::MOV64rm,
7840 X86::LCMPXCHG64, X86::MOV64rr,
7841 X86::NOT64r, X86::RAX,
7842 X86::GR64RegisterClass);
7843 case X86::ATOMNAND64:
7844 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr,
7845 X86::AND64ri32, X86::MOV64rm,
7846 X86::LCMPXCHG64, X86::MOV64rr,
7847 X86::NOT64r, X86::RAX,
7848 X86::GR64RegisterClass, true);
7849 case X86::ATOMMIN64:
7850 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL64rr);
7851 case X86::ATOMMAX64:
7852 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG64rr);
7853 case X86::ATOMUMIN64:
7854 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB64rr);
7855 case X86::ATOMUMAX64:
7856 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA64rr);
7858 // This group does 64-bit operations on a 32-bit host.
7859 case X86::ATOMAND6432:
7860 return EmitAtomicBit6432WithCustomInserter(MI, BB,
7861 X86::AND32rr, X86::AND32rr,
7862 X86::AND32ri, X86::AND32ri,
7864 case X86::ATOMOR6432:
7865 return EmitAtomicBit6432WithCustomInserter(MI, BB,
7866 X86::OR32rr, X86::OR32rr,
7867 X86::OR32ri, X86::OR32ri,
7869 case X86::ATOMXOR6432:
7870 return EmitAtomicBit6432WithCustomInserter(MI, BB,
7871 X86::XOR32rr, X86::XOR32rr,
7872 X86::XOR32ri, X86::XOR32ri,
7874 case X86::ATOMNAND6432:
7875 return EmitAtomicBit6432WithCustomInserter(MI, BB,
7876 X86::AND32rr, X86::AND32rr,
7877 X86::AND32ri, X86::AND32ri,
7879 case X86::ATOMADD6432:
7880 return EmitAtomicBit6432WithCustomInserter(MI, BB,
7881 X86::ADD32rr, X86::ADC32rr,
7882 X86::ADD32ri, X86::ADC32ri,
7884 case X86::ATOMSUB6432:
7885 return EmitAtomicBit6432WithCustomInserter(MI, BB,
7886 X86::SUB32rr, X86::SBB32rr,
7887 X86::SUB32ri, X86::SBB32ri,
7889 case X86::ATOMSWAP6432:
7890 return EmitAtomicBit6432WithCustomInserter(MI, BB,
7891 X86::MOV32rr, X86::MOV32rr,
7892 X86::MOV32ri, X86::MOV32ri,
7897 //===----------------------------------------------------------------------===//
7898 // X86 Optimization Hooks
7899 //===----------------------------------------------------------------------===//
7901 void X86TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
7905 const SelectionDAG &DAG,
7906 unsigned Depth) const {
7907 unsigned Opc = Op.getOpcode();
7908 assert((Opc >= ISD::BUILTIN_OP_END ||
7909 Opc == ISD::INTRINSIC_WO_CHAIN ||
7910 Opc == ISD::INTRINSIC_W_CHAIN ||
7911 Opc == ISD::INTRINSIC_VOID) &&
7912 "Should use MaskedValueIsZero if you don't know whether Op"
7913 " is a target node!");
7915 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0); // Don't know anything.
7924 // These nodes' second result is a boolean.
7925 if (Op.getResNo() == 0)
7929 KnownZero |= APInt::getHighBitsSet(Mask.getBitWidth(),
7930 Mask.getBitWidth() - 1);
7935 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
7936 /// node is a GlobalAddress + offset.
7937 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
7938 GlobalValue* &GA, int64_t &Offset) const{
7939 if (N->getOpcode() == X86ISD::Wrapper) {
7940 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
7941 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
7942 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
7946 return TargetLowering::isGAPlusOffset(N, GA, Offset);
7949 static bool isBaseAlignmentOfN(unsigned N, SDNode *Base,
7950 const TargetLowering &TLI) {
7953 if (TLI.isGAPlusOffset(Base, GV, Offset))
7954 return (GV->getAlignment() >= N && (Offset % N) == 0);
7955 // DAG combine handles the stack object case.
7959 static bool EltsFromConsecutiveLoads(SDNode *N, SDValue PermMask,
7960 unsigned NumElems, MVT EVT,
7962 SelectionDAG &DAG, MachineFrameInfo *MFI,
7963 const TargetLowering &TLI) {
7965 for (unsigned i = 0; i < NumElems; ++i) {
7966 SDValue Idx = PermMask.getOperand(i);
7967 if (Idx.getOpcode() == ISD::UNDEF) {
7973 SDValue Elt = DAG.getShuffleScalarElt(N, i);
7974 if (!Elt.getNode() ||
7975 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
7978 Base = Elt.getNode();
7979 if (Base->getOpcode() == ISD::UNDEF)
7983 if (Elt.getOpcode() == ISD::UNDEF)
7986 if (!TLI.isConsecutiveLoad(Elt.getNode(), Base,
7987 EVT.getSizeInBits()/8, i, MFI))
7993 /// PerformShuffleCombine - Combine a vector_shuffle that is equal to
7994 /// build_vector load1, load2, load3, load4, <0, 1, 2, 3> into a 128-bit load
7995 /// if the load addresses are consecutive, non-overlapping, and in the right
7997 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
7998 const TargetLowering &TLI) {
7999 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
8000 DebugLoc dl = N->getDebugLoc();
8001 MVT VT = N->getValueType(0);
8002 MVT EVT = VT.getVectorElementType();
8003 SDValue PermMask = N->getOperand(2);
8004 unsigned NumElems = PermMask.getNumOperands();
8005 SDNode *Base = NULL;
8006 if (!EltsFromConsecutiveLoads(N, PermMask, NumElems, EVT, Base,
8010 LoadSDNode *LD = cast<LoadSDNode>(Base);
8011 if (isBaseAlignmentOfN(16, Base->getOperand(1).getNode(), TLI))
8012 return DAG.getLoad(VT, dl, LD->getChain(), LD->getBasePtr(),
8013 LD->getSrcValue(), LD->getSrcValueOffset(),
8015 return DAG.getLoad(VT, dl, LD->getChain(), LD->getBasePtr(),
8016 LD->getSrcValue(), LD->getSrcValueOffset(),
8017 LD->isVolatile(), LD->getAlignment());
8020 /// PerformBuildVectorCombine - build_vector 0,(load i64 / f64) -> movq / movsd.
8021 static SDValue PerformBuildVectorCombine(SDNode *N, SelectionDAG &DAG,
8022 TargetLowering::DAGCombinerInfo &DCI,
8023 const X86Subtarget *Subtarget,
8024 const TargetLowering &TLI) {
8025 unsigned NumOps = N->getNumOperands();
8026 DebugLoc dl = N->getDebugLoc();
8028 // Ignore single operand BUILD_VECTOR.
8032 MVT VT = N->getValueType(0);
8033 MVT EVT = VT.getVectorElementType();
8034 if ((EVT != MVT::i64 && EVT != MVT::f64) || Subtarget->is64Bit())
8035 // We are looking for load i64 and zero extend. We want to transform
8036 // it before legalizer has a chance to expand it. Also look for i64
8037 // BUILD_PAIR bit casted to f64.
8039 // This must be an insertion into a zero vector.
8040 SDValue HighElt = N->getOperand(1);
8041 if (!isZeroNode(HighElt))
8044 // Value must be a load.
8045 SDNode *Base = N->getOperand(0).getNode();
8046 if (!isa<LoadSDNode>(Base)) {
8047 if (Base->getOpcode() != ISD::BIT_CONVERT)
8049 Base = Base->getOperand(0).getNode();
8050 if (!isa<LoadSDNode>(Base))
8054 // Transform it into VZEXT_LOAD addr.
8055 LoadSDNode *LD = cast<LoadSDNode>(Base);
8057 // Load must not be an extload.
8058 if (LD->getExtensionType() != ISD::NON_EXTLOAD)
8061 // Load type should legal type so we don't have to legalize it.
8062 if (!TLI.isTypeLegal(VT))
8065 SDVTList Tys = DAG.getVTList(VT, MVT::Other);
8066 SDValue Ops[] = { LD->getChain(), LD->getBasePtr() };
8067 SDValue ResNode = DAG.getNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops, 2);
8068 TargetLowering::TargetLoweringOpt TLO(DAG);
8069 TLO.CombineTo(SDValue(Base, 1), ResNode.getValue(1));
8070 DCI.CommitTargetLoweringOpt(TLO);
8074 /// PerformSELECTCombine - Do target-specific dag combines on SELECT nodes.
8075 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
8076 const X86Subtarget *Subtarget) {
8077 DebugLoc dl = N->getDebugLoc();
8078 SDValue Cond = N->getOperand(0);
8080 // If we have SSE[12] support, try to form min/max nodes.
8081 if (Subtarget->hasSSE2() &&
8082 (N->getValueType(0) == MVT::f32 || N->getValueType(0) == MVT::f64)) {
8083 if (Cond.getOpcode() == ISD::SETCC) {
8084 // Get the LHS/RHS of the select.
8085 SDValue LHS = N->getOperand(1);
8086 SDValue RHS = N->getOperand(2);
8087 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
8089 unsigned Opcode = 0;
8090 if (LHS == Cond.getOperand(0) && RHS == Cond.getOperand(1)) {
8093 case ISD::SETOLE: // (X <= Y) ? X : Y -> min
8096 if (!UnsafeFPMath) break;
8098 case ISD::SETOLT: // (X olt/lt Y) ? X : Y -> min
8100 Opcode = X86ISD::FMIN;
8103 case ISD::SETOGT: // (X > Y) ? X : Y -> max
8106 if (!UnsafeFPMath) break;
8108 case ISD::SETUGE: // (X uge/ge Y) ? X : Y -> max
8110 Opcode = X86ISD::FMAX;
8113 } else if (LHS == Cond.getOperand(1) && RHS == Cond.getOperand(0)) {
8116 case ISD::SETOGT: // (X > Y) ? Y : X -> min
8119 if (!UnsafeFPMath) break;
8121 case ISD::SETUGE: // (X uge/ge Y) ? Y : X -> min
8123 Opcode = X86ISD::FMIN;
8126 case ISD::SETOLE: // (X <= Y) ? Y : X -> max
8129 if (!UnsafeFPMath) break;
8131 case ISD::SETOLT: // (X olt/lt Y) ? Y : X -> max
8133 Opcode = X86ISD::FMAX;
8139 return DAG.getNode(Opcode, dl, N->getValueType(0), LHS, RHS);
8147 /// PerformShiftCombine - Transforms vector shift nodes to use vector shifts
8149 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
8150 const X86Subtarget *Subtarget) {
8151 // On X86 with SSE2 support, we can transform this to a vector shift if
8152 // all elements are shifted by the same amount. We can't do this in legalize
8153 // because the a constant vector is typically transformed to a constant pool
8154 // so we have no knowledge of the shift amount.
8155 if (!Subtarget->hasSSE2())
8158 MVT VT = N->getValueType(0);
8159 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16)
8162 SDValue ShAmtOp = N->getOperand(1);
8163 MVT EltVT = VT.getVectorElementType();
8164 DebugLoc dl = N->getDebugLoc();
8166 if (ShAmtOp.getOpcode() == ISD::BUILD_VECTOR) {
8167 unsigned NumElts = VT.getVectorNumElements();
8169 for (; i != NumElts; ++i) {
8170 SDValue Arg = ShAmtOp.getOperand(i);
8171 if (Arg.getOpcode() == ISD::UNDEF) continue;
8175 for (; i != NumElts; ++i) {
8176 SDValue Arg = ShAmtOp.getOperand(i);
8177 if (Arg.getOpcode() == ISD::UNDEF) continue;
8178 if (Arg != BaseShAmt) {
8182 } else if (ShAmtOp.getOpcode() == ISD::VECTOR_SHUFFLE &&
8183 isSplatMask(ShAmtOp.getOperand(2).getNode())) {
8184 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, ShAmtOp,
8185 DAG.getIntPtrConstant(0));
8189 if (EltVT.bitsGT(MVT::i32))
8190 BaseShAmt = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, BaseShAmt);
8191 else if (EltVT.bitsLT(MVT::i32))
8192 BaseShAmt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, BaseShAmt);
8194 // The shift amount is identical so we can do a vector shift.
8195 SDValue ValOp = N->getOperand(0);
8196 switch (N->getOpcode()) {
8198 assert(0 && "Unknown shift opcode!");
8201 if (VT == MVT::v2i64)
8202 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
8203 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32),
8205 if (VT == MVT::v4i32)
8206 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
8207 DAG.getConstant(Intrinsic::x86_sse2_pslli_d, MVT::i32),
8209 if (VT == MVT::v8i16)
8210 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
8211 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32),
8215 if (VT == MVT::v4i32)
8216 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
8217 DAG.getConstant(Intrinsic::x86_sse2_psrai_d, MVT::i32),
8219 if (VT == MVT::v8i16)
8220 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
8221 DAG.getConstant(Intrinsic::x86_sse2_psrai_w, MVT::i32),
8225 if (VT == MVT::v2i64)
8226 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
8227 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32),
8229 if (VT == MVT::v4i32)
8230 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
8231 DAG.getConstant(Intrinsic::x86_sse2_psrli_d, MVT::i32),
8233 if (VT == MVT::v8i16)
8234 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
8235 DAG.getConstant(Intrinsic::x86_sse2_psrli_w, MVT::i32),
8242 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
8243 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
8244 const X86Subtarget *Subtarget) {
8245 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
8246 // the FP state in cases where an emms may be missing.
8247 // A preferable solution to the general problem is to figure out the right
8248 // places to insert EMMS. This qualifies as a quick hack.
8249 StoreSDNode *St = cast<StoreSDNode>(N);
8250 if (St->getValue().getValueType().isVector() &&
8251 St->getValue().getValueType().getSizeInBits() == 64 &&
8252 isa<LoadSDNode>(St->getValue()) &&
8253 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
8254 St->getChain().hasOneUse() && !St->isVolatile()) {
8255 SDNode* LdVal = St->getValue().getNode();
8257 int TokenFactorIndex = -1;
8258 SmallVector<SDValue, 8> Ops;
8259 SDNode* ChainVal = St->getChain().getNode();
8260 // Must be a store of a load. We currently handle two cases: the load
8261 // is a direct child, and it's under an intervening TokenFactor. It is
8262 // possible to dig deeper under nested TokenFactors.
8263 if (ChainVal == LdVal)
8264 Ld = cast<LoadSDNode>(St->getChain());
8265 else if (St->getValue().hasOneUse() &&
8266 ChainVal->getOpcode() == ISD::TokenFactor) {
8267 for (unsigned i=0, e = ChainVal->getNumOperands(); i != e; ++i) {
8268 if (ChainVal->getOperand(i).getNode() == LdVal) {
8269 TokenFactorIndex = i;
8270 Ld = cast<LoadSDNode>(St->getValue());
8272 Ops.push_back(ChainVal->getOperand(i));
8276 DebugLoc dl = N->getDebugLoc();
8277 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
8278 if (Subtarget->is64Bit()) {
8279 SDValue NewLd = DAG.getLoad(MVT::i64, dl, Ld->getChain(),
8280 Ld->getBasePtr(), Ld->getSrcValue(),
8281 Ld->getSrcValueOffset(), Ld->isVolatile(),
8282 Ld->getAlignment());
8283 SDValue NewChain = NewLd.getValue(1);
8284 if (TokenFactorIndex != -1) {
8285 Ops.push_back(NewChain);
8286 NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Ops[0],
8289 return DAG.getStore(NewChain, dl, NewLd, St->getBasePtr(),
8290 St->getSrcValue(), St->getSrcValueOffset(),
8291 St->isVolatile(), St->getAlignment());
8294 // Otherwise, lower to two 32-bit copies.
8295 SDValue LoAddr = Ld->getBasePtr();
8296 SDValue HiAddr = DAG.getNode(ISD::ADD, dl, MVT::i32, LoAddr,
8297 DAG.getConstant(4, MVT::i32));
8299 SDValue LoLd = DAG.getLoad(MVT::i32, dl, Ld->getChain(), LoAddr,
8300 Ld->getSrcValue(), Ld->getSrcValueOffset(),
8301 Ld->isVolatile(), Ld->getAlignment());
8302 SDValue HiLd = DAG.getLoad(MVT::i32, dl, Ld->getChain(), HiAddr,
8303 Ld->getSrcValue(), Ld->getSrcValueOffset()+4,
8305 MinAlign(Ld->getAlignment(), 4));
8307 SDValue NewChain = LoLd.getValue(1);
8308 if (TokenFactorIndex != -1) {
8309 Ops.push_back(LoLd);
8310 Ops.push_back(HiLd);
8311 NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Ops[0],
8315 LoAddr = St->getBasePtr();
8316 HiAddr = DAG.getNode(ISD::ADD, dl, MVT::i32, LoAddr,
8317 DAG.getConstant(4, MVT::i32));
8319 SDValue LoSt = DAG.getStore(NewChain, dl, LoLd, LoAddr,
8320 St->getSrcValue(), St->getSrcValueOffset(),
8321 St->isVolatile(), St->getAlignment());
8322 SDValue HiSt = DAG.getStore(NewChain, dl, HiLd, HiAddr,
8324 St->getSrcValueOffset() + 4,
8326 MinAlign(St->getAlignment(), 4));
8327 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, LoSt, HiSt);
8333 /// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and
8334 /// X86ISD::FXOR nodes.
8335 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
8336 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
8337 // F[X]OR(0.0, x) -> x
8338 // F[X]OR(x, 0.0) -> x
8339 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
8340 if (C->getValueAPF().isPosZero())
8341 return N->getOperand(1);
8342 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
8343 if (C->getValueAPF().isPosZero())
8344 return N->getOperand(0);
8348 /// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes.
8349 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
8350 // FAND(0.0, x) -> 0.0
8351 // FAND(x, 0.0) -> 0.0
8352 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
8353 if (C->getValueAPF().isPosZero())
8354 return N->getOperand(0);
8355 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
8356 if (C->getValueAPF().isPosZero())
8357 return N->getOperand(1);
8361 static SDValue PerformBTCombine(SDNode *N,
8363 TargetLowering::DAGCombinerInfo &DCI) {
8364 // BT ignores high bits in the bit index operand.
8365 SDValue Op1 = N->getOperand(1);
8366 if (Op1.hasOneUse()) {
8367 unsigned BitWidth = Op1.getValueSizeInBits();
8368 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
8369 APInt KnownZero, KnownOne;
8370 TargetLowering::TargetLoweringOpt TLO(DAG);
8371 TargetLowering &TLI = DAG.getTargetLoweringInfo();
8372 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
8373 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
8374 DCI.CommitTargetLoweringOpt(TLO);
8379 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
8380 DAGCombinerInfo &DCI) const {
8381 SelectionDAG &DAG = DCI.DAG;
8382 switch (N->getOpcode()) {
8384 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, *this);
8385 case ISD::BUILD_VECTOR:
8386 return PerformBuildVectorCombine(N, DAG, DCI, Subtarget, *this);
8387 case ISD::SELECT: return PerformSELECTCombine(N, DAG, Subtarget);
8390 case ISD::SRL: return PerformShiftCombine(N, DAG, Subtarget);
8391 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
8393 case X86ISD::FOR: return PerformFORCombine(N, DAG);
8394 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
8395 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
8401 //===----------------------------------------------------------------------===//
8402 // X86 Inline Assembly Support
8403 //===----------------------------------------------------------------------===//
8405 /// getConstraintType - Given a constraint letter, return the type of
8406 /// constraint it is for this target.
8407 X86TargetLowering::ConstraintType
8408 X86TargetLowering::getConstraintType(const std::string &Constraint) const {
8409 if (Constraint.size() == 1) {
8410 switch (Constraint[0]) {
8422 return C_RegisterClass;
8430 return TargetLowering::getConstraintType(Constraint);
8433 /// LowerXConstraint - try to replace an X constraint, which matches anything,
8434 /// with another that has more specific requirements based on the type of the
8435 /// corresponding operand.
8436 const char *X86TargetLowering::
8437 LowerXConstraint(MVT ConstraintVT) const {
8438 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
8439 // 'f' like normal targets.
8440 if (ConstraintVT.isFloatingPoint()) {
8441 if (Subtarget->hasSSE2())
8443 if (Subtarget->hasSSE1())
8447 return TargetLowering::LowerXConstraint(ConstraintVT);
8450 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
8451 /// vector. If it is invalid, don't add anything to Ops.
8452 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
8455 std::vector<SDValue>&Ops,
8456 SelectionDAG &DAG) const {
8457 SDValue Result(0, 0);
8459 switch (Constraint) {
8462 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
8463 if (C->getZExtValue() <= 31) {
8464 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
8470 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
8471 if (C->getZExtValue() <= 63) {
8472 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
8478 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
8479 if (C->getZExtValue() <= 255) {
8480 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
8486 // 32-bit signed value
8487 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
8488 const ConstantInt *CI = C->getConstantIntValue();
8489 if (CI->isValueValidForType(Type::Int32Ty, C->getSExtValue())) {
8490 // Widen to 64 bits here to get it sign extended.
8491 Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64);
8494 // FIXME gcc accepts some relocatable values here too, but only in certain
8495 // memory models; it's complicated.
8500 // 32-bit unsigned value
8501 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
8502 const ConstantInt *CI = C->getConstantIntValue();
8503 if (CI->isValueValidForType(Type::Int32Ty, C->getZExtValue())) {
8504 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
8508 // FIXME gcc accepts some relocatable values here too, but only in certain
8509 // memory models; it's complicated.
8513 // Literal immediates are always ok.
8514 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
8515 // Widen to 64 bits here to get it sign extended.
8516 Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64);
8520 // If we are in non-pic codegen mode, we allow the address of a global (with
8521 // an optional displacement) to be used with 'i'.
8522 GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Op);
8525 // Match either (GA) or (GA+C)
8527 Offset = GA->getOffset();
8528 } else if (Op.getOpcode() == ISD::ADD) {
8529 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
8530 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(0));
8532 Offset = GA->getOffset()+C->getZExtValue();
8534 C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
8535 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(0));
8537 Offset = GA->getOffset()+C->getZExtValue();
8545 Op = LowerGlobalAddress(GA->getGlobal(), Op.getDebugLoc(),
8548 Op = DAG.getTargetGlobalAddress(GA->getGlobal(), GA->getValueType(0),
8554 // Otherwise, not valid for this mode.
8559 if (Result.getNode()) {
8560 Ops.push_back(Result);
8563 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, hasMemory,
8567 std::vector<unsigned> X86TargetLowering::
8568 getRegClassForInlineAsmConstraint(const std::string &Constraint,
8570 if (Constraint.size() == 1) {
8571 // FIXME: not handling fp-stack yet!
8572 switch (Constraint[0]) { // GCC X86 Constraint Letters
8573 default: break; // Unknown constraint letter
8574 case 'q': // Q_REGS (GENERAL_REGS in 64-bit mode)
8577 return make_vector<unsigned>(X86::EAX, X86::EDX, X86::ECX, X86::EBX, 0);
8578 else if (VT == MVT::i16)
8579 return make_vector<unsigned>(X86::AX, X86::DX, X86::CX, X86::BX, 0);
8580 else if (VT == MVT::i8)
8581 return make_vector<unsigned>(X86::AL, X86::DL, X86::CL, X86::BL, 0);
8582 else if (VT == MVT::i64)
8583 return make_vector<unsigned>(X86::RAX, X86::RDX, X86::RCX, X86::RBX, 0);
8588 return std::vector<unsigned>();
8591 std::pair<unsigned, const TargetRegisterClass*>
8592 X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
8594 // First, see if this is a constraint that directly corresponds to an LLVM
8596 if (Constraint.size() == 1) {
8597 // GCC Constraint Letters
8598 switch (Constraint[0]) {
8600 case 'r': // GENERAL_REGS
8601 case 'R': // LEGACY_REGS
8602 case 'l': // INDEX_REGS
8604 return std::make_pair(0U, X86::GR8RegisterClass);
8606 return std::make_pair(0U, X86::GR16RegisterClass);
8607 if (VT == MVT::i32 || !Subtarget->is64Bit())
8608 return std::make_pair(0U, X86::GR32RegisterClass);
8609 return std::make_pair(0U, X86::GR64RegisterClass);
8610 case 'f': // FP Stack registers.
8611 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
8612 // value to the correct fpstack register class.
8613 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
8614 return std::make_pair(0U, X86::RFP32RegisterClass);
8615 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
8616 return std::make_pair(0U, X86::RFP64RegisterClass);
8617 return std::make_pair(0U, X86::RFP80RegisterClass);
8618 case 'y': // MMX_REGS if MMX allowed.
8619 if (!Subtarget->hasMMX()) break;
8620 return std::make_pair(0U, X86::VR64RegisterClass);
8621 case 'Y': // SSE_REGS if SSE2 allowed
8622 if (!Subtarget->hasSSE2()) break;
8624 case 'x': // SSE_REGS if SSE1 allowed
8625 if (!Subtarget->hasSSE1()) break;
8627 switch (VT.getSimpleVT()) {
8629 // Scalar SSE types.
8632 return std::make_pair(0U, X86::FR32RegisterClass);
8635 return std::make_pair(0U, X86::FR64RegisterClass);
8643 return std::make_pair(0U, X86::VR128RegisterClass);
8649 // Use the default implementation in TargetLowering to convert the register
8650 // constraint into a member of a register class.
8651 std::pair<unsigned, const TargetRegisterClass*> Res;
8652 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
8654 // Not found as a standard register?
8655 if (Res.second == 0) {
8656 // GCC calls "st(0)" just plain "st".
8657 if (StringsEqualNoCase("{st}", Constraint)) {
8658 Res.first = X86::ST0;
8659 Res.second = X86::RFP80RegisterClass;
8661 // 'A' means EAX + EDX.
8662 if (Constraint == "A") {
8663 Res.first = X86::EAX;
8664 Res.second = X86::GRADRegisterClass;
8669 // Otherwise, check to see if this is a register class of the wrong value
8670 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
8671 // turn into {ax},{dx}.
8672 if (Res.second->hasType(VT))
8673 return Res; // Correct type already, nothing to do.
8675 // All of the single-register GCC register classes map their values onto
8676 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
8677 // really want an 8-bit or 32-bit register, map to the appropriate register
8678 // class and return the appropriate register.
8679 if (Res.second == X86::GR16RegisterClass) {
8680 if (VT == MVT::i8) {
8681 unsigned DestReg = 0;
8682 switch (Res.first) {
8684 case X86::AX: DestReg = X86::AL; break;
8685 case X86::DX: DestReg = X86::DL; break;
8686 case X86::CX: DestReg = X86::CL; break;
8687 case X86::BX: DestReg = X86::BL; break;
8690 Res.first = DestReg;
8691 Res.second = Res.second = X86::GR8RegisterClass;
8693 } else if (VT == MVT::i32) {
8694 unsigned DestReg = 0;
8695 switch (Res.first) {
8697 case X86::AX: DestReg = X86::EAX; break;
8698 case X86::DX: DestReg = X86::EDX; break;
8699 case X86::CX: DestReg = X86::ECX; break;
8700 case X86::BX: DestReg = X86::EBX; break;
8701 case X86::SI: DestReg = X86::ESI; break;
8702 case X86::DI: DestReg = X86::EDI; break;
8703 case X86::BP: DestReg = X86::EBP; break;
8704 case X86::SP: DestReg = X86::ESP; break;
8707 Res.first = DestReg;
8708 Res.second = Res.second = X86::GR32RegisterClass;
8710 } else if (VT == MVT::i64) {
8711 unsigned DestReg = 0;
8712 switch (Res.first) {
8714 case X86::AX: DestReg = X86::RAX; break;
8715 case X86::DX: DestReg = X86::RDX; break;
8716 case X86::CX: DestReg = X86::RCX; break;
8717 case X86::BX: DestReg = X86::RBX; break;
8718 case X86::SI: DestReg = X86::RSI; break;
8719 case X86::DI: DestReg = X86::RDI; break;
8720 case X86::BP: DestReg = X86::RBP; break;
8721 case X86::SP: DestReg = X86::RSP; break;
8724 Res.first = DestReg;
8725 Res.second = Res.second = X86::GR64RegisterClass;
8728 } else if (Res.second == X86::FR32RegisterClass ||
8729 Res.second == X86::FR64RegisterClass ||
8730 Res.second == X86::VR128RegisterClass) {
8731 // Handle references to XMM physical registers that got mapped into the
8732 // wrong class. This can happen with constraints like {xmm0} where the
8733 // target independent register mapper will just pick the first match it can
8734 // find, ignoring the required type.
8736 Res.second = X86::FR32RegisterClass;
8737 else if (VT == MVT::f64)
8738 Res.second = X86::FR64RegisterClass;
8739 else if (X86::VR128RegisterClass->hasType(VT))
8740 Res.second = X86::VR128RegisterClass;
8746 //===----------------------------------------------------------------------===//
8747 // X86 Widen vector type
8748 //===----------------------------------------------------------------------===//
8750 /// getWidenVectorType: given a vector type, returns the type to widen
8751 /// to (e.g., v7i8 to v8i8). If the vector type is legal, it returns itself.
8752 /// If there is no vector type that we want to widen to, returns MVT::Other
8753 /// When and where to widen is target dependent based on the cost of
8754 /// scalarizing vs using the wider vector type.
8756 MVT X86TargetLowering::getWidenVectorType(MVT VT) const {
8757 assert(VT.isVector());
8758 if (isTypeLegal(VT))
8761 // TODO: In computeRegisterProperty, we can compute the list of legal vector
8762 // type based on element type. This would speed up our search (though
8763 // it may not be worth it since the size of the list is relatively
8765 MVT EltVT = VT.getVectorElementType();
8766 unsigned NElts = VT.getVectorNumElements();
8768 // On X86, it make sense to widen any vector wider than 1
8772 for (unsigned nVT = MVT::FIRST_VECTOR_VALUETYPE;
8773 nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) {
8774 MVT SVT = (MVT::SimpleValueType)nVT;
8776 if (isTypeLegal(SVT) &&
8777 SVT.getVectorElementType() == EltVT &&
8778 SVT.getVectorNumElements() > NElts)