1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #include "X86ISelLowering.h"
16 #include "Utils/X86ShuffleDecode.h"
17 #include "X86CallingConv.h"
18 #include "X86FrameLowering.h"
19 #include "X86InstrBuilder.h"
20 #include "X86MachineFunctionInfo.h"
21 #include "X86TargetMachine.h"
22 #include "X86TargetObjectFile.h"
23 #include "llvm/ADT/SmallBitVector.h"
24 #include "llvm/ADT/SmallSet.h"
25 #include "llvm/ADT/Statistic.h"
26 #include "llvm/ADT/StringExtras.h"
27 #include "llvm/ADT/StringSwitch.h"
28 #include "llvm/Analysis/EHPersonalities.h"
29 #include "llvm/CodeGen/IntrinsicLowering.h"
30 #include "llvm/CodeGen/MachineFrameInfo.h"
31 #include "llvm/CodeGen/MachineFunction.h"
32 #include "llvm/CodeGen/MachineInstrBuilder.h"
33 #include "llvm/CodeGen/MachineJumpTableInfo.h"
34 #include "llvm/CodeGen/MachineModuleInfo.h"
35 #include "llvm/CodeGen/MachineRegisterInfo.h"
36 #include "llvm/CodeGen/WinEHFuncInfo.h"
37 #include "llvm/IR/CallSite.h"
38 #include "llvm/IR/CallingConv.h"
39 #include "llvm/IR/Constants.h"
40 #include "llvm/IR/DerivedTypes.h"
41 #include "llvm/IR/Function.h"
42 #include "llvm/IR/GlobalAlias.h"
43 #include "llvm/IR/GlobalVariable.h"
44 #include "llvm/IR/Instructions.h"
45 #include "llvm/IR/Intrinsics.h"
46 #include "llvm/MC/MCAsmInfo.h"
47 #include "llvm/MC/MCContext.h"
48 #include "llvm/MC/MCExpr.h"
49 #include "llvm/MC/MCSymbol.h"
50 #include "llvm/Support/CommandLine.h"
51 #include "llvm/Support/Debug.h"
52 #include "llvm/Support/ErrorHandling.h"
53 #include "llvm/Support/MathExtras.h"
54 #include "llvm/Target/TargetOptions.h"
55 #include "X86IntrinsicsInfo.h"
61 #define DEBUG_TYPE "x86-isel"
63 STATISTIC(NumTailCalls, "Number of tail calls");
65 static cl::opt<bool> ExperimentalVectorWideningLegalization(
66 "x86-experimental-vector-widening-legalization", cl::init(false),
67 cl::desc("Enable an experimental vector type legalization through widening "
68 "rather than promotion."),
71 X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
72 const X86Subtarget &STI)
73 : TargetLowering(TM), Subtarget(&STI) {
74 X86ScalarSSEf64 = Subtarget->hasSSE2();
75 X86ScalarSSEf32 = Subtarget->hasSSE1();
76 MVT PtrVT = MVT::getIntegerVT(8 * TM.getPointerSize());
78 // Set up the TargetLowering object.
80 // X86 is weird. It always uses i8 for shift amounts and setcc results.
81 setBooleanContents(ZeroOrOneBooleanContent);
82 // X86-SSE is even stranger. It uses -1 or 0 for vector masks.
83 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
85 // For 64-bit, since we have so many registers, use the ILP scheduler.
86 // For 32-bit, use the register pressure specific scheduling.
87 // For Atom, always use ILP scheduling.
88 if (Subtarget->isAtom())
89 setSchedulingPreference(Sched::ILP);
90 else if (Subtarget->is64Bit())
91 setSchedulingPreference(Sched::ILP);
93 setSchedulingPreference(Sched::RegPressure);
94 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
95 setStackPointerRegisterToSaveRestore(RegInfo->getStackRegister());
97 // Bypass expensive divides on Atom when compiling with O2.
98 if (TM.getOptLevel() >= CodeGenOpt::Default) {
99 if (Subtarget->hasSlowDivide32())
100 addBypassSlowDiv(32, 8);
101 if (Subtarget->hasSlowDivide64() && Subtarget->is64Bit())
102 addBypassSlowDiv(64, 16);
105 if (Subtarget->isTargetKnownWindowsMSVC()) {
106 // Setup Windows compiler runtime calls.
107 setLibcallName(RTLIB::SDIV_I64, "_alldiv");
108 setLibcallName(RTLIB::UDIV_I64, "_aulldiv");
109 setLibcallName(RTLIB::SREM_I64, "_allrem");
110 setLibcallName(RTLIB::UREM_I64, "_aullrem");
111 setLibcallName(RTLIB::MUL_I64, "_allmul");
112 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall);
113 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall);
114 setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::X86_StdCall);
115 setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::X86_StdCall);
116 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::X86_StdCall);
119 if (Subtarget->isTargetDarwin()) {
120 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
121 setUseUnderscoreSetJmp(false);
122 setUseUnderscoreLongJmp(false);
123 } else if (Subtarget->isTargetWindowsGNU()) {
124 // MS runtime is weird: it exports _setjmp, but longjmp!
125 setUseUnderscoreSetJmp(true);
126 setUseUnderscoreLongJmp(false);
128 setUseUnderscoreSetJmp(true);
129 setUseUnderscoreLongJmp(true);
132 // Set up the register classes.
133 addRegisterClass(MVT::i8, &X86::GR8RegClass);
134 addRegisterClass(MVT::i16, &X86::GR16RegClass);
135 addRegisterClass(MVT::i32, &X86::GR32RegClass);
136 if (Subtarget->is64Bit())
137 addRegisterClass(MVT::i64, &X86::GR64RegClass);
139 for (MVT VT : MVT::integer_valuetypes())
140 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
142 // We don't accept any truncstore of integer registers.
143 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
144 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
145 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
146 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
147 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
148 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
150 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
152 // SETOEQ and SETUNE require checking two conditions.
153 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
154 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
155 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
156 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
157 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
158 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
160 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
162 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
163 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
164 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
166 if (Subtarget->is64Bit()) {
167 if (!Subtarget->useSoftFloat() && Subtarget->hasAVX512())
168 // f32/f64 are legal, f80 is custom.
169 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
171 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
172 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
173 } else if (!Subtarget->useSoftFloat()) {
174 // We have an algorithm for SSE2->double, and we turn this into a
175 // 64-bit FILD followed by conditional FADD for other targets.
176 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
177 // We have an algorithm for SSE2, and we turn this into a 64-bit
178 // FILD or VCVTUSI2SS/SD for other targets.
179 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
182 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
184 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
185 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
187 if (!Subtarget->useSoftFloat()) {
188 // SSE has no i16 to fp conversion, only i32
189 if (X86ScalarSSEf32) {
190 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
191 // f32 and f64 cases are Legal, f80 case is not
192 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
194 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
195 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
198 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
199 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
202 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
204 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
205 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
207 if (!Subtarget->useSoftFloat()) {
208 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
209 // are Legal, f80 is custom lowered.
210 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
211 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
213 if (X86ScalarSSEf32) {
214 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
215 // f32 and f64 cases are Legal, f80 case is not
216 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
218 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
219 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
222 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
223 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Expand);
224 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Expand);
227 // Handle FP_TO_UINT by promoting the destination to a larger signed
229 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
230 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
231 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
233 if (Subtarget->is64Bit()) {
234 if (!Subtarget->useSoftFloat() && Subtarget->hasAVX512()) {
235 // FP_TO_UINT-i32/i64 is legal for f32/f64, but custom for f80.
236 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
237 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Custom);
239 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
240 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
242 } else if (!Subtarget->useSoftFloat()) {
243 // Since AVX is a superset of SSE3, only check for SSE here.
244 if (Subtarget->hasSSE1() && !Subtarget->hasSSE3())
245 // Expand FP_TO_UINT into a select.
246 // FIXME: We would like to use a Custom expander here eventually to do
247 // the optimal thing for SSE vs. the default expansion in the legalizer.
248 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
250 // With AVX512 we can use vcvts[ds]2usi for f32/f64->i32, f80 is custom.
251 // With SSE3 we can use fisttpll to convert to a signed i64; without
252 // SSE, we're stuck with a fistpll.
253 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
255 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Custom);
258 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
259 if (!X86ScalarSSEf64) {
260 setOperationAction(ISD::BITCAST , MVT::f32 , Expand);
261 setOperationAction(ISD::BITCAST , MVT::i32 , Expand);
262 if (Subtarget->is64Bit()) {
263 setOperationAction(ISD::BITCAST , MVT::f64 , Expand);
264 // Without SSE, i64->f64 goes through memory.
265 setOperationAction(ISD::BITCAST , MVT::i64 , Expand);
269 // Scalar integer divide and remainder are lowered to use operations that
270 // produce two results, to match the available instructions. This exposes
271 // the two-result form to trivial CSE, which is able to combine x/y and x%y
272 // into a single instruction.
274 // Scalar integer multiply-high is also lowered to use two-result
275 // operations, to match the available instructions. However, plain multiply
276 // (low) operations are left as Legal, as there are single-result
277 // instructions for this in x86. Using the two-result multiply instructions
278 // when both high and low results are needed must be arranged by dagcombine.
279 for (auto VT : { MVT::i8, MVT::i16, MVT::i32, MVT::i64 }) {
280 setOperationAction(ISD::MULHS, VT, Expand);
281 setOperationAction(ISD::MULHU, VT, Expand);
282 setOperationAction(ISD::SDIV, VT, Expand);
283 setOperationAction(ISD::UDIV, VT, Expand);
284 setOperationAction(ISD::SREM, VT, Expand);
285 setOperationAction(ISD::UREM, VT, Expand);
287 // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences.
288 setOperationAction(ISD::ADDC, VT, Custom);
289 setOperationAction(ISD::ADDE, VT, Custom);
290 setOperationAction(ISD::SUBC, VT, Custom);
291 setOperationAction(ISD::SUBE, VT, Custom);
294 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
295 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
296 setOperationAction(ISD::BR_CC , MVT::f32, Expand);
297 setOperationAction(ISD::BR_CC , MVT::f64, Expand);
298 setOperationAction(ISD::BR_CC , MVT::f80, Expand);
299 setOperationAction(ISD::BR_CC , MVT::i8, Expand);
300 setOperationAction(ISD::BR_CC , MVT::i16, Expand);
301 setOperationAction(ISD::BR_CC , MVT::i32, Expand);
302 setOperationAction(ISD::BR_CC , MVT::i64, Expand);
303 setOperationAction(ISD::SELECT_CC , MVT::f32, Expand);
304 setOperationAction(ISD::SELECT_CC , MVT::f64, Expand);
305 setOperationAction(ISD::SELECT_CC , MVT::f80, Expand);
306 setOperationAction(ISD::SELECT_CC , MVT::i8, Expand);
307 setOperationAction(ISD::SELECT_CC , MVT::i16, Expand);
308 setOperationAction(ISD::SELECT_CC , MVT::i32, Expand);
309 setOperationAction(ISD::SELECT_CC , MVT::i64, Expand);
310 if (Subtarget->is64Bit())
311 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
312 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
313 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
314 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
315 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
317 if (Subtarget->is32Bit() && Subtarget->isTargetKnownWindowsMSVC()) {
318 // On 32 bit MSVC, `fmodf(f32)` is not defined - only `fmod(f64)`
319 // is. We should promote the value to 64-bits to solve this.
320 // This is what the CRT headers do - `fmodf` is an inline header
321 // function casting to f64 and calling `fmod`.
322 setOperationAction(ISD::FREM , MVT::f32 , Promote);
324 setOperationAction(ISD::FREM , MVT::f32 , Expand);
327 setOperationAction(ISD::FREM , MVT::f64 , Expand);
328 setOperationAction(ISD::FREM , MVT::f80 , Expand);
329 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
331 // Promote the i8 variants and force them on up to i32 which has a shorter
333 setOperationAction(ISD::CTTZ , MVT::i8 , Promote);
334 AddPromotedToType (ISD::CTTZ , MVT::i8 , MVT::i32);
335 setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i8 , Promote);
336 AddPromotedToType (ISD::CTTZ_ZERO_UNDEF , MVT::i8 , MVT::i32);
337 if (Subtarget->hasBMI()) {
338 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16 , Expand);
339 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32 , Expand);
340 if (Subtarget->is64Bit())
341 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
343 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
344 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
345 if (Subtarget->is64Bit())
346 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
349 if (Subtarget->hasLZCNT()) {
350 // When promoting the i8 variants, force them to i32 for a shorter
352 setOperationAction(ISD::CTLZ , MVT::i8 , Promote);
353 AddPromotedToType (ISD::CTLZ , MVT::i8 , MVT::i32);
354 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Promote);
355 AddPromotedToType (ISD::CTLZ_ZERO_UNDEF, MVT::i8 , MVT::i32);
356 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Expand);
357 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Expand);
358 if (Subtarget->is64Bit())
359 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
361 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
362 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
363 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
364 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Custom);
365 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Custom);
366 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Custom);
367 if (Subtarget->is64Bit()) {
368 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
369 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom);
373 // Special handling for half-precision floating point conversions.
374 // If we don't have F16C support, then lower half float conversions
375 // into library calls.
376 if (Subtarget->useSoftFloat() || !Subtarget->hasF16C()) {
377 setOperationAction(ISD::FP16_TO_FP, MVT::f32, Expand);
378 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand);
381 // There's never any support for operations beyond MVT::f32.
382 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand);
383 setOperationAction(ISD::FP16_TO_FP, MVT::f80, Expand);
384 setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand);
385 setOperationAction(ISD::FP_TO_FP16, MVT::f80, Expand);
387 setLoadExtAction(ISD::EXTLOAD, MVT::f32, MVT::f16, Expand);
388 setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f16, Expand);
389 setLoadExtAction(ISD::EXTLOAD, MVT::f80, MVT::f16, Expand);
390 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
391 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
392 setTruncStoreAction(MVT::f80, MVT::f16, Expand);
394 if (Subtarget->hasPOPCNT()) {
395 setOperationAction(ISD::CTPOP , MVT::i8 , Promote);
397 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
398 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
399 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
400 if (Subtarget->is64Bit())
401 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
404 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
406 if (!Subtarget->hasMOVBE())
407 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
409 // These should be promoted to a larger select which is supported.
410 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
411 // X86 wants to expand cmov itself.
412 setOperationAction(ISD::SELECT , MVT::i8 , Custom);
413 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
414 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
415 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
416 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
417 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
418 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
419 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
420 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
421 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
422 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
423 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
424 setOperationAction(ISD::SETCCE , MVT::i8 , Custom);
425 setOperationAction(ISD::SETCCE , MVT::i16 , Custom);
426 setOperationAction(ISD::SETCCE , MVT::i32 , Custom);
427 if (Subtarget->is64Bit()) {
428 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
429 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
430 setOperationAction(ISD::SETCCE , MVT::i64 , Custom);
432 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
433 // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support
434 // SjLj exception handling but a light-weight setjmp/longjmp replacement to
435 // support continuation, user-level threading, and etc.. As a result, no
436 // other SjLj exception interfaces are implemented and please don't build
437 // your own exception handling based on them.
438 // LLVM/Clang supports zero-cost DWARF exception handling.
439 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
440 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
443 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
444 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
445 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
446 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
447 if (Subtarget->is64Bit())
448 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
449 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
450 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom);
451 if (Subtarget->is64Bit()) {
452 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
453 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
454 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
455 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
456 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom);
458 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
459 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
460 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
461 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
462 if (Subtarget->is64Bit()) {
463 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
464 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
465 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
468 if (Subtarget->hasSSE1())
469 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
471 setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom);
473 // Expand certain atomics
474 for (auto VT : { MVT::i8, MVT::i16, MVT::i32, MVT::i64 }) {
475 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, VT, Custom);
476 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom);
477 setOperationAction(ISD::ATOMIC_STORE, VT, Custom);
480 if (Subtarget->hasCmpxchg16b()) {
481 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, MVT::i128, Custom);
484 // FIXME - use subtarget debug flags
485 if (!Subtarget->isTargetDarwin() && !Subtarget->isTargetELF() &&
486 !Subtarget->isTargetCygMing() && !Subtarget->isTargetWin64()) {
487 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
490 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
491 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
493 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
494 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
496 setOperationAction(ISD::TRAP, MVT::Other, Legal);
497 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Legal);
499 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
500 setOperationAction(ISD::VASTART , MVT::Other, Custom);
501 setOperationAction(ISD::VAEND , MVT::Other, Expand);
502 if (Subtarget->is64Bit()) {
503 setOperationAction(ISD::VAARG , MVT::Other, Custom);
504 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
506 // TargetInfo::CharPtrBuiltinVaList
507 setOperationAction(ISD::VAARG , MVT::Other, Expand);
508 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
511 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
512 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
514 setOperationAction(ISD::DYNAMIC_STACKALLOC, PtrVT, Custom);
516 // GC_TRANSITION_START and GC_TRANSITION_END need custom lowering.
517 setOperationAction(ISD::GC_TRANSITION_START, MVT::Other, Custom);
518 setOperationAction(ISD::GC_TRANSITION_END, MVT::Other, Custom);
520 if (!Subtarget->useSoftFloat() && X86ScalarSSEf64) {
521 // f32 and f64 use SSE.
522 // Set up the FP register classes.
523 addRegisterClass(MVT::f32, &X86::FR32RegClass);
524 addRegisterClass(MVT::f64, &X86::FR64RegClass);
526 // Use ANDPD to simulate FABS.
527 setOperationAction(ISD::FABS , MVT::f64, Custom);
528 setOperationAction(ISD::FABS , MVT::f32, Custom);
530 // Use XORP to simulate FNEG.
531 setOperationAction(ISD::FNEG , MVT::f64, Custom);
532 setOperationAction(ISD::FNEG , MVT::f32, Custom);
534 // Use ANDPD and ORPD to simulate FCOPYSIGN.
535 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
536 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
538 // Lower this to FGETSIGNx86 plus an AND.
539 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom);
540 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom);
542 // We don't support sin/cos/fmod
543 setOperationAction(ISD::FSIN , MVT::f64, Expand);
544 setOperationAction(ISD::FCOS , MVT::f64, Expand);
545 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
546 setOperationAction(ISD::FSIN , MVT::f32, Expand);
547 setOperationAction(ISD::FCOS , MVT::f32, Expand);
548 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
550 // Expand FP immediates into loads from the stack, except for the special
552 addLegalFPImmediate(APFloat(+0.0)); // xorpd
553 addLegalFPImmediate(APFloat(+0.0f)); // xorps
554 } else if (!Subtarget->useSoftFloat() && X86ScalarSSEf32) {
555 // Use SSE for f32, x87 for f64.
556 // Set up the FP register classes.
557 addRegisterClass(MVT::f32, &X86::FR32RegClass);
558 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
560 // Use ANDPS to simulate FABS.
561 setOperationAction(ISD::FABS , MVT::f32, Custom);
563 // Use XORP to simulate FNEG.
564 setOperationAction(ISD::FNEG , MVT::f32, Custom);
566 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
568 // Use ANDPS and ORPS to simulate FCOPYSIGN.
569 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
570 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
572 // We don't support sin/cos/fmod
573 setOperationAction(ISD::FSIN , MVT::f32, Expand);
574 setOperationAction(ISD::FCOS , MVT::f32, Expand);
575 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
577 // Special cases we handle for FP constants.
578 addLegalFPImmediate(APFloat(+0.0f)); // xorps
579 addLegalFPImmediate(APFloat(+0.0)); // FLD0
580 addLegalFPImmediate(APFloat(+1.0)); // FLD1
581 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
582 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
584 if (!TM.Options.UnsafeFPMath) {
585 setOperationAction(ISD::FSIN , MVT::f64, Expand);
586 setOperationAction(ISD::FCOS , MVT::f64, Expand);
587 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
589 } else if (!Subtarget->useSoftFloat()) {
590 // f32 and f64 in x87.
591 // Set up the FP register classes.
592 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
593 addRegisterClass(MVT::f32, &X86::RFP32RegClass);
595 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
596 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
597 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
598 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
600 if (!TM.Options.UnsafeFPMath) {
601 setOperationAction(ISD::FSIN , MVT::f64, Expand);
602 setOperationAction(ISD::FSIN , MVT::f32, Expand);
603 setOperationAction(ISD::FCOS , MVT::f64, Expand);
604 setOperationAction(ISD::FCOS , MVT::f32, Expand);
605 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
606 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
608 addLegalFPImmediate(APFloat(+0.0)); // FLD0
609 addLegalFPImmediate(APFloat(+1.0)); // FLD1
610 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
611 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
612 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
613 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
614 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
615 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
618 // We don't support FMA.
619 setOperationAction(ISD::FMA, MVT::f64, Expand);
620 setOperationAction(ISD::FMA, MVT::f32, Expand);
622 // Long double always uses X87.
623 if (!Subtarget->useSoftFloat()) {
624 addRegisterClass(MVT::f80, &X86::RFP80RegClass);
625 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
626 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
628 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended);
629 addLegalFPImmediate(TmpFlt); // FLD0
631 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
634 APFloat TmpFlt2(+1.0);
635 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
637 addLegalFPImmediate(TmpFlt2); // FLD1
638 TmpFlt2.changeSign();
639 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
642 if (!TM.Options.UnsafeFPMath) {
643 setOperationAction(ISD::FSIN , MVT::f80, Expand);
644 setOperationAction(ISD::FCOS , MVT::f80, Expand);
645 setOperationAction(ISD::FSINCOS, MVT::f80, Expand);
648 setOperationAction(ISD::FFLOOR, MVT::f80, Expand);
649 setOperationAction(ISD::FCEIL, MVT::f80, Expand);
650 setOperationAction(ISD::FTRUNC, MVT::f80, Expand);
651 setOperationAction(ISD::FRINT, MVT::f80, Expand);
652 setOperationAction(ISD::FNEARBYINT, MVT::f80, Expand);
653 setOperationAction(ISD::FMA, MVT::f80, Expand);
656 // Always use a library call for pow.
657 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
658 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
659 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
661 setOperationAction(ISD::FLOG, MVT::f80, Expand);
662 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
663 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
664 setOperationAction(ISD::FEXP, MVT::f80, Expand);
665 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
666 setOperationAction(ISD::FMINNUM, MVT::f80, Expand);
667 setOperationAction(ISD::FMAXNUM, MVT::f80, Expand);
669 // First set operation action for all vector types to either promote
670 // (for widening) or expand (for scalarization). Then we will selectively
671 // turn on ones that can be effectively codegen'd.
672 for (MVT VT : MVT::vector_valuetypes()) {
673 setOperationAction(ISD::ADD , VT, Expand);
674 setOperationAction(ISD::SUB , VT, Expand);
675 setOperationAction(ISD::FADD, VT, Expand);
676 setOperationAction(ISD::FNEG, VT, Expand);
677 setOperationAction(ISD::FSUB, VT, Expand);
678 setOperationAction(ISD::MUL , VT, Expand);
679 setOperationAction(ISD::FMUL, VT, Expand);
680 setOperationAction(ISD::SDIV, VT, Expand);
681 setOperationAction(ISD::UDIV, VT, Expand);
682 setOperationAction(ISD::FDIV, VT, Expand);
683 setOperationAction(ISD::SREM, VT, Expand);
684 setOperationAction(ISD::UREM, VT, Expand);
685 setOperationAction(ISD::LOAD, VT, Expand);
686 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);
687 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT,Expand);
688 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
689 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT,Expand);
690 setOperationAction(ISD::INSERT_SUBVECTOR, VT,Expand);
691 setOperationAction(ISD::FABS, VT, Expand);
692 setOperationAction(ISD::FSIN, VT, Expand);
693 setOperationAction(ISD::FSINCOS, VT, Expand);
694 setOperationAction(ISD::FCOS, VT, Expand);
695 setOperationAction(ISD::FSINCOS, VT, Expand);
696 setOperationAction(ISD::FREM, VT, Expand);
697 setOperationAction(ISD::FMA, VT, Expand);
698 setOperationAction(ISD::FPOWI, VT, Expand);
699 setOperationAction(ISD::FSQRT, VT, Expand);
700 setOperationAction(ISD::FCOPYSIGN, VT, Expand);
701 setOperationAction(ISD::FFLOOR, VT, Expand);
702 setOperationAction(ISD::FCEIL, VT, Expand);
703 setOperationAction(ISD::FTRUNC, VT, Expand);
704 setOperationAction(ISD::FRINT, VT, Expand);
705 setOperationAction(ISD::FNEARBYINT, VT, Expand);
706 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
707 setOperationAction(ISD::MULHS, VT, Expand);
708 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
709 setOperationAction(ISD::MULHU, VT, Expand);
710 setOperationAction(ISD::SDIVREM, VT, Expand);
711 setOperationAction(ISD::UDIVREM, VT, Expand);
712 setOperationAction(ISD::FPOW, VT, Expand);
713 setOperationAction(ISD::CTPOP, VT, Expand);
714 setOperationAction(ISD::CTTZ, VT, Expand);
715 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
716 setOperationAction(ISD::CTLZ, VT, Expand);
717 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
718 setOperationAction(ISD::SHL, VT, Expand);
719 setOperationAction(ISD::SRA, VT, Expand);
720 setOperationAction(ISD::SRL, VT, Expand);
721 setOperationAction(ISD::ROTL, VT, Expand);
722 setOperationAction(ISD::ROTR, VT, Expand);
723 setOperationAction(ISD::BSWAP, VT, Expand);
724 setOperationAction(ISD::SETCC, VT, Expand);
725 setOperationAction(ISD::FLOG, VT, Expand);
726 setOperationAction(ISD::FLOG2, VT, Expand);
727 setOperationAction(ISD::FLOG10, VT, Expand);
728 setOperationAction(ISD::FEXP, VT, Expand);
729 setOperationAction(ISD::FEXP2, VT, Expand);
730 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
731 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
732 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
733 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
734 setOperationAction(ISD::SIGN_EXTEND_INREG, VT,Expand);
735 setOperationAction(ISD::TRUNCATE, VT, Expand);
736 setOperationAction(ISD::SIGN_EXTEND, VT, Expand);
737 setOperationAction(ISD::ZERO_EXTEND, VT, Expand);
738 setOperationAction(ISD::ANY_EXTEND, VT, Expand);
739 setOperationAction(ISD::VSELECT, VT, Expand);
740 setOperationAction(ISD::SELECT_CC, VT, Expand);
741 for (MVT InnerVT : MVT::vector_valuetypes()) {
742 setTruncStoreAction(InnerVT, VT, Expand);
744 setLoadExtAction(ISD::SEXTLOAD, InnerVT, VT, Expand);
745 setLoadExtAction(ISD::ZEXTLOAD, InnerVT, VT, Expand);
747 // N.b. ISD::EXTLOAD legality is basically ignored except for i1-like
748 // types, we have to deal with them whether we ask for Expansion or not.
749 // Setting Expand causes its own optimisation problems though, so leave
751 if (VT.getVectorElementType() == MVT::i1)
752 setLoadExtAction(ISD::EXTLOAD, InnerVT, VT, Expand);
754 // EXTLOAD for MVT::f16 vectors is not legal because f16 vectors are
755 // split/scalarized right now.
756 if (VT.getVectorElementType() == MVT::f16)
757 setLoadExtAction(ISD::EXTLOAD, InnerVT, VT, Expand);
761 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
762 // with -msoft-float, disable use of MMX as well.
763 if (!Subtarget->useSoftFloat() && Subtarget->hasMMX()) {
764 addRegisterClass(MVT::x86mmx, &X86::VR64RegClass);
765 // No operations on x86mmx supported, everything uses intrinsics.
768 // MMX-sized vectors (other than x86mmx) are expected to be expanded
769 // into smaller operations.
770 for (MVT MMXTy : {MVT::v8i8, MVT::v4i16, MVT::v2i32, MVT::v1i64}) {
771 setOperationAction(ISD::MULHS, MMXTy, Expand);
772 setOperationAction(ISD::AND, MMXTy, Expand);
773 setOperationAction(ISD::OR, MMXTy, Expand);
774 setOperationAction(ISD::XOR, MMXTy, Expand);
775 setOperationAction(ISD::SCALAR_TO_VECTOR, MMXTy, Expand);
776 setOperationAction(ISD::SELECT, MMXTy, Expand);
777 setOperationAction(ISD::BITCAST, MMXTy, Expand);
779 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand);
781 if (!Subtarget->useSoftFloat() && Subtarget->hasSSE1()) {
782 addRegisterClass(MVT::v4f32, &X86::VR128RegClass);
784 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
785 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
786 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
787 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
788 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
789 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
790 setOperationAction(ISD::FABS, MVT::v4f32, Custom);
791 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
792 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
793 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
794 setOperationAction(ISD::VSELECT, MVT::v4f32, Custom);
795 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
796 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
797 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Custom);
800 if (!Subtarget->useSoftFloat() && Subtarget->hasSSE2()) {
801 addRegisterClass(MVT::v2f64, &X86::VR128RegClass);
803 // FIXME: Unfortunately, -soft-float and -no-implicit-float mean XMM
804 // registers cannot be used even for integer operations.
805 addRegisterClass(MVT::v16i8, &X86::VR128RegClass);
806 addRegisterClass(MVT::v8i16, &X86::VR128RegClass);
807 addRegisterClass(MVT::v4i32, &X86::VR128RegClass);
808 addRegisterClass(MVT::v2i64, &X86::VR128RegClass);
810 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
811 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
812 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
813 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
814 setOperationAction(ISD::MUL, MVT::v16i8, Custom);
815 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
816 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
817 setOperationAction(ISD::UMUL_LOHI, MVT::v4i32, Custom);
818 setOperationAction(ISD::SMUL_LOHI, MVT::v4i32, Custom);
819 setOperationAction(ISD::MULHU, MVT::v8i16, Legal);
820 setOperationAction(ISD::MULHS, MVT::v8i16, Legal);
821 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
822 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
823 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
824 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
825 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
826 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
827 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
828 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
829 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
830 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
831 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
832 setOperationAction(ISD::FABS, MVT::v2f64, Custom);
834 setOperationAction(ISD::SMAX, MVT::v8i16, Legal);
835 setOperationAction(ISD::UMAX, MVT::v16i8, Legal);
836 setOperationAction(ISD::SMIN, MVT::v8i16, Legal);
837 setOperationAction(ISD::UMIN, MVT::v16i8, Legal);
839 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
840 setOperationAction(ISD::SETCC, MVT::v16i8, Custom);
841 setOperationAction(ISD::SETCC, MVT::v8i16, Custom);
842 setOperationAction(ISD::SETCC, MVT::v4i32, Custom);
844 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
845 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
846 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
847 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
848 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
850 setOperationAction(ISD::CTPOP, MVT::v16i8, Custom);
851 setOperationAction(ISD::CTPOP, MVT::v8i16, Custom);
852 setOperationAction(ISD::CTPOP, MVT::v4i32, Custom);
853 setOperationAction(ISD::CTPOP, MVT::v2i64, Custom);
855 setOperationAction(ISD::CTTZ, MVT::v16i8, Custom);
856 setOperationAction(ISD::CTTZ, MVT::v8i16, Custom);
857 setOperationAction(ISD::CTTZ, MVT::v4i32, Custom);
858 // ISD::CTTZ v2i64 - scalarization is faster.
859 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v16i8, Custom);
860 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v8i16, Custom);
861 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v4i32, Custom);
862 // ISD::CTTZ_ZERO_UNDEF v2i64 - scalarization is faster.
864 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
865 for (auto VT : { MVT::v16i8, MVT::v8i16, MVT::v4i32 }) {
866 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
867 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
868 setOperationAction(ISD::VSELECT, VT, Custom);
869 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
872 // We support custom legalizing of sext and anyext loads for specific
873 // memory vector types which we can load as a scalar (or sequence of
874 // scalars) and extend in-register to a legal 128-bit vector type. For sext
875 // loads these must work with a single scalar load.
876 for (MVT VT : MVT::integer_vector_valuetypes()) {
877 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v4i8, Custom);
878 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v4i16, Custom);
879 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v8i8, Custom);
880 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i8, Custom);
881 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i16, Custom);
882 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i32, Custom);
883 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4i8, Custom);
884 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4i16, Custom);
885 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v8i8, Custom);
888 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
889 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
890 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
891 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
892 setOperationAction(ISD::VSELECT, MVT::v2f64, Custom);
893 setOperationAction(ISD::VSELECT, MVT::v2i64, Custom);
894 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
895 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
897 if (Subtarget->is64Bit()) {
898 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
899 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
902 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
903 for (auto VT : { MVT::v16i8, MVT::v8i16, MVT::v4i32 }) {
904 setOperationAction(ISD::AND, VT, Promote);
905 AddPromotedToType (ISD::AND, VT, MVT::v2i64);
906 setOperationAction(ISD::OR, VT, Promote);
907 AddPromotedToType (ISD::OR, VT, MVT::v2i64);
908 setOperationAction(ISD::XOR, VT, Promote);
909 AddPromotedToType (ISD::XOR, VT, MVT::v2i64);
910 setOperationAction(ISD::LOAD, VT, Promote);
911 AddPromotedToType (ISD::LOAD, VT, MVT::v2i64);
912 setOperationAction(ISD::SELECT, VT, Promote);
913 AddPromotedToType (ISD::SELECT, VT, MVT::v2i64);
916 // Custom lower v2i64 and v2f64 selects.
917 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
918 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
919 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
920 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
922 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
923 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
925 setOperationAction(ISD::SINT_TO_FP, MVT::v2i32, Custom);
927 setOperationAction(ISD::UINT_TO_FP, MVT::v4i8, Custom);
928 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);
929 // As there is no 64-bit GPR available, we need build a special custom
930 // sequence to convert from v2i32 to v2f32.
931 if (!Subtarget->is64Bit())
932 setOperationAction(ISD::UINT_TO_FP, MVT::v2f32, Custom);
934 setOperationAction(ISD::FP_EXTEND, MVT::v2f32, Custom);
935 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Custom);
937 for (MVT VT : MVT::fp_vector_valuetypes())
938 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2f32, Legal);
940 setOperationAction(ISD::BITCAST, MVT::v2i32, Custom);
941 setOperationAction(ISD::BITCAST, MVT::v4i16, Custom);
942 setOperationAction(ISD::BITCAST, MVT::v8i8, Custom);
945 if (!Subtarget->useSoftFloat() && Subtarget->hasSSE41()) {
946 for (MVT RoundedTy : {MVT::f32, MVT::f64, MVT::v4f32, MVT::v2f64}) {
947 setOperationAction(ISD::FFLOOR, RoundedTy, Legal);
948 setOperationAction(ISD::FCEIL, RoundedTy, Legal);
949 setOperationAction(ISD::FTRUNC, RoundedTy, Legal);
950 setOperationAction(ISD::FRINT, RoundedTy, Legal);
951 setOperationAction(ISD::FNEARBYINT, RoundedTy, Legal);
954 setOperationAction(ISD::SMAX, MVT::v16i8, Legal);
955 setOperationAction(ISD::SMAX, MVT::v4i32, Legal);
956 setOperationAction(ISD::UMAX, MVT::v8i16, Legal);
957 setOperationAction(ISD::UMAX, MVT::v4i32, Legal);
958 setOperationAction(ISD::SMIN, MVT::v16i8, Legal);
959 setOperationAction(ISD::SMIN, MVT::v4i32, Legal);
960 setOperationAction(ISD::UMIN, MVT::v8i16, Legal);
961 setOperationAction(ISD::UMIN, MVT::v4i32, Legal);
963 // FIXME: Do we need to handle scalar-to-vector here?
964 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
966 // We directly match byte blends in the backend as they match the VSELECT
968 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
970 // SSE41 brings specific instructions for doing vector sign extend even in
971 // cases where we don't have SRA.
972 for (MVT VT : MVT::integer_vector_valuetypes()) {
973 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i8, Custom);
974 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i16, Custom);
975 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i32, Custom);
978 // SSE41 also has vector sign/zero extending loads, PMOV[SZ]X
979 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i16, MVT::v8i8, Legal);
980 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i32, MVT::v4i8, Legal);
981 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i64, MVT::v2i8, Legal);
982 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i32, MVT::v4i16, Legal);
983 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i64, MVT::v2i16, Legal);
984 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i64, MVT::v2i32, Legal);
986 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i16, MVT::v8i8, Legal);
987 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i32, MVT::v4i8, Legal);
988 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i64, MVT::v2i8, Legal);
989 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i32, MVT::v4i16, Legal);
990 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i64, MVT::v2i16, Legal);
991 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i64, MVT::v2i32, Legal);
993 // i8 and i16 vectors are custom because the source register and source
994 // source memory operand types are not the same width. f32 vectors are
995 // custom since the immediate controlling the insert encodes additional
997 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
998 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
999 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
1000 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
1002 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
1003 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
1004 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
1005 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
1007 // FIXME: these should be Legal, but that's only for the case where
1008 // the index is constant. For now custom expand to deal with that.
1009 if (Subtarget->is64Bit()) {
1010 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
1011 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
1015 if (Subtarget->hasSSE2()) {
1016 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v2i64, Custom);
1017 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v4i32, Custom);
1018 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v8i16, Custom);
1020 setOperationAction(ISD::SRL, MVT::v8i16, Custom);
1021 setOperationAction(ISD::SRL, MVT::v16i8, Custom);
1023 setOperationAction(ISD::SHL, MVT::v8i16, Custom);
1024 setOperationAction(ISD::SHL, MVT::v16i8, Custom);
1026 setOperationAction(ISD::SRA, MVT::v8i16, Custom);
1027 setOperationAction(ISD::SRA, MVT::v16i8, Custom);
1029 // In the customized shift lowering, the legal cases in AVX2 will be
1031 setOperationAction(ISD::SRL, MVT::v2i64, Custom);
1032 setOperationAction(ISD::SRL, MVT::v4i32, Custom);
1034 setOperationAction(ISD::SHL, MVT::v2i64, Custom);
1035 setOperationAction(ISD::SHL, MVT::v4i32, Custom);
1037 setOperationAction(ISD::SRA, MVT::v2i64, Custom);
1038 setOperationAction(ISD::SRA, MVT::v4i32, Custom);
1041 if (Subtarget->hasXOP()) {
1042 setOperationAction(ISD::ROTL, MVT::v16i8, Custom);
1043 setOperationAction(ISD::ROTL, MVT::v8i16, Custom);
1044 setOperationAction(ISD::ROTL, MVT::v4i32, Custom);
1045 setOperationAction(ISD::ROTL, MVT::v2i64, Custom);
1046 setOperationAction(ISD::ROTL, MVT::v32i8, Custom);
1047 setOperationAction(ISD::ROTL, MVT::v16i16, Custom);
1048 setOperationAction(ISD::ROTL, MVT::v8i32, Custom);
1049 setOperationAction(ISD::ROTL, MVT::v4i64, Custom);
1052 if (!Subtarget->useSoftFloat() && Subtarget->hasFp256()) {
1053 addRegisterClass(MVT::v32i8, &X86::VR256RegClass);
1054 addRegisterClass(MVT::v16i16, &X86::VR256RegClass);
1055 addRegisterClass(MVT::v8i32, &X86::VR256RegClass);
1056 addRegisterClass(MVT::v8f32, &X86::VR256RegClass);
1057 addRegisterClass(MVT::v4i64, &X86::VR256RegClass);
1058 addRegisterClass(MVT::v4f64, &X86::VR256RegClass);
1060 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
1061 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
1062 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
1064 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
1065 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
1066 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
1067 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
1068 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
1069 setOperationAction(ISD::FFLOOR, MVT::v8f32, Legal);
1070 setOperationAction(ISD::FCEIL, MVT::v8f32, Legal);
1071 setOperationAction(ISD::FTRUNC, MVT::v8f32, Legal);
1072 setOperationAction(ISD::FRINT, MVT::v8f32, Legal);
1073 setOperationAction(ISD::FNEARBYINT, MVT::v8f32, Legal);
1074 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
1075 setOperationAction(ISD::FABS, MVT::v8f32, Custom);
1077 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
1078 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
1079 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
1080 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
1081 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
1082 setOperationAction(ISD::FFLOOR, MVT::v4f64, Legal);
1083 setOperationAction(ISD::FCEIL, MVT::v4f64, Legal);
1084 setOperationAction(ISD::FTRUNC, MVT::v4f64, Legal);
1085 setOperationAction(ISD::FRINT, MVT::v4f64, Legal);
1086 setOperationAction(ISD::FNEARBYINT, MVT::v4f64, Legal);
1087 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
1088 setOperationAction(ISD::FABS, MVT::v4f64, Custom);
1090 // (fp_to_int:v8i16 (v8f32 ..)) requires the result type to be promoted
1091 // even though v8i16 is a legal type.
1092 setOperationAction(ISD::FP_TO_SINT, MVT::v8i16, Promote);
1093 setOperationAction(ISD::FP_TO_UINT, MVT::v8i16, Promote);
1094 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
1096 setOperationAction(ISD::SINT_TO_FP, MVT::v8i16, Promote);
1097 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
1098 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal);
1100 setOperationAction(ISD::UINT_TO_FP, MVT::v8i8, Custom);
1101 setOperationAction(ISD::UINT_TO_FP, MVT::v8i16, Custom);
1103 for (MVT VT : MVT::fp_vector_valuetypes())
1104 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4f32, Legal);
1106 setOperationAction(ISD::SRL, MVT::v16i16, Custom);
1107 setOperationAction(ISD::SRL, MVT::v32i8, Custom);
1109 setOperationAction(ISD::SHL, MVT::v16i16, Custom);
1110 setOperationAction(ISD::SHL, MVT::v32i8, Custom);
1112 setOperationAction(ISD::SRA, MVT::v16i16, Custom);
1113 setOperationAction(ISD::SRA, MVT::v32i8, Custom);
1115 setOperationAction(ISD::SETCC, MVT::v32i8, Custom);
1116 setOperationAction(ISD::SETCC, MVT::v16i16, Custom);
1117 setOperationAction(ISD::SETCC, MVT::v8i32, Custom);
1118 setOperationAction(ISD::SETCC, MVT::v4i64, Custom);
1120 setOperationAction(ISD::SELECT, MVT::v4f64, Custom);
1121 setOperationAction(ISD::SELECT, MVT::v4i64, Custom);
1122 setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
1124 setOperationAction(ISD::SIGN_EXTEND, MVT::v4i64, Custom);
1125 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i32, Custom);
1126 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1127 setOperationAction(ISD::ZERO_EXTEND, MVT::v4i64, Custom);
1128 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i32, Custom);
1129 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i16, Custom);
1130 setOperationAction(ISD::ANY_EXTEND, MVT::v4i64, Custom);
1131 setOperationAction(ISD::ANY_EXTEND, MVT::v8i32, Custom);
1132 setOperationAction(ISD::ANY_EXTEND, MVT::v16i16, Custom);
1133 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1134 setOperationAction(ISD::TRUNCATE, MVT::v8i16, Custom);
1135 setOperationAction(ISD::TRUNCATE, MVT::v4i32, Custom);
1137 setOperationAction(ISD::CTPOP, MVT::v32i8, Custom);
1138 setOperationAction(ISD::CTPOP, MVT::v16i16, Custom);
1139 setOperationAction(ISD::CTPOP, MVT::v8i32, Custom);
1140 setOperationAction(ISD::CTPOP, MVT::v4i64, Custom);
1142 setOperationAction(ISD::CTTZ, MVT::v32i8, Custom);
1143 setOperationAction(ISD::CTTZ, MVT::v16i16, Custom);
1144 setOperationAction(ISD::CTTZ, MVT::v8i32, Custom);
1145 setOperationAction(ISD::CTTZ, MVT::v4i64, Custom);
1146 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v32i8, Custom);
1147 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v16i16, Custom);
1148 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v8i32, Custom);
1149 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v4i64, Custom);
1151 if (Subtarget->hasAnyFMA()) {
1152 setOperationAction(ISD::FMA, MVT::v8f32, Legal);
1153 setOperationAction(ISD::FMA, MVT::v4f64, Legal);
1154 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
1155 setOperationAction(ISD::FMA, MVT::v2f64, Legal);
1156 setOperationAction(ISD::FMA, MVT::f32, Legal);
1157 setOperationAction(ISD::FMA, MVT::f64, Legal);
1160 if (Subtarget->hasInt256()) {
1161 setOperationAction(ISD::ADD, MVT::v4i64, Legal);
1162 setOperationAction(ISD::ADD, MVT::v8i32, Legal);
1163 setOperationAction(ISD::ADD, MVT::v16i16, Legal);
1164 setOperationAction(ISD::ADD, MVT::v32i8, Legal);
1166 setOperationAction(ISD::SUB, MVT::v4i64, Legal);
1167 setOperationAction(ISD::SUB, MVT::v8i32, Legal);
1168 setOperationAction(ISD::SUB, MVT::v16i16, Legal);
1169 setOperationAction(ISD::SUB, MVT::v32i8, Legal);
1171 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1172 setOperationAction(ISD::MUL, MVT::v8i32, Legal);
1173 setOperationAction(ISD::MUL, MVT::v16i16, Legal);
1174 setOperationAction(ISD::MUL, MVT::v32i8, Custom);
1176 setOperationAction(ISD::UMUL_LOHI, MVT::v8i32, Custom);
1177 setOperationAction(ISD::SMUL_LOHI, MVT::v8i32, Custom);
1178 setOperationAction(ISD::MULHU, MVT::v16i16, Legal);
1179 setOperationAction(ISD::MULHS, MVT::v16i16, Legal);
1181 setOperationAction(ISD::SMAX, MVT::v32i8, Legal);
1182 setOperationAction(ISD::SMAX, MVT::v16i16, Legal);
1183 setOperationAction(ISD::SMAX, MVT::v8i32, Legal);
1184 setOperationAction(ISD::UMAX, MVT::v32i8, Legal);
1185 setOperationAction(ISD::UMAX, MVT::v16i16, Legal);
1186 setOperationAction(ISD::UMAX, MVT::v8i32, Legal);
1187 setOperationAction(ISD::SMIN, MVT::v32i8, Legal);
1188 setOperationAction(ISD::SMIN, MVT::v16i16, Legal);
1189 setOperationAction(ISD::SMIN, MVT::v8i32, Legal);
1190 setOperationAction(ISD::UMIN, MVT::v32i8, Legal);
1191 setOperationAction(ISD::UMIN, MVT::v16i16, Legal);
1192 setOperationAction(ISD::UMIN, MVT::v8i32, Legal);
1194 // The custom lowering for UINT_TO_FP for v8i32 becomes interesting
1195 // when we have a 256bit-wide blend with immediate.
1196 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Custom);
1198 // AVX2 also has wider vector sign/zero extending loads, VPMOV[SZ]X
1199 setLoadExtAction(ISD::SEXTLOAD, MVT::v16i16, MVT::v16i8, Legal);
1200 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i32, MVT::v8i8, Legal);
1201 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i64, MVT::v4i8, Legal);
1202 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i32, MVT::v8i16, Legal);
1203 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i64, MVT::v4i16, Legal);
1204 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i64, MVT::v4i32, Legal);
1206 setLoadExtAction(ISD::ZEXTLOAD, MVT::v16i16, MVT::v16i8, Legal);
1207 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i32, MVT::v8i8, Legal);
1208 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i64, MVT::v4i8, Legal);
1209 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i32, MVT::v8i16, Legal);
1210 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i64, MVT::v4i16, Legal);
1211 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i64, MVT::v4i32, Legal);
1213 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
1214 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
1215 setOperationAction(ISD::ADD, MVT::v16i16, Custom);
1216 setOperationAction(ISD::ADD, MVT::v32i8, Custom);
1218 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
1219 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
1220 setOperationAction(ISD::SUB, MVT::v16i16, Custom);
1221 setOperationAction(ISD::SUB, MVT::v32i8, Custom);
1223 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1224 setOperationAction(ISD::MUL, MVT::v8i32, Custom);
1225 setOperationAction(ISD::MUL, MVT::v16i16, Custom);
1226 setOperationAction(ISD::MUL, MVT::v32i8, Custom);
1228 setOperationAction(ISD::SMAX, MVT::v32i8, Custom);
1229 setOperationAction(ISD::SMAX, MVT::v16i16, Custom);
1230 setOperationAction(ISD::SMAX, MVT::v8i32, Custom);
1231 setOperationAction(ISD::UMAX, MVT::v32i8, Custom);
1232 setOperationAction(ISD::UMAX, MVT::v16i16, Custom);
1233 setOperationAction(ISD::UMAX, MVT::v8i32, Custom);
1234 setOperationAction(ISD::SMIN, MVT::v32i8, Custom);
1235 setOperationAction(ISD::SMIN, MVT::v16i16, Custom);
1236 setOperationAction(ISD::SMIN, MVT::v8i32, Custom);
1237 setOperationAction(ISD::UMIN, MVT::v32i8, Custom);
1238 setOperationAction(ISD::UMIN, MVT::v16i16, Custom);
1239 setOperationAction(ISD::UMIN, MVT::v8i32, Custom);
1242 // In the customized shift lowering, the legal cases in AVX2 will be
1244 setOperationAction(ISD::SRL, MVT::v4i64, Custom);
1245 setOperationAction(ISD::SRL, MVT::v8i32, Custom);
1247 setOperationAction(ISD::SHL, MVT::v4i64, Custom);
1248 setOperationAction(ISD::SHL, MVT::v8i32, Custom);
1250 setOperationAction(ISD::SRA, MVT::v4i64, Custom);
1251 setOperationAction(ISD::SRA, MVT::v8i32, Custom);
1253 // Custom lower several nodes for 256-bit types.
1254 for (MVT VT : MVT::vector_valuetypes()) {
1255 if (VT.getScalarSizeInBits() >= 32) {
1256 setOperationAction(ISD::MLOAD, VT, Legal);
1257 setOperationAction(ISD::MSTORE, VT, Legal);
1259 // Extract subvector is special because the value type
1260 // (result) is 128-bit but the source is 256-bit wide.
1261 if (VT.is128BitVector()) {
1262 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1264 // Do not attempt to custom lower other non-256-bit vectors
1265 if (!VT.is256BitVector())
1268 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1269 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1270 setOperationAction(ISD::VSELECT, VT, Custom);
1271 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1272 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1273 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1274 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1275 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom);
1278 if (Subtarget->hasInt256())
1279 setOperationAction(ISD::VSELECT, MVT::v32i8, Legal);
1281 // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64.
1282 for (auto VT : { MVT::v32i8, MVT::v16i16, MVT::v8i32 }) {
1283 setOperationAction(ISD::AND, VT, Promote);
1284 AddPromotedToType (ISD::AND, VT, MVT::v4i64);
1285 setOperationAction(ISD::OR, VT, Promote);
1286 AddPromotedToType (ISD::OR, VT, MVT::v4i64);
1287 setOperationAction(ISD::XOR, VT, Promote);
1288 AddPromotedToType (ISD::XOR, VT, MVT::v4i64);
1289 setOperationAction(ISD::LOAD, VT, Promote);
1290 AddPromotedToType (ISD::LOAD, VT, MVT::v4i64);
1291 setOperationAction(ISD::SELECT, VT, Promote);
1292 AddPromotedToType (ISD::SELECT, VT, MVT::v4i64);
1296 if (!Subtarget->useSoftFloat() && Subtarget->hasAVX512()) {
1297 addRegisterClass(MVT::v16i32, &X86::VR512RegClass);
1298 addRegisterClass(MVT::v16f32, &X86::VR512RegClass);
1299 addRegisterClass(MVT::v8i64, &X86::VR512RegClass);
1300 addRegisterClass(MVT::v8f64, &X86::VR512RegClass);
1302 addRegisterClass(MVT::i1, &X86::VK1RegClass);
1303 addRegisterClass(MVT::v8i1, &X86::VK8RegClass);
1304 addRegisterClass(MVT::v16i1, &X86::VK16RegClass);
1306 for (MVT VT : MVT::fp_vector_valuetypes())
1307 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v8f32, Legal);
1309 setLoadExtAction(ISD::ZEXTLOAD, MVT::v16i32, MVT::v16i8, Legal);
1310 setLoadExtAction(ISD::SEXTLOAD, MVT::v16i32, MVT::v16i8, Legal);
1311 setLoadExtAction(ISD::ZEXTLOAD, MVT::v16i32, MVT::v16i16, Legal);
1312 setLoadExtAction(ISD::SEXTLOAD, MVT::v16i32, MVT::v16i16, Legal);
1313 setLoadExtAction(ISD::ZEXTLOAD, MVT::v32i16, MVT::v32i8, Legal);
1314 setLoadExtAction(ISD::SEXTLOAD, MVT::v32i16, MVT::v32i8, Legal);
1315 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i64, MVT::v8i8, Legal);
1316 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i64, MVT::v8i8, Legal);
1317 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i64, MVT::v8i16, Legal);
1318 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i64, MVT::v8i16, Legal);
1319 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i64, MVT::v8i32, Legal);
1320 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i64, MVT::v8i32, Legal);
1322 setOperationAction(ISD::BR_CC, MVT::i1, Expand);
1323 setOperationAction(ISD::SETCC, MVT::i1, Custom);
1324 setOperationAction(ISD::SELECT_CC, MVT::i1, Expand);
1325 setOperationAction(ISD::XOR, MVT::i1, Legal);
1326 setOperationAction(ISD::OR, MVT::i1, Legal);
1327 setOperationAction(ISD::AND, MVT::i1, Legal);
1328 setOperationAction(ISD::SUB, MVT::i1, Custom);
1329 setOperationAction(ISD::ADD, MVT::i1, Custom);
1330 setOperationAction(ISD::MUL, MVT::i1, Custom);
1331 setOperationAction(ISD::LOAD, MVT::v16f32, Legal);
1332 setOperationAction(ISD::LOAD, MVT::v8f64, Legal);
1333 setOperationAction(ISD::LOAD, MVT::v8i64, Legal);
1334 setOperationAction(ISD::LOAD, MVT::v16i32, Legal);
1335 setOperationAction(ISD::LOAD, MVT::v16i1, Legal);
1337 setOperationAction(ISD::FADD, MVT::v16f32, Legal);
1338 setOperationAction(ISD::FSUB, MVT::v16f32, Legal);
1339 setOperationAction(ISD::FMUL, MVT::v16f32, Legal);
1340 setOperationAction(ISD::FDIV, MVT::v16f32, Legal);
1341 setOperationAction(ISD::FSQRT, MVT::v16f32, Legal);
1342 setOperationAction(ISD::FNEG, MVT::v16f32, Custom);
1344 setOperationAction(ISD::FADD, MVT::v8f64, Legal);
1345 setOperationAction(ISD::FSUB, MVT::v8f64, Legal);
1346 setOperationAction(ISD::FMUL, MVT::v8f64, Legal);
1347 setOperationAction(ISD::FDIV, MVT::v8f64, Legal);
1348 setOperationAction(ISD::FSQRT, MVT::v8f64, Legal);
1349 setOperationAction(ISD::FNEG, MVT::v8f64, Custom);
1350 setOperationAction(ISD::FMA, MVT::v8f64, Legal);
1351 setOperationAction(ISD::FMA, MVT::v16f32, Legal);
1353 setOperationAction(ISD::FP_TO_SINT, MVT::v16i32, Legal);
1354 setOperationAction(ISD::FP_TO_UINT, MVT::v16i32, Legal);
1355 setOperationAction(ISD::FP_TO_UINT, MVT::v8i32, Legal);
1356 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
1357 setOperationAction(ISD::SINT_TO_FP, MVT::v16i32, Legal);
1358 setOperationAction(ISD::SINT_TO_FP, MVT::v8i1, Custom);
1359 setOperationAction(ISD::SINT_TO_FP, MVT::v16i1, Custom);
1360 setOperationAction(ISD::SINT_TO_FP, MVT::v16i8, Promote);
1361 setOperationAction(ISD::SINT_TO_FP, MVT::v16i16, Promote);
1362 setOperationAction(ISD::UINT_TO_FP, MVT::v16i32, Legal);
1363 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Legal);
1364 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
1365 setOperationAction(ISD::UINT_TO_FP, MVT::v16i8, Custom);
1366 setOperationAction(ISD::UINT_TO_FP, MVT::v16i16, Custom);
1367 setOperationAction(ISD::FP_ROUND, MVT::v8f32, Legal);
1368 setOperationAction(ISD::FP_EXTEND, MVT::v8f32, Legal);
1370 setTruncStoreAction(MVT::v8i64, MVT::v8i8, Legal);
1371 setTruncStoreAction(MVT::v8i64, MVT::v8i16, Legal);
1372 setTruncStoreAction(MVT::v8i64, MVT::v8i32, Legal);
1373 setTruncStoreAction(MVT::v16i32, MVT::v16i8, Legal);
1374 setTruncStoreAction(MVT::v16i32, MVT::v16i16, Legal);
1375 if (Subtarget->hasVLX()){
1376 setTruncStoreAction(MVT::v4i64, MVT::v4i8, Legal);
1377 setTruncStoreAction(MVT::v4i64, MVT::v4i16, Legal);
1378 setTruncStoreAction(MVT::v4i64, MVT::v4i32, Legal);
1379 setTruncStoreAction(MVT::v8i32, MVT::v8i8, Legal);
1380 setTruncStoreAction(MVT::v8i32, MVT::v8i16, Legal);
1382 setTruncStoreAction(MVT::v2i64, MVT::v2i8, Legal);
1383 setTruncStoreAction(MVT::v2i64, MVT::v2i16, Legal);
1384 setTruncStoreAction(MVT::v2i64, MVT::v2i32, Legal);
1385 setTruncStoreAction(MVT::v4i32, MVT::v4i8, Legal);
1386 setTruncStoreAction(MVT::v4i32, MVT::v4i16, Legal);
1388 setOperationAction(ISD::TRUNCATE, MVT::i1, Custom);
1389 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1390 setOperationAction(ISD::TRUNCATE, MVT::v8i32, Custom);
1391 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i1, Custom);
1392 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i1, Custom);
1393 if (Subtarget->hasDQI()) {
1394 setOperationAction(ISD::TRUNCATE, MVT::v2i1, Custom);
1395 setOperationAction(ISD::TRUNCATE, MVT::v4i1, Custom);
1397 setOperationAction(ISD::SINT_TO_FP, MVT::v8i64, Legal);
1398 setOperationAction(ISD::UINT_TO_FP, MVT::v8i64, Legal);
1399 setOperationAction(ISD::FP_TO_SINT, MVT::v8i64, Legal);
1400 setOperationAction(ISD::FP_TO_UINT, MVT::v8i64, Legal);
1401 if (Subtarget->hasVLX()) {
1402 setOperationAction(ISD::SINT_TO_FP, MVT::v4i64, Legal);
1403 setOperationAction(ISD::SINT_TO_FP, MVT::v2i64, Legal);
1404 setOperationAction(ISD::UINT_TO_FP, MVT::v4i64, Legal);
1405 setOperationAction(ISD::UINT_TO_FP, MVT::v2i64, Legal);
1406 setOperationAction(ISD::FP_TO_SINT, MVT::v4i64, Legal);
1407 setOperationAction(ISD::FP_TO_SINT, MVT::v2i64, Legal);
1408 setOperationAction(ISD::FP_TO_UINT, MVT::v4i64, Legal);
1409 setOperationAction(ISD::FP_TO_UINT, MVT::v2i64, Legal);
1412 if (Subtarget->hasVLX()) {
1413 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
1414 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Legal);
1415 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
1416 setOperationAction(ISD::FP_TO_UINT, MVT::v8i32, Legal);
1417 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
1418 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
1419 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
1420 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
1422 setOperationAction(ISD::TRUNCATE, MVT::v8i1, Custom);
1423 setOperationAction(ISD::TRUNCATE, MVT::v16i1, Custom);
1424 setOperationAction(ISD::TRUNCATE, MVT::v16i16, Custom);
1425 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i32, Custom);
1426 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i64, Custom);
1427 setOperationAction(ISD::ANY_EXTEND, MVT::v16i32, Custom);
1428 setOperationAction(ISD::ANY_EXTEND, MVT::v8i64, Custom);
1429 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i32, Custom);
1430 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i64, Custom);
1431 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i8, Custom);
1432 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i16, Custom);
1433 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1434 if (Subtarget->hasDQI()) {
1435 setOperationAction(ISD::SIGN_EXTEND, MVT::v4i32, Custom);
1436 setOperationAction(ISD::SIGN_EXTEND, MVT::v2i64, Custom);
1438 setOperationAction(ISD::FFLOOR, MVT::v16f32, Legal);
1439 setOperationAction(ISD::FFLOOR, MVT::v8f64, Legal);
1440 setOperationAction(ISD::FCEIL, MVT::v16f32, Legal);
1441 setOperationAction(ISD::FCEIL, MVT::v8f64, Legal);
1442 setOperationAction(ISD::FTRUNC, MVT::v16f32, Legal);
1443 setOperationAction(ISD::FTRUNC, MVT::v8f64, Legal);
1444 setOperationAction(ISD::FRINT, MVT::v16f32, Legal);
1445 setOperationAction(ISD::FRINT, MVT::v8f64, Legal);
1446 setOperationAction(ISD::FNEARBYINT, MVT::v16f32, Legal);
1447 setOperationAction(ISD::FNEARBYINT, MVT::v8f64, Legal);
1449 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f64, Custom);
1450 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i64, Custom);
1451 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16f32, Custom);
1452 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i32, Custom);
1453 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i1, Custom);
1455 setOperationAction(ISD::SETCC, MVT::v16i1, Custom);
1456 setOperationAction(ISD::SETCC, MVT::v8i1, Custom);
1458 setOperationAction(ISD::MUL, MVT::v8i64, Custom);
1460 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i1, Custom);
1461 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i1, Custom);
1462 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i1, Custom);
1463 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i1, Custom);
1464 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i1, Custom);
1465 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i1, Custom);
1466 setOperationAction(ISD::SELECT, MVT::v8f64, Custom);
1467 setOperationAction(ISD::SELECT, MVT::v8i64, Custom);
1468 setOperationAction(ISD::SELECT, MVT::v16f32, Custom);
1469 setOperationAction(ISD::SELECT, MVT::v16i1, Custom);
1470 setOperationAction(ISD::SELECT, MVT::v8i1, Custom);
1472 setOperationAction(ISD::SMAX, MVT::v16i32, Legal);
1473 setOperationAction(ISD::SMAX, MVT::v8i64, Legal);
1474 setOperationAction(ISD::UMAX, MVT::v16i32, Legal);
1475 setOperationAction(ISD::UMAX, MVT::v8i64, Legal);
1476 setOperationAction(ISD::SMIN, MVT::v16i32, Legal);
1477 setOperationAction(ISD::SMIN, MVT::v8i64, Legal);
1478 setOperationAction(ISD::UMIN, MVT::v16i32, Legal);
1479 setOperationAction(ISD::UMIN, MVT::v8i64, Legal);
1481 setOperationAction(ISD::ADD, MVT::v8i64, Legal);
1482 setOperationAction(ISD::ADD, MVT::v16i32, Legal);
1484 setOperationAction(ISD::SUB, MVT::v8i64, Legal);
1485 setOperationAction(ISD::SUB, MVT::v16i32, Legal);
1487 setOperationAction(ISD::MUL, MVT::v16i32, Legal);
1489 setOperationAction(ISD::SRL, MVT::v8i64, Custom);
1490 setOperationAction(ISD::SRL, MVT::v16i32, Custom);
1492 setOperationAction(ISD::SHL, MVT::v8i64, Custom);
1493 setOperationAction(ISD::SHL, MVT::v16i32, Custom);
1495 setOperationAction(ISD::SRA, MVT::v8i64, Custom);
1496 setOperationAction(ISD::SRA, MVT::v16i32, Custom);
1498 setOperationAction(ISD::AND, MVT::v8i64, Legal);
1499 setOperationAction(ISD::OR, MVT::v8i64, Legal);
1500 setOperationAction(ISD::XOR, MVT::v8i64, Legal);
1501 setOperationAction(ISD::AND, MVT::v16i32, Legal);
1502 setOperationAction(ISD::OR, MVT::v16i32, Legal);
1503 setOperationAction(ISD::XOR, MVT::v16i32, Legal);
1505 if (Subtarget->hasCDI()) {
1506 setOperationAction(ISD::CTLZ, MVT::v8i64, Legal);
1507 setOperationAction(ISD::CTLZ, MVT::v16i32, Legal);
1508 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v8i64, Legal);
1509 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v16i32, Legal);
1511 setOperationAction(ISD::CTLZ, MVT::v8i16, Custom);
1512 setOperationAction(ISD::CTLZ, MVT::v16i8, Custom);
1513 setOperationAction(ISD::CTLZ, MVT::v16i16, Custom);
1514 setOperationAction(ISD::CTLZ, MVT::v32i8, Custom);
1515 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v8i16, Custom);
1516 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v16i8, Custom);
1517 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v16i16, Custom);
1518 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v32i8, Custom);
1520 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v8i64, Custom);
1521 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v16i32, Custom);
1523 if (Subtarget->hasVLX()) {
1524 setOperationAction(ISD::CTLZ, MVT::v4i64, Legal);
1525 setOperationAction(ISD::CTLZ, MVT::v8i32, Legal);
1526 setOperationAction(ISD::CTLZ, MVT::v2i64, Legal);
1527 setOperationAction(ISD::CTLZ, MVT::v4i32, Legal);
1528 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v4i64, Legal);
1529 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v8i32, Legal);
1530 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v2i64, Legal);
1531 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v4i32, Legal);
1533 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v4i64, Custom);
1534 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v8i32, Custom);
1535 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v2i64, Custom);
1536 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v4i32, Custom);
1538 setOperationAction(ISD::CTLZ, MVT::v4i64, Custom);
1539 setOperationAction(ISD::CTLZ, MVT::v8i32, Custom);
1540 setOperationAction(ISD::CTLZ, MVT::v2i64, Custom);
1541 setOperationAction(ISD::CTLZ, MVT::v4i32, Custom);
1542 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v4i64, Custom);
1543 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v8i32, Custom);
1544 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v2i64, Custom);
1545 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v4i32, Custom);
1547 } // Subtarget->hasCDI()
1549 if (Subtarget->hasDQI()) {
1550 setOperationAction(ISD::MUL, MVT::v2i64, Legal);
1551 setOperationAction(ISD::MUL, MVT::v4i64, Legal);
1552 setOperationAction(ISD::MUL, MVT::v8i64, Legal);
1554 // Custom lower several nodes.
1555 for (MVT VT : MVT::vector_valuetypes()) {
1556 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1558 setOperationAction(ISD::AND, VT, Legal);
1559 setOperationAction(ISD::OR, VT, Legal);
1560 setOperationAction(ISD::XOR, VT, Legal);
1562 if (EltSize >= 32 && VT.getSizeInBits() <= 512) {
1563 setOperationAction(ISD::MGATHER, VT, Custom);
1564 setOperationAction(ISD::MSCATTER, VT, Custom);
1566 // Extract subvector is special because the value type
1567 // (result) is 256/128-bit but the source is 512-bit wide.
1568 if (VT.is128BitVector() || VT.is256BitVector()) {
1569 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1571 if (VT.getVectorElementType() == MVT::i1)
1572 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal);
1574 // Do not attempt to custom lower other non-512-bit vectors
1575 if (!VT.is512BitVector())
1578 if (EltSize >= 32) {
1579 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1580 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1581 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1582 setOperationAction(ISD::VSELECT, VT, Legal);
1583 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1584 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1585 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1586 setOperationAction(ISD::MLOAD, VT, Legal);
1587 setOperationAction(ISD::MSTORE, VT, Legal);
1590 for (auto VT : { MVT::v64i8, MVT::v32i16, MVT::v16i32 }) {
1591 setOperationAction(ISD::SELECT, VT, Promote);
1592 AddPromotedToType (ISD::SELECT, VT, MVT::v8i64);
1596 if (!Subtarget->useSoftFloat() && Subtarget->hasBWI()) {
1597 addRegisterClass(MVT::v32i16, &X86::VR512RegClass);
1598 addRegisterClass(MVT::v64i8, &X86::VR512RegClass);
1600 addRegisterClass(MVT::v32i1, &X86::VK32RegClass);
1601 addRegisterClass(MVT::v64i1, &X86::VK64RegClass);
1603 setOperationAction(ISD::LOAD, MVT::v32i16, Legal);
1604 setOperationAction(ISD::LOAD, MVT::v64i8, Legal);
1605 setOperationAction(ISD::SETCC, MVT::v32i1, Custom);
1606 setOperationAction(ISD::SETCC, MVT::v64i1, Custom);
1607 setOperationAction(ISD::ADD, MVT::v32i16, Legal);
1608 setOperationAction(ISD::ADD, MVT::v64i8, Legal);
1609 setOperationAction(ISD::SUB, MVT::v32i16, Legal);
1610 setOperationAction(ISD::SUB, MVT::v64i8, Legal);
1611 setOperationAction(ISD::MUL, MVT::v32i16, Legal);
1612 setOperationAction(ISD::MULHS, MVT::v32i16, Legal);
1613 setOperationAction(ISD::MULHU, MVT::v32i16, Legal);
1614 setOperationAction(ISD::CONCAT_VECTORS, MVT::v32i1, Custom);
1615 setOperationAction(ISD::CONCAT_VECTORS, MVT::v64i1, Custom);
1616 setOperationAction(ISD::CONCAT_VECTORS, MVT::v32i16, Custom);
1617 setOperationAction(ISD::CONCAT_VECTORS, MVT::v64i8, Custom);
1618 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v32i1, Custom);
1619 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v64i1, Custom);
1620 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v32i16, Custom);
1621 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v64i8, Custom);
1622 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v32i16, Custom);
1623 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v64i8, Custom);
1624 setOperationAction(ISD::SELECT, MVT::v32i1, Custom);
1625 setOperationAction(ISD::SELECT, MVT::v64i1, Custom);
1626 setOperationAction(ISD::SIGN_EXTEND, MVT::v32i8, Custom);
1627 setOperationAction(ISD::ZERO_EXTEND, MVT::v32i8, Custom);
1628 setOperationAction(ISD::SIGN_EXTEND, MVT::v32i16, Custom);
1629 setOperationAction(ISD::ZERO_EXTEND, MVT::v32i16, Custom);
1630 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v32i16, Custom);
1631 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v64i8, Custom);
1632 setOperationAction(ISD::SIGN_EXTEND, MVT::v64i8, Custom);
1633 setOperationAction(ISD::ZERO_EXTEND, MVT::v64i8, Custom);
1634 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v32i1, Custom);
1635 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v64i1, Custom);
1636 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v32i16, Custom);
1637 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v64i8, Custom);
1638 setOperationAction(ISD::VSELECT, MVT::v32i16, Legal);
1639 setOperationAction(ISD::VSELECT, MVT::v64i8, Legal);
1640 setOperationAction(ISD::TRUNCATE, MVT::v32i1, Custom);
1641 setOperationAction(ISD::TRUNCATE, MVT::v64i1, Custom);
1642 setOperationAction(ISD::TRUNCATE, MVT::v32i8, Custom);
1643 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v32i1, Custom);
1644 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v64i1, Custom);
1646 setOperationAction(ISD::SMAX, MVT::v64i8, Legal);
1647 setOperationAction(ISD::SMAX, MVT::v32i16, Legal);
1648 setOperationAction(ISD::UMAX, MVT::v64i8, Legal);
1649 setOperationAction(ISD::UMAX, MVT::v32i16, Legal);
1650 setOperationAction(ISD::SMIN, MVT::v64i8, Legal);
1651 setOperationAction(ISD::SMIN, MVT::v32i16, Legal);
1652 setOperationAction(ISD::UMIN, MVT::v64i8, Legal);
1653 setOperationAction(ISD::UMIN, MVT::v32i16, Legal);
1655 setTruncStoreAction(MVT::v32i16, MVT::v32i8, Legal);
1656 setTruncStoreAction(MVT::v16i16, MVT::v16i8, Legal);
1657 if (Subtarget->hasVLX())
1658 setTruncStoreAction(MVT::v8i16, MVT::v8i8, Legal);
1660 if (Subtarget->hasCDI()) {
1661 setOperationAction(ISD::CTLZ, MVT::v32i16, Custom);
1662 setOperationAction(ISD::CTLZ, MVT::v64i8, Custom);
1663 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v32i16, Custom);
1664 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v64i8, Custom);
1667 for (auto VT : { MVT::v64i8, MVT::v32i16 }) {
1668 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1669 setOperationAction(ISD::VSELECT, VT, Legal);
1673 if (!Subtarget->useSoftFloat() && Subtarget->hasVLX()) {
1674 addRegisterClass(MVT::v4i1, &X86::VK4RegClass);
1675 addRegisterClass(MVT::v2i1, &X86::VK2RegClass);
1677 setOperationAction(ISD::SETCC, MVT::v4i1, Custom);
1678 setOperationAction(ISD::SETCC, MVT::v2i1, Custom);
1679 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i1, Custom);
1680 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i1, Custom);
1681 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v8i1, Custom);
1682 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v4i1, Custom);
1683 setOperationAction(ISD::SELECT, MVT::v4i1, Custom);
1684 setOperationAction(ISD::SELECT, MVT::v2i1, Custom);
1685 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i1, Custom);
1686 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i1, Custom);
1687 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i1, Custom);
1688 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i1, Custom);
1690 setOperationAction(ISD::AND, MVT::v8i32, Legal);
1691 setOperationAction(ISD::OR, MVT::v8i32, Legal);
1692 setOperationAction(ISD::XOR, MVT::v8i32, Legal);
1693 setOperationAction(ISD::AND, MVT::v4i32, Legal);
1694 setOperationAction(ISD::OR, MVT::v4i32, Legal);
1695 setOperationAction(ISD::XOR, MVT::v4i32, Legal);
1696 setOperationAction(ISD::SRA, MVT::v2i64, Custom);
1697 setOperationAction(ISD::SRA, MVT::v4i64, Custom);
1699 setOperationAction(ISD::SMAX, MVT::v2i64, Legal);
1700 setOperationAction(ISD::SMAX, MVT::v4i64, Legal);
1701 setOperationAction(ISD::UMAX, MVT::v2i64, Legal);
1702 setOperationAction(ISD::UMAX, MVT::v4i64, Legal);
1703 setOperationAction(ISD::SMIN, MVT::v2i64, Legal);
1704 setOperationAction(ISD::SMIN, MVT::v4i64, Legal);
1705 setOperationAction(ISD::UMIN, MVT::v2i64, Legal);
1706 setOperationAction(ISD::UMIN, MVT::v4i64, Legal);
1709 // We want to custom lower some of our intrinsics.
1710 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
1711 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
1712 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
1713 if (!Subtarget->is64Bit()) {
1714 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i64, Custom);
1715 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::i64, Custom);
1718 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't
1719 // handle type legalization for these operations here.
1721 // FIXME: We really should do custom legalization for addition and
1722 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better
1723 // than generic legalization for 64-bit multiplication-with-overflow, though.
1724 for (auto VT : { MVT::i8, MVT::i16, MVT::i32, MVT::i64 }) {
1725 if (VT == MVT::i64 && !Subtarget->is64Bit())
1727 // Add/Sub/Mul with overflow operations are custom lowered.
1728 setOperationAction(ISD::SADDO, VT, Custom);
1729 setOperationAction(ISD::UADDO, VT, Custom);
1730 setOperationAction(ISD::SSUBO, VT, Custom);
1731 setOperationAction(ISD::USUBO, VT, Custom);
1732 setOperationAction(ISD::SMULO, VT, Custom);
1733 setOperationAction(ISD::UMULO, VT, Custom);
1736 if (!Subtarget->is64Bit()) {
1737 // These libcalls are not available in 32-bit.
1738 setLibcallName(RTLIB::SHL_I128, nullptr);
1739 setLibcallName(RTLIB::SRL_I128, nullptr);
1740 setLibcallName(RTLIB::SRA_I128, nullptr);
1743 // Combine sin / cos into one node or libcall if possible.
1744 if (Subtarget->hasSinCos()) {
1745 setLibcallName(RTLIB::SINCOS_F32, "sincosf");
1746 setLibcallName(RTLIB::SINCOS_F64, "sincos");
1747 if (Subtarget->isTargetDarwin()) {
1748 // For MacOSX, we don't want the normal expansion of a libcall to sincos.
1749 // We want to issue a libcall to __sincos_stret to avoid memory traffic.
1750 setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
1751 setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
1755 if (Subtarget->isTargetWin64()) {
1756 setOperationAction(ISD::SDIV, MVT::i128, Custom);
1757 setOperationAction(ISD::UDIV, MVT::i128, Custom);
1758 setOperationAction(ISD::SREM, MVT::i128, Custom);
1759 setOperationAction(ISD::UREM, MVT::i128, Custom);
1760 setOperationAction(ISD::SDIVREM, MVT::i128, Custom);
1761 setOperationAction(ISD::UDIVREM, MVT::i128, Custom);
1764 // We have target-specific dag combine patterns for the following nodes:
1765 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
1766 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
1767 setTargetDAGCombine(ISD::BITCAST);
1768 setTargetDAGCombine(ISD::VSELECT);
1769 setTargetDAGCombine(ISD::SELECT);
1770 setTargetDAGCombine(ISD::SHL);
1771 setTargetDAGCombine(ISD::SRA);
1772 setTargetDAGCombine(ISD::SRL);
1773 setTargetDAGCombine(ISD::OR);
1774 setTargetDAGCombine(ISD::AND);
1775 setTargetDAGCombine(ISD::ADD);
1776 setTargetDAGCombine(ISD::FADD);
1777 setTargetDAGCombine(ISD::FSUB);
1778 setTargetDAGCombine(ISD::FNEG);
1779 setTargetDAGCombine(ISD::FMA);
1780 setTargetDAGCombine(ISD::SUB);
1781 setTargetDAGCombine(ISD::LOAD);
1782 setTargetDAGCombine(ISD::MLOAD);
1783 setTargetDAGCombine(ISD::STORE);
1784 setTargetDAGCombine(ISD::MSTORE);
1785 setTargetDAGCombine(ISD::TRUNCATE);
1786 setTargetDAGCombine(ISD::ZERO_EXTEND);
1787 setTargetDAGCombine(ISD::ANY_EXTEND);
1788 setTargetDAGCombine(ISD::SIGN_EXTEND);
1789 setTargetDAGCombine(ISD::SIGN_EXTEND_INREG);
1790 setTargetDAGCombine(ISD::SINT_TO_FP);
1791 setTargetDAGCombine(ISD::UINT_TO_FP);
1792 setTargetDAGCombine(ISD::SETCC);
1793 setTargetDAGCombine(ISD::BUILD_VECTOR);
1794 setTargetDAGCombine(ISD::MUL);
1795 setTargetDAGCombine(ISD::XOR);
1797 computeRegisterProperties(Subtarget->getRegisterInfo());
1799 MaxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
1800 MaxStoresPerMemsetOptSize = 8;
1801 MaxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores
1802 MaxStoresPerMemcpyOptSize = 4;
1803 MaxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores
1804 MaxStoresPerMemmoveOptSize = 4;
1805 setPrefLoopAlignment(4); // 2^4 bytes.
1807 // A predictable cmov does not hurt on an in-order CPU.
1808 // FIXME: Use a CPU attribute to trigger this, not a CPU model.
1809 PredictableSelectIsExpensive = !Subtarget->isAtom();
1810 EnableExtLdPromotion = true;
1811 setPrefFunctionAlignment(4); // 2^4 bytes.
1813 verifyIntrinsicTables();
1816 // This has so far only been implemented for 64-bit MachO.
1817 bool X86TargetLowering::useLoadStackGuardNode() const {
1818 return Subtarget->isTargetMachO() && Subtarget->is64Bit();
1821 TargetLoweringBase::LegalizeTypeAction
1822 X86TargetLowering::getPreferredVectorAction(EVT VT) const {
1823 if (ExperimentalVectorWideningLegalization &&
1824 VT.getVectorNumElements() != 1 &&
1825 VT.getVectorElementType().getSimpleVT() != MVT::i1)
1826 return TypeWidenVector;
1828 return TargetLoweringBase::getPreferredVectorAction(VT);
1831 EVT X86TargetLowering::getSetCCResultType(const DataLayout &DL, LLVMContext &,
1834 return Subtarget->hasAVX512() ? MVT::i1: MVT::i8;
1836 if (VT.isSimple()) {
1837 MVT VVT = VT.getSimpleVT();
1838 const unsigned NumElts = VVT.getVectorNumElements();
1839 const MVT EltVT = VVT.getVectorElementType();
1840 if (VVT.is512BitVector()) {
1841 if (Subtarget->hasAVX512())
1842 if (EltVT == MVT::i32 || EltVT == MVT::i64 ||
1843 EltVT == MVT::f32 || EltVT == MVT::f64)
1845 case 8: return MVT::v8i1;
1846 case 16: return MVT::v16i1;
1848 if (Subtarget->hasBWI())
1849 if (EltVT == MVT::i8 || EltVT == MVT::i16)
1851 case 32: return MVT::v32i1;
1852 case 64: return MVT::v64i1;
1856 if (VVT.is256BitVector() || VVT.is128BitVector()) {
1857 if (Subtarget->hasVLX())
1858 if (EltVT == MVT::i32 || EltVT == MVT::i64 ||
1859 EltVT == MVT::f32 || EltVT == MVT::f64)
1861 case 2: return MVT::v2i1;
1862 case 4: return MVT::v4i1;
1863 case 8: return MVT::v8i1;
1865 if (Subtarget->hasBWI() && Subtarget->hasVLX())
1866 if (EltVT == MVT::i8 || EltVT == MVT::i16)
1868 case 8: return MVT::v8i1;
1869 case 16: return MVT::v16i1;
1870 case 32: return MVT::v32i1;
1875 return VT.changeVectorElementTypeToInteger();
1878 /// Helper for getByValTypeAlignment to determine
1879 /// the desired ByVal argument alignment.
1880 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) {
1883 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1884 if (VTy->getBitWidth() == 128)
1886 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1887 unsigned EltAlign = 0;
1888 getMaxByValAlign(ATy->getElementType(), EltAlign);
1889 if (EltAlign > MaxAlign)
1890 MaxAlign = EltAlign;
1891 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
1892 for (auto *EltTy : STy->elements()) {
1893 unsigned EltAlign = 0;
1894 getMaxByValAlign(EltTy, EltAlign);
1895 if (EltAlign > MaxAlign)
1896 MaxAlign = EltAlign;
1903 /// Return the desired alignment for ByVal aggregate
1904 /// function arguments in the caller parameter area. For X86, aggregates
1905 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
1906 /// are at 4-byte boundaries.
1907 unsigned X86TargetLowering::getByValTypeAlignment(Type *Ty,
1908 const DataLayout &DL) const {
1909 if (Subtarget->is64Bit()) {
1910 // Max of 8 and alignment of type.
1911 unsigned TyAlign = DL.getABITypeAlignment(Ty);
1918 if (Subtarget->hasSSE1())
1919 getMaxByValAlign(Ty, Align);
1923 /// Returns the target specific optimal type for load
1924 /// and store operations as a result of memset, memcpy, and memmove
1925 /// lowering. If DstAlign is zero that means it's safe to destination
1926 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
1927 /// means there isn't a need to check it against alignment requirement,
1928 /// probably because the source does not need to be loaded. If 'IsMemset' is
1929 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
1930 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
1931 /// source is constant so it does not need to be loaded.
1932 /// It returns EVT::Other if the type should be determined using generic
1933 /// target-independent logic.
1935 X86TargetLowering::getOptimalMemOpType(uint64_t Size,
1936 unsigned DstAlign, unsigned SrcAlign,
1937 bool IsMemset, bool ZeroMemset,
1939 MachineFunction &MF) const {
1940 const Function *F = MF.getFunction();
1941 if ((!IsMemset || ZeroMemset) &&
1942 !F->hasFnAttribute(Attribute::NoImplicitFloat)) {
1944 (!Subtarget->isUnalignedMem16Slow() ||
1945 ((DstAlign == 0 || DstAlign >= 16) &&
1946 (SrcAlign == 0 || SrcAlign >= 16)))) {
1948 // FIXME: Check if unaligned 32-byte accesses are slow.
1949 if (Subtarget->hasInt256())
1951 if (Subtarget->hasFp256())
1954 if (Subtarget->hasSSE2())
1956 if (Subtarget->hasSSE1())
1958 } else if (!MemcpyStrSrc && Size >= 8 &&
1959 !Subtarget->is64Bit() &&
1960 Subtarget->hasSSE2()) {
1961 // Do not use f64 to lower memcpy if source is string constant. It's
1962 // better to use i32 to avoid the loads.
1966 // This is a compromise. If we reach here, unaligned accesses may be slow on
1967 // this target. However, creating smaller, aligned accesses could be even
1968 // slower and would certainly be a lot more code.
1969 if (Subtarget->is64Bit() && Size >= 8)
1974 bool X86TargetLowering::isSafeMemOpType(MVT VT) const {
1976 return X86ScalarSSEf32;
1977 else if (VT == MVT::f64)
1978 return X86ScalarSSEf64;
1983 X86TargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
1988 switch (VT.getSizeInBits()) {
1990 // 8-byte and under are always assumed to be fast.
1994 *Fast = !Subtarget->isUnalignedMem16Slow();
1997 *Fast = !Subtarget->isUnalignedMem32Slow();
1999 // TODO: What about AVX-512 (512-bit) accesses?
2002 // Misaligned accesses of any size are always allowed.
2006 /// Return the entry encoding for a jump table in the
2007 /// current function. The returned value is a member of the
2008 /// MachineJumpTableInfo::JTEntryKind enum.
2009 unsigned X86TargetLowering::getJumpTableEncoding() const {
2010 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
2012 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
2013 Subtarget->isPICStyleGOT())
2014 return MachineJumpTableInfo::EK_Custom32;
2016 // Otherwise, use the normal jump table encoding heuristics.
2017 return TargetLowering::getJumpTableEncoding();
2020 bool X86TargetLowering::useSoftFloat() const {
2021 return Subtarget->useSoftFloat();
2025 X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
2026 const MachineBasicBlock *MBB,
2027 unsigned uid,MCContext &Ctx) const{
2028 assert(MBB->getParent()->getTarget().getRelocationModel() == Reloc::PIC_ &&
2029 Subtarget->isPICStyleGOT());
2030 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
2032 return MCSymbolRefExpr::create(MBB->getSymbol(),
2033 MCSymbolRefExpr::VK_GOTOFF, Ctx);
2036 /// Returns relocation base for the given PIC jumptable.
2037 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
2038 SelectionDAG &DAG) const {
2039 if (!Subtarget->is64Bit())
2040 // This doesn't have SDLoc associated with it, but is not really the
2041 // same as a Register.
2042 return DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(),
2043 getPointerTy(DAG.getDataLayout()));
2047 /// This returns the relocation base for the given PIC jumptable,
2048 /// the same as getPICJumpTableRelocBase, but as an MCExpr.
2049 const MCExpr *X86TargetLowering::
2050 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
2051 MCContext &Ctx) const {
2052 // X86-64 uses RIP relative addressing based on the jump table label.
2053 if (Subtarget->isPICStyleRIPRel())
2054 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
2056 // Otherwise, the reference is relative to the PIC base.
2057 return MCSymbolRefExpr::create(MF->getPICBaseSymbol(), Ctx);
2060 std::pair<const TargetRegisterClass *, uint8_t>
2061 X86TargetLowering::findRepresentativeClass(const TargetRegisterInfo *TRI,
2063 const TargetRegisterClass *RRC = nullptr;
2065 switch (VT.SimpleTy) {
2067 return TargetLowering::findRepresentativeClass(TRI, VT);
2068 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
2069 RRC = Subtarget->is64Bit() ? &X86::GR64RegClass : &X86::GR32RegClass;
2072 RRC = &X86::VR64RegClass;
2074 case MVT::f32: case MVT::f64:
2075 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
2076 case MVT::v4f32: case MVT::v2f64:
2077 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32:
2079 RRC = &X86::VR128RegClass;
2082 return std::make_pair(RRC, Cost);
2085 bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace,
2086 unsigned &Offset) const {
2087 if (!Subtarget->isTargetLinux())
2090 if (Subtarget->is64Bit()) {
2091 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs:
2093 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
2105 Value *X86TargetLowering::getSafeStackPointerLocation(IRBuilder<> &IRB) const {
2106 if (!Subtarget->isTargetAndroid())
2107 return TargetLowering::getSafeStackPointerLocation(IRB);
2109 // Android provides a fixed TLS slot for the SafeStack pointer. See the
2110 // definition of TLS_SLOT_SAFESTACK in
2111 // https://android.googlesource.com/platform/bionic/+/master/libc/private/bionic_tls.h
2112 unsigned AddressSpace, Offset;
2113 if (Subtarget->is64Bit()) {
2114 // %fs:0x48, unless we're using a Kernel code model, in which case it's %gs:
2116 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
2126 return ConstantExpr::getIntToPtr(
2127 ConstantInt::get(Type::getInt32Ty(IRB.getContext()), Offset),
2128 Type::getInt8PtrTy(IRB.getContext())->getPointerTo(AddressSpace));
2131 bool X86TargetLowering::isNoopAddrSpaceCast(unsigned SrcAS,
2132 unsigned DestAS) const {
2133 assert(SrcAS != DestAS && "Expected different address spaces!");
2135 return SrcAS < 256 && DestAS < 256;
2138 //===----------------------------------------------------------------------===//
2139 // Return Value Calling Convention Implementation
2140 //===----------------------------------------------------------------------===//
2142 #include "X86GenCallingConv.inc"
2144 bool X86TargetLowering::CanLowerReturn(
2145 CallingConv::ID CallConv, MachineFunction &MF, bool isVarArg,
2146 const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context) const {
2147 SmallVector<CCValAssign, 16> RVLocs;
2148 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
2149 return CCInfo.CheckReturn(Outs, RetCC_X86);
2152 const MCPhysReg *X86TargetLowering::getScratchRegisters(CallingConv::ID) const {
2153 static const MCPhysReg ScratchRegs[] = { X86::R11, 0 };
2158 X86TargetLowering::LowerReturn(SDValue Chain,
2159 CallingConv::ID CallConv, bool isVarArg,
2160 const SmallVectorImpl<ISD::OutputArg> &Outs,
2161 const SmallVectorImpl<SDValue> &OutVals,
2162 SDLoc dl, SelectionDAG &DAG) const {
2163 MachineFunction &MF = DAG.getMachineFunction();
2164 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2166 SmallVector<CCValAssign, 16> RVLocs;
2167 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, *DAG.getContext());
2168 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
2171 SmallVector<SDValue, 6> RetOps;
2172 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
2173 // Operand #1 = Bytes To Pop
2174 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(), dl,
2177 // Copy the result values into the output registers.
2178 for (unsigned i = 0; i != RVLocs.size(); ++i) {
2179 CCValAssign &VA = RVLocs[i];
2180 assert(VA.isRegLoc() && "Can only return in registers!");
2181 SDValue ValToCopy = OutVals[i];
2182 EVT ValVT = ValToCopy.getValueType();
2184 // Promote values to the appropriate types.
2185 if (VA.getLocInfo() == CCValAssign::SExt)
2186 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy);
2187 else if (VA.getLocInfo() == CCValAssign::ZExt)
2188 ValToCopy = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ValToCopy);
2189 else if (VA.getLocInfo() == CCValAssign::AExt) {
2190 if (ValVT.isVector() && ValVT.getVectorElementType() == MVT::i1)
2191 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy);
2193 ValToCopy = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ValToCopy);
2195 else if (VA.getLocInfo() == CCValAssign::BCvt)
2196 ValToCopy = DAG.getBitcast(VA.getLocVT(), ValToCopy);
2198 assert(VA.getLocInfo() != CCValAssign::FPExt &&
2199 "Unexpected FP-extend for return value.");
2201 // If this is x86-64, and we disabled SSE, we can't return FP values,
2202 // or SSE or MMX vectors.
2203 if ((ValVT == MVT::f32 || ValVT == MVT::f64 ||
2204 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) &&
2205 (Subtarget->is64Bit() && !Subtarget->hasSSE1())) {
2206 report_fatal_error("SSE register return with SSE disabled");
2208 // Likewise we can't return F64 values with SSE1 only. gcc does so, but
2209 // llvm-gcc has never done it right and no one has noticed, so this
2210 // should be OK for now.
2211 if (ValVT == MVT::f64 &&
2212 (Subtarget->is64Bit() && !Subtarget->hasSSE2()))
2213 report_fatal_error("SSE2 register return with SSE2 disabled");
2215 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
2216 // the RET instruction and handled by the FP Stackifier.
2217 if (VA.getLocReg() == X86::FP0 ||
2218 VA.getLocReg() == X86::FP1) {
2219 // If this is a copy from an xmm register to ST(0), use an FPExtend to
2220 // change the value to the FP stack register class.
2221 if (isScalarFPTypeInSSEReg(VA.getValVT()))
2222 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
2223 RetOps.push_back(ValToCopy);
2224 // Don't emit a copytoreg.
2228 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
2229 // which is returned in RAX / RDX.
2230 if (Subtarget->is64Bit()) {
2231 if (ValVT == MVT::x86mmx) {
2232 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
2233 ValToCopy = DAG.getBitcast(MVT::i64, ValToCopy);
2234 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
2236 // If we don't have SSE2 available, convert to v4f32 so the generated
2237 // register is legal.
2238 if (!Subtarget->hasSSE2())
2239 ValToCopy = DAG.getBitcast(MVT::v4f32, ValToCopy);
2244 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
2245 Flag = Chain.getValue(1);
2246 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2249 // All x86 ABIs require that for returning structs by value we copy
2250 // the sret argument into %rax/%eax (depending on ABI) for the return.
2251 // We saved the argument into a virtual register in the entry block,
2252 // so now we copy the value out and into %rax/%eax.
2254 // Checking Function.hasStructRetAttr() here is insufficient because the IR
2255 // may not have an explicit sret argument. If FuncInfo.CanLowerReturn is
2256 // false, then an sret argument may be implicitly inserted in the SelDAG. In
2257 // either case FuncInfo->setSRetReturnReg() will have been called.
2258 if (unsigned SRetReg = FuncInfo->getSRetReturnReg()) {
2259 SDValue Val = DAG.getCopyFromReg(Chain, dl, SRetReg,
2260 getPointerTy(MF.getDataLayout()));
2263 = (Subtarget->is64Bit() && !Subtarget->isTarget64BitILP32()) ?
2264 X86::RAX : X86::EAX;
2265 Chain = DAG.getCopyToReg(Chain, dl, RetValReg, Val, Flag);
2266 Flag = Chain.getValue(1);
2268 // RAX/EAX now acts like a return value.
2270 DAG.getRegister(RetValReg, getPointerTy(DAG.getDataLayout())));
2273 RetOps[0] = Chain; // Update chain.
2275 // Add the flag if we have it.
2277 RetOps.push_back(Flag);
2279 return DAG.getNode(X86ISD::RET_FLAG, dl, MVT::Other, RetOps);
2282 bool X86TargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
2283 if (N->getNumValues() != 1)
2285 if (!N->hasNUsesOfValue(1, 0))
2288 SDValue TCChain = Chain;
2289 SDNode *Copy = *N->use_begin();
2290 if (Copy->getOpcode() == ISD::CopyToReg) {
2291 // If the copy has a glue operand, we conservatively assume it isn't safe to
2292 // perform a tail call.
2293 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
2295 TCChain = Copy->getOperand(0);
2296 } else if (Copy->getOpcode() != ISD::FP_EXTEND)
2299 bool HasRet = false;
2300 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
2302 if (UI->getOpcode() != X86ISD::RET_FLAG)
2304 // If we are returning more than one value, we can definitely
2305 // not make a tail call see PR19530
2306 if (UI->getNumOperands() > 4)
2308 if (UI->getNumOperands() == 4 &&
2309 UI->getOperand(UI->getNumOperands()-1).getValueType() != MVT::Glue)
2322 X86TargetLowering::getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT,
2323 ISD::NodeType ExtendKind) const {
2325 // TODO: Is this also valid on 32-bit?
2326 if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND)
2327 ReturnMVT = MVT::i8;
2329 ReturnMVT = MVT::i32;
2331 EVT MinVT = getRegisterType(Context, ReturnMVT);
2332 return VT.bitsLT(MinVT) ? MinVT : VT;
2335 /// Lower the result values of a call into the
2336 /// appropriate copies out of appropriate physical registers.
2339 X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
2340 CallingConv::ID CallConv, bool isVarArg,
2341 const SmallVectorImpl<ISD::InputArg> &Ins,
2342 SDLoc dl, SelectionDAG &DAG,
2343 SmallVectorImpl<SDValue> &InVals) const {
2345 // Assign locations to each value returned by this call.
2346 SmallVector<CCValAssign, 16> RVLocs;
2347 bool Is64Bit = Subtarget->is64Bit();
2348 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
2350 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
2352 // Copy all of the result registers out of their specified physreg.
2353 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
2354 CCValAssign &VA = RVLocs[i];
2355 EVT CopyVT = VA.getLocVT();
2357 // If this is x86-64, and we disabled SSE, we can't return FP values
2358 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
2359 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) {
2360 report_fatal_error("SSE register return with SSE disabled");
2363 // If we prefer to use the value in xmm registers, copy it out as f80 and
2364 // use a truncate to move it from fp stack reg to xmm reg.
2365 bool RoundAfterCopy = false;
2366 if ((VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1) &&
2367 isScalarFPTypeInSSEReg(VA.getValVT())) {
2369 RoundAfterCopy = (CopyVT != VA.getLocVT());
2372 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
2373 CopyVT, InFlag).getValue(1);
2374 SDValue Val = Chain.getValue(0);
2377 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
2378 // This truncation won't change the value.
2379 DAG.getIntPtrConstant(1, dl));
2381 if (VA.isExtInLoc() && VA.getValVT().getScalarType() == MVT::i1)
2382 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
2384 InFlag = Chain.getValue(2);
2385 InVals.push_back(Val);
2391 //===----------------------------------------------------------------------===//
2392 // C & StdCall & Fast Calling Convention implementation
2393 //===----------------------------------------------------------------------===//
2394 // StdCall calling convention seems to be standard for many Windows' API
2395 // routines and around. It differs from C calling convention just a little:
2396 // callee should clean up the stack, not caller. Symbols should be also
2397 // decorated in some fancy way :) It doesn't support any vector arguments.
2398 // For info on fast calling convention see Fast Calling Convention (tail call)
2399 // implementation LowerX86_32FastCCCallTo.
2401 /// CallIsStructReturn - Determines whether a call uses struct return
2403 enum StructReturnType {
2408 static StructReturnType
2409 callIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
2411 return NotStructReturn;
2413 const ISD::ArgFlagsTy &Flags = Outs[0].Flags;
2414 if (!Flags.isSRet())
2415 return NotStructReturn;
2416 if (Flags.isInReg())
2417 return RegStructReturn;
2418 return StackStructReturn;
2421 /// Determines whether a function uses struct return semantics.
2422 static StructReturnType
2423 argsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
2425 return NotStructReturn;
2427 const ISD::ArgFlagsTy &Flags = Ins[0].Flags;
2428 if (!Flags.isSRet())
2429 return NotStructReturn;
2430 if (Flags.isInReg())
2431 return RegStructReturn;
2432 return StackStructReturn;
2435 /// Make a copy of an aggregate at address specified by "Src" to address
2436 /// "Dst" with size and alignment information specified by the specific
2437 /// parameter attribute. The copy will be passed as a byval function parameter.
2439 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
2440 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
2442 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), dl, MVT::i32);
2444 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
2445 /*isVolatile*/false, /*AlwaysInline=*/true,
2446 /*isTailCall*/false,
2447 MachinePointerInfo(), MachinePointerInfo());
2450 /// Return true if the calling convention is one that we can guarantee TCO for.
2451 static bool canGuaranteeTCO(CallingConv::ID CC) {
2452 return (CC == CallingConv::Fast || CC == CallingConv::GHC ||
2453 CC == CallingConv::HiPE || CC == CallingConv::HHVM);
2456 /// Return true if we might ever do TCO for calls with this calling convention.
2457 static bool mayTailCallThisCC(CallingConv::ID CC) {
2459 // C calling conventions:
2460 case CallingConv::C:
2461 case CallingConv::X86_64_Win64:
2462 case CallingConv::X86_64_SysV:
2463 // Callee pop conventions:
2464 case CallingConv::X86_ThisCall:
2465 case CallingConv::X86_StdCall:
2466 case CallingConv::X86_VectorCall:
2467 case CallingConv::X86_FastCall:
2470 return canGuaranteeTCO(CC);
2474 /// Return true if the function is being made into a tailcall target by
2475 /// changing its ABI.
2476 static bool shouldGuaranteeTCO(CallingConv::ID CC, bool GuaranteedTailCallOpt) {
2477 return GuaranteedTailCallOpt && canGuaranteeTCO(CC);
2480 bool X86TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
2482 CI->getParent()->getParent()->getFnAttribute("disable-tail-calls");
2483 if (!CI->isTailCall() || Attr.getValueAsString() == "true")
2487 CallingConv::ID CalleeCC = CS.getCallingConv();
2488 if (!mayTailCallThisCC(CalleeCC))
2495 X86TargetLowering::LowerMemArgument(SDValue Chain,
2496 CallingConv::ID CallConv,
2497 const SmallVectorImpl<ISD::InputArg> &Ins,
2498 SDLoc dl, SelectionDAG &DAG,
2499 const CCValAssign &VA,
2500 MachineFrameInfo *MFI,
2502 // Create the nodes corresponding to a load from this parameter slot.
2503 ISD::ArgFlagsTy Flags = Ins[i].Flags;
2504 bool AlwaysUseMutable = shouldGuaranteeTCO(
2505 CallConv, DAG.getTarget().Options.GuaranteedTailCallOpt);
2506 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
2509 // If value is passed by pointer we have address passed instead of the value
2511 bool ExtendedInMem = VA.isExtInLoc() &&
2512 VA.getValVT().getScalarType() == MVT::i1;
2514 if (VA.getLocInfo() == CCValAssign::Indirect || ExtendedInMem)
2515 ValVT = VA.getLocVT();
2517 ValVT = VA.getValVT();
2519 // FIXME: For now, all byval parameter objects are marked mutable. This can be
2520 // changed with more analysis.
2521 // In case of tail call optimization mark all arguments mutable. Since they
2522 // could be overwritten by lowering of arguments in case of a tail call.
2523 if (Flags.isByVal()) {
2524 unsigned Bytes = Flags.getByValSize();
2525 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects.
2526 int FI = MFI->CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable);
2527 return DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
2529 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
2530 VA.getLocMemOffset(), isImmutable);
2531 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
2532 SDValue Val = DAG.getLoad(
2533 ValVT, dl, Chain, FIN,
2534 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI), false,
2536 return ExtendedInMem ?
2537 DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val) : Val;
2541 // FIXME: Get this from tablegen.
2542 static ArrayRef<MCPhysReg> get64BitArgumentGPRs(CallingConv::ID CallConv,
2543 const X86Subtarget *Subtarget) {
2544 assert(Subtarget->is64Bit());
2546 if (Subtarget->isCallingConvWin64(CallConv)) {
2547 static const MCPhysReg GPR64ArgRegsWin64[] = {
2548 X86::RCX, X86::RDX, X86::R8, X86::R9
2550 return makeArrayRef(std::begin(GPR64ArgRegsWin64), std::end(GPR64ArgRegsWin64));
2553 static const MCPhysReg GPR64ArgRegs64Bit[] = {
2554 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
2556 return makeArrayRef(std::begin(GPR64ArgRegs64Bit), std::end(GPR64ArgRegs64Bit));
2559 // FIXME: Get this from tablegen.
2560 static ArrayRef<MCPhysReg> get64BitArgumentXMMs(MachineFunction &MF,
2561 CallingConv::ID CallConv,
2562 const X86Subtarget *Subtarget) {
2563 assert(Subtarget->is64Bit());
2564 if (Subtarget->isCallingConvWin64(CallConv)) {
2565 // The XMM registers which might contain var arg parameters are shadowed
2566 // in their paired GPR. So we only need to save the GPR to their home
2568 // TODO: __vectorcall will change this.
2572 const Function *Fn = MF.getFunction();
2573 bool NoImplicitFloatOps = Fn->hasFnAttribute(Attribute::NoImplicitFloat);
2574 bool isSoftFloat = Subtarget->useSoftFloat();
2575 assert(!(isSoftFloat && NoImplicitFloatOps) &&
2576 "SSE register cannot be used when SSE is disabled!");
2577 if (isSoftFloat || NoImplicitFloatOps || !Subtarget->hasSSE1())
2578 // Kernel mode asks for SSE to be disabled, so there are no XMM argument
2582 static const MCPhysReg XMMArgRegs64Bit[] = {
2583 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2584 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2586 return makeArrayRef(std::begin(XMMArgRegs64Bit), std::end(XMMArgRegs64Bit));
2589 SDValue X86TargetLowering::LowerFormalArguments(
2590 SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
2591 const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc dl, SelectionDAG &DAG,
2592 SmallVectorImpl<SDValue> &InVals) const {
2593 MachineFunction &MF = DAG.getMachineFunction();
2594 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2595 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
2597 const Function* Fn = MF.getFunction();
2598 if (Fn->hasExternalLinkage() &&
2599 Subtarget->isTargetCygMing() &&
2600 Fn->getName() == "main")
2601 FuncInfo->setForceFramePointer(true);
2603 MachineFrameInfo *MFI = MF.getFrameInfo();
2604 bool Is64Bit = Subtarget->is64Bit();
2605 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2607 assert(!(isVarArg && canGuaranteeTCO(CallConv)) &&
2608 "Var args not supported with calling convention fastcc, ghc or hipe");
2610 // Assign locations to all of the incoming arguments.
2611 SmallVector<CCValAssign, 16> ArgLocs;
2612 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
2614 // Allocate shadow area for Win64
2616 CCInfo.AllocateStack(32, 8);
2618 CCInfo.AnalyzeFormalArguments(Ins, CC_X86);
2620 unsigned LastVal = ~0U;
2622 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2623 CCValAssign &VA = ArgLocs[i];
2624 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
2626 assert(VA.getValNo() != LastVal &&
2627 "Don't support value assigned to multiple locs yet");
2629 LastVal = VA.getValNo();
2631 if (VA.isRegLoc()) {
2632 EVT RegVT = VA.getLocVT();
2633 const TargetRegisterClass *RC;
2634 if (RegVT == MVT::i32)
2635 RC = &X86::GR32RegClass;
2636 else if (Is64Bit && RegVT == MVT::i64)
2637 RC = &X86::GR64RegClass;
2638 else if (RegVT == MVT::f32)
2639 RC = &X86::FR32RegClass;
2640 else if (RegVT == MVT::f64)
2641 RC = &X86::FR64RegClass;
2642 else if (RegVT.is512BitVector())
2643 RC = &X86::VR512RegClass;
2644 else if (RegVT.is256BitVector())
2645 RC = &X86::VR256RegClass;
2646 else if (RegVT.is128BitVector())
2647 RC = &X86::VR128RegClass;
2648 else if (RegVT == MVT::x86mmx)
2649 RC = &X86::VR64RegClass;
2650 else if (RegVT == MVT::i1)
2651 RC = &X86::VK1RegClass;
2652 else if (RegVT == MVT::v8i1)
2653 RC = &X86::VK8RegClass;
2654 else if (RegVT == MVT::v16i1)
2655 RC = &X86::VK16RegClass;
2656 else if (RegVT == MVT::v32i1)
2657 RC = &X86::VK32RegClass;
2658 else if (RegVT == MVT::v64i1)
2659 RC = &X86::VK64RegClass;
2661 llvm_unreachable("Unknown argument type!");
2663 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2664 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
2666 // If this is an 8 or 16-bit value, it is really passed promoted to 32
2667 // bits. Insert an assert[sz]ext to capture this, then truncate to the
2669 if (VA.getLocInfo() == CCValAssign::SExt)
2670 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
2671 DAG.getValueType(VA.getValVT()));
2672 else if (VA.getLocInfo() == CCValAssign::ZExt)
2673 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
2674 DAG.getValueType(VA.getValVT()));
2675 else if (VA.getLocInfo() == CCValAssign::BCvt)
2676 ArgValue = DAG.getBitcast(VA.getValVT(), ArgValue);
2678 if (VA.isExtInLoc()) {
2679 // Handle MMX values passed in XMM regs.
2680 if (RegVT.isVector() && VA.getValVT().getScalarType() != MVT::i1)
2681 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(), ArgValue);
2683 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
2686 assert(VA.isMemLoc());
2687 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
2690 // If value is passed via pointer - do a load.
2691 if (VA.getLocInfo() == CCValAssign::Indirect)
2692 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue,
2693 MachinePointerInfo(), false, false, false, 0);
2695 InVals.push_back(ArgValue);
2698 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2699 // All x86 ABIs require that for returning structs by value we copy the
2700 // sret argument into %rax/%eax (depending on ABI) for the return. Save
2701 // the argument into a virtual register so that we can access it from the
2703 if (Ins[i].Flags.isSRet()) {
2704 unsigned Reg = FuncInfo->getSRetReturnReg();
2706 MVT PtrTy = getPointerTy(DAG.getDataLayout());
2707 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(PtrTy));
2708 FuncInfo->setSRetReturnReg(Reg);
2710 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[i]);
2711 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
2716 unsigned StackSize = CCInfo.getNextStackOffset();
2717 // Align stack specially for tail calls.
2718 if (shouldGuaranteeTCO(CallConv,
2719 MF.getTarget().Options.GuaranteedTailCallOpt))
2720 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
2722 // If the function takes variable number of arguments, make a frame index for
2723 // the start of the first vararg value... for expansion of llvm.va_start. We
2724 // can skip this if there are no va_start calls.
2725 if (MFI->hasVAStart() &&
2726 (Is64Bit || (CallConv != CallingConv::X86_FastCall &&
2727 CallConv != CallingConv::X86_ThisCall))) {
2728 FuncInfo->setVarArgsFrameIndex(
2729 MFI->CreateFixedObject(1, StackSize, true));
2732 // Figure out if XMM registers are in use.
2733 assert(!(Subtarget->useSoftFloat() &&
2734 Fn->hasFnAttribute(Attribute::NoImplicitFloat)) &&
2735 "SSE register cannot be used when SSE is disabled!");
2737 // 64-bit calling conventions support varargs and register parameters, so we
2738 // have to do extra work to spill them in the prologue.
2739 if (Is64Bit && isVarArg && MFI->hasVAStart()) {
2740 // Find the first unallocated argument registers.
2741 ArrayRef<MCPhysReg> ArgGPRs = get64BitArgumentGPRs(CallConv, Subtarget);
2742 ArrayRef<MCPhysReg> ArgXMMs = get64BitArgumentXMMs(MF, CallConv, Subtarget);
2743 unsigned NumIntRegs = CCInfo.getFirstUnallocated(ArgGPRs);
2744 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(ArgXMMs);
2745 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) &&
2746 "SSE register cannot be used when SSE is disabled!");
2748 // Gather all the live in physical registers.
2749 SmallVector<SDValue, 6> LiveGPRs;
2750 SmallVector<SDValue, 8> LiveXMMRegs;
2752 for (MCPhysReg Reg : ArgGPRs.slice(NumIntRegs)) {
2753 unsigned GPR = MF.addLiveIn(Reg, &X86::GR64RegClass);
2755 DAG.getCopyFromReg(Chain, dl, GPR, MVT::i64));
2757 if (!ArgXMMs.empty()) {
2758 unsigned AL = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
2759 ALVal = DAG.getCopyFromReg(Chain, dl, AL, MVT::i8);
2760 for (MCPhysReg Reg : ArgXMMs.slice(NumXMMRegs)) {
2761 unsigned XMMReg = MF.addLiveIn(Reg, &X86::VR128RegClass);
2762 LiveXMMRegs.push_back(
2763 DAG.getCopyFromReg(Chain, dl, XMMReg, MVT::v4f32));
2768 // Get to the caller-allocated home save location. Add 8 to account
2769 // for the return address.
2770 int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
2771 FuncInfo->setRegSaveFrameIndex(
2772 MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false));
2773 // Fixup to set vararg frame on shadow area (4 x i64).
2775 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex());
2777 // For X86-64, if there are vararg parameters that are passed via
2778 // registers, then we must store them to their spots on the stack so
2779 // they may be loaded by deferencing the result of va_next.
2780 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8);
2781 FuncInfo->setVarArgsFPOffset(ArgGPRs.size() * 8 + NumXMMRegs * 16);
2782 FuncInfo->setRegSaveFrameIndex(MFI->CreateStackObject(
2783 ArgGPRs.size() * 8 + ArgXMMs.size() * 16, 16, false));
2786 // Store the integer parameter registers.
2787 SmallVector<SDValue, 8> MemOps;
2788 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
2789 getPointerTy(DAG.getDataLayout()));
2790 unsigned Offset = FuncInfo->getVarArgsGPOffset();
2791 for (SDValue Val : LiveGPRs) {
2792 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(DAG.getDataLayout()),
2793 RSFIN, DAG.getIntPtrConstant(Offset, dl));
2795 DAG.getStore(Val.getValue(1), dl, Val, FIN,
2796 MachinePointerInfo::getFixedStack(
2797 DAG.getMachineFunction(),
2798 FuncInfo->getRegSaveFrameIndex(), Offset),
2800 MemOps.push_back(Store);
2804 if (!ArgXMMs.empty() && NumXMMRegs != ArgXMMs.size()) {
2805 // Now store the XMM (fp + vector) parameter registers.
2806 SmallVector<SDValue, 12> SaveXMMOps;
2807 SaveXMMOps.push_back(Chain);
2808 SaveXMMOps.push_back(ALVal);
2809 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2810 FuncInfo->getRegSaveFrameIndex(), dl));
2811 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2812 FuncInfo->getVarArgsFPOffset(), dl));
2813 SaveXMMOps.insert(SaveXMMOps.end(), LiveXMMRegs.begin(),
2815 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
2816 MVT::Other, SaveXMMOps));
2819 if (!MemOps.empty())
2820 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
2823 if (isVarArg && MFI->hasMustTailInVarArgFunc()) {
2824 // Find the largest legal vector type.
2825 MVT VecVT = MVT::Other;
2826 // FIXME: Only some x86_32 calling conventions support AVX512.
2827 if (Subtarget->hasAVX512() &&
2828 (Is64Bit || (CallConv == CallingConv::X86_VectorCall ||
2829 CallConv == CallingConv::Intel_OCL_BI)))
2830 VecVT = MVT::v16f32;
2831 else if (Subtarget->hasAVX())
2833 else if (Subtarget->hasSSE2())
2836 // We forward some GPRs and some vector types.
2837 SmallVector<MVT, 2> RegParmTypes;
2838 MVT IntVT = Is64Bit ? MVT::i64 : MVT::i32;
2839 RegParmTypes.push_back(IntVT);
2840 if (VecVT != MVT::Other)
2841 RegParmTypes.push_back(VecVT);
2843 // Compute the set of forwarded registers. The rest are scratch.
2844 SmallVectorImpl<ForwardedRegister> &Forwards =
2845 FuncInfo->getForwardedMustTailRegParms();
2846 CCInfo.analyzeMustTailForwardedRegisters(Forwards, RegParmTypes, CC_X86);
2848 // Conservatively forward AL on x86_64, since it might be used for varargs.
2849 if (Is64Bit && !CCInfo.isAllocated(X86::AL)) {
2850 unsigned ALVReg = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
2851 Forwards.push_back(ForwardedRegister(ALVReg, X86::AL, MVT::i8));
2854 // Copy all forwards from physical to virtual registers.
2855 for (ForwardedRegister &F : Forwards) {
2856 // FIXME: Can we use a less constrained schedule?
2857 SDValue RegVal = DAG.getCopyFromReg(Chain, dl, F.VReg, F.VT);
2858 F.VReg = MF.getRegInfo().createVirtualRegister(getRegClassFor(F.VT));
2859 Chain = DAG.getCopyToReg(Chain, dl, F.VReg, RegVal);
2863 // Some CCs need callee pop.
2864 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2865 MF.getTarget().Options.GuaranteedTailCallOpt)) {
2866 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything.
2868 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing.
2869 // If this is an sret function, the return should pop the hidden pointer.
2870 if (!Is64Bit && !canGuaranteeTCO(CallConv) &&
2871 !Subtarget->getTargetTriple().isOSMSVCRT() &&
2872 argsAreStructReturn(Ins) == StackStructReturn)
2873 FuncInfo->setBytesToPopOnReturn(4);
2877 // RegSaveFrameIndex is X86-64 only.
2878 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
2879 if (CallConv == CallingConv::X86_FastCall ||
2880 CallConv == CallingConv::X86_ThisCall)
2881 // fastcc functions can't have varargs.
2882 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA);
2885 FuncInfo->setArgumentStackSize(StackSize);
2887 if (WinEHFuncInfo *EHInfo = MF.getWinEHFuncInfo()) {
2888 EHPersonality Personality = classifyEHPersonality(Fn->getPersonalityFn());
2889 if (Personality == EHPersonality::CoreCLR) {
2891 // TODO: Add a mechanism to frame lowering that will allow us to indicate
2892 // that we'd prefer this slot be allocated towards the bottom of the frame
2893 // (i.e. near the stack pointer after allocating the frame). Every
2894 // funclet needs a copy of this slot in its (mostly empty) frame, and the
2895 // offset from the bottom of this and each funclet's frame must be the
2896 // same, so the size of funclets' (mostly empty) frames is dictated by
2897 // how far this slot is from the bottom (since they allocate just enough
2898 // space to accomodate holding this slot at the correct offset).
2899 int PSPSymFI = MFI->CreateStackObject(8, 8, /*isSS=*/false);
2900 EHInfo->PSPSymFrameIdx = PSPSymFI;
2908 X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
2909 SDValue StackPtr, SDValue Arg,
2910 SDLoc dl, SelectionDAG &DAG,
2911 const CCValAssign &VA,
2912 ISD::ArgFlagsTy Flags) const {
2913 unsigned LocMemOffset = VA.getLocMemOffset();
2914 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset, dl);
2915 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(DAG.getDataLayout()),
2917 if (Flags.isByVal())
2918 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
2920 return DAG.getStore(
2921 Chain, dl, Arg, PtrOff,
2922 MachinePointerInfo::getStack(DAG.getMachineFunction(), LocMemOffset),
2926 /// Emit a load of return address if tail call
2927 /// optimization is performed and it is required.
2929 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
2930 SDValue &OutRetAddr, SDValue Chain,
2931 bool IsTailCall, bool Is64Bit,
2932 int FPDiff, SDLoc dl) const {
2933 // Adjust the Return address stack slot.
2934 EVT VT = getPointerTy(DAG.getDataLayout());
2935 OutRetAddr = getReturnAddressFrameIndex(DAG);
2937 // Load the "old" Return address.
2938 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(),
2939 false, false, false, 0);
2940 return SDValue(OutRetAddr.getNode(), 1);
2943 /// Emit a store of the return address if tail call
2944 /// optimization is performed and it is required (FPDiff!=0).
2945 static SDValue EmitTailCallStoreRetAddr(SelectionDAG &DAG, MachineFunction &MF,
2946 SDValue Chain, SDValue RetAddrFrIdx,
2947 EVT PtrVT, unsigned SlotSize,
2948 int FPDiff, SDLoc dl) {
2949 // Store the return address to the appropriate stack slot.
2950 if (!FPDiff) return Chain;
2951 // Calculate the new stack slot for the return address.
2952 int NewReturnAddrFI =
2953 MF.getFrameInfo()->CreateFixedObject(SlotSize, (int64_t)FPDiff - SlotSize,
2955 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, PtrVT);
2956 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
2957 MachinePointerInfo::getFixedStack(
2958 DAG.getMachineFunction(), NewReturnAddrFI),
2963 /// Returns a vector_shuffle mask for an movs{s|d}, movd
2964 /// operation of specified width.
2965 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
2967 unsigned NumElems = VT.getVectorNumElements();
2968 SmallVector<int, 8> Mask;
2969 Mask.push_back(NumElems);
2970 for (unsigned i = 1; i != NumElems; ++i)
2972 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
2976 X86TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
2977 SmallVectorImpl<SDValue> &InVals) const {
2978 SelectionDAG &DAG = CLI.DAG;
2980 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
2981 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
2982 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
2983 SDValue Chain = CLI.Chain;
2984 SDValue Callee = CLI.Callee;
2985 CallingConv::ID CallConv = CLI.CallConv;
2986 bool &isTailCall = CLI.IsTailCall;
2987 bool isVarArg = CLI.IsVarArg;
2989 MachineFunction &MF = DAG.getMachineFunction();
2990 bool Is64Bit = Subtarget->is64Bit();
2991 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2992 StructReturnType SR = callIsStructReturn(Outs);
2993 bool IsSibcall = false;
2994 X86MachineFunctionInfo *X86Info = MF.getInfo<X86MachineFunctionInfo>();
2995 auto Attr = MF.getFunction()->getFnAttribute("disable-tail-calls");
2997 if (Attr.getValueAsString() == "true")
3000 if (Subtarget->isPICStyleGOT() &&
3001 !MF.getTarget().Options.GuaranteedTailCallOpt) {
3002 // If we are using a GOT, disable tail calls to external symbols with
3003 // default visibility. Tail calling such a symbol requires using a GOT
3004 // relocation, which forces early binding of the symbol. This breaks code
3005 // that require lazy function symbol resolution. Using musttail or
3006 // GuaranteedTailCallOpt will override this.
3007 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
3008 if (!G || (!G->getGlobal()->hasLocalLinkage() &&
3009 G->getGlobal()->hasDefaultVisibility()))
3013 bool IsMustTail = CLI.CS && CLI.CS->isMustTailCall();
3015 // Force this to be a tail call. The verifier rules are enough to ensure
3016 // that we can lower this successfully without moving the return address
3019 } else if (isTailCall) {
3020 // Check if it's really possible to do a tail call.
3021 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
3022 isVarArg, SR != NotStructReturn,
3023 MF.getFunction()->hasStructRetAttr(), CLI.RetTy,
3024 Outs, OutVals, Ins, DAG);
3026 // Sibcalls are automatically detected tailcalls which do not require
3028 if (!MF.getTarget().Options.GuaranteedTailCallOpt && isTailCall)
3035 assert(!(isVarArg && canGuaranteeTCO(CallConv)) &&
3036 "Var args not supported with calling convention fastcc, ghc or hipe");
3038 // Analyze operands of the call, assigning locations to each operand.
3039 SmallVector<CCValAssign, 16> ArgLocs;
3040 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
3042 // Allocate shadow area for Win64
3044 CCInfo.AllocateStack(32, 8);
3046 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3048 // Get a count of how many bytes are to be pushed on the stack.
3049 unsigned NumBytes = CCInfo.getAlignedCallFrameSize();
3051 // This is a sibcall. The memory operands are available in caller's
3052 // own caller's stack.
3054 else if (MF.getTarget().Options.GuaranteedTailCallOpt &&
3055 canGuaranteeTCO(CallConv))
3056 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
3059 if (isTailCall && !IsSibcall && !IsMustTail) {
3060 // Lower arguments at fp - stackoffset + fpdiff.
3061 unsigned NumBytesCallerPushed = X86Info->getBytesToPopOnReturn();
3063 FPDiff = NumBytesCallerPushed - NumBytes;
3065 // Set the delta of movement of the returnaddr stackslot.
3066 // But only set if delta is greater than previous delta.
3067 if (FPDiff < X86Info->getTCReturnAddrDelta())
3068 X86Info->setTCReturnAddrDelta(FPDiff);
3071 unsigned NumBytesToPush = NumBytes;
3072 unsigned NumBytesToPop = NumBytes;
3074 // If we have an inalloca argument, all stack space has already been allocated
3075 // for us and be right at the top of the stack. We don't support multiple
3076 // arguments passed in memory when using inalloca.
3077 if (!Outs.empty() && Outs.back().Flags.isInAlloca()) {
3079 if (!ArgLocs.back().isMemLoc())
3080 report_fatal_error("cannot use inalloca attribute on a register "
3082 if (ArgLocs.back().getLocMemOffset() != 0)
3083 report_fatal_error("any parameter with the inalloca attribute must be "
3084 "the only memory argument");
3088 Chain = DAG.getCALLSEQ_START(
3089 Chain, DAG.getIntPtrConstant(NumBytesToPush, dl, true), dl);
3091 SDValue RetAddrFrIdx;
3092 // Load return address for tail calls.
3093 if (isTailCall && FPDiff)
3094 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall,
3095 Is64Bit, FPDiff, dl);
3097 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
3098 SmallVector<SDValue, 8> MemOpChains;
3101 // Walk the register/memloc assignments, inserting copies/loads. In the case
3102 // of tail call optimization arguments are handle later.
3103 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
3104 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3105 // Skip inalloca arguments, they have already been written.
3106 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3107 if (Flags.isInAlloca())
3110 CCValAssign &VA = ArgLocs[i];
3111 EVT RegVT = VA.getLocVT();
3112 SDValue Arg = OutVals[i];
3113 bool isByVal = Flags.isByVal();
3115 // Promote the value if needed.
3116 switch (VA.getLocInfo()) {
3117 default: llvm_unreachable("Unknown loc info!");
3118 case CCValAssign::Full: break;
3119 case CCValAssign::SExt:
3120 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
3122 case CCValAssign::ZExt:
3123 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
3125 case CCValAssign::AExt:
3126 if (Arg.getValueType().isVector() &&
3127 Arg.getValueType().getVectorElementType() == MVT::i1)
3128 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
3129 else if (RegVT.is128BitVector()) {
3130 // Special case: passing MMX values in XMM registers.
3131 Arg = DAG.getBitcast(MVT::i64, Arg);
3132 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
3133 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
3135 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
3137 case CCValAssign::BCvt:
3138 Arg = DAG.getBitcast(RegVT, Arg);
3140 case CCValAssign::Indirect: {
3141 // Store the argument.
3142 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
3143 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
3144 Chain = DAG.getStore(
3145 Chain, dl, Arg, SpillSlot,
3146 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI),
3153 if (VA.isRegLoc()) {
3154 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
3155 if (isVarArg && IsWin64) {
3156 // Win64 ABI requires argument XMM reg to be copied to the corresponding
3157 // shadow reg if callee is a varargs function.
3158 unsigned ShadowReg = 0;
3159 switch (VA.getLocReg()) {
3160 case X86::XMM0: ShadowReg = X86::RCX; break;
3161 case X86::XMM1: ShadowReg = X86::RDX; break;
3162 case X86::XMM2: ShadowReg = X86::R8; break;
3163 case X86::XMM3: ShadowReg = X86::R9; break;
3166 RegsToPass.push_back(std::make_pair(ShadowReg, Arg));
3168 } else if (!IsSibcall && (!isTailCall || isByVal)) {
3169 assert(VA.isMemLoc());
3170 if (!StackPtr.getNode())
3171 StackPtr = DAG.getCopyFromReg(Chain, dl, RegInfo->getStackRegister(),
3172 getPointerTy(DAG.getDataLayout()));
3173 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
3174 dl, DAG, VA, Flags));
3178 if (!MemOpChains.empty())
3179 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
3181 if (Subtarget->isPICStyleGOT()) {
3182 // ELF / PIC requires GOT in the EBX register before function calls via PLT
3185 RegsToPass.push_back(std::make_pair(
3186 unsigned(X86::EBX), DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(),
3187 getPointerTy(DAG.getDataLayout()))));
3189 // If we are tail calling and generating PIC/GOT style code load the
3190 // address of the callee into ECX. The value in ecx is used as target of
3191 // the tail jump. This is done to circumvent the ebx/callee-saved problem
3192 // for tail calls on PIC/GOT architectures. Normally we would just put the
3193 // address of GOT into ebx and then call target@PLT. But for tail calls
3194 // ebx would be restored (since ebx is callee saved) before jumping to the
3197 // Note: The actual moving to ECX is done further down.
3198 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
3199 if (G && !G->getGlobal()->hasLocalLinkage() &&
3200 G->getGlobal()->hasDefaultVisibility())
3201 Callee = LowerGlobalAddress(Callee, DAG);
3202 else if (isa<ExternalSymbolSDNode>(Callee))
3203 Callee = LowerExternalSymbol(Callee, DAG);
3207 if (Is64Bit && isVarArg && !IsWin64 && !IsMustTail) {
3208 // From AMD64 ABI document:
3209 // For calls that may call functions that use varargs or stdargs
3210 // (prototype-less calls or calls to functions containing ellipsis (...) in
3211 // the declaration) %al is used as hidden argument to specify the number
3212 // of SSE registers used. The contents of %al do not need to match exactly
3213 // the number of registers, but must be an ubound on the number of SSE
3214 // registers used and is in the range 0 - 8 inclusive.
3216 // Count the number of XMM registers allocated.
3217 static const MCPhysReg XMMArgRegs[] = {
3218 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
3219 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
3221 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs);
3222 assert((Subtarget->hasSSE1() || !NumXMMRegs)
3223 && "SSE registers cannot be used when SSE is disabled");
3225 RegsToPass.push_back(std::make_pair(unsigned(X86::AL),
3226 DAG.getConstant(NumXMMRegs, dl,
3230 if (isVarArg && IsMustTail) {
3231 const auto &Forwards = X86Info->getForwardedMustTailRegParms();
3232 for (const auto &F : Forwards) {
3233 SDValue Val = DAG.getCopyFromReg(Chain, dl, F.VReg, F.VT);
3234 RegsToPass.push_back(std::make_pair(unsigned(F.PReg), Val));
3238 // For tail calls lower the arguments to the 'real' stack slots. Sibcalls
3239 // don't need this because the eligibility check rejects calls that require
3240 // shuffling arguments passed in memory.
3241 if (!IsSibcall && isTailCall) {
3242 // Force all the incoming stack arguments to be loaded from the stack
3243 // before any new outgoing arguments are stored to the stack, because the
3244 // outgoing stack slots may alias the incoming argument stack slots, and
3245 // the alias isn't otherwise explicit. This is slightly more conservative
3246 // than necessary, because it means that each store effectively depends
3247 // on every argument instead of just those arguments it would clobber.
3248 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
3250 SmallVector<SDValue, 8> MemOpChains2;
3253 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3254 CCValAssign &VA = ArgLocs[i];
3257 assert(VA.isMemLoc());
3258 SDValue Arg = OutVals[i];
3259 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3260 // Skip inalloca arguments. They don't require any work.
3261 if (Flags.isInAlloca())
3263 // Create frame index.
3264 int32_t Offset = VA.getLocMemOffset()+FPDiff;
3265 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
3266 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
3267 FIN = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
3269 if (Flags.isByVal()) {
3270 // Copy relative to framepointer.
3271 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset(), dl);
3272 if (!StackPtr.getNode())
3273 StackPtr = DAG.getCopyFromReg(Chain, dl, RegInfo->getStackRegister(),
3274 getPointerTy(DAG.getDataLayout()));
3275 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(DAG.getDataLayout()),
3278 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
3282 // Store relative to framepointer.
3283 MemOpChains2.push_back(DAG.getStore(
3284 ArgChain, dl, Arg, FIN,
3285 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI),
3290 if (!MemOpChains2.empty())
3291 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains2);
3293 // Store the return address to the appropriate stack slot.
3294 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx,
3295 getPointerTy(DAG.getDataLayout()),
3296 RegInfo->getSlotSize(), FPDiff, dl);
3299 // Build a sequence of copy-to-reg nodes chained together with token chain
3300 // and flag operands which copy the outgoing args into registers.
3302 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
3303 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
3304 RegsToPass[i].second, InFlag);
3305 InFlag = Chain.getValue(1);
3308 if (DAG.getTarget().getCodeModel() == CodeModel::Large) {
3309 assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
3310 // In the 64-bit large code model, we have to make all calls
3311 // through a register, since the call instruction's 32-bit
3312 // pc-relative offset may not be large enough to hold the whole
3314 } else if (Callee->getOpcode() == ISD::GlobalAddress) {
3315 // If the callee is a GlobalAddress node (quite common, every direct call
3316 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
3318 GlobalAddressSDNode* G = cast<GlobalAddressSDNode>(Callee);
3320 // We should use extra load for direct calls to dllimported functions in
3322 const GlobalValue *GV = G->getGlobal();
3323 if (!GV->hasDLLImportStorageClass()) {
3324 unsigned char OpFlags = 0;
3325 bool ExtraLoad = false;
3326 unsigned WrapperKind = ISD::DELETED_NODE;
3328 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
3329 // external symbols most go through the PLT in PIC mode. If the symbol
3330 // has hidden or protected visibility, or if it is static or local, then
3331 // we don't need to use the PLT - we can directly call it.
3332 if (Subtarget->isTargetELF() &&
3333 DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
3334 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
3335 OpFlags = X86II::MO_PLT;
3336 } else if (Subtarget->isPICStyleStubAny() &&
3337 !GV->isStrongDefinitionForLinker() &&
3338 (!Subtarget->getTargetTriple().isMacOSX() ||
3339 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
3340 // PC-relative references to external symbols should go through $stub,
3341 // unless we're building with the leopard linker or later, which
3342 // automatically synthesizes these stubs.
3343 OpFlags = X86II::MO_DARWIN_STUB;
3344 } else if (Subtarget->isPICStyleRIPRel() && isa<Function>(GV) &&
3345 cast<Function>(GV)->hasFnAttribute(Attribute::NonLazyBind)) {
3346 // If the function is marked as non-lazy, generate an indirect call
3347 // which loads from the GOT directly. This avoids runtime overhead
3348 // at the cost of eager binding (and one extra byte of encoding).
3349 OpFlags = X86II::MO_GOTPCREL;
3350 WrapperKind = X86ISD::WrapperRIP;
3354 Callee = DAG.getTargetGlobalAddress(
3355 GV, dl, getPointerTy(DAG.getDataLayout()), G->getOffset(), OpFlags);
3357 // Add a wrapper if needed.
3358 if (WrapperKind != ISD::DELETED_NODE)
3359 Callee = DAG.getNode(X86ISD::WrapperRIP, dl,
3360 getPointerTy(DAG.getDataLayout()), Callee);
3361 // Add extra indirection if needed.
3363 Callee = DAG.getLoad(
3364 getPointerTy(DAG.getDataLayout()), dl, DAG.getEntryNode(), Callee,
3365 MachinePointerInfo::getGOT(DAG.getMachineFunction()), false, false,
3368 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
3369 unsigned char OpFlags = 0;
3371 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to
3372 // external symbols should go through the PLT.
3373 if (Subtarget->isTargetELF() &&
3374 DAG.getTarget().getRelocationModel() == Reloc::PIC_) {
3375 OpFlags = X86II::MO_PLT;
3376 } else if (Subtarget->isPICStyleStubAny() &&
3377 (!Subtarget->getTargetTriple().isMacOSX() ||
3378 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
3379 // PC-relative references to external symbols should go through $stub,
3380 // unless we're building with the leopard linker or later, which
3381 // automatically synthesizes these stubs.
3382 OpFlags = X86II::MO_DARWIN_STUB;
3385 Callee = DAG.getTargetExternalSymbol(
3386 S->getSymbol(), getPointerTy(DAG.getDataLayout()), OpFlags);
3387 } else if (Subtarget->isTarget64BitILP32() &&
3388 Callee->getValueType(0) == MVT::i32) {
3389 // Zero-extend the 32-bit Callee address into a 64-bit according to x32 ABI
3390 Callee = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, Callee);
3393 // Returns a chain & a flag for retval copy to use.
3394 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
3395 SmallVector<SDValue, 8> Ops;
3397 if (!IsSibcall && isTailCall) {
3398 Chain = DAG.getCALLSEQ_END(Chain,
3399 DAG.getIntPtrConstant(NumBytesToPop, dl, true),
3400 DAG.getIntPtrConstant(0, dl, true), InFlag, dl);
3401 InFlag = Chain.getValue(1);
3404 Ops.push_back(Chain);
3405 Ops.push_back(Callee);
3408 Ops.push_back(DAG.getConstant(FPDiff, dl, MVT::i32));
3410 // Add argument registers to the end of the list so that they are known live
3412 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
3413 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
3414 RegsToPass[i].second.getValueType()));
3416 // Add a register mask operand representing the call-preserved registers.
3417 const uint32_t *Mask = RegInfo->getCallPreservedMask(MF, CallConv);
3418 assert(Mask && "Missing call preserved mask for calling convention");
3420 // If this is an invoke in a 32-bit function using a funclet-based
3421 // personality, assume the function clobbers all registers. If an exception
3422 // is thrown, the runtime will not restore CSRs.
3423 // FIXME: Model this more precisely so that we can register allocate across
3424 // the normal edge and spill and fill across the exceptional edge.
3425 if (!Is64Bit && CLI.CS && CLI.CS->isInvoke()) {
3426 const Function *CallerFn = MF.getFunction();
3427 EHPersonality Pers =
3428 CallerFn->hasPersonalityFn()
3429 ? classifyEHPersonality(CallerFn->getPersonalityFn())
3430 : EHPersonality::Unknown;
3431 if (isFuncletEHPersonality(Pers))
3432 Mask = RegInfo->getNoPreservedMask();
3435 Ops.push_back(DAG.getRegisterMask(Mask));
3437 if (InFlag.getNode())
3438 Ops.push_back(InFlag);
3442 //// If this is the first return lowered for this function, add the regs
3443 //// to the liveout set for the function.
3444 // This isn't right, although it's probably harmless on x86; liveouts
3445 // should be computed from returns not tail calls. Consider a void
3446 // function making a tail call to a function returning int.
3447 MF.getFrameInfo()->setHasTailCall();
3448 return DAG.getNode(X86ISD::TC_RETURN, dl, NodeTys, Ops);
3451 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, Ops);
3452 InFlag = Chain.getValue(1);
3454 // Create the CALLSEQ_END node.
3455 unsigned NumBytesForCalleeToPop;
3456 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
3457 DAG.getTarget().Options.GuaranteedTailCallOpt))
3458 NumBytesForCalleeToPop = NumBytes; // Callee pops everything
3459 else if (!Is64Bit && !canGuaranteeTCO(CallConv) &&
3460 !Subtarget->getTargetTriple().isOSMSVCRT() &&
3461 SR == StackStructReturn)
3462 // If this is a call to a struct-return function, the callee
3463 // pops the hidden struct pointer, so we have to push it back.
3464 // This is common for Darwin/X86, Linux & Mingw32 targets.
3465 // For MSVC Win32 targets, the caller pops the hidden struct pointer.
3466 NumBytesForCalleeToPop = 4;
3468 NumBytesForCalleeToPop = 0; // Callee pops nothing.
3470 // Returns a flag for retval copy to use.
3472 Chain = DAG.getCALLSEQ_END(Chain,
3473 DAG.getIntPtrConstant(NumBytesToPop, dl, true),
3474 DAG.getIntPtrConstant(NumBytesForCalleeToPop, dl,
3477 InFlag = Chain.getValue(1);
3480 // Handle result values, copying them out of physregs into vregs that we
3482 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
3483 Ins, dl, DAG, InVals);
3486 //===----------------------------------------------------------------------===//
3487 // Fast Calling Convention (tail call) implementation
3488 //===----------------------------------------------------------------------===//
3490 // Like std call, callee cleans arguments, convention except that ECX is
3491 // reserved for storing the tail called function address. Only 2 registers are
3492 // free for argument passing (inreg). Tail call optimization is performed
3494 // * tailcallopt is enabled
3495 // * caller/callee are fastcc
3496 // On X86_64 architecture with GOT-style position independent code only local
3497 // (within module) calls are supported at the moment.
3498 // To keep the stack aligned according to platform abi the function
3499 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
3500 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
3501 // If a tail called function callee has more arguments than the caller the
3502 // caller needs to make sure that there is room to move the RETADDR to. This is
3503 // achieved by reserving an area the size of the argument delta right after the
3504 // original RETADDR, but before the saved framepointer or the spilled registers
3505 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
3517 /// Make the stack size align e.g 16n + 12 aligned for a 16-byte align
3520 X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
3521 SelectionDAG& DAG) const {
3522 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
3523 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
3524 unsigned StackAlignment = TFI.getStackAlignment();
3525 uint64_t AlignMask = StackAlignment - 1;
3526 int64_t Offset = StackSize;
3527 unsigned SlotSize = RegInfo->getSlotSize();
3528 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
3529 // Number smaller than 12 so just add the difference.
3530 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
3532 // Mask out lower bits, add stackalignment once plus the 12 bytes.
3533 Offset = ((~AlignMask) & Offset) + StackAlignment +
3534 (StackAlignment-SlotSize);
3539 /// Return true if the given stack call argument is already available in the
3540 /// same position (relatively) of the caller's incoming argument stack.
3542 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
3543 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
3544 const X86InstrInfo *TII) {
3545 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
3547 if (Arg.getOpcode() == ISD::CopyFromReg) {
3548 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
3549 if (!TargetRegisterInfo::isVirtualRegister(VR))
3551 MachineInstr *Def = MRI->getVRegDef(VR);
3554 if (!Flags.isByVal()) {
3555 if (!TII->isLoadFromStackSlot(Def, FI))
3558 unsigned Opcode = Def->getOpcode();
3559 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r ||
3560 Opcode == X86::LEA64_32r) &&
3561 Def->getOperand(1).isFI()) {
3562 FI = Def->getOperand(1).getIndex();
3563 Bytes = Flags.getByValSize();
3567 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
3568 if (Flags.isByVal())
3569 // ByVal argument is passed in as a pointer but it's now being
3570 // dereferenced. e.g.
3571 // define @foo(%struct.X* %A) {
3572 // tail call @bar(%struct.X* byval %A)
3575 SDValue Ptr = Ld->getBasePtr();
3576 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
3579 FI = FINode->getIndex();
3580 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) {
3581 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg);
3582 FI = FINode->getIndex();
3583 Bytes = Flags.getByValSize();
3587 assert(FI != INT_MAX);
3588 if (!MFI->isFixedObjectIndex(FI))
3590 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
3593 /// Check whether the call is eligible for tail call optimization. Targets
3594 /// that want to do tail call optimization should implement this function.
3595 bool X86TargetLowering::IsEligibleForTailCallOptimization(
3596 SDValue Callee, CallingConv::ID CalleeCC, bool isVarArg,
3597 bool isCalleeStructRet, bool isCallerStructRet, Type *RetTy,
3598 const SmallVectorImpl<ISD::OutputArg> &Outs,
3599 const SmallVectorImpl<SDValue> &OutVals,
3600 const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG &DAG) const {
3601 if (!mayTailCallThisCC(CalleeCC))
3604 // If -tailcallopt is specified, make fastcc functions tail-callable.
3605 MachineFunction &MF = DAG.getMachineFunction();
3606 const Function *CallerF = MF.getFunction();
3608 // If the function return type is x86_fp80 and the callee return type is not,
3609 // then the FP_EXTEND of the call result is not a nop. It's not safe to
3610 // perform a tailcall optimization here.
3611 if (CallerF->getReturnType()->isX86_FP80Ty() && !RetTy->isX86_FP80Ty())
3614 CallingConv::ID CallerCC = CallerF->getCallingConv();
3615 bool CCMatch = CallerCC == CalleeCC;
3616 bool IsCalleeWin64 = Subtarget->isCallingConvWin64(CalleeCC);
3617 bool IsCallerWin64 = Subtarget->isCallingConvWin64(CallerCC);
3619 // Win64 functions have extra shadow space for argument homing. Don't do the
3620 // sibcall if the caller and callee have mismatched expectations for this
3622 if (IsCalleeWin64 != IsCallerWin64)
3625 if (DAG.getTarget().Options.GuaranteedTailCallOpt) {
3626 if (canGuaranteeTCO(CalleeCC) && CCMatch)
3631 // Look for obvious safe cases to perform tail call optimization that do not
3632 // require ABI changes. This is what gcc calls sibcall.
3634 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
3635 // emit a special epilogue.
3636 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
3637 if (RegInfo->needsStackRealignment(MF))
3640 // Also avoid sibcall optimization if either caller or callee uses struct
3641 // return semantics.
3642 if (isCalleeStructRet || isCallerStructRet)
3645 // Do not sibcall optimize vararg calls unless all arguments are passed via
3647 if (isVarArg && !Outs.empty()) {
3648 // Optimizing for varargs on Win64 is unlikely to be safe without
3649 // additional testing.
3650 if (IsCalleeWin64 || IsCallerWin64)
3653 SmallVector<CCValAssign, 16> ArgLocs;
3654 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
3657 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3658 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
3659 if (!ArgLocs[i].isRegLoc())
3663 // If the call result is in ST0 / ST1, it needs to be popped off the x87
3664 // stack. Therefore, if it's not used by the call it is not safe to optimize
3665 // this into a sibcall.
3666 bool Unused = false;
3667 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
3674 SmallVector<CCValAssign, 16> RVLocs;
3675 CCState CCInfo(CalleeCC, false, DAG.getMachineFunction(), RVLocs,
3677 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
3678 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
3679 CCValAssign &VA = RVLocs[i];
3680 if (VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1)
3685 // If the calling conventions do not match, then we'd better make sure the
3686 // results are returned in the same way as what the caller expects.
3688 SmallVector<CCValAssign, 16> RVLocs1;
3689 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(), RVLocs1,
3691 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86);
3693 SmallVector<CCValAssign, 16> RVLocs2;
3694 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(), RVLocs2,
3696 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86);
3698 if (RVLocs1.size() != RVLocs2.size())
3700 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
3701 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
3703 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
3705 if (RVLocs1[i].isRegLoc()) {
3706 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
3709 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
3715 unsigned StackArgsSize = 0;
3717 // If the callee takes no arguments then go on to check the results of the
3719 if (!Outs.empty()) {
3720 // Check if stack adjustment is needed. For now, do not do this if any
3721 // argument is passed on the stack.
3722 SmallVector<CCValAssign, 16> ArgLocs;
3723 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
3726 // Allocate shadow area for Win64
3728 CCInfo.AllocateStack(32, 8);
3730 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3731 StackArgsSize = CCInfo.getNextStackOffset();
3733 if (CCInfo.getNextStackOffset()) {
3734 // Check if the arguments are already laid out in the right way as
3735 // the caller's fixed stack objects.
3736 MachineFrameInfo *MFI = MF.getFrameInfo();
3737 const MachineRegisterInfo *MRI = &MF.getRegInfo();
3738 const X86InstrInfo *TII = Subtarget->getInstrInfo();
3739 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3740 CCValAssign &VA = ArgLocs[i];
3741 SDValue Arg = OutVals[i];
3742 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3743 if (VA.getLocInfo() == CCValAssign::Indirect)
3745 if (!VA.isRegLoc()) {
3746 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
3753 // If the tailcall address may be in a register, then make sure it's
3754 // possible to register allocate for it. In 32-bit, the call address can
3755 // only target EAX, EDX, or ECX since the tail call must be scheduled after
3756 // callee-saved registers are restored. These happen to be the same
3757 // registers used to pass 'inreg' arguments so watch out for those.
3758 if (!Subtarget->is64Bit() &&
3759 ((!isa<GlobalAddressSDNode>(Callee) &&
3760 !isa<ExternalSymbolSDNode>(Callee)) ||
3761 DAG.getTarget().getRelocationModel() == Reloc::PIC_)) {
3762 unsigned NumInRegs = 0;
3763 // In PIC we need an extra register to formulate the address computation
3765 unsigned MaxInRegs =
3766 (DAG.getTarget().getRelocationModel() == Reloc::PIC_) ? 2 : 3;
3768 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3769 CCValAssign &VA = ArgLocs[i];
3772 unsigned Reg = VA.getLocReg();
3775 case X86::EAX: case X86::EDX: case X86::ECX:
3776 if (++NumInRegs == MaxInRegs)
3784 bool CalleeWillPop =
3785 X86::isCalleePop(CalleeCC, Subtarget->is64Bit(), isVarArg,
3786 MF.getTarget().Options.GuaranteedTailCallOpt);
3788 if (unsigned BytesToPop =
3789 MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn()) {
3790 // If we have bytes to pop, the callee must pop them.
3791 bool CalleePopMatches = CalleeWillPop && BytesToPop == StackArgsSize;
3792 if (!CalleePopMatches)
3794 } else if (CalleeWillPop && StackArgsSize > 0) {
3795 // If we don't have bytes to pop, make sure the callee doesn't pop any.
3803 X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
3804 const TargetLibraryInfo *libInfo) const {
3805 return X86::createFastISel(funcInfo, libInfo);
3808 //===----------------------------------------------------------------------===//
3809 // Other Lowering Hooks
3810 //===----------------------------------------------------------------------===//
3812 static bool MayFoldLoad(SDValue Op) {
3813 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode());
3816 static bool MayFoldIntoStore(SDValue Op) {
3817 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin());
3820 static bool isTargetShuffle(unsigned Opcode) {
3822 default: return false;
3823 case X86ISD::BLENDI:
3824 case X86ISD::PSHUFB:
3825 case X86ISD::PSHUFD:
3826 case X86ISD::PSHUFHW:
3827 case X86ISD::PSHUFLW:
3829 case X86ISD::PALIGNR:
3830 case X86ISD::MOVLHPS:
3831 case X86ISD::MOVLHPD:
3832 case X86ISD::MOVHLPS:
3833 case X86ISD::MOVLPS:
3834 case X86ISD::MOVLPD:
3835 case X86ISD::MOVSHDUP:
3836 case X86ISD::MOVSLDUP:
3837 case X86ISD::MOVDDUP:
3840 case X86ISD::UNPCKL:
3841 case X86ISD::UNPCKH:
3842 case X86ISD::VPERMILPI:
3843 case X86ISD::VPERM2X128:
3844 case X86ISD::VPERMI:
3845 case X86ISD::VPERMV:
3846 case X86ISD::VPERMV3:
3851 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, MVT VT,
3852 SDValue V1, unsigned TargetMask,
3853 SelectionDAG &DAG) {
3855 default: llvm_unreachable("Unknown x86 shuffle node");
3856 case X86ISD::PSHUFD:
3857 case X86ISD::PSHUFHW:
3858 case X86ISD::PSHUFLW:
3859 case X86ISD::VPERMILPI:
3860 case X86ISD::VPERMI:
3861 return DAG.getNode(Opc, dl, VT, V1,
3862 DAG.getConstant(TargetMask, dl, MVT::i8));
3866 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, MVT VT,
3867 SDValue V1, SDValue V2, SelectionDAG &DAG) {
3869 default: llvm_unreachable("Unknown x86 shuffle node");
3870 case X86ISD::MOVLHPS:
3871 case X86ISD::MOVLHPD:
3872 case X86ISD::MOVHLPS:
3873 case X86ISD::MOVLPS:
3874 case X86ISD::MOVLPD:
3877 case X86ISD::UNPCKL:
3878 case X86ISD::UNPCKH:
3879 return DAG.getNode(Opc, dl, VT, V1, V2);
3883 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
3884 MachineFunction &MF = DAG.getMachineFunction();
3885 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
3886 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
3887 int ReturnAddrIndex = FuncInfo->getRAIndex();
3889 if (ReturnAddrIndex == 0) {
3890 // Set up a frame object for the return address.
3891 unsigned SlotSize = RegInfo->getSlotSize();
3892 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize,
3895 FuncInfo->setRAIndex(ReturnAddrIndex);
3898 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy(DAG.getDataLayout()));
3901 bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
3902 bool hasSymbolicDisplacement) {
3903 // Offset should fit into 32 bit immediate field.
3904 if (!isInt<32>(Offset))
3907 // If we don't have a symbolic displacement - we don't have any extra
3909 if (!hasSymbolicDisplacement)
3912 // FIXME: Some tweaks might be needed for medium code model.
3913 if (M != CodeModel::Small && M != CodeModel::Kernel)
3916 // For small code model we assume that latest object is 16MB before end of 31
3917 // bits boundary. We may also accept pretty large negative constants knowing
3918 // that all objects are in the positive half of address space.
3919 if (M == CodeModel::Small && Offset < 16*1024*1024)
3922 // For kernel code model we know that all object resist in the negative half
3923 // of 32bits address space. We may not accept negative offsets, since they may
3924 // be just off and we may accept pretty large positive ones.
3925 if (M == CodeModel::Kernel && Offset >= 0)
3931 /// Determines whether the callee is required to pop its own arguments.
3932 /// Callee pop is necessary to support tail calls.
3933 bool X86::isCalleePop(CallingConv::ID CallingConv,
3934 bool is64Bit, bool IsVarArg, bool GuaranteeTCO) {
3935 // If GuaranteeTCO is true, we force some calls to be callee pop so that we
3936 // can guarantee TCO.
3937 if (!IsVarArg && shouldGuaranteeTCO(CallingConv, GuaranteeTCO))
3940 switch (CallingConv) {
3943 case CallingConv::X86_StdCall:
3944 case CallingConv::X86_FastCall:
3945 case CallingConv::X86_ThisCall:
3946 case CallingConv::X86_VectorCall:
3951 /// \brief Return true if the condition is an unsigned comparison operation.
3952 static bool isX86CCUnsigned(unsigned X86CC) {
3954 default: llvm_unreachable("Invalid integer condition!");
3955 case X86::COND_E: return true;
3956 case X86::COND_G: return false;
3957 case X86::COND_GE: return false;
3958 case X86::COND_L: return false;
3959 case X86::COND_LE: return false;
3960 case X86::COND_NE: return true;
3961 case X86::COND_B: return true;
3962 case X86::COND_A: return true;
3963 case X86::COND_BE: return true;
3964 case X86::COND_AE: return true;
3968 static X86::CondCode TranslateIntegerX86CC(ISD::CondCode SetCCOpcode) {
3969 switch (SetCCOpcode) {
3970 default: llvm_unreachable("Invalid integer condition!");
3971 case ISD::SETEQ: return X86::COND_E;
3972 case ISD::SETGT: return X86::COND_G;
3973 case ISD::SETGE: return X86::COND_GE;
3974 case ISD::SETLT: return X86::COND_L;
3975 case ISD::SETLE: return X86::COND_LE;
3976 case ISD::SETNE: return X86::COND_NE;
3977 case ISD::SETULT: return X86::COND_B;
3978 case ISD::SETUGT: return X86::COND_A;
3979 case ISD::SETULE: return X86::COND_BE;
3980 case ISD::SETUGE: return X86::COND_AE;
3984 /// Do a one-to-one translation of a ISD::CondCode to the X86-specific
3985 /// condition code, returning the condition code and the LHS/RHS of the
3986 /// comparison to make.
3987 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, SDLoc DL, bool isFP,
3988 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
3990 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
3991 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
3992 // X > -1 -> X == 0, jump !sign.
3993 RHS = DAG.getConstant(0, DL, RHS.getValueType());
3994 return X86::COND_NS;
3996 if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
3997 // X < 0 -> X == 0, jump on sign.
4000 if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
4002 RHS = DAG.getConstant(0, DL, RHS.getValueType());
4003 return X86::COND_LE;
4007 return TranslateIntegerX86CC(SetCCOpcode);
4010 // First determine if it is required or is profitable to flip the operands.
4012 // If LHS is a foldable load, but RHS is not, flip the condition.
4013 if (ISD::isNON_EXTLoad(LHS.getNode()) &&
4014 !ISD::isNON_EXTLoad(RHS.getNode())) {
4015 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
4016 std::swap(LHS, RHS);
4019 switch (SetCCOpcode) {
4025 std::swap(LHS, RHS);
4029 // On a floating point condition, the flags are set as follows:
4031 // 0 | 0 | 0 | X > Y
4032 // 0 | 0 | 1 | X < Y
4033 // 1 | 0 | 0 | X == Y
4034 // 1 | 1 | 1 | unordered
4035 switch (SetCCOpcode) {
4036 default: llvm_unreachable("Condcode should be pre-legalized away");
4038 case ISD::SETEQ: return X86::COND_E;
4039 case ISD::SETOLT: // flipped
4041 case ISD::SETGT: return X86::COND_A;
4042 case ISD::SETOLE: // flipped
4044 case ISD::SETGE: return X86::COND_AE;
4045 case ISD::SETUGT: // flipped
4047 case ISD::SETLT: return X86::COND_B;
4048 case ISD::SETUGE: // flipped
4050 case ISD::SETLE: return X86::COND_BE;
4052 case ISD::SETNE: return X86::COND_NE;
4053 case ISD::SETUO: return X86::COND_P;
4054 case ISD::SETO: return X86::COND_NP;
4056 case ISD::SETUNE: return X86::COND_INVALID;
4060 /// Is there a floating point cmov for the specific X86 condition code?
4061 /// Current x86 isa includes the following FP cmov instructions:
4062 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
4063 static bool hasFPCMov(unsigned X86CC) {
4079 /// Returns true if the target can instruction select the
4080 /// specified FP immediate natively. If false, the legalizer will
4081 /// materialize the FP immediate as a load from a constant pool.
4082 bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
4083 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
4084 if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
4090 bool X86TargetLowering::shouldReduceLoadWidth(SDNode *Load,
4091 ISD::LoadExtType ExtTy,
4093 // "ELF Handling for Thread-Local Storage" specifies that R_X86_64_GOTTPOFF
4094 // relocation target a movq or addq instruction: don't let the load shrink.
4095 SDValue BasePtr = cast<LoadSDNode>(Load)->getBasePtr();
4096 if (BasePtr.getOpcode() == X86ISD::WrapperRIP)
4097 if (const auto *GA = dyn_cast<GlobalAddressSDNode>(BasePtr.getOperand(0)))
4098 return GA->getTargetFlags() != X86II::MO_GOTTPOFF;
4102 /// \brief Returns true if it is beneficial to convert a load of a constant
4103 /// to just the constant itself.
4104 bool X86TargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
4106 assert(Ty->isIntegerTy());
4108 unsigned BitSize = Ty->getPrimitiveSizeInBits();
4109 if (BitSize == 0 || BitSize > 64)
4114 bool X86TargetLowering::isExtractSubvectorCheap(EVT ResVT,
4115 unsigned Index) const {
4116 if (!isOperationLegalOrCustom(ISD::EXTRACT_SUBVECTOR, ResVT))
4119 return (Index == 0 || Index == ResVT.getVectorNumElements());
4122 bool X86TargetLowering::isCheapToSpeculateCttz() const {
4123 // Speculate cttz only if we can directly use TZCNT.
4124 return Subtarget->hasBMI();
4127 bool X86TargetLowering::isCheapToSpeculateCtlz() const {
4128 // Speculate ctlz only if we can directly use LZCNT.
4129 return Subtarget->hasLZCNT();
4132 /// Return true if every element in Mask, beginning
4133 /// from position Pos and ending in Pos+Size is undef.
4134 static bool isUndefInRange(ArrayRef<int> Mask, unsigned Pos, unsigned Size) {
4135 for (unsigned i = Pos, e = Pos + Size; i != e; ++i)
4141 /// Return true if Val is undef or if its value falls within the
4142 /// specified range (L, H].
4143 static bool isUndefOrInRange(int Val, int Low, int Hi) {
4144 return (Val < 0) || (Val >= Low && Val < Hi);
4147 /// Val is either less than zero (undef) or equal to the specified value.
4148 static bool isUndefOrEqual(int Val, int CmpVal) {
4149 return (Val < 0 || Val == CmpVal);
4152 /// Return true if every element in Mask, beginning
4153 /// from position Pos and ending in Pos+Size, falls within the specified
4154 /// sequential range (Low, Low+Size]. or is undef.
4155 static bool isSequentialOrUndefInRange(ArrayRef<int> Mask,
4156 unsigned Pos, unsigned Size, int Low) {
4157 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low)
4158 if (!isUndefOrEqual(Mask[i], Low))
4163 /// Return true if the specified EXTRACT_SUBVECTOR operand specifies a vector
4164 /// extract that is suitable for instruction that extract 128 or 256 bit vectors
4165 static bool isVEXTRACTIndex(SDNode *N, unsigned vecWidth) {
4166 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4167 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4170 // The index should be aligned on a vecWidth-bit boundary.
4172 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4174 MVT VT = N->getSimpleValueType(0);
4175 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4176 bool Result = (Index * ElSize) % vecWidth == 0;
4181 /// Return true if the specified INSERT_SUBVECTOR
4182 /// operand specifies a subvector insert that is suitable for input to
4183 /// insertion of 128 or 256-bit subvectors
4184 static bool isVINSERTIndex(SDNode *N, unsigned vecWidth) {
4185 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4186 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4188 // The index should be aligned on a vecWidth-bit boundary.
4190 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4192 MVT VT = N->getSimpleValueType(0);
4193 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4194 bool Result = (Index * ElSize) % vecWidth == 0;
4199 bool X86::isVINSERT128Index(SDNode *N) {
4200 return isVINSERTIndex(N, 128);
4203 bool X86::isVINSERT256Index(SDNode *N) {
4204 return isVINSERTIndex(N, 256);
4207 bool X86::isVEXTRACT128Index(SDNode *N) {
4208 return isVEXTRACTIndex(N, 128);
4211 bool X86::isVEXTRACT256Index(SDNode *N) {
4212 return isVEXTRACTIndex(N, 256);
4215 static unsigned getExtractVEXTRACTImmediate(SDNode *N, unsigned vecWidth) {
4216 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4217 assert(isa<ConstantSDNode>(N->getOperand(1).getNode()) &&
4218 "Illegal extract subvector for VEXTRACT");
4221 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4223 MVT VecVT = N->getOperand(0).getSimpleValueType();
4224 MVT ElVT = VecVT.getVectorElementType();
4226 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4227 return Index / NumElemsPerChunk;
4230 static unsigned getInsertVINSERTImmediate(SDNode *N, unsigned vecWidth) {
4231 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4232 assert(isa<ConstantSDNode>(N->getOperand(2).getNode()) &&
4233 "Illegal insert subvector for VINSERT");
4236 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4238 MVT VecVT = N->getSimpleValueType(0);
4239 MVT ElVT = VecVT.getVectorElementType();
4241 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4242 return Index / NumElemsPerChunk;
4245 /// Return the appropriate immediate to extract the specified
4246 /// EXTRACT_SUBVECTOR index with VEXTRACTF128 and VINSERTI128 instructions.
4247 unsigned X86::getExtractVEXTRACT128Immediate(SDNode *N) {
4248 return getExtractVEXTRACTImmediate(N, 128);
4251 /// Return the appropriate immediate to extract the specified
4252 /// EXTRACT_SUBVECTOR index with VEXTRACTF64x4 and VINSERTI64x4 instructions.
4253 unsigned X86::getExtractVEXTRACT256Immediate(SDNode *N) {
4254 return getExtractVEXTRACTImmediate(N, 256);
4257 /// Return the appropriate immediate to insert at the specified
4258 /// INSERT_SUBVECTOR index with VINSERTF128 and VINSERTI128 instructions.
4259 unsigned X86::getInsertVINSERT128Immediate(SDNode *N) {
4260 return getInsertVINSERTImmediate(N, 128);
4263 /// Return the appropriate immediate to insert at the specified
4264 /// INSERT_SUBVECTOR index with VINSERTF46x4 and VINSERTI64x4 instructions.
4265 unsigned X86::getInsertVINSERT256Immediate(SDNode *N) {
4266 return getInsertVINSERTImmediate(N, 256);
4269 /// Returns true if Elt is a constant zero or a floating point constant +0.0.
4270 bool X86::isZeroNode(SDValue Elt) {
4271 return isNullConstant(Elt) || isNullFPConstant(Elt);
4274 // Build a vector of constants
4275 // Use an UNDEF node if MaskElt == -1.
4276 // Spilt 64-bit constants in the 32-bit mode.
4277 static SDValue getConstVector(ArrayRef<int> Values, MVT VT,
4279 SDLoc dl, bool IsMask = false) {
4281 SmallVector<SDValue, 32> Ops;
4284 MVT ConstVecVT = VT;
4285 unsigned NumElts = VT.getVectorNumElements();
4286 bool In64BitMode = DAG.getTargetLoweringInfo().isTypeLegal(MVT::i64);
4287 if (!In64BitMode && VT.getVectorElementType() == MVT::i64) {
4288 ConstVecVT = MVT::getVectorVT(MVT::i32, NumElts * 2);
4292 MVT EltVT = ConstVecVT.getVectorElementType();
4293 for (unsigned i = 0; i < NumElts; ++i) {
4294 bool IsUndef = Values[i] < 0 && IsMask;
4295 SDValue OpNode = IsUndef ? DAG.getUNDEF(EltVT) :
4296 DAG.getConstant(Values[i], dl, EltVT);
4297 Ops.push_back(OpNode);
4299 Ops.push_back(IsUndef ? DAG.getUNDEF(EltVT) :
4300 DAG.getConstant(0, dl, EltVT));
4302 SDValue ConstsNode = DAG.getNode(ISD::BUILD_VECTOR, dl, ConstVecVT, Ops);
4304 ConstsNode = DAG.getBitcast(VT, ConstsNode);
4308 /// Returns a vector of specified type with all zero elements.
4309 static SDValue getZeroVector(MVT VT, const X86Subtarget *Subtarget,
4310 SelectionDAG &DAG, SDLoc dl) {
4311 assert(VT.isVector() && "Expected a vector type");
4313 // Always build SSE zero vectors as <4 x i32> bitcasted
4314 // to their dest type. This ensures they get CSE'd.
4316 if (VT.is128BitVector()) { // SSE
4317 if (Subtarget->hasSSE2()) { // SSE2
4318 SDValue Cst = DAG.getConstant(0, dl, MVT::i32);
4319 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4321 SDValue Cst = DAG.getConstantFP(+0.0, dl, MVT::f32);
4322 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
4324 } else if (VT.is256BitVector()) { // AVX
4325 if (Subtarget->hasInt256()) { // AVX2
4326 SDValue Cst = DAG.getConstant(0, dl, MVT::i32);
4327 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4328 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
4330 // 256-bit logic and arithmetic instructions in AVX are all
4331 // floating-point, no support for integer ops. Emit fp zeroed vectors.
4332 SDValue Cst = DAG.getConstantFP(+0.0, dl, MVT::f32);
4333 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4334 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops);
4336 } else if (VT.is512BitVector()) { // AVX-512
4337 SDValue Cst = DAG.getConstant(0, dl, MVT::i32);
4338 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst,
4339 Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4340 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i32, Ops);
4341 } else if (VT.getVectorElementType() == MVT::i1) {
4343 assert((Subtarget->hasBWI() || VT.getVectorNumElements() <= 16)
4344 && "Unexpected vector type");
4345 assert((Subtarget->hasVLX() || VT.getVectorNumElements() >= 8)
4346 && "Unexpected vector type");
4347 SDValue Cst = DAG.getConstant(0, dl, MVT::i1);
4348 SmallVector<SDValue, 64> Ops(VT.getVectorNumElements(), Cst);
4349 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
4351 llvm_unreachable("Unexpected vector type");
4353 return DAG.getBitcast(VT, Vec);
4356 static SDValue ExtractSubVector(SDValue Vec, unsigned IdxVal,
4357 SelectionDAG &DAG, SDLoc dl,
4358 unsigned vectorWidth) {
4359 assert((vectorWidth == 128 || vectorWidth == 256) &&
4360 "Unsupported vector width");
4361 EVT VT = Vec.getValueType();
4362 EVT ElVT = VT.getVectorElementType();
4363 unsigned Factor = VT.getSizeInBits()/vectorWidth;
4364 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT,
4365 VT.getVectorNumElements()/Factor);
4367 // Extract from UNDEF is UNDEF.
4368 if (Vec.getOpcode() == ISD::UNDEF)
4369 return DAG.getUNDEF(ResultVT);
4371 // Extract the relevant vectorWidth bits. Generate an EXTRACT_SUBVECTOR
4372 unsigned ElemsPerChunk = vectorWidth / ElVT.getSizeInBits();
4373 assert(isPowerOf2_32(ElemsPerChunk) && "Elements per chunk not power of 2");
4375 // This is the index of the first element of the vectorWidth-bit chunk
4376 // we want. Since ElemsPerChunk is a power of 2 just need to clear bits.
4377 IdxVal &= ~(ElemsPerChunk - 1);
4379 // If the input is a buildvector just emit a smaller one.
4380 if (Vec.getOpcode() == ISD::BUILD_VECTOR)
4381 return DAG.getNode(ISD::BUILD_VECTOR, dl, ResultVT,
4382 makeArrayRef(Vec->op_begin() + IdxVal, ElemsPerChunk));
4384 SDValue VecIdx = DAG.getIntPtrConstant(IdxVal, dl);
4385 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec, VecIdx);
4388 /// Generate a DAG to grab 128-bits from a vector > 128 bits. This
4389 /// sets things up to match to an AVX VEXTRACTF128 / VEXTRACTI128
4390 /// or AVX-512 VEXTRACTF32x4 / VEXTRACTI32x4
4391 /// instructions or a simple subregister reference. Idx is an index in the
4392 /// 128 bits we want. It need not be aligned to a 128-bit boundary. That makes
4393 /// lowering EXTRACT_VECTOR_ELT operations easier.
4394 static SDValue Extract128BitVector(SDValue Vec, unsigned IdxVal,
4395 SelectionDAG &DAG, SDLoc dl) {
4396 assert((Vec.getValueType().is256BitVector() ||
4397 Vec.getValueType().is512BitVector()) && "Unexpected vector size!");
4398 return ExtractSubVector(Vec, IdxVal, DAG, dl, 128);
4401 /// Generate a DAG to grab 256-bits from a 512-bit vector.
4402 static SDValue Extract256BitVector(SDValue Vec, unsigned IdxVal,
4403 SelectionDAG &DAG, SDLoc dl) {
4404 assert(Vec.getValueType().is512BitVector() && "Unexpected vector size!");
4405 return ExtractSubVector(Vec, IdxVal, DAG, dl, 256);
4408 static SDValue InsertSubVector(SDValue Result, SDValue Vec,
4409 unsigned IdxVal, SelectionDAG &DAG,
4410 SDLoc dl, unsigned vectorWidth) {
4411 assert((vectorWidth == 128 || vectorWidth == 256) &&
4412 "Unsupported vector width");
4413 // Inserting UNDEF is Result
4414 if (Vec.getOpcode() == ISD::UNDEF)
4416 EVT VT = Vec.getValueType();
4417 EVT ElVT = VT.getVectorElementType();
4418 EVT ResultVT = Result.getValueType();
4420 // Insert the relevant vectorWidth bits.
4421 unsigned ElemsPerChunk = vectorWidth/ElVT.getSizeInBits();
4422 assert(isPowerOf2_32(ElemsPerChunk) && "Elements per chunk not power of 2");
4424 // This is the index of the first element of the vectorWidth-bit chunk
4425 // we want. Since ElemsPerChunk is a power of 2 just need to clear bits.
4426 IdxVal &= ~(ElemsPerChunk - 1);
4428 SDValue VecIdx = DAG.getIntPtrConstant(IdxVal, dl);
4429 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec, VecIdx);
4432 /// Generate a DAG to put 128-bits into a vector > 128 bits. This
4433 /// sets things up to match to an AVX VINSERTF128/VINSERTI128 or
4434 /// AVX-512 VINSERTF32x4/VINSERTI32x4 instructions or a
4435 /// simple superregister reference. Idx is an index in the 128 bits
4436 /// we want. It need not be aligned to a 128-bit boundary. That makes
4437 /// lowering INSERT_VECTOR_ELT operations easier.
4438 static SDValue Insert128BitVector(SDValue Result, SDValue Vec, unsigned IdxVal,
4439 SelectionDAG &DAG, SDLoc dl) {
4440 assert(Vec.getValueType().is128BitVector() && "Unexpected vector size!");
4442 // For insertion into the zero index (low half) of a 256-bit vector, it is
4443 // more efficient to generate a blend with immediate instead of an insert*128.
4444 // We are still creating an INSERT_SUBVECTOR below with an undef node to
4445 // extend the subvector to the size of the result vector. Make sure that
4446 // we are not recursing on that node by checking for undef here.
4447 if (IdxVal == 0 && Result.getValueType().is256BitVector() &&
4448 Result.getOpcode() != ISD::UNDEF) {
4449 EVT ResultVT = Result.getValueType();
4450 SDValue ZeroIndex = DAG.getIntPtrConstant(0, dl);
4451 SDValue Undef = DAG.getUNDEF(ResultVT);
4452 SDValue Vec256 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Undef,
4455 // The blend instruction, and therefore its mask, depend on the data type.
4456 MVT ScalarType = ResultVT.getVectorElementType().getSimpleVT();
4457 if (ScalarType.isFloatingPoint()) {
4458 // Choose either vblendps (float) or vblendpd (double).
4459 unsigned ScalarSize = ScalarType.getSizeInBits();
4460 assert((ScalarSize == 64 || ScalarSize == 32) && "Unknown float type");
4461 unsigned MaskVal = (ScalarSize == 64) ? 0x03 : 0x0f;
4462 SDValue Mask = DAG.getConstant(MaskVal, dl, MVT::i8);
4463 return DAG.getNode(X86ISD::BLENDI, dl, ResultVT, Result, Vec256, Mask);
4466 const X86Subtarget &Subtarget =
4467 static_cast<const X86Subtarget &>(DAG.getSubtarget());
4469 // AVX2 is needed for 256-bit integer blend support.
4470 // Integers must be cast to 32-bit because there is only vpblendd;
4471 // vpblendw can't be used for this because it has a handicapped mask.
4473 // If we don't have AVX2, then cast to float. Using a wrong domain blend
4474 // is still more efficient than using the wrong domain vinsertf128 that
4475 // will be created by InsertSubVector().
4476 MVT CastVT = Subtarget.hasAVX2() ? MVT::v8i32 : MVT::v8f32;
4478 SDValue Mask = DAG.getConstant(0x0f, dl, MVT::i8);
4479 Vec256 = DAG.getBitcast(CastVT, Vec256);
4480 Vec256 = DAG.getNode(X86ISD::BLENDI, dl, CastVT, Result, Vec256, Mask);
4481 return DAG.getBitcast(ResultVT, Vec256);
4484 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 128);
4487 static SDValue Insert256BitVector(SDValue Result, SDValue Vec, unsigned IdxVal,
4488 SelectionDAG &DAG, SDLoc dl) {
4489 assert(Vec.getValueType().is256BitVector() && "Unexpected vector size!");
4490 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 256);
4493 /// Insert i1-subvector to i1-vector.
4494 static SDValue Insert1BitVector(SDValue Op, SelectionDAG &DAG) {
4497 SDValue Vec = Op.getOperand(0);
4498 SDValue SubVec = Op.getOperand(1);
4499 SDValue Idx = Op.getOperand(2);
4501 if (!isa<ConstantSDNode>(Idx))
4504 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
4505 if (IdxVal == 0 && Vec.isUndef()) // the operation is legal
4508 MVT OpVT = Op.getSimpleValueType();
4509 MVT SubVecVT = SubVec.getSimpleValueType();
4510 unsigned NumElems = OpVT.getVectorNumElements();
4511 unsigned SubVecNumElems = SubVecVT.getVectorNumElements();
4513 assert(IdxVal + SubVecNumElems <= NumElems &&
4514 IdxVal % SubVecVT.getSizeInBits() == 0 &&
4515 "Unexpected index value in INSERT_SUBVECTOR");
4517 // There are 3 possible cases:
4518 // 1. Subvector should be inserted in the lower part (IdxVal == 0)
4519 // 2. Subvector should be inserted in the upper part
4520 // (IdxVal + SubVecNumElems == NumElems)
4521 // 3. Subvector should be inserted in the middle (for example v2i1
4522 // to v16i1, index 2)
4524 SDValue ZeroIdx = DAG.getIntPtrConstant(0, dl);
4525 SDValue Undef = DAG.getUNDEF(OpVT);
4526 SDValue WideSubVec =
4527 DAG.getNode(ISD::INSERT_SUBVECTOR, dl, OpVT, Undef, SubVec, ZeroIdx);
4529 return DAG.getNode(X86ISD::VSHLI, dl, OpVT, WideSubVec,
4530 DAG.getConstant(IdxVal, dl, MVT::i8));
4532 if (ISD::isBuildVectorAllZeros(Vec.getNode())) {
4533 unsigned ShiftLeft = NumElems - SubVecNumElems;
4534 unsigned ShiftRight = NumElems - SubVecNumElems - IdxVal;
4535 WideSubVec = DAG.getNode(X86ISD::VSHLI, dl, OpVT, WideSubVec,
4536 DAG.getConstant(ShiftLeft, dl, MVT::i8));
4537 return ShiftRight ? DAG.getNode(X86ISD::VSRLI, dl, OpVT, WideSubVec,
4538 DAG.getConstant(ShiftRight, dl, MVT::i8)) : WideSubVec;
4542 // Zero lower bits of the Vec
4543 SDValue ShiftBits = DAG.getConstant(SubVecNumElems, dl, MVT::i8);
4544 Vec = DAG.getNode(X86ISD::VSRLI, dl, OpVT, Vec, ShiftBits);
4545 Vec = DAG.getNode(X86ISD::VSHLI, dl, OpVT, Vec, ShiftBits);
4546 // Merge them together
4547 return DAG.getNode(ISD::OR, dl, OpVT, Vec, WideSubVec);
4550 // Simple case when we put subvector in the upper part
4551 if (IdxVal + SubVecNumElems == NumElems) {
4552 // Zero upper bits of the Vec
4553 WideSubVec = DAG.getNode(X86ISD::VSHLI, dl, OpVT, Vec,
4554 DAG.getConstant(IdxVal, dl, MVT::i8));
4555 SDValue ShiftBits = DAG.getConstant(SubVecNumElems, dl, MVT::i8);
4556 Vec = DAG.getNode(X86ISD::VSHLI, dl, OpVT, Vec, ShiftBits);
4557 Vec = DAG.getNode(X86ISD::VSRLI, dl, OpVT, Vec, ShiftBits);
4558 return DAG.getNode(ISD::OR, dl, OpVT, Vec, WideSubVec);
4560 // Subvector should be inserted in the middle - use shuffle
4561 SmallVector<int, 64> Mask;
4562 for (unsigned i = 0; i < NumElems; ++i)
4563 Mask.push_back(i >= IdxVal && i < IdxVal + SubVecNumElems ?
4565 return DAG.getVectorShuffle(OpVT, dl, WideSubVec, Vec, Mask);
4568 /// Concat two 128-bit vectors into a 256 bit vector using VINSERTF128
4569 /// instructions. This is used because creating CONCAT_VECTOR nodes of
4570 /// BUILD_VECTORS returns a larger BUILD_VECTOR while we're trying to lower
4571 /// large BUILD_VECTORS.
4572 static SDValue Concat128BitVectors(SDValue V1, SDValue V2, EVT VT,
4573 unsigned NumElems, SelectionDAG &DAG,
4575 SDValue V = Insert128BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
4576 return Insert128BitVector(V, V2, NumElems/2, DAG, dl);
4579 static SDValue Concat256BitVectors(SDValue V1, SDValue V2, EVT VT,
4580 unsigned NumElems, SelectionDAG &DAG,
4582 SDValue V = Insert256BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
4583 return Insert256BitVector(V, V2, NumElems/2, DAG, dl);
4586 /// Returns a vector of specified type with all bits set.
4587 /// Always build ones vectors as <4 x i32> or <8 x i32>. For 256-bit types with
4588 /// no AVX2 supprt, use two <4 x i32> inserted in a <8 x i32> appropriately.
4589 /// Then bitcast to their original type, ensuring they get CSE'd.
4590 static SDValue getOnesVector(EVT VT, const X86Subtarget *Subtarget,
4591 SelectionDAG &DAG, SDLoc dl) {
4592 assert(VT.isVector() && "Expected a vector type");
4594 SDValue Cst = DAG.getConstant(~0U, dl, MVT::i32);
4596 if (VT.is512BitVector()) {
4597 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst,
4598 Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4599 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i32, Ops);
4600 } else if (VT.is256BitVector()) {
4601 if (Subtarget->hasInt256()) { // AVX2
4602 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4603 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
4605 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4606 Vec = Concat128BitVectors(Vec, Vec, MVT::v8i32, 8, DAG, dl);
4608 } else if (VT.is128BitVector()) {
4609 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4611 llvm_unreachable("Unexpected vector type");
4613 return DAG.getBitcast(VT, Vec);
4616 /// Returns a vector_shuffle node for an unpackl operation.
4617 static SDValue getUnpackl(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
4619 unsigned NumElems = VT.getVectorNumElements();
4620 SmallVector<int, 8> Mask;
4621 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
4623 Mask.push_back(i + NumElems);
4625 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4628 /// Returns a vector_shuffle node for an unpackh operation.
4629 static SDValue getUnpackh(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
4631 unsigned NumElems = VT.getVectorNumElements();
4632 SmallVector<int, 8> Mask;
4633 for (unsigned i = 0, Half = NumElems/2; i != Half; ++i) {
4634 Mask.push_back(i + Half);
4635 Mask.push_back(i + NumElems + Half);
4637 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4640 /// Return a vector_shuffle of the specified vector of zero or undef vector.
4641 /// This produces a shuffle where the low element of V2 is swizzled into the
4642 /// zero/undef vector, landing at element Idx.
4643 /// This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
4644 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
4646 const X86Subtarget *Subtarget,
4647 SelectionDAG &DAG) {
4648 MVT VT = V2.getSimpleValueType();
4650 ? getZeroVector(VT, Subtarget, DAG, SDLoc(V2)) : DAG.getUNDEF(VT);
4651 unsigned NumElems = VT.getVectorNumElements();
4652 SmallVector<int, 16> MaskVec;
4653 for (unsigned i = 0; i != NumElems; ++i)
4654 // If this is the insertion idx, put the low elt of V2 here.
4655 MaskVec.push_back(i == Idx ? NumElems : i);
4656 return DAG.getVectorShuffle(VT, SDLoc(V2), V1, V2, &MaskVec[0]);
4659 /// Calculates the shuffle mask corresponding to the target-specific opcode.
4660 /// Returns true if the Mask could be calculated. Sets IsUnary to true if only
4661 /// uses one source. Note that this will set IsUnary for shuffles which use a
4662 /// single input multiple times, and in those cases it will
4663 /// adjust the mask to only have indices within that single input.
4664 /// FIXME: Add support for Decode*Mask functions that return SM_SentinelZero.
4665 static bool getTargetShuffleMask(SDNode *N, MVT VT,
4666 SmallVectorImpl<int> &Mask, bool &IsUnary) {
4667 unsigned NumElems = VT.getVectorNumElements();
4671 bool IsFakeUnary = false;
4672 switch(N->getOpcode()) {
4673 case X86ISD::BLENDI:
4674 ImmN = N->getOperand(N->getNumOperands()-1);
4675 DecodeBLENDMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4678 ImmN = N->getOperand(N->getNumOperands()-1);
4679 DecodeSHUFPMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4680 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4682 case X86ISD::UNPCKH:
4683 DecodeUNPCKHMask(VT, Mask);
4684 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4686 case X86ISD::UNPCKL:
4687 DecodeUNPCKLMask(VT, Mask);
4688 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4690 case X86ISD::MOVHLPS:
4691 DecodeMOVHLPSMask(NumElems, Mask);
4692 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4694 case X86ISD::MOVLHPS:
4695 DecodeMOVLHPSMask(NumElems, Mask);
4696 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4698 case X86ISD::PALIGNR:
4699 ImmN = N->getOperand(N->getNumOperands()-1);
4700 DecodePALIGNRMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4702 case X86ISD::PSHUFD:
4703 case X86ISD::VPERMILPI:
4704 ImmN = N->getOperand(N->getNumOperands()-1);
4705 DecodePSHUFMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4708 case X86ISD::PSHUFHW:
4709 ImmN = N->getOperand(N->getNumOperands()-1);
4710 DecodePSHUFHWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4713 case X86ISD::PSHUFLW:
4714 ImmN = N->getOperand(N->getNumOperands()-1);
4715 DecodePSHUFLWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4718 case X86ISD::PSHUFB: {
4720 SDValue MaskNode = N->getOperand(1);
4721 while (MaskNode->getOpcode() == ISD::BITCAST)
4722 MaskNode = MaskNode->getOperand(0);
4724 if (MaskNode->getOpcode() == ISD::BUILD_VECTOR) {
4725 // If we have a build-vector, then things are easy.
4726 MVT VT = MaskNode.getSimpleValueType();
4727 assert(VT.isVector() &&
4728 "Can't produce a non-vector with a build_vector!");
4729 if (!VT.isInteger())
4732 int NumBytesPerElement = VT.getVectorElementType().getSizeInBits() / 8;
4734 SmallVector<uint64_t, 32> RawMask;
4735 for (int i = 0, e = MaskNode->getNumOperands(); i < e; ++i) {
4736 SDValue Op = MaskNode->getOperand(i);
4737 if (Op->getOpcode() == ISD::UNDEF) {
4738 RawMask.push_back((uint64_t)SM_SentinelUndef);
4741 auto *CN = dyn_cast<ConstantSDNode>(Op.getNode());
4744 APInt MaskElement = CN->getAPIntValue();
4746 // We now have to decode the element which could be any integer size and
4747 // extract each byte of it.
4748 for (int j = 0; j < NumBytesPerElement; ++j) {
4749 // Note that this is x86 and so always little endian: the low byte is
4750 // the first byte of the mask.
4751 RawMask.push_back(MaskElement.getLoBits(8).getZExtValue());
4752 MaskElement = MaskElement.lshr(8);
4755 DecodePSHUFBMask(RawMask, Mask);
4759 auto *MaskLoad = dyn_cast<LoadSDNode>(MaskNode);
4763 SDValue Ptr = MaskLoad->getBasePtr();
4764 if (Ptr->getOpcode() == X86ISD::Wrapper ||
4765 Ptr->getOpcode() == X86ISD::WrapperRIP)
4766 Ptr = Ptr->getOperand(0);
4768 auto *MaskCP = dyn_cast<ConstantPoolSDNode>(Ptr);
4769 if (!MaskCP || MaskCP->isMachineConstantPoolEntry())
4772 if (auto *C = dyn_cast<Constant>(MaskCP->getConstVal())) {
4773 DecodePSHUFBMask(C, Mask);
4781 case X86ISD::VPERMI:
4782 ImmN = N->getOperand(N->getNumOperands()-1);
4783 DecodeVPERMMask(cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4788 DecodeScalarMoveMask(VT, /* IsLoad */ false, Mask);
4790 case X86ISD::VPERM2X128:
4791 ImmN = N->getOperand(N->getNumOperands()-1);
4792 DecodeVPERM2X128Mask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4793 if (Mask.empty()) return false;
4794 // Mask only contains negative index if an element is zero.
4795 if (std::any_of(Mask.begin(), Mask.end(),
4796 [](int M){ return M == SM_SentinelZero; }))
4799 case X86ISD::MOVSLDUP:
4800 DecodeMOVSLDUPMask(VT, Mask);
4803 case X86ISD::MOVSHDUP:
4804 DecodeMOVSHDUPMask(VT, Mask);
4807 case X86ISD::MOVDDUP:
4808 DecodeMOVDDUPMask(VT, Mask);
4811 case X86ISD::MOVLHPD:
4812 case X86ISD::MOVLPD:
4813 case X86ISD::MOVLPS:
4814 // Not yet implemented
4816 case X86ISD::VPERMV: {
4818 SDValue MaskNode = N->getOperand(0);
4819 while (MaskNode->getOpcode() == ISD::BITCAST)
4820 MaskNode = MaskNode->getOperand(0);
4822 unsigned MaskLoBits = Log2_64(VT.getVectorNumElements());
4823 SmallVector<uint64_t, 32> RawMask;
4824 if (MaskNode->getOpcode() == ISD::BUILD_VECTOR) {
4825 // If we have a build-vector, then things are easy.
4826 assert(MaskNode.getSimpleValueType().isInteger() &&
4827 MaskNode.getSimpleValueType().getVectorNumElements() ==
4828 VT.getVectorNumElements());
4830 for (unsigned i = 0; i < MaskNode->getNumOperands(); ++i) {
4831 SDValue Op = MaskNode->getOperand(i);
4832 if (Op->getOpcode() == ISD::UNDEF)
4833 RawMask.push_back((uint64_t)SM_SentinelUndef);
4834 else if (isa<ConstantSDNode>(Op)) {
4835 APInt MaskElement = cast<ConstantSDNode>(Op)->getAPIntValue();
4836 RawMask.push_back(MaskElement.getLoBits(MaskLoBits).getZExtValue());
4840 DecodeVPERMVMask(RawMask, Mask);
4843 if (MaskNode->getOpcode() == X86ISD::VBROADCAST) {
4844 unsigned NumEltsInMask = MaskNode->getNumOperands();
4845 MaskNode = MaskNode->getOperand(0);
4846 auto *CN = dyn_cast<ConstantSDNode>(MaskNode);
4848 APInt MaskEltValue = CN->getAPIntValue();
4849 for (unsigned i = 0; i < NumEltsInMask; ++i)
4850 RawMask.push_back(MaskEltValue.getLoBits(MaskLoBits).getZExtValue());
4851 DecodeVPERMVMask(RawMask, Mask);
4854 // It may be a scalar load
4857 auto *MaskLoad = dyn_cast<LoadSDNode>(MaskNode);
4861 SDValue Ptr = MaskLoad->getBasePtr();
4862 if (Ptr->getOpcode() == X86ISD::Wrapper ||
4863 Ptr->getOpcode() == X86ISD::WrapperRIP)
4864 Ptr = Ptr->getOperand(0);
4866 auto *MaskCP = dyn_cast<ConstantPoolSDNode>(Ptr);
4867 if (!MaskCP || MaskCP->isMachineConstantPoolEntry())
4870 auto *C = dyn_cast<Constant>(MaskCP->getConstVal());
4872 DecodeVPERMVMask(C, VT, Mask);
4879 case X86ISD::VPERMV3: {
4881 SDValue MaskNode = N->getOperand(1);
4882 while (MaskNode->getOpcode() == ISD::BITCAST)
4883 MaskNode = MaskNode->getOperand(1);
4885 if (MaskNode->getOpcode() == ISD::BUILD_VECTOR) {
4886 // If we have a build-vector, then things are easy.
4887 assert(MaskNode.getSimpleValueType().isInteger() &&
4888 MaskNode.getSimpleValueType().getVectorNumElements() ==
4889 VT.getVectorNumElements());
4891 SmallVector<uint64_t, 32> RawMask;
4892 unsigned MaskLoBits = Log2_64(VT.getVectorNumElements()*2);
4894 for (unsigned i = 0; i < MaskNode->getNumOperands(); ++i) {
4895 SDValue Op = MaskNode->getOperand(i);
4896 if (Op->getOpcode() == ISD::UNDEF)
4897 RawMask.push_back((uint64_t)SM_SentinelUndef);
4899 auto *CN = dyn_cast<ConstantSDNode>(Op.getNode());
4902 APInt MaskElement = CN->getAPIntValue();
4903 RawMask.push_back(MaskElement.getLoBits(MaskLoBits).getZExtValue());
4906 DecodeVPERMV3Mask(RawMask, Mask);
4910 auto *MaskLoad = dyn_cast<LoadSDNode>(MaskNode);
4914 SDValue Ptr = MaskLoad->getBasePtr();
4915 if (Ptr->getOpcode() == X86ISD::Wrapper ||
4916 Ptr->getOpcode() == X86ISD::WrapperRIP)
4917 Ptr = Ptr->getOperand(0);
4919 auto *MaskCP = dyn_cast<ConstantPoolSDNode>(Ptr);
4920 if (!MaskCP || MaskCP->isMachineConstantPoolEntry())
4923 auto *C = dyn_cast<Constant>(MaskCP->getConstVal());
4925 DecodeVPERMV3Mask(C, VT, Mask);
4932 default: llvm_unreachable("unknown target shuffle node");
4935 // If we have a fake unary shuffle, the shuffle mask is spread across two
4936 // inputs that are actually the same node. Re-map the mask to always point
4937 // into the first input.
4940 if (M >= (int)Mask.size())
4946 /// Returns the scalar element that will make up the ith
4947 /// element of the result of the vector shuffle.
4948 static SDValue getShuffleScalarElt(SDNode *N, unsigned Index, SelectionDAG &DAG,
4951 return SDValue(); // Limit search depth.
4953 SDValue V = SDValue(N, 0);
4954 EVT VT = V.getValueType();
4955 unsigned Opcode = V.getOpcode();
4957 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars.
4958 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) {
4959 int Elt = SV->getMaskElt(Index);
4962 return DAG.getUNDEF(VT.getVectorElementType());
4964 unsigned NumElems = VT.getVectorNumElements();
4965 SDValue NewV = (Elt < (int)NumElems) ? SV->getOperand(0)
4966 : SV->getOperand(1);
4967 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG, Depth+1);
4970 // Recurse into target specific vector shuffles to find scalars.
4971 if (isTargetShuffle(Opcode)) {
4972 MVT ShufVT = V.getSimpleValueType();
4973 unsigned NumElems = ShufVT.getVectorNumElements();
4974 SmallVector<int, 16> ShuffleMask;
4977 if (!getTargetShuffleMask(N, ShufVT, ShuffleMask, IsUnary))
4980 int Elt = ShuffleMask[Index];
4982 return DAG.getUNDEF(ShufVT.getVectorElementType());
4984 SDValue NewV = (Elt < (int)NumElems) ? N->getOperand(0)
4986 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG,
4990 // Actual nodes that may contain scalar elements
4991 if (Opcode == ISD::BITCAST) {
4992 V = V.getOperand(0);
4993 EVT SrcVT = V.getValueType();
4994 unsigned NumElems = VT.getVectorNumElements();
4996 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems)
5000 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR)
5001 return (Index == 0) ? V.getOperand(0)
5002 : DAG.getUNDEF(VT.getVectorElementType());
5004 if (V.getOpcode() == ISD::BUILD_VECTOR)
5005 return V.getOperand(Index);
5010 /// Custom lower build_vector of v16i8.
5011 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
5012 unsigned NumNonZero, unsigned NumZero,
5014 const X86Subtarget* Subtarget,
5015 const TargetLowering &TLI) {
5023 // SSE4.1 - use PINSRB to insert each byte directly.
5024 if (Subtarget->hasSSE41()) {
5025 for (unsigned i = 0; i < 16; ++i) {
5026 bool isNonZero = (NonZeros & (1 << i)) != 0;
5030 V = getZeroVector(MVT::v16i8, Subtarget, DAG, dl);
5032 V = DAG.getUNDEF(MVT::v16i8);
5035 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
5036 MVT::v16i8, V, Op.getOperand(i),
5037 DAG.getIntPtrConstant(i, dl));
5044 // Pre-SSE4.1 - merge byte pairs and insert with PINSRW.
5045 for (unsigned i = 0; i < 16; ++i) {
5046 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
5047 if (ThisIsNonZero && First) {
5049 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
5051 V = DAG.getUNDEF(MVT::v8i16);
5056 SDValue ThisElt, LastElt;
5057 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
5058 if (LastIsNonZero) {
5059 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
5060 MVT::i16, Op.getOperand(i-1));
5062 if (ThisIsNonZero) {
5063 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
5064 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
5065 ThisElt, DAG.getConstant(8, dl, MVT::i8));
5067 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
5071 if (ThisElt.getNode())
5072 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
5073 DAG.getIntPtrConstant(i/2, dl));
5077 return DAG.getBitcast(MVT::v16i8, V);
5080 /// Custom lower build_vector of v8i16.
5081 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
5082 unsigned NumNonZero, unsigned NumZero,
5084 const X86Subtarget* Subtarget,
5085 const TargetLowering &TLI) {
5092 for (unsigned i = 0; i < 8; ++i) {
5093 bool isNonZero = (NonZeros & (1 << i)) != 0;
5097 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
5099 V = DAG.getUNDEF(MVT::v8i16);
5102 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
5103 MVT::v8i16, V, Op.getOperand(i),
5104 DAG.getIntPtrConstant(i, dl));
5111 /// Custom lower build_vector of v4i32 or v4f32.
5112 static SDValue LowerBuildVectorv4x32(SDValue Op, SelectionDAG &DAG,
5113 const X86Subtarget *Subtarget,
5114 const TargetLowering &TLI) {
5115 // Find all zeroable elements.
5116 std::bitset<4> Zeroable;
5117 for (int i=0; i < 4; ++i) {
5118 SDValue Elt = Op->getOperand(i);
5119 Zeroable[i] = (Elt.getOpcode() == ISD::UNDEF || X86::isZeroNode(Elt));
5121 assert(Zeroable.size() - Zeroable.count() > 1 &&
5122 "We expect at least two non-zero elements!");
5124 // We only know how to deal with build_vector nodes where elements are either
5125 // zeroable or extract_vector_elt with constant index.
5126 SDValue FirstNonZero;
5127 unsigned FirstNonZeroIdx;
5128 for (unsigned i=0; i < 4; ++i) {
5131 SDValue Elt = Op->getOperand(i);
5132 if (Elt.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
5133 !isa<ConstantSDNode>(Elt.getOperand(1)))
5135 // Make sure that this node is extracting from a 128-bit vector.
5136 MVT VT = Elt.getOperand(0).getSimpleValueType();
5137 if (!VT.is128BitVector())
5139 if (!FirstNonZero.getNode()) {
5141 FirstNonZeroIdx = i;
5145 assert(FirstNonZero.getNode() && "Unexpected build vector of all zeros!");
5146 SDValue V1 = FirstNonZero.getOperand(0);
5147 MVT VT = V1.getSimpleValueType();
5149 // See if this build_vector can be lowered as a blend with zero.
5151 unsigned EltMaskIdx, EltIdx;
5153 for (EltIdx = 0; EltIdx < 4; ++EltIdx) {
5154 if (Zeroable[EltIdx]) {
5155 // The zero vector will be on the right hand side.
5156 Mask[EltIdx] = EltIdx+4;
5160 Elt = Op->getOperand(EltIdx);
5161 // By construction, Elt is a EXTRACT_VECTOR_ELT with constant index.
5162 EltMaskIdx = cast<ConstantSDNode>(Elt.getOperand(1))->getZExtValue();
5163 if (Elt.getOperand(0) != V1 || EltMaskIdx != EltIdx)
5165 Mask[EltIdx] = EltIdx;
5169 // Let the shuffle legalizer deal with blend operations.
5170 SDValue VZero = getZeroVector(VT, Subtarget, DAG, SDLoc(Op));
5171 if (V1.getSimpleValueType() != VT)
5172 V1 = DAG.getNode(ISD::BITCAST, SDLoc(V1), VT, V1);
5173 return DAG.getVectorShuffle(VT, SDLoc(V1), V1, VZero, &Mask[0]);
5176 // See if we can lower this build_vector to a INSERTPS.
5177 if (!Subtarget->hasSSE41())
5180 SDValue V2 = Elt.getOperand(0);
5181 if (Elt == FirstNonZero && EltIdx == FirstNonZeroIdx)
5184 bool CanFold = true;
5185 for (unsigned i = EltIdx + 1; i < 4 && CanFold; ++i) {
5189 SDValue Current = Op->getOperand(i);
5190 SDValue SrcVector = Current->getOperand(0);
5193 CanFold = SrcVector == V1 &&
5194 cast<ConstantSDNode>(Current.getOperand(1))->getZExtValue() == i;
5200 assert(V1.getNode() && "Expected at least two non-zero elements!");
5201 if (V1.getSimpleValueType() != MVT::v4f32)
5202 V1 = DAG.getNode(ISD::BITCAST, SDLoc(V1), MVT::v4f32, V1);
5203 if (V2.getSimpleValueType() != MVT::v4f32)
5204 V2 = DAG.getNode(ISD::BITCAST, SDLoc(V2), MVT::v4f32, V2);
5206 // Ok, we can emit an INSERTPS instruction.
5207 unsigned ZMask = Zeroable.to_ulong();
5209 unsigned InsertPSMask = EltMaskIdx << 6 | EltIdx << 4 | ZMask;
5210 assert((InsertPSMask & ~0xFFu) == 0 && "Invalid mask!");
5212 SDValue Result = DAG.getNode(X86ISD::INSERTPS, DL, MVT::v4f32, V1, V2,
5213 DAG.getIntPtrConstant(InsertPSMask, DL));
5214 return DAG.getBitcast(VT, Result);
5217 /// Return a vector logical shift node.
5218 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
5219 unsigned NumBits, SelectionDAG &DAG,
5220 const TargetLowering &TLI, SDLoc dl) {
5221 assert(VT.is128BitVector() && "Unknown type for VShift");
5222 MVT ShVT = MVT::v2i64;
5223 unsigned Opc = isLeft ? X86ISD::VSHLDQ : X86ISD::VSRLDQ;
5224 SrcOp = DAG.getBitcast(ShVT, SrcOp);
5225 MVT ScalarShiftTy = TLI.getScalarShiftAmountTy(DAG.getDataLayout(), VT);
5226 assert(NumBits % 8 == 0 && "Only support byte sized shifts");
5227 SDValue ShiftVal = DAG.getConstant(NumBits/8, dl, ScalarShiftTy);
5228 return DAG.getBitcast(VT, DAG.getNode(Opc, dl, ShVT, SrcOp, ShiftVal));
5232 LowerAsSplatVectorLoad(SDValue SrcOp, MVT VT, SDLoc dl, SelectionDAG &DAG) {
5234 // Check if the scalar load can be widened into a vector load. And if
5235 // the address is "base + cst" see if the cst can be "absorbed" into
5236 // the shuffle mask.
5237 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) {
5238 SDValue Ptr = LD->getBasePtr();
5239 if (!ISD::isNormalLoad(LD) || LD->isVolatile())
5241 EVT PVT = LD->getValueType(0);
5242 if (PVT != MVT::i32 && PVT != MVT::f32)
5247 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) {
5248 FI = FINode->getIndex();
5250 } else if (DAG.isBaseWithConstantOffset(Ptr) &&
5251 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
5252 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
5253 Offset = Ptr.getConstantOperandVal(1);
5254 Ptr = Ptr.getOperand(0);
5259 // FIXME: 256-bit vector instructions don't require a strict alignment,
5260 // improve this code to support it better.
5261 unsigned RequiredAlign = VT.getSizeInBits()/8;
5262 SDValue Chain = LD->getChain();
5263 // Make sure the stack object alignment is at least 16 or 32.
5264 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
5265 if (DAG.InferPtrAlignment(Ptr) < RequiredAlign) {
5266 if (MFI->isFixedObjectIndex(FI)) {
5267 // Can't change the alignment. FIXME: It's possible to compute
5268 // the exact stack offset and reference FI + adjust offset instead.
5269 // If someone *really* cares about this. That's the way to implement it.
5272 MFI->setObjectAlignment(FI, RequiredAlign);
5276 // (Offset % 16 or 32) must be multiple of 4. Then address is then
5277 // Ptr + (Offset & ~15).
5280 if ((Offset % RequiredAlign) & 3)
5282 int64_t StartOffset = Offset & ~int64_t(RequiredAlign - 1);
5285 Ptr = DAG.getNode(ISD::ADD, DL, Ptr.getValueType(), Ptr,
5286 DAG.getConstant(StartOffset, DL, Ptr.getValueType()));
5289 int EltNo = (Offset - StartOffset) >> 2;
5290 unsigned NumElems = VT.getVectorNumElements();
5292 EVT NVT = EVT::getVectorVT(*DAG.getContext(), PVT, NumElems);
5293 SDValue V1 = DAG.getLoad(NVT, dl, Chain, Ptr,
5294 LD->getPointerInfo().getWithOffset(StartOffset),
5295 false, false, false, 0);
5297 SmallVector<int, 8> Mask(NumElems, EltNo);
5299 return DAG.getVectorShuffle(NVT, dl, V1, DAG.getUNDEF(NVT), &Mask[0]);
5305 /// Given the initializing elements 'Elts' of a vector of type 'VT', see if the
5306 /// elements can be replaced by a single large load which has the same value as
5307 /// a build_vector or insert_subvector whose loaded operands are 'Elts'.
5309 /// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a
5311 /// FIXME: we'd also like to handle the case where the last elements are zero
5312 /// rather than undef via VZEXT_LOAD, but we do not detect that case today.
5313 /// There's even a handy isZeroNode for that purpose.
5314 static SDValue EltsFromConsecutiveLoads(EVT VT, ArrayRef<SDValue> Elts,
5315 SDLoc &DL, SelectionDAG &DAG,
5316 bool isAfterLegalize) {
5317 unsigned NumElems = Elts.size();
5319 LoadSDNode *LDBase = nullptr;
5320 unsigned LastLoadedElt = -1U;
5322 // For each element in the initializer, see if we've found a load or an undef.
5323 // If we don't find an initial load element, or later load elements are
5324 // non-consecutive, bail out.
5325 for (unsigned i = 0; i < NumElems; ++i) {
5326 SDValue Elt = Elts[i];
5327 // Look through a bitcast.
5328 if (Elt.getNode() && Elt.getOpcode() == ISD::BITCAST)
5329 Elt = Elt.getOperand(0);
5330 if (!Elt.getNode() ||
5331 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
5334 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
5336 LDBase = cast<LoadSDNode>(Elt.getNode());
5340 if (Elt.getOpcode() == ISD::UNDEF)
5343 LoadSDNode *LD = cast<LoadSDNode>(Elt);
5344 EVT LdVT = Elt.getValueType();
5345 // Each loaded element must be the correct fractional portion of the
5346 // requested vector load.
5347 if (LdVT.getSizeInBits() != VT.getSizeInBits() / NumElems)
5349 if (!DAG.isConsecutiveLoad(LD, LDBase, LdVT.getSizeInBits() / 8, i))
5354 // If we have found an entire vector of loads and undefs, then return a large
5355 // load of the entire vector width starting at the base pointer. If we found
5356 // consecutive loads for the low half, generate a vzext_load node.
5357 if (LastLoadedElt == NumElems - 1) {
5358 assert(LDBase && "Did not find base load for merging consecutive loads");
5359 EVT EltVT = LDBase->getValueType(0);
5360 // Ensure that the input vector size for the merged loads matches the
5361 // cumulative size of the input elements.
5362 if (VT.getSizeInBits() != EltVT.getSizeInBits() * NumElems)
5365 if (isAfterLegalize &&
5366 !DAG.getTargetLoweringInfo().isOperationLegal(ISD::LOAD, VT))
5369 SDValue NewLd = SDValue();
5371 NewLd = DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
5372 LDBase->getPointerInfo(), LDBase->isVolatile(),
5373 LDBase->isNonTemporal(), LDBase->isInvariant(),
5374 LDBase->getAlignment());
5376 if (LDBase->hasAnyUseOfValue(1)) {
5377 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
5379 SDValue(NewLd.getNode(), 1));
5380 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
5381 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
5382 SDValue(NewLd.getNode(), 1));
5388 //TODO: The code below fires only for for loading the low v2i32 / v2f32
5389 //of a v4i32 / v4f32. It's probably worth generalizing.
5390 EVT EltVT = VT.getVectorElementType();
5391 if (NumElems == 4 && LastLoadedElt == 1 && (EltVT.getSizeInBits() == 32) &&
5392 DAG.getTargetLoweringInfo().isTypeLegal(MVT::v2i64)) {
5393 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
5394 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() };
5396 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys, Ops, MVT::i64,
5397 LDBase->getPointerInfo(),
5398 LDBase->getAlignment(),
5399 false/*isVolatile*/, true/*ReadMem*/,
5402 // Make sure the newly-created LOAD is in the same position as LDBase in
5403 // terms of dependency. We create a TokenFactor for LDBase and ResNode, and
5404 // update uses of LDBase's output chain to use the TokenFactor.
5405 if (LDBase->hasAnyUseOfValue(1)) {
5406 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
5407 SDValue(LDBase, 1), SDValue(ResNode.getNode(), 1));
5408 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
5409 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
5410 SDValue(ResNode.getNode(), 1));
5413 return DAG.getBitcast(VT, ResNode);
5418 /// LowerVectorBroadcast - Attempt to use the vbroadcast instruction
5419 /// to generate a splat value for the following cases:
5420 /// 1. A splat BUILD_VECTOR which uses a single scalar load, or a constant.
5421 /// 2. A splat shuffle which uses a scalar_to_vector node which comes from
5422 /// a scalar load, or a constant.
5423 /// The VBROADCAST node is returned when a pattern is found,
5424 /// or SDValue() otherwise.
5425 static SDValue LowerVectorBroadcast(SDValue Op, const X86Subtarget* Subtarget,
5426 SelectionDAG &DAG) {
5427 // VBROADCAST requires AVX.
5428 // TODO: Splats could be generated for non-AVX CPUs using SSE
5429 // instructions, but there's less potential gain for only 128-bit vectors.
5430 if (!Subtarget->hasAVX())
5433 MVT VT = Op.getSimpleValueType();
5436 assert((VT.is128BitVector() || VT.is256BitVector() || VT.is512BitVector()) &&
5437 "Unsupported vector type for broadcast.");
5442 switch (Op.getOpcode()) {
5444 // Unknown pattern found.
5447 case ISD::BUILD_VECTOR: {
5448 auto *BVOp = cast<BuildVectorSDNode>(Op.getNode());
5449 BitVector UndefElements;
5450 SDValue Splat = BVOp->getSplatValue(&UndefElements);
5452 // We need a splat of a single value to use broadcast, and it doesn't
5453 // make any sense if the value is only in one element of the vector.
5454 if (!Splat || (VT.getVectorNumElements() - UndefElements.count()) <= 1)
5458 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
5459 Ld.getOpcode() == ISD::ConstantFP);
5461 // Make sure that all of the users of a non-constant load are from the
5462 // BUILD_VECTOR node.
5463 if (!ConstSplatVal && !BVOp->isOnlyUserOf(Ld.getNode()))
5468 case ISD::VECTOR_SHUFFLE: {
5469 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
5471 // Shuffles must have a splat mask where the first element is
5473 if ((!SVOp->isSplat()) || SVOp->getMaskElt(0) != 0)
5476 SDValue Sc = Op.getOperand(0);
5477 if (Sc.getOpcode() != ISD::SCALAR_TO_VECTOR &&
5478 Sc.getOpcode() != ISD::BUILD_VECTOR) {
5480 if (!Subtarget->hasInt256())
5483 // Use the register form of the broadcast instruction available on AVX2.
5484 if (VT.getSizeInBits() >= 256)
5485 Sc = Extract128BitVector(Sc, 0, DAG, dl);
5486 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Sc);
5489 Ld = Sc.getOperand(0);
5490 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
5491 Ld.getOpcode() == ISD::ConstantFP);
5493 // The scalar_to_vector node and the suspected
5494 // load node must have exactly one user.
5495 // Constants may have multiple users.
5497 // AVX-512 has register version of the broadcast
5498 bool hasRegVer = Subtarget->hasAVX512() && VT.is512BitVector() &&
5499 Ld.getValueType().getSizeInBits() >= 32;
5500 if (!ConstSplatVal && ((!Sc.hasOneUse() || !Ld.hasOneUse()) &&
5507 unsigned ScalarSize = Ld.getValueType().getSizeInBits();
5508 bool IsGE256 = (VT.getSizeInBits() >= 256);
5510 // When optimizing for size, generate up to 5 extra bytes for a broadcast
5511 // instruction to save 8 or more bytes of constant pool data.
5512 // TODO: If multiple splats are generated to load the same constant,
5513 // it may be detrimental to overall size. There needs to be a way to detect
5514 // that condition to know if this is truly a size win.
5515 bool OptForSize = DAG.getMachineFunction().getFunction()->optForSize();
5517 // Handle broadcasting a single constant scalar from the constant pool
5519 // On Sandybridge (no AVX2), it is still better to load a constant vector
5520 // from the constant pool and not to broadcast it from a scalar.
5521 // But override that restriction when optimizing for size.
5522 // TODO: Check if splatting is recommended for other AVX-capable CPUs.
5523 if (ConstSplatVal && (Subtarget->hasAVX2() || OptForSize)) {
5524 EVT CVT = Ld.getValueType();
5525 assert(!CVT.isVector() && "Must not broadcast a vector type");
5527 // Splat f32, i32, v4f64, v4i64 in all cases with AVX2.
5528 // For size optimization, also splat v2f64 and v2i64, and for size opt
5529 // with AVX2, also splat i8 and i16.
5530 // With pattern matching, the VBROADCAST node may become a VMOVDDUP.
5531 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64) ||
5532 (OptForSize && (ScalarSize == 64 || Subtarget->hasAVX2()))) {
5533 const Constant *C = nullptr;
5534 if (ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Ld))
5535 C = CI->getConstantIntValue();
5536 else if (ConstantFPSDNode *CF = dyn_cast<ConstantFPSDNode>(Ld))
5537 C = CF->getConstantFPValue();
5539 assert(C && "Invalid constant type");
5541 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5543 DAG.getConstantPool(C, TLI.getPointerTy(DAG.getDataLayout()));
5544 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
5546 CVT, dl, DAG.getEntryNode(), CP,
5547 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()), false,
5548 false, false, Alignment);
5550 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5554 bool IsLoad = ISD::isNormalLoad(Ld.getNode());
5556 // Handle AVX2 in-register broadcasts.
5557 if (!IsLoad && Subtarget->hasInt256() &&
5558 (ScalarSize == 32 || (IsGE256 && ScalarSize == 64)))
5559 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5561 // The scalar source must be a normal load.
5565 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64) ||
5566 (Subtarget->hasVLX() && ScalarSize == 64))
5567 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5569 // The integer check is needed for the 64-bit into 128-bit so it doesn't match
5570 // double since there is no vbroadcastsd xmm
5571 if (Subtarget->hasInt256() && Ld.getValueType().isInteger()) {
5572 if (ScalarSize == 8 || ScalarSize == 16 || ScalarSize == 64)
5573 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5576 // Unsupported broadcast.
5580 /// \brief For an EXTRACT_VECTOR_ELT with a constant index return the real
5581 /// underlying vector and index.
5583 /// Modifies \p ExtractedFromVec to the real vector and returns the real
5585 static int getUnderlyingExtractedFromVec(SDValue &ExtractedFromVec,
5587 int Idx = cast<ConstantSDNode>(ExtIdx)->getZExtValue();
5588 if (!isa<ShuffleVectorSDNode>(ExtractedFromVec))
5591 // For 256-bit vectors, LowerEXTRACT_VECTOR_ELT_SSE4 may have already
5593 // (extract_vector_elt (v8f32 %vreg1), Constant<6>)
5595 // (extract_vector_elt (vector_shuffle<2,u,u,u>
5596 // (extract_subvector (v8f32 %vreg0), Constant<4>),
5599 // In this case the vector is the extract_subvector expression and the index
5600 // is 2, as specified by the shuffle.
5601 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(ExtractedFromVec);
5602 SDValue ShuffleVec = SVOp->getOperand(0);
5603 MVT ShuffleVecVT = ShuffleVec.getSimpleValueType();
5604 assert(ShuffleVecVT.getVectorElementType() ==
5605 ExtractedFromVec.getSimpleValueType().getVectorElementType());
5607 int ShuffleIdx = SVOp->getMaskElt(Idx);
5608 if (isUndefOrInRange(ShuffleIdx, 0, ShuffleVecVT.getVectorNumElements())) {
5609 ExtractedFromVec = ShuffleVec;
5615 static SDValue buildFromShuffleMostly(SDValue Op, SelectionDAG &DAG) {
5616 MVT VT = Op.getSimpleValueType();
5618 // Skip if insert_vec_elt is not supported.
5619 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5620 if (!TLI.isOperationLegalOrCustom(ISD::INSERT_VECTOR_ELT, VT))
5624 unsigned NumElems = Op.getNumOperands();
5628 SmallVector<unsigned, 4> InsertIndices;
5629 SmallVector<int, 8> Mask(NumElems, -1);
5631 for (unsigned i = 0; i != NumElems; ++i) {
5632 unsigned Opc = Op.getOperand(i).getOpcode();
5634 if (Opc == ISD::UNDEF)
5637 if (Opc != ISD::EXTRACT_VECTOR_ELT) {
5638 // Quit if more than 1 elements need inserting.
5639 if (InsertIndices.size() > 1)
5642 InsertIndices.push_back(i);
5646 SDValue ExtractedFromVec = Op.getOperand(i).getOperand(0);
5647 SDValue ExtIdx = Op.getOperand(i).getOperand(1);
5648 // Quit if non-constant index.
5649 if (!isa<ConstantSDNode>(ExtIdx))
5651 int Idx = getUnderlyingExtractedFromVec(ExtractedFromVec, ExtIdx);
5653 // Quit if extracted from vector of different type.
5654 if (ExtractedFromVec.getValueType() != VT)
5657 if (!VecIn1.getNode())
5658 VecIn1 = ExtractedFromVec;
5659 else if (VecIn1 != ExtractedFromVec) {
5660 if (!VecIn2.getNode())
5661 VecIn2 = ExtractedFromVec;
5662 else if (VecIn2 != ExtractedFromVec)
5663 // Quit if more than 2 vectors to shuffle
5667 if (ExtractedFromVec == VecIn1)
5669 else if (ExtractedFromVec == VecIn2)
5670 Mask[i] = Idx + NumElems;
5673 if (!VecIn1.getNode())
5676 VecIn2 = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT);
5677 SDValue NV = DAG.getVectorShuffle(VT, DL, VecIn1, VecIn2, &Mask[0]);
5678 for (unsigned i = 0, e = InsertIndices.size(); i != e; ++i) {
5679 unsigned Idx = InsertIndices[i];
5680 NV = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VT, NV, Op.getOperand(Idx),
5681 DAG.getIntPtrConstant(Idx, DL));
5687 static SDValue ConvertI1VectorToInteger(SDValue Op, SelectionDAG &DAG) {
5688 assert(ISD::isBuildVectorOfConstantSDNodes(Op.getNode()) &&
5689 Op.getScalarValueSizeInBits() == 1 &&
5690 "Can not convert non-constant vector");
5691 uint64_t Immediate = 0;
5692 for (unsigned idx = 0, e = Op.getNumOperands(); idx < e; ++idx) {
5693 SDValue In = Op.getOperand(idx);
5694 if (In.getOpcode() != ISD::UNDEF)
5695 Immediate |= cast<ConstantSDNode>(In)->getZExtValue() << idx;
5699 MVT::getIntegerVT(std::max((int)Op.getValueType().getSizeInBits(), 8));
5700 return DAG.getConstant(Immediate, dl, VT);
5702 // Lower BUILD_VECTOR operation for v8i1 and v16i1 types.
5704 X86TargetLowering::LowerBUILD_VECTORvXi1(SDValue Op, SelectionDAG &DAG) const {
5706 MVT VT = Op.getSimpleValueType();
5707 assert((VT.getVectorElementType() == MVT::i1) &&
5708 "Unexpected type in LowerBUILD_VECTORvXi1!");
5711 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
5712 SDValue Cst = DAG.getTargetConstant(0, dl, MVT::i1);
5713 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
5714 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
5717 if (ISD::isBuildVectorAllOnes(Op.getNode())) {
5718 SDValue Cst = DAG.getTargetConstant(1, dl, MVT::i1);
5719 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
5720 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
5723 if (ISD::isBuildVectorOfConstantSDNodes(Op.getNode())) {
5724 SDValue Imm = ConvertI1VectorToInteger(Op, DAG);
5725 if (Imm.getValueSizeInBits() == VT.getSizeInBits())
5726 return DAG.getBitcast(VT, Imm);
5727 SDValue ExtVec = DAG.getBitcast(MVT::v8i1, Imm);
5728 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, ExtVec,
5729 DAG.getIntPtrConstant(0, dl));
5732 // Vector has one or more non-const elements
5733 uint64_t Immediate = 0;
5734 SmallVector<unsigned, 16> NonConstIdx;
5735 bool IsSplat = true;
5736 bool HasConstElts = false;
5738 for (unsigned idx = 0, e = Op.getNumOperands(); idx < e; ++idx) {
5739 SDValue In = Op.getOperand(idx);
5740 if (In.getOpcode() == ISD::UNDEF)
5742 if (!isa<ConstantSDNode>(In))
5743 NonConstIdx.push_back(idx);
5745 Immediate |= cast<ConstantSDNode>(In)->getZExtValue() << idx;
5746 HasConstElts = true;
5750 else if (In != Op.getOperand(SplatIdx))
5754 // for splat use " (select i1 splat_elt, all-ones, all-zeroes)"
5756 return DAG.getNode(ISD::SELECT, dl, VT, Op.getOperand(SplatIdx),
5757 DAG.getConstant(1, dl, VT),
5758 DAG.getConstant(0, dl, VT));
5760 // insert elements one by one
5764 MVT ImmVT = MVT::getIntegerVT(std::max((int)VT.getSizeInBits(), 8));
5765 Imm = DAG.getConstant(Immediate, dl, ImmVT);
5767 else if (HasConstElts)
5768 Imm = DAG.getConstant(0, dl, VT);
5770 Imm = DAG.getUNDEF(VT);
5771 if (Imm.getValueSizeInBits() == VT.getSizeInBits())
5772 DstVec = DAG.getBitcast(VT, Imm);
5774 SDValue ExtVec = DAG.getBitcast(MVT::v8i1, Imm);
5775 DstVec = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, ExtVec,
5776 DAG.getIntPtrConstant(0, dl));
5779 for (unsigned i = 0; i < NonConstIdx.size(); ++i) {
5780 unsigned InsertIdx = NonConstIdx[i];
5781 DstVec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, DstVec,
5782 Op.getOperand(InsertIdx),
5783 DAG.getIntPtrConstant(InsertIdx, dl));
5788 /// \brief Return true if \p N implements a horizontal binop and return the
5789 /// operands for the horizontal binop into V0 and V1.
5791 /// This is a helper function of LowerToHorizontalOp().
5792 /// This function checks that the build_vector \p N in input implements a
5793 /// horizontal operation. Parameter \p Opcode defines the kind of horizontal
5794 /// operation to match.
5795 /// For example, if \p Opcode is equal to ISD::ADD, then this function
5796 /// checks if \p N implements a horizontal arithmetic add; if instead \p Opcode
5797 /// is equal to ISD::SUB, then this function checks if this is a horizontal
5800 /// This function only analyzes elements of \p N whose indices are
5801 /// in range [BaseIdx, LastIdx).
5802 static bool isHorizontalBinOp(const BuildVectorSDNode *N, unsigned Opcode,
5804 unsigned BaseIdx, unsigned LastIdx,
5805 SDValue &V0, SDValue &V1) {
5806 EVT VT = N->getValueType(0);
5808 assert(BaseIdx * 2 <= LastIdx && "Invalid Indices in input!");
5809 assert(VT.isVector() && VT.getVectorNumElements() >= LastIdx &&
5810 "Invalid Vector in input!");
5812 bool IsCommutable = (Opcode == ISD::ADD || Opcode == ISD::FADD);
5813 bool CanFold = true;
5814 unsigned ExpectedVExtractIdx = BaseIdx;
5815 unsigned NumElts = LastIdx - BaseIdx;
5816 V0 = DAG.getUNDEF(VT);
5817 V1 = DAG.getUNDEF(VT);
5819 // Check if N implements a horizontal binop.
5820 for (unsigned i = 0, e = NumElts; i != e && CanFold; ++i) {
5821 SDValue Op = N->getOperand(i + BaseIdx);
5824 if (Op->getOpcode() == ISD::UNDEF) {
5825 // Update the expected vector extract index.
5826 if (i * 2 == NumElts)
5827 ExpectedVExtractIdx = BaseIdx;
5828 ExpectedVExtractIdx += 2;
5832 CanFold = Op->getOpcode() == Opcode && Op->hasOneUse();
5837 SDValue Op0 = Op.getOperand(0);
5838 SDValue Op1 = Op.getOperand(1);
5840 // Try to match the following pattern:
5841 // (BINOP (extract_vector_elt A, I), (extract_vector_elt A, I+1))
5842 CanFold = (Op0.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
5843 Op1.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
5844 Op0.getOperand(0) == Op1.getOperand(0) &&
5845 isa<ConstantSDNode>(Op0.getOperand(1)) &&
5846 isa<ConstantSDNode>(Op1.getOperand(1)));
5850 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
5851 unsigned I1 = cast<ConstantSDNode>(Op1.getOperand(1))->getZExtValue();
5853 if (i * 2 < NumElts) {
5854 if (V0.getOpcode() == ISD::UNDEF) {
5855 V0 = Op0.getOperand(0);
5856 if (V0.getValueType() != VT)
5860 if (V1.getOpcode() == ISD::UNDEF) {
5861 V1 = Op0.getOperand(0);
5862 if (V1.getValueType() != VT)
5865 if (i * 2 == NumElts)
5866 ExpectedVExtractIdx = BaseIdx;
5869 SDValue Expected = (i * 2 < NumElts) ? V0 : V1;
5870 if (I0 == ExpectedVExtractIdx)
5871 CanFold = I1 == I0 + 1 && Op0.getOperand(0) == Expected;
5872 else if (IsCommutable && I1 == ExpectedVExtractIdx) {
5873 // Try to match the following dag sequence:
5874 // (BINOP (extract_vector_elt A, I+1), (extract_vector_elt A, I))
5875 CanFold = I0 == I1 + 1 && Op1.getOperand(0) == Expected;
5879 ExpectedVExtractIdx += 2;
5885 /// \brief Emit a sequence of two 128-bit horizontal add/sub followed by
5886 /// a concat_vector.
5888 /// This is a helper function of LowerToHorizontalOp().
5889 /// This function expects two 256-bit vectors called V0 and V1.
5890 /// At first, each vector is split into two separate 128-bit vectors.
5891 /// Then, the resulting 128-bit vectors are used to implement two
5892 /// horizontal binary operations.
5894 /// The kind of horizontal binary operation is defined by \p X86Opcode.
5896 /// \p Mode specifies how the 128-bit parts of V0 and V1 are passed in input to
5897 /// the two new horizontal binop.
5898 /// When Mode is set, the first horizontal binop dag node would take as input
5899 /// the lower 128-bit of V0 and the upper 128-bit of V0. The second
5900 /// horizontal binop dag node would take as input the lower 128-bit of V1
5901 /// and the upper 128-bit of V1.
5903 /// HADD V0_LO, V0_HI
5904 /// HADD V1_LO, V1_HI
5906 /// Otherwise, the first horizontal binop dag node takes as input the lower
5907 /// 128-bit of V0 and the lower 128-bit of V1, and the second horizontal binop
5908 /// dag node takes the upper 128-bit of V0 and the upper 128-bit of V1.
5910 /// HADD V0_LO, V1_LO
5911 /// HADD V0_HI, V1_HI
5913 /// If \p isUndefLO is set, then the algorithm propagates UNDEF to the lower
5914 /// 128-bits of the result. If \p isUndefHI is set, then UNDEF is propagated to
5915 /// the upper 128-bits of the result.
5916 static SDValue ExpandHorizontalBinOp(const SDValue &V0, const SDValue &V1,
5917 SDLoc DL, SelectionDAG &DAG,
5918 unsigned X86Opcode, bool Mode,
5919 bool isUndefLO, bool isUndefHI) {
5920 EVT VT = V0.getValueType();
5921 assert(VT.is256BitVector() && VT == V1.getValueType() &&
5922 "Invalid nodes in input!");
5924 unsigned NumElts = VT.getVectorNumElements();
5925 SDValue V0_LO = Extract128BitVector(V0, 0, DAG, DL);
5926 SDValue V0_HI = Extract128BitVector(V0, NumElts/2, DAG, DL);
5927 SDValue V1_LO = Extract128BitVector(V1, 0, DAG, DL);
5928 SDValue V1_HI = Extract128BitVector(V1, NumElts/2, DAG, DL);
5929 EVT NewVT = V0_LO.getValueType();
5931 SDValue LO = DAG.getUNDEF(NewVT);
5932 SDValue HI = DAG.getUNDEF(NewVT);
5935 // Don't emit a horizontal binop if the result is expected to be UNDEF.
5936 if (!isUndefLO && V0->getOpcode() != ISD::UNDEF)
5937 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V0_HI);
5938 if (!isUndefHI && V1->getOpcode() != ISD::UNDEF)
5939 HI = DAG.getNode(X86Opcode, DL, NewVT, V1_LO, V1_HI);
5941 // Don't emit a horizontal binop if the result is expected to be UNDEF.
5942 if (!isUndefLO && (V0_LO->getOpcode() != ISD::UNDEF ||
5943 V1_LO->getOpcode() != ISD::UNDEF))
5944 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V1_LO);
5946 if (!isUndefHI && (V0_HI->getOpcode() != ISD::UNDEF ||
5947 V1_HI->getOpcode() != ISD::UNDEF))
5948 HI = DAG.getNode(X86Opcode, DL, NewVT, V0_HI, V1_HI);
5951 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LO, HI);
5954 /// Try to fold a build_vector that performs an 'addsub' to an X86ISD::ADDSUB
5956 static SDValue LowerToAddSub(const BuildVectorSDNode *BV,
5957 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
5958 MVT VT = BV->getSimpleValueType(0);
5959 if ((!Subtarget->hasSSE3() || (VT != MVT::v4f32 && VT != MVT::v2f64)) &&
5960 (!Subtarget->hasAVX() || (VT != MVT::v8f32 && VT != MVT::v4f64)))
5964 unsigned NumElts = VT.getVectorNumElements();
5965 SDValue InVec0 = DAG.getUNDEF(VT);
5966 SDValue InVec1 = DAG.getUNDEF(VT);
5968 assert((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v4f32 ||
5969 VT == MVT::v2f64) && "build_vector with an invalid type found!");
5971 // Odd-numbered elements in the input build vector are obtained from
5972 // adding two integer/float elements.
5973 // Even-numbered elements in the input build vector are obtained from
5974 // subtracting two integer/float elements.
5975 unsigned ExpectedOpcode = ISD::FSUB;
5976 unsigned NextExpectedOpcode = ISD::FADD;
5977 bool AddFound = false;
5978 bool SubFound = false;
5980 for (unsigned i = 0, e = NumElts; i != e; ++i) {
5981 SDValue Op = BV->getOperand(i);
5983 // Skip 'undef' values.
5984 unsigned Opcode = Op.getOpcode();
5985 if (Opcode == ISD::UNDEF) {
5986 std::swap(ExpectedOpcode, NextExpectedOpcode);
5990 // Early exit if we found an unexpected opcode.
5991 if (Opcode != ExpectedOpcode)
5994 SDValue Op0 = Op.getOperand(0);
5995 SDValue Op1 = Op.getOperand(1);
5997 // Try to match the following pattern:
5998 // (BINOP (extract_vector_elt A, i), (extract_vector_elt B, i))
5999 // Early exit if we cannot match that sequence.
6000 if (Op0.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
6001 Op1.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
6002 !isa<ConstantSDNode>(Op0.getOperand(1)) ||
6003 !isa<ConstantSDNode>(Op1.getOperand(1)) ||
6004 Op0.getOperand(1) != Op1.getOperand(1))
6007 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
6011 // We found a valid add/sub node. Update the information accordingly.
6017 // Update InVec0 and InVec1.
6018 if (InVec0.getOpcode() == ISD::UNDEF) {
6019 InVec0 = Op0.getOperand(0);
6020 if (InVec0.getSimpleValueType() != VT)
6023 if (InVec1.getOpcode() == ISD::UNDEF) {
6024 InVec1 = Op1.getOperand(0);
6025 if (InVec1.getSimpleValueType() != VT)
6029 // Make sure that operands in input to each add/sub node always
6030 // come from a same pair of vectors.
6031 if (InVec0 != Op0.getOperand(0)) {
6032 if (ExpectedOpcode == ISD::FSUB)
6035 // FADD is commutable. Try to commute the operands
6036 // and then test again.
6037 std::swap(Op0, Op1);
6038 if (InVec0 != Op0.getOperand(0))
6042 if (InVec1 != Op1.getOperand(0))
6045 // Update the pair of expected opcodes.
6046 std::swap(ExpectedOpcode, NextExpectedOpcode);
6049 // Don't try to fold this build_vector into an ADDSUB if the inputs are undef.
6050 if (AddFound && SubFound && InVec0.getOpcode() != ISD::UNDEF &&
6051 InVec1.getOpcode() != ISD::UNDEF)
6052 return DAG.getNode(X86ISD::ADDSUB, DL, VT, InVec0, InVec1);
6057 /// Lower BUILD_VECTOR to a horizontal add/sub operation if possible.
6058 static SDValue LowerToHorizontalOp(const BuildVectorSDNode *BV,
6059 const X86Subtarget *Subtarget,
6060 SelectionDAG &DAG) {
6061 MVT VT = BV->getSimpleValueType(0);
6062 unsigned NumElts = VT.getVectorNumElements();
6063 unsigned NumUndefsLO = 0;
6064 unsigned NumUndefsHI = 0;
6065 unsigned Half = NumElts/2;
6067 // Count the number of UNDEF operands in the build_vector in input.
6068 for (unsigned i = 0, e = Half; i != e; ++i)
6069 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
6072 for (unsigned i = Half, e = NumElts; i != e; ++i)
6073 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
6076 // Early exit if this is either a build_vector of all UNDEFs or all the
6077 // operands but one are UNDEF.
6078 if (NumUndefsLO + NumUndefsHI + 1 >= NumElts)
6082 SDValue InVec0, InVec1;
6083 if ((VT == MVT::v4f32 || VT == MVT::v2f64) && Subtarget->hasSSE3()) {
6084 // Try to match an SSE3 float HADD/HSUB.
6085 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
6086 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
6088 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
6089 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
6090 } else if ((VT == MVT::v4i32 || VT == MVT::v8i16) && Subtarget->hasSSSE3()) {
6091 // Try to match an SSSE3 integer HADD/HSUB.
6092 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
6093 return DAG.getNode(X86ISD::HADD, DL, VT, InVec0, InVec1);
6095 if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
6096 return DAG.getNode(X86ISD::HSUB, DL, VT, InVec0, InVec1);
6099 if (!Subtarget->hasAVX())
6102 if ((VT == MVT::v8f32 || VT == MVT::v4f64)) {
6103 // Try to match an AVX horizontal add/sub of packed single/double
6104 // precision floating point values from 256-bit vectors.
6105 SDValue InVec2, InVec3;
6106 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, Half, InVec0, InVec1) &&
6107 isHorizontalBinOp(BV, ISD::FADD, DAG, Half, NumElts, InVec2, InVec3) &&
6108 ((InVec0.getOpcode() == ISD::UNDEF ||
6109 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6110 ((InVec1.getOpcode() == ISD::UNDEF ||
6111 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6112 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
6114 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, Half, InVec0, InVec1) &&
6115 isHorizontalBinOp(BV, ISD::FSUB, DAG, Half, NumElts, InVec2, InVec3) &&
6116 ((InVec0.getOpcode() == ISD::UNDEF ||
6117 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6118 ((InVec1.getOpcode() == ISD::UNDEF ||
6119 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6120 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
6121 } else if (VT == MVT::v8i32 || VT == MVT::v16i16) {
6122 // Try to match an AVX2 horizontal add/sub of signed integers.
6123 SDValue InVec2, InVec3;
6125 bool CanFold = true;
6127 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, Half, InVec0, InVec1) &&
6128 isHorizontalBinOp(BV, ISD::ADD, DAG, Half, NumElts, InVec2, InVec3) &&
6129 ((InVec0.getOpcode() == ISD::UNDEF ||
6130 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6131 ((InVec1.getOpcode() == ISD::UNDEF ||
6132 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6133 X86Opcode = X86ISD::HADD;
6134 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, Half, InVec0, InVec1) &&
6135 isHorizontalBinOp(BV, ISD::SUB, DAG, Half, NumElts, InVec2, InVec3) &&
6136 ((InVec0.getOpcode() == ISD::UNDEF ||
6137 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6138 ((InVec1.getOpcode() == ISD::UNDEF ||
6139 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6140 X86Opcode = X86ISD::HSUB;
6145 // Fold this build_vector into a single horizontal add/sub.
6146 // Do this only if the target has AVX2.
6147 if (Subtarget->hasAVX2())
6148 return DAG.getNode(X86Opcode, DL, VT, InVec0, InVec1);
6150 // Do not try to expand this build_vector into a pair of horizontal
6151 // add/sub if we can emit a pair of scalar add/sub.
6152 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
6155 // Convert this build_vector into a pair of horizontal binop followed by
6157 bool isUndefLO = NumUndefsLO == Half;
6158 bool isUndefHI = NumUndefsHI == Half;
6159 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, false,
6160 isUndefLO, isUndefHI);
6164 if ((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v8i32 ||
6165 VT == MVT::v16i16) && Subtarget->hasAVX()) {
6167 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
6168 X86Opcode = X86ISD::HADD;
6169 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
6170 X86Opcode = X86ISD::HSUB;
6171 else if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
6172 X86Opcode = X86ISD::FHADD;
6173 else if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
6174 X86Opcode = X86ISD::FHSUB;
6178 // Don't try to expand this build_vector into a pair of horizontal add/sub
6179 // if we can simply emit a pair of scalar add/sub.
6180 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
6183 // Convert this build_vector into two horizontal add/sub followed by
6185 bool isUndefLO = NumUndefsLO == Half;
6186 bool isUndefHI = NumUndefsHI == Half;
6187 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, true,
6188 isUndefLO, isUndefHI);
6195 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
6198 MVT VT = Op.getSimpleValueType();
6199 MVT ExtVT = VT.getVectorElementType();
6200 unsigned NumElems = Op.getNumOperands();
6202 // Generate vectors for predicate vectors.
6203 if (VT.getVectorElementType() == MVT::i1 && Subtarget->hasAVX512())
6204 return LowerBUILD_VECTORvXi1(Op, DAG);
6206 // Vectors containing all zeros can be matched by pxor and xorps later
6207 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
6208 // Canonicalize this to <4 x i32> to 1) ensure the zero vectors are CSE'd
6209 // and 2) ensure that i64 scalars are eliminated on x86-32 hosts.
6210 if (VT == MVT::v4i32 || VT == MVT::v8i32 || VT == MVT::v16i32)
6213 return getZeroVector(VT, Subtarget, DAG, dl);
6216 // Vectors containing all ones can be matched by pcmpeqd on 128-bit width
6217 // vectors or broken into v4i32 operations on 256-bit vectors. AVX2 can use
6218 // vpcmpeqd on 256-bit vectors.
6219 if (Subtarget->hasSSE2() && ISD::isBuildVectorAllOnes(Op.getNode())) {
6220 if (VT == MVT::v4i32 || (VT == MVT::v8i32 && Subtarget->hasInt256()))
6223 if (!VT.is512BitVector())
6224 return getOnesVector(VT, Subtarget, DAG, dl);
6227 BuildVectorSDNode *BV = cast<BuildVectorSDNode>(Op.getNode());
6228 if (SDValue AddSub = LowerToAddSub(BV, Subtarget, DAG))
6230 if (SDValue HorizontalOp = LowerToHorizontalOp(BV, Subtarget, DAG))
6231 return HorizontalOp;
6232 if (SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG))
6235 unsigned EVTBits = ExtVT.getSizeInBits();
6237 unsigned NumZero = 0;
6238 unsigned NumNonZero = 0;
6239 uint64_t NonZeros = 0;
6240 bool IsAllConstants = true;
6241 SmallSet<SDValue, 8> Values;
6242 for (unsigned i = 0; i < NumElems; ++i) {
6243 SDValue Elt = Op.getOperand(i);
6244 if (Elt.getOpcode() == ISD::UNDEF)
6247 if (Elt.getOpcode() != ISD::Constant &&
6248 Elt.getOpcode() != ISD::ConstantFP)
6249 IsAllConstants = false;
6250 if (X86::isZeroNode(Elt))
6253 assert(i < sizeof(NonZeros) * 8); // Make sure the shift is within range.
6254 NonZeros |= ((uint64_t)1 << i);
6259 // All undef vector. Return an UNDEF. All zero vectors were handled above.
6260 if (NumNonZero == 0)
6261 return DAG.getUNDEF(VT);
6263 // Special case for single non-zero, non-undef, element.
6264 if (NumNonZero == 1) {
6265 unsigned Idx = countTrailingZeros(NonZeros);
6266 SDValue Item = Op.getOperand(Idx);
6268 // If this is an insertion of an i64 value on x86-32, and if the top bits of
6269 // the value are obviously zero, truncate the value to i32 and do the
6270 // insertion that way. Only do this if the value is non-constant or if the
6271 // value is a constant being inserted into element 0. It is cheaper to do
6272 // a constant pool load than it is to do a movd + shuffle.
6273 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
6274 (!IsAllConstants || Idx == 0)) {
6275 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
6277 assert(VT == MVT::v2i64 && "Expected an SSE value type!");
6278 MVT VecVT = MVT::v4i32;
6280 // Truncate the value (which may itself be a constant) to i32, and
6281 // convert it to a vector with movd (S2V+shuffle to zero extend).
6282 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
6283 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
6284 return DAG.getBitcast(VT, getShuffleVectorZeroOrUndef(
6285 Item, Idx * 2, true, Subtarget, DAG));
6289 // If we have a constant or non-constant insertion into the low element of
6290 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
6291 // the rest of the elements. This will be matched as movd/movq/movss/movsd
6292 // depending on what the source datatype is.
6295 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6297 if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
6298 (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
6299 if (VT.is512BitVector()) {
6300 SDValue ZeroVec = getZeroVector(VT, Subtarget, DAG, dl);
6301 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, ZeroVec,
6302 Item, DAG.getIntPtrConstant(0, dl));
6304 assert((VT.is128BitVector() || VT.is256BitVector()) &&
6305 "Expected an SSE value type!");
6306 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6307 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
6308 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6311 // We can't directly insert an i8 or i16 into a vector, so zero extend
6313 if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
6314 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
6315 if (VT.is256BitVector()) {
6316 if (Subtarget->hasAVX()) {
6317 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v8i32, Item);
6318 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6320 // Without AVX, we need to extend to a 128-bit vector and then
6321 // insert into the 256-bit vector.
6322 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
6323 SDValue ZeroVec = getZeroVector(MVT::v8i32, Subtarget, DAG, dl);
6324 Item = Insert128BitVector(ZeroVec, Item, 0, DAG, dl);
6327 assert(VT.is128BitVector() && "Expected an SSE value type!");
6328 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
6329 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6331 return DAG.getBitcast(VT, Item);
6335 // Is it a vector logical left shift?
6336 if (NumElems == 2 && Idx == 1 &&
6337 X86::isZeroNode(Op.getOperand(0)) &&
6338 !X86::isZeroNode(Op.getOperand(1))) {
6339 unsigned NumBits = VT.getSizeInBits();
6340 return getVShift(true, VT,
6341 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
6342 VT, Op.getOperand(1)),
6343 NumBits/2, DAG, *this, dl);
6346 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
6349 // Otherwise, if this is a vector with i32 or f32 elements, and the element
6350 // is a non-constant being inserted into an element other than the low one,
6351 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
6352 // movd/movss) to move this into the low element, then shuffle it into
6354 if (EVTBits == 32) {
6355 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6356 return getShuffleVectorZeroOrUndef(Item, Idx, NumZero > 0, Subtarget, DAG);
6360 // Splat is obviously ok. Let legalizer expand it to a shuffle.
6361 if (Values.size() == 1) {
6362 if (EVTBits == 32) {
6363 // Instead of a shuffle like this:
6364 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
6365 // Check if it's possible to issue this instead.
6366 // shuffle (vload ptr)), undef, <1, 1, 1, 1>
6367 unsigned Idx = countTrailingZeros(NonZeros);
6368 SDValue Item = Op.getOperand(Idx);
6369 if (Op.getNode()->isOnlyUserOf(Item.getNode()))
6370 return LowerAsSplatVectorLoad(Item, VT, dl, DAG);
6375 // A vector full of immediates; various special cases are already
6376 // handled, so this is best done with a single constant-pool load.
6380 // For AVX-length vectors, see if we can use a vector load to get all of the
6381 // elements, otherwise build the individual 128-bit pieces and use
6382 // shuffles to put them in place.
6383 if (VT.is256BitVector() || VT.is512BitVector()) {
6384 SmallVector<SDValue, 64> V(Op->op_begin(), Op->op_begin() + NumElems);
6386 // Check for a build vector of consecutive loads.
6387 if (SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG, false))
6390 EVT HVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems/2);
6392 // Build both the lower and upper subvector.
6393 SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
6394 makeArrayRef(&V[0], NumElems/2));
6395 SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
6396 makeArrayRef(&V[NumElems / 2], NumElems/2));
6398 // Recreate the wider vector with the lower and upper part.
6399 if (VT.is256BitVector())
6400 return Concat128BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
6401 return Concat256BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
6404 // Let legalizer expand 2-wide build_vectors.
6405 if (EVTBits == 64) {
6406 if (NumNonZero == 1) {
6407 // One half is zero or undef.
6408 unsigned Idx = countTrailingZeros(NonZeros);
6409 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
6410 Op.getOperand(Idx));
6411 return getShuffleVectorZeroOrUndef(V2, Idx, true, Subtarget, DAG);
6416 // If element VT is < 32 bits, convert it to inserts into a zero vector.
6417 if (EVTBits == 8 && NumElems == 16)
6418 if (SDValue V = LowerBuildVectorv16i8(Op, NonZeros, NumNonZero, NumZero,
6419 DAG, Subtarget, *this))
6422 if (EVTBits == 16 && NumElems == 8)
6423 if (SDValue V = LowerBuildVectorv8i16(Op, NonZeros, NumNonZero, NumZero,
6424 DAG, Subtarget, *this))
6427 // If element VT is == 32 bits and has 4 elems, try to generate an INSERTPS
6428 if (EVTBits == 32 && NumElems == 4)
6429 if (SDValue V = LowerBuildVectorv4x32(Op, DAG, Subtarget, *this))
6432 // If element VT is == 32 bits, turn it into a number of shuffles.
6433 SmallVector<SDValue, 8> V(NumElems);
6434 if (NumElems == 4 && NumZero > 0) {
6435 for (unsigned i = 0; i < 4; ++i) {
6436 bool isZero = !(NonZeros & (1ULL << i));
6438 V[i] = getZeroVector(VT, Subtarget, DAG, dl);
6440 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
6443 for (unsigned i = 0; i < 2; ++i) {
6444 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
6447 V[i] = V[i*2]; // Must be a zero vector.
6450 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
6453 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
6456 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
6461 bool Reverse1 = (NonZeros & 0x3) == 2;
6462 bool Reverse2 = ((NonZeros & (0x3 << 2)) >> 2) == 2;
6466 static_cast<int>(Reverse2 ? NumElems+1 : NumElems),
6467 static_cast<int>(Reverse2 ? NumElems : NumElems+1)
6469 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
6472 if (Values.size() > 1 && VT.is128BitVector()) {
6473 // Check for a build vector of consecutive loads.
6474 for (unsigned i = 0; i < NumElems; ++i)
6475 V[i] = Op.getOperand(i);
6477 // Check for elements which are consecutive loads.
6478 if (SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG, false))
6481 // Check for a build vector from mostly shuffle plus few inserting.
6482 if (SDValue Sh = buildFromShuffleMostly(Op, DAG))
6485 // For SSE 4.1, use insertps to put the high elements into the low element.
6486 if (Subtarget->hasSSE41()) {
6488 if (Op.getOperand(0).getOpcode() != ISD::UNDEF)
6489 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0));
6491 Result = DAG.getUNDEF(VT);
6493 for (unsigned i = 1; i < NumElems; ++i) {
6494 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue;
6495 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result,
6496 Op.getOperand(i), DAG.getIntPtrConstant(i, dl));
6501 // Otherwise, expand into a number of unpckl*, start by extending each of
6502 // our (non-undef) elements to the full vector width with the element in the
6503 // bottom slot of the vector (which generates no code for SSE).
6504 for (unsigned i = 0; i < NumElems; ++i) {
6505 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
6506 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
6508 V[i] = DAG.getUNDEF(VT);
6511 // Next, we iteratively mix elements, e.g. for v4f32:
6512 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
6513 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
6514 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
6515 unsigned EltStride = NumElems >> 1;
6516 while (EltStride != 0) {
6517 for (unsigned i = 0; i < EltStride; ++i) {
6518 // If V[i+EltStride] is undef and this is the first round of mixing,
6519 // then it is safe to just drop this shuffle: V[i] is already in the
6520 // right place, the one element (since it's the first round) being
6521 // inserted as undef can be dropped. This isn't safe for successive
6522 // rounds because they will permute elements within both vectors.
6523 if (V[i+EltStride].getOpcode() == ISD::UNDEF &&
6524 EltStride == NumElems/2)
6527 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]);
6536 // 256-bit AVX can use the vinsertf128 instruction
6537 // to create 256-bit vectors from two other 128-bit ones.
6538 static SDValue LowerAVXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
6540 MVT ResVT = Op.getSimpleValueType();
6542 assert((ResVT.is256BitVector() ||
6543 ResVT.is512BitVector()) && "Value type must be 256-/512-bit wide");
6545 SDValue V1 = Op.getOperand(0);
6546 SDValue V2 = Op.getOperand(1);
6547 unsigned NumElems = ResVT.getVectorNumElements();
6548 if (ResVT.is256BitVector())
6549 return Concat128BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
6551 if (Op.getNumOperands() == 4) {
6552 MVT HalfVT = MVT::getVectorVT(ResVT.getVectorElementType(),
6553 ResVT.getVectorNumElements()/2);
6554 SDValue V3 = Op.getOperand(2);
6555 SDValue V4 = Op.getOperand(3);
6556 return Concat256BitVectors(Concat128BitVectors(V1, V2, HalfVT, NumElems/2, DAG, dl),
6557 Concat128BitVectors(V3, V4, HalfVT, NumElems/2, DAG, dl), ResVT, NumElems, DAG, dl);
6559 return Concat256BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
6562 static SDValue LowerCONCAT_VECTORSvXi1(SDValue Op,
6563 const X86Subtarget *Subtarget,
6564 SelectionDAG & DAG) {
6566 MVT ResVT = Op.getSimpleValueType();
6567 unsigned NumOfOperands = Op.getNumOperands();
6569 assert(isPowerOf2_32(NumOfOperands) &&
6570 "Unexpected number of operands in CONCAT_VECTORS");
6572 SDValue Undef = DAG.getUNDEF(ResVT);
6573 if (NumOfOperands > 2) {
6574 // Specialize the cases when all, or all but one, of the operands are undef.
6575 unsigned NumOfDefinedOps = 0;
6577 for (unsigned i = 0; i < NumOfOperands; i++)
6578 if (!Op.getOperand(i).isUndef()) {
6582 if (NumOfDefinedOps == 0)
6584 if (NumOfDefinedOps == 1) {
6585 unsigned SubVecNumElts =
6586 Op.getOperand(OpIdx).getValueType().getVectorNumElements();
6587 SDValue IdxVal = DAG.getIntPtrConstant(SubVecNumElts * OpIdx, dl);
6588 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, Undef,
6589 Op.getOperand(OpIdx), IdxVal);
6592 MVT HalfVT = MVT::getVectorVT(ResVT.getVectorElementType(),
6593 ResVT.getVectorNumElements()/2);
6594 SmallVector<SDValue, 2> Ops;
6595 for (unsigned i = 0; i < NumOfOperands/2; i++)
6596 Ops.push_back(Op.getOperand(i));
6597 SDValue Lo = DAG.getNode(ISD::CONCAT_VECTORS, dl, HalfVT, Ops);
6599 for (unsigned i = NumOfOperands/2; i < NumOfOperands; i++)
6600 Ops.push_back(Op.getOperand(i));
6601 SDValue Hi = DAG.getNode(ISD::CONCAT_VECTORS, dl, HalfVT, Ops);
6602 return DAG.getNode(ISD::CONCAT_VECTORS, dl, ResVT, Lo, Hi);
6606 SDValue V1 = Op.getOperand(0);
6607 SDValue V2 = Op.getOperand(1);
6608 unsigned NumElems = ResVT.getVectorNumElements();
6609 assert(V1.getValueType() == V2.getValueType() &&
6610 V1.getValueType().getVectorNumElements() == NumElems/2 &&
6611 "Unexpected operands in CONCAT_VECTORS");
6613 if (ResVT.getSizeInBits() >= 16)
6614 return Op; // The operation is legal with KUNPCK
6616 bool IsZeroV1 = ISD::isBuildVectorAllZeros(V1.getNode());
6617 bool IsZeroV2 = ISD::isBuildVectorAllZeros(V2.getNode());
6618 SDValue ZeroVec = getZeroVector(ResVT, Subtarget, DAG, dl);
6619 if (IsZeroV1 && IsZeroV2)
6622 SDValue ZeroIdx = DAG.getIntPtrConstant(0, dl);
6624 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, Undef, V1, ZeroIdx);
6626 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, ZeroVec, V1, ZeroIdx);
6628 SDValue IdxVal = DAG.getIntPtrConstant(NumElems/2, dl);
6630 V2 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, Undef, V2, IdxVal);
6633 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, ZeroVec, V2, IdxVal);
6635 V1 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, Undef, V1, ZeroIdx);
6636 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, V1, V2, IdxVal);
6639 static SDValue LowerCONCAT_VECTORS(SDValue Op,
6640 const X86Subtarget *Subtarget,
6641 SelectionDAG &DAG) {
6642 MVT VT = Op.getSimpleValueType();
6643 if (VT.getVectorElementType() == MVT::i1)
6644 return LowerCONCAT_VECTORSvXi1(Op, Subtarget, DAG);
6646 assert((VT.is256BitVector() && Op.getNumOperands() == 2) ||
6647 (VT.is512BitVector() && (Op.getNumOperands() == 2 ||
6648 Op.getNumOperands() == 4)));
6650 // AVX can use the vinsertf128 instruction to create 256-bit vectors
6651 // from two other 128-bit ones.
6653 // 512-bit vector may contain 2 256-bit vectors or 4 128-bit vectors
6654 return LowerAVXCONCAT_VECTORS(Op, DAG);
6657 //===----------------------------------------------------------------------===//
6658 // Vector shuffle lowering
6660 // This is an experimental code path for lowering vector shuffles on x86. It is
6661 // designed to handle arbitrary vector shuffles and blends, gracefully
6662 // degrading performance as necessary. It works hard to recognize idiomatic
6663 // shuffles and lower them to optimal instruction patterns without leaving
6664 // a framework that allows reasonably efficient handling of all vector shuffle
6666 //===----------------------------------------------------------------------===//
6668 /// \brief Tiny helper function to identify a no-op mask.
6670 /// This is a somewhat boring predicate function. It checks whether the mask
6671 /// array input, which is assumed to be a single-input shuffle mask of the kind
6672 /// used by the X86 shuffle instructions (not a fully general
6673 /// ShuffleVectorSDNode mask) requires any shuffles to occur. Both undef and an
6674 /// in-place shuffle are 'no-op's.
6675 static bool isNoopShuffleMask(ArrayRef<int> Mask) {
6676 for (int i = 0, Size = Mask.size(); i < Size; ++i)
6677 if (Mask[i] != -1 && Mask[i] != i)
6682 /// \brief Helper function to classify a mask as a single-input mask.
6684 /// This isn't a generic single-input test because in the vector shuffle
6685 /// lowering we canonicalize single inputs to be the first input operand. This
6686 /// means we can more quickly test for a single input by only checking whether
6687 /// an input from the second operand exists. We also assume that the size of
6688 /// mask corresponds to the size of the input vectors which isn't true in the
6689 /// fully general case.
6690 static bool isSingleInputShuffleMask(ArrayRef<int> Mask) {
6692 if (M >= (int)Mask.size())
6697 /// \brief Test whether there are elements crossing 128-bit lanes in this
6700 /// X86 divides up its shuffles into in-lane and cross-lane shuffle operations
6701 /// and we routinely test for these.
6702 static bool is128BitLaneCrossingShuffleMask(MVT VT, ArrayRef<int> Mask) {
6703 int LaneSize = 128 / VT.getScalarSizeInBits();
6704 int Size = Mask.size();
6705 for (int i = 0; i < Size; ++i)
6706 if (Mask[i] >= 0 && (Mask[i] % Size) / LaneSize != i / LaneSize)
6711 /// \brief Test whether a shuffle mask is equivalent within each 128-bit lane.
6713 /// This checks a shuffle mask to see if it is performing the same
6714 /// 128-bit lane-relative shuffle in each 128-bit lane. This trivially implies
6715 /// that it is also not lane-crossing. It may however involve a blend from the
6716 /// same lane of a second vector.
6718 /// The specific repeated shuffle mask is populated in \p RepeatedMask, as it is
6719 /// non-trivial to compute in the face of undef lanes. The representation is
6720 /// *not* suitable for use with existing 128-bit shuffles as it will contain
6721 /// entries from both V1 and V2 inputs to the wider mask.
6723 is128BitLaneRepeatedShuffleMask(MVT VT, ArrayRef<int> Mask,
6724 SmallVectorImpl<int> &RepeatedMask) {
6725 int LaneSize = 128 / VT.getScalarSizeInBits();
6726 RepeatedMask.resize(LaneSize, -1);
6727 int Size = Mask.size();
6728 for (int i = 0; i < Size; ++i) {
6731 if ((Mask[i] % Size) / LaneSize != i / LaneSize)
6732 // This entry crosses lanes, so there is no way to model this shuffle.
6735 // Ok, handle the in-lane shuffles by detecting if and when they repeat.
6736 if (RepeatedMask[i % LaneSize] == -1)
6737 // This is the first non-undef entry in this slot of a 128-bit lane.
6738 RepeatedMask[i % LaneSize] =
6739 Mask[i] < Size ? Mask[i] % LaneSize : Mask[i] % LaneSize + Size;
6740 else if (RepeatedMask[i % LaneSize] + (i / LaneSize) * LaneSize != Mask[i])
6741 // Found a mismatch with the repeated mask.
6747 /// \brief Checks whether a shuffle mask is equivalent to an explicit list of
6750 /// This is a fast way to test a shuffle mask against a fixed pattern:
6752 /// if (isShuffleEquivalent(Mask, 3, 2, {1, 0})) { ... }
6754 /// It returns true if the mask is exactly as wide as the argument list, and
6755 /// each element of the mask is either -1 (signifying undef) or the value given
6756 /// in the argument.
6757 static bool isShuffleEquivalent(SDValue V1, SDValue V2, ArrayRef<int> Mask,
6758 ArrayRef<int> ExpectedMask) {
6759 if (Mask.size() != ExpectedMask.size())
6762 int Size = Mask.size();
6764 // If the values are build vectors, we can look through them to find
6765 // equivalent inputs that make the shuffles equivalent.
6766 auto *BV1 = dyn_cast<BuildVectorSDNode>(V1);
6767 auto *BV2 = dyn_cast<BuildVectorSDNode>(V2);
6769 for (int i = 0; i < Size; ++i)
6770 if (Mask[i] != -1 && Mask[i] != ExpectedMask[i]) {
6771 auto *MaskBV = Mask[i] < Size ? BV1 : BV2;
6772 auto *ExpectedBV = ExpectedMask[i] < Size ? BV1 : BV2;
6773 if (!MaskBV || !ExpectedBV ||
6774 MaskBV->getOperand(Mask[i] % Size) !=
6775 ExpectedBV->getOperand(ExpectedMask[i] % Size))
6782 /// \brief Get a 4-lane 8-bit shuffle immediate for a mask.
6784 /// This helper function produces an 8-bit shuffle immediate corresponding to
6785 /// the ubiquitous shuffle encoding scheme used in x86 instructions for
6786 /// shuffling 4 lanes. It can be used with most of the PSHUF instructions for
6789 /// NB: We rely heavily on "undef" masks preserving the input lane.
6790 static SDValue getV4X86ShuffleImm8ForMask(ArrayRef<int> Mask, SDLoc DL,
6791 SelectionDAG &DAG) {
6792 assert(Mask.size() == 4 && "Only 4-lane shuffle masks");
6793 assert(Mask[0] >= -1 && Mask[0] < 4 && "Out of bound mask element!");
6794 assert(Mask[1] >= -1 && Mask[1] < 4 && "Out of bound mask element!");
6795 assert(Mask[2] >= -1 && Mask[2] < 4 && "Out of bound mask element!");
6796 assert(Mask[3] >= -1 && Mask[3] < 4 && "Out of bound mask element!");
6799 Imm |= (Mask[0] == -1 ? 0 : Mask[0]) << 0;
6800 Imm |= (Mask[1] == -1 ? 1 : Mask[1]) << 2;
6801 Imm |= (Mask[2] == -1 ? 2 : Mask[2]) << 4;
6802 Imm |= (Mask[3] == -1 ? 3 : Mask[3]) << 6;
6803 return DAG.getConstant(Imm, DL, MVT::i8);
6806 /// \brief Compute whether each element of a shuffle is zeroable.
6808 /// A "zeroable" vector shuffle element is one which can be lowered to zero.
6809 /// Either it is an undef element in the shuffle mask, the element of the input
6810 /// referenced is undef, or the element of the input referenced is known to be
6811 /// zero. Many x86 shuffles can zero lanes cheaply and we often want to handle
6812 /// as many lanes with this technique as possible to simplify the remaining
6814 static SmallBitVector computeZeroableShuffleElements(ArrayRef<int> Mask,
6815 SDValue V1, SDValue V2) {
6816 SmallBitVector Zeroable(Mask.size(), false);
6818 while (V1.getOpcode() == ISD::BITCAST)
6819 V1 = V1->getOperand(0);
6820 while (V2.getOpcode() == ISD::BITCAST)
6821 V2 = V2->getOperand(0);
6823 bool V1IsZero = ISD::isBuildVectorAllZeros(V1.getNode());
6824 bool V2IsZero = ISD::isBuildVectorAllZeros(V2.getNode());
6826 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6828 // Handle the easy cases.
6829 if (M < 0 || (M >= 0 && M < Size && V1IsZero) || (M >= Size && V2IsZero)) {
6834 // If this is an index into a build_vector node (which has the same number
6835 // of elements), dig out the input value and use it.
6836 SDValue V = M < Size ? V1 : V2;
6837 if (V.getOpcode() != ISD::BUILD_VECTOR || Size != (int)V.getNumOperands())
6840 SDValue Input = V.getOperand(M % Size);
6841 // The UNDEF opcode check really should be dead code here, but not quite
6842 // worth asserting on (it isn't invalid, just unexpected).
6843 if (Input.getOpcode() == ISD::UNDEF || X86::isZeroNode(Input))
6850 // X86 has dedicated unpack instructions that can handle specific blend
6851 // operations: UNPCKH and UNPCKL.
6852 static SDValue lowerVectorShuffleWithUNPCK(SDLoc DL, MVT VT, ArrayRef<int> Mask,
6853 SDValue V1, SDValue V2,
6854 SelectionDAG &DAG) {
6855 int NumElts = VT.getVectorNumElements();
6856 int NumEltsInLane = 128 / VT.getScalarSizeInBits();
6857 SmallVector<int, 8> Unpckl;
6858 SmallVector<int, 8> Unpckh;
6860 for (int i = 0; i < NumElts; ++i) {
6861 unsigned LaneStart = (i / NumEltsInLane) * NumEltsInLane;
6862 int LoPos = (i % NumEltsInLane) / 2 + LaneStart + NumElts * (i % 2);
6863 int HiPos = LoPos + NumEltsInLane / 2;
6864 Unpckl.push_back(LoPos);
6865 Unpckh.push_back(HiPos);
6868 if (isShuffleEquivalent(V1, V2, Mask, Unpckl))
6869 return DAG.getNode(X86ISD::UNPCKL, DL, VT, V1, V2);
6870 if (isShuffleEquivalent(V1, V2, Mask, Unpckh))
6871 return DAG.getNode(X86ISD::UNPCKH, DL, VT, V1, V2);
6873 // Commute and try again.
6874 ShuffleVectorSDNode::commuteMask(Unpckl);
6875 if (isShuffleEquivalent(V1, V2, Mask, Unpckl))
6876 return DAG.getNode(X86ISD::UNPCKL, DL, VT, V2, V1);
6878 ShuffleVectorSDNode::commuteMask(Unpckh);
6879 if (isShuffleEquivalent(V1, V2, Mask, Unpckh))
6880 return DAG.getNode(X86ISD::UNPCKH, DL, VT, V2, V1);
6885 /// \brief Try to emit a bitmask instruction for a shuffle.
6887 /// This handles cases where we can model a blend exactly as a bitmask due to
6888 /// one of the inputs being zeroable.
6889 static SDValue lowerVectorShuffleAsBitMask(SDLoc DL, MVT VT, SDValue V1,
6890 SDValue V2, ArrayRef<int> Mask,
6891 SelectionDAG &DAG) {
6892 MVT EltVT = VT.getVectorElementType();
6893 int NumEltBits = EltVT.getSizeInBits();
6894 MVT IntEltVT = MVT::getIntegerVT(NumEltBits);
6895 SDValue Zero = DAG.getConstant(0, DL, IntEltVT);
6896 SDValue AllOnes = DAG.getConstant(APInt::getAllOnesValue(NumEltBits), DL,
6898 if (EltVT.isFloatingPoint()) {
6899 Zero = DAG.getBitcast(EltVT, Zero);
6900 AllOnes = DAG.getBitcast(EltVT, AllOnes);
6902 SmallVector<SDValue, 16> VMaskOps(Mask.size(), Zero);
6903 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
6905 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6908 if (Mask[i] % Size != i)
6909 return SDValue(); // Not a blend.
6911 V = Mask[i] < Size ? V1 : V2;
6912 else if (V != (Mask[i] < Size ? V1 : V2))
6913 return SDValue(); // Can only let one input through the mask.
6915 VMaskOps[i] = AllOnes;
6918 return SDValue(); // No non-zeroable elements!
6920 SDValue VMask = DAG.getNode(ISD::BUILD_VECTOR, DL, VT, VMaskOps);
6921 V = DAG.getNode(VT.isFloatingPoint()
6922 ? (unsigned) X86ISD::FAND : (unsigned) ISD::AND,
6927 /// \brief Try to emit a blend instruction for a shuffle using bit math.
6929 /// This is used as a fallback approach when first class blend instructions are
6930 /// unavailable. Currently it is only suitable for integer vectors, but could
6931 /// be generalized for floating point vectors if desirable.
6932 static SDValue lowerVectorShuffleAsBitBlend(SDLoc DL, MVT VT, SDValue V1,
6933 SDValue V2, ArrayRef<int> Mask,
6934 SelectionDAG &DAG) {
6935 assert(VT.isInteger() && "Only supports integer vector types!");
6936 MVT EltVT = VT.getVectorElementType();
6937 int NumEltBits = EltVT.getSizeInBits();
6938 SDValue Zero = DAG.getConstant(0, DL, EltVT);
6939 SDValue AllOnes = DAG.getConstant(APInt::getAllOnesValue(NumEltBits), DL,
6941 SmallVector<SDValue, 16> MaskOps;
6942 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6943 if (Mask[i] != -1 && Mask[i] != i && Mask[i] != i + Size)
6944 return SDValue(); // Shuffled input!
6945 MaskOps.push_back(Mask[i] < Size ? AllOnes : Zero);
6948 SDValue V1Mask = DAG.getNode(ISD::BUILD_VECTOR, DL, VT, MaskOps);
6949 V1 = DAG.getNode(ISD::AND, DL, VT, V1, V1Mask);
6950 // We have to cast V2 around.
6951 MVT MaskVT = MVT::getVectorVT(MVT::i64, VT.getSizeInBits() / 64);
6952 V2 = DAG.getBitcast(VT, DAG.getNode(X86ISD::ANDNP, DL, MaskVT,
6953 DAG.getBitcast(MaskVT, V1Mask),
6954 DAG.getBitcast(MaskVT, V2)));
6955 return DAG.getNode(ISD::OR, DL, VT, V1, V2);
6958 /// \brief Try to emit a blend instruction for a shuffle.
6960 /// This doesn't do any checks for the availability of instructions for blending
6961 /// these values. It relies on the availability of the X86ISD::BLENDI pattern to
6962 /// be matched in the backend with the type given. What it does check for is
6963 /// that the shuffle mask is a blend, or convertible into a blend with zero.
6964 static SDValue lowerVectorShuffleAsBlend(SDLoc DL, MVT VT, SDValue V1,
6965 SDValue V2, ArrayRef<int> Original,
6966 const X86Subtarget *Subtarget,
6967 SelectionDAG &DAG) {
6968 bool V1IsZero = ISD::isBuildVectorAllZeros(V1.getNode());
6969 bool V2IsZero = ISD::isBuildVectorAllZeros(V2.getNode());
6970 SmallVector<int, 8> Mask(Original.begin(), Original.end());
6971 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
6972 bool ForceV1Zero = false, ForceV2Zero = false;
6974 // Attempt to generate the binary blend mask. If an input is zero then
6975 // we can use any lane.
6976 // TODO: generalize the zero matching to any scalar like isShuffleEquivalent.
6977 unsigned BlendMask = 0;
6978 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6984 if (M == i + Size) {
6985 BlendMask |= 1u << i;
6996 BlendMask |= 1u << i;
7001 return SDValue(); // Shuffled input!
7004 // Create a REAL zero vector - ISD::isBuildVectorAllZeros allows UNDEFs.
7006 V1 = getZeroVector(VT, Subtarget, DAG, DL);
7008 V2 = getZeroVector(VT, Subtarget, DAG, DL);
7010 auto ScaleBlendMask = [](unsigned BlendMask, int Size, int Scale) {
7011 unsigned ScaledMask = 0;
7012 for (int i = 0; i != Size; ++i)
7013 if (BlendMask & (1u << i))
7014 for (int j = 0; j != Scale; ++j)
7015 ScaledMask |= 1u << (i * Scale + j);
7019 switch (VT.SimpleTy) {
7024 return DAG.getNode(X86ISD::BLENDI, DL, VT, V1, V2,
7025 DAG.getConstant(BlendMask, DL, MVT::i8));
7029 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
7033 // If we have AVX2 it is faster to use VPBLENDD when the shuffle fits into
7034 // that instruction.
7035 if (Subtarget->hasAVX2()) {
7036 // Scale the blend by the number of 32-bit dwords per element.
7037 int Scale = VT.getScalarSizeInBits() / 32;
7038 BlendMask = ScaleBlendMask(BlendMask, Mask.size(), Scale);
7039 MVT BlendVT = VT.getSizeInBits() > 128 ? MVT::v8i32 : MVT::v4i32;
7040 V1 = DAG.getBitcast(BlendVT, V1);
7041 V2 = DAG.getBitcast(BlendVT, V2);
7042 return DAG.getBitcast(
7043 VT, DAG.getNode(X86ISD::BLENDI, DL, BlendVT, V1, V2,
7044 DAG.getConstant(BlendMask, DL, MVT::i8)));
7048 // For integer shuffles we need to expand the mask and cast the inputs to
7049 // v8i16s prior to blending.
7050 int Scale = 8 / VT.getVectorNumElements();
7051 BlendMask = ScaleBlendMask(BlendMask, Mask.size(), Scale);
7052 V1 = DAG.getBitcast(MVT::v8i16, V1);
7053 V2 = DAG.getBitcast(MVT::v8i16, V2);
7054 return DAG.getBitcast(VT,
7055 DAG.getNode(X86ISD::BLENDI, DL, MVT::v8i16, V1, V2,
7056 DAG.getConstant(BlendMask, DL, MVT::i8)));
7060 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
7061 SmallVector<int, 8> RepeatedMask;
7062 if (is128BitLaneRepeatedShuffleMask(MVT::v16i16, Mask, RepeatedMask)) {
7063 // We can lower these with PBLENDW which is mirrored across 128-bit lanes.
7064 assert(RepeatedMask.size() == 8 && "Repeated mask size doesn't match!");
7066 for (int i = 0; i < 8; ++i)
7067 if (RepeatedMask[i] >= 16)
7068 BlendMask |= 1u << i;
7069 return DAG.getNode(X86ISD::BLENDI, DL, MVT::v16i16, V1, V2,
7070 DAG.getConstant(BlendMask, DL, MVT::i8));
7076 assert((VT.is128BitVector() || Subtarget->hasAVX2()) &&
7077 "256-bit byte-blends require AVX2 support!");
7079 // Attempt to lower to a bitmask if we can. VPAND is faster than VPBLENDVB.
7080 if (SDValue Masked = lowerVectorShuffleAsBitMask(DL, VT, V1, V2, Mask, DAG))
7083 // Scale the blend by the number of bytes per element.
7084 int Scale = VT.getScalarSizeInBits() / 8;
7086 // This form of blend is always done on bytes. Compute the byte vector
7088 MVT BlendVT = MVT::getVectorVT(MVT::i8, VT.getSizeInBits() / 8);
7090 // Compute the VSELECT mask. Note that VSELECT is really confusing in the
7091 // mix of LLVM's code generator and the x86 backend. We tell the code
7092 // generator that boolean values in the elements of an x86 vector register
7093 // are -1 for true and 0 for false. We then use the LLVM semantics of 'true'
7094 // mapping a select to operand #1, and 'false' mapping to operand #2. The
7095 // reality in x86 is that vector masks (pre-AVX-512) use only the high bit
7096 // of the element (the remaining are ignored) and 0 in that high bit would
7097 // mean operand #1 while 1 in the high bit would mean operand #2. So while
7098 // the LLVM model for boolean values in vector elements gets the relevant
7099 // bit set, it is set backwards and over constrained relative to x86's
7101 SmallVector<SDValue, 32> VSELECTMask;
7102 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7103 for (int j = 0; j < Scale; ++j)
7104 VSELECTMask.push_back(
7105 Mask[i] < 0 ? DAG.getUNDEF(MVT::i8)
7106 : DAG.getConstant(Mask[i] < Size ? -1 : 0, DL,
7109 V1 = DAG.getBitcast(BlendVT, V1);
7110 V2 = DAG.getBitcast(BlendVT, V2);
7111 return DAG.getBitcast(VT, DAG.getNode(ISD::VSELECT, DL, BlendVT,
7112 DAG.getNode(ISD::BUILD_VECTOR, DL,
7113 BlendVT, VSELECTMask),
7118 llvm_unreachable("Not a supported integer vector type!");
7122 /// \brief Try to lower as a blend of elements from two inputs followed by
7123 /// a single-input permutation.
7125 /// This matches the pattern where we can blend elements from two inputs and
7126 /// then reduce the shuffle to a single-input permutation.
7127 static SDValue lowerVectorShuffleAsBlendAndPermute(SDLoc DL, MVT VT, SDValue V1,
7130 SelectionDAG &DAG) {
7131 // We build up the blend mask while checking whether a blend is a viable way
7132 // to reduce the shuffle.
7133 SmallVector<int, 32> BlendMask(Mask.size(), -1);
7134 SmallVector<int, 32> PermuteMask(Mask.size(), -1);
7136 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
7140 assert(Mask[i] < Size * 2 && "Shuffle input is out of bounds.");
7142 if (BlendMask[Mask[i] % Size] == -1)
7143 BlendMask[Mask[i] % Size] = Mask[i];
7144 else if (BlendMask[Mask[i] % Size] != Mask[i])
7145 return SDValue(); // Can't blend in the needed input!
7147 PermuteMask[i] = Mask[i] % Size;
7150 SDValue V = DAG.getVectorShuffle(VT, DL, V1, V2, BlendMask);
7151 return DAG.getVectorShuffle(VT, DL, V, DAG.getUNDEF(VT), PermuteMask);
7154 /// \brief Generic routine to decompose a shuffle and blend into indepndent
7155 /// blends and permutes.
7157 /// This matches the extremely common pattern for handling combined
7158 /// shuffle+blend operations on newer X86 ISAs where we have very fast blend
7159 /// operations. It will try to pick the best arrangement of shuffles and
7161 static SDValue lowerVectorShuffleAsDecomposedShuffleBlend(SDLoc DL, MVT VT,
7165 SelectionDAG &DAG) {
7166 // Shuffle the input elements into the desired positions in V1 and V2 and
7167 // blend them together.
7168 SmallVector<int, 32> V1Mask(Mask.size(), -1);
7169 SmallVector<int, 32> V2Mask(Mask.size(), -1);
7170 SmallVector<int, 32> BlendMask(Mask.size(), -1);
7171 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7172 if (Mask[i] >= 0 && Mask[i] < Size) {
7173 V1Mask[i] = Mask[i];
7175 } else if (Mask[i] >= Size) {
7176 V2Mask[i] = Mask[i] - Size;
7177 BlendMask[i] = i + Size;
7180 // Try to lower with the simpler initial blend strategy unless one of the
7181 // input shuffles would be a no-op. We prefer to shuffle inputs as the
7182 // shuffle may be able to fold with a load or other benefit. However, when
7183 // we'll have to do 2x as many shuffles in order to achieve this, blending
7184 // first is a better strategy.
7185 if (!isNoopShuffleMask(V1Mask) && !isNoopShuffleMask(V2Mask))
7186 if (SDValue BlendPerm =
7187 lowerVectorShuffleAsBlendAndPermute(DL, VT, V1, V2, Mask, DAG))
7190 V1 = DAG.getVectorShuffle(VT, DL, V1, DAG.getUNDEF(VT), V1Mask);
7191 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Mask);
7192 return DAG.getVectorShuffle(VT, DL, V1, V2, BlendMask);
7195 /// \brief Try to lower a vector shuffle as a byte rotation.
7197 /// SSSE3 has a generic PALIGNR instruction in x86 that will do an arbitrary
7198 /// byte-rotation of the concatenation of two vectors; pre-SSSE3 can use
7199 /// a PSRLDQ/PSLLDQ/POR pattern to get a similar effect. This routine will
7200 /// try to generically lower a vector shuffle through such an pattern. It
7201 /// does not check for the profitability of lowering either as PALIGNR or
7202 /// PSRLDQ/PSLLDQ/POR, only whether the mask is valid to lower in that form.
7203 /// This matches shuffle vectors that look like:
7205 /// v8i16 [11, 12, 13, 14, 15, 0, 1, 2]
7207 /// Essentially it concatenates V1 and V2, shifts right by some number of
7208 /// elements, and takes the low elements as the result. Note that while this is
7209 /// specified as a *right shift* because x86 is little-endian, it is a *left
7210 /// rotate* of the vector lanes.
7211 static SDValue lowerVectorShuffleAsByteRotate(SDLoc DL, MVT VT, SDValue V1,
7214 const X86Subtarget *Subtarget,
7215 SelectionDAG &DAG) {
7216 assert(!isNoopShuffleMask(Mask) && "We shouldn't lower no-op shuffles!");
7218 int NumElts = Mask.size();
7219 int NumLanes = VT.getSizeInBits() / 128;
7220 int NumLaneElts = NumElts / NumLanes;
7222 // We need to detect various ways of spelling a rotation:
7223 // [11, 12, 13, 14, 15, 0, 1, 2]
7224 // [-1, 12, 13, 14, -1, -1, 1, -1]
7225 // [-1, -1, -1, -1, -1, -1, 1, 2]
7226 // [ 3, 4, 5, 6, 7, 8, 9, 10]
7227 // [-1, 4, 5, 6, -1, -1, 9, -1]
7228 // [-1, 4, 5, 6, -1, -1, -1, -1]
7231 for (int l = 0; l < NumElts; l += NumLaneElts) {
7232 for (int i = 0; i < NumLaneElts; ++i) {
7233 if (Mask[l + i] == -1)
7235 assert(Mask[l + i] >= 0 && "Only -1 is a valid negative mask element!");
7237 // Get the mod-Size index and lane correct it.
7238 int LaneIdx = (Mask[l + i] % NumElts) - l;
7239 // Make sure it was in this lane.
7240 if (LaneIdx < 0 || LaneIdx >= NumLaneElts)
7243 // Determine where a rotated vector would have started.
7244 int StartIdx = i - LaneIdx;
7246 // The identity rotation isn't interesting, stop.
7249 // If we found the tail of a vector the rotation must be the missing
7250 // front. If we found the head of a vector, it must be how much of the
7252 int CandidateRotation = StartIdx < 0 ? -StartIdx : NumLaneElts - StartIdx;
7255 Rotation = CandidateRotation;
7256 else if (Rotation != CandidateRotation)
7257 // The rotations don't match, so we can't match this mask.
7260 // Compute which value this mask is pointing at.
7261 SDValue MaskV = Mask[l + i] < NumElts ? V1 : V2;
7263 // Compute which of the two target values this index should be assigned
7264 // to. This reflects whether the high elements are remaining or the low
7265 // elements are remaining.
7266 SDValue &TargetV = StartIdx < 0 ? Hi : Lo;
7268 // Either set up this value if we've not encountered it before, or check
7269 // that it remains consistent.
7272 else if (TargetV != MaskV)
7273 // This may be a rotation, but it pulls from the inputs in some
7274 // unsupported interleaving.
7279 // Check that we successfully analyzed the mask, and normalize the results.
7280 assert(Rotation != 0 && "Failed to locate a viable rotation!");
7281 assert((Lo || Hi) && "Failed to find a rotated input vector!");
7287 // The actual rotate instruction rotates bytes, so we need to scale the
7288 // rotation based on how many bytes are in the vector lane.
7289 int Scale = 16 / NumLaneElts;
7291 // SSSE3 targets can use the palignr instruction.
7292 if (Subtarget->hasSSSE3()) {
7293 // Cast the inputs to i8 vector of correct length to match PALIGNR.
7294 MVT AlignVT = MVT::getVectorVT(MVT::i8, 16 * NumLanes);
7295 Lo = DAG.getBitcast(AlignVT, Lo);
7296 Hi = DAG.getBitcast(AlignVT, Hi);
7298 return DAG.getBitcast(
7299 VT, DAG.getNode(X86ISD::PALIGNR, DL, AlignVT, Lo, Hi,
7300 DAG.getConstant(Rotation * Scale, DL, MVT::i8)));
7303 assert(VT.is128BitVector() &&
7304 "Rotate-based lowering only supports 128-bit lowering!");
7305 assert(Mask.size() <= 16 &&
7306 "Can shuffle at most 16 bytes in a 128-bit vector!");
7308 // Default SSE2 implementation
7309 int LoByteShift = 16 - Rotation * Scale;
7310 int HiByteShift = Rotation * Scale;
7312 // Cast the inputs to v2i64 to match PSLLDQ/PSRLDQ.
7313 Lo = DAG.getBitcast(MVT::v2i64, Lo);
7314 Hi = DAG.getBitcast(MVT::v2i64, Hi);
7316 SDValue LoShift = DAG.getNode(X86ISD::VSHLDQ, DL, MVT::v2i64, Lo,
7317 DAG.getConstant(LoByteShift, DL, MVT::i8));
7318 SDValue HiShift = DAG.getNode(X86ISD::VSRLDQ, DL, MVT::v2i64, Hi,
7319 DAG.getConstant(HiByteShift, DL, MVT::i8));
7320 return DAG.getBitcast(VT,
7321 DAG.getNode(ISD::OR, DL, MVT::v2i64, LoShift, HiShift));
7324 /// \brief Try to lower a vector shuffle as a bit shift (shifts in zeros).
7326 /// Attempts to match a shuffle mask against the PSLL(W/D/Q/DQ) and
7327 /// PSRL(W/D/Q/DQ) SSE2 and AVX2 logical bit-shift instructions. The function
7328 /// matches elements from one of the input vectors shuffled to the left or
7329 /// right with zeroable elements 'shifted in'. It handles both the strictly
7330 /// bit-wise element shifts and the byte shift across an entire 128-bit double
7333 /// PSHL : (little-endian) left bit shift.
7334 /// [ zz, 0, zz, 2 ]
7335 /// [ -1, 4, zz, -1 ]
7336 /// PSRL : (little-endian) right bit shift.
7338 /// [ -1, -1, 7, zz]
7339 /// PSLLDQ : (little-endian) left byte shift
7340 /// [ zz, 0, 1, 2, 3, 4, 5, 6]
7341 /// [ zz, zz, -1, -1, 2, 3, 4, -1]
7342 /// [ zz, zz, zz, zz, zz, zz, -1, 1]
7343 /// PSRLDQ : (little-endian) right byte shift
7344 /// [ 5, 6, 7, zz, zz, zz, zz, zz]
7345 /// [ -1, 5, 6, 7, zz, zz, zz, zz]
7346 /// [ 1, 2, -1, -1, -1, -1, zz, zz]
7347 static SDValue lowerVectorShuffleAsShift(SDLoc DL, MVT VT, SDValue V1,
7348 SDValue V2, ArrayRef<int> Mask,
7349 SelectionDAG &DAG) {
7350 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7352 int Size = Mask.size();
7353 assert(Size == (int)VT.getVectorNumElements() && "Unexpected mask size");
7355 auto CheckZeros = [&](int Shift, int Scale, bool Left) {
7356 for (int i = 0; i < Size; i += Scale)
7357 for (int j = 0; j < Shift; ++j)
7358 if (!Zeroable[i + j + (Left ? 0 : (Scale - Shift))])
7364 auto MatchShift = [&](int Shift, int Scale, bool Left, SDValue V) {
7365 for (int i = 0; i != Size; i += Scale) {
7366 unsigned Pos = Left ? i + Shift : i;
7367 unsigned Low = Left ? i : i + Shift;
7368 unsigned Len = Scale - Shift;
7369 if (!isSequentialOrUndefInRange(Mask, Pos, Len,
7370 Low + (V == V1 ? 0 : Size)))
7374 int ShiftEltBits = VT.getScalarSizeInBits() * Scale;
7375 bool ByteShift = ShiftEltBits > 64;
7376 unsigned OpCode = Left ? (ByteShift ? X86ISD::VSHLDQ : X86ISD::VSHLI)
7377 : (ByteShift ? X86ISD::VSRLDQ : X86ISD::VSRLI);
7378 int ShiftAmt = Shift * VT.getScalarSizeInBits() / (ByteShift ? 8 : 1);
7380 // Normalize the scale for byte shifts to still produce an i64 element
7382 Scale = ByteShift ? Scale / 2 : Scale;
7384 // We need to round trip through the appropriate type for the shift.
7385 MVT ShiftSVT = MVT::getIntegerVT(VT.getScalarSizeInBits() * Scale);
7386 MVT ShiftVT = MVT::getVectorVT(ShiftSVT, Size / Scale);
7387 assert(DAG.getTargetLoweringInfo().isTypeLegal(ShiftVT) &&
7388 "Illegal integer vector type");
7389 V = DAG.getBitcast(ShiftVT, V);
7391 V = DAG.getNode(OpCode, DL, ShiftVT, V,
7392 DAG.getConstant(ShiftAmt, DL, MVT::i8));
7393 return DAG.getBitcast(VT, V);
7396 // SSE/AVX supports logical shifts up to 64-bit integers - so we can just
7397 // keep doubling the size of the integer elements up to that. We can
7398 // then shift the elements of the integer vector by whole multiples of
7399 // their width within the elements of the larger integer vector. Test each
7400 // multiple to see if we can find a match with the moved element indices
7401 // and that the shifted in elements are all zeroable.
7402 for (int Scale = 2; Scale * VT.getScalarSizeInBits() <= 128; Scale *= 2)
7403 for (int Shift = 1; Shift != Scale; ++Shift)
7404 for (bool Left : {true, false})
7405 if (CheckZeros(Shift, Scale, Left))
7406 for (SDValue V : {V1, V2})
7407 if (SDValue Match = MatchShift(Shift, Scale, Left, V))
7414 /// \brief Try to lower a vector shuffle using SSE4a EXTRQ/INSERTQ.
7415 static SDValue lowerVectorShuffleWithSSE4A(SDLoc DL, MVT VT, SDValue V1,
7416 SDValue V2, ArrayRef<int> Mask,
7417 SelectionDAG &DAG) {
7418 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7419 assert(!Zeroable.all() && "Fully zeroable shuffle mask");
7421 int Size = Mask.size();
7422 int HalfSize = Size / 2;
7423 assert(Size == (int)VT.getVectorNumElements() && "Unexpected mask size");
7425 // Upper half must be undefined.
7426 if (!isUndefInRange(Mask, HalfSize, HalfSize))
7429 // EXTRQ: Extract Len elements from lower half of source, starting at Idx.
7430 // Remainder of lower half result is zero and upper half is all undef.
7431 auto LowerAsEXTRQ = [&]() {
7432 // Determine the extraction length from the part of the
7433 // lower half that isn't zeroable.
7435 for (; Len > 0; --Len)
7436 if (!Zeroable[Len - 1])
7438 assert(Len > 0 && "Zeroable shuffle mask");
7440 // Attempt to match first Len sequential elements from the lower half.
7443 for (int i = 0; i != Len; ++i) {
7447 SDValue &V = (M < Size ? V1 : V2);
7450 // The extracted elements must start at a valid index and all mask
7451 // elements must be in the lower half.
7452 if (i > M || M >= HalfSize)
7455 if (Idx < 0 || (Src == V && Idx == (M - i))) {
7466 assert((Idx + Len) <= HalfSize && "Illegal extraction mask");
7467 int BitLen = (Len * VT.getScalarSizeInBits()) & 0x3f;
7468 int BitIdx = (Idx * VT.getScalarSizeInBits()) & 0x3f;
7469 return DAG.getNode(X86ISD::EXTRQI, DL, VT, Src,
7470 DAG.getConstant(BitLen, DL, MVT::i8),
7471 DAG.getConstant(BitIdx, DL, MVT::i8));
7474 if (SDValue ExtrQ = LowerAsEXTRQ())
7477 // INSERTQ: Extract lowest Len elements from lower half of second source and
7478 // insert over first source, starting at Idx.
7479 // { A[0], .., A[Idx-1], B[0], .., B[Len-1], A[Idx+Len], .., UNDEF, ... }
7480 auto LowerAsInsertQ = [&]() {
7481 for (int Idx = 0; Idx != HalfSize; ++Idx) {
7484 // Attempt to match first source from mask before insertion point.
7485 if (isUndefInRange(Mask, 0, Idx)) {
7487 } else if (isSequentialOrUndefInRange(Mask, 0, Idx, 0)) {
7489 } else if (isSequentialOrUndefInRange(Mask, 0, Idx, Size)) {
7495 // Extend the extraction length looking to match both the insertion of
7496 // the second source and the remaining elements of the first.
7497 for (int Hi = Idx + 1; Hi <= HalfSize; ++Hi) {
7502 if (isSequentialOrUndefInRange(Mask, Idx, Len, 0)) {
7504 } else if (isSequentialOrUndefInRange(Mask, Idx, Len, Size)) {
7510 // Match the remaining elements of the lower half.
7511 if (isUndefInRange(Mask, Hi, HalfSize - Hi)) {
7513 } else if ((!Base || (Base == V1)) &&
7514 isSequentialOrUndefInRange(Mask, Hi, HalfSize - Hi, Hi)) {
7516 } else if ((!Base || (Base == V2)) &&
7517 isSequentialOrUndefInRange(Mask, Hi, HalfSize - Hi,
7524 // We may not have a base (first source) - this can safely be undefined.
7526 Base = DAG.getUNDEF(VT);
7528 int BitLen = (Len * VT.getScalarSizeInBits()) & 0x3f;
7529 int BitIdx = (Idx * VT.getScalarSizeInBits()) & 0x3f;
7530 return DAG.getNode(X86ISD::INSERTQI, DL, VT, Base, Insert,
7531 DAG.getConstant(BitLen, DL, MVT::i8),
7532 DAG.getConstant(BitIdx, DL, MVT::i8));
7539 if (SDValue InsertQ = LowerAsInsertQ())
7545 /// \brief Lower a vector shuffle as a zero or any extension.
7547 /// Given a specific number of elements, element bit width, and extension
7548 /// stride, produce either a zero or any extension based on the available
7549 /// features of the subtarget. The extended elements are consecutive and
7550 /// begin and can start from an offseted element index in the input; to
7551 /// avoid excess shuffling the offset must either being in the bottom lane
7552 /// or at the start of a higher lane. All extended elements must be from
7554 static SDValue lowerVectorShuffleAsSpecificZeroOrAnyExtend(
7555 SDLoc DL, MVT VT, int Scale, int Offset, bool AnyExt, SDValue InputV,
7556 ArrayRef<int> Mask, const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7557 assert(Scale > 1 && "Need a scale to extend.");
7558 int EltBits = VT.getScalarSizeInBits();
7559 int NumElements = VT.getVectorNumElements();
7560 int NumEltsPerLane = 128 / EltBits;
7561 int OffsetLane = Offset / NumEltsPerLane;
7562 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
7563 "Only 8, 16, and 32 bit elements can be extended.");
7564 assert(Scale * EltBits <= 64 && "Cannot zero extend past 64 bits.");
7565 assert(0 <= Offset && "Extension offset must be positive.");
7566 assert((Offset < NumEltsPerLane || Offset % NumEltsPerLane == 0) &&
7567 "Extension offset must be in the first lane or start an upper lane.");
7569 // Check that an index is in same lane as the base offset.
7570 auto SafeOffset = [&](int Idx) {
7571 return OffsetLane == (Idx / NumEltsPerLane);
7574 // Shift along an input so that the offset base moves to the first element.
7575 auto ShuffleOffset = [&](SDValue V) {
7579 SmallVector<int, 8> ShMask((unsigned)NumElements, -1);
7580 for (int i = 0; i * Scale < NumElements; ++i) {
7581 int SrcIdx = i + Offset;
7582 ShMask[i] = SafeOffset(SrcIdx) ? SrcIdx : -1;
7584 return DAG.getVectorShuffle(VT, DL, V, DAG.getUNDEF(VT), ShMask);
7587 // Found a valid zext mask! Try various lowering strategies based on the
7588 // input type and available ISA extensions.
7589 if (Subtarget->hasSSE41()) {
7590 // Not worth offseting 128-bit vectors if scale == 2, a pattern using
7591 // PUNPCK will catch this in a later shuffle match.
7592 if (Offset && Scale == 2 && VT.is128BitVector())
7594 MVT ExtVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits * Scale),
7595 NumElements / Scale);
7596 InputV = DAG.getNode(X86ISD::VZEXT, DL, ExtVT, ShuffleOffset(InputV));
7597 return DAG.getBitcast(VT, InputV);
7600 assert(VT.is128BitVector() && "Only 128-bit vectors can be extended.");
7602 // For any extends we can cheat for larger element sizes and use shuffle
7603 // instructions that can fold with a load and/or copy.
7604 if (AnyExt && EltBits == 32) {
7605 int PSHUFDMask[4] = {Offset, -1, SafeOffset(Offset + 1) ? Offset + 1 : -1,
7607 return DAG.getBitcast(
7608 VT, DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
7609 DAG.getBitcast(MVT::v4i32, InputV),
7610 getV4X86ShuffleImm8ForMask(PSHUFDMask, DL, DAG)));
7612 if (AnyExt && EltBits == 16 && Scale > 2) {
7613 int PSHUFDMask[4] = {Offset / 2, -1,
7614 SafeOffset(Offset + 1) ? (Offset + 1) / 2 : -1, -1};
7615 InputV = DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
7616 DAG.getBitcast(MVT::v4i32, InputV),
7617 getV4X86ShuffleImm8ForMask(PSHUFDMask, DL, DAG));
7618 int PSHUFWMask[4] = {1, -1, -1, -1};
7619 unsigned OddEvenOp = (Offset & 1 ? X86ISD::PSHUFLW : X86ISD::PSHUFHW);
7620 return DAG.getBitcast(
7621 VT, DAG.getNode(OddEvenOp, DL, MVT::v8i16,
7622 DAG.getBitcast(MVT::v8i16, InputV),
7623 getV4X86ShuffleImm8ForMask(PSHUFWMask, DL, DAG)));
7626 // The SSE4A EXTRQ instruction can efficiently extend the first 2 lanes
7628 if ((Scale * EltBits) == 64 && EltBits < 32 && Subtarget->hasSSE4A()) {
7629 assert(NumElements == (int)Mask.size() && "Unexpected shuffle mask size!");
7630 assert(VT.is128BitVector() && "Unexpected vector width!");
7632 int LoIdx = Offset * EltBits;
7633 SDValue Lo = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64,
7634 DAG.getNode(X86ISD::EXTRQI, DL, VT, InputV,
7635 DAG.getConstant(EltBits, DL, MVT::i8),
7636 DAG.getConstant(LoIdx, DL, MVT::i8)));
7638 if (isUndefInRange(Mask, NumElements / 2, NumElements / 2) ||
7639 !SafeOffset(Offset + 1))
7640 return DAG.getNode(ISD::BITCAST, DL, VT, Lo);
7642 int HiIdx = (Offset + 1) * EltBits;
7643 SDValue Hi = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64,
7644 DAG.getNode(X86ISD::EXTRQI, DL, VT, InputV,
7645 DAG.getConstant(EltBits, DL, MVT::i8),
7646 DAG.getConstant(HiIdx, DL, MVT::i8)));
7647 return DAG.getNode(ISD::BITCAST, DL, VT,
7648 DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2i64, Lo, Hi));
7651 // If this would require more than 2 unpack instructions to expand, use
7652 // pshufb when available. We can only use more than 2 unpack instructions
7653 // when zero extending i8 elements which also makes it easier to use pshufb.
7654 if (Scale > 4 && EltBits == 8 && Subtarget->hasSSSE3()) {
7655 assert(NumElements == 16 && "Unexpected byte vector width!");
7656 SDValue PSHUFBMask[16];
7657 for (int i = 0; i < 16; ++i) {
7658 int Idx = Offset + (i / Scale);
7659 PSHUFBMask[i] = DAG.getConstant(
7660 (i % Scale == 0 && SafeOffset(Idx)) ? Idx : 0x80, DL, MVT::i8);
7662 InputV = DAG.getBitcast(MVT::v16i8, InputV);
7663 return DAG.getBitcast(VT,
7664 DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, InputV,
7665 DAG.getNode(ISD::BUILD_VECTOR, DL,
7666 MVT::v16i8, PSHUFBMask)));
7669 // If we are extending from an offset, ensure we start on a boundary that
7670 // we can unpack from.
7671 int AlignToUnpack = Offset % (NumElements / Scale);
7672 if (AlignToUnpack) {
7673 SmallVector<int, 8> ShMask((unsigned)NumElements, -1);
7674 for (int i = AlignToUnpack; i < NumElements; ++i)
7675 ShMask[i - AlignToUnpack] = i;
7676 InputV = DAG.getVectorShuffle(VT, DL, InputV, DAG.getUNDEF(VT), ShMask);
7677 Offset -= AlignToUnpack;
7680 // Otherwise emit a sequence of unpacks.
7682 unsigned UnpackLoHi = X86ISD::UNPCKL;
7683 if (Offset >= (NumElements / 2)) {
7684 UnpackLoHi = X86ISD::UNPCKH;
7685 Offset -= (NumElements / 2);
7688 MVT InputVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits), NumElements);
7689 SDValue Ext = AnyExt ? DAG.getUNDEF(InputVT)
7690 : getZeroVector(InputVT, Subtarget, DAG, DL);
7691 InputV = DAG.getBitcast(InputVT, InputV);
7692 InputV = DAG.getNode(UnpackLoHi, DL, InputVT, InputV, Ext);
7696 } while (Scale > 1);
7697 return DAG.getBitcast(VT, InputV);
7700 /// \brief Try to lower a vector shuffle as a zero extension on any microarch.
7702 /// This routine will try to do everything in its power to cleverly lower
7703 /// a shuffle which happens to match the pattern of a zero extend. It doesn't
7704 /// check for the profitability of this lowering, it tries to aggressively
7705 /// match this pattern. It will use all of the micro-architectural details it
7706 /// can to emit an efficient lowering. It handles both blends with all-zero
7707 /// inputs to explicitly zero-extend and undef-lanes (sometimes undef due to
7708 /// masking out later).
7710 /// The reason we have dedicated lowering for zext-style shuffles is that they
7711 /// are both incredibly common and often quite performance sensitive.
7712 static SDValue lowerVectorShuffleAsZeroOrAnyExtend(
7713 SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
7714 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7715 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7717 int Bits = VT.getSizeInBits();
7718 int NumLanes = Bits / 128;
7719 int NumElements = VT.getVectorNumElements();
7720 int NumEltsPerLane = NumElements / NumLanes;
7721 assert(VT.getScalarSizeInBits() <= 32 &&
7722 "Exceeds 32-bit integer zero extension limit");
7723 assert((int)Mask.size() == NumElements && "Unexpected shuffle mask size");
7725 // Define a helper function to check a particular ext-scale and lower to it if
7727 auto Lower = [&](int Scale) -> SDValue {
7732 for (int i = 0; i < NumElements; ++i) {
7735 continue; // Valid anywhere but doesn't tell us anything.
7736 if (i % Scale != 0) {
7737 // Each of the extended elements need to be zeroable.
7741 // We no longer are in the anyext case.
7746 // Each of the base elements needs to be consecutive indices into the
7747 // same input vector.
7748 SDValue V = M < NumElements ? V1 : V2;
7749 M = M % NumElements;
7752 Offset = M - (i / Scale);
7753 } else if (InputV != V)
7754 return SDValue(); // Flip-flopping inputs.
7756 // Offset must start in the lowest 128-bit lane or at the start of an
7758 // FIXME: Is it ever worth allowing a negative base offset?
7759 if (!((0 <= Offset && Offset < NumEltsPerLane) ||
7760 (Offset % NumEltsPerLane) == 0))
7763 // If we are offsetting, all referenced entries must come from the same
7765 if (Offset && (Offset / NumEltsPerLane) != (M / NumEltsPerLane))
7768 if ((M % NumElements) != (Offset + (i / Scale)))
7769 return SDValue(); // Non-consecutive strided elements.
7773 // If we fail to find an input, we have a zero-shuffle which should always
7774 // have already been handled.
7775 // FIXME: Maybe handle this here in case during blending we end up with one?
7779 // If we are offsetting, don't extend if we only match a single input, we
7780 // can always do better by using a basic PSHUF or PUNPCK.
7781 if (Offset != 0 && Matches < 2)
7784 return lowerVectorShuffleAsSpecificZeroOrAnyExtend(
7785 DL, VT, Scale, Offset, AnyExt, InputV, Mask, Subtarget, DAG);
7788 // The widest scale possible for extending is to a 64-bit integer.
7789 assert(Bits % 64 == 0 &&
7790 "The number of bits in a vector must be divisible by 64 on x86!");
7791 int NumExtElements = Bits / 64;
7793 // Each iteration, try extending the elements half as much, but into twice as
7795 for (; NumExtElements < NumElements; NumExtElements *= 2) {
7796 assert(NumElements % NumExtElements == 0 &&
7797 "The input vector size must be divisible by the extended size.");
7798 if (SDValue V = Lower(NumElements / NumExtElements))
7802 // General extends failed, but 128-bit vectors may be able to use MOVQ.
7806 // Returns one of the source operands if the shuffle can be reduced to a
7807 // MOVQ, copying the lower 64-bits and zero-extending to the upper 64-bits.
7808 auto CanZExtLowHalf = [&]() {
7809 for (int i = NumElements / 2; i != NumElements; ++i)
7812 if (isSequentialOrUndefInRange(Mask, 0, NumElements / 2, 0))
7814 if (isSequentialOrUndefInRange(Mask, 0, NumElements / 2, NumElements))
7819 if (SDValue V = CanZExtLowHalf()) {
7820 V = DAG.getBitcast(MVT::v2i64, V);
7821 V = DAG.getNode(X86ISD::VZEXT_MOVL, DL, MVT::v2i64, V);
7822 return DAG.getBitcast(VT, V);
7825 // No viable ext lowering found.
7829 /// \brief Try to get a scalar value for a specific element of a vector.
7831 /// Looks through BUILD_VECTOR and SCALAR_TO_VECTOR nodes to find a scalar.
7832 static SDValue getScalarValueForVectorElement(SDValue V, int Idx,
7833 SelectionDAG &DAG) {
7834 MVT VT = V.getSimpleValueType();
7835 MVT EltVT = VT.getVectorElementType();
7836 while (V.getOpcode() == ISD::BITCAST)
7837 V = V.getOperand(0);
7838 // If the bitcasts shift the element size, we can't extract an equivalent
7840 MVT NewVT = V.getSimpleValueType();
7841 if (!NewVT.isVector() || NewVT.getScalarSizeInBits() != VT.getScalarSizeInBits())
7844 if (V.getOpcode() == ISD::BUILD_VECTOR ||
7845 (Idx == 0 && V.getOpcode() == ISD::SCALAR_TO_VECTOR)) {
7846 // Ensure the scalar operand is the same size as the destination.
7847 // FIXME: Add support for scalar truncation where possible.
7848 SDValue S = V.getOperand(Idx);
7849 if (EltVT.getSizeInBits() == S.getSimpleValueType().getSizeInBits())
7850 return DAG.getNode(ISD::BITCAST, SDLoc(V), EltVT, S);
7856 /// \brief Helper to test for a load that can be folded with x86 shuffles.
7858 /// This is particularly important because the set of instructions varies
7859 /// significantly based on whether the operand is a load or not.
7860 static bool isShuffleFoldableLoad(SDValue V) {
7861 while (V.getOpcode() == ISD::BITCAST)
7862 V = V.getOperand(0);
7864 return ISD::isNON_EXTLoad(V.getNode());
7867 /// \brief Try to lower insertion of a single element into a zero vector.
7869 /// This is a common pattern that we have especially efficient patterns to lower
7870 /// across all subtarget feature sets.
7871 static SDValue lowerVectorShuffleAsElementInsertion(
7872 SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
7873 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7874 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7876 MVT EltVT = VT.getVectorElementType();
7878 int V2Index = std::find_if(Mask.begin(), Mask.end(),
7879 [&Mask](int M) { return M >= (int)Mask.size(); }) -
7881 bool IsV1Zeroable = true;
7882 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7883 if (i != V2Index && !Zeroable[i]) {
7884 IsV1Zeroable = false;
7888 // Check for a single input from a SCALAR_TO_VECTOR node.
7889 // FIXME: All of this should be canonicalized into INSERT_VECTOR_ELT and
7890 // all the smarts here sunk into that routine. However, the current
7891 // lowering of BUILD_VECTOR makes that nearly impossible until the old
7892 // vector shuffle lowering is dead.
7893 SDValue V2S = getScalarValueForVectorElement(V2, Mask[V2Index] - Mask.size(),
7895 if (V2S && DAG.getTargetLoweringInfo().isTypeLegal(V2S.getValueType())) {
7896 // We need to zext the scalar if it is smaller than an i32.
7897 V2S = DAG.getBitcast(EltVT, V2S);
7898 if (EltVT == MVT::i8 || EltVT == MVT::i16) {
7899 // Using zext to expand a narrow element won't work for non-zero
7904 // Zero-extend directly to i32.
7906 V2S = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, V2S);
7908 V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, ExtVT, V2S);
7909 } else if (Mask[V2Index] != (int)Mask.size() || EltVT == MVT::i8 ||
7910 EltVT == MVT::i16) {
7911 // Either not inserting from the low element of the input or the input
7912 // element size is too small to use VZEXT_MOVL to clear the high bits.
7916 if (!IsV1Zeroable) {
7917 // If V1 can't be treated as a zero vector we have fewer options to lower
7918 // this. We can't support integer vectors or non-zero targets cheaply, and
7919 // the V1 elements can't be permuted in any way.
7920 assert(VT == ExtVT && "Cannot change extended type when non-zeroable!");
7921 if (!VT.isFloatingPoint() || V2Index != 0)
7923 SmallVector<int, 8> V1Mask(Mask.begin(), Mask.end());
7924 V1Mask[V2Index] = -1;
7925 if (!isNoopShuffleMask(V1Mask))
7927 // This is essentially a special case blend operation, but if we have
7928 // general purpose blend operations, they are always faster. Bail and let
7929 // the rest of the lowering handle these as blends.
7930 if (Subtarget->hasSSE41())
7933 // Otherwise, use MOVSD or MOVSS.
7934 assert((EltVT == MVT::f32 || EltVT == MVT::f64) &&
7935 "Only two types of floating point element types to handle!");
7936 return DAG.getNode(EltVT == MVT::f32 ? X86ISD::MOVSS : X86ISD::MOVSD, DL,
7940 // This lowering only works for the low element with floating point vectors.
7941 if (VT.isFloatingPoint() && V2Index != 0)
7944 V2 = DAG.getNode(X86ISD::VZEXT_MOVL, DL, ExtVT, V2);
7946 V2 = DAG.getBitcast(VT, V2);
7949 // If we have 4 or fewer lanes we can cheaply shuffle the element into
7950 // the desired position. Otherwise it is more efficient to do a vector
7951 // shift left. We know that we can do a vector shift left because all
7952 // the inputs are zero.
7953 if (VT.isFloatingPoint() || VT.getVectorNumElements() <= 4) {
7954 SmallVector<int, 4> V2Shuffle(Mask.size(), 1);
7955 V2Shuffle[V2Index] = 0;
7956 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Shuffle);
7958 V2 = DAG.getBitcast(MVT::v2i64, V2);
7960 X86ISD::VSHLDQ, DL, MVT::v2i64, V2,
7961 DAG.getConstant(V2Index * EltVT.getSizeInBits() / 8, DL,
7962 DAG.getTargetLoweringInfo().getScalarShiftAmountTy(
7963 DAG.getDataLayout(), VT)));
7964 V2 = DAG.getBitcast(VT, V2);
7970 /// \brief Try to lower broadcast of a single - truncated - integer element,
7971 /// coming from a scalar_to_vector/build_vector node \p V0 with larger elements.
7973 /// This assumes we have AVX2.
7974 static SDValue lowerVectorShuffleAsTruncBroadcast(SDLoc DL, MVT VT, SDValue V0,
7976 const X86Subtarget *Subtarget,
7977 SelectionDAG &DAG) {
7978 assert(Subtarget->hasAVX2() &&
7979 "We can only lower integer broadcasts with AVX2!");
7981 EVT EltVT = VT.getVectorElementType();
7982 EVT V0VT = V0.getValueType();
7984 assert(VT.isInteger() && "Unexpected non-integer trunc broadcast!");
7985 assert(V0VT.isVector() && "Unexpected non-vector vector-sized value!");
7987 EVT V0EltVT = V0VT.getVectorElementType();
7988 if (!V0EltVT.isInteger())
7991 const unsigned EltSize = EltVT.getSizeInBits();
7992 const unsigned V0EltSize = V0EltVT.getSizeInBits();
7994 // This is only a truncation if the original element type is larger.
7995 if (V0EltSize <= EltSize)
7998 assert(((V0EltSize % EltSize) == 0) &&
7999 "Scalar type sizes must all be powers of 2 on x86!");
8001 const unsigned V0Opc = V0.getOpcode();
8002 const unsigned Scale = V0EltSize / EltSize;
8003 const unsigned V0BroadcastIdx = BroadcastIdx / Scale;
8005 if ((V0Opc != ISD::SCALAR_TO_VECTOR || V0BroadcastIdx != 0) &&
8006 V0Opc != ISD::BUILD_VECTOR)
8009 SDValue Scalar = V0.getOperand(V0BroadcastIdx);
8011 // If we're extracting non-least-significant bits, shift so we can truncate.
8012 // Hopefully, we can fold away the trunc/srl/load into the broadcast.
8013 // Even if we can't (and !isShuffleFoldableLoad(Scalar)), prefer
8014 // vpbroadcast+vmovd+shr to vpshufb(m)+vmovd.
8015 if (const int OffsetIdx = BroadcastIdx % Scale)
8016 Scalar = DAG.getNode(ISD::SRL, DL, Scalar.getValueType(), Scalar,
8017 DAG.getConstant(OffsetIdx * EltSize, DL, Scalar.getValueType()));
8019 return DAG.getNode(X86ISD::VBROADCAST, DL, VT,
8020 DAG.getNode(ISD::TRUNCATE, DL, EltVT, Scalar));
8023 /// \brief Try to lower broadcast of a single element.
8025 /// For convenience, this code also bundles all of the subtarget feature set
8026 /// filtering. While a little annoying to re-dispatch on type here, there isn't
8027 /// a convenient way to factor it out.
8028 static SDValue lowerVectorShuffleAsBroadcast(SDLoc DL, MVT VT, SDValue V,
8030 const X86Subtarget *Subtarget,
8031 SelectionDAG &DAG) {
8032 if (!Subtarget->hasAVX())
8034 if (VT.isInteger() && !Subtarget->hasAVX2())
8037 // Check that the mask is a broadcast.
8038 int BroadcastIdx = -1;
8040 if (M >= 0 && BroadcastIdx == -1)
8042 else if (M >= 0 && M != BroadcastIdx)
8045 assert(BroadcastIdx < (int)Mask.size() && "We only expect to be called with "
8046 "a sorted mask where the broadcast "
8049 // Go up the chain of (vector) values to find a scalar load that we can
8050 // combine with the broadcast.
8052 switch (V.getOpcode()) {
8053 case ISD::CONCAT_VECTORS: {
8054 int OperandSize = Mask.size() / V.getNumOperands();
8055 V = V.getOperand(BroadcastIdx / OperandSize);
8056 BroadcastIdx %= OperandSize;
8060 case ISD::INSERT_SUBVECTOR: {
8061 SDValue VOuter = V.getOperand(0), VInner = V.getOperand(1);
8062 auto ConstantIdx = dyn_cast<ConstantSDNode>(V.getOperand(2));
8066 int BeginIdx = (int)ConstantIdx->getZExtValue();
8068 BeginIdx + (int)VInner.getSimpleValueType().getVectorNumElements();
8069 if (BroadcastIdx >= BeginIdx && BroadcastIdx < EndIdx) {
8070 BroadcastIdx -= BeginIdx;
8081 // Check if this is a broadcast of a scalar. We special case lowering
8082 // for scalars so that we can more effectively fold with loads.
8083 // First, look through bitcast: if the original value has a larger element
8084 // type than the shuffle, the broadcast element is in essence truncated.
8085 // Make that explicit to ease folding.
8086 if (V.getOpcode() == ISD::BITCAST && VT.isInteger())
8087 if (SDValue TruncBroadcast = lowerVectorShuffleAsTruncBroadcast(
8088 DL, VT, V.getOperand(0), BroadcastIdx, Subtarget, DAG))
8089 return TruncBroadcast;
8091 // Also check the simpler case, where we can directly reuse the scalar.
8092 if (V.getOpcode() == ISD::BUILD_VECTOR ||
8093 (V.getOpcode() == ISD::SCALAR_TO_VECTOR && BroadcastIdx == 0)) {
8094 V = V.getOperand(BroadcastIdx);
8096 // If the scalar isn't a load, we can't broadcast from it in AVX1.
8097 // Only AVX2 has register broadcasts.
8098 if (!Subtarget->hasAVX2() && !isShuffleFoldableLoad(V))
8100 } else if (BroadcastIdx != 0 || !Subtarget->hasAVX2()) {
8101 // We can't broadcast from a vector register without AVX2, and we can only
8102 // broadcast from the zero-element of a vector register.
8106 return DAG.getNode(X86ISD::VBROADCAST, DL, VT, V);
8109 // Check for whether we can use INSERTPS to perform the shuffle. We only use
8110 // INSERTPS when the V1 elements are already in the correct locations
8111 // because otherwise we can just always use two SHUFPS instructions which
8112 // are much smaller to encode than a SHUFPS and an INSERTPS. We can also
8113 // perform INSERTPS if a single V1 element is out of place and all V2
8114 // elements are zeroable.
8115 static SDValue lowerVectorShuffleAsInsertPS(SDValue Op, SDValue V1, SDValue V2,
8117 SelectionDAG &DAG) {
8118 assert(Op.getSimpleValueType() == MVT::v4f32 && "Bad shuffle type!");
8119 assert(V1.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
8120 assert(V2.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
8121 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
8123 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
8126 int V1DstIndex = -1;
8127 int V2DstIndex = -1;
8128 bool V1UsedInPlace = false;
8130 for (int i = 0; i < 4; ++i) {
8131 // Synthesize a zero mask from the zeroable elements (includes undefs).
8137 // Flag if we use any V1 inputs in place.
8139 V1UsedInPlace = true;
8143 // We can only insert a single non-zeroable element.
8144 if (V1DstIndex != -1 || V2DstIndex != -1)
8148 // V1 input out of place for insertion.
8151 // V2 input for insertion.
8156 // Don't bother if we have no (non-zeroable) element for insertion.
8157 if (V1DstIndex == -1 && V2DstIndex == -1)
8160 // Determine element insertion src/dst indices. The src index is from the
8161 // start of the inserted vector, not the start of the concatenated vector.
8162 unsigned V2SrcIndex = 0;
8163 if (V1DstIndex != -1) {
8164 // If we have a V1 input out of place, we use V1 as the V2 element insertion
8165 // and don't use the original V2 at all.
8166 V2SrcIndex = Mask[V1DstIndex];
8167 V2DstIndex = V1DstIndex;
8170 V2SrcIndex = Mask[V2DstIndex] - 4;
8173 // If no V1 inputs are used in place, then the result is created only from
8174 // the zero mask and the V2 insertion - so remove V1 dependency.
8176 V1 = DAG.getUNDEF(MVT::v4f32);
8178 unsigned InsertPSMask = V2SrcIndex << 6 | V2DstIndex << 4 | ZMask;
8179 assert((InsertPSMask & ~0xFFu) == 0 && "Invalid mask!");
8181 // Insert the V2 element into the desired position.
8183 return DAG.getNode(X86ISD::INSERTPS, DL, MVT::v4f32, V1, V2,
8184 DAG.getConstant(InsertPSMask, DL, MVT::i8));
8187 /// \brief Try to lower a shuffle as a permute of the inputs followed by an
8188 /// UNPCK instruction.
8190 /// This specifically targets cases where we end up with alternating between
8191 /// the two inputs, and so can permute them into something that feeds a single
8192 /// UNPCK instruction. Note that this routine only targets integer vectors
8193 /// because for floating point vectors we have a generalized SHUFPS lowering
8194 /// strategy that handles everything that doesn't *exactly* match an unpack,
8195 /// making this clever lowering unnecessary.
8196 static SDValue lowerVectorShuffleAsPermuteAndUnpack(SDLoc DL, MVT VT,
8197 SDValue V1, SDValue V2,
8199 SelectionDAG &DAG) {
8200 assert(!VT.isFloatingPoint() &&
8201 "This routine only supports integer vectors.");
8202 assert(!isSingleInputShuffleMask(Mask) &&
8203 "This routine should only be used when blending two inputs.");
8204 assert(Mask.size() >= 2 && "Single element masks are invalid.");
8206 int Size = Mask.size();
8208 int NumLoInputs = std::count_if(Mask.begin(), Mask.end(), [Size](int M) {
8209 return M >= 0 && M % Size < Size / 2;
8211 int NumHiInputs = std::count_if(
8212 Mask.begin(), Mask.end(), [Size](int M) { return M % Size >= Size / 2; });
8214 bool UnpackLo = NumLoInputs >= NumHiInputs;
8216 auto TryUnpack = [&](MVT UnpackVT, int Scale) {
8217 SmallVector<int, 32> V1Mask(Mask.size(), -1);
8218 SmallVector<int, 32> V2Mask(Mask.size(), -1);
8220 for (int i = 0; i < Size; ++i) {
8224 // Each element of the unpack contains Scale elements from this mask.
8225 int UnpackIdx = i / Scale;
8227 // We only handle the case where V1 feeds the first slots of the unpack.
8228 // We rely on canonicalization to ensure this is the case.
8229 if ((UnpackIdx % 2 == 0) != (Mask[i] < Size))
8232 // Setup the mask for this input. The indexing is tricky as we have to
8233 // handle the unpack stride.
8234 SmallVectorImpl<int> &VMask = (UnpackIdx % 2 == 0) ? V1Mask : V2Mask;
8235 VMask[(UnpackIdx / 2) * Scale + i % Scale + (UnpackLo ? 0 : Size / 2)] =
8239 // If we will have to shuffle both inputs to use the unpack, check whether
8240 // we can just unpack first and shuffle the result. If so, skip this unpack.
8241 if ((NumLoInputs == 0 || NumHiInputs == 0) && !isNoopShuffleMask(V1Mask) &&
8242 !isNoopShuffleMask(V2Mask))
8245 // Shuffle the inputs into place.
8246 V1 = DAG.getVectorShuffle(VT, DL, V1, DAG.getUNDEF(VT), V1Mask);
8247 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Mask);
8249 // Cast the inputs to the type we will use to unpack them.
8250 V1 = DAG.getBitcast(UnpackVT, V1);
8251 V2 = DAG.getBitcast(UnpackVT, V2);
8253 // Unpack the inputs and cast the result back to the desired type.
8254 return DAG.getBitcast(
8255 VT, DAG.getNode(UnpackLo ? X86ISD::UNPCKL : X86ISD::UNPCKH, DL,
8259 // We try each unpack from the largest to the smallest to try and find one
8260 // that fits this mask.
8261 int OrigNumElements = VT.getVectorNumElements();
8262 int OrigScalarSize = VT.getScalarSizeInBits();
8263 for (int ScalarSize = 64; ScalarSize >= OrigScalarSize; ScalarSize /= 2) {
8264 int Scale = ScalarSize / OrigScalarSize;
8265 int NumElements = OrigNumElements / Scale;
8266 MVT UnpackVT = MVT::getVectorVT(MVT::getIntegerVT(ScalarSize), NumElements);
8267 if (SDValue Unpack = TryUnpack(UnpackVT, Scale))
8271 // If none of the unpack-rooted lowerings worked (or were profitable) try an
8273 if (NumLoInputs == 0 || NumHiInputs == 0) {
8274 assert((NumLoInputs > 0 || NumHiInputs > 0) &&
8275 "We have to have *some* inputs!");
8276 int HalfOffset = NumLoInputs == 0 ? Size / 2 : 0;
8278 // FIXME: We could consider the total complexity of the permute of each
8279 // possible unpacking. Or at the least we should consider how many
8280 // half-crossings are created.
8281 // FIXME: We could consider commuting the unpacks.
8283 SmallVector<int, 32> PermMask;
8284 PermMask.assign(Size, -1);
8285 for (int i = 0; i < Size; ++i) {
8289 assert(Mask[i] % Size >= HalfOffset && "Found input from wrong half!");
8292 2 * ((Mask[i] % Size) - HalfOffset) + (Mask[i] < Size ? 0 : 1);
8294 return DAG.getVectorShuffle(
8295 VT, DL, DAG.getNode(NumLoInputs == 0 ? X86ISD::UNPCKH : X86ISD::UNPCKL,
8297 DAG.getUNDEF(VT), PermMask);
8303 /// \brief Handle lowering of 2-lane 64-bit floating point shuffles.
8305 /// This is the basis function for the 2-lane 64-bit shuffles as we have full
8306 /// support for floating point shuffles but not integer shuffles. These
8307 /// instructions will incur a domain crossing penalty on some chips though so
8308 /// it is better to avoid lowering through this for integer vectors where
8310 static SDValue lowerV2F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8311 const X86Subtarget *Subtarget,
8312 SelectionDAG &DAG) {
8314 assert(Op.getSimpleValueType() == MVT::v2f64 && "Bad shuffle type!");
8315 assert(V1.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
8316 assert(V2.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
8317 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8318 ArrayRef<int> Mask = SVOp->getMask();
8319 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
8321 if (isSingleInputShuffleMask(Mask)) {
8322 // Use low duplicate instructions for masks that match their pattern.
8323 if (Subtarget->hasSSE3())
8324 if (isShuffleEquivalent(V1, V2, Mask, {0, 0}))
8325 return DAG.getNode(X86ISD::MOVDDUP, DL, MVT::v2f64, V1);
8327 // Straight shuffle of a single input vector. Simulate this by using the
8328 // single input as both of the "inputs" to this instruction..
8329 unsigned SHUFPDMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1);
8331 if (Subtarget->hasAVX()) {
8332 // If we have AVX, we can use VPERMILPS which will allow folding a load
8333 // into the shuffle.
8334 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v2f64, V1,
8335 DAG.getConstant(SHUFPDMask, DL, MVT::i8));
8338 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v2f64, V1, V1,
8339 DAG.getConstant(SHUFPDMask, DL, MVT::i8));
8341 assert(Mask[0] >= 0 && Mask[0] < 2 && "Non-canonicalized blend!");
8342 assert(Mask[1] >= 2 && "Non-canonicalized blend!");
8344 // If we have a single input, insert that into V1 if we can do so cheaply.
8345 if ((Mask[0] >= 2) + (Mask[1] >= 2) == 1) {
8346 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8347 DL, MVT::v2f64, V1, V2, Mask, Subtarget, DAG))
8349 // Try inverting the insertion since for v2 masks it is easy to do and we
8350 // can't reliably sort the mask one way or the other.
8351 int InverseMask[2] = {Mask[0] < 0 ? -1 : (Mask[0] ^ 2),
8352 Mask[1] < 0 ? -1 : (Mask[1] ^ 2)};
8353 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8354 DL, MVT::v2f64, V2, V1, InverseMask, Subtarget, DAG))
8358 // Try to use one of the special instruction patterns to handle two common
8359 // blend patterns if a zero-blend above didn't work.
8360 if (isShuffleEquivalent(V1, V2, Mask, {0, 3}) ||
8361 isShuffleEquivalent(V1, V2, Mask, {1, 3}))
8362 if (SDValue V1S = getScalarValueForVectorElement(V1, Mask[0], DAG))
8363 // We can either use a special instruction to load over the low double or
8364 // to move just the low double.
8366 isShuffleFoldableLoad(V1S) ? X86ISD::MOVLPD : X86ISD::MOVSD,
8368 DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2f64, V1S));
8370 if (Subtarget->hasSSE41())
8371 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v2f64, V1, V2, Mask,
8375 // Use dedicated unpack instructions for masks that match their pattern.
8377 lowerVectorShuffleWithUNPCK(DL, MVT::v2f64, Mask, V1, V2, DAG))
8380 unsigned SHUFPDMask = (Mask[0] == 1) | (((Mask[1] - 2) == 1) << 1);
8381 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v2f64, V1, V2,
8382 DAG.getConstant(SHUFPDMask, DL, MVT::i8));
8385 /// \brief Handle lowering of 2-lane 64-bit integer shuffles.
8387 /// Tries to lower a 2-lane 64-bit shuffle using shuffle operations provided by
8388 /// the integer unit to minimize domain crossing penalties. However, for blends
8389 /// it falls back to the floating point shuffle operation with appropriate bit
8391 static SDValue lowerV2I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8392 const X86Subtarget *Subtarget,
8393 SelectionDAG &DAG) {
8395 assert(Op.getSimpleValueType() == MVT::v2i64 && "Bad shuffle type!");
8396 assert(V1.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
8397 assert(V2.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
8398 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8399 ArrayRef<int> Mask = SVOp->getMask();
8400 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
8402 if (isSingleInputShuffleMask(Mask)) {
8403 // Check for being able to broadcast a single element.
8404 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v2i64, V1,
8405 Mask, Subtarget, DAG))
8408 // Straight shuffle of a single input vector. For everything from SSE2
8409 // onward this has a single fast instruction with no scary immediates.
8410 // We have to map the mask as it is actually a v4i32 shuffle instruction.
8411 V1 = DAG.getBitcast(MVT::v4i32, V1);
8412 int WidenedMask[4] = {
8413 std::max(Mask[0], 0) * 2, std::max(Mask[0], 0) * 2 + 1,
8414 std::max(Mask[1], 0) * 2, std::max(Mask[1], 0) * 2 + 1};
8415 return DAG.getBitcast(
8417 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V1,
8418 getV4X86ShuffleImm8ForMask(WidenedMask, DL, DAG)));
8420 assert(Mask[0] != -1 && "No undef lanes in multi-input v2 shuffles!");
8421 assert(Mask[1] != -1 && "No undef lanes in multi-input v2 shuffles!");
8422 assert(Mask[0] < 2 && "We sort V1 to be the first input.");
8423 assert(Mask[1] >= 2 && "We sort V2 to be the second input.");
8425 // If we have a blend of two PACKUS operations an the blend aligns with the
8426 // low and half halves, we can just merge the PACKUS operations. This is
8427 // particularly important as it lets us merge shuffles that this routine itself
8429 auto GetPackNode = [](SDValue V) {
8430 while (V.getOpcode() == ISD::BITCAST)
8431 V = V.getOperand(0);
8433 return V.getOpcode() == X86ISD::PACKUS ? V : SDValue();
8435 if (SDValue V1Pack = GetPackNode(V1))
8436 if (SDValue V2Pack = GetPackNode(V2))
8437 return DAG.getBitcast(MVT::v2i64,
8438 DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8,
8439 Mask[0] == 0 ? V1Pack.getOperand(0)
8440 : V1Pack.getOperand(1),
8441 Mask[1] == 2 ? V2Pack.getOperand(0)
8442 : V2Pack.getOperand(1)));
8444 // Try to use shift instructions.
8446 lowerVectorShuffleAsShift(DL, MVT::v2i64, V1, V2, Mask, DAG))
8449 // When loading a scalar and then shuffling it into a vector we can often do
8450 // the insertion cheaply.
8451 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8452 DL, MVT::v2i64, V1, V2, Mask, Subtarget, DAG))
8454 // Try inverting the insertion since for v2 masks it is easy to do and we
8455 // can't reliably sort the mask one way or the other.
8456 int InverseMask[2] = {Mask[0] ^ 2, Mask[1] ^ 2};
8457 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8458 DL, MVT::v2i64, V2, V1, InverseMask, Subtarget, DAG))
8461 // We have different paths for blend lowering, but they all must use the
8462 // *exact* same predicate.
8463 bool IsBlendSupported = Subtarget->hasSSE41();
8464 if (IsBlendSupported)
8465 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v2i64, V1, V2, Mask,
8469 // Use dedicated unpack instructions for masks that match their pattern.
8471 lowerVectorShuffleWithUNPCK(DL, MVT::v2i64, Mask, V1, V2, DAG))
8474 // Try to use byte rotation instructions.
8475 // Its more profitable for pre-SSSE3 to use shuffles/unpacks.
8476 if (Subtarget->hasSSSE3())
8477 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8478 DL, MVT::v2i64, V1, V2, Mask, Subtarget, DAG))
8481 // If we have direct support for blends, we should lower by decomposing into
8482 // a permute. That will be faster than the domain cross.
8483 if (IsBlendSupported)
8484 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v2i64, V1, V2,
8487 // We implement this with SHUFPD which is pretty lame because it will likely
8488 // incur 2 cycles of stall for integer vectors on Nehalem and older chips.
8489 // However, all the alternatives are still more cycles and newer chips don't
8490 // have this problem. It would be really nice if x86 had better shuffles here.
8491 V1 = DAG.getBitcast(MVT::v2f64, V1);
8492 V2 = DAG.getBitcast(MVT::v2f64, V2);
8493 return DAG.getBitcast(MVT::v2i64,
8494 DAG.getVectorShuffle(MVT::v2f64, DL, V1, V2, Mask));
8497 /// \brief Test whether this can be lowered with a single SHUFPS instruction.
8499 /// This is used to disable more specialized lowerings when the shufps lowering
8500 /// will happen to be efficient.
8501 static bool isSingleSHUFPSMask(ArrayRef<int> Mask) {
8502 // This routine only handles 128-bit shufps.
8503 assert(Mask.size() == 4 && "Unsupported mask size!");
8505 // To lower with a single SHUFPS we need to have the low half and high half
8506 // each requiring a single input.
8507 if (Mask[0] != -1 && Mask[1] != -1 && (Mask[0] < 4) != (Mask[1] < 4))
8509 if (Mask[2] != -1 && Mask[3] != -1 && (Mask[2] < 4) != (Mask[3] < 4))
8515 /// \brief Lower a vector shuffle using the SHUFPS instruction.
8517 /// This is a helper routine dedicated to lowering vector shuffles using SHUFPS.
8518 /// It makes no assumptions about whether this is the *best* lowering, it simply
8520 static SDValue lowerVectorShuffleWithSHUFPS(SDLoc DL, MVT VT,
8521 ArrayRef<int> Mask, SDValue V1,
8522 SDValue V2, SelectionDAG &DAG) {
8523 SDValue LowV = V1, HighV = V2;
8524 int NewMask[4] = {Mask[0], Mask[1], Mask[2], Mask[3]};
8527 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
8529 if (NumV2Elements == 1) {
8531 std::find_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; }) -
8534 // Compute the index adjacent to V2Index and in the same half by toggling
8536 int V2AdjIndex = V2Index ^ 1;
8538 if (Mask[V2AdjIndex] == -1) {
8539 // Handles all the cases where we have a single V2 element and an undef.
8540 // This will only ever happen in the high lanes because we commute the
8541 // vector otherwise.
8543 std::swap(LowV, HighV);
8544 NewMask[V2Index] -= 4;
8546 // Handle the case where the V2 element ends up adjacent to a V1 element.
8547 // To make this work, blend them together as the first step.
8548 int V1Index = V2AdjIndex;
8549 int BlendMask[4] = {Mask[V2Index] - 4, 0, Mask[V1Index], 0};
8550 V2 = DAG.getNode(X86ISD::SHUFP, DL, VT, V2, V1,
8551 getV4X86ShuffleImm8ForMask(BlendMask, DL, DAG));
8553 // Now proceed to reconstruct the final blend as we have the necessary
8554 // high or low half formed.
8561 NewMask[V1Index] = 2; // We put the V1 element in V2[2].
8562 NewMask[V2Index] = 0; // We shifted the V2 element into V2[0].
8564 } else if (NumV2Elements == 2) {
8565 if (Mask[0] < 4 && Mask[1] < 4) {
8566 // Handle the easy case where we have V1 in the low lanes and V2 in the
8570 } else if (Mask[2] < 4 && Mask[3] < 4) {
8571 // We also handle the reversed case because this utility may get called
8572 // when we detect a SHUFPS pattern but can't easily commute the shuffle to
8573 // arrange things in the right direction.
8579 // We have a mixture of V1 and V2 in both low and high lanes. Rather than
8580 // trying to place elements directly, just blend them and set up the final
8581 // shuffle to place them.
8583 // The first two blend mask elements are for V1, the second two are for
8585 int BlendMask[4] = {Mask[0] < 4 ? Mask[0] : Mask[1],
8586 Mask[2] < 4 ? Mask[2] : Mask[3],
8587 (Mask[0] >= 4 ? Mask[0] : Mask[1]) - 4,
8588 (Mask[2] >= 4 ? Mask[2] : Mask[3]) - 4};
8589 V1 = DAG.getNode(X86ISD::SHUFP, DL, VT, V1, V2,
8590 getV4X86ShuffleImm8ForMask(BlendMask, DL, DAG));
8592 // Now we do a normal shuffle of V1 by giving V1 as both operands to
8595 NewMask[0] = Mask[0] < 4 ? 0 : 2;
8596 NewMask[1] = Mask[0] < 4 ? 2 : 0;
8597 NewMask[2] = Mask[2] < 4 ? 1 : 3;
8598 NewMask[3] = Mask[2] < 4 ? 3 : 1;
8601 return DAG.getNode(X86ISD::SHUFP, DL, VT, LowV, HighV,
8602 getV4X86ShuffleImm8ForMask(NewMask, DL, DAG));
8605 /// \brief Lower 4-lane 32-bit floating point shuffles.
8607 /// Uses instructions exclusively from the floating point unit to minimize
8608 /// domain crossing penalties, as these are sufficient to implement all v4f32
8610 static SDValue lowerV4F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8611 const X86Subtarget *Subtarget,
8612 SelectionDAG &DAG) {
8614 assert(Op.getSimpleValueType() == MVT::v4f32 && "Bad shuffle type!");
8615 assert(V1.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
8616 assert(V2.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
8617 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8618 ArrayRef<int> Mask = SVOp->getMask();
8619 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
8622 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
8624 if (NumV2Elements == 0) {
8625 // Check for being able to broadcast a single element.
8626 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v4f32, V1,
8627 Mask, Subtarget, DAG))
8630 // Use even/odd duplicate instructions for masks that match their pattern.
8631 if (Subtarget->hasSSE3()) {
8632 if (isShuffleEquivalent(V1, V2, Mask, {0, 0, 2, 2}))
8633 return DAG.getNode(X86ISD::MOVSLDUP, DL, MVT::v4f32, V1);
8634 if (isShuffleEquivalent(V1, V2, Mask, {1, 1, 3, 3}))
8635 return DAG.getNode(X86ISD::MOVSHDUP, DL, MVT::v4f32, V1);
8638 if (Subtarget->hasAVX()) {
8639 // If we have AVX, we can use VPERMILPS which will allow folding a load
8640 // into the shuffle.
8641 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v4f32, V1,
8642 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
8645 // Otherwise, use a straight shuffle of a single input vector. We pass the
8646 // input vector to both operands to simulate this with a SHUFPS.
8647 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f32, V1, V1,
8648 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
8651 // There are special ways we can lower some single-element blends. However, we
8652 // have custom ways we can lower more complex single-element blends below that
8653 // we defer to if both this and BLENDPS fail to match, so restrict this to
8654 // when the V2 input is targeting element 0 of the mask -- that is the fast
8656 if (NumV2Elements == 1 && Mask[0] >= 4)
8657 if (SDValue V = lowerVectorShuffleAsElementInsertion(DL, MVT::v4f32, V1, V2,
8658 Mask, Subtarget, DAG))
8661 if (Subtarget->hasSSE41()) {
8662 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4f32, V1, V2, Mask,
8666 // Use INSERTPS if we can complete the shuffle efficiently.
8667 if (SDValue V = lowerVectorShuffleAsInsertPS(Op, V1, V2, Mask, DAG))
8670 if (!isSingleSHUFPSMask(Mask))
8671 if (SDValue BlendPerm = lowerVectorShuffleAsBlendAndPermute(
8672 DL, MVT::v4f32, V1, V2, Mask, DAG))
8676 // Use dedicated unpack instructions for masks that match their pattern.
8678 lowerVectorShuffleWithUNPCK(DL, MVT::v4f32, Mask, V1, V2, DAG))
8681 // Otherwise fall back to a SHUFPS lowering strategy.
8682 return lowerVectorShuffleWithSHUFPS(DL, MVT::v4f32, Mask, V1, V2, DAG);
8685 /// \brief Lower 4-lane i32 vector shuffles.
8687 /// We try to handle these with integer-domain shuffles where we can, but for
8688 /// blends we use the floating point domain blend instructions.
8689 static SDValue lowerV4I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8690 const X86Subtarget *Subtarget,
8691 SelectionDAG &DAG) {
8693 assert(Op.getSimpleValueType() == MVT::v4i32 && "Bad shuffle type!");
8694 assert(V1.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
8695 assert(V2.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
8696 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8697 ArrayRef<int> Mask = SVOp->getMask();
8698 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
8700 // Whenever we can lower this as a zext, that instruction is strictly faster
8701 // than any alternative. It also allows us to fold memory operands into the
8702 // shuffle in many cases.
8703 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v4i32, V1, V2,
8704 Mask, Subtarget, DAG))
8708 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
8710 if (NumV2Elements == 0) {
8711 // Check for being able to broadcast a single element.
8712 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v4i32, V1,
8713 Mask, Subtarget, DAG))
8716 // Straight shuffle of a single input vector. For everything from SSE2
8717 // onward this has a single fast instruction with no scary immediates.
8718 // We coerce the shuffle pattern to be compatible with UNPCK instructions
8719 // but we aren't actually going to use the UNPCK instruction because doing
8720 // so prevents folding a load into this instruction or making a copy.
8721 const int UnpackLoMask[] = {0, 0, 1, 1};
8722 const int UnpackHiMask[] = {2, 2, 3, 3};
8723 if (isShuffleEquivalent(V1, V2, Mask, {0, 0, 1, 1}))
8724 Mask = UnpackLoMask;
8725 else if (isShuffleEquivalent(V1, V2, Mask, {2, 2, 3, 3}))
8726 Mask = UnpackHiMask;
8728 return DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V1,
8729 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
8732 // Try to use shift instructions.
8734 lowerVectorShuffleAsShift(DL, MVT::v4i32, V1, V2, Mask, DAG))
8737 // There are special ways we can lower some single-element blends.
8738 if (NumV2Elements == 1)
8739 if (SDValue V = lowerVectorShuffleAsElementInsertion(DL, MVT::v4i32, V1, V2,
8740 Mask, Subtarget, DAG))
8743 // We have different paths for blend lowering, but they all must use the
8744 // *exact* same predicate.
8745 bool IsBlendSupported = Subtarget->hasSSE41();
8746 if (IsBlendSupported)
8747 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4i32, V1, V2, Mask,
8751 if (SDValue Masked =
8752 lowerVectorShuffleAsBitMask(DL, MVT::v4i32, V1, V2, Mask, DAG))
8755 // Use dedicated unpack instructions for masks that match their pattern.
8757 lowerVectorShuffleWithUNPCK(DL, MVT::v4i32, Mask, V1, V2, DAG))
8760 // Try to use byte rotation instructions.
8761 // Its more profitable for pre-SSSE3 to use shuffles/unpacks.
8762 if (Subtarget->hasSSSE3())
8763 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8764 DL, MVT::v4i32, V1, V2, Mask, Subtarget, DAG))
8767 // If we have direct support for blends, we should lower by decomposing into
8768 // a permute. That will be faster than the domain cross.
8769 if (IsBlendSupported)
8770 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4i32, V1, V2,
8773 // Try to lower by permuting the inputs into an unpack instruction.
8774 if (SDValue Unpack = lowerVectorShuffleAsPermuteAndUnpack(DL, MVT::v4i32, V1,
8778 // We implement this with SHUFPS because it can blend from two vectors.
8779 // Because we're going to eventually use SHUFPS, we use SHUFPS even to build
8780 // up the inputs, bypassing domain shift penalties that we would encur if we
8781 // directly used PSHUFD on Nehalem and older. For newer chips, this isn't
8783 return DAG.getBitcast(
8785 DAG.getVectorShuffle(MVT::v4f32, DL, DAG.getBitcast(MVT::v4f32, V1),
8786 DAG.getBitcast(MVT::v4f32, V2), Mask));
8789 /// \brief Lowering of single-input v8i16 shuffles is the cornerstone of SSE2
8790 /// shuffle lowering, and the most complex part.
8792 /// The lowering strategy is to try to form pairs of input lanes which are
8793 /// targeted at the same half of the final vector, and then use a dword shuffle
8794 /// to place them onto the right half, and finally unpack the paired lanes into
8795 /// their final position.
8797 /// The exact breakdown of how to form these dword pairs and align them on the
8798 /// correct sides is really tricky. See the comments within the function for
8799 /// more of the details.
8801 /// This code also handles repeated 128-bit lanes of v8i16 shuffles, but each
8802 /// lane must shuffle the *exact* same way. In fact, you must pass a v8 Mask to
8803 /// this routine for it to work correctly. To shuffle a 256-bit or 512-bit i16
8804 /// vector, form the analogous 128-bit 8-element Mask.
8805 static SDValue lowerV8I16GeneralSingleInputVectorShuffle(
8806 SDLoc DL, MVT VT, SDValue V, MutableArrayRef<int> Mask,
8807 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
8808 assert(VT.getVectorElementType() == MVT::i16 && "Bad input type!");
8809 MVT PSHUFDVT = MVT::getVectorVT(MVT::i32, VT.getVectorNumElements() / 2);
8811 assert(Mask.size() == 8 && "Shuffle mask length doen't match!");
8812 MutableArrayRef<int> LoMask = Mask.slice(0, 4);
8813 MutableArrayRef<int> HiMask = Mask.slice(4, 4);
8815 SmallVector<int, 4> LoInputs;
8816 std::copy_if(LoMask.begin(), LoMask.end(), std::back_inserter(LoInputs),
8817 [](int M) { return M >= 0; });
8818 std::sort(LoInputs.begin(), LoInputs.end());
8819 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()), LoInputs.end());
8820 SmallVector<int, 4> HiInputs;
8821 std::copy_if(HiMask.begin(), HiMask.end(), std::back_inserter(HiInputs),
8822 [](int M) { return M >= 0; });
8823 std::sort(HiInputs.begin(), HiInputs.end());
8824 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()), HiInputs.end());
8826 std::lower_bound(LoInputs.begin(), LoInputs.end(), 4) - LoInputs.begin();
8827 int NumHToL = LoInputs.size() - NumLToL;
8829 std::lower_bound(HiInputs.begin(), HiInputs.end(), 4) - HiInputs.begin();
8830 int NumHToH = HiInputs.size() - NumLToH;
8831 MutableArrayRef<int> LToLInputs(LoInputs.data(), NumLToL);
8832 MutableArrayRef<int> LToHInputs(HiInputs.data(), NumLToH);
8833 MutableArrayRef<int> HToLInputs(LoInputs.data() + NumLToL, NumHToL);
8834 MutableArrayRef<int> HToHInputs(HiInputs.data() + NumLToH, NumHToH);
8836 // Simplify the 1-into-3 and 3-into-1 cases with a single pshufd. For all
8837 // such inputs we can swap two of the dwords across the half mark and end up
8838 // with <=2 inputs to each half in each half. Once there, we can fall through
8839 // to the generic code below. For example:
8841 // Input: [a, b, c, d, e, f, g, h] -PSHUFD[0,2,1,3]-> [a, b, e, f, c, d, g, h]
8842 // Mask: [0, 1, 2, 7, 4, 5, 6, 3] -----------------> [0, 1, 4, 7, 2, 3, 6, 5]
8844 // However in some very rare cases we have a 1-into-3 or 3-into-1 on one half
8845 // and an existing 2-into-2 on the other half. In this case we may have to
8846 // pre-shuffle the 2-into-2 half to avoid turning it into a 3-into-1 or
8847 // 1-into-3 which could cause us to cycle endlessly fixing each side in turn.
8848 // Fortunately, we don't have to handle anything but a 2-into-2 pattern
8849 // because any other situation (including a 3-into-1 or 1-into-3 in the other
8850 // half than the one we target for fixing) will be fixed when we re-enter this
8851 // path. We will also combine away any sequence of PSHUFD instructions that
8852 // result into a single instruction. Here is an example of the tricky case:
8854 // Input: [a, b, c, d, e, f, g, h] -PSHUFD[0,2,1,3]-> [a, b, e, f, c, d, g, h]
8855 // Mask: [3, 7, 1, 0, 2, 7, 3, 5] -THIS-IS-BAD!!!!-> [5, 7, 1, 0, 4, 7, 5, 3]
8857 // This now has a 1-into-3 in the high half! Instead, we do two shuffles:
8859 // Input: [a, b, c, d, e, f, g, h] PSHUFHW[0,2,1,3]-> [a, b, c, d, e, g, f, h]
8860 // Mask: [3, 7, 1, 0, 2, 7, 3, 5] -----------------> [3, 7, 1, 0, 2, 7, 3, 6]
8862 // Input: [a, b, c, d, e, g, f, h] -PSHUFD[0,2,1,3]-> [a, b, e, g, c, d, f, h]
8863 // Mask: [3, 7, 1, 0, 2, 7, 3, 6] -----------------> [5, 7, 1, 0, 4, 7, 5, 6]
8865 // The result is fine to be handled by the generic logic.
8866 auto balanceSides = [&](ArrayRef<int> AToAInputs, ArrayRef<int> BToAInputs,
8867 ArrayRef<int> BToBInputs, ArrayRef<int> AToBInputs,
8868 int AOffset, int BOffset) {
8869 assert((AToAInputs.size() == 3 || AToAInputs.size() == 1) &&
8870 "Must call this with A having 3 or 1 inputs from the A half.");
8871 assert((BToAInputs.size() == 1 || BToAInputs.size() == 3) &&
8872 "Must call this with B having 1 or 3 inputs from the B half.");
8873 assert(AToAInputs.size() + BToAInputs.size() == 4 &&
8874 "Must call this with either 3:1 or 1:3 inputs (summing to 4).");
8876 bool ThreeAInputs = AToAInputs.size() == 3;
8878 // Compute the index of dword with only one word among the three inputs in
8879 // a half by taking the sum of the half with three inputs and subtracting
8880 // the sum of the actual three inputs. The difference is the remaining
8883 int &TripleDWord = ThreeAInputs ? ADWord : BDWord;
8884 int &OneInputDWord = ThreeAInputs ? BDWord : ADWord;
8885 int TripleInputOffset = ThreeAInputs ? AOffset : BOffset;
8886 ArrayRef<int> TripleInputs = ThreeAInputs ? AToAInputs : BToAInputs;
8887 int OneInput = ThreeAInputs ? BToAInputs[0] : AToAInputs[0];
8888 int TripleInputSum = 0 + 1 + 2 + 3 + (4 * TripleInputOffset);
8889 int TripleNonInputIdx =
8890 TripleInputSum - std::accumulate(TripleInputs.begin(), TripleInputs.end(), 0);
8891 TripleDWord = TripleNonInputIdx / 2;
8893 // We use xor with one to compute the adjacent DWord to whichever one the
8895 OneInputDWord = (OneInput / 2) ^ 1;
8897 // Check for one tricky case: We're fixing a 3<-1 or a 1<-3 shuffle for AToA
8898 // and BToA inputs. If there is also such a problem with the BToB and AToB
8899 // inputs, we don't try to fix it necessarily -- we'll recurse and see it in
8900 // the next pass. However, if we have a 2<-2 in the BToB and AToB inputs, it
8901 // is essential that we don't *create* a 3<-1 as then we might oscillate.
8902 if (BToBInputs.size() == 2 && AToBInputs.size() == 2) {
8903 // Compute how many inputs will be flipped by swapping these DWords. We
8905 // to balance this to ensure we don't form a 3-1 shuffle in the other
8907 int NumFlippedAToBInputs =
8908 std::count(AToBInputs.begin(), AToBInputs.end(), 2 * ADWord) +
8909 std::count(AToBInputs.begin(), AToBInputs.end(), 2 * ADWord + 1);
8910 int NumFlippedBToBInputs =
8911 std::count(BToBInputs.begin(), BToBInputs.end(), 2 * BDWord) +
8912 std::count(BToBInputs.begin(), BToBInputs.end(), 2 * BDWord + 1);
8913 if ((NumFlippedAToBInputs == 1 &&
8914 (NumFlippedBToBInputs == 0 || NumFlippedBToBInputs == 2)) ||
8915 (NumFlippedBToBInputs == 1 &&
8916 (NumFlippedAToBInputs == 0 || NumFlippedAToBInputs == 2))) {
8917 // We choose whether to fix the A half or B half based on whether that
8918 // half has zero flipped inputs. At zero, we may not be able to fix it
8919 // with that half. We also bias towards fixing the B half because that
8920 // will more commonly be the high half, and we have to bias one way.
8921 auto FixFlippedInputs = [&V, &DL, &Mask, &DAG](int PinnedIdx, int DWord,
8922 ArrayRef<int> Inputs) {
8923 int FixIdx = PinnedIdx ^ 1; // The adjacent slot to the pinned slot.
8924 bool IsFixIdxInput = std::find(Inputs.begin(), Inputs.end(),
8925 PinnedIdx ^ 1) != Inputs.end();
8926 // Determine whether the free index is in the flipped dword or the
8927 // unflipped dword based on where the pinned index is. We use this bit
8928 // in an xor to conditionally select the adjacent dword.
8929 int FixFreeIdx = 2 * (DWord ^ (PinnedIdx / 2 == DWord));
8930 bool IsFixFreeIdxInput = std::find(Inputs.begin(), Inputs.end(),
8931 FixFreeIdx) != Inputs.end();
8932 if (IsFixIdxInput == IsFixFreeIdxInput)
8934 IsFixFreeIdxInput = std::find(Inputs.begin(), Inputs.end(),
8935 FixFreeIdx) != Inputs.end();
8936 assert(IsFixIdxInput != IsFixFreeIdxInput &&
8937 "We need to be changing the number of flipped inputs!");
8938 int PSHUFHalfMask[] = {0, 1, 2, 3};
8939 std::swap(PSHUFHalfMask[FixFreeIdx % 4], PSHUFHalfMask[FixIdx % 4]);
8940 V = DAG.getNode(FixIdx < 4 ? X86ISD::PSHUFLW : X86ISD::PSHUFHW, DL,
8942 getV4X86ShuffleImm8ForMask(PSHUFHalfMask, DL, DAG));
8945 if (M != -1 && M == FixIdx)
8947 else if (M != -1 && M == FixFreeIdx)
8950 if (NumFlippedBToBInputs != 0) {
8952 BToAInputs.size() == 3 ? TripleNonInputIdx : OneInput;
8953 FixFlippedInputs(BPinnedIdx, BDWord, BToBInputs);
8955 assert(NumFlippedAToBInputs != 0 && "Impossible given predicates!");
8956 int APinnedIdx = ThreeAInputs ? TripleNonInputIdx : OneInput;
8957 FixFlippedInputs(APinnedIdx, ADWord, AToBInputs);
8962 int PSHUFDMask[] = {0, 1, 2, 3};
8963 PSHUFDMask[ADWord] = BDWord;
8964 PSHUFDMask[BDWord] = ADWord;
8967 DAG.getNode(X86ISD::PSHUFD, DL, PSHUFDVT, DAG.getBitcast(PSHUFDVT, V),
8968 getV4X86ShuffleImm8ForMask(PSHUFDMask, DL, DAG)));
8970 // Adjust the mask to match the new locations of A and B.
8972 if (M != -1 && M/2 == ADWord)
8973 M = 2 * BDWord + M % 2;
8974 else if (M != -1 && M/2 == BDWord)
8975 M = 2 * ADWord + M % 2;
8977 // Recurse back into this routine to re-compute state now that this isn't
8978 // a 3 and 1 problem.
8979 return lowerV8I16GeneralSingleInputVectorShuffle(DL, VT, V, Mask, Subtarget,
8982 if ((NumLToL == 3 && NumHToL == 1) || (NumLToL == 1 && NumHToL == 3))
8983 return balanceSides(LToLInputs, HToLInputs, HToHInputs, LToHInputs, 0, 4);
8984 else if ((NumHToH == 3 && NumLToH == 1) || (NumHToH == 1 && NumLToH == 3))
8985 return balanceSides(HToHInputs, LToHInputs, LToLInputs, HToLInputs, 4, 0);
8987 // At this point there are at most two inputs to the low and high halves from
8988 // each half. That means the inputs can always be grouped into dwords and
8989 // those dwords can then be moved to the correct half with a dword shuffle.
8990 // We use at most one low and one high word shuffle to collect these paired
8991 // inputs into dwords, and finally a dword shuffle to place them.
8992 int PSHUFLMask[4] = {-1, -1, -1, -1};
8993 int PSHUFHMask[4] = {-1, -1, -1, -1};
8994 int PSHUFDMask[4] = {-1, -1, -1, -1};
8996 // First fix the masks for all the inputs that are staying in their
8997 // original halves. This will then dictate the targets of the cross-half
8999 auto fixInPlaceInputs =
9000 [&PSHUFDMask](ArrayRef<int> InPlaceInputs, ArrayRef<int> IncomingInputs,
9001 MutableArrayRef<int> SourceHalfMask,
9002 MutableArrayRef<int> HalfMask, int HalfOffset) {
9003 if (InPlaceInputs.empty())
9005 if (InPlaceInputs.size() == 1) {
9006 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
9007 InPlaceInputs[0] - HalfOffset;
9008 PSHUFDMask[InPlaceInputs[0] / 2] = InPlaceInputs[0] / 2;
9011 if (IncomingInputs.empty()) {
9012 // Just fix all of the in place inputs.
9013 for (int Input : InPlaceInputs) {
9014 SourceHalfMask[Input - HalfOffset] = Input - HalfOffset;
9015 PSHUFDMask[Input / 2] = Input / 2;
9020 assert(InPlaceInputs.size() == 2 && "Cannot handle 3 or 4 inputs!");
9021 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
9022 InPlaceInputs[0] - HalfOffset;
9023 // Put the second input next to the first so that they are packed into
9024 // a dword. We find the adjacent index by toggling the low bit.
9025 int AdjIndex = InPlaceInputs[0] ^ 1;
9026 SourceHalfMask[AdjIndex - HalfOffset] = InPlaceInputs[1] - HalfOffset;
9027 std::replace(HalfMask.begin(), HalfMask.end(), InPlaceInputs[1], AdjIndex);
9028 PSHUFDMask[AdjIndex / 2] = AdjIndex / 2;
9030 fixInPlaceInputs(LToLInputs, HToLInputs, PSHUFLMask, LoMask, 0);
9031 fixInPlaceInputs(HToHInputs, LToHInputs, PSHUFHMask, HiMask, 4);
9033 // Now gather the cross-half inputs and place them into a free dword of
9034 // their target half.
9035 // FIXME: This operation could almost certainly be simplified dramatically to
9036 // look more like the 3-1 fixing operation.
9037 auto moveInputsToRightHalf = [&PSHUFDMask](
9038 MutableArrayRef<int> IncomingInputs, ArrayRef<int> ExistingInputs,
9039 MutableArrayRef<int> SourceHalfMask, MutableArrayRef<int> HalfMask,
9040 MutableArrayRef<int> FinalSourceHalfMask, int SourceOffset,
9042 auto isWordClobbered = [](ArrayRef<int> SourceHalfMask, int Word) {
9043 return SourceHalfMask[Word] != -1 && SourceHalfMask[Word] != Word;
9045 auto isDWordClobbered = [&isWordClobbered](ArrayRef<int> SourceHalfMask,
9047 int LowWord = Word & ~1;
9048 int HighWord = Word | 1;
9049 return isWordClobbered(SourceHalfMask, LowWord) ||
9050 isWordClobbered(SourceHalfMask, HighWord);
9053 if (IncomingInputs.empty())
9056 if (ExistingInputs.empty()) {
9057 // Map any dwords with inputs from them into the right half.
9058 for (int Input : IncomingInputs) {
9059 // If the source half mask maps over the inputs, turn those into
9060 // swaps and use the swapped lane.
9061 if (isWordClobbered(SourceHalfMask, Input - SourceOffset)) {
9062 if (SourceHalfMask[SourceHalfMask[Input - SourceOffset]] == -1) {
9063 SourceHalfMask[SourceHalfMask[Input - SourceOffset]] =
9064 Input - SourceOffset;
9065 // We have to swap the uses in our half mask in one sweep.
9066 for (int &M : HalfMask)
9067 if (M == SourceHalfMask[Input - SourceOffset] + SourceOffset)
9069 else if (M == Input)
9070 M = SourceHalfMask[Input - SourceOffset] + SourceOffset;
9072 assert(SourceHalfMask[SourceHalfMask[Input - SourceOffset]] ==
9073 Input - SourceOffset &&
9074 "Previous placement doesn't match!");
9076 // Note that this correctly re-maps both when we do a swap and when
9077 // we observe the other side of the swap above. We rely on that to
9078 // avoid swapping the members of the input list directly.
9079 Input = SourceHalfMask[Input - SourceOffset] + SourceOffset;
9082 // Map the input's dword into the correct half.
9083 if (PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] == -1)
9084 PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] = Input / 2;
9086 assert(PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] ==
9088 "Previous placement doesn't match!");
9091 // And just directly shift any other-half mask elements to be same-half
9092 // as we will have mirrored the dword containing the element into the
9093 // same position within that half.
9094 for (int &M : HalfMask)
9095 if (M >= SourceOffset && M < SourceOffset + 4) {
9096 M = M - SourceOffset + DestOffset;
9097 assert(M >= 0 && "This should never wrap below zero!");
9102 // Ensure we have the input in a viable dword of its current half. This
9103 // is particularly tricky because the original position may be clobbered
9104 // by inputs being moved and *staying* in that half.
9105 if (IncomingInputs.size() == 1) {
9106 if (isWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
9107 int InputFixed = std::find(std::begin(SourceHalfMask),
9108 std::end(SourceHalfMask), -1) -
9109 std::begin(SourceHalfMask) + SourceOffset;
9110 SourceHalfMask[InputFixed - SourceOffset] =
9111 IncomingInputs[0] - SourceOffset;
9112 std::replace(HalfMask.begin(), HalfMask.end(), IncomingInputs[0],
9114 IncomingInputs[0] = InputFixed;
9116 } else if (IncomingInputs.size() == 2) {
9117 if (IncomingInputs[0] / 2 != IncomingInputs[1] / 2 ||
9118 isDWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
9119 // We have two non-adjacent or clobbered inputs we need to extract from
9120 // the source half. To do this, we need to map them into some adjacent
9121 // dword slot in the source mask.
9122 int InputsFixed[2] = {IncomingInputs[0] - SourceOffset,
9123 IncomingInputs[1] - SourceOffset};
9125 // If there is a free slot in the source half mask adjacent to one of
9126 // the inputs, place the other input in it. We use (Index XOR 1) to
9127 // compute an adjacent index.
9128 if (!isWordClobbered(SourceHalfMask, InputsFixed[0]) &&
9129 SourceHalfMask[InputsFixed[0] ^ 1] == -1) {
9130 SourceHalfMask[InputsFixed[0]] = InputsFixed[0];
9131 SourceHalfMask[InputsFixed[0] ^ 1] = InputsFixed[1];
9132 InputsFixed[1] = InputsFixed[0] ^ 1;
9133 } else if (!isWordClobbered(SourceHalfMask, InputsFixed[1]) &&
9134 SourceHalfMask[InputsFixed[1] ^ 1] == -1) {
9135 SourceHalfMask[InputsFixed[1]] = InputsFixed[1];
9136 SourceHalfMask[InputsFixed[1] ^ 1] = InputsFixed[0];
9137 InputsFixed[0] = InputsFixed[1] ^ 1;
9138 } else if (SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1)] == -1 &&
9139 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1) + 1] == -1) {
9140 // The two inputs are in the same DWord but it is clobbered and the
9141 // adjacent DWord isn't used at all. Move both inputs to the free
9143 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1)] = InputsFixed[0];
9144 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1) + 1] = InputsFixed[1];
9145 InputsFixed[0] = 2 * ((InputsFixed[0] / 2) ^ 1);
9146 InputsFixed[1] = 2 * ((InputsFixed[0] / 2) ^ 1) + 1;
9148 // The only way we hit this point is if there is no clobbering
9149 // (because there are no off-half inputs to this half) and there is no
9150 // free slot adjacent to one of the inputs. In this case, we have to
9151 // swap an input with a non-input.
9152 for (int i = 0; i < 4; ++i)
9153 assert((SourceHalfMask[i] == -1 || SourceHalfMask[i] == i) &&
9154 "We can't handle any clobbers here!");
9155 assert(InputsFixed[1] != (InputsFixed[0] ^ 1) &&
9156 "Cannot have adjacent inputs here!");
9158 SourceHalfMask[InputsFixed[0] ^ 1] = InputsFixed[1];
9159 SourceHalfMask[InputsFixed[1]] = InputsFixed[0] ^ 1;
9161 // We also have to update the final source mask in this case because
9162 // it may need to undo the above swap.
9163 for (int &M : FinalSourceHalfMask)
9164 if (M == (InputsFixed[0] ^ 1) + SourceOffset)
9165 M = InputsFixed[1] + SourceOffset;
9166 else if (M == InputsFixed[1] + SourceOffset)
9167 M = (InputsFixed[0] ^ 1) + SourceOffset;
9169 InputsFixed[1] = InputsFixed[0] ^ 1;
9172 // Point everything at the fixed inputs.
9173 for (int &M : HalfMask)
9174 if (M == IncomingInputs[0])
9175 M = InputsFixed[0] + SourceOffset;
9176 else if (M == IncomingInputs[1])
9177 M = InputsFixed[1] + SourceOffset;
9179 IncomingInputs[0] = InputsFixed[0] + SourceOffset;
9180 IncomingInputs[1] = InputsFixed[1] + SourceOffset;
9183 llvm_unreachable("Unhandled input size!");
9186 // Now hoist the DWord down to the right half.
9187 int FreeDWord = (PSHUFDMask[DestOffset / 2] == -1 ? 0 : 1) + DestOffset / 2;
9188 assert(PSHUFDMask[FreeDWord] == -1 && "DWord not free");
9189 PSHUFDMask[FreeDWord] = IncomingInputs[0] / 2;
9190 for (int &M : HalfMask)
9191 for (int Input : IncomingInputs)
9193 M = FreeDWord * 2 + Input % 2;
9195 moveInputsToRightHalf(HToLInputs, LToLInputs, PSHUFHMask, LoMask, HiMask,
9196 /*SourceOffset*/ 4, /*DestOffset*/ 0);
9197 moveInputsToRightHalf(LToHInputs, HToHInputs, PSHUFLMask, HiMask, LoMask,
9198 /*SourceOffset*/ 0, /*DestOffset*/ 4);
9200 // Now enact all the shuffles we've computed to move the inputs into their
9202 if (!isNoopShuffleMask(PSHUFLMask))
9203 V = DAG.getNode(X86ISD::PSHUFLW, DL, VT, V,
9204 getV4X86ShuffleImm8ForMask(PSHUFLMask, DL, DAG));
9205 if (!isNoopShuffleMask(PSHUFHMask))
9206 V = DAG.getNode(X86ISD::PSHUFHW, DL, VT, V,
9207 getV4X86ShuffleImm8ForMask(PSHUFHMask, DL, DAG));
9208 if (!isNoopShuffleMask(PSHUFDMask))
9211 DAG.getNode(X86ISD::PSHUFD, DL, PSHUFDVT, DAG.getBitcast(PSHUFDVT, V),
9212 getV4X86ShuffleImm8ForMask(PSHUFDMask, DL, DAG)));
9214 // At this point, each half should contain all its inputs, and we can then
9215 // just shuffle them into their final position.
9216 assert(std::count_if(LoMask.begin(), LoMask.end(),
9217 [](int M) { return M >= 4; }) == 0 &&
9218 "Failed to lift all the high half inputs to the low mask!");
9219 assert(std::count_if(HiMask.begin(), HiMask.end(),
9220 [](int M) { return M >= 0 && M < 4; }) == 0 &&
9221 "Failed to lift all the low half inputs to the high mask!");
9223 // Do a half shuffle for the low mask.
9224 if (!isNoopShuffleMask(LoMask))
9225 V = DAG.getNode(X86ISD::PSHUFLW, DL, VT, V,
9226 getV4X86ShuffleImm8ForMask(LoMask, DL, DAG));
9228 // Do a half shuffle with the high mask after shifting its values down.
9229 for (int &M : HiMask)
9232 if (!isNoopShuffleMask(HiMask))
9233 V = DAG.getNode(X86ISD::PSHUFHW, DL, VT, V,
9234 getV4X86ShuffleImm8ForMask(HiMask, DL, DAG));
9239 /// \brief Helper to form a PSHUFB-based shuffle+blend.
9240 static SDValue lowerVectorShuffleAsPSHUFB(SDLoc DL, MVT VT, SDValue V1,
9241 SDValue V2, ArrayRef<int> Mask,
9242 SelectionDAG &DAG, bool &V1InUse,
9244 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
9250 int Size = Mask.size();
9251 int Scale = 16 / Size;
9252 for (int i = 0; i < 16; ++i) {
9253 if (Mask[i / Scale] == -1) {
9254 V1Mask[i] = V2Mask[i] = DAG.getUNDEF(MVT::i8);
9256 const int ZeroMask = 0x80;
9257 int V1Idx = Mask[i / Scale] < Size ? Mask[i / Scale] * Scale + i % Scale
9259 int V2Idx = Mask[i / Scale] < Size
9261 : (Mask[i / Scale] - Size) * Scale + i % Scale;
9262 if (Zeroable[i / Scale])
9263 V1Idx = V2Idx = ZeroMask;
9264 V1Mask[i] = DAG.getConstant(V1Idx, DL, MVT::i8);
9265 V2Mask[i] = DAG.getConstant(V2Idx, DL, MVT::i8);
9266 V1InUse |= (ZeroMask != V1Idx);
9267 V2InUse |= (ZeroMask != V2Idx);
9272 V1 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8,
9273 DAG.getBitcast(MVT::v16i8, V1),
9274 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V1Mask));
9276 V2 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8,
9277 DAG.getBitcast(MVT::v16i8, V2),
9278 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V2Mask));
9280 // If we need shuffled inputs from both, blend the two.
9282 if (V1InUse && V2InUse)
9283 V = DAG.getNode(ISD::OR, DL, MVT::v16i8, V1, V2);
9285 V = V1InUse ? V1 : V2;
9287 // Cast the result back to the correct type.
9288 return DAG.getBitcast(VT, V);
9291 /// \brief Generic lowering of 8-lane i16 shuffles.
9293 /// This handles both single-input shuffles and combined shuffle/blends with
9294 /// two inputs. The single input shuffles are immediately delegated to
9295 /// a dedicated lowering routine.
9297 /// The blends are lowered in one of three fundamental ways. If there are few
9298 /// enough inputs, it delegates to a basic UNPCK-based strategy. If the shuffle
9299 /// of the input is significantly cheaper when lowered as an interleaving of
9300 /// the two inputs, try to interleave them. Otherwise, blend the low and high
9301 /// halves of the inputs separately (making them have relatively few inputs)
9302 /// and then concatenate them.
9303 static SDValue lowerV8I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9304 const X86Subtarget *Subtarget,
9305 SelectionDAG &DAG) {
9307 assert(Op.getSimpleValueType() == MVT::v8i16 && "Bad shuffle type!");
9308 assert(V1.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
9309 assert(V2.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
9310 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9311 ArrayRef<int> OrigMask = SVOp->getMask();
9312 int MaskStorage[8] = {OrigMask[0], OrigMask[1], OrigMask[2], OrigMask[3],
9313 OrigMask[4], OrigMask[5], OrigMask[6], OrigMask[7]};
9314 MutableArrayRef<int> Mask(MaskStorage);
9316 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
9318 // Whenever we can lower this as a zext, that instruction is strictly faster
9319 // than any alternative.
9320 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(
9321 DL, MVT::v8i16, V1, V2, OrigMask, Subtarget, DAG))
9324 auto isV1 = [](int M) { return M >= 0 && M < 8; };
9326 auto isV2 = [](int M) { return M >= 8; };
9328 int NumV2Inputs = std::count_if(Mask.begin(), Mask.end(), isV2);
9330 if (NumV2Inputs == 0) {
9331 // Check for being able to broadcast a single element.
9332 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v8i16, V1,
9333 Mask, Subtarget, DAG))
9336 // Try to use shift instructions.
9338 lowerVectorShuffleAsShift(DL, MVT::v8i16, V1, V1, Mask, DAG))
9341 // Use dedicated unpack instructions for masks that match their pattern.
9343 lowerVectorShuffleWithUNPCK(DL, MVT::v8i16, Mask, V1, V2, DAG))
9346 // Try to use byte rotation instructions.
9347 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(DL, MVT::v8i16, V1, V1,
9348 Mask, Subtarget, DAG))
9351 return lowerV8I16GeneralSingleInputVectorShuffle(DL, MVT::v8i16, V1, Mask,
9355 assert(std::any_of(Mask.begin(), Mask.end(), isV1) &&
9356 "All single-input shuffles should be canonicalized to be V1-input "
9359 // Try to use shift instructions.
9361 lowerVectorShuffleAsShift(DL, MVT::v8i16, V1, V2, Mask, DAG))
9364 // See if we can use SSE4A Extraction / Insertion.
9365 if (Subtarget->hasSSE4A())
9366 if (SDValue V = lowerVectorShuffleWithSSE4A(DL, MVT::v8i16, V1, V2, Mask, DAG))
9369 // There are special ways we can lower some single-element blends.
9370 if (NumV2Inputs == 1)
9371 if (SDValue V = lowerVectorShuffleAsElementInsertion(DL, MVT::v8i16, V1, V2,
9372 Mask, Subtarget, DAG))
9375 // We have different paths for blend lowering, but they all must use the
9376 // *exact* same predicate.
9377 bool IsBlendSupported = Subtarget->hasSSE41();
9378 if (IsBlendSupported)
9379 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8i16, V1, V2, Mask,
9383 if (SDValue Masked =
9384 lowerVectorShuffleAsBitMask(DL, MVT::v8i16, V1, V2, Mask, DAG))
9387 // Use dedicated unpack instructions for masks that match their pattern.
9389 lowerVectorShuffleWithUNPCK(DL, MVT::v8i16, Mask, V1, V2, DAG))
9392 // Try to use byte rotation instructions.
9393 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
9394 DL, MVT::v8i16, V1, V2, Mask, Subtarget, DAG))
9397 if (SDValue BitBlend =
9398 lowerVectorShuffleAsBitBlend(DL, MVT::v8i16, V1, V2, Mask, DAG))
9401 if (SDValue Unpack = lowerVectorShuffleAsPermuteAndUnpack(DL, MVT::v8i16, V1,
9405 // If we can't directly blend but can use PSHUFB, that will be better as it
9406 // can both shuffle and set up the inefficient blend.
9407 if (!IsBlendSupported && Subtarget->hasSSSE3()) {
9408 bool V1InUse, V2InUse;
9409 return lowerVectorShuffleAsPSHUFB(DL, MVT::v8i16, V1, V2, Mask, DAG,
9413 // We can always bit-blend if we have to so the fallback strategy is to
9414 // decompose into single-input permutes and blends.
9415 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8i16, V1, V2,
9419 /// \brief Check whether a compaction lowering can be done by dropping even
9420 /// elements and compute how many times even elements must be dropped.
9422 /// This handles shuffles which take every Nth element where N is a power of
9423 /// two. Example shuffle masks:
9425 /// N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 0, 2, 4, 6, 8, 10, 12, 14
9426 /// N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30
9427 /// N = 2: 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12
9428 /// N = 2: 0, 4, 8, 12, 16, 20, 24, 28, 0, 4, 8, 12, 16, 20, 24, 28
9429 /// N = 3: 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8
9430 /// N = 3: 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24
9432 /// Any of these lanes can of course be undef.
9434 /// This routine only supports N <= 3.
9435 /// FIXME: Evaluate whether either AVX or AVX-512 have any opportunities here
9438 /// \returns N above, or the number of times even elements must be dropped if
9439 /// there is such a number. Otherwise returns zero.
9440 static int canLowerByDroppingEvenElements(ArrayRef<int> Mask) {
9441 // Figure out whether we're looping over two inputs or just one.
9442 bool IsSingleInput = isSingleInputShuffleMask(Mask);
9444 // The modulus for the shuffle vector entries is based on whether this is
9445 // a single input or not.
9446 int ShuffleModulus = Mask.size() * (IsSingleInput ? 1 : 2);
9447 assert(isPowerOf2_32((uint32_t)ShuffleModulus) &&
9448 "We should only be called with masks with a power-of-2 size!");
9450 uint64_t ModMask = (uint64_t)ShuffleModulus - 1;
9452 // We track whether the input is viable for all power-of-2 strides 2^1, 2^2,
9453 // and 2^3 simultaneously. This is because we may have ambiguity with
9454 // partially undef inputs.
9455 bool ViableForN[3] = {true, true, true};
9457 for (int i = 0, e = Mask.size(); i < e; ++i) {
9458 // Ignore undef lanes, we'll optimistically collapse them to the pattern we
9463 bool IsAnyViable = false;
9464 for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
9465 if (ViableForN[j]) {
9468 // The shuffle mask must be equal to (i * 2^N) % M.
9469 if ((uint64_t)Mask[i] == (((uint64_t)i << N) & ModMask))
9472 ViableForN[j] = false;
9474 // Early exit if we exhaust the possible powers of two.
9479 for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
9483 // Return 0 as there is no viable power of two.
9487 /// \brief Generic lowering of v16i8 shuffles.
9489 /// This is a hybrid strategy to lower v16i8 vectors. It first attempts to
9490 /// detect any complexity reducing interleaving. If that doesn't help, it uses
9491 /// UNPCK to spread the i8 elements across two i16-element vectors, and uses
9492 /// the existing lowering for v8i16 blends on each half, finally PACK-ing them
9494 static SDValue lowerV16I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9495 const X86Subtarget *Subtarget,
9496 SelectionDAG &DAG) {
9498 assert(Op.getSimpleValueType() == MVT::v16i8 && "Bad shuffle type!");
9499 assert(V1.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
9500 assert(V2.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
9501 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9502 ArrayRef<int> Mask = SVOp->getMask();
9503 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
9505 // Try to use shift instructions.
9507 lowerVectorShuffleAsShift(DL, MVT::v16i8, V1, V2, Mask, DAG))
9510 // Try to use byte rotation instructions.
9511 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
9512 DL, MVT::v16i8, V1, V2, Mask, Subtarget, DAG))
9515 // Try to use a zext lowering.
9516 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(
9517 DL, MVT::v16i8, V1, V2, Mask, Subtarget, DAG))
9520 // See if we can use SSE4A Extraction / Insertion.
9521 if (Subtarget->hasSSE4A())
9522 if (SDValue V = lowerVectorShuffleWithSSE4A(DL, MVT::v16i8, V1, V2, Mask, DAG))
9526 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 16; });
9528 // For single-input shuffles, there are some nicer lowering tricks we can use.
9529 if (NumV2Elements == 0) {
9530 // Check for being able to broadcast a single element.
9531 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v16i8, V1,
9532 Mask, Subtarget, DAG))
9535 // Check whether we can widen this to an i16 shuffle by duplicating bytes.
9536 // Notably, this handles splat and partial-splat shuffles more efficiently.
9537 // However, it only makes sense if the pre-duplication shuffle simplifies
9538 // things significantly. Currently, this means we need to be able to
9539 // express the pre-duplication shuffle as an i16 shuffle.
9541 // FIXME: We should check for other patterns which can be widened into an
9542 // i16 shuffle as well.
9543 auto canWidenViaDuplication = [](ArrayRef<int> Mask) {
9544 for (int i = 0; i < 16; i += 2)
9545 if (Mask[i] != -1 && Mask[i + 1] != -1 && Mask[i] != Mask[i + 1])
9550 auto tryToWidenViaDuplication = [&]() -> SDValue {
9551 if (!canWidenViaDuplication(Mask))
9553 SmallVector<int, 4> LoInputs;
9554 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(LoInputs),
9555 [](int M) { return M >= 0 && M < 8; });
9556 std::sort(LoInputs.begin(), LoInputs.end());
9557 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()),
9559 SmallVector<int, 4> HiInputs;
9560 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(HiInputs),
9561 [](int M) { return M >= 8; });
9562 std::sort(HiInputs.begin(), HiInputs.end());
9563 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()),
9566 bool TargetLo = LoInputs.size() >= HiInputs.size();
9567 ArrayRef<int> InPlaceInputs = TargetLo ? LoInputs : HiInputs;
9568 ArrayRef<int> MovingInputs = TargetLo ? HiInputs : LoInputs;
9570 int PreDupI16Shuffle[] = {-1, -1, -1, -1, -1, -1, -1, -1};
9571 SmallDenseMap<int, int, 8> LaneMap;
9572 for (int I : InPlaceInputs) {
9573 PreDupI16Shuffle[I/2] = I/2;
9576 int j = TargetLo ? 0 : 4, je = j + 4;
9577 for (int i = 0, ie = MovingInputs.size(); i < ie; ++i) {
9578 // Check if j is already a shuffle of this input. This happens when
9579 // there are two adjacent bytes after we move the low one.
9580 if (PreDupI16Shuffle[j] != MovingInputs[i] / 2) {
9581 // If we haven't yet mapped the input, search for a slot into which
9583 while (j < je && PreDupI16Shuffle[j] != -1)
9587 // We can't place the inputs into a single half with a simple i16 shuffle, so bail.
9590 // Map this input with the i16 shuffle.
9591 PreDupI16Shuffle[j] = MovingInputs[i] / 2;
9594 // Update the lane map based on the mapping we ended up with.
9595 LaneMap[MovingInputs[i]] = 2 * j + MovingInputs[i] % 2;
9597 V1 = DAG.getBitcast(
9599 DAG.getVectorShuffle(MVT::v8i16, DL, DAG.getBitcast(MVT::v8i16, V1),
9600 DAG.getUNDEF(MVT::v8i16), PreDupI16Shuffle));
9602 // Unpack the bytes to form the i16s that will be shuffled into place.
9603 V1 = DAG.getNode(TargetLo ? X86ISD::UNPCKL : X86ISD::UNPCKH, DL,
9604 MVT::v16i8, V1, V1);
9606 int PostDupI16Shuffle[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9607 for (int i = 0; i < 16; ++i)
9608 if (Mask[i] != -1) {
9609 int MappedMask = LaneMap[Mask[i]] - (TargetLo ? 0 : 8);
9610 assert(MappedMask < 8 && "Invalid v8 shuffle mask!");
9611 if (PostDupI16Shuffle[i / 2] == -1)
9612 PostDupI16Shuffle[i / 2] = MappedMask;
9614 assert(PostDupI16Shuffle[i / 2] == MappedMask &&
9615 "Conflicting entrties in the original shuffle!");
9617 return DAG.getBitcast(
9619 DAG.getVectorShuffle(MVT::v8i16, DL, DAG.getBitcast(MVT::v8i16, V1),
9620 DAG.getUNDEF(MVT::v8i16), PostDupI16Shuffle));
9622 if (SDValue V = tryToWidenViaDuplication())
9626 if (SDValue Masked =
9627 lowerVectorShuffleAsBitMask(DL, MVT::v16i8, V1, V2, Mask, DAG))
9630 // Use dedicated unpack instructions for masks that match their pattern.
9632 lowerVectorShuffleWithUNPCK(DL, MVT::v16i8, Mask, V1, V2, DAG))
9635 // Check for SSSE3 which lets us lower all v16i8 shuffles much more directly
9636 // with PSHUFB. It is important to do this before we attempt to generate any
9637 // blends but after all of the single-input lowerings. If the single input
9638 // lowerings can find an instruction sequence that is faster than a PSHUFB, we
9639 // want to preserve that and we can DAG combine any longer sequences into
9640 // a PSHUFB in the end. But once we start blending from multiple inputs,
9641 // the complexity of DAG combining bad patterns back into PSHUFB is too high,
9642 // and there are *very* few patterns that would actually be faster than the
9643 // PSHUFB approach because of its ability to zero lanes.
9645 // FIXME: The only exceptions to the above are blends which are exact
9646 // interleavings with direct instructions supporting them. We currently don't
9647 // handle those well here.
9648 if (Subtarget->hasSSSE3()) {
9649 bool V1InUse = false;
9650 bool V2InUse = false;
9652 SDValue PSHUFB = lowerVectorShuffleAsPSHUFB(DL, MVT::v16i8, V1, V2, Mask,
9653 DAG, V1InUse, V2InUse);
9655 // If both V1 and V2 are in use and we can use a direct blend or an unpack,
9656 // do so. This avoids using them to handle blends-with-zero which is
9657 // important as a single pshufb is significantly faster for that.
9658 if (V1InUse && V2InUse) {
9659 if (Subtarget->hasSSE41())
9660 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v16i8, V1, V2,
9661 Mask, Subtarget, DAG))
9664 // We can use an unpack to do the blending rather than an or in some
9665 // cases. Even though the or may be (very minorly) more efficient, we
9666 // preference this lowering because there are common cases where part of
9667 // the complexity of the shuffles goes away when we do the final blend as
9669 // FIXME: It might be worth trying to detect if the unpack-feeding
9670 // shuffles will both be pshufb, in which case we shouldn't bother with
9672 if (SDValue Unpack = lowerVectorShuffleAsPermuteAndUnpack(
9673 DL, MVT::v16i8, V1, V2, Mask, DAG))
9680 // There are special ways we can lower some single-element blends.
9681 if (NumV2Elements == 1)
9682 if (SDValue V = lowerVectorShuffleAsElementInsertion(DL, MVT::v16i8, V1, V2,
9683 Mask, Subtarget, DAG))
9686 if (SDValue BitBlend =
9687 lowerVectorShuffleAsBitBlend(DL, MVT::v16i8, V1, V2, Mask, DAG))
9690 // Check whether a compaction lowering can be done. This handles shuffles
9691 // which take every Nth element for some even N. See the helper function for
9694 // We special case these as they can be particularly efficiently handled with
9695 // the PACKUSB instruction on x86 and they show up in common patterns of
9696 // rearranging bytes to truncate wide elements.
9697 if (int NumEvenDrops = canLowerByDroppingEvenElements(Mask)) {
9698 // NumEvenDrops is the power of two stride of the elements. Another way of
9699 // thinking about it is that we need to drop the even elements this many
9700 // times to get the original input.
9701 bool IsSingleInput = isSingleInputShuffleMask(Mask);
9703 // First we need to zero all the dropped bytes.
9704 assert(NumEvenDrops <= 3 &&
9705 "No support for dropping even elements more than 3 times.");
9706 // We use the mask type to pick which bytes are preserved based on how many
9707 // elements are dropped.
9708 MVT MaskVTs[] = { MVT::v8i16, MVT::v4i32, MVT::v2i64 };
9709 SDValue ByteClearMask = DAG.getBitcast(
9710 MVT::v16i8, DAG.getConstant(0xFF, DL, MaskVTs[NumEvenDrops - 1]));
9711 V1 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V1, ByteClearMask);
9713 V2 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V2, ByteClearMask);
9715 // Now pack things back together.
9716 V1 = DAG.getBitcast(MVT::v8i16, V1);
9717 V2 = IsSingleInput ? V1 : DAG.getBitcast(MVT::v8i16, V2);
9718 SDValue Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, V1, V2);
9719 for (int i = 1; i < NumEvenDrops; ++i) {
9720 Result = DAG.getBitcast(MVT::v8i16, Result);
9721 Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, Result, Result);
9727 // Handle multi-input cases by blending single-input shuffles.
9728 if (NumV2Elements > 0)
9729 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v16i8, V1, V2,
9732 // The fallback path for single-input shuffles widens this into two v8i16
9733 // vectors with unpacks, shuffles those, and then pulls them back together
9737 int LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9738 int HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9739 for (int i = 0; i < 16; ++i)
9741 (i < 8 ? LoBlendMask[i] : HiBlendMask[i % 8]) = Mask[i];
9743 SDValue Zero = getZeroVector(MVT::v8i16, Subtarget, DAG, DL);
9745 SDValue VLoHalf, VHiHalf;
9746 // Check if any of the odd lanes in the v16i8 are used. If not, we can mask
9747 // them out and avoid using UNPCK{L,H} to extract the elements of V as
9749 if (std::none_of(std::begin(LoBlendMask), std::end(LoBlendMask),
9750 [](int M) { return M >= 0 && M % 2 == 1; }) &&
9751 std::none_of(std::begin(HiBlendMask), std::end(HiBlendMask),
9752 [](int M) { return M >= 0 && M % 2 == 1; })) {
9753 // Use a mask to drop the high bytes.
9754 VLoHalf = DAG.getBitcast(MVT::v8i16, V);
9755 VLoHalf = DAG.getNode(ISD::AND, DL, MVT::v8i16, VLoHalf,
9756 DAG.getConstant(0x00FF, DL, MVT::v8i16));
9758 // This will be a single vector shuffle instead of a blend so nuke VHiHalf.
9759 VHiHalf = DAG.getUNDEF(MVT::v8i16);
9761 // Squash the masks to point directly into VLoHalf.
9762 for (int &M : LoBlendMask)
9765 for (int &M : HiBlendMask)
9769 // Otherwise just unpack the low half of V into VLoHalf and the high half into
9770 // VHiHalf so that we can blend them as i16s.
9771 VLoHalf = DAG.getBitcast(
9772 MVT::v8i16, DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i8, V, Zero));
9773 VHiHalf = DAG.getBitcast(
9774 MVT::v8i16, DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i8, V, Zero));
9777 SDValue LoV = DAG.getVectorShuffle(MVT::v8i16, DL, VLoHalf, VHiHalf, LoBlendMask);
9778 SDValue HiV = DAG.getVectorShuffle(MVT::v8i16, DL, VLoHalf, VHiHalf, HiBlendMask);
9780 return DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, LoV, HiV);
9783 /// \brief Dispatching routine to lower various 128-bit x86 vector shuffles.
9785 /// This routine breaks down the specific type of 128-bit shuffle and
9786 /// dispatches to the lowering routines accordingly.
9787 static SDValue lower128BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9788 MVT VT, const X86Subtarget *Subtarget,
9789 SelectionDAG &DAG) {
9790 switch (VT.SimpleTy) {
9792 return lowerV2I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9794 return lowerV2F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9796 return lowerV4I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9798 return lowerV4F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9800 return lowerV8I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
9802 return lowerV16I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
9805 llvm_unreachable("Unimplemented!");
9809 /// \brief Helper function to test whether a shuffle mask could be
9810 /// simplified by widening the elements being shuffled.
9812 /// Appends the mask for wider elements in WidenedMask if valid. Otherwise
9813 /// leaves it in an unspecified state.
9815 /// NOTE: This must handle normal vector shuffle masks and *target* vector
9816 /// shuffle masks. The latter have the special property of a '-2' representing
9817 /// a zero-ed lane of a vector.
9818 static bool canWidenShuffleElements(ArrayRef<int> Mask,
9819 SmallVectorImpl<int> &WidenedMask) {
9820 for (int i = 0, Size = Mask.size(); i < Size; i += 2) {
9821 // If both elements are undef, its trivial.
9822 if (Mask[i] == SM_SentinelUndef && Mask[i + 1] == SM_SentinelUndef) {
9823 WidenedMask.push_back(SM_SentinelUndef);
9827 // Check for an undef mask and a mask value properly aligned to fit with
9828 // a pair of values. If we find such a case, use the non-undef mask's value.
9829 if (Mask[i] == SM_SentinelUndef && Mask[i + 1] >= 0 && Mask[i + 1] % 2 == 1) {
9830 WidenedMask.push_back(Mask[i + 1] / 2);
9833 if (Mask[i + 1] == SM_SentinelUndef && Mask[i] >= 0 && Mask[i] % 2 == 0) {
9834 WidenedMask.push_back(Mask[i] / 2);
9838 // When zeroing, we need to spread the zeroing across both lanes to widen.
9839 if (Mask[i] == SM_SentinelZero || Mask[i + 1] == SM_SentinelZero) {
9840 if ((Mask[i] == SM_SentinelZero || Mask[i] == SM_SentinelUndef) &&
9841 (Mask[i + 1] == SM_SentinelZero || Mask[i + 1] == SM_SentinelUndef)) {
9842 WidenedMask.push_back(SM_SentinelZero);
9848 // Finally check if the two mask values are adjacent and aligned with
9850 if (Mask[i] != SM_SentinelUndef && Mask[i] % 2 == 0 && Mask[i] + 1 == Mask[i + 1]) {
9851 WidenedMask.push_back(Mask[i] / 2);
9855 // Otherwise we can't safely widen the elements used in this shuffle.
9858 assert(WidenedMask.size() == Mask.size() / 2 &&
9859 "Incorrect size of mask after widening the elements!");
9864 /// \brief Generic routine to split vector shuffle into half-sized shuffles.
9866 /// This routine just extracts two subvectors, shuffles them independently, and
9867 /// then concatenates them back together. This should work effectively with all
9868 /// AVX vector shuffle types.
9869 static SDValue splitAndLowerVectorShuffle(SDLoc DL, MVT VT, SDValue V1,
9870 SDValue V2, ArrayRef<int> Mask,
9871 SelectionDAG &DAG) {
9872 assert(VT.getSizeInBits() >= 256 &&
9873 "Only for 256-bit or wider vector shuffles!");
9874 assert(V1.getSimpleValueType() == VT && "Bad operand type!");
9875 assert(V2.getSimpleValueType() == VT && "Bad operand type!");
9877 ArrayRef<int> LoMask = Mask.slice(0, Mask.size() / 2);
9878 ArrayRef<int> HiMask = Mask.slice(Mask.size() / 2);
9880 int NumElements = VT.getVectorNumElements();
9881 int SplitNumElements = NumElements / 2;
9882 MVT ScalarVT = VT.getVectorElementType();
9883 MVT SplitVT = MVT::getVectorVT(ScalarVT, NumElements / 2);
9885 // Rather than splitting build-vectors, just build two narrower build
9886 // vectors. This helps shuffling with splats and zeros.
9887 auto SplitVector = [&](SDValue V) {
9888 while (V.getOpcode() == ISD::BITCAST)
9889 V = V->getOperand(0);
9891 MVT OrigVT = V.getSimpleValueType();
9892 int OrigNumElements = OrigVT.getVectorNumElements();
9893 int OrigSplitNumElements = OrigNumElements / 2;
9894 MVT OrigScalarVT = OrigVT.getVectorElementType();
9895 MVT OrigSplitVT = MVT::getVectorVT(OrigScalarVT, OrigNumElements / 2);
9899 auto *BV = dyn_cast<BuildVectorSDNode>(V);
9901 LoV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, OrigSplitVT, V,
9902 DAG.getIntPtrConstant(0, DL));
9903 HiV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, OrigSplitVT, V,
9904 DAG.getIntPtrConstant(OrigSplitNumElements, DL));
9907 SmallVector<SDValue, 16> LoOps, HiOps;
9908 for (int i = 0; i < OrigSplitNumElements; ++i) {
9909 LoOps.push_back(BV->getOperand(i));
9910 HiOps.push_back(BV->getOperand(i + OrigSplitNumElements));
9912 LoV = DAG.getNode(ISD::BUILD_VECTOR, DL, OrigSplitVT, LoOps);
9913 HiV = DAG.getNode(ISD::BUILD_VECTOR, DL, OrigSplitVT, HiOps);
9915 return std::make_pair(DAG.getBitcast(SplitVT, LoV),
9916 DAG.getBitcast(SplitVT, HiV));
9919 SDValue LoV1, HiV1, LoV2, HiV2;
9920 std::tie(LoV1, HiV1) = SplitVector(V1);
9921 std::tie(LoV2, HiV2) = SplitVector(V2);
9923 // Now create two 4-way blends of these half-width vectors.
9924 auto HalfBlend = [&](ArrayRef<int> HalfMask) {
9925 bool UseLoV1 = false, UseHiV1 = false, UseLoV2 = false, UseHiV2 = false;
9926 SmallVector<int, 32> V1BlendMask, V2BlendMask, BlendMask;
9927 for (int i = 0; i < SplitNumElements; ++i) {
9928 int M = HalfMask[i];
9929 if (M >= NumElements) {
9930 if (M >= NumElements + SplitNumElements)
9934 V2BlendMask.push_back(M - NumElements);
9935 V1BlendMask.push_back(-1);
9936 BlendMask.push_back(SplitNumElements + i);
9937 } else if (M >= 0) {
9938 if (M >= SplitNumElements)
9942 V2BlendMask.push_back(-1);
9943 V1BlendMask.push_back(M);
9944 BlendMask.push_back(i);
9946 V2BlendMask.push_back(-1);
9947 V1BlendMask.push_back(-1);
9948 BlendMask.push_back(-1);
9952 // Because the lowering happens after all combining takes place, we need to
9953 // manually combine these blend masks as much as possible so that we create
9954 // a minimal number of high-level vector shuffle nodes.
9956 // First try just blending the halves of V1 or V2.
9957 if (!UseLoV1 && !UseHiV1 && !UseLoV2 && !UseHiV2)
9958 return DAG.getUNDEF(SplitVT);
9959 if (!UseLoV2 && !UseHiV2)
9960 return DAG.getVectorShuffle(SplitVT, DL, LoV1, HiV1, V1BlendMask);
9961 if (!UseLoV1 && !UseHiV1)
9962 return DAG.getVectorShuffle(SplitVT, DL, LoV2, HiV2, V2BlendMask);
9964 SDValue V1Blend, V2Blend;
9965 if (UseLoV1 && UseHiV1) {
9967 DAG.getVectorShuffle(SplitVT, DL, LoV1, HiV1, V1BlendMask);
9969 // We only use half of V1 so map the usage down into the final blend mask.
9970 V1Blend = UseLoV1 ? LoV1 : HiV1;
9971 for (int i = 0; i < SplitNumElements; ++i)
9972 if (BlendMask[i] >= 0 && BlendMask[i] < SplitNumElements)
9973 BlendMask[i] = V1BlendMask[i] - (UseLoV1 ? 0 : SplitNumElements);
9975 if (UseLoV2 && UseHiV2) {
9977 DAG.getVectorShuffle(SplitVT, DL, LoV2, HiV2, V2BlendMask);
9979 // We only use half of V2 so map the usage down into the final blend mask.
9980 V2Blend = UseLoV2 ? LoV2 : HiV2;
9981 for (int i = 0; i < SplitNumElements; ++i)
9982 if (BlendMask[i] >= SplitNumElements)
9983 BlendMask[i] = V2BlendMask[i] + (UseLoV2 ? SplitNumElements : 0);
9985 return DAG.getVectorShuffle(SplitVT, DL, V1Blend, V2Blend, BlendMask);
9987 SDValue Lo = HalfBlend(LoMask);
9988 SDValue Hi = HalfBlend(HiMask);
9989 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Lo, Hi);
9992 /// \brief Either split a vector in halves or decompose the shuffles and the
9995 /// This is provided as a good fallback for many lowerings of non-single-input
9996 /// shuffles with more than one 128-bit lane. In those cases, we want to select
9997 /// between splitting the shuffle into 128-bit components and stitching those
9998 /// back together vs. extracting the single-input shuffles and blending those
10000 static SDValue lowerVectorShuffleAsSplitOrBlend(SDLoc DL, MVT VT, SDValue V1,
10001 SDValue V2, ArrayRef<int> Mask,
10002 SelectionDAG &DAG) {
10003 assert(!isSingleInputShuffleMask(Mask) && "This routine must not be used to "
10004 "lower single-input shuffles as it "
10005 "could then recurse on itself.");
10006 int Size = Mask.size();
10008 // If this can be modeled as a broadcast of two elements followed by a blend,
10009 // prefer that lowering. This is especially important because broadcasts can
10010 // often fold with memory operands.
10011 auto DoBothBroadcast = [&] {
10012 int V1BroadcastIdx = -1, V2BroadcastIdx = -1;
10015 if (V2BroadcastIdx == -1)
10016 V2BroadcastIdx = M - Size;
10017 else if (M - Size != V2BroadcastIdx)
10019 } else if (M >= 0) {
10020 if (V1BroadcastIdx == -1)
10021 V1BroadcastIdx = M;
10022 else if (M != V1BroadcastIdx)
10027 if (DoBothBroadcast())
10028 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask,
10031 // If the inputs all stem from a single 128-bit lane of each input, then we
10032 // split them rather than blending because the split will decompose to
10033 // unusually few instructions.
10034 int LaneCount = VT.getSizeInBits() / 128;
10035 int LaneSize = Size / LaneCount;
10036 SmallBitVector LaneInputs[2];
10037 LaneInputs[0].resize(LaneCount, false);
10038 LaneInputs[1].resize(LaneCount, false);
10039 for (int i = 0; i < Size; ++i)
10041 LaneInputs[Mask[i] / Size][(Mask[i] % Size) / LaneSize] = true;
10042 if (LaneInputs[0].count() <= 1 && LaneInputs[1].count() <= 1)
10043 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
10045 // Otherwise, just fall back to decomposed shuffles and a blend. This requires
10046 // that the decomposed single-input shuffles don't end up here.
10047 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask, DAG);
10050 /// \brief Lower a vector shuffle crossing multiple 128-bit lanes as
10051 /// a permutation and blend of those lanes.
10053 /// This essentially blends the out-of-lane inputs to each lane into the lane
10054 /// from a permuted copy of the vector. This lowering strategy results in four
10055 /// instructions in the worst case for a single-input cross lane shuffle which
10056 /// is lower than any other fully general cross-lane shuffle strategy I'm aware
10057 /// of. Special cases for each particular shuffle pattern should be handled
10058 /// prior to trying this lowering.
10059 static SDValue lowerVectorShuffleAsLanePermuteAndBlend(SDLoc DL, MVT VT,
10060 SDValue V1, SDValue V2,
10061 ArrayRef<int> Mask,
10062 SelectionDAG &DAG) {
10063 // FIXME: This should probably be generalized for 512-bit vectors as well.
10064 assert(VT.is256BitVector() && "Only for 256-bit vector shuffles!");
10065 int LaneSize = Mask.size() / 2;
10067 // If there are only inputs from one 128-bit lane, splitting will in fact be
10068 // less expensive. The flags track whether the given lane contains an element
10069 // that crosses to another lane.
10070 bool LaneCrossing[2] = {false, false};
10071 for (int i = 0, Size = Mask.size(); i < Size; ++i)
10072 if (Mask[i] >= 0 && (Mask[i] % Size) / LaneSize != i / LaneSize)
10073 LaneCrossing[(Mask[i] % Size) / LaneSize] = true;
10074 if (!LaneCrossing[0] || !LaneCrossing[1])
10075 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
10077 if (isSingleInputShuffleMask(Mask)) {
10078 SmallVector<int, 32> FlippedBlendMask;
10079 for (int i = 0, Size = Mask.size(); i < Size; ++i)
10080 FlippedBlendMask.push_back(
10081 Mask[i] < 0 ? -1 : (((Mask[i] % Size) / LaneSize == i / LaneSize)
10083 : Mask[i] % LaneSize +
10084 (i / LaneSize) * LaneSize + Size));
10086 // Flip the vector, and blend the results which should now be in-lane. The
10087 // VPERM2X128 mask uses the low 2 bits for the low source and bits 4 and
10088 // 5 for the high source. The value 3 selects the high half of source 2 and
10089 // the value 2 selects the low half of source 2. We only use source 2 to
10090 // allow folding it into a memory operand.
10091 unsigned PERMMask = 3 | 2 << 4;
10092 SDValue Flipped = DAG.getNode(X86ISD::VPERM2X128, DL, VT, DAG.getUNDEF(VT),
10093 V1, DAG.getConstant(PERMMask, DL, MVT::i8));
10094 return DAG.getVectorShuffle(VT, DL, V1, Flipped, FlippedBlendMask);
10097 // This now reduces to two single-input shuffles of V1 and V2 which at worst
10098 // will be handled by the above logic and a blend of the results, much like
10099 // other patterns in AVX.
10100 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask, DAG);
10103 /// \brief Handle lowering 2-lane 128-bit shuffles.
10104 static SDValue lowerV2X128VectorShuffle(SDLoc DL, MVT VT, SDValue V1,
10105 SDValue V2, ArrayRef<int> Mask,
10106 const X86Subtarget *Subtarget,
10107 SelectionDAG &DAG) {
10108 // TODO: If minimizing size and one of the inputs is a zero vector and the
10109 // the zero vector has only one use, we could use a VPERM2X128 to save the
10110 // instruction bytes needed to explicitly generate the zero vector.
10112 // Blends are faster and handle all the non-lane-crossing cases.
10113 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, VT, V1, V2, Mask,
10117 bool IsV1Zero = ISD::isBuildVectorAllZeros(V1.getNode());
10118 bool IsV2Zero = ISD::isBuildVectorAllZeros(V2.getNode());
10120 // If either input operand is a zero vector, use VPERM2X128 because its mask
10121 // allows us to replace the zero input with an implicit zero.
10122 if (!IsV1Zero && !IsV2Zero) {
10123 // Check for patterns which can be matched with a single insert of a 128-bit
10125 bool OnlyUsesV1 = isShuffleEquivalent(V1, V2, Mask, {0, 1, 0, 1});
10126 if (OnlyUsesV1 || isShuffleEquivalent(V1, V2, Mask, {0, 1, 4, 5})) {
10127 MVT SubVT = MVT::getVectorVT(VT.getVectorElementType(),
10128 VT.getVectorNumElements() / 2);
10129 SDValue LoV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT, V1,
10130 DAG.getIntPtrConstant(0, DL));
10131 SDValue HiV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT,
10132 OnlyUsesV1 ? V1 : V2,
10133 DAG.getIntPtrConstant(0, DL));
10134 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LoV, HiV);
10138 // Otherwise form a 128-bit permutation. After accounting for undefs,
10139 // convert the 64-bit shuffle mask selection values into 128-bit
10140 // selection bits by dividing the indexes by 2 and shifting into positions
10141 // defined by a vperm2*128 instruction's immediate control byte.
10143 // The immediate permute control byte looks like this:
10144 // [1:0] - select 128 bits from sources for low half of destination
10146 // [3] - zero low half of destination
10147 // [5:4] - select 128 bits from sources for high half of destination
10149 // [7] - zero high half of destination
10151 int MaskLO = Mask[0];
10152 if (MaskLO == SM_SentinelUndef)
10153 MaskLO = Mask[1] == SM_SentinelUndef ? 0 : Mask[1];
10155 int MaskHI = Mask[2];
10156 if (MaskHI == SM_SentinelUndef)
10157 MaskHI = Mask[3] == SM_SentinelUndef ? 0 : Mask[3];
10159 unsigned PermMask = MaskLO / 2 | (MaskHI / 2) << 4;
10161 // If either input is a zero vector, replace it with an undef input.
10162 // Shuffle mask values < 4 are selecting elements of V1.
10163 // Shuffle mask values >= 4 are selecting elements of V2.
10164 // Adjust each half of the permute mask by clearing the half that was
10165 // selecting the zero vector and setting the zero mask bit.
10167 V1 = DAG.getUNDEF(VT);
10169 PermMask = (PermMask & 0xf0) | 0x08;
10171 PermMask = (PermMask & 0x0f) | 0x80;
10174 V2 = DAG.getUNDEF(VT);
10176 PermMask = (PermMask & 0xf0) | 0x08;
10178 PermMask = (PermMask & 0x0f) | 0x80;
10181 return DAG.getNode(X86ISD::VPERM2X128, DL, VT, V1, V2,
10182 DAG.getConstant(PermMask, DL, MVT::i8));
10185 /// \brief Lower a vector shuffle by first fixing the 128-bit lanes and then
10186 /// shuffling each lane.
10188 /// This will only succeed when the result of fixing the 128-bit lanes results
10189 /// in a single-input non-lane-crossing shuffle with a repeating shuffle mask in
10190 /// each 128-bit lanes. This handles many cases where we can quickly blend away
10191 /// the lane crosses early and then use simpler shuffles within each lane.
10193 /// FIXME: It might be worthwhile at some point to support this without
10194 /// requiring the 128-bit lane-relative shuffles to be repeating, but currently
10195 /// in x86 only floating point has interesting non-repeating shuffles, and even
10196 /// those are still *marginally* more expensive.
10197 static SDValue lowerVectorShuffleByMerging128BitLanes(
10198 SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
10199 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
10200 assert(!isSingleInputShuffleMask(Mask) &&
10201 "This is only useful with multiple inputs.");
10203 int Size = Mask.size();
10204 int LaneSize = 128 / VT.getScalarSizeInBits();
10205 int NumLanes = Size / LaneSize;
10206 assert(NumLanes > 1 && "Only handles 256-bit and wider shuffles.");
10208 // See if we can build a hypothetical 128-bit lane-fixing shuffle mask. Also
10209 // check whether the in-128-bit lane shuffles share a repeating pattern.
10210 SmallVector<int, 4> Lanes;
10211 Lanes.resize(NumLanes, -1);
10212 SmallVector<int, 4> InLaneMask;
10213 InLaneMask.resize(LaneSize, -1);
10214 for (int i = 0; i < Size; ++i) {
10218 int j = i / LaneSize;
10220 if (Lanes[j] < 0) {
10221 // First entry we've seen for this lane.
10222 Lanes[j] = Mask[i] / LaneSize;
10223 } else if (Lanes[j] != Mask[i] / LaneSize) {
10224 // This doesn't match the lane selected previously!
10228 // Check that within each lane we have a consistent shuffle mask.
10229 int k = i % LaneSize;
10230 if (InLaneMask[k] < 0) {
10231 InLaneMask[k] = Mask[i] % LaneSize;
10232 } else if (InLaneMask[k] != Mask[i] % LaneSize) {
10233 // This doesn't fit a repeating in-lane mask.
10238 // First shuffle the lanes into place.
10239 MVT LaneVT = MVT::getVectorVT(VT.isFloatingPoint() ? MVT::f64 : MVT::i64,
10240 VT.getSizeInBits() / 64);
10241 SmallVector<int, 8> LaneMask;
10242 LaneMask.resize(NumLanes * 2, -1);
10243 for (int i = 0; i < NumLanes; ++i)
10244 if (Lanes[i] >= 0) {
10245 LaneMask[2 * i + 0] = 2*Lanes[i] + 0;
10246 LaneMask[2 * i + 1] = 2*Lanes[i] + 1;
10249 V1 = DAG.getBitcast(LaneVT, V1);
10250 V2 = DAG.getBitcast(LaneVT, V2);
10251 SDValue LaneShuffle = DAG.getVectorShuffle(LaneVT, DL, V1, V2, LaneMask);
10253 // Cast it back to the type we actually want.
10254 LaneShuffle = DAG.getBitcast(VT, LaneShuffle);
10256 // Now do a simple shuffle that isn't lane crossing.
10257 SmallVector<int, 8> NewMask;
10258 NewMask.resize(Size, -1);
10259 for (int i = 0; i < Size; ++i)
10261 NewMask[i] = (i / LaneSize) * LaneSize + Mask[i] % LaneSize;
10262 assert(!is128BitLaneCrossingShuffleMask(VT, NewMask) &&
10263 "Must not introduce lane crosses at this point!");
10265 return DAG.getVectorShuffle(VT, DL, LaneShuffle, DAG.getUNDEF(VT), NewMask);
10268 /// \brief Test whether the specified input (0 or 1) is in-place blended by the
10271 /// This returns true if the elements from a particular input are already in the
10272 /// slot required by the given mask and require no permutation.
10273 static bool isShuffleMaskInputInPlace(int Input, ArrayRef<int> Mask) {
10274 assert((Input == 0 || Input == 1) && "Only two inputs to shuffles.");
10275 int Size = Mask.size();
10276 for (int i = 0; i < Size; ++i)
10277 if (Mask[i] >= 0 && Mask[i] / Size == Input && Mask[i] % Size != i)
10283 static SDValue lowerVectorShuffleWithSHUFPD(SDLoc DL, MVT VT,
10284 ArrayRef<int> Mask, SDValue V1,
10285 SDValue V2, SelectionDAG &DAG) {
10287 // Mask for V8F64: 0/1, 8/9, 2/3, 10/11, 4/5, ..
10288 // Mask for V4F64; 0/1, 4/5, 2/3, 6/7..
10289 assert(VT.getScalarSizeInBits() == 64 && "Unexpected data type for VSHUFPD");
10290 int NumElts = VT.getVectorNumElements();
10291 bool ShufpdMask = true;
10292 bool CommutableMask = true;
10293 unsigned Immediate = 0;
10294 for (int i = 0; i < NumElts; ++i) {
10297 int Val = (i & 6) + NumElts * (i & 1);
10298 int CommutVal = (i & 0xe) + NumElts * ((i & 1)^1);
10299 if (Mask[i] < Val || Mask[i] > Val + 1)
10300 ShufpdMask = false;
10301 if (Mask[i] < CommutVal || Mask[i] > CommutVal + 1)
10302 CommutableMask = false;
10303 Immediate |= (Mask[i] % 2) << i;
10306 return DAG.getNode(X86ISD::SHUFP, DL, VT, V1, V2,
10307 DAG.getConstant(Immediate, DL, MVT::i8));
10308 if (CommutableMask)
10309 return DAG.getNode(X86ISD::SHUFP, DL, VT, V2, V1,
10310 DAG.getConstant(Immediate, DL, MVT::i8));
10314 /// \brief Handle lowering of 4-lane 64-bit floating point shuffles.
10316 /// Also ends up handling lowering of 4-lane 64-bit integer shuffles when AVX2
10317 /// isn't available.
10318 static SDValue lowerV4F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10319 const X86Subtarget *Subtarget,
10320 SelectionDAG &DAG) {
10322 assert(V1.getSimpleValueType() == MVT::v4f64 && "Bad operand type!");
10323 assert(V2.getSimpleValueType() == MVT::v4f64 && "Bad operand type!");
10324 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10325 ArrayRef<int> Mask = SVOp->getMask();
10326 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
10328 SmallVector<int, 4> WidenedMask;
10329 if (canWidenShuffleElements(Mask, WidenedMask))
10330 return lowerV2X128VectorShuffle(DL, MVT::v4f64, V1, V2, Mask, Subtarget,
10333 if (isSingleInputShuffleMask(Mask)) {
10334 // Check for being able to broadcast a single element.
10335 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v4f64, V1,
10336 Mask, Subtarget, DAG))
10339 // Use low duplicate instructions for masks that match their pattern.
10340 if (isShuffleEquivalent(V1, V2, Mask, {0, 0, 2, 2}))
10341 return DAG.getNode(X86ISD::MOVDDUP, DL, MVT::v4f64, V1);
10343 if (!is128BitLaneCrossingShuffleMask(MVT::v4f64, Mask)) {
10344 // Non-half-crossing single input shuffles can be lowerid with an
10345 // interleaved permutation.
10346 unsigned VPERMILPMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1) |
10347 ((Mask[2] == 3) << 2) | ((Mask[3] == 3) << 3);
10348 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v4f64, V1,
10349 DAG.getConstant(VPERMILPMask, DL, MVT::i8));
10352 // With AVX2 we have direct support for this permutation.
10353 if (Subtarget->hasAVX2())
10354 return DAG.getNode(X86ISD::VPERMI, DL, MVT::v4f64, V1,
10355 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
10357 // Otherwise, fall back.
10358 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v4f64, V1, V2, Mask,
10362 // Use dedicated unpack instructions for masks that match their pattern.
10364 lowerVectorShuffleWithUNPCK(DL, MVT::v4f64, Mask, V1, V2, DAG))
10367 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4f64, V1, V2, Mask,
10371 // Check if the blend happens to exactly fit that of SHUFPD.
10373 lowerVectorShuffleWithSHUFPD(DL, MVT::v4f64, Mask, V1, V2, DAG))
10376 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10377 // shuffle. However, if we have AVX2 and either inputs are already in place,
10378 // we will be able to shuffle even across lanes the other input in a single
10379 // instruction so skip this pattern.
10380 if (!(Subtarget->hasAVX2() && (isShuffleMaskInputInPlace(0, Mask) ||
10381 isShuffleMaskInputInPlace(1, Mask))))
10382 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10383 DL, MVT::v4f64, V1, V2, Mask, Subtarget, DAG))
10386 // If we have AVX2 then we always want to lower with a blend because an v4 we
10387 // can fully permute the elements.
10388 if (Subtarget->hasAVX2())
10389 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4f64, V1, V2,
10392 // Otherwise fall back on generic lowering.
10393 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v4f64, V1, V2, Mask, DAG);
10396 /// \brief Handle lowering of 4-lane 64-bit integer shuffles.
10398 /// This routine is only called when we have AVX2 and thus a reasonable
10399 /// instruction set for v4i64 shuffling..
10400 static SDValue lowerV4I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10401 const X86Subtarget *Subtarget,
10402 SelectionDAG &DAG) {
10404 assert(V1.getSimpleValueType() == MVT::v4i64 && "Bad operand type!");
10405 assert(V2.getSimpleValueType() == MVT::v4i64 && "Bad operand type!");
10406 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10407 ArrayRef<int> Mask = SVOp->getMask();
10408 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
10409 assert(Subtarget->hasAVX2() && "We can only lower v4i64 with AVX2!");
10411 SmallVector<int, 4> WidenedMask;
10412 if (canWidenShuffleElements(Mask, WidenedMask))
10413 return lowerV2X128VectorShuffle(DL, MVT::v4i64, V1, V2, Mask, Subtarget,
10416 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4i64, V1, V2, Mask,
10420 // Check for being able to broadcast a single element.
10421 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v4i64, V1,
10422 Mask, Subtarget, DAG))
10425 // When the shuffle is mirrored between the 128-bit lanes of the unit, we can
10426 // use lower latency instructions that will operate on both 128-bit lanes.
10427 SmallVector<int, 2> RepeatedMask;
10428 if (is128BitLaneRepeatedShuffleMask(MVT::v4i64, Mask, RepeatedMask)) {
10429 if (isSingleInputShuffleMask(Mask)) {
10430 int PSHUFDMask[] = {-1, -1, -1, -1};
10431 for (int i = 0; i < 2; ++i)
10432 if (RepeatedMask[i] >= 0) {
10433 PSHUFDMask[2 * i] = 2 * RepeatedMask[i];
10434 PSHUFDMask[2 * i + 1] = 2 * RepeatedMask[i] + 1;
10436 return DAG.getBitcast(
10438 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v8i32,
10439 DAG.getBitcast(MVT::v8i32, V1),
10440 getV4X86ShuffleImm8ForMask(PSHUFDMask, DL, DAG)));
10444 // AVX2 provides a direct instruction for permuting a single input across
10446 if (isSingleInputShuffleMask(Mask))
10447 return DAG.getNode(X86ISD::VPERMI, DL, MVT::v4i64, V1,
10448 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
10450 // Try to use shift instructions.
10451 if (SDValue Shift =
10452 lowerVectorShuffleAsShift(DL, MVT::v4i64, V1, V2, Mask, DAG))
10455 // Use dedicated unpack instructions for masks that match their pattern.
10457 lowerVectorShuffleWithUNPCK(DL, MVT::v4i64, Mask, V1, V2, DAG))
10460 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10461 // shuffle. However, if we have AVX2 and either inputs are already in place,
10462 // we will be able to shuffle even across lanes the other input in a single
10463 // instruction so skip this pattern.
10464 if (!(Subtarget->hasAVX2() && (isShuffleMaskInputInPlace(0, Mask) ||
10465 isShuffleMaskInputInPlace(1, Mask))))
10466 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10467 DL, MVT::v4i64, V1, V2, Mask, Subtarget, DAG))
10470 // Otherwise fall back on generic blend lowering.
10471 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4i64, V1, V2,
10475 /// \brief Handle lowering of 8-lane 32-bit floating point shuffles.
10477 /// Also ends up handling lowering of 8-lane 32-bit integer shuffles when AVX2
10478 /// isn't available.
10479 static SDValue lowerV8F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10480 const X86Subtarget *Subtarget,
10481 SelectionDAG &DAG) {
10483 assert(V1.getSimpleValueType() == MVT::v8f32 && "Bad operand type!");
10484 assert(V2.getSimpleValueType() == MVT::v8f32 && "Bad operand type!");
10485 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10486 ArrayRef<int> Mask = SVOp->getMask();
10487 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10489 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8f32, V1, V2, Mask,
10493 // Check for being able to broadcast a single element.
10494 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v8f32, V1,
10495 Mask, Subtarget, DAG))
10498 // If the shuffle mask is repeated in each 128-bit lane, we have many more
10499 // options to efficiently lower the shuffle.
10500 SmallVector<int, 4> RepeatedMask;
10501 if (is128BitLaneRepeatedShuffleMask(MVT::v8f32, Mask, RepeatedMask)) {
10502 assert(RepeatedMask.size() == 4 &&
10503 "Repeated masks must be half the mask width!");
10505 // Use even/odd duplicate instructions for masks that match their pattern.
10506 if (isShuffleEquivalent(V1, V2, Mask, {0, 0, 2, 2, 4, 4, 6, 6}))
10507 return DAG.getNode(X86ISD::MOVSLDUP, DL, MVT::v8f32, V1);
10508 if (isShuffleEquivalent(V1, V2, Mask, {1, 1, 3, 3, 5, 5, 7, 7}))
10509 return DAG.getNode(X86ISD::MOVSHDUP, DL, MVT::v8f32, V1);
10511 if (isSingleInputShuffleMask(Mask))
10512 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v8f32, V1,
10513 getV4X86ShuffleImm8ForMask(RepeatedMask, DL, DAG));
10515 // Use dedicated unpack instructions for masks that match their pattern.
10517 lowerVectorShuffleWithUNPCK(DL, MVT::v8f32, Mask, V1, V2, DAG))
10520 // Otherwise, fall back to a SHUFPS sequence. Here it is important that we
10521 // have already handled any direct blends. We also need to squash the
10522 // repeated mask into a simulated v4f32 mask.
10523 for (int i = 0; i < 4; ++i)
10524 if (RepeatedMask[i] >= 8)
10525 RepeatedMask[i] -= 4;
10526 return lowerVectorShuffleWithSHUFPS(DL, MVT::v8f32, RepeatedMask, V1, V2, DAG);
10529 // If we have a single input shuffle with different shuffle patterns in the
10530 // two 128-bit lanes use the variable mask to VPERMILPS.
10531 if (isSingleInputShuffleMask(Mask)) {
10532 SDValue VPermMask[8];
10533 for (int i = 0; i < 8; ++i)
10534 VPermMask[i] = Mask[i] < 0 ? DAG.getUNDEF(MVT::i32)
10535 : DAG.getConstant(Mask[i], DL, MVT::i32);
10536 if (!is128BitLaneCrossingShuffleMask(MVT::v8f32, Mask))
10537 return DAG.getNode(
10538 X86ISD::VPERMILPV, DL, MVT::v8f32, V1,
10539 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i32, VPermMask));
10541 if (Subtarget->hasAVX2())
10542 return DAG.getNode(
10543 X86ISD::VPERMV, DL, MVT::v8f32,
10544 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i32, VPermMask), V1);
10546 // Otherwise, fall back.
10547 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v8f32, V1, V2, Mask,
10551 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10553 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10554 DL, MVT::v8f32, V1, V2, Mask, Subtarget, DAG))
10557 // If we have AVX2 then we always want to lower with a blend because at v8 we
10558 // can fully permute the elements.
10559 if (Subtarget->hasAVX2())
10560 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8f32, V1, V2,
10563 // Otherwise fall back on generic lowering.
10564 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v8f32, V1, V2, Mask, DAG);
10567 /// \brief Handle lowering of 8-lane 32-bit integer shuffles.
10569 /// This routine is only called when we have AVX2 and thus a reasonable
10570 /// instruction set for v8i32 shuffling..
10571 static SDValue lowerV8I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10572 const X86Subtarget *Subtarget,
10573 SelectionDAG &DAG) {
10575 assert(V1.getSimpleValueType() == MVT::v8i32 && "Bad operand type!");
10576 assert(V2.getSimpleValueType() == MVT::v8i32 && "Bad operand type!");
10577 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10578 ArrayRef<int> Mask = SVOp->getMask();
10579 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10580 assert(Subtarget->hasAVX2() && "We can only lower v8i32 with AVX2!");
10582 // Whenever we can lower this as a zext, that instruction is strictly faster
10583 // than any alternative. It also allows us to fold memory operands into the
10584 // shuffle in many cases.
10585 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v8i32, V1, V2,
10586 Mask, Subtarget, DAG))
10589 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8i32, V1, V2, Mask,
10593 // Check for being able to broadcast a single element.
10594 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v8i32, V1,
10595 Mask, Subtarget, DAG))
10598 // If the shuffle mask is repeated in each 128-bit lane we can use more
10599 // efficient instructions that mirror the shuffles across the two 128-bit
10601 SmallVector<int, 4> RepeatedMask;
10602 if (is128BitLaneRepeatedShuffleMask(MVT::v8i32, Mask, RepeatedMask)) {
10603 assert(RepeatedMask.size() == 4 && "Unexpected repeated mask size!");
10604 if (isSingleInputShuffleMask(Mask))
10605 return DAG.getNode(X86ISD::PSHUFD, DL, MVT::v8i32, V1,
10606 getV4X86ShuffleImm8ForMask(RepeatedMask, DL, DAG));
10608 // Use dedicated unpack instructions for masks that match their pattern.
10610 lowerVectorShuffleWithUNPCK(DL, MVT::v8i32, Mask, V1, V2, DAG))
10614 // Try to use shift instructions.
10615 if (SDValue Shift =
10616 lowerVectorShuffleAsShift(DL, MVT::v8i32, V1, V2, Mask, DAG))
10619 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
10620 DL, MVT::v8i32, V1, V2, Mask, Subtarget, DAG))
10623 // If the shuffle patterns aren't repeated but it is a single input, directly
10624 // generate a cross-lane VPERMD instruction.
10625 if (isSingleInputShuffleMask(Mask)) {
10626 SDValue VPermMask[8];
10627 for (int i = 0; i < 8; ++i)
10628 VPermMask[i] = Mask[i] < 0 ? DAG.getUNDEF(MVT::i32)
10629 : DAG.getConstant(Mask[i], DL, MVT::i32);
10630 return DAG.getNode(
10631 X86ISD::VPERMV, DL, MVT::v8i32,
10632 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i32, VPermMask), V1);
10635 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10637 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10638 DL, MVT::v8i32, V1, V2, Mask, Subtarget, DAG))
10641 // Otherwise fall back on generic blend lowering.
10642 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8i32, V1, V2,
10646 /// \brief Handle lowering of 16-lane 16-bit integer shuffles.
10648 /// This routine is only called when we have AVX2 and thus a reasonable
10649 /// instruction set for v16i16 shuffling..
10650 static SDValue lowerV16I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10651 const X86Subtarget *Subtarget,
10652 SelectionDAG &DAG) {
10654 assert(V1.getSimpleValueType() == MVT::v16i16 && "Bad operand type!");
10655 assert(V2.getSimpleValueType() == MVT::v16i16 && "Bad operand type!");
10656 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10657 ArrayRef<int> Mask = SVOp->getMask();
10658 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
10659 assert(Subtarget->hasAVX2() && "We can only lower v16i16 with AVX2!");
10661 // Whenever we can lower this as a zext, that instruction is strictly faster
10662 // than any alternative. It also allows us to fold memory operands into the
10663 // shuffle in many cases.
10664 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v16i16, V1, V2,
10665 Mask, Subtarget, DAG))
10668 // Check for being able to broadcast a single element.
10669 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v16i16, V1,
10670 Mask, Subtarget, DAG))
10673 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v16i16, V1, V2, Mask,
10677 // Use dedicated unpack instructions for masks that match their pattern.
10679 lowerVectorShuffleWithUNPCK(DL, MVT::v16i16, Mask, V1, V2, DAG))
10682 // Try to use shift instructions.
10683 if (SDValue Shift =
10684 lowerVectorShuffleAsShift(DL, MVT::v16i16, V1, V2, Mask, DAG))
10687 // Try to use byte rotation instructions.
10688 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
10689 DL, MVT::v16i16, V1, V2, Mask, Subtarget, DAG))
10692 if (isSingleInputShuffleMask(Mask)) {
10693 // There are no generalized cross-lane shuffle operations available on i16
10695 if (is128BitLaneCrossingShuffleMask(MVT::v16i16, Mask))
10696 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v16i16, V1, V2,
10699 SmallVector<int, 8> RepeatedMask;
10700 if (is128BitLaneRepeatedShuffleMask(MVT::v16i16, Mask, RepeatedMask)) {
10701 // As this is a single-input shuffle, the repeated mask should be
10702 // a strictly valid v8i16 mask that we can pass through to the v8i16
10703 // lowering to handle even the v16 case.
10704 return lowerV8I16GeneralSingleInputVectorShuffle(
10705 DL, MVT::v16i16, V1, RepeatedMask, Subtarget, DAG);
10708 SDValue PSHUFBMask[32];
10709 for (int i = 0; i < 16; ++i) {
10710 if (Mask[i] == -1) {
10711 PSHUFBMask[2 * i] = PSHUFBMask[2 * i + 1] = DAG.getUNDEF(MVT::i8);
10715 int M = i < 8 ? Mask[i] : Mask[i] - 8;
10716 assert(M >= 0 && M < 8 && "Invalid single-input mask!");
10717 PSHUFBMask[2 * i] = DAG.getConstant(2 * M, DL, MVT::i8);
10718 PSHUFBMask[2 * i + 1] = DAG.getConstant(2 * M + 1, DL, MVT::i8);
10720 return DAG.getBitcast(MVT::v16i16,
10721 DAG.getNode(X86ISD::PSHUFB, DL, MVT::v32i8,
10722 DAG.getBitcast(MVT::v32i8, V1),
10723 DAG.getNode(ISD::BUILD_VECTOR, DL,
10724 MVT::v32i8, PSHUFBMask)));
10727 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10729 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10730 DL, MVT::v16i16, V1, V2, Mask, Subtarget, DAG))
10733 // Otherwise fall back on generic lowering.
10734 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v16i16, V1, V2, Mask, DAG);
10737 /// \brief Handle lowering of 32-lane 8-bit integer shuffles.
10739 /// This routine is only called when we have AVX2 and thus a reasonable
10740 /// instruction set for v32i8 shuffling..
10741 static SDValue lowerV32I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10742 const X86Subtarget *Subtarget,
10743 SelectionDAG &DAG) {
10745 assert(V1.getSimpleValueType() == MVT::v32i8 && "Bad operand type!");
10746 assert(V2.getSimpleValueType() == MVT::v32i8 && "Bad operand type!");
10747 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10748 ArrayRef<int> Mask = SVOp->getMask();
10749 assert(Mask.size() == 32 && "Unexpected mask size for v32 shuffle!");
10750 assert(Subtarget->hasAVX2() && "We can only lower v32i8 with AVX2!");
10752 // Whenever we can lower this as a zext, that instruction is strictly faster
10753 // than any alternative. It also allows us to fold memory operands into the
10754 // shuffle in many cases.
10755 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v32i8, V1, V2,
10756 Mask, Subtarget, DAG))
10759 // Check for being able to broadcast a single element.
10760 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v32i8, V1,
10761 Mask, Subtarget, DAG))
10764 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v32i8, V1, V2, Mask,
10768 // Use dedicated unpack instructions for masks that match their pattern.
10770 lowerVectorShuffleWithUNPCK(DL, MVT::v32i8, Mask, V1, V2, DAG))
10773 // Try to use shift instructions.
10774 if (SDValue Shift =
10775 lowerVectorShuffleAsShift(DL, MVT::v32i8, V1, V2, Mask, DAG))
10778 // Try to use byte rotation instructions.
10779 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
10780 DL, MVT::v32i8, V1, V2, Mask, Subtarget, DAG))
10783 if (isSingleInputShuffleMask(Mask)) {
10784 // There are no generalized cross-lane shuffle operations available on i8
10786 if (is128BitLaneCrossingShuffleMask(MVT::v32i8, Mask))
10787 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v32i8, V1, V2,
10790 SDValue PSHUFBMask[32];
10791 for (int i = 0; i < 32; ++i)
10794 ? DAG.getUNDEF(MVT::i8)
10795 : DAG.getConstant(Mask[i] < 16 ? Mask[i] : Mask[i] - 16, DL,
10798 return DAG.getNode(
10799 X86ISD::PSHUFB, DL, MVT::v32i8, V1,
10800 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, PSHUFBMask));
10803 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10805 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10806 DL, MVT::v32i8, V1, V2, Mask, Subtarget, DAG))
10809 // Otherwise fall back on generic lowering.
10810 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v32i8, V1, V2, Mask, DAG);
10813 /// \brief High-level routine to lower various 256-bit x86 vector shuffles.
10815 /// This routine either breaks down the specific type of a 256-bit x86 vector
10816 /// shuffle or splits it into two 128-bit shuffles and fuses the results back
10817 /// together based on the available instructions.
10818 static SDValue lower256BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10819 MVT VT, const X86Subtarget *Subtarget,
10820 SelectionDAG &DAG) {
10822 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10823 ArrayRef<int> Mask = SVOp->getMask();
10825 // If we have a single input to the zero element, insert that into V1 if we
10826 // can do so cheaply.
10827 int NumElts = VT.getVectorNumElements();
10828 int NumV2Elements = std::count_if(Mask.begin(), Mask.end(), [NumElts](int M) {
10829 return M >= NumElts;
10832 if (NumV2Elements == 1 && Mask[0] >= NumElts)
10833 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
10834 DL, VT, V1, V2, Mask, Subtarget, DAG))
10837 // There is a really nice hard cut-over between AVX1 and AVX2 that means we
10838 // can check for those subtargets here and avoid much of the subtarget
10839 // querying in the per-vector-type lowering routines. With AVX1 we have
10840 // essentially *zero* ability to manipulate a 256-bit vector with integer
10841 // types. Since we'll use floating point types there eventually, just
10842 // immediately cast everything to a float and operate entirely in that domain.
10843 if (VT.isInteger() && !Subtarget->hasAVX2()) {
10844 int ElementBits = VT.getScalarSizeInBits();
10845 if (ElementBits < 32)
10846 // No floating point type available, decompose into 128-bit vectors.
10847 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
10849 MVT FpVT = MVT::getVectorVT(MVT::getFloatingPointVT(ElementBits),
10850 VT.getVectorNumElements());
10851 V1 = DAG.getBitcast(FpVT, V1);
10852 V2 = DAG.getBitcast(FpVT, V2);
10853 return DAG.getBitcast(VT, DAG.getVectorShuffle(FpVT, DL, V1, V2, Mask));
10856 switch (VT.SimpleTy) {
10858 return lowerV4F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10860 return lowerV4I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10862 return lowerV8F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10864 return lowerV8I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10866 return lowerV16I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
10868 return lowerV32I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
10871 llvm_unreachable("Not a valid 256-bit x86 vector type!");
10875 /// \brief Try to lower a vector shuffle as a 128-bit shuffles.
10876 static SDValue lowerV4X128VectorShuffle(SDLoc DL, MVT VT,
10877 ArrayRef<int> Mask,
10878 SDValue V1, SDValue V2,
10879 SelectionDAG &DAG) {
10880 assert(VT.getScalarSizeInBits() == 64 &&
10881 "Unexpected element type size for 128bit shuffle.");
10883 // To handle 256 bit vector requires VLX and most probably
10884 // function lowerV2X128VectorShuffle() is better solution.
10885 assert(VT.is512BitVector() && "Unexpected vector size for 128bit shuffle.");
10887 SmallVector<int, 4> WidenedMask;
10888 if (!canWidenShuffleElements(Mask, WidenedMask))
10891 // Form a 128-bit permutation.
10892 // Convert the 64-bit shuffle mask selection values into 128-bit selection
10893 // bits defined by a vshuf64x2 instruction's immediate control byte.
10894 unsigned PermMask = 0, Imm = 0;
10895 unsigned ControlBitsNum = WidenedMask.size() / 2;
10897 for (int i = 0, Size = WidenedMask.size(); i < Size; ++i) {
10898 if (WidenedMask[i] == SM_SentinelZero)
10901 // Use first element in place of undef mask.
10902 Imm = (WidenedMask[i] == SM_SentinelUndef) ? 0 : WidenedMask[i];
10903 PermMask |= (Imm % WidenedMask.size()) << (i * ControlBitsNum);
10906 return DAG.getNode(X86ISD::SHUF128, DL, VT, V1, V2,
10907 DAG.getConstant(PermMask, DL, MVT::i8));
10910 static SDValue lowerVectorShuffleWithPERMV(SDLoc DL, MVT VT,
10911 ArrayRef<int> Mask, SDValue V1,
10912 SDValue V2, SelectionDAG &DAG) {
10914 assert(VT.getScalarSizeInBits() >= 16 && "Unexpected data type for PERMV");
10916 MVT MaskEltVT = MVT::getIntegerVT(VT.getScalarSizeInBits());
10917 MVT MaskVecVT = MVT::getVectorVT(MaskEltVT, VT.getVectorNumElements());
10919 SDValue MaskNode = getConstVector(Mask, MaskVecVT, DAG, DL, true);
10920 if (isSingleInputShuffleMask(Mask))
10921 return DAG.getNode(X86ISD::VPERMV, DL, VT, MaskNode, V1);
10923 return DAG.getNode(X86ISD::VPERMV3, DL, VT, V1, MaskNode, V2);
10926 /// \brief Handle lowering of 8-lane 64-bit floating point shuffles.
10927 static SDValue lowerV8F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10928 const X86Subtarget *Subtarget,
10929 SelectionDAG &DAG) {
10931 assert(V1.getSimpleValueType() == MVT::v8f64 && "Bad operand type!");
10932 assert(V2.getSimpleValueType() == MVT::v8f64 && "Bad operand type!");
10933 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10934 ArrayRef<int> Mask = SVOp->getMask();
10935 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10937 if (SDValue Shuf128 =
10938 lowerV4X128VectorShuffle(DL, MVT::v8f64, Mask, V1, V2, DAG))
10941 if (SDValue Unpck =
10942 lowerVectorShuffleWithUNPCK(DL, MVT::v8f64, Mask, V1, V2, DAG))
10945 return lowerVectorShuffleWithPERMV(DL, MVT::v8f64, Mask, V1, V2, DAG);
10948 /// \brief Handle lowering of 16-lane 32-bit floating point shuffles.
10949 static SDValue lowerV16F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10950 const X86Subtarget *Subtarget,
10951 SelectionDAG &DAG) {
10953 assert(V1.getSimpleValueType() == MVT::v16f32 && "Bad operand type!");
10954 assert(V2.getSimpleValueType() == MVT::v16f32 && "Bad operand type!");
10955 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10956 ArrayRef<int> Mask = SVOp->getMask();
10957 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
10959 if (SDValue Unpck =
10960 lowerVectorShuffleWithUNPCK(DL, MVT::v16f32, Mask, V1, V2, DAG))
10963 return lowerVectorShuffleWithPERMV(DL, MVT::v16f32, Mask, V1, V2, DAG);
10966 /// \brief Handle lowering of 8-lane 64-bit integer shuffles.
10967 static SDValue lowerV8I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10968 const X86Subtarget *Subtarget,
10969 SelectionDAG &DAG) {
10971 assert(V1.getSimpleValueType() == MVT::v8i64 && "Bad operand type!");
10972 assert(V2.getSimpleValueType() == MVT::v8i64 && "Bad operand type!");
10973 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10974 ArrayRef<int> Mask = SVOp->getMask();
10975 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10977 if (SDValue Shuf128 =
10978 lowerV4X128VectorShuffle(DL, MVT::v8i64, Mask, V1, V2, DAG))
10981 if (SDValue Unpck =
10982 lowerVectorShuffleWithUNPCK(DL, MVT::v8i64, Mask, V1, V2, DAG))
10985 return lowerVectorShuffleWithPERMV(DL, MVT::v8i64, Mask, V1, V2, DAG);
10988 /// \brief Handle lowering of 16-lane 32-bit integer shuffles.
10989 static SDValue lowerV16I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10990 const X86Subtarget *Subtarget,
10991 SelectionDAG &DAG) {
10993 assert(V1.getSimpleValueType() == MVT::v16i32 && "Bad operand type!");
10994 assert(V2.getSimpleValueType() == MVT::v16i32 && "Bad operand type!");
10995 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10996 ArrayRef<int> Mask = SVOp->getMask();
10997 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
10999 if (SDValue Unpck =
11000 lowerVectorShuffleWithUNPCK(DL, MVT::v16i32, Mask, V1, V2, DAG))
11003 return lowerVectorShuffleWithPERMV(DL, MVT::v16i32, Mask, V1, V2, DAG);
11006 /// \brief Handle lowering of 32-lane 16-bit integer shuffles.
11007 static SDValue lowerV32I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
11008 const X86Subtarget *Subtarget,
11009 SelectionDAG &DAG) {
11011 assert(V1.getSimpleValueType() == MVT::v32i16 && "Bad operand type!");
11012 assert(V2.getSimpleValueType() == MVT::v32i16 && "Bad operand type!");
11013 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11014 ArrayRef<int> Mask = SVOp->getMask();
11015 assert(Mask.size() == 32 && "Unexpected mask size for v32 shuffle!");
11016 assert(Subtarget->hasBWI() && "We can only lower v32i16 with AVX-512-BWI!");
11018 return lowerVectorShuffleWithPERMV(DL, MVT::v32i16, Mask, V1, V2, DAG);
11021 /// \brief Handle lowering of 64-lane 8-bit integer shuffles.
11022 static SDValue lowerV64I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
11023 const X86Subtarget *Subtarget,
11024 SelectionDAG &DAG) {
11026 assert(V1.getSimpleValueType() == MVT::v64i8 && "Bad operand type!");
11027 assert(V2.getSimpleValueType() == MVT::v64i8 && "Bad operand type!");
11028 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11029 ArrayRef<int> Mask = SVOp->getMask();
11030 assert(Mask.size() == 64 && "Unexpected mask size for v64 shuffle!");
11031 assert(Subtarget->hasBWI() && "We can only lower v64i8 with AVX-512-BWI!");
11033 // FIXME: Implement direct support for this type!
11034 return splitAndLowerVectorShuffle(DL, MVT::v64i8, V1, V2, Mask, DAG);
11037 /// \brief High-level routine to lower various 512-bit x86 vector shuffles.
11039 /// This routine either breaks down the specific type of a 512-bit x86 vector
11040 /// shuffle or splits it into two 256-bit shuffles and fuses the results back
11041 /// together based on the available instructions.
11042 static SDValue lower512BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
11043 MVT VT, const X86Subtarget *Subtarget,
11044 SelectionDAG &DAG) {
11046 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11047 ArrayRef<int> Mask = SVOp->getMask();
11048 assert(Subtarget->hasAVX512() &&
11049 "Cannot lower 512-bit vectors w/ basic ISA!");
11051 // Check for being able to broadcast a single element.
11052 if (SDValue Broadcast =
11053 lowerVectorShuffleAsBroadcast(DL, VT, V1, Mask, Subtarget, DAG))
11056 // Dispatch to each element type for lowering. If we don't have supprot for
11057 // specific element type shuffles at 512 bits, immediately split them and
11058 // lower them. Each lowering routine of a given type is allowed to assume that
11059 // the requisite ISA extensions for that element type are available.
11060 switch (VT.SimpleTy) {
11062 return lowerV8F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
11064 return lowerV16F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
11066 return lowerV8I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
11068 return lowerV16I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
11070 if (Subtarget->hasBWI())
11071 return lowerV32I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
11074 if (Subtarget->hasBWI())
11075 return lowerV64I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
11079 llvm_unreachable("Not a valid 512-bit x86 vector type!");
11082 // Otherwise fall back on splitting.
11083 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
11086 // Lower vXi1 vector shuffles.
11087 // There is no a dedicated instruction on AVX-512 that shuffles the masks.
11088 // The only way to shuffle bits is to sign-extend the mask vector to SIMD
11089 // vector, shuffle and then truncate it back.
11090 static SDValue lower1BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
11091 MVT VT, const X86Subtarget *Subtarget,
11092 SelectionDAG &DAG) {
11094 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11095 ArrayRef<int> Mask = SVOp->getMask();
11096 assert(Subtarget->hasAVX512() &&
11097 "Cannot lower 512-bit vectors w/o basic ISA!");
11099 switch (VT.SimpleTy) {
11101 llvm_unreachable("Expected a vector of i1 elements");
11103 ExtVT = MVT::v2i64;
11106 ExtVT = MVT::v4i32;
11109 ExtVT = MVT::v8i64; // Take 512-bit type, more shuffles on KNL
11112 ExtVT = MVT::v16i32;
11115 ExtVT = MVT::v32i16;
11118 ExtVT = MVT::v64i8;
11122 if (ISD::isBuildVectorAllZeros(V1.getNode()))
11123 V1 = getZeroVector(ExtVT, Subtarget, DAG, DL);
11124 else if (ISD::isBuildVectorAllOnes(V1.getNode()))
11125 V1 = getOnesVector(ExtVT, Subtarget, DAG, DL);
11127 V1 = DAG.getNode(ISD::SIGN_EXTEND, DL, ExtVT, V1);
11130 V2 = DAG.getUNDEF(ExtVT);
11131 else if (ISD::isBuildVectorAllZeros(V2.getNode()))
11132 V2 = getZeroVector(ExtVT, Subtarget, DAG, DL);
11133 else if (ISD::isBuildVectorAllOnes(V2.getNode()))
11134 V2 = getOnesVector(ExtVT, Subtarget, DAG, DL);
11136 V2 = DAG.getNode(ISD::SIGN_EXTEND, DL, ExtVT, V2);
11137 return DAG.getNode(ISD::TRUNCATE, DL, VT,
11138 DAG.getVectorShuffle(ExtVT, DL, V1, V2, Mask));
11140 /// \brief Top-level lowering for x86 vector shuffles.
11142 /// This handles decomposition, canonicalization, and lowering of all x86
11143 /// vector shuffles. Most of the specific lowering strategies are encapsulated
11144 /// above in helper routines. The canonicalization attempts to widen shuffles
11145 /// to involve fewer lanes of wider elements, consolidate symmetric patterns
11146 /// s.t. only one of the two inputs needs to be tested, etc.
11147 static SDValue lowerVectorShuffle(SDValue Op, const X86Subtarget *Subtarget,
11148 SelectionDAG &DAG) {
11149 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11150 ArrayRef<int> Mask = SVOp->getMask();
11151 SDValue V1 = Op.getOperand(0);
11152 SDValue V2 = Op.getOperand(1);
11153 MVT VT = Op.getSimpleValueType();
11154 int NumElements = VT.getVectorNumElements();
11156 bool Is1BitVector = (VT.getVectorElementType() == MVT::i1);
11158 assert((VT.getSizeInBits() != 64 || Is1BitVector) &&
11159 "Can't lower MMX shuffles");
11161 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
11162 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
11163 if (V1IsUndef && V2IsUndef)
11164 return DAG.getUNDEF(VT);
11166 // When we create a shuffle node we put the UNDEF node to second operand,
11167 // but in some cases the first operand may be transformed to UNDEF.
11168 // In this case we should just commute the node.
11170 return DAG.getCommutedVectorShuffle(*SVOp);
11172 // Check for non-undef masks pointing at an undef vector and make the masks
11173 // undef as well. This makes it easier to match the shuffle based solely on
11177 if (M >= NumElements) {
11178 SmallVector<int, 8> NewMask(Mask.begin(), Mask.end());
11179 for (int &M : NewMask)
11180 if (M >= NumElements)
11182 return DAG.getVectorShuffle(VT, dl, V1, V2, NewMask);
11185 // We actually see shuffles that are entirely re-arrangements of a set of
11186 // zero inputs. This mostly happens while decomposing complex shuffles into
11187 // simple ones. Directly lower these as a buildvector of zeros.
11188 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
11189 if (Zeroable.all())
11190 return getZeroVector(VT, Subtarget, DAG, dl);
11192 // Try to collapse shuffles into using a vector type with fewer elements but
11193 // wider element types. We cap this to not form integers or floating point
11194 // elements wider than 64 bits, but it might be interesting to form i128
11195 // integers to handle flipping the low and high halves of AVX 256-bit vectors.
11196 SmallVector<int, 16> WidenedMask;
11197 if (VT.getScalarSizeInBits() < 64 && !Is1BitVector &&
11198 canWidenShuffleElements(Mask, WidenedMask)) {
11199 MVT NewEltVT = VT.isFloatingPoint()
11200 ? MVT::getFloatingPointVT(VT.getScalarSizeInBits() * 2)
11201 : MVT::getIntegerVT(VT.getScalarSizeInBits() * 2);
11202 MVT NewVT = MVT::getVectorVT(NewEltVT, VT.getVectorNumElements() / 2);
11203 // Make sure that the new vector type is legal. For example, v2f64 isn't
11205 if (DAG.getTargetLoweringInfo().isTypeLegal(NewVT)) {
11206 V1 = DAG.getBitcast(NewVT, V1);
11207 V2 = DAG.getBitcast(NewVT, V2);
11208 return DAG.getBitcast(
11209 VT, DAG.getVectorShuffle(NewVT, dl, V1, V2, WidenedMask));
11213 int NumV1Elements = 0, NumUndefElements = 0, NumV2Elements = 0;
11214 for (int M : SVOp->getMask())
11216 ++NumUndefElements;
11217 else if (M < NumElements)
11222 // Commute the shuffle as needed such that more elements come from V1 than
11223 // V2. This allows us to match the shuffle pattern strictly on how many
11224 // elements come from V1 without handling the symmetric cases.
11225 if (NumV2Elements > NumV1Elements)
11226 return DAG.getCommutedVectorShuffle(*SVOp);
11228 // When the number of V1 and V2 elements are the same, try to minimize the
11229 // number of uses of V2 in the low half of the vector. When that is tied,
11230 // ensure that the sum of indices for V1 is equal to or lower than the sum
11231 // indices for V2. When those are equal, try to ensure that the number of odd
11232 // indices for V1 is lower than the number of odd indices for V2.
11233 if (NumV1Elements == NumV2Elements) {
11234 int LowV1Elements = 0, LowV2Elements = 0;
11235 for (int M : SVOp->getMask().slice(0, NumElements / 2))
11236 if (M >= NumElements)
11240 if (LowV2Elements > LowV1Elements) {
11241 return DAG.getCommutedVectorShuffle(*SVOp);
11242 } else if (LowV2Elements == LowV1Elements) {
11243 int SumV1Indices = 0, SumV2Indices = 0;
11244 for (int i = 0, Size = SVOp->getMask().size(); i < Size; ++i)
11245 if (SVOp->getMask()[i] >= NumElements)
11247 else if (SVOp->getMask()[i] >= 0)
11249 if (SumV2Indices < SumV1Indices) {
11250 return DAG.getCommutedVectorShuffle(*SVOp);
11251 } else if (SumV2Indices == SumV1Indices) {
11252 int NumV1OddIndices = 0, NumV2OddIndices = 0;
11253 for (int i = 0, Size = SVOp->getMask().size(); i < Size; ++i)
11254 if (SVOp->getMask()[i] >= NumElements)
11255 NumV2OddIndices += i % 2;
11256 else if (SVOp->getMask()[i] >= 0)
11257 NumV1OddIndices += i % 2;
11258 if (NumV2OddIndices < NumV1OddIndices)
11259 return DAG.getCommutedVectorShuffle(*SVOp);
11264 // For each vector width, delegate to a specialized lowering routine.
11265 if (VT.is128BitVector())
11266 return lower128BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
11268 if (VT.is256BitVector())
11269 return lower256BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
11271 if (VT.is512BitVector())
11272 return lower512BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
11275 return lower1BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
11276 llvm_unreachable("Unimplemented!");
11279 // This function assumes its argument is a BUILD_VECTOR of constants or
11280 // undef SDNodes. i.e: ISD::isBuildVectorOfConstantSDNodes(BuildVector) is
11282 static bool BUILD_VECTORtoBlendMask(BuildVectorSDNode *BuildVector,
11283 unsigned &MaskValue) {
11285 unsigned NumElems = BuildVector->getNumOperands();
11287 // There are 2 lanes if (NumElems > 8), and 1 lane otherwise.
11288 // We don't handle the >2 lanes case right now.
11289 unsigned NumLanes = (NumElems - 1) / 8 + 1;
11293 unsigned NumElemsInLane = NumElems / NumLanes;
11295 // Blend for v16i16 should be symmetric for the both lanes.
11296 for (unsigned i = 0; i < NumElemsInLane; ++i) {
11297 SDValue EltCond = BuildVector->getOperand(i);
11298 SDValue SndLaneEltCond =
11299 (NumLanes == 2) ? BuildVector->getOperand(i + NumElemsInLane) : EltCond;
11301 int Lane1Cond = -1, Lane2Cond = -1;
11302 if (isa<ConstantSDNode>(EltCond))
11303 Lane1Cond = !isNullConstant(EltCond);
11304 if (isa<ConstantSDNode>(SndLaneEltCond))
11305 Lane2Cond = !isNullConstant(SndLaneEltCond);
11307 unsigned LaneMask = 0;
11308 if (Lane1Cond == Lane2Cond || Lane2Cond < 0)
11309 // Lane1Cond != 0, means we want the first argument.
11310 // Lane1Cond == 0, means we want the second argument.
11311 // The encoding of this argument is 0 for the first argument, 1
11312 // for the second. Therefore, invert the condition.
11313 LaneMask = !Lane1Cond << i;
11314 else if (Lane1Cond < 0)
11315 LaneMask = !Lane2Cond << i;
11319 MaskValue |= LaneMask;
11321 MaskValue |= LaneMask << NumElemsInLane;
11326 /// \brief Try to lower a VSELECT instruction to a vector shuffle.
11327 static SDValue lowerVSELECTtoVectorShuffle(SDValue Op,
11328 const X86Subtarget *Subtarget,
11329 SelectionDAG &DAG) {
11330 SDValue Cond = Op.getOperand(0);
11331 SDValue LHS = Op.getOperand(1);
11332 SDValue RHS = Op.getOperand(2);
11334 MVT VT = Op.getSimpleValueType();
11336 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
11338 auto *CondBV = cast<BuildVectorSDNode>(Cond);
11340 // Only non-legal VSELECTs reach this lowering, convert those into generic
11341 // shuffles and re-use the shuffle lowering path for blends.
11342 SmallVector<int, 32> Mask;
11343 for (int i = 0, Size = VT.getVectorNumElements(); i < Size; ++i) {
11344 SDValue CondElt = CondBV->getOperand(i);
11346 isa<ConstantSDNode>(CondElt) ? i + (isNullConstant(CondElt) ? Size : 0)
11349 return DAG.getVectorShuffle(VT, dl, LHS, RHS, Mask);
11352 SDValue X86TargetLowering::LowerVSELECT(SDValue Op, SelectionDAG &DAG) const {
11353 // A vselect where all conditions and data are constants can be optimized into
11354 // a single vector load by SelectionDAGLegalize::ExpandBUILD_VECTOR().
11355 if (ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(0).getNode()) &&
11356 ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(1).getNode()) &&
11357 ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(2).getNode()))
11360 // Try to lower this to a blend-style vector shuffle. This can handle all
11361 // constant condition cases.
11362 if (SDValue BlendOp = lowerVSELECTtoVectorShuffle(Op, Subtarget, DAG))
11365 // Variable blends are only legal from SSE4.1 onward.
11366 if (!Subtarget->hasSSE41())
11369 // Only some types will be legal on some subtargets. If we can emit a legal
11370 // VSELECT-matching blend, return Op, and but if we need to expand, return
11372 switch (Op.getSimpleValueType().SimpleTy) {
11374 // Most of the vector types have blends past SSE4.1.
11378 // The byte blends for AVX vectors were introduced only in AVX2.
11379 if (Subtarget->hasAVX2())
11386 // AVX-512 BWI and VLX features support VSELECT with i16 elements.
11387 if (Subtarget->hasBWI() && Subtarget->hasVLX())
11390 // FIXME: We should custom lower this by fixing the condition and using i8
11396 static SDValue LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) {
11397 MVT VT = Op.getSimpleValueType();
11400 if (!Op.getOperand(0).getSimpleValueType().is128BitVector())
11403 if (VT.getSizeInBits() == 8) {
11404 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
11405 Op.getOperand(0), Op.getOperand(1));
11406 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
11407 DAG.getValueType(VT));
11408 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
11411 if (VT.getSizeInBits() == 16) {
11412 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
11413 if (isNullConstant(Op.getOperand(1)))
11414 return DAG.getNode(
11415 ISD::TRUNCATE, dl, MVT::i16,
11416 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
11417 DAG.getBitcast(MVT::v4i32, Op.getOperand(0)),
11418 Op.getOperand(1)));
11419 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
11420 Op.getOperand(0), Op.getOperand(1));
11421 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
11422 DAG.getValueType(VT));
11423 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
11426 if (VT == MVT::f32) {
11427 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
11428 // the result back to FR32 register. It's only worth matching if the
11429 // result has a single use which is a store or a bitcast to i32. And in
11430 // the case of a store, it's not worth it if the index is a constant 0,
11431 // because a MOVSSmr can be used instead, which is smaller and faster.
11432 if (!Op.hasOneUse())
11434 SDNode *User = *Op.getNode()->use_begin();
11435 if ((User->getOpcode() != ISD::STORE ||
11436 isNullConstant(Op.getOperand(1))) &&
11437 (User->getOpcode() != ISD::BITCAST ||
11438 User->getValueType(0) != MVT::i32))
11440 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
11441 DAG.getBitcast(MVT::v4i32, Op.getOperand(0)),
11443 return DAG.getBitcast(MVT::f32, Extract);
11446 if (VT == MVT::i32 || VT == MVT::i64) {
11447 // ExtractPS/pextrq works with constant index.
11448 if (isa<ConstantSDNode>(Op.getOperand(1)))
11454 /// Extract one bit from mask vector, like v16i1 or v8i1.
11455 /// AVX-512 feature.
11457 X86TargetLowering::ExtractBitFromMaskVector(SDValue Op, SelectionDAG &DAG) const {
11458 SDValue Vec = Op.getOperand(0);
11460 MVT VecVT = Vec.getSimpleValueType();
11461 SDValue Idx = Op.getOperand(1);
11462 MVT EltVT = Op.getSimpleValueType();
11464 assert((EltVT == MVT::i1) && "Unexpected operands in ExtractBitFromMaskVector");
11465 assert((VecVT.getVectorNumElements() <= 16 || Subtarget->hasBWI()) &&
11466 "Unexpected vector type in ExtractBitFromMaskVector");
11468 // variable index can't be handled in mask registers,
11469 // extend vector to VR512
11470 if (!isa<ConstantSDNode>(Idx)) {
11471 MVT ExtVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
11472 SDValue Ext = DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVT, Vec);
11473 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
11474 ExtVT.getVectorElementType(), Ext, Idx);
11475 return DAG.getNode(ISD::TRUNCATE, dl, EltVT, Elt);
11478 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
11479 const TargetRegisterClass* rc = getRegClassFor(VecVT);
11480 if (!Subtarget->hasDQI() && (VecVT.getVectorNumElements() <= 8))
11481 rc = getRegClassFor(MVT::v16i1);
11482 unsigned MaxSift = rc->getSize()*8 - 1;
11483 Vec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, Vec,
11484 DAG.getConstant(MaxSift - IdxVal, dl, MVT::i8));
11485 Vec = DAG.getNode(X86ISD::VSRLI, dl, VecVT, Vec,
11486 DAG.getConstant(MaxSift, dl, MVT::i8));
11487 return DAG.getNode(X86ISD::VEXTRACT, dl, MVT::i1, Vec,
11488 DAG.getIntPtrConstant(0, dl));
11492 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
11493 SelectionDAG &DAG) const {
11495 SDValue Vec = Op.getOperand(0);
11496 MVT VecVT = Vec.getSimpleValueType();
11497 SDValue Idx = Op.getOperand(1);
11499 if (Op.getSimpleValueType() == MVT::i1)
11500 return ExtractBitFromMaskVector(Op, DAG);
11502 if (!isa<ConstantSDNode>(Idx)) {
11503 if (VecVT.is512BitVector() ||
11504 (VecVT.is256BitVector() && Subtarget->hasInt256() &&
11505 VecVT.getVectorElementType().getSizeInBits() == 32)) {
11508 MVT::getIntegerVT(VecVT.getVectorElementType().getSizeInBits());
11509 MVT MaskVT = MVT::getVectorVT(MaskEltVT, VecVT.getSizeInBits() /
11510 MaskEltVT.getSizeInBits());
11512 Idx = DAG.getZExtOrTrunc(Idx, dl, MaskEltVT);
11513 auto PtrVT = getPointerTy(DAG.getDataLayout());
11514 SDValue Mask = DAG.getNode(X86ISD::VINSERT, dl, MaskVT,
11515 getZeroVector(MaskVT, Subtarget, DAG, dl), Idx,
11516 DAG.getConstant(0, dl, PtrVT));
11517 SDValue Perm = DAG.getNode(X86ISD::VPERMV, dl, VecVT, Mask, Vec);
11518 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Perm,
11519 DAG.getConstant(0, dl, PtrVT));
11524 // If this is a 256-bit vector result, first extract the 128-bit vector and
11525 // then extract the element from the 128-bit vector.
11526 if (VecVT.is256BitVector() || VecVT.is512BitVector()) {
11528 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
11529 // Get the 128-bit vector.
11530 Vec = Extract128BitVector(Vec, IdxVal, DAG, dl);
11531 MVT EltVT = VecVT.getVectorElementType();
11533 unsigned ElemsPerChunk = 128 / EltVT.getSizeInBits();
11534 assert(isPowerOf2_32(ElemsPerChunk) && "Elements per chunk not power of 2");
11536 // Find IdxVal modulo ElemsPerChunk. Since ElemsPerChunk is a power of 2
11537 // this can be done with a mask.
11538 IdxVal &= ElemsPerChunk - 1;
11539 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec,
11540 DAG.getConstant(IdxVal, dl, MVT::i32));
11543 assert(VecVT.is128BitVector() && "Unexpected vector length");
11545 if (Subtarget->hasSSE41())
11546 if (SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG))
11549 MVT VT = Op.getSimpleValueType();
11550 // TODO: handle v16i8.
11551 if (VT.getSizeInBits() == 16) {
11552 SDValue Vec = Op.getOperand(0);
11553 if (isNullConstant(Op.getOperand(1)))
11554 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
11555 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
11556 DAG.getBitcast(MVT::v4i32, Vec),
11557 Op.getOperand(1)));
11558 // Transform it so it match pextrw which produces a 32-bit result.
11559 MVT EltVT = MVT::i32;
11560 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
11561 Op.getOperand(0), Op.getOperand(1));
11562 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
11563 DAG.getValueType(VT));
11564 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
11567 if (VT.getSizeInBits() == 32) {
11568 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
11572 // SHUFPS the element to the lowest double word, then movss.
11573 int Mask[4] = { static_cast<int>(Idx), -1, -1, -1 };
11574 MVT VVT = Op.getOperand(0).getSimpleValueType();
11575 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
11576 DAG.getUNDEF(VVT), Mask);
11577 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
11578 DAG.getIntPtrConstant(0, dl));
11581 if (VT.getSizeInBits() == 64) {
11582 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
11583 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
11584 // to match extract_elt for f64.
11585 if (isNullConstant(Op.getOperand(1)))
11588 // UNPCKHPD the element to the lowest double word, then movsd.
11589 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
11590 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
11591 int Mask[2] = { 1, -1 };
11592 MVT VVT = Op.getOperand(0).getSimpleValueType();
11593 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
11594 DAG.getUNDEF(VVT), Mask);
11595 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
11596 DAG.getIntPtrConstant(0, dl));
11602 /// Insert one bit to mask vector, like v16i1 or v8i1.
11603 /// AVX-512 feature.
11605 X86TargetLowering::InsertBitToMaskVector(SDValue Op, SelectionDAG &DAG) const {
11607 SDValue Vec = Op.getOperand(0);
11608 SDValue Elt = Op.getOperand(1);
11609 SDValue Idx = Op.getOperand(2);
11610 MVT VecVT = Vec.getSimpleValueType();
11612 if (!isa<ConstantSDNode>(Idx)) {
11613 // Non constant index. Extend source and destination,
11614 // insert element and then truncate the result.
11615 MVT ExtVecVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
11616 MVT ExtEltVT = (VecVT == MVT::v8i1 ? MVT::i64 : MVT::i32);
11617 SDValue ExtOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ExtVecVT,
11618 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVecVT, Vec),
11619 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtEltVT, Elt), Idx);
11620 return DAG.getNode(ISD::TRUNCATE, dl, VecVT, ExtOp);
11623 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
11624 SDValue EltInVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Elt);
11626 EltInVec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, EltInVec,
11627 DAG.getConstant(IdxVal, dl, MVT::i8));
11628 if (Vec.getOpcode() == ISD::UNDEF)
11630 return DAG.getNode(ISD::OR, dl, VecVT, Vec, EltInVec);
11633 SDValue X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op,
11634 SelectionDAG &DAG) const {
11635 MVT VT = Op.getSimpleValueType();
11636 MVT EltVT = VT.getVectorElementType();
11638 if (EltVT == MVT::i1)
11639 return InsertBitToMaskVector(Op, DAG);
11642 SDValue N0 = Op.getOperand(0);
11643 SDValue N1 = Op.getOperand(1);
11644 SDValue N2 = Op.getOperand(2);
11645 if (!isa<ConstantSDNode>(N2))
11647 auto *N2C = cast<ConstantSDNode>(N2);
11648 unsigned IdxVal = N2C->getZExtValue();
11650 // If the vector is wider than 128 bits, extract the 128-bit subvector, insert
11651 // into that, and then insert the subvector back into the result.
11652 if (VT.is256BitVector() || VT.is512BitVector()) {
11653 // With a 256-bit vector, we can insert into the zero element efficiently
11654 // using a blend if we have AVX or AVX2 and the right data type.
11655 if (VT.is256BitVector() && IdxVal == 0) {
11656 // TODO: It is worthwhile to cast integer to floating point and back
11657 // and incur a domain crossing penalty if that's what we'll end up
11658 // doing anyway after extracting to a 128-bit vector.
11659 if ((Subtarget->hasAVX() && (EltVT == MVT::f64 || EltVT == MVT::f32)) ||
11660 (Subtarget->hasAVX2() && EltVT == MVT::i32)) {
11661 SDValue N1Vec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, N1);
11662 N2 = DAG.getIntPtrConstant(1, dl);
11663 return DAG.getNode(X86ISD::BLENDI, dl, VT, N0, N1Vec, N2);
11667 // Get the desired 128-bit vector chunk.
11668 SDValue V = Extract128BitVector(N0, IdxVal, DAG, dl);
11670 // Insert the element into the desired chunk.
11671 unsigned NumEltsIn128 = 128 / EltVT.getSizeInBits();
11672 assert(isPowerOf2_32(NumEltsIn128));
11673 // Since NumEltsIn128 is a power of 2 we can use mask instead of modulo.
11674 unsigned IdxIn128 = IdxVal & (NumEltsIn128 - 1);
11676 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V, N1,
11677 DAG.getConstant(IdxIn128, dl, MVT::i32));
11679 // Insert the changed part back into the bigger vector
11680 return Insert128BitVector(N0, V, IdxVal, DAG, dl);
11682 assert(VT.is128BitVector() && "Only 128-bit vector types should be left!");
11684 if (Subtarget->hasSSE41()) {
11685 if (EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) {
11687 if (VT == MVT::v8i16) {
11688 Opc = X86ISD::PINSRW;
11690 assert(VT == MVT::v16i8);
11691 Opc = X86ISD::PINSRB;
11694 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
11696 if (N1.getValueType() != MVT::i32)
11697 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
11698 if (N2.getValueType() != MVT::i32)
11699 N2 = DAG.getIntPtrConstant(IdxVal, dl);
11700 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
11703 if (EltVT == MVT::f32) {
11704 // Bits [7:6] of the constant are the source select. This will always be
11705 // zero here. The DAG Combiner may combine an extract_elt index into
11706 // these bits. For example (insert (extract, 3), 2) could be matched by
11707 // putting the '3' into bits [7:6] of X86ISD::INSERTPS.
11708 // Bits [5:4] of the constant are the destination select. This is the
11709 // value of the incoming immediate.
11710 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
11711 // combine either bitwise AND or insert of float 0.0 to set these bits.
11713 bool MinSize = DAG.getMachineFunction().getFunction()->optForMinSize();
11714 if (IdxVal == 0 && (!MinSize || !MayFoldLoad(N1))) {
11715 // If this is an insertion of 32-bits into the low 32-bits of
11716 // a vector, we prefer to generate a blend with immediate rather
11717 // than an insertps. Blends are simpler operations in hardware and so
11718 // will always have equal or better performance than insertps.
11719 // But if optimizing for size and there's a load folding opportunity,
11720 // generate insertps because blendps does not have a 32-bit memory
11722 N2 = DAG.getIntPtrConstant(1, dl);
11723 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
11724 return DAG.getNode(X86ISD::BLENDI, dl, VT, N0, N1, N2);
11726 N2 = DAG.getIntPtrConstant(IdxVal << 4, dl);
11727 // Create this as a scalar to vector..
11728 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
11729 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
11732 if (EltVT == MVT::i32 || EltVT == MVT::i64) {
11733 // PINSR* works with constant index.
11738 if (EltVT == MVT::i8)
11741 if (EltVT.getSizeInBits() == 16) {
11742 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
11743 // as its second argument.
11744 if (N1.getValueType() != MVT::i32)
11745 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
11746 if (N2.getValueType() != MVT::i32)
11747 N2 = DAG.getIntPtrConstant(IdxVal, dl);
11748 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);
11753 static SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) {
11755 MVT OpVT = Op.getSimpleValueType();
11757 // If this is a 256-bit vector result, first insert into a 128-bit
11758 // vector and then insert into the 256-bit vector.
11759 if (!OpVT.is128BitVector()) {
11760 // Insert into a 128-bit vector.
11761 unsigned SizeFactor = OpVT.getSizeInBits()/128;
11762 MVT VT128 = MVT::getVectorVT(OpVT.getVectorElementType(),
11763 OpVT.getVectorNumElements() / SizeFactor);
11765 Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Op.getOperand(0));
11767 // Insert the 128-bit vector.
11768 return Insert128BitVector(DAG.getUNDEF(OpVT), Op, 0, DAG, dl);
11771 if (OpVT == MVT::v1i64 &&
11772 Op.getOperand(0).getValueType() == MVT::i64)
11773 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
11775 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
11776 assert(OpVT.is128BitVector() && "Expected an SSE type!");
11777 return DAG.getBitcast(
11778 OpVT, DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, AnyExt));
11781 // Lower a node with an EXTRACT_SUBVECTOR opcode. This may result in
11782 // a simple subregister reference or explicit instructions to grab
11783 // upper bits of a vector.
11784 static SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
11785 SelectionDAG &DAG) {
11787 SDValue In = Op.getOperand(0);
11788 SDValue Idx = Op.getOperand(1);
11789 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
11790 MVT ResVT = Op.getSimpleValueType();
11791 MVT InVT = In.getSimpleValueType();
11793 if (Subtarget->hasFp256()) {
11794 if (ResVT.is128BitVector() &&
11795 (InVT.is256BitVector() || InVT.is512BitVector()) &&
11796 isa<ConstantSDNode>(Idx)) {
11797 return Extract128BitVector(In, IdxVal, DAG, dl);
11799 if (ResVT.is256BitVector() && InVT.is512BitVector() &&
11800 isa<ConstantSDNode>(Idx)) {
11801 return Extract256BitVector(In, IdxVal, DAG, dl);
11807 // Lower a node with an INSERT_SUBVECTOR opcode. This may result in a
11808 // simple superregister reference or explicit instructions to insert
11809 // the upper bits of a vector.
11810 static SDValue LowerINSERT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
11811 SelectionDAG &DAG) {
11812 if (!Subtarget->hasAVX())
11816 SDValue Vec = Op.getOperand(0);
11817 SDValue SubVec = Op.getOperand(1);
11818 SDValue Idx = Op.getOperand(2);
11820 if (!isa<ConstantSDNode>(Idx))
11823 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
11824 MVT OpVT = Op.getSimpleValueType();
11825 MVT SubVecVT = SubVec.getSimpleValueType();
11827 // Fold two 16-byte subvector loads into one 32-byte load:
11828 // (insert_subvector (insert_subvector undef, (load addr), 0),
11829 // (load addr + 16), Elts/2)
11831 if ((IdxVal == OpVT.getVectorNumElements() / 2) &&
11832 Vec.getOpcode() == ISD::INSERT_SUBVECTOR &&
11833 OpVT.is256BitVector() && SubVecVT.is128BitVector()) {
11834 auto *Idx2 = dyn_cast<ConstantSDNode>(Vec.getOperand(2));
11835 if (Idx2 && Idx2->getZExtValue() == 0) {
11836 SDValue SubVec2 = Vec.getOperand(1);
11837 // If needed, look through a bitcast to get to the load.
11838 if (SubVec2.getNode() && SubVec2.getOpcode() == ISD::BITCAST)
11839 SubVec2 = SubVec2.getOperand(0);
11841 if (auto *FirstLd = dyn_cast<LoadSDNode>(SubVec2)) {
11843 unsigned Alignment = FirstLd->getAlignment();
11844 unsigned AS = FirstLd->getAddressSpace();
11845 const X86TargetLowering *TLI = Subtarget->getTargetLowering();
11846 if (TLI->allowsMemoryAccess(*DAG.getContext(), DAG.getDataLayout(),
11847 OpVT, AS, Alignment, &Fast) && Fast) {
11848 SDValue Ops[] = { SubVec2, SubVec };
11849 if (SDValue Ld = EltsFromConsecutiveLoads(OpVT, Ops, dl, DAG, false))
11856 if ((OpVT.is256BitVector() || OpVT.is512BitVector()) &&
11857 SubVecVT.is128BitVector())
11858 return Insert128BitVector(Vec, SubVec, IdxVal, DAG, dl);
11860 if (OpVT.is512BitVector() && SubVecVT.is256BitVector())
11861 return Insert256BitVector(Vec, SubVec, IdxVal, DAG, dl);
11863 if (OpVT.getVectorElementType() == MVT::i1)
11864 return Insert1BitVector(Op, DAG);
11869 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
11870 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
11871 // one of the above mentioned nodes. It has to be wrapped because otherwise
11872 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
11873 // be used to form addressing mode. These wrapped nodes will be selected
11876 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
11877 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
11879 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
11880 // global base reg.
11881 unsigned char OpFlag = 0;
11882 unsigned WrapperKind = X86ISD::Wrapper;
11883 CodeModel::Model M = DAG.getTarget().getCodeModel();
11885 if (Subtarget->isPICStyleRIPRel() &&
11886 (M == CodeModel::Small || M == CodeModel::Kernel))
11887 WrapperKind = X86ISD::WrapperRIP;
11888 else if (Subtarget->isPICStyleGOT())
11889 OpFlag = X86II::MO_GOTOFF;
11890 else if (Subtarget->isPICStyleStubPIC())
11891 OpFlag = X86II::MO_PIC_BASE_OFFSET;
11893 auto PtrVT = getPointerTy(DAG.getDataLayout());
11894 SDValue Result = DAG.getTargetConstantPool(
11895 CP->getConstVal(), PtrVT, CP->getAlignment(), CP->getOffset(), OpFlag);
11897 Result = DAG.getNode(WrapperKind, DL, PtrVT, Result);
11898 // With PIC, the address is actually $g + Offset.
11901 DAG.getNode(ISD::ADD, DL, PtrVT,
11902 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), Result);
11908 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
11909 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
11911 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
11912 // global base reg.
11913 unsigned char OpFlag = 0;
11914 unsigned WrapperKind = X86ISD::Wrapper;
11915 CodeModel::Model M = DAG.getTarget().getCodeModel();
11917 if (Subtarget->isPICStyleRIPRel() &&
11918 (M == CodeModel::Small || M == CodeModel::Kernel))
11919 WrapperKind = X86ISD::WrapperRIP;
11920 else if (Subtarget->isPICStyleGOT())
11921 OpFlag = X86II::MO_GOTOFF;
11922 else if (Subtarget->isPICStyleStubPIC())
11923 OpFlag = X86II::MO_PIC_BASE_OFFSET;
11925 auto PtrVT = getPointerTy(DAG.getDataLayout());
11926 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, OpFlag);
11928 Result = DAG.getNode(WrapperKind, DL, PtrVT, Result);
11930 // With PIC, the address is actually $g + Offset.
11933 DAG.getNode(ISD::ADD, DL, PtrVT,
11934 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), Result);
11940 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const {
11941 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
11943 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
11944 // global base reg.
11945 unsigned char OpFlag = 0;
11946 unsigned WrapperKind = X86ISD::Wrapper;
11947 CodeModel::Model M = DAG.getTarget().getCodeModel();
11949 if (Subtarget->isPICStyleRIPRel() &&
11950 (M == CodeModel::Small || M == CodeModel::Kernel)) {
11951 if (Subtarget->isTargetDarwin() || Subtarget->isTargetELF())
11952 OpFlag = X86II::MO_GOTPCREL;
11953 WrapperKind = X86ISD::WrapperRIP;
11954 } else if (Subtarget->isPICStyleGOT()) {
11955 OpFlag = X86II::MO_GOT;
11956 } else if (Subtarget->isPICStyleStubPIC()) {
11957 OpFlag = X86II::MO_DARWIN_NONLAZY_PIC_BASE;
11958 } else if (Subtarget->isPICStyleStubNoDynamic()) {
11959 OpFlag = X86II::MO_DARWIN_NONLAZY;
11962 auto PtrVT = getPointerTy(DAG.getDataLayout());
11963 SDValue Result = DAG.getTargetExternalSymbol(Sym, PtrVT, OpFlag);
11966 Result = DAG.getNode(WrapperKind, DL, PtrVT, Result);
11968 // With PIC, the address is actually $g + Offset.
11969 if (DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
11970 !Subtarget->is64Bit()) {
11972 DAG.getNode(ISD::ADD, DL, PtrVT,
11973 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), Result);
11976 // For symbols that require a load from a stub to get the address, emit the
11978 if (isGlobalStubReference(OpFlag))
11979 Result = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), Result,
11980 MachinePointerInfo::getGOT(DAG.getMachineFunction()),
11981 false, false, false, 0);
11987 X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
11988 // Create the TargetBlockAddressAddress node.
11989 unsigned char OpFlags =
11990 Subtarget->ClassifyBlockAddressReference();
11991 CodeModel::Model M = DAG.getTarget().getCodeModel();
11992 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
11993 int64_t Offset = cast<BlockAddressSDNode>(Op)->getOffset();
11995 auto PtrVT = getPointerTy(DAG.getDataLayout());
11996 SDValue Result = DAG.getTargetBlockAddress(BA, PtrVT, Offset, OpFlags);
11998 if (Subtarget->isPICStyleRIPRel() &&
11999 (M == CodeModel::Small || M == CodeModel::Kernel))
12000 Result = DAG.getNode(X86ISD::WrapperRIP, dl, PtrVT, Result);
12002 Result = DAG.getNode(X86ISD::Wrapper, dl, PtrVT, Result);
12004 // With PIC, the address is actually $g + Offset.
12005 if (isGlobalRelativeToPICBase(OpFlags)) {
12006 Result = DAG.getNode(ISD::ADD, dl, PtrVT,
12007 DAG.getNode(X86ISD::GlobalBaseReg, dl, PtrVT), Result);
12014 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, SDLoc dl,
12015 int64_t Offset, SelectionDAG &DAG) const {
12016 // Create the TargetGlobalAddress node, folding in the constant
12017 // offset if it is legal.
12018 unsigned char OpFlags =
12019 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget());
12020 CodeModel::Model M = DAG.getTarget().getCodeModel();
12021 auto PtrVT = getPointerTy(DAG.getDataLayout());
12023 if (OpFlags == X86II::MO_NO_FLAG &&
12024 X86::isOffsetSuitableForCodeModel(Offset, M)) {
12025 // A direct static reference to a global.
12026 Result = DAG.getTargetGlobalAddress(GV, dl, PtrVT, Offset);
12029 Result = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, OpFlags);
12032 if (Subtarget->isPICStyleRIPRel() &&
12033 (M == CodeModel::Small || M == CodeModel::Kernel))
12034 Result = DAG.getNode(X86ISD::WrapperRIP, dl, PtrVT, Result);
12036 Result = DAG.getNode(X86ISD::Wrapper, dl, PtrVT, Result);
12038 // With PIC, the address is actually $g + Offset.
12039 if (isGlobalRelativeToPICBase(OpFlags)) {
12040 Result = DAG.getNode(ISD::ADD, dl, PtrVT,
12041 DAG.getNode(X86ISD::GlobalBaseReg, dl, PtrVT), Result);
12044 // For globals that require a load from a stub to get the address, emit the
12046 if (isGlobalStubReference(OpFlags))
12047 Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Result,
12048 MachinePointerInfo::getGOT(DAG.getMachineFunction()),
12049 false, false, false, 0);
12051 // If there was a non-zero offset that we didn't fold, create an explicit
12052 // addition for it.
12054 Result = DAG.getNode(ISD::ADD, dl, PtrVT, Result,
12055 DAG.getConstant(Offset, dl, PtrVT));
12061 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
12062 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
12063 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
12064 return LowerGlobalAddress(GV, SDLoc(Op), Offset, DAG);
12068 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
12069 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg,
12070 unsigned char OperandFlags, bool LocalDynamic = false) {
12071 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
12072 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
12074 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
12075 GA->getValueType(0),
12079 X86ISD::NodeType CallType = LocalDynamic ? X86ISD::TLSBASEADDR
12083 SDValue Ops[] = { Chain, TGA, *InFlag };
12084 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
12086 SDValue Ops[] = { Chain, TGA };
12087 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
12090 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
12091 MFI->setAdjustsStack(true);
12092 MFI->setHasCalls(true);
12094 SDValue Flag = Chain.getValue(1);
12095 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
12098 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
12100 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
12103 SDLoc dl(GA); // ? function entry point might be better
12104 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
12105 DAG.getNode(X86ISD::GlobalBaseReg,
12106 SDLoc(), PtrVT), InFlag);
12107 InFlag = Chain.getValue(1);
12109 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
12112 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
12114 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
12116 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT,
12117 X86::RAX, X86II::MO_TLSGD);
12120 static SDValue LowerToTLSLocalDynamicModel(GlobalAddressSDNode *GA,
12126 // Get the start address of the TLS block for this module.
12127 X86MachineFunctionInfo* MFI = DAG.getMachineFunction()
12128 .getInfo<X86MachineFunctionInfo>();
12129 MFI->incNumLocalDynamicTLSAccesses();
12133 Base = GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT, X86::RAX,
12134 X86II::MO_TLSLD, /*LocalDynamic=*/true);
12137 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
12138 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), InFlag);
12139 InFlag = Chain.getValue(1);
12140 Base = GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX,
12141 X86II::MO_TLSLDM, /*LocalDynamic=*/true);
12144 // Note: the CleanupLocalDynamicTLSPass will remove redundant computations
12148 unsigned char OperandFlags = X86II::MO_DTPOFF;
12149 unsigned WrapperKind = X86ISD::Wrapper;
12150 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
12151 GA->getValueType(0),
12152 GA->getOffset(), OperandFlags);
12153 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
12155 // Add x@dtpoff with the base.
12156 return DAG.getNode(ISD::ADD, dl, PtrVT, Offset, Base);
12159 // Lower ISD::GlobalTLSAddress using the "initial exec" or "local exec" model.
12160 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
12161 const EVT PtrVT, TLSModel::Model model,
12162 bool is64Bit, bool isPIC) {
12165 // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit).
12166 Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(*DAG.getContext(),
12167 is64Bit ? 257 : 256));
12169 SDValue ThreadPointer =
12170 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), DAG.getIntPtrConstant(0, dl),
12171 MachinePointerInfo(Ptr), false, false, false, 0);
12173 unsigned char OperandFlags = 0;
12174 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
12176 unsigned WrapperKind = X86ISD::Wrapper;
12177 if (model == TLSModel::LocalExec) {
12178 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
12179 } else if (model == TLSModel::InitialExec) {
12181 OperandFlags = X86II::MO_GOTTPOFF;
12182 WrapperKind = X86ISD::WrapperRIP;
12184 OperandFlags = isPIC ? X86II::MO_GOTNTPOFF : X86II::MO_INDNTPOFF;
12187 llvm_unreachable("Unexpected model");
12190 // emit "addl x@ntpoff,%eax" (local exec)
12191 // or "addl x@indntpoff,%eax" (initial exec)
12192 // or "addl x@gotntpoff(%ebx) ,%eax" (initial exec, 32-bit pic)
12194 DAG.getTargetGlobalAddress(GA->getGlobal(), dl, GA->getValueType(0),
12195 GA->getOffset(), OperandFlags);
12196 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
12198 if (model == TLSModel::InitialExec) {
12199 if (isPIC && !is64Bit) {
12200 Offset = DAG.getNode(ISD::ADD, dl, PtrVT,
12201 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT),
12205 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
12206 MachinePointerInfo::getGOT(DAG.getMachineFunction()),
12207 false, false, false, 0);
12210 // The address of the thread local variable is the add of the thread
12211 // pointer with the offset of the variable.
12212 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
12216 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
12218 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
12219 const GlobalValue *GV = GA->getGlobal();
12220 auto PtrVT = getPointerTy(DAG.getDataLayout());
12222 if (Subtarget->isTargetELF()) {
12223 if (DAG.getTarget().Options.EmulatedTLS)
12224 return LowerToTLSEmulatedModel(GA, DAG);
12225 TLSModel::Model model = DAG.getTarget().getTLSModel(GV);
12227 case TLSModel::GeneralDynamic:
12228 if (Subtarget->is64Bit())
12229 return LowerToTLSGeneralDynamicModel64(GA, DAG, PtrVT);
12230 return LowerToTLSGeneralDynamicModel32(GA, DAG, PtrVT);
12231 case TLSModel::LocalDynamic:
12232 return LowerToTLSLocalDynamicModel(GA, DAG, PtrVT,
12233 Subtarget->is64Bit());
12234 case TLSModel::InitialExec:
12235 case TLSModel::LocalExec:
12236 return LowerToTLSExecModel(GA, DAG, PtrVT, model, Subtarget->is64Bit(),
12237 DAG.getTarget().getRelocationModel() ==
12240 llvm_unreachable("Unknown TLS model.");
12243 if (Subtarget->isTargetDarwin()) {
12244 // Darwin only has one model of TLS. Lower to that.
12245 unsigned char OpFlag = 0;
12246 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ?
12247 X86ISD::WrapperRIP : X86ISD::Wrapper;
12249 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
12250 // global base reg.
12251 bool PIC32 = (DAG.getTarget().getRelocationModel() == Reloc::PIC_) &&
12252 !Subtarget->is64Bit();
12254 OpFlag = X86II::MO_TLVP_PIC_BASE;
12256 OpFlag = X86II::MO_TLVP;
12258 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL,
12259 GA->getValueType(0),
12260 GA->getOffset(), OpFlag);
12261 SDValue Offset = DAG.getNode(WrapperKind, DL, PtrVT, Result);
12263 // With PIC32, the address is actually $g + Offset.
12265 Offset = DAG.getNode(ISD::ADD, DL, PtrVT,
12266 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT),
12269 // Lowering the machine isd will make sure everything is in the right
12271 SDValue Chain = DAG.getEntryNode();
12272 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
12273 SDValue Args[] = { Chain, Offset };
12274 Chain = DAG.getNode(X86ISD::TLSCALL, DL, NodeTys, Args);
12276 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls.
12277 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
12278 MFI->setAdjustsStack(true);
12280 // And our return value (tls address) is in the standard call return value
12282 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
12283 return DAG.getCopyFromReg(Chain, DL, Reg, PtrVT, Chain.getValue(1));
12286 if (Subtarget->isTargetKnownWindowsMSVC() ||
12287 Subtarget->isTargetWindowsGNU()) {
12288 // Just use the implicit TLS architecture
12289 // Need to generate someting similar to:
12290 // mov rdx, qword [gs:abs 58H]; Load pointer to ThreadLocalStorage
12292 // mov ecx, dword [rel _tls_index]: Load index (from C runtime)
12293 // mov rcx, qword [rdx+rcx*8]
12294 // mov eax, .tls$:tlsvar
12295 // [rax+rcx] contains the address
12296 // Windows 64bit: gs:0x58
12297 // Windows 32bit: fs:__tls_array
12300 SDValue Chain = DAG.getEntryNode();
12302 // Get the Thread Pointer, which is %fs:__tls_array (32-bit) or
12303 // %gs:0x58 (64-bit). On MinGW, __tls_array is not available, so directly
12304 // use its literal value of 0x2C.
12305 Value *Ptr = Constant::getNullValue(Subtarget->is64Bit()
12306 ? Type::getInt8PtrTy(*DAG.getContext(),
12308 : Type::getInt32PtrTy(*DAG.getContext(),
12311 SDValue TlsArray = Subtarget->is64Bit()
12312 ? DAG.getIntPtrConstant(0x58, dl)
12313 : (Subtarget->isTargetWindowsGNU()
12314 ? DAG.getIntPtrConstant(0x2C, dl)
12315 : DAG.getExternalSymbol("_tls_array", PtrVT));
12317 SDValue ThreadPointer =
12318 DAG.getLoad(PtrVT, dl, Chain, TlsArray, MachinePointerInfo(Ptr), false,
12322 if (GV->getThreadLocalMode() == GlobalVariable::LocalExecTLSModel) {
12323 res = ThreadPointer;
12325 // Load the _tls_index variable
12326 SDValue IDX = DAG.getExternalSymbol("_tls_index", PtrVT);
12327 if (Subtarget->is64Bit())
12328 IDX = DAG.getExtLoad(ISD::ZEXTLOAD, dl, PtrVT, Chain, IDX,
12329 MachinePointerInfo(), MVT::i32, false, false,
12332 IDX = DAG.getLoad(PtrVT, dl, Chain, IDX, MachinePointerInfo(), false,
12335 auto &DL = DAG.getDataLayout();
12337 DAG.getConstant(Log2_64_Ceil(DL.getPointerSize()), dl, PtrVT);
12338 IDX = DAG.getNode(ISD::SHL, dl, PtrVT, IDX, Scale);
12340 res = DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, IDX);
12343 res = DAG.getLoad(PtrVT, dl, Chain, res, MachinePointerInfo(), false, false,
12346 // Get the offset of start of .tls section
12347 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
12348 GA->getValueType(0),
12349 GA->getOffset(), X86II::MO_SECREL);
12350 SDValue Offset = DAG.getNode(X86ISD::Wrapper, dl, PtrVT, TGA);
12352 // The address of the thread local variable is the add of the thread
12353 // pointer with the offset of the variable.
12354 return DAG.getNode(ISD::ADD, dl, PtrVT, res, Offset);
12357 llvm_unreachable("TLS not implemented for this target.");
12360 /// LowerShiftParts - Lower SRA_PARTS and friends, which return two i32 values
12361 /// and take a 2 x i32 value to shift plus a shift amount.
12362 static SDValue LowerShiftParts(SDValue Op, SelectionDAG &DAG) {
12363 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
12364 MVT VT = Op.getSimpleValueType();
12365 unsigned VTBits = VT.getSizeInBits();
12367 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
12368 SDValue ShOpLo = Op.getOperand(0);
12369 SDValue ShOpHi = Op.getOperand(1);
12370 SDValue ShAmt = Op.getOperand(2);
12371 // X86ISD::SHLD and X86ISD::SHRD have defined overflow behavior but the
12372 // generic ISD nodes haven't. Insert an AND to be safe, it's optimized away
12374 SDValue SafeShAmt = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
12375 DAG.getConstant(VTBits - 1, dl, MVT::i8));
12376 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
12377 DAG.getConstant(VTBits - 1, dl, MVT::i8))
12378 : DAG.getConstant(0, dl, VT);
12380 SDValue Tmp2, Tmp3;
12381 if (Op.getOpcode() == ISD::SHL_PARTS) {
12382 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
12383 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, SafeShAmt);
12385 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
12386 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, SafeShAmt);
12389 // If the shift amount is larger or equal than the width of a part we can't
12390 // rely on the results of shld/shrd. Insert a test and select the appropriate
12391 // values for large shift amounts.
12392 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
12393 DAG.getConstant(VTBits, dl, MVT::i8));
12394 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
12395 AndNode, DAG.getConstant(0, dl, MVT::i8));
12398 SDValue CC = DAG.getConstant(X86::COND_NE, dl, MVT::i8);
12399 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
12400 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
12402 if (Op.getOpcode() == ISD::SHL_PARTS) {
12403 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
12404 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
12406 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
12407 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
12410 SDValue Ops[2] = { Lo, Hi };
12411 return DAG.getMergeValues(Ops, dl);
12414 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op,
12415 SelectionDAG &DAG) const {
12416 SDValue Src = Op.getOperand(0);
12417 MVT SrcVT = Src.getSimpleValueType();
12418 MVT VT = Op.getSimpleValueType();
12421 if (SrcVT.isVector()) {
12422 if (SrcVT == MVT::v2i32 && VT == MVT::v2f64) {
12423 return DAG.getNode(X86ISD::CVTDQ2PD, dl, VT,
12424 DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v4i32, Src,
12425 DAG.getUNDEF(SrcVT)));
12427 if (SrcVT.getVectorElementType() == MVT::i1) {
12428 MVT IntegerVT = MVT::getVectorVT(MVT::i32, SrcVT.getVectorNumElements());
12429 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
12430 DAG.getNode(ISD::SIGN_EXTEND, dl, IntegerVT, Src));
12435 assert(SrcVT <= MVT::i64 && SrcVT >= MVT::i16 &&
12436 "Unknown SINT_TO_FP to lower!");
12438 // These are really Legal; return the operand so the caller accepts it as
12440 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
12442 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
12443 Subtarget->is64Bit()) {
12447 unsigned Size = SrcVT.getSizeInBits()/8;
12448 MachineFunction &MF = DAG.getMachineFunction();
12449 auto PtrVT = getPointerTy(MF.getDataLayout());
12450 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false);
12451 SDValue StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
12452 SDValue Chain = DAG.getStore(
12453 DAG.getEntryNode(), dl, Op.getOperand(0), StackSlot,
12454 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SSFI), false,
12456 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
12459 SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
12461 SelectionDAG &DAG) const {
12465 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
12467 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Glue);
12469 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
12471 unsigned ByteSize = SrcVT.getSizeInBits()/8;
12473 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(StackSlot);
12474 MachineMemOperand *MMO;
12476 int SSFI = FI->getIndex();
12477 MMO = DAG.getMachineFunction().getMachineMemOperand(
12478 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SSFI),
12479 MachineMemOperand::MOLoad, ByteSize, ByteSize);
12481 MMO = cast<LoadSDNode>(StackSlot)->getMemOperand();
12482 StackSlot = StackSlot.getOperand(1);
12484 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) };
12485 SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG :
12487 Tys, Ops, SrcVT, MMO);
12490 Chain = Result.getValue(1);
12491 SDValue InFlag = Result.getValue(2);
12493 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
12494 // shouldn't be necessary except that RFP cannot be live across
12495 // multiple blocks. When stackifier is fixed, they can be uncoupled.
12496 MachineFunction &MF = DAG.getMachineFunction();
12497 unsigned SSFISize = Op.getValueType().getSizeInBits()/8;
12498 int SSFI = MF.getFrameInfo()->CreateStackObject(SSFISize, SSFISize, false);
12499 auto PtrVT = getPointerTy(MF.getDataLayout());
12500 SDValue StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
12501 Tys = DAG.getVTList(MVT::Other);
12503 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag
12505 MachineMemOperand *MMO = DAG.getMachineFunction().getMachineMemOperand(
12506 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SSFI),
12507 MachineMemOperand::MOStore, SSFISize, SSFISize);
12509 Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys,
12510 Ops, Op.getValueType(), MMO);
12511 Result = DAG.getLoad(
12512 Op.getValueType(), DL, Chain, StackSlot,
12513 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SSFI),
12514 false, false, false, 0);
12520 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
12521 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op,
12522 SelectionDAG &DAG) const {
12523 // This algorithm is not obvious. Here it is what we're trying to output:
12526 punpckldq (c0), %xmm0 // c0: (uint4){ 0x43300000U, 0x45300000U, 0U, 0U }
12527 subpd (c1), %xmm0 // c1: (double2){ 0x1.0p52, 0x1.0p52 * 0x1.0p32 }
12529 haddpd %xmm0, %xmm0
12531 pshufd $0x4e, %xmm0, %xmm1
12537 LLVMContext *Context = DAG.getContext();
12539 // Build some magic constants.
12540 static const uint32_t CV0[] = { 0x43300000, 0x45300000, 0, 0 };
12541 Constant *C0 = ConstantDataVector::get(*Context, CV0);
12542 auto PtrVT = getPointerTy(DAG.getDataLayout());
12543 SDValue CPIdx0 = DAG.getConstantPool(C0, PtrVT, 16);
12545 SmallVector<Constant*,2> CV1;
12547 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
12548 APInt(64, 0x4330000000000000ULL))));
12550 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
12551 APInt(64, 0x4530000000000000ULL))));
12552 Constant *C1 = ConstantVector::get(CV1);
12553 SDValue CPIdx1 = DAG.getConstantPool(C1, PtrVT, 16);
12555 // Load the 64-bit value into an XMM register.
12556 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
12559 DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
12560 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()),
12561 false, false, false, 16);
12563 getUnpackl(DAG, dl, MVT::v4i32, DAG.getBitcast(MVT::v4i32, XR1), CLod0);
12566 DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
12567 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()),
12568 false, false, false, 16);
12569 SDValue XR2F = DAG.getBitcast(MVT::v2f64, Unpck1);
12570 // TODO: Are there any fast-math-flags to propagate here?
12571 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
12574 if (Subtarget->hasSSE3()) {
12575 // FIXME: The 'haddpd' instruction may be slower than 'movhlps + addsd'.
12576 Result = DAG.getNode(X86ISD::FHADD, dl, MVT::v2f64, Sub, Sub);
12578 SDValue S2F = DAG.getBitcast(MVT::v4i32, Sub);
12579 SDValue Shuffle = getTargetShuffleNode(X86ISD::PSHUFD, dl, MVT::v4i32,
12581 Result = DAG.getNode(ISD::FADD, dl, MVT::v2f64,
12582 DAG.getBitcast(MVT::v2f64, Shuffle), Sub);
12585 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Result,
12586 DAG.getIntPtrConstant(0, dl));
12589 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
12590 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op,
12591 SelectionDAG &DAG) const {
12593 // FP constant to bias correct the final result.
12594 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL), dl,
12597 // Load the 32-bit value into an XMM register.
12598 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
12601 // Zero out the upper parts of the register.
12602 Load = getShuffleVectorZeroOrUndef(Load, 0, true, Subtarget, DAG);
12604 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
12605 DAG.getBitcast(MVT::v2f64, Load),
12606 DAG.getIntPtrConstant(0, dl));
12608 // Or the load with the bias.
12609 SDValue Or = DAG.getNode(
12610 ISD::OR, dl, MVT::v2i64,
12611 DAG.getBitcast(MVT::v2i64,
12612 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, Load)),
12613 DAG.getBitcast(MVT::v2i64,
12614 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, Bias)));
12616 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
12617 DAG.getBitcast(MVT::v2f64, Or), DAG.getIntPtrConstant(0, dl));
12619 // Subtract the bias.
12620 // TODO: Are there any fast-math-flags to propagate here?
12621 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
12623 // Handle final rounding.
12624 MVT DestVT = Op.getSimpleValueType();
12626 if (DestVT.bitsLT(MVT::f64))
12627 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
12628 DAG.getIntPtrConstant(0, dl));
12629 if (DestVT.bitsGT(MVT::f64))
12630 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
12632 // Handle final rounding.
12636 static SDValue lowerUINT_TO_FP_vXi32(SDValue Op, SelectionDAG &DAG,
12637 const X86Subtarget &Subtarget) {
12638 // The algorithm is the following:
12639 // #ifdef __SSE4_1__
12640 // uint4 lo = _mm_blend_epi16( v, (uint4) 0x4b000000, 0xaa);
12641 // uint4 hi = _mm_blend_epi16( _mm_srli_epi32(v,16),
12642 // (uint4) 0x53000000, 0xaa);
12644 // uint4 lo = (v & (uint4) 0xffff) | (uint4) 0x4b000000;
12645 // uint4 hi = (v >> 16) | (uint4) 0x53000000;
12647 // float4 fhi = (float4) hi - (0x1.0p39f + 0x1.0p23f);
12648 // return (float4) lo + fhi;
12650 // We shouldn't use it when unsafe-fp-math is enabled though: we might later
12651 // reassociate the two FADDs, and if we do that, the algorithm fails
12652 // spectacularly (PR24512).
12653 // FIXME: If we ever have some kind of Machine FMF, this should be marked
12654 // as non-fast and always be enabled. Why isn't SDAG FMF enough? Because
12655 // there's also the MachineCombiner reassociations happening on Machine IR.
12656 if (DAG.getTarget().Options.UnsafeFPMath)
12660 SDValue V = Op->getOperand(0);
12661 MVT VecIntVT = V.getSimpleValueType();
12662 bool Is128 = VecIntVT == MVT::v4i32;
12663 MVT VecFloatVT = Is128 ? MVT::v4f32 : MVT::v8f32;
12664 // If we convert to something else than the supported type, e.g., to v4f64,
12666 if (VecFloatVT != Op->getSimpleValueType(0))
12669 unsigned NumElts = VecIntVT.getVectorNumElements();
12670 assert((VecIntVT == MVT::v4i32 || VecIntVT == MVT::v8i32) &&
12671 "Unsupported custom type");
12672 assert(NumElts <= 8 && "The size of the constant array must be fixed");
12674 // In the #idef/#else code, we have in common:
12675 // - The vector of constants:
12681 // Create the splat vector for 0x4b000000.
12682 SDValue CstLow = DAG.getConstant(0x4b000000, DL, MVT::i32);
12683 SDValue CstLowArray[] = {CstLow, CstLow, CstLow, CstLow,
12684 CstLow, CstLow, CstLow, CstLow};
12685 SDValue VecCstLow = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
12686 makeArrayRef(&CstLowArray[0], NumElts));
12687 // Create the splat vector for 0x53000000.
12688 SDValue CstHigh = DAG.getConstant(0x53000000, DL, MVT::i32);
12689 SDValue CstHighArray[] = {CstHigh, CstHigh, CstHigh, CstHigh,
12690 CstHigh, CstHigh, CstHigh, CstHigh};
12691 SDValue VecCstHigh = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
12692 makeArrayRef(&CstHighArray[0], NumElts));
12694 // Create the right shift.
12695 SDValue CstShift = DAG.getConstant(16, DL, MVT::i32);
12696 SDValue CstShiftArray[] = {CstShift, CstShift, CstShift, CstShift,
12697 CstShift, CstShift, CstShift, CstShift};
12698 SDValue VecCstShift = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
12699 makeArrayRef(&CstShiftArray[0], NumElts));
12700 SDValue HighShift = DAG.getNode(ISD::SRL, DL, VecIntVT, V, VecCstShift);
12703 if (Subtarget.hasSSE41()) {
12704 MVT VecI16VT = Is128 ? MVT::v8i16 : MVT::v16i16;
12705 // uint4 lo = _mm_blend_epi16( v, (uint4) 0x4b000000, 0xaa);
12706 SDValue VecCstLowBitcast = DAG.getBitcast(VecI16VT, VecCstLow);
12707 SDValue VecBitcast = DAG.getBitcast(VecI16VT, V);
12708 // Low will be bitcasted right away, so do not bother bitcasting back to its
12710 Low = DAG.getNode(X86ISD::BLENDI, DL, VecI16VT, VecBitcast,
12711 VecCstLowBitcast, DAG.getConstant(0xaa, DL, MVT::i32));
12712 // uint4 hi = _mm_blend_epi16( _mm_srli_epi32(v,16),
12713 // (uint4) 0x53000000, 0xaa);
12714 SDValue VecCstHighBitcast = DAG.getBitcast(VecI16VT, VecCstHigh);
12715 SDValue VecShiftBitcast = DAG.getBitcast(VecI16VT, HighShift);
12716 // High will be bitcasted right away, so do not bother bitcasting back to
12717 // its original type.
12718 High = DAG.getNode(X86ISD::BLENDI, DL, VecI16VT, VecShiftBitcast,
12719 VecCstHighBitcast, DAG.getConstant(0xaa, DL, MVT::i32));
12721 SDValue CstMask = DAG.getConstant(0xffff, DL, MVT::i32);
12722 SDValue VecCstMask = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT, CstMask,
12723 CstMask, CstMask, CstMask);
12724 // uint4 lo = (v & (uint4) 0xffff) | (uint4) 0x4b000000;
12725 SDValue LowAnd = DAG.getNode(ISD::AND, DL, VecIntVT, V, VecCstMask);
12726 Low = DAG.getNode(ISD::OR, DL, VecIntVT, LowAnd, VecCstLow);
12728 // uint4 hi = (v >> 16) | (uint4) 0x53000000;
12729 High = DAG.getNode(ISD::OR, DL, VecIntVT, HighShift, VecCstHigh);
12732 // Create the vector constant for -(0x1.0p39f + 0x1.0p23f).
12733 SDValue CstFAdd = DAG.getConstantFP(
12734 APFloat(APFloat::IEEEsingle, APInt(32, 0xD3000080)), DL, MVT::f32);
12735 SDValue CstFAddArray[] = {CstFAdd, CstFAdd, CstFAdd, CstFAdd,
12736 CstFAdd, CstFAdd, CstFAdd, CstFAdd};
12737 SDValue VecCstFAdd = DAG.getNode(ISD::BUILD_VECTOR, DL, VecFloatVT,
12738 makeArrayRef(&CstFAddArray[0], NumElts));
12740 // float4 fhi = (float4) hi - (0x1.0p39f + 0x1.0p23f);
12741 SDValue HighBitcast = DAG.getBitcast(VecFloatVT, High);
12742 // TODO: Are there any fast-math-flags to propagate here?
12744 DAG.getNode(ISD::FADD, DL, VecFloatVT, HighBitcast, VecCstFAdd);
12745 // return (float4) lo + fhi;
12746 SDValue LowBitcast = DAG.getBitcast(VecFloatVT, Low);
12747 return DAG.getNode(ISD::FADD, DL, VecFloatVT, LowBitcast, FHigh);
12750 SDValue X86TargetLowering::lowerUINT_TO_FP_vec(SDValue Op,
12751 SelectionDAG &DAG) const {
12752 SDValue N0 = Op.getOperand(0);
12753 MVT SVT = N0.getSimpleValueType();
12756 switch (SVT.SimpleTy) {
12758 llvm_unreachable("Custom UINT_TO_FP is not supported!");
12763 MVT NVT = MVT::getVectorVT(MVT::i32, SVT.getVectorNumElements());
12764 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
12765 DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, N0));
12769 return lowerUINT_TO_FP_vXi32(Op, DAG, *Subtarget);
12772 assert(Subtarget->hasAVX512());
12773 return DAG.getNode(ISD::UINT_TO_FP, dl, Op.getValueType(),
12774 DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v16i32, N0));
12778 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op,
12779 SelectionDAG &DAG) const {
12780 SDValue N0 = Op.getOperand(0);
12782 auto PtrVT = getPointerTy(DAG.getDataLayout());
12784 if (Op.getSimpleValueType().isVector())
12785 return lowerUINT_TO_FP_vec(Op, DAG);
12787 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't
12788 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
12789 // the optimization here.
12790 if (DAG.SignBitIsZero(N0))
12791 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
12793 MVT SrcVT = N0.getSimpleValueType();
12794 MVT DstVT = Op.getSimpleValueType();
12796 if (Subtarget->hasAVX512() && isScalarFPTypeInSSEReg(DstVT) &&
12797 (SrcVT == MVT::i32 || (SrcVT == MVT::i64 && Subtarget->is64Bit()))) {
12798 // Conversions from unsigned i32 to f32/f64 are legal,
12799 // using VCVTUSI2SS/SD. Same for i64 in 64-bit mode.
12803 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64)
12804 return LowerUINT_TO_FP_i64(Op, DAG);
12805 if (SrcVT == MVT::i32 && X86ScalarSSEf64)
12806 return LowerUINT_TO_FP_i32(Op, DAG);
12807 if (Subtarget->is64Bit() && SrcVT == MVT::i64 && DstVT == MVT::f32)
12810 // Make a 64-bit buffer, and use it to build an FILD.
12811 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
12812 if (SrcVT == MVT::i32) {
12813 SDValue WordOff = DAG.getConstant(4, dl, PtrVT);
12814 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl, PtrVT, StackSlot, WordOff);
12815 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
12816 StackSlot, MachinePointerInfo(),
12818 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, dl, MVT::i32),
12819 OffsetSlot, MachinePointerInfo(),
12821 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
12825 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP");
12826 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
12827 StackSlot, MachinePointerInfo(),
12829 // For i64 source, we need to add the appropriate power of 2 if the input
12830 // was negative. This is the same as the optimization in
12831 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here,
12832 // we must be careful to do the computation in x87 extended precision, not
12833 // in SSE. (The generic code can't know it's OK to do this, or how to.)
12834 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex();
12835 MachineMemOperand *MMO = DAG.getMachineFunction().getMachineMemOperand(
12836 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SSFI),
12837 MachineMemOperand::MOLoad, 8, 8);
12839 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other);
12840 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) };
12841 SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops,
12844 APInt FF(32, 0x5F800000ULL);
12846 // Check whether the sign bit is set.
12847 SDValue SignSet = DAG.getSetCC(
12848 dl, getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), MVT::i64),
12849 Op.getOperand(0), DAG.getConstant(0, dl, MVT::i64), ISD::SETLT);
12851 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
12852 SDValue FudgePtr = DAG.getConstantPool(
12853 ConstantInt::get(*DAG.getContext(), FF.zext(64)), PtrVT);
12855 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
12856 SDValue Zero = DAG.getIntPtrConstant(0, dl);
12857 SDValue Four = DAG.getIntPtrConstant(4, dl);
12858 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
12860 FudgePtr = DAG.getNode(ISD::ADD, dl, PtrVT, FudgePtr, Offset);
12862 // Load the value out, extending it from f32 to f80.
12863 // FIXME: Avoid the extend by constructing the right constant pool?
12864 SDValue Fudge = DAG.getExtLoad(
12865 ISD::EXTLOAD, dl, MVT::f80, DAG.getEntryNode(), FudgePtr,
12866 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()), MVT::f32,
12867 false, false, false, 4);
12868 // Extend everything to 80 bits to force it to be done on x87.
12869 // TODO: Are there any fast-math-flags to propagate here?
12870 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge);
12871 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add,
12872 DAG.getIntPtrConstant(0, dl));
12875 // If the given FP_TO_SINT (IsSigned) or FP_TO_UINT (!IsSigned) operation
12876 // is legal, or has an fp128 or f16 source (which needs to be promoted to f32),
12877 // just return an <SDValue(), SDValue()> pair.
12878 // Otherwise it is assumed to be a conversion from one of f32, f64 or f80
12879 // to i16, i32 or i64, and we lower it to a legal sequence.
12880 // If lowered to the final integer result we return a <result, SDValue()> pair.
12881 // Otherwise we lower it to a sequence ending with a FIST, return a
12882 // <FIST, StackSlot> pair, and the caller is responsible for loading
12883 // the final integer result from StackSlot.
12884 std::pair<SDValue,SDValue>
12885 X86TargetLowering::FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG,
12886 bool IsSigned, bool IsReplace) const {
12889 EVT DstTy = Op.getValueType();
12890 EVT TheVT = Op.getOperand(0).getValueType();
12891 auto PtrVT = getPointerTy(DAG.getDataLayout());
12893 if (TheVT != MVT::f32 && TheVT != MVT::f64 && TheVT != MVT::f80) {
12894 // f16 must be promoted before using the lowering in this routine.
12895 // fp128 does not use this lowering.
12896 return std::make_pair(SDValue(), SDValue());
12899 // If using FIST to compute an unsigned i64, we'll need some fixup
12900 // to handle values above the maximum signed i64. A FIST is always
12901 // used for the 32-bit subtarget, but also for f80 on a 64-bit target.
12902 bool UnsignedFixup = !IsSigned &&
12903 DstTy == MVT::i64 &&
12904 (!Subtarget->is64Bit() ||
12905 !isScalarFPTypeInSSEReg(TheVT));
12907 if (!IsSigned && DstTy != MVT::i64 && !Subtarget->hasAVX512()) {
12908 // Replace the fp-to-uint32 operation with an fp-to-sint64 FIST.
12909 // The low 32 bits of the fist result will have the correct uint32 result.
12910 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
12914 assert(DstTy.getSimpleVT() <= MVT::i64 &&
12915 DstTy.getSimpleVT() >= MVT::i16 &&
12916 "Unknown FP_TO_INT to lower!");
12918 // These are really Legal.
12919 if (DstTy == MVT::i32 &&
12920 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
12921 return std::make_pair(SDValue(), SDValue());
12922 if (Subtarget->is64Bit() &&
12923 DstTy == MVT::i64 &&
12924 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
12925 return std::make_pair(SDValue(), SDValue());
12927 // We lower FP->int64 into FISTP64 followed by a load from a temporary
12929 MachineFunction &MF = DAG.getMachineFunction();
12930 unsigned MemSize = DstTy.getSizeInBits()/8;
12931 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
12932 SDValue StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
12935 switch (DstTy.getSimpleVT().SimpleTy) {
12936 default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
12937 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
12938 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
12939 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
12942 SDValue Chain = DAG.getEntryNode();
12943 SDValue Value = Op.getOperand(0);
12944 SDValue Adjust; // 0x0 or 0x80000000, for result sign bit adjustment.
12946 if (UnsignedFixup) {
12948 // Conversion to unsigned i64 is implemented with a select,
12949 // depending on whether the source value fits in the range
12950 // of a signed i64. Let Thresh be the FP equivalent of
12951 // 0x8000000000000000ULL.
12953 // Adjust i32 = (Value < Thresh) ? 0 : 0x80000000;
12954 // FistSrc = (Value < Thresh) ? Value : (Value - Thresh);
12955 // Fist-to-mem64 FistSrc
12956 // Add 0 or 0x800...0ULL to the 64-bit result, which is equivalent
12957 // to XOR'ing the high 32 bits with Adjust.
12959 // Being a power of 2, Thresh is exactly representable in all FP formats.
12960 // For X87 we'd like to use the smallest FP type for this constant, but
12961 // for DAG type consistency we have to match the FP operand type.
12963 APFloat Thresh(APFloat::IEEEsingle, APInt(32, 0x5f000000));
12964 LLVM_ATTRIBUTE_UNUSED APFloat::opStatus Status = APFloat::opOK;
12965 bool LosesInfo = false;
12966 if (TheVT == MVT::f64)
12967 // The rounding mode is irrelevant as the conversion should be exact.
12968 Status = Thresh.convert(APFloat::IEEEdouble, APFloat::rmNearestTiesToEven,
12970 else if (TheVT == MVT::f80)
12971 Status = Thresh.convert(APFloat::x87DoubleExtended,
12972 APFloat::rmNearestTiesToEven, &LosesInfo);
12974 assert(Status == APFloat::opOK && !LosesInfo &&
12975 "FP conversion should have been exact");
12977 SDValue ThreshVal = DAG.getConstantFP(Thresh, DL, TheVT);
12979 SDValue Cmp = DAG.getSetCC(DL,
12980 getSetCCResultType(DAG.getDataLayout(),
12981 *DAG.getContext(), TheVT),
12982 Value, ThreshVal, ISD::SETLT);
12983 Adjust = DAG.getSelect(DL, MVT::i32, Cmp,
12984 DAG.getConstant(0, DL, MVT::i32),
12985 DAG.getConstant(0x80000000, DL, MVT::i32));
12986 SDValue Sub = DAG.getNode(ISD::FSUB, DL, TheVT, Value, ThreshVal);
12987 Cmp = DAG.getSetCC(DL, getSetCCResultType(DAG.getDataLayout(),
12988 *DAG.getContext(), TheVT),
12989 Value, ThreshVal, ISD::SETLT);
12990 Value = DAG.getSelect(DL, TheVT, Cmp, Value, Sub);
12993 // FIXME This causes a redundant load/store if the SSE-class value is already
12994 // in memory, such as if it is on the callstack.
12995 if (isScalarFPTypeInSSEReg(TheVT)) {
12996 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
12997 Chain = DAG.getStore(Chain, DL, Value, StackSlot,
12998 MachinePointerInfo::getFixedStack(MF, SSFI), false,
13000 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
13002 Chain, StackSlot, DAG.getValueType(TheVT)
13005 MachineMemOperand *MMO =
13006 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(MF, SSFI),
13007 MachineMemOperand::MOLoad, MemSize, MemSize);
13008 Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops, DstTy, MMO);
13009 Chain = Value.getValue(1);
13010 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
13011 StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
13014 MachineMemOperand *MMO =
13015 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(MF, SSFI),
13016 MachineMemOperand::MOStore, MemSize, MemSize);
13018 if (UnsignedFixup) {
13020 // Insert the FIST, load its result as two i32's,
13021 // and XOR the high i32 with Adjust.
13023 SDValue FistOps[] = { Chain, Value, StackSlot };
13024 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
13025 FistOps, DstTy, MMO);
13027 SDValue Low32 = DAG.getLoad(MVT::i32, DL, FIST, StackSlot,
13028 MachinePointerInfo(),
13029 false, false, false, 0);
13030 SDValue HighAddr = DAG.getNode(ISD::ADD, DL, PtrVT, StackSlot,
13031 DAG.getConstant(4, DL, PtrVT));
13033 SDValue High32 = DAG.getLoad(MVT::i32, DL, FIST, HighAddr,
13034 MachinePointerInfo(),
13035 false, false, false, 0);
13036 High32 = DAG.getNode(ISD::XOR, DL, MVT::i32, High32, Adjust);
13038 if (Subtarget->is64Bit()) {
13039 // Join High32 and Low32 into a 64-bit result.
13040 // (High32 << 32) | Low32
13041 Low32 = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64, Low32);
13042 High32 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, High32);
13043 High32 = DAG.getNode(ISD::SHL, DL, MVT::i64, High32,
13044 DAG.getConstant(32, DL, MVT::i8));
13045 SDValue Result = DAG.getNode(ISD::OR, DL, MVT::i64, High32, Low32);
13046 return std::make_pair(Result, SDValue());
13049 SDValue ResultOps[] = { Low32, High32 };
13051 SDValue pair = IsReplace
13052 ? DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, ResultOps)
13053 : DAG.getMergeValues(ResultOps, DL);
13054 return std::make_pair(pair, SDValue());
13056 // Build the FP_TO_INT*_IN_MEM
13057 SDValue Ops[] = { Chain, Value, StackSlot };
13058 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
13060 return std::make_pair(FIST, StackSlot);
13064 static SDValue LowerAVXExtend(SDValue Op, SelectionDAG &DAG,
13065 const X86Subtarget *Subtarget) {
13066 MVT VT = Op->getSimpleValueType(0);
13067 SDValue In = Op->getOperand(0);
13068 MVT InVT = In.getSimpleValueType();
13071 if (VT.is512BitVector() || InVT.getVectorElementType() == MVT::i1)
13072 return DAG.getNode(ISD::ZERO_EXTEND, dl, VT, In);
13074 // Optimize vectors in AVX mode:
13077 // Use vpunpcklwd for 4 lower elements v8i16 -> v4i32.
13078 // Use vpunpckhwd for 4 upper elements v8i16 -> v4i32.
13079 // Concat upper and lower parts.
13082 // Use vpunpckldq for 4 lower elements v4i32 -> v2i64.
13083 // Use vpunpckhdq for 4 upper elements v4i32 -> v2i64.
13084 // Concat upper and lower parts.
13087 if (((VT != MVT::v16i16) || (InVT != MVT::v16i8)) &&
13088 ((VT != MVT::v8i32) || (InVT != MVT::v8i16)) &&
13089 ((VT != MVT::v4i64) || (InVT != MVT::v4i32)))
13092 if (Subtarget->hasInt256())
13093 return DAG.getNode(X86ISD::VZEXT, dl, VT, In);
13095 SDValue ZeroVec = getZeroVector(InVT, Subtarget, DAG, dl);
13096 SDValue Undef = DAG.getUNDEF(InVT);
13097 bool NeedZero = Op.getOpcode() == ISD::ZERO_EXTEND;
13098 SDValue OpLo = getUnpackl(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
13099 SDValue OpHi = getUnpackh(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
13101 MVT HVT = MVT::getVectorVT(VT.getVectorElementType(),
13102 VT.getVectorNumElements()/2);
13104 OpLo = DAG.getBitcast(HVT, OpLo);
13105 OpHi = DAG.getBitcast(HVT, OpHi);
13107 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
13110 static SDValue LowerZERO_EXTEND_AVX512(SDValue Op,
13111 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
13112 MVT VT = Op->getSimpleValueType(0);
13113 SDValue In = Op->getOperand(0);
13114 MVT InVT = In.getSimpleValueType();
13116 unsigned int NumElts = VT.getVectorNumElements();
13117 if (NumElts != 8 && NumElts != 16 && !Subtarget->hasBWI())
13120 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1)
13121 return DAG.getNode(X86ISD::VZEXT, DL, VT, In);
13123 assert(InVT.getVectorElementType() == MVT::i1);
13124 MVT ExtVT = NumElts == 8 ? MVT::v8i64 : MVT::v16i32;
13126 DAG.getConstant(APInt(ExtVT.getScalarSizeInBits(), 1), DL, ExtVT);
13128 DAG.getConstant(APInt::getNullValue(ExtVT.getScalarSizeInBits()), DL, ExtVT);
13130 SDValue V = DAG.getNode(ISD::VSELECT, DL, ExtVT, In, One, Zero);
13131 if (VT.is512BitVector())
13133 return DAG.getNode(X86ISD::VTRUNC, DL, VT, V);
13136 static SDValue LowerANY_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
13137 SelectionDAG &DAG) {
13138 if (Subtarget->hasFp256())
13139 if (SDValue Res = LowerAVXExtend(Op, DAG, Subtarget))
13145 static SDValue LowerZERO_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
13146 SelectionDAG &DAG) {
13148 MVT VT = Op.getSimpleValueType();
13149 SDValue In = Op.getOperand(0);
13150 MVT SVT = In.getSimpleValueType();
13152 if (VT.is512BitVector() || SVT.getVectorElementType() == MVT::i1)
13153 return LowerZERO_EXTEND_AVX512(Op, Subtarget, DAG);
13155 if (Subtarget->hasFp256())
13156 if (SDValue Res = LowerAVXExtend(Op, DAG, Subtarget))
13159 assert(!VT.is256BitVector() || !SVT.is128BitVector() ||
13160 VT.getVectorNumElements() != SVT.getVectorNumElements());
13164 SDValue X86TargetLowering::LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const {
13166 MVT VT = Op.getSimpleValueType();
13167 SDValue In = Op.getOperand(0);
13168 MVT InVT = In.getSimpleValueType();
13170 if (VT == MVT::i1) {
13171 assert((InVT.isInteger() && (InVT.getSizeInBits() <= 64)) &&
13172 "Invalid scalar TRUNCATE operation");
13173 if (InVT.getSizeInBits() >= 32)
13175 In = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, In);
13176 return DAG.getNode(ISD::TRUNCATE, DL, VT, In);
13178 assert(VT.getVectorNumElements() == InVT.getVectorNumElements() &&
13179 "Invalid TRUNCATE operation");
13181 // move vector to mask - truncate solution for SKX
13182 if (VT.getVectorElementType() == MVT::i1) {
13183 if (InVT.is512BitVector() && InVT.getScalarSizeInBits() <= 16 &&
13184 Subtarget->hasBWI())
13185 return Op; // legal, will go to VPMOVB2M, VPMOVW2M
13186 if ((InVT.is256BitVector() || InVT.is128BitVector())
13187 && InVT.getScalarSizeInBits() <= 16 &&
13188 Subtarget->hasBWI() && Subtarget->hasVLX())
13189 return Op; // legal, will go to VPMOVB2M, VPMOVW2M
13190 if (InVT.is512BitVector() && InVT.getScalarSizeInBits() >= 32 &&
13191 Subtarget->hasDQI())
13192 return Op; // legal, will go to VPMOVD2M, VPMOVQ2M
13193 if ((InVT.is256BitVector() || InVT.is128BitVector())
13194 && InVT.getScalarSizeInBits() >= 32 &&
13195 Subtarget->hasDQI() && Subtarget->hasVLX())
13196 return Op; // legal, will go to VPMOVB2M, VPMOVQ2M
13199 if (VT.getVectorElementType() == MVT::i1) {
13200 assert(VT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
13201 unsigned NumElts = InVT.getVectorNumElements();
13202 assert ((NumElts == 8 || NumElts == 16) && "Unexpected vector type");
13203 if (InVT.getSizeInBits() < 512) {
13204 MVT ExtVT = (NumElts == 16)? MVT::v16i32 : MVT::v8i64;
13205 In = DAG.getNode(ISD::SIGN_EXTEND, DL, ExtVT, In);
13210 DAG.getConstant(APInt::getSignBit(InVT.getScalarSizeInBits()), DL, InVT);
13211 SDValue And = DAG.getNode(ISD::AND, DL, InVT, OneV, In);
13212 return DAG.getNode(X86ISD::TESTM, DL, VT, And, And);
13215 // vpmovqb/w/d, vpmovdb/w, vpmovwb
13216 if (Subtarget->hasAVX512()) {
13217 // word to byte only under BWI
13218 if (InVT == MVT::v16i16 && !Subtarget->hasBWI()) // v16i16 -> v16i8
13219 return DAG.getNode(X86ISD::VTRUNC, DL, VT,
13220 DAG.getNode(X86ISD::VSEXT, DL, MVT::v16i32, In));
13221 return DAG.getNode(X86ISD::VTRUNC, DL, VT, In);
13223 if ((VT == MVT::v4i32) && (InVT == MVT::v4i64)) {
13224 // On AVX2, v4i64 -> v4i32 becomes VPERMD.
13225 if (Subtarget->hasInt256()) {
13226 static const int ShufMask[] = {0, 2, 4, 6, -1, -1, -1, -1};
13227 In = DAG.getBitcast(MVT::v8i32, In);
13228 In = DAG.getVectorShuffle(MVT::v8i32, DL, In, DAG.getUNDEF(MVT::v8i32),
13230 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, In,
13231 DAG.getIntPtrConstant(0, DL));
13234 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
13235 DAG.getIntPtrConstant(0, DL));
13236 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
13237 DAG.getIntPtrConstant(2, DL));
13238 OpLo = DAG.getBitcast(MVT::v4i32, OpLo);
13239 OpHi = DAG.getBitcast(MVT::v4i32, OpHi);
13240 static const int ShufMask[] = {0, 2, 4, 6};
13241 return DAG.getVectorShuffle(VT, DL, OpLo, OpHi, ShufMask);
13244 if ((VT == MVT::v8i16) && (InVT == MVT::v8i32)) {
13245 // On AVX2, v8i32 -> v8i16 becomed PSHUFB.
13246 if (Subtarget->hasInt256()) {
13247 In = DAG.getBitcast(MVT::v32i8, In);
13249 SmallVector<SDValue,32> pshufbMask;
13250 for (unsigned i = 0; i < 2; ++i) {
13251 pshufbMask.push_back(DAG.getConstant(0x0, DL, MVT::i8));
13252 pshufbMask.push_back(DAG.getConstant(0x1, DL, MVT::i8));
13253 pshufbMask.push_back(DAG.getConstant(0x4, DL, MVT::i8));
13254 pshufbMask.push_back(DAG.getConstant(0x5, DL, MVT::i8));
13255 pshufbMask.push_back(DAG.getConstant(0x8, DL, MVT::i8));
13256 pshufbMask.push_back(DAG.getConstant(0x9, DL, MVT::i8));
13257 pshufbMask.push_back(DAG.getConstant(0xc, DL, MVT::i8));
13258 pshufbMask.push_back(DAG.getConstant(0xd, DL, MVT::i8));
13259 for (unsigned j = 0; j < 8; ++j)
13260 pshufbMask.push_back(DAG.getConstant(0x80, DL, MVT::i8));
13262 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, pshufbMask);
13263 In = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v32i8, In, BV);
13264 In = DAG.getBitcast(MVT::v4i64, In);
13266 static const int ShufMask[] = {0, 2, -1, -1};
13267 In = DAG.getVectorShuffle(MVT::v4i64, DL, In, DAG.getUNDEF(MVT::v4i64),
13269 In = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
13270 DAG.getIntPtrConstant(0, DL));
13271 return DAG.getBitcast(VT, In);
13274 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
13275 DAG.getIntPtrConstant(0, DL));
13277 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
13278 DAG.getIntPtrConstant(4, DL));
13280 OpLo = DAG.getBitcast(MVT::v16i8, OpLo);
13281 OpHi = DAG.getBitcast(MVT::v16i8, OpHi);
13283 // The PSHUFB mask:
13284 static const int ShufMask1[] = {0, 1, 4, 5, 8, 9, 12, 13,
13285 -1, -1, -1, -1, -1, -1, -1, -1};
13287 SDValue Undef = DAG.getUNDEF(MVT::v16i8);
13288 OpLo = DAG.getVectorShuffle(MVT::v16i8, DL, OpLo, Undef, ShufMask1);
13289 OpHi = DAG.getVectorShuffle(MVT::v16i8, DL, OpHi, Undef, ShufMask1);
13291 OpLo = DAG.getBitcast(MVT::v4i32, OpLo);
13292 OpHi = DAG.getBitcast(MVT::v4i32, OpHi);
13294 // The MOVLHPS Mask:
13295 static const int ShufMask2[] = {0, 1, 4, 5};
13296 SDValue res = DAG.getVectorShuffle(MVT::v4i32, DL, OpLo, OpHi, ShufMask2);
13297 return DAG.getBitcast(MVT::v8i16, res);
13300 // Handle truncation of V256 to V128 using shuffles.
13301 if (!VT.is128BitVector() || !InVT.is256BitVector())
13304 assert(Subtarget->hasFp256() && "256-bit vector without AVX!");
13306 unsigned NumElems = VT.getVectorNumElements();
13307 MVT NVT = MVT::getVectorVT(VT.getVectorElementType(), NumElems * 2);
13309 SmallVector<int, 16> MaskVec(NumElems * 2, -1);
13310 // Prepare truncation shuffle mask
13311 for (unsigned i = 0; i != NumElems; ++i)
13312 MaskVec[i] = i * 2;
13313 SDValue V = DAG.getVectorShuffle(NVT, DL, DAG.getBitcast(NVT, In),
13314 DAG.getUNDEF(NVT), &MaskVec[0]);
13315 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, V,
13316 DAG.getIntPtrConstant(0, DL));
13319 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op,
13320 SelectionDAG &DAG) const {
13321 assert(!Op.getSimpleValueType().isVector());
13323 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
13324 /*IsSigned=*/ true, /*IsReplace=*/ false);
13325 SDValue FIST = Vals.first, StackSlot = Vals.second;
13326 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
13327 if (!FIST.getNode())
13330 if (StackSlot.getNode())
13331 // Load the result.
13332 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
13333 FIST, StackSlot, MachinePointerInfo(),
13334 false, false, false, 0);
13336 // The node is the result.
13340 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op,
13341 SelectionDAG &DAG) const {
13342 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
13343 /*IsSigned=*/ false, /*IsReplace=*/ false);
13344 SDValue FIST = Vals.first, StackSlot = Vals.second;
13345 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
13346 if (!FIST.getNode())
13349 if (StackSlot.getNode())
13350 // Load the result.
13351 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
13352 FIST, StackSlot, MachinePointerInfo(),
13353 false, false, false, 0);
13355 // The node is the result.
13359 static SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) {
13361 MVT VT = Op.getSimpleValueType();
13362 SDValue In = Op.getOperand(0);
13363 MVT SVT = In.getSimpleValueType();
13365 assert(SVT == MVT::v2f32 && "Only customize MVT::v2f32 type legalization!");
13367 return DAG.getNode(X86ISD::VFPEXT, DL, VT,
13368 DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v4f32,
13369 In, DAG.getUNDEF(SVT)));
13372 /// The only differences between FABS and FNEG are the mask and the logic op.
13373 /// FNEG also has a folding opportunity for FNEG(FABS(x)).
13374 static SDValue LowerFABSorFNEG(SDValue Op, SelectionDAG &DAG) {
13375 assert((Op.getOpcode() == ISD::FABS || Op.getOpcode() == ISD::FNEG) &&
13376 "Wrong opcode for lowering FABS or FNEG.");
13378 bool IsFABS = (Op.getOpcode() == ISD::FABS);
13380 // If this is a FABS and it has an FNEG user, bail out to fold the combination
13381 // into an FNABS. We'll lower the FABS after that if it is still in use.
13383 for (SDNode *User : Op->uses())
13384 if (User->getOpcode() == ISD::FNEG)
13388 MVT VT = Op.getSimpleValueType();
13390 // FIXME: Use function attribute "OptimizeForSize" and/or CodeGenOpt::Level to
13391 // decide if we should generate a 16-byte constant mask when we only need 4 or
13392 // 8 bytes for the scalar case.
13398 if (VT.isVector()) {
13400 EltVT = VT.getVectorElementType();
13401 NumElts = VT.getVectorNumElements();
13403 // There are no scalar bitwise logical SSE/AVX instructions, so we
13404 // generate a 16-byte vector constant and logic op even for the scalar case.
13405 // Using a 16-byte mask allows folding the load of the mask with
13406 // the logic op, so it can save (~4 bytes) on code size.
13407 LogicVT = (VT == MVT::f64) ? MVT::v2f64 : MVT::v4f32;
13409 NumElts = (VT == MVT::f64) ? 2 : 4;
13412 unsigned EltBits = EltVT.getSizeInBits();
13413 LLVMContext *Context = DAG.getContext();
13414 // For FABS, mask is 0x7f...; for FNEG, mask is 0x80...
13416 IsFABS ? APInt::getSignedMaxValue(EltBits) : APInt::getSignBit(EltBits);
13417 Constant *C = ConstantInt::get(*Context, MaskElt);
13418 C = ConstantVector::getSplat(NumElts, C);
13419 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13420 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy(DAG.getDataLayout()));
13421 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
13423 DAG.getLoad(LogicVT, dl, DAG.getEntryNode(), CPIdx,
13424 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()),
13425 false, false, false, Alignment);
13427 SDValue Op0 = Op.getOperand(0);
13428 bool IsFNABS = !IsFABS && (Op0.getOpcode() == ISD::FABS);
13430 IsFABS ? X86ISD::FAND : IsFNABS ? X86ISD::FOR : X86ISD::FXOR;
13431 SDValue Operand = IsFNABS ? Op0.getOperand(0) : Op0;
13434 return DAG.getNode(LogicOp, dl, LogicVT, Operand, Mask);
13436 // For the scalar case extend to a 128-bit vector, perform the logic op,
13437 // and extract the scalar result back out.
13438 Operand = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LogicVT, Operand);
13439 SDValue LogicNode = DAG.getNode(LogicOp, dl, LogicVT, Operand, Mask);
13440 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, LogicNode,
13441 DAG.getIntPtrConstant(0, dl));
13444 static SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) {
13445 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13446 LLVMContext *Context = DAG.getContext();
13447 SDValue Op0 = Op.getOperand(0);
13448 SDValue Op1 = Op.getOperand(1);
13450 MVT VT = Op.getSimpleValueType();
13451 MVT SrcVT = Op1.getSimpleValueType();
13453 // If second operand is smaller, extend it first.
13454 if (SrcVT.bitsLT(VT)) {
13455 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
13458 // And if it is bigger, shrink it first.
13459 if (SrcVT.bitsGT(VT)) {
13460 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1, dl));
13464 // At this point the operands and the result should have the same
13465 // type, and that won't be f80 since that is not custom lowered.
13467 const fltSemantics &Sem =
13468 VT == MVT::f64 ? APFloat::IEEEdouble : APFloat::IEEEsingle;
13469 const unsigned SizeInBits = VT.getSizeInBits();
13471 SmallVector<Constant *, 4> CV(
13472 VT == MVT::f64 ? 2 : 4,
13473 ConstantFP::get(*Context, APFloat(Sem, APInt(SizeInBits, 0))));
13475 // First, clear all bits but the sign bit from the second operand (sign).
13476 CV[0] = ConstantFP::get(*Context,
13477 APFloat(Sem, APInt::getHighBitsSet(SizeInBits, 1)));
13478 Constant *C = ConstantVector::get(CV);
13479 auto PtrVT = TLI.getPointerTy(DAG.getDataLayout());
13480 SDValue CPIdx = DAG.getConstantPool(C, PtrVT, 16);
13482 // Perform all logic operations as 16-byte vectors because there are no
13483 // scalar FP logic instructions in SSE. This allows load folding of the
13484 // constants into the logic instructions.
13485 MVT LogicVT = (VT == MVT::f64) ? MVT::v2f64 : MVT::v4f32;
13487 DAG.getLoad(LogicVT, dl, DAG.getEntryNode(), CPIdx,
13488 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()),
13489 false, false, false, 16);
13490 Op1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LogicVT, Op1);
13491 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, LogicVT, Op1, Mask1);
13493 // Next, clear the sign bit from the first operand (magnitude).
13494 // If it's a constant, we can clear it here.
13495 if (ConstantFPSDNode *Op0CN = dyn_cast<ConstantFPSDNode>(Op0)) {
13496 APFloat APF = Op0CN->getValueAPF();
13497 // If the magnitude is a positive zero, the sign bit alone is enough.
13498 if (APF.isPosZero())
13499 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SrcVT, SignBit,
13500 DAG.getIntPtrConstant(0, dl));
13502 CV[0] = ConstantFP::get(*Context, APF);
13504 CV[0] = ConstantFP::get(
13506 APFloat(Sem, APInt::getLowBitsSet(SizeInBits, SizeInBits - 1)));
13508 C = ConstantVector::get(CV);
13509 CPIdx = DAG.getConstantPool(C, PtrVT, 16);
13511 DAG.getLoad(LogicVT, dl, DAG.getEntryNode(), CPIdx,
13512 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()),
13513 false, false, false, 16);
13514 // If the magnitude operand wasn't a constant, we need to AND out the sign.
13515 if (!isa<ConstantFPSDNode>(Op0)) {
13516 Op0 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LogicVT, Op0);
13517 Val = DAG.getNode(X86ISD::FAND, dl, LogicVT, Op0, Val);
13519 // OR the magnitude value with the sign bit.
13520 Val = DAG.getNode(X86ISD::FOR, dl, LogicVT, Val, SignBit);
13521 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SrcVT, Val,
13522 DAG.getIntPtrConstant(0, dl));
13525 static SDValue LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) {
13526 SDValue N0 = Op.getOperand(0);
13528 MVT VT = Op.getSimpleValueType();
13530 // Lower ISD::FGETSIGN to (AND (X86ISD::FGETSIGNx86 ...) 1).
13531 SDValue xFGETSIGN = DAG.getNode(X86ISD::FGETSIGNx86, dl, VT, N0,
13532 DAG.getConstant(1, dl, VT));
13533 return DAG.getNode(ISD::AND, dl, VT, xFGETSIGN, DAG.getConstant(1, dl, VT));
13536 // Check whether an OR'd tree is PTEST-able.
13537 static SDValue LowerVectorAllZeroTest(SDValue Op, const X86Subtarget *Subtarget,
13538 SelectionDAG &DAG) {
13539 assert(Op.getOpcode() == ISD::OR && "Only check OR'd tree.");
13541 if (!Subtarget->hasSSE41())
13544 if (!Op->hasOneUse())
13547 SDNode *N = Op.getNode();
13550 SmallVector<SDValue, 8> Opnds;
13551 DenseMap<SDValue, unsigned> VecInMap;
13552 SmallVector<SDValue, 8> VecIns;
13553 EVT VT = MVT::Other;
13555 // Recognize a special case where a vector is casted into wide integer to
13557 Opnds.push_back(N->getOperand(0));
13558 Opnds.push_back(N->getOperand(1));
13560 for (unsigned Slot = 0, e = Opnds.size(); Slot < e; ++Slot) {
13561 SmallVectorImpl<SDValue>::const_iterator I = Opnds.begin() + Slot;
13562 // BFS traverse all OR'd operands.
13563 if (I->getOpcode() == ISD::OR) {
13564 Opnds.push_back(I->getOperand(0));
13565 Opnds.push_back(I->getOperand(1));
13566 // Re-evaluate the number of nodes to be traversed.
13567 e += 2; // 2 more nodes (LHS and RHS) are pushed.
13571 // Quit if a non-EXTRACT_VECTOR_ELT
13572 if (I->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
13575 // Quit if without a constant index.
13576 SDValue Idx = I->getOperand(1);
13577 if (!isa<ConstantSDNode>(Idx))
13580 SDValue ExtractedFromVec = I->getOperand(0);
13581 DenseMap<SDValue, unsigned>::iterator M = VecInMap.find(ExtractedFromVec);
13582 if (M == VecInMap.end()) {
13583 VT = ExtractedFromVec.getValueType();
13584 // Quit if not 128/256-bit vector.
13585 if (!VT.is128BitVector() && !VT.is256BitVector())
13587 // Quit if not the same type.
13588 if (VecInMap.begin() != VecInMap.end() &&
13589 VT != VecInMap.begin()->first.getValueType())
13591 M = VecInMap.insert(std::make_pair(ExtractedFromVec, 0)).first;
13592 VecIns.push_back(ExtractedFromVec);
13594 M->second |= 1U << cast<ConstantSDNode>(Idx)->getZExtValue();
13597 assert((VT.is128BitVector() || VT.is256BitVector()) &&
13598 "Not extracted from 128-/256-bit vector.");
13600 unsigned FullMask = (1U << VT.getVectorNumElements()) - 1U;
13602 for (DenseMap<SDValue, unsigned>::const_iterator
13603 I = VecInMap.begin(), E = VecInMap.end(); I != E; ++I) {
13604 // Quit if not all elements are used.
13605 if (I->second != FullMask)
13609 MVT TestVT = VT.is128BitVector() ? MVT::v2i64 : MVT::v4i64;
13611 // Cast all vectors into TestVT for PTEST.
13612 for (unsigned i = 0, e = VecIns.size(); i < e; ++i)
13613 VecIns[i] = DAG.getBitcast(TestVT, VecIns[i]);
13615 // If more than one full vectors are evaluated, OR them first before PTEST.
13616 for (unsigned Slot = 0, e = VecIns.size(); e - Slot > 1; Slot += 2, e += 1) {
13617 // Each iteration will OR 2 nodes and append the result until there is only
13618 // 1 node left, i.e. the final OR'd value of all vectors.
13619 SDValue LHS = VecIns[Slot];
13620 SDValue RHS = VecIns[Slot + 1];
13621 VecIns.push_back(DAG.getNode(ISD::OR, DL, TestVT, LHS, RHS));
13624 return DAG.getNode(X86ISD::PTEST, DL, MVT::i32,
13625 VecIns.back(), VecIns.back());
13628 /// \brief return true if \c Op has a use that doesn't just read flags.
13629 static bool hasNonFlagsUse(SDValue Op) {
13630 for (SDNode::use_iterator UI = Op->use_begin(), UE = Op->use_end(); UI != UE;
13632 SDNode *User = *UI;
13633 unsigned UOpNo = UI.getOperandNo();
13634 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
13635 // Look pass truncate.
13636 UOpNo = User->use_begin().getOperandNo();
13637 User = *User->use_begin();
13640 if (User->getOpcode() != ISD::BRCOND && User->getOpcode() != ISD::SETCC &&
13641 !(User->getOpcode() == ISD::SELECT && UOpNo == 0))
13647 /// Emit nodes that will be selected as "test Op0,Op0", or something
13649 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC, SDLoc dl,
13650 SelectionDAG &DAG) const {
13651 if (Op.getValueType() == MVT::i1) {
13652 SDValue ExtOp = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i8, Op);
13653 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, ExtOp,
13654 DAG.getConstant(0, dl, MVT::i8));
13656 // CF and OF aren't always set the way we want. Determine which
13657 // of these we need.
13658 bool NeedCF = false;
13659 bool NeedOF = false;
13662 case X86::COND_A: case X86::COND_AE:
13663 case X86::COND_B: case X86::COND_BE:
13666 case X86::COND_G: case X86::COND_GE:
13667 case X86::COND_L: case X86::COND_LE:
13668 case X86::COND_O: case X86::COND_NO: {
13669 // Check if we really need to set the
13670 // Overflow flag. If NoSignedWrap is present
13671 // that is not actually needed.
13672 switch (Op->getOpcode()) {
13677 const auto *BinNode = cast<BinaryWithFlagsSDNode>(Op.getNode());
13678 if (BinNode->Flags.hasNoSignedWrap())
13688 // See if we can use the EFLAGS value from the operand instead of
13689 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
13690 // we prove that the arithmetic won't overflow, we can't use OF or CF.
13691 if (Op.getResNo() != 0 || NeedOF || NeedCF) {
13692 // Emit a CMP with 0, which is the TEST pattern.
13693 //if (Op.getValueType() == MVT::i1)
13694 // return DAG.getNode(X86ISD::CMP, dl, MVT::i1, Op,
13695 // DAG.getConstant(0, MVT::i1));
13696 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
13697 DAG.getConstant(0, dl, Op.getValueType()));
13699 unsigned Opcode = 0;
13700 unsigned NumOperands = 0;
13702 // Truncate operations may prevent the merge of the SETCC instruction
13703 // and the arithmetic instruction before it. Attempt to truncate the operands
13704 // of the arithmetic instruction and use a reduced bit-width instruction.
13705 bool NeedTruncation = false;
13706 SDValue ArithOp = Op;
13707 if (Op->getOpcode() == ISD::TRUNCATE && Op->hasOneUse()) {
13708 SDValue Arith = Op->getOperand(0);
13709 // Both the trunc and the arithmetic op need to have one user each.
13710 if (Arith->hasOneUse())
13711 switch (Arith.getOpcode()) {
13718 NeedTruncation = true;
13724 // NOTICE: In the code below we use ArithOp to hold the arithmetic operation
13725 // which may be the result of a CAST. We use the variable 'Op', which is the
13726 // non-casted variable when we check for possible users.
13727 switch (ArithOp.getOpcode()) {
13729 // Due to an isel shortcoming, be conservative if this add is likely to be
13730 // selected as part of a load-modify-store instruction. When the root node
13731 // in a match is a store, isel doesn't know how to remap non-chain non-flag
13732 // uses of other nodes in the match, such as the ADD in this case. This
13733 // leads to the ADD being left around and reselected, with the result being
13734 // two adds in the output. Alas, even if none our users are stores, that
13735 // doesn't prove we're O.K. Ergo, if we have any parents that aren't
13736 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require
13737 // climbing the DAG back to the root, and it doesn't seem to be worth the
13739 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
13740 UE = Op.getNode()->use_end(); UI != UE; ++UI)
13741 if (UI->getOpcode() != ISD::CopyToReg &&
13742 UI->getOpcode() != ISD::SETCC &&
13743 UI->getOpcode() != ISD::STORE)
13746 if (ConstantSDNode *C =
13747 dyn_cast<ConstantSDNode>(ArithOp.getNode()->getOperand(1))) {
13748 // An add of one will be selected as an INC.
13749 if (C->isOne() && !Subtarget->slowIncDec()) {
13750 Opcode = X86ISD::INC;
13755 // An add of negative one (subtract of one) will be selected as a DEC.
13756 if (C->isAllOnesValue() && !Subtarget->slowIncDec()) {
13757 Opcode = X86ISD::DEC;
13763 // Otherwise use a regular EFLAGS-setting add.
13764 Opcode = X86ISD::ADD;
13769 // If we have a constant logical shift that's only used in a comparison
13770 // against zero turn it into an equivalent AND. This allows turning it into
13771 // a TEST instruction later.
13772 if ((X86CC == X86::COND_E || X86CC == X86::COND_NE) && Op->hasOneUse() &&
13773 isa<ConstantSDNode>(Op->getOperand(1)) && !hasNonFlagsUse(Op)) {
13774 EVT VT = Op.getValueType();
13775 unsigned BitWidth = VT.getSizeInBits();
13776 unsigned ShAmt = Op->getConstantOperandVal(1);
13777 if (ShAmt >= BitWidth) // Avoid undefined shifts.
13779 APInt Mask = ArithOp.getOpcode() == ISD::SRL
13780 ? APInt::getHighBitsSet(BitWidth, BitWidth - ShAmt)
13781 : APInt::getLowBitsSet(BitWidth, BitWidth - ShAmt);
13782 if (!Mask.isSignedIntN(32)) // Avoid large immediates.
13784 SDValue New = DAG.getNode(ISD::AND, dl, VT, Op->getOperand(0),
13785 DAG.getConstant(Mask, dl, VT));
13786 DAG.ReplaceAllUsesWith(Op, New);
13792 // If the primary and result isn't used, don't bother using X86ISD::AND,
13793 // because a TEST instruction will be better.
13794 if (!hasNonFlagsUse(Op))
13800 // Due to the ISEL shortcoming noted above, be conservative if this op is
13801 // likely to be selected as part of a load-modify-store instruction.
13802 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
13803 UE = Op.getNode()->use_end(); UI != UE; ++UI)
13804 if (UI->getOpcode() == ISD::STORE)
13807 // Otherwise use a regular EFLAGS-setting instruction.
13808 switch (ArithOp.getOpcode()) {
13809 default: llvm_unreachable("unexpected operator!");
13810 case ISD::SUB: Opcode = X86ISD::SUB; break;
13811 case ISD::XOR: Opcode = X86ISD::XOR; break;
13812 case ISD::AND: Opcode = X86ISD::AND; break;
13814 if (!NeedTruncation && (X86CC == X86::COND_E || X86CC == X86::COND_NE)) {
13815 SDValue EFLAGS = LowerVectorAllZeroTest(Op, Subtarget, DAG);
13816 if (EFLAGS.getNode())
13819 Opcode = X86ISD::OR;
13833 return SDValue(Op.getNode(), 1);
13839 // If we found that truncation is beneficial, perform the truncation and
13841 if (NeedTruncation) {
13842 EVT VT = Op.getValueType();
13843 SDValue WideVal = Op->getOperand(0);
13844 EVT WideVT = WideVal.getValueType();
13845 unsigned ConvertedOp = 0;
13846 // Use a target machine opcode to prevent further DAGCombine
13847 // optimizations that may separate the arithmetic operations
13848 // from the setcc node.
13849 switch (WideVal.getOpcode()) {
13851 case ISD::ADD: ConvertedOp = X86ISD::ADD; break;
13852 case ISD::SUB: ConvertedOp = X86ISD::SUB; break;
13853 case ISD::AND: ConvertedOp = X86ISD::AND; break;
13854 case ISD::OR: ConvertedOp = X86ISD::OR; break;
13855 case ISD::XOR: ConvertedOp = X86ISD::XOR; break;
13859 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13860 if (TLI.isOperationLegal(WideVal.getOpcode(), WideVT)) {
13861 SDValue V0 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(0));
13862 SDValue V1 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(1));
13863 Op = DAG.getNode(ConvertedOp, dl, VT, V0, V1);
13869 // Emit a CMP with 0, which is the TEST pattern.
13870 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
13871 DAG.getConstant(0, dl, Op.getValueType()));
13873 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
13874 SmallVector<SDValue, 4> Ops(Op->op_begin(), Op->op_begin() + NumOperands);
13876 SDValue New = DAG.getNode(Opcode, dl, VTs, Ops);
13877 DAG.ReplaceAllUsesWith(Op, New);
13878 return SDValue(New.getNode(), 1);
13881 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
13883 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
13884 SDLoc dl, SelectionDAG &DAG) const {
13885 if (isNullConstant(Op1))
13886 return EmitTest(Op0, X86CC, dl, DAG);
13888 assert(!(isa<ConstantSDNode>(Op1) && Op0.getValueType() == MVT::i1) &&
13889 "Unexpected comparison operation for MVT::i1 operands");
13891 if ((Op0.getValueType() == MVT::i8 || Op0.getValueType() == MVT::i16 ||
13892 Op0.getValueType() == MVT::i32 || Op0.getValueType() == MVT::i64)) {
13893 // Do the comparison at i32 if it's smaller, besides the Atom case.
13894 // This avoids subregister aliasing issues. Keep the smaller reference
13895 // if we're optimizing for size, however, as that'll allow better folding
13896 // of memory operations.
13897 if (Op0.getValueType() != MVT::i32 && Op0.getValueType() != MVT::i64 &&
13898 !DAG.getMachineFunction().getFunction()->optForMinSize() &&
13899 !Subtarget->isAtom()) {
13900 unsigned ExtendOp =
13901 isX86CCUnsigned(X86CC) ? ISD::ZERO_EXTEND : ISD::SIGN_EXTEND;
13902 Op0 = DAG.getNode(ExtendOp, dl, MVT::i32, Op0);
13903 Op1 = DAG.getNode(ExtendOp, dl, MVT::i32, Op1);
13905 // Use SUB instead of CMP to enable CSE between SUB and CMP.
13906 SDVTList VTs = DAG.getVTList(Op0.getValueType(), MVT::i32);
13907 SDValue Sub = DAG.getNode(X86ISD::SUB, dl, VTs,
13909 return SDValue(Sub.getNode(), 1);
13911 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
13914 /// Convert a comparison if required by the subtarget.
13915 SDValue X86TargetLowering::ConvertCmpIfNecessary(SDValue Cmp,
13916 SelectionDAG &DAG) const {
13917 // If the subtarget does not support the FUCOMI instruction, floating-point
13918 // comparisons have to be converted.
13919 if (Subtarget->hasCMov() ||
13920 Cmp.getOpcode() != X86ISD::CMP ||
13921 !Cmp.getOperand(0).getValueType().isFloatingPoint() ||
13922 !Cmp.getOperand(1).getValueType().isFloatingPoint())
13925 // The instruction selector will select an FUCOM instruction instead of
13926 // FUCOMI, which writes the comparison result to FPSW instead of EFLAGS. Hence
13927 // build an SDNode sequence that transfers the result from FPSW into EFLAGS:
13928 // (X86sahf (trunc (srl (X86fp_stsw (trunc (X86cmp ...)), 8))))
13930 SDValue TruncFPSW = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, Cmp);
13931 SDValue FNStSW = DAG.getNode(X86ISD::FNSTSW16r, dl, MVT::i16, TruncFPSW);
13932 SDValue Srl = DAG.getNode(ISD::SRL, dl, MVT::i16, FNStSW,
13933 DAG.getConstant(8, dl, MVT::i8));
13934 SDValue TruncSrl = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Srl);
13936 // Some 64-bit targets lack SAHF support, but they do support FCOMI.
13937 assert(Subtarget->hasLAHFSAHF() && "Target doesn't support SAHF or FCOMI?");
13938 return DAG.getNode(X86ISD::SAHF, dl, MVT::i32, TruncSrl);
13941 /// The minimum architected relative accuracy is 2^-12. We need one
13942 /// Newton-Raphson step to have a good float result (24 bits of precision).
13943 SDValue X86TargetLowering::getRsqrtEstimate(SDValue Op,
13944 DAGCombinerInfo &DCI,
13945 unsigned &RefinementSteps,
13946 bool &UseOneConstNR) const {
13947 EVT VT = Op.getValueType();
13948 const char *RecipOp;
13950 // SSE1 has rsqrtss and rsqrtps. AVX adds a 256-bit variant for rsqrtps.
13951 // TODO: Add support for AVX512 (v16f32).
13952 // It is likely not profitable to do this for f64 because a double-precision
13953 // rsqrt estimate with refinement on x86 prior to FMA requires at least 16
13954 // instructions: convert to single, rsqrtss, convert back to double, refine
13955 // (3 steps = at least 13 insts). If an 'rsqrtsd' variant was added to the ISA
13956 // along with FMA, this could be a throughput win.
13957 if (VT == MVT::f32 && Subtarget->hasSSE1())
13959 else if ((VT == MVT::v4f32 && Subtarget->hasSSE1()) ||
13960 (VT == MVT::v8f32 && Subtarget->hasAVX()))
13961 RecipOp = "vec-sqrtf";
13965 TargetRecip Recips = DCI.DAG.getTarget().Options.Reciprocals;
13966 if (!Recips.isEnabled(RecipOp))
13969 RefinementSteps = Recips.getRefinementSteps(RecipOp);
13970 UseOneConstNR = false;
13971 return DCI.DAG.getNode(X86ISD::FRSQRT, SDLoc(Op), VT, Op);
13974 /// The minimum architected relative accuracy is 2^-12. We need one
13975 /// Newton-Raphson step to have a good float result (24 bits of precision).
13976 SDValue X86TargetLowering::getRecipEstimate(SDValue Op,
13977 DAGCombinerInfo &DCI,
13978 unsigned &RefinementSteps) const {
13979 EVT VT = Op.getValueType();
13980 const char *RecipOp;
13982 // SSE1 has rcpss and rcpps. AVX adds a 256-bit variant for rcpps.
13983 // TODO: Add support for AVX512 (v16f32).
13984 // It is likely not profitable to do this for f64 because a double-precision
13985 // reciprocal estimate with refinement on x86 prior to FMA requires
13986 // 15 instructions: convert to single, rcpss, convert back to double, refine
13987 // (3 steps = 12 insts). If an 'rcpsd' variant was added to the ISA
13988 // along with FMA, this could be a throughput win.
13989 if (VT == MVT::f32 && Subtarget->hasSSE1())
13991 else if ((VT == MVT::v4f32 && Subtarget->hasSSE1()) ||
13992 (VT == MVT::v8f32 && Subtarget->hasAVX()))
13993 RecipOp = "vec-divf";
13997 TargetRecip Recips = DCI.DAG.getTarget().Options.Reciprocals;
13998 if (!Recips.isEnabled(RecipOp))
14001 RefinementSteps = Recips.getRefinementSteps(RecipOp);
14002 return DCI.DAG.getNode(X86ISD::FRCP, SDLoc(Op), VT, Op);
14005 /// If we have at least two divisions that use the same divisor, convert to
14006 /// multplication by a reciprocal. This may need to be adjusted for a given
14007 /// CPU if a division's cost is not at least twice the cost of a multiplication.
14008 /// This is because we still need one division to calculate the reciprocal and
14009 /// then we need two multiplies by that reciprocal as replacements for the
14010 /// original divisions.
14011 unsigned X86TargetLowering::combineRepeatedFPDivisors() const {
14015 /// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node
14016 /// if it's possible.
14017 SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC,
14018 SDLoc dl, SelectionDAG &DAG) const {
14019 SDValue Op0 = And.getOperand(0);
14020 SDValue Op1 = And.getOperand(1);
14021 if (Op0.getOpcode() == ISD::TRUNCATE)
14022 Op0 = Op0.getOperand(0);
14023 if (Op1.getOpcode() == ISD::TRUNCATE)
14024 Op1 = Op1.getOperand(0);
14027 if (Op1.getOpcode() == ISD::SHL)
14028 std::swap(Op0, Op1);
14029 if (Op0.getOpcode() == ISD::SHL) {
14030 if (isOneConstant(Op0.getOperand(0))) {
14031 // If we looked past a truncate, check that it's only truncating away
14033 unsigned BitWidth = Op0.getValueSizeInBits();
14034 unsigned AndBitWidth = And.getValueSizeInBits();
14035 if (BitWidth > AndBitWidth) {
14037 DAG.computeKnownBits(Op0, Zeros, Ones);
14038 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth)
14042 RHS = Op0.getOperand(1);
14044 } else if (Op1.getOpcode() == ISD::Constant) {
14045 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1);
14046 uint64_t AndRHSVal = AndRHS->getZExtValue();
14047 SDValue AndLHS = Op0;
14049 if (AndRHSVal == 1 && AndLHS.getOpcode() == ISD::SRL) {
14050 LHS = AndLHS.getOperand(0);
14051 RHS = AndLHS.getOperand(1);
14054 // Use BT if the immediate can't be encoded in a TEST instruction.
14055 if (!isUInt<32>(AndRHSVal) && isPowerOf2_64(AndRHSVal)) {
14057 RHS = DAG.getConstant(Log2_64_Ceil(AndRHSVal), dl, LHS.getValueType());
14061 if (LHS.getNode()) {
14062 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT
14063 // instruction. Since the shift amount is in-range-or-undefined, we know
14064 // that doing a bittest on the i32 value is ok. We extend to i32 because
14065 // the encoding for the i16 version is larger than the i32 version.
14066 // Also promote i16 to i32 for performance / code size reason.
14067 if (LHS.getValueType() == MVT::i8 ||
14068 LHS.getValueType() == MVT::i16)
14069 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
14071 // If the operand types disagree, extend the shift amount to match. Since
14072 // BT ignores high bits (like shifts) we can use anyextend.
14073 if (LHS.getValueType() != RHS.getValueType())
14074 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
14076 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
14077 X86::CondCode Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
14078 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
14079 DAG.getConstant(Cond, dl, MVT::i8), BT);
14085 /// \brief - Turns an ISD::CondCode into a value suitable for SSE floating point
14087 static int translateX86FSETCC(ISD::CondCode SetCCOpcode, SDValue &Op0,
14092 // SSE Condition code mapping:
14101 switch (SetCCOpcode) {
14102 default: llvm_unreachable("Unexpected SETCC condition");
14104 case ISD::SETEQ: SSECC = 0; break;
14106 case ISD::SETGT: Swap = true; // Fallthrough
14108 case ISD::SETOLT: SSECC = 1; break;
14110 case ISD::SETGE: Swap = true; // Fallthrough
14112 case ISD::SETOLE: SSECC = 2; break;
14113 case ISD::SETUO: SSECC = 3; break;
14115 case ISD::SETNE: SSECC = 4; break;
14116 case ISD::SETULE: Swap = true; // Fallthrough
14117 case ISD::SETUGE: SSECC = 5; break;
14118 case ISD::SETULT: Swap = true; // Fallthrough
14119 case ISD::SETUGT: SSECC = 6; break;
14120 case ISD::SETO: SSECC = 7; break;
14122 case ISD::SETONE: SSECC = 8; break;
14125 std::swap(Op0, Op1);
14130 // Lower256IntVSETCC - Break a VSETCC 256-bit integer VSETCC into two new 128
14131 // ones, and then concatenate the result back.
14132 static SDValue Lower256IntVSETCC(SDValue Op, SelectionDAG &DAG) {
14133 MVT VT = Op.getSimpleValueType();
14135 assert(VT.is256BitVector() && Op.getOpcode() == ISD::SETCC &&
14136 "Unsupported value type for operation");
14138 unsigned NumElems = VT.getVectorNumElements();
14140 SDValue CC = Op.getOperand(2);
14142 // Extract the LHS vectors
14143 SDValue LHS = Op.getOperand(0);
14144 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
14145 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
14147 // Extract the RHS vectors
14148 SDValue RHS = Op.getOperand(1);
14149 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
14150 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
14152 // Issue the operation on the smaller types and concatenate the result back
14153 MVT EltVT = VT.getVectorElementType();
14154 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
14155 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
14156 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1, CC),
14157 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC));
14160 static SDValue LowerBoolVSETCC_AVX512(SDValue Op, SelectionDAG &DAG) {
14161 SDValue Op0 = Op.getOperand(0);
14162 SDValue Op1 = Op.getOperand(1);
14163 SDValue CC = Op.getOperand(2);
14164 MVT VT = Op.getSimpleValueType();
14167 assert(Op0.getSimpleValueType().getVectorElementType() == MVT::i1 &&
14168 "Unexpected type for boolean compare operation");
14169 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
14170 SDValue NotOp0 = DAG.getNode(ISD::XOR, dl, VT, Op0,
14171 DAG.getConstant(-1, dl, VT));
14172 SDValue NotOp1 = DAG.getNode(ISD::XOR, dl, VT, Op1,
14173 DAG.getConstant(-1, dl, VT));
14174 switch (SetCCOpcode) {
14175 default: llvm_unreachable("Unexpected SETCC condition");
14177 // (x == y) -> ~(x ^ y)
14178 return DAG.getNode(ISD::XOR, dl, VT,
14179 DAG.getNode(ISD::XOR, dl, VT, Op0, Op1),
14180 DAG.getConstant(-1, dl, VT));
14182 // (x != y) -> (x ^ y)
14183 return DAG.getNode(ISD::XOR, dl, VT, Op0, Op1);
14186 // (x > y) -> (x & ~y)
14187 return DAG.getNode(ISD::AND, dl, VT, Op0, NotOp1);
14190 // (x < y) -> (~x & y)
14191 return DAG.getNode(ISD::AND, dl, VT, NotOp0, Op1);
14194 // (x <= y) -> (~x | y)
14195 return DAG.getNode(ISD::OR, dl, VT, NotOp0, Op1);
14198 // (x >=y) -> (x | ~y)
14199 return DAG.getNode(ISD::OR, dl, VT, Op0, NotOp1);
14203 static SDValue LowerIntVSETCC_AVX512(SDValue Op, SelectionDAG &DAG,
14204 const X86Subtarget *Subtarget) {
14205 SDValue Op0 = Op.getOperand(0);
14206 SDValue Op1 = Op.getOperand(1);
14207 SDValue CC = Op.getOperand(2);
14208 MVT VT = Op.getSimpleValueType();
14211 assert(Op0.getSimpleValueType().getVectorElementType().getSizeInBits() >= 8 &&
14212 Op.getSimpleValueType().getVectorElementType() == MVT::i1 &&
14213 "Cannot set masked compare for this operation");
14215 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
14217 bool Unsigned = false;
14220 switch (SetCCOpcode) {
14221 default: llvm_unreachable("Unexpected SETCC condition");
14222 case ISD::SETNE: SSECC = 4; break;
14223 case ISD::SETEQ: Opc = X86ISD::PCMPEQM; break;
14224 case ISD::SETUGT: SSECC = 6; Unsigned = true; break;
14225 case ISD::SETLT: Swap = true; //fall-through
14226 case ISD::SETGT: Opc = X86ISD::PCMPGTM; break;
14227 case ISD::SETULT: SSECC = 1; Unsigned = true; break;
14228 case ISD::SETUGE: SSECC = 5; Unsigned = true; break; //NLT
14229 case ISD::SETGE: Swap = true; SSECC = 2; break; // LE + swap
14230 case ISD::SETULE: Unsigned = true; //fall-through
14231 case ISD::SETLE: SSECC = 2; break;
14235 std::swap(Op0, Op1);
14237 return DAG.getNode(Opc, dl, VT, Op0, Op1);
14238 Opc = Unsigned ? X86ISD::CMPMU: X86ISD::CMPM;
14239 return DAG.getNode(Opc, dl, VT, Op0, Op1,
14240 DAG.getConstant(SSECC, dl, MVT::i8));
14243 /// \brief Try to turn a VSETULT into a VSETULE by modifying its second
14244 /// operand \p Op1. If non-trivial (for example because it's not constant)
14245 /// return an empty value.
14246 static SDValue ChangeVSETULTtoVSETULE(SDLoc dl, SDValue Op1, SelectionDAG &DAG)
14248 BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(Op1.getNode());
14252 MVT VT = Op1.getSimpleValueType();
14253 MVT EVT = VT.getVectorElementType();
14254 unsigned n = VT.getVectorNumElements();
14255 SmallVector<SDValue, 8> ULTOp1;
14257 for (unsigned i = 0; i < n; ++i) {
14258 ConstantSDNode *Elt = dyn_cast<ConstantSDNode>(BV->getOperand(i));
14259 if (!Elt || Elt->isOpaque() || Elt->getSimpleValueType(0) != EVT)
14262 // Avoid underflow.
14263 APInt Val = Elt->getAPIntValue();
14267 ULTOp1.push_back(DAG.getConstant(Val - 1, dl, EVT));
14270 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, ULTOp1);
14273 static SDValue LowerVSETCC(SDValue Op, const X86Subtarget *Subtarget,
14274 SelectionDAG &DAG) {
14275 SDValue Op0 = Op.getOperand(0);
14276 SDValue Op1 = Op.getOperand(1);
14277 SDValue CC = Op.getOperand(2);
14278 MVT VT = Op.getSimpleValueType();
14279 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
14280 bool isFP = Op.getOperand(1).getSimpleValueType().isFloatingPoint();
14285 MVT EltVT = Op0.getSimpleValueType().getVectorElementType();
14286 assert(EltVT == MVT::f32 || EltVT == MVT::f64);
14289 unsigned SSECC = translateX86FSETCC(SetCCOpcode, Op0, Op1);
14290 unsigned Opc = X86ISD::CMPP;
14291 if (Subtarget->hasAVX512() && VT.getVectorElementType() == MVT::i1) {
14292 assert(VT.getVectorNumElements() <= 16);
14293 Opc = X86ISD::CMPM;
14295 // In the two special cases we can't handle, emit two comparisons.
14298 unsigned CombineOpc;
14299 if (SetCCOpcode == ISD::SETUEQ) {
14300 CC0 = 3; CC1 = 0; CombineOpc = ISD::OR;
14302 assert(SetCCOpcode == ISD::SETONE);
14303 CC0 = 7; CC1 = 4; CombineOpc = ISD::AND;
14306 SDValue Cmp0 = DAG.getNode(Opc, dl, VT, Op0, Op1,
14307 DAG.getConstant(CC0, dl, MVT::i8));
14308 SDValue Cmp1 = DAG.getNode(Opc, dl, VT, Op0, Op1,
14309 DAG.getConstant(CC1, dl, MVT::i8));
14310 return DAG.getNode(CombineOpc, dl, VT, Cmp0, Cmp1);
14312 // Handle all other FP comparisons here.
14313 return DAG.getNode(Opc, dl, VT, Op0, Op1,
14314 DAG.getConstant(SSECC, dl, MVT::i8));
14317 MVT VTOp0 = Op0.getSimpleValueType();
14318 assert(VTOp0 == Op1.getSimpleValueType() &&
14319 "Expected operands with same type!");
14320 assert(VT.getVectorNumElements() == VTOp0.getVectorNumElements() &&
14321 "Invalid number of packed elements for source and destination!");
14323 if (VT.is128BitVector() && VTOp0.is256BitVector()) {
14324 // On non-AVX512 targets, a vector of MVT::i1 is promoted by the type
14325 // legalizer to a wider vector type. In the case of 'vsetcc' nodes, the
14326 // legalizer firstly checks if the first operand in input to the setcc has
14327 // a legal type. If so, then it promotes the return type to that same type.
14328 // Otherwise, the return type is promoted to the 'next legal type' which,
14329 // for a vector of MVT::i1 is always a 128-bit integer vector type.
14331 // We reach this code only if the following two conditions are met:
14332 // 1. Both return type and operand type have been promoted to wider types
14333 // by the type legalizer.
14334 // 2. The original operand type has been promoted to a 256-bit vector.
14336 // Note that condition 2. only applies for AVX targets.
14337 SDValue NewOp = DAG.getSetCC(dl, VTOp0, Op0, Op1, SetCCOpcode);
14338 return DAG.getZExtOrTrunc(NewOp, dl, VT);
14341 // The non-AVX512 code below works under the assumption that source and
14342 // destination types are the same.
14343 assert((Subtarget->hasAVX512() || (VT == VTOp0)) &&
14344 "Value types for source and destination must be the same!");
14346 // Break 256-bit integer vector compare into smaller ones.
14347 if (VT.is256BitVector() && !Subtarget->hasInt256())
14348 return Lower256IntVSETCC(Op, DAG);
14350 MVT OpVT = Op1.getSimpleValueType();
14351 if (OpVT.getVectorElementType() == MVT::i1)
14352 return LowerBoolVSETCC_AVX512(Op, DAG);
14354 bool MaskResult = (VT.getVectorElementType() == MVT::i1);
14355 if (Subtarget->hasAVX512()) {
14356 if (Op1.getSimpleValueType().is512BitVector() ||
14357 (Subtarget->hasBWI() && Subtarget->hasVLX()) ||
14358 (MaskResult && OpVT.getVectorElementType().getSizeInBits() >= 32))
14359 return LowerIntVSETCC_AVX512(Op, DAG, Subtarget);
14361 // In AVX-512 architecture setcc returns mask with i1 elements,
14362 // But there is no compare instruction for i8 and i16 elements in KNL.
14363 // We are not talking about 512-bit operands in this case, these
14364 // types are illegal.
14366 (OpVT.getVectorElementType().getSizeInBits() < 32 &&
14367 OpVT.getVectorElementType().getSizeInBits() >= 8))
14368 return DAG.getNode(ISD::TRUNCATE, dl, VT,
14369 DAG.getNode(ISD::SETCC, dl, OpVT, Op0, Op1, CC));
14372 // Lower using XOP integer comparisons.
14373 if ((VT == MVT::v16i8 || VT == MVT::v8i16 ||
14374 VT == MVT::v4i32 || VT == MVT::v2i64) && Subtarget->hasXOP()) {
14375 // Translate compare code to XOP PCOM compare mode.
14376 unsigned CmpMode = 0;
14377 switch (SetCCOpcode) {
14378 default: llvm_unreachable("Unexpected SETCC condition");
14380 case ISD::SETLT: CmpMode = 0x00; break;
14382 case ISD::SETLE: CmpMode = 0x01; break;
14384 case ISD::SETGT: CmpMode = 0x02; break;
14386 case ISD::SETGE: CmpMode = 0x03; break;
14387 case ISD::SETEQ: CmpMode = 0x04; break;
14388 case ISD::SETNE: CmpMode = 0x05; break;
14391 // Are we comparing unsigned or signed integers?
14392 unsigned Opc = ISD::isUnsignedIntSetCC(SetCCOpcode)
14393 ? X86ISD::VPCOMU : X86ISD::VPCOM;
14395 return DAG.getNode(Opc, dl, VT, Op0, Op1,
14396 DAG.getConstant(CmpMode, dl, MVT::i8));
14399 // We are handling one of the integer comparisons here. Since SSE only has
14400 // GT and EQ comparisons for integer, swapping operands and multiple
14401 // operations may be required for some comparisons.
14403 bool Swap = false, Invert = false, FlipSigns = false, MinMax = false;
14404 bool Subus = false;
14406 switch (SetCCOpcode) {
14407 default: llvm_unreachable("Unexpected SETCC condition");
14408 case ISD::SETNE: Invert = true;
14409 case ISD::SETEQ: Opc = X86ISD::PCMPEQ; break;
14410 case ISD::SETLT: Swap = true;
14411 case ISD::SETGT: Opc = X86ISD::PCMPGT; break;
14412 case ISD::SETGE: Swap = true;
14413 case ISD::SETLE: Opc = X86ISD::PCMPGT;
14414 Invert = true; break;
14415 case ISD::SETULT: Swap = true;
14416 case ISD::SETUGT: Opc = X86ISD::PCMPGT;
14417 FlipSigns = true; break;
14418 case ISD::SETUGE: Swap = true;
14419 case ISD::SETULE: Opc = X86ISD::PCMPGT;
14420 FlipSigns = true; Invert = true; break;
14423 // Special case: Use min/max operations for SETULE/SETUGE
14424 MVT VET = VT.getVectorElementType();
14426 (Subtarget->hasSSE41() && (VET >= MVT::i8 && VET <= MVT::i32))
14427 || (Subtarget->hasSSE2() && (VET == MVT::i8));
14430 switch (SetCCOpcode) {
14432 case ISD::SETULE: Opc = ISD::UMIN; MinMax = true; break;
14433 case ISD::SETUGE: Opc = ISD::UMAX; MinMax = true; break;
14436 if (MinMax) { Swap = false; Invert = false; FlipSigns = false; }
14439 bool hasSubus = Subtarget->hasSSE2() && (VET == MVT::i8 || VET == MVT::i16);
14440 if (!MinMax && hasSubus) {
14441 // As another special case, use PSUBUS[BW] when it's profitable. E.g. for
14443 // t = psubus Op0, Op1
14444 // pcmpeq t, <0..0>
14445 switch (SetCCOpcode) {
14447 case ISD::SETULT: {
14448 // If the comparison is against a constant we can turn this into a
14449 // setule. With psubus, setule does not require a swap. This is
14450 // beneficial because the constant in the register is no longer
14451 // destructed as the destination so it can be hoisted out of a loop.
14452 // Only do this pre-AVX since vpcmp* is no longer destructive.
14453 if (Subtarget->hasAVX())
14455 SDValue ULEOp1 = ChangeVSETULTtoVSETULE(dl, Op1, DAG);
14456 if (ULEOp1.getNode()) {
14458 Subus = true; Invert = false; Swap = false;
14462 // Psubus is better than flip-sign because it requires no inversion.
14463 case ISD::SETUGE: Subus = true; Invert = false; Swap = true; break;
14464 case ISD::SETULE: Subus = true; Invert = false; Swap = false; break;
14468 Opc = X86ISD::SUBUS;
14474 std::swap(Op0, Op1);
14476 // Check that the operation in question is available (most are plain SSE2,
14477 // but PCMPGTQ and PCMPEQQ have different requirements).
14478 if (VT == MVT::v2i64) {
14479 if (Opc == X86ISD::PCMPGT && !Subtarget->hasSSE42()) {
14480 assert(Subtarget->hasSSE2() && "Don't know how to lower!");
14482 // First cast everything to the right type.
14483 Op0 = DAG.getBitcast(MVT::v4i32, Op0);
14484 Op1 = DAG.getBitcast(MVT::v4i32, Op1);
14486 // Since SSE has no unsigned integer comparisons, we need to flip the sign
14487 // bits of the inputs before performing those operations. The lower
14488 // compare is always unsigned.
14491 SB = DAG.getConstant(0x80000000U, dl, MVT::v4i32);
14493 SDValue Sign = DAG.getConstant(0x80000000U, dl, MVT::i32);
14494 SDValue Zero = DAG.getConstant(0x00000000U, dl, MVT::i32);
14495 SB = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
14496 Sign, Zero, Sign, Zero);
14498 Op0 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op0, SB);
14499 Op1 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op1, SB);
14501 // Emulate PCMPGTQ with (hi1 > hi2) | ((hi1 == hi2) & (lo1 > lo2))
14502 SDValue GT = DAG.getNode(X86ISD::PCMPGT, dl, MVT::v4i32, Op0, Op1);
14503 SDValue EQ = DAG.getNode(X86ISD::PCMPEQ, dl, MVT::v4i32, Op0, Op1);
14505 // Create masks for only the low parts/high parts of the 64 bit integers.
14506 static const int MaskHi[] = { 1, 1, 3, 3 };
14507 static const int MaskLo[] = { 0, 0, 2, 2 };
14508 SDValue EQHi = DAG.getVectorShuffle(MVT::v4i32, dl, EQ, EQ, MaskHi);
14509 SDValue GTLo = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskLo);
14510 SDValue GTHi = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskHi);
14512 SDValue Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, EQHi, GTLo);
14513 Result = DAG.getNode(ISD::OR, dl, MVT::v4i32, Result, GTHi);
14516 Result = DAG.getNOT(dl, Result, MVT::v4i32);
14518 return DAG.getBitcast(VT, Result);
14521 if (Opc == X86ISD::PCMPEQ && !Subtarget->hasSSE41()) {
14522 // If pcmpeqq is missing but pcmpeqd is available synthesize pcmpeqq with
14523 // pcmpeqd + pshufd + pand.
14524 assert(Subtarget->hasSSE2() && !FlipSigns && "Don't know how to lower!");
14526 // First cast everything to the right type.
14527 Op0 = DAG.getBitcast(MVT::v4i32, Op0);
14528 Op1 = DAG.getBitcast(MVT::v4i32, Op1);
14531 SDValue Result = DAG.getNode(Opc, dl, MVT::v4i32, Op0, Op1);
14533 // Make sure the lower and upper halves are both all-ones.
14534 static const int Mask[] = { 1, 0, 3, 2 };
14535 SDValue Shuf = DAG.getVectorShuffle(MVT::v4i32, dl, Result, Result, Mask);
14536 Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, Result, Shuf);
14539 Result = DAG.getNOT(dl, Result, MVT::v4i32);
14541 return DAG.getBitcast(VT, Result);
14545 // Since SSE has no unsigned integer comparisons, we need to flip the sign
14546 // bits of the inputs before performing those operations.
14548 MVT EltVT = VT.getVectorElementType();
14549 SDValue SB = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()), dl,
14551 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SB);
14552 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SB);
14555 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
14557 // If the logical-not of the result is required, perform that now.
14559 Result = DAG.getNOT(dl, Result, VT);
14562 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Op0, Result);
14565 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Result,
14566 getZeroVector(VT, Subtarget, DAG, dl));
14571 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
14573 MVT VT = Op.getSimpleValueType();
14575 if (VT.isVector()) return LowerVSETCC(Op, Subtarget, DAG);
14577 assert(((!Subtarget->hasAVX512() && VT == MVT::i8) || (VT == MVT::i1))
14578 && "SetCC type must be 8-bit or 1-bit integer");
14579 SDValue Op0 = Op.getOperand(0);
14580 SDValue Op1 = Op.getOperand(1);
14582 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
14584 // Optimize to BT if possible.
14585 // Lower (X & (1 << N)) == 0 to BT(X, N).
14586 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
14587 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
14588 if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() &&
14589 isNullConstant(Op1) &&
14590 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
14591 if (SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG)) {
14593 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, NewSetCC);
14598 // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of
14600 if ((isOneConstant(Op1) || isNullConstant(Op1)) &&
14601 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
14603 // If the input is a setcc, then reuse the input setcc or use a new one with
14604 // the inverted condition.
14605 if (Op0.getOpcode() == X86ISD::SETCC) {
14606 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0);
14607 bool Invert = (CC == ISD::SETNE) ^ isNullConstant(Op1);
14611 CCode = X86::GetOppositeBranchCondition(CCode);
14612 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
14613 DAG.getConstant(CCode, dl, MVT::i8),
14614 Op0.getOperand(1));
14616 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
14620 if ((Op0.getValueType() == MVT::i1) && isOneConstant(Op1) &&
14621 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
14623 ISD::CondCode NewCC = ISD::getSetCCInverse(CC, true);
14624 return DAG.getSetCC(dl, VT, Op0, DAG.getConstant(0, dl, MVT::i1), NewCC);
14627 bool isFP = Op1.getSimpleValueType().isFloatingPoint();
14628 unsigned X86CC = TranslateX86CC(CC, dl, isFP, Op0, Op1, DAG);
14629 if (X86CC == X86::COND_INVALID)
14632 SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, dl, DAG);
14633 EFLAGS = ConvertCmpIfNecessary(EFLAGS, DAG);
14634 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
14635 DAG.getConstant(X86CC, dl, MVT::i8), EFLAGS);
14637 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
14641 SDValue X86TargetLowering::LowerSETCCE(SDValue Op, SelectionDAG &DAG) const {
14642 SDValue LHS = Op.getOperand(0);
14643 SDValue RHS = Op.getOperand(1);
14644 SDValue Carry = Op.getOperand(2);
14645 SDValue Cond = Op.getOperand(3);
14648 assert(LHS.getSimpleValueType().isInteger() && "SETCCE is integer only.");
14649 X86::CondCode CC = TranslateIntegerX86CC(cast<CondCodeSDNode>(Cond)->get());
14651 assert(Carry.getOpcode() != ISD::CARRY_FALSE);
14652 SDVTList VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
14653 SDValue Cmp = DAG.getNode(X86ISD::SBB, DL, VTs, LHS, RHS, Carry);
14654 return DAG.getNode(X86ISD::SETCC, DL, Op.getValueType(),
14655 DAG.getConstant(CC, DL, MVT::i8), Cmp.getValue(1));
14658 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
14659 static bool isX86LogicalCmp(SDValue Op) {
14660 unsigned Opc = Op.getNode()->getOpcode();
14661 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI ||
14662 Opc == X86ISD::SAHF)
14664 if (Op.getResNo() == 1 &&
14665 (Opc == X86ISD::ADD ||
14666 Opc == X86ISD::SUB ||
14667 Opc == X86ISD::ADC ||
14668 Opc == X86ISD::SBB ||
14669 Opc == X86ISD::SMUL ||
14670 Opc == X86ISD::UMUL ||
14671 Opc == X86ISD::INC ||
14672 Opc == X86ISD::DEC ||
14673 Opc == X86ISD::OR ||
14674 Opc == X86ISD::XOR ||
14675 Opc == X86ISD::AND))
14678 if (Op.getResNo() == 2 && Opc == X86ISD::UMUL)
14684 static bool isTruncWithZeroHighBitsInput(SDValue V, SelectionDAG &DAG) {
14685 if (V.getOpcode() != ISD::TRUNCATE)
14688 SDValue VOp0 = V.getOperand(0);
14689 unsigned InBits = VOp0.getValueSizeInBits();
14690 unsigned Bits = V.getValueSizeInBits();
14691 return DAG.MaskedValueIsZero(VOp0, APInt::getHighBitsSet(InBits,InBits-Bits));
14694 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
14695 bool addTest = true;
14696 SDValue Cond = Op.getOperand(0);
14697 SDValue Op1 = Op.getOperand(1);
14698 SDValue Op2 = Op.getOperand(2);
14700 MVT VT = Op1.getSimpleValueType();
14703 // Lower FP selects into a CMP/AND/ANDN/OR sequence when the necessary SSE ops
14704 // are available or VBLENDV if AVX is available.
14705 // Otherwise FP cmovs get lowered into a less efficient branch sequence later.
14706 if (Cond.getOpcode() == ISD::SETCC &&
14707 ((Subtarget->hasSSE2() && (VT == MVT::f32 || VT == MVT::f64)) ||
14708 (Subtarget->hasSSE1() && VT == MVT::f32)) &&
14709 VT == Cond.getOperand(0).getSimpleValueType() && Cond->hasOneUse()) {
14710 SDValue CondOp0 = Cond.getOperand(0), CondOp1 = Cond.getOperand(1);
14711 int SSECC = translateX86FSETCC(
14712 cast<CondCodeSDNode>(Cond.getOperand(2))->get(), CondOp0, CondOp1);
14715 if (Subtarget->hasAVX512()) {
14716 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CondOp0, CondOp1,
14717 DAG.getConstant(SSECC, DL, MVT::i8));
14718 return DAG.getNode(X86ISD::SELECT, DL, VT, Cmp, Op1, Op2);
14721 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, VT, CondOp0, CondOp1,
14722 DAG.getConstant(SSECC, DL, MVT::i8));
14724 // If we have AVX, we can use a variable vector select (VBLENDV) instead
14725 // of 3 logic instructions for size savings and potentially speed.
14726 // Unfortunately, there is no scalar form of VBLENDV.
14728 // If either operand is a constant, don't try this. We can expect to
14729 // optimize away at least one of the logic instructions later in that
14730 // case, so that sequence would be faster than a variable blend.
14732 // BLENDV was introduced with SSE 4.1, but the 2 register form implicitly
14733 // uses XMM0 as the selection register. That may need just as many
14734 // instructions as the AND/ANDN/OR sequence due to register moves, so
14737 if (Subtarget->hasAVX() &&
14738 !isa<ConstantFPSDNode>(Op1) && !isa<ConstantFPSDNode>(Op2)) {
14740 // Convert to vectors, do a VSELECT, and convert back to scalar.
14741 // All of the conversions should be optimized away.
14743 MVT VecVT = VT == MVT::f32 ? MVT::v4f32 : MVT::v2f64;
14744 SDValue VOp1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VecVT, Op1);
14745 SDValue VOp2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VecVT, Op2);
14746 SDValue VCmp = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VecVT, Cmp);
14748 MVT VCmpVT = VT == MVT::f32 ? MVT::v4i32 : MVT::v2i64;
14749 VCmp = DAG.getBitcast(VCmpVT, VCmp);
14751 SDValue VSel = DAG.getNode(ISD::VSELECT, DL, VecVT, VCmp, VOp1, VOp2);
14753 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT,
14754 VSel, DAG.getIntPtrConstant(0, DL));
14756 SDValue AndN = DAG.getNode(X86ISD::FANDN, DL, VT, Cmp, Op2);
14757 SDValue And = DAG.getNode(X86ISD::FAND, DL, VT, Cmp, Op1);
14758 return DAG.getNode(X86ISD::FOR, DL, VT, AndN, And);
14762 if (VT.isVector() && VT.getVectorElementType() == MVT::i1) {
14764 if (ISD::isBuildVectorOfConstantSDNodes(Op1.getNode()))
14765 Op1Scalar = ConvertI1VectorToInteger(Op1, DAG);
14766 else if (Op1.getOpcode() == ISD::BITCAST && Op1.getOperand(0))
14767 Op1Scalar = Op1.getOperand(0);
14769 if (ISD::isBuildVectorOfConstantSDNodes(Op2.getNode()))
14770 Op2Scalar = ConvertI1VectorToInteger(Op2, DAG);
14771 else if (Op2.getOpcode() == ISD::BITCAST && Op2.getOperand(0))
14772 Op2Scalar = Op2.getOperand(0);
14773 if (Op1Scalar.getNode() && Op2Scalar.getNode()) {
14774 SDValue newSelect = DAG.getNode(ISD::SELECT, DL,
14775 Op1Scalar.getValueType(),
14776 Cond, Op1Scalar, Op2Scalar);
14777 if (newSelect.getValueSizeInBits() == VT.getSizeInBits())
14778 return DAG.getBitcast(VT, newSelect);
14779 SDValue ExtVec = DAG.getBitcast(MVT::v8i1, newSelect);
14780 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, ExtVec,
14781 DAG.getIntPtrConstant(0, DL));
14785 if (VT == MVT::v4i1 || VT == MVT::v2i1) {
14786 SDValue zeroConst = DAG.getIntPtrConstant(0, DL);
14787 Op1 = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, MVT::v8i1,
14788 DAG.getUNDEF(MVT::v8i1), Op1, zeroConst);
14789 Op2 = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, MVT::v8i1,
14790 DAG.getUNDEF(MVT::v8i1), Op2, zeroConst);
14791 SDValue newSelect = DAG.getNode(ISD::SELECT, DL, MVT::v8i1,
14793 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, newSelect, zeroConst);
14796 if (Cond.getOpcode() == ISD::SETCC) {
14797 SDValue NewCond = LowerSETCC(Cond, DAG);
14798 if (NewCond.getNode())
14802 // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y
14803 // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y
14804 // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y
14805 // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y
14806 if (Cond.getOpcode() == X86ISD::SETCC &&
14807 Cond.getOperand(1).getOpcode() == X86ISD::CMP &&
14808 isNullConstant(Cond.getOperand(1).getOperand(1))) {
14809 SDValue Cmp = Cond.getOperand(1);
14811 unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue();
14813 if ((isAllOnesConstant(Op1) || isAllOnesConstant(Op2)) &&
14814 (CondCode == X86::COND_E || CondCode == X86::COND_NE)) {
14815 SDValue Y = isAllOnesConstant(Op2) ? Op1 : Op2;
14817 SDValue CmpOp0 = Cmp.getOperand(0);
14818 // Apply further optimizations for special cases
14819 // (select (x != 0), -1, 0) -> neg & sbb
14820 // (select (x == 0), 0, -1) -> neg & sbb
14821 if (isNullConstant(Y) &&
14822 (isAllOnesConstant(Op1) == (CondCode == X86::COND_NE))) {
14823 SDVTList VTs = DAG.getVTList(CmpOp0.getValueType(), MVT::i32);
14824 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, VTs,
14825 DAG.getConstant(0, DL,
14826 CmpOp0.getValueType()),
14828 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
14829 DAG.getConstant(X86::COND_B, DL, MVT::i8),
14830 SDValue(Neg.getNode(), 1));
14834 Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32,
14835 CmpOp0, DAG.getConstant(1, DL, CmpOp0.getValueType()));
14836 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
14838 SDValue Res = // Res = 0 or -1.
14839 DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
14840 DAG.getConstant(X86::COND_B, DL, MVT::i8), Cmp);
14842 if (isAllOnesConstant(Op1) != (CondCode == X86::COND_E))
14843 Res = DAG.getNOT(DL, Res, Res.getValueType());
14845 if (!isNullConstant(Op2))
14846 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y);
14851 // Look past (and (setcc_carry (cmp ...)), 1).
14852 if (Cond.getOpcode() == ISD::AND &&
14853 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY &&
14854 isOneConstant(Cond.getOperand(1)))
14855 Cond = Cond.getOperand(0);
14857 // If condition flag is set by a X86ISD::CMP, then use it as the condition
14858 // setting operand in place of the X86ISD::SETCC.
14859 unsigned CondOpcode = Cond.getOpcode();
14860 if (CondOpcode == X86ISD::SETCC ||
14861 CondOpcode == X86ISD::SETCC_CARRY) {
14862 CC = Cond.getOperand(0);
14864 SDValue Cmp = Cond.getOperand(1);
14865 unsigned Opc = Cmp.getOpcode();
14866 MVT VT = Op.getSimpleValueType();
14868 bool IllegalFPCMov = false;
14869 if (VT.isFloatingPoint() && !VT.isVector() &&
14870 !isScalarFPTypeInSSEReg(VT)) // FPStack?
14871 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
14873 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
14874 Opc == X86ISD::BT) { // FIXME
14878 } else if (CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
14879 CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
14880 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
14881 Cond.getOperand(0).getValueType() != MVT::i8)) {
14882 SDValue LHS = Cond.getOperand(0);
14883 SDValue RHS = Cond.getOperand(1);
14884 unsigned X86Opcode;
14887 switch (CondOpcode) {
14888 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
14889 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
14890 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
14891 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
14892 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
14893 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
14894 default: llvm_unreachable("unexpected overflowing operator");
14896 if (CondOpcode == ISD::UMULO)
14897 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
14900 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
14902 SDValue X86Op = DAG.getNode(X86Opcode, DL, VTs, LHS, RHS);
14904 if (CondOpcode == ISD::UMULO)
14905 Cond = X86Op.getValue(2);
14907 Cond = X86Op.getValue(1);
14909 CC = DAG.getConstant(X86Cond, DL, MVT::i8);
14914 // Look past the truncate if the high bits are known zero.
14915 if (isTruncWithZeroHighBitsInput(Cond, DAG))
14916 Cond = Cond.getOperand(0);
14918 // We know the result of AND is compared against zero. Try to match
14920 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
14921 if (SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG)) {
14922 CC = NewSetCC.getOperand(0);
14923 Cond = NewSetCC.getOperand(1);
14930 CC = DAG.getConstant(X86::COND_NE, DL, MVT::i8);
14931 Cond = EmitTest(Cond, X86::COND_NE, DL, DAG);
14934 // a < b ? -1 : 0 -> RES = ~setcc_carry
14935 // a < b ? 0 : -1 -> RES = setcc_carry
14936 // a >= b ? -1 : 0 -> RES = setcc_carry
14937 // a >= b ? 0 : -1 -> RES = ~setcc_carry
14938 if (Cond.getOpcode() == X86ISD::SUB) {
14939 Cond = ConvertCmpIfNecessary(Cond, DAG);
14940 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue();
14942 if ((CondCode == X86::COND_AE || CondCode == X86::COND_B) &&
14943 (isAllOnesConstant(Op1) || isAllOnesConstant(Op2)) &&
14944 (isNullConstant(Op1) || isNullConstant(Op2))) {
14945 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
14946 DAG.getConstant(X86::COND_B, DL, MVT::i8),
14948 if (isAllOnesConstant(Op1) != (CondCode == X86::COND_B))
14949 return DAG.getNOT(DL, Res, Res.getValueType());
14954 // X86 doesn't have an i8 cmov. If both operands are the result of a truncate
14955 // widen the cmov and push the truncate through. This avoids introducing a new
14956 // branch during isel and doesn't add any extensions.
14957 if (Op.getValueType() == MVT::i8 &&
14958 Op1.getOpcode() == ISD::TRUNCATE && Op2.getOpcode() == ISD::TRUNCATE) {
14959 SDValue T1 = Op1.getOperand(0), T2 = Op2.getOperand(0);
14960 if (T1.getValueType() == T2.getValueType() &&
14961 // Blacklist CopyFromReg to avoid partial register stalls.
14962 T1.getOpcode() != ISD::CopyFromReg && T2.getOpcode()!=ISD::CopyFromReg){
14963 SDVTList VTs = DAG.getVTList(T1.getValueType(), MVT::Glue);
14964 SDValue Cmov = DAG.getNode(X86ISD::CMOV, DL, VTs, T2, T1, CC, Cond);
14965 return DAG.getNode(ISD::TRUNCATE, DL, Op.getValueType(), Cmov);
14969 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
14970 // condition is true.
14971 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
14972 SDValue Ops[] = { Op2, Op1, CC, Cond };
14973 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops);
14976 static SDValue LowerSIGN_EXTEND_AVX512(SDValue Op,
14977 const X86Subtarget *Subtarget,
14978 SelectionDAG &DAG) {
14979 MVT VT = Op->getSimpleValueType(0);
14980 SDValue In = Op->getOperand(0);
14981 MVT InVT = In.getSimpleValueType();
14982 MVT VTElt = VT.getVectorElementType();
14983 MVT InVTElt = InVT.getVectorElementType();
14987 if ((InVTElt == MVT::i1) &&
14988 (((Subtarget->hasBWI() && Subtarget->hasVLX() &&
14989 VT.getSizeInBits() <= 256 && VTElt.getSizeInBits() <= 16)) ||
14991 ((Subtarget->hasBWI() && VT.is512BitVector() &&
14992 VTElt.getSizeInBits() <= 16)) ||
14994 ((Subtarget->hasDQI() && Subtarget->hasVLX() &&
14995 VT.getSizeInBits() <= 256 && VTElt.getSizeInBits() >= 32)) ||
14997 ((Subtarget->hasDQI() && VT.is512BitVector() &&
14998 VTElt.getSizeInBits() >= 32))))
14999 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
15001 unsigned int NumElts = VT.getVectorNumElements();
15003 if (NumElts != 8 && NumElts != 16 && !Subtarget->hasBWI())
15006 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1) {
15007 if (In.getOpcode() == X86ISD::VSEXT || In.getOpcode() == X86ISD::VZEXT)
15008 return DAG.getNode(In.getOpcode(), dl, VT, In.getOperand(0));
15009 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
15012 assert (InVT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
15013 MVT ExtVT = NumElts == 8 ? MVT::v8i64 : MVT::v16i32;
15015 DAG.getConstant(APInt::getAllOnesValue(ExtVT.getScalarSizeInBits()), dl,
15018 DAG.getConstant(APInt::getNullValue(ExtVT.getScalarSizeInBits()), dl, ExtVT);
15020 SDValue V = DAG.getNode(ISD::VSELECT, dl, ExtVT, In, NegOne, Zero);
15021 if (VT.is512BitVector())
15023 return DAG.getNode(X86ISD::VTRUNC, dl, VT, V);
15026 static SDValue LowerSIGN_EXTEND_VECTOR_INREG(SDValue Op,
15027 const X86Subtarget *Subtarget,
15028 SelectionDAG &DAG) {
15029 SDValue In = Op->getOperand(0);
15030 MVT VT = Op->getSimpleValueType(0);
15031 MVT InVT = In.getSimpleValueType();
15032 assert(VT.getSizeInBits() == InVT.getSizeInBits());
15034 MVT InSVT = InVT.getVectorElementType();
15035 assert(VT.getVectorElementType().getSizeInBits() > InSVT.getSizeInBits());
15037 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16)
15039 if (InSVT != MVT::i32 && InSVT != MVT::i16 && InSVT != MVT::i8)
15044 // SSE41 targets can use the pmovsx* instructions directly.
15045 if (Subtarget->hasSSE41())
15046 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
15048 // pre-SSE41 targets unpack lower lanes and then sign-extend using SRAI.
15052 // As SRAI is only available on i16/i32 types, we expand only up to i32
15053 // and handle i64 separately.
15054 while (CurrVT != VT && CurrVT.getVectorElementType() != MVT::i32) {
15055 Curr = DAG.getNode(X86ISD::UNPCKL, dl, CurrVT, DAG.getUNDEF(CurrVT), Curr);
15056 MVT CurrSVT = MVT::getIntegerVT(CurrVT.getScalarSizeInBits() * 2);
15057 CurrVT = MVT::getVectorVT(CurrSVT, CurrVT.getVectorNumElements() / 2);
15058 Curr = DAG.getBitcast(CurrVT, Curr);
15061 SDValue SignExt = Curr;
15062 if (CurrVT != InVT) {
15063 unsigned SignExtShift =
15064 CurrVT.getVectorElementType().getSizeInBits() - InSVT.getSizeInBits();
15065 SignExt = DAG.getNode(X86ISD::VSRAI, dl, CurrVT, Curr,
15066 DAG.getConstant(SignExtShift, dl, MVT::i8));
15072 if (VT == MVT::v2i64 && CurrVT == MVT::v4i32) {
15073 SDValue Sign = DAG.getNode(X86ISD::VSRAI, dl, CurrVT, Curr,
15074 DAG.getConstant(31, dl, MVT::i8));
15075 SDValue Ext = DAG.getVectorShuffle(CurrVT, dl, SignExt, Sign, {0, 4, 1, 5});
15076 return DAG.getBitcast(VT, Ext);
15082 static SDValue LowerSIGN_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
15083 SelectionDAG &DAG) {
15084 MVT VT = Op->getSimpleValueType(0);
15085 SDValue In = Op->getOperand(0);
15086 MVT InVT = In.getSimpleValueType();
15089 if (VT.is512BitVector() || InVT.getVectorElementType() == MVT::i1)
15090 return LowerSIGN_EXTEND_AVX512(Op, Subtarget, DAG);
15092 if ((VT != MVT::v4i64 || InVT != MVT::v4i32) &&
15093 (VT != MVT::v8i32 || InVT != MVT::v8i16) &&
15094 (VT != MVT::v16i16 || InVT != MVT::v16i8))
15097 if (Subtarget->hasInt256())
15098 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
15100 // Optimize vectors in AVX mode
15101 // Sign extend v8i16 to v8i32 and
15104 // Divide input vector into two parts
15105 // for v4i32 the shuffle mask will be { 0, 1, -1, -1} {2, 3, -1, -1}
15106 // use vpmovsx instruction to extend v4i32 -> v2i64; v8i16 -> v4i32
15107 // concat the vectors to original VT
15109 unsigned NumElems = InVT.getVectorNumElements();
15110 SDValue Undef = DAG.getUNDEF(InVT);
15112 SmallVector<int,8> ShufMask1(NumElems, -1);
15113 for (unsigned i = 0; i != NumElems/2; ++i)
15116 SDValue OpLo = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask1[0]);
15118 SmallVector<int,8> ShufMask2(NumElems, -1);
15119 for (unsigned i = 0; i != NumElems/2; ++i)
15120 ShufMask2[i] = i + NumElems/2;
15122 SDValue OpHi = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask2[0]);
15124 MVT HalfVT = MVT::getVectorVT(VT.getVectorElementType(),
15125 VT.getVectorNumElements()/2);
15127 OpLo = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpLo);
15128 OpHi = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpHi);
15130 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
15133 // Lower vector extended loads using a shuffle. If SSSE3 is not available we
15134 // may emit an illegal shuffle but the expansion is still better than scalar
15135 // code. We generate X86ISD::VSEXT for SEXTLOADs if it's available, otherwise
15136 // we'll emit a shuffle and a arithmetic shift.
15137 // FIXME: Is the expansion actually better than scalar code? It doesn't seem so.
15138 // TODO: It is possible to support ZExt by zeroing the undef values during
15139 // the shuffle phase or after the shuffle.
15140 static SDValue LowerExtendedLoad(SDValue Op, const X86Subtarget *Subtarget,
15141 SelectionDAG &DAG) {
15142 MVT RegVT = Op.getSimpleValueType();
15143 assert(RegVT.isVector() && "We only custom lower vector sext loads.");
15144 assert(RegVT.isInteger() &&
15145 "We only custom lower integer vector sext loads.");
15147 // Nothing useful we can do without SSE2 shuffles.
15148 assert(Subtarget->hasSSE2() && "We only custom lower sext loads with SSE2.");
15150 LoadSDNode *Ld = cast<LoadSDNode>(Op.getNode());
15152 EVT MemVT = Ld->getMemoryVT();
15153 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
15154 unsigned RegSz = RegVT.getSizeInBits();
15156 ISD::LoadExtType Ext = Ld->getExtensionType();
15158 assert((Ext == ISD::EXTLOAD || Ext == ISD::SEXTLOAD)
15159 && "Only anyext and sext are currently implemented.");
15160 assert(MemVT != RegVT && "Cannot extend to the same type");
15161 assert(MemVT.isVector() && "Must load a vector from memory");
15163 unsigned NumElems = RegVT.getVectorNumElements();
15164 unsigned MemSz = MemVT.getSizeInBits();
15165 assert(RegSz > MemSz && "Register size must be greater than the mem size");
15167 if (Ext == ISD::SEXTLOAD && RegSz == 256 && !Subtarget->hasInt256()) {
15168 // The only way in which we have a legal 256-bit vector result but not the
15169 // integer 256-bit operations needed to directly lower a sextload is if we
15170 // have AVX1 but not AVX2. In that case, we can always emit a sextload to
15171 // a 128-bit vector and a normal sign_extend to 256-bits that should get
15172 // correctly legalized. We do this late to allow the canonical form of
15173 // sextload to persist throughout the rest of the DAG combiner -- it wants
15174 // to fold together any extensions it can, and so will fuse a sign_extend
15175 // of an sextload into a sextload targeting a wider value.
15177 if (MemSz == 128) {
15178 // Just switch this to a normal load.
15179 assert(TLI.isTypeLegal(MemVT) && "If the memory type is a 128-bit type, "
15180 "it must be a legal 128-bit vector "
15182 Load = DAG.getLoad(MemVT, dl, Ld->getChain(), Ld->getBasePtr(),
15183 Ld->getPointerInfo(), Ld->isVolatile(), Ld->isNonTemporal(),
15184 Ld->isInvariant(), Ld->getAlignment());
15186 assert(MemSz < 128 &&
15187 "Can't extend a type wider than 128 bits to a 256 bit vector!");
15188 // Do an sext load to a 128-bit vector type. We want to use the same
15189 // number of elements, but elements half as wide. This will end up being
15190 // recursively lowered by this routine, but will succeed as we definitely
15191 // have all the necessary features if we're using AVX1.
15193 EVT::getIntegerVT(*DAG.getContext(), RegVT.getScalarSizeInBits() / 2);
15194 EVT HalfVecVT = EVT::getVectorVT(*DAG.getContext(), HalfEltVT, NumElems);
15196 DAG.getExtLoad(Ext, dl, HalfVecVT, Ld->getChain(), Ld->getBasePtr(),
15197 Ld->getPointerInfo(), MemVT, Ld->isVolatile(),
15198 Ld->isNonTemporal(), Ld->isInvariant(),
15199 Ld->getAlignment());
15202 // Replace chain users with the new chain.
15203 assert(Load->getNumValues() == 2 && "Loads must carry a chain!");
15204 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), Load.getValue(1));
15206 // Finally, do a normal sign-extend to the desired register.
15207 return DAG.getSExtOrTrunc(Load, dl, RegVT);
15210 // All sizes must be a power of two.
15211 assert(isPowerOf2_32(RegSz * MemSz * NumElems) &&
15212 "Non-power-of-two elements are not custom lowered!");
15214 // Attempt to load the original value using scalar loads.
15215 // Find the largest scalar type that divides the total loaded size.
15216 MVT SclrLoadTy = MVT::i8;
15217 for (MVT Tp : MVT::integer_valuetypes()) {
15218 if (TLI.isTypeLegal(Tp) && ((MemSz % Tp.getSizeInBits()) == 0)) {
15223 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
15224 if (TLI.isTypeLegal(MVT::f64) && SclrLoadTy.getSizeInBits() < 64 &&
15226 SclrLoadTy = MVT::f64;
15228 // Calculate the number of scalar loads that we need to perform
15229 // in order to load our vector from memory.
15230 unsigned NumLoads = MemSz / SclrLoadTy.getSizeInBits();
15232 assert((Ext != ISD::SEXTLOAD || NumLoads == 1) &&
15233 "Can only lower sext loads with a single scalar load!");
15235 unsigned loadRegZize = RegSz;
15236 if (Ext == ISD::SEXTLOAD && RegSz >= 256)
15239 // Represent our vector as a sequence of elements which are the
15240 // largest scalar that we can load.
15241 EVT LoadUnitVecVT = EVT::getVectorVT(
15242 *DAG.getContext(), SclrLoadTy, loadRegZize / SclrLoadTy.getSizeInBits());
15244 // Represent the data using the same element type that is stored in
15245 // memory. In practice, we ''widen'' MemVT.
15247 EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
15248 loadRegZize / MemVT.getScalarSizeInBits());
15250 assert(WideVecVT.getSizeInBits() == LoadUnitVecVT.getSizeInBits() &&
15251 "Invalid vector type");
15253 // We can't shuffle using an illegal type.
15254 assert(TLI.isTypeLegal(WideVecVT) &&
15255 "We only lower types that form legal widened vector types");
15257 SmallVector<SDValue, 8> Chains;
15258 SDValue Ptr = Ld->getBasePtr();
15259 SDValue Increment = DAG.getConstant(SclrLoadTy.getSizeInBits() / 8, dl,
15260 TLI.getPointerTy(DAG.getDataLayout()));
15261 SDValue Res = DAG.getUNDEF(LoadUnitVecVT);
15263 for (unsigned i = 0; i < NumLoads; ++i) {
15264 // Perform a single load.
15265 SDValue ScalarLoad =
15266 DAG.getLoad(SclrLoadTy, dl, Ld->getChain(), Ptr, Ld->getPointerInfo(),
15267 Ld->isVolatile(), Ld->isNonTemporal(), Ld->isInvariant(),
15268 Ld->getAlignment());
15269 Chains.push_back(ScalarLoad.getValue(1));
15270 // Create the first element type using SCALAR_TO_VECTOR in order to avoid
15271 // another round of DAGCombining.
15273 Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LoadUnitVecVT, ScalarLoad);
15275 Res = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, LoadUnitVecVT, Res,
15276 ScalarLoad, DAG.getIntPtrConstant(i, dl));
15278 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
15281 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
15283 // Bitcast the loaded value to a vector of the original element type, in
15284 // the size of the target vector type.
15285 SDValue SlicedVec = DAG.getBitcast(WideVecVT, Res);
15286 unsigned SizeRatio = RegSz / MemSz;
15288 if (Ext == ISD::SEXTLOAD) {
15289 // If we have SSE4.1, we can directly emit a VSEXT node.
15290 if (Subtarget->hasSSE41()) {
15291 SDValue Sext = DAG.getNode(X86ISD::VSEXT, dl, RegVT, SlicedVec);
15292 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
15296 // Otherwise we'll use SIGN_EXTEND_VECTOR_INREG to sign extend the lowest
15298 assert(TLI.isOperationLegalOrCustom(ISD::SIGN_EXTEND_VECTOR_INREG, RegVT) &&
15299 "We can't implement a sext load without SIGN_EXTEND_VECTOR_INREG!");
15301 SDValue Shuff = DAG.getSignExtendVectorInReg(SlicedVec, dl, RegVT);
15302 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
15306 // Redistribute the loaded elements into the different locations.
15307 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
15308 for (unsigned i = 0; i != NumElems; ++i)
15309 ShuffleVec[i * SizeRatio] = i;
15311 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec,
15312 DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
15314 // Bitcast to the requested type.
15315 Shuff = DAG.getBitcast(RegVT, Shuff);
15316 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
15320 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
15321 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
15322 // from the AND / OR.
15323 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
15324 Opc = Op.getOpcode();
15325 if (Opc != ISD::OR && Opc != ISD::AND)
15327 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
15328 Op.getOperand(0).hasOneUse() &&
15329 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
15330 Op.getOperand(1).hasOneUse());
15333 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
15334 // 1 and that the SETCC node has a single use.
15335 static bool isXor1OfSetCC(SDValue Op) {
15336 if (Op.getOpcode() != ISD::XOR)
15338 if (isOneConstant(Op.getOperand(1)))
15339 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
15340 Op.getOperand(0).hasOneUse();
15344 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
15345 bool addTest = true;
15346 SDValue Chain = Op.getOperand(0);
15347 SDValue Cond = Op.getOperand(1);
15348 SDValue Dest = Op.getOperand(2);
15351 bool Inverted = false;
15353 if (Cond.getOpcode() == ISD::SETCC) {
15354 // Check for setcc([su]{add,sub,mul}o == 0).
15355 if (cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETEQ &&
15356 isNullConstant(Cond.getOperand(1)) &&
15357 Cond.getOperand(0).getResNo() == 1 &&
15358 (Cond.getOperand(0).getOpcode() == ISD::SADDO ||
15359 Cond.getOperand(0).getOpcode() == ISD::UADDO ||
15360 Cond.getOperand(0).getOpcode() == ISD::SSUBO ||
15361 Cond.getOperand(0).getOpcode() == ISD::USUBO ||
15362 Cond.getOperand(0).getOpcode() == ISD::SMULO ||
15363 Cond.getOperand(0).getOpcode() == ISD::UMULO)) {
15365 Cond = Cond.getOperand(0);
15367 SDValue NewCond = LowerSETCC(Cond, DAG);
15368 if (NewCond.getNode())
15373 // FIXME: LowerXALUO doesn't handle these!!
15374 else if (Cond.getOpcode() == X86ISD::ADD ||
15375 Cond.getOpcode() == X86ISD::SUB ||
15376 Cond.getOpcode() == X86ISD::SMUL ||
15377 Cond.getOpcode() == X86ISD::UMUL)
15378 Cond = LowerXALUO(Cond, DAG);
15381 // Look pass (and (setcc_carry (cmp ...)), 1).
15382 if (Cond.getOpcode() == ISD::AND &&
15383 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY &&
15384 isOneConstant(Cond.getOperand(1)))
15385 Cond = Cond.getOperand(0);
15387 // If condition flag is set by a X86ISD::CMP, then use it as the condition
15388 // setting operand in place of the X86ISD::SETCC.
15389 unsigned CondOpcode = Cond.getOpcode();
15390 if (CondOpcode == X86ISD::SETCC ||
15391 CondOpcode == X86ISD::SETCC_CARRY) {
15392 CC = Cond.getOperand(0);
15394 SDValue Cmp = Cond.getOperand(1);
15395 unsigned Opc = Cmp.getOpcode();
15396 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
15397 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
15401 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
15405 // These can only come from an arithmetic instruction with overflow,
15406 // e.g. SADDO, UADDO.
15407 Cond = Cond.getNode()->getOperand(1);
15413 CondOpcode = Cond.getOpcode();
15414 if (CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
15415 CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
15416 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
15417 Cond.getOperand(0).getValueType() != MVT::i8)) {
15418 SDValue LHS = Cond.getOperand(0);
15419 SDValue RHS = Cond.getOperand(1);
15420 unsigned X86Opcode;
15423 // Keep this in sync with LowerXALUO, otherwise we might create redundant
15424 // instructions that can't be removed afterwards (i.e. X86ISD::ADD and
15426 switch (CondOpcode) {
15427 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
15429 if (isOneConstant(RHS)) {
15430 X86Opcode = X86ISD::INC; X86Cond = X86::COND_O;
15433 X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
15434 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
15436 if (isOneConstant(RHS)) {
15437 X86Opcode = X86ISD::DEC; X86Cond = X86::COND_O;
15440 X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
15441 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
15442 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
15443 default: llvm_unreachable("unexpected overflowing operator");
15446 X86Cond = X86::GetOppositeBranchCondition((X86::CondCode)X86Cond);
15447 if (CondOpcode == ISD::UMULO)
15448 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
15451 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
15453 SDValue X86Op = DAG.getNode(X86Opcode, dl, VTs, LHS, RHS);
15455 if (CondOpcode == ISD::UMULO)
15456 Cond = X86Op.getValue(2);
15458 Cond = X86Op.getValue(1);
15460 CC = DAG.getConstant(X86Cond, dl, MVT::i8);
15464 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
15465 SDValue Cmp = Cond.getOperand(0).getOperand(1);
15466 if (CondOpc == ISD::OR) {
15467 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
15468 // two branches instead of an explicit OR instruction with a
15470 if (Cmp == Cond.getOperand(1).getOperand(1) &&
15471 isX86LogicalCmp(Cmp)) {
15472 CC = Cond.getOperand(0).getOperand(0);
15473 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15474 Chain, Dest, CC, Cmp);
15475 CC = Cond.getOperand(1).getOperand(0);
15479 } else { // ISD::AND
15480 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
15481 // two branches instead of an explicit AND instruction with a
15482 // separate test. However, we only do this if this block doesn't
15483 // have a fall-through edge, because this requires an explicit
15484 // jmp when the condition is false.
15485 if (Cmp == Cond.getOperand(1).getOperand(1) &&
15486 isX86LogicalCmp(Cmp) &&
15487 Op.getNode()->hasOneUse()) {
15488 X86::CondCode CCode =
15489 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
15490 CCode = X86::GetOppositeBranchCondition(CCode);
15491 CC = DAG.getConstant(CCode, dl, MVT::i8);
15492 SDNode *User = *Op.getNode()->use_begin();
15493 // Look for an unconditional branch following this conditional branch.
15494 // We need this because we need to reverse the successors in order
15495 // to implement FCMP_OEQ.
15496 if (User->getOpcode() == ISD::BR) {
15497 SDValue FalseBB = User->getOperand(1);
15499 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
15500 assert(NewBR == User);
15504 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15505 Chain, Dest, CC, Cmp);
15506 X86::CondCode CCode =
15507 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
15508 CCode = X86::GetOppositeBranchCondition(CCode);
15509 CC = DAG.getConstant(CCode, dl, MVT::i8);
15515 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
15516 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
15517 // It should be transformed during dag combiner except when the condition
15518 // is set by a arithmetics with overflow node.
15519 X86::CondCode CCode =
15520 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
15521 CCode = X86::GetOppositeBranchCondition(CCode);
15522 CC = DAG.getConstant(CCode, dl, MVT::i8);
15523 Cond = Cond.getOperand(0).getOperand(1);
15525 } else if (Cond.getOpcode() == ISD::SETCC &&
15526 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETOEQ) {
15527 // For FCMP_OEQ, we can emit
15528 // two branches instead of an explicit AND instruction with a
15529 // separate test. However, we only do this if this block doesn't
15530 // have a fall-through edge, because this requires an explicit
15531 // jmp when the condition is false.
15532 if (Op.getNode()->hasOneUse()) {
15533 SDNode *User = *Op.getNode()->use_begin();
15534 // Look for an unconditional branch following this conditional branch.
15535 // We need this because we need to reverse the successors in order
15536 // to implement FCMP_OEQ.
15537 if (User->getOpcode() == ISD::BR) {
15538 SDValue FalseBB = User->getOperand(1);
15540 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
15541 assert(NewBR == User);
15545 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
15546 Cond.getOperand(0), Cond.getOperand(1));
15547 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
15548 CC = DAG.getConstant(X86::COND_NE, dl, MVT::i8);
15549 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15550 Chain, Dest, CC, Cmp);
15551 CC = DAG.getConstant(X86::COND_P, dl, MVT::i8);
15556 } else if (Cond.getOpcode() == ISD::SETCC &&
15557 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETUNE) {
15558 // For FCMP_UNE, we can emit
15559 // two branches instead of an explicit AND instruction with a
15560 // separate test. However, we only do this if this block doesn't
15561 // have a fall-through edge, because this requires an explicit
15562 // jmp when the condition is false.
15563 if (Op.getNode()->hasOneUse()) {
15564 SDNode *User = *Op.getNode()->use_begin();
15565 // Look for an unconditional branch following this conditional branch.
15566 // We need this because we need to reverse the successors in order
15567 // to implement FCMP_UNE.
15568 if (User->getOpcode() == ISD::BR) {
15569 SDValue FalseBB = User->getOperand(1);
15571 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
15572 assert(NewBR == User);
15575 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
15576 Cond.getOperand(0), Cond.getOperand(1));
15577 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
15578 CC = DAG.getConstant(X86::COND_NE, dl, MVT::i8);
15579 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15580 Chain, Dest, CC, Cmp);
15581 CC = DAG.getConstant(X86::COND_NP, dl, MVT::i8);
15591 // Look pass the truncate if the high bits are known zero.
15592 if (isTruncWithZeroHighBitsInput(Cond, DAG))
15593 Cond = Cond.getOperand(0);
15595 // We know the result of AND is compared against zero. Try to match
15597 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
15598 if (SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG)) {
15599 CC = NewSetCC.getOperand(0);
15600 Cond = NewSetCC.getOperand(1);
15607 X86::CondCode X86Cond = Inverted ? X86::COND_E : X86::COND_NE;
15608 CC = DAG.getConstant(X86Cond, dl, MVT::i8);
15609 Cond = EmitTest(Cond, X86Cond, dl, DAG);
15611 Cond = ConvertCmpIfNecessary(Cond, DAG);
15612 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15613 Chain, Dest, CC, Cond);
15616 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
15617 // Calls to _alloca are needed to probe the stack when allocating more than 4k
15618 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
15619 // that the guard pages used by the OS virtual memory manager are allocated in
15620 // correct sequence.
15622 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
15623 SelectionDAG &DAG) const {
15624 MachineFunction &MF = DAG.getMachineFunction();
15625 bool SplitStack = MF.shouldSplitStack();
15626 bool Lower = (Subtarget->isOSWindows() && !Subtarget->isTargetMachO()) ||
15631 SDNode *Node = Op.getNode();
15632 SDValue Chain = Op.getOperand(0);
15633 SDValue Size = Op.getOperand(1);
15634 unsigned Align = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
15635 EVT VT = Node->getValueType(0);
15637 // Chain the dynamic stack allocation so that it doesn't modify the stack
15638 // pointer when other instructions are using the stack.
15639 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, dl, true), dl);
15641 bool Is64Bit = Subtarget->is64Bit();
15642 MVT SPTy = getPointerTy(DAG.getDataLayout());
15646 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
15647 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
15648 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
15649 " not tell us which reg is the stack pointer!");
15650 EVT VT = Node->getValueType(0);
15651 SDValue Tmp3 = Node->getOperand(2);
15653 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT);
15654 Chain = SP.getValue(1);
15655 unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue();
15656 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
15657 unsigned StackAlign = TFI.getStackAlignment();
15658 Result = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value
15659 if (Align > StackAlign)
15660 Result = DAG.getNode(ISD::AND, dl, VT, Result,
15661 DAG.getConstant(-(uint64_t)Align, dl, VT));
15662 Chain = DAG.getCopyToReg(Chain, dl, SPReg, Result); // Output chain
15663 } else if (SplitStack) {
15664 MachineRegisterInfo &MRI = MF.getRegInfo();
15667 // The 64 bit implementation of segmented stacks needs to clobber both r10
15668 // r11. This makes it impossible to use it along with nested parameters.
15669 const Function *F = MF.getFunction();
15671 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
15673 if (I->hasNestAttr())
15674 report_fatal_error("Cannot use segmented stacks with functions that "
15675 "have nested arguments.");
15678 const TargetRegisterClass *AddrRegClass = getRegClassFor(SPTy);
15679 unsigned Vreg = MRI.createVirtualRegister(AddrRegClass);
15680 Chain = DAG.getCopyToReg(Chain, dl, Vreg, Size);
15681 Result = DAG.getNode(X86ISD::SEG_ALLOCA, dl, SPTy, Chain,
15682 DAG.getRegister(Vreg, SPTy));
15685 const unsigned Reg = (Subtarget->isTarget64BitLP64() ? X86::RAX : X86::EAX);
15687 Chain = DAG.getCopyToReg(Chain, dl, Reg, Size, Flag);
15688 Flag = Chain.getValue(1);
15689 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
15691 Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag);
15693 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
15694 unsigned SPReg = RegInfo->getStackRegister();
15695 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, SPTy);
15696 Chain = SP.getValue(1);
15699 SP = DAG.getNode(ISD::AND, dl, VT, SP.getValue(0),
15700 DAG.getConstant(-(uint64_t)Align, dl, VT));
15701 Chain = DAG.getCopyToReg(Chain, dl, SPReg, SP);
15707 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, dl, true),
15708 DAG.getIntPtrConstant(0, dl, true), SDValue(), dl);
15710 SDValue Ops[2] = {Result, Chain};
15711 return DAG.getMergeValues(Ops, dl);
15714 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
15715 MachineFunction &MF = DAG.getMachineFunction();
15716 auto PtrVT = getPointerTy(MF.getDataLayout());
15717 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
15719 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
15722 if (!Subtarget->is64Bit() ||
15723 Subtarget->isCallingConvWin64(MF.getFunction()->getCallingConv())) {
15724 // vastart just stores the address of the VarArgsFrameIndex slot into the
15725 // memory location argument.
15726 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
15727 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
15728 MachinePointerInfo(SV), false, false, 0);
15732 // gp_offset (0 - 6 * 8)
15733 // fp_offset (48 - 48 + 8 * 16)
15734 // overflow_arg_area (point to parameters coming in memory).
15736 SmallVector<SDValue, 8> MemOps;
15737 SDValue FIN = Op.getOperand(1);
15739 SDValue Store = DAG.getStore(Op.getOperand(0), DL,
15740 DAG.getConstant(FuncInfo->getVarArgsGPOffset(),
15742 FIN, MachinePointerInfo(SV), false, false, 0);
15743 MemOps.push_back(Store);
15746 FIN = DAG.getNode(ISD::ADD, DL, PtrVT, FIN, DAG.getIntPtrConstant(4, DL));
15747 Store = DAG.getStore(Op.getOperand(0), DL,
15748 DAG.getConstant(FuncInfo->getVarArgsFPOffset(), DL,
15750 FIN, MachinePointerInfo(SV, 4), false, false, 0);
15751 MemOps.push_back(Store);
15753 // Store ptr to overflow_arg_area
15754 FIN = DAG.getNode(ISD::ADD, DL, PtrVT, FIN, DAG.getIntPtrConstant(4, DL));
15755 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
15756 Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN,
15757 MachinePointerInfo(SV, 8),
15759 MemOps.push_back(Store);
15761 // Store ptr to reg_save_area.
15762 FIN = DAG.getNode(ISD::ADD, DL, PtrVT, FIN, DAG.getIntPtrConstant(
15763 Subtarget->isTarget64BitLP64() ? 8 : 4, DL));
15764 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(), PtrVT);
15765 Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN, MachinePointerInfo(
15766 SV, Subtarget->isTarget64BitLP64() ? 16 : 12), false, false, 0);
15767 MemOps.push_back(Store);
15768 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps);
15771 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
15772 assert(Subtarget->is64Bit() &&
15773 "LowerVAARG only handles 64-bit va_arg!");
15774 assert(Op.getNode()->getNumOperands() == 4);
15776 MachineFunction &MF = DAG.getMachineFunction();
15777 if (Subtarget->isCallingConvWin64(MF.getFunction()->getCallingConv()))
15778 // The Win64 ABI uses char* instead of a structure.
15779 return DAG.expandVAArg(Op.getNode());
15781 SDValue Chain = Op.getOperand(0);
15782 SDValue SrcPtr = Op.getOperand(1);
15783 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
15784 unsigned Align = Op.getConstantOperandVal(3);
15787 EVT ArgVT = Op.getNode()->getValueType(0);
15788 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
15789 uint32_t ArgSize = DAG.getDataLayout().getTypeAllocSize(ArgTy);
15792 // Decide which area this value should be read from.
15793 // TODO: Implement the AMD64 ABI in its entirety. This simple
15794 // selection mechanism works only for the basic types.
15795 if (ArgVT == MVT::f80) {
15796 llvm_unreachable("va_arg for f80 not yet implemented");
15797 } else if (ArgVT.isFloatingPoint() && ArgSize <= 16 /*bytes*/) {
15798 ArgMode = 2; // Argument passed in XMM register. Use fp_offset.
15799 } else if (ArgVT.isInteger() && ArgSize <= 32 /*bytes*/) {
15800 ArgMode = 1; // Argument passed in GPR64 register(s). Use gp_offset.
15802 llvm_unreachable("Unhandled argument type in LowerVAARG");
15805 if (ArgMode == 2) {
15806 // Sanity Check: Make sure using fp_offset makes sense.
15807 assert(!Subtarget->useSoftFloat() &&
15808 !(MF.getFunction()->hasFnAttribute(Attribute::NoImplicitFloat)) &&
15809 Subtarget->hasSSE1());
15812 // Insert VAARG_64 node into the DAG
15813 // VAARG_64 returns two values: Variable Argument Address, Chain
15814 SDValue InstOps[] = {Chain, SrcPtr, DAG.getConstant(ArgSize, dl, MVT::i32),
15815 DAG.getConstant(ArgMode, dl, MVT::i8),
15816 DAG.getConstant(Align, dl, MVT::i32)};
15817 SDVTList VTs = DAG.getVTList(getPointerTy(DAG.getDataLayout()), MVT::Other);
15818 SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl,
15819 VTs, InstOps, MVT::i64,
15820 MachinePointerInfo(SV),
15822 /*Volatile=*/false,
15824 /*WriteMem=*/true);
15825 Chain = VAARG.getValue(1);
15827 // Load the next argument and return it
15828 return DAG.getLoad(ArgVT, dl,
15831 MachinePointerInfo(),
15832 false, false, false, 0);
15835 static SDValue LowerVACOPY(SDValue Op, const X86Subtarget *Subtarget,
15836 SelectionDAG &DAG) {
15837 // X86-64 va_list is a struct { i32, i32, i8*, i8* }, except on Windows,
15838 // where a va_list is still an i8*.
15839 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
15840 if (Subtarget->isCallingConvWin64(
15841 DAG.getMachineFunction().getFunction()->getCallingConv()))
15842 // Probably a Win64 va_copy.
15843 return DAG.expandVACopy(Op.getNode());
15845 SDValue Chain = Op.getOperand(0);
15846 SDValue DstPtr = Op.getOperand(1);
15847 SDValue SrcPtr = Op.getOperand(2);
15848 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
15849 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
15852 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr,
15853 DAG.getIntPtrConstant(24, DL), 8, /*isVolatile*/false,
15855 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
15858 // getTargetVShiftByConstNode - Handle vector element shifts where the shift
15859 // amount is a constant. Takes immediate version of shift as input.
15860 static SDValue getTargetVShiftByConstNode(unsigned Opc, SDLoc dl, MVT VT,
15861 SDValue SrcOp, uint64_t ShiftAmt,
15862 SelectionDAG &DAG) {
15863 MVT ElementType = VT.getVectorElementType();
15865 // Fold this packed shift into its first operand if ShiftAmt is 0.
15869 // Check for ShiftAmt >= element width
15870 if (ShiftAmt >= ElementType.getSizeInBits()) {
15871 if (Opc == X86ISD::VSRAI)
15872 ShiftAmt = ElementType.getSizeInBits() - 1;
15874 return DAG.getConstant(0, dl, VT);
15877 assert((Opc == X86ISD::VSHLI || Opc == X86ISD::VSRLI || Opc == X86ISD::VSRAI)
15878 && "Unknown target vector shift-by-constant node");
15880 // Fold this packed vector shift into a build vector if SrcOp is a
15881 // vector of Constants or UNDEFs, and SrcOp valuetype is the same as VT.
15882 if (VT == SrcOp.getSimpleValueType() &&
15883 ISD::isBuildVectorOfConstantSDNodes(SrcOp.getNode())) {
15884 SmallVector<SDValue, 8> Elts;
15885 unsigned NumElts = SrcOp->getNumOperands();
15886 ConstantSDNode *ND;
15889 default: llvm_unreachable(nullptr);
15890 case X86ISD::VSHLI:
15891 for (unsigned i=0; i!=NumElts; ++i) {
15892 SDValue CurrentOp = SrcOp->getOperand(i);
15893 if (CurrentOp->getOpcode() == ISD::UNDEF) {
15894 Elts.push_back(CurrentOp);
15897 ND = cast<ConstantSDNode>(CurrentOp);
15898 const APInt &C = ND->getAPIntValue();
15899 Elts.push_back(DAG.getConstant(C.shl(ShiftAmt), dl, ElementType));
15902 case X86ISD::VSRLI:
15903 for (unsigned i=0; i!=NumElts; ++i) {
15904 SDValue CurrentOp = SrcOp->getOperand(i);
15905 if (CurrentOp->getOpcode() == ISD::UNDEF) {
15906 Elts.push_back(CurrentOp);
15909 ND = cast<ConstantSDNode>(CurrentOp);
15910 const APInt &C = ND->getAPIntValue();
15911 Elts.push_back(DAG.getConstant(C.lshr(ShiftAmt), dl, ElementType));
15914 case X86ISD::VSRAI:
15915 for (unsigned i=0; i!=NumElts; ++i) {
15916 SDValue CurrentOp = SrcOp->getOperand(i);
15917 if (CurrentOp->getOpcode() == ISD::UNDEF) {
15918 Elts.push_back(CurrentOp);
15921 ND = cast<ConstantSDNode>(CurrentOp);
15922 const APInt &C = ND->getAPIntValue();
15923 Elts.push_back(DAG.getConstant(C.ashr(ShiftAmt), dl, ElementType));
15928 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
15931 return DAG.getNode(Opc, dl, VT, SrcOp,
15932 DAG.getConstant(ShiftAmt, dl, MVT::i8));
15935 // getTargetVShiftNode - Handle vector element shifts where the shift amount
15936 // may or may not be a constant. Takes immediate version of shift as input.
15937 static SDValue getTargetVShiftNode(unsigned Opc, SDLoc dl, MVT VT,
15938 SDValue SrcOp, SDValue ShAmt,
15939 SelectionDAG &DAG) {
15940 MVT SVT = ShAmt.getSimpleValueType();
15941 assert((SVT == MVT::i32 || SVT == MVT::i64) && "Unexpected value type!");
15943 // Catch shift-by-constant.
15944 if (ConstantSDNode *CShAmt = dyn_cast<ConstantSDNode>(ShAmt))
15945 return getTargetVShiftByConstNode(Opc, dl, VT, SrcOp,
15946 CShAmt->getZExtValue(), DAG);
15948 // Change opcode to non-immediate version
15950 default: llvm_unreachable("Unknown target vector shift node");
15951 case X86ISD::VSHLI: Opc = X86ISD::VSHL; break;
15952 case X86ISD::VSRLI: Opc = X86ISD::VSRL; break;
15953 case X86ISD::VSRAI: Opc = X86ISD::VSRA; break;
15956 const X86Subtarget &Subtarget =
15957 static_cast<const X86Subtarget &>(DAG.getSubtarget());
15958 if (Subtarget.hasSSE41() && ShAmt.getOpcode() == ISD::ZERO_EXTEND &&
15959 ShAmt.getOperand(0).getSimpleValueType() == MVT::i16) {
15960 // Let the shuffle legalizer expand this shift amount node.
15961 SDValue Op0 = ShAmt.getOperand(0);
15962 Op0 = DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(Op0), MVT::v8i16, Op0);
15963 ShAmt = getShuffleVectorZeroOrUndef(Op0, 0, true, &Subtarget, DAG);
15965 // Need to build a vector containing shift amount.
15966 // SSE/AVX packed shifts only use the lower 64-bit of the shift count.
15967 SmallVector<SDValue, 4> ShOps;
15968 ShOps.push_back(ShAmt);
15969 if (SVT == MVT::i32) {
15970 ShOps.push_back(DAG.getConstant(0, dl, SVT));
15971 ShOps.push_back(DAG.getUNDEF(SVT));
15973 ShOps.push_back(DAG.getUNDEF(SVT));
15975 MVT BVT = SVT == MVT::i32 ? MVT::v4i32 : MVT::v2i64;
15976 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, BVT, ShOps);
15979 // The return type has to be a 128-bit type with the same element
15980 // type as the input type.
15981 MVT EltVT = VT.getVectorElementType();
15982 MVT ShVT = MVT::getVectorVT(EltVT, 128/EltVT.getSizeInBits());
15984 ShAmt = DAG.getBitcast(ShVT, ShAmt);
15985 return DAG.getNode(Opc, dl, VT, SrcOp, ShAmt);
15988 /// \brief Return Mask with the necessary casting or extending
15989 /// for \p Mask according to \p MaskVT when lowering masking intrinsics
15990 static SDValue getMaskNode(SDValue Mask, MVT MaskVT,
15991 const X86Subtarget *Subtarget,
15992 SelectionDAG &DAG, SDLoc dl) {
15994 if (MaskVT.bitsGT(Mask.getSimpleValueType())) {
15995 // Mask should be extended
15996 Mask = DAG.getNode(ISD::ANY_EXTEND, dl,
15997 MVT::getIntegerVT(MaskVT.getSizeInBits()), Mask);
16000 if (Mask.getSimpleValueType() == MVT::i64 && Subtarget->is32Bit()) {
16001 assert(MaskVT == MVT::v64i1 && "Unexpected mask VT!");
16002 assert(Subtarget->hasBWI() && "Expected AVX512BW target!");
16003 // In case 32bit mode, bitcast i64 is illegal, extend/split it.
16005 Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Mask,
16006 DAG.getConstant(0, dl, MVT::i32));
16007 Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Mask,
16008 DAG.getConstant(1, dl, MVT::i32));
16010 Lo = DAG.getNode(ISD::BITCAST, dl, MVT::v32i1, Lo);
16011 Hi = DAG.getNode(ISD::BITCAST, dl, MVT::v32i1, Hi);
16013 return DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v64i1, Hi, Lo);
16016 MVT BitcastVT = MVT::getVectorVT(MVT::i1,
16017 Mask.getSimpleValueType().getSizeInBits());
16018 // In case when MaskVT equals v2i1 or v4i1, low 2 or 4 elements
16019 // are extracted by EXTRACT_SUBVECTOR.
16020 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
16021 DAG.getBitcast(BitcastVT, Mask),
16022 DAG.getIntPtrConstant(0, dl));
16026 /// \brief Return (and \p Op, \p Mask) for compare instructions or
16027 /// (vselect \p Mask, \p Op, \p PreservedSrc) for others along with the
16028 /// necessary casting or extending for \p Mask when lowering masking intrinsics
16029 static SDValue getVectorMaskingNode(SDValue Op, SDValue Mask,
16030 SDValue PreservedSrc,
16031 const X86Subtarget *Subtarget,
16032 SelectionDAG &DAG) {
16033 MVT VT = Op.getSimpleValueType();
16034 MVT MaskVT = MVT::getVectorVT(MVT::i1, VT.getVectorNumElements());
16035 unsigned OpcodeSelect = ISD::VSELECT;
16038 if (isAllOnesConstant(Mask))
16041 SDValue VMask = getMaskNode(Mask, MaskVT, Subtarget, DAG, dl);
16043 switch (Op.getOpcode()) {
16045 case X86ISD::PCMPEQM:
16046 case X86ISD::PCMPGTM:
16048 case X86ISD::CMPMU:
16049 return DAG.getNode(ISD::AND, dl, VT, Op, VMask);
16050 case X86ISD::VFPCLASS:
16051 case X86ISD::VFPCLASSS:
16052 return DAG.getNode(ISD::OR, dl, VT, Op, VMask);
16053 case X86ISD::VTRUNC:
16054 case X86ISD::VTRUNCS:
16055 case X86ISD::VTRUNCUS:
16056 // We can't use ISD::VSELECT here because it is not always "Legal"
16057 // for the destination type. For example vpmovqb require only AVX512
16058 // and vselect that can operate on byte element type require BWI
16059 OpcodeSelect = X86ISD::SELECT;
16062 if (PreservedSrc.getOpcode() == ISD::UNDEF)
16063 PreservedSrc = getZeroVector(VT, Subtarget, DAG, dl);
16064 return DAG.getNode(OpcodeSelect, dl, VT, VMask, Op, PreservedSrc);
16067 /// \brief Creates an SDNode for a predicated scalar operation.
16068 /// \returns (X86vselect \p Mask, \p Op, \p PreservedSrc).
16069 /// The mask is coming as MVT::i8 and it should be truncated
16070 /// to MVT::i1 while lowering masking intrinsics.
16071 /// The main difference between ScalarMaskingNode and VectorMaskingNode is using
16072 /// "X86select" instead of "vselect". We just can't create the "vselect" node
16073 /// for a scalar instruction.
16074 static SDValue getScalarMaskingNode(SDValue Op, SDValue Mask,
16075 SDValue PreservedSrc,
16076 const X86Subtarget *Subtarget,
16077 SelectionDAG &DAG) {
16078 if (isAllOnesConstant(Mask))
16081 MVT VT = Op.getSimpleValueType();
16083 // The mask should be of type MVT::i1
16084 SDValue IMask = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, Mask);
16086 if (Op.getOpcode() == X86ISD::FSETCC)
16087 return DAG.getNode(ISD::AND, dl, VT, Op, IMask);
16088 if (Op.getOpcode() == X86ISD::VFPCLASS ||
16089 Op.getOpcode() == X86ISD::VFPCLASSS)
16090 return DAG.getNode(ISD::OR, dl, VT, Op, IMask);
16092 if (PreservedSrc.getOpcode() == ISD::UNDEF)
16093 PreservedSrc = getZeroVector(VT, Subtarget, DAG, dl);
16094 return DAG.getNode(X86ISD::SELECT, dl, VT, IMask, Op, PreservedSrc);
16097 static int getSEHRegistrationNodeSize(const Function *Fn) {
16098 if (!Fn->hasPersonalityFn())
16099 report_fatal_error(
16100 "querying registration node size for function without personality");
16101 // The RegNodeSize is 6 32-bit words for SEH and 4 for C++ EH. See
16102 // WinEHStatePass for the full struct definition.
16103 switch (classifyEHPersonality(Fn->getPersonalityFn())) {
16104 case EHPersonality::MSVC_X86SEH: return 24;
16105 case EHPersonality::MSVC_CXX: return 16;
16108 report_fatal_error("can only recover FP for MSVC EH personality functions");
16111 /// When the 32-bit MSVC runtime transfers control to us, either to an outlined
16112 /// function or when returning to a parent frame after catching an exception, we
16113 /// recover the parent frame pointer by doing arithmetic on the incoming EBP.
16114 /// Here's the math:
16115 /// RegNodeBase = EntryEBP - RegNodeSize
16116 /// ParentFP = RegNodeBase - RegNodeFrameOffset
16117 /// Subtracting RegNodeSize takes us to the offset of the registration node, and
16118 /// subtracting the offset (negative on x86) takes us back to the parent FP.
16119 static SDValue recoverFramePointer(SelectionDAG &DAG, const Function *Fn,
16120 SDValue EntryEBP) {
16121 MachineFunction &MF = DAG.getMachineFunction();
16124 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
16125 MVT PtrVT = TLI.getPointerTy(DAG.getDataLayout());
16127 // It's possible that the parent function no longer has a personality function
16128 // if the exceptional code was optimized away, in which case we just return
16129 // the incoming EBP.
16130 if (!Fn->hasPersonalityFn())
16133 int RegNodeSize = getSEHRegistrationNodeSize(Fn);
16135 // Get an MCSymbol that will ultimately resolve to the frame offset of the EH
16137 MCSymbol *OffsetSym =
16138 MF.getMMI().getContext().getOrCreateParentFrameOffsetSymbol(
16139 GlobalValue::getRealLinkageName(Fn->getName()));
16140 SDValue OffsetSymVal = DAG.getMCSymbol(OffsetSym, PtrVT);
16141 SDValue RegNodeFrameOffset =
16142 DAG.getNode(ISD::LOCAL_RECOVER, dl, PtrVT, OffsetSymVal);
16144 // RegNodeBase = EntryEBP - RegNodeSize
16145 // ParentFP = RegNodeBase - RegNodeFrameOffset
16146 SDValue RegNodeBase = DAG.getNode(ISD::SUB, dl, PtrVT, EntryEBP,
16147 DAG.getConstant(RegNodeSize, dl, PtrVT));
16148 return DAG.getNode(ISD::SUB, dl, PtrVT, RegNodeBase, RegNodeFrameOffset);
16151 static SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
16152 SelectionDAG &DAG) {
16154 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
16155 MVT VT = Op.getSimpleValueType();
16156 const IntrinsicData* IntrData = getIntrinsicWithoutChain(IntNo);
16158 switch(IntrData->Type) {
16159 case INTR_TYPE_1OP:
16160 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1));
16161 case INTR_TYPE_2OP:
16162 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
16164 case INTR_TYPE_2OP_IMM8:
16165 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
16166 DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op.getOperand(2)));
16167 case INTR_TYPE_3OP:
16168 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
16169 Op.getOperand(2), Op.getOperand(3));
16170 case INTR_TYPE_4OP:
16171 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
16172 Op.getOperand(2), Op.getOperand(3), Op.getOperand(4));
16173 case INTR_TYPE_1OP_MASK_RM: {
16174 SDValue Src = Op.getOperand(1);
16175 SDValue PassThru = Op.getOperand(2);
16176 SDValue Mask = Op.getOperand(3);
16177 SDValue RoundingMode;
16178 // We allways add rounding mode to the Node.
16179 // If the rounding mode is not specified, we add the
16180 // "current direction" mode.
16181 if (Op.getNumOperands() == 4)
16183 DAG.getConstant(X86::STATIC_ROUNDING::CUR_DIRECTION, dl, MVT::i32);
16185 RoundingMode = Op.getOperand(4);
16186 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1;
16187 if (IntrWithRoundingModeOpcode != 0)
16188 if (cast<ConstantSDNode>(RoundingMode)->getZExtValue() !=
16189 X86::STATIC_ROUNDING::CUR_DIRECTION)
16190 return getVectorMaskingNode(DAG.getNode(IntrWithRoundingModeOpcode,
16191 dl, Op.getValueType(), Src, RoundingMode),
16192 Mask, PassThru, Subtarget, DAG);
16193 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src,
16195 Mask, PassThru, Subtarget, DAG);
16197 case INTR_TYPE_1OP_MASK: {
16198 SDValue Src = Op.getOperand(1);
16199 SDValue PassThru = Op.getOperand(2);
16200 SDValue Mask = Op.getOperand(3);
16201 // We add rounding mode to the Node when
16202 // - RM Opcode is specified and
16203 // - RM is not "current direction".
16204 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1;
16205 if (IntrWithRoundingModeOpcode != 0) {
16206 SDValue Rnd = Op.getOperand(4);
16207 unsigned Round = cast<ConstantSDNode>(Rnd)->getZExtValue();
16208 if (Round != X86::STATIC_ROUNDING::CUR_DIRECTION) {
16209 return getVectorMaskingNode(DAG.getNode(IntrWithRoundingModeOpcode,
16210 dl, Op.getValueType(),
16212 Mask, PassThru, Subtarget, DAG);
16215 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src),
16216 Mask, PassThru, Subtarget, DAG);
16218 case INTR_TYPE_SCALAR_MASK: {
16219 SDValue Src1 = Op.getOperand(1);
16220 SDValue Src2 = Op.getOperand(2);
16221 SDValue passThru = Op.getOperand(3);
16222 SDValue Mask = Op.getOperand(4);
16223 return getScalarMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src1, Src2),
16224 Mask, passThru, Subtarget, DAG);
16226 case INTR_TYPE_SCALAR_MASK_RM: {
16227 SDValue Src1 = Op.getOperand(1);
16228 SDValue Src2 = Op.getOperand(2);
16229 SDValue Src0 = Op.getOperand(3);
16230 SDValue Mask = Op.getOperand(4);
16231 // There are 2 kinds of intrinsics in this group:
16232 // (1) With suppress-all-exceptions (sae) or rounding mode- 6 operands
16233 // (2) With rounding mode and sae - 7 operands.
16234 if (Op.getNumOperands() == 6) {
16235 SDValue Sae = Op.getOperand(5);
16236 unsigned Opc = IntrData->Opc1 ? IntrData->Opc1 : IntrData->Opc0;
16237 return getScalarMaskingNode(DAG.getNode(Opc, dl, VT, Src1, Src2,
16239 Mask, Src0, Subtarget, DAG);
16241 assert(Op.getNumOperands() == 7 && "Unexpected intrinsic form");
16242 SDValue RoundingMode = Op.getOperand(5);
16243 SDValue Sae = Op.getOperand(6);
16244 return getScalarMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src1, Src2,
16245 RoundingMode, Sae),
16246 Mask, Src0, Subtarget, DAG);
16248 case INTR_TYPE_2OP_MASK:
16249 case INTR_TYPE_2OP_IMM8_MASK: {
16250 SDValue Src1 = Op.getOperand(1);
16251 SDValue Src2 = Op.getOperand(2);
16252 SDValue PassThru = Op.getOperand(3);
16253 SDValue Mask = Op.getOperand(4);
16255 if (IntrData->Type == INTR_TYPE_2OP_IMM8_MASK)
16256 Src2 = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Src2);
16258 // We specify 2 possible opcodes for intrinsics with rounding modes.
16259 // First, we check if the intrinsic may have non-default rounding mode,
16260 // (IntrData->Opc1 != 0), then we check the rounding mode operand.
16261 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1;
16262 if (IntrWithRoundingModeOpcode != 0) {
16263 SDValue Rnd = Op.getOperand(5);
16264 unsigned Round = cast<ConstantSDNode>(Rnd)->getZExtValue();
16265 if (Round != X86::STATIC_ROUNDING::CUR_DIRECTION) {
16266 return getVectorMaskingNode(DAG.getNode(IntrWithRoundingModeOpcode,
16267 dl, Op.getValueType(),
16269 Mask, PassThru, Subtarget, DAG);
16272 // TODO: Intrinsics should have fast-math-flags to propagate.
16273 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT,Src1,Src2),
16274 Mask, PassThru, Subtarget, DAG);
16276 case INTR_TYPE_2OP_MASK_RM: {
16277 SDValue Src1 = Op.getOperand(1);
16278 SDValue Src2 = Op.getOperand(2);
16279 SDValue PassThru = Op.getOperand(3);
16280 SDValue Mask = Op.getOperand(4);
16281 // We specify 2 possible modes for intrinsics, with/without rounding
16283 // First, we check if the intrinsic have rounding mode (6 operands),
16284 // if not, we set rounding mode to "current".
16286 if (Op.getNumOperands() == 6)
16287 Rnd = Op.getOperand(5);
16289 Rnd = DAG.getConstant(X86::STATIC_ROUNDING::CUR_DIRECTION, dl, MVT::i32);
16290 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT,
16292 Mask, PassThru, Subtarget, DAG);
16294 case INTR_TYPE_3OP_SCALAR_MASK_RM: {
16295 SDValue Src1 = Op.getOperand(1);
16296 SDValue Src2 = Op.getOperand(2);
16297 SDValue Src3 = Op.getOperand(3);
16298 SDValue PassThru = Op.getOperand(4);
16299 SDValue Mask = Op.getOperand(5);
16300 SDValue Sae = Op.getOperand(6);
16302 return getScalarMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src1,
16304 Mask, PassThru, Subtarget, DAG);
16306 case INTR_TYPE_3OP_MASK_RM: {
16307 SDValue Src1 = Op.getOperand(1);
16308 SDValue Src2 = Op.getOperand(2);
16309 SDValue Imm = Op.getOperand(3);
16310 SDValue PassThru = Op.getOperand(4);
16311 SDValue Mask = Op.getOperand(5);
16312 // We specify 2 possible modes for intrinsics, with/without rounding
16314 // First, we check if the intrinsic have rounding mode (7 operands),
16315 // if not, we set rounding mode to "current".
16317 if (Op.getNumOperands() == 7)
16318 Rnd = Op.getOperand(6);
16320 Rnd = DAG.getConstant(X86::STATIC_ROUNDING::CUR_DIRECTION, dl, MVT::i32);
16321 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT,
16322 Src1, Src2, Imm, Rnd),
16323 Mask, PassThru, Subtarget, DAG);
16325 case INTR_TYPE_3OP_IMM8_MASK:
16326 case INTR_TYPE_3OP_MASK:
16327 case INSERT_SUBVEC: {
16328 SDValue Src1 = Op.getOperand(1);
16329 SDValue Src2 = Op.getOperand(2);
16330 SDValue Src3 = Op.getOperand(3);
16331 SDValue PassThru = Op.getOperand(4);
16332 SDValue Mask = Op.getOperand(5);
16334 if (IntrData->Type == INTR_TYPE_3OP_IMM8_MASK)
16335 Src3 = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Src3);
16336 else if (IntrData->Type == INSERT_SUBVEC) {
16337 // imm should be adapted to ISD::INSERT_SUBVECTOR behavior
16338 assert(isa<ConstantSDNode>(Src3) && "Expected a ConstantSDNode here!");
16339 unsigned Imm = cast<ConstantSDNode>(Src3)->getZExtValue();
16340 Imm *= Src2.getSimpleValueType().getVectorNumElements();
16341 Src3 = DAG.getTargetConstant(Imm, dl, MVT::i32);
16344 // We specify 2 possible opcodes for intrinsics with rounding modes.
16345 // First, we check if the intrinsic may have non-default rounding mode,
16346 // (IntrData->Opc1 != 0), then we check the rounding mode operand.
16347 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1;
16348 if (IntrWithRoundingModeOpcode != 0) {
16349 SDValue Rnd = Op.getOperand(6);
16350 unsigned Round = cast<ConstantSDNode>(Rnd)->getZExtValue();
16351 if (Round != X86::STATIC_ROUNDING::CUR_DIRECTION) {
16352 return getVectorMaskingNode(DAG.getNode(IntrWithRoundingModeOpcode,
16353 dl, Op.getValueType(),
16354 Src1, Src2, Src3, Rnd),
16355 Mask, PassThru, Subtarget, DAG);
16358 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT,
16360 Mask, PassThru, Subtarget, DAG);
16362 case VPERM_3OP_MASKZ:
16363 case VPERM_3OP_MASK:{
16364 // Src2 is the PassThru
16365 SDValue Src1 = Op.getOperand(1);
16366 SDValue Src2 = Op.getOperand(2);
16367 SDValue Src3 = Op.getOperand(3);
16368 SDValue Mask = Op.getOperand(4);
16369 MVT VT = Op.getSimpleValueType();
16370 SDValue PassThru = SDValue();
16372 // set PassThru element
16373 if (IntrData->Type == VPERM_3OP_MASKZ)
16374 PassThru = getZeroVector(VT, Subtarget, DAG, dl);
16376 PassThru = DAG.getBitcast(VT, Src2);
16378 // Swap Src1 and Src2 in the node creation
16379 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0,
16380 dl, Op.getValueType(),
16382 Mask, PassThru, Subtarget, DAG);
16386 case FMA_OP_MASK: {
16387 SDValue Src1 = Op.getOperand(1);
16388 SDValue Src2 = Op.getOperand(2);
16389 SDValue Src3 = Op.getOperand(3);
16390 SDValue Mask = Op.getOperand(4);
16391 MVT VT = Op.getSimpleValueType();
16392 SDValue PassThru = SDValue();
16394 // set PassThru element
16395 if (IntrData->Type == FMA_OP_MASKZ)
16396 PassThru = getZeroVector(VT, Subtarget, DAG, dl);
16397 else if (IntrData->Type == FMA_OP_MASK3)
16402 // We specify 2 possible opcodes for intrinsics with rounding modes.
16403 // First, we check if the intrinsic may have non-default rounding mode,
16404 // (IntrData->Opc1 != 0), then we check the rounding mode operand.
16405 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1;
16406 if (IntrWithRoundingModeOpcode != 0) {
16407 SDValue Rnd = Op.getOperand(5);
16408 if (cast<ConstantSDNode>(Rnd)->getZExtValue() !=
16409 X86::STATIC_ROUNDING::CUR_DIRECTION)
16410 return getVectorMaskingNode(DAG.getNode(IntrWithRoundingModeOpcode,
16411 dl, Op.getValueType(),
16412 Src1, Src2, Src3, Rnd),
16413 Mask, PassThru, Subtarget, DAG);
16415 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0,
16416 dl, Op.getValueType(),
16418 Mask, PassThru, Subtarget, DAG);
16420 case TERLOG_OP_MASK:
16421 case TERLOG_OP_MASKZ: {
16422 SDValue Src1 = Op.getOperand(1);
16423 SDValue Src2 = Op.getOperand(2);
16424 SDValue Src3 = Op.getOperand(3);
16425 SDValue Src4 = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op.getOperand(4));
16426 SDValue Mask = Op.getOperand(5);
16427 MVT VT = Op.getSimpleValueType();
16428 SDValue PassThru = Src1;
16429 // Set PassThru element.
16430 if (IntrData->Type == TERLOG_OP_MASKZ)
16431 PassThru = getZeroVector(VT, Subtarget, DAG, dl);
16433 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT,
16434 Src1, Src2, Src3, Src4),
16435 Mask, PassThru, Subtarget, DAG);
16438 // FPclass intrinsics with mask
16439 SDValue Src1 = Op.getOperand(1);
16440 MVT VT = Src1.getSimpleValueType();
16441 MVT MaskVT = MVT::getVectorVT(MVT::i1, VT.getVectorNumElements());
16442 SDValue Imm = Op.getOperand(2);
16443 SDValue Mask = Op.getOperand(3);
16444 MVT BitcastVT = MVT::getVectorVT(MVT::i1,
16445 Mask.getSimpleValueType().getSizeInBits());
16446 SDValue FPclass = DAG.getNode(IntrData->Opc0, dl, MaskVT, Src1, Imm);
16447 SDValue FPclassMask = getVectorMaskingNode(FPclass, Mask,
16448 DAG.getTargetConstant(0, dl, MaskVT),
16450 SDValue Res = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, BitcastVT,
16451 DAG.getUNDEF(BitcastVT), FPclassMask,
16452 DAG.getIntPtrConstant(0, dl));
16453 return DAG.getBitcast(Op.getValueType(), Res);
16456 SDValue Src1 = Op.getOperand(1);
16457 SDValue Imm = Op.getOperand(2);
16458 SDValue Mask = Op.getOperand(3);
16459 SDValue FPclass = DAG.getNode(IntrData->Opc0, dl, MVT::i1, Src1, Imm);
16460 SDValue FPclassMask = getScalarMaskingNode(FPclass, Mask,
16461 DAG.getTargetConstant(0, dl, MVT::i1), Subtarget, DAG);
16462 return DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i8, FPclassMask);
16465 case CMP_MASK_CC: {
16466 // Comparison intrinsics with masks.
16467 // Example of transformation:
16468 // (i8 (int_x86_avx512_mask_pcmpeq_q_128
16469 // (v2i64 %a), (v2i64 %b), (i8 %mask))) ->
16471 // (v8i1 (insert_subvector undef,
16472 // (v2i1 (and (PCMPEQM %a, %b),
16473 // (extract_subvector
16474 // (v8i1 (bitcast %mask)), 0))), 0))))
16475 MVT VT = Op.getOperand(1).getSimpleValueType();
16476 MVT MaskVT = MVT::getVectorVT(MVT::i1, VT.getVectorNumElements());
16477 SDValue Mask = Op.getOperand((IntrData->Type == CMP_MASK_CC) ? 4 : 3);
16478 MVT BitcastVT = MVT::getVectorVT(MVT::i1,
16479 Mask.getSimpleValueType().getSizeInBits());
16481 if (IntrData->Type == CMP_MASK_CC) {
16482 SDValue CC = Op.getOperand(3);
16483 CC = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, CC);
16484 // We specify 2 possible opcodes for intrinsics with rounding modes.
16485 // First, we check if the intrinsic may have non-default rounding mode,
16486 // (IntrData->Opc1 != 0), then we check the rounding mode operand.
16487 if (IntrData->Opc1 != 0) {
16488 SDValue Rnd = Op.getOperand(5);
16489 if (cast<ConstantSDNode>(Rnd)->getZExtValue() !=
16490 X86::STATIC_ROUNDING::CUR_DIRECTION)
16491 Cmp = DAG.getNode(IntrData->Opc1, dl, MaskVT, Op.getOperand(1),
16492 Op.getOperand(2), CC, Rnd);
16494 //default rounding mode
16496 Cmp = DAG.getNode(IntrData->Opc0, dl, MaskVT, Op.getOperand(1),
16497 Op.getOperand(2), CC);
16500 assert(IntrData->Type == CMP_MASK && "Unexpected intrinsic type!");
16501 Cmp = DAG.getNode(IntrData->Opc0, dl, MaskVT, Op.getOperand(1),
16504 SDValue CmpMask = getVectorMaskingNode(Cmp, Mask,
16505 DAG.getTargetConstant(0, dl,
16508 SDValue Res = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, BitcastVT,
16509 DAG.getUNDEF(BitcastVT), CmpMask,
16510 DAG.getIntPtrConstant(0, dl));
16511 return DAG.getBitcast(Op.getValueType(), Res);
16513 case CMP_MASK_SCALAR_CC: {
16514 SDValue Src1 = Op.getOperand(1);
16515 SDValue Src2 = Op.getOperand(2);
16516 SDValue CC = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op.getOperand(3));
16517 SDValue Mask = Op.getOperand(4);
16520 if (IntrData->Opc1 != 0) {
16521 SDValue Rnd = Op.getOperand(5);
16522 if (cast<ConstantSDNode>(Rnd)->getZExtValue() !=
16523 X86::STATIC_ROUNDING::CUR_DIRECTION)
16524 Cmp = DAG.getNode(IntrData->Opc1, dl, MVT::i1, Src1, Src2, CC, Rnd);
16526 //default rounding mode
16528 Cmp = DAG.getNode(IntrData->Opc0, dl, MVT::i1, Src1, Src2, CC);
16530 SDValue CmpMask = getScalarMaskingNode(Cmp, Mask,
16531 DAG.getTargetConstant(0, dl,
16535 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::i8,
16536 DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i8, CmpMask),
16537 DAG.getValueType(MVT::i1));
16539 case COMI: { // Comparison intrinsics
16540 ISD::CondCode CC = (ISD::CondCode)IntrData->Opc1;
16541 SDValue LHS = Op.getOperand(1);
16542 SDValue RHS = Op.getOperand(2);
16543 unsigned X86CC = TranslateX86CC(CC, dl, true, LHS, RHS, DAG);
16544 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!");
16545 SDValue Cond = DAG.getNode(IntrData->Opc0, dl, MVT::i32, LHS, RHS);
16546 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
16547 DAG.getConstant(X86CC, dl, MVT::i8), Cond);
16548 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
16550 case COMI_RM: { // Comparison intrinsics with Sae
16551 SDValue LHS = Op.getOperand(1);
16552 SDValue RHS = Op.getOperand(2);
16553 SDValue CC = Op.getOperand(3);
16554 SDValue Sae = Op.getOperand(4);
16555 auto ComiType = TranslateX86ConstCondToX86CC(CC);
16556 // choose between ordered and unordered (comi/ucomi)
16557 unsigned comiOp = std::get<0>(ComiType) ? IntrData->Opc0 : IntrData->Opc1;
16559 if (cast<ConstantSDNode>(Sae)->getZExtValue() !=
16560 X86::STATIC_ROUNDING::CUR_DIRECTION)
16561 Cond = DAG.getNode(comiOp, dl, MVT::i32, LHS, RHS, Sae);
16563 Cond = DAG.getNode(comiOp, dl, MVT::i32, LHS, RHS);
16564 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
16565 DAG.getConstant(std::get<1>(ComiType), dl, MVT::i8), Cond);
16566 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
16569 return getTargetVShiftNode(IntrData->Opc0, dl, Op.getSimpleValueType(),
16570 Op.getOperand(1), Op.getOperand(2), DAG);
16572 return getVectorMaskingNode(getTargetVShiftNode(IntrData->Opc0, dl,
16573 Op.getSimpleValueType(),
16575 Op.getOperand(2), DAG),
16576 Op.getOperand(4), Op.getOperand(3), Subtarget,
16578 case COMPRESS_EXPAND_IN_REG: {
16579 SDValue Mask = Op.getOperand(3);
16580 SDValue DataToCompress = Op.getOperand(1);
16581 SDValue PassThru = Op.getOperand(2);
16582 if (isAllOnesConstant(Mask)) // return data as is
16583 return Op.getOperand(1);
16585 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT,
16587 Mask, PassThru, Subtarget, DAG);
16590 SDValue Mask = Op.getOperand(1);
16591 MVT MaskVT = MVT::getVectorVT(MVT::i1, Mask.getSimpleValueType().getSizeInBits());
16592 Mask = DAG.getBitcast(MaskVT, Mask);
16593 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Mask);
16596 SDValue Mask = Op.getOperand(3);
16597 MVT VT = Op.getSimpleValueType();
16598 MVT MaskVT = MVT::getVectorVT(MVT::i1, VT.getVectorNumElements());
16599 SDValue VMask = getMaskNode(Mask, MaskVT, Subtarget, DAG, dl);
16600 return DAG.getNode(IntrData->Opc0, dl, VT, VMask, Op.getOperand(1),
16609 default: return SDValue(); // Don't custom lower most intrinsics.
16611 case Intrinsic::x86_avx2_permd:
16612 case Intrinsic::x86_avx2_permps:
16613 // Operands intentionally swapped. Mask is last operand to intrinsic,
16614 // but second operand for node/instruction.
16615 return DAG.getNode(X86ISD::VPERMV, dl, Op.getValueType(),
16616 Op.getOperand(2), Op.getOperand(1));
16618 // ptest and testp intrinsics. The intrinsic these come from are designed to
16619 // return an integer value, not just an instruction so lower it to the ptest
16620 // or testp pattern and a setcc for the result.
16621 case Intrinsic::x86_sse41_ptestz:
16622 case Intrinsic::x86_sse41_ptestc:
16623 case Intrinsic::x86_sse41_ptestnzc:
16624 case Intrinsic::x86_avx_ptestz_256:
16625 case Intrinsic::x86_avx_ptestc_256:
16626 case Intrinsic::x86_avx_ptestnzc_256:
16627 case Intrinsic::x86_avx_vtestz_ps:
16628 case Intrinsic::x86_avx_vtestc_ps:
16629 case Intrinsic::x86_avx_vtestnzc_ps:
16630 case Intrinsic::x86_avx_vtestz_pd:
16631 case Intrinsic::x86_avx_vtestc_pd:
16632 case Intrinsic::x86_avx_vtestnzc_pd:
16633 case Intrinsic::x86_avx_vtestz_ps_256:
16634 case Intrinsic::x86_avx_vtestc_ps_256:
16635 case Intrinsic::x86_avx_vtestnzc_ps_256:
16636 case Intrinsic::x86_avx_vtestz_pd_256:
16637 case Intrinsic::x86_avx_vtestc_pd_256:
16638 case Intrinsic::x86_avx_vtestnzc_pd_256: {
16639 bool IsTestPacked = false;
16642 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
16643 case Intrinsic::x86_avx_vtestz_ps:
16644 case Intrinsic::x86_avx_vtestz_pd:
16645 case Intrinsic::x86_avx_vtestz_ps_256:
16646 case Intrinsic::x86_avx_vtestz_pd_256:
16647 IsTestPacked = true; // Fallthrough
16648 case Intrinsic::x86_sse41_ptestz:
16649 case Intrinsic::x86_avx_ptestz_256:
16651 X86CC = X86::COND_E;
16653 case Intrinsic::x86_avx_vtestc_ps:
16654 case Intrinsic::x86_avx_vtestc_pd:
16655 case Intrinsic::x86_avx_vtestc_ps_256:
16656 case Intrinsic::x86_avx_vtestc_pd_256:
16657 IsTestPacked = true; // Fallthrough
16658 case Intrinsic::x86_sse41_ptestc:
16659 case Intrinsic::x86_avx_ptestc_256:
16661 X86CC = X86::COND_B;
16663 case Intrinsic::x86_avx_vtestnzc_ps:
16664 case Intrinsic::x86_avx_vtestnzc_pd:
16665 case Intrinsic::x86_avx_vtestnzc_ps_256:
16666 case Intrinsic::x86_avx_vtestnzc_pd_256:
16667 IsTestPacked = true; // Fallthrough
16668 case Intrinsic::x86_sse41_ptestnzc:
16669 case Intrinsic::x86_avx_ptestnzc_256:
16671 X86CC = X86::COND_A;
16675 SDValue LHS = Op.getOperand(1);
16676 SDValue RHS = Op.getOperand(2);
16677 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST;
16678 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS);
16679 SDValue CC = DAG.getConstant(X86CC, dl, MVT::i8);
16680 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
16681 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
16683 case Intrinsic::x86_avx512_kortestz_w:
16684 case Intrinsic::x86_avx512_kortestc_w: {
16685 unsigned X86CC = (IntNo == Intrinsic::x86_avx512_kortestz_w)? X86::COND_E: X86::COND_B;
16686 SDValue LHS = DAG.getBitcast(MVT::v16i1, Op.getOperand(1));
16687 SDValue RHS = DAG.getBitcast(MVT::v16i1, Op.getOperand(2));
16688 SDValue CC = DAG.getConstant(X86CC, dl, MVT::i8);
16689 SDValue Test = DAG.getNode(X86ISD::KORTEST, dl, MVT::i32, LHS, RHS);
16690 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i1, CC, Test);
16691 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
16694 case Intrinsic::x86_sse42_pcmpistria128:
16695 case Intrinsic::x86_sse42_pcmpestria128:
16696 case Intrinsic::x86_sse42_pcmpistric128:
16697 case Intrinsic::x86_sse42_pcmpestric128:
16698 case Intrinsic::x86_sse42_pcmpistrio128:
16699 case Intrinsic::x86_sse42_pcmpestrio128:
16700 case Intrinsic::x86_sse42_pcmpistris128:
16701 case Intrinsic::x86_sse42_pcmpestris128:
16702 case Intrinsic::x86_sse42_pcmpistriz128:
16703 case Intrinsic::x86_sse42_pcmpestriz128: {
16707 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
16708 case Intrinsic::x86_sse42_pcmpistria128:
16709 Opcode = X86ISD::PCMPISTRI;
16710 X86CC = X86::COND_A;
16712 case Intrinsic::x86_sse42_pcmpestria128:
16713 Opcode = X86ISD::PCMPESTRI;
16714 X86CC = X86::COND_A;
16716 case Intrinsic::x86_sse42_pcmpistric128:
16717 Opcode = X86ISD::PCMPISTRI;
16718 X86CC = X86::COND_B;
16720 case Intrinsic::x86_sse42_pcmpestric128:
16721 Opcode = X86ISD::PCMPESTRI;
16722 X86CC = X86::COND_B;
16724 case Intrinsic::x86_sse42_pcmpistrio128:
16725 Opcode = X86ISD::PCMPISTRI;
16726 X86CC = X86::COND_O;
16728 case Intrinsic::x86_sse42_pcmpestrio128:
16729 Opcode = X86ISD::PCMPESTRI;
16730 X86CC = X86::COND_O;
16732 case Intrinsic::x86_sse42_pcmpistris128:
16733 Opcode = X86ISD::PCMPISTRI;
16734 X86CC = X86::COND_S;
16736 case Intrinsic::x86_sse42_pcmpestris128:
16737 Opcode = X86ISD::PCMPESTRI;
16738 X86CC = X86::COND_S;
16740 case Intrinsic::x86_sse42_pcmpistriz128:
16741 Opcode = X86ISD::PCMPISTRI;
16742 X86CC = X86::COND_E;
16744 case Intrinsic::x86_sse42_pcmpestriz128:
16745 Opcode = X86ISD::PCMPESTRI;
16746 X86CC = X86::COND_E;
16749 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
16750 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
16751 SDValue PCMP = DAG.getNode(Opcode, dl, VTs, NewOps);
16752 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
16753 DAG.getConstant(X86CC, dl, MVT::i8),
16754 SDValue(PCMP.getNode(), 1));
16755 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
16758 case Intrinsic::x86_sse42_pcmpistri128:
16759 case Intrinsic::x86_sse42_pcmpestri128: {
16761 if (IntNo == Intrinsic::x86_sse42_pcmpistri128)
16762 Opcode = X86ISD::PCMPISTRI;
16764 Opcode = X86ISD::PCMPESTRI;
16766 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
16767 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
16768 return DAG.getNode(Opcode, dl, VTs, NewOps);
16771 case Intrinsic::x86_seh_lsda: {
16772 // Compute the symbol for the LSDA. We know it'll get emitted later.
16773 MachineFunction &MF = DAG.getMachineFunction();
16774 SDValue Op1 = Op.getOperand(1);
16775 auto *Fn = cast<Function>(cast<GlobalAddressSDNode>(Op1)->getGlobal());
16776 MCSymbol *LSDASym = MF.getMMI().getContext().getOrCreateLSDASymbol(
16777 GlobalValue::getRealLinkageName(Fn->getName()));
16779 // Generate a simple absolute symbol reference. This intrinsic is only
16780 // supported on 32-bit Windows, which isn't PIC.
16781 SDValue Result = DAG.getMCSymbol(LSDASym, VT);
16782 return DAG.getNode(X86ISD::Wrapper, dl, VT, Result);
16785 case Intrinsic::x86_seh_recoverfp: {
16786 SDValue FnOp = Op.getOperand(1);
16787 SDValue IncomingFPOp = Op.getOperand(2);
16788 GlobalAddressSDNode *GSD = dyn_cast<GlobalAddressSDNode>(FnOp);
16789 auto *Fn = dyn_cast_or_null<Function>(GSD ? GSD->getGlobal() : nullptr);
16791 report_fatal_error(
16792 "llvm.x86.seh.recoverfp must take a function as the first argument");
16793 return recoverFramePointer(DAG, Fn, IncomingFPOp);
16796 case Intrinsic::localaddress: {
16797 // Returns one of the stack, base, or frame pointer registers, depending on
16798 // which is used to reference local variables.
16799 MachineFunction &MF = DAG.getMachineFunction();
16800 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
16802 if (RegInfo->hasBasePointer(MF))
16803 Reg = RegInfo->getBaseRegister();
16804 else // This function handles the SP or FP case.
16805 Reg = RegInfo->getPtrSizedFrameRegister(MF);
16806 return DAG.getCopyFromReg(DAG.getEntryNode(), dl, Reg, VT);
16811 static SDValue getGatherNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
16812 SDValue Src, SDValue Mask, SDValue Base,
16813 SDValue Index, SDValue ScaleOp, SDValue Chain,
16814 const X86Subtarget * Subtarget) {
16816 auto *C = cast<ConstantSDNode>(ScaleOp);
16817 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), dl, MVT::i8);
16818 MVT MaskVT = MVT::getVectorVT(MVT::i1,
16819 Index.getSimpleValueType().getVectorNumElements());
16821 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
16823 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), dl, MaskVT);
16825 MVT BitcastVT = MVT::getVectorVT(MVT::i1,
16826 Mask.getSimpleValueType().getSizeInBits());
16828 // In case when MaskVT equals v2i1 or v4i1, low 2 or 4 elements
16829 // are extracted by EXTRACT_SUBVECTOR.
16830 MaskInReg = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
16831 DAG.getBitcast(BitcastVT, Mask),
16832 DAG.getIntPtrConstant(0, dl));
16834 SDVTList VTs = DAG.getVTList(Op.getValueType(), MaskVT, MVT::Other);
16835 SDValue Disp = DAG.getTargetConstant(0, dl, MVT::i32);
16836 SDValue Segment = DAG.getRegister(0, MVT::i32);
16837 if (Src.getOpcode() == ISD::UNDEF)
16838 Src = getZeroVector(Op.getSimpleValueType(), Subtarget, DAG, dl);
16839 SDValue Ops[] = {Src, MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
16840 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
16841 SDValue RetOps[] = { SDValue(Res, 0), SDValue(Res, 2) };
16842 return DAG.getMergeValues(RetOps, dl);
16845 static SDValue getScatterNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
16846 SDValue Src, SDValue Mask, SDValue Base,
16847 SDValue Index, SDValue ScaleOp, SDValue Chain) {
16849 auto *C = cast<ConstantSDNode>(ScaleOp);
16850 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), dl, MVT::i8);
16851 SDValue Disp = DAG.getTargetConstant(0, dl, MVT::i32);
16852 SDValue Segment = DAG.getRegister(0, MVT::i32);
16853 MVT MaskVT = MVT::getVectorVT(MVT::i1,
16854 Index.getSimpleValueType().getVectorNumElements());
16856 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
16858 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), dl, MaskVT);
16860 MVT BitcastVT = MVT::getVectorVT(MVT::i1,
16861 Mask.getSimpleValueType().getSizeInBits());
16863 // In case when MaskVT equals v2i1 or v4i1, low 2 or 4 elements
16864 // are extracted by EXTRACT_SUBVECTOR.
16865 MaskInReg = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
16866 DAG.getBitcast(BitcastVT, Mask),
16867 DAG.getIntPtrConstant(0, dl));
16869 SDVTList VTs = DAG.getVTList(MaskVT, MVT::Other);
16870 SDValue Ops[] = {Base, Scale, Index, Disp, Segment, MaskInReg, Src, Chain};
16871 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
16872 return SDValue(Res, 1);
16875 static SDValue getPrefetchNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
16876 SDValue Mask, SDValue Base, SDValue Index,
16877 SDValue ScaleOp, SDValue Chain) {
16879 auto *C = cast<ConstantSDNode>(ScaleOp);
16880 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), dl, MVT::i8);
16881 SDValue Disp = DAG.getTargetConstant(0, dl, MVT::i32);
16882 SDValue Segment = DAG.getRegister(0, MVT::i32);
16884 MVT::getVectorVT(MVT::i1, Index.getSimpleValueType().getVectorNumElements());
16886 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
16888 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), dl, MaskVT);
16890 MaskInReg = DAG.getBitcast(MaskVT, Mask);
16891 //SDVTList VTs = DAG.getVTList(MVT::Other);
16892 SDValue Ops[] = {MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
16893 SDNode *Res = DAG.getMachineNode(Opc, dl, MVT::Other, Ops);
16894 return SDValue(Res, 0);
16897 // getReadPerformanceCounter - Handles the lowering of builtin intrinsics that
16898 // read performance monitor counters (x86_rdpmc).
16899 static void getReadPerformanceCounter(SDNode *N, SDLoc DL,
16900 SelectionDAG &DAG, const X86Subtarget *Subtarget,
16901 SmallVectorImpl<SDValue> &Results) {
16902 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
16903 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
16906 // The ECX register is used to select the index of the performance counter
16908 SDValue Chain = DAG.getCopyToReg(N->getOperand(0), DL, X86::ECX,
16910 SDValue rd = DAG.getNode(X86ISD::RDPMC_DAG, DL, Tys, Chain);
16912 // Reads the content of a 64-bit performance counter and returns it in the
16913 // registers EDX:EAX.
16914 if (Subtarget->is64Bit()) {
16915 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
16916 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
16919 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
16920 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
16923 Chain = HI.getValue(1);
16925 if (Subtarget->is64Bit()) {
16926 // The EAX register is loaded with the low-order 32 bits. The EDX register
16927 // is loaded with the supported high-order bits of the counter.
16928 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
16929 DAG.getConstant(32, DL, MVT::i8));
16930 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
16931 Results.push_back(Chain);
16935 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
16936 SDValue Ops[] = { LO, HI };
16937 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
16938 Results.push_back(Pair);
16939 Results.push_back(Chain);
16942 // getReadTimeStampCounter - Handles the lowering of builtin intrinsics that
16943 // read the time stamp counter (x86_rdtsc and x86_rdtscp). This function is
16944 // also used to custom lower READCYCLECOUNTER nodes.
16945 static void getReadTimeStampCounter(SDNode *N, SDLoc DL, unsigned Opcode,
16946 SelectionDAG &DAG, const X86Subtarget *Subtarget,
16947 SmallVectorImpl<SDValue> &Results) {
16948 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
16949 SDValue rd = DAG.getNode(Opcode, DL, Tys, N->getOperand(0));
16952 // The processor's time-stamp counter (a 64-bit MSR) is stored into the
16953 // EDX:EAX registers. EDX is loaded with the high-order 32 bits of the MSR
16954 // and the EAX register is loaded with the low-order 32 bits.
16955 if (Subtarget->is64Bit()) {
16956 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
16957 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
16960 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
16961 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
16964 SDValue Chain = HI.getValue(1);
16966 if (Opcode == X86ISD::RDTSCP_DAG) {
16967 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
16969 // Instruction RDTSCP loads the IA32:TSC_AUX_MSR (address C000_0103H) into
16970 // the ECX register. Add 'ecx' explicitly to the chain.
16971 SDValue ecx = DAG.getCopyFromReg(Chain, DL, X86::ECX, MVT::i32,
16973 // Explicitly store the content of ECX at the location passed in input
16974 // to the 'rdtscp' intrinsic.
16975 Chain = DAG.getStore(ecx.getValue(1), DL, ecx, N->getOperand(2),
16976 MachinePointerInfo(), false, false, 0);
16979 if (Subtarget->is64Bit()) {
16980 // The EDX register is loaded with the high-order 32 bits of the MSR, and
16981 // the EAX register is loaded with the low-order 32 bits.
16982 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
16983 DAG.getConstant(32, DL, MVT::i8));
16984 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
16985 Results.push_back(Chain);
16989 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
16990 SDValue Ops[] = { LO, HI };
16991 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
16992 Results.push_back(Pair);
16993 Results.push_back(Chain);
16996 static SDValue LowerREADCYCLECOUNTER(SDValue Op, const X86Subtarget *Subtarget,
16997 SelectionDAG &DAG) {
16998 SmallVector<SDValue, 2> Results;
17000 getReadTimeStampCounter(Op.getNode(), DL, X86ISD::RDTSC_DAG, DAG, Subtarget,
17002 return DAG.getMergeValues(Results, DL);
17005 static SDValue LowerSEHRESTOREFRAME(SDValue Op, const X86Subtarget *Subtarget,
17006 SelectionDAG &DAG) {
17007 MachineFunction &MF = DAG.getMachineFunction();
17008 const Function *Fn = MF.getFunction();
17010 SDValue Chain = Op.getOperand(0);
17012 assert(Subtarget->getFrameLowering()->hasFP(MF) &&
17013 "using llvm.x86.seh.restoreframe requires a frame pointer");
17015 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
17016 MVT VT = TLI.getPointerTy(DAG.getDataLayout());
17018 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
17019 unsigned FrameReg =
17020 RegInfo->getPtrSizedFrameRegister(DAG.getMachineFunction());
17021 unsigned SPReg = RegInfo->getStackRegister();
17022 unsigned SlotSize = RegInfo->getSlotSize();
17024 // Get incoming EBP.
17025 SDValue IncomingEBP =
17026 DAG.getCopyFromReg(Chain, dl, FrameReg, VT);
17028 // SP is saved in the first field of every registration node, so load
17029 // [EBP-RegNodeSize] into SP.
17030 int RegNodeSize = getSEHRegistrationNodeSize(Fn);
17031 SDValue SPAddr = DAG.getNode(ISD::ADD, dl, VT, IncomingEBP,
17032 DAG.getConstant(-RegNodeSize, dl, VT));
17034 DAG.getLoad(VT, dl, Chain, SPAddr, MachinePointerInfo(), false, false,
17035 false, VT.getScalarSizeInBits() / 8);
17036 Chain = DAG.getCopyToReg(Chain, dl, SPReg, NewSP);
17038 if (!RegInfo->needsStackRealignment(MF)) {
17039 // Adjust EBP to point back to the original frame position.
17040 SDValue NewFP = recoverFramePointer(DAG, Fn, IncomingEBP);
17041 Chain = DAG.getCopyToReg(Chain, dl, FrameReg, NewFP);
17043 assert(RegInfo->hasBasePointer(MF) &&
17044 "functions with Win32 EH must use frame or base pointer register");
17046 // Reload the base pointer (ESI) with the adjusted incoming EBP.
17047 SDValue NewBP = recoverFramePointer(DAG, Fn, IncomingEBP);
17048 Chain = DAG.getCopyToReg(Chain, dl, RegInfo->getBaseRegister(), NewBP);
17050 // Reload the spilled EBP value, now that the stack and base pointers are
17052 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
17053 X86FI->setHasSEHFramePtrSave(true);
17054 int FI = MF.getFrameInfo()->CreateSpillStackObject(SlotSize, SlotSize);
17055 X86FI->setSEHFramePtrSaveIndex(FI);
17056 SDValue NewFP = DAG.getLoad(VT, dl, Chain, DAG.getFrameIndex(FI, VT),
17057 MachinePointerInfo(), false, false, false,
17058 VT.getScalarSizeInBits() / 8);
17059 Chain = DAG.getCopyToReg(NewFP, dl, FrameReg, NewFP);
17065 static SDValue MarkEHRegistrationNode(SDValue Op, SelectionDAG &DAG) {
17066 MachineFunction &MF = DAG.getMachineFunction();
17067 SDValue Chain = Op.getOperand(0);
17068 SDValue RegNode = Op.getOperand(2);
17069 WinEHFuncInfo *EHInfo = MF.getWinEHFuncInfo();
17071 report_fatal_error("EH registrations only live in functions using WinEH");
17073 // Cast the operand to an alloca, and remember the frame index.
17074 auto *FINode = dyn_cast<FrameIndexSDNode>(RegNode);
17076 report_fatal_error("llvm.x86.seh.ehregnode expects a static alloca");
17077 EHInfo->EHRegNodeFrameIndex = FINode->getIndex();
17079 // Return the chain operand without making any DAG nodes.
17083 /// \brief Lower intrinsics for TRUNCATE_TO_MEM case
17084 /// return truncate Store/MaskedStore Node
17085 static SDValue LowerINTRINSIC_TRUNCATE_TO_MEM(const SDValue & Op,
17089 SDValue Mask = Op.getOperand(4);
17090 SDValue DataToTruncate = Op.getOperand(3);
17091 SDValue Addr = Op.getOperand(2);
17092 SDValue Chain = Op.getOperand(0);
17094 MVT VT = DataToTruncate.getSimpleValueType();
17095 MVT SVT = MVT::getVectorVT(ElementType, VT.getVectorNumElements());
17097 if (isAllOnesConstant(Mask)) // return just a truncate store
17098 return DAG.getTruncStore(Chain, dl, DataToTruncate, Addr,
17099 MachinePointerInfo(), SVT, false, false,
17100 SVT.getScalarSizeInBits()/8);
17102 MVT MaskVT = MVT::getVectorVT(MVT::i1, VT.getVectorNumElements());
17103 MVT BitcastVT = MVT::getVectorVT(MVT::i1,
17104 Mask.getSimpleValueType().getSizeInBits());
17105 // In case when MaskVT equals v2i1 or v4i1, low 2 or 4 elements
17106 // are extracted by EXTRACT_SUBVECTOR.
17107 SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
17108 DAG.getBitcast(BitcastVT, Mask),
17109 DAG.getIntPtrConstant(0, dl));
17111 MachineMemOperand *MMO = DAG.getMachineFunction().
17112 getMachineMemOperand(MachinePointerInfo(),
17113 MachineMemOperand::MOStore, SVT.getStoreSize(),
17114 SVT.getScalarSizeInBits()/8);
17116 return DAG.getMaskedStore(Chain, dl, DataToTruncate, Addr,
17117 VMask, SVT, MMO, true);
17120 static SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
17121 SelectionDAG &DAG) {
17122 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
17124 const IntrinsicData* IntrData = getIntrinsicWithChain(IntNo);
17126 if (IntNo == llvm::Intrinsic::x86_seh_restoreframe)
17127 return LowerSEHRESTOREFRAME(Op, Subtarget, DAG);
17128 else if (IntNo == llvm::Intrinsic::x86_seh_ehregnode)
17129 return MarkEHRegistrationNode(Op, DAG);
17134 switch(IntrData->Type) {
17135 default: llvm_unreachable("Unknown Intrinsic Type");
17138 // Emit the node with the right value type.
17139 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Glue, MVT::Other);
17140 SDValue Result = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(0));
17142 // If the value returned by RDRAND/RDSEED was valid (CF=1), return 1.
17143 // Otherwise return the value from Rand, which is always 0, casted to i32.
17144 SDValue Ops[] = { DAG.getZExtOrTrunc(Result, dl, Op->getValueType(1)),
17145 DAG.getConstant(1, dl, Op->getValueType(1)),
17146 DAG.getConstant(X86::COND_B, dl, MVT::i32),
17147 SDValue(Result.getNode(), 1) };
17148 SDValue isValid = DAG.getNode(X86ISD::CMOV, dl,
17149 DAG.getVTList(Op->getValueType(1), MVT::Glue),
17152 // Return { result, isValid, chain }.
17153 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(), Result, isValid,
17154 SDValue(Result.getNode(), 2));
17157 //gather(v1, mask, index, base, scale);
17158 SDValue Chain = Op.getOperand(0);
17159 SDValue Src = Op.getOperand(2);
17160 SDValue Base = Op.getOperand(3);
17161 SDValue Index = Op.getOperand(4);
17162 SDValue Mask = Op.getOperand(5);
17163 SDValue Scale = Op.getOperand(6);
17164 return getGatherNode(IntrData->Opc0, Op, DAG, Src, Mask, Base, Index, Scale,
17168 //scatter(base, mask, index, v1, scale);
17169 SDValue Chain = Op.getOperand(0);
17170 SDValue Base = Op.getOperand(2);
17171 SDValue Mask = Op.getOperand(3);
17172 SDValue Index = Op.getOperand(4);
17173 SDValue Src = Op.getOperand(5);
17174 SDValue Scale = Op.getOperand(6);
17175 return getScatterNode(IntrData->Opc0, Op, DAG, Src, Mask, Base, Index,
17179 SDValue Hint = Op.getOperand(6);
17180 unsigned HintVal = cast<ConstantSDNode>(Hint)->getZExtValue();
17181 assert(HintVal < 2 && "Wrong prefetch hint in intrinsic: should be 0 or 1");
17182 unsigned Opcode = (HintVal ? IntrData->Opc1 : IntrData->Opc0);
17183 SDValue Chain = Op.getOperand(0);
17184 SDValue Mask = Op.getOperand(2);
17185 SDValue Index = Op.getOperand(3);
17186 SDValue Base = Op.getOperand(4);
17187 SDValue Scale = Op.getOperand(5);
17188 return getPrefetchNode(Opcode, Op, DAG, Mask, Base, Index, Scale, Chain);
17190 // Read Time Stamp Counter (RDTSC) and Processor ID (RDTSCP).
17192 SmallVector<SDValue, 2> Results;
17193 getReadTimeStampCounter(Op.getNode(), dl, IntrData->Opc0, DAG, Subtarget,
17195 return DAG.getMergeValues(Results, dl);
17197 // Read Performance Monitoring Counters.
17199 SmallVector<SDValue, 2> Results;
17200 getReadPerformanceCounter(Op.getNode(), dl, DAG, Subtarget, Results);
17201 return DAG.getMergeValues(Results, dl);
17203 // XTEST intrinsics.
17205 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
17206 SDValue InTrans = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(0));
17207 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
17208 DAG.getConstant(X86::COND_NE, dl, MVT::i8),
17210 SDValue Ret = DAG.getNode(ISD::ZERO_EXTEND, dl, Op->getValueType(0), SetCC);
17211 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(),
17212 Ret, SDValue(InTrans.getNode(), 1));
17216 SmallVector<SDValue, 2> Results;
17217 SDVTList CFVTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
17218 SDVTList VTs = DAG.getVTList(Op.getOperand(3)->getValueType(0), MVT::Other);
17219 SDValue GenCF = DAG.getNode(X86ISD::ADD, dl, CFVTs, Op.getOperand(2),
17220 DAG.getConstant(-1, dl, MVT::i8));
17221 SDValue Res = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(3),
17222 Op.getOperand(4), GenCF.getValue(1));
17223 SDValue Store = DAG.getStore(Op.getOperand(0), dl, Res.getValue(0),
17224 Op.getOperand(5), MachinePointerInfo(),
17226 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
17227 DAG.getConstant(X86::COND_B, dl, MVT::i8),
17229 Results.push_back(SetCC);
17230 Results.push_back(Store);
17231 return DAG.getMergeValues(Results, dl);
17233 case COMPRESS_TO_MEM: {
17235 SDValue Mask = Op.getOperand(4);
17236 SDValue DataToCompress = Op.getOperand(3);
17237 SDValue Addr = Op.getOperand(2);
17238 SDValue Chain = Op.getOperand(0);
17240 MVT VT = DataToCompress.getSimpleValueType();
17241 if (isAllOnesConstant(Mask)) // return just a store
17242 return DAG.getStore(Chain, dl, DataToCompress, Addr,
17243 MachinePointerInfo(), false, false,
17244 VT.getScalarSizeInBits()/8);
17246 SDValue Compressed =
17247 getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, DataToCompress),
17248 Mask, DAG.getUNDEF(VT), Subtarget, DAG);
17249 return DAG.getStore(Chain, dl, Compressed, Addr,
17250 MachinePointerInfo(), false, false,
17251 VT.getScalarSizeInBits()/8);
17253 case TRUNCATE_TO_MEM_VI8:
17254 return LowerINTRINSIC_TRUNCATE_TO_MEM(Op, DAG, MVT::i8);
17255 case TRUNCATE_TO_MEM_VI16:
17256 return LowerINTRINSIC_TRUNCATE_TO_MEM(Op, DAG, MVT::i16);
17257 case TRUNCATE_TO_MEM_VI32:
17258 return LowerINTRINSIC_TRUNCATE_TO_MEM(Op, DAG, MVT::i32);
17259 case EXPAND_FROM_MEM: {
17261 SDValue Mask = Op.getOperand(4);
17262 SDValue PassThru = Op.getOperand(3);
17263 SDValue Addr = Op.getOperand(2);
17264 SDValue Chain = Op.getOperand(0);
17265 MVT VT = Op.getSimpleValueType();
17267 if (isAllOnesConstant(Mask)) // return just a load
17268 return DAG.getLoad(VT, dl, Chain, Addr, MachinePointerInfo(), false, false,
17269 false, VT.getScalarSizeInBits()/8);
17271 SDValue DataToExpand = DAG.getLoad(VT, dl, Chain, Addr, MachinePointerInfo(),
17272 false, false, false,
17273 VT.getScalarSizeInBits()/8);
17275 SDValue Results[] = {
17276 getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, DataToExpand),
17277 Mask, PassThru, Subtarget, DAG), Chain};
17278 return DAG.getMergeValues(Results, dl);
17283 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op,
17284 SelectionDAG &DAG) const {
17285 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
17286 MFI->setReturnAddressIsTaken(true);
17288 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
17291 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
17293 EVT PtrVT = getPointerTy(DAG.getDataLayout());
17296 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
17297 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
17298 SDValue Offset = DAG.getConstant(RegInfo->getSlotSize(), dl, PtrVT);
17299 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
17300 DAG.getNode(ISD::ADD, dl, PtrVT,
17301 FrameAddr, Offset),
17302 MachinePointerInfo(), false, false, false, 0);
17305 // Just load the return address.
17306 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
17307 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
17308 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
17311 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
17312 MachineFunction &MF = DAG.getMachineFunction();
17313 MachineFrameInfo *MFI = MF.getFrameInfo();
17314 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
17315 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
17316 EVT VT = Op.getValueType();
17318 MFI->setFrameAddressIsTaken(true);
17320 if (MF.getTarget().getMCAsmInfo()->usesWindowsCFI()) {
17321 // Depth > 0 makes no sense on targets which use Windows unwind codes. It
17322 // is not possible to crawl up the stack without looking at the unwind codes
17324 int FrameAddrIndex = FuncInfo->getFAIndex();
17325 if (!FrameAddrIndex) {
17326 // Set up a frame object for the return address.
17327 unsigned SlotSize = RegInfo->getSlotSize();
17328 FrameAddrIndex = MF.getFrameInfo()->CreateFixedObject(
17329 SlotSize, /*Offset=*/0, /*IsImmutable=*/false);
17330 FuncInfo->setFAIndex(FrameAddrIndex);
17332 return DAG.getFrameIndex(FrameAddrIndex, VT);
17335 unsigned FrameReg =
17336 RegInfo->getPtrSizedFrameRegister(DAG.getMachineFunction());
17337 SDLoc dl(Op); // FIXME probably not meaningful
17338 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
17339 assert(((FrameReg == X86::RBP && VT == MVT::i64) ||
17340 (FrameReg == X86::EBP && VT == MVT::i32)) &&
17341 "Invalid Frame Register!");
17342 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
17344 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
17345 MachinePointerInfo(),
17346 false, false, false, 0);
17350 // FIXME? Maybe this could be a TableGen attribute on some registers and
17351 // this table could be generated automatically from RegInfo.
17352 unsigned X86TargetLowering::getRegisterByName(const char* RegName, EVT VT,
17353 SelectionDAG &DAG) const {
17354 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
17355 const MachineFunction &MF = DAG.getMachineFunction();
17357 unsigned Reg = StringSwitch<unsigned>(RegName)
17358 .Case("esp", X86::ESP)
17359 .Case("rsp", X86::RSP)
17360 .Case("ebp", X86::EBP)
17361 .Case("rbp", X86::RBP)
17364 if (Reg == X86::EBP || Reg == X86::RBP) {
17365 if (!TFI.hasFP(MF))
17366 report_fatal_error("register " + StringRef(RegName) +
17367 " is allocatable: function has no frame pointer");
17370 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
17371 unsigned FrameReg =
17372 RegInfo->getPtrSizedFrameRegister(DAG.getMachineFunction());
17373 assert((FrameReg == X86::EBP || FrameReg == X86::RBP) &&
17374 "Invalid Frame Register!");
17382 report_fatal_error("Invalid register name global variable");
17385 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
17386 SelectionDAG &DAG) const {
17387 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
17388 return DAG.getIntPtrConstant(2 * RegInfo->getSlotSize(), SDLoc(Op));
17391 unsigned X86TargetLowering::getExceptionPointerRegister(
17392 const Constant *PersonalityFn) const {
17393 if (classifyEHPersonality(PersonalityFn) == EHPersonality::CoreCLR)
17394 return Subtarget->isTarget64BitLP64() ? X86::RDX : X86::EDX;
17396 return Subtarget->isTarget64BitLP64() ? X86::RAX : X86::EAX;
17399 unsigned X86TargetLowering::getExceptionSelectorRegister(
17400 const Constant *PersonalityFn) const {
17401 // Funclet personalities don't use selectors (the runtime does the selection).
17402 assert(!isFuncletEHPersonality(classifyEHPersonality(PersonalityFn)));
17403 return Subtarget->isTarget64BitLP64() ? X86::RDX : X86::EDX;
17406 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
17407 SDValue Chain = Op.getOperand(0);
17408 SDValue Offset = Op.getOperand(1);
17409 SDValue Handler = Op.getOperand(2);
17412 EVT PtrVT = getPointerTy(DAG.getDataLayout());
17413 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
17414 unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction());
17415 assert(((FrameReg == X86::RBP && PtrVT == MVT::i64) ||
17416 (FrameReg == X86::EBP && PtrVT == MVT::i32)) &&
17417 "Invalid Frame Register!");
17418 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, PtrVT);
17419 unsigned StoreAddrReg = (PtrVT == MVT::i64) ? X86::RCX : X86::ECX;
17421 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, Frame,
17422 DAG.getIntPtrConstant(RegInfo->getSlotSize(),
17424 StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, StoreAddr, Offset);
17425 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(),
17427 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
17429 return DAG.getNode(X86ISD::EH_RETURN, dl, MVT::Other, Chain,
17430 DAG.getRegister(StoreAddrReg, PtrVT));
17433 SDValue X86TargetLowering::lowerEH_SJLJ_SETJMP(SDValue Op,
17434 SelectionDAG &DAG) const {
17436 return DAG.getNode(X86ISD::EH_SJLJ_SETJMP, DL,
17437 DAG.getVTList(MVT::i32, MVT::Other),
17438 Op.getOperand(0), Op.getOperand(1));
17441 SDValue X86TargetLowering::lowerEH_SJLJ_LONGJMP(SDValue Op,
17442 SelectionDAG &DAG) const {
17444 return DAG.getNode(X86ISD::EH_SJLJ_LONGJMP, DL, MVT::Other,
17445 Op.getOperand(0), Op.getOperand(1));
17448 static SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) {
17449 return Op.getOperand(0);
17452 SDValue X86TargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
17453 SelectionDAG &DAG) const {
17454 SDValue Root = Op.getOperand(0);
17455 SDValue Trmp = Op.getOperand(1); // trampoline
17456 SDValue FPtr = Op.getOperand(2); // nested function
17457 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
17460 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
17461 const TargetRegisterInfo *TRI = Subtarget->getRegisterInfo();
17463 if (Subtarget->is64Bit()) {
17464 SDValue OutChains[6];
17466 // Large code-model.
17467 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode.
17468 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode.
17470 const unsigned char N86R10 = TRI->getEncodingValue(X86::R10) & 0x7;
17471 const unsigned char N86R11 = TRI->getEncodingValue(X86::R11) & 0x7;
17473 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
17475 // Load the pointer to the nested function into R11.
17476 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
17477 SDValue Addr = Trmp;
17478 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, dl, MVT::i16),
17479 Addr, MachinePointerInfo(TrmpAddr),
17482 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17483 DAG.getConstant(2, dl, MVT::i64));
17484 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr,
17485 MachinePointerInfo(TrmpAddr, 2),
17488 // Load the 'nest' parameter value into R10.
17489 // R10 is specified in X86CallingConv.td
17490 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
17491 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17492 DAG.getConstant(10, dl, MVT::i64));
17493 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, dl, MVT::i16),
17494 Addr, MachinePointerInfo(TrmpAddr, 10),
17497 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17498 DAG.getConstant(12, dl, MVT::i64));
17499 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr,
17500 MachinePointerInfo(TrmpAddr, 12),
17503 // Jump to the nested function.
17504 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
17505 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17506 DAG.getConstant(20, dl, MVT::i64));
17507 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, dl, MVT::i16),
17508 Addr, MachinePointerInfo(TrmpAddr, 20),
17511 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
17512 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17513 DAG.getConstant(22, dl, MVT::i64));
17514 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, dl, MVT::i8),
17515 Addr, MachinePointerInfo(TrmpAddr, 22),
17518 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
17520 const Function *Func =
17521 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
17522 CallingConv::ID CC = Func->getCallingConv();
17527 llvm_unreachable("Unsupported calling convention");
17528 case CallingConv::C:
17529 case CallingConv::X86_StdCall: {
17530 // Pass 'nest' parameter in ECX.
17531 // Must be kept in sync with X86CallingConv.td
17532 NestReg = X86::ECX;
17534 // Check that ECX wasn't needed by an 'inreg' parameter.
17535 FunctionType *FTy = Func->getFunctionType();
17536 const AttributeSet &Attrs = Func->getAttributes();
17538 if (!Attrs.isEmpty() && !Func->isVarArg()) {
17539 unsigned InRegCount = 0;
17542 for (FunctionType::param_iterator I = FTy->param_begin(),
17543 E = FTy->param_end(); I != E; ++I, ++Idx)
17544 if (Attrs.hasAttribute(Idx, Attribute::InReg)) {
17545 auto &DL = DAG.getDataLayout();
17546 // FIXME: should only count parameters that are lowered to integers.
17547 InRegCount += (DL.getTypeSizeInBits(*I) + 31) / 32;
17550 if (InRegCount > 2) {
17551 report_fatal_error("Nest register in use - reduce number of inreg"
17557 case CallingConv::X86_FastCall:
17558 case CallingConv::X86_ThisCall:
17559 case CallingConv::Fast:
17560 // Pass 'nest' parameter in EAX.
17561 // Must be kept in sync with X86CallingConv.td
17562 NestReg = X86::EAX;
17566 SDValue OutChains[4];
17567 SDValue Addr, Disp;
17569 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17570 DAG.getConstant(10, dl, MVT::i32));
17571 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
17573 // This is storing the opcode for MOV32ri.
17574 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte.
17575 const unsigned char N86Reg = TRI->getEncodingValue(NestReg) & 0x7;
17576 OutChains[0] = DAG.getStore(Root, dl,
17577 DAG.getConstant(MOV32ri|N86Reg, dl, MVT::i8),
17578 Trmp, MachinePointerInfo(TrmpAddr),
17581 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17582 DAG.getConstant(1, dl, MVT::i32));
17583 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr,
17584 MachinePointerInfo(TrmpAddr, 1),
17587 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode.
17588 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17589 DAG.getConstant(5, dl, MVT::i32));
17590 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, dl, MVT::i8),
17591 Addr, MachinePointerInfo(TrmpAddr, 5),
17594 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17595 DAG.getConstant(6, dl, MVT::i32));
17596 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr,
17597 MachinePointerInfo(TrmpAddr, 6),
17600 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
17604 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op,
17605 SelectionDAG &DAG) const {
17607 The rounding mode is in bits 11:10 of FPSR, and has the following
17609 00 Round to nearest
17614 FLT_ROUNDS, on the other hand, expects the following:
17621 To perform the conversion, we do:
17622 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
17625 MachineFunction &MF = DAG.getMachineFunction();
17626 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
17627 unsigned StackAlignment = TFI.getStackAlignment();
17628 MVT VT = Op.getSimpleValueType();
17631 // Save FP Control Word to stack slot
17632 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false);
17633 SDValue StackSlot =
17634 DAG.getFrameIndex(SSFI, getPointerTy(DAG.getDataLayout()));
17636 MachineMemOperand *MMO =
17637 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(MF, SSFI),
17638 MachineMemOperand::MOStore, 2, 2);
17640 SDValue Ops[] = { DAG.getEntryNode(), StackSlot };
17641 SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL,
17642 DAG.getVTList(MVT::Other),
17643 Ops, MVT::i16, MMO);
17645 // Load FP Control Word from stack slot
17646 SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot,
17647 MachinePointerInfo(), false, false, false, 0);
17649 // Transform as necessary
17651 DAG.getNode(ISD::SRL, DL, MVT::i16,
17652 DAG.getNode(ISD::AND, DL, MVT::i16,
17653 CWD, DAG.getConstant(0x800, DL, MVT::i16)),
17654 DAG.getConstant(11, DL, MVT::i8));
17656 DAG.getNode(ISD::SRL, DL, MVT::i16,
17657 DAG.getNode(ISD::AND, DL, MVT::i16,
17658 CWD, DAG.getConstant(0x400, DL, MVT::i16)),
17659 DAG.getConstant(9, DL, MVT::i8));
17662 DAG.getNode(ISD::AND, DL, MVT::i16,
17663 DAG.getNode(ISD::ADD, DL, MVT::i16,
17664 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2),
17665 DAG.getConstant(1, DL, MVT::i16)),
17666 DAG.getConstant(3, DL, MVT::i16));
17668 return DAG.getNode((VT.getSizeInBits() < 16 ?
17669 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal);
17672 /// \brief Lower a vector CTLZ using native supported vector CTLZ instruction.
17674 // 1. i32/i64 128/256-bit vector (native support require VLX) are expended
17675 // to 512-bit vector.
17676 // 2. i8/i16 vector implemented using dword LZCNT vector instruction
17677 // ( sub(trunc(lzcnt(zext32(x)))) ). In case zext32(x) is illegal,
17678 // split the vector, perform operation on it's Lo a Hi part and
17679 // concatenate the results.
17680 static SDValue LowerVectorCTLZ_AVX512(SDValue Op, SelectionDAG &DAG) {
17682 MVT VT = Op.getSimpleValueType();
17683 MVT EltVT = VT.getVectorElementType();
17684 unsigned NumElems = VT.getVectorNumElements();
17686 if (EltVT == MVT::i64 || EltVT == MVT::i32) {
17687 // Extend to 512 bit vector.
17688 assert((VT.is256BitVector() || VT.is128BitVector()) &&
17689 "Unsupported value type for operation");
17691 MVT NewVT = MVT::getVectorVT(EltVT, 512 / VT.getScalarSizeInBits());
17692 SDValue Vec512 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, NewVT,
17693 DAG.getUNDEF(NewVT),
17695 DAG.getIntPtrConstant(0, dl));
17696 SDValue CtlzNode = DAG.getNode(ISD::CTLZ, dl, NewVT, Vec512);
17698 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, CtlzNode,
17699 DAG.getIntPtrConstant(0, dl));
17702 assert((EltVT == MVT::i8 || EltVT == MVT::i16) &&
17703 "Unsupported element type");
17705 if (16 < NumElems) {
17706 // Split vector, it's Lo and Hi parts will be handled in next iteration.
17708 std::tie(Lo, Hi) = DAG.SplitVector(Op.getOperand(0), dl);
17709 MVT OutVT = MVT::getVectorVT(EltVT, NumElems/2);
17711 Lo = DAG.getNode(Op.getOpcode(), dl, OutVT, Lo);
17712 Hi = DAG.getNode(Op.getOpcode(), dl, OutVT, Hi);
17714 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, Lo, Hi);
17717 MVT NewVT = MVT::getVectorVT(MVT::i32, NumElems);
17719 assert((NewVT.is256BitVector() || NewVT.is512BitVector()) &&
17720 "Unsupported value type for operation");
17722 // Use native supported vector instruction vplzcntd.
17723 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, NewVT, Op.getOperand(0));
17724 SDValue CtlzNode = DAG.getNode(ISD::CTLZ, dl, NewVT, Op);
17725 SDValue TruncNode = DAG.getNode(ISD::TRUNCATE, dl, VT, CtlzNode);
17726 SDValue Delta = DAG.getConstant(32 - EltVT.getSizeInBits(), dl, VT);
17728 return DAG.getNode(ISD::SUB, dl, VT, TruncNode, Delta);
17731 static SDValue LowerCTLZ(SDValue Op, const X86Subtarget *Subtarget,
17732 SelectionDAG &DAG) {
17733 MVT VT = Op.getSimpleValueType();
17735 unsigned NumBits = VT.getSizeInBits();
17738 if (VT.isVector() && Subtarget->hasAVX512())
17739 return LowerVectorCTLZ_AVX512(Op, DAG);
17741 Op = Op.getOperand(0);
17742 if (VT == MVT::i8) {
17743 // Zero extend to i32 since there is not an i8 bsr.
17745 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
17748 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
17749 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
17750 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
17752 // If src is zero (i.e. bsr sets ZF), returns NumBits.
17755 DAG.getConstant(NumBits + NumBits - 1, dl, OpVT),
17756 DAG.getConstant(X86::COND_E, dl, MVT::i8),
17759 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops);
17761 // Finally xor with NumBits-1.
17762 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op,
17763 DAG.getConstant(NumBits - 1, dl, OpVT));
17766 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
17770 static SDValue LowerCTLZ_ZERO_UNDEF(SDValue Op, const X86Subtarget *Subtarget,
17771 SelectionDAG &DAG) {
17772 MVT VT = Op.getSimpleValueType();
17774 unsigned NumBits = VT.getSizeInBits();
17777 if (VT.isVector() && Subtarget->hasAVX512())
17778 return LowerVectorCTLZ_AVX512(Op, DAG);
17780 Op = Op.getOperand(0);
17781 if (VT == MVT::i8) {
17782 // Zero extend to i32 since there is not an i8 bsr.
17784 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
17787 // Issue a bsr (scan bits in reverse).
17788 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
17789 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
17791 // And xor with NumBits-1.
17792 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op,
17793 DAG.getConstant(NumBits - 1, dl, OpVT));
17796 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
17800 static SDValue LowerCTTZ(SDValue Op, SelectionDAG &DAG) {
17801 MVT VT = Op.getSimpleValueType();
17802 unsigned NumBits = VT.getScalarSizeInBits();
17805 if (VT.isVector()) {
17806 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
17808 SDValue N0 = Op.getOperand(0);
17809 SDValue Zero = DAG.getConstant(0, dl, VT);
17811 // lsb(x) = (x & -x)
17812 SDValue LSB = DAG.getNode(ISD::AND, dl, VT, N0,
17813 DAG.getNode(ISD::SUB, dl, VT, Zero, N0));
17815 // cttz_undef(x) = (width - 1) - ctlz(lsb)
17816 if (Op.getOpcode() == ISD::CTTZ_ZERO_UNDEF &&
17817 TLI.isOperationLegal(ISD::CTLZ, VT)) {
17818 SDValue WidthMinusOne = DAG.getConstant(NumBits - 1, dl, VT);
17819 return DAG.getNode(ISD::SUB, dl, VT, WidthMinusOne,
17820 DAG.getNode(ISD::CTLZ, dl, VT, LSB));
17823 // cttz(x) = ctpop(lsb - 1)
17824 SDValue One = DAG.getConstant(1, dl, VT);
17825 return DAG.getNode(ISD::CTPOP, dl, VT,
17826 DAG.getNode(ISD::SUB, dl, VT, LSB, One));
17829 assert(Op.getOpcode() == ISD::CTTZ &&
17830 "Only scalar CTTZ requires custom lowering");
17832 // Issue a bsf (scan bits forward) which also sets EFLAGS.
17833 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
17834 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op.getOperand(0));
17836 // If src is zero (i.e. bsf sets ZF), returns NumBits.
17839 DAG.getConstant(NumBits, dl, VT),
17840 DAG.getConstant(X86::COND_E, dl, MVT::i8),
17843 return DAG.getNode(X86ISD::CMOV, dl, VT, Ops);
17846 // Lower256IntArith - Break a 256-bit integer operation into two new 128-bit
17847 // ones, and then concatenate the result back.
17848 static SDValue Lower256IntArith(SDValue Op, SelectionDAG &DAG) {
17849 MVT VT = Op.getSimpleValueType();
17851 assert(VT.is256BitVector() && VT.isInteger() &&
17852 "Unsupported value type for operation");
17854 unsigned NumElems = VT.getVectorNumElements();
17857 // Extract the LHS vectors
17858 SDValue LHS = Op.getOperand(0);
17859 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
17860 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
17862 // Extract the RHS vectors
17863 SDValue RHS = Op.getOperand(1);
17864 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
17865 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
17867 MVT EltVT = VT.getVectorElementType();
17868 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
17870 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
17871 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1),
17872 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2));
17875 static SDValue LowerADD(SDValue Op, SelectionDAG &DAG) {
17876 if (Op.getValueType() == MVT::i1)
17877 return DAG.getNode(ISD::XOR, SDLoc(Op), Op.getValueType(),
17878 Op.getOperand(0), Op.getOperand(1));
17879 assert(Op.getSimpleValueType().is256BitVector() &&
17880 Op.getSimpleValueType().isInteger() &&
17881 "Only handle AVX 256-bit vector integer operation");
17882 return Lower256IntArith(Op, DAG);
17885 static SDValue LowerSUB(SDValue Op, SelectionDAG &DAG) {
17886 if (Op.getValueType() == MVT::i1)
17887 return DAG.getNode(ISD::XOR, SDLoc(Op), Op.getValueType(),
17888 Op.getOperand(0), Op.getOperand(1));
17889 assert(Op.getSimpleValueType().is256BitVector() &&
17890 Op.getSimpleValueType().isInteger() &&
17891 "Only handle AVX 256-bit vector integer operation");
17892 return Lower256IntArith(Op, DAG);
17895 static SDValue LowerMINMAX(SDValue Op, SelectionDAG &DAG) {
17896 assert(Op.getSimpleValueType().is256BitVector() &&
17897 Op.getSimpleValueType().isInteger() &&
17898 "Only handle AVX 256-bit vector integer operation");
17899 return Lower256IntArith(Op, DAG);
17902 static SDValue LowerMUL(SDValue Op, const X86Subtarget *Subtarget,
17903 SelectionDAG &DAG) {
17905 MVT VT = Op.getSimpleValueType();
17908 return DAG.getNode(ISD::AND, dl, VT, Op.getOperand(0), Op.getOperand(1));
17910 // Decompose 256-bit ops into smaller 128-bit ops.
17911 if (VT.is256BitVector() && !Subtarget->hasInt256())
17912 return Lower256IntArith(Op, DAG);
17914 SDValue A = Op.getOperand(0);
17915 SDValue B = Op.getOperand(1);
17917 // Lower v16i8/v32i8 mul as promotion to v8i16/v16i16 vector
17918 // pairs, multiply and truncate.
17919 if (VT == MVT::v16i8 || VT == MVT::v32i8) {
17920 if (Subtarget->hasInt256()) {
17921 if (VT == MVT::v32i8) {
17922 MVT SubVT = MVT::getVectorVT(MVT::i8, VT.getVectorNumElements() / 2);
17923 SDValue Lo = DAG.getIntPtrConstant(0, dl);
17924 SDValue Hi = DAG.getIntPtrConstant(VT.getVectorNumElements() / 2, dl);
17925 SDValue ALo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, A, Lo);
17926 SDValue BLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, B, Lo);
17927 SDValue AHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, A, Hi);
17928 SDValue BHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, B, Hi);
17929 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
17930 DAG.getNode(ISD::MUL, dl, SubVT, ALo, BLo),
17931 DAG.getNode(ISD::MUL, dl, SubVT, AHi, BHi));
17934 MVT ExVT = MVT::getVectorVT(MVT::i16, VT.getVectorNumElements());
17935 return DAG.getNode(
17936 ISD::TRUNCATE, dl, VT,
17937 DAG.getNode(ISD::MUL, dl, ExVT,
17938 DAG.getNode(ISD::SIGN_EXTEND, dl, ExVT, A),
17939 DAG.getNode(ISD::SIGN_EXTEND, dl, ExVT, B)));
17942 assert(VT == MVT::v16i8 &&
17943 "Pre-AVX2 support only supports v16i8 multiplication");
17944 MVT ExVT = MVT::v8i16;
17946 // Extract the lo parts and sign extend to i16
17948 if (Subtarget->hasSSE41()) {
17949 ALo = DAG.getNode(X86ISD::VSEXT, dl, ExVT, A);
17950 BLo = DAG.getNode(X86ISD::VSEXT, dl, ExVT, B);
17952 const int ShufMask[] = {-1, 0, -1, 1, -1, 2, -1, 3,
17953 -1, 4, -1, 5, -1, 6, -1, 7};
17954 ALo = DAG.getVectorShuffle(VT, dl, A, A, ShufMask);
17955 BLo = DAG.getVectorShuffle(VT, dl, B, B, ShufMask);
17956 ALo = DAG.getBitcast(ExVT, ALo);
17957 BLo = DAG.getBitcast(ExVT, BLo);
17958 ALo = DAG.getNode(ISD::SRA, dl, ExVT, ALo, DAG.getConstant(8, dl, ExVT));
17959 BLo = DAG.getNode(ISD::SRA, dl, ExVT, BLo, DAG.getConstant(8, dl, ExVT));
17962 // Extract the hi parts and sign extend to i16
17964 if (Subtarget->hasSSE41()) {
17965 const int ShufMask[] = {8, 9, 10, 11, 12, 13, 14, 15,
17966 -1, -1, -1, -1, -1, -1, -1, -1};
17967 AHi = DAG.getVectorShuffle(VT, dl, A, A, ShufMask);
17968 BHi = DAG.getVectorShuffle(VT, dl, B, B, ShufMask);
17969 AHi = DAG.getNode(X86ISD::VSEXT, dl, ExVT, AHi);
17970 BHi = DAG.getNode(X86ISD::VSEXT, dl, ExVT, BHi);
17972 const int ShufMask[] = {-1, 8, -1, 9, -1, 10, -1, 11,
17973 -1, 12, -1, 13, -1, 14, -1, 15};
17974 AHi = DAG.getVectorShuffle(VT, dl, A, A, ShufMask);
17975 BHi = DAG.getVectorShuffle(VT, dl, B, B, ShufMask);
17976 AHi = DAG.getBitcast(ExVT, AHi);
17977 BHi = DAG.getBitcast(ExVT, BHi);
17978 AHi = DAG.getNode(ISD::SRA, dl, ExVT, AHi, DAG.getConstant(8, dl, ExVT));
17979 BHi = DAG.getNode(ISD::SRA, dl, ExVT, BHi, DAG.getConstant(8, dl, ExVT));
17982 // Multiply, mask the lower 8bits of the lo/hi results and pack
17983 SDValue RLo = DAG.getNode(ISD::MUL, dl, ExVT, ALo, BLo);
17984 SDValue RHi = DAG.getNode(ISD::MUL, dl, ExVT, AHi, BHi);
17985 RLo = DAG.getNode(ISD::AND, dl, ExVT, RLo, DAG.getConstant(255, dl, ExVT));
17986 RHi = DAG.getNode(ISD::AND, dl, ExVT, RHi, DAG.getConstant(255, dl, ExVT));
17987 return DAG.getNode(X86ISD::PACKUS, dl, VT, RLo, RHi);
17990 // Lower v4i32 mul as 2x shuffle, 2x pmuludq, 2x shuffle.
17991 if (VT == MVT::v4i32) {
17992 assert(Subtarget->hasSSE2() && !Subtarget->hasSSE41() &&
17993 "Should not custom lower when pmuldq is available!");
17995 // Extract the odd parts.
17996 static const int UnpackMask[] = { 1, -1, 3, -1 };
17997 SDValue Aodds = DAG.getVectorShuffle(VT, dl, A, A, UnpackMask);
17998 SDValue Bodds = DAG.getVectorShuffle(VT, dl, B, B, UnpackMask);
18000 // Multiply the even parts.
18001 SDValue Evens = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, A, B);
18002 // Now multiply odd parts.
18003 SDValue Odds = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, Aodds, Bodds);
18005 Evens = DAG.getBitcast(VT, Evens);
18006 Odds = DAG.getBitcast(VT, Odds);
18008 // Merge the two vectors back together with a shuffle. This expands into 2
18010 static const int ShufMask[] = { 0, 4, 2, 6 };
18011 return DAG.getVectorShuffle(VT, dl, Evens, Odds, ShufMask);
18014 assert((VT == MVT::v2i64 || VT == MVT::v4i64 || VT == MVT::v8i64) &&
18015 "Only know how to lower V2I64/V4I64/V8I64 multiply");
18017 // Ahi = psrlqi(a, 32);
18018 // Bhi = psrlqi(b, 32);
18020 // AloBlo = pmuludq(a, b);
18021 // AloBhi = pmuludq(a, Bhi);
18022 // AhiBlo = pmuludq(Ahi, b);
18024 // AloBhi = psllqi(AloBhi, 32);
18025 // AhiBlo = psllqi(AhiBlo, 32);
18026 // return AloBlo + AloBhi + AhiBlo;
18028 SDValue Ahi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, A, 32, DAG);
18029 SDValue Bhi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, B, 32, DAG);
18031 SDValue AhiBlo = Ahi;
18032 SDValue AloBhi = Bhi;
18033 // Bit cast to 32-bit vectors for MULUDQ
18034 MVT MulVT = (VT == MVT::v2i64) ? MVT::v4i32 :
18035 (VT == MVT::v4i64) ? MVT::v8i32 : MVT::v16i32;
18036 A = DAG.getBitcast(MulVT, A);
18037 B = DAG.getBitcast(MulVT, B);
18038 Ahi = DAG.getBitcast(MulVT, Ahi);
18039 Bhi = DAG.getBitcast(MulVT, Bhi);
18041 SDValue AloBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, B);
18042 // After shifting right const values the result may be all-zero.
18043 if (!ISD::isBuildVectorAllZeros(Ahi.getNode())) {
18044 AhiBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, Ahi, B);
18045 AhiBlo = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AhiBlo, 32, DAG);
18047 if (!ISD::isBuildVectorAllZeros(Bhi.getNode())) {
18048 AloBhi = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, Bhi);
18049 AloBhi = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AloBhi, 32, DAG);
18052 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
18053 return DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
18056 SDValue X86TargetLowering::LowerWin64_i128OP(SDValue Op, SelectionDAG &DAG) const {
18057 assert(Subtarget->isTargetWin64() && "Unexpected target");
18058 EVT VT = Op.getValueType();
18059 assert(VT.isInteger() && VT.getSizeInBits() == 128 &&
18060 "Unexpected return type for lowering");
18064 switch (Op->getOpcode()) {
18065 default: llvm_unreachable("Unexpected request for libcall!");
18066 case ISD::SDIV: isSigned = true; LC = RTLIB::SDIV_I128; break;
18067 case ISD::UDIV: isSigned = false; LC = RTLIB::UDIV_I128; break;
18068 case ISD::SREM: isSigned = true; LC = RTLIB::SREM_I128; break;
18069 case ISD::UREM: isSigned = false; LC = RTLIB::UREM_I128; break;
18070 case ISD::SDIVREM: isSigned = true; LC = RTLIB::SDIVREM_I128; break;
18071 case ISD::UDIVREM: isSigned = false; LC = RTLIB::UDIVREM_I128; break;
18075 SDValue InChain = DAG.getEntryNode();
18077 TargetLowering::ArgListTy Args;
18078 TargetLowering::ArgListEntry Entry;
18079 for (unsigned i = 0, e = Op->getNumOperands(); i != e; ++i) {
18080 EVT ArgVT = Op->getOperand(i).getValueType();
18081 assert(ArgVT.isInteger() && ArgVT.getSizeInBits() == 128 &&
18082 "Unexpected argument type for lowering");
18083 SDValue StackPtr = DAG.CreateStackTemporary(ArgVT, 16);
18084 Entry.Node = StackPtr;
18085 InChain = DAG.getStore(InChain, dl, Op->getOperand(i), StackPtr, MachinePointerInfo(),
18087 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
18088 Entry.Ty = PointerType::get(ArgTy,0);
18089 Entry.isSExt = false;
18090 Entry.isZExt = false;
18091 Args.push_back(Entry);
18094 SDValue Callee = DAG.getExternalSymbol(getLibcallName(LC),
18095 getPointerTy(DAG.getDataLayout()));
18097 TargetLowering::CallLoweringInfo CLI(DAG);
18098 CLI.setDebugLoc(dl).setChain(InChain)
18099 .setCallee(getLibcallCallingConv(LC),
18100 static_cast<EVT>(MVT::v2i64).getTypeForEVT(*DAG.getContext()),
18101 Callee, std::move(Args), 0)
18102 .setInRegister().setSExtResult(isSigned).setZExtResult(!isSigned);
18104 std::pair<SDValue, SDValue> CallInfo = LowerCallTo(CLI);
18105 return DAG.getBitcast(VT, CallInfo.first);
18108 static SDValue LowerMUL_LOHI(SDValue Op, const X86Subtarget *Subtarget,
18109 SelectionDAG &DAG) {
18110 SDValue Op0 = Op.getOperand(0), Op1 = Op.getOperand(1);
18111 MVT VT = Op0.getSimpleValueType();
18114 assert((VT == MVT::v4i32 && Subtarget->hasSSE2()) ||
18115 (VT == MVT::v8i32 && Subtarget->hasInt256()));
18117 // PMULxD operations multiply each even value (starting at 0) of LHS with
18118 // the related value of RHS and produce a widen result.
18119 // E.g., PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
18120 // => <2 x i64> <ae|cg>
18122 // In other word, to have all the results, we need to perform two PMULxD:
18123 // 1. one with the even values.
18124 // 2. one with the odd values.
18125 // To achieve #2, with need to place the odd values at an even position.
18127 // Place the odd value at an even position (basically, shift all values 1
18128 // step to the left):
18129 const int Mask[] = {1, -1, 3, -1, 5, -1, 7, -1};
18130 // <a|b|c|d> => <b|undef|d|undef>
18131 SDValue Odd0 = DAG.getVectorShuffle(VT, dl, Op0, Op0, Mask);
18132 // <e|f|g|h> => <f|undef|h|undef>
18133 SDValue Odd1 = DAG.getVectorShuffle(VT, dl, Op1, Op1, Mask);
18135 // Emit two multiplies, one for the lower 2 ints and one for the higher 2
18137 MVT MulVT = VT == MVT::v4i32 ? MVT::v2i64 : MVT::v4i64;
18138 bool IsSigned = Op->getOpcode() == ISD::SMUL_LOHI;
18140 (!IsSigned || !Subtarget->hasSSE41()) ? X86ISD::PMULUDQ : X86ISD::PMULDQ;
18141 // PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
18142 // => <2 x i64> <ae|cg>
18143 SDValue Mul1 = DAG.getBitcast(VT, DAG.getNode(Opcode, dl, MulVT, Op0, Op1));
18144 // PMULUDQ <4 x i32> <b|undef|d|undef>, <4 x i32> <f|undef|h|undef>
18145 // => <2 x i64> <bf|dh>
18146 SDValue Mul2 = DAG.getBitcast(VT, DAG.getNode(Opcode, dl, MulVT, Odd0, Odd1));
18148 // Shuffle it back into the right order.
18149 SDValue Highs, Lows;
18150 if (VT == MVT::v8i32) {
18151 const int HighMask[] = {1, 9, 3, 11, 5, 13, 7, 15};
18152 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
18153 const int LowMask[] = {0, 8, 2, 10, 4, 12, 6, 14};
18154 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
18156 const int HighMask[] = {1, 5, 3, 7};
18157 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
18158 const int LowMask[] = {0, 4, 2, 6};
18159 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
18162 // If we have a signed multiply but no PMULDQ fix up the high parts of a
18163 // unsigned multiply.
18164 if (IsSigned && !Subtarget->hasSSE41()) {
18165 SDValue ShAmt = DAG.getConstant(
18167 DAG.getTargetLoweringInfo().getShiftAmountTy(VT, DAG.getDataLayout()));
18168 SDValue T1 = DAG.getNode(ISD::AND, dl, VT,
18169 DAG.getNode(ISD::SRA, dl, VT, Op0, ShAmt), Op1);
18170 SDValue T2 = DAG.getNode(ISD::AND, dl, VT,
18171 DAG.getNode(ISD::SRA, dl, VT, Op1, ShAmt), Op0);
18173 SDValue Fixup = DAG.getNode(ISD::ADD, dl, VT, T1, T2);
18174 Highs = DAG.getNode(ISD::SUB, dl, VT, Highs, Fixup);
18177 // The first result of MUL_LOHI is actually the low value, followed by the
18179 SDValue Ops[] = {Lows, Highs};
18180 return DAG.getMergeValues(Ops, dl);
18183 // Return true if the required (according to Opcode) shift-imm form is natively
18184 // supported by the Subtarget
18185 static bool SupportedVectorShiftWithImm(MVT VT, const X86Subtarget *Subtarget,
18187 if (VT.getScalarSizeInBits() < 16)
18190 if (VT.is512BitVector() &&
18191 (VT.getScalarSizeInBits() > 16 || Subtarget->hasBWI()))
18194 bool LShift = VT.is128BitVector() ||
18195 (VT.is256BitVector() && Subtarget->hasInt256());
18197 bool AShift = LShift && (Subtarget->hasVLX() ||
18198 (VT != MVT::v2i64 && VT != MVT::v4i64));
18199 return (Opcode == ISD::SRA) ? AShift : LShift;
18202 // The shift amount is a variable, but it is the same for all vector lanes.
18203 // These instructions are defined together with shift-immediate.
18205 bool SupportedVectorShiftWithBaseAmnt(MVT VT, const X86Subtarget *Subtarget,
18207 return SupportedVectorShiftWithImm(VT, Subtarget, Opcode);
18210 // Return true if the required (according to Opcode) variable-shift form is
18211 // natively supported by the Subtarget
18212 static bool SupportedVectorVarShift(MVT VT, const X86Subtarget *Subtarget,
18215 if (!Subtarget->hasInt256() || VT.getScalarSizeInBits() < 16)
18218 // vXi16 supported only on AVX-512, BWI
18219 if (VT.getScalarSizeInBits() == 16 && !Subtarget->hasBWI())
18222 if (VT.is512BitVector() || Subtarget->hasVLX())
18225 bool LShift = VT.is128BitVector() || VT.is256BitVector();
18226 bool AShift = LShift && VT != MVT::v2i64 && VT != MVT::v4i64;
18227 return (Opcode == ISD::SRA) ? AShift : LShift;
18230 static SDValue LowerScalarImmediateShift(SDValue Op, SelectionDAG &DAG,
18231 const X86Subtarget *Subtarget) {
18232 MVT VT = Op.getSimpleValueType();
18234 SDValue R = Op.getOperand(0);
18235 SDValue Amt = Op.getOperand(1);
18237 unsigned X86Opc = (Op.getOpcode() == ISD::SHL) ? X86ISD::VSHLI :
18238 (Op.getOpcode() == ISD::SRL) ? X86ISD::VSRLI : X86ISD::VSRAI;
18240 auto ArithmeticShiftRight64 = [&](uint64_t ShiftAmt) {
18241 assert((VT == MVT::v2i64 || VT == MVT::v4i64) && "Unexpected SRA type");
18242 MVT ExVT = MVT::getVectorVT(MVT::i32, VT.getVectorNumElements() * 2);
18243 SDValue Ex = DAG.getBitcast(ExVT, R);
18245 if (ShiftAmt >= 32) {
18246 // Splat sign to upper i32 dst, and SRA upper i32 src to lower i32.
18248 getTargetVShiftByConstNode(X86ISD::VSRAI, dl, ExVT, Ex, 31, DAG);
18249 SDValue Lower = getTargetVShiftByConstNode(X86ISD::VSRAI, dl, ExVT, Ex,
18250 ShiftAmt - 32, DAG);
18251 if (VT == MVT::v2i64)
18252 Ex = DAG.getVectorShuffle(ExVT, dl, Upper, Lower, {5, 1, 7, 3});
18253 if (VT == MVT::v4i64)
18254 Ex = DAG.getVectorShuffle(ExVT, dl, Upper, Lower,
18255 {9, 1, 11, 3, 13, 5, 15, 7});
18257 // SRA upper i32, SHL whole i64 and select lower i32.
18258 SDValue Upper = getTargetVShiftByConstNode(X86ISD::VSRAI, dl, ExVT, Ex,
18261 getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, R, ShiftAmt, DAG);
18262 Lower = DAG.getBitcast(ExVT, Lower);
18263 if (VT == MVT::v2i64)
18264 Ex = DAG.getVectorShuffle(ExVT, dl, Upper, Lower, {4, 1, 6, 3});
18265 if (VT == MVT::v4i64)
18266 Ex = DAG.getVectorShuffle(ExVT, dl, Upper, Lower,
18267 {8, 1, 10, 3, 12, 5, 14, 7});
18269 return DAG.getBitcast(VT, Ex);
18272 // Optimize shl/srl/sra with constant shift amount.
18273 if (auto *BVAmt = dyn_cast<BuildVectorSDNode>(Amt)) {
18274 if (auto *ShiftConst = BVAmt->getConstantSplatNode()) {
18275 uint64_t ShiftAmt = ShiftConst->getZExtValue();
18277 if (SupportedVectorShiftWithImm(VT, Subtarget, Op.getOpcode()))
18278 return getTargetVShiftByConstNode(X86Opc, dl, VT, R, ShiftAmt, DAG);
18280 // i64 SRA needs to be performed as partial shifts.
18281 if ((VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64)) &&
18282 Op.getOpcode() == ISD::SRA && !Subtarget->hasXOP())
18283 return ArithmeticShiftRight64(ShiftAmt);
18285 if (VT == MVT::v16i8 || (Subtarget->hasInt256() && VT == MVT::v32i8)) {
18286 unsigned NumElts = VT.getVectorNumElements();
18287 MVT ShiftVT = MVT::getVectorVT(MVT::i16, NumElts / 2);
18289 // Simple i8 add case
18290 if (Op.getOpcode() == ISD::SHL && ShiftAmt == 1)
18291 return DAG.getNode(ISD::ADD, dl, VT, R, R);
18293 // ashr(R, 7) === cmp_slt(R, 0)
18294 if (Op.getOpcode() == ISD::SRA && ShiftAmt == 7) {
18295 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
18296 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
18299 // XOP can shift v16i8 directly instead of as shift v8i16 + mask.
18300 if (VT == MVT::v16i8 && Subtarget->hasXOP())
18303 if (Op.getOpcode() == ISD::SHL) {
18304 // Make a large shift.
18305 SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, ShiftVT,
18307 SHL = DAG.getBitcast(VT, SHL);
18308 // Zero out the rightmost bits.
18309 SmallVector<SDValue, 32> V(
18310 NumElts, DAG.getConstant(uint8_t(-1U << ShiftAmt), dl, MVT::i8));
18311 return DAG.getNode(ISD::AND, dl, VT, SHL,
18312 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
18314 if (Op.getOpcode() == ISD::SRL) {
18315 // Make a large shift.
18316 SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, ShiftVT,
18318 SRL = DAG.getBitcast(VT, SRL);
18319 // Zero out the leftmost bits.
18320 SmallVector<SDValue, 32> V(
18321 NumElts, DAG.getConstant(uint8_t(-1U) >> ShiftAmt, dl, MVT::i8));
18322 return DAG.getNode(ISD::AND, dl, VT, SRL,
18323 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
18325 if (Op.getOpcode() == ISD::SRA) {
18326 // ashr(R, Amt) === sub(xor(lshr(R, Amt), Mask), Mask)
18327 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
18328 SmallVector<SDValue, 32> V(NumElts,
18329 DAG.getConstant(128 >> ShiftAmt, dl,
18331 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V);
18332 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
18333 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
18336 llvm_unreachable("Unknown shift opcode.");
18341 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
18342 if (!Subtarget->is64Bit() && !Subtarget->hasXOP() &&
18343 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64))) {
18345 // Peek through any splat that was introduced for i64 shift vectorization.
18346 int SplatIndex = -1;
18347 if (ShuffleVectorSDNode *SVN = dyn_cast<ShuffleVectorSDNode>(Amt.getNode()))
18348 if (SVN->isSplat()) {
18349 SplatIndex = SVN->getSplatIndex();
18350 Amt = Amt.getOperand(0);
18351 assert(SplatIndex < (int)VT.getVectorNumElements() &&
18352 "Splat shuffle referencing second operand");
18355 if (Amt.getOpcode() != ISD::BITCAST ||
18356 Amt.getOperand(0).getOpcode() != ISD::BUILD_VECTOR)
18359 Amt = Amt.getOperand(0);
18360 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
18361 VT.getVectorNumElements();
18362 unsigned RatioInLog2 = Log2_32_Ceil(Ratio);
18363 uint64_t ShiftAmt = 0;
18364 unsigned BaseOp = (SplatIndex < 0 ? 0 : SplatIndex * Ratio);
18365 for (unsigned i = 0; i != Ratio; ++i) {
18366 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Amt.getOperand(i + BaseOp));
18370 ShiftAmt |= C->getZExtValue() << (i * (1 << (6 - RatioInLog2)));
18373 // Check remaining shift amounts (if not a splat).
18374 if (SplatIndex < 0) {
18375 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
18376 uint64_t ShAmt = 0;
18377 for (unsigned j = 0; j != Ratio; ++j) {
18378 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Amt.getOperand(i + j));
18382 ShAmt |= C->getZExtValue() << (j * (1 << (6 - RatioInLog2)));
18384 if (ShAmt != ShiftAmt)
18389 if (SupportedVectorShiftWithImm(VT, Subtarget, Op.getOpcode()))
18390 return getTargetVShiftByConstNode(X86Opc, dl, VT, R, ShiftAmt, DAG);
18392 if (Op.getOpcode() == ISD::SRA)
18393 return ArithmeticShiftRight64(ShiftAmt);
18399 static SDValue LowerScalarVariableShift(SDValue Op, SelectionDAG &DAG,
18400 const X86Subtarget* Subtarget) {
18401 MVT VT = Op.getSimpleValueType();
18403 SDValue R = Op.getOperand(0);
18404 SDValue Amt = Op.getOperand(1);
18406 unsigned X86OpcI = (Op.getOpcode() == ISD::SHL) ? X86ISD::VSHLI :
18407 (Op.getOpcode() == ISD::SRL) ? X86ISD::VSRLI : X86ISD::VSRAI;
18409 unsigned X86OpcV = (Op.getOpcode() == ISD::SHL) ? X86ISD::VSHL :
18410 (Op.getOpcode() == ISD::SRL) ? X86ISD::VSRL : X86ISD::VSRA;
18412 if (SupportedVectorShiftWithBaseAmnt(VT, Subtarget, Op.getOpcode())) {
18414 MVT EltVT = VT.getVectorElementType();
18416 if (BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(Amt)) {
18417 // Check if this build_vector node is doing a splat.
18418 // If so, then set BaseShAmt equal to the splat value.
18419 BaseShAmt = BV->getSplatValue();
18420 if (BaseShAmt && BaseShAmt.getOpcode() == ISD::UNDEF)
18421 BaseShAmt = SDValue();
18423 if (Amt.getOpcode() == ISD::EXTRACT_SUBVECTOR)
18424 Amt = Amt.getOperand(0);
18426 ShuffleVectorSDNode *SVN = dyn_cast<ShuffleVectorSDNode>(Amt);
18427 if (SVN && SVN->isSplat()) {
18428 unsigned SplatIdx = (unsigned)SVN->getSplatIndex();
18429 SDValue InVec = Amt.getOperand(0);
18430 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
18431 assert((SplatIdx < InVec.getSimpleValueType().getVectorNumElements()) &&
18432 "Unexpected shuffle index found!");
18433 BaseShAmt = InVec.getOperand(SplatIdx);
18434 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
18435 if (ConstantSDNode *C =
18436 dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
18437 if (C->getZExtValue() == SplatIdx)
18438 BaseShAmt = InVec.getOperand(1);
18443 // Avoid introducing an extract element from a shuffle.
18444 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InVec,
18445 DAG.getIntPtrConstant(SplatIdx, dl));
18449 if (BaseShAmt.getNode()) {
18450 assert(EltVT.bitsLE(MVT::i64) && "Unexpected element type!");
18451 if (EltVT != MVT::i64 && EltVT.bitsGT(MVT::i32))
18452 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, BaseShAmt);
18453 else if (EltVT.bitsLT(MVT::i32))
18454 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, BaseShAmt);
18456 return getTargetVShiftNode(X86OpcI, dl, VT, R, BaseShAmt, DAG);
18460 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
18461 if (!Subtarget->is64Bit() && VT == MVT::v2i64 &&
18462 Amt.getOpcode() == ISD::BITCAST &&
18463 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
18464 Amt = Amt.getOperand(0);
18465 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
18466 VT.getVectorNumElements();
18467 std::vector<SDValue> Vals(Ratio);
18468 for (unsigned i = 0; i != Ratio; ++i)
18469 Vals[i] = Amt.getOperand(i);
18470 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
18471 for (unsigned j = 0; j != Ratio; ++j)
18472 if (Vals[j] != Amt.getOperand(i + j))
18476 if (SupportedVectorShiftWithBaseAmnt(VT, Subtarget, Op.getOpcode()))
18477 return DAG.getNode(X86OpcV, dl, VT, R, Op.getOperand(1));
18482 static SDValue LowerShift(SDValue Op, const X86Subtarget* Subtarget,
18483 SelectionDAG &DAG) {
18484 MVT VT = Op.getSimpleValueType();
18486 SDValue R = Op.getOperand(0);
18487 SDValue Amt = Op.getOperand(1);
18489 assert(VT.isVector() && "Custom lowering only for vector shifts!");
18490 assert(Subtarget->hasSSE2() && "Only custom lower when we have SSE2!");
18492 if (SDValue V = LowerScalarImmediateShift(Op, DAG, Subtarget))
18495 if (SDValue V = LowerScalarVariableShift(Op, DAG, Subtarget))
18498 if (SupportedVectorVarShift(VT, Subtarget, Op.getOpcode()))
18501 // XOP has 128-bit variable logical/arithmetic shifts.
18502 // +ve/-ve Amt = shift left/right.
18503 if (Subtarget->hasXOP() &&
18504 (VT == MVT::v2i64 || VT == MVT::v4i32 ||
18505 VT == MVT::v8i16 || VT == MVT::v16i8)) {
18506 if (Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SRA) {
18507 SDValue Zero = getZeroVector(VT, Subtarget, DAG, dl);
18508 Amt = DAG.getNode(ISD::SUB, dl, VT, Zero, Amt);
18510 if (Op.getOpcode() == ISD::SHL || Op.getOpcode() == ISD::SRL)
18511 return DAG.getNode(X86ISD::VPSHL, dl, VT, R, Amt);
18512 if (Op.getOpcode() == ISD::SRA)
18513 return DAG.getNode(X86ISD::VPSHA, dl, VT, R, Amt);
18516 // 2i64 vector logical shifts can efficiently avoid scalarization - do the
18517 // shifts per-lane and then shuffle the partial results back together.
18518 if (VT == MVT::v2i64 && Op.getOpcode() != ISD::SRA) {
18519 // Splat the shift amounts so the scalar shifts above will catch it.
18520 SDValue Amt0 = DAG.getVectorShuffle(VT, dl, Amt, Amt, {0, 0});
18521 SDValue Amt1 = DAG.getVectorShuffle(VT, dl, Amt, Amt, {1, 1});
18522 SDValue R0 = DAG.getNode(Op->getOpcode(), dl, VT, R, Amt0);
18523 SDValue R1 = DAG.getNode(Op->getOpcode(), dl, VT, R, Amt1);
18524 return DAG.getVectorShuffle(VT, dl, R0, R1, {0, 3});
18527 // i64 vector arithmetic shift can be emulated with the transform:
18528 // M = lshr(SIGN_BIT, Amt)
18529 // ashr(R, Amt) === sub(xor(lshr(R, Amt), M), M)
18530 if ((VT == MVT::v2i64 || (VT == MVT::v4i64 && Subtarget->hasInt256())) &&
18531 Op.getOpcode() == ISD::SRA) {
18532 SDValue S = DAG.getConstant(APInt::getSignBit(64), dl, VT);
18533 SDValue M = DAG.getNode(ISD::SRL, dl, VT, S, Amt);
18534 R = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
18535 R = DAG.getNode(ISD::XOR, dl, VT, R, M);
18536 R = DAG.getNode(ISD::SUB, dl, VT, R, M);
18540 // If possible, lower this packed shift into a vector multiply instead of
18541 // expanding it into a sequence of scalar shifts.
18542 // Do this only if the vector shift count is a constant build_vector.
18543 if (Op.getOpcode() == ISD::SHL &&
18544 (VT == MVT::v8i16 || VT == MVT::v4i32 ||
18545 (Subtarget->hasInt256() && VT == MVT::v16i16)) &&
18546 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
18547 SmallVector<SDValue, 8> Elts;
18548 MVT SVT = VT.getVectorElementType();
18549 unsigned SVTBits = SVT.getSizeInBits();
18550 APInt One(SVTBits, 1);
18551 unsigned NumElems = VT.getVectorNumElements();
18553 for (unsigned i=0; i !=NumElems; ++i) {
18554 SDValue Op = Amt->getOperand(i);
18555 if (Op->getOpcode() == ISD::UNDEF) {
18556 Elts.push_back(Op);
18560 ConstantSDNode *ND = cast<ConstantSDNode>(Op);
18561 APInt C(SVTBits, ND->getAPIntValue().getZExtValue());
18562 uint64_t ShAmt = C.getZExtValue();
18563 if (ShAmt >= SVTBits) {
18564 Elts.push_back(DAG.getUNDEF(SVT));
18567 Elts.push_back(DAG.getConstant(One.shl(ShAmt), dl, SVT));
18569 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
18570 return DAG.getNode(ISD::MUL, dl, VT, R, BV);
18573 // Lower SHL with variable shift amount.
18574 if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) {
18575 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(23, dl, VT));
18577 Op = DAG.getNode(ISD::ADD, dl, VT, Op,
18578 DAG.getConstant(0x3f800000U, dl, VT));
18579 Op = DAG.getBitcast(MVT::v4f32, Op);
18580 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op);
18581 return DAG.getNode(ISD::MUL, dl, VT, Op, R);
18584 // If possible, lower this shift as a sequence of two shifts by
18585 // constant plus a MOVSS/MOVSD instead of scalarizing it.
18587 // (v4i32 (srl A, (build_vector < X, Y, Y, Y>)))
18589 // Could be rewritten as:
18590 // (v4i32 (MOVSS (srl A, <Y,Y,Y,Y>), (srl A, <X,X,X,X>)))
18592 // The advantage is that the two shifts from the example would be
18593 // lowered as X86ISD::VSRLI nodes. This would be cheaper than scalarizing
18594 // the vector shift into four scalar shifts plus four pairs of vector
18596 if ((VT == MVT::v8i16 || VT == MVT::v4i32) &&
18597 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
18598 unsigned TargetOpcode = X86ISD::MOVSS;
18599 bool CanBeSimplified;
18600 // The splat value for the first packed shift (the 'X' from the example).
18601 SDValue Amt1 = Amt->getOperand(0);
18602 // The splat value for the second packed shift (the 'Y' from the example).
18603 SDValue Amt2 = (VT == MVT::v4i32) ? Amt->getOperand(1) :
18604 Amt->getOperand(2);
18606 // See if it is possible to replace this node with a sequence of
18607 // two shifts followed by a MOVSS/MOVSD
18608 if (VT == MVT::v4i32) {
18609 // Check if it is legal to use a MOVSS.
18610 CanBeSimplified = Amt2 == Amt->getOperand(2) &&
18611 Amt2 == Amt->getOperand(3);
18612 if (!CanBeSimplified) {
18613 // Otherwise, check if we can still simplify this node using a MOVSD.
18614 CanBeSimplified = Amt1 == Amt->getOperand(1) &&
18615 Amt->getOperand(2) == Amt->getOperand(3);
18616 TargetOpcode = X86ISD::MOVSD;
18617 Amt2 = Amt->getOperand(2);
18620 // Do similar checks for the case where the machine value type
18622 CanBeSimplified = Amt1 == Amt->getOperand(1);
18623 for (unsigned i=3; i != 8 && CanBeSimplified; ++i)
18624 CanBeSimplified = Amt2 == Amt->getOperand(i);
18626 if (!CanBeSimplified) {
18627 TargetOpcode = X86ISD::MOVSD;
18628 CanBeSimplified = true;
18629 Amt2 = Amt->getOperand(4);
18630 for (unsigned i=0; i != 4 && CanBeSimplified; ++i)
18631 CanBeSimplified = Amt1 == Amt->getOperand(i);
18632 for (unsigned j=4; j != 8 && CanBeSimplified; ++j)
18633 CanBeSimplified = Amt2 == Amt->getOperand(j);
18637 if (CanBeSimplified && isa<ConstantSDNode>(Amt1) &&
18638 isa<ConstantSDNode>(Amt2)) {
18639 // Replace this node with two shifts followed by a MOVSS/MOVSD.
18640 MVT CastVT = MVT::v4i32;
18642 DAG.getConstant(cast<ConstantSDNode>(Amt1)->getAPIntValue(), dl, VT);
18643 SDValue Shift1 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat1);
18645 DAG.getConstant(cast<ConstantSDNode>(Amt2)->getAPIntValue(), dl, VT);
18646 SDValue Shift2 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat2);
18647 if (TargetOpcode == X86ISD::MOVSD)
18648 CastVT = MVT::v2i64;
18649 SDValue BitCast1 = DAG.getBitcast(CastVT, Shift1);
18650 SDValue BitCast2 = DAG.getBitcast(CastVT, Shift2);
18651 SDValue Result = getTargetShuffleNode(TargetOpcode, dl, CastVT, BitCast2,
18653 return DAG.getBitcast(VT, Result);
18657 // v4i32 Non Uniform Shifts.
18658 // If the shift amount is constant we can shift each lane using the SSE2
18659 // immediate shifts, else we need to zero-extend each lane to the lower i64
18660 // and shift using the SSE2 variable shifts.
18661 // The separate results can then be blended together.
18662 if (VT == MVT::v4i32) {
18663 unsigned Opc = Op.getOpcode();
18664 SDValue Amt0, Amt1, Amt2, Amt3;
18665 if (ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
18666 Amt0 = DAG.getVectorShuffle(VT, dl, Amt, DAG.getUNDEF(VT), {0, 0, 0, 0});
18667 Amt1 = DAG.getVectorShuffle(VT, dl, Amt, DAG.getUNDEF(VT), {1, 1, 1, 1});
18668 Amt2 = DAG.getVectorShuffle(VT, dl, Amt, DAG.getUNDEF(VT), {2, 2, 2, 2});
18669 Amt3 = DAG.getVectorShuffle(VT, dl, Amt, DAG.getUNDEF(VT), {3, 3, 3, 3});
18671 // ISD::SHL is handled above but we include it here for completeness.
18674 llvm_unreachable("Unknown target vector shift node");
18676 Opc = X86ISD::VSHL;
18679 Opc = X86ISD::VSRL;
18682 Opc = X86ISD::VSRA;
18685 // The SSE2 shifts use the lower i64 as the same shift amount for
18686 // all lanes and the upper i64 is ignored. These shuffle masks
18687 // optimally zero-extend each lanes on SSE2/SSE41/AVX targets.
18688 SDValue Z = getZeroVector(VT, Subtarget, DAG, dl);
18689 Amt0 = DAG.getVectorShuffle(VT, dl, Amt, Z, {0, 4, -1, -1});
18690 Amt1 = DAG.getVectorShuffle(VT, dl, Amt, Z, {1, 5, -1, -1});
18691 Amt2 = DAG.getVectorShuffle(VT, dl, Amt, Z, {2, 6, -1, -1});
18692 Amt3 = DAG.getVectorShuffle(VT, dl, Amt, Z, {3, 7, -1, -1});
18695 SDValue R0 = DAG.getNode(Opc, dl, VT, R, Amt0);
18696 SDValue R1 = DAG.getNode(Opc, dl, VT, R, Amt1);
18697 SDValue R2 = DAG.getNode(Opc, dl, VT, R, Amt2);
18698 SDValue R3 = DAG.getNode(Opc, dl, VT, R, Amt3);
18699 SDValue R02 = DAG.getVectorShuffle(VT, dl, R0, R2, {0, -1, 6, -1});
18700 SDValue R13 = DAG.getVectorShuffle(VT, dl, R1, R3, {-1, 1, -1, 7});
18701 return DAG.getVectorShuffle(VT, dl, R02, R13, {0, 5, 2, 7});
18704 if (VT == MVT::v16i8 ||
18705 (VT == MVT::v32i8 && Subtarget->hasInt256() && !Subtarget->hasXOP())) {
18706 MVT ExtVT = MVT::getVectorVT(MVT::i16, VT.getVectorNumElements() / 2);
18707 unsigned ShiftOpcode = Op->getOpcode();
18709 auto SignBitSelect = [&](MVT SelVT, SDValue Sel, SDValue V0, SDValue V1) {
18710 // On SSE41 targets we make use of the fact that VSELECT lowers
18711 // to PBLENDVB which selects bytes based just on the sign bit.
18712 if (Subtarget->hasSSE41()) {
18713 V0 = DAG.getBitcast(VT, V0);
18714 V1 = DAG.getBitcast(VT, V1);
18715 Sel = DAG.getBitcast(VT, Sel);
18716 return DAG.getBitcast(SelVT,
18717 DAG.getNode(ISD::VSELECT, dl, VT, Sel, V0, V1));
18719 // On pre-SSE41 targets we test for the sign bit by comparing to
18720 // zero - a negative value will set all bits of the lanes to true
18721 // and VSELECT uses that in its OR(AND(V0,C),AND(V1,~C)) lowering.
18722 SDValue Z = getZeroVector(SelVT, Subtarget, DAG, dl);
18723 SDValue C = DAG.getNode(X86ISD::PCMPGT, dl, SelVT, Z, Sel);
18724 return DAG.getNode(ISD::VSELECT, dl, SelVT, C, V0, V1);
18727 // Turn 'a' into a mask suitable for VSELECT: a = a << 5;
18728 // We can safely do this using i16 shifts as we're only interested in
18729 // the 3 lower bits of each byte.
18730 Amt = DAG.getBitcast(ExtVT, Amt);
18731 Amt = DAG.getNode(ISD::SHL, dl, ExtVT, Amt, DAG.getConstant(5, dl, ExtVT));
18732 Amt = DAG.getBitcast(VT, Amt);
18734 if (Op->getOpcode() == ISD::SHL || Op->getOpcode() == ISD::SRL) {
18735 // r = VSELECT(r, shift(r, 4), a);
18737 DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(4, dl, VT));
18738 R = SignBitSelect(VT, Amt, M, R);
18741 Amt = DAG.getNode(ISD::ADD, dl, VT, Amt, Amt);
18743 // r = VSELECT(r, shift(r, 2), a);
18744 M = DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(2, dl, VT));
18745 R = SignBitSelect(VT, Amt, M, R);
18748 Amt = DAG.getNode(ISD::ADD, dl, VT, Amt, Amt);
18750 // return VSELECT(r, shift(r, 1), a);
18751 M = DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(1, dl, VT));
18752 R = SignBitSelect(VT, Amt, M, R);
18756 if (Op->getOpcode() == ISD::SRA) {
18757 // For SRA we need to unpack each byte to the higher byte of a i16 vector
18758 // so we can correctly sign extend. We don't care what happens to the
18760 SDValue ALo = DAG.getNode(X86ISD::UNPCKL, dl, VT, DAG.getUNDEF(VT), Amt);
18761 SDValue AHi = DAG.getNode(X86ISD::UNPCKH, dl, VT, DAG.getUNDEF(VT), Amt);
18762 SDValue RLo = DAG.getNode(X86ISD::UNPCKL, dl, VT, DAG.getUNDEF(VT), R);
18763 SDValue RHi = DAG.getNode(X86ISD::UNPCKH, dl, VT, DAG.getUNDEF(VT), R);
18764 ALo = DAG.getBitcast(ExtVT, ALo);
18765 AHi = DAG.getBitcast(ExtVT, AHi);
18766 RLo = DAG.getBitcast(ExtVT, RLo);
18767 RHi = DAG.getBitcast(ExtVT, RHi);
18769 // r = VSELECT(r, shift(r, 4), a);
18770 SDValue MLo = DAG.getNode(ShiftOpcode, dl, ExtVT, RLo,
18771 DAG.getConstant(4, dl, ExtVT));
18772 SDValue MHi = DAG.getNode(ShiftOpcode, dl, ExtVT, RHi,
18773 DAG.getConstant(4, dl, ExtVT));
18774 RLo = SignBitSelect(ExtVT, ALo, MLo, RLo);
18775 RHi = SignBitSelect(ExtVT, AHi, MHi, RHi);
18778 ALo = DAG.getNode(ISD::ADD, dl, ExtVT, ALo, ALo);
18779 AHi = DAG.getNode(ISD::ADD, dl, ExtVT, AHi, AHi);
18781 // r = VSELECT(r, shift(r, 2), a);
18782 MLo = DAG.getNode(ShiftOpcode, dl, ExtVT, RLo,
18783 DAG.getConstant(2, dl, ExtVT));
18784 MHi = DAG.getNode(ShiftOpcode, dl, ExtVT, RHi,
18785 DAG.getConstant(2, dl, ExtVT));
18786 RLo = SignBitSelect(ExtVT, ALo, MLo, RLo);
18787 RHi = SignBitSelect(ExtVT, AHi, MHi, RHi);
18790 ALo = DAG.getNode(ISD::ADD, dl, ExtVT, ALo, ALo);
18791 AHi = DAG.getNode(ISD::ADD, dl, ExtVT, AHi, AHi);
18793 // r = VSELECT(r, shift(r, 1), a);
18794 MLo = DAG.getNode(ShiftOpcode, dl, ExtVT, RLo,
18795 DAG.getConstant(1, dl, ExtVT));
18796 MHi = DAG.getNode(ShiftOpcode, dl, ExtVT, RHi,
18797 DAG.getConstant(1, dl, ExtVT));
18798 RLo = SignBitSelect(ExtVT, ALo, MLo, RLo);
18799 RHi = SignBitSelect(ExtVT, AHi, MHi, RHi);
18801 // Logical shift the result back to the lower byte, leaving a zero upper
18803 // meaning that we can safely pack with PACKUSWB.
18805 DAG.getNode(ISD::SRL, dl, ExtVT, RLo, DAG.getConstant(8, dl, ExtVT));
18807 DAG.getNode(ISD::SRL, dl, ExtVT, RHi, DAG.getConstant(8, dl, ExtVT));
18808 return DAG.getNode(X86ISD::PACKUS, dl, VT, RLo, RHi);
18812 // It's worth extending once and using the v8i32 shifts for 16-bit types, but
18813 // the extra overheads to get from v16i8 to v8i32 make the existing SSE
18814 // solution better.
18815 if (Subtarget->hasInt256() && VT == MVT::v8i16) {
18816 MVT ExtVT = MVT::v8i32;
18818 Op.getOpcode() == ISD::SRA ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
18819 R = DAG.getNode(ExtOpc, dl, ExtVT, R);
18820 Amt = DAG.getNode(ISD::ANY_EXTEND, dl, ExtVT, Amt);
18821 return DAG.getNode(ISD::TRUNCATE, dl, VT,
18822 DAG.getNode(Op.getOpcode(), dl, ExtVT, R, Amt));
18825 if (Subtarget->hasInt256() && !Subtarget->hasXOP() && VT == MVT::v16i16) {
18826 MVT ExtVT = MVT::v8i32;
18827 SDValue Z = getZeroVector(VT, Subtarget, DAG, dl);
18828 SDValue ALo = DAG.getNode(X86ISD::UNPCKL, dl, VT, Amt, Z);
18829 SDValue AHi = DAG.getNode(X86ISD::UNPCKH, dl, VT, Amt, Z);
18830 SDValue RLo = DAG.getNode(X86ISD::UNPCKL, dl, VT, R, R);
18831 SDValue RHi = DAG.getNode(X86ISD::UNPCKH, dl, VT, R, R);
18832 ALo = DAG.getBitcast(ExtVT, ALo);
18833 AHi = DAG.getBitcast(ExtVT, AHi);
18834 RLo = DAG.getBitcast(ExtVT, RLo);
18835 RHi = DAG.getBitcast(ExtVT, RHi);
18836 SDValue Lo = DAG.getNode(Op.getOpcode(), dl, ExtVT, RLo, ALo);
18837 SDValue Hi = DAG.getNode(Op.getOpcode(), dl, ExtVT, RHi, AHi);
18838 Lo = DAG.getNode(ISD::SRL, dl, ExtVT, Lo, DAG.getConstant(16, dl, ExtVT));
18839 Hi = DAG.getNode(ISD::SRL, dl, ExtVT, Hi, DAG.getConstant(16, dl, ExtVT));
18840 return DAG.getNode(X86ISD::PACKUS, dl, VT, Lo, Hi);
18843 if (VT == MVT::v8i16) {
18844 unsigned ShiftOpcode = Op->getOpcode();
18846 auto SignBitSelect = [&](SDValue Sel, SDValue V0, SDValue V1) {
18847 // On SSE41 targets we make use of the fact that VSELECT lowers
18848 // to PBLENDVB which selects bytes based just on the sign bit.
18849 if (Subtarget->hasSSE41()) {
18850 MVT ExtVT = MVT::getVectorVT(MVT::i8, VT.getVectorNumElements() * 2);
18851 V0 = DAG.getBitcast(ExtVT, V0);
18852 V1 = DAG.getBitcast(ExtVT, V1);
18853 Sel = DAG.getBitcast(ExtVT, Sel);
18854 return DAG.getBitcast(
18855 VT, DAG.getNode(ISD::VSELECT, dl, ExtVT, Sel, V0, V1));
18857 // On pre-SSE41 targets we splat the sign bit - a negative value will
18858 // set all bits of the lanes to true and VSELECT uses that in
18859 // its OR(AND(V0,C),AND(V1,~C)) lowering.
18861 DAG.getNode(ISD::SRA, dl, VT, Sel, DAG.getConstant(15, dl, VT));
18862 return DAG.getNode(ISD::VSELECT, dl, VT, C, V0, V1);
18865 // Turn 'a' into a mask suitable for VSELECT: a = a << 12;
18866 if (Subtarget->hasSSE41()) {
18867 // On SSE41 targets we need to replicate the shift mask in both
18868 // bytes for PBLENDVB.
18871 DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(4, dl, VT)),
18872 DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(12, dl, VT)));
18874 Amt = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(12, dl, VT));
18877 // r = VSELECT(r, shift(r, 8), a);
18878 SDValue M = DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(8, dl, VT));
18879 R = SignBitSelect(Amt, M, R);
18882 Amt = DAG.getNode(ISD::ADD, dl, VT, Amt, Amt);
18884 // r = VSELECT(r, shift(r, 4), a);
18885 M = DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(4, dl, VT));
18886 R = SignBitSelect(Amt, M, R);
18889 Amt = DAG.getNode(ISD::ADD, dl, VT, Amt, Amt);
18891 // r = VSELECT(r, shift(r, 2), a);
18892 M = DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(2, dl, VT));
18893 R = SignBitSelect(Amt, M, R);
18896 Amt = DAG.getNode(ISD::ADD, dl, VT, Amt, Amt);
18898 // return VSELECT(r, shift(r, 1), a);
18899 M = DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(1, dl, VT));
18900 R = SignBitSelect(Amt, M, R);
18904 // Decompose 256-bit shifts into smaller 128-bit shifts.
18905 if (VT.is256BitVector()) {
18906 unsigned NumElems = VT.getVectorNumElements();
18907 MVT EltVT = VT.getVectorElementType();
18908 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
18910 // Extract the two vectors
18911 SDValue V1 = Extract128BitVector(R, 0, DAG, dl);
18912 SDValue V2 = Extract128BitVector(R, NumElems/2, DAG, dl);
18914 // Recreate the shift amount vectors
18915 SDValue Amt1, Amt2;
18916 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
18917 // Constant shift amount
18918 SmallVector<SDValue, 8> Ops(Amt->op_begin(), Amt->op_begin() + NumElems);
18919 ArrayRef<SDValue> Amt1Csts = makeArrayRef(Ops).slice(0, NumElems / 2);
18920 ArrayRef<SDValue> Amt2Csts = makeArrayRef(Ops).slice(NumElems / 2);
18922 Amt1 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt1Csts);
18923 Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt2Csts);
18925 // Variable shift amount
18926 Amt1 = Extract128BitVector(Amt, 0, DAG, dl);
18927 Amt2 = Extract128BitVector(Amt, NumElems/2, DAG, dl);
18930 // Issue new vector shifts for the smaller types
18931 V1 = DAG.getNode(Op.getOpcode(), dl, NewVT, V1, Amt1);
18932 V2 = DAG.getNode(Op.getOpcode(), dl, NewVT, V2, Amt2);
18934 // Concatenate the result back
18935 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, V1, V2);
18941 static SDValue LowerRotate(SDValue Op, const X86Subtarget *Subtarget,
18942 SelectionDAG &DAG) {
18943 MVT VT = Op.getSimpleValueType();
18945 SDValue R = Op.getOperand(0);
18946 SDValue Amt = Op.getOperand(1);
18948 assert(VT.isVector() && "Custom lowering only for vector rotates!");
18949 assert(Subtarget->hasXOP() && "XOP support required for vector rotates!");
18950 assert((Op.getOpcode() == ISD::ROTL) && "Only ROTL supported");
18952 // XOP has 128-bit vector variable + immediate rotates.
18953 // +ve/-ve Amt = rotate left/right.
18955 // Split 256-bit integers.
18956 if (VT.is256BitVector())
18957 return Lower256IntArith(Op, DAG);
18959 assert(VT.is128BitVector() && "Only rotate 128-bit vectors!");
18961 // Attempt to rotate by immediate.
18962 if (auto *BVAmt = dyn_cast<BuildVectorSDNode>(Amt)) {
18963 if (auto *RotateConst = BVAmt->getConstantSplatNode()) {
18964 uint64_t RotateAmt = RotateConst->getAPIntValue().getZExtValue();
18965 assert(RotateAmt < VT.getScalarSizeInBits() && "Rotation out of range");
18966 return DAG.getNode(X86ISD::VPROTI, DL, VT, R,
18967 DAG.getConstant(RotateAmt, DL, MVT::i8));
18971 // Use general rotate by variable (per-element).
18972 return DAG.getNode(X86ISD::VPROT, DL, VT, R, Amt);
18975 static SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) {
18976 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
18977 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
18978 // looks for this combo and may remove the "setcc" instruction if the "setcc"
18979 // has only one use.
18980 SDNode *N = Op.getNode();
18981 SDValue LHS = N->getOperand(0);
18982 SDValue RHS = N->getOperand(1);
18983 unsigned BaseOp = 0;
18986 switch (Op.getOpcode()) {
18987 default: llvm_unreachable("Unknown ovf instruction!");
18989 // A subtract of one will be selected as a INC. Note that INC doesn't
18990 // set CF, so we can't do this for UADDO.
18991 if (isOneConstant(RHS)) {
18992 BaseOp = X86ISD::INC;
18993 Cond = X86::COND_O;
18996 BaseOp = X86ISD::ADD;
18997 Cond = X86::COND_O;
19000 BaseOp = X86ISD::ADD;
19001 Cond = X86::COND_B;
19004 // A subtract of one will be selected as a DEC. Note that DEC doesn't
19005 // set CF, so we can't do this for USUBO.
19006 if (isOneConstant(RHS)) {
19007 BaseOp = X86ISD::DEC;
19008 Cond = X86::COND_O;
19011 BaseOp = X86ISD::SUB;
19012 Cond = X86::COND_O;
19015 BaseOp = X86ISD::SUB;
19016 Cond = X86::COND_B;
19019 BaseOp = N->getValueType(0) == MVT::i8 ? X86ISD::SMUL8 : X86ISD::SMUL;
19020 Cond = X86::COND_O;
19022 case ISD::UMULO: { // i64, i8 = umulo lhs, rhs --> i64, i64, i32 umul lhs,rhs
19023 if (N->getValueType(0) == MVT::i8) {
19024 BaseOp = X86ISD::UMUL8;
19025 Cond = X86::COND_O;
19028 SDVTList VTs = DAG.getVTList(N->getValueType(0), N->getValueType(0),
19030 SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS);
19033 DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
19034 DAG.getConstant(X86::COND_O, DL, MVT::i32),
19035 SDValue(Sum.getNode(), 2));
19037 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
19041 // Also sets EFLAGS.
19042 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
19043 SDValue Sum = DAG.getNode(BaseOp, DL, VTs, LHS, RHS);
19046 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1),
19047 DAG.getConstant(Cond, DL, MVT::i32),
19048 SDValue(Sum.getNode(), 1));
19050 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
19053 /// Returns true if the operand type is exactly twice the native width, and
19054 /// the corresponding cmpxchg8b or cmpxchg16b instruction is available.
19055 /// Used to know whether to use cmpxchg8/16b when expanding atomic operations
19056 /// (otherwise we leave them alone to become __sync_fetch_and_... calls).
19057 bool X86TargetLowering::needsCmpXchgNb(Type *MemType) const {
19058 unsigned OpWidth = MemType->getPrimitiveSizeInBits();
19061 return !Subtarget->is64Bit(); // FIXME this should be Subtarget.hasCmpxchg8b
19062 else if (OpWidth == 128)
19063 return Subtarget->hasCmpxchg16b();
19068 bool X86TargetLowering::shouldExpandAtomicStoreInIR(StoreInst *SI) const {
19069 return needsCmpXchgNb(SI->getValueOperand()->getType());
19072 // Note: this turns large loads into lock cmpxchg8b/16b.
19073 // FIXME: On 32 bits x86, fild/movq might be faster than lock cmpxchg8b.
19074 TargetLowering::AtomicExpansionKind
19075 X86TargetLowering::shouldExpandAtomicLoadInIR(LoadInst *LI) const {
19076 auto PTy = cast<PointerType>(LI->getPointerOperand()->getType());
19077 return needsCmpXchgNb(PTy->getElementType()) ? AtomicExpansionKind::CmpXChg
19078 : AtomicExpansionKind::None;
19081 TargetLowering::AtomicExpansionKind
19082 X86TargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const {
19083 unsigned NativeWidth = Subtarget->is64Bit() ? 64 : 32;
19084 Type *MemType = AI->getType();
19086 // If the operand is too big, we must see if cmpxchg8/16b is available
19087 // and default to library calls otherwise.
19088 if (MemType->getPrimitiveSizeInBits() > NativeWidth) {
19089 return needsCmpXchgNb(MemType) ? AtomicExpansionKind::CmpXChg
19090 : AtomicExpansionKind::None;
19093 AtomicRMWInst::BinOp Op = AI->getOperation();
19096 llvm_unreachable("Unknown atomic operation");
19097 case AtomicRMWInst::Xchg:
19098 case AtomicRMWInst::Add:
19099 case AtomicRMWInst::Sub:
19100 // It's better to use xadd, xsub or xchg for these in all cases.
19101 return AtomicExpansionKind::None;
19102 case AtomicRMWInst::Or:
19103 case AtomicRMWInst::And:
19104 case AtomicRMWInst::Xor:
19105 // If the atomicrmw's result isn't actually used, we can just add a "lock"
19106 // prefix to a normal instruction for these operations.
19107 return !AI->use_empty() ? AtomicExpansionKind::CmpXChg
19108 : AtomicExpansionKind::None;
19109 case AtomicRMWInst::Nand:
19110 case AtomicRMWInst::Max:
19111 case AtomicRMWInst::Min:
19112 case AtomicRMWInst::UMax:
19113 case AtomicRMWInst::UMin:
19114 // These always require a non-trivial set of data operations on x86. We must
19115 // use a cmpxchg loop.
19116 return AtomicExpansionKind::CmpXChg;
19120 static bool hasMFENCE(const X86Subtarget& Subtarget) {
19121 // Use mfence if we have SSE2 or we're on x86-64 (even if we asked for
19122 // no-sse2). There isn't any reason to disable it if the target processor
19124 return Subtarget.hasSSE2() || Subtarget.is64Bit();
19128 X86TargetLowering::lowerIdempotentRMWIntoFencedLoad(AtomicRMWInst *AI) const {
19129 unsigned NativeWidth = Subtarget->is64Bit() ? 64 : 32;
19130 Type *MemType = AI->getType();
19131 // Accesses larger than the native width are turned into cmpxchg/libcalls, so
19132 // there is no benefit in turning such RMWs into loads, and it is actually
19133 // harmful as it introduces a mfence.
19134 if (MemType->getPrimitiveSizeInBits() > NativeWidth)
19137 auto Builder = IRBuilder<>(AI);
19138 Module *M = Builder.GetInsertBlock()->getParent()->getParent();
19139 auto SynchScope = AI->getSynchScope();
19140 // We must restrict the ordering to avoid generating loads with Release or
19141 // ReleaseAcquire orderings.
19142 auto Order = AtomicCmpXchgInst::getStrongestFailureOrdering(AI->getOrdering());
19143 auto Ptr = AI->getPointerOperand();
19145 // Before the load we need a fence. Here is an example lifted from
19146 // http://www.hpl.hp.com/techreports/2012/HPL-2012-68.pdf showing why a fence
19149 // x.store(1, relaxed);
19150 // r1 = y.fetch_add(0, release);
19152 // y.fetch_add(42, acquire);
19153 // r2 = x.load(relaxed);
19154 // r1 = r2 = 0 is impossible, but becomes possible if the idempotent rmw is
19155 // lowered to just a load without a fence. A mfence flushes the store buffer,
19156 // making the optimization clearly correct.
19157 // FIXME: it is required if isAtLeastRelease(Order) but it is not clear
19158 // otherwise, we might be able to be more aggressive on relaxed idempotent
19159 // rmw. In practice, they do not look useful, so we don't try to be
19160 // especially clever.
19161 if (SynchScope == SingleThread)
19162 // FIXME: we could just insert an X86ISD::MEMBARRIER here, except we are at
19163 // the IR level, so we must wrap it in an intrinsic.
19166 if (!hasMFENCE(*Subtarget))
19167 // FIXME: it might make sense to use a locked operation here but on a
19168 // different cache-line to prevent cache-line bouncing. In practice it
19169 // is probably a small win, and x86 processors without mfence are rare
19170 // enough that we do not bother.
19174 llvm::Intrinsic::getDeclaration(M, Intrinsic::x86_sse2_mfence);
19175 Builder.CreateCall(MFence, {});
19177 // Finally we can emit the atomic load.
19178 LoadInst *Loaded = Builder.CreateAlignedLoad(Ptr,
19179 AI->getType()->getPrimitiveSizeInBits());
19180 Loaded->setAtomic(Order, SynchScope);
19181 AI->replaceAllUsesWith(Loaded);
19182 AI->eraseFromParent();
19186 static SDValue LowerATOMIC_FENCE(SDValue Op, const X86Subtarget *Subtarget,
19187 SelectionDAG &DAG) {
19189 AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>(
19190 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue());
19191 SynchronizationScope FenceScope = static_cast<SynchronizationScope>(
19192 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
19194 // The only fence that needs an instruction is a sequentially-consistent
19195 // cross-thread fence.
19196 if (FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread) {
19197 if (hasMFENCE(*Subtarget))
19198 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
19200 SDValue Chain = Op.getOperand(0);
19201 SDValue Zero = DAG.getConstant(0, dl, MVT::i32);
19203 DAG.getRegister(X86::ESP, MVT::i32), // Base
19204 DAG.getTargetConstant(1, dl, MVT::i8), // Scale
19205 DAG.getRegister(0, MVT::i32), // Index
19206 DAG.getTargetConstant(0, dl, MVT::i32), // Disp
19207 DAG.getRegister(0, MVT::i32), // Segment.
19211 SDNode *Res = DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops);
19212 return SDValue(Res, 0);
19215 // MEMBARRIER is a compiler barrier; it codegens to a no-op.
19216 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
19219 static SDValue LowerCMP_SWAP(SDValue Op, const X86Subtarget *Subtarget,
19220 SelectionDAG &DAG) {
19221 MVT T = Op.getSimpleValueType();
19225 switch(T.SimpleTy) {
19226 default: llvm_unreachable("Invalid value type!");
19227 case MVT::i8: Reg = X86::AL; size = 1; break;
19228 case MVT::i16: Reg = X86::AX; size = 2; break;
19229 case MVT::i32: Reg = X86::EAX; size = 4; break;
19231 assert(Subtarget->is64Bit() && "Node not type legal!");
19232 Reg = X86::RAX; size = 8;
19235 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg,
19236 Op.getOperand(2), SDValue());
19237 SDValue Ops[] = { cpIn.getValue(0),
19240 DAG.getTargetConstant(size, DL, MVT::i8),
19241 cpIn.getValue(1) };
19242 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
19243 MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand();
19244 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys,
19248 DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1));
19249 SDValue EFLAGS = DAG.getCopyFromReg(cpOut.getValue(1), DL, X86::EFLAGS,
19250 MVT::i32, cpOut.getValue(2));
19251 SDValue Success = DAG.getNode(X86ISD::SETCC, DL, Op->getValueType(1),
19252 DAG.getConstant(X86::COND_E, DL, MVT::i8),
19255 DAG.ReplaceAllUsesOfValueWith(Op.getValue(0), cpOut);
19256 DAG.ReplaceAllUsesOfValueWith(Op.getValue(1), Success);
19257 DAG.ReplaceAllUsesOfValueWith(Op.getValue(2), EFLAGS.getValue(1));
19261 static SDValue LowerBITCAST(SDValue Op, const X86Subtarget *Subtarget,
19262 SelectionDAG &DAG) {
19263 MVT SrcVT = Op.getOperand(0).getSimpleValueType();
19264 MVT DstVT = Op.getSimpleValueType();
19266 if (SrcVT == MVT::v2i32 || SrcVT == MVT::v4i16 || SrcVT == MVT::v8i8) {
19267 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
19268 if (DstVT != MVT::f64)
19269 // This conversion needs to be expanded.
19272 SDValue InVec = Op->getOperand(0);
19274 unsigned NumElts = SrcVT.getVectorNumElements();
19275 MVT SVT = SrcVT.getVectorElementType();
19277 // Widen the vector in input in the case of MVT::v2i32.
19278 // Example: from MVT::v2i32 to MVT::v4i32.
19279 SmallVector<SDValue, 16> Elts;
19280 for (unsigned i = 0, e = NumElts; i != e; ++i)
19281 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT, InVec,
19282 DAG.getIntPtrConstant(i, dl)));
19284 // Explicitly mark the extra elements as Undef.
19285 Elts.append(NumElts, DAG.getUNDEF(SVT));
19287 EVT NewVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
19288 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Elts);
19289 SDValue ToV2F64 = DAG.getBitcast(MVT::v2f64, BV);
19290 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, ToV2F64,
19291 DAG.getIntPtrConstant(0, dl));
19294 assert(Subtarget->is64Bit() && !Subtarget->hasSSE2() &&
19295 Subtarget->hasMMX() && "Unexpected custom BITCAST");
19296 assert((DstVT == MVT::i64 ||
19297 (DstVT.isVector() && DstVT.getSizeInBits()==64)) &&
19298 "Unexpected custom BITCAST");
19299 // i64 <=> MMX conversions are Legal.
19300 if (SrcVT==MVT::i64 && DstVT.isVector())
19302 if (DstVT==MVT::i64 && SrcVT.isVector())
19304 // MMX <=> MMX conversions are Legal.
19305 if (SrcVT.isVector() && DstVT.isVector())
19307 // All other conversions need to be expanded.
19311 /// Compute the horizontal sum of bytes in V for the elements of VT.
19313 /// Requires V to be a byte vector and VT to be an integer vector type with
19314 /// wider elements than V's type. The width of the elements of VT determines
19315 /// how many bytes of V are summed horizontally to produce each element of the
19317 static SDValue LowerHorizontalByteSum(SDValue V, MVT VT,
19318 const X86Subtarget *Subtarget,
19319 SelectionDAG &DAG) {
19321 MVT ByteVecVT = V.getSimpleValueType();
19322 MVT EltVT = VT.getVectorElementType();
19323 int NumElts = VT.getVectorNumElements();
19324 assert(ByteVecVT.getVectorElementType() == MVT::i8 &&
19325 "Expected value to have byte element type.");
19326 assert(EltVT != MVT::i8 &&
19327 "Horizontal byte sum only makes sense for wider elements!");
19328 unsigned VecSize = VT.getSizeInBits();
19329 assert(ByteVecVT.getSizeInBits() == VecSize && "Cannot change vector size!");
19331 // PSADBW instruction horizontally add all bytes and leave the result in i64
19332 // chunks, thus directly computes the pop count for v2i64 and v4i64.
19333 if (EltVT == MVT::i64) {
19334 SDValue Zeros = getZeroVector(ByteVecVT, Subtarget, DAG, DL);
19335 MVT SadVecVT = MVT::getVectorVT(MVT::i64, VecSize / 64);
19336 V = DAG.getNode(X86ISD::PSADBW, DL, SadVecVT, V, Zeros);
19337 return DAG.getBitcast(VT, V);
19340 if (EltVT == MVT::i32) {
19341 // We unpack the low half and high half into i32s interleaved with zeros so
19342 // that we can use PSADBW to horizontally sum them. The most useful part of
19343 // this is that it lines up the results of two PSADBW instructions to be
19344 // two v2i64 vectors which concatenated are the 4 population counts. We can
19345 // then use PACKUSWB to shrink and concatenate them into a v4i32 again.
19346 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, DL);
19347 SDValue Low = DAG.getNode(X86ISD::UNPCKL, DL, VT, V, Zeros);
19348 SDValue High = DAG.getNode(X86ISD::UNPCKH, DL, VT, V, Zeros);
19350 // Do the horizontal sums into two v2i64s.
19351 Zeros = getZeroVector(ByteVecVT, Subtarget, DAG, DL);
19352 MVT SadVecVT = MVT::getVectorVT(MVT::i64, VecSize / 64);
19353 Low = DAG.getNode(X86ISD::PSADBW, DL, SadVecVT,
19354 DAG.getBitcast(ByteVecVT, Low), Zeros);
19355 High = DAG.getNode(X86ISD::PSADBW, DL, SadVecVT,
19356 DAG.getBitcast(ByteVecVT, High), Zeros);
19358 // Merge them together.
19359 MVT ShortVecVT = MVT::getVectorVT(MVT::i16, VecSize / 16);
19360 V = DAG.getNode(X86ISD::PACKUS, DL, ByteVecVT,
19361 DAG.getBitcast(ShortVecVT, Low),
19362 DAG.getBitcast(ShortVecVT, High));
19364 return DAG.getBitcast(VT, V);
19367 // The only element type left is i16.
19368 assert(EltVT == MVT::i16 && "Unknown how to handle type");
19370 // To obtain pop count for each i16 element starting from the pop count for
19371 // i8 elements, shift the i16s left by 8, sum as i8s, and then shift as i16s
19372 // right by 8. It is important to shift as i16s as i8 vector shift isn't
19373 // directly supported.
19374 SmallVector<SDValue, 16> Shifters(NumElts, DAG.getConstant(8, DL, EltVT));
19375 SDValue Shifter = DAG.getNode(ISD::BUILD_VECTOR, DL, VT, Shifters);
19376 SDValue Shl = DAG.getNode(ISD::SHL, DL, VT, DAG.getBitcast(VT, V), Shifter);
19377 V = DAG.getNode(ISD::ADD, DL, ByteVecVT, DAG.getBitcast(ByteVecVT, Shl),
19378 DAG.getBitcast(ByteVecVT, V));
19379 return DAG.getNode(ISD::SRL, DL, VT, DAG.getBitcast(VT, V), Shifter);
19382 static SDValue LowerVectorCTPOPInRegLUT(SDValue Op, SDLoc DL,
19383 const X86Subtarget *Subtarget,
19384 SelectionDAG &DAG) {
19385 MVT VT = Op.getSimpleValueType();
19386 MVT EltVT = VT.getVectorElementType();
19387 unsigned VecSize = VT.getSizeInBits();
19389 // Implement a lookup table in register by using an algorithm based on:
19390 // http://wm.ite.pl/articles/sse-popcount.html
19392 // The general idea is that every lower byte nibble in the input vector is an
19393 // index into a in-register pre-computed pop count table. We then split up the
19394 // input vector in two new ones: (1) a vector with only the shifted-right
19395 // higher nibbles for each byte and (2) a vector with the lower nibbles (and
19396 // masked out higher ones) for each byte. PSHUB is used separately with both
19397 // to index the in-register table. Next, both are added and the result is a
19398 // i8 vector where each element contains the pop count for input byte.
19400 // To obtain the pop count for elements != i8, we follow up with the same
19401 // approach and use additional tricks as described below.
19403 const int LUT[16] = {/* 0 */ 0, /* 1 */ 1, /* 2 */ 1, /* 3 */ 2,
19404 /* 4 */ 1, /* 5 */ 2, /* 6 */ 2, /* 7 */ 3,
19405 /* 8 */ 1, /* 9 */ 2, /* a */ 2, /* b */ 3,
19406 /* c */ 2, /* d */ 3, /* e */ 3, /* f */ 4};
19408 int NumByteElts = VecSize / 8;
19409 MVT ByteVecVT = MVT::getVectorVT(MVT::i8, NumByteElts);
19410 SDValue In = DAG.getBitcast(ByteVecVT, Op);
19411 SmallVector<SDValue, 16> LUTVec;
19412 for (int i = 0; i < NumByteElts; ++i)
19413 LUTVec.push_back(DAG.getConstant(LUT[i % 16], DL, MVT::i8));
19414 SDValue InRegLUT = DAG.getNode(ISD::BUILD_VECTOR, DL, ByteVecVT, LUTVec);
19415 SmallVector<SDValue, 16> Mask0F(NumByteElts,
19416 DAG.getConstant(0x0F, DL, MVT::i8));
19417 SDValue M0F = DAG.getNode(ISD::BUILD_VECTOR, DL, ByteVecVT, Mask0F);
19420 SmallVector<SDValue, 16> Four(NumByteElts, DAG.getConstant(4, DL, MVT::i8));
19421 SDValue FourV = DAG.getNode(ISD::BUILD_VECTOR, DL, ByteVecVT, Four);
19422 SDValue HighNibbles = DAG.getNode(ISD::SRL, DL, ByteVecVT, In, FourV);
19425 SDValue LowNibbles = DAG.getNode(ISD::AND, DL, ByteVecVT, In, M0F);
19427 // The input vector is used as the shuffle mask that index elements into the
19428 // LUT. After counting low and high nibbles, add the vector to obtain the
19429 // final pop count per i8 element.
19430 SDValue HighPopCnt =
19431 DAG.getNode(X86ISD::PSHUFB, DL, ByteVecVT, InRegLUT, HighNibbles);
19432 SDValue LowPopCnt =
19433 DAG.getNode(X86ISD::PSHUFB, DL, ByteVecVT, InRegLUT, LowNibbles);
19434 SDValue PopCnt = DAG.getNode(ISD::ADD, DL, ByteVecVT, HighPopCnt, LowPopCnt);
19436 if (EltVT == MVT::i8)
19439 return LowerHorizontalByteSum(PopCnt, VT, Subtarget, DAG);
19442 static SDValue LowerVectorCTPOPBitmath(SDValue Op, SDLoc DL,
19443 const X86Subtarget *Subtarget,
19444 SelectionDAG &DAG) {
19445 MVT VT = Op.getSimpleValueType();
19446 assert(VT.is128BitVector() &&
19447 "Only 128-bit vector bitmath lowering supported.");
19449 int VecSize = VT.getSizeInBits();
19450 MVT EltVT = VT.getVectorElementType();
19451 int Len = EltVT.getSizeInBits();
19453 // This is the vectorized version of the "best" algorithm from
19454 // http://graphics.stanford.edu/~seander/bithacks.html#CountBitsSetParallel
19455 // with a minor tweak to use a series of adds + shifts instead of vector
19456 // multiplications. Implemented for all integer vector types. We only use
19457 // this when we don't have SSSE3 which allows a LUT-based lowering that is
19458 // much faster, even faster than using native popcnt instructions.
19460 auto GetShift = [&](unsigned OpCode, SDValue V, int Shifter) {
19461 MVT VT = V.getSimpleValueType();
19462 SmallVector<SDValue, 32> Shifters(
19463 VT.getVectorNumElements(),
19464 DAG.getConstant(Shifter, DL, VT.getVectorElementType()));
19465 return DAG.getNode(OpCode, DL, VT, V,
19466 DAG.getNode(ISD::BUILD_VECTOR, DL, VT, Shifters));
19468 auto GetMask = [&](SDValue V, APInt Mask) {
19469 MVT VT = V.getSimpleValueType();
19470 SmallVector<SDValue, 32> Masks(
19471 VT.getVectorNumElements(),
19472 DAG.getConstant(Mask, DL, VT.getVectorElementType()));
19473 return DAG.getNode(ISD::AND, DL, VT, V,
19474 DAG.getNode(ISD::BUILD_VECTOR, DL, VT, Masks));
19477 // We don't want to incur the implicit masks required to SRL vNi8 vectors on
19478 // x86, so set the SRL type to have elements at least i16 wide. This is
19479 // correct because all of our SRLs are followed immediately by a mask anyways
19480 // that handles any bits that sneak into the high bits of the byte elements.
19481 MVT SrlVT = Len > 8 ? VT : MVT::getVectorVT(MVT::i16, VecSize / 16);
19485 // v = v - ((v >> 1) & 0x55555555...)
19487 DAG.getBitcast(VT, GetShift(ISD::SRL, DAG.getBitcast(SrlVT, V), 1));
19488 SDValue And = GetMask(Srl, APInt::getSplat(Len, APInt(8, 0x55)));
19489 V = DAG.getNode(ISD::SUB, DL, VT, V, And);
19491 // v = (v & 0x33333333...) + ((v >> 2) & 0x33333333...)
19492 SDValue AndLHS = GetMask(V, APInt::getSplat(Len, APInt(8, 0x33)));
19493 Srl = DAG.getBitcast(VT, GetShift(ISD::SRL, DAG.getBitcast(SrlVT, V), 2));
19494 SDValue AndRHS = GetMask(Srl, APInt::getSplat(Len, APInt(8, 0x33)));
19495 V = DAG.getNode(ISD::ADD, DL, VT, AndLHS, AndRHS);
19497 // v = (v + (v >> 4)) & 0x0F0F0F0F...
19498 Srl = DAG.getBitcast(VT, GetShift(ISD::SRL, DAG.getBitcast(SrlVT, V), 4));
19499 SDValue Add = DAG.getNode(ISD::ADD, DL, VT, V, Srl);
19500 V = GetMask(Add, APInt::getSplat(Len, APInt(8, 0x0F)));
19502 // At this point, V contains the byte-wise population count, and we are
19503 // merely doing a horizontal sum if necessary to get the wider element
19505 if (EltVT == MVT::i8)
19508 return LowerHorizontalByteSum(
19509 DAG.getBitcast(MVT::getVectorVT(MVT::i8, VecSize / 8), V), VT, Subtarget,
19513 static SDValue LowerVectorCTPOP(SDValue Op, const X86Subtarget *Subtarget,
19514 SelectionDAG &DAG) {
19515 MVT VT = Op.getSimpleValueType();
19516 // FIXME: Need to add AVX-512 support here!
19517 assert((VT.is256BitVector() || VT.is128BitVector()) &&
19518 "Unknown CTPOP type to handle");
19519 SDLoc DL(Op.getNode());
19520 SDValue Op0 = Op.getOperand(0);
19522 if (!Subtarget->hasSSSE3()) {
19523 // We can't use the fast LUT approach, so fall back on vectorized bitmath.
19524 assert(VT.is128BitVector() && "Only 128-bit vectors supported in SSE!");
19525 return LowerVectorCTPOPBitmath(Op0, DL, Subtarget, DAG);
19528 if (VT.is256BitVector() && !Subtarget->hasInt256()) {
19529 unsigned NumElems = VT.getVectorNumElements();
19531 // Extract each 128-bit vector, compute pop count and concat the result.
19532 SDValue LHS = Extract128BitVector(Op0, 0, DAG, DL);
19533 SDValue RHS = Extract128BitVector(Op0, NumElems/2, DAG, DL);
19535 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT,
19536 LowerVectorCTPOPInRegLUT(LHS, DL, Subtarget, DAG),
19537 LowerVectorCTPOPInRegLUT(RHS, DL, Subtarget, DAG));
19540 return LowerVectorCTPOPInRegLUT(Op0, DL, Subtarget, DAG);
19543 static SDValue LowerCTPOP(SDValue Op, const X86Subtarget *Subtarget,
19544 SelectionDAG &DAG) {
19545 assert(Op.getSimpleValueType().isVector() &&
19546 "We only do custom lowering for vector population count.");
19547 return LowerVectorCTPOP(Op, Subtarget, DAG);
19550 static SDValue LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) {
19551 SDNode *Node = Op.getNode();
19553 EVT T = Node->getValueType(0);
19554 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
19555 DAG.getConstant(0, dl, T), Node->getOperand(2));
19556 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
19557 cast<AtomicSDNode>(Node)->getMemoryVT(),
19558 Node->getOperand(0),
19559 Node->getOperand(1), negOp,
19560 cast<AtomicSDNode>(Node)->getMemOperand(),
19561 cast<AtomicSDNode>(Node)->getOrdering(),
19562 cast<AtomicSDNode>(Node)->getSynchScope());
19565 static SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) {
19566 SDNode *Node = Op.getNode();
19568 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
19570 // Convert seq_cst store -> xchg
19571 // Convert wide store -> swap (-> cmpxchg8b/cmpxchg16b)
19572 // FIXME: On 32-bit, store -> fist or movq would be more efficient
19573 // (The only way to get a 16-byte store is cmpxchg16b)
19574 // FIXME: 16-byte ATOMIC_SWAP isn't actually hooked up at the moment.
19575 if (cast<AtomicSDNode>(Node)->getOrdering() == SequentiallyConsistent ||
19576 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
19577 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
19578 cast<AtomicSDNode>(Node)->getMemoryVT(),
19579 Node->getOperand(0),
19580 Node->getOperand(1), Node->getOperand(2),
19581 cast<AtomicSDNode>(Node)->getMemOperand(),
19582 cast<AtomicSDNode>(Node)->getOrdering(),
19583 cast<AtomicSDNode>(Node)->getSynchScope());
19584 return Swap.getValue(1);
19586 // Other atomic stores have a simple pattern.
19590 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
19591 MVT VT = Op.getNode()->getSimpleValueType(0);
19593 // Let legalize expand this if it isn't a legal type yet.
19594 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
19597 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
19600 bool ExtraOp = false;
19601 switch (Op.getOpcode()) {
19602 default: llvm_unreachable("Invalid code");
19603 case ISD::ADDC: Opc = X86ISD::ADD; break;
19604 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break;
19605 case ISD::SUBC: Opc = X86ISD::SUB; break;
19606 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break;
19610 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
19612 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
19613 Op.getOperand(1), Op.getOperand(2));
19616 static SDValue LowerFSINCOS(SDValue Op, const X86Subtarget *Subtarget,
19617 SelectionDAG &DAG) {
19618 assert(Subtarget->isTargetDarwin() && Subtarget->is64Bit());
19620 // For MacOSX, we want to call an alternative entry point: __sincos_stret,
19621 // which returns the values as { float, float } (in XMM0) or
19622 // { double, double } (which is returned in XMM0, XMM1).
19624 SDValue Arg = Op.getOperand(0);
19625 EVT ArgVT = Arg.getValueType();
19626 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
19628 TargetLowering::ArgListTy Args;
19629 TargetLowering::ArgListEntry Entry;
19633 Entry.isSExt = false;
19634 Entry.isZExt = false;
19635 Args.push_back(Entry);
19637 bool isF64 = ArgVT == MVT::f64;
19638 // Only optimize x86_64 for now. i386 is a bit messy. For f32,
19639 // the small struct {f32, f32} is returned in (eax, edx). For f64,
19640 // the results are returned via SRet in memory.
19641 const char *LibcallName = isF64 ? "__sincos_stret" : "__sincosf_stret";
19642 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
19644 DAG.getExternalSymbol(LibcallName, TLI.getPointerTy(DAG.getDataLayout()));
19646 Type *RetTy = isF64
19647 ? (Type*)StructType::get(ArgTy, ArgTy, nullptr)
19648 : (Type*)VectorType::get(ArgTy, 4);
19650 TargetLowering::CallLoweringInfo CLI(DAG);
19651 CLI.setDebugLoc(dl).setChain(DAG.getEntryNode())
19652 .setCallee(CallingConv::C, RetTy, Callee, std::move(Args), 0);
19654 std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI);
19657 // Returned in xmm0 and xmm1.
19658 return CallResult.first;
19660 // Returned in bits 0:31 and 32:64 xmm0.
19661 SDValue SinVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
19662 CallResult.first, DAG.getIntPtrConstant(0, dl));
19663 SDValue CosVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
19664 CallResult.first, DAG.getIntPtrConstant(1, dl));
19665 SDVTList Tys = DAG.getVTList(ArgVT, ArgVT);
19666 return DAG.getNode(ISD::MERGE_VALUES, dl, Tys, SinVal, CosVal);
19669 static SDValue LowerMSCATTER(SDValue Op, const X86Subtarget *Subtarget,
19670 SelectionDAG &DAG) {
19671 assert(Subtarget->hasAVX512() &&
19672 "MGATHER/MSCATTER are supported on AVX-512 arch only");
19674 MaskedScatterSDNode *N = cast<MaskedScatterSDNode>(Op.getNode());
19675 MVT VT = N->getValue().getSimpleValueType();
19676 assert(VT.getScalarSizeInBits() >= 32 && "Unsupported scatter op");
19679 // X86 scatter kills mask register, so its type should be added to
19680 // the list of return values
19681 if (N->getNumValues() == 1) {
19682 SDValue Index = N->getIndex();
19683 if (!Subtarget->hasVLX() && !VT.is512BitVector() &&
19684 !Index.getSimpleValueType().is512BitVector())
19685 Index = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i64, Index);
19687 SDVTList VTs = DAG.getVTList(N->getMask().getValueType(), MVT::Other);
19688 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), N->getOperand(2),
19689 N->getOperand(3), Index };
19691 SDValue NewScatter = DAG.getMaskedScatter(VTs, VT, dl, Ops, N->getMemOperand());
19692 DAG.ReplaceAllUsesWith(Op, SDValue(NewScatter.getNode(), 1));
19693 return SDValue(NewScatter.getNode(), 0);
19698 static SDValue LowerMGATHER(SDValue Op, const X86Subtarget *Subtarget,
19699 SelectionDAG &DAG) {
19700 assert(Subtarget->hasAVX512() &&
19701 "MGATHER/MSCATTER are supported on AVX-512 arch only");
19703 MaskedGatherSDNode *N = cast<MaskedGatherSDNode>(Op.getNode());
19704 MVT VT = Op.getSimpleValueType();
19705 assert(VT.getScalarSizeInBits() >= 32 && "Unsupported gather op");
19708 SDValue Index = N->getIndex();
19709 if (!Subtarget->hasVLX() && !VT.is512BitVector() &&
19710 !Index.getSimpleValueType().is512BitVector()) {
19711 Index = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i64, Index);
19712 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), N->getOperand(2),
19713 N->getOperand(3), Index };
19714 DAG.UpdateNodeOperands(N, Ops);
19719 SDValue X86TargetLowering::LowerGC_TRANSITION_START(SDValue Op,
19720 SelectionDAG &DAG) const {
19721 // TODO: Eventually, the lowering of these nodes should be informed by or
19722 // deferred to the GC strategy for the function in which they appear. For
19723 // now, however, they must be lowered to something. Since they are logically
19724 // no-ops in the case of a null GC strategy (or a GC strategy which does not
19725 // require special handling for these nodes), lower them as literal NOOPs for
19727 SmallVector<SDValue, 2> Ops;
19729 Ops.push_back(Op.getOperand(0));
19730 if (Op->getGluedNode())
19731 Ops.push_back(Op->getOperand(Op->getNumOperands() - 1));
19734 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
19735 SDValue NOOP(DAG.getMachineNode(X86::NOOP, SDLoc(Op), VTs, Ops), 0);
19740 SDValue X86TargetLowering::LowerGC_TRANSITION_END(SDValue Op,
19741 SelectionDAG &DAG) const {
19742 // TODO: Eventually, the lowering of these nodes should be informed by or
19743 // deferred to the GC strategy for the function in which they appear. For
19744 // now, however, they must be lowered to something. Since they are logically
19745 // no-ops in the case of a null GC strategy (or a GC strategy which does not
19746 // require special handling for these nodes), lower them as literal NOOPs for
19748 SmallVector<SDValue, 2> Ops;
19750 Ops.push_back(Op.getOperand(0));
19751 if (Op->getGluedNode())
19752 Ops.push_back(Op->getOperand(Op->getNumOperands() - 1));
19755 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
19756 SDValue NOOP(DAG.getMachineNode(X86::NOOP, SDLoc(Op), VTs, Ops), 0);
19761 /// LowerOperation - Provide custom lowering hooks for some operations.
19763 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
19764 switch (Op.getOpcode()) {
19765 default: llvm_unreachable("Should not custom lower this!");
19766 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, Subtarget, DAG);
19767 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS:
19768 return LowerCMP_SWAP(Op, Subtarget, DAG);
19769 case ISD::CTPOP: return LowerCTPOP(Op, Subtarget, DAG);
19770 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
19771 case ISD::ATOMIC_STORE: return LowerATOMIC_STORE(Op,DAG);
19772 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
19773 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, Subtarget, DAG);
19774 case ISD::VECTOR_SHUFFLE: return lowerVectorShuffle(Op, Subtarget, DAG);
19775 case ISD::VSELECT: return LowerVSELECT(Op, DAG);
19776 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
19777 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
19778 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op,Subtarget,DAG);
19779 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, Subtarget,DAG);
19780 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
19781 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
19782 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
19783 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
19784 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
19785 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
19786 case ISD::SHL_PARTS:
19787 case ISD::SRA_PARTS:
19788 case ISD::SRL_PARTS: return LowerShiftParts(Op, DAG);
19789 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
19790 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
19791 case ISD::TRUNCATE: return LowerTRUNCATE(Op, DAG);
19792 case ISD::ZERO_EXTEND: return LowerZERO_EXTEND(Op, Subtarget, DAG);
19793 case ISD::SIGN_EXTEND: return LowerSIGN_EXTEND(Op, Subtarget, DAG);
19794 case ISD::ANY_EXTEND: return LowerANY_EXTEND(Op, Subtarget, DAG);
19795 case ISD::SIGN_EXTEND_VECTOR_INREG:
19796 return LowerSIGN_EXTEND_VECTOR_INREG(Op, Subtarget, DAG);
19797 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
19798 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
19799 case ISD::FP_EXTEND: return LowerFP_EXTEND(Op, DAG);
19800 case ISD::LOAD: return LowerExtendedLoad(Op, Subtarget, DAG);
19802 case ISD::FNEG: return LowerFABSorFNEG(Op, DAG);
19803 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
19804 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG);
19805 case ISD::SETCC: return LowerSETCC(Op, DAG);
19806 case ISD::SETCCE: return LowerSETCCE(Op, DAG);
19807 case ISD::SELECT: return LowerSELECT(Op, DAG);
19808 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
19809 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
19810 case ISD::VASTART: return LowerVASTART(Op, DAG);
19811 case ISD::VAARG: return LowerVAARG(Op, DAG);
19812 case ISD::VACOPY: return LowerVACOPY(Op, Subtarget, DAG);
19813 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, Subtarget, DAG);
19814 case ISD::INTRINSIC_VOID:
19815 case ISD::INTRINSIC_W_CHAIN: return LowerINTRINSIC_W_CHAIN(Op, Subtarget, DAG);
19816 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
19817 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
19818 case ISD::FRAME_TO_ARGS_OFFSET:
19819 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
19820 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
19821 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
19822 case ISD::EH_SJLJ_SETJMP: return lowerEH_SJLJ_SETJMP(Op, DAG);
19823 case ISD::EH_SJLJ_LONGJMP: return lowerEH_SJLJ_LONGJMP(Op, DAG);
19824 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
19825 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
19826 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
19827 case ISD::CTLZ: return LowerCTLZ(Op, Subtarget, DAG);
19828 case ISD::CTLZ_ZERO_UNDEF: return LowerCTLZ_ZERO_UNDEF(Op, Subtarget, DAG);
19830 case ISD::CTTZ_ZERO_UNDEF: return LowerCTTZ(Op, DAG);
19831 case ISD::MUL: return LowerMUL(Op, Subtarget, DAG);
19832 case ISD::UMUL_LOHI:
19833 case ISD::SMUL_LOHI: return LowerMUL_LOHI(Op, Subtarget, DAG);
19834 case ISD::ROTL: return LowerRotate(Op, Subtarget, DAG);
19837 case ISD::SHL: return LowerShift(Op, Subtarget, DAG);
19843 case ISD::UMULO: return LowerXALUO(Op, DAG);
19844 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, Subtarget,DAG);
19845 case ISD::BITCAST: return LowerBITCAST(Op, Subtarget, DAG);
19849 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
19850 case ISD::ADD: return LowerADD(Op, DAG);
19851 case ISD::SUB: return LowerSUB(Op, DAG);
19855 case ISD::UMIN: return LowerMINMAX(Op, DAG);
19856 case ISD::FSINCOS: return LowerFSINCOS(Op, Subtarget, DAG);
19857 case ISD::MGATHER: return LowerMGATHER(Op, Subtarget, DAG);
19858 case ISD::MSCATTER: return LowerMSCATTER(Op, Subtarget, DAG);
19859 case ISD::GC_TRANSITION_START:
19860 return LowerGC_TRANSITION_START(Op, DAG);
19861 case ISD::GC_TRANSITION_END: return LowerGC_TRANSITION_END(Op, DAG);
19865 /// ReplaceNodeResults - Replace a node with an illegal result type
19866 /// with a new node built out of custom code.
19867 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
19868 SmallVectorImpl<SDValue>&Results,
19869 SelectionDAG &DAG) const {
19871 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
19872 switch (N->getOpcode()) {
19874 llvm_unreachable("Do not know how to custom type legalize this operation!");
19875 case X86ISD::AVG: {
19876 // Legalize types for X86ISD::AVG by expanding vectors.
19877 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
19879 auto InVT = N->getValueType(0);
19880 auto InVTSize = InVT.getSizeInBits();
19881 const unsigned RegSize =
19882 (InVTSize > 128) ? ((InVTSize > 256) ? 512 : 256) : 128;
19883 assert((!Subtarget->hasAVX512() || RegSize < 512) &&
19884 "512-bit vector requires AVX512");
19885 assert((!Subtarget->hasAVX2() || RegSize < 256) &&
19886 "256-bit vector requires AVX2");
19888 auto ElemVT = InVT.getVectorElementType();
19889 auto RegVT = EVT::getVectorVT(*DAG.getContext(), ElemVT,
19890 RegSize / ElemVT.getSizeInBits());
19891 assert(RegSize % InVT.getSizeInBits() == 0);
19892 unsigned NumConcat = RegSize / InVT.getSizeInBits();
19894 SmallVector<SDValue, 16> Ops(NumConcat, DAG.getUNDEF(InVT));
19895 Ops[0] = N->getOperand(0);
19896 SDValue InVec0 = DAG.getNode(ISD::CONCAT_VECTORS, dl, RegVT, Ops);
19897 Ops[0] = N->getOperand(1);
19898 SDValue InVec1 = DAG.getNode(ISD::CONCAT_VECTORS, dl, RegVT, Ops);
19900 SDValue Res = DAG.getNode(X86ISD::AVG, dl, RegVT, InVec0, InVec1);
19901 Results.push_back(DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InVT, Res,
19902 DAG.getIntPtrConstant(0, dl)));
19905 // We might have generated v2f32 FMIN/FMAX operations. Widen them to v4f32.
19906 case X86ISD::FMINC:
19908 case X86ISD::FMAXC:
19909 case X86ISD::FMAX: {
19910 EVT VT = N->getValueType(0);
19911 assert(VT == MVT::v2f32 && "Unexpected type (!= v2f32) on FMIN/FMAX.");
19912 SDValue UNDEF = DAG.getUNDEF(VT);
19913 SDValue LHS = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v4f32,
19914 N->getOperand(0), UNDEF);
19915 SDValue RHS = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v4f32,
19916 N->getOperand(1), UNDEF);
19917 Results.push_back(DAG.getNode(N->getOpcode(), dl, MVT::v4f32, LHS, RHS));
19920 case ISD::SIGN_EXTEND_INREG:
19925 // We don't want to expand or promote these.
19932 case ISD::UDIVREM: {
19933 SDValue V = LowerWin64_i128OP(SDValue(N,0), DAG);
19934 Results.push_back(V);
19937 case ISD::FP_TO_SINT:
19938 case ISD::FP_TO_UINT: {
19939 bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT;
19941 std::pair<SDValue,SDValue> Vals =
19942 FP_TO_INTHelper(SDValue(N, 0), DAG, IsSigned, /*IsReplace=*/ true);
19943 SDValue FIST = Vals.first, StackSlot = Vals.second;
19944 if (FIST.getNode()) {
19945 EVT VT = N->getValueType(0);
19946 // Return a load from the stack slot.
19947 if (StackSlot.getNode())
19948 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot,
19949 MachinePointerInfo(),
19950 false, false, false, 0));
19952 Results.push_back(FIST);
19956 case ISD::UINT_TO_FP: {
19957 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
19958 if (N->getOperand(0).getValueType() != MVT::v2i32 ||
19959 N->getValueType(0) != MVT::v2f32)
19961 SDValue ZExtIn = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v2i64,
19963 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL), dl,
19965 SDValue VBias = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2f64, Bias, Bias);
19966 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64, ZExtIn,
19967 DAG.getBitcast(MVT::v2i64, VBias));
19968 Or = DAG.getBitcast(MVT::v2f64, Or);
19969 // TODO: Are there any fast-math-flags to propagate here?
19970 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, Or, VBias);
19971 Results.push_back(DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, Sub));
19974 case ISD::FP_ROUND: {
19975 if (!TLI.isTypeLegal(N->getOperand(0).getValueType()))
19977 SDValue V = DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, N->getOperand(0));
19978 Results.push_back(V);
19981 case ISD::FP_EXTEND: {
19982 // Right now, only MVT::v2f32 has OperationAction for FP_EXTEND.
19983 // No other ValueType for FP_EXTEND should reach this point.
19984 assert(N->getValueType(0) == MVT::v2f32 &&
19985 "Do not know how to legalize this Node");
19988 case ISD::INTRINSIC_W_CHAIN: {
19989 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
19991 default : llvm_unreachable("Do not know how to custom type "
19992 "legalize this intrinsic operation!");
19993 case Intrinsic::x86_rdtsc:
19994 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
19996 case Intrinsic::x86_rdtscp:
19997 return getReadTimeStampCounter(N, dl, X86ISD::RDTSCP_DAG, DAG, Subtarget,
19999 case Intrinsic::x86_rdpmc:
20000 return getReadPerformanceCounter(N, dl, DAG, Subtarget, Results);
20003 case ISD::INTRINSIC_WO_CHAIN: {
20004 Results.push_back(LowerINTRINSIC_WO_CHAIN(SDValue(N, 0), Subtarget, DAG));
20007 case ISD::READCYCLECOUNTER: {
20008 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
20011 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS: {
20012 EVT T = N->getValueType(0);
20013 assert((T == MVT::i64 || T == MVT::i128) && "can only expand cmpxchg pair");
20014 bool Regs64bit = T == MVT::i128;
20015 MVT HalfT = Regs64bit ? MVT::i64 : MVT::i32;
20016 SDValue cpInL, cpInH;
20017 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
20018 DAG.getConstant(0, dl, HalfT));
20019 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
20020 DAG.getConstant(1, dl, HalfT));
20021 cpInL = DAG.getCopyToReg(N->getOperand(0), dl,
20022 Regs64bit ? X86::RAX : X86::EAX,
20024 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl,
20025 Regs64bit ? X86::RDX : X86::EDX,
20026 cpInH, cpInL.getValue(1));
20027 SDValue swapInL, swapInH;
20028 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
20029 DAG.getConstant(0, dl, HalfT));
20030 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
20031 DAG.getConstant(1, dl, HalfT));
20032 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl,
20033 Regs64bit ? X86::RBX : X86::EBX,
20034 swapInL, cpInH.getValue(1));
20035 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl,
20036 Regs64bit ? X86::RCX : X86::ECX,
20037 swapInH, swapInL.getValue(1));
20038 SDValue Ops[] = { swapInH.getValue(0),
20040 swapInH.getValue(1) };
20041 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
20042 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand();
20043 unsigned Opcode = Regs64bit ? X86ISD::LCMPXCHG16_DAG :
20044 X86ISD::LCMPXCHG8_DAG;
20045 SDValue Result = DAG.getMemIntrinsicNode(Opcode, dl, Tys, Ops, T, MMO);
20046 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl,
20047 Regs64bit ? X86::RAX : X86::EAX,
20048 HalfT, Result.getValue(1));
20049 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl,
20050 Regs64bit ? X86::RDX : X86::EDX,
20051 HalfT, cpOutL.getValue(2));
20052 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
20054 SDValue EFLAGS = DAG.getCopyFromReg(cpOutH.getValue(1), dl, X86::EFLAGS,
20055 MVT::i32, cpOutH.getValue(2));
20057 DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
20058 DAG.getConstant(X86::COND_E, dl, MVT::i8), EFLAGS);
20059 Success = DAG.getZExtOrTrunc(Success, dl, N->getValueType(1));
20061 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, T, OpsF));
20062 Results.push_back(Success);
20063 Results.push_back(EFLAGS.getValue(1));
20066 case ISD::ATOMIC_SWAP:
20067 case ISD::ATOMIC_LOAD_ADD:
20068 case ISD::ATOMIC_LOAD_SUB:
20069 case ISD::ATOMIC_LOAD_AND:
20070 case ISD::ATOMIC_LOAD_OR:
20071 case ISD::ATOMIC_LOAD_XOR:
20072 case ISD::ATOMIC_LOAD_NAND:
20073 case ISD::ATOMIC_LOAD_MIN:
20074 case ISD::ATOMIC_LOAD_MAX:
20075 case ISD::ATOMIC_LOAD_UMIN:
20076 case ISD::ATOMIC_LOAD_UMAX:
20077 case ISD::ATOMIC_LOAD: {
20078 // Delegate to generic TypeLegalization. Situations we can really handle
20079 // should have already been dealt with by AtomicExpandPass.cpp.
20082 case ISD::BITCAST: {
20083 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
20084 EVT DstVT = N->getValueType(0);
20085 EVT SrcVT = N->getOperand(0)->getValueType(0);
20087 if (SrcVT != MVT::f64 ||
20088 (DstVT != MVT::v2i32 && DstVT != MVT::v4i16 && DstVT != MVT::v8i8))
20091 unsigned NumElts = DstVT.getVectorNumElements();
20092 EVT SVT = DstVT.getVectorElementType();
20093 EVT WiderVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
20094 SDValue Expanded = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
20095 MVT::v2f64, N->getOperand(0));
20096 SDValue ToVecInt = DAG.getBitcast(WiderVT, Expanded);
20098 if (ExperimentalVectorWideningLegalization) {
20099 // If we are legalizing vectors by widening, we already have the desired
20100 // legal vector type, just return it.
20101 Results.push_back(ToVecInt);
20105 SmallVector<SDValue, 8> Elts;
20106 for (unsigned i = 0, e = NumElts; i != e; ++i)
20107 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT,
20108 ToVecInt, DAG.getIntPtrConstant(i, dl)));
20110 Results.push_back(DAG.getNode(ISD::BUILD_VECTOR, dl, DstVT, Elts));
20115 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
20116 switch ((X86ISD::NodeType)Opcode) {
20117 case X86ISD::FIRST_NUMBER: break;
20118 case X86ISD::BSF: return "X86ISD::BSF";
20119 case X86ISD::BSR: return "X86ISD::BSR";
20120 case X86ISD::SHLD: return "X86ISD::SHLD";
20121 case X86ISD::SHRD: return "X86ISD::SHRD";
20122 case X86ISD::FAND: return "X86ISD::FAND";
20123 case X86ISD::FANDN: return "X86ISD::FANDN";
20124 case X86ISD::FOR: return "X86ISD::FOR";
20125 case X86ISD::FXOR: return "X86ISD::FXOR";
20126 case X86ISD::FILD: return "X86ISD::FILD";
20127 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
20128 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
20129 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
20130 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
20131 case X86ISD::FLD: return "X86ISD::FLD";
20132 case X86ISD::FST: return "X86ISD::FST";
20133 case X86ISD::CALL: return "X86ISD::CALL";
20134 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
20135 case X86ISD::RDTSCP_DAG: return "X86ISD::RDTSCP_DAG";
20136 case X86ISD::RDPMC_DAG: return "X86ISD::RDPMC_DAG";
20137 case X86ISD::BT: return "X86ISD::BT";
20138 case X86ISD::CMP: return "X86ISD::CMP";
20139 case X86ISD::COMI: return "X86ISD::COMI";
20140 case X86ISD::UCOMI: return "X86ISD::UCOMI";
20141 case X86ISD::CMPM: return "X86ISD::CMPM";
20142 case X86ISD::CMPMU: return "X86ISD::CMPMU";
20143 case X86ISD::CMPM_RND: return "X86ISD::CMPM_RND";
20144 case X86ISD::SETCC: return "X86ISD::SETCC";
20145 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY";
20146 case X86ISD::FSETCC: return "X86ISD::FSETCC";
20147 case X86ISD::FGETSIGNx86: return "X86ISD::FGETSIGNx86";
20148 case X86ISD::CMOV: return "X86ISD::CMOV";
20149 case X86ISD::BRCOND: return "X86ISD::BRCOND";
20150 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
20151 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
20152 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
20153 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
20154 case X86ISD::Wrapper: return "X86ISD::Wrapper";
20155 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
20156 case X86ISD::MOVDQ2Q: return "X86ISD::MOVDQ2Q";
20157 case X86ISD::MMX_MOVD2W: return "X86ISD::MMX_MOVD2W";
20158 case X86ISD::MMX_MOVW2D: return "X86ISD::MMX_MOVW2D";
20159 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
20160 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
20161 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
20162 case X86ISD::PINSRB: return "X86ISD::PINSRB";
20163 case X86ISD::PINSRW: return "X86ISD::PINSRW";
20164 case X86ISD::MMX_PINSRW: return "X86ISD::MMX_PINSRW";
20165 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
20166 case X86ISD::ANDNP: return "X86ISD::ANDNP";
20167 case X86ISD::PSIGN: return "X86ISD::PSIGN";
20168 case X86ISD::BLENDI: return "X86ISD::BLENDI";
20169 case X86ISD::SHRUNKBLEND: return "X86ISD::SHRUNKBLEND";
20170 case X86ISD::ADDUS: return "X86ISD::ADDUS";
20171 case X86ISD::SUBUS: return "X86ISD::SUBUS";
20172 case X86ISD::HADD: return "X86ISD::HADD";
20173 case X86ISD::HSUB: return "X86ISD::HSUB";
20174 case X86ISD::FHADD: return "X86ISD::FHADD";
20175 case X86ISD::FHSUB: return "X86ISD::FHSUB";
20176 case X86ISD::ABS: return "X86ISD::ABS";
20177 case X86ISD::CONFLICT: return "X86ISD::CONFLICT";
20178 case X86ISD::FMAX: return "X86ISD::FMAX";
20179 case X86ISD::FMAX_RND: return "X86ISD::FMAX_RND";
20180 case X86ISD::FMIN: return "X86ISD::FMIN";
20181 case X86ISD::FMIN_RND: return "X86ISD::FMIN_RND";
20182 case X86ISD::FMAXC: return "X86ISD::FMAXC";
20183 case X86ISD::FMINC: return "X86ISD::FMINC";
20184 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
20185 case X86ISD::FRCP: return "X86ISD::FRCP";
20186 case X86ISD::EXTRQI: return "X86ISD::EXTRQI";
20187 case X86ISD::INSERTQI: return "X86ISD::INSERTQI";
20188 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
20189 case X86ISD::TLSBASEADDR: return "X86ISD::TLSBASEADDR";
20190 case X86ISD::TLSCALL: return "X86ISD::TLSCALL";
20191 case X86ISD::EH_SJLJ_SETJMP: return "X86ISD::EH_SJLJ_SETJMP";
20192 case X86ISD::EH_SJLJ_LONGJMP: return "X86ISD::EH_SJLJ_LONGJMP";
20193 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
20194 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
20195 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
20196 case X86ISD::FNSTSW16r: return "X86ISD::FNSTSW16r";
20197 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
20198 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
20199 case X86ISD::LCMPXCHG16_DAG: return "X86ISD::LCMPXCHG16_DAG";
20200 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
20201 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
20202 case X86ISD::VZEXT: return "X86ISD::VZEXT";
20203 case X86ISD::VSEXT: return "X86ISD::VSEXT";
20204 case X86ISD::VTRUNC: return "X86ISD::VTRUNC";
20205 case X86ISD::VTRUNCS: return "X86ISD::VTRUNCS";
20206 case X86ISD::VTRUNCUS: return "X86ISD::VTRUNCUS";
20207 case X86ISD::VINSERT: return "X86ISD::VINSERT";
20208 case X86ISD::VFPEXT: return "X86ISD::VFPEXT";
20209 case X86ISD::VFPROUND: return "X86ISD::VFPROUND";
20210 case X86ISD::CVTDQ2PD: return "X86ISD::CVTDQ2PD";
20211 case X86ISD::CVTUDQ2PD: return "X86ISD::CVTUDQ2PD";
20212 case X86ISD::VSHLDQ: return "X86ISD::VSHLDQ";
20213 case X86ISD::VSRLDQ: return "X86ISD::VSRLDQ";
20214 case X86ISD::VSHL: return "X86ISD::VSHL";
20215 case X86ISD::VSRL: return "X86ISD::VSRL";
20216 case X86ISD::VSRA: return "X86ISD::VSRA";
20217 case X86ISD::VSHLI: return "X86ISD::VSHLI";
20218 case X86ISD::VSRLI: return "X86ISD::VSRLI";
20219 case X86ISD::VSRAI: return "X86ISD::VSRAI";
20220 case X86ISD::CMPP: return "X86ISD::CMPP";
20221 case X86ISD::PCMPEQ: return "X86ISD::PCMPEQ";
20222 case X86ISD::PCMPGT: return "X86ISD::PCMPGT";
20223 case X86ISD::PCMPEQM: return "X86ISD::PCMPEQM";
20224 case X86ISD::PCMPGTM: return "X86ISD::PCMPGTM";
20225 case X86ISD::ADD: return "X86ISD::ADD";
20226 case X86ISD::SUB: return "X86ISD::SUB";
20227 case X86ISD::ADC: return "X86ISD::ADC";
20228 case X86ISD::SBB: return "X86ISD::SBB";
20229 case X86ISD::SMUL: return "X86ISD::SMUL";
20230 case X86ISD::UMUL: return "X86ISD::UMUL";
20231 case X86ISD::SMUL8: return "X86ISD::SMUL8";
20232 case X86ISD::UMUL8: return "X86ISD::UMUL8";
20233 case X86ISD::SDIVREM8_SEXT_HREG: return "X86ISD::SDIVREM8_SEXT_HREG";
20234 case X86ISD::UDIVREM8_ZEXT_HREG: return "X86ISD::UDIVREM8_ZEXT_HREG";
20235 case X86ISD::INC: return "X86ISD::INC";
20236 case X86ISD::DEC: return "X86ISD::DEC";
20237 case X86ISD::OR: return "X86ISD::OR";
20238 case X86ISD::XOR: return "X86ISD::XOR";
20239 case X86ISD::AND: return "X86ISD::AND";
20240 case X86ISD::BEXTR: return "X86ISD::BEXTR";
20241 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
20242 case X86ISD::PTEST: return "X86ISD::PTEST";
20243 case X86ISD::TESTP: return "X86ISD::TESTP";
20244 case X86ISD::TESTM: return "X86ISD::TESTM";
20245 case X86ISD::TESTNM: return "X86ISD::TESTNM";
20246 case X86ISD::KORTEST: return "X86ISD::KORTEST";
20247 case X86ISD::KTEST: return "X86ISD::KTEST";
20248 case X86ISD::PACKSS: return "X86ISD::PACKSS";
20249 case X86ISD::PACKUS: return "X86ISD::PACKUS";
20250 case X86ISD::PALIGNR: return "X86ISD::PALIGNR";
20251 case X86ISD::VALIGN: return "X86ISD::VALIGN";
20252 case X86ISD::PSHUFD: return "X86ISD::PSHUFD";
20253 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW";
20254 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW";
20255 case X86ISD::SHUFP: return "X86ISD::SHUFP";
20256 case X86ISD::SHUF128: return "X86ISD::SHUF128";
20257 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS";
20258 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD";
20259 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS";
20260 case X86ISD::MOVLPS: return "X86ISD::MOVLPS";
20261 case X86ISD::MOVLPD: return "X86ISD::MOVLPD";
20262 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP";
20263 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP";
20264 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP";
20265 case X86ISD::MOVSD: return "X86ISD::MOVSD";
20266 case X86ISD::MOVSS: return "X86ISD::MOVSS";
20267 case X86ISD::UNPCKL: return "X86ISD::UNPCKL";
20268 case X86ISD::UNPCKH: return "X86ISD::UNPCKH";
20269 case X86ISD::VBROADCAST: return "X86ISD::VBROADCAST";
20270 case X86ISD::VBROADCASTM: return "X86ISD::VBROADCASTM";
20271 case X86ISD::SUBV_BROADCAST: return "X86ISD::SUBV_BROADCAST";
20272 case X86ISD::VEXTRACT: return "X86ISD::VEXTRACT";
20273 case X86ISD::VPERMILPV: return "X86ISD::VPERMILPV";
20274 case X86ISD::VPERMILPI: return "X86ISD::VPERMILPI";
20275 case X86ISD::VPERM2X128: return "X86ISD::VPERM2X128";
20276 case X86ISD::VPERMV: return "X86ISD::VPERMV";
20277 case X86ISD::VPERMV3: return "X86ISD::VPERMV3";
20278 case X86ISD::VPERMIV3: return "X86ISD::VPERMIV3";
20279 case X86ISD::VPERMI: return "X86ISD::VPERMI";
20280 case X86ISD::VPTERNLOG: return "X86ISD::VPTERNLOG";
20281 case X86ISD::VFIXUPIMM: return "X86ISD::VFIXUPIMM";
20282 case X86ISD::VRANGE: return "X86ISD::VRANGE";
20283 case X86ISD::PMULUDQ: return "X86ISD::PMULUDQ";
20284 case X86ISD::PMULDQ: return "X86ISD::PMULDQ";
20285 case X86ISD::PSADBW: return "X86ISD::PSADBW";
20286 case X86ISD::DBPSADBW: return "X86ISD::DBPSADBW";
20287 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
20288 case X86ISD::VAARG_64: return "X86ISD::VAARG_64";
20289 case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA";
20290 case X86ISD::MEMBARRIER: return "X86ISD::MEMBARRIER";
20291 case X86ISD::MFENCE: return "X86ISD::MFENCE";
20292 case X86ISD::SFENCE: return "X86ISD::SFENCE";
20293 case X86ISD::LFENCE: return "X86ISD::LFENCE";
20294 case X86ISD::SEG_ALLOCA: return "X86ISD::SEG_ALLOCA";
20295 case X86ISD::SAHF: return "X86ISD::SAHF";
20296 case X86ISD::RDRAND: return "X86ISD::RDRAND";
20297 case X86ISD::RDSEED: return "X86ISD::RDSEED";
20298 case X86ISD::VPMADDUBSW: return "X86ISD::VPMADDUBSW";
20299 case X86ISD::VPMADDWD: return "X86ISD::VPMADDWD";
20300 case X86ISD::VPROT: return "X86ISD::VPROT";
20301 case X86ISD::VPROTI: return "X86ISD::VPROTI";
20302 case X86ISD::VPSHA: return "X86ISD::VPSHA";
20303 case X86ISD::VPSHL: return "X86ISD::VPSHL";
20304 case X86ISD::VPCOM: return "X86ISD::VPCOM";
20305 case X86ISD::VPCOMU: return "X86ISD::VPCOMU";
20306 case X86ISD::FMADD: return "X86ISD::FMADD";
20307 case X86ISD::FMSUB: return "X86ISD::FMSUB";
20308 case X86ISD::FNMADD: return "X86ISD::FNMADD";
20309 case X86ISD::FNMSUB: return "X86ISD::FNMSUB";
20310 case X86ISD::FMADDSUB: return "X86ISD::FMADDSUB";
20311 case X86ISD::FMSUBADD: return "X86ISD::FMSUBADD";
20312 case X86ISD::FMADD_RND: return "X86ISD::FMADD_RND";
20313 case X86ISD::FNMADD_RND: return "X86ISD::FNMADD_RND";
20314 case X86ISD::FMSUB_RND: return "X86ISD::FMSUB_RND";
20315 case X86ISD::FNMSUB_RND: return "X86ISD::FNMSUB_RND";
20316 case X86ISD::FMADDSUB_RND: return "X86ISD::FMADDSUB_RND";
20317 case X86ISD::FMSUBADD_RND: return "X86ISD::FMSUBADD_RND";
20318 case X86ISD::VRNDSCALE: return "X86ISD::VRNDSCALE";
20319 case X86ISD::VREDUCE: return "X86ISD::VREDUCE";
20320 case X86ISD::VGETMANT: return "X86ISD::VGETMANT";
20321 case X86ISD::PCMPESTRI: return "X86ISD::PCMPESTRI";
20322 case X86ISD::PCMPISTRI: return "X86ISD::PCMPISTRI";
20323 case X86ISD::XTEST: return "X86ISD::XTEST";
20324 case X86ISD::COMPRESS: return "X86ISD::COMPRESS";
20325 case X86ISD::EXPAND: return "X86ISD::EXPAND";
20326 case X86ISD::SELECT: return "X86ISD::SELECT";
20327 case X86ISD::ADDSUB: return "X86ISD::ADDSUB";
20328 case X86ISD::RCP28: return "X86ISD::RCP28";
20329 case X86ISD::EXP2: return "X86ISD::EXP2";
20330 case X86ISD::RSQRT28: return "X86ISD::RSQRT28";
20331 case X86ISD::FADD_RND: return "X86ISD::FADD_RND";
20332 case X86ISD::FSUB_RND: return "X86ISD::FSUB_RND";
20333 case X86ISD::FMUL_RND: return "X86ISD::FMUL_RND";
20334 case X86ISD::FDIV_RND: return "X86ISD::FDIV_RND";
20335 case X86ISD::FSQRT_RND: return "X86ISD::FSQRT_RND";
20336 case X86ISD::FGETEXP_RND: return "X86ISD::FGETEXP_RND";
20337 case X86ISD::SCALEF: return "X86ISD::SCALEF";
20338 case X86ISD::ADDS: return "X86ISD::ADDS";
20339 case X86ISD::SUBS: return "X86ISD::SUBS";
20340 case X86ISD::AVG: return "X86ISD::AVG";
20341 case X86ISD::MULHRS: return "X86ISD::MULHRS";
20342 case X86ISD::SINT_TO_FP_RND: return "X86ISD::SINT_TO_FP_RND";
20343 case X86ISD::UINT_TO_FP_RND: return "X86ISD::UINT_TO_FP_RND";
20344 case X86ISD::FP_TO_SINT_RND: return "X86ISD::FP_TO_SINT_RND";
20345 case X86ISD::FP_TO_UINT_RND: return "X86ISD::FP_TO_UINT_RND";
20346 case X86ISD::VFPCLASS: return "X86ISD::VFPCLASS";
20347 case X86ISD::VFPCLASSS: return "X86ISD::VFPCLASSS";
20352 // isLegalAddressingMode - Return true if the addressing mode represented
20353 // by AM is legal for this target, for a load/store of the specified type.
20354 bool X86TargetLowering::isLegalAddressingMode(const DataLayout &DL,
20355 const AddrMode &AM, Type *Ty,
20356 unsigned AS) const {
20357 // X86 supports extremely general addressing modes.
20358 CodeModel::Model M = getTargetMachine().getCodeModel();
20359 Reloc::Model R = getTargetMachine().getRelocationModel();
20361 // X86 allows a sign-extended 32-bit immediate field as a displacement.
20362 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != nullptr))
20367 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
20369 // If a reference to this global requires an extra load, we can't fold it.
20370 if (isGlobalStubReference(GVFlags))
20373 // If BaseGV requires a register for the PIC base, we cannot also have a
20374 // BaseReg specified.
20375 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
20378 // If lower 4G is not available, then we must use rip-relative addressing.
20379 if ((M != CodeModel::Small || R != Reloc::Static) &&
20380 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
20384 switch (AM.Scale) {
20390 // These scales always work.
20395 // These scales are formed with basereg+scalereg. Only accept if there is
20400 default: // Other stuff never works.
20407 bool X86TargetLowering::isVectorShiftByScalarCheap(Type *Ty) const {
20408 unsigned Bits = Ty->getScalarSizeInBits();
20410 // 8-bit shifts are always expensive, but versions with a scalar amount aren't
20411 // particularly cheaper than those without.
20415 // On AVX2 there are new vpsllv[dq] instructions (and other shifts), that make
20416 // variable shifts just as cheap as scalar ones.
20417 if (Subtarget->hasInt256() && (Bits == 32 || Bits == 64))
20420 // Otherwise, it's significantly cheaper to shift by a scalar amount than by a
20421 // fully general vector.
20425 bool X86TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
20426 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
20428 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
20429 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
20430 return NumBits1 > NumBits2;
20433 bool X86TargetLowering::allowTruncateForTailCall(Type *Ty1, Type *Ty2) const {
20434 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
20437 if (!isTypeLegal(EVT::getEVT(Ty1)))
20440 assert(Ty1->getPrimitiveSizeInBits() <= 64 && "i128 is probably not a noop");
20442 // Assuming the caller doesn't have a zeroext or signext return parameter,
20443 // truncation all the way down to i1 is valid.
20447 bool X86TargetLowering::isLegalICmpImmediate(int64_t Imm) const {
20448 return isInt<32>(Imm);
20451 bool X86TargetLowering::isLegalAddImmediate(int64_t Imm) const {
20452 // Can also use sub to handle negated immediates.
20453 return isInt<32>(Imm);
20456 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
20457 if (!VT1.isInteger() || !VT2.isInteger())
20459 unsigned NumBits1 = VT1.getSizeInBits();
20460 unsigned NumBits2 = VT2.getSizeInBits();
20461 return NumBits1 > NumBits2;
20464 bool X86TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
20465 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
20466 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit();
20469 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
20470 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
20471 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
20474 bool X86TargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
20475 EVT VT1 = Val.getValueType();
20476 if (isZExtFree(VT1, VT2))
20479 if (Val.getOpcode() != ISD::LOAD)
20482 if (!VT1.isSimple() || !VT1.isInteger() ||
20483 !VT2.isSimple() || !VT2.isInteger())
20486 switch (VT1.getSimpleVT().SimpleTy) {
20491 // X86 has 8, 16, and 32-bit zero-extending loads.
20498 bool X86TargetLowering::isVectorLoadExtDesirable(SDValue) const { return true; }
20501 X86TargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
20502 if (!Subtarget->hasAnyFMA())
20505 VT = VT.getScalarType();
20507 if (!VT.isSimple())
20510 switch (VT.getSimpleVT().SimpleTy) {
20521 bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
20522 // i16 instructions are longer (0x66 prefix) and potentially slower.
20523 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
20526 /// isShuffleMaskLegal - Targets can use this to indicate that they only
20527 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
20528 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
20529 /// are assumed to be legal.
20531 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
20533 if (!VT.isSimple())
20536 // Not for i1 vectors
20537 if (VT.getSimpleVT().getScalarType() == MVT::i1)
20540 // Very little shuffling can be done for 64-bit vectors right now.
20541 if (VT.getSimpleVT().getSizeInBits() == 64)
20544 // We only care that the types being shuffled are legal. The lowering can
20545 // handle any possible shuffle mask that results.
20546 return isTypeLegal(VT.getSimpleVT());
20550 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
20552 // Just delegate to the generic legality, clear masks aren't special.
20553 return isShuffleMaskLegal(Mask, VT);
20556 //===----------------------------------------------------------------------===//
20557 // X86 Scheduler Hooks
20558 //===----------------------------------------------------------------------===//
20560 /// Utility function to emit xbegin specifying the start of an RTM region.
20561 static MachineBasicBlock *EmitXBegin(MachineInstr *MI, MachineBasicBlock *MBB,
20562 const TargetInstrInfo *TII) {
20563 DebugLoc DL = MI->getDebugLoc();
20565 const BasicBlock *BB = MBB->getBasicBlock();
20566 MachineFunction::iterator I = ++MBB->getIterator();
20568 // For the v = xbegin(), we generate
20579 MachineBasicBlock *thisMBB = MBB;
20580 MachineFunction *MF = MBB->getParent();
20581 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
20582 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
20583 MF->insert(I, mainMBB);
20584 MF->insert(I, sinkMBB);
20586 // Transfer the remainder of BB and its successor edges to sinkMBB.
20587 sinkMBB->splice(sinkMBB->begin(), MBB,
20588 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
20589 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
20593 // # fallthrough to mainMBB
20594 // # abortion to sinkMBB
20595 BuildMI(thisMBB, DL, TII->get(X86::XBEGIN_4)).addMBB(sinkMBB);
20596 thisMBB->addSuccessor(mainMBB);
20597 thisMBB->addSuccessor(sinkMBB);
20601 BuildMI(mainMBB, DL, TII->get(X86::MOV32ri), X86::EAX).addImm(-1);
20602 mainMBB->addSuccessor(sinkMBB);
20605 // EAX is live into the sinkMBB
20606 sinkMBB->addLiveIn(X86::EAX);
20607 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
20608 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
20611 MI->eraseFromParent();
20615 // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
20616 // or XMM0_V32I8 in AVX all of this code can be replaced with that
20617 // in the .td file.
20618 static MachineBasicBlock *EmitPCMPSTRM(MachineInstr *MI, MachineBasicBlock *BB,
20619 const TargetInstrInfo *TII) {
20621 switch (MI->getOpcode()) {
20622 default: llvm_unreachable("illegal opcode!");
20623 case X86::PCMPISTRM128REG: Opc = X86::PCMPISTRM128rr; break;
20624 case X86::VPCMPISTRM128REG: Opc = X86::VPCMPISTRM128rr; break;
20625 case X86::PCMPISTRM128MEM: Opc = X86::PCMPISTRM128rm; break;
20626 case X86::VPCMPISTRM128MEM: Opc = X86::VPCMPISTRM128rm; break;
20627 case X86::PCMPESTRM128REG: Opc = X86::PCMPESTRM128rr; break;
20628 case X86::VPCMPESTRM128REG: Opc = X86::VPCMPESTRM128rr; break;
20629 case X86::PCMPESTRM128MEM: Opc = X86::PCMPESTRM128rm; break;
20630 case X86::VPCMPESTRM128MEM: Opc = X86::VPCMPESTRM128rm; break;
20633 DebugLoc dl = MI->getDebugLoc();
20634 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
20636 unsigned NumArgs = MI->getNumOperands();
20637 for (unsigned i = 1; i < NumArgs; ++i) {
20638 MachineOperand &Op = MI->getOperand(i);
20639 if (!(Op.isReg() && Op.isImplicit()))
20640 MIB.addOperand(Op);
20642 if (MI->hasOneMemOperand())
20643 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
20645 BuildMI(*BB, MI, dl,
20646 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
20647 .addReg(X86::XMM0);
20649 MI->eraseFromParent();
20653 // FIXME: Custom handling because TableGen doesn't support multiple implicit
20654 // defs in an instruction pattern
20655 static MachineBasicBlock *EmitPCMPSTRI(MachineInstr *MI, MachineBasicBlock *BB,
20656 const TargetInstrInfo *TII) {
20658 switch (MI->getOpcode()) {
20659 default: llvm_unreachable("illegal opcode!");
20660 case X86::PCMPISTRIREG: Opc = X86::PCMPISTRIrr; break;
20661 case X86::VPCMPISTRIREG: Opc = X86::VPCMPISTRIrr; break;
20662 case X86::PCMPISTRIMEM: Opc = X86::PCMPISTRIrm; break;
20663 case X86::VPCMPISTRIMEM: Opc = X86::VPCMPISTRIrm; break;
20664 case X86::PCMPESTRIREG: Opc = X86::PCMPESTRIrr; break;
20665 case X86::VPCMPESTRIREG: Opc = X86::VPCMPESTRIrr; break;
20666 case X86::PCMPESTRIMEM: Opc = X86::PCMPESTRIrm; break;
20667 case X86::VPCMPESTRIMEM: Opc = X86::VPCMPESTRIrm; break;
20670 DebugLoc dl = MI->getDebugLoc();
20671 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
20673 unsigned NumArgs = MI->getNumOperands(); // remove the results
20674 for (unsigned i = 1; i < NumArgs; ++i) {
20675 MachineOperand &Op = MI->getOperand(i);
20676 if (!(Op.isReg() && Op.isImplicit()))
20677 MIB.addOperand(Op);
20679 if (MI->hasOneMemOperand())
20680 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
20682 BuildMI(*BB, MI, dl,
20683 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
20686 MI->eraseFromParent();
20690 static MachineBasicBlock *EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB,
20691 const X86Subtarget *Subtarget) {
20692 DebugLoc dl = MI->getDebugLoc();
20693 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
20694 // Address into RAX/EAX, other two args into ECX, EDX.
20695 unsigned MemOpc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
20696 unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
20697 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg);
20698 for (int i = 0; i < X86::AddrNumOperands; ++i)
20699 MIB.addOperand(MI->getOperand(i));
20701 unsigned ValOps = X86::AddrNumOperands;
20702 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
20703 .addReg(MI->getOperand(ValOps).getReg());
20704 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EDX)
20705 .addReg(MI->getOperand(ValOps+1).getReg());
20707 // The instruction doesn't actually take any operands though.
20708 BuildMI(*BB, MI, dl, TII->get(X86::MONITORrrr));
20710 MI->eraseFromParent(); // The pseudo is gone now.
20714 MachineBasicBlock *
20715 X86TargetLowering::EmitVAARG64WithCustomInserter(MachineInstr *MI,
20716 MachineBasicBlock *MBB) const {
20717 // Emit va_arg instruction on X86-64.
20719 // Operands to this pseudo-instruction:
20720 // 0 ) Output : destination address (reg)
20721 // 1-5) Input : va_list address (addr, i64mem)
20722 // 6 ) ArgSize : Size (in bytes) of vararg type
20723 // 7 ) ArgMode : 0=overflow only, 1=use gp_offset, 2=use fp_offset
20724 // 8 ) Align : Alignment of type
20725 // 9 ) EFLAGS (implicit-def)
20727 assert(MI->getNumOperands() == 10 && "VAARG_64 should have 10 operands!");
20728 static_assert(X86::AddrNumOperands == 5,
20729 "VAARG_64 assumes 5 address operands");
20731 unsigned DestReg = MI->getOperand(0).getReg();
20732 MachineOperand &Base = MI->getOperand(1);
20733 MachineOperand &Scale = MI->getOperand(2);
20734 MachineOperand &Index = MI->getOperand(3);
20735 MachineOperand &Disp = MI->getOperand(4);
20736 MachineOperand &Segment = MI->getOperand(5);
20737 unsigned ArgSize = MI->getOperand(6).getImm();
20738 unsigned ArgMode = MI->getOperand(7).getImm();
20739 unsigned Align = MI->getOperand(8).getImm();
20741 // Memory Reference
20742 assert(MI->hasOneMemOperand() && "Expected VAARG_64 to have one memoperand");
20743 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
20744 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
20746 // Machine Information
20747 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
20748 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
20749 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64);
20750 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32);
20751 DebugLoc DL = MI->getDebugLoc();
20753 // struct va_list {
20756 // i64 overflow_area (address)
20757 // i64 reg_save_area (address)
20759 // sizeof(va_list) = 24
20760 // alignment(va_list) = 8
20762 unsigned TotalNumIntRegs = 6;
20763 unsigned TotalNumXMMRegs = 8;
20764 bool UseGPOffset = (ArgMode == 1);
20765 bool UseFPOffset = (ArgMode == 2);
20766 unsigned MaxOffset = TotalNumIntRegs * 8 +
20767 (UseFPOffset ? TotalNumXMMRegs * 16 : 0);
20769 /* Align ArgSize to a multiple of 8 */
20770 unsigned ArgSizeA8 = (ArgSize + 7) & ~7;
20771 bool NeedsAlign = (Align > 8);
20773 MachineBasicBlock *thisMBB = MBB;
20774 MachineBasicBlock *overflowMBB;
20775 MachineBasicBlock *offsetMBB;
20776 MachineBasicBlock *endMBB;
20778 unsigned OffsetDestReg = 0; // Argument address computed by offsetMBB
20779 unsigned OverflowDestReg = 0; // Argument address computed by overflowMBB
20780 unsigned OffsetReg = 0;
20782 if (!UseGPOffset && !UseFPOffset) {
20783 // If we only pull from the overflow region, we don't create a branch.
20784 // We don't need to alter control flow.
20785 OffsetDestReg = 0; // unused
20786 OverflowDestReg = DestReg;
20788 offsetMBB = nullptr;
20789 overflowMBB = thisMBB;
20792 // First emit code to check if gp_offset (or fp_offset) is below the bound.
20793 // If so, pull the argument from reg_save_area. (branch to offsetMBB)
20794 // If not, pull from overflow_area. (branch to overflowMBB)
20799 // offsetMBB overflowMBB
20804 // Registers for the PHI in endMBB
20805 OffsetDestReg = MRI.createVirtualRegister(AddrRegClass);
20806 OverflowDestReg = MRI.createVirtualRegister(AddrRegClass);
20808 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
20809 MachineFunction *MF = MBB->getParent();
20810 overflowMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20811 offsetMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20812 endMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20814 MachineFunction::iterator MBBIter = ++MBB->getIterator();
20816 // Insert the new basic blocks
20817 MF->insert(MBBIter, offsetMBB);
20818 MF->insert(MBBIter, overflowMBB);
20819 MF->insert(MBBIter, endMBB);
20821 // Transfer the remainder of MBB and its successor edges to endMBB.
20822 endMBB->splice(endMBB->begin(), thisMBB,
20823 std::next(MachineBasicBlock::iterator(MI)), thisMBB->end());
20824 endMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
20826 // Make offsetMBB and overflowMBB successors of thisMBB
20827 thisMBB->addSuccessor(offsetMBB);
20828 thisMBB->addSuccessor(overflowMBB);
20830 // endMBB is a successor of both offsetMBB and overflowMBB
20831 offsetMBB->addSuccessor(endMBB);
20832 overflowMBB->addSuccessor(endMBB);
20834 // Load the offset value into a register
20835 OffsetReg = MRI.createVirtualRegister(OffsetRegClass);
20836 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg)
20840 .addDisp(Disp, UseFPOffset ? 4 : 0)
20841 .addOperand(Segment)
20842 .setMemRefs(MMOBegin, MMOEnd);
20844 // Check if there is enough room left to pull this argument.
20845 BuildMI(thisMBB, DL, TII->get(X86::CMP32ri))
20847 .addImm(MaxOffset + 8 - ArgSizeA8);
20849 // Branch to "overflowMBB" if offset >= max
20850 // Fall through to "offsetMBB" otherwise
20851 BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE)))
20852 .addMBB(overflowMBB);
20855 // In offsetMBB, emit code to use the reg_save_area.
20857 assert(OffsetReg != 0);
20859 // Read the reg_save_area address.
20860 unsigned RegSaveReg = MRI.createVirtualRegister(AddrRegClass);
20861 BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg)
20866 .addOperand(Segment)
20867 .setMemRefs(MMOBegin, MMOEnd);
20869 // Zero-extend the offset
20870 unsigned OffsetReg64 = MRI.createVirtualRegister(AddrRegClass);
20871 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64)
20874 .addImm(X86::sub_32bit);
20876 // Add the offset to the reg_save_area to get the final address.
20877 BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg)
20878 .addReg(OffsetReg64)
20879 .addReg(RegSaveReg);
20881 // Compute the offset for the next argument
20882 unsigned NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass);
20883 BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg)
20885 .addImm(UseFPOffset ? 16 : 8);
20887 // Store it back into the va_list.
20888 BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr))
20892 .addDisp(Disp, UseFPOffset ? 4 : 0)
20893 .addOperand(Segment)
20894 .addReg(NextOffsetReg)
20895 .setMemRefs(MMOBegin, MMOEnd);
20898 BuildMI(offsetMBB, DL, TII->get(X86::JMP_1))
20903 // Emit code to use overflow area
20906 // Load the overflow_area address into a register.
20907 unsigned OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass);
20908 BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg)
20913 .addOperand(Segment)
20914 .setMemRefs(MMOBegin, MMOEnd);
20916 // If we need to align it, do so. Otherwise, just copy the address
20917 // to OverflowDestReg.
20919 // Align the overflow address
20920 assert((Align & (Align-1)) == 0 && "Alignment must be a power of 2");
20921 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass);
20923 // aligned_addr = (addr + (align-1)) & ~(align-1)
20924 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg)
20925 .addReg(OverflowAddrReg)
20928 BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg)
20930 .addImm(~(uint64_t)(Align-1));
20932 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg)
20933 .addReg(OverflowAddrReg);
20936 // Compute the next overflow address after this argument.
20937 // (the overflow address should be kept 8-byte aligned)
20938 unsigned NextAddrReg = MRI.createVirtualRegister(AddrRegClass);
20939 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg)
20940 .addReg(OverflowDestReg)
20941 .addImm(ArgSizeA8);
20943 // Store the new overflow address.
20944 BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr))
20949 .addOperand(Segment)
20950 .addReg(NextAddrReg)
20951 .setMemRefs(MMOBegin, MMOEnd);
20953 // If we branched, emit the PHI to the front of endMBB.
20955 BuildMI(*endMBB, endMBB->begin(), DL,
20956 TII->get(X86::PHI), DestReg)
20957 .addReg(OffsetDestReg).addMBB(offsetMBB)
20958 .addReg(OverflowDestReg).addMBB(overflowMBB);
20961 // Erase the pseudo instruction
20962 MI->eraseFromParent();
20967 MachineBasicBlock *
20968 X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
20970 MachineBasicBlock *MBB) const {
20971 // Emit code to save XMM registers to the stack. The ABI says that the
20972 // number of registers to save is given in %al, so it's theoretically
20973 // possible to do an indirect jump trick to avoid saving all of them,
20974 // however this code takes a simpler approach and just executes all
20975 // of the stores if %al is non-zero. It's less code, and it's probably
20976 // easier on the hardware branch predictor, and stores aren't all that
20977 // expensive anyway.
20979 // Create the new basic blocks. One block contains all the XMM stores,
20980 // and one block is the final destination regardless of whether any
20981 // stores were performed.
20982 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
20983 MachineFunction *F = MBB->getParent();
20984 MachineFunction::iterator MBBIter = ++MBB->getIterator();
20985 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB);
20986 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB);
20987 F->insert(MBBIter, XMMSaveMBB);
20988 F->insert(MBBIter, EndMBB);
20990 // Transfer the remainder of MBB and its successor edges to EndMBB.
20991 EndMBB->splice(EndMBB->begin(), MBB,
20992 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
20993 EndMBB->transferSuccessorsAndUpdatePHIs(MBB);
20995 // The original block will now fall through to the XMM save block.
20996 MBB->addSuccessor(XMMSaveMBB);
20997 // The XMMSaveMBB will fall through to the end block.
20998 XMMSaveMBB->addSuccessor(EndMBB);
21000 // Now add the instructions.
21001 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
21002 DebugLoc DL = MI->getDebugLoc();
21004 unsigned CountReg = MI->getOperand(0).getReg();
21005 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm();
21006 int64_t VarArgsFPOffset = MI->getOperand(2).getImm();
21008 if (!Subtarget->isCallingConvWin64(F->getFunction()->getCallingConv())) {
21009 // If %al is 0, branch around the XMM save block.
21010 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
21011 BuildMI(MBB, DL, TII->get(X86::JE_1)).addMBB(EndMBB);
21012 MBB->addSuccessor(EndMBB);
21015 // Make sure the last operand is EFLAGS, which gets clobbered by the branch
21016 // that was just emitted, but clearly shouldn't be "saved".
21017 assert((MI->getNumOperands() <= 3 ||
21018 !MI->getOperand(MI->getNumOperands() - 1).isReg() ||
21019 MI->getOperand(MI->getNumOperands() - 1).getReg() == X86::EFLAGS)
21020 && "Expected last argument to be EFLAGS");
21021 unsigned MOVOpc = Subtarget->hasFp256() ? X86::VMOVAPSmr : X86::MOVAPSmr;
21022 // In the XMM save block, save all the XMM argument registers.
21023 for (int i = 3, e = MI->getNumOperands() - 1; i != e; ++i) {
21024 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
21025 MachineMemOperand *MMO = F->getMachineMemOperand(
21026 MachinePointerInfo::getFixedStack(*F, RegSaveFrameIndex, Offset),
21027 MachineMemOperand::MOStore,
21028 /*Size=*/16, /*Align=*/16);
21029 BuildMI(XMMSaveMBB, DL, TII->get(MOVOpc))
21030 .addFrameIndex(RegSaveFrameIndex)
21031 .addImm(/*Scale=*/1)
21032 .addReg(/*IndexReg=*/0)
21033 .addImm(/*Disp=*/Offset)
21034 .addReg(/*Segment=*/0)
21035 .addReg(MI->getOperand(i).getReg())
21036 .addMemOperand(MMO);
21039 MI->eraseFromParent(); // The pseudo instruction is gone now.
21044 // The EFLAGS operand of SelectItr might be missing a kill marker
21045 // because there were multiple uses of EFLAGS, and ISel didn't know
21046 // which to mark. Figure out whether SelectItr should have had a
21047 // kill marker, and set it if it should. Returns the correct kill
21049 static bool checkAndUpdateEFLAGSKill(MachineBasicBlock::iterator SelectItr,
21050 MachineBasicBlock* BB,
21051 const TargetRegisterInfo* TRI) {
21052 // Scan forward through BB for a use/def of EFLAGS.
21053 MachineBasicBlock::iterator miI(std::next(SelectItr));
21054 for (MachineBasicBlock::iterator miE = BB->end(); miI != miE; ++miI) {
21055 const MachineInstr& mi = *miI;
21056 if (mi.readsRegister(X86::EFLAGS))
21058 if (mi.definesRegister(X86::EFLAGS))
21059 break; // Should have kill-flag - update below.
21062 // If we hit the end of the block, check whether EFLAGS is live into a
21064 if (miI == BB->end()) {
21065 for (MachineBasicBlock::succ_iterator sItr = BB->succ_begin(),
21066 sEnd = BB->succ_end();
21067 sItr != sEnd; ++sItr) {
21068 MachineBasicBlock* succ = *sItr;
21069 if (succ->isLiveIn(X86::EFLAGS))
21074 // We found a def, or hit the end of the basic block and EFLAGS wasn't live
21075 // out. SelectMI should have a kill flag on EFLAGS.
21076 SelectItr->addRegisterKilled(X86::EFLAGS, TRI);
21080 // Return true if it is OK for this CMOV pseudo-opcode to be cascaded
21081 // together with other CMOV pseudo-opcodes into a single basic-block with
21082 // conditional jump around it.
21083 static bool isCMOVPseudo(MachineInstr *MI) {
21084 switch (MI->getOpcode()) {
21085 case X86::CMOV_FR32:
21086 case X86::CMOV_FR64:
21087 case X86::CMOV_GR8:
21088 case X86::CMOV_GR16:
21089 case X86::CMOV_GR32:
21090 case X86::CMOV_RFP32:
21091 case X86::CMOV_RFP64:
21092 case X86::CMOV_RFP80:
21093 case X86::CMOV_V2F64:
21094 case X86::CMOV_V2I64:
21095 case X86::CMOV_V4F32:
21096 case X86::CMOV_V4F64:
21097 case X86::CMOV_V4I64:
21098 case X86::CMOV_V16F32:
21099 case X86::CMOV_V8F32:
21100 case X86::CMOV_V8F64:
21101 case X86::CMOV_V8I64:
21102 case X86::CMOV_V8I1:
21103 case X86::CMOV_V16I1:
21104 case X86::CMOV_V32I1:
21105 case X86::CMOV_V64I1:
21113 MachineBasicBlock *
21114 X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
21115 MachineBasicBlock *BB) const {
21116 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
21117 DebugLoc DL = MI->getDebugLoc();
21119 // To "insert" a SELECT_CC instruction, we actually have to insert the
21120 // diamond control-flow pattern. The incoming instruction knows the
21121 // destination vreg to set, the condition code register to branch on, the
21122 // true/false values to select between, and a branch opcode to use.
21123 const BasicBlock *LLVM_BB = BB->getBasicBlock();
21124 MachineFunction::iterator It = ++BB->getIterator();
21129 // cmpTY ccX, r1, r2
21131 // fallthrough --> copy0MBB
21132 MachineBasicBlock *thisMBB = BB;
21133 MachineFunction *F = BB->getParent();
21135 // This code lowers all pseudo-CMOV instructions. Generally it lowers these
21136 // as described above, by inserting a BB, and then making a PHI at the join
21137 // point to select the true and false operands of the CMOV in the PHI.
21139 // The code also handles two different cases of multiple CMOV opcodes
21143 // In this case, there are multiple CMOVs in a row, all which are based on
21144 // the same condition setting (or the exact opposite condition setting).
21145 // In this case we can lower all the CMOVs using a single inserted BB, and
21146 // then make a number of PHIs at the join point to model the CMOVs. The only
21147 // trickiness here, is that in a case like:
21149 // t2 = CMOV cond1 t1, f1
21150 // t3 = CMOV cond1 t2, f2
21152 // when rewriting this into PHIs, we have to perform some renaming on the
21153 // temps since you cannot have a PHI operand refer to a PHI result earlier
21154 // in the same block. The "simple" but wrong lowering would be:
21156 // t2 = PHI t1(BB1), f1(BB2)
21157 // t3 = PHI t2(BB1), f2(BB2)
21159 // but clearly t2 is not defined in BB1, so that is incorrect. The proper
21160 // renaming is to note that on the path through BB1, t2 is really just a
21161 // copy of t1, and do that renaming, properly generating:
21163 // t2 = PHI t1(BB1), f1(BB2)
21164 // t3 = PHI t1(BB1), f2(BB2)
21166 // Case 2, we lower cascaded CMOVs such as
21168 // (CMOV (CMOV F, T, cc1), T, cc2)
21170 // to two successives branches. For that, we look for another CMOV as the
21171 // following instruction.
21173 // Without this, we would add a PHI between the two jumps, which ends up
21174 // creating a few copies all around. For instance, for
21176 // (sitofp (zext (fcmp une)))
21178 // we would generate:
21180 // ucomiss %xmm1, %xmm0
21181 // movss <1.0f>, %xmm0
21182 // movaps %xmm0, %xmm1
21184 // xorps %xmm1, %xmm1
21187 // movaps %xmm1, %xmm0
21191 // because this custom-inserter would have generated:
21203 // A: X = ...; Y = ...
21205 // C: Z = PHI [X, A], [Y, B]
21207 // E: PHI [X, C], [Z, D]
21209 // If we lower both CMOVs in a single step, we can instead generate:
21221 // A: X = ...; Y = ...
21223 // E: PHI [X, A], [X, C], [Y, D]
21225 // Which, in our sitofp/fcmp example, gives us something like:
21227 // ucomiss %xmm1, %xmm0
21228 // movss <1.0f>, %xmm0
21231 // xorps %xmm0, %xmm0
21235 MachineInstr *CascadedCMOV = nullptr;
21236 MachineInstr *LastCMOV = MI;
21237 X86::CondCode CC = X86::CondCode(MI->getOperand(3).getImm());
21238 X86::CondCode OppCC = X86::GetOppositeBranchCondition(CC);
21239 MachineBasicBlock::iterator NextMIIt =
21240 std::next(MachineBasicBlock::iterator(MI));
21242 // Check for case 1, where there are multiple CMOVs with the same condition
21243 // first. Of the two cases of multiple CMOV lowerings, case 1 reduces the
21244 // number of jumps the most.
21246 if (isCMOVPseudo(MI)) {
21247 // See if we have a string of CMOVS with the same condition.
21248 while (NextMIIt != BB->end() &&
21249 isCMOVPseudo(NextMIIt) &&
21250 (NextMIIt->getOperand(3).getImm() == CC ||
21251 NextMIIt->getOperand(3).getImm() == OppCC)) {
21252 LastCMOV = &*NextMIIt;
21257 // This checks for case 2, but only do this if we didn't already find
21258 // case 1, as indicated by LastCMOV == MI.
21259 if (LastCMOV == MI &&
21260 NextMIIt != BB->end() && NextMIIt->getOpcode() == MI->getOpcode() &&
21261 NextMIIt->getOperand(2).getReg() == MI->getOperand(2).getReg() &&
21262 NextMIIt->getOperand(1).getReg() == MI->getOperand(0).getReg()) {
21263 CascadedCMOV = &*NextMIIt;
21266 MachineBasicBlock *jcc1MBB = nullptr;
21268 // If we have a cascaded CMOV, we lower it to two successive branches to
21269 // the same block. EFLAGS is used by both, so mark it as live in the second.
21270 if (CascadedCMOV) {
21271 jcc1MBB = F->CreateMachineBasicBlock(LLVM_BB);
21272 F->insert(It, jcc1MBB);
21273 jcc1MBB->addLiveIn(X86::EFLAGS);
21276 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
21277 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
21278 F->insert(It, copy0MBB);
21279 F->insert(It, sinkMBB);
21281 // If the EFLAGS register isn't dead in the terminator, then claim that it's
21282 // live into the sink and copy blocks.
21283 const TargetRegisterInfo *TRI = Subtarget->getRegisterInfo();
21285 MachineInstr *LastEFLAGSUser = CascadedCMOV ? CascadedCMOV : LastCMOV;
21286 if (!LastEFLAGSUser->killsRegister(X86::EFLAGS) &&
21287 !checkAndUpdateEFLAGSKill(LastEFLAGSUser, BB, TRI)) {
21288 copy0MBB->addLiveIn(X86::EFLAGS);
21289 sinkMBB->addLiveIn(X86::EFLAGS);
21292 // Transfer the remainder of BB and its successor edges to sinkMBB.
21293 sinkMBB->splice(sinkMBB->begin(), BB,
21294 std::next(MachineBasicBlock::iterator(LastCMOV)), BB->end());
21295 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
21297 // Add the true and fallthrough blocks as its successors.
21298 if (CascadedCMOV) {
21299 // The fallthrough block may be jcc1MBB, if we have a cascaded CMOV.
21300 BB->addSuccessor(jcc1MBB);
21302 // In that case, jcc1MBB will itself fallthrough the copy0MBB, and
21303 // jump to the sinkMBB.
21304 jcc1MBB->addSuccessor(copy0MBB);
21305 jcc1MBB->addSuccessor(sinkMBB);
21307 BB->addSuccessor(copy0MBB);
21310 // The true block target of the first (or only) branch is always sinkMBB.
21311 BB->addSuccessor(sinkMBB);
21313 // Create the conditional branch instruction.
21314 unsigned Opc = X86::GetCondBranchFromCond(CC);
21315 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
21317 if (CascadedCMOV) {
21318 unsigned Opc2 = X86::GetCondBranchFromCond(
21319 (X86::CondCode)CascadedCMOV->getOperand(3).getImm());
21320 BuildMI(jcc1MBB, DL, TII->get(Opc2)).addMBB(sinkMBB);
21324 // %FalseValue = ...
21325 // # fallthrough to sinkMBB
21326 copy0MBB->addSuccessor(sinkMBB);
21329 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
21331 MachineBasicBlock::iterator MIItBegin = MachineBasicBlock::iterator(MI);
21332 MachineBasicBlock::iterator MIItEnd =
21333 std::next(MachineBasicBlock::iterator(LastCMOV));
21334 MachineBasicBlock::iterator SinkInsertionPoint = sinkMBB->begin();
21335 DenseMap<unsigned, std::pair<unsigned, unsigned>> RegRewriteTable;
21336 MachineInstrBuilder MIB;
21338 // As we are creating the PHIs, we have to be careful if there is more than
21339 // one. Later CMOVs may reference the results of earlier CMOVs, but later
21340 // PHIs have to reference the individual true/false inputs from earlier PHIs.
21341 // That also means that PHI construction must work forward from earlier to
21342 // later, and that the code must maintain a mapping from earlier PHI's
21343 // destination registers, and the registers that went into the PHI.
21345 for (MachineBasicBlock::iterator MIIt = MIItBegin; MIIt != MIItEnd; ++MIIt) {
21346 unsigned DestReg = MIIt->getOperand(0).getReg();
21347 unsigned Op1Reg = MIIt->getOperand(1).getReg();
21348 unsigned Op2Reg = MIIt->getOperand(2).getReg();
21350 // If this CMOV we are generating is the opposite condition from
21351 // the jump we generated, then we have to swap the operands for the
21352 // PHI that is going to be generated.
21353 if (MIIt->getOperand(3).getImm() == OppCC)
21354 std::swap(Op1Reg, Op2Reg);
21356 if (RegRewriteTable.find(Op1Reg) != RegRewriteTable.end())
21357 Op1Reg = RegRewriteTable[Op1Reg].first;
21359 if (RegRewriteTable.find(Op2Reg) != RegRewriteTable.end())
21360 Op2Reg = RegRewriteTable[Op2Reg].second;
21362 MIB = BuildMI(*sinkMBB, SinkInsertionPoint, DL,
21363 TII->get(X86::PHI), DestReg)
21364 .addReg(Op1Reg).addMBB(copy0MBB)
21365 .addReg(Op2Reg).addMBB(thisMBB);
21367 // Add this PHI to the rewrite table.
21368 RegRewriteTable[DestReg] = std::make_pair(Op1Reg, Op2Reg);
21371 // If we have a cascaded CMOV, the second Jcc provides the same incoming
21372 // value as the first Jcc (the True operand of the SELECT_CC/CMOV nodes).
21373 if (CascadedCMOV) {
21374 MIB.addReg(MI->getOperand(2).getReg()).addMBB(jcc1MBB);
21375 // Copy the PHI result to the register defined by the second CMOV.
21376 BuildMI(*sinkMBB, std::next(MachineBasicBlock::iterator(MIB.getInstr())),
21377 DL, TII->get(TargetOpcode::COPY),
21378 CascadedCMOV->getOperand(0).getReg())
21379 .addReg(MI->getOperand(0).getReg());
21380 CascadedCMOV->eraseFromParent();
21383 // Now remove the CMOV(s).
21384 for (MachineBasicBlock::iterator MIIt = MIItBegin; MIIt != MIItEnd; )
21385 (MIIt++)->eraseFromParent();
21390 MachineBasicBlock *
21391 X86TargetLowering::EmitLoweredAtomicFP(MachineInstr *MI,
21392 MachineBasicBlock *BB) const {
21393 // Combine the following atomic floating-point modification pattern:
21394 // a.store(reg OP a.load(acquire), release)
21395 // Transform them into:
21396 // OPss (%gpr), %xmm
21397 // movss %xmm, (%gpr)
21398 // Or sd equivalent for 64-bit operations.
21400 switch (MI->getOpcode()) {
21401 default: llvm_unreachable("unexpected instr type for EmitLoweredAtomicFP");
21402 case X86::RELEASE_FADD32mr: MOp = X86::MOVSSmr; FOp = X86::ADDSSrm; break;
21403 case X86::RELEASE_FADD64mr: MOp = X86::MOVSDmr; FOp = X86::ADDSDrm; break;
21405 const X86InstrInfo *TII = Subtarget->getInstrInfo();
21406 DebugLoc DL = MI->getDebugLoc();
21407 MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
21408 MachineOperand MSrc = MI->getOperand(0);
21409 unsigned VSrc = MI->getOperand(5).getReg();
21410 const MachineOperand &Disp = MI->getOperand(3);
21411 MachineOperand ZeroDisp = MachineOperand::CreateImm(0);
21412 bool hasDisp = Disp.isGlobal() || Disp.isImm();
21413 if (hasDisp && MSrc.isReg())
21414 MSrc.setIsKill(false);
21415 MachineInstrBuilder MIM = BuildMI(*BB, MI, DL, TII->get(MOp))
21416 .addOperand(/*Base=*/MSrc)
21417 .addImm(/*Scale=*/1)
21418 .addReg(/*Index=*/0)
21419 .addDisp(hasDisp ? Disp : ZeroDisp, /*off=*/0)
21421 MachineInstr *MIO = BuildMI(*BB, (MachineInstr *)MIM, DL, TII->get(FOp),
21422 MRI.createVirtualRegister(MRI.getRegClass(VSrc)))
21424 .addOperand(/*Base=*/MSrc)
21425 .addImm(/*Scale=*/1)
21426 .addReg(/*Index=*/0)
21427 .addDisp(hasDisp ? Disp : ZeroDisp, /*off=*/0)
21428 .addReg(/*Segment=*/0);
21429 MIM.addReg(MIO->getOperand(0).getReg(), RegState::Kill);
21430 MI->eraseFromParent(); // The pseudo instruction is gone now.
21434 MachineBasicBlock *
21435 X86TargetLowering::EmitLoweredSegAlloca(MachineInstr *MI,
21436 MachineBasicBlock *BB) const {
21437 MachineFunction *MF = BB->getParent();
21438 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
21439 DebugLoc DL = MI->getDebugLoc();
21440 const BasicBlock *LLVM_BB = BB->getBasicBlock();
21442 assert(MF->shouldSplitStack());
21444 const bool Is64Bit = Subtarget->is64Bit();
21445 const bool IsLP64 = Subtarget->isTarget64BitLP64();
21447 const unsigned TlsReg = Is64Bit ? X86::FS : X86::GS;
21448 const unsigned TlsOffset = IsLP64 ? 0x70 : Is64Bit ? 0x40 : 0x30;
21451 // ... [Till the alloca]
21452 // If stacklet is not large enough, jump to mallocMBB
21455 // Allocate by subtracting from RSP
21456 // Jump to continueMBB
21459 // Allocate by call to runtime
21463 // [rest of original BB]
21466 MachineBasicBlock *mallocMBB = MF->CreateMachineBasicBlock(LLVM_BB);
21467 MachineBasicBlock *bumpMBB = MF->CreateMachineBasicBlock(LLVM_BB);
21468 MachineBasicBlock *continueMBB = MF->CreateMachineBasicBlock(LLVM_BB);
21470 MachineRegisterInfo &MRI = MF->getRegInfo();
21471 const TargetRegisterClass *AddrRegClass =
21472 getRegClassFor(getPointerTy(MF->getDataLayout()));
21474 unsigned mallocPtrVReg = MRI.createVirtualRegister(AddrRegClass),
21475 bumpSPPtrVReg = MRI.createVirtualRegister(AddrRegClass),
21476 tmpSPVReg = MRI.createVirtualRegister(AddrRegClass),
21477 SPLimitVReg = MRI.createVirtualRegister(AddrRegClass),
21478 sizeVReg = MI->getOperand(1).getReg(),
21479 physSPReg = IsLP64 || Subtarget->isTargetNaCl64() ? X86::RSP : X86::ESP;
21481 MachineFunction::iterator MBBIter = ++BB->getIterator();
21483 MF->insert(MBBIter, bumpMBB);
21484 MF->insert(MBBIter, mallocMBB);
21485 MF->insert(MBBIter, continueMBB);
21487 continueMBB->splice(continueMBB->begin(), BB,
21488 std::next(MachineBasicBlock::iterator(MI)), BB->end());
21489 continueMBB->transferSuccessorsAndUpdatePHIs(BB);
21491 // Add code to the main basic block to check if the stack limit has been hit,
21492 // and if so, jump to mallocMBB otherwise to bumpMBB.
21493 BuildMI(BB, DL, TII->get(TargetOpcode::COPY), tmpSPVReg).addReg(physSPReg);
21494 BuildMI(BB, DL, TII->get(IsLP64 ? X86::SUB64rr:X86::SUB32rr), SPLimitVReg)
21495 .addReg(tmpSPVReg).addReg(sizeVReg);
21496 BuildMI(BB, DL, TII->get(IsLP64 ? X86::CMP64mr:X86::CMP32mr))
21497 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg)
21498 .addReg(SPLimitVReg);
21499 BuildMI(BB, DL, TII->get(X86::JG_1)).addMBB(mallocMBB);
21501 // bumpMBB simply decreases the stack pointer, since we know the current
21502 // stacklet has enough space.
21503 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), physSPReg)
21504 .addReg(SPLimitVReg);
21505 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), bumpSPPtrVReg)
21506 .addReg(SPLimitVReg);
21507 BuildMI(bumpMBB, DL, TII->get(X86::JMP_1)).addMBB(continueMBB);
21509 // Calls into a routine in libgcc to allocate more space from the heap.
21510 const uint32_t *RegMask =
21511 Subtarget->getRegisterInfo()->getCallPreservedMask(*MF, CallingConv::C);
21513 BuildMI(mallocMBB, DL, TII->get(X86::MOV64rr), X86::RDI)
21515 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
21516 .addExternalSymbol("__morestack_allocate_stack_space")
21517 .addRegMask(RegMask)
21518 .addReg(X86::RDI, RegState::Implicit)
21519 .addReg(X86::RAX, RegState::ImplicitDefine);
21520 } else if (Is64Bit) {
21521 BuildMI(mallocMBB, DL, TII->get(X86::MOV32rr), X86::EDI)
21523 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
21524 .addExternalSymbol("__morestack_allocate_stack_space")
21525 .addRegMask(RegMask)
21526 .addReg(X86::EDI, RegState::Implicit)
21527 .addReg(X86::EAX, RegState::ImplicitDefine);
21529 BuildMI(mallocMBB, DL, TII->get(X86::SUB32ri), physSPReg).addReg(physSPReg)
21531 BuildMI(mallocMBB, DL, TII->get(X86::PUSH32r)).addReg(sizeVReg);
21532 BuildMI(mallocMBB, DL, TII->get(X86::CALLpcrel32))
21533 .addExternalSymbol("__morestack_allocate_stack_space")
21534 .addRegMask(RegMask)
21535 .addReg(X86::EAX, RegState::ImplicitDefine);
21539 BuildMI(mallocMBB, DL, TII->get(X86::ADD32ri), physSPReg).addReg(physSPReg)
21542 BuildMI(mallocMBB, DL, TII->get(TargetOpcode::COPY), mallocPtrVReg)
21543 .addReg(IsLP64 ? X86::RAX : X86::EAX);
21544 BuildMI(mallocMBB, DL, TII->get(X86::JMP_1)).addMBB(continueMBB);
21546 // Set up the CFG correctly.
21547 BB->addSuccessor(bumpMBB);
21548 BB->addSuccessor(mallocMBB);
21549 mallocMBB->addSuccessor(continueMBB);
21550 bumpMBB->addSuccessor(continueMBB);
21552 // Take care of the PHI nodes.
21553 BuildMI(*continueMBB, continueMBB->begin(), DL, TII->get(X86::PHI),
21554 MI->getOperand(0).getReg())
21555 .addReg(mallocPtrVReg).addMBB(mallocMBB)
21556 .addReg(bumpSPPtrVReg).addMBB(bumpMBB);
21558 // Delete the original pseudo instruction.
21559 MI->eraseFromParent();
21562 return continueMBB;
21565 MachineBasicBlock *
21566 X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI,
21567 MachineBasicBlock *BB) const {
21568 assert(!Subtarget->isTargetMachO());
21569 DebugLoc DL = MI->getDebugLoc();
21570 MachineInstr *ResumeMI = Subtarget->getFrameLowering()->emitStackProbe(
21571 *BB->getParent(), *BB, MI, DL, false);
21572 MachineBasicBlock *ResumeBB = ResumeMI->getParent();
21573 MI->eraseFromParent(); // The pseudo instruction is gone now.
21577 MachineBasicBlock *
21578 X86TargetLowering::EmitLoweredCatchRet(MachineInstr *MI,
21579 MachineBasicBlock *BB) const {
21580 MachineFunction *MF = BB->getParent();
21581 const TargetInstrInfo &TII = *Subtarget->getInstrInfo();
21582 MachineBasicBlock *TargetMBB = MI->getOperand(0).getMBB();
21583 DebugLoc DL = MI->getDebugLoc();
21585 assert(!isAsynchronousEHPersonality(
21586 classifyEHPersonality(MF->getFunction()->getPersonalityFn())) &&
21587 "SEH does not use catchret!");
21589 // Only 32-bit EH needs to worry about manually restoring stack pointers.
21590 if (!Subtarget->is32Bit())
21593 // C++ EH creates a new target block to hold the restore code, and wires up
21594 // the new block to the return destination with a normal JMP_4.
21595 MachineBasicBlock *RestoreMBB =
21596 MF->CreateMachineBasicBlock(BB->getBasicBlock());
21597 assert(BB->succ_size() == 1);
21598 MF->insert(std::next(BB->getIterator()), RestoreMBB);
21599 RestoreMBB->transferSuccessorsAndUpdatePHIs(BB);
21600 BB->addSuccessor(RestoreMBB);
21601 MI->getOperand(0).setMBB(RestoreMBB);
21603 auto RestoreMBBI = RestoreMBB->begin();
21604 BuildMI(*RestoreMBB, RestoreMBBI, DL, TII.get(X86::EH_RESTORE));
21605 BuildMI(*RestoreMBB, RestoreMBBI, DL, TII.get(X86::JMP_4)).addMBB(TargetMBB);
21609 MachineBasicBlock *
21610 X86TargetLowering::EmitLoweredCatchPad(MachineInstr *MI,
21611 MachineBasicBlock *BB) const {
21612 MachineFunction *MF = BB->getParent();
21613 const Constant *PerFn = MF->getFunction()->getPersonalityFn();
21614 bool IsSEH = isAsynchronousEHPersonality(classifyEHPersonality(PerFn));
21615 // Only 32-bit SEH requires special handling for catchpad.
21616 if (IsSEH && Subtarget->is32Bit()) {
21617 const TargetInstrInfo &TII = *Subtarget->getInstrInfo();
21618 DebugLoc DL = MI->getDebugLoc();
21619 BuildMI(*BB, MI, DL, TII.get(X86::EH_RESTORE));
21621 MI->eraseFromParent();
21625 MachineBasicBlock *
21626 X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI,
21627 MachineBasicBlock *BB) const {
21628 // This is pretty easy. We're taking the value that we received from
21629 // our load from the relocation, sticking it in either RDI (x86-64)
21630 // or EAX and doing an indirect call. The return value will then
21631 // be in the normal return register.
21632 MachineFunction *F = BB->getParent();
21633 const X86InstrInfo *TII = Subtarget->getInstrInfo();
21634 DebugLoc DL = MI->getDebugLoc();
21636 assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?");
21637 assert(MI->getOperand(3).isGlobal() && "This should be a global");
21639 // Get a register mask for the lowered call.
21640 // FIXME: The 32-bit calls have non-standard calling conventions. Use a
21641 // proper register mask.
21642 const uint32_t *RegMask =
21643 Subtarget->is64Bit() ?
21644 Subtarget->getRegisterInfo()->getDarwinTLSCallPreservedMask() :
21645 Subtarget->getRegisterInfo()->getCallPreservedMask(*F, CallingConv::C);
21646 if (Subtarget->is64Bit()) {
21647 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
21648 TII->get(X86::MOV64rm), X86::RDI)
21650 .addImm(0).addReg(0)
21651 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
21652 MI->getOperand(3).getTargetFlags())
21654 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m));
21655 addDirectMem(MIB, X86::RDI);
21656 MIB.addReg(X86::RAX, RegState::ImplicitDefine).addRegMask(RegMask);
21657 } else if (F->getTarget().getRelocationModel() != Reloc::PIC_) {
21658 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
21659 TII->get(X86::MOV32rm), X86::EAX)
21661 .addImm(0).addReg(0)
21662 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
21663 MI->getOperand(3).getTargetFlags())
21665 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
21666 addDirectMem(MIB, X86::EAX);
21667 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
21669 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
21670 TII->get(X86::MOV32rm), X86::EAX)
21671 .addReg(TII->getGlobalBaseReg(F))
21672 .addImm(0).addReg(0)
21673 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
21674 MI->getOperand(3).getTargetFlags())
21676 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
21677 addDirectMem(MIB, X86::EAX);
21678 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
21681 MI->eraseFromParent(); // The pseudo instruction is gone now.
21685 MachineBasicBlock *
21686 X86TargetLowering::emitEHSjLjSetJmp(MachineInstr *MI,
21687 MachineBasicBlock *MBB) const {
21688 DebugLoc DL = MI->getDebugLoc();
21689 MachineFunction *MF = MBB->getParent();
21690 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
21691 MachineRegisterInfo &MRI = MF->getRegInfo();
21693 const BasicBlock *BB = MBB->getBasicBlock();
21694 MachineFunction::iterator I = ++MBB->getIterator();
21696 // Memory Reference
21697 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
21698 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
21701 unsigned MemOpndSlot = 0;
21703 unsigned CurOp = 0;
21705 DstReg = MI->getOperand(CurOp++).getReg();
21706 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
21707 assert(RC->hasType(MVT::i32) && "Invalid destination!");
21708 unsigned mainDstReg = MRI.createVirtualRegister(RC);
21709 unsigned restoreDstReg = MRI.createVirtualRegister(RC);
21711 MemOpndSlot = CurOp;
21713 MVT PVT = getPointerTy(MF->getDataLayout());
21714 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
21715 "Invalid Pointer Size!");
21717 // For v = setjmp(buf), we generate
21720 // buf[LabelOffset] = restoreMBB <-- takes address of restoreMBB
21721 // SjLjSetup restoreMBB
21727 // v = phi(main, restore)
21730 // if base pointer being used, load it from frame
21733 MachineBasicBlock *thisMBB = MBB;
21734 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
21735 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
21736 MachineBasicBlock *restoreMBB = MF->CreateMachineBasicBlock(BB);
21737 MF->insert(I, mainMBB);
21738 MF->insert(I, sinkMBB);
21739 MF->push_back(restoreMBB);
21740 restoreMBB->setHasAddressTaken();
21742 MachineInstrBuilder MIB;
21744 // Transfer the remainder of BB and its successor edges to sinkMBB.
21745 sinkMBB->splice(sinkMBB->begin(), MBB,
21746 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
21747 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
21750 unsigned PtrStoreOpc = 0;
21751 unsigned LabelReg = 0;
21752 const int64_t LabelOffset = 1 * PVT.getStoreSize();
21753 Reloc::Model RM = MF->getTarget().getRelocationModel();
21754 bool UseImmLabel = (MF->getTarget().getCodeModel() == CodeModel::Small) &&
21755 (RM == Reloc::Static || RM == Reloc::DynamicNoPIC);
21757 // Prepare IP either in reg or imm.
21758 if (!UseImmLabel) {
21759 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mr : X86::MOV32mr;
21760 const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
21761 LabelReg = MRI.createVirtualRegister(PtrRC);
21762 if (Subtarget->is64Bit()) {
21763 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA64r), LabelReg)
21767 .addMBB(restoreMBB)
21770 const X86InstrInfo *XII = static_cast<const X86InstrInfo*>(TII);
21771 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA32r), LabelReg)
21772 .addReg(XII->getGlobalBaseReg(MF))
21775 .addMBB(restoreMBB, Subtarget->ClassifyBlockAddressReference())
21779 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mi32 : X86::MOV32mi;
21781 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PtrStoreOpc));
21782 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
21783 if (i == X86::AddrDisp)
21784 MIB.addDisp(MI->getOperand(MemOpndSlot + i), LabelOffset);
21786 MIB.addOperand(MI->getOperand(MemOpndSlot + i));
21789 MIB.addReg(LabelReg);
21791 MIB.addMBB(restoreMBB);
21792 MIB.setMemRefs(MMOBegin, MMOEnd);
21794 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::EH_SjLj_Setup))
21795 .addMBB(restoreMBB);
21797 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
21798 MIB.addRegMask(RegInfo->getNoPreservedMask());
21799 thisMBB->addSuccessor(mainMBB);
21800 thisMBB->addSuccessor(restoreMBB);
21804 BuildMI(mainMBB, DL, TII->get(X86::MOV32r0), mainDstReg);
21805 mainMBB->addSuccessor(sinkMBB);
21808 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
21809 TII->get(X86::PHI), DstReg)
21810 .addReg(mainDstReg).addMBB(mainMBB)
21811 .addReg(restoreDstReg).addMBB(restoreMBB);
21814 if (RegInfo->hasBasePointer(*MF)) {
21815 const bool Uses64BitFramePtr =
21816 Subtarget->isTarget64BitLP64() || Subtarget->isTargetNaCl64();
21817 X86MachineFunctionInfo *X86FI = MF->getInfo<X86MachineFunctionInfo>();
21818 X86FI->setRestoreBasePointer(MF);
21819 unsigned FramePtr = RegInfo->getFrameRegister(*MF);
21820 unsigned BasePtr = RegInfo->getBaseRegister();
21821 unsigned Opm = Uses64BitFramePtr ? X86::MOV64rm : X86::MOV32rm;
21822 addRegOffset(BuildMI(restoreMBB, DL, TII->get(Opm), BasePtr),
21823 FramePtr, true, X86FI->getRestoreBasePointerOffset())
21824 .setMIFlag(MachineInstr::FrameSetup);
21826 BuildMI(restoreMBB, DL, TII->get(X86::MOV32ri), restoreDstReg).addImm(1);
21827 BuildMI(restoreMBB, DL, TII->get(X86::JMP_1)).addMBB(sinkMBB);
21828 restoreMBB->addSuccessor(sinkMBB);
21830 MI->eraseFromParent();
21834 MachineBasicBlock *
21835 X86TargetLowering::emitEHSjLjLongJmp(MachineInstr *MI,
21836 MachineBasicBlock *MBB) const {
21837 DebugLoc DL = MI->getDebugLoc();
21838 MachineFunction *MF = MBB->getParent();
21839 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
21840 MachineRegisterInfo &MRI = MF->getRegInfo();
21842 // Memory Reference
21843 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
21844 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
21846 MVT PVT = getPointerTy(MF->getDataLayout());
21847 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
21848 "Invalid Pointer Size!");
21850 const TargetRegisterClass *RC =
21851 (PVT == MVT::i64) ? &X86::GR64RegClass : &X86::GR32RegClass;
21852 unsigned Tmp = MRI.createVirtualRegister(RC);
21853 // Since FP is only updated here but NOT referenced, it's treated as GPR.
21854 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
21855 unsigned FP = (PVT == MVT::i64) ? X86::RBP : X86::EBP;
21856 unsigned SP = RegInfo->getStackRegister();
21858 MachineInstrBuilder MIB;
21860 const int64_t LabelOffset = 1 * PVT.getStoreSize();
21861 const int64_t SPOffset = 2 * PVT.getStoreSize();
21863 unsigned PtrLoadOpc = (PVT == MVT::i64) ? X86::MOV64rm : X86::MOV32rm;
21864 unsigned IJmpOpc = (PVT == MVT::i64) ? X86::JMP64r : X86::JMP32r;
21867 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), FP);
21868 for (unsigned i = 0; i < X86::AddrNumOperands; ++i)
21869 MIB.addOperand(MI->getOperand(i));
21870 MIB.setMemRefs(MMOBegin, MMOEnd);
21872 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), Tmp);
21873 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
21874 if (i == X86::AddrDisp)
21875 MIB.addDisp(MI->getOperand(i), LabelOffset);
21877 MIB.addOperand(MI->getOperand(i));
21879 MIB.setMemRefs(MMOBegin, MMOEnd);
21881 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), SP);
21882 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
21883 if (i == X86::AddrDisp)
21884 MIB.addDisp(MI->getOperand(i), SPOffset);
21886 MIB.addOperand(MI->getOperand(i));
21888 MIB.setMemRefs(MMOBegin, MMOEnd);
21890 BuildMI(*MBB, MI, DL, TII->get(IJmpOpc)).addReg(Tmp);
21892 MI->eraseFromParent();
21896 // Replace 213-type (isel default) FMA3 instructions with 231-type for
21897 // accumulator loops. Writing back to the accumulator allows the coalescer
21898 // to remove extra copies in the loop.
21899 // FIXME: Do this on AVX512. We don't support 231 variants yet (PR23937).
21900 MachineBasicBlock *
21901 X86TargetLowering::emitFMA3Instr(MachineInstr *MI,
21902 MachineBasicBlock *MBB) const {
21903 MachineOperand &AddendOp = MI->getOperand(3);
21905 // Bail out early if the addend isn't a register - we can't switch these.
21906 if (!AddendOp.isReg())
21909 MachineFunction &MF = *MBB->getParent();
21910 MachineRegisterInfo &MRI = MF.getRegInfo();
21912 // Check whether the addend is defined by a PHI:
21913 assert(MRI.hasOneDef(AddendOp.getReg()) && "Multiple defs in SSA?");
21914 MachineInstr &AddendDef = *MRI.def_instr_begin(AddendOp.getReg());
21915 if (!AddendDef.isPHI())
21918 // Look for the following pattern:
21920 // %addend = phi [%entry, 0], [%loop, %result]
21922 // %result<tied1> = FMA213 %m2<tied0>, %m1, %addend
21926 // %addend = phi [%entry, 0], [%loop, %result]
21928 // %result<tied1> = FMA231 %addend<tied0>, %m1, %m2
21930 for (unsigned i = 1, e = AddendDef.getNumOperands(); i < e; i += 2) {
21931 assert(AddendDef.getOperand(i).isReg());
21932 MachineOperand PHISrcOp = AddendDef.getOperand(i);
21933 MachineInstr &PHISrcInst = *MRI.def_instr_begin(PHISrcOp.getReg());
21934 if (&PHISrcInst == MI) {
21935 // Found a matching instruction.
21936 unsigned NewFMAOpc = 0;
21937 switch (MI->getOpcode()) {
21938 case X86::VFMADDPDr213r: NewFMAOpc = X86::VFMADDPDr231r; break;
21939 case X86::VFMADDPSr213r: NewFMAOpc = X86::VFMADDPSr231r; break;
21940 case X86::VFMADDSDr213r: NewFMAOpc = X86::VFMADDSDr231r; break;
21941 case X86::VFMADDSSr213r: NewFMAOpc = X86::VFMADDSSr231r; break;
21942 case X86::VFMSUBPDr213r: NewFMAOpc = X86::VFMSUBPDr231r; break;
21943 case X86::VFMSUBPSr213r: NewFMAOpc = X86::VFMSUBPSr231r; break;
21944 case X86::VFMSUBSDr213r: NewFMAOpc = X86::VFMSUBSDr231r; break;
21945 case X86::VFMSUBSSr213r: NewFMAOpc = X86::VFMSUBSSr231r; break;
21946 case X86::VFNMADDPDr213r: NewFMAOpc = X86::VFNMADDPDr231r; break;
21947 case X86::VFNMADDPSr213r: NewFMAOpc = X86::VFNMADDPSr231r; break;
21948 case X86::VFNMADDSDr213r: NewFMAOpc = X86::VFNMADDSDr231r; break;
21949 case X86::VFNMADDSSr213r: NewFMAOpc = X86::VFNMADDSSr231r; break;
21950 case X86::VFNMSUBPDr213r: NewFMAOpc = X86::VFNMSUBPDr231r; break;
21951 case X86::VFNMSUBPSr213r: NewFMAOpc = X86::VFNMSUBPSr231r; break;
21952 case X86::VFNMSUBSDr213r: NewFMAOpc = X86::VFNMSUBSDr231r; break;
21953 case X86::VFNMSUBSSr213r: NewFMAOpc = X86::VFNMSUBSSr231r; break;
21954 case X86::VFMADDSUBPDr213r: NewFMAOpc = X86::VFMADDSUBPDr231r; break;
21955 case X86::VFMADDSUBPSr213r: NewFMAOpc = X86::VFMADDSUBPSr231r; break;
21956 case X86::VFMSUBADDPDr213r: NewFMAOpc = X86::VFMSUBADDPDr231r; break;
21957 case X86::VFMSUBADDPSr213r: NewFMAOpc = X86::VFMSUBADDPSr231r; break;
21959 case X86::VFMADDPDr213rY: NewFMAOpc = X86::VFMADDPDr231rY; break;
21960 case X86::VFMADDPSr213rY: NewFMAOpc = X86::VFMADDPSr231rY; break;
21961 case X86::VFMSUBPDr213rY: NewFMAOpc = X86::VFMSUBPDr231rY; break;
21962 case X86::VFMSUBPSr213rY: NewFMAOpc = X86::VFMSUBPSr231rY; break;
21963 case X86::VFNMADDPDr213rY: NewFMAOpc = X86::VFNMADDPDr231rY; break;
21964 case X86::VFNMADDPSr213rY: NewFMAOpc = X86::VFNMADDPSr231rY; break;
21965 case X86::VFNMSUBPDr213rY: NewFMAOpc = X86::VFNMSUBPDr231rY; break;
21966 case X86::VFNMSUBPSr213rY: NewFMAOpc = X86::VFNMSUBPSr231rY; break;
21967 case X86::VFMADDSUBPDr213rY: NewFMAOpc = X86::VFMADDSUBPDr231rY; break;
21968 case X86::VFMADDSUBPSr213rY: NewFMAOpc = X86::VFMADDSUBPSr231rY; break;
21969 case X86::VFMSUBADDPDr213rY: NewFMAOpc = X86::VFMSUBADDPDr231rY; break;
21970 case X86::VFMSUBADDPSr213rY: NewFMAOpc = X86::VFMSUBADDPSr231rY; break;
21971 default: llvm_unreachable("Unrecognized FMA variant.");
21974 const TargetInstrInfo &TII = *Subtarget->getInstrInfo();
21975 MachineInstrBuilder MIB =
21976 BuildMI(MF, MI->getDebugLoc(), TII.get(NewFMAOpc))
21977 .addOperand(MI->getOperand(0))
21978 .addOperand(MI->getOperand(3))
21979 .addOperand(MI->getOperand(2))
21980 .addOperand(MI->getOperand(1));
21981 MBB->insert(MachineBasicBlock::iterator(MI), MIB);
21982 MI->eraseFromParent();
21989 MachineBasicBlock *
21990 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
21991 MachineBasicBlock *BB) const {
21992 switch (MI->getOpcode()) {
21993 default: llvm_unreachable("Unexpected instr type to insert");
21994 case X86::TAILJMPd64:
21995 case X86::TAILJMPr64:
21996 case X86::TAILJMPm64:
21997 case X86::TAILJMPd64_REX:
21998 case X86::TAILJMPr64_REX:
21999 case X86::TAILJMPm64_REX:
22000 llvm_unreachable("TAILJMP64 would not be touched here.");
22001 case X86::TCRETURNdi64:
22002 case X86::TCRETURNri64:
22003 case X86::TCRETURNmi64:
22005 case X86::WIN_ALLOCA:
22006 return EmitLoweredWinAlloca(MI, BB);
22007 case X86::CATCHRET:
22008 return EmitLoweredCatchRet(MI, BB);
22009 case X86::CATCHPAD:
22010 return EmitLoweredCatchPad(MI, BB);
22011 case X86::SEG_ALLOCA_32:
22012 case X86::SEG_ALLOCA_64:
22013 return EmitLoweredSegAlloca(MI, BB);
22014 case X86::TLSCall_32:
22015 case X86::TLSCall_64:
22016 return EmitLoweredTLSCall(MI, BB);
22017 case X86::CMOV_FR32:
22018 case X86::CMOV_FR64:
22019 case X86::CMOV_GR8:
22020 case X86::CMOV_GR16:
22021 case X86::CMOV_GR32:
22022 case X86::CMOV_RFP32:
22023 case X86::CMOV_RFP64:
22024 case X86::CMOV_RFP80:
22025 case X86::CMOV_V2F64:
22026 case X86::CMOV_V2I64:
22027 case X86::CMOV_V4F32:
22028 case X86::CMOV_V4F64:
22029 case X86::CMOV_V4I64:
22030 case X86::CMOV_V16F32:
22031 case X86::CMOV_V8F32:
22032 case X86::CMOV_V8F64:
22033 case X86::CMOV_V8I64:
22034 case X86::CMOV_V8I1:
22035 case X86::CMOV_V16I1:
22036 case X86::CMOV_V32I1:
22037 case X86::CMOV_V64I1:
22038 return EmitLoweredSelect(MI, BB);
22040 case X86::RELEASE_FADD32mr:
22041 case X86::RELEASE_FADD64mr:
22042 return EmitLoweredAtomicFP(MI, BB);
22044 case X86::FP32_TO_INT16_IN_MEM:
22045 case X86::FP32_TO_INT32_IN_MEM:
22046 case X86::FP32_TO_INT64_IN_MEM:
22047 case X86::FP64_TO_INT16_IN_MEM:
22048 case X86::FP64_TO_INT32_IN_MEM:
22049 case X86::FP64_TO_INT64_IN_MEM:
22050 case X86::FP80_TO_INT16_IN_MEM:
22051 case X86::FP80_TO_INT32_IN_MEM:
22052 case X86::FP80_TO_INT64_IN_MEM: {
22053 MachineFunction *F = BB->getParent();
22054 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
22055 DebugLoc DL = MI->getDebugLoc();
22057 // Change the floating point control register to use "round towards zero"
22058 // mode when truncating to an integer value.
22059 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false);
22060 addFrameReference(BuildMI(*BB, MI, DL,
22061 TII->get(X86::FNSTCW16m)), CWFrameIdx);
22063 // Load the old value of the high byte of the control word...
22065 F->getRegInfo().createVirtualRegister(&X86::GR16RegClass);
22066 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW),
22069 // Set the high part to be round to zero...
22070 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
22073 // Reload the modified control word now...
22074 addFrameReference(BuildMI(*BB, MI, DL,
22075 TII->get(X86::FLDCW16m)), CWFrameIdx);
22077 // Restore the memory image of control word to original value
22078 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
22081 // Get the X86 opcode to use.
22083 switch (MI->getOpcode()) {
22084 default: llvm_unreachable("illegal opcode!");
22085 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
22086 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
22087 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
22088 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
22089 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
22090 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
22091 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
22092 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
22093 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
22097 MachineOperand &Op = MI->getOperand(0);
22099 AM.BaseType = X86AddressMode::RegBase;
22100 AM.Base.Reg = Op.getReg();
22102 AM.BaseType = X86AddressMode::FrameIndexBase;
22103 AM.Base.FrameIndex = Op.getIndex();
22105 Op = MI->getOperand(1);
22107 AM.Scale = Op.getImm();
22108 Op = MI->getOperand(2);
22110 AM.IndexReg = Op.getImm();
22111 Op = MI->getOperand(3);
22112 if (Op.isGlobal()) {
22113 AM.GV = Op.getGlobal();
22115 AM.Disp = Op.getImm();
22117 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM)
22118 .addReg(MI->getOperand(X86::AddrNumOperands).getReg());
22120 // Reload the original control word now.
22121 addFrameReference(BuildMI(*BB, MI, DL,
22122 TII->get(X86::FLDCW16m)), CWFrameIdx);
22124 MI->eraseFromParent(); // The pseudo instruction is gone now.
22127 // String/text processing lowering.
22128 case X86::PCMPISTRM128REG:
22129 case X86::VPCMPISTRM128REG:
22130 case X86::PCMPISTRM128MEM:
22131 case X86::VPCMPISTRM128MEM:
22132 case X86::PCMPESTRM128REG:
22133 case X86::VPCMPESTRM128REG:
22134 case X86::PCMPESTRM128MEM:
22135 case X86::VPCMPESTRM128MEM:
22136 assert(Subtarget->hasSSE42() &&
22137 "Target must have SSE4.2 or AVX features enabled");
22138 return EmitPCMPSTRM(MI, BB, Subtarget->getInstrInfo());
22140 // String/text processing lowering.
22141 case X86::PCMPISTRIREG:
22142 case X86::VPCMPISTRIREG:
22143 case X86::PCMPISTRIMEM:
22144 case X86::VPCMPISTRIMEM:
22145 case X86::PCMPESTRIREG:
22146 case X86::VPCMPESTRIREG:
22147 case X86::PCMPESTRIMEM:
22148 case X86::VPCMPESTRIMEM:
22149 assert(Subtarget->hasSSE42() &&
22150 "Target must have SSE4.2 or AVX features enabled");
22151 return EmitPCMPSTRI(MI, BB, Subtarget->getInstrInfo());
22153 // Thread synchronization.
22155 return EmitMonitor(MI, BB, Subtarget);
22159 return EmitXBegin(MI, BB, Subtarget->getInstrInfo());
22161 case X86::VASTART_SAVE_XMM_REGS:
22162 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
22164 case X86::VAARG_64:
22165 return EmitVAARG64WithCustomInserter(MI, BB);
22167 case X86::EH_SjLj_SetJmp32:
22168 case X86::EH_SjLj_SetJmp64:
22169 return emitEHSjLjSetJmp(MI, BB);
22171 case X86::EH_SjLj_LongJmp32:
22172 case X86::EH_SjLj_LongJmp64:
22173 return emitEHSjLjLongJmp(MI, BB);
22175 case TargetOpcode::STATEPOINT:
22176 // As an implementation detail, STATEPOINT shares the STACKMAP format at
22177 // this point in the process. We diverge later.
22178 return emitPatchPoint(MI, BB);
22180 case TargetOpcode::STACKMAP:
22181 case TargetOpcode::PATCHPOINT:
22182 return emitPatchPoint(MI, BB);
22184 case X86::VFMADDPDr213r:
22185 case X86::VFMADDPSr213r:
22186 case X86::VFMADDSDr213r:
22187 case X86::VFMADDSSr213r:
22188 case X86::VFMSUBPDr213r:
22189 case X86::VFMSUBPSr213r:
22190 case X86::VFMSUBSDr213r:
22191 case X86::VFMSUBSSr213r:
22192 case X86::VFNMADDPDr213r:
22193 case X86::VFNMADDPSr213r:
22194 case X86::VFNMADDSDr213r:
22195 case X86::VFNMADDSSr213r:
22196 case X86::VFNMSUBPDr213r:
22197 case X86::VFNMSUBPSr213r:
22198 case X86::VFNMSUBSDr213r:
22199 case X86::VFNMSUBSSr213r:
22200 case X86::VFMADDSUBPDr213r:
22201 case X86::VFMADDSUBPSr213r:
22202 case X86::VFMSUBADDPDr213r:
22203 case X86::VFMSUBADDPSr213r:
22204 case X86::VFMADDPDr213rY:
22205 case X86::VFMADDPSr213rY:
22206 case X86::VFMSUBPDr213rY:
22207 case X86::VFMSUBPSr213rY:
22208 case X86::VFNMADDPDr213rY:
22209 case X86::VFNMADDPSr213rY:
22210 case X86::VFNMSUBPDr213rY:
22211 case X86::VFNMSUBPSr213rY:
22212 case X86::VFMADDSUBPDr213rY:
22213 case X86::VFMADDSUBPSr213rY:
22214 case X86::VFMSUBADDPDr213rY:
22215 case X86::VFMSUBADDPSr213rY:
22216 return emitFMA3Instr(MI, BB);
22220 //===----------------------------------------------------------------------===//
22221 // X86 Optimization Hooks
22222 //===----------------------------------------------------------------------===//
22224 void X86TargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
22227 const SelectionDAG &DAG,
22228 unsigned Depth) const {
22229 unsigned BitWidth = KnownZero.getBitWidth();
22230 unsigned Opc = Op.getOpcode();
22231 assert((Opc >= ISD::BUILTIN_OP_END ||
22232 Opc == ISD::INTRINSIC_WO_CHAIN ||
22233 Opc == ISD::INTRINSIC_W_CHAIN ||
22234 Opc == ISD::INTRINSIC_VOID) &&
22235 "Should use MaskedValueIsZero if you don't know whether Op"
22236 " is a target node!");
22238 KnownZero = KnownOne = APInt(BitWidth, 0); // Don't know anything.
22252 // These nodes' second result is a boolean.
22253 if (Op.getResNo() == 0)
22256 case X86ISD::SETCC:
22257 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1);
22259 case ISD::INTRINSIC_WO_CHAIN: {
22260 unsigned IntId = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
22261 unsigned NumLoBits = 0;
22264 case Intrinsic::x86_sse_movmsk_ps:
22265 case Intrinsic::x86_avx_movmsk_ps_256:
22266 case Intrinsic::x86_sse2_movmsk_pd:
22267 case Intrinsic::x86_avx_movmsk_pd_256:
22268 case Intrinsic::x86_mmx_pmovmskb:
22269 case Intrinsic::x86_sse2_pmovmskb_128:
22270 case Intrinsic::x86_avx2_pmovmskb: {
22271 // High bits of movmskp{s|d}, pmovmskb are known zero.
22273 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
22274 case Intrinsic::x86_sse_movmsk_ps: NumLoBits = 4; break;
22275 case Intrinsic::x86_avx_movmsk_ps_256: NumLoBits = 8; break;
22276 case Intrinsic::x86_sse2_movmsk_pd: NumLoBits = 2; break;
22277 case Intrinsic::x86_avx_movmsk_pd_256: NumLoBits = 4; break;
22278 case Intrinsic::x86_mmx_pmovmskb: NumLoBits = 8; break;
22279 case Intrinsic::x86_sse2_pmovmskb_128: NumLoBits = 16; break;
22280 case Intrinsic::x86_avx2_pmovmskb: NumLoBits = 32; break;
22282 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - NumLoBits);
22291 unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(
22293 const SelectionDAG &,
22294 unsigned Depth) const {
22295 // SETCC_CARRY sets the dest to ~0 for true or 0 for false.
22296 if (Op.getOpcode() == X86ISD::SETCC_CARRY)
22297 return Op.getValueType().getScalarSizeInBits();
22303 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
22304 /// node is a GlobalAddress + offset.
22305 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
22306 const GlobalValue* &GA,
22307 int64_t &Offset) const {
22308 if (N->getOpcode() == X86ISD::Wrapper) {
22309 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
22310 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
22311 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
22315 return TargetLowering::isGAPlusOffset(N, GA, Offset);
22318 /// isShuffleHigh128VectorInsertLow - Checks whether the shuffle node is the
22319 /// same as extracting the high 128-bit part of 256-bit vector and then
22320 /// inserting the result into the low part of a new 256-bit vector
22321 static bool isShuffleHigh128VectorInsertLow(ShuffleVectorSDNode *SVOp) {
22322 EVT VT = SVOp->getValueType(0);
22323 unsigned NumElems = VT.getVectorNumElements();
22325 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
22326 for (unsigned i = 0, j = NumElems/2; i != NumElems/2; ++i, ++j)
22327 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
22328 SVOp->getMaskElt(j) >= 0)
22334 /// isShuffleLow128VectorInsertHigh - Checks whether the shuffle node is the
22335 /// same as extracting the low 128-bit part of 256-bit vector and then
22336 /// inserting the result into the high part of a new 256-bit vector
22337 static bool isShuffleLow128VectorInsertHigh(ShuffleVectorSDNode *SVOp) {
22338 EVT VT = SVOp->getValueType(0);
22339 unsigned NumElems = VT.getVectorNumElements();
22341 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
22342 for (unsigned i = NumElems/2, j = 0; i != NumElems; ++i, ++j)
22343 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
22344 SVOp->getMaskElt(j) >= 0)
22350 /// PerformShuffleCombine256 - Performs shuffle combines for 256-bit vectors.
22351 static SDValue PerformShuffleCombine256(SDNode *N, SelectionDAG &DAG,
22352 TargetLowering::DAGCombinerInfo &DCI,
22353 const X86Subtarget* Subtarget) {
22355 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
22356 SDValue V1 = SVOp->getOperand(0);
22357 SDValue V2 = SVOp->getOperand(1);
22358 MVT VT = SVOp->getSimpleValueType(0);
22359 unsigned NumElems = VT.getVectorNumElements();
22361 if (V1.getOpcode() == ISD::CONCAT_VECTORS &&
22362 V2.getOpcode() == ISD::CONCAT_VECTORS) {
22366 // V UNDEF BUILD_VECTOR UNDEF
22368 // CONCAT_VECTOR CONCAT_VECTOR
22371 // RESULT: V + zero extended
22373 if (V2.getOperand(0).getOpcode() != ISD::BUILD_VECTOR ||
22374 V2.getOperand(1).getOpcode() != ISD::UNDEF ||
22375 V1.getOperand(1).getOpcode() != ISD::UNDEF)
22378 if (!ISD::isBuildVectorAllZeros(V2.getOperand(0).getNode()))
22381 // To match the shuffle mask, the first half of the mask should
22382 // be exactly the first vector, and all the rest a splat with the
22383 // first element of the second one.
22384 for (unsigned i = 0; i != NumElems/2; ++i)
22385 if (!isUndefOrEqual(SVOp->getMaskElt(i), i) ||
22386 !isUndefOrEqual(SVOp->getMaskElt(i+NumElems/2), NumElems))
22389 // If V1 is coming from a vector load then just fold to a VZEXT_LOAD.
22390 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(V1.getOperand(0))) {
22391 if (Ld->hasNUsesOfValue(1, 0)) {
22392 SDVTList Tys = DAG.getVTList(MVT::v4i64, MVT::Other);
22393 SDValue Ops[] = { Ld->getChain(), Ld->getBasePtr() };
22395 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops,
22397 Ld->getPointerInfo(),
22398 Ld->getAlignment(),
22399 false/*isVolatile*/, true/*ReadMem*/,
22400 false/*WriteMem*/);
22402 // Make sure the newly-created LOAD is in the same position as Ld in
22403 // terms of dependency. We create a TokenFactor for Ld and ResNode,
22404 // and update uses of Ld's output chain to use the TokenFactor.
22405 if (Ld->hasAnyUseOfValue(1)) {
22406 SDValue NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
22407 SDValue(Ld, 1), SDValue(ResNode.getNode(), 1));
22408 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), NewChain);
22409 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(Ld, 1),
22410 SDValue(ResNode.getNode(), 1));
22413 return DAG.getBitcast(VT, ResNode);
22417 // Emit a zeroed vector and insert the desired subvector on its
22419 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
22420 SDValue InsV = Insert128BitVector(Zeros, V1.getOperand(0), 0, DAG, dl);
22421 return DCI.CombineTo(N, InsV);
22424 //===--------------------------------------------------------------------===//
22425 // Combine some shuffles into subvector extracts and inserts:
22428 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
22429 if (isShuffleHigh128VectorInsertLow(SVOp)) {
22430 SDValue V = Extract128BitVector(V1, NumElems/2, DAG, dl);
22431 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, 0, DAG, dl);
22432 return DCI.CombineTo(N, InsV);
22435 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
22436 if (isShuffleLow128VectorInsertHigh(SVOp)) {
22437 SDValue V = Extract128BitVector(V1, 0, DAG, dl);
22438 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, NumElems/2, DAG, dl);
22439 return DCI.CombineTo(N, InsV);
22445 /// \brief Combine an arbitrary chain of shuffles into a single instruction if
22448 /// This is the leaf of the recursive combinine below. When we have found some
22449 /// chain of single-use x86 shuffle instructions and accumulated the combined
22450 /// shuffle mask represented by them, this will try to pattern match that mask
22451 /// into either a single instruction if there is a special purpose instruction
22452 /// for this operation, or into a PSHUFB instruction which is a fully general
22453 /// instruction but should only be used to replace chains over a certain depth.
22454 static bool combineX86ShuffleChain(SDValue Op, SDValue Root, ArrayRef<int> Mask,
22455 int Depth, bool HasPSHUFB, SelectionDAG &DAG,
22456 TargetLowering::DAGCombinerInfo &DCI,
22457 const X86Subtarget *Subtarget) {
22458 assert(!Mask.empty() && "Cannot combine an empty shuffle mask!");
22460 // Find the operand that enters the chain. Note that multiple uses are OK
22461 // here, we're not going to remove the operand we find.
22462 SDValue Input = Op.getOperand(0);
22463 while (Input.getOpcode() == ISD::BITCAST)
22464 Input = Input.getOperand(0);
22466 MVT VT = Input.getSimpleValueType();
22467 MVT RootVT = Root.getSimpleValueType();
22470 if (Mask.size() == 1) {
22471 int Index = Mask[0];
22472 assert((Index >= 0 || Index == SM_SentinelUndef ||
22473 Index == SM_SentinelZero) &&
22474 "Invalid shuffle index found!");
22476 // We may end up with an accumulated mask of size 1 as a result of
22477 // widening of shuffle operands (see function canWidenShuffleElements).
22478 // If the only shuffle index is equal to SM_SentinelZero then propagate
22479 // a zero vector. Otherwise, the combine shuffle mask is a no-op shuffle
22480 // mask, and therefore the entire chain of shuffles can be folded away.
22481 if (Index == SM_SentinelZero)
22482 DCI.CombineTo(Root.getNode(), getZeroVector(RootVT, Subtarget, DAG, DL));
22484 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Input),
22489 // Use the float domain if the operand type is a floating point type.
22490 bool FloatDomain = VT.isFloatingPoint();
22492 // For floating point shuffles, we don't have free copies in the shuffle
22493 // instructions or the ability to load as part of the instruction, so
22494 // canonicalize their shuffles to UNPCK or MOV variants.
22496 // Note that even with AVX we prefer the PSHUFD form of shuffle for integer
22497 // vectors because it can have a load folded into it that UNPCK cannot. This
22498 // doesn't preclude something switching to the shorter encoding post-RA.
22500 // FIXME: Should teach these routines about AVX vector widths.
22501 if (FloatDomain && VT.is128BitVector()) {
22502 if (Mask.equals({0, 0}) || Mask.equals({1, 1})) {
22503 bool Lo = Mask.equals({0, 0});
22506 // Check if we have SSE3 which will let us use MOVDDUP. That instruction
22507 // is no slower than UNPCKLPD but has the option to fold the input operand
22508 // into even an unaligned memory load.
22509 if (Lo && Subtarget->hasSSE3()) {
22510 Shuffle = X86ISD::MOVDDUP;
22511 ShuffleVT = MVT::v2f64;
22513 // We have MOVLHPS and MOVHLPS throughout SSE and they encode smaller
22514 // than the UNPCK variants.
22515 Shuffle = Lo ? X86ISD::MOVLHPS : X86ISD::MOVHLPS;
22516 ShuffleVT = MVT::v4f32;
22518 if (Depth == 1 && Root->getOpcode() == Shuffle)
22519 return false; // Nothing to do!
22520 Op = DAG.getBitcast(ShuffleVT, Input);
22521 DCI.AddToWorklist(Op.getNode());
22522 if (Shuffle == X86ISD::MOVDDUP)
22523 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op);
22525 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
22526 DCI.AddToWorklist(Op.getNode());
22527 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Op),
22531 if (Subtarget->hasSSE3() &&
22532 (Mask.equals({0, 0, 2, 2}) || Mask.equals({1, 1, 3, 3}))) {
22533 bool Lo = Mask.equals({0, 0, 2, 2});
22534 unsigned Shuffle = Lo ? X86ISD::MOVSLDUP : X86ISD::MOVSHDUP;
22535 MVT ShuffleVT = MVT::v4f32;
22536 if (Depth == 1 && Root->getOpcode() == Shuffle)
22537 return false; // Nothing to do!
22538 Op = DAG.getBitcast(ShuffleVT, Input);
22539 DCI.AddToWorklist(Op.getNode());
22540 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op);
22541 DCI.AddToWorklist(Op.getNode());
22542 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Op),
22546 if (Mask.equals({0, 0, 1, 1}) || Mask.equals({2, 2, 3, 3})) {
22547 bool Lo = Mask.equals({0, 0, 1, 1});
22548 unsigned Shuffle = Lo ? X86ISD::UNPCKL : X86ISD::UNPCKH;
22549 MVT ShuffleVT = MVT::v4f32;
22550 if (Depth == 1 && Root->getOpcode() == Shuffle)
22551 return false; // Nothing to do!
22552 Op = DAG.getBitcast(ShuffleVT, Input);
22553 DCI.AddToWorklist(Op.getNode());
22554 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
22555 DCI.AddToWorklist(Op.getNode());
22556 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Op),
22562 // We always canonicalize the 8 x i16 and 16 x i8 shuffles into their UNPCK
22563 // variants as none of these have single-instruction variants that are
22564 // superior to the UNPCK formulation.
22565 if (!FloatDomain && VT.is128BitVector() &&
22566 (Mask.equals({0, 0, 1, 1, 2, 2, 3, 3}) ||
22567 Mask.equals({4, 4, 5, 5, 6, 6, 7, 7}) ||
22568 Mask.equals({0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7}) ||
22570 {8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}))) {
22571 bool Lo = Mask[0] == 0;
22572 unsigned Shuffle = Lo ? X86ISD::UNPCKL : X86ISD::UNPCKH;
22573 if (Depth == 1 && Root->getOpcode() == Shuffle)
22574 return false; // Nothing to do!
22576 switch (Mask.size()) {
22578 ShuffleVT = MVT::v8i16;
22581 ShuffleVT = MVT::v16i8;
22584 llvm_unreachable("Impossible mask size!");
22586 Op = DAG.getBitcast(ShuffleVT, Input);
22587 DCI.AddToWorklist(Op.getNode());
22588 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
22589 DCI.AddToWorklist(Op.getNode());
22590 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Op),
22595 // Don't try to re-form single instruction chains under any circumstances now
22596 // that we've done encoding canonicalization for them.
22600 // If we have 3 or more shuffle instructions or a chain involving PSHUFB, we
22601 // can replace them with a single PSHUFB instruction profitably. Intel's
22602 // manuals suggest only using PSHUFB if doing so replacing 5 instructions, but
22603 // in practice PSHUFB tends to be *very* fast so we're more aggressive.
22604 if ((Depth >= 3 || HasPSHUFB) && Subtarget->hasSSSE3()) {
22605 SmallVector<SDValue, 16> PSHUFBMask;
22606 int NumBytes = VT.getSizeInBits() / 8;
22607 int Ratio = NumBytes / Mask.size();
22608 for (int i = 0; i < NumBytes; ++i) {
22609 if (Mask[i / Ratio] == SM_SentinelUndef) {
22610 PSHUFBMask.push_back(DAG.getUNDEF(MVT::i8));
22613 int M = Mask[i / Ratio] != SM_SentinelZero
22614 ? Ratio * Mask[i / Ratio] + i % Ratio
22616 PSHUFBMask.push_back(DAG.getConstant(M, DL, MVT::i8));
22618 MVT ByteVT = MVT::getVectorVT(MVT::i8, NumBytes);
22619 Op = DAG.getBitcast(ByteVT, Input);
22620 DCI.AddToWorklist(Op.getNode());
22621 SDValue PSHUFBMaskOp =
22622 DAG.getNode(ISD::BUILD_VECTOR, DL, ByteVT, PSHUFBMask);
22623 DCI.AddToWorklist(PSHUFBMaskOp.getNode());
22624 Op = DAG.getNode(X86ISD::PSHUFB, DL, ByteVT, Op, PSHUFBMaskOp);
22625 DCI.AddToWorklist(Op.getNode());
22626 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Op),
22631 // Failed to find any combines.
22635 /// \brief Fully generic combining of x86 shuffle instructions.
22637 /// This should be the last combine run over the x86 shuffle instructions. Once
22638 /// they have been fully optimized, this will recursively consider all chains
22639 /// of single-use shuffle instructions, build a generic model of the cumulative
22640 /// shuffle operation, and check for simpler instructions which implement this
22641 /// operation. We use this primarily for two purposes:
22643 /// 1) Collapse generic shuffles to specialized single instructions when
22644 /// equivalent. In most cases, this is just an encoding size win, but
22645 /// sometimes we will collapse multiple generic shuffles into a single
22646 /// special-purpose shuffle.
22647 /// 2) Look for sequences of shuffle instructions with 3 or more total
22648 /// instructions, and replace them with the slightly more expensive SSSE3
22649 /// PSHUFB instruction if available. We do this as the last combining step
22650 /// to ensure we avoid using PSHUFB if we can implement the shuffle with
22651 /// a suitable short sequence of other instructions. The PHUFB will either
22652 /// use a register or have to read from memory and so is slightly (but only
22653 /// slightly) more expensive than the other shuffle instructions.
22655 /// Because this is inherently a quadratic operation (for each shuffle in
22656 /// a chain, we recurse up the chain), the depth is limited to 8 instructions.
22657 /// This should never be an issue in practice as the shuffle lowering doesn't
22658 /// produce sequences of more than 8 instructions.
22660 /// FIXME: We will currently miss some cases where the redundant shuffling
22661 /// would simplify under the threshold for PSHUFB formation because of
22662 /// combine-ordering. To fix this, we should do the redundant instruction
22663 /// combining in this recursive walk.
22664 static bool combineX86ShufflesRecursively(SDValue Op, SDValue Root,
22665 ArrayRef<int> RootMask,
22666 int Depth, bool HasPSHUFB,
22668 TargetLowering::DAGCombinerInfo &DCI,
22669 const X86Subtarget *Subtarget) {
22670 // Bound the depth of our recursive combine because this is ultimately
22671 // quadratic in nature.
22675 // Directly rip through bitcasts to find the underlying operand.
22676 while (Op.getOpcode() == ISD::BITCAST && Op.getOperand(0).hasOneUse())
22677 Op = Op.getOperand(0);
22679 MVT VT = Op.getSimpleValueType();
22680 if (!VT.isVector())
22681 return false; // Bail if we hit a non-vector.
22683 assert(Root.getSimpleValueType().isVector() &&
22684 "Shuffles operate on vector types!");
22685 assert(VT.getSizeInBits() == Root.getSimpleValueType().getSizeInBits() &&
22686 "Can only combine shuffles of the same vector register size.");
22688 if (!isTargetShuffle(Op.getOpcode()))
22690 SmallVector<int, 16> OpMask;
22692 bool HaveMask = getTargetShuffleMask(Op.getNode(), VT, OpMask, IsUnary);
22693 // We only can combine unary shuffles which we can decode the mask for.
22694 if (!HaveMask || !IsUnary)
22697 assert(VT.getVectorNumElements() == OpMask.size() &&
22698 "Different mask size from vector size!");
22699 assert(((RootMask.size() > OpMask.size() &&
22700 RootMask.size() % OpMask.size() == 0) ||
22701 (OpMask.size() > RootMask.size() &&
22702 OpMask.size() % RootMask.size() == 0) ||
22703 OpMask.size() == RootMask.size()) &&
22704 "The smaller number of elements must divide the larger.");
22705 int RootRatio = std::max<int>(1, OpMask.size() / RootMask.size());
22706 int OpRatio = std::max<int>(1, RootMask.size() / OpMask.size());
22707 assert(((RootRatio == 1 && OpRatio == 1) ||
22708 (RootRatio == 1) != (OpRatio == 1)) &&
22709 "Must not have a ratio for both incoming and op masks!");
22711 SmallVector<int, 16> Mask;
22712 Mask.reserve(std::max(OpMask.size(), RootMask.size()));
22714 // Merge this shuffle operation's mask into our accumulated mask. Note that
22715 // this shuffle's mask will be the first applied to the input, followed by the
22716 // root mask to get us all the way to the root value arrangement. The reason
22717 // for this order is that we are recursing up the operation chain.
22718 for (int i = 0, e = std::max(OpMask.size(), RootMask.size()); i < e; ++i) {
22719 int RootIdx = i / RootRatio;
22720 if (RootMask[RootIdx] < 0) {
22721 // This is a zero or undef lane, we're done.
22722 Mask.push_back(RootMask[RootIdx]);
22726 int RootMaskedIdx = RootMask[RootIdx] * RootRatio + i % RootRatio;
22727 int OpIdx = RootMaskedIdx / OpRatio;
22728 if (OpMask[OpIdx] < 0) {
22729 // The incoming lanes are zero or undef, it doesn't matter which ones we
22731 Mask.push_back(OpMask[OpIdx]);
22735 // Ok, we have non-zero lanes, map them through.
22736 Mask.push_back(OpMask[OpIdx] * OpRatio +
22737 RootMaskedIdx % OpRatio);
22740 // See if we can recurse into the operand to combine more things.
22741 switch (Op.getOpcode()) {
22742 case X86ISD::PSHUFB:
22744 case X86ISD::PSHUFD:
22745 case X86ISD::PSHUFHW:
22746 case X86ISD::PSHUFLW:
22747 if (Op.getOperand(0).hasOneUse() &&
22748 combineX86ShufflesRecursively(Op.getOperand(0), Root, Mask, Depth + 1,
22749 HasPSHUFB, DAG, DCI, Subtarget))
22753 case X86ISD::UNPCKL:
22754 case X86ISD::UNPCKH:
22755 assert(Op.getOperand(0) == Op.getOperand(1) &&
22756 "We only combine unary shuffles!");
22757 // We can't check for single use, we have to check that this shuffle is the
22759 if (Op->isOnlyUserOf(Op.getOperand(0).getNode()) &&
22760 combineX86ShufflesRecursively(Op.getOperand(0), Root, Mask, Depth + 1,
22761 HasPSHUFB, DAG, DCI, Subtarget))
22766 // Minor canonicalization of the accumulated shuffle mask to make it easier
22767 // to match below. All this does is detect masks with squential pairs of
22768 // elements, and shrink them to the half-width mask. It does this in a loop
22769 // so it will reduce the size of the mask to the minimal width mask which
22770 // performs an equivalent shuffle.
22771 SmallVector<int, 16> WidenedMask;
22772 while (Mask.size() > 1 && canWidenShuffleElements(Mask, WidenedMask)) {
22773 Mask = std::move(WidenedMask);
22774 WidenedMask.clear();
22777 return combineX86ShuffleChain(Op, Root, Mask, Depth, HasPSHUFB, DAG, DCI,
22781 /// \brief Get the PSHUF-style mask from PSHUF node.
22783 /// This is a very minor wrapper around getTargetShuffleMask to easy forming v4
22784 /// PSHUF-style masks that can be reused with such instructions.
22785 static SmallVector<int, 4> getPSHUFShuffleMask(SDValue N) {
22786 MVT VT = N.getSimpleValueType();
22787 SmallVector<int, 4> Mask;
22789 bool HaveMask = getTargetShuffleMask(N.getNode(), VT, Mask, IsUnary);
22793 // If we have more than 128-bits, only the low 128-bits of shuffle mask
22794 // matter. Check that the upper masks are repeats and remove them.
22795 if (VT.getSizeInBits() > 128) {
22796 int LaneElts = 128 / VT.getScalarSizeInBits();
22798 for (int i = 1, NumLanes = VT.getSizeInBits() / 128; i < NumLanes; ++i)
22799 for (int j = 0; j < LaneElts; ++j)
22800 assert(Mask[j] == Mask[i * LaneElts + j] - (LaneElts * i) &&
22801 "Mask doesn't repeat in high 128-bit lanes!");
22803 Mask.resize(LaneElts);
22806 switch (N.getOpcode()) {
22807 case X86ISD::PSHUFD:
22809 case X86ISD::PSHUFLW:
22812 case X86ISD::PSHUFHW:
22813 Mask.erase(Mask.begin(), Mask.begin() + 4);
22814 for (int &M : Mask)
22818 llvm_unreachable("No valid shuffle instruction found!");
22822 /// \brief Search for a combinable shuffle across a chain ending in pshufd.
22824 /// We walk up the chain and look for a combinable shuffle, skipping over
22825 /// shuffles that we could hoist this shuffle's transformation past without
22826 /// altering anything.
22828 combineRedundantDWordShuffle(SDValue N, MutableArrayRef<int> Mask,
22830 TargetLowering::DAGCombinerInfo &DCI) {
22831 assert(N.getOpcode() == X86ISD::PSHUFD &&
22832 "Called with something other than an x86 128-bit half shuffle!");
22835 // Walk up a single-use chain looking for a combinable shuffle. Keep a stack
22836 // of the shuffles in the chain so that we can form a fresh chain to replace
22838 SmallVector<SDValue, 8> Chain;
22839 SDValue V = N.getOperand(0);
22840 for (; V.hasOneUse(); V = V.getOperand(0)) {
22841 switch (V.getOpcode()) {
22843 return SDValue(); // Nothing combined!
22846 // Skip bitcasts as we always know the type for the target specific
22850 case X86ISD::PSHUFD:
22851 // Found another dword shuffle.
22854 case X86ISD::PSHUFLW:
22855 // Check that the low words (being shuffled) are the identity in the
22856 // dword shuffle, and the high words are self-contained.
22857 if (Mask[0] != 0 || Mask[1] != 1 ||
22858 !(Mask[2] >= 2 && Mask[2] < 4 && Mask[3] >= 2 && Mask[3] < 4))
22861 Chain.push_back(V);
22864 case X86ISD::PSHUFHW:
22865 // Check that the high words (being shuffled) are the identity in the
22866 // dword shuffle, and the low words are self-contained.
22867 if (Mask[2] != 2 || Mask[3] != 3 ||
22868 !(Mask[0] >= 0 && Mask[0] < 2 && Mask[1] >= 0 && Mask[1] < 2))
22871 Chain.push_back(V);
22874 case X86ISD::UNPCKL:
22875 case X86ISD::UNPCKH:
22876 // For either i8 -> i16 or i16 -> i32 unpacks, we can combine a dword
22877 // shuffle into a preceding word shuffle.
22878 if (V.getSimpleValueType().getVectorElementType() != MVT::i8 &&
22879 V.getSimpleValueType().getVectorElementType() != MVT::i16)
22882 // Search for a half-shuffle which we can combine with.
22883 unsigned CombineOp =
22884 V.getOpcode() == X86ISD::UNPCKL ? X86ISD::PSHUFLW : X86ISD::PSHUFHW;
22885 if (V.getOperand(0) != V.getOperand(1) ||
22886 !V->isOnlyUserOf(V.getOperand(0).getNode()))
22888 Chain.push_back(V);
22889 V = V.getOperand(0);
22891 switch (V.getOpcode()) {
22893 return SDValue(); // Nothing to combine.
22895 case X86ISD::PSHUFLW:
22896 case X86ISD::PSHUFHW:
22897 if (V.getOpcode() == CombineOp)
22900 Chain.push_back(V);
22904 V = V.getOperand(0);
22908 } while (V.hasOneUse());
22911 // Break out of the loop if we break out of the switch.
22915 if (!V.hasOneUse())
22916 // We fell out of the loop without finding a viable combining instruction.
22919 // Merge this node's mask and our incoming mask.
22920 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
22921 for (int &M : Mask)
22923 V = DAG.getNode(V.getOpcode(), DL, V.getValueType(), V.getOperand(0),
22924 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
22926 // Rebuild the chain around this new shuffle.
22927 while (!Chain.empty()) {
22928 SDValue W = Chain.pop_back_val();
22930 if (V.getValueType() != W.getOperand(0).getValueType())
22931 V = DAG.getBitcast(W.getOperand(0).getValueType(), V);
22933 switch (W.getOpcode()) {
22935 llvm_unreachable("Only PSHUF and UNPCK instructions get here!");
22937 case X86ISD::UNPCKL:
22938 case X86ISD::UNPCKH:
22939 V = DAG.getNode(W.getOpcode(), DL, W.getValueType(), V, V);
22942 case X86ISD::PSHUFD:
22943 case X86ISD::PSHUFLW:
22944 case X86ISD::PSHUFHW:
22945 V = DAG.getNode(W.getOpcode(), DL, W.getValueType(), V, W.getOperand(1));
22949 if (V.getValueType() != N.getValueType())
22950 V = DAG.getBitcast(N.getValueType(), V);
22952 // Return the new chain to replace N.
22956 /// \brief Search for a combinable shuffle across a chain ending in pshuflw or
22959 /// We walk up the chain, skipping shuffles of the other half and looking
22960 /// through shuffles which switch halves trying to find a shuffle of the same
22961 /// pair of dwords.
22962 static bool combineRedundantHalfShuffle(SDValue N, MutableArrayRef<int> Mask,
22964 TargetLowering::DAGCombinerInfo &DCI) {
22966 (N.getOpcode() == X86ISD::PSHUFLW || N.getOpcode() == X86ISD::PSHUFHW) &&
22967 "Called with something other than an x86 128-bit half shuffle!");
22969 unsigned CombineOpcode = N.getOpcode();
22971 // Walk up a single-use chain looking for a combinable shuffle.
22972 SDValue V = N.getOperand(0);
22973 for (; V.hasOneUse(); V = V.getOperand(0)) {
22974 switch (V.getOpcode()) {
22976 return false; // Nothing combined!
22979 // Skip bitcasts as we always know the type for the target specific
22983 case X86ISD::PSHUFLW:
22984 case X86ISD::PSHUFHW:
22985 if (V.getOpcode() == CombineOpcode)
22988 // Other-half shuffles are no-ops.
22991 // Break out of the loop if we break out of the switch.
22995 if (!V.hasOneUse())
22996 // We fell out of the loop without finding a viable combining instruction.
22999 // Combine away the bottom node as its shuffle will be accumulated into
23000 // a preceding shuffle.
23001 DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
23003 // Record the old value.
23006 // Merge this node's mask and our incoming mask (adjusted to account for all
23007 // the pshufd instructions encountered).
23008 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
23009 for (int &M : Mask)
23011 V = DAG.getNode(V.getOpcode(), DL, MVT::v8i16, V.getOperand(0),
23012 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
23014 // Check that the shuffles didn't cancel each other out. If not, we need to
23015 // combine to the new one.
23017 // Replace the combinable shuffle with the combined one, updating all users
23018 // so that we re-evaluate the chain here.
23019 DCI.CombineTo(Old.getNode(), V, /*AddTo*/ true);
23024 /// \brief Try to combine x86 target specific shuffles.
23025 static SDValue PerformTargetShuffleCombine(SDValue N, SelectionDAG &DAG,
23026 TargetLowering::DAGCombinerInfo &DCI,
23027 const X86Subtarget *Subtarget) {
23029 MVT VT = N.getSimpleValueType();
23030 SmallVector<int, 4> Mask;
23032 switch (N.getOpcode()) {
23033 case X86ISD::PSHUFD:
23034 case X86ISD::PSHUFLW:
23035 case X86ISD::PSHUFHW:
23036 Mask = getPSHUFShuffleMask(N);
23037 assert(Mask.size() == 4);
23039 case X86ISD::UNPCKL: {
23040 // Combine X86ISD::UNPCKL and ISD::VECTOR_SHUFFLE into X86ISD::UNPCKH, in
23041 // which X86ISD::UNPCKL has a ISD::UNDEF operand, and ISD::VECTOR_SHUFFLE
23042 // moves upper half elements into the lower half part. For example:
23044 // t2: v16i8 = vector_shuffle<8,9,10,11,12,13,14,15,u,u,u,u,u,u,u,u> t1,
23046 // t3: v16i8 = X86ISD::UNPCKL undef:v16i8, t2
23048 // will be combined to:
23050 // t3: v16i8 = X86ISD::UNPCKH undef:v16i8, t1
23052 // This is only for 128-bit vectors. From SSE4.1 onward this combine may not
23053 // happen due to advanced instructions.
23054 if (!VT.is128BitVector())
23057 auto Op0 = N.getOperand(0);
23058 auto Op1 = N.getOperand(1);
23059 if (Op0.getOpcode() == ISD::UNDEF &&
23060 Op1.getNode()->getOpcode() == ISD::VECTOR_SHUFFLE) {
23061 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(Op1.getNode())->getMask();
23063 unsigned NumElts = VT.getVectorNumElements();
23064 SmallVector<int, 8> ExpectedMask(NumElts, -1);
23065 std::iota(ExpectedMask.begin(), ExpectedMask.begin() + NumElts / 2,
23068 auto ShufOp = Op1.getOperand(0);
23069 if (isShuffleEquivalent(Op1, ShufOp, Mask, ExpectedMask))
23070 return DAG.getNode(X86ISD::UNPCKH, DL, VT, N.getOperand(0), ShufOp);
23078 // Nuke no-op shuffles that show up after combining.
23079 if (isNoopShuffleMask(Mask))
23080 return DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
23082 // Look for simplifications involving one or two shuffle instructions.
23083 SDValue V = N.getOperand(0);
23084 switch (N.getOpcode()) {
23087 case X86ISD::PSHUFLW:
23088 case X86ISD::PSHUFHW:
23089 assert(VT.getVectorElementType() == MVT::i16 && "Bad word shuffle type!");
23091 if (combineRedundantHalfShuffle(N, Mask, DAG, DCI))
23092 return SDValue(); // We combined away this shuffle, so we're done.
23094 // See if this reduces to a PSHUFD which is no more expensive and can
23095 // combine with more operations. Note that it has to at least flip the
23096 // dwords as otherwise it would have been removed as a no-op.
23097 if (makeArrayRef(Mask).equals({2, 3, 0, 1})) {
23098 int DMask[] = {0, 1, 2, 3};
23099 int DOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 2;
23100 DMask[DOffset + 0] = DOffset + 1;
23101 DMask[DOffset + 1] = DOffset + 0;
23102 MVT DVT = MVT::getVectorVT(MVT::i32, VT.getVectorNumElements() / 2);
23103 V = DAG.getBitcast(DVT, V);
23104 DCI.AddToWorklist(V.getNode());
23105 V = DAG.getNode(X86ISD::PSHUFD, DL, DVT, V,
23106 getV4X86ShuffleImm8ForMask(DMask, DL, DAG));
23107 DCI.AddToWorklist(V.getNode());
23108 return DAG.getBitcast(VT, V);
23111 // Look for shuffle patterns which can be implemented as a single unpack.
23112 // FIXME: This doesn't handle the location of the PSHUFD generically, and
23113 // only works when we have a PSHUFD followed by two half-shuffles.
23114 if (Mask[0] == Mask[1] && Mask[2] == Mask[3] &&
23115 (V.getOpcode() == X86ISD::PSHUFLW ||
23116 V.getOpcode() == X86ISD::PSHUFHW) &&
23117 V.getOpcode() != N.getOpcode() &&
23119 SDValue D = V.getOperand(0);
23120 while (D.getOpcode() == ISD::BITCAST && D.hasOneUse())
23121 D = D.getOperand(0);
23122 if (D.getOpcode() == X86ISD::PSHUFD && D.hasOneUse()) {
23123 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
23124 SmallVector<int, 4> DMask = getPSHUFShuffleMask(D);
23125 int NOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
23126 int VOffset = V.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
23128 for (int i = 0; i < 4; ++i) {
23129 WordMask[i + NOffset] = Mask[i] + NOffset;
23130 WordMask[i + VOffset] = VMask[i] + VOffset;
23132 // Map the word mask through the DWord mask.
23134 for (int i = 0; i < 8; ++i)
23135 MappedMask[i] = 2 * DMask[WordMask[i] / 2] + WordMask[i] % 2;
23136 if (makeArrayRef(MappedMask).equals({0, 0, 1, 1, 2, 2, 3, 3}) ||
23137 makeArrayRef(MappedMask).equals({4, 4, 5, 5, 6, 6, 7, 7})) {
23138 // We can replace all three shuffles with an unpack.
23139 V = DAG.getBitcast(VT, D.getOperand(0));
23140 DCI.AddToWorklist(V.getNode());
23141 return DAG.getNode(MappedMask[0] == 0 ? X86ISD::UNPCKL
23150 case X86ISD::PSHUFD:
23151 if (SDValue NewN = combineRedundantDWordShuffle(N, Mask, DAG, DCI))
23160 /// \brief Try to combine a shuffle into a target-specific add-sub node.
23162 /// We combine this directly on the abstract vector shuffle nodes so it is
23163 /// easier to generically match. We also insert dummy vector shuffle nodes for
23164 /// the operands which explicitly discard the lanes which are unused by this
23165 /// operation to try to flow through the rest of the combiner the fact that
23166 /// they're unused.
23167 static SDValue combineShuffleToAddSub(SDNode *N, SelectionDAG &DAG) {
23169 EVT VT = N->getValueType(0);
23171 // We only handle target-independent shuffles.
23172 // FIXME: It would be easy and harmless to use the target shuffle mask
23173 // extraction tool to support more.
23174 if (N->getOpcode() != ISD::VECTOR_SHUFFLE)
23177 auto *SVN = cast<ShuffleVectorSDNode>(N);
23178 SmallVector<int, 8> Mask;
23179 for (int M : SVN->getMask())
23182 SDValue V1 = N->getOperand(0);
23183 SDValue V2 = N->getOperand(1);
23185 // We require the first shuffle operand to be the FSUB node, and the second to
23186 // be the FADD node.
23187 if (V1.getOpcode() == ISD::FADD && V2.getOpcode() == ISD::FSUB) {
23188 ShuffleVectorSDNode::commuteMask(Mask);
23190 } else if (V1.getOpcode() != ISD::FSUB || V2.getOpcode() != ISD::FADD)
23193 // If there are other uses of these operations we can't fold them.
23194 if (!V1->hasOneUse() || !V2->hasOneUse())
23197 // Ensure that both operations have the same operands. Note that we can
23198 // commute the FADD operands.
23199 SDValue LHS = V1->getOperand(0), RHS = V1->getOperand(1);
23200 if ((V2->getOperand(0) != LHS || V2->getOperand(1) != RHS) &&
23201 (V2->getOperand(0) != RHS || V2->getOperand(1) != LHS))
23204 // We're looking for blends between FADD and FSUB nodes. We insist on these
23205 // nodes being lined up in a specific expected pattern.
23206 if (!(isShuffleEquivalent(V1, V2, Mask, {0, 3}) ||
23207 isShuffleEquivalent(V1, V2, Mask, {0, 5, 2, 7}) ||
23208 isShuffleEquivalent(V1, V2, Mask, {0, 9, 2, 11, 4, 13, 6, 15})))
23211 // Only specific types are legal at this point, assert so we notice if and
23212 // when these change.
23213 assert((VT == MVT::v4f32 || VT == MVT::v2f64 || VT == MVT::v8f32 ||
23214 VT == MVT::v4f64) &&
23215 "Unknown vector type encountered!");
23217 return DAG.getNode(X86ISD::ADDSUB, DL, VT, LHS, RHS);
23220 /// PerformShuffleCombine - Performs several different shuffle combines.
23221 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
23222 TargetLowering::DAGCombinerInfo &DCI,
23223 const X86Subtarget *Subtarget) {
23225 SDValue N0 = N->getOperand(0);
23226 SDValue N1 = N->getOperand(1);
23227 EVT VT = N->getValueType(0);
23229 // Don't create instructions with illegal types after legalize types has run.
23230 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23231 if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType()))
23234 // If we have legalized the vector types, look for blends of FADD and FSUB
23235 // nodes that we can fuse into an ADDSUB node.
23236 if (TLI.isTypeLegal(VT) && Subtarget->hasSSE3())
23237 if (SDValue AddSub = combineShuffleToAddSub(N, DAG))
23240 // Combine 256-bit vector shuffles. This is only profitable when in AVX mode
23241 if (TLI.isTypeLegal(VT) && Subtarget->hasFp256() && VT.is256BitVector() &&
23242 N->getOpcode() == ISD::VECTOR_SHUFFLE)
23243 return PerformShuffleCombine256(N, DAG, DCI, Subtarget);
23245 // During Type Legalization, when promoting illegal vector types,
23246 // the backend might introduce new shuffle dag nodes and bitcasts.
23248 // This code performs the following transformation:
23249 // fold: (shuffle (bitcast (BINOP A, B)), Undef, <Mask>) ->
23250 // (shuffle (BINOP (bitcast A), (bitcast B)), Undef, <Mask>)
23252 // We do this only if both the bitcast and the BINOP dag nodes have
23253 // one use. Also, perform this transformation only if the new binary
23254 // operation is legal. This is to avoid introducing dag nodes that
23255 // potentially need to be further expanded (or custom lowered) into a
23256 // less optimal sequence of dag nodes.
23257 if (!DCI.isBeforeLegalize() && DCI.isBeforeLegalizeOps() &&
23258 N1.getOpcode() == ISD::UNDEF && N0.hasOneUse() &&
23259 N0.getOpcode() == ISD::BITCAST) {
23260 SDValue BC0 = N0.getOperand(0);
23261 EVT SVT = BC0.getValueType();
23262 unsigned Opcode = BC0.getOpcode();
23263 unsigned NumElts = VT.getVectorNumElements();
23265 if (BC0.hasOneUse() && SVT.isVector() &&
23266 SVT.getVectorNumElements() * 2 == NumElts &&
23267 TLI.isOperationLegal(Opcode, VT)) {
23268 bool CanFold = false;
23280 unsigned SVTNumElts = SVT.getVectorNumElements();
23281 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
23282 for (unsigned i = 0, e = SVTNumElts; i != e && CanFold; ++i)
23283 CanFold = SVOp->getMaskElt(i) == (int)(i * 2);
23284 for (unsigned i = SVTNumElts, e = NumElts; i != e && CanFold; ++i)
23285 CanFold = SVOp->getMaskElt(i) < 0;
23288 SDValue BC00 = DAG.getBitcast(VT, BC0.getOperand(0));
23289 SDValue BC01 = DAG.getBitcast(VT, BC0.getOperand(1));
23290 SDValue NewBinOp = DAG.getNode(BC0.getOpcode(), dl, VT, BC00, BC01);
23291 return DAG.getVectorShuffle(VT, dl, NewBinOp, N1, &SVOp->getMask()[0]);
23296 // Combine a vector_shuffle that is equal to build_vector load1, load2, load3,
23297 // load4, <0, 1, 2, 3> into a 128-bit load if the load addresses are
23298 // consecutive, non-overlapping, and in the right order.
23299 SmallVector<SDValue, 16> Elts;
23300 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
23301 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0));
23303 if (SDValue LD = EltsFromConsecutiveLoads(VT, Elts, dl, DAG, true))
23306 if (isTargetShuffle(N->getOpcode())) {
23308 PerformTargetShuffleCombine(SDValue(N, 0), DAG, DCI, Subtarget);
23309 if (Shuffle.getNode())
23312 // Try recursively combining arbitrary sequences of x86 shuffle
23313 // instructions into higher-order shuffles. We do this after combining
23314 // specific PSHUF instruction sequences into their minimal form so that we
23315 // can evaluate how many specialized shuffle instructions are involved in
23316 // a particular chain.
23317 SmallVector<int, 1> NonceMask; // Just a placeholder.
23318 NonceMask.push_back(0);
23319 if (combineX86ShufflesRecursively(SDValue(N, 0), SDValue(N, 0), NonceMask,
23320 /*Depth*/ 1, /*HasPSHUFB*/ false, DAG,
23322 return SDValue(); // This routine will use CombineTo to replace N.
23328 /// XFormVExtractWithShuffleIntoLoad - Check if a vector extract from a target
23329 /// specific shuffle of a load can be folded into a single element load.
23330 /// Similar handling for VECTOR_SHUFFLE is performed by DAGCombiner, but
23331 /// shuffles have been custom lowered so we need to handle those here.
23332 static SDValue XFormVExtractWithShuffleIntoLoad(SDNode *N, SelectionDAG &DAG,
23333 TargetLowering::DAGCombinerInfo &DCI) {
23334 if (DCI.isBeforeLegalizeOps())
23337 SDValue InVec = N->getOperand(0);
23338 SDValue EltNo = N->getOperand(1);
23340 if (!isa<ConstantSDNode>(EltNo))
23343 EVT OriginalVT = InVec.getValueType();
23345 if (InVec.getOpcode() == ISD::BITCAST) {
23346 // Don't duplicate a load with other uses.
23347 if (!InVec.hasOneUse())
23349 EVT BCVT = InVec.getOperand(0).getValueType();
23350 if (!BCVT.isVector() ||
23351 BCVT.getVectorNumElements() != OriginalVT.getVectorNumElements())
23353 InVec = InVec.getOperand(0);
23356 EVT CurrentVT = InVec.getValueType();
23358 if (!isTargetShuffle(InVec.getOpcode()))
23361 // Don't duplicate a load with other uses.
23362 if (!InVec.hasOneUse())
23365 SmallVector<int, 16> ShuffleMask;
23367 if (!getTargetShuffleMask(InVec.getNode(), CurrentVT.getSimpleVT(),
23368 ShuffleMask, UnaryShuffle))
23371 // Select the input vector, guarding against out of range extract vector.
23372 unsigned NumElems = CurrentVT.getVectorNumElements();
23373 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
23374 int Idx = (Elt > (int)NumElems) ? -1 : ShuffleMask[Elt];
23375 SDValue LdNode = (Idx < (int)NumElems) ? InVec.getOperand(0)
23376 : InVec.getOperand(1);
23378 // If inputs to shuffle are the same for both ops, then allow 2 uses
23379 unsigned AllowedUses = InVec.getNumOperands() > 1 &&
23380 InVec.getOperand(0) == InVec.getOperand(1) ? 2 : 1;
23382 if (LdNode.getOpcode() == ISD::BITCAST) {
23383 // Don't duplicate a load with other uses.
23384 if (!LdNode.getNode()->hasNUsesOfValue(AllowedUses, 0))
23387 AllowedUses = 1; // only allow 1 load use if we have a bitcast
23388 LdNode = LdNode.getOperand(0);
23391 if (!ISD::isNormalLoad(LdNode.getNode()))
23394 LoadSDNode *LN0 = cast<LoadSDNode>(LdNode);
23396 if (!LN0 ||!LN0->hasNUsesOfValue(AllowedUses, 0) || LN0->isVolatile())
23399 EVT EltVT = N->getValueType(0);
23400 // If there's a bitcast before the shuffle, check if the load type and
23401 // alignment is valid.
23402 unsigned Align = LN0->getAlignment();
23403 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23404 unsigned NewAlign = DAG.getDataLayout().getABITypeAlignment(
23405 EltVT.getTypeForEVT(*DAG.getContext()));
23407 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, EltVT))
23410 // All checks match so transform back to vector_shuffle so that DAG combiner
23411 // can finish the job
23414 // Create shuffle node taking into account the case that its a unary shuffle
23415 SDValue Shuffle = (UnaryShuffle) ? DAG.getUNDEF(CurrentVT)
23416 : InVec.getOperand(1);
23417 Shuffle = DAG.getVectorShuffle(CurrentVT, dl,
23418 InVec.getOperand(0), Shuffle,
23420 Shuffle = DAG.getBitcast(OriginalVT, Shuffle);
23421 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, N->getValueType(0), Shuffle,
23425 static SDValue PerformBITCASTCombine(SDNode *N, SelectionDAG &DAG,
23426 const X86Subtarget *Subtarget) {
23427 SDValue N0 = N->getOperand(0);
23428 EVT VT = N->getValueType(0);
23430 // Detect bitcasts between i32 to x86mmx low word. Since MMX types are
23431 // special and don't usually play with other vector types, it's better to
23432 // handle them early to be sure we emit efficient code by avoiding
23433 // store-load conversions.
23434 if (VT == MVT::x86mmx && N0.getOpcode() == ISD::BUILD_VECTOR &&
23435 N0.getValueType() == MVT::v2i32 &&
23436 isNullConstant(N0.getOperand(1))) {
23437 SDValue N00 = N0->getOperand(0);
23438 if (N00.getValueType() == MVT::i32)
23439 return DAG.getNode(X86ISD::MMX_MOVW2D, SDLoc(N00), VT, N00);
23442 // Convert a bitcasted integer logic operation that has one bitcasted
23443 // floating-point operand and one constant operand into a floating-point
23444 // logic operation. This may create a load of the constant, but that is
23445 // cheaper than materializing the constant in an integer register and
23446 // transferring it to an SSE register or transferring the SSE operand to
23447 // integer register and back.
23449 switch (N0.getOpcode()) {
23450 case ISD::AND: FPOpcode = X86ISD::FAND; break;
23451 case ISD::OR: FPOpcode = X86ISD::FOR; break;
23452 case ISD::XOR: FPOpcode = X86ISD::FXOR; break;
23453 default: return SDValue();
23455 if (((Subtarget->hasSSE1() && VT == MVT::f32) ||
23456 (Subtarget->hasSSE2() && VT == MVT::f64)) &&
23457 isa<ConstantSDNode>(N0.getOperand(1)) &&
23458 N0.getOperand(0).getOpcode() == ISD::BITCAST &&
23459 N0.getOperand(0).getOperand(0).getValueType() == VT) {
23460 SDValue N000 = N0.getOperand(0).getOperand(0);
23461 SDValue FPConst = DAG.getBitcast(VT, N0.getOperand(1));
23462 return DAG.getNode(FPOpcode, SDLoc(N0), VT, N000, FPConst);
23468 /// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index
23469 /// generation and convert it from being a bunch of shuffles and extracts
23470 /// into a somewhat faster sequence. For i686, the best sequence is apparently
23471 /// storing the value and loading scalars back, while for x64 we should
23472 /// use 64-bit extracts and shifts.
23473 static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG,
23474 TargetLowering::DAGCombinerInfo &DCI) {
23475 if (SDValue NewOp = XFormVExtractWithShuffleIntoLoad(N, DAG, DCI))
23478 SDValue InputVector = N->getOperand(0);
23479 SDLoc dl(InputVector);
23480 // Detect mmx to i32 conversion through a v2i32 elt extract.
23481 if (InputVector.getOpcode() == ISD::BITCAST && InputVector.hasOneUse() &&
23482 N->getValueType(0) == MVT::i32 &&
23483 InputVector.getValueType() == MVT::v2i32) {
23485 // The bitcast source is a direct mmx result.
23486 SDValue MMXSrc = InputVector.getNode()->getOperand(0);
23487 if (MMXSrc.getValueType() == MVT::x86mmx)
23488 return DAG.getNode(X86ISD::MMX_MOVD2W, SDLoc(InputVector),
23489 N->getValueType(0),
23490 InputVector.getNode()->getOperand(0));
23492 // The mmx is indirect: (i64 extract_elt (v1i64 bitcast (x86mmx ...))).
23493 if (MMXSrc.getOpcode() == ISD::EXTRACT_VECTOR_ELT && MMXSrc.hasOneUse() &&
23494 MMXSrc.getValueType() == MVT::i64) {
23495 SDValue MMXSrcOp = MMXSrc.getOperand(0);
23496 if (MMXSrcOp.hasOneUse() && MMXSrcOp.getOpcode() == ISD::BITCAST &&
23497 MMXSrcOp.getValueType() == MVT::v1i64 &&
23498 MMXSrcOp.getOperand(0).getValueType() == MVT::x86mmx)
23499 return DAG.getNode(X86ISD::MMX_MOVD2W, SDLoc(InputVector),
23500 N->getValueType(0), MMXSrcOp.getOperand(0));
23504 EVT VT = N->getValueType(0);
23506 if (VT == MVT::i1 && isa<ConstantSDNode>(N->getOperand(1)) &&
23507 InputVector.getOpcode() == ISD::BITCAST &&
23508 isa<ConstantSDNode>(InputVector.getOperand(0))) {
23509 uint64_t ExtractedElt =
23510 cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
23511 uint64_t InputValue =
23512 cast<ConstantSDNode>(InputVector.getOperand(0))->getZExtValue();
23513 uint64_t Res = (InputValue >> ExtractedElt) & 1;
23514 return DAG.getConstant(Res, dl, MVT::i1);
23516 // Only operate on vectors of 4 elements, where the alternative shuffling
23517 // gets to be more expensive.
23518 if (InputVector.getValueType() != MVT::v4i32)
23521 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a
23522 // single use which is a sign-extend or zero-extend, and all elements are
23524 SmallVector<SDNode *, 4> Uses;
23525 unsigned ExtractedElements = 0;
23526 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(),
23527 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) {
23528 if (UI.getUse().getResNo() != InputVector.getResNo())
23531 SDNode *Extract = *UI;
23532 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
23535 if (Extract->getValueType(0) != MVT::i32)
23537 if (!Extract->hasOneUse())
23539 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND &&
23540 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND)
23542 if (!isa<ConstantSDNode>(Extract->getOperand(1)))
23545 // Record which element was extracted.
23546 ExtractedElements |=
23547 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue();
23549 Uses.push_back(Extract);
23552 // If not all the elements were used, this may not be worthwhile.
23553 if (ExtractedElements != 15)
23556 // Ok, we've now decided to do the transformation.
23557 // If 64-bit shifts are legal, use the extract-shift sequence,
23558 // otherwise bounce the vector off the cache.
23559 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23562 if (TLI.isOperationLegal(ISD::SRA, MVT::i64)) {
23563 SDValue Cst = DAG.getBitcast(MVT::v2i64, InputVector);
23564 auto &DL = DAG.getDataLayout();
23565 EVT VecIdxTy = DAG.getTargetLoweringInfo().getVectorIdxTy(DL);
23566 SDValue BottomHalf = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64, Cst,
23567 DAG.getConstant(0, dl, VecIdxTy));
23568 SDValue TopHalf = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64, Cst,
23569 DAG.getConstant(1, dl, VecIdxTy));
23571 SDValue ShAmt = DAG.getConstant(
23572 32, dl, DAG.getTargetLoweringInfo().getShiftAmountTy(MVT::i64, DL));
23573 Vals[0] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, BottomHalf);
23574 Vals[1] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32,
23575 DAG.getNode(ISD::SRA, dl, MVT::i64, BottomHalf, ShAmt));
23576 Vals[2] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, TopHalf);
23577 Vals[3] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32,
23578 DAG.getNode(ISD::SRA, dl, MVT::i64, TopHalf, ShAmt));
23580 // Store the value to a temporary stack slot.
23581 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType());
23582 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr,
23583 MachinePointerInfo(), false, false, 0);
23585 EVT ElementType = InputVector.getValueType().getVectorElementType();
23586 unsigned EltSize = ElementType.getSizeInBits() / 8;
23588 // Replace each use (extract) with a load of the appropriate element.
23589 for (unsigned i = 0; i < 4; ++i) {
23590 uint64_t Offset = EltSize * i;
23591 auto PtrVT = TLI.getPointerTy(DAG.getDataLayout());
23592 SDValue OffsetVal = DAG.getConstant(Offset, dl, PtrVT);
23594 SDValue ScalarAddr =
23595 DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, OffsetVal);
23597 // Load the scalar.
23598 Vals[i] = DAG.getLoad(ElementType, dl, Ch,
23599 ScalarAddr, MachinePointerInfo(),
23600 false, false, false, 0);
23605 // Replace the extracts
23606 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(),
23607 UE = Uses.end(); UI != UE; ++UI) {
23608 SDNode *Extract = *UI;
23610 SDValue Idx = Extract->getOperand(1);
23611 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
23612 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), Vals[IdxVal]);
23615 // The replacement was made in place; don't return anything.
23620 transformVSELECTtoBlendVECTOR_SHUFFLE(SDNode *N, SelectionDAG &DAG,
23621 const X86Subtarget *Subtarget) {
23623 SDValue Cond = N->getOperand(0);
23624 SDValue LHS = N->getOperand(1);
23625 SDValue RHS = N->getOperand(2);
23627 if (Cond.getOpcode() == ISD::SIGN_EXTEND) {
23628 SDValue CondSrc = Cond->getOperand(0);
23629 if (CondSrc->getOpcode() == ISD::SIGN_EXTEND_INREG)
23630 Cond = CondSrc->getOperand(0);
23633 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
23636 // A vselect where all conditions and data are constants can be optimized into
23637 // a single vector load by SelectionDAGLegalize::ExpandBUILD_VECTOR().
23638 if (ISD::isBuildVectorOfConstantSDNodes(LHS.getNode()) &&
23639 ISD::isBuildVectorOfConstantSDNodes(RHS.getNode()))
23642 unsigned MaskValue = 0;
23643 if (!BUILD_VECTORtoBlendMask(cast<BuildVectorSDNode>(Cond), MaskValue))
23646 MVT VT = N->getSimpleValueType(0);
23647 unsigned NumElems = VT.getVectorNumElements();
23648 SmallVector<int, 8> ShuffleMask(NumElems, -1);
23649 for (unsigned i = 0; i < NumElems; ++i) {
23650 // Be sure we emit undef where we can.
23651 if (Cond.getOperand(i)->getOpcode() == ISD::UNDEF)
23652 ShuffleMask[i] = -1;
23654 ShuffleMask[i] = i + NumElems * ((MaskValue >> i) & 1);
23657 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23658 if (!TLI.isShuffleMaskLegal(ShuffleMask, VT))
23660 return DAG.getVectorShuffle(VT, dl, LHS, RHS, &ShuffleMask[0]);
23663 /// PerformSELECTCombine - Do target-specific dag combines on SELECT and VSELECT
23665 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
23666 TargetLowering::DAGCombinerInfo &DCI,
23667 const X86Subtarget *Subtarget) {
23669 SDValue Cond = N->getOperand(0);
23670 // Get the LHS/RHS of the select.
23671 SDValue LHS = N->getOperand(1);
23672 SDValue RHS = N->getOperand(2);
23673 EVT VT = LHS.getValueType();
23674 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23676 // If we have SSE[12] support, try to form min/max nodes. SSE min/max
23677 // instructions match the semantics of the common C idiom x<y?x:y but not
23678 // x<=y?x:y, because of how they handle negative zero (which can be
23679 // ignored in unsafe-math mode).
23680 // We also try to create v2f32 min/max nodes, which we later widen to v4f32.
23681 if (Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() &&
23682 VT != MVT::f80 && (TLI.isTypeLegal(VT) || VT == MVT::v2f32) &&
23683 (Subtarget->hasSSE2() ||
23684 (Subtarget->hasSSE1() && VT.getScalarType() == MVT::f32))) {
23685 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
23687 unsigned Opcode = 0;
23688 // Check for x CC y ? x : y.
23689 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
23690 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
23694 // Converting this to a min would handle NaNs incorrectly, and swapping
23695 // the operands would cause it to handle comparisons between positive
23696 // and negative zero incorrectly.
23697 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
23698 if (!DAG.getTarget().Options.UnsafeFPMath &&
23699 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
23701 std::swap(LHS, RHS);
23703 Opcode = X86ISD::FMIN;
23706 // Converting this to a min would handle comparisons between positive
23707 // and negative zero incorrectly.
23708 if (!DAG.getTarget().Options.UnsafeFPMath &&
23709 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
23711 Opcode = X86ISD::FMIN;
23714 // Converting this to a min would handle both negative zeros and NaNs
23715 // incorrectly, but we can swap the operands to fix both.
23716 std::swap(LHS, RHS);
23720 Opcode = X86ISD::FMIN;
23724 // Converting this to a max would handle comparisons between positive
23725 // and negative zero incorrectly.
23726 if (!DAG.getTarget().Options.UnsafeFPMath &&
23727 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
23729 Opcode = X86ISD::FMAX;
23732 // Converting this to a max would handle NaNs incorrectly, and swapping
23733 // the operands would cause it to handle comparisons between positive
23734 // and negative zero incorrectly.
23735 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
23736 if (!DAG.getTarget().Options.UnsafeFPMath &&
23737 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
23739 std::swap(LHS, RHS);
23741 Opcode = X86ISD::FMAX;
23744 // Converting this to a max would handle both negative zeros and NaNs
23745 // incorrectly, but we can swap the operands to fix both.
23746 std::swap(LHS, RHS);
23750 Opcode = X86ISD::FMAX;
23753 // Check for x CC y ? y : x -- a min/max with reversed arms.
23754 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
23755 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
23759 // Converting this to a min would handle comparisons between positive
23760 // and negative zero incorrectly, and swapping the operands would
23761 // cause it to handle NaNs incorrectly.
23762 if (!DAG.getTarget().Options.UnsafeFPMath &&
23763 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) {
23764 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
23766 std::swap(LHS, RHS);
23768 Opcode = X86ISD::FMIN;
23771 // Converting this to a min would handle NaNs incorrectly.
23772 if (!DAG.getTarget().Options.UnsafeFPMath &&
23773 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
23775 Opcode = X86ISD::FMIN;
23778 // Converting this to a min would handle both negative zeros and NaNs
23779 // incorrectly, but we can swap the operands to fix both.
23780 std::swap(LHS, RHS);
23784 Opcode = X86ISD::FMIN;
23788 // Converting this to a max would handle NaNs incorrectly.
23789 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
23791 Opcode = X86ISD::FMAX;
23794 // Converting this to a max would handle comparisons between positive
23795 // and negative zero incorrectly, and swapping the operands would
23796 // cause it to handle NaNs incorrectly.
23797 if (!DAG.getTarget().Options.UnsafeFPMath &&
23798 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) {
23799 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
23801 std::swap(LHS, RHS);
23803 Opcode = X86ISD::FMAX;
23806 // Converting this to a max would handle both negative zeros and NaNs
23807 // incorrectly, but we can swap the operands to fix both.
23808 std::swap(LHS, RHS);
23812 Opcode = X86ISD::FMAX;
23818 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
23821 EVT CondVT = Cond.getValueType();
23822 if (Subtarget->hasAVX512() && VT.isVector() && CondVT.isVector() &&
23823 CondVT.getVectorElementType() == MVT::i1) {
23824 // v16i8 (select v16i1, v16i8, v16i8) does not have a proper
23825 // lowering on KNL. In this case we convert it to
23826 // v16i8 (select v16i8, v16i8, v16i8) and use AVX instruction.
23827 // The same situation for all 128 and 256-bit vectors of i8 and i16.
23828 // Since SKX these selects have a proper lowering.
23829 EVT OpVT = LHS.getValueType();
23830 if ((OpVT.is128BitVector() || OpVT.is256BitVector()) &&
23831 (OpVT.getVectorElementType() == MVT::i8 ||
23832 OpVT.getVectorElementType() == MVT::i16) &&
23833 !(Subtarget->hasBWI() && Subtarget->hasVLX())) {
23834 Cond = DAG.getNode(ISD::SIGN_EXTEND, DL, OpVT, Cond);
23835 DCI.AddToWorklist(Cond.getNode());
23836 return DAG.getNode(N->getOpcode(), DL, OpVT, Cond, LHS, RHS);
23839 // If this is a select between two integer constants, try to do some
23841 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
23842 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
23843 // Don't do this for crazy integer types.
23844 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
23845 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
23846 // so that TrueC (the true value) is larger than FalseC.
23847 bool NeedsCondInvert = false;
23849 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
23850 // Efficiently invertible.
23851 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
23852 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
23853 isa<ConstantSDNode>(Cond.getOperand(1))))) {
23854 NeedsCondInvert = true;
23855 std::swap(TrueC, FalseC);
23858 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
23859 if (FalseC->getAPIntValue() == 0 &&
23860 TrueC->getAPIntValue().isPowerOf2()) {
23861 if (NeedsCondInvert) // Invert the condition if needed.
23862 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
23863 DAG.getConstant(1, DL, Cond.getValueType()));
23865 // Zero extend the condition if needed.
23866 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
23868 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
23869 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
23870 DAG.getConstant(ShAmt, DL, MVT::i8));
23873 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
23874 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
23875 if (NeedsCondInvert) // Invert the condition if needed.
23876 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
23877 DAG.getConstant(1, DL, Cond.getValueType()));
23879 // Zero extend the condition if needed.
23880 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
23881 FalseC->getValueType(0), Cond);
23882 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
23883 SDValue(FalseC, 0));
23886 // Optimize cases that will turn into an LEA instruction. This requires
23887 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
23888 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
23889 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
23890 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
23892 bool isFastMultiplier = false;
23894 switch ((unsigned char)Diff) {
23896 case 1: // result = add base, cond
23897 case 2: // result = lea base( , cond*2)
23898 case 3: // result = lea base(cond, cond*2)
23899 case 4: // result = lea base( , cond*4)
23900 case 5: // result = lea base(cond, cond*4)
23901 case 8: // result = lea base( , cond*8)
23902 case 9: // result = lea base(cond, cond*8)
23903 isFastMultiplier = true;
23908 if (isFastMultiplier) {
23909 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
23910 if (NeedsCondInvert) // Invert the condition if needed.
23911 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
23912 DAG.getConstant(1, DL, Cond.getValueType()));
23914 // Zero extend the condition if needed.
23915 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
23917 // Scale the condition by the difference.
23919 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
23920 DAG.getConstant(Diff, DL,
23921 Cond.getValueType()));
23923 // Add the base if non-zero.
23924 if (FalseC->getAPIntValue() != 0)
23925 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
23926 SDValue(FalseC, 0));
23933 // Canonicalize max and min:
23934 // (x > y) ? x : y -> (x >= y) ? x : y
23935 // (x < y) ? x : y -> (x <= y) ? x : y
23936 // This allows use of COND_S / COND_NS (see TranslateX86CC) which eliminates
23937 // the need for an extra compare
23938 // against zero. e.g.
23939 // (x - y) > 0 : (x - y) ? 0 -> (x - y) >= 0 : (x - y) ? 0
23941 // testl %edi, %edi
23943 // cmovgl %edi, %eax
23947 // cmovsl %eax, %edi
23948 if (N->getOpcode() == ISD::SELECT && Cond.getOpcode() == ISD::SETCC &&
23949 DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
23950 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
23951 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
23956 ISD::CondCode NewCC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGE;
23957 Cond = DAG.getSetCC(SDLoc(Cond), Cond.getValueType(),
23958 Cond.getOperand(0), Cond.getOperand(1), NewCC);
23959 return DAG.getNode(ISD::SELECT, DL, VT, Cond, LHS, RHS);
23964 // Early exit check
23965 if (!TLI.isTypeLegal(VT))
23968 // Match VSELECTs into subs with unsigned saturation.
23969 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC &&
23970 // psubus is available in SSE2 and AVX2 for i8 and i16 vectors.
23971 ((Subtarget->hasSSE2() && (VT == MVT::v16i8 || VT == MVT::v8i16)) ||
23972 (Subtarget->hasAVX2() && (VT == MVT::v32i8 || VT == MVT::v16i16)))) {
23973 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
23975 // Check if one of the arms of the VSELECT is a zero vector. If it's on the
23976 // left side invert the predicate to simplify logic below.
23978 if (ISD::isBuildVectorAllZeros(LHS.getNode())) {
23980 CC = ISD::getSetCCInverse(CC, true);
23981 } else if (ISD::isBuildVectorAllZeros(RHS.getNode())) {
23985 if (Other.getNode() && Other->getNumOperands() == 2 &&
23986 DAG.isEqualTo(Other->getOperand(0), Cond.getOperand(0))) {
23987 SDValue OpLHS = Other->getOperand(0), OpRHS = Other->getOperand(1);
23988 SDValue CondRHS = Cond->getOperand(1);
23990 // Look for a general sub with unsigned saturation first.
23991 // x >= y ? x-y : 0 --> subus x, y
23992 // x > y ? x-y : 0 --> subus x, y
23993 if ((CC == ISD::SETUGE || CC == ISD::SETUGT) &&
23994 Other->getOpcode() == ISD::SUB && DAG.isEqualTo(OpRHS, CondRHS))
23995 return DAG.getNode(X86ISD::SUBUS, DL, VT, OpLHS, OpRHS);
23997 if (auto *OpRHSBV = dyn_cast<BuildVectorSDNode>(OpRHS))
23998 if (auto *OpRHSConst = OpRHSBV->getConstantSplatNode()) {
23999 if (auto *CondRHSBV = dyn_cast<BuildVectorSDNode>(CondRHS))
24000 if (auto *CondRHSConst = CondRHSBV->getConstantSplatNode())
24001 // If the RHS is a constant we have to reverse the const
24002 // canonicalization.
24003 // x > C-1 ? x+-C : 0 --> subus x, C
24004 if (CC == ISD::SETUGT && Other->getOpcode() == ISD::ADD &&
24005 CondRHSConst->getAPIntValue() ==
24006 (-OpRHSConst->getAPIntValue() - 1))
24007 return DAG.getNode(
24008 X86ISD::SUBUS, DL, VT, OpLHS,
24009 DAG.getConstant(-OpRHSConst->getAPIntValue(), DL, VT));
24011 // Another special case: If C was a sign bit, the sub has been
24012 // canonicalized into a xor.
24013 // FIXME: Would it be better to use computeKnownBits to determine
24014 // whether it's safe to decanonicalize the xor?
24015 // x s< 0 ? x^C : 0 --> subus x, C
24016 if (CC == ISD::SETLT && Other->getOpcode() == ISD::XOR &&
24017 ISD::isBuildVectorAllZeros(CondRHS.getNode()) &&
24018 OpRHSConst->getAPIntValue().isSignBit())
24019 // Note that we have to rebuild the RHS constant here to ensure we
24020 // don't rely on particular values of undef lanes.
24021 return DAG.getNode(
24022 X86ISD::SUBUS, DL, VT, OpLHS,
24023 DAG.getConstant(OpRHSConst->getAPIntValue(), DL, VT));
24028 // Simplify vector selection if condition value type matches vselect
24030 if (N->getOpcode() == ISD::VSELECT && CondVT == VT) {
24031 assert(Cond.getValueType().isVector() &&
24032 "vector select expects a vector selector!");
24034 bool TValIsAllOnes = ISD::isBuildVectorAllOnes(LHS.getNode());
24035 bool FValIsAllZeros = ISD::isBuildVectorAllZeros(RHS.getNode());
24037 // Try invert the condition if true value is not all 1s and false value
24039 if (!TValIsAllOnes && !FValIsAllZeros &&
24040 // Check if the selector will be produced by CMPP*/PCMP*
24041 Cond.getOpcode() == ISD::SETCC &&
24042 // Check if SETCC has already been promoted
24043 TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT) ==
24045 bool TValIsAllZeros = ISD::isBuildVectorAllZeros(LHS.getNode());
24046 bool FValIsAllOnes = ISD::isBuildVectorAllOnes(RHS.getNode());
24048 if (TValIsAllZeros || FValIsAllOnes) {
24049 SDValue CC = Cond.getOperand(2);
24050 ISD::CondCode NewCC =
24051 ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
24052 Cond.getOperand(0).getValueType().isInteger());
24053 Cond = DAG.getSetCC(DL, CondVT, Cond.getOperand(0), Cond.getOperand(1), NewCC);
24054 std::swap(LHS, RHS);
24055 TValIsAllOnes = FValIsAllOnes;
24056 FValIsAllZeros = TValIsAllZeros;
24060 if (TValIsAllOnes || FValIsAllZeros) {
24063 if (TValIsAllOnes && FValIsAllZeros)
24065 else if (TValIsAllOnes)
24067 DAG.getNode(ISD::OR, DL, CondVT, Cond, DAG.getBitcast(CondVT, RHS));
24068 else if (FValIsAllZeros)
24069 Ret = DAG.getNode(ISD::AND, DL, CondVT, Cond,
24070 DAG.getBitcast(CondVT, LHS));
24072 return DAG.getBitcast(VT, Ret);
24076 // We should generate an X86ISD::BLENDI from a vselect if its argument
24077 // is a sign_extend_inreg of an any_extend of a BUILD_VECTOR of
24078 // constants. This specific pattern gets generated when we split a
24079 // selector for a 512 bit vector in a machine without AVX512 (but with
24080 // 256-bit vectors), during legalization:
24082 // (vselect (sign_extend (any_extend (BUILD_VECTOR)) i1) LHS RHS)
24084 // Iff we find this pattern and the build_vectors are built from
24085 // constants, we translate the vselect into a shuffle_vector that we
24086 // know will be matched by LowerVECTOR_SHUFFLEtoBlend.
24087 if ((N->getOpcode() == ISD::VSELECT ||
24088 N->getOpcode() == X86ISD::SHRUNKBLEND) &&
24089 !DCI.isBeforeLegalize() && !VT.is512BitVector()) {
24090 SDValue Shuffle = transformVSELECTtoBlendVECTOR_SHUFFLE(N, DAG, Subtarget);
24091 if (Shuffle.getNode())
24095 // If this is a *dynamic* select (non-constant condition) and we can match
24096 // this node with one of the variable blend instructions, restructure the
24097 // condition so that the blends can use the high bit of each element and use
24098 // SimplifyDemandedBits to simplify the condition operand.
24099 if (N->getOpcode() == ISD::VSELECT && DCI.isBeforeLegalizeOps() &&
24100 !DCI.isBeforeLegalize() &&
24101 !ISD::isBuildVectorOfConstantSDNodes(Cond.getNode())) {
24102 unsigned BitWidth = Cond.getValueType().getScalarSizeInBits();
24104 // Don't optimize vector selects that map to mask-registers.
24108 // We can only handle the cases where VSELECT is directly legal on the
24109 // subtarget. We custom lower VSELECT nodes with constant conditions and
24110 // this makes it hard to see whether a dynamic VSELECT will correctly
24111 // lower, so we both check the operation's status and explicitly handle the
24112 // cases where a *dynamic* blend will fail even though a constant-condition
24113 // blend could be custom lowered.
24114 // FIXME: We should find a better way to handle this class of problems.
24115 // Potentially, we should combine constant-condition vselect nodes
24116 // pre-legalization into shuffles and not mark as many types as custom
24118 if (!TLI.isOperationLegalOrCustom(ISD::VSELECT, VT))
24120 // FIXME: We don't support i16-element blends currently. We could and
24121 // should support them by making *all* the bits in the condition be set
24122 // rather than just the high bit and using an i8-element blend.
24123 if (VT.getVectorElementType() == MVT::i16)
24125 // Dynamic blending was only available from SSE4.1 onward.
24126 if (VT.is128BitVector() && !Subtarget->hasSSE41())
24128 // Byte blends are only available in AVX2
24129 if (VT == MVT::v32i8 && !Subtarget->hasAVX2())
24132 assert(BitWidth >= 8 && BitWidth <= 64 && "Invalid mask size");
24133 APInt DemandedMask = APInt::getHighBitsSet(BitWidth, 1);
24135 APInt KnownZero, KnownOne;
24136 TargetLowering::TargetLoweringOpt TLO(DAG, DCI.isBeforeLegalize(),
24137 DCI.isBeforeLegalizeOps());
24138 if (TLO.ShrinkDemandedConstant(Cond, DemandedMask) ||
24139 TLI.SimplifyDemandedBits(Cond, DemandedMask, KnownZero, KnownOne,
24141 // If we changed the computation somewhere in the DAG, this change
24142 // will affect all users of Cond.
24143 // Make sure it is fine and update all the nodes so that we do not
24144 // use the generic VSELECT anymore. Otherwise, we may perform
24145 // wrong optimizations as we messed up with the actual expectation
24146 // for the vector boolean values.
24147 if (Cond != TLO.Old) {
24148 // Check all uses of that condition operand to check whether it will be
24149 // consumed by non-BLEND instructions, which may depend on all bits are
24151 for (SDNode::use_iterator I = Cond->use_begin(), E = Cond->use_end();
24153 if (I->getOpcode() != ISD::VSELECT)
24154 // TODO: Add other opcodes eventually lowered into BLEND.
24157 // Update all the users of the condition, before committing the change,
24158 // so that the VSELECT optimizations that expect the correct vector
24159 // boolean value will not be triggered.
24160 for (SDNode::use_iterator I = Cond->use_begin(), E = Cond->use_end();
24162 DAG.ReplaceAllUsesOfValueWith(
24164 DAG.getNode(X86ISD::SHRUNKBLEND, SDLoc(*I), I->getValueType(0),
24165 Cond, I->getOperand(1), I->getOperand(2)));
24166 DCI.CommitTargetLoweringOpt(TLO);
24169 // At this point, only Cond is changed. Change the condition
24170 // just for N to keep the opportunity to optimize all other
24171 // users their own way.
24172 DAG.ReplaceAllUsesOfValueWith(
24174 DAG.getNode(X86ISD::SHRUNKBLEND, SDLoc(N), N->getValueType(0),
24175 TLO.New, N->getOperand(1), N->getOperand(2)));
24183 // Check whether a boolean test is testing a boolean value generated by
24184 // X86ISD::SETCC. If so, return the operand of that SETCC and proper condition
24187 // Simplify the following patterns:
24188 // (Op (CMP (SETCC Cond EFLAGS) 1) EQ) or
24189 // (Op (CMP (SETCC Cond EFLAGS) 0) NEQ)
24190 // to (Op EFLAGS Cond)
24192 // (Op (CMP (SETCC Cond EFLAGS) 0) EQ) or
24193 // (Op (CMP (SETCC Cond EFLAGS) 1) NEQ)
24194 // to (Op EFLAGS !Cond)
24196 // where Op could be BRCOND or CMOV.
24198 static SDValue checkBoolTestSetCCCombine(SDValue Cmp, X86::CondCode &CC) {
24199 // Quit if not CMP and SUB with its value result used.
24200 if (Cmp.getOpcode() != X86ISD::CMP &&
24201 (Cmp.getOpcode() != X86ISD::SUB || Cmp.getNode()->hasAnyUseOfValue(0)))
24204 // Quit if not used as a boolean value.
24205 if (CC != X86::COND_E && CC != X86::COND_NE)
24208 // Check CMP operands. One of them should be 0 or 1 and the other should be
24209 // an SetCC or extended from it.
24210 SDValue Op1 = Cmp.getOperand(0);
24211 SDValue Op2 = Cmp.getOperand(1);
24214 const ConstantSDNode* C = nullptr;
24215 bool needOppositeCond = (CC == X86::COND_E);
24216 bool checkAgainstTrue = false; // Is it a comparison against 1?
24218 if ((C = dyn_cast<ConstantSDNode>(Op1)))
24220 else if ((C = dyn_cast<ConstantSDNode>(Op2)))
24222 else // Quit if all operands are not constants.
24225 if (C->getZExtValue() == 1) {
24226 needOppositeCond = !needOppositeCond;
24227 checkAgainstTrue = true;
24228 } else if (C->getZExtValue() != 0)
24229 // Quit if the constant is neither 0 or 1.
24232 bool truncatedToBoolWithAnd = false;
24233 // Skip (zext $x), (trunc $x), or (and $x, 1) node.
24234 while (SetCC.getOpcode() == ISD::ZERO_EXTEND ||
24235 SetCC.getOpcode() == ISD::TRUNCATE ||
24236 SetCC.getOpcode() == ISD::AND) {
24237 if (SetCC.getOpcode() == ISD::AND) {
24239 if (isOneConstant(SetCC.getOperand(0)))
24241 if (isOneConstant(SetCC.getOperand(1)))
24245 SetCC = SetCC.getOperand(OpIdx);
24246 truncatedToBoolWithAnd = true;
24248 SetCC = SetCC.getOperand(0);
24251 switch (SetCC.getOpcode()) {
24252 case X86ISD::SETCC_CARRY:
24253 // Since SETCC_CARRY gives output based on R = CF ? ~0 : 0, it's unsafe to
24254 // simplify it if the result of SETCC_CARRY is not canonicalized to 0 or 1,
24255 // i.e. it's a comparison against true but the result of SETCC_CARRY is not
24256 // truncated to i1 using 'and'.
24257 if (checkAgainstTrue && !truncatedToBoolWithAnd)
24259 assert(X86::CondCode(SetCC.getConstantOperandVal(0)) == X86::COND_B &&
24260 "Invalid use of SETCC_CARRY!");
24262 case X86ISD::SETCC:
24263 // Set the condition code or opposite one if necessary.
24264 CC = X86::CondCode(SetCC.getConstantOperandVal(0));
24265 if (needOppositeCond)
24266 CC = X86::GetOppositeBranchCondition(CC);
24267 return SetCC.getOperand(1);
24268 case X86ISD::CMOV: {
24269 // Check whether false/true value has canonical one, i.e. 0 or 1.
24270 ConstantSDNode *FVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(0));
24271 ConstantSDNode *TVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(1));
24272 // Quit if true value is not a constant.
24275 // Quit if false value is not a constant.
24277 SDValue Op = SetCC.getOperand(0);
24278 // Skip 'zext' or 'trunc' node.
24279 if (Op.getOpcode() == ISD::ZERO_EXTEND ||
24280 Op.getOpcode() == ISD::TRUNCATE)
24281 Op = Op.getOperand(0);
24282 // A special case for rdrand/rdseed, where 0 is set if false cond is
24284 if ((Op.getOpcode() != X86ISD::RDRAND &&
24285 Op.getOpcode() != X86ISD::RDSEED) || Op.getResNo() != 0)
24288 // Quit if false value is not the constant 0 or 1.
24289 bool FValIsFalse = true;
24290 if (FVal && FVal->getZExtValue() != 0) {
24291 if (FVal->getZExtValue() != 1)
24293 // If FVal is 1, opposite cond is needed.
24294 needOppositeCond = !needOppositeCond;
24295 FValIsFalse = false;
24297 // Quit if TVal is not the constant opposite of FVal.
24298 if (FValIsFalse && TVal->getZExtValue() != 1)
24300 if (!FValIsFalse && TVal->getZExtValue() != 0)
24302 CC = X86::CondCode(SetCC.getConstantOperandVal(2));
24303 if (needOppositeCond)
24304 CC = X86::GetOppositeBranchCondition(CC);
24305 return SetCC.getOperand(3);
24312 /// Check whether Cond is an AND/OR of SETCCs off of the same EFLAGS.
24314 /// (X86or (X86setcc) (X86setcc))
24315 /// (X86cmp (and (X86setcc) (X86setcc)), 0)
24316 static bool checkBoolTestAndOrSetCCCombine(SDValue Cond, X86::CondCode &CC0,
24317 X86::CondCode &CC1, SDValue &Flags,
24319 if (Cond->getOpcode() == X86ISD::CMP) {
24320 if (!isNullConstant(Cond->getOperand(1)))
24323 Cond = Cond->getOperand(0);
24328 SDValue SetCC0, SetCC1;
24329 switch (Cond->getOpcode()) {
24330 default: return false;
24337 SetCC0 = Cond->getOperand(0);
24338 SetCC1 = Cond->getOperand(1);
24342 // Make sure we have SETCC nodes, using the same flags value.
24343 if (SetCC0.getOpcode() != X86ISD::SETCC ||
24344 SetCC1.getOpcode() != X86ISD::SETCC ||
24345 SetCC0->getOperand(1) != SetCC1->getOperand(1))
24348 CC0 = (X86::CondCode)SetCC0->getConstantOperandVal(0);
24349 CC1 = (X86::CondCode)SetCC1->getConstantOperandVal(0);
24350 Flags = SetCC0->getOperand(1);
24354 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
24355 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
24356 TargetLowering::DAGCombinerInfo &DCI,
24357 const X86Subtarget *Subtarget) {
24360 // If the flag operand isn't dead, don't touch this CMOV.
24361 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
24364 SDValue FalseOp = N->getOperand(0);
24365 SDValue TrueOp = N->getOperand(1);
24366 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
24367 SDValue Cond = N->getOperand(3);
24369 if (CC == X86::COND_E || CC == X86::COND_NE) {
24370 switch (Cond.getOpcode()) {
24374 // If operand of BSR / BSF are proven never zero, then ZF cannot be set.
24375 if (DAG.isKnownNeverZero(Cond.getOperand(0)))
24376 return (CC == X86::COND_E) ? FalseOp : TrueOp;
24382 Flags = checkBoolTestSetCCCombine(Cond, CC);
24383 if (Flags.getNode() &&
24384 // Extra check as FCMOV only supports a subset of X86 cond.
24385 (FalseOp.getValueType() != MVT::f80 || hasFPCMov(CC))) {
24386 SDValue Ops[] = { FalseOp, TrueOp,
24387 DAG.getConstant(CC, DL, MVT::i8), Flags };
24388 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), Ops);
24391 // If this is a select between two integer constants, try to do some
24392 // optimizations. Note that the operands are ordered the opposite of SELECT
24394 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(TrueOp)) {
24395 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(FalseOp)) {
24396 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
24397 // larger than FalseC (the false value).
24398 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
24399 CC = X86::GetOppositeBranchCondition(CC);
24400 std::swap(TrueC, FalseC);
24401 std::swap(TrueOp, FalseOp);
24404 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
24405 // This is efficient for any integer data type (including i8/i16) and
24407 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
24408 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
24409 DAG.getConstant(CC, DL, MVT::i8), Cond);
24411 // Zero extend the condition if needed.
24412 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
24414 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
24415 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
24416 DAG.getConstant(ShAmt, DL, MVT::i8));
24417 if (N->getNumValues() == 2) // Dead flag value?
24418 return DCI.CombineTo(N, Cond, SDValue());
24422 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
24423 // for any integer data type, including i8/i16.
24424 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
24425 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
24426 DAG.getConstant(CC, DL, MVT::i8), Cond);
24428 // Zero extend the condition if needed.
24429 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
24430 FalseC->getValueType(0), Cond);
24431 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
24432 SDValue(FalseC, 0));
24434 if (N->getNumValues() == 2) // Dead flag value?
24435 return DCI.CombineTo(N, Cond, SDValue());
24439 // Optimize cases that will turn into an LEA instruction. This requires
24440 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
24441 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
24442 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
24443 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
24445 bool isFastMultiplier = false;
24447 switch ((unsigned char)Diff) {
24449 case 1: // result = add base, cond
24450 case 2: // result = lea base( , cond*2)
24451 case 3: // result = lea base(cond, cond*2)
24452 case 4: // result = lea base( , cond*4)
24453 case 5: // result = lea base(cond, cond*4)
24454 case 8: // result = lea base( , cond*8)
24455 case 9: // result = lea base(cond, cond*8)
24456 isFastMultiplier = true;
24461 if (isFastMultiplier) {
24462 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
24463 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
24464 DAG.getConstant(CC, DL, MVT::i8), Cond);
24465 // Zero extend the condition if needed.
24466 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
24468 // Scale the condition by the difference.
24470 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
24471 DAG.getConstant(Diff, DL, Cond.getValueType()));
24473 // Add the base if non-zero.
24474 if (FalseC->getAPIntValue() != 0)
24475 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
24476 SDValue(FalseC, 0));
24477 if (N->getNumValues() == 2) // Dead flag value?
24478 return DCI.CombineTo(N, Cond, SDValue());
24485 // Handle these cases:
24486 // (select (x != c), e, c) -> select (x != c), e, x),
24487 // (select (x == c), c, e) -> select (x == c), x, e)
24488 // where the c is an integer constant, and the "select" is the combination
24489 // of CMOV and CMP.
24491 // The rationale for this change is that the conditional-move from a constant
24492 // needs two instructions, however, conditional-move from a register needs
24493 // only one instruction.
24495 // CAVEAT: By replacing a constant with a symbolic value, it may obscure
24496 // some instruction-combining opportunities. This opt needs to be
24497 // postponed as late as possible.
24499 if (!DCI.isBeforeLegalize() && !DCI.isBeforeLegalizeOps()) {
24500 // the DCI.xxxx conditions are provided to postpone the optimization as
24501 // late as possible.
24503 ConstantSDNode *CmpAgainst = nullptr;
24504 if ((Cond.getOpcode() == X86ISD::CMP || Cond.getOpcode() == X86ISD::SUB) &&
24505 (CmpAgainst = dyn_cast<ConstantSDNode>(Cond.getOperand(1))) &&
24506 !isa<ConstantSDNode>(Cond.getOperand(0))) {
24508 if (CC == X86::COND_NE &&
24509 CmpAgainst == dyn_cast<ConstantSDNode>(FalseOp)) {
24510 CC = X86::GetOppositeBranchCondition(CC);
24511 std::swap(TrueOp, FalseOp);
24514 if (CC == X86::COND_E &&
24515 CmpAgainst == dyn_cast<ConstantSDNode>(TrueOp)) {
24516 SDValue Ops[] = { FalseOp, Cond.getOperand(0),
24517 DAG.getConstant(CC, DL, MVT::i8), Cond };
24518 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList (), Ops);
24523 // Fold and/or of setcc's to double CMOV:
24524 // (CMOV F, T, ((cc1 | cc2) != 0)) -> (CMOV (CMOV F, T, cc1), T, cc2)
24525 // (CMOV F, T, ((cc1 & cc2) != 0)) -> (CMOV (CMOV T, F, !cc1), F, !cc2)
24527 // This combine lets us generate:
24528 // cmovcc1 (jcc1 if we don't have CMOV)
24534 // cmovne (jne if we don't have CMOV)
24535 // When we can't use the CMOV instruction, it might increase branch
24537 // When we can use CMOV, or when there is no mispredict, this improves
24538 // throughput and reduces register pressure.
24540 if (CC == X86::COND_NE) {
24542 X86::CondCode CC0, CC1;
24544 if (checkBoolTestAndOrSetCCCombine(Cond, CC0, CC1, Flags, isAndSetCC)) {
24546 std::swap(FalseOp, TrueOp);
24547 CC0 = X86::GetOppositeBranchCondition(CC0);
24548 CC1 = X86::GetOppositeBranchCondition(CC1);
24551 SDValue LOps[] = {FalseOp, TrueOp, DAG.getConstant(CC0, DL, MVT::i8),
24553 SDValue LCMOV = DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), LOps);
24554 SDValue Ops[] = {LCMOV, TrueOp, DAG.getConstant(CC1, DL, MVT::i8), Flags};
24555 SDValue CMOV = DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), Ops);
24556 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), SDValue(CMOV.getNode(), 1));
24564 /// PerformMulCombine - Optimize a single multiply with constant into two
24565 /// in order to implement it with two cheaper instructions, e.g.
24566 /// LEA + SHL, LEA + LEA.
24567 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
24568 TargetLowering::DAGCombinerInfo &DCI) {
24569 // An imul is usually smaller than the alternative sequence.
24570 if (DAG.getMachineFunction().getFunction()->optForMinSize())
24573 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
24576 EVT VT = N->getValueType(0);
24577 if (VT != MVT::i64 && VT != MVT::i32)
24580 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
24583 uint64_t MulAmt = C->getZExtValue();
24584 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
24587 uint64_t MulAmt1 = 0;
24588 uint64_t MulAmt2 = 0;
24589 if ((MulAmt % 9) == 0) {
24591 MulAmt2 = MulAmt / 9;
24592 } else if ((MulAmt % 5) == 0) {
24594 MulAmt2 = MulAmt / 5;
24595 } else if ((MulAmt % 3) == 0) {
24597 MulAmt2 = MulAmt / 3;
24600 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
24603 if (isPowerOf2_64(MulAmt2) &&
24604 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
24605 // If second multiplifer is pow2, issue it first. We want the multiply by
24606 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
24608 std::swap(MulAmt1, MulAmt2);
24611 if (isPowerOf2_64(MulAmt1))
24612 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
24613 DAG.getConstant(Log2_64(MulAmt1), DL, MVT::i8));
24615 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
24616 DAG.getConstant(MulAmt1, DL, VT));
24618 if (isPowerOf2_64(MulAmt2))
24619 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
24620 DAG.getConstant(Log2_64(MulAmt2), DL, MVT::i8));
24622 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
24623 DAG.getConstant(MulAmt2, DL, VT));
24625 // Do not add new nodes to DAG combiner worklist.
24626 DCI.CombineTo(N, NewMul, false);
24631 static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) {
24632 SDValue N0 = N->getOperand(0);
24633 SDValue N1 = N->getOperand(1);
24634 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
24635 EVT VT = N0.getValueType();
24637 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2))
24638 // since the result of setcc_c is all zero's or all ones.
24639 if (VT.isInteger() && !VT.isVector() &&
24640 N1C && N0.getOpcode() == ISD::AND &&
24641 N0.getOperand(1).getOpcode() == ISD::Constant) {
24642 SDValue N00 = N0.getOperand(0);
24643 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
24644 APInt ShAmt = N1C->getAPIntValue();
24645 Mask = Mask.shl(ShAmt);
24646 bool MaskOK = false;
24647 // We can handle cases concerning bit-widening nodes containing setcc_c if
24648 // we carefully interrogate the mask to make sure we are semantics
24650 // The transform is not safe if the result of C1 << C2 exceeds the bitwidth
24651 // of the underlying setcc_c operation if the setcc_c was zero extended.
24652 // Consider the following example:
24653 // zext(setcc_c) -> i32 0x0000FFFF
24654 // c1 -> i32 0x0000FFFF
24655 // c2 -> i32 0x00000001
24656 // (shl (and (setcc_c), c1), c2) -> i32 0x0001FFFE
24657 // (and setcc_c, (c1 << c2)) -> i32 0x0000FFFE
24658 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
24660 } else if (N00.getOpcode() == ISD::SIGN_EXTEND &&
24661 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
24663 } else if ((N00.getOpcode() == ISD::ZERO_EXTEND ||
24664 N00.getOpcode() == ISD::ANY_EXTEND) &&
24665 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
24666 MaskOK = Mask.isIntN(N00.getOperand(0).getValueSizeInBits());
24668 if (MaskOK && Mask != 0) {
24670 return DAG.getNode(ISD::AND, DL, VT, N00, DAG.getConstant(Mask, DL, VT));
24674 // Hardware support for vector shifts is sparse which makes us scalarize the
24675 // vector operations in many cases. Also, on sandybridge ADD is faster than
24677 // (shl V, 1) -> add V,V
24678 if (auto *N1BV = dyn_cast<BuildVectorSDNode>(N1))
24679 if (auto *N1SplatC = N1BV->getConstantSplatNode()) {
24680 assert(N0.getValueType().isVector() && "Invalid vector shift type");
24681 // We shift all of the values by one. In many cases we do not have
24682 // hardware support for this operation. This is better expressed as an ADD
24684 if (N1SplatC->getAPIntValue() == 1)
24685 return DAG.getNode(ISD::ADD, SDLoc(N), VT, N0, N0);
24691 /// \brief Returns a vector of 0s if the node in input is a vector logical
24692 /// shift by a constant amount which is known to be bigger than or equal
24693 /// to the vector element size in bits.
24694 static SDValue performShiftToAllZeros(SDNode *N, SelectionDAG &DAG,
24695 const X86Subtarget *Subtarget) {
24696 EVT VT = N->getValueType(0);
24698 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16 &&
24699 (!Subtarget->hasInt256() ||
24700 (VT != MVT::v4i64 && VT != MVT::v8i32 && VT != MVT::v16i16)))
24703 SDValue Amt = N->getOperand(1);
24705 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Amt))
24706 if (auto *AmtSplat = AmtBV->getConstantSplatNode()) {
24707 APInt ShiftAmt = AmtSplat->getAPIntValue();
24708 unsigned MaxAmount =
24709 VT.getSimpleVT().getVectorElementType().getSizeInBits();
24711 // SSE2/AVX2 logical shifts always return a vector of 0s
24712 // if the shift amount is bigger than or equal to
24713 // the element size. The constant shift amount will be
24714 // encoded as a 8-bit immediate.
24715 if (ShiftAmt.trunc(8).uge(MaxAmount))
24716 return getZeroVector(VT.getSimpleVT(), Subtarget, DAG, DL);
24722 /// PerformShiftCombine - Combine shifts.
24723 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
24724 TargetLowering::DAGCombinerInfo &DCI,
24725 const X86Subtarget *Subtarget) {
24726 if (N->getOpcode() == ISD::SHL)
24727 if (SDValue V = PerformSHLCombine(N, DAG))
24730 // Try to fold this logical shift into a zero vector.
24731 if (N->getOpcode() != ISD::SRA)
24732 if (SDValue V = performShiftToAllZeros(N, DAG, Subtarget))
24738 // CMPEQCombine - Recognize the distinctive (AND (setcc ...) (setcc ..))
24739 // where both setccs reference the same FP CMP, and rewrite for CMPEQSS
24740 // and friends. Likewise for OR -> CMPNEQSS.
24741 static SDValue CMPEQCombine(SDNode *N, SelectionDAG &DAG,
24742 TargetLowering::DAGCombinerInfo &DCI,
24743 const X86Subtarget *Subtarget) {
24746 // SSE1 supports CMP{eq|ne}SS, and SSE2 added CMP{eq|ne}SD, but
24747 // we're requiring SSE2 for both.
24748 if (Subtarget->hasSSE2() && isAndOrOfSetCCs(SDValue(N, 0U), opcode)) {
24749 SDValue N0 = N->getOperand(0);
24750 SDValue N1 = N->getOperand(1);
24751 SDValue CMP0 = N0->getOperand(1);
24752 SDValue CMP1 = N1->getOperand(1);
24755 // The SETCCs should both refer to the same CMP.
24756 if (CMP0.getOpcode() != X86ISD::CMP || CMP0 != CMP1)
24759 SDValue CMP00 = CMP0->getOperand(0);
24760 SDValue CMP01 = CMP0->getOperand(1);
24761 EVT VT = CMP00.getValueType();
24763 if (VT == MVT::f32 || VT == MVT::f64) {
24764 bool ExpectingFlags = false;
24765 // Check for any users that want flags:
24766 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
24767 !ExpectingFlags && UI != UE; ++UI)
24768 switch (UI->getOpcode()) {
24773 ExpectingFlags = true;
24775 case ISD::CopyToReg:
24776 case ISD::SIGN_EXTEND:
24777 case ISD::ZERO_EXTEND:
24778 case ISD::ANY_EXTEND:
24782 if (!ExpectingFlags) {
24783 enum X86::CondCode cc0 = (enum X86::CondCode)N0.getConstantOperandVal(0);
24784 enum X86::CondCode cc1 = (enum X86::CondCode)N1.getConstantOperandVal(0);
24786 if (cc1 == X86::COND_E || cc1 == X86::COND_NE) {
24787 X86::CondCode tmp = cc0;
24792 if ((cc0 == X86::COND_E && cc1 == X86::COND_NP) ||
24793 (cc0 == X86::COND_NE && cc1 == X86::COND_P)) {
24794 // FIXME: need symbolic constants for these magic numbers.
24795 // See X86ATTInstPrinter.cpp:printSSECC().
24796 unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4;
24797 if (Subtarget->hasAVX512()) {
24798 SDValue FSetCC = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CMP00,
24800 DAG.getConstant(x86cc, DL, MVT::i8));
24801 if (N->getValueType(0) != MVT::i1)
24802 return DAG.getNode(ISD::ZERO_EXTEND, DL, N->getValueType(0),
24806 SDValue OnesOrZeroesF = DAG.getNode(X86ISD::FSETCC, DL,
24807 CMP00.getValueType(), CMP00, CMP01,
24808 DAG.getConstant(x86cc, DL,
24811 bool is64BitFP = (CMP00.getValueType() == MVT::f64);
24812 MVT IntVT = is64BitFP ? MVT::i64 : MVT::i32;
24814 if (is64BitFP && !Subtarget->is64Bit()) {
24815 // On a 32-bit target, we cannot bitcast the 64-bit float to a
24816 // 64-bit integer, since that's not a legal type. Since
24817 // OnesOrZeroesF is all ones of all zeroes, we don't need all the
24818 // bits, but can do this little dance to extract the lowest 32 bits
24819 // and work with those going forward.
24820 SDValue Vector64 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2f64,
24822 SDValue Vector32 = DAG.getBitcast(MVT::v4f32, Vector64);
24823 OnesOrZeroesF = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32,
24824 Vector32, DAG.getIntPtrConstant(0, DL));
24828 SDValue OnesOrZeroesI = DAG.getBitcast(IntVT, OnesOrZeroesF);
24829 SDValue ANDed = DAG.getNode(ISD::AND, DL, IntVT, OnesOrZeroesI,
24830 DAG.getConstant(1, DL, IntVT));
24831 SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8,
24833 return OneBitOfTruth;
24841 /// CanFoldXORWithAllOnes - Test whether the XOR operand is a AllOnes vector
24842 /// so it can be folded inside ANDNP.
24843 static bool CanFoldXORWithAllOnes(const SDNode *N) {
24844 EVT VT = N->getValueType(0);
24846 // Match direct AllOnes for 128 and 256-bit vectors
24847 if (ISD::isBuildVectorAllOnes(N))
24850 // Look through a bit convert.
24851 if (N->getOpcode() == ISD::BITCAST)
24852 N = N->getOperand(0).getNode();
24854 // Sometimes the operand may come from a insert_subvector building a 256-bit
24856 if (VT.is256BitVector() &&
24857 N->getOpcode() == ISD::INSERT_SUBVECTOR) {
24858 SDValue V1 = N->getOperand(0);
24859 SDValue V2 = N->getOperand(1);
24861 if (V1.getOpcode() == ISD::INSERT_SUBVECTOR &&
24862 V1.getOperand(0).getOpcode() == ISD::UNDEF &&
24863 ISD::isBuildVectorAllOnes(V1.getOperand(1).getNode()) &&
24864 ISD::isBuildVectorAllOnes(V2.getNode()))
24871 // On AVX/AVX2 the type v8i1 is legalized to v8i16, which is an XMM sized
24872 // register. In most cases we actually compare or select YMM-sized registers
24873 // and mixing the two types creates horrible code. This method optimizes
24874 // some of the transition sequences.
24875 static SDValue WidenMaskArithmetic(SDNode *N, SelectionDAG &DAG,
24876 TargetLowering::DAGCombinerInfo &DCI,
24877 const X86Subtarget *Subtarget) {
24878 EVT VT = N->getValueType(0);
24879 if (!VT.is256BitVector())
24882 assert((N->getOpcode() == ISD::ANY_EXTEND ||
24883 N->getOpcode() == ISD::ZERO_EXTEND ||
24884 N->getOpcode() == ISD::SIGN_EXTEND) && "Invalid Node");
24886 SDValue Narrow = N->getOperand(0);
24887 EVT NarrowVT = Narrow->getValueType(0);
24888 if (!NarrowVT.is128BitVector())
24891 if (Narrow->getOpcode() != ISD::XOR &&
24892 Narrow->getOpcode() != ISD::AND &&
24893 Narrow->getOpcode() != ISD::OR)
24896 SDValue N0 = Narrow->getOperand(0);
24897 SDValue N1 = Narrow->getOperand(1);
24900 // The Left side has to be a trunc.
24901 if (N0.getOpcode() != ISD::TRUNCATE)
24904 // The type of the truncated inputs.
24905 EVT WideVT = N0->getOperand(0)->getValueType(0);
24909 // The right side has to be a 'trunc' or a constant vector.
24910 bool RHSTrunc = N1.getOpcode() == ISD::TRUNCATE;
24911 ConstantSDNode *RHSConstSplat = nullptr;
24912 if (auto *RHSBV = dyn_cast<BuildVectorSDNode>(N1))
24913 RHSConstSplat = RHSBV->getConstantSplatNode();
24914 if (!RHSTrunc && !RHSConstSplat)
24917 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
24919 if (!TLI.isOperationLegalOrPromote(Narrow->getOpcode(), WideVT))
24922 // Set N0 and N1 to hold the inputs to the new wide operation.
24923 N0 = N0->getOperand(0);
24924 if (RHSConstSplat) {
24925 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, WideVT.getVectorElementType(),
24926 SDValue(RHSConstSplat, 0));
24927 SmallVector<SDValue, 8> C(WideVT.getVectorNumElements(), N1);
24928 N1 = DAG.getNode(ISD::BUILD_VECTOR, DL, WideVT, C);
24929 } else if (RHSTrunc) {
24930 N1 = N1->getOperand(0);
24933 // Generate the wide operation.
24934 SDValue Op = DAG.getNode(Narrow->getOpcode(), DL, WideVT, N0, N1);
24935 unsigned Opcode = N->getOpcode();
24937 case ISD::ANY_EXTEND:
24939 case ISD::ZERO_EXTEND: {
24940 unsigned InBits = NarrowVT.getScalarSizeInBits();
24941 APInt Mask = APInt::getAllOnesValue(InBits);
24942 Mask = Mask.zext(VT.getScalarSizeInBits());
24943 return DAG.getNode(ISD::AND, DL, VT,
24944 Op, DAG.getConstant(Mask, DL, VT));
24946 case ISD::SIGN_EXTEND:
24947 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT,
24948 Op, DAG.getValueType(NarrowVT));
24950 llvm_unreachable("Unexpected opcode");
24954 static SDValue VectorZextCombine(SDNode *N, SelectionDAG &DAG,
24955 TargetLowering::DAGCombinerInfo &DCI,
24956 const X86Subtarget *Subtarget) {
24957 SDValue N0 = N->getOperand(0);
24958 SDValue N1 = N->getOperand(1);
24961 // A vector zext_in_reg may be represented as a shuffle,
24962 // feeding into a bitcast (this represents anyext) feeding into
24963 // an and with a mask.
24964 // We'd like to try to combine that into a shuffle with zero
24965 // plus a bitcast, removing the and.
24966 if (N0.getOpcode() != ISD::BITCAST ||
24967 N0.getOperand(0).getOpcode() != ISD::VECTOR_SHUFFLE)
24970 // The other side of the AND should be a splat of 2^C, where C
24971 // is the number of bits in the source type.
24972 if (N1.getOpcode() == ISD::BITCAST)
24973 N1 = N1.getOperand(0);
24974 if (N1.getOpcode() != ISD::BUILD_VECTOR)
24976 BuildVectorSDNode *Vector = cast<BuildVectorSDNode>(N1);
24978 ShuffleVectorSDNode *Shuffle = cast<ShuffleVectorSDNode>(N0.getOperand(0));
24979 EVT SrcType = Shuffle->getValueType(0);
24981 // We expect a single-source shuffle
24982 if (Shuffle->getOperand(1)->getOpcode() != ISD::UNDEF)
24985 unsigned SrcSize = SrcType.getScalarSizeInBits();
24987 APInt SplatValue, SplatUndef;
24988 unsigned SplatBitSize;
24990 if (!Vector->isConstantSplat(SplatValue, SplatUndef,
24991 SplatBitSize, HasAnyUndefs))
24994 unsigned ResSize = N1.getValueType().getScalarSizeInBits();
24995 // Make sure the splat matches the mask we expect
24996 if (SplatBitSize > ResSize ||
24997 (SplatValue + 1).exactLogBase2() != (int)SrcSize)
25000 // Make sure the input and output size make sense
25001 if (SrcSize >= ResSize || ResSize % SrcSize)
25004 // We expect a shuffle of the form <0, u, u, u, 1, u, u, u...>
25005 // The number of u's between each two values depends on the ratio between
25006 // the source and dest type.
25007 unsigned ZextRatio = ResSize / SrcSize;
25008 bool IsZext = true;
25009 for (unsigned i = 0; i < SrcType.getVectorNumElements(); ++i) {
25010 if (i % ZextRatio) {
25011 if (Shuffle->getMaskElt(i) > 0) {
25017 if (Shuffle->getMaskElt(i) != (int)(i / ZextRatio)) {
25018 // Expected element number
25028 // Ok, perform the transformation - replace the shuffle with
25029 // a shuffle of the form <0, k, k, k, 1, k, k, k> with zero
25030 // (instead of undef) where the k elements come from the zero vector.
25031 SmallVector<int, 8> Mask;
25032 unsigned NumElems = SrcType.getVectorNumElements();
25033 for (unsigned i = 0; i < NumElems; ++i)
25035 Mask.push_back(NumElems);
25037 Mask.push_back(i / ZextRatio);
25039 SDValue NewShuffle = DAG.getVectorShuffle(Shuffle->getValueType(0), DL,
25040 Shuffle->getOperand(0), DAG.getConstant(0, DL, SrcType), Mask);
25041 return DAG.getBitcast(N0.getValueType(), NewShuffle);
25044 /// If both input operands of a logic op are being cast from floating point
25045 /// types, try to convert this into a floating point logic node to avoid
25046 /// unnecessary moves from SSE to integer registers.
25047 static SDValue convertIntLogicToFPLogic(SDNode *N, SelectionDAG &DAG,
25048 const X86Subtarget *Subtarget) {
25049 unsigned FPOpcode = ISD::DELETED_NODE;
25050 if (N->getOpcode() == ISD::AND)
25051 FPOpcode = X86ISD::FAND;
25052 else if (N->getOpcode() == ISD::OR)
25053 FPOpcode = X86ISD::FOR;
25054 else if (N->getOpcode() == ISD::XOR)
25055 FPOpcode = X86ISD::FXOR;
25057 assert(FPOpcode != ISD::DELETED_NODE &&
25058 "Unexpected input node for FP logic conversion");
25060 EVT VT = N->getValueType(0);
25061 SDValue N0 = N->getOperand(0);
25062 SDValue N1 = N->getOperand(1);
25064 if (N0.getOpcode() == ISD::BITCAST && N1.getOpcode() == ISD::BITCAST &&
25065 ((Subtarget->hasSSE1() && VT == MVT::i32) ||
25066 (Subtarget->hasSSE2() && VT == MVT::i64))) {
25067 SDValue N00 = N0.getOperand(0);
25068 SDValue N10 = N1.getOperand(0);
25069 EVT N00Type = N00.getValueType();
25070 EVT N10Type = N10.getValueType();
25071 if (N00Type.isFloatingPoint() && N10Type.isFloatingPoint()) {
25072 SDValue FPLogic = DAG.getNode(FPOpcode, DL, N00Type, N00, N10);
25073 return DAG.getBitcast(VT, FPLogic);
25079 static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG,
25080 TargetLowering::DAGCombinerInfo &DCI,
25081 const X86Subtarget *Subtarget) {
25082 if (DCI.isBeforeLegalizeOps())
25085 if (SDValue Zext = VectorZextCombine(N, DAG, DCI, Subtarget))
25088 if (SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget))
25091 if (SDValue FPLogic = convertIntLogicToFPLogic(N, DAG, Subtarget))
25094 EVT VT = N->getValueType(0);
25095 SDValue N0 = N->getOperand(0);
25096 SDValue N1 = N->getOperand(1);
25099 // Create BEXTR instructions
25100 // BEXTR is ((X >> imm) & (2**size-1))
25101 if (VT == MVT::i32 || VT == MVT::i64) {
25102 // Check for BEXTR.
25103 if ((Subtarget->hasBMI() || Subtarget->hasTBM()) &&
25104 (N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::SRL)) {
25105 ConstantSDNode *MaskNode = dyn_cast<ConstantSDNode>(N1);
25106 ConstantSDNode *ShiftNode = dyn_cast<ConstantSDNode>(N0.getOperand(1));
25107 if (MaskNode && ShiftNode) {
25108 uint64_t Mask = MaskNode->getZExtValue();
25109 uint64_t Shift = ShiftNode->getZExtValue();
25110 if (isMask_64(Mask)) {
25111 uint64_t MaskSize = countPopulation(Mask);
25112 if (Shift + MaskSize <= VT.getSizeInBits())
25113 return DAG.getNode(X86ISD::BEXTR, DL, VT, N0.getOperand(0),
25114 DAG.getConstant(Shift | (MaskSize << 8), DL,
25123 // Want to form ANDNP nodes:
25124 // 1) In the hopes of then easily combining them with OR and AND nodes
25125 // to form PBLEND/PSIGN.
25126 // 2) To match ANDN packed intrinsics
25127 if (VT != MVT::v2i64 && VT != MVT::v4i64)
25130 // Check LHS for vnot
25131 if (N0.getOpcode() == ISD::XOR &&
25132 //ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode()))
25133 CanFoldXORWithAllOnes(N0.getOperand(1).getNode()))
25134 return DAG.getNode(X86ISD::ANDNP, DL, VT, N0.getOperand(0), N1);
25136 // Check RHS for vnot
25137 if (N1.getOpcode() == ISD::XOR &&
25138 //ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode()))
25139 CanFoldXORWithAllOnes(N1.getOperand(1).getNode()))
25140 return DAG.getNode(X86ISD::ANDNP, DL, VT, N1.getOperand(0), N0);
25145 static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
25146 TargetLowering::DAGCombinerInfo &DCI,
25147 const X86Subtarget *Subtarget) {
25148 if (DCI.isBeforeLegalizeOps())
25151 if (SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget))
25154 if (SDValue FPLogic = convertIntLogicToFPLogic(N, DAG, Subtarget))
25157 SDValue N0 = N->getOperand(0);
25158 SDValue N1 = N->getOperand(1);
25159 EVT VT = N->getValueType(0);
25161 // look for psign/blend
25162 if (VT == MVT::v2i64 || VT == MVT::v4i64) {
25163 if (!Subtarget->hasSSSE3() ||
25164 (VT == MVT::v4i64 && !Subtarget->hasInt256()))
25167 // Canonicalize pandn to RHS
25168 if (N0.getOpcode() == X86ISD::ANDNP)
25170 // or (and (m, y), (pandn m, x))
25171 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::ANDNP) {
25172 SDValue Mask = N1.getOperand(0);
25173 SDValue X = N1.getOperand(1);
25175 if (N0.getOperand(0) == Mask)
25176 Y = N0.getOperand(1);
25177 if (N0.getOperand(1) == Mask)
25178 Y = N0.getOperand(0);
25180 // Check to see if the mask appeared in both the AND and ANDNP and
25184 // Validate that X, Y, and Mask are BIT_CONVERTS, and see through them.
25185 // Look through mask bitcast.
25186 if (Mask.getOpcode() == ISD::BITCAST)
25187 Mask = Mask.getOperand(0);
25188 if (X.getOpcode() == ISD::BITCAST)
25189 X = X.getOperand(0);
25190 if (Y.getOpcode() == ISD::BITCAST)
25191 Y = Y.getOperand(0);
25193 EVT MaskVT = Mask.getValueType();
25195 // Validate that the Mask operand is a vector sra node.
25196 // FIXME: what to do for bytes, since there is a psignb/pblendvb, but
25197 // there is no psrai.b
25198 unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits();
25199 unsigned SraAmt = ~0;
25200 if (Mask.getOpcode() == ISD::SRA) {
25201 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Mask.getOperand(1)))
25202 if (auto *AmtConst = AmtBV->getConstantSplatNode())
25203 SraAmt = AmtConst->getZExtValue();
25204 } else if (Mask.getOpcode() == X86ISD::VSRAI) {
25205 SDValue SraC = Mask.getOperand(1);
25206 SraAmt = cast<ConstantSDNode>(SraC)->getZExtValue();
25208 if ((SraAmt + 1) != EltBits)
25213 // Now we know we at least have a plendvb with the mask val. See if
25214 // we can form a psignb/w/d.
25215 // psign = x.type == y.type == mask.type && y = sub(0, x);
25216 if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X &&
25217 ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) &&
25218 X.getValueType() == MaskVT && Y.getValueType() == MaskVT) {
25219 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
25220 "Unsupported VT for PSIGN");
25221 Mask = DAG.getNode(X86ISD::PSIGN, DL, MaskVT, X, Mask.getOperand(0));
25222 return DAG.getBitcast(VT, Mask);
25224 // PBLENDVB only available on SSE 4.1
25225 if (!Subtarget->hasSSE41())
25228 MVT BlendVT = (VT == MVT::v4i64) ? MVT::v32i8 : MVT::v16i8;
25230 X = DAG.getBitcast(BlendVT, X);
25231 Y = DAG.getBitcast(BlendVT, Y);
25232 Mask = DAG.getBitcast(BlendVT, Mask);
25233 Mask = DAG.getNode(ISD::VSELECT, DL, BlendVT, Mask, Y, X);
25234 return DAG.getBitcast(VT, Mask);
25238 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64)
25241 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
25242 bool OptForSize = DAG.getMachineFunction().getFunction()->optForSize();
25244 // SHLD/SHRD instructions have lower register pressure, but on some
25245 // platforms they have higher latency than the equivalent
25246 // series of shifts/or that would otherwise be generated.
25247 // Don't fold (or (x << c) | (y >> (64 - c))) if SHLD/SHRD instructions
25248 // have higher latencies and we are not optimizing for size.
25249 if (!OptForSize && Subtarget->isSHLDSlow())
25252 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
25254 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
25256 if (!N0.hasOneUse() || !N1.hasOneUse())
25259 SDValue ShAmt0 = N0.getOperand(1);
25260 if (ShAmt0.getValueType() != MVT::i8)
25262 SDValue ShAmt1 = N1.getOperand(1);
25263 if (ShAmt1.getValueType() != MVT::i8)
25265 if (ShAmt0.getOpcode() == ISD::TRUNCATE)
25266 ShAmt0 = ShAmt0.getOperand(0);
25267 if (ShAmt1.getOpcode() == ISD::TRUNCATE)
25268 ShAmt1 = ShAmt1.getOperand(0);
25271 unsigned Opc = X86ISD::SHLD;
25272 SDValue Op0 = N0.getOperand(0);
25273 SDValue Op1 = N1.getOperand(0);
25274 if (ShAmt0.getOpcode() == ISD::SUB) {
25275 Opc = X86ISD::SHRD;
25276 std::swap(Op0, Op1);
25277 std::swap(ShAmt0, ShAmt1);
25280 unsigned Bits = VT.getSizeInBits();
25281 if (ShAmt1.getOpcode() == ISD::SUB) {
25282 SDValue Sum = ShAmt1.getOperand(0);
25283 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) {
25284 SDValue ShAmt1Op1 = ShAmt1.getOperand(1);
25285 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE)
25286 ShAmt1Op1 = ShAmt1Op1.getOperand(0);
25287 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0)
25288 return DAG.getNode(Opc, DL, VT,
25290 DAG.getNode(ISD::TRUNCATE, DL,
25293 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) {
25294 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0);
25296 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits)
25297 return DAG.getNode(Opc, DL, VT,
25298 N0.getOperand(0), N1.getOperand(0),
25299 DAG.getNode(ISD::TRUNCATE, DL,
25306 // Generate NEG and CMOV for integer abs.
25307 static SDValue performIntegerAbsCombine(SDNode *N, SelectionDAG &DAG) {
25308 EVT VT = N->getValueType(0);
25310 // Since X86 does not have CMOV for 8-bit integer, we don't convert
25311 // 8-bit integer abs to NEG and CMOV.
25312 if (VT.isInteger() && VT.getSizeInBits() == 8)
25315 SDValue N0 = N->getOperand(0);
25316 SDValue N1 = N->getOperand(1);
25319 // Check pattern of XOR(ADD(X,Y), Y) where Y is SRA(X, size(X)-1)
25320 // and change it to SUB and CMOV.
25321 if (VT.isInteger() && N->getOpcode() == ISD::XOR &&
25322 N0.getOpcode() == ISD::ADD &&
25323 N0.getOperand(1) == N1 &&
25324 N1.getOpcode() == ISD::SRA &&
25325 N1.getOperand(0) == N0.getOperand(0))
25326 if (ConstantSDNode *Y1C = dyn_cast<ConstantSDNode>(N1.getOperand(1)))
25327 if (Y1C->getAPIntValue() == VT.getSizeInBits()-1) {
25328 // Generate SUB & CMOV.
25329 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, DAG.getVTList(VT, MVT::i32),
25330 DAG.getConstant(0, DL, VT), N0.getOperand(0));
25332 SDValue Ops[] = { N0.getOperand(0), Neg,
25333 DAG.getConstant(X86::COND_GE, DL, MVT::i8),
25334 SDValue(Neg.getNode(), 1) };
25335 return DAG.getNode(X86ISD::CMOV, DL, DAG.getVTList(VT, MVT::Glue), Ops);
25340 // Try to turn tests against the signbit in the form of:
25341 // XOR(TRUNCATE(SRL(X, size(X)-1)), 1)
25344 static SDValue foldXorTruncShiftIntoCmp(SDNode *N, SelectionDAG &DAG) {
25345 // This is only worth doing if the output type is i8.
25346 if (N->getValueType(0) != MVT::i8)
25349 SDValue N0 = N->getOperand(0);
25350 SDValue N1 = N->getOperand(1);
25352 // We should be performing an xor against a truncated shift.
25353 if (N0.getOpcode() != ISD::TRUNCATE || !N0.hasOneUse())
25356 // Make sure we are performing an xor against one.
25357 if (!isOneConstant(N1))
25360 // SetCC on x86 zero extends so only act on this if it's a logical shift.
25361 SDValue Shift = N0.getOperand(0);
25362 if (Shift.getOpcode() != ISD::SRL || !Shift.hasOneUse())
25365 // Make sure we are truncating from one of i16, i32 or i64.
25366 EVT ShiftTy = Shift.getValueType();
25367 if (ShiftTy != MVT::i16 && ShiftTy != MVT::i32 && ShiftTy != MVT::i64)
25370 // Make sure the shift amount extracts the sign bit.
25371 if (!isa<ConstantSDNode>(Shift.getOperand(1)) ||
25372 Shift.getConstantOperandVal(1) != ShiftTy.getSizeInBits() - 1)
25375 // Create a greater-than comparison against -1.
25376 // N.B. Using SETGE against 0 works but we want a canonical looking
25377 // comparison, using SETGT matches up with what TranslateX86CC.
25379 SDValue ShiftOp = Shift.getOperand(0);
25380 EVT ShiftOpTy = ShiftOp.getValueType();
25381 SDValue Cond = DAG.getSetCC(DL, MVT::i8, ShiftOp,
25382 DAG.getConstant(-1, DL, ShiftOpTy), ISD::SETGT);
25386 static SDValue PerformXorCombine(SDNode *N, SelectionDAG &DAG,
25387 TargetLowering::DAGCombinerInfo &DCI,
25388 const X86Subtarget *Subtarget) {
25389 if (DCI.isBeforeLegalizeOps())
25392 if (SDValue RV = foldXorTruncShiftIntoCmp(N, DAG))
25395 if (Subtarget->hasCMov())
25396 if (SDValue RV = performIntegerAbsCombine(N, DAG))
25399 if (SDValue FPLogic = convertIntLogicToFPLogic(N, DAG, Subtarget))
25405 /// This function detects the AVG pattern between vectors of unsigned i8/i16,
25406 /// which is c = (a + b + 1) / 2, and replace this operation with the efficient
25407 /// X86ISD::AVG instruction.
25408 static SDValue detectAVGPattern(SDValue In, EVT VT, SelectionDAG &DAG,
25409 const X86Subtarget *Subtarget, SDLoc DL) {
25410 if (!VT.isVector() || !VT.isSimple())
25412 EVT InVT = In.getValueType();
25413 unsigned NumElems = VT.getVectorNumElements();
25415 EVT ScalarVT = VT.getVectorElementType();
25416 if (!((ScalarVT == MVT::i8 || ScalarVT == MVT::i16) &&
25417 isPowerOf2_32(NumElems)))
25420 // InScalarVT is the intermediate type in AVG pattern and it should be greater
25421 // than the original input type (i8/i16).
25422 EVT InScalarVT = InVT.getVectorElementType();
25423 if (InScalarVT.getSizeInBits() <= ScalarVT.getSizeInBits())
25426 if (Subtarget->hasAVX512()) {
25427 if (VT.getSizeInBits() > 512)
25429 } else if (Subtarget->hasAVX2()) {
25430 if (VT.getSizeInBits() > 256)
25433 if (VT.getSizeInBits() > 128)
25437 // Detect the following pattern:
25439 // %1 = zext <N x i8> %a to <N x i32>
25440 // %2 = zext <N x i8> %b to <N x i32>
25441 // %3 = add nuw nsw <N x i32> %1, <i32 1 x N>
25442 // %4 = add nuw nsw <N x i32> %3, %2
25443 // %5 = lshr <N x i32> %N, <i32 1 x N>
25444 // %6 = trunc <N x i32> %5 to <N x i8>
25446 // In AVX512, the last instruction can also be a trunc store.
25448 if (In.getOpcode() != ISD::SRL)
25451 // A lambda checking the given SDValue is a constant vector and each element
25452 // is in the range [Min, Max].
25453 auto IsConstVectorInRange = [](SDValue V, unsigned Min, unsigned Max) {
25454 BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(V);
25455 if (!BV || !BV->isConstant())
25457 for (unsigned i = 0, e = V.getNumOperands(); i < e; i++) {
25458 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V.getOperand(i));
25461 uint64_t Val = C->getZExtValue();
25462 if (Val < Min || Val > Max)
25468 // Check if each element of the vector is left-shifted by one.
25469 auto LHS = In.getOperand(0);
25470 auto RHS = In.getOperand(1);
25471 if (!IsConstVectorInRange(RHS, 1, 1))
25473 if (LHS.getOpcode() != ISD::ADD)
25476 // Detect a pattern of a + b + 1 where the order doesn't matter.
25477 SDValue Operands[3];
25478 Operands[0] = LHS.getOperand(0);
25479 Operands[1] = LHS.getOperand(1);
25481 // Take care of the case when one of the operands is a constant vector whose
25482 // element is in the range [1, 256].
25483 if (IsConstVectorInRange(Operands[1], 1, ScalarVT == MVT::i8 ? 256 : 65536) &&
25484 Operands[0].getOpcode() == ISD::ZERO_EXTEND &&
25485 Operands[0].getOperand(0).getValueType() == VT) {
25486 // The pattern is detected. Subtract one from the constant vector, then
25487 // demote it and emit X86ISD::AVG instruction.
25488 SDValue One = DAG.getConstant(1, DL, InScalarVT);
25489 SDValue Ones = DAG.getNode(ISD::BUILD_VECTOR, DL, InVT,
25490 SmallVector<SDValue, 8>(NumElems, One));
25491 Operands[1] = DAG.getNode(ISD::SUB, DL, InVT, Operands[1], Ones);
25492 Operands[1] = DAG.getNode(ISD::TRUNCATE, DL, VT, Operands[1]);
25493 return DAG.getNode(X86ISD::AVG, DL, VT, Operands[0].getOperand(0),
25497 if (Operands[0].getOpcode() == ISD::ADD)
25498 std::swap(Operands[0], Operands[1]);
25499 else if (Operands[1].getOpcode() != ISD::ADD)
25501 Operands[2] = Operands[1].getOperand(0);
25502 Operands[1] = Operands[1].getOperand(1);
25504 // Now we have three operands of two additions. Check that one of them is a
25505 // constant vector with ones, and the other two are promoted from i8/i16.
25506 for (int i = 0; i < 3; ++i) {
25507 if (!IsConstVectorInRange(Operands[i], 1, 1))
25509 std::swap(Operands[i], Operands[2]);
25511 // Check if Operands[0] and Operands[1] are results of type promotion.
25512 for (int j = 0; j < 2; ++j)
25513 if (Operands[j].getOpcode() != ISD::ZERO_EXTEND ||
25514 Operands[j].getOperand(0).getValueType() != VT)
25517 // The pattern is detected, emit X86ISD::AVG instruction.
25518 return DAG.getNode(X86ISD::AVG, DL, VT, Operands[0].getOperand(0),
25519 Operands[1].getOperand(0));
25525 static SDValue PerformTRUNCATECombine(SDNode *N, SelectionDAG &DAG,
25526 const X86Subtarget *Subtarget) {
25527 return detectAVGPattern(N->getOperand(0), N->getValueType(0), DAG, Subtarget,
25531 /// PerformLOADCombine - Do target-specific dag combines on LOAD nodes.
25532 static SDValue PerformLOADCombine(SDNode *N, SelectionDAG &DAG,
25533 TargetLowering::DAGCombinerInfo &DCI,
25534 const X86Subtarget *Subtarget) {
25535 LoadSDNode *Ld = cast<LoadSDNode>(N);
25536 EVT RegVT = Ld->getValueType(0);
25537 EVT MemVT = Ld->getMemoryVT();
25539 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
25541 // For chips with slow 32-byte unaligned loads, break the 32-byte operation
25542 // into two 16-byte operations.
25543 ISD::LoadExtType Ext = Ld->getExtensionType();
25545 unsigned AddressSpace = Ld->getAddressSpace();
25546 unsigned Alignment = Ld->getAlignment();
25547 if (RegVT.is256BitVector() && !DCI.isBeforeLegalizeOps() &&
25548 Ext == ISD::NON_EXTLOAD &&
25549 TLI.allowsMemoryAccess(*DAG.getContext(), DAG.getDataLayout(), RegVT,
25550 AddressSpace, Alignment, &Fast) && !Fast) {
25551 unsigned NumElems = RegVT.getVectorNumElements();
25555 SDValue Ptr = Ld->getBasePtr();
25556 SDValue Increment =
25557 DAG.getConstant(16, dl, TLI.getPointerTy(DAG.getDataLayout()));
25559 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
25561 SDValue Load1 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
25562 Ld->getPointerInfo(), Ld->isVolatile(),
25563 Ld->isNonTemporal(), Ld->isInvariant(),
25565 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
25566 SDValue Load2 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
25567 Ld->getPointerInfo(), Ld->isVolatile(),
25568 Ld->isNonTemporal(), Ld->isInvariant(),
25569 std::min(16U, Alignment));
25570 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
25572 Load2.getValue(1));
25574 SDValue NewVec = DAG.getUNDEF(RegVT);
25575 NewVec = Insert128BitVector(NewVec, Load1, 0, DAG, dl);
25576 NewVec = Insert128BitVector(NewVec, Load2, NumElems/2, DAG, dl);
25577 return DCI.CombineTo(N, NewVec, TF, true);
25583 /// PerformMLOADCombine - Resolve extending loads
25584 static SDValue PerformMLOADCombine(SDNode *N, SelectionDAG &DAG,
25585 TargetLowering::DAGCombinerInfo &DCI,
25586 const X86Subtarget *Subtarget) {
25587 MaskedLoadSDNode *Mld = cast<MaskedLoadSDNode>(N);
25588 if (Mld->getExtensionType() != ISD::SEXTLOAD)
25591 EVT VT = Mld->getValueType(0);
25592 unsigned NumElems = VT.getVectorNumElements();
25593 EVT LdVT = Mld->getMemoryVT();
25596 assert(LdVT != VT && "Cannot extend to the same type");
25597 unsigned ToSz = VT.getVectorElementType().getSizeInBits();
25598 unsigned FromSz = LdVT.getVectorElementType().getSizeInBits();
25599 // From, To sizes and ElemCount must be pow of two
25600 assert (isPowerOf2_32(NumElems * FromSz * ToSz) &&
25601 "Unexpected size for extending masked load");
25603 unsigned SizeRatio = ToSz / FromSz;
25604 assert(SizeRatio * NumElems * FromSz == VT.getSizeInBits());
25606 // Create a type on which we perform the shuffle
25607 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
25608 LdVT.getScalarType(), NumElems*SizeRatio);
25609 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
25611 // Convert Src0 value
25612 SDValue WideSrc0 = DAG.getBitcast(WideVecVT, Mld->getSrc0());
25613 if (Mld->getSrc0().getOpcode() != ISD::UNDEF) {
25614 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
25615 for (unsigned i = 0; i != NumElems; ++i)
25616 ShuffleVec[i] = i * SizeRatio;
25618 // Can't shuffle using an illegal type.
25619 assert(DAG.getTargetLoweringInfo().isTypeLegal(WideVecVT) &&
25620 "WideVecVT should be legal");
25621 WideSrc0 = DAG.getVectorShuffle(WideVecVT, dl, WideSrc0,
25622 DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
25624 // Prepare the new mask
25626 SDValue Mask = Mld->getMask();
25627 if (Mask.getValueType() == VT) {
25628 // Mask and original value have the same type
25629 NewMask = DAG.getBitcast(WideVecVT, Mask);
25630 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
25631 for (unsigned i = 0; i != NumElems; ++i)
25632 ShuffleVec[i] = i * SizeRatio;
25633 for (unsigned i = NumElems; i != NumElems * SizeRatio; ++i)
25634 ShuffleVec[i] = NumElems * SizeRatio;
25635 NewMask = DAG.getVectorShuffle(WideVecVT, dl, NewMask,
25636 DAG.getConstant(0, dl, WideVecVT),
25640 assert(Mask.getValueType().getVectorElementType() == MVT::i1);
25641 unsigned WidenNumElts = NumElems*SizeRatio;
25642 unsigned MaskNumElts = VT.getVectorNumElements();
25643 EVT NewMaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
25646 unsigned NumConcat = WidenNumElts / MaskNumElts;
25647 SmallVector<SDValue, 16> Ops(NumConcat);
25648 SDValue ZeroVal = DAG.getConstant(0, dl, Mask.getValueType());
25650 for (unsigned i = 1; i != NumConcat; ++i)
25653 NewMask = DAG.getNode(ISD::CONCAT_VECTORS, dl, NewMaskVT, Ops);
25656 SDValue WideLd = DAG.getMaskedLoad(WideVecVT, dl, Mld->getChain(),
25657 Mld->getBasePtr(), NewMask, WideSrc0,
25658 Mld->getMemoryVT(), Mld->getMemOperand(),
25660 SDValue NewVec = DAG.getNode(X86ISD::VSEXT, dl, VT, WideLd);
25661 return DCI.CombineTo(N, NewVec, WideLd.getValue(1), true);
25663 /// PerformMSTORECombine - Resolve truncating stores
25664 static SDValue PerformMSTORECombine(SDNode *N, SelectionDAG &DAG,
25665 const X86Subtarget *Subtarget) {
25666 MaskedStoreSDNode *Mst = cast<MaskedStoreSDNode>(N);
25667 if (!Mst->isTruncatingStore())
25670 EVT VT = Mst->getValue().getValueType();
25671 unsigned NumElems = VT.getVectorNumElements();
25672 EVT StVT = Mst->getMemoryVT();
25675 assert(StVT != VT && "Cannot truncate to the same type");
25676 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
25677 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
25679 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
25681 // The truncating store is legal in some cases. For example
25682 // vpmovqb, vpmovqw, vpmovqd, vpmovdb, vpmovdw
25683 // are designated for truncate store.
25684 // In this case we don't need any further transformations.
25685 if (TLI.isTruncStoreLegal(VT, StVT))
25688 // From, To sizes and ElemCount must be pow of two
25689 assert (isPowerOf2_32(NumElems * FromSz * ToSz) &&
25690 "Unexpected size for truncating masked store");
25691 // We are going to use the original vector elt for storing.
25692 // Accumulated smaller vector elements must be a multiple of the store size.
25693 assert (((NumElems * FromSz) % ToSz) == 0 &&
25694 "Unexpected ratio for truncating masked store");
25696 unsigned SizeRatio = FromSz / ToSz;
25697 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
25699 // Create a type on which we perform the shuffle
25700 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
25701 StVT.getScalarType(), NumElems*SizeRatio);
25703 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
25705 SDValue WideVec = DAG.getBitcast(WideVecVT, Mst->getValue());
25706 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
25707 for (unsigned i = 0; i != NumElems; ++i)
25708 ShuffleVec[i] = i * SizeRatio;
25710 // Can't shuffle using an illegal type.
25711 assert(DAG.getTargetLoweringInfo().isTypeLegal(WideVecVT) &&
25712 "WideVecVT should be legal");
25714 SDValue TruncatedVal = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
25715 DAG.getUNDEF(WideVecVT),
25719 SDValue Mask = Mst->getMask();
25720 if (Mask.getValueType() == VT) {
25721 // Mask and original value have the same type
25722 NewMask = DAG.getBitcast(WideVecVT, Mask);
25723 for (unsigned i = 0; i != NumElems; ++i)
25724 ShuffleVec[i] = i * SizeRatio;
25725 for (unsigned i = NumElems; i != NumElems*SizeRatio; ++i)
25726 ShuffleVec[i] = NumElems*SizeRatio;
25727 NewMask = DAG.getVectorShuffle(WideVecVT, dl, NewMask,
25728 DAG.getConstant(0, dl, WideVecVT),
25732 assert(Mask.getValueType().getVectorElementType() == MVT::i1);
25733 unsigned WidenNumElts = NumElems*SizeRatio;
25734 unsigned MaskNumElts = VT.getVectorNumElements();
25735 EVT NewMaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
25738 unsigned NumConcat = WidenNumElts / MaskNumElts;
25739 SmallVector<SDValue, 16> Ops(NumConcat);
25740 SDValue ZeroVal = DAG.getConstant(0, dl, Mask.getValueType());
25742 for (unsigned i = 1; i != NumConcat; ++i)
25745 NewMask = DAG.getNode(ISD::CONCAT_VECTORS, dl, NewMaskVT, Ops);
25748 return DAG.getMaskedStore(Mst->getChain(), dl, TruncatedVal,
25749 Mst->getBasePtr(), NewMask, StVT,
25750 Mst->getMemOperand(), false);
25752 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
25753 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
25754 const X86Subtarget *Subtarget) {
25755 StoreSDNode *St = cast<StoreSDNode>(N);
25756 EVT VT = St->getValue().getValueType();
25757 EVT StVT = St->getMemoryVT();
25759 SDValue StoredVal = St->getOperand(1);
25760 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
25762 // If we are saving a concatenation of two XMM registers and 32-byte stores
25763 // are slow, such as on Sandy Bridge, perform two 16-byte stores.
25765 unsigned AddressSpace = St->getAddressSpace();
25766 unsigned Alignment = St->getAlignment();
25767 if (VT.is256BitVector() && StVT == VT &&
25768 TLI.allowsMemoryAccess(*DAG.getContext(), DAG.getDataLayout(), VT,
25769 AddressSpace, Alignment, &Fast) && !Fast) {
25770 unsigned NumElems = VT.getVectorNumElements();
25774 SDValue Value0 = Extract128BitVector(StoredVal, 0, DAG, dl);
25775 SDValue Value1 = Extract128BitVector(StoredVal, NumElems/2, DAG, dl);
25778 DAG.getConstant(16, dl, TLI.getPointerTy(DAG.getDataLayout()));
25779 SDValue Ptr0 = St->getBasePtr();
25780 SDValue Ptr1 = DAG.getNode(ISD::ADD, dl, Ptr0.getValueType(), Ptr0, Stride);
25782 SDValue Ch0 = DAG.getStore(St->getChain(), dl, Value0, Ptr0,
25783 St->getPointerInfo(), St->isVolatile(),
25784 St->isNonTemporal(), Alignment);
25785 SDValue Ch1 = DAG.getStore(St->getChain(), dl, Value1, Ptr1,
25786 St->getPointerInfo(), St->isVolatile(),
25787 St->isNonTemporal(),
25788 std::min(16U, Alignment));
25789 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ch0, Ch1);
25792 // Optimize trunc store (of multiple scalars) to shuffle and store.
25793 // First, pack all of the elements in one place. Next, store to memory
25794 // in fewer chunks.
25795 if (St->isTruncatingStore() && VT.isVector()) {
25796 // Check if we can detect an AVG pattern from the truncation. If yes,
25797 // replace the trunc store by a normal store with the result of X86ISD::AVG
25800 detectAVGPattern(St->getValue(), St->getMemoryVT(), DAG, Subtarget, dl);
25802 return DAG.getStore(St->getChain(), dl, Avg, St->getBasePtr(),
25803 St->getPointerInfo(), St->isVolatile(),
25804 St->isNonTemporal(), St->getAlignment());
25806 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
25807 unsigned NumElems = VT.getVectorNumElements();
25808 assert(StVT != VT && "Cannot truncate to the same type");
25809 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
25810 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
25812 // The truncating store is legal in some cases. For example
25813 // vpmovqb, vpmovqw, vpmovqd, vpmovdb, vpmovdw
25814 // are designated for truncate store.
25815 // In this case we don't need any further transformations.
25816 if (TLI.isTruncStoreLegal(VT, StVT))
25819 // From, To sizes and ElemCount must be pow of two
25820 if (!isPowerOf2_32(NumElems * FromSz * ToSz)) return SDValue();
25821 // We are going to use the original vector elt for storing.
25822 // Accumulated smaller vector elements must be a multiple of the store size.
25823 if (0 != (NumElems * FromSz) % ToSz) return SDValue();
25825 unsigned SizeRatio = FromSz / ToSz;
25827 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
25829 // Create a type on which we perform the shuffle
25830 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
25831 StVT.getScalarType(), NumElems*SizeRatio);
25833 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
25835 SDValue WideVec = DAG.getBitcast(WideVecVT, St->getValue());
25836 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
25837 for (unsigned i = 0; i != NumElems; ++i)
25838 ShuffleVec[i] = i * SizeRatio;
25840 // Can't shuffle using an illegal type.
25841 if (!TLI.isTypeLegal(WideVecVT))
25844 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
25845 DAG.getUNDEF(WideVecVT),
25847 // At this point all of the data is stored at the bottom of the
25848 // register. We now need to save it to mem.
25850 // Find the largest store unit
25851 MVT StoreType = MVT::i8;
25852 for (MVT Tp : MVT::integer_valuetypes()) {
25853 if (TLI.isTypeLegal(Tp) && Tp.getSizeInBits() <= NumElems * ToSz)
25857 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
25858 if (TLI.isTypeLegal(MVT::f64) && StoreType.getSizeInBits() < 64 &&
25859 (64 <= NumElems * ToSz))
25860 StoreType = MVT::f64;
25862 // Bitcast the original vector into a vector of store-size units
25863 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(),
25864 StoreType, VT.getSizeInBits()/StoreType.getSizeInBits());
25865 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits());
25866 SDValue ShuffWide = DAG.getBitcast(StoreVecVT, Shuff);
25867 SmallVector<SDValue, 8> Chains;
25868 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits() / 8, dl,
25869 TLI.getPointerTy(DAG.getDataLayout()));
25870 SDValue Ptr = St->getBasePtr();
25872 // Perform one or more big stores into memory.
25873 for (unsigned i=0, e=(ToSz*NumElems)/StoreType.getSizeInBits(); i!=e; ++i) {
25874 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
25875 StoreType, ShuffWide,
25876 DAG.getIntPtrConstant(i, dl));
25877 SDValue Ch = DAG.getStore(St->getChain(), dl, SubVec, Ptr,
25878 St->getPointerInfo(), St->isVolatile(),
25879 St->isNonTemporal(), St->getAlignment());
25880 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
25881 Chains.push_back(Ch);
25884 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
25887 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
25888 // the FP state in cases where an emms may be missing.
25889 // A preferable solution to the general problem is to figure out the right
25890 // places to insert EMMS. This qualifies as a quick hack.
25892 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
25893 if (VT.getSizeInBits() != 64)
25896 const Function *F = DAG.getMachineFunction().getFunction();
25897 bool NoImplicitFloatOps = F->hasFnAttribute(Attribute::NoImplicitFloat);
25899 !Subtarget->useSoftFloat() && !NoImplicitFloatOps && Subtarget->hasSSE2();
25900 if ((VT.isVector() ||
25901 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
25902 isa<LoadSDNode>(St->getValue()) &&
25903 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
25904 St->getChain().hasOneUse() && !St->isVolatile()) {
25905 SDNode* LdVal = St->getValue().getNode();
25906 LoadSDNode *Ld = nullptr;
25907 int TokenFactorIndex = -1;
25908 SmallVector<SDValue, 8> Ops;
25909 SDNode* ChainVal = St->getChain().getNode();
25910 // Must be a store of a load. We currently handle two cases: the load
25911 // is a direct child, and it's under an intervening TokenFactor. It is
25912 // possible to dig deeper under nested TokenFactors.
25913 if (ChainVal == LdVal)
25914 Ld = cast<LoadSDNode>(St->getChain());
25915 else if (St->getValue().hasOneUse() &&
25916 ChainVal->getOpcode() == ISD::TokenFactor) {
25917 for (unsigned i = 0, e = ChainVal->getNumOperands(); i != e; ++i) {
25918 if (ChainVal->getOperand(i).getNode() == LdVal) {
25919 TokenFactorIndex = i;
25920 Ld = cast<LoadSDNode>(St->getValue());
25922 Ops.push_back(ChainVal->getOperand(i));
25926 if (!Ld || !ISD::isNormalLoad(Ld))
25929 // If this is not the MMX case, i.e. we are just turning i64 load/store
25930 // into f64 load/store, avoid the transformation if there are multiple
25931 // uses of the loaded value.
25932 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
25937 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
25938 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
25940 if (Subtarget->is64Bit() || F64IsLegal) {
25941 MVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
25942 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(),
25943 Ld->getPointerInfo(), Ld->isVolatile(),
25944 Ld->isNonTemporal(), Ld->isInvariant(),
25945 Ld->getAlignment());
25946 SDValue NewChain = NewLd.getValue(1);
25947 if (TokenFactorIndex != -1) {
25948 Ops.push_back(NewChain);
25949 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
25951 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
25952 St->getPointerInfo(),
25953 St->isVolatile(), St->isNonTemporal(),
25954 St->getAlignment());
25957 // Otherwise, lower to two pairs of 32-bit loads / stores.
25958 SDValue LoAddr = Ld->getBasePtr();
25959 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
25960 DAG.getConstant(4, LdDL, MVT::i32));
25962 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
25963 Ld->getPointerInfo(),
25964 Ld->isVolatile(), Ld->isNonTemporal(),
25965 Ld->isInvariant(), Ld->getAlignment());
25966 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
25967 Ld->getPointerInfo().getWithOffset(4),
25968 Ld->isVolatile(), Ld->isNonTemporal(),
25970 MinAlign(Ld->getAlignment(), 4));
25972 SDValue NewChain = LoLd.getValue(1);
25973 if (TokenFactorIndex != -1) {
25974 Ops.push_back(LoLd);
25975 Ops.push_back(HiLd);
25976 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
25979 LoAddr = St->getBasePtr();
25980 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
25981 DAG.getConstant(4, StDL, MVT::i32));
25983 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
25984 St->getPointerInfo(),
25985 St->isVolatile(), St->isNonTemporal(),
25986 St->getAlignment());
25987 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
25988 St->getPointerInfo().getWithOffset(4),
25990 St->isNonTemporal(),
25991 MinAlign(St->getAlignment(), 4));
25992 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
25995 // This is similar to the above case, but here we handle a scalar 64-bit
25996 // integer store that is extracted from a vector on a 32-bit target.
25997 // If we have SSE2, then we can treat it like a floating-point double
25998 // to get past legalization. The execution dependencies fixup pass will
25999 // choose the optimal machine instruction for the store if this really is
26000 // an integer or v2f32 rather than an f64.
26001 if (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit() &&
26002 St->getOperand(1).getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
26003 SDValue OldExtract = St->getOperand(1);
26004 SDValue ExtOp0 = OldExtract.getOperand(0);
26005 unsigned VecSize = ExtOp0.getValueSizeInBits();
26006 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), MVT::f64, VecSize / 64);
26007 SDValue BitCast = DAG.getBitcast(VecVT, ExtOp0);
26008 SDValue NewExtract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
26009 BitCast, OldExtract.getOperand(1));
26010 return DAG.getStore(St->getChain(), dl, NewExtract, St->getBasePtr(),
26011 St->getPointerInfo(), St->isVolatile(),
26012 St->isNonTemporal(), St->getAlignment());
26018 /// Return 'true' if this vector operation is "horizontal"
26019 /// and return the operands for the horizontal operation in LHS and RHS. A
26020 /// horizontal operation performs the binary operation on successive elements
26021 /// of its first operand, then on successive elements of its second operand,
26022 /// returning the resulting values in a vector. For example, if
26023 /// A = < float a0, float a1, float a2, float a3 >
26025 /// B = < float b0, float b1, float b2, float b3 >
26026 /// then the result of doing a horizontal operation on A and B is
26027 /// A horizontal-op B = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >.
26028 /// In short, LHS and RHS are inspected to see if LHS op RHS is of the form
26029 /// A horizontal-op B, for some already available A and B, and if so then LHS is
26030 /// set to A, RHS to B, and the routine returns 'true'.
26031 /// Note that the binary operation should have the property that if one of the
26032 /// operands is UNDEF then the result is UNDEF.
26033 static bool isHorizontalBinOp(SDValue &LHS, SDValue &RHS, bool IsCommutative) {
26034 // Look for the following pattern: if
26035 // A = < float a0, float a1, float a2, float a3 >
26036 // B = < float b0, float b1, float b2, float b3 >
26038 // LHS = VECTOR_SHUFFLE A, B, <0, 2, 4, 6>
26039 // RHS = VECTOR_SHUFFLE A, B, <1, 3, 5, 7>
26040 // then LHS op RHS = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >
26041 // which is A horizontal-op B.
26043 // At least one of the operands should be a vector shuffle.
26044 if (LHS.getOpcode() != ISD::VECTOR_SHUFFLE &&
26045 RHS.getOpcode() != ISD::VECTOR_SHUFFLE)
26048 MVT VT = LHS.getSimpleValueType();
26050 assert((VT.is128BitVector() || VT.is256BitVector()) &&
26051 "Unsupported vector type for horizontal add/sub");
26053 // Handle 128 and 256-bit vector lengths. AVX defines horizontal add/sub to
26054 // operate independently on 128-bit lanes.
26055 unsigned NumElts = VT.getVectorNumElements();
26056 unsigned NumLanes = VT.getSizeInBits()/128;
26057 unsigned NumLaneElts = NumElts / NumLanes;
26058 assert((NumLaneElts % 2 == 0) &&
26059 "Vector type should have an even number of elements in each lane");
26060 unsigned HalfLaneElts = NumLaneElts/2;
26062 // View LHS in the form
26063 // LHS = VECTOR_SHUFFLE A, B, LMask
26064 // If LHS is not a shuffle then pretend it is the shuffle
26065 // LHS = VECTOR_SHUFFLE LHS, undef, <0, 1, ..., N-1>
26066 // NOTE: in what follows a default initialized SDValue represents an UNDEF of
26069 SmallVector<int, 16> LMask(NumElts);
26070 if (LHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
26071 if (LHS.getOperand(0).getOpcode() != ISD::UNDEF)
26072 A = LHS.getOperand(0);
26073 if (LHS.getOperand(1).getOpcode() != ISD::UNDEF)
26074 B = LHS.getOperand(1);
26075 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(LHS.getNode())->getMask();
26076 std::copy(Mask.begin(), Mask.end(), LMask.begin());
26078 if (LHS.getOpcode() != ISD::UNDEF)
26080 for (unsigned i = 0; i != NumElts; ++i)
26084 // Likewise, view RHS in the form
26085 // RHS = VECTOR_SHUFFLE C, D, RMask
26087 SmallVector<int, 16> RMask(NumElts);
26088 if (RHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
26089 if (RHS.getOperand(0).getOpcode() != ISD::UNDEF)
26090 C = RHS.getOperand(0);
26091 if (RHS.getOperand(1).getOpcode() != ISD::UNDEF)
26092 D = RHS.getOperand(1);
26093 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(RHS.getNode())->getMask();
26094 std::copy(Mask.begin(), Mask.end(), RMask.begin());
26096 if (RHS.getOpcode() != ISD::UNDEF)
26098 for (unsigned i = 0; i != NumElts; ++i)
26102 // Check that the shuffles are both shuffling the same vectors.
26103 if (!(A == C && B == D) && !(A == D && B == C))
26106 // If everything is UNDEF then bail out: it would be better to fold to UNDEF.
26107 if (!A.getNode() && !B.getNode())
26110 // If A and B occur in reverse order in RHS, then "swap" them (which means
26111 // rewriting the mask).
26113 ShuffleVectorSDNode::commuteMask(RMask);
26115 // At this point LHS and RHS are equivalent to
26116 // LHS = VECTOR_SHUFFLE A, B, LMask
26117 // RHS = VECTOR_SHUFFLE A, B, RMask
26118 // Check that the masks correspond to performing a horizontal operation.
26119 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
26120 for (unsigned i = 0; i != NumLaneElts; ++i) {
26121 int LIdx = LMask[i+l], RIdx = RMask[i+l];
26123 // Ignore any UNDEF components.
26124 if (LIdx < 0 || RIdx < 0 ||
26125 (!A.getNode() && (LIdx < (int)NumElts || RIdx < (int)NumElts)) ||
26126 (!B.getNode() && (LIdx >= (int)NumElts || RIdx >= (int)NumElts)))
26129 // Check that successive elements are being operated on. If not, this is
26130 // not a horizontal operation.
26131 unsigned Src = (i/HalfLaneElts); // each lane is split between srcs
26132 int Index = 2*(i%HalfLaneElts) + NumElts*Src + l;
26133 if (!(LIdx == Index && RIdx == Index + 1) &&
26134 !(IsCommutative && LIdx == Index + 1 && RIdx == Index))
26139 LHS = A.getNode() ? A : B; // If A is 'UNDEF', use B for it.
26140 RHS = B.getNode() ? B : A; // If B is 'UNDEF', use A for it.
26144 /// Do target-specific dag combines on floating point adds.
26145 static SDValue PerformFADDCombine(SDNode *N, SelectionDAG &DAG,
26146 const X86Subtarget *Subtarget) {
26147 EVT VT = N->getValueType(0);
26148 SDValue LHS = N->getOperand(0);
26149 SDValue RHS = N->getOperand(1);
26151 // Try to synthesize horizontal adds from adds of shuffles.
26152 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
26153 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
26154 isHorizontalBinOp(LHS, RHS, true))
26155 return DAG.getNode(X86ISD::FHADD, SDLoc(N), VT, LHS, RHS);
26159 /// Do target-specific dag combines on floating point subs.
26160 static SDValue PerformFSUBCombine(SDNode *N, SelectionDAG &DAG,
26161 const X86Subtarget *Subtarget) {
26162 EVT VT = N->getValueType(0);
26163 SDValue LHS = N->getOperand(0);
26164 SDValue RHS = N->getOperand(1);
26166 // Try to synthesize horizontal subs from subs of shuffles.
26167 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
26168 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
26169 isHorizontalBinOp(LHS, RHS, false))
26170 return DAG.getNode(X86ISD::FHSUB, SDLoc(N), VT, LHS, RHS);
26174 /// Do target-specific dag combines on floating point negations.
26175 static SDValue PerformFNEGCombine(SDNode *N, SelectionDAG &DAG,
26176 const X86Subtarget *Subtarget) {
26177 EVT VT = N->getValueType(0);
26178 EVT SVT = VT.getScalarType();
26179 SDValue Arg = N->getOperand(0);
26182 // Let legalize expand this if it isn't a legal type yet.
26183 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
26186 // If we're negating a FMUL node on a target with FMA, then we can avoid the
26187 // use of a constant by performing (-0 - A*B) instead.
26188 // FIXME: Check rounding control flags as well once it becomes available.
26189 if (Arg.getOpcode() == ISD::FMUL && (SVT == MVT::f32 || SVT == MVT::f64) &&
26190 Arg->getFlags()->hasNoSignedZeros() && Subtarget->hasAnyFMA()) {
26191 SDValue Zero = DAG.getConstantFP(0.0, DL, VT);
26192 return DAG.getNode(X86ISD::FNMSUB, DL, VT, Arg.getOperand(0),
26193 Arg.getOperand(1), Zero);
26196 // If we're negating a FMA node, then we can adjust the
26197 // instruction to include the extra negation.
26198 if (Arg.hasOneUse()) {
26199 switch (Arg.getOpcode()) {
26200 case X86ISD::FMADD:
26201 return DAG.getNode(X86ISD::FNMSUB, DL, VT, Arg.getOperand(0),
26202 Arg.getOperand(1), Arg.getOperand(2));
26203 case X86ISD::FMSUB:
26204 return DAG.getNode(X86ISD::FNMADD, DL, VT, Arg.getOperand(0),
26205 Arg.getOperand(1), Arg.getOperand(2));
26206 case X86ISD::FNMADD:
26207 return DAG.getNode(X86ISD::FMSUB, DL, VT, Arg.getOperand(0),
26208 Arg.getOperand(1), Arg.getOperand(2));
26209 case X86ISD::FNMSUB:
26210 return DAG.getNode(X86ISD::FMADD, DL, VT, Arg.getOperand(0),
26211 Arg.getOperand(1), Arg.getOperand(2));
26217 /// Do target-specific dag combines on X86ISD::FOR and X86ISD::FXOR nodes.
26218 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG,
26219 const X86Subtarget *Subtarget) {
26220 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
26222 // F[X]OR(0.0, x) -> x
26223 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
26224 if (C->getValueAPF().isPosZero())
26225 return N->getOperand(1);
26227 // F[X]OR(x, 0.0) -> x
26228 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
26229 if (C->getValueAPF().isPosZero())
26230 return N->getOperand(0);
26232 EVT VT = N->getValueType(0);
26233 if (VT.is512BitVector() && !Subtarget->hasDQI()) {
26235 MVT IntScalar = MVT::getIntegerVT(VT.getScalarSizeInBits());
26236 MVT IntVT = MVT::getVectorVT(IntScalar, VT.getVectorNumElements());
26238 SDValue Op0 = DAG.getNode(ISD::BITCAST, dl, IntVT, N->getOperand(0));
26239 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, IntVT, N->getOperand(1));
26240 unsigned IntOpcode = (N->getOpcode() == X86ISD::FOR) ? ISD::OR : ISD::XOR;
26241 SDValue IntOp = DAG.getNode(IntOpcode, dl, IntVT, Op0, Op1);
26242 return DAG.getNode(ISD::BITCAST, dl, VT, IntOp);
26247 /// Do target-specific dag combines on X86ISD::FMIN and X86ISD::FMAX nodes.
26248 static SDValue PerformFMinFMaxCombine(SDNode *N, SelectionDAG &DAG) {
26249 assert(N->getOpcode() == X86ISD::FMIN || N->getOpcode() == X86ISD::FMAX);
26251 // Only perform optimizations if UnsafeMath is used.
26252 if (!DAG.getTarget().Options.UnsafeFPMath)
26255 // If we run in unsafe-math mode, then convert the FMAX and FMIN nodes
26256 // into FMINC and FMAXC, which are Commutative operations.
26257 unsigned NewOp = 0;
26258 switch (N->getOpcode()) {
26259 default: llvm_unreachable("unknown opcode");
26260 case X86ISD::FMIN: NewOp = X86ISD::FMINC; break;
26261 case X86ISD::FMAX: NewOp = X86ISD::FMAXC; break;
26264 return DAG.getNode(NewOp, SDLoc(N), N->getValueType(0),
26265 N->getOperand(0), N->getOperand(1));
26268 /// Do target-specific dag combines on X86ISD::FAND nodes.
26269 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
26270 // FAND(0.0, x) -> 0.0
26271 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
26272 if (C->getValueAPF().isPosZero())
26273 return N->getOperand(0);
26275 // FAND(x, 0.0) -> 0.0
26276 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
26277 if (C->getValueAPF().isPosZero())
26278 return N->getOperand(1);
26283 /// Do target-specific dag combines on X86ISD::FANDN nodes
26284 static SDValue PerformFANDNCombine(SDNode *N, SelectionDAG &DAG) {
26285 // FANDN(0.0, x) -> x
26286 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
26287 if (C->getValueAPF().isPosZero())
26288 return N->getOperand(1);
26290 // FANDN(x, 0.0) -> 0.0
26291 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
26292 if (C->getValueAPF().isPosZero())
26293 return N->getOperand(1);
26298 static SDValue PerformBTCombine(SDNode *N,
26300 TargetLowering::DAGCombinerInfo &DCI) {
26301 // BT ignores high bits in the bit index operand.
26302 SDValue Op1 = N->getOperand(1);
26303 if (Op1.hasOneUse()) {
26304 unsigned BitWidth = Op1.getValueSizeInBits();
26305 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
26306 APInt KnownZero, KnownOne;
26307 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
26308 !DCI.isBeforeLegalizeOps());
26309 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
26310 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
26311 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
26312 DCI.CommitTargetLoweringOpt(TLO);
26317 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
26318 SDValue Op = N->getOperand(0);
26319 if (Op.getOpcode() == ISD::BITCAST)
26320 Op = Op.getOperand(0);
26321 EVT VT = N->getValueType(0), OpVT = Op.getValueType();
26322 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
26323 VT.getVectorElementType().getSizeInBits() ==
26324 OpVT.getVectorElementType().getSizeInBits()) {
26325 return DAG.getNode(ISD::BITCAST, SDLoc(N), VT, Op);
26330 static SDValue PerformSIGN_EXTEND_INREGCombine(SDNode *N, SelectionDAG &DAG,
26331 const X86Subtarget *Subtarget) {
26332 EVT VT = N->getValueType(0);
26333 if (!VT.isVector())
26336 SDValue N0 = N->getOperand(0);
26337 SDValue N1 = N->getOperand(1);
26338 EVT ExtraVT = cast<VTSDNode>(N1)->getVT();
26341 // The SIGN_EXTEND_INREG to v4i64 is expensive operation on the
26342 // both SSE and AVX2 since there is no sign-extended shift right
26343 // operation on a vector with 64-bit elements.
26344 //(sext_in_reg (v4i64 anyext (v4i32 x )), ExtraVT) ->
26345 // (v4i64 sext (v4i32 sext_in_reg (v4i32 x , ExtraVT)))
26346 if (VT == MVT::v4i64 && (N0.getOpcode() == ISD::ANY_EXTEND ||
26347 N0.getOpcode() == ISD::SIGN_EXTEND)) {
26348 SDValue N00 = N0.getOperand(0);
26350 // EXTLOAD has a better solution on AVX2,
26351 // it may be replaced with X86ISD::VSEXT node.
26352 if (N00.getOpcode() == ISD::LOAD && Subtarget->hasInt256())
26353 if (!ISD::isNormalLoad(N00.getNode()))
26356 if (N00.getValueType() == MVT::v4i32 && ExtraVT.getSizeInBits() < 128) {
26357 SDValue Tmp = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v4i32,
26359 return DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i64, Tmp);
26365 /// sext(add_nsw(x, C)) --> add(sext(x), C_sext)
26366 /// Promoting a sign extension ahead of an 'add nsw' exposes opportunities
26367 /// to combine math ops, use an LEA, or use a complex addressing mode. This can
26368 /// eliminate extend, add, and shift instructions.
26369 static SDValue promoteSextBeforeAddNSW(SDNode *Sext, SelectionDAG &DAG,
26370 const X86Subtarget *Subtarget) {
26371 // TODO: This should be valid for other integer types.
26372 EVT VT = Sext->getValueType(0);
26373 if (VT != MVT::i64)
26376 // We need an 'add nsw' feeding into the 'sext'.
26377 SDValue Add = Sext->getOperand(0);
26378 if (Add.getOpcode() != ISD::ADD || !Add->getFlags()->hasNoSignedWrap())
26381 // Having a constant operand to the 'add' ensures that we are not increasing
26382 // the instruction count because the constant is extended for free below.
26383 // A constant operand can also become the displacement field of an LEA.
26384 auto *AddOp1 = dyn_cast<ConstantSDNode>(Add.getOperand(1));
26388 // Don't make the 'add' bigger if there's no hope of combining it with some
26389 // other 'add' or 'shl' instruction.
26390 // TODO: It may be profitable to generate simpler LEA instructions in place
26391 // of single 'add' instructions, but the cost model for selecting an LEA
26392 // currently has a high threshold.
26393 bool HasLEAPotential = false;
26394 for (auto *User : Sext->uses()) {
26395 if (User->getOpcode() == ISD::ADD || User->getOpcode() == ISD::SHL) {
26396 HasLEAPotential = true;
26400 if (!HasLEAPotential)
26403 // Everything looks good, so pull the 'sext' ahead of the 'add'.
26404 int64_t AddConstant = AddOp1->getSExtValue();
26405 SDValue AddOp0 = Add.getOperand(0);
26406 SDValue NewSext = DAG.getNode(ISD::SIGN_EXTEND, SDLoc(Sext), VT, AddOp0);
26407 SDValue NewConstant = DAG.getConstant(AddConstant, SDLoc(Add), VT);
26409 // The wider add is guaranteed to not wrap because both operands are
26412 Flags.setNoSignedWrap(true);
26413 return DAG.getNode(ISD::ADD, SDLoc(Add), VT, NewSext, NewConstant, &Flags);
26416 static SDValue PerformSExtCombine(SDNode *N, SelectionDAG &DAG,
26417 TargetLowering::DAGCombinerInfo &DCI,
26418 const X86Subtarget *Subtarget) {
26419 SDValue N0 = N->getOperand(0);
26420 EVT VT = N->getValueType(0);
26421 EVT SVT = VT.getScalarType();
26422 EVT InVT = N0.getValueType();
26423 EVT InSVT = InVT.getScalarType();
26426 // (i8,i32 sext (sdivrem (i8 x, i8 y)) ->
26427 // (i8,i32 (sdivrem_sext_hreg (i8 x, i8 y)
26428 // This exposes the sext to the sdivrem lowering, so that it directly extends
26429 // from AH (which we otherwise need to do contortions to access).
26430 if (N0.getOpcode() == ISD::SDIVREM && N0.getResNo() == 1 &&
26431 InVT == MVT::i8 && VT == MVT::i32) {
26432 SDVTList NodeTys = DAG.getVTList(MVT::i8, VT);
26433 SDValue R = DAG.getNode(X86ISD::SDIVREM8_SEXT_HREG, DL, NodeTys,
26434 N0.getOperand(0), N0.getOperand(1));
26435 DAG.ReplaceAllUsesOfValueWith(N0.getValue(0), R.getValue(0));
26436 return R.getValue(1);
26439 if (!DCI.isBeforeLegalizeOps()) {
26440 if (InVT == MVT::i1) {
26441 SDValue Zero = DAG.getConstant(0, DL, VT);
26443 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), DL, VT);
26444 return DAG.getNode(ISD::SELECT, DL, VT, N0, AllOnes, Zero);
26449 if (VT.isVector() && Subtarget->hasSSE2()) {
26450 auto ExtendVecSize = [&DAG](SDLoc DL, SDValue N, unsigned Size) {
26451 EVT InVT = N.getValueType();
26452 EVT OutVT = EVT::getVectorVT(*DAG.getContext(), InVT.getScalarType(),
26453 Size / InVT.getScalarSizeInBits());
26454 SmallVector<SDValue, 8> Opnds(Size / InVT.getSizeInBits(),
26455 DAG.getUNDEF(InVT));
26457 return DAG.getNode(ISD::CONCAT_VECTORS, DL, OutVT, Opnds);
26460 // If target-size is less than 128-bits, extend to a type that would extend
26461 // to 128 bits, extend that and extract the original target vector.
26462 if (VT.getSizeInBits() < 128 && !(128 % VT.getSizeInBits()) &&
26463 (SVT == MVT::i64 || SVT == MVT::i32 || SVT == MVT::i16) &&
26464 (InSVT == MVT::i32 || InSVT == MVT::i16 || InSVT == MVT::i8)) {
26465 unsigned Scale = 128 / VT.getSizeInBits();
26467 EVT::getVectorVT(*DAG.getContext(), SVT, 128 / SVT.getSizeInBits());
26468 SDValue Ex = ExtendVecSize(DL, N0, Scale * InVT.getSizeInBits());
26469 SDValue SExt = DAG.getNode(ISD::SIGN_EXTEND, DL, ExVT, Ex);
26470 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, SExt,
26471 DAG.getIntPtrConstant(0, DL));
26474 // If target-size is 128-bits, then convert to ISD::SIGN_EXTEND_VECTOR_INREG
26475 // which ensures lowering to X86ISD::VSEXT (pmovsx*).
26476 if (VT.getSizeInBits() == 128 &&
26477 (SVT == MVT::i64 || SVT == MVT::i32 || SVT == MVT::i16) &&
26478 (InSVT == MVT::i32 || InSVT == MVT::i16 || InSVT == MVT::i8)) {
26479 SDValue ExOp = ExtendVecSize(DL, N0, 128);
26480 return DAG.getSignExtendVectorInReg(ExOp, DL, VT);
26483 // On pre-AVX2 targets, split into 128-bit nodes of
26484 // ISD::SIGN_EXTEND_VECTOR_INREG.
26485 if (!Subtarget->hasInt256() && !(VT.getSizeInBits() % 128) &&
26486 (SVT == MVT::i64 || SVT == MVT::i32 || SVT == MVT::i16) &&
26487 (InSVT == MVT::i32 || InSVT == MVT::i16 || InSVT == MVT::i8)) {
26488 unsigned NumVecs = VT.getSizeInBits() / 128;
26489 unsigned NumSubElts = 128 / SVT.getSizeInBits();
26490 EVT SubVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumSubElts);
26491 EVT InSubVT = EVT::getVectorVT(*DAG.getContext(), InSVT, NumSubElts);
26493 SmallVector<SDValue, 8> Opnds;
26494 for (unsigned i = 0, Offset = 0; i != NumVecs;
26495 ++i, Offset += NumSubElts) {
26496 SDValue SrcVec = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InSubVT, N0,
26497 DAG.getIntPtrConstant(Offset, DL));
26498 SrcVec = ExtendVecSize(DL, SrcVec, 128);
26499 SrcVec = DAG.getSignExtendVectorInReg(SrcVec, DL, SubVT);
26500 Opnds.push_back(SrcVec);
26502 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Opnds);
26506 if (Subtarget->hasAVX() && VT.is256BitVector())
26507 if (SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget))
26510 if (SDValue NewAdd = promoteSextBeforeAddNSW(N, DAG, Subtarget))
26516 static SDValue PerformFMACombine(SDNode *N, SelectionDAG &DAG,
26517 const X86Subtarget* Subtarget) {
26519 EVT VT = N->getValueType(0);
26521 // Let legalize expand this if it isn't a legal type yet.
26522 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
26525 EVT ScalarVT = VT.getScalarType();
26526 if ((ScalarVT != MVT::f32 && ScalarVT != MVT::f64) || !Subtarget->hasAnyFMA())
26529 SDValue A = N->getOperand(0);
26530 SDValue B = N->getOperand(1);
26531 SDValue C = N->getOperand(2);
26533 bool NegA = (A.getOpcode() == ISD::FNEG);
26534 bool NegB = (B.getOpcode() == ISD::FNEG);
26535 bool NegC = (C.getOpcode() == ISD::FNEG);
26537 // Negative multiplication when NegA xor NegB
26538 bool NegMul = (NegA != NegB);
26540 A = A.getOperand(0);
26542 B = B.getOperand(0);
26544 C = C.getOperand(0);
26548 Opcode = (!NegC) ? X86ISD::FMADD : X86ISD::FMSUB;
26550 Opcode = (!NegC) ? X86ISD::FNMADD : X86ISD::FNMSUB;
26552 return DAG.getNode(Opcode, dl, VT, A, B, C);
26555 static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG,
26556 TargetLowering::DAGCombinerInfo &DCI,
26557 const X86Subtarget *Subtarget) {
26558 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) ->
26559 // (and (i32 x86isd::setcc_carry), 1)
26560 // This eliminates the zext. This transformation is necessary because
26561 // ISD::SETCC is always legalized to i8.
26563 SDValue N0 = N->getOperand(0);
26564 EVT VT = N->getValueType(0);
26566 if (N0.getOpcode() == ISD::AND &&
26568 N0.getOperand(0).hasOneUse()) {
26569 SDValue N00 = N0.getOperand(0);
26570 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
26571 if (!isOneConstant(N0.getOperand(1)))
26573 return DAG.getNode(ISD::AND, dl, VT,
26574 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
26575 N00.getOperand(0), N00.getOperand(1)),
26576 DAG.getConstant(1, dl, VT));
26580 if (N0.getOpcode() == ISD::TRUNCATE &&
26582 N0.getOperand(0).hasOneUse()) {
26583 SDValue N00 = N0.getOperand(0);
26584 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
26585 return DAG.getNode(ISD::AND, dl, VT,
26586 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
26587 N00.getOperand(0), N00.getOperand(1)),
26588 DAG.getConstant(1, dl, VT));
26592 if (VT.is256BitVector())
26593 if (SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget))
26596 // (i8,i32 zext (udivrem (i8 x, i8 y)) ->
26597 // (i8,i32 (udivrem_zext_hreg (i8 x, i8 y)
26598 // This exposes the zext to the udivrem lowering, so that it directly extends
26599 // from AH (which we otherwise need to do contortions to access).
26600 if (N0.getOpcode() == ISD::UDIVREM &&
26601 N0.getResNo() == 1 && N0.getValueType() == MVT::i8 &&
26602 (VT == MVT::i32 || VT == MVT::i64)) {
26603 SDVTList NodeTys = DAG.getVTList(MVT::i8, VT);
26604 SDValue R = DAG.getNode(X86ISD::UDIVREM8_ZEXT_HREG, dl, NodeTys,
26605 N0.getOperand(0), N0.getOperand(1));
26606 DAG.ReplaceAllUsesOfValueWith(N0.getValue(0), R.getValue(0));
26607 return R.getValue(1);
26613 // Optimize x == -y --> x+y == 0
26614 // x != -y --> x+y != 0
26615 static SDValue PerformISDSETCCCombine(SDNode *N, SelectionDAG &DAG,
26616 const X86Subtarget* Subtarget) {
26617 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
26618 SDValue LHS = N->getOperand(0);
26619 SDValue RHS = N->getOperand(1);
26620 EVT VT = N->getValueType(0);
26623 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && LHS.getOpcode() == ISD::SUB)
26624 if (isNullConstant(LHS.getOperand(0)) && LHS.hasOneUse()) {
26625 SDValue addV = DAG.getNode(ISD::ADD, DL, LHS.getValueType(), RHS,
26626 LHS.getOperand(1));
26627 return DAG.getSetCC(DL, N->getValueType(0), addV,
26628 DAG.getConstant(0, DL, addV.getValueType()), CC);
26630 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && RHS.getOpcode() == ISD::SUB)
26631 if (isNullConstant(RHS.getOperand(0)) && RHS.hasOneUse()) {
26632 SDValue addV = DAG.getNode(ISD::ADD, DL, RHS.getValueType(), LHS,
26633 RHS.getOperand(1));
26634 return DAG.getSetCC(DL, N->getValueType(0), addV,
26635 DAG.getConstant(0, DL, addV.getValueType()), CC);
26638 if (VT.getScalarType() == MVT::i1 &&
26639 (CC == ISD::SETNE || CC == ISD::SETEQ || ISD::isSignedIntSetCC(CC))) {
26641 (LHS.getOpcode() == ISD::SIGN_EXTEND) &&
26642 (LHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
26643 bool IsVZero1 = ISD::isBuildVectorAllZeros(RHS.getNode());
26645 if (!IsSEXT0 || !IsVZero1) {
26646 // Swap the operands and update the condition code.
26647 std::swap(LHS, RHS);
26648 CC = ISD::getSetCCSwappedOperands(CC);
26650 IsSEXT0 = (LHS.getOpcode() == ISD::SIGN_EXTEND) &&
26651 (LHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
26652 IsVZero1 = ISD::isBuildVectorAllZeros(RHS.getNode());
26655 if (IsSEXT0 && IsVZero1) {
26656 assert(VT == LHS.getOperand(0).getValueType() &&
26657 "Uexpected operand type");
26658 if (CC == ISD::SETGT)
26659 return DAG.getConstant(0, DL, VT);
26660 if (CC == ISD::SETLE)
26661 return DAG.getConstant(1, DL, VT);
26662 if (CC == ISD::SETEQ || CC == ISD::SETGE)
26663 return DAG.getNOT(DL, LHS.getOperand(0), VT);
26665 assert((CC == ISD::SETNE || CC == ISD::SETLT) &&
26666 "Unexpected condition code!");
26667 return LHS.getOperand(0);
26674 static SDValue PerformBLENDICombine(SDNode *N, SelectionDAG &DAG) {
26675 SDValue V0 = N->getOperand(0);
26676 SDValue V1 = N->getOperand(1);
26678 EVT VT = N->getValueType(0);
26680 // Canonicalize a v2f64 blend with a mask of 2 by swapping the vector
26681 // operands and changing the mask to 1. This saves us a bunch of
26682 // pattern-matching possibilities related to scalar math ops in SSE/AVX.
26683 // x86InstrInfo knows how to commute this back after instruction selection
26684 // if it would help register allocation.
26686 // TODO: If optimizing for size or a processor that doesn't suffer from
26687 // partial register update stalls, this should be transformed into a MOVSD
26688 // instruction because a MOVSD is 1-2 bytes smaller than a BLENDPD.
26690 if (VT == MVT::v2f64)
26691 if (auto *Mask = dyn_cast<ConstantSDNode>(N->getOperand(2)))
26692 if (Mask->getZExtValue() == 2 && !isShuffleFoldableLoad(V0)) {
26693 SDValue NewMask = DAG.getConstant(1, DL, MVT::i8);
26694 return DAG.getNode(X86ISD::BLENDI, DL, VT, V1, V0, NewMask);
26700 // Helper function of PerformSETCCCombine. It is to materialize "setb reg"
26701 // as "sbb reg,reg", since it can be extended without zext and produces
26702 // an all-ones bit which is more useful than 0/1 in some cases.
26703 static SDValue MaterializeSETB(SDLoc DL, SDValue EFLAGS, SelectionDAG &DAG,
26706 return DAG.getNode(ISD::AND, DL, VT,
26707 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
26708 DAG.getConstant(X86::COND_B, DL, MVT::i8),
26710 DAG.getConstant(1, DL, VT));
26711 assert (VT == MVT::i1 && "Unexpected type for SECCC node");
26712 return DAG.getNode(ISD::TRUNCATE, DL, MVT::i1,
26713 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
26714 DAG.getConstant(X86::COND_B, DL, MVT::i8),
26718 // Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT
26719 static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG,
26720 TargetLowering::DAGCombinerInfo &DCI,
26721 const X86Subtarget *Subtarget) {
26723 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(0));
26724 SDValue EFLAGS = N->getOperand(1);
26726 if (CC == X86::COND_A) {
26727 // Try to convert COND_A into COND_B in an attempt to facilitate
26728 // materializing "setb reg".
26730 // Do not flip "e > c", where "c" is a constant, because Cmp instruction
26731 // cannot take an immediate as its first operand.
26733 if (EFLAGS.getOpcode() == X86ISD::SUB && EFLAGS.hasOneUse() &&
26734 EFLAGS.getValueType().isInteger() &&
26735 !isa<ConstantSDNode>(EFLAGS.getOperand(1))) {
26736 SDValue NewSub = DAG.getNode(X86ISD::SUB, SDLoc(EFLAGS),
26737 EFLAGS.getNode()->getVTList(),
26738 EFLAGS.getOperand(1), EFLAGS.getOperand(0));
26739 SDValue NewEFLAGS = SDValue(NewSub.getNode(), EFLAGS.getResNo());
26740 return MaterializeSETB(DL, NewEFLAGS, DAG, N->getSimpleValueType(0));
26744 // Materialize "setb reg" as "sbb reg,reg", since it can be extended without
26745 // a zext and produces an all-ones bit which is more useful than 0/1 in some
26747 if (CC == X86::COND_B)
26748 return MaterializeSETB(DL, EFLAGS, DAG, N->getSimpleValueType(0));
26750 if (SDValue Flags = checkBoolTestSetCCCombine(EFLAGS, CC)) {
26751 SDValue Cond = DAG.getConstant(CC, DL, MVT::i8);
26752 return DAG.getNode(X86ISD::SETCC, DL, N->getVTList(), Cond, Flags);
26758 // Optimize branch condition evaluation.
26760 static SDValue PerformBrCondCombine(SDNode *N, SelectionDAG &DAG,
26761 TargetLowering::DAGCombinerInfo &DCI,
26762 const X86Subtarget *Subtarget) {
26764 SDValue Chain = N->getOperand(0);
26765 SDValue Dest = N->getOperand(1);
26766 SDValue EFLAGS = N->getOperand(3);
26767 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(2));
26769 if (SDValue Flags = checkBoolTestSetCCCombine(EFLAGS, CC)) {
26770 SDValue Cond = DAG.getConstant(CC, DL, MVT::i8);
26771 return DAG.getNode(X86ISD::BRCOND, DL, N->getVTList(), Chain, Dest, Cond,
26778 static SDValue performVectorCompareAndMaskUnaryOpCombine(SDNode *N,
26779 SelectionDAG &DAG) {
26780 // Take advantage of vector comparisons producing 0 or -1 in each lane to
26781 // optimize away operation when it's from a constant.
26783 // The general transformation is:
26784 // UNARYOP(AND(VECTOR_CMP(x,y), constant)) -->
26785 // AND(VECTOR_CMP(x,y), constant2)
26786 // constant2 = UNARYOP(constant)
26788 // Early exit if this isn't a vector operation, the operand of the
26789 // unary operation isn't a bitwise AND, or if the sizes of the operations
26790 // aren't the same.
26791 EVT VT = N->getValueType(0);
26792 if (!VT.isVector() || N->getOperand(0)->getOpcode() != ISD::AND ||
26793 N->getOperand(0)->getOperand(0)->getOpcode() != ISD::SETCC ||
26794 VT.getSizeInBits() != N->getOperand(0)->getValueType(0).getSizeInBits())
26797 // Now check that the other operand of the AND is a constant. We could
26798 // make the transformation for non-constant splats as well, but it's unclear
26799 // that would be a benefit as it would not eliminate any operations, just
26800 // perform one more step in scalar code before moving to the vector unit.
26801 if (BuildVectorSDNode *BV =
26802 dyn_cast<BuildVectorSDNode>(N->getOperand(0)->getOperand(1))) {
26803 // Bail out if the vector isn't a constant.
26804 if (!BV->isConstant())
26807 // Everything checks out. Build up the new and improved node.
26809 EVT IntVT = BV->getValueType(0);
26810 // Create a new constant of the appropriate type for the transformed
26812 SDValue SourceConst = DAG.getNode(N->getOpcode(), DL, VT, SDValue(BV, 0));
26813 // The AND node needs bitcasts to/from an integer vector type around it.
26814 SDValue MaskConst = DAG.getBitcast(IntVT, SourceConst);
26815 SDValue NewAnd = DAG.getNode(ISD::AND, DL, IntVT,
26816 N->getOperand(0)->getOperand(0), MaskConst);
26817 SDValue Res = DAG.getBitcast(VT, NewAnd);
26824 static SDValue PerformUINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
26825 const X86Subtarget *Subtarget) {
26826 SDValue Op0 = N->getOperand(0);
26827 EVT VT = N->getValueType(0);
26828 EVT InVT = Op0.getValueType();
26829 EVT InSVT = InVT.getScalarType();
26830 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
26832 // UINT_TO_FP(vXi8) -> SINT_TO_FP(ZEXT(vXi8 to vXi32))
26833 // UINT_TO_FP(vXi16) -> SINT_TO_FP(ZEXT(vXi16 to vXi32))
26834 if (InVT.isVector() && (InSVT == MVT::i8 || InSVT == MVT::i16)) {
26836 EVT DstVT = EVT::getVectorVT(*DAG.getContext(), MVT::i32,
26837 InVT.getVectorNumElements());
26838 SDValue P = DAG.getNode(ISD::ZERO_EXTEND, dl, DstVT, Op0);
26840 if (TLI.isOperationLegal(ISD::UINT_TO_FP, DstVT))
26841 return DAG.getNode(ISD::UINT_TO_FP, dl, VT, P);
26843 return DAG.getNode(ISD::SINT_TO_FP, dl, VT, P);
26849 static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
26850 const X86Subtarget *Subtarget) {
26851 // First try to optimize away the conversion entirely when it's
26852 // conditionally from a constant. Vectors only.
26853 if (SDValue Res = performVectorCompareAndMaskUnaryOpCombine(N, DAG))
26856 // Now move on to more general possibilities.
26857 SDValue Op0 = N->getOperand(0);
26858 EVT VT = N->getValueType(0);
26859 EVT InVT = Op0.getValueType();
26860 EVT InSVT = InVT.getScalarType();
26862 // SINT_TO_FP(vXi8) -> SINT_TO_FP(SEXT(vXi8 to vXi32))
26863 // SINT_TO_FP(vXi16) -> SINT_TO_FP(SEXT(vXi16 to vXi32))
26864 if (InVT.isVector() && (InSVT == MVT::i8 || InSVT == MVT::i16)) {
26866 EVT DstVT = EVT::getVectorVT(*DAG.getContext(), MVT::i32,
26867 InVT.getVectorNumElements());
26868 SDValue P = DAG.getNode(ISD::SIGN_EXTEND, dl, DstVT, Op0);
26869 return DAG.getNode(ISD::SINT_TO_FP, dl, VT, P);
26872 // Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have
26873 // a 32-bit target where SSE doesn't support i64->FP operations.
26874 if (!Subtarget->useSoftFloat() && Op0.getOpcode() == ISD::LOAD) {
26875 LoadSDNode *Ld = cast<LoadSDNode>(Op0.getNode());
26876 EVT LdVT = Ld->getValueType(0);
26878 // This transformation is not supported if the result type is f16
26879 if (VT == MVT::f16)
26882 if (!Ld->isVolatile() && !VT.isVector() &&
26883 ISD::isNON_EXTLoad(Op0.getNode()) && Op0.hasOneUse() &&
26884 !Subtarget->is64Bit() && LdVT == MVT::i64) {
26885 SDValue FILDChain = Subtarget->getTargetLowering()->BuildFILD(
26886 SDValue(N, 0), LdVT, Ld->getChain(), Op0, DAG);
26887 DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), FILDChain.getValue(1));
26894 // Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS
26895 static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG,
26896 X86TargetLowering::DAGCombinerInfo &DCI) {
26897 // If the LHS and RHS of the ADC node are zero, then it can't overflow and
26898 // the result is either zero or one (depending on the input carry bit).
26899 // Strength reduce this down to a "set on carry" aka SETCC_CARRY&1.
26900 if (X86::isZeroNode(N->getOperand(0)) &&
26901 X86::isZeroNode(N->getOperand(1)) &&
26902 // We don't have a good way to replace an EFLAGS use, so only do this when
26904 SDValue(N, 1).use_empty()) {
26906 EVT VT = N->getValueType(0);
26907 SDValue CarryOut = DAG.getConstant(0, DL, N->getValueType(1));
26908 SDValue Res1 = DAG.getNode(ISD::AND, DL, VT,
26909 DAG.getNode(X86ISD::SETCC_CARRY, DL, VT,
26910 DAG.getConstant(X86::COND_B, DL,
26913 DAG.getConstant(1, DL, VT));
26914 return DCI.CombineTo(N, Res1, CarryOut);
26920 // fold (add Y, (sete X, 0)) -> adc 0, Y
26921 // (add Y, (setne X, 0)) -> sbb -1, Y
26922 // (sub (sete X, 0), Y) -> sbb 0, Y
26923 // (sub (setne X, 0), Y) -> adc -1, Y
26924 static SDValue OptimizeConditionalInDecrement(SDNode *N, SelectionDAG &DAG) {
26927 // Look through ZExts.
26928 SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0);
26929 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse())
26932 SDValue SetCC = Ext.getOperand(0);
26933 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse())
26936 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0);
26937 if (CC != X86::COND_E && CC != X86::COND_NE)
26940 SDValue Cmp = SetCC.getOperand(1);
26941 if (Cmp.getOpcode() != X86ISD::CMP || !Cmp.hasOneUse() ||
26942 !X86::isZeroNode(Cmp.getOperand(1)) ||
26943 !Cmp.getOperand(0).getValueType().isInteger())
26946 SDValue CmpOp0 = Cmp.getOperand(0);
26947 SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, CmpOp0,
26948 DAG.getConstant(1, DL, CmpOp0.getValueType()));
26950 SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1);
26951 if (CC == X86::COND_NE)
26952 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB,
26953 DL, OtherVal.getValueType(), OtherVal,
26954 DAG.getConstant(-1ULL, DL, OtherVal.getValueType()),
26956 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC,
26957 DL, OtherVal.getValueType(), OtherVal,
26958 DAG.getConstant(0, DL, OtherVal.getValueType()), NewCmp);
26961 /// PerformADDCombine - Do target-specific dag combines on integer adds.
26962 static SDValue PerformAddCombine(SDNode *N, SelectionDAG &DAG,
26963 const X86Subtarget *Subtarget) {
26964 EVT VT = N->getValueType(0);
26965 SDValue Op0 = N->getOperand(0);
26966 SDValue Op1 = N->getOperand(1);
26968 // Try to synthesize horizontal adds from adds of shuffles.
26969 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
26970 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
26971 isHorizontalBinOp(Op0, Op1, true))
26972 return DAG.getNode(X86ISD::HADD, SDLoc(N), VT, Op0, Op1);
26974 return OptimizeConditionalInDecrement(N, DAG);
26977 static SDValue PerformSubCombine(SDNode *N, SelectionDAG &DAG,
26978 const X86Subtarget *Subtarget) {
26979 SDValue Op0 = N->getOperand(0);
26980 SDValue Op1 = N->getOperand(1);
26982 // X86 can't encode an immediate LHS of a sub. See if we can push the
26983 // negation into a preceding instruction.
26984 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op0)) {
26985 // If the RHS of the sub is a XOR with one use and a constant, invert the
26986 // immediate. Then add one to the LHS of the sub so we can turn
26987 // X-Y -> X+~Y+1, saving one register.
26988 if (Op1->hasOneUse() && Op1.getOpcode() == ISD::XOR &&
26989 isa<ConstantSDNode>(Op1.getOperand(1))) {
26990 APInt XorC = cast<ConstantSDNode>(Op1.getOperand(1))->getAPIntValue();
26991 EVT VT = Op0.getValueType();
26992 SDValue NewXor = DAG.getNode(ISD::XOR, SDLoc(Op1), VT,
26994 DAG.getConstant(~XorC, SDLoc(Op1), VT));
26995 return DAG.getNode(ISD::ADD, SDLoc(N), VT, NewXor,
26996 DAG.getConstant(C->getAPIntValue() + 1, SDLoc(N), VT));
27000 // Try to synthesize horizontal adds from adds of shuffles.
27001 EVT VT = N->getValueType(0);
27002 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
27003 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
27004 isHorizontalBinOp(Op0, Op1, true))
27005 return DAG.getNode(X86ISD::HSUB, SDLoc(N), VT, Op0, Op1);
27007 return OptimizeConditionalInDecrement(N, DAG);
27010 /// performVZEXTCombine - Performs build vector combines
27011 static SDValue performVZEXTCombine(SDNode *N, SelectionDAG &DAG,
27012 TargetLowering::DAGCombinerInfo &DCI,
27013 const X86Subtarget *Subtarget) {
27015 MVT VT = N->getSimpleValueType(0);
27016 SDValue Op = N->getOperand(0);
27017 MVT OpVT = Op.getSimpleValueType();
27018 MVT OpEltVT = OpVT.getVectorElementType();
27019 unsigned InputBits = OpEltVT.getSizeInBits() * VT.getVectorNumElements();
27021 // (vzext (bitcast (vzext (x)) -> (vzext x)
27023 while (V.getOpcode() == ISD::BITCAST)
27024 V = V.getOperand(0);
27026 if (V != Op && V.getOpcode() == X86ISD::VZEXT) {
27027 MVT InnerVT = V.getSimpleValueType();
27028 MVT InnerEltVT = InnerVT.getVectorElementType();
27030 // If the element sizes match exactly, we can just do one larger vzext. This
27031 // is always an exact type match as vzext operates on integer types.
27032 if (OpEltVT == InnerEltVT) {
27033 assert(OpVT == InnerVT && "Types must match for vzext!");
27034 return DAG.getNode(X86ISD::VZEXT, DL, VT, V.getOperand(0));
27037 // The only other way we can combine them is if only a single element of the
27038 // inner vzext is used in the input to the outer vzext.
27039 if (InnerEltVT.getSizeInBits() < InputBits)
27042 // In this case, the inner vzext is completely dead because we're going to
27043 // only look at bits inside of the low element. Just do the outer vzext on
27044 // a bitcast of the input to the inner.
27045 return DAG.getNode(X86ISD::VZEXT, DL, VT, DAG.getBitcast(OpVT, V));
27048 // Check if we can bypass extracting and re-inserting an element of an input
27049 // vector. Essentially:
27050 // (bitcast (sclr2vec (ext_vec_elt x))) -> (bitcast x)
27051 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR &&
27052 V.getOperand(0).getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
27053 V.getOperand(0).getSimpleValueType().getSizeInBits() == InputBits) {
27054 SDValue ExtractedV = V.getOperand(0);
27055 SDValue OrigV = ExtractedV.getOperand(0);
27056 if (isNullConstant(ExtractedV.getOperand(1))) {
27057 MVT OrigVT = OrigV.getSimpleValueType();
27058 // Extract a subvector if necessary...
27059 if (OrigVT.getSizeInBits() > OpVT.getSizeInBits()) {
27060 int Ratio = OrigVT.getSizeInBits() / OpVT.getSizeInBits();
27061 OrigVT = MVT::getVectorVT(OrigVT.getVectorElementType(),
27062 OrigVT.getVectorNumElements() / Ratio);
27063 OrigV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, OrigVT, OrigV,
27064 DAG.getIntPtrConstant(0, DL));
27066 Op = DAG.getBitcast(OpVT, OrigV);
27067 return DAG.getNode(X86ISD::VZEXT, DL, VT, Op);
27074 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
27075 DAGCombinerInfo &DCI) const {
27076 SelectionDAG &DAG = DCI.DAG;
27077 switch (N->getOpcode()) {
27079 case ISD::EXTRACT_VECTOR_ELT:
27080 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, DCI);
27083 case X86ISD::SHRUNKBLEND:
27084 return PerformSELECTCombine(N, DAG, DCI, Subtarget);
27085 case ISD::BITCAST: return PerformBITCASTCombine(N, DAG, Subtarget);
27086 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI, Subtarget);
27087 case ISD::ADD: return PerformAddCombine(N, DAG, Subtarget);
27088 case ISD::SUB: return PerformSubCombine(N, DAG, Subtarget);
27089 case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI);
27090 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
27093 case ISD::SRL: return PerformShiftCombine(N, DAG, DCI, Subtarget);
27094 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget);
27095 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget);
27096 case ISD::XOR: return PerformXorCombine(N, DAG, DCI, Subtarget);
27097 case ISD::LOAD: return PerformLOADCombine(N, DAG, DCI, Subtarget);
27098 case ISD::MLOAD: return PerformMLOADCombine(N, DAG, DCI, Subtarget);
27099 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
27100 case ISD::MSTORE: return PerformMSTORECombine(N, DAG, Subtarget);
27101 case ISD::SINT_TO_FP: return PerformSINT_TO_FPCombine(N, DAG, Subtarget);
27102 case ISD::UINT_TO_FP: return PerformUINT_TO_FPCombine(N, DAG, Subtarget);
27103 case ISD::FADD: return PerformFADDCombine(N, DAG, Subtarget);
27104 case ISD::FSUB: return PerformFSUBCombine(N, DAG, Subtarget);
27105 case ISD::FNEG: return PerformFNEGCombine(N, DAG, Subtarget);
27106 case ISD::TRUNCATE: return PerformTRUNCATECombine(N, DAG, Subtarget);
27108 case X86ISD::FOR: return PerformFORCombine(N, DAG, Subtarget);
27110 case X86ISD::FMAX: return PerformFMinFMaxCombine(N, DAG);
27111 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
27112 case X86ISD::FANDN: return PerformFANDNCombine(N, DAG);
27113 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
27114 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
27115 case ISD::ANY_EXTEND:
27116 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG, DCI, Subtarget);
27117 case ISD::SIGN_EXTEND: return PerformSExtCombine(N, DAG, DCI, Subtarget);
27118 case ISD::SIGN_EXTEND_INREG:
27119 return PerformSIGN_EXTEND_INREGCombine(N, DAG, Subtarget);
27120 case ISD::SETCC: return PerformISDSETCCCombine(N, DAG, Subtarget);
27121 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG, DCI, Subtarget);
27122 case X86ISD::BRCOND: return PerformBrCondCombine(N, DAG, DCI, Subtarget);
27123 case X86ISD::VZEXT: return performVZEXTCombine(N, DAG, DCI, Subtarget);
27124 case X86ISD::SHUFP: // Handle all target specific shuffles
27125 case X86ISD::PALIGNR:
27126 case X86ISD::UNPCKH:
27127 case X86ISD::UNPCKL:
27128 case X86ISD::MOVHLPS:
27129 case X86ISD::MOVLHPS:
27130 case X86ISD::PSHUFB:
27131 case X86ISD::PSHUFD:
27132 case X86ISD::PSHUFHW:
27133 case X86ISD::PSHUFLW:
27134 case X86ISD::MOVSS:
27135 case X86ISD::MOVSD:
27136 case X86ISD::VPERMILPI:
27137 case X86ISD::VPERM2X128:
27138 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget);
27139 case ISD::FMA: return PerformFMACombine(N, DAG, Subtarget);
27140 case X86ISD::BLENDI: return PerformBLENDICombine(N, DAG);
27146 /// isTypeDesirableForOp - Return true if the target has native support for
27147 /// the specified value type and it is 'desirable' to use the type for the
27148 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
27149 /// instruction encodings are longer and some i16 instructions are slow.
27150 bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const {
27151 if (!isTypeLegal(VT))
27153 if (VT != MVT::i16)
27160 case ISD::SIGN_EXTEND:
27161 case ISD::ZERO_EXTEND:
27162 case ISD::ANY_EXTEND:
27175 /// IsDesirableToPromoteOp - This method query the target whether it is
27176 /// beneficial for dag combiner to promote the specified node. If true, it
27177 /// should return the desired promotion type by reference.
27178 bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
27179 EVT VT = Op.getValueType();
27180 if (VT != MVT::i16)
27183 bool Promote = false;
27184 bool Commute = false;
27185 switch (Op.getOpcode()) {
27188 LoadSDNode *LD = cast<LoadSDNode>(Op);
27189 // If the non-extending load has a single use and it's not live out, then it
27190 // might be folded.
27191 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&&
27192 Op.hasOneUse()*/) {
27193 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
27194 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
27195 // The only case where we'd want to promote LOAD (rather then it being
27196 // promoted as an operand is when it's only use is liveout.
27197 if (UI->getOpcode() != ISD::CopyToReg)
27204 case ISD::SIGN_EXTEND:
27205 case ISD::ZERO_EXTEND:
27206 case ISD::ANY_EXTEND:
27211 SDValue N0 = Op.getOperand(0);
27212 // Look out for (store (shl (load), x)).
27213 if (MayFoldLoad(N0) && MayFoldIntoStore(Op))
27226 SDValue N0 = Op.getOperand(0);
27227 SDValue N1 = Op.getOperand(1);
27228 if (!Commute && MayFoldLoad(N1))
27230 // Avoid disabling potential load folding opportunities.
27231 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op)))
27233 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op)))
27243 //===----------------------------------------------------------------------===//
27244 // X86 Inline Assembly Support
27245 //===----------------------------------------------------------------------===//
27247 // Helper to match a string separated by whitespace.
27248 static bool matchAsm(StringRef S, ArrayRef<const char *> Pieces) {
27249 S = S.substr(S.find_first_not_of(" \t")); // Skip leading whitespace.
27251 for (StringRef Piece : Pieces) {
27252 if (!S.startswith(Piece)) // Check if the piece matches.
27255 S = S.substr(Piece.size());
27256 StringRef::size_type Pos = S.find_first_not_of(" \t");
27257 if (Pos == 0) // We matched a prefix.
27266 static bool clobbersFlagRegisters(const SmallVector<StringRef, 4> &AsmPieces) {
27268 if (AsmPieces.size() == 3 || AsmPieces.size() == 4) {
27269 if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{cc}") &&
27270 std::count(AsmPieces.begin(), AsmPieces.end(), "~{flags}") &&
27271 std::count(AsmPieces.begin(), AsmPieces.end(), "~{fpsr}")) {
27273 if (AsmPieces.size() == 3)
27275 else if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{dirflag}"))
27282 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
27283 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
27285 std::string AsmStr = IA->getAsmString();
27287 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
27288 if (!Ty || Ty->getBitWidth() % 16 != 0)
27291 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
27292 SmallVector<StringRef, 4> AsmPieces;
27293 SplitString(AsmStr, AsmPieces, ";\n");
27295 switch (AsmPieces.size()) {
27296 default: return false;
27298 // FIXME: this should verify that we are targeting a 486 or better. If not,
27299 // we will turn this bswap into something that will be lowered to logical
27300 // ops instead of emitting the bswap asm. For now, we don't support 486 or
27301 // lower so don't worry about this.
27303 if (matchAsm(AsmPieces[0], {"bswap", "$0"}) ||
27304 matchAsm(AsmPieces[0], {"bswapl", "$0"}) ||
27305 matchAsm(AsmPieces[0], {"bswapq", "$0"}) ||
27306 matchAsm(AsmPieces[0], {"bswap", "${0:q}"}) ||
27307 matchAsm(AsmPieces[0], {"bswapl", "${0:q}"}) ||
27308 matchAsm(AsmPieces[0], {"bswapq", "${0:q}"})) {
27309 // No need to check constraints, nothing other than the equivalent of
27310 // "=r,0" would be valid here.
27311 return IntrinsicLowering::LowerToByteSwap(CI);
27314 // rorw $$8, ${0:w} --> llvm.bswap.i16
27315 if (CI->getType()->isIntegerTy(16) &&
27316 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
27317 (matchAsm(AsmPieces[0], {"rorw", "$$8,", "${0:w}"}) ||
27318 matchAsm(AsmPieces[0], {"rolw", "$$8,", "${0:w}"}))) {
27320 StringRef ConstraintsStr = IA->getConstraintString();
27321 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
27322 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
27323 if (clobbersFlagRegisters(AsmPieces))
27324 return IntrinsicLowering::LowerToByteSwap(CI);
27328 if (CI->getType()->isIntegerTy(32) &&
27329 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
27330 matchAsm(AsmPieces[0], {"rorw", "$$8,", "${0:w}"}) &&
27331 matchAsm(AsmPieces[1], {"rorl", "$$16,", "$0"}) &&
27332 matchAsm(AsmPieces[2], {"rorw", "$$8,", "${0:w}"})) {
27334 StringRef ConstraintsStr = IA->getConstraintString();
27335 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
27336 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
27337 if (clobbersFlagRegisters(AsmPieces))
27338 return IntrinsicLowering::LowerToByteSwap(CI);
27341 if (CI->getType()->isIntegerTy(64)) {
27342 InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints();
27343 if (Constraints.size() >= 2 &&
27344 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
27345 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
27346 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
27347 if (matchAsm(AsmPieces[0], {"bswap", "%eax"}) &&
27348 matchAsm(AsmPieces[1], {"bswap", "%edx"}) &&
27349 matchAsm(AsmPieces[2], {"xchgl", "%eax,", "%edx"}))
27350 return IntrinsicLowering::LowerToByteSwap(CI);
27358 /// getConstraintType - Given a constraint letter, return the type of
27359 /// constraint it is for this target.
27360 X86TargetLowering::ConstraintType
27361 X86TargetLowering::getConstraintType(StringRef Constraint) const {
27362 if (Constraint.size() == 1) {
27363 switch (Constraint[0]) {
27374 return C_RegisterClass;
27398 return TargetLowering::getConstraintType(Constraint);
27401 /// Examine constraint type and operand type and determine a weight value.
27402 /// This object must already have been set up with the operand type
27403 /// and the current alternative constraint selected.
27404 TargetLowering::ConstraintWeight
27405 X86TargetLowering::getSingleConstraintMatchWeight(
27406 AsmOperandInfo &info, const char *constraint) const {
27407 ConstraintWeight weight = CW_Invalid;
27408 Value *CallOperandVal = info.CallOperandVal;
27409 // If we don't have a value, we can't do a match,
27410 // but allow it at the lowest weight.
27411 if (!CallOperandVal)
27413 Type *type = CallOperandVal->getType();
27414 // Look at the constraint type.
27415 switch (*constraint) {
27417 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
27428 if (CallOperandVal->getType()->isIntegerTy())
27429 weight = CW_SpecificReg;
27434 if (type->isFloatingPointTy())
27435 weight = CW_SpecificReg;
27438 if (type->isX86_MMXTy() && Subtarget->hasMMX())
27439 weight = CW_SpecificReg;
27443 if (((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasSSE1()) ||
27444 ((type->getPrimitiveSizeInBits() == 256) && Subtarget->hasFp256()))
27445 weight = CW_Register;
27448 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) {
27449 if (C->getZExtValue() <= 31)
27450 weight = CW_Constant;
27454 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
27455 if (C->getZExtValue() <= 63)
27456 weight = CW_Constant;
27460 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
27461 if ((C->getSExtValue() >= -0x80) && (C->getSExtValue() <= 0x7f))
27462 weight = CW_Constant;
27466 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
27467 if ((C->getZExtValue() == 0xff) || (C->getZExtValue() == 0xffff))
27468 weight = CW_Constant;
27472 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
27473 if (C->getZExtValue() <= 3)
27474 weight = CW_Constant;
27478 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
27479 if (C->getZExtValue() <= 0xff)
27480 weight = CW_Constant;
27485 if (isa<ConstantFP>(CallOperandVal)) {
27486 weight = CW_Constant;
27490 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
27491 if ((C->getSExtValue() >= -0x80000000LL) &&
27492 (C->getSExtValue() <= 0x7fffffffLL))
27493 weight = CW_Constant;
27497 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
27498 if (C->getZExtValue() <= 0xffffffff)
27499 weight = CW_Constant;
27506 /// LowerXConstraint - try to replace an X constraint, which matches anything,
27507 /// with another that has more specific requirements based on the type of the
27508 /// corresponding operand.
27509 const char *X86TargetLowering::
27510 LowerXConstraint(EVT ConstraintVT) const {
27511 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
27512 // 'f' like normal targets.
27513 if (ConstraintVT.isFloatingPoint()) {
27514 if (Subtarget->hasSSE2())
27516 if (Subtarget->hasSSE1())
27520 return TargetLowering::LowerXConstraint(ConstraintVT);
27523 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
27524 /// vector. If it is invalid, don't add anything to Ops.
27525 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
27526 std::string &Constraint,
27527 std::vector<SDValue>&Ops,
27528 SelectionDAG &DAG) const {
27531 // Only support length 1 constraints for now.
27532 if (Constraint.length() > 1) return;
27534 char ConstraintLetter = Constraint[0];
27535 switch (ConstraintLetter) {
27538 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
27539 if (C->getZExtValue() <= 31) {
27540 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
27541 Op.getValueType());
27547 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
27548 if (C->getZExtValue() <= 63) {
27549 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
27550 Op.getValueType());
27556 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
27557 if (isInt<8>(C->getSExtValue())) {
27558 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
27559 Op.getValueType());
27565 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
27566 if (C->getZExtValue() == 0xff || C->getZExtValue() == 0xffff ||
27567 (Subtarget->is64Bit() && C->getZExtValue() == 0xffffffff)) {
27568 Result = DAG.getTargetConstant(C->getSExtValue(), SDLoc(Op),
27569 Op.getValueType());
27575 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
27576 if (C->getZExtValue() <= 3) {
27577 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
27578 Op.getValueType());
27584 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
27585 if (C->getZExtValue() <= 255) {
27586 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
27587 Op.getValueType());
27593 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
27594 if (C->getZExtValue() <= 127) {
27595 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
27596 Op.getValueType());
27602 // 32-bit signed value
27603 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
27604 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
27605 C->getSExtValue())) {
27606 // Widen to 64 bits here to get it sign extended.
27607 Result = DAG.getTargetConstant(C->getSExtValue(), SDLoc(Op), MVT::i64);
27610 // FIXME gcc accepts some relocatable values here too, but only in certain
27611 // memory models; it's complicated.
27616 // 32-bit unsigned value
27617 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
27618 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
27619 C->getZExtValue())) {
27620 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
27621 Op.getValueType());
27625 // FIXME gcc accepts some relocatable values here too, but only in certain
27626 // memory models; it's complicated.
27630 // Literal immediates are always ok.
27631 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
27632 // Widen to 64 bits here to get it sign extended.
27633 Result = DAG.getTargetConstant(CST->getSExtValue(), SDLoc(Op), MVT::i64);
27637 // In any sort of PIC mode addresses need to be computed at runtime by
27638 // adding in a register or some sort of table lookup. These can't
27639 // be used as immediates.
27640 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC())
27643 // If we are in non-pic codegen mode, we allow the address of a global (with
27644 // an optional displacement) to be used with 'i'.
27645 GlobalAddressSDNode *GA = nullptr;
27646 int64_t Offset = 0;
27648 // Match either (GA), (GA+C), (GA+C1+C2), etc.
27650 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
27651 Offset += GA->getOffset();
27653 } else if (Op.getOpcode() == ISD::ADD) {
27654 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
27655 Offset += C->getZExtValue();
27656 Op = Op.getOperand(0);
27659 } else if (Op.getOpcode() == ISD::SUB) {
27660 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
27661 Offset += -C->getZExtValue();
27662 Op = Op.getOperand(0);
27667 // Otherwise, this isn't something we can handle, reject it.
27671 const GlobalValue *GV = GA->getGlobal();
27672 // If we require an extra load to get this address, as in PIC mode, we
27673 // can't accept it.
27674 if (isGlobalStubReference(
27675 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget())))
27678 Result = DAG.getTargetGlobalAddress(GV, SDLoc(Op),
27679 GA->getValueType(0), Offset);
27684 if (Result.getNode()) {
27685 Ops.push_back(Result);
27688 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
27691 std::pair<unsigned, const TargetRegisterClass *>
27692 X86TargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
27693 StringRef Constraint,
27695 // First, see if this is a constraint that directly corresponds to an LLVM
27697 if (Constraint.size() == 1) {
27698 // GCC Constraint Letters
27699 switch (Constraint[0]) {
27701 // TODO: Slight differences here in allocation order and leaving
27702 // RIP in the class. Do they matter any more here than they do
27703 // in the normal allocation?
27704 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
27705 if (Subtarget->is64Bit()) {
27706 if (VT == MVT::i32 || VT == MVT::f32)
27707 return std::make_pair(0U, &X86::GR32RegClass);
27708 if (VT == MVT::i16)
27709 return std::make_pair(0U, &X86::GR16RegClass);
27710 if (VT == MVT::i8 || VT == MVT::i1)
27711 return std::make_pair(0U, &X86::GR8RegClass);
27712 if (VT == MVT::i64 || VT == MVT::f64)
27713 return std::make_pair(0U, &X86::GR64RegClass);
27716 // 32-bit fallthrough
27717 case 'Q': // Q_REGS
27718 if (VT == MVT::i32 || VT == MVT::f32)
27719 return std::make_pair(0U, &X86::GR32_ABCDRegClass);
27720 if (VT == MVT::i16)
27721 return std::make_pair(0U, &X86::GR16_ABCDRegClass);
27722 if (VT == MVT::i8 || VT == MVT::i1)
27723 return std::make_pair(0U, &X86::GR8_ABCD_LRegClass);
27724 if (VT == MVT::i64)
27725 return std::make_pair(0U, &X86::GR64_ABCDRegClass);
27727 case 'r': // GENERAL_REGS
27728 case 'l': // INDEX_REGS
27729 if (VT == MVT::i8 || VT == MVT::i1)
27730 return std::make_pair(0U, &X86::GR8RegClass);
27731 if (VT == MVT::i16)
27732 return std::make_pair(0U, &X86::GR16RegClass);
27733 if (VT == MVT::i32 || VT == MVT::f32 || !Subtarget->is64Bit())
27734 return std::make_pair(0U, &X86::GR32RegClass);
27735 return std::make_pair(0U, &X86::GR64RegClass);
27736 case 'R': // LEGACY_REGS
27737 if (VT == MVT::i8 || VT == MVT::i1)
27738 return std::make_pair(0U, &X86::GR8_NOREXRegClass);
27739 if (VT == MVT::i16)
27740 return std::make_pair(0U, &X86::GR16_NOREXRegClass);
27741 if (VT == MVT::i32 || !Subtarget->is64Bit())
27742 return std::make_pair(0U, &X86::GR32_NOREXRegClass);
27743 return std::make_pair(0U, &X86::GR64_NOREXRegClass);
27744 case 'f': // FP Stack registers.
27745 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
27746 // value to the correct fpstack register class.
27747 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
27748 return std::make_pair(0U, &X86::RFP32RegClass);
27749 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
27750 return std::make_pair(0U, &X86::RFP64RegClass);
27751 return std::make_pair(0U, &X86::RFP80RegClass);
27752 case 'y': // MMX_REGS if MMX allowed.
27753 if (!Subtarget->hasMMX()) break;
27754 return std::make_pair(0U, &X86::VR64RegClass);
27755 case 'Y': // SSE_REGS if SSE2 allowed
27756 if (!Subtarget->hasSSE2()) break;
27758 case 'x': // SSE_REGS if SSE1 allowed or AVX_REGS if AVX allowed
27759 if (!Subtarget->hasSSE1()) break;
27761 switch (VT.SimpleTy) {
27763 // Scalar SSE types.
27766 return std::make_pair(0U, &X86::FR32RegClass);
27769 return std::make_pair(0U, &X86::FR64RegClass);
27777 return std::make_pair(0U, &X86::VR128RegClass);
27785 return std::make_pair(0U, &X86::VR256RegClass);
27790 return std::make_pair(0U, &X86::VR512RegClass);
27796 // Use the default implementation in TargetLowering to convert the register
27797 // constraint into a member of a register class.
27798 std::pair<unsigned, const TargetRegisterClass*> Res;
27799 Res = TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
27801 // Not found as a standard register?
27803 // Map st(0) -> st(7) -> ST0
27804 if (Constraint.size() == 7 && Constraint[0] == '{' &&
27805 tolower(Constraint[1]) == 's' &&
27806 tolower(Constraint[2]) == 't' &&
27807 Constraint[3] == '(' &&
27808 (Constraint[4] >= '0' && Constraint[4] <= '7') &&
27809 Constraint[5] == ')' &&
27810 Constraint[6] == '}') {
27812 Res.first = X86::FP0+Constraint[4]-'0';
27813 Res.second = &X86::RFP80RegClass;
27817 // GCC allows "st(0)" to be called just plain "st".
27818 if (StringRef("{st}").equals_lower(Constraint)) {
27819 Res.first = X86::FP0;
27820 Res.second = &X86::RFP80RegClass;
27825 if (StringRef("{flags}").equals_lower(Constraint)) {
27826 Res.first = X86::EFLAGS;
27827 Res.second = &X86::CCRRegClass;
27831 // 'A' means EAX + EDX.
27832 if (Constraint == "A") {
27833 Res.first = X86::EAX;
27834 Res.second = &X86::GR32_ADRegClass;
27840 // Otherwise, check to see if this is a register class of the wrong value
27841 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
27842 // turn into {ax},{dx}.
27843 // MVT::Other is used to specify clobber names.
27844 if (Res.second->hasType(VT) || VT == MVT::Other)
27845 return Res; // Correct type already, nothing to do.
27847 // Get a matching integer of the correct size. i.e. "ax" with MVT::32 should
27848 // return "eax". This should even work for things like getting 64bit integer
27849 // registers when given an f64 type.
27850 const TargetRegisterClass *Class = Res.second;
27851 if (Class == &X86::GR8RegClass || Class == &X86::GR16RegClass ||
27852 Class == &X86::GR32RegClass || Class == &X86::GR64RegClass) {
27853 unsigned Size = VT.getSizeInBits();
27854 MVT::SimpleValueType SimpleTy = Size == 1 || Size == 8 ? MVT::i8
27855 : Size == 16 ? MVT::i16
27856 : Size == 32 ? MVT::i32
27857 : Size == 64 ? MVT::i64
27859 unsigned DestReg = getX86SubSuperRegisterOrZero(Res.first, SimpleTy);
27861 Res.first = DestReg;
27862 Res.second = SimpleTy == MVT::i8 ? &X86::GR8RegClass
27863 : SimpleTy == MVT::i16 ? &X86::GR16RegClass
27864 : SimpleTy == MVT::i32 ? &X86::GR32RegClass
27865 : &X86::GR64RegClass;
27866 assert(Res.second->contains(Res.first) && "Register in register class");
27868 // No register found/type mismatch.
27870 Res.second = nullptr;
27872 } else if (Class == &X86::FR32RegClass || Class == &X86::FR64RegClass ||
27873 Class == &X86::VR128RegClass || Class == &X86::VR256RegClass ||
27874 Class == &X86::FR32XRegClass || Class == &X86::FR64XRegClass ||
27875 Class == &X86::VR128XRegClass || Class == &X86::VR256XRegClass ||
27876 Class == &X86::VR512RegClass) {
27877 // Handle references to XMM physical registers that got mapped into the
27878 // wrong class. This can happen with constraints like {xmm0} where the
27879 // target independent register mapper will just pick the first match it can
27880 // find, ignoring the required type.
27882 if (VT == MVT::f32 || VT == MVT::i32)
27883 Res.second = &X86::FR32RegClass;
27884 else if (VT == MVT::f64 || VT == MVT::i64)
27885 Res.second = &X86::FR64RegClass;
27886 else if (X86::VR128RegClass.hasType(VT))
27887 Res.second = &X86::VR128RegClass;
27888 else if (X86::VR256RegClass.hasType(VT))
27889 Res.second = &X86::VR256RegClass;
27890 else if (X86::VR512RegClass.hasType(VT))
27891 Res.second = &X86::VR512RegClass;
27893 // Type mismatch and not a clobber: Return an error;
27895 Res.second = nullptr;
27902 int X86TargetLowering::getScalingFactorCost(const DataLayout &DL,
27903 const AddrMode &AM, Type *Ty,
27904 unsigned AS) const {
27905 // Scaling factors are not free at all.
27906 // An indexed folded instruction, i.e., inst (reg1, reg2, scale),
27907 // will take 2 allocations in the out of order engine instead of 1
27908 // for plain addressing mode, i.e. inst (reg1).
27910 // vaddps (%rsi,%drx), %ymm0, %ymm1
27911 // Requires two allocations (one for the load, one for the computation)
27913 // vaddps (%rsi), %ymm0, %ymm1
27914 // Requires just 1 allocation, i.e., freeing allocations for other operations
27915 // and having less micro operations to execute.
27917 // For some X86 architectures, this is even worse because for instance for
27918 // stores, the complex addressing mode forces the instruction to use the
27919 // "load" ports instead of the dedicated "store" port.
27920 // E.g., on Haswell:
27921 // vmovaps %ymm1, (%r8, %rdi) can use port 2 or 3.
27922 // vmovaps %ymm1, (%r8) can use port 2, 3, or 7.
27923 if (isLegalAddressingMode(DL, AM, Ty, AS))
27924 // Scale represents reg2 * scale, thus account for 1
27925 // as soon as we use a second register.
27926 return AM.Scale != 0;
27930 bool X86TargetLowering::isIntDivCheap(EVT VT, AttributeSet Attr) const {
27931 // Integer division on x86 is expensive. However, when aggressively optimizing
27932 // for code size, we prefer to use a div instruction, as it is usually smaller
27933 // than the alternative sequence.
27934 // The exception to this is vector division. Since x86 doesn't have vector
27935 // integer division, leaving the division as-is is a loss even in terms of
27936 // size, because it will have to be scalarized, while the alternative code
27937 // sequence can be performed in vector form.
27938 bool OptSize = Attr.hasAttribute(AttributeSet::FunctionIndex,
27939 Attribute::MinSize);
27940 return OptSize && !VT.isVector();
27943 void X86TargetLowering::markInRegArguments(SelectionDAG &DAG,
27944 TargetLowering::ArgListTy& Args) const {
27945 // The MCU psABI requires some arguments to be passed in-register.
27946 // For regular calls, the inreg arguments are marked by the front-end.
27947 // However, for compiler generated library calls, we have to patch this
27949 if (!Subtarget->isTargetMCU() || !Args.size())
27952 unsigned FreeRegs = 3;
27953 for (auto &Arg : Args) {
27954 // For library functions, we do not expect any fancy types.
27955 unsigned Size = DAG.getDataLayout().getTypeSizeInBits(Arg.Ty);
27956 unsigned SizeInRegs = (Size + 31) / 32;
27957 if (SizeInRegs > 2 || SizeInRegs > FreeRegs)
27960 Arg.isInReg = true;
27961 FreeRegs -= SizeInRegs;