1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #include "X86ISelLowering.h"
16 #include "Utils/X86ShuffleDecode.h"
17 #include "X86CallingConv.h"
18 #include "X86FrameLowering.h"
19 #include "X86InstrBuilder.h"
20 #include "X86MachineFunctionInfo.h"
21 #include "X86TargetMachine.h"
22 #include "X86TargetObjectFile.h"
23 #include "llvm/ADT/SmallBitVector.h"
24 #include "llvm/ADT/SmallSet.h"
25 #include "llvm/ADT/Statistic.h"
26 #include "llvm/ADT/StringExtras.h"
27 #include "llvm/ADT/StringSwitch.h"
28 #include "llvm/Analysis/LibCallSemantics.h"
29 #include "llvm/CodeGen/IntrinsicLowering.h"
30 #include "llvm/CodeGen/MachineFrameInfo.h"
31 #include "llvm/CodeGen/MachineFunction.h"
32 #include "llvm/CodeGen/MachineInstrBuilder.h"
33 #include "llvm/CodeGen/MachineJumpTableInfo.h"
34 #include "llvm/CodeGen/MachineModuleInfo.h"
35 #include "llvm/CodeGen/MachineRegisterInfo.h"
36 #include "llvm/CodeGen/WinEHFuncInfo.h"
37 #include "llvm/IR/CallSite.h"
38 #include "llvm/IR/CallingConv.h"
39 #include "llvm/IR/Constants.h"
40 #include "llvm/IR/DerivedTypes.h"
41 #include "llvm/IR/Function.h"
42 #include "llvm/IR/GlobalAlias.h"
43 #include "llvm/IR/GlobalVariable.h"
44 #include "llvm/IR/Instructions.h"
45 #include "llvm/IR/Intrinsics.h"
46 #include "llvm/MC/MCAsmInfo.h"
47 #include "llvm/MC/MCContext.h"
48 #include "llvm/MC/MCExpr.h"
49 #include "llvm/MC/MCSymbol.h"
50 #include "llvm/Support/CommandLine.h"
51 #include "llvm/Support/Debug.h"
52 #include "llvm/Support/ErrorHandling.h"
53 #include "llvm/Support/MathExtras.h"
54 #include "llvm/Target/TargetOptions.h"
55 #include "X86IntrinsicsInfo.h"
61 #define DEBUG_TYPE "x86-isel"
63 STATISTIC(NumTailCalls, "Number of tail calls");
65 static cl::opt<bool> ExperimentalVectorWideningLegalization(
66 "x86-experimental-vector-widening-legalization", cl::init(false),
67 cl::desc("Enable an experimental vector type legalization through widening "
68 "rather than promotion."),
71 X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
72 const X86Subtarget &STI)
73 : TargetLowering(TM), Subtarget(&STI) {
74 X86ScalarSSEf64 = Subtarget->hasSSE2();
75 X86ScalarSSEf32 = Subtarget->hasSSE1();
76 MVT PtrVT = MVT::getIntegerVT(8 * TM.getPointerSize());
78 // Set up the TargetLowering object.
80 // X86 is weird. It always uses i8 for shift amounts and setcc results.
81 setBooleanContents(ZeroOrOneBooleanContent);
82 // X86-SSE is even stranger. It uses -1 or 0 for vector masks.
83 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
85 // For 64-bit, since we have so many registers, use the ILP scheduler.
86 // For 32-bit, use the register pressure specific scheduling.
87 // For Atom, always use ILP scheduling.
88 if (Subtarget->isAtom())
89 setSchedulingPreference(Sched::ILP);
90 else if (Subtarget->is64Bit())
91 setSchedulingPreference(Sched::ILP);
93 setSchedulingPreference(Sched::RegPressure);
94 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
95 setStackPointerRegisterToSaveRestore(RegInfo->getStackRegister());
97 // Bypass expensive divides on Atom when compiling with O2.
98 if (TM.getOptLevel() >= CodeGenOpt::Default) {
99 if (Subtarget->hasSlowDivide32())
100 addBypassSlowDiv(32, 8);
101 if (Subtarget->hasSlowDivide64() && Subtarget->is64Bit())
102 addBypassSlowDiv(64, 16);
105 if (Subtarget->isTargetKnownWindowsMSVC()) {
106 // Setup Windows compiler runtime calls.
107 setLibcallName(RTLIB::SDIV_I64, "_alldiv");
108 setLibcallName(RTLIB::UDIV_I64, "_aulldiv");
109 setLibcallName(RTLIB::SREM_I64, "_allrem");
110 setLibcallName(RTLIB::UREM_I64, "_aullrem");
111 setLibcallName(RTLIB::MUL_I64, "_allmul");
112 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall);
113 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall);
114 setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::X86_StdCall);
115 setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::X86_StdCall);
116 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::X86_StdCall);
119 if (Subtarget->isTargetDarwin()) {
120 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
121 setUseUnderscoreSetJmp(false);
122 setUseUnderscoreLongJmp(false);
123 } else if (Subtarget->isTargetWindowsGNU()) {
124 // MS runtime is weird: it exports _setjmp, but longjmp!
125 setUseUnderscoreSetJmp(true);
126 setUseUnderscoreLongJmp(false);
128 setUseUnderscoreSetJmp(true);
129 setUseUnderscoreLongJmp(true);
132 // Set up the register classes.
133 addRegisterClass(MVT::i8, &X86::GR8RegClass);
134 addRegisterClass(MVT::i16, &X86::GR16RegClass);
135 addRegisterClass(MVT::i32, &X86::GR32RegClass);
136 if (Subtarget->is64Bit())
137 addRegisterClass(MVT::i64, &X86::GR64RegClass);
139 for (MVT VT : MVT::integer_valuetypes())
140 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
142 // We don't accept any truncstore of integer registers.
143 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
144 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
145 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
146 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
147 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
148 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
150 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
152 // SETOEQ and SETUNE require checking two conditions.
153 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
154 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
155 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
156 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
157 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
158 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
160 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
162 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
163 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
164 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
166 if (Subtarget->is64Bit()) {
167 if (!Subtarget->useSoftFloat() && Subtarget->hasAVX512())
168 // f32/f64 are legal, f80 is custom.
169 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
171 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
172 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
173 } else if (!Subtarget->useSoftFloat()) {
174 // We have an algorithm for SSE2->double, and we turn this into a
175 // 64-bit FILD followed by conditional FADD for other targets.
176 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
177 // We have an algorithm for SSE2, and we turn this into a 64-bit
178 // FILD or VCVTUSI2SS/SD for other targets.
179 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
182 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
184 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
185 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
187 if (!Subtarget->useSoftFloat()) {
188 // SSE has no i16 to fp conversion, only i32
189 if (X86ScalarSSEf32) {
190 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
191 // f32 and f64 cases are Legal, f80 case is not
192 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
194 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
195 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
198 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
199 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
202 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
204 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
205 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
207 if (!Subtarget->useSoftFloat()) {
208 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
209 // are Legal, f80 is custom lowered.
210 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
211 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
213 if (X86ScalarSSEf32) {
214 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
215 // f32 and f64 cases are Legal, f80 case is not
216 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
218 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
219 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
222 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
223 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Expand);
224 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Expand);
227 // Handle FP_TO_UINT by promoting the destination to a larger signed
229 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
230 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
231 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
233 if (Subtarget->is64Bit()) {
234 if (!Subtarget->useSoftFloat() && Subtarget->hasAVX512()) {
235 // FP_TO_UINT-i32/i64 is legal for f32/f64, but custom for f80.
236 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
237 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Custom);
239 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
240 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
242 } else if (!Subtarget->useSoftFloat()) {
243 // Since AVX is a superset of SSE3, only check for SSE here.
244 if (Subtarget->hasSSE1() && !Subtarget->hasSSE3())
245 // Expand FP_TO_UINT into a select.
246 // FIXME: We would like to use a Custom expander here eventually to do
247 // the optimal thing for SSE vs. the default expansion in the legalizer.
248 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
250 // With AVX512 we can use vcvts[ds]2usi for f32/f64->i32, f80 is custom.
251 // With SSE3 we can use fisttpll to convert to a signed i64; without
252 // SSE, we're stuck with a fistpll.
253 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
255 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Custom);
258 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
259 if (!X86ScalarSSEf64) {
260 setOperationAction(ISD::BITCAST , MVT::f32 , Expand);
261 setOperationAction(ISD::BITCAST , MVT::i32 , Expand);
262 if (Subtarget->is64Bit()) {
263 setOperationAction(ISD::BITCAST , MVT::f64 , Expand);
264 // Without SSE, i64->f64 goes through memory.
265 setOperationAction(ISD::BITCAST , MVT::i64 , Expand);
269 // Scalar integer divide and remainder are lowered to use operations that
270 // produce two results, to match the available instructions. This exposes
271 // the two-result form to trivial CSE, which is able to combine x/y and x%y
272 // into a single instruction.
274 // Scalar integer multiply-high is also lowered to use two-result
275 // operations, to match the available instructions. However, plain multiply
276 // (low) operations are left as Legal, as there are single-result
277 // instructions for this in x86. Using the two-result multiply instructions
278 // when both high and low results are needed must be arranged by dagcombine.
279 for (auto VT : { MVT::i8, MVT::i16, MVT::i32, MVT::i64 }) {
280 setOperationAction(ISD::MULHS, VT, Expand);
281 setOperationAction(ISD::MULHU, VT, Expand);
282 setOperationAction(ISD::SDIV, VT, Expand);
283 setOperationAction(ISD::UDIV, VT, Expand);
284 setOperationAction(ISD::SREM, VT, Expand);
285 setOperationAction(ISD::UREM, VT, Expand);
287 // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences.
288 setOperationAction(ISD::ADDC, VT, Custom);
289 setOperationAction(ISD::ADDE, VT, Custom);
290 setOperationAction(ISD::SUBC, VT, Custom);
291 setOperationAction(ISD::SUBE, VT, Custom);
294 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
295 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
296 setOperationAction(ISD::BR_CC , MVT::f32, Expand);
297 setOperationAction(ISD::BR_CC , MVT::f64, Expand);
298 setOperationAction(ISD::BR_CC , MVT::f80, Expand);
299 setOperationAction(ISD::BR_CC , MVT::i8, Expand);
300 setOperationAction(ISD::BR_CC , MVT::i16, Expand);
301 setOperationAction(ISD::BR_CC , MVT::i32, Expand);
302 setOperationAction(ISD::BR_CC , MVT::i64, Expand);
303 setOperationAction(ISD::SELECT_CC , MVT::f32, Expand);
304 setOperationAction(ISD::SELECT_CC , MVT::f64, Expand);
305 setOperationAction(ISD::SELECT_CC , MVT::f80, Expand);
306 setOperationAction(ISD::SELECT_CC , MVT::i8, Expand);
307 setOperationAction(ISD::SELECT_CC , MVT::i16, Expand);
308 setOperationAction(ISD::SELECT_CC , MVT::i32, Expand);
309 setOperationAction(ISD::SELECT_CC , MVT::i64, Expand);
310 if (Subtarget->is64Bit())
311 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
312 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
313 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
314 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
315 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
317 if (Subtarget->is32Bit() && Subtarget->isTargetKnownWindowsMSVC()) {
318 // On 32 bit MSVC, `fmodf(f32)` is not defined - only `fmod(f64)`
319 // is. We should promote the value to 64-bits to solve this.
320 // This is what the CRT headers do - `fmodf` is an inline header
321 // function casting to f64 and calling `fmod`.
322 setOperationAction(ISD::FREM , MVT::f32 , Promote);
324 setOperationAction(ISD::FREM , MVT::f32 , Expand);
327 setOperationAction(ISD::FREM , MVT::f64 , Expand);
328 setOperationAction(ISD::FREM , MVT::f80 , Expand);
329 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
331 // Promote the i8 variants and force them on up to i32 which has a shorter
333 setOperationAction(ISD::CTTZ , MVT::i8 , Promote);
334 AddPromotedToType (ISD::CTTZ , MVT::i8 , MVT::i32);
335 setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i8 , Promote);
336 AddPromotedToType (ISD::CTTZ_ZERO_UNDEF , MVT::i8 , MVT::i32);
337 if (Subtarget->hasBMI()) {
338 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16 , Expand);
339 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32 , Expand);
340 if (Subtarget->is64Bit())
341 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
343 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
344 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
345 if (Subtarget->is64Bit())
346 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
349 if (Subtarget->hasLZCNT()) {
350 // When promoting the i8 variants, force them to i32 for a shorter
352 setOperationAction(ISD::CTLZ , MVT::i8 , Promote);
353 AddPromotedToType (ISD::CTLZ , MVT::i8 , MVT::i32);
354 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Promote);
355 AddPromotedToType (ISD::CTLZ_ZERO_UNDEF, MVT::i8 , MVT::i32);
356 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Expand);
357 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Expand);
358 if (Subtarget->is64Bit())
359 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
361 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
362 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
363 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
364 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Custom);
365 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Custom);
366 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Custom);
367 if (Subtarget->is64Bit()) {
368 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
369 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom);
373 // Special handling for half-precision floating point conversions.
374 // If we don't have F16C support, then lower half float conversions
375 // into library calls.
376 if (Subtarget->useSoftFloat() || !Subtarget->hasF16C()) {
377 setOperationAction(ISD::FP16_TO_FP, MVT::f32, Expand);
378 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand);
381 // There's never any support for operations beyond MVT::f32.
382 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand);
383 setOperationAction(ISD::FP16_TO_FP, MVT::f80, Expand);
384 setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand);
385 setOperationAction(ISD::FP_TO_FP16, MVT::f80, Expand);
387 setLoadExtAction(ISD::EXTLOAD, MVT::f32, MVT::f16, Expand);
388 setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f16, Expand);
389 setLoadExtAction(ISD::EXTLOAD, MVT::f80, MVT::f16, Expand);
390 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
391 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
392 setTruncStoreAction(MVT::f80, MVT::f16, Expand);
394 if (Subtarget->hasPOPCNT()) {
395 setOperationAction(ISD::CTPOP , MVT::i8 , Promote);
397 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
398 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
399 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
400 if (Subtarget->is64Bit())
401 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
404 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
406 if (!Subtarget->hasMOVBE())
407 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
409 // These should be promoted to a larger select which is supported.
410 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
411 // X86 wants to expand cmov itself.
412 setOperationAction(ISD::SELECT , MVT::i8 , Custom);
413 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
414 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
415 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
416 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
417 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
418 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
419 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
420 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
421 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
422 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
423 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
424 if (Subtarget->is64Bit()) {
425 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
426 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
428 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
429 // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support
430 // SjLj exception handling but a light-weight setjmp/longjmp replacement to
431 // support continuation, user-level threading, and etc.. As a result, no
432 // other SjLj exception interfaces are implemented and please don't build
433 // your own exception handling based on them.
434 // LLVM/Clang supports zero-cost DWARF exception handling.
435 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
436 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
439 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
440 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
441 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
442 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
443 if (Subtarget->is64Bit())
444 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
445 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
446 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom);
447 if (Subtarget->is64Bit()) {
448 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
449 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
450 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
451 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
452 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom);
454 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
455 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
456 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
457 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
458 if (Subtarget->is64Bit()) {
459 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
460 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
461 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
464 if (Subtarget->hasSSE1())
465 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
467 setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom);
469 // Expand certain atomics
470 for (auto VT : { MVT::i8, MVT::i16, MVT::i32, MVT::i64 }) {
471 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, VT, Custom);
472 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom);
473 setOperationAction(ISD::ATOMIC_STORE, VT, Custom);
476 if (Subtarget->hasCmpxchg16b()) {
477 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, MVT::i128, Custom);
480 // FIXME - use subtarget debug flags
481 if (!Subtarget->isTargetDarwin() && !Subtarget->isTargetELF() &&
482 !Subtarget->isTargetCygMing() && !Subtarget->isTargetWin64()) {
483 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
486 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
487 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
489 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
490 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
492 setOperationAction(ISD::TRAP, MVT::Other, Legal);
493 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Legal);
495 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
496 setOperationAction(ISD::VASTART , MVT::Other, Custom);
497 setOperationAction(ISD::VAEND , MVT::Other, Expand);
498 if (Subtarget->is64Bit()) {
499 setOperationAction(ISD::VAARG , MVT::Other, Custom);
500 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
502 // TargetInfo::CharPtrBuiltinVaList
503 setOperationAction(ISD::VAARG , MVT::Other, Expand);
504 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
507 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
508 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
510 setOperationAction(ISD::DYNAMIC_STACKALLOC, PtrVT, Custom);
512 // GC_TRANSITION_START and GC_TRANSITION_END need custom lowering.
513 setOperationAction(ISD::GC_TRANSITION_START, MVT::Other, Custom);
514 setOperationAction(ISD::GC_TRANSITION_END, MVT::Other, Custom);
516 if (!Subtarget->useSoftFloat() && X86ScalarSSEf64) {
517 // f32 and f64 use SSE.
518 // Set up the FP register classes.
519 addRegisterClass(MVT::f32, &X86::FR32RegClass);
520 addRegisterClass(MVT::f64, &X86::FR64RegClass);
522 // Use ANDPD to simulate FABS.
523 setOperationAction(ISD::FABS , MVT::f64, Custom);
524 setOperationAction(ISD::FABS , MVT::f32, Custom);
526 // Use XORP to simulate FNEG.
527 setOperationAction(ISD::FNEG , MVT::f64, Custom);
528 setOperationAction(ISD::FNEG , MVT::f32, Custom);
530 // Use ANDPD and ORPD to simulate FCOPYSIGN.
531 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
532 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
534 // Lower this to FGETSIGNx86 plus an AND.
535 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom);
536 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom);
538 // We don't support sin/cos/fmod
539 setOperationAction(ISD::FSIN , MVT::f64, Expand);
540 setOperationAction(ISD::FCOS , MVT::f64, Expand);
541 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
542 setOperationAction(ISD::FSIN , MVT::f32, Expand);
543 setOperationAction(ISD::FCOS , MVT::f32, Expand);
544 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
546 // Expand FP immediates into loads from the stack, except for the special
548 addLegalFPImmediate(APFloat(+0.0)); // xorpd
549 addLegalFPImmediate(APFloat(+0.0f)); // xorps
550 } else if (!Subtarget->useSoftFloat() && X86ScalarSSEf32) {
551 // Use SSE for f32, x87 for f64.
552 // Set up the FP register classes.
553 addRegisterClass(MVT::f32, &X86::FR32RegClass);
554 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
556 // Use ANDPS to simulate FABS.
557 setOperationAction(ISD::FABS , MVT::f32, Custom);
559 // Use XORP to simulate FNEG.
560 setOperationAction(ISD::FNEG , MVT::f32, Custom);
562 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
564 // Use ANDPS and ORPS to simulate FCOPYSIGN.
565 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
566 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
568 // We don't support sin/cos/fmod
569 setOperationAction(ISD::FSIN , MVT::f32, Expand);
570 setOperationAction(ISD::FCOS , MVT::f32, Expand);
571 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
573 // Special cases we handle for FP constants.
574 addLegalFPImmediate(APFloat(+0.0f)); // xorps
575 addLegalFPImmediate(APFloat(+0.0)); // FLD0
576 addLegalFPImmediate(APFloat(+1.0)); // FLD1
577 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
578 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
580 if (!TM.Options.UnsafeFPMath) {
581 setOperationAction(ISD::FSIN , MVT::f64, Expand);
582 setOperationAction(ISD::FCOS , MVT::f64, Expand);
583 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
585 } else if (!Subtarget->useSoftFloat()) {
586 // f32 and f64 in x87.
587 // Set up the FP register classes.
588 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
589 addRegisterClass(MVT::f32, &X86::RFP32RegClass);
591 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
592 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
593 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
594 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
596 if (!TM.Options.UnsafeFPMath) {
597 setOperationAction(ISD::FSIN , MVT::f64, Expand);
598 setOperationAction(ISD::FSIN , MVT::f32, Expand);
599 setOperationAction(ISD::FCOS , MVT::f64, Expand);
600 setOperationAction(ISD::FCOS , MVT::f32, Expand);
601 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
602 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
604 addLegalFPImmediate(APFloat(+0.0)); // FLD0
605 addLegalFPImmediate(APFloat(+1.0)); // FLD1
606 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
607 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
608 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
609 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
610 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
611 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
614 // We don't support FMA.
615 setOperationAction(ISD::FMA, MVT::f64, Expand);
616 setOperationAction(ISD::FMA, MVT::f32, Expand);
618 // Long double always uses X87.
619 if (!Subtarget->useSoftFloat()) {
620 addRegisterClass(MVT::f80, &X86::RFP80RegClass);
621 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
622 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
624 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended);
625 addLegalFPImmediate(TmpFlt); // FLD0
627 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
630 APFloat TmpFlt2(+1.0);
631 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
633 addLegalFPImmediate(TmpFlt2); // FLD1
634 TmpFlt2.changeSign();
635 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
638 if (!TM.Options.UnsafeFPMath) {
639 setOperationAction(ISD::FSIN , MVT::f80, Expand);
640 setOperationAction(ISD::FCOS , MVT::f80, Expand);
641 setOperationAction(ISD::FSINCOS, MVT::f80, Expand);
644 setOperationAction(ISD::FFLOOR, MVT::f80, Expand);
645 setOperationAction(ISD::FCEIL, MVT::f80, Expand);
646 setOperationAction(ISD::FTRUNC, MVT::f80, Expand);
647 setOperationAction(ISD::FRINT, MVT::f80, Expand);
648 setOperationAction(ISD::FNEARBYINT, MVT::f80, Expand);
649 setOperationAction(ISD::FMA, MVT::f80, Expand);
652 // Always use a library call for pow.
653 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
654 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
655 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
657 setOperationAction(ISD::FLOG, MVT::f80, Expand);
658 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
659 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
660 setOperationAction(ISD::FEXP, MVT::f80, Expand);
661 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
662 setOperationAction(ISD::FMINNUM, MVT::f80, Expand);
663 setOperationAction(ISD::FMAXNUM, MVT::f80, Expand);
665 // First set operation action for all vector types to either promote
666 // (for widening) or expand (for scalarization). Then we will selectively
667 // turn on ones that can be effectively codegen'd.
668 for (MVT VT : MVT::vector_valuetypes()) {
669 setOperationAction(ISD::ADD , VT, Expand);
670 setOperationAction(ISD::SUB , VT, Expand);
671 setOperationAction(ISD::FADD, VT, Expand);
672 setOperationAction(ISD::FNEG, VT, Expand);
673 setOperationAction(ISD::FSUB, VT, Expand);
674 setOperationAction(ISD::MUL , VT, Expand);
675 setOperationAction(ISD::FMUL, VT, Expand);
676 setOperationAction(ISD::SDIV, VT, Expand);
677 setOperationAction(ISD::UDIV, VT, Expand);
678 setOperationAction(ISD::FDIV, VT, Expand);
679 setOperationAction(ISD::SREM, VT, Expand);
680 setOperationAction(ISD::UREM, VT, Expand);
681 setOperationAction(ISD::LOAD, VT, Expand);
682 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);
683 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT,Expand);
684 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
685 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT,Expand);
686 setOperationAction(ISD::INSERT_SUBVECTOR, VT,Expand);
687 setOperationAction(ISD::FABS, VT, Expand);
688 setOperationAction(ISD::FSIN, VT, Expand);
689 setOperationAction(ISD::FSINCOS, VT, Expand);
690 setOperationAction(ISD::FCOS, VT, Expand);
691 setOperationAction(ISD::FSINCOS, VT, Expand);
692 setOperationAction(ISD::FREM, VT, Expand);
693 setOperationAction(ISD::FMA, VT, Expand);
694 setOperationAction(ISD::FPOWI, VT, Expand);
695 setOperationAction(ISD::FSQRT, VT, Expand);
696 setOperationAction(ISD::FCOPYSIGN, VT, Expand);
697 setOperationAction(ISD::FFLOOR, VT, Expand);
698 setOperationAction(ISD::FCEIL, VT, Expand);
699 setOperationAction(ISD::FTRUNC, VT, Expand);
700 setOperationAction(ISD::FRINT, VT, Expand);
701 setOperationAction(ISD::FNEARBYINT, VT, Expand);
702 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
703 setOperationAction(ISD::MULHS, VT, Expand);
704 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
705 setOperationAction(ISD::MULHU, VT, Expand);
706 setOperationAction(ISD::SDIVREM, VT, Expand);
707 setOperationAction(ISD::UDIVREM, VT, Expand);
708 setOperationAction(ISD::FPOW, VT, Expand);
709 setOperationAction(ISD::CTPOP, VT, Expand);
710 setOperationAction(ISD::CTTZ, VT, Expand);
711 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
712 setOperationAction(ISD::CTLZ, VT, Expand);
713 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
714 setOperationAction(ISD::SHL, VT, Expand);
715 setOperationAction(ISD::SRA, VT, Expand);
716 setOperationAction(ISD::SRL, VT, Expand);
717 setOperationAction(ISD::ROTL, VT, Expand);
718 setOperationAction(ISD::ROTR, VT, Expand);
719 setOperationAction(ISD::BSWAP, VT, Expand);
720 setOperationAction(ISD::SETCC, VT, Expand);
721 setOperationAction(ISD::FLOG, VT, Expand);
722 setOperationAction(ISD::FLOG2, VT, Expand);
723 setOperationAction(ISD::FLOG10, VT, Expand);
724 setOperationAction(ISD::FEXP, VT, Expand);
725 setOperationAction(ISD::FEXP2, VT, Expand);
726 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
727 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
728 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
729 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
730 setOperationAction(ISD::SIGN_EXTEND_INREG, VT,Expand);
731 setOperationAction(ISD::TRUNCATE, VT, Expand);
732 setOperationAction(ISD::SIGN_EXTEND, VT, Expand);
733 setOperationAction(ISD::ZERO_EXTEND, VT, Expand);
734 setOperationAction(ISD::ANY_EXTEND, VT, Expand);
735 setOperationAction(ISD::VSELECT, VT, Expand);
736 setOperationAction(ISD::SELECT_CC, VT, Expand);
737 for (MVT InnerVT : MVT::vector_valuetypes()) {
738 setTruncStoreAction(InnerVT, VT, Expand);
740 setLoadExtAction(ISD::SEXTLOAD, InnerVT, VT, Expand);
741 setLoadExtAction(ISD::ZEXTLOAD, InnerVT, VT, Expand);
743 // N.b. ISD::EXTLOAD legality is basically ignored except for i1-like
744 // types, we have to deal with them whether we ask for Expansion or not.
745 // Setting Expand causes its own optimisation problems though, so leave
747 if (VT.getVectorElementType() == MVT::i1)
748 setLoadExtAction(ISD::EXTLOAD, InnerVT, VT, Expand);
750 // EXTLOAD for MVT::f16 vectors is not legal because f16 vectors are
751 // split/scalarized right now.
752 if (VT.getVectorElementType() == MVT::f16)
753 setLoadExtAction(ISD::EXTLOAD, InnerVT, VT, Expand);
757 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
758 // with -msoft-float, disable use of MMX as well.
759 if (!Subtarget->useSoftFloat() && Subtarget->hasMMX()) {
760 addRegisterClass(MVT::x86mmx, &X86::VR64RegClass);
761 // No operations on x86mmx supported, everything uses intrinsics.
764 // MMX-sized vectors (other than x86mmx) are expected to be expanded
765 // into smaller operations.
766 for (MVT MMXTy : {MVT::v8i8, MVT::v4i16, MVT::v2i32, MVT::v1i64}) {
767 setOperationAction(ISD::MULHS, MMXTy, Expand);
768 setOperationAction(ISD::AND, MMXTy, Expand);
769 setOperationAction(ISD::OR, MMXTy, Expand);
770 setOperationAction(ISD::XOR, MMXTy, Expand);
771 setOperationAction(ISD::SCALAR_TO_VECTOR, MMXTy, Expand);
772 setOperationAction(ISD::SELECT, MMXTy, Expand);
773 setOperationAction(ISD::BITCAST, MMXTy, Expand);
775 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand);
777 if (!Subtarget->useSoftFloat() && Subtarget->hasSSE1()) {
778 addRegisterClass(MVT::v4f32, &X86::VR128RegClass);
780 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
781 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
782 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
783 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
784 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
785 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
786 setOperationAction(ISD::FABS, MVT::v4f32, Custom);
787 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
788 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
789 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
790 setOperationAction(ISD::VSELECT, MVT::v4f32, Custom);
791 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
792 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
793 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Custom);
796 if (!Subtarget->useSoftFloat() && Subtarget->hasSSE2()) {
797 addRegisterClass(MVT::v2f64, &X86::VR128RegClass);
799 // FIXME: Unfortunately, -soft-float and -no-implicit-float mean XMM
800 // registers cannot be used even for integer operations.
801 addRegisterClass(MVT::v16i8, &X86::VR128RegClass);
802 addRegisterClass(MVT::v8i16, &X86::VR128RegClass);
803 addRegisterClass(MVT::v4i32, &X86::VR128RegClass);
804 addRegisterClass(MVT::v2i64, &X86::VR128RegClass);
806 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
807 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
808 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
809 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
810 setOperationAction(ISD::MUL, MVT::v16i8, Custom);
811 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
812 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
813 setOperationAction(ISD::UMUL_LOHI, MVT::v4i32, Custom);
814 setOperationAction(ISD::SMUL_LOHI, MVT::v4i32, Custom);
815 setOperationAction(ISD::MULHU, MVT::v8i16, Legal);
816 setOperationAction(ISD::MULHS, MVT::v8i16, Legal);
817 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
818 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
819 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
820 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
821 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
822 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
823 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
824 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
825 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
826 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
827 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
828 setOperationAction(ISD::FABS, MVT::v2f64, Custom);
830 setOperationAction(ISD::SMAX, MVT::v8i16, Legal);
831 setOperationAction(ISD::UMAX, MVT::v16i8, Legal);
832 setOperationAction(ISD::SMIN, MVT::v8i16, Legal);
833 setOperationAction(ISD::UMIN, MVT::v16i8, Legal);
835 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
836 setOperationAction(ISD::SETCC, MVT::v16i8, Custom);
837 setOperationAction(ISD::SETCC, MVT::v8i16, Custom);
838 setOperationAction(ISD::SETCC, MVT::v4i32, Custom);
840 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
841 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
842 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
843 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
844 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
846 setOperationAction(ISD::CTPOP, MVT::v16i8, Custom);
847 setOperationAction(ISD::CTPOP, MVT::v8i16, Custom);
848 setOperationAction(ISD::CTPOP, MVT::v4i32, Custom);
849 setOperationAction(ISD::CTPOP, MVT::v2i64, Custom);
851 setOperationAction(ISD::CTTZ, MVT::v16i8, Custom);
852 setOperationAction(ISD::CTTZ, MVT::v8i16, Custom);
853 setOperationAction(ISD::CTTZ, MVT::v4i32, Custom);
854 // ISD::CTTZ v2i64 - scalarization is faster.
855 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v16i8, Custom);
856 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v8i16, Custom);
857 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v4i32, Custom);
858 // ISD::CTTZ_ZERO_UNDEF v2i64 - scalarization is faster.
860 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
861 for (auto VT : { MVT::v16i8, MVT::v8i16, MVT::v4i32 }) {
862 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
863 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
864 setOperationAction(ISD::VSELECT, VT, Custom);
865 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
868 // We support custom legalizing of sext and anyext loads for specific
869 // memory vector types which we can load as a scalar (or sequence of
870 // scalars) and extend in-register to a legal 128-bit vector type. For sext
871 // loads these must work with a single scalar load.
872 for (MVT VT : MVT::integer_vector_valuetypes()) {
873 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v4i8, Custom);
874 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v4i16, Custom);
875 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v8i8, Custom);
876 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i8, Custom);
877 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i16, Custom);
878 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i32, Custom);
879 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4i8, Custom);
880 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4i16, Custom);
881 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v8i8, Custom);
884 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
885 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
886 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
887 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
888 setOperationAction(ISD::VSELECT, MVT::v2f64, Custom);
889 setOperationAction(ISD::VSELECT, MVT::v2i64, Custom);
890 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
891 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
893 if (Subtarget->is64Bit()) {
894 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
895 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
898 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
899 for (auto VT : { MVT::v16i8, MVT::v8i16, MVT::v4i32 }) {
900 setOperationAction(ISD::AND, VT, Promote);
901 AddPromotedToType (ISD::AND, VT, MVT::v2i64);
902 setOperationAction(ISD::OR, VT, Promote);
903 AddPromotedToType (ISD::OR, VT, MVT::v2i64);
904 setOperationAction(ISD::XOR, VT, Promote);
905 AddPromotedToType (ISD::XOR, VT, MVT::v2i64);
906 setOperationAction(ISD::LOAD, VT, Promote);
907 AddPromotedToType (ISD::LOAD, VT, MVT::v2i64);
908 setOperationAction(ISD::SELECT, VT, Promote);
909 AddPromotedToType (ISD::SELECT, VT, MVT::v2i64);
912 // Custom lower v2i64 and v2f64 selects.
913 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
914 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
915 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
916 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
918 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
919 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
921 setOperationAction(ISD::SINT_TO_FP, MVT::v2i32, Custom);
923 setOperationAction(ISD::UINT_TO_FP, MVT::v4i8, Custom);
924 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);
925 // As there is no 64-bit GPR available, we need build a special custom
926 // sequence to convert from v2i32 to v2f32.
927 if (!Subtarget->is64Bit())
928 setOperationAction(ISD::UINT_TO_FP, MVT::v2f32, Custom);
930 setOperationAction(ISD::FP_EXTEND, MVT::v2f32, Custom);
931 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Custom);
933 for (MVT VT : MVT::fp_vector_valuetypes())
934 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2f32, Legal);
936 setOperationAction(ISD::BITCAST, MVT::v2i32, Custom);
937 setOperationAction(ISD::BITCAST, MVT::v4i16, Custom);
938 setOperationAction(ISD::BITCAST, MVT::v8i8, Custom);
941 if (!Subtarget->useSoftFloat() && Subtarget->hasSSE41()) {
942 for (MVT RoundedTy : {MVT::f32, MVT::f64, MVT::v4f32, MVT::v2f64}) {
943 setOperationAction(ISD::FFLOOR, RoundedTy, Legal);
944 setOperationAction(ISD::FCEIL, RoundedTy, Legal);
945 setOperationAction(ISD::FTRUNC, RoundedTy, Legal);
946 setOperationAction(ISD::FRINT, RoundedTy, Legal);
947 setOperationAction(ISD::FNEARBYINT, RoundedTy, Legal);
950 setOperationAction(ISD::SMAX, MVT::v16i8, Legal);
951 setOperationAction(ISD::SMAX, MVT::v4i32, Legal);
952 setOperationAction(ISD::UMAX, MVT::v8i16, Legal);
953 setOperationAction(ISD::UMAX, MVT::v4i32, Legal);
954 setOperationAction(ISD::SMIN, MVT::v16i8, Legal);
955 setOperationAction(ISD::SMIN, MVT::v4i32, Legal);
956 setOperationAction(ISD::UMIN, MVT::v8i16, Legal);
957 setOperationAction(ISD::UMIN, MVT::v4i32, Legal);
959 // FIXME: Do we need to handle scalar-to-vector here?
960 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
962 // We directly match byte blends in the backend as they match the VSELECT
964 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
966 // SSE41 brings specific instructions for doing vector sign extend even in
967 // cases where we don't have SRA.
968 for (MVT VT : MVT::integer_vector_valuetypes()) {
969 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i8, Custom);
970 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i16, Custom);
971 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i32, Custom);
974 // SSE41 also has vector sign/zero extending loads, PMOV[SZ]X
975 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i16, MVT::v8i8, Legal);
976 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i32, MVT::v4i8, Legal);
977 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i64, MVT::v2i8, Legal);
978 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i32, MVT::v4i16, Legal);
979 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i64, MVT::v2i16, Legal);
980 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i64, MVT::v2i32, Legal);
982 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i16, MVT::v8i8, Legal);
983 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i32, MVT::v4i8, Legal);
984 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i64, MVT::v2i8, Legal);
985 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i32, MVT::v4i16, Legal);
986 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i64, MVT::v2i16, Legal);
987 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i64, MVT::v2i32, Legal);
989 // i8 and i16 vectors are custom because the source register and source
990 // source memory operand types are not the same width. f32 vectors are
991 // custom since the immediate controlling the insert encodes additional
993 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
994 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
995 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
996 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
998 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
999 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
1000 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
1001 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
1003 // FIXME: these should be Legal, but that's only for the case where
1004 // the index is constant. For now custom expand to deal with that.
1005 if (Subtarget->is64Bit()) {
1006 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
1007 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
1011 if (Subtarget->hasSSE2()) {
1012 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v2i64, Custom);
1013 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v4i32, Custom);
1014 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v8i16, Custom);
1016 setOperationAction(ISD::SRL, MVT::v8i16, Custom);
1017 setOperationAction(ISD::SRL, MVT::v16i8, Custom);
1019 setOperationAction(ISD::SHL, MVT::v8i16, Custom);
1020 setOperationAction(ISD::SHL, MVT::v16i8, Custom);
1022 setOperationAction(ISD::SRA, MVT::v8i16, Custom);
1023 setOperationAction(ISD::SRA, MVT::v16i8, Custom);
1025 // In the customized shift lowering, the legal cases in AVX2 will be
1027 setOperationAction(ISD::SRL, MVT::v2i64, Custom);
1028 setOperationAction(ISD::SRL, MVT::v4i32, Custom);
1030 setOperationAction(ISD::SHL, MVT::v2i64, Custom);
1031 setOperationAction(ISD::SHL, MVT::v4i32, Custom);
1033 setOperationAction(ISD::SRA, MVT::v2i64, Custom);
1034 setOperationAction(ISD::SRA, MVT::v4i32, Custom);
1037 if (Subtarget->hasXOP()) {
1038 setOperationAction(ISD::ROTL, MVT::v16i8, Custom);
1039 setOperationAction(ISD::ROTL, MVT::v8i16, Custom);
1040 setOperationAction(ISD::ROTL, MVT::v4i32, Custom);
1041 setOperationAction(ISD::ROTL, MVT::v2i64, Custom);
1042 setOperationAction(ISD::ROTL, MVT::v32i8, Custom);
1043 setOperationAction(ISD::ROTL, MVT::v16i16, Custom);
1044 setOperationAction(ISD::ROTL, MVT::v8i32, Custom);
1045 setOperationAction(ISD::ROTL, MVT::v4i64, Custom);
1048 if (!Subtarget->useSoftFloat() && Subtarget->hasFp256()) {
1049 addRegisterClass(MVT::v32i8, &X86::VR256RegClass);
1050 addRegisterClass(MVT::v16i16, &X86::VR256RegClass);
1051 addRegisterClass(MVT::v8i32, &X86::VR256RegClass);
1052 addRegisterClass(MVT::v8f32, &X86::VR256RegClass);
1053 addRegisterClass(MVT::v4i64, &X86::VR256RegClass);
1054 addRegisterClass(MVT::v4f64, &X86::VR256RegClass);
1056 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
1057 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
1058 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
1060 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
1061 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
1062 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
1063 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
1064 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
1065 setOperationAction(ISD::FFLOOR, MVT::v8f32, Legal);
1066 setOperationAction(ISD::FCEIL, MVT::v8f32, Legal);
1067 setOperationAction(ISD::FTRUNC, MVT::v8f32, Legal);
1068 setOperationAction(ISD::FRINT, MVT::v8f32, Legal);
1069 setOperationAction(ISD::FNEARBYINT, MVT::v8f32, Legal);
1070 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
1071 setOperationAction(ISD::FABS, MVT::v8f32, Custom);
1073 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
1074 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
1075 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
1076 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
1077 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
1078 setOperationAction(ISD::FFLOOR, MVT::v4f64, Legal);
1079 setOperationAction(ISD::FCEIL, MVT::v4f64, Legal);
1080 setOperationAction(ISD::FTRUNC, MVT::v4f64, Legal);
1081 setOperationAction(ISD::FRINT, MVT::v4f64, Legal);
1082 setOperationAction(ISD::FNEARBYINT, MVT::v4f64, Legal);
1083 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
1084 setOperationAction(ISD::FABS, MVT::v4f64, Custom);
1086 // (fp_to_int:v8i16 (v8f32 ..)) requires the result type to be promoted
1087 // even though v8i16 is a legal type.
1088 setOperationAction(ISD::FP_TO_SINT, MVT::v8i16, Promote);
1089 setOperationAction(ISD::FP_TO_UINT, MVT::v8i16, Promote);
1090 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
1092 setOperationAction(ISD::SINT_TO_FP, MVT::v8i16, Promote);
1093 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
1094 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal);
1096 setOperationAction(ISD::UINT_TO_FP, MVT::v8i8, Custom);
1097 setOperationAction(ISD::UINT_TO_FP, MVT::v8i16, Custom);
1099 for (MVT VT : MVT::fp_vector_valuetypes())
1100 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4f32, Legal);
1102 setOperationAction(ISD::SRL, MVT::v16i16, Custom);
1103 setOperationAction(ISD::SRL, MVT::v32i8, Custom);
1105 setOperationAction(ISD::SHL, MVT::v16i16, Custom);
1106 setOperationAction(ISD::SHL, MVT::v32i8, Custom);
1108 setOperationAction(ISD::SRA, MVT::v16i16, Custom);
1109 setOperationAction(ISD::SRA, MVT::v32i8, Custom);
1111 setOperationAction(ISD::SETCC, MVT::v32i8, Custom);
1112 setOperationAction(ISD::SETCC, MVT::v16i16, Custom);
1113 setOperationAction(ISD::SETCC, MVT::v8i32, Custom);
1114 setOperationAction(ISD::SETCC, MVT::v4i64, Custom);
1116 setOperationAction(ISD::SELECT, MVT::v4f64, Custom);
1117 setOperationAction(ISD::SELECT, MVT::v4i64, Custom);
1118 setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
1120 setOperationAction(ISD::SIGN_EXTEND, MVT::v4i64, Custom);
1121 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i32, Custom);
1122 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1123 setOperationAction(ISD::ZERO_EXTEND, MVT::v4i64, Custom);
1124 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i32, Custom);
1125 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i16, Custom);
1126 setOperationAction(ISD::ANY_EXTEND, MVT::v4i64, Custom);
1127 setOperationAction(ISD::ANY_EXTEND, MVT::v8i32, Custom);
1128 setOperationAction(ISD::ANY_EXTEND, MVT::v16i16, Custom);
1129 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1130 setOperationAction(ISD::TRUNCATE, MVT::v8i16, Custom);
1131 setOperationAction(ISD::TRUNCATE, MVT::v4i32, Custom);
1133 setOperationAction(ISD::CTPOP, MVT::v32i8, Custom);
1134 setOperationAction(ISD::CTPOP, MVT::v16i16, Custom);
1135 setOperationAction(ISD::CTPOP, MVT::v8i32, Custom);
1136 setOperationAction(ISD::CTPOP, MVT::v4i64, Custom);
1138 setOperationAction(ISD::CTTZ, MVT::v32i8, Custom);
1139 setOperationAction(ISD::CTTZ, MVT::v16i16, Custom);
1140 setOperationAction(ISD::CTTZ, MVT::v8i32, Custom);
1141 setOperationAction(ISD::CTTZ, MVT::v4i64, Custom);
1142 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v32i8, Custom);
1143 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v16i16, Custom);
1144 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v8i32, Custom);
1145 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v4i64, Custom);
1147 if (Subtarget->hasFMA() || Subtarget->hasFMA4() || Subtarget->hasAVX512()) {
1148 setOperationAction(ISD::FMA, MVT::v8f32, Legal);
1149 setOperationAction(ISD::FMA, MVT::v4f64, Legal);
1150 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
1151 setOperationAction(ISD::FMA, MVT::v2f64, Legal);
1152 setOperationAction(ISD::FMA, MVT::f32, Legal);
1153 setOperationAction(ISD::FMA, MVT::f64, Legal);
1156 if (Subtarget->hasInt256()) {
1157 setOperationAction(ISD::ADD, MVT::v4i64, Legal);
1158 setOperationAction(ISD::ADD, MVT::v8i32, Legal);
1159 setOperationAction(ISD::ADD, MVT::v16i16, Legal);
1160 setOperationAction(ISD::ADD, MVT::v32i8, Legal);
1162 setOperationAction(ISD::SUB, MVT::v4i64, Legal);
1163 setOperationAction(ISD::SUB, MVT::v8i32, Legal);
1164 setOperationAction(ISD::SUB, MVT::v16i16, Legal);
1165 setOperationAction(ISD::SUB, MVT::v32i8, Legal);
1167 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1168 setOperationAction(ISD::MUL, MVT::v8i32, Legal);
1169 setOperationAction(ISD::MUL, MVT::v16i16, Legal);
1170 setOperationAction(ISD::MUL, MVT::v32i8, Custom);
1172 setOperationAction(ISD::UMUL_LOHI, MVT::v8i32, Custom);
1173 setOperationAction(ISD::SMUL_LOHI, MVT::v8i32, Custom);
1174 setOperationAction(ISD::MULHU, MVT::v16i16, Legal);
1175 setOperationAction(ISD::MULHS, MVT::v16i16, Legal);
1177 setOperationAction(ISD::SMAX, MVT::v32i8, Legal);
1178 setOperationAction(ISD::SMAX, MVT::v16i16, Legal);
1179 setOperationAction(ISD::SMAX, MVT::v8i32, Legal);
1180 setOperationAction(ISD::UMAX, MVT::v32i8, Legal);
1181 setOperationAction(ISD::UMAX, MVT::v16i16, Legal);
1182 setOperationAction(ISD::UMAX, MVT::v8i32, Legal);
1183 setOperationAction(ISD::SMIN, MVT::v32i8, Legal);
1184 setOperationAction(ISD::SMIN, MVT::v16i16, Legal);
1185 setOperationAction(ISD::SMIN, MVT::v8i32, Legal);
1186 setOperationAction(ISD::UMIN, MVT::v32i8, Legal);
1187 setOperationAction(ISD::UMIN, MVT::v16i16, Legal);
1188 setOperationAction(ISD::UMIN, MVT::v8i32, Legal);
1190 // The custom lowering for UINT_TO_FP for v8i32 becomes interesting
1191 // when we have a 256bit-wide blend with immediate.
1192 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Custom);
1194 // AVX2 also has wider vector sign/zero extending loads, VPMOV[SZ]X
1195 setLoadExtAction(ISD::SEXTLOAD, MVT::v16i16, MVT::v16i8, Legal);
1196 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i32, MVT::v8i8, Legal);
1197 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i64, MVT::v4i8, Legal);
1198 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i32, MVT::v8i16, Legal);
1199 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i64, MVT::v4i16, Legal);
1200 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i64, MVT::v4i32, Legal);
1202 setLoadExtAction(ISD::ZEXTLOAD, MVT::v16i16, MVT::v16i8, Legal);
1203 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i32, MVT::v8i8, Legal);
1204 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i64, MVT::v4i8, Legal);
1205 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i32, MVT::v8i16, Legal);
1206 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i64, MVT::v4i16, Legal);
1207 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i64, MVT::v4i32, Legal);
1209 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
1210 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
1211 setOperationAction(ISD::ADD, MVT::v16i16, Custom);
1212 setOperationAction(ISD::ADD, MVT::v32i8, Custom);
1214 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
1215 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
1216 setOperationAction(ISD::SUB, MVT::v16i16, Custom);
1217 setOperationAction(ISD::SUB, MVT::v32i8, Custom);
1219 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1220 setOperationAction(ISD::MUL, MVT::v8i32, Custom);
1221 setOperationAction(ISD::MUL, MVT::v16i16, Custom);
1222 setOperationAction(ISD::MUL, MVT::v32i8, Custom);
1224 setOperationAction(ISD::SMAX, MVT::v32i8, Custom);
1225 setOperationAction(ISD::SMAX, MVT::v16i16, Custom);
1226 setOperationAction(ISD::SMAX, MVT::v8i32, Custom);
1227 setOperationAction(ISD::UMAX, MVT::v32i8, Custom);
1228 setOperationAction(ISD::UMAX, MVT::v16i16, Custom);
1229 setOperationAction(ISD::UMAX, MVT::v8i32, Custom);
1230 setOperationAction(ISD::SMIN, MVT::v32i8, Custom);
1231 setOperationAction(ISD::SMIN, MVT::v16i16, Custom);
1232 setOperationAction(ISD::SMIN, MVT::v8i32, Custom);
1233 setOperationAction(ISD::UMIN, MVT::v32i8, Custom);
1234 setOperationAction(ISD::UMIN, MVT::v16i16, Custom);
1235 setOperationAction(ISD::UMIN, MVT::v8i32, Custom);
1238 // In the customized shift lowering, the legal cases in AVX2 will be
1240 setOperationAction(ISD::SRL, MVT::v4i64, Custom);
1241 setOperationAction(ISD::SRL, MVT::v8i32, Custom);
1243 setOperationAction(ISD::SHL, MVT::v4i64, Custom);
1244 setOperationAction(ISD::SHL, MVT::v8i32, Custom);
1246 setOperationAction(ISD::SRA, MVT::v4i64, Custom);
1247 setOperationAction(ISD::SRA, MVT::v8i32, Custom);
1249 // Custom lower several nodes for 256-bit types.
1250 for (MVT VT : MVT::vector_valuetypes()) {
1251 if (VT.getScalarSizeInBits() >= 32) {
1252 setOperationAction(ISD::MLOAD, VT, Legal);
1253 setOperationAction(ISD::MSTORE, VT, Legal);
1255 // Extract subvector is special because the value type
1256 // (result) is 128-bit but the source is 256-bit wide.
1257 if (VT.is128BitVector()) {
1258 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1260 // Do not attempt to custom lower other non-256-bit vectors
1261 if (!VT.is256BitVector())
1264 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1265 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1266 setOperationAction(ISD::VSELECT, VT, Custom);
1267 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1268 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1269 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1270 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1271 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom);
1274 if (Subtarget->hasInt256())
1275 setOperationAction(ISD::VSELECT, MVT::v32i8, Legal);
1277 // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64.
1278 for (auto VT : { MVT::v32i8, MVT::v16i16, MVT::v8i32 }) {
1279 setOperationAction(ISD::AND, VT, Promote);
1280 AddPromotedToType (ISD::AND, VT, MVT::v4i64);
1281 setOperationAction(ISD::OR, VT, Promote);
1282 AddPromotedToType (ISD::OR, VT, MVT::v4i64);
1283 setOperationAction(ISD::XOR, VT, Promote);
1284 AddPromotedToType (ISD::XOR, VT, MVT::v4i64);
1285 setOperationAction(ISD::LOAD, VT, Promote);
1286 AddPromotedToType (ISD::LOAD, VT, MVT::v4i64);
1287 setOperationAction(ISD::SELECT, VT, Promote);
1288 AddPromotedToType (ISD::SELECT, VT, MVT::v4i64);
1292 if (!Subtarget->useSoftFloat() && Subtarget->hasAVX512()) {
1293 addRegisterClass(MVT::v16i32, &X86::VR512RegClass);
1294 addRegisterClass(MVT::v16f32, &X86::VR512RegClass);
1295 addRegisterClass(MVT::v8i64, &X86::VR512RegClass);
1296 addRegisterClass(MVT::v8f64, &X86::VR512RegClass);
1298 addRegisterClass(MVT::i1, &X86::VK1RegClass);
1299 addRegisterClass(MVT::v8i1, &X86::VK8RegClass);
1300 addRegisterClass(MVT::v16i1, &X86::VK16RegClass);
1302 for (MVT VT : MVT::fp_vector_valuetypes())
1303 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v8f32, Legal);
1305 setLoadExtAction(ISD::ZEXTLOAD, MVT::v16i32, MVT::v16i8, Legal);
1306 setLoadExtAction(ISD::SEXTLOAD, MVT::v16i32, MVT::v16i8, Legal);
1307 setLoadExtAction(ISD::ZEXTLOAD, MVT::v16i32, MVT::v16i16, Legal);
1308 setLoadExtAction(ISD::SEXTLOAD, MVT::v16i32, MVT::v16i16, Legal);
1309 setLoadExtAction(ISD::ZEXTLOAD, MVT::v32i16, MVT::v32i8, Legal);
1310 setLoadExtAction(ISD::SEXTLOAD, MVT::v32i16, MVT::v32i8, Legal);
1311 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i64, MVT::v8i8, Legal);
1312 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i64, MVT::v8i8, Legal);
1313 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i64, MVT::v8i16, Legal);
1314 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i64, MVT::v8i16, Legal);
1315 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i64, MVT::v8i32, Legal);
1316 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i64, MVT::v8i32, Legal);
1318 setOperationAction(ISD::BR_CC, MVT::i1, Expand);
1319 setOperationAction(ISD::SETCC, MVT::i1, Custom);
1320 setOperationAction(ISD::SELECT_CC, MVT::i1, Expand);
1321 setOperationAction(ISD::XOR, MVT::i1, Legal);
1322 setOperationAction(ISD::OR, MVT::i1, Legal);
1323 setOperationAction(ISD::AND, MVT::i1, Legal);
1324 setOperationAction(ISD::SUB, MVT::i1, Custom);
1325 setOperationAction(ISD::ADD, MVT::i1, Custom);
1326 setOperationAction(ISD::MUL, MVT::i1, Custom);
1327 setOperationAction(ISD::LOAD, MVT::v16f32, Legal);
1328 setOperationAction(ISD::LOAD, MVT::v8f64, Legal);
1329 setOperationAction(ISD::LOAD, MVT::v8i64, Legal);
1330 setOperationAction(ISD::LOAD, MVT::v16i32, Legal);
1331 setOperationAction(ISD::LOAD, MVT::v16i1, Legal);
1333 setOperationAction(ISD::FADD, MVT::v16f32, Legal);
1334 setOperationAction(ISD::FSUB, MVT::v16f32, Legal);
1335 setOperationAction(ISD::FMUL, MVT::v16f32, Legal);
1336 setOperationAction(ISD::FDIV, MVT::v16f32, Legal);
1337 setOperationAction(ISD::FSQRT, MVT::v16f32, Legal);
1338 setOperationAction(ISD::FNEG, MVT::v16f32, Custom);
1340 setOperationAction(ISD::FADD, MVT::v8f64, Legal);
1341 setOperationAction(ISD::FSUB, MVT::v8f64, Legal);
1342 setOperationAction(ISD::FMUL, MVT::v8f64, Legal);
1343 setOperationAction(ISD::FDIV, MVT::v8f64, Legal);
1344 setOperationAction(ISD::FSQRT, MVT::v8f64, Legal);
1345 setOperationAction(ISD::FNEG, MVT::v8f64, Custom);
1346 setOperationAction(ISD::FMA, MVT::v8f64, Legal);
1347 setOperationAction(ISD::FMA, MVT::v16f32, Legal);
1349 setOperationAction(ISD::FP_TO_SINT, MVT::v16i32, Legal);
1350 setOperationAction(ISD::FP_TO_UINT, MVT::v16i32, Legal);
1351 setOperationAction(ISD::FP_TO_UINT, MVT::v8i32, Legal);
1352 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
1353 setOperationAction(ISD::SINT_TO_FP, MVT::v16i32, Legal);
1354 setOperationAction(ISD::SINT_TO_FP, MVT::v8i1, Custom);
1355 setOperationAction(ISD::SINT_TO_FP, MVT::v16i1, Custom);
1356 setOperationAction(ISD::SINT_TO_FP, MVT::v16i8, Promote);
1357 setOperationAction(ISD::SINT_TO_FP, MVT::v16i16, Promote);
1358 setOperationAction(ISD::UINT_TO_FP, MVT::v16i32, Legal);
1359 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Legal);
1360 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
1361 setOperationAction(ISD::UINT_TO_FP, MVT::v16i8, Custom);
1362 setOperationAction(ISD::UINT_TO_FP, MVT::v16i16, Custom);
1363 setOperationAction(ISD::FP_ROUND, MVT::v8f32, Legal);
1364 setOperationAction(ISD::FP_EXTEND, MVT::v8f32, Legal);
1366 setTruncStoreAction(MVT::v8i64, MVT::v8i8, Legal);
1367 setTruncStoreAction(MVT::v8i64, MVT::v8i16, Legal);
1368 setTruncStoreAction(MVT::v8i64, MVT::v8i32, Legal);
1369 setTruncStoreAction(MVT::v16i32, MVT::v16i8, Legal);
1370 setTruncStoreAction(MVT::v16i32, MVT::v16i16, Legal);
1371 if (Subtarget->hasVLX()){
1372 setTruncStoreAction(MVT::v4i64, MVT::v4i8, Legal);
1373 setTruncStoreAction(MVT::v4i64, MVT::v4i16, Legal);
1374 setTruncStoreAction(MVT::v4i64, MVT::v4i32, Legal);
1375 setTruncStoreAction(MVT::v8i32, MVT::v8i8, Legal);
1376 setTruncStoreAction(MVT::v8i32, MVT::v8i16, Legal);
1378 setTruncStoreAction(MVT::v2i64, MVT::v2i8, Legal);
1379 setTruncStoreAction(MVT::v2i64, MVT::v2i16, Legal);
1380 setTruncStoreAction(MVT::v2i64, MVT::v2i32, Legal);
1381 setTruncStoreAction(MVT::v4i32, MVT::v4i8, Legal);
1382 setTruncStoreAction(MVT::v4i32, MVT::v4i16, Legal);
1384 setOperationAction(ISD::TRUNCATE, MVT::i1, Custom);
1385 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1386 setOperationAction(ISD::TRUNCATE, MVT::v8i32, Custom);
1387 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i1, Custom);
1388 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i1, Custom);
1389 if (Subtarget->hasDQI()) {
1390 setOperationAction(ISD::TRUNCATE, MVT::v2i1, Custom);
1391 setOperationAction(ISD::TRUNCATE, MVT::v4i1, Custom);
1393 setOperationAction(ISD::SINT_TO_FP, MVT::v8i64, Legal);
1394 setOperationAction(ISD::UINT_TO_FP, MVT::v8i64, Legal);
1395 setOperationAction(ISD::FP_TO_SINT, MVT::v8i64, Legal);
1396 setOperationAction(ISD::FP_TO_UINT, MVT::v8i64, Legal);
1397 if (Subtarget->hasVLX()) {
1398 setOperationAction(ISD::SINT_TO_FP, MVT::v4i64, Legal);
1399 setOperationAction(ISD::SINT_TO_FP, MVT::v2i64, Legal);
1400 setOperationAction(ISD::UINT_TO_FP, MVT::v4i64, Legal);
1401 setOperationAction(ISD::UINT_TO_FP, MVT::v2i64, Legal);
1402 setOperationAction(ISD::FP_TO_SINT, MVT::v4i64, Legal);
1403 setOperationAction(ISD::FP_TO_SINT, MVT::v2i64, Legal);
1404 setOperationAction(ISD::FP_TO_UINT, MVT::v4i64, Legal);
1405 setOperationAction(ISD::FP_TO_UINT, MVT::v2i64, Legal);
1408 if (Subtarget->hasVLX()) {
1409 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
1410 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Legal);
1411 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
1412 setOperationAction(ISD::FP_TO_UINT, MVT::v8i32, Legal);
1413 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
1414 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
1415 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
1416 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
1418 setOperationAction(ISD::TRUNCATE, MVT::v8i1, Custom);
1419 setOperationAction(ISD::TRUNCATE, MVT::v16i1, Custom);
1420 setOperationAction(ISD::TRUNCATE, MVT::v16i16, Custom);
1421 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i32, Custom);
1422 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i64, Custom);
1423 setOperationAction(ISD::ANY_EXTEND, MVT::v16i32, Custom);
1424 setOperationAction(ISD::ANY_EXTEND, MVT::v8i64, Custom);
1425 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i32, Custom);
1426 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i64, Custom);
1427 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i8, Custom);
1428 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i16, Custom);
1429 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1430 if (Subtarget->hasDQI()) {
1431 setOperationAction(ISD::SIGN_EXTEND, MVT::v4i32, Custom);
1432 setOperationAction(ISD::SIGN_EXTEND, MVT::v2i64, Custom);
1434 setOperationAction(ISD::FFLOOR, MVT::v16f32, Legal);
1435 setOperationAction(ISD::FFLOOR, MVT::v8f64, Legal);
1436 setOperationAction(ISD::FCEIL, MVT::v16f32, Legal);
1437 setOperationAction(ISD::FCEIL, MVT::v8f64, Legal);
1438 setOperationAction(ISD::FTRUNC, MVT::v16f32, Legal);
1439 setOperationAction(ISD::FTRUNC, MVT::v8f64, Legal);
1440 setOperationAction(ISD::FRINT, MVT::v16f32, Legal);
1441 setOperationAction(ISD::FRINT, MVT::v8f64, Legal);
1442 setOperationAction(ISD::FNEARBYINT, MVT::v16f32, Legal);
1443 setOperationAction(ISD::FNEARBYINT, MVT::v8f64, Legal);
1445 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f64, Custom);
1446 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i64, Custom);
1447 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16f32, Custom);
1448 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i32, Custom);
1449 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i1, Legal);
1451 setOperationAction(ISD::SETCC, MVT::v16i1, Custom);
1452 setOperationAction(ISD::SETCC, MVT::v8i1, Custom);
1454 setOperationAction(ISD::MUL, MVT::v8i64, Custom);
1456 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i1, Custom);
1457 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i1, Custom);
1458 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i1, Custom);
1459 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i1, Custom);
1460 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i1, Custom);
1461 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i1, Custom);
1462 setOperationAction(ISD::SELECT, MVT::v8f64, Custom);
1463 setOperationAction(ISD::SELECT, MVT::v8i64, Custom);
1464 setOperationAction(ISD::SELECT, MVT::v16f32, Custom);
1465 setOperationAction(ISD::SELECT, MVT::v16i1, Custom);
1466 setOperationAction(ISD::SELECT, MVT::v8i1, Custom);
1468 setOperationAction(ISD::SMAX, MVT::v16i32, Legal);
1469 setOperationAction(ISD::SMAX, MVT::v8i64, Legal);
1470 setOperationAction(ISD::UMAX, MVT::v16i32, Legal);
1471 setOperationAction(ISD::UMAX, MVT::v8i64, Legal);
1472 setOperationAction(ISD::SMIN, MVT::v16i32, Legal);
1473 setOperationAction(ISD::SMIN, MVT::v8i64, Legal);
1474 setOperationAction(ISD::UMIN, MVT::v16i32, Legal);
1475 setOperationAction(ISD::UMIN, MVT::v8i64, Legal);
1477 setOperationAction(ISD::ADD, MVT::v8i64, Legal);
1478 setOperationAction(ISD::ADD, MVT::v16i32, Legal);
1480 setOperationAction(ISD::SUB, MVT::v8i64, Legal);
1481 setOperationAction(ISD::SUB, MVT::v16i32, Legal);
1483 setOperationAction(ISD::MUL, MVT::v16i32, Legal);
1485 setOperationAction(ISD::SRL, MVT::v8i64, Custom);
1486 setOperationAction(ISD::SRL, MVT::v16i32, Custom);
1488 setOperationAction(ISD::SHL, MVT::v8i64, Custom);
1489 setOperationAction(ISD::SHL, MVT::v16i32, Custom);
1491 setOperationAction(ISD::SRA, MVT::v8i64, Custom);
1492 setOperationAction(ISD::SRA, MVT::v16i32, Custom);
1494 setOperationAction(ISD::AND, MVT::v8i64, Legal);
1495 setOperationAction(ISD::OR, MVT::v8i64, Legal);
1496 setOperationAction(ISD::XOR, MVT::v8i64, Legal);
1497 setOperationAction(ISD::AND, MVT::v16i32, Legal);
1498 setOperationAction(ISD::OR, MVT::v16i32, Legal);
1499 setOperationAction(ISD::XOR, MVT::v16i32, Legal);
1501 if (Subtarget->hasCDI()) {
1502 setOperationAction(ISD::CTLZ, MVT::v8i64, Legal);
1503 setOperationAction(ISD::CTLZ, MVT::v16i32, Legal);
1504 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v8i64, Legal);
1505 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v16i32, Legal);
1507 setOperationAction(ISD::CTLZ, MVT::v8i16, Custom);
1508 setOperationAction(ISD::CTLZ, MVT::v16i8, Custom);
1509 setOperationAction(ISD::CTLZ, MVT::v16i16, Custom);
1510 setOperationAction(ISD::CTLZ, MVT::v32i8, Custom);
1511 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v8i16, Custom);
1512 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v16i8, Custom);
1513 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v16i16, Custom);
1514 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v32i8, Custom);
1516 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v8i64, Custom);
1517 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v16i32, Custom);
1519 if (Subtarget->hasVLX()) {
1520 setOperationAction(ISD::CTLZ, MVT::v4i64, Legal);
1521 setOperationAction(ISD::CTLZ, MVT::v8i32, Legal);
1522 setOperationAction(ISD::CTLZ, MVT::v2i64, Legal);
1523 setOperationAction(ISD::CTLZ, MVT::v4i32, Legal);
1524 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v4i64, Legal);
1525 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v8i32, Legal);
1526 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v2i64, Legal);
1527 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v4i32, Legal);
1529 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v4i64, Custom);
1530 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v8i32, Custom);
1531 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v2i64, Custom);
1532 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v4i32, Custom);
1534 setOperationAction(ISD::CTLZ, MVT::v4i64, Custom);
1535 setOperationAction(ISD::CTLZ, MVT::v8i32, Custom);
1536 setOperationAction(ISD::CTLZ, MVT::v2i64, Custom);
1537 setOperationAction(ISD::CTLZ, MVT::v4i32, Custom);
1538 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v4i64, Custom);
1539 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v8i32, Custom);
1540 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v2i64, Custom);
1541 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v4i32, Custom);
1543 } // Subtarget->hasCDI()
1545 if (Subtarget->hasDQI()) {
1546 setOperationAction(ISD::MUL, MVT::v2i64, Legal);
1547 setOperationAction(ISD::MUL, MVT::v4i64, Legal);
1548 setOperationAction(ISD::MUL, MVT::v8i64, Legal);
1550 // Custom lower several nodes.
1551 for (MVT VT : MVT::vector_valuetypes()) {
1552 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1554 setOperationAction(ISD::AND, VT, Legal);
1555 setOperationAction(ISD::OR, VT, Legal);
1556 setOperationAction(ISD::XOR, VT, Legal);
1558 if (EltSize >= 32 && VT.getSizeInBits() <= 512) {
1559 setOperationAction(ISD::MGATHER, VT, Custom);
1560 setOperationAction(ISD::MSCATTER, VT, Custom);
1562 // Extract subvector is special because the value type
1563 // (result) is 256/128-bit but the source is 512-bit wide.
1564 if (VT.is128BitVector() || VT.is256BitVector()) {
1565 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1567 if (VT.getVectorElementType() == MVT::i1)
1568 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal);
1570 // Do not attempt to custom lower other non-512-bit vectors
1571 if (!VT.is512BitVector())
1574 if (EltSize >= 32) {
1575 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1576 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1577 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1578 setOperationAction(ISD::VSELECT, VT, Legal);
1579 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1580 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1581 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1582 setOperationAction(ISD::MLOAD, VT, Legal);
1583 setOperationAction(ISD::MSTORE, VT, Legal);
1586 for (auto VT : { MVT::v64i8, MVT::v32i16, MVT::v16i32 }) {
1587 setOperationAction(ISD::SELECT, VT, Promote);
1588 AddPromotedToType (ISD::SELECT, VT, MVT::v8i64);
1592 if (!Subtarget->useSoftFloat() && Subtarget->hasBWI()) {
1593 addRegisterClass(MVT::v32i16, &X86::VR512RegClass);
1594 addRegisterClass(MVT::v64i8, &X86::VR512RegClass);
1596 addRegisterClass(MVT::v32i1, &X86::VK32RegClass);
1597 addRegisterClass(MVT::v64i1, &X86::VK64RegClass);
1599 setOperationAction(ISD::LOAD, MVT::v32i16, Legal);
1600 setOperationAction(ISD::LOAD, MVT::v64i8, Legal);
1601 setOperationAction(ISD::SETCC, MVT::v32i1, Custom);
1602 setOperationAction(ISD::SETCC, MVT::v64i1, Custom);
1603 setOperationAction(ISD::ADD, MVT::v32i16, Legal);
1604 setOperationAction(ISD::ADD, MVT::v64i8, Legal);
1605 setOperationAction(ISD::SUB, MVT::v32i16, Legal);
1606 setOperationAction(ISD::SUB, MVT::v64i8, Legal);
1607 setOperationAction(ISD::MUL, MVT::v32i16, Legal);
1608 setOperationAction(ISD::MULHS, MVT::v32i16, Legal);
1609 setOperationAction(ISD::MULHU, MVT::v32i16, Legal);
1610 setOperationAction(ISD::CONCAT_VECTORS, MVT::v32i1, Legal);
1611 setOperationAction(ISD::CONCAT_VECTORS, MVT::v64i1, Legal);
1612 setOperationAction(ISD::CONCAT_VECTORS, MVT::v32i16, Custom);
1613 setOperationAction(ISD::CONCAT_VECTORS, MVT::v64i8, Custom);
1614 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v32i1, Custom);
1615 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v64i1, Custom);
1616 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v32i16, Custom);
1617 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v64i8, Custom);
1618 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v32i16, Custom);
1619 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v64i8, Custom);
1620 setOperationAction(ISD::SELECT, MVT::v32i1, Custom);
1621 setOperationAction(ISD::SELECT, MVT::v64i1, Custom);
1622 setOperationAction(ISD::SIGN_EXTEND, MVT::v32i8, Custom);
1623 setOperationAction(ISD::ZERO_EXTEND, MVT::v32i8, Custom);
1624 setOperationAction(ISD::SIGN_EXTEND, MVT::v32i16, Custom);
1625 setOperationAction(ISD::ZERO_EXTEND, MVT::v32i16, Custom);
1626 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v32i16, Custom);
1627 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v64i8, Custom);
1628 setOperationAction(ISD::SIGN_EXTEND, MVT::v64i8, Custom);
1629 setOperationAction(ISD::ZERO_EXTEND, MVT::v64i8, Custom);
1630 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v32i1, Custom);
1631 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v64i1, Custom);
1632 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v32i16, Custom);
1633 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v64i8, Custom);
1634 setOperationAction(ISD::VSELECT, MVT::v32i16, Legal);
1635 setOperationAction(ISD::VSELECT, MVT::v64i8, Legal);
1636 setOperationAction(ISD::TRUNCATE, MVT::v32i1, Custom);
1637 setOperationAction(ISD::TRUNCATE, MVT::v64i1, Custom);
1638 setOperationAction(ISD::TRUNCATE, MVT::v32i8, Custom);
1639 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v32i1, Custom);
1640 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v64i1, Custom);
1642 setOperationAction(ISD::SMAX, MVT::v64i8, Legal);
1643 setOperationAction(ISD::SMAX, MVT::v32i16, Legal);
1644 setOperationAction(ISD::UMAX, MVT::v64i8, Legal);
1645 setOperationAction(ISD::UMAX, MVT::v32i16, Legal);
1646 setOperationAction(ISD::SMIN, MVT::v64i8, Legal);
1647 setOperationAction(ISD::SMIN, MVT::v32i16, Legal);
1648 setOperationAction(ISD::UMIN, MVT::v64i8, Legal);
1649 setOperationAction(ISD::UMIN, MVT::v32i16, Legal);
1651 setTruncStoreAction(MVT::v32i16, MVT::v32i8, Legal);
1652 setTruncStoreAction(MVT::v16i16, MVT::v16i8, Legal);
1653 if (Subtarget->hasVLX())
1654 setTruncStoreAction(MVT::v8i16, MVT::v8i8, Legal);
1656 if (Subtarget->hasCDI()) {
1657 setOperationAction(ISD::CTLZ, MVT::v32i16, Custom);
1658 setOperationAction(ISD::CTLZ, MVT::v64i8, Custom);
1659 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v32i16, Custom);
1660 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v64i8, Custom);
1663 for (auto VT : { MVT::v64i8, MVT::v32i16 }) {
1664 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1665 setOperationAction(ISD::VSELECT, VT, Legal);
1669 if (!Subtarget->useSoftFloat() && Subtarget->hasVLX()) {
1670 addRegisterClass(MVT::v4i1, &X86::VK4RegClass);
1671 addRegisterClass(MVT::v2i1, &X86::VK2RegClass);
1673 setOperationAction(ISD::SETCC, MVT::v4i1, Custom);
1674 setOperationAction(ISD::SETCC, MVT::v2i1, Custom);
1675 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i1, Custom);
1676 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i1, Custom);
1677 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v8i1, Custom);
1678 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v4i1, Custom);
1679 setOperationAction(ISD::SELECT, MVT::v4i1, Custom);
1680 setOperationAction(ISD::SELECT, MVT::v2i1, Custom);
1681 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i1, Custom);
1682 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i1, Custom);
1683 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i1, Custom);
1684 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i1, Custom);
1686 setOperationAction(ISD::AND, MVT::v8i32, Legal);
1687 setOperationAction(ISD::OR, MVT::v8i32, Legal);
1688 setOperationAction(ISD::XOR, MVT::v8i32, Legal);
1689 setOperationAction(ISD::AND, MVT::v4i32, Legal);
1690 setOperationAction(ISD::OR, MVT::v4i32, Legal);
1691 setOperationAction(ISD::XOR, MVT::v4i32, Legal);
1692 setOperationAction(ISD::SRA, MVT::v2i64, Custom);
1693 setOperationAction(ISD::SRA, MVT::v4i64, Custom);
1695 setOperationAction(ISD::SMAX, MVT::v2i64, Legal);
1696 setOperationAction(ISD::SMAX, MVT::v4i64, Legal);
1697 setOperationAction(ISD::UMAX, MVT::v2i64, Legal);
1698 setOperationAction(ISD::UMAX, MVT::v4i64, Legal);
1699 setOperationAction(ISD::SMIN, MVT::v2i64, Legal);
1700 setOperationAction(ISD::SMIN, MVT::v4i64, Legal);
1701 setOperationAction(ISD::UMIN, MVT::v2i64, Legal);
1702 setOperationAction(ISD::UMIN, MVT::v4i64, Legal);
1705 // We want to custom lower some of our intrinsics.
1706 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
1707 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
1708 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
1709 if (!Subtarget->is64Bit())
1710 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i64, Custom);
1712 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't
1713 // handle type legalization for these operations here.
1715 // FIXME: We really should do custom legalization for addition and
1716 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better
1717 // than generic legalization for 64-bit multiplication-with-overflow, though.
1718 for (auto VT : { MVT::i8, MVT::i16, MVT::i32, MVT::i64 }) {
1719 if (VT == MVT::i64 && !Subtarget->is64Bit())
1721 // Add/Sub/Mul with overflow operations are custom lowered.
1722 setOperationAction(ISD::SADDO, VT, Custom);
1723 setOperationAction(ISD::UADDO, VT, Custom);
1724 setOperationAction(ISD::SSUBO, VT, Custom);
1725 setOperationAction(ISD::USUBO, VT, Custom);
1726 setOperationAction(ISD::SMULO, VT, Custom);
1727 setOperationAction(ISD::UMULO, VT, Custom);
1730 if (!Subtarget->is64Bit()) {
1731 // These libcalls are not available in 32-bit.
1732 setLibcallName(RTLIB::SHL_I128, nullptr);
1733 setLibcallName(RTLIB::SRL_I128, nullptr);
1734 setLibcallName(RTLIB::SRA_I128, nullptr);
1737 // Combine sin / cos into one node or libcall if possible.
1738 if (Subtarget->hasSinCos()) {
1739 setLibcallName(RTLIB::SINCOS_F32, "sincosf");
1740 setLibcallName(RTLIB::SINCOS_F64, "sincos");
1741 if (Subtarget->isTargetDarwin()) {
1742 // For MacOSX, we don't want the normal expansion of a libcall to sincos.
1743 // We want to issue a libcall to __sincos_stret to avoid memory traffic.
1744 setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
1745 setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
1749 if (Subtarget->isTargetWin64()) {
1750 setOperationAction(ISD::SDIV, MVT::i128, Custom);
1751 setOperationAction(ISD::UDIV, MVT::i128, Custom);
1752 setOperationAction(ISD::SREM, MVT::i128, Custom);
1753 setOperationAction(ISD::UREM, MVT::i128, Custom);
1754 setOperationAction(ISD::SDIVREM, MVT::i128, Custom);
1755 setOperationAction(ISD::UDIVREM, MVT::i128, Custom);
1758 // We have target-specific dag combine patterns for the following nodes:
1759 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
1760 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
1761 setTargetDAGCombine(ISD::BITCAST);
1762 setTargetDAGCombine(ISD::VSELECT);
1763 setTargetDAGCombine(ISD::SELECT);
1764 setTargetDAGCombine(ISD::SHL);
1765 setTargetDAGCombine(ISD::SRA);
1766 setTargetDAGCombine(ISD::SRL);
1767 setTargetDAGCombine(ISD::OR);
1768 setTargetDAGCombine(ISD::AND);
1769 setTargetDAGCombine(ISD::ADD);
1770 setTargetDAGCombine(ISD::FADD);
1771 setTargetDAGCombine(ISD::FSUB);
1772 setTargetDAGCombine(ISD::FMA);
1773 setTargetDAGCombine(ISD::SUB);
1774 setTargetDAGCombine(ISD::LOAD);
1775 setTargetDAGCombine(ISD::MLOAD);
1776 setTargetDAGCombine(ISD::STORE);
1777 setTargetDAGCombine(ISD::MSTORE);
1778 setTargetDAGCombine(ISD::ZERO_EXTEND);
1779 setTargetDAGCombine(ISD::ANY_EXTEND);
1780 setTargetDAGCombine(ISD::SIGN_EXTEND);
1781 setTargetDAGCombine(ISD::SIGN_EXTEND_INREG);
1782 setTargetDAGCombine(ISD::SINT_TO_FP);
1783 setTargetDAGCombine(ISD::UINT_TO_FP);
1784 setTargetDAGCombine(ISD::SETCC);
1785 setTargetDAGCombine(ISD::BUILD_VECTOR);
1786 setTargetDAGCombine(ISD::MUL);
1787 setTargetDAGCombine(ISD::XOR);
1789 computeRegisterProperties(Subtarget->getRegisterInfo());
1791 MaxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
1792 MaxStoresPerMemsetOptSize = 8;
1793 MaxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores
1794 MaxStoresPerMemcpyOptSize = 4;
1795 MaxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores
1796 MaxStoresPerMemmoveOptSize = 4;
1797 setPrefLoopAlignment(4); // 2^4 bytes.
1799 // A predictable cmov does not hurt on an in-order CPU.
1800 // FIXME: Use a CPU attribute to trigger this, not a CPU model.
1801 PredictableSelectIsExpensive = !Subtarget->isAtom();
1802 EnableExtLdPromotion = true;
1803 setPrefFunctionAlignment(4); // 2^4 bytes.
1805 verifyIntrinsicTables();
1808 // This has so far only been implemented for 64-bit MachO.
1809 bool X86TargetLowering::useLoadStackGuardNode() const {
1810 return Subtarget->isTargetMachO() && Subtarget->is64Bit();
1813 TargetLoweringBase::LegalizeTypeAction
1814 X86TargetLowering::getPreferredVectorAction(EVT VT) const {
1815 if (ExperimentalVectorWideningLegalization &&
1816 VT.getVectorNumElements() != 1 &&
1817 VT.getVectorElementType().getSimpleVT() != MVT::i1)
1818 return TypeWidenVector;
1820 return TargetLoweringBase::getPreferredVectorAction(VT);
1823 EVT X86TargetLowering::getSetCCResultType(const DataLayout &DL, LLVMContext &,
1826 return Subtarget->hasAVX512() ? MVT::i1: MVT::i8;
1828 if (VT.isSimple()) {
1829 MVT VVT = VT.getSimpleVT();
1830 const unsigned NumElts = VVT.getVectorNumElements();
1831 const MVT EltVT = VVT.getVectorElementType();
1832 if (VVT.is512BitVector()) {
1833 if (Subtarget->hasAVX512())
1834 if (EltVT == MVT::i32 || EltVT == MVT::i64 ||
1835 EltVT == MVT::f32 || EltVT == MVT::f64)
1837 case 8: return MVT::v8i1;
1838 case 16: return MVT::v16i1;
1840 if (Subtarget->hasBWI())
1841 if (EltVT == MVT::i8 || EltVT == MVT::i16)
1843 case 32: return MVT::v32i1;
1844 case 64: return MVT::v64i1;
1848 if (VVT.is256BitVector() || VVT.is128BitVector()) {
1849 if (Subtarget->hasVLX())
1850 if (EltVT == MVT::i32 || EltVT == MVT::i64 ||
1851 EltVT == MVT::f32 || EltVT == MVT::f64)
1853 case 2: return MVT::v2i1;
1854 case 4: return MVT::v4i1;
1855 case 8: return MVT::v8i1;
1857 if (Subtarget->hasBWI() && Subtarget->hasVLX())
1858 if (EltVT == MVT::i8 || EltVT == MVT::i16)
1860 case 8: return MVT::v8i1;
1861 case 16: return MVT::v16i1;
1862 case 32: return MVT::v32i1;
1867 return VT.changeVectorElementTypeToInteger();
1870 /// Helper for getByValTypeAlignment to determine
1871 /// the desired ByVal argument alignment.
1872 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) {
1875 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1876 if (VTy->getBitWidth() == 128)
1878 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1879 unsigned EltAlign = 0;
1880 getMaxByValAlign(ATy->getElementType(), EltAlign);
1881 if (EltAlign > MaxAlign)
1882 MaxAlign = EltAlign;
1883 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
1884 for (auto *EltTy : STy->elements()) {
1885 unsigned EltAlign = 0;
1886 getMaxByValAlign(EltTy, EltAlign);
1887 if (EltAlign > MaxAlign)
1888 MaxAlign = EltAlign;
1895 /// Return the desired alignment for ByVal aggregate
1896 /// function arguments in the caller parameter area. For X86, aggregates
1897 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
1898 /// are at 4-byte boundaries.
1899 unsigned X86TargetLowering::getByValTypeAlignment(Type *Ty,
1900 const DataLayout &DL) const {
1901 if (Subtarget->is64Bit()) {
1902 // Max of 8 and alignment of type.
1903 unsigned TyAlign = DL.getABITypeAlignment(Ty);
1910 if (Subtarget->hasSSE1())
1911 getMaxByValAlign(Ty, Align);
1915 /// Returns the target specific optimal type for load
1916 /// and store operations as a result of memset, memcpy, and memmove
1917 /// lowering. If DstAlign is zero that means it's safe to destination
1918 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
1919 /// means there isn't a need to check it against alignment requirement,
1920 /// probably because the source does not need to be loaded. If 'IsMemset' is
1921 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
1922 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
1923 /// source is constant so it does not need to be loaded.
1924 /// It returns EVT::Other if the type should be determined using generic
1925 /// target-independent logic.
1927 X86TargetLowering::getOptimalMemOpType(uint64_t Size,
1928 unsigned DstAlign, unsigned SrcAlign,
1929 bool IsMemset, bool ZeroMemset,
1931 MachineFunction &MF) const {
1932 const Function *F = MF.getFunction();
1933 if ((!IsMemset || ZeroMemset) &&
1934 !F->hasFnAttribute(Attribute::NoImplicitFloat)) {
1936 (!Subtarget->isUnalignedMem16Slow() ||
1937 ((DstAlign == 0 || DstAlign >= 16) &&
1938 (SrcAlign == 0 || SrcAlign >= 16)))) {
1940 // FIXME: Check if unaligned 32-byte accesses are slow.
1941 if (Subtarget->hasInt256())
1943 if (Subtarget->hasFp256())
1946 if (Subtarget->hasSSE2())
1948 if (Subtarget->hasSSE1())
1950 } else if (!MemcpyStrSrc && Size >= 8 &&
1951 !Subtarget->is64Bit() &&
1952 Subtarget->hasSSE2()) {
1953 // Do not use f64 to lower memcpy if source is string constant. It's
1954 // better to use i32 to avoid the loads.
1958 // This is a compromise. If we reach here, unaligned accesses may be slow on
1959 // this target. However, creating smaller, aligned accesses could be even
1960 // slower and would certainly be a lot more code.
1961 if (Subtarget->is64Bit() && Size >= 8)
1966 bool X86TargetLowering::isSafeMemOpType(MVT VT) const {
1968 return X86ScalarSSEf32;
1969 else if (VT == MVT::f64)
1970 return X86ScalarSSEf64;
1975 X86TargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
1980 switch (VT.getSizeInBits()) {
1982 // 8-byte and under are always assumed to be fast.
1986 *Fast = !Subtarget->isUnalignedMem16Slow();
1989 *Fast = !Subtarget->isUnalignedMem32Slow();
1991 // TODO: What about AVX-512 (512-bit) accesses?
1994 // Misaligned accesses of any size are always allowed.
1998 /// Return the entry encoding for a jump table in the
1999 /// current function. The returned value is a member of the
2000 /// MachineJumpTableInfo::JTEntryKind enum.
2001 unsigned X86TargetLowering::getJumpTableEncoding() const {
2002 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
2004 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
2005 Subtarget->isPICStyleGOT())
2006 return MachineJumpTableInfo::EK_Custom32;
2008 // Otherwise, use the normal jump table encoding heuristics.
2009 return TargetLowering::getJumpTableEncoding();
2012 bool X86TargetLowering::useSoftFloat() const {
2013 return Subtarget->useSoftFloat();
2017 X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
2018 const MachineBasicBlock *MBB,
2019 unsigned uid,MCContext &Ctx) const{
2020 assert(MBB->getParent()->getTarget().getRelocationModel() == Reloc::PIC_ &&
2021 Subtarget->isPICStyleGOT());
2022 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
2024 return MCSymbolRefExpr::create(MBB->getSymbol(),
2025 MCSymbolRefExpr::VK_GOTOFF, Ctx);
2028 /// Returns relocation base for the given PIC jumptable.
2029 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
2030 SelectionDAG &DAG) const {
2031 if (!Subtarget->is64Bit())
2032 // This doesn't have SDLoc associated with it, but is not really the
2033 // same as a Register.
2034 return DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(),
2035 getPointerTy(DAG.getDataLayout()));
2039 /// This returns the relocation base for the given PIC jumptable,
2040 /// the same as getPICJumpTableRelocBase, but as an MCExpr.
2041 const MCExpr *X86TargetLowering::
2042 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
2043 MCContext &Ctx) const {
2044 // X86-64 uses RIP relative addressing based on the jump table label.
2045 if (Subtarget->isPICStyleRIPRel())
2046 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
2048 // Otherwise, the reference is relative to the PIC base.
2049 return MCSymbolRefExpr::create(MF->getPICBaseSymbol(), Ctx);
2052 std::pair<const TargetRegisterClass *, uint8_t>
2053 X86TargetLowering::findRepresentativeClass(const TargetRegisterInfo *TRI,
2055 const TargetRegisterClass *RRC = nullptr;
2057 switch (VT.SimpleTy) {
2059 return TargetLowering::findRepresentativeClass(TRI, VT);
2060 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
2061 RRC = Subtarget->is64Bit() ? &X86::GR64RegClass : &X86::GR32RegClass;
2064 RRC = &X86::VR64RegClass;
2066 case MVT::f32: case MVT::f64:
2067 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
2068 case MVT::v4f32: case MVT::v2f64:
2069 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32:
2071 RRC = &X86::VR128RegClass;
2074 return std::make_pair(RRC, Cost);
2077 bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace,
2078 unsigned &Offset) const {
2079 if (!Subtarget->isTargetLinux())
2082 if (Subtarget->is64Bit()) {
2083 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs:
2085 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
2097 Value *X86TargetLowering::getSafeStackPointerLocation(IRBuilder<> &IRB) const {
2098 if (!Subtarget->isTargetAndroid())
2099 return TargetLowering::getSafeStackPointerLocation(IRB);
2101 // Android provides a fixed TLS slot for the SafeStack pointer. See the
2102 // definition of TLS_SLOT_SAFESTACK in
2103 // https://android.googlesource.com/platform/bionic/+/master/libc/private/bionic_tls.h
2104 unsigned AddressSpace, Offset;
2105 if (Subtarget->is64Bit()) {
2106 // %fs:0x48, unless we're using a Kernel code model, in which case it's %gs:
2108 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
2118 return ConstantExpr::getIntToPtr(
2119 ConstantInt::get(Type::getInt32Ty(IRB.getContext()), Offset),
2120 Type::getInt8PtrTy(IRB.getContext())->getPointerTo(AddressSpace));
2123 bool X86TargetLowering::isNoopAddrSpaceCast(unsigned SrcAS,
2124 unsigned DestAS) const {
2125 assert(SrcAS != DestAS && "Expected different address spaces!");
2127 return SrcAS < 256 && DestAS < 256;
2130 //===----------------------------------------------------------------------===//
2131 // Return Value Calling Convention Implementation
2132 //===----------------------------------------------------------------------===//
2134 #include "X86GenCallingConv.inc"
2136 bool X86TargetLowering::CanLowerReturn(
2137 CallingConv::ID CallConv, MachineFunction &MF, bool isVarArg,
2138 const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context) const {
2139 SmallVector<CCValAssign, 16> RVLocs;
2140 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
2141 return CCInfo.CheckReturn(Outs, RetCC_X86);
2144 const MCPhysReg *X86TargetLowering::getScratchRegisters(CallingConv::ID) const {
2145 static const MCPhysReg ScratchRegs[] = { X86::R11, 0 };
2150 X86TargetLowering::LowerReturn(SDValue Chain,
2151 CallingConv::ID CallConv, bool isVarArg,
2152 const SmallVectorImpl<ISD::OutputArg> &Outs,
2153 const SmallVectorImpl<SDValue> &OutVals,
2154 SDLoc dl, SelectionDAG &DAG) const {
2155 MachineFunction &MF = DAG.getMachineFunction();
2156 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2158 SmallVector<CCValAssign, 16> RVLocs;
2159 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, *DAG.getContext());
2160 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
2163 SmallVector<SDValue, 6> RetOps;
2164 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
2165 // Operand #1 = Bytes To Pop
2166 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(), dl,
2169 // Copy the result values into the output registers.
2170 for (unsigned i = 0; i != RVLocs.size(); ++i) {
2171 CCValAssign &VA = RVLocs[i];
2172 assert(VA.isRegLoc() && "Can only return in registers!");
2173 SDValue ValToCopy = OutVals[i];
2174 EVT ValVT = ValToCopy.getValueType();
2176 // Promote values to the appropriate types.
2177 if (VA.getLocInfo() == CCValAssign::SExt)
2178 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy);
2179 else if (VA.getLocInfo() == CCValAssign::ZExt)
2180 ValToCopy = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ValToCopy);
2181 else if (VA.getLocInfo() == CCValAssign::AExt) {
2182 if (ValVT.isVector() && ValVT.getVectorElementType() == MVT::i1)
2183 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy);
2185 ValToCopy = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ValToCopy);
2187 else if (VA.getLocInfo() == CCValAssign::BCvt)
2188 ValToCopy = DAG.getBitcast(VA.getLocVT(), ValToCopy);
2190 assert(VA.getLocInfo() != CCValAssign::FPExt &&
2191 "Unexpected FP-extend for return value.");
2193 // If this is x86-64, and we disabled SSE, we can't return FP values,
2194 // or SSE or MMX vectors.
2195 if ((ValVT == MVT::f32 || ValVT == MVT::f64 ||
2196 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) &&
2197 (Subtarget->is64Bit() && !Subtarget->hasSSE1())) {
2198 report_fatal_error("SSE register return with SSE disabled");
2200 // Likewise we can't return F64 values with SSE1 only. gcc does so, but
2201 // llvm-gcc has never done it right and no one has noticed, so this
2202 // should be OK for now.
2203 if (ValVT == MVT::f64 &&
2204 (Subtarget->is64Bit() && !Subtarget->hasSSE2()))
2205 report_fatal_error("SSE2 register return with SSE2 disabled");
2207 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
2208 // the RET instruction and handled by the FP Stackifier.
2209 if (VA.getLocReg() == X86::FP0 ||
2210 VA.getLocReg() == X86::FP1) {
2211 // If this is a copy from an xmm register to ST(0), use an FPExtend to
2212 // change the value to the FP stack register class.
2213 if (isScalarFPTypeInSSEReg(VA.getValVT()))
2214 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
2215 RetOps.push_back(ValToCopy);
2216 // Don't emit a copytoreg.
2220 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
2221 // which is returned in RAX / RDX.
2222 if (Subtarget->is64Bit()) {
2223 if (ValVT == MVT::x86mmx) {
2224 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
2225 ValToCopy = DAG.getBitcast(MVT::i64, ValToCopy);
2226 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
2228 // If we don't have SSE2 available, convert to v4f32 so the generated
2229 // register is legal.
2230 if (!Subtarget->hasSSE2())
2231 ValToCopy = DAG.getBitcast(MVT::v4f32, ValToCopy);
2236 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
2237 Flag = Chain.getValue(1);
2238 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2241 // All x86 ABIs require that for returning structs by value we copy
2242 // the sret argument into %rax/%eax (depending on ABI) for the return.
2243 // We saved the argument into a virtual register in the entry block,
2244 // so now we copy the value out and into %rax/%eax.
2246 // Checking Function.hasStructRetAttr() here is insufficient because the IR
2247 // may not have an explicit sret argument. If FuncInfo.CanLowerReturn is
2248 // false, then an sret argument may be implicitly inserted in the SelDAG. In
2249 // either case FuncInfo->setSRetReturnReg() will have been called.
2250 if (unsigned SRetReg = FuncInfo->getSRetReturnReg()) {
2251 SDValue Val = DAG.getCopyFromReg(Chain, dl, SRetReg,
2252 getPointerTy(MF.getDataLayout()));
2255 = (Subtarget->is64Bit() && !Subtarget->isTarget64BitILP32()) ?
2256 X86::RAX : X86::EAX;
2257 Chain = DAG.getCopyToReg(Chain, dl, RetValReg, Val, Flag);
2258 Flag = Chain.getValue(1);
2260 // RAX/EAX now acts like a return value.
2262 DAG.getRegister(RetValReg, getPointerTy(DAG.getDataLayout())));
2265 RetOps[0] = Chain; // Update chain.
2267 // Add the flag if we have it.
2269 RetOps.push_back(Flag);
2271 return DAG.getNode(X86ISD::RET_FLAG, dl, MVT::Other, RetOps);
2274 bool X86TargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
2275 if (N->getNumValues() != 1)
2277 if (!N->hasNUsesOfValue(1, 0))
2280 SDValue TCChain = Chain;
2281 SDNode *Copy = *N->use_begin();
2282 if (Copy->getOpcode() == ISD::CopyToReg) {
2283 // If the copy has a glue operand, we conservatively assume it isn't safe to
2284 // perform a tail call.
2285 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
2287 TCChain = Copy->getOperand(0);
2288 } else if (Copy->getOpcode() != ISD::FP_EXTEND)
2291 bool HasRet = false;
2292 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
2294 if (UI->getOpcode() != X86ISD::RET_FLAG)
2296 // If we are returning more than one value, we can definitely
2297 // not make a tail call see PR19530
2298 if (UI->getNumOperands() > 4)
2300 if (UI->getNumOperands() == 4 &&
2301 UI->getOperand(UI->getNumOperands()-1).getValueType() != MVT::Glue)
2314 X86TargetLowering::getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT,
2315 ISD::NodeType ExtendKind) const {
2317 // TODO: Is this also valid on 32-bit?
2318 if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND)
2319 ReturnMVT = MVT::i8;
2321 ReturnMVT = MVT::i32;
2323 EVT MinVT = getRegisterType(Context, ReturnMVT);
2324 return VT.bitsLT(MinVT) ? MinVT : VT;
2327 /// Lower the result values of a call into the
2328 /// appropriate copies out of appropriate physical registers.
2331 X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
2332 CallingConv::ID CallConv, bool isVarArg,
2333 const SmallVectorImpl<ISD::InputArg> &Ins,
2334 SDLoc dl, SelectionDAG &DAG,
2335 SmallVectorImpl<SDValue> &InVals) const {
2337 // Assign locations to each value returned by this call.
2338 SmallVector<CCValAssign, 16> RVLocs;
2339 bool Is64Bit = Subtarget->is64Bit();
2340 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
2342 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
2344 // Copy all of the result registers out of their specified physreg.
2345 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
2346 CCValAssign &VA = RVLocs[i];
2347 EVT CopyVT = VA.getLocVT();
2349 // If this is x86-64, and we disabled SSE, we can't return FP values
2350 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
2351 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) {
2352 report_fatal_error("SSE register return with SSE disabled");
2355 // If we prefer to use the value in xmm registers, copy it out as f80 and
2356 // use a truncate to move it from fp stack reg to xmm reg.
2357 bool RoundAfterCopy = false;
2358 if ((VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1) &&
2359 isScalarFPTypeInSSEReg(VA.getValVT())) {
2361 RoundAfterCopy = (CopyVT != VA.getLocVT());
2364 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
2365 CopyVT, InFlag).getValue(1);
2366 SDValue Val = Chain.getValue(0);
2369 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
2370 // This truncation won't change the value.
2371 DAG.getIntPtrConstant(1, dl));
2373 if (VA.isExtInLoc() && VA.getValVT().getScalarType() == MVT::i1)
2374 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
2376 InFlag = Chain.getValue(2);
2377 InVals.push_back(Val);
2383 //===----------------------------------------------------------------------===//
2384 // C & StdCall & Fast Calling Convention implementation
2385 //===----------------------------------------------------------------------===//
2386 // StdCall calling convention seems to be standard for many Windows' API
2387 // routines and around. It differs from C calling convention just a little:
2388 // callee should clean up the stack, not caller. Symbols should be also
2389 // decorated in some fancy way :) It doesn't support any vector arguments.
2390 // For info on fast calling convention see Fast Calling Convention (tail call)
2391 // implementation LowerX86_32FastCCCallTo.
2393 /// CallIsStructReturn - Determines whether a call uses struct return
2395 enum StructReturnType {
2400 static StructReturnType
2401 callIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
2403 return NotStructReturn;
2405 const ISD::ArgFlagsTy &Flags = Outs[0].Flags;
2406 if (!Flags.isSRet())
2407 return NotStructReturn;
2408 if (Flags.isInReg())
2409 return RegStructReturn;
2410 return StackStructReturn;
2413 /// Determines whether a function uses struct return semantics.
2414 static StructReturnType
2415 argsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
2417 return NotStructReturn;
2419 const ISD::ArgFlagsTy &Flags = Ins[0].Flags;
2420 if (!Flags.isSRet())
2421 return NotStructReturn;
2422 if (Flags.isInReg())
2423 return RegStructReturn;
2424 return StackStructReturn;
2427 /// Make a copy of an aggregate at address specified by "Src" to address
2428 /// "Dst" with size and alignment information specified by the specific
2429 /// parameter attribute. The copy will be passed as a byval function parameter.
2431 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
2432 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
2434 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), dl, MVT::i32);
2436 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
2437 /*isVolatile*/false, /*AlwaysInline=*/true,
2438 /*isTailCall*/false,
2439 MachinePointerInfo(), MachinePointerInfo());
2442 /// Return true if the calling convention is one that we can guarantee TCO for.
2443 static bool canGuaranteeTCO(CallingConv::ID CC) {
2444 return (CC == CallingConv::Fast || CC == CallingConv::GHC ||
2445 CC == CallingConv::HiPE || CC == CallingConv::HHVM);
2448 /// Return true if we might ever do TCO for calls with this calling convention.
2449 static bool mayTailCallThisCC(CallingConv::ID CC) {
2451 // C calling conventions:
2452 case CallingConv::C:
2453 case CallingConv::X86_64_Win64:
2454 case CallingConv::X86_64_SysV:
2455 // Callee pop conventions:
2456 case CallingConv::X86_ThisCall:
2457 case CallingConv::X86_StdCall:
2458 case CallingConv::X86_VectorCall:
2459 case CallingConv::X86_FastCall:
2462 return canGuaranteeTCO(CC);
2466 /// Return true if the function is being made into a tailcall target by
2467 /// changing its ABI.
2468 static bool shouldGuaranteeTCO(CallingConv::ID CC, bool GuaranteedTailCallOpt) {
2469 return GuaranteedTailCallOpt && canGuaranteeTCO(CC);
2472 bool X86TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
2474 CI->getParent()->getParent()->getFnAttribute("disable-tail-calls");
2475 if (!CI->isTailCall() || Attr.getValueAsString() == "true")
2479 CallingConv::ID CalleeCC = CS.getCallingConv();
2480 if (!mayTailCallThisCC(CalleeCC))
2487 X86TargetLowering::LowerMemArgument(SDValue Chain,
2488 CallingConv::ID CallConv,
2489 const SmallVectorImpl<ISD::InputArg> &Ins,
2490 SDLoc dl, SelectionDAG &DAG,
2491 const CCValAssign &VA,
2492 MachineFrameInfo *MFI,
2494 // Create the nodes corresponding to a load from this parameter slot.
2495 ISD::ArgFlagsTy Flags = Ins[i].Flags;
2496 bool AlwaysUseMutable = shouldGuaranteeTCO(
2497 CallConv, DAG.getTarget().Options.GuaranteedTailCallOpt);
2498 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
2501 // If value is passed by pointer we have address passed instead of the value
2503 bool ExtendedInMem = VA.isExtInLoc() &&
2504 VA.getValVT().getScalarType() == MVT::i1;
2506 if (VA.getLocInfo() == CCValAssign::Indirect || ExtendedInMem)
2507 ValVT = VA.getLocVT();
2509 ValVT = VA.getValVT();
2511 // FIXME: For now, all byval parameter objects are marked mutable. This can be
2512 // changed with more analysis.
2513 // In case of tail call optimization mark all arguments mutable. Since they
2514 // could be overwritten by lowering of arguments in case of a tail call.
2515 if (Flags.isByVal()) {
2516 unsigned Bytes = Flags.getByValSize();
2517 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects.
2518 int FI = MFI->CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable);
2519 return DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
2521 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
2522 VA.getLocMemOffset(), isImmutable);
2523 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
2524 SDValue Val = DAG.getLoad(
2525 ValVT, dl, Chain, FIN,
2526 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI), false,
2528 return ExtendedInMem ?
2529 DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val) : Val;
2533 // FIXME: Get this from tablegen.
2534 static ArrayRef<MCPhysReg> get64BitArgumentGPRs(CallingConv::ID CallConv,
2535 const X86Subtarget *Subtarget) {
2536 assert(Subtarget->is64Bit());
2538 if (Subtarget->isCallingConvWin64(CallConv)) {
2539 static const MCPhysReg GPR64ArgRegsWin64[] = {
2540 X86::RCX, X86::RDX, X86::R8, X86::R9
2542 return makeArrayRef(std::begin(GPR64ArgRegsWin64), std::end(GPR64ArgRegsWin64));
2545 static const MCPhysReg GPR64ArgRegs64Bit[] = {
2546 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
2548 return makeArrayRef(std::begin(GPR64ArgRegs64Bit), std::end(GPR64ArgRegs64Bit));
2551 // FIXME: Get this from tablegen.
2552 static ArrayRef<MCPhysReg> get64BitArgumentXMMs(MachineFunction &MF,
2553 CallingConv::ID CallConv,
2554 const X86Subtarget *Subtarget) {
2555 assert(Subtarget->is64Bit());
2556 if (Subtarget->isCallingConvWin64(CallConv)) {
2557 // The XMM registers which might contain var arg parameters are shadowed
2558 // in their paired GPR. So we only need to save the GPR to their home
2560 // TODO: __vectorcall will change this.
2564 const Function *Fn = MF.getFunction();
2565 bool NoImplicitFloatOps = Fn->hasFnAttribute(Attribute::NoImplicitFloat);
2566 bool isSoftFloat = Subtarget->useSoftFloat();
2567 assert(!(isSoftFloat && NoImplicitFloatOps) &&
2568 "SSE register cannot be used when SSE is disabled!");
2569 if (isSoftFloat || NoImplicitFloatOps || !Subtarget->hasSSE1())
2570 // Kernel mode asks for SSE to be disabled, so there are no XMM argument
2574 static const MCPhysReg XMMArgRegs64Bit[] = {
2575 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2576 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2578 return makeArrayRef(std::begin(XMMArgRegs64Bit), std::end(XMMArgRegs64Bit));
2581 SDValue X86TargetLowering::LowerFormalArguments(
2582 SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
2583 const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc dl, SelectionDAG &DAG,
2584 SmallVectorImpl<SDValue> &InVals) const {
2585 MachineFunction &MF = DAG.getMachineFunction();
2586 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2587 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
2589 const Function* Fn = MF.getFunction();
2590 if (Fn->hasExternalLinkage() &&
2591 Subtarget->isTargetCygMing() &&
2592 Fn->getName() == "main")
2593 FuncInfo->setForceFramePointer(true);
2595 MachineFrameInfo *MFI = MF.getFrameInfo();
2596 bool Is64Bit = Subtarget->is64Bit();
2597 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2599 assert(!(isVarArg && canGuaranteeTCO(CallConv)) &&
2600 "Var args not supported with calling convention fastcc, ghc or hipe");
2602 // Assign locations to all of the incoming arguments.
2603 SmallVector<CCValAssign, 16> ArgLocs;
2604 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
2606 // Allocate shadow area for Win64
2608 CCInfo.AllocateStack(32, 8);
2610 CCInfo.AnalyzeFormalArguments(Ins, CC_X86);
2612 unsigned LastVal = ~0U;
2614 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2615 CCValAssign &VA = ArgLocs[i];
2616 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
2618 assert(VA.getValNo() != LastVal &&
2619 "Don't support value assigned to multiple locs yet");
2621 LastVal = VA.getValNo();
2623 if (VA.isRegLoc()) {
2624 EVT RegVT = VA.getLocVT();
2625 const TargetRegisterClass *RC;
2626 if (RegVT == MVT::i32)
2627 RC = &X86::GR32RegClass;
2628 else if (Is64Bit && RegVT == MVT::i64)
2629 RC = &X86::GR64RegClass;
2630 else if (RegVT == MVT::f32)
2631 RC = &X86::FR32RegClass;
2632 else if (RegVT == MVT::f64)
2633 RC = &X86::FR64RegClass;
2634 else if (RegVT.is512BitVector())
2635 RC = &X86::VR512RegClass;
2636 else if (RegVT.is256BitVector())
2637 RC = &X86::VR256RegClass;
2638 else if (RegVT.is128BitVector())
2639 RC = &X86::VR128RegClass;
2640 else if (RegVT == MVT::x86mmx)
2641 RC = &X86::VR64RegClass;
2642 else if (RegVT == MVT::i1)
2643 RC = &X86::VK1RegClass;
2644 else if (RegVT == MVT::v8i1)
2645 RC = &X86::VK8RegClass;
2646 else if (RegVT == MVT::v16i1)
2647 RC = &X86::VK16RegClass;
2648 else if (RegVT == MVT::v32i1)
2649 RC = &X86::VK32RegClass;
2650 else if (RegVT == MVT::v64i1)
2651 RC = &X86::VK64RegClass;
2653 llvm_unreachable("Unknown argument type!");
2655 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2656 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
2658 // If this is an 8 or 16-bit value, it is really passed promoted to 32
2659 // bits. Insert an assert[sz]ext to capture this, then truncate to the
2661 if (VA.getLocInfo() == CCValAssign::SExt)
2662 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
2663 DAG.getValueType(VA.getValVT()));
2664 else if (VA.getLocInfo() == CCValAssign::ZExt)
2665 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
2666 DAG.getValueType(VA.getValVT()));
2667 else if (VA.getLocInfo() == CCValAssign::BCvt)
2668 ArgValue = DAG.getBitcast(VA.getValVT(), ArgValue);
2670 if (VA.isExtInLoc()) {
2671 // Handle MMX values passed in XMM regs.
2672 if (RegVT.isVector() && VA.getValVT().getScalarType() != MVT::i1)
2673 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(), ArgValue);
2675 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
2678 assert(VA.isMemLoc());
2679 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
2682 // If value is passed via pointer - do a load.
2683 if (VA.getLocInfo() == CCValAssign::Indirect)
2684 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue,
2685 MachinePointerInfo(), false, false, false, 0);
2687 InVals.push_back(ArgValue);
2690 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2691 // All x86 ABIs require that for returning structs by value we copy the
2692 // sret argument into %rax/%eax (depending on ABI) for the return. Save
2693 // the argument into a virtual register so that we can access it from the
2695 if (Ins[i].Flags.isSRet()) {
2696 unsigned Reg = FuncInfo->getSRetReturnReg();
2698 MVT PtrTy = getPointerTy(DAG.getDataLayout());
2699 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(PtrTy));
2700 FuncInfo->setSRetReturnReg(Reg);
2702 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[i]);
2703 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
2708 unsigned StackSize = CCInfo.getNextStackOffset();
2709 // Align stack specially for tail calls.
2710 if (shouldGuaranteeTCO(CallConv,
2711 MF.getTarget().Options.GuaranteedTailCallOpt))
2712 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
2714 // If the function takes variable number of arguments, make a frame index for
2715 // the start of the first vararg value... for expansion of llvm.va_start. We
2716 // can skip this if there are no va_start calls.
2717 if (MFI->hasVAStart() &&
2718 (Is64Bit || (CallConv != CallingConv::X86_FastCall &&
2719 CallConv != CallingConv::X86_ThisCall))) {
2720 FuncInfo->setVarArgsFrameIndex(
2721 MFI->CreateFixedObject(1, StackSize, true));
2724 MachineModuleInfo &MMI = MF.getMMI();
2726 // Figure out if XMM registers are in use.
2727 assert(!(Subtarget->useSoftFloat() &&
2728 Fn->hasFnAttribute(Attribute::NoImplicitFloat)) &&
2729 "SSE register cannot be used when SSE is disabled!");
2731 // 64-bit calling conventions support varargs and register parameters, so we
2732 // have to do extra work to spill them in the prologue.
2733 if (Is64Bit && isVarArg && MFI->hasVAStart()) {
2734 // Find the first unallocated argument registers.
2735 ArrayRef<MCPhysReg> ArgGPRs = get64BitArgumentGPRs(CallConv, Subtarget);
2736 ArrayRef<MCPhysReg> ArgXMMs = get64BitArgumentXMMs(MF, CallConv, Subtarget);
2737 unsigned NumIntRegs = CCInfo.getFirstUnallocated(ArgGPRs);
2738 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(ArgXMMs);
2739 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) &&
2740 "SSE register cannot be used when SSE is disabled!");
2742 // Gather all the live in physical registers.
2743 SmallVector<SDValue, 6> LiveGPRs;
2744 SmallVector<SDValue, 8> LiveXMMRegs;
2746 for (MCPhysReg Reg : ArgGPRs.slice(NumIntRegs)) {
2747 unsigned GPR = MF.addLiveIn(Reg, &X86::GR64RegClass);
2749 DAG.getCopyFromReg(Chain, dl, GPR, MVT::i64));
2751 if (!ArgXMMs.empty()) {
2752 unsigned AL = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
2753 ALVal = DAG.getCopyFromReg(Chain, dl, AL, MVT::i8);
2754 for (MCPhysReg Reg : ArgXMMs.slice(NumXMMRegs)) {
2755 unsigned XMMReg = MF.addLiveIn(Reg, &X86::VR128RegClass);
2756 LiveXMMRegs.push_back(
2757 DAG.getCopyFromReg(Chain, dl, XMMReg, MVT::v4f32));
2762 // Get to the caller-allocated home save location. Add 8 to account
2763 // for the return address.
2764 int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
2765 FuncInfo->setRegSaveFrameIndex(
2766 MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false));
2767 // Fixup to set vararg frame on shadow area (4 x i64).
2769 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex());
2771 // For X86-64, if there are vararg parameters that are passed via
2772 // registers, then we must store them to their spots on the stack so
2773 // they may be loaded by deferencing the result of va_next.
2774 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8);
2775 FuncInfo->setVarArgsFPOffset(ArgGPRs.size() * 8 + NumXMMRegs * 16);
2776 FuncInfo->setRegSaveFrameIndex(MFI->CreateStackObject(
2777 ArgGPRs.size() * 8 + ArgXMMs.size() * 16, 16, false));
2780 // Store the integer parameter registers.
2781 SmallVector<SDValue, 8> MemOps;
2782 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
2783 getPointerTy(DAG.getDataLayout()));
2784 unsigned Offset = FuncInfo->getVarArgsGPOffset();
2785 for (SDValue Val : LiveGPRs) {
2786 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(DAG.getDataLayout()),
2787 RSFIN, DAG.getIntPtrConstant(Offset, dl));
2789 DAG.getStore(Val.getValue(1), dl, Val, FIN,
2790 MachinePointerInfo::getFixedStack(
2791 DAG.getMachineFunction(),
2792 FuncInfo->getRegSaveFrameIndex(), Offset),
2794 MemOps.push_back(Store);
2798 if (!ArgXMMs.empty() && NumXMMRegs != ArgXMMs.size()) {
2799 // Now store the XMM (fp + vector) parameter registers.
2800 SmallVector<SDValue, 12> SaveXMMOps;
2801 SaveXMMOps.push_back(Chain);
2802 SaveXMMOps.push_back(ALVal);
2803 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2804 FuncInfo->getRegSaveFrameIndex(), dl));
2805 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2806 FuncInfo->getVarArgsFPOffset(), dl));
2807 SaveXMMOps.insert(SaveXMMOps.end(), LiveXMMRegs.begin(),
2809 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
2810 MVT::Other, SaveXMMOps));
2813 if (!MemOps.empty())
2814 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
2817 if (isVarArg && MFI->hasMustTailInVarArgFunc()) {
2818 // Find the largest legal vector type.
2819 MVT VecVT = MVT::Other;
2820 // FIXME: Only some x86_32 calling conventions support AVX512.
2821 if (Subtarget->hasAVX512() &&
2822 (Is64Bit || (CallConv == CallingConv::X86_VectorCall ||
2823 CallConv == CallingConv::Intel_OCL_BI)))
2824 VecVT = MVT::v16f32;
2825 else if (Subtarget->hasAVX())
2827 else if (Subtarget->hasSSE2())
2830 // We forward some GPRs and some vector types.
2831 SmallVector<MVT, 2> RegParmTypes;
2832 MVT IntVT = Is64Bit ? MVT::i64 : MVT::i32;
2833 RegParmTypes.push_back(IntVT);
2834 if (VecVT != MVT::Other)
2835 RegParmTypes.push_back(VecVT);
2837 // Compute the set of forwarded registers. The rest are scratch.
2838 SmallVectorImpl<ForwardedRegister> &Forwards =
2839 FuncInfo->getForwardedMustTailRegParms();
2840 CCInfo.analyzeMustTailForwardedRegisters(Forwards, RegParmTypes, CC_X86);
2842 // Conservatively forward AL on x86_64, since it might be used for varargs.
2843 if (Is64Bit && !CCInfo.isAllocated(X86::AL)) {
2844 unsigned ALVReg = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
2845 Forwards.push_back(ForwardedRegister(ALVReg, X86::AL, MVT::i8));
2848 // Copy all forwards from physical to virtual registers.
2849 for (ForwardedRegister &F : Forwards) {
2850 // FIXME: Can we use a less constrained schedule?
2851 SDValue RegVal = DAG.getCopyFromReg(Chain, dl, F.VReg, F.VT);
2852 F.VReg = MF.getRegInfo().createVirtualRegister(getRegClassFor(F.VT));
2853 Chain = DAG.getCopyToReg(Chain, dl, F.VReg, RegVal);
2857 // Some CCs need callee pop.
2858 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2859 MF.getTarget().Options.GuaranteedTailCallOpt)) {
2860 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything.
2862 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing.
2863 // If this is an sret function, the return should pop the hidden pointer.
2864 if (!Is64Bit && !canGuaranteeTCO(CallConv) &&
2865 !Subtarget->getTargetTriple().isOSMSVCRT() &&
2866 argsAreStructReturn(Ins) == StackStructReturn)
2867 FuncInfo->setBytesToPopOnReturn(4);
2871 // RegSaveFrameIndex is X86-64 only.
2872 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
2873 if (CallConv == CallingConv::X86_FastCall ||
2874 CallConv == CallingConv::X86_ThisCall)
2875 // fastcc functions can't have varargs.
2876 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA);
2879 FuncInfo->setArgumentStackSize(StackSize);
2881 if (MMI.hasWinEHFuncInfo(Fn) && Is64Bit &&
2882 classifyEHPersonality(Fn->getPersonalityFn()) ==
2883 EHPersonality::MSVC_CXX) {
2884 int UnwindHelpFI = MFI->CreateStackObject(8, 8, /*isSS=*/false);
2885 SDValue StackSlot = DAG.getFrameIndex(UnwindHelpFI, MVT::i64);
2886 MMI.getWinEHFuncInfo(MF.getFunction()).UnwindHelpFrameIdx = UnwindHelpFI;
2887 SDValue Neg2 = DAG.getConstant(-2, dl, MVT::i64);
2888 Chain = DAG.getStore(Chain, dl, Neg2, StackSlot,
2889 MachinePointerInfo::getFixedStack(
2890 DAG.getMachineFunction(), UnwindHelpFI),
2891 /*isVolatile=*/true,
2892 /*isNonTemporal=*/false, /*Alignment=*/0);
2899 X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
2900 SDValue StackPtr, SDValue Arg,
2901 SDLoc dl, SelectionDAG &DAG,
2902 const CCValAssign &VA,
2903 ISD::ArgFlagsTy Flags) const {
2904 unsigned LocMemOffset = VA.getLocMemOffset();
2905 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset, dl);
2906 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(DAG.getDataLayout()),
2908 if (Flags.isByVal())
2909 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
2911 return DAG.getStore(
2912 Chain, dl, Arg, PtrOff,
2913 MachinePointerInfo::getStack(DAG.getMachineFunction(), LocMemOffset),
2917 /// Emit a load of return address if tail call
2918 /// optimization is performed and it is required.
2920 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
2921 SDValue &OutRetAddr, SDValue Chain,
2922 bool IsTailCall, bool Is64Bit,
2923 int FPDiff, SDLoc dl) const {
2924 // Adjust the Return address stack slot.
2925 EVT VT = getPointerTy(DAG.getDataLayout());
2926 OutRetAddr = getReturnAddressFrameIndex(DAG);
2928 // Load the "old" Return address.
2929 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(),
2930 false, false, false, 0);
2931 return SDValue(OutRetAddr.getNode(), 1);
2934 /// Emit a store of the return address if tail call
2935 /// optimization is performed and it is required (FPDiff!=0).
2936 static SDValue EmitTailCallStoreRetAddr(SelectionDAG &DAG, MachineFunction &MF,
2937 SDValue Chain, SDValue RetAddrFrIdx,
2938 EVT PtrVT, unsigned SlotSize,
2939 int FPDiff, SDLoc dl) {
2940 // Store the return address to the appropriate stack slot.
2941 if (!FPDiff) return Chain;
2942 // Calculate the new stack slot for the return address.
2943 int NewReturnAddrFI =
2944 MF.getFrameInfo()->CreateFixedObject(SlotSize, (int64_t)FPDiff - SlotSize,
2946 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, PtrVT);
2947 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
2948 MachinePointerInfo::getFixedStack(
2949 DAG.getMachineFunction(), NewReturnAddrFI),
2954 /// Returns a vector_shuffle mask for an movs{s|d}, movd
2955 /// operation of specified width.
2956 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
2958 unsigned NumElems = VT.getVectorNumElements();
2959 SmallVector<int, 8> Mask;
2960 Mask.push_back(NumElems);
2961 for (unsigned i = 1; i != NumElems; ++i)
2963 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
2967 X86TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
2968 SmallVectorImpl<SDValue> &InVals) const {
2969 SelectionDAG &DAG = CLI.DAG;
2971 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
2972 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
2973 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
2974 SDValue Chain = CLI.Chain;
2975 SDValue Callee = CLI.Callee;
2976 CallingConv::ID CallConv = CLI.CallConv;
2977 bool &isTailCall = CLI.IsTailCall;
2978 bool isVarArg = CLI.IsVarArg;
2980 MachineFunction &MF = DAG.getMachineFunction();
2981 bool Is64Bit = Subtarget->is64Bit();
2982 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2983 StructReturnType SR = callIsStructReturn(Outs);
2984 bool IsSibcall = false;
2985 X86MachineFunctionInfo *X86Info = MF.getInfo<X86MachineFunctionInfo>();
2986 auto Attr = MF.getFunction()->getFnAttribute("disable-tail-calls");
2988 if (Attr.getValueAsString() == "true")
2991 if (Subtarget->isPICStyleGOT() &&
2992 !MF.getTarget().Options.GuaranteedTailCallOpt) {
2993 // If we are using a GOT, disable tail calls to external symbols with
2994 // default visibility. Tail calling such a symbol requires using a GOT
2995 // relocation, which forces early binding of the symbol. This breaks code
2996 // that require lazy function symbol resolution. Using musttail or
2997 // GuaranteedTailCallOpt will override this.
2998 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
2999 if (!G || (!G->getGlobal()->hasLocalLinkage() &&
3000 G->getGlobal()->hasDefaultVisibility()))
3004 bool IsMustTail = CLI.CS && CLI.CS->isMustTailCall();
3006 // Force this to be a tail call. The verifier rules are enough to ensure
3007 // that we can lower this successfully without moving the return address
3010 } else if (isTailCall) {
3011 // Check if it's really possible to do a tail call.
3012 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
3013 isVarArg, SR != NotStructReturn,
3014 MF.getFunction()->hasStructRetAttr(), CLI.RetTy,
3015 Outs, OutVals, Ins, DAG);
3017 // Sibcalls are automatically detected tailcalls which do not require
3019 if (!MF.getTarget().Options.GuaranteedTailCallOpt && isTailCall)
3026 assert(!(isVarArg && canGuaranteeTCO(CallConv)) &&
3027 "Var args not supported with calling convention fastcc, ghc or hipe");
3029 // Analyze operands of the call, assigning locations to each operand.
3030 SmallVector<CCValAssign, 16> ArgLocs;
3031 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
3033 // Allocate shadow area for Win64
3035 CCInfo.AllocateStack(32, 8);
3037 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3039 // Get a count of how many bytes are to be pushed on the stack.
3040 unsigned NumBytes = CCInfo.getAlignedCallFrameSize();
3042 // This is a sibcall. The memory operands are available in caller's
3043 // own caller's stack.
3045 else if (MF.getTarget().Options.GuaranteedTailCallOpt &&
3046 canGuaranteeTCO(CallConv))
3047 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
3050 if (isTailCall && !IsSibcall && !IsMustTail) {
3051 // Lower arguments at fp - stackoffset + fpdiff.
3052 unsigned NumBytesCallerPushed = X86Info->getBytesToPopOnReturn();
3054 FPDiff = NumBytesCallerPushed - NumBytes;
3056 // Set the delta of movement of the returnaddr stackslot.
3057 // But only set if delta is greater than previous delta.
3058 if (FPDiff < X86Info->getTCReturnAddrDelta())
3059 X86Info->setTCReturnAddrDelta(FPDiff);
3062 unsigned NumBytesToPush = NumBytes;
3063 unsigned NumBytesToPop = NumBytes;
3065 // If we have an inalloca argument, all stack space has already been allocated
3066 // for us and be right at the top of the stack. We don't support multiple
3067 // arguments passed in memory when using inalloca.
3068 if (!Outs.empty() && Outs.back().Flags.isInAlloca()) {
3070 if (!ArgLocs.back().isMemLoc())
3071 report_fatal_error("cannot use inalloca attribute on a register "
3073 if (ArgLocs.back().getLocMemOffset() != 0)
3074 report_fatal_error("any parameter with the inalloca attribute must be "
3075 "the only memory argument");
3079 Chain = DAG.getCALLSEQ_START(
3080 Chain, DAG.getIntPtrConstant(NumBytesToPush, dl, true), dl);
3082 SDValue RetAddrFrIdx;
3083 // Load return address for tail calls.
3084 if (isTailCall && FPDiff)
3085 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall,
3086 Is64Bit, FPDiff, dl);
3088 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
3089 SmallVector<SDValue, 8> MemOpChains;
3092 // Walk the register/memloc assignments, inserting copies/loads. In the case
3093 // of tail call optimization arguments are handle later.
3094 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
3095 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3096 // Skip inalloca arguments, they have already been written.
3097 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3098 if (Flags.isInAlloca())
3101 CCValAssign &VA = ArgLocs[i];
3102 EVT RegVT = VA.getLocVT();
3103 SDValue Arg = OutVals[i];
3104 bool isByVal = Flags.isByVal();
3106 // Promote the value if needed.
3107 switch (VA.getLocInfo()) {
3108 default: llvm_unreachable("Unknown loc info!");
3109 case CCValAssign::Full: break;
3110 case CCValAssign::SExt:
3111 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
3113 case CCValAssign::ZExt:
3114 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
3116 case CCValAssign::AExt:
3117 if (Arg.getValueType().isVector() &&
3118 Arg.getValueType().getVectorElementType() == MVT::i1)
3119 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
3120 else if (RegVT.is128BitVector()) {
3121 // Special case: passing MMX values in XMM registers.
3122 Arg = DAG.getBitcast(MVT::i64, Arg);
3123 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
3124 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
3126 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
3128 case CCValAssign::BCvt:
3129 Arg = DAG.getBitcast(RegVT, Arg);
3131 case CCValAssign::Indirect: {
3132 // Store the argument.
3133 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
3134 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
3135 Chain = DAG.getStore(
3136 Chain, dl, Arg, SpillSlot,
3137 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI),
3144 if (VA.isRegLoc()) {
3145 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
3146 if (isVarArg && IsWin64) {
3147 // Win64 ABI requires argument XMM reg to be copied to the corresponding
3148 // shadow reg if callee is a varargs function.
3149 unsigned ShadowReg = 0;
3150 switch (VA.getLocReg()) {
3151 case X86::XMM0: ShadowReg = X86::RCX; break;
3152 case X86::XMM1: ShadowReg = X86::RDX; break;
3153 case X86::XMM2: ShadowReg = X86::R8; break;
3154 case X86::XMM3: ShadowReg = X86::R9; break;
3157 RegsToPass.push_back(std::make_pair(ShadowReg, Arg));
3159 } else if (!IsSibcall && (!isTailCall || isByVal)) {
3160 assert(VA.isMemLoc());
3161 if (!StackPtr.getNode())
3162 StackPtr = DAG.getCopyFromReg(Chain, dl, RegInfo->getStackRegister(),
3163 getPointerTy(DAG.getDataLayout()));
3164 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
3165 dl, DAG, VA, Flags));
3169 if (!MemOpChains.empty())
3170 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
3172 if (Subtarget->isPICStyleGOT()) {
3173 // ELF / PIC requires GOT in the EBX register before function calls via PLT
3176 RegsToPass.push_back(std::make_pair(
3177 unsigned(X86::EBX), DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(),
3178 getPointerTy(DAG.getDataLayout()))));
3180 // If we are tail calling and generating PIC/GOT style code load the
3181 // address of the callee into ECX. The value in ecx is used as target of
3182 // the tail jump. This is done to circumvent the ebx/callee-saved problem
3183 // for tail calls on PIC/GOT architectures. Normally we would just put the
3184 // address of GOT into ebx and then call target@PLT. But for tail calls
3185 // ebx would be restored (since ebx is callee saved) before jumping to the
3188 // Note: The actual moving to ECX is done further down.
3189 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
3190 if (G && !G->getGlobal()->hasLocalLinkage() &&
3191 G->getGlobal()->hasDefaultVisibility())
3192 Callee = LowerGlobalAddress(Callee, DAG);
3193 else if (isa<ExternalSymbolSDNode>(Callee))
3194 Callee = LowerExternalSymbol(Callee, DAG);
3198 if (Is64Bit && isVarArg && !IsWin64 && !IsMustTail) {
3199 // From AMD64 ABI document:
3200 // For calls that may call functions that use varargs or stdargs
3201 // (prototype-less calls or calls to functions containing ellipsis (...) in
3202 // the declaration) %al is used as hidden argument to specify the number
3203 // of SSE registers used. The contents of %al do not need to match exactly
3204 // the number of registers, but must be an ubound on the number of SSE
3205 // registers used and is in the range 0 - 8 inclusive.
3207 // Count the number of XMM registers allocated.
3208 static const MCPhysReg XMMArgRegs[] = {
3209 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
3210 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
3212 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs);
3213 assert((Subtarget->hasSSE1() || !NumXMMRegs)
3214 && "SSE registers cannot be used when SSE is disabled");
3216 RegsToPass.push_back(std::make_pair(unsigned(X86::AL),
3217 DAG.getConstant(NumXMMRegs, dl,
3221 if (isVarArg && IsMustTail) {
3222 const auto &Forwards = X86Info->getForwardedMustTailRegParms();
3223 for (const auto &F : Forwards) {
3224 SDValue Val = DAG.getCopyFromReg(Chain, dl, F.VReg, F.VT);
3225 RegsToPass.push_back(std::make_pair(unsigned(F.PReg), Val));
3229 // For tail calls lower the arguments to the 'real' stack slots. Sibcalls
3230 // don't need this because the eligibility check rejects calls that require
3231 // shuffling arguments passed in memory.
3232 if (!IsSibcall && isTailCall) {
3233 // Force all the incoming stack arguments to be loaded from the stack
3234 // before any new outgoing arguments are stored to the stack, because the
3235 // outgoing stack slots may alias the incoming argument stack slots, and
3236 // the alias isn't otherwise explicit. This is slightly more conservative
3237 // than necessary, because it means that each store effectively depends
3238 // on every argument instead of just those arguments it would clobber.
3239 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
3241 SmallVector<SDValue, 8> MemOpChains2;
3244 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3245 CCValAssign &VA = ArgLocs[i];
3248 assert(VA.isMemLoc());
3249 SDValue Arg = OutVals[i];
3250 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3251 // Skip inalloca arguments. They don't require any work.
3252 if (Flags.isInAlloca())
3254 // Create frame index.
3255 int32_t Offset = VA.getLocMemOffset()+FPDiff;
3256 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
3257 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
3258 FIN = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
3260 if (Flags.isByVal()) {
3261 // Copy relative to framepointer.
3262 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset(), dl);
3263 if (!StackPtr.getNode())
3264 StackPtr = DAG.getCopyFromReg(Chain, dl, RegInfo->getStackRegister(),
3265 getPointerTy(DAG.getDataLayout()));
3266 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(DAG.getDataLayout()),
3269 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
3273 // Store relative to framepointer.
3274 MemOpChains2.push_back(DAG.getStore(
3275 ArgChain, dl, Arg, FIN,
3276 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI),
3281 if (!MemOpChains2.empty())
3282 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains2);
3284 // Store the return address to the appropriate stack slot.
3285 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx,
3286 getPointerTy(DAG.getDataLayout()),
3287 RegInfo->getSlotSize(), FPDiff, dl);
3290 // Build a sequence of copy-to-reg nodes chained together with token chain
3291 // and flag operands which copy the outgoing args into registers.
3293 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
3294 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
3295 RegsToPass[i].second, InFlag);
3296 InFlag = Chain.getValue(1);
3299 if (DAG.getTarget().getCodeModel() == CodeModel::Large) {
3300 assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
3301 // In the 64-bit large code model, we have to make all calls
3302 // through a register, since the call instruction's 32-bit
3303 // pc-relative offset may not be large enough to hold the whole
3305 } else if (Callee->getOpcode() == ISD::GlobalAddress) {
3306 // If the callee is a GlobalAddress node (quite common, every direct call
3307 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
3309 GlobalAddressSDNode* G = cast<GlobalAddressSDNode>(Callee);
3311 // We should use extra load for direct calls to dllimported functions in
3313 const GlobalValue *GV = G->getGlobal();
3314 if (!GV->hasDLLImportStorageClass()) {
3315 unsigned char OpFlags = 0;
3316 bool ExtraLoad = false;
3317 unsigned WrapperKind = ISD::DELETED_NODE;
3319 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
3320 // external symbols most go through the PLT in PIC mode. If the symbol
3321 // has hidden or protected visibility, or if it is static or local, then
3322 // we don't need to use the PLT - we can directly call it.
3323 if (Subtarget->isTargetELF() &&
3324 DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
3325 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
3326 OpFlags = X86II::MO_PLT;
3327 } else if (Subtarget->isPICStyleStubAny() &&
3328 !GV->isStrongDefinitionForLinker() &&
3329 (!Subtarget->getTargetTriple().isMacOSX() ||
3330 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
3331 // PC-relative references to external symbols should go through $stub,
3332 // unless we're building with the leopard linker or later, which
3333 // automatically synthesizes these stubs.
3334 OpFlags = X86II::MO_DARWIN_STUB;
3335 } else if (Subtarget->isPICStyleRIPRel() && isa<Function>(GV) &&
3336 cast<Function>(GV)->hasFnAttribute(Attribute::NonLazyBind)) {
3337 // If the function is marked as non-lazy, generate an indirect call
3338 // which loads from the GOT directly. This avoids runtime overhead
3339 // at the cost of eager binding (and one extra byte of encoding).
3340 OpFlags = X86II::MO_GOTPCREL;
3341 WrapperKind = X86ISD::WrapperRIP;
3345 Callee = DAG.getTargetGlobalAddress(
3346 GV, dl, getPointerTy(DAG.getDataLayout()), G->getOffset(), OpFlags);
3348 // Add a wrapper if needed.
3349 if (WrapperKind != ISD::DELETED_NODE)
3350 Callee = DAG.getNode(X86ISD::WrapperRIP, dl,
3351 getPointerTy(DAG.getDataLayout()), Callee);
3352 // Add extra indirection if needed.
3354 Callee = DAG.getLoad(
3355 getPointerTy(DAG.getDataLayout()), dl, DAG.getEntryNode(), Callee,
3356 MachinePointerInfo::getGOT(DAG.getMachineFunction()), false, false,
3359 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
3360 unsigned char OpFlags = 0;
3362 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to
3363 // external symbols should go through the PLT.
3364 if (Subtarget->isTargetELF() &&
3365 DAG.getTarget().getRelocationModel() == Reloc::PIC_) {
3366 OpFlags = X86II::MO_PLT;
3367 } else if (Subtarget->isPICStyleStubAny() &&
3368 (!Subtarget->getTargetTriple().isMacOSX() ||
3369 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
3370 // PC-relative references to external symbols should go through $stub,
3371 // unless we're building with the leopard linker or later, which
3372 // automatically synthesizes these stubs.
3373 OpFlags = X86II::MO_DARWIN_STUB;
3376 Callee = DAG.getTargetExternalSymbol(
3377 S->getSymbol(), getPointerTy(DAG.getDataLayout()), OpFlags);
3378 } else if (Subtarget->isTarget64BitILP32() &&
3379 Callee->getValueType(0) == MVT::i32) {
3380 // Zero-extend the 32-bit Callee address into a 64-bit according to x32 ABI
3381 Callee = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, Callee);
3384 // Returns a chain & a flag for retval copy to use.
3385 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
3386 SmallVector<SDValue, 8> Ops;
3388 if (!IsSibcall && isTailCall) {
3389 Chain = DAG.getCALLSEQ_END(Chain,
3390 DAG.getIntPtrConstant(NumBytesToPop, dl, true),
3391 DAG.getIntPtrConstant(0, dl, true), InFlag, dl);
3392 InFlag = Chain.getValue(1);
3395 Ops.push_back(Chain);
3396 Ops.push_back(Callee);
3399 Ops.push_back(DAG.getConstant(FPDiff, dl, MVT::i32));
3401 // Add argument registers to the end of the list so that they are known live
3403 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
3404 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
3405 RegsToPass[i].second.getValueType()));
3407 // Add a register mask operand representing the call-preserved registers.
3408 const uint32_t *Mask = RegInfo->getCallPreservedMask(MF, CallConv);
3409 assert(Mask && "Missing call preserved mask for calling convention");
3411 // If this is an invoke in a 32-bit function using a funclet-based
3412 // personality, assume the function clobbers all registers. If an exception
3413 // is thrown, the runtime will not restore CSRs.
3414 // FIXME: Model this more precisely so that we can register allocate across
3415 // the normal edge and spill and fill across the exceptional edge.
3416 if (!Is64Bit && CLI.CS && CLI.CS->isInvoke()) {
3417 const Function *CallerFn = MF.getFunction();
3418 EHPersonality Pers =
3419 CallerFn->hasPersonalityFn()
3420 ? classifyEHPersonality(CallerFn->getPersonalityFn())
3421 : EHPersonality::Unknown;
3422 if (isFuncletEHPersonality(Pers))
3423 Mask = RegInfo->getNoPreservedMask();
3426 Ops.push_back(DAG.getRegisterMask(Mask));
3428 if (InFlag.getNode())
3429 Ops.push_back(InFlag);
3433 //// If this is the first return lowered for this function, add the regs
3434 //// to the liveout set for the function.
3435 // This isn't right, although it's probably harmless on x86; liveouts
3436 // should be computed from returns not tail calls. Consider a void
3437 // function making a tail call to a function returning int.
3438 MF.getFrameInfo()->setHasTailCall();
3439 return DAG.getNode(X86ISD::TC_RETURN, dl, NodeTys, Ops);
3442 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, Ops);
3443 InFlag = Chain.getValue(1);
3445 // Create the CALLSEQ_END node.
3446 unsigned NumBytesForCalleeToPop;
3447 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
3448 DAG.getTarget().Options.GuaranteedTailCallOpt))
3449 NumBytesForCalleeToPop = NumBytes; // Callee pops everything
3450 else if (!Is64Bit && !canGuaranteeTCO(CallConv) &&
3451 !Subtarget->getTargetTriple().isOSMSVCRT() &&
3452 SR == StackStructReturn)
3453 // If this is a call to a struct-return function, the callee
3454 // pops the hidden struct pointer, so we have to push it back.
3455 // This is common for Darwin/X86, Linux & Mingw32 targets.
3456 // For MSVC Win32 targets, the caller pops the hidden struct pointer.
3457 NumBytesForCalleeToPop = 4;
3459 NumBytesForCalleeToPop = 0; // Callee pops nothing.
3461 // Returns a flag for retval copy to use.
3463 Chain = DAG.getCALLSEQ_END(Chain,
3464 DAG.getIntPtrConstant(NumBytesToPop, dl, true),
3465 DAG.getIntPtrConstant(NumBytesForCalleeToPop, dl,
3468 InFlag = Chain.getValue(1);
3471 // Handle result values, copying them out of physregs into vregs that we
3473 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
3474 Ins, dl, DAG, InVals);
3477 //===----------------------------------------------------------------------===//
3478 // Fast Calling Convention (tail call) implementation
3479 //===----------------------------------------------------------------------===//
3481 // Like std call, callee cleans arguments, convention except that ECX is
3482 // reserved for storing the tail called function address. Only 2 registers are
3483 // free for argument passing (inreg). Tail call optimization is performed
3485 // * tailcallopt is enabled
3486 // * caller/callee are fastcc
3487 // On X86_64 architecture with GOT-style position independent code only local
3488 // (within module) calls are supported at the moment.
3489 // To keep the stack aligned according to platform abi the function
3490 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
3491 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
3492 // If a tail called function callee has more arguments than the caller the
3493 // caller needs to make sure that there is room to move the RETADDR to. This is
3494 // achieved by reserving an area the size of the argument delta right after the
3495 // original RETADDR, but before the saved framepointer or the spilled registers
3496 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
3508 /// Make the stack size align e.g 16n + 12 aligned for a 16-byte align
3511 X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
3512 SelectionDAG& DAG) const {
3513 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
3514 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
3515 unsigned StackAlignment = TFI.getStackAlignment();
3516 uint64_t AlignMask = StackAlignment - 1;
3517 int64_t Offset = StackSize;
3518 unsigned SlotSize = RegInfo->getSlotSize();
3519 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
3520 // Number smaller than 12 so just add the difference.
3521 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
3523 // Mask out lower bits, add stackalignment once plus the 12 bytes.
3524 Offset = ((~AlignMask) & Offset) + StackAlignment +
3525 (StackAlignment-SlotSize);
3530 /// Return true if the given stack call argument is already available in the
3531 /// same position (relatively) of the caller's incoming argument stack.
3533 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
3534 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
3535 const X86InstrInfo *TII) {
3536 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
3538 if (Arg.getOpcode() == ISD::CopyFromReg) {
3539 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
3540 if (!TargetRegisterInfo::isVirtualRegister(VR))
3542 MachineInstr *Def = MRI->getVRegDef(VR);
3545 if (!Flags.isByVal()) {
3546 if (!TII->isLoadFromStackSlot(Def, FI))
3549 unsigned Opcode = Def->getOpcode();
3550 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r ||
3551 Opcode == X86::LEA64_32r) &&
3552 Def->getOperand(1).isFI()) {
3553 FI = Def->getOperand(1).getIndex();
3554 Bytes = Flags.getByValSize();
3558 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
3559 if (Flags.isByVal())
3560 // ByVal argument is passed in as a pointer but it's now being
3561 // dereferenced. e.g.
3562 // define @foo(%struct.X* %A) {
3563 // tail call @bar(%struct.X* byval %A)
3566 SDValue Ptr = Ld->getBasePtr();
3567 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
3570 FI = FINode->getIndex();
3571 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) {
3572 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg);
3573 FI = FINode->getIndex();
3574 Bytes = Flags.getByValSize();
3578 assert(FI != INT_MAX);
3579 if (!MFI->isFixedObjectIndex(FI))
3581 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
3584 /// Check whether the call is eligible for tail call optimization. Targets
3585 /// that want to do tail call optimization should implement this function.
3586 bool X86TargetLowering::IsEligibleForTailCallOptimization(
3587 SDValue Callee, CallingConv::ID CalleeCC, bool isVarArg,
3588 bool isCalleeStructRet, bool isCallerStructRet, Type *RetTy,
3589 const SmallVectorImpl<ISD::OutputArg> &Outs,
3590 const SmallVectorImpl<SDValue> &OutVals,
3591 const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG &DAG) const {
3592 if (!mayTailCallThisCC(CalleeCC))
3595 // If -tailcallopt is specified, make fastcc functions tail-callable.
3596 MachineFunction &MF = DAG.getMachineFunction();
3597 const Function *CallerF = MF.getFunction();
3599 // If the function return type is x86_fp80 and the callee return type is not,
3600 // then the FP_EXTEND of the call result is not a nop. It's not safe to
3601 // perform a tailcall optimization here.
3602 if (CallerF->getReturnType()->isX86_FP80Ty() && !RetTy->isX86_FP80Ty())
3605 CallingConv::ID CallerCC = CallerF->getCallingConv();
3606 bool CCMatch = CallerCC == CalleeCC;
3607 bool IsCalleeWin64 = Subtarget->isCallingConvWin64(CalleeCC);
3608 bool IsCallerWin64 = Subtarget->isCallingConvWin64(CallerCC);
3610 // Win64 functions have extra shadow space for argument homing. Don't do the
3611 // sibcall if the caller and callee have mismatched expectations for this
3613 if (IsCalleeWin64 != IsCallerWin64)
3616 if (DAG.getTarget().Options.GuaranteedTailCallOpt) {
3617 if (canGuaranteeTCO(CalleeCC) && CCMatch)
3622 // Look for obvious safe cases to perform tail call optimization that do not
3623 // require ABI changes. This is what gcc calls sibcall.
3625 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
3626 // emit a special epilogue.
3627 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
3628 if (RegInfo->needsStackRealignment(MF))
3631 // Also avoid sibcall optimization if either caller or callee uses struct
3632 // return semantics.
3633 if (isCalleeStructRet || isCallerStructRet)
3636 // Do not sibcall optimize vararg calls unless all arguments are passed via
3638 if (isVarArg && !Outs.empty()) {
3639 // Optimizing for varargs on Win64 is unlikely to be safe without
3640 // additional testing.
3641 if (IsCalleeWin64 || IsCallerWin64)
3644 SmallVector<CCValAssign, 16> ArgLocs;
3645 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
3648 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3649 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
3650 if (!ArgLocs[i].isRegLoc())
3654 // If the call result is in ST0 / ST1, it needs to be popped off the x87
3655 // stack. Therefore, if it's not used by the call it is not safe to optimize
3656 // this into a sibcall.
3657 bool Unused = false;
3658 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
3665 SmallVector<CCValAssign, 16> RVLocs;
3666 CCState CCInfo(CalleeCC, false, DAG.getMachineFunction(), RVLocs,
3668 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
3669 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
3670 CCValAssign &VA = RVLocs[i];
3671 if (VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1)
3676 // If the calling conventions do not match, then we'd better make sure the
3677 // results are returned in the same way as what the caller expects.
3679 SmallVector<CCValAssign, 16> RVLocs1;
3680 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(), RVLocs1,
3682 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86);
3684 SmallVector<CCValAssign, 16> RVLocs2;
3685 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(), RVLocs2,
3687 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86);
3689 if (RVLocs1.size() != RVLocs2.size())
3691 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
3692 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
3694 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
3696 if (RVLocs1[i].isRegLoc()) {
3697 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
3700 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
3706 unsigned StackArgsSize = 0;
3708 // If the callee takes no arguments then go on to check the results of the
3710 if (!Outs.empty()) {
3711 // Check if stack adjustment is needed. For now, do not do this if any
3712 // argument is passed on the stack.
3713 SmallVector<CCValAssign, 16> ArgLocs;
3714 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
3717 // Allocate shadow area for Win64
3719 CCInfo.AllocateStack(32, 8);
3721 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3722 StackArgsSize = CCInfo.getNextStackOffset();
3724 if (CCInfo.getNextStackOffset()) {
3725 // Check if the arguments are already laid out in the right way as
3726 // the caller's fixed stack objects.
3727 MachineFrameInfo *MFI = MF.getFrameInfo();
3728 const MachineRegisterInfo *MRI = &MF.getRegInfo();
3729 const X86InstrInfo *TII = Subtarget->getInstrInfo();
3730 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3731 CCValAssign &VA = ArgLocs[i];
3732 SDValue Arg = OutVals[i];
3733 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3734 if (VA.getLocInfo() == CCValAssign::Indirect)
3736 if (!VA.isRegLoc()) {
3737 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
3744 // If the tailcall address may be in a register, then make sure it's
3745 // possible to register allocate for it. In 32-bit, the call address can
3746 // only target EAX, EDX, or ECX since the tail call must be scheduled after
3747 // callee-saved registers are restored. These happen to be the same
3748 // registers used to pass 'inreg' arguments so watch out for those.
3749 if (!Subtarget->is64Bit() &&
3750 ((!isa<GlobalAddressSDNode>(Callee) &&
3751 !isa<ExternalSymbolSDNode>(Callee)) ||
3752 DAG.getTarget().getRelocationModel() == Reloc::PIC_)) {
3753 unsigned NumInRegs = 0;
3754 // In PIC we need an extra register to formulate the address computation
3756 unsigned MaxInRegs =
3757 (DAG.getTarget().getRelocationModel() == Reloc::PIC_) ? 2 : 3;
3759 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3760 CCValAssign &VA = ArgLocs[i];
3763 unsigned Reg = VA.getLocReg();
3766 case X86::EAX: case X86::EDX: case X86::ECX:
3767 if (++NumInRegs == MaxInRegs)
3775 bool CalleeWillPop =
3776 X86::isCalleePop(CalleeCC, Subtarget->is64Bit(), isVarArg,
3777 MF.getTarget().Options.GuaranteedTailCallOpt);
3779 if (unsigned BytesToPop =
3780 MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn()) {
3781 // If we have bytes to pop, the callee must pop them.
3782 bool CalleePopMatches = CalleeWillPop && BytesToPop == StackArgsSize;
3783 if (!CalleePopMatches)
3785 } else if (CalleeWillPop && StackArgsSize > 0) {
3786 // If we don't have bytes to pop, make sure the callee doesn't pop any.
3794 X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
3795 const TargetLibraryInfo *libInfo) const {
3796 return X86::createFastISel(funcInfo, libInfo);
3799 //===----------------------------------------------------------------------===//
3800 // Other Lowering Hooks
3801 //===----------------------------------------------------------------------===//
3803 static bool MayFoldLoad(SDValue Op) {
3804 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode());
3807 static bool MayFoldIntoStore(SDValue Op) {
3808 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin());
3811 static bool isTargetShuffle(unsigned Opcode) {
3813 default: return false;
3814 case X86ISD::BLENDI:
3815 case X86ISD::PSHUFB:
3816 case X86ISD::PSHUFD:
3817 case X86ISD::PSHUFHW:
3818 case X86ISD::PSHUFLW:
3820 case X86ISD::PALIGNR:
3821 case X86ISD::MOVLHPS:
3822 case X86ISD::MOVLHPD:
3823 case X86ISD::MOVHLPS:
3824 case X86ISD::MOVLPS:
3825 case X86ISD::MOVLPD:
3826 case X86ISD::MOVSHDUP:
3827 case X86ISD::MOVSLDUP:
3828 case X86ISD::MOVDDUP:
3831 case X86ISD::UNPCKL:
3832 case X86ISD::UNPCKH:
3833 case X86ISD::VPERMILPI:
3834 case X86ISD::VPERM2X128:
3835 case X86ISD::VPERMI:
3836 case X86ISD::VPERMV:
3837 case X86ISD::VPERMV3:
3842 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, MVT VT,
3843 SDValue V1, unsigned TargetMask,
3844 SelectionDAG &DAG) {
3846 default: llvm_unreachable("Unknown x86 shuffle node");
3847 case X86ISD::PSHUFD:
3848 case X86ISD::PSHUFHW:
3849 case X86ISD::PSHUFLW:
3850 case X86ISD::VPERMILPI:
3851 case X86ISD::VPERMI:
3852 return DAG.getNode(Opc, dl, VT, V1,
3853 DAG.getConstant(TargetMask, dl, MVT::i8));
3857 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, MVT VT,
3858 SDValue V1, SDValue V2, SelectionDAG &DAG) {
3860 default: llvm_unreachable("Unknown x86 shuffle node");
3861 case X86ISD::MOVLHPS:
3862 case X86ISD::MOVLHPD:
3863 case X86ISD::MOVHLPS:
3864 case X86ISD::MOVLPS:
3865 case X86ISD::MOVLPD:
3868 case X86ISD::UNPCKL:
3869 case X86ISD::UNPCKH:
3870 return DAG.getNode(Opc, dl, VT, V1, V2);
3874 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
3875 MachineFunction &MF = DAG.getMachineFunction();
3876 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
3877 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
3878 int ReturnAddrIndex = FuncInfo->getRAIndex();
3880 if (ReturnAddrIndex == 0) {
3881 // Set up a frame object for the return address.
3882 unsigned SlotSize = RegInfo->getSlotSize();
3883 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize,
3886 FuncInfo->setRAIndex(ReturnAddrIndex);
3889 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy(DAG.getDataLayout()));
3892 bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
3893 bool hasSymbolicDisplacement) {
3894 // Offset should fit into 32 bit immediate field.
3895 if (!isInt<32>(Offset))
3898 // If we don't have a symbolic displacement - we don't have any extra
3900 if (!hasSymbolicDisplacement)
3903 // FIXME: Some tweaks might be needed for medium code model.
3904 if (M != CodeModel::Small && M != CodeModel::Kernel)
3907 // For small code model we assume that latest object is 16MB before end of 31
3908 // bits boundary. We may also accept pretty large negative constants knowing
3909 // that all objects are in the positive half of address space.
3910 if (M == CodeModel::Small && Offset < 16*1024*1024)
3913 // For kernel code model we know that all object resist in the negative half
3914 // of 32bits address space. We may not accept negative offsets, since they may
3915 // be just off and we may accept pretty large positive ones.
3916 if (M == CodeModel::Kernel && Offset >= 0)
3922 /// Determines whether the callee is required to pop its own arguments.
3923 /// Callee pop is necessary to support tail calls.
3924 bool X86::isCalleePop(CallingConv::ID CallingConv,
3925 bool is64Bit, bool IsVarArg, bool GuaranteeTCO) {
3926 // If GuaranteeTCO is true, we force some calls to be callee pop so that we
3927 // can guarantee TCO.
3928 if (!IsVarArg && shouldGuaranteeTCO(CallingConv, GuaranteeTCO))
3931 switch (CallingConv) {
3934 case CallingConv::X86_StdCall:
3935 case CallingConv::X86_FastCall:
3936 case CallingConv::X86_ThisCall:
3937 case CallingConv::X86_VectorCall:
3942 /// \brief Return true if the condition is an unsigned comparison operation.
3943 static bool isX86CCUnsigned(unsigned X86CC) {
3945 default: llvm_unreachable("Invalid integer condition!");
3946 case X86::COND_E: return true;
3947 case X86::COND_G: return false;
3948 case X86::COND_GE: return false;
3949 case X86::COND_L: return false;
3950 case X86::COND_LE: return false;
3951 case X86::COND_NE: return true;
3952 case X86::COND_B: return true;
3953 case X86::COND_A: return true;
3954 case X86::COND_BE: return true;
3955 case X86::COND_AE: return true;
3959 /// Do a one-to-one translation of a ISD::CondCode to the X86-specific
3960 /// condition code, returning the condition code and the LHS/RHS of the
3961 /// comparison to make.
3962 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, SDLoc DL, bool isFP,
3963 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
3965 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
3966 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
3967 // X > -1 -> X == 0, jump !sign.
3968 RHS = DAG.getConstant(0, DL, RHS.getValueType());
3969 return X86::COND_NS;
3971 if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
3972 // X < 0 -> X == 0, jump on sign.
3975 if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
3977 RHS = DAG.getConstant(0, DL, RHS.getValueType());
3978 return X86::COND_LE;
3982 switch (SetCCOpcode) {
3983 default: llvm_unreachable("Invalid integer condition!");
3984 case ISD::SETEQ: return X86::COND_E;
3985 case ISD::SETGT: return X86::COND_G;
3986 case ISD::SETGE: return X86::COND_GE;
3987 case ISD::SETLT: return X86::COND_L;
3988 case ISD::SETLE: return X86::COND_LE;
3989 case ISD::SETNE: return X86::COND_NE;
3990 case ISD::SETULT: return X86::COND_B;
3991 case ISD::SETUGT: return X86::COND_A;
3992 case ISD::SETULE: return X86::COND_BE;
3993 case ISD::SETUGE: return X86::COND_AE;
3997 // First determine if it is required or is profitable to flip the operands.
3999 // If LHS is a foldable load, but RHS is not, flip the condition.
4000 if (ISD::isNON_EXTLoad(LHS.getNode()) &&
4001 !ISD::isNON_EXTLoad(RHS.getNode())) {
4002 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
4003 std::swap(LHS, RHS);
4006 switch (SetCCOpcode) {
4012 std::swap(LHS, RHS);
4016 // On a floating point condition, the flags are set as follows:
4018 // 0 | 0 | 0 | X > Y
4019 // 0 | 0 | 1 | X < Y
4020 // 1 | 0 | 0 | X == Y
4021 // 1 | 1 | 1 | unordered
4022 switch (SetCCOpcode) {
4023 default: llvm_unreachable("Condcode should be pre-legalized away");
4025 case ISD::SETEQ: return X86::COND_E;
4026 case ISD::SETOLT: // flipped
4028 case ISD::SETGT: return X86::COND_A;
4029 case ISD::SETOLE: // flipped
4031 case ISD::SETGE: return X86::COND_AE;
4032 case ISD::SETUGT: // flipped
4034 case ISD::SETLT: return X86::COND_B;
4035 case ISD::SETUGE: // flipped
4037 case ISD::SETLE: return X86::COND_BE;
4039 case ISD::SETNE: return X86::COND_NE;
4040 case ISD::SETUO: return X86::COND_P;
4041 case ISD::SETO: return X86::COND_NP;
4043 case ISD::SETUNE: return X86::COND_INVALID;
4047 /// Is there a floating point cmov for the specific X86 condition code?
4048 /// Current x86 isa includes the following FP cmov instructions:
4049 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
4050 static bool hasFPCMov(unsigned X86CC) {
4066 /// Returns true if the target can instruction select the
4067 /// specified FP immediate natively. If false, the legalizer will
4068 /// materialize the FP immediate as a load from a constant pool.
4069 bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
4070 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
4071 if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
4077 bool X86TargetLowering::shouldReduceLoadWidth(SDNode *Load,
4078 ISD::LoadExtType ExtTy,
4080 // "ELF Handling for Thread-Local Storage" specifies that R_X86_64_GOTTPOFF
4081 // relocation target a movq or addq instruction: don't let the load shrink.
4082 SDValue BasePtr = cast<LoadSDNode>(Load)->getBasePtr();
4083 if (BasePtr.getOpcode() == X86ISD::WrapperRIP)
4084 if (const auto *GA = dyn_cast<GlobalAddressSDNode>(BasePtr.getOperand(0)))
4085 return GA->getTargetFlags() != X86II::MO_GOTTPOFF;
4089 /// \brief Returns true if it is beneficial to convert a load of a constant
4090 /// to just the constant itself.
4091 bool X86TargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
4093 assert(Ty->isIntegerTy());
4095 unsigned BitSize = Ty->getPrimitiveSizeInBits();
4096 if (BitSize == 0 || BitSize > 64)
4101 bool X86TargetLowering::isExtractSubvectorCheap(EVT ResVT,
4102 unsigned Index) const {
4103 if (!isOperationLegalOrCustom(ISD::EXTRACT_SUBVECTOR, ResVT))
4106 return (Index == 0 || Index == ResVT.getVectorNumElements());
4109 bool X86TargetLowering::isCheapToSpeculateCttz() const {
4110 // Speculate cttz only if we can directly use TZCNT.
4111 return Subtarget->hasBMI();
4114 bool X86TargetLowering::isCheapToSpeculateCtlz() const {
4115 // Speculate ctlz only if we can directly use LZCNT.
4116 return Subtarget->hasLZCNT();
4119 /// Return true if every element in Mask, beginning
4120 /// from position Pos and ending in Pos+Size is undef.
4121 static bool isUndefInRange(ArrayRef<int> Mask, unsigned Pos, unsigned Size) {
4122 for (unsigned i = Pos, e = Pos + Size; i != e; ++i)
4128 /// Return true if Val is undef or if its value falls within the
4129 /// specified range (L, H].
4130 static bool isUndefOrInRange(int Val, int Low, int Hi) {
4131 return (Val < 0) || (Val >= Low && Val < Hi);
4134 /// Val is either less than zero (undef) or equal to the specified value.
4135 static bool isUndefOrEqual(int Val, int CmpVal) {
4136 return (Val < 0 || Val == CmpVal);
4139 /// Return true if every element in Mask, beginning
4140 /// from position Pos and ending in Pos+Size, falls within the specified
4141 /// sequential range (Low, Low+Size]. or is undef.
4142 static bool isSequentialOrUndefInRange(ArrayRef<int> Mask,
4143 unsigned Pos, unsigned Size, int Low) {
4144 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low)
4145 if (!isUndefOrEqual(Mask[i], Low))
4150 /// Return true if the specified EXTRACT_SUBVECTOR operand specifies a vector
4151 /// extract that is suitable for instruction that extract 128 or 256 bit vectors
4152 static bool isVEXTRACTIndex(SDNode *N, unsigned vecWidth) {
4153 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4154 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4157 // The index should be aligned on a vecWidth-bit boundary.
4159 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4161 MVT VT = N->getSimpleValueType(0);
4162 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4163 bool Result = (Index * ElSize) % vecWidth == 0;
4168 /// Return true if the specified INSERT_SUBVECTOR
4169 /// operand specifies a subvector insert that is suitable for input to
4170 /// insertion of 128 or 256-bit subvectors
4171 static bool isVINSERTIndex(SDNode *N, unsigned vecWidth) {
4172 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4173 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4175 // The index should be aligned on a vecWidth-bit boundary.
4177 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4179 MVT VT = N->getSimpleValueType(0);
4180 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4181 bool Result = (Index * ElSize) % vecWidth == 0;
4186 bool X86::isVINSERT128Index(SDNode *N) {
4187 return isVINSERTIndex(N, 128);
4190 bool X86::isVINSERT256Index(SDNode *N) {
4191 return isVINSERTIndex(N, 256);
4194 bool X86::isVEXTRACT128Index(SDNode *N) {
4195 return isVEXTRACTIndex(N, 128);
4198 bool X86::isVEXTRACT256Index(SDNode *N) {
4199 return isVEXTRACTIndex(N, 256);
4202 static unsigned getExtractVEXTRACTImmediate(SDNode *N, unsigned vecWidth) {
4203 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4204 assert(isa<ConstantSDNode>(N->getOperand(1).getNode()) &&
4205 "Illegal extract subvector for VEXTRACT");
4208 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4210 MVT VecVT = N->getOperand(0).getSimpleValueType();
4211 MVT ElVT = VecVT.getVectorElementType();
4213 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4214 return Index / NumElemsPerChunk;
4217 static unsigned getInsertVINSERTImmediate(SDNode *N, unsigned vecWidth) {
4218 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4219 assert(isa<ConstantSDNode>(N->getOperand(2).getNode()) &&
4220 "Illegal insert subvector for VINSERT");
4223 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4225 MVT VecVT = N->getSimpleValueType(0);
4226 MVT ElVT = VecVT.getVectorElementType();
4228 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4229 return Index / NumElemsPerChunk;
4232 /// Return the appropriate immediate to extract the specified
4233 /// EXTRACT_SUBVECTOR index with VEXTRACTF128 and VINSERTI128 instructions.
4234 unsigned X86::getExtractVEXTRACT128Immediate(SDNode *N) {
4235 return getExtractVEXTRACTImmediate(N, 128);
4238 /// Return the appropriate immediate to extract the specified
4239 /// EXTRACT_SUBVECTOR index with VEXTRACTF64x4 and VINSERTI64x4 instructions.
4240 unsigned X86::getExtractVEXTRACT256Immediate(SDNode *N) {
4241 return getExtractVEXTRACTImmediate(N, 256);
4244 /// Return the appropriate immediate to insert at the specified
4245 /// INSERT_SUBVECTOR index with VINSERTF128 and VINSERTI128 instructions.
4246 unsigned X86::getInsertVINSERT128Immediate(SDNode *N) {
4247 return getInsertVINSERTImmediate(N, 128);
4250 /// Return the appropriate immediate to insert at the specified
4251 /// INSERT_SUBVECTOR index with VINSERTF46x4 and VINSERTI64x4 instructions.
4252 unsigned X86::getInsertVINSERT256Immediate(SDNode *N) {
4253 return getInsertVINSERTImmediate(N, 256);
4256 /// Returns true if V is a constant integer zero.
4257 static bool isZero(SDValue V) {
4258 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
4259 return C && C->isNullValue();
4262 /// Returns true if Elt is a constant zero or a floating point constant +0.0.
4263 bool X86::isZeroNode(SDValue Elt) {
4266 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Elt))
4267 return CFP->getValueAPF().isPosZero();
4271 // Build a vector of constants
4272 // Use an UNDEF node if MaskElt == -1.
4273 // Spilt 64-bit constants in the 32-bit mode.
4274 static SDValue getConstVector(ArrayRef<int> Values, MVT VT,
4276 SDLoc dl, bool IsMask = false) {
4278 SmallVector<SDValue, 32> Ops;
4281 MVT ConstVecVT = VT;
4282 unsigned NumElts = VT.getVectorNumElements();
4283 bool In64BitMode = DAG.getTargetLoweringInfo().isTypeLegal(MVT::i64);
4284 if (!In64BitMode && VT.getVectorElementType() == MVT::i64) {
4285 ConstVecVT = MVT::getVectorVT(MVT::i32, NumElts * 2);
4289 MVT EltVT = ConstVecVT.getVectorElementType();
4290 for (unsigned i = 0; i < NumElts; ++i) {
4291 bool IsUndef = Values[i] < 0 && IsMask;
4292 SDValue OpNode = IsUndef ? DAG.getUNDEF(EltVT) :
4293 DAG.getConstant(Values[i], dl, EltVT);
4294 Ops.push_back(OpNode);
4296 Ops.push_back(IsUndef ? DAG.getUNDEF(EltVT) :
4297 DAG.getConstant(0, dl, EltVT));
4299 SDValue ConstsNode = DAG.getNode(ISD::BUILD_VECTOR, dl, ConstVecVT, Ops);
4301 ConstsNode = DAG.getBitcast(VT, ConstsNode);
4305 /// Returns a vector of specified type with all zero elements.
4306 static SDValue getZeroVector(EVT VT, const X86Subtarget *Subtarget,
4307 SelectionDAG &DAG, SDLoc dl) {
4308 assert(VT.isVector() && "Expected a vector type");
4310 // Always build SSE zero vectors as <4 x i32> bitcasted
4311 // to their dest type. This ensures they get CSE'd.
4313 if (VT.is128BitVector()) { // SSE
4314 if (Subtarget->hasSSE2()) { // SSE2
4315 SDValue Cst = DAG.getConstant(0, dl, MVT::i32);
4316 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4318 SDValue Cst = DAG.getConstantFP(+0.0, dl, MVT::f32);
4319 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
4321 } else if (VT.is256BitVector()) { // AVX
4322 if (Subtarget->hasInt256()) { // AVX2
4323 SDValue Cst = DAG.getConstant(0, dl, MVT::i32);
4324 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4325 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
4327 // 256-bit logic and arithmetic instructions in AVX are all
4328 // floating-point, no support for integer ops. Emit fp zeroed vectors.
4329 SDValue Cst = DAG.getConstantFP(+0.0, dl, MVT::f32);
4330 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4331 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops);
4333 } else if (VT.is512BitVector()) { // AVX-512
4334 SDValue Cst = DAG.getConstant(0, dl, MVT::i32);
4335 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst,
4336 Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4337 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i32, Ops);
4338 } else if (VT.getVectorElementType() == MVT::i1) {
4340 assert((Subtarget->hasBWI() || VT.getVectorNumElements() <= 16)
4341 && "Unexpected vector type");
4342 assert((Subtarget->hasVLX() || VT.getVectorNumElements() >= 8)
4343 && "Unexpected vector type");
4344 SDValue Cst = DAG.getConstant(0, dl, MVT::i1);
4345 SmallVector<SDValue, 64> Ops(VT.getVectorNumElements(), Cst);
4346 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
4348 llvm_unreachable("Unexpected vector type");
4350 return DAG.getBitcast(VT, Vec);
4353 static SDValue ExtractSubVector(SDValue Vec, unsigned IdxVal,
4354 SelectionDAG &DAG, SDLoc dl,
4355 unsigned vectorWidth) {
4356 assert((vectorWidth == 128 || vectorWidth == 256) &&
4357 "Unsupported vector width");
4358 EVT VT = Vec.getValueType();
4359 EVT ElVT = VT.getVectorElementType();
4360 unsigned Factor = VT.getSizeInBits()/vectorWidth;
4361 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT,
4362 VT.getVectorNumElements()/Factor);
4364 // Extract from UNDEF is UNDEF.
4365 if (Vec.getOpcode() == ISD::UNDEF)
4366 return DAG.getUNDEF(ResultVT);
4368 // Extract the relevant vectorWidth bits. Generate an EXTRACT_SUBVECTOR
4369 unsigned ElemsPerChunk = vectorWidth / ElVT.getSizeInBits();
4370 assert(isPowerOf2_32(ElemsPerChunk) && "Elements per chunk not power of 2");
4372 // This is the index of the first element of the vectorWidth-bit chunk
4373 // we want. Since ElemsPerChunk is a power of 2 just need to clear bits.
4374 IdxVal &= ~(ElemsPerChunk - 1);
4376 // If the input is a buildvector just emit a smaller one.
4377 if (Vec.getOpcode() == ISD::BUILD_VECTOR)
4378 return DAG.getNode(ISD::BUILD_VECTOR, dl, ResultVT,
4379 makeArrayRef(Vec->op_begin() + IdxVal, ElemsPerChunk));
4381 SDValue VecIdx = DAG.getIntPtrConstant(IdxVal, dl);
4382 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec, VecIdx);
4385 /// Generate a DAG to grab 128-bits from a vector > 128 bits. This
4386 /// sets things up to match to an AVX VEXTRACTF128 / VEXTRACTI128
4387 /// or AVX-512 VEXTRACTF32x4 / VEXTRACTI32x4
4388 /// instructions or a simple subregister reference. Idx is an index in the
4389 /// 128 bits we want. It need not be aligned to a 128-bit boundary. That makes
4390 /// lowering EXTRACT_VECTOR_ELT operations easier.
4391 static SDValue Extract128BitVector(SDValue Vec, unsigned IdxVal,
4392 SelectionDAG &DAG, SDLoc dl) {
4393 assert((Vec.getValueType().is256BitVector() ||
4394 Vec.getValueType().is512BitVector()) && "Unexpected vector size!");
4395 return ExtractSubVector(Vec, IdxVal, DAG, dl, 128);
4398 /// Generate a DAG to grab 256-bits from a 512-bit vector.
4399 static SDValue Extract256BitVector(SDValue Vec, unsigned IdxVal,
4400 SelectionDAG &DAG, SDLoc dl) {
4401 assert(Vec.getValueType().is512BitVector() && "Unexpected vector size!");
4402 return ExtractSubVector(Vec, IdxVal, DAG, dl, 256);
4405 static SDValue InsertSubVector(SDValue Result, SDValue Vec,
4406 unsigned IdxVal, SelectionDAG &DAG,
4407 SDLoc dl, unsigned vectorWidth) {
4408 assert((vectorWidth == 128 || vectorWidth == 256) &&
4409 "Unsupported vector width");
4410 // Inserting UNDEF is Result
4411 if (Vec.getOpcode() == ISD::UNDEF)
4413 EVT VT = Vec.getValueType();
4414 EVT ElVT = VT.getVectorElementType();
4415 EVT ResultVT = Result.getValueType();
4417 // Insert the relevant vectorWidth bits.
4418 unsigned ElemsPerChunk = vectorWidth/ElVT.getSizeInBits();
4419 assert(isPowerOf2_32(ElemsPerChunk) && "Elements per chunk not power of 2");
4421 // This is the index of the first element of the vectorWidth-bit chunk
4422 // we want. Since ElemsPerChunk is a power of 2 just need to clear bits.
4423 IdxVal &= ~(ElemsPerChunk - 1);
4425 SDValue VecIdx = DAG.getIntPtrConstant(IdxVal, dl);
4426 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec, VecIdx);
4429 /// Generate a DAG to put 128-bits into a vector > 128 bits. This
4430 /// sets things up to match to an AVX VINSERTF128/VINSERTI128 or
4431 /// AVX-512 VINSERTF32x4/VINSERTI32x4 instructions or a
4432 /// simple superregister reference. Idx is an index in the 128 bits
4433 /// we want. It need not be aligned to a 128-bit boundary. That makes
4434 /// lowering INSERT_VECTOR_ELT operations easier.
4435 static SDValue Insert128BitVector(SDValue Result, SDValue Vec, unsigned IdxVal,
4436 SelectionDAG &DAG, SDLoc dl) {
4437 assert(Vec.getValueType().is128BitVector() && "Unexpected vector size!");
4439 // For insertion into the zero index (low half) of a 256-bit vector, it is
4440 // more efficient to generate a blend with immediate instead of an insert*128.
4441 // We are still creating an INSERT_SUBVECTOR below with an undef node to
4442 // extend the subvector to the size of the result vector. Make sure that
4443 // we are not recursing on that node by checking for undef here.
4444 if (IdxVal == 0 && Result.getValueType().is256BitVector() &&
4445 Result.getOpcode() != ISD::UNDEF) {
4446 EVT ResultVT = Result.getValueType();
4447 SDValue ZeroIndex = DAG.getIntPtrConstant(0, dl);
4448 SDValue Undef = DAG.getUNDEF(ResultVT);
4449 SDValue Vec256 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Undef,
4452 // The blend instruction, and therefore its mask, depend on the data type.
4453 MVT ScalarType = ResultVT.getVectorElementType().getSimpleVT();
4454 if (ScalarType.isFloatingPoint()) {
4455 // Choose either vblendps (float) or vblendpd (double).
4456 unsigned ScalarSize = ScalarType.getSizeInBits();
4457 assert((ScalarSize == 64 || ScalarSize == 32) && "Unknown float type");
4458 unsigned MaskVal = (ScalarSize == 64) ? 0x03 : 0x0f;
4459 SDValue Mask = DAG.getConstant(MaskVal, dl, MVT::i8);
4460 return DAG.getNode(X86ISD::BLENDI, dl, ResultVT, Result, Vec256, Mask);
4463 const X86Subtarget &Subtarget =
4464 static_cast<const X86Subtarget &>(DAG.getSubtarget());
4466 // AVX2 is needed for 256-bit integer blend support.
4467 // Integers must be cast to 32-bit because there is only vpblendd;
4468 // vpblendw can't be used for this because it has a handicapped mask.
4470 // If we don't have AVX2, then cast to float. Using a wrong domain blend
4471 // is still more efficient than using the wrong domain vinsertf128 that
4472 // will be created by InsertSubVector().
4473 MVT CastVT = Subtarget.hasAVX2() ? MVT::v8i32 : MVT::v8f32;
4475 SDValue Mask = DAG.getConstant(0x0f, dl, MVT::i8);
4476 Vec256 = DAG.getBitcast(CastVT, Vec256);
4477 Vec256 = DAG.getNode(X86ISD::BLENDI, dl, CastVT, Result, Vec256, Mask);
4478 return DAG.getBitcast(ResultVT, Vec256);
4481 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 128);
4484 static SDValue Insert256BitVector(SDValue Result, SDValue Vec, unsigned IdxVal,
4485 SelectionDAG &DAG, SDLoc dl) {
4486 assert(Vec.getValueType().is256BitVector() && "Unexpected vector size!");
4487 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 256);
4490 /// Concat two 128-bit vectors into a 256 bit vector using VINSERTF128
4491 /// instructions. This is used because creating CONCAT_VECTOR nodes of
4492 /// BUILD_VECTORS returns a larger BUILD_VECTOR while we're trying to lower
4493 /// large BUILD_VECTORS.
4494 static SDValue Concat128BitVectors(SDValue V1, SDValue V2, EVT VT,
4495 unsigned NumElems, SelectionDAG &DAG,
4497 SDValue V = Insert128BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
4498 return Insert128BitVector(V, V2, NumElems/2, DAG, dl);
4501 static SDValue Concat256BitVectors(SDValue V1, SDValue V2, EVT VT,
4502 unsigned NumElems, SelectionDAG &DAG,
4504 SDValue V = Insert256BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
4505 return Insert256BitVector(V, V2, NumElems/2, DAG, dl);
4508 /// Returns a vector of specified type with all bits set.
4509 /// Always build ones vectors as <4 x i32> or <8 x i32>. For 256-bit types with
4510 /// no AVX2 supprt, use two <4 x i32> inserted in a <8 x i32> appropriately.
4511 /// Then bitcast to their original type, ensuring they get CSE'd.
4512 static SDValue getOnesVector(EVT VT, const X86Subtarget *Subtarget,
4513 SelectionDAG &DAG, SDLoc dl) {
4514 assert(VT.isVector() && "Expected a vector type");
4516 SDValue Cst = DAG.getConstant(~0U, dl, MVT::i32);
4518 if (VT.is512BitVector()) {
4519 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst,
4520 Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4521 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i32, Ops);
4522 } else if (VT.is256BitVector()) {
4523 if (Subtarget->hasInt256()) { // AVX2
4524 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4525 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
4527 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4528 Vec = Concat128BitVectors(Vec, Vec, MVT::v8i32, 8, DAG, dl);
4530 } else if (VT.is128BitVector()) {
4531 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4533 llvm_unreachable("Unexpected vector type");
4535 return DAG.getBitcast(VT, Vec);
4538 /// Returns a vector_shuffle node for an unpackl operation.
4539 static SDValue getUnpackl(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
4541 unsigned NumElems = VT.getVectorNumElements();
4542 SmallVector<int, 8> Mask;
4543 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
4545 Mask.push_back(i + NumElems);
4547 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4550 /// Returns a vector_shuffle node for an unpackh operation.
4551 static SDValue getUnpackh(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
4553 unsigned NumElems = VT.getVectorNumElements();
4554 SmallVector<int, 8> Mask;
4555 for (unsigned i = 0, Half = NumElems/2; i != Half; ++i) {
4556 Mask.push_back(i + Half);
4557 Mask.push_back(i + NumElems + Half);
4559 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4562 /// Return a vector_shuffle of the specified vector of zero or undef vector.
4563 /// This produces a shuffle where the low element of V2 is swizzled into the
4564 /// zero/undef vector, landing at element Idx.
4565 /// This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
4566 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
4568 const X86Subtarget *Subtarget,
4569 SelectionDAG &DAG) {
4570 MVT VT = V2.getSimpleValueType();
4572 ? getZeroVector(VT, Subtarget, DAG, SDLoc(V2)) : DAG.getUNDEF(VT);
4573 unsigned NumElems = VT.getVectorNumElements();
4574 SmallVector<int, 16> MaskVec;
4575 for (unsigned i = 0; i != NumElems; ++i)
4576 // If this is the insertion idx, put the low elt of V2 here.
4577 MaskVec.push_back(i == Idx ? NumElems : i);
4578 return DAG.getVectorShuffle(VT, SDLoc(V2), V1, V2, &MaskVec[0]);
4581 /// Calculates the shuffle mask corresponding to the target-specific opcode.
4582 /// Returns true if the Mask could be calculated. Sets IsUnary to true if only
4583 /// uses one source. Note that this will set IsUnary for shuffles which use a
4584 /// single input multiple times, and in those cases it will
4585 /// adjust the mask to only have indices within that single input.
4586 /// FIXME: Add support for Decode*Mask functions that return SM_SentinelZero.
4587 static bool getTargetShuffleMask(SDNode *N, MVT VT,
4588 SmallVectorImpl<int> &Mask, bool &IsUnary) {
4589 unsigned NumElems = VT.getVectorNumElements();
4593 bool IsFakeUnary = false;
4594 switch(N->getOpcode()) {
4595 case X86ISD::BLENDI:
4596 ImmN = N->getOperand(N->getNumOperands()-1);
4597 DecodeBLENDMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4600 ImmN = N->getOperand(N->getNumOperands()-1);
4601 DecodeSHUFPMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4602 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4604 case X86ISD::UNPCKH:
4605 DecodeUNPCKHMask(VT, Mask);
4606 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4608 case X86ISD::UNPCKL:
4609 DecodeUNPCKLMask(VT, Mask);
4610 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4612 case X86ISD::MOVHLPS:
4613 DecodeMOVHLPSMask(NumElems, Mask);
4614 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4616 case X86ISD::MOVLHPS:
4617 DecodeMOVLHPSMask(NumElems, Mask);
4618 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4620 case X86ISD::PALIGNR:
4621 ImmN = N->getOperand(N->getNumOperands()-1);
4622 DecodePALIGNRMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4624 case X86ISD::PSHUFD:
4625 case X86ISD::VPERMILPI:
4626 ImmN = N->getOperand(N->getNumOperands()-1);
4627 DecodePSHUFMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4630 case X86ISD::PSHUFHW:
4631 ImmN = N->getOperand(N->getNumOperands()-1);
4632 DecodePSHUFHWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4635 case X86ISD::PSHUFLW:
4636 ImmN = N->getOperand(N->getNumOperands()-1);
4637 DecodePSHUFLWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4640 case X86ISD::PSHUFB: {
4642 SDValue MaskNode = N->getOperand(1);
4643 while (MaskNode->getOpcode() == ISD::BITCAST)
4644 MaskNode = MaskNode->getOperand(0);
4646 if (MaskNode->getOpcode() == ISD::BUILD_VECTOR) {
4647 // If we have a build-vector, then things are easy.
4648 MVT VT = MaskNode.getSimpleValueType();
4649 assert(VT.isVector() &&
4650 "Can't produce a non-vector with a build_vector!");
4651 if (!VT.isInteger())
4654 int NumBytesPerElement = VT.getVectorElementType().getSizeInBits() / 8;
4656 SmallVector<uint64_t, 32> RawMask;
4657 for (int i = 0, e = MaskNode->getNumOperands(); i < e; ++i) {
4658 SDValue Op = MaskNode->getOperand(i);
4659 if (Op->getOpcode() == ISD::UNDEF) {
4660 RawMask.push_back((uint64_t)SM_SentinelUndef);
4663 auto *CN = dyn_cast<ConstantSDNode>(Op.getNode());
4666 APInt MaskElement = CN->getAPIntValue();
4668 // We now have to decode the element which could be any integer size and
4669 // extract each byte of it.
4670 for (int j = 0; j < NumBytesPerElement; ++j) {
4671 // Note that this is x86 and so always little endian: the low byte is
4672 // the first byte of the mask.
4673 RawMask.push_back(MaskElement.getLoBits(8).getZExtValue());
4674 MaskElement = MaskElement.lshr(8);
4677 DecodePSHUFBMask(RawMask, Mask);
4681 auto *MaskLoad = dyn_cast<LoadSDNode>(MaskNode);
4685 SDValue Ptr = MaskLoad->getBasePtr();
4686 if (Ptr->getOpcode() == X86ISD::Wrapper ||
4687 Ptr->getOpcode() == X86ISD::WrapperRIP)
4688 Ptr = Ptr->getOperand(0);
4690 auto *MaskCP = dyn_cast<ConstantPoolSDNode>(Ptr);
4691 if (!MaskCP || MaskCP->isMachineConstantPoolEntry())
4694 if (auto *C = dyn_cast<Constant>(MaskCP->getConstVal())) {
4695 DecodePSHUFBMask(C, Mask);
4703 case X86ISD::VPERMI:
4704 ImmN = N->getOperand(N->getNumOperands()-1);
4705 DecodeVPERMMask(cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4710 DecodeScalarMoveMask(VT, /* IsLoad */ false, Mask);
4712 case X86ISD::VPERM2X128:
4713 ImmN = N->getOperand(N->getNumOperands()-1);
4714 DecodeVPERM2X128Mask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4715 if (Mask.empty()) return false;
4716 // Mask only contains negative index if an element is zero.
4717 if (std::any_of(Mask.begin(), Mask.end(),
4718 [](int M){ return M == SM_SentinelZero; }))
4721 case X86ISD::MOVSLDUP:
4722 DecodeMOVSLDUPMask(VT, Mask);
4725 case X86ISD::MOVSHDUP:
4726 DecodeMOVSHDUPMask(VT, Mask);
4729 case X86ISD::MOVDDUP:
4730 DecodeMOVDDUPMask(VT, Mask);
4733 case X86ISD::MOVLHPD:
4734 case X86ISD::MOVLPD:
4735 case X86ISD::MOVLPS:
4736 // Not yet implemented
4738 case X86ISD::VPERMV: {
4740 SDValue MaskNode = N->getOperand(0);
4741 while (MaskNode->getOpcode() == ISD::BITCAST)
4742 MaskNode = MaskNode->getOperand(0);
4744 unsigned MaskLoBits = Log2_64(VT.getVectorNumElements());
4745 SmallVector<uint64_t, 32> RawMask;
4746 if (MaskNode->getOpcode() == ISD::BUILD_VECTOR) {
4747 // If we have a build-vector, then things are easy.
4748 assert(MaskNode.getSimpleValueType().isInteger() &&
4749 MaskNode.getSimpleValueType().getVectorNumElements() ==
4750 VT.getVectorNumElements());
4752 for (unsigned i = 0; i < MaskNode->getNumOperands(); ++i) {
4753 SDValue Op = MaskNode->getOperand(i);
4754 if (Op->getOpcode() == ISD::UNDEF)
4755 RawMask.push_back((uint64_t)SM_SentinelUndef);
4756 else if (isa<ConstantSDNode>(Op)) {
4757 APInt MaskElement = cast<ConstantSDNode>(Op)->getAPIntValue();
4758 RawMask.push_back(MaskElement.getLoBits(MaskLoBits).getZExtValue());
4762 DecodeVPERMVMask(RawMask, Mask);
4765 if (MaskNode->getOpcode() == X86ISD::VBROADCAST) {
4766 unsigned NumEltsInMask = MaskNode->getNumOperands();
4767 MaskNode = MaskNode->getOperand(0);
4768 auto *CN = dyn_cast<ConstantSDNode>(MaskNode);
4770 APInt MaskEltValue = CN->getAPIntValue();
4771 for (unsigned i = 0; i < NumEltsInMask; ++i)
4772 RawMask.push_back(MaskEltValue.getLoBits(MaskLoBits).getZExtValue());
4773 DecodeVPERMVMask(RawMask, Mask);
4776 // It may be a scalar load
4779 auto *MaskLoad = dyn_cast<LoadSDNode>(MaskNode);
4783 SDValue Ptr = MaskLoad->getBasePtr();
4784 if (Ptr->getOpcode() == X86ISD::Wrapper ||
4785 Ptr->getOpcode() == X86ISD::WrapperRIP)
4786 Ptr = Ptr->getOperand(0);
4788 auto *MaskCP = dyn_cast<ConstantPoolSDNode>(Ptr);
4789 if (!MaskCP || MaskCP->isMachineConstantPoolEntry())
4792 auto *C = dyn_cast<Constant>(MaskCP->getConstVal());
4794 DecodeVPERMVMask(C, VT, Mask);
4801 case X86ISD::VPERMV3: {
4803 SDValue MaskNode = N->getOperand(1);
4804 while (MaskNode->getOpcode() == ISD::BITCAST)
4805 MaskNode = MaskNode->getOperand(1);
4807 if (MaskNode->getOpcode() == ISD::BUILD_VECTOR) {
4808 // If we have a build-vector, then things are easy.
4809 assert(MaskNode.getSimpleValueType().isInteger() &&
4810 MaskNode.getSimpleValueType().getVectorNumElements() ==
4811 VT.getVectorNumElements());
4813 SmallVector<uint64_t, 32> RawMask;
4814 unsigned MaskLoBits = Log2_64(VT.getVectorNumElements()*2);
4816 for (unsigned i = 0; i < MaskNode->getNumOperands(); ++i) {
4817 SDValue Op = MaskNode->getOperand(i);
4818 if (Op->getOpcode() == ISD::UNDEF)
4819 RawMask.push_back((uint64_t)SM_SentinelUndef);
4821 auto *CN = dyn_cast<ConstantSDNode>(Op.getNode());
4824 APInt MaskElement = CN->getAPIntValue();
4825 RawMask.push_back(MaskElement.getLoBits(MaskLoBits).getZExtValue());
4828 DecodeVPERMV3Mask(RawMask, Mask);
4832 auto *MaskLoad = dyn_cast<LoadSDNode>(MaskNode);
4836 SDValue Ptr = MaskLoad->getBasePtr();
4837 if (Ptr->getOpcode() == X86ISD::Wrapper ||
4838 Ptr->getOpcode() == X86ISD::WrapperRIP)
4839 Ptr = Ptr->getOperand(0);
4841 auto *MaskCP = dyn_cast<ConstantPoolSDNode>(Ptr);
4842 if (!MaskCP || MaskCP->isMachineConstantPoolEntry())
4845 auto *C = dyn_cast<Constant>(MaskCP->getConstVal());
4847 DecodeVPERMV3Mask(C, VT, Mask);
4854 default: llvm_unreachable("unknown target shuffle node");
4857 // If we have a fake unary shuffle, the shuffle mask is spread across two
4858 // inputs that are actually the same node. Re-map the mask to always point
4859 // into the first input.
4862 if (M >= (int)Mask.size())
4868 /// Returns the scalar element that will make up the ith
4869 /// element of the result of the vector shuffle.
4870 static SDValue getShuffleScalarElt(SDNode *N, unsigned Index, SelectionDAG &DAG,
4873 return SDValue(); // Limit search depth.
4875 SDValue V = SDValue(N, 0);
4876 EVT VT = V.getValueType();
4877 unsigned Opcode = V.getOpcode();
4879 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars.
4880 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) {
4881 int Elt = SV->getMaskElt(Index);
4884 return DAG.getUNDEF(VT.getVectorElementType());
4886 unsigned NumElems = VT.getVectorNumElements();
4887 SDValue NewV = (Elt < (int)NumElems) ? SV->getOperand(0)
4888 : SV->getOperand(1);
4889 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG, Depth+1);
4892 // Recurse into target specific vector shuffles to find scalars.
4893 if (isTargetShuffle(Opcode)) {
4894 MVT ShufVT = V.getSimpleValueType();
4895 unsigned NumElems = ShufVT.getVectorNumElements();
4896 SmallVector<int, 16> ShuffleMask;
4899 if (!getTargetShuffleMask(N, ShufVT, ShuffleMask, IsUnary))
4902 int Elt = ShuffleMask[Index];
4904 return DAG.getUNDEF(ShufVT.getVectorElementType());
4906 SDValue NewV = (Elt < (int)NumElems) ? N->getOperand(0)
4908 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG,
4912 // Actual nodes that may contain scalar elements
4913 if (Opcode == ISD::BITCAST) {
4914 V = V.getOperand(0);
4915 EVT SrcVT = V.getValueType();
4916 unsigned NumElems = VT.getVectorNumElements();
4918 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems)
4922 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR)
4923 return (Index == 0) ? V.getOperand(0)
4924 : DAG.getUNDEF(VT.getVectorElementType());
4926 if (V.getOpcode() == ISD::BUILD_VECTOR)
4927 return V.getOperand(Index);
4932 /// Custom lower build_vector of v16i8.
4933 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
4934 unsigned NumNonZero, unsigned NumZero,
4936 const X86Subtarget* Subtarget,
4937 const TargetLowering &TLI) {
4945 // SSE4.1 - use PINSRB to insert each byte directly.
4946 if (Subtarget->hasSSE41()) {
4947 for (unsigned i = 0; i < 16; ++i) {
4948 bool isNonZero = (NonZeros & (1 << i)) != 0;
4952 V = getZeroVector(MVT::v16i8, Subtarget, DAG, dl);
4954 V = DAG.getUNDEF(MVT::v16i8);
4957 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
4958 MVT::v16i8, V, Op.getOperand(i),
4959 DAG.getIntPtrConstant(i, dl));
4966 // Pre-SSE4.1 - merge byte pairs and insert with PINSRW.
4967 for (unsigned i = 0; i < 16; ++i) {
4968 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
4969 if (ThisIsNonZero && First) {
4971 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
4973 V = DAG.getUNDEF(MVT::v8i16);
4978 SDValue ThisElt, LastElt;
4979 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
4980 if (LastIsNonZero) {
4981 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
4982 MVT::i16, Op.getOperand(i-1));
4984 if (ThisIsNonZero) {
4985 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
4986 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
4987 ThisElt, DAG.getConstant(8, dl, MVT::i8));
4989 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
4993 if (ThisElt.getNode())
4994 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
4995 DAG.getIntPtrConstant(i/2, dl));
4999 return DAG.getBitcast(MVT::v16i8, V);
5002 /// Custom lower build_vector of v8i16.
5003 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
5004 unsigned NumNonZero, unsigned NumZero,
5006 const X86Subtarget* Subtarget,
5007 const TargetLowering &TLI) {
5014 for (unsigned i = 0; i < 8; ++i) {
5015 bool isNonZero = (NonZeros & (1 << i)) != 0;
5019 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
5021 V = DAG.getUNDEF(MVT::v8i16);
5024 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
5025 MVT::v8i16, V, Op.getOperand(i),
5026 DAG.getIntPtrConstant(i, dl));
5033 /// Custom lower build_vector of v4i32 or v4f32.
5034 static SDValue LowerBuildVectorv4x32(SDValue Op, SelectionDAG &DAG,
5035 const X86Subtarget *Subtarget,
5036 const TargetLowering &TLI) {
5037 // Find all zeroable elements.
5038 std::bitset<4> Zeroable;
5039 for (int i=0; i < 4; ++i) {
5040 SDValue Elt = Op->getOperand(i);
5041 Zeroable[i] = (Elt.getOpcode() == ISD::UNDEF || X86::isZeroNode(Elt));
5043 assert(Zeroable.size() - Zeroable.count() > 1 &&
5044 "We expect at least two non-zero elements!");
5046 // We only know how to deal with build_vector nodes where elements are either
5047 // zeroable or extract_vector_elt with constant index.
5048 SDValue FirstNonZero;
5049 unsigned FirstNonZeroIdx;
5050 for (unsigned i=0; i < 4; ++i) {
5053 SDValue Elt = Op->getOperand(i);
5054 if (Elt.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
5055 !isa<ConstantSDNode>(Elt.getOperand(1)))
5057 // Make sure that this node is extracting from a 128-bit vector.
5058 MVT VT = Elt.getOperand(0).getSimpleValueType();
5059 if (!VT.is128BitVector())
5061 if (!FirstNonZero.getNode()) {
5063 FirstNonZeroIdx = i;
5067 assert(FirstNonZero.getNode() && "Unexpected build vector of all zeros!");
5068 SDValue V1 = FirstNonZero.getOperand(0);
5069 MVT VT = V1.getSimpleValueType();
5071 // See if this build_vector can be lowered as a blend with zero.
5073 unsigned EltMaskIdx, EltIdx;
5075 for (EltIdx = 0; EltIdx < 4; ++EltIdx) {
5076 if (Zeroable[EltIdx]) {
5077 // The zero vector will be on the right hand side.
5078 Mask[EltIdx] = EltIdx+4;
5082 Elt = Op->getOperand(EltIdx);
5083 // By construction, Elt is a EXTRACT_VECTOR_ELT with constant index.
5084 EltMaskIdx = cast<ConstantSDNode>(Elt.getOperand(1))->getZExtValue();
5085 if (Elt.getOperand(0) != V1 || EltMaskIdx != EltIdx)
5087 Mask[EltIdx] = EltIdx;
5091 // Let the shuffle legalizer deal with blend operations.
5092 SDValue VZero = getZeroVector(VT, Subtarget, DAG, SDLoc(Op));
5093 if (V1.getSimpleValueType() != VT)
5094 V1 = DAG.getNode(ISD::BITCAST, SDLoc(V1), VT, V1);
5095 return DAG.getVectorShuffle(VT, SDLoc(V1), V1, VZero, &Mask[0]);
5098 // See if we can lower this build_vector to a INSERTPS.
5099 if (!Subtarget->hasSSE41())
5102 SDValue V2 = Elt.getOperand(0);
5103 if (Elt == FirstNonZero && EltIdx == FirstNonZeroIdx)
5106 bool CanFold = true;
5107 for (unsigned i = EltIdx + 1; i < 4 && CanFold; ++i) {
5111 SDValue Current = Op->getOperand(i);
5112 SDValue SrcVector = Current->getOperand(0);
5115 CanFold = SrcVector == V1 &&
5116 cast<ConstantSDNode>(Current.getOperand(1))->getZExtValue() == i;
5122 assert(V1.getNode() && "Expected at least two non-zero elements!");
5123 if (V1.getSimpleValueType() != MVT::v4f32)
5124 V1 = DAG.getNode(ISD::BITCAST, SDLoc(V1), MVT::v4f32, V1);
5125 if (V2.getSimpleValueType() != MVT::v4f32)
5126 V2 = DAG.getNode(ISD::BITCAST, SDLoc(V2), MVT::v4f32, V2);
5128 // Ok, we can emit an INSERTPS instruction.
5129 unsigned ZMask = Zeroable.to_ulong();
5131 unsigned InsertPSMask = EltMaskIdx << 6 | EltIdx << 4 | ZMask;
5132 assert((InsertPSMask & ~0xFFu) == 0 && "Invalid mask!");
5134 SDValue Result = DAG.getNode(X86ISD::INSERTPS, DL, MVT::v4f32, V1, V2,
5135 DAG.getIntPtrConstant(InsertPSMask, DL));
5136 return DAG.getBitcast(VT, Result);
5139 /// Return a vector logical shift node.
5140 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
5141 unsigned NumBits, SelectionDAG &DAG,
5142 const TargetLowering &TLI, SDLoc dl) {
5143 assert(VT.is128BitVector() && "Unknown type for VShift");
5144 MVT ShVT = MVT::v2i64;
5145 unsigned Opc = isLeft ? X86ISD::VSHLDQ : X86ISD::VSRLDQ;
5146 SrcOp = DAG.getBitcast(ShVT, SrcOp);
5147 MVT ScalarShiftTy = TLI.getScalarShiftAmountTy(DAG.getDataLayout(), VT);
5148 assert(NumBits % 8 == 0 && "Only support byte sized shifts");
5149 SDValue ShiftVal = DAG.getConstant(NumBits/8, dl, ScalarShiftTy);
5150 return DAG.getBitcast(VT, DAG.getNode(Opc, dl, ShVT, SrcOp, ShiftVal));
5154 LowerAsSplatVectorLoad(SDValue SrcOp, MVT VT, SDLoc dl, SelectionDAG &DAG) {
5156 // Check if the scalar load can be widened into a vector load. And if
5157 // the address is "base + cst" see if the cst can be "absorbed" into
5158 // the shuffle mask.
5159 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) {
5160 SDValue Ptr = LD->getBasePtr();
5161 if (!ISD::isNormalLoad(LD) || LD->isVolatile())
5163 EVT PVT = LD->getValueType(0);
5164 if (PVT != MVT::i32 && PVT != MVT::f32)
5169 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) {
5170 FI = FINode->getIndex();
5172 } else if (DAG.isBaseWithConstantOffset(Ptr) &&
5173 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
5174 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
5175 Offset = Ptr.getConstantOperandVal(1);
5176 Ptr = Ptr.getOperand(0);
5181 // FIXME: 256-bit vector instructions don't require a strict alignment,
5182 // improve this code to support it better.
5183 unsigned RequiredAlign = VT.getSizeInBits()/8;
5184 SDValue Chain = LD->getChain();
5185 // Make sure the stack object alignment is at least 16 or 32.
5186 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
5187 if (DAG.InferPtrAlignment(Ptr) < RequiredAlign) {
5188 if (MFI->isFixedObjectIndex(FI)) {
5189 // Can't change the alignment. FIXME: It's possible to compute
5190 // the exact stack offset and reference FI + adjust offset instead.
5191 // If someone *really* cares about this. That's the way to implement it.
5194 MFI->setObjectAlignment(FI, RequiredAlign);
5198 // (Offset % 16 or 32) must be multiple of 4. Then address is then
5199 // Ptr + (Offset & ~15).
5202 if ((Offset % RequiredAlign) & 3)
5204 int64_t StartOffset = Offset & ~int64_t(RequiredAlign - 1);
5207 Ptr = DAG.getNode(ISD::ADD, DL, Ptr.getValueType(), Ptr,
5208 DAG.getConstant(StartOffset, DL, Ptr.getValueType()));
5211 int EltNo = (Offset - StartOffset) >> 2;
5212 unsigned NumElems = VT.getVectorNumElements();
5214 EVT NVT = EVT::getVectorVT(*DAG.getContext(), PVT, NumElems);
5215 SDValue V1 = DAG.getLoad(NVT, dl, Chain, Ptr,
5216 LD->getPointerInfo().getWithOffset(StartOffset),
5217 false, false, false, 0);
5219 SmallVector<int, 8> Mask(NumElems, EltNo);
5221 return DAG.getVectorShuffle(NVT, dl, V1, DAG.getUNDEF(NVT), &Mask[0]);
5227 /// Given the initializing elements 'Elts' of a vector of type 'VT', see if the
5228 /// elements can be replaced by a single large load which has the same value as
5229 /// a build_vector or insert_subvector whose loaded operands are 'Elts'.
5231 /// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a
5233 /// FIXME: we'd also like to handle the case where the last elements are zero
5234 /// rather than undef via VZEXT_LOAD, but we do not detect that case today.
5235 /// There's even a handy isZeroNode for that purpose.
5236 static SDValue EltsFromConsecutiveLoads(EVT VT, ArrayRef<SDValue> Elts,
5237 SDLoc &DL, SelectionDAG &DAG,
5238 bool isAfterLegalize) {
5239 unsigned NumElems = Elts.size();
5241 LoadSDNode *LDBase = nullptr;
5242 unsigned LastLoadedElt = -1U;
5244 // For each element in the initializer, see if we've found a load or an undef.
5245 // If we don't find an initial load element, or later load elements are
5246 // non-consecutive, bail out.
5247 for (unsigned i = 0; i < NumElems; ++i) {
5248 SDValue Elt = Elts[i];
5249 // Look through a bitcast.
5250 if (Elt.getNode() && Elt.getOpcode() == ISD::BITCAST)
5251 Elt = Elt.getOperand(0);
5252 if (!Elt.getNode() ||
5253 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
5256 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
5258 LDBase = cast<LoadSDNode>(Elt.getNode());
5262 if (Elt.getOpcode() == ISD::UNDEF)
5265 LoadSDNode *LD = cast<LoadSDNode>(Elt);
5266 EVT LdVT = Elt.getValueType();
5267 // Each loaded element must be the correct fractional portion of the
5268 // requested vector load.
5269 if (LdVT.getSizeInBits() != VT.getSizeInBits() / NumElems)
5271 if (!DAG.isConsecutiveLoad(LD, LDBase, LdVT.getSizeInBits() / 8, i))
5276 // If we have found an entire vector of loads and undefs, then return a large
5277 // load of the entire vector width starting at the base pointer. If we found
5278 // consecutive loads for the low half, generate a vzext_load node.
5279 if (LastLoadedElt == NumElems - 1) {
5280 assert(LDBase && "Did not find base load for merging consecutive loads");
5281 EVT EltVT = LDBase->getValueType(0);
5282 // Ensure that the input vector size for the merged loads matches the
5283 // cumulative size of the input elements.
5284 if (VT.getSizeInBits() != EltVT.getSizeInBits() * NumElems)
5287 if (isAfterLegalize &&
5288 !DAG.getTargetLoweringInfo().isOperationLegal(ISD::LOAD, VT))
5291 SDValue NewLd = SDValue();
5293 NewLd = DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
5294 LDBase->getPointerInfo(), LDBase->isVolatile(),
5295 LDBase->isNonTemporal(), LDBase->isInvariant(),
5296 LDBase->getAlignment());
5298 if (LDBase->hasAnyUseOfValue(1)) {
5299 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
5301 SDValue(NewLd.getNode(), 1));
5302 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
5303 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
5304 SDValue(NewLd.getNode(), 1));
5310 //TODO: The code below fires only for for loading the low v2i32 / v2f32
5311 //of a v4i32 / v4f32. It's probably worth generalizing.
5312 EVT EltVT = VT.getVectorElementType();
5313 if (NumElems == 4 && LastLoadedElt == 1 && (EltVT.getSizeInBits() == 32) &&
5314 DAG.getTargetLoweringInfo().isTypeLegal(MVT::v2i64)) {
5315 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
5316 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() };
5318 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys, Ops, MVT::i64,
5319 LDBase->getPointerInfo(),
5320 LDBase->getAlignment(),
5321 false/*isVolatile*/, true/*ReadMem*/,
5324 // Make sure the newly-created LOAD is in the same position as LDBase in
5325 // terms of dependency. We create a TokenFactor for LDBase and ResNode, and
5326 // update uses of LDBase's output chain to use the TokenFactor.
5327 if (LDBase->hasAnyUseOfValue(1)) {
5328 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
5329 SDValue(LDBase, 1), SDValue(ResNode.getNode(), 1));
5330 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
5331 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
5332 SDValue(ResNode.getNode(), 1));
5335 return DAG.getBitcast(VT, ResNode);
5340 /// LowerVectorBroadcast - Attempt to use the vbroadcast instruction
5341 /// to generate a splat value for the following cases:
5342 /// 1. A splat BUILD_VECTOR which uses a single scalar load, or a constant.
5343 /// 2. A splat shuffle which uses a scalar_to_vector node which comes from
5344 /// a scalar load, or a constant.
5345 /// The VBROADCAST node is returned when a pattern is found,
5346 /// or SDValue() otherwise.
5347 static SDValue LowerVectorBroadcast(SDValue Op, const X86Subtarget* Subtarget,
5348 SelectionDAG &DAG) {
5349 // VBROADCAST requires AVX.
5350 // TODO: Splats could be generated for non-AVX CPUs using SSE
5351 // instructions, but there's less potential gain for only 128-bit vectors.
5352 if (!Subtarget->hasAVX())
5355 MVT VT = Op.getSimpleValueType();
5358 assert((VT.is128BitVector() || VT.is256BitVector() || VT.is512BitVector()) &&
5359 "Unsupported vector type for broadcast.");
5364 switch (Op.getOpcode()) {
5366 // Unknown pattern found.
5369 case ISD::BUILD_VECTOR: {
5370 auto *BVOp = cast<BuildVectorSDNode>(Op.getNode());
5371 BitVector UndefElements;
5372 SDValue Splat = BVOp->getSplatValue(&UndefElements);
5374 // We need a splat of a single value to use broadcast, and it doesn't
5375 // make any sense if the value is only in one element of the vector.
5376 if (!Splat || (VT.getVectorNumElements() - UndefElements.count()) <= 1)
5380 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
5381 Ld.getOpcode() == ISD::ConstantFP);
5383 // Make sure that all of the users of a non-constant load are from the
5384 // BUILD_VECTOR node.
5385 if (!ConstSplatVal && !BVOp->isOnlyUserOf(Ld.getNode()))
5390 case ISD::VECTOR_SHUFFLE: {
5391 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
5393 // Shuffles must have a splat mask where the first element is
5395 if ((!SVOp->isSplat()) || SVOp->getMaskElt(0) != 0)
5398 SDValue Sc = Op.getOperand(0);
5399 if (Sc.getOpcode() != ISD::SCALAR_TO_VECTOR &&
5400 Sc.getOpcode() != ISD::BUILD_VECTOR) {
5402 if (!Subtarget->hasInt256())
5405 // Use the register form of the broadcast instruction available on AVX2.
5406 if (VT.getSizeInBits() >= 256)
5407 Sc = Extract128BitVector(Sc, 0, DAG, dl);
5408 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Sc);
5411 Ld = Sc.getOperand(0);
5412 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
5413 Ld.getOpcode() == ISD::ConstantFP);
5415 // The scalar_to_vector node and the suspected
5416 // load node must have exactly one user.
5417 // Constants may have multiple users.
5419 // AVX-512 has register version of the broadcast
5420 bool hasRegVer = Subtarget->hasAVX512() && VT.is512BitVector() &&
5421 Ld.getValueType().getSizeInBits() >= 32;
5422 if (!ConstSplatVal && ((!Sc.hasOneUse() || !Ld.hasOneUse()) &&
5429 unsigned ScalarSize = Ld.getValueType().getSizeInBits();
5430 bool IsGE256 = (VT.getSizeInBits() >= 256);
5432 // When optimizing for size, generate up to 5 extra bytes for a broadcast
5433 // instruction to save 8 or more bytes of constant pool data.
5434 // TODO: If multiple splats are generated to load the same constant,
5435 // it may be detrimental to overall size. There needs to be a way to detect
5436 // that condition to know if this is truly a size win.
5437 bool OptForSize = DAG.getMachineFunction().getFunction()->optForSize();
5439 // Handle broadcasting a single constant scalar from the constant pool
5441 // On Sandybridge (no AVX2), it is still better to load a constant vector
5442 // from the constant pool and not to broadcast it from a scalar.
5443 // But override that restriction when optimizing for size.
5444 // TODO: Check if splatting is recommended for other AVX-capable CPUs.
5445 if (ConstSplatVal && (Subtarget->hasAVX2() || OptForSize)) {
5446 EVT CVT = Ld.getValueType();
5447 assert(!CVT.isVector() && "Must not broadcast a vector type");
5449 // Splat f32, i32, v4f64, v4i64 in all cases with AVX2.
5450 // For size optimization, also splat v2f64 and v2i64, and for size opt
5451 // with AVX2, also splat i8 and i16.
5452 // With pattern matching, the VBROADCAST node may become a VMOVDDUP.
5453 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64) ||
5454 (OptForSize && (ScalarSize == 64 || Subtarget->hasAVX2()))) {
5455 const Constant *C = nullptr;
5456 if (ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Ld))
5457 C = CI->getConstantIntValue();
5458 else if (ConstantFPSDNode *CF = dyn_cast<ConstantFPSDNode>(Ld))
5459 C = CF->getConstantFPValue();
5461 assert(C && "Invalid constant type");
5463 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5465 DAG.getConstantPool(C, TLI.getPointerTy(DAG.getDataLayout()));
5466 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
5468 CVT, dl, DAG.getEntryNode(), CP,
5469 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()), false,
5470 false, false, Alignment);
5472 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5476 bool IsLoad = ISD::isNormalLoad(Ld.getNode());
5478 // Handle AVX2 in-register broadcasts.
5479 if (!IsLoad && Subtarget->hasInt256() &&
5480 (ScalarSize == 32 || (IsGE256 && ScalarSize == 64)))
5481 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5483 // The scalar source must be a normal load.
5487 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64) ||
5488 (Subtarget->hasVLX() && ScalarSize == 64))
5489 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5491 // The integer check is needed for the 64-bit into 128-bit so it doesn't match
5492 // double since there is no vbroadcastsd xmm
5493 if (Subtarget->hasInt256() && Ld.getValueType().isInteger()) {
5494 if (ScalarSize == 8 || ScalarSize == 16 || ScalarSize == 64)
5495 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5498 // Unsupported broadcast.
5502 /// \brief For an EXTRACT_VECTOR_ELT with a constant index return the real
5503 /// underlying vector and index.
5505 /// Modifies \p ExtractedFromVec to the real vector and returns the real
5507 static int getUnderlyingExtractedFromVec(SDValue &ExtractedFromVec,
5509 int Idx = cast<ConstantSDNode>(ExtIdx)->getZExtValue();
5510 if (!isa<ShuffleVectorSDNode>(ExtractedFromVec))
5513 // For 256-bit vectors, LowerEXTRACT_VECTOR_ELT_SSE4 may have already
5515 // (extract_vector_elt (v8f32 %vreg1), Constant<6>)
5517 // (extract_vector_elt (vector_shuffle<2,u,u,u>
5518 // (extract_subvector (v8f32 %vreg0), Constant<4>),
5521 // In this case the vector is the extract_subvector expression and the index
5522 // is 2, as specified by the shuffle.
5523 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(ExtractedFromVec);
5524 SDValue ShuffleVec = SVOp->getOperand(0);
5525 MVT ShuffleVecVT = ShuffleVec.getSimpleValueType();
5526 assert(ShuffleVecVT.getVectorElementType() ==
5527 ExtractedFromVec.getSimpleValueType().getVectorElementType());
5529 int ShuffleIdx = SVOp->getMaskElt(Idx);
5530 if (isUndefOrInRange(ShuffleIdx, 0, ShuffleVecVT.getVectorNumElements())) {
5531 ExtractedFromVec = ShuffleVec;
5537 static SDValue buildFromShuffleMostly(SDValue Op, SelectionDAG &DAG) {
5538 MVT VT = Op.getSimpleValueType();
5540 // Skip if insert_vec_elt is not supported.
5541 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5542 if (!TLI.isOperationLegalOrCustom(ISD::INSERT_VECTOR_ELT, VT))
5546 unsigned NumElems = Op.getNumOperands();
5550 SmallVector<unsigned, 4> InsertIndices;
5551 SmallVector<int, 8> Mask(NumElems, -1);
5553 for (unsigned i = 0; i != NumElems; ++i) {
5554 unsigned Opc = Op.getOperand(i).getOpcode();
5556 if (Opc == ISD::UNDEF)
5559 if (Opc != ISD::EXTRACT_VECTOR_ELT) {
5560 // Quit if more than 1 elements need inserting.
5561 if (InsertIndices.size() > 1)
5564 InsertIndices.push_back(i);
5568 SDValue ExtractedFromVec = Op.getOperand(i).getOperand(0);
5569 SDValue ExtIdx = Op.getOperand(i).getOperand(1);
5570 // Quit if non-constant index.
5571 if (!isa<ConstantSDNode>(ExtIdx))
5573 int Idx = getUnderlyingExtractedFromVec(ExtractedFromVec, ExtIdx);
5575 // Quit if extracted from vector of different type.
5576 if (ExtractedFromVec.getValueType() != VT)
5579 if (!VecIn1.getNode())
5580 VecIn1 = ExtractedFromVec;
5581 else if (VecIn1 != ExtractedFromVec) {
5582 if (!VecIn2.getNode())
5583 VecIn2 = ExtractedFromVec;
5584 else if (VecIn2 != ExtractedFromVec)
5585 // Quit if more than 2 vectors to shuffle
5589 if (ExtractedFromVec == VecIn1)
5591 else if (ExtractedFromVec == VecIn2)
5592 Mask[i] = Idx + NumElems;
5595 if (!VecIn1.getNode())
5598 VecIn2 = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT);
5599 SDValue NV = DAG.getVectorShuffle(VT, DL, VecIn1, VecIn2, &Mask[0]);
5600 for (unsigned i = 0, e = InsertIndices.size(); i != e; ++i) {
5601 unsigned Idx = InsertIndices[i];
5602 NV = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VT, NV, Op.getOperand(Idx),
5603 DAG.getIntPtrConstant(Idx, DL));
5609 static SDValue ConvertI1VectorToInteger(SDValue Op, SelectionDAG &DAG) {
5610 assert(ISD::isBuildVectorOfConstantSDNodes(Op.getNode()) &&
5611 Op.getScalarValueSizeInBits() == 1 &&
5612 "Can not convert non-constant vector");
5613 uint64_t Immediate = 0;
5614 for (unsigned idx = 0, e = Op.getNumOperands(); idx < e; ++idx) {
5615 SDValue In = Op.getOperand(idx);
5616 if (In.getOpcode() != ISD::UNDEF)
5617 Immediate |= cast<ConstantSDNode>(In)->getZExtValue() << idx;
5621 MVT::getIntegerVT(std::max((int)Op.getValueType().getSizeInBits(), 8));
5622 return DAG.getConstant(Immediate, dl, VT);
5624 // Lower BUILD_VECTOR operation for v8i1 and v16i1 types.
5626 X86TargetLowering::LowerBUILD_VECTORvXi1(SDValue Op, SelectionDAG &DAG) const {
5628 MVT VT = Op.getSimpleValueType();
5629 assert((VT.getVectorElementType() == MVT::i1) &&
5630 "Unexpected type in LowerBUILD_VECTORvXi1!");
5633 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
5634 SDValue Cst = DAG.getTargetConstant(0, dl, MVT::i1);
5635 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
5636 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
5639 if (ISD::isBuildVectorAllOnes(Op.getNode())) {
5640 SDValue Cst = DAG.getTargetConstant(1, dl, MVT::i1);
5641 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
5642 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
5645 if (ISD::isBuildVectorOfConstantSDNodes(Op.getNode())) {
5646 SDValue Imm = ConvertI1VectorToInteger(Op, DAG);
5647 if (Imm.getValueSizeInBits() == VT.getSizeInBits())
5648 return DAG.getBitcast(VT, Imm);
5649 SDValue ExtVec = DAG.getBitcast(MVT::v8i1, Imm);
5650 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, ExtVec,
5651 DAG.getIntPtrConstant(0, dl));
5654 // Vector has one or more non-const elements
5655 uint64_t Immediate = 0;
5656 SmallVector<unsigned, 16> NonConstIdx;
5657 bool IsSplat = true;
5658 bool HasConstElts = false;
5660 for (unsigned idx = 0, e = Op.getNumOperands(); idx < e; ++idx) {
5661 SDValue In = Op.getOperand(idx);
5662 if (In.getOpcode() == ISD::UNDEF)
5664 if (!isa<ConstantSDNode>(In))
5665 NonConstIdx.push_back(idx);
5667 Immediate |= cast<ConstantSDNode>(In)->getZExtValue() << idx;
5668 HasConstElts = true;
5672 else if (In != Op.getOperand(SplatIdx))
5676 // for splat use " (select i1 splat_elt, all-ones, all-zeroes)"
5678 return DAG.getNode(ISD::SELECT, dl, VT, Op.getOperand(SplatIdx),
5679 DAG.getConstant(1, dl, VT),
5680 DAG.getConstant(0, dl, VT));
5682 // insert elements one by one
5686 MVT ImmVT = MVT::getIntegerVT(std::max((int)VT.getSizeInBits(), 8));
5687 Imm = DAG.getConstant(Immediate, dl, ImmVT);
5689 else if (HasConstElts)
5690 Imm = DAG.getConstant(0, dl, VT);
5692 Imm = DAG.getUNDEF(VT);
5693 if (Imm.getValueSizeInBits() == VT.getSizeInBits())
5694 DstVec = DAG.getBitcast(VT, Imm);
5696 SDValue ExtVec = DAG.getBitcast(MVT::v8i1, Imm);
5697 DstVec = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, ExtVec,
5698 DAG.getIntPtrConstant(0, dl));
5701 for (unsigned i = 0; i < NonConstIdx.size(); ++i) {
5702 unsigned InsertIdx = NonConstIdx[i];
5703 DstVec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, DstVec,
5704 Op.getOperand(InsertIdx),
5705 DAG.getIntPtrConstant(InsertIdx, dl));
5710 /// \brief Return true if \p N implements a horizontal binop and return the
5711 /// operands for the horizontal binop into V0 and V1.
5713 /// This is a helper function of LowerToHorizontalOp().
5714 /// This function checks that the build_vector \p N in input implements a
5715 /// horizontal operation. Parameter \p Opcode defines the kind of horizontal
5716 /// operation to match.
5717 /// For example, if \p Opcode is equal to ISD::ADD, then this function
5718 /// checks if \p N implements a horizontal arithmetic add; if instead \p Opcode
5719 /// is equal to ISD::SUB, then this function checks if this is a horizontal
5722 /// This function only analyzes elements of \p N whose indices are
5723 /// in range [BaseIdx, LastIdx).
5724 static bool isHorizontalBinOp(const BuildVectorSDNode *N, unsigned Opcode,
5726 unsigned BaseIdx, unsigned LastIdx,
5727 SDValue &V0, SDValue &V1) {
5728 EVT VT = N->getValueType(0);
5730 assert(BaseIdx * 2 <= LastIdx && "Invalid Indices in input!");
5731 assert(VT.isVector() && VT.getVectorNumElements() >= LastIdx &&
5732 "Invalid Vector in input!");
5734 bool IsCommutable = (Opcode == ISD::ADD || Opcode == ISD::FADD);
5735 bool CanFold = true;
5736 unsigned ExpectedVExtractIdx = BaseIdx;
5737 unsigned NumElts = LastIdx - BaseIdx;
5738 V0 = DAG.getUNDEF(VT);
5739 V1 = DAG.getUNDEF(VT);
5741 // Check if N implements a horizontal binop.
5742 for (unsigned i = 0, e = NumElts; i != e && CanFold; ++i) {
5743 SDValue Op = N->getOperand(i + BaseIdx);
5746 if (Op->getOpcode() == ISD::UNDEF) {
5747 // Update the expected vector extract index.
5748 if (i * 2 == NumElts)
5749 ExpectedVExtractIdx = BaseIdx;
5750 ExpectedVExtractIdx += 2;
5754 CanFold = Op->getOpcode() == Opcode && Op->hasOneUse();
5759 SDValue Op0 = Op.getOperand(0);
5760 SDValue Op1 = Op.getOperand(1);
5762 // Try to match the following pattern:
5763 // (BINOP (extract_vector_elt A, I), (extract_vector_elt A, I+1))
5764 CanFold = (Op0.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
5765 Op1.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
5766 Op0.getOperand(0) == Op1.getOperand(0) &&
5767 isa<ConstantSDNode>(Op0.getOperand(1)) &&
5768 isa<ConstantSDNode>(Op1.getOperand(1)));
5772 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
5773 unsigned I1 = cast<ConstantSDNode>(Op1.getOperand(1))->getZExtValue();
5775 if (i * 2 < NumElts) {
5776 if (V0.getOpcode() == ISD::UNDEF) {
5777 V0 = Op0.getOperand(0);
5778 if (V0.getValueType() != VT)
5782 if (V1.getOpcode() == ISD::UNDEF) {
5783 V1 = Op0.getOperand(0);
5784 if (V1.getValueType() != VT)
5787 if (i * 2 == NumElts)
5788 ExpectedVExtractIdx = BaseIdx;
5791 SDValue Expected = (i * 2 < NumElts) ? V0 : V1;
5792 if (I0 == ExpectedVExtractIdx)
5793 CanFold = I1 == I0 + 1 && Op0.getOperand(0) == Expected;
5794 else if (IsCommutable && I1 == ExpectedVExtractIdx) {
5795 // Try to match the following dag sequence:
5796 // (BINOP (extract_vector_elt A, I+1), (extract_vector_elt A, I))
5797 CanFold = I0 == I1 + 1 && Op1.getOperand(0) == Expected;
5801 ExpectedVExtractIdx += 2;
5807 /// \brief Emit a sequence of two 128-bit horizontal add/sub followed by
5808 /// a concat_vector.
5810 /// This is a helper function of LowerToHorizontalOp().
5811 /// This function expects two 256-bit vectors called V0 and V1.
5812 /// At first, each vector is split into two separate 128-bit vectors.
5813 /// Then, the resulting 128-bit vectors are used to implement two
5814 /// horizontal binary operations.
5816 /// The kind of horizontal binary operation is defined by \p X86Opcode.
5818 /// \p Mode specifies how the 128-bit parts of V0 and V1 are passed in input to
5819 /// the two new horizontal binop.
5820 /// When Mode is set, the first horizontal binop dag node would take as input
5821 /// the lower 128-bit of V0 and the upper 128-bit of V0. The second
5822 /// horizontal binop dag node would take as input the lower 128-bit of V1
5823 /// and the upper 128-bit of V1.
5825 /// HADD V0_LO, V0_HI
5826 /// HADD V1_LO, V1_HI
5828 /// Otherwise, the first horizontal binop dag node takes as input the lower
5829 /// 128-bit of V0 and the lower 128-bit of V1, and the second horizontal binop
5830 /// dag node takes the upper 128-bit of V0 and the upper 128-bit of V1.
5832 /// HADD V0_LO, V1_LO
5833 /// HADD V0_HI, V1_HI
5835 /// If \p isUndefLO is set, then the algorithm propagates UNDEF to the lower
5836 /// 128-bits of the result. If \p isUndefHI is set, then UNDEF is propagated to
5837 /// the upper 128-bits of the result.
5838 static SDValue ExpandHorizontalBinOp(const SDValue &V0, const SDValue &V1,
5839 SDLoc DL, SelectionDAG &DAG,
5840 unsigned X86Opcode, bool Mode,
5841 bool isUndefLO, bool isUndefHI) {
5842 EVT VT = V0.getValueType();
5843 assert(VT.is256BitVector() && VT == V1.getValueType() &&
5844 "Invalid nodes in input!");
5846 unsigned NumElts = VT.getVectorNumElements();
5847 SDValue V0_LO = Extract128BitVector(V0, 0, DAG, DL);
5848 SDValue V0_HI = Extract128BitVector(V0, NumElts/2, DAG, DL);
5849 SDValue V1_LO = Extract128BitVector(V1, 0, DAG, DL);
5850 SDValue V1_HI = Extract128BitVector(V1, NumElts/2, DAG, DL);
5851 EVT NewVT = V0_LO.getValueType();
5853 SDValue LO = DAG.getUNDEF(NewVT);
5854 SDValue HI = DAG.getUNDEF(NewVT);
5857 // Don't emit a horizontal binop if the result is expected to be UNDEF.
5858 if (!isUndefLO && V0->getOpcode() != ISD::UNDEF)
5859 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V0_HI);
5860 if (!isUndefHI && V1->getOpcode() != ISD::UNDEF)
5861 HI = DAG.getNode(X86Opcode, DL, NewVT, V1_LO, V1_HI);
5863 // Don't emit a horizontal binop if the result is expected to be UNDEF.
5864 if (!isUndefLO && (V0_LO->getOpcode() != ISD::UNDEF ||
5865 V1_LO->getOpcode() != ISD::UNDEF))
5866 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V1_LO);
5868 if (!isUndefHI && (V0_HI->getOpcode() != ISD::UNDEF ||
5869 V1_HI->getOpcode() != ISD::UNDEF))
5870 HI = DAG.getNode(X86Opcode, DL, NewVT, V0_HI, V1_HI);
5873 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LO, HI);
5876 /// Try to fold a build_vector that performs an 'addsub' to an X86ISD::ADDSUB
5878 static SDValue LowerToAddSub(const BuildVectorSDNode *BV,
5879 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
5880 MVT VT = BV->getSimpleValueType(0);
5881 if ((!Subtarget->hasSSE3() || (VT != MVT::v4f32 && VT != MVT::v2f64)) &&
5882 (!Subtarget->hasAVX() || (VT != MVT::v8f32 && VT != MVT::v4f64)))
5886 unsigned NumElts = VT.getVectorNumElements();
5887 SDValue InVec0 = DAG.getUNDEF(VT);
5888 SDValue InVec1 = DAG.getUNDEF(VT);
5890 assert((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v4f32 ||
5891 VT == MVT::v2f64) && "build_vector with an invalid type found!");
5893 // Odd-numbered elements in the input build vector are obtained from
5894 // adding two integer/float elements.
5895 // Even-numbered elements in the input build vector are obtained from
5896 // subtracting two integer/float elements.
5897 unsigned ExpectedOpcode = ISD::FSUB;
5898 unsigned NextExpectedOpcode = ISD::FADD;
5899 bool AddFound = false;
5900 bool SubFound = false;
5902 for (unsigned i = 0, e = NumElts; i != e; ++i) {
5903 SDValue Op = BV->getOperand(i);
5905 // Skip 'undef' values.
5906 unsigned Opcode = Op.getOpcode();
5907 if (Opcode == ISD::UNDEF) {
5908 std::swap(ExpectedOpcode, NextExpectedOpcode);
5912 // Early exit if we found an unexpected opcode.
5913 if (Opcode != ExpectedOpcode)
5916 SDValue Op0 = Op.getOperand(0);
5917 SDValue Op1 = Op.getOperand(1);
5919 // Try to match the following pattern:
5920 // (BINOP (extract_vector_elt A, i), (extract_vector_elt B, i))
5921 // Early exit if we cannot match that sequence.
5922 if (Op0.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
5923 Op1.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
5924 !isa<ConstantSDNode>(Op0.getOperand(1)) ||
5925 !isa<ConstantSDNode>(Op1.getOperand(1)) ||
5926 Op0.getOperand(1) != Op1.getOperand(1))
5929 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
5933 // We found a valid add/sub node. Update the information accordingly.
5939 // Update InVec0 and InVec1.
5940 if (InVec0.getOpcode() == ISD::UNDEF) {
5941 InVec0 = Op0.getOperand(0);
5942 if (InVec0.getSimpleValueType() != VT)
5945 if (InVec1.getOpcode() == ISD::UNDEF) {
5946 InVec1 = Op1.getOperand(0);
5947 if (InVec1.getSimpleValueType() != VT)
5951 // Make sure that operands in input to each add/sub node always
5952 // come from a same pair of vectors.
5953 if (InVec0 != Op0.getOperand(0)) {
5954 if (ExpectedOpcode == ISD::FSUB)
5957 // FADD is commutable. Try to commute the operands
5958 // and then test again.
5959 std::swap(Op0, Op1);
5960 if (InVec0 != Op0.getOperand(0))
5964 if (InVec1 != Op1.getOperand(0))
5967 // Update the pair of expected opcodes.
5968 std::swap(ExpectedOpcode, NextExpectedOpcode);
5971 // Don't try to fold this build_vector into an ADDSUB if the inputs are undef.
5972 if (AddFound && SubFound && InVec0.getOpcode() != ISD::UNDEF &&
5973 InVec1.getOpcode() != ISD::UNDEF)
5974 return DAG.getNode(X86ISD::ADDSUB, DL, VT, InVec0, InVec1);
5979 /// Lower BUILD_VECTOR to a horizontal add/sub operation if possible.
5980 static SDValue LowerToHorizontalOp(const BuildVectorSDNode *BV,
5981 const X86Subtarget *Subtarget,
5982 SelectionDAG &DAG) {
5983 MVT VT = BV->getSimpleValueType(0);
5984 unsigned NumElts = VT.getVectorNumElements();
5985 unsigned NumUndefsLO = 0;
5986 unsigned NumUndefsHI = 0;
5987 unsigned Half = NumElts/2;
5989 // Count the number of UNDEF operands in the build_vector in input.
5990 for (unsigned i = 0, e = Half; i != e; ++i)
5991 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
5994 for (unsigned i = Half, e = NumElts; i != e; ++i)
5995 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
5998 // Early exit if this is either a build_vector of all UNDEFs or all the
5999 // operands but one are UNDEF.
6000 if (NumUndefsLO + NumUndefsHI + 1 >= NumElts)
6004 SDValue InVec0, InVec1;
6005 if ((VT == MVT::v4f32 || VT == MVT::v2f64) && Subtarget->hasSSE3()) {
6006 // Try to match an SSE3 float HADD/HSUB.
6007 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
6008 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
6010 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
6011 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
6012 } else if ((VT == MVT::v4i32 || VT == MVT::v8i16) && Subtarget->hasSSSE3()) {
6013 // Try to match an SSSE3 integer HADD/HSUB.
6014 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
6015 return DAG.getNode(X86ISD::HADD, DL, VT, InVec0, InVec1);
6017 if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
6018 return DAG.getNode(X86ISD::HSUB, DL, VT, InVec0, InVec1);
6021 if (!Subtarget->hasAVX())
6024 if ((VT == MVT::v8f32 || VT == MVT::v4f64)) {
6025 // Try to match an AVX horizontal add/sub of packed single/double
6026 // precision floating point values from 256-bit vectors.
6027 SDValue InVec2, InVec3;
6028 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, Half, InVec0, InVec1) &&
6029 isHorizontalBinOp(BV, ISD::FADD, DAG, Half, NumElts, InVec2, InVec3) &&
6030 ((InVec0.getOpcode() == ISD::UNDEF ||
6031 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6032 ((InVec1.getOpcode() == ISD::UNDEF ||
6033 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6034 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
6036 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, Half, InVec0, InVec1) &&
6037 isHorizontalBinOp(BV, ISD::FSUB, DAG, Half, NumElts, InVec2, InVec3) &&
6038 ((InVec0.getOpcode() == ISD::UNDEF ||
6039 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6040 ((InVec1.getOpcode() == ISD::UNDEF ||
6041 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6042 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
6043 } else if (VT == MVT::v8i32 || VT == MVT::v16i16) {
6044 // Try to match an AVX2 horizontal add/sub of signed integers.
6045 SDValue InVec2, InVec3;
6047 bool CanFold = true;
6049 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, Half, InVec0, InVec1) &&
6050 isHorizontalBinOp(BV, ISD::ADD, DAG, Half, NumElts, InVec2, InVec3) &&
6051 ((InVec0.getOpcode() == ISD::UNDEF ||
6052 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6053 ((InVec1.getOpcode() == ISD::UNDEF ||
6054 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6055 X86Opcode = X86ISD::HADD;
6056 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, Half, InVec0, InVec1) &&
6057 isHorizontalBinOp(BV, ISD::SUB, DAG, Half, NumElts, InVec2, InVec3) &&
6058 ((InVec0.getOpcode() == ISD::UNDEF ||
6059 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6060 ((InVec1.getOpcode() == ISD::UNDEF ||
6061 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6062 X86Opcode = X86ISD::HSUB;
6067 // Fold this build_vector into a single horizontal add/sub.
6068 // Do this only if the target has AVX2.
6069 if (Subtarget->hasAVX2())
6070 return DAG.getNode(X86Opcode, DL, VT, InVec0, InVec1);
6072 // Do not try to expand this build_vector into a pair of horizontal
6073 // add/sub if we can emit a pair of scalar add/sub.
6074 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
6077 // Convert this build_vector into a pair of horizontal binop followed by
6079 bool isUndefLO = NumUndefsLO == Half;
6080 bool isUndefHI = NumUndefsHI == Half;
6081 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, false,
6082 isUndefLO, isUndefHI);
6086 if ((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v8i32 ||
6087 VT == MVT::v16i16) && Subtarget->hasAVX()) {
6089 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
6090 X86Opcode = X86ISD::HADD;
6091 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
6092 X86Opcode = X86ISD::HSUB;
6093 else if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
6094 X86Opcode = X86ISD::FHADD;
6095 else if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
6096 X86Opcode = X86ISD::FHSUB;
6100 // Don't try to expand this build_vector into a pair of horizontal add/sub
6101 // if we can simply emit a pair of scalar add/sub.
6102 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
6105 // Convert this build_vector into two horizontal add/sub followed by
6107 bool isUndefLO = NumUndefsLO == Half;
6108 bool isUndefHI = NumUndefsHI == Half;
6109 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, true,
6110 isUndefLO, isUndefHI);
6117 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
6120 MVT VT = Op.getSimpleValueType();
6121 MVT ExtVT = VT.getVectorElementType();
6122 unsigned NumElems = Op.getNumOperands();
6124 // Generate vectors for predicate vectors.
6125 if (VT.getVectorElementType() == MVT::i1 && Subtarget->hasAVX512())
6126 return LowerBUILD_VECTORvXi1(Op, DAG);
6128 // Vectors containing all zeros can be matched by pxor and xorps later
6129 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
6130 // Canonicalize this to <4 x i32> to 1) ensure the zero vectors are CSE'd
6131 // and 2) ensure that i64 scalars are eliminated on x86-32 hosts.
6132 if (VT == MVT::v4i32 || VT == MVT::v8i32 || VT == MVT::v16i32)
6135 return getZeroVector(VT, Subtarget, DAG, dl);
6138 // Vectors containing all ones can be matched by pcmpeqd on 128-bit width
6139 // vectors or broken into v4i32 operations on 256-bit vectors. AVX2 can use
6140 // vpcmpeqd on 256-bit vectors.
6141 if (Subtarget->hasSSE2() && ISD::isBuildVectorAllOnes(Op.getNode())) {
6142 if (VT == MVT::v4i32 || (VT == MVT::v8i32 && Subtarget->hasInt256()))
6145 if (!VT.is512BitVector())
6146 return getOnesVector(VT, Subtarget, DAG, dl);
6149 BuildVectorSDNode *BV = cast<BuildVectorSDNode>(Op.getNode());
6150 if (SDValue AddSub = LowerToAddSub(BV, Subtarget, DAG))
6152 if (SDValue HorizontalOp = LowerToHorizontalOp(BV, Subtarget, DAG))
6153 return HorizontalOp;
6154 if (SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG))
6157 unsigned EVTBits = ExtVT.getSizeInBits();
6159 unsigned NumZero = 0;
6160 unsigned NumNonZero = 0;
6161 unsigned NonZeros = 0;
6162 bool IsAllConstants = true;
6163 SmallSet<SDValue, 8> Values;
6164 for (unsigned i = 0; i < NumElems; ++i) {
6165 SDValue Elt = Op.getOperand(i);
6166 if (Elt.getOpcode() == ISD::UNDEF)
6169 if (Elt.getOpcode() != ISD::Constant &&
6170 Elt.getOpcode() != ISD::ConstantFP)
6171 IsAllConstants = false;
6172 if (X86::isZeroNode(Elt))
6175 NonZeros |= (1 << i);
6180 // All undef vector. Return an UNDEF. All zero vectors were handled above.
6181 if (NumNonZero == 0)
6182 return DAG.getUNDEF(VT);
6184 // Special case for single non-zero, non-undef, element.
6185 if (NumNonZero == 1) {
6186 unsigned Idx = countTrailingZeros(NonZeros);
6187 SDValue Item = Op.getOperand(Idx);
6189 // If this is an insertion of an i64 value on x86-32, and if the top bits of
6190 // the value are obviously zero, truncate the value to i32 and do the
6191 // insertion that way. Only do this if the value is non-constant or if the
6192 // value is a constant being inserted into element 0. It is cheaper to do
6193 // a constant pool load than it is to do a movd + shuffle.
6194 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
6195 (!IsAllConstants || Idx == 0)) {
6196 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
6198 assert(VT == MVT::v2i64 && "Expected an SSE value type!");
6199 MVT VecVT = MVT::v4i32;
6201 // Truncate the value (which may itself be a constant) to i32, and
6202 // convert it to a vector with movd (S2V+shuffle to zero extend).
6203 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
6204 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
6205 return DAG.getBitcast(VT, getShuffleVectorZeroOrUndef(
6206 Item, Idx * 2, true, Subtarget, DAG));
6210 // If we have a constant or non-constant insertion into the low element of
6211 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
6212 // the rest of the elements. This will be matched as movd/movq/movss/movsd
6213 // depending on what the source datatype is.
6216 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6218 if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
6219 (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
6220 if (VT.is512BitVector()) {
6221 SDValue ZeroVec = getZeroVector(VT, Subtarget, DAG, dl);
6222 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, ZeroVec,
6223 Item, DAG.getIntPtrConstant(0, dl));
6225 assert((VT.is128BitVector() || VT.is256BitVector()) &&
6226 "Expected an SSE value type!");
6227 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6228 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
6229 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6232 // We can't directly insert an i8 or i16 into a vector, so zero extend
6234 if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
6235 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
6236 if (VT.is256BitVector()) {
6237 if (Subtarget->hasAVX()) {
6238 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v8i32, Item);
6239 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6241 // Without AVX, we need to extend to a 128-bit vector and then
6242 // insert into the 256-bit vector.
6243 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
6244 SDValue ZeroVec = getZeroVector(MVT::v8i32, Subtarget, DAG, dl);
6245 Item = Insert128BitVector(ZeroVec, Item, 0, DAG, dl);
6248 assert(VT.is128BitVector() && "Expected an SSE value type!");
6249 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
6250 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6252 return DAG.getBitcast(VT, Item);
6256 // Is it a vector logical left shift?
6257 if (NumElems == 2 && Idx == 1 &&
6258 X86::isZeroNode(Op.getOperand(0)) &&
6259 !X86::isZeroNode(Op.getOperand(1))) {
6260 unsigned NumBits = VT.getSizeInBits();
6261 return getVShift(true, VT,
6262 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
6263 VT, Op.getOperand(1)),
6264 NumBits/2, DAG, *this, dl);
6267 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
6270 // Otherwise, if this is a vector with i32 or f32 elements, and the element
6271 // is a non-constant being inserted into an element other than the low one,
6272 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
6273 // movd/movss) to move this into the low element, then shuffle it into
6275 if (EVTBits == 32) {
6276 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6277 return getShuffleVectorZeroOrUndef(Item, Idx, NumZero > 0, Subtarget, DAG);
6281 // Splat is obviously ok. Let legalizer expand it to a shuffle.
6282 if (Values.size() == 1) {
6283 if (EVTBits == 32) {
6284 // Instead of a shuffle like this:
6285 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
6286 // Check if it's possible to issue this instead.
6287 // shuffle (vload ptr)), undef, <1, 1, 1, 1>
6288 unsigned Idx = countTrailingZeros(NonZeros);
6289 SDValue Item = Op.getOperand(Idx);
6290 if (Op.getNode()->isOnlyUserOf(Item.getNode()))
6291 return LowerAsSplatVectorLoad(Item, VT, dl, DAG);
6296 // A vector full of immediates; various special cases are already
6297 // handled, so this is best done with a single constant-pool load.
6301 // For AVX-length vectors, see if we can use a vector load to get all of the
6302 // elements, otherwise build the individual 128-bit pieces and use
6303 // shuffles to put them in place.
6304 if (VT.is256BitVector() || VT.is512BitVector()) {
6305 SmallVector<SDValue, 64> V(Op->op_begin(), Op->op_begin() + NumElems);
6307 // Check for a build vector of consecutive loads.
6308 if (SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG, false))
6311 EVT HVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems/2);
6313 // Build both the lower and upper subvector.
6314 SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
6315 makeArrayRef(&V[0], NumElems/2));
6316 SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
6317 makeArrayRef(&V[NumElems / 2], NumElems/2));
6319 // Recreate the wider vector with the lower and upper part.
6320 if (VT.is256BitVector())
6321 return Concat128BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
6322 return Concat256BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
6325 // Let legalizer expand 2-wide build_vectors.
6326 if (EVTBits == 64) {
6327 if (NumNonZero == 1) {
6328 // One half is zero or undef.
6329 unsigned Idx = countTrailingZeros(NonZeros);
6330 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
6331 Op.getOperand(Idx));
6332 return getShuffleVectorZeroOrUndef(V2, Idx, true, Subtarget, DAG);
6337 // If element VT is < 32 bits, convert it to inserts into a zero vector.
6338 if (EVTBits == 8 && NumElems == 16)
6339 if (SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
6343 if (EVTBits == 16 && NumElems == 8)
6344 if (SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
6348 // If element VT is == 32 bits and has 4 elems, try to generate an INSERTPS
6349 if (EVTBits == 32 && NumElems == 4)
6350 if (SDValue V = LowerBuildVectorv4x32(Op, DAG, Subtarget, *this))
6353 // If element VT is == 32 bits, turn it into a number of shuffles.
6354 SmallVector<SDValue, 8> V(NumElems);
6355 if (NumElems == 4 && NumZero > 0) {
6356 for (unsigned i = 0; i < 4; ++i) {
6357 bool isZero = !(NonZeros & (1 << i));
6359 V[i] = getZeroVector(VT, Subtarget, DAG, dl);
6361 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
6364 for (unsigned i = 0; i < 2; ++i) {
6365 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
6368 V[i] = V[i*2]; // Must be a zero vector.
6371 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
6374 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
6377 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
6382 bool Reverse1 = (NonZeros & 0x3) == 2;
6383 bool Reverse2 = ((NonZeros & (0x3 << 2)) >> 2) == 2;
6387 static_cast<int>(Reverse2 ? NumElems+1 : NumElems),
6388 static_cast<int>(Reverse2 ? NumElems : NumElems+1)
6390 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
6393 if (Values.size() > 1 && VT.is128BitVector()) {
6394 // Check for a build vector of consecutive loads.
6395 for (unsigned i = 0; i < NumElems; ++i)
6396 V[i] = Op.getOperand(i);
6398 // Check for elements which are consecutive loads.
6399 if (SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG, false))
6402 // Check for a build vector from mostly shuffle plus few inserting.
6403 if (SDValue Sh = buildFromShuffleMostly(Op, DAG))
6406 // For SSE 4.1, use insertps to put the high elements into the low element.
6407 if (Subtarget->hasSSE41()) {
6409 if (Op.getOperand(0).getOpcode() != ISD::UNDEF)
6410 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0));
6412 Result = DAG.getUNDEF(VT);
6414 for (unsigned i = 1; i < NumElems; ++i) {
6415 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue;
6416 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result,
6417 Op.getOperand(i), DAG.getIntPtrConstant(i, dl));
6422 // Otherwise, expand into a number of unpckl*, start by extending each of
6423 // our (non-undef) elements to the full vector width with the element in the
6424 // bottom slot of the vector (which generates no code for SSE).
6425 for (unsigned i = 0; i < NumElems; ++i) {
6426 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
6427 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
6429 V[i] = DAG.getUNDEF(VT);
6432 // Next, we iteratively mix elements, e.g. for v4f32:
6433 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
6434 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
6435 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
6436 unsigned EltStride = NumElems >> 1;
6437 while (EltStride != 0) {
6438 for (unsigned i = 0; i < EltStride; ++i) {
6439 // If V[i+EltStride] is undef and this is the first round of mixing,
6440 // then it is safe to just drop this shuffle: V[i] is already in the
6441 // right place, the one element (since it's the first round) being
6442 // inserted as undef can be dropped. This isn't safe for successive
6443 // rounds because they will permute elements within both vectors.
6444 if (V[i+EltStride].getOpcode() == ISD::UNDEF &&
6445 EltStride == NumElems/2)
6448 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]);
6457 // 256-bit AVX can use the vinsertf128 instruction
6458 // to create 256-bit vectors from two other 128-bit ones.
6459 static SDValue LowerAVXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
6461 MVT ResVT = Op.getSimpleValueType();
6463 assert((ResVT.is256BitVector() ||
6464 ResVT.is512BitVector()) && "Value type must be 256-/512-bit wide");
6466 SDValue V1 = Op.getOperand(0);
6467 SDValue V2 = Op.getOperand(1);
6468 unsigned NumElems = ResVT.getVectorNumElements();
6469 if (ResVT.is256BitVector())
6470 return Concat128BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
6472 if (Op.getNumOperands() == 4) {
6473 MVT HalfVT = MVT::getVectorVT(ResVT.getVectorElementType(),
6474 ResVT.getVectorNumElements()/2);
6475 SDValue V3 = Op.getOperand(2);
6476 SDValue V4 = Op.getOperand(3);
6477 return Concat256BitVectors(Concat128BitVectors(V1, V2, HalfVT, NumElems/2, DAG, dl),
6478 Concat128BitVectors(V3, V4, HalfVT, NumElems/2, DAG, dl), ResVT, NumElems, DAG, dl);
6480 return Concat256BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
6483 static SDValue LowerCONCAT_VECTORSvXi1(SDValue Op,
6484 const X86Subtarget *Subtarget,
6485 SelectionDAG & DAG) {
6487 MVT ResVT = Op.getSimpleValueType();
6488 unsigned NumOfOperands = Op.getNumOperands();
6490 assert(isPowerOf2_32(NumOfOperands) &&
6491 "Unexpected number of operands in CONCAT_VECTORS");
6493 if (NumOfOperands > 2) {
6494 MVT HalfVT = MVT::getVectorVT(ResVT.getVectorElementType(),
6495 ResVT.getVectorNumElements()/2);
6496 SmallVector<SDValue, 2> Ops;
6497 for (unsigned i = 0; i < NumOfOperands/2; i++)
6498 Ops.push_back(Op.getOperand(i));
6499 SDValue Lo = DAG.getNode(ISD::CONCAT_VECTORS, dl, HalfVT, Ops);
6501 for (unsigned i = NumOfOperands/2; i < NumOfOperands; i++)
6502 Ops.push_back(Op.getOperand(i));
6503 SDValue Hi = DAG.getNode(ISD::CONCAT_VECTORS, dl, HalfVT, Ops);
6504 return DAG.getNode(ISD::CONCAT_VECTORS, dl, ResVT, Lo, Hi);
6507 SDValue V1 = Op.getOperand(0);
6508 SDValue V2 = Op.getOperand(1);
6509 bool IsZeroV1 = ISD::isBuildVectorAllZeros(V1.getNode());
6510 bool IsZeroV2 = ISD::isBuildVectorAllZeros(V2.getNode());
6512 if (IsZeroV1 && IsZeroV2)
6513 return getZeroVector(ResVT, Subtarget, DAG, dl);
6515 SDValue ZeroIdx = DAG.getIntPtrConstant(0, dl);
6516 SDValue Undef = DAG.getUNDEF(ResVT);
6517 unsigned NumElems = ResVT.getVectorNumElements();
6518 SDValue ShiftBits = DAG.getConstant(NumElems/2, dl, MVT::i8);
6520 V2 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, Undef, V2, ZeroIdx);
6521 V2 = DAG.getNode(X86ISD::VSHLI, dl, ResVT, V2, ShiftBits);
6525 V1 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, Undef, V1, ZeroIdx);
6526 // Zero the upper bits of V1
6527 V1 = DAG.getNode(X86ISD::VSHLI, dl, ResVT, V1, ShiftBits);
6528 V1 = DAG.getNode(X86ISD::VSRLI, dl, ResVT, V1, ShiftBits);
6531 return DAG.getNode(ISD::OR, dl, ResVT, V1, V2);
6534 static SDValue LowerCONCAT_VECTORS(SDValue Op,
6535 const X86Subtarget *Subtarget,
6536 SelectionDAG &DAG) {
6537 MVT VT = Op.getSimpleValueType();
6538 if (VT.getVectorElementType() == MVT::i1)
6539 return LowerCONCAT_VECTORSvXi1(Op, Subtarget, DAG);
6541 assert((VT.is256BitVector() && Op.getNumOperands() == 2) ||
6542 (VT.is512BitVector() && (Op.getNumOperands() == 2 ||
6543 Op.getNumOperands() == 4)));
6545 // AVX can use the vinsertf128 instruction to create 256-bit vectors
6546 // from two other 128-bit ones.
6548 // 512-bit vector may contain 2 256-bit vectors or 4 128-bit vectors
6549 return LowerAVXCONCAT_VECTORS(Op, DAG);
6552 //===----------------------------------------------------------------------===//
6553 // Vector shuffle lowering
6555 // This is an experimental code path for lowering vector shuffles on x86. It is
6556 // designed to handle arbitrary vector shuffles and blends, gracefully
6557 // degrading performance as necessary. It works hard to recognize idiomatic
6558 // shuffles and lower them to optimal instruction patterns without leaving
6559 // a framework that allows reasonably efficient handling of all vector shuffle
6561 //===----------------------------------------------------------------------===//
6563 /// \brief Tiny helper function to identify a no-op mask.
6565 /// This is a somewhat boring predicate function. It checks whether the mask
6566 /// array input, which is assumed to be a single-input shuffle mask of the kind
6567 /// used by the X86 shuffle instructions (not a fully general
6568 /// ShuffleVectorSDNode mask) requires any shuffles to occur. Both undef and an
6569 /// in-place shuffle are 'no-op's.
6570 static bool isNoopShuffleMask(ArrayRef<int> Mask) {
6571 for (int i = 0, Size = Mask.size(); i < Size; ++i)
6572 if (Mask[i] != -1 && Mask[i] != i)
6577 /// \brief Helper function to classify a mask as a single-input mask.
6579 /// This isn't a generic single-input test because in the vector shuffle
6580 /// lowering we canonicalize single inputs to be the first input operand. This
6581 /// means we can more quickly test for a single input by only checking whether
6582 /// an input from the second operand exists. We also assume that the size of
6583 /// mask corresponds to the size of the input vectors which isn't true in the
6584 /// fully general case.
6585 static bool isSingleInputShuffleMask(ArrayRef<int> Mask) {
6587 if (M >= (int)Mask.size())
6592 /// \brief Test whether there are elements crossing 128-bit lanes in this
6595 /// X86 divides up its shuffles into in-lane and cross-lane shuffle operations
6596 /// and we routinely test for these.
6597 static bool is128BitLaneCrossingShuffleMask(MVT VT, ArrayRef<int> Mask) {
6598 int LaneSize = 128 / VT.getScalarSizeInBits();
6599 int Size = Mask.size();
6600 for (int i = 0; i < Size; ++i)
6601 if (Mask[i] >= 0 && (Mask[i] % Size) / LaneSize != i / LaneSize)
6606 /// \brief Test whether a shuffle mask is equivalent within each 128-bit lane.
6608 /// This checks a shuffle mask to see if it is performing the same
6609 /// 128-bit lane-relative shuffle in each 128-bit lane. This trivially implies
6610 /// that it is also not lane-crossing. It may however involve a blend from the
6611 /// same lane of a second vector.
6613 /// The specific repeated shuffle mask is populated in \p RepeatedMask, as it is
6614 /// non-trivial to compute in the face of undef lanes. The representation is
6615 /// *not* suitable for use with existing 128-bit shuffles as it will contain
6616 /// entries from both V1 and V2 inputs to the wider mask.
6618 is128BitLaneRepeatedShuffleMask(MVT VT, ArrayRef<int> Mask,
6619 SmallVectorImpl<int> &RepeatedMask) {
6620 int LaneSize = 128 / VT.getScalarSizeInBits();
6621 RepeatedMask.resize(LaneSize, -1);
6622 int Size = Mask.size();
6623 for (int i = 0; i < Size; ++i) {
6626 if ((Mask[i] % Size) / LaneSize != i / LaneSize)
6627 // This entry crosses lanes, so there is no way to model this shuffle.
6630 // Ok, handle the in-lane shuffles by detecting if and when they repeat.
6631 if (RepeatedMask[i % LaneSize] == -1)
6632 // This is the first non-undef entry in this slot of a 128-bit lane.
6633 RepeatedMask[i % LaneSize] =
6634 Mask[i] < Size ? Mask[i] % LaneSize : Mask[i] % LaneSize + Size;
6635 else if (RepeatedMask[i % LaneSize] + (i / LaneSize) * LaneSize != Mask[i])
6636 // Found a mismatch with the repeated mask.
6642 /// \brief Checks whether a shuffle mask is equivalent to an explicit list of
6645 /// This is a fast way to test a shuffle mask against a fixed pattern:
6647 /// if (isShuffleEquivalent(Mask, 3, 2, {1, 0})) { ... }
6649 /// It returns true if the mask is exactly as wide as the argument list, and
6650 /// each element of the mask is either -1 (signifying undef) or the value given
6651 /// in the argument.
6652 static bool isShuffleEquivalent(SDValue V1, SDValue V2, ArrayRef<int> Mask,
6653 ArrayRef<int> ExpectedMask) {
6654 if (Mask.size() != ExpectedMask.size())
6657 int Size = Mask.size();
6659 // If the values are build vectors, we can look through them to find
6660 // equivalent inputs that make the shuffles equivalent.
6661 auto *BV1 = dyn_cast<BuildVectorSDNode>(V1);
6662 auto *BV2 = dyn_cast<BuildVectorSDNode>(V2);
6664 for (int i = 0; i < Size; ++i)
6665 if (Mask[i] != -1 && Mask[i] != ExpectedMask[i]) {
6666 auto *MaskBV = Mask[i] < Size ? BV1 : BV2;
6667 auto *ExpectedBV = ExpectedMask[i] < Size ? BV1 : BV2;
6668 if (!MaskBV || !ExpectedBV ||
6669 MaskBV->getOperand(Mask[i] % Size) !=
6670 ExpectedBV->getOperand(ExpectedMask[i] % Size))
6677 /// \brief Get a 4-lane 8-bit shuffle immediate for a mask.
6679 /// This helper function produces an 8-bit shuffle immediate corresponding to
6680 /// the ubiquitous shuffle encoding scheme used in x86 instructions for
6681 /// shuffling 4 lanes. It can be used with most of the PSHUF instructions for
6684 /// NB: We rely heavily on "undef" masks preserving the input lane.
6685 static SDValue getV4X86ShuffleImm8ForMask(ArrayRef<int> Mask, SDLoc DL,
6686 SelectionDAG &DAG) {
6687 assert(Mask.size() == 4 && "Only 4-lane shuffle masks");
6688 assert(Mask[0] >= -1 && Mask[0] < 4 && "Out of bound mask element!");
6689 assert(Mask[1] >= -1 && Mask[1] < 4 && "Out of bound mask element!");
6690 assert(Mask[2] >= -1 && Mask[2] < 4 && "Out of bound mask element!");
6691 assert(Mask[3] >= -1 && Mask[3] < 4 && "Out of bound mask element!");
6694 Imm |= (Mask[0] == -1 ? 0 : Mask[0]) << 0;
6695 Imm |= (Mask[1] == -1 ? 1 : Mask[1]) << 2;
6696 Imm |= (Mask[2] == -1 ? 2 : Mask[2]) << 4;
6697 Imm |= (Mask[3] == -1 ? 3 : Mask[3]) << 6;
6698 return DAG.getConstant(Imm, DL, MVT::i8);
6701 /// \brief Compute whether each element of a shuffle is zeroable.
6703 /// A "zeroable" vector shuffle element is one which can be lowered to zero.
6704 /// Either it is an undef element in the shuffle mask, the element of the input
6705 /// referenced is undef, or the element of the input referenced is known to be
6706 /// zero. Many x86 shuffles can zero lanes cheaply and we often want to handle
6707 /// as many lanes with this technique as possible to simplify the remaining
6709 static SmallBitVector computeZeroableShuffleElements(ArrayRef<int> Mask,
6710 SDValue V1, SDValue V2) {
6711 SmallBitVector Zeroable(Mask.size(), false);
6713 while (V1.getOpcode() == ISD::BITCAST)
6714 V1 = V1->getOperand(0);
6715 while (V2.getOpcode() == ISD::BITCAST)
6716 V2 = V2->getOperand(0);
6718 bool V1IsZero = ISD::isBuildVectorAllZeros(V1.getNode());
6719 bool V2IsZero = ISD::isBuildVectorAllZeros(V2.getNode());
6721 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6723 // Handle the easy cases.
6724 if (M < 0 || (M >= 0 && M < Size && V1IsZero) || (M >= Size && V2IsZero)) {
6729 // If this is an index into a build_vector node (which has the same number
6730 // of elements), dig out the input value and use it.
6731 SDValue V = M < Size ? V1 : V2;
6732 if (V.getOpcode() != ISD::BUILD_VECTOR || Size != (int)V.getNumOperands())
6735 SDValue Input = V.getOperand(M % Size);
6736 // The UNDEF opcode check really should be dead code here, but not quite
6737 // worth asserting on (it isn't invalid, just unexpected).
6738 if (Input.getOpcode() == ISD::UNDEF || X86::isZeroNode(Input))
6745 // X86 has dedicated unpack instructions that can handle specific blend
6746 // operations: UNPCKH and UNPCKL.
6747 static SDValue lowerVectorShuffleWithUNPCK(SDLoc DL, MVT VT, ArrayRef<int> Mask,
6748 SDValue V1, SDValue V2,
6749 SelectionDAG &DAG) {
6750 int NumElts = VT.getVectorNumElements();
6751 int NumEltsInLane = 128 / VT.getScalarSizeInBits();
6752 SmallVector<int, 8> Unpckl;
6753 SmallVector<int, 8> Unpckh;
6755 for (int i = 0; i < NumElts; ++i) {
6756 unsigned LaneStart = (i / NumEltsInLane) * NumEltsInLane;
6757 int LoPos = (i % NumEltsInLane) / 2 + LaneStart + NumElts * (i % 2);
6758 int HiPos = LoPos + NumEltsInLane / 2;
6759 Unpckl.push_back(LoPos);
6760 Unpckh.push_back(HiPos);
6763 if (isShuffleEquivalent(V1, V2, Mask, Unpckl))
6764 return DAG.getNode(X86ISD::UNPCKL, DL, VT, V1, V2);
6765 if (isShuffleEquivalent(V1, V2, Mask, Unpckh))
6766 return DAG.getNode(X86ISD::UNPCKH, DL, VT, V1, V2);
6768 // Commute and try again.
6769 ShuffleVectorSDNode::commuteMask(Unpckl);
6770 if (isShuffleEquivalent(V1, V2, Mask, Unpckl))
6771 return DAG.getNode(X86ISD::UNPCKL, DL, VT, V2, V1);
6773 ShuffleVectorSDNode::commuteMask(Unpckh);
6774 if (isShuffleEquivalent(V1, V2, Mask, Unpckh))
6775 return DAG.getNode(X86ISD::UNPCKH, DL, VT, V2, V1);
6780 /// \brief Try to emit a bitmask instruction for a shuffle.
6782 /// This handles cases where we can model a blend exactly as a bitmask due to
6783 /// one of the inputs being zeroable.
6784 static SDValue lowerVectorShuffleAsBitMask(SDLoc DL, MVT VT, SDValue V1,
6785 SDValue V2, ArrayRef<int> Mask,
6786 SelectionDAG &DAG) {
6787 MVT EltVT = VT.getVectorElementType();
6788 int NumEltBits = EltVT.getSizeInBits();
6789 MVT IntEltVT = MVT::getIntegerVT(NumEltBits);
6790 SDValue Zero = DAG.getConstant(0, DL, IntEltVT);
6791 SDValue AllOnes = DAG.getConstant(APInt::getAllOnesValue(NumEltBits), DL,
6793 if (EltVT.isFloatingPoint()) {
6794 Zero = DAG.getBitcast(EltVT, Zero);
6795 AllOnes = DAG.getBitcast(EltVT, AllOnes);
6797 SmallVector<SDValue, 16> VMaskOps(Mask.size(), Zero);
6798 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
6800 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6803 if (Mask[i] % Size != i)
6804 return SDValue(); // Not a blend.
6806 V = Mask[i] < Size ? V1 : V2;
6807 else if (V != (Mask[i] < Size ? V1 : V2))
6808 return SDValue(); // Can only let one input through the mask.
6810 VMaskOps[i] = AllOnes;
6813 return SDValue(); // No non-zeroable elements!
6815 SDValue VMask = DAG.getNode(ISD::BUILD_VECTOR, DL, VT, VMaskOps);
6816 V = DAG.getNode(VT.isFloatingPoint()
6817 ? (unsigned) X86ISD::FAND : (unsigned) ISD::AND,
6822 /// \brief Try to emit a blend instruction for a shuffle using bit math.
6824 /// This is used as a fallback approach when first class blend instructions are
6825 /// unavailable. Currently it is only suitable for integer vectors, but could
6826 /// be generalized for floating point vectors if desirable.
6827 static SDValue lowerVectorShuffleAsBitBlend(SDLoc DL, MVT VT, SDValue V1,
6828 SDValue V2, ArrayRef<int> Mask,
6829 SelectionDAG &DAG) {
6830 assert(VT.isInteger() && "Only supports integer vector types!");
6831 MVT EltVT = VT.getVectorElementType();
6832 int NumEltBits = EltVT.getSizeInBits();
6833 SDValue Zero = DAG.getConstant(0, DL, EltVT);
6834 SDValue AllOnes = DAG.getConstant(APInt::getAllOnesValue(NumEltBits), DL,
6836 SmallVector<SDValue, 16> MaskOps;
6837 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6838 if (Mask[i] != -1 && Mask[i] != i && Mask[i] != i + Size)
6839 return SDValue(); // Shuffled input!
6840 MaskOps.push_back(Mask[i] < Size ? AllOnes : Zero);
6843 SDValue V1Mask = DAG.getNode(ISD::BUILD_VECTOR, DL, VT, MaskOps);
6844 V1 = DAG.getNode(ISD::AND, DL, VT, V1, V1Mask);
6845 // We have to cast V2 around.
6846 MVT MaskVT = MVT::getVectorVT(MVT::i64, VT.getSizeInBits() / 64);
6847 V2 = DAG.getBitcast(VT, DAG.getNode(X86ISD::ANDNP, DL, MaskVT,
6848 DAG.getBitcast(MaskVT, V1Mask),
6849 DAG.getBitcast(MaskVT, V2)));
6850 return DAG.getNode(ISD::OR, DL, VT, V1, V2);
6853 /// \brief Try to emit a blend instruction for a shuffle.
6855 /// This doesn't do any checks for the availability of instructions for blending
6856 /// these values. It relies on the availability of the X86ISD::BLENDI pattern to
6857 /// be matched in the backend with the type given. What it does check for is
6858 /// that the shuffle mask is a blend, or convertible into a blend with zero.
6859 static SDValue lowerVectorShuffleAsBlend(SDLoc DL, MVT VT, SDValue V1,
6860 SDValue V2, ArrayRef<int> Original,
6861 const X86Subtarget *Subtarget,
6862 SelectionDAG &DAG) {
6863 bool V1IsZero = ISD::isBuildVectorAllZeros(V1.getNode());
6864 bool V2IsZero = ISD::isBuildVectorAllZeros(V2.getNode());
6865 SmallVector<int, 8> Mask(Original.begin(), Original.end());
6866 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
6867 bool ForceV1Zero = false, ForceV2Zero = false;
6869 // Attempt to generate the binary blend mask. If an input is zero then
6870 // we can use any lane.
6871 // TODO: generalize the zero matching to any scalar like isShuffleEquivalent.
6872 unsigned BlendMask = 0;
6873 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6879 if (M == i + Size) {
6880 BlendMask |= 1u << i;
6891 BlendMask |= 1u << i;
6896 return SDValue(); // Shuffled input!
6899 // Create a REAL zero vector - ISD::isBuildVectorAllZeros allows UNDEFs.
6901 V1 = getZeroVector(VT, Subtarget, DAG, DL);
6903 V2 = getZeroVector(VT, Subtarget, DAG, DL);
6905 auto ScaleBlendMask = [](unsigned BlendMask, int Size, int Scale) {
6906 unsigned ScaledMask = 0;
6907 for (int i = 0; i != Size; ++i)
6908 if (BlendMask & (1u << i))
6909 for (int j = 0; j != Scale; ++j)
6910 ScaledMask |= 1u << (i * Scale + j);
6914 switch (VT.SimpleTy) {
6919 return DAG.getNode(X86ISD::BLENDI, DL, VT, V1, V2,
6920 DAG.getConstant(BlendMask, DL, MVT::i8));
6924 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
6928 // If we have AVX2 it is faster to use VPBLENDD when the shuffle fits into
6929 // that instruction.
6930 if (Subtarget->hasAVX2()) {
6931 // Scale the blend by the number of 32-bit dwords per element.
6932 int Scale = VT.getScalarSizeInBits() / 32;
6933 BlendMask = ScaleBlendMask(BlendMask, Mask.size(), Scale);
6934 MVT BlendVT = VT.getSizeInBits() > 128 ? MVT::v8i32 : MVT::v4i32;
6935 V1 = DAG.getBitcast(BlendVT, V1);
6936 V2 = DAG.getBitcast(BlendVT, V2);
6937 return DAG.getBitcast(
6938 VT, DAG.getNode(X86ISD::BLENDI, DL, BlendVT, V1, V2,
6939 DAG.getConstant(BlendMask, DL, MVT::i8)));
6943 // For integer shuffles we need to expand the mask and cast the inputs to
6944 // v8i16s prior to blending.
6945 int Scale = 8 / VT.getVectorNumElements();
6946 BlendMask = ScaleBlendMask(BlendMask, Mask.size(), Scale);
6947 V1 = DAG.getBitcast(MVT::v8i16, V1);
6948 V2 = DAG.getBitcast(MVT::v8i16, V2);
6949 return DAG.getBitcast(VT,
6950 DAG.getNode(X86ISD::BLENDI, DL, MVT::v8i16, V1, V2,
6951 DAG.getConstant(BlendMask, DL, MVT::i8)));
6955 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
6956 SmallVector<int, 8> RepeatedMask;
6957 if (is128BitLaneRepeatedShuffleMask(MVT::v16i16, Mask, RepeatedMask)) {
6958 // We can lower these with PBLENDW which is mirrored across 128-bit lanes.
6959 assert(RepeatedMask.size() == 8 && "Repeated mask size doesn't match!");
6961 for (int i = 0; i < 8; ++i)
6962 if (RepeatedMask[i] >= 16)
6963 BlendMask |= 1u << i;
6964 return DAG.getNode(X86ISD::BLENDI, DL, MVT::v16i16, V1, V2,
6965 DAG.getConstant(BlendMask, DL, MVT::i8));
6971 assert((VT.is128BitVector() || Subtarget->hasAVX2()) &&
6972 "256-bit byte-blends require AVX2 support!");
6974 // Attempt to lower to a bitmask if we can. VPAND is faster than VPBLENDVB.
6975 if (SDValue Masked = lowerVectorShuffleAsBitMask(DL, VT, V1, V2, Mask, DAG))
6978 // Scale the blend by the number of bytes per element.
6979 int Scale = VT.getScalarSizeInBits() / 8;
6981 // This form of blend is always done on bytes. Compute the byte vector
6983 MVT BlendVT = MVT::getVectorVT(MVT::i8, VT.getSizeInBits() / 8);
6985 // Compute the VSELECT mask. Note that VSELECT is really confusing in the
6986 // mix of LLVM's code generator and the x86 backend. We tell the code
6987 // generator that boolean values in the elements of an x86 vector register
6988 // are -1 for true and 0 for false. We then use the LLVM semantics of 'true'
6989 // mapping a select to operand #1, and 'false' mapping to operand #2. The
6990 // reality in x86 is that vector masks (pre-AVX-512) use only the high bit
6991 // of the element (the remaining are ignored) and 0 in that high bit would
6992 // mean operand #1 while 1 in the high bit would mean operand #2. So while
6993 // the LLVM model for boolean values in vector elements gets the relevant
6994 // bit set, it is set backwards and over constrained relative to x86's
6996 SmallVector<SDValue, 32> VSELECTMask;
6997 for (int i = 0, Size = Mask.size(); i < Size; ++i)
6998 for (int j = 0; j < Scale; ++j)
6999 VSELECTMask.push_back(
7000 Mask[i] < 0 ? DAG.getUNDEF(MVT::i8)
7001 : DAG.getConstant(Mask[i] < Size ? -1 : 0, DL,
7004 V1 = DAG.getBitcast(BlendVT, V1);
7005 V2 = DAG.getBitcast(BlendVT, V2);
7006 return DAG.getBitcast(VT, DAG.getNode(ISD::VSELECT, DL, BlendVT,
7007 DAG.getNode(ISD::BUILD_VECTOR, DL,
7008 BlendVT, VSELECTMask),
7013 llvm_unreachable("Not a supported integer vector type!");
7017 /// \brief Try to lower as a blend of elements from two inputs followed by
7018 /// a single-input permutation.
7020 /// This matches the pattern where we can blend elements from two inputs and
7021 /// then reduce the shuffle to a single-input permutation.
7022 static SDValue lowerVectorShuffleAsBlendAndPermute(SDLoc DL, MVT VT, SDValue V1,
7025 SelectionDAG &DAG) {
7026 // We build up the blend mask while checking whether a blend is a viable way
7027 // to reduce the shuffle.
7028 SmallVector<int, 32> BlendMask(Mask.size(), -1);
7029 SmallVector<int, 32> PermuteMask(Mask.size(), -1);
7031 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
7035 assert(Mask[i] < Size * 2 && "Shuffle input is out of bounds.");
7037 if (BlendMask[Mask[i] % Size] == -1)
7038 BlendMask[Mask[i] % Size] = Mask[i];
7039 else if (BlendMask[Mask[i] % Size] != Mask[i])
7040 return SDValue(); // Can't blend in the needed input!
7042 PermuteMask[i] = Mask[i] % Size;
7045 SDValue V = DAG.getVectorShuffle(VT, DL, V1, V2, BlendMask);
7046 return DAG.getVectorShuffle(VT, DL, V, DAG.getUNDEF(VT), PermuteMask);
7049 /// \brief Generic routine to decompose a shuffle and blend into indepndent
7050 /// blends and permutes.
7052 /// This matches the extremely common pattern for handling combined
7053 /// shuffle+blend operations on newer X86 ISAs where we have very fast blend
7054 /// operations. It will try to pick the best arrangement of shuffles and
7056 static SDValue lowerVectorShuffleAsDecomposedShuffleBlend(SDLoc DL, MVT VT,
7060 SelectionDAG &DAG) {
7061 // Shuffle the input elements into the desired positions in V1 and V2 and
7062 // blend them together.
7063 SmallVector<int, 32> V1Mask(Mask.size(), -1);
7064 SmallVector<int, 32> V2Mask(Mask.size(), -1);
7065 SmallVector<int, 32> BlendMask(Mask.size(), -1);
7066 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7067 if (Mask[i] >= 0 && Mask[i] < Size) {
7068 V1Mask[i] = Mask[i];
7070 } else if (Mask[i] >= Size) {
7071 V2Mask[i] = Mask[i] - Size;
7072 BlendMask[i] = i + Size;
7075 // Try to lower with the simpler initial blend strategy unless one of the
7076 // input shuffles would be a no-op. We prefer to shuffle inputs as the
7077 // shuffle may be able to fold with a load or other benefit. However, when
7078 // we'll have to do 2x as many shuffles in order to achieve this, blending
7079 // first is a better strategy.
7080 if (!isNoopShuffleMask(V1Mask) && !isNoopShuffleMask(V2Mask))
7081 if (SDValue BlendPerm =
7082 lowerVectorShuffleAsBlendAndPermute(DL, VT, V1, V2, Mask, DAG))
7085 V1 = DAG.getVectorShuffle(VT, DL, V1, DAG.getUNDEF(VT), V1Mask);
7086 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Mask);
7087 return DAG.getVectorShuffle(VT, DL, V1, V2, BlendMask);
7090 /// \brief Try to lower a vector shuffle as a byte rotation.
7092 /// SSSE3 has a generic PALIGNR instruction in x86 that will do an arbitrary
7093 /// byte-rotation of the concatenation of two vectors; pre-SSSE3 can use
7094 /// a PSRLDQ/PSLLDQ/POR pattern to get a similar effect. This routine will
7095 /// try to generically lower a vector shuffle through such an pattern. It
7096 /// does not check for the profitability of lowering either as PALIGNR or
7097 /// PSRLDQ/PSLLDQ/POR, only whether the mask is valid to lower in that form.
7098 /// This matches shuffle vectors that look like:
7100 /// v8i16 [11, 12, 13, 14, 15, 0, 1, 2]
7102 /// Essentially it concatenates V1 and V2, shifts right by some number of
7103 /// elements, and takes the low elements as the result. Note that while this is
7104 /// specified as a *right shift* because x86 is little-endian, it is a *left
7105 /// rotate* of the vector lanes.
7106 static SDValue lowerVectorShuffleAsByteRotate(SDLoc DL, MVT VT, SDValue V1,
7109 const X86Subtarget *Subtarget,
7110 SelectionDAG &DAG) {
7111 assert(!isNoopShuffleMask(Mask) && "We shouldn't lower no-op shuffles!");
7113 int NumElts = Mask.size();
7114 int NumLanes = VT.getSizeInBits() / 128;
7115 int NumLaneElts = NumElts / NumLanes;
7117 // We need to detect various ways of spelling a rotation:
7118 // [11, 12, 13, 14, 15, 0, 1, 2]
7119 // [-1, 12, 13, 14, -1, -1, 1, -1]
7120 // [-1, -1, -1, -1, -1, -1, 1, 2]
7121 // [ 3, 4, 5, 6, 7, 8, 9, 10]
7122 // [-1, 4, 5, 6, -1, -1, 9, -1]
7123 // [-1, 4, 5, 6, -1, -1, -1, -1]
7126 for (int l = 0; l < NumElts; l += NumLaneElts) {
7127 for (int i = 0; i < NumLaneElts; ++i) {
7128 if (Mask[l + i] == -1)
7130 assert(Mask[l + i] >= 0 && "Only -1 is a valid negative mask element!");
7132 // Get the mod-Size index and lane correct it.
7133 int LaneIdx = (Mask[l + i] % NumElts) - l;
7134 // Make sure it was in this lane.
7135 if (LaneIdx < 0 || LaneIdx >= NumLaneElts)
7138 // Determine where a rotated vector would have started.
7139 int StartIdx = i - LaneIdx;
7141 // The identity rotation isn't interesting, stop.
7144 // If we found the tail of a vector the rotation must be the missing
7145 // front. If we found the head of a vector, it must be how much of the
7147 int CandidateRotation = StartIdx < 0 ? -StartIdx : NumLaneElts - StartIdx;
7150 Rotation = CandidateRotation;
7151 else if (Rotation != CandidateRotation)
7152 // The rotations don't match, so we can't match this mask.
7155 // Compute which value this mask is pointing at.
7156 SDValue MaskV = Mask[l + i] < NumElts ? V1 : V2;
7158 // Compute which of the two target values this index should be assigned
7159 // to. This reflects whether the high elements are remaining or the low
7160 // elements are remaining.
7161 SDValue &TargetV = StartIdx < 0 ? Hi : Lo;
7163 // Either set up this value if we've not encountered it before, or check
7164 // that it remains consistent.
7167 else if (TargetV != MaskV)
7168 // This may be a rotation, but it pulls from the inputs in some
7169 // unsupported interleaving.
7174 // Check that we successfully analyzed the mask, and normalize the results.
7175 assert(Rotation != 0 && "Failed to locate a viable rotation!");
7176 assert((Lo || Hi) && "Failed to find a rotated input vector!");
7182 // The actual rotate instruction rotates bytes, so we need to scale the
7183 // rotation based on how many bytes are in the vector lane.
7184 int Scale = 16 / NumLaneElts;
7186 // SSSE3 targets can use the palignr instruction.
7187 if (Subtarget->hasSSSE3()) {
7188 // Cast the inputs to i8 vector of correct length to match PALIGNR.
7189 MVT AlignVT = MVT::getVectorVT(MVT::i8, 16 * NumLanes);
7190 Lo = DAG.getBitcast(AlignVT, Lo);
7191 Hi = DAG.getBitcast(AlignVT, Hi);
7193 return DAG.getBitcast(
7194 VT, DAG.getNode(X86ISD::PALIGNR, DL, AlignVT, Lo, Hi,
7195 DAG.getConstant(Rotation * Scale, DL, MVT::i8)));
7198 assert(VT.is128BitVector() &&
7199 "Rotate-based lowering only supports 128-bit lowering!");
7200 assert(Mask.size() <= 16 &&
7201 "Can shuffle at most 16 bytes in a 128-bit vector!");
7203 // Default SSE2 implementation
7204 int LoByteShift = 16 - Rotation * Scale;
7205 int HiByteShift = Rotation * Scale;
7207 // Cast the inputs to v2i64 to match PSLLDQ/PSRLDQ.
7208 Lo = DAG.getBitcast(MVT::v2i64, Lo);
7209 Hi = DAG.getBitcast(MVT::v2i64, Hi);
7211 SDValue LoShift = DAG.getNode(X86ISD::VSHLDQ, DL, MVT::v2i64, Lo,
7212 DAG.getConstant(LoByteShift, DL, MVT::i8));
7213 SDValue HiShift = DAG.getNode(X86ISD::VSRLDQ, DL, MVT::v2i64, Hi,
7214 DAG.getConstant(HiByteShift, DL, MVT::i8));
7215 return DAG.getBitcast(VT,
7216 DAG.getNode(ISD::OR, DL, MVT::v2i64, LoShift, HiShift));
7219 /// \brief Try to lower a vector shuffle as a bit shift (shifts in zeros).
7221 /// Attempts to match a shuffle mask against the PSLL(W/D/Q/DQ) and
7222 /// PSRL(W/D/Q/DQ) SSE2 and AVX2 logical bit-shift instructions. The function
7223 /// matches elements from one of the input vectors shuffled to the left or
7224 /// right with zeroable elements 'shifted in'. It handles both the strictly
7225 /// bit-wise element shifts and the byte shift across an entire 128-bit double
7228 /// PSHL : (little-endian) left bit shift.
7229 /// [ zz, 0, zz, 2 ]
7230 /// [ -1, 4, zz, -1 ]
7231 /// PSRL : (little-endian) right bit shift.
7233 /// [ -1, -1, 7, zz]
7234 /// PSLLDQ : (little-endian) left byte shift
7235 /// [ zz, 0, 1, 2, 3, 4, 5, 6]
7236 /// [ zz, zz, -1, -1, 2, 3, 4, -1]
7237 /// [ zz, zz, zz, zz, zz, zz, -1, 1]
7238 /// PSRLDQ : (little-endian) right byte shift
7239 /// [ 5, 6, 7, zz, zz, zz, zz, zz]
7240 /// [ -1, 5, 6, 7, zz, zz, zz, zz]
7241 /// [ 1, 2, -1, -1, -1, -1, zz, zz]
7242 static SDValue lowerVectorShuffleAsShift(SDLoc DL, MVT VT, SDValue V1,
7243 SDValue V2, ArrayRef<int> Mask,
7244 SelectionDAG &DAG) {
7245 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7247 int Size = Mask.size();
7248 assert(Size == (int)VT.getVectorNumElements() && "Unexpected mask size");
7250 auto CheckZeros = [&](int Shift, int Scale, bool Left) {
7251 for (int i = 0; i < Size; i += Scale)
7252 for (int j = 0; j < Shift; ++j)
7253 if (!Zeroable[i + j + (Left ? 0 : (Scale - Shift))])
7259 auto MatchShift = [&](int Shift, int Scale, bool Left, SDValue V) {
7260 for (int i = 0; i != Size; i += Scale) {
7261 unsigned Pos = Left ? i + Shift : i;
7262 unsigned Low = Left ? i : i + Shift;
7263 unsigned Len = Scale - Shift;
7264 if (!isSequentialOrUndefInRange(Mask, Pos, Len,
7265 Low + (V == V1 ? 0 : Size)))
7269 int ShiftEltBits = VT.getScalarSizeInBits() * Scale;
7270 bool ByteShift = ShiftEltBits > 64;
7271 unsigned OpCode = Left ? (ByteShift ? X86ISD::VSHLDQ : X86ISD::VSHLI)
7272 : (ByteShift ? X86ISD::VSRLDQ : X86ISD::VSRLI);
7273 int ShiftAmt = Shift * VT.getScalarSizeInBits() / (ByteShift ? 8 : 1);
7275 // Normalize the scale for byte shifts to still produce an i64 element
7277 Scale = ByteShift ? Scale / 2 : Scale;
7279 // We need to round trip through the appropriate type for the shift.
7280 MVT ShiftSVT = MVT::getIntegerVT(VT.getScalarSizeInBits() * Scale);
7281 MVT ShiftVT = MVT::getVectorVT(ShiftSVT, Size / Scale);
7282 assert(DAG.getTargetLoweringInfo().isTypeLegal(ShiftVT) &&
7283 "Illegal integer vector type");
7284 V = DAG.getBitcast(ShiftVT, V);
7286 V = DAG.getNode(OpCode, DL, ShiftVT, V,
7287 DAG.getConstant(ShiftAmt, DL, MVT::i8));
7288 return DAG.getBitcast(VT, V);
7291 // SSE/AVX supports logical shifts up to 64-bit integers - so we can just
7292 // keep doubling the size of the integer elements up to that. We can
7293 // then shift the elements of the integer vector by whole multiples of
7294 // their width within the elements of the larger integer vector. Test each
7295 // multiple to see if we can find a match with the moved element indices
7296 // and that the shifted in elements are all zeroable.
7297 for (int Scale = 2; Scale * VT.getScalarSizeInBits() <= 128; Scale *= 2)
7298 for (int Shift = 1; Shift != Scale; ++Shift)
7299 for (bool Left : {true, false})
7300 if (CheckZeros(Shift, Scale, Left))
7301 for (SDValue V : {V1, V2})
7302 if (SDValue Match = MatchShift(Shift, Scale, Left, V))
7309 /// \brief Try to lower a vector shuffle using SSE4a EXTRQ/INSERTQ.
7310 static SDValue lowerVectorShuffleWithSSE4A(SDLoc DL, MVT VT, SDValue V1,
7311 SDValue V2, ArrayRef<int> Mask,
7312 SelectionDAG &DAG) {
7313 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7314 assert(!Zeroable.all() && "Fully zeroable shuffle mask");
7316 int Size = Mask.size();
7317 int HalfSize = Size / 2;
7318 assert(Size == (int)VT.getVectorNumElements() && "Unexpected mask size");
7320 // Upper half must be undefined.
7321 if (!isUndefInRange(Mask, HalfSize, HalfSize))
7324 // EXTRQ: Extract Len elements from lower half of source, starting at Idx.
7325 // Remainder of lower half result is zero and upper half is all undef.
7326 auto LowerAsEXTRQ = [&]() {
7327 // Determine the extraction length from the part of the
7328 // lower half that isn't zeroable.
7330 for (; Len > 0; --Len)
7331 if (!Zeroable[Len - 1])
7333 assert(Len > 0 && "Zeroable shuffle mask");
7335 // Attempt to match first Len sequential elements from the lower half.
7338 for (int i = 0; i != Len; ++i) {
7342 SDValue &V = (M < Size ? V1 : V2);
7345 // All mask elements must be in the lower half.
7349 if (Idx < 0 || (Src == V && Idx == (M - i))) {
7360 assert((Idx + Len) <= HalfSize && "Illegal extraction mask");
7361 int BitLen = (Len * VT.getScalarSizeInBits()) & 0x3f;
7362 int BitIdx = (Idx * VT.getScalarSizeInBits()) & 0x3f;
7363 return DAG.getNode(X86ISD::EXTRQI, DL, VT, Src,
7364 DAG.getConstant(BitLen, DL, MVT::i8),
7365 DAG.getConstant(BitIdx, DL, MVT::i8));
7368 if (SDValue ExtrQ = LowerAsEXTRQ())
7371 // INSERTQ: Extract lowest Len elements from lower half of second source and
7372 // insert over first source, starting at Idx.
7373 // { A[0], .., A[Idx-1], B[0], .., B[Len-1], A[Idx+Len], .., UNDEF, ... }
7374 auto LowerAsInsertQ = [&]() {
7375 for (int Idx = 0; Idx != HalfSize; ++Idx) {
7378 // Attempt to match first source from mask before insertion point.
7379 if (isUndefInRange(Mask, 0, Idx)) {
7381 } else if (isSequentialOrUndefInRange(Mask, 0, Idx, 0)) {
7383 } else if (isSequentialOrUndefInRange(Mask, 0, Idx, Size)) {
7389 // Extend the extraction length looking to match both the insertion of
7390 // the second source and the remaining elements of the first.
7391 for (int Hi = Idx + 1; Hi <= HalfSize; ++Hi) {
7396 if (isSequentialOrUndefInRange(Mask, Idx, Len, 0)) {
7398 } else if (isSequentialOrUndefInRange(Mask, Idx, Len, Size)) {
7404 // Match the remaining elements of the lower half.
7405 if (isUndefInRange(Mask, Hi, HalfSize - Hi)) {
7407 } else if ((!Base || (Base == V1)) &&
7408 isSequentialOrUndefInRange(Mask, Hi, HalfSize - Hi, Hi)) {
7410 } else if ((!Base || (Base == V2)) &&
7411 isSequentialOrUndefInRange(Mask, Hi, HalfSize - Hi,
7418 // We may not have a base (first source) - this can safely be undefined.
7420 Base = DAG.getUNDEF(VT);
7422 int BitLen = (Len * VT.getScalarSizeInBits()) & 0x3f;
7423 int BitIdx = (Idx * VT.getScalarSizeInBits()) & 0x3f;
7424 return DAG.getNode(X86ISD::INSERTQI, DL, VT, Base, Insert,
7425 DAG.getConstant(BitLen, DL, MVT::i8),
7426 DAG.getConstant(BitIdx, DL, MVT::i8));
7433 if (SDValue InsertQ = LowerAsInsertQ())
7439 /// \brief Lower a vector shuffle as a zero or any extension.
7441 /// Given a specific number of elements, element bit width, and extension
7442 /// stride, produce either a zero or any extension based on the available
7443 /// features of the subtarget. The extended elements are consecutive and
7444 /// begin and can start from an offseted element index in the input; to
7445 /// avoid excess shuffling the offset must either being in the bottom lane
7446 /// or at the start of a higher lane. All extended elements must be from
7448 static SDValue lowerVectorShuffleAsSpecificZeroOrAnyExtend(
7449 SDLoc DL, MVT VT, int Scale, int Offset, bool AnyExt, SDValue InputV,
7450 ArrayRef<int> Mask, const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7451 assert(Scale > 1 && "Need a scale to extend.");
7452 int EltBits = VT.getScalarSizeInBits();
7453 int NumElements = VT.getVectorNumElements();
7454 int NumEltsPerLane = 128 / EltBits;
7455 int OffsetLane = Offset / NumEltsPerLane;
7456 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
7457 "Only 8, 16, and 32 bit elements can be extended.");
7458 assert(Scale * EltBits <= 64 && "Cannot zero extend past 64 bits.");
7459 assert(0 <= Offset && "Extension offset must be positive.");
7460 assert((Offset < NumEltsPerLane || Offset % NumEltsPerLane == 0) &&
7461 "Extension offset must be in the first lane or start an upper lane.");
7463 // Check that an index is in same lane as the base offset.
7464 auto SafeOffset = [&](int Idx) {
7465 return OffsetLane == (Idx / NumEltsPerLane);
7468 // Shift along an input so that the offset base moves to the first element.
7469 auto ShuffleOffset = [&](SDValue V) {
7473 SmallVector<int, 8> ShMask((unsigned)NumElements, -1);
7474 for (int i = 0; i * Scale < NumElements; ++i) {
7475 int SrcIdx = i + Offset;
7476 ShMask[i] = SafeOffset(SrcIdx) ? SrcIdx : -1;
7478 return DAG.getVectorShuffle(VT, DL, V, DAG.getUNDEF(VT), ShMask);
7481 // Found a valid zext mask! Try various lowering strategies based on the
7482 // input type and available ISA extensions.
7483 if (Subtarget->hasSSE41()) {
7484 // Not worth offseting 128-bit vectors if scale == 2, a pattern using
7485 // PUNPCK will catch this in a later shuffle match.
7486 if (Offset && Scale == 2 && VT.is128BitVector())
7488 MVT ExtVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits * Scale),
7489 NumElements / Scale);
7490 InputV = DAG.getNode(X86ISD::VZEXT, DL, ExtVT, ShuffleOffset(InputV));
7491 return DAG.getBitcast(VT, InputV);
7494 assert(VT.is128BitVector() && "Only 128-bit vectors can be extended.");
7496 // For any extends we can cheat for larger element sizes and use shuffle
7497 // instructions that can fold with a load and/or copy.
7498 if (AnyExt && EltBits == 32) {
7499 int PSHUFDMask[4] = {Offset, -1, SafeOffset(Offset + 1) ? Offset + 1 : -1,
7501 return DAG.getBitcast(
7502 VT, DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
7503 DAG.getBitcast(MVT::v4i32, InputV),
7504 getV4X86ShuffleImm8ForMask(PSHUFDMask, DL, DAG)));
7506 if (AnyExt && EltBits == 16 && Scale > 2) {
7507 int PSHUFDMask[4] = {Offset / 2, -1,
7508 SafeOffset(Offset + 1) ? (Offset + 1) / 2 : -1, -1};
7509 InputV = DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
7510 DAG.getBitcast(MVT::v4i32, InputV),
7511 getV4X86ShuffleImm8ForMask(PSHUFDMask, DL, DAG));
7512 int PSHUFWMask[4] = {1, -1, -1, -1};
7513 unsigned OddEvenOp = (Offset & 1 ? X86ISD::PSHUFLW : X86ISD::PSHUFHW);
7514 return DAG.getBitcast(
7515 VT, DAG.getNode(OddEvenOp, DL, MVT::v8i16,
7516 DAG.getBitcast(MVT::v8i16, InputV),
7517 getV4X86ShuffleImm8ForMask(PSHUFWMask, DL, DAG)));
7520 // The SSE4A EXTRQ instruction can efficiently extend the first 2 lanes
7522 if ((Scale * EltBits) == 64 && EltBits < 32 && Subtarget->hasSSE4A()) {
7523 assert(NumElements == (int)Mask.size() && "Unexpected shuffle mask size!");
7524 assert(VT.is128BitVector() && "Unexpected vector width!");
7526 int LoIdx = Offset * EltBits;
7527 SDValue Lo = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64,
7528 DAG.getNode(X86ISD::EXTRQI, DL, VT, InputV,
7529 DAG.getConstant(EltBits, DL, MVT::i8),
7530 DAG.getConstant(LoIdx, DL, MVT::i8)));
7532 if (isUndefInRange(Mask, NumElements / 2, NumElements / 2) ||
7533 !SafeOffset(Offset + 1))
7534 return DAG.getNode(ISD::BITCAST, DL, VT, Lo);
7536 int HiIdx = (Offset + 1) * EltBits;
7537 SDValue Hi = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64,
7538 DAG.getNode(X86ISD::EXTRQI, DL, VT, InputV,
7539 DAG.getConstant(EltBits, DL, MVT::i8),
7540 DAG.getConstant(HiIdx, DL, MVT::i8)));
7541 return DAG.getNode(ISD::BITCAST, DL, VT,
7542 DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2i64, Lo, Hi));
7545 // If this would require more than 2 unpack instructions to expand, use
7546 // pshufb when available. We can only use more than 2 unpack instructions
7547 // when zero extending i8 elements which also makes it easier to use pshufb.
7548 if (Scale > 4 && EltBits == 8 && Subtarget->hasSSSE3()) {
7549 assert(NumElements == 16 && "Unexpected byte vector width!");
7550 SDValue PSHUFBMask[16];
7551 for (int i = 0; i < 16; ++i) {
7552 int Idx = Offset + (i / Scale);
7553 PSHUFBMask[i] = DAG.getConstant(
7554 (i % Scale == 0 && SafeOffset(Idx)) ? Idx : 0x80, DL, MVT::i8);
7556 InputV = DAG.getBitcast(MVT::v16i8, InputV);
7557 return DAG.getBitcast(VT,
7558 DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, InputV,
7559 DAG.getNode(ISD::BUILD_VECTOR, DL,
7560 MVT::v16i8, PSHUFBMask)));
7563 // If we are extending from an offset, ensure we start on a boundary that
7564 // we can unpack from.
7565 int AlignToUnpack = Offset % (NumElements / Scale);
7566 if (AlignToUnpack) {
7567 SmallVector<int, 8> ShMask((unsigned)NumElements, -1);
7568 for (int i = AlignToUnpack; i < NumElements; ++i)
7569 ShMask[i - AlignToUnpack] = i;
7570 InputV = DAG.getVectorShuffle(VT, DL, InputV, DAG.getUNDEF(VT), ShMask);
7571 Offset -= AlignToUnpack;
7574 // Otherwise emit a sequence of unpacks.
7576 unsigned UnpackLoHi = X86ISD::UNPCKL;
7577 if (Offset >= (NumElements / 2)) {
7578 UnpackLoHi = X86ISD::UNPCKH;
7579 Offset -= (NumElements / 2);
7582 MVT InputVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits), NumElements);
7583 SDValue Ext = AnyExt ? DAG.getUNDEF(InputVT)
7584 : getZeroVector(InputVT, Subtarget, DAG, DL);
7585 InputV = DAG.getBitcast(InputVT, InputV);
7586 InputV = DAG.getNode(UnpackLoHi, DL, InputVT, InputV, Ext);
7590 } while (Scale > 1);
7591 return DAG.getBitcast(VT, InputV);
7594 /// \brief Try to lower a vector shuffle as a zero extension on any microarch.
7596 /// This routine will try to do everything in its power to cleverly lower
7597 /// a shuffle which happens to match the pattern of a zero extend. It doesn't
7598 /// check for the profitability of this lowering, it tries to aggressively
7599 /// match this pattern. It will use all of the micro-architectural details it
7600 /// can to emit an efficient lowering. It handles both blends with all-zero
7601 /// inputs to explicitly zero-extend and undef-lanes (sometimes undef due to
7602 /// masking out later).
7604 /// The reason we have dedicated lowering for zext-style shuffles is that they
7605 /// are both incredibly common and often quite performance sensitive.
7606 static SDValue lowerVectorShuffleAsZeroOrAnyExtend(
7607 SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
7608 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7609 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7611 int Bits = VT.getSizeInBits();
7612 int NumLanes = Bits / 128;
7613 int NumElements = VT.getVectorNumElements();
7614 int NumEltsPerLane = NumElements / NumLanes;
7615 assert(VT.getScalarSizeInBits() <= 32 &&
7616 "Exceeds 32-bit integer zero extension limit");
7617 assert((int)Mask.size() == NumElements && "Unexpected shuffle mask size");
7619 // Define a helper function to check a particular ext-scale and lower to it if
7621 auto Lower = [&](int Scale) -> SDValue {
7626 for (int i = 0; i < NumElements; ++i) {
7629 continue; // Valid anywhere but doesn't tell us anything.
7630 if (i % Scale != 0) {
7631 // Each of the extended elements need to be zeroable.
7635 // We no longer are in the anyext case.
7640 // Each of the base elements needs to be consecutive indices into the
7641 // same input vector.
7642 SDValue V = M < NumElements ? V1 : V2;
7643 M = M % NumElements;
7646 Offset = M - (i / Scale);
7647 } else if (InputV != V)
7648 return SDValue(); // Flip-flopping inputs.
7650 // Offset must start in the lowest 128-bit lane or at the start of an
7652 // FIXME: Is it ever worth allowing a negative base offset?
7653 if (!((0 <= Offset && Offset < NumEltsPerLane) ||
7654 (Offset % NumEltsPerLane) == 0))
7657 // If we are offsetting, all referenced entries must come from the same
7659 if (Offset && (Offset / NumEltsPerLane) != (M / NumEltsPerLane))
7662 if ((M % NumElements) != (Offset + (i / Scale)))
7663 return SDValue(); // Non-consecutive strided elements.
7667 // If we fail to find an input, we have a zero-shuffle which should always
7668 // have already been handled.
7669 // FIXME: Maybe handle this here in case during blending we end up with one?
7673 // If we are offsetting, don't extend if we only match a single input, we
7674 // can always do better by using a basic PSHUF or PUNPCK.
7675 if (Offset != 0 && Matches < 2)
7678 return lowerVectorShuffleAsSpecificZeroOrAnyExtend(
7679 DL, VT, Scale, Offset, AnyExt, InputV, Mask, Subtarget, DAG);
7682 // The widest scale possible for extending is to a 64-bit integer.
7683 assert(Bits % 64 == 0 &&
7684 "The number of bits in a vector must be divisible by 64 on x86!");
7685 int NumExtElements = Bits / 64;
7687 // Each iteration, try extending the elements half as much, but into twice as
7689 for (; NumExtElements < NumElements; NumExtElements *= 2) {
7690 assert(NumElements % NumExtElements == 0 &&
7691 "The input vector size must be divisible by the extended size.");
7692 if (SDValue V = Lower(NumElements / NumExtElements))
7696 // General extends failed, but 128-bit vectors may be able to use MOVQ.
7700 // Returns one of the source operands if the shuffle can be reduced to a
7701 // MOVQ, copying the lower 64-bits and zero-extending to the upper 64-bits.
7702 auto CanZExtLowHalf = [&]() {
7703 for (int i = NumElements / 2; i != NumElements; ++i)
7706 if (isSequentialOrUndefInRange(Mask, 0, NumElements / 2, 0))
7708 if (isSequentialOrUndefInRange(Mask, 0, NumElements / 2, NumElements))
7713 if (SDValue V = CanZExtLowHalf()) {
7714 V = DAG.getBitcast(MVT::v2i64, V);
7715 V = DAG.getNode(X86ISD::VZEXT_MOVL, DL, MVT::v2i64, V);
7716 return DAG.getBitcast(VT, V);
7719 // No viable ext lowering found.
7723 /// \brief Try to get a scalar value for a specific element of a vector.
7725 /// Looks through BUILD_VECTOR and SCALAR_TO_VECTOR nodes to find a scalar.
7726 static SDValue getScalarValueForVectorElement(SDValue V, int Idx,
7727 SelectionDAG &DAG) {
7728 MVT VT = V.getSimpleValueType();
7729 MVT EltVT = VT.getVectorElementType();
7730 while (V.getOpcode() == ISD::BITCAST)
7731 V = V.getOperand(0);
7732 // If the bitcasts shift the element size, we can't extract an equivalent
7734 MVT NewVT = V.getSimpleValueType();
7735 if (!NewVT.isVector() || NewVT.getScalarSizeInBits() != VT.getScalarSizeInBits())
7738 if (V.getOpcode() == ISD::BUILD_VECTOR ||
7739 (Idx == 0 && V.getOpcode() == ISD::SCALAR_TO_VECTOR)) {
7740 // Ensure the scalar operand is the same size as the destination.
7741 // FIXME: Add support for scalar truncation where possible.
7742 SDValue S = V.getOperand(Idx);
7743 if (EltVT.getSizeInBits() == S.getSimpleValueType().getSizeInBits())
7744 return DAG.getNode(ISD::BITCAST, SDLoc(V), EltVT, S);
7750 /// \brief Helper to test for a load that can be folded with x86 shuffles.
7752 /// This is particularly important because the set of instructions varies
7753 /// significantly based on whether the operand is a load or not.
7754 static bool isShuffleFoldableLoad(SDValue V) {
7755 while (V.getOpcode() == ISD::BITCAST)
7756 V = V.getOperand(0);
7758 return ISD::isNON_EXTLoad(V.getNode());
7761 /// \brief Try to lower insertion of a single element into a zero vector.
7763 /// This is a common pattern that we have especially efficient patterns to lower
7764 /// across all subtarget feature sets.
7765 static SDValue lowerVectorShuffleAsElementInsertion(
7766 SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
7767 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7768 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7770 MVT EltVT = VT.getVectorElementType();
7772 int V2Index = std::find_if(Mask.begin(), Mask.end(),
7773 [&Mask](int M) { return M >= (int)Mask.size(); }) -
7775 bool IsV1Zeroable = true;
7776 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7777 if (i != V2Index && !Zeroable[i]) {
7778 IsV1Zeroable = false;
7782 // Check for a single input from a SCALAR_TO_VECTOR node.
7783 // FIXME: All of this should be canonicalized into INSERT_VECTOR_ELT and
7784 // all the smarts here sunk into that routine. However, the current
7785 // lowering of BUILD_VECTOR makes that nearly impossible until the old
7786 // vector shuffle lowering is dead.
7787 SDValue V2S = getScalarValueForVectorElement(V2, Mask[V2Index] - Mask.size(),
7789 if (V2S && DAG.getTargetLoweringInfo().isTypeLegal(V2S.getValueType())) {
7790 // We need to zext the scalar if it is smaller than an i32.
7791 V2S = DAG.getBitcast(EltVT, V2S);
7792 if (EltVT == MVT::i8 || EltVT == MVT::i16) {
7793 // Using zext to expand a narrow element won't work for non-zero
7798 // Zero-extend directly to i32.
7800 V2S = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, V2S);
7802 V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, ExtVT, V2S);
7803 } else if (Mask[V2Index] != (int)Mask.size() || EltVT == MVT::i8 ||
7804 EltVT == MVT::i16) {
7805 // Either not inserting from the low element of the input or the input
7806 // element size is too small to use VZEXT_MOVL to clear the high bits.
7810 if (!IsV1Zeroable) {
7811 // If V1 can't be treated as a zero vector we have fewer options to lower
7812 // this. We can't support integer vectors or non-zero targets cheaply, and
7813 // the V1 elements can't be permuted in any way.
7814 assert(VT == ExtVT && "Cannot change extended type when non-zeroable!");
7815 if (!VT.isFloatingPoint() || V2Index != 0)
7817 SmallVector<int, 8> V1Mask(Mask.begin(), Mask.end());
7818 V1Mask[V2Index] = -1;
7819 if (!isNoopShuffleMask(V1Mask))
7821 // This is essentially a special case blend operation, but if we have
7822 // general purpose blend operations, they are always faster. Bail and let
7823 // the rest of the lowering handle these as blends.
7824 if (Subtarget->hasSSE41())
7827 // Otherwise, use MOVSD or MOVSS.
7828 assert((EltVT == MVT::f32 || EltVT == MVT::f64) &&
7829 "Only two types of floating point element types to handle!");
7830 return DAG.getNode(EltVT == MVT::f32 ? X86ISD::MOVSS : X86ISD::MOVSD, DL,
7834 // This lowering only works for the low element with floating point vectors.
7835 if (VT.isFloatingPoint() && V2Index != 0)
7838 V2 = DAG.getNode(X86ISD::VZEXT_MOVL, DL, ExtVT, V2);
7840 V2 = DAG.getBitcast(VT, V2);
7843 // If we have 4 or fewer lanes we can cheaply shuffle the element into
7844 // the desired position. Otherwise it is more efficient to do a vector
7845 // shift left. We know that we can do a vector shift left because all
7846 // the inputs are zero.
7847 if (VT.isFloatingPoint() || VT.getVectorNumElements() <= 4) {
7848 SmallVector<int, 4> V2Shuffle(Mask.size(), 1);
7849 V2Shuffle[V2Index] = 0;
7850 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Shuffle);
7852 V2 = DAG.getBitcast(MVT::v2i64, V2);
7854 X86ISD::VSHLDQ, DL, MVT::v2i64, V2,
7855 DAG.getConstant(V2Index * EltVT.getSizeInBits() / 8, DL,
7856 DAG.getTargetLoweringInfo().getScalarShiftAmountTy(
7857 DAG.getDataLayout(), VT)));
7858 V2 = DAG.getBitcast(VT, V2);
7864 /// \brief Try to lower broadcast of a single - truncated - integer element,
7865 /// coming from a scalar_to_vector/build_vector node \p V0 with larger elements.
7867 /// This assumes we have AVX2.
7868 static SDValue lowerVectorShuffleAsTruncBroadcast(SDLoc DL, MVT VT, SDValue V0,
7870 const X86Subtarget *Subtarget,
7871 SelectionDAG &DAG) {
7872 assert(Subtarget->hasAVX2() &&
7873 "We can only lower integer broadcasts with AVX2!");
7875 EVT EltVT = VT.getVectorElementType();
7876 EVT V0VT = V0.getValueType();
7878 assert(VT.isInteger() && "Unexpected non-integer trunc broadcast!");
7879 assert(V0VT.isVector() && "Unexpected non-vector vector-sized value!");
7881 EVT V0EltVT = V0VT.getVectorElementType();
7882 if (!V0EltVT.isInteger())
7885 const unsigned EltSize = EltVT.getSizeInBits();
7886 const unsigned V0EltSize = V0EltVT.getSizeInBits();
7888 // This is only a truncation if the original element type is larger.
7889 if (V0EltSize <= EltSize)
7892 assert(((V0EltSize % EltSize) == 0) &&
7893 "Scalar type sizes must all be powers of 2 on x86!");
7895 const unsigned V0Opc = V0.getOpcode();
7896 const unsigned Scale = V0EltSize / EltSize;
7897 const unsigned V0BroadcastIdx = BroadcastIdx / Scale;
7899 if ((V0Opc != ISD::SCALAR_TO_VECTOR || V0BroadcastIdx != 0) &&
7900 V0Opc != ISD::BUILD_VECTOR)
7903 SDValue Scalar = V0.getOperand(V0BroadcastIdx);
7905 // If we're extracting non-least-significant bits, shift so we can truncate.
7906 // Hopefully, we can fold away the trunc/srl/load into the broadcast.
7907 // Even if we can't (and !isShuffleFoldableLoad(Scalar)), prefer
7908 // vpbroadcast+vmovd+shr to vpshufb(m)+vmovd.
7909 if (const int OffsetIdx = BroadcastIdx % Scale)
7910 Scalar = DAG.getNode(ISD::SRL, DL, Scalar.getValueType(), Scalar,
7911 DAG.getConstant(OffsetIdx * EltSize, DL, Scalar.getValueType()));
7913 return DAG.getNode(X86ISD::VBROADCAST, DL, VT,
7914 DAG.getNode(ISD::TRUNCATE, DL, EltVT, Scalar));
7917 /// \brief Try to lower broadcast of a single element.
7919 /// For convenience, this code also bundles all of the subtarget feature set
7920 /// filtering. While a little annoying to re-dispatch on type here, there isn't
7921 /// a convenient way to factor it out.
7922 static SDValue lowerVectorShuffleAsBroadcast(SDLoc DL, MVT VT, SDValue V,
7924 const X86Subtarget *Subtarget,
7925 SelectionDAG &DAG) {
7926 if (!Subtarget->hasAVX())
7928 if (VT.isInteger() && !Subtarget->hasAVX2())
7931 // Check that the mask is a broadcast.
7932 int BroadcastIdx = -1;
7934 if (M >= 0 && BroadcastIdx == -1)
7936 else if (M >= 0 && M != BroadcastIdx)
7939 assert(BroadcastIdx < (int)Mask.size() && "We only expect to be called with "
7940 "a sorted mask where the broadcast "
7943 // Go up the chain of (vector) values to find a scalar load that we can
7944 // combine with the broadcast.
7946 switch (V.getOpcode()) {
7947 case ISD::CONCAT_VECTORS: {
7948 int OperandSize = Mask.size() / V.getNumOperands();
7949 V = V.getOperand(BroadcastIdx / OperandSize);
7950 BroadcastIdx %= OperandSize;
7954 case ISD::INSERT_SUBVECTOR: {
7955 SDValue VOuter = V.getOperand(0), VInner = V.getOperand(1);
7956 auto ConstantIdx = dyn_cast<ConstantSDNode>(V.getOperand(2));
7960 int BeginIdx = (int)ConstantIdx->getZExtValue();
7962 BeginIdx + (int)VInner.getSimpleValueType().getVectorNumElements();
7963 if (BroadcastIdx >= BeginIdx && BroadcastIdx < EndIdx) {
7964 BroadcastIdx -= BeginIdx;
7975 // Check if this is a broadcast of a scalar. We special case lowering
7976 // for scalars so that we can more effectively fold with loads.
7977 // First, look through bitcast: if the original value has a larger element
7978 // type than the shuffle, the broadcast element is in essence truncated.
7979 // Make that explicit to ease folding.
7980 if (V.getOpcode() == ISD::BITCAST && VT.isInteger())
7981 if (SDValue TruncBroadcast = lowerVectorShuffleAsTruncBroadcast(
7982 DL, VT, V.getOperand(0), BroadcastIdx, Subtarget, DAG))
7983 return TruncBroadcast;
7985 // Also check the simpler case, where we can directly reuse the scalar.
7986 if (V.getOpcode() == ISD::BUILD_VECTOR ||
7987 (V.getOpcode() == ISD::SCALAR_TO_VECTOR && BroadcastIdx == 0)) {
7988 V = V.getOperand(BroadcastIdx);
7990 // If the scalar isn't a load, we can't broadcast from it in AVX1.
7991 // Only AVX2 has register broadcasts.
7992 if (!Subtarget->hasAVX2() && !isShuffleFoldableLoad(V))
7994 } else if (BroadcastIdx != 0 || !Subtarget->hasAVX2()) {
7995 // We can't broadcast from a vector register without AVX2, and we can only
7996 // broadcast from the zero-element of a vector register.
8000 return DAG.getNode(X86ISD::VBROADCAST, DL, VT, V);
8003 // Check for whether we can use INSERTPS to perform the shuffle. We only use
8004 // INSERTPS when the V1 elements are already in the correct locations
8005 // because otherwise we can just always use two SHUFPS instructions which
8006 // are much smaller to encode than a SHUFPS and an INSERTPS. We can also
8007 // perform INSERTPS if a single V1 element is out of place and all V2
8008 // elements are zeroable.
8009 static SDValue lowerVectorShuffleAsInsertPS(SDValue Op, SDValue V1, SDValue V2,
8011 SelectionDAG &DAG) {
8012 assert(Op.getSimpleValueType() == MVT::v4f32 && "Bad shuffle type!");
8013 assert(V1.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
8014 assert(V2.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
8015 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
8017 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
8020 int V1DstIndex = -1;
8021 int V2DstIndex = -1;
8022 bool V1UsedInPlace = false;
8024 for (int i = 0; i < 4; ++i) {
8025 // Synthesize a zero mask from the zeroable elements (includes undefs).
8031 // Flag if we use any V1 inputs in place.
8033 V1UsedInPlace = true;
8037 // We can only insert a single non-zeroable element.
8038 if (V1DstIndex != -1 || V2DstIndex != -1)
8042 // V1 input out of place for insertion.
8045 // V2 input for insertion.
8050 // Don't bother if we have no (non-zeroable) element for insertion.
8051 if (V1DstIndex == -1 && V2DstIndex == -1)
8054 // Determine element insertion src/dst indices. The src index is from the
8055 // start of the inserted vector, not the start of the concatenated vector.
8056 unsigned V2SrcIndex = 0;
8057 if (V1DstIndex != -1) {
8058 // If we have a V1 input out of place, we use V1 as the V2 element insertion
8059 // and don't use the original V2 at all.
8060 V2SrcIndex = Mask[V1DstIndex];
8061 V2DstIndex = V1DstIndex;
8064 V2SrcIndex = Mask[V2DstIndex] - 4;
8067 // If no V1 inputs are used in place, then the result is created only from
8068 // the zero mask and the V2 insertion - so remove V1 dependency.
8070 V1 = DAG.getUNDEF(MVT::v4f32);
8072 unsigned InsertPSMask = V2SrcIndex << 6 | V2DstIndex << 4 | ZMask;
8073 assert((InsertPSMask & ~0xFFu) == 0 && "Invalid mask!");
8075 // Insert the V2 element into the desired position.
8077 return DAG.getNode(X86ISD::INSERTPS, DL, MVT::v4f32, V1, V2,
8078 DAG.getConstant(InsertPSMask, DL, MVT::i8));
8081 /// \brief Try to lower a shuffle as a permute of the inputs followed by an
8082 /// UNPCK instruction.
8084 /// This specifically targets cases where we end up with alternating between
8085 /// the two inputs, and so can permute them into something that feeds a single
8086 /// UNPCK instruction. Note that this routine only targets integer vectors
8087 /// because for floating point vectors we have a generalized SHUFPS lowering
8088 /// strategy that handles everything that doesn't *exactly* match an unpack,
8089 /// making this clever lowering unnecessary.
8090 static SDValue lowerVectorShuffleAsPermuteAndUnpack(SDLoc DL, MVT VT,
8091 SDValue V1, SDValue V2,
8093 SelectionDAG &DAG) {
8094 assert(!VT.isFloatingPoint() &&
8095 "This routine only supports integer vectors.");
8096 assert(!isSingleInputShuffleMask(Mask) &&
8097 "This routine should only be used when blending two inputs.");
8098 assert(Mask.size() >= 2 && "Single element masks are invalid.");
8100 int Size = Mask.size();
8102 int NumLoInputs = std::count_if(Mask.begin(), Mask.end(), [Size](int M) {
8103 return M >= 0 && M % Size < Size / 2;
8105 int NumHiInputs = std::count_if(
8106 Mask.begin(), Mask.end(), [Size](int M) { return M % Size >= Size / 2; });
8108 bool UnpackLo = NumLoInputs >= NumHiInputs;
8110 auto TryUnpack = [&](MVT UnpackVT, int Scale) {
8111 SmallVector<int, 32> V1Mask(Mask.size(), -1);
8112 SmallVector<int, 32> V2Mask(Mask.size(), -1);
8114 for (int i = 0; i < Size; ++i) {
8118 // Each element of the unpack contains Scale elements from this mask.
8119 int UnpackIdx = i / Scale;
8121 // We only handle the case where V1 feeds the first slots of the unpack.
8122 // We rely on canonicalization to ensure this is the case.
8123 if ((UnpackIdx % 2 == 0) != (Mask[i] < Size))
8126 // Setup the mask for this input. The indexing is tricky as we have to
8127 // handle the unpack stride.
8128 SmallVectorImpl<int> &VMask = (UnpackIdx % 2 == 0) ? V1Mask : V2Mask;
8129 VMask[(UnpackIdx / 2) * Scale + i % Scale + (UnpackLo ? 0 : Size / 2)] =
8133 // If we will have to shuffle both inputs to use the unpack, check whether
8134 // we can just unpack first and shuffle the result. If so, skip this unpack.
8135 if ((NumLoInputs == 0 || NumHiInputs == 0) && !isNoopShuffleMask(V1Mask) &&
8136 !isNoopShuffleMask(V2Mask))
8139 // Shuffle the inputs into place.
8140 V1 = DAG.getVectorShuffle(VT, DL, V1, DAG.getUNDEF(VT), V1Mask);
8141 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Mask);
8143 // Cast the inputs to the type we will use to unpack them.
8144 V1 = DAG.getBitcast(UnpackVT, V1);
8145 V2 = DAG.getBitcast(UnpackVT, V2);
8147 // Unpack the inputs and cast the result back to the desired type.
8148 return DAG.getBitcast(
8149 VT, DAG.getNode(UnpackLo ? X86ISD::UNPCKL : X86ISD::UNPCKH, DL,
8153 // We try each unpack from the largest to the smallest to try and find one
8154 // that fits this mask.
8155 int OrigNumElements = VT.getVectorNumElements();
8156 int OrigScalarSize = VT.getScalarSizeInBits();
8157 for (int ScalarSize = 64; ScalarSize >= OrigScalarSize; ScalarSize /= 2) {
8158 int Scale = ScalarSize / OrigScalarSize;
8159 int NumElements = OrigNumElements / Scale;
8160 MVT UnpackVT = MVT::getVectorVT(MVT::getIntegerVT(ScalarSize), NumElements);
8161 if (SDValue Unpack = TryUnpack(UnpackVT, Scale))
8165 // If none of the unpack-rooted lowerings worked (or were profitable) try an
8167 if (NumLoInputs == 0 || NumHiInputs == 0) {
8168 assert((NumLoInputs > 0 || NumHiInputs > 0) &&
8169 "We have to have *some* inputs!");
8170 int HalfOffset = NumLoInputs == 0 ? Size / 2 : 0;
8172 // FIXME: We could consider the total complexity of the permute of each
8173 // possible unpacking. Or at the least we should consider how many
8174 // half-crossings are created.
8175 // FIXME: We could consider commuting the unpacks.
8177 SmallVector<int, 32> PermMask;
8178 PermMask.assign(Size, -1);
8179 for (int i = 0; i < Size; ++i) {
8183 assert(Mask[i] % Size >= HalfOffset && "Found input from wrong half!");
8186 2 * ((Mask[i] % Size) - HalfOffset) + (Mask[i] < Size ? 0 : 1);
8188 return DAG.getVectorShuffle(
8189 VT, DL, DAG.getNode(NumLoInputs == 0 ? X86ISD::UNPCKH : X86ISD::UNPCKL,
8191 DAG.getUNDEF(VT), PermMask);
8197 /// \brief Handle lowering of 2-lane 64-bit floating point shuffles.
8199 /// This is the basis function for the 2-lane 64-bit shuffles as we have full
8200 /// support for floating point shuffles but not integer shuffles. These
8201 /// instructions will incur a domain crossing penalty on some chips though so
8202 /// it is better to avoid lowering through this for integer vectors where
8204 static SDValue lowerV2F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8205 const X86Subtarget *Subtarget,
8206 SelectionDAG &DAG) {
8208 assert(Op.getSimpleValueType() == MVT::v2f64 && "Bad shuffle type!");
8209 assert(V1.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
8210 assert(V2.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
8211 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8212 ArrayRef<int> Mask = SVOp->getMask();
8213 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
8215 if (isSingleInputShuffleMask(Mask)) {
8216 // Use low duplicate instructions for masks that match their pattern.
8217 if (Subtarget->hasSSE3())
8218 if (isShuffleEquivalent(V1, V2, Mask, {0, 0}))
8219 return DAG.getNode(X86ISD::MOVDDUP, DL, MVT::v2f64, V1);
8221 // Straight shuffle of a single input vector. Simulate this by using the
8222 // single input as both of the "inputs" to this instruction..
8223 unsigned SHUFPDMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1);
8225 if (Subtarget->hasAVX()) {
8226 // If we have AVX, we can use VPERMILPS which will allow folding a load
8227 // into the shuffle.
8228 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v2f64, V1,
8229 DAG.getConstant(SHUFPDMask, DL, MVT::i8));
8232 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v2f64, V1, V1,
8233 DAG.getConstant(SHUFPDMask, DL, MVT::i8));
8235 assert(Mask[0] >= 0 && Mask[0] < 2 && "Non-canonicalized blend!");
8236 assert(Mask[1] >= 2 && "Non-canonicalized blend!");
8238 // If we have a single input, insert that into V1 if we can do so cheaply.
8239 if ((Mask[0] >= 2) + (Mask[1] >= 2) == 1) {
8240 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8241 DL, MVT::v2f64, V1, V2, Mask, Subtarget, DAG))
8243 // Try inverting the insertion since for v2 masks it is easy to do and we
8244 // can't reliably sort the mask one way or the other.
8245 int InverseMask[2] = {Mask[0] < 0 ? -1 : (Mask[0] ^ 2),
8246 Mask[1] < 0 ? -1 : (Mask[1] ^ 2)};
8247 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8248 DL, MVT::v2f64, V2, V1, InverseMask, Subtarget, DAG))
8252 // Try to use one of the special instruction patterns to handle two common
8253 // blend patterns if a zero-blend above didn't work.
8254 if (isShuffleEquivalent(V1, V2, Mask, {0, 3}) ||
8255 isShuffleEquivalent(V1, V2, Mask, {1, 3}))
8256 if (SDValue V1S = getScalarValueForVectorElement(V1, Mask[0], DAG))
8257 // We can either use a special instruction to load over the low double or
8258 // to move just the low double.
8260 isShuffleFoldableLoad(V1S) ? X86ISD::MOVLPD : X86ISD::MOVSD,
8262 DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2f64, V1S));
8264 if (Subtarget->hasSSE41())
8265 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v2f64, V1, V2, Mask,
8269 // Use dedicated unpack instructions for masks that match their pattern.
8271 lowerVectorShuffleWithUNPCK(DL, MVT::v2f64, Mask, V1, V2, DAG))
8274 unsigned SHUFPDMask = (Mask[0] == 1) | (((Mask[1] - 2) == 1) << 1);
8275 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v2f64, V1, V2,
8276 DAG.getConstant(SHUFPDMask, DL, MVT::i8));
8279 /// \brief Handle lowering of 2-lane 64-bit integer shuffles.
8281 /// Tries to lower a 2-lane 64-bit shuffle using shuffle operations provided by
8282 /// the integer unit to minimize domain crossing penalties. However, for blends
8283 /// it falls back to the floating point shuffle operation with appropriate bit
8285 static SDValue lowerV2I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8286 const X86Subtarget *Subtarget,
8287 SelectionDAG &DAG) {
8289 assert(Op.getSimpleValueType() == MVT::v2i64 && "Bad shuffle type!");
8290 assert(V1.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
8291 assert(V2.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
8292 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8293 ArrayRef<int> Mask = SVOp->getMask();
8294 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
8296 if (isSingleInputShuffleMask(Mask)) {
8297 // Check for being able to broadcast a single element.
8298 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v2i64, V1,
8299 Mask, Subtarget, DAG))
8302 // Straight shuffle of a single input vector. For everything from SSE2
8303 // onward this has a single fast instruction with no scary immediates.
8304 // We have to map the mask as it is actually a v4i32 shuffle instruction.
8305 V1 = DAG.getBitcast(MVT::v4i32, V1);
8306 int WidenedMask[4] = {
8307 std::max(Mask[0], 0) * 2, std::max(Mask[0], 0) * 2 + 1,
8308 std::max(Mask[1], 0) * 2, std::max(Mask[1], 0) * 2 + 1};
8309 return DAG.getBitcast(
8311 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V1,
8312 getV4X86ShuffleImm8ForMask(WidenedMask, DL, DAG)));
8314 assert(Mask[0] != -1 && "No undef lanes in multi-input v2 shuffles!");
8315 assert(Mask[1] != -1 && "No undef lanes in multi-input v2 shuffles!");
8316 assert(Mask[0] < 2 && "We sort V1 to be the first input.");
8317 assert(Mask[1] >= 2 && "We sort V2 to be the second input.");
8319 // If we have a blend of two PACKUS operations an the blend aligns with the
8320 // low and half halves, we can just merge the PACKUS operations. This is
8321 // particularly important as it lets us merge shuffles that this routine itself
8323 auto GetPackNode = [](SDValue V) {
8324 while (V.getOpcode() == ISD::BITCAST)
8325 V = V.getOperand(0);
8327 return V.getOpcode() == X86ISD::PACKUS ? V : SDValue();
8329 if (SDValue V1Pack = GetPackNode(V1))
8330 if (SDValue V2Pack = GetPackNode(V2))
8331 return DAG.getBitcast(MVT::v2i64,
8332 DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8,
8333 Mask[0] == 0 ? V1Pack.getOperand(0)
8334 : V1Pack.getOperand(1),
8335 Mask[1] == 2 ? V2Pack.getOperand(0)
8336 : V2Pack.getOperand(1)));
8338 // Try to use shift instructions.
8340 lowerVectorShuffleAsShift(DL, MVT::v2i64, V1, V2, Mask, DAG))
8343 // When loading a scalar and then shuffling it into a vector we can often do
8344 // the insertion cheaply.
8345 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8346 DL, MVT::v2i64, V1, V2, Mask, Subtarget, DAG))
8348 // Try inverting the insertion since for v2 masks it is easy to do and we
8349 // can't reliably sort the mask one way or the other.
8350 int InverseMask[2] = {Mask[0] ^ 2, Mask[1] ^ 2};
8351 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8352 DL, MVT::v2i64, V2, V1, InverseMask, Subtarget, DAG))
8355 // We have different paths for blend lowering, but they all must use the
8356 // *exact* same predicate.
8357 bool IsBlendSupported = Subtarget->hasSSE41();
8358 if (IsBlendSupported)
8359 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v2i64, V1, V2, Mask,
8363 // Use dedicated unpack instructions for masks that match their pattern.
8365 lowerVectorShuffleWithUNPCK(DL, MVT::v2i64, Mask, V1, V2, DAG))
8368 // Try to use byte rotation instructions.
8369 // Its more profitable for pre-SSSE3 to use shuffles/unpacks.
8370 if (Subtarget->hasSSSE3())
8371 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8372 DL, MVT::v2i64, V1, V2, Mask, Subtarget, DAG))
8375 // If we have direct support for blends, we should lower by decomposing into
8376 // a permute. That will be faster than the domain cross.
8377 if (IsBlendSupported)
8378 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v2i64, V1, V2,
8381 // We implement this with SHUFPD which is pretty lame because it will likely
8382 // incur 2 cycles of stall for integer vectors on Nehalem and older chips.
8383 // However, all the alternatives are still more cycles and newer chips don't
8384 // have this problem. It would be really nice if x86 had better shuffles here.
8385 V1 = DAG.getBitcast(MVT::v2f64, V1);
8386 V2 = DAG.getBitcast(MVT::v2f64, V2);
8387 return DAG.getBitcast(MVT::v2i64,
8388 DAG.getVectorShuffle(MVT::v2f64, DL, V1, V2, Mask));
8391 /// \brief Test whether this can be lowered with a single SHUFPS instruction.
8393 /// This is used to disable more specialized lowerings when the shufps lowering
8394 /// will happen to be efficient.
8395 static bool isSingleSHUFPSMask(ArrayRef<int> Mask) {
8396 // This routine only handles 128-bit shufps.
8397 assert(Mask.size() == 4 && "Unsupported mask size!");
8399 // To lower with a single SHUFPS we need to have the low half and high half
8400 // each requiring a single input.
8401 if (Mask[0] != -1 && Mask[1] != -1 && (Mask[0] < 4) != (Mask[1] < 4))
8403 if (Mask[2] != -1 && Mask[3] != -1 && (Mask[2] < 4) != (Mask[3] < 4))
8409 /// \brief Lower a vector shuffle using the SHUFPS instruction.
8411 /// This is a helper routine dedicated to lowering vector shuffles using SHUFPS.
8412 /// It makes no assumptions about whether this is the *best* lowering, it simply
8414 static SDValue lowerVectorShuffleWithSHUFPS(SDLoc DL, MVT VT,
8415 ArrayRef<int> Mask, SDValue V1,
8416 SDValue V2, SelectionDAG &DAG) {
8417 SDValue LowV = V1, HighV = V2;
8418 int NewMask[4] = {Mask[0], Mask[1], Mask[2], Mask[3]};
8421 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
8423 if (NumV2Elements == 1) {
8425 std::find_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; }) -
8428 // Compute the index adjacent to V2Index and in the same half by toggling
8430 int V2AdjIndex = V2Index ^ 1;
8432 if (Mask[V2AdjIndex] == -1) {
8433 // Handles all the cases where we have a single V2 element and an undef.
8434 // This will only ever happen in the high lanes because we commute the
8435 // vector otherwise.
8437 std::swap(LowV, HighV);
8438 NewMask[V2Index] -= 4;
8440 // Handle the case where the V2 element ends up adjacent to a V1 element.
8441 // To make this work, blend them together as the first step.
8442 int V1Index = V2AdjIndex;
8443 int BlendMask[4] = {Mask[V2Index] - 4, 0, Mask[V1Index], 0};
8444 V2 = DAG.getNode(X86ISD::SHUFP, DL, VT, V2, V1,
8445 getV4X86ShuffleImm8ForMask(BlendMask, DL, DAG));
8447 // Now proceed to reconstruct the final blend as we have the necessary
8448 // high or low half formed.
8455 NewMask[V1Index] = 2; // We put the V1 element in V2[2].
8456 NewMask[V2Index] = 0; // We shifted the V2 element into V2[0].
8458 } else if (NumV2Elements == 2) {
8459 if (Mask[0] < 4 && Mask[1] < 4) {
8460 // Handle the easy case where we have V1 in the low lanes and V2 in the
8464 } else if (Mask[2] < 4 && Mask[3] < 4) {
8465 // We also handle the reversed case because this utility may get called
8466 // when we detect a SHUFPS pattern but can't easily commute the shuffle to
8467 // arrange things in the right direction.
8473 // We have a mixture of V1 and V2 in both low and high lanes. Rather than
8474 // trying to place elements directly, just blend them and set up the final
8475 // shuffle to place them.
8477 // The first two blend mask elements are for V1, the second two are for
8479 int BlendMask[4] = {Mask[0] < 4 ? Mask[0] : Mask[1],
8480 Mask[2] < 4 ? Mask[2] : Mask[3],
8481 (Mask[0] >= 4 ? Mask[0] : Mask[1]) - 4,
8482 (Mask[2] >= 4 ? Mask[2] : Mask[3]) - 4};
8483 V1 = DAG.getNode(X86ISD::SHUFP, DL, VT, V1, V2,
8484 getV4X86ShuffleImm8ForMask(BlendMask, DL, DAG));
8486 // Now we do a normal shuffle of V1 by giving V1 as both operands to
8489 NewMask[0] = Mask[0] < 4 ? 0 : 2;
8490 NewMask[1] = Mask[0] < 4 ? 2 : 0;
8491 NewMask[2] = Mask[2] < 4 ? 1 : 3;
8492 NewMask[3] = Mask[2] < 4 ? 3 : 1;
8495 return DAG.getNode(X86ISD::SHUFP, DL, VT, LowV, HighV,
8496 getV4X86ShuffleImm8ForMask(NewMask, DL, DAG));
8499 /// \brief Lower 4-lane 32-bit floating point shuffles.
8501 /// Uses instructions exclusively from the floating point unit to minimize
8502 /// domain crossing penalties, as these are sufficient to implement all v4f32
8504 static SDValue lowerV4F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8505 const X86Subtarget *Subtarget,
8506 SelectionDAG &DAG) {
8508 assert(Op.getSimpleValueType() == MVT::v4f32 && "Bad shuffle type!");
8509 assert(V1.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
8510 assert(V2.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
8511 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8512 ArrayRef<int> Mask = SVOp->getMask();
8513 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
8516 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
8518 if (NumV2Elements == 0) {
8519 // Check for being able to broadcast a single element.
8520 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v4f32, V1,
8521 Mask, Subtarget, DAG))
8524 // Use even/odd duplicate instructions for masks that match their pattern.
8525 if (Subtarget->hasSSE3()) {
8526 if (isShuffleEquivalent(V1, V2, Mask, {0, 0, 2, 2}))
8527 return DAG.getNode(X86ISD::MOVSLDUP, DL, MVT::v4f32, V1);
8528 if (isShuffleEquivalent(V1, V2, Mask, {1, 1, 3, 3}))
8529 return DAG.getNode(X86ISD::MOVSHDUP, DL, MVT::v4f32, V1);
8532 if (Subtarget->hasAVX()) {
8533 // If we have AVX, we can use VPERMILPS which will allow folding a load
8534 // into the shuffle.
8535 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v4f32, V1,
8536 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
8539 // Otherwise, use a straight shuffle of a single input vector. We pass the
8540 // input vector to both operands to simulate this with a SHUFPS.
8541 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f32, V1, V1,
8542 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
8545 // There are special ways we can lower some single-element blends. However, we
8546 // have custom ways we can lower more complex single-element blends below that
8547 // we defer to if both this and BLENDPS fail to match, so restrict this to
8548 // when the V2 input is targeting element 0 of the mask -- that is the fast
8550 if (NumV2Elements == 1 && Mask[0] >= 4)
8551 if (SDValue V = lowerVectorShuffleAsElementInsertion(DL, MVT::v4f32, V1, V2,
8552 Mask, Subtarget, DAG))
8555 if (Subtarget->hasSSE41()) {
8556 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4f32, V1, V2, Mask,
8560 // Use INSERTPS if we can complete the shuffle efficiently.
8561 if (SDValue V = lowerVectorShuffleAsInsertPS(Op, V1, V2, Mask, DAG))
8564 if (!isSingleSHUFPSMask(Mask))
8565 if (SDValue BlendPerm = lowerVectorShuffleAsBlendAndPermute(
8566 DL, MVT::v4f32, V1, V2, Mask, DAG))
8570 // Use dedicated unpack instructions for masks that match their pattern.
8572 lowerVectorShuffleWithUNPCK(DL, MVT::v4f32, Mask, V1, V2, DAG))
8575 // Otherwise fall back to a SHUFPS lowering strategy.
8576 return lowerVectorShuffleWithSHUFPS(DL, MVT::v4f32, Mask, V1, V2, DAG);
8579 /// \brief Lower 4-lane i32 vector shuffles.
8581 /// We try to handle these with integer-domain shuffles where we can, but for
8582 /// blends we use the floating point domain blend instructions.
8583 static SDValue lowerV4I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8584 const X86Subtarget *Subtarget,
8585 SelectionDAG &DAG) {
8587 assert(Op.getSimpleValueType() == MVT::v4i32 && "Bad shuffle type!");
8588 assert(V1.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
8589 assert(V2.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
8590 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8591 ArrayRef<int> Mask = SVOp->getMask();
8592 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
8594 // Whenever we can lower this as a zext, that instruction is strictly faster
8595 // than any alternative. It also allows us to fold memory operands into the
8596 // shuffle in many cases.
8597 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v4i32, V1, V2,
8598 Mask, Subtarget, DAG))
8602 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
8604 if (NumV2Elements == 0) {
8605 // Check for being able to broadcast a single element.
8606 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v4i32, V1,
8607 Mask, Subtarget, DAG))
8610 // Straight shuffle of a single input vector. For everything from SSE2
8611 // onward this has a single fast instruction with no scary immediates.
8612 // We coerce the shuffle pattern to be compatible with UNPCK instructions
8613 // but we aren't actually going to use the UNPCK instruction because doing
8614 // so prevents folding a load into this instruction or making a copy.
8615 const int UnpackLoMask[] = {0, 0, 1, 1};
8616 const int UnpackHiMask[] = {2, 2, 3, 3};
8617 if (isShuffleEquivalent(V1, V2, Mask, {0, 0, 1, 1}))
8618 Mask = UnpackLoMask;
8619 else if (isShuffleEquivalent(V1, V2, Mask, {2, 2, 3, 3}))
8620 Mask = UnpackHiMask;
8622 return DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V1,
8623 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
8626 // Try to use shift instructions.
8628 lowerVectorShuffleAsShift(DL, MVT::v4i32, V1, V2, Mask, DAG))
8631 // There are special ways we can lower some single-element blends.
8632 if (NumV2Elements == 1)
8633 if (SDValue V = lowerVectorShuffleAsElementInsertion(DL, MVT::v4i32, V1, V2,
8634 Mask, Subtarget, DAG))
8637 // We have different paths for blend lowering, but they all must use the
8638 // *exact* same predicate.
8639 bool IsBlendSupported = Subtarget->hasSSE41();
8640 if (IsBlendSupported)
8641 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4i32, V1, V2, Mask,
8645 if (SDValue Masked =
8646 lowerVectorShuffleAsBitMask(DL, MVT::v4i32, V1, V2, Mask, DAG))
8649 // Use dedicated unpack instructions for masks that match their pattern.
8651 lowerVectorShuffleWithUNPCK(DL, MVT::v4i32, Mask, V1, V2, DAG))
8654 // Try to use byte rotation instructions.
8655 // Its more profitable for pre-SSSE3 to use shuffles/unpacks.
8656 if (Subtarget->hasSSSE3())
8657 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8658 DL, MVT::v4i32, V1, V2, Mask, Subtarget, DAG))
8661 // If we have direct support for blends, we should lower by decomposing into
8662 // a permute. That will be faster than the domain cross.
8663 if (IsBlendSupported)
8664 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4i32, V1, V2,
8667 // Try to lower by permuting the inputs into an unpack instruction.
8668 if (SDValue Unpack = lowerVectorShuffleAsPermuteAndUnpack(DL, MVT::v4i32, V1,
8672 // We implement this with SHUFPS because it can blend from two vectors.
8673 // Because we're going to eventually use SHUFPS, we use SHUFPS even to build
8674 // up the inputs, bypassing domain shift penalties that we would encur if we
8675 // directly used PSHUFD on Nehalem and older. For newer chips, this isn't
8677 return DAG.getBitcast(
8679 DAG.getVectorShuffle(MVT::v4f32, DL, DAG.getBitcast(MVT::v4f32, V1),
8680 DAG.getBitcast(MVT::v4f32, V2), Mask));
8683 /// \brief Lowering of single-input v8i16 shuffles is the cornerstone of SSE2
8684 /// shuffle lowering, and the most complex part.
8686 /// The lowering strategy is to try to form pairs of input lanes which are
8687 /// targeted at the same half of the final vector, and then use a dword shuffle
8688 /// to place them onto the right half, and finally unpack the paired lanes into
8689 /// their final position.
8691 /// The exact breakdown of how to form these dword pairs and align them on the
8692 /// correct sides is really tricky. See the comments within the function for
8693 /// more of the details.
8695 /// This code also handles repeated 128-bit lanes of v8i16 shuffles, but each
8696 /// lane must shuffle the *exact* same way. In fact, you must pass a v8 Mask to
8697 /// this routine for it to work correctly. To shuffle a 256-bit or 512-bit i16
8698 /// vector, form the analogous 128-bit 8-element Mask.
8699 static SDValue lowerV8I16GeneralSingleInputVectorShuffle(
8700 SDLoc DL, MVT VT, SDValue V, MutableArrayRef<int> Mask,
8701 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
8702 assert(VT.getVectorElementType() == MVT::i16 && "Bad input type!");
8703 MVT PSHUFDVT = MVT::getVectorVT(MVT::i32, VT.getVectorNumElements() / 2);
8705 assert(Mask.size() == 8 && "Shuffle mask length doen't match!");
8706 MutableArrayRef<int> LoMask = Mask.slice(0, 4);
8707 MutableArrayRef<int> HiMask = Mask.slice(4, 4);
8709 SmallVector<int, 4> LoInputs;
8710 std::copy_if(LoMask.begin(), LoMask.end(), std::back_inserter(LoInputs),
8711 [](int M) { return M >= 0; });
8712 std::sort(LoInputs.begin(), LoInputs.end());
8713 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()), LoInputs.end());
8714 SmallVector<int, 4> HiInputs;
8715 std::copy_if(HiMask.begin(), HiMask.end(), std::back_inserter(HiInputs),
8716 [](int M) { return M >= 0; });
8717 std::sort(HiInputs.begin(), HiInputs.end());
8718 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()), HiInputs.end());
8720 std::lower_bound(LoInputs.begin(), LoInputs.end(), 4) - LoInputs.begin();
8721 int NumHToL = LoInputs.size() - NumLToL;
8723 std::lower_bound(HiInputs.begin(), HiInputs.end(), 4) - HiInputs.begin();
8724 int NumHToH = HiInputs.size() - NumLToH;
8725 MutableArrayRef<int> LToLInputs(LoInputs.data(), NumLToL);
8726 MutableArrayRef<int> LToHInputs(HiInputs.data(), NumLToH);
8727 MutableArrayRef<int> HToLInputs(LoInputs.data() + NumLToL, NumHToL);
8728 MutableArrayRef<int> HToHInputs(HiInputs.data() + NumLToH, NumHToH);
8730 // Simplify the 1-into-3 and 3-into-1 cases with a single pshufd. For all
8731 // such inputs we can swap two of the dwords across the half mark and end up
8732 // with <=2 inputs to each half in each half. Once there, we can fall through
8733 // to the generic code below. For example:
8735 // Input: [a, b, c, d, e, f, g, h] -PSHUFD[0,2,1,3]-> [a, b, e, f, c, d, g, h]
8736 // Mask: [0, 1, 2, 7, 4, 5, 6, 3] -----------------> [0, 1, 4, 7, 2, 3, 6, 5]
8738 // However in some very rare cases we have a 1-into-3 or 3-into-1 on one half
8739 // and an existing 2-into-2 on the other half. In this case we may have to
8740 // pre-shuffle the 2-into-2 half to avoid turning it into a 3-into-1 or
8741 // 1-into-3 which could cause us to cycle endlessly fixing each side in turn.
8742 // Fortunately, we don't have to handle anything but a 2-into-2 pattern
8743 // because any other situation (including a 3-into-1 or 1-into-3 in the other
8744 // half than the one we target for fixing) will be fixed when we re-enter this
8745 // path. We will also combine away any sequence of PSHUFD instructions that
8746 // result into a single instruction. Here is an example of the tricky case:
8748 // Input: [a, b, c, d, e, f, g, h] -PSHUFD[0,2,1,3]-> [a, b, e, f, c, d, g, h]
8749 // Mask: [3, 7, 1, 0, 2, 7, 3, 5] -THIS-IS-BAD!!!!-> [5, 7, 1, 0, 4, 7, 5, 3]
8751 // This now has a 1-into-3 in the high half! Instead, we do two shuffles:
8753 // Input: [a, b, c, d, e, f, g, h] PSHUFHW[0,2,1,3]-> [a, b, c, d, e, g, f, h]
8754 // Mask: [3, 7, 1, 0, 2, 7, 3, 5] -----------------> [3, 7, 1, 0, 2, 7, 3, 6]
8756 // Input: [a, b, c, d, e, g, f, h] -PSHUFD[0,2,1,3]-> [a, b, e, g, c, d, f, h]
8757 // Mask: [3, 7, 1, 0, 2, 7, 3, 6] -----------------> [5, 7, 1, 0, 4, 7, 5, 6]
8759 // The result is fine to be handled by the generic logic.
8760 auto balanceSides = [&](ArrayRef<int> AToAInputs, ArrayRef<int> BToAInputs,
8761 ArrayRef<int> BToBInputs, ArrayRef<int> AToBInputs,
8762 int AOffset, int BOffset) {
8763 assert((AToAInputs.size() == 3 || AToAInputs.size() == 1) &&
8764 "Must call this with A having 3 or 1 inputs from the A half.");
8765 assert((BToAInputs.size() == 1 || BToAInputs.size() == 3) &&
8766 "Must call this with B having 1 or 3 inputs from the B half.");
8767 assert(AToAInputs.size() + BToAInputs.size() == 4 &&
8768 "Must call this with either 3:1 or 1:3 inputs (summing to 4).");
8770 bool ThreeAInputs = AToAInputs.size() == 3;
8772 // Compute the index of dword with only one word among the three inputs in
8773 // a half by taking the sum of the half with three inputs and subtracting
8774 // the sum of the actual three inputs. The difference is the remaining
8777 int &TripleDWord = ThreeAInputs ? ADWord : BDWord;
8778 int &OneInputDWord = ThreeAInputs ? BDWord : ADWord;
8779 int TripleInputOffset = ThreeAInputs ? AOffset : BOffset;
8780 ArrayRef<int> TripleInputs = ThreeAInputs ? AToAInputs : BToAInputs;
8781 int OneInput = ThreeAInputs ? BToAInputs[0] : AToAInputs[0];
8782 int TripleInputSum = 0 + 1 + 2 + 3 + (4 * TripleInputOffset);
8783 int TripleNonInputIdx =
8784 TripleInputSum - std::accumulate(TripleInputs.begin(), TripleInputs.end(), 0);
8785 TripleDWord = TripleNonInputIdx / 2;
8787 // We use xor with one to compute the adjacent DWord to whichever one the
8789 OneInputDWord = (OneInput / 2) ^ 1;
8791 // Check for one tricky case: We're fixing a 3<-1 or a 1<-3 shuffle for AToA
8792 // and BToA inputs. If there is also such a problem with the BToB and AToB
8793 // inputs, we don't try to fix it necessarily -- we'll recurse and see it in
8794 // the next pass. However, if we have a 2<-2 in the BToB and AToB inputs, it
8795 // is essential that we don't *create* a 3<-1 as then we might oscillate.
8796 if (BToBInputs.size() == 2 && AToBInputs.size() == 2) {
8797 // Compute how many inputs will be flipped by swapping these DWords. We
8799 // to balance this to ensure we don't form a 3-1 shuffle in the other
8801 int NumFlippedAToBInputs =
8802 std::count(AToBInputs.begin(), AToBInputs.end(), 2 * ADWord) +
8803 std::count(AToBInputs.begin(), AToBInputs.end(), 2 * ADWord + 1);
8804 int NumFlippedBToBInputs =
8805 std::count(BToBInputs.begin(), BToBInputs.end(), 2 * BDWord) +
8806 std::count(BToBInputs.begin(), BToBInputs.end(), 2 * BDWord + 1);
8807 if ((NumFlippedAToBInputs == 1 &&
8808 (NumFlippedBToBInputs == 0 || NumFlippedBToBInputs == 2)) ||
8809 (NumFlippedBToBInputs == 1 &&
8810 (NumFlippedAToBInputs == 0 || NumFlippedAToBInputs == 2))) {
8811 // We choose whether to fix the A half or B half based on whether that
8812 // half has zero flipped inputs. At zero, we may not be able to fix it
8813 // with that half. We also bias towards fixing the B half because that
8814 // will more commonly be the high half, and we have to bias one way.
8815 auto FixFlippedInputs = [&V, &DL, &Mask, &DAG](int PinnedIdx, int DWord,
8816 ArrayRef<int> Inputs) {
8817 int FixIdx = PinnedIdx ^ 1; // The adjacent slot to the pinned slot.
8818 bool IsFixIdxInput = std::find(Inputs.begin(), Inputs.end(),
8819 PinnedIdx ^ 1) != Inputs.end();
8820 // Determine whether the free index is in the flipped dword or the
8821 // unflipped dword based on where the pinned index is. We use this bit
8822 // in an xor to conditionally select the adjacent dword.
8823 int FixFreeIdx = 2 * (DWord ^ (PinnedIdx / 2 == DWord));
8824 bool IsFixFreeIdxInput = std::find(Inputs.begin(), Inputs.end(),
8825 FixFreeIdx) != Inputs.end();
8826 if (IsFixIdxInput == IsFixFreeIdxInput)
8828 IsFixFreeIdxInput = std::find(Inputs.begin(), Inputs.end(),
8829 FixFreeIdx) != Inputs.end();
8830 assert(IsFixIdxInput != IsFixFreeIdxInput &&
8831 "We need to be changing the number of flipped inputs!");
8832 int PSHUFHalfMask[] = {0, 1, 2, 3};
8833 std::swap(PSHUFHalfMask[FixFreeIdx % 4], PSHUFHalfMask[FixIdx % 4]);
8834 V = DAG.getNode(FixIdx < 4 ? X86ISD::PSHUFLW : X86ISD::PSHUFHW, DL,
8836 getV4X86ShuffleImm8ForMask(PSHUFHalfMask, DL, DAG));
8839 if (M != -1 && M == FixIdx)
8841 else if (M != -1 && M == FixFreeIdx)
8844 if (NumFlippedBToBInputs != 0) {
8846 BToAInputs.size() == 3 ? TripleNonInputIdx : OneInput;
8847 FixFlippedInputs(BPinnedIdx, BDWord, BToBInputs);
8849 assert(NumFlippedAToBInputs != 0 && "Impossible given predicates!");
8850 int APinnedIdx = ThreeAInputs ? TripleNonInputIdx : OneInput;
8851 FixFlippedInputs(APinnedIdx, ADWord, AToBInputs);
8856 int PSHUFDMask[] = {0, 1, 2, 3};
8857 PSHUFDMask[ADWord] = BDWord;
8858 PSHUFDMask[BDWord] = ADWord;
8861 DAG.getNode(X86ISD::PSHUFD, DL, PSHUFDVT, DAG.getBitcast(PSHUFDVT, V),
8862 getV4X86ShuffleImm8ForMask(PSHUFDMask, DL, DAG)));
8864 // Adjust the mask to match the new locations of A and B.
8866 if (M != -1 && M/2 == ADWord)
8867 M = 2 * BDWord + M % 2;
8868 else if (M != -1 && M/2 == BDWord)
8869 M = 2 * ADWord + M % 2;
8871 // Recurse back into this routine to re-compute state now that this isn't
8872 // a 3 and 1 problem.
8873 return lowerV8I16GeneralSingleInputVectorShuffle(DL, VT, V, Mask, Subtarget,
8876 if ((NumLToL == 3 && NumHToL == 1) || (NumLToL == 1 && NumHToL == 3))
8877 return balanceSides(LToLInputs, HToLInputs, HToHInputs, LToHInputs, 0, 4);
8878 else if ((NumHToH == 3 && NumLToH == 1) || (NumHToH == 1 && NumLToH == 3))
8879 return balanceSides(HToHInputs, LToHInputs, LToLInputs, HToLInputs, 4, 0);
8881 // At this point there are at most two inputs to the low and high halves from
8882 // each half. That means the inputs can always be grouped into dwords and
8883 // those dwords can then be moved to the correct half with a dword shuffle.
8884 // We use at most one low and one high word shuffle to collect these paired
8885 // inputs into dwords, and finally a dword shuffle to place them.
8886 int PSHUFLMask[4] = {-1, -1, -1, -1};
8887 int PSHUFHMask[4] = {-1, -1, -1, -1};
8888 int PSHUFDMask[4] = {-1, -1, -1, -1};
8890 // First fix the masks for all the inputs that are staying in their
8891 // original halves. This will then dictate the targets of the cross-half
8893 auto fixInPlaceInputs =
8894 [&PSHUFDMask](ArrayRef<int> InPlaceInputs, ArrayRef<int> IncomingInputs,
8895 MutableArrayRef<int> SourceHalfMask,
8896 MutableArrayRef<int> HalfMask, int HalfOffset) {
8897 if (InPlaceInputs.empty())
8899 if (InPlaceInputs.size() == 1) {
8900 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
8901 InPlaceInputs[0] - HalfOffset;
8902 PSHUFDMask[InPlaceInputs[0] / 2] = InPlaceInputs[0] / 2;
8905 if (IncomingInputs.empty()) {
8906 // Just fix all of the in place inputs.
8907 for (int Input : InPlaceInputs) {
8908 SourceHalfMask[Input - HalfOffset] = Input - HalfOffset;
8909 PSHUFDMask[Input / 2] = Input / 2;
8914 assert(InPlaceInputs.size() == 2 && "Cannot handle 3 or 4 inputs!");
8915 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
8916 InPlaceInputs[0] - HalfOffset;
8917 // Put the second input next to the first so that they are packed into
8918 // a dword. We find the adjacent index by toggling the low bit.
8919 int AdjIndex = InPlaceInputs[0] ^ 1;
8920 SourceHalfMask[AdjIndex - HalfOffset] = InPlaceInputs[1] - HalfOffset;
8921 std::replace(HalfMask.begin(), HalfMask.end(), InPlaceInputs[1], AdjIndex);
8922 PSHUFDMask[AdjIndex / 2] = AdjIndex / 2;
8924 fixInPlaceInputs(LToLInputs, HToLInputs, PSHUFLMask, LoMask, 0);
8925 fixInPlaceInputs(HToHInputs, LToHInputs, PSHUFHMask, HiMask, 4);
8927 // Now gather the cross-half inputs and place them into a free dword of
8928 // their target half.
8929 // FIXME: This operation could almost certainly be simplified dramatically to
8930 // look more like the 3-1 fixing operation.
8931 auto moveInputsToRightHalf = [&PSHUFDMask](
8932 MutableArrayRef<int> IncomingInputs, ArrayRef<int> ExistingInputs,
8933 MutableArrayRef<int> SourceHalfMask, MutableArrayRef<int> HalfMask,
8934 MutableArrayRef<int> FinalSourceHalfMask, int SourceOffset,
8936 auto isWordClobbered = [](ArrayRef<int> SourceHalfMask, int Word) {
8937 return SourceHalfMask[Word] != -1 && SourceHalfMask[Word] != Word;
8939 auto isDWordClobbered = [&isWordClobbered](ArrayRef<int> SourceHalfMask,
8941 int LowWord = Word & ~1;
8942 int HighWord = Word | 1;
8943 return isWordClobbered(SourceHalfMask, LowWord) ||
8944 isWordClobbered(SourceHalfMask, HighWord);
8947 if (IncomingInputs.empty())
8950 if (ExistingInputs.empty()) {
8951 // Map any dwords with inputs from them into the right half.
8952 for (int Input : IncomingInputs) {
8953 // If the source half mask maps over the inputs, turn those into
8954 // swaps and use the swapped lane.
8955 if (isWordClobbered(SourceHalfMask, Input - SourceOffset)) {
8956 if (SourceHalfMask[SourceHalfMask[Input - SourceOffset]] == -1) {
8957 SourceHalfMask[SourceHalfMask[Input - SourceOffset]] =
8958 Input - SourceOffset;
8959 // We have to swap the uses in our half mask in one sweep.
8960 for (int &M : HalfMask)
8961 if (M == SourceHalfMask[Input - SourceOffset] + SourceOffset)
8963 else if (M == Input)
8964 M = SourceHalfMask[Input - SourceOffset] + SourceOffset;
8966 assert(SourceHalfMask[SourceHalfMask[Input - SourceOffset]] ==
8967 Input - SourceOffset &&
8968 "Previous placement doesn't match!");
8970 // Note that this correctly re-maps both when we do a swap and when
8971 // we observe the other side of the swap above. We rely on that to
8972 // avoid swapping the members of the input list directly.
8973 Input = SourceHalfMask[Input - SourceOffset] + SourceOffset;
8976 // Map the input's dword into the correct half.
8977 if (PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] == -1)
8978 PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] = Input / 2;
8980 assert(PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] ==
8982 "Previous placement doesn't match!");
8985 // And just directly shift any other-half mask elements to be same-half
8986 // as we will have mirrored the dword containing the element into the
8987 // same position within that half.
8988 for (int &M : HalfMask)
8989 if (M >= SourceOffset && M < SourceOffset + 4) {
8990 M = M - SourceOffset + DestOffset;
8991 assert(M >= 0 && "This should never wrap below zero!");
8996 // Ensure we have the input in a viable dword of its current half. This
8997 // is particularly tricky because the original position may be clobbered
8998 // by inputs being moved and *staying* in that half.
8999 if (IncomingInputs.size() == 1) {
9000 if (isWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
9001 int InputFixed = std::find(std::begin(SourceHalfMask),
9002 std::end(SourceHalfMask), -1) -
9003 std::begin(SourceHalfMask) + SourceOffset;
9004 SourceHalfMask[InputFixed - SourceOffset] =
9005 IncomingInputs[0] - SourceOffset;
9006 std::replace(HalfMask.begin(), HalfMask.end(), IncomingInputs[0],
9008 IncomingInputs[0] = InputFixed;
9010 } else if (IncomingInputs.size() == 2) {
9011 if (IncomingInputs[0] / 2 != IncomingInputs[1] / 2 ||
9012 isDWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
9013 // We have two non-adjacent or clobbered inputs we need to extract from
9014 // the source half. To do this, we need to map them into some adjacent
9015 // dword slot in the source mask.
9016 int InputsFixed[2] = {IncomingInputs[0] - SourceOffset,
9017 IncomingInputs[1] - SourceOffset};
9019 // If there is a free slot in the source half mask adjacent to one of
9020 // the inputs, place the other input in it. We use (Index XOR 1) to
9021 // compute an adjacent index.
9022 if (!isWordClobbered(SourceHalfMask, InputsFixed[0]) &&
9023 SourceHalfMask[InputsFixed[0] ^ 1] == -1) {
9024 SourceHalfMask[InputsFixed[0]] = InputsFixed[0];
9025 SourceHalfMask[InputsFixed[0] ^ 1] = InputsFixed[1];
9026 InputsFixed[1] = InputsFixed[0] ^ 1;
9027 } else if (!isWordClobbered(SourceHalfMask, InputsFixed[1]) &&
9028 SourceHalfMask[InputsFixed[1] ^ 1] == -1) {
9029 SourceHalfMask[InputsFixed[1]] = InputsFixed[1];
9030 SourceHalfMask[InputsFixed[1] ^ 1] = InputsFixed[0];
9031 InputsFixed[0] = InputsFixed[1] ^ 1;
9032 } else if (SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1)] == -1 &&
9033 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1) + 1] == -1) {
9034 // The two inputs are in the same DWord but it is clobbered and the
9035 // adjacent DWord isn't used at all. Move both inputs to the free
9037 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1)] = InputsFixed[0];
9038 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1) + 1] = InputsFixed[1];
9039 InputsFixed[0] = 2 * ((InputsFixed[0] / 2) ^ 1);
9040 InputsFixed[1] = 2 * ((InputsFixed[0] / 2) ^ 1) + 1;
9042 // The only way we hit this point is if there is no clobbering
9043 // (because there are no off-half inputs to this half) and there is no
9044 // free slot adjacent to one of the inputs. In this case, we have to
9045 // swap an input with a non-input.
9046 for (int i = 0; i < 4; ++i)
9047 assert((SourceHalfMask[i] == -1 || SourceHalfMask[i] == i) &&
9048 "We can't handle any clobbers here!");
9049 assert(InputsFixed[1] != (InputsFixed[0] ^ 1) &&
9050 "Cannot have adjacent inputs here!");
9052 SourceHalfMask[InputsFixed[0] ^ 1] = InputsFixed[1];
9053 SourceHalfMask[InputsFixed[1]] = InputsFixed[0] ^ 1;
9055 // We also have to update the final source mask in this case because
9056 // it may need to undo the above swap.
9057 for (int &M : FinalSourceHalfMask)
9058 if (M == (InputsFixed[0] ^ 1) + SourceOffset)
9059 M = InputsFixed[1] + SourceOffset;
9060 else if (M == InputsFixed[1] + SourceOffset)
9061 M = (InputsFixed[0] ^ 1) + SourceOffset;
9063 InputsFixed[1] = InputsFixed[0] ^ 1;
9066 // Point everything at the fixed inputs.
9067 for (int &M : HalfMask)
9068 if (M == IncomingInputs[0])
9069 M = InputsFixed[0] + SourceOffset;
9070 else if (M == IncomingInputs[1])
9071 M = InputsFixed[1] + SourceOffset;
9073 IncomingInputs[0] = InputsFixed[0] + SourceOffset;
9074 IncomingInputs[1] = InputsFixed[1] + SourceOffset;
9077 llvm_unreachable("Unhandled input size!");
9080 // Now hoist the DWord down to the right half.
9081 int FreeDWord = (PSHUFDMask[DestOffset / 2] == -1 ? 0 : 1) + DestOffset / 2;
9082 assert(PSHUFDMask[FreeDWord] == -1 && "DWord not free");
9083 PSHUFDMask[FreeDWord] = IncomingInputs[0] / 2;
9084 for (int &M : HalfMask)
9085 for (int Input : IncomingInputs)
9087 M = FreeDWord * 2 + Input % 2;
9089 moveInputsToRightHalf(HToLInputs, LToLInputs, PSHUFHMask, LoMask, HiMask,
9090 /*SourceOffset*/ 4, /*DestOffset*/ 0);
9091 moveInputsToRightHalf(LToHInputs, HToHInputs, PSHUFLMask, HiMask, LoMask,
9092 /*SourceOffset*/ 0, /*DestOffset*/ 4);
9094 // Now enact all the shuffles we've computed to move the inputs into their
9096 if (!isNoopShuffleMask(PSHUFLMask))
9097 V = DAG.getNode(X86ISD::PSHUFLW, DL, VT, V,
9098 getV4X86ShuffleImm8ForMask(PSHUFLMask, DL, DAG));
9099 if (!isNoopShuffleMask(PSHUFHMask))
9100 V = DAG.getNode(X86ISD::PSHUFHW, DL, VT, V,
9101 getV4X86ShuffleImm8ForMask(PSHUFHMask, DL, DAG));
9102 if (!isNoopShuffleMask(PSHUFDMask))
9105 DAG.getNode(X86ISD::PSHUFD, DL, PSHUFDVT, DAG.getBitcast(PSHUFDVT, V),
9106 getV4X86ShuffleImm8ForMask(PSHUFDMask, DL, DAG)));
9108 // At this point, each half should contain all its inputs, and we can then
9109 // just shuffle them into their final position.
9110 assert(std::count_if(LoMask.begin(), LoMask.end(),
9111 [](int M) { return M >= 4; }) == 0 &&
9112 "Failed to lift all the high half inputs to the low mask!");
9113 assert(std::count_if(HiMask.begin(), HiMask.end(),
9114 [](int M) { return M >= 0 && M < 4; }) == 0 &&
9115 "Failed to lift all the low half inputs to the high mask!");
9117 // Do a half shuffle for the low mask.
9118 if (!isNoopShuffleMask(LoMask))
9119 V = DAG.getNode(X86ISD::PSHUFLW, DL, VT, V,
9120 getV4X86ShuffleImm8ForMask(LoMask, DL, DAG));
9122 // Do a half shuffle with the high mask after shifting its values down.
9123 for (int &M : HiMask)
9126 if (!isNoopShuffleMask(HiMask))
9127 V = DAG.getNode(X86ISD::PSHUFHW, DL, VT, V,
9128 getV4X86ShuffleImm8ForMask(HiMask, DL, DAG));
9133 /// \brief Helper to form a PSHUFB-based shuffle+blend.
9134 static SDValue lowerVectorShuffleAsPSHUFB(SDLoc DL, MVT VT, SDValue V1,
9135 SDValue V2, ArrayRef<int> Mask,
9136 SelectionDAG &DAG, bool &V1InUse,
9138 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
9144 int Size = Mask.size();
9145 int Scale = 16 / Size;
9146 for (int i = 0; i < 16; ++i) {
9147 if (Mask[i / Scale] == -1) {
9148 V1Mask[i] = V2Mask[i] = DAG.getUNDEF(MVT::i8);
9150 const int ZeroMask = 0x80;
9151 int V1Idx = Mask[i / Scale] < Size ? Mask[i / Scale] * Scale + i % Scale
9153 int V2Idx = Mask[i / Scale] < Size
9155 : (Mask[i / Scale] - Size) * Scale + i % Scale;
9156 if (Zeroable[i / Scale])
9157 V1Idx = V2Idx = ZeroMask;
9158 V1Mask[i] = DAG.getConstant(V1Idx, DL, MVT::i8);
9159 V2Mask[i] = DAG.getConstant(V2Idx, DL, MVT::i8);
9160 V1InUse |= (ZeroMask != V1Idx);
9161 V2InUse |= (ZeroMask != V2Idx);
9166 V1 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8,
9167 DAG.getBitcast(MVT::v16i8, V1),
9168 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V1Mask));
9170 V2 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8,
9171 DAG.getBitcast(MVT::v16i8, V2),
9172 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V2Mask));
9174 // If we need shuffled inputs from both, blend the two.
9176 if (V1InUse && V2InUse)
9177 V = DAG.getNode(ISD::OR, DL, MVT::v16i8, V1, V2);
9179 V = V1InUse ? V1 : V2;
9181 // Cast the result back to the correct type.
9182 return DAG.getBitcast(VT, V);
9185 /// \brief Generic lowering of 8-lane i16 shuffles.
9187 /// This handles both single-input shuffles and combined shuffle/blends with
9188 /// two inputs. The single input shuffles are immediately delegated to
9189 /// a dedicated lowering routine.
9191 /// The blends are lowered in one of three fundamental ways. If there are few
9192 /// enough inputs, it delegates to a basic UNPCK-based strategy. If the shuffle
9193 /// of the input is significantly cheaper when lowered as an interleaving of
9194 /// the two inputs, try to interleave them. Otherwise, blend the low and high
9195 /// halves of the inputs separately (making them have relatively few inputs)
9196 /// and then concatenate them.
9197 static SDValue lowerV8I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9198 const X86Subtarget *Subtarget,
9199 SelectionDAG &DAG) {
9201 assert(Op.getSimpleValueType() == MVT::v8i16 && "Bad shuffle type!");
9202 assert(V1.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
9203 assert(V2.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
9204 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9205 ArrayRef<int> OrigMask = SVOp->getMask();
9206 int MaskStorage[8] = {OrigMask[0], OrigMask[1], OrigMask[2], OrigMask[3],
9207 OrigMask[4], OrigMask[5], OrigMask[6], OrigMask[7]};
9208 MutableArrayRef<int> Mask(MaskStorage);
9210 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
9212 // Whenever we can lower this as a zext, that instruction is strictly faster
9213 // than any alternative.
9214 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(
9215 DL, MVT::v8i16, V1, V2, OrigMask, Subtarget, DAG))
9218 auto isV1 = [](int M) { return M >= 0 && M < 8; };
9220 auto isV2 = [](int M) { return M >= 8; };
9222 int NumV2Inputs = std::count_if(Mask.begin(), Mask.end(), isV2);
9224 if (NumV2Inputs == 0) {
9225 // Check for being able to broadcast a single element.
9226 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v8i16, V1,
9227 Mask, Subtarget, DAG))
9230 // Try to use shift instructions.
9232 lowerVectorShuffleAsShift(DL, MVT::v8i16, V1, V1, Mask, DAG))
9235 // Use dedicated unpack instructions for masks that match their pattern.
9237 lowerVectorShuffleWithUNPCK(DL, MVT::v8i16, Mask, V1, V2, DAG))
9240 // Try to use byte rotation instructions.
9241 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(DL, MVT::v8i16, V1, V1,
9242 Mask, Subtarget, DAG))
9245 return lowerV8I16GeneralSingleInputVectorShuffle(DL, MVT::v8i16, V1, Mask,
9249 assert(std::any_of(Mask.begin(), Mask.end(), isV1) &&
9250 "All single-input shuffles should be canonicalized to be V1-input "
9253 // Try to use shift instructions.
9255 lowerVectorShuffleAsShift(DL, MVT::v8i16, V1, V2, Mask, DAG))
9258 // See if we can use SSE4A Extraction / Insertion.
9259 if (Subtarget->hasSSE4A())
9260 if (SDValue V = lowerVectorShuffleWithSSE4A(DL, MVT::v8i16, V1, V2, Mask, DAG))
9263 // There are special ways we can lower some single-element blends.
9264 if (NumV2Inputs == 1)
9265 if (SDValue V = lowerVectorShuffleAsElementInsertion(DL, MVT::v8i16, V1, V2,
9266 Mask, Subtarget, DAG))
9269 // We have different paths for blend lowering, but they all must use the
9270 // *exact* same predicate.
9271 bool IsBlendSupported = Subtarget->hasSSE41();
9272 if (IsBlendSupported)
9273 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8i16, V1, V2, Mask,
9277 if (SDValue Masked =
9278 lowerVectorShuffleAsBitMask(DL, MVT::v8i16, V1, V2, Mask, DAG))
9281 // Use dedicated unpack instructions for masks that match their pattern.
9283 lowerVectorShuffleWithUNPCK(DL, MVT::v8i16, Mask, V1, V2, DAG))
9286 // Try to use byte rotation instructions.
9287 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
9288 DL, MVT::v8i16, V1, V2, Mask, Subtarget, DAG))
9291 if (SDValue BitBlend =
9292 lowerVectorShuffleAsBitBlend(DL, MVT::v8i16, V1, V2, Mask, DAG))
9295 if (SDValue Unpack = lowerVectorShuffleAsPermuteAndUnpack(DL, MVT::v8i16, V1,
9299 // If we can't directly blend but can use PSHUFB, that will be better as it
9300 // can both shuffle and set up the inefficient blend.
9301 if (!IsBlendSupported && Subtarget->hasSSSE3()) {
9302 bool V1InUse, V2InUse;
9303 return lowerVectorShuffleAsPSHUFB(DL, MVT::v8i16, V1, V2, Mask, DAG,
9307 // We can always bit-blend if we have to so the fallback strategy is to
9308 // decompose into single-input permutes and blends.
9309 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8i16, V1, V2,
9313 /// \brief Check whether a compaction lowering can be done by dropping even
9314 /// elements and compute how many times even elements must be dropped.
9316 /// This handles shuffles which take every Nth element where N is a power of
9317 /// two. Example shuffle masks:
9319 /// N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 0, 2, 4, 6, 8, 10, 12, 14
9320 /// N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30
9321 /// N = 2: 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12
9322 /// N = 2: 0, 4, 8, 12, 16, 20, 24, 28, 0, 4, 8, 12, 16, 20, 24, 28
9323 /// N = 3: 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8
9324 /// N = 3: 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24
9326 /// Any of these lanes can of course be undef.
9328 /// This routine only supports N <= 3.
9329 /// FIXME: Evaluate whether either AVX or AVX-512 have any opportunities here
9332 /// \returns N above, or the number of times even elements must be dropped if
9333 /// there is such a number. Otherwise returns zero.
9334 static int canLowerByDroppingEvenElements(ArrayRef<int> Mask) {
9335 // Figure out whether we're looping over two inputs or just one.
9336 bool IsSingleInput = isSingleInputShuffleMask(Mask);
9338 // The modulus for the shuffle vector entries is based on whether this is
9339 // a single input or not.
9340 int ShuffleModulus = Mask.size() * (IsSingleInput ? 1 : 2);
9341 assert(isPowerOf2_32((uint32_t)ShuffleModulus) &&
9342 "We should only be called with masks with a power-of-2 size!");
9344 uint64_t ModMask = (uint64_t)ShuffleModulus - 1;
9346 // We track whether the input is viable for all power-of-2 strides 2^1, 2^2,
9347 // and 2^3 simultaneously. This is because we may have ambiguity with
9348 // partially undef inputs.
9349 bool ViableForN[3] = {true, true, true};
9351 for (int i = 0, e = Mask.size(); i < e; ++i) {
9352 // Ignore undef lanes, we'll optimistically collapse them to the pattern we
9357 bool IsAnyViable = false;
9358 for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
9359 if (ViableForN[j]) {
9362 // The shuffle mask must be equal to (i * 2^N) % M.
9363 if ((uint64_t)Mask[i] == (((uint64_t)i << N) & ModMask))
9366 ViableForN[j] = false;
9368 // Early exit if we exhaust the possible powers of two.
9373 for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
9377 // Return 0 as there is no viable power of two.
9381 /// \brief Generic lowering of v16i8 shuffles.
9383 /// This is a hybrid strategy to lower v16i8 vectors. It first attempts to
9384 /// detect any complexity reducing interleaving. If that doesn't help, it uses
9385 /// UNPCK to spread the i8 elements across two i16-element vectors, and uses
9386 /// the existing lowering for v8i16 blends on each half, finally PACK-ing them
9388 static SDValue lowerV16I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9389 const X86Subtarget *Subtarget,
9390 SelectionDAG &DAG) {
9392 assert(Op.getSimpleValueType() == MVT::v16i8 && "Bad shuffle type!");
9393 assert(V1.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
9394 assert(V2.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
9395 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9396 ArrayRef<int> Mask = SVOp->getMask();
9397 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
9399 // Try to use shift instructions.
9401 lowerVectorShuffleAsShift(DL, MVT::v16i8, V1, V2, Mask, DAG))
9404 // Try to use byte rotation instructions.
9405 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
9406 DL, MVT::v16i8, V1, V2, Mask, Subtarget, DAG))
9409 // Try to use a zext lowering.
9410 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(
9411 DL, MVT::v16i8, V1, V2, Mask, Subtarget, DAG))
9414 // See if we can use SSE4A Extraction / Insertion.
9415 if (Subtarget->hasSSE4A())
9416 if (SDValue V = lowerVectorShuffleWithSSE4A(DL, MVT::v16i8, V1, V2, Mask, DAG))
9420 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 16; });
9422 // For single-input shuffles, there are some nicer lowering tricks we can use.
9423 if (NumV2Elements == 0) {
9424 // Check for being able to broadcast a single element.
9425 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v16i8, V1,
9426 Mask, Subtarget, DAG))
9429 // Check whether we can widen this to an i16 shuffle by duplicating bytes.
9430 // Notably, this handles splat and partial-splat shuffles more efficiently.
9431 // However, it only makes sense if the pre-duplication shuffle simplifies
9432 // things significantly. Currently, this means we need to be able to
9433 // express the pre-duplication shuffle as an i16 shuffle.
9435 // FIXME: We should check for other patterns which can be widened into an
9436 // i16 shuffle as well.
9437 auto canWidenViaDuplication = [](ArrayRef<int> Mask) {
9438 for (int i = 0; i < 16; i += 2)
9439 if (Mask[i] != -1 && Mask[i + 1] != -1 && Mask[i] != Mask[i + 1])
9444 auto tryToWidenViaDuplication = [&]() -> SDValue {
9445 if (!canWidenViaDuplication(Mask))
9447 SmallVector<int, 4> LoInputs;
9448 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(LoInputs),
9449 [](int M) { return M >= 0 && M < 8; });
9450 std::sort(LoInputs.begin(), LoInputs.end());
9451 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()),
9453 SmallVector<int, 4> HiInputs;
9454 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(HiInputs),
9455 [](int M) { return M >= 8; });
9456 std::sort(HiInputs.begin(), HiInputs.end());
9457 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()),
9460 bool TargetLo = LoInputs.size() >= HiInputs.size();
9461 ArrayRef<int> InPlaceInputs = TargetLo ? LoInputs : HiInputs;
9462 ArrayRef<int> MovingInputs = TargetLo ? HiInputs : LoInputs;
9464 int PreDupI16Shuffle[] = {-1, -1, -1, -1, -1, -1, -1, -1};
9465 SmallDenseMap<int, int, 8> LaneMap;
9466 for (int I : InPlaceInputs) {
9467 PreDupI16Shuffle[I/2] = I/2;
9470 int j = TargetLo ? 0 : 4, je = j + 4;
9471 for (int i = 0, ie = MovingInputs.size(); i < ie; ++i) {
9472 // Check if j is already a shuffle of this input. This happens when
9473 // there are two adjacent bytes after we move the low one.
9474 if (PreDupI16Shuffle[j] != MovingInputs[i] / 2) {
9475 // If we haven't yet mapped the input, search for a slot into which
9477 while (j < je && PreDupI16Shuffle[j] != -1)
9481 // We can't place the inputs into a single half with a simple i16 shuffle, so bail.
9484 // Map this input with the i16 shuffle.
9485 PreDupI16Shuffle[j] = MovingInputs[i] / 2;
9488 // Update the lane map based on the mapping we ended up with.
9489 LaneMap[MovingInputs[i]] = 2 * j + MovingInputs[i] % 2;
9491 V1 = DAG.getBitcast(
9493 DAG.getVectorShuffle(MVT::v8i16, DL, DAG.getBitcast(MVT::v8i16, V1),
9494 DAG.getUNDEF(MVT::v8i16), PreDupI16Shuffle));
9496 // Unpack the bytes to form the i16s that will be shuffled into place.
9497 V1 = DAG.getNode(TargetLo ? X86ISD::UNPCKL : X86ISD::UNPCKH, DL,
9498 MVT::v16i8, V1, V1);
9500 int PostDupI16Shuffle[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9501 for (int i = 0; i < 16; ++i)
9502 if (Mask[i] != -1) {
9503 int MappedMask = LaneMap[Mask[i]] - (TargetLo ? 0 : 8);
9504 assert(MappedMask < 8 && "Invalid v8 shuffle mask!");
9505 if (PostDupI16Shuffle[i / 2] == -1)
9506 PostDupI16Shuffle[i / 2] = MappedMask;
9508 assert(PostDupI16Shuffle[i / 2] == MappedMask &&
9509 "Conflicting entrties in the original shuffle!");
9511 return DAG.getBitcast(
9513 DAG.getVectorShuffle(MVT::v8i16, DL, DAG.getBitcast(MVT::v8i16, V1),
9514 DAG.getUNDEF(MVT::v8i16), PostDupI16Shuffle));
9516 if (SDValue V = tryToWidenViaDuplication())
9520 if (SDValue Masked =
9521 lowerVectorShuffleAsBitMask(DL, MVT::v16i8, V1, V2, Mask, DAG))
9524 // Use dedicated unpack instructions for masks that match their pattern.
9526 lowerVectorShuffleWithUNPCK(DL, MVT::v16i8, Mask, V1, V2, DAG))
9529 // Check for SSSE3 which lets us lower all v16i8 shuffles much more directly
9530 // with PSHUFB. It is important to do this before we attempt to generate any
9531 // blends but after all of the single-input lowerings. If the single input
9532 // lowerings can find an instruction sequence that is faster than a PSHUFB, we
9533 // want to preserve that and we can DAG combine any longer sequences into
9534 // a PSHUFB in the end. But once we start blending from multiple inputs,
9535 // the complexity of DAG combining bad patterns back into PSHUFB is too high,
9536 // and there are *very* few patterns that would actually be faster than the
9537 // PSHUFB approach because of its ability to zero lanes.
9539 // FIXME: The only exceptions to the above are blends which are exact
9540 // interleavings with direct instructions supporting them. We currently don't
9541 // handle those well here.
9542 if (Subtarget->hasSSSE3()) {
9543 bool V1InUse = false;
9544 bool V2InUse = false;
9546 SDValue PSHUFB = lowerVectorShuffleAsPSHUFB(DL, MVT::v16i8, V1, V2, Mask,
9547 DAG, V1InUse, V2InUse);
9549 // If both V1 and V2 are in use and we can use a direct blend or an unpack,
9550 // do so. This avoids using them to handle blends-with-zero which is
9551 // important as a single pshufb is significantly faster for that.
9552 if (V1InUse && V2InUse) {
9553 if (Subtarget->hasSSE41())
9554 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v16i8, V1, V2,
9555 Mask, Subtarget, DAG))
9558 // We can use an unpack to do the blending rather than an or in some
9559 // cases. Even though the or may be (very minorly) more efficient, we
9560 // preference this lowering because there are common cases where part of
9561 // the complexity of the shuffles goes away when we do the final blend as
9563 // FIXME: It might be worth trying to detect if the unpack-feeding
9564 // shuffles will both be pshufb, in which case we shouldn't bother with
9566 if (SDValue Unpack = lowerVectorShuffleAsPermuteAndUnpack(
9567 DL, MVT::v16i8, V1, V2, Mask, DAG))
9574 // There are special ways we can lower some single-element blends.
9575 if (NumV2Elements == 1)
9576 if (SDValue V = lowerVectorShuffleAsElementInsertion(DL, MVT::v16i8, V1, V2,
9577 Mask, Subtarget, DAG))
9580 if (SDValue BitBlend =
9581 lowerVectorShuffleAsBitBlend(DL, MVT::v16i8, V1, V2, Mask, DAG))
9584 // Check whether a compaction lowering can be done. This handles shuffles
9585 // which take every Nth element for some even N. See the helper function for
9588 // We special case these as they can be particularly efficiently handled with
9589 // the PACKUSB instruction on x86 and they show up in common patterns of
9590 // rearranging bytes to truncate wide elements.
9591 if (int NumEvenDrops = canLowerByDroppingEvenElements(Mask)) {
9592 // NumEvenDrops is the power of two stride of the elements. Another way of
9593 // thinking about it is that we need to drop the even elements this many
9594 // times to get the original input.
9595 bool IsSingleInput = isSingleInputShuffleMask(Mask);
9597 // First we need to zero all the dropped bytes.
9598 assert(NumEvenDrops <= 3 &&
9599 "No support for dropping even elements more than 3 times.");
9600 // We use the mask type to pick which bytes are preserved based on how many
9601 // elements are dropped.
9602 MVT MaskVTs[] = { MVT::v8i16, MVT::v4i32, MVT::v2i64 };
9603 SDValue ByteClearMask = DAG.getBitcast(
9604 MVT::v16i8, DAG.getConstant(0xFF, DL, MaskVTs[NumEvenDrops - 1]));
9605 V1 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V1, ByteClearMask);
9607 V2 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V2, ByteClearMask);
9609 // Now pack things back together.
9610 V1 = DAG.getBitcast(MVT::v8i16, V1);
9611 V2 = IsSingleInput ? V1 : DAG.getBitcast(MVT::v8i16, V2);
9612 SDValue Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, V1, V2);
9613 for (int i = 1; i < NumEvenDrops; ++i) {
9614 Result = DAG.getBitcast(MVT::v8i16, Result);
9615 Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, Result, Result);
9621 // Handle multi-input cases by blending single-input shuffles.
9622 if (NumV2Elements > 0)
9623 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v16i8, V1, V2,
9626 // The fallback path for single-input shuffles widens this into two v8i16
9627 // vectors with unpacks, shuffles those, and then pulls them back together
9631 int LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9632 int HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9633 for (int i = 0; i < 16; ++i)
9635 (i < 8 ? LoBlendMask[i] : HiBlendMask[i % 8]) = Mask[i];
9637 SDValue Zero = getZeroVector(MVT::v8i16, Subtarget, DAG, DL);
9639 SDValue VLoHalf, VHiHalf;
9640 // Check if any of the odd lanes in the v16i8 are used. If not, we can mask
9641 // them out and avoid using UNPCK{L,H} to extract the elements of V as
9643 if (std::none_of(std::begin(LoBlendMask), std::end(LoBlendMask),
9644 [](int M) { return M >= 0 && M % 2 == 1; }) &&
9645 std::none_of(std::begin(HiBlendMask), std::end(HiBlendMask),
9646 [](int M) { return M >= 0 && M % 2 == 1; })) {
9647 // Use a mask to drop the high bytes.
9648 VLoHalf = DAG.getBitcast(MVT::v8i16, V);
9649 VLoHalf = DAG.getNode(ISD::AND, DL, MVT::v8i16, VLoHalf,
9650 DAG.getConstant(0x00FF, DL, MVT::v8i16));
9652 // This will be a single vector shuffle instead of a blend so nuke VHiHalf.
9653 VHiHalf = DAG.getUNDEF(MVT::v8i16);
9655 // Squash the masks to point directly into VLoHalf.
9656 for (int &M : LoBlendMask)
9659 for (int &M : HiBlendMask)
9663 // Otherwise just unpack the low half of V into VLoHalf and the high half into
9664 // VHiHalf so that we can blend them as i16s.
9665 VLoHalf = DAG.getBitcast(
9666 MVT::v8i16, DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i8, V, Zero));
9667 VHiHalf = DAG.getBitcast(
9668 MVT::v8i16, DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i8, V, Zero));
9671 SDValue LoV = DAG.getVectorShuffle(MVT::v8i16, DL, VLoHalf, VHiHalf, LoBlendMask);
9672 SDValue HiV = DAG.getVectorShuffle(MVT::v8i16, DL, VLoHalf, VHiHalf, HiBlendMask);
9674 return DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, LoV, HiV);
9677 /// \brief Dispatching routine to lower various 128-bit x86 vector shuffles.
9679 /// This routine breaks down the specific type of 128-bit shuffle and
9680 /// dispatches to the lowering routines accordingly.
9681 static SDValue lower128BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9682 MVT VT, const X86Subtarget *Subtarget,
9683 SelectionDAG &DAG) {
9684 switch (VT.SimpleTy) {
9686 return lowerV2I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9688 return lowerV2F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9690 return lowerV4I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9692 return lowerV4F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9694 return lowerV8I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
9696 return lowerV16I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
9699 llvm_unreachable("Unimplemented!");
9703 /// \brief Helper function to test whether a shuffle mask could be
9704 /// simplified by widening the elements being shuffled.
9706 /// Appends the mask for wider elements in WidenedMask if valid. Otherwise
9707 /// leaves it in an unspecified state.
9709 /// NOTE: This must handle normal vector shuffle masks and *target* vector
9710 /// shuffle masks. The latter have the special property of a '-2' representing
9711 /// a zero-ed lane of a vector.
9712 static bool canWidenShuffleElements(ArrayRef<int> Mask,
9713 SmallVectorImpl<int> &WidenedMask) {
9714 for (int i = 0, Size = Mask.size(); i < Size; i += 2) {
9715 // If both elements are undef, its trivial.
9716 if (Mask[i] == SM_SentinelUndef && Mask[i + 1] == SM_SentinelUndef) {
9717 WidenedMask.push_back(SM_SentinelUndef);
9721 // Check for an undef mask and a mask value properly aligned to fit with
9722 // a pair of values. If we find such a case, use the non-undef mask's value.
9723 if (Mask[i] == SM_SentinelUndef && Mask[i + 1] >= 0 && Mask[i + 1] % 2 == 1) {
9724 WidenedMask.push_back(Mask[i + 1] / 2);
9727 if (Mask[i + 1] == SM_SentinelUndef && Mask[i] >= 0 && Mask[i] % 2 == 0) {
9728 WidenedMask.push_back(Mask[i] / 2);
9732 // When zeroing, we need to spread the zeroing across both lanes to widen.
9733 if (Mask[i] == SM_SentinelZero || Mask[i + 1] == SM_SentinelZero) {
9734 if ((Mask[i] == SM_SentinelZero || Mask[i] == SM_SentinelUndef) &&
9735 (Mask[i + 1] == SM_SentinelZero || Mask[i + 1] == SM_SentinelUndef)) {
9736 WidenedMask.push_back(SM_SentinelZero);
9742 // Finally check if the two mask values are adjacent and aligned with
9744 if (Mask[i] != SM_SentinelUndef && Mask[i] % 2 == 0 && Mask[i] + 1 == Mask[i + 1]) {
9745 WidenedMask.push_back(Mask[i] / 2);
9749 // Otherwise we can't safely widen the elements used in this shuffle.
9752 assert(WidenedMask.size() == Mask.size() / 2 &&
9753 "Incorrect size of mask after widening the elements!");
9758 /// \brief Generic routine to split vector shuffle into half-sized shuffles.
9760 /// This routine just extracts two subvectors, shuffles them independently, and
9761 /// then concatenates them back together. This should work effectively with all
9762 /// AVX vector shuffle types.
9763 static SDValue splitAndLowerVectorShuffle(SDLoc DL, MVT VT, SDValue V1,
9764 SDValue V2, ArrayRef<int> Mask,
9765 SelectionDAG &DAG) {
9766 assert(VT.getSizeInBits() >= 256 &&
9767 "Only for 256-bit or wider vector shuffles!");
9768 assert(V1.getSimpleValueType() == VT && "Bad operand type!");
9769 assert(V2.getSimpleValueType() == VT && "Bad operand type!");
9771 ArrayRef<int> LoMask = Mask.slice(0, Mask.size() / 2);
9772 ArrayRef<int> HiMask = Mask.slice(Mask.size() / 2);
9774 int NumElements = VT.getVectorNumElements();
9775 int SplitNumElements = NumElements / 2;
9776 MVT ScalarVT = VT.getVectorElementType();
9777 MVT SplitVT = MVT::getVectorVT(ScalarVT, NumElements / 2);
9779 // Rather than splitting build-vectors, just build two narrower build
9780 // vectors. This helps shuffling with splats and zeros.
9781 auto SplitVector = [&](SDValue V) {
9782 while (V.getOpcode() == ISD::BITCAST)
9783 V = V->getOperand(0);
9785 MVT OrigVT = V.getSimpleValueType();
9786 int OrigNumElements = OrigVT.getVectorNumElements();
9787 int OrigSplitNumElements = OrigNumElements / 2;
9788 MVT OrigScalarVT = OrigVT.getVectorElementType();
9789 MVT OrigSplitVT = MVT::getVectorVT(OrigScalarVT, OrigNumElements / 2);
9793 auto *BV = dyn_cast<BuildVectorSDNode>(V);
9795 LoV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, OrigSplitVT, V,
9796 DAG.getIntPtrConstant(0, DL));
9797 HiV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, OrigSplitVT, V,
9798 DAG.getIntPtrConstant(OrigSplitNumElements, DL));
9801 SmallVector<SDValue, 16> LoOps, HiOps;
9802 for (int i = 0; i < OrigSplitNumElements; ++i) {
9803 LoOps.push_back(BV->getOperand(i));
9804 HiOps.push_back(BV->getOperand(i + OrigSplitNumElements));
9806 LoV = DAG.getNode(ISD::BUILD_VECTOR, DL, OrigSplitVT, LoOps);
9807 HiV = DAG.getNode(ISD::BUILD_VECTOR, DL, OrigSplitVT, HiOps);
9809 return std::make_pair(DAG.getBitcast(SplitVT, LoV),
9810 DAG.getBitcast(SplitVT, HiV));
9813 SDValue LoV1, HiV1, LoV2, HiV2;
9814 std::tie(LoV1, HiV1) = SplitVector(V1);
9815 std::tie(LoV2, HiV2) = SplitVector(V2);
9817 // Now create two 4-way blends of these half-width vectors.
9818 auto HalfBlend = [&](ArrayRef<int> HalfMask) {
9819 bool UseLoV1 = false, UseHiV1 = false, UseLoV2 = false, UseHiV2 = false;
9820 SmallVector<int, 32> V1BlendMask, V2BlendMask, BlendMask;
9821 for (int i = 0; i < SplitNumElements; ++i) {
9822 int M = HalfMask[i];
9823 if (M >= NumElements) {
9824 if (M >= NumElements + SplitNumElements)
9828 V2BlendMask.push_back(M - NumElements);
9829 V1BlendMask.push_back(-1);
9830 BlendMask.push_back(SplitNumElements + i);
9831 } else if (M >= 0) {
9832 if (M >= SplitNumElements)
9836 V2BlendMask.push_back(-1);
9837 V1BlendMask.push_back(M);
9838 BlendMask.push_back(i);
9840 V2BlendMask.push_back(-1);
9841 V1BlendMask.push_back(-1);
9842 BlendMask.push_back(-1);
9846 // Because the lowering happens after all combining takes place, we need to
9847 // manually combine these blend masks as much as possible so that we create
9848 // a minimal number of high-level vector shuffle nodes.
9850 // First try just blending the halves of V1 or V2.
9851 if (!UseLoV1 && !UseHiV1 && !UseLoV2 && !UseHiV2)
9852 return DAG.getUNDEF(SplitVT);
9853 if (!UseLoV2 && !UseHiV2)
9854 return DAG.getVectorShuffle(SplitVT, DL, LoV1, HiV1, V1BlendMask);
9855 if (!UseLoV1 && !UseHiV1)
9856 return DAG.getVectorShuffle(SplitVT, DL, LoV2, HiV2, V2BlendMask);
9858 SDValue V1Blend, V2Blend;
9859 if (UseLoV1 && UseHiV1) {
9861 DAG.getVectorShuffle(SplitVT, DL, LoV1, HiV1, V1BlendMask);
9863 // We only use half of V1 so map the usage down into the final blend mask.
9864 V1Blend = UseLoV1 ? LoV1 : HiV1;
9865 for (int i = 0; i < SplitNumElements; ++i)
9866 if (BlendMask[i] >= 0 && BlendMask[i] < SplitNumElements)
9867 BlendMask[i] = V1BlendMask[i] - (UseLoV1 ? 0 : SplitNumElements);
9869 if (UseLoV2 && UseHiV2) {
9871 DAG.getVectorShuffle(SplitVT, DL, LoV2, HiV2, V2BlendMask);
9873 // We only use half of V2 so map the usage down into the final blend mask.
9874 V2Blend = UseLoV2 ? LoV2 : HiV2;
9875 for (int i = 0; i < SplitNumElements; ++i)
9876 if (BlendMask[i] >= SplitNumElements)
9877 BlendMask[i] = V2BlendMask[i] + (UseLoV2 ? SplitNumElements : 0);
9879 return DAG.getVectorShuffle(SplitVT, DL, V1Blend, V2Blend, BlendMask);
9881 SDValue Lo = HalfBlend(LoMask);
9882 SDValue Hi = HalfBlend(HiMask);
9883 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Lo, Hi);
9886 /// \brief Either split a vector in halves or decompose the shuffles and the
9889 /// This is provided as a good fallback for many lowerings of non-single-input
9890 /// shuffles with more than one 128-bit lane. In those cases, we want to select
9891 /// between splitting the shuffle into 128-bit components and stitching those
9892 /// back together vs. extracting the single-input shuffles and blending those
9894 static SDValue lowerVectorShuffleAsSplitOrBlend(SDLoc DL, MVT VT, SDValue V1,
9895 SDValue V2, ArrayRef<int> Mask,
9896 SelectionDAG &DAG) {
9897 assert(!isSingleInputShuffleMask(Mask) && "This routine must not be used to "
9898 "lower single-input shuffles as it "
9899 "could then recurse on itself.");
9900 int Size = Mask.size();
9902 // If this can be modeled as a broadcast of two elements followed by a blend,
9903 // prefer that lowering. This is especially important because broadcasts can
9904 // often fold with memory operands.
9905 auto DoBothBroadcast = [&] {
9906 int V1BroadcastIdx = -1, V2BroadcastIdx = -1;
9909 if (V2BroadcastIdx == -1)
9910 V2BroadcastIdx = M - Size;
9911 else if (M - Size != V2BroadcastIdx)
9913 } else if (M >= 0) {
9914 if (V1BroadcastIdx == -1)
9916 else if (M != V1BroadcastIdx)
9921 if (DoBothBroadcast())
9922 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask,
9925 // If the inputs all stem from a single 128-bit lane of each input, then we
9926 // split them rather than blending because the split will decompose to
9927 // unusually few instructions.
9928 int LaneCount = VT.getSizeInBits() / 128;
9929 int LaneSize = Size / LaneCount;
9930 SmallBitVector LaneInputs[2];
9931 LaneInputs[0].resize(LaneCount, false);
9932 LaneInputs[1].resize(LaneCount, false);
9933 for (int i = 0; i < Size; ++i)
9935 LaneInputs[Mask[i] / Size][(Mask[i] % Size) / LaneSize] = true;
9936 if (LaneInputs[0].count() <= 1 && LaneInputs[1].count() <= 1)
9937 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
9939 // Otherwise, just fall back to decomposed shuffles and a blend. This requires
9940 // that the decomposed single-input shuffles don't end up here.
9941 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask, DAG);
9944 /// \brief Lower a vector shuffle crossing multiple 128-bit lanes as
9945 /// a permutation and blend of those lanes.
9947 /// This essentially blends the out-of-lane inputs to each lane into the lane
9948 /// from a permuted copy of the vector. This lowering strategy results in four
9949 /// instructions in the worst case for a single-input cross lane shuffle which
9950 /// is lower than any other fully general cross-lane shuffle strategy I'm aware
9951 /// of. Special cases for each particular shuffle pattern should be handled
9952 /// prior to trying this lowering.
9953 static SDValue lowerVectorShuffleAsLanePermuteAndBlend(SDLoc DL, MVT VT,
9954 SDValue V1, SDValue V2,
9956 SelectionDAG &DAG) {
9957 // FIXME: This should probably be generalized for 512-bit vectors as well.
9958 assert(VT.is256BitVector() && "Only for 256-bit vector shuffles!");
9959 int LaneSize = Mask.size() / 2;
9961 // If there are only inputs from one 128-bit lane, splitting will in fact be
9962 // less expensive. The flags track whether the given lane contains an element
9963 // that crosses to another lane.
9964 bool LaneCrossing[2] = {false, false};
9965 for (int i = 0, Size = Mask.size(); i < Size; ++i)
9966 if (Mask[i] >= 0 && (Mask[i] % Size) / LaneSize != i / LaneSize)
9967 LaneCrossing[(Mask[i] % Size) / LaneSize] = true;
9968 if (!LaneCrossing[0] || !LaneCrossing[1])
9969 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
9971 if (isSingleInputShuffleMask(Mask)) {
9972 SmallVector<int, 32> FlippedBlendMask;
9973 for (int i = 0, Size = Mask.size(); i < Size; ++i)
9974 FlippedBlendMask.push_back(
9975 Mask[i] < 0 ? -1 : (((Mask[i] % Size) / LaneSize == i / LaneSize)
9977 : Mask[i] % LaneSize +
9978 (i / LaneSize) * LaneSize + Size));
9980 // Flip the vector, and blend the results which should now be in-lane. The
9981 // VPERM2X128 mask uses the low 2 bits for the low source and bits 4 and
9982 // 5 for the high source. The value 3 selects the high half of source 2 and
9983 // the value 2 selects the low half of source 2. We only use source 2 to
9984 // allow folding it into a memory operand.
9985 unsigned PERMMask = 3 | 2 << 4;
9986 SDValue Flipped = DAG.getNode(X86ISD::VPERM2X128, DL, VT, DAG.getUNDEF(VT),
9987 V1, DAG.getConstant(PERMMask, DL, MVT::i8));
9988 return DAG.getVectorShuffle(VT, DL, V1, Flipped, FlippedBlendMask);
9991 // This now reduces to two single-input shuffles of V1 and V2 which at worst
9992 // will be handled by the above logic and a blend of the results, much like
9993 // other patterns in AVX.
9994 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask, DAG);
9997 /// \brief Handle lowering 2-lane 128-bit shuffles.
9998 static SDValue lowerV2X128VectorShuffle(SDLoc DL, MVT VT, SDValue V1,
9999 SDValue V2, ArrayRef<int> Mask,
10000 const X86Subtarget *Subtarget,
10001 SelectionDAG &DAG) {
10002 // TODO: If minimizing size and one of the inputs is a zero vector and the
10003 // the zero vector has only one use, we could use a VPERM2X128 to save the
10004 // instruction bytes needed to explicitly generate the zero vector.
10006 // Blends are faster and handle all the non-lane-crossing cases.
10007 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, VT, V1, V2, Mask,
10011 bool IsV1Zero = ISD::isBuildVectorAllZeros(V1.getNode());
10012 bool IsV2Zero = ISD::isBuildVectorAllZeros(V2.getNode());
10014 // If either input operand is a zero vector, use VPERM2X128 because its mask
10015 // allows us to replace the zero input with an implicit zero.
10016 if (!IsV1Zero && !IsV2Zero) {
10017 // Check for patterns which can be matched with a single insert of a 128-bit
10019 bool OnlyUsesV1 = isShuffleEquivalent(V1, V2, Mask, {0, 1, 0, 1});
10020 if (OnlyUsesV1 || isShuffleEquivalent(V1, V2, Mask, {0, 1, 4, 5})) {
10021 MVT SubVT = MVT::getVectorVT(VT.getVectorElementType(),
10022 VT.getVectorNumElements() / 2);
10023 SDValue LoV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT, V1,
10024 DAG.getIntPtrConstant(0, DL));
10025 SDValue HiV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT,
10026 OnlyUsesV1 ? V1 : V2,
10027 DAG.getIntPtrConstant(0, DL));
10028 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LoV, HiV);
10032 // Otherwise form a 128-bit permutation. After accounting for undefs,
10033 // convert the 64-bit shuffle mask selection values into 128-bit
10034 // selection bits by dividing the indexes by 2 and shifting into positions
10035 // defined by a vperm2*128 instruction's immediate control byte.
10037 // The immediate permute control byte looks like this:
10038 // [1:0] - select 128 bits from sources for low half of destination
10040 // [3] - zero low half of destination
10041 // [5:4] - select 128 bits from sources for high half of destination
10043 // [7] - zero high half of destination
10045 int MaskLO = Mask[0];
10046 if (MaskLO == SM_SentinelUndef)
10047 MaskLO = Mask[1] == SM_SentinelUndef ? 0 : Mask[1];
10049 int MaskHI = Mask[2];
10050 if (MaskHI == SM_SentinelUndef)
10051 MaskHI = Mask[3] == SM_SentinelUndef ? 0 : Mask[3];
10053 unsigned PermMask = MaskLO / 2 | (MaskHI / 2) << 4;
10055 // If either input is a zero vector, replace it with an undef input.
10056 // Shuffle mask values < 4 are selecting elements of V1.
10057 // Shuffle mask values >= 4 are selecting elements of V2.
10058 // Adjust each half of the permute mask by clearing the half that was
10059 // selecting the zero vector and setting the zero mask bit.
10061 V1 = DAG.getUNDEF(VT);
10063 PermMask = (PermMask & 0xf0) | 0x08;
10065 PermMask = (PermMask & 0x0f) | 0x80;
10068 V2 = DAG.getUNDEF(VT);
10070 PermMask = (PermMask & 0xf0) | 0x08;
10072 PermMask = (PermMask & 0x0f) | 0x80;
10075 return DAG.getNode(X86ISD::VPERM2X128, DL, VT, V1, V2,
10076 DAG.getConstant(PermMask, DL, MVT::i8));
10079 /// \brief Lower a vector shuffle by first fixing the 128-bit lanes and then
10080 /// shuffling each lane.
10082 /// This will only succeed when the result of fixing the 128-bit lanes results
10083 /// in a single-input non-lane-crossing shuffle with a repeating shuffle mask in
10084 /// each 128-bit lanes. This handles many cases where we can quickly blend away
10085 /// the lane crosses early and then use simpler shuffles within each lane.
10087 /// FIXME: It might be worthwhile at some point to support this without
10088 /// requiring the 128-bit lane-relative shuffles to be repeating, but currently
10089 /// in x86 only floating point has interesting non-repeating shuffles, and even
10090 /// those are still *marginally* more expensive.
10091 static SDValue lowerVectorShuffleByMerging128BitLanes(
10092 SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
10093 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
10094 assert(!isSingleInputShuffleMask(Mask) &&
10095 "This is only useful with multiple inputs.");
10097 int Size = Mask.size();
10098 int LaneSize = 128 / VT.getScalarSizeInBits();
10099 int NumLanes = Size / LaneSize;
10100 assert(NumLanes > 1 && "Only handles 256-bit and wider shuffles.");
10102 // See if we can build a hypothetical 128-bit lane-fixing shuffle mask. Also
10103 // check whether the in-128-bit lane shuffles share a repeating pattern.
10104 SmallVector<int, 4> Lanes;
10105 Lanes.resize(NumLanes, -1);
10106 SmallVector<int, 4> InLaneMask;
10107 InLaneMask.resize(LaneSize, -1);
10108 for (int i = 0; i < Size; ++i) {
10112 int j = i / LaneSize;
10114 if (Lanes[j] < 0) {
10115 // First entry we've seen for this lane.
10116 Lanes[j] = Mask[i] / LaneSize;
10117 } else if (Lanes[j] != Mask[i] / LaneSize) {
10118 // This doesn't match the lane selected previously!
10122 // Check that within each lane we have a consistent shuffle mask.
10123 int k = i % LaneSize;
10124 if (InLaneMask[k] < 0) {
10125 InLaneMask[k] = Mask[i] % LaneSize;
10126 } else if (InLaneMask[k] != Mask[i] % LaneSize) {
10127 // This doesn't fit a repeating in-lane mask.
10132 // First shuffle the lanes into place.
10133 MVT LaneVT = MVT::getVectorVT(VT.isFloatingPoint() ? MVT::f64 : MVT::i64,
10134 VT.getSizeInBits() / 64);
10135 SmallVector<int, 8> LaneMask;
10136 LaneMask.resize(NumLanes * 2, -1);
10137 for (int i = 0; i < NumLanes; ++i)
10138 if (Lanes[i] >= 0) {
10139 LaneMask[2 * i + 0] = 2*Lanes[i] + 0;
10140 LaneMask[2 * i + 1] = 2*Lanes[i] + 1;
10143 V1 = DAG.getBitcast(LaneVT, V1);
10144 V2 = DAG.getBitcast(LaneVT, V2);
10145 SDValue LaneShuffle = DAG.getVectorShuffle(LaneVT, DL, V1, V2, LaneMask);
10147 // Cast it back to the type we actually want.
10148 LaneShuffle = DAG.getBitcast(VT, LaneShuffle);
10150 // Now do a simple shuffle that isn't lane crossing.
10151 SmallVector<int, 8> NewMask;
10152 NewMask.resize(Size, -1);
10153 for (int i = 0; i < Size; ++i)
10155 NewMask[i] = (i / LaneSize) * LaneSize + Mask[i] % LaneSize;
10156 assert(!is128BitLaneCrossingShuffleMask(VT, NewMask) &&
10157 "Must not introduce lane crosses at this point!");
10159 return DAG.getVectorShuffle(VT, DL, LaneShuffle, DAG.getUNDEF(VT), NewMask);
10162 /// \brief Test whether the specified input (0 or 1) is in-place blended by the
10165 /// This returns true if the elements from a particular input are already in the
10166 /// slot required by the given mask and require no permutation.
10167 static bool isShuffleMaskInputInPlace(int Input, ArrayRef<int> Mask) {
10168 assert((Input == 0 || Input == 1) && "Only two inputs to shuffles.");
10169 int Size = Mask.size();
10170 for (int i = 0; i < Size; ++i)
10171 if (Mask[i] >= 0 && Mask[i] / Size == Input && Mask[i] % Size != i)
10177 static SDValue lowerVectorShuffleWithSHUFPD(SDLoc DL, MVT VT,
10178 ArrayRef<int> Mask, SDValue V1,
10179 SDValue V2, SelectionDAG &DAG) {
10181 // Mask for V8F64: 0/1, 8/9, 2/3, 10/11, 4/5, ..
10182 // Mask for V4F64; 0/1, 4/5, 2/3, 6/7..
10183 assert(VT.getScalarSizeInBits() == 64 && "Unexpected data type for VSHUFPD");
10184 int NumElts = VT.getVectorNumElements();
10185 bool ShufpdMask = true;
10186 bool CommutableMask = true;
10187 unsigned Immediate = 0;
10188 for (int i = 0; i < NumElts; ++i) {
10191 int Val = (i & 6) + NumElts * (i & 1);
10192 int CommutVal = (i & 0xe) + NumElts * ((i & 1)^1);
10193 if (Mask[i] < Val || Mask[i] > Val + 1)
10194 ShufpdMask = false;
10195 if (Mask[i] < CommutVal || Mask[i] > CommutVal + 1)
10196 CommutableMask = false;
10197 Immediate |= (Mask[i] % 2) << i;
10200 return DAG.getNode(X86ISD::SHUFP, DL, VT, V1, V2,
10201 DAG.getConstant(Immediate, DL, MVT::i8));
10202 if (CommutableMask)
10203 return DAG.getNode(X86ISD::SHUFP, DL, VT, V2, V1,
10204 DAG.getConstant(Immediate, DL, MVT::i8));
10208 /// \brief Handle lowering of 4-lane 64-bit floating point shuffles.
10210 /// Also ends up handling lowering of 4-lane 64-bit integer shuffles when AVX2
10211 /// isn't available.
10212 static SDValue lowerV4F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10213 const X86Subtarget *Subtarget,
10214 SelectionDAG &DAG) {
10216 assert(V1.getSimpleValueType() == MVT::v4f64 && "Bad operand type!");
10217 assert(V2.getSimpleValueType() == MVT::v4f64 && "Bad operand type!");
10218 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10219 ArrayRef<int> Mask = SVOp->getMask();
10220 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
10222 SmallVector<int, 4> WidenedMask;
10223 if (canWidenShuffleElements(Mask, WidenedMask))
10224 return lowerV2X128VectorShuffle(DL, MVT::v4f64, V1, V2, Mask, Subtarget,
10227 if (isSingleInputShuffleMask(Mask)) {
10228 // Check for being able to broadcast a single element.
10229 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v4f64, V1,
10230 Mask, Subtarget, DAG))
10233 // Use low duplicate instructions for masks that match their pattern.
10234 if (isShuffleEquivalent(V1, V2, Mask, {0, 0, 2, 2}))
10235 return DAG.getNode(X86ISD::MOVDDUP, DL, MVT::v4f64, V1);
10237 if (!is128BitLaneCrossingShuffleMask(MVT::v4f64, Mask)) {
10238 // Non-half-crossing single input shuffles can be lowerid with an
10239 // interleaved permutation.
10240 unsigned VPERMILPMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1) |
10241 ((Mask[2] == 3) << 2) | ((Mask[3] == 3) << 3);
10242 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v4f64, V1,
10243 DAG.getConstant(VPERMILPMask, DL, MVT::i8));
10246 // With AVX2 we have direct support for this permutation.
10247 if (Subtarget->hasAVX2())
10248 return DAG.getNode(X86ISD::VPERMI, DL, MVT::v4f64, V1,
10249 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
10251 // Otherwise, fall back.
10252 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v4f64, V1, V2, Mask,
10256 // Use dedicated unpack instructions for masks that match their pattern.
10258 lowerVectorShuffleWithUNPCK(DL, MVT::v4f64, Mask, V1, V2, DAG))
10261 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4f64, V1, V2, Mask,
10265 // Check if the blend happens to exactly fit that of SHUFPD.
10267 lowerVectorShuffleWithSHUFPD(DL, MVT::v4f64, Mask, V1, V2, DAG))
10270 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10271 // shuffle. However, if we have AVX2 and either inputs are already in place,
10272 // we will be able to shuffle even across lanes the other input in a single
10273 // instruction so skip this pattern.
10274 if (!(Subtarget->hasAVX2() && (isShuffleMaskInputInPlace(0, Mask) ||
10275 isShuffleMaskInputInPlace(1, Mask))))
10276 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10277 DL, MVT::v4f64, V1, V2, Mask, Subtarget, DAG))
10280 // If we have AVX2 then we always want to lower with a blend because an v4 we
10281 // can fully permute the elements.
10282 if (Subtarget->hasAVX2())
10283 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4f64, V1, V2,
10286 // Otherwise fall back on generic lowering.
10287 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v4f64, V1, V2, Mask, DAG);
10290 /// \brief Handle lowering of 4-lane 64-bit integer shuffles.
10292 /// This routine is only called when we have AVX2 and thus a reasonable
10293 /// instruction set for v4i64 shuffling..
10294 static SDValue lowerV4I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10295 const X86Subtarget *Subtarget,
10296 SelectionDAG &DAG) {
10298 assert(V1.getSimpleValueType() == MVT::v4i64 && "Bad operand type!");
10299 assert(V2.getSimpleValueType() == MVT::v4i64 && "Bad operand type!");
10300 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10301 ArrayRef<int> Mask = SVOp->getMask();
10302 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
10303 assert(Subtarget->hasAVX2() && "We can only lower v4i64 with AVX2!");
10305 SmallVector<int, 4> WidenedMask;
10306 if (canWidenShuffleElements(Mask, WidenedMask))
10307 return lowerV2X128VectorShuffle(DL, MVT::v4i64, V1, V2, Mask, Subtarget,
10310 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4i64, V1, V2, Mask,
10314 // Check for being able to broadcast a single element.
10315 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v4i64, V1,
10316 Mask, Subtarget, DAG))
10319 // When the shuffle is mirrored between the 128-bit lanes of the unit, we can
10320 // use lower latency instructions that will operate on both 128-bit lanes.
10321 SmallVector<int, 2> RepeatedMask;
10322 if (is128BitLaneRepeatedShuffleMask(MVT::v4i64, Mask, RepeatedMask)) {
10323 if (isSingleInputShuffleMask(Mask)) {
10324 int PSHUFDMask[] = {-1, -1, -1, -1};
10325 for (int i = 0; i < 2; ++i)
10326 if (RepeatedMask[i] >= 0) {
10327 PSHUFDMask[2 * i] = 2 * RepeatedMask[i];
10328 PSHUFDMask[2 * i + 1] = 2 * RepeatedMask[i] + 1;
10330 return DAG.getBitcast(
10332 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v8i32,
10333 DAG.getBitcast(MVT::v8i32, V1),
10334 getV4X86ShuffleImm8ForMask(PSHUFDMask, DL, DAG)));
10338 // AVX2 provides a direct instruction for permuting a single input across
10340 if (isSingleInputShuffleMask(Mask))
10341 return DAG.getNode(X86ISD::VPERMI, DL, MVT::v4i64, V1,
10342 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
10344 // Try to use shift instructions.
10345 if (SDValue Shift =
10346 lowerVectorShuffleAsShift(DL, MVT::v4i64, V1, V2, Mask, DAG))
10349 // Use dedicated unpack instructions for masks that match their pattern.
10351 lowerVectorShuffleWithUNPCK(DL, MVT::v4i64, Mask, V1, V2, DAG))
10354 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10355 // shuffle. However, if we have AVX2 and either inputs are already in place,
10356 // we will be able to shuffle even across lanes the other input in a single
10357 // instruction so skip this pattern.
10358 if (!(Subtarget->hasAVX2() && (isShuffleMaskInputInPlace(0, Mask) ||
10359 isShuffleMaskInputInPlace(1, Mask))))
10360 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10361 DL, MVT::v4i64, V1, V2, Mask, Subtarget, DAG))
10364 // Otherwise fall back on generic blend lowering.
10365 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4i64, V1, V2,
10369 /// \brief Handle lowering of 8-lane 32-bit floating point shuffles.
10371 /// Also ends up handling lowering of 8-lane 32-bit integer shuffles when AVX2
10372 /// isn't available.
10373 static SDValue lowerV8F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10374 const X86Subtarget *Subtarget,
10375 SelectionDAG &DAG) {
10377 assert(V1.getSimpleValueType() == MVT::v8f32 && "Bad operand type!");
10378 assert(V2.getSimpleValueType() == MVT::v8f32 && "Bad operand type!");
10379 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10380 ArrayRef<int> Mask = SVOp->getMask();
10381 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10383 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8f32, V1, V2, Mask,
10387 // Check for being able to broadcast a single element.
10388 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v8f32, V1,
10389 Mask, Subtarget, DAG))
10392 // If the shuffle mask is repeated in each 128-bit lane, we have many more
10393 // options to efficiently lower the shuffle.
10394 SmallVector<int, 4> RepeatedMask;
10395 if (is128BitLaneRepeatedShuffleMask(MVT::v8f32, Mask, RepeatedMask)) {
10396 assert(RepeatedMask.size() == 4 &&
10397 "Repeated masks must be half the mask width!");
10399 // Use even/odd duplicate instructions for masks that match their pattern.
10400 if (isShuffleEquivalent(V1, V2, Mask, {0, 0, 2, 2, 4, 4, 6, 6}))
10401 return DAG.getNode(X86ISD::MOVSLDUP, DL, MVT::v8f32, V1);
10402 if (isShuffleEquivalent(V1, V2, Mask, {1, 1, 3, 3, 5, 5, 7, 7}))
10403 return DAG.getNode(X86ISD::MOVSHDUP, DL, MVT::v8f32, V1);
10405 if (isSingleInputShuffleMask(Mask))
10406 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v8f32, V1,
10407 getV4X86ShuffleImm8ForMask(RepeatedMask, DL, DAG));
10409 // Use dedicated unpack instructions for masks that match their pattern.
10411 lowerVectorShuffleWithUNPCK(DL, MVT::v8f32, Mask, V1, V2, DAG))
10414 // Otherwise, fall back to a SHUFPS sequence. Here it is important that we
10415 // have already handled any direct blends. We also need to squash the
10416 // repeated mask into a simulated v4f32 mask.
10417 for (int i = 0; i < 4; ++i)
10418 if (RepeatedMask[i] >= 8)
10419 RepeatedMask[i] -= 4;
10420 return lowerVectorShuffleWithSHUFPS(DL, MVT::v8f32, RepeatedMask, V1, V2, DAG);
10423 // If we have a single input shuffle with different shuffle patterns in the
10424 // two 128-bit lanes use the variable mask to VPERMILPS.
10425 if (isSingleInputShuffleMask(Mask)) {
10426 SDValue VPermMask[8];
10427 for (int i = 0; i < 8; ++i)
10428 VPermMask[i] = Mask[i] < 0 ? DAG.getUNDEF(MVT::i32)
10429 : DAG.getConstant(Mask[i], DL, MVT::i32);
10430 if (!is128BitLaneCrossingShuffleMask(MVT::v8f32, Mask))
10431 return DAG.getNode(
10432 X86ISD::VPERMILPV, DL, MVT::v8f32, V1,
10433 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i32, VPermMask));
10435 if (Subtarget->hasAVX2())
10436 return DAG.getNode(
10437 X86ISD::VPERMV, DL, MVT::v8f32,
10438 DAG.getBitcast(MVT::v8f32, DAG.getNode(ISD::BUILD_VECTOR, DL,
10439 MVT::v8i32, VPermMask)),
10442 // Otherwise, fall back.
10443 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v8f32, V1, V2, Mask,
10447 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10449 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10450 DL, MVT::v8f32, V1, V2, Mask, Subtarget, DAG))
10453 // If we have AVX2 then we always want to lower with a blend because at v8 we
10454 // can fully permute the elements.
10455 if (Subtarget->hasAVX2())
10456 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8f32, V1, V2,
10459 // Otherwise fall back on generic lowering.
10460 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v8f32, V1, V2, Mask, DAG);
10463 /// \brief Handle lowering of 8-lane 32-bit integer shuffles.
10465 /// This routine is only called when we have AVX2 and thus a reasonable
10466 /// instruction set for v8i32 shuffling..
10467 static SDValue lowerV8I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10468 const X86Subtarget *Subtarget,
10469 SelectionDAG &DAG) {
10471 assert(V1.getSimpleValueType() == MVT::v8i32 && "Bad operand type!");
10472 assert(V2.getSimpleValueType() == MVT::v8i32 && "Bad operand type!");
10473 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10474 ArrayRef<int> Mask = SVOp->getMask();
10475 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10476 assert(Subtarget->hasAVX2() && "We can only lower v8i32 with AVX2!");
10478 // Whenever we can lower this as a zext, that instruction is strictly faster
10479 // than any alternative. It also allows us to fold memory operands into the
10480 // shuffle in many cases.
10481 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v8i32, V1, V2,
10482 Mask, Subtarget, DAG))
10485 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8i32, V1, V2, Mask,
10489 // Check for being able to broadcast a single element.
10490 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v8i32, V1,
10491 Mask, Subtarget, DAG))
10494 // If the shuffle mask is repeated in each 128-bit lane we can use more
10495 // efficient instructions that mirror the shuffles across the two 128-bit
10497 SmallVector<int, 4> RepeatedMask;
10498 if (is128BitLaneRepeatedShuffleMask(MVT::v8i32, Mask, RepeatedMask)) {
10499 assert(RepeatedMask.size() == 4 && "Unexpected repeated mask size!");
10500 if (isSingleInputShuffleMask(Mask))
10501 return DAG.getNode(X86ISD::PSHUFD, DL, MVT::v8i32, V1,
10502 getV4X86ShuffleImm8ForMask(RepeatedMask, DL, DAG));
10504 // Use dedicated unpack instructions for masks that match their pattern.
10506 lowerVectorShuffleWithUNPCK(DL, MVT::v8i32, Mask, V1, V2, DAG))
10510 // Try to use shift instructions.
10511 if (SDValue Shift =
10512 lowerVectorShuffleAsShift(DL, MVT::v8i32, V1, V2, Mask, DAG))
10515 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
10516 DL, MVT::v8i32, V1, V2, Mask, Subtarget, DAG))
10519 // If the shuffle patterns aren't repeated but it is a single input, directly
10520 // generate a cross-lane VPERMD instruction.
10521 if (isSingleInputShuffleMask(Mask)) {
10522 SDValue VPermMask[8];
10523 for (int i = 0; i < 8; ++i)
10524 VPermMask[i] = Mask[i] < 0 ? DAG.getUNDEF(MVT::i32)
10525 : DAG.getConstant(Mask[i], DL, MVT::i32);
10526 return DAG.getNode(
10527 X86ISD::VPERMV, DL, MVT::v8i32,
10528 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i32, VPermMask), V1);
10531 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10533 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10534 DL, MVT::v8i32, V1, V2, Mask, Subtarget, DAG))
10537 // Otherwise fall back on generic blend lowering.
10538 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8i32, V1, V2,
10542 /// \brief Handle lowering of 16-lane 16-bit integer shuffles.
10544 /// This routine is only called when we have AVX2 and thus a reasonable
10545 /// instruction set for v16i16 shuffling..
10546 static SDValue lowerV16I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10547 const X86Subtarget *Subtarget,
10548 SelectionDAG &DAG) {
10550 assert(V1.getSimpleValueType() == MVT::v16i16 && "Bad operand type!");
10551 assert(V2.getSimpleValueType() == MVT::v16i16 && "Bad operand type!");
10552 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10553 ArrayRef<int> Mask = SVOp->getMask();
10554 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
10555 assert(Subtarget->hasAVX2() && "We can only lower v16i16 with AVX2!");
10557 // Whenever we can lower this as a zext, that instruction is strictly faster
10558 // than any alternative. It also allows us to fold memory operands into the
10559 // shuffle in many cases.
10560 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v16i16, V1, V2,
10561 Mask, Subtarget, DAG))
10564 // Check for being able to broadcast a single element.
10565 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v16i16, V1,
10566 Mask, Subtarget, DAG))
10569 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v16i16, V1, V2, Mask,
10573 // Use dedicated unpack instructions for masks that match their pattern.
10575 lowerVectorShuffleWithUNPCK(DL, MVT::v16i16, Mask, V1, V2, DAG))
10578 // Try to use shift instructions.
10579 if (SDValue Shift =
10580 lowerVectorShuffleAsShift(DL, MVT::v16i16, V1, V2, Mask, DAG))
10583 // Try to use byte rotation instructions.
10584 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
10585 DL, MVT::v16i16, V1, V2, Mask, Subtarget, DAG))
10588 if (isSingleInputShuffleMask(Mask)) {
10589 // There are no generalized cross-lane shuffle operations available on i16
10591 if (is128BitLaneCrossingShuffleMask(MVT::v16i16, Mask))
10592 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v16i16, V1, V2,
10595 SmallVector<int, 8> RepeatedMask;
10596 if (is128BitLaneRepeatedShuffleMask(MVT::v16i16, Mask, RepeatedMask)) {
10597 // As this is a single-input shuffle, the repeated mask should be
10598 // a strictly valid v8i16 mask that we can pass through to the v8i16
10599 // lowering to handle even the v16 case.
10600 return lowerV8I16GeneralSingleInputVectorShuffle(
10601 DL, MVT::v16i16, V1, RepeatedMask, Subtarget, DAG);
10604 SDValue PSHUFBMask[32];
10605 for (int i = 0; i < 16; ++i) {
10606 if (Mask[i] == -1) {
10607 PSHUFBMask[2 * i] = PSHUFBMask[2 * i + 1] = DAG.getUNDEF(MVT::i8);
10611 int M = i < 8 ? Mask[i] : Mask[i] - 8;
10612 assert(M >= 0 && M < 8 && "Invalid single-input mask!");
10613 PSHUFBMask[2 * i] = DAG.getConstant(2 * M, DL, MVT::i8);
10614 PSHUFBMask[2 * i + 1] = DAG.getConstant(2 * M + 1, DL, MVT::i8);
10616 return DAG.getBitcast(MVT::v16i16,
10617 DAG.getNode(X86ISD::PSHUFB, DL, MVT::v32i8,
10618 DAG.getBitcast(MVT::v32i8, V1),
10619 DAG.getNode(ISD::BUILD_VECTOR, DL,
10620 MVT::v32i8, PSHUFBMask)));
10623 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10625 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10626 DL, MVT::v16i16, V1, V2, Mask, Subtarget, DAG))
10629 // Otherwise fall back on generic lowering.
10630 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v16i16, V1, V2, Mask, DAG);
10633 /// \brief Handle lowering of 32-lane 8-bit integer shuffles.
10635 /// This routine is only called when we have AVX2 and thus a reasonable
10636 /// instruction set for v32i8 shuffling..
10637 static SDValue lowerV32I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10638 const X86Subtarget *Subtarget,
10639 SelectionDAG &DAG) {
10641 assert(V1.getSimpleValueType() == MVT::v32i8 && "Bad operand type!");
10642 assert(V2.getSimpleValueType() == MVT::v32i8 && "Bad operand type!");
10643 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10644 ArrayRef<int> Mask = SVOp->getMask();
10645 assert(Mask.size() == 32 && "Unexpected mask size for v32 shuffle!");
10646 assert(Subtarget->hasAVX2() && "We can only lower v32i8 with AVX2!");
10648 // Whenever we can lower this as a zext, that instruction is strictly faster
10649 // than any alternative. It also allows us to fold memory operands into the
10650 // shuffle in many cases.
10651 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v32i8, V1, V2,
10652 Mask, Subtarget, DAG))
10655 // Check for being able to broadcast a single element.
10656 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v32i8, V1,
10657 Mask, Subtarget, DAG))
10660 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v32i8, V1, V2, Mask,
10664 // Use dedicated unpack instructions for masks that match their pattern.
10666 lowerVectorShuffleWithUNPCK(DL, MVT::v32i8, Mask, V1, V2, DAG))
10669 // Try to use shift instructions.
10670 if (SDValue Shift =
10671 lowerVectorShuffleAsShift(DL, MVT::v32i8, V1, V2, Mask, DAG))
10674 // Try to use byte rotation instructions.
10675 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
10676 DL, MVT::v32i8, V1, V2, Mask, Subtarget, DAG))
10679 if (isSingleInputShuffleMask(Mask)) {
10680 // There are no generalized cross-lane shuffle operations available on i8
10682 if (is128BitLaneCrossingShuffleMask(MVT::v32i8, Mask))
10683 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v32i8, V1, V2,
10686 SDValue PSHUFBMask[32];
10687 for (int i = 0; i < 32; ++i)
10690 ? DAG.getUNDEF(MVT::i8)
10691 : DAG.getConstant(Mask[i] < 16 ? Mask[i] : Mask[i] - 16, DL,
10694 return DAG.getNode(
10695 X86ISD::PSHUFB, DL, MVT::v32i8, V1,
10696 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, PSHUFBMask));
10699 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10701 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10702 DL, MVT::v32i8, V1, V2, Mask, Subtarget, DAG))
10705 // Otherwise fall back on generic lowering.
10706 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v32i8, V1, V2, Mask, DAG);
10709 /// \brief High-level routine to lower various 256-bit x86 vector shuffles.
10711 /// This routine either breaks down the specific type of a 256-bit x86 vector
10712 /// shuffle or splits it into two 128-bit shuffles and fuses the results back
10713 /// together based on the available instructions.
10714 static SDValue lower256BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10715 MVT VT, const X86Subtarget *Subtarget,
10716 SelectionDAG &DAG) {
10718 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10719 ArrayRef<int> Mask = SVOp->getMask();
10721 // If we have a single input to the zero element, insert that into V1 if we
10722 // can do so cheaply.
10723 int NumElts = VT.getVectorNumElements();
10724 int NumV2Elements = std::count_if(Mask.begin(), Mask.end(), [NumElts](int M) {
10725 return M >= NumElts;
10728 if (NumV2Elements == 1 && Mask[0] >= NumElts)
10729 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
10730 DL, VT, V1, V2, Mask, Subtarget, DAG))
10733 // There is a really nice hard cut-over between AVX1 and AVX2 that means we
10734 // can check for those subtargets here and avoid much of the subtarget
10735 // querying in the per-vector-type lowering routines. With AVX1 we have
10736 // essentially *zero* ability to manipulate a 256-bit vector with integer
10737 // types. Since we'll use floating point types there eventually, just
10738 // immediately cast everything to a float and operate entirely in that domain.
10739 if (VT.isInteger() && !Subtarget->hasAVX2()) {
10740 int ElementBits = VT.getScalarSizeInBits();
10741 if (ElementBits < 32)
10742 // No floating point type available, decompose into 128-bit vectors.
10743 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
10745 MVT FpVT = MVT::getVectorVT(MVT::getFloatingPointVT(ElementBits),
10746 VT.getVectorNumElements());
10747 V1 = DAG.getBitcast(FpVT, V1);
10748 V2 = DAG.getBitcast(FpVT, V2);
10749 return DAG.getBitcast(VT, DAG.getVectorShuffle(FpVT, DL, V1, V2, Mask));
10752 switch (VT.SimpleTy) {
10754 return lowerV4F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10756 return lowerV4I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10758 return lowerV8F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10760 return lowerV8I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10762 return lowerV16I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
10764 return lowerV32I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
10767 llvm_unreachable("Not a valid 256-bit x86 vector type!");
10771 /// \brief Try to lower a vector shuffle as a 128-bit shuffles.
10772 static SDValue lowerV4X128VectorShuffle(SDLoc DL, MVT VT,
10773 ArrayRef<int> Mask,
10774 SDValue V1, SDValue V2,
10775 SelectionDAG &DAG) {
10776 assert(VT.getScalarSizeInBits() == 64 &&
10777 "Unexpected element type size for 128bit shuffle.");
10779 // To handle 256 bit vector requires VLX and most probably
10780 // function lowerV2X128VectorShuffle() is better solution.
10781 assert(VT.is512BitVector() && "Unexpected vector size for 128bit shuffle.");
10783 SmallVector<int, 4> WidenedMask;
10784 if (!canWidenShuffleElements(Mask, WidenedMask))
10787 // Form a 128-bit permutation.
10788 // Convert the 64-bit shuffle mask selection values into 128-bit selection
10789 // bits defined by a vshuf64x2 instruction's immediate control byte.
10790 unsigned PermMask = 0, Imm = 0;
10791 unsigned ControlBitsNum = WidenedMask.size() / 2;
10793 for (int i = 0, Size = WidenedMask.size(); i < Size; ++i) {
10794 if (WidenedMask[i] == SM_SentinelZero)
10797 // Use first element in place of undef mask.
10798 Imm = (WidenedMask[i] == SM_SentinelUndef) ? 0 : WidenedMask[i];
10799 PermMask |= (Imm % WidenedMask.size()) << (i * ControlBitsNum);
10802 return DAG.getNode(X86ISD::SHUF128, DL, VT, V1, V2,
10803 DAG.getConstant(PermMask, DL, MVT::i8));
10806 static SDValue lowerVectorShuffleWithPERMV(SDLoc DL, MVT VT,
10807 ArrayRef<int> Mask, SDValue V1,
10808 SDValue V2, SelectionDAG &DAG) {
10810 assert(VT.getScalarSizeInBits() >= 16 && "Unexpected data type for PERMV");
10812 MVT MaskEltVT = MVT::getIntegerVT(VT.getScalarSizeInBits());
10813 MVT MaskVecVT = MVT::getVectorVT(MaskEltVT, VT.getVectorNumElements());
10815 SDValue MaskNode = getConstVector(Mask, MaskVecVT, DAG, DL, true);
10816 if (isSingleInputShuffleMask(Mask))
10817 return DAG.getNode(X86ISD::VPERMV, DL, VT, MaskNode, V1);
10819 return DAG.getNode(X86ISD::VPERMV3, DL, VT, V1, MaskNode, V2);
10822 /// \brief Handle lowering of 8-lane 64-bit floating point shuffles.
10823 static SDValue lowerV8F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10824 const X86Subtarget *Subtarget,
10825 SelectionDAG &DAG) {
10827 assert(V1.getSimpleValueType() == MVT::v8f64 && "Bad operand type!");
10828 assert(V2.getSimpleValueType() == MVT::v8f64 && "Bad operand type!");
10829 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10830 ArrayRef<int> Mask = SVOp->getMask();
10831 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10833 if (SDValue Shuf128 =
10834 lowerV4X128VectorShuffle(DL, MVT::v8f64, Mask, V1, V2, DAG))
10837 if (SDValue Unpck =
10838 lowerVectorShuffleWithUNPCK(DL, MVT::v8f64, Mask, V1, V2, DAG))
10841 return lowerVectorShuffleWithPERMV(DL, MVT::v8f64, Mask, V1, V2, DAG);
10844 /// \brief Handle lowering of 16-lane 32-bit floating point shuffles.
10845 static SDValue lowerV16F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10846 const X86Subtarget *Subtarget,
10847 SelectionDAG &DAG) {
10849 assert(V1.getSimpleValueType() == MVT::v16f32 && "Bad operand type!");
10850 assert(V2.getSimpleValueType() == MVT::v16f32 && "Bad operand type!");
10851 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10852 ArrayRef<int> Mask = SVOp->getMask();
10853 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
10855 if (SDValue Unpck =
10856 lowerVectorShuffleWithUNPCK(DL, MVT::v16f32, Mask, V1, V2, DAG))
10859 return lowerVectorShuffleWithPERMV(DL, MVT::v16f32, Mask, V1, V2, DAG);
10862 /// \brief Handle lowering of 8-lane 64-bit integer shuffles.
10863 static SDValue lowerV8I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10864 const X86Subtarget *Subtarget,
10865 SelectionDAG &DAG) {
10867 assert(V1.getSimpleValueType() == MVT::v8i64 && "Bad operand type!");
10868 assert(V2.getSimpleValueType() == MVT::v8i64 && "Bad operand type!");
10869 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10870 ArrayRef<int> Mask = SVOp->getMask();
10871 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10873 if (SDValue Shuf128 =
10874 lowerV4X128VectorShuffle(DL, MVT::v8i64, Mask, V1, V2, DAG))
10877 if (SDValue Unpck =
10878 lowerVectorShuffleWithUNPCK(DL, MVT::v8i64, Mask, V1, V2, DAG))
10881 return lowerVectorShuffleWithPERMV(DL, MVT::v8i64, Mask, V1, V2, DAG);
10884 /// \brief Handle lowering of 16-lane 32-bit integer shuffles.
10885 static SDValue lowerV16I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10886 const X86Subtarget *Subtarget,
10887 SelectionDAG &DAG) {
10889 assert(V1.getSimpleValueType() == MVT::v16i32 && "Bad operand type!");
10890 assert(V2.getSimpleValueType() == MVT::v16i32 && "Bad operand type!");
10891 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10892 ArrayRef<int> Mask = SVOp->getMask();
10893 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
10895 if (SDValue Unpck =
10896 lowerVectorShuffleWithUNPCK(DL, MVT::v16i32, Mask, V1, V2, DAG))
10899 return lowerVectorShuffleWithPERMV(DL, MVT::v16i32, Mask, V1, V2, DAG);
10902 /// \brief Handle lowering of 32-lane 16-bit integer shuffles.
10903 static SDValue lowerV32I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10904 const X86Subtarget *Subtarget,
10905 SelectionDAG &DAG) {
10907 assert(V1.getSimpleValueType() == MVT::v32i16 && "Bad operand type!");
10908 assert(V2.getSimpleValueType() == MVT::v32i16 && "Bad operand type!");
10909 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10910 ArrayRef<int> Mask = SVOp->getMask();
10911 assert(Mask.size() == 32 && "Unexpected mask size for v32 shuffle!");
10912 assert(Subtarget->hasBWI() && "We can only lower v32i16 with AVX-512-BWI!");
10914 return lowerVectorShuffleWithPERMV(DL, MVT::v32i16, Mask, V1, V2, DAG);
10917 /// \brief Handle lowering of 64-lane 8-bit integer shuffles.
10918 static SDValue lowerV64I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10919 const X86Subtarget *Subtarget,
10920 SelectionDAG &DAG) {
10922 assert(V1.getSimpleValueType() == MVT::v64i8 && "Bad operand type!");
10923 assert(V2.getSimpleValueType() == MVT::v64i8 && "Bad operand type!");
10924 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10925 ArrayRef<int> Mask = SVOp->getMask();
10926 assert(Mask.size() == 64 && "Unexpected mask size for v64 shuffle!");
10927 assert(Subtarget->hasBWI() && "We can only lower v64i8 with AVX-512-BWI!");
10929 // FIXME: Implement direct support for this type!
10930 return splitAndLowerVectorShuffle(DL, MVT::v64i8, V1, V2, Mask, DAG);
10933 /// \brief High-level routine to lower various 512-bit x86 vector shuffles.
10935 /// This routine either breaks down the specific type of a 512-bit x86 vector
10936 /// shuffle or splits it into two 256-bit shuffles and fuses the results back
10937 /// together based on the available instructions.
10938 static SDValue lower512BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10939 MVT VT, const X86Subtarget *Subtarget,
10940 SelectionDAG &DAG) {
10942 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10943 ArrayRef<int> Mask = SVOp->getMask();
10944 assert(Subtarget->hasAVX512() &&
10945 "Cannot lower 512-bit vectors w/ basic ISA!");
10947 // Check for being able to broadcast a single element.
10948 if (SDValue Broadcast =
10949 lowerVectorShuffleAsBroadcast(DL, VT, V1, Mask, Subtarget, DAG))
10952 // Dispatch to each element type for lowering. If we don't have supprot for
10953 // specific element type shuffles at 512 bits, immediately split them and
10954 // lower them. Each lowering routine of a given type is allowed to assume that
10955 // the requisite ISA extensions for that element type are available.
10956 switch (VT.SimpleTy) {
10958 return lowerV8F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10960 return lowerV16F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10962 return lowerV8I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10964 return lowerV16I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10966 if (Subtarget->hasBWI())
10967 return lowerV32I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
10970 if (Subtarget->hasBWI())
10971 return lowerV64I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
10975 llvm_unreachable("Not a valid 512-bit x86 vector type!");
10978 // Otherwise fall back on splitting.
10979 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
10982 // Lower vXi1 vector shuffles.
10983 // There is no a dedicated instruction on AVX-512 that shuffles the masks.
10984 // The only way to shuffle bits is to sign-extend the mask vector to SIMD
10985 // vector, shuffle and then truncate it back.
10986 static SDValue lower1BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10987 MVT VT, const X86Subtarget *Subtarget,
10988 SelectionDAG &DAG) {
10990 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10991 ArrayRef<int> Mask = SVOp->getMask();
10992 assert(Subtarget->hasAVX512() &&
10993 "Cannot lower 512-bit vectors w/o basic ISA!");
10995 switch (VT.SimpleTy) {
10997 llvm_unreachable("Expected a vector of i1 elements");
10999 ExtVT = MVT::v2i64;
11002 ExtVT = MVT::v4i32;
11005 ExtVT = MVT::v8i64; // Take 512-bit type, more shuffles on KNL
11008 ExtVT = MVT::v16i32;
11011 ExtVT = MVT::v32i16;
11014 ExtVT = MVT::v64i8;
11018 if (ISD::isBuildVectorAllZeros(V1.getNode()))
11019 V1 = getZeroVector(ExtVT, Subtarget, DAG, DL);
11020 else if (ISD::isBuildVectorAllOnes(V1.getNode()))
11021 V1 = getOnesVector(ExtVT, Subtarget, DAG, DL);
11023 V1 = DAG.getNode(ISD::SIGN_EXTEND, DL, ExtVT, V1);
11026 V2 = DAG.getUNDEF(ExtVT);
11027 else if (ISD::isBuildVectorAllZeros(V2.getNode()))
11028 V2 = getZeroVector(ExtVT, Subtarget, DAG, DL);
11029 else if (ISD::isBuildVectorAllOnes(V2.getNode()))
11030 V2 = getOnesVector(ExtVT, Subtarget, DAG, DL);
11032 V2 = DAG.getNode(ISD::SIGN_EXTEND, DL, ExtVT, V2);
11033 return DAG.getNode(ISD::TRUNCATE, DL, VT,
11034 DAG.getVectorShuffle(ExtVT, DL, V1, V2, Mask));
11036 /// \brief Top-level lowering for x86 vector shuffles.
11038 /// This handles decomposition, canonicalization, and lowering of all x86
11039 /// vector shuffles. Most of the specific lowering strategies are encapsulated
11040 /// above in helper routines. The canonicalization attempts to widen shuffles
11041 /// to involve fewer lanes of wider elements, consolidate symmetric patterns
11042 /// s.t. only one of the two inputs needs to be tested, etc.
11043 static SDValue lowerVectorShuffle(SDValue Op, const X86Subtarget *Subtarget,
11044 SelectionDAG &DAG) {
11045 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11046 ArrayRef<int> Mask = SVOp->getMask();
11047 SDValue V1 = Op.getOperand(0);
11048 SDValue V2 = Op.getOperand(1);
11049 MVT VT = Op.getSimpleValueType();
11050 int NumElements = VT.getVectorNumElements();
11052 bool Is1BitVector = (VT.getVectorElementType() == MVT::i1);
11054 assert((VT.getSizeInBits() != 64 || Is1BitVector) &&
11055 "Can't lower MMX shuffles");
11057 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
11058 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
11059 if (V1IsUndef && V2IsUndef)
11060 return DAG.getUNDEF(VT);
11062 // When we create a shuffle node we put the UNDEF node to second operand,
11063 // but in some cases the first operand may be transformed to UNDEF.
11064 // In this case we should just commute the node.
11066 return DAG.getCommutedVectorShuffle(*SVOp);
11068 // Check for non-undef masks pointing at an undef vector and make the masks
11069 // undef as well. This makes it easier to match the shuffle based solely on
11073 if (M >= NumElements) {
11074 SmallVector<int, 8> NewMask(Mask.begin(), Mask.end());
11075 for (int &M : NewMask)
11076 if (M >= NumElements)
11078 return DAG.getVectorShuffle(VT, dl, V1, V2, NewMask);
11081 // We actually see shuffles that are entirely re-arrangements of a set of
11082 // zero inputs. This mostly happens while decomposing complex shuffles into
11083 // simple ones. Directly lower these as a buildvector of zeros.
11084 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
11085 if (Zeroable.all())
11086 return getZeroVector(VT, Subtarget, DAG, dl);
11088 // Try to collapse shuffles into using a vector type with fewer elements but
11089 // wider element types. We cap this to not form integers or floating point
11090 // elements wider than 64 bits, but it might be interesting to form i128
11091 // integers to handle flipping the low and high halves of AVX 256-bit vectors.
11092 SmallVector<int, 16> WidenedMask;
11093 if (VT.getScalarSizeInBits() < 64 && !Is1BitVector &&
11094 canWidenShuffleElements(Mask, WidenedMask)) {
11095 MVT NewEltVT = VT.isFloatingPoint()
11096 ? MVT::getFloatingPointVT(VT.getScalarSizeInBits() * 2)
11097 : MVT::getIntegerVT(VT.getScalarSizeInBits() * 2);
11098 MVT NewVT = MVT::getVectorVT(NewEltVT, VT.getVectorNumElements() / 2);
11099 // Make sure that the new vector type is legal. For example, v2f64 isn't
11101 if (DAG.getTargetLoweringInfo().isTypeLegal(NewVT)) {
11102 V1 = DAG.getBitcast(NewVT, V1);
11103 V2 = DAG.getBitcast(NewVT, V2);
11104 return DAG.getBitcast(
11105 VT, DAG.getVectorShuffle(NewVT, dl, V1, V2, WidenedMask));
11109 int NumV1Elements = 0, NumUndefElements = 0, NumV2Elements = 0;
11110 for (int M : SVOp->getMask())
11112 ++NumUndefElements;
11113 else if (M < NumElements)
11118 // Commute the shuffle as needed such that more elements come from V1 than
11119 // V2. This allows us to match the shuffle pattern strictly on how many
11120 // elements come from V1 without handling the symmetric cases.
11121 if (NumV2Elements > NumV1Elements)
11122 return DAG.getCommutedVectorShuffle(*SVOp);
11124 // When the number of V1 and V2 elements are the same, try to minimize the
11125 // number of uses of V2 in the low half of the vector. When that is tied,
11126 // ensure that the sum of indices for V1 is equal to or lower than the sum
11127 // indices for V2. When those are equal, try to ensure that the number of odd
11128 // indices for V1 is lower than the number of odd indices for V2.
11129 if (NumV1Elements == NumV2Elements) {
11130 int LowV1Elements = 0, LowV2Elements = 0;
11131 for (int M : SVOp->getMask().slice(0, NumElements / 2))
11132 if (M >= NumElements)
11136 if (LowV2Elements > LowV1Elements) {
11137 return DAG.getCommutedVectorShuffle(*SVOp);
11138 } else if (LowV2Elements == LowV1Elements) {
11139 int SumV1Indices = 0, SumV2Indices = 0;
11140 for (int i = 0, Size = SVOp->getMask().size(); i < Size; ++i)
11141 if (SVOp->getMask()[i] >= NumElements)
11143 else if (SVOp->getMask()[i] >= 0)
11145 if (SumV2Indices < SumV1Indices) {
11146 return DAG.getCommutedVectorShuffle(*SVOp);
11147 } else if (SumV2Indices == SumV1Indices) {
11148 int NumV1OddIndices = 0, NumV2OddIndices = 0;
11149 for (int i = 0, Size = SVOp->getMask().size(); i < Size; ++i)
11150 if (SVOp->getMask()[i] >= NumElements)
11151 NumV2OddIndices += i % 2;
11152 else if (SVOp->getMask()[i] >= 0)
11153 NumV1OddIndices += i % 2;
11154 if (NumV2OddIndices < NumV1OddIndices)
11155 return DAG.getCommutedVectorShuffle(*SVOp);
11160 // For each vector width, delegate to a specialized lowering routine.
11161 if (VT.is128BitVector())
11162 return lower128BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
11164 if (VT.is256BitVector())
11165 return lower256BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
11167 if (VT.is512BitVector())
11168 return lower512BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
11171 return lower1BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
11172 llvm_unreachable("Unimplemented!");
11175 // This function assumes its argument is a BUILD_VECTOR of constants or
11176 // undef SDNodes. i.e: ISD::isBuildVectorOfConstantSDNodes(BuildVector) is
11178 static bool BUILD_VECTORtoBlendMask(BuildVectorSDNode *BuildVector,
11179 unsigned &MaskValue) {
11181 unsigned NumElems = BuildVector->getNumOperands();
11183 // There are 2 lanes if (NumElems > 8), and 1 lane otherwise.
11184 // We don't handle the >2 lanes case right now.
11185 unsigned NumLanes = (NumElems - 1) / 8 + 1;
11189 unsigned NumElemsInLane = NumElems / NumLanes;
11191 // Blend for v16i16 should be symmetric for the both lanes.
11192 for (unsigned i = 0; i < NumElemsInLane; ++i) {
11193 SDValue EltCond = BuildVector->getOperand(i);
11194 SDValue SndLaneEltCond =
11195 (NumLanes == 2) ? BuildVector->getOperand(i + NumElemsInLane) : EltCond;
11197 int Lane1Cond = -1, Lane2Cond = -1;
11198 if (isa<ConstantSDNode>(EltCond))
11199 Lane1Cond = !isZero(EltCond);
11200 if (isa<ConstantSDNode>(SndLaneEltCond))
11201 Lane2Cond = !isZero(SndLaneEltCond);
11203 unsigned LaneMask = 0;
11204 if (Lane1Cond == Lane2Cond || Lane2Cond < 0)
11205 // Lane1Cond != 0, means we want the first argument.
11206 // Lane1Cond == 0, means we want the second argument.
11207 // The encoding of this argument is 0 for the first argument, 1
11208 // for the second. Therefore, invert the condition.
11209 LaneMask = !Lane1Cond << i;
11210 else if (Lane1Cond < 0)
11211 LaneMask = !Lane2Cond << i;
11215 MaskValue |= LaneMask;
11217 MaskValue |= LaneMask << NumElemsInLane;
11222 /// \brief Try to lower a VSELECT instruction to a vector shuffle.
11223 static SDValue lowerVSELECTtoVectorShuffle(SDValue Op,
11224 const X86Subtarget *Subtarget,
11225 SelectionDAG &DAG) {
11226 SDValue Cond = Op.getOperand(0);
11227 SDValue LHS = Op.getOperand(1);
11228 SDValue RHS = Op.getOperand(2);
11230 MVT VT = Op.getSimpleValueType();
11232 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
11234 auto *CondBV = cast<BuildVectorSDNode>(Cond);
11236 // Only non-legal VSELECTs reach this lowering, convert those into generic
11237 // shuffles and re-use the shuffle lowering path for blends.
11238 SmallVector<int, 32> Mask;
11239 for (int i = 0, Size = VT.getVectorNumElements(); i < Size; ++i) {
11240 SDValue CondElt = CondBV->getOperand(i);
11242 isa<ConstantSDNode>(CondElt) ? i + (isZero(CondElt) ? Size : 0) : -1);
11244 return DAG.getVectorShuffle(VT, dl, LHS, RHS, Mask);
11247 SDValue X86TargetLowering::LowerVSELECT(SDValue Op, SelectionDAG &DAG) const {
11248 // A vselect where all conditions and data are constants can be optimized into
11249 // a single vector load by SelectionDAGLegalize::ExpandBUILD_VECTOR().
11250 if (ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(0).getNode()) &&
11251 ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(1).getNode()) &&
11252 ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(2).getNode()))
11255 // Try to lower this to a blend-style vector shuffle. This can handle all
11256 // constant condition cases.
11257 if (SDValue BlendOp = lowerVSELECTtoVectorShuffle(Op, Subtarget, DAG))
11260 // Variable blends are only legal from SSE4.1 onward.
11261 if (!Subtarget->hasSSE41())
11264 // Only some types will be legal on some subtargets. If we can emit a legal
11265 // VSELECT-matching blend, return Op, and but if we need to expand, return
11267 switch (Op.getSimpleValueType().SimpleTy) {
11269 // Most of the vector types have blends past SSE4.1.
11273 // The byte blends for AVX vectors were introduced only in AVX2.
11274 if (Subtarget->hasAVX2())
11281 // AVX-512 BWI and VLX features support VSELECT with i16 elements.
11282 if (Subtarget->hasBWI() && Subtarget->hasVLX())
11285 // FIXME: We should custom lower this by fixing the condition and using i8
11291 static SDValue LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) {
11292 MVT VT = Op.getSimpleValueType();
11295 if (!Op.getOperand(0).getSimpleValueType().is128BitVector())
11298 if (VT.getSizeInBits() == 8) {
11299 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
11300 Op.getOperand(0), Op.getOperand(1));
11301 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
11302 DAG.getValueType(VT));
11303 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
11306 if (VT.getSizeInBits() == 16) {
11307 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
11308 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
11310 return DAG.getNode(
11311 ISD::TRUNCATE, dl, MVT::i16,
11312 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
11313 DAG.getBitcast(MVT::v4i32, Op.getOperand(0)),
11314 Op.getOperand(1)));
11315 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
11316 Op.getOperand(0), Op.getOperand(1));
11317 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
11318 DAG.getValueType(VT));
11319 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
11322 if (VT == MVT::f32) {
11323 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
11324 // the result back to FR32 register. It's only worth matching if the
11325 // result has a single use which is a store or a bitcast to i32. And in
11326 // the case of a store, it's not worth it if the index is a constant 0,
11327 // because a MOVSSmr can be used instead, which is smaller and faster.
11328 if (!Op.hasOneUse())
11330 SDNode *User = *Op.getNode()->use_begin();
11331 if ((User->getOpcode() != ISD::STORE ||
11332 (isa<ConstantSDNode>(Op.getOperand(1)) &&
11333 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
11334 (User->getOpcode() != ISD::BITCAST ||
11335 User->getValueType(0) != MVT::i32))
11337 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
11338 DAG.getBitcast(MVT::v4i32, Op.getOperand(0)),
11340 return DAG.getBitcast(MVT::f32, Extract);
11343 if (VT == MVT::i32 || VT == MVT::i64) {
11344 // ExtractPS/pextrq works with constant index.
11345 if (isa<ConstantSDNode>(Op.getOperand(1)))
11351 /// Extract one bit from mask vector, like v16i1 or v8i1.
11352 /// AVX-512 feature.
11354 X86TargetLowering::ExtractBitFromMaskVector(SDValue Op, SelectionDAG &DAG) const {
11355 SDValue Vec = Op.getOperand(0);
11357 MVT VecVT = Vec.getSimpleValueType();
11358 SDValue Idx = Op.getOperand(1);
11359 MVT EltVT = Op.getSimpleValueType();
11361 assert((EltVT == MVT::i1) && "Unexpected operands in ExtractBitFromMaskVector");
11362 assert((VecVT.getVectorNumElements() <= 16 || Subtarget->hasBWI()) &&
11363 "Unexpected vector type in ExtractBitFromMaskVector");
11365 // variable index can't be handled in mask registers,
11366 // extend vector to VR512
11367 if (!isa<ConstantSDNode>(Idx)) {
11368 MVT ExtVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
11369 SDValue Ext = DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVT, Vec);
11370 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
11371 ExtVT.getVectorElementType(), Ext, Idx);
11372 return DAG.getNode(ISD::TRUNCATE, dl, EltVT, Elt);
11375 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
11376 const TargetRegisterClass* rc = getRegClassFor(VecVT);
11377 if (!Subtarget->hasDQI() && (VecVT.getVectorNumElements() <= 8))
11378 rc = getRegClassFor(MVT::v16i1);
11379 unsigned MaxSift = rc->getSize()*8 - 1;
11380 Vec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, Vec,
11381 DAG.getConstant(MaxSift - IdxVal, dl, MVT::i8));
11382 Vec = DAG.getNode(X86ISD::VSRLI, dl, VecVT, Vec,
11383 DAG.getConstant(MaxSift, dl, MVT::i8));
11384 return DAG.getNode(X86ISD::VEXTRACT, dl, MVT::i1, Vec,
11385 DAG.getIntPtrConstant(0, dl));
11389 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
11390 SelectionDAG &DAG) const {
11392 SDValue Vec = Op.getOperand(0);
11393 MVT VecVT = Vec.getSimpleValueType();
11394 SDValue Idx = Op.getOperand(1);
11396 if (Op.getSimpleValueType() == MVT::i1)
11397 return ExtractBitFromMaskVector(Op, DAG);
11399 if (!isa<ConstantSDNode>(Idx)) {
11400 if (VecVT.is512BitVector() ||
11401 (VecVT.is256BitVector() && Subtarget->hasInt256() &&
11402 VecVT.getVectorElementType().getSizeInBits() == 32)) {
11405 MVT::getIntegerVT(VecVT.getVectorElementType().getSizeInBits());
11406 MVT MaskVT = MVT::getVectorVT(MaskEltVT, VecVT.getSizeInBits() /
11407 MaskEltVT.getSizeInBits());
11409 Idx = DAG.getZExtOrTrunc(Idx, dl, MaskEltVT);
11410 auto PtrVT = getPointerTy(DAG.getDataLayout());
11411 SDValue Mask = DAG.getNode(X86ISD::VINSERT, dl, MaskVT,
11412 getZeroVector(MaskVT, Subtarget, DAG, dl), Idx,
11413 DAG.getConstant(0, dl, PtrVT));
11414 SDValue Perm = DAG.getNode(X86ISD::VPERMV, dl, VecVT, Mask, Vec);
11415 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Perm,
11416 DAG.getConstant(0, dl, PtrVT));
11421 // If this is a 256-bit vector result, first extract the 128-bit vector and
11422 // then extract the element from the 128-bit vector.
11423 if (VecVT.is256BitVector() || VecVT.is512BitVector()) {
11425 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
11426 // Get the 128-bit vector.
11427 Vec = Extract128BitVector(Vec, IdxVal, DAG, dl);
11428 MVT EltVT = VecVT.getVectorElementType();
11430 unsigned ElemsPerChunk = 128 / EltVT.getSizeInBits();
11431 assert(isPowerOf2_32(ElemsPerChunk) && "Elements per chunk not power of 2");
11433 // Find IdxVal modulo ElemsPerChunk. Since ElemsPerChunk is a power of 2
11434 // this can be done with a mask.
11435 IdxVal &= ElemsPerChunk - 1;
11436 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec,
11437 DAG.getConstant(IdxVal, dl, MVT::i32));
11440 assert(VecVT.is128BitVector() && "Unexpected vector length");
11442 if (Subtarget->hasSSE41())
11443 if (SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG))
11446 MVT VT = Op.getSimpleValueType();
11447 // TODO: handle v16i8.
11448 if (VT.getSizeInBits() == 16) {
11449 SDValue Vec = Op.getOperand(0);
11450 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
11452 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
11453 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
11454 DAG.getBitcast(MVT::v4i32, Vec),
11455 Op.getOperand(1)));
11456 // Transform it so it match pextrw which produces a 32-bit result.
11457 MVT EltVT = MVT::i32;
11458 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
11459 Op.getOperand(0), Op.getOperand(1));
11460 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
11461 DAG.getValueType(VT));
11462 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
11465 if (VT.getSizeInBits() == 32) {
11466 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
11470 // SHUFPS the element to the lowest double word, then movss.
11471 int Mask[4] = { static_cast<int>(Idx), -1, -1, -1 };
11472 MVT VVT = Op.getOperand(0).getSimpleValueType();
11473 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
11474 DAG.getUNDEF(VVT), Mask);
11475 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
11476 DAG.getIntPtrConstant(0, dl));
11479 if (VT.getSizeInBits() == 64) {
11480 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
11481 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
11482 // to match extract_elt for f64.
11483 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
11487 // UNPCKHPD the element to the lowest double word, then movsd.
11488 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
11489 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
11490 int Mask[2] = { 1, -1 };
11491 MVT VVT = Op.getOperand(0).getSimpleValueType();
11492 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
11493 DAG.getUNDEF(VVT), Mask);
11494 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
11495 DAG.getIntPtrConstant(0, dl));
11501 /// Insert one bit to mask vector, like v16i1 or v8i1.
11502 /// AVX-512 feature.
11504 X86TargetLowering::InsertBitToMaskVector(SDValue Op, SelectionDAG &DAG) const {
11506 SDValue Vec = Op.getOperand(0);
11507 SDValue Elt = Op.getOperand(1);
11508 SDValue Idx = Op.getOperand(2);
11509 MVT VecVT = Vec.getSimpleValueType();
11511 if (!isa<ConstantSDNode>(Idx)) {
11512 // Non constant index. Extend source and destination,
11513 // insert element and then truncate the result.
11514 MVT ExtVecVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
11515 MVT ExtEltVT = (VecVT == MVT::v8i1 ? MVT::i64 : MVT::i32);
11516 SDValue ExtOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ExtVecVT,
11517 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVecVT, Vec),
11518 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtEltVT, Elt), Idx);
11519 return DAG.getNode(ISD::TRUNCATE, dl, VecVT, ExtOp);
11522 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
11523 SDValue EltInVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Elt);
11525 EltInVec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, EltInVec,
11526 DAG.getConstant(IdxVal, dl, MVT::i8));
11527 if (Vec.getOpcode() == ISD::UNDEF)
11529 return DAG.getNode(ISD::OR, dl, VecVT, Vec, EltInVec);
11532 SDValue X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op,
11533 SelectionDAG &DAG) const {
11534 MVT VT = Op.getSimpleValueType();
11535 MVT EltVT = VT.getVectorElementType();
11537 if (EltVT == MVT::i1)
11538 return InsertBitToMaskVector(Op, DAG);
11541 SDValue N0 = Op.getOperand(0);
11542 SDValue N1 = Op.getOperand(1);
11543 SDValue N2 = Op.getOperand(2);
11544 if (!isa<ConstantSDNode>(N2))
11546 auto *N2C = cast<ConstantSDNode>(N2);
11547 unsigned IdxVal = N2C->getZExtValue();
11549 // If the vector is wider than 128 bits, extract the 128-bit subvector, insert
11550 // into that, and then insert the subvector back into the result.
11551 if (VT.is256BitVector() || VT.is512BitVector()) {
11552 // With a 256-bit vector, we can insert into the zero element efficiently
11553 // using a blend if we have AVX or AVX2 and the right data type.
11554 if (VT.is256BitVector() && IdxVal == 0) {
11555 // TODO: It is worthwhile to cast integer to floating point and back
11556 // and incur a domain crossing penalty if that's what we'll end up
11557 // doing anyway after extracting to a 128-bit vector.
11558 if ((Subtarget->hasAVX() && (EltVT == MVT::f64 || EltVT == MVT::f32)) ||
11559 (Subtarget->hasAVX2() && EltVT == MVT::i32)) {
11560 SDValue N1Vec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, N1);
11561 N2 = DAG.getIntPtrConstant(1, dl);
11562 return DAG.getNode(X86ISD::BLENDI, dl, VT, N0, N1Vec, N2);
11566 // Get the desired 128-bit vector chunk.
11567 SDValue V = Extract128BitVector(N0, IdxVal, DAG, dl);
11569 // Insert the element into the desired chunk.
11570 unsigned NumEltsIn128 = 128 / EltVT.getSizeInBits();
11571 assert(isPowerOf2_32(NumEltsIn128));
11572 // Since NumEltsIn128 is a power of 2 we can use mask instead of modulo.
11573 unsigned IdxIn128 = IdxVal & (NumEltsIn128 - 1);
11575 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V, N1,
11576 DAG.getConstant(IdxIn128, dl, MVT::i32));
11578 // Insert the changed part back into the bigger vector
11579 return Insert128BitVector(N0, V, IdxVal, DAG, dl);
11581 assert(VT.is128BitVector() && "Only 128-bit vector types should be left!");
11583 if (Subtarget->hasSSE41()) {
11584 if (EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) {
11586 if (VT == MVT::v8i16) {
11587 Opc = X86ISD::PINSRW;
11589 assert(VT == MVT::v16i8);
11590 Opc = X86ISD::PINSRB;
11593 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
11595 if (N1.getValueType() != MVT::i32)
11596 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
11597 if (N2.getValueType() != MVT::i32)
11598 N2 = DAG.getIntPtrConstant(IdxVal, dl);
11599 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
11602 if (EltVT == MVT::f32) {
11603 // Bits [7:6] of the constant are the source select. This will always be
11604 // zero here. The DAG Combiner may combine an extract_elt index into
11605 // these bits. For example (insert (extract, 3), 2) could be matched by
11606 // putting the '3' into bits [7:6] of X86ISD::INSERTPS.
11607 // Bits [5:4] of the constant are the destination select. This is the
11608 // value of the incoming immediate.
11609 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
11610 // combine either bitwise AND or insert of float 0.0 to set these bits.
11612 bool MinSize = DAG.getMachineFunction().getFunction()->optForMinSize();
11613 if (IdxVal == 0 && (!MinSize || !MayFoldLoad(N1))) {
11614 // If this is an insertion of 32-bits into the low 32-bits of
11615 // a vector, we prefer to generate a blend with immediate rather
11616 // than an insertps. Blends are simpler operations in hardware and so
11617 // will always have equal or better performance than insertps.
11618 // But if optimizing for size and there's a load folding opportunity,
11619 // generate insertps because blendps does not have a 32-bit memory
11621 N2 = DAG.getIntPtrConstant(1, dl);
11622 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
11623 return DAG.getNode(X86ISD::BLENDI, dl, VT, N0, N1, N2);
11625 N2 = DAG.getIntPtrConstant(IdxVal << 4, dl);
11626 // Create this as a scalar to vector..
11627 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
11628 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
11631 if (EltVT == MVT::i32 || EltVT == MVT::i64) {
11632 // PINSR* works with constant index.
11637 if (EltVT == MVT::i8)
11640 if (EltVT.getSizeInBits() == 16) {
11641 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
11642 // as its second argument.
11643 if (N1.getValueType() != MVT::i32)
11644 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
11645 if (N2.getValueType() != MVT::i32)
11646 N2 = DAG.getIntPtrConstant(IdxVal, dl);
11647 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);
11652 static SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) {
11654 MVT OpVT = Op.getSimpleValueType();
11656 // If this is a 256-bit vector result, first insert into a 128-bit
11657 // vector and then insert into the 256-bit vector.
11658 if (!OpVT.is128BitVector()) {
11659 // Insert into a 128-bit vector.
11660 unsigned SizeFactor = OpVT.getSizeInBits()/128;
11661 MVT VT128 = MVT::getVectorVT(OpVT.getVectorElementType(),
11662 OpVT.getVectorNumElements() / SizeFactor);
11664 Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Op.getOperand(0));
11666 // Insert the 128-bit vector.
11667 return Insert128BitVector(DAG.getUNDEF(OpVT), Op, 0, DAG, dl);
11670 if (OpVT == MVT::v1i64 &&
11671 Op.getOperand(0).getValueType() == MVT::i64)
11672 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
11674 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
11675 assert(OpVT.is128BitVector() && "Expected an SSE type!");
11676 return DAG.getBitcast(
11677 OpVT, DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, AnyExt));
11680 // Lower a node with an EXTRACT_SUBVECTOR opcode. This may result in
11681 // a simple subregister reference or explicit instructions to grab
11682 // upper bits of a vector.
11683 static SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
11684 SelectionDAG &DAG) {
11686 SDValue In = Op.getOperand(0);
11687 SDValue Idx = Op.getOperand(1);
11688 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
11689 MVT ResVT = Op.getSimpleValueType();
11690 MVT InVT = In.getSimpleValueType();
11692 if (Subtarget->hasFp256()) {
11693 if (ResVT.is128BitVector() &&
11694 (InVT.is256BitVector() || InVT.is512BitVector()) &&
11695 isa<ConstantSDNode>(Idx)) {
11696 return Extract128BitVector(In, IdxVal, DAG, dl);
11698 if (ResVT.is256BitVector() && InVT.is512BitVector() &&
11699 isa<ConstantSDNode>(Idx)) {
11700 return Extract256BitVector(In, IdxVal, DAG, dl);
11706 // Lower a node with an INSERT_SUBVECTOR opcode. This may result in a
11707 // simple superregister reference or explicit instructions to insert
11708 // the upper bits of a vector.
11709 static SDValue LowerINSERT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
11710 SelectionDAG &DAG) {
11711 if (!Subtarget->hasAVX())
11715 SDValue Vec = Op.getOperand(0);
11716 SDValue SubVec = Op.getOperand(1);
11717 SDValue Idx = Op.getOperand(2);
11719 if (!isa<ConstantSDNode>(Idx))
11722 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
11723 MVT OpVT = Op.getSimpleValueType();
11724 MVT SubVecVT = SubVec.getSimpleValueType();
11726 // Fold two 16-byte subvector loads into one 32-byte load:
11727 // (insert_subvector (insert_subvector undef, (load addr), 0),
11728 // (load addr + 16), Elts/2)
11730 if ((IdxVal == OpVT.getVectorNumElements() / 2) &&
11731 Vec.getOpcode() == ISD::INSERT_SUBVECTOR &&
11732 OpVT.is256BitVector() && SubVecVT.is128BitVector()) {
11733 auto *Idx2 = dyn_cast<ConstantSDNode>(Vec.getOperand(2));
11734 if (Idx2 && Idx2->getZExtValue() == 0) {
11735 SDValue SubVec2 = Vec.getOperand(1);
11736 // If needed, look through a bitcast to get to the load.
11737 if (SubVec2.getNode() && SubVec2.getOpcode() == ISD::BITCAST)
11738 SubVec2 = SubVec2.getOperand(0);
11740 if (auto *FirstLd = dyn_cast<LoadSDNode>(SubVec2)) {
11742 unsigned Alignment = FirstLd->getAlignment();
11743 unsigned AS = FirstLd->getAddressSpace();
11744 const X86TargetLowering *TLI = Subtarget->getTargetLowering();
11745 if (TLI->allowsMemoryAccess(*DAG.getContext(), DAG.getDataLayout(),
11746 OpVT, AS, Alignment, &Fast) && Fast) {
11747 SDValue Ops[] = { SubVec2, SubVec };
11748 if (SDValue Ld = EltsFromConsecutiveLoads(OpVT, Ops, dl, DAG, false))
11755 if ((OpVT.is256BitVector() || OpVT.is512BitVector()) &&
11756 SubVecVT.is128BitVector())
11757 return Insert128BitVector(Vec, SubVec, IdxVal, DAG, dl);
11759 if (OpVT.is512BitVector() && SubVecVT.is256BitVector())
11760 return Insert256BitVector(Vec, SubVec, IdxVal, DAG, dl);
11762 if (OpVT.getVectorElementType() == MVT::i1) {
11763 if (IdxVal == 0 && Vec.getOpcode() == ISD::UNDEF) // the operation is legal
11765 SDValue ZeroIdx = DAG.getIntPtrConstant(0, dl);
11766 SDValue Undef = DAG.getUNDEF(OpVT);
11767 unsigned NumElems = OpVT.getVectorNumElements();
11768 SDValue ShiftBits = DAG.getConstant(NumElems/2, dl, MVT::i8);
11770 if (IdxVal == OpVT.getVectorNumElements() / 2) {
11771 // Zero upper bits of the Vec
11772 Vec = DAG.getNode(X86ISD::VSHLI, dl, OpVT, Vec, ShiftBits);
11773 Vec = DAG.getNode(X86ISD::VSRLI, dl, OpVT, Vec, ShiftBits);
11775 SDValue Vec2 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, OpVT, Undef,
11777 Vec2 = DAG.getNode(X86ISD::VSHLI, dl, OpVT, Vec2, ShiftBits);
11778 return DAG.getNode(ISD::OR, dl, OpVT, Vec, Vec2);
11781 SDValue Vec2 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, OpVT, Undef,
11783 // Zero upper bits of the Vec2
11784 Vec2 = DAG.getNode(X86ISD::VSHLI, dl, OpVT, Vec2, ShiftBits);
11785 Vec2 = DAG.getNode(X86ISD::VSRLI, dl, OpVT, Vec2, ShiftBits);
11786 // Zero lower bits of the Vec
11787 Vec = DAG.getNode(X86ISD::VSRLI, dl, OpVT, Vec, ShiftBits);
11788 Vec = DAG.getNode(X86ISD::VSHLI, dl, OpVT, Vec, ShiftBits);
11789 // Merge them together
11790 return DAG.getNode(ISD::OR, dl, OpVT, Vec, Vec2);
11796 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
11797 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
11798 // one of the above mentioned nodes. It has to be wrapped because otherwise
11799 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
11800 // be used to form addressing mode. These wrapped nodes will be selected
11803 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
11804 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
11806 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
11807 // global base reg.
11808 unsigned char OpFlag = 0;
11809 unsigned WrapperKind = X86ISD::Wrapper;
11810 CodeModel::Model M = DAG.getTarget().getCodeModel();
11812 if (Subtarget->isPICStyleRIPRel() &&
11813 (M == CodeModel::Small || M == CodeModel::Kernel))
11814 WrapperKind = X86ISD::WrapperRIP;
11815 else if (Subtarget->isPICStyleGOT())
11816 OpFlag = X86II::MO_GOTOFF;
11817 else if (Subtarget->isPICStyleStubPIC())
11818 OpFlag = X86II::MO_PIC_BASE_OFFSET;
11820 auto PtrVT = getPointerTy(DAG.getDataLayout());
11821 SDValue Result = DAG.getTargetConstantPool(
11822 CP->getConstVal(), PtrVT, CP->getAlignment(), CP->getOffset(), OpFlag);
11824 Result = DAG.getNode(WrapperKind, DL, PtrVT, Result);
11825 // With PIC, the address is actually $g + Offset.
11828 DAG.getNode(ISD::ADD, DL, PtrVT,
11829 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), Result);
11835 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
11836 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
11838 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
11839 // global base reg.
11840 unsigned char OpFlag = 0;
11841 unsigned WrapperKind = X86ISD::Wrapper;
11842 CodeModel::Model M = DAG.getTarget().getCodeModel();
11844 if (Subtarget->isPICStyleRIPRel() &&
11845 (M == CodeModel::Small || M == CodeModel::Kernel))
11846 WrapperKind = X86ISD::WrapperRIP;
11847 else if (Subtarget->isPICStyleGOT())
11848 OpFlag = X86II::MO_GOTOFF;
11849 else if (Subtarget->isPICStyleStubPIC())
11850 OpFlag = X86II::MO_PIC_BASE_OFFSET;
11852 auto PtrVT = getPointerTy(DAG.getDataLayout());
11853 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, OpFlag);
11855 Result = DAG.getNode(WrapperKind, DL, PtrVT, Result);
11857 // With PIC, the address is actually $g + Offset.
11860 DAG.getNode(ISD::ADD, DL, PtrVT,
11861 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), Result);
11867 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const {
11868 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
11870 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
11871 // global base reg.
11872 unsigned char OpFlag = 0;
11873 unsigned WrapperKind = X86ISD::Wrapper;
11874 CodeModel::Model M = DAG.getTarget().getCodeModel();
11876 if (Subtarget->isPICStyleRIPRel() &&
11877 (M == CodeModel::Small || M == CodeModel::Kernel)) {
11878 if (Subtarget->isTargetDarwin() || Subtarget->isTargetELF())
11879 OpFlag = X86II::MO_GOTPCREL;
11880 WrapperKind = X86ISD::WrapperRIP;
11881 } else if (Subtarget->isPICStyleGOT()) {
11882 OpFlag = X86II::MO_GOT;
11883 } else if (Subtarget->isPICStyleStubPIC()) {
11884 OpFlag = X86II::MO_DARWIN_NONLAZY_PIC_BASE;
11885 } else if (Subtarget->isPICStyleStubNoDynamic()) {
11886 OpFlag = X86II::MO_DARWIN_NONLAZY;
11889 auto PtrVT = getPointerTy(DAG.getDataLayout());
11890 SDValue Result = DAG.getTargetExternalSymbol(Sym, PtrVT, OpFlag);
11893 Result = DAG.getNode(WrapperKind, DL, PtrVT, Result);
11895 // With PIC, the address is actually $g + Offset.
11896 if (DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
11897 !Subtarget->is64Bit()) {
11899 DAG.getNode(ISD::ADD, DL, PtrVT,
11900 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), Result);
11903 // For symbols that require a load from a stub to get the address, emit the
11905 if (isGlobalStubReference(OpFlag))
11906 Result = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), Result,
11907 MachinePointerInfo::getGOT(DAG.getMachineFunction()),
11908 false, false, false, 0);
11914 X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
11915 // Create the TargetBlockAddressAddress node.
11916 unsigned char OpFlags =
11917 Subtarget->ClassifyBlockAddressReference();
11918 CodeModel::Model M = DAG.getTarget().getCodeModel();
11919 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
11920 int64_t Offset = cast<BlockAddressSDNode>(Op)->getOffset();
11922 auto PtrVT = getPointerTy(DAG.getDataLayout());
11923 SDValue Result = DAG.getTargetBlockAddress(BA, PtrVT, Offset, OpFlags);
11925 if (Subtarget->isPICStyleRIPRel() &&
11926 (M == CodeModel::Small || M == CodeModel::Kernel))
11927 Result = DAG.getNode(X86ISD::WrapperRIP, dl, PtrVT, Result);
11929 Result = DAG.getNode(X86ISD::Wrapper, dl, PtrVT, Result);
11931 // With PIC, the address is actually $g + Offset.
11932 if (isGlobalRelativeToPICBase(OpFlags)) {
11933 Result = DAG.getNode(ISD::ADD, dl, PtrVT,
11934 DAG.getNode(X86ISD::GlobalBaseReg, dl, PtrVT), Result);
11941 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, SDLoc dl,
11942 int64_t Offset, SelectionDAG &DAG) const {
11943 // Create the TargetGlobalAddress node, folding in the constant
11944 // offset if it is legal.
11945 unsigned char OpFlags =
11946 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget());
11947 CodeModel::Model M = DAG.getTarget().getCodeModel();
11948 auto PtrVT = getPointerTy(DAG.getDataLayout());
11950 if (OpFlags == X86II::MO_NO_FLAG &&
11951 X86::isOffsetSuitableForCodeModel(Offset, M)) {
11952 // A direct static reference to a global.
11953 Result = DAG.getTargetGlobalAddress(GV, dl, PtrVT, Offset);
11956 Result = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, OpFlags);
11959 if (Subtarget->isPICStyleRIPRel() &&
11960 (M == CodeModel::Small || M == CodeModel::Kernel))
11961 Result = DAG.getNode(X86ISD::WrapperRIP, dl, PtrVT, Result);
11963 Result = DAG.getNode(X86ISD::Wrapper, dl, PtrVT, Result);
11965 // With PIC, the address is actually $g + Offset.
11966 if (isGlobalRelativeToPICBase(OpFlags)) {
11967 Result = DAG.getNode(ISD::ADD, dl, PtrVT,
11968 DAG.getNode(X86ISD::GlobalBaseReg, dl, PtrVT), Result);
11971 // For globals that require a load from a stub to get the address, emit the
11973 if (isGlobalStubReference(OpFlags))
11974 Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Result,
11975 MachinePointerInfo::getGOT(DAG.getMachineFunction()),
11976 false, false, false, 0);
11978 // If there was a non-zero offset that we didn't fold, create an explicit
11979 // addition for it.
11981 Result = DAG.getNode(ISD::ADD, dl, PtrVT, Result,
11982 DAG.getConstant(Offset, dl, PtrVT));
11988 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
11989 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
11990 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
11991 return LowerGlobalAddress(GV, SDLoc(Op), Offset, DAG);
11995 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
11996 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg,
11997 unsigned char OperandFlags, bool LocalDynamic = false) {
11998 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
11999 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
12001 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
12002 GA->getValueType(0),
12006 X86ISD::NodeType CallType = LocalDynamic ? X86ISD::TLSBASEADDR
12010 SDValue Ops[] = { Chain, TGA, *InFlag };
12011 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
12013 SDValue Ops[] = { Chain, TGA };
12014 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
12017 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
12018 MFI->setAdjustsStack(true);
12019 MFI->setHasCalls(true);
12021 SDValue Flag = Chain.getValue(1);
12022 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
12025 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
12027 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
12030 SDLoc dl(GA); // ? function entry point might be better
12031 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
12032 DAG.getNode(X86ISD::GlobalBaseReg,
12033 SDLoc(), PtrVT), InFlag);
12034 InFlag = Chain.getValue(1);
12036 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
12039 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
12041 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
12043 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT,
12044 X86::RAX, X86II::MO_TLSGD);
12047 static SDValue LowerToTLSLocalDynamicModel(GlobalAddressSDNode *GA,
12053 // Get the start address of the TLS block for this module.
12054 X86MachineFunctionInfo* MFI = DAG.getMachineFunction()
12055 .getInfo<X86MachineFunctionInfo>();
12056 MFI->incNumLocalDynamicTLSAccesses();
12060 Base = GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT, X86::RAX,
12061 X86II::MO_TLSLD, /*LocalDynamic=*/true);
12064 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
12065 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), InFlag);
12066 InFlag = Chain.getValue(1);
12067 Base = GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX,
12068 X86II::MO_TLSLDM, /*LocalDynamic=*/true);
12071 // Note: the CleanupLocalDynamicTLSPass will remove redundant computations
12075 unsigned char OperandFlags = X86II::MO_DTPOFF;
12076 unsigned WrapperKind = X86ISD::Wrapper;
12077 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
12078 GA->getValueType(0),
12079 GA->getOffset(), OperandFlags);
12080 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
12082 // Add x@dtpoff with the base.
12083 return DAG.getNode(ISD::ADD, dl, PtrVT, Offset, Base);
12086 // Lower ISD::GlobalTLSAddress using the "initial exec" or "local exec" model.
12087 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
12088 const EVT PtrVT, TLSModel::Model model,
12089 bool is64Bit, bool isPIC) {
12092 // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit).
12093 Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(*DAG.getContext(),
12094 is64Bit ? 257 : 256));
12096 SDValue ThreadPointer =
12097 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), DAG.getIntPtrConstant(0, dl),
12098 MachinePointerInfo(Ptr), false, false, false, 0);
12100 unsigned char OperandFlags = 0;
12101 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
12103 unsigned WrapperKind = X86ISD::Wrapper;
12104 if (model == TLSModel::LocalExec) {
12105 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
12106 } else if (model == TLSModel::InitialExec) {
12108 OperandFlags = X86II::MO_GOTTPOFF;
12109 WrapperKind = X86ISD::WrapperRIP;
12111 OperandFlags = isPIC ? X86II::MO_GOTNTPOFF : X86II::MO_INDNTPOFF;
12114 llvm_unreachable("Unexpected model");
12117 // emit "addl x@ntpoff,%eax" (local exec)
12118 // or "addl x@indntpoff,%eax" (initial exec)
12119 // or "addl x@gotntpoff(%ebx) ,%eax" (initial exec, 32-bit pic)
12121 DAG.getTargetGlobalAddress(GA->getGlobal(), dl, GA->getValueType(0),
12122 GA->getOffset(), OperandFlags);
12123 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
12125 if (model == TLSModel::InitialExec) {
12126 if (isPIC && !is64Bit) {
12127 Offset = DAG.getNode(ISD::ADD, dl, PtrVT,
12128 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT),
12132 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
12133 MachinePointerInfo::getGOT(DAG.getMachineFunction()),
12134 false, false, false, 0);
12137 // The address of the thread local variable is the add of the thread
12138 // pointer with the offset of the variable.
12139 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
12143 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
12145 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
12146 const GlobalValue *GV = GA->getGlobal();
12147 auto PtrVT = getPointerTy(DAG.getDataLayout());
12149 if (Subtarget->isTargetELF()) {
12150 if (DAG.getTarget().Options.EmulatedTLS)
12151 return LowerToTLSEmulatedModel(GA, DAG);
12152 TLSModel::Model model = DAG.getTarget().getTLSModel(GV);
12154 case TLSModel::GeneralDynamic:
12155 if (Subtarget->is64Bit())
12156 return LowerToTLSGeneralDynamicModel64(GA, DAG, PtrVT);
12157 return LowerToTLSGeneralDynamicModel32(GA, DAG, PtrVT);
12158 case TLSModel::LocalDynamic:
12159 return LowerToTLSLocalDynamicModel(GA, DAG, PtrVT,
12160 Subtarget->is64Bit());
12161 case TLSModel::InitialExec:
12162 case TLSModel::LocalExec:
12163 return LowerToTLSExecModel(GA, DAG, PtrVT, model, Subtarget->is64Bit(),
12164 DAG.getTarget().getRelocationModel() ==
12167 llvm_unreachable("Unknown TLS model.");
12170 if (Subtarget->isTargetDarwin()) {
12171 // Darwin only has one model of TLS. Lower to that.
12172 unsigned char OpFlag = 0;
12173 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ?
12174 X86ISD::WrapperRIP : X86ISD::Wrapper;
12176 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
12177 // global base reg.
12178 bool PIC32 = (DAG.getTarget().getRelocationModel() == Reloc::PIC_) &&
12179 !Subtarget->is64Bit();
12181 OpFlag = X86II::MO_TLVP_PIC_BASE;
12183 OpFlag = X86II::MO_TLVP;
12185 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL,
12186 GA->getValueType(0),
12187 GA->getOffset(), OpFlag);
12188 SDValue Offset = DAG.getNode(WrapperKind, DL, PtrVT, Result);
12190 // With PIC32, the address is actually $g + Offset.
12192 Offset = DAG.getNode(ISD::ADD, DL, PtrVT,
12193 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT),
12196 // Lowering the machine isd will make sure everything is in the right
12198 SDValue Chain = DAG.getEntryNode();
12199 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
12200 SDValue Args[] = { Chain, Offset };
12201 Chain = DAG.getNode(X86ISD::TLSCALL, DL, NodeTys, Args);
12203 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls.
12204 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
12205 MFI->setAdjustsStack(true);
12207 // And our return value (tls address) is in the standard call return value
12209 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
12210 return DAG.getCopyFromReg(Chain, DL, Reg, PtrVT, Chain.getValue(1));
12213 if (Subtarget->isTargetKnownWindowsMSVC() ||
12214 Subtarget->isTargetWindowsGNU()) {
12215 // Just use the implicit TLS architecture
12216 // Need to generate someting similar to:
12217 // mov rdx, qword [gs:abs 58H]; Load pointer to ThreadLocalStorage
12219 // mov ecx, dword [rel _tls_index]: Load index (from C runtime)
12220 // mov rcx, qword [rdx+rcx*8]
12221 // mov eax, .tls$:tlsvar
12222 // [rax+rcx] contains the address
12223 // Windows 64bit: gs:0x58
12224 // Windows 32bit: fs:__tls_array
12227 SDValue Chain = DAG.getEntryNode();
12229 // Get the Thread Pointer, which is %fs:__tls_array (32-bit) or
12230 // %gs:0x58 (64-bit). On MinGW, __tls_array is not available, so directly
12231 // use its literal value of 0x2C.
12232 Value *Ptr = Constant::getNullValue(Subtarget->is64Bit()
12233 ? Type::getInt8PtrTy(*DAG.getContext(),
12235 : Type::getInt32PtrTy(*DAG.getContext(),
12238 SDValue TlsArray = Subtarget->is64Bit()
12239 ? DAG.getIntPtrConstant(0x58, dl)
12240 : (Subtarget->isTargetWindowsGNU()
12241 ? DAG.getIntPtrConstant(0x2C, dl)
12242 : DAG.getExternalSymbol("_tls_array", PtrVT));
12244 SDValue ThreadPointer =
12245 DAG.getLoad(PtrVT, dl, Chain, TlsArray, MachinePointerInfo(Ptr), false,
12249 if (GV->getThreadLocalMode() == GlobalVariable::LocalExecTLSModel) {
12250 res = ThreadPointer;
12252 // Load the _tls_index variable
12253 SDValue IDX = DAG.getExternalSymbol("_tls_index", PtrVT);
12254 if (Subtarget->is64Bit())
12255 IDX = DAG.getExtLoad(ISD::ZEXTLOAD, dl, PtrVT, Chain, IDX,
12256 MachinePointerInfo(), MVT::i32, false, false,
12259 IDX = DAG.getLoad(PtrVT, dl, Chain, IDX, MachinePointerInfo(), false,
12262 auto &DL = DAG.getDataLayout();
12264 DAG.getConstant(Log2_64_Ceil(DL.getPointerSize()), dl, PtrVT);
12265 IDX = DAG.getNode(ISD::SHL, dl, PtrVT, IDX, Scale);
12267 res = DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, IDX);
12270 res = DAG.getLoad(PtrVT, dl, Chain, res, MachinePointerInfo(), false, false,
12273 // Get the offset of start of .tls section
12274 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
12275 GA->getValueType(0),
12276 GA->getOffset(), X86II::MO_SECREL);
12277 SDValue Offset = DAG.getNode(X86ISD::Wrapper, dl, PtrVT, TGA);
12279 // The address of the thread local variable is the add of the thread
12280 // pointer with the offset of the variable.
12281 return DAG.getNode(ISD::ADD, dl, PtrVT, res, Offset);
12284 llvm_unreachable("TLS not implemented for this target.");
12287 /// LowerShiftParts - Lower SRA_PARTS and friends, which return two i32 values
12288 /// and take a 2 x i32 value to shift plus a shift amount.
12289 static SDValue LowerShiftParts(SDValue Op, SelectionDAG &DAG) {
12290 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
12291 MVT VT = Op.getSimpleValueType();
12292 unsigned VTBits = VT.getSizeInBits();
12294 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
12295 SDValue ShOpLo = Op.getOperand(0);
12296 SDValue ShOpHi = Op.getOperand(1);
12297 SDValue ShAmt = Op.getOperand(2);
12298 // X86ISD::SHLD and X86ISD::SHRD have defined overflow behavior but the
12299 // generic ISD nodes haven't. Insert an AND to be safe, it's optimized away
12301 SDValue SafeShAmt = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
12302 DAG.getConstant(VTBits - 1, dl, MVT::i8));
12303 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
12304 DAG.getConstant(VTBits - 1, dl, MVT::i8))
12305 : DAG.getConstant(0, dl, VT);
12307 SDValue Tmp2, Tmp3;
12308 if (Op.getOpcode() == ISD::SHL_PARTS) {
12309 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
12310 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, SafeShAmt);
12312 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
12313 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, SafeShAmt);
12316 // If the shift amount is larger or equal than the width of a part we can't
12317 // rely on the results of shld/shrd. Insert a test and select the appropriate
12318 // values for large shift amounts.
12319 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
12320 DAG.getConstant(VTBits, dl, MVT::i8));
12321 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
12322 AndNode, DAG.getConstant(0, dl, MVT::i8));
12325 SDValue CC = DAG.getConstant(X86::COND_NE, dl, MVT::i8);
12326 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
12327 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
12329 if (Op.getOpcode() == ISD::SHL_PARTS) {
12330 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
12331 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
12333 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
12334 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
12337 SDValue Ops[2] = { Lo, Hi };
12338 return DAG.getMergeValues(Ops, dl);
12341 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op,
12342 SelectionDAG &DAG) const {
12343 SDValue Src = Op.getOperand(0);
12344 MVT SrcVT = Src.getSimpleValueType();
12345 MVT VT = Op.getSimpleValueType();
12348 if (SrcVT.isVector()) {
12349 if (SrcVT == MVT::v2i32 && VT == MVT::v2f64) {
12350 return DAG.getNode(X86ISD::CVTDQ2PD, dl, VT,
12351 DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v4i32, Src,
12352 DAG.getUNDEF(SrcVT)));
12354 if (SrcVT.getVectorElementType() == MVT::i1) {
12355 MVT IntegerVT = MVT::getVectorVT(MVT::i32, SrcVT.getVectorNumElements());
12356 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
12357 DAG.getNode(ISD::SIGN_EXTEND, dl, IntegerVT, Src));
12362 assert(SrcVT <= MVT::i64 && SrcVT >= MVT::i16 &&
12363 "Unknown SINT_TO_FP to lower!");
12365 // These are really Legal; return the operand so the caller accepts it as
12367 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
12369 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
12370 Subtarget->is64Bit()) {
12374 unsigned Size = SrcVT.getSizeInBits()/8;
12375 MachineFunction &MF = DAG.getMachineFunction();
12376 auto PtrVT = getPointerTy(MF.getDataLayout());
12377 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false);
12378 SDValue StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
12379 SDValue Chain = DAG.getStore(
12380 DAG.getEntryNode(), dl, Op.getOperand(0), StackSlot,
12381 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SSFI), false,
12383 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
12386 SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
12388 SelectionDAG &DAG) const {
12392 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
12394 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Glue);
12396 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
12398 unsigned ByteSize = SrcVT.getSizeInBits()/8;
12400 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(StackSlot);
12401 MachineMemOperand *MMO;
12403 int SSFI = FI->getIndex();
12404 MMO = DAG.getMachineFunction().getMachineMemOperand(
12405 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SSFI),
12406 MachineMemOperand::MOLoad, ByteSize, ByteSize);
12408 MMO = cast<LoadSDNode>(StackSlot)->getMemOperand();
12409 StackSlot = StackSlot.getOperand(1);
12411 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) };
12412 SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG :
12414 Tys, Ops, SrcVT, MMO);
12417 Chain = Result.getValue(1);
12418 SDValue InFlag = Result.getValue(2);
12420 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
12421 // shouldn't be necessary except that RFP cannot be live across
12422 // multiple blocks. When stackifier is fixed, they can be uncoupled.
12423 MachineFunction &MF = DAG.getMachineFunction();
12424 unsigned SSFISize = Op.getValueType().getSizeInBits()/8;
12425 int SSFI = MF.getFrameInfo()->CreateStackObject(SSFISize, SSFISize, false);
12426 auto PtrVT = getPointerTy(MF.getDataLayout());
12427 SDValue StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
12428 Tys = DAG.getVTList(MVT::Other);
12430 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag
12432 MachineMemOperand *MMO = DAG.getMachineFunction().getMachineMemOperand(
12433 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SSFI),
12434 MachineMemOperand::MOStore, SSFISize, SSFISize);
12436 Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys,
12437 Ops, Op.getValueType(), MMO);
12438 Result = DAG.getLoad(
12439 Op.getValueType(), DL, Chain, StackSlot,
12440 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SSFI),
12441 false, false, false, 0);
12447 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
12448 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op,
12449 SelectionDAG &DAG) const {
12450 // This algorithm is not obvious. Here it is what we're trying to output:
12453 punpckldq (c0), %xmm0 // c0: (uint4){ 0x43300000U, 0x45300000U, 0U, 0U }
12454 subpd (c1), %xmm0 // c1: (double2){ 0x1.0p52, 0x1.0p52 * 0x1.0p32 }
12456 haddpd %xmm0, %xmm0
12458 pshufd $0x4e, %xmm0, %xmm1
12464 LLVMContext *Context = DAG.getContext();
12466 // Build some magic constants.
12467 static const uint32_t CV0[] = { 0x43300000, 0x45300000, 0, 0 };
12468 Constant *C0 = ConstantDataVector::get(*Context, CV0);
12469 auto PtrVT = getPointerTy(DAG.getDataLayout());
12470 SDValue CPIdx0 = DAG.getConstantPool(C0, PtrVT, 16);
12472 SmallVector<Constant*,2> CV1;
12474 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
12475 APInt(64, 0x4330000000000000ULL))));
12477 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
12478 APInt(64, 0x4530000000000000ULL))));
12479 Constant *C1 = ConstantVector::get(CV1);
12480 SDValue CPIdx1 = DAG.getConstantPool(C1, PtrVT, 16);
12482 // Load the 64-bit value into an XMM register.
12483 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
12486 DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
12487 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()),
12488 false, false, false, 16);
12490 getUnpackl(DAG, dl, MVT::v4i32, DAG.getBitcast(MVT::v4i32, XR1), CLod0);
12493 DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
12494 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()),
12495 false, false, false, 16);
12496 SDValue XR2F = DAG.getBitcast(MVT::v2f64, Unpck1);
12497 // TODO: Are there any fast-math-flags to propagate here?
12498 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
12501 if (Subtarget->hasSSE3()) {
12502 // FIXME: The 'haddpd' instruction may be slower than 'movhlps + addsd'.
12503 Result = DAG.getNode(X86ISD::FHADD, dl, MVT::v2f64, Sub, Sub);
12505 SDValue S2F = DAG.getBitcast(MVT::v4i32, Sub);
12506 SDValue Shuffle = getTargetShuffleNode(X86ISD::PSHUFD, dl, MVT::v4i32,
12508 Result = DAG.getNode(ISD::FADD, dl, MVT::v2f64,
12509 DAG.getBitcast(MVT::v2f64, Shuffle), Sub);
12512 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Result,
12513 DAG.getIntPtrConstant(0, dl));
12516 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
12517 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op,
12518 SelectionDAG &DAG) const {
12520 // FP constant to bias correct the final result.
12521 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL), dl,
12524 // Load the 32-bit value into an XMM register.
12525 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
12528 // Zero out the upper parts of the register.
12529 Load = getShuffleVectorZeroOrUndef(Load, 0, true, Subtarget, DAG);
12531 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
12532 DAG.getBitcast(MVT::v2f64, Load),
12533 DAG.getIntPtrConstant(0, dl));
12535 // Or the load with the bias.
12536 SDValue Or = DAG.getNode(
12537 ISD::OR, dl, MVT::v2i64,
12538 DAG.getBitcast(MVT::v2i64,
12539 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, Load)),
12540 DAG.getBitcast(MVT::v2i64,
12541 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, Bias)));
12543 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
12544 DAG.getBitcast(MVT::v2f64, Or), DAG.getIntPtrConstant(0, dl));
12546 // Subtract the bias.
12547 // TODO: Are there any fast-math-flags to propagate here?
12548 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
12550 // Handle final rounding.
12551 MVT DestVT = Op.getSimpleValueType();
12553 if (DestVT.bitsLT(MVT::f64))
12554 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
12555 DAG.getIntPtrConstant(0, dl));
12556 if (DestVT.bitsGT(MVT::f64))
12557 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
12559 // Handle final rounding.
12563 static SDValue lowerUINT_TO_FP_vXi32(SDValue Op, SelectionDAG &DAG,
12564 const X86Subtarget &Subtarget) {
12565 // The algorithm is the following:
12566 // #ifdef __SSE4_1__
12567 // uint4 lo = _mm_blend_epi16( v, (uint4) 0x4b000000, 0xaa);
12568 // uint4 hi = _mm_blend_epi16( _mm_srli_epi32(v,16),
12569 // (uint4) 0x53000000, 0xaa);
12571 // uint4 lo = (v & (uint4) 0xffff) | (uint4) 0x4b000000;
12572 // uint4 hi = (v >> 16) | (uint4) 0x53000000;
12574 // float4 fhi = (float4) hi - (0x1.0p39f + 0x1.0p23f);
12575 // return (float4) lo + fhi;
12577 // We shouldn't use it when unsafe-fp-math is enabled though: we might later
12578 // reassociate the two FADDs, and if we do that, the algorithm fails
12579 // spectacularly (PR24512).
12580 // FIXME: If we ever have some kind of Machine FMF, this should be marked
12581 // as non-fast and always be enabled. Why isn't SDAG FMF enough? Because
12582 // there's also the MachineCombiner reassociations happening on Machine IR.
12583 if (DAG.getTarget().Options.UnsafeFPMath)
12587 SDValue V = Op->getOperand(0);
12588 MVT VecIntVT = V.getSimpleValueType();
12589 bool Is128 = VecIntVT == MVT::v4i32;
12590 MVT VecFloatVT = Is128 ? MVT::v4f32 : MVT::v8f32;
12591 // If we convert to something else than the supported type, e.g., to v4f64,
12593 if (VecFloatVT != Op->getSimpleValueType(0))
12596 unsigned NumElts = VecIntVT.getVectorNumElements();
12597 assert((VecIntVT == MVT::v4i32 || VecIntVT == MVT::v8i32) &&
12598 "Unsupported custom type");
12599 assert(NumElts <= 8 && "The size of the constant array must be fixed");
12601 // In the #idef/#else code, we have in common:
12602 // - The vector of constants:
12608 // Create the splat vector for 0x4b000000.
12609 SDValue CstLow = DAG.getConstant(0x4b000000, DL, MVT::i32);
12610 SDValue CstLowArray[] = {CstLow, CstLow, CstLow, CstLow,
12611 CstLow, CstLow, CstLow, CstLow};
12612 SDValue VecCstLow = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
12613 makeArrayRef(&CstLowArray[0], NumElts));
12614 // Create the splat vector for 0x53000000.
12615 SDValue CstHigh = DAG.getConstant(0x53000000, DL, MVT::i32);
12616 SDValue CstHighArray[] = {CstHigh, CstHigh, CstHigh, CstHigh,
12617 CstHigh, CstHigh, CstHigh, CstHigh};
12618 SDValue VecCstHigh = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
12619 makeArrayRef(&CstHighArray[0], NumElts));
12621 // Create the right shift.
12622 SDValue CstShift = DAG.getConstant(16, DL, MVT::i32);
12623 SDValue CstShiftArray[] = {CstShift, CstShift, CstShift, CstShift,
12624 CstShift, CstShift, CstShift, CstShift};
12625 SDValue VecCstShift = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
12626 makeArrayRef(&CstShiftArray[0], NumElts));
12627 SDValue HighShift = DAG.getNode(ISD::SRL, DL, VecIntVT, V, VecCstShift);
12630 if (Subtarget.hasSSE41()) {
12631 MVT VecI16VT = Is128 ? MVT::v8i16 : MVT::v16i16;
12632 // uint4 lo = _mm_blend_epi16( v, (uint4) 0x4b000000, 0xaa);
12633 SDValue VecCstLowBitcast = DAG.getBitcast(VecI16VT, VecCstLow);
12634 SDValue VecBitcast = DAG.getBitcast(VecI16VT, V);
12635 // Low will be bitcasted right away, so do not bother bitcasting back to its
12637 Low = DAG.getNode(X86ISD::BLENDI, DL, VecI16VT, VecBitcast,
12638 VecCstLowBitcast, DAG.getConstant(0xaa, DL, MVT::i32));
12639 // uint4 hi = _mm_blend_epi16( _mm_srli_epi32(v,16),
12640 // (uint4) 0x53000000, 0xaa);
12641 SDValue VecCstHighBitcast = DAG.getBitcast(VecI16VT, VecCstHigh);
12642 SDValue VecShiftBitcast = DAG.getBitcast(VecI16VT, HighShift);
12643 // High will be bitcasted right away, so do not bother bitcasting back to
12644 // its original type.
12645 High = DAG.getNode(X86ISD::BLENDI, DL, VecI16VT, VecShiftBitcast,
12646 VecCstHighBitcast, DAG.getConstant(0xaa, DL, MVT::i32));
12648 SDValue CstMask = DAG.getConstant(0xffff, DL, MVT::i32);
12649 SDValue VecCstMask = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT, CstMask,
12650 CstMask, CstMask, CstMask);
12651 // uint4 lo = (v & (uint4) 0xffff) | (uint4) 0x4b000000;
12652 SDValue LowAnd = DAG.getNode(ISD::AND, DL, VecIntVT, V, VecCstMask);
12653 Low = DAG.getNode(ISD::OR, DL, VecIntVT, LowAnd, VecCstLow);
12655 // uint4 hi = (v >> 16) | (uint4) 0x53000000;
12656 High = DAG.getNode(ISD::OR, DL, VecIntVT, HighShift, VecCstHigh);
12659 // Create the vector constant for -(0x1.0p39f + 0x1.0p23f).
12660 SDValue CstFAdd = DAG.getConstantFP(
12661 APFloat(APFloat::IEEEsingle, APInt(32, 0xD3000080)), DL, MVT::f32);
12662 SDValue CstFAddArray[] = {CstFAdd, CstFAdd, CstFAdd, CstFAdd,
12663 CstFAdd, CstFAdd, CstFAdd, CstFAdd};
12664 SDValue VecCstFAdd = DAG.getNode(ISD::BUILD_VECTOR, DL, VecFloatVT,
12665 makeArrayRef(&CstFAddArray[0], NumElts));
12667 // float4 fhi = (float4) hi - (0x1.0p39f + 0x1.0p23f);
12668 SDValue HighBitcast = DAG.getBitcast(VecFloatVT, High);
12669 // TODO: Are there any fast-math-flags to propagate here?
12671 DAG.getNode(ISD::FADD, DL, VecFloatVT, HighBitcast, VecCstFAdd);
12672 // return (float4) lo + fhi;
12673 SDValue LowBitcast = DAG.getBitcast(VecFloatVT, Low);
12674 return DAG.getNode(ISD::FADD, DL, VecFloatVT, LowBitcast, FHigh);
12677 SDValue X86TargetLowering::lowerUINT_TO_FP_vec(SDValue Op,
12678 SelectionDAG &DAG) const {
12679 SDValue N0 = Op.getOperand(0);
12680 MVT SVT = N0.getSimpleValueType();
12683 switch (SVT.SimpleTy) {
12685 llvm_unreachable("Custom UINT_TO_FP is not supported!");
12690 MVT NVT = MVT::getVectorVT(MVT::i32, SVT.getVectorNumElements());
12691 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
12692 DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, N0));
12696 return lowerUINT_TO_FP_vXi32(Op, DAG, *Subtarget);
12699 assert(Subtarget->hasAVX512());
12700 return DAG.getNode(ISD::UINT_TO_FP, dl, Op.getValueType(),
12701 DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v16i32, N0));
12705 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op,
12706 SelectionDAG &DAG) const {
12707 SDValue N0 = Op.getOperand(0);
12709 auto PtrVT = getPointerTy(DAG.getDataLayout());
12711 if (Op.getSimpleValueType().isVector())
12712 return lowerUINT_TO_FP_vec(Op, DAG);
12714 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't
12715 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
12716 // the optimization here.
12717 if (DAG.SignBitIsZero(N0))
12718 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
12720 MVT SrcVT = N0.getSimpleValueType();
12721 MVT DstVT = Op.getSimpleValueType();
12723 if (Subtarget->hasAVX512() && isScalarFPTypeInSSEReg(DstVT) &&
12724 (SrcVT == MVT::i32 || (SrcVT == MVT::i64 && Subtarget->is64Bit()))) {
12725 // Conversions from unsigned i32 to f32/f64 are legal,
12726 // using VCVTUSI2SS/SD. Same for i64 in 64-bit mode.
12730 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64)
12731 return LowerUINT_TO_FP_i64(Op, DAG);
12732 if (SrcVT == MVT::i32 && X86ScalarSSEf64)
12733 return LowerUINT_TO_FP_i32(Op, DAG);
12734 if (Subtarget->is64Bit() && SrcVT == MVT::i64 && DstVT == MVT::f32)
12737 // Make a 64-bit buffer, and use it to build an FILD.
12738 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
12739 if (SrcVT == MVT::i32) {
12740 SDValue WordOff = DAG.getConstant(4, dl, PtrVT);
12741 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl, PtrVT, StackSlot, WordOff);
12742 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
12743 StackSlot, MachinePointerInfo(),
12745 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, dl, MVT::i32),
12746 OffsetSlot, MachinePointerInfo(),
12748 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
12752 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP");
12753 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
12754 StackSlot, MachinePointerInfo(),
12756 // For i64 source, we need to add the appropriate power of 2 if the input
12757 // was negative. This is the same as the optimization in
12758 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here,
12759 // we must be careful to do the computation in x87 extended precision, not
12760 // in SSE. (The generic code can't know it's OK to do this, or how to.)
12761 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex();
12762 MachineMemOperand *MMO = DAG.getMachineFunction().getMachineMemOperand(
12763 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SSFI),
12764 MachineMemOperand::MOLoad, 8, 8);
12766 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other);
12767 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) };
12768 SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops,
12771 APInt FF(32, 0x5F800000ULL);
12773 // Check whether the sign bit is set.
12774 SDValue SignSet = DAG.getSetCC(
12775 dl, getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), MVT::i64),
12776 Op.getOperand(0), DAG.getConstant(0, dl, MVT::i64), ISD::SETLT);
12778 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
12779 SDValue FudgePtr = DAG.getConstantPool(
12780 ConstantInt::get(*DAG.getContext(), FF.zext(64)), PtrVT);
12782 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
12783 SDValue Zero = DAG.getIntPtrConstant(0, dl);
12784 SDValue Four = DAG.getIntPtrConstant(4, dl);
12785 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
12787 FudgePtr = DAG.getNode(ISD::ADD, dl, PtrVT, FudgePtr, Offset);
12789 // Load the value out, extending it from f32 to f80.
12790 // FIXME: Avoid the extend by constructing the right constant pool?
12791 SDValue Fudge = DAG.getExtLoad(
12792 ISD::EXTLOAD, dl, MVT::f80, DAG.getEntryNode(), FudgePtr,
12793 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()), MVT::f32,
12794 false, false, false, 4);
12795 // Extend everything to 80 bits to force it to be done on x87.
12796 // TODO: Are there any fast-math-flags to propagate here?
12797 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge);
12798 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add,
12799 DAG.getIntPtrConstant(0, dl));
12802 // If the given FP_TO_SINT (IsSigned) or FP_TO_UINT (!IsSigned) operation
12803 // is legal, or has an fp128 or f16 source (which needs to be promoted to f32),
12804 // just return an <SDValue(), SDValue()> pair.
12805 // Otherwise it is assumed to be a conversion from one of f32, f64 or f80
12806 // to i16, i32 or i64, and we lower it to a legal sequence.
12807 // If lowered to the final integer result we return a <result, SDValue()> pair.
12808 // Otherwise we lower it to a sequence ending with a FIST, return a
12809 // <FIST, StackSlot> pair, and the caller is responsible for loading
12810 // the final integer result from StackSlot.
12811 std::pair<SDValue,SDValue>
12812 X86TargetLowering::FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG,
12813 bool IsSigned, bool IsReplace) const {
12816 EVT DstTy = Op.getValueType();
12817 EVT TheVT = Op.getOperand(0).getValueType();
12818 auto PtrVT = getPointerTy(DAG.getDataLayout());
12820 if (TheVT != MVT::f32 && TheVT != MVT::f64 && TheVT != MVT::f80) {
12821 // f16 must be promoted before using the lowering in this routine.
12822 // fp128 does not use this lowering.
12823 return std::make_pair(SDValue(), SDValue());
12826 // If using FIST to compute an unsigned i64, we'll need some fixup
12827 // to handle values above the maximum signed i64. A FIST is always
12828 // used for the 32-bit subtarget, but also for f80 on a 64-bit target.
12829 bool UnsignedFixup = !IsSigned &&
12830 DstTy == MVT::i64 &&
12831 (!Subtarget->is64Bit() ||
12832 !isScalarFPTypeInSSEReg(TheVT));
12834 if (!IsSigned && DstTy != MVT::i64 && !Subtarget->hasAVX512()) {
12835 // Replace the fp-to-uint32 operation with an fp-to-sint64 FIST.
12836 // The low 32 bits of the fist result will have the correct uint32 result.
12837 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
12841 assert(DstTy.getSimpleVT() <= MVT::i64 &&
12842 DstTy.getSimpleVT() >= MVT::i16 &&
12843 "Unknown FP_TO_INT to lower!");
12845 // These are really Legal.
12846 if (DstTy == MVT::i32 &&
12847 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
12848 return std::make_pair(SDValue(), SDValue());
12849 if (Subtarget->is64Bit() &&
12850 DstTy == MVT::i64 &&
12851 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
12852 return std::make_pair(SDValue(), SDValue());
12854 // We lower FP->int64 into FISTP64 followed by a load from a temporary
12856 MachineFunction &MF = DAG.getMachineFunction();
12857 unsigned MemSize = DstTy.getSizeInBits()/8;
12858 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
12859 SDValue StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
12862 switch (DstTy.getSimpleVT().SimpleTy) {
12863 default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
12864 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
12865 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
12866 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
12869 SDValue Chain = DAG.getEntryNode();
12870 SDValue Value = Op.getOperand(0);
12871 SDValue Adjust; // 0x0 or 0x80000000, for result sign bit adjustment.
12873 if (UnsignedFixup) {
12875 // Conversion to unsigned i64 is implemented with a select,
12876 // depending on whether the source value fits in the range
12877 // of a signed i64. Let Thresh be the FP equivalent of
12878 // 0x8000000000000000ULL.
12880 // Adjust i32 = (Value < Thresh) ? 0 : 0x80000000;
12881 // FistSrc = (Value < Thresh) ? Value : (Value - Thresh);
12882 // Fist-to-mem64 FistSrc
12883 // Add 0 or 0x800...0ULL to the 64-bit result, which is equivalent
12884 // to XOR'ing the high 32 bits with Adjust.
12886 // Being a power of 2, Thresh is exactly representable in all FP formats.
12887 // For X87 we'd like to use the smallest FP type for this constant, but
12888 // for DAG type consistency we have to match the FP operand type.
12890 APFloat Thresh(APFloat::IEEEsingle, APInt(32, 0x5f000000));
12891 LLVM_ATTRIBUTE_UNUSED APFloat::opStatus Status = APFloat::opOK;
12892 bool LosesInfo = false;
12893 if (TheVT == MVT::f64)
12894 // The rounding mode is irrelevant as the conversion should be exact.
12895 Status = Thresh.convert(APFloat::IEEEdouble, APFloat::rmNearestTiesToEven,
12897 else if (TheVT == MVT::f80)
12898 Status = Thresh.convert(APFloat::x87DoubleExtended,
12899 APFloat::rmNearestTiesToEven, &LosesInfo);
12901 assert(Status == APFloat::opOK && !LosesInfo &&
12902 "FP conversion should have been exact");
12904 SDValue ThreshVal = DAG.getConstantFP(Thresh, DL, TheVT);
12906 SDValue Cmp = DAG.getSetCC(DL,
12907 getSetCCResultType(DAG.getDataLayout(),
12908 *DAG.getContext(), TheVT),
12909 Value, ThreshVal, ISD::SETLT);
12910 Adjust = DAG.getSelect(DL, MVT::i32, Cmp,
12911 DAG.getConstant(0, DL, MVT::i32),
12912 DAG.getConstant(0x80000000, DL, MVT::i32));
12913 SDValue Sub = DAG.getNode(ISD::FSUB, DL, TheVT, Value, ThreshVal);
12914 Cmp = DAG.getSetCC(DL, getSetCCResultType(DAG.getDataLayout(),
12915 *DAG.getContext(), TheVT),
12916 Value, ThreshVal, ISD::SETLT);
12917 Value = DAG.getSelect(DL, TheVT, Cmp, Value, Sub);
12920 // FIXME This causes a redundant load/store if the SSE-class value is already
12921 // in memory, such as if it is on the callstack.
12922 if (isScalarFPTypeInSSEReg(TheVT)) {
12923 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
12924 Chain = DAG.getStore(Chain, DL, Value, StackSlot,
12925 MachinePointerInfo::getFixedStack(MF, SSFI), false,
12927 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
12929 Chain, StackSlot, DAG.getValueType(TheVT)
12932 MachineMemOperand *MMO =
12933 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(MF, SSFI),
12934 MachineMemOperand::MOLoad, MemSize, MemSize);
12935 Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops, DstTy, MMO);
12936 Chain = Value.getValue(1);
12937 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
12938 StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
12941 MachineMemOperand *MMO =
12942 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(MF, SSFI),
12943 MachineMemOperand::MOStore, MemSize, MemSize);
12945 if (UnsignedFixup) {
12947 // Insert the FIST, load its result as two i32's,
12948 // and XOR the high i32 with Adjust.
12950 SDValue FistOps[] = { Chain, Value, StackSlot };
12951 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
12952 FistOps, DstTy, MMO);
12954 SDValue Low32 = DAG.getLoad(MVT::i32, DL, FIST, StackSlot,
12955 MachinePointerInfo(),
12956 false, false, false, 0);
12957 SDValue HighAddr = DAG.getNode(ISD::ADD, DL, PtrVT, StackSlot,
12958 DAG.getConstant(4, DL, PtrVT));
12960 SDValue High32 = DAG.getLoad(MVT::i32, DL, FIST, HighAddr,
12961 MachinePointerInfo(),
12962 false, false, false, 0);
12963 High32 = DAG.getNode(ISD::XOR, DL, MVT::i32, High32, Adjust);
12965 if (Subtarget->is64Bit()) {
12966 // Join High32 and Low32 into a 64-bit result.
12967 // (High32 << 32) | Low32
12968 Low32 = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64, Low32);
12969 High32 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, High32);
12970 High32 = DAG.getNode(ISD::SHL, DL, MVT::i64, High32,
12971 DAG.getConstant(32, DL, MVT::i8));
12972 SDValue Result = DAG.getNode(ISD::OR, DL, MVT::i64, High32, Low32);
12973 return std::make_pair(Result, SDValue());
12976 SDValue ResultOps[] = { Low32, High32 };
12978 SDValue pair = IsReplace
12979 ? DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, ResultOps)
12980 : DAG.getMergeValues(ResultOps, DL);
12981 return std::make_pair(pair, SDValue());
12983 // Build the FP_TO_INT*_IN_MEM
12984 SDValue Ops[] = { Chain, Value, StackSlot };
12985 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
12987 return std::make_pair(FIST, StackSlot);
12991 static SDValue LowerAVXExtend(SDValue Op, SelectionDAG &DAG,
12992 const X86Subtarget *Subtarget) {
12993 MVT VT = Op->getSimpleValueType(0);
12994 SDValue In = Op->getOperand(0);
12995 MVT InVT = In.getSimpleValueType();
12998 if (VT.is512BitVector() || InVT.getVectorElementType() == MVT::i1)
12999 return DAG.getNode(ISD::ZERO_EXTEND, dl, VT, In);
13001 // Optimize vectors in AVX mode:
13004 // Use vpunpcklwd for 4 lower elements v8i16 -> v4i32.
13005 // Use vpunpckhwd for 4 upper elements v8i16 -> v4i32.
13006 // Concat upper and lower parts.
13009 // Use vpunpckldq for 4 lower elements v4i32 -> v2i64.
13010 // Use vpunpckhdq for 4 upper elements v4i32 -> v2i64.
13011 // Concat upper and lower parts.
13014 if (((VT != MVT::v16i16) || (InVT != MVT::v16i8)) &&
13015 ((VT != MVT::v8i32) || (InVT != MVT::v8i16)) &&
13016 ((VT != MVT::v4i64) || (InVT != MVT::v4i32)))
13019 if (Subtarget->hasInt256())
13020 return DAG.getNode(X86ISD::VZEXT, dl, VT, In);
13022 SDValue ZeroVec = getZeroVector(InVT, Subtarget, DAG, dl);
13023 SDValue Undef = DAG.getUNDEF(InVT);
13024 bool NeedZero = Op.getOpcode() == ISD::ZERO_EXTEND;
13025 SDValue OpLo = getUnpackl(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
13026 SDValue OpHi = getUnpackh(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
13028 MVT HVT = MVT::getVectorVT(VT.getVectorElementType(),
13029 VT.getVectorNumElements()/2);
13031 OpLo = DAG.getBitcast(HVT, OpLo);
13032 OpHi = DAG.getBitcast(HVT, OpHi);
13034 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
13037 static SDValue LowerZERO_EXTEND_AVX512(SDValue Op,
13038 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
13039 MVT VT = Op->getSimpleValueType(0);
13040 SDValue In = Op->getOperand(0);
13041 MVT InVT = In.getSimpleValueType();
13043 unsigned int NumElts = VT.getVectorNumElements();
13044 if (NumElts != 8 && NumElts != 16 && !Subtarget->hasBWI())
13047 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1)
13048 return DAG.getNode(X86ISD::VZEXT, DL, VT, In);
13050 assert(InVT.getVectorElementType() == MVT::i1);
13051 MVT ExtVT = NumElts == 8 ? MVT::v8i64 : MVT::v16i32;
13053 DAG.getConstant(APInt(ExtVT.getScalarSizeInBits(), 1), DL, ExtVT);
13055 DAG.getConstant(APInt::getNullValue(ExtVT.getScalarSizeInBits()), DL, ExtVT);
13057 SDValue V = DAG.getNode(ISD::VSELECT, DL, ExtVT, In, One, Zero);
13058 if (VT.is512BitVector())
13060 return DAG.getNode(X86ISD::VTRUNC, DL, VT, V);
13063 static SDValue LowerANY_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
13064 SelectionDAG &DAG) {
13065 if (Subtarget->hasFp256())
13066 if (SDValue Res = LowerAVXExtend(Op, DAG, Subtarget))
13072 static SDValue LowerZERO_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
13073 SelectionDAG &DAG) {
13075 MVT VT = Op.getSimpleValueType();
13076 SDValue In = Op.getOperand(0);
13077 MVT SVT = In.getSimpleValueType();
13079 if (VT.is512BitVector() || SVT.getVectorElementType() == MVT::i1)
13080 return LowerZERO_EXTEND_AVX512(Op, Subtarget, DAG);
13082 if (Subtarget->hasFp256())
13083 if (SDValue Res = LowerAVXExtend(Op, DAG, Subtarget))
13086 assert(!VT.is256BitVector() || !SVT.is128BitVector() ||
13087 VT.getVectorNumElements() != SVT.getVectorNumElements());
13091 SDValue X86TargetLowering::LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const {
13093 MVT VT = Op.getSimpleValueType();
13094 SDValue In = Op.getOperand(0);
13095 MVT InVT = In.getSimpleValueType();
13097 if (VT == MVT::i1) {
13098 assert((InVT.isInteger() && (InVT.getSizeInBits() <= 64)) &&
13099 "Invalid scalar TRUNCATE operation");
13100 if (InVT.getSizeInBits() >= 32)
13102 In = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, In);
13103 return DAG.getNode(ISD::TRUNCATE, DL, VT, In);
13105 assert(VT.getVectorNumElements() == InVT.getVectorNumElements() &&
13106 "Invalid TRUNCATE operation");
13108 // move vector to mask - truncate solution for SKX
13109 if (VT.getVectorElementType() == MVT::i1) {
13110 if (InVT.is512BitVector() && InVT.getScalarSizeInBits() <= 16 &&
13111 Subtarget->hasBWI())
13112 return Op; // legal, will go to VPMOVB2M, VPMOVW2M
13113 if ((InVT.is256BitVector() || InVT.is128BitVector())
13114 && InVT.getScalarSizeInBits() <= 16 &&
13115 Subtarget->hasBWI() && Subtarget->hasVLX())
13116 return Op; // legal, will go to VPMOVB2M, VPMOVW2M
13117 if (InVT.is512BitVector() && InVT.getScalarSizeInBits() >= 32 &&
13118 Subtarget->hasDQI())
13119 return Op; // legal, will go to VPMOVD2M, VPMOVQ2M
13120 if ((InVT.is256BitVector() || InVT.is128BitVector())
13121 && InVT.getScalarSizeInBits() >= 32 &&
13122 Subtarget->hasDQI() && Subtarget->hasVLX())
13123 return Op; // legal, will go to VPMOVB2M, VPMOVQ2M
13126 if (VT.getVectorElementType() == MVT::i1) {
13127 assert(VT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
13128 unsigned NumElts = InVT.getVectorNumElements();
13129 assert ((NumElts == 8 || NumElts == 16) && "Unexpected vector type");
13130 if (InVT.getSizeInBits() < 512) {
13131 MVT ExtVT = (NumElts == 16)? MVT::v16i32 : MVT::v8i64;
13132 In = DAG.getNode(ISD::SIGN_EXTEND, DL, ExtVT, In);
13137 DAG.getConstant(APInt::getSignBit(InVT.getScalarSizeInBits()), DL, InVT);
13138 SDValue And = DAG.getNode(ISD::AND, DL, InVT, OneV, In);
13139 return DAG.getNode(X86ISD::TESTM, DL, VT, And, And);
13142 // vpmovqb/w/d, vpmovdb/w, vpmovwb
13143 if (Subtarget->hasAVX512()) {
13144 // word to byte only under BWI
13145 if (InVT == MVT::v16i16 && !Subtarget->hasBWI()) // v16i16 -> v16i8
13146 return DAG.getNode(X86ISD::VTRUNC, DL, VT,
13147 DAG.getNode(X86ISD::VSEXT, DL, MVT::v16i32, In));
13148 return DAG.getNode(X86ISD::VTRUNC, DL, VT, In);
13150 if ((VT == MVT::v4i32) && (InVT == MVT::v4i64)) {
13151 // On AVX2, v4i64 -> v4i32 becomes VPERMD.
13152 if (Subtarget->hasInt256()) {
13153 static const int ShufMask[] = {0, 2, 4, 6, -1, -1, -1, -1};
13154 In = DAG.getBitcast(MVT::v8i32, In);
13155 In = DAG.getVectorShuffle(MVT::v8i32, DL, In, DAG.getUNDEF(MVT::v8i32),
13157 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, In,
13158 DAG.getIntPtrConstant(0, DL));
13161 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
13162 DAG.getIntPtrConstant(0, DL));
13163 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
13164 DAG.getIntPtrConstant(2, DL));
13165 OpLo = DAG.getBitcast(MVT::v4i32, OpLo);
13166 OpHi = DAG.getBitcast(MVT::v4i32, OpHi);
13167 static const int ShufMask[] = {0, 2, 4, 6};
13168 return DAG.getVectorShuffle(VT, DL, OpLo, OpHi, ShufMask);
13171 if ((VT == MVT::v8i16) && (InVT == MVT::v8i32)) {
13172 // On AVX2, v8i32 -> v8i16 becomed PSHUFB.
13173 if (Subtarget->hasInt256()) {
13174 In = DAG.getBitcast(MVT::v32i8, In);
13176 SmallVector<SDValue,32> pshufbMask;
13177 for (unsigned i = 0; i < 2; ++i) {
13178 pshufbMask.push_back(DAG.getConstant(0x0, DL, MVT::i8));
13179 pshufbMask.push_back(DAG.getConstant(0x1, DL, MVT::i8));
13180 pshufbMask.push_back(DAG.getConstant(0x4, DL, MVT::i8));
13181 pshufbMask.push_back(DAG.getConstant(0x5, DL, MVT::i8));
13182 pshufbMask.push_back(DAG.getConstant(0x8, DL, MVT::i8));
13183 pshufbMask.push_back(DAG.getConstant(0x9, DL, MVT::i8));
13184 pshufbMask.push_back(DAG.getConstant(0xc, DL, MVT::i8));
13185 pshufbMask.push_back(DAG.getConstant(0xd, DL, MVT::i8));
13186 for (unsigned j = 0; j < 8; ++j)
13187 pshufbMask.push_back(DAG.getConstant(0x80, DL, MVT::i8));
13189 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, pshufbMask);
13190 In = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v32i8, In, BV);
13191 In = DAG.getBitcast(MVT::v4i64, In);
13193 static const int ShufMask[] = {0, 2, -1, -1};
13194 In = DAG.getVectorShuffle(MVT::v4i64, DL, In, DAG.getUNDEF(MVT::v4i64),
13196 In = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
13197 DAG.getIntPtrConstant(0, DL));
13198 return DAG.getBitcast(VT, In);
13201 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
13202 DAG.getIntPtrConstant(0, DL));
13204 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
13205 DAG.getIntPtrConstant(4, DL));
13207 OpLo = DAG.getBitcast(MVT::v16i8, OpLo);
13208 OpHi = DAG.getBitcast(MVT::v16i8, OpHi);
13210 // The PSHUFB mask:
13211 static const int ShufMask1[] = {0, 1, 4, 5, 8, 9, 12, 13,
13212 -1, -1, -1, -1, -1, -1, -1, -1};
13214 SDValue Undef = DAG.getUNDEF(MVT::v16i8);
13215 OpLo = DAG.getVectorShuffle(MVT::v16i8, DL, OpLo, Undef, ShufMask1);
13216 OpHi = DAG.getVectorShuffle(MVT::v16i8, DL, OpHi, Undef, ShufMask1);
13218 OpLo = DAG.getBitcast(MVT::v4i32, OpLo);
13219 OpHi = DAG.getBitcast(MVT::v4i32, OpHi);
13221 // The MOVLHPS Mask:
13222 static const int ShufMask2[] = {0, 1, 4, 5};
13223 SDValue res = DAG.getVectorShuffle(MVT::v4i32, DL, OpLo, OpHi, ShufMask2);
13224 return DAG.getBitcast(MVT::v8i16, res);
13227 // Handle truncation of V256 to V128 using shuffles.
13228 if (!VT.is128BitVector() || !InVT.is256BitVector())
13231 assert(Subtarget->hasFp256() && "256-bit vector without AVX!");
13233 unsigned NumElems = VT.getVectorNumElements();
13234 MVT NVT = MVT::getVectorVT(VT.getVectorElementType(), NumElems * 2);
13236 SmallVector<int, 16> MaskVec(NumElems * 2, -1);
13237 // Prepare truncation shuffle mask
13238 for (unsigned i = 0; i != NumElems; ++i)
13239 MaskVec[i] = i * 2;
13240 SDValue V = DAG.getVectorShuffle(NVT, DL, DAG.getBitcast(NVT, In),
13241 DAG.getUNDEF(NVT), &MaskVec[0]);
13242 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, V,
13243 DAG.getIntPtrConstant(0, DL));
13246 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op,
13247 SelectionDAG &DAG) const {
13248 assert(!Op.getSimpleValueType().isVector());
13250 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
13251 /*IsSigned=*/ true, /*IsReplace=*/ false);
13252 SDValue FIST = Vals.first, StackSlot = Vals.second;
13253 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
13254 if (!FIST.getNode())
13257 if (StackSlot.getNode())
13258 // Load the result.
13259 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
13260 FIST, StackSlot, MachinePointerInfo(),
13261 false, false, false, 0);
13263 // The node is the result.
13267 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op,
13268 SelectionDAG &DAG) const {
13269 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
13270 /*IsSigned=*/ false, /*IsReplace=*/ false);
13271 SDValue FIST = Vals.first, StackSlot = Vals.second;
13272 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
13273 if (!FIST.getNode())
13276 if (StackSlot.getNode())
13277 // Load the result.
13278 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
13279 FIST, StackSlot, MachinePointerInfo(),
13280 false, false, false, 0);
13282 // The node is the result.
13286 static SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) {
13288 MVT VT = Op.getSimpleValueType();
13289 SDValue In = Op.getOperand(0);
13290 MVT SVT = In.getSimpleValueType();
13292 assert(SVT == MVT::v2f32 && "Only customize MVT::v2f32 type legalization!");
13294 return DAG.getNode(X86ISD::VFPEXT, DL, VT,
13295 DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v4f32,
13296 In, DAG.getUNDEF(SVT)));
13299 /// The only differences between FABS and FNEG are the mask and the logic op.
13300 /// FNEG also has a folding opportunity for FNEG(FABS(x)).
13301 static SDValue LowerFABSorFNEG(SDValue Op, SelectionDAG &DAG) {
13302 assert((Op.getOpcode() == ISD::FABS || Op.getOpcode() == ISD::FNEG) &&
13303 "Wrong opcode for lowering FABS or FNEG.");
13305 bool IsFABS = (Op.getOpcode() == ISD::FABS);
13307 // If this is a FABS and it has an FNEG user, bail out to fold the combination
13308 // into an FNABS. We'll lower the FABS after that if it is still in use.
13310 for (SDNode *User : Op->uses())
13311 if (User->getOpcode() == ISD::FNEG)
13315 MVT VT = Op.getSimpleValueType();
13317 // FIXME: Use function attribute "OptimizeForSize" and/or CodeGenOpt::Level to
13318 // decide if we should generate a 16-byte constant mask when we only need 4 or
13319 // 8 bytes for the scalar case.
13325 if (VT.isVector()) {
13327 EltVT = VT.getVectorElementType();
13328 NumElts = VT.getVectorNumElements();
13330 // There are no scalar bitwise logical SSE/AVX instructions, so we
13331 // generate a 16-byte vector constant and logic op even for the scalar case.
13332 // Using a 16-byte mask allows folding the load of the mask with
13333 // the logic op, so it can save (~4 bytes) on code size.
13334 LogicVT = (VT == MVT::f64) ? MVT::v2f64 : MVT::v4f32;
13336 NumElts = (VT == MVT::f64) ? 2 : 4;
13339 unsigned EltBits = EltVT.getSizeInBits();
13340 LLVMContext *Context = DAG.getContext();
13341 // For FABS, mask is 0x7f...; for FNEG, mask is 0x80...
13343 IsFABS ? APInt::getSignedMaxValue(EltBits) : APInt::getSignBit(EltBits);
13344 Constant *C = ConstantInt::get(*Context, MaskElt);
13345 C = ConstantVector::getSplat(NumElts, C);
13346 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13347 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy(DAG.getDataLayout()));
13348 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
13350 DAG.getLoad(LogicVT, dl, DAG.getEntryNode(), CPIdx,
13351 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()),
13352 false, false, false, Alignment);
13354 SDValue Op0 = Op.getOperand(0);
13355 bool IsFNABS = !IsFABS && (Op0.getOpcode() == ISD::FABS);
13357 IsFABS ? X86ISD::FAND : IsFNABS ? X86ISD::FOR : X86ISD::FXOR;
13358 SDValue Operand = IsFNABS ? Op0.getOperand(0) : Op0;
13361 return DAG.getNode(LogicOp, dl, LogicVT, Operand, Mask);
13363 // For the scalar case extend to a 128-bit vector, perform the logic op,
13364 // and extract the scalar result back out.
13365 Operand = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LogicVT, Operand);
13366 SDValue LogicNode = DAG.getNode(LogicOp, dl, LogicVT, Operand, Mask);
13367 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, LogicNode,
13368 DAG.getIntPtrConstant(0, dl));
13371 static SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) {
13372 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13373 LLVMContext *Context = DAG.getContext();
13374 SDValue Op0 = Op.getOperand(0);
13375 SDValue Op1 = Op.getOperand(1);
13377 MVT VT = Op.getSimpleValueType();
13378 MVT SrcVT = Op1.getSimpleValueType();
13380 // If second operand is smaller, extend it first.
13381 if (SrcVT.bitsLT(VT)) {
13382 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
13385 // And if it is bigger, shrink it first.
13386 if (SrcVT.bitsGT(VT)) {
13387 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1, dl));
13391 // At this point the operands and the result should have the same
13392 // type, and that won't be f80 since that is not custom lowered.
13394 const fltSemantics &Sem =
13395 VT == MVT::f64 ? APFloat::IEEEdouble : APFloat::IEEEsingle;
13396 const unsigned SizeInBits = VT.getSizeInBits();
13398 SmallVector<Constant *, 4> CV(
13399 VT == MVT::f64 ? 2 : 4,
13400 ConstantFP::get(*Context, APFloat(Sem, APInt(SizeInBits, 0))));
13402 // First, clear all bits but the sign bit from the second operand (sign).
13403 CV[0] = ConstantFP::get(*Context,
13404 APFloat(Sem, APInt::getHighBitsSet(SizeInBits, 1)));
13405 Constant *C = ConstantVector::get(CV);
13406 auto PtrVT = TLI.getPointerTy(DAG.getDataLayout());
13407 SDValue CPIdx = DAG.getConstantPool(C, PtrVT, 16);
13409 // Perform all logic operations as 16-byte vectors because there are no
13410 // scalar FP logic instructions in SSE. This allows load folding of the
13411 // constants into the logic instructions.
13412 MVT LogicVT = (VT == MVT::f64) ? MVT::v2f64 : MVT::v4f32;
13414 DAG.getLoad(LogicVT, dl, DAG.getEntryNode(), CPIdx,
13415 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()),
13416 false, false, false, 16);
13417 Op1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LogicVT, Op1);
13418 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, LogicVT, Op1, Mask1);
13420 // Next, clear the sign bit from the first operand (magnitude).
13421 // If it's a constant, we can clear it here.
13422 if (ConstantFPSDNode *Op0CN = dyn_cast<ConstantFPSDNode>(Op0)) {
13423 APFloat APF = Op0CN->getValueAPF();
13424 // If the magnitude is a positive zero, the sign bit alone is enough.
13425 if (APF.isPosZero())
13426 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SrcVT, SignBit,
13427 DAG.getIntPtrConstant(0, dl));
13429 CV[0] = ConstantFP::get(*Context, APF);
13431 CV[0] = ConstantFP::get(
13433 APFloat(Sem, APInt::getLowBitsSet(SizeInBits, SizeInBits - 1)));
13435 C = ConstantVector::get(CV);
13436 CPIdx = DAG.getConstantPool(C, PtrVT, 16);
13438 DAG.getLoad(LogicVT, dl, DAG.getEntryNode(), CPIdx,
13439 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()),
13440 false, false, false, 16);
13441 // If the magnitude operand wasn't a constant, we need to AND out the sign.
13442 if (!isa<ConstantFPSDNode>(Op0)) {
13443 Op0 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LogicVT, Op0);
13444 Val = DAG.getNode(X86ISD::FAND, dl, LogicVT, Op0, Val);
13446 // OR the magnitude value with the sign bit.
13447 Val = DAG.getNode(X86ISD::FOR, dl, LogicVT, Val, SignBit);
13448 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SrcVT, Val,
13449 DAG.getIntPtrConstant(0, dl));
13452 static SDValue LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) {
13453 SDValue N0 = Op.getOperand(0);
13455 MVT VT = Op.getSimpleValueType();
13457 // Lower ISD::FGETSIGN to (AND (X86ISD::FGETSIGNx86 ...) 1).
13458 SDValue xFGETSIGN = DAG.getNode(X86ISD::FGETSIGNx86, dl, VT, N0,
13459 DAG.getConstant(1, dl, VT));
13460 return DAG.getNode(ISD::AND, dl, VT, xFGETSIGN, DAG.getConstant(1, dl, VT));
13463 // Check whether an OR'd tree is PTEST-able.
13464 static SDValue LowerVectorAllZeroTest(SDValue Op, const X86Subtarget *Subtarget,
13465 SelectionDAG &DAG) {
13466 assert(Op.getOpcode() == ISD::OR && "Only check OR'd tree.");
13468 if (!Subtarget->hasSSE41())
13471 if (!Op->hasOneUse())
13474 SDNode *N = Op.getNode();
13477 SmallVector<SDValue, 8> Opnds;
13478 DenseMap<SDValue, unsigned> VecInMap;
13479 SmallVector<SDValue, 8> VecIns;
13480 EVT VT = MVT::Other;
13482 // Recognize a special case where a vector is casted into wide integer to
13484 Opnds.push_back(N->getOperand(0));
13485 Opnds.push_back(N->getOperand(1));
13487 for (unsigned Slot = 0, e = Opnds.size(); Slot < e; ++Slot) {
13488 SmallVectorImpl<SDValue>::const_iterator I = Opnds.begin() + Slot;
13489 // BFS traverse all OR'd operands.
13490 if (I->getOpcode() == ISD::OR) {
13491 Opnds.push_back(I->getOperand(0));
13492 Opnds.push_back(I->getOperand(1));
13493 // Re-evaluate the number of nodes to be traversed.
13494 e += 2; // 2 more nodes (LHS and RHS) are pushed.
13498 // Quit if a non-EXTRACT_VECTOR_ELT
13499 if (I->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
13502 // Quit if without a constant index.
13503 SDValue Idx = I->getOperand(1);
13504 if (!isa<ConstantSDNode>(Idx))
13507 SDValue ExtractedFromVec = I->getOperand(0);
13508 DenseMap<SDValue, unsigned>::iterator M = VecInMap.find(ExtractedFromVec);
13509 if (M == VecInMap.end()) {
13510 VT = ExtractedFromVec.getValueType();
13511 // Quit if not 128/256-bit vector.
13512 if (!VT.is128BitVector() && !VT.is256BitVector())
13514 // Quit if not the same type.
13515 if (VecInMap.begin() != VecInMap.end() &&
13516 VT != VecInMap.begin()->first.getValueType())
13518 M = VecInMap.insert(std::make_pair(ExtractedFromVec, 0)).first;
13519 VecIns.push_back(ExtractedFromVec);
13521 M->second |= 1U << cast<ConstantSDNode>(Idx)->getZExtValue();
13524 assert((VT.is128BitVector() || VT.is256BitVector()) &&
13525 "Not extracted from 128-/256-bit vector.");
13527 unsigned FullMask = (1U << VT.getVectorNumElements()) - 1U;
13529 for (DenseMap<SDValue, unsigned>::const_iterator
13530 I = VecInMap.begin(), E = VecInMap.end(); I != E; ++I) {
13531 // Quit if not all elements are used.
13532 if (I->second != FullMask)
13536 MVT TestVT = VT.is128BitVector() ? MVT::v2i64 : MVT::v4i64;
13538 // Cast all vectors into TestVT for PTEST.
13539 for (unsigned i = 0, e = VecIns.size(); i < e; ++i)
13540 VecIns[i] = DAG.getBitcast(TestVT, VecIns[i]);
13542 // If more than one full vectors are evaluated, OR them first before PTEST.
13543 for (unsigned Slot = 0, e = VecIns.size(); e - Slot > 1; Slot += 2, e += 1) {
13544 // Each iteration will OR 2 nodes and append the result until there is only
13545 // 1 node left, i.e. the final OR'd value of all vectors.
13546 SDValue LHS = VecIns[Slot];
13547 SDValue RHS = VecIns[Slot + 1];
13548 VecIns.push_back(DAG.getNode(ISD::OR, DL, TestVT, LHS, RHS));
13551 return DAG.getNode(X86ISD::PTEST, DL, MVT::i32,
13552 VecIns.back(), VecIns.back());
13555 /// \brief return true if \c Op has a use that doesn't just read flags.
13556 static bool hasNonFlagsUse(SDValue Op) {
13557 for (SDNode::use_iterator UI = Op->use_begin(), UE = Op->use_end(); UI != UE;
13559 SDNode *User = *UI;
13560 unsigned UOpNo = UI.getOperandNo();
13561 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
13562 // Look pass truncate.
13563 UOpNo = User->use_begin().getOperandNo();
13564 User = *User->use_begin();
13567 if (User->getOpcode() != ISD::BRCOND && User->getOpcode() != ISD::SETCC &&
13568 !(User->getOpcode() == ISD::SELECT && UOpNo == 0))
13574 /// Emit nodes that will be selected as "test Op0,Op0", or something
13576 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC, SDLoc dl,
13577 SelectionDAG &DAG) const {
13578 if (Op.getValueType() == MVT::i1) {
13579 SDValue ExtOp = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i8, Op);
13580 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, ExtOp,
13581 DAG.getConstant(0, dl, MVT::i8));
13583 // CF and OF aren't always set the way we want. Determine which
13584 // of these we need.
13585 bool NeedCF = false;
13586 bool NeedOF = false;
13589 case X86::COND_A: case X86::COND_AE:
13590 case X86::COND_B: case X86::COND_BE:
13593 case X86::COND_G: case X86::COND_GE:
13594 case X86::COND_L: case X86::COND_LE:
13595 case X86::COND_O: case X86::COND_NO: {
13596 // Check if we really need to set the
13597 // Overflow flag. If NoSignedWrap is present
13598 // that is not actually needed.
13599 switch (Op->getOpcode()) {
13604 const auto *BinNode = cast<BinaryWithFlagsSDNode>(Op.getNode());
13605 if (BinNode->Flags.hasNoSignedWrap())
13615 // See if we can use the EFLAGS value from the operand instead of
13616 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
13617 // we prove that the arithmetic won't overflow, we can't use OF or CF.
13618 if (Op.getResNo() != 0 || NeedOF || NeedCF) {
13619 // Emit a CMP with 0, which is the TEST pattern.
13620 //if (Op.getValueType() == MVT::i1)
13621 // return DAG.getNode(X86ISD::CMP, dl, MVT::i1, Op,
13622 // DAG.getConstant(0, MVT::i1));
13623 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
13624 DAG.getConstant(0, dl, Op.getValueType()));
13626 unsigned Opcode = 0;
13627 unsigned NumOperands = 0;
13629 // Truncate operations may prevent the merge of the SETCC instruction
13630 // and the arithmetic instruction before it. Attempt to truncate the operands
13631 // of the arithmetic instruction and use a reduced bit-width instruction.
13632 bool NeedTruncation = false;
13633 SDValue ArithOp = Op;
13634 if (Op->getOpcode() == ISD::TRUNCATE && Op->hasOneUse()) {
13635 SDValue Arith = Op->getOperand(0);
13636 // Both the trunc and the arithmetic op need to have one user each.
13637 if (Arith->hasOneUse())
13638 switch (Arith.getOpcode()) {
13645 NeedTruncation = true;
13651 // NOTICE: In the code below we use ArithOp to hold the arithmetic operation
13652 // which may be the result of a CAST. We use the variable 'Op', which is the
13653 // non-casted variable when we check for possible users.
13654 switch (ArithOp.getOpcode()) {
13656 // Due to an isel shortcoming, be conservative if this add is likely to be
13657 // selected as part of a load-modify-store instruction. When the root node
13658 // in a match is a store, isel doesn't know how to remap non-chain non-flag
13659 // uses of other nodes in the match, such as the ADD in this case. This
13660 // leads to the ADD being left around and reselected, with the result being
13661 // two adds in the output. Alas, even if none our users are stores, that
13662 // doesn't prove we're O.K. Ergo, if we have any parents that aren't
13663 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require
13664 // climbing the DAG back to the root, and it doesn't seem to be worth the
13666 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
13667 UE = Op.getNode()->use_end(); UI != UE; ++UI)
13668 if (UI->getOpcode() != ISD::CopyToReg &&
13669 UI->getOpcode() != ISD::SETCC &&
13670 UI->getOpcode() != ISD::STORE)
13673 if (ConstantSDNode *C =
13674 dyn_cast<ConstantSDNode>(ArithOp.getNode()->getOperand(1))) {
13675 // An add of one will be selected as an INC.
13676 if (C->getAPIntValue() == 1 && !Subtarget->slowIncDec()) {
13677 Opcode = X86ISD::INC;
13682 // An add of negative one (subtract of one) will be selected as a DEC.
13683 if (C->getAPIntValue().isAllOnesValue() && !Subtarget->slowIncDec()) {
13684 Opcode = X86ISD::DEC;
13690 // Otherwise use a regular EFLAGS-setting add.
13691 Opcode = X86ISD::ADD;
13696 // If we have a constant logical shift that's only used in a comparison
13697 // against zero turn it into an equivalent AND. This allows turning it into
13698 // a TEST instruction later.
13699 if ((X86CC == X86::COND_E || X86CC == X86::COND_NE) && Op->hasOneUse() &&
13700 isa<ConstantSDNode>(Op->getOperand(1)) && !hasNonFlagsUse(Op)) {
13701 EVT VT = Op.getValueType();
13702 unsigned BitWidth = VT.getSizeInBits();
13703 unsigned ShAmt = Op->getConstantOperandVal(1);
13704 if (ShAmt >= BitWidth) // Avoid undefined shifts.
13706 APInt Mask = ArithOp.getOpcode() == ISD::SRL
13707 ? APInt::getHighBitsSet(BitWidth, BitWidth - ShAmt)
13708 : APInt::getLowBitsSet(BitWidth, BitWidth - ShAmt);
13709 if (!Mask.isSignedIntN(32)) // Avoid large immediates.
13711 SDValue New = DAG.getNode(ISD::AND, dl, VT, Op->getOperand(0),
13712 DAG.getConstant(Mask, dl, VT));
13713 DAG.ReplaceAllUsesWith(Op, New);
13719 // If the primary and result isn't used, don't bother using X86ISD::AND,
13720 // because a TEST instruction will be better.
13721 if (!hasNonFlagsUse(Op))
13727 // Due to the ISEL shortcoming noted above, be conservative if this op is
13728 // likely to be selected as part of a load-modify-store instruction.
13729 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
13730 UE = Op.getNode()->use_end(); UI != UE; ++UI)
13731 if (UI->getOpcode() == ISD::STORE)
13734 // Otherwise use a regular EFLAGS-setting instruction.
13735 switch (ArithOp.getOpcode()) {
13736 default: llvm_unreachable("unexpected operator!");
13737 case ISD::SUB: Opcode = X86ISD::SUB; break;
13738 case ISD::XOR: Opcode = X86ISD::XOR; break;
13739 case ISD::AND: Opcode = X86ISD::AND; break;
13741 if (!NeedTruncation && (X86CC == X86::COND_E || X86CC == X86::COND_NE)) {
13742 SDValue EFLAGS = LowerVectorAllZeroTest(Op, Subtarget, DAG);
13743 if (EFLAGS.getNode())
13746 Opcode = X86ISD::OR;
13760 return SDValue(Op.getNode(), 1);
13766 // If we found that truncation is beneficial, perform the truncation and
13768 if (NeedTruncation) {
13769 EVT VT = Op.getValueType();
13770 SDValue WideVal = Op->getOperand(0);
13771 EVT WideVT = WideVal.getValueType();
13772 unsigned ConvertedOp = 0;
13773 // Use a target machine opcode to prevent further DAGCombine
13774 // optimizations that may separate the arithmetic operations
13775 // from the setcc node.
13776 switch (WideVal.getOpcode()) {
13778 case ISD::ADD: ConvertedOp = X86ISD::ADD; break;
13779 case ISD::SUB: ConvertedOp = X86ISD::SUB; break;
13780 case ISD::AND: ConvertedOp = X86ISD::AND; break;
13781 case ISD::OR: ConvertedOp = X86ISD::OR; break;
13782 case ISD::XOR: ConvertedOp = X86ISD::XOR; break;
13786 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13787 if (TLI.isOperationLegal(WideVal.getOpcode(), WideVT)) {
13788 SDValue V0 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(0));
13789 SDValue V1 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(1));
13790 Op = DAG.getNode(ConvertedOp, dl, VT, V0, V1);
13796 // Emit a CMP with 0, which is the TEST pattern.
13797 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
13798 DAG.getConstant(0, dl, Op.getValueType()));
13800 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
13801 SmallVector<SDValue, 4> Ops(Op->op_begin(), Op->op_begin() + NumOperands);
13803 SDValue New = DAG.getNode(Opcode, dl, VTs, Ops);
13804 DAG.ReplaceAllUsesWith(Op, New);
13805 return SDValue(New.getNode(), 1);
13808 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
13810 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
13811 SDLoc dl, SelectionDAG &DAG) const {
13812 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1)) {
13813 if (C->getAPIntValue() == 0)
13814 return EmitTest(Op0, X86CC, dl, DAG);
13816 assert(Op0.getValueType() != MVT::i1 &&
13817 "Unexpected comparison operation for MVT::i1 operands");
13820 if ((Op0.getValueType() == MVT::i8 || Op0.getValueType() == MVT::i16 ||
13821 Op0.getValueType() == MVT::i32 || Op0.getValueType() == MVT::i64)) {
13822 // Do the comparison at i32 if it's smaller, besides the Atom case.
13823 // This avoids subregister aliasing issues. Keep the smaller reference
13824 // if we're optimizing for size, however, as that'll allow better folding
13825 // of memory operations.
13826 if (Op0.getValueType() != MVT::i32 && Op0.getValueType() != MVT::i64 &&
13827 !DAG.getMachineFunction().getFunction()->optForMinSize() &&
13828 !Subtarget->isAtom()) {
13829 unsigned ExtendOp =
13830 isX86CCUnsigned(X86CC) ? ISD::ZERO_EXTEND : ISD::SIGN_EXTEND;
13831 Op0 = DAG.getNode(ExtendOp, dl, MVT::i32, Op0);
13832 Op1 = DAG.getNode(ExtendOp, dl, MVT::i32, Op1);
13834 // Use SUB instead of CMP to enable CSE between SUB and CMP.
13835 SDVTList VTs = DAG.getVTList(Op0.getValueType(), MVT::i32);
13836 SDValue Sub = DAG.getNode(X86ISD::SUB, dl, VTs,
13838 return SDValue(Sub.getNode(), 1);
13840 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
13843 /// Convert a comparison if required by the subtarget.
13844 SDValue X86TargetLowering::ConvertCmpIfNecessary(SDValue Cmp,
13845 SelectionDAG &DAG) const {
13846 // If the subtarget does not support the FUCOMI instruction, floating-point
13847 // comparisons have to be converted.
13848 if (Subtarget->hasCMov() ||
13849 Cmp.getOpcode() != X86ISD::CMP ||
13850 !Cmp.getOperand(0).getValueType().isFloatingPoint() ||
13851 !Cmp.getOperand(1).getValueType().isFloatingPoint())
13854 // The instruction selector will select an FUCOM instruction instead of
13855 // FUCOMI, which writes the comparison result to FPSW instead of EFLAGS. Hence
13856 // build an SDNode sequence that transfers the result from FPSW into EFLAGS:
13857 // (X86sahf (trunc (srl (X86fp_stsw (trunc (X86cmp ...)), 8))))
13859 SDValue TruncFPSW = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, Cmp);
13860 SDValue FNStSW = DAG.getNode(X86ISD::FNSTSW16r, dl, MVT::i16, TruncFPSW);
13861 SDValue Srl = DAG.getNode(ISD::SRL, dl, MVT::i16, FNStSW,
13862 DAG.getConstant(8, dl, MVT::i8));
13863 SDValue TruncSrl = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Srl);
13864 return DAG.getNode(X86ISD::SAHF, dl, MVT::i32, TruncSrl);
13867 /// The minimum architected relative accuracy is 2^-12. We need one
13868 /// Newton-Raphson step to have a good float result (24 bits of precision).
13869 SDValue X86TargetLowering::getRsqrtEstimate(SDValue Op,
13870 DAGCombinerInfo &DCI,
13871 unsigned &RefinementSteps,
13872 bool &UseOneConstNR) const {
13873 EVT VT = Op.getValueType();
13874 const char *RecipOp;
13876 // SSE1 has rsqrtss and rsqrtps. AVX adds a 256-bit variant for rsqrtps.
13877 // TODO: Add support for AVX512 (v16f32).
13878 // It is likely not profitable to do this for f64 because a double-precision
13879 // rsqrt estimate with refinement on x86 prior to FMA requires at least 16
13880 // instructions: convert to single, rsqrtss, convert back to double, refine
13881 // (3 steps = at least 13 insts). If an 'rsqrtsd' variant was added to the ISA
13882 // along with FMA, this could be a throughput win.
13883 if (VT == MVT::f32 && Subtarget->hasSSE1())
13885 else if ((VT == MVT::v4f32 && Subtarget->hasSSE1()) ||
13886 (VT == MVT::v8f32 && Subtarget->hasAVX()))
13887 RecipOp = "vec-sqrtf";
13891 TargetRecip Recips = DCI.DAG.getTarget().Options.Reciprocals;
13892 if (!Recips.isEnabled(RecipOp))
13895 RefinementSteps = Recips.getRefinementSteps(RecipOp);
13896 UseOneConstNR = false;
13897 return DCI.DAG.getNode(X86ISD::FRSQRT, SDLoc(Op), VT, Op);
13900 /// The minimum architected relative accuracy is 2^-12. We need one
13901 /// Newton-Raphson step to have a good float result (24 bits of precision).
13902 SDValue X86TargetLowering::getRecipEstimate(SDValue Op,
13903 DAGCombinerInfo &DCI,
13904 unsigned &RefinementSteps) const {
13905 EVT VT = Op.getValueType();
13906 const char *RecipOp;
13908 // SSE1 has rcpss and rcpps. AVX adds a 256-bit variant for rcpps.
13909 // TODO: Add support for AVX512 (v16f32).
13910 // It is likely not profitable to do this for f64 because a double-precision
13911 // reciprocal estimate with refinement on x86 prior to FMA requires
13912 // 15 instructions: convert to single, rcpss, convert back to double, refine
13913 // (3 steps = 12 insts). If an 'rcpsd' variant was added to the ISA
13914 // along with FMA, this could be a throughput win.
13915 if (VT == MVT::f32 && Subtarget->hasSSE1())
13917 else if ((VT == MVT::v4f32 && Subtarget->hasSSE1()) ||
13918 (VT == MVT::v8f32 && Subtarget->hasAVX()))
13919 RecipOp = "vec-divf";
13923 TargetRecip Recips = DCI.DAG.getTarget().Options.Reciprocals;
13924 if (!Recips.isEnabled(RecipOp))
13927 RefinementSteps = Recips.getRefinementSteps(RecipOp);
13928 return DCI.DAG.getNode(X86ISD::FRCP, SDLoc(Op), VT, Op);
13931 /// If we have at least two divisions that use the same divisor, convert to
13932 /// multplication by a reciprocal. This may need to be adjusted for a given
13933 /// CPU if a division's cost is not at least twice the cost of a multiplication.
13934 /// This is because we still need one division to calculate the reciprocal and
13935 /// then we need two multiplies by that reciprocal as replacements for the
13936 /// original divisions.
13937 unsigned X86TargetLowering::combineRepeatedFPDivisors() const {
13941 static bool isAllOnes(SDValue V) {
13942 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
13943 return C && C->isAllOnesValue();
13946 /// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node
13947 /// if it's possible.
13948 SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC,
13949 SDLoc dl, SelectionDAG &DAG) const {
13950 SDValue Op0 = And.getOperand(0);
13951 SDValue Op1 = And.getOperand(1);
13952 if (Op0.getOpcode() == ISD::TRUNCATE)
13953 Op0 = Op0.getOperand(0);
13954 if (Op1.getOpcode() == ISD::TRUNCATE)
13955 Op1 = Op1.getOperand(0);
13958 if (Op1.getOpcode() == ISD::SHL)
13959 std::swap(Op0, Op1);
13960 if (Op0.getOpcode() == ISD::SHL) {
13961 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0)))
13962 if (And00C->getZExtValue() == 1) {
13963 // If we looked past a truncate, check that it's only truncating away
13965 unsigned BitWidth = Op0.getValueSizeInBits();
13966 unsigned AndBitWidth = And.getValueSizeInBits();
13967 if (BitWidth > AndBitWidth) {
13969 DAG.computeKnownBits(Op0, Zeros, Ones);
13970 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth)
13974 RHS = Op0.getOperand(1);
13976 } else if (Op1.getOpcode() == ISD::Constant) {
13977 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1);
13978 uint64_t AndRHSVal = AndRHS->getZExtValue();
13979 SDValue AndLHS = Op0;
13981 if (AndRHSVal == 1 && AndLHS.getOpcode() == ISD::SRL) {
13982 LHS = AndLHS.getOperand(0);
13983 RHS = AndLHS.getOperand(1);
13986 // Use BT if the immediate can't be encoded in a TEST instruction.
13987 if (!isUInt<32>(AndRHSVal) && isPowerOf2_64(AndRHSVal)) {
13989 RHS = DAG.getConstant(Log2_64_Ceil(AndRHSVal), dl, LHS.getValueType());
13993 if (LHS.getNode()) {
13994 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT
13995 // instruction. Since the shift amount is in-range-or-undefined, we know
13996 // that doing a bittest on the i32 value is ok. We extend to i32 because
13997 // the encoding for the i16 version is larger than the i32 version.
13998 // Also promote i16 to i32 for performance / code size reason.
13999 if (LHS.getValueType() == MVT::i8 ||
14000 LHS.getValueType() == MVT::i16)
14001 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
14003 // If the operand types disagree, extend the shift amount to match. Since
14004 // BT ignores high bits (like shifts) we can use anyextend.
14005 if (LHS.getValueType() != RHS.getValueType())
14006 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
14008 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
14009 X86::CondCode Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
14010 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
14011 DAG.getConstant(Cond, dl, MVT::i8), BT);
14017 /// \brief - Turns an ISD::CondCode into a value suitable for SSE floating point
14019 static int translateX86FSETCC(ISD::CondCode SetCCOpcode, SDValue &Op0,
14024 // SSE Condition code mapping:
14033 switch (SetCCOpcode) {
14034 default: llvm_unreachable("Unexpected SETCC condition");
14036 case ISD::SETEQ: SSECC = 0; break;
14038 case ISD::SETGT: Swap = true; // Fallthrough
14040 case ISD::SETOLT: SSECC = 1; break;
14042 case ISD::SETGE: Swap = true; // Fallthrough
14044 case ISD::SETOLE: SSECC = 2; break;
14045 case ISD::SETUO: SSECC = 3; break;
14047 case ISD::SETNE: SSECC = 4; break;
14048 case ISD::SETULE: Swap = true; // Fallthrough
14049 case ISD::SETUGE: SSECC = 5; break;
14050 case ISD::SETULT: Swap = true; // Fallthrough
14051 case ISD::SETUGT: SSECC = 6; break;
14052 case ISD::SETO: SSECC = 7; break;
14054 case ISD::SETONE: SSECC = 8; break;
14057 std::swap(Op0, Op1);
14062 // Lower256IntVSETCC - Break a VSETCC 256-bit integer VSETCC into two new 128
14063 // ones, and then concatenate the result back.
14064 static SDValue Lower256IntVSETCC(SDValue Op, SelectionDAG &DAG) {
14065 MVT VT = Op.getSimpleValueType();
14067 assert(VT.is256BitVector() && Op.getOpcode() == ISD::SETCC &&
14068 "Unsupported value type for operation");
14070 unsigned NumElems = VT.getVectorNumElements();
14072 SDValue CC = Op.getOperand(2);
14074 // Extract the LHS vectors
14075 SDValue LHS = Op.getOperand(0);
14076 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
14077 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
14079 // Extract the RHS vectors
14080 SDValue RHS = Op.getOperand(1);
14081 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
14082 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
14084 // Issue the operation on the smaller types and concatenate the result back
14085 MVT EltVT = VT.getVectorElementType();
14086 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
14087 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
14088 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1, CC),
14089 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC));
14092 static SDValue LowerBoolVSETCC_AVX512(SDValue Op, SelectionDAG &DAG) {
14093 SDValue Op0 = Op.getOperand(0);
14094 SDValue Op1 = Op.getOperand(1);
14095 SDValue CC = Op.getOperand(2);
14096 MVT VT = Op.getSimpleValueType();
14099 assert(Op0.getSimpleValueType().getVectorElementType() == MVT::i1 &&
14100 "Unexpected type for boolean compare operation");
14101 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
14102 SDValue NotOp0 = DAG.getNode(ISD::XOR, dl, VT, Op0,
14103 DAG.getConstant(-1, dl, VT));
14104 SDValue NotOp1 = DAG.getNode(ISD::XOR, dl, VT, Op1,
14105 DAG.getConstant(-1, dl, VT));
14106 switch (SetCCOpcode) {
14107 default: llvm_unreachable("Unexpected SETCC condition");
14109 // (x == y) -> ~(x ^ y)
14110 return DAG.getNode(ISD::XOR, dl, VT,
14111 DAG.getNode(ISD::XOR, dl, VT, Op0, Op1),
14112 DAG.getConstant(-1, dl, VT));
14114 // (x != y) -> (x ^ y)
14115 return DAG.getNode(ISD::XOR, dl, VT, Op0, Op1);
14118 // (x > y) -> (x & ~y)
14119 return DAG.getNode(ISD::AND, dl, VT, Op0, NotOp1);
14122 // (x < y) -> (~x & y)
14123 return DAG.getNode(ISD::AND, dl, VT, NotOp0, Op1);
14126 // (x <= y) -> (~x | y)
14127 return DAG.getNode(ISD::OR, dl, VT, NotOp0, Op1);
14130 // (x >=y) -> (x | ~y)
14131 return DAG.getNode(ISD::OR, dl, VT, Op0, NotOp1);
14135 static SDValue LowerIntVSETCC_AVX512(SDValue Op, SelectionDAG &DAG,
14136 const X86Subtarget *Subtarget) {
14137 SDValue Op0 = Op.getOperand(0);
14138 SDValue Op1 = Op.getOperand(1);
14139 SDValue CC = Op.getOperand(2);
14140 MVT VT = Op.getSimpleValueType();
14143 assert(Op0.getSimpleValueType().getVectorElementType().getSizeInBits() >= 8 &&
14144 Op.getSimpleValueType().getVectorElementType() == MVT::i1 &&
14145 "Cannot set masked compare for this operation");
14147 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
14149 bool Unsigned = false;
14152 switch (SetCCOpcode) {
14153 default: llvm_unreachable("Unexpected SETCC condition");
14154 case ISD::SETNE: SSECC = 4; break;
14155 case ISD::SETEQ: Opc = X86ISD::PCMPEQM; break;
14156 case ISD::SETUGT: SSECC = 6; Unsigned = true; break;
14157 case ISD::SETLT: Swap = true; //fall-through
14158 case ISD::SETGT: Opc = X86ISD::PCMPGTM; break;
14159 case ISD::SETULT: SSECC = 1; Unsigned = true; break;
14160 case ISD::SETUGE: SSECC = 5; Unsigned = true; break; //NLT
14161 case ISD::SETGE: Swap = true; SSECC = 2; break; // LE + swap
14162 case ISD::SETULE: Unsigned = true; //fall-through
14163 case ISD::SETLE: SSECC = 2; break;
14167 std::swap(Op0, Op1);
14169 return DAG.getNode(Opc, dl, VT, Op0, Op1);
14170 Opc = Unsigned ? X86ISD::CMPMU: X86ISD::CMPM;
14171 return DAG.getNode(Opc, dl, VT, Op0, Op1,
14172 DAG.getConstant(SSECC, dl, MVT::i8));
14175 /// \brief Try to turn a VSETULT into a VSETULE by modifying its second
14176 /// operand \p Op1. If non-trivial (for example because it's not constant)
14177 /// return an empty value.
14178 static SDValue ChangeVSETULTtoVSETULE(SDLoc dl, SDValue Op1, SelectionDAG &DAG)
14180 BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(Op1.getNode());
14184 MVT VT = Op1.getSimpleValueType();
14185 MVT EVT = VT.getVectorElementType();
14186 unsigned n = VT.getVectorNumElements();
14187 SmallVector<SDValue, 8> ULTOp1;
14189 for (unsigned i = 0; i < n; ++i) {
14190 ConstantSDNode *Elt = dyn_cast<ConstantSDNode>(BV->getOperand(i));
14191 if (!Elt || Elt->isOpaque() || Elt->getSimpleValueType(0) != EVT)
14194 // Avoid underflow.
14195 APInt Val = Elt->getAPIntValue();
14199 ULTOp1.push_back(DAG.getConstant(Val - 1, dl, EVT));
14202 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, ULTOp1);
14205 static SDValue LowerVSETCC(SDValue Op, const X86Subtarget *Subtarget,
14206 SelectionDAG &DAG) {
14207 SDValue Op0 = Op.getOperand(0);
14208 SDValue Op1 = Op.getOperand(1);
14209 SDValue CC = Op.getOperand(2);
14210 MVT VT = Op.getSimpleValueType();
14211 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
14212 bool isFP = Op.getOperand(1).getSimpleValueType().isFloatingPoint();
14217 MVT EltVT = Op0.getSimpleValueType().getVectorElementType();
14218 assert(EltVT == MVT::f32 || EltVT == MVT::f64);
14221 unsigned SSECC = translateX86FSETCC(SetCCOpcode, Op0, Op1);
14222 unsigned Opc = X86ISD::CMPP;
14223 if (Subtarget->hasAVX512() && VT.getVectorElementType() == MVT::i1) {
14224 assert(VT.getVectorNumElements() <= 16);
14225 Opc = X86ISD::CMPM;
14227 // In the two special cases we can't handle, emit two comparisons.
14230 unsigned CombineOpc;
14231 if (SetCCOpcode == ISD::SETUEQ) {
14232 CC0 = 3; CC1 = 0; CombineOpc = ISD::OR;
14234 assert(SetCCOpcode == ISD::SETONE);
14235 CC0 = 7; CC1 = 4; CombineOpc = ISD::AND;
14238 SDValue Cmp0 = DAG.getNode(Opc, dl, VT, Op0, Op1,
14239 DAG.getConstant(CC0, dl, MVT::i8));
14240 SDValue Cmp1 = DAG.getNode(Opc, dl, VT, Op0, Op1,
14241 DAG.getConstant(CC1, dl, MVT::i8));
14242 return DAG.getNode(CombineOpc, dl, VT, Cmp0, Cmp1);
14244 // Handle all other FP comparisons here.
14245 return DAG.getNode(Opc, dl, VT, Op0, Op1,
14246 DAG.getConstant(SSECC, dl, MVT::i8));
14249 MVT VTOp0 = Op0.getSimpleValueType();
14250 assert(VTOp0 == Op1.getSimpleValueType() &&
14251 "Expected operands with same type!");
14252 assert(VT.getVectorNumElements() == VTOp0.getVectorNumElements() &&
14253 "Invalid number of packed elements for source and destination!");
14255 if (VT.is128BitVector() && VTOp0.is256BitVector()) {
14256 // On non-AVX512 targets, a vector of MVT::i1 is promoted by the type
14257 // legalizer to a wider vector type. In the case of 'vsetcc' nodes, the
14258 // legalizer firstly checks if the first operand in input to the setcc has
14259 // a legal type. If so, then it promotes the return type to that same type.
14260 // Otherwise, the return type is promoted to the 'next legal type' which,
14261 // for a vector of MVT::i1 is always a 128-bit integer vector type.
14263 // We reach this code only if the following two conditions are met:
14264 // 1. Both return type and operand type have been promoted to wider types
14265 // by the type legalizer.
14266 // 2. The original operand type has been promoted to a 256-bit vector.
14268 // Note that condition 2. only applies for AVX targets.
14269 SDValue NewOp = DAG.getSetCC(dl, VTOp0, Op0, Op1, SetCCOpcode);
14270 return DAG.getZExtOrTrunc(NewOp, dl, VT);
14273 // The non-AVX512 code below works under the assumption that source and
14274 // destination types are the same.
14275 assert((Subtarget->hasAVX512() || (VT == VTOp0)) &&
14276 "Value types for source and destination must be the same!");
14278 // Break 256-bit integer vector compare into smaller ones.
14279 if (VT.is256BitVector() && !Subtarget->hasInt256())
14280 return Lower256IntVSETCC(Op, DAG);
14282 MVT OpVT = Op1.getSimpleValueType();
14283 if (OpVT.getVectorElementType() == MVT::i1)
14284 return LowerBoolVSETCC_AVX512(Op, DAG);
14286 bool MaskResult = (VT.getVectorElementType() == MVT::i1);
14287 if (Subtarget->hasAVX512()) {
14288 if (Op1.getSimpleValueType().is512BitVector() ||
14289 (Subtarget->hasBWI() && Subtarget->hasVLX()) ||
14290 (MaskResult && OpVT.getVectorElementType().getSizeInBits() >= 32))
14291 return LowerIntVSETCC_AVX512(Op, DAG, Subtarget);
14293 // In AVX-512 architecture setcc returns mask with i1 elements,
14294 // But there is no compare instruction for i8 and i16 elements in KNL.
14295 // We are not talking about 512-bit operands in this case, these
14296 // types are illegal.
14298 (OpVT.getVectorElementType().getSizeInBits() < 32 &&
14299 OpVT.getVectorElementType().getSizeInBits() >= 8))
14300 return DAG.getNode(ISD::TRUNCATE, dl, VT,
14301 DAG.getNode(ISD::SETCC, dl, OpVT, Op0, Op1, CC));
14304 // Lower using XOP integer comparisons.
14305 if ((VT == MVT::v16i8 || VT == MVT::v8i16 ||
14306 VT == MVT::v4i32 || VT == MVT::v2i64) && Subtarget->hasXOP()) {
14307 // Translate compare code to XOP PCOM compare mode.
14308 unsigned CmpMode = 0;
14309 switch (SetCCOpcode) {
14310 default: llvm_unreachable("Unexpected SETCC condition");
14312 case ISD::SETLT: CmpMode = 0x00; break;
14314 case ISD::SETLE: CmpMode = 0x01; break;
14316 case ISD::SETGT: CmpMode = 0x02; break;
14318 case ISD::SETGE: CmpMode = 0x03; break;
14319 case ISD::SETEQ: CmpMode = 0x04; break;
14320 case ISD::SETNE: CmpMode = 0x05; break;
14323 // Are we comparing unsigned or signed integers?
14324 unsigned Opc = ISD::isUnsignedIntSetCC(SetCCOpcode)
14325 ? X86ISD::VPCOMU : X86ISD::VPCOM;
14327 return DAG.getNode(Opc, dl, VT, Op0, Op1,
14328 DAG.getConstant(CmpMode, dl, MVT::i8));
14331 // We are handling one of the integer comparisons here. Since SSE only has
14332 // GT and EQ comparisons for integer, swapping operands and multiple
14333 // operations may be required for some comparisons.
14335 bool Swap = false, Invert = false, FlipSigns = false, MinMax = false;
14336 bool Subus = false;
14338 switch (SetCCOpcode) {
14339 default: llvm_unreachable("Unexpected SETCC condition");
14340 case ISD::SETNE: Invert = true;
14341 case ISD::SETEQ: Opc = X86ISD::PCMPEQ; break;
14342 case ISD::SETLT: Swap = true;
14343 case ISD::SETGT: Opc = X86ISD::PCMPGT; break;
14344 case ISD::SETGE: Swap = true;
14345 case ISD::SETLE: Opc = X86ISD::PCMPGT;
14346 Invert = true; break;
14347 case ISD::SETULT: Swap = true;
14348 case ISD::SETUGT: Opc = X86ISD::PCMPGT;
14349 FlipSigns = true; break;
14350 case ISD::SETUGE: Swap = true;
14351 case ISD::SETULE: Opc = X86ISD::PCMPGT;
14352 FlipSigns = true; Invert = true; break;
14355 // Special case: Use min/max operations for SETULE/SETUGE
14356 MVT VET = VT.getVectorElementType();
14358 (Subtarget->hasSSE41() && (VET >= MVT::i8 && VET <= MVT::i32))
14359 || (Subtarget->hasSSE2() && (VET == MVT::i8));
14362 switch (SetCCOpcode) {
14364 case ISD::SETULE: Opc = ISD::UMIN; MinMax = true; break;
14365 case ISD::SETUGE: Opc = ISD::UMAX; MinMax = true; break;
14368 if (MinMax) { Swap = false; Invert = false; FlipSigns = false; }
14371 bool hasSubus = Subtarget->hasSSE2() && (VET == MVT::i8 || VET == MVT::i16);
14372 if (!MinMax && hasSubus) {
14373 // As another special case, use PSUBUS[BW] when it's profitable. E.g. for
14375 // t = psubus Op0, Op1
14376 // pcmpeq t, <0..0>
14377 switch (SetCCOpcode) {
14379 case ISD::SETULT: {
14380 // If the comparison is against a constant we can turn this into a
14381 // setule. With psubus, setule does not require a swap. This is
14382 // beneficial because the constant in the register is no longer
14383 // destructed as the destination so it can be hoisted out of a loop.
14384 // Only do this pre-AVX since vpcmp* is no longer destructive.
14385 if (Subtarget->hasAVX())
14387 SDValue ULEOp1 = ChangeVSETULTtoVSETULE(dl, Op1, DAG);
14388 if (ULEOp1.getNode()) {
14390 Subus = true; Invert = false; Swap = false;
14394 // Psubus is better than flip-sign because it requires no inversion.
14395 case ISD::SETUGE: Subus = true; Invert = false; Swap = true; break;
14396 case ISD::SETULE: Subus = true; Invert = false; Swap = false; break;
14400 Opc = X86ISD::SUBUS;
14406 std::swap(Op0, Op1);
14408 // Check that the operation in question is available (most are plain SSE2,
14409 // but PCMPGTQ and PCMPEQQ have different requirements).
14410 if (VT == MVT::v2i64) {
14411 if (Opc == X86ISD::PCMPGT && !Subtarget->hasSSE42()) {
14412 assert(Subtarget->hasSSE2() && "Don't know how to lower!");
14414 // First cast everything to the right type.
14415 Op0 = DAG.getBitcast(MVT::v4i32, Op0);
14416 Op1 = DAG.getBitcast(MVT::v4i32, Op1);
14418 // Since SSE has no unsigned integer comparisons, we need to flip the sign
14419 // bits of the inputs before performing those operations. The lower
14420 // compare is always unsigned.
14423 SB = DAG.getConstant(0x80000000U, dl, MVT::v4i32);
14425 SDValue Sign = DAG.getConstant(0x80000000U, dl, MVT::i32);
14426 SDValue Zero = DAG.getConstant(0x00000000U, dl, MVT::i32);
14427 SB = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
14428 Sign, Zero, Sign, Zero);
14430 Op0 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op0, SB);
14431 Op1 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op1, SB);
14433 // Emulate PCMPGTQ with (hi1 > hi2) | ((hi1 == hi2) & (lo1 > lo2))
14434 SDValue GT = DAG.getNode(X86ISD::PCMPGT, dl, MVT::v4i32, Op0, Op1);
14435 SDValue EQ = DAG.getNode(X86ISD::PCMPEQ, dl, MVT::v4i32, Op0, Op1);
14437 // Create masks for only the low parts/high parts of the 64 bit integers.
14438 static const int MaskHi[] = { 1, 1, 3, 3 };
14439 static const int MaskLo[] = { 0, 0, 2, 2 };
14440 SDValue EQHi = DAG.getVectorShuffle(MVT::v4i32, dl, EQ, EQ, MaskHi);
14441 SDValue GTLo = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskLo);
14442 SDValue GTHi = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskHi);
14444 SDValue Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, EQHi, GTLo);
14445 Result = DAG.getNode(ISD::OR, dl, MVT::v4i32, Result, GTHi);
14448 Result = DAG.getNOT(dl, Result, MVT::v4i32);
14450 return DAG.getBitcast(VT, Result);
14453 if (Opc == X86ISD::PCMPEQ && !Subtarget->hasSSE41()) {
14454 // If pcmpeqq is missing but pcmpeqd is available synthesize pcmpeqq with
14455 // pcmpeqd + pshufd + pand.
14456 assert(Subtarget->hasSSE2() && !FlipSigns && "Don't know how to lower!");
14458 // First cast everything to the right type.
14459 Op0 = DAG.getBitcast(MVT::v4i32, Op0);
14460 Op1 = DAG.getBitcast(MVT::v4i32, Op1);
14463 SDValue Result = DAG.getNode(Opc, dl, MVT::v4i32, Op0, Op1);
14465 // Make sure the lower and upper halves are both all-ones.
14466 static const int Mask[] = { 1, 0, 3, 2 };
14467 SDValue Shuf = DAG.getVectorShuffle(MVT::v4i32, dl, Result, Result, Mask);
14468 Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, Result, Shuf);
14471 Result = DAG.getNOT(dl, Result, MVT::v4i32);
14473 return DAG.getBitcast(VT, Result);
14477 // Since SSE has no unsigned integer comparisons, we need to flip the sign
14478 // bits of the inputs before performing those operations.
14480 MVT EltVT = VT.getVectorElementType();
14481 SDValue SB = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()), dl,
14483 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SB);
14484 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SB);
14487 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
14489 // If the logical-not of the result is required, perform that now.
14491 Result = DAG.getNOT(dl, Result, VT);
14494 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Op0, Result);
14497 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Result,
14498 getZeroVector(VT, Subtarget, DAG, dl));
14503 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
14505 MVT VT = Op.getSimpleValueType();
14507 if (VT.isVector()) return LowerVSETCC(Op, Subtarget, DAG);
14509 assert(((!Subtarget->hasAVX512() && VT == MVT::i8) || (VT == MVT::i1))
14510 && "SetCC type must be 8-bit or 1-bit integer");
14511 SDValue Op0 = Op.getOperand(0);
14512 SDValue Op1 = Op.getOperand(1);
14514 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
14516 // Optimize to BT if possible.
14517 // Lower (X & (1 << N)) == 0 to BT(X, N).
14518 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
14519 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
14520 if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() &&
14521 Op1.getOpcode() == ISD::Constant &&
14522 cast<ConstantSDNode>(Op1)->isNullValue() &&
14523 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
14524 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG);
14525 if (NewSetCC.getNode()) {
14527 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, NewSetCC);
14532 // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of
14534 if (Op1.getOpcode() == ISD::Constant &&
14535 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 ||
14536 cast<ConstantSDNode>(Op1)->isNullValue()) &&
14537 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
14539 // If the input is a setcc, then reuse the input setcc or use a new one with
14540 // the inverted condition.
14541 if (Op0.getOpcode() == X86ISD::SETCC) {
14542 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0);
14543 bool Invert = (CC == ISD::SETNE) ^
14544 cast<ConstantSDNode>(Op1)->isNullValue();
14548 CCode = X86::GetOppositeBranchCondition(CCode);
14549 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
14550 DAG.getConstant(CCode, dl, MVT::i8),
14551 Op0.getOperand(1));
14553 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
14557 if ((Op0.getValueType() == MVT::i1) && (Op1.getOpcode() == ISD::Constant) &&
14558 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1) &&
14559 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
14561 ISD::CondCode NewCC = ISD::getSetCCInverse(CC, true);
14562 return DAG.getSetCC(dl, VT, Op0, DAG.getConstant(0, dl, MVT::i1), NewCC);
14565 bool isFP = Op1.getSimpleValueType().isFloatingPoint();
14566 unsigned X86CC = TranslateX86CC(CC, dl, isFP, Op0, Op1, DAG);
14567 if (X86CC == X86::COND_INVALID)
14570 SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, dl, DAG);
14571 EFLAGS = ConvertCmpIfNecessary(EFLAGS, DAG);
14572 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
14573 DAG.getConstant(X86CC, dl, MVT::i8), EFLAGS);
14575 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
14579 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
14580 static bool isX86LogicalCmp(SDValue Op) {
14581 unsigned Opc = Op.getNode()->getOpcode();
14582 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI ||
14583 Opc == X86ISD::SAHF)
14585 if (Op.getResNo() == 1 &&
14586 (Opc == X86ISD::ADD ||
14587 Opc == X86ISD::SUB ||
14588 Opc == X86ISD::ADC ||
14589 Opc == X86ISD::SBB ||
14590 Opc == X86ISD::SMUL ||
14591 Opc == X86ISD::UMUL ||
14592 Opc == X86ISD::INC ||
14593 Opc == X86ISD::DEC ||
14594 Opc == X86ISD::OR ||
14595 Opc == X86ISD::XOR ||
14596 Opc == X86ISD::AND))
14599 if (Op.getResNo() == 2 && Opc == X86ISD::UMUL)
14605 static bool isTruncWithZeroHighBitsInput(SDValue V, SelectionDAG &DAG) {
14606 if (V.getOpcode() != ISD::TRUNCATE)
14609 SDValue VOp0 = V.getOperand(0);
14610 unsigned InBits = VOp0.getValueSizeInBits();
14611 unsigned Bits = V.getValueSizeInBits();
14612 return DAG.MaskedValueIsZero(VOp0, APInt::getHighBitsSet(InBits,InBits-Bits));
14615 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
14616 bool addTest = true;
14617 SDValue Cond = Op.getOperand(0);
14618 SDValue Op1 = Op.getOperand(1);
14619 SDValue Op2 = Op.getOperand(2);
14621 MVT VT = Op1.getSimpleValueType();
14624 // Lower FP selects into a CMP/AND/ANDN/OR sequence when the necessary SSE ops
14625 // are available or VBLENDV if AVX is available.
14626 // Otherwise FP cmovs get lowered into a less efficient branch sequence later.
14627 if (Cond.getOpcode() == ISD::SETCC &&
14628 ((Subtarget->hasSSE2() && (VT == MVT::f32 || VT == MVT::f64)) ||
14629 (Subtarget->hasSSE1() && VT == MVT::f32)) &&
14630 VT == Cond.getOperand(0).getSimpleValueType() && Cond->hasOneUse()) {
14631 SDValue CondOp0 = Cond.getOperand(0), CondOp1 = Cond.getOperand(1);
14632 int SSECC = translateX86FSETCC(
14633 cast<CondCodeSDNode>(Cond.getOperand(2))->get(), CondOp0, CondOp1);
14636 if (Subtarget->hasAVX512()) {
14637 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CondOp0, CondOp1,
14638 DAG.getConstant(SSECC, DL, MVT::i8));
14639 return DAG.getNode(X86ISD::SELECT, DL, VT, Cmp, Op1, Op2);
14642 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, VT, CondOp0, CondOp1,
14643 DAG.getConstant(SSECC, DL, MVT::i8));
14645 // If we have AVX, we can use a variable vector select (VBLENDV) instead
14646 // of 3 logic instructions for size savings and potentially speed.
14647 // Unfortunately, there is no scalar form of VBLENDV.
14649 // If either operand is a constant, don't try this. We can expect to
14650 // optimize away at least one of the logic instructions later in that
14651 // case, so that sequence would be faster than a variable blend.
14653 // BLENDV was introduced with SSE 4.1, but the 2 register form implicitly
14654 // uses XMM0 as the selection register. That may need just as many
14655 // instructions as the AND/ANDN/OR sequence due to register moves, so
14658 if (Subtarget->hasAVX() &&
14659 !isa<ConstantFPSDNode>(Op1) && !isa<ConstantFPSDNode>(Op2)) {
14661 // Convert to vectors, do a VSELECT, and convert back to scalar.
14662 // All of the conversions should be optimized away.
14664 MVT VecVT = VT == MVT::f32 ? MVT::v4f32 : MVT::v2f64;
14665 SDValue VOp1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VecVT, Op1);
14666 SDValue VOp2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VecVT, Op2);
14667 SDValue VCmp = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VecVT, Cmp);
14669 MVT VCmpVT = VT == MVT::f32 ? MVT::v4i32 : MVT::v2i64;
14670 VCmp = DAG.getBitcast(VCmpVT, VCmp);
14672 SDValue VSel = DAG.getNode(ISD::VSELECT, DL, VecVT, VCmp, VOp1, VOp2);
14674 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT,
14675 VSel, DAG.getIntPtrConstant(0, DL));
14677 SDValue AndN = DAG.getNode(X86ISD::FANDN, DL, VT, Cmp, Op2);
14678 SDValue And = DAG.getNode(X86ISD::FAND, DL, VT, Cmp, Op1);
14679 return DAG.getNode(X86ISD::FOR, DL, VT, AndN, And);
14683 if (VT.isVector() && VT.getVectorElementType() == MVT::i1) {
14685 if (ISD::isBuildVectorOfConstantSDNodes(Op1.getNode()))
14686 Op1Scalar = ConvertI1VectorToInteger(Op1, DAG);
14687 else if (Op1.getOpcode() == ISD::BITCAST && Op1.getOperand(0))
14688 Op1Scalar = Op1.getOperand(0);
14690 if (ISD::isBuildVectorOfConstantSDNodes(Op2.getNode()))
14691 Op2Scalar = ConvertI1VectorToInteger(Op2, DAG);
14692 else if (Op2.getOpcode() == ISD::BITCAST && Op2.getOperand(0))
14693 Op2Scalar = Op2.getOperand(0);
14694 if (Op1Scalar.getNode() && Op2Scalar.getNode()) {
14695 SDValue newSelect = DAG.getNode(ISD::SELECT, DL,
14696 Op1Scalar.getValueType(),
14697 Cond, Op1Scalar, Op2Scalar);
14698 if (newSelect.getValueSizeInBits() == VT.getSizeInBits())
14699 return DAG.getBitcast(VT, newSelect);
14700 SDValue ExtVec = DAG.getBitcast(MVT::v8i1, newSelect);
14701 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, ExtVec,
14702 DAG.getIntPtrConstant(0, DL));
14706 if (VT == MVT::v4i1 || VT == MVT::v2i1) {
14707 SDValue zeroConst = DAG.getIntPtrConstant(0, DL);
14708 Op1 = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, MVT::v8i1,
14709 DAG.getUNDEF(MVT::v8i1), Op1, zeroConst);
14710 Op2 = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, MVT::v8i1,
14711 DAG.getUNDEF(MVT::v8i1), Op2, zeroConst);
14712 SDValue newSelect = DAG.getNode(ISD::SELECT, DL, MVT::v8i1,
14714 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, newSelect, zeroConst);
14717 if (Cond.getOpcode() == ISD::SETCC) {
14718 SDValue NewCond = LowerSETCC(Cond, DAG);
14719 if (NewCond.getNode())
14723 // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y
14724 // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y
14725 // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y
14726 // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y
14727 if (Cond.getOpcode() == X86ISD::SETCC &&
14728 Cond.getOperand(1).getOpcode() == X86ISD::CMP &&
14729 isZero(Cond.getOperand(1).getOperand(1))) {
14730 SDValue Cmp = Cond.getOperand(1);
14732 unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue();
14734 if ((isAllOnes(Op1) || isAllOnes(Op2)) &&
14735 (CondCode == X86::COND_E || CondCode == X86::COND_NE)) {
14736 SDValue Y = isAllOnes(Op2) ? Op1 : Op2;
14738 SDValue CmpOp0 = Cmp.getOperand(0);
14739 // Apply further optimizations for special cases
14740 // (select (x != 0), -1, 0) -> neg & sbb
14741 // (select (x == 0), 0, -1) -> neg & sbb
14742 if (ConstantSDNode *YC = dyn_cast<ConstantSDNode>(Y))
14743 if (YC->isNullValue() &&
14744 (isAllOnes(Op1) == (CondCode == X86::COND_NE))) {
14745 SDVTList VTs = DAG.getVTList(CmpOp0.getValueType(), MVT::i32);
14746 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, VTs,
14747 DAG.getConstant(0, DL,
14748 CmpOp0.getValueType()),
14750 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
14751 DAG.getConstant(X86::COND_B, DL, MVT::i8),
14752 SDValue(Neg.getNode(), 1));
14756 Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32,
14757 CmpOp0, DAG.getConstant(1, DL, CmpOp0.getValueType()));
14758 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
14760 SDValue Res = // Res = 0 or -1.
14761 DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
14762 DAG.getConstant(X86::COND_B, DL, MVT::i8), Cmp);
14764 if (isAllOnes(Op1) != (CondCode == X86::COND_E))
14765 Res = DAG.getNOT(DL, Res, Res.getValueType());
14767 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2);
14768 if (!N2C || !N2C->isNullValue())
14769 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y);
14774 // Look past (and (setcc_carry (cmp ...)), 1).
14775 if (Cond.getOpcode() == ISD::AND &&
14776 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
14777 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
14778 if (C && C->getAPIntValue() == 1)
14779 Cond = Cond.getOperand(0);
14782 // If condition flag is set by a X86ISD::CMP, then use it as the condition
14783 // setting operand in place of the X86ISD::SETCC.
14784 unsigned CondOpcode = Cond.getOpcode();
14785 if (CondOpcode == X86ISD::SETCC ||
14786 CondOpcode == X86ISD::SETCC_CARRY) {
14787 CC = Cond.getOperand(0);
14789 SDValue Cmp = Cond.getOperand(1);
14790 unsigned Opc = Cmp.getOpcode();
14791 MVT VT = Op.getSimpleValueType();
14793 bool IllegalFPCMov = false;
14794 if (VT.isFloatingPoint() && !VT.isVector() &&
14795 !isScalarFPTypeInSSEReg(VT)) // FPStack?
14796 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
14798 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
14799 Opc == X86ISD::BT) { // FIXME
14803 } else if (CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
14804 CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
14805 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
14806 Cond.getOperand(0).getValueType() != MVT::i8)) {
14807 SDValue LHS = Cond.getOperand(0);
14808 SDValue RHS = Cond.getOperand(1);
14809 unsigned X86Opcode;
14812 switch (CondOpcode) {
14813 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
14814 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
14815 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
14816 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
14817 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
14818 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
14819 default: llvm_unreachable("unexpected overflowing operator");
14821 if (CondOpcode == ISD::UMULO)
14822 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
14825 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
14827 SDValue X86Op = DAG.getNode(X86Opcode, DL, VTs, LHS, RHS);
14829 if (CondOpcode == ISD::UMULO)
14830 Cond = X86Op.getValue(2);
14832 Cond = X86Op.getValue(1);
14834 CC = DAG.getConstant(X86Cond, DL, MVT::i8);
14839 // Look past the truncate if the high bits are known zero.
14840 if (isTruncWithZeroHighBitsInput(Cond, DAG))
14841 Cond = Cond.getOperand(0);
14843 // We know the result of AND is compared against zero. Try to match
14845 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
14846 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG);
14847 if (NewSetCC.getNode()) {
14848 CC = NewSetCC.getOperand(0);
14849 Cond = NewSetCC.getOperand(1);
14856 CC = DAG.getConstant(X86::COND_NE, DL, MVT::i8);
14857 Cond = EmitTest(Cond, X86::COND_NE, DL, DAG);
14860 // a < b ? -1 : 0 -> RES = ~setcc_carry
14861 // a < b ? 0 : -1 -> RES = setcc_carry
14862 // a >= b ? -1 : 0 -> RES = setcc_carry
14863 // a >= b ? 0 : -1 -> RES = ~setcc_carry
14864 if (Cond.getOpcode() == X86ISD::SUB) {
14865 Cond = ConvertCmpIfNecessary(Cond, DAG);
14866 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue();
14868 if ((CondCode == X86::COND_AE || CondCode == X86::COND_B) &&
14869 (isAllOnes(Op1) || isAllOnes(Op2)) && (isZero(Op1) || isZero(Op2))) {
14870 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
14871 DAG.getConstant(X86::COND_B, DL, MVT::i8),
14873 if (isAllOnes(Op1) != (CondCode == X86::COND_B))
14874 return DAG.getNOT(DL, Res, Res.getValueType());
14879 // X86 doesn't have an i8 cmov. If both operands are the result of a truncate
14880 // widen the cmov and push the truncate through. This avoids introducing a new
14881 // branch during isel and doesn't add any extensions.
14882 if (Op.getValueType() == MVT::i8 &&
14883 Op1.getOpcode() == ISD::TRUNCATE && Op2.getOpcode() == ISD::TRUNCATE) {
14884 SDValue T1 = Op1.getOperand(0), T2 = Op2.getOperand(0);
14885 if (T1.getValueType() == T2.getValueType() &&
14886 // Blacklist CopyFromReg to avoid partial register stalls.
14887 T1.getOpcode() != ISD::CopyFromReg && T2.getOpcode()!=ISD::CopyFromReg){
14888 SDVTList VTs = DAG.getVTList(T1.getValueType(), MVT::Glue);
14889 SDValue Cmov = DAG.getNode(X86ISD::CMOV, DL, VTs, T2, T1, CC, Cond);
14890 return DAG.getNode(ISD::TRUNCATE, DL, Op.getValueType(), Cmov);
14894 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
14895 // condition is true.
14896 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
14897 SDValue Ops[] = { Op2, Op1, CC, Cond };
14898 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops);
14901 static SDValue LowerSIGN_EXTEND_AVX512(SDValue Op,
14902 const X86Subtarget *Subtarget,
14903 SelectionDAG &DAG) {
14904 MVT VT = Op->getSimpleValueType(0);
14905 SDValue In = Op->getOperand(0);
14906 MVT InVT = In.getSimpleValueType();
14907 MVT VTElt = VT.getVectorElementType();
14908 MVT InVTElt = InVT.getVectorElementType();
14912 if ((InVTElt == MVT::i1) &&
14913 (((Subtarget->hasBWI() && Subtarget->hasVLX() &&
14914 VT.getSizeInBits() <= 256 && VTElt.getSizeInBits() <= 16)) ||
14916 ((Subtarget->hasBWI() && VT.is512BitVector() &&
14917 VTElt.getSizeInBits() <= 16)) ||
14919 ((Subtarget->hasDQI() && Subtarget->hasVLX() &&
14920 VT.getSizeInBits() <= 256 && VTElt.getSizeInBits() >= 32)) ||
14922 ((Subtarget->hasDQI() && VT.is512BitVector() &&
14923 VTElt.getSizeInBits() >= 32))))
14924 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
14926 unsigned int NumElts = VT.getVectorNumElements();
14928 if (NumElts != 8 && NumElts != 16 && !Subtarget->hasBWI())
14931 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1) {
14932 if (In.getOpcode() == X86ISD::VSEXT || In.getOpcode() == X86ISD::VZEXT)
14933 return DAG.getNode(In.getOpcode(), dl, VT, In.getOperand(0));
14934 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
14937 assert (InVT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
14938 MVT ExtVT = NumElts == 8 ? MVT::v8i64 : MVT::v16i32;
14940 DAG.getConstant(APInt::getAllOnesValue(ExtVT.getScalarSizeInBits()), dl,
14943 DAG.getConstant(APInt::getNullValue(ExtVT.getScalarSizeInBits()), dl, ExtVT);
14945 SDValue V = DAG.getNode(ISD::VSELECT, dl, ExtVT, In, NegOne, Zero);
14946 if (VT.is512BitVector())
14948 return DAG.getNode(X86ISD::VTRUNC, dl, VT, V);
14951 static SDValue LowerSIGN_EXTEND_VECTOR_INREG(SDValue Op,
14952 const X86Subtarget *Subtarget,
14953 SelectionDAG &DAG) {
14954 SDValue In = Op->getOperand(0);
14955 MVT VT = Op->getSimpleValueType(0);
14956 MVT InVT = In.getSimpleValueType();
14957 assert(VT.getSizeInBits() == InVT.getSizeInBits());
14959 MVT InSVT = InVT.getVectorElementType();
14960 assert(VT.getVectorElementType().getSizeInBits() > InSVT.getSizeInBits());
14962 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16)
14964 if (InSVT != MVT::i32 && InSVT != MVT::i16 && InSVT != MVT::i8)
14969 // SSE41 targets can use the pmovsx* instructions directly.
14970 if (Subtarget->hasSSE41())
14971 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
14973 // pre-SSE41 targets unpack lower lanes and then sign-extend using SRAI.
14977 // As SRAI is only available on i16/i32 types, we expand only up to i32
14978 // and handle i64 separately.
14979 while (CurrVT != VT && CurrVT.getVectorElementType() != MVT::i32) {
14980 Curr = DAG.getNode(X86ISD::UNPCKL, dl, CurrVT, DAG.getUNDEF(CurrVT), Curr);
14981 MVT CurrSVT = MVT::getIntegerVT(CurrVT.getScalarSizeInBits() * 2);
14982 CurrVT = MVT::getVectorVT(CurrSVT, CurrVT.getVectorNumElements() / 2);
14983 Curr = DAG.getBitcast(CurrVT, Curr);
14986 SDValue SignExt = Curr;
14987 if (CurrVT != InVT) {
14988 unsigned SignExtShift =
14989 CurrVT.getVectorElementType().getSizeInBits() - InSVT.getSizeInBits();
14990 SignExt = DAG.getNode(X86ISD::VSRAI, dl, CurrVT, Curr,
14991 DAG.getConstant(SignExtShift, dl, MVT::i8));
14997 if (VT == MVT::v2i64 && CurrVT == MVT::v4i32) {
14998 SDValue Sign = DAG.getNode(X86ISD::VSRAI, dl, CurrVT, Curr,
14999 DAG.getConstant(31, dl, MVT::i8));
15000 SDValue Ext = DAG.getVectorShuffle(CurrVT, dl, SignExt, Sign, {0, 4, 1, 5});
15001 return DAG.getBitcast(VT, Ext);
15007 static SDValue LowerSIGN_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
15008 SelectionDAG &DAG) {
15009 MVT VT = Op->getSimpleValueType(0);
15010 SDValue In = Op->getOperand(0);
15011 MVT InVT = In.getSimpleValueType();
15014 if (VT.is512BitVector() || InVT.getVectorElementType() == MVT::i1)
15015 return LowerSIGN_EXTEND_AVX512(Op, Subtarget, DAG);
15017 if ((VT != MVT::v4i64 || InVT != MVT::v4i32) &&
15018 (VT != MVT::v8i32 || InVT != MVT::v8i16) &&
15019 (VT != MVT::v16i16 || InVT != MVT::v16i8))
15022 if (Subtarget->hasInt256())
15023 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
15025 // Optimize vectors in AVX mode
15026 // Sign extend v8i16 to v8i32 and
15029 // Divide input vector into two parts
15030 // for v4i32 the shuffle mask will be { 0, 1, -1, -1} {2, 3, -1, -1}
15031 // use vpmovsx instruction to extend v4i32 -> v2i64; v8i16 -> v4i32
15032 // concat the vectors to original VT
15034 unsigned NumElems = InVT.getVectorNumElements();
15035 SDValue Undef = DAG.getUNDEF(InVT);
15037 SmallVector<int,8> ShufMask1(NumElems, -1);
15038 for (unsigned i = 0; i != NumElems/2; ++i)
15041 SDValue OpLo = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask1[0]);
15043 SmallVector<int,8> ShufMask2(NumElems, -1);
15044 for (unsigned i = 0; i != NumElems/2; ++i)
15045 ShufMask2[i] = i + NumElems/2;
15047 SDValue OpHi = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask2[0]);
15049 MVT HalfVT = MVT::getVectorVT(VT.getVectorElementType(),
15050 VT.getVectorNumElements()/2);
15052 OpLo = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpLo);
15053 OpHi = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpHi);
15055 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
15058 // Lower vector extended loads using a shuffle. If SSSE3 is not available we
15059 // may emit an illegal shuffle but the expansion is still better than scalar
15060 // code. We generate X86ISD::VSEXT for SEXTLOADs if it's available, otherwise
15061 // we'll emit a shuffle and a arithmetic shift.
15062 // FIXME: Is the expansion actually better than scalar code? It doesn't seem so.
15063 // TODO: It is possible to support ZExt by zeroing the undef values during
15064 // the shuffle phase or after the shuffle.
15065 static SDValue LowerExtendedLoad(SDValue Op, const X86Subtarget *Subtarget,
15066 SelectionDAG &DAG) {
15067 MVT RegVT = Op.getSimpleValueType();
15068 assert(RegVT.isVector() && "We only custom lower vector sext loads.");
15069 assert(RegVT.isInteger() &&
15070 "We only custom lower integer vector sext loads.");
15072 // Nothing useful we can do without SSE2 shuffles.
15073 assert(Subtarget->hasSSE2() && "We only custom lower sext loads with SSE2.");
15075 LoadSDNode *Ld = cast<LoadSDNode>(Op.getNode());
15077 EVT MemVT = Ld->getMemoryVT();
15078 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
15079 unsigned RegSz = RegVT.getSizeInBits();
15081 ISD::LoadExtType Ext = Ld->getExtensionType();
15083 assert((Ext == ISD::EXTLOAD || Ext == ISD::SEXTLOAD)
15084 && "Only anyext and sext are currently implemented.");
15085 assert(MemVT != RegVT && "Cannot extend to the same type");
15086 assert(MemVT.isVector() && "Must load a vector from memory");
15088 unsigned NumElems = RegVT.getVectorNumElements();
15089 unsigned MemSz = MemVT.getSizeInBits();
15090 assert(RegSz > MemSz && "Register size must be greater than the mem size");
15092 if (Ext == ISD::SEXTLOAD && RegSz == 256 && !Subtarget->hasInt256()) {
15093 // The only way in which we have a legal 256-bit vector result but not the
15094 // integer 256-bit operations needed to directly lower a sextload is if we
15095 // have AVX1 but not AVX2. In that case, we can always emit a sextload to
15096 // a 128-bit vector and a normal sign_extend to 256-bits that should get
15097 // correctly legalized. We do this late to allow the canonical form of
15098 // sextload to persist throughout the rest of the DAG combiner -- it wants
15099 // to fold together any extensions it can, and so will fuse a sign_extend
15100 // of an sextload into a sextload targeting a wider value.
15102 if (MemSz == 128) {
15103 // Just switch this to a normal load.
15104 assert(TLI.isTypeLegal(MemVT) && "If the memory type is a 128-bit type, "
15105 "it must be a legal 128-bit vector "
15107 Load = DAG.getLoad(MemVT, dl, Ld->getChain(), Ld->getBasePtr(),
15108 Ld->getPointerInfo(), Ld->isVolatile(), Ld->isNonTemporal(),
15109 Ld->isInvariant(), Ld->getAlignment());
15111 assert(MemSz < 128 &&
15112 "Can't extend a type wider than 128 bits to a 256 bit vector!");
15113 // Do an sext load to a 128-bit vector type. We want to use the same
15114 // number of elements, but elements half as wide. This will end up being
15115 // recursively lowered by this routine, but will succeed as we definitely
15116 // have all the necessary features if we're using AVX1.
15118 EVT::getIntegerVT(*DAG.getContext(), RegVT.getScalarSizeInBits() / 2);
15119 EVT HalfVecVT = EVT::getVectorVT(*DAG.getContext(), HalfEltVT, NumElems);
15121 DAG.getExtLoad(Ext, dl, HalfVecVT, Ld->getChain(), Ld->getBasePtr(),
15122 Ld->getPointerInfo(), MemVT, Ld->isVolatile(),
15123 Ld->isNonTemporal(), Ld->isInvariant(),
15124 Ld->getAlignment());
15127 // Replace chain users with the new chain.
15128 assert(Load->getNumValues() == 2 && "Loads must carry a chain!");
15129 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), Load.getValue(1));
15131 // Finally, do a normal sign-extend to the desired register.
15132 return DAG.getSExtOrTrunc(Load, dl, RegVT);
15135 // All sizes must be a power of two.
15136 assert(isPowerOf2_32(RegSz * MemSz * NumElems) &&
15137 "Non-power-of-two elements are not custom lowered!");
15139 // Attempt to load the original value using scalar loads.
15140 // Find the largest scalar type that divides the total loaded size.
15141 MVT SclrLoadTy = MVT::i8;
15142 for (MVT Tp : MVT::integer_valuetypes()) {
15143 if (TLI.isTypeLegal(Tp) && ((MemSz % Tp.getSizeInBits()) == 0)) {
15148 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
15149 if (TLI.isTypeLegal(MVT::f64) && SclrLoadTy.getSizeInBits() < 64 &&
15151 SclrLoadTy = MVT::f64;
15153 // Calculate the number of scalar loads that we need to perform
15154 // in order to load our vector from memory.
15155 unsigned NumLoads = MemSz / SclrLoadTy.getSizeInBits();
15157 assert((Ext != ISD::SEXTLOAD || NumLoads == 1) &&
15158 "Can only lower sext loads with a single scalar load!");
15160 unsigned loadRegZize = RegSz;
15161 if (Ext == ISD::SEXTLOAD && RegSz >= 256)
15164 // Represent our vector as a sequence of elements which are the
15165 // largest scalar that we can load.
15166 EVT LoadUnitVecVT = EVT::getVectorVT(
15167 *DAG.getContext(), SclrLoadTy, loadRegZize / SclrLoadTy.getSizeInBits());
15169 // Represent the data using the same element type that is stored in
15170 // memory. In practice, we ''widen'' MemVT.
15172 EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
15173 loadRegZize / MemVT.getScalarSizeInBits());
15175 assert(WideVecVT.getSizeInBits() == LoadUnitVecVT.getSizeInBits() &&
15176 "Invalid vector type");
15178 // We can't shuffle using an illegal type.
15179 assert(TLI.isTypeLegal(WideVecVT) &&
15180 "We only lower types that form legal widened vector types");
15182 SmallVector<SDValue, 8> Chains;
15183 SDValue Ptr = Ld->getBasePtr();
15184 SDValue Increment = DAG.getConstant(SclrLoadTy.getSizeInBits() / 8, dl,
15185 TLI.getPointerTy(DAG.getDataLayout()));
15186 SDValue Res = DAG.getUNDEF(LoadUnitVecVT);
15188 for (unsigned i = 0; i < NumLoads; ++i) {
15189 // Perform a single load.
15190 SDValue ScalarLoad =
15191 DAG.getLoad(SclrLoadTy, dl, Ld->getChain(), Ptr, Ld->getPointerInfo(),
15192 Ld->isVolatile(), Ld->isNonTemporal(), Ld->isInvariant(),
15193 Ld->getAlignment());
15194 Chains.push_back(ScalarLoad.getValue(1));
15195 // Create the first element type using SCALAR_TO_VECTOR in order to avoid
15196 // another round of DAGCombining.
15198 Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LoadUnitVecVT, ScalarLoad);
15200 Res = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, LoadUnitVecVT, Res,
15201 ScalarLoad, DAG.getIntPtrConstant(i, dl));
15203 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
15206 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
15208 // Bitcast the loaded value to a vector of the original element type, in
15209 // the size of the target vector type.
15210 SDValue SlicedVec = DAG.getBitcast(WideVecVT, Res);
15211 unsigned SizeRatio = RegSz / MemSz;
15213 if (Ext == ISD::SEXTLOAD) {
15214 // If we have SSE4.1, we can directly emit a VSEXT node.
15215 if (Subtarget->hasSSE41()) {
15216 SDValue Sext = DAG.getNode(X86ISD::VSEXT, dl, RegVT, SlicedVec);
15217 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
15221 // Otherwise we'll use SIGN_EXTEND_VECTOR_INREG to sign extend the lowest
15223 assert(TLI.isOperationLegalOrCustom(ISD::SIGN_EXTEND_VECTOR_INREG, RegVT) &&
15224 "We can't implement a sext load without SIGN_EXTEND_VECTOR_INREG!");
15226 SDValue Shuff = DAG.getSignExtendVectorInReg(SlicedVec, dl, RegVT);
15227 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
15231 // Redistribute the loaded elements into the different locations.
15232 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
15233 for (unsigned i = 0; i != NumElems; ++i)
15234 ShuffleVec[i * SizeRatio] = i;
15236 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec,
15237 DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
15239 // Bitcast to the requested type.
15240 Shuff = DAG.getBitcast(RegVT, Shuff);
15241 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
15245 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
15246 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
15247 // from the AND / OR.
15248 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
15249 Opc = Op.getOpcode();
15250 if (Opc != ISD::OR && Opc != ISD::AND)
15252 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
15253 Op.getOperand(0).hasOneUse() &&
15254 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
15255 Op.getOperand(1).hasOneUse());
15258 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
15259 // 1 and that the SETCC node has a single use.
15260 static bool isXor1OfSetCC(SDValue Op) {
15261 if (Op.getOpcode() != ISD::XOR)
15263 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
15264 if (N1C && N1C->getAPIntValue() == 1) {
15265 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
15266 Op.getOperand(0).hasOneUse();
15271 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
15272 bool addTest = true;
15273 SDValue Chain = Op.getOperand(0);
15274 SDValue Cond = Op.getOperand(1);
15275 SDValue Dest = Op.getOperand(2);
15278 bool Inverted = false;
15280 if (Cond.getOpcode() == ISD::SETCC) {
15281 // Check for setcc([su]{add,sub,mul}o == 0).
15282 if (cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETEQ &&
15283 isa<ConstantSDNode>(Cond.getOperand(1)) &&
15284 cast<ConstantSDNode>(Cond.getOperand(1))->isNullValue() &&
15285 Cond.getOperand(0).getResNo() == 1 &&
15286 (Cond.getOperand(0).getOpcode() == ISD::SADDO ||
15287 Cond.getOperand(0).getOpcode() == ISD::UADDO ||
15288 Cond.getOperand(0).getOpcode() == ISD::SSUBO ||
15289 Cond.getOperand(0).getOpcode() == ISD::USUBO ||
15290 Cond.getOperand(0).getOpcode() == ISD::SMULO ||
15291 Cond.getOperand(0).getOpcode() == ISD::UMULO)) {
15293 Cond = Cond.getOperand(0);
15295 SDValue NewCond = LowerSETCC(Cond, DAG);
15296 if (NewCond.getNode())
15301 // FIXME: LowerXALUO doesn't handle these!!
15302 else if (Cond.getOpcode() == X86ISD::ADD ||
15303 Cond.getOpcode() == X86ISD::SUB ||
15304 Cond.getOpcode() == X86ISD::SMUL ||
15305 Cond.getOpcode() == X86ISD::UMUL)
15306 Cond = LowerXALUO(Cond, DAG);
15309 // Look pass (and (setcc_carry (cmp ...)), 1).
15310 if (Cond.getOpcode() == ISD::AND &&
15311 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
15312 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
15313 if (C && C->getAPIntValue() == 1)
15314 Cond = Cond.getOperand(0);
15317 // If condition flag is set by a X86ISD::CMP, then use it as the condition
15318 // setting operand in place of the X86ISD::SETCC.
15319 unsigned CondOpcode = Cond.getOpcode();
15320 if (CondOpcode == X86ISD::SETCC ||
15321 CondOpcode == X86ISD::SETCC_CARRY) {
15322 CC = Cond.getOperand(0);
15324 SDValue Cmp = Cond.getOperand(1);
15325 unsigned Opc = Cmp.getOpcode();
15326 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
15327 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
15331 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
15335 // These can only come from an arithmetic instruction with overflow,
15336 // e.g. SADDO, UADDO.
15337 Cond = Cond.getNode()->getOperand(1);
15343 CondOpcode = Cond.getOpcode();
15344 if (CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
15345 CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
15346 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
15347 Cond.getOperand(0).getValueType() != MVT::i8)) {
15348 SDValue LHS = Cond.getOperand(0);
15349 SDValue RHS = Cond.getOperand(1);
15350 unsigned X86Opcode;
15353 // Keep this in sync with LowerXALUO, otherwise we might create redundant
15354 // instructions that can't be removed afterwards (i.e. X86ISD::ADD and
15356 switch (CondOpcode) {
15357 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
15359 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
15361 X86Opcode = X86ISD::INC; X86Cond = X86::COND_O;
15364 X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
15365 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
15367 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
15369 X86Opcode = X86ISD::DEC; X86Cond = X86::COND_O;
15372 X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
15373 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
15374 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
15375 default: llvm_unreachable("unexpected overflowing operator");
15378 X86Cond = X86::GetOppositeBranchCondition((X86::CondCode)X86Cond);
15379 if (CondOpcode == ISD::UMULO)
15380 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
15383 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
15385 SDValue X86Op = DAG.getNode(X86Opcode, dl, VTs, LHS, RHS);
15387 if (CondOpcode == ISD::UMULO)
15388 Cond = X86Op.getValue(2);
15390 Cond = X86Op.getValue(1);
15392 CC = DAG.getConstant(X86Cond, dl, MVT::i8);
15396 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
15397 SDValue Cmp = Cond.getOperand(0).getOperand(1);
15398 if (CondOpc == ISD::OR) {
15399 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
15400 // two branches instead of an explicit OR instruction with a
15402 if (Cmp == Cond.getOperand(1).getOperand(1) &&
15403 isX86LogicalCmp(Cmp)) {
15404 CC = Cond.getOperand(0).getOperand(0);
15405 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15406 Chain, Dest, CC, Cmp);
15407 CC = Cond.getOperand(1).getOperand(0);
15411 } else { // ISD::AND
15412 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
15413 // two branches instead of an explicit AND instruction with a
15414 // separate test. However, we only do this if this block doesn't
15415 // have a fall-through edge, because this requires an explicit
15416 // jmp when the condition is false.
15417 if (Cmp == Cond.getOperand(1).getOperand(1) &&
15418 isX86LogicalCmp(Cmp) &&
15419 Op.getNode()->hasOneUse()) {
15420 X86::CondCode CCode =
15421 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
15422 CCode = X86::GetOppositeBranchCondition(CCode);
15423 CC = DAG.getConstant(CCode, dl, MVT::i8);
15424 SDNode *User = *Op.getNode()->use_begin();
15425 // Look for an unconditional branch following this conditional branch.
15426 // We need this because we need to reverse the successors in order
15427 // to implement FCMP_OEQ.
15428 if (User->getOpcode() == ISD::BR) {
15429 SDValue FalseBB = User->getOperand(1);
15431 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
15432 assert(NewBR == User);
15436 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15437 Chain, Dest, CC, Cmp);
15438 X86::CondCode CCode =
15439 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
15440 CCode = X86::GetOppositeBranchCondition(CCode);
15441 CC = DAG.getConstant(CCode, dl, MVT::i8);
15447 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
15448 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
15449 // It should be transformed during dag combiner except when the condition
15450 // is set by a arithmetics with overflow node.
15451 X86::CondCode CCode =
15452 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
15453 CCode = X86::GetOppositeBranchCondition(CCode);
15454 CC = DAG.getConstant(CCode, dl, MVT::i8);
15455 Cond = Cond.getOperand(0).getOperand(1);
15457 } else if (Cond.getOpcode() == ISD::SETCC &&
15458 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETOEQ) {
15459 // For FCMP_OEQ, we can emit
15460 // two branches instead of an explicit AND instruction with a
15461 // separate test. However, we only do this if this block doesn't
15462 // have a fall-through edge, because this requires an explicit
15463 // jmp when the condition is false.
15464 if (Op.getNode()->hasOneUse()) {
15465 SDNode *User = *Op.getNode()->use_begin();
15466 // Look for an unconditional branch following this conditional branch.
15467 // We need this because we need to reverse the successors in order
15468 // to implement FCMP_OEQ.
15469 if (User->getOpcode() == ISD::BR) {
15470 SDValue FalseBB = User->getOperand(1);
15472 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
15473 assert(NewBR == User);
15477 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
15478 Cond.getOperand(0), Cond.getOperand(1));
15479 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
15480 CC = DAG.getConstant(X86::COND_NE, dl, MVT::i8);
15481 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15482 Chain, Dest, CC, Cmp);
15483 CC = DAG.getConstant(X86::COND_P, dl, MVT::i8);
15488 } else if (Cond.getOpcode() == ISD::SETCC &&
15489 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETUNE) {
15490 // For FCMP_UNE, we can emit
15491 // two branches instead of an explicit AND instruction with a
15492 // separate test. However, we only do this if this block doesn't
15493 // have a fall-through edge, because this requires an explicit
15494 // jmp when the condition is false.
15495 if (Op.getNode()->hasOneUse()) {
15496 SDNode *User = *Op.getNode()->use_begin();
15497 // Look for an unconditional branch following this conditional branch.
15498 // We need this because we need to reverse the successors in order
15499 // to implement FCMP_UNE.
15500 if (User->getOpcode() == ISD::BR) {
15501 SDValue FalseBB = User->getOperand(1);
15503 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
15504 assert(NewBR == User);
15507 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
15508 Cond.getOperand(0), Cond.getOperand(1));
15509 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
15510 CC = DAG.getConstant(X86::COND_NE, dl, MVT::i8);
15511 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15512 Chain, Dest, CC, Cmp);
15513 CC = DAG.getConstant(X86::COND_NP, dl, MVT::i8);
15523 // Look pass the truncate if the high bits are known zero.
15524 if (isTruncWithZeroHighBitsInput(Cond, DAG))
15525 Cond = Cond.getOperand(0);
15527 // We know the result of AND is compared against zero. Try to match
15529 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
15530 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
15531 if (NewSetCC.getNode()) {
15532 CC = NewSetCC.getOperand(0);
15533 Cond = NewSetCC.getOperand(1);
15540 X86::CondCode X86Cond = Inverted ? X86::COND_E : X86::COND_NE;
15541 CC = DAG.getConstant(X86Cond, dl, MVT::i8);
15542 Cond = EmitTest(Cond, X86Cond, dl, DAG);
15544 Cond = ConvertCmpIfNecessary(Cond, DAG);
15545 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15546 Chain, Dest, CC, Cond);
15549 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
15550 // Calls to _alloca are needed to probe the stack when allocating more than 4k
15551 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
15552 // that the guard pages used by the OS virtual memory manager are allocated in
15553 // correct sequence.
15555 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
15556 SelectionDAG &DAG) const {
15557 MachineFunction &MF = DAG.getMachineFunction();
15558 bool SplitStack = MF.shouldSplitStack();
15559 bool Lower = (Subtarget->isOSWindows() && !Subtarget->isTargetMachO()) ||
15564 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
15565 SDNode* Node = Op.getNode();
15567 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
15568 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
15569 " not tell us which reg is the stack pointer!");
15570 EVT VT = Node->getValueType(0);
15571 SDValue Tmp1 = SDValue(Node, 0);
15572 SDValue Tmp2 = SDValue(Node, 1);
15573 SDValue Tmp3 = Node->getOperand(2);
15574 SDValue Chain = Tmp1.getOperand(0);
15576 // Chain the dynamic stack allocation so that it doesn't modify the stack
15577 // pointer when other instructions are using the stack.
15578 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, dl, true),
15581 SDValue Size = Tmp2.getOperand(1);
15582 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT);
15583 Chain = SP.getValue(1);
15584 unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue();
15585 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
15586 unsigned StackAlign = TFI.getStackAlignment();
15587 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value
15588 if (Align > StackAlign)
15589 Tmp1 = DAG.getNode(ISD::AND, dl, VT, Tmp1,
15590 DAG.getConstant(-(uint64_t)Align, dl, VT));
15591 Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); // Output chain
15593 Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, dl, true),
15594 DAG.getIntPtrConstant(0, dl, true), SDValue(),
15597 SDValue Ops[2] = { Tmp1, Tmp2 };
15598 return DAG.getMergeValues(Ops, dl);
15602 SDValue Chain = Op.getOperand(0);
15603 SDValue Size = Op.getOperand(1);
15604 unsigned Align = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
15605 EVT VT = Op.getNode()->getValueType(0);
15607 bool Is64Bit = Subtarget->is64Bit();
15608 MVT SPTy = getPointerTy(DAG.getDataLayout());
15611 MachineRegisterInfo &MRI = MF.getRegInfo();
15614 // The 64 bit implementation of segmented stacks needs to clobber both r10
15615 // r11. This makes it impossible to use it along with nested parameters.
15616 const Function *F = MF.getFunction();
15618 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
15620 if (I->hasNestAttr())
15621 report_fatal_error("Cannot use segmented stacks with functions that "
15622 "have nested arguments.");
15625 const TargetRegisterClass *AddrRegClass = getRegClassFor(SPTy);
15626 unsigned Vreg = MRI.createVirtualRegister(AddrRegClass);
15627 Chain = DAG.getCopyToReg(Chain, dl, Vreg, Size);
15628 SDValue Value = DAG.getNode(X86ISD::SEG_ALLOCA, dl, SPTy, Chain,
15629 DAG.getRegister(Vreg, SPTy));
15630 SDValue Ops1[2] = { Value, Chain };
15631 return DAG.getMergeValues(Ops1, dl);
15634 const unsigned Reg = (Subtarget->isTarget64BitLP64() ? X86::RAX : X86::EAX);
15636 Chain = DAG.getCopyToReg(Chain, dl, Reg, Size, Flag);
15637 Flag = Chain.getValue(1);
15638 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
15640 Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag);
15642 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
15643 unsigned SPReg = RegInfo->getStackRegister();
15644 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, SPTy);
15645 Chain = SP.getValue(1);
15648 SP = DAG.getNode(ISD::AND, dl, VT, SP.getValue(0),
15649 DAG.getConstant(-(uint64_t)Align, dl, VT));
15650 Chain = DAG.getCopyToReg(Chain, dl, SPReg, SP);
15653 SDValue Ops1[2] = { SP, Chain };
15654 return DAG.getMergeValues(Ops1, dl);
15658 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
15659 MachineFunction &MF = DAG.getMachineFunction();
15660 auto PtrVT = getPointerTy(MF.getDataLayout());
15661 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
15663 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
15666 if (!Subtarget->is64Bit() ||
15667 Subtarget->isCallingConvWin64(MF.getFunction()->getCallingConv())) {
15668 // vastart just stores the address of the VarArgsFrameIndex slot into the
15669 // memory location argument.
15670 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
15671 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
15672 MachinePointerInfo(SV), false, false, 0);
15676 // gp_offset (0 - 6 * 8)
15677 // fp_offset (48 - 48 + 8 * 16)
15678 // overflow_arg_area (point to parameters coming in memory).
15680 SmallVector<SDValue, 8> MemOps;
15681 SDValue FIN = Op.getOperand(1);
15683 SDValue Store = DAG.getStore(Op.getOperand(0), DL,
15684 DAG.getConstant(FuncInfo->getVarArgsGPOffset(),
15686 FIN, MachinePointerInfo(SV), false, false, 0);
15687 MemOps.push_back(Store);
15690 FIN = DAG.getNode(ISD::ADD, DL, PtrVT, FIN, DAG.getIntPtrConstant(4, DL));
15691 Store = DAG.getStore(Op.getOperand(0), DL,
15692 DAG.getConstant(FuncInfo->getVarArgsFPOffset(), DL,
15694 FIN, MachinePointerInfo(SV, 4), false, false, 0);
15695 MemOps.push_back(Store);
15697 // Store ptr to overflow_arg_area
15698 FIN = DAG.getNode(ISD::ADD, DL, PtrVT, FIN, DAG.getIntPtrConstant(4, DL));
15699 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
15700 Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN,
15701 MachinePointerInfo(SV, 8),
15703 MemOps.push_back(Store);
15705 // Store ptr to reg_save_area.
15706 FIN = DAG.getNode(ISD::ADD, DL, PtrVT, FIN, DAG.getIntPtrConstant(
15707 Subtarget->isTarget64BitLP64() ? 8 : 4, DL));
15708 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(), PtrVT);
15709 Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN, MachinePointerInfo(
15710 SV, Subtarget->isTarget64BitLP64() ? 16 : 12), false, false, 0);
15711 MemOps.push_back(Store);
15712 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps);
15715 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
15716 assert(Subtarget->is64Bit() &&
15717 "LowerVAARG only handles 64-bit va_arg!");
15718 assert(Op.getNode()->getNumOperands() == 4);
15720 MachineFunction &MF = DAG.getMachineFunction();
15721 if (Subtarget->isCallingConvWin64(MF.getFunction()->getCallingConv()))
15722 // The Win64 ABI uses char* instead of a structure.
15723 return DAG.expandVAArg(Op.getNode());
15725 SDValue Chain = Op.getOperand(0);
15726 SDValue SrcPtr = Op.getOperand(1);
15727 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
15728 unsigned Align = Op.getConstantOperandVal(3);
15731 EVT ArgVT = Op.getNode()->getValueType(0);
15732 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
15733 uint32_t ArgSize = DAG.getDataLayout().getTypeAllocSize(ArgTy);
15736 // Decide which area this value should be read from.
15737 // TODO: Implement the AMD64 ABI in its entirety. This simple
15738 // selection mechanism works only for the basic types.
15739 if (ArgVT == MVT::f80) {
15740 llvm_unreachable("va_arg for f80 not yet implemented");
15741 } else if (ArgVT.isFloatingPoint() && ArgSize <= 16 /*bytes*/) {
15742 ArgMode = 2; // Argument passed in XMM register. Use fp_offset.
15743 } else if (ArgVT.isInteger() && ArgSize <= 32 /*bytes*/) {
15744 ArgMode = 1; // Argument passed in GPR64 register(s). Use gp_offset.
15746 llvm_unreachable("Unhandled argument type in LowerVAARG");
15749 if (ArgMode == 2) {
15750 // Sanity Check: Make sure using fp_offset makes sense.
15751 assert(!Subtarget->useSoftFloat() &&
15752 !(MF.getFunction()->hasFnAttribute(Attribute::NoImplicitFloat)) &&
15753 Subtarget->hasSSE1());
15756 // Insert VAARG_64 node into the DAG
15757 // VAARG_64 returns two values: Variable Argument Address, Chain
15758 SDValue InstOps[] = {Chain, SrcPtr, DAG.getConstant(ArgSize, dl, MVT::i32),
15759 DAG.getConstant(ArgMode, dl, MVT::i8),
15760 DAG.getConstant(Align, dl, MVT::i32)};
15761 SDVTList VTs = DAG.getVTList(getPointerTy(DAG.getDataLayout()), MVT::Other);
15762 SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl,
15763 VTs, InstOps, MVT::i64,
15764 MachinePointerInfo(SV),
15766 /*Volatile=*/false,
15768 /*WriteMem=*/true);
15769 Chain = VAARG.getValue(1);
15771 // Load the next argument and return it
15772 return DAG.getLoad(ArgVT, dl,
15775 MachinePointerInfo(),
15776 false, false, false, 0);
15779 static SDValue LowerVACOPY(SDValue Op, const X86Subtarget *Subtarget,
15780 SelectionDAG &DAG) {
15781 // X86-64 va_list is a struct { i32, i32, i8*, i8* }, except on Windows,
15782 // where a va_list is still an i8*.
15783 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
15784 if (Subtarget->isCallingConvWin64(
15785 DAG.getMachineFunction().getFunction()->getCallingConv()))
15786 // Probably a Win64 va_copy.
15787 return DAG.expandVACopy(Op.getNode());
15789 SDValue Chain = Op.getOperand(0);
15790 SDValue DstPtr = Op.getOperand(1);
15791 SDValue SrcPtr = Op.getOperand(2);
15792 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
15793 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
15796 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr,
15797 DAG.getIntPtrConstant(24, DL), 8, /*isVolatile*/false,
15799 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
15802 // getTargetVShiftByConstNode - Handle vector element shifts where the shift
15803 // amount is a constant. Takes immediate version of shift as input.
15804 static SDValue getTargetVShiftByConstNode(unsigned Opc, SDLoc dl, MVT VT,
15805 SDValue SrcOp, uint64_t ShiftAmt,
15806 SelectionDAG &DAG) {
15807 MVT ElementType = VT.getVectorElementType();
15809 // Fold this packed shift into its first operand if ShiftAmt is 0.
15813 // Check for ShiftAmt >= element width
15814 if (ShiftAmt >= ElementType.getSizeInBits()) {
15815 if (Opc == X86ISD::VSRAI)
15816 ShiftAmt = ElementType.getSizeInBits() - 1;
15818 return DAG.getConstant(0, dl, VT);
15821 assert((Opc == X86ISD::VSHLI || Opc == X86ISD::VSRLI || Opc == X86ISD::VSRAI)
15822 && "Unknown target vector shift-by-constant node");
15824 // Fold this packed vector shift into a build vector if SrcOp is a
15825 // vector of Constants or UNDEFs, and SrcOp valuetype is the same as VT.
15826 if (VT == SrcOp.getSimpleValueType() &&
15827 ISD::isBuildVectorOfConstantSDNodes(SrcOp.getNode())) {
15828 SmallVector<SDValue, 8> Elts;
15829 unsigned NumElts = SrcOp->getNumOperands();
15830 ConstantSDNode *ND;
15833 default: llvm_unreachable(nullptr);
15834 case X86ISD::VSHLI:
15835 for (unsigned i=0; i!=NumElts; ++i) {
15836 SDValue CurrentOp = SrcOp->getOperand(i);
15837 if (CurrentOp->getOpcode() == ISD::UNDEF) {
15838 Elts.push_back(CurrentOp);
15841 ND = cast<ConstantSDNode>(CurrentOp);
15842 const APInt &C = ND->getAPIntValue();
15843 Elts.push_back(DAG.getConstant(C.shl(ShiftAmt), dl, ElementType));
15846 case X86ISD::VSRLI:
15847 for (unsigned i=0; i!=NumElts; ++i) {
15848 SDValue CurrentOp = SrcOp->getOperand(i);
15849 if (CurrentOp->getOpcode() == ISD::UNDEF) {
15850 Elts.push_back(CurrentOp);
15853 ND = cast<ConstantSDNode>(CurrentOp);
15854 const APInt &C = ND->getAPIntValue();
15855 Elts.push_back(DAG.getConstant(C.lshr(ShiftAmt), dl, ElementType));
15858 case X86ISD::VSRAI:
15859 for (unsigned i=0; i!=NumElts; ++i) {
15860 SDValue CurrentOp = SrcOp->getOperand(i);
15861 if (CurrentOp->getOpcode() == ISD::UNDEF) {
15862 Elts.push_back(CurrentOp);
15865 ND = cast<ConstantSDNode>(CurrentOp);
15866 const APInt &C = ND->getAPIntValue();
15867 Elts.push_back(DAG.getConstant(C.ashr(ShiftAmt), dl, ElementType));
15872 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
15875 return DAG.getNode(Opc, dl, VT, SrcOp,
15876 DAG.getConstant(ShiftAmt, dl, MVT::i8));
15879 // getTargetVShiftNode - Handle vector element shifts where the shift amount
15880 // may or may not be a constant. Takes immediate version of shift as input.
15881 static SDValue getTargetVShiftNode(unsigned Opc, SDLoc dl, MVT VT,
15882 SDValue SrcOp, SDValue ShAmt,
15883 SelectionDAG &DAG) {
15884 MVT SVT = ShAmt.getSimpleValueType();
15885 assert((SVT == MVT::i32 || SVT == MVT::i64) && "Unexpected value type!");
15887 // Catch shift-by-constant.
15888 if (ConstantSDNode *CShAmt = dyn_cast<ConstantSDNode>(ShAmt))
15889 return getTargetVShiftByConstNode(Opc, dl, VT, SrcOp,
15890 CShAmt->getZExtValue(), DAG);
15892 // Change opcode to non-immediate version
15894 default: llvm_unreachable("Unknown target vector shift node");
15895 case X86ISD::VSHLI: Opc = X86ISD::VSHL; break;
15896 case X86ISD::VSRLI: Opc = X86ISD::VSRL; break;
15897 case X86ISD::VSRAI: Opc = X86ISD::VSRA; break;
15900 const X86Subtarget &Subtarget =
15901 static_cast<const X86Subtarget &>(DAG.getSubtarget());
15902 if (Subtarget.hasSSE41() && ShAmt.getOpcode() == ISD::ZERO_EXTEND &&
15903 ShAmt.getOperand(0).getSimpleValueType() == MVT::i16) {
15904 // Let the shuffle legalizer expand this shift amount node.
15905 SDValue Op0 = ShAmt.getOperand(0);
15906 Op0 = DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(Op0), MVT::v8i16, Op0);
15907 ShAmt = getShuffleVectorZeroOrUndef(Op0, 0, true, &Subtarget, DAG);
15909 // Need to build a vector containing shift amount.
15910 // SSE/AVX packed shifts only use the lower 64-bit of the shift count.
15911 SmallVector<SDValue, 4> ShOps;
15912 ShOps.push_back(ShAmt);
15913 if (SVT == MVT::i32) {
15914 ShOps.push_back(DAG.getConstant(0, dl, SVT));
15915 ShOps.push_back(DAG.getUNDEF(SVT));
15917 ShOps.push_back(DAG.getUNDEF(SVT));
15919 MVT BVT = SVT == MVT::i32 ? MVT::v4i32 : MVT::v2i64;
15920 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, BVT, ShOps);
15923 // The return type has to be a 128-bit type with the same element
15924 // type as the input type.
15925 MVT EltVT = VT.getVectorElementType();
15926 MVT ShVT = MVT::getVectorVT(EltVT, 128/EltVT.getSizeInBits());
15928 ShAmt = DAG.getBitcast(ShVT, ShAmt);
15929 return DAG.getNode(Opc, dl, VT, SrcOp, ShAmt);
15932 /// \brief Return (and \p Op, \p Mask) for compare instructions or
15933 /// (vselect \p Mask, \p Op, \p PreservedSrc) for others along with the
15934 /// necessary casting or extending for \p Mask when lowering masking intrinsics
15935 static SDValue getVectorMaskingNode(SDValue Op, SDValue Mask,
15936 SDValue PreservedSrc,
15937 const X86Subtarget *Subtarget,
15938 SelectionDAG &DAG) {
15939 MVT VT = Op.getSimpleValueType();
15940 MVT MaskVT = MVT::getVectorVT(MVT::i1, VT.getVectorNumElements());
15942 unsigned OpcodeSelect = ISD::VSELECT;
15945 if (isAllOnes(Mask))
15948 if (MaskVT.bitsGT(Mask.getSimpleValueType())) {
15949 MVT newMaskVT = MVT::getIntegerVT(MaskVT.getSizeInBits());
15950 VMask = DAG.getBitcast(MaskVT,
15951 DAG.getNode(ISD::ANY_EXTEND, dl, newMaskVT, Mask));
15953 MVT BitcastVT = MVT::getVectorVT(MVT::i1,
15954 Mask.getSimpleValueType().getSizeInBits());
15955 // In case when MaskVT equals v2i1 or v4i1, low 2 or 4 elements
15956 // are extracted by EXTRACT_SUBVECTOR.
15957 VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
15958 DAG.getBitcast(BitcastVT, Mask),
15959 DAG.getIntPtrConstant(0, dl));
15962 switch (Op.getOpcode()) {
15964 case X86ISD::PCMPEQM:
15965 case X86ISD::PCMPGTM:
15967 case X86ISD::CMPMU:
15968 return DAG.getNode(ISD::AND, dl, VT, Op, VMask);
15969 case X86ISD::VFPCLASS:
15970 return DAG.getNode(ISD::OR, dl, VT, Op, VMask);
15971 case X86ISD::VTRUNC:
15972 case X86ISD::VTRUNCS:
15973 case X86ISD::VTRUNCUS:
15974 // We can't use ISD::VSELECT here because it is not always "Legal"
15975 // for the destination type. For example vpmovqb require only AVX512
15976 // and vselect that can operate on byte element type require BWI
15977 OpcodeSelect = X86ISD::SELECT;
15980 if (PreservedSrc.getOpcode() == ISD::UNDEF)
15981 PreservedSrc = getZeroVector(VT, Subtarget, DAG, dl);
15982 return DAG.getNode(OpcodeSelect, dl, VT, VMask, Op, PreservedSrc);
15985 /// \brief Creates an SDNode for a predicated scalar operation.
15986 /// \returns (X86vselect \p Mask, \p Op, \p PreservedSrc).
15987 /// The mask is coming as MVT::i8 and it should be truncated
15988 /// to MVT::i1 while lowering masking intrinsics.
15989 /// The main difference between ScalarMaskingNode and VectorMaskingNode is using
15990 /// "X86select" instead of "vselect". We just can't create the "vselect" node
15991 /// for a scalar instruction.
15992 static SDValue getScalarMaskingNode(SDValue Op, SDValue Mask,
15993 SDValue PreservedSrc,
15994 const X86Subtarget *Subtarget,
15995 SelectionDAG &DAG) {
15996 if (isAllOnes(Mask))
15999 MVT VT = Op.getSimpleValueType();
16001 // The mask should be of type MVT::i1
16002 SDValue IMask = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, Mask);
16004 if (Op.getOpcode() == X86ISD::FSETCC)
16005 return DAG.getNode(ISD::AND, dl, VT, Op, IMask);
16006 if (Op.getOpcode() == X86ISD::VFPCLASS)
16007 return DAG.getNode(ISD::OR, dl, VT, Op, IMask);
16009 if (PreservedSrc.getOpcode() == ISD::UNDEF)
16010 PreservedSrc = getZeroVector(VT, Subtarget, DAG, dl);
16011 return DAG.getNode(X86ISD::SELECT, dl, VT, IMask, Op, PreservedSrc);
16014 static int getSEHRegistrationNodeSize(const Function *Fn) {
16015 if (!Fn->hasPersonalityFn())
16016 report_fatal_error(
16017 "querying registration node size for function without personality");
16018 // The RegNodeSize is 6 32-bit words for SEH and 4 for C++ EH. See
16019 // WinEHStatePass for the full struct definition.
16020 switch (classifyEHPersonality(Fn->getPersonalityFn())) {
16021 case EHPersonality::MSVC_X86SEH: return 24;
16022 case EHPersonality::MSVC_CXX: return 16;
16025 report_fatal_error("can only recover FP for MSVC EH personality functions");
16028 /// When the 32-bit MSVC runtime transfers control to us, either to an outlined
16029 /// function or when returning to a parent frame after catching an exception, we
16030 /// recover the parent frame pointer by doing arithmetic on the incoming EBP.
16031 /// Here's the math:
16032 /// RegNodeBase = EntryEBP - RegNodeSize
16033 /// ParentFP = RegNodeBase - RegNodeFrameOffset
16034 /// Subtracting RegNodeSize takes us to the offset of the registration node, and
16035 /// subtracting the offset (negative on x86) takes us back to the parent FP.
16036 static SDValue recoverFramePointer(SelectionDAG &DAG, const Function *Fn,
16037 SDValue EntryEBP) {
16038 MachineFunction &MF = DAG.getMachineFunction();
16041 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
16042 MVT PtrVT = TLI.getPointerTy(DAG.getDataLayout());
16044 // It's possible that the parent function no longer has a personality function
16045 // if the exceptional code was optimized away, in which case we just return
16046 // the incoming EBP.
16047 if (!Fn->hasPersonalityFn())
16050 int RegNodeSize = getSEHRegistrationNodeSize(Fn);
16052 // Get an MCSymbol that will ultimately resolve to the frame offset of the EH
16054 MCSymbol *OffsetSym =
16055 MF.getMMI().getContext().getOrCreateParentFrameOffsetSymbol(
16056 GlobalValue::getRealLinkageName(Fn->getName()));
16057 SDValue OffsetSymVal = DAG.getMCSymbol(OffsetSym, PtrVT);
16058 SDValue RegNodeFrameOffset =
16059 DAG.getNode(ISD::LOCAL_RECOVER, dl, PtrVT, OffsetSymVal);
16061 // RegNodeBase = EntryEBP - RegNodeSize
16062 // ParentFP = RegNodeBase - RegNodeFrameOffset
16063 SDValue RegNodeBase = DAG.getNode(ISD::SUB, dl, PtrVT, EntryEBP,
16064 DAG.getConstant(RegNodeSize, dl, PtrVT));
16065 return DAG.getNode(ISD::SUB, dl, PtrVT, RegNodeBase, RegNodeFrameOffset);
16068 static SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
16069 SelectionDAG &DAG) {
16071 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
16072 MVT VT = Op.getSimpleValueType();
16073 const IntrinsicData* IntrData = getIntrinsicWithoutChain(IntNo);
16075 switch(IntrData->Type) {
16076 case INTR_TYPE_1OP:
16077 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1));
16078 case INTR_TYPE_2OP:
16079 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
16081 case INTR_TYPE_2OP_IMM8:
16082 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
16083 DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op.getOperand(2)));
16084 case INTR_TYPE_3OP:
16085 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
16086 Op.getOperand(2), Op.getOperand(3));
16087 case INTR_TYPE_4OP:
16088 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
16089 Op.getOperand(2), Op.getOperand(3), Op.getOperand(4));
16090 case INTR_TYPE_1OP_MASK_RM: {
16091 SDValue Src = Op.getOperand(1);
16092 SDValue PassThru = Op.getOperand(2);
16093 SDValue Mask = Op.getOperand(3);
16094 SDValue RoundingMode;
16095 // We allways add rounding mode to the Node.
16096 // If the rounding mode is not specified, we add the
16097 // "current direction" mode.
16098 if (Op.getNumOperands() == 4)
16100 DAG.getConstant(X86::STATIC_ROUNDING::CUR_DIRECTION, dl, MVT::i32);
16102 RoundingMode = Op.getOperand(4);
16103 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1;
16104 if (IntrWithRoundingModeOpcode != 0)
16105 if (cast<ConstantSDNode>(RoundingMode)->getZExtValue() !=
16106 X86::STATIC_ROUNDING::CUR_DIRECTION)
16107 return getVectorMaskingNode(DAG.getNode(IntrWithRoundingModeOpcode,
16108 dl, Op.getValueType(), Src, RoundingMode),
16109 Mask, PassThru, Subtarget, DAG);
16110 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src,
16112 Mask, PassThru, Subtarget, DAG);
16114 case INTR_TYPE_1OP_MASK: {
16115 SDValue Src = Op.getOperand(1);
16116 SDValue PassThru = Op.getOperand(2);
16117 SDValue Mask = Op.getOperand(3);
16118 // We add rounding mode to the Node when
16119 // - RM Opcode is specified and
16120 // - RM is not "current direction".
16121 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1;
16122 if (IntrWithRoundingModeOpcode != 0) {
16123 SDValue Rnd = Op.getOperand(4);
16124 unsigned Round = cast<ConstantSDNode>(Rnd)->getZExtValue();
16125 if (Round != X86::STATIC_ROUNDING::CUR_DIRECTION) {
16126 return getVectorMaskingNode(DAG.getNode(IntrWithRoundingModeOpcode,
16127 dl, Op.getValueType(),
16129 Mask, PassThru, Subtarget, DAG);
16132 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src),
16133 Mask, PassThru, Subtarget, DAG);
16135 case INTR_TYPE_SCALAR_MASK: {
16136 SDValue Src1 = Op.getOperand(1);
16137 SDValue Src2 = Op.getOperand(2);
16138 SDValue passThru = Op.getOperand(3);
16139 SDValue Mask = Op.getOperand(4);
16140 return getScalarMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src1, Src2),
16141 Mask, passThru, Subtarget, DAG);
16143 case INTR_TYPE_SCALAR_MASK_RM: {
16144 SDValue Src1 = Op.getOperand(1);
16145 SDValue Src2 = Op.getOperand(2);
16146 SDValue Src0 = Op.getOperand(3);
16147 SDValue Mask = Op.getOperand(4);
16148 // There are 2 kinds of intrinsics in this group:
16149 // (1) With suppress-all-exceptions (sae) or rounding mode- 6 operands
16150 // (2) With rounding mode and sae - 7 operands.
16151 if (Op.getNumOperands() == 6) {
16152 SDValue Sae = Op.getOperand(5);
16153 unsigned Opc = IntrData->Opc1 ? IntrData->Opc1 : IntrData->Opc0;
16154 return getScalarMaskingNode(DAG.getNode(Opc, dl, VT, Src1, Src2,
16156 Mask, Src0, Subtarget, DAG);
16158 assert(Op.getNumOperands() == 7 && "Unexpected intrinsic form");
16159 SDValue RoundingMode = Op.getOperand(5);
16160 SDValue Sae = Op.getOperand(6);
16161 return getScalarMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src1, Src2,
16162 RoundingMode, Sae),
16163 Mask, Src0, Subtarget, DAG);
16165 case INTR_TYPE_2OP_MASK:
16166 case INTR_TYPE_2OP_IMM8_MASK: {
16167 SDValue Src1 = Op.getOperand(1);
16168 SDValue Src2 = Op.getOperand(2);
16169 SDValue PassThru = Op.getOperand(3);
16170 SDValue Mask = Op.getOperand(4);
16172 if (IntrData->Type == INTR_TYPE_2OP_IMM8_MASK)
16173 Src2 = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Src2);
16175 // We specify 2 possible opcodes for intrinsics with rounding modes.
16176 // First, we check if the intrinsic may have non-default rounding mode,
16177 // (IntrData->Opc1 != 0), then we check the rounding mode operand.
16178 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1;
16179 if (IntrWithRoundingModeOpcode != 0) {
16180 SDValue Rnd = Op.getOperand(5);
16181 unsigned Round = cast<ConstantSDNode>(Rnd)->getZExtValue();
16182 if (Round != X86::STATIC_ROUNDING::CUR_DIRECTION) {
16183 return getVectorMaskingNode(DAG.getNode(IntrWithRoundingModeOpcode,
16184 dl, Op.getValueType(),
16186 Mask, PassThru, Subtarget, DAG);
16189 // TODO: Intrinsics should have fast-math-flags to propagate.
16190 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT,Src1,Src2),
16191 Mask, PassThru, Subtarget, DAG);
16193 case INTR_TYPE_2OP_MASK_RM: {
16194 SDValue Src1 = Op.getOperand(1);
16195 SDValue Src2 = Op.getOperand(2);
16196 SDValue PassThru = Op.getOperand(3);
16197 SDValue Mask = Op.getOperand(4);
16198 // We specify 2 possible modes for intrinsics, with/without rounding
16200 // First, we check if the intrinsic have rounding mode (6 operands),
16201 // if not, we set rounding mode to "current".
16203 if (Op.getNumOperands() == 6)
16204 Rnd = Op.getOperand(5);
16206 Rnd = DAG.getConstant(X86::STATIC_ROUNDING::CUR_DIRECTION, dl, MVT::i32);
16207 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT,
16209 Mask, PassThru, Subtarget, DAG);
16211 case INTR_TYPE_3OP_SCALAR_MASK_RM: {
16212 SDValue Src1 = Op.getOperand(1);
16213 SDValue Src2 = Op.getOperand(2);
16214 SDValue Src3 = Op.getOperand(3);
16215 SDValue PassThru = Op.getOperand(4);
16216 SDValue Mask = Op.getOperand(5);
16217 SDValue Sae = Op.getOperand(6);
16219 return getScalarMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src1,
16221 Mask, PassThru, Subtarget, DAG);
16223 case INTR_TYPE_3OP_MASK_RM: {
16224 SDValue Src1 = Op.getOperand(1);
16225 SDValue Src2 = Op.getOperand(2);
16226 SDValue Imm = Op.getOperand(3);
16227 SDValue PassThru = Op.getOperand(4);
16228 SDValue Mask = Op.getOperand(5);
16229 // We specify 2 possible modes for intrinsics, with/without rounding
16231 // First, we check if the intrinsic have rounding mode (7 operands),
16232 // if not, we set rounding mode to "current".
16234 if (Op.getNumOperands() == 7)
16235 Rnd = Op.getOperand(6);
16237 Rnd = DAG.getConstant(X86::STATIC_ROUNDING::CUR_DIRECTION, dl, MVT::i32);
16238 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT,
16239 Src1, Src2, Imm, Rnd),
16240 Mask, PassThru, Subtarget, DAG);
16242 case INTR_TYPE_3OP_IMM8_MASK:
16243 case INTR_TYPE_3OP_MASK:
16244 case INSERT_SUBVEC: {
16245 SDValue Src1 = Op.getOperand(1);
16246 SDValue Src2 = Op.getOperand(2);
16247 SDValue Src3 = Op.getOperand(3);
16248 SDValue PassThru = Op.getOperand(4);
16249 SDValue Mask = Op.getOperand(5);
16251 if (IntrData->Type == INTR_TYPE_3OP_IMM8_MASK)
16252 Src3 = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Src3);
16253 else if (IntrData->Type == INSERT_SUBVEC) {
16254 // imm should be adapted to ISD::INSERT_SUBVECTOR behavior
16255 assert(isa<ConstantSDNode>(Src3) && "Expected a ConstantSDNode here!");
16256 unsigned Imm = cast<ConstantSDNode>(Src3)->getZExtValue();
16257 Imm *= Src2.getSimpleValueType().getVectorNumElements();
16258 Src3 = DAG.getTargetConstant(Imm, dl, MVT::i32);
16261 // We specify 2 possible opcodes for intrinsics with rounding modes.
16262 // First, we check if the intrinsic may have non-default rounding mode,
16263 // (IntrData->Opc1 != 0), then we check the rounding mode operand.
16264 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1;
16265 if (IntrWithRoundingModeOpcode != 0) {
16266 SDValue Rnd = Op.getOperand(6);
16267 unsigned Round = cast<ConstantSDNode>(Rnd)->getZExtValue();
16268 if (Round != X86::STATIC_ROUNDING::CUR_DIRECTION) {
16269 return getVectorMaskingNode(DAG.getNode(IntrWithRoundingModeOpcode,
16270 dl, Op.getValueType(),
16271 Src1, Src2, Src3, Rnd),
16272 Mask, PassThru, Subtarget, DAG);
16275 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT,
16277 Mask, PassThru, Subtarget, DAG);
16279 case VPERM_3OP_MASKZ:
16280 case VPERM_3OP_MASK:
16283 case FMA_OP_MASK: {
16284 SDValue Src1 = Op.getOperand(1);
16285 SDValue Src2 = Op.getOperand(2);
16286 SDValue Src3 = Op.getOperand(3);
16287 SDValue Mask = Op.getOperand(4);
16288 MVT VT = Op.getSimpleValueType();
16289 SDValue PassThru = SDValue();
16291 // set PassThru element
16292 if (IntrData->Type == VPERM_3OP_MASKZ || IntrData->Type == FMA_OP_MASKZ)
16293 PassThru = getZeroVector(VT, Subtarget, DAG, dl);
16294 else if (IntrData->Type == FMA_OP_MASK3)
16299 // We specify 2 possible opcodes for intrinsics with rounding modes.
16300 // First, we check if the intrinsic may have non-default rounding mode,
16301 // (IntrData->Opc1 != 0), then we check the rounding mode operand.
16302 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1;
16303 if (IntrWithRoundingModeOpcode != 0) {
16304 SDValue Rnd = Op.getOperand(5);
16305 if (cast<ConstantSDNode>(Rnd)->getZExtValue() !=
16306 X86::STATIC_ROUNDING::CUR_DIRECTION)
16307 return getVectorMaskingNode(DAG.getNode(IntrWithRoundingModeOpcode,
16308 dl, Op.getValueType(),
16309 Src1, Src2, Src3, Rnd),
16310 Mask, PassThru, Subtarget, DAG);
16312 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0,
16313 dl, Op.getValueType(),
16315 Mask, PassThru, Subtarget, DAG);
16317 case TERLOG_OP_MASK:
16318 case TERLOG_OP_MASKZ: {
16319 SDValue Src1 = Op.getOperand(1);
16320 SDValue Src2 = Op.getOperand(2);
16321 SDValue Src3 = Op.getOperand(3);
16322 SDValue Src4 = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op.getOperand(4));
16323 SDValue Mask = Op.getOperand(5);
16324 MVT VT = Op.getSimpleValueType();
16325 SDValue PassThru = Src1;
16326 // Set PassThru element.
16327 if (IntrData->Type == TERLOG_OP_MASKZ)
16328 PassThru = getZeroVector(VT, Subtarget, DAG, dl);
16330 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT,
16331 Src1, Src2, Src3, Src4),
16332 Mask, PassThru, Subtarget, DAG);
16335 // FPclass intrinsics with mask
16336 SDValue Src1 = Op.getOperand(1);
16337 MVT VT = Src1.getSimpleValueType();
16338 MVT MaskVT = MVT::getVectorVT(MVT::i1, VT.getVectorNumElements());
16339 SDValue Imm = Op.getOperand(2);
16340 SDValue Mask = Op.getOperand(3);
16341 MVT BitcastVT = MVT::getVectorVT(MVT::i1,
16342 Mask.getSimpleValueType().getSizeInBits());
16343 SDValue FPclass = DAG.getNode(IntrData->Opc0, dl, MaskVT, Src1, Imm);
16344 SDValue FPclassMask = getVectorMaskingNode(FPclass, Mask,
16345 DAG.getTargetConstant(0, dl, MaskVT),
16347 SDValue Res = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, BitcastVT,
16348 DAG.getUNDEF(BitcastVT), FPclassMask,
16349 DAG.getIntPtrConstant(0, dl));
16350 return DAG.getBitcast(Op.getValueType(), Res);
16353 SDValue Src1 = Op.getOperand(1);
16354 SDValue Imm = Op.getOperand(2);
16355 SDValue Mask = Op.getOperand(3);
16356 SDValue FPclass = DAG.getNode(IntrData->Opc0, dl, MVT::i1, Src1, Imm);
16357 SDValue FPclassMask = getScalarMaskingNode(FPclass, Mask,
16358 DAG.getTargetConstant(0, dl, MVT::i1), Subtarget, DAG);
16359 return DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i8, FPclassMask);
16362 case CMP_MASK_CC: {
16363 // Comparison intrinsics with masks.
16364 // Example of transformation:
16365 // (i8 (int_x86_avx512_mask_pcmpeq_q_128
16366 // (v2i64 %a), (v2i64 %b), (i8 %mask))) ->
16368 // (v8i1 (insert_subvector undef,
16369 // (v2i1 (and (PCMPEQM %a, %b),
16370 // (extract_subvector
16371 // (v8i1 (bitcast %mask)), 0))), 0))))
16372 MVT VT = Op.getOperand(1).getSimpleValueType();
16373 MVT MaskVT = MVT::getVectorVT(MVT::i1, VT.getVectorNumElements());
16374 SDValue Mask = Op.getOperand((IntrData->Type == CMP_MASK_CC) ? 4 : 3);
16375 MVT BitcastVT = MVT::getVectorVT(MVT::i1,
16376 Mask.getSimpleValueType().getSizeInBits());
16378 if (IntrData->Type == CMP_MASK_CC) {
16379 SDValue CC = Op.getOperand(3);
16380 CC = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, CC);
16381 // We specify 2 possible opcodes for intrinsics with rounding modes.
16382 // First, we check if the intrinsic may have non-default rounding mode,
16383 // (IntrData->Opc1 != 0), then we check the rounding mode operand.
16384 if (IntrData->Opc1 != 0) {
16385 SDValue Rnd = Op.getOperand(5);
16386 if (cast<ConstantSDNode>(Rnd)->getZExtValue() !=
16387 X86::STATIC_ROUNDING::CUR_DIRECTION)
16388 Cmp = DAG.getNode(IntrData->Opc1, dl, MaskVT, Op.getOperand(1),
16389 Op.getOperand(2), CC, Rnd);
16391 //default rounding mode
16393 Cmp = DAG.getNode(IntrData->Opc0, dl, MaskVT, Op.getOperand(1),
16394 Op.getOperand(2), CC);
16397 assert(IntrData->Type == CMP_MASK && "Unexpected intrinsic type!");
16398 Cmp = DAG.getNode(IntrData->Opc0, dl, MaskVT, Op.getOperand(1),
16401 SDValue CmpMask = getVectorMaskingNode(Cmp, Mask,
16402 DAG.getTargetConstant(0, dl,
16405 SDValue Res = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, BitcastVT,
16406 DAG.getUNDEF(BitcastVT), CmpMask,
16407 DAG.getIntPtrConstant(0, dl));
16408 return DAG.getBitcast(Op.getValueType(), Res);
16410 case CMP_MASK_SCALAR_CC: {
16411 SDValue Src1 = Op.getOperand(1);
16412 SDValue Src2 = Op.getOperand(2);
16413 SDValue CC = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op.getOperand(3));
16414 SDValue Mask = Op.getOperand(4);
16417 if (IntrData->Opc1 != 0) {
16418 SDValue Rnd = Op.getOperand(5);
16419 if (cast<ConstantSDNode>(Rnd)->getZExtValue() !=
16420 X86::STATIC_ROUNDING::CUR_DIRECTION)
16421 Cmp = DAG.getNode(IntrData->Opc1, dl, MVT::i1, Src1, Src2, CC, Rnd);
16423 //default rounding mode
16425 Cmp = DAG.getNode(IntrData->Opc0, dl, MVT::i1, Src1, Src2, CC);
16427 SDValue CmpMask = getScalarMaskingNode(Cmp, Mask,
16428 DAG.getTargetConstant(0, dl,
16432 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::i8,
16433 DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i8, CmpMask),
16434 DAG.getValueType(MVT::i1));
16436 case COMI: { // Comparison intrinsics
16437 ISD::CondCode CC = (ISD::CondCode)IntrData->Opc1;
16438 SDValue LHS = Op.getOperand(1);
16439 SDValue RHS = Op.getOperand(2);
16440 unsigned X86CC = TranslateX86CC(CC, dl, true, LHS, RHS, DAG);
16441 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!");
16442 SDValue Cond = DAG.getNode(IntrData->Opc0, dl, MVT::i32, LHS, RHS);
16443 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
16444 DAG.getConstant(X86CC, dl, MVT::i8), Cond);
16445 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
16448 return getTargetVShiftNode(IntrData->Opc0, dl, Op.getSimpleValueType(),
16449 Op.getOperand(1), Op.getOperand(2), DAG);
16451 return getVectorMaskingNode(getTargetVShiftNode(IntrData->Opc0, dl,
16452 Op.getSimpleValueType(),
16454 Op.getOperand(2), DAG),
16455 Op.getOperand(4), Op.getOperand(3), Subtarget,
16457 case COMPRESS_EXPAND_IN_REG: {
16458 SDValue Mask = Op.getOperand(3);
16459 SDValue DataToCompress = Op.getOperand(1);
16460 SDValue PassThru = Op.getOperand(2);
16461 if (isAllOnes(Mask)) // return data as is
16462 return Op.getOperand(1);
16464 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT,
16466 Mask, PassThru, Subtarget, DAG);
16469 SDValue Mask = Op.getOperand(3);
16470 MVT VT = Op.getSimpleValueType();
16471 MVT MaskVT = MVT::getVectorVT(MVT::i1, VT.getVectorNumElements());
16472 MVT BitcastVT = MVT::getVectorVT(MVT::i1,
16473 Mask.getSimpleValueType().getSizeInBits());
16475 SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
16476 DAG.getBitcast(BitcastVT, Mask),
16477 DAG.getIntPtrConstant(0, dl));
16478 return DAG.getNode(IntrData->Opc0, dl, VT, VMask, Op.getOperand(1),
16487 default: return SDValue(); // Don't custom lower most intrinsics.
16489 case Intrinsic::x86_avx2_permd:
16490 case Intrinsic::x86_avx2_permps:
16491 // Operands intentionally swapped. Mask is last operand to intrinsic,
16492 // but second operand for node/instruction.
16493 return DAG.getNode(X86ISD::VPERMV, dl, Op.getValueType(),
16494 Op.getOperand(2), Op.getOperand(1));
16496 // ptest and testp intrinsics. The intrinsic these come from are designed to
16497 // return an integer value, not just an instruction so lower it to the ptest
16498 // or testp pattern and a setcc for the result.
16499 case Intrinsic::x86_sse41_ptestz:
16500 case Intrinsic::x86_sse41_ptestc:
16501 case Intrinsic::x86_sse41_ptestnzc:
16502 case Intrinsic::x86_avx_ptestz_256:
16503 case Intrinsic::x86_avx_ptestc_256:
16504 case Intrinsic::x86_avx_ptestnzc_256:
16505 case Intrinsic::x86_avx_vtestz_ps:
16506 case Intrinsic::x86_avx_vtestc_ps:
16507 case Intrinsic::x86_avx_vtestnzc_ps:
16508 case Intrinsic::x86_avx_vtestz_pd:
16509 case Intrinsic::x86_avx_vtestc_pd:
16510 case Intrinsic::x86_avx_vtestnzc_pd:
16511 case Intrinsic::x86_avx_vtestz_ps_256:
16512 case Intrinsic::x86_avx_vtestc_ps_256:
16513 case Intrinsic::x86_avx_vtestnzc_ps_256:
16514 case Intrinsic::x86_avx_vtestz_pd_256:
16515 case Intrinsic::x86_avx_vtestc_pd_256:
16516 case Intrinsic::x86_avx_vtestnzc_pd_256: {
16517 bool IsTestPacked = false;
16520 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
16521 case Intrinsic::x86_avx_vtestz_ps:
16522 case Intrinsic::x86_avx_vtestz_pd:
16523 case Intrinsic::x86_avx_vtestz_ps_256:
16524 case Intrinsic::x86_avx_vtestz_pd_256:
16525 IsTestPacked = true; // Fallthrough
16526 case Intrinsic::x86_sse41_ptestz:
16527 case Intrinsic::x86_avx_ptestz_256:
16529 X86CC = X86::COND_E;
16531 case Intrinsic::x86_avx_vtestc_ps:
16532 case Intrinsic::x86_avx_vtestc_pd:
16533 case Intrinsic::x86_avx_vtestc_ps_256:
16534 case Intrinsic::x86_avx_vtestc_pd_256:
16535 IsTestPacked = true; // Fallthrough
16536 case Intrinsic::x86_sse41_ptestc:
16537 case Intrinsic::x86_avx_ptestc_256:
16539 X86CC = X86::COND_B;
16541 case Intrinsic::x86_avx_vtestnzc_ps:
16542 case Intrinsic::x86_avx_vtestnzc_pd:
16543 case Intrinsic::x86_avx_vtestnzc_ps_256:
16544 case Intrinsic::x86_avx_vtestnzc_pd_256:
16545 IsTestPacked = true; // Fallthrough
16546 case Intrinsic::x86_sse41_ptestnzc:
16547 case Intrinsic::x86_avx_ptestnzc_256:
16549 X86CC = X86::COND_A;
16553 SDValue LHS = Op.getOperand(1);
16554 SDValue RHS = Op.getOperand(2);
16555 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST;
16556 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS);
16557 SDValue CC = DAG.getConstant(X86CC, dl, MVT::i8);
16558 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
16559 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
16561 case Intrinsic::x86_avx512_kortestz_w:
16562 case Intrinsic::x86_avx512_kortestc_w: {
16563 unsigned X86CC = (IntNo == Intrinsic::x86_avx512_kortestz_w)? X86::COND_E: X86::COND_B;
16564 SDValue LHS = DAG.getBitcast(MVT::v16i1, Op.getOperand(1));
16565 SDValue RHS = DAG.getBitcast(MVT::v16i1, Op.getOperand(2));
16566 SDValue CC = DAG.getConstant(X86CC, dl, MVT::i8);
16567 SDValue Test = DAG.getNode(X86ISD::KORTEST, dl, MVT::i32, LHS, RHS);
16568 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i1, CC, Test);
16569 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
16572 case Intrinsic::x86_sse42_pcmpistria128:
16573 case Intrinsic::x86_sse42_pcmpestria128:
16574 case Intrinsic::x86_sse42_pcmpistric128:
16575 case Intrinsic::x86_sse42_pcmpestric128:
16576 case Intrinsic::x86_sse42_pcmpistrio128:
16577 case Intrinsic::x86_sse42_pcmpestrio128:
16578 case Intrinsic::x86_sse42_pcmpistris128:
16579 case Intrinsic::x86_sse42_pcmpestris128:
16580 case Intrinsic::x86_sse42_pcmpistriz128:
16581 case Intrinsic::x86_sse42_pcmpestriz128: {
16585 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
16586 case Intrinsic::x86_sse42_pcmpistria128:
16587 Opcode = X86ISD::PCMPISTRI;
16588 X86CC = X86::COND_A;
16590 case Intrinsic::x86_sse42_pcmpestria128:
16591 Opcode = X86ISD::PCMPESTRI;
16592 X86CC = X86::COND_A;
16594 case Intrinsic::x86_sse42_pcmpistric128:
16595 Opcode = X86ISD::PCMPISTRI;
16596 X86CC = X86::COND_B;
16598 case Intrinsic::x86_sse42_pcmpestric128:
16599 Opcode = X86ISD::PCMPESTRI;
16600 X86CC = X86::COND_B;
16602 case Intrinsic::x86_sse42_pcmpistrio128:
16603 Opcode = X86ISD::PCMPISTRI;
16604 X86CC = X86::COND_O;
16606 case Intrinsic::x86_sse42_pcmpestrio128:
16607 Opcode = X86ISD::PCMPESTRI;
16608 X86CC = X86::COND_O;
16610 case Intrinsic::x86_sse42_pcmpistris128:
16611 Opcode = X86ISD::PCMPISTRI;
16612 X86CC = X86::COND_S;
16614 case Intrinsic::x86_sse42_pcmpestris128:
16615 Opcode = X86ISD::PCMPESTRI;
16616 X86CC = X86::COND_S;
16618 case Intrinsic::x86_sse42_pcmpistriz128:
16619 Opcode = X86ISD::PCMPISTRI;
16620 X86CC = X86::COND_E;
16622 case Intrinsic::x86_sse42_pcmpestriz128:
16623 Opcode = X86ISD::PCMPESTRI;
16624 X86CC = X86::COND_E;
16627 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
16628 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
16629 SDValue PCMP = DAG.getNode(Opcode, dl, VTs, NewOps);
16630 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
16631 DAG.getConstant(X86CC, dl, MVT::i8),
16632 SDValue(PCMP.getNode(), 1));
16633 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
16636 case Intrinsic::x86_sse42_pcmpistri128:
16637 case Intrinsic::x86_sse42_pcmpestri128: {
16639 if (IntNo == Intrinsic::x86_sse42_pcmpistri128)
16640 Opcode = X86ISD::PCMPISTRI;
16642 Opcode = X86ISD::PCMPESTRI;
16644 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
16645 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
16646 return DAG.getNode(Opcode, dl, VTs, NewOps);
16649 case Intrinsic::x86_seh_lsda: {
16650 // Compute the symbol for the LSDA. We know it'll get emitted later.
16651 MachineFunction &MF = DAG.getMachineFunction();
16652 SDValue Op1 = Op.getOperand(1);
16653 auto *Fn = cast<Function>(cast<GlobalAddressSDNode>(Op1)->getGlobal());
16654 MCSymbol *LSDASym = MF.getMMI().getContext().getOrCreateLSDASymbol(
16655 GlobalValue::getRealLinkageName(Fn->getName()));
16657 // Generate a simple absolute symbol reference. This intrinsic is only
16658 // supported on 32-bit Windows, which isn't PIC.
16659 SDValue Result = DAG.getMCSymbol(LSDASym, VT);
16660 return DAG.getNode(X86ISD::Wrapper, dl, VT, Result);
16663 case Intrinsic::x86_seh_recoverfp: {
16664 SDValue FnOp = Op.getOperand(1);
16665 SDValue IncomingFPOp = Op.getOperand(2);
16666 GlobalAddressSDNode *GSD = dyn_cast<GlobalAddressSDNode>(FnOp);
16667 auto *Fn = dyn_cast_or_null<Function>(GSD ? GSD->getGlobal() : nullptr);
16669 report_fatal_error(
16670 "llvm.x86.seh.recoverfp must take a function as the first argument");
16671 return recoverFramePointer(DAG, Fn, IncomingFPOp);
16674 case Intrinsic::localaddress: {
16675 // Returns one of the stack, base, or frame pointer registers, depending on
16676 // which is used to reference local variables.
16677 MachineFunction &MF = DAG.getMachineFunction();
16678 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
16680 if (RegInfo->hasBasePointer(MF))
16681 Reg = RegInfo->getBaseRegister();
16682 else // This function handles the SP or FP case.
16683 Reg = RegInfo->getPtrSizedFrameRegister(MF);
16684 return DAG.getCopyFromReg(DAG.getEntryNode(), dl, Reg, VT);
16689 static SDValue getGatherNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
16690 SDValue Src, SDValue Mask, SDValue Base,
16691 SDValue Index, SDValue ScaleOp, SDValue Chain,
16692 const X86Subtarget * Subtarget) {
16694 auto *C = cast<ConstantSDNode>(ScaleOp);
16695 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), dl, MVT::i8);
16696 MVT MaskVT = MVT::getVectorVT(MVT::i1,
16697 Index.getSimpleValueType().getVectorNumElements());
16699 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
16701 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), dl, MaskVT);
16703 MVT BitcastVT = MVT::getVectorVT(MVT::i1,
16704 Mask.getSimpleValueType().getSizeInBits());
16706 // In case when MaskVT equals v2i1 or v4i1, low 2 or 4 elements
16707 // are extracted by EXTRACT_SUBVECTOR.
16708 MaskInReg = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
16709 DAG.getBitcast(BitcastVT, Mask),
16710 DAG.getIntPtrConstant(0, dl));
16712 SDVTList VTs = DAG.getVTList(Op.getValueType(), MaskVT, MVT::Other);
16713 SDValue Disp = DAG.getTargetConstant(0, dl, MVT::i32);
16714 SDValue Segment = DAG.getRegister(0, MVT::i32);
16715 if (Src.getOpcode() == ISD::UNDEF)
16716 Src = getZeroVector(Op.getValueType(), Subtarget, DAG, dl);
16717 SDValue Ops[] = {Src, MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
16718 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
16719 SDValue RetOps[] = { SDValue(Res, 0), SDValue(Res, 2) };
16720 return DAG.getMergeValues(RetOps, dl);
16723 static SDValue getScatterNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
16724 SDValue Src, SDValue Mask, SDValue Base,
16725 SDValue Index, SDValue ScaleOp, SDValue Chain) {
16727 auto *C = cast<ConstantSDNode>(ScaleOp);
16728 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), dl, MVT::i8);
16729 SDValue Disp = DAG.getTargetConstant(0, dl, MVT::i32);
16730 SDValue Segment = DAG.getRegister(0, MVT::i32);
16731 MVT MaskVT = MVT::getVectorVT(MVT::i1,
16732 Index.getSimpleValueType().getVectorNumElements());
16734 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
16736 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), dl, MaskVT);
16738 MVT BitcastVT = MVT::getVectorVT(MVT::i1,
16739 Mask.getSimpleValueType().getSizeInBits());
16741 // In case when MaskVT equals v2i1 or v4i1, low 2 or 4 elements
16742 // are extracted by EXTRACT_SUBVECTOR.
16743 MaskInReg = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
16744 DAG.getBitcast(BitcastVT, Mask),
16745 DAG.getIntPtrConstant(0, dl));
16747 SDVTList VTs = DAG.getVTList(MaskVT, MVT::Other);
16748 SDValue Ops[] = {Base, Scale, Index, Disp, Segment, MaskInReg, Src, Chain};
16749 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
16750 return SDValue(Res, 1);
16753 static SDValue getPrefetchNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
16754 SDValue Mask, SDValue Base, SDValue Index,
16755 SDValue ScaleOp, SDValue Chain) {
16757 auto *C = cast<ConstantSDNode>(ScaleOp);
16758 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), dl, MVT::i8);
16759 SDValue Disp = DAG.getTargetConstant(0, dl, MVT::i32);
16760 SDValue Segment = DAG.getRegister(0, MVT::i32);
16762 MVT::getVectorVT(MVT::i1, Index.getSimpleValueType().getVectorNumElements());
16764 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
16766 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), dl, MaskVT);
16768 MaskInReg = DAG.getBitcast(MaskVT, Mask);
16769 //SDVTList VTs = DAG.getVTList(MVT::Other);
16770 SDValue Ops[] = {MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
16771 SDNode *Res = DAG.getMachineNode(Opc, dl, MVT::Other, Ops);
16772 return SDValue(Res, 0);
16775 // getReadPerformanceCounter - Handles the lowering of builtin intrinsics that
16776 // read performance monitor counters (x86_rdpmc).
16777 static void getReadPerformanceCounter(SDNode *N, SDLoc DL,
16778 SelectionDAG &DAG, const X86Subtarget *Subtarget,
16779 SmallVectorImpl<SDValue> &Results) {
16780 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
16781 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
16784 // The ECX register is used to select the index of the performance counter
16786 SDValue Chain = DAG.getCopyToReg(N->getOperand(0), DL, X86::ECX,
16788 SDValue rd = DAG.getNode(X86ISD::RDPMC_DAG, DL, Tys, Chain);
16790 // Reads the content of a 64-bit performance counter and returns it in the
16791 // registers EDX:EAX.
16792 if (Subtarget->is64Bit()) {
16793 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
16794 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
16797 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
16798 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
16801 Chain = HI.getValue(1);
16803 if (Subtarget->is64Bit()) {
16804 // The EAX register is loaded with the low-order 32 bits. The EDX register
16805 // is loaded with the supported high-order bits of the counter.
16806 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
16807 DAG.getConstant(32, DL, MVT::i8));
16808 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
16809 Results.push_back(Chain);
16813 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
16814 SDValue Ops[] = { LO, HI };
16815 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
16816 Results.push_back(Pair);
16817 Results.push_back(Chain);
16820 // getReadTimeStampCounter - Handles the lowering of builtin intrinsics that
16821 // read the time stamp counter (x86_rdtsc and x86_rdtscp). This function is
16822 // also used to custom lower READCYCLECOUNTER nodes.
16823 static void getReadTimeStampCounter(SDNode *N, SDLoc DL, unsigned Opcode,
16824 SelectionDAG &DAG, const X86Subtarget *Subtarget,
16825 SmallVectorImpl<SDValue> &Results) {
16826 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
16827 SDValue rd = DAG.getNode(Opcode, DL, Tys, N->getOperand(0));
16830 // The processor's time-stamp counter (a 64-bit MSR) is stored into the
16831 // EDX:EAX registers. EDX is loaded with the high-order 32 bits of the MSR
16832 // and the EAX register is loaded with the low-order 32 bits.
16833 if (Subtarget->is64Bit()) {
16834 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
16835 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
16838 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
16839 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
16842 SDValue Chain = HI.getValue(1);
16844 if (Opcode == X86ISD::RDTSCP_DAG) {
16845 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
16847 // Instruction RDTSCP loads the IA32:TSC_AUX_MSR (address C000_0103H) into
16848 // the ECX register. Add 'ecx' explicitly to the chain.
16849 SDValue ecx = DAG.getCopyFromReg(Chain, DL, X86::ECX, MVT::i32,
16851 // Explicitly store the content of ECX at the location passed in input
16852 // to the 'rdtscp' intrinsic.
16853 Chain = DAG.getStore(ecx.getValue(1), DL, ecx, N->getOperand(2),
16854 MachinePointerInfo(), false, false, 0);
16857 if (Subtarget->is64Bit()) {
16858 // The EDX register is loaded with the high-order 32 bits of the MSR, and
16859 // the EAX register is loaded with the low-order 32 bits.
16860 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
16861 DAG.getConstant(32, DL, MVT::i8));
16862 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
16863 Results.push_back(Chain);
16867 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
16868 SDValue Ops[] = { LO, HI };
16869 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
16870 Results.push_back(Pair);
16871 Results.push_back(Chain);
16874 static SDValue LowerREADCYCLECOUNTER(SDValue Op, const X86Subtarget *Subtarget,
16875 SelectionDAG &DAG) {
16876 SmallVector<SDValue, 2> Results;
16878 getReadTimeStampCounter(Op.getNode(), DL, X86ISD::RDTSC_DAG, DAG, Subtarget,
16880 return DAG.getMergeValues(Results, DL);
16883 static SDValue LowerSEHRESTOREFRAME(SDValue Op, const X86Subtarget *Subtarget,
16884 SelectionDAG &DAG) {
16885 MachineFunction &MF = DAG.getMachineFunction();
16886 const Function *Fn = MF.getFunction();
16888 SDValue Chain = Op.getOperand(0);
16890 assert(Subtarget->getFrameLowering()->hasFP(MF) &&
16891 "using llvm.x86.seh.restoreframe requires a frame pointer");
16893 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
16894 MVT VT = TLI.getPointerTy(DAG.getDataLayout());
16896 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
16897 unsigned FrameReg =
16898 RegInfo->getPtrSizedFrameRegister(DAG.getMachineFunction());
16899 unsigned SPReg = RegInfo->getStackRegister();
16900 unsigned SlotSize = RegInfo->getSlotSize();
16902 // Get incoming EBP.
16903 SDValue IncomingEBP =
16904 DAG.getCopyFromReg(Chain, dl, FrameReg, VT);
16906 // SP is saved in the first field of every registration node, so load
16907 // [EBP-RegNodeSize] into SP.
16908 int RegNodeSize = getSEHRegistrationNodeSize(Fn);
16909 SDValue SPAddr = DAG.getNode(ISD::ADD, dl, VT, IncomingEBP,
16910 DAG.getConstant(-RegNodeSize, dl, VT));
16912 DAG.getLoad(VT, dl, Chain, SPAddr, MachinePointerInfo(), false, false,
16913 false, VT.getScalarSizeInBits() / 8);
16914 Chain = DAG.getCopyToReg(Chain, dl, SPReg, NewSP);
16916 if (!RegInfo->needsStackRealignment(MF)) {
16917 // Adjust EBP to point back to the original frame position.
16918 SDValue NewFP = recoverFramePointer(DAG, Fn, IncomingEBP);
16919 Chain = DAG.getCopyToReg(Chain, dl, FrameReg, NewFP);
16921 assert(RegInfo->hasBasePointer(MF) &&
16922 "functions with Win32 EH must use frame or base pointer register");
16924 // Reload the base pointer (ESI) with the adjusted incoming EBP.
16925 SDValue NewBP = recoverFramePointer(DAG, Fn, IncomingEBP);
16926 Chain = DAG.getCopyToReg(Chain, dl, RegInfo->getBaseRegister(), NewBP);
16928 // Reload the spilled EBP value, now that the stack and base pointers are
16930 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
16931 X86FI->setHasSEHFramePtrSave(true);
16932 int FI = MF.getFrameInfo()->CreateSpillStackObject(SlotSize, SlotSize);
16933 X86FI->setSEHFramePtrSaveIndex(FI);
16934 SDValue NewFP = DAG.getLoad(VT, dl, Chain, DAG.getFrameIndex(FI, VT),
16935 MachinePointerInfo(), false, false, false,
16936 VT.getScalarSizeInBits() / 8);
16937 Chain = DAG.getCopyToReg(NewFP, dl, FrameReg, NewFP);
16943 /// \brief Lower intrinsics for TRUNCATE_TO_MEM case
16944 /// return truncate Store/MaskedStore Node
16945 static SDValue LowerINTRINSIC_TRUNCATE_TO_MEM(const SDValue & Op,
16949 SDValue Mask = Op.getOperand(4);
16950 SDValue DataToTruncate = Op.getOperand(3);
16951 SDValue Addr = Op.getOperand(2);
16952 SDValue Chain = Op.getOperand(0);
16954 MVT VT = DataToTruncate.getSimpleValueType();
16955 MVT SVT = MVT::getVectorVT(ElementType, VT.getVectorNumElements());
16957 if (isAllOnes(Mask)) // return just a truncate store
16958 return DAG.getTruncStore(Chain, dl, DataToTruncate, Addr,
16959 MachinePointerInfo(), SVT, false, false,
16960 SVT.getScalarSizeInBits()/8);
16962 MVT MaskVT = MVT::getVectorVT(MVT::i1, VT.getVectorNumElements());
16963 MVT BitcastVT = MVT::getVectorVT(MVT::i1,
16964 Mask.getSimpleValueType().getSizeInBits());
16965 // In case when MaskVT equals v2i1 or v4i1, low 2 or 4 elements
16966 // are extracted by EXTRACT_SUBVECTOR.
16967 SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
16968 DAG.getBitcast(BitcastVT, Mask),
16969 DAG.getIntPtrConstant(0, dl));
16971 MachineMemOperand *MMO = DAG.getMachineFunction().
16972 getMachineMemOperand(MachinePointerInfo(),
16973 MachineMemOperand::MOStore, SVT.getStoreSize(),
16974 SVT.getScalarSizeInBits()/8);
16976 return DAG.getMaskedStore(Chain, dl, DataToTruncate, Addr,
16977 VMask, SVT, MMO, true);
16980 static SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
16981 SelectionDAG &DAG) {
16982 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
16984 const IntrinsicData* IntrData = getIntrinsicWithChain(IntNo);
16986 if (IntNo == llvm::Intrinsic::x86_seh_restoreframe)
16987 return LowerSEHRESTOREFRAME(Op, Subtarget, DAG);
16992 switch(IntrData->Type) {
16993 default: llvm_unreachable("Unknown Intrinsic Type");
16996 // Emit the node with the right value type.
16997 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Glue, MVT::Other);
16998 SDValue Result = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(0));
17000 // If the value returned by RDRAND/RDSEED was valid (CF=1), return 1.
17001 // Otherwise return the value from Rand, which is always 0, casted to i32.
17002 SDValue Ops[] = { DAG.getZExtOrTrunc(Result, dl, Op->getValueType(1)),
17003 DAG.getConstant(1, dl, Op->getValueType(1)),
17004 DAG.getConstant(X86::COND_B, dl, MVT::i32),
17005 SDValue(Result.getNode(), 1) };
17006 SDValue isValid = DAG.getNode(X86ISD::CMOV, dl,
17007 DAG.getVTList(Op->getValueType(1), MVT::Glue),
17010 // Return { result, isValid, chain }.
17011 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(), Result, isValid,
17012 SDValue(Result.getNode(), 2));
17015 //gather(v1, mask, index, base, scale);
17016 SDValue Chain = Op.getOperand(0);
17017 SDValue Src = Op.getOperand(2);
17018 SDValue Base = Op.getOperand(3);
17019 SDValue Index = Op.getOperand(4);
17020 SDValue Mask = Op.getOperand(5);
17021 SDValue Scale = Op.getOperand(6);
17022 return getGatherNode(IntrData->Opc0, Op, DAG, Src, Mask, Base, Index, Scale,
17026 //scatter(base, mask, index, v1, scale);
17027 SDValue Chain = Op.getOperand(0);
17028 SDValue Base = Op.getOperand(2);
17029 SDValue Mask = Op.getOperand(3);
17030 SDValue Index = Op.getOperand(4);
17031 SDValue Src = Op.getOperand(5);
17032 SDValue Scale = Op.getOperand(6);
17033 return getScatterNode(IntrData->Opc0, Op, DAG, Src, Mask, Base, Index,
17037 SDValue Hint = Op.getOperand(6);
17038 unsigned HintVal = cast<ConstantSDNode>(Hint)->getZExtValue();
17039 assert(HintVal < 2 && "Wrong prefetch hint in intrinsic: should be 0 or 1");
17040 unsigned Opcode = (HintVal ? IntrData->Opc1 : IntrData->Opc0);
17041 SDValue Chain = Op.getOperand(0);
17042 SDValue Mask = Op.getOperand(2);
17043 SDValue Index = Op.getOperand(3);
17044 SDValue Base = Op.getOperand(4);
17045 SDValue Scale = Op.getOperand(5);
17046 return getPrefetchNode(Opcode, Op, DAG, Mask, Base, Index, Scale, Chain);
17048 // Read Time Stamp Counter (RDTSC) and Processor ID (RDTSCP).
17050 SmallVector<SDValue, 2> Results;
17051 getReadTimeStampCounter(Op.getNode(), dl, IntrData->Opc0, DAG, Subtarget,
17053 return DAG.getMergeValues(Results, dl);
17055 // Read Performance Monitoring Counters.
17057 SmallVector<SDValue, 2> Results;
17058 getReadPerformanceCounter(Op.getNode(), dl, DAG, Subtarget, Results);
17059 return DAG.getMergeValues(Results, dl);
17061 // XTEST intrinsics.
17063 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
17064 SDValue InTrans = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(0));
17065 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
17066 DAG.getConstant(X86::COND_NE, dl, MVT::i8),
17068 SDValue Ret = DAG.getNode(ISD::ZERO_EXTEND, dl, Op->getValueType(0), SetCC);
17069 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(),
17070 Ret, SDValue(InTrans.getNode(), 1));
17074 SmallVector<SDValue, 2> Results;
17075 SDVTList CFVTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
17076 SDVTList VTs = DAG.getVTList(Op.getOperand(3)->getValueType(0), MVT::Other);
17077 SDValue GenCF = DAG.getNode(X86ISD::ADD, dl, CFVTs, Op.getOperand(2),
17078 DAG.getConstant(-1, dl, MVT::i8));
17079 SDValue Res = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(3),
17080 Op.getOperand(4), GenCF.getValue(1));
17081 SDValue Store = DAG.getStore(Op.getOperand(0), dl, Res.getValue(0),
17082 Op.getOperand(5), MachinePointerInfo(),
17084 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
17085 DAG.getConstant(X86::COND_B, dl, MVT::i8),
17087 Results.push_back(SetCC);
17088 Results.push_back(Store);
17089 return DAG.getMergeValues(Results, dl);
17091 case COMPRESS_TO_MEM: {
17093 SDValue Mask = Op.getOperand(4);
17094 SDValue DataToCompress = Op.getOperand(3);
17095 SDValue Addr = Op.getOperand(2);
17096 SDValue Chain = Op.getOperand(0);
17098 MVT VT = DataToCompress.getSimpleValueType();
17099 if (isAllOnes(Mask)) // return just a store
17100 return DAG.getStore(Chain, dl, DataToCompress, Addr,
17101 MachinePointerInfo(), false, false,
17102 VT.getScalarSizeInBits()/8);
17104 SDValue Compressed =
17105 getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, DataToCompress),
17106 Mask, DAG.getUNDEF(VT), Subtarget, DAG);
17107 return DAG.getStore(Chain, dl, Compressed, Addr,
17108 MachinePointerInfo(), false, false,
17109 VT.getScalarSizeInBits()/8);
17111 case TRUNCATE_TO_MEM_VI8:
17112 return LowerINTRINSIC_TRUNCATE_TO_MEM(Op, DAG, MVT::i8);
17113 case TRUNCATE_TO_MEM_VI16:
17114 return LowerINTRINSIC_TRUNCATE_TO_MEM(Op, DAG, MVT::i16);
17115 case TRUNCATE_TO_MEM_VI32:
17116 return LowerINTRINSIC_TRUNCATE_TO_MEM(Op, DAG, MVT::i32);
17117 case EXPAND_FROM_MEM: {
17119 SDValue Mask = Op.getOperand(4);
17120 SDValue PassThru = Op.getOperand(3);
17121 SDValue Addr = Op.getOperand(2);
17122 SDValue Chain = Op.getOperand(0);
17123 MVT VT = Op.getSimpleValueType();
17125 if (isAllOnes(Mask)) // return just a load
17126 return DAG.getLoad(VT, dl, Chain, Addr, MachinePointerInfo(), false, false,
17127 false, VT.getScalarSizeInBits()/8);
17129 SDValue DataToExpand = DAG.getLoad(VT, dl, Chain, Addr, MachinePointerInfo(),
17130 false, false, false,
17131 VT.getScalarSizeInBits()/8);
17133 SDValue Results[] = {
17134 getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, DataToExpand),
17135 Mask, PassThru, Subtarget, DAG), Chain};
17136 return DAG.getMergeValues(Results, dl);
17141 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op,
17142 SelectionDAG &DAG) const {
17143 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
17144 MFI->setReturnAddressIsTaken(true);
17146 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
17149 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
17151 EVT PtrVT = getPointerTy(DAG.getDataLayout());
17154 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
17155 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
17156 SDValue Offset = DAG.getConstant(RegInfo->getSlotSize(), dl, PtrVT);
17157 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
17158 DAG.getNode(ISD::ADD, dl, PtrVT,
17159 FrameAddr, Offset),
17160 MachinePointerInfo(), false, false, false, 0);
17163 // Just load the return address.
17164 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
17165 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
17166 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
17169 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
17170 MachineFunction &MF = DAG.getMachineFunction();
17171 MachineFrameInfo *MFI = MF.getFrameInfo();
17172 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
17173 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
17174 EVT VT = Op.getValueType();
17176 MFI->setFrameAddressIsTaken(true);
17178 if (MF.getTarget().getMCAsmInfo()->usesWindowsCFI()) {
17179 // Depth > 0 makes no sense on targets which use Windows unwind codes. It
17180 // is not possible to crawl up the stack without looking at the unwind codes
17182 int FrameAddrIndex = FuncInfo->getFAIndex();
17183 if (!FrameAddrIndex) {
17184 // Set up a frame object for the return address.
17185 unsigned SlotSize = RegInfo->getSlotSize();
17186 FrameAddrIndex = MF.getFrameInfo()->CreateFixedObject(
17187 SlotSize, /*Offset=*/0, /*IsImmutable=*/false);
17188 FuncInfo->setFAIndex(FrameAddrIndex);
17190 return DAG.getFrameIndex(FrameAddrIndex, VT);
17193 unsigned FrameReg =
17194 RegInfo->getPtrSizedFrameRegister(DAG.getMachineFunction());
17195 SDLoc dl(Op); // FIXME probably not meaningful
17196 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
17197 assert(((FrameReg == X86::RBP && VT == MVT::i64) ||
17198 (FrameReg == X86::EBP && VT == MVT::i32)) &&
17199 "Invalid Frame Register!");
17200 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
17202 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
17203 MachinePointerInfo(),
17204 false, false, false, 0);
17208 // FIXME? Maybe this could be a TableGen attribute on some registers and
17209 // this table could be generated automatically from RegInfo.
17210 unsigned X86TargetLowering::getRegisterByName(const char* RegName, EVT VT,
17211 SelectionDAG &DAG) const {
17212 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
17213 const MachineFunction &MF = DAG.getMachineFunction();
17215 unsigned Reg = StringSwitch<unsigned>(RegName)
17216 .Case("esp", X86::ESP)
17217 .Case("rsp", X86::RSP)
17218 .Case("ebp", X86::EBP)
17219 .Case("rbp", X86::RBP)
17222 if (Reg == X86::EBP || Reg == X86::RBP) {
17223 if (!TFI.hasFP(MF))
17224 report_fatal_error("register " + StringRef(RegName) +
17225 " is allocatable: function has no frame pointer");
17228 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
17229 unsigned FrameReg =
17230 RegInfo->getPtrSizedFrameRegister(DAG.getMachineFunction());
17231 assert((FrameReg == X86::EBP || FrameReg == X86::RBP) &&
17232 "Invalid Frame Register!");
17240 report_fatal_error("Invalid register name global variable");
17243 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
17244 SelectionDAG &DAG) const {
17245 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
17246 return DAG.getIntPtrConstant(2 * RegInfo->getSlotSize(), SDLoc(Op));
17249 unsigned X86TargetLowering::getExceptionPointerRegister(
17250 const Constant *PersonalityFn) const {
17251 if (classifyEHPersonality(PersonalityFn) == EHPersonality::CoreCLR)
17252 return Subtarget->isTarget64BitLP64() ? X86::RDX : X86::EDX;
17254 return Subtarget->isTarget64BitLP64() ? X86::RAX : X86::EAX;
17257 unsigned X86TargetLowering::getExceptionSelectorRegister(
17258 const Constant *PersonalityFn) const {
17259 // Funclet personalities don't use selectors (the runtime does the selection).
17260 assert(!isFuncletEHPersonality(classifyEHPersonality(PersonalityFn)));
17261 return Subtarget->isTarget64BitLP64() ? X86::RDX : X86::EDX;
17264 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
17265 SDValue Chain = Op.getOperand(0);
17266 SDValue Offset = Op.getOperand(1);
17267 SDValue Handler = Op.getOperand(2);
17270 EVT PtrVT = getPointerTy(DAG.getDataLayout());
17271 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
17272 unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction());
17273 assert(((FrameReg == X86::RBP && PtrVT == MVT::i64) ||
17274 (FrameReg == X86::EBP && PtrVT == MVT::i32)) &&
17275 "Invalid Frame Register!");
17276 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, PtrVT);
17277 unsigned StoreAddrReg = (PtrVT == MVT::i64) ? X86::RCX : X86::ECX;
17279 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, Frame,
17280 DAG.getIntPtrConstant(RegInfo->getSlotSize(),
17282 StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, StoreAddr, Offset);
17283 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(),
17285 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
17287 return DAG.getNode(X86ISD::EH_RETURN, dl, MVT::Other, Chain,
17288 DAG.getRegister(StoreAddrReg, PtrVT));
17291 SDValue X86TargetLowering::lowerEH_SJLJ_SETJMP(SDValue Op,
17292 SelectionDAG &DAG) const {
17294 return DAG.getNode(X86ISD::EH_SJLJ_SETJMP, DL,
17295 DAG.getVTList(MVT::i32, MVT::Other),
17296 Op.getOperand(0), Op.getOperand(1));
17299 SDValue X86TargetLowering::lowerEH_SJLJ_LONGJMP(SDValue Op,
17300 SelectionDAG &DAG) const {
17302 return DAG.getNode(X86ISD::EH_SJLJ_LONGJMP, DL, MVT::Other,
17303 Op.getOperand(0), Op.getOperand(1));
17306 static SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) {
17307 return Op.getOperand(0);
17310 SDValue X86TargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
17311 SelectionDAG &DAG) const {
17312 SDValue Root = Op.getOperand(0);
17313 SDValue Trmp = Op.getOperand(1); // trampoline
17314 SDValue FPtr = Op.getOperand(2); // nested function
17315 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
17318 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
17319 const TargetRegisterInfo *TRI = Subtarget->getRegisterInfo();
17321 if (Subtarget->is64Bit()) {
17322 SDValue OutChains[6];
17324 // Large code-model.
17325 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode.
17326 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode.
17328 const unsigned char N86R10 = TRI->getEncodingValue(X86::R10) & 0x7;
17329 const unsigned char N86R11 = TRI->getEncodingValue(X86::R11) & 0x7;
17331 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
17333 // Load the pointer to the nested function into R11.
17334 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
17335 SDValue Addr = Trmp;
17336 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, dl, MVT::i16),
17337 Addr, MachinePointerInfo(TrmpAddr),
17340 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17341 DAG.getConstant(2, dl, MVT::i64));
17342 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr,
17343 MachinePointerInfo(TrmpAddr, 2),
17346 // Load the 'nest' parameter value into R10.
17347 // R10 is specified in X86CallingConv.td
17348 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
17349 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17350 DAG.getConstant(10, dl, MVT::i64));
17351 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, dl, MVT::i16),
17352 Addr, MachinePointerInfo(TrmpAddr, 10),
17355 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17356 DAG.getConstant(12, dl, MVT::i64));
17357 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr,
17358 MachinePointerInfo(TrmpAddr, 12),
17361 // Jump to the nested function.
17362 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
17363 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17364 DAG.getConstant(20, dl, MVT::i64));
17365 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, dl, MVT::i16),
17366 Addr, MachinePointerInfo(TrmpAddr, 20),
17369 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
17370 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17371 DAG.getConstant(22, dl, MVT::i64));
17372 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, dl, MVT::i8),
17373 Addr, MachinePointerInfo(TrmpAddr, 22),
17376 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
17378 const Function *Func =
17379 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
17380 CallingConv::ID CC = Func->getCallingConv();
17385 llvm_unreachable("Unsupported calling convention");
17386 case CallingConv::C:
17387 case CallingConv::X86_StdCall: {
17388 // Pass 'nest' parameter in ECX.
17389 // Must be kept in sync with X86CallingConv.td
17390 NestReg = X86::ECX;
17392 // Check that ECX wasn't needed by an 'inreg' parameter.
17393 FunctionType *FTy = Func->getFunctionType();
17394 const AttributeSet &Attrs = Func->getAttributes();
17396 if (!Attrs.isEmpty() && !Func->isVarArg()) {
17397 unsigned InRegCount = 0;
17400 for (FunctionType::param_iterator I = FTy->param_begin(),
17401 E = FTy->param_end(); I != E; ++I, ++Idx)
17402 if (Attrs.hasAttribute(Idx, Attribute::InReg)) {
17403 auto &DL = DAG.getDataLayout();
17404 // FIXME: should only count parameters that are lowered to integers.
17405 InRegCount += (DL.getTypeSizeInBits(*I) + 31) / 32;
17408 if (InRegCount > 2) {
17409 report_fatal_error("Nest register in use - reduce number of inreg"
17415 case CallingConv::X86_FastCall:
17416 case CallingConv::X86_ThisCall:
17417 case CallingConv::Fast:
17418 // Pass 'nest' parameter in EAX.
17419 // Must be kept in sync with X86CallingConv.td
17420 NestReg = X86::EAX;
17424 SDValue OutChains[4];
17425 SDValue Addr, Disp;
17427 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17428 DAG.getConstant(10, dl, MVT::i32));
17429 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
17431 // This is storing the opcode for MOV32ri.
17432 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte.
17433 const unsigned char N86Reg = TRI->getEncodingValue(NestReg) & 0x7;
17434 OutChains[0] = DAG.getStore(Root, dl,
17435 DAG.getConstant(MOV32ri|N86Reg, dl, MVT::i8),
17436 Trmp, MachinePointerInfo(TrmpAddr),
17439 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17440 DAG.getConstant(1, dl, MVT::i32));
17441 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr,
17442 MachinePointerInfo(TrmpAddr, 1),
17445 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode.
17446 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17447 DAG.getConstant(5, dl, MVT::i32));
17448 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, dl, MVT::i8),
17449 Addr, MachinePointerInfo(TrmpAddr, 5),
17452 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17453 DAG.getConstant(6, dl, MVT::i32));
17454 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr,
17455 MachinePointerInfo(TrmpAddr, 6),
17458 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
17462 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op,
17463 SelectionDAG &DAG) const {
17465 The rounding mode is in bits 11:10 of FPSR, and has the following
17467 00 Round to nearest
17472 FLT_ROUNDS, on the other hand, expects the following:
17479 To perform the conversion, we do:
17480 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
17483 MachineFunction &MF = DAG.getMachineFunction();
17484 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
17485 unsigned StackAlignment = TFI.getStackAlignment();
17486 MVT VT = Op.getSimpleValueType();
17489 // Save FP Control Word to stack slot
17490 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false);
17491 SDValue StackSlot =
17492 DAG.getFrameIndex(SSFI, getPointerTy(DAG.getDataLayout()));
17494 MachineMemOperand *MMO =
17495 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(MF, SSFI),
17496 MachineMemOperand::MOStore, 2, 2);
17498 SDValue Ops[] = { DAG.getEntryNode(), StackSlot };
17499 SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL,
17500 DAG.getVTList(MVT::Other),
17501 Ops, MVT::i16, MMO);
17503 // Load FP Control Word from stack slot
17504 SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot,
17505 MachinePointerInfo(), false, false, false, 0);
17507 // Transform as necessary
17509 DAG.getNode(ISD::SRL, DL, MVT::i16,
17510 DAG.getNode(ISD::AND, DL, MVT::i16,
17511 CWD, DAG.getConstant(0x800, DL, MVT::i16)),
17512 DAG.getConstant(11, DL, MVT::i8));
17514 DAG.getNode(ISD::SRL, DL, MVT::i16,
17515 DAG.getNode(ISD::AND, DL, MVT::i16,
17516 CWD, DAG.getConstant(0x400, DL, MVT::i16)),
17517 DAG.getConstant(9, DL, MVT::i8));
17520 DAG.getNode(ISD::AND, DL, MVT::i16,
17521 DAG.getNode(ISD::ADD, DL, MVT::i16,
17522 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2),
17523 DAG.getConstant(1, DL, MVT::i16)),
17524 DAG.getConstant(3, DL, MVT::i16));
17526 return DAG.getNode((VT.getSizeInBits() < 16 ?
17527 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal);
17530 /// \brief Lower a vector CTLZ using native supported vector CTLZ instruction.
17532 // 1. i32/i64 128/256-bit vector (native support require VLX) are expended
17533 // to 512-bit vector.
17534 // 2. i8/i16 vector implemented using dword LZCNT vector instruction
17535 // ( sub(trunc(lzcnt(zext32(x)))) ). In case zext32(x) is illegal,
17536 // split the vector, perform operation on it's Lo a Hi part and
17537 // concatenate the results.
17538 static SDValue LowerVectorCTLZ_AVX512(SDValue Op, SelectionDAG &DAG) {
17540 MVT VT = Op.getSimpleValueType();
17541 MVT EltVT = VT.getVectorElementType();
17542 unsigned NumElems = VT.getVectorNumElements();
17544 if (EltVT == MVT::i64 || EltVT == MVT::i32) {
17545 // Extend to 512 bit vector.
17546 assert((VT.is256BitVector() || VT.is128BitVector()) &&
17547 "Unsupported value type for operation");
17549 MVT NewVT = MVT::getVectorVT(EltVT, 512 / VT.getScalarSizeInBits());
17550 SDValue Vec512 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, NewVT,
17551 DAG.getUNDEF(NewVT),
17553 DAG.getIntPtrConstant(0, dl));
17554 SDValue CtlzNode = DAG.getNode(ISD::CTLZ, dl, NewVT, Vec512);
17556 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, CtlzNode,
17557 DAG.getIntPtrConstant(0, dl));
17560 assert((EltVT == MVT::i8 || EltVT == MVT::i16) &&
17561 "Unsupported element type");
17563 if (16 < NumElems) {
17564 // Split vector, it's Lo and Hi parts will be handled in next iteration.
17566 std::tie(Lo, Hi) = DAG.SplitVector(Op.getOperand(0), dl);
17567 MVT OutVT = MVT::getVectorVT(EltVT, NumElems/2);
17569 Lo = DAG.getNode(Op.getOpcode(), dl, OutVT, Lo);
17570 Hi = DAG.getNode(Op.getOpcode(), dl, OutVT, Hi);
17572 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, Lo, Hi);
17575 MVT NewVT = MVT::getVectorVT(MVT::i32, NumElems);
17577 assert((NewVT.is256BitVector() || NewVT.is512BitVector()) &&
17578 "Unsupported value type for operation");
17580 // Use native supported vector instruction vplzcntd.
17581 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, NewVT, Op.getOperand(0));
17582 SDValue CtlzNode = DAG.getNode(ISD::CTLZ, dl, NewVT, Op);
17583 SDValue TruncNode = DAG.getNode(ISD::TRUNCATE, dl, VT, CtlzNode);
17584 SDValue Delta = DAG.getConstant(32 - EltVT.getSizeInBits(), dl, VT);
17586 return DAG.getNode(ISD::SUB, dl, VT, TruncNode, Delta);
17589 static SDValue LowerCTLZ(SDValue Op, const X86Subtarget *Subtarget,
17590 SelectionDAG &DAG) {
17591 MVT VT = Op.getSimpleValueType();
17593 unsigned NumBits = VT.getSizeInBits();
17596 if (VT.isVector() && Subtarget->hasAVX512())
17597 return LowerVectorCTLZ_AVX512(Op, DAG);
17599 Op = Op.getOperand(0);
17600 if (VT == MVT::i8) {
17601 // Zero extend to i32 since there is not an i8 bsr.
17603 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
17606 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
17607 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
17608 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
17610 // If src is zero (i.e. bsr sets ZF), returns NumBits.
17613 DAG.getConstant(NumBits + NumBits - 1, dl, OpVT),
17614 DAG.getConstant(X86::COND_E, dl, MVT::i8),
17617 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops);
17619 // Finally xor with NumBits-1.
17620 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op,
17621 DAG.getConstant(NumBits - 1, dl, OpVT));
17624 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
17628 static SDValue LowerCTLZ_ZERO_UNDEF(SDValue Op, const X86Subtarget *Subtarget,
17629 SelectionDAG &DAG) {
17630 MVT VT = Op.getSimpleValueType();
17632 unsigned NumBits = VT.getSizeInBits();
17635 if (VT.isVector() && Subtarget->hasAVX512())
17636 return LowerVectorCTLZ_AVX512(Op, DAG);
17638 Op = Op.getOperand(0);
17639 if (VT == MVT::i8) {
17640 // Zero extend to i32 since there is not an i8 bsr.
17642 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
17645 // Issue a bsr (scan bits in reverse).
17646 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
17647 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
17649 // And xor with NumBits-1.
17650 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op,
17651 DAG.getConstant(NumBits - 1, dl, OpVT));
17654 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
17658 static SDValue LowerCTTZ(SDValue Op, SelectionDAG &DAG) {
17659 MVT VT = Op.getSimpleValueType();
17660 unsigned NumBits = VT.getScalarSizeInBits();
17663 if (VT.isVector()) {
17664 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
17666 SDValue N0 = Op.getOperand(0);
17667 SDValue Zero = DAG.getConstant(0, dl, VT);
17669 // lsb(x) = (x & -x)
17670 SDValue LSB = DAG.getNode(ISD::AND, dl, VT, N0,
17671 DAG.getNode(ISD::SUB, dl, VT, Zero, N0));
17673 // cttz_undef(x) = (width - 1) - ctlz(lsb)
17674 if (Op.getOpcode() == ISD::CTTZ_ZERO_UNDEF &&
17675 TLI.isOperationLegal(ISD::CTLZ, VT)) {
17676 SDValue WidthMinusOne = DAG.getConstant(NumBits - 1, dl, VT);
17677 return DAG.getNode(ISD::SUB, dl, VT, WidthMinusOne,
17678 DAG.getNode(ISD::CTLZ, dl, VT, LSB));
17681 // cttz(x) = ctpop(lsb - 1)
17682 SDValue One = DAG.getConstant(1, dl, VT);
17683 return DAG.getNode(ISD::CTPOP, dl, VT,
17684 DAG.getNode(ISD::SUB, dl, VT, LSB, One));
17687 assert(Op.getOpcode() == ISD::CTTZ &&
17688 "Only scalar CTTZ requires custom lowering");
17690 // Issue a bsf (scan bits forward) which also sets EFLAGS.
17691 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
17692 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op.getOperand(0));
17694 // If src is zero (i.e. bsf sets ZF), returns NumBits.
17697 DAG.getConstant(NumBits, dl, VT),
17698 DAG.getConstant(X86::COND_E, dl, MVT::i8),
17701 return DAG.getNode(X86ISD::CMOV, dl, VT, Ops);
17704 // Lower256IntArith - Break a 256-bit integer operation into two new 128-bit
17705 // ones, and then concatenate the result back.
17706 static SDValue Lower256IntArith(SDValue Op, SelectionDAG &DAG) {
17707 MVT VT = Op.getSimpleValueType();
17709 assert(VT.is256BitVector() && VT.isInteger() &&
17710 "Unsupported value type for operation");
17712 unsigned NumElems = VT.getVectorNumElements();
17715 // Extract the LHS vectors
17716 SDValue LHS = Op.getOperand(0);
17717 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
17718 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
17720 // Extract the RHS vectors
17721 SDValue RHS = Op.getOperand(1);
17722 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
17723 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
17725 MVT EltVT = VT.getVectorElementType();
17726 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
17728 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
17729 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1),
17730 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2));
17733 static SDValue LowerADD(SDValue Op, SelectionDAG &DAG) {
17734 if (Op.getValueType() == MVT::i1)
17735 return DAG.getNode(ISD::XOR, SDLoc(Op), Op.getValueType(),
17736 Op.getOperand(0), Op.getOperand(1));
17737 assert(Op.getSimpleValueType().is256BitVector() &&
17738 Op.getSimpleValueType().isInteger() &&
17739 "Only handle AVX 256-bit vector integer operation");
17740 return Lower256IntArith(Op, DAG);
17743 static SDValue LowerSUB(SDValue Op, SelectionDAG &DAG) {
17744 if (Op.getValueType() == MVT::i1)
17745 return DAG.getNode(ISD::XOR, SDLoc(Op), Op.getValueType(),
17746 Op.getOperand(0), Op.getOperand(1));
17747 assert(Op.getSimpleValueType().is256BitVector() &&
17748 Op.getSimpleValueType().isInteger() &&
17749 "Only handle AVX 256-bit vector integer operation");
17750 return Lower256IntArith(Op, DAG);
17753 static SDValue LowerMINMAX(SDValue Op, SelectionDAG &DAG) {
17754 assert(Op.getSimpleValueType().is256BitVector() &&
17755 Op.getSimpleValueType().isInteger() &&
17756 "Only handle AVX 256-bit vector integer operation");
17757 return Lower256IntArith(Op, DAG);
17760 static SDValue LowerMUL(SDValue Op, const X86Subtarget *Subtarget,
17761 SelectionDAG &DAG) {
17763 MVT VT = Op.getSimpleValueType();
17766 return DAG.getNode(ISD::AND, dl, VT, Op.getOperand(0), Op.getOperand(1));
17768 // Decompose 256-bit ops into smaller 128-bit ops.
17769 if (VT.is256BitVector() && !Subtarget->hasInt256())
17770 return Lower256IntArith(Op, DAG);
17772 SDValue A = Op.getOperand(0);
17773 SDValue B = Op.getOperand(1);
17775 // Lower v16i8/v32i8 mul as promotion to v8i16/v16i16 vector
17776 // pairs, multiply and truncate.
17777 if (VT == MVT::v16i8 || VT == MVT::v32i8) {
17778 if (Subtarget->hasInt256()) {
17779 if (VT == MVT::v32i8) {
17780 MVT SubVT = MVT::getVectorVT(MVT::i8, VT.getVectorNumElements() / 2);
17781 SDValue Lo = DAG.getIntPtrConstant(0, dl);
17782 SDValue Hi = DAG.getIntPtrConstant(VT.getVectorNumElements() / 2, dl);
17783 SDValue ALo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, A, Lo);
17784 SDValue BLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, B, Lo);
17785 SDValue AHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, A, Hi);
17786 SDValue BHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, B, Hi);
17787 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
17788 DAG.getNode(ISD::MUL, dl, SubVT, ALo, BLo),
17789 DAG.getNode(ISD::MUL, dl, SubVT, AHi, BHi));
17792 MVT ExVT = MVT::getVectorVT(MVT::i16, VT.getVectorNumElements());
17793 return DAG.getNode(
17794 ISD::TRUNCATE, dl, VT,
17795 DAG.getNode(ISD::MUL, dl, ExVT,
17796 DAG.getNode(ISD::SIGN_EXTEND, dl, ExVT, A),
17797 DAG.getNode(ISD::SIGN_EXTEND, dl, ExVT, B)));
17800 assert(VT == MVT::v16i8 &&
17801 "Pre-AVX2 support only supports v16i8 multiplication");
17802 MVT ExVT = MVT::v8i16;
17804 // Extract the lo parts and sign extend to i16
17806 if (Subtarget->hasSSE41()) {
17807 ALo = DAG.getNode(X86ISD::VSEXT, dl, ExVT, A);
17808 BLo = DAG.getNode(X86ISD::VSEXT, dl, ExVT, B);
17810 const int ShufMask[] = {-1, 0, -1, 1, -1, 2, -1, 3,
17811 -1, 4, -1, 5, -1, 6, -1, 7};
17812 ALo = DAG.getVectorShuffle(VT, dl, A, A, ShufMask);
17813 BLo = DAG.getVectorShuffle(VT, dl, B, B, ShufMask);
17814 ALo = DAG.getBitcast(ExVT, ALo);
17815 BLo = DAG.getBitcast(ExVT, BLo);
17816 ALo = DAG.getNode(ISD::SRA, dl, ExVT, ALo, DAG.getConstant(8, dl, ExVT));
17817 BLo = DAG.getNode(ISD::SRA, dl, ExVT, BLo, DAG.getConstant(8, dl, ExVT));
17820 // Extract the hi parts and sign extend to i16
17822 if (Subtarget->hasSSE41()) {
17823 const int ShufMask[] = {8, 9, 10, 11, 12, 13, 14, 15,
17824 -1, -1, -1, -1, -1, -1, -1, -1};
17825 AHi = DAG.getVectorShuffle(VT, dl, A, A, ShufMask);
17826 BHi = DAG.getVectorShuffle(VT, dl, B, B, ShufMask);
17827 AHi = DAG.getNode(X86ISD::VSEXT, dl, ExVT, AHi);
17828 BHi = DAG.getNode(X86ISD::VSEXT, dl, ExVT, BHi);
17830 const int ShufMask[] = {-1, 8, -1, 9, -1, 10, -1, 11,
17831 -1, 12, -1, 13, -1, 14, -1, 15};
17832 AHi = DAG.getVectorShuffle(VT, dl, A, A, ShufMask);
17833 BHi = DAG.getVectorShuffle(VT, dl, B, B, ShufMask);
17834 AHi = DAG.getBitcast(ExVT, AHi);
17835 BHi = DAG.getBitcast(ExVT, BHi);
17836 AHi = DAG.getNode(ISD::SRA, dl, ExVT, AHi, DAG.getConstant(8, dl, ExVT));
17837 BHi = DAG.getNode(ISD::SRA, dl, ExVT, BHi, DAG.getConstant(8, dl, ExVT));
17840 // Multiply, mask the lower 8bits of the lo/hi results and pack
17841 SDValue RLo = DAG.getNode(ISD::MUL, dl, ExVT, ALo, BLo);
17842 SDValue RHi = DAG.getNode(ISD::MUL, dl, ExVT, AHi, BHi);
17843 RLo = DAG.getNode(ISD::AND, dl, ExVT, RLo, DAG.getConstant(255, dl, ExVT));
17844 RHi = DAG.getNode(ISD::AND, dl, ExVT, RHi, DAG.getConstant(255, dl, ExVT));
17845 return DAG.getNode(X86ISD::PACKUS, dl, VT, RLo, RHi);
17848 // Lower v4i32 mul as 2x shuffle, 2x pmuludq, 2x shuffle.
17849 if (VT == MVT::v4i32) {
17850 assert(Subtarget->hasSSE2() && !Subtarget->hasSSE41() &&
17851 "Should not custom lower when pmuldq is available!");
17853 // Extract the odd parts.
17854 static const int UnpackMask[] = { 1, -1, 3, -1 };
17855 SDValue Aodds = DAG.getVectorShuffle(VT, dl, A, A, UnpackMask);
17856 SDValue Bodds = DAG.getVectorShuffle(VT, dl, B, B, UnpackMask);
17858 // Multiply the even parts.
17859 SDValue Evens = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, A, B);
17860 // Now multiply odd parts.
17861 SDValue Odds = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, Aodds, Bodds);
17863 Evens = DAG.getBitcast(VT, Evens);
17864 Odds = DAG.getBitcast(VT, Odds);
17866 // Merge the two vectors back together with a shuffle. This expands into 2
17868 static const int ShufMask[] = { 0, 4, 2, 6 };
17869 return DAG.getVectorShuffle(VT, dl, Evens, Odds, ShufMask);
17872 assert((VT == MVT::v2i64 || VT == MVT::v4i64 || VT == MVT::v8i64) &&
17873 "Only know how to lower V2I64/V4I64/V8I64 multiply");
17875 // Ahi = psrlqi(a, 32);
17876 // Bhi = psrlqi(b, 32);
17878 // AloBlo = pmuludq(a, b);
17879 // AloBhi = pmuludq(a, Bhi);
17880 // AhiBlo = pmuludq(Ahi, b);
17882 // AloBhi = psllqi(AloBhi, 32);
17883 // AhiBlo = psllqi(AhiBlo, 32);
17884 // return AloBlo + AloBhi + AhiBlo;
17886 SDValue Ahi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, A, 32, DAG);
17887 SDValue Bhi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, B, 32, DAG);
17889 SDValue AhiBlo = Ahi;
17890 SDValue AloBhi = Bhi;
17891 // Bit cast to 32-bit vectors for MULUDQ
17892 MVT MulVT = (VT == MVT::v2i64) ? MVT::v4i32 :
17893 (VT == MVT::v4i64) ? MVT::v8i32 : MVT::v16i32;
17894 A = DAG.getBitcast(MulVT, A);
17895 B = DAG.getBitcast(MulVT, B);
17896 Ahi = DAG.getBitcast(MulVT, Ahi);
17897 Bhi = DAG.getBitcast(MulVT, Bhi);
17899 SDValue AloBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, B);
17900 // After shifting right const values the result may be all-zero.
17901 if (!ISD::isBuildVectorAllZeros(Ahi.getNode())) {
17902 AhiBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, Ahi, B);
17903 AhiBlo = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AhiBlo, 32, DAG);
17905 if (!ISD::isBuildVectorAllZeros(Bhi.getNode())) {
17906 AloBhi = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, Bhi);
17907 AloBhi = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AloBhi, 32, DAG);
17910 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
17911 return DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
17914 SDValue X86TargetLowering::LowerWin64_i128OP(SDValue Op, SelectionDAG &DAG) const {
17915 assert(Subtarget->isTargetWin64() && "Unexpected target");
17916 EVT VT = Op.getValueType();
17917 assert(VT.isInteger() && VT.getSizeInBits() == 128 &&
17918 "Unexpected return type for lowering");
17922 switch (Op->getOpcode()) {
17923 default: llvm_unreachable("Unexpected request for libcall!");
17924 case ISD::SDIV: isSigned = true; LC = RTLIB::SDIV_I128; break;
17925 case ISD::UDIV: isSigned = false; LC = RTLIB::UDIV_I128; break;
17926 case ISD::SREM: isSigned = true; LC = RTLIB::SREM_I128; break;
17927 case ISD::UREM: isSigned = false; LC = RTLIB::UREM_I128; break;
17928 case ISD::SDIVREM: isSigned = true; LC = RTLIB::SDIVREM_I128; break;
17929 case ISD::UDIVREM: isSigned = false; LC = RTLIB::UDIVREM_I128; break;
17933 SDValue InChain = DAG.getEntryNode();
17935 TargetLowering::ArgListTy Args;
17936 TargetLowering::ArgListEntry Entry;
17937 for (unsigned i = 0, e = Op->getNumOperands(); i != e; ++i) {
17938 EVT ArgVT = Op->getOperand(i).getValueType();
17939 assert(ArgVT.isInteger() && ArgVT.getSizeInBits() == 128 &&
17940 "Unexpected argument type for lowering");
17941 SDValue StackPtr = DAG.CreateStackTemporary(ArgVT, 16);
17942 Entry.Node = StackPtr;
17943 InChain = DAG.getStore(InChain, dl, Op->getOperand(i), StackPtr, MachinePointerInfo(),
17945 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
17946 Entry.Ty = PointerType::get(ArgTy,0);
17947 Entry.isSExt = false;
17948 Entry.isZExt = false;
17949 Args.push_back(Entry);
17952 SDValue Callee = DAG.getExternalSymbol(getLibcallName(LC),
17953 getPointerTy(DAG.getDataLayout()));
17955 TargetLowering::CallLoweringInfo CLI(DAG);
17956 CLI.setDebugLoc(dl).setChain(InChain)
17957 .setCallee(getLibcallCallingConv(LC),
17958 static_cast<EVT>(MVT::v2i64).getTypeForEVT(*DAG.getContext()),
17959 Callee, std::move(Args), 0)
17960 .setInRegister().setSExtResult(isSigned).setZExtResult(!isSigned);
17962 std::pair<SDValue, SDValue> CallInfo = LowerCallTo(CLI);
17963 return DAG.getBitcast(VT, CallInfo.first);
17966 static SDValue LowerMUL_LOHI(SDValue Op, const X86Subtarget *Subtarget,
17967 SelectionDAG &DAG) {
17968 SDValue Op0 = Op.getOperand(0), Op1 = Op.getOperand(1);
17969 MVT VT = Op0.getSimpleValueType();
17972 assert((VT == MVT::v4i32 && Subtarget->hasSSE2()) ||
17973 (VT == MVT::v8i32 && Subtarget->hasInt256()));
17975 // PMULxD operations multiply each even value (starting at 0) of LHS with
17976 // the related value of RHS and produce a widen result.
17977 // E.g., PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
17978 // => <2 x i64> <ae|cg>
17980 // In other word, to have all the results, we need to perform two PMULxD:
17981 // 1. one with the even values.
17982 // 2. one with the odd values.
17983 // To achieve #2, with need to place the odd values at an even position.
17985 // Place the odd value at an even position (basically, shift all values 1
17986 // step to the left):
17987 const int Mask[] = {1, -1, 3, -1, 5, -1, 7, -1};
17988 // <a|b|c|d> => <b|undef|d|undef>
17989 SDValue Odd0 = DAG.getVectorShuffle(VT, dl, Op0, Op0, Mask);
17990 // <e|f|g|h> => <f|undef|h|undef>
17991 SDValue Odd1 = DAG.getVectorShuffle(VT, dl, Op1, Op1, Mask);
17993 // Emit two multiplies, one for the lower 2 ints and one for the higher 2
17995 MVT MulVT = VT == MVT::v4i32 ? MVT::v2i64 : MVT::v4i64;
17996 bool IsSigned = Op->getOpcode() == ISD::SMUL_LOHI;
17998 (!IsSigned || !Subtarget->hasSSE41()) ? X86ISD::PMULUDQ : X86ISD::PMULDQ;
17999 // PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
18000 // => <2 x i64> <ae|cg>
18001 SDValue Mul1 = DAG.getBitcast(VT, DAG.getNode(Opcode, dl, MulVT, Op0, Op1));
18002 // PMULUDQ <4 x i32> <b|undef|d|undef>, <4 x i32> <f|undef|h|undef>
18003 // => <2 x i64> <bf|dh>
18004 SDValue Mul2 = DAG.getBitcast(VT, DAG.getNode(Opcode, dl, MulVT, Odd0, Odd1));
18006 // Shuffle it back into the right order.
18007 SDValue Highs, Lows;
18008 if (VT == MVT::v8i32) {
18009 const int HighMask[] = {1, 9, 3, 11, 5, 13, 7, 15};
18010 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
18011 const int LowMask[] = {0, 8, 2, 10, 4, 12, 6, 14};
18012 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
18014 const int HighMask[] = {1, 5, 3, 7};
18015 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
18016 const int LowMask[] = {0, 4, 2, 6};
18017 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
18020 // If we have a signed multiply but no PMULDQ fix up the high parts of a
18021 // unsigned multiply.
18022 if (IsSigned && !Subtarget->hasSSE41()) {
18023 SDValue ShAmt = DAG.getConstant(
18025 DAG.getTargetLoweringInfo().getShiftAmountTy(VT, DAG.getDataLayout()));
18026 SDValue T1 = DAG.getNode(ISD::AND, dl, VT,
18027 DAG.getNode(ISD::SRA, dl, VT, Op0, ShAmt), Op1);
18028 SDValue T2 = DAG.getNode(ISD::AND, dl, VT,
18029 DAG.getNode(ISD::SRA, dl, VT, Op1, ShAmt), Op0);
18031 SDValue Fixup = DAG.getNode(ISD::ADD, dl, VT, T1, T2);
18032 Highs = DAG.getNode(ISD::SUB, dl, VT, Highs, Fixup);
18035 // The first result of MUL_LOHI is actually the low value, followed by the
18037 SDValue Ops[] = {Lows, Highs};
18038 return DAG.getMergeValues(Ops, dl);
18041 // Return true if the required (according to Opcode) shift-imm form is natively
18042 // supported by the Subtarget
18043 static bool SupportedVectorShiftWithImm(MVT VT, const X86Subtarget *Subtarget,
18045 if (VT.getScalarSizeInBits() < 16)
18048 if (VT.is512BitVector() &&
18049 (VT.getScalarSizeInBits() > 16 || Subtarget->hasBWI()))
18052 bool LShift = VT.is128BitVector() ||
18053 (VT.is256BitVector() && Subtarget->hasInt256());
18055 bool AShift = LShift && (Subtarget->hasVLX() ||
18056 (VT != MVT::v2i64 && VT != MVT::v4i64));
18057 return (Opcode == ISD::SRA) ? AShift : LShift;
18060 // The shift amount is a variable, but it is the same for all vector lanes.
18061 // These instructions are defined together with shift-immediate.
18063 bool SupportedVectorShiftWithBaseAmnt(MVT VT, const X86Subtarget *Subtarget,
18065 return SupportedVectorShiftWithImm(VT, Subtarget, Opcode);
18068 // Return true if the required (according to Opcode) variable-shift form is
18069 // natively supported by the Subtarget
18070 static bool SupportedVectorVarShift(MVT VT, const X86Subtarget *Subtarget,
18073 if (!Subtarget->hasInt256() || VT.getScalarSizeInBits() < 16)
18076 // vXi16 supported only on AVX-512, BWI
18077 if (VT.getScalarSizeInBits() == 16 && !Subtarget->hasBWI())
18080 if (VT.is512BitVector() || Subtarget->hasVLX())
18083 bool LShift = VT.is128BitVector() || VT.is256BitVector();
18084 bool AShift = LShift && VT != MVT::v2i64 && VT != MVT::v4i64;
18085 return (Opcode == ISD::SRA) ? AShift : LShift;
18088 static SDValue LowerScalarImmediateShift(SDValue Op, SelectionDAG &DAG,
18089 const X86Subtarget *Subtarget) {
18090 MVT VT = Op.getSimpleValueType();
18092 SDValue R = Op.getOperand(0);
18093 SDValue Amt = Op.getOperand(1);
18095 unsigned X86Opc = (Op.getOpcode() == ISD::SHL) ? X86ISD::VSHLI :
18096 (Op.getOpcode() == ISD::SRL) ? X86ISD::VSRLI : X86ISD::VSRAI;
18098 auto ArithmeticShiftRight64 = [&](uint64_t ShiftAmt) {
18099 assert((VT == MVT::v2i64 || VT == MVT::v4i64) && "Unexpected SRA type");
18100 MVT ExVT = MVT::getVectorVT(MVT::i32, VT.getVectorNumElements() * 2);
18101 SDValue Ex = DAG.getBitcast(ExVT, R);
18103 if (ShiftAmt >= 32) {
18104 // Splat sign to upper i32 dst, and SRA upper i32 src to lower i32.
18106 getTargetVShiftByConstNode(X86ISD::VSRAI, dl, ExVT, Ex, 31, DAG);
18107 SDValue Lower = getTargetVShiftByConstNode(X86ISD::VSRAI, dl, ExVT, Ex,
18108 ShiftAmt - 32, DAG);
18109 if (VT == MVT::v2i64)
18110 Ex = DAG.getVectorShuffle(ExVT, dl, Upper, Lower, {5, 1, 7, 3});
18111 if (VT == MVT::v4i64)
18112 Ex = DAG.getVectorShuffle(ExVT, dl, Upper, Lower,
18113 {9, 1, 11, 3, 13, 5, 15, 7});
18115 // SRA upper i32, SHL whole i64 and select lower i32.
18116 SDValue Upper = getTargetVShiftByConstNode(X86ISD::VSRAI, dl, ExVT, Ex,
18119 getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, R, ShiftAmt, DAG);
18120 Lower = DAG.getBitcast(ExVT, Lower);
18121 if (VT == MVT::v2i64)
18122 Ex = DAG.getVectorShuffle(ExVT, dl, Upper, Lower, {4, 1, 6, 3});
18123 if (VT == MVT::v4i64)
18124 Ex = DAG.getVectorShuffle(ExVT, dl, Upper, Lower,
18125 {8, 1, 10, 3, 12, 5, 14, 7});
18127 return DAG.getBitcast(VT, Ex);
18130 // Optimize shl/srl/sra with constant shift amount.
18131 if (auto *BVAmt = dyn_cast<BuildVectorSDNode>(Amt)) {
18132 if (auto *ShiftConst = BVAmt->getConstantSplatNode()) {
18133 uint64_t ShiftAmt = ShiftConst->getZExtValue();
18135 if (SupportedVectorShiftWithImm(VT, Subtarget, Op.getOpcode()))
18136 return getTargetVShiftByConstNode(X86Opc, dl, VT, R, ShiftAmt, DAG);
18138 // i64 SRA needs to be performed as partial shifts.
18139 if ((VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64)) &&
18140 Op.getOpcode() == ISD::SRA && !Subtarget->hasXOP())
18141 return ArithmeticShiftRight64(ShiftAmt);
18143 if (VT == MVT::v16i8 || (Subtarget->hasInt256() && VT == MVT::v32i8)) {
18144 unsigned NumElts = VT.getVectorNumElements();
18145 MVT ShiftVT = MVT::getVectorVT(MVT::i16, NumElts / 2);
18147 // Simple i8 add case
18148 if (Op.getOpcode() == ISD::SHL && ShiftAmt == 1)
18149 return DAG.getNode(ISD::ADD, dl, VT, R, R);
18151 // ashr(R, 7) === cmp_slt(R, 0)
18152 if (Op.getOpcode() == ISD::SRA && ShiftAmt == 7) {
18153 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
18154 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
18157 // XOP can shift v16i8 directly instead of as shift v8i16 + mask.
18158 if (VT == MVT::v16i8 && Subtarget->hasXOP())
18161 if (Op.getOpcode() == ISD::SHL) {
18162 // Make a large shift.
18163 SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, ShiftVT,
18165 SHL = DAG.getBitcast(VT, SHL);
18166 // Zero out the rightmost bits.
18167 SmallVector<SDValue, 32> V(
18168 NumElts, DAG.getConstant(uint8_t(-1U << ShiftAmt), dl, MVT::i8));
18169 return DAG.getNode(ISD::AND, dl, VT, SHL,
18170 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
18172 if (Op.getOpcode() == ISD::SRL) {
18173 // Make a large shift.
18174 SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, ShiftVT,
18176 SRL = DAG.getBitcast(VT, SRL);
18177 // Zero out the leftmost bits.
18178 SmallVector<SDValue, 32> V(
18179 NumElts, DAG.getConstant(uint8_t(-1U) >> ShiftAmt, dl, MVT::i8));
18180 return DAG.getNode(ISD::AND, dl, VT, SRL,
18181 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
18183 if (Op.getOpcode() == ISD::SRA) {
18184 // ashr(R, Amt) === sub(xor(lshr(R, Amt), Mask), Mask)
18185 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
18186 SmallVector<SDValue, 32> V(NumElts,
18187 DAG.getConstant(128 >> ShiftAmt, dl,
18189 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V);
18190 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
18191 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
18194 llvm_unreachable("Unknown shift opcode.");
18199 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
18200 if (!Subtarget->is64Bit() && !Subtarget->hasXOP() &&
18201 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64))) {
18203 // Peek through any splat that was introduced for i64 shift vectorization.
18204 int SplatIndex = -1;
18205 if (ShuffleVectorSDNode *SVN = dyn_cast<ShuffleVectorSDNode>(Amt.getNode()))
18206 if (SVN->isSplat()) {
18207 SplatIndex = SVN->getSplatIndex();
18208 Amt = Amt.getOperand(0);
18209 assert(SplatIndex < (int)VT.getVectorNumElements() &&
18210 "Splat shuffle referencing second operand");
18213 if (Amt.getOpcode() != ISD::BITCAST ||
18214 Amt.getOperand(0).getOpcode() != ISD::BUILD_VECTOR)
18217 Amt = Amt.getOperand(0);
18218 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
18219 VT.getVectorNumElements();
18220 unsigned RatioInLog2 = Log2_32_Ceil(Ratio);
18221 uint64_t ShiftAmt = 0;
18222 unsigned BaseOp = (SplatIndex < 0 ? 0 : SplatIndex * Ratio);
18223 for (unsigned i = 0; i != Ratio; ++i) {
18224 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Amt.getOperand(i + BaseOp));
18228 ShiftAmt |= C->getZExtValue() << (i * (1 << (6 - RatioInLog2)));
18231 // Check remaining shift amounts (if not a splat).
18232 if (SplatIndex < 0) {
18233 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
18234 uint64_t ShAmt = 0;
18235 for (unsigned j = 0; j != Ratio; ++j) {
18236 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Amt.getOperand(i + j));
18240 ShAmt |= C->getZExtValue() << (j * (1 << (6 - RatioInLog2)));
18242 if (ShAmt != ShiftAmt)
18247 if (SupportedVectorShiftWithImm(VT, Subtarget, Op.getOpcode()))
18248 return getTargetVShiftByConstNode(X86Opc, dl, VT, R, ShiftAmt, DAG);
18250 if (Op.getOpcode() == ISD::SRA)
18251 return ArithmeticShiftRight64(ShiftAmt);
18257 static SDValue LowerScalarVariableShift(SDValue Op, SelectionDAG &DAG,
18258 const X86Subtarget* Subtarget) {
18259 MVT VT = Op.getSimpleValueType();
18261 SDValue R = Op.getOperand(0);
18262 SDValue Amt = Op.getOperand(1);
18264 unsigned X86OpcI = (Op.getOpcode() == ISD::SHL) ? X86ISD::VSHLI :
18265 (Op.getOpcode() == ISD::SRL) ? X86ISD::VSRLI : X86ISD::VSRAI;
18267 unsigned X86OpcV = (Op.getOpcode() == ISD::SHL) ? X86ISD::VSHL :
18268 (Op.getOpcode() == ISD::SRL) ? X86ISD::VSRL : X86ISD::VSRA;
18270 if (SupportedVectorShiftWithBaseAmnt(VT, Subtarget, Op.getOpcode())) {
18272 MVT EltVT = VT.getVectorElementType();
18274 if (BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(Amt)) {
18275 // Check if this build_vector node is doing a splat.
18276 // If so, then set BaseShAmt equal to the splat value.
18277 BaseShAmt = BV->getSplatValue();
18278 if (BaseShAmt && BaseShAmt.getOpcode() == ISD::UNDEF)
18279 BaseShAmt = SDValue();
18281 if (Amt.getOpcode() == ISD::EXTRACT_SUBVECTOR)
18282 Amt = Amt.getOperand(0);
18284 ShuffleVectorSDNode *SVN = dyn_cast<ShuffleVectorSDNode>(Amt);
18285 if (SVN && SVN->isSplat()) {
18286 unsigned SplatIdx = (unsigned)SVN->getSplatIndex();
18287 SDValue InVec = Amt.getOperand(0);
18288 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
18289 assert((SplatIdx < InVec.getSimpleValueType().getVectorNumElements()) &&
18290 "Unexpected shuffle index found!");
18291 BaseShAmt = InVec.getOperand(SplatIdx);
18292 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
18293 if (ConstantSDNode *C =
18294 dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
18295 if (C->getZExtValue() == SplatIdx)
18296 BaseShAmt = InVec.getOperand(1);
18301 // Avoid introducing an extract element from a shuffle.
18302 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InVec,
18303 DAG.getIntPtrConstant(SplatIdx, dl));
18307 if (BaseShAmt.getNode()) {
18308 assert(EltVT.bitsLE(MVT::i64) && "Unexpected element type!");
18309 if (EltVT != MVT::i64 && EltVT.bitsGT(MVT::i32))
18310 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, BaseShAmt);
18311 else if (EltVT.bitsLT(MVT::i32))
18312 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, BaseShAmt);
18314 return getTargetVShiftNode(X86OpcI, dl, VT, R, BaseShAmt, DAG);
18318 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
18319 if (!Subtarget->is64Bit() && VT == MVT::v2i64 &&
18320 Amt.getOpcode() == ISD::BITCAST &&
18321 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
18322 Amt = Amt.getOperand(0);
18323 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
18324 VT.getVectorNumElements();
18325 std::vector<SDValue> Vals(Ratio);
18326 for (unsigned i = 0; i != Ratio; ++i)
18327 Vals[i] = Amt.getOperand(i);
18328 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
18329 for (unsigned j = 0; j != Ratio; ++j)
18330 if (Vals[j] != Amt.getOperand(i + j))
18334 if (SupportedVectorShiftWithBaseAmnt(VT, Subtarget, Op.getOpcode()))
18335 return DAG.getNode(X86OpcV, dl, VT, R, Op.getOperand(1));
18340 static SDValue LowerShift(SDValue Op, const X86Subtarget* Subtarget,
18341 SelectionDAG &DAG) {
18342 MVT VT = Op.getSimpleValueType();
18344 SDValue R = Op.getOperand(0);
18345 SDValue Amt = Op.getOperand(1);
18347 assert(VT.isVector() && "Custom lowering only for vector shifts!");
18348 assert(Subtarget->hasSSE2() && "Only custom lower when we have SSE2!");
18350 if (SDValue V = LowerScalarImmediateShift(Op, DAG, Subtarget))
18353 if (SDValue V = LowerScalarVariableShift(Op, DAG, Subtarget))
18356 if (SupportedVectorVarShift(VT, Subtarget, Op.getOpcode()))
18359 // XOP has 128-bit variable logical/arithmetic shifts.
18360 // +ve/-ve Amt = shift left/right.
18361 if (Subtarget->hasXOP() &&
18362 (VT == MVT::v2i64 || VT == MVT::v4i32 ||
18363 VT == MVT::v8i16 || VT == MVT::v16i8)) {
18364 if (Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SRA) {
18365 SDValue Zero = getZeroVector(VT, Subtarget, DAG, dl);
18366 Amt = DAG.getNode(ISD::SUB, dl, VT, Zero, Amt);
18368 if (Op.getOpcode() == ISD::SHL || Op.getOpcode() == ISD::SRL)
18369 return DAG.getNode(X86ISD::VPSHL, dl, VT, R, Amt);
18370 if (Op.getOpcode() == ISD::SRA)
18371 return DAG.getNode(X86ISD::VPSHA, dl, VT, R, Amt);
18374 // 2i64 vector logical shifts can efficiently avoid scalarization - do the
18375 // shifts per-lane and then shuffle the partial results back together.
18376 if (VT == MVT::v2i64 && Op.getOpcode() != ISD::SRA) {
18377 // Splat the shift amounts so the scalar shifts above will catch it.
18378 SDValue Amt0 = DAG.getVectorShuffle(VT, dl, Amt, Amt, {0, 0});
18379 SDValue Amt1 = DAG.getVectorShuffle(VT, dl, Amt, Amt, {1, 1});
18380 SDValue R0 = DAG.getNode(Op->getOpcode(), dl, VT, R, Amt0);
18381 SDValue R1 = DAG.getNode(Op->getOpcode(), dl, VT, R, Amt1);
18382 return DAG.getVectorShuffle(VT, dl, R0, R1, {0, 3});
18385 // i64 vector arithmetic shift can be emulated with the transform:
18386 // M = lshr(SIGN_BIT, Amt)
18387 // ashr(R, Amt) === sub(xor(lshr(R, Amt), M), M)
18388 if ((VT == MVT::v2i64 || (VT == MVT::v4i64 && Subtarget->hasInt256())) &&
18389 Op.getOpcode() == ISD::SRA) {
18390 SDValue S = DAG.getConstant(APInt::getSignBit(64), dl, VT);
18391 SDValue M = DAG.getNode(ISD::SRL, dl, VT, S, Amt);
18392 R = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
18393 R = DAG.getNode(ISD::XOR, dl, VT, R, M);
18394 R = DAG.getNode(ISD::SUB, dl, VT, R, M);
18398 // If possible, lower this packed shift into a vector multiply instead of
18399 // expanding it into a sequence of scalar shifts.
18400 // Do this only if the vector shift count is a constant build_vector.
18401 if (Op.getOpcode() == ISD::SHL &&
18402 (VT == MVT::v8i16 || VT == MVT::v4i32 ||
18403 (Subtarget->hasInt256() && VT == MVT::v16i16)) &&
18404 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
18405 SmallVector<SDValue, 8> Elts;
18406 MVT SVT = VT.getVectorElementType();
18407 unsigned SVTBits = SVT.getSizeInBits();
18408 APInt One(SVTBits, 1);
18409 unsigned NumElems = VT.getVectorNumElements();
18411 for (unsigned i=0; i !=NumElems; ++i) {
18412 SDValue Op = Amt->getOperand(i);
18413 if (Op->getOpcode() == ISD::UNDEF) {
18414 Elts.push_back(Op);
18418 ConstantSDNode *ND = cast<ConstantSDNode>(Op);
18419 APInt C(SVTBits, ND->getAPIntValue().getZExtValue());
18420 uint64_t ShAmt = C.getZExtValue();
18421 if (ShAmt >= SVTBits) {
18422 Elts.push_back(DAG.getUNDEF(SVT));
18425 Elts.push_back(DAG.getConstant(One.shl(ShAmt), dl, SVT));
18427 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
18428 return DAG.getNode(ISD::MUL, dl, VT, R, BV);
18431 // Lower SHL with variable shift amount.
18432 if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) {
18433 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(23, dl, VT));
18435 Op = DAG.getNode(ISD::ADD, dl, VT, Op,
18436 DAG.getConstant(0x3f800000U, dl, VT));
18437 Op = DAG.getBitcast(MVT::v4f32, Op);
18438 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op);
18439 return DAG.getNode(ISD::MUL, dl, VT, Op, R);
18442 // If possible, lower this shift as a sequence of two shifts by
18443 // constant plus a MOVSS/MOVSD instead of scalarizing it.
18445 // (v4i32 (srl A, (build_vector < X, Y, Y, Y>)))
18447 // Could be rewritten as:
18448 // (v4i32 (MOVSS (srl A, <Y,Y,Y,Y>), (srl A, <X,X,X,X>)))
18450 // The advantage is that the two shifts from the example would be
18451 // lowered as X86ISD::VSRLI nodes. This would be cheaper than scalarizing
18452 // the vector shift into four scalar shifts plus four pairs of vector
18454 if ((VT == MVT::v8i16 || VT == MVT::v4i32) &&
18455 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
18456 unsigned TargetOpcode = X86ISD::MOVSS;
18457 bool CanBeSimplified;
18458 // The splat value for the first packed shift (the 'X' from the example).
18459 SDValue Amt1 = Amt->getOperand(0);
18460 // The splat value for the second packed shift (the 'Y' from the example).
18461 SDValue Amt2 = (VT == MVT::v4i32) ? Amt->getOperand(1) :
18462 Amt->getOperand(2);
18464 // See if it is possible to replace this node with a sequence of
18465 // two shifts followed by a MOVSS/MOVSD
18466 if (VT == MVT::v4i32) {
18467 // Check if it is legal to use a MOVSS.
18468 CanBeSimplified = Amt2 == Amt->getOperand(2) &&
18469 Amt2 == Amt->getOperand(3);
18470 if (!CanBeSimplified) {
18471 // Otherwise, check if we can still simplify this node using a MOVSD.
18472 CanBeSimplified = Amt1 == Amt->getOperand(1) &&
18473 Amt->getOperand(2) == Amt->getOperand(3);
18474 TargetOpcode = X86ISD::MOVSD;
18475 Amt2 = Amt->getOperand(2);
18478 // Do similar checks for the case where the machine value type
18480 CanBeSimplified = Amt1 == Amt->getOperand(1);
18481 for (unsigned i=3; i != 8 && CanBeSimplified; ++i)
18482 CanBeSimplified = Amt2 == Amt->getOperand(i);
18484 if (!CanBeSimplified) {
18485 TargetOpcode = X86ISD::MOVSD;
18486 CanBeSimplified = true;
18487 Amt2 = Amt->getOperand(4);
18488 for (unsigned i=0; i != 4 && CanBeSimplified; ++i)
18489 CanBeSimplified = Amt1 == Amt->getOperand(i);
18490 for (unsigned j=4; j != 8 && CanBeSimplified; ++j)
18491 CanBeSimplified = Amt2 == Amt->getOperand(j);
18495 if (CanBeSimplified && isa<ConstantSDNode>(Amt1) &&
18496 isa<ConstantSDNode>(Amt2)) {
18497 // Replace this node with two shifts followed by a MOVSS/MOVSD.
18498 MVT CastVT = MVT::v4i32;
18500 DAG.getConstant(cast<ConstantSDNode>(Amt1)->getAPIntValue(), dl, VT);
18501 SDValue Shift1 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat1);
18503 DAG.getConstant(cast<ConstantSDNode>(Amt2)->getAPIntValue(), dl, VT);
18504 SDValue Shift2 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat2);
18505 if (TargetOpcode == X86ISD::MOVSD)
18506 CastVT = MVT::v2i64;
18507 SDValue BitCast1 = DAG.getBitcast(CastVT, Shift1);
18508 SDValue BitCast2 = DAG.getBitcast(CastVT, Shift2);
18509 SDValue Result = getTargetShuffleNode(TargetOpcode, dl, CastVT, BitCast2,
18511 return DAG.getBitcast(VT, Result);
18515 // v4i32 Non Uniform Shifts.
18516 // If the shift amount is constant we can shift each lane using the SSE2
18517 // immediate shifts, else we need to zero-extend each lane to the lower i64
18518 // and shift using the SSE2 variable shifts.
18519 // The separate results can then be blended together.
18520 if (VT == MVT::v4i32) {
18521 unsigned Opc = Op.getOpcode();
18522 SDValue Amt0, Amt1, Amt2, Amt3;
18523 if (ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
18524 Amt0 = DAG.getVectorShuffle(VT, dl, Amt, DAG.getUNDEF(VT), {0, 0, 0, 0});
18525 Amt1 = DAG.getVectorShuffle(VT, dl, Amt, DAG.getUNDEF(VT), {1, 1, 1, 1});
18526 Amt2 = DAG.getVectorShuffle(VT, dl, Amt, DAG.getUNDEF(VT), {2, 2, 2, 2});
18527 Amt3 = DAG.getVectorShuffle(VT, dl, Amt, DAG.getUNDEF(VT), {3, 3, 3, 3});
18529 // ISD::SHL is handled above but we include it here for completeness.
18532 llvm_unreachable("Unknown target vector shift node");
18534 Opc = X86ISD::VSHL;
18537 Opc = X86ISD::VSRL;
18540 Opc = X86ISD::VSRA;
18543 // The SSE2 shifts use the lower i64 as the same shift amount for
18544 // all lanes and the upper i64 is ignored. These shuffle masks
18545 // optimally zero-extend each lanes on SSE2/SSE41/AVX targets.
18546 SDValue Z = getZeroVector(VT, Subtarget, DAG, dl);
18547 Amt0 = DAG.getVectorShuffle(VT, dl, Amt, Z, {0, 4, -1, -1});
18548 Amt1 = DAG.getVectorShuffle(VT, dl, Amt, Z, {1, 5, -1, -1});
18549 Amt2 = DAG.getVectorShuffle(VT, dl, Amt, Z, {2, 6, -1, -1});
18550 Amt3 = DAG.getVectorShuffle(VT, dl, Amt, Z, {3, 7, -1, -1});
18553 SDValue R0 = DAG.getNode(Opc, dl, VT, R, Amt0);
18554 SDValue R1 = DAG.getNode(Opc, dl, VT, R, Amt1);
18555 SDValue R2 = DAG.getNode(Opc, dl, VT, R, Amt2);
18556 SDValue R3 = DAG.getNode(Opc, dl, VT, R, Amt3);
18557 SDValue R02 = DAG.getVectorShuffle(VT, dl, R0, R2, {0, -1, 6, -1});
18558 SDValue R13 = DAG.getVectorShuffle(VT, dl, R1, R3, {-1, 1, -1, 7});
18559 return DAG.getVectorShuffle(VT, dl, R02, R13, {0, 5, 2, 7});
18562 if (VT == MVT::v16i8 ||
18563 (VT == MVT::v32i8 && Subtarget->hasInt256() && !Subtarget->hasXOP())) {
18564 MVT ExtVT = MVT::getVectorVT(MVT::i16, VT.getVectorNumElements() / 2);
18565 unsigned ShiftOpcode = Op->getOpcode();
18567 auto SignBitSelect = [&](MVT SelVT, SDValue Sel, SDValue V0, SDValue V1) {
18568 // On SSE41 targets we make use of the fact that VSELECT lowers
18569 // to PBLENDVB which selects bytes based just on the sign bit.
18570 if (Subtarget->hasSSE41()) {
18571 V0 = DAG.getBitcast(VT, V0);
18572 V1 = DAG.getBitcast(VT, V1);
18573 Sel = DAG.getBitcast(VT, Sel);
18574 return DAG.getBitcast(SelVT,
18575 DAG.getNode(ISD::VSELECT, dl, VT, Sel, V0, V1));
18577 // On pre-SSE41 targets we test for the sign bit by comparing to
18578 // zero - a negative value will set all bits of the lanes to true
18579 // and VSELECT uses that in its OR(AND(V0,C),AND(V1,~C)) lowering.
18580 SDValue Z = getZeroVector(SelVT, Subtarget, DAG, dl);
18581 SDValue C = DAG.getNode(X86ISD::PCMPGT, dl, SelVT, Z, Sel);
18582 return DAG.getNode(ISD::VSELECT, dl, SelVT, C, V0, V1);
18585 // Turn 'a' into a mask suitable for VSELECT: a = a << 5;
18586 // We can safely do this using i16 shifts as we're only interested in
18587 // the 3 lower bits of each byte.
18588 Amt = DAG.getBitcast(ExtVT, Amt);
18589 Amt = DAG.getNode(ISD::SHL, dl, ExtVT, Amt, DAG.getConstant(5, dl, ExtVT));
18590 Amt = DAG.getBitcast(VT, Amt);
18592 if (Op->getOpcode() == ISD::SHL || Op->getOpcode() == ISD::SRL) {
18593 // r = VSELECT(r, shift(r, 4), a);
18595 DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(4, dl, VT));
18596 R = SignBitSelect(VT, Amt, M, R);
18599 Amt = DAG.getNode(ISD::ADD, dl, VT, Amt, Amt);
18601 // r = VSELECT(r, shift(r, 2), a);
18602 M = DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(2, dl, VT));
18603 R = SignBitSelect(VT, Amt, M, R);
18606 Amt = DAG.getNode(ISD::ADD, dl, VT, Amt, Amt);
18608 // return VSELECT(r, shift(r, 1), a);
18609 M = DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(1, dl, VT));
18610 R = SignBitSelect(VT, Amt, M, R);
18614 if (Op->getOpcode() == ISD::SRA) {
18615 // For SRA we need to unpack each byte to the higher byte of a i16 vector
18616 // so we can correctly sign extend. We don't care what happens to the
18618 SDValue ALo = DAG.getNode(X86ISD::UNPCKL, dl, VT, DAG.getUNDEF(VT), Amt);
18619 SDValue AHi = DAG.getNode(X86ISD::UNPCKH, dl, VT, DAG.getUNDEF(VT), Amt);
18620 SDValue RLo = DAG.getNode(X86ISD::UNPCKL, dl, VT, DAG.getUNDEF(VT), R);
18621 SDValue RHi = DAG.getNode(X86ISD::UNPCKH, dl, VT, DAG.getUNDEF(VT), R);
18622 ALo = DAG.getBitcast(ExtVT, ALo);
18623 AHi = DAG.getBitcast(ExtVT, AHi);
18624 RLo = DAG.getBitcast(ExtVT, RLo);
18625 RHi = DAG.getBitcast(ExtVT, RHi);
18627 // r = VSELECT(r, shift(r, 4), a);
18628 SDValue MLo = DAG.getNode(ShiftOpcode, dl, ExtVT, RLo,
18629 DAG.getConstant(4, dl, ExtVT));
18630 SDValue MHi = DAG.getNode(ShiftOpcode, dl, ExtVT, RHi,
18631 DAG.getConstant(4, dl, ExtVT));
18632 RLo = SignBitSelect(ExtVT, ALo, MLo, RLo);
18633 RHi = SignBitSelect(ExtVT, AHi, MHi, RHi);
18636 ALo = DAG.getNode(ISD::ADD, dl, ExtVT, ALo, ALo);
18637 AHi = DAG.getNode(ISD::ADD, dl, ExtVT, AHi, AHi);
18639 // r = VSELECT(r, shift(r, 2), a);
18640 MLo = DAG.getNode(ShiftOpcode, dl, ExtVT, RLo,
18641 DAG.getConstant(2, dl, ExtVT));
18642 MHi = DAG.getNode(ShiftOpcode, dl, ExtVT, RHi,
18643 DAG.getConstant(2, dl, ExtVT));
18644 RLo = SignBitSelect(ExtVT, ALo, MLo, RLo);
18645 RHi = SignBitSelect(ExtVT, AHi, MHi, RHi);
18648 ALo = DAG.getNode(ISD::ADD, dl, ExtVT, ALo, ALo);
18649 AHi = DAG.getNode(ISD::ADD, dl, ExtVT, AHi, AHi);
18651 // r = VSELECT(r, shift(r, 1), a);
18652 MLo = DAG.getNode(ShiftOpcode, dl, ExtVT, RLo,
18653 DAG.getConstant(1, dl, ExtVT));
18654 MHi = DAG.getNode(ShiftOpcode, dl, ExtVT, RHi,
18655 DAG.getConstant(1, dl, ExtVT));
18656 RLo = SignBitSelect(ExtVT, ALo, MLo, RLo);
18657 RHi = SignBitSelect(ExtVT, AHi, MHi, RHi);
18659 // Logical shift the result back to the lower byte, leaving a zero upper
18661 // meaning that we can safely pack with PACKUSWB.
18663 DAG.getNode(ISD::SRL, dl, ExtVT, RLo, DAG.getConstant(8, dl, ExtVT));
18665 DAG.getNode(ISD::SRL, dl, ExtVT, RHi, DAG.getConstant(8, dl, ExtVT));
18666 return DAG.getNode(X86ISD::PACKUS, dl, VT, RLo, RHi);
18670 // It's worth extending once and using the v8i32 shifts for 16-bit types, but
18671 // the extra overheads to get from v16i8 to v8i32 make the existing SSE
18672 // solution better.
18673 if (Subtarget->hasInt256() && VT == MVT::v8i16) {
18674 MVT ExtVT = MVT::v8i32;
18676 Op.getOpcode() == ISD::SRA ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
18677 R = DAG.getNode(ExtOpc, dl, ExtVT, R);
18678 Amt = DAG.getNode(ISD::ANY_EXTEND, dl, ExtVT, Amt);
18679 return DAG.getNode(ISD::TRUNCATE, dl, VT,
18680 DAG.getNode(Op.getOpcode(), dl, ExtVT, R, Amt));
18683 if (Subtarget->hasInt256() && !Subtarget->hasXOP() && VT == MVT::v16i16) {
18684 MVT ExtVT = MVT::v8i32;
18685 SDValue Z = getZeroVector(VT, Subtarget, DAG, dl);
18686 SDValue ALo = DAG.getNode(X86ISD::UNPCKL, dl, VT, Amt, Z);
18687 SDValue AHi = DAG.getNode(X86ISD::UNPCKH, dl, VT, Amt, Z);
18688 SDValue RLo = DAG.getNode(X86ISD::UNPCKL, dl, VT, R, R);
18689 SDValue RHi = DAG.getNode(X86ISD::UNPCKH, dl, VT, R, R);
18690 ALo = DAG.getBitcast(ExtVT, ALo);
18691 AHi = DAG.getBitcast(ExtVT, AHi);
18692 RLo = DAG.getBitcast(ExtVT, RLo);
18693 RHi = DAG.getBitcast(ExtVT, RHi);
18694 SDValue Lo = DAG.getNode(Op.getOpcode(), dl, ExtVT, RLo, ALo);
18695 SDValue Hi = DAG.getNode(Op.getOpcode(), dl, ExtVT, RHi, AHi);
18696 Lo = DAG.getNode(ISD::SRL, dl, ExtVT, Lo, DAG.getConstant(16, dl, ExtVT));
18697 Hi = DAG.getNode(ISD::SRL, dl, ExtVT, Hi, DAG.getConstant(16, dl, ExtVT));
18698 return DAG.getNode(X86ISD::PACKUS, dl, VT, Lo, Hi);
18701 if (VT == MVT::v8i16) {
18702 unsigned ShiftOpcode = Op->getOpcode();
18704 auto SignBitSelect = [&](SDValue Sel, SDValue V0, SDValue V1) {
18705 // On SSE41 targets we make use of the fact that VSELECT lowers
18706 // to PBLENDVB which selects bytes based just on the sign bit.
18707 if (Subtarget->hasSSE41()) {
18708 MVT ExtVT = MVT::getVectorVT(MVT::i8, VT.getVectorNumElements() * 2);
18709 V0 = DAG.getBitcast(ExtVT, V0);
18710 V1 = DAG.getBitcast(ExtVT, V1);
18711 Sel = DAG.getBitcast(ExtVT, Sel);
18712 return DAG.getBitcast(
18713 VT, DAG.getNode(ISD::VSELECT, dl, ExtVT, Sel, V0, V1));
18715 // On pre-SSE41 targets we splat the sign bit - a negative value will
18716 // set all bits of the lanes to true and VSELECT uses that in
18717 // its OR(AND(V0,C),AND(V1,~C)) lowering.
18719 DAG.getNode(ISD::SRA, dl, VT, Sel, DAG.getConstant(15, dl, VT));
18720 return DAG.getNode(ISD::VSELECT, dl, VT, C, V0, V1);
18723 // Turn 'a' into a mask suitable for VSELECT: a = a << 12;
18724 if (Subtarget->hasSSE41()) {
18725 // On SSE41 targets we need to replicate the shift mask in both
18726 // bytes for PBLENDVB.
18729 DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(4, dl, VT)),
18730 DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(12, dl, VT)));
18732 Amt = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(12, dl, VT));
18735 // r = VSELECT(r, shift(r, 8), a);
18736 SDValue M = DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(8, dl, VT));
18737 R = SignBitSelect(Amt, M, R);
18740 Amt = DAG.getNode(ISD::ADD, dl, VT, Amt, Amt);
18742 // r = VSELECT(r, shift(r, 4), a);
18743 M = DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(4, dl, VT));
18744 R = SignBitSelect(Amt, M, R);
18747 Amt = DAG.getNode(ISD::ADD, dl, VT, Amt, Amt);
18749 // r = VSELECT(r, shift(r, 2), a);
18750 M = DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(2, dl, VT));
18751 R = SignBitSelect(Amt, M, R);
18754 Amt = DAG.getNode(ISD::ADD, dl, VT, Amt, Amt);
18756 // return VSELECT(r, shift(r, 1), a);
18757 M = DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(1, dl, VT));
18758 R = SignBitSelect(Amt, M, R);
18762 // Decompose 256-bit shifts into smaller 128-bit shifts.
18763 if (VT.is256BitVector()) {
18764 unsigned NumElems = VT.getVectorNumElements();
18765 MVT EltVT = VT.getVectorElementType();
18766 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
18768 // Extract the two vectors
18769 SDValue V1 = Extract128BitVector(R, 0, DAG, dl);
18770 SDValue V2 = Extract128BitVector(R, NumElems/2, DAG, dl);
18772 // Recreate the shift amount vectors
18773 SDValue Amt1, Amt2;
18774 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
18775 // Constant shift amount
18776 SmallVector<SDValue, 8> Ops(Amt->op_begin(), Amt->op_begin() + NumElems);
18777 ArrayRef<SDValue> Amt1Csts = makeArrayRef(Ops).slice(0, NumElems / 2);
18778 ArrayRef<SDValue> Amt2Csts = makeArrayRef(Ops).slice(NumElems / 2);
18780 Amt1 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt1Csts);
18781 Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt2Csts);
18783 // Variable shift amount
18784 Amt1 = Extract128BitVector(Amt, 0, DAG, dl);
18785 Amt2 = Extract128BitVector(Amt, NumElems/2, DAG, dl);
18788 // Issue new vector shifts for the smaller types
18789 V1 = DAG.getNode(Op.getOpcode(), dl, NewVT, V1, Amt1);
18790 V2 = DAG.getNode(Op.getOpcode(), dl, NewVT, V2, Amt2);
18792 // Concatenate the result back
18793 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, V1, V2);
18799 static SDValue LowerRotate(SDValue Op, const X86Subtarget *Subtarget,
18800 SelectionDAG &DAG) {
18801 MVT VT = Op.getSimpleValueType();
18803 SDValue R = Op.getOperand(0);
18804 SDValue Amt = Op.getOperand(1);
18806 assert(VT.isVector() && "Custom lowering only for vector rotates!");
18807 assert(Subtarget->hasXOP() && "XOP support required for vector rotates!");
18808 assert((Op.getOpcode() == ISD::ROTL) && "Only ROTL supported");
18810 // XOP has 128-bit vector variable + immediate rotates.
18811 // +ve/-ve Amt = rotate left/right.
18813 // Split 256-bit integers.
18814 if (VT.is256BitVector())
18815 return Lower256IntArith(Op, DAG);
18817 assert(VT.is128BitVector() && "Only rotate 128-bit vectors!");
18819 // Attempt to rotate by immediate.
18820 if (auto *BVAmt = dyn_cast<BuildVectorSDNode>(Amt)) {
18821 if (auto *RotateConst = BVAmt->getConstantSplatNode()) {
18822 uint64_t RotateAmt = RotateConst->getAPIntValue().getZExtValue();
18823 assert(RotateAmt < VT.getScalarSizeInBits() && "Rotation out of range");
18824 return DAG.getNode(X86ISD::VPROTI, DL, VT, R,
18825 DAG.getConstant(RotateAmt, DL, MVT::i8));
18829 // Use general rotate by variable (per-element).
18830 return DAG.getNode(X86ISD::VPROT, DL, VT, R, Amt);
18833 static SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) {
18834 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
18835 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
18836 // looks for this combo and may remove the "setcc" instruction if the "setcc"
18837 // has only one use.
18838 SDNode *N = Op.getNode();
18839 SDValue LHS = N->getOperand(0);
18840 SDValue RHS = N->getOperand(1);
18841 unsigned BaseOp = 0;
18844 switch (Op.getOpcode()) {
18845 default: llvm_unreachable("Unknown ovf instruction!");
18847 // A subtract of one will be selected as a INC. Note that INC doesn't
18848 // set CF, so we can't do this for UADDO.
18849 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
18851 BaseOp = X86ISD::INC;
18852 Cond = X86::COND_O;
18855 BaseOp = X86ISD::ADD;
18856 Cond = X86::COND_O;
18859 BaseOp = X86ISD::ADD;
18860 Cond = X86::COND_B;
18863 // A subtract of one will be selected as a DEC. Note that DEC doesn't
18864 // set CF, so we can't do this for USUBO.
18865 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
18867 BaseOp = X86ISD::DEC;
18868 Cond = X86::COND_O;
18871 BaseOp = X86ISD::SUB;
18872 Cond = X86::COND_O;
18875 BaseOp = X86ISD::SUB;
18876 Cond = X86::COND_B;
18879 BaseOp = N->getValueType(0) == MVT::i8 ? X86ISD::SMUL8 : X86ISD::SMUL;
18880 Cond = X86::COND_O;
18882 case ISD::UMULO: { // i64, i8 = umulo lhs, rhs --> i64, i64, i32 umul lhs,rhs
18883 if (N->getValueType(0) == MVT::i8) {
18884 BaseOp = X86ISD::UMUL8;
18885 Cond = X86::COND_O;
18888 SDVTList VTs = DAG.getVTList(N->getValueType(0), N->getValueType(0),
18890 SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS);
18893 DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
18894 DAG.getConstant(X86::COND_O, DL, MVT::i32),
18895 SDValue(Sum.getNode(), 2));
18897 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
18901 // Also sets EFLAGS.
18902 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
18903 SDValue Sum = DAG.getNode(BaseOp, DL, VTs, LHS, RHS);
18906 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1),
18907 DAG.getConstant(Cond, DL, MVT::i32),
18908 SDValue(Sum.getNode(), 1));
18910 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
18913 /// Returns true if the operand type is exactly twice the native width, and
18914 /// the corresponding cmpxchg8b or cmpxchg16b instruction is available.
18915 /// Used to know whether to use cmpxchg8/16b when expanding atomic operations
18916 /// (otherwise we leave them alone to become __sync_fetch_and_... calls).
18917 bool X86TargetLowering::needsCmpXchgNb(Type *MemType) const {
18918 unsigned OpWidth = MemType->getPrimitiveSizeInBits();
18921 return !Subtarget->is64Bit(); // FIXME this should be Subtarget.hasCmpxchg8b
18922 else if (OpWidth == 128)
18923 return Subtarget->hasCmpxchg16b();
18928 bool X86TargetLowering::shouldExpandAtomicStoreInIR(StoreInst *SI) const {
18929 return needsCmpXchgNb(SI->getValueOperand()->getType());
18932 // Note: this turns large loads into lock cmpxchg8b/16b.
18933 // FIXME: On 32 bits x86, fild/movq might be faster than lock cmpxchg8b.
18934 TargetLowering::AtomicExpansionKind
18935 X86TargetLowering::shouldExpandAtomicLoadInIR(LoadInst *LI) const {
18936 auto PTy = cast<PointerType>(LI->getPointerOperand()->getType());
18937 return needsCmpXchgNb(PTy->getElementType()) ? AtomicExpansionKind::CmpXChg
18938 : AtomicExpansionKind::None;
18941 TargetLowering::AtomicExpansionKind
18942 X86TargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const {
18943 unsigned NativeWidth = Subtarget->is64Bit() ? 64 : 32;
18944 Type *MemType = AI->getType();
18946 // If the operand is too big, we must see if cmpxchg8/16b is available
18947 // and default to library calls otherwise.
18948 if (MemType->getPrimitiveSizeInBits() > NativeWidth) {
18949 return needsCmpXchgNb(MemType) ? AtomicExpansionKind::CmpXChg
18950 : AtomicExpansionKind::None;
18953 AtomicRMWInst::BinOp Op = AI->getOperation();
18956 llvm_unreachable("Unknown atomic operation");
18957 case AtomicRMWInst::Xchg:
18958 case AtomicRMWInst::Add:
18959 case AtomicRMWInst::Sub:
18960 // It's better to use xadd, xsub or xchg for these in all cases.
18961 return AtomicExpansionKind::None;
18962 case AtomicRMWInst::Or:
18963 case AtomicRMWInst::And:
18964 case AtomicRMWInst::Xor:
18965 // If the atomicrmw's result isn't actually used, we can just add a "lock"
18966 // prefix to a normal instruction for these operations.
18967 return !AI->use_empty() ? AtomicExpansionKind::CmpXChg
18968 : AtomicExpansionKind::None;
18969 case AtomicRMWInst::Nand:
18970 case AtomicRMWInst::Max:
18971 case AtomicRMWInst::Min:
18972 case AtomicRMWInst::UMax:
18973 case AtomicRMWInst::UMin:
18974 // These always require a non-trivial set of data operations on x86. We must
18975 // use a cmpxchg loop.
18976 return AtomicExpansionKind::CmpXChg;
18980 static bool hasMFENCE(const X86Subtarget& Subtarget) {
18981 // Use mfence if we have SSE2 or we're on x86-64 (even if we asked for
18982 // no-sse2). There isn't any reason to disable it if the target processor
18984 return Subtarget.hasSSE2() || Subtarget.is64Bit();
18988 X86TargetLowering::lowerIdempotentRMWIntoFencedLoad(AtomicRMWInst *AI) const {
18989 unsigned NativeWidth = Subtarget->is64Bit() ? 64 : 32;
18990 Type *MemType = AI->getType();
18991 // Accesses larger than the native width are turned into cmpxchg/libcalls, so
18992 // there is no benefit in turning such RMWs into loads, and it is actually
18993 // harmful as it introduces a mfence.
18994 if (MemType->getPrimitiveSizeInBits() > NativeWidth)
18997 auto Builder = IRBuilder<>(AI);
18998 Module *M = Builder.GetInsertBlock()->getParent()->getParent();
18999 auto SynchScope = AI->getSynchScope();
19000 // We must restrict the ordering to avoid generating loads with Release or
19001 // ReleaseAcquire orderings.
19002 auto Order = AtomicCmpXchgInst::getStrongestFailureOrdering(AI->getOrdering());
19003 auto Ptr = AI->getPointerOperand();
19005 // Before the load we need a fence. Here is an example lifted from
19006 // http://www.hpl.hp.com/techreports/2012/HPL-2012-68.pdf showing why a fence
19009 // x.store(1, relaxed);
19010 // r1 = y.fetch_add(0, release);
19012 // y.fetch_add(42, acquire);
19013 // r2 = x.load(relaxed);
19014 // r1 = r2 = 0 is impossible, but becomes possible if the idempotent rmw is
19015 // lowered to just a load without a fence. A mfence flushes the store buffer,
19016 // making the optimization clearly correct.
19017 // FIXME: it is required if isAtLeastRelease(Order) but it is not clear
19018 // otherwise, we might be able to be more aggressive on relaxed idempotent
19019 // rmw. In practice, they do not look useful, so we don't try to be
19020 // especially clever.
19021 if (SynchScope == SingleThread)
19022 // FIXME: we could just insert an X86ISD::MEMBARRIER here, except we are at
19023 // the IR level, so we must wrap it in an intrinsic.
19026 if (!hasMFENCE(*Subtarget))
19027 // FIXME: it might make sense to use a locked operation here but on a
19028 // different cache-line to prevent cache-line bouncing. In practice it
19029 // is probably a small win, and x86 processors without mfence are rare
19030 // enough that we do not bother.
19034 llvm::Intrinsic::getDeclaration(M, Intrinsic::x86_sse2_mfence);
19035 Builder.CreateCall(MFence, {});
19037 // Finally we can emit the atomic load.
19038 LoadInst *Loaded = Builder.CreateAlignedLoad(Ptr,
19039 AI->getType()->getPrimitiveSizeInBits());
19040 Loaded->setAtomic(Order, SynchScope);
19041 AI->replaceAllUsesWith(Loaded);
19042 AI->eraseFromParent();
19046 static SDValue LowerATOMIC_FENCE(SDValue Op, const X86Subtarget *Subtarget,
19047 SelectionDAG &DAG) {
19049 AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>(
19050 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue());
19051 SynchronizationScope FenceScope = static_cast<SynchronizationScope>(
19052 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
19054 // The only fence that needs an instruction is a sequentially-consistent
19055 // cross-thread fence.
19056 if (FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread) {
19057 if (hasMFENCE(*Subtarget))
19058 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
19060 SDValue Chain = Op.getOperand(0);
19061 SDValue Zero = DAG.getConstant(0, dl, MVT::i32);
19063 DAG.getRegister(X86::ESP, MVT::i32), // Base
19064 DAG.getTargetConstant(1, dl, MVT::i8), // Scale
19065 DAG.getRegister(0, MVT::i32), // Index
19066 DAG.getTargetConstant(0, dl, MVT::i32), // Disp
19067 DAG.getRegister(0, MVT::i32), // Segment.
19071 SDNode *Res = DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops);
19072 return SDValue(Res, 0);
19075 // MEMBARRIER is a compiler barrier; it codegens to a no-op.
19076 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
19079 static SDValue LowerCMP_SWAP(SDValue Op, const X86Subtarget *Subtarget,
19080 SelectionDAG &DAG) {
19081 MVT T = Op.getSimpleValueType();
19085 switch(T.SimpleTy) {
19086 default: llvm_unreachable("Invalid value type!");
19087 case MVT::i8: Reg = X86::AL; size = 1; break;
19088 case MVT::i16: Reg = X86::AX; size = 2; break;
19089 case MVT::i32: Reg = X86::EAX; size = 4; break;
19091 assert(Subtarget->is64Bit() && "Node not type legal!");
19092 Reg = X86::RAX; size = 8;
19095 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg,
19096 Op.getOperand(2), SDValue());
19097 SDValue Ops[] = { cpIn.getValue(0),
19100 DAG.getTargetConstant(size, DL, MVT::i8),
19101 cpIn.getValue(1) };
19102 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
19103 MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand();
19104 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys,
19108 DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1));
19109 SDValue EFLAGS = DAG.getCopyFromReg(cpOut.getValue(1), DL, X86::EFLAGS,
19110 MVT::i32, cpOut.getValue(2));
19111 SDValue Success = DAG.getNode(X86ISD::SETCC, DL, Op->getValueType(1),
19112 DAG.getConstant(X86::COND_E, DL, MVT::i8),
19115 DAG.ReplaceAllUsesOfValueWith(Op.getValue(0), cpOut);
19116 DAG.ReplaceAllUsesOfValueWith(Op.getValue(1), Success);
19117 DAG.ReplaceAllUsesOfValueWith(Op.getValue(2), EFLAGS.getValue(1));
19121 static SDValue LowerBITCAST(SDValue Op, const X86Subtarget *Subtarget,
19122 SelectionDAG &DAG) {
19123 MVT SrcVT = Op.getOperand(0).getSimpleValueType();
19124 MVT DstVT = Op.getSimpleValueType();
19126 if (SrcVT == MVT::v2i32 || SrcVT == MVT::v4i16 || SrcVT == MVT::v8i8) {
19127 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
19128 if (DstVT != MVT::f64)
19129 // This conversion needs to be expanded.
19132 SDValue InVec = Op->getOperand(0);
19134 unsigned NumElts = SrcVT.getVectorNumElements();
19135 MVT SVT = SrcVT.getVectorElementType();
19137 // Widen the vector in input in the case of MVT::v2i32.
19138 // Example: from MVT::v2i32 to MVT::v4i32.
19139 SmallVector<SDValue, 16> Elts;
19140 for (unsigned i = 0, e = NumElts; i != e; ++i)
19141 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT, InVec,
19142 DAG.getIntPtrConstant(i, dl)));
19144 // Explicitly mark the extra elements as Undef.
19145 Elts.append(NumElts, DAG.getUNDEF(SVT));
19147 EVT NewVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
19148 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Elts);
19149 SDValue ToV2F64 = DAG.getBitcast(MVT::v2f64, BV);
19150 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, ToV2F64,
19151 DAG.getIntPtrConstant(0, dl));
19154 assert(Subtarget->is64Bit() && !Subtarget->hasSSE2() &&
19155 Subtarget->hasMMX() && "Unexpected custom BITCAST");
19156 assert((DstVT == MVT::i64 ||
19157 (DstVT.isVector() && DstVT.getSizeInBits()==64)) &&
19158 "Unexpected custom BITCAST");
19159 // i64 <=> MMX conversions are Legal.
19160 if (SrcVT==MVT::i64 && DstVT.isVector())
19162 if (DstVT==MVT::i64 && SrcVT.isVector())
19164 // MMX <=> MMX conversions are Legal.
19165 if (SrcVT.isVector() && DstVT.isVector())
19167 // All other conversions need to be expanded.
19171 /// Compute the horizontal sum of bytes in V for the elements of VT.
19173 /// Requires V to be a byte vector and VT to be an integer vector type with
19174 /// wider elements than V's type. The width of the elements of VT determines
19175 /// how many bytes of V are summed horizontally to produce each element of the
19177 static SDValue LowerHorizontalByteSum(SDValue V, MVT VT,
19178 const X86Subtarget *Subtarget,
19179 SelectionDAG &DAG) {
19181 MVT ByteVecVT = V.getSimpleValueType();
19182 MVT EltVT = VT.getVectorElementType();
19183 int NumElts = VT.getVectorNumElements();
19184 assert(ByteVecVT.getVectorElementType() == MVT::i8 &&
19185 "Expected value to have byte element type.");
19186 assert(EltVT != MVT::i8 &&
19187 "Horizontal byte sum only makes sense for wider elements!");
19188 unsigned VecSize = VT.getSizeInBits();
19189 assert(ByteVecVT.getSizeInBits() == VecSize && "Cannot change vector size!");
19191 // PSADBW instruction horizontally add all bytes and leave the result in i64
19192 // chunks, thus directly computes the pop count for v2i64 and v4i64.
19193 if (EltVT == MVT::i64) {
19194 SDValue Zeros = getZeroVector(ByteVecVT, Subtarget, DAG, DL);
19195 V = DAG.getNode(X86ISD::PSADBW, DL, ByteVecVT, V, Zeros);
19196 return DAG.getBitcast(VT, V);
19199 if (EltVT == MVT::i32) {
19200 // We unpack the low half and high half into i32s interleaved with zeros so
19201 // that we can use PSADBW to horizontally sum them. The most useful part of
19202 // this is that it lines up the results of two PSADBW instructions to be
19203 // two v2i64 vectors which concatenated are the 4 population counts. We can
19204 // then use PACKUSWB to shrink and concatenate them into a v4i32 again.
19205 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, DL);
19206 SDValue Low = DAG.getNode(X86ISD::UNPCKL, DL, VT, V, Zeros);
19207 SDValue High = DAG.getNode(X86ISD::UNPCKH, DL, VT, V, Zeros);
19209 // Do the horizontal sums into two v2i64s.
19210 Zeros = getZeroVector(ByteVecVT, Subtarget, DAG, DL);
19211 Low = DAG.getNode(X86ISD::PSADBW, DL, ByteVecVT,
19212 DAG.getBitcast(ByteVecVT, Low), Zeros);
19213 High = DAG.getNode(X86ISD::PSADBW, DL, ByteVecVT,
19214 DAG.getBitcast(ByteVecVT, High), Zeros);
19216 // Merge them together.
19217 MVT ShortVecVT = MVT::getVectorVT(MVT::i16, VecSize / 16);
19218 V = DAG.getNode(X86ISD::PACKUS, DL, ByteVecVT,
19219 DAG.getBitcast(ShortVecVT, Low),
19220 DAG.getBitcast(ShortVecVT, High));
19222 return DAG.getBitcast(VT, V);
19225 // The only element type left is i16.
19226 assert(EltVT == MVT::i16 && "Unknown how to handle type");
19228 // To obtain pop count for each i16 element starting from the pop count for
19229 // i8 elements, shift the i16s left by 8, sum as i8s, and then shift as i16s
19230 // right by 8. It is important to shift as i16s as i8 vector shift isn't
19231 // directly supported.
19232 SmallVector<SDValue, 16> Shifters(NumElts, DAG.getConstant(8, DL, EltVT));
19233 SDValue Shifter = DAG.getNode(ISD::BUILD_VECTOR, DL, VT, Shifters);
19234 SDValue Shl = DAG.getNode(ISD::SHL, DL, VT, DAG.getBitcast(VT, V), Shifter);
19235 V = DAG.getNode(ISD::ADD, DL, ByteVecVT, DAG.getBitcast(ByteVecVT, Shl),
19236 DAG.getBitcast(ByteVecVT, V));
19237 return DAG.getNode(ISD::SRL, DL, VT, DAG.getBitcast(VT, V), Shifter);
19240 static SDValue LowerVectorCTPOPInRegLUT(SDValue Op, SDLoc DL,
19241 const X86Subtarget *Subtarget,
19242 SelectionDAG &DAG) {
19243 MVT VT = Op.getSimpleValueType();
19244 MVT EltVT = VT.getVectorElementType();
19245 unsigned VecSize = VT.getSizeInBits();
19247 // Implement a lookup table in register by using an algorithm based on:
19248 // http://wm.ite.pl/articles/sse-popcount.html
19250 // The general idea is that every lower byte nibble in the input vector is an
19251 // index into a in-register pre-computed pop count table. We then split up the
19252 // input vector in two new ones: (1) a vector with only the shifted-right
19253 // higher nibbles for each byte and (2) a vector with the lower nibbles (and
19254 // masked out higher ones) for each byte. PSHUB is used separately with both
19255 // to index the in-register table. Next, both are added and the result is a
19256 // i8 vector where each element contains the pop count for input byte.
19258 // To obtain the pop count for elements != i8, we follow up with the same
19259 // approach and use additional tricks as described below.
19261 const int LUT[16] = {/* 0 */ 0, /* 1 */ 1, /* 2 */ 1, /* 3 */ 2,
19262 /* 4 */ 1, /* 5 */ 2, /* 6 */ 2, /* 7 */ 3,
19263 /* 8 */ 1, /* 9 */ 2, /* a */ 2, /* b */ 3,
19264 /* c */ 2, /* d */ 3, /* e */ 3, /* f */ 4};
19266 int NumByteElts = VecSize / 8;
19267 MVT ByteVecVT = MVT::getVectorVT(MVT::i8, NumByteElts);
19268 SDValue In = DAG.getBitcast(ByteVecVT, Op);
19269 SmallVector<SDValue, 16> LUTVec;
19270 for (int i = 0; i < NumByteElts; ++i)
19271 LUTVec.push_back(DAG.getConstant(LUT[i % 16], DL, MVT::i8));
19272 SDValue InRegLUT = DAG.getNode(ISD::BUILD_VECTOR, DL, ByteVecVT, LUTVec);
19273 SmallVector<SDValue, 16> Mask0F(NumByteElts,
19274 DAG.getConstant(0x0F, DL, MVT::i8));
19275 SDValue M0F = DAG.getNode(ISD::BUILD_VECTOR, DL, ByteVecVT, Mask0F);
19278 SmallVector<SDValue, 16> Four(NumByteElts, DAG.getConstant(4, DL, MVT::i8));
19279 SDValue FourV = DAG.getNode(ISD::BUILD_VECTOR, DL, ByteVecVT, Four);
19280 SDValue HighNibbles = DAG.getNode(ISD::SRL, DL, ByteVecVT, In, FourV);
19283 SDValue LowNibbles = DAG.getNode(ISD::AND, DL, ByteVecVT, In, M0F);
19285 // The input vector is used as the shuffle mask that index elements into the
19286 // LUT. After counting low and high nibbles, add the vector to obtain the
19287 // final pop count per i8 element.
19288 SDValue HighPopCnt =
19289 DAG.getNode(X86ISD::PSHUFB, DL, ByteVecVT, InRegLUT, HighNibbles);
19290 SDValue LowPopCnt =
19291 DAG.getNode(X86ISD::PSHUFB, DL, ByteVecVT, InRegLUT, LowNibbles);
19292 SDValue PopCnt = DAG.getNode(ISD::ADD, DL, ByteVecVT, HighPopCnt, LowPopCnt);
19294 if (EltVT == MVT::i8)
19297 return LowerHorizontalByteSum(PopCnt, VT, Subtarget, DAG);
19300 static SDValue LowerVectorCTPOPBitmath(SDValue Op, SDLoc DL,
19301 const X86Subtarget *Subtarget,
19302 SelectionDAG &DAG) {
19303 MVT VT = Op.getSimpleValueType();
19304 assert(VT.is128BitVector() &&
19305 "Only 128-bit vector bitmath lowering supported.");
19307 int VecSize = VT.getSizeInBits();
19308 MVT EltVT = VT.getVectorElementType();
19309 int Len = EltVT.getSizeInBits();
19311 // This is the vectorized version of the "best" algorithm from
19312 // http://graphics.stanford.edu/~seander/bithacks.html#CountBitsSetParallel
19313 // with a minor tweak to use a series of adds + shifts instead of vector
19314 // multiplications. Implemented for all integer vector types. We only use
19315 // this when we don't have SSSE3 which allows a LUT-based lowering that is
19316 // much faster, even faster than using native popcnt instructions.
19318 auto GetShift = [&](unsigned OpCode, SDValue V, int Shifter) {
19319 MVT VT = V.getSimpleValueType();
19320 SmallVector<SDValue, 32> Shifters(
19321 VT.getVectorNumElements(),
19322 DAG.getConstant(Shifter, DL, VT.getVectorElementType()));
19323 return DAG.getNode(OpCode, DL, VT, V,
19324 DAG.getNode(ISD::BUILD_VECTOR, DL, VT, Shifters));
19326 auto GetMask = [&](SDValue V, APInt Mask) {
19327 MVT VT = V.getSimpleValueType();
19328 SmallVector<SDValue, 32> Masks(
19329 VT.getVectorNumElements(),
19330 DAG.getConstant(Mask, DL, VT.getVectorElementType()));
19331 return DAG.getNode(ISD::AND, DL, VT, V,
19332 DAG.getNode(ISD::BUILD_VECTOR, DL, VT, Masks));
19335 // We don't want to incur the implicit masks required to SRL vNi8 vectors on
19336 // x86, so set the SRL type to have elements at least i16 wide. This is
19337 // correct because all of our SRLs are followed immediately by a mask anyways
19338 // that handles any bits that sneak into the high bits of the byte elements.
19339 MVT SrlVT = Len > 8 ? VT : MVT::getVectorVT(MVT::i16, VecSize / 16);
19343 // v = v - ((v >> 1) & 0x55555555...)
19345 DAG.getBitcast(VT, GetShift(ISD::SRL, DAG.getBitcast(SrlVT, V), 1));
19346 SDValue And = GetMask(Srl, APInt::getSplat(Len, APInt(8, 0x55)));
19347 V = DAG.getNode(ISD::SUB, DL, VT, V, And);
19349 // v = (v & 0x33333333...) + ((v >> 2) & 0x33333333...)
19350 SDValue AndLHS = GetMask(V, APInt::getSplat(Len, APInt(8, 0x33)));
19351 Srl = DAG.getBitcast(VT, GetShift(ISD::SRL, DAG.getBitcast(SrlVT, V), 2));
19352 SDValue AndRHS = GetMask(Srl, APInt::getSplat(Len, APInt(8, 0x33)));
19353 V = DAG.getNode(ISD::ADD, DL, VT, AndLHS, AndRHS);
19355 // v = (v + (v >> 4)) & 0x0F0F0F0F...
19356 Srl = DAG.getBitcast(VT, GetShift(ISD::SRL, DAG.getBitcast(SrlVT, V), 4));
19357 SDValue Add = DAG.getNode(ISD::ADD, DL, VT, V, Srl);
19358 V = GetMask(Add, APInt::getSplat(Len, APInt(8, 0x0F)));
19360 // At this point, V contains the byte-wise population count, and we are
19361 // merely doing a horizontal sum if necessary to get the wider element
19363 if (EltVT == MVT::i8)
19366 return LowerHorizontalByteSum(
19367 DAG.getBitcast(MVT::getVectorVT(MVT::i8, VecSize / 8), V), VT, Subtarget,
19371 static SDValue LowerVectorCTPOP(SDValue Op, const X86Subtarget *Subtarget,
19372 SelectionDAG &DAG) {
19373 MVT VT = Op.getSimpleValueType();
19374 // FIXME: Need to add AVX-512 support here!
19375 assert((VT.is256BitVector() || VT.is128BitVector()) &&
19376 "Unknown CTPOP type to handle");
19377 SDLoc DL(Op.getNode());
19378 SDValue Op0 = Op.getOperand(0);
19380 if (!Subtarget->hasSSSE3()) {
19381 // We can't use the fast LUT approach, so fall back on vectorized bitmath.
19382 assert(VT.is128BitVector() && "Only 128-bit vectors supported in SSE!");
19383 return LowerVectorCTPOPBitmath(Op0, DL, Subtarget, DAG);
19386 if (VT.is256BitVector() && !Subtarget->hasInt256()) {
19387 unsigned NumElems = VT.getVectorNumElements();
19389 // Extract each 128-bit vector, compute pop count and concat the result.
19390 SDValue LHS = Extract128BitVector(Op0, 0, DAG, DL);
19391 SDValue RHS = Extract128BitVector(Op0, NumElems/2, DAG, DL);
19393 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT,
19394 LowerVectorCTPOPInRegLUT(LHS, DL, Subtarget, DAG),
19395 LowerVectorCTPOPInRegLUT(RHS, DL, Subtarget, DAG));
19398 return LowerVectorCTPOPInRegLUT(Op0, DL, Subtarget, DAG);
19401 static SDValue LowerCTPOP(SDValue Op, const X86Subtarget *Subtarget,
19402 SelectionDAG &DAG) {
19403 assert(Op.getSimpleValueType().isVector() &&
19404 "We only do custom lowering for vector population count.");
19405 return LowerVectorCTPOP(Op, Subtarget, DAG);
19408 static SDValue LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) {
19409 SDNode *Node = Op.getNode();
19411 EVT T = Node->getValueType(0);
19412 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
19413 DAG.getConstant(0, dl, T), Node->getOperand(2));
19414 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
19415 cast<AtomicSDNode>(Node)->getMemoryVT(),
19416 Node->getOperand(0),
19417 Node->getOperand(1), negOp,
19418 cast<AtomicSDNode>(Node)->getMemOperand(),
19419 cast<AtomicSDNode>(Node)->getOrdering(),
19420 cast<AtomicSDNode>(Node)->getSynchScope());
19423 static SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) {
19424 SDNode *Node = Op.getNode();
19426 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
19428 // Convert seq_cst store -> xchg
19429 // Convert wide store -> swap (-> cmpxchg8b/cmpxchg16b)
19430 // FIXME: On 32-bit, store -> fist or movq would be more efficient
19431 // (The only way to get a 16-byte store is cmpxchg16b)
19432 // FIXME: 16-byte ATOMIC_SWAP isn't actually hooked up at the moment.
19433 if (cast<AtomicSDNode>(Node)->getOrdering() == SequentiallyConsistent ||
19434 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
19435 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
19436 cast<AtomicSDNode>(Node)->getMemoryVT(),
19437 Node->getOperand(0),
19438 Node->getOperand(1), Node->getOperand(2),
19439 cast<AtomicSDNode>(Node)->getMemOperand(),
19440 cast<AtomicSDNode>(Node)->getOrdering(),
19441 cast<AtomicSDNode>(Node)->getSynchScope());
19442 return Swap.getValue(1);
19444 // Other atomic stores have a simple pattern.
19448 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
19449 MVT VT = Op.getNode()->getSimpleValueType(0);
19451 // Let legalize expand this if it isn't a legal type yet.
19452 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
19455 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
19458 bool ExtraOp = false;
19459 switch (Op.getOpcode()) {
19460 default: llvm_unreachable("Invalid code");
19461 case ISD::ADDC: Opc = X86ISD::ADD; break;
19462 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break;
19463 case ISD::SUBC: Opc = X86ISD::SUB; break;
19464 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break;
19468 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
19470 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
19471 Op.getOperand(1), Op.getOperand(2));
19474 static SDValue LowerFSINCOS(SDValue Op, const X86Subtarget *Subtarget,
19475 SelectionDAG &DAG) {
19476 assert(Subtarget->isTargetDarwin() && Subtarget->is64Bit());
19478 // For MacOSX, we want to call an alternative entry point: __sincos_stret,
19479 // which returns the values as { float, float } (in XMM0) or
19480 // { double, double } (which is returned in XMM0, XMM1).
19482 SDValue Arg = Op.getOperand(0);
19483 EVT ArgVT = Arg.getValueType();
19484 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
19486 TargetLowering::ArgListTy Args;
19487 TargetLowering::ArgListEntry Entry;
19491 Entry.isSExt = false;
19492 Entry.isZExt = false;
19493 Args.push_back(Entry);
19495 bool isF64 = ArgVT == MVT::f64;
19496 // Only optimize x86_64 for now. i386 is a bit messy. For f32,
19497 // the small struct {f32, f32} is returned in (eax, edx). For f64,
19498 // the results are returned via SRet in memory.
19499 const char *LibcallName = isF64 ? "__sincos_stret" : "__sincosf_stret";
19500 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
19502 DAG.getExternalSymbol(LibcallName, TLI.getPointerTy(DAG.getDataLayout()));
19504 Type *RetTy = isF64
19505 ? (Type*)StructType::get(ArgTy, ArgTy, nullptr)
19506 : (Type*)VectorType::get(ArgTy, 4);
19508 TargetLowering::CallLoweringInfo CLI(DAG);
19509 CLI.setDebugLoc(dl).setChain(DAG.getEntryNode())
19510 .setCallee(CallingConv::C, RetTy, Callee, std::move(Args), 0);
19512 std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI);
19515 // Returned in xmm0 and xmm1.
19516 return CallResult.first;
19518 // Returned in bits 0:31 and 32:64 xmm0.
19519 SDValue SinVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
19520 CallResult.first, DAG.getIntPtrConstant(0, dl));
19521 SDValue CosVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
19522 CallResult.first, DAG.getIntPtrConstant(1, dl));
19523 SDVTList Tys = DAG.getVTList(ArgVT, ArgVT);
19524 return DAG.getNode(ISD::MERGE_VALUES, dl, Tys, SinVal, CosVal);
19527 static SDValue LowerMSCATTER(SDValue Op, const X86Subtarget *Subtarget,
19528 SelectionDAG &DAG) {
19529 assert(Subtarget->hasAVX512() &&
19530 "MGATHER/MSCATTER are supported on AVX-512 arch only");
19532 MaskedScatterSDNode *N = cast<MaskedScatterSDNode>(Op.getNode());
19533 MVT VT = N->getValue().getSimpleValueType();
19534 assert(VT.getScalarSizeInBits() >= 32 && "Unsupported scatter op");
19537 // X86 scatter kills mask register, so its type should be added to
19538 // the list of return values
19539 if (N->getNumValues() == 1) {
19540 SDValue Index = N->getIndex();
19541 if (!Subtarget->hasVLX() && !VT.is512BitVector() &&
19542 !Index.getSimpleValueType().is512BitVector())
19543 Index = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i64, Index);
19545 SDVTList VTs = DAG.getVTList(N->getMask().getValueType(), MVT::Other);
19546 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), N->getOperand(2),
19547 N->getOperand(3), Index };
19549 SDValue NewScatter = DAG.getMaskedScatter(VTs, VT, dl, Ops, N->getMemOperand());
19550 DAG.ReplaceAllUsesWith(Op, SDValue(NewScatter.getNode(), 1));
19551 return SDValue(NewScatter.getNode(), 0);
19556 static SDValue LowerMGATHER(SDValue Op, const X86Subtarget *Subtarget,
19557 SelectionDAG &DAG) {
19558 assert(Subtarget->hasAVX512() &&
19559 "MGATHER/MSCATTER are supported on AVX-512 arch only");
19561 MaskedGatherSDNode *N = cast<MaskedGatherSDNode>(Op.getNode());
19562 MVT VT = Op.getSimpleValueType();
19563 assert(VT.getScalarSizeInBits() >= 32 && "Unsupported gather op");
19566 SDValue Index = N->getIndex();
19567 if (!Subtarget->hasVLX() && !VT.is512BitVector() &&
19568 !Index.getSimpleValueType().is512BitVector()) {
19569 Index = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i64, Index);
19570 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), N->getOperand(2),
19571 N->getOperand(3), Index };
19572 DAG.UpdateNodeOperands(N, Ops);
19577 SDValue X86TargetLowering::LowerGC_TRANSITION_START(SDValue Op,
19578 SelectionDAG &DAG) const {
19579 // TODO: Eventually, the lowering of these nodes should be informed by or
19580 // deferred to the GC strategy for the function in which they appear. For
19581 // now, however, they must be lowered to something. Since they are logically
19582 // no-ops in the case of a null GC strategy (or a GC strategy which does not
19583 // require special handling for these nodes), lower them as literal NOOPs for
19585 SmallVector<SDValue, 2> Ops;
19587 Ops.push_back(Op.getOperand(0));
19588 if (Op->getGluedNode())
19589 Ops.push_back(Op->getOperand(Op->getNumOperands() - 1));
19592 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
19593 SDValue NOOP(DAG.getMachineNode(X86::NOOP, SDLoc(Op), VTs, Ops), 0);
19598 SDValue X86TargetLowering::LowerGC_TRANSITION_END(SDValue Op,
19599 SelectionDAG &DAG) const {
19600 // TODO: Eventually, the lowering of these nodes should be informed by or
19601 // deferred to the GC strategy for the function in which they appear. For
19602 // now, however, they must be lowered to something. Since they are logically
19603 // no-ops in the case of a null GC strategy (or a GC strategy which does not
19604 // require special handling for these nodes), lower them as literal NOOPs for
19606 SmallVector<SDValue, 2> Ops;
19608 Ops.push_back(Op.getOperand(0));
19609 if (Op->getGluedNode())
19610 Ops.push_back(Op->getOperand(Op->getNumOperands() - 1));
19613 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
19614 SDValue NOOP(DAG.getMachineNode(X86::NOOP, SDLoc(Op), VTs, Ops), 0);
19619 /// LowerOperation - Provide custom lowering hooks for some operations.
19621 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
19622 switch (Op.getOpcode()) {
19623 default: llvm_unreachable("Should not custom lower this!");
19624 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, Subtarget, DAG);
19625 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS:
19626 return LowerCMP_SWAP(Op, Subtarget, DAG);
19627 case ISD::CTPOP: return LowerCTPOP(Op, Subtarget, DAG);
19628 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
19629 case ISD::ATOMIC_STORE: return LowerATOMIC_STORE(Op,DAG);
19630 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
19631 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, Subtarget, DAG);
19632 case ISD::VECTOR_SHUFFLE: return lowerVectorShuffle(Op, Subtarget, DAG);
19633 case ISD::VSELECT: return LowerVSELECT(Op, DAG);
19634 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
19635 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
19636 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op,Subtarget,DAG);
19637 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, Subtarget,DAG);
19638 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
19639 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
19640 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
19641 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
19642 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
19643 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
19644 case ISD::SHL_PARTS:
19645 case ISD::SRA_PARTS:
19646 case ISD::SRL_PARTS: return LowerShiftParts(Op, DAG);
19647 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
19648 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
19649 case ISD::TRUNCATE: return LowerTRUNCATE(Op, DAG);
19650 case ISD::ZERO_EXTEND: return LowerZERO_EXTEND(Op, Subtarget, DAG);
19651 case ISD::SIGN_EXTEND: return LowerSIGN_EXTEND(Op, Subtarget, DAG);
19652 case ISD::ANY_EXTEND: return LowerANY_EXTEND(Op, Subtarget, DAG);
19653 case ISD::SIGN_EXTEND_VECTOR_INREG:
19654 return LowerSIGN_EXTEND_VECTOR_INREG(Op, Subtarget, DAG);
19655 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
19656 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
19657 case ISD::FP_EXTEND: return LowerFP_EXTEND(Op, DAG);
19658 case ISD::LOAD: return LowerExtendedLoad(Op, Subtarget, DAG);
19660 case ISD::FNEG: return LowerFABSorFNEG(Op, DAG);
19661 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
19662 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG);
19663 case ISD::SETCC: return LowerSETCC(Op, DAG);
19664 case ISD::SELECT: return LowerSELECT(Op, DAG);
19665 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
19666 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
19667 case ISD::VASTART: return LowerVASTART(Op, DAG);
19668 case ISD::VAARG: return LowerVAARG(Op, DAG);
19669 case ISD::VACOPY: return LowerVACOPY(Op, Subtarget, DAG);
19670 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, Subtarget, DAG);
19671 case ISD::INTRINSIC_VOID:
19672 case ISD::INTRINSIC_W_CHAIN: return LowerINTRINSIC_W_CHAIN(Op, Subtarget, DAG);
19673 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
19674 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
19675 case ISD::FRAME_TO_ARGS_OFFSET:
19676 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
19677 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
19678 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
19679 case ISD::EH_SJLJ_SETJMP: return lowerEH_SJLJ_SETJMP(Op, DAG);
19680 case ISD::EH_SJLJ_LONGJMP: return lowerEH_SJLJ_LONGJMP(Op, DAG);
19681 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
19682 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
19683 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
19684 case ISD::CTLZ: return LowerCTLZ(Op, Subtarget, DAG);
19685 case ISD::CTLZ_ZERO_UNDEF: return LowerCTLZ_ZERO_UNDEF(Op, Subtarget, DAG);
19687 case ISD::CTTZ_ZERO_UNDEF: return LowerCTTZ(Op, DAG);
19688 case ISD::MUL: return LowerMUL(Op, Subtarget, DAG);
19689 case ISD::UMUL_LOHI:
19690 case ISD::SMUL_LOHI: return LowerMUL_LOHI(Op, Subtarget, DAG);
19691 case ISD::ROTL: return LowerRotate(Op, Subtarget, DAG);
19694 case ISD::SHL: return LowerShift(Op, Subtarget, DAG);
19700 case ISD::UMULO: return LowerXALUO(Op, DAG);
19701 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, Subtarget,DAG);
19702 case ISD::BITCAST: return LowerBITCAST(Op, Subtarget, DAG);
19706 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
19707 case ISD::ADD: return LowerADD(Op, DAG);
19708 case ISD::SUB: return LowerSUB(Op, DAG);
19712 case ISD::UMIN: return LowerMINMAX(Op, DAG);
19713 case ISD::FSINCOS: return LowerFSINCOS(Op, Subtarget, DAG);
19714 case ISD::MGATHER: return LowerMGATHER(Op, Subtarget, DAG);
19715 case ISD::MSCATTER: return LowerMSCATTER(Op, Subtarget, DAG);
19716 case ISD::GC_TRANSITION_START:
19717 return LowerGC_TRANSITION_START(Op, DAG);
19718 case ISD::GC_TRANSITION_END: return LowerGC_TRANSITION_END(Op, DAG);
19722 /// ReplaceNodeResults - Replace a node with an illegal result type
19723 /// with a new node built out of custom code.
19724 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
19725 SmallVectorImpl<SDValue>&Results,
19726 SelectionDAG &DAG) const {
19728 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
19729 switch (N->getOpcode()) {
19731 llvm_unreachable("Do not know how to custom type legalize this operation!");
19732 // We might have generated v2f32 FMIN/FMAX operations. Widen them to v4f32.
19733 case X86ISD::FMINC:
19735 case X86ISD::FMAXC:
19736 case X86ISD::FMAX: {
19737 EVT VT = N->getValueType(0);
19738 assert(VT == MVT::v2f32 && "Unexpected type (!= v2f32) on FMIN/FMAX.");
19739 SDValue UNDEF = DAG.getUNDEF(VT);
19740 SDValue LHS = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v4f32,
19741 N->getOperand(0), UNDEF);
19742 SDValue RHS = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v4f32,
19743 N->getOperand(1), UNDEF);
19744 Results.push_back(DAG.getNode(N->getOpcode(), dl, MVT::v4f32, LHS, RHS));
19747 case ISD::SIGN_EXTEND_INREG:
19752 // We don't want to expand or promote these.
19759 case ISD::UDIVREM: {
19760 SDValue V = LowerWin64_i128OP(SDValue(N,0), DAG);
19761 Results.push_back(V);
19764 case ISD::FP_TO_SINT:
19765 case ISD::FP_TO_UINT: {
19766 bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT;
19768 std::pair<SDValue,SDValue> Vals =
19769 FP_TO_INTHelper(SDValue(N, 0), DAG, IsSigned, /*IsReplace=*/ true);
19770 SDValue FIST = Vals.first, StackSlot = Vals.second;
19771 if (FIST.getNode()) {
19772 EVT VT = N->getValueType(0);
19773 // Return a load from the stack slot.
19774 if (StackSlot.getNode())
19775 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot,
19776 MachinePointerInfo(),
19777 false, false, false, 0));
19779 Results.push_back(FIST);
19783 case ISD::UINT_TO_FP: {
19784 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
19785 if (N->getOperand(0).getValueType() != MVT::v2i32 ||
19786 N->getValueType(0) != MVT::v2f32)
19788 SDValue ZExtIn = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v2i64,
19790 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL), dl,
19792 SDValue VBias = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2f64, Bias, Bias);
19793 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64, ZExtIn,
19794 DAG.getBitcast(MVT::v2i64, VBias));
19795 Or = DAG.getBitcast(MVT::v2f64, Or);
19796 // TODO: Are there any fast-math-flags to propagate here?
19797 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, Or, VBias);
19798 Results.push_back(DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, Sub));
19801 case ISD::FP_ROUND: {
19802 if (!TLI.isTypeLegal(N->getOperand(0).getValueType()))
19804 SDValue V = DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, N->getOperand(0));
19805 Results.push_back(V);
19808 case ISD::FP_EXTEND: {
19809 // Right now, only MVT::v2f32 has OperationAction for FP_EXTEND.
19810 // No other ValueType for FP_EXTEND should reach this point.
19811 assert(N->getValueType(0) == MVT::v2f32 &&
19812 "Do not know how to legalize this Node");
19815 case ISD::INTRINSIC_W_CHAIN: {
19816 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
19818 default : llvm_unreachable("Do not know how to custom type "
19819 "legalize this intrinsic operation!");
19820 case Intrinsic::x86_rdtsc:
19821 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
19823 case Intrinsic::x86_rdtscp:
19824 return getReadTimeStampCounter(N, dl, X86ISD::RDTSCP_DAG, DAG, Subtarget,
19826 case Intrinsic::x86_rdpmc:
19827 return getReadPerformanceCounter(N, dl, DAG, Subtarget, Results);
19830 case ISD::READCYCLECOUNTER: {
19831 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
19834 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS: {
19835 EVT T = N->getValueType(0);
19836 assert((T == MVT::i64 || T == MVT::i128) && "can only expand cmpxchg pair");
19837 bool Regs64bit = T == MVT::i128;
19838 MVT HalfT = Regs64bit ? MVT::i64 : MVT::i32;
19839 SDValue cpInL, cpInH;
19840 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
19841 DAG.getConstant(0, dl, HalfT));
19842 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
19843 DAG.getConstant(1, dl, HalfT));
19844 cpInL = DAG.getCopyToReg(N->getOperand(0), dl,
19845 Regs64bit ? X86::RAX : X86::EAX,
19847 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl,
19848 Regs64bit ? X86::RDX : X86::EDX,
19849 cpInH, cpInL.getValue(1));
19850 SDValue swapInL, swapInH;
19851 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
19852 DAG.getConstant(0, dl, HalfT));
19853 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
19854 DAG.getConstant(1, dl, HalfT));
19855 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl,
19856 Regs64bit ? X86::RBX : X86::EBX,
19857 swapInL, cpInH.getValue(1));
19858 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl,
19859 Regs64bit ? X86::RCX : X86::ECX,
19860 swapInH, swapInL.getValue(1));
19861 SDValue Ops[] = { swapInH.getValue(0),
19863 swapInH.getValue(1) };
19864 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
19865 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand();
19866 unsigned Opcode = Regs64bit ? X86ISD::LCMPXCHG16_DAG :
19867 X86ISD::LCMPXCHG8_DAG;
19868 SDValue Result = DAG.getMemIntrinsicNode(Opcode, dl, Tys, Ops, T, MMO);
19869 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl,
19870 Regs64bit ? X86::RAX : X86::EAX,
19871 HalfT, Result.getValue(1));
19872 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl,
19873 Regs64bit ? X86::RDX : X86::EDX,
19874 HalfT, cpOutL.getValue(2));
19875 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
19877 SDValue EFLAGS = DAG.getCopyFromReg(cpOutH.getValue(1), dl, X86::EFLAGS,
19878 MVT::i32, cpOutH.getValue(2));
19880 DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
19881 DAG.getConstant(X86::COND_E, dl, MVT::i8), EFLAGS);
19882 Success = DAG.getZExtOrTrunc(Success, dl, N->getValueType(1));
19884 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, T, OpsF));
19885 Results.push_back(Success);
19886 Results.push_back(EFLAGS.getValue(1));
19889 case ISD::ATOMIC_SWAP:
19890 case ISD::ATOMIC_LOAD_ADD:
19891 case ISD::ATOMIC_LOAD_SUB:
19892 case ISD::ATOMIC_LOAD_AND:
19893 case ISD::ATOMIC_LOAD_OR:
19894 case ISD::ATOMIC_LOAD_XOR:
19895 case ISD::ATOMIC_LOAD_NAND:
19896 case ISD::ATOMIC_LOAD_MIN:
19897 case ISD::ATOMIC_LOAD_MAX:
19898 case ISD::ATOMIC_LOAD_UMIN:
19899 case ISD::ATOMIC_LOAD_UMAX:
19900 case ISD::ATOMIC_LOAD: {
19901 // Delegate to generic TypeLegalization. Situations we can really handle
19902 // should have already been dealt with by AtomicExpandPass.cpp.
19905 case ISD::BITCAST: {
19906 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
19907 EVT DstVT = N->getValueType(0);
19908 EVT SrcVT = N->getOperand(0)->getValueType(0);
19910 if (SrcVT != MVT::f64 ||
19911 (DstVT != MVT::v2i32 && DstVT != MVT::v4i16 && DstVT != MVT::v8i8))
19914 unsigned NumElts = DstVT.getVectorNumElements();
19915 EVT SVT = DstVT.getVectorElementType();
19916 EVT WiderVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
19917 SDValue Expanded = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
19918 MVT::v2f64, N->getOperand(0));
19919 SDValue ToVecInt = DAG.getBitcast(WiderVT, Expanded);
19921 if (ExperimentalVectorWideningLegalization) {
19922 // If we are legalizing vectors by widening, we already have the desired
19923 // legal vector type, just return it.
19924 Results.push_back(ToVecInt);
19928 SmallVector<SDValue, 8> Elts;
19929 for (unsigned i = 0, e = NumElts; i != e; ++i)
19930 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT,
19931 ToVecInt, DAG.getIntPtrConstant(i, dl)));
19933 Results.push_back(DAG.getNode(ISD::BUILD_VECTOR, dl, DstVT, Elts));
19938 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
19939 switch ((X86ISD::NodeType)Opcode) {
19940 case X86ISD::FIRST_NUMBER: break;
19941 case X86ISD::BSF: return "X86ISD::BSF";
19942 case X86ISD::BSR: return "X86ISD::BSR";
19943 case X86ISD::SHLD: return "X86ISD::SHLD";
19944 case X86ISD::SHRD: return "X86ISD::SHRD";
19945 case X86ISD::FAND: return "X86ISD::FAND";
19946 case X86ISD::FANDN: return "X86ISD::FANDN";
19947 case X86ISD::FOR: return "X86ISD::FOR";
19948 case X86ISD::FXOR: return "X86ISD::FXOR";
19949 case X86ISD::FILD: return "X86ISD::FILD";
19950 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
19951 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
19952 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
19953 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
19954 case X86ISD::FLD: return "X86ISD::FLD";
19955 case X86ISD::FST: return "X86ISD::FST";
19956 case X86ISD::CALL: return "X86ISD::CALL";
19957 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
19958 case X86ISD::RDTSCP_DAG: return "X86ISD::RDTSCP_DAG";
19959 case X86ISD::RDPMC_DAG: return "X86ISD::RDPMC_DAG";
19960 case X86ISD::BT: return "X86ISD::BT";
19961 case X86ISD::CMP: return "X86ISD::CMP";
19962 case X86ISD::COMI: return "X86ISD::COMI";
19963 case X86ISD::UCOMI: return "X86ISD::UCOMI";
19964 case X86ISD::CMPM: return "X86ISD::CMPM";
19965 case X86ISD::CMPMU: return "X86ISD::CMPMU";
19966 case X86ISD::CMPM_RND: return "X86ISD::CMPM_RND";
19967 case X86ISD::SETCC: return "X86ISD::SETCC";
19968 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY";
19969 case X86ISD::FSETCC: return "X86ISD::FSETCC";
19970 case X86ISD::FGETSIGNx86: return "X86ISD::FGETSIGNx86";
19971 case X86ISD::CMOV: return "X86ISD::CMOV";
19972 case X86ISD::BRCOND: return "X86ISD::BRCOND";
19973 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
19974 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
19975 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
19976 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
19977 case X86ISD::Wrapper: return "X86ISD::Wrapper";
19978 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
19979 case X86ISD::MOVDQ2Q: return "X86ISD::MOVDQ2Q";
19980 case X86ISD::MMX_MOVD2W: return "X86ISD::MMX_MOVD2W";
19981 case X86ISD::MMX_MOVW2D: return "X86ISD::MMX_MOVW2D";
19982 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
19983 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
19984 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
19985 case X86ISD::PINSRB: return "X86ISD::PINSRB";
19986 case X86ISD::PINSRW: return "X86ISD::PINSRW";
19987 case X86ISD::MMX_PINSRW: return "X86ISD::MMX_PINSRW";
19988 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
19989 case X86ISD::ANDNP: return "X86ISD::ANDNP";
19990 case X86ISD::PSIGN: return "X86ISD::PSIGN";
19991 case X86ISD::BLENDI: return "X86ISD::BLENDI";
19992 case X86ISD::SHRUNKBLEND: return "X86ISD::SHRUNKBLEND";
19993 case X86ISD::ADDUS: return "X86ISD::ADDUS";
19994 case X86ISD::SUBUS: return "X86ISD::SUBUS";
19995 case X86ISD::HADD: return "X86ISD::HADD";
19996 case X86ISD::HSUB: return "X86ISD::HSUB";
19997 case X86ISD::FHADD: return "X86ISD::FHADD";
19998 case X86ISD::FHSUB: return "X86ISD::FHSUB";
19999 case X86ISD::ABS: return "X86ISD::ABS";
20000 case X86ISD::CONFLICT: return "X86ISD::CONFLICT";
20001 case X86ISD::FMAX: return "X86ISD::FMAX";
20002 case X86ISD::FMAX_RND: return "X86ISD::FMAX_RND";
20003 case X86ISD::FMIN: return "X86ISD::FMIN";
20004 case X86ISD::FMIN_RND: return "X86ISD::FMIN_RND";
20005 case X86ISD::FMAXC: return "X86ISD::FMAXC";
20006 case X86ISD::FMINC: return "X86ISD::FMINC";
20007 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
20008 case X86ISD::FRCP: return "X86ISD::FRCP";
20009 case X86ISD::EXTRQI: return "X86ISD::EXTRQI";
20010 case X86ISD::INSERTQI: return "X86ISD::INSERTQI";
20011 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
20012 case X86ISD::TLSBASEADDR: return "X86ISD::TLSBASEADDR";
20013 case X86ISD::TLSCALL: return "X86ISD::TLSCALL";
20014 case X86ISD::EH_SJLJ_SETJMP: return "X86ISD::EH_SJLJ_SETJMP";
20015 case X86ISD::EH_SJLJ_LONGJMP: return "X86ISD::EH_SJLJ_LONGJMP";
20016 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
20017 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
20018 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
20019 case X86ISD::FNSTSW16r: return "X86ISD::FNSTSW16r";
20020 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
20021 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
20022 case X86ISD::LCMPXCHG16_DAG: return "X86ISD::LCMPXCHG16_DAG";
20023 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
20024 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
20025 case X86ISD::VZEXT: return "X86ISD::VZEXT";
20026 case X86ISD::VSEXT: return "X86ISD::VSEXT";
20027 case X86ISD::VTRUNC: return "X86ISD::VTRUNC";
20028 case X86ISD::VTRUNCS: return "X86ISD::VTRUNCS";
20029 case X86ISD::VTRUNCUS: return "X86ISD::VTRUNCUS";
20030 case X86ISD::VINSERT: return "X86ISD::VINSERT";
20031 case X86ISD::VFPEXT: return "X86ISD::VFPEXT";
20032 case X86ISD::VFPROUND: return "X86ISD::VFPROUND";
20033 case X86ISD::CVTDQ2PD: return "X86ISD::CVTDQ2PD";
20034 case X86ISD::CVTUDQ2PD: return "X86ISD::CVTUDQ2PD";
20035 case X86ISD::VSHLDQ: return "X86ISD::VSHLDQ";
20036 case X86ISD::VSRLDQ: return "X86ISD::VSRLDQ";
20037 case X86ISD::VSHL: return "X86ISD::VSHL";
20038 case X86ISD::VSRL: return "X86ISD::VSRL";
20039 case X86ISD::VSRA: return "X86ISD::VSRA";
20040 case X86ISD::VSHLI: return "X86ISD::VSHLI";
20041 case X86ISD::VSRLI: return "X86ISD::VSRLI";
20042 case X86ISD::VSRAI: return "X86ISD::VSRAI";
20043 case X86ISD::CMPP: return "X86ISD::CMPP";
20044 case X86ISD::PCMPEQ: return "X86ISD::PCMPEQ";
20045 case X86ISD::PCMPGT: return "X86ISD::PCMPGT";
20046 case X86ISD::PCMPEQM: return "X86ISD::PCMPEQM";
20047 case X86ISD::PCMPGTM: return "X86ISD::PCMPGTM";
20048 case X86ISD::ADD: return "X86ISD::ADD";
20049 case X86ISD::SUB: return "X86ISD::SUB";
20050 case X86ISD::ADC: return "X86ISD::ADC";
20051 case X86ISD::SBB: return "X86ISD::SBB";
20052 case X86ISD::SMUL: return "X86ISD::SMUL";
20053 case X86ISD::UMUL: return "X86ISD::UMUL";
20054 case X86ISD::SMUL8: return "X86ISD::SMUL8";
20055 case X86ISD::UMUL8: return "X86ISD::UMUL8";
20056 case X86ISD::SDIVREM8_SEXT_HREG: return "X86ISD::SDIVREM8_SEXT_HREG";
20057 case X86ISD::UDIVREM8_ZEXT_HREG: return "X86ISD::UDIVREM8_ZEXT_HREG";
20058 case X86ISD::INC: return "X86ISD::INC";
20059 case X86ISD::DEC: return "X86ISD::DEC";
20060 case X86ISD::OR: return "X86ISD::OR";
20061 case X86ISD::XOR: return "X86ISD::XOR";
20062 case X86ISD::AND: return "X86ISD::AND";
20063 case X86ISD::BEXTR: return "X86ISD::BEXTR";
20064 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
20065 case X86ISD::PTEST: return "X86ISD::PTEST";
20066 case X86ISD::TESTP: return "X86ISD::TESTP";
20067 case X86ISD::TESTM: return "X86ISD::TESTM";
20068 case X86ISD::TESTNM: return "X86ISD::TESTNM";
20069 case X86ISD::KORTEST: return "X86ISD::KORTEST";
20070 case X86ISD::KTEST: return "X86ISD::KTEST";
20071 case X86ISD::PACKSS: return "X86ISD::PACKSS";
20072 case X86ISD::PACKUS: return "X86ISD::PACKUS";
20073 case X86ISD::PALIGNR: return "X86ISD::PALIGNR";
20074 case X86ISD::VALIGN: return "X86ISD::VALIGN";
20075 case X86ISD::PSHUFD: return "X86ISD::PSHUFD";
20076 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW";
20077 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW";
20078 case X86ISD::SHUFP: return "X86ISD::SHUFP";
20079 case X86ISD::SHUF128: return "X86ISD::SHUF128";
20080 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS";
20081 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD";
20082 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS";
20083 case X86ISD::MOVLPS: return "X86ISD::MOVLPS";
20084 case X86ISD::MOVLPD: return "X86ISD::MOVLPD";
20085 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP";
20086 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP";
20087 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP";
20088 case X86ISD::MOVSD: return "X86ISD::MOVSD";
20089 case X86ISD::MOVSS: return "X86ISD::MOVSS";
20090 case X86ISD::UNPCKL: return "X86ISD::UNPCKL";
20091 case X86ISD::UNPCKH: return "X86ISD::UNPCKH";
20092 case X86ISD::VBROADCAST: return "X86ISD::VBROADCAST";
20093 case X86ISD::SUBV_BROADCAST: return "X86ISD::SUBV_BROADCAST";
20094 case X86ISD::VEXTRACT: return "X86ISD::VEXTRACT";
20095 case X86ISD::VPERMILPV: return "X86ISD::VPERMILPV";
20096 case X86ISD::VPERMILPI: return "X86ISD::VPERMILPI";
20097 case X86ISD::VPERM2X128: return "X86ISD::VPERM2X128";
20098 case X86ISD::VPERMV: return "X86ISD::VPERMV";
20099 case X86ISD::VPERMV3: return "X86ISD::VPERMV3";
20100 case X86ISD::VPERMIV3: return "X86ISD::VPERMIV3";
20101 case X86ISD::VPERMI: return "X86ISD::VPERMI";
20102 case X86ISD::VPTERNLOG: return "X86ISD::VPTERNLOG";
20103 case X86ISD::VFIXUPIMM: return "X86ISD::VFIXUPIMM";
20104 case X86ISD::VRANGE: return "X86ISD::VRANGE";
20105 case X86ISD::PMULUDQ: return "X86ISD::PMULUDQ";
20106 case X86ISD::PMULDQ: return "X86ISD::PMULDQ";
20107 case X86ISD::PSADBW: return "X86ISD::PSADBW";
20108 case X86ISD::DBPSADBW: return "X86ISD::DBPSADBW";
20109 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
20110 case X86ISD::VAARG_64: return "X86ISD::VAARG_64";
20111 case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA";
20112 case X86ISD::MEMBARRIER: return "X86ISD::MEMBARRIER";
20113 case X86ISD::MFENCE: return "X86ISD::MFENCE";
20114 case X86ISD::SFENCE: return "X86ISD::SFENCE";
20115 case X86ISD::LFENCE: return "X86ISD::LFENCE";
20116 case X86ISD::SEG_ALLOCA: return "X86ISD::SEG_ALLOCA";
20117 case X86ISD::SAHF: return "X86ISD::SAHF";
20118 case X86ISD::RDRAND: return "X86ISD::RDRAND";
20119 case X86ISD::RDSEED: return "X86ISD::RDSEED";
20120 case X86ISD::VPMADDUBSW: return "X86ISD::VPMADDUBSW";
20121 case X86ISD::VPMADDWD: return "X86ISD::VPMADDWD";
20122 case X86ISD::VPROT: return "X86ISD::VPROT";
20123 case X86ISD::VPROTI: return "X86ISD::VPROTI";
20124 case X86ISD::VPSHA: return "X86ISD::VPSHA";
20125 case X86ISD::VPSHL: return "X86ISD::VPSHL";
20126 case X86ISD::VPCOM: return "X86ISD::VPCOM";
20127 case X86ISD::VPCOMU: return "X86ISD::VPCOMU";
20128 case X86ISD::FMADD: return "X86ISD::FMADD";
20129 case X86ISD::FMSUB: return "X86ISD::FMSUB";
20130 case X86ISD::FNMADD: return "X86ISD::FNMADD";
20131 case X86ISD::FNMSUB: return "X86ISD::FNMSUB";
20132 case X86ISD::FMADDSUB: return "X86ISD::FMADDSUB";
20133 case X86ISD::FMSUBADD: return "X86ISD::FMSUBADD";
20134 case X86ISD::FMADD_RND: return "X86ISD::FMADD_RND";
20135 case X86ISD::FNMADD_RND: return "X86ISD::FNMADD_RND";
20136 case X86ISD::FMSUB_RND: return "X86ISD::FMSUB_RND";
20137 case X86ISD::FNMSUB_RND: return "X86ISD::FNMSUB_RND";
20138 case X86ISD::FMADDSUB_RND: return "X86ISD::FMADDSUB_RND";
20139 case X86ISD::FMSUBADD_RND: return "X86ISD::FMSUBADD_RND";
20140 case X86ISD::VRNDSCALE: return "X86ISD::VRNDSCALE";
20141 case X86ISD::VREDUCE: return "X86ISD::VREDUCE";
20142 case X86ISD::VGETMANT: return "X86ISD::VGETMANT";
20143 case X86ISD::PCMPESTRI: return "X86ISD::PCMPESTRI";
20144 case X86ISD::PCMPISTRI: return "X86ISD::PCMPISTRI";
20145 case X86ISD::XTEST: return "X86ISD::XTEST";
20146 case X86ISD::COMPRESS: return "X86ISD::COMPRESS";
20147 case X86ISD::EXPAND: return "X86ISD::EXPAND";
20148 case X86ISD::SELECT: return "X86ISD::SELECT";
20149 case X86ISD::ADDSUB: return "X86ISD::ADDSUB";
20150 case X86ISD::RCP28: return "X86ISD::RCP28";
20151 case X86ISD::EXP2: return "X86ISD::EXP2";
20152 case X86ISD::RSQRT28: return "X86ISD::RSQRT28";
20153 case X86ISD::FADD_RND: return "X86ISD::FADD_RND";
20154 case X86ISD::FSUB_RND: return "X86ISD::FSUB_RND";
20155 case X86ISD::FMUL_RND: return "X86ISD::FMUL_RND";
20156 case X86ISD::FDIV_RND: return "X86ISD::FDIV_RND";
20157 case X86ISD::FSQRT_RND: return "X86ISD::FSQRT_RND";
20158 case X86ISD::FGETEXP_RND: return "X86ISD::FGETEXP_RND";
20159 case X86ISD::SCALEF: return "X86ISD::SCALEF";
20160 case X86ISD::ADDS: return "X86ISD::ADDS";
20161 case X86ISD::SUBS: return "X86ISD::SUBS";
20162 case X86ISD::AVG: return "X86ISD::AVG";
20163 case X86ISD::MULHRS: return "X86ISD::MULHRS";
20164 case X86ISD::SINT_TO_FP_RND: return "X86ISD::SINT_TO_FP_RND";
20165 case X86ISD::UINT_TO_FP_RND: return "X86ISD::UINT_TO_FP_RND";
20166 case X86ISD::FP_TO_SINT_RND: return "X86ISD::FP_TO_SINT_RND";
20167 case X86ISD::FP_TO_UINT_RND: return "X86ISD::FP_TO_UINT_RND";
20168 case X86ISD::VFPCLASS: return "X86ISD::VFPCLASS";
20173 // isLegalAddressingMode - Return true if the addressing mode represented
20174 // by AM is legal for this target, for a load/store of the specified type.
20175 bool X86TargetLowering::isLegalAddressingMode(const DataLayout &DL,
20176 const AddrMode &AM, Type *Ty,
20177 unsigned AS) const {
20178 // X86 supports extremely general addressing modes.
20179 CodeModel::Model M = getTargetMachine().getCodeModel();
20180 Reloc::Model R = getTargetMachine().getRelocationModel();
20182 // X86 allows a sign-extended 32-bit immediate field as a displacement.
20183 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != nullptr))
20188 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
20190 // If a reference to this global requires an extra load, we can't fold it.
20191 if (isGlobalStubReference(GVFlags))
20194 // If BaseGV requires a register for the PIC base, we cannot also have a
20195 // BaseReg specified.
20196 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
20199 // If lower 4G is not available, then we must use rip-relative addressing.
20200 if ((M != CodeModel::Small || R != Reloc::Static) &&
20201 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
20205 switch (AM.Scale) {
20211 // These scales always work.
20216 // These scales are formed with basereg+scalereg. Only accept if there is
20221 default: // Other stuff never works.
20228 bool X86TargetLowering::isVectorShiftByScalarCheap(Type *Ty) const {
20229 unsigned Bits = Ty->getScalarSizeInBits();
20231 // 8-bit shifts are always expensive, but versions with a scalar amount aren't
20232 // particularly cheaper than those without.
20236 // On AVX2 there are new vpsllv[dq] instructions (and other shifts), that make
20237 // variable shifts just as cheap as scalar ones.
20238 if (Subtarget->hasInt256() && (Bits == 32 || Bits == 64))
20241 // Otherwise, it's significantly cheaper to shift by a scalar amount than by a
20242 // fully general vector.
20246 bool X86TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
20247 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
20249 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
20250 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
20251 return NumBits1 > NumBits2;
20254 bool X86TargetLowering::allowTruncateForTailCall(Type *Ty1, Type *Ty2) const {
20255 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
20258 if (!isTypeLegal(EVT::getEVT(Ty1)))
20261 assert(Ty1->getPrimitiveSizeInBits() <= 64 && "i128 is probably not a noop");
20263 // Assuming the caller doesn't have a zeroext or signext return parameter,
20264 // truncation all the way down to i1 is valid.
20268 bool X86TargetLowering::isLegalICmpImmediate(int64_t Imm) const {
20269 return isInt<32>(Imm);
20272 bool X86TargetLowering::isLegalAddImmediate(int64_t Imm) const {
20273 // Can also use sub to handle negated immediates.
20274 return isInt<32>(Imm);
20277 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
20278 if (!VT1.isInteger() || !VT2.isInteger())
20280 unsigned NumBits1 = VT1.getSizeInBits();
20281 unsigned NumBits2 = VT2.getSizeInBits();
20282 return NumBits1 > NumBits2;
20285 bool X86TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
20286 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
20287 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit();
20290 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
20291 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
20292 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
20295 bool X86TargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
20296 EVT VT1 = Val.getValueType();
20297 if (isZExtFree(VT1, VT2))
20300 if (Val.getOpcode() != ISD::LOAD)
20303 if (!VT1.isSimple() || !VT1.isInteger() ||
20304 !VT2.isSimple() || !VT2.isInteger())
20307 switch (VT1.getSimpleVT().SimpleTy) {
20312 // X86 has 8, 16, and 32-bit zero-extending loads.
20319 bool X86TargetLowering::isVectorLoadExtDesirable(SDValue) const { return true; }
20322 X86TargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
20323 if (!(Subtarget->hasFMA() || Subtarget->hasFMA4() || Subtarget->hasAVX512()))
20326 VT = VT.getScalarType();
20328 if (!VT.isSimple())
20331 switch (VT.getSimpleVT().SimpleTy) {
20342 bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
20343 // i16 instructions are longer (0x66 prefix) and potentially slower.
20344 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
20347 /// isShuffleMaskLegal - Targets can use this to indicate that they only
20348 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
20349 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
20350 /// are assumed to be legal.
20352 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
20354 if (!VT.isSimple())
20357 // Not for i1 vectors
20358 if (VT.getSimpleVT().getScalarType() == MVT::i1)
20361 // Very little shuffling can be done for 64-bit vectors right now.
20362 if (VT.getSimpleVT().getSizeInBits() == 64)
20365 // We only care that the types being shuffled are legal. The lowering can
20366 // handle any possible shuffle mask that results.
20367 return isTypeLegal(VT.getSimpleVT());
20371 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
20373 // Just delegate to the generic legality, clear masks aren't special.
20374 return isShuffleMaskLegal(Mask, VT);
20377 //===----------------------------------------------------------------------===//
20378 // X86 Scheduler Hooks
20379 //===----------------------------------------------------------------------===//
20381 /// Utility function to emit xbegin specifying the start of an RTM region.
20382 static MachineBasicBlock *EmitXBegin(MachineInstr *MI, MachineBasicBlock *MBB,
20383 const TargetInstrInfo *TII) {
20384 DebugLoc DL = MI->getDebugLoc();
20386 const BasicBlock *BB = MBB->getBasicBlock();
20387 MachineFunction::iterator I = ++MBB->getIterator();
20389 // For the v = xbegin(), we generate
20400 MachineBasicBlock *thisMBB = MBB;
20401 MachineFunction *MF = MBB->getParent();
20402 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
20403 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
20404 MF->insert(I, mainMBB);
20405 MF->insert(I, sinkMBB);
20407 // Transfer the remainder of BB and its successor edges to sinkMBB.
20408 sinkMBB->splice(sinkMBB->begin(), MBB,
20409 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
20410 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
20414 // # fallthrough to mainMBB
20415 // # abortion to sinkMBB
20416 BuildMI(thisMBB, DL, TII->get(X86::XBEGIN_4)).addMBB(sinkMBB);
20417 thisMBB->addSuccessor(mainMBB);
20418 thisMBB->addSuccessor(sinkMBB);
20422 BuildMI(mainMBB, DL, TII->get(X86::MOV32ri), X86::EAX).addImm(-1);
20423 mainMBB->addSuccessor(sinkMBB);
20426 // EAX is live into the sinkMBB
20427 sinkMBB->addLiveIn(X86::EAX);
20428 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
20429 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
20432 MI->eraseFromParent();
20436 // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
20437 // or XMM0_V32I8 in AVX all of this code can be replaced with that
20438 // in the .td file.
20439 static MachineBasicBlock *EmitPCMPSTRM(MachineInstr *MI, MachineBasicBlock *BB,
20440 const TargetInstrInfo *TII) {
20442 switch (MI->getOpcode()) {
20443 default: llvm_unreachable("illegal opcode!");
20444 case X86::PCMPISTRM128REG: Opc = X86::PCMPISTRM128rr; break;
20445 case X86::VPCMPISTRM128REG: Opc = X86::VPCMPISTRM128rr; break;
20446 case X86::PCMPISTRM128MEM: Opc = X86::PCMPISTRM128rm; break;
20447 case X86::VPCMPISTRM128MEM: Opc = X86::VPCMPISTRM128rm; break;
20448 case X86::PCMPESTRM128REG: Opc = X86::PCMPESTRM128rr; break;
20449 case X86::VPCMPESTRM128REG: Opc = X86::VPCMPESTRM128rr; break;
20450 case X86::PCMPESTRM128MEM: Opc = X86::PCMPESTRM128rm; break;
20451 case X86::VPCMPESTRM128MEM: Opc = X86::VPCMPESTRM128rm; break;
20454 DebugLoc dl = MI->getDebugLoc();
20455 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
20457 unsigned NumArgs = MI->getNumOperands();
20458 for (unsigned i = 1; i < NumArgs; ++i) {
20459 MachineOperand &Op = MI->getOperand(i);
20460 if (!(Op.isReg() && Op.isImplicit()))
20461 MIB.addOperand(Op);
20463 if (MI->hasOneMemOperand())
20464 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
20466 BuildMI(*BB, MI, dl,
20467 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
20468 .addReg(X86::XMM0);
20470 MI->eraseFromParent();
20474 // FIXME: Custom handling because TableGen doesn't support multiple implicit
20475 // defs in an instruction pattern
20476 static MachineBasicBlock *EmitPCMPSTRI(MachineInstr *MI, MachineBasicBlock *BB,
20477 const TargetInstrInfo *TII) {
20479 switch (MI->getOpcode()) {
20480 default: llvm_unreachable("illegal opcode!");
20481 case X86::PCMPISTRIREG: Opc = X86::PCMPISTRIrr; break;
20482 case X86::VPCMPISTRIREG: Opc = X86::VPCMPISTRIrr; break;
20483 case X86::PCMPISTRIMEM: Opc = X86::PCMPISTRIrm; break;
20484 case X86::VPCMPISTRIMEM: Opc = X86::VPCMPISTRIrm; break;
20485 case X86::PCMPESTRIREG: Opc = X86::PCMPESTRIrr; break;
20486 case X86::VPCMPESTRIREG: Opc = X86::VPCMPESTRIrr; break;
20487 case X86::PCMPESTRIMEM: Opc = X86::PCMPESTRIrm; break;
20488 case X86::VPCMPESTRIMEM: Opc = X86::VPCMPESTRIrm; break;
20491 DebugLoc dl = MI->getDebugLoc();
20492 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
20494 unsigned NumArgs = MI->getNumOperands(); // remove the results
20495 for (unsigned i = 1; i < NumArgs; ++i) {
20496 MachineOperand &Op = MI->getOperand(i);
20497 if (!(Op.isReg() && Op.isImplicit()))
20498 MIB.addOperand(Op);
20500 if (MI->hasOneMemOperand())
20501 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
20503 BuildMI(*BB, MI, dl,
20504 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
20507 MI->eraseFromParent();
20511 static MachineBasicBlock *EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB,
20512 const X86Subtarget *Subtarget) {
20513 DebugLoc dl = MI->getDebugLoc();
20514 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
20515 // Address into RAX/EAX, other two args into ECX, EDX.
20516 unsigned MemOpc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
20517 unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
20518 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg);
20519 for (int i = 0; i < X86::AddrNumOperands; ++i)
20520 MIB.addOperand(MI->getOperand(i));
20522 unsigned ValOps = X86::AddrNumOperands;
20523 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
20524 .addReg(MI->getOperand(ValOps).getReg());
20525 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EDX)
20526 .addReg(MI->getOperand(ValOps+1).getReg());
20528 // The instruction doesn't actually take any operands though.
20529 BuildMI(*BB, MI, dl, TII->get(X86::MONITORrrr));
20531 MI->eraseFromParent(); // The pseudo is gone now.
20535 MachineBasicBlock *
20536 X86TargetLowering::EmitVAARG64WithCustomInserter(MachineInstr *MI,
20537 MachineBasicBlock *MBB) const {
20538 // Emit va_arg instruction on X86-64.
20540 // Operands to this pseudo-instruction:
20541 // 0 ) Output : destination address (reg)
20542 // 1-5) Input : va_list address (addr, i64mem)
20543 // 6 ) ArgSize : Size (in bytes) of vararg type
20544 // 7 ) ArgMode : 0=overflow only, 1=use gp_offset, 2=use fp_offset
20545 // 8 ) Align : Alignment of type
20546 // 9 ) EFLAGS (implicit-def)
20548 assert(MI->getNumOperands() == 10 && "VAARG_64 should have 10 operands!");
20549 static_assert(X86::AddrNumOperands == 5,
20550 "VAARG_64 assumes 5 address operands");
20552 unsigned DestReg = MI->getOperand(0).getReg();
20553 MachineOperand &Base = MI->getOperand(1);
20554 MachineOperand &Scale = MI->getOperand(2);
20555 MachineOperand &Index = MI->getOperand(3);
20556 MachineOperand &Disp = MI->getOperand(4);
20557 MachineOperand &Segment = MI->getOperand(5);
20558 unsigned ArgSize = MI->getOperand(6).getImm();
20559 unsigned ArgMode = MI->getOperand(7).getImm();
20560 unsigned Align = MI->getOperand(8).getImm();
20562 // Memory Reference
20563 assert(MI->hasOneMemOperand() && "Expected VAARG_64 to have one memoperand");
20564 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
20565 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
20567 // Machine Information
20568 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
20569 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
20570 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64);
20571 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32);
20572 DebugLoc DL = MI->getDebugLoc();
20574 // struct va_list {
20577 // i64 overflow_area (address)
20578 // i64 reg_save_area (address)
20580 // sizeof(va_list) = 24
20581 // alignment(va_list) = 8
20583 unsigned TotalNumIntRegs = 6;
20584 unsigned TotalNumXMMRegs = 8;
20585 bool UseGPOffset = (ArgMode == 1);
20586 bool UseFPOffset = (ArgMode == 2);
20587 unsigned MaxOffset = TotalNumIntRegs * 8 +
20588 (UseFPOffset ? TotalNumXMMRegs * 16 : 0);
20590 /* Align ArgSize to a multiple of 8 */
20591 unsigned ArgSizeA8 = (ArgSize + 7) & ~7;
20592 bool NeedsAlign = (Align > 8);
20594 MachineBasicBlock *thisMBB = MBB;
20595 MachineBasicBlock *overflowMBB;
20596 MachineBasicBlock *offsetMBB;
20597 MachineBasicBlock *endMBB;
20599 unsigned OffsetDestReg = 0; // Argument address computed by offsetMBB
20600 unsigned OverflowDestReg = 0; // Argument address computed by overflowMBB
20601 unsigned OffsetReg = 0;
20603 if (!UseGPOffset && !UseFPOffset) {
20604 // If we only pull from the overflow region, we don't create a branch.
20605 // We don't need to alter control flow.
20606 OffsetDestReg = 0; // unused
20607 OverflowDestReg = DestReg;
20609 offsetMBB = nullptr;
20610 overflowMBB = thisMBB;
20613 // First emit code to check if gp_offset (or fp_offset) is below the bound.
20614 // If so, pull the argument from reg_save_area. (branch to offsetMBB)
20615 // If not, pull from overflow_area. (branch to overflowMBB)
20620 // offsetMBB overflowMBB
20625 // Registers for the PHI in endMBB
20626 OffsetDestReg = MRI.createVirtualRegister(AddrRegClass);
20627 OverflowDestReg = MRI.createVirtualRegister(AddrRegClass);
20629 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
20630 MachineFunction *MF = MBB->getParent();
20631 overflowMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20632 offsetMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20633 endMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20635 MachineFunction::iterator MBBIter = ++MBB->getIterator();
20637 // Insert the new basic blocks
20638 MF->insert(MBBIter, offsetMBB);
20639 MF->insert(MBBIter, overflowMBB);
20640 MF->insert(MBBIter, endMBB);
20642 // Transfer the remainder of MBB and its successor edges to endMBB.
20643 endMBB->splice(endMBB->begin(), thisMBB,
20644 std::next(MachineBasicBlock::iterator(MI)), thisMBB->end());
20645 endMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
20647 // Make offsetMBB and overflowMBB successors of thisMBB
20648 thisMBB->addSuccessor(offsetMBB);
20649 thisMBB->addSuccessor(overflowMBB);
20651 // endMBB is a successor of both offsetMBB and overflowMBB
20652 offsetMBB->addSuccessor(endMBB);
20653 overflowMBB->addSuccessor(endMBB);
20655 // Load the offset value into a register
20656 OffsetReg = MRI.createVirtualRegister(OffsetRegClass);
20657 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg)
20661 .addDisp(Disp, UseFPOffset ? 4 : 0)
20662 .addOperand(Segment)
20663 .setMemRefs(MMOBegin, MMOEnd);
20665 // Check if there is enough room left to pull this argument.
20666 BuildMI(thisMBB, DL, TII->get(X86::CMP32ri))
20668 .addImm(MaxOffset + 8 - ArgSizeA8);
20670 // Branch to "overflowMBB" if offset >= max
20671 // Fall through to "offsetMBB" otherwise
20672 BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE)))
20673 .addMBB(overflowMBB);
20676 // In offsetMBB, emit code to use the reg_save_area.
20678 assert(OffsetReg != 0);
20680 // Read the reg_save_area address.
20681 unsigned RegSaveReg = MRI.createVirtualRegister(AddrRegClass);
20682 BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg)
20687 .addOperand(Segment)
20688 .setMemRefs(MMOBegin, MMOEnd);
20690 // Zero-extend the offset
20691 unsigned OffsetReg64 = MRI.createVirtualRegister(AddrRegClass);
20692 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64)
20695 .addImm(X86::sub_32bit);
20697 // Add the offset to the reg_save_area to get the final address.
20698 BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg)
20699 .addReg(OffsetReg64)
20700 .addReg(RegSaveReg);
20702 // Compute the offset for the next argument
20703 unsigned NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass);
20704 BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg)
20706 .addImm(UseFPOffset ? 16 : 8);
20708 // Store it back into the va_list.
20709 BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr))
20713 .addDisp(Disp, UseFPOffset ? 4 : 0)
20714 .addOperand(Segment)
20715 .addReg(NextOffsetReg)
20716 .setMemRefs(MMOBegin, MMOEnd);
20719 BuildMI(offsetMBB, DL, TII->get(X86::JMP_1))
20724 // Emit code to use overflow area
20727 // Load the overflow_area address into a register.
20728 unsigned OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass);
20729 BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg)
20734 .addOperand(Segment)
20735 .setMemRefs(MMOBegin, MMOEnd);
20737 // If we need to align it, do so. Otherwise, just copy the address
20738 // to OverflowDestReg.
20740 // Align the overflow address
20741 assert((Align & (Align-1)) == 0 && "Alignment must be a power of 2");
20742 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass);
20744 // aligned_addr = (addr + (align-1)) & ~(align-1)
20745 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg)
20746 .addReg(OverflowAddrReg)
20749 BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg)
20751 .addImm(~(uint64_t)(Align-1));
20753 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg)
20754 .addReg(OverflowAddrReg);
20757 // Compute the next overflow address after this argument.
20758 // (the overflow address should be kept 8-byte aligned)
20759 unsigned NextAddrReg = MRI.createVirtualRegister(AddrRegClass);
20760 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg)
20761 .addReg(OverflowDestReg)
20762 .addImm(ArgSizeA8);
20764 // Store the new overflow address.
20765 BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr))
20770 .addOperand(Segment)
20771 .addReg(NextAddrReg)
20772 .setMemRefs(MMOBegin, MMOEnd);
20774 // If we branched, emit the PHI to the front of endMBB.
20776 BuildMI(*endMBB, endMBB->begin(), DL,
20777 TII->get(X86::PHI), DestReg)
20778 .addReg(OffsetDestReg).addMBB(offsetMBB)
20779 .addReg(OverflowDestReg).addMBB(overflowMBB);
20782 // Erase the pseudo instruction
20783 MI->eraseFromParent();
20788 MachineBasicBlock *
20789 X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
20791 MachineBasicBlock *MBB) const {
20792 // Emit code to save XMM registers to the stack. The ABI says that the
20793 // number of registers to save is given in %al, so it's theoretically
20794 // possible to do an indirect jump trick to avoid saving all of them,
20795 // however this code takes a simpler approach and just executes all
20796 // of the stores if %al is non-zero. It's less code, and it's probably
20797 // easier on the hardware branch predictor, and stores aren't all that
20798 // expensive anyway.
20800 // Create the new basic blocks. One block contains all the XMM stores,
20801 // and one block is the final destination regardless of whether any
20802 // stores were performed.
20803 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
20804 MachineFunction *F = MBB->getParent();
20805 MachineFunction::iterator MBBIter = ++MBB->getIterator();
20806 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB);
20807 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB);
20808 F->insert(MBBIter, XMMSaveMBB);
20809 F->insert(MBBIter, EndMBB);
20811 // Transfer the remainder of MBB and its successor edges to EndMBB.
20812 EndMBB->splice(EndMBB->begin(), MBB,
20813 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
20814 EndMBB->transferSuccessorsAndUpdatePHIs(MBB);
20816 // The original block will now fall through to the XMM save block.
20817 MBB->addSuccessor(XMMSaveMBB);
20818 // The XMMSaveMBB will fall through to the end block.
20819 XMMSaveMBB->addSuccessor(EndMBB);
20821 // Now add the instructions.
20822 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
20823 DebugLoc DL = MI->getDebugLoc();
20825 unsigned CountReg = MI->getOperand(0).getReg();
20826 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm();
20827 int64_t VarArgsFPOffset = MI->getOperand(2).getImm();
20829 if (!Subtarget->isCallingConvWin64(F->getFunction()->getCallingConv())) {
20830 // If %al is 0, branch around the XMM save block.
20831 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
20832 BuildMI(MBB, DL, TII->get(X86::JE_1)).addMBB(EndMBB);
20833 MBB->addSuccessor(EndMBB);
20836 // Make sure the last operand is EFLAGS, which gets clobbered by the branch
20837 // that was just emitted, but clearly shouldn't be "saved".
20838 assert((MI->getNumOperands() <= 3 ||
20839 !MI->getOperand(MI->getNumOperands() - 1).isReg() ||
20840 MI->getOperand(MI->getNumOperands() - 1).getReg() == X86::EFLAGS)
20841 && "Expected last argument to be EFLAGS");
20842 unsigned MOVOpc = Subtarget->hasFp256() ? X86::VMOVAPSmr : X86::MOVAPSmr;
20843 // In the XMM save block, save all the XMM argument registers.
20844 for (int i = 3, e = MI->getNumOperands() - 1; i != e; ++i) {
20845 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
20846 MachineMemOperand *MMO = F->getMachineMemOperand(
20847 MachinePointerInfo::getFixedStack(*F, RegSaveFrameIndex, Offset),
20848 MachineMemOperand::MOStore,
20849 /*Size=*/16, /*Align=*/16);
20850 BuildMI(XMMSaveMBB, DL, TII->get(MOVOpc))
20851 .addFrameIndex(RegSaveFrameIndex)
20852 .addImm(/*Scale=*/1)
20853 .addReg(/*IndexReg=*/0)
20854 .addImm(/*Disp=*/Offset)
20855 .addReg(/*Segment=*/0)
20856 .addReg(MI->getOperand(i).getReg())
20857 .addMemOperand(MMO);
20860 MI->eraseFromParent(); // The pseudo instruction is gone now.
20865 // The EFLAGS operand of SelectItr might be missing a kill marker
20866 // because there were multiple uses of EFLAGS, and ISel didn't know
20867 // which to mark. Figure out whether SelectItr should have had a
20868 // kill marker, and set it if it should. Returns the correct kill
20870 static bool checkAndUpdateEFLAGSKill(MachineBasicBlock::iterator SelectItr,
20871 MachineBasicBlock* BB,
20872 const TargetRegisterInfo* TRI) {
20873 // Scan forward through BB for a use/def of EFLAGS.
20874 MachineBasicBlock::iterator miI(std::next(SelectItr));
20875 for (MachineBasicBlock::iterator miE = BB->end(); miI != miE; ++miI) {
20876 const MachineInstr& mi = *miI;
20877 if (mi.readsRegister(X86::EFLAGS))
20879 if (mi.definesRegister(X86::EFLAGS))
20880 break; // Should have kill-flag - update below.
20883 // If we hit the end of the block, check whether EFLAGS is live into a
20885 if (miI == BB->end()) {
20886 for (MachineBasicBlock::succ_iterator sItr = BB->succ_begin(),
20887 sEnd = BB->succ_end();
20888 sItr != sEnd; ++sItr) {
20889 MachineBasicBlock* succ = *sItr;
20890 if (succ->isLiveIn(X86::EFLAGS))
20895 // We found a def, or hit the end of the basic block and EFLAGS wasn't live
20896 // out. SelectMI should have a kill flag on EFLAGS.
20897 SelectItr->addRegisterKilled(X86::EFLAGS, TRI);
20901 // Return true if it is OK for this CMOV pseudo-opcode to be cascaded
20902 // together with other CMOV pseudo-opcodes into a single basic-block with
20903 // conditional jump around it.
20904 static bool isCMOVPseudo(MachineInstr *MI) {
20905 switch (MI->getOpcode()) {
20906 case X86::CMOV_FR32:
20907 case X86::CMOV_FR64:
20908 case X86::CMOV_GR8:
20909 case X86::CMOV_GR16:
20910 case X86::CMOV_GR32:
20911 case X86::CMOV_RFP32:
20912 case X86::CMOV_RFP64:
20913 case X86::CMOV_RFP80:
20914 case X86::CMOV_V2F64:
20915 case X86::CMOV_V2I64:
20916 case X86::CMOV_V4F32:
20917 case X86::CMOV_V4F64:
20918 case X86::CMOV_V4I64:
20919 case X86::CMOV_V16F32:
20920 case X86::CMOV_V8F32:
20921 case X86::CMOV_V8F64:
20922 case X86::CMOV_V8I64:
20923 case X86::CMOV_V8I1:
20924 case X86::CMOV_V16I1:
20925 case X86::CMOV_V32I1:
20926 case X86::CMOV_V64I1:
20934 MachineBasicBlock *
20935 X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
20936 MachineBasicBlock *BB) const {
20937 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
20938 DebugLoc DL = MI->getDebugLoc();
20940 // To "insert" a SELECT_CC instruction, we actually have to insert the
20941 // diamond control-flow pattern. The incoming instruction knows the
20942 // destination vreg to set, the condition code register to branch on, the
20943 // true/false values to select between, and a branch opcode to use.
20944 const BasicBlock *LLVM_BB = BB->getBasicBlock();
20945 MachineFunction::iterator It = ++BB->getIterator();
20950 // cmpTY ccX, r1, r2
20952 // fallthrough --> copy0MBB
20953 MachineBasicBlock *thisMBB = BB;
20954 MachineFunction *F = BB->getParent();
20956 // This code lowers all pseudo-CMOV instructions. Generally it lowers these
20957 // as described above, by inserting a BB, and then making a PHI at the join
20958 // point to select the true and false operands of the CMOV in the PHI.
20960 // The code also handles two different cases of multiple CMOV opcodes
20964 // In this case, there are multiple CMOVs in a row, all which are based on
20965 // the same condition setting (or the exact opposite condition setting).
20966 // In this case we can lower all the CMOVs using a single inserted BB, and
20967 // then make a number of PHIs at the join point to model the CMOVs. The only
20968 // trickiness here, is that in a case like:
20970 // t2 = CMOV cond1 t1, f1
20971 // t3 = CMOV cond1 t2, f2
20973 // when rewriting this into PHIs, we have to perform some renaming on the
20974 // temps since you cannot have a PHI operand refer to a PHI result earlier
20975 // in the same block. The "simple" but wrong lowering would be:
20977 // t2 = PHI t1(BB1), f1(BB2)
20978 // t3 = PHI t2(BB1), f2(BB2)
20980 // but clearly t2 is not defined in BB1, so that is incorrect. The proper
20981 // renaming is to note that on the path through BB1, t2 is really just a
20982 // copy of t1, and do that renaming, properly generating:
20984 // t2 = PHI t1(BB1), f1(BB2)
20985 // t3 = PHI t1(BB1), f2(BB2)
20987 // Case 2, we lower cascaded CMOVs such as
20989 // (CMOV (CMOV F, T, cc1), T, cc2)
20991 // to two successives branches. For that, we look for another CMOV as the
20992 // following instruction.
20994 // Without this, we would add a PHI between the two jumps, which ends up
20995 // creating a few copies all around. For instance, for
20997 // (sitofp (zext (fcmp une)))
20999 // we would generate:
21001 // ucomiss %xmm1, %xmm0
21002 // movss <1.0f>, %xmm0
21003 // movaps %xmm0, %xmm1
21005 // xorps %xmm1, %xmm1
21008 // movaps %xmm1, %xmm0
21012 // because this custom-inserter would have generated:
21024 // A: X = ...; Y = ...
21026 // C: Z = PHI [X, A], [Y, B]
21028 // E: PHI [X, C], [Z, D]
21030 // If we lower both CMOVs in a single step, we can instead generate:
21042 // A: X = ...; Y = ...
21044 // E: PHI [X, A], [X, C], [Y, D]
21046 // Which, in our sitofp/fcmp example, gives us something like:
21048 // ucomiss %xmm1, %xmm0
21049 // movss <1.0f>, %xmm0
21052 // xorps %xmm0, %xmm0
21056 MachineInstr *CascadedCMOV = nullptr;
21057 MachineInstr *LastCMOV = MI;
21058 X86::CondCode CC = X86::CondCode(MI->getOperand(3).getImm());
21059 X86::CondCode OppCC = X86::GetOppositeBranchCondition(CC);
21060 MachineBasicBlock::iterator NextMIIt =
21061 std::next(MachineBasicBlock::iterator(MI));
21063 // Check for case 1, where there are multiple CMOVs with the same condition
21064 // first. Of the two cases of multiple CMOV lowerings, case 1 reduces the
21065 // number of jumps the most.
21067 if (isCMOVPseudo(MI)) {
21068 // See if we have a string of CMOVS with the same condition.
21069 while (NextMIIt != BB->end() &&
21070 isCMOVPseudo(NextMIIt) &&
21071 (NextMIIt->getOperand(3).getImm() == CC ||
21072 NextMIIt->getOperand(3).getImm() == OppCC)) {
21073 LastCMOV = &*NextMIIt;
21078 // This checks for case 2, but only do this if we didn't already find
21079 // case 1, as indicated by LastCMOV == MI.
21080 if (LastCMOV == MI &&
21081 NextMIIt != BB->end() && NextMIIt->getOpcode() == MI->getOpcode() &&
21082 NextMIIt->getOperand(2).getReg() == MI->getOperand(2).getReg() &&
21083 NextMIIt->getOperand(1).getReg() == MI->getOperand(0).getReg()) {
21084 CascadedCMOV = &*NextMIIt;
21087 MachineBasicBlock *jcc1MBB = nullptr;
21089 // If we have a cascaded CMOV, we lower it to two successive branches to
21090 // the same block. EFLAGS is used by both, so mark it as live in the second.
21091 if (CascadedCMOV) {
21092 jcc1MBB = F->CreateMachineBasicBlock(LLVM_BB);
21093 F->insert(It, jcc1MBB);
21094 jcc1MBB->addLiveIn(X86::EFLAGS);
21097 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
21098 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
21099 F->insert(It, copy0MBB);
21100 F->insert(It, sinkMBB);
21102 // If the EFLAGS register isn't dead in the terminator, then claim that it's
21103 // live into the sink and copy blocks.
21104 const TargetRegisterInfo *TRI = Subtarget->getRegisterInfo();
21106 MachineInstr *LastEFLAGSUser = CascadedCMOV ? CascadedCMOV : LastCMOV;
21107 if (!LastEFLAGSUser->killsRegister(X86::EFLAGS) &&
21108 !checkAndUpdateEFLAGSKill(LastEFLAGSUser, BB, TRI)) {
21109 copy0MBB->addLiveIn(X86::EFLAGS);
21110 sinkMBB->addLiveIn(X86::EFLAGS);
21113 // Transfer the remainder of BB and its successor edges to sinkMBB.
21114 sinkMBB->splice(sinkMBB->begin(), BB,
21115 std::next(MachineBasicBlock::iterator(LastCMOV)), BB->end());
21116 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
21118 // Add the true and fallthrough blocks as its successors.
21119 if (CascadedCMOV) {
21120 // The fallthrough block may be jcc1MBB, if we have a cascaded CMOV.
21121 BB->addSuccessor(jcc1MBB);
21123 // In that case, jcc1MBB will itself fallthrough the copy0MBB, and
21124 // jump to the sinkMBB.
21125 jcc1MBB->addSuccessor(copy0MBB);
21126 jcc1MBB->addSuccessor(sinkMBB);
21128 BB->addSuccessor(copy0MBB);
21131 // The true block target of the first (or only) branch is always sinkMBB.
21132 BB->addSuccessor(sinkMBB);
21134 // Create the conditional branch instruction.
21135 unsigned Opc = X86::GetCondBranchFromCond(CC);
21136 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
21138 if (CascadedCMOV) {
21139 unsigned Opc2 = X86::GetCondBranchFromCond(
21140 (X86::CondCode)CascadedCMOV->getOperand(3).getImm());
21141 BuildMI(jcc1MBB, DL, TII->get(Opc2)).addMBB(sinkMBB);
21145 // %FalseValue = ...
21146 // # fallthrough to sinkMBB
21147 copy0MBB->addSuccessor(sinkMBB);
21150 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
21152 MachineBasicBlock::iterator MIItBegin = MachineBasicBlock::iterator(MI);
21153 MachineBasicBlock::iterator MIItEnd =
21154 std::next(MachineBasicBlock::iterator(LastCMOV));
21155 MachineBasicBlock::iterator SinkInsertionPoint = sinkMBB->begin();
21156 DenseMap<unsigned, std::pair<unsigned, unsigned>> RegRewriteTable;
21157 MachineInstrBuilder MIB;
21159 // As we are creating the PHIs, we have to be careful if there is more than
21160 // one. Later CMOVs may reference the results of earlier CMOVs, but later
21161 // PHIs have to reference the individual true/false inputs from earlier PHIs.
21162 // That also means that PHI construction must work forward from earlier to
21163 // later, and that the code must maintain a mapping from earlier PHI's
21164 // destination registers, and the registers that went into the PHI.
21166 for (MachineBasicBlock::iterator MIIt = MIItBegin; MIIt != MIItEnd; ++MIIt) {
21167 unsigned DestReg = MIIt->getOperand(0).getReg();
21168 unsigned Op1Reg = MIIt->getOperand(1).getReg();
21169 unsigned Op2Reg = MIIt->getOperand(2).getReg();
21171 // If this CMOV we are generating is the opposite condition from
21172 // the jump we generated, then we have to swap the operands for the
21173 // PHI that is going to be generated.
21174 if (MIIt->getOperand(3).getImm() == OppCC)
21175 std::swap(Op1Reg, Op2Reg);
21177 if (RegRewriteTable.find(Op1Reg) != RegRewriteTable.end())
21178 Op1Reg = RegRewriteTable[Op1Reg].first;
21180 if (RegRewriteTable.find(Op2Reg) != RegRewriteTable.end())
21181 Op2Reg = RegRewriteTable[Op2Reg].second;
21183 MIB = BuildMI(*sinkMBB, SinkInsertionPoint, DL,
21184 TII->get(X86::PHI), DestReg)
21185 .addReg(Op1Reg).addMBB(copy0MBB)
21186 .addReg(Op2Reg).addMBB(thisMBB);
21188 // Add this PHI to the rewrite table.
21189 RegRewriteTable[DestReg] = std::make_pair(Op1Reg, Op2Reg);
21192 // If we have a cascaded CMOV, the second Jcc provides the same incoming
21193 // value as the first Jcc (the True operand of the SELECT_CC/CMOV nodes).
21194 if (CascadedCMOV) {
21195 MIB.addReg(MI->getOperand(2).getReg()).addMBB(jcc1MBB);
21196 // Copy the PHI result to the register defined by the second CMOV.
21197 BuildMI(*sinkMBB, std::next(MachineBasicBlock::iterator(MIB.getInstr())),
21198 DL, TII->get(TargetOpcode::COPY),
21199 CascadedCMOV->getOperand(0).getReg())
21200 .addReg(MI->getOperand(0).getReg());
21201 CascadedCMOV->eraseFromParent();
21204 // Now remove the CMOV(s).
21205 for (MachineBasicBlock::iterator MIIt = MIItBegin; MIIt != MIItEnd; )
21206 (MIIt++)->eraseFromParent();
21211 MachineBasicBlock *
21212 X86TargetLowering::EmitLoweredAtomicFP(MachineInstr *MI,
21213 MachineBasicBlock *BB) const {
21214 // Combine the following atomic floating-point modification pattern:
21215 // a.store(reg OP a.load(acquire), release)
21216 // Transform them into:
21217 // OPss (%gpr), %xmm
21218 // movss %xmm, (%gpr)
21219 // Or sd equivalent for 64-bit operations.
21221 switch (MI->getOpcode()) {
21222 default: llvm_unreachable("unexpected instr type for EmitLoweredAtomicFP");
21223 case X86::RELEASE_FADD32mr: MOp = X86::MOVSSmr; FOp = X86::ADDSSrm; break;
21224 case X86::RELEASE_FADD64mr: MOp = X86::MOVSDmr; FOp = X86::ADDSDrm; break;
21226 const X86InstrInfo *TII = Subtarget->getInstrInfo();
21227 DebugLoc DL = MI->getDebugLoc();
21228 MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
21229 MachineOperand MSrc = MI->getOperand(0);
21230 unsigned VSrc = MI->getOperand(5).getReg();
21231 const MachineOperand &Disp = MI->getOperand(3);
21232 MachineOperand ZeroDisp = MachineOperand::CreateImm(0);
21233 bool hasDisp = Disp.isGlobal() || Disp.isImm();
21234 if (hasDisp && MSrc.isReg())
21235 MSrc.setIsKill(false);
21236 MachineInstrBuilder MIM = BuildMI(*BB, MI, DL, TII->get(MOp))
21237 .addOperand(/*Base=*/MSrc)
21238 .addImm(/*Scale=*/1)
21239 .addReg(/*Index=*/0)
21240 .addDisp(hasDisp ? Disp : ZeroDisp, /*off=*/0)
21242 MachineInstr *MIO = BuildMI(*BB, (MachineInstr *)MIM, DL, TII->get(FOp),
21243 MRI.createVirtualRegister(MRI.getRegClass(VSrc)))
21245 .addOperand(/*Base=*/MSrc)
21246 .addImm(/*Scale=*/1)
21247 .addReg(/*Index=*/0)
21248 .addDisp(hasDisp ? Disp : ZeroDisp, /*off=*/0)
21249 .addReg(/*Segment=*/0);
21250 MIM.addReg(MIO->getOperand(0).getReg(), RegState::Kill);
21251 MI->eraseFromParent(); // The pseudo instruction is gone now.
21255 MachineBasicBlock *
21256 X86TargetLowering::EmitLoweredSegAlloca(MachineInstr *MI,
21257 MachineBasicBlock *BB) const {
21258 MachineFunction *MF = BB->getParent();
21259 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
21260 DebugLoc DL = MI->getDebugLoc();
21261 const BasicBlock *LLVM_BB = BB->getBasicBlock();
21263 assert(MF->shouldSplitStack());
21265 const bool Is64Bit = Subtarget->is64Bit();
21266 const bool IsLP64 = Subtarget->isTarget64BitLP64();
21268 const unsigned TlsReg = Is64Bit ? X86::FS : X86::GS;
21269 const unsigned TlsOffset = IsLP64 ? 0x70 : Is64Bit ? 0x40 : 0x30;
21272 // ... [Till the alloca]
21273 // If stacklet is not large enough, jump to mallocMBB
21276 // Allocate by subtracting from RSP
21277 // Jump to continueMBB
21280 // Allocate by call to runtime
21284 // [rest of original BB]
21287 MachineBasicBlock *mallocMBB = MF->CreateMachineBasicBlock(LLVM_BB);
21288 MachineBasicBlock *bumpMBB = MF->CreateMachineBasicBlock(LLVM_BB);
21289 MachineBasicBlock *continueMBB = MF->CreateMachineBasicBlock(LLVM_BB);
21291 MachineRegisterInfo &MRI = MF->getRegInfo();
21292 const TargetRegisterClass *AddrRegClass =
21293 getRegClassFor(getPointerTy(MF->getDataLayout()));
21295 unsigned mallocPtrVReg = MRI.createVirtualRegister(AddrRegClass),
21296 bumpSPPtrVReg = MRI.createVirtualRegister(AddrRegClass),
21297 tmpSPVReg = MRI.createVirtualRegister(AddrRegClass),
21298 SPLimitVReg = MRI.createVirtualRegister(AddrRegClass),
21299 sizeVReg = MI->getOperand(1).getReg(),
21300 physSPReg = IsLP64 || Subtarget->isTargetNaCl64() ? X86::RSP : X86::ESP;
21302 MachineFunction::iterator MBBIter = ++BB->getIterator();
21304 MF->insert(MBBIter, bumpMBB);
21305 MF->insert(MBBIter, mallocMBB);
21306 MF->insert(MBBIter, continueMBB);
21308 continueMBB->splice(continueMBB->begin(), BB,
21309 std::next(MachineBasicBlock::iterator(MI)), BB->end());
21310 continueMBB->transferSuccessorsAndUpdatePHIs(BB);
21312 // Add code to the main basic block to check if the stack limit has been hit,
21313 // and if so, jump to mallocMBB otherwise to bumpMBB.
21314 BuildMI(BB, DL, TII->get(TargetOpcode::COPY), tmpSPVReg).addReg(physSPReg);
21315 BuildMI(BB, DL, TII->get(IsLP64 ? X86::SUB64rr:X86::SUB32rr), SPLimitVReg)
21316 .addReg(tmpSPVReg).addReg(sizeVReg);
21317 BuildMI(BB, DL, TII->get(IsLP64 ? X86::CMP64mr:X86::CMP32mr))
21318 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg)
21319 .addReg(SPLimitVReg);
21320 BuildMI(BB, DL, TII->get(X86::JG_1)).addMBB(mallocMBB);
21322 // bumpMBB simply decreases the stack pointer, since we know the current
21323 // stacklet has enough space.
21324 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), physSPReg)
21325 .addReg(SPLimitVReg);
21326 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), bumpSPPtrVReg)
21327 .addReg(SPLimitVReg);
21328 BuildMI(bumpMBB, DL, TII->get(X86::JMP_1)).addMBB(continueMBB);
21330 // Calls into a routine in libgcc to allocate more space from the heap.
21331 const uint32_t *RegMask =
21332 Subtarget->getRegisterInfo()->getCallPreservedMask(*MF, CallingConv::C);
21334 BuildMI(mallocMBB, DL, TII->get(X86::MOV64rr), X86::RDI)
21336 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
21337 .addExternalSymbol("__morestack_allocate_stack_space")
21338 .addRegMask(RegMask)
21339 .addReg(X86::RDI, RegState::Implicit)
21340 .addReg(X86::RAX, RegState::ImplicitDefine);
21341 } else if (Is64Bit) {
21342 BuildMI(mallocMBB, DL, TII->get(X86::MOV32rr), X86::EDI)
21344 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
21345 .addExternalSymbol("__morestack_allocate_stack_space")
21346 .addRegMask(RegMask)
21347 .addReg(X86::EDI, RegState::Implicit)
21348 .addReg(X86::EAX, RegState::ImplicitDefine);
21350 BuildMI(mallocMBB, DL, TII->get(X86::SUB32ri), physSPReg).addReg(physSPReg)
21352 BuildMI(mallocMBB, DL, TII->get(X86::PUSH32r)).addReg(sizeVReg);
21353 BuildMI(mallocMBB, DL, TII->get(X86::CALLpcrel32))
21354 .addExternalSymbol("__morestack_allocate_stack_space")
21355 .addRegMask(RegMask)
21356 .addReg(X86::EAX, RegState::ImplicitDefine);
21360 BuildMI(mallocMBB, DL, TII->get(X86::ADD32ri), physSPReg).addReg(physSPReg)
21363 BuildMI(mallocMBB, DL, TII->get(TargetOpcode::COPY), mallocPtrVReg)
21364 .addReg(IsLP64 ? X86::RAX : X86::EAX);
21365 BuildMI(mallocMBB, DL, TII->get(X86::JMP_1)).addMBB(continueMBB);
21367 // Set up the CFG correctly.
21368 BB->addSuccessor(bumpMBB);
21369 BB->addSuccessor(mallocMBB);
21370 mallocMBB->addSuccessor(continueMBB);
21371 bumpMBB->addSuccessor(continueMBB);
21373 // Take care of the PHI nodes.
21374 BuildMI(*continueMBB, continueMBB->begin(), DL, TII->get(X86::PHI),
21375 MI->getOperand(0).getReg())
21376 .addReg(mallocPtrVReg).addMBB(mallocMBB)
21377 .addReg(bumpSPPtrVReg).addMBB(bumpMBB);
21379 // Delete the original pseudo instruction.
21380 MI->eraseFromParent();
21383 return continueMBB;
21386 MachineBasicBlock *
21387 X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI,
21388 MachineBasicBlock *BB) const {
21389 assert(!Subtarget->isTargetMachO());
21390 DebugLoc DL = MI->getDebugLoc();
21391 MachineInstr *ResumeMI = Subtarget->getFrameLowering()->emitStackProbe(
21392 *BB->getParent(), *BB, MI, DL, false);
21393 MachineBasicBlock *ResumeBB = ResumeMI->getParent();
21394 MI->eraseFromParent(); // The pseudo instruction is gone now.
21398 MachineBasicBlock *
21399 X86TargetLowering::EmitLoweredCatchRet(MachineInstr *MI,
21400 MachineBasicBlock *BB) const {
21401 MachineFunction *MF = BB->getParent();
21402 const TargetInstrInfo &TII = *Subtarget->getInstrInfo();
21403 MachineBasicBlock *TargetMBB = MI->getOperand(0).getMBB();
21404 DebugLoc DL = MI->getDebugLoc();
21406 assert(!isAsynchronousEHPersonality(
21407 classifyEHPersonality(MF->getFunction()->getPersonalityFn())) &&
21408 "SEH does not use catchret!");
21410 // Only 32-bit EH needs to worry about manually restoring stack pointers.
21411 if (!Subtarget->is32Bit())
21414 // C++ EH creates a new target block to hold the restore code, and wires up
21415 // the new block to the return destination with a normal JMP_4.
21416 MachineBasicBlock *RestoreMBB =
21417 MF->CreateMachineBasicBlock(BB->getBasicBlock());
21418 assert(BB->succ_size() == 1);
21419 MF->insert(std::next(BB->getIterator()), RestoreMBB);
21420 RestoreMBB->transferSuccessorsAndUpdatePHIs(BB);
21421 BB->addSuccessor(RestoreMBB);
21422 MI->getOperand(0).setMBB(RestoreMBB);
21424 auto RestoreMBBI = RestoreMBB->begin();
21425 BuildMI(*RestoreMBB, RestoreMBBI, DL, TII.get(X86::EH_RESTORE));
21426 BuildMI(*RestoreMBB, RestoreMBBI, DL, TII.get(X86::JMP_4)).addMBB(TargetMBB);
21430 MachineBasicBlock *
21431 X86TargetLowering::EmitLoweredCatchPad(MachineInstr *MI,
21432 MachineBasicBlock *BB) const {
21433 MachineFunction *MF = BB->getParent();
21434 const Constant *PerFn = MF->getFunction()->getPersonalityFn();
21435 bool IsSEH = isAsynchronousEHPersonality(classifyEHPersonality(PerFn));
21436 // Only 32-bit SEH requires special handling for catchpad.
21437 if (IsSEH && Subtarget->is32Bit()) {
21438 const TargetInstrInfo &TII = *Subtarget->getInstrInfo();
21439 DebugLoc DL = MI->getDebugLoc();
21440 BuildMI(*BB, MI, DL, TII.get(X86::EH_RESTORE));
21442 MI->eraseFromParent();
21446 MachineBasicBlock *
21447 X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI,
21448 MachineBasicBlock *BB) const {
21449 // This is pretty easy. We're taking the value that we received from
21450 // our load from the relocation, sticking it in either RDI (x86-64)
21451 // or EAX and doing an indirect call. The return value will then
21452 // be in the normal return register.
21453 MachineFunction *F = BB->getParent();
21454 const X86InstrInfo *TII = Subtarget->getInstrInfo();
21455 DebugLoc DL = MI->getDebugLoc();
21457 assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?");
21458 assert(MI->getOperand(3).isGlobal() && "This should be a global");
21460 // Get a register mask for the lowered call.
21461 // FIXME: The 32-bit calls have non-standard calling conventions. Use a
21462 // proper register mask.
21463 const uint32_t *RegMask =
21464 Subtarget->is64Bit() ?
21465 Subtarget->getRegisterInfo()->getDarwinTLSCallPreservedMask() :
21466 Subtarget->getRegisterInfo()->getCallPreservedMask(*F, CallingConv::C);
21467 if (Subtarget->is64Bit()) {
21468 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
21469 TII->get(X86::MOV64rm), X86::RDI)
21471 .addImm(0).addReg(0)
21472 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
21473 MI->getOperand(3).getTargetFlags())
21475 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m));
21476 addDirectMem(MIB, X86::RDI);
21477 MIB.addReg(X86::RAX, RegState::ImplicitDefine).addRegMask(RegMask);
21478 } else if (F->getTarget().getRelocationModel() != Reloc::PIC_) {
21479 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
21480 TII->get(X86::MOV32rm), X86::EAX)
21482 .addImm(0).addReg(0)
21483 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
21484 MI->getOperand(3).getTargetFlags())
21486 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
21487 addDirectMem(MIB, X86::EAX);
21488 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
21490 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
21491 TII->get(X86::MOV32rm), X86::EAX)
21492 .addReg(TII->getGlobalBaseReg(F))
21493 .addImm(0).addReg(0)
21494 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
21495 MI->getOperand(3).getTargetFlags())
21497 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
21498 addDirectMem(MIB, X86::EAX);
21499 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
21502 MI->eraseFromParent(); // The pseudo instruction is gone now.
21506 MachineBasicBlock *
21507 X86TargetLowering::emitEHSjLjSetJmp(MachineInstr *MI,
21508 MachineBasicBlock *MBB) const {
21509 DebugLoc DL = MI->getDebugLoc();
21510 MachineFunction *MF = MBB->getParent();
21511 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
21512 MachineRegisterInfo &MRI = MF->getRegInfo();
21514 const BasicBlock *BB = MBB->getBasicBlock();
21515 MachineFunction::iterator I = ++MBB->getIterator();
21517 // Memory Reference
21518 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
21519 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
21522 unsigned MemOpndSlot = 0;
21524 unsigned CurOp = 0;
21526 DstReg = MI->getOperand(CurOp++).getReg();
21527 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
21528 assert(RC->hasType(MVT::i32) && "Invalid destination!");
21529 unsigned mainDstReg = MRI.createVirtualRegister(RC);
21530 unsigned restoreDstReg = MRI.createVirtualRegister(RC);
21532 MemOpndSlot = CurOp;
21534 MVT PVT = getPointerTy(MF->getDataLayout());
21535 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
21536 "Invalid Pointer Size!");
21538 // For v = setjmp(buf), we generate
21541 // buf[LabelOffset] = restoreMBB <-- takes address of restoreMBB
21542 // SjLjSetup restoreMBB
21548 // v = phi(main, restore)
21551 // if base pointer being used, load it from frame
21554 MachineBasicBlock *thisMBB = MBB;
21555 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
21556 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
21557 MachineBasicBlock *restoreMBB = MF->CreateMachineBasicBlock(BB);
21558 MF->insert(I, mainMBB);
21559 MF->insert(I, sinkMBB);
21560 MF->push_back(restoreMBB);
21561 restoreMBB->setHasAddressTaken();
21563 MachineInstrBuilder MIB;
21565 // Transfer the remainder of BB and its successor edges to sinkMBB.
21566 sinkMBB->splice(sinkMBB->begin(), MBB,
21567 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
21568 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
21571 unsigned PtrStoreOpc = 0;
21572 unsigned LabelReg = 0;
21573 const int64_t LabelOffset = 1 * PVT.getStoreSize();
21574 Reloc::Model RM = MF->getTarget().getRelocationModel();
21575 bool UseImmLabel = (MF->getTarget().getCodeModel() == CodeModel::Small) &&
21576 (RM == Reloc::Static || RM == Reloc::DynamicNoPIC);
21578 // Prepare IP either in reg or imm.
21579 if (!UseImmLabel) {
21580 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mr : X86::MOV32mr;
21581 const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
21582 LabelReg = MRI.createVirtualRegister(PtrRC);
21583 if (Subtarget->is64Bit()) {
21584 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA64r), LabelReg)
21588 .addMBB(restoreMBB)
21591 const X86InstrInfo *XII = static_cast<const X86InstrInfo*>(TII);
21592 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA32r), LabelReg)
21593 .addReg(XII->getGlobalBaseReg(MF))
21596 .addMBB(restoreMBB, Subtarget->ClassifyBlockAddressReference())
21600 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mi32 : X86::MOV32mi;
21602 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PtrStoreOpc));
21603 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
21604 if (i == X86::AddrDisp)
21605 MIB.addDisp(MI->getOperand(MemOpndSlot + i), LabelOffset);
21607 MIB.addOperand(MI->getOperand(MemOpndSlot + i));
21610 MIB.addReg(LabelReg);
21612 MIB.addMBB(restoreMBB);
21613 MIB.setMemRefs(MMOBegin, MMOEnd);
21615 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::EH_SjLj_Setup))
21616 .addMBB(restoreMBB);
21618 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
21619 MIB.addRegMask(RegInfo->getNoPreservedMask());
21620 thisMBB->addSuccessor(mainMBB);
21621 thisMBB->addSuccessor(restoreMBB);
21625 BuildMI(mainMBB, DL, TII->get(X86::MOV32r0), mainDstReg);
21626 mainMBB->addSuccessor(sinkMBB);
21629 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
21630 TII->get(X86::PHI), DstReg)
21631 .addReg(mainDstReg).addMBB(mainMBB)
21632 .addReg(restoreDstReg).addMBB(restoreMBB);
21635 if (RegInfo->hasBasePointer(*MF)) {
21636 const bool Uses64BitFramePtr =
21637 Subtarget->isTarget64BitLP64() || Subtarget->isTargetNaCl64();
21638 X86MachineFunctionInfo *X86FI = MF->getInfo<X86MachineFunctionInfo>();
21639 X86FI->setRestoreBasePointer(MF);
21640 unsigned FramePtr = RegInfo->getFrameRegister(*MF);
21641 unsigned BasePtr = RegInfo->getBaseRegister();
21642 unsigned Opm = Uses64BitFramePtr ? X86::MOV64rm : X86::MOV32rm;
21643 addRegOffset(BuildMI(restoreMBB, DL, TII->get(Opm), BasePtr),
21644 FramePtr, true, X86FI->getRestoreBasePointerOffset())
21645 .setMIFlag(MachineInstr::FrameSetup);
21647 BuildMI(restoreMBB, DL, TII->get(X86::MOV32ri), restoreDstReg).addImm(1);
21648 BuildMI(restoreMBB, DL, TII->get(X86::JMP_1)).addMBB(sinkMBB);
21649 restoreMBB->addSuccessor(sinkMBB);
21651 MI->eraseFromParent();
21655 MachineBasicBlock *
21656 X86TargetLowering::emitEHSjLjLongJmp(MachineInstr *MI,
21657 MachineBasicBlock *MBB) const {
21658 DebugLoc DL = MI->getDebugLoc();
21659 MachineFunction *MF = MBB->getParent();
21660 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
21661 MachineRegisterInfo &MRI = MF->getRegInfo();
21663 // Memory Reference
21664 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
21665 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
21667 MVT PVT = getPointerTy(MF->getDataLayout());
21668 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
21669 "Invalid Pointer Size!");
21671 const TargetRegisterClass *RC =
21672 (PVT == MVT::i64) ? &X86::GR64RegClass : &X86::GR32RegClass;
21673 unsigned Tmp = MRI.createVirtualRegister(RC);
21674 // Since FP is only updated here but NOT referenced, it's treated as GPR.
21675 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
21676 unsigned FP = (PVT == MVT::i64) ? X86::RBP : X86::EBP;
21677 unsigned SP = RegInfo->getStackRegister();
21679 MachineInstrBuilder MIB;
21681 const int64_t LabelOffset = 1 * PVT.getStoreSize();
21682 const int64_t SPOffset = 2 * PVT.getStoreSize();
21684 unsigned PtrLoadOpc = (PVT == MVT::i64) ? X86::MOV64rm : X86::MOV32rm;
21685 unsigned IJmpOpc = (PVT == MVT::i64) ? X86::JMP64r : X86::JMP32r;
21688 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), FP);
21689 for (unsigned i = 0; i < X86::AddrNumOperands; ++i)
21690 MIB.addOperand(MI->getOperand(i));
21691 MIB.setMemRefs(MMOBegin, MMOEnd);
21693 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), Tmp);
21694 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
21695 if (i == X86::AddrDisp)
21696 MIB.addDisp(MI->getOperand(i), LabelOffset);
21698 MIB.addOperand(MI->getOperand(i));
21700 MIB.setMemRefs(MMOBegin, MMOEnd);
21702 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), SP);
21703 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
21704 if (i == X86::AddrDisp)
21705 MIB.addDisp(MI->getOperand(i), SPOffset);
21707 MIB.addOperand(MI->getOperand(i));
21709 MIB.setMemRefs(MMOBegin, MMOEnd);
21711 BuildMI(*MBB, MI, DL, TII->get(IJmpOpc)).addReg(Tmp);
21713 MI->eraseFromParent();
21717 // Replace 213-type (isel default) FMA3 instructions with 231-type for
21718 // accumulator loops. Writing back to the accumulator allows the coalescer
21719 // to remove extra copies in the loop.
21720 // FIXME: Do this on AVX512. We don't support 231 variants yet (PR23937).
21721 MachineBasicBlock *
21722 X86TargetLowering::emitFMA3Instr(MachineInstr *MI,
21723 MachineBasicBlock *MBB) const {
21724 MachineOperand &AddendOp = MI->getOperand(3);
21726 // Bail out early if the addend isn't a register - we can't switch these.
21727 if (!AddendOp.isReg())
21730 MachineFunction &MF = *MBB->getParent();
21731 MachineRegisterInfo &MRI = MF.getRegInfo();
21733 // Check whether the addend is defined by a PHI:
21734 assert(MRI.hasOneDef(AddendOp.getReg()) && "Multiple defs in SSA?");
21735 MachineInstr &AddendDef = *MRI.def_instr_begin(AddendOp.getReg());
21736 if (!AddendDef.isPHI())
21739 // Look for the following pattern:
21741 // %addend = phi [%entry, 0], [%loop, %result]
21743 // %result<tied1> = FMA213 %m2<tied0>, %m1, %addend
21747 // %addend = phi [%entry, 0], [%loop, %result]
21749 // %result<tied1> = FMA231 %addend<tied0>, %m1, %m2
21751 for (unsigned i = 1, e = AddendDef.getNumOperands(); i < e; i += 2) {
21752 assert(AddendDef.getOperand(i).isReg());
21753 MachineOperand PHISrcOp = AddendDef.getOperand(i);
21754 MachineInstr &PHISrcInst = *MRI.def_instr_begin(PHISrcOp.getReg());
21755 if (&PHISrcInst == MI) {
21756 // Found a matching instruction.
21757 unsigned NewFMAOpc = 0;
21758 switch (MI->getOpcode()) {
21759 case X86::VFMADDPDr213r: NewFMAOpc = X86::VFMADDPDr231r; break;
21760 case X86::VFMADDPSr213r: NewFMAOpc = X86::VFMADDPSr231r; break;
21761 case X86::VFMADDSDr213r: NewFMAOpc = X86::VFMADDSDr231r; break;
21762 case X86::VFMADDSSr213r: NewFMAOpc = X86::VFMADDSSr231r; break;
21763 case X86::VFMSUBPDr213r: NewFMAOpc = X86::VFMSUBPDr231r; break;
21764 case X86::VFMSUBPSr213r: NewFMAOpc = X86::VFMSUBPSr231r; break;
21765 case X86::VFMSUBSDr213r: NewFMAOpc = X86::VFMSUBSDr231r; break;
21766 case X86::VFMSUBSSr213r: NewFMAOpc = X86::VFMSUBSSr231r; break;
21767 case X86::VFNMADDPDr213r: NewFMAOpc = X86::VFNMADDPDr231r; break;
21768 case X86::VFNMADDPSr213r: NewFMAOpc = X86::VFNMADDPSr231r; break;
21769 case X86::VFNMADDSDr213r: NewFMAOpc = X86::VFNMADDSDr231r; break;
21770 case X86::VFNMADDSSr213r: NewFMAOpc = X86::VFNMADDSSr231r; break;
21771 case X86::VFNMSUBPDr213r: NewFMAOpc = X86::VFNMSUBPDr231r; break;
21772 case X86::VFNMSUBPSr213r: NewFMAOpc = X86::VFNMSUBPSr231r; break;
21773 case X86::VFNMSUBSDr213r: NewFMAOpc = X86::VFNMSUBSDr231r; break;
21774 case X86::VFNMSUBSSr213r: NewFMAOpc = X86::VFNMSUBSSr231r; break;
21775 case X86::VFMADDSUBPDr213r: NewFMAOpc = X86::VFMADDSUBPDr231r; break;
21776 case X86::VFMADDSUBPSr213r: NewFMAOpc = X86::VFMADDSUBPSr231r; break;
21777 case X86::VFMSUBADDPDr213r: NewFMAOpc = X86::VFMSUBADDPDr231r; break;
21778 case X86::VFMSUBADDPSr213r: NewFMAOpc = X86::VFMSUBADDPSr231r; break;
21780 case X86::VFMADDPDr213rY: NewFMAOpc = X86::VFMADDPDr231rY; break;
21781 case X86::VFMADDPSr213rY: NewFMAOpc = X86::VFMADDPSr231rY; break;
21782 case X86::VFMSUBPDr213rY: NewFMAOpc = X86::VFMSUBPDr231rY; break;
21783 case X86::VFMSUBPSr213rY: NewFMAOpc = X86::VFMSUBPSr231rY; break;
21784 case X86::VFNMADDPDr213rY: NewFMAOpc = X86::VFNMADDPDr231rY; break;
21785 case X86::VFNMADDPSr213rY: NewFMAOpc = X86::VFNMADDPSr231rY; break;
21786 case X86::VFNMSUBPDr213rY: NewFMAOpc = X86::VFNMSUBPDr231rY; break;
21787 case X86::VFNMSUBPSr213rY: NewFMAOpc = X86::VFNMSUBPSr231rY; break;
21788 case X86::VFMADDSUBPDr213rY: NewFMAOpc = X86::VFMADDSUBPDr231rY; break;
21789 case X86::VFMADDSUBPSr213rY: NewFMAOpc = X86::VFMADDSUBPSr231rY; break;
21790 case X86::VFMSUBADDPDr213rY: NewFMAOpc = X86::VFMSUBADDPDr231rY; break;
21791 case X86::VFMSUBADDPSr213rY: NewFMAOpc = X86::VFMSUBADDPSr231rY; break;
21792 default: llvm_unreachable("Unrecognized FMA variant.");
21795 const TargetInstrInfo &TII = *Subtarget->getInstrInfo();
21796 MachineInstrBuilder MIB =
21797 BuildMI(MF, MI->getDebugLoc(), TII.get(NewFMAOpc))
21798 .addOperand(MI->getOperand(0))
21799 .addOperand(MI->getOperand(3))
21800 .addOperand(MI->getOperand(2))
21801 .addOperand(MI->getOperand(1));
21802 MBB->insert(MachineBasicBlock::iterator(MI), MIB);
21803 MI->eraseFromParent();
21810 MachineBasicBlock *
21811 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
21812 MachineBasicBlock *BB) const {
21813 switch (MI->getOpcode()) {
21814 default: llvm_unreachable("Unexpected instr type to insert");
21815 case X86::TAILJMPd64:
21816 case X86::TAILJMPr64:
21817 case X86::TAILJMPm64:
21818 case X86::TAILJMPd64_REX:
21819 case X86::TAILJMPr64_REX:
21820 case X86::TAILJMPm64_REX:
21821 llvm_unreachable("TAILJMP64 would not be touched here.");
21822 case X86::TCRETURNdi64:
21823 case X86::TCRETURNri64:
21824 case X86::TCRETURNmi64:
21826 case X86::WIN_ALLOCA:
21827 return EmitLoweredWinAlloca(MI, BB);
21828 case X86::CATCHRET:
21829 return EmitLoweredCatchRet(MI, BB);
21830 case X86::CATCHPAD:
21831 return EmitLoweredCatchPad(MI, BB);
21832 case X86::SEG_ALLOCA_32:
21833 case X86::SEG_ALLOCA_64:
21834 return EmitLoweredSegAlloca(MI, BB);
21835 case X86::TLSCall_32:
21836 case X86::TLSCall_64:
21837 return EmitLoweredTLSCall(MI, BB);
21838 case X86::CMOV_FR32:
21839 case X86::CMOV_FR64:
21840 case X86::CMOV_GR8:
21841 case X86::CMOV_GR16:
21842 case X86::CMOV_GR32:
21843 case X86::CMOV_RFP32:
21844 case X86::CMOV_RFP64:
21845 case X86::CMOV_RFP80:
21846 case X86::CMOV_V2F64:
21847 case X86::CMOV_V2I64:
21848 case X86::CMOV_V4F32:
21849 case X86::CMOV_V4F64:
21850 case X86::CMOV_V4I64:
21851 case X86::CMOV_V16F32:
21852 case X86::CMOV_V8F32:
21853 case X86::CMOV_V8F64:
21854 case X86::CMOV_V8I64:
21855 case X86::CMOV_V8I1:
21856 case X86::CMOV_V16I1:
21857 case X86::CMOV_V32I1:
21858 case X86::CMOV_V64I1:
21859 return EmitLoweredSelect(MI, BB);
21861 case X86::RELEASE_FADD32mr:
21862 case X86::RELEASE_FADD64mr:
21863 return EmitLoweredAtomicFP(MI, BB);
21865 case X86::FP32_TO_INT16_IN_MEM:
21866 case X86::FP32_TO_INT32_IN_MEM:
21867 case X86::FP32_TO_INT64_IN_MEM:
21868 case X86::FP64_TO_INT16_IN_MEM:
21869 case X86::FP64_TO_INT32_IN_MEM:
21870 case X86::FP64_TO_INT64_IN_MEM:
21871 case X86::FP80_TO_INT16_IN_MEM:
21872 case X86::FP80_TO_INT32_IN_MEM:
21873 case X86::FP80_TO_INT64_IN_MEM: {
21874 MachineFunction *F = BB->getParent();
21875 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
21876 DebugLoc DL = MI->getDebugLoc();
21878 // Change the floating point control register to use "round towards zero"
21879 // mode when truncating to an integer value.
21880 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false);
21881 addFrameReference(BuildMI(*BB, MI, DL,
21882 TII->get(X86::FNSTCW16m)), CWFrameIdx);
21884 // Load the old value of the high byte of the control word...
21886 F->getRegInfo().createVirtualRegister(&X86::GR16RegClass);
21887 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW),
21890 // Set the high part to be round to zero...
21891 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
21894 // Reload the modified control word now...
21895 addFrameReference(BuildMI(*BB, MI, DL,
21896 TII->get(X86::FLDCW16m)), CWFrameIdx);
21898 // Restore the memory image of control word to original value
21899 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
21902 // Get the X86 opcode to use.
21904 switch (MI->getOpcode()) {
21905 default: llvm_unreachable("illegal opcode!");
21906 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
21907 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
21908 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
21909 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
21910 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
21911 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
21912 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
21913 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
21914 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
21918 MachineOperand &Op = MI->getOperand(0);
21920 AM.BaseType = X86AddressMode::RegBase;
21921 AM.Base.Reg = Op.getReg();
21923 AM.BaseType = X86AddressMode::FrameIndexBase;
21924 AM.Base.FrameIndex = Op.getIndex();
21926 Op = MI->getOperand(1);
21928 AM.Scale = Op.getImm();
21929 Op = MI->getOperand(2);
21931 AM.IndexReg = Op.getImm();
21932 Op = MI->getOperand(3);
21933 if (Op.isGlobal()) {
21934 AM.GV = Op.getGlobal();
21936 AM.Disp = Op.getImm();
21938 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM)
21939 .addReg(MI->getOperand(X86::AddrNumOperands).getReg());
21941 // Reload the original control word now.
21942 addFrameReference(BuildMI(*BB, MI, DL,
21943 TII->get(X86::FLDCW16m)), CWFrameIdx);
21945 MI->eraseFromParent(); // The pseudo instruction is gone now.
21948 // String/text processing lowering.
21949 case X86::PCMPISTRM128REG:
21950 case X86::VPCMPISTRM128REG:
21951 case X86::PCMPISTRM128MEM:
21952 case X86::VPCMPISTRM128MEM:
21953 case X86::PCMPESTRM128REG:
21954 case X86::VPCMPESTRM128REG:
21955 case X86::PCMPESTRM128MEM:
21956 case X86::VPCMPESTRM128MEM:
21957 assert(Subtarget->hasSSE42() &&
21958 "Target must have SSE4.2 or AVX features enabled");
21959 return EmitPCMPSTRM(MI, BB, Subtarget->getInstrInfo());
21961 // String/text processing lowering.
21962 case X86::PCMPISTRIREG:
21963 case X86::VPCMPISTRIREG:
21964 case X86::PCMPISTRIMEM:
21965 case X86::VPCMPISTRIMEM:
21966 case X86::PCMPESTRIREG:
21967 case X86::VPCMPESTRIREG:
21968 case X86::PCMPESTRIMEM:
21969 case X86::VPCMPESTRIMEM:
21970 assert(Subtarget->hasSSE42() &&
21971 "Target must have SSE4.2 or AVX features enabled");
21972 return EmitPCMPSTRI(MI, BB, Subtarget->getInstrInfo());
21974 // Thread synchronization.
21976 return EmitMonitor(MI, BB, Subtarget);
21980 return EmitXBegin(MI, BB, Subtarget->getInstrInfo());
21982 case X86::VASTART_SAVE_XMM_REGS:
21983 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
21985 case X86::VAARG_64:
21986 return EmitVAARG64WithCustomInserter(MI, BB);
21988 case X86::EH_SjLj_SetJmp32:
21989 case X86::EH_SjLj_SetJmp64:
21990 return emitEHSjLjSetJmp(MI, BB);
21992 case X86::EH_SjLj_LongJmp32:
21993 case X86::EH_SjLj_LongJmp64:
21994 return emitEHSjLjLongJmp(MI, BB);
21996 case TargetOpcode::STATEPOINT:
21997 // As an implementation detail, STATEPOINT shares the STACKMAP format at
21998 // this point in the process. We diverge later.
21999 return emitPatchPoint(MI, BB);
22001 case TargetOpcode::STACKMAP:
22002 case TargetOpcode::PATCHPOINT:
22003 return emitPatchPoint(MI, BB);
22005 case X86::VFMADDPDr213r:
22006 case X86::VFMADDPSr213r:
22007 case X86::VFMADDSDr213r:
22008 case X86::VFMADDSSr213r:
22009 case X86::VFMSUBPDr213r:
22010 case X86::VFMSUBPSr213r:
22011 case X86::VFMSUBSDr213r:
22012 case X86::VFMSUBSSr213r:
22013 case X86::VFNMADDPDr213r:
22014 case X86::VFNMADDPSr213r:
22015 case X86::VFNMADDSDr213r:
22016 case X86::VFNMADDSSr213r:
22017 case X86::VFNMSUBPDr213r:
22018 case X86::VFNMSUBPSr213r:
22019 case X86::VFNMSUBSDr213r:
22020 case X86::VFNMSUBSSr213r:
22021 case X86::VFMADDSUBPDr213r:
22022 case X86::VFMADDSUBPSr213r:
22023 case X86::VFMSUBADDPDr213r:
22024 case X86::VFMSUBADDPSr213r:
22025 case X86::VFMADDPDr213rY:
22026 case X86::VFMADDPSr213rY:
22027 case X86::VFMSUBPDr213rY:
22028 case X86::VFMSUBPSr213rY:
22029 case X86::VFNMADDPDr213rY:
22030 case X86::VFNMADDPSr213rY:
22031 case X86::VFNMSUBPDr213rY:
22032 case X86::VFNMSUBPSr213rY:
22033 case X86::VFMADDSUBPDr213rY:
22034 case X86::VFMADDSUBPSr213rY:
22035 case X86::VFMSUBADDPDr213rY:
22036 case X86::VFMSUBADDPSr213rY:
22037 return emitFMA3Instr(MI, BB);
22041 //===----------------------------------------------------------------------===//
22042 // X86 Optimization Hooks
22043 //===----------------------------------------------------------------------===//
22045 void X86TargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
22048 const SelectionDAG &DAG,
22049 unsigned Depth) const {
22050 unsigned BitWidth = KnownZero.getBitWidth();
22051 unsigned Opc = Op.getOpcode();
22052 assert((Opc >= ISD::BUILTIN_OP_END ||
22053 Opc == ISD::INTRINSIC_WO_CHAIN ||
22054 Opc == ISD::INTRINSIC_W_CHAIN ||
22055 Opc == ISD::INTRINSIC_VOID) &&
22056 "Should use MaskedValueIsZero if you don't know whether Op"
22057 " is a target node!");
22059 KnownZero = KnownOne = APInt(BitWidth, 0); // Don't know anything.
22073 // These nodes' second result is a boolean.
22074 if (Op.getResNo() == 0)
22077 case X86ISD::SETCC:
22078 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1);
22080 case ISD::INTRINSIC_WO_CHAIN: {
22081 unsigned IntId = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
22082 unsigned NumLoBits = 0;
22085 case Intrinsic::x86_sse_movmsk_ps:
22086 case Intrinsic::x86_avx_movmsk_ps_256:
22087 case Intrinsic::x86_sse2_movmsk_pd:
22088 case Intrinsic::x86_avx_movmsk_pd_256:
22089 case Intrinsic::x86_mmx_pmovmskb:
22090 case Intrinsic::x86_sse2_pmovmskb_128:
22091 case Intrinsic::x86_avx2_pmovmskb: {
22092 // High bits of movmskp{s|d}, pmovmskb are known zero.
22094 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
22095 case Intrinsic::x86_sse_movmsk_ps: NumLoBits = 4; break;
22096 case Intrinsic::x86_avx_movmsk_ps_256: NumLoBits = 8; break;
22097 case Intrinsic::x86_sse2_movmsk_pd: NumLoBits = 2; break;
22098 case Intrinsic::x86_avx_movmsk_pd_256: NumLoBits = 4; break;
22099 case Intrinsic::x86_mmx_pmovmskb: NumLoBits = 8; break;
22100 case Intrinsic::x86_sse2_pmovmskb_128: NumLoBits = 16; break;
22101 case Intrinsic::x86_avx2_pmovmskb: NumLoBits = 32; break;
22103 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - NumLoBits);
22112 unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(
22114 const SelectionDAG &,
22115 unsigned Depth) const {
22116 // SETCC_CARRY sets the dest to ~0 for true or 0 for false.
22117 if (Op.getOpcode() == X86ISD::SETCC_CARRY)
22118 return Op.getValueType().getScalarSizeInBits();
22124 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
22125 /// node is a GlobalAddress + offset.
22126 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
22127 const GlobalValue* &GA,
22128 int64_t &Offset) const {
22129 if (N->getOpcode() == X86ISD::Wrapper) {
22130 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
22131 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
22132 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
22136 return TargetLowering::isGAPlusOffset(N, GA, Offset);
22139 /// isShuffleHigh128VectorInsertLow - Checks whether the shuffle node is the
22140 /// same as extracting the high 128-bit part of 256-bit vector and then
22141 /// inserting the result into the low part of a new 256-bit vector
22142 static bool isShuffleHigh128VectorInsertLow(ShuffleVectorSDNode *SVOp) {
22143 EVT VT = SVOp->getValueType(0);
22144 unsigned NumElems = VT.getVectorNumElements();
22146 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
22147 for (unsigned i = 0, j = NumElems/2; i != NumElems/2; ++i, ++j)
22148 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
22149 SVOp->getMaskElt(j) >= 0)
22155 /// isShuffleLow128VectorInsertHigh - Checks whether the shuffle node is the
22156 /// same as extracting the low 128-bit part of 256-bit vector and then
22157 /// inserting the result into the high part of a new 256-bit vector
22158 static bool isShuffleLow128VectorInsertHigh(ShuffleVectorSDNode *SVOp) {
22159 EVT VT = SVOp->getValueType(0);
22160 unsigned NumElems = VT.getVectorNumElements();
22162 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
22163 for (unsigned i = NumElems/2, j = 0; i != NumElems; ++i, ++j)
22164 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
22165 SVOp->getMaskElt(j) >= 0)
22171 /// PerformShuffleCombine256 - Performs shuffle combines for 256-bit vectors.
22172 static SDValue PerformShuffleCombine256(SDNode *N, SelectionDAG &DAG,
22173 TargetLowering::DAGCombinerInfo &DCI,
22174 const X86Subtarget* Subtarget) {
22176 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
22177 SDValue V1 = SVOp->getOperand(0);
22178 SDValue V2 = SVOp->getOperand(1);
22179 EVT VT = SVOp->getValueType(0);
22180 unsigned NumElems = VT.getVectorNumElements();
22182 if (V1.getOpcode() == ISD::CONCAT_VECTORS &&
22183 V2.getOpcode() == ISD::CONCAT_VECTORS) {
22187 // V UNDEF BUILD_VECTOR UNDEF
22189 // CONCAT_VECTOR CONCAT_VECTOR
22192 // RESULT: V + zero extended
22194 if (V2.getOperand(0).getOpcode() != ISD::BUILD_VECTOR ||
22195 V2.getOperand(1).getOpcode() != ISD::UNDEF ||
22196 V1.getOperand(1).getOpcode() != ISD::UNDEF)
22199 if (!ISD::isBuildVectorAllZeros(V2.getOperand(0).getNode()))
22202 // To match the shuffle mask, the first half of the mask should
22203 // be exactly the first vector, and all the rest a splat with the
22204 // first element of the second one.
22205 for (unsigned i = 0; i != NumElems/2; ++i)
22206 if (!isUndefOrEqual(SVOp->getMaskElt(i), i) ||
22207 !isUndefOrEqual(SVOp->getMaskElt(i+NumElems/2), NumElems))
22210 // If V1 is coming from a vector load then just fold to a VZEXT_LOAD.
22211 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(V1.getOperand(0))) {
22212 if (Ld->hasNUsesOfValue(1, 0)) {
22213 SDVTList Tys = DAG.getVTList(MVT::v4i64, MVT::Other);
22214 SDValue Ops[] = { Ld->getChain(), Ld->getBasePtr() };
22216 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops,
22218 Ld->getPointerInfo(),
22219 Ld->getAlignment(),
22220 false/*isVolatile*/, true/*ReadMem*/,
22221 false/*WriteMem*/);
22223 // Make sure the newly-created LOAD is in the same position as Ld in
22224 // terms of dependency. We create a TokenFactor for Ld and ResNode,
22225 // and update uses of Ld's output chain to use the TokenFactor.
22226 if (Ld->hasAnyUseOfValue(1)) {
22227 SDValue NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
22228 SDValue(Ld, 1), SDValue(ResNode.getNode(), 1));
22229 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), NewChain);
22230 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(Ld, 1),
22231 SDValue(ResNode.getNode(), 1));
22234 return DAG.getBitcast(VT, ResNode);
22238 // Emit a zeroed vector and insert the desired subvector on its
22240 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
22241 SDValue InsV = Insert128BitVector(Zeros, V1.getOperand(0), 0, DAG, dl);
22242 return DCI.CombineTo(N, InsV);
22245 //===--------------------------------------------------------------------===//
22246 // Combine some shuffles into subvector extracts and inserts:
22249 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
22250 if (isShuffleHigh128VectorInsertLow(SVOp)) {
22251 SDValue V = Extract128BitVector(V1, NumElems/2, DAG, dl);
22252 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, 0, DAG, dl);
22253 return DCI.CombineTo(N, InsV);
22256 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
22257 if (isShuffleLow128VectorInsertHigh(SVOp)) {
22258 SDValue V = Extract128BitVector(V1, 0, DAG, dl);
22259 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, NumElems/2, DAG, dl);
22260 return DCI.CombineTo(N, InsV);
22266 /// \brief Combine an arbitrary chain of shuffles into a single instruction if
22269 /// This is the leaf of the recursive combinine below. When we have found some
22270 /// chain of single-use x86 shuffle instructions and accumulated the combined
22271 /// shuffle mask represented by them, this will try to pattern match that mask
22272 /// into either a single instruction if there is a special purpose instruction
22273 /// for this operation, or into a PSHUFB instruction which is a fully general
22274 /// instruction but should only be used to replace chains over a certain depth.
22275 static bool combineX86ShuffleChain(SDValue Op, SDValue Root, ArrayRef<int> Mask,
22276 int Depth, bool HasPSHUFB, SelectionDAG &DAG,
22277 TargetLowering::DAGCombinerInfo &DCI,
22278 const X86Subtarget *Subtarget) {
22279 assert(!Mask.empty() && "Cannot combine an empty shuffle mask!");
22281 // Find the operand that enters the chain. Note that multiple uses are OK
22282 // here, we're not going to remove the operand we find.
22283 SDValue Input = Op.getOperand(0);
22284 while (Input.getOpcode() == ISD::BITCAST)
22285 Input = Input.getOperand(0);
22287 MVT VT = Input.getSimpleValueType();
22288 MVT RootVT = Root.getSimpleValueType();
22291 if (Mask.size() == 1) {
22292 int Index = Mask[0];
22293 assert((Index >= 0 || Index == SM_SentinelUndef ||
22294 Index == SM_SentinelZero) &&
22295 "Invalid shuffle index found!");
22297 // We may end up with an accumulated mask of size 1 as a result of
22298 // widening of shuffle operands (see function canWidenShuffleElements).
22299 // If the only shuffle index is equal to SM_SentinelZero then propagate
22300 // a zero vector. Otherwise, the combine shuffle mask is a no-op shuffle
22301 // mask, and therefore the entire chain of shuffles can be folded away.
22302 if (Index == SM_SentinelZero)
22303 DCI.CombineTo(Root.getNode(), getZeroVector(RootVT, Subtarget, DAG, DL));
22305 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Input),
22310 // Use the float domain if the operand type is a floating point type.
22311 bool FloatDomain = VT.isFloatingPoint();
22313 // For floating point shuffles, we don't have free copies in the shuffle
22314 // instructions or the ability to load as part of the instruction, so
22315 // canonicalize their shuffles to UNPCK or MOV variants.
22317 // Note that even with AVX we prefer the PSHUFD form of shuffle for integer
22318 // vectors because it can have a load folded into it that UNPCK cannot. This
22319 // doesn't preclude something switching to the shorter encoding post-RA.
22321 // FIXME: Should teach these routines about AVX vector widths.
22322 if (FloatDomain && VT.is128BitVector()) {
22323 if (Mask.equals({0, 0}) || Mask.equals({1, 1})) {
22324 bool Lo = Mask.equals({0, 0});
22327 // Check if we have SSE3 which will let us use MOVDDUP. That instruction
22328 // is no slower than UNPCKLPD but has the option to fold the input operand
22329 // into even an unaligned memory load.
22330 if (Lo && Subtarget->hasSSE3()) {
22331 Shuffle = X86ISD::MOVDDUP;
22332 ShuffleVT = MVT::v2f64;
22334 // We have MOVLHPS and MOVHLPS throughout SSE and they encode smaller
22335 // than the UNPCK variants.
22336 Shuffle = Lo ? X86ISD::MOVLHPS : X86ISD::MOVHLPS;
22337 ShuffleVT = MVT::v4f32;
22339 if (Depth == 1 && Root->getOpcode() == Shuffle)
22340 return false; // Nothing to do!
22341 Op = DAG.getBitcast(ShuffleVT, Input);
22342 DCI.AddToWorklist(Op.getNode());
22343 if (Shuffle == X86ISD::MOVDDUP)
22344 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op);
22346 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
22347 DCI.AddToWorklist(Op.getNode());
22348 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Op),
22352 if (Subtarget->hasSSE3() &&
22353 (Mask.equals({0, 0, 2, 2}) || Mask.equals({1, 1, 3, 3}))) {
22354 bool Lo = Mask.equals({0, 0, 2, 2});
22355 unsigned Shuffle = Lo ? X86ISD::MOVSLDUP : X86ISD::MOVSHDUP;
22356 MVT ShuffleVT = MVT::v4f32;
22357 if (Depth == 1 && Root->getOpcode() == Shuffle)
22358 return false; // Nothing to do!
22359 Op = DAG.getBitcast(ShuffleVT, Input);
22360 DCI.AddToWorklist(Op.getNode());
22361 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op);
22362 DCI.AddToWorklist(Op.getNode());
22363 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Op),
22367 if (Mask.equals({0, 0, 1, 1}) || Mask.equals({2, 2, 3, 3})) {
22368 bool Lo = Mask.equals({0, 0, 1, 1});
22369 unsigned Shuffle = Lo ? X86ISD::UNPCKL : X86ISD::UNPCKH;
22370 MVT ShuffleVT = MVT::v4f32;
22371 if (Depth == 1 && Root->getOpcode() == Shuffle)
22372 return false; // Nothing to do!
22373 Op = DAG.getBitcast(ShuffleVT, Input);
22374 DCI.AddToWorklist(Op.getNode());
22375 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
22376 DCI.AddToWorklist(Op.getNode());
22377 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Op),
22383 // We always canonicalize the 8 x i16 and 16 x i8 shuffles into their UNPCK
22384 // variants as none of these have single-instruction variants that are
22385 // superior to the UNPCK formulation.
22386 if (!FloatDomain && VT.is128BitVector() &&
22387 (Mask.equals({0, 0, 1, 1, 2, 2, 3, 3}) ||
22388 Mask.equals({4, 4, 5, 5, 6, 6, 7, 7}) ||
22389 Mask.equals({0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7}) ||
22391 {8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}))) {
22392 bool Lo = Mask[0] == 0;
22393 unsigned Shuffle = Lo ? X86ISD::UNPCKL : X86ISD::UNPCKH;
22394 if (Depth == 1 && Root->getOpcode() == Shuffle)
22395 return false; // Nothing to do!
22397 switch (Mask.size()) {
22399 ShuffleVT = MVT::v8i16;
22402 ShuffleVT = MVT::v16i8;
22405 llvm_unreachable("Impossible mask size!");
22407 Op = DAG.getBitcast(ShuffleVT, Input);
22408 DCI.AddToWorklist(Op.getNode());
22409 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
22410 DCI.AddToWorklist(Op.getNode());
22411 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Op),
22416 // Don't try to re-form single instruction chains under any circumstances now
22417 // that we've done encoding canonicalization for them.
22421 // If we have 3 or more shuffle instructions or a chain involving PSHUFB, we
22422 // can replace them with a single PSHUFB instruction profitably. Intel's
22423 // manuals suggest only using PSHUFB if doing so replacing 5 instructions, but
22424 // in practice PSHUFB tends to be *very* fast so we're more aggressive.
22425 if ((Depth >= 3 || HasPSHUFB) && Subtarget->hasSSSE3()) {
22426 SmallVector<SDValue, 16> PSHUFBMask;
22427 int NumBytes = VT.getSizeInBits() / 8;
22428 int Ratio = NumBytes / Mask.size();
22429 for (int i = 0; i < NumBytes; ++i) {
22430 if (Mask[i / Ratio] == SM_SentinelUndef) {
22431 PSHUFBMask.push_back(DAG.getUNDEF(MVT::i8));
22434 int M = Mask[i / Ratio] != SM_SentinelZero
22435 ? Ratio * Mask[i / Ratio] + i % Ratio
22437 PSHUFBMask.push_back(DAG.getConstant(M, DL, MVT::i8));
22439 MVT ByteVT = MVT::getVectorVT(MVT::i8, NumBytes);
22440 Op = DAG.getBitcast(ByteVT, Input);
22441 DCI.AddToWorklist(Op.getNode());
22442 SDValue PSHUFBMaskOp =
22443 DAG.getNode(ISD::BUILD_VECTOR, DL, ByteVT, PSHUFBMask);
22444 DCI.AddToWorklist(PSHUFBMaskOp.getNode());
22445 Op = DAG.getNode(X86ISD::PSHUFB, DL, ByteVT, Op, PSHUFBMaskOp);
22446 DCI.AddToWorklist(Op.getNode());
22447 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Op),
22452 // Failed to find any combines.
22456 /// \brief Fully generic combining of x86 shuffle instructions.
22458 /// This should be the last combine run over the x86 shuffle instructions. Once
22459 /// they have been fully optimized, this will recursively consider all chains
22460 /// of single-use shuffle instructions, build a generic model of the cumulative
22461 /// shuffle operation, and check for simpler instructions which implement this
22462 /// operation. We use this primarily for two purposes:
22464 /// 1) Collapse generic shuffles to specialized single instructions when
22465 /// equivalent. In most cases, this is just an encoding size win, but
22466 /// sometimes we will collapse multiple generic shuffles into a single
22467 /// special-purpose shuffle.
22468 /// 2) Look for sequences of shuffle instructions with 3 or more total
22469 /// instructions, and replace them with the slightly more expensive SSSE3
22470 /// PSHUFB instruction if available. We do this as the last combining step
22471 /// to ensure we avoid using PSHUFB if we can implement the shuffle with
22472 /// a suitable short sequence of other instructions. The PHUFB will either
22473 /// use a register or have to read from memory and so is slightly (but only
22474 /// slightly) more expensive than the other shuffle instructions.
22476 /// Because this is inherently a quadratic operation (for each shuffle in
22477 /// a chain, we recurse up the chain), the depth is limited to 8 instructions.
22478 /// This should never be an issue in practice as the shuffle lowering doesn't
22479 /// produce sequences of more than 8 instructions.
22481 /// FIXME: We will currently miss some cases where the redundant shuffling
22482 /// would simplify under the threshold for PSHUFB formation because of
22483 /// combine-ordering. To fix this, we should do the redundant instruction
22484 /// combining in this recursive walk.
22485 static bool combineX86ShufflesRecursively(SDValue Op, SDValue Root,
22486 ArrayRef<int> RootMask,
22487 int Depth, bool HasPSHUFB,
22489 TargetLowering::DAGCombinerInfo &DCI,
22490 const X86Subtarget *Subtarget) {
22491 // Bound the depth of our recursive combine because this is ultimately
22492 // quadratic in nature.
22496 // Directly rip through bitcasts to find the underlying operand.
22497 while (Op.getOpcode() == ISD::BITCAST && Op.getOperand(0).hasOneUse())
22498 Op = Op.getOperand(0);
22500 MVT VT = Op.getSimpleValueType();
22501 if (!VT.isVector())
22502 return false; // Bail if we hit a non-vector.
22504 assert(Root.getSimpleValueType().isVector() &&
22505 "Shuffles operate on vector types!");
22506 assert(VT.getSizeInBits() == Root.getSimpleValueType().getSizeInBits() &&
22507 "Can only combine shuffles of the same vector register size.");
22509 if (!isTargetShuffle(Op.getOpcode()))
22511 SmallVector<int, 16> OpMask;
22513 bool HaveMask = getTargetShuffleMask(Op.getNode(), VT, OpMask, IsUnary);
22514 // We only can combine unary shuffles which we can decode the mask for.
22515 if (!HaveMask || !IsUnary)
22518 assert(VT.getVectorNumElements() == OpMask.size() &&
22519 "Different mask size from vector size!");
22520 assert(((RootMask.size() > OpMask.size() &&
22521 RootMask.size() % OpMask.size() == 0) ||
22522 (OpMask.size() > RootMask.size() &&
22523 OpMask.size() % RootMask.size() == 0) ||
22524 OpMask.size() == RootMask.size()) &&
22525 "The smaller number of elements must divide the larger.");
22526 int RootRatio = std::max<int>(1, OpMask.size() / RootMask.size());
22527 int OpRatio = std::max<int>(1, RootMask.size() / OpMask.size());
22528 assert(((RootRatio == 1 && OpRatio == 1) ||
22529 (RootRatio == 1) != (OpRatio == 1)) &&
22530 "Must not have a ratio for both incoming and op masks!");
22532 SmallVector<int, 16> Mask;
22533 Mask.reserve(std::max(OpMask.size(), RootMask.size()));
22535 // Merge this shuffle operation's mask into our accumulated mask. Note that
22536 // this shuffle's mask will be the first applied to the input, followed by the
22537 // root mask to get us all the way to the root value arrangement. The reason
22538 // for this order is that we are recursing up the operation chain.
22539 for (int i = 0, e = std::max(OpMask.size(), RootMask.size()); i < e; ++i) {
22540 int RootIdx = i / RootRatio;
22541 if (RootMask[RootIdx] < 0) {
22542 // This is a zero or undef lane, we're done.
22543 Mask.push_back(RootMask[RootIdx]);
22547 int RootMaskedIdx = RootMask[RootIdx] * RootRatio + i % RootRatio;
22548 int OpIdx = RootMaskedIdx / OpRatio;
22549 if (OpMask[OpIdx] < 0) {
22550 // The incoming lanes are zero or undef, it doesn't matter which ones we
22552 Mask.push_back(OpMask[OpIdx]);
22556 // Ok, we have non-zero lanes, map them through.
22557 Mask.push_back(OpMask[OpIdx] * OpRatio +
22558 RootMaskedIdx % OpRatio);
22561 // See if we can recurse into the operand to combine more things.
22562 switch (Op.getOpcode()) {
22563 case X86ISD::PSHUFB:
22565 case X86ISD::PSHUFD:
22566 case X86ISD::PSHUFHW:
22567 case X86ISD::PSHUFLW:
22568 if (Op.getOperand(0).hasOneUse() &&
22569 combineX86ShufflesRecursively(Op.getOperand(0), Root, Mask, Depth + 1,
22570 HasPSHUFB, DAG, DCI, Subtarget))
22574 case X86ISD::UNPCKL:
22575 case X86ISD::UNPCKH:
22576 assert(Op.getOperand(0) == Op.getOperand(1) &&
22577 "We only combine unary shuffles!");
22578 // We can't check for single use, we have to check that this shuffle is the
22580 if (Op->isOnlyUserOf(Op.getOperand(0).getNode()) &&
22581 combineX86ShufflesRecursively(Op.getOperand(0), Root, Mask, Depth + 1,
22582 HasPSHUFB, DAG, DCI, Subtarget))
22587 // Minor canonicalization of the accumulated shuffle mask to make it easier
22588 // to match below. All this does is detect masks with squential pairs of
22589 // elements, and shrink them to the half-width mask. It does this in a loop
22590 // so it will reduce the size of the mask to the minimal width mask which
22591 // performs an equivalent shuffle.
22592 SmallVector<int, 16> WidenedMask;
22593 while (Mask.size() > 1 && canWidenShuffleElements(Mask, WidenedMask)) {
22594 Mask = std::move(WidenedMask);
22595 WidenedMask.clear();
22598 return combineX86ShuffleChain(Op, Root, Mask, Depth, HasPSHUFB, DAG, DCI,
22602 /// \brief Get the PSHUF-style mask from PSHUF node.
22604 /// This is a very minor wrapper around getTargetShuffleMask to easy forming v4
22605 /// PSHUF-style masks that can be reused with such instructions.
22606 static SmallVector<int, 4> getPSHUFShuffleMask(SDValue N) {
22607 MVT VT = N.getSimpleValueType();
22608 SmallVector<int, 4> Mask;
22610 bool HaveMask = getTargetShuffleMask(N.getNode(), VT, Mask, IsUnary);
22614 // If we have more than 128-bits, only the low 128-bits of shuffle mask
22615 // matter. Check that the upper masks are repeats and remove them.
22616 if (VT.getSizeInBits() > 128) {
22617 int LaneElts = 128 / VT.getScalarSizeInBits();
22619 for (int i = 1, NumLanes = VT.getSizeInBits() / 128; i < NumLanes; ++i)
22620 for (int j = 0; j < LaneElts; ++j)
22621 assert(Mask[j] == Mask[i * LaneElts + j] - (LaneElts * i) &&
22622 "Mask doesn't repeat in high 128-bit lanes!");
22624 Mask.resize(LaneElts);
22627 switch (N.getOpcode()) {
22628 case X86ISD::PSHUFD:
22630 case X86ISD::PSHUFLW:
22633 case X86ISD::PSHUFHW:
22634 Mask.erase(Mask.begin(), Mask.begin() + 4);
22635 for (int &M : Mask)
22639 llvm_unreachable("No valid shuffle instruction found!");
22643 /// \brief Search for a combinable shuffle across a chain ending in pshufd.
22645 /// We walk up the chain and look for a combinable shuffle, skipping over
22646 /// shuffles that we could hoist this shuffle's transformation past without
22647 /// altering anything.
22649 combineRedundantDWordShuffle(SDValue N, MutableArrayRef<int> Mask,
22651 TargetLowering::DAGCombinerInfo &DCI) {
22652 assert(N.getOpcode() == X86ISD::PSHUFD &&
22653 "Called with something other than an x86 128-bit half shuffle!");
22656 // Walk up a single-use chain looking for a combinable shuffle. Keep a stack
22657 // of the shuffles in the chain so that we can form a fresh chain to replace
22659 SmallVector<SDValue, 8> Chain;
22660 SDValue V = N.getOperand(0);
22661 for (; V.hasOneUse(); V = V.getOperand(0)) {
22662 switch (V.getOpcode()) {
22664 return SDValue(); // Nothing combined!
22667 // Skip bitcasts as we always know the type for the target specific
22671 case X86ISD::PSHUFD:
22672 // Found another dword shuffle.
22675 case X86ISD::PSHUFLW:
22676 // Check that the low words (being shuffled) are the identity in the
22677 // dword shuffle, and the high words are self-contained.
22678 if (Mask[0] != 0 || Mask[1] != 1 ||
22679 !(Mask[2] >= 2 && Mask[2] < 4 && Mask[3] >= 2 && Mask[3] < 4))
22682 Chain.push_back(V);
22685 case X86ISD::PSHUFHW:
22686 // Check that the high words (being shuffled) are the identity in the
22687 // dword shuffle, and the low words are self-contained.
22688 if (Mask[2] != 2 || Mask[3] != 3 ||
22689 !(Mask[0] >= 0 && Mask[0] < 2 && Mask[1] >= 0 && Mask[1] < 2))
22692 Chain.push_back(V);
22695 case X86ISD::UNPCKL:
22696 case X86ISD::UNPCKH:
22697 // For either i8 -> i16 or i16 -> i32 unpacks, we can combine a dword
22698 // shuffle into a preceding word shuffle.
22699 if (V.getSimpleValueType().getVectorElementType() != MVT::i8 &&
22700 V.getSimpleValueType().getVectorElementType() != MVT::i16)
22703 // Search for a half-shuffle which we can combine with.
22704 unsigned CombineOp =
22705 V.getOpcode() == X86ISD::UNPCKL ? X86ISD::PSHUFLW : X86ISD::PSHUFHW;
22706 if (V.getOperand(0) != V.getOperand(1) ||
22707 !V->isOnlyUserOf(V.getOperand(0).getNode()))
22709 Chain.push_back(V);
22710 V = V.getOperand(0);
22712 switch (V.getOpcode()) {
22714 return SDValue(); // Nothing to combine.
22716 case X86ISD::PSHUFLW:
22717 case X86ISD::PSHUFHW:
22718 if (V.getOpcode() == CombineOp)
22721 Chain.push_back(V);
22725 V = V.getOperand(0);
22729 } while (V.hasOneUse());
22732 // Break out of the loop if we break out of the switch.
22736 if (!V.hasOneUse())
22737 // We fell out of the loop without finding a viable combining instruction.
22740 // Merge this node's mask and our incoming mask.
22741 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
22742 for (int &M : Mask)
22744 V = DAG.getNode(V.getOpcode(), DL, V.getValueType(), V.getOperand(0),
22745 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
22747 // Rebuild the chain around this new shuffle.
22748 while (!Chain.empty()) {
22749 SDValue W = Chain.pop_back_val();
22751 if (V.getValueType() != W.getOperand(0).getValueType())
22752 V = DAG.getBitcast(W.getOperand(0).getValueType(), V);
22754 switch (W.getOpcode()) {
22756 llvm_unreachable("Only PSHUF and UNPCK instructions get here!");
22758 case X86ISD::UNPCKL:
22759 case X86ISD::UNPCKH:
22760 V = DAG.getNode(W.getOpcode(), DL, W.getValueType(), V, V);
22763 case X86ISD::PSHUFD:
22764 case X86ISD::PSHUFLW:
22765 case X86ISD::PSHUFHW:
22766 V = DAG.getNode(W.getOpcode(), DL, W.getValueType(), V, W.getOperand(1));
22770 if (V.getValueType() != N.getValueType())
22771 V = DAG.getBitcast(N.getValueType(), V);
22773 // Return the new chain to replace N.
22777 /// \brief Search for a combinable shuffle across a chain ending in pshuflw or
22780 /// We walk up the chain, skipping shuffles of the other half and looking
22781 /// through shuffles which switch halves trying to find a shuffle of the same
22782 /// pair of dwords.
22783 static bool combineRedundantHalfShuffle(SDValue N, MutableArrayRef<int> Mask,
22785 TargetLowering::DAGCombinerInfo &DCI) {
22787 (N.getOpcode() == X86ISD::PSHUFLW || N.getOpcode() == X86ISD::PSHUFHW) &&
22788 "Called with something other than an x86 128-bit half shuffle!");
22790 unsigned CombineOpcode = N.getOpcode();
22792 // Walk up a single-use chain looking for a combinable shuffle.
22793 SDValue V = N.getOperand(0);
22794 for (; V.hasOneUse(); V = V.getOperand(0)) {
22795 switch (V.getOpcode()) {
22797 return false; // Nothing combined!
22800 // Skip bitcasts as we always know the type for the target specific
22804 case X86ISD::PSHUFLW:
22805 case X86ISD::PSHUFHW:
22806 if (V.getOpcode() == CombineOpcode)
22809 // Other-half shuffles are no-ops.
22812 // Break out of the loop if we break out of the switch.
22816 if (!V.hasOneUse())
22817 // We fell out of the loop without finding a viable combining instruction.
22820 // Combine away the bottom node as its shuffle will be accumulated into
22821 // a preceding shuffle.
22822 DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
22824 // Record the old value.
22827 // Merge this node's mask and our incoming mask (adjusted to account for all
22828 // the pshufd instructions encountered).
22829 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
22830 for (int &M : Mask)
22832 V = DAG.getNode(V.getOpcode(), DL, MVT::v8i16, V.getOperand(0),
22833 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
22835 // Check that the shuffles didn't cancel each other out. If not, we need to
22836 // combine to the new one.
22838 // Replace the combinable shuffle with the combined one, updating all users
22839 // so that we re-evaluate the chain here.
22840 DCI.CombineTo(Old.getNode(), V, /*AddTo*/ true);
22845 /// \brief Try to combine x86 target specific shuffles.
22846 static SDValue PerformTargetShuffleCombine(SDValue N, SelectionDAG &DAG,
22847 TargetLowering::DAGCombinerInfo &DCI,
22848 const X86Subtarget *Subtarget) {
22850 MVT VT = N.getSimpleValueType();
22851 SmallVector<int, 4> Mask;
22853 switch (N.getOpcode()) {
22854 case X86ISD::PSHUFD:
22855 case X86ISD::PSHUFLW:
22856 case X86ISD::PSHUFHW:
22857 Mask = getPSHUFShuffleMask(N);
22858 assert(Mask.size() == 4);
22864 // Nuke no-op shuffles that show up after combining.
22865 if (isNoopShuffleMask(Mask))
22866 return DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
22868 // Look for simplifications involving one or two shuffle instructions.
22869 SDValue V = N.getOperand(0);
22870 switch (N.getOpcode()) {
22873 case X86ISD::PSHUFLW:
22874 case X86ISD::PSHUFHW:
22875 assert(VT.getVectorElementType() == MVT::i16 && "Bad word shuffle type!");
22877 if (combineRedundantHalfShuffle(N, Mask, DAG, DCI))
22878 return SDValue(); // We combined away this shuffle, so we're done.
22880 // See if this reduces to a PSHUFD which is no more expensive and can
22881 // combine with more operations. Note that it has to at least flip the
22882 // dwords as otherwise it would have been removed as a no-op.
22883 if (makeArrayRef(Mask).equals({2, 3, 0, 1})) {
22884 int DMask[] = {0, 1, 2, 3};
22885 int DOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 2;
22886 DMask[DOffset + 0] = DOffset + 1;
22887 DMask[DOffset + 1] = DOffset + 0;
22888 MVT DVT = MVT::getVectorVT(MVT::i32, VT.getVectorNumElements() / 2);
22889 V = DAG.getBitcast(DVT, V);
22890 DCI.AddToWorklist(V.getNode());
22891 V = DAG.getNode(X86ISD::PSHUFD, DL, DVT, V,
22892 getV4X86ShuffleImm8ForMask(DMask, DL, DAG));
22893 DCI.AddToWorklist(V.getNode());
22894 return DAG.getBitcast(VT, V);
22897 // Look for shuffle patterns which can be implemented as a single unpack.
22898 // FIXME: This doesn't handle the location of the PSHUFD generically, and
22899 // only works when we have a PSHUFD followed by two half-shuffles.
22900 if (Mask[0] == Mask[1] && Mask[2] == Mask[3] &&
22901 (V.getOpcode() == X86ISD::PSHUFLW ||
22902 V.getOpcode() == X86ISD::PSHUFHW) &&
22903 V.getOpcode() != N.getOpcode() &&
22905 SDValue D = V.getOperand(0);
22906 while (D.getOpcode() == ISD::BITCAST && D.hasOneUse())
22907 D = D.getOperand(0);
22908 if (D.getOpcode() == X86ISD::PSHUFD && D.hasOneUse()) {
22909 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
22910 SmallVector<int, 4> DMask = getPSHUFShuffleMask(D);
22911 int NOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
22912 int VOffset = V.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
22914 for (int i = 0; i < 4; ++i) {
22915 WordMask[i + NOffset] = Mask[i] + NOffset;
22916 WordMask[i + VOffset] = VMask[i] + VOffset;
22918 // Map the word mask through the DWord mask.
22920 for (int i = 0; i < 8; ++i)
22921 MappedMask[i] = 2 * DMask[WordMask[i] / 2] + WordMask[i] % 2;
22922 if (makeArrayRef(MappedMask).equals({0, 0, 1, 1, 2, 2, 3, 3}) ||
22923 makeArrayRef(MappedMask).equals({4, 4, 5, 5, 6, 6, 7, 7})) {
22924 // We can replace all three shuffles with an unpack.
22925 V = DAG.getBitcast(VT, D.getOperand(0));
22926 DCI.AddToWorklist(V.getNode());
22927 return DAG.getNode(MappedMask[0] == 0 ? X86ISD::UNPCKL
22936 case X86ISD::PSHUFD:
22937 if (SDValue NewN = combineRedundantDWordShuffle(N, Mask, DAG, DCI))
22946 /// \brief Try to combine a shuffle into a target-specific add-sub node.
22948 /// We combine this directly on the abstract vector shuffle nodes so it is
22949 /// easier to generically match. We also insert dummy vector shuffle nodes for
22950 /// the operands which explicitly discard the lanes which are unused by this
22951 /// operation to try to flow through the rest of the combiner the fact that
22952 /// they're unused.
22953 static SDValue combineShuffleToAddSub(SDNode *N, SelectionDAG &DAG) {
22955 EVT VT = N->getValueType(0);
22957 // We only handle target-independent shuffles.
22958 // FIXME: It would be easy and harmless to use the target shuffle mask
22959 // extraction tool to support more.
22960 if (N->getOpcode() != ISD::VECTOR_SHUFFLE)
22963 auto *SVN = cast<ShuffleVectorSDNode>(N);
22964 ArrayRef<int> Mask = SVN->getMask();
22965 SDValue V1 = N->getOperand(0);
22966 SDValue V2 = N->getOperand(1);
22968 // We require the first shuffle operand to be the SUB node, and the second to
22969 // be the ADD node.
22970 // FIXME: We should support the commuted patterns.
22971 if (V1->getOpcode() != ISD::FSUB || V2->getOpcode() != ISD::FADD)
22974 // If there are other uses of these operations we can't fold them.
22975 if (!V1->hasOneUse() || !V2->hasOneUse())
22978 // Ensure that both operations have the same operands. Note that we can
22979 // commute the FADD operands.
22980 SDValue LHS = V1->getOperand(0), RHS = V1->getOperand(1);
22981 if ((V2->getOperand(0) != LHS || V2->getOperand(1) != RHS) &&
22982 (V2->getOperand(0) != RHS || V2->getOperand(1) != LHS))
22985 // We're looking for blends between FADD and FSUB nodes. We insist on these
22986 // nodes being lined up in a specific expected pattern.
22987 if (!(isShuffleEquivalent(V1, V2, Mask, {0, 3}) ||
22988 isShuffleEquivalent(V1, V2, Mask, {0, 5, 2, 7}) ||
22989 isShuffleEquivalent(V1, V2, Mask, {0, 9, 2, 11, 4, 13, 6, 15})))
22992 // Only specific types are legal at this point, assert so we notice if and
22993 // when these change.
22994 assert((VT == MVT::v4f32 || VT == MVT::v2f64 || VT == MVT::v8f32 ||
22995 VT == MVT::v4f64) &&
22996 "Unknown vector type encountered!");
22998 return DAG.getNode(X86ISD::ADDSUB, DL, VT, LHS, RHS);
23001 /// PerformShuffleCombine - Performs several different shuffle combines.
23002 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
23003 TargetLowering::DAGCombinerInfo &DCI,
23004 const X86Subtarget *Subtarget) {
23006 SDValue N0 = N->getOperand(0);
23007 SDValue N1 = N->getOperand(1);
23008 EVT VT = N->getValueType(0);
23010 // Don't create instructions with illegal types after legalize types has run.
23011 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23012 if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType()))
23015 // If we have legalized the vector types, look for blends of FADD and FSUB
23016 // nodes that we can fuse into an ADDSUB node.
23017 if (TLI.isTypeLegal(VT) && Subtarget->hasSSE3())
23018 if (SDValue AddSub = combineShuffleToAddSub(N, DAG))
23021 // Combine 256-bit vector shuffles. This is only profitable when in AVX mode
23022 if (Subtarget->hasFp256() && VT.is256BitVector() &&
23023 N->getOpcode() == ISD::VECTOR_SHUFFLE)
23024 return PerformShuffleCombine256(N, DAG, DCI, Subtarget);
23026 // During Type Legalization, when promoting illegal vector types,
23027 // the backend might introduce new shuffle dag nodes and bitcasts.
23029 // This code performs the following transformation:
23030 // fold: (shuffle (bitcast (BINOP A, B)), Undef, <Mask>) ->
23031 // (shuffle (BINOP (bitcast A), (bitcast B)), Undef, <Mask>)
23033 // We do this only if both the bitcast and the BINOP dag nodes have
23034 // one use. Also, perform this transformation only if the new binary
23035 // operation is legal. This is to avoid introducing dag nodes that
23036 // potentially need to be further expanded (or custom lowered) into a
23037 // less optimal sequence of dag nodes.
23038 if (!DCI.isBeforeLegalize() && DCI.isBeforeLegalizeOps() &&
23039 N1.getOpcode() == ISD::UNDEF && N0.hasOneUse() &&
23040 N0.getOpcode() == ISD::BITCAST) {
23041 SDValue BC0 = N0.getOperand(0);
23042 EVT SVT = BC0.getValueType();
23043 unsigned Opcode = BC0.getOpcode();
23044 unsigned NumElts = VT.getVectorNumElements();
23046 if (BC0.hasOneUse() && SVT.isVector() &&
23047 SVT.getVectorNumElements() * 2 == NumElts &&
23048 TLI.isOperationLegal(Opcode, VT)) {
23049 bool CanFold = false;
23061 unsigned SVTNumElts = SVT.getVectorNumElements();
23062 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
23063 for (unsigned i = 0, e = SVTNumElts; i != e && CanFold; ++i)
23064 CanFold = SVOp->getMaskElt(i) == (int)(i * 2);
23065 for (unsigned i = SVTNumElts, e = NumElts; i != e && CanFold; ++i)
23066 CanFold = SVOp->getMaskElt(i) < 0;
23069 SDValue BC00 = DAG.getBitcast(VT, BC0.getOperand(0));
23070 SDValue BC01 = DAG.getBitcast(VT, BC0.getOperand(1));
23071 SDValue NewBinOp = DAG.getNode(BC0.getOpcode(), dl, VT, BC00, BC01);
23072 return DAG.getVectorShuffle(VT, dl, NewBinOp, N1, &SVOp->getMask()[0]);
23077 // Combine a vector_shuffle that is equal to build_vector load1, load2, load3,
23078 // load4, <0, 1, 2, 3> into a 128-bit load if the load addresses are
23079 // consecutive, non-overlapping, and in the right order.
23080 SmallVector<SDValue, 16> Elts;
23081 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
23082 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0));
23084 if (SDValue LD = EltsFromConsecutiveLoads(VT, Elts, dl, DAG, true))
23087 if (isTargetShuffle(N->getOpcode())) {
23089 PerformTargetShuffleCombine(SDValue(N, 0), DAG, DCI, Subtarget);
23090 if (Shuffle.getNode())
23093 // Try recursively combining arbitrary sequences of x86 shuffle
23094 // instructions into higher-order shuffles. We do this after combining
23095 // specific PSHUF instruction sequences into their minimal form so that we
23096 // can evaluate how many specialized shuffle instructions are involved in
23097 // a particular chain.
23098 SmallVector<int, 1> NonceMask; // Just a placeholder.
23099 NonceMask.push_back(0);
23100 if (combineX86ShufflesRecursively(SDValue(N, 0), SDValue(N, 0), NonceMask,
23101 /*Depth*/ 1, /*HasPSHUFB*/ false, DAG,
23103 return SDValue(); // This routine will use CombineTo to replace N.
23109 /// XFormVExtractWithShuffleIntoLoad - Check if a vector extract from a target
23110 /// specific shuffle of a load can be folded into a single element load.
23111 /// Similar handling for VECTOR_SHUFFLE is performed by DAGCombiner, but
23112 /// shuffles have been custom lowered so we need to handle those here.
23113 static SDValue XFormVExtractWithShuffleIntoLoad(SDNode *N, SelectionDAG &DAG,
23114 TargetLowering::DAGCombinerInfo &DCI) {
23115 if (DCI.isBeforeLegalizeOps())
23118 SDValue InVec = N->getOperand(0);
23119 SDValue EltNo = N->getOperand(1);
23121 if (!isa<ConstantSDNode>(EltNo))
23124 EVT OriginalVT = InVec.getValueType();
23126 if (InVec.getOpcode() == ISD::BITCAST) {
23127 // Don't duplicate a load with other uses.
23128 if (!InVec.hasOneUse())
23130 EVT BCVT = InVec.getOperand(0).getValueType();
23131 if (!BCVT.isVector() ||
23132 BCVT.getVectorNumElements() != OriginalVT.getVectorNumElements())
23134 InVec = InVec.getOperand(0);
23137 EVT CurrentVT = InVec.getValueType();
23139 if (!isTargetShuffle(InVec.getOpcode()))
23142 // Don't duplicate a load with other uses.
23143 if (!InVec.hasOneUse())
23146 SmallVector<int, 16> ShuffleMask;
23148 if (!getTargetShuffleMask(InVec.getNode(), CurrentVT.getSimpleVT(),
23149 ShuffleMask, UnaryShuffle))
23152 // Select the input vector, guarding against out of range extract vector.
23153 unsigned NumElems = CurrentVT.getVectorNumElements();
23154 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
23155 int Idx = (Elt > (int)NumElems) ? -1 : ShuffleMask[Elt];
23156 SDValue LdNode = (Idx < (int)NumElems) ? InVec.getOperand(0)
23157 : InVec.getOperand(1);
23159 // If inputs to shuffle are the same for both ops, then allow 2 uses
23160 unsigned AllowedUses = InVec.getNumOperands() > 1 &&
23161 InVec.getOperand(0) == InVec.getOperand(1) ? 2 : 1;
23163 if (LdNode.getOpcode() == ISD::BITCAST) {
23164 // Don't duplicate a load with other uses.
23165 if (!LdNode.getNode()->hasNUsesOfValue(AllowedUses, 0))
23168 AllowedUses = 1; // only allow 1 load use if we have a bitcast
23169 LdNode = LdNode.getOperand(0);
23172 if (!ISD::isNormalLoad(LdNode.getNode()))
23175 LoadSDNode *LN0 = cast<LoadSDNode>(LdNode);
23177 if (!LN0 ||!LN0->hasNUsesOfValue(AllowedUses, 0) || LN0->isVolatile())
23180 EVT EltVT = N->getValueType(0);
23181 // If there's a bitcast before the shuffle, check if the load type and
23182 // alignment is valid.
23183 unsigned Align = LN0->getAlignment();
23184 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23185 unsigned NewAlign = DAG.getDataLayout().getABITypeAlignment(
23186 EltVT.getTypeForEVT(*DAG.getContext()));
23188 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, EltVT))
23191 // All checks match so transform back to vector_shuffle so that DAG combiner
23192 // can finish the job
23195 // Create shuffle node taking into account the case that its a unary shuffle
23196 SDValue Shuffle = (UnaryShuffle) ? DAG.getUNDEF(CurrentVT)
23197 : InVec.getOperand(1);
23198 Shuffle = DAG.getVectorShuffle(CurrentVT, dl,
23199 InVec.getOperand(0), Shuffle,
23201 Shuffle = DAG.getBitcast(OriginalVT, Shuffle);
23202 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, N->getValueType(0), Shuffle,
23206 static SDValue PerformBITCASTCombine(SDNode *N, SelectionDAG &DAG,
23207 const X86Subtarget *Subtarget) {
23208 SDValue N0 = N->getOperand(0);
23209 EVT VT = N->getValueType(0);
23211 // Detect bitcasts between i32 to x86mmx low word. Since MMX types are
23212 // special and don't usually play with other vector types, it's better to
23213 // handle them early to be sure we emit efficient code by avoiding
23214 // store-load conversions.
23215 if (VT == MVT::x86mmx && N0.getOpcode() == ISD::BUILD_VECTOR &&
23216 N0.getValueType() == MVT::v2i32 &&
23217 isa<ConstantSDNode>(N0.getOperand(1))) {
23218 SDValue N00 = N0->getOperand(0);
23219 if (N0.getConstantOperandVal(1) == 0 && N00.getValueType() == MVT::i32)
23220 return DAG.getNode(X86ISD::MMX_MOVW2D, SDLoc(N00), VT, N00);
23223 // Convert a bitcasted integer logic operation that has one bitcasted
23224 // floating-point operand and one constant operand into a floating-point
23225 // logic operation. This may create a load of the constant, but that is
23226 // cheaper than materializing the constant in an integer register and
23227 // transferring it to an SSE register or transferring the SSE operand to
23228 // integer register and back.
23230 switch (N0.getOpcode()) {
23231 case ISD::AND: FPOpcode = X86ISD::FAND; break;
23232 case ISD::OR: FPOpcode = X86ISD::FOR; break;
23233 case ISD::XOR: FPOpcode = X86ISD::FXOR; break;
23234 default: return SDValue();
23236 if (((Subtarget->hasSSE1() && VT == MVT::f32) ||
23237 (Subtarget->hasSSE2() && VT == MVT::f64)) &&
23238 isa<ConstantSDNode>(N0.getOperand(1)) &&
23239 N0.getOperand(0).getOpcode() == ISD::BITCAST &&
23240 N0.getOperand(0).getOperand(0).getValueType() == VT) {
23241 SDValue N000 = N0.getOperand(0).getOperand(0);
23242 SDValue FPConst = DAG.getBitcast(VT, N0.getOperand(1));
23243 return DAG.getNode(FPOpcode, SDLoc(N0), VT, N000, FPConst);
23249 /// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index
23250 /// generation and convert it from being a bunch of shuffles and extracts
23251 /// into a somewhat faster sequence. For i686, the best sequence is apparently
23252 /// storing the value and loading scalars back, while for x64 we should
23253 /// use 64-bit extracts and shifts.
23254 static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG,
23255 TargetLowering::DAGCombinerInfo &DCI) {
23256 if (SDValue NewOp = XFormVExtractWithShuffleIntoLoad(N, DAG, DCI))
23259 SDValue InputVector = N->getOperand(0);
23260 SDLoc dl(InputVector);
23261 // Detect mmx to i32 conversion through a v2i32 elt extract.
23262 if (InputVector.getOpcode() == ISD::BITCAST && InputVector.hasOneUse() &&
23263 N->getValueType(0) == MVT::i32 &&
23264 InputVector.getValueType() == MVT::v2i32) {
23266 // The bitcast source is a direct mmx result.
23267 SDValue MMXSrc = InputVector.getNode()->getOperand(0);
23268 if (MMXSrc.getValueType() == MVT::x86mmx)
23269 return DAG.getNode(X86ISD::MMX_MOVD2W, SDLoc(InputVector),
23270 N->getValueType(0),
23271 InputVector.getNode()->getOperand(0));
23273 // The mmx is indirect: (i64 extract_elt (v1i64 bitcast (x86mmx ...))).
23274 if (MMXSrc.getOpcode() == ISD::EXTRACT_VECTOR_ELT && MMXSrc.hasOneUse() &&
23275 MMXSrc.getValueType() == MVT::i64) {
23276 SDValue MMXSrcOp = MMXSrc.getOperand(0);
23277 if (MMXSrcOp.hasOneUse() && MMXSrcOp.getOpcode() == ISD::BITCAST &&
23278 MMXSrcOp.getValueType() == MVT::v1i64 &&
23279 MMXSrcOp.getOperand(0).getValueType() == MVT::x86mmx)
23280 return DAG.getNode(X86ISD::MMX_MOVD2W, SDLoc(InputVector),
23281 N->getValueType(0), MMXSrcOp.getOperand(0));
23285 EVT VT = N->getValueType(0);
23287 if (VT == MVT::i1 && isa<ConstantSDNode>(N->getOperand(1)) &&
23288 InputVector.getOpcode() == ISD::BITCAST &&
23289 isa<ConstantSDNode>(InputVector.getOperand(0))) {
23290 uint64_t ExtractedElt =
23291 cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
23292 uint64_t InputValue =
23293 cast<ConstantSDNode>(InputVector.getOperand(0))->getZExtValue();
23294 uint64_t Res = (InputValue >> ExtractedElt) & 1;
23295 return DAG.getConstant(Res, dl, MVT::i1);
23297 // Only operate on vectors of 4 elements, where the alternative shuffling
23298 // gets to be more expensive.
23299 if (InputVector.getValueType() != MVT::v4i32)
23302 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a
23303 // single use which is a sign-extend or zero-extend, and all elements are
23305 SmallVector<SDNode *, 4> Uses;
23306 unsigned ExtractedElements = 0;
23307 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(),
23308 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) {
23309 if (UI.getUse().getResNo() != InputVector.getResNo())
23312 SDNode *Extract = *UI;
23313 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
23316 if (Extract->getValueType(0) != MVT::i32)
23318 if (!Extract->hasOneUse())
23320 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND &&
23321 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND)
23323 if (!isa<ConstantSDNode>(Extract->getOperand(1)))
23326 // Record which element was extracted.
23327 ExtractedElements |=
23328 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue();
23330 Uses.push_back(Extract);
23333 // If not all the elements were used, this may not be worthwhile.
23334 if (ExtractedElements != 15)
23337 // Ok, we've now decided to do the transformation.
23338 // If 64-bit shifts are legal, use the extract-shift sequence,
23339 // otherwise bounce the vector off the cache.
23340 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23343 if (TLI.isOperationLegal(ISD::SRA, MVT::i64)) {
23344 SDValue Cst = DAG.getBitcast(MVT::v2i64, InputVector);
23345 auto &DL = DAG.getDataLayout();
23346 EVT VecIdxTy = DAG.getTargetLoweringInfo().getVectorIdxTy(DL);
23347 SDValue BottomHalf = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64, Cst,
23348 DAG.getConstant(0, dl, VecIdxTy));
23349 SDValue TopHalf = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64, Cst,
23350 DAG.getConstant(1, dl, VecIdxTy));
23352 SDValue ShAmt = DAG.getConstant(
23353 32, dl, DAG.getTargetLoweringInfo().getShiftAmountTy(MVT::i64, DL));
23354 Vals[0] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, BottomHalf);
23355 Vals[1] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32,
23356 DAG.getNode(ISD::SRA, dl, MVT::i64, BottomHalf, ShAmt));
23357 Vals[2] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, TopHalf);
23358 Vals[3] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32,
23359 DAG.getNode(ISD::SRA, dl, MVT::i64, TopHalf, ShAmt));
23361 // Store the value to a temporary stack slot.
23362 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType());
23363 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr,
23364 MachinePointerInfo(), false, false, 0);
23366 EVT ElementType = InputVector.getValueType().getVectorElementType();
23367 unsigned EltSize = ElementType.getSizeInBits() / 8;
23369 // Replace each use (extract) with a load of the appropriate element.
23370 for (unsigned i = 0; i < 4; ++i) {
23371 uint64_t Offset = EltSize * i;
23372 auto PtrVT = TLI.getPointerTy(DAG.getDataLayout());
23373 SDValue OffsetVal = DAG.getConstant(Offset, dl, PtrVT);
23375 SDValue ScalarAddr =
23376 DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, OffsetVal);
23378 // Load the scalar.
23379 Vals[i] = DAG.getLoad(ElementType, dl, Ch,
23380 ScalarAddr, MachinePointerInfo(),
23381 false, false, false, 0);
23386 // Replace the extracts
23387 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(),
23388 UE = Uses.end(); UI != UE; ++UI) {
23389 SDNode *Extract = *UI;
23391 SDValue Idx = Extract->getOperand(1);
23392 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
23393 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), Vals[IdxVal]);
23396 // The replacement was made in place; don't return anything.
23401 transformVSELECTtoBlendVECTOR_SHUFFLE(SDNode *N, SelectionDAG &DAG,
23402 const X86Subtarget *Subtarget) {
23404 SDValue Cond = N->getOperand(0);
23405 SDValue LHS = N->getOperand(1);
23406 SDValue RHS = N->getOperand(2);
23408 if (Cond.getOpcode() == ISD::SIGN_EXTEND) {
23409 SDValue CondSrc = Cond->getOperand(0);
23410 if (CondSrc->getOpcode() == ISD::SIGN_EXTEND_INREG)
23411 Cond = CondSrc->getOperand(0);
23414 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
23417 // A vselect where all conditions and data are constants can be optimized into
23418 // a single vector load by SelectionDAGLegalize::ExpandBUILD_VECTOR().
23419 if (ISD::isBuildVectorOfConstantSDNodes(LHS.getNode()) &&
23420 ISD::isBuildVectorOfConstantSDNodes(RHS.getNode()))
23423 unsigned MaskValue = 0;
23424 if (!BUILD_VECTORtoBlendMask(cast<BuildVectorSDNode>(Cond), MaskValue))
23427 MVT VT = N->getSimpleValueType(0);
23428 unsigned NumElems = VT.getVectorNumElements();
23429 SmallVector<int, 8> ShuffleMask(NumElems, -1);
23430 for (unsigned i = 0; i < NumElems; ++i) {
23431 // Be sure we emit undef where we can.
23432 if (Cond.getOperand(i)->getOpcode() == ISD::UNDEF)
23433 ShuffleMask[i] = -1;
23435 ShuffleMask[i] = i + NumElems * ((MaskValue >> i) & 1);
23438 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23439 if (!TLI.isShuffleMaskLegal(ShuffleMask, VT))
23441 return DAG.getVectorShuffle(VT, dl, LHS, RHS, &ShuffleMask[0]);
23444 /// PerformSELECTCombine - Do target-specific dag combines on SELECT and VSELECT
23446 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
23447 TargetLowering::DAGCombinerInfo &DCI,
23448 const X86Subtarget *Subtarget) {
23450 SDValue Cond = N->getOperand(0);
23451 // Get the LHS/RHS of the select.
23452 SDValue LHS = N->getOperand(1);
23453 SDValue RHS = N->getOperand(2);
23454 EVT VT = LHS.getValueType();
23455 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23457 // If we have SSE[12] support, try to form min/max nodes. SSE min/max
23458 // instructions match the semantics of the common C idiom x<y?x:y but not
23459 // x<=y?x:y, because of how they handle negative zero (which can be
23460 // ignored in unsafe-math mode).
23461 // We also try to create v2f32 min/max nodes, which we later widen to v4f32.
23462 if (Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() &&
23463 VT != MVT::f80 && (TLI.isTypeLegal(VT) || VT == MVT::v2f32) &&
23464 (Subtarget->hasSSE2() ||
23465 (Subtarget->hasSSE1() && VT.getScalarType() == MVT::f32))) {
23466 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
23468 unsigned Opcode = 0;
23469 // Check for x CC y ? x : y.
23470 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
23471 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
23475 // Converting this to a min would handle NaNs incorrectly, and swapping
23476 // the operands would cause it to handle comparisons between positive
23477 // and negative zero incorrectly.
23478 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
23479 if (!DAG.getTarget().Options.UnsafeFPMath &&
23480 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
23482 std::swap(LHS, RHS);
23484 Opcode = X86ISD::FMIN;
23487 // Converting this to a min would handle comparisons between positive
23488 // and negative zero incorrectly.
23489 if (!DAG.getTarget().Options.UnsafeFPMath &&
23490 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
23492 Opcode = X86ISD::FMIN;
23495 // Converting this to a min would handle both negative zeros and NaNs
23496 // incorrectly, but we can swap the operands to fix both.
23497 std::swap(LHS, RHS);
23501 Opcode = X86ISD::FMIN;
23505 // Converting this to a max would handle comparisons between positive
23506 // and negative zero incorrectly.
23507 if (!DAG.getTarget().Options.UnsafeFPMath &&
23508 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
23510 Opcode = X86ISD::FMAX;
23513 // Converting this to a max would handle NaNs incorrectly, and swapping
23514 // the operands would cause it to handle comparisons between positive
23515 // and negative zero incorrectly.
23516 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
23517 if (!DAG.getTarget().Options.UnsafeFPMath &&
23518 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
23520 std::swap(LHS, RHS);
23522 Opcode = X86ISD::FMAX;
23525 // Converting this to a max would handle both negative zeros and NaNs
23526 // incorrectly, but we can swap the operands to fix both.
23527 std::swap(LHS, RHS);
23531 Opcode = X86ISD::FMAX;
23534 // Check for x CC y ? y : x -- a min/max with reversed arms.
23535 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
23536 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
23540 // Converting this to a min would handle comparisons between positive
23541 // and negative zero incorrectly, and swapping the operands would
23542 // cause it to handle NaNs incorrectly.
23543 if (!DAG.getTarget().Options.UnsafeFPMath &&
23544 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) {
23545 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
23547 std::swap(LHS, RHS);
23549 Opcode = X86ISD::FMIN;
23552 // Converting this to a min would handle NaNs incorrectly.
23553 if (!DAG.getTarget().Options.UnsafeFPMath &&
23554 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
23556 Opcode = X86ISD::FMIN;
23559 // Converting this to a min would handle both negative zeros and NaNs
23560 // incorrectly, but we can swap the operands to fix both.
23561 std::swap(LHS, RHS);
23565 Opcode = X86ISD::FMIN;
23569 // Converting this to a max would handle NaNs incorrectly.
23570 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
23572 Opcode = X86ISD::FMAX;
23575 // Converting this to a max would handle comparisons between positive
23576 // and negative zero incorrectly, and swapping the operands would
23577 // cause it to handle NaNs incorrectly.
23578 if (!DAG.getTarget().Options.UnsafeFPMath &&
23579 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) {
23580 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
23582 std::swap(LHS, RHS);
23584 Opcode = X86ISD::FMAX;
23587 // Converting this to a max would handle both negative zeros and NaNs
23588 // incorrectly, but we can swap the operands to fix both.
23589 std::swap(LHS, RHS);
23593 Opcode = X86ISD::FMAX;
23599 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
23602 EVT CondVT = Cond.getValueType();
23603 if (Subtarget->hasAVX512() && VT.isVector() && CondVT.isVector() &&
23604 CondVT.getVectorElementType() == MVT::i1) {
23605 // v16i8 (select v16i1, v16i8, v16i8) does not have a proper
23606 // lowering on KNL. In this case we convert it to
23607 // v16i8 (select v16i8, v16i8, v16i8) and use AVX instruction.
23608 // The same situation for all 128 and 256-bit vectors of i8 and i16.
23609 // Since SKX these selects have a proper lowering.
23610 EVT OpVT = LHS.getValueType();
23611 if ((OpVT.is128BitVector() || OpVT.is256BitVector()) &&
23612 (OpVT.getVectorElementType() == MVT::i8 ||
23613 OpVT.getVectorElementType() == MVT::i16) &&
23614 !(Subtarget->hasBWI() && Subtarget->hasVLX())) {
23615 Cond = DAG.getNode(ISD::SIGN_EXTEND, DL, OpVT, Cond);
23616 DCI.AddToWorklist(Cond.getNode());
23617 return DAG.getNode(N->getOpcode(), DL, OpVT, Cond, LHS, RHS);
23620 // If this is a select between two integer constants, try to do some
23622 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
23623 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
23624 // Don't do this for crazy integer types.
23625 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
23626 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
23627 // so that TrueC (the true value) is larger than FalseC.
23628 bool NeedsCondInvert = false;
23630 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
23631 // Efficiently invertible.
23632 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
23633 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
23634 isa<ConstantSDNode>(Cond.getOperand(1))))) {
23635 NeedsCondInvert = true;
23636 std::swap(TrueC, FalseC);
23639 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
23640 if (FalseC->getAPIntValue() == 0 &&
23641 TrueC->getAPIntValue().isPowerOf2()) {
23642 if (NeedsCondInvert) // Invert the condition if needed.
23643 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
23644 DAG.getConstant(1, DL, Cond.getValueType()));
23646 // Zero extend the condition if needed.
23647 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
23649 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
23650 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
23651 DAG.getConstant(ShAmt, DL, MVT::i8));
23654 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
23655 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
23656 if (NeedsCondInvert) // Invert the condition if needed.
23657 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
23658 DAG.getConstant(1, DL, Cond.getValueType()));
23660 // Zero extend the condition if needed.
23661 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
23662 FalseC->getValueType(0), Cond);
23663 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
23664 SDValue(FalseC, 0));
23667 // Optimize cases that will turn into an LEA instruction. This requires
23668 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
23669 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
23670 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
23671 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
23673 bool isFastMultiplier = false;
23675 switch ((unsigned char)Diff) {
23677 case 1: // result = add base, cond
23678 case 2: // result = lea base( , cond*2)
23679 case 3: // result = lea base(cond, cond*2)
23680 case 4: // result = lea base( , cond*4)
23681 case 5: // result = lea base(cond, cond*4)
23682 case 8: // result = lea base( , cond*8)
23683 case 9: // result = lea base(cond, cond*8)
23684 isFastMultiplier = true;
23689 if (isFastMultiplier) {
23690 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
23691 if (NeedsCondInvert) // Invert the condition if needed.
23692 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
23693 DAG.getConstant(1, DL, Cond.getValueType()));
23695 // Zero extend the condition if needed.
23696 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
23698 // Scale the condition by the difference.
23700 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
23701 DAG.getConstant(Diff, DL,
23702 Cond.getValueType()));
23704 // Add the base if non-zero.
23705 if (FalseC->getAPIntValue() != 0)
23706 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
23707 SDValue(FalseC, 0));
23714 // Canonicalize max and min:
23715 // (x > y) ? x : y -> (x >= y) ? x : y
23716 // (x < y) ? x : y -> (x <= y) ? x : y
23717 // This allows use of COND_S / COND_NS (see TranslateX86CC) which eliminates
23718 // the need for an extra compare
23719 // against zero. e.g.
23720 // (x - y) > 0 : (x - y) ? 0 -> (x - y) >= 0 : (x - y) ? 0
23722 // testl %edi, %edi
23724 // cmovgl %edi, %eax
23728 // cmovsl %eax, %edi
23729 if (N->getOpcode() == ISD::SELECT && Cond.getOpcode() == ISD::SETCC &&
23730 DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
23731 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
23732 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
23737 ISD::CondCode NewCC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGE;
23738 Cond = DAG.getSetCC(SDLoc(Cond), Cond.getValueType(),
23739 Cond.getOperand(0), Cond.getOperand(1), NewCC);
23740 return DAG.getNode(ISD::SELECT, DL, VT, Cond, LHS, RHS);
23745 // Early exit check
23746 if (!TLI.isTypeLegal(VT))
23749 // Match VSELECTs into subs with unsigned saturation.
23750 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC &&
23751 // psubus is available in SSE2 and AVX2 for i8 and i16 vectors.
23752 ((Subtarget->hasSSE2() && (VT == MVT::v16i8 || VT == MVT::v8i16)) ||
23753 (Subtarget->hasAVX2() && (VT == MVT::v32i8 || VT == MVT::v16i16)))) {
23754 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
23756 // Check if one of the arms of the VSELECT is a zero vector. If it's on the
23757 // left side invert the predicate to simplify logic below.
23759 if (ISD::isBuildVectorAllZeros(LHS.getNode())) {
23761 CC = ISD::getSetCCInverse(CC, true);
23762 } else if (ISD::isBuildVectorAllZeros(RHS.getNode())) {
23766 if (Other.getNode() && Other->getNumOperands() == 2 &&
23767 DAG.isEqualTo(Other->getOperand(0), Cond.getOperand(0))) {
23768 SDValue OpLHS = Other->getOperand(0), OpRHS = Other->getOperand(1);
23769 SDValue CondRHS = Cond->getOperand(1);
23771 // Look for a general sub with unsigned saturation first.
23772 // x >= y ? x-y : 0 --> subus x, y
23773 // x > y ? x-y : 0 --> subus x, y
23774 if ((CC == ISD::SETUGE || CC == ISD::SETUGT) &&
23775 Other->getOpcode() == ISD::SUB && DAG.isEqualTo(OpRHS, CondRHS))
23776 return DAG.getNode(X86ISD::SUBUS, DL, VT, OpLHS, OpRHS);
23778 if (auto *OpRHSBV = dyn_cast<BuildVectorSDNode>(OpRHS))
23779 if (auto *OpRHSConst = OpRHSBV->getConstantSplatNode()) {
23780 if (auto *CondRHSBV = dyn_cast<BuildVectorSDNode>(CondRHS))
23781 if (auto *CondRHSConst = CondRHSBV->getConstantSplatNode())
23782 // If the RHS is a constant we have to reverse the const
23783 // canonicalization.
23784 // x > C-1 ? x+-C : 0 --> subus x, C
23785 if (CC == ISD::SETUGT && Other->getOpcode() == ISD::ADD &&
23786 CondRHSConst->getAPIntValue() ==
23787 (-OpRHSConst->getAPIntValue() - 1))
23788 return DAG.getNode(
23789 X86ISD::SUBUS, DL, VT, OpLHS,
23790 DAG.getConstant(-OpRHSConst->getAPIntValue(), DL, VT));
23792 // Another special case: If C was a sign bit, the sub has been
23793 // canonicalized into a xor.
23794 // FIXME: Would it be better to use computeKnownBits to determine
23795 // whether it's safe to decanonicalize the xor?
23796 // x s< 0 ? x^C : 0 --> subus x, C
23797 if (CC == ISD::SETLT && Other->getOpcode() == ISD::XOR &&
23798 ISD::isBuildVectorAllZeros(CondRHS.getNode()) &&
23799 OpRHSConst->getAPIntValue().isSignBit())
23800 // Note that we have to rebuild the RHS constant here to ensure we
23801 // don't rely on particular values of undef lanes.
23802 return DAG.getNode(
23803 X86ISD::SUBUS, DL, VT, OpLHS,
23804 DAG.getConstant(OpRHSConst->getAPIntValue(), DL, VT));
23809 // Simplify vector selection if condition value type matches vselect
23811 if (N->getOpcode() == ISD::VSELECT && CondVT == VT) {
23812 assert(Cond.getValueType().isVector() &&
23813 "vector select expects a vector selector!");
23815 bool TValIsAllOnes = ISD::isBuildVectorAllOnes(LHS.getNode());
23816 bool FValIsAllZeros = ISD::isBuildVectorAllZeros(RHS.getNode());
23818 // Try invert the condition if true value is not all 1s and false value
23820 if (!TValIsAllOnes && !FValIsAllZeros &&
23821 // Check if the selector will be produced by CMPP*/PCMP*
23822 Cond.getOpcode() == ISD::SETCC &&
23823 // Check if SETCC has already been promoted
23824 TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT) ==
23826 bool TValIsAllZeros = ISD::isBuildVectorAllZeros(LHS.getNode());
23827 bool FValIsAllOnes = ISD::isBuildVectorAllOnes(RHS.getNode());
23829 if (TValIsAllZeros || FValIsAllOnes) {
23830 SDValue CC = Cond.getOperand(2);
23831 ISD::CondCode NewCC =
23832 ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
23833 Cond.getOperand(0).getValueType().isInteger());
23834 Cond = DAG.getSetCC(DL, CondVT, Cond.getOperand(0), Cond.getOperand(1), NewCC);
23835 std::swap(LHS, RHS);
23836 TValIsAllOnes = FValIsAllOnes;
23837 FValIsAllZeros = TValIsAllZeros;
23841 if (TValIsAllOnes || FValIsAllZeros) {
23844 if (TValIsAllOnes && FValIsAllZeros)
23846 else if (TValIsAllOnes)
23848 DAG.getNode(ISD::OR, DL, CondVT, Cond, DAG.getBitcast(CondVT, RHS));
23849 else if (FValIsAllZeros)
23850 Ret = DAG.getNode(ISD::AND, DL, CondVT, Cond,
23851 DAG.getBitcast(CondVT, LHS));
23853 return DAG.getBitcast(VT, Ret);
23857 // We should generate an X86ISD::BLENDI from a vselect if its argument
23858 // is a sign_extend_inreg of an any_extend of a BUILD_VECTOR of
23859 // constants. This specific pattern gets generated when we split a
23860 // selector for a 512 bit vector in a machine without AVX512 (but with
23861 // 256-bit vectors), during legalization:
23863 // (vselect (sign_extend (any_extend (BUILD_VECTOR)) i1) LHS RHS)
23865 // Iff we find this pattern and the build_vectors are built from
23866 // constants, we translate the vselect into a shuffle_vector that we
23867 // know will be matched by LowerVECTOR_SHUFFLEtoBlend.
23868 if ((N->getOpcode() == ISD::VSELECT ||
23869 N->getOpcode() == X86ISD::SHRUNKBLEND) &&
23870 !DCI.isBeforeLegalize() && !VT.is512BitVector()) {
23871 SDValue Shuffle = transformVSELECTtoBlendVECTOR_SHUFFLE(N, DAG, Subtarget);
23872 if (Shuffle.getNode())
23876 // If this is a *dynamic* select (non-constant condition) and we can match
23877 // this node with one of the variable blend instructions, restructure the
23878 // condition so that the blends can use the high bit of each element and use
23879 // SimplifyDemandedBits to simplify the condition operand.
23880 if (N->getOpcode() == ISD::VSELECT && DCI.isBeforeLegalizeOps() &&
23881 !DCI.isBeforeLegalize() &&
23882 !ISD::isBuildVectorOfConstantSDNodes(Cond.getNode())) {
23883 unsigned BitWidth = Cond.getValueType().getScalarSizeInBits();
23885 // Don't optimize vector selects that map to mask-registers.
23889 // We can only handle the cases where VSELECT is directly legal on the
23890 // subtarget. We custom lower VSELECT nodes with constant conditions and
23891 // this makes it hard to see whether a dynamic VSELECT will correctly
23892 // lower, so we both check the operation's status and explicitly handle the
23893 // cases where a *dynamic* blend will fail even though a constant-condition
23894 // blend could be custom lowered.
23895 // FIXME: We should find a better way to handle this class of problems.
23896 // Potentially, we should combine constant-condition vselect nodes
23897 // pre-legalization into shuffles and not mark as many types as custom
23899 if (!TLI.isOperationLegalOrCustom(ISD::VSELECT, VT))
23901 // FIXME: We don't support i16-element blends currently. We could and
23902 // should support them by making *all* the bits in the condition be set
23903 // rather than just the high bit and using an i8-element blend.
23904 if (VT.getVectorElementType() == MVT::i16)
23906 // Dynamic blending was only available from SSE4.1 onward.
23907 if (VT.is128BitVector() && !Subtarget->hasSSE41())
23909 // Byte blends are only available in AVX2
23910 if (VT == MVT::v32i8 && !Subtarget->hasAVX2())
23913 assert(BitWidth >= 8 && BitWidth <= 64 && "Invalid mask size");
23914 APInt DemandedMask = APInt::getHighBitsSet(BitWidth, 1);
23916 APInt KnownZero, KnownOne;
23917 TargetLowering::TargetLoweringOpt TLO(DAG, DCI.isBeforeLegalize(),
23918 DCI.isBeforeLegalizeOps());
23919 if (TLO.ShrinkDemandedConstant(Cond, DemandedMask) ||
23920 TLI.SimplifyDemandedBits(Cond, DemandedMask, KnownZero, KnownOne,
23922 // If we changed the computation somewhere in the DAG, this change
23923 // will affect all users of Cond.
23924 // Make sure it is fine and update all the nodes so that we do not
23925 // use the generic VSELECT anymore. Otherwise, we may perform
23926 // wrong optimizations as we messed up with the actual expectation
23927 // for the vector boolean values.
23928 if (Cond != TLO.Old) {
23929 // Check all uses of that condition operand to check whether it will be
23930 // consumed by non-BLEND instructions, which may depend on all bits are
23932 for (SDNode::use_iterator I = Cond->use_begin(), E = Cond->use_end();
23934 if (I->getOpcode() != ISD::VSELECT)
23935 // TODO: Add other opcodes eventually lowered into BLEND.
23938 // Update all the users of the condition, before committing the change,
23939 // so that the VSELECT optimizations that expect the correct vector
23940 // boolean value will not be triggered.
23941 for (SDNode::use_iterator I = Cond->use_begin(), E = Cond->use_end();
23943 DAG.ReplaceAllUsesOfValueWith(
23945 DAG.getNode(X86ISD::SHRUNKBLEND, SDLoc(*I), I->getValueType(0),
23946 Cond, I->getOperand(1), I->getOperand(2)));
23947 DCI.CommitTargetLoweringOpt(TLO);
23950 // At this point, only Cond is changed. Change the condition
23951 // just for N to keep the opportunity to optimize all other
23952 // users their own way.
23953 DAG.ReplaceAllUsesOfValueWith(
23955 DAG.getNode(X86ISD::SHRUNKBLEND, SDLoc(N), N->getValueType(0),
23956 TLO.New, N->getOperand(1), N->getOperand(2)));
23964 // Check whether a boolean test is testing a boolean value generated by
23965 // X86ISD::SETCC. If so, return the operand of that SETCC and proper condition
23968 // Simplify the following patterns:
23969 // (Op (CMP (SETCC Cond EFLAGS) 1) EQ) or
23970 // (Op (CMP (SETCC Cond EFLAGS) 0) NEQ)
23971 // to (Op EFLAGS Cond)
23973 // (Op (CMP (SETCC Cond EFLAGS) 0) EQ) or
23974 // (Op (CMP (SETCC Cond EFLAGS) 1) NEQ)
23975 // to (Op EFLAGS !Cond)
23977 // where Op could be BRCOND or CMOV.
23979 static SDValue checkBoolTestSetCCCombine(SDValue Cmp, X86::CondCode &CC) {
23980 // Quit if not CMP and SUB with its value result used.
23981 if (Cmp.getOpcode() != X86ISD::CMP &&
23982 (Cmp.getOpcode() != X86ISD::SUB || Cmp.getNode()->hasAnyUseOfValue(0)))
23985 // Quit if not used as a boolean value.
23986 if (CC != X86::COND_E && CC != X86::COND_NE)
23989 // Check CMP operands. One of them should be 0 or 1 and the other should be
23990 // an SetCC or extended from it.
23991 SDValue Op1 = Cmp.getOperand(0);
23992 SDValue Op2 = Cmp.getOperand(1);
23995 const ConstantSDNode* C = nullptr;
23996 bool needOppositeCond = (CC == X86::COND_E);
23997 bool checkAgainstTrue = false; // Is it a comparison against 1?
23999 if ((C = dyn_cast<ConstantSDNode>(Op1)))
24001 else if ((C = dyn_cast<ConstantSDNode>(Op2)))
24003 else // Quit if all operands are not constants.
24006 if (C->getZExtValue() == 1) {
24007 needOppositeCond = !needOppositeCond;
24008 checkAgainstTrue = true;
24009 } else if (C->getZExtValue() != 0)
24010 // Quit if the constant is neither 0 or 1.
24013 bool truncatedToBoolWithAnd = false;
24014 // Skip (zext $x), (trunc $x), or (and $x, 1) node.
24015 while (SetCC.getOpcode() == ISD::ZERO_EXTEND ||
24016 SetCC.getOpcode() == ISD::TRUNCATE ||
24017 SetCC.getOpcode() == ISD::AND) {
24018 if (SetCC.getOpcode() == ISD::AND) {
24020 ConstantSDNode *CS;
24021 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(0))) &&
24022 CS->getZExtValue() == 1)
24024 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(1))) &&
24025 CS->getZExtValue() == 1)
24029 SetCC = SetCC.getOperand(OpIdx);
24030 truncatedToBoolWithAnd = true;
24032 SetCC = SetCC.getOperand(0);
24035 switch (SetCC.getOpcode()) {
24036 case X86ISD::SETCC_CARRY:
24037 // Since SETCC_CARRY gives output based on R = CF ? ~0 : 0, it's unsafe to
24038 // simplify it if the result of SETCC_CARRY is not canonicalized to 0 or 1,
24039 // i.e. it's a comparison against true but the result of SETCC_CARRY is not
24040 // truncated to i1 using 'and'.
24041 if (checkAgainstTrue && !truncatedToBoolWithAnd)
24043 assert(X86::CondCode(SetCC.getConstantOperandVal(0)) == X86::COND_B &&
24044 "Invalid use of SETCC_CARRY!");
24046 case X86ISD::SETCC:
24047 // Set the condition code or opposite one if necessary.
24048 CC = X86::CondCode(SetCC.getConstantOperandVal(0));
24049 if (needOppositeCond)
24050 CC = X86::GetOppositeBranchCondition(CC);
24051 return SetCC.getOperand(1);
24052 case X86ISD::CMOV: {
24053 // Check whether false/true value has canonical one, i.e. 0 or 1.
24054 ConstantSDNode *FVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(0));
24055 ConstantSDNode *TVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(1));
24056 // Quit if true value is not a constant.
24059 // Quit if false value is not a constant.
24061 SDValue Op = SetCC.getOperand(0);
24062 // Skip 'zext' or 'trunc' node.
24063 if (Op.getOpcode() == ISD::ZERO_EXTEND ||
24064 Op.getOpcode() == ISD::TRUNCATE)
24065 Op = Op.getOperand(0);
24066 // A special case for rdrand/rdseed, where 0 is set if false cond is
24068 if ((Op.getOpcode() != X86ISD::RDRAND &&
24069 Op.getOpcode() != X86ISD::RDSEED) || Op.getResNo() != 0)
24072 // Quit if false value is not the constant 0 or 1.
24073 bool FValIsFalse = true;
24074 if (FVal && FVal->getZExtValue() != 0) {
24075 if (FVal->getZExtValue() != 1)
24077 // If FVal is 1, opposite cond is needed.
24078 needOppositeCond = !needOppositeCond;
24079 FValIsFalse = false;
24081 // Quit if TVal is not the constant opposite of FVal.
24082 if (FValIsFalse && TVal->getZExtValue() != 1)
24084 if (!FValIsFalse && TVal->getZExtValue() != 0)
24086 CC = X86::CondCode(SetCC.getConstantOperandVal(2));
24087 if (needOppositeCond)
24088 CC = X86::GetOppositeBranchCondition(CC);
24089 return SetCC.getOperand(3);
24096 /// Check whether Cond is an AND/OR of SETCCs off of the same EFLAGS.
24098 /// (X86or (X86setcc) (X86setcc))
24099 /// (X86cmp (and (X86setcc) (X86setcc)), 0)
24100 static bool checkBoolTestAndOrSetCCCombine(SDValue Cond, X86::CondCode &CC0,
24101 X86::CondCode &CC1, SDValue &Flags,
24103 if (Cond->getOpcode() == X86ISD::CMP) {
24104 ConstantSDNode *CondOp1C = dyn_cast<ConstantSDNode>(Cond->getOperand(1));
24105 if (!CondOp1C || !CondOp1C->isNullValue())
24108 Cond = Cond->getOperand(0);
24113 SDValue SetCC0, SetCC1;
24114 switch (Cond->getOpcode()) {
24115 default: return false;
24122 SetCC0 = Cond->getOperand(0);
24123 SetCC1 = Cond->getOperand(1);
24127 // Make sure we have SETCC nodes, using the same flags value.
24128 if (SetCC0.getOpcode() != X86ISD::SETCC ||
24129 SetCC1.getOpcode() != X86ISD::SETCC ||
24130 SetCC0->getOperand(1) != SetCC1->getOperand(1))
24133 CC0 = (X86::CondCode)SetCC0->getConstantOperandVal(0);
24134 CC1 = (X86::CondCode)SetCC1->getConstantOperandVal(0);
24135 Flags = SetCC0->getOperand(1);
24139 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
24140 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
24141 TargetLowering::DAGCombinerInfo &DCI,
24142 const X86Subtarget *Subtarget) {
24145 // If the flag operand isn't dead, don't touch this CMOV.
24146 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
24149 SDValue FalseOp = N->getOperand(0);
24150 SDValue TrueOp = N->getOperand(1);
24151 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
24152 SDValue Cond = N->getOperand(3);
24154 if (CC == X86::COND_E || CC == X86::COND_NE) {
24155 switch (Cond.getOpcode()) {
24159 // If operand of BSR / BSF are proven never zero, then ZF cannot be set.
24160 if (DAG.isKnownNeverZero(Cond.getOperand(0)))
24161 return (CC == X86::COND_E) ? FalseOp : TrueOp;
24167 Flags = checkBoolTestSetCCCombine(Cond, CC);
24168 if (Flags.getNode() &&
24169 // Extra check as FCMOV only supports a subset of X86 cond.
24170 (FalseOp.getValueType() != MVT::f80 || hasFPCMov(CC))) {
24171 SDValue Ops[] = { FalseOp, TrueOp,
24172 DAG.getConstant(CC, DL, MVT::i8), Flags };
24173 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), Ops);
24176 // If this is a select between two integer constants, try to do some
24177 // optimizations. Note that the operands are ordered the opposite of SELECT
24179 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(TrueOp)) {
24180 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(FalseOp)) {
24181 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
24182 // larger than FalseC (the false value).
24183 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
24184 CC = X86::GetOppositeBranchCondition(CC);
24185 std::swap(TrueC, FalseC);
24186 std::swap(TrueOp, FalseOp);
24189 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
24190 // This is efficient for any integer data type (including i8/i16) and
24192 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
24193 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
24194 DAG.getConstant(CC, DL, MVT::i8), Cond);
24196 // Zero extend the condition if needed.
24197 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
24199 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
24200 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
24201 DAG.getConstant(ShAmt, DL, MVT::i8));
24202 if (N->getNumValues() == 2) // Dead flag value?
24203 return DCI.CombineTo(N, Cond, SDValue());
24207 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
24208 // for any integer data type, including i8/i16.
24209 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
24210 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
24211 DAG.getConstant(CC, DL, MVT::i8), Cond);
24213 // Zero extend the condition if needed.
24214 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
24215 FalseC->getValueType(0), Cond);
24216 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
24217 SDValue(FalseC, 0));
24219 if (N->getNumValues() == 2) // Dead flag value?
24220 return DCI.CombineTo(N, Cond, SDValue());
24224 // Optimize cases that will turn into an LEA instruction. This requires
24225 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
24226 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
24227 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
24228 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
24230 bool isFastMultiplier = false;
24232 switch ((unsigned char)Diff) {
24234 case 1: // result = add base, cond
24235 case 2: // result = lea base( , cond*2)
24236 case 3: // result = lea base(cond, cond*2)
24237 case 4: // result = lea base( , cond*4)
24238 case 5: // result = lea base(cond, cond*4)
24239 case 8: // result = lea base( , cond*8)
24240 case 9: // result = lea base(cond, cond*8)
24241 isFastMultiplier = true;
24246 if (isFastMultiplier) {
24247 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
24248 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
24249 DAG.getConstant(CC, DL, MVT::i8), Cond);
24250 // Zero extend the condition if needed.
24251 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
24253 // Scale the condition by the difference.
24255 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
24256 DAG.getConstant(Diff, DL, Cond.getValueType()));
24258 // Add the base if non-zero.
24259 if (FalseC->getAPIntValue() != 0)
24260 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
24261 SDValue(FalseC, 0));
24262 if (N->getNumValues() == 2) // Dead flag value?
24263 return DCI.CombineTo(N, Cond, SDValue());
24270 // Handle these cases:
24271 // (select (x != c), e, c) -> select (x != c), e, x),
24272 // (select (x == c), c, e) -> select (x == c), x, e)
24273 // where the c is an integer constant, and the "select" is the combination
24274 // of CMOV and CMP.
24276 // The rationale for this change is that the conditional-move from a constant
24277 // needs two instructions, however, conditional-move from a register needs
24278 // only one instruction.
24280 // CAVEAT: By replacing a constant with a symbolic value, it may obscure
24281 // some instruction-combining opportunities. This opt needs to be
24282 // postponed as late as possible.
24284 if (!DCI.isBeforeLegalize() && !DCI.isBeforeLegalizeOps()) {
24285 // the DCI.xxxx conditions are provided to postpone the optimization as
24286 // late as possible.
24288 ConstantSDNode *CmpAgainst = nullptr;
24289 if ((Cond.getOpcode() == X86ISD::CMP || Cond.getOpcode() == X86ISD::SUB) &&
24290 (CmpAgainst = dyn_cast<ConstantSDNode>(Cond.getOperand(1))) &&
24291 !isa<ConstantSDNode>(Cond.getOperand(0))) {
24293 if (CC == X86::COND_NE &&
24294 CmpAgainst == dyn_cast<ConstantSDNode>(FalseOp)) {
24295 CC = X86::GetOppositeBranchCondition(CC);
24296 std::swap(TrueOp, FalseOp);
24299 if (CC == X86::COND_E &&
24300 CmpAgainst == dyn_cast<ConstantSDNode>(TrueOp)) {
24301 SDValue Ops[] = { FalseOp, Cond.getOperand(0),
24302 DAG.getConstant(CC, DL, MVT::i8), Cond };
24303 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList (), Ops);
24308 // Fold and/or of setcc's to double CMOV:
24309 // (CMOV F, T, ((cc1 | cc2) != 0)) -> (CMOV (CMOV F, T, cc1), T, cc2)
24310 // (CMOV F, T, ((cc1 & cc2) != 0)) -> (CMOV (CMOV T, F, !cc1), F, !cc2)
24312 // This combine lets us generate:
24313 // cmovcc1 (jcc1 if we don't have CMOV)
24319 // cmovne (jne if we don't have CMOV)
24320 // When we can't use the CMOV instruction, it might increase branch
24322 // When we can use CMOV, or when there is no mispredict, this improves
24323 // throughput and reduces register pressure.
24325 if (CC == X86::COND_NE) {
24327 X86::CondCode CC0, CC1;
24329 if (checkBoolTestAndOrSetCCCombine(Cond, CC0, CC1, Flags, isAndSetCC)) {
24331 std::swap(FalseOp, TrueOp);
24332 CC0 = X86::GetOppositeBranchCondition(CC0);
24333 CC1 = X86::GetOppositeBranchCondition(CC1);
24336 SDValue LOps[] = {FalseOp, TrueOp, DAG.getConstant(CC0, DL, MVT::i8),
24338 SDValue LCMOV = DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), LOps);
24339 SDValue Ops[] = {LCMOV, TrueOp, DAG.getConstant(CC1, DL, MVT::i8), Flags};
24340 SDValue CMOV = DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), Ops);
24341 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), SDValue(CMOV.getNode(), 1));
24349 /// PerformMulCombine - Optimize a single multiply with constant into two
24350 /// in order to implement it with two cheaper instructions, e.g.
24351 /// LEA + SHL, LEA + LEA.
24352 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
24353 TargetLowering::DAGCombinerInfo &DCI) {
24354 // An imul is usually smaller than the alternative sequence.
24355 if (DAG.getMachineFunction().getFunction()->optForMinSize())
24358 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
24361 EVT VT = N->getValueType(0);
24362 if (VT != MVT::i64 && VT != MVT::i32)
24365 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
24368 uint64_t MulAmt = C->getZExtValue();
24369 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
24372 uint64_t MulAmt1 = 0;
24373 uint64_t MulAmt2 = 0;
24374 if ((MulAmt % 9) == 0) {
24376 MulAmt2 = MulAmt / 9;
24377 } else if ((MulAmt % 5) == 0) {
24379 MulAmt2 = MulAmt / 5;
24380 } else if ((MulAmt % 3) == 0) {
24382 MulAmt2 = MulAmt / 3;
24385 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
24388 if (isPowerOf2_64(MulAmt2) &&
24389 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
24390 // If second multiplifer is pow2, issue it first. We want the multiply by
24391 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
24393 std::swap(MulAmt1, MulAmt2);
24396 if (isPowerOf2_64(MulAmt1))
24397 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
24398 DAG.getConstant(Log2_64(MulAmt1), DL, MVT::i8));
24400 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
24401 DAG.getConstant(MulAmt1, DL, VT));
24403 if (isPowerOf2_64(MulAmt2))
24404 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
24405 DAG.getConstant(Log2_64(MulAmt2), DL, MVT::i8));
24407 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
24408 DAG.getConstant(MulAmt2, DL, VT));
24410 // Do not add new nodes to DAG combiner worklist.
24411 DCI.CombineTo(N, NewMul, false);
24416 static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) {
24417 SDValue N0 = N->getOperand(0);
24418 SDValue N1 = N->getOperand(1);
24419 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
24420 EVT VT = N0.getValueType();
24422 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2))
24423 // since the result of setcc_c is all zero's or all ones.
24424 if (VT.isInteger() && !VT.isVector() &&
24425 N1C && N0.getOpcode() == ISD::AND &&
24426 N0.getOperand(1).getOpcode() == ISD::Constant) {
24427 SDValue N00 = N0.getOperand(0);
24428 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
24429 APInt ShAmt = N1C->getAPIntValue();
24430 Mask = Mask.shl(ShAmt);
24431 bool MaskOK = false;
24432 // We can handle cases concerning bit-widening nodes containing setcc_c if
24433 // we carefully interrogate the mask to make sure we are semantics
24435 // The transform is not safe if the result of C1 << C2 exceeds the bitwidth
24436 // of the underlying setcc_c operation if the setcc_c was zero extended.
24437 // Consider the following example:
24438 // zext(setcc_c) -> i32 0x0000FFFF
24439 // c1 -> i32 0x0000FFFF
24440 // c2 -> i32 0x00000001
24441 // (shl (and (setcc_c), c1), c2) -> i32 0x0001FFFE
24442 // (and setcc_c, (c1 << c2)) -> i32 0x0000FFFE
24443 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
24445 } else if (N00.getOpcode() == ISD::SIGN_EXTEND &&
24446 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
24448 } else if ((N00.getOpcode() == ISD::ZERO_EXTEND ||
24449 N00.getOpcode() == ISD::ANY_EXTEND) &&
24450 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
24451 MaskOK = Mask.isIntN(N00.getOperand(0).getValueSizeInBits());
24453 if (MaskOK && Mask != 0) {
24455 return DAG.getNode(ISD::AND, DL, VT, N00, DAG.getConstant(Mask, DL, VT));
24459 // Hardware support for vector shifts is sparse which makes us scalarize the
24460 // vector operations in many cases. Also, on sandybridge ADD is faster than
24462 // (shl V, 1) -> add V,V
24463 if (auto *N1BV = dyn_cast<BuildVectorSDNode>(N1))
24464 if (auto *N1SplatC = N1BV->getConstantSplatNode()) {
24465 assert(N0.getValueType().isVector() && "Invalid vector shift type");
24466 // We shift all of the values by one. In many cases we do not have
24467 // hardware support for this operation. This is better expressed as an ADD
24469 if (N1SplatC->getAPIntValue() == 1)
24470 return DAG.getNode(ISD::ADD, SDLoc(N), VT, N0, N0);
24476 /// \brief Returns a vector of 0s if the node in input is a vector logical
24477 /// shift by a constant amount which is known to be bigger than or equal
24478 /// to the vector element size in bits.
24479 static SDValue performShiftToAllZeros(SDNode *N, SelectionDAG &DAG,
24480 const X86Subtarget *Subtarget) {
24481 EVT VT = N->getValueType(0);
24483 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16 &&
24484 (!Subtarget->hasInt256() ||
24485 (VT != MVT::v4i64 && VT != MVT::v8i32 && VT != MVT::v16i16)))
24488 SDValue Amt = N->getOperand(1);
24490 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Amt))
24491 if (auto *AmtSplat = AmtBV->getConstantSplatNode()) {
24492 APInt ShiftAmt = AmtSplat->getAPIntValue();
24493 unsigned MaxAmount =
24494 VT.getSimpleVT().getVectorElementType().getSizeInBits();
24496 // SSE2/AVX2 logical shifts always return a vector of 0s
24497 // if the shift amount is bigger than or equal to
24498 // the element size. The constant shift amount will be
24499 // encoded as a 8-bit immediate.
24500 if (ShiftAmt.trunc(8).uge(MaxAmount))
24501 return getZeroVector(VT, Subtarget, DAG, DL);
24507 /// PerformShiftCombine - Combine shifts.
24508 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
24509 TargetLowering::DAGCombinerInfo &DCI,
24510 const X86Subtarget *Subtarget) {
24511 if (N->getOpcode() == ISD::SHL)
24512 if (SDValue V = PerformSHLCombine(N, DAG))
24515 // Try to fold this logical shift into a zero vector.
24516 if (N->getOpcode() != ISD::SRA)
24517 if (SDValue V = performShiftToAllZeros(N, DAG, Subtarget))
24523 // CMPEQCombine - Recognize the distinctive (AND (setcc ...) (setcc ..))
24524 // where both setccs reference the same FP CMP, and rewrite for CMPEQSS
24525 // and friends. Likewise for OR -> CMPNEQSS.
24526 static SDValue CMPEQCombine(SDNode *N, SelectionDAG &DAG,
24527 TargetLowering::DAGCombinerInfo &DCI,
24528 const X86Subtarget *Subtarget) {
24531 // SSE1 supports CMP{eq|ne}SS, and SSE2 added CMP{eq|ne}SD, but
24532 // we're requiring SSE2 for both.
24533 if (Subtarget->hasSSE2() && isAndOrOfSetCCs(SDValue(N, 0U), opcode)) {
24534 SDValue N0 = N->getOperand(0);
24535 SDValue N1 = N->getOperand(1);
24536 SDValue CMP0 = N0->getOperand(1);
24537 SDValue CMP1 = N1->getOperand(1);
24540 // The SETCCs should both refer to the same CMP.
24541 if (CMP0.getOpcode() != X86ISD::CMP || CMP0 != CMP1)
24544 SDValue CMP00 = CMP0->getOperand(0);
24545 SDValue CMP01 = CMP0->getOperand(1);
24546 EVT VT = CMP00.getValueType();
24548 if (VT == MVT::f32 || VT == MVT::f64) {
24549 bool ExpectingFlags = false;
24550 // Check for any users that want flags:
24551 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
24552 !ExpectingFlags && UI != UE; ++UI)
24553 switch (UI->getOpcode()) {
24558 ExpectingFlags = true;
24560 case ISD::CopyToReg:
24561 case ISD::SIGN_EXTEND:
24562 case ISD::ZERO_EXTEND:
24563 case ISD::ANY_EXTEND:
24567 if (!ExpectingFlags) {
24568 enum X86::CondCode cc0 = (enum X86::CondCode)N0.getConstantOperandVal(0);
24569 enum X86::CondCode cc1 = (enum X86::CondCode)N1.getConstantOperandVal(0);
24571 if (cc1 == X86::COND_E || cc1 == X86::COND_NE) {
24572 X86::CondCode tmp = cc0;
24577 if ((cc0 == X86::COND_E && cc1 == X86::COND_NP) ||
24578 (cc0 == X86::COND_NE && cc1 == X86::COND_P)) {
24579 // FIXME: need symbolic constants for these magic numbers.
24580 // See X86ATTInstPrinter.cpp:printSSECC().
24581 unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4;
24582 if (Subtarget->hasAVX512()) {
24583 SDValue FSetCC = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CMP00,
24585 DAG.getConstant(x86cc, DL, MVT::i8));
24586 if (N->getValueType(0) != MVT::i1)
24587 return DAG.getNode(ISD::ZERO_EXTEND, DL, N->getValueType(0),
24591 SDValue OnesOrZeroesF = DAG.getNode(X86ISD::FSETCC, DL,
24592 CMP00.getValueType(), CMP00, CMP01,
24593 DAG.getConstant(x86cc, DL,
24596 bool is64BitFP = (CMP00.getValueType() == MVT::f64);
24597 MVT IntVT = is64BitFP ? MVT::i64 : MVT::i32;
24599 if (is64BitFP && !Subtarget->is64Bit()) {
24600 // On a 32-bit target, we cannot bitcast the 64-bit float to a
24601 // 64-bit integer, since that's not a legal type. Since
24602 // OnesOrZeroesF is all ones of all zeroes, we don't need all the
24603 // bits, but can do this little dance to extract the lowest 32 bits
24604 // and work with those going forward.
24605 SDValue Vector64 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2f64,
24607 SDValue Vector32 = DAG.getBitcast(MVT::v4f32, Vector64);
24608 OnesOrZeroesF = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32,
24609 Vector32, DAG.getIntPtrConstant(0, DL));
24613 SDValue OnesOrZeroesI = DAG.getBitcast(IntVT, OnesOrZeroesF);
24614 SDValue ANDed = DAG.getNode(ISD::AND, DL, IntVT, OnesOrZeroesI,
24615 DAG.getConstant(1, DL, IntVT));
24616 SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8,
24618 return OneBitOfTruth;
24626 /// CanFoldXORWithAllOnes - Test whether the XOR operand is a AllOnes vector
24627 /// so it can be folded inside ANDNP.
24628 static bool CanFoldXORWithAllOnes(const SDNode *N) {
24629 EVT VT = N->getValueType(0);
24631 // Match direct AllOnes for 128 and 256-bit vectors
24632 if (ISD::isBuildVectorAllOnes(N))
24635 // Look through a bit convert.
24636 if (N->getOpcode() == ISD::BITCAST)
24637 N = N->getOperand(0).getNode();
24639 // Sometimes the operand may come from a insert_subvector building a 256-bit
24641 if (VT.is256BitVector() &&
24642 N->getOpcode() == ISD::INSERT_SUBVECTOR) {
24643 SDValue V1 = N->getOperand(0);
24644 SDValue V2 = N->getOperand(1);
24646 if (V1.getOpcode() == ISD::INSERT_SUBVECTOR &&
24647 V1.getOperand(0).getOpcode() == ISD::UNDEF &&
24648 ISD::isBuildVectorAllOnes(V1.getOperand(1).getNode()) &&
24649 ISD::isBuildVectorAllOnes(V2.getNode()))
24656 // On AVX/AVX2 the type v8i1 is legalized to v8i16, which is an XMM sized
24657 // register. In most cases we actually compare or select YMM-sized registers
24658 // and mixing the two types creates horrible code. This method optimizes
24659 // some of the transition sequences.
24660 static SDValue WidenMaskArithmetic(SDNode *N, SelectionDAG &DAG,
24661 TargetLowering::DAGCombinerInfo &DCI,
24662 const X86Subtarget *Subtarget) {
24663 EVT VT = N->getValueType(0);
24664 if (!VT.is256BitVector())
24667 assert((N->getOpcode() == ISD::ANY_EXTEND ||
24668 N->getOpcode() == ISD::ZERO_EXTEND ||
24669 N->getOpcode() == ISD::SIGN_EXTEND) && "Invalid Node");
24671 SDValue Narrow = N->getOperand(0);
24672 EVT NarrowVT = Narrow->getValueType(0);
24673 if (!NarrowVT.is128BitVector())
24676 if (Narrow->getOpcode() != ISD::XOR &&
24677 Narrow->getOpcode() != ISD::AND &&
24678 Narrow->getOpcode() != ISD::OR)
24681 SDValue N0 = Narrow->getOperand(0);
24682 SDValue N1 = Narrow->getOperand(1);
24685 // The Left side has to be a trunc.
24686 if (N0.getOpcode() != ISD::TRUNCATE)
24689 // The type of the truncated inputs.
24690 EVT WideVT = N0->getOperand(0)->getValueType(0);
24694 // The right side has to be a 'trunc' or a constant vector.
24695 bool RHSTrunc = N1.getOpcode() == ISD::TRUNCATE;
24696 ConstantSDNode *RHSConstSplat = nullptr;
24697 if (auto *RHSBV = dyn_cast<BuildVectorSDNode>(N1))
24698 RHSConstSplat = RHSBV->getConstantSplatNode();
24699 if (!RHSTrunc && !RHSConstSplat)
24702 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
24704 if (!TLI.isOperationLegalOrPromote(Narrow->getOpcode(), WideVT))
24707 // Set N0 and N1 to hold the inputs to the new wide operation.
24708 N0 = N0->getOperand(0);
24709 if (RHSConstSplat) {
24710 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, WideVT.getVectorElementType(),
24711 SDValue(RHSConstSplat, 0));
24712 SmallVector<SDValue, 8> C(WideVT.getVectorNumElements(), N1);
24713 N1 = DAG.getNode(ISD::BUILD_VECTOR, DL, WideVT, C);
24714 } else if (RHSTrunc) {
24715 N1 = N1->getOperand(0);
24718 // Generate the wide operation.
24719 SDValue Op = DAG.getNode(Narrow->getOpcode(), DL, WideVT, N0, N1);
24720 unsigned Opcode = N->getOpcode();
24722 case ISD::ANY_EXTEND:
24724 case ISD::ZERO_EXTEND: {
24725 unsigned InBits = NarrowVT.getScalarSizeInBits();
24726 APInt Mask = APInt::getAllOnesValue(InBits);
24727 Mask = Mask.zext(VT.getScalarSizeInBits());
24728 return DAG.getNode(ISD::AND, DL, VT,
24729 Op, DAG.getConstant(Mask, DL, VT));
24731 case ISD::SIGN_EXTEND:
24732 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT,
24733 Op, DAG.getValueType(NarrowVT));
24735 llvm_unreachable("Unexpected opcode");
24739 static SDValue VectorZextCombine(SDNode *N, SelectionDAG &DAG,
24740 TargetLowering::DAGCombinerInfo &DCI,
24741 const X86Subtarget *Subtarget) {
24742 SDValue N0 = N->getOperand(0);
24743 SDValue N1 = N->getOperand(1);
24746 // A vector zext_in_reg may be represented as a shuffle,
24747 // feeding into a bitcast (this represents anyext) feeding into
24748 // an and with a mask.
24749 // We'd like to try to combine that into a shuffle with zero
24750 // plus a bitcast, removing the and.
24751 if (N0.getOpcode() != ISD::BITCAST ||
24752 N0.getOperand(0).getOpcode() != ISD::VECTOR_SHUFFLE)
24755 // The other side of the AND should be a splat of 2^C, where C
24756 // is the number of bits in the source type.
24757 if (N1.getOpcode() == ISD::BITCAST)
24758 N1 = N1.getOperand(0);
24759 if (N1.getOpcode() != ISD::BUILD_VECTOR)
24761 BuildVectorSDNode *Vector = cast<BuildVectorSDNode>(N1);
24763 ShuffleVectorSDNode *Shuffle = cast<ShuffleVectorSDNode>(N0.getOperand(0));
24764 EVT SrcType = Shuffle->getValueType(0);
24766 // We expect a single-source shuffle
24767 if (Shuffle->getOperand(1)->getOpcode() != ISD::UNDEF)
24770 unsigned SrcSize = SrcType.getScalarSizeInBits();
24772 APInt SplatValue, SplatUndef;
24773 unsigned SplatBitSize;
24775 if (!Vector->isConstantSplat(SplatValue, SplatUndef,
24776 SplatBitSize, HasAnyUndefs))
24779 unsigned ResSize = N1.getValueType().getScalarSizeInBits();
24780 // Make sure the splat matches the mask we expect
24781 if (SplatBitSize > ResSize ||
24782 (SplatValue + 1).exactLogBase2() != (int)SrcSize)
24785 // Make sure the input and output size make sense
24786 if (SrcSize >= ResSize || ResSize % SrcSize)
24789 // We expect a shuffle of the form <0, u, u, u, 1, u, u, u...>
24790 // The number of u's between each two values depends on the ratio between
24791 // the source and dest type.
24792 unsigned ZextRatio = ResSize / SrcSize;
24793 bool IsZext = true;
24794 for (unsigned i = 0; i < SrcType.getVectorNumElements(); ++i) {
24795 if (i % ZextRatio) {
24796 if (Shuffle->getMaskElt(i) > 0) {
24802 if (Shuffle->getMaskElt(i) != (int)(i / ZextRatio)) {
24803 // Expected element number
24813 // Ok, perform the transformation - replace the shuffle with
24814 // a shuffle of the form <0, k, k, k, 1, k, k, k> with zero
24815 // (instead of undef) where the k elements come from the zero vector.
24816 SmallVector<int, 8> Mask;
24817 unsigned NumElems = SrcType.getVectorNumElements();
24818 for (unsigned i = 0; i < NumElems; ++i)
24820 Mask.push_back(NumElems);
24822 Mask.push_back(i / ZextRatio);
24824 SDValue NewShuffle = DAG.getVectorShuffle(Shuffle->getValueType(0), DL,
24825 Shuffle->getOperand(0), DAG.getConstant(0, DL, SrcType), Mask);
24826 return DAG.getBitcast(N0.getValueType(), NewShuffle);
24829 /// If both input operands of a logic op are being cast from floating point
24830 /// types, try to convert this into a floating point logic node to avoid
24831 /// unnecessary moves from SSE to integer registers.
24832 static SDValue convertIntLogicToFPLogic(SDNode *N, SelectionDAG &DAG,
24833 const X86Subtarget *Subtarget) {
24834 unsigned FPOpcode = ISD::DELETED_NODE;
24835 if (N->getOpcode() == ISD::AND)
24836 FPOpcode = X86ISD::FAND;
24837 else if (N->getOpcode() == ISD::OR)
24838 FPOpcode = X86ISD::FOR;
24839 else if (N->getOpcode() == ISD::XOR)
24840 FPOpcode = X86ISD::FXOR;
24842 assert(FPOpcode != ISD::DELETED_NODE &&
24843 "Unexpected input node for FP logic conversion");
24845 EVT VT = N->getValueType(0);
24846 SDValue N0 = N->getOperand(0);
24847 SDValue N1 = N->getOperand(1);
24849 if (N0.getOpcode() == ISD::BITCAST && N1.getOpcode() == ISD::BITCAST &&
24850 ((Subtarget->hasSSE1() && VT == MVT::i32) ||
24851 (Subtarget->hasSSE2() && VT == MVT::i64))) {
24852 SDValue N00 = N0.getOperand(0);
24853 SDValue N10 = N1.getOperand(0);
24854 EVT N00Type = N00.getValueType();
24855 EVT N10Type = N10.getValueType();
24856 if (N00Type.isFloatingPoint() && N10Type.isFloatingPoint()) {
24857 SDValue FPLogic = DAG.getNode(FPOpcode, DL, N00Type, N00, N10);
24858 return DAG.getBitcast(VT, FPLogic);
24864 static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG,
24865 TargetLowering::DAGCombinerInfo &DCI,
24866 const X86Subtarget *Subtarget) {
24867 if (DCI.isBeforeLegalizeOps())
24870 if (SDValue Zext = VectorZextCombine(N, DAG, DCI, Subtarget))
24873 if (SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget))
24876 if (SDValue FPLogic = convertIntLogicToFPLogic(N, DAG, Subtarget))
24879 EVT VT = N->getValueType(0);
24880 SDValue N0 = N->getOperand(0);
24881 SDValue N1 = N->getOperand(1);
24884 // Create BEXTR instructions
24885 // BEXTR is ((X >> imm) & (2**size-1))
24886 if (VT == MVT::i32 || VT == MVT::i64) {
24887 // Check for BEXTR.
24888 if ((Subtarget->hasBMI() || Subtarget->hasTBM()) &&
24889 (N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::SRL)) {
24890 ConstantSDNode *MaskNode = dyn_cast<ConstantSDNode>(N1);
24891 ConstantSDNode *ShiftNode = dyn_cast<ConstantSDNode>(N0.getOperand(1));
24892 if (MaskNode && ShiftNode) {
24893 uint64_t Mask = MaskNode->getZExtValue();
24894 uint64_t Shift = ShiftNode->getZExtValue();
24895 if (isMask_64(Mask)) {
24896 uint64_t MaskSize = countPopulation(Mask);
24897 if (Shift + MaskSize <= VT.getSizeInBits())
24898 return DAG.getNode(X86ISD::BEXTR, DL, VT, N0.getOperand(0),
24899 DAG.getConstant(Shift | (MaskSize << 8), DL,
24908 // Want to form ANDNP nodes:
24909 // 1) In the hopes of then easily combining them with OR and AND nodes
24910 // to form PBLEND/PSIGN.
24911 // 2) To match ANDN packed intrinsics
24912 if (VT != MVT::v2i64 && VT != MVT::v4i64)
24915 // Check LHS for vnot
24916 if (N0.getOpcode() == ISD::XOR &&
24917 //ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode()))
24918 CanFoldXORWithAllOnes(N0.getOperand(1).getNode()))
24919 return DAG.getNode(X86ISD::ANDNP, DL, VT, N0.getOperand(0), N1);
24921 // Check RHS for vnot
24922 if (N1.getOpcode() == ISD::XOR &&
24923 //ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode()))
24924 CanFoldXORWithAllOnes(N1.getOperand(1).getNode()))
24925 return DAG.getNode(X86ISD::ANDNP, DL, VT, N1.getOperand(0), N0);
24930 static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
24931 TargetLowering::DAGCombinerInfo &DCI,
24932 const X86Subtarget *Subtarget) {
24933 if (DCI.isBeforeLegalizeOps())
24936 if (SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget))
24939 if (SDValue FPLogic = convertIntLogicToFPLogic(N, DAG, Subtarget))
24942 SDValue N0 = N->getOperand(0);
24943 SDValue N1 = N->getOperand(1);
24944 EVT VT = N->getValueType(0);
24946 // look for psign/blend
24947 if (VT == MVT::v2i64 || VT == MVT::v4i64) {
24948 if (!Subtarget->hasSSSE3() ||
24949 (VT == MVT::v4i64 && !Subtarget->hasInt256()))
24952 // Canonicalize pandn to RHS
24953 if (N0.getOpcode() == X86ISD::ANDNP)
24955 // or (and (m, y), (pandn m, x))
24956 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::ANDNP) {
24957 SDValue Mask = N1.getOperand(0);
24958 SDValue X = N1.getOperand(1);
24960 if (N0.getOperand(0) == Mask)
24961 Y = N0.getOperand(1);
24962 if (N0.getOperand(1) == Mask)
24963 Y = N0.getOperand(0);
24965 // Check to see if the mask appeared in both the AND and ANDNP and
24969 // Validate that X, Y, and Mask are BIT_CONVERTS, and see through them.
24970 // Look through mask bitcast.
24971 if (Mask.getOpcode() == ISD::BITCAST)
24972 Mask = Mask.getOperand(0);
24973 if (X.getOpcode() == ISD::BITCAST)
24974 X = X.getOperand(0);
24975 if (Y.getOpcode() == ISD::BITCAST)
24976 Y = Y.getOperand(0);
24978 EVT MaskVT = Mask.getValueType();
24980 // Validate that the Mask operand is a vector sra node.
24981 // FIXME: what to do for bytes, since there is a psignb/pblendvb, but
24982 // there is no psrai.b
24983 unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits();
24984 unsigned SraAmt = ~0;
24985 if (Mask.getOpcode() == ISD::SRA) {
24986 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Mask.getOperand(1)))
24987 if (auto *AmtConst = AmtBV->getConstantSplatNode())
24988 SraAmt = AmtConst->getZExtValue();
24989 } else if (Mask.getOpcode() == X86ISD::VSRAI) {
24990 SDValue SraC = Mask.getOperand(1);
24991 SraAmt = cast<ConstantSDNode>(SraC)->getZExtValue();
24993 if ((SraAmt + 1) != EltBits)
24998 // Now we know we at least have a plendvb with the mask val. See if
24999 // we can form a psignb/w/d.
25000 // psign = x.type == y.type == mask.type && y = sub(0, x);
25001 if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X &&
25002 ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) &&
25003 X.getValueType() == MaskVT && Y.getValueType() == MaskVT) {
25004 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
25005 "Unsupported VT for PSIGN");
25006 Mask = DAG.getNode(X86ISD::PSIGN, DL, MaskVT, X, Mask.getOperand(0));
25007 return DAG.getBitcast(VT, Mask);
25009 // PBLENDVB only available on SSE 4.1
25010 if (!Subtarget->hasSSE41())
25013 MVT BlendVT = (VT == MVT::v4i64) ? MVT::v32i8 : MVT::v16i8;
25015 X = DAG.getBitcast(BlendVT, X);
25016 Y = DAG.getBitcast(BlendVT, Y);
25017 Mask = DAG.getBitcast(BlendVT, Mask);
25018 Mask = DAG.getNode(ISD::VSELECT, DL, BlendVT, Mask, Y, X);
25019 return DAG.getBitcast(VT, Mask);
25023 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64)
25026 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
25027 bool OptForSize = DAG.getMachineFunction().getFunction()->optForSize();
25029 // SHLD/SHRD instructions have lower register pressure, but on some
25030 // platforms they have higher latency than the equivalent
25031 // series of shifts/or that would otherwise be generated.
25032 // Don't fold (or (x << c) | (y >> (64 - c))) if SHLD/SHRD instructions
25033 // have higher latencies and we are not optimizing for size.
25034 if (!OptForSize && Subtarget->isSHLDSlow())
25037 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
25039 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
25041 if (!N0.hasOneUse() || !N1.hasOneUse())
25044 SDValue ShAmt0 = N0.getOperand(1);
25045 if (ShAmt0.getValueType() != MVT::i8)
25047 SDValue ShAmt1 = N1.getOperand(1);
25048 if (ShAmt1.getValueType() != MVT::i8)
25050 if (ShAmt0.getOpcode() == ISD::TRUNCATE)
25051 ShAmt0 = ShAmt0.getOperand(0);
25052 if (ShAmt1.getOpcode() == ISD::TRUNCATE)
25053 ShAmt1 = ShAmt1.getOperand(0);
25056 unsigned Opc = X86ISD::SHLD;
25057 SDValue Op0 = N0.getOperand(0);
25058 SDValue Op1 = N1.getOperand(0);
25059 if (ShAmt0.getOpcode() == ISD::SUB) {
25060 Opc = X86ISD::SHRD;
25061 std::swap(Op0, Op1);
25062 std::swap(ShAmt0, ShAmt1);
25065 unsigned Bits = VT.getSizeInBits();
25066 if (ShAmt1.getOpcode() == ISD::SUB) {
25067 SDValue Sum = ShAmt1.getOperand(0);
25068 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) {
25069 SDValue ShAmt1Op1 = ShAmt1.getOperand(1);
25070 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE)
25071 ShAmt1Op1 = ShAmt1Op1.getOperand(0);
25072 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0)
25073 return DAG.getNode(Opc, DL, VT,
25075 DAG.getNode(ISD::TRUNCATE, DL,
25078 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) {
25079 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0);
25081 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits)
25082 return DAG.getNode(Opc, DL, VT,
25083 N0.getOperand(0), N1.getOperand(0),
25084 DAG.getNode(ISD::TRUNCATE, DL,
25091 // Generate NEG and CMOV for integer abs.
25092 static SDValue performIntegerAbsCombine(SDNode *N, SelectionDAG &DAG) {
25093 EVT VT = N->getValueType(0);
25095 // Since X86 does not have CMOV for 8-bit integer, we don't convert
25096 // 8-bit integer abs to NEG and CMOV.
25097 if (VT.isInteger() && VT.getSizeInBits() == 8)
25100 SDValue N0 = N->getOperand(0);
25101 SDValue N1 = N->getOperand(1);
25104 // Check pattern of XOR(ADD(X,Y), Y) where Y is SRA(X, size(X)-1)
25105 // and change it to SUB and CMOV.
25106 if (VT.isInteger() && N->getOpcode() == ISD::XOR &&
25107 N0.getOpcode() == ISD::ADD &&
25108 N0.getOperand(1) == N1 &&
25109 N1.getOpcode() == ISD::SRA &&
25110 N1.getOperand(0) == N0.getOperand(0))
25111 if (ConstantSDNode *Y1C = dyn_cast<ConstantSDNode>(N1.getOperand(1)))
25112 if (Y1C->getAPIntValue() == VT.getSizeInBits()-1) {
25113 // Generate SUB & CMOV.
25114 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, DAG.getVTList(VT, MVT::i32),
25115 DAG.getConstant(0, DL, VT), N0.getOperand(0));
25117 SDValue Ops[] = { N0.getOperand(0), Neg,
25118 DAG.getConstant(X86::COND_GE, DL, MVT::i8),
25119 SDValue(Neg.getNode(), 1) };
25120 return DAG.getNode(X86ISD::CMOV, DL, DAG.getVTList(VT, MVT::Glue), Ops);
25125 // Try to turn tests against the signbit in the form of:
25126 // XOR(TRUNCATE(SRL(X, size(X)-1)), 1)
25129 static SDValue foldXorTruncShiftIntoCmp(SDNode *N, SelectionDAG &DAG) {
25130 // This is only worth doing if the output type is i8.
25131 if (N->getValueType(0) != MVT::i8)
25134 SDValue N0 = N->getOperand(0);
25135 SDValue N1 = N->getOperand(1);
25137 // We should be performing an xor against a truncated shift.
25138 if (N0.getOpcode() != ISD::TRUNCATE || !N0.hasOneUse())
25141 // Make sure we are performing an xor against one.
25142 if (!isa<ConstantSDNode>(N1) || !cast<ConstantSDNode>(N1)->isOne())
25145 // SetCC on x86 zero extends so only act on this if it's a logical shift.
25146 SDValue Shift = N0.getOperand(0);
25147 if (Shift.getOpcode() != ISD::SRL || !Shift.hasOneUse())
25150 // Make sure we are truncating from one of i16, i32 or i64.
25151 EVT ShiftTy = Shift.getValueType();
25152 if (ShiftTy != MVT::i16 && ShiftTy != MVT::i32 && ShiftTy != MVT::i64)
25155 // Make sure the shift amount extracts the sign bit.
25156 if (!isa<ConstantSDNode>(Shift.getOperand(1)) ||
25157 Shift.getConstantOperandVal(1) != ShiftTy.getSizeInBits() - 1)
25160 // Create a greater-than comparison against -1.
25161 // N.B. Using SETGE against 0 works but we want a canonical looking
25162 // comparison, using SETGT matches up with what TranslateX86CC.
25164 SDValue ShiftOp = Shift.getOperand(0);
25165 EVT ShiftOpTy = ShiftOp.getValueType();
25166 SDValue Cond = DAG.getSetCC(DL, MVT::i8, ShiftOp,
25167 DAG.getConstant(-1, DL, ShiftOpTy), ISD::SETGT);
25171 static SDValue PerformXorCombine(SDNode *N, SelectionDAG &DAG,
25172 TargetLowering::DAGCombinerInfo &DCI,
25173 const X86Subtarget *Subtarget) {
25174 if (DCI.isBeforeLegalizeOps())
25177 if (SDValue RV = foldXorTruncShiftIntoCmp(N, DAG))
25180 if (Subtarget->hasCMov())
25181 if (SDValue RV = performIntegerAbsCombine(N, DAG))
25184 if (SDValue FPLogic = convertIntLogicToFPLogic(N, DAG, Subtarget))
25190 /// PerformLOADCombine - Do target-specific dag combines on LOAD nodes.
25191 static SDValue PerformLOADCombine(SDNode *N, SelectionDAG &DAG,
25192 TargetLowering::DAGCombinerInfo &DCI,
25193 const X86Subtarget *Subtarget) {
25194 LoadSDNode *Ld = cast<LoadSDNode>(N);
25195 EVT RegVT = Ld->getValueType(0);
25196 EVT MemVT = Ld->getMemoryVT();
25198 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
25200 // For chips with slow 32-byte unaligned loads, break the 32-byte operation
25201 // into two 16-byte operations.
25202 ISD::LoadExtType Ext = Ld->getExtensionType();
25204 unsigned AddressSpace = Ld->getAddressSpace();
25205 unsigned Alignment = Ld->getAlignment();
25206 if (RegVT.is256BitVector() && !DCI.isBeforeLegalizeOps() &&
25207 Ext == ISD::NON_EXTLOAD &&
25208 TLI.allowsMemoryAccess(*DAG.getContext(), DAG.getDataLayout(), RegVT,
25209 AddressSpace, Alignment, &Fast) && !Fast) {
25210 unsigned NumElems = RegVT.getVectorNumElements();
25214 SDValue Ptr = Ld->getBasePtr();
25215 SDValue Increment =
25216 DAG.getConstant(16, dl, TLI.getPointerTy(DAG.getDataLayout()));
25218 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
25220 SDValue Load1 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
25221 Ld->getPointerInfo(), Ld->isVolatile(),
25222 Ld->isNonTemporal(), Ld->isInvariant(),
25224 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
25225 SDValue Load2 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
25226 Ld->getPointerInfo(), Ld->isVolatile(),
25227 Ld->isNonTemporal(), Ld->isInvariant(),
25228 std::min(16U, Alignment));
25229 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
25231 Load2.getValue(1));
25233 SDValue NewVec = DAG.getUNDEF(RegVT);
25234 NewVec = Insert128BitVector(NewVec, Load1, 0, DAG, dl);
25235 NewVec = Insert128BitVector(NewVec, Load2, NumElems/2, DAG, dl);
25236 return DCI.CombineTo(N, NewVec, TF, true);
25242 /// PerformMLOADCombine - Resolve extending loads
25243 static SDValue PerformMLOADCombine(SDNode *N, SelectionDAG &DAG,
25244 TargetLowering::DAGCombinerInfo &DCI,
25245 const X86Subtarget *Subtarget) {
25246 MaskedLoadSDNode *Mld = cast<MaskedLoadSDNode>(N);
25247 if (Mld->getExtensionType() != ISD::SEXTLOAD)
25250 EVT VT = Mld->getValueType(0);
25251 unsigned NumElems = VT.getVectorNumElements();
25252 EVT LdVT = Mld->getMemoryVT();
25255 assert(LdVT != VT && "Cannot extend to the same type");
25256 unsigned ToSz = VT.getVectorElementType().getSizeInBits();
25257 unsigned FromSz = LdVT.getVectorElementType().getSizeInBits();
25258 // From, To sizes and ElemCount must be pow of two
25259 assert (isPowerOf2_32(NumElems * FromSz * ToSz) &&
25260 "Unexpected size for extending masked load");
25262 unsigned SizeRatio = ToSz / FromSz;
25263 assert(SizeRatio * NumElems * FromSz == VT.getSizeInBits());
25265 // Create a type on which we perform the shuffle
25266 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
25267 LdVT.getScalarType(), NumElems*SizeRatio);
25268 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
25270 // Convert Src0 value
25271 SDValue WideSrc0 = DAG.getBitcast(WideVecVT, Mld->getSrc0());
25272 if (Mld->getSrc0().getOpcode() != ISD::UNDEF) {
25273 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
25274 for (unsigned i = 0; i != NumElems; ++i)
25275 ShuffleVec[i] = i * SizeRatio;
25277 // Can't shuffle using an illegal type.
25278 assert(DAG.getTargetLoweringInfo().isTypeLegal(WideVecVT) &&
25279 "WideVecVT should be legal");
25280 WideSrc0 = DAG.getVectorShuffle(WideVecVT, dl, WideSrc0,
25281 DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
25283 // Prepare the new mask
25285 SDValue Mask = Mld->getMask();
25286 if (Mask.getValueType() == VT) {
25287 // Mask and original value have the same type
25288 NewMask = DAG.getBitcast(WideVecVT, Mask);
25289 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
25290 for (unsigned i = 0; i != NumElems; ++i)
25291 ShuffleVec[i] = i * SizeRatio;
25292 for (unsigned i = NumElems; i != NumElems*SizeRatio; ++i)
25293 ShuffleVec[i] = NumElems*SizeRatio;
25294 NewMask = DAG.getVectorShuffle(WideVecVT, dl, NewMask,
25295 DAG.getConstant(0, dl, WideVecVT),
25299 assert(Mask.getValueType().getVectorElementType() == MVT::i1);
25300 unsigned WidenNumElts = NumElems*SizeRatio;
25301 unsigned MaskNumElts = VT.getVectorNumElements();
25302 EVT NewMaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
25305 unsigned NumConcat = WidenNumElts / MaskNumElts;
25306 SmallVector<SDValue, 16> Ops(NumConcat);
25307 SDValue ZeroVal = DAG.getConstant(0, dl, Mask.getValueType());
25309 for (unsigned i = 1; i != NumConcat; ++i)
25312 NewMask = DAG.getNode(ISD::CONCAT_VECTORS, dl, NewMaskVT, Ops);
25315 SDValue WideLd = DAG.getMaskedLoad(WideVecVT, dl, Mld->getChain(),
25316 Mld->getBasePtr(), NewMask, WideSrc0,
25317 Mld->getMemoryVT(), Mld->getMemOperand(),
25319 SDValue NewVec = DAG.getNode(X86ISD::VSEXT, dl, VT, WideLd);
25320 return DCI.CombineTo(N, NewVec, WideLd.getValue(1), true);
25322 /// PerformMSTORECombine - Resolve truncating stores
25323 static SDValue PerformMSTORECombine(SDNode *N, SelectionDAG &DAG,
25324 const X86Subtarget *Subtarget) {
25325 MaskedStoreSDNode *Mst = cast<MaskedStoreSDNode>(N);
25326 if (!Mst->isTruncatingStore())
25329 EVT VT = Mst->getValue().getValueType();
25330 unsigned NumElems = VT.getVectorNumElements();
25331 EVT StVT = Mst->getMemoryVT();
25334 assert(StVT != VT && "Cannot truncate to the same type");
25335 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
25336 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
25338 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
25340 // The truncating store is legal in some cases. For example
25341 // vpmovqb, vpmovqw, vpmovqd, vpmovdb, vpmovdw
25342 // are designated for truncate store.
25343 // In this case we don't need any further transformations.
25344 if (TLI.isTruncStoreLegal(VT, StVT))
25347 // From, To sizes and ElemCount must be pow of two
25348 assert (isPowerOf2_32(NumElems * FromSz * ToSz) &&
25349 "Unexpected size for truncating masked store");
25350 // We are going to use the original vector elt for storing.
25351 // Accumulated smaller vector elements must be a multiple of the store size.
25352 assert (((NumElems * FromSz) % ToSz) == 0 &&
25353 "Unexpected ratio for truncating masked store");
25355 unsigned SizeRatio = FromSz / ToSz;
25356 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
25358 // Create a type on which we perform the shuffle
25359 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
25360 StVT.getScalarType(), NumElems*SizeRatio);
25362 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
25364 SDValue WideVec = DAG.getBitcast(WideVecVT, Mst->getValue());
25365 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
25366 for (unsigned i = 0; i != NumElems; ++i)
25367 ShuffleVec[i] = i * SizeRatio;
25369 // Can't shuffle using an illegal type.
25370 assert(DAG.getTargetLoweringInfo().isTypeLegal(WideVecVT) &&
25371 "WideVecVT should be legal");
25373 SDValue TruncatedVal = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
25374 DAG.getUNDEF(WideVecVT),
25378 SDValue Mask = Mst->getMask();
25379 if (Mask.getValueType() == VT) {
25380 // Mask and original value have the same type
25381 NewMask = DAG.getBitcast(WideVecVT, Mask);
25382 for (unsigned i = 0; i != NumElems; ++i)
25383 ShuffleVec[i] = i * SizeRatio;
25384 for (unsigned i = NumElems; i != NumElems*SizeRatio; ++i)
25385 ShuffleVec[i] = NumElems*SizeRatio;
25386 NewMask = DAG.getVectorShuffle(WideVecVT, dl, NewMask,
25387 DAG.getConstant(0, dl, WideVecVT),
25391 assert(Mask.getValueType().getVectorElementType() == MVT::i1);
25392 unsigned WidenNumElts = NumElems*SizeRatio;
25393 unsigned MaskNumElts = VT.getVectorNumElements();
25394 EVT NewMaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
25397 unsigned NumConcat = WidenNumElts / MaskNumElts;
25398 SmallVector<SDValue, 16> Ops(NumConcat);
25399 SDValue ZeroVal = DAG.getConstant(0, dl, Mask.getValueType());
25401 for (unsigned i = 1; i != NumConcat; ++i)
25404 NewMask = DAG.getNode(ISD::CONCAT_VECTORS, dl, NewMaskVT, Ops);
25407 return DAG.getMaskedStore(Mst->getChain(), dl, TruncatedVal, Mst->getBasePtr(),
25408 NewMask, StVT, Mst->getMemOperand(), false);
25410 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
25411 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
25412 const X86Subtarget *Subtarget) {
25413 StoreSDNode *St = cast<StoreSDNode>(N);
25414 EVT VT = St->getValue().getValueType();
25415 EVT StVT = St->getMemoryVT();
25417 SDValue StoredVal = St->getOperand(1);
25418 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
25420 // If we are saving a concatenation of two XMM registers and 32-byte stores
25421 // are slow, such as on Sandy Bridge, perform two 16-byte stores.
25423 unsigned AddressSpace = St->getAddressSpace();
25424 unsigned Alignment = St->getAlignment();
25425 if (VT.is256BitVector() && StVT == VT &&
25426 TLI.allowsMemoryAccess(*DAG.getContext(), DAG.getDataLayout(), VT,
25427 AddressSpace, Alignment, &Fast) && !Fast) {
25428 unsigned NumElems = VT.getVectorNumElements();
25432 SDValue Value0 = Extract128BitVector(StoredVal, 0, DAG, dl);
25433 SDValue Value1 = Extract128BitVector(StoredVal, NumElems/2, DAG, dl);
25436 DAG.getConstant(16, dl, TLI.getPointerTy(DAG.getDataLayout()));
25437 SDValue Ptr0 = St->getBasePtr();
25438 SDValue Ptr1 = DAG.getNode(ISD::ADD, dl, Ptr0.getValueType(), Ptr0, Stride);
25440 SDValue Ch0 = DAG.getStore(St->getChain(), dl, Value0, Ptr0,
25441 St->getPointerInfo(), St->isVolatile(),
25442 St->isNonTemporal(), Alignment);
25443 SDValue Ch1 = DAG.getStore(St->getChain(), dl, Value1, Ptr1,
25444 St->getPointerInfo(), St->isVolatile(),
25445 St->isNonTemporal(),
25446 std::min(16U, Alignment));
25447 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ch0, Ch1);
25450 // Optimize trunc store (of multiple scalars) to shuffle and store.
25451 // First, pack all of the elements in one place. Next, store to memory
25452 // in fewer chunks.
25453 if (St->isTruncatingStore() && VT.isVector()) {
25454 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
25455 unsigned NumElems = VT.getVectorNumElements();
25456 assert(StVT != VT && "Cannot truncate to the same type");
25457 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
25458 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
25460 // The truncating store is legal in some cases. For example
25461 // vpmovqb, vpmovqw, vpmovqd, vpmovdb, vpmovdw
25462 // are designated for truncate store.
25463 // In this case we don't need any further transformations.
25464 if (TLI.isTruncStoreLegal(VT, StVT))
25467 // From, To sizes and ElemCount must be pow of two
25468 if (!isPowerOf2_32(NumElems * FromSz * ToSz)) return SDValue();
25469 // We are going to use the original vector elt for storing.
25470 // Accumulated smaller vector elements must be a multiple of the store size.
25471 if (0 != (NumElems * FromSz) % ToSz) return SDValue();
25473 unsigned SizeRatio = FromSz / ToSz;
25475 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
25477 // Create a type on which we perform the shuffle
25478 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
25479 StVT.getScalarType(), NumElems*SizeRatio);
25481 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
25483 SDValue WideVec = DAG.getBitcast(WideVecVT, St->getValue());
25484 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
25485 for (unsigned i = 0; i != NumElems; ++i)
25486 ShuffleVec[i] = i * SizeRatio;
25488 // Can't shuffle using an illegal type.
25489 if (!TLI.isTypeLegal(WideVecVT))
25492 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
25493 DAG.getUNDEF(WideVecVT),
25495 // At this point all of the data is stored at the bottom of the
25496 // register. We now need to save it to mem.
25498 // Find the largest store unit
25499 MVT StoreType = MVT::i8;
25500 for (MVT Tp : MVT::integer_valuetypes()) {
25501 if (TLI.isTypeLegal(Tp) && Tp.getSizeInBits() <= NumElems * ToSz)
25505 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
25506 if (TLI.isTypeLegal(MVT::f64) && StoreType.getSizeInBits() < 64 &&
25507 (64 <= NumElems * ToSz))
25508 StoreType = MVT::f64;
25510 // Bitcast the original vector into a vector of store-size units
25511 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(),
25512 StoreType, VT.getSizeInBits()/StoreType.getSizeInBits());
25513 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits());
25514 SDValue ShuffWide = DAG.getBitcast(StoreVecVT, Shuff);
25515 SmallVector<SDValue, 8> Chains;
25516 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits() / 8, dl,
25517 TLI.getPointerTy(DAG.getDataLayout()));
25518 SDValue Ptr = St->getBasePtr();
25520 // Perform one or more big stores into memory.
25521 for (unsigned i=0, e=(ToSz*NumElems)/StoreType.getSizeInBits(); i!=e; ++i) {
25522 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
25523 StoreType, ShuffWide,
25524 DAG.getIntPtrConstant(i, dl));
25525 SDValue Ch = DAG.getStore(St->getChain(), dl, SubVec, Ptr,
25526 St->getPointerInfo(), St->isVolatile(),
25527 St->isNonTemporal(), St->getAlignment());
25528 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
25529 Chains.push_back(Ch);
25532 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
25535 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
25536 // the FP state in cases where an emms may be missing.
25537 // A preferable solution to the general problem is to figure out the right
25538 // places to insert EMMS. This qualifies as a quick hack.
25540 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
25541 if (VT.getSizeInBits() != 64)
25544 const Function *F = DAG.getMachineFunction().getFunction();
25545 bool NoImplicitFloatOps = F->hasFnAttribute(Attribute::NoImplicitFloat);
25547 !Subtarget->useSoftFloat() && !NoImplicitFloatOps && Subtarget->hasSSE2();
25548 if ((VT.isVector() ||
25549 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
25550 isa<LoadSDNode>(St->getValue()) &&
25551 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
25552 St->getChain().hasOneUse() && !St->isVolatile()) {
25553 SDNode* LdVal = St->getValue().getNode();
25554 LoadSDNode *Ld = nullptr;
25555 int TokenFactorIndex = -1;
25556 SmallVector<SDValue, 8> Ops;
25557 SDNode* ChainVal = St->getChain().getNode();
25558 // Must be a store of a load. We currently handle two cases: the load
25559 // is a direct child, and it's under an intervening TokenFactor. It is
25560 // possible to dig deeper under nested TokenFactors.
25561 if (ChainVal == LdVal)
25562 Ld = cast<LoadSDNode>(St->getChain());
25563 else if (St->getValue().hasOneUse() &&
25564 ChainVal->getOpcode() == ISD::TokenFactor) {
25565 for (unsigned i = 0, e = ChainVal->getNumOperands(); i != e; ++i) {
25566 if (ChainVal->getOperand(i).getNode() == LdVal) {
25567 TokenFactorIndex = i;
25568 Ld = cast<LoadSDNode>(St->getValue());
25570 Ops.push_back(ChainVal->getOperand(i));
25574 if (!Ld || !ISD::isNormalLoad(Ld))
25577 // If this is not the MMX case, i.e. we are just turning i64 load/store
25578 // into f64 load/store, avoid the transformation if there are multiple
25579 // uses of the loaded value.
25580 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
25585 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
25586 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
25588 if (Subtarget->is64Bit() || F64IsLegal) {
25589 MVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
25590 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(),
25591 Ld->getPointerInfo(), Ld->isVolatile(),
25592 Ld->isNonTemporal(), Ld->isInvariant(),
25593 Ld->getAlignment());
25594 SDValue NewChain = NewLd.getValue(1);
25595 if (TokenFactorIndex != -1) {
25596 Ops.push_back(NewChain);
25597 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
25599 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
25600 St->getPointerInfo(),
25601 St->isVolatile(), St->isNonTemporal(),
25602 St->getAlignment());
25605 // Otherwise, lower to two pairs of 32-bit loads / stores.
25606 SDValue LoAddr = Ld->getBasePtr();
25607 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
25608 DAG.getConstant(4, LdDL, MVT::i32));
25610 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
25611 Ld->getPointerInfo(),
25612 Ld->isVolatile(), Ld->isNonTemporal(),
25613 Ld->isInvariant(), Ld->getAlignment());
25614 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
25615 Ld->getPointerInfo().getWithOffset(4),
25616 Ld->isVolatile(), Ld->isNonTemporal(),
25618 MinAlign(Ld->getAlignment(), 4));
25620 SDValue NewChain = LoLd.getValue(1);
25621 if (TokenFactorIndex != -1) {
25622 Ops.push_back(LoLd);
25623 Ops.push_back(HiLd);
25624 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
25627 LoAddr = St->getBasePtr();
25628 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
25629 DAG.getConstant(4, StDL, MVT::i32));
25631 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
25632 St->getPointerInfo(),
25633 St->isVolatile(), St->isNonTemporal(),
25634 St->getAlignment());
25635 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
25636 St->getPointerInfo().getWithOffset(4),
25638 St->isNonTemporal(),
25639 MinAlign(St->getAlignment(), 4));
25640 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
25643 // This is similar to the above case, but here we handle a scalar 64-bit
25644 // integer store that is extracted from a vector on a 32-bit target.
25645 // If we have SSE2, then we can treat it like a floating-point double
25646 // to get past legalization. The execution dependencies fixup pass will
25647 // choose the optimal machine instruction for the store if this really is
25648 // an integer or v2f32 rather than an f64.
25649 if (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit() &&
25650 St->getOperand(1).getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
25651 SDValue OldExtract = St->getOperand(1);
25652 SDValue ExtOp0 = OldExtract.getOperand(0);
25653 unsigned VecSize = ExtOp0.getValueSizeInBits();
25654 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), MVT::f64, VecSize / 64);
25655 SDValue BitCast = DAG.getBitcast(VecVT, ExtOp0);
25656 SDValue NewExtract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
25657 BitCast, OldExtract.getOperand(1));
25658 return DAG.getStore(St->getChain(), dl, NewExtract, St->getBasePtr(),
25659 St->getPointerInfo(), St->isVolatile(),
25660 St->isNonTemporal(), St->getAlignment());
25666 /// Return 'true' if this vector operation is "horizontal"
25667 /// and return the operands for the horizontal operation in LHS and RHS. A
25668 /// horizontal operation performs the binary operation on successive elements
25669 /// of its first operand, then on successive elements of its second operand,
25670 /// returning the resulting values in a vector. For example, if
25671 /// A = < float a0, float a1, float a2, float a3 >
25673 /// B = < float b0, float b1, float b2, float b3 >
25674 /// then the result of doing a horizontal operation on A and B is
25675 /// A horizontal-op B = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >.
25676 /// In short, LHS and RHS are inspected to see if LHS op RHS is of the form
25677 /// A horizontal-op B, for some already available A and B, and if so then LHS is
25678 /// set to A, RHS to B, and the routine returns 'true'.
25679 /// Note that the binary operation should have the property that if one of the
25680 /// operands is UNDEF then the result is UNDEF.
25681 static bool isHorizontalBinOp(SDValue &LHS, SDValue &RHS, bool IsCommutative) {
25682 // Look for the following pattern: if
25683 // A = < float a0, float a1, float a2, float a3 >
25684 // B = < float b0, float b1, float b2, float b3 >
25686 // LHS = VECTOR_SHUFFLE A, B, <0, 2, 4, 6>
25687 // RHS = VECTOR_SHUFFLE A, B, <1, 3, 5, 7>
25688 // then LHS op RHS = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >
25689 // which is A horizontal-op B.
25691 // At least one of the operands should be a vector shuffle.
25692 if (LHS.getOpcode() != ISD::VECTOR_SHUFFLE &&
25693 RHS.getOpcode() != ISD::VECTOR_SHUFFLE)
25696 MVT VT = LHS.getSimpleValueType();
25698 assert((VT.is128BitVector() || VT.is256BitVector()) &&
25699 "Unsupported vector type for horizontal add/sub");
25701 // Handle 128 and 256-bit vector lengths. AVX defines horizontal add/sub to
25702 // operate independently on 128-bit lanes.
25703 unsigned NumElts = VT.getVectorNumElements();
25704 unsigned NumLanes = VT.getSizeInBits()/128;
25705 unsigned NumLaneElts = NumElts / NumLanes;
25706 assert((NumLaneElts % 2 == 0) &&
25707 "Vector type should have an even number of elements in each lane");
25708 unsigned HalfLaneElts = NumLaneElts/2;
25710 // View LHS in the form
25711 // LHS = VECTOR_SHUFFLE A, B, LMask
25712 // If LHS is not a shuffle then pretend it is the shuffle
25713 // LHS = VECTOR_SHUFFLE LHS, undef, <0, 1, ..., N-1>
25714 // NOTE: in what follows a default initialized SDValue represents an UNDEF of
25717 SmallVector<int, 16> LMask(NumElts);
25718 if (LHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
25719 if (LHS.getOperand(0).getOpcode() != ISD::UNDEF)
25720 A = LHS.getOperand(0);
25721 if (LHS.getOperand(1).getOpcode() != ISD::UNDEF)
25722 B = LHS.getOperand(1);
25723 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(LHS.getNode())->getMask();
25724 std::copy(Mask.begin(), Mask.end(), LMask.begin());
25726 if (LHS.getOpcode() != ISD::UNDEF)
25728 for (unsigned i = 0; i != NumElts; ++i)
25732 // Likewise, view RHS in the form
25733 // RHS = VECTOR_SHUFFLE C, D, RMask
25735 SmallVector<int, 16> RMask(NumElts);
25736 if (RHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
25737 if (RHS.getOperand(0).getOpcode() != ISD::UNDEF)
25738 C = RHS.getOperand(0);
25739 if (RHS.getOperand(1).getOpcode() != ISD::UNDEF)
25740 D = RHS.getOperand(1);
25741 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(RHS.getNode())->getMask();
25742 std::copy(Mask.begin(), Mask.end(), RMask.begin());
25744 if (RHS.getOpcode() != ISD::UNDEF)
25746 for (unsigned i = 0; i != NumElts; ++i)
25750 // Check that the shuffles are both shuffling the same vectors.
25751 if (!(A == C && B == D) && !(A == D && B == C))
25754 // If everything is UNDEF then bail out: it would be better to fold to UNDEF.
25755 if (!A.getNode() && !B.getNode())
25758 // If A and B occur in reverse order in RHS, then "swap" them (which means
25759 // rewriting the mask).
25761 ShuffleVectorSDNode::commuteMask(RMask);
25763 // At this point LHS and RHS are equivalent to
25764 // LHS = VECTOR_SHUFFLE A, B, LMask
25765 // RHS = VECTOR_SHUFFLE A, B, RMask
25766 // Check that the masks correspond to performing a horizontal operation.
25767 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
25768 for (unsigned i = 0; i != NumLaneElts; ++i) {
25769 int LIdx = LMask[i+l], RIdx = RMask[i+l];
25771 // Ignore any UNDEF components.
25772 if (LIdx < 0 || RIdx < 0 ||
25773 (!A.getNode() && (LIdx < (int)NumElts || RIdx < (int)NumElts)) ||
25774 (!B.getNode() && (LIdx >= (int)NumElts || RIdx >= (int)NumElts)))
25777 // Check that successive elements are being operated on. If not, this is
25778 // not a horizontal operation.
25779 unsigned Src = (i/HalfLaneElts); // each lane is split between srcs
25780 int Index = 2*(i%HalfLaneElts) + NumElts*Src + l;
25781 if (!(LIdx == Index && RIdx == Index + 1) &&
25782 !(IsCommutative && LIdx == Index + 1 && RIdx == Index))
25787 LHS = A.getNode() ? A : B; // If A is 'UNDEF', use B for it.
25788 RHS = B.getNode() ? B : A; // If B is 'UNDEF', use A for it.
25792 /// Do target-specific dag combines on floating point adds.
25793 static SDValue PerformFADDCombine(SDNode *N, SelectionDAG &DAG,
25794 const X86Subtarget *Subtarget) {
25795 EVT VT = N->getValueType(0);
25796 SDValue LHS = N->getOperand(0);
25797 SDValue RHS = N->getOperand(1);
25799 // Try to synthesize horizontal adds from adds of shuffles.
25800 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
25801 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
25802 isHorizontalBinOp(LHS, RHS, true))
25803 return DAG.getNode(X86ISD::FHADD, SDLoc(N), VT, LHS, RHS);
25807 /// Do target-specific dag combines on floating point subs.
25808 static SDValue PerformFSUBCombine(SDNode *N, SelectionDAG &DAG,
25809 const X86Subtarget *Subtarget) {
25810 EVT VT = N->getValueType(0);
25811 SDValue LHS = N->getOperand(0);
25812 SDValue RHS = N->getOperand(1);
25814 // Try to synthesize horizontal subs from subs of shuffles.
25815 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
25816 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
25817 isHorizontalBinOp(LHS, RHS, false))
25818 return DAG.getNode(X86ISD::FHSUB, SDLoc(N), VT, LHS, RHS);
25822 /// Do target-specific dag combines on X86ISD::FOR and X86ISD::FXOR nodes.
25823 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG,
25824 const X86Subtarget *Subtarget) {
25825 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
25827 // F[X]OR(0.0, x) -> x
25828 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
25829 if (C->getValueAPF().isPosZero())
25830 return N->getOperand(1);
25832 // F[X]OR(x, 0.0) -> x
25833 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
25834 if (C->getValueAPF().isPosZero())
25835 return N->getOperand(0);
25837 EVT VT = N->getValueType(0);
25838 if (VT.is512BitVector() && !Subtarget->hasDQI()) {
25840 MVT IntScalar = MVT::getIntegerVT(VT.getScalarSizeInBits());
25841 MVT IntVT = MVT::getVectorVT(IntScalar, VT.getVectorNumElements());
25843 SDValue Op0 = DAG.getNode(ISD::BITCAST, dl, IntVT, N->getOperand(0));
25844 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, IntVT, N->getOperand(1));
25845 unsigned IntOpcode = (N->getOpcode() == X86ISD::FOR) ? ISD::OR : ISD::XOR;
25846 SDValue IntOp = DAG.getNode(IntOpcode, dl, IntVT, Op0, Op1);
25847 return DAG.getNode(ISD::BITCAST, dl, VT, IntOp);
25852 /// Do target-specific dag combines on X86ISD::FMIN and X86ISD::FMAX nodes.
25853 static SDValue PerformFMinFMaxCombine(SDNode *N, SelectionDAG &DAG) {
25854 assert(N->getOpcode() == X86ISD::FMIN || N->getOpcode() == X86ISD::FMAX);
25856 // Only perform optimizations if UnsafeMath is used.
25857 if (!DAG.getTarget().Options.UnsafeFPMath)
25860 // If we run in unsafe-math mode, then convert the FMAX and FMIN nodes
25861 // into FMINC and FMAXC, which are Commutative operations.
25862 unsigned NewOp = 0;
25863 switch (N->getOpcode()) {
25864 default: llvm_unreachable("unknown opcode");
25865 case X86ISD::FMIN: NewOp = X86ISD::FMINC; break;
25866 case X86ISD::FMAX: NewOp = X86ISD::FMAXC; break;
25869 return DAG.getNode(NewOp, SDLoc(N), N->getValueType(0),
25870 N->getOperand(0), N->getOperand(1));
25873 /// Do target-specific dag combines on X86ISD::FAND nodes.
25874 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
25875 // FAND(0.0, x) -> 0.0
25876 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
25877 if (C->getValueAPF().isPosZero())
25878 return N->getOperand(0);
25880 // FAND(x, 0.0) -> 0.0
25881 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
25882 if (C->getValueAPF().isPosZero())
25883 return N->getOperand(1);
25888 /// Do target-specific dag combines on X86ISD::FANDN nodes
25889 static SDValue PerformFANDNCombine(SDNode *N, SelectionDAG &DAG) {
25890 // FANDN(0.0, x) -> x
25891 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
25892 if (C->getValueAPF().isPosZero())
25893 return N->getOperand(1);
25895 // FANDN(x, 0.0) -> 0.0
25896 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
25897 if (C->getValueAPF().isPosZero())
25898 return N->getOperand(1);
25903 static SDValue PerformBTCombine(SDNode *N,
25905 TargetLowering::DAGCombinerInfo &DCI) {
25906 // BT ignores high bits in the bit index operand.
25907 SDValue Op1 = N->getOperand(1);
25908 if (Op1.hasOneUse()) {
25909 unsigned BitWidth = Op1.getValueSizeInBits();
25910 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
25911 APInt KnownZero, KnownOne;
25912 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
25913 !DCI.isBeforeLegalizeOps());
25914 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
25915 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
25916 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
25917 DCI.CommitTargetLoweringOpt(TLO);
25922 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
25923 SDValue Op = N->getOperand(0);
25924 if (Op.getOpcode() == ISD::BITCAST)
25925 Op = Op.getOperand(0);
25926 EVT VT = N->getValueType(0), OpVT = Op.getValueType();
25927 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
25928 VT.getVectorElementType().getSizeInBits() ==
25929 OpVT.getVectorElementType().getSizeInBits()) {
25930 return DAG.getNode(ISD::BITCAST, SDLoc(N), VT, Op);
25935 static SDValue PerformSIGN_EXTEND_INREGCombine(SDNode *N, SelectionDAG &DAG,
25936 const X86Subtarget *Subtarget) {
25937 EVT VT = N->getValueType(0);
25938 if (!VT.isVector())
25941 SDValue N0 = N->getOperand(0);
25942 SDValue N1 = N->getOperand(1);
25943 EVT ExtraVT = cast<VTSDNode>(N1)->getVT();
25946 // The SIGN_EXTEND_INREG to v4i64 is expensive operation on the
25947 // both SSE and AVX2 since there is no sign-extended shift right
25948 // operation on a vector with 64-bit elements.
25949 //(sext_in_reg (v4i64 anyext (v4i32 x )), ExtraVT) ->
25950 // (v4i64 sext (v4i32 sext_in_reg (v4i32 x , ExtraVT)))
25951 if (VT == MVT::v4i64 && (N0.getOpcode() == ISD::ANY_EXTEND ||
25952 N0.getOpcode() == ISD::SIGN_EXTEND)) {
25953 SDValue N00 = N0.getOperand(0);
25955 // EXTLOAD has a better solution on AVX2,
25956 // it may be replaced with X86ISD::VSEXT node.
25957 if (N00.getOpcode() == ISD::LOAD && Subtarget->hasInt256())
25958 if (!ISD::isNormalLoad(N00.getNode()))
25961 if (N00.getValueType() == MVT::v4i32 && ExtraVT.getSizeInBits() < 128) {
25962 SDValue Tmp = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v4i32,
25964 return DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i64, Tmp);
25970 /// sext(add_nsw(x, C)) --> add(sext(x), C_sext)
25971 /// Promoting a sign extension ahead of an 'add nsw' exposes opportunities
25972 /// to combine math ops, use an LEA, or use a complex addressing mode. This can
25973 /// eliminate extend, add, and shift instructions.
25974 static SDValue promoteSextBeforeAddNSW(SDNode *Sext, SelectionDAG &DAG,
25975 const X86Subtarget *Subtarget) {
25976 // TODO: This should be valid for other integer types.
25977 EVT VT = Sext->getValueType(0);
25978 if (VT != MVT::i64)
25981 // We need an 'add nsw' feeding into the 'sext'.
25982 SDValue Add = Sext->getOperand(0);
25983 if (Add.getOpcode() != ISD::ADD || !Add->getFlags()->hasNoSignedWrap())
25986 // Having a constant operand to the 'add' ensures that we are not increasing
25987 // the instruction count because the constant is extended for free below.
25988 // A constant operand can also become the displacement field of an LEA.
25989 auto *AddOp1 = dyn_cast<ConstantSDNode>(Add.getOperand(1));
25993 // Don't make the 'add' bigger if there's no hope of combining it with some
25994 // other 'add' or 'shl' instruction.
25995 // TODO: It may be profitable to generate simpler LEA instructions in place
25996 // of single 'add' instructions, but the cost model for selecting an LEA
25997 // currently has a high threshold.
25998 bool HasLEAPotential = false;
25999 for (auto *User : Sext->uses()) {
26000 if (User->getOpcode() == ISD::ADD || User->getOpcode() == ISD::SHL) {
26001 HasLEAPotential = true;
26005 if (!HasLEAPotential)
26008 // Everything looks good, so pull the 'sext' ahead of the 'add'.
26009 int64_t AddConstant = AddOp1->getSExtValue();
26010 SDValue AddOp0 = Add.getOperand(0);
26011 SDValue NewSext = DAG.getNode(ISD::SIGN_EXTEND, SDLoc(Sext), VT, AddOp0);
26012 SDValue NewConstant = DAG.getConstant(AddConstant, SDLoc(Add), VT);
26014 // The wider add is guaranteed to not wrap because both operands are
26017 Flags.setNoSignedWrap(true);
26018 return DAG.getNode(ISD::ADD, SDLoc(Add), VT, NewSext, NewConstant, &Flags);
26021 static SDValue PerformSExtCombine(SDNode *N, SelectionDAG &DAG,
26022 TargetLowering::DAGCombinerInfo &DCI,
26023 const X86Subtarget *Subtarget) {
26024 SDValue N0 = N->getOperand(0);
26025 EVT VT = N->getValueType(0);
26026 EVT SVT = VT.getScalarType();
26027 EVT InVT = N0.getValueType();
26028 EVT InSVT = InVT.getScalarType();
26031 // (i8,i32 sext (sdivrem (i8 x, i8 y)) ->
26032 // (i8,i32 (sdivrem_sext_hreg (i8 x, i8 y)
26033 // This exposes the sext to the sdivrem lowering, so that it directly extends
26034 // from AH (which we otherwise need to do contortions to access).
26035 if (N0.getOpcode() == ISD::SDIVREM && N0.getResNo() == 1 &&
26036 InVT == MVT::i8 && VT == MVT::i32) {
26037 SDVTList NodeTys = DAG.getVTList(MVT::i8, VT);
26038 SDValue R = DAG.getNode(X86ISD::SDIVREM8_SEXT_HREG, DL, NodeTys,
26039 N0.getOperand(0), N0.getOperand(1));
26040 DAG.ReplaceAllUsesOfValueWith(N0.getValue(0), R.getValue(0));
26041 return R.getValue(1);
26044 if (!DCI.isBeforeLegalizeOps()) {
26045 if (InVT == MVT::i1) {
26046 SDValue Zero = DAG.getConstant(0, DL, VT);
26048 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), DL, VT);
26049 return DAG.getNode(ISD::SELECT, DL, VT, N0, AllOnes, Zero);
26054 if (VT.isVector() && Subtarget->hasSSE2()) {
26055 auto ExtendVecSize = [&DAG](SDLoc DL, SDValue N, unsigned Size) {
26056 EVT InVT = N.getValueType();
26057 EVT OutVT = EVT::getVectorVT(*DAG.getContext(), InVT.getScalarType(),
26058 Size / InVT.getScalarSizeInBits());
26059 SmallVector<SDValue, 8> Opnds(Size / InVT.getSizeInBits(),
26060 DAG.getUNDEF(InVT));
26062 return DAG.getNode(ISD::CONCAT_VECTORS, DL, OutVT, Opnds);
26065 // If target-size is less than 128-bits, extend to a type that would extend
26066 // to 128 bits, extend that and extract the original target vector.
26067 if (VT.getSizeInBits() < 128 && !(128 % VT.getSizeInBits()) &&
26068 (SVT == MVT::i64 || SVT == MVT::i32 || SVT == MVT::i16) &&
26069 (InSVT == MVT::i32 || InSVT == MVT::i16 || InSVT == MVT::i8)) {
26070 unsigned Scale = 128 / VT.getSizeInBits();
26072 EVT::getVectorVT(*DAG.getContext(), SVT, 128 / SVT.getSizeInBits());
26073 SDValue Ex = ExtendVecSize(DL, N0, Scale * InVT.getSizeInBits());
26074 SDValue SExt = DAG.getNode(ISD::SIGN_EXTEND, DL, ExVT, Ex);
26075 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, SExt,
26076 DAG.getIntPtrConstant(0, DL));
26079 // If target-size is 128-bits, then convert to ISD::SIGN_EXTEND_VECTOR_INREG
26080 // which ensures lowering to X86ISD::VSEXT (pmovsx*).
26081 if (VT.getSizeInBits() == 128 &&
26082 (SVT == MVT::i64 || SVT == MVT::i32 || SVT == MVT::i16) &&
26083 (InSVT == MVT::i32 || InSVT == MVT::i16 || InSVT == MVT::i8)) {
26084 SDValue ExOp = ExtendVecSize(DL, N0, 128);
26085 return DAG.getSignExtendVectorInReg(ExOp, DL, VT);
26088 // On pre-AVX2 targets, split into 128-bit nodes of
26089 // ISD::SIGN_EXTEND_VECTOR_INREG.
26090 if (!Subtarget->hasInt256() && !(VT.getSizeInBits() % 128) &&
26091 (SVT == MVT::i64 || SVT == MVT::i32 || SVT == MVT::i16) &&
26092 (InSVT == MVT::i32 || InSVT == MVT::i16 || InSVT == MVT::i8)) {
26093 unsigned NumVecs = VT.getSizeInBits() / 128;
26094 unsigned NumSubElts = 128 / SVT.getSizeInBits();
26095 EVT SubVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumSubElts);
26096 EVT InSubVT = EVT::getVectorVT(*DAG.getContext(), InSVT, NumSubElts);
26098 SmallVector<SDValue, 8> Opnds;
26099 for (unsigned i = 0, Offset = 0; i != NumVecs;
26100 ++i, Offset += NumSubElts) {
26101 SDValue SrcVec = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InSubVT, N0,
26102 DAG.getIntPtrConstant(Offset, DL));
26103 SrcVec = ExtendVecSize(DL, SrcVec, 128);
26104 SrcVec = DAG.getSignExtendVectorInReg(SrcVec, DL, SubVT);
26105 Opnds.push_back(SrcVec);
26107 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Opnds);
26111 if (Subtarget->hasAVX() && VT.is256BitVector())
26112 if (SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget))
26115 if (SDValue NewAdd = promoteSextBeforeAddNSW(N, DAG, Subtarget))
26121 static SDValue PerformFMACombine(SDNode *N, SelectionDAG &DAG,
26122 const X86Subtarget* Subtarget) {
26124 EVT VT = N->getValueType(0);
26126 // Let legalize expand this if it isn't a legal type yet.
26127 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
26130 EVT ScalarVT = VT.getScalarType();
26131 if ((ScalarVT != MVT::f32 && ScalarVT != MVT::f64) ||
26132 (!Subtarget->hasFMA() && !Subtarget->hasFMA4() &&
26133 !Subtarget->hasAVX512()))
26136 SDValue A = N->getOperand(0);
26137 SDValue B = N->getOperand(1);
26138 SDValue C = N->getOperand(2);
26140 bool NegA = (A.getOpcode() == ISD::FNEG);
26141 bool NegB = (B.getOpcode() == ISD::FNEG);
26142 bool NegC = (C.getOpcode() == ISD::FNEG);
26144 // Negative multiplication when NegA xor NegB
26145 bool NegMul = (NegA != NegB);
26147 A = A.getOperand(0);
26149 B = B.getOperand(0);
26151 C = C.getOperand(0);
26155 Opcode = (!NegC) ? X86ISD::FMADD : X86ISD::FMSUB;
26157 Opcode = (!NegC) ? X86ISD::FNMADD : X86ISD::FNMSUB;
26159 return DAG.getNode(Opcode, dl, VT, A, B, C);
26162 static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG,
26163 TargetLowering::DAGCombinerInfo &DCI,
26164 const X86Subtarget *Subtarget) {
26165 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) ->
26166 // (and (i32 x86isd::setcc_carry), 1)
26167 // This eliminates the zext. This transformation is necessary because
26168 // ISD::SETCC is always legalized to i8.
26170 SDValue N0 = N->getOperand(0);
26171 EVT VT = N->getValueType(0);
26173 if (N0.getOpcode() == ISD::AND &&
26175 N0.getOperand(0).hasOneUse()) {
26176 SDValue N00 = N0.getOperand(0);
26177 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
26178 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
26179 if (!C || C->getZExtValue() != 1)
26181 return DAG.getNode(ISD::AND, dl, VT,
26182 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
26183 N00.getOperand(0), N00.getOperand(1)),
26184 DAG.getConstant(1, dl, VT));
26188 if (N0.getOpcode() == ISD::TRUNCATE &&
26190 N0.getOperand(0).hasOneUse()) {
26191 SDValue N00 = N0.getOperand(0);
26192 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
26193 return DAG.getNode(ISD::AND, dl, VT,
26194 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
26195 N00.getOperand(0), N00.getOperand(1)),
26196 DAG.getConstant(1, dl, VT));
26200 if (VT.is256BitVector())
26201 if (SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget))
26204 // (i8,i32 zext (udivrem (i8 x, i8 y)) ->
26205 // (i8,i32 (udivrem_zext_hreg (i8 x, i8 y)
26206 // This exposes the zext to the udivrem lowering, so that it directly extends
26207 // from AH (which we otherwise need to do contortions to access).
26208 if (N0.getOpcode() == ISD::UDIVREM &&
26209 N0.getResNo() == 1 && N0.getValueType() == MVT::i8 &&
26210 (VT == MVT::i32 || VT == MVT::i64)) {
26211 SDVTList NodeTys = DAG.getVTList(MVT::i8, VT);
26212 SDValue R = DAG.getNode(X86ISD::UDIVREM8_ZEXT_HREG, dl, NodeTys,
26213 N0.getOperand(0), N0.getOperand(1));
26214 DAG.ReplaceAllUsesOfValueWith(N0.getValue(0), R.getValue(0));
26215 return R.getValue(1);
26221 // Optimize x == -y --> x+y == 0
26222 // x != -y --> x+y != 0
26223 static SDValue PerformISDSETCCCombine(SDNode *N, SelectionDAG &DAG,
26224 const X86Subtarget* Subtarget) {
26225 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
26226 SDValue LHS = N->getOperand(0);
26227 SDValue RHS = N->getOperand(1);
26228 EVT VT = N->getValueType(0);
26231 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && LHS.getOpcode() == ISD::SUB)
26232 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(LHS.getOperand(0)))
26233 if (C->getAPIntValue() == 0 && LHS.hasOneUse()) {
26234 SDValue addV = DAG.getNode(ISD::ADD, DL, LHS.getValueType(), RHS,
26235 LHS.getOperand(1));
26236 return DAG.getSetCC(DL, N->getValueType(0), addV,
26237 DAG.getConstant(0, DL, addV.getValueType()), CC);
26239 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && RHS.getOpcode() == ISD::SUB)
26240 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS.getOperand(0)))
26241 if (C->getAPIntValue() == 0 && RHS.hasOneUse()) {
26242 SDValue addV = DAG.getNode(ISD::ADD, DL, RHS.getValueType(), LHS,
26243 RHS.getOperand(1));
26244 return DAG.getSetCC(DL, N->getValueType(0), addV,
26245 DAG.getConstant(0, DL, addV.getValueType()), CC);
26248 if (VT.getScalarType() == MVT::i1 &&
26249 (CC == ISD::SETNE || CC == ISD::SETEQ || ISD::isSignedIntSetCC(CC))) {
26251 (LHS.getOpcode() == ISD::SIGN_EXTEND) &&
26252 (LHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
26253 bool IsVZero1 = ISD::isBuildVectorAllZeros(RHS.getNode());
26255 if (!IsSEXT0 || !IsVZero1) {
26256 // Swap the operands and update the condition code.
26257 std::swap(LHS, RHS);
26258 CC = ISD::getSetCCSwappedOperands(CC);
26260 IsSEXT0 = (LHS.getOpcode() == ISD::SIGN_EXTEND) &&
26261 (LHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
26262 IsVZero1 = ISD::isBuildVectorAllZeros(RHS.getNode());
26265 if (IsSEXT0 && IsVZero1) {
26266 assert(VT == LHS.getOperand(0).getValueType() &&
26267 "Uexpected operand type");
26268 if (CC == ISD::SETGT)
26269 return DAG.getConstant(0, DL, VT);
26270 if (CC == ISD::SETLE)
26271 return DAG.getConstant(1, DL, VT);
26272 if (CC == ISD::SETEQ || CC == ISD::SETGE)
26273 return DAG.getNOT(DL, LHS.getOperand(0), VT);
26275 assert((CC == ISD::SETNE || CC == ISD::SETLT) &&
26276 "Unexpected condition code!");
26277 return LHS.getOperand(0);
26284 static SDValue PerformBLENDICombine(SDNode *N, SelectionDAG &DAG) {
26285 SDValue V0 = N->getOperand(0);
26286 SDValue V1 = N->getOperand(1);
26288 EVT VT = N->getValueType(0);
26290 // Canonicalize a v2f64 blend with a mask of 2 by swapping the vector
26291 // operands and changing the mask to 1. This saves us a bunch of
26292 // pattern-matching possibilities related to scalar math ops in SSE/AVX.
26293 // x86InstrInfo knows how to commute this back after instruction selection
26294 // if it would help register allocation.
26296 // TODO: If optimizing for size or a processor that doesn't suffer from
26297 // partial register update stalls, this should be transformed into a MOVSD
26298 // instruction because a MOVSD is 1-2 bytes smaller than a BLENDPD.
26300 if (VT == MVT::v2f64)
26301 if (auto *Mask = dyn_cast<ConstantSDNode>(N->getOperand(2)))
26302 if (Mask->getZExtValue() == 2 && !isShuffleFoldableLoad(V0)) {
26303 SDValue NewMask = DAG.getConstant(1, DL, MVT::i8);
26304 return DAG.getNode(X86ISD::BLENDI, DL, VT, V1, V0, NewMask);
26310 // Helper function of PerformSETCCCombine. It is to materialize "setb reg"
26311 // as "sbb reg,reg", since it can be extended without zext and produces
26312 // an all-ones bit which is more useful than 0/1 in some cases.
26313 static SDValue MaterializeSETB(SDLoc DL, SDValue EFLAGS, SelectionDAG &DAG,
26316 return DAG.getNode(ISD::AND, DL, VT,
26317 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
26318 DAG.getConstant(X86::COND_B, DL, MVT::i8),
26320 DAG.getConstant(1, DL, VT));
26321 assert (VT == MVT::i1 && "Unexpected type for SECCC node");
26322 return DAG.getNode(ISD::TRUNCATE, DL, MVT::i1,
26323 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
26324 DAG.getConstant(X86::COND_B, DL, MVT::i8),
26328 // Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT
26329 static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG,
26330 TargetLowering::DAGCombinerInfo &DCI,
26331 const X86Subtarget *Subtarget) {
26333 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(0));
26334 SDValue EFLAGS = N->getOperand(1);
26336 if (CC == X86::COND_A) {
26337 // Try to convert COND_A into COND_B in an attempt to facilitate
26338 // materializing "setb reg".
26340 // Do not flip "e > c", where "c" is a constant, because Cmp instruction
26341 // cannot take an immediate as its first operand.
26343 if (EFLAGS.getOpcode() == X86ISD::SUB && EFLAGS.hasOneUse() &&
26344 EFLAGS.getValueType().isInteger() &&
26345 !isa<ConstantSDNode>(EFLAGS.getOperand(1))) {
26346 SDValue NewSub = DAG.getNode(X86ISD::SUB, SDLoc(EFLAGS),
26347 EFLAGS.getNode()->getVTList(),
26348 EFLAGS.getOperand(1), EFLAGS.getOperand(0));
26349 SDValue NewEFLAGS = SDValue(NewSub.getNode(), EFLAGS.getResNo());
26350 return MaterializeSETB(DL, NewEFLAGS, DAG, N->getSimpleValueType(0));
26354 // Materialize "setb reg" as "sbb reg,reg", since it can be extended without
26355 // a zext and produces an all-ones bit which is more useful than 0/1 in some
26357 if (CC == X86::COND_B)
26358 return MaterializeSETB(DL, EFLAGS, DAG, N->getSimpleValueType(0));
26360 if (SDValue Flags = checkBoolTestSetCCCombine(EFLAGS, CC)) {
26361 SDValue Cond = DAG.getConstant(CC, DL, MVT::i8);
26362 return DAG.getNode(X86ISD::SETCC, DL, N->getVTList(), Cond, Flags);
26368 // Optimize branch condition evaluation.
26370 static SDValue PerformBrCondCombine(SDNode *N, SelectionDAG &DAG,
26371 TargetLowering::DAGCombinerInfo &DCI,
26372 const X86Subtarget *Subtarget) {
26374 SDValue Chain = N->getOperand(0);
26375 SDValue Dest = N->getOperand(1);
26376 SDValue EFLAGS = N->getOperand(3);
26377 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(2));
26379 if (SDValue Flags = checkBoolTestSetCCCombine(EFLAGS, CC)) {
26380 SDValue Cond = DAG.getConstant(CC, DL, MVT::i8);
26381 return DAG.getNode(X86ISD::BRCOND, DL, N->getVTList(), Chain, Dest, Cond,
26388 static SDValue performVectorCompareAndMaskUnaryOpCombine(SDNode *N,
26389 SelectionDAG &DAG) {
26390 // Take advantage of vector comparisons producing 0 or -1 in each lane to
26391 // optimize away operation when it's from a constant.
26393 // The general transformation is:
26394 // UNARYOP(AND(VECTOR_CMP(x,y), constant)) -->
26395 // AND(VECTOR_CMP(x,y), constant2)
26396 // constant2 = UNARYOP(constant)
26398 // Early exit if this isn't a vector operation, the operand of the
26399 // unary operation isn't a bitwise AND, or if the sizes of the operations
26400 // aren't the same.
26401 EVT VT = N->getValueType(0);
26402 if (!VT.isVector() || N->getOperand(0)->getOpcode() != ISD::AND ||
26403 N->getOperand(0)->getOperand(0)->getOpcode() != ISD::SETCC ||
26404 VT.getSizeInBits() != N->getOperand(0)->getValueType(0).getSizeInBits())
26407 // Now check that the other operand of the AND is a constant. We could
26408 // make the transformation for non-constant splats as well, but it's unclear
26409 // that would be a benefit as it would not eliminate any operations, just
26410 // perform one more step in scalar code before moving to the vector unit.
26411 if (BuildVectorSDNode *BV =
26412 dyn_cast<BuildVectorSDNode>(N->getOperand(0)->getOperand(1))) {
26413 // Bail out if the vector isn't a constant.
26414 if (!BV->isConstant())
26417 // Everything checks out. Build up the new and improved node.
26419 EVT IntVT = BV->getValueType(0);
26420 // Create a new constant of the appropriate type for the transformed
26422 SDValue SourceConst = DAG.getNode(N->getOpcode(), DL, VT, SDValue(BV, 0));
26423 // The AND node needs bitcasts to/from an integer vector type around it.
26424 SDValue MaskConst = DAG.getBitcast(IntVT, SourceConst);
26425 SDValue NewAnd = DAG.getNode(ISD::AND, DL, IntVT,
26426 N->getOperand(0)->getOperand(0), MaskConst);
26427 SDValue Res = DAG.getBitcast(VT, NewAnd);
26434 static SDValue PerformUINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
26435 const X86Subtarget *Subtarget) {
26436 SDValue Op0 = N->getOperand(0);
26437 EVT VT = N->getValueType(0);
26438 EVT InVT = Op0.getValueType();
26439 EVT InSVT = InVT.getScalarType();
26440 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
26442 // UINT_TO_FP(vXi8) -> SINT_TO_FP(ZEXT(vXi8 to vXi32))
26443 // UINT_TO_FP(vXi16) -> SINT_TO_FP(ZEXT(vXi16 to vXi32))
26444 if (InVT.isVector() && (InSVT == MVT::i8 || InSVT == MVT::i16)) {
26446 EVT DstVT = EVT::getVectorVT(*DAG.getContext(), MVT::i32,
26447 InVT.getVectorNumElements());
26448 SDValue P = DAG.getNode(ISD::ZERO_EXTEND, dl, DstVT, Op0);
26450 if (TLI.isOperationLegal(ISD::UINT_TO_FP, DstVT))
26451 return DAG.getNode(ISD::UINT_TO_FP, dl, VT, P);
26453 return DAG.getNode(ISD::SINT_TO_FP, dl, VT, P);
26459 static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
26460 const X86Subtarget *Subtarget) {
26461 // First try to optimize away the conversion entirely when it's
26462 // conditionally from a constant. Vectors only.
26463 if (SDValue Res = performVectorCompareAndMaskUnaryOpCombine(N, DAG))
26466 // Now move on to more general possibilities.
26467 SDValue Op0 = N->getOperand(0);
26468 EVT VT = N->getValueType(0);
26469 EVT InVT = Op0.getValueType();
26470 EVT InSVT = InVT.getScalarType();
26472 // SINT_TO_FP(vXi8) -> SINT_TO_FP(SEXT(vXi8 to vXi32))
26473 // SINT_TO_FP(vXi16) -> SINT_TO_FP(SEXT(vXi16 to vXi32))
26474 if (InVT.isVector() && (InSVT == MVT::i8 || InSVT == MVT::i16)) {
26476 EVT DstVT = EVT::getVectorVT(*DAG.getContext(), MVT::i32,
26477 InVT.getVectorNumElements());
26478 SDValue P = DAG.getNode(ISD::SIGN_EXTEND, dl, DstVT, Op0);
26479 return DAG.getNode(ISD::SINT_TO_FP, dl, VT, P);
26482 // Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have
26483 // a 32-bit target where SSE doesn't support i64->FP operations.
26484 if (!Subtarget->useSoftFloat() && Op0.getOpcode() == ISD::LOAD) {
26485 LoadSDNode *Ld = cast<LoadSDNode>(Op0.getNode());
26486 EVT LdVT = Ld->getValueType(0);
26488 // This transformation is not supported if the result type is f16
26489 if (VT == MVT::f16)
26492 if (!Ld->isVolatile() && !VT.isVector() &&
26493 ISD::isNON_EXTLoad(Op0.getNode()) && Op0.hasOneUse() &&
26494 !Subtarget->is64Bit() && LdVT == MVT::i64) {
26495 SDValue FILDChain = Subtarget->getTargetLowering()->BuildFILD(
26496 SDValue(N, 0), LdVT, Ld->getChain(), Op0, DAG);
26497 DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), FILDChain.getValue(1));
26504 // Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS
26505 static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG,
26506 X86TargetLowering::DAGCombinerInfo &DCI) {
26507 // If the LHS and RHS of the ADC node are zero, then it can't overflow and
26508 // the result is either zero or one (depending on the input carry bit).
26509 // Strength reduce this down to a "set on carry" aka SETCC_CARRY&1.
26510 if (X86::isZeroNode(N->getOperand(0)) &&
26511 X86::isZeroNode(N->getOperand(1)) &&
26512 // We don't have a good way to replace an EFLAGS use, so only do this when
26514 SDValue(N, 1).use_empty()) {
26516 EVT VT = N->getValueType(0);
26517 SDValue CarryOut = DAG.getConstant(0, DL, N->getValueType(1));
26518 SDValue Res1 = DAG.getNode(ISD::AND, DL, VT,
26519 DAG.getNode(X86ISD::SETCC_CARRY, DL, VT,
26520 DAG.getConstant(X86::COND_B, DL,
26523 DAG.getConstant(1, DL, VT));
26524 return DCI.CombineTo(N, Res1, CarryOut);
26530 // fold (add Y, (sete X, 0)) -> adc 0, Y
26531 // (add Y, (setne X, 0)) -> sbb -1, Y
26532 // (sub (sete X, 0), Y) -> sbb 0, Y
26533 // (sub (setne X, 0), Y) -> adc -1, Y
26534 static SDValue OptimizeConditionalInDecrement(SDNode *N, SelectionDAG &DAG) {
26537 // Look through ZExts.
26538 SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0);
26539 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse())
26542 SDValue SetCC = Ext.getOperand(0);
26543 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse())
26546 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0);
26547 if (CC != X86::COND_E && CC != X86::COND_NE)
26550 SDValue Cmp = SetCC.getOperand(1);
26551 if (Cmp.getOpcode() != X86ISD::CMP || !Cmp.hasOneUse() ||
26552 !X86::isZeroNode(Cmp.getOperand(1)) ||
26553 !Cmp.getOperand(0).getValueType().isInteger())
26556 SDValue CmpOp0 = Cmp.getOperand(0);
26557 SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, CmpOp0,
26558 DAG.getConstant(1, DL, CmpOp0.getValueType()));
26560 SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1);
26561 if (CC == X86::COND_NE)
26562 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB,
26563 DL, OtherVal.getValueType(), OtherVal,
26564 DAG.getConstant(-1ULL, DL, OtherVal.getValueType()),
26566 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC,
26567 DL, OtherVal.getValueType(), OtherVal,
26568 DAG.getConstant(0, DL, OtherVal.getValueType()), NewCmp);
26571 /// PerformADDCombine - Do target-specific dag combines on integer adds.
26572 static SDValue PerformAddCombine(SDNode *N, SelectionDAG &DAG,
26573 const X86Subtarget *Subtarget) {
26574 EVT VT = N->getValueType(0);
26575 SDValue Op0 = N->getOperand(0);
26576 SDValue Op1 = N->getOperand(1);
26578 // Try to synthesize horizontal adds from adds of shuffles.
26579 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
26580 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
26581 isHorizontalBinOp(Op0, Op1, true))
26582 return DAG.getNode(X86ISD::HADD, SDLoc(N), VT, Op0, Op1);
26584 return OptimizeConditionalInDecrement(N, DAG);
26587 static SDValue PerformSubCombine(SDNode *N, SelectionDAG &DAG,
26588 const X86Subtarget *Subtarget) {
26589 SDValue Op0 = N->getOperand(0);
26590 SDValue Op1 = N->getOperand(1);
26592 // X86 can't encode an immediate LHS of a sub. See if we can push the
26593 // negation into a preceding instruction.
26594 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op0)) {
26595 // If the RHS of the sub is a XOR with one use and a constant, invert the
26596 // immediate. Then add one to the LHS of the sub so we can turn
26597 // X-Y -> X+~Y+1, saving one register.
26598 if (Op1->hasOneUse() && Op1.getOpcode() == ISD::XOR &&
26599 isa<ConstantSDNode>(Op1.getOperand(1))) {
26600 APInt XorC = cast<ConstantSDNode>(Op1.getOperand(1))->getAPIntValue();
26601 EVT VT = Op0.getValueType();
26602 SDValue NewXor = DAG.getNode(ISD::XOR, SDLoc(Op1), VT,
26604 DAG.getConstant(~XorC, SDLoc(Op1), VT));
26605 return DAG.getNode(ISD::ADD, SDLoc(N), VT, NewXor,
26606 DAG.getConstant(C->getAPIntValue() + 1, SDLoc(N), VT));
26610 // Try to synthesize horizontal adds from adds of shuffles.
26611 EVT VT = N->getValueType(0);
26612 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
26613 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
26614 isHorizontalBinOp(Op0, Op1, true))
26615 return DAG.getNode(X86ISD::HSUB, SDLoc(N), VT, Op0, Op1);
26617 return OptimizeConditionalInDecrement(N, DAG);
26620 /// performVZEXTCombine - Performs build vector combines
26621 static SDValue performVZEXTCombine(SDNode *N, SelectionDAG &DAG,
26622 TargetLowering::DAGCombinerInfo &DCI,
26623 const X86Subtarget *Subtarget) {
26625 MVT VT = N->getSimpleValueType(0);
26626 SDValue Op = N->getOperand(0);
26627 MVT OpVT = Op.getSimpleValueType();
26628 MVT OpEltVT = OpVT.getVectorElementType();
26629 unsigned InputBits = OpEltVT.getSizeInBits() * VT.getVectorNumElements();
26631 // (vzext (bitcast (vzext (x)) -> (vzext x)
26633 while (V.getOpcode() == ISD::BITCAST)
26634 V = V.getOperand(0);
26636 if (V != Op && V.getOpcode() == X86ISD::VZEXT) {
26637 MVT InnerVT = V.getSimpleValueType();
26638 MVT InnerEltVT = InnerVT.getVectorElementType();
26640 // If the element sizes match exactly, we can just do one larger vzext. This
26641 // is always an exact type match as vzext operates on integer types.
26642 if (OpEltVT == InnerEltVT) {
26643 assert(OpVT == InnerVT && "Types must match for vzext!");
26644 return DAG.getNode(X86ISD::VZEXT, DL, VT, V.getOperand(0));
26647 // The only other way we can combine them is if only a single element of the
26648 // inner vzext is used in the input to the outer vzext.
26649 if (InnerEltVT.getSizeInBits() < InputBits)
26652 // In this case, the inner vzext is completely dead because we're going to
26653 // only look at bits inside of the low element. Just do the outer vzext on
26654 // a bitcast of the input to the inner.
26655 return DAG.getNode(X86ISD::VZEXT, DL, VT, DAG.getBitcast(OpVT, V));
26658 // Check if we can bypass extracting and re-inserting an element of an input
26659 // vector. Essentially:
26660 // (bitcast (sclr2vec (ext_vec_elt x))) -> (bitcast x)
26661 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR &&
26662 V.getOperand(0).getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
26663 V.getOperand(0).getSimpleValueType().getSizeInBits() == InputBits) {
26664 SDValue ExtractedV = V.getOperand(0);
26665 SDValue OrigV = ExtractedV.getOperand(0);
26666 if (auto *ExtractIdx = dyn_cast<ConstantSDNode>(ExtractedV.getOperand(1)))
26667 if (ExtractIdx->getZExtValue() == 0) {
26668 MVT OrigVT = OrigV.getSimpleValueType();
26669 // Extract a subvector if necessary...
26670 if (OrigVT.getSizeInBits() > OpVT.getSizeInBits()) {
26671 int Ratio = OrigVT.getSizeInBits() / OpVT.getSizeInBits();
26672 OrigVT = MVT::getVectorVT(OrigVT.getVectorElementType(),
26673 OrigVT.getVectorNumElements() / Ratio);
26674 OrigV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, OrigVT, OrigV,
26675 DAG.getIntPtrConstant(0, DL));
26677 Op = DAG.getBitcast(OpVT, OrigV);
26678 return DAG.getNode(X86ISD::VZEXT, DL, VT, Op);
26685 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
26686 DAGCombinerInfo &DCI) const {
26687 SelectionDAG &DAG = DCI.DAG;
26688 switch (N->getOpcode()) {
26690 case ISD::EXTRACT_VECTOR_ELT:
26691 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, DCI);
26694 case X86ISD::SHRUNKBLEND:
26695 return PerformSELECTCombine(N, DAG, DCI, Subtarget);
26696 case ISD::BITCAST: return PerformBITCASTCombine(N, DAG, Subtarget);
26697 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI, Subtarget);
26698 case ISD::ADD: return PerformAddCombine(N, DAG, Subtarget);
26699 case ISD::SUB: return PerformSubCombine(N, DAG, Subtarget);
26700 case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI);
26701 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
26704 case ISD::SRL: return PerformShiftCombine(N, DAG, DCI, Subtarget);
26705 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget);
26706 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget);
26707 case ISD::XOR: return PerformXorCombine(N, DAG, DCI, Subtarget);
26708 case ISD::LOAD: return PerformLOADCombine(N, DAG, DCI, Subtarget);
26709 case ISD::MLOAD: return PerformMLOADCombine(N, DAG, DCI, Subtarget);
26710 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
26711 case ISD::MSTORE: return PerformMSTORECombine(N, DAG, Subtarget);
26712 case ISD::SINT_TO_FP: return PerformSINT_TO_FPCombine(N, DAG, Subtarget);
26713 case ISD::UINT_TO_FP: return PerformUINT_TO_FPCombine(N, DAG, Subtarget);
26714 case ISD::FADD: return PerformFADDCombine(N, DAG, Subtarget);
26715 case ISD::FSUB: return PerformFSUBCombine(N, DAG, Subtarget);
26717 case X86ISD::FOR: return PerformFORCombine(N, DAG, Subtarget);
26719 case X86ISD::FMAX: return PerformFMinFMaxCombine(N, DAG);
26720 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
26721 case X86ISD::FANDN: return PerformFANDNCombine(N, DAG);
26722 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
26723 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
26724 case ISD::ANY_EXTEND:
26725 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG, DCI, Subtarget);
26726 case ISD::SIGN_EXTEND: return PerformSExtCombine(N, DAG, DCI, Subtarget);
26727 case ISD::SIGN_EXTEND_INREG:
26728 return PerformSIGN_EXTEND_INREGCombine(N, DAG, Subtarget);
26729 case ISD::SETCC: return PerformISDSETCCCombine(N, DAG, Subtarget);
26730 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG, DCI, Subtarget);
26731 case X86ISD::BRCOND: return PerformBrCondCombine(N, DAG, DCI, Subtarget);
26732 case X86ISD::VZEXT: return performVZEXTCombine(N, DAG, DCI, Subtarget);
26733 case X86ISD::SHUFP: // Handle all target specific shuffles
26734 case X86ISD::PALIGNR:
26735 case X86ISD::UNPCKH:
26736 case X86ISD::UNPCKL:
26737 case X86ISD::MOVHLPS:
26738 case X86ISD::MOVLHPS:
26739 case X86ISD::PSHUFB:
26740 case X86ISD::PSHUFD:
26741 case X86ISD::PSHUFHW:
26742 case X86ISD::PSHUFLW:
26743 case X86ISD::MOVSS:
26744 case X86ISD::MOVSD:
26745 case X86ISD::VPERMILPI:
26746 case X86ISD::VPERM2X128:
26747 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget);
26748 case ISD::FMA: return PerformFMACombine(N, DAG, Subtarget);
26749 case X86ISD::BLENDI: return PerformBLENDICombine(N, DAG);
26755 /// isTypeDesirableForOp - Return true if the target has native support for
26756 /// the specified value type and it is 'desirable' to use the type for the
26757 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
26758 /// instruction encodings are longer and some i16 instructions are slow.
26759 bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const {
26760 if (!isTypeLegal(VT))
26762 if (VT != MVT::i16)
26769 case ISD::SIGN_EXTEND:
26770 case ISD::ZERO_EXTEND:
26771 case ISD::ANY_EXTEND:
26784 /// IsDesirableToPromoteOp - This method query the target whether it is
26785 /// beneficial for dag combiner to promote the specified node. If true, it
26786 /// should return the desired promotion type by reference.
26787 bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
26788 EVT VT = Op.getValueType();
26789 if (VT != MVT::i16)
26792 bool Promote = false;
26793 bool Commute = false;
26794 switch (Op.getOpcode()) {
26797 LoadSDNode *LD = cast<LoadSDNode>(Op);
26798 // If the non-extending load has a single use and it's not live out, then it
26799 // might be folded.
26800 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&&
26801 Op.hasOneUse()*/) {
26802 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
26803 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
26804 // The only case where we'd want to promote LOAD (rather then it being
26805 // promoted as an operand is when it's only use is liveout.
26806 if (UI->getOpcode() != ISD::CopyToReg)
26813 case ISD::SIGN_EXTEND:
26814 case ISD::ZERO_EXTEND:
26815 case ISD::ANY_EXTEND:
26820 SDValue N0 = Op.getOperand(0);
26821 // Look out for (store (shl (load), x)).
26822 if (MayFoldLoad(N0) && MayFoldIntoStore(Op))
26835 SDValue N0 = Op.getOperand(0);
26836 SDValue N1 = Op.getOperand(1);
26837 if (!Commute && MayFoldLoad(N1))
26839 // Avoid disabling potential load folding opportunities.
26840 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op)))
26842 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op)))
26852 //===----------------------------------------------------------------------===//
26853 // X86 Inline Assembly Support
26854 //===----------------------------------------------------------------------===//
26856 // Helper to match a string separated by whitespace.
26857 static bool matchAsm(StringRef S, ArrayRef<const char *> Pieces) {
26858 S = S.substr(S.find_first_not_of(" \t")); // Skip leading whitespace.
26860 for (StringRef Piece : Pieces) {
26861 if (!S.startswith(Piece)) // Check if the piece matches.
26864 S = S.substr(Piece.size());
26865 StringRef::size_type Pos = S.find_first_not_of(" \t");
26866 if (Pos == 0) // We matched a prefix.
26875 static bool clobbersFlagRegisters(const SmallVector<StringRef, 4> &AsmPieces) {
26877 if (AsmPieces.size() == 3 || AsmPieces.size() == 4) {
26878 if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{cc}") &&
26879 std::count(AsmPieces.begin(), AsmPieces.end(), "~{flags}") &&
26880 std::count(AsmPieces.begin(), AsmPieces.end(), "~{fpsr}")) {
26882 if (AsmPieces.size() == 3)
26884 else if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{dirflag}"))
26891 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
26892 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
26894 std::string AsmStr = IA->getAsmString();
26896 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
26897 if (!Ty || Ty->getBitWidth() % 16 != 0)
26900 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
26901 SmallVector<StringRef, 4> AsmPieces;
26902 SplitString(AsmStr, AsmPieces, ";\n");
26904 switch (AsmPieces.size()) {
26905 default: return false;
26907 // FIXME: this should verify that we are targeting a 486 or better. If not,
26908 // we will turn this bswap into something that will be lowered to logical
26909 // ops instead of emitting the bswap asm. For now, we don't support 486 or
26910 // lower so don't worry about this.
26912 if (matchAsm(AsmPieces[0], {"bswap", "$0"}) ||
26913 matchAsm(AsmPieces[0], {"bswapl", "$0"}) ||
26914 matchAsm(AsmPieces[0], {"bswapq", "$0"}) ||
26915 matchAsm(AsmPieces[0], {"bswap", "${0:q}"}) ||
26916 matchAsm(AsmPieces[0], {"bswapl", "${0:q}"}) ||
26917 matchAsm(AsmPieces[0], {"bswapq", "${0:q}"})) {
26918 // No need to check constraints, nothing other than the equivalent of
26919 // "=r,0" would be valid here.
26920 return IntrinsicLowering::LowerToByteSwap(CI);
26923 // rorw $$8, ${0:w} --> llvm.bswap.i16
26924 if (CI->getType()->isIntegerTy(16) &&
26925 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
26926 (matchAsm(AsmPieces[0], {"rorw", "$$8,", "${0:w}"}) ||
26927 matchAsm(AsmPieces[0], {"rolw", "$$8,", "${0:w}"}))) {
26929 StringRef ConstraintsStr = IA->getConstraintString();
26930 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
26931 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
26932 if (clobbersFlagRegisters(AsmPieces))
26933 return IntrinsicLowering::LowerToByteSwap(CI);
26937 if (CI->getType()->isIntegerTy(32) &&
26938 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
26939 matchAsm(AsmPieces[0], {"rorw", "$$8,", "${0:w}"}) &&
26940 matchAsm(AsmPieces[1], {"rorl", "$$16,", "$0"}) &&
26941 matchAsm(AsmPieces[2], {"rorw", "$$8,", "${0:w}"})) {
26943 StringRef ConstraintsStr = IA->getConstraintString();
26944 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
26945 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
26946 if (clobbersFlagRegisters(AsmPieces))
26947 return IntrinsicLowering::LowerToByteSwap(CI);
26950 if (CI->getType()->isIntegerTy(64)) {
26951 InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints();
26952 if (Constraints.size() >= 2 &&
26953 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
26954 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
26955 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
26956 if (matchAsm(AsmPieces[0], {"bswap", "%eax"}) &&
26957 matchAsm(AsmPieces[1], {"bswap", "%edx"}) &&
26958 matchAsm(AsmPieces[2], {"xchgl", "%eax,", "%edx"}))
26959 return IntrinsicLowering::LowerToByteSwap(CI);
26967 /// getConstraintType - Given a constraint letter, return the type of
26968 /// constraint it is for this target.
26969 X86TargetLowering::ConstraintType
26970 X86TargetLowering::getConstraintType(StringRef Constraint) const {
26971 if (Constraint.size() == 1) {
26972 switch (Constraint[0]) {
26983 return C_RegisterClass;
27007 return TargetLowering::getConstraintType(Constraint);
27010 /// Examine constraint type and operand type and determine a weight value.
27011 /// This object must already have been set up with the operand type
27012 /// and the current alternative constraint selected.
27013 TargetLowering::ConstraintWeight
27014 X86TargetLowering::getSingleConstraintMatchWeight(
27015 AsmOperandInfo &info, const char *constraint) const {
27016 ConstraintWeight weight = CW_Invalid;
27017 Value *CallOperandVal = info.CallOperandVal;
27018 // If we don't have a value, we can't do a match,
27019 // but allow it at the lowest weight.
27020 if (!CallOperandVal)
27022 Type *type = CallOperandVal->getType();
27023 // Look at the constraint type.
27024 switch (*constraint) {
27026 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
27037 if (CallOperandVal->getType()->isIntegerTy())
27038 weight = CW_SpecificReg;
27043 if (type->isFloatingPointTy())
27044 weight = CW_SpecificReg;
27047 if (type->isX86_MMXTy() && Subtarget->hasMMX())
27048 weight = CW_SpecificReg;
27052 if (((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasSSE1()) ||
27053 ((type->getPrimitiveSizeInBits() == 256) && Subtarget->hasFp256()))
27054 weight = CW_Register;
27057 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) {
27058 if (C->getZExtValue() <= 31)
27059 weight = CW_Constant;
27063 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
27064 if (C->getZExtValue() <= 63)
27065 weight = CW_Constant;
27069 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
27070 if ((C->getSExtValue() >= -0x80) && (C->getSExtValue() <= 0x7f))
27071 weight = CW_Constant;
27075 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
27076 if ((C->getZExtValue() == 0xff) || (C->getZExtValue() == 0xffff))
27077 weight = CW_Constant;
27081 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
27082 if (C->getZExtValue() <= 3)
27083 weight = CW_Constant;
27087 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
27088 if (C->getZExtValue() <= 0xff)
27089 weight = CW_Constant;
27094 if (isa<ConstantFP>(CallOperandVal)) {
27095 weight = CW_Constant;
27099 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
27100 if ((C->getSExtValue() >= -0x80000000LL) &&
27101 (C->getSExtValue() <= 0x7fffffffLL))
27102 weight = CW_Constant;
27106 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
27107 if (C->getZExtValue() <= 0xffffffff)
27108 weight = CW_Constant;
27115 /// LowerXConstraint - try to replace an X constraint, which matches anything,
27116 /// with another that has more specific requirements based on the type of the
27117 /// corresponding operand.
27118 const char *X86TargetLowering::
27119 LowerXConstraint(EVT ConstraintVT) const {
27120 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
27121 // 'f' like normal targets.
27122 if (ConstraintVT.isFloatingPoint()) {
27123 if (Subtarget->hasSSE2())
27125 if (Subtarget->hasSSE1())
27129 return TargetLowering::LowerXConstraint(ConstraintVT);
27132 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
27133 /// vector. If it is invalid, don't add anything to Ops.
27134 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
27135 std::string &Constraint,
27136 std::vector<SDValue>&Ops,
27137 SelectionDAG &DAG) const {
27140 // Only support length 1 constraints for now.
27141 if (Constraint.length() > 1) return;
27143 char ConstraintLetter = Constraint[0];
27144 switch (ConstraintLetter) {
27147 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
27148 if (C->getZExtValue() <= 31) {
27149 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
27150 Op.getValueType());
27156 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
27157 if (C->getZExtValue() <= 63) {
27158 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
27159 Op.getValueType());
27165 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
27166 if (isInt<8>(C->getSExtValue())) {
27167 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
27168 Op.getValueType());
27174 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
27175 if (C->getZExtValue() == 0xff || C->getZExtValue() == 0xffff ||
27176 (Subtarget->is64Bit() && C->getZExtValue() == 0xffffffff)) {
27177 Result = DAG.getTargetConstant(C->getSExtValue(), SDLoc(Op),
27178 Op.getValueType());
27184 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
27185 if (C->getZExtValue() <= 3) {
27186 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
27187 Op.getValueType());
27193 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
27194 if (C->getZExtValue() <= 255) {
27195 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
27196 Op.getValueType());
27202 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
27203 if (C->getZExtValue() <= 127) {
27204 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
27205 Op.getValueType());
27211 // 32-bit signed value
27212 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
27213 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
27214 C->getSExtValue())) {
27215 // Widen to 64 bits here to get it sign extended.
27216 Result = DAG.getTargetConstant(C->getSExtValue(), SDLoc(Op), MVT::i64);
27219 // FIXME gcc accepts some relocatable values here too, but only in certain
27220 // memory models; it's complicated.
27225 // 32-bit unsigned value
27226 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
27227 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
27228 C->getZExtValue())) {
27229 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
27230 Op.getValueType());
27234 // FIXME gcc accepts some relocatable values here too, but only in certain
27235 // memory models; it's complicated.
27239 // Literal immediates are always ok.
27240 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
27241 // Widen to 64 bits here to get it sign extended.
27242 Result = DAG.getTargetConstant(CST->getSExtValue(), SDLoc(Op), MVT::i64);
27246 // In any sort of PIC mode addresses need to be computed at runtime by
27247 // adding in a register or some sort of table lookup. These can't
27248 // be used as immediates.
27249 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC())
27252 // If we are in non-pic codegen mode, we allow the address of a global (with
27253 // an optional displacement) to be used with 'i'.
27254 GlobalAddressSDNode *GA = nullptr;
27255 int64_t Offset = 0;
27257 // Match either (GA), (GA+C), (GA+C1+C2), etc.
27259 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
27260 Offset += GA->getOffset();
27262 } else if (Op.getOpcode() == ISD::ADD) {
27263 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
27264 Offset += C->getZExtValue();
27265 Op = Op.getOperand(0);
27268 } else if (Op.getOpcode() == ISD::SUB) {
27269 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
27270 Offset += -C->getZExtValue();
27271 Op = Op.getOperand(0);
27276 // Otherwise, this isn't something we can handle, reject it.
27280 const GlobalValue *GV = GA->getGlobal();
27281 // If we require an extra load to get this address, as in PIC mode, we
27282 // can't accept it.
27283 if (isGlobalStubReference(
27284 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget())))
27287 Result = DAG.getTargetGlobalAddress(GV, SDLoc(Op),
27288 GA->getValueType(0), Offset);
27293 if (Result.getNode()) {
27294 Ops.push_back(Result);
27297 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
27300 std::pair<unsigned, const TargetRegisterClass *>
27301 X86TargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
27302 StringRef Constraint,
27304 // First, see if this is a constraint that directly corresponds to an LLVM
27306 if (Constraint.size() == 1) {
27307 // GCC Constraint Letters
27308 switch (Constraint[0]) {
27310 // TODO: Slight differences here in allocation order and leaving
27311 // RIP in the class. Do they matter any more here than they do
27312 // in the normal allocation?
27313 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
27314 if (Subtarget->is64Bit()) {
27315 if (VT == MVT::i32 || VT == MVT::f32)
27316 return std::make_pair(0U, &X86::GR32RegClass);
27317 if (VT == MVT::i16)
27318 return std::make_pair(0U, &X86::GR16RegClass);
27319 if (VT == MVT::i8 || VT == MVT::i1)
27320 return std::make_pair(0U, &X86::GR8RegClass);
27321 if (VT == MVT::i64 || VT == MVT::f64)
27322 return std::make_pair(0U, &X86::GR64RegClass);
27325 // 32-bit fallthrough
27326 case 'Q': // Q_REGS
27327 if (VT == MVT::i32 || VT == MVT::f32)
27328 return std::make_pair(0U, &X86::GR32_ABCDRegClass);
27329 if (VT == MVT::i16)
27330 return std::make_pair(0U, &X86::GR16_ABCDRegClass);
27331 if (VT == MVT::i8 || VT == MVT::i1)
27332 return std::make_pair(0U, &X86::GR8_ABCD_LRegClass);
27333 if (VT == MVT::i64)
27334 return std::make_pair(0U, &X86::GR64_ABCDRegClass);
27336 case 'r': // GENERAL_REGS
27337 case 'l': // INDEX_REGS
27338 if (VT == MVT::i8 || VT == MVT::i1)
27339 return std::make_pair(0U, &X86::GR8RegClass);
27340 if (VT == MVT::i16)
27341 return std::make_pair(0U, &X86::GR16RegClass);
27342 if (VT == MVT::i32 || VT == MVT::f32 || !Subtarget->is64Bit())
27343 return std::make_pair(0U, &X86::GR32RegClass);
27344 return std::make_pair(0U, &X86::GR64RegClass);
27345 case 'R': // LEGACY_REGS
27346 if (VT == MVT::i8 || VT == MVT::i1)
27347 return std::make_pair(0U, &X86::GR8_NOREXRegClass);
27348 if (VT == MVT::i16)
27349 return std::make_pair(0U, &X86::GR16_NOREXRegClass);
27350 if (VT == MVT::i32 || !Subtarget->is64Bit())
27351 return std::make_pair(0U, &X86::GR32_NOREXRegClass);
27352 return std::make_pair(0U, &X86::GR64_NOREXRegClass);
27353 case 'f': // FP Stack registers.
27354 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
27355 // value to the correct fpstack register class.
27356 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
27357 return std::make_pair(0U, &X86::RFP32RegClass);
27358 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
27359 return std::make_pair(0U, &X86::RFP64RegClass);
27360 return std::make_pair(0U, &X86::RFP80RegClass);
27361 case 'y': // MMX_REGS if MMX allowed.
27362 if (!Subtarget->hasMMX()) break;
27363 return std::make_pair(0U, &X86::VR64RegClass);
27364 case 'Y': // SSE_REGS if SSE2 allowed
27365 if (!Subtarget->hasSSE2()) break;
27367 case 'x': // SSE_REGS if SSE1 allowed or AVX_REGS if AVX allowed
27368 if (!Subtarget->hasSSE1()) break;
27370 switch (VT.SimpleTy) {
27372 // Scalar SSE types.
27375 return std::make_pair(0U, &X86::FR32RegClass);
27378 return std::make_pair(0U, &X86::FR64RegClass);
27386 return std::make_pair(0U, &X86::VR128RegClass);
27394 return std::make_pair(0U, &X86::VR256RegClass);
27399 return std::make_pair(0U, &X86::VR512RegClass);
27405 // Use the default implementation in TargetLowering to convert the register
27406 // constraint into a member of a register class.
27407 std::pair<unsigned, const TargetRegisterClass*> Res;
27408 Res = TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
27410 // Not found as a standard register?
27412 // Map st(0) -> st(7) -> ST0
27413 if (Constraint.size() == 7 && Constraint[0] == '{' &&
27414 tolower(Constraint[1]) == 's' &&
27415 tolower(Constraint[2]) == 't' &&
27416 Constraint[3] == '(' &&
27417 (Constraint[4] >= '0' && Constraint[4] <= '7') &&
27418 Constraint[5] == ')' &&
27419 Constraint[6] == '}') {
27421 Res.first = X86::FP0+Constraint[4]-'0';
27422 Res.second = &X86::RFP80RegClass;
27426 // GCC allows "st(0)" to be called just plain "st".
27427 if (StringRef("{st}").equals_lower(Constraint)) {
27428 Res.first = X86::FP0;
27429 Res.second = &X86::RFP80RegClass;
27434 if (StringRef("{flags}").equals_lower(Constraint)) {
27435 Res.first = X86::EFLAGS;
27436 Res.second = &X86::CCRRegClass;
27440 // 'A' means EAX + EDX.
27441 if (Constraint == "A") {
27442 Res.first = X86::EAX;
27443 Res.second = &X86::GR32_ADRegClass;
27449 // Otherwise, check to see if this is a register class of the wrong value
27450 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
27451 // turn into {ax},{dx}.
27452 // MVT::Other is used to specify clobber names.
27453 if (Res.second->hasType(VT) || VT == MVT::Other)
27454 return Res; // Correct type already, nothing to do.
27456 // Get a matching integer of the correct size. i.e. "ax" with MVT::32 should
27457 // return "eax". This should even work for things like getting 64bit integer
27458 // registers when given an f64 type.
27459 const TargetRegisterClass *Class = Res.second;
27460 if (Class == &X86::GR8RegClass || Class == &X86::GR16RegClass ||
27461 Class == &X86::GR32RegClass || Class == &X86::GR64RegClass) {
27462 unsigned Size = VT.getSizeInBits();
27463 MVT::SimpleValueType SimpleTy = Size == 1 || Size == 8 ? MVT::i8
27464 : Size == 16 ? MVT::i16
27465 : Size == 32 ? MVT::i32
27466 : Size == 64 ? MVT::i64
27468 unsigned DestReg = getX86SubSuperRegisterOrZero(Res.first, SimpleTy);
27470 Res.first = DestReg;
27471 Res.second = SimpleTy == MVT::i8 ? &X86::GR8RegClass
27472 : SimpleTy == MVT::i16 ? &X86::GR16RegClass
27473 : SimpleTy == MVT::i32 ? &X86::GR32RegClass
27474 : &X86::GR64RegClass;
27475 assert(Res.second->contains(Res.first) && "Register in register class");
27477 // No register found/type mismatch.
27479 Res.second = nullptr;
27481 } else if (Class == &X86::FR32RegClass || Class == &X86::FR64RegClass ||
27482 Class == &X86::VR128RegClass || Class == &X86::VR256RegClass ||
27483 Class == &X86::FR32XRegClass || Class == &X86::FR64XRegClass ||
27484 Class == &X86::VR128XRegClass || Class == &X86::VR256XRegClass ||
27485 Class == &X86::VR512RegClass) {
27486 // Handle references to XMM physical registers that got mapped into the
27487 // wrong class. This can happen with constraints like {xmm0} where the
27488 // target independent register mapper will just pick the first match it can
27489 // find, ignoring the required type.
27491 if (VT == MVT::f32 || VT == MVT::i32)
27492 Res.second = &X86::FR32RegClass;
27493 else if (VT == MVT::f64 || VT == MVT::i64)
27494 Res.second = &X86::FR64RegClass;
27495 else if (X86::VR128RegClass.hasType(VT))
27496 Res.second = &X86::VR128RegClass;
27497 else if (X86::VR256RegClass.hasType(VT))
27498 Res.second = &X86::VR256RegClass;
27499 else if (X86::VR512RegClass.hasType(VT))
27500 Res.second = &X86::VR512RegClass;
27502 // Type mismatch and not a clobber: Return an error;
27504 Res.second = nullptr;
27511 int X86TargetLowering::getScalingFactorCost(const DataLayout &DL,
27512 const AddrMode &AM, Type *Ty,
27513 unsigned AS) const {
27514 // Scaling factors are not free at all.
27515 // An indexed folded instruction, i.e., inst (reg1, reg2, scale),
27516 // will take 2 allocations in the out of order engine instead of 1
27517 // for plain addressing mode, i.e. inst (reg1).
27519 // vaddps (%rsi,%drx), %ymm0, %ymm1
27520 // Requires two allocations (one for the load, one for the computation)
27522 // vaddps (%rsi), %ymm0, %ymm1
27523 // Requires just 1 allocation, i.e., freeing allocations for other operations
27524 // and having less micro operations to execute.
27526 // For some X86 architectures, this is even worse because for instance for
27527 // stores, the complex addressing mode forces the instruction to use the
27528 // "load" ports instead of the dedicated "store" port.
27529 // E.g., on Haswell:
27530 // vmovaps %ymm1, (%r8, %rdi) can use port 2 or 3.
27531 // vmovaps %ymm1, (%r8) can use port 2, 3, or 7.
27532 if (isLegalAddressingMode(DL, AM, Ty, AS))
27533 // Scale represents reg2 * scale, thus account for 1
27534 // as soon as we use a second register.
27535 return AM.Scale != 0;
27539 bool X86TargetLowering::isIntDivCheap(EVT VT, AttributeSet Attr) const {
27540 // Integer division on x86 is expensive. However, when aggressively optimizing
27541 // for code size, we prefer to use a div instruction, as it is usually smaller
27542 // than the alternative sequence.
27543 // The exception to this is vector division. Since x86 doesn't have vector
27544 // integer division, leaving the division as-is is a loss even in terms of
27545 // size, because it will have to be scalarized, while the alternative code
27546 // sequence can be performed in vector form.
27547 bool OptSize = Attr.hasAttribute(AttributeSet::FunctionIndex,
27548 Attribute::MinSize);
27549 return OptSize && !VT.isVector();
27552 void X86TargetLowering::markInRegArguments(SelectionDAG &DAG,
27553 TargetLowering::ArgListTy& Args) const {
27554 // The MCU psABI requires some arguments to be passed in-register.
27555 // For regular calls, the inreg arguments are marked by the front-end.
27556 // However, for compiler generated library calls, we have to patch this
27558 if (!Subtarget->isTargetMCU() || !Args.size())
27561 unsigned FreeRegs = 3;
27562 for (auto &Arg : Args) {
27563 // For library functions, we do not expect any fancy types.
27564 unsigned Size = DAG.getDataLayout().getTypeSizeInBits(Arg.Ty);
27565 unsigned SizeInRegs = (Size + 31) / 32;
27566 if (SizeInRegs > 2 || SizeInRegs > FreeRegs)
27569 Arg.isInReg = true;
27570 FreeRegs -= SizeInRegs;