1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "x86-isel"
16 #include "X86ISelLowering.h"
17 #include "Utils/X86ShuffleDecode.h"
19 #include "X86InstrBuilder.h"
20 #include "X86TargetMachine.h"
21 #include "X86TargetObjectFile.h"
22 #include "llvm/ADT/SmallSet.h"
23 #include "llvm/ADT/Statistic.h"
24 #include "llvm/ADT/StringExtras.h"
25 #include "llvm/ADT/VariadicFunction.h"
26 #include "llvm/CodeGen/IntrinsicLowering.h"
27 #include "llvm/CodeGen/MachineFrameInfo.h"
28 #include "llvm/CodeGen/MachineFunction.h"
29 #include "llvm/CodeGen/MachineInstrBuilder.h"
30 #include "llvm/CodeGen/MachineJumpTableInfo.h"
31 #include "llvm/CodeGen/MachineModuleInfo.h"
32 #include "llvm/CodeGen/MachineRegisterInfo.h"
33 #include "llvm/IR/CallingConv.h"
34 #include "llvm/IR/Constants.h"
35 #include "llvm/IR/DerivedTypes.h"
36 #include "llvm/IR/Function.h"
37 #include "llvm/IR/GlobalAlias.h"
38 #include "llvm/IR/GlobalVariable.h"
39 #include "llvm/IR/Instructions.h"
40 #include "llvm/IR/Intrinsics.h"
41 #include "llvm/IR/LLVMContext.h"
42 #include "llvm/MC/MCAsmInfo.h"
43 #include "llvm/MC/MCContext.h"
44 #include "llvm/MC/MCExpr.h"
45 #include "llvm/MC/MCSymbol.h"
46 #include "llvm/Support/CallSite.h"
47 #include "llvm/Support/Debug.h"
48 #include "llvm/Support/ErrorHandling.h"
49 #include "llvm/Support/MathExtras.h"
50 #include "llvm/Target/TargetOptions.h"
55 STATISTIC(NumTailCalls, "Number of tail calls");
57 // Forward declarations.
58 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
61 static SDValue ExtractSubVector(SDValue Vec, unsigned IdxVal,
62 SelectionDAG &DAG, SDLoc dl,
63 unsigned vectorWidth) {
64 assert((vectorWidth == 128 || vectorWidth == 256) &&
65 "Unsupported vector width");
66 EVT VT = Vec.getValueType();
67 EVT ElVT = VT.getVectorElementType();
68 unsigned Factor = VT.getSizeInBits()/vectorWidth;
69 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT,
70 VT.getVectorNumElements()/Factor);
72 // Extract from UNDEF is UNDEF.
73 if (Vec.getOpcode() == ISD::UNDEF)
74 return DAG.getUNDEF(ResultVT);
76 // Extract the relevant vectorWidth bits. Generate an EXTRACT_SUBVECTOR
77 unsigned ElemsPerChunk = vectorWidth / ElVT.getSizeInBits();
79 // This is the index of the first element of the vectorWidth-bit chunk
81 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits()) / vectorWidth)
84 // If the input is a buildvector just emit a smaller one.
85 if (Vec.getOpcode() == ISD::BUILD_VECTOR)
86 return DAG.getNode(ISD::BUILD_VECTOR, dl, ResultVT,
87 Vec->op_begin()+NormalizedIdxVal, ElemsPerChunk);
89 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal);
90 SDValue Result = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec,
96 /// Generate a DAG to grab 128-bits from a vector > 128 bits. This
97 /// sets things up to match to an AVX VEXTRACTF128 / VEXTRACTI128
98 /// or AVX-512 VEXTRACTF32x4 / VEXTRACTI32x4
99 /// instructions or a simple subregister reference. Idx is an index in the
100 /// 128 bits we want. It need not be aligned to a 128-bit bounday. That makes
101 /// lowering EXTRACT_VECTOR_ELT operations easier.
102 static SDValue Extract128BitVector(SDValue Vec, unsigned IdxVal,
103 SelectionDAG &DAG, SDLoc dl) {
104 assert((Vec.getValueType().is256BitVector() ||
105 Vec.getValueType().is512BitVector()) && "Unexpected vector size!");
106 return ExtractSubVector(Vec, IdxVal, DAG, dl, 128);
109 /// Generate a DAG to grab 256-bits from a 512-bit vector.
110 static SDValue Extract256BitVector(SDValue Vec, unsigned IdxVal,
111 SelectionDAG &DAG, SDLoc dl) {
112 assert(Vec.getValueType().is512BitVector() && "Unexpected vector size!");
113 return ExtractSubVector(Vec, IdxVal, DAG, dl, 256);
116 static SDValue InsertSubVector(SDValue Result, SDValue Vec,
117 unsigned IdxVal, SelectionDAG &DAG,
118 SDLoc dl, unsigned vectorWidth) {
119 assert((vectorWidth == 128 || vectorWidth == 256) &&
120 "Unsupported vector width");
121 // Inserting UNDEF is Result
122 if (Vec.getOpcode() == ISD::UNDEF)
124 EVT VT = Vec.getValueType();
125 EVT ElVT = VT.getVectorElementType();
126 EVT ResultVT = Result.getValueType();
128 // Insert the relevant vectorWidth bits.
129 unsigned ElemsPerChunk = vectorWidth/ElVT.getSizeInBits();
131 // This is the index of the first element of the vectorWidth-bit chunk
133 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits())/vectorWidth)
136 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal);
137 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec,
140 /// Generate a DAG to put 128-bits into a vector > 128 bits. This
141 /// sets things up to match to an AVX VINSERTF128/VINSERTI128 or
142 /// AVX-512 VINSERTF32x4/VINSERTI32x4 instructions or a
143 /// simple superregister reference. Idx is an index in the 128 bits
144 /// we want. It need not be aligned to a 128-bit bounday. That makes
145 /// lowering INSERT_VECTOR_ELT operations easier.
146 static SDValue Insert128BitVector(SDValue Result, SDValue Vec,
147 unsigned IdxVal, SelectionDAG &DAG,
149 assert(Vec.getValueType().is128BitVector() && "Unexpected vector size!");
150 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 128);
153 static SDValue Insert256BitVector(SDValue Result, SDValue Vec,
154 unsigned IdxVal, SelectionDAG &DAG,
156 assert(Vec.getValueType().is256BitVector() && "Unexpected vector size!");
157 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 256);
160 /// Concat two 128-bit vectors into a 256 bit vector using VINSERTF128
161 /// instructions. This is used because creating CONCAT_VECTOR nodes of
162 /// BUILD_VECTORS returns a larger BUILD_VECTOR while we're trying to lower
163 /// large BUILD_VECTORS.
164 static SDValue Concat128BitVectors(SDValue V1, SDValue V2, EVT VT,
165 unsigned NumElems, SelectionDAG &DAG,
167 SDValue V = Insert128BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
168 return Insert128BitVector(V, V2, NumElems/2, DAG, dl);
171 static SDValue Concat256BitVectors(SDValue V1, SDValue V2, EVT VT,
172 unsigned NumElems, SelectionDAG &DAG,
174 SDValue V = Insert256BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
175 return Insert256BitVector(V, V2, NumElems/2, DAG, dl);
178 static TargetLoweringObjectFile *createTLOF(X86TargetMachine &TM) {
179 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
180 bool is64Bit = Subtarget->is64Bit();
182 if (Subtarget->isTargetEnvMacho()) {
184 return new X86_64MachoTargetObjectFile();
185 return new TargetLoweringObjectFileMachO();
188 if (Subtarget->isTargetLinux())
189 return new X86LinuxTargetObjectFile();
190 if (Subtarget->isTargetELF())
191 return new TargetLoweringObjectFileELF();
192 if (Subtarget->isTargetCOFF() && !Subtarget->isTargetEnvMacho())
193 return new TargetLoweringObjectFileCOFF();
194 llvm_unreachable("unknown subtarget type");
197 X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
198 : TargetLowering(TM, createTLOF(TM)) {
199 Subtarget = &TM.getSubtarget<X86Subtarget>();
200 X86ScalarSSEf64 = Subtarget->hasSSE2();
201 X86ScalarSSEf32 = Subtarget->hasSSE1();
202 TD = getDataLayout();
204 resetOperationActions();
207 void X86TargetLowering::resetOperationActions() {
208 const TargetMachine &TM = getTargetMachine();
209 static bool FirstTimeThrough = true;
211 // If none of the target options have changed, then we don't need to reset the
212 // operation actions.
213 if (!FirstTimeThrough && TO == TM.Options) return;
215 if (!FirstTimeThrough) {
216 // Reinitialize the actions.
218 FirstTimeThrough = false;
223 // Set up the TargetLowering object.
224 static const MVT IntVTs[] = { MVT::i8, MVT::i16, MVT::i32, MVT::i64 };
226 // X86 is weird, it always uses i8 for shift amounts and setcc results.
227 setBooleanContents(ZeroOrOneBooleanContent);
228 // X86-SSE is even stranger. It uses -1 or 0 for vector masks.
229 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
231 // For 64-bit since we have so many registers use the ILP scheduler, for
232 // 32-bit code use the register pressure specific scheduling.
233 // For Atom, always use ILP scheduling.
234 if (Subtarget->isAtom())
235 setSchedulingPreference(Sched::ILP);
236 else if (Subtarget->is64Bit())
237 setSchedulingPreference(Sched::ILP);
239 setSchedulingPreference(Sched::RegPressure);
240 const X86RegisterInfo *RegInfo =
241 static_cast<const X86RegisterInfo*>(TM.getRegisterInfo());
242 setStackPointerRegisterToSaveRestore(RegInfo->getStackRegister());
244 // Bypass expensive divides on Atom when compiling with O2
245 if (Subtarget->hasSlowDivide() && TM.getOptLevel() >= CodeGenOpt::Default) {
246 addBypassSlowDiv(32, 8);
247 if (Subtarget->is64Bit())
248 addBypassSlowDiv(64, 16);
251 if (Subtarget->isTargetWindows() && !Subtarget->isTargetCygMing()) {
252 // Setup Windows compiler runtime calls.
253 setLibcallName(RTLIB::SDIV_I64, "_alldiv");
254 setLibcallName(RTLIB::UDIV_I64, "_aulldiv");
255 setLibcallName(RTLIB::SREM_I64, "_allrem");
256 setLibcallName(RTLIB::UREM_I64, "_aullrem");
257 setLibcallName(RTLIB::MUL_I64, "_allmul");
258 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall);
259 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall);
260 setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::X86_StdCall);
261 setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::X86_StdCall);
262 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::X86_StdCall);
264 // The _ftol2 runtime function has an unusual calling conv, which
265 // is modeled by a special pseudo-instruction.
266 setLibcallName(RTLIB::FPTOUINT_F64_I64, 0);
267 setLibcallName(RTLIB::FPTOUINT_F32_I64, 0);
268 setLibcallName(RTLIB::FPTOUINT_F64_I32, 0);
269 setLibcallName(RTLIB::FPTOUINT_F32_I32, 0);
272 if (Subtarget->isTargetDarwin()) {
273 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
274 setUseUnderscoreSetJmp(false);
275 setUseUnderscoreLongJmp(false);
276 } else if (Subtarget->isTargetMingw()) {
277 // MS runtime is weird: it exports _setjmp, but longjmp!
278 setUseUnderscoreSetJmp(true);
279 setUseUnderscoreLongJmp(false);
281 setUseUnderscoreSetJmp(true);
282 setUseUnderscoreLongJmp(true);
285 // Set up the register classes.
286 addRegisterClass(MVT::i8, &X86::GR8RegClass);
287 addRegisterClass(MVT::i16, &X86::GR16RegClass);
288 addRegisterClass(MVT::i32, &X86::GR32RegClass);
289 if (Subtarget->is64Bit())
290 addRegisterClass(MVT::i64, &X86::GR64RegClass);
292 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
294 // We don't accept any truncstore of integer registers.
295 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
296 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
297 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
298 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
299 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
300 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
302 // SETOEQ and SETUNE require checking two conditions.
303 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
304 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
305 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
306 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
307 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
308 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
310 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
312 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
313 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
314 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
316 if (Subtarget->is64Bit()) {
317 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
318 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
319 } else if (!TM.Options.UseSoftFloat) {
320 // We have an algorithm for SSE2->double, and we turn this into a
321 // 64-bit FILD followed by conditional FADD for other targets.
322 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
323 // We have an algorithm for SSE2, and we turn this into a 64-bit
324 // FILD for other targets.
325 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
328 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
330 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
331 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
333 if (!TM.Options.UseSoftFloat) {
334 // SSE has no i16 to fp conversion, only i32
335 if (X86ScalarSSEf32) {
336 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
337 // f32 and f64 cases are Legal, f80 case is not
338 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
340 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
341 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
344 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
345 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
348 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
349 // are Legal, f80 is custom lowered.
350 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
351 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
353 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
355 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
356 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
358 if (X86ScalarSSEf32) {
359 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
360 // f32 and f64 cases are Legal, f80 case is not
361 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
363 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
364 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
367 // Handle FP_TO_UINT by promoting the destination to a larger signed
369 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
370 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
371 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
373 if (Subtarget->is64Bit()) {
374 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
375 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
376 } else if (!TM.Options.UseSoftFloat) {
377 // Since AVX is a superset of SSE3, only check for SSE here.
378 if (Subtarget->hasSSE1() && !Subtarget->hasSSE3())
379 // Expand FP_TO_UINT into a select.
380 // FIXME: We would like to use a Custom expander here eventually to do
381 // the optimal thing for SSE vs. the default expansion in the legalizer.
382 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
384 // With SSE3 we can use fisttpll to convert to a signed i64; without
385 // SSE, we're stuck with a fistpll.
386 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
389 if (isTargetFTOL()) {
390 // Use the _ftol2 runtime function, which has a pseudo-instruction
391 // to handle its weird calling convention.
392 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Custom);
395 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
396 if (!X86ScalarSSEf64) {
397 setOperationAction(ISD::BITCAST , MVT::f32 , Expand);
398 setOperationAction(ISD::BITCAST , MVT::i32 , Expand);
399 if (Subtarget->is64Bit()) {
400 setOperationAction(ISD::BITCAST , MVT::f64 , Expand);
401 // Without SSE, i64->f64 goes through memory.
402 setOperationAction(ISD::BITCAST , MVT::i64 , Expand);
406 // Scalar integer divide and remainder are lowered to use operations that
407 // produce two results, to match the available instructions. This exposes
408 // the two-result form to trivial CSE, which is able to combine x/y and x%y
409 // into a single instruction.
411 // Scalar integer multiply-high is also lowered to use two-result
412 // operations, to match the available instructions. However, plain multiply
413 // (low) operations are left as Legal, as there are single-result
414 // instructions for this in x86. Using the two-result multiply instructions
415 // when both high and low results are needed must be arranged by dagcombine.
416 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
418 setOperationAction(ISD::MULHS, VT, Expand);
419 setOperationAction(ISD::MULHU, VT, Expand);
420 setOperationAction(ISD::SDIV, VT, Expand);
421 setOperationAction(ISD::UDIV, VT, Expand);
422 setOperationAction(ISD::SREM, VT, Expand);
423 setOperationAction(ISD::UREM, VT, Expand);
425 // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences.
426 setOperationAction(ISD::ADDC, VT, Custom);
427 setOperationAction(ISD::ADDE, VT, Custom);
428 setOperationAction(ISD::SUBC, VT, Custom);
429 setOperationAction(ISD::SUBE, VT, Custom);
432 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
433 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
434 setOperationAction(ISD::BR_CC , MVT::f32, Expand);
435 setOperationAction(ISD::BR_CC , MVT::f64, Expand);
436 setOperationAction(ISD::BR_CC , MVT::f80, Expand);
437 setOperationAction(ISD::BR_CC , MVT::i8, Expand);
438 setOperationAction(ISD::BR_CC , MVT::i16, Expand);
439 setOperationAction(ISD::BR_CC , MVT::i32, Expand);
440 setOperationAction(ISD::BR_CC , MVT::i64, Expand);
441 setOperationAction(ISD::SELECT_CC , MVT::Other, Expand);
442 if (Subtarget->is64Bit())
443 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
444 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
445 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
446 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
447 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
448 setOperationAction(ISD::FREM , MVT::f32 , Expand);
449 setOperationAction(ISD::FREM , MVT::f64 , Expand);
450 setOperationAction(ISD::FREM , MVT::f80 , Expand);
451 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
453 // Promote the i8 variants and force them on up to i32 which has a shorter
455 setOperationAction(ISD::CTTZ , MVT::i8 , Promote);
456 AddPromotedToType (ISD::CTTZ , MVT::i8 , MVT::i32);
457 setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i8 , Promote);
458 AddPromotedToType (ISD::CTTZ_ZERO_UNDEF , MVT::i8 , MVT::i32);
459 if (Subtarget->hasBMI()) {
460 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16 , Expand);
461 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32 , Expand);
462 if (Subtarget->is64Bit())
463 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
465 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
466 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
467 if (Subtarget->is64Bit())
468 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
471 if (Subtarget->hasLZCNT()) {
472 // When promoting the i8 variants, force them to i32 for a shorter
474 setOperationAction(ISD::CTLZ , MVT::i8 , Promote);
475 AddPromotedToType (ISD::CTLZ , MVT::i8 , MVT::i32);
476 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Promote);
477 AddPromotedToType (ISD::CTLZ_ZERO_UNDEF, MVT::i8 , MVT::i32);
478 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Expand);
479 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Expand);
480 if (Subtarget->is64Bit())
481 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
483 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
484 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
485 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
486 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Custom);
487 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Custom);
488 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Custom);
489 if (Subtarget->is64Bit()) {
490 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
491 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom);
495 if (Subtarget->hasPOPCNT()) {
496 setOperationAction(ISD::CTPOP , MVT::i8 , Promote);
498 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
499 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
500 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
501 if (Subtarget->is64Bit())
502 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
505 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
506 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
508 // These should be promoted to a larger select which is supported.
509 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
510 // X86 wants to expand cmov itself.
511 setOperationAction(ISD::SELECT , MVT::i8 , Custom);
512 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
513 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
514 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
515 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
516 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
517 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
518 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
519 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
520 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
521 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
522 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
523 if (Subtarget->is64Bit()) {
524 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
525 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
527 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
528 // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support
529 // SjLj exception handling but a light-weight setjmp/longjmp replacement to
530 // support continuation, user-level threading, and etc.. As a result, no
531 // other SjLj exception interfaces are implemented and please don't build
532 // your own exception handling based on them.
533 // LLVM/Clang supports zero-cost DWARF exception handling.
534 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
535 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
538 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
539 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
540 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
541 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
542 if (Subtarget->is64Bit())
543 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
544 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
545 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom);
546 if (Subtarget->is64Bit()) {
547 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
548 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
549 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
550 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
551 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom);
553 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
554 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
555 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
556 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
557 if (Subtarget->is64Bit()) {
558 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
559 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
560 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
563 if (Subtarget->hasSSE1())
564 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
566 setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom);
568 // Expand certain atomics
569 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
571 setOperationAction(ISD::ATOMIC_CMP_SWAP, VT, Custom);
572 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom);
573 setOperationAction(ISD::ATOMIC_STORE, VT, Custom);
576 if (!Subtarget->is64Bit()) {
577 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Custom);
578 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i64, Custom);
579 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom);
580 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i64, Custom);
581 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i64, Custom);
582 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i64, Custom);
583 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i64, Custom);
584 setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Custom);
585 setOperationAction(ISD::ATOMIC_LOAD_MAX, MVT::i64, Custom);
586 setOperationAction(ISD::ATOMIC_LOAD_MIN, MVT::i64, Custom);
587 setOperationAction(ISD::ATOMIC_LOAD_UMAX, MVT::i64, Custom);
588 setOperationAction(ISD::ATOMIC_LOAD_UMIN, MVT::i64, Custom);
591 if (Subtarget->hasCmpxchg16b()) {
592 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i128, Custom);
595 // FIXME - use subtarget debug flags
596 if (!Subtarget->isTargetDarwin() &&
597 !Subtarget->isTargetELF() &&
598 !Subtarget->isTargetCygMing()) {
599 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
602 if (Subtarget->is64Bit()) {
603 setExceptionPointerRegister(X86::RAX);
604 setExceptionSelectorRegister(X86::RDX);
606 setExceptionPointerRegister(X86::EAX);
607 setExceptionSelectorRegister(X86::EDX);
609 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
610 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
612 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
613 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
615 setOperationAction(ISD::TRAP, MVT::Other, Legal);
616 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Legal);
618 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
619 setOperationAction(ISD::VASTART , MVT::Other, Custom);
620 setOperationAction(ISD::VAEND , MVT::Other, Expand);
621 if (Subtarget->is64Bit() && !Subtarget->isTargetWin64()) {
622 // TargetInfo::X86_64ABIBuiltinVaList
623 setOperationAction(ISD::VAARG , MVT::Other, Custom);
624 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
626 // TargetInfo::CharPtrBuiltinVaList
627 setOperationAction(ISD::VAARG , MVT::Other, Expand);
628 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
631 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
632 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
634 if (Subtarget->isTargetCOFF() && !Subtarget->isTargetEnvMacho())
635 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ?
636 MVT::i64 : MVT::i32, Custom);
637 else if (TM.Options.EnableSegmentedStacks)
638 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ?
639 MVT::i64 : MVT::i32, Custom);
641 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ?
642 MVT::i64 : MVT::i32, Expand);
644 if (!TM.Options.UseSoftFloat && X86ScalarSSEf64) {
645 // f32 and f64 use SSE.
646 // Set up the FP register classes.
647 addRegisterClass(MVT::f32, &X86::FR32RegClass);
648 addRegisterClass(MVT::f64, &X86::FR64RegClass);
650 // Use ANDPD to simulate FABS.
651 setOperationAction(ISD::FABS , MVT::f64, Custom);
652 setOperationAction(ISD::FABS , MVT::f32, Custom);
654 // Use XORP to simulate FNEG.
655 setOperationAction(ISD::FNEG , MVT::f64, Custom);
656 setOperationAction(ISD::FNEG , MVT::f32, Custom);
658 // Use ANDPD and ORPD to simulate FCOPYSIGN.
659 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
660 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
662 // Lower this to FGETSIGNx86 plus an AND.
663 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom);
664 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom);
666 // We don't support sin/cos/fmod
667 setOperationAction(ISD::FSIN , MVT::f64, Expand);
668 setOperationAction(ISD::FCOS , MVT::f64, Expand);
669 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
670 setOperationAction(ISD::FSIN , MVT::f32, Expand);
671 setOperationAction(ISD::FCOS , MVT::f32, Expand);
672 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
674 // Expand FP immediates into loads from the stack, except for the special
676 addLegalFPImmediate(APFloat(+0.0)); // xorpd
677 addLegalFPImmediate(APFloat(+0.0f)); // xorps
678 } else if (!TM.Options.UseSoftFloat && X86ScalarSSEf32) {
679 // Use SSE for f32, x87 for f64.
680 // Set up the FP register classes.
681 addRegisterClass(MVT::f32, &X86::FR32RegClass);
682 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
684 // Use ANDPS to simulate FABS.
685 setOperationAction(ISD::FABS , MVT::f32, Custom);
687 // Use XORP to simulate FNEG.
688 setOperationAction(ISD::FNEG , MVT::f32, Custom);
690 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
692 // Use ANDPS and ORPS to simulate FCOPYSIGN.
693 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
694 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
696 // We don't support sin/cos/fmod
697 setOperationAction(ISD::FSIN , MVT::f32, Expand);
698 setOperationAction(ISD::FCOS , MVT::f32, Expand);
699 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
701 // Special cases we handle for FP constants.
702 addLegalFPImmediate(APFloat(+0.0f)); // xorps
703 addLegalFPImmediate(APFloat(+0.0)); // FLD0
704 addLegalFPImmediate(APFloat(+1.0)); // FLD1
705 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
706 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
708 if (!TM.Options.UnsafeFPMath) {
709 setOperationAction(ISD::FSIN , MVT::f64, Expand);
710 setOperationAction(ISD::FCOS , MVT::f64, Expand);
711 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
713 } else if (!TM.Options.UseSoftFloat) {
714 // f32 and f64 in x87.
715 // Set up the FP register classes.
716 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
717 addRegisterClass(MVT::f32, &X86::RFP32RegClass);
719 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
720 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
721 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
722 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
724 if (!TM.Options.UnsafeFPMath) {
725 setOperationAction(ISD::FSIN , MVT::f64, Expand);
726 setOperationAction(ISD::FSIN , MVT::f32, Expand);
727 setOperationAction(ISD::FCOS , MVT::f64, Expand);
728 setOperationAction(ISD::FCOS , MVT::f32, Expand);
729 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
730 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
732 addLegalFPImmediate(APFloat(+0.0)); // FLD0
733 addLegalFPImmediate(APFloat(+1.0)); // FLD1
734 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
735 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
736 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
737 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
738 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
739 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
742 // We don't support FMA.
743 setOperationAction(ISD::FMA, MVT::f64, Expand);
744 setOperationAction(ISD::FMA, MVT::f32, Expand);
746 // Long double always uses X87.
747 if (!TM.Options.UseSoftFloat) {
748 addRegisterClass(MVT::f80, &X86::RFP80RegClass);
749 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
750 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
752 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended);
753 addLegalFPImmediate(TmpFlt); // FLD0
755 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
758 APFloat TmpFlt2(+1.0);
759 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
761 addLegalFPImmediate(TmpFlt2); // FLD1
762 TmpFlt2.changeSign();
763 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
766 if (!TM.Options.UnsafeFPMath) {
767 setOperationAction(ISD::FSIN , MVT::f80, Expand);
768 setOperationAction(ISD::FCOS , MVT::f80, Expand);
769 setOperationAction(ISD::FSINCOS, MVT::f80, Expand);
772 setOperationAction(ISD::FFLOOR, MVT::f80, Expand);
773 setOperationAction(ISD::FCEIL, MVT::f80, Expand);
774 setOperationAction(ISD::FTRUNC, MVT::f80, Expand);
775 setOperationAction(ISD::FRINT, MVT::f80, Expand);
776 setOperationAction(ISD::FNEARBYINT, MVT::f80, Expand);
777 setOperationAction(ISD::FMA, MVT::f80, Expand);
780 // Always use a library call for pow.
781 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
782 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
783 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
785 setOperationAction(ISD::FLOG, MVT::f80, Expand);
786 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
787 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
788 setOperationAction(ISD::FEXP, MVT::f80, Expand);
789 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
791 // First set operation action for all vector types to either promote
792 // (for widening) or expand (for scalarization). Then we will selectively
793 // turn on ones that can be effectively codegen'd.
794 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
795 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
796 MVT VT = (MVT::SimpleValueType)i;
797 setOperationAction(ISD::ADD , VT, Expand);
798 setOperationAction(ISD::SUB , VT, Expand);
799 setOperationAction(ISD::FADD, VT, Expand);
800 setOperationAction(ISD::FNEG, VT, Expand);
801 setOperationAction(ISD::FSUB, VT, Expand);
802 setOperationAction(ISD::MUL , VT, Expand);
803 setOperationAction(ISD::FMUL, VT, Expand);
804 setOperationAction(ISD::SDIV, VT, Expand);
805 setOperationAction(ISD::UDIV, VT, Expand);
806 setOperationAction(ISD::FDIV, VT, Expand);
807 setOperationAction(ISD::SREM, VT, Expand);
808 setOperationAction(ISD::UREM, VT, Expand);
809 setOperationAction(ISD::LOAD, VT, Expand);
810 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);
811 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT,Expand);
812 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
813 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT,Expand);
814 setOperationAction(ISD::INSERT_SUBVECTOR, VT,Expand);
815 setOperationAction(ISD::FABS, VT, Expand);
816 setOperationAction(ISD::FSIN, VT, Expand);
817 setOperationAction(ISD::FSINCOS, VT, Expand);
818 setOperationAction(ISD::FCOS, VT, Expand);
819 setOperationAction(ISD::FSINCOS, VT, Expand);
820 setOperationAction(ISD::FREM, VT, Expand);
821 setOperationAction(ISD::FMA, VT, Expand);
822 setOperationAction(ISD::FPOWI, VT, Expand);
823 setOperationAction(ISD::FSQRT, VT, Expand);
824 setOperationAction(ISD::FCOPYSIGN, VT, Expand);
825 setOperationAction(ISD::FFLOOR, VT, Expand);
826 setOperationAction(ISD::FCEIL, VT, Expand);
827 setOperationAction(ISD::FTRUNC, VT, Expand);
828 setOperationAction(ISD::FRINT, VT, Expand);
829 setOperationAction(ISD::FNEARBYINT, VT, Expand);
830 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
831 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
832 setOperationAction(ISD::SDIVREM, VT, Expand);
833 setOperationAction(ISD::UDIVREM, VT, Expand);
834 setOperationAction(ISD::FPOW, VT, Expand);
835 setOperationAction(ISD::CTPOP, VT, Expand);
836 setOperationAction(ISD::CTTZ, VT, Expand);
837 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
838 setOperationAction(ISD::CTLZ, VT, Expand);
839 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
840 setOperationAction(ISD::SHL, VT, Expand);
841 setOperationAction(ISD::SRA, VT, Expand);
842 setOperationAction(ISD::SRL, VT, Expand);
843 setOperationAction(ISD::ROTL, VT, Expand);
844 setOperationAction(ISD::ROTR, VT, Expand);
845 setOperationAction(ISD::BSWAP, VT, Expand);
846 setOperationAction(ISD::SETCC, VT, Expand);
847 setOperationAction(ISD::FLOG, VT, Expand);
848 setOperationAction(ISD::FLOG2, VT, Expand);
849 setOperationAction(ISD::FLOG10, VT, Expand);
850 setOperationAction(ISD::FEXP, VT, Expand);
851 setOperationAction(ISD::FEXP2, VT, Expand);
852 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
853 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
854 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
855 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
856 setOperationAction(ISD::SIGN_EXTEND_INREG, VT,Expand);
857 setOperationAction(ISD::TRUNCATE, VT, Expand);
858 setOperationAction(ISD::SIGN_EXTEND, VT, Expand);
859 setOperationAction(ISD::ZERO_EXTEND, VT, Expand);
860 setOperationAction(ISD::ANY_EXTEND, VT, Expand);
861 setOperationAction(ISD::VSELECT, VT, Expand);
862 for (int InnerVT = MVT::FIRST_VECTOR_VALUETYPE;
863 InnerVT <= MVT::LAST_VECTOR_VALUETYPE; ++InnerVT)
864 setTruncStoreAction(VT,
865 (MVT::SimpleValueType)InnerVT, Expand);
866 setLoadExtAction(ISD::SEXTLOAD, VT, Expand);
867 setLoadExtAction(ISD::ZEXTLOAD, VT, Expand);
868 setLoadExtAction(ISD::EXTLOAD, VT, Expand);
871 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
872 // with -msoft-float, disable use of MMX as well.
873 if (!TM.Options.UseSoftFloat && Subtarget->hasMMX()) {
874 addRegisterClass(MVT::x86mmx, &X86::VR64RegClass);
875 // No operations on x86mmx supported, everything uses intrinsics.
878 // MMX-sized vectors (other than x86mmx) are expected to be expanded
879 // into smaller operations.
880 setOperationAction(ISD::MULHS, MVT::v8i8, Expand);
881 setOperationAction(ISD::MULHS, MVT::v4i16, Expand);
882 setOperationAction(ISD::MULHS, MVT::v2i32, Expand);
883 setOperationAction(ISD::MULHS, MVT::v1i64, Expand);
884 setOperationAction(ISD::AND, MVT::v8i8, Expand);
885 setOperationAction(ISD::AND, MVT::v4i16, Expand);
886 setOperationAction(ISD::AND, MVT::v2i32, Expand);
887 setOperationAction(ISD::AND, MVT::v1i64, Expand);
888 setOperationAction(ISD::OR, MVT::v8i8, Expand);
889 setOperationAction(ISD::OR, MVT::v4i16, Expand);
890 setOperationAction(ISD::OR, MVT::v2i32, Expand);
891 setOperationAction(ISD::OR, MVT::v1i64, Expand);
892 setOperationAction(ISD::XOR, MVT::v8i8, Expand);
893 setOperationAction(ISD::XOR, MVT::v4i16, Expand);
894 setOperationAction(ISD::XOR, MVT::v2i32, Expand);
895 setOperationAction(ISD::XOR, MVT::v1i64, Expand);
896 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Expand);
897 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Expand);
898 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i32, Expand);
899 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Expand);
900 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand);
901 setOperationAction(ISD::SELECT, MVT::v8i8, Expand);
902 setOperationAction(ISD::SELECT, MVT::v4i16, Expand);
903 setOperationAction(ISD::SELECT, MVT::v2i32, Expand);
904 setOperationAction(ISD::SELECT, MVT::v1i64, Expand);
905 setOperationAction(ISD::BITCAST, MVT::v8i8, Expand);
906 setOperationAction(ISD::BITCAST, MVT::v4i16, Expand);
907 setOperationAction(ISD::BITCAST, MVT::v2i32, Expand);
908 setOperationAction(ISD::BITCAST, MVT::v1i64, Expand);
910 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE1()) {
911 addRegisterClass(MVT::v4f32, &X86::VR128RegClass);
913 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
914 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
915 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
916 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
917 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
918 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
919 setOperationAction(ISD::FABS, MVT::v4f32, Custom);
920 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
921 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
922 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
923 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
924 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
927 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE2()) {
928 addRegisterClass(MVT::v2f64, &X86::VR128RegClass);
930 // FIXME: Unfortunately -soft-float and -no-implicit-float means XMM
931 // registers cannot be used even for integer operations.
932 addRegisterClass(MVT::v16i8, &X86::VR128RegClass);
933 addRegisterClass(MVT::v8i16, &X86::VR128RegClass);
934 addRegisterClass(MVT::v4i32, &X86::VR128RegClass);
935 addRegisterClass(MVT::v2i64, &X86::VR128RegClass);
937 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
938 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
939 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
940 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
941 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
942 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
943 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
944 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
945 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
946 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
947 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
948 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
949 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
950 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
951 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
952 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
953 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
954 setOperationAction(ISD::FABS, MVT::v2f64, Custom);
956 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
957 setOperationAction(ISD::SETCC, MVT::v16i8, Custom);
958 setOperationAction(ISD::SETCC, MVT::v8i16, Custom);
959 setOperationAction(ISD::SETCC, MVT::v4i32, Custom);
961 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
962 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
963 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
964 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
965 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
967 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
968 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
969 MVT VT = (MVT::SimpleValueType)i;
970 // Do not attempt to custom lower non-power-of-2 vectors
971 if (!isPowerOf2_32(VT.getVectorNumElements()))
973 // Do not attempt to custom lower non-128-bit vectors
974 if (!VT.is128BitVector())
976 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
977 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
978 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
981 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
982 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
983 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
984 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
985 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
986 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
988 if (Subtarget->is64Bit()) {
989 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
990 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
993 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
994 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
995 MVT VT = (MVT::SimpleValueType)i;
997 // Do not attempt to promote non-128-bit vectors
998 if (!VT.is128BitVector())
1001 setOperationAction(ISD::AND, VT, Promote);
1002 AddPromotedToType (ISD::AND, VT, MVT::v2i64);
1003 setOperationAction(ISD::OR, VT, Promote);
1004 AddPromotedToType (ISD::OR, VT, MVT::v2i64);
1005 setOperationAction(ISD::XOR, VT, Promote);
1006 AddPromotedToType (ISD::XOR, VT, MVT::v2i64);
1007 setOperationAction(ISD::LOAD, VT, Promote);
1008 AddPromotedToType (ISD::LOAD, VT, MVT::v2i64);
1009 setOperationAction(ISD::SELECT, VT, Promote);
1010 AddPromotedToType (ISD::SELECT, VT, MVT::v2i64);
1013 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
1015 // Custom lower v2i64 and v2f64 selects.
1016 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
1017 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
1018 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
1019 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
1021 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
1022 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
1024 setOperationAction(ISD::UINT_TO_FP, MVT::v4i8, Custom);
1025 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);
1026 // As there is no 64-bit GPR available, we need build a special custom
1027 // sequence to convert from v2i32 to v2f32.
1028 if (!Subtarget->is64Bit())
1029 setOperationAction(ISD::UINT_TO_FP, MVT::v2f32, Custom);
1031 setOperationAction(ISD::FP_EXTEND, MVT::v2f32, Custom);
1032 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Custom);
1034 setLoadExtAction(ISD::EXTLOAD, MVT::v2f32, Legal);
1037 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE41()) {
1038 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
1039 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
1040 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
1041 setOperationAction(ISD::FRINT, MVT::f32, Legal);
1042 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
1043 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
1044 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
1045 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
1046 setOperationAction(ISD::FRINT, MVT::f64, Legal);
1047 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
1049 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal);
1050 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal);
1051 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal);
1052 setOperationAction(ISD::FRINT, MVT::v4f32, Legal);
1053 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal);
1054 setOperationAction(ISD::FFLOOR, MVT::v2f64, Legal);
1055 setOperationAction(ISD::FCEIL, MVT::v2f64, Legal);
1056 setOperationAction(ISD::FTRUNC, MVT::v2f64, Legal);
1057 setOperationAction(ISD::FRINT, MVT::v2f64, Legal);
1058 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Legal);
1060 // FIXME: Do we need to handle scalar-to-vector here?
1061 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
1063 setOperationAction(ISD::VSELECT, MVT::v2f64, Legal);
1064 setOperationAction(ISD::VSELECT, MVT::v2i64, Legal);
1065 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
1066 setOperationAction(ISD::VSELECT, MVT::v4i32, Legal);
1067 setOperationAction(ISD::VSELECT, MVT::v4f32, Legal);
1069 // i8 and i16 vectors are custom , because the source register and source
1070 // source memory operand types are not the same width. f32 vectors are
1071 // custom since the immediate controlling the insert encodes additional
1073 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
1074 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
1075 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
1076 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
1078 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
1079 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
1080 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
1081 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
1083 // FIXME: these should be Legal but thats only for the case where
1084 // the index is constant. For now custom expand to deal with that.
1085 if (Subtarget->is64Bit()) {
1086 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
1087 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
1091 if (Subtarget->hasSSE2()) {
1092 setOperationAction(ISD::SRL, MVT::v8i16, Custom);
1093 setOperationAction(ISD::SRL, MVT::v16i8, Custom);
1095 setOperationAction(ISD::SHL, MVT::v8i16, Custom);
1096 setOperationAction(ISD::SHL, MVT::v16i8, Custom);
1098 setOperationAction(ISD::SRA, MVT::v8i16, Custom);
1099 setOperationAction(ISD::SRA, MVT::v16i8, Custom);
1101 // In the customized shift lowering, the legal cases in AVX2 will be
1103 setOperationAction(ISD::SRL, MVT::v2i64, Custom);
1104 setOperationAction(ISD::SRL, MVT::v4i32, Custom);
1106 setOperationAction(ISD::SHL, MVT::v2i64, Custom);
1107 setOperationAction(ISD::SHL, MVT::v4i32, Custom);
1109 setOperationAction(ISD::SRA, MVT::v4i32, Custom);
1111 setOperationAction(ISD::SDIV, MVT::v8i16, Custom);
1112 setOperationAction(ISD::SDIV, MVT::v4i32, Custom);
1115 if (!TM.Options.UseSoftFloat && Subtarget->hasFp256()) {
1116 addRegisterClass(MVT::v32i8, &X86::VR256RegClass);
1117 addRegisterClass(MVT::v16i16, &X86::VR256RegClass);
1118 addRegisterClass(MVT::v8i32, &X86::VR256RegClass);
1119 addRegisterClass(MVT::v8f32, &X86::VR256RegClass);
1120 addRegisterClass(MVT::v4i64, &X86::VR256RegClass);
1121 addRegisterClass(MVT::v4f64, &X86::VR256RegClass);
1123 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
1124 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
1125 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
1127 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
1128 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
1129 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
1130 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
1131 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
1132 setOperationAction(ISD::FFLOOR, MVT::v8f32, Legal);
1133 setOperationAction(ISD::FCEIL, MVT::v8f32, Legal);
1134 setOperationAction(ISD::FTRUNC, MVT::v8f32, Legal);
1135 setOperationAction(ISD::FRINT, MVT::v8f32, Legal);
1136 setOperationAction(ISD::FNEARBYINT, MVT::v8f32, Legal);
1137 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
1138 setOperationAction(ISD::FABS, MVT::v8f32, Custom);
1140 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
1141 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
1142 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
1143 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
1144 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
1145 setOperationAction(ISD::FFLOOR, MVT::v4f64, Legal);
1146 setOperationAction(ISD::FCEIL, MVT::v4f64, Legal);
1147 setOperationAction(ISD::FTRUNC, MVT::v4f64, Legal);
1148 setOperationAction(ISD::FRINT, MVT::v4f64, Legal);
1149 setOperationAction(ISD::FNEARBYINT, MVT::v4f64, Legal);
1150 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
1151 setOperationAction(ISD::FABS, MVT::v4f64, Custom);
1153 setOperationAction(ISD::TRUNCATE, MVT::v8i16, Custom);
1154 setOperationAction(ISD::TRUNCATE, MVT::v4i32, Custom);
1156 setOperationAction(ISD::FP_TO_SINT, MVT::v8i16, Custom);
1158 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
1159 setOperationAction(ISD::SINT_TO_FP, MVT::v8i16, Promote);
1160 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
1161 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal);
1163 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i32, Custom);
1164 setOperationAction(ISD::UINT_TO_FP, MVT::v8i8, Custom);
1165 setOperationAction(ISD::UINT_TO_FP, MVT::v8i16, Custom);
1167 setLoadExtAction(ISD::EXTLOAD, MVT::v4f32, Legal);
1169 setOperationAction(ISD::SRL, MVT::v16i16, Custom);
1170 setOperationAction(ISD::SRL, MVT::v32i8, Custom);
1172 setOperationAction(ISD::SHL, MVT::v16i16, Custom);
1173 setOperationAction(ISD::SHL, MVT::v32i8, Custom);
1175 setOperationAction(ISD::SRA, MVT::v16i16, Custom);
1176 setOperationAction(ISD::SRA, MVT::v32i8, Custom);
1178 setOperationAction(ISD::SDIV, MVT::v16i16, Custom);
1180 setOperationAction(ISD::SETCC, MVT::v32i8, Custom);
1181 setOperationAction(ISD::SETCC, MVT::v16i16, Custom);
1182 setOperationAction(ISD::SETCC, MVT::v8i32, Custom);
1183 setOperationAction(ISD::SETCC, MVT::v4i64, Custom);
1185 setOperationAction(ISD::SELECT, MVT::v4f64, Custom);
1186 setOperationAction(ISD::SELECT, MVT::v4i64, Custom);
1187 setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
1189 setOperationAction(ISD::VSELECT, MVT::v4f64, Legal);
1190 setOperationAction(ISD::VSELECT, MVT::v4i64, Legal);
1191 setOperationAction(ISD::VSELECT, MVT::v8i32, Legal);
1192 setOperationAction(ISD::VSELECT, MVT::v8f32, Legal);
1194 setOperationAction(ISD::SIGN_EXTEND, MVT::v4i64, Custom);
1195 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i32, Custom);
1196 setOperationAction(ISD::ZERO_EXTEND, MVT::v4i64, Custom);
1197 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i32, Custom);
1198 setOperationAction(ISD::ANY_EXTEND, MVT::v4i64, Custom);
1199 setOperationAction(ISD::ANY_EXTEND, MVT::v8i32, Custom);
1201 if (Subtarget->hasFMA() || Subtarget->hasFMA4()) {
1202 setOperationAction(ISD::FMA, MVT::v8f32, Legal);
1203 setOperationAction(ISD::FMA, MVT::v4f64, Legal);
1204 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
1205 setOperationAction(ISD::FMA, MVT::v2f64, Legal);
1206 setOperationAction(ISD::FMA, MVT::f32, Legal);
1207 setOperationAction(ISD::FMA, MVT::f64, Legal);
1210 if (Subtarget->hasInt256()) {
1211 setOperationAction(ISD::ADD, MVT::v4i64, Legal);
1212 setOperationAction(ISD::ADD, MVT::v8i32, Legal);
1213 setOperationAction(ISD::ADD, MVT::v16i16, Legal);
1214 setOperationAction(ISD::ADD, MVT::v32i8, Legal);
1216 setOperationAction(ISD::SUB, MVT::v4i64, Legal);
1217 setOperationAction(ISD::SUB, MVT::v8i32, Legal);
1218 setOperationAction(ISD::SUB, MVT::v16i16, Legal);
1219 setOperationAction(ISD::SUB, MVT::v32i8, Legal);
1221 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1222 setOperationAction(ISD::MUL, MVT::v8i32, Legal);
1223 setOperationAction(ISD::MUL, MVT::v16i16, Legal);
1224 // Don't lower v32i8 because there is no 128-bit byte mul
1226 setOperationAction(ISD::VSELECT, MVT::v32i8, Legal);
1228 setOperationAction(ISD::SDIV, MVT::v8i32, Custom);
1230 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
1231 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
1232 setOperationAction(ISD::ADD, MVT::v16i16, Custom);
1233 setOperationAction(ISD::ADD, MVT::v32i8, Custom);
1235 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
1236 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
1237 setOperationAction(ISD::SUB, MVT::v16i16, Custom);
1238 setOperationAction(ISD::SUB, MVT::v32i8, Custom);
1240 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1241 setOperationAction(ISD::MUL, MVT::v8i32, Custom);
1242 setOperationAction(ISD::MUL, MVT::v16i16, Custom);
1243 // Don't lower v32i8 because there is no 128-bit byte mul
1246 // In the customized shift lowering, the legal cases in AVX2 will be
1248 setOperationAction(ISD::SRL, MVT::v4i64, Custom);
1249 setOperationAction(ISD::SRL, MVT::v8i32, Custom);
1251 setOperationAction(ISD::SHL, MVT::v4i64, Custom);
1252 setOperationAction(ISD::SHL, MVT::v8i32, Custom);
1254 setOperationAction(ISD::SRA, MVT::v8i32, Custom);
1256 // Custom lower several nodes for 256-bit types.
1257 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
1258 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
1259 MVT VT = (MVT::SimpleValueType)i;
1261 // Extract subvector is special because the value type
1262 // (result) is 128-bit but the source is 256-bit wide.
1263 if (VT.is128BitVector())
1264 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1266 // Do not attempt to custom lower other non-256-bit vectors
1267 if (!VT.is256BitVector())
1270 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1271 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1272 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1273 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1274 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1275 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1276 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom);
1279 // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64.
1280 for (int i = MVT::v32i8; i != MVT::v4i64; ++i) {
1281 MVT VT = (MVT::SimpleValueType)i;
1283 // Do not attempt to promote non-256-bit vectors
1284 if (!VT.is256BitVector())
1287 setOperationAction(ISD::AND, VT, Promote);
1288 AddPromotedToType (ISD::AND, VT, MVT::v4i64);
1289 setOperationAction(ISD::OR, VT, Promote);
1290 AddPromotedToType (ISD::OR, VT, MVT::v4i64);
1291 setOperationAction(ISD::XOR, VT, Promote);
1292 AddPromotedToType (ISD::XOR, VT, MVT::v4i64);
1293 setOperationAction(ISD::LOAD, VT, Promote);
1294 AddPromotedToType (ISD::LOAD, VT, MVT::v4i64);
1295 setOperationAction(ISD::SELECT, VT, Promote);
1296 AddPromotedToType (ISD::SELECT, VT, MVT::v4i64);
1300 if (!TM.Options.UseSoftFloat && Subtarget->hasAVX512()) {
1301 addRegisterClass(MVT::v16i32, &X86::VR512RegClass);
1302 addRegisterClass(MVT::v16f32, &X86::VR512RegClass);
1303 addRegisterClass(MVT::v8i64, &X86::VR512RegClass);
1304 addRegisterClass(MVT::v8f64, &X86::VR512RegClass);
1306 addRegisterClass(MVT::v8i1, &X86::VK8RegClass);
1307 addRegisterClass(MVT::v16i1, &X86::VK16RegClass);
1309 setLoadExtAction(ISD::EXTLOAD, MVT::v8f32, Legal);
1310 setOperationAction(ISD::LOAD, MVT::v16f32, Legal);
1311 setOperationAction(ISD::LOAD, MVT::v8f64, Legal);
1312 setOperationAction(ISD::LOAD, MVT::v8i64, Legal);
1313 setOperationAction(ISD::LOAD, MVT::v16i32, Legal);
1314 setOperationAction(ISD::LOAD, MVT::v16i1, Legal);
1316 setOperationAction(ISD::FADD, MVT::v16f32, Legal);
1317 setOperationAction(ISD::FSUB, MVT::v16f32, Legal);
1318 setOperationAction(ISD::FMUL, MVT::v16f32, Legal);
1319 setOperationAction(ISD::FDIV, MVT::v16f32, Legal);
1320 setOperationAction(ISD::FSQRT, MVT::v16f32, Legal);
1321 setOperationAction(ISD::FNEG, MVT::v16f32, Custom);
1323 setOperationAction(ISD::FADD, MVT::v8f64, Legal);
1324 setOperationAction(ISD::FSUB, MVT::v8f64, Legal);
1325 setOperationAction(ISD::FMUL, MVT::v8f64, Legal);
1326 setOperationAction(ISD::FDIV, MVT::v8f64, Legal);
1327 setOperationAction(ISD::FSQRT, MVT::v8f64, Legal);
1328 setOperationAction(ISD::FNEG, MVT::v8f64, Custom);
1329 setOperationAction(ISD::FMA, MVT::v8f64, Legal);
1330 setOperationAction(ISD::FMA, MVT::v16f32, Legal);
1331 setOperationAction(ISD::SDIV, MVT::v16i32, Custom);
1334 setOperationAction(ISD::FP_TO_SINT, MVT::v16i32, Legal);
1335 setOperationAction(ISD::FP_TO_UINT, MVT::v16i32, Legal);
1336 setOperationAction(ISD::FP_TO_UINT, MVT::v8i32, Legal);
1337 setOperationAction(ISD::SINT_TO_FP, MVT::v16i32, Legal);
1338 setOperationAction(ISD::UINT_TO_FP, MVT::v16i32, Legal);
1339 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Legal);
1340 setOperationAction(ISD::FP_ROUND, MVT::v8f32, Legal);
1341 setOperationAction(ISD::FP_EXTEND, MVT::v8f32, Legal);
1343 setOperationAction(ISD::TRUNCATE, MVT::i1, Legal);
1344 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1345 setOperationAction(ISD::TRUNCATE, MVT::v8i32, Custom);
1346 setOperationAction(ISD::TRUNCATE, MVT::v8i1, Custom);
1347 setOperationAction(ISD::TRUNCATE, MVT::v16i1, Custom);
1348 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i32, Custom);
1349 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i64, Custom);
1350 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i32, Custom);
1351 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i64, Custom);
1352 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i8, Custom);
1353 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i16, Custom);
1354 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1356 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f64, Custom);
1357 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i64, Custom);
1358 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16f32, Custom);
1359 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i32, Custom);
1360 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i1, Custom);
1362 setOperationAction(ISD::SETCC, MVT::v16i1, Custom);
1363 setOperationAction(ISD::SETCC, MVT::v8i1, Custom);
1365 setOperationAction(ISD::MUL, MVT::v8i64, Custom);
1367 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i1, Custom);
1368 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i1, Custom);
1369 setOperationAction(ISD::SELECT, MVT::v8f64, Custom);
1370 setOperationAction(ISD::SELECT, MVT::v8i64, Custom);
1371 setOperationAction(ISD::SELECT, MVT::v16f32, Custom);
1373 setOperationAction(ISD::ADD, MVT::v8i64, Legal);
1374 setOperationAction(ISD::ADD, MVT::v16i32, Legal);
1376 setOperationAction(ISD::SUB, MVT::v8i64, Legal);
1377 setOperationAction(ISD::SUB, MVT::v16i32, Legal);
1379 setOperationAction(ISD::MUL, MVT::v16i32, Legal);
1381 setOperationAction(ISD::SRL, MVT::v8i64, Custom);
1382 setOperationAction(ISD::SRL, MVT::v16i32, Custom);
1384 setOperationAction(ISD::SHL, MVT::v8i64, Custom);
1385 setOperationAction(ISD::SHL, MVT::v16i32, Custom);
1387 setOperationAction(ISD::SRA, MVT::v8i64, Custom);
1388 setOperationAction(ISD::SRA, MVT::v16i32, Custom);
1390 setOperationAction(ISD::AND, MVT::v8i64, Legal);
1391 setOperationAction(ISD::OR, MVT::v8i64, Legal);
1392 setOperationAction(ISD::XOR, MVT::v8i64, Legal);
1393 setOperationAction(ISD::AND, MVT::v16i32, Legal);
1394 setOperationAction(ISD::OR, MVT::v16i32, Legal);
1395 setOperationAction(ISD::XOR, MVT::v16i32, Legal);
1397 // Custom lower several nodes.
1398 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
1399 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
1400 MVT VT = (MVT::SimpleValueType)i;
1402 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1403 // Extract subvector is special because the value type
1404 // (result) is 256/128-bit but the source is 512-bit wide.
1405 if (VT.is128BitVector() || VT.is256BitVector())
1406 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1408 if (VT.getVectorElementType() == MVT::i1)
1409 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal);
1411 // Do not attempt to custom lower other non-512-bit vectors
1412 if (!VT.is512BitVector())
1415 if ( EltSize >= 32) {
1416 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1417 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1418 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1419 setOperationAction(ISD::VSELECT, VT, Legal);
1420 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1421 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1422 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1425 for (int i = MVT::v32i8; i != MVT::v8i64; ++i) {
1426 MVT VT = (MVT::SimpleValueType)i;
1428 // Do not attempt to promote non-256-bit vectors
1429 if (!VT.is512BitVector())
1432 setOperationAction(ISD::SELECT, VT, Promote);
1433 AddPromotedToType (ISD::SELECT, VT, MVT::v8i64);
1437 // SIGN_EXTEND_INREGs are evaluated by the extend type. Handle the expansion
1438 // of this type with custom code.
1439 for (int VT = MVT::FIRST_VECTOR_VALUETYPE;
1440 VT != MVT::LAST_VECTOR_VALUETYPE; VT++) {
1441 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,
1445 // We want to custom lower some of our intrinsics.
1446 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
1447 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
1448 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
1450 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't
1451 // handle type legalization for these operations here.
1453 // FIXME: We really should do custom legalization for addition and
1454 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better
1455 // than generic legalization for 64-bit multiplication-with-overflow, though.
1456 for (unsigned i = 0, e = 3+Subtarget->is64Bit(); i != e; ++i) {
1457 // Add/Sub/Mul with overflow operations are custom lowered.
1459 setOperationAction(ISD::SADDO, VT, Custom);
1460 setOperationAction(ISD::UADDO, VT, Custom);
1461 setOperationAction(ISD::SSUBO, VT, Custom);
1462 setOperationAction(ISD::USUBO, VT, Custom);
1463 setOperationAction(ISD::SMULO, VT, Custom);
1464 setOperationAction(ISD::UMULO, VT, Custom);
1467 // There are no 8-bit 3-address imul/mul instructions
1468 setOperationAction(ISD::SMULO, MVT::i8, Expand);
1469 setOperationAction(ISD::UMULO, MVT::i8, Expand);
1471 if (!Subtarget->is64Bit()) {
1472 // These libcalls are not available in 32-bit.
1473 setLibcallName(RTLIB::SHL_I128, 0);
1474 setLibcallName(RTLIB::SRL_I128, 0);
1475 setLibcallName(RTLIB::SRA_I128, 0);
1478 // Combine sin / cos into one node or libcall if possible.
1479 if (Subtarget->hasSinCos()) {
1480 setLibcallName(RTLIB::SINCOS_F32, "sincosf");
1481 setLibcallName(RTLIB::SINCOS_F64, "sincos");
1482 if (Subtarget->isTargetDarwin()) {
1483 // For MacOSX, we don't want to the normal expansion of a libcall to
1484 // sincos. We want to issue a libcall to __sincos_stret to avoid memory
1486 setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
1487 setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
1491 // We have target-specific dag combine patterns for the following nodes:
1492 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
1493 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
1494 setTargetDAGCombine(ISD::VSELECT);
1495 setTargetDAGCombine(ISD::SELECT);
1496 setTargetDAGCombine(ISD::SHL);
1497 setTargetDAGCombine(ISD::SRA);
1498 setTargetDAGCombine(ISD::SRL);
1499 setTargetDAGCombine(ISD::OR);
1500 setTargetDAGCombine(ISD::AND);
1501 setTargetDAGCombine(ISD::ADD);
1502 setTargetDAGCombine(ISD::FADD);
1503 setTargetDAGCombine(ISD::FSUB);
1504 setTargetDAGCombine(ISD::FMA);
1505 setTargetDAGCombine(ISD::SUB);
1506 setTargetDAGCombine(ISD::LOAD);
1507 setTargetDAGCombine(ISD::STORE);
1508 setTargetDAGCombine(ISD::ZERO_EXTEND);
1509 setTargetDAGCombine(ISD::ANY_EXTEND);
1510 setTargetDAGCombine(ISD::SIGN_EXTEND);
1511 setTargetDAGCombine(ISD::SIGN_EXTEND_INREG);
1512 setTargetDAGCombine(ISD::TRUNCATE);
1513 setTargetDAGCombine(ISD::SINT_TO_FP);
1514 setTargetDAGCombine(ISD::SETCC);
1515 if (Subtarget->is64Bit())
1516 setTargetDAGCombine(ISD::MUL);
1517 setTargetDAGCombine(ISD::XOR);
1519 computeRegisterProperties();
1521 // On Darwin, -Os means optimize for size without hurting performance,
1522 // do not reduce the limit.
1523 MaxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
1524 MaxStoresPerMemsetOptSize = Subtarget->isTargetDarwin() ? 16 : 8;
1525 MaxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores
1526 MaxStoresPerMemcpyOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1527 MaxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores
1528 MaxStoresPerMemmoveOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1529 setPrefLoopAlignment(4); // 2^4 bytes.
1531 // Predictable cmov don't hurt on atom because it's in-order.
1532 PredictableSelectIsExpensive = !Subtarget->isAtom();
1534 setPrefFunctionAlignment(4); // 2^4 bytes.
1537 EVT X86TargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
1538 if (!VT.isVector()) return MVT::i8;
1539 return VT.changeVectorElementTypeToInteger();
1542 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
1543 /// the desired ByVal argument alignment.
1544 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) {
1547 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1548 if (VTy->getBitWidth() == 128)
1550 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1551 unsigned EltAlign = 0;
1552 getMaxByValAlign(ATy->getElementType(), EltAlign);
1553 if (EltAlign > MaxAlign)
1554 MaxAlign = EltAlign;
1555 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
1556 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
1557 unsigned EltAlign = 0;
1558 getMaxByValAlign(STy->getElementType(i), EltAlign);
1559 if (EltAlign > MaxAlign)
1560 MaxAlign = EltAlign;
1567 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1568 /// function arguments in the caller parameter area. For X86, aggregates
1569 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
1570 /// are at 4-byte boundaries.
1571 unsigned X86TargetLowering::getByValTypeAlignment(Type *Ty) const {
1572 if (Subtarget->is64Bit()) {
1573 // Max of 8 and alignment of type.
1574 unsigned TyAlign = TD->getABITypeAlignment(Ty);
1581 if (Subtarget->hasSSE1())
1582 getMaxByValAlign(Ty, Align);
1586 /// getOptimalMemOpType - Returns the target specific optimal type for load
1587 /// and store operations as a result of memset, memcpy, and memmove
1588 /// lowering. If DstAlign is zero that means it's safe to destination
1589 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
1590 /// means there isn't a need to check it against alignment requirement,
1591 /// probably because the source does not need to be loaded. If 'IsMemset' is
1592 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
1593 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
1594 /// source is constant so it does not need to be loaded.
1595 /// It returns EVT::Other if the type should be determined using generic
1596 /// target-independent logic.
1598 X86TargetLowering::getOptimalMemOpType(uint64_t Size,
1599 unsigned DstAlign, unsigned SrcAlign,
1600 bool IsMemset, bool ZeroMemset,
1602 MachineFunction &MF) const {
1603 const Function *F = MF.getFunction();
1604 if ((!IsMemset || ZeroMemset) &&
1605 !F->getAttributes().hasAttribute(AttributeSet::FunctionIndex,
1606 Attribute::NoImplicitFloat)) {
1608 (Subtarget->isUnalignedMemAccessFast() ||
1609 ((DstAlign == 0 || DstAlign >= 16) &&
1610 (SrcAlign == 0 || SrcAlign >= 16)))) {
1612 if (Subtarget->hasInt256())
1614 if (Subtarget->hasFp256())
1617 if (Subtarget->hasSSE2())
1619 if (Subtarget->hasSSE1())
1621 } else if (!MemcpyStrSrc && Size >= 8 &&
1622 !Subtarget->is64Bit() &&
1623 Subtarget->hasSSE2()) {
1624 // Do not use f64 to lower memcpy if source is string constant. It's
1625 // better to use i32 to avoid the loads.
1629 if (Subtarget->is64Bit() && Size >= 8)
1634 bool X86TargetLowering::isSafeMemOpType(MVT VT) const {
1636 return X86ScalarSSEf32;
1637 else if (VT == MVT::f64)
1638 return X86ScalarSSEf64;
1643 X86TargetLowering::allowsUnalignedMemoryAccesses(EVT VT, bool *Fast) const {
1645 *Fast = Subtarget->isUnalignedMemAccessFast();
1649 /// getJumpTableEncoding - Return the entry encoding for a jump table in the
1650 /// current function. The returned value is a member of the
1651 /// MachineJumpTableInfo::JTEntryKind enum.
1652 unsigned X86TargetLowering::getJumpTableEncoding() const {
1653 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
1655 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1656 Subtarget->isPICStyleGOT())
1657 return MachineJumpTableInfo::EK_Custom32;
1659 // Otherwise, use the normal jump table encoding heuristics.
1660 return TargetLowering::getJumpTableEncoding();
1664 X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
1665 const MachineBasicBlock *MBB,
1666 unsigned uid,MCContext &Ctx) const{
1667 assert(getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1668 Subtarget->isPICStyleGOT());
1669 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
1671 return MCSymbolRefExpr::Create(MBB->getSymbol(),
1672 MCSymbolRefExpr::VK_GOTOFF, Ctx);
1675 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
1677 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
1678 SelectionDAG &DAG) const {
1679 if (!Subtarget->is64Bit())
1680 // This doesn't have SDLoc associated with it, but is not really the
1681 // same as a Register.
1682 return DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), getPointerTy());
1686 /// getPICJumpTableRelocBaseExpr - This returns the relocation base for the
1687 /// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an
1689 const MCExpr *X86TargetLowering::
1690 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
1691 MCContext &Ctx) const {
1692 // X86-64 uses RIP relative addressing based on the jump table label.
1693 if (Subtarget->isPICStyleRIPRel())
1694 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
1696 // Otherwise, the reference is relative to the PIC base.
1697 return MCSymbolRefExpr::Create(MF->getPICBaseSymbol(), Ctx);
1700 // FIXME: Why this routine is here? Move to RegInfo!
1701 std::pair<const TargetRegisterClass*, uint8_t>
1702 X86TargetLowering::findRepresentativeClass(MVT VT) const{
1703 const TargetRegisterClass *RRC = 0;
1705 switch (VT.SimpleTy) {
1707 return TargetLowering::findRepresentativeClass(VT);
1708 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
1709 RRC = Subtarget->is64Bit() ?
1710 (const TargetRegisterClass*)&X86::GR64RegClass :
1711 (const TargetRegisterClass*)&X86::GR32RegClass;
1714 RRC = &X86::VR64RegClass;
1716 case MVT::f32: case MVT::f64:
1717 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
1718 case MVT::v4f32: case MVT::v2f64:
1719 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32:
1721 RRC = &X86::VR128RegClass;
1724 return std::make_pair(RRC, Cost);
1727 bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace,
1728 unsigned &Offset) const {
1729 if (!Subtarget->isTargetLinux())
1732 if (Subtarget->is64Bit()) {
1733 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs:
1735 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
1747 //===----------------------------------------------------------------------===//
1748 // Return Value Calling Convention Implementation
1749 //===----------------------------------------------------------------------===//
1751 #include "X86GenCallingConv.inc"
1754 X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv,
1755 MachineFunction &MF, bool isVarArg,
1756 const SmallVectorImpl<ISD::OutputArg> &Outs,
1757 LLVMContext &Context) const {
1758 SmallVector<CCValAssign, 16> RVLocs;
1759 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
1761 return CCInfo.CheckReturn(Outs, RetCC_X86);
1765 X86TargetLowering::LowerReturn(SDValue Chain,
1766 CallingConv::ID CallConv, bool isVarArg,
1767 const SmallVectorImpl<ISD::OutputArg> &Outs,
1768 const SmallVectorImpl<SDValue> &OutVals,
1769 SDLoc dl, SelectionDAG &DAG) const {
1770 MachineFunction &MF = DAG.getMachineFunction();
1771 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1773 SmallVector<CCValAssign, 16> RVLocs;
1774 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
1775 RVLocs, *DAG.getContext());
1776 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
1779 SmallVector<SDValue, 6> RetOps;
1780 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
1781 // Operand #1 = Bytes To Pop
1782 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(),
1785 // Copy the result values into the output registers.
1786 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1787 CCValAssign &VA = RVLocs[i];
1788 assert(VA.isRegLoc() && "Can only return in registers!");
1789 SDValue ValToCopy = OutVals[i];
1790 EVT ValVT = ValToCopy.getValueType();
1792 // Promote values to the appropriate types
1793 if (VA.getLocInfo() == CCValAssign::SExt)
1794 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy);
1795 else if (VA.getLocInfo() == CCValAssign::ZExt)
1796 ValToCopy = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ValToCopy);
1797 else if (VA.getLocInfo() == CCValAssign::AExt)
1798 ValToCopy = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ValToCopy);
1799 else if (VA.getLocInfo() == CCValAssign::BCvt)
1800 ValToCopy = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), ValToCopy);
1802 // If this is x86-64, and we disabled SSE, we can't return FP values,
1803 // or SSE or MMX vectors.
1804 if ((ValVT == MVT::f32 || ValVT == MVT::f64 ||
1805 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) &&
1806 (Subtarget->is64Bit() && !Subtarget->hasSSE1())) {
1807 report_fatal_error("SSE register return with SSE disabled");
1809 // Likewise we can't return F64 values with SSE1 only. gcc does so, but
1810 // llvm-gcc has never done it right and no one has noticed, so this
1811 // should be OK for now.
1812 if (ValVT == MVT::f64 &&
1813 (Subtarget->is64Bit() && !Subtarget->hasSSE2()))
1814 report_fatal_error("SSE2 register return with SSE2 disabled");
1816 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
1817 // the RET instruction and handled by the FP Stackifier.
1818 if (VA.getLocReg() == X86::ST0 ||
1819 VA.getLocReg() == X86::ST1) {
1820 // If this is a copy from an xmm register to ST(0), use an FPExtend to
1821 // change the value to the FP stack register class.
1822 if (isScalarFPTypeInSSEReg(VA.getValVT()))
1823 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
1824 RetOps.push_back(ValToCopy);
1825 // Don't emit a copytoreg.
1829 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
1830 // which is returned in RAX / RDX.
1831 if (Subtarget->is64Bit()) {
1832 if (ValVT == MVT::x86mmx) {
1833 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
1834 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ValToCopy);
1835 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
1837 // If we don't have SSE2 available, convert to v4f32 so the generated
1838 // register is legal.
1839 if (!Subtarget->hasSSE2())
1840 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32,ValToCopy);
1845 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
1846 Flag = Chain.getValue(1);
1847 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
1850 // The x86-64 ABIs require that for returning structs by value we copy
1851 // the sret argument into %rax/%eax (depending on ABI) for the return.
1852 // Win32 requires us to put the sret argument to %eax as well.
1853 // We saved the argument into a virtual register in the entry block,
1854 // so now we copy the value out and into %rax/%eax.
1855 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr() &&
1856 (Subtarget->is64Bit() || Subtarget->isTargetWindows())) {
1857 MachineFunction &MF = DAG.getMachineFunction();
1858 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1859 unsigned Reg = FuncInfo->getSRetReturnReg();
1861 "SRetReturnReg should have been set in LowerFormalArguments().");
1862 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
1865 = (Subtarget->is64Bit() && !Subtarget->isTarget64BitILP32()) ?
1866 X86::RAX : X86::EAX;
1867 Chain = DAG.getCopyToReg(Chain, dl, RetValReg, Val, Flag);
1868 Flag = Chain.getValue(1);
1870 // RAX/EAX now acts like a return value.
1871 RetOps.push_back(DAG.getRegister(RetValReg, getPointerTy()));
1874 RetOps[0] = Chain; // Update chain.
1876 // Add the flag if we have it.
1878 RetOps.push_back(Flag);
1880 return DAG.getNode(X86ISD::RET_FLAG, dl,
1881 MVT::Other, &RetOps[0], RetOps.size());
1884 bool X86TargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
1885 if (N->getNumValues() != 1)
1887 if (!N->hasNUsesOfValue(1, 0))
1890 SDValue TCChain = Chain;
1891 SDNode *Copy = *N->use_begin();
1892 if (Copy->getOpcode() == ISD::CopyToReg) {
1893 // If the copy has a glue operand, we conservatively assume it isn't safe to
1894 // perform a tail call.
1895 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
1897 TCChain = Copy->getOperand(0);
1898 } else if (Copy->getOpcode() != ISD::FP_EXTEND)
1901 bool HasRet = false;
1902 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
1904 if (UI->getOpcode() != X86ISD::RET_FLAG)
1917 X86TargetLowering::getTypeForExtArgOrReturn(MVT VT,
1918 ISD::NodeType ExtendKind) const {
1920 // TODO: Is this also valid on 32-bit?
1921 if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND)
1922 ReturnMVT = MVT::i8;
1924 ReturnMVT = MVT::i32;
1926 MVT MinVT = getRegisterType(ReturnMVT);
1927 return VT.bitsLT(MinVT) ? MinVT : VT;
1930 /// LowerCallResult - Lower the result values of a call into the
1931 /// appropriate copies out of appropriate physical registers.
1934 X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
1935 CallingConv::ID CallConv, bool isVarArg,
1936 const SmallVectorImpl<ISD::InputArg> &Ins,
1937 SDLoc dl, SelectionDAG &DAG,
1938 SmallVectorImpl<SDValue> &InVals) const {
1940 // Assign locations to each value returned by this call.
1941 SmallVector<CCValAssign, 16> RVLocs;
1942 bool Is64Bit = Subtarget->is64Bit();
1943 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
1944 getTargetMachine(), RVLocs, *DAG.getContext());
1945 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
1947 // Copy all of the result registers out of their specified physreg.
1948 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
1949 CCValAssign &VA = RVLocs[i];
1950 EVT CopyVT = VA.getValVT();
1952 // If this is x86-64, and we disabled SSE, we can't return FP values
1953 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
1954 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) {
1955 report_fatal_error("SSE register return with SSE disabled");
1960 // If this is a call to a function that returns an fp value on the floating
1961 // point stack, we must guarantee the value is popped from the stack, so
1962 // a CopyFromReg is not good enough - the copy instruction may be eliminated
1963 // if the return value is not used. We use the FpPOP_RETVAL instruction
1965 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1) {
1966 // If we prefer to use the value in xmm registers, copy it out as f80 and
1967 // use a truncate to move it from fp stack reg to xmm reg.
1968 if (isScalarFPTypeInSSEReg(VA.getValVT())) CopyVT = MVT::f80;
1969 SDValue Ops[] = { Chain, InFlag };
1970 Chain = SDValue(DAG.getMachineNode(X86::FpPOP_RETVAL, dl, CopyVT,
1971 MVT::Other, MVT::Glue, Ops), 1);
1972 Val = Chain.getValue(0);
1974 // Round the f80 to the right size, which also moves it to the appropriate
1976 if (CopyVT != VA.getValVT())
1977 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
1978 // This truncation won't change the value.
1979 DAG.getIntPtrConstant(1));
1981 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
1982 CopyVT, InFlag).getValue(1);
1983 Val = Chain.getValue(0);
1985 InFlag = Chain.getValue(2);
1986 InVals.push_back(Val);
1992 //===----------------------------------------------------------------------===//
1993 // C & StdCall & Fast Calling Convention implementation
1994 //===----------------------------------------------------------------------===//
1995 // StdCall calling convention seems to be standard for many Windows' API
1996 // routines and around. It differs from C calling convention just a little:
1997 // callee should clean up the stack, not caller. Symbols should be also
1998 // decorated in some fancy way :) It doesn't support any vector arguments.
1999 // For info on fast calling convention see Fast Calling Convention (tail call)
2000 // implementation LowerX86_32FastCCCallTo.
2002 /// CallIsStructReturn - Determines whether a call uses struct return
2004 enum StructReturnType {
2009 static StructReturnType
2010 callIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
2012 return NotStructReturn;
2014 const ISD::ArgFlagsTy &Flags = Outs[0].Flags;
2015 if (!Flags.isSRet())
2016 return NotStructReturn;
2017 if (Flags.isInReg())
2018 return RegStructReturn;
2019 return StackStructReturn;
2022 /// ArgsAreStructReturn - Determines whether a function uses struct
2023 /// return semantics.
2024 static StructReturnType
2025 argsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
2027 return NotStructReturn;
2029 const ISD::ArgFlagsTy &Flags = Ins[0].Flags;
2030 if (!Flags.isSRet())
2031 return NotStructReturn;
2032 if (Flags.isInReg())
2033 return RegStructReturn;
2034 return StackStructReturn;
2037 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
2038 /// by "Src" to address "Dst" with size and alignment information specified by
2039 /// the specific parameter attribute. The copy will be passed as a byval
2040 /// function parameter.
2042 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
2043 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
2045 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
2047 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
2048 /*isVolatile*/false, /*AlwaysInline=*/true,
2049 MachinePointerInfo(), MachinePointerInfo());
2052 /// IsTailCallConvention - Return true if the calling convention is one that
2053 /// supports tail call optimization.
2054 static bool IsTailCallConvention(CallingConv::ID CC) {
2055 return (CC == CallingConv::Fast || CC == CallingConv::GHC ||
2056 CC == CallingConv::HiPE);
2059 /// \brief Return true if the calling convention is a C calling convention.
2060 static bool IsCCallConvention(CallingConv::ID CC) {
2061 return (CC == CallingConv::C || CC == CallingConv::X86_64_Win64 ||
2062 CC == CallingConv::X86_64_SysV);
2065 bool X86TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
2066 if (!CI->isTailCall() || getTargetMachine().Options.DisableTailCalls)
2070 CallingConv::ID CalleeCC = CS.getCallingConv();
2071 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
2077 /// FuncIsMadeTailCallSafe - Return true if the function is being made into
2078 /// a tailcall target by changing its ABI.
2079 static bool FuncIsMadeTailCallSafe(CallingConv::ID CC,
2080 bool GuaranteedTailCallOpt) {
2081 return GuaranteedTailCallOpt && IsTailCallConvention(CC);
2085 X86TargetLowering::LowerMemArgument(SDValue Chain,
2086 CallingConv::ID CallConv,
2087 const SmallVectorImpl<ISD::InputArg> &Ins,
2088 SDLoc dl, SelectionDAG &DAG,
2089 const CCValAssign &VA,
2090 MachineFrameInfo *MFI,
2092 // Create the nodes corresponding to a load from this parameter slot.
2093 ISD::ArgFlagsTy Flags = Ins[i].Flags;
2094 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(CallConv,
2095 getTargetMachine().Options.GuaranteedTailCallOpt);
2096 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
2099 // If value is passed by pointer we have address passed instead of the value
2101 if (VA.getLocInfo() == CCValAssign::Indirect)
2102 ValVT = VA.getLocVT();
2104 ValVT = VA.getValVT();
2106 // FIXME: For now, all byval parameter objects are marked mutable. This can be
2107 // changed with more analysis.
2108 // In case of tail call optimization mark all arguments mutable. Since they
2109 // could be overwritten by lowering of arguments in case of a tail call.
2110 if (Flags.isByVal()) {
2111 unsigned Bytes = Flags.getByValSize();
2112 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects.
2113 int FI = MFI->CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable);
2114 return DAG.getFrameIndex(FI, getPointerTy());
2116 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
2117 VA.getLocMemOffset(), isImmutable);
2118 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2119 return DAG.getLoad(ValVT, dl, Chain, FIN,
2120 MachinePointerInfo::getFixedStack(FI),
2121 false, false, false, 0);
2126 X86TargetLowering::LowerFormalArguments(SDValue Chain,
2127 CallingConv::ID CallConv,
2129 const SmallVectorImpl<ISD::InputArg> &Ins,
2132 SmallVectorImpl<SDValue> &InVals)
2134 MachineFunction &MF = DAG.getMachineFunction();
2135 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2137 const Function* Fn = MF.getFunction();
2138 if (Fn->hasExternalLinkage() &&
2139 Subtarget->isTargetCygMing() &&
2140 Fn->getName() == "main")
2141 FuncInfo->setForceFramePointer(true);
2143 MachineFrameInfo *MFI = MF.getFrameInfo();
2144 bool Is64Bit = Subtarget->is64Bit();
2145 bool IsWindows = Subtarget->isTargetWindows();
2146 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2148 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2149 "Var args not supported with calling convention fastcc, ghc or hipe");
2151 // Assign locations to all of the incoming arguments.
2152 SmallVector<CCValAssign, 16> ArgLocs;
2153 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
2154 ArgLocs, *DAG.getContext());
2156 // Allocate shadow area for Win64
2158 CCInfo.AllocateStack(32, 8);
2160 CCInfo.AnalyzeFormalArguments(Ins, CC_X86);
2162 unsigned LastVal = ~0U;
2164 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2165 CCValAssign &VA = ArgLocs[i];
2166 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
2168 assert(VA.getValNo() != LastVal &&
2169 "Don't support value assigned to multiple locs yet");
2171 LastVal = VA.getValNo();
2173 if (VA.isRegLoc()) {
2174 EVT RegVT = VA.getLocVT();
2175 const TargetRegisterClass *RC;
2176 if (RegVT == MVT::i32)
2177 RC = &X86::GR32RegClass;
2178 else if (Is64Bit && RegVT == MVT::i64)
2179 RC = &X86::GR64RegClass;
2180 else if (RegVT == MVT::f32)
2181 RC = &X86::FR32RegClass;
2182 else if (RegVT == MVT::f64)
2183 RC = &X86::FR64RegClass;
2184 else if (RegVT.is512BitVector())
2185 RC = &X86::VR512RegClass;
2186 else if (RegVT.is256BitVector())
2187 RC = &X86::VR256RegClass;
2188 else if (RegVT.is128BitVector())
2189 RC = &X86::VR128RegClass;
2190 else if (RegVT == MVT::x86mmx)
2191 RC = &X86::VR64RegClass;
2192 else if (RegVT == MVT::v8i1)
2193 RC = &X86::VK8RegClass;
2194 else if (RegVT == MVT::v16i1)
2195 RC = &X86::VK16RegClass;
2197 llvm_unreachable("Unknown argument type!");
2199 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2200 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
2202 // If this is an 8 or 16-bit value, it is really passed promoted to 32
2203 // bits. Insert an assert[sz]ext to capture this, then truncate to the
2205 if (VA.getLocInfo() == CCValAssign::SExt)
2206 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
2207 DAG.getValueType(VA.getValVT()));
2208 else if (VA.getLocInfo() == CCValAssign::ZExt)
2209 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
2210 DAG.getValueType(VA.getValVT()));
2211 else if (VA.getLocInfo() == CCValAssign::BCvt)
2212 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
2214 if (VA.isExtInLoc()) {
2215 // Handle MMX values passed in XMM regs.
2216 if (RegVT.isVector())
2217 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(), ArgValue);
2219 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
2222 assert(VA.isMemLoc());
2223 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
2226 // If value is passed via pointer - do a load.
2227 if (VA.getLocInfo() == CCValAssign::Indirect)
2228 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue,
2229 MachinePointerInfo(), false, false, false, 0);
2231 InVals.push_back(ArgValue);
2234 // The x86-64 ABIs require that for returning structs by value we copy
2235 // the sret argument into %rax/%eax (depending on ABI) for the return.
2236 // Win32 requires us to put the sret argument to %eax as well.
2237 // Save the argument into a virtual register so that we can access it
2238 // from the return points.
2239 if (MF.getFunction()->hasStructRetAttr() &&
2240 (Subtarget->is64Bit() || Subtarget->isTargetWindows())) {
2241 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2242 unsigned Reg = FuncInfo->getSRetReturnReg();
2244 MVT PtrTy = getPointerTy();
2245 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(PtrTy));
2246 FuncInfo->setSRetReturnReg(Reg);
2248 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]);
2249 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
2252 unsigned StackSize = CCInfo.getNextStackOffset();
2253 // Align stack specially for tail calls.
2254 if (FuncIsMadeTailCallSafe(CallConv,
2255 MF.getTarget().Options.GuaranteedTailCallOpt))
2256 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
2258 // If the function takes variable number of arguments, make a frame index for
2259 // the start of the first vararg value... for expansion of llvm.va_start.
2261 if (Is64Bit || (CallConv != CallingConv::X86_FastCall &&
2262 CallConv != CallingConv::X86_ThisCall)) {
2263 FuncInfo->setVarArgsFrameIndex(MFI->CreateFixedObject(1, StackSize,true));
2266 unsigned TotalNumIntRegs = 0, TotalNumXMMRegs = 0;
2268 // FIXME: We should really autogenerate these arrays
2269 static const uint16_t GPR64ArgRegsWin64[] = {
2270 X86::RCX, X86::RDX, X86::R8, X86::R9
2272 static const uint16_t GPR64ArgRegs64Bit[] = {
2273 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
2275 static const uint16_t XMMArgRegs64Bit[] = {
2276 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2277 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2279 const uint16_t *GPR64ArgRegs;
2280 unsigned NumXMMRegs = 0;
2283 // The XMM registers which might contain var arg parameters are shadowed
2284 // in their paired GPR. So we only need to save the GPR to their home
2286 TotalNumIntRegs = 4;
2287 GPR64ArgRegs = GPR64ArgRegsWin64;
2289 TotalNumIntRegs = 6; TotalNumXMMRegs = 8;
2290 GPR64ArgRegs = GPR64ArgRegs64Bit;
2292 NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs64Bit,
2295 unsigned NumIntRegs = CCInfo.getFirstUnallocated(GPR64ArgRegs,
2298 bool NoImplicitFloatOps = Fn->getAttributes().
2299 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoImplicitFloat);
2300 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) &&
2301 "SSE register cannot be used when SSE is disabled!");
2302 assert(!(NumXMMRegs && MF.getTarget().Options.UseSoftFloat &&
2303 NoImplicitFloatOps) &&
2304 "SSE register cannot be used when SSE is disabled!");
2305 if (MF.getTarget().Options.UseSoftFloat || NoImplicitFloatOps ||
2306 !Subtarget->hasSSE1())
2307 // Kernel mode asks for SSE to be disabled, so don't push them
2309 TotalNumXMMRegs = 0;
2312 const TargetFrameLowering &TFI = *getTargetMachine().getFrameLowering();
2313 // Get to the caller-allocated home save location. Add 8 to account
2314 // for the return address.
2315 int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
2316 FuncInfo->setRegSaveFrameIndex(
2317 MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false));
2318 // Fixup to set vararg frame on shadow area (4 x i64).
2320 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex());
2322 // For X86-64, if there are vararg parameters that are passed via
2323 // registers, then we must store them to their spots on the stack so
2324 // they may be loaded by deferencing the result of va_next.
2325 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8);
2326 FuncInfo->setVarArgsFPOffset(TotalNumIntRegs * 8 + NumXMMRegs * 16);
2327 FuncInfo->setRegSaveFrameIndex(
2328 MFI->CreateStackObject(TotalNumIntRegs * 8 + TotalNumXMMRegs * 16, 16,
2332 // Store the integer parameter registers.
2333 SmallVector<SDValue, 8> MemOps;
2334 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
2336 unsigned Offset = FuncInfo->getVarArgsGPOffset();
2337 for (; NumIntRegs != TotalNumIntRegs; ++NumIntRegs) {
2338 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN,
2339 DAG.getIntPtrConstant(Offset));
2340 unsigned VReg = MF.addLiveIn(GPR64ArgRegs[NumIntRegs],
2341 &X86::GR64RegClass);
2342 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
2344 DAG.getStore(Val.getValue(1), dl, Val, FIN,
2345 MachinePointerInfo::getFixedStack(
2346 FuncInfo->getRegSaveFrameIndex(), Offset),
2348 MemOps.push_back(Store);
2352 if (TotalNumXMMRegs != 0 && NumXMMRegs != TotalNumXMMRegs) {
2353 // Now store the XMM (fp + vector) parameter registers.
2354 SmallVector<SDValue, 11> SaveXMMOps;
2355 SaveXMMOps.push_back(Chain);
2357 unsigned AL = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
2358 SDValue ALVal = DAG.getCopyFromReg(DAG.getEntryNode(), dl, AL, MVT::i8);
2359 SaveXMMOps.push_back(ALVal);
2361 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2362 FuncInfo->getRegSaveFrameIndex()));
2363 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2364 FuncInfo->getVarArgsFPOffset()));
2366 for (; NumXMMRegs != TotalNumXMMRegs; ++NumXMMRegs) {
2367 unsigned VReg = MF.addLiveIn(XMMArgRegs64Bit[NumXMMRegs],
2368 &X86::VR128RegClass);
2369 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::v4f32);
2370 SaveXMMOps.push_back(Val);
2372 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
2374 &SaveXMMOps[0], SaveXMMOps.size()));
2377 if (!MemOps.empty())
2378 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2379 &MemOps[0], MemOps.size());
2383 // Some CCs need callee pop.
2384 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2385 MF.getTarget().Options.GuaranteedTailCallOpt)) {
2386 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything.
2388 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing.
2389 // If this is an sret function, the return should pop the hidden pointer.
2390 if (!Is64Bit && !IsTailCallConvention(CallConv) && !IsWindows &&
2391 argsAreStructReturn(Ins) == StackStructReturn)
2392 FuncInfo->setBytesToPopOnReturn(4);
2396 // RegSaveFrameIndex is X86-64 only.
2397 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
2398 if (CallConv == CallingConv::X86_FastCall ||
2399 CallConv == CallingConv::X86_ThisCall)
2400 // fastcc functions can't have varargs.
2401 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA);
2404 FuncInfo->setArgumentStackSize(StackSize);
2410 X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
2411 SDValue StackPtr, SDValue Arg,
2412 SDLoc dl, SelectionDAG &DAG,
2413 const CCValAssign &VA,
2414 ISD::ArgFlagsTy Flags) const {
2415 unsigned LocMemOffset = VA.getLocMemOffset();
2416 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
2417 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
2418 if (Flags.isByVal())
2419 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
2421 return DAG.getStore(Chain, dl, Arg, PtrOff,
2422 MachinePointerInfo::getStack(LocMemOffset),
2426 /// EmitTailCallLoadRetAddr - Emit a load of return address if tail call
2427 /// optimization is performed and it is required.
2429 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
2430 SDValue &OutRetAddr, SDValue Chain,
2431 bool IsTailCall, bool Is64Bit,
2432 int FPDiff, SDLoc dl) const {
2433 // Adjust the Return address stack slot.
2434 EVT VT = getPointerTy();
2435 OutRetAddr = getReturnAddressFrameIndex(DAG);
2437 // Load the "old" Return address.
2438 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(),
2439 false, false, false, 0);
2440 return SDValue(OutRetAddr.getNode(), 1);
2443 /// EmitTailCallStoreRetAddr - Emit a store of the return address if tail call
2444 /// optimization is performed and it is required (FPDiff!=0).
2446 EmitTailCallStoreRetAddr(SelectionDAG & DAG, MachineFunction &MF,
2447 SDValue Chain, SDValue RetAddrFrIdx, EVT PtrVT,
2448 unsigned SlotSize, int FPDiff, SDLoc dl) {
2449 // Store the return address to the appropriate stack slot.
2450 if (!FPDiff) return Chain;
2451 // Calculate the new stack slot for the return address.
2452 int NewReturnAddrFI =
2453 MF.getFrameInfo()->CreateFixedObject(SlotSize, (int64_t)FPDiff - SlotSize,
2455 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, PtrVT);
2456 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
2457 MachinePointerInfo::getFixedStack(NewReturnAddrFI),
2463 X86TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
2464 SmallVectorImpl<SDValue> &InVals) const {
2465 SelectionDAG &DAG = CLI.DAG;
2467 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
2468 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
2469 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
2470 SDValue Chain = CLI.Chain;
2471 SDValue Callee = CLI.Callee;
2472 CallingConv::ID CallConv = CLI.CallConv;
2473 bool &isTailCall = CLI.IsTailCall;
2474 bool isVarArg = CLI.IsVarArg;
2476 MachineFunction &MF = DAG.getMachineFunction();
2477 bool Is64Bit = Subtarget->is64Bit();
2478 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2479 bool IsWindows = Subtarget->isTargetWindows();
2480 StructReturnType SR = callIsStructReturn(Outs);
2481 bool IsSibcall = false;
2483 if (MF.getTarget().Options.DisableTailCalls)
2487 // Check if it's really possible to do a tail call.
2488 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
2489 isVarArg, SR != NotStructReturn,
2490 MF.getFunction()->hasStructRetAttr(), CLI.RetTy,
2491 Outs, OutVals, Ins, DAG);
2493 // Sibcalls are automatically detected tailcalls which do not require
2495 if (!MF.getTarget().Options.GuaranteedTailCallOpt && isTailCall)
2502 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2503 "Var args not supported with calling convention fastcc, ghc or hipe");
2505 // Analyze operands of the call, assigning locations to each operand.
2506 SmallVector<CCValAssign, 16> ArgLocs;
2507 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
2508 ArgLocs, *DAG.getContext());
2510 // Allocate shadow area for Win64
2512 CCInfo.AllocateStack(32, 8);
2514 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2516 // Get a count of how many bytes are to be pushed on the stack.
2517 unsigned NumBytes = CCInfo.getNextStackOffset();
2519 // This is a sibcall. The memory operands are available in caller's
2520 // own caller's stack.
2522 else if (getTargetMachine().Options.GuaranteedTailCallOpt &&
2523 IsTailCallConvention(CallConv))
2524 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
2527 if (isTailCall && !IsSibcall) {
2528 // Lower arguments at fp - stackoffset + fpdiff.
2529 X86MachineFunctionInfo *X86Info = MF.getInfo<X86MachineFunctionInfo>();
2530 unsigned NumBytesCallerPushed = X86Info->getBytesToPopOnReturn();
2532 FPDiff = NumBytesCallerPushed - NumBytes;
2534 // Set the delta of movement of the returnaddr stackslot.
2535 // But only set if delta is greater than previous delta.
2536 if (FPDiff < X86Info->getTCReturnAddrDelta())
2537 X86Info->setTCReturnAddrDelta(FPDiff);
2541 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true),
2544 SDValue RetAddrFrIdx;
2545 // Load return address for tail calls.
2546 if (isTailCall && FPDiff)
2547 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall,
2548 Is64Bit, FPDiff, dl);
2550 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
2551 SmallVector<SDValue, 8> MemOpChains;
2554 // Walk the register/memloc assignments, inserting copies/loads. In the case
2555 // of tail call optimization arguments are handle later.
2556 const X86RegisterInfo *RegInfo =
2557 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
2558 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2559 CCValAssign &VA = ArgLocs[i];
2560 EVT RegVT = VA.getLocVT();
2561 SDValue Arg = OutVals[i];
2562 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2563 bool isByVal = Flags.isByVal();
2565 // Promote the value if needed.
2566 switch (VA.getLocInfo()) {
2567 default: llvm_unreachable("Unknown loc info!");
2568 case CCValAssign::Full: break;
2569 case CCValAssign::SExt:
2570 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
2572 case CCValAssign::ZExt:
2573 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
2575 case CCValAssign::AExt:
2576 if (RegVT.is128BitVector()) {
2577 // Special case: passing MMX values in XMM registers.
2578 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg);
2579 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
2580 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
2582 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
2584 case CCValAssign::BCvt:
2585 Arg = DAG.getNode(ISD::BITCAST, dl, RegVT, Arg);
2587 case CCValAssign::Indirect: {
2588 // Store the argument.
2589 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
2590 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
2591 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot,
2592 MachinePointerInfo::getFixedStack(FI),
2599 if (VA.isRegLoc()) {
2600 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2601 if (isVarArg && IsWin64) {
2602 // Win64 ABI requires argument XMM reg to be copied to the corresponding
2603 // shadow reg if callee is a varargs function.
2604 unsigned ShadowReg = 0;
2605 switch (VA.getLocReg()) {
2606 case X86::XMM0: ShadowReg = X86::RCX; break;
2607 case X86::XMM1: ShadowReg = X86::RDX; break;
2608 case X86::XMM2: ShadowReg = X86::R8; break;
2609 case X86::XMM3: ShadowReg = X86::R9; break;
2612 RegsToPass.push_back(std::make_pair(ShadowReg, Arg));
2614 } else if (!IsSibcall && (!isTailCall || isByVal)) {
2615 assert(VA.isMemLoc());
2616 if (StackPtr.getNode() == 0)
2617 StackPtr = DAG.getCopyFromReg(Chain, dl, RegInfo->getStackRegister(),
2619 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
2620 dl, DAG, VA, Flags));
2624 if (!MemOpChains.empty())
2625 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2626 &MemOpChains[0], MemOpChains.size());
2628 if (Subtarget->isPICStyleGOT()) {
2629 // ELF / PIC requires GOT in the EBX register before function calls via PLT
2632 RegsToPass.push_back(std::make_pair(unsigned(X86::EBX),
2633 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), getPointerTy())));
2635 // If we are tail calling and generating PIC/GOT style code load the
2636 // address of the callee into ECX. The value in ecx is used as target of
2637 // the tail jump. This is done to circumvent the ebx/callee-saved problem
2638 // for tail calls on PIC/GOT architectures. Normally we would just put the
2639 // address of GOT into ebx and then call target@PLT. But for tail calls
2640 // ebx would be restored (since ebx is callee saved) before jumping to the
2643 // Note: The actual moving to ECX is done further down.
2644 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
2645 if (G && !G->getGlobal()->hasHiddenVisibility() &&
2646 !G->getGlobal()->hasProtectedVisibility())
2647 Callee = LowerGlobalAddress(Callee, DAG);
2648 else if (isa<ExternalSymbolSDNode>(Callee))
2649 Callee = LowerExternalSymbol(Callee, DAG);
2653 if (Is64Bit && isVarArg && !IsWin64) {
2654 // From AMD64 ABI document:
2655 // For calls that may call functions that use varargs or stdargs
2656 // (prototype-less calls or calls to functions containing ellipsis (...) in
2657 // the declaration) %al is used as hidden argument to specify the number
2658 // of SSE registers used. The contents of %al do not need to match exactly
2659 // the number of registers, but must be an ubound on the number of SSE
2660 // registers used and is in the range 0 - 8 inclusive.
2662 // Count the number of XMM registers allocated.
2663 static const uint16_t XMMArgRegs[] = {
2664 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2665 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2667 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
2668 assert((Subtarget->hasSSE1() || !NumXMMRegs)
2669 && "SSE registers cannot be used when SSE is disabled");
2671 RegsToPass.push_back(std::make_pair(unsigned(X86::AL),
2672 DAG.getConstant(NumXMMRegs, MVT::i8)));
2675 // For tail calls lower the arguments to the 'real' stack slot.
2677 // Force all the incoming stack arguments to be loaded from the stack
2678 // before any new outgoing arguments are stored to the stack, because the
2679 // outgoing stack slots may alias the incoming argument stack slots, and
2680 // the alias isn't otherwise explicit. This is slightly more conservative
2681 // than necessary, because it means that each store effectively depends
2682 // on every argument instead of just those arguments it would clobber.
2683 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
2685 SmallVector<SDValue, 8> MemOpChains2;
2688 if (getTargetMachine().Options.GuaranteedTailCallOpt) {
2689 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2690 CCValAssign &VA = ArgLocs[i];
2693 assert(VA.isMemLoc());
2694 SDValue Arg = OutVals[i];
2695 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2696 // Create frame index.
2697 int32_t Offset = VA.getLocMemOffset()+FPDiff;
2698 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
2699 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
2700 FIN = DAG.getFrameIndex(FI, getPointerTy());
2702 if (Flags.isByVal()) {
2703 // Copy relative to framepointer.
2704 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset());
2705 if (StackPtr.getNode() == 0)
2706 StackPtr = DAG.getCopyFromReg(Chain, dl,
2707 RegInfo->getStackRegister(),
2709 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source);
2711 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
2715 // Store relative to framepointer.
2716 MemOpChains2.push_back(
2717 DAG.getStore(ArgChain, dl, Arg, FIN,
2718 MachinePointerInfo::getFixedStack(FI),
2724 if (!MemOpChains2.empty())
2725 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2726 &MemOpChains2[0], MemOpChains2.size());
2728 // Store the return address to the appropriate stack slot.
2729 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx,
2730 getPointerTy(), RegInfo->getSlotSize(),
2734 // Build a sequence of copy-to-reg nodes chained together with token chain
2735 // and flag operands which copy the outgoing args into registers.
2737 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2738 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
2739 RegsToPass[i].second, InFlag);
2740 InFlag = Chain.getValue(1);
2743 if (getTargetMachine().getCodeModel() == CodeModel::Large) {
2744 assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
2745 // In the 64-bit large code model, we have to make all calls
2746 // through a register, since the call instruction's 32-bit
2747 // pc-relative offset may not be large enough to hold the whole
2749 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2750 // If the callee is a GlobalAddress node (quite common, every direct call
2751 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
2754 // We should use extra load for direct calls to dllimported functions in
2756 const GlobalValue *GV = G->getGlobal();
2757 if (!GV->hasDLLImportLinkage()) {
2758 unsigned char OpFlags = 0;
2759 bool ExtraLoad = false;
2760 unsigned WrapperKind = ISD::DELETED_NODE;
2762 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
2763 // external symbols most go through the PLT in PIC mode. If the symbol
2764 // has hidden or protected visibility, or if it is static or local, then
2765 // we don't need to use the PLT - we can directly call it.
2766 if (Subtarget->isTargetELF() &&
2767 getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
2768 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
2769 OpFlags = X86II::MO_PLT;
2770 } else if (Subtarget->isPICStyleStubAny() &&
2771 (GV->isDeclaration() || GV->isWeakForLinker()) &&
2772 (!Subtarget->getTargetTriple().isMacOSX() ||
2773 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
2774 // PC-relative references to external symbols should go through $stub,
2775 // unless we're building with the leopard linker or later, which
2776 // automatically synthesizes these stubs.
2777 OpFlags = X86II::MO_DARWIN_STUB;
2778 } else if (Subtarget->isPICStyleRIPRel() &&
2779 isa<Function>(GV) &&
2780 cast<Function>(GV)->getAttributes().
2781 hasAttribute(AttributeSet::FunctionIndex,
2782 Attribute::NonLazyBind)) {
2783 // If the function is marked as non-lazy, generate an indirect call
2784 // which loads from the GOT directly. This avoids runtime overhead
2785 // at the cost of eager binding (and one extra byte of encoding).
2786 OpFlags = X86II::MO_GOTPCREL;
2787 WrapperKind = X86ISD::WrapperRIP;
2791 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(),
2792 G->getOffset(), OpFlags);
2794 // Add a wrapper if needed.
2795 if (WrapperKind != ISD::DELETED_NODE)
2796 Callee = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Callee);
2797 // Add extra indirection if needed.
2799 Callee = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Callee,
2800 MachinePointerInfo::getGOT(),
2801 false, false, false, 0);
2803 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
2804 unsigned char OpFlags = 0;
2806 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to
2807 // external symbols should go through the PLT.
2808 if (Subtarget->isTargetELF() &&
2809 getTargetMachine().getRelocationModel() == Reloc::PIC_) {
2810 OpFlags = X86II::MO_PLT;
2811 } else if (Subtarget->isPICStyleStubAny() &&
2812 (!Subtarget->getTargetTriple().isMacOSX() ||
2813 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
2814 // PC-relative references to external symbols should go through $stub,
2815 // unless we're building with the leopard linker or later, which
2816 // automatically synthesizes these stubs.
2817 OpFlags = X86II::MO_DARWIN_STUB;
2820 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(),
2824 // Returns a chain & a flag for retval copy to use.
2825 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
2826 SmallVector<SDValue, 8> Ops;
2828 if (!IsSibcall && isTailCall) {
2829 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
2830 DAG.getIntPtrConstant(0, true), InFlag, dl);
2831 InFlag = Chain.getValue(1);
2834 Ops.push_back(Chain);
2835 Ops.push_back(Callee);
2838 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32));
2840 // Add argument registers to the end of the list so that they are known live
2842 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
2843 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
2844 RegsToPass[i].second.getValueType()));
2846 // Add a register mask operand representing the call-preserved registers.
2847 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
2848 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv);
2849 assert(Mask && "Missing call preserved mask for calling convention");
2850 Ops.push_back(DAG.getRegisterMask(Mask));
2852 if (InFlag.getNode())
2853 Ops.push_back(InFlag);
2857 //// If this is the first return lowered for this function, add the regs
2858 //// to the liveout set for the function.
2859 // This isn't right, although it's probably harmless on x86; liveouts
2860 // should be computed from returns not tail calls. Consider a void
2861 // function making a tail call to a function returning int.
2862 return DAG.getNode(X86ISD::TC_RETURN, dl, NodeTys, &Ops[0], Ops.size());
2865 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, &Ops[0], Ops.size());
2866 InFlag = Chain.getValue(1);
2868 // Create the CALLSEQ_END node.
2869 unsigned NumBytesForCalleeToPush;
2870 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2871 getTargetMachine().Options.GuaranteedTailCallOpt))
2872 NumBytesForCalleeToPush = NumBytes; // Callee pops everything
2873 else if (!Is64Bit && !IsTailCallConvention(CallConv) && !IsWindows &&
2874 SR == StackStructReturn)
2875 // If this is a call to a struct-return function, the callee
2876 // pops the hidden struct pointer, so we have to push it back.
2877 // This is common for Darwin/X86, Linux & Mingw32 targets.
2878 // For MSVC Win32 targets, the caller pops the hidden struct pointer.
2879 NumBytesForCalleeToPush = 4;
2881 NumBytesForCalleeToPush = 0; // Callee pops nothing.
2883 // Returns a flag for retval copy to use.
2885 Chain = DAG.getCALLSEQ_END(Chain,
2886 DAG.getIntPtrConstant(NumBytes, true),
2887 DAG.getIntPtrConstant(NumBytesForCalleeToPush,
2890 InFlag = Chain.getValue(1);
2893 // Handle result values, copying them out of physregs into vregs that we
2895 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
2896 Ins, dl, DAG, InVals);
2899 //===----------------------------------------------------------------------===//
2900 // Fast Calling Convention (tail call) implementation
2901 //===----------------------------------------------------------------------===//
2903 // Like std call, callee cleans arguments, convention except that ECX is
2904 // reserved for storing the tail called function address. Only 2 registers are
2905 // free for argument passing (inreg). Tail call optimization is performed
2907 // * tailcallopt is enabled
2908 // * caller/callee are fastcc
2909 // On X86_64 architecture with GOT-style position independent code only local
2910 // (within module) calls are supported at the moment.
2911 // To keep the stack aligned according to platform abi the function
2912 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
2913 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
2914 // If a tail called function callee has more arguments than the caller the
2915 // caller needs to make sure that there is room to move the RETADDR to. This is
2916 // achieved by reserving an area the size of the argument delta right after the
2917 // original REtADDR, but before the saved framepointer or the spilled registers
2918 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
2930 /// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned
2931 /// for a 16 byte align requirement.
2933 X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
2934 SelectionDAG& DAG) const {
2935 MachineFunction &MF = DAG.getMachineFunction();
2936 const TargetMachine &TM = MF.getTarget();
2937 const X86RegisterInfo *RegInfo =
2938 static_cast<const X86RegisterInfo*>(TM.getRegisterInfo());
2939 const TargetFrameLowering &TFI = *TM.getFrameLowering();
2940 unsigned StackAlignment = TFI.getStackAlignment();
2941 uint64_t AlignMask = StackAlignment - 1;
2942 int64_t Offset = StackSize;
2943 unsigned SlotSize = RegInfo->getSlotSize();
2944 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
2945 // Number smaller than 12 so just add the difference.
2946 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
2948 // Mask out lower bits, add stackalignment once plus the 12 bytes.
2949 Offset = ((~AlignMask) & Offset) + StackAlignment +
2950 (StackAlignment-SlotSize);
2955 /// MatchingStackOffset - Return true if the given stack call argument is
2956 /// already available in the same position (relatively) of the caller's
2957 /// incoming argument stack.
2959 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
2960 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
2961 const X86InstrInfo *TII) {
2962 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
2964 if (Arg.getOpcode() == ISD::CopyFromReg) {
2965 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
2966 if (!TargetRegisterInfo::isVirtualRegister(VR))
2968 MachineInstr *Def = MRI->getVRegDef(VR);
2971 if (!Flags.isByVal()) {
2972 if (!TII->isLoadFromStackSlot(Def, FI))
2975 unsigned Opcode = Def->getOpcode();
2976 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r) &&
2977 Def->getOperand(1).isFI()) {
2978 FI = Def->getOperand(1).getIndex();
2979 Bytes = Flags.getByValSize();
2983 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
2984 if (Flags.isByVal())
2985 // ByVal argument is passed in as a pointer but it's now being
2986 // dereferenced. e.g.
2987 // define @foo(%struct.X* %A) {
2988 // tail call @bar(%struct.X* byval %A)
2991 SDValue Ptr = Ld->getBasePtr();
2992 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
2995 FI = FINode->getIndex();
2996 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) {
2997 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg);
2998 FI = FINode->getIndex();
2999 Bytes = Flags.getByValSize();
3003 assert(FI != INT_MAX);
3004 if (!MFI->isFixedObjectIndex(FI))
3006 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
3009 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
3010 /// for tail call optimization. Targets which want to do tail call
3011 /// optimization should implement this function.
3013 X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
3014 CallingConv::ID CalleeCC,
3016 bool isCalleeStructRet,
3017 bool isCallerStructRet,
3019 const SmallVectorImpl<ISD::OutputArg> &Outs,
3020 const SmallVectorImpl<SDValue> &OutVals,
3021 const SmallVectorImpl<ISD::InputArg> &Ins,
3022 SelectionDAG &DAG) const {
3023 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
3026 // If -tailcallopt is specified, make fastcc functions tail-callable.
3027 const MachineFunction &MF = DAG.getMachineFunction();
3028 const Function *CallerF = MF.getFunction();
3030 // If the function return type is x86_fp80 and the callee return type is not,
3031 // then the FP_EXTEND of the call result is not a nop. It's not safe to
3032 // perform a tailcall optimization here.
3033 if (CallerF->getReturnType()->isX86_FP80Ty() && !RetTy->isX86_FP80Ty())
3036 CallingConv::ID CallerCC = CallerF->getCallingConv();
3037 bool CCMatch = CallerCC == CalleeCC;
3038 bool IsCalleeWin64 = Subtarget->isCallingConvWin64(CalleeCC);
3039 bool IsCallerWin64 = Subtarget->isCallingConvWin64(CallerCC);
3041 if (getTargetMachine().Options.GuaranteedTailCallOpt) {
3042 if (IsTailCallConvention(CalleeCC) && CCMatch)
3047 // Look for obvious safe cases to perform tail call optimization that do not
3048 // require ABI changes. This is what gcc calls sibcall.
3050 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
3051 // emit a special epilogue.
3052 const X86RegisterInfo *RegInfo =
3053 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
3054 if (RegInfo->needsStackRealignment(MF))
3057 // Also avoid sibcall optimization if either caller or callee uses struct
3058 // return semantics.
3059 if (isCalleeStructRet || isCallerStructRet)
3062 // An stdcall caller is expected to clean up its arguments; the callee
3063 // isn't going to do that.
3064 if (!CCMatch && CallerCC == CallingConv::X86_StdCall)
3067 // Do not sibcall optimize vararg calls unless all arguments are passed via
3069 if (isVarArg && !Outs.empty()) {
3071 // Optimizing for varargs on Win64 is unlikely to be safe without
3072 // additional testing.
3073 if (IsCalleeWin64 || IsCallerWin64)
3076 SmallVector<CCValAssign, 16> ArgLocs;
3077 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(),
3078 getTargetMachine(), ArgLocs, *DAG.getContext());
3080 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3081 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
3082 if (!ArgLocs[i].isRegLoc())
3086 // If the call result is in ST0 / ST1, it needs to be popped off the x87
3087 // stack. Therefore, if it's not used by the call it is not safe to optimize
3088 // this into a sibcall.
3089 bool Unused = false;
3090 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
3097 SmallVector<CCValAssign, 16> RVLocs;
3098 CCState CCInfo(CalleeCC, false, DAG.getMachineFunction(),
3099 getTargetMachine(), RVLocs, *DAG.getContext());
3100 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
3101 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
3102 CCValAssign &VA = RVLocs[i];
3103 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1)
3108 // If the calling conventions do not match, then we'd better make sure the
3109 // results are returned in the same way as what the caller expects.
3111 SmallVector<CCValAssign, 16> RVLocs1;
3112 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(),
3113 getTargetMachine(), RVLocs1, *DAG.getContext());
3114 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86);
3116 SmallVector<CCValAssign, 16> RVLocs2;
3117 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(),
3118 getTargetMachine(), RVLocs2, *DAG.getContext());
3119 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86);
3121 if (RVLocs1.size() != RVLocs2.size())
3123 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
3124 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
3126 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
3128 if (RVLocs1[i].isRegLoc()) {
3129 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
3132 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
3138 // If the callee takes no arguments then go on to check the results of the
3140 if (!Outs.empty()) {
3141 // Check if stack adjustment is needed. For now, do not do this if any
3142 // argument is passed on the stack.
3143 SmallVector<CCValAssign, 16> ArgLocs;
3144 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(),
3145 getTargetMachine(), ArgLocs, *DAG.getContext());
3147 // Allocate shadow area for Win64
3149 CCInfo.AllocateStack(32, 8);
3151 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3152 if (CCInfo.getNextStackOffset()) {
3153 MachineFunction &MF = DAG.getMachineFunction();
3154 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn())
3157 // Check if the arguments are already laid out in the right way as
3158 // the caller's fixed stack objects.
3159 MachineFrameInfo *MFI = MF.getFrameInfo();
3160 const MachineRegisterInfo *MRI = &MF.getRegInfo();
3161 const X86InstrInfo *TII =
3162 ((const X86TargetMachine&)getTargetMachine()).getInstrInfo();
3163 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3164 CCValAssign &VA = ArgLocs[i];
3165 SDValue Arg = OutVals[i];
3166 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3167 if (VA.getLocInfo() == CCValAssign::Indirect)
3169 if (!VA.isRegLoc()) {
3170 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
3177 // If the tailcall address may be in a register, then make sure it's
3178 // possible to register allocate for it. In 32-bit, the call address can
3179 // only target EAX, EDX, or ECX since the tail call must be scheduled after
3180 // callee-saved registers are restored. These happen to be the same
3181 // registers used to pass 'inreg' arguments so watch out for those.
3182 if (!Subtarget->is64Bit() &&
3183 ((!isa<GlobalAddressSDNode>(Callee) &&
3184 !isa<ExternalSymbolSDNode>(Callee)) ||
3185 getTargetMachine().getRelocationModel() == Reloc::PIC_)) {
3186 unsigned NumInRegs = 0;
3187 // In PIC we need an extra register to formulate the address computation
3189 unsigned MaxInRegs =
3190 (getTargetMachine().getRelocationModel() == Reloc::PIC_) ? 2 : 3;
3192 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3193 CCValAssign &VA = ArgLocs[i];
3196 unsigned Reg = VA.getLocReg();
3199 case X86::EAX: case X86::EDX: case X86::ECX:
3200 if (++NumInRegs == MaxInRegs)
3212 X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
3213 const TargetLibraryInfo *libInfo) const {
3214 return X86::createFastISel(funcInfo, libInfo);
3217 //===----------------------------------------------------------------------===//
3218 // Other Lowering Hooks
3219 //===----------------------------------------------------------------------===//
3221 static bool MayFoldLoad(SDValue Op) {
3222 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode());
3225 static bool MayFoldIntoStore(SDValue Op) {
3226 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin());
3229 static bool isTargetShuffle(unsigned Opcode) {
3231 default: return false;
3232 case X86ISD::PSHUFD:
3233 case X86ISD::PSHUFHW:
3234 case X86ISD::PSHUFLW:
3236 case X86ISD::PALIGNR:
3237 case X86ISD::MOVLHPS:
3238 case X86ISD::MOVLHPD:
3239 case X86ISD::MOVHLPS:
3240 case X86ISD::MOVLPS:
3241 case X86ISD::MOVLPD:
3242 case X86ISD::MOVSHDUP:
3243 case X86ISD::MOVSLDUP:
3244 case X86ISD::MOVDDUP:
3247 case X86ISD::UNPCKL:
3248 case X86ISD::UNPCKH:
3249 case X86ISD::VPERMILP:
3250 case X86ISD::VPERM2X128:
3251 case X86ISD::VPERMI:
3256 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3257 SDValue V1, SelectionDAG &DAG) {
3259 default: llvm_unreachable("Unknown x86 shuffle node");
3260 case X86ISD::MOVSHDUP:
3261 case X86ISD::MOVSLDUP:
3262 case X86ISD::MOVDDUP:
3263 return DAG.getNode(Opc, dl, VT, V1);
3267 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3268 SDValue V1, unsigned TargetMask,
3269 SelectionDAG &DAG) {
3271 default: llvm_unreachable("Unknown x86 shuffle node");
3272 case X86ISD::PSHUFD:
3273 case X86ISD::PSHUFHW:
3274 case X86ISD::PSHUFLW:
3275 case X86ISD::VPERMILP:
3276 case X86ISD::VPERMI:
3277 return DAG.getNode(Opc, dl, VT, V1, DAG.getConstant(TargetMask, MVT::i8));
3281 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3282 SDValue V1, SDValue V2, unsigned TargetMask,
3283 SelectionDAG &DAG) {
3285 default: llvm_unreachable("Unknown x86 shuffle node");
3286 case X86ISD::PALIGNR:
3288 case X86ISD::VPERM2X128:
3289 return DAG.getNode(Opc, dl, VT, V1, V2,
3290 DAG.getConstant(TargetMask, MVT::i8));
3294 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3295 SDValue V1, SDValue V2, SelectionDAG &DAG) {
3297 default: llvm_unreachable("Unknown x86 shuffle node");
3298 case X86ISD::MOVLHPS:
3299 case X86ISD::MOVLHPD:
3300 case X86ISD::MOVHLPS:
3301 case X86ISD::MOVLPS:
3302 case X86ISD::MOVLPD:
3305 case X86ISD::UNPCKL:
3306 case X86ISD::UNPCKH:
3307 return DAG.getNode(Opc, dl, VT, V1, V2);
3311 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
3312 MachineFunction &MF = DAG.getMachineFunction();
3313 const X86RegisterInfo *RegInfo =
3314 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
3315 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
3316 int ReturnAddrIndex = FuncInfo->getRAIndex();
3318 if (ReturnAddrIndex == 0) {
3319 // Set up a frame object for the return address.
3320 unsigned SlotSize = RegInfo->getSlotSize();
3321 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize,
3324 FuncInfo->setRAIndex(ReturnAddrIndex);
3327 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
3330 bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
3331 bool hasSymbolicDisplacement) {
3332 // Offset should fit into 32 bit immediate field.
3333 if (!isInt<32>(Offset))
3336 // If we don't have a symbolic displacement - we don't have any extra
3338 if (!hasSymbolicDisplacement)
3341 // FIXME: Some tweaks might be needed for medium code model.
3342 if (M != CodeModel::Small && M != CodeModel::Kernel)
3345 // For small code model we assume that latest object is 16MB before end of 31
3346 // bits boundary. We may also accept pretty large negative constants knowing
3347 // that all objects are in the positive half of address space.
3348 if (M == CodeModel::Small && Offset < 16*1024*1024)
3351 // For kernel code model we know that all object resist in the negative half
3352 // of 32bits address space. We may not accept negative offsets, since they may
3353 // be just off and we may accept pretty large positive ones.
3354 if (M == CodeModel::Kernel && Offset > 0)
3360 /// isCalleePop - Determines whether the callee is required to pop its
3361 /// own arguments. Callee pop is necessary to support tail calls.
3362 bool X86::isCalleePop(CallingConv::ID CallingConv,
3363 bool is64Bit, bool IsVarArg, bool TailCallOpt) {
3367 switch (CallingConv) {
3370 case CallingConv::X86_StdCall:
3372 case CallingConv::X86_FastCall:
3374 case CallingConv::X86_ThisCall:
3376 case CallingConv::Fast:
3378 case CallingConv::GHC:
3380 case CallingConv::HiPE:
3385 /// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86
3386 /// specific condition code, returning the condition code and the LHS/RHS of the
3387 /// comparison to make.
3388 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
3389 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
3391 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
3392 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
3393 // X > -1 -> X == 0, jump !sign.
3394 RHS = DAG.getConstant(0, RHS.getValueType());
3395 return X86::COND_NS;
3397 if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
3398 // X < 0 -> X == 0, jump on sign.
3401 if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
3403 RHS = DAG.getConstant(0, RHS.getValueType());
3404 return X86::COND_LE;
3408 switch (SetCCOpcode) {
3409 default: llvm_unreachable("Invalid integer condition!");
3410 case ISD::SETEQ: return X86::COND_E;
3411 case ISD::SETGT: return X86::COND_G;
3412 case ISD::SETGE: return X86::COND_GE;
3413 case ISD::SETLT: return X86::COND_L;
3414 case ISD::SETLE: return X86::COND_LE;
3415 case ISD::SETNE: return X86::COND_NE;
3416 case ISD::SETULT: return X86::COND_B;
3417 case ISD::SETUGT: return X86::COND_A;
3418 case ISD::SETULE: return X86::COND_BE;
3419 case ISD::SETUGE: return X86::COND_AE;
3423 // First determine if it is required or is profitable to flip the operands.
3425 // If LHS is a foldable load, but RHS is not, flip the condition.
3426 if (ISD::isNON_EXTLoad(LHS.getNode()) &&
3427 !ISD::isNON_EXTLoad(RHS.getNode())) {
3428 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
3429 std::swap(LHS, RHS);
3432 switch (SetCCOpcode) {
3438 std::swap(LHS, RHS);
3442 // On a floating point condition, the flags are set as follows:
3444 // 0 | 0 | 0 | X > Y
3445 // 0 | 0 | 1 | X < Y
3446 // 1 | 0 | 0 | X == Y
3447 // 1 | 1 | 1 | unordered
3448 switch (SetCCOpcode) {
3449 default: llvm_unreachable("Condcode should be pre-legalized away");
3451 case ISD::SETEQ: return X86::COND_E;
3452 case ISD::SETOLT: // flipped
3454 case ISD::SETGT: return X86::COND_A;
3455 case ISD::SETOLE: // flipped
3457 case ISD::SETGE: return X86::COND_AE;
3458 case ISD::SETUGT: // flipped
3460 case ISD::SETLT: return X86::COND_B;
3461 case ISD::SETUGE: // flipped
3463 case ISD::SETLE: return X86::COND_BE;
3465 case ISD::SETNE: return X86::COND_NE;
3466 case ISD::SETUO: return X86::COND_P;
3467 case ISD::SETO: return X86::COND_NP;
3469 case ISD::SETUNE: return X86::COND_INVALID;
3473 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
3474 /// code. Current x86 isa includes the following FP cmov instructions:
3475 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
3476 static bool hasFPCMov(unsigned X86CC) {
3492 /// isFPImmLegal - Returns true if the target can instruction select the
3493 /// specified FP immediate natively. If false, the legalizer will
3494 /// materialize the FP immediate as a load from a constant pool.
3495 bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
3496 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
3497 if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
3503 /// isUndefOrInRange - Return true if Val is undef or if its value falls within
3504 /// the specified range (L, H].
3505 static bool isUndefOrInRange(int Val, int Low, int Hi) {
3506 return (Val < 0) || (Val >= Low && Val < Hi);
3509 /// isUndefOrEqual - Val is either less than zero (undef) or equal to the
3510 /// specified value.
3511 static bool isUndefOrEqual(int Val, int CmpVal) {
3512 return (Val < 0 || Val == CmpVal);
3515 /// isSequentialOrUndefInRange - Return true if every element in Mask, beginning
3516 /// from position Pos and ending in Pos+Size, falls within the specified
3517 /// sequential range (L, L+Pos]. or is undef.
3518 static bool isSequentialOrUndefInRange(ArrayRef<int> Mask,
3519 unsigned Pos, unsigned Size, int Low) {
3520 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low)
3521 if (!isUndefOrEqual(Mask[i], Low))
3526 /// isPSHUFDMask - Return true if the node specifies a shuffle of elements that
3527 /// is suitable for input to PSHUFD or PSHUFW. That is, it doesn't reference
3528 /// the second operand.
3529 static bool isPSHUFDMask(ArrayRef<int> Mask, MVT VT) {
3530 if (VT == MVT::v4f32 || VT == MVT::v4i32 )
3531 return (Mask[0] < 4 && Mask[1] < 4 && Mask[2] < 4 && Mask[3] < 4);
3532 if (VT == MVT::v2f64 || VT == MVT::v2i64)
3533 return (Mask[0] < 2 && Mask[1] < 2);
3537 /// isPSHUFHWMask - Return true if the node specifies a shuffle of elements that
3538 /// is suitable for input to PSHUFHW.
3539 static bool isPSHUFHWMask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
3540 if (VT != MVT::v8i16 && (!HasInt256 || VT != MVT::v16i16))
3543 // Lower quadword copied in order or undef.
3544 if (!isSequentialOrUndefInRange(Mask, 0, 4, 0))
3547 // Upper quadword shuffled.
3548 for (unsigned i = 4; i != 8; ++i)
3549 if (!isUndefOrInRange(Mask[i], 4, 8))
3552 if (VT == MVT::v16i16) {
3553 // Lower quadword copied in order or undef.
3554 if (!isSequentialOrUndefInRange(Mask, 8, 4, 8))
3557 // Upper quadword shuffled.
3558 for (unsigned i = 12; i != 16; ++i)
3559 if (!isUndefOrInRange(Mask[i], 12, 16))
3566 /// isPSHUFLWMask - Return true if the node specifies a shuffle of elements that
3567 /// is suitable for input to PSHUFLW.
3568 static bool isPSHUFLWMask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
3569 if (VT != MVT::v8i16 && (!HasInt256 || VT != MVT::v16i16))
3572 // Upper quadword copied in order.
3573 if (!isSequentialOrUndefInRange(Mask, 4, 4, 4))
3576 // Lower quadword shuffled.
3577 for (unsigned i = 0; i != 4; ++i)
3578 if (!isUndefOrInRange(Mask[i], 0, 4))
3581 if (VT == MVT::v16i16) {
3582 // Upper quadword copied in order.
3583 if (!isSequentialOrUndefInRange(Mask, 12, 4, 12))
3586 // Lower quadword shuffled.
3587 for (unsigned i = 8; i != 12; ++i)
3588 if (!isUndefOrInRange(Mask[i], 8, 12))
3595 /// isPALIGNRMask - Return true if the node specifies a shuffle of elements that
3596 /// is suitable for input to PALIGNR.
3597 static bool isPALIGNRMask(ArrayRef<int> Mask, MVT VT,
3598 const X86Subtarget *Subtarget) {
3599 if ((VT.is128BitVector() && !Subtarget->hasSSSE3()) ||
3600 (VT.is256BitVector() && !Subtarget->hasInt256()))
3603 unsigned NumElts = VT.getVectorNumElements();
3604 unsigned NumLanes = VT.is512BitVector() ? 1: VT.getSizeInBits()/128;
3605 unsigned NumLaneElts = NumElts/NumLanes;
3607 // Do not handle 64-bit element shuffles with palignr.
3608 if (NumLaneElts == 2)
3611 for (unsigned l = 0; l != NumElts; l+=NumLaneElts) {
3613 for (i = 0; i != NumLaneElts; ++i) {
3618 // Lane is all undef, go to next lane
3619 if (i == NumLaneElts)
3622 int Start = Mask[i+l];
3624 // Make sure its in this lane in one of the sources
3625 if (!isUndefOrInRange(Start, l, l+NumLaneElts) &&
3626 !isUndefOrInRange(Start, l+NumElts, l+NumElts+NumLaneElts))
3629 // If not lane 0, then we must match lane 0
3630 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Start, Mask[i]+l))
3633 // Correct second source to be contiguous with first source
3634 if (Start >= (int)NumElts)
3635 Start -= NumElts - NumLaneElts;
3637 // Make sure we're shifting in the right direction.
3638 if (Start <= (int)(i+l))
3643 // Check the rest of the elements to see if they are consecutive.
3644 for (++i; i != NumLaneElts; ++i) {
3645 int Idx = Mask[i+l];
3647 // Make sure its in this lane
3648 if (!isUndefOrInRange(Idx, l, l+NumLaneElts) &&
3649 !isUndefOrInRange(Idx, l+NumElts, l+NumElts+NumLaneElts))
3652 // If not lane 0, then we must match lane 0
3653 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Idx, Mask[i]+l))
3656 if (Idx >= (int)NumElts)
3657 Idx -= NumElts - NumLaneElts;
3659 if (!isUndefOrEqual(Idx, Start+i))
3668 /// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming
3669 /// the two vector operands have swapped position.
3670 static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask,
3671 unsigned NumElems) {
3672 for (unsigned i = 0; i != NumElems; ++i) {
3676 else if (idx < (int)NumElems)
3677 Mask[i] = idx + NumElems;
3679 Mask[i] = idx - NumElems;
3683 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
3684 /// specifies a shuffle of elements that is suitable for input to 128/256-bit
3685 /// SHUFPS and SHUFPD. If Commuted is true, then it checks for sources to be
3686 /// reverse of what x86 shuffles want.
3687 static bool isSHUFPMask(ArrayRef<int> Mask, MVT VT, bool Commuted = false) {
3689 unsigned NumElems = VT.getVectorNumElements();
3690 unsigned NumLanes = VT.getSizeInBits()/128;
3691 unsigned NumLaneElems = NumElems/NumLanes;
3693 if (NumLaneElems != 2 && NumLaneElems != 4)
3696 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
3697 bool symetricMaskRequired =
3698 (VT.getSizeInBits() >= 256) && (EltSize == 32);
3700 // VSHUFPSY divides the resulting vector into 4 chunks.
3701 // The sources are also splitted into 4 chunks, and each destination
3702 // chunk must come from a different source chunk.
3704 // SRC1 => X7 X6 X5 X4 X3 X2 X1 X0
3705 // SRC2 => Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y9
3707 // DST => Y7..Y4, Y7..Y4, X7..X4, X7..X4,
3708 // Y3..Y0, Y3..Y0, X3..X0, X3..X0
3710 // VSHUFPDY divides the resulting vector into 4 chunks.
3711 // The sources are also splitted into 4 chunks, and each destination
3712 // chunk must come from a different source chunk.
3714 // SRC1 => X3 X2 X1 X0
3715 // SRC2 => Y3 Y2 Y1 Y0
3717 // DST => Y3..Y2, X3..X2, Y1..Y0, X1..X0
3719 SmallVector<int, 4> MaskVal(NumLaneElems, -1);
3720 unsigned HalfLaneElems = NumLaneElems/2;
3721 for (unsigned l = 0; l != NumElems; l += NumLaneElems) {
3722 for (unsigned i = 0; i != NumLaneElems; ++i) {
3723 int Idx = Mask[i+l];
3724 unsigned RngStart = l + ((Commuted == (i<HalfLaneElems)) ? NumElems : 0);
3725 if (!isUndefOrInRange(Idx, RngStart, RngStart+NumLaneElems))
3727 // For VSHUFPSY, the mask of the second half must be the same as the
3728 // first but with the appropriate offsets. This works in the same way as
3729 // VPERMILPS works with masks.
3730 if (!symetricMaskRequired || Idx < 0)
3732 if (MaskVal[i] < 0) {
3733 MaskVal[i] = Idx - l;
3736 if ((signed)(Idx - l) != MaskVal[i])
3744 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
3745 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
3746 static bool isMOVHLPSMask(ArrayRef<int> Mask, MVT VT) {
3747 if (!VT.is128BitVector())
3750 unsigned NumElems = VT.getVectorNumElements();
3755 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3
3756 return isUndefOrEqual(Mask[0], 6) &&
3757 isUndefOrEqual(Mask[1], 7) &&
3758 isUndefOrEqual(Mask[2], 2) &&
3759 isUndefOrEqual(Mask[3], 3);
3762 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
3763 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
3765 static bool isMOVHLPS_v_undef_Mask(ArrayRef<int> Mask, MVT VT) {
3766 if (!VT.is128BitVector())
3769 unsigned NumElems = VT.getVectorNumElements();
3774 return isUndefOrEqual(Mask[0], 2) &&
3775 isUndefOrEqual(Mask[1], 3) &&
3776 isUndefOrEqual(Mask[2], 2) &&
3777 isUndefOrEqual(Mask[3], 3);
3780 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
3781 /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
3782 static bool isMOVLPMask(ArrayRef<int> Mask, MVT VT) {
3783 if (!VT.is128BitVector())
3786 unsigned NumElems = VT.getVectorNumElements();
3788 if (NumElems != 2 && NumElems != 4)
3791 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
3792 if (!isUndefOrEqual(Mask[i], i + NumElems))
3795 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i)
3796 if (!isUndefOrEqual(Mask[i], i))
3802 /// isMOVLHPSMask - Return true if the specified VECTOR_SHUFFLE operand
3803 /// specifies a shuffle of elements that is suitable for input to MOVLHPS.
3804 static bool isMOVLHPSMask(ArrayRef<int> Mask, MVT VT) {
3805 if (!VT.is128BitVector())
3808 unsigned NumElems = VT.getVectorNumElements();
3810 if (NumElems != 2 && NumElems != 4)
3813 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
3814 if (!isUndefOrEqual(Mask[i], i))
3817 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
3818 if (!isUndefOrEqual(Mask[i + e], i + NumElems))
3825 // Some special combinations that can be optimized.
3828 SDValue Compact8x32ShuffleNode(ShuffleVectorSDNode *SVOp,
3829 SelectionDAG &DAG) {
3830 MVT VT = SVOp->getSimpleValueType(0);
3833 if (VT != MVT::v8i32 && VT != MVT::v8f32)
3836 ArrayRef<int> Mask = SVOp->getMask();
3838 // These are the special masks that may be optimized.
3839 static const int MaskToOptimizeEven[] = {0, 8, 2, 10, 4, 12, 6, 14};
3840 static const int MaskToOptimizeOdd[] = {1, 9, 3, 11, 5, 13, 7, 15};
3841 bool MatchEvenMask = true;
3842 bool MatchOddMask = true;
3843 for (int i=0; i<8; ++i) {
3844 if (!isUndefOrEqual(Mask[i], MaskToOptimizeEven[i]))
3845 MatchEvenMask = false;
3846 if (!isUndefOrEqual(Mask[i], MaskToOptimizeOdd[i]))
3847 MatchOddMask = false;
3850 if (!MatchEvenMask && !MatchOddMask)
3853 SDValue UndefNode = DAG.getNode(ISD::UNDEF, dl, VT);
3855 SDValue Op0 = SVOp->getOperand(0);
3856 SDValue Op1 = SVOp->getOperand(1);
3858 if (MatchEvenMask) {
3859 // Shift the second operand right to 32 bits.
3860 static const int ShiftRightMask[] = {-1, 0, -1, 2, -1, 4, -1, 6 };
3861 Op1 = DAG.getVectorShuffle(VT, dl, Op1, UndefNode, ShiftRightMask);
3863 // Shift the first operand left to 32 bits.
3864 static const int ShiftLeftMask[] = {1, -1, 3, -1, 5, -1, 7, -1 };
3865 Op0 = DAG.getVectorShuffle(VT, dl, Op0, UndefNode, ShiftLeftMask);
3867 static const int BlendMask[] = {0, 9, 2, 11, 4, 13, 6, 15};
3868 return DAG.getVectorShuffle(VT, dl, Op0, Op1, BlendMask);
3871 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
3872 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
3873 static bool isUNPCKLMask(ArrayRef<int> Mask, MVT VT,
3874 bool HasInt256, bool V2IsSplat = false) {
3876 assert(VT.getSizeInBits() >= 128 &&
3877 "Unsupported vector type for unpckl");
3879 // AVX defines UNPCK* to operate independently on 128-bit lanes.
3881 unsigned NumOf256BitLanes;
3882 unsigned NumElts = VT.getVectorNumElements();
3883 if (VT.is256BitVector()) {
3884 if (NumElts != 4 && NumElts != 8 &&
3885 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
3888 NumOf256BitLanes = 1;
3889 } else if (VT.is512BitVector()) {
3890 assert(VT.getScalarType().getSizeInBits() >= 32 &&
3891 "Unsupported vector type for unpckh");
3893 NumOf256BitLanes = 2;
3896 NumOf256BitLanes = 1;
3899 unsigned NumEltsInStride = NumElts/NumOf256BitLanes;
3900 unsigned NumLaneElts = NumEltsInStride/NumLanes;
3902 for (unsigned l256 = 0; l256 < NumOf256BitLanes; l256 += 1) {
3903 for (unsigned l = 0; l != NumEltsInStride; l += NumLaneElts) {
3904 for (unsigned i = 0, j = l; i != NumLaneElts; i += 2, ++j) {
3905 int BitI = Mask[l256*NumEltsInStride+l+i];
3906 int BitI1 = Mask[l256*NumEltsInStride+l+i+1];
3907 if (!isUndefOrEqual(BitI, j+l256*NumElts))
3909 if (V2IsSplat && !isUndefOrEqual(BitI1, NumElts))
3911 if (!isUndefOrEqual(BitI1, j+l256*NumElts+NumEltsInStride))
3919 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
3920 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
3921 static bool isUNPCKHMask(ArrayRef<int> Mask, MVT VT,
3922 bool HasInt256, bool V2IsSplat = false) {
3923 assert(VT.getSizeInBits() >= 128 &&
3924 "Unsupported vector type for unpckh");
3926 // AVX defines UNPCK* to operate independently on 128-bit lanes.
3928 unsigned NumOf256BitLanes;
3929 unsigned NumElts = VT.getVectorNumElements();
3930 if (VT.is256BitVector()) {
3931 if (NumElts != 4 && NumElts != 8 &&
3932 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
3935 NumOf256BitLanes = 1;
3936 } else if (VT.is512BitVector()) {
3937 assert(VT.getScalarType().getSizeInBits() >= 32 &&
3938 "Unsupported vector type for unpckh");
3940 NumOf256BitLanes = 2;
3943 NumOf256BitLanes = 1;
3946 unsigned NumEltsInStride = NumElts/NumOf256BitLanes;
3947 unsigned NumLaneElts = NumEltsInStride/NumLanes;
3949 for (unsigned l256 = 0; l256 < NumOf256BitLanes; l256 += 1) {
3950 for (unsigned l = 0; l != NumEltsInStride; l += NumLaneElts) {
3951 for (unsigned i = 0, j = l+NumLaneElts/2; i != NumLaneElts; i += 2, ++j) {
3952 int BitI = Mask[l256*NumEltsInStride+l+i];
3953 int BitI1 = Mask[l256*NumEltsInStride+l+i+1];
3954 if (!isUndefOrEqual(BitI, j+l256*NumElts))
3956 if (V2IsSplat && !isUndefOrEqual(BitI1, NumElts))
3958 if (!isUndefOrEqual(BitI1, j+l256*NumElts+NumEltsInStride))
3966 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
3967 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
3969 static bool isUNPCKL_v_undef_Mask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
3970 unsigned NumElts = VT.getVectorNumElements();
3971 bool Is256BitVec = VT.is256BitVector();
3973 if (VT.is512BitVector())
3975 assert((VT.is128BitVector() || VT.is256BitVector()) &&
3976 "Unsupported vector type for unpckh");
3978 if (Is256BitVec && NumElts != 4 && NumElts != 8 &&
3979 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
3982 // For 256-bit i64/f64, use MOVDDUPY instead, so reject the matching pattern
3983 // FIXME: Need a better way to get rid of this, there's no latency difference
3984 // between UNPCKLPD and MOVDDUP, the later should always be checked first and
3985 // the former later. We should also remove the "_undef" special mask.
3986 if (NumElts == 4 && Is256BitVec)
3989 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
3990 // independently on 128-bit lanes.
3991 unsigned NumLanes = VT.getSizeInBits()/128;
3992 unsigned NumLaneElts = NumElts/NumLanes;
3994 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
3995 for (unsigned i = 0, j = l; i != NumLaneElts; i += 2, ++j) {
3996 int BitI = Mask[l+i];
3997 int BitI1 = Mask[l+i+1];
3999 if (!isUndefOrEqual(BitI, j))
4001 if (!isUndefOrEqual(BitI1, j))
4009 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
4010 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
4012 static bool isUNPCKH_v_undef_Mask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
4013 unsigned NumElts = VT.getVectorNumElements();
4015 if (VT.is512BitVector())
4018 assert((VT.is128BitVector() || VT.is256BitVector()) &&
4019 "Unsupported vector type for unpckh");
4021 if (VT.is256BitVector() && NumElts != 4 && NumElts != 8 &&
4022 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4025 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
4026 // independently on 128-bit lanes.
4027 unsigned NumLanes = VT.getSizeInBits()/128;
4028 unsigned NumLaneElts = NumElts/NumLanes;
4030 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4031 for (unsigned i = 0, j = l+NumLaneElts/2; i != NumLaneElts; i += 2, ++j) {
4032 int BitI = Mask[l+i];
4033 int BitI1 = Mask[l+i+1];
4034 if (!isUndefOrEqual(BitI, j))
4036 if (!isUndefOrEqual(BitI1, j))
4043 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
4044 /// specifies a shuffle of elements that is suitable for input to MOVSS,
4045 /// MOVSD, and MOVD, i.e. setting the lowest element.
4046 static bool isMOVLMask(ArrayRef<int> Mask, EVT VT) {
4047 if (VT.getVectorElementType().getSizeInBits() < 32)
4049 if (!VT.is128BitVector())
4052 unsigned NumElts = VT.getVectorNumElements();
4054 if (!isUndefOrEqual(Mask[0], NumElts))
4057 for (unsigned i = 1; i != NumElts; ++i)
4058 if (!isUndefOrEqual(Mask[i], i))
4064 /// isVPERM2X128Mask - Match 256-bit shuffles where the elements are considered
4065 /// as permutations between 128-bit chunks or halves. As an example: this
4067 /// vector_shuffle <4, 5, 6, 7, 12, 13, 14, 15>
4068 /// The first half comes from the second half of V1 and the second half from the
4069 /// the second half of V2.
4070 static bool isVPERM2X128Mask(ArrayRef<int> Mask, MVT VT, bool HasFp256) {
4071 if (!HasFp256 || !VT.is256BitVector())
4074 // The shuffle result is divided into half A and half B. In total the two
4075 // sources have 4 halves, namely: C, D, E, F. The final values of A and
4076 // B must come from C, D, E or F.
4077 unsigned HalfSize = VT.getVectorNumElements()/2;
4078 bool MatchA = false, MatchB = false;
4080 // Check if A comes from one of C, D, E, F.
4081 for (unsigned Half = 0; Half != 4; ++Half) {
4082 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, Half*HalfSize)) {
4088 // Check if B comes from one of C, D, E, F.
4089 for (unsigned Half = 0; Half != 4; ++Half) {
4090 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, Half*HalfSize)) {
4096 return MatchA && MatchB;
4099 /// getShuffleVPERM2X128Immediate - Return the appropriate immediate to shuffle
4100 /// the specified VECTOR_MASK mask with VPERM2F128/VPERM2I128 instructions.
4101 static unsigned getShuffleVPERM2X128Immediate(ShuffleVectorSDNode *SVOp) {
4102 MVT VT = SVOp->getSimpleValueType(0);
4104 unsigned HalfSize = VT.getVectorNumElements()/2;
4106 unsigned FstHalf = 0, SndHalf = 0;
4107 for (unsigned i = 0; i < HalfSize; ++i) {
4108 if (SVOp->getMaskElt(i) > 0) {
4109 FstHalf = SVOp->getMaskElt(i)/HalfSize;
4113 for (unsigned i = HalfSize; i < HalfSize*2; ++i) {
4114 if (SVOp->getMaskElt(i) > 0) {
4115 SndHalf = SVOp->getMaskElt(i)/HalfSize;
4120 return (FstHalf | (SndHalf << 4));
4123 // Symetric in-lane mask. Each lane has 4 elements (for imm8)
4124 static bool isPermImmMask(ArrayRef<int> Mask, MVT VT, unsigned& Imm8) {
4125 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4129 unsigned NumElts = VT.getVectorNumElements();
4131 if (VT.is128BitVector() || (VT.is256BitVector() && EltSize == 64)) {
4132 for (unsigned i = 0; i != NumElts; ++i) {
4135 Imm8 |= Mask[i] << (i*2);
4140 unsigned LaneSize = 4;
4141 SmallVector<int, 4> MaskVal(LaneSize, -1);
4143 for (unsigned l = 0; l != NumElts; l += LaneSize) {
4144 for (unsigned i = 0; i != LaneSize; ++i) {
4145 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize))
4149 if (MaskVal[i] < 0) {
4150 MaskVal[i] = Mask[i+l] - l;
4151 Imm8 |= MaskVal[i] << (i*2);
4154 if (Mask[i+l] != (signed)(MaskVal[i]+l))
4161 /// isVPERMILPMask - Return true if the specified VECTOR_SHUFFLE operand
4162 /// specifies a shuffle of elements that is suitable for input to VPERMILPD*.
4163 /// Note that VPERMIL mask matching is different depending whether theunderlying
4164 /// type is 32 or 64. In the VPERMILPS the high half of the mask should point
4165 /// to the same elements of the low, but to the higher half of the source.
4166 /// In VPERMILPD the two lanes could be shuffled independently of each other
4167 /// with the same restriction that lanes can't be crossed. Also handles PSHUFDY.
4168 static bool isVPERMILPMask(ArrayRef<int> Mask, MVT VT) {
4169 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4170 if (VT.getSizeInBits() < 256 || EltSize < 32)
4172 bool symetricMaskRequired = (EltSize == 32);
4173 unsigned NumElts = VT.getVectorNumElements();
4175 unsigned NumLanes = VT.getSizeInBits()/128;
4176 unsigned LaneSize = NumElts/NumLanes;
4177 // 2 or 4 elements in one lane
4179 SmallVector<int, 4> ExpectedMaskVal(LaneSize, -1);
4180 for (unsigned l = 0; l != NumElts; l += LaneSize) {
4181 for (unsigned i = 0; i != LaneSize; ++i) {
4182 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize))
4184 if (symetricMaskRequired) {
4185 if (ExpectedMaskVal[i] < 0 && Mask[i+l] >= 0) {
4186 ExpectedMaskVal[i] = Mask[i+l] - l;
4189 if (!isUndefOrEqual(Mask[i+l], ExpectedMaskVal[i]+l))
4197 /// isCommutedMOVLMask - Returns true if the shuffle mask is except the reverse
4198 /// of what x86 movss want. X86 movs requires the lowest element to be lowest
4199 /// element of vector 2 and the other elements to come from vector 1 in order.
4200 static bool isCommutedMOVLMask(ArrayRef<int> Mask, MVT VT,
4201 bool V2IsSplat = false, bool V2IsUndef = false) {
4202 if (!VT.is128BitVector())
4205 unsigned NumOps = VT.getVectorNumElements();
4206 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16)
4209 if (!isUndefOrEqual(Mask[0], 0))
4212 for (unsigned i = 1; i != NumOps; ++i)
4213 if (!(isUndefOrEqual(Mask[i], i+NumOps) ||
4214 (V2IsUndef && isUndefOrInRange(Mask[i], NumOps, NumOps*2)) ||
4215 (V2IsSplat && isUndefOrEqual(Mask[i], NumOps))))
4221 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4222 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
4223 /// Masks to match: <1, 1, 3, 3> or <1, 1, 3, 3, 5, 5, 7, 7>
4224 static bool isMOVSHDUPMask(ArrayRef<int> Mask, MVT VT,
4225 const X86Subtarget *Subtarget) {
4226 if (!Subtarget->hasSSE3())
4229 unsigned NumElems = VT.getVectorNumElements();
4231 if ((VT.is128BitVector() && NumElems != 4) ||
4232 (VT.is256BitVector() && NumElems != 8) ||
4233 (VT.is512BitVector() && NumElems != 16))
4236 // "i+1" is the value the indexed mask element must have
4237 for (unsigned i = 0; i != NumElems; i += 2)
4238 if (!isUndefOrEqual(Mask[i], i+1) ||
4239 !isUndefOrEqual(Mask[i+1], i+1))
4245 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4246 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
4247 /// Masks to match: <0, 0, 2, 2> or <0, 0, 2, 2, 4, 4, 6, 6>
4248 static bool isMOVSLDUPMask(ArrayRef<int> Mask, MVT VT,
4249 const X86Subtarget *Subtarget) {
4250 if (!Subtarget->hasSSE3())
4253 unsigned NumElems = VT.getVectorNumElements();
4255 if ((VT.is128BitVector() && NumElems != 4) ||
4256 (VT.is256BitVector() && NumElems != 8) ||
4257 (VT.is512BitVector() && NumElems != 16))
4260 // "i" is the value the indexed mask element must have
4261 for (unsigned i = 0; i != NumElems; i += 2)
4262 if (!isUndefOrEqual(Mask[i], i) ||
4263 !isUndefOrEqual(Mask[i+1], i))
4269 /// isMOVDDUPYMask - Return true if the specified VECTOR_SHUFFLE operand
4270 /// specifies a shuffle of elements that is suitable for input to 256-bit
4271 /// version of MOVDDUP.
4272 static bool isMOVDDUPYMask(ArrayRef<int> Mask, MVT VT, bool HasFp256) {
4273 if (!HasFp256 || !VT.is256BitVector())
4276 unsigned NumElts = VT.getVectorNumElements();
4280 for (unsigned i = 0; i != NumElts/2; ++i)
4281 if (!isUndefOrEqual(Mask[i], 0))
4283 for (unsigned i = NumElts/2; i != NumElts; ++i)
4284 if (!isUndefOrEqual(Mask[i], NumElts/2))
4289 /// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4290 /// specifies a shuffle of elements that is suitable for input to 128-bit
4291 /// version of MOVDDUP.
4292 static bool isMOVDDUPMask(ArrayRef<int> Mask, MVT VT) {
4293 if (!VT.is128BitVector())
4296 unsigned e = VT.getVectorNumElements() / 2;
4297 for (unsigned i = 0; i != e; ++i)
4298 if (!isUndefOrEqual(Mask[i], i))
4300 for (unsigned i = 0; i != e; ++i)
4301 if (!isUndefOrEqual(Mask[e+i], i))
4306 /// isVEXTRACTIndex - Return true if the specified
4307 /// EXTRACT_SUBVECTOR operand specifies a vector extract that is
4308 /// suitable for instruction that extract 128 or 256 bit vectors
4309 static bool isVEXTRACTIndex(SDNode *N, unsigned vecWidth) {
4310 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4311 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4314 // The index should be aligned on a vecWidth-bit boundary.
4316 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4318 MVT VT = N->getSimpleValueType(0);
4319 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4320 bool Result = (Index * ElSize) % vecWidth == 0;
4325 /// isVINSERTIndex - Return true if the specified INSERT_SUBVECTOR
4326 /// operand specifies a subvector insert that is suitable for input to
4327 /// insertion of 128 or 256-bit subvectors
4328 static bool isVINSERTIndex(SDNode *N, unsigned vecWidth) {
4329 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4330 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4332 // The index should be aligned on a vecWidth-bit boundary.
4334 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4336 MVT VT = N->getSimpleValueType(0);
4337 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4338 bool Result = (Index * ElSize) % vecWidth == 0;
4343 bool X86::isVINSERT128Index(SDNode *N) {
4344 return isVINSERTIndex(N, 128);
4347 bool X86::isVINSERT256Index(SDNode *N) {
4348 return isVINSERTIndex(N, 256);
4351 bool X86::isVEXTRACT128Index(SDNode *N) {
4352 return isVEXTRACTIndex(N, 128);
4355 bool X86::isVEXTRACT256Index(SDNode *N) {
4356 return isVEXTRACTIndex(N, 256);
4359 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
4360 /// the specified VECTOR_SHUFFLE mask with PSHUF* and SHUFP* instructions.
4361 /// Handles 128-bit and 256-bit.
4362 static unsigned getShuffleSHUFImmediate(ShuffleVectorSDNode *N) {
4363 MVT VT = N->getSimpleValueType(0);
4365 assert((VT.getSizeInBits() >= 128) &&
4366 "Unsupported vector type for PSHUF/SHUFP");
4368 // Handle 128 and 256-bit vector lengths. AVX defines PSHUF/SHUFP to operate
4369 // independently on 128-bit lanes.
4370 unsigned NumElts = VT.getVectorNumElements();
4371 unsigned NumLanes = VT.getSizeInBits()/128;
4372 unsigned NumLaneElts = NumElts/NumLanes;
4374 assert((NumLaneElts == 2 || NumLaneElts == 4 || NumLaneElts == 8) &&
4375 "Only supports 2, 4 or 8 elements per lane");
4377 unsigned Shift = (NumLaneElts >= 4) ? 1 : 0;
4379 for (unsigned i = 0; i != NumElts; ++i) {
4380 int Elt = N->getMaskElt(i);
4381 if (Elt < 0) continue;
4382 Elt &= NumLaneElts - 1;
4383 unsigned ShAmt = (i << Shift) % 8;
4384 Mask |= Elt << ShAmt;
4390 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
4391 /// the specified VECTOR_SHUFFLE mask with the PSHUFHW instruction.
4392 static unsigned getShufflePSHUFHWImmediate(ShuffleVectorSDNode *N) {
4393 MVT VT = N->getSimpleValueType(0);
4395 assert((VT == MVT::v8i16 || VT == MVT::v16i16) &&
4396 "Unsupported vector type for PSHUFHW");
4398 unsigned NumElts = VT.getVectorNumElements();
4401 for (unsigned l = 0; l != NumElts; l += 8) {
4402 // 8 nodes per lane, but we only care about the last 4.
4403 for (unsigned i = 0; i < 4; ++i) {
4404 int Elt = N->getMaskElt(l+i+4);
4405 if (Elt < 0) continue;
4406 Elt &= 0x3; // only 2-bits.
4407 Mask |= Elt << (i * 2);
4414 /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
4415 /// the specified VECTOR_SHUFFLE mask with the PSHUFLW instruction.
4416 static unsigned getShufflePSHUFLWImmediate(ShuffleVectorSDNode *N) {
4417 MVT VT = N->getSimpleValueType(0);
4419 assert((VT == MVT::v8i16 || VT == MVT::v16i16) &&
4420 "Unsupported vector type for PSHUFHW");
4422 unsigned NumElts = VT.getVectorNumElements();
4425 for (unsigned l = 0; l != NumElts; l += 8) {
4426 // 8 nodes per lane, but we only care about the first 4.
4427 for (unsigned i = 0; i < 4; ++i) {
4428 int Elt = N->getMaskElt(l+i);
4429 if (Elt < 0) continue;
4430 Elt &= 0x3; // only 2-bits
4431 Mask |= Elt << (i * 2);
4438 /// getShufflePALIGNRImmediate - Return the appropriate immediate to shuffle
4439 /// the specified VECTOR_SHUFFLE mask with the PALIGNR instruction.
4440 static unsigned getShufflePALIGNRImmediate(ShuffleVectorSDNode *SVOp) {
4441 MVT VT = SVOp->getSimpleValueType(0);
4442 unsigned EltSize = VT.is512BitVector() ? 1 :
4443 VT.getVectorElementType().getSizeInBits() >> 3;
4445 unsigned NumElts = VT.getVectorNumElements();
4446 unsigned NumLanes = VT.is512BitVector() ? 1 : VT.getSizeInBits()/128;
4447 unsigned NumLaneElts = NumElts/NumLanes;
4451 for (i = 0; i != NumElts; ++i) {
4452 Val = SVOp->getMaskElt(i);
4456 if (Val >= (int)NumElts)
4457 Val -= NumElts - NumLaneElts;
4459 assert(Val - i > 0 && "PALIGNR imm should be positive");
4460 return (Val - i) * EltSize;
4463 static unsigned getExtractVEXTRACTImmediate(SDNode *N, unsigned vecWidth) {
4464 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4465 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4466 llvm_unreachable("Illegal extract subvector for VEXTRACT");
4469 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4471 MVT VecVT = N->getOperand(0).getSimpleValueType();
4472 MVT ElVT = VecVT.getVectorElementType();
4474 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4475 return Index / NumElemsPerChunk;
4478 static unsigned getInsertVINSERTImmediate(SDNode *N, unsigned vecWidth) {
4479 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4480 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4481 llvm_unreachable("Illegal insert subvector for VINSERT");
4484 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4486 MVT VecVT = N->getSimpleValueType(0);
4487 MVT ElVT = VecVT.getVectorElementType();
4489 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4490 return Index / NumElemsPerChunk;
4493 /// getExtractVEXTRACT128Immediate - Return the appropriate immediate
4494 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF128
4495 /// and VINSERTI128 instructions.
4496 unsigned X86::getExtractVEXTRACT128Immediate(SDNode *N) {
4497 return getExtractVEXTRACTImmediate(N, 128);
4500 /// getExtractVEXTRACT256Immediate - Return the appropriate immediate
4501 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF64x4
4502 /// and VINSERTI64x4 instructions.
4503 unsigned X86::getExtractVEXTRACT256Immediate(SDNode *N) {
4504 return getExtractVEXTRACTImmediate(N, 256);
4507 /// getInsertVINSERT128Immediate - Return the appropriate immediate
4508 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF128
4509 /// and VINSERTI128 instructions.
4510 unsigned X86::getInsertVINSERT128Immediate(SDNode *N) {
4511 return getInsertVINSERTImmediate(N, 128);
4514 /// getInsertVINSERT256Immediate - Return the appropriate immediate
4515 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF46x4
4516 /// and VINSERTI64x4 instructions.
4517 unsigned X86::getInsertVINSERT256Immediate(SDNode *N) {
4518 return getInsertVINSERTImmediate(N, 256);
4521 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
4523 bool X86::isZeroNode(SDValue Elt) {
4524 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Elt))
4525 return CN->isNullValue();
4526 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Elt))
4527 return CFP->getValueAPF().isPosZero();
4531 /// CommuteVectorShuffle - Swap vector_shuffle operands as well as values in
4532 /// their permute mask.
4533 static SDValue CommuteVectorShuffle(ShuffleVectorSDNode *SVOp,
4534 SelectionDAG &DAG) {
4535 MVT VT = SVOp->getSimpleValueType(0);
4536 unsigned NumElems = VT.getVectorNumElements();
4537 SmallVector<int, 8> MaskVec;
4539 for (unsigned i = 0; i != NumElems; ++i) {
4540 int Idx = SVOp->getMaskElt(i);
4542 if (Idx < (int)NumElems)
4547 MaskVec.push_back(Idx);
4549 return DAG.getVectorShuffle(VT, SDLoc(SVOp), SVOp->getOperand(1),
4550 SVOp->getOperand(0), &MaskVec[0]);
4553 /// ShouldXformToMOVHLPS - Return true if the node should be transformed to
4554 /// match movhlps. The lower half elements should come from upper half of
4555 /// V1 (and in order), and the upper half elements should come from the upper
4556 /// half of V2 (and in order).
4557 static bool ShouldXformToMOVHLPS(ArrayRef<int> Mask, MVT VT) {
4558 if (!VT.is128BitVector())
4560 if (VT.getVectorNumElements() != 4)
4562 for (unsigned i = 0, e = 2; i != e; ++i)
4563 if (!isUndefOrEqual(Mask[i], i+2))
4565 for (unsigned i = 2; i != 4; ++i)
4566 if (!isUndefOrEqual(Mask[i], i+4))
4571 /// isScalarLoadToVector - Returns true if the node is a scalar load that
4572 /// is promoted to a vector. It also returns the LoadSDNode by reference if
4574 static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = NULL) {
4575 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR)
4577 N = N->getOperand(0).getNode();
4578 if (!ISD::isNON_EXTLoad(N))
4581 *LD = cast<LoadSDNode>(N);
4585 // Test whether the given value is a vector value which will be legalized
4587 static bool WillBeConstantPoolLoad(SDNode *N) {
4588 if (N->getOpcode() != ISD::BUILD_VECTOR)
4591 // Check for any non-constant elements.
4592 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
4593 switch (N->getOperand(i).getNode()->getOpcode()) {
4595 case ISD::ConstantFP:
4602 // Vectors of all-zeros and all-ones are materialized with special
4603 // instructions rather than being loaded.
4604 return !ISD::isBuildVectorAllZeros(N) &&
4605 !ISD::isBuildVectorAllOnes(N);
4608 /// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to
4609 /// match movlp{s|d}. The lower half elements should come from lower half of
4610 /// V1 (and in order), and the upper half elements should come from the upper
4611 /// half of V2 (and in order). And since V1 will become the source of the
4612 /// MOVLP, it must be either a vector load or a scalar load to vector.
4613 static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2,
4614 ArrayRef<int> Mask, MVT VT) {
4615 if (!VT.is128BitVector())
4618 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1))
4620 // Is V2 is a vector load, don't do this transformation. We will try to use
4621 // load folding shufps op.
4622 if (ISD::isNON_EXTLoad(V2) || WillBeConstantPoolLoad(V2))
4625 unsigned NumElems = VT.getVectorNumElements();
4627 if (NumElems != 2 && NumElems != 4)
4629 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4630 if (!isUndefOrEqual(Mask[i], i))
4632 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i)
4633 if (!isUndefOrEqual(Mask[i], i+NumElems))
4638 /// isSplatVector - Returns true if N is a BUILD_VECTOR node whose elements are
4640 static bool isSplatVector(SDNode *N) {
4641 if (N->getOpcode() != ISD::BUILD_VECTOR)
4644 SDValue SplatValue = N->getOperand(0);
4645 for (unsigned i = 1, e = N->getNumOperands(); i != e; ++i)
4646 if (N->getOperand(i) != SplatValue)
4651 /// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
4652 /// to an zero vector.
4653 /// FIXME: move to dag combiner / method on ShuffleVectorSDNode
4654 static bool isZeroShuffle(ShuffleVectorSDNode *N) {
4655 SDValue V1 = N->getOperand(0);
4656 SDValue V2 = N->getOperand(1);
4657 unsigned NumElems = N->getValueType(0).getVectorNumElements();
4658 for (unsigned i = 0; i != NumElems; ++i) {
4659 int Idx = N->getMaskElt(i);
4660 if (Idx >= (int)NumElems) {
4661 unsigned Opc = V2.getOpcode();
4662 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode()))
4664 if (Opc != ISD::BUILD_VECTOR ||
4665 !X86::isZeroNode(V2.getOperand(Idx-NumElems)))
4667 } else if (Idx >= 0) {
4668 unsigned Opc = V1.getOpcode();
4669 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode()))
4671 if (Opc != ISD::BUILD_VECTOR ||
4672 !X86::isZeroNode(V1.getOperand(Idx)))
4679 /// getZeroVector - Returns a vector of specified type with all zero elements.
4681 static SDValue getZeroVector(EVT VT, const X86Subtarget *Subtarget,
4682 SelectionDAG &DAG, SDLoc dl) {
4683 assert(VT.isVector() && "Expected a vector type");
4685 // Always build SSE zero vectors as <4 x i32> bitcasted
4686 // to their dest type. This ensures they get CSE'd.
4688 if (VT.is128BitVector()) { // SSE
4689 if (Subtarget->hasSSE2()) { // SSE2
4690 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
4691 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4693 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
4694 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
4696 } else if (VT.is256BitVector()) { // AVX
4697 if (Subtarget->hasInt256()) { // AVX2
4698 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
4699 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4700 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops,
4701 array_lengthof(Ops));
4703 // 256-bit logic and arithmetic instructions in AVX are all
4704 // floating-point, no support for integer ops. Emit fp zeroed vectors.
4705 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
4706 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4707 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops,
4708 array_lengthof(Ops));
4710 } else if (VT.is512BitVector()) { // AVX-512
4711 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
4712 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst,
4713 Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4714 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i32, Ops, 16);
4716 llvm_unreachable("Unexpected vector type");
4718 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
4721 /// getOnesVector - Returns a vector of specified type with all bits set.
4722 /// Always build ones vectors as <4 x i32> or <8 x i32>. For 256-bit types with
4723 /// no AVX2 supprt, use two <4 x i32> inserted in a <8 x i32> appropriately.
4724 /// Then bitcast to their original type, ensuring they get CSE'd.
4725 static SDValue getOnesVector(MVT VT, bool HasInt256, SelectionDAG &DAG,
4727 assert(VT.isVector() && "Expected a vector type");
4729 SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32);
4731 if (VT.is256BitVector()) {
4732 if (HasInt256) { // AVX2
4733 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4734 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops,
4735 array_lengthof(Ops));
4737 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4738 Vec = Concat128BitVectors(Vec, Vec, MVT::v8i32, 8, DAG, dl);
4740 } else if (VT.is128BitVector()) {
4741 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4743 llvm_unreachable("Unexpected vector type");
4745 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
4748 /// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements
4749 /// that point to V2 points to its first element.
4750 static void NormalizeMask(SmallVectorImpl<int> &Mask, unsigned NumElems) {
4751 for (unsigned i = 0; i != NumElems; ++i) {
4752 if (Mask[i] > (int)NumElems) {
4758 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
4759 /// operation of specified width.
4760 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
4762 unsigned NumElems = VT.getVectorNumElements();
4763 SmallVector<int, 8> Mask;
4764 Mask.push_back(NumElems);
4765 for (unsigned i = 1; i != NumElems; ++i)
4767 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4770 /// getUnpackl - Returns a vector_shuffle node for an unpackl operation.
4771 static SDValue getUnpackl(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
4773 unsigned NumElems = VT.getVectorNumElements();
4774 SmallVector<int, 8> Mask;
4775 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
4777 Mask.push_back(i + NumElems);
4779 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4782 /// getUnpackh - Returns a vector_shuffle node for an unpackh operation.
4783 static SDValue getUnpackh(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
4785 unsigned NumElems = VT.getVectorNumElements();
4786 SmallVector<int, 8> Mask;
4787 for (unsigned i = 0, Half = NumElems/2; i != Half; ++i) {
4788 Mask.push_back(i + Half);
4789 Mask.push_back(i + NumElems + Half);
4791 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4794 // PromoteSplati8i16 - All i16 and i8 vector types can't be used directly by
4795 // a generic shuffle instruction because the target has no such instructions.
4796 // Generate shuffles which repeat i16 and i8 several times until they can be
4797 // represented by v4f32 and then be manipulated by target suported shuffles.
4798 static SDValue PromoteSplati8i16(SDValue V, SelectionDAG &DAG, int &EltNo) {
4799 MVT VT = V.getSimpleValueType();
4800 int NumElems = VT.getVectorNumElements();
4803 while (NumElems > 4) {
4804 if (EltNo < NumElems/2) {
4805 V = getUnpackl(DAG, dl, VT, V, V);
4807 V = getUnpackh(DAG, dl, VT, V, V);
4808 EltNo -= NumElems/2;
4815 /// getLegalSplat - Generate a legal splat with supported x86 shuffles
4816 static SDValue getLegalSplat(SelectionDAG &DAG, SDValue V, int EltNo) {
4817 MVT VT = V.getSimpleValueType();
4820 if (VT.is128BitVector()) {
4821 V = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V);
4822 int SplatMask[4] = { EltNo, EltNo, EltNo, EltNo };
4823 V = DAG.getVectorShuffle(MVT::v4f32, dl, V, DAG.getUNDEF(MVT::v4f32),
4825 } else if (VT.is256BitVector()) {
4826 // To use VPERMILPS to splat scalars, the second half of indicies must
4827 // refer to the higher part, which is a duplication of the lower one,
4828 // because VPERMILPS can only handle in-lane permutations.
4829 int SplatMask[8] = { EltNo, EltNo, EltNo, EltNo,
4830 EltNo+4, EltNo+4, EltNo+4, EltNo+4 };
4832 V = DAG.getNode(ISD::BITCAST, dl, MVT::v8f32, V);
4833 V = DAG.getVectorShuffle(MVT::v8f32, dl, V, DAG.getUNDEF(MVT::v8f32),
4836 llvm_unreachable("Vector size not supported");
4838 return DAG.getNode(ISD::BITCAST, dl, VT, V);
4841 /// PromoteSplat - Splat is promoted to target supported vector shuffles.
4842 static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG) {
4843 MVT SrcVT = SV->getSimpleValueType(0);
4844 SDValue V1 = SV->getOperand(0);
4847 int EltNo = SV->getSplatIndex();
4848 int NumElems = SrcVT.getVectorNumElements();
4849 bool Is256BitVec = SrcVT.is256BitVector();
4851 assert(((SrcVT.is128BitVector() && NumElems > 4) || Is256BitVec) &&
4852 "Unknown how to promote splat for type");
4854 // Extract the 128-bit part containing the splat element and update
4855 // the splat element index when it refers to the higher register.
4857 V1 = Extract128BitVector(V1, EltNo, DAG, dl);
4858 if (EltNo >= NumElems/2)
4859 EltNo -= NumElems/2;
4862 // All i16 and i8 vector types can't be used directly by a generic shuffle
4863 // instruction because the target has no such instruction. Generate shuffles
4864 // which repeat i16 and i8 several times until they fit in i32, and then can
4865 // be manipulated by target suported shuffles.
4866 MVT EltVT = SrcVT.getVectorElementType();
4867 if (EltVT == MVT::i8 || EltVT == MVT::i16)
4868 V1 = PromoteSplati8i16(V1, DAG, EltNo);
4870 // Recreate the 256-bit vector and place the same 128-bit vector
4871 // into the low and high part. This is necessary because we want
4872 // to use VPERM* to shuffle the vectors
4874 V1 = DAG.getNode(ISD::CONCAT_VECTORS, dl, SrcVT, V1, V1);
4877 return getLegalSplat(DAG, V1, EltNo);
4880 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
4881 /// vector of zero or undef vector. This produces a shuffle where the low
4882 /// element of V2 is swizzled into the zero/undef vector, landing at element
4883 /// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
4884 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
4886 const X86Subtarget *Subtarget,
4887 SelectionDAG &DAG) {
4888 MVT VT = V2.getSimpleValueType();
4890 ? getZeroVector(VT, Subtarget, DAG, SDLoc(V2)) : DAG.getUNDEF(VT);
4891 unsigned NumElems = VT.getVectorNumElements();
4892 SmallVector<int, 16> MaskVec;
4893 for (unsigned i = 0; i != NumElems; ++i)
4894 // If this is the insertion idx, put the low elt of V2 here.
4895 MaskVec.push_back(i == Idx ? NumElems : i);
4896 return DAG.getVectorShuffle(VT, SDLoc(V2), V1, V2, &MaskVec[0]);
4899 /// getTargetShuffleMask - Calculates the shuffle mask corresponding to the
4900 /// target specific opcode. Returns true if the Mask could be calculated.
4901 /// Sets IsUnary to true if only uses one source.
4902 static bool getTargetShuffleMask(SDNode *N, MVT VT,
4903 SmallVectorImpl<int> &Mask, bool &IsUnary) {
4904 unsigned NumElems = VT.getVectorNumElements();
4908 switch(N->getOpcode()) {
4910 ImmN = N->getOperand(N->getNumOperands()-1);
4911 DecodeSHUFPMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4913 case X86ISD::UNPCKH:
4914 DecodeUNPCKHMask(VT, Mask);
4916 case X86ISD::UNPCKL:
4917 DecodeUNPCKLMask(VT, Mask);
4919 case X86ISD::MOVHLPS:
4920 DecodeMOVHLPSMask(NumElems, Mask);
4922 case X86ISD::MOVLHPS:
4923 DecodeMOVLHPSMask(NumElems, Mask);
4925 case X86ISD::PALIGNR:
4926 ImmN = N->getOperand(N->getNumOperands()-1);
4927 DecodePALIGNRMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4929 case X86ISD::PSHUFD:
4930 case X86ISD::VPERMILP:
4931 ImmN = N->getOperand(N->getNumOperands()-1);
4932 DecodePSHUFMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4935 case X86ISD::PSHUFHW:
4936 ImmN = N->getOperand(N->getNumOperands()-1);
4937 DecodePSHUFHWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4940 case X86ISD::PSHUFLW:
4941 ImmN = N->getOperand(N->getNumOperands()-1);
4942 DecodePSHUFLWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4945 case X86ISD::VPERMI:
4946 ImmN = N->getOperand(N->getNumOperands()-1);
4947 DecodeVPERMMask(cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4951 case X86ISD::MOVSD: {
4952 // The index 0 always comes from the first element of the second source,
4953 // this is why MOVSS and MOVSD are used in the first place. The other
4954 // elements come from the other positions of the first source vector
4955 Mask.push_back(NumElems);
4956 for (unsigned i = 1; i != NumElems; ++i) {
4961 case X86ISD::VPERM2X128:
4962 ImmN = N->getOperand(N->getNumOperands()-1);
4963 DecodeVPERM2X128Mask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4964 if (Mask.empty()) return false;
4966 case X86ISD::MOVDDUP:
4967 case X86ISD::MOVLHPD:
4968 case X86ISD::MOVLPD:
4969 case X86ISD::MOVLPS:
4970 case X86ISD::MOVSHDUP:
4971 case X86ISD::MOVSLDUP:
4972 // Not yet implemented
4974 default: llvm_unreachable("unknown target shuffle node");
4980 /// getShuffleScalarElt - Returns the scalar element that will make up the ith
4981 /// element of the result of the vector shuffle.
4982 static SDValue getShuffleScalarElt(SDNode *N, unsigned Index, SelectionDAG &DAG,
4985 return SDValue(); // Limit search depth.
4987 SDValue V = SDValue(N, 0);
4988 EVT VT = V.getValueType();
4989 unsigned Opcode = V.getOpcode();
4991 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars.
4992 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) {
4993 int Elt = SV->getMaskElt(Index);
4996 return DAG.getUNDEF(VT.getVectorElementType());
4998 unsigned NumElems = VT.getVectorNumElements();
4999 SDValue NewV = (Elt < (int)NumElems) ? SV->getOperand(0)
5000 : SV->getOperand(1);
5001 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG, Depth+1);
5004 // Recurse into target specific vector shuffles to find scalars.
5005 if (isTargetShuffle(Opcode)) {
5006 MVT ShufVT = V.getSimpleValueType();
5007 unsigned NumElems = ShufVT.getVectorNumElements();
5008 SmallVector<int, 16> ShuffleMask;
5011 if (!getTargetShuffleMask(N, ShufVT, ShuffleMask, IsUnary))
5014 int Elt = ShuffleMask[Index];
5016 return DAG.getUNDEF(ShufVT.getVectorElementType());
5018 SDValue NewV = (Elt < (int)NumElems) ? N->getOperand(0)
5020 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG,
5024 // Actual nodes that may contain scalar elements
5025 if (Opcode == ISD::BITCAST) {
5026 V = V.getOperand(0);
5027 EVT SrcVT = V.getValueType();
5028 unsigned NumElems = VT.getVectorNumElements();
5030 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems)
5034 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR)
5035 return (Index == 0) ? V.getOperand(0)
5036 : DAG.getUNDEF(VT.getVectorElementType());
5038 if (V.getOpcode() == ISD::BUILD_VECTOR)
5039 return V.getOperand(Index);
5044 /// getNumOfConsecutiveZeros - Return the number of elements of a vector
5045 /// shuffle operation which come from a consecutively from a zero. The
5046 /// search can start in two different directions, from left or right.
5047 /// We count undefs as zeros until PreferredNum is reached.
5048 static unsigned getNumOfConsecutiveZeros(ShuffleVectorSDNode *SVOp,
5049 unsigned NumElems, bool ZerosFromLeft,
5051 unsigned PreferredNum = -1U) {
5052 unsigned NumZeros = 0;
5053 for (unsigned i = 0; i != NumElems; ++i) {
5054 unsigned Index = ZerosFromLeft ? i : NumElems - i - 1;
5055 SDValue Elt = getShuffleScalarElt(SVOp, Index, DAG, 0);
5059 if (X86::isZeroNode(Elt))
5061 else if (Elt.getOpcode() == ISD::UNDEF) // Undef as zero up to PreferredNum.
5062 NumZeros = std::min(NumZeros + 1, PreferredNum);
5070 /// isShuffleMaskConsecutive - Check if the shuffle mask indicies [MaskI, MaskE)
5071 /// correspond consecutively to elements from one of the vector operands,
5072 /// starting from its index OpIdx. Also tell OpNum which source vector operand.
5074 bool isShuffleMaskConsecutive(ShuffleVectorSDNode *SVOp,
5075 unsigned MaskI, unsigned MaskE, unsigned OpIdx,
5076 unsigned NumElems, unsigned &OpNum) {
5077 bool SeenV1 = false;
5078 bool SeenV2 = false;
5080 for (unsigned i = MaskI; i != MaskE; ++i, ++OpIdx) {
5081 int Idx = SVOp->getMaskElt(i);
5082 // Ignore undef indicies
5086 if (Idx < (int)NumElems)
5091 // Only accept consecutive elements from the same vector
5092 if ((Idx % NumElems != OpIdx) || (SeenV1 && SeenV2))
5096 OpNum = SeenV1 ? 0 : 1;
5100 /// isVectorShiftRight - Returns true if the shuffle can be implemented as a
5101 /// logical left shift of a vector.
5102 static bool isVectorShiftRight(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5103 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5105 SVOp->getSimpleValueType(0).getVectorNumElements();
5106 unsigned NumZeros = getNumOfConsecutiveZeros(
5107 SVOp, NumElems, false /* check zeros from right */, DAG,
5108 SVOp->getMaskElt(0));
5114 // Considering the elements in the mask that are not consecutive zeros,
5115 // check if they consecutively come from only one of the source vectors.
5117 // V1 = {X, A, B, C} 0
5119 // vector_shuffle V1, V2 <1, 2, 3, X>
5121 if (!isShuffleMaskConsecutive(SVOp,
5122 0, // Mask Start Index
5123 NumElems-NumZeros, // Mask End Index(exclusive)
5124 NumZeros, // Where to start looking in the src vector
5125 NumElems, // Number of elements in vector
5126 OpSrc)) // Which source operand ?
5131 ShVal = SVOp->getOperand(OpSrc);
5135 /// isVectorShiftLeft - Returns true if the shuffle can be implemented as a
5136 /// logical left shift of a vector.
5137 static bool isVectorShiftLeft(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5138 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5140 SVOp->getSimpleValueType(0).getVectorNumElements();
5141 unsigned NumZeros = getNumOfConsecutiveZeros(
5142 SVOp, NumElems, true /* check zeros from left */, DAG,
5143 NumElems - SVOp->getMaskElt(NumElems - 1) - 1);
5149 // Considering the elements in the mask that are not consecutive zeros,
5150 // check if they consecutively come from only one of the source vectors.
5152 // 0 { A, B, X, X } = V2
5154 // vector_shuffle V1, V2 <X, X, 4, 5>
5156 if (!isShuffleMaskConsecutive(SVOp,
5157 NumZeros, // Mask Start Index
5158 NumElems, // Mask End Index(exclusive)
5159 0, // Where to start looking in the src vector
5160 NumElems, // Number of elements in vector
5161 OpSrc)) // Which source operand ?
5166 ShVal = SVOp->getOperand(OpSrc);
5170 /// isVectorShift - Returns true if the shuffle can be implemented as a
5171 /// logical left or right shift of a vector.
5172 static bool isVectorShift(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5173 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5174 // Although the logic below support any bitwidth size, there are no
5175 // shift instructions which handle more than 128-bit vectors.
5176 if (!SVOp->getSimpleValueType(0).is128BitVector())
5179 if (isVectorShiftLeft(SVOp, DAG, isLeft, ShVal, ShAmt) ||
5180 isVectorShiftRight(SVOp, DAG, isLeft, ShVal, ShAmt))
5186 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
5188 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
5189 unsigned NumNonZero, unsigned NumZero,
5191 const X86Subtarget* Subtarget,
5192 const TargetLowering &TLI) {
5199 for (unsigned i = 0; i < 16; ++i) {
5200 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
5201 if (ThisIsNonZero && First) {
5203 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
5205 V = DAG.getUNDEF(MVT::v8i16);
5210 SDValue ThisElt(0, 0), LastElt(0, 0);
5211 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
5212 if (LastIsNonZero) {
5213 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
5214 MVT::i16, Op.getOperand(i-1));
5216 if (ThisIsNonZero) {
5217 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
5218 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
5219 ThisElt, DAG.getConstant(8, MVT::i8));
5221 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
5225 if (ThisElt.getNode())
5226 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
5227 DAG.getIntPtrConstant(i/2));
5231 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V);
5234 /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
5236 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
5237 unsigned NumNonZero, unsigned NumZero,
5239 const X86Subtarget* Subtarget,
5240 const TargetLowering &TLI) {
5247 for (unsigned i = 0; i < 8; ++i) {
5248 bool isNonZero = (NonZeros & (1 << i)) != 0;
5252 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
5254 V = DAG.getUNDEF(MVT::v8i16);
5257 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
5258 MVT::v8i16, V, Op.getOperand(i),
5259 DAG.getIntPtrConstant(i));
5266 /// getVShift - Return a vector logical shift node.
5268 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
5269 unsigned NumBits, SelectionDAG &DAG,
5270 const TargetLowering &TLI, SDLoc dl) {
5271 assert(VT.is128BitVector() && "Unknown type for VShift");
5272 EVT ShVT = MVT::v2i64;
5273 unsigned Opc = isLeft ? X86ISD::VSHLDQ : X86ISD::VSRLDQ;
5274 SrcOp = DAG.getNode(ISD::BITCAST, dl, ShVT, SrcOp);
5275 return DAG.getNode(ISD::BITCAST, dl, VT,
5276 DAG.getNode(Opc, dl, ShVT, SrcOp,
5277 DAG.getConstant(NumBits,
5278 TLI.getScalarShiftAmountTy(SrcOp.getValueType()))));
5282 LowerAsSplatVectorLoad(SDValue SrcOp, MVT VT, SDLoc dl, SelectionDAG &DAG) {
5284 // Check if the scalar load can be widened into a vector load. And if
5285 // the address is "base + cst" see if the cst can be "absorbed" into
5286 // the shuffle mask.
5287 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) {
5288 SDValue Ptr = LD->getBasePtr();
5289 if (!ISD::isNormalLoad(LD) || LD->isVolatile())
5291 EVT PVT = LD->getValueType(0);
5292 if (PVT != MVT::i32 && PVT != MVT::f32)
5297 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) {
5298 FI = FINode->getIndex();
5300 } else if (DAG.isBaseWithConstantOffset(Ptr) &&
5301 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
5302 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
5303 Offset = Ptr.getConstantOperandVal(1);
5304 Ptr = Ptr.getOperand(0);
5309 // FIXME: 256-bit vector instructions don't require a strict alignment,
5310 // improve this code to support it better.
5311 unsigned RequiredAlign = VT.getSizeInBits()/8;
5312 SDValue Chain = LD->getChain();
5313 // Make sure the stack object alignment is at least 16 or 32.
5314 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
5315 if (DAG.InferPtrAlignment(Ptr) < RequiredAlign) {
5316 if (MFI->isFixedObjectIndex(FI)) {
5317 // Can't change the alignment. FIXME: It's possible to compute
5318 // the exact stack offset and reference FI + adjust offset instead.
5319 // If someone *really* cares about this. That's the way to implement it.
5322 MFI->setObjectAlignment(FI, RequiredAlign);
5326 // (Offset % 16 or 32) must be multiple of 4. Then address is then
5327 // Ptr + (Offset & ~15).
5330 if ((Offset % RequiredAlign) & 3)
5332 int64_t StartOffset = Offset & ~(RequiredAlign-1);
5334 Ptr = DAG.getNode(ISD::ADD, SDLoc(Ptr), Ptr.getValueType(),
5335 Ptr,DAG.getConstant(StartOffset, Ptr.getValueType()));
5337 int EltNo = (Offset - StartOffset) >> 2;
5338 unsigned NumElems = VT.getVectorNumElements();
5340 EVT NVT = EVT::getVectorVT(*DAG.getContext(), PVT, NumElems);
5341 SDValue V1 = DAG.getLoad(NVT, dl, Chain, Ptr,
5342 LD->getPointerInfo().getWithOffset(StartOffset),
5343 false, false, false, 0);
5345 SmallVector<int, 8> Mask;
5346 for (unsigned i = 0; i != NumElems; ++i)
5347 Mask.push_back(EltNo);
5349 return DAG.getVectorShuffle(NVT, dl, V1, DAG.getUNDEF(NVT), &Mask[0]);
5355 /// EltsFromConsecutiveLoads - Given the initializing elements 'Elts' of a
5356 /// vector of type 'VT', see if the elements can be replaced by a single large
5357 /// load which has the same value as a build_vector whose operands are 'elts'.
5359 /// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a
5361 /// FIXME: we'd also like to handle the case where the last elements are zero
5362 /// rather than undef via VZEXT_LOAD, but we do not detect that case today.
5363 /// There's even a handy isZeroNode for that purpose.
5364 static SDValue EltsFromConsecutiveLoads(EVT VT, SmallVectorImpl<SDValue> &Elts,
5365 SDLoc &DL, SelectionDAG &DAG) {
5366 EVT EltVT = VT.getVectorElementType();
5367 unsigned NumElems = Elts.size();
5369 LoadSDNode *LDBase = NULL;
5370 unsigned LastLoadedElt = -1U;
5372 // For each element in the initializer, see if we've found a load or an undef.
5373 // If we don't find an initial load element, or later load elements are
5374 // non-consecutive, bail out.
5375 for (unsigned i = 0; i < NumElems; ++i) {
5376 SDValue Elt = Elts[i];
5378 if (!Elt.getNode() ||
5379 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
5382 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
5384 LDBase = cast<LoadSDNode>(Elt.getNode());
5388 if (Elt.getOpcode() == ISD::UNDEF)
5391 LoadSDNode *LD = cast<LoadSDNode>(Elt);
5392 if (!DAG.isConsecutiveLoad(LD, LDBase, EltVT.getSizeInBits()/8, i))
5397 // If we have found an entire vector of loads and undefs, then return a large
5398 // load of the entire vector width starting at the base pointer. If we found
5399 // consecutive loads for the low half, generate a vzext_load node.
5400 if (LastLoadedElt == NumElems - 1) {
5401 SDValue NewLd = SDValue();
5402 if (DAG.InferPtrAlignment(LDBase->getBasePtr()) >= 16)
5403 NewLd = DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
5404 LDBase->getPointerInfo(),
5405 LDBase->isVolatile(), LDBase->isNonTemporal(),
5406 LDBase->isInvariant(), 0);
5407 NewLd = DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
5408 LDBase->getPointerInfo(),
5409 LDBase->isVolatile(), LDBase->isNonTemporal(),
5410 LDBase->isInvariant(), LDBase->getAlignment());
5412 if (LDBase->hasAnyUseOfValue(1)) {
5413 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
5415 SDValue(NewLd.getNode(), 1));
5416 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
5417 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
5418 SDValue(NewLd.getNode(), 1));
5423 if (NumElems == 4 && LastLoadedElt == 1 &&
5424 DAG.getTargetLoweringInfo().isTypeLegal(MVT::v2i64)) {
5425 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
5426 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() };
5428 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys, Ops,
5429 array_lengthof(Ops), MVT::i64,
5430 LDBase->getPointerInfo(),
5431 LDBase->getAlignment(),
5432 false/*isVolatile*/, true/*ReadMem*/,
5435 // Make sure the newly-created LOAD is in the same position as LDBase in
5436 // terms of dependency. We create a TokenFactor for LDBase and ResNode, and
5437 // update uses of LDBase's output chain to use the TokenFactor.
5438 if (LDBase->hasAnyUseOfValue(1)) {
5439 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
5440 SDValue(LDBase, 1), SDValue(ResNode.getNode(), 1));
5441 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
5442 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
5443 SDValue(ResNode.getNode(), 1));
5446 return DAG.getNode(ISD::BITCAST, DL, VT, ResNode);
5451 /// LowerVectorBroadcast - Attempt to use the vbroadcast instruction
5452 /// to generate a splat value for the following cases:
5453 /// 1. A splat BUILD_VECTOR which uses a single scalar load, or a constant.
5454 /// 2. A splat shuffle which uses a scalar_to_vector node which comes from
5455 /// a scalar load, or a constant.
5456 /// The VBROADCAST node is returned when a pattern is found,
5457 /// or SDValue() otherwise.
5458 static SDValue LowerVectorBroadcast(SDValue Op, const X86Subtarget* Subtarget,
5459 SelectionDAG &DAG) {
5460 if (!Subtarget->hasFp256())
5463 MVT VT = Op.getSimpleValueType();
5466 assert((VT.is128BitVector() || VT.is256BitVector() || VT.is512BitVector()) &&
5467 "Unsupported vector type for broadcast.");
5472 switch (Op.getOpcode()) {
5474 // Unknown pattern found.
5477 case ISD::BUILD_VECTOR: {
5478 // The BUILD_VECTOR node must be a splat.
5479 if (!isSplatVector(Op.getNode()))
5482 Ld = Op.getOperand(0);
5483 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
5484 Ld.getOpcode() == ISD::ConstantFP);
5486 // The suspected load node has several users. Make sure that all
5487 // of its users are from the BUILD_VECTOR node.
5488 // Constants may have multiple users.
5489 if (!ConstSplatVal && !Ld->hasNUsesOfValue(VT.getVectorNumElements(), 0))
5494 case ISD::VECTOR_SHUFFLE: {
5495 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
5497 // Shuffles must have a splat mask where the first element is
5499 if ((!SVOp->isSplat()) || SVOp->getMaskElt(0) != 0)
5502 SDValue Sc = Op.getOperand(0);
5503 if (Sc.getOpcode() != ISD::SCALAR_TO_VECTOR &&
5504 Sc.getOpcode() != ISD::BUILD_VECTOR) {
5506 if (!Subtarget->hasInt256())
5509 // Use the register form of the broadcast instruction available on AVX2.
5510 if (VT.getSizeInBits() >= 256)
5511 Sc = Extract128BitVector(Sc, 0, DAG, dl);
5512 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Sc);
5515 Ld = Sc.getOperand(0);
5516 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
5517 Ld.getOpcode() == ISD::ConstantFP);
5519 // The scalar_to_vector node and the suspected
5520 // load node must have exactly one user.
5521 // Constants may have multiple users.
5523 // AVX-512 has register version of the broadcast
5524 bool hasRegVer = Subtarget->hasAVX512() && VT.is512BitVector() &&
5525 Ld.getValueType().getSizeInBits() >= 32;
5526 if (!ConstSplatVal && ((!Sc.hasOneUse() || !Ld.hasOneUse()) &&
5533 bool IsGE256 = (VT.getSizeInBits() >= 256);
5535 // Handle the broadcasting a single constant scalar from the constant pool
5536 // into a vector. On Sandybridge it is still better to load a constant vector
5537 // from the constant pool and not to broadcast it from a scalar.
5538 if (ConstSplatVal && Subtarget->hasInt256()) {
5539 EVT CVT = Ld.getValueType();
5540 assert(!CVT.isVector() && "Must not broadcast a vector type");
5541 unsigned ScalarSize = CVT.getSizeInBits();
5543 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64)) {
5544 const Constant *C = 0;
5545 if (ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Ld))
5546 C = CI->getConstantIntValue();
5547 else if (ConstantFPSDNode *CF = dyn_cast<ConstantFPSDNode>(Ld))
5548 C = CF->getConstantFPValue();
5550 assert(C && "Invalid constant type");
5552 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5553 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
5554 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
5555 Ld = DAG.getLoad(CVT, dl, DAG.getEntryNode(), CP,
5556 MachinePointerInfo::getConstantPool(),
5557 false, false, false, Alignment);
5559 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5563 bool IsLoad = ISD::isNormalLoad(Ld.getNode());
5564 unsigned ScalarSize = Ld.getValueType().getSizeInBits();
5566 // Handle AVX2 in-register broadcasts.
5567 if (!IsLoad && Subtarget->hasInt256() &&
5568 (ScalarSize == 32 || (IsGE256 && ScalarSize == 64)))
5569 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5571 // The scalar source must be a normal load.
5575 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64))
5576 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5578 // The integer check is needed for the 64-bit into 128-bit so it doesn't match
5579 // double since there is no vbroadcastsd xmm
5580 if (Subtarget->hasInt256() && Ld.getValueType().isInteger()) {
5581 if (ScalarSize == 8 || ScalarSize == 16 || ScalarSize == 64)
5582 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5585 // Unsupported broadcast.
5589 static SDValue buildFromShuffleMostly(SDValue Op, SelectionDAG &DAG) {
5590 MVT VT = Op.getSimpleValueType();
5592 // Skip if insert_vec_elt is not supported.
5593 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5594 if (!TLI.isOperationLegalOrCustom(ISD::INSERT_VECTOR_ELT, VT))
5598 unsigned NumElems = Op.getNumOperands();
5602 SmallVector<unsigned, 4> InsertIndices;
5603 SmallVector<int, 8> Mask(NumElems, -1);
5605 for (unsigned i = 0; i != NumElems; ++i) {
5606 unsigned Opc = Op.getOperand(i).getOpcode();
5608 if (Opc == ISD::UNDEF)
5611 if (Opc != ISD::EXTRACT_VECTOR_ELT) {
5612 // Quit if more than 1 elements need inserting.
5613 if (InsertIndices.size() > 1)
5616 InsertIndices.push_back(i);
5620 SDValue ExtractedFromVec = Op.getOperand(i).getOperand(0);
5621 SDValue ExtIdx = Op.getOperand(i).getOperand(1);
5623 // Quit if extracted from vector of different type.
5624 if (ExtractedFromVec.getValueType() != VT)
5627 // Quit if non-constant index.
5628 if (!isa<ConstantSDNode>(ExtIdx))
5631 if (VecIn1.getNode() == 0)
5632 VecIn1 = ExtractedFromVec;
5633 else if (VecIn1 != ExtractedFromVec) {
5634 if (VecIn2.getNode() == 0)
5635 VecIn2 = ExtractedFromVec;
5636 else if (VecIn2 != ExtractedFromVec)
5637 // Quit if more than 2 vectors to shuffle
5641 unsigned Idx = cast<ConstantSDNode>(ExtIdx)->getZExtValue();
5643 if (ExtractedFromVec == VecIn1)
5645 else if (ExtractedFromVec == VecIn2)
5646 Mask[i] = Idx + NumElems;
5649 if (VecIn1.getNode() == 0)
5652 VecIn2 = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT);
5653 SDValue NV = DAG.getVectorShuffle(VT, DL, VecIn1, VecIn2, &Mask[0]);
5654 for (unsigned i = 0, e = InsertIndices.size(); i != e; ++i) {
5655 unsigned Idx = InsertIndices[i];
5656 NV = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VT, NV, Op.getOperand(Idx),
5657 DAG.getIntPtrConstant(Idx));
5663 // Lower BUILD_VECTOR operation for v8i1 and v16i1 types.
5665 X86TargetLowering::LowerBUILD_VECTORvXi1(SDValue Op, SelectionDAG &DAG) const {
5667 MVT VT = Op.getSimpleValueType();
5668 assert((VT.getVectorElementType() == MVT::i1) && (VT.getSizeInBits() <= 16) &&
5669 "Unexpected type in LowerBUILD_VECTORvXi1!");
5672 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
5673 SDValue Cst = DAG.getTargetConstant(0, MVT::i1);
5674 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst,
5675 Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5676 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT,
5677 Ops, VT.getVectorNumElements());
5680 if (ISD::isBuildVectorAllOnes(Op.getNode())) {
5681 SDValue Cst = DAG.getTargetConstant(1, MVT::i1);
5682 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst,
5683 Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5684 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT,
5685 Ops, VT.getVectorNumElements());
5688 bool AllContants = true;
5689 uint64_t Immediate = 0;
5690 for (unsigned idx = 0, e = Op.getNumOperands(); idx < e; ++idx) {
5691 SDValue In = Op.getOperand(idx);
5692 if (In.getOpcode() == ISD::UNDEF)
5694 if (!isa<ConstantSDNode>(In)) {
5695 AllContants = false;
5698 if (cast<ConstantSDNode>(In)->getZExtValue())
5699 Immediate |= (1ULL << idx);
5703 SDValue FullMask = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1,
5704 DAG.getConstant(Immediate, MVT::i16));
5705 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, FullMask,
5706 DAG.getIntPtrConstant(0));
5709 // Splat vector (with undefs)
5710 SDValue In = Op.getOperand(0);
5711 for (unsigned i = 1, e = Op.getNumOperands(); i != e; ++i) {
5712 if (Op.getOperand(i) != In && Op.getOperand(i).getOpcode() != ISD::UNDEF)
5713 llvm_unreachable("Unsupported predicate operation");
5716 SDValue EFLAGS, X86CC;
5717 if (In.getOpcode() == ISD::SETCC) {
5718 SDValue Op0 = In.getOperand(0);
5719 SDValue Op1 = In.getOperand(1);
5720 ISD::CondCode CC = cast<CondCodeSDNode>(In.getOperand(2))->get();
5721 bool isFP = Op1.getValueType().isFloatingPoint();
5722 unsigned X86CCVal = TranslateX86CC(CC, isFP, Op0, Op1, DAG);
5724 assert(X86CCVal != X86::COND_INVALID && "Unsupported predicate operation");
5726 X86CC = DAG.getConstant(X86CCVal, MVT::i8);
5727 EFLAGS = EmitCmp(Op0, Op1, X86CCVal, DAG);
5728 EFLAGS = ConvertCmpIfNecessary(EFLAGS, DAG);
5729 } else if (In.getOpcode() == X86ISD::SETCC) {
5730 X86CC = In.getOperand(0);
5731 EFLAGS = In.getOperand(1);
5740 // res = allOnes ### CMOVNE -1, %res
5743 MVT InVT = In.getSimpleValueType();
5744 SDValue Bit1 = DAG.getNode(ISD::AND, dl, InVT, In, DAG.getConstant(1, InVT));
5745 EFLAGS = EmitTest(Bit1, X86::COND_NE, DAG);
5746 X86CC = DAG.getConstant(X86::COND_NE, MVT::i8);
5749 if (VT == MVT::v16i1) {
5750 SDValue Cst1 = DAG.getConstant(-1, MVT::i16);
5751 SDValue Cst0 = DAG.getConstant(0, MVT::i16);
5752 SDValue CmovOp = DAG.getNode(X86ISD::CMOV, dl, MVT::i16,
5753 Cst0, Cst1, X86CC, EFLAGS);
5754 return DAG.getNode(ISD::BITCAST, dl, VT, CmovOp);
5757 if (VT == MVT::v8i1) {
5758 SDValue Cst1 = DAG.getConstant(-1, MVT::i32);
5759 SDValue Cst0 = DAG.getConstant(0, MVT::i32);
5760 SDValue CmovOp = DAG.getNode(X86ISD::CMOV, dl, MVT::i32,
5761 Cst0, Cst1, X86CC, EFLAGS);
5762 CmovOp = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, CmovOp);
5763 return DAG.getNode(ISD::BITCAST, dl, VT, CmovOp);
5765 llvm_unreachable("Unsupported predicate operation");
5769 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
5772 MVT VT = Op.getSimpleValueType();
5773 MVT ExtVT = VT.getVectorElementType();
5774 unsigned NumElems = Op.getNumOperands();
5776 // Generate vectors for predicate vectors.
5777 if (VT.getScalarType() == MVT::i1 && Subtarget->hasAVX512())
5778 return LowerBUILD_VECTORvXi1(Op, DAG);
5780 // Vectors containing all zeros can be matched by pxor and xorps later
5781 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
5782 // Canonicalize this to <4 x i32> to 1) ensure the zero vectors are CSE'd
5783 // and 2) ensure that i64 scalars are eliminated on x86-32 hosts.
5784 if (VT == MVT::v4i32 || VT == MVT::v8i32 || VT == MVT::v16i32)
5787 return getZeroVector(VT, Subtarget, DAG, dl);
5790 // Vectors containing all ones can be matched by pcmpeqd on 128-bit width
5791 // vectors or broken into v4i32 operations on 256-bit vectors. AVX2 can use
5792 // vpcmpeqd on 256-bit vectors.
5793 if (Subtarget->hasSSE2() && ISD::isBuildVectorAllOnes(Op.getNode())) {
5794 if (VT == MVT::v4i32 || (VT == MVT::v8i32 && Subtarget->hasInt256()))
5797 if (!VT.is512BitVector())
5798 return getOnesVector(VT, Subtarget->hasInt256(), DAG, dl);
5801 SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG);
5802 if (Broadcast.getNode())
5805 unsigned EVTBits = ExtVT.getSizeInBits();
5807 unsigned NumZero = 0;
5808 unsigned NumNonZero = 0;
5809 unsigned NonZeros = 0;
5810 bool IsAllConstants = true;
5811 SmallSet<SDValue, 8> Values;
5812 for (unsigned i = 0; i < NumElems; ++i) {
5813 SDValue Elt = Op.getOperand(i);
5814 if (Elt.getOpcode() == ISD::UNDEF)
5817 if (Elt.getOpcode() != ISD::Constant &&
5818 Elt.getOpcode() != ISD::ConstantFP)
5819 IsAllConstants = false;
5820 if (X86::isZeroNode(Elt))
5823 NonZeros |= (1 << i);
5828 // All undef vector. Return an UNDEF. All zero vectors were handled above.
5829 if (NumNonZero == 0)
5830 return DAG.getUNDEF(VT);
5832 // Special case for single non-zero, non-undef, element.
5833 if (NumNonZero == 1) {
5834 unsigned Idx = countTrailingZeros(NonZeros);
5835 SDValue Item = Op.getOperand(Idx);
5837 // If this is an insertion of an i64 value on x86-32, and if the top bits of
5838 // the value are obviously zero, truncate the value to i32 and do the
5839 // insertion that way. Only do this if the value is non-constant or if the
5840 // value is a constant being inserted into element 0. It is cheaper to do
5841 // a constant pool load than it is to do a movd + shuffle.
5842 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
5843 (!IsAllConstants || Idx == 0)) {
5844 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
5846 assert(VT == MVT::v2i64 && "Expected an SSE value type!");
5847 EVT VecVT = MVT::v4i32;
5848 unsigned VecElts = 4;
5850 // Truncate the value (which may itself be a constant) to i32, and
5851 // convert it to a vector with movd (S2V+shuffle to zero extend).
5852 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
5853 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
5854 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
5856 // Now we have our 32-bit value zero extended in the low element of
5857 // a vector. If Idx != 0, swizzle it into place.
5859 SmallVector<int, 4> Mask;
5860 Mask.push_back(Idx);
5861 for (unsigned i = 1; i != VecElts; ++i)
5863 Item = DAG.getVectorShuffle(VecVT, dl, Item, DAG.getUNDEF(VecVT),
5866 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
5870 // If we have a constant or non-constant insertion into the low element of
5871 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
5872 // the rest of the elements. This will be matched as movd/movq/movss/movsd
5873 // depending on what the source datatype is.
5876 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5878 if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
5879 (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
5880 if (VT.is256BitVector() || VT.is512BitVector()) {
5881 SDValue ZeroVec = getZeroVector(VT, Subtarget, DAG, dl);
5882 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, ZeroVec,
5883 Item, DAG.getIntPtrConstant(0));
5885 assert(VT.is128BitVector() && "Expected an SSE value type!");
5886 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5887 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
5888 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
5891 if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
5892 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
5893 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
5894 if (VT.is256BitVector()) {
5895 SDValue ZeroVec = getZeroVector(MVT::v8i32, Subtarget, DAG, dl);
5896 Item = Insert128BitVector(ZeroVec, Item, 0, DAG, dl);
5898 assert(VT.is128BitVector() && "Expected an SSE value type!");
5899 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
5901 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
5905 // Is it a vector logical left shift?
5906 if (NumElems == 2 && Idx == 1 &&
5907 X86::isZeroNode(Op.getOperand(0)) &&
5908 !X86::isZeroNode(Op.getOperand(1))) {
5909 unsigned NumBits = VT.getSizeInBits();
5910 return getVShift(true, VT,
5911 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
5912 VT, Op.getOperand(1)),
5913 NumBits/2, DAG, *this, dl);
5916 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
5919 // Otherwise, if this is a vector with i32 or f32 elements, and the element
5920 // is a non-constant being inserted into an element other than the low one,
5921 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
5922 // movd/movss) to move this into the low element, then shuffle it into
5924 if (EVTBits == 32) {
5925 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5927 // Turn it into a shuffle of zero and zero-extended scalar to vector.
5928 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0, Subtarget, DAG);
5929 SmallVector<int, 8> MaskVec;
5930 for (unsigned i = 0; i != NumElems; ++i)
5931 MaskVec.push_back(i == Idx ? 0 : 1);
5932 return DAG.getVectorShuffle(VT, dl, Item, DAG.getUNDEF(VT), &MaskVec[0]);
5936 // Splat is obviously ok. Let legalizer expand it to a shuffle.
5937 if (Values.size() == 1) {
5938 if (EVTBits == 32) {
5939 // Instead of a shuffle like this:
5940 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
5941 // Check if it's possible to issue this instead.
5942 // shuffle (vload ptr)), undef, <1, 1, 1, 1>
5943 unsigned Idx = countTrailingZeros(NonZeros);
5944 SDValue Item = Op.getOperand(Idx);
5945 if (Op.getNode()->isOnlyUserOf(Item.getNode()))
5946 return LowerAsSplatVectorLoad(Item, VT, dl, DAG);
5951 // A vector full of immediates; various special cases are already
5952 // handled, so this is best done with a single constant-pool load.
5956 // For AVX-length vectors, build the individual 128-bit pieces and use
5957 // shuffles to put them in place.
5958 if (VT.is256BitVector()) {
5959 SmallVector<SDValue, 32> V;
5960 for (unsigned i = 0; i != NumElems; ++i)
5961 V.push_back(Op.getOperand(i));
5963 EVT HVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems/2);
5965 // Build both the lower and upper subvector.
5966 SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT, &V[0], NumElems/2);
5967 SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT, &V[NumElems / 2],
5970 // Recreate the wider vector with the lower and upper part.
5971 return Concat128BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
5974 // Let legalizer expand 2-wide build_vectors.
5975 if (EVTBits == 64) {
5976 if (NumNonZero == 1) {
5977 // One half is zero or undef.
5978 unsigned Idx = countTrailingZeros(NonZeros);
5979 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
5980 Op.getOperand(Idx));
5981 return getShuffleVectorZeroOrUndef(V2, Idx, true, Subtarget, DAG);
5986 // If element VT is < 32 bits, convert it to inserts into a zero vector.
5987 if (EVTBits == 8 && NumElems == 16) {
5988 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
5990 if (V.getNode()) return V;
5993 if (EVTBits == 16 && NumElems == 8) {
5994 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
5996 if (V.getNode()) return V;
5999 // If element VT is == 32 bits, turn it into a number of shuffles.
6000 SmallVector<SDValue, 8> V(NumElems);
6001 if (NumElems == 4 && NumZero > 0) {
6002 for (unsigned i = 0; i < 4; ++i) {
6003 bool isZero = !(NonZeros & (1 << i));
6005 V[i] = getZeroVector(VT, Subtarget, DAG, dl);
6007 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
6010 for (unsigned i = 0; i < 2; ++i) {
6011 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
6014 V[i] = V[i*2]; // Must be a zero vector.
6017 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
6020 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
6023 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
6028 bool Reverse1 = (NonZeros & 0x3) == 2;
6029 bool Reverse2 = ((NonZeros & (0x3 << 2)) >> 2) == 2;
6033 static_cast<int>(Reverse2 ? NumElems+1 : NumElems),
6034 static_cast<int>(Reverse2 ? NumElems : NumElems+1)
6036 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
6039 if (Values.size() > 1 && VT.is128BitVector()) {
6040 // Check for a build vector of consecutive loads.
6041 for (unsigned i = 0; i < NumElems; ++i)
6042 V[i] = Op.getOperand(i);
6044 // Check for elements which are consecutive loads.
6045 SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG);
6049 // Check for a build vector from mostly shuffle plus few inserting.
6050 SDValue Sh = buildFromShuffleMostly(Op, DAG);
6054 // For SSE 4.1, use insertps to put the high elements into the low element.
6055 if (getSubtarget()->hasSSE41()) {
6057 if (Op.getOperand(0).getOpcode() != ISD::UNDEF)
6058 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0));
6060 Result = DAG.getUNDEF(VT);
6062 for (unsigned i = 1; i < NumElems; ++i) {
6063 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue;
6064 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result,
6065 Op.getOperand(i), DAG.getIntPtrConstant(i));
6070 // Otherwise, expand into a number of unpckl*, start by extending each of
6071 // our (non-undef) elements to the full vector width with the element in the
6072 // bottom slot of the vector (which generates no code for SSE).
6073 for (unsigned i = 0; i < NumElems; ++i) {
6074 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
6075 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
6077 V[i] = DAG.getUNDEF(VT);
6080 // Next, we iteratively mix elements, e.g. for v4f32:
6081 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
6082 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
6083 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
6084 unsigned EltStride = NumElems >> 1;
6085 while (EltStride != 0) {
6086 for (unsigned i = 0; i < EltStride; ++i) {
6087 // If V[i+EltStride] is undef and this is the first round of mixing,
6088 // then it is safe to just drop this shuffle: V[i] is already in the
6089 // right place, the one element (since it's the first round) being
6090 // inserted as undef can be dropped. This isn't safe for successive
6091 // rounds because they will permute elements within both vectors.
6092 if (V[i+EltStride].getOpcode() == ISD::UNDEF &&
6093 EltStride == NumElems/2)
6096 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]);
6105 // LowerAVXCONCAT_VECTORS - 256-bit AVX can use the vinsertf128 instruction
6106 // to create 256-bit vectors from two other 128-bit ones.
6107 static SDValue LowerAVXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
6109 MVT ResVT = Op.getSimpleValueType();
6111 assert((ResVT.is256BitVector() ||
6112 ResVT.is512BitVector()) && "Value type must be 256-/512-bit wide");
6114 SDValue V1 = Op.getOperand(0);
6115 SDValue V2 = Op.getOperand(1);
6116 unsigned NumElems = ResVT.getVectorNumElements();
6117 if(ResVT.is256BitVector())
6118 return Concat128BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
6120 return Concat256BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
6123 static SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
6124 assert(Op.getNumOperands() == 2);
6126 // AVX/AVX-512 can use the vinsertf128 instruction to create 256-bit vectors
6127 // from two other 128-bit ones.
6128 return LowerAVXCONCAT_VECTORS(Op, DAG);
6131 // Try to lower a shuffle node into a simple blend instruction.
6133 LowerVECTOR_SHUFFLEtoBlend(ShuffleVectorSDNode *SVOp,
6134 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
6135 SDValue V1 = SVOp->getOperand(0);
6136 SDValue V2 = SVOp->getOperand(1);
6138 MVT VT = SVOp->getSimpleValueType(0);
6139 MVT EltVT = VT.getVectorElementType();
6140 unsigned NumElems = VT.getVectorNumElements();
6142 if (!Subtarget->hasSSE41() || EltVT == MVT::i8)
6144 if (!Subtarget->hasInt256() && VT == MVT::v16i16)
6147 // Check the mask for BLEND and build the value.
6148 unsigned MaskValue = 0;
6149 // There are 2 lanes if (NumElems > 8), and 1 lane otherwise.
6150 unsigned NumLanes = (NumElems-1)/8 + 1;
6151 unsigned NumElemsInLane = NumElems / NumLanes;
6153 // Blend for v16i16 should be symetric for the both lanes.
6154 for (unsigned i = 0; i < NumElemsInLane; ++i) {
6156 int SndLaneEltIdx = (NumLanes == 2) ?
6157 SVOp->getMaskElt(i + NumElemsInLane) : -1;
6158 int EltIdx = SVOp->getMaskElt(i);
6160 if ((EltIdx < 0 || EltIdx == (int)i) &&
6161 (SndLaneEltIdx < 0 || SndLaneEltIdx == (int)(i + NumElemsInLane)))
6164 if (((unsigned)EltIdx == (i + NumElems)) &&
6165 (SndLaneEltIdx < 0 ||
6166 (unsigned)SndLaneEltIdx == i + NumElems + NumElemsInLane))
6167 MaskValue |= (1<<i);
6172 // Convert i32 vectors to floating point if it is not AVX2.
6173 // AVX2 introduced VPBLENDD instruction for 128 and 256-bit vectors.
6175 if (EltVT == MVT::i64 || (EltVT == MVT::i32 && !Subtarget->hasInt256())) {
6176 BlendVT = MVT::getVectorVT(MVT::getFloatingPointVT(EltVT.getSizeInBits()),
6178 V1 = DAG.getNode(ISD::BITCAST, dl, VT, V1);
6179 V2 = DAG.getNode(ISD::BITCAST, dl, VT, V2);
6182 SDValue Ret = DAG.getNode(X86ISD::BLENDI, dl, BlendVT, V1, V2,
6183 DAG.getConstant(MaskValue, MVT::i32));
6184 return DAG.getNode(ISD::BITCAST, dl, VT, Ret);
6187 // v8i16 shuffles - Prefer shuffles in the following order:
6188 // 1. [all] pshuflw, pshufhw, optional move
6189 // 2. [ssse3] 1 x pshufb
6190 // 3. [ssse3] 2 x pshufb + 1 x por
6191 // 4. [all] mov + pshuflw + pshufhw + N x (pextrw + pinsrw)
6193 LowerVECTOR_SHUFFLEv8i16(SDValue Op, const X86Subtarget *Subtarget,
6194 SelectionDAG &DAG) {
6195 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6196 SDValue V1 = SVOp->getOperand(0);
6197 SDValue V2 = SVOp->getOperand(1);
6199 SmallVector<int, 8> MaskVals;
6201 // Determine if more than 1 of the words in each of the low and high quadwords
6202 // of the result come from the same quadword of one of the two inputs. Undef
6203 // mask values count as coming from any quadword, for better codegen.
6204 unsigned LoQuad[] = { 0, 0, 0, 0 };
6205 unsigned HiQuad[] = { 0, 0, 0, 0 };
6206 std::bitset<4> InputQuads;
6207 for (unsigned i = 0; i < 8; ++i) {
6208 unsigned *Quad = i < 4 ? LoQuad : HiQuad;
6209 int EltIdx = SVOp->getMaskElt(i);
6210 MaskVals.push_back(EltIdx);
6219 InputQuads.set(EltIdx / 4);
6222 int BestLoQuad = -1;
6223 unsigned MaxQuad = 1;
6224 for (unsigned i = 0; i < 4; ++i) {
6225 if (LoQuad[i] > MaxQuad) {
6227 MaxQuad = LoQuad[i];
6231 int BestHiQuad = -1;
6233 for (unsigned i = 0; i < 4; ++i) {
6234 if (HiQuad[i] > MaxQuad) {
6236 MaxQuad = HiQuad[i];
6240 // For SSSE3, If all 8 words of the result come from only 1 quadword of each
6241 // of the two input vectors, shuffle them into one input vector so only a
6242 // single pshufb instruction is necessary. If There are more than 2 input
6243 // quads, disable the next transformation since it does not help SSSE3.
6244 bool V1Used = InputQuads[0] || InputQuads[1];
6245 bool V2Used = InputQuads[2] || InputQuads[3];
6246 if (Subtarget->hasSSSE3()) {
6247 if (InputQuads.count() == 2 && V1Used && V2Used) {
6248 BestLoQuad = InputQuads[0] ? 0 : 1;
6249 BestHiQuad = InputQuads[2] ? 2 : 3;
6251 if (InputQuads.count() > 2) {
6257 // If BestLoQuad or BestHiQuad are set, shuffle the quads together and update
6258 // the shuffle mask. If a quad is scored as -1, that means that it contains
6259 // words from all 4 input quadwords.
6261 if (BestLoQuad >= 0 || BestHiQuad >= 0) {
6263 BestLoQuad < 0 ? 0 : BestLoQuad,
6264 BestHiQuad < 0 ? 1 : BestHiQuad
6266 NewV = DAG.getVectorShuffle(MVT::v2i64, dl,
6267 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V1),
6268 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V2), &MaskV[0]);
6269 NewV = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, NewV);
6271 // Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the
6272 // source words for the shuffle, to aid later transformations.
6273 bool AllWordsInNewV = true;
6274 bool InOrder[2] = { true, true };
6275 for (unsigned i = 0; i != 8; ++i) {
6276 int idx = MaskVals[i];
6278 InOrder[i/4] = false;
6279 if (idx < 0 || (idx/4) == BestLoQuad || (idx/4) == BestHiQuad)
6281 AllWordsInNewV = false;
6285 bool pshuflw = AllWordsInNewV, pshufhw = AllWordsInNewV;
6286 if (AllWordsInNewV) {
6287 for (int i = 0; i != 8; ++i) {
6288 int idx = MaskVals[i];
6291 idx = MaskVals[i] = (idx / 4) == BestLoQuad ? (idx & 3) : (idx & 3) + 4;
6292 if ((idx != i) && idx < 4)
6294 if ((idx != i) && idx > 3)
6303 // If we've eliminated the use of V2, and the new mask is a pshuflw or
6304 // pshufhw, that's as cheap as it gets. Return the new shuffle.
6305 if ((pshufhw && InOrder[0]) || (pshuflw && InOrder[1])) {
6306 unsigned Opc = pshufhw ? X86ISD::PSHUFHW : X86ISD::PSHUFLW;
6307 unsigned TargetMask = 0;
6308 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV,
6309 DAG.getUNDEF(MVT::v8i16), &MaskVals[0]);
6310 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
6311 TargetMask = pshufhw ? getShufflePSHUFHWImmediate(SVOp):
6312 getShufflePSHUFLWImmediate(SVOp);
6313 V1 = NewV.getOperand(0);
6314 return getTargetShuffleNode(Opc, dl, MVT::v8i16, V1, TargetMask, DAG);
6318 // Promote splats to a larger type which usually leads to more efficient code.
6319 // FIXME: Is this true if pshufb is available?
6320 if (SVOp->isSplat())
6321 return PromoteSplat(SVOp, DAG);
6323 // If we have SSSE3, and all words of the result are from 1 input vector,
6324 // case 2 is generated, otherwise case 3 is generated. If no SSSE3
6325 // is present, fall back to case 4.
6326 if (Subtarget->hasSSSE3()) {
6327 SmallVector<SDValue,16> pshufbMask;
6329 // If we have elements from both input vectors, set the high bit of the
6330 // shuffle mask element to zero out elements that come from V2 in the V1
6331 // mask, and elements that come from V1 in the V2 mask, so that the two
6332 // results can be OR'd together.
6333 bool TwoInputs = V1Used && V2Used;
6334 for (unsigned i = 0; i != 8; ++i) {
6335 int EltIdx = MaskVals[i] * 2;
6336 int Idx0 = (TwoInputs && (EltIdx >= 16)) ? 0x80 : EltIdx;
6337 int Idx1 = (TwoInputs && (EltIdx >= 16)) ? 0x80 : EltIdx+1;
6338 pshufbMask.push_back(DAG.getConstant(Idx0, MVT::i8));
6339 pshufbMask.push_back(DAG.getConstant(Idx1, MVT::i8));
6341 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V1);
6342 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
6343 DAG.getNode(ISD::BUILD_VECTOR, dl,
6344 MVT::v16i8, &pshufbMask[0], 16));
6346 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
6348 // Calculate the shuffle mask for the second input, shuffle it, and
6349 // OR it with the first shuffled input.
6351 for (unsigned i = 0; i != 8; ++i) {
6352 int EltIdx = MaskVals[i] * 2;
6353 int Idx0 = (EltIdx < 16) ? 0x80 : EltIdx - 16;
6354 int Idx1 = (EltIdx < 16) ? 0x80 : EltIdx - 15;
6355 pshufbMask.push_back(DAG.getConstant(Idx0, MVT::i8));
6356 pshufbMask.push_back(DAG.getConstant(Idx1, MVT::i8));
6358 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V2);
6359 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
6360 DAG.getNode(ISD::BUILD_VECTOR, dl,
6361 MVT::v16i8, &pshufbMask[0], 16));
6362 V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
6363 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
6366 // If BestLoQuad >= 0, generate a pshuflw to put the low elements in order,
6367 // and update MaskVals with new element order.
6368 std::bitset<8> InOrder;
6369 if (BestLoQuad >= 0) {
6370 int MaskV[] = { -1, -1, -1, -1, 4, 5, 6, 7 };
6371 for (int i = 0; i != 4; ++i) {
6372 int idx = MaskVals[i];
6375 } else if ((idx / 4) == BestLoQuad) {
6380 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
6383 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSSE3()) {
6384 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
6385 NewV = getTargetShuffleNode(X86ISD::PSHUFLW, dl, MVT::v8i16,
6387 getShufflePSHUFLWImmediate(SVOp), DAG);
6391 // If BestHi >= 0, generate a pshufhw to put the high elements in order,
6392 // and update MaskVals with the new element order.
6393 if (BestHiQuad >= 0) {
6394 int MaskV[] = { 0, 1, 2, 3, -1, -1, -1, -1 };
6395 for (unsigned i = 4; i != 8; ++i) {
6396 int idx = MaskVals[i];
6399 } else if ((idx / 4) == BestHiQuad) {
6400 MaskV[i] = (idx & 3) + 4;
6404 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
6407 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSSE3()) {
6408 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
6409 NewV = getTargetShuffleNode(X86ISD::PSHUFHW, dl, MVT::v8i16,
6411 getShufflePSHUFHWImmediate(SVOp), DAG);
6415 // In case BestHi & BestLo were both -1, which means each quadword has a word
6416 // from each of the four input quadwords, calculate the InOrder bitvector now
6417 // before falling through to the insert/extract cleanup.
6418 if (BestLoQuad == -1 && BestHiQuad == -1) {
6420 for (int i = 0; i != 8; ++i)
6421 if (MaskVals[i] < 0 || MaskVals[i] == i)
6425 // The other elements are put in the right place using pextrw and pinsrw.
6426 for (unsigned i = 0; i != 8; ++i) {
6429 int EltIdx = MaskVals[i];
6432 SDValue ExtOp = (EltIdx < 8) ?
6433 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1,
6434 DAG.getIntPtrConstant(EltIdx)) :
6435 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2,
6436 DAG.getIntPtrConstant(EltIdx - 8));
6437 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp,
6438 DAG.getIntPtrConstant(i));
6443 // v16i8 shuffles - Prefer shuffles in the following order:
6444 // 1. [ssse3] 1 x pshufb
6445 // 2. [ssse3] 2 x pshufb + 1 x por
6446 // 3. [all] v8i16 shuffle + N x pextrw + rotate + pinsrw
6447 static SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp,
6448 const X86Subtarget* Subtarget,
6449 SelectionDAG &DAG) {
6450 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6451 SDValue V1 = SVOp->getOperand(0);
6452 SDValue V2 = SVOp->getOperand(1);
6454 ArrayRef<int> MaskVals = SVOp->getMask();
6456 // Promote splats to a larger type which usually leads to more efficient code.
6457 // FIXME: Is this true if pshufb is available?
6458 if (SVOp->isSplat())
6459 return PromoteSplat(SVOp, DAG);
6461 // If we have SSSE3, case 1 is generated when all result bytes come from
6462 // one of the inputs. Otherwise, case 2 is generated. If no SSSE3 is
6463 // present, fall back to case 3.
6465 // If SSSE3, use 1 pshufb instruction per vector with elements in the result.
6466 if (Subtarget->hasSSSE3()) {
6467 SmallVector<SDValue,16> pshufbMask;
6469 // If all result elements are from one input vector, then only translate
6470 // undef mask values to 0x80 (zero out result) in the pshufb mask.
6472 // Otherwise, we have elements from both input vectors, and must zero out
6473 // elements that come from V2 in the first mask, and V1 in the second mask
6474 // so that we can OR them together.
6475 for (unsigned i = 0; i != 16; ++i) {
6476 int EltIdx = MaskVals[i];
6477 if (EltIdx < 0 || EltIdx >= 16)
6479 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
6481 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
6482 DAG.getNode(ISD::BUILD_VECTOR, dl,
6483 MVT::v16i8, &pshufbMask[0], 16));
6485 // As PSHUFB will zero elements with negative indices, it's safe to ignore
6486 // the 2nd operand if it's undefined or zero.
6487 if (V2.getOpcode() == ISD::UNDEF ||
6488 ISD::isBuildVectorAllZeros(V2.getNode()))
6491 // Calculate the shuffle mask for the second input, shuffle it, and
6492 // OR it with the first shuffled input.
6494 for (unsigned i = 0; i != 16; ++i) {
6495 int EltIdx = MaskVals[i];
6496 EltIdx = (EltIdx < 16) ? 0x80 : EltIdx - 16;
6497 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
6499 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
6500 DAG.getNode(ISD::BUILD_VECTOR, dl,
6501 MVT::v16i8, &pshufbMask[0], 16));
6502 return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
6505 // No SSSE3 - Calculate in place words and then fix all out of place words
6506 // With 0-16 extracts & inserts. Worst case is 16 bytes out of order from
6507 // the 16 different words that comprise the two doublequadword input vectors.
6508 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
6509 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V2);
6511 for (int i = 0; i != 8; ++i) {
6512 int Elt0 = MaskVals[i*2];
6513 int Elt1 = MaskVals[i*2+1];
6515 // This word of the result is all undef, skip it.
6516 if (Elt0 < 0 && Elt1 < 0)
6519 // This word of the result is already in the correct place, skip it.
6520 if ((Elt0 == i*2) && (Elt1 == i*2+1))
6523 SDValue Elt0Src = Elt0 < 16 ? V1 : V2;
6524 SDValue Elt1Src = Elt1 < 16 ? V1 : V2;
6527 // If Elt0 and Elt1 are defined, are consecutive, and can be load
6528 // using a single extract together, load it and store it.
6529 if ((Elt0 >= 0) && ((Elt0 + 1) == Elt1) && ((Elt0 & 1) == 0)) {
6530 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
6531 DAG.getIntPtrConstant(Elt1 / 2));
6532 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
6533 DAG.getIntPtrConstant(i));
6537 // If Elt1 is defined, extract it from the appropriate source. If the
6538 // source byte is not also odd, shift the extracted word left 8 bits
6539 // otherwise clear the bottom 8 bits if we need to do an or.
6541 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
6542 DAG.getIntPtrConstant(Elt1 / 2));
6543 if ((Elt1 & 1) == 0)
6544 InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt,
6546 TLI.getShiftAmountTy(InsElt.getValueType())));
6548 InsElt = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt,
6549 DAG.getConstant(0xFF00, MVT::i16));
6551 // If Elt0 is defined, extract it from the appropriate source. If the
6552 // source byte is not also even, shift the extracted word right 8 bits. If
6553 // Elt1 was also defined, OR the extracted values together before
6554 // inserting them in the result.
6556 SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16,
6557 Elt0Src, DAG.getIntPtrConstant(Elt0 / 2));
6558 if ((Elt0 & 1) != 0)
6559 InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0,
6561 TLI.getShiftAmountTy(InsElt0.getValueType())));
6563 InsElt0 = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt0,
6564 DAG.getConstant(0x00FF, MVT::i16));
6565 InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0)
6568 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
6569 DAG.getIntPtrConstant(i));
6571 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, NewV);
6574 // v32i8 shuffles - Translate to VPSHUFB if possible.
6576 SDValue LowerVECTOR_SHUFFLEv32i8(ShuffleVectorSDNode *SVOp,
6577 const X86Subtarget *Subtarget,
6578 SelectionDAG &DAG) {
6579 MVT VT = SVOp->getSimpleValueType(0);
6580 SDValue V1 = SVOp->getOperand(0);
6581 SDValue V2 = SVOp->getOperand(1);
6583 SmallVector<int, 32> MaskVals(SVOp->getMask().begin(), SVOp->getMask().end());
6585 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
6586 bool V1IsAllZero = ISD::isBuildVectorAllZeros(V1.getNode());
6587 bool V2IsAllZero = ISD::isBuildVectorAllZeros(V2.getNode());
6589 // VPSHUFB may be generated if
6590 // (1) one of input vector is undefined or zeroinitializer.
6591 // The mask value 0x80 puts 0 in the corresponding slot of the vector.
6592 // And (2) the mask indexes don't cross the 128-bit lane.
6593 if (VT != MVT::v32i8 || !Subtarget->hasInt256() ||
6594 (!V2IsUndef && !V2IsAllZero && !V1IsAllZero))
6597 if (V1IsAllZero && !V2IsAllZero) {
6598 CommuteVectorShuffleMask(MaskVals, 32);
6601 SmallVector<SDValue, 32> pshufbMask;
6602 for (unsigned i = 0; i != 32; i++) {
6603 int EltIdx = MaskVals[i];
6604 if (EltIdx < 0 || EltIdx >= 32)
6607 if ((EltIdx >= 16 && i < 16) || (EltIdx < 16 && i >= 16))
6608 // Cross lane is not allowed.
6612 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
6614 return DAG.getNode(X86ISD::PSHUFB, dl, MVT::v32i8, V1,
6615 DAG.getNode(ISD::BUILD_VECTOR, dl,
6616 MVT::v32i8, &pshufbMask[0], 32));
6619 /// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide
6620 /// ones, or rewriting v4i32 / v4f32 as 2 wide ones if possible. This can be
6621 /// done when every pair / quad of shuffle mask elements point to elements in
6622 /// the right sequence. e.g.
6623 /// vector_shuffle X, Y, <2, 3, | 10, 11, | 0, 1, | 14, 15>
6625 SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp,
6626 SelectionDAG &DAG) {
6627 MVT VT = SVOp->getSimpleValueType(0);
6629 unsigned NumElems = VT.getVectorNumElements();
6632 switch (VT.SimpleTy) {
6633 default: llvm_unreachable("Unexpected!");
6634 case MVT::v4f32: NewVT = MVT::v2f64; Scale = 2; break;
6635 case MVT::v4i32: NewVT = MVT::v2i64; Scale = 2; break;
6636 case MVT::v8i16: NewVT = MVT::v4i32; Scale = 2; break;
6637 case MVT::v16i8: NewVT = MVT::v4i32; Scale = 4; break;
6638 case MVT::v16i16: NewVT = MVT::v8i32; Scale = 2; break;
6639 case MVT::v32i8: NewVT = MVT::v8i32; Scale = 4; break;
6642 SmallVector<int, 8> MaskVec;
6643 for (unsigned i = 0; i != NumElems; i += Scale) {
6645 for (unsigned j = 0; j != Scale; ++j) {
6646 int EltIdx = SVOp->getMaskElt(i+j);
6650 StartIdx = (EltIdx / Scale);
6651 if (EltIdx != (int)(StartIdx*Scale + j))
6654 MaskVec.push_back(StartIdx);
6657 SDValue V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(0));
6658 SDValue V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(1));
6659 return DAG.getVectorShuffle(NewVT, dl, V1, V2, &MaskVec[0]);
6662 /// getVZextMovL - Return a zero-extending vector move low node.
6664 static SDValue getVZextMovL(MVT VT, MVT OpVT,
6665 SDValue SrcOp, SelectionDAG &DAG,
6666 const X86Subtarget *Subtarget, SDLoc dl) {
6667 if (VT == MVT::v2f64 || VT == MVT::v4f32) {
6668 LoadSDNode *LD = NULL;
6669 if (!isScalarLoadToVector(SrcOp.getNode(), &LD))
6670 LD = dyn_cast<LoadSDNode>(SrcOp);
6672 // movssrr and movsdrr do not clear top bits. Try to use movd, movq
6674 MVT ExtVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32;
6675 if ((ExtVT != MVT::i64 || Subtarget->is64Bit()) &&
6676 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR &&
6677 SrcOp.getOperand(0).getOpcode() == ISD::BITCAST &&
6678 SrcOp.getOperand(0).getOperand(0).getValueType() == ExtVT) {
6680 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32;
6681 return DAG.getNode(ISD::BITCAST, dl, VT,
6682 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
6683 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
6691 return DAG.getNode(ISD::BITCAST, dl, VT,
6692 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
6693 DAG.getNode(ISD::BITCAST, dl,
6697 /// LowerVECTOR_SHUFFLE_256 - Handle all 256-bit wide vectors shuffles
6698 /// which could not be matched by any known target speficic shuffle
6700 LowerVECTOR_SHUFFLE_256(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
6702 SDValue NewOp = Compact8x32ShuffleNode(SVOp, DAG);
6703 if (NewOp.getNode())
6706 MVT VT = SVOp->getSimpleValueType(0);
6708 unsigned NumElems = VT.getVectorNumElements();
6709 unsigned NumLaneElems = NumElems / 2;
6712 MVT EltVT = VT.getVectorElementType();
6713 MVT NVT = MVT::getVectorVT(EltVT, NumLaneElems);
6716 SmallVector<int, 16> Mask;
6717 for (unsigned l = 0; l < 2; ++l) {
6718 // Build a shuffle mask for the output, discovering on the fly which
6719 // input vectors to use as shuffle operands (recorded in InputUsed).
6720 // If building a suitable shuffle vector proves too hard, then bail
6721 // out with UseBuildVector set.
6722 bool UseBuildVector = false;
6723 int InputUsed[2] = { -1, -1 }; // Not yet discovered.
6724 unsigned LaneStart = l * NumLaneElems;
6725 for (unsigned i = 0; i != NumLaneElems; ++i) {
6726 // The mask element. This indexes into the input.
6727 int Idx = SVOp->getMaskElt(i+LaneStart);
6729 // the mask element does not index into any input vector.
6734 // The input vector this mask element indexes into.
6735 int Input = Idx / NumLaneElems;
6737 // Turn the index into an offset from the start of the input vector.
6738 Idx -= Input * NumLaneElems;
6740 // Find or create a shuffle vector operand to hold this input.
6742 for (OpNo = 0; OpNo < array_lengthof(InputUsed); ++OpNo) {
6743 if (InputUsed[OpNo] == Input)
6744 // This input vector is already an operand.
6746 if (InputUsed[OpNo] < 0) {
6747 // Create a new operand for this input vector.
6748 InputUsed[OpNo] = Input;
6753 if (OpNo >= array_lengthof(InputUsed)) {
6754 // More than two input vectors used! Give up on trying to create a
6755 // shuffle vector. Insert all elements into a BUILD_VECTOR instead.
6756 UseBuildVector = true;
6760 // Add the mask index for the new shuffle vector.
6761 Mask.push_back(Idx + OpNo * NumLaneElems);
6764 if (UseBuildVector) {
6765 SmallVector<SDValue, 16> SVOps;
6766 for (unsigned i = 0; i != NumLaneElems; ++i) {
6767 // The mask element. This indexes into the input.
6768 int Idx = SVOp->getMaskElt(i+LaneStart);
6770 SVOps.push_back(DAG.getUNDEF(EltVT));
6774 // The input vector this mask element indexes into.
6775 int Input = Idx / NumElems;
6777 // Turn the index into an offset from the start of the input vector.
6778 Idx -= Input * NumElems;
6780 // Extract the vector element by hand.
6781 SVOps.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
6782 SVOp->getOperand(Input),
6783 DAG.getIntPtrConstant(Idx)));
6786 // Construct the output using a BUILD_VECTOR.
6787 Output[l] = DAG.getNode(ISD::BUILD_VECTOR, dl, NVT, &SVOps[0],
6789 } else if (InputUsed[0] < 0) {
6790 // No input vectors were used! The result is undefined.
6791 Output[l] = DAG.getUNDEF(NVT);
6793 SDValue Op0 = Extract128BitVector(SVOp->getOperand(InputUsed[0] / 2),
6794 (InputUsed[0] % 2) * NumLaneElems,
6796 // If only one input was used, use an undefined vector for the other.
6797 SDValue Op1 = (InputUsed[1] < 0) ? DAG.getUNDEF(NVT) :
6798 Extract128BitVector(SVOp->getOperand(InputUsed[1] / 2),
6799 (InputUsed[1] % 2) * NumLaneElems, DAG, dl);
6800 // At least one input vector was used. Create a new shuffle vector.
6801 Output[l] = DAG.getVectorShuffle(NVT, dl, Op0, Op1, &Mask[0]);
6807 // Concatenate the result back
6808 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, Output[0], Output[1]);
6811 /// LowerVECTOR_SHUFFLE_128v4 - Handle all 128-bit wide vectors with
6812 /// 4 elements, and match them with several different shuffle types.
6814 LowerVECTOR_SHUFFLE_128v4(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
6815 SDValue V1 = SVOp->getOperand(0);
6816 SDValue V2 = SVOp->getOperand(1);
6818 MVT VT = SVOp->getSimpleValueType(0);
6820 assert(VT.is128BitVector() && "Unsupported vector size");
6822 std::pair<int, int> Locs[4];
6823 int Mask1[] = { -1, -1, -1, -1 };
6824 SmallVector<int, 8> PermMask(SVOp->getMask().begin(), SVOp->getMask().end());
6828 for (unsigned i = 0; i != 4; ++i) {
6829 int Idx = PermMask[i];
6831 Locs[i] = std::make_pair(-1, -1);
6833 assert(Idx < 8 && "Invalid VECTOR_SHUFFLE index!");
6835 Locs[i] = std::make_pair(0, NumLo);
6839 Locs[i] = std::make_pair(1, NumHi);
6841 Mask1[2+NumHi] = Idx;
6847 if (NumLo <= 2 && NumHi <= 2) {
6848 // If no more than two elements come from either vector. This can be
6849 // implemented with two shuffles. First shuffle gather the elements.
6850 // The second shuffle, which takes the first shuffle as both of its
6851 // vector operands, put the elements into the right order.
6852 V1 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
6854 int Mask2[] = { -1, -1, -1, -1 };
6856 for (unsigned i = 0; i != 4; ++i)
6857 if (Locs[i].first != -1) {
6858 unsigned Idx = (i < 2) ? 0 : 4;
6859 Idx += Locs[i].first * 2 + Locs[i].second;
6863 return DAG.getVectorShuffle(VT, dl, V1, V1, &Mask2[0]);
6866 if (NumLo == 3 || NumHi == 3) {
6867 // Otherwise, we must have three elements from one vector, call it X, and
6868 // one element from the other, call it Y. First, use a shufps to build an
6869 // intermediate vector with the one element from Y and the element from X
6870 // that will be in the same half in the final destination (the indexes don't
6871 // matter). Then, use a shufps to build the final vector, taking the half
6872 // containing the element from Y from the intermediate, and the other half
6875 // Normalize it so the 3 elements come from V1.
6876 CommuteVectorShuffleMask(PermMask, 4);
6880 // Find the element from V2.
6882 for (HiIndex = 0; HiIndex < 3; ++HiIndex) {
6883 int Val = PermMask[HiIndex];
6890 Mask1[0] = PermMask[HiIndex];
6892 Mask1[2] = PermMask[HiIndex^1];
6894 V2 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
6897 Mask1[0] = PermMask[0];
6898 Mask1[1] = PermMask[1];
6899 Mask1[2] = HiIndex & 1 ? 6 : 4;
6900 Mask1[3] = HiIndex & 1 ? 4 : 6;
6901 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
6904 Mask1[0] = HiIndex & 1 ? 2 : 0;
6905 Mask1[1] = HiIndex & 1 ? 0 : 2;
6906 Mask1[2] = PermMask[2];
6907 Mask1[3] = PermMask[3];
6912 return DAG.getVectorShuffle(VT, dl, V2, V1, &Mask1[0]);
6915 // Break it into (shuffle shuffle_hi, shuffle_lo).
6916 int LoMask[] = { -1, -1, -1, -1 };
6917 int HiMask[] = { -1, -1, -1, -1 };
6919 int *MaskPtr = LoMask;
6920 unsigned MaskIdx = 0;
6923 for (unsigned i = 0; i != 4; ++i) {
6930 int Idx = PermMask[i];
6932 Locs[i] = std::make_pair(-1, -1);
6933 } else if (Idx < 4) {
6934 Locs[i] = std::make_pair(MaskIdx, LoIdx);
6935 MaskPtr[LoIdx] = Idx;
6938 Locs[i] = std::make_pair(MaskIdx, HiIdx);
6939 MaskPtr[HiIdx] = Idx;
6944 SDValue LoShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &LoMask[0]);
6945 SDValue HiShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &HiMask[0]);
6946 int MaskOps[] = { -1, -1, -1, -1 };
6947 for (unsigned i = 0; i != 4; ++i)
6948 if (Locs[i].first != -1)
6949 MaskOps[i] = Locs[i].first * 4 + Locs[i].second;
6950 return DAG.getVectorShuffle(VT, dl, LoShuffle, HiShuffle, &MaskOps[0]);
6953 static bool MayFoldVectorLoad(SDValue V) {
6954 while (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
6955 V = V.getOperand(0);
6957 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR)
6958 V = V.getOperand(0);
6959 if (V.hasOneUse() && V.getOpcode() == ISD::BUILD_VECTOR &&
6960 V.getNumOperands() == 2 && V.getOperand(1).getOpcode() == ISD::UNDEF)
6961 // BUILD_VECTOR (load), undef
6962 V = V.getOperand(0);
6964 return MayFoldLoad(V);
6968 SDValue getMOVDDup(SDValue &Op, SDLoc &dl, SDValue V1, SelectionDAG &DAG) {
6969 MVT VT = Op.getSimpleValueType();
6971 // Canonizalize to v2f64.
6972 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, V1);
6973 return DAG.getNode(ISD::BITCAST, dl, VT,
6974 getTargetShuffleNode(X86ISD::MOVDDUP, dl, MVT::v2f64,
6979 SDValue getMOVLowToHigh(SDValue &Op, SDLoc &dl, SelectionDAG &DAG,
6981 SDValue V1 = Op.getOperand(0);
6982 SDValue V2 = Op.getOperand(1);
6983 MVT VT = Op.getSimpleValueType();
6985 assert(VT != MVT::v2i64 && "unsupported shuffle type");
6987 if (HasSSE2 && VT == MVT::v2f64)
6988 return getTargetShuffleNode(X86ISD::MOVLHPD, dl, VT, V1, V2, DAG);
6990 // v4f32 or v4i32: canonizalized to v4f32 (which is legal for SSE1)
6991 return DAG.getNode(ISD::BITCAST, dl, VT,
6992 getTargetShuffleNode(X86ISD::MOVLHPS, dl, MVT::v4f32,
6993 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V1),
6994 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V2), DAG));
6998 SDValue getMOVHighToLow(SDValue &Op, SDLoc &dl, SelectionDAG &DAG) {
6999 SDValue V1 = Op.getOperand(0);
7000 SDValue V2 = Op.getOperand(1);
7001 MVT VT = Op.getSimpleValueType();
7003 assert((VT == MVT::v4i32 || VT == MVT::v4f32) &&
7004 "unsupported shuffle type");
7006 if (V2.getOpcode() == ISD::UNDEF)
7010 return getTargetShuffleNode(X86ISD::MOVHLPS, dl, VT, V1, V2, DAG);
7014 SDValue getMOVLP(SDValue &Op, SDLoc &dl, SelectionDAG &DAG, bool HasSSE2) {
7015 SDValue V1 = Op.getOperand(0);
7016 SDValue V2 = Op.getOperand(1);
7017 MVT VT = Op.getSimpleValueType();
7018 unsigned NumElems = VT.getVectorNumElements();
7020 // Use MOVLPS and MOVLPD in case V1 or V2 are loads. During isel, the second
7021 // operand of these instructions is only memory, so check if there's a
7022 // potencial load folding here, otherwise use SHUFPS or MOVSD to match the
7024 bool CanFoldLoad = false;
7026 // Trivial case, when V2 comes from a load.
7027 if (MayFoldVectorLoad(V2))
7030 // When V1 is a load, it can be folded later into a store in isel, example:
7031 // (store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)), addr:$src1)
7033 // (MOVLPSmr addr:$src1, VR128:$src2)
7034 // So, recognize this potential and also use MOVLPS or MOVLPD
7035 else if (MayFoldVectorLoad(V1) && MayFoldIntoStore(Op))
7038 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7040 if (HasSSE2 && NumElems == 2)
7041 return getTargetShuffleNode(X86ISD::MOVLPD, dl, VT, V1, V2, DAG);
7044 // If we don't care about the second element, proceed to use movss.
7045 if (SVOp->getMaskElt(1) != -1)
7046 return getTargetShuffleNode(X86ISD::MOVLPS, dl, VT, V1, V2, DAG);
7049 // movl and movlp will both match v2i64, but v2i64 is never matched by
7050 // movl earlier because we make it strict to avoid messing with the movlp load
7051 // folding logic (see the code above getMOVLP call). Match it here then,
7052 // this is horrible, but will stay like this until we move all shuffle
7053 // matching to x86 specific nodes. Note that for the 1st condition all
7054 // types are matched with movsd.
7056 // FIXME: isMOVLMask should be checked and matched before getMOVLP,
7057 // as to remove this logic from here, as much as possible
7058 if (NumElems == 2 || !isMOVLMask(SVOp->getMask(), VT))
7059 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
7060 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
7063 assert(VT != MVT::v4i32 && "unsupported shuffle type");
7065 // Invert the operand order and use SHUFPS to match it.
7066 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V2, V1,
7067 getShuffleSHUFImmediate(SVOp), DAG);
7070 // Reduce a vector shuffle to zext.
7071 static SDValue LowerVectorIntExtend(SDValue Op, const X86Subtarget *Subtarget,
7072 SelectionDAG &DAG) {
7073 // PMOVZX is only available from SSE41.
7074 if (!Subtarget->hasSSE41())
7077 MVT VT = Op.getSimpleValueType();
7079 // Only AVX2 support 256-bit vector integer extending.
7080 if (!Subtarget->hasInt256() && VT.is256BitVector())
7083 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7085 SDValue V1 = Op.getOperand(0);
7086 SDValue V2 = Op.getOperand(1);
7087 unsigned NumElems = VT.getVectorNumElements();
7089 // Extending is an unary operation and the element type of the source vector
7090 // won't be equal to or larger than i64.
7091 if (V2.getOpcode() != ISD::UNDEF || !VT.isInteger() ||
7092 VT.getVectorElementType() == MVT::i64)
7095 // Find the expansion ratio, e.g. expanding from i8 to i32 has a ratio of 4.
7096 unsigned Shift = 1; // Start from 2, i.e. 1 << 1.
7097 while ((1U << Shift) < NumElems) {
7098 if (SVOp->getMaskElt(1U << Shift) == 1)
7101 // The maximal ratio is 8, i.e. from i8 to i64.
7106 // Check the shuffle mask.
7107 unsigned Mask = (1U << Shift) - 1;
7108 for (unsigned i = 0; i != NumElems; ++i) {
7109 int EltIdx = SVOp->getMaskElt(i);
7110 if ((i & Mask) != 0 && EltIdx != -1)
7112 if ((i & Mask) == 0 && (unsigned)EltIdx != (i >> Shift))
7116 unsigned NBits = VT.getVectorElementType().getSizeInBits() << Shift;
7117 MVT NeVT = MVT::getIntegerVT(NBits);
7118 MVT NVT = MVT::getVectorVT(NeVT, NumElems >> Shift);
7120 if (!DAG.getTargetLoweringInfo().isTypeLegal(NVT))
7123 // Simplify the operand as it's prepared to be fed into shuffle.
7124 unsigned SignificantBits = NVT.getSizeInBits() >> Shift;
7125 if (V1.getOpcode() == ISD::BITCAST &&
7126 V1.getOperand(0).getOpcode() == ISD::SCALAR_TO_VECTOR &&
7127 V1.getOperand(0).getOperand(0).getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
7128 V1.getOperand(0).getOperand(0)
7129 .getSimpleValueType().getSizeInBits() == SignificantBits) {
7130 // (bitcast (sclr2vec (ext_vec_elt x))) -> (bitcast x)
7131 SDValue V = V1.getOperand(0).getOperand(0).getOperand(0);
7132 ConstantSDNode *CIdx =
7133 dyn_cast<ConstantSDNode>(V1.getOperand(0).getOperand(0).getOperand(1));
7134 // If it's foldable, i.e. normal load with single use, we will let code
7135 // selection to fold it. Otherwise, we will short the conversion sequence.
7136 if (CIdx && CIdx->getZExtValue() == 0 &&
7137 (!ISD::isNormalLoad(V.getNode()) || !V.hasOneUse())) {
7138 MVT FullVT = V.getSimpleValueType();
7139 MVT V1VT = V1.getSimpleValueType();
7140 if (FullVT.getSizeInBits() > V1VT.getSizeInBits()) {
7141 // The "ext_vec_elt" node is wider than the result node.
7142 // In this case we should extract subvector from V.
7143 // (bitcast (sclr2vec (ext_vec_elt x))) -> (bitcast (extract_subvector x)).
7144 unsigned Ratio = FullVT.getSizeInBits() / V1VT.getSizeInBits();
7145 MVT SubVecVT = MVT::getVectorVT(FullVT.getVectorElementType(),
7146 FullVT.getVectorNumElements()/Ratio);
7147 V = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVecVT, V,
7148 DAG.getIntPtrConstant(0));
7150 V1 = DAG.getNode(ISD::BITCAST, DL, V1VT, V);
7154 return DAG.getNode(ISD::BITCAST, DL, VT,
7155 DAG.getNode(X86ISD::VZEXT, DL, NVT, V1));
7159 NormalizeVectorShuffle(SDValue Op, const X86Subtarget *Subtarget,
7160 SelectionDAG &DAG) {
7161 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7162 MVT VT = Op.getSimpleValueType();
7164 SDValue V1 = Op.getOperand(0);
7165 SDValue V2 = Op.getOperand(1);
7167 if (isZeroShuffle(SVOp))
7168 return getZeroVector(VT, Subtarget, DAG, dl);
7170 // Handle splat operations
7171 if (SVOp->isSplat()) {
7172 // Use vbroadcast whenever the splat comes from a foldable load
7173 SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG);
7174 if (Broadcast.getNode())
7178 // Check integer expanding shuffles.
7179 SDValue NewOp = LowerVectorIntExtend(Op, Subtarget, DAG);
7180 if (NewOp.getNode())
7183 // If the shuffle can be profitably rewritten as a narrower shuffle, then
7185 if (VT == MVT::v8i16 || VT == MVT::v16i8 ||
7186 VT == MVT::v16i16 || VT == MVT::v32i8) {
7187 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
7188 if (NewOp.getNode())
7189 return DAG.getNode(ISD::BITCAST, dl, VT, NewOp);
7190 } else if ((VT == MVT::v4i32 ||
7191 (VT == MVT::v4f32 && Subtarget->hasSSE2()))) {
7192 // FIXME: Figure out a cleaner way to do this.
7193 // Try to make use of movq to zero out the top part.
7194 if (ISD::isBuildVectorAllZeros(V2.getNode())) {
7195 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
7196 if (NewOp.getNode()) {
7197 MVT NewVT = NewOp.getSimpleValueType();
7198 if (isCommutedMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(),
7199 NewVT, true, false))
7200 return getVZextMovL(VT, NewVT, NewOp.getOperand(0),
7201 DAG, Subtarget, dl);
7203 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) {
7204 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
7205 if (NewOp.getNode()) {
7206 MVT NewVT = NewOp.getSimpleValueType();
7207 if (isMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(), NewVT))
7208 return getVZextMovL(VT, NewVT, NewOp.getOperand(1),
7209 DAG, Subtarget, dl);
7217 X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const {
7218 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7219 SDValue V1 = Op.getOperand(0);
7220 SDValue V2 = Op.getOperand(1);
7221 MVT VT = Op.getSimpleValueType();
7223 unsigned NumElems = VT.getVectorNumElements();
7224 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
7225 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
7226 bool V1IsSplat = false;
7227 bool V2IsSplat = false;
7228 bool HasSSE2 = Subtarget->hasSSE2();
7229 bool HasFp256 = Subtarget->hasFp256();
7230 bool HasInt256 = Subtarget->hasInt256();
7231 MachineFunction &MF = DAG.getMachineFunction();
7232 bool OptForSize = MF.getFunction()->getAttributes().
7233 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
7235 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
7237 if (V1IsUndef && V2IsUndef)
7238 return DAG.getUNDEF(VT);
7240 assert(!V1IsUndef && "Op 1 of shuffle should not be undef");
7242 // Vector shuffle lowering takes 3 steps:
7244 // 1) Normalize the input vectors. Here splats, zeroed vectors, profitable
7245 // narrowing and commutation of operands should be handled.
7246 // 2) Matching of shuffles with known shuffle masks to x86 target specific
7248 // 3) Rewriting of unmatched masks into new generic shuffle operations,
7249 // so the shuffle can be broken into other shuffles and the legalizer can
7250 // try the lowering again.
7252 // The general idea is that no vector_shuffle operation should be left to
7253 // be matched during isel, all of them must be converted to a target specific
7256 // Normalize the input vectors. Here splats, zeroed vectors, profitable
7257 // narrowing and commutation of operands should be handled. The actual code
7258 // doesn't include all of those, work in progress...
7259 SDValue NewOp = NormalizeVectorShuffle(Op, Subtarget, DAG);
7260 if (NewOp.getNode())
7263 SmallVector<int, 8> M(SVOp->getMask().begin(), SVOp->getMask().end());
7265 // NOTE: isPSHUFDMask can also match both masks below (unpckl_undef and
7266 // unpckh_undef). Only use pshufd if speed is more important than size.
7267 if (OptForSize && isUNPCKL_v_undef_Mask(M, VT, HasInt256))
7268 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
7269 if (OptForSize && isUNPCKH_v_undef_Mask(M, VT, HasInt256))
7270 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
7272 if (isMOVDDUPMask(M, VT) && Subtarget->hasSSE3() &&
7273 V2IsUndef && MayFoldVectorLoad(V1))
7274 return getMOVDDup(Op, dl, V1, DAG);
7276 if (isMOVHLPS_v_undef_Mask(M, VT))
7277 return getMOVHighToLow(Op, dl, DAG);
7279 // Use to match splats
7280 if (HasSSE2 && isUNPCKHMask(M, VT, HasInt256) && V2IsUndef &&
7281 (VT == MVT::v2f64 || VT == MVT::v2i64))
7282 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
7284 if (isPSHUFDMask(M, VT)) {
7285 // The actual implementation will match the mask in the if above and then
7286 // during isel it can match several different instructions, not only pshufd
7287 // as its name says, sad but true, emulate the behavior for now...
7288 if (isMOVDDUPMask(M, VT) && ((VT == MVT::v4f32 || VT == MVT::v2i64)))
7289 return getTargetShuffleNode(X86ISD::MOVLHPS, dl, VT, V1, V1, DAG);
7291 unsigned TargetMask = getShuffleSHUFImmediate(SVOp);
7293 if (HasSSE2 && (VT == MVT::v4f32 || VT == MVT::v4i32))
7294 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1, TargetMask, DAG);
7296 if (HasFp256 && (VT == MVT::v4f32 || VT == MVT::v2f64))
7297 return getTargetShuffleNode(X86ISD::VPERMILP, dl, VT, V1, TargetMask,
7300 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V1,
7304 if (isPALIGNRMask(M, VT, Subtarget))
7305 return getTargetShuffleNode(X86ISD::PALIGNR, dl, VT, V1, V2,
7306 getShufflePALIGNRImmediate(SVOp),
7309 // Check if this can be converted into a logical shift.
7310 bool isLeft = false;
7313 bool isShift = HasSSE2 && isVectorShift(SVOp, DAG, isLeft, ShVal, ShAmt);
7314 if (isShift && ShVal.hasOneUse()) {
7315 // If the shifted value has multiple uses, it may be cheaper to use
7316 // v_set0 + movlhps or movhlps, etc.
7317 MVT EltVT = VT.getVectorElementType();
7318 ShAmt *= EltVT.getSizeInBits();
7319 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
7322 if (isMOVLMask(M, VT)) {
7323 if (ISD::isBuildVectorAllZeros(V1.getNode()))
7324 return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl);
7325 if (!isMOVLPMask(M, VT)) {
7326 if (HasSSE2 && (VT == MVT::v2i64 || VT == MVT::v2f64))
7327 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
7329 if (VT == MVT::v4i32 || VT == MVT::v4f32)
7330 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
7334 // FIXME: fold these into legal mask.
7335 if (isMOVLHPSMask(M, VT) && !isUNPCKLMask(M, VT, HasInt256))
7336 return getMOVLowToHigh(Op, dl, DAG, HasSSE2);
7338 if (isMOVHLPSMask(M, VT))
7339 return getMOVHighToLow(Op, dl, DAG);
7341 if (V2IsUndef && isMOVSHDUPMask(M, VT, Subtarget))
7342 return getTargetShuffleNode(X86ISD::MOVSHDUP, dl, VT, V1, DAG);
7344 if (V2IsUndef && isMOVSLDUPMask(M, VT, Subtarget))
7345 return getTargetShuffleNode(X86ISD::MOVSLDUP, dl, VT, V1, DAG);
7347 if (isMOVLPMask(M, VT))
7348 return getMOVLP(Op, dl, DAG, HasSSE2);
7350 if (ShouldXformToMOVHLPS(M, VT) ||
7351 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), M, VT))
7352 return CommuteVectorShuffle(SVOp, DAG);
7355 // No better options. Use a vshldq / vsrldq.
7356 MVT EltVT = VT.getVectorElementType();
7357 ShAmt *= EltVT.getSizeInBits();
7358 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
7361 bool Commuted = false;
7362 // FIXME: This should also accept a bitcast of a splat? Be careful, not
7363 // 1,1,1,1 -> v8i16 though.
7364 V1IsSplat = isSplatVector(V1.getNode());
7365 V2IsSplat = isSplatVector(V2.getNode());
7367 // Canonicalize the splat or undef, if present, to be on the RHS.
7368 if (!V2IsUndef && V1IsSplat && !V2IsSplat) {
7369 CommuteVectorShuffleMask(M, NumElems);
7371 std::swap(V1IsSplat, V2IsSplat);
7375 if (isCommutedMOVLMask(M, VT, V2IsSplat, V2IsUndef)) {
7376 // Shuffling low element of v1 into undef, just return v1.
7379 // If V2 is a splat, the mask may be malformed such as <4,3,3,3>, which
7380 // the instruction selector will not match, so get a canonical MOVL with
7381 // swapped operands to undo the commute.
7382 return getMOVL(DAG, dl, VT, V2, V1);
7385 if (isUNPCKLMask(M, VT, HasInt256))
7386 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
7388 if (isUNPCKHMask(M, VT, HasInt256))
7389 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
7392 // Normalize mask so all entries that point to V2 points to its first
7393 // element then try to match unpck{h|l} again. If match, return a
7394 // new vector_shuffle with the corrected mask.p
7395 SmallVector<int, 8> NewMask(M.begin(), M.end());
7396 NormalizeMask(NewMask, NumElems);
7397 if (isUNPCKLMask(NewMask, VT, HasInt256, true))
7398 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
7399 if (isUNPCKHMask(NewMask, VT, HasInt256, true))
7400 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
7404 // Commute is back and try unpck* again.
7405 // FIXME: this seems wrong.
7406 CommuteVectorShuffleMask(M, NumElems);
7408 std::swap(V1IsSplat, V2IsSplat);
7411 if (isUNPCKLMask(M, VT, HasInt256))
7412 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
7414 if (isUNPCKHMask(M, VT, HasInt256))
7415 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
7418 // Normalize the node to match x86 shuffle ops if needed
7419 if (!V2IsUndef && (isSHUFPMask(M, VT, /* Commuted */ true)))
7420 return CommuteVectorShuffle(SVOp, DAG);
7422 // The checks below are all present in isShuffleMaskLegal, but they are
7423 // inlined here right now to enable us to directly emit target specific
7424 // nodes, and remove one by one until they don't return Op anymore.
7426 if (ShuffleVectorSDNode::isSplatMask(&M[0], VT) &&
7427 SVOp->getSplatIndex() == 0 && V2IsUndef) {
7428 if (VT == MVT::v2f64 || VT == MVT::v2i64)
7429 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
7432 if (isPSHUFHWMask(M, VT, HasInt256))
7433 return getTargetShuffleNode(X86ISD::PSHUFHW, dl, VT, V1,
7434 getShufflePSHUFHWImmediate(SVOp),
7437 if (isPSHUFLWMask(M, VT, HasInt256))
7438 return getTargetShuffleNode(X86ISD::PSHUFLW, dl, VT, V1,
7439 getShufflePSHUFLWImmediate(SVOp),
7442 if (isSHUFPMask(M, VT))
7443 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V2,
7444 getShuffleSHUFImmediate(SVOp), DAG);
7446 if (isUNPCKL_v_undef_Mask(M, VT, HasInt256))
7447 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
7448 if (isUNPCKH_v_undef_Mask(M, VT, HasInt256))
7449 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
7451 //===--------------------------------------------------------------------===//
7452 // Generate target specific nodes for 128 or 256-bit shuffles only
7453 // supported in the AVX instruction set.
7456 // Handle VMOVDDUPY permutations
7457 if (V2IsUndef && isMOVDDUPYMask(M, VT, HasFp256))
7458 return getTargetShuffleNode(X86ISD::MOVDDUP, dl, VT, V1, DAG);
7460 // Handle VPERMILPS/D* permutations
7461 if (isVPERMILPMask(M, VT)) {
7462 if ((HasInt256 && VT == MVT::v8i32) || VT == MVT::v16i32)
7463 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1,
7464 getShuffleSHUFImmediate(SVOp), DAG);
7465 return getTargetShuffleNode(X86ISD::VPERMILP, dl, VT, V1,
7466 getShuffleSHUFImmediate(SVOp), DAG);
7469 // Handle VPERM2F128/VPERM2I128 permutations
7470 if (isVPERM2X128Mask(M, VT, HasFp256))
7471 return getTargetShuffleNode(X86ISD::VPERM2X128, dl, VT, V1,
7472 V2, getShuffleVPERM2X128Immediate(SVOp), DAG);
7474 SDValue BlendOp = LowerVECTOR_SHUFFLEtoBlend(SVOp, Subtarget, DAG);
7475 if (BlendOp.getNode())
7479 if (V2IsUndef && HasInt256 && isPermImmMask(M, VT, Imm8))
7480 return getTargetShuffleNode(X86ISD::VPERMI, dl, VT, V1, Imm8, DAG);
7482 if ((V2IsUndef && HasInt256 && VT.is256BitVector() && NumElems == 8) ||
7483 VT.is512BitVector()) {
7484 MVT MaskEltVT = MVT::getIntegerVT(VT.getVectorElementType().getSizeInBits());
7485 MVT MaskVectorVT = MVT::getVectorVT(MaskEltVT, NumElems);
7486 SmallVector<SDValue, 16> permclMask;
7487 for (unsigned i = 0; i != NumElems; ++i) {
7488 permclMask.push_back(DAG.getConstant((M[i]>=0) ? M[i] : 0, MaskEltVT));
7491 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVectorVT,
7492 &permclMask[0], NumElems);
7494 // Bitcast is for VPERMPS since mask is v8i32 but node takes v8f32
7495 return DAG.getNode(X86ISD::VPERMV, dl, VT,
7496 DAG.getNode(ISD::BITCAST, dl, VT, Mask), V1);
7497 return DAG.getNode(X86ISD::VPERMV3, dl, VT,
7498 DAG.getNode(ISD::BITCAST, dl, VT, Mask), V1, V2);
7501 //===--------------------------------------------------------------------===//
7502 // Since no target specific shuffle was selected for this generic one,
7503 // lower it into other known shuffles. FIXME: this isn't true yet, but
7504 // this is the plan.
7507 // Handle v8i16 specifically since SSE can do byte extraction and insertion.
7508 if (VT == MVT::v8i16) {
7509 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(Op, Subtarget, DAG);
7510 if (NewOp.getNode())
7514 if (VT == MVT::v16i8) {
7515 SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(SVOp, Subtarget, DAG);
7516 if (NewOp.getNode())
7520 if (VT == MVT::v32i8) {
7521 SDValue NewOp = LowerVECTOR_SHUFFLEv32i8(SVOp, Subtarget, DAG);
7522 if (NewOp.getNode())
7526 // Handle all 128-bit wide vectors with 4 elements, and match them with
7527 // several different shuffle types.
7528 if (NumElems == 4 && VT.is128BitVector())
7529 return LowerVECTOR_SHUFFLE_128v4(SVOp, DAG);
7531 // Handle general 256-bit shuffles
7532 if (VT.is256BitVector())
7533 return LowerVECTOR_SHUFFLE_256(SVOp, DAG);
7538 static SDValue LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) {
7539 MVT VT = Op.getSimpleValueType();
7542 if (!Op.getOperand(0).getSimpleValueType().is128BitVector())
7545 if (VT.getSizeInBits() == 8) {
7546 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
7547 Op.getOperand(0), Op.getOperand(1));
7548 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
7549 DAG.getValueType(VT));
7550 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
7553 if (VT.getSizeInBits() == 16) {
7554 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
7555 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
7557 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
7558 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
7559 DAG.getNode(ISD::BITCAST, dl,
7563 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
7564 Op.getOperand(0), Op.getOperand(1));
7565 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
7566 DAG.getValueType(VT));
7567 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
7570 if (VT == MVT::f32) {
7571 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
7572 // the result back to FR32 register. It's only worth matching if the
7573 // result has a single use which is a store or a bitcast to i32. And in
7574 // the case of a store, it's not worth it if the index is a constant 0,
7575 // because a MOVSSmr can be used instead, which is smaller and faster.
7576 if (!Op.hasOneUse())
7578 SDNode *User = *Op.getNode()->use_begin();
7579 if ((User->getOpcode() != ISD::STORE ||
7580 (isa<ConstantSDNode>(Op.getOperand(1)) &&
7581 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
7582 (User->getOpcode() != ISD::BITCAST ||
7583 User->getValueType(0) != MVT::i32))
7585 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
7586 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32,
7589 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, Extract);
7592 if (VT == MVT::i32 || VT == MVT::i64) {
7593 // ExtractPS/pextrq works with constant index.
7594 if (isa<ConstantSDNode>(Op.getOperand(1)))
7601 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
7602 SelectionDAG &DAG) const {
7604 SDValue Vec = Op.getOperand(0);
7605 MVT VecVT = Vec.getSimpleValueType();
7606 SDValue Idx = Op.getOperand(1);
7607 if (!isa<ConstantSDNode>(Idx)) {
7608 if (VecVT.is512BitVector() ||
7609 (VecVT.is256BitVector() && Subtarget->hasInt256() &&
7610 VecVT.getVectorElementType().getSizeInBits() == 32)) {
7613 MVT::getIntegerVT(VecVT.getVectorElementType().getSizeInBits());
7614 MVT MaskVT = MVT::getVectorVT(MaskEltVT, VecVT.getSizeInBits() /
7615 MaskEltVT.getSizeInBits());
7617 if (Idx.getSimpleValueType() != MaskEltVT)
7618 if (Idx.getOpcode() == ISD::ZERO_EXTEND ||
7619 Idx.getOpcode() == ISD::SIGN_EXTEND)
7620 Idx = Idx.getOperand(0);
7621 assert(Idx.getSimpleValueType() == MaskEltVT &&
7622 "Unexpected index in insertelement");
7623 SDValue Mask = DAG.getNode(X86ISD::VINSERT, dl, MaskVT,
7624 getZeroVector(MaskVT, Subtarget, DAG, dl),
7625 Idx, DAG.getConstant(0, getPointerTy()));
7626 SDValue Perm = DAG.getNode(X86ISD::VPERMV, dl, VecVT, Mask, Vec);
7627 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(),
7628 Perm, DAG.getConstant(0, getPointerTy()));
7633 // If this is a 256-bit vector result, first extract the 128-bit vector and
7634 // then extract the element from the 128-bit vector.
7635 if (VecVT.is256BitVector() || VecVT.is512BitVector()) {
7637 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
7638 // Get the 128-bit vector.
7639 Vec = Extract128BitVector(Vec, IdxVal, DAG, dl);
7640 MVT EltVT = VecVT.getVectorElementType();
7642 unsigned ElemsPerChunk = 128 / EltVT.getSizeInBits();
7644 //if (IdxVal >= NumElems/2)
7645 // IdxVal -= NumElems/2;
7646 IdxVal -= (IdxVal/ElemsPerChunk)*ElemsPerChunk;
7647 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec,
7648 DAG.getConstant(IdxVal, MVT::i32));
7651 assert(VecVT.is128BitVector() && "Unexpected vector length");
7653 if (Subtarget->hasSSE41()) {
7654 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG);
7659 MVT VT = Op.getSimpleValueType();
7660 // TODO: handle v16i8.
7661 if (VT.getSizeInBits() == 16) {
7662 SDValue Vec = Op.getOperand(0);
7663 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
7665 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
7666 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
7667 DAG.getNode(ISD::BITCAST, dl,
7670 // Transform it so it match pextrw which produces a 32-bit result.
7671 MVT EltVT = MVT::i32;
7672 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
7673 Op.getOperand(0), Op.getOperand(1));
7674 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
7675 DAG.getValueType(VT));
7676 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
7679 if (VT.getSizeInBits() == 32) {
7680 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
7684 // SHUFPS the element to the lowest double word, then movss.
7685 int Mask[4] = { static_cast<int>(Idx), -1, -1, -1 };
7686 MVT VVT = Op.getOperand(0).getSimpleValueType();
7687 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
7688 DAG.getUNDEF(VVT), Mask);
7689 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
7690 DAG.getIntPtrConstant(0));
7693 if (VT.getSizeInBits() == 64) {
7694 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
7695 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
7696 // to match extract_elt for f64.
7697 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
7701 // UNPCKHPD the element to the lowest double word, then movsd.
7702 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
7703 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
7704 int Mask[2] = { 1, -1 };
7705 MVT VVT = Op.getOperand(0).getSimpleValueType();
7706 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
7707 DAG.getUNDEF(VVT), Mask);
7708 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
7709 DAG.getIntPtrConstant(0));
7715 static SDValue LowerINSERT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) {
7716 MVT VT = Op.getSimpleValueType();
7717 MVT EltVT = VT.getVectorElementType();
7720 SDValue N0 = Op.getOperand(0);
7721 SDValue N1 = Op.getOperand(1);
7722 SDValue N2 = Op.getOperand(2);
7724 if (!VT.is128BitVector())
7727 if ((EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) &&
7728 isa<ConstantSDNode>(N2)) {
7730 if (VT == MVT::v8i16)
7731 Opc = X86ISD::PINSRW;
7732 else if (VT == MVT::v16i8)
7733 Opc = X86ISD::PINSRB;
7735 Opc = X86ISD::PINSRB;
7737 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
7739 if (N1.getValueType() != MVT::i32)
7740 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
7741 if (N2.getValueType() != MVT::i32)
7742 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
7743 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
7746 if (EltVT == MVT::f32 && isa<ConstantSDNode>(N2)) {
7747 // Bits [7:6] of the constant are the source select. This will always be
7748 // zero here. The DAG Combiner may combine an extract_elt index into these
7749 // bits. For example (insert (extract, 3), 2) could be matched by putting
7750 // the '3' into bits [7:6] of X86ISD::INSERTPS.
7751 // Bits [5:4] of the constant are the destination select. This is the
7752 // value of the incoming immediate.
7753 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
7754 // combine either bitwise AND or insert of float 0.0 to set these bits.
7755 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue() << 4);
7756 // Create this as a scalar to vector..
7757 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
7758 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
7761 if ((EltVT == MVT::i32 || EltVT == MVT::i64) && isa<ConstantSDNode>(N2)) {
7762 // PINSR* works with constant index.
7769 X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const {
7770 MVT VT = Op.getSimpleValueType();
7771 MVT EltVT = VT.getVectorElementType();
7774 SDValue N0 = Op.getOperand(0);
7775 SDValue N1 = Op.getOperand(1);
7776 SDValue N2 = Op.getOperand(2);
7778 // If this is a 256-bit vector result, first extract the 128-bit vector,
7779 // insert the element into the extracted half and then place it back.
7780 if (VT.is256BitVector() || VT.is512BitVector()) {
7781 if (!isa<ConstantSDNode>(N2))
7784 // Get the desired 128-bit vector half.
7785 unsigned IdxVal = cast<ConstantSDNode>(N2)->getZExtValue();
7786 SDValue V = Extract128BitVector(N0, IdxVal, DAG, dl);
7788 // Insert the element into the desired half.
7789 unsigned NumEltsIn128 = 128/EltVT.getSizeInBits();
7790 unsigned IdxIn128 = IdxVal - (IdxVal/NumEltsIn128) * NumEltsIn128;
7792 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V, N1,
7793 DAG.getConstant(IdxIn128, MVT::i32));
7795 // Insert the changed part back to the 256-bit vector
7796 return Insert128BitVector(N0, V, IdxVal, DAG, dl);
7799 if (Subtarget->hasSSE41())
7800 return LowerINSERT_VECTOR_ELT_SSE4(Op, DAG);
7802 if (EltVT == MVT::i8)
7805 if (EltVT.getSizeInBits() == 16 && isa<ConstantSDNode>(N2)) {
7806 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
7807 // as its second argument.
7808 if (N1.getValueType() != MVT::i32)
7809 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
7810 if (N2.getValueType() != MVT::i32)
7811 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
7812 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);
7817 static SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) {
7819 MVT OpVT = Op.getSimpleValueType();
7821 // If this is a 256-bit vector result, first insert into a 128-bit
7822 // vector and then insert into the 256-bit vector.
7823 if (!OpVT.is128BitVector()) {
7824 // Insert into a 128-bit vector.
7825 unsigned SizeFactor = OpVT.getSizeInBits()/128;
7826 MVT VT128 = MVT::getVectorVT(OpVT.getVectorElementType(),
7827 OpVT.getVectorNumElements() / SizeFactor);
7829 Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Op.getOperand(0));
7831 // Insert the 128-bit vector.
7832 return Insert128BitVector(DAG.getUNDEF(OpVT), Op, 0, DAG, dl);
7835 if (OpVT == MVT::v1i64 &&
7836 Op.getOperand(0).getValueType() == MVT::i64)
7837 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
7839 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
7840 assert(OpVT.is128BitVector() && "Expected an SSE type!");
7841 return DAG.getNode(ISD::BITCAST, dl, OpVT,
7842 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,AnyExt));
7845 // Lower a node with an EXTRACT_SUBVECTOR opcode. This may result in
7846 // a simple subregister reference or explicit instructions to grab
7847 // upper bits of a vector.
7848 static SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
7849 SelectionDAG &DAG) {
7851 SDValue In = Op.getOperand(0);
7852 SDValue Idx = Op.getOperand(1);
7853 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
7854 MVT ResVT = Op.getSimpleValueType();
7855 MVT InVT = In.getSimpleValueType();
7857 if (Subtarget->hasFp256()) {
7858 if (ResVT.is128BitVector() &&
7859 (InVT.is256BitVector() || InVT.is512BitVector()) &&
7860 isa<ConstantSDNode>(Idx)) {
7861 return Extract128BitVector(In, IdxVal, DAG, dl);
7863 if (ResVT.is256BitVector() && InVT.is512BitVector() &&
7864 isa<ConstantSDNode>(Idx)) {
7865 return Extract256BitVector(In, IdxVal, DAG, dl);
7871 // Lower a node with an INSERT_SUBVECTOR opcode. This may result in a
7872 // simple superregister reference or explicit instructions to insert
7873 // the upper bits of a vector.
7874 static SDValue LowerINSERT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
7875 SelectionDAG &DAG) {
7876 if (Subtarget->hasFp256()) {
7877 SDLoc dl(Op.getNode());
7878 SDValue Vec = Op.getNode()->getOperand(0);
7879 SDValue SubVec = Op.getNode()->getOperand(1);
7880 SDValue Idx = Op.getNode()->getOperand(2);
7882 if ((Op.getNode()->getSimpleValueType(0).is256BitVector() ||
7883 Op.getNode()->getSimpleValueType(0).is512BitVector()) &&
7884 SubVec.getNode()->getSimpleValueType(0).is128BitVector() &&
7885 isa<ConstantSDNode>(Idx)) {
7886 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
7887 return Insert128BitVector(Vec, SubVec, IdxVal, DAG, dl);
7890 if (Op.getNode()->getSimpleValueType(0).is512BitVector() &&
7891 SubVec.getNode()->getSimpleValueType(0).is256BitVector() &&
7892 isa<ConstantSDNode>(Idx)) {
7893 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
7894 return Insert256BitVector(Vec, SubVec, IdxVal, DAG, dl);
7900 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
7901 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
7902 // one of the above mentioned nodes. It has to be wrapped because otherwise
7903 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
7904 // be used to form addressing mode. These wrapped nodes will be selected
7907 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
7908 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
7910 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
7912 unsigned char OpFlag = 0;
7913 unsigned WrapperKind = X86ISD::Wrapper;
7914 CodeModel::Model M = getTargetMachine().getCodeModel();
7916 if (Subtarget->isPICStyleRIPRel() &&
7917 (M == CodeModel::Small || M == CodeModel::Kernel))
7918 WrapperKind = X86ISD::WrapperRIP;
7919 else if (Subtarget->isPICStyleGOT())
7920 OpFlag = X86II::MO_GOTOFF;
7921 else if (Subtarget->isPICStyleStubPIC())
7922 OpFlag = X86II::MO_PIC_BASE_OFFSET;
7924 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(),
7926 CP->getOffset(), OpFlag);
7928 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
7929 // With PIC, the address is actually $g + Offset.
7931 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7932 DAG.getNode(X86ISD::GlobalBaseReg,
7933 SDLoc(), getPointerTy()),
7940 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
7941 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
7943 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
7945 unsigned char OpFlag = 0;
7946 unsigned WrapperKind = X86ISD::Wrapper;
7947 CodeModel::Model M = getTargetMachine().getCodeModel();
7949 if (Subtarget->isPICStyleRIPRel() &&
7950 (M == CodeModel::Small || M == CodeModel::Kernel))
7951 WrapperKind = X86ISD::WrapperRIP;
7952 else if (Subtarget->isPICStyleGOT())
7953 OpFlag = X86II::MO_GOTOFF;
7954 else if (Subtarget->isPICStyleStubPIC())
7955 OpFlag = X86II::MO_PIC_BASE_OFFSET;
7957 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(),
7960 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
7962 // With PIC, the address is actually $g + Offset.
7964 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7965 DAG.getNode(X86ISD::GlobalBaseReg,
7966 SDLoc(), getPointerTy()),
7973 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const {
7974 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
7976 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
7978 unsigned char OpFlag = 0;
7979 unsigned WrapperKind = X86ISD::Wrapper;
7980 CodeModel::Model M = getTargetMachine().getCodeModel();
7982 if (Subtarget->isPICStyleRIPRel() &&
7983 (M == CodeModel::Small || M == CodeModel::Kernel)) {
7984 if (Subtarget->isTargetDarwin() || Subtarget->isTargetELF())
7985 OpFlag = X86II::MO_GOTPCREL;
7986 WrapperKind = X86ISD::WrapperRIP;
7987 } else if (Subtarget->isPICStyleGOT()) {
7988 OpFlag = X86II::MO_GOT;
7989 } else if (Subtarget->isPICStyleStubPIC()) {
7990 OpFlag = X86II::MO_DARWIN_NONLAZY_PIC_BASE;
7991 } else if (Subtarget->isPICStyleStubNoDynamic()) {
7992 OpFlag = X86II::MO_DARWIN_NONLAZY;
7995 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag);
7998 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
8000 // With PIC, the address is actually $g + Offset.
8001 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
8002 !Subtarget->is64Bit()) {
8003 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
8004 DAG.getNode(X86ISD::GlobalBaseReg,
8005 SDLoc(), getPointerTy()),
8009 // For symbols that require a load from a stub to get the address, emit the
8011 if (isGlobalStubReference(OpFlag))
8012 Result = DAG.getLoad(getPointerTy(), DL, DAG.getEntryNode(), Result,
8013 MachinePointerInfo::getGOT(), false, false, false, 0);
8019 X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
8020 // Create the TargetBlockAddressAddress node.
8021 unsigned char OpFlags =
8022 Subtarget->ClassifyBlockAddressReference();
8023 CodeModel::Model M = getTargetMachine().getCodeModel();
8024 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
8025 int64_t Offset = cast<BlockAddressSDNode>(Op)->getOffset();
8027 SDValue Result = DAG.getTargetBlockAddress(BA, getPointerTy(), Offset,
8030 if (Subtarget->isPICStyleRIPRel() &&
8031 (M == CodeModel::Small || M == CodeModel::Kernel))
8032 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
8034 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
8036 // With PIC, the address is actually $g + Offset.
8037 if (isGlobalRelativeToPICBase(OpFlags)) {
8038 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
8039 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
8047 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, SDLoc dl,
8048 int64_t Offset, SelectionDAG &DAG) const {
8049 // Create the TargetGlobalAddress node, folding in the constant
8050 // offset if it is legal.
8051 unsigned char OpFlags =
8052 Subtarget->ClassifyGlobalReference(GV, getTargetMachine());
8053 CodeModel::Model M = getTargetMachine().getCodeModel();
8055 if (OpFlags == X86II::MO_NO_FLAG &&
8056 X86::isOffsetSuitableForCodeModel(Offset, M)) {
8057 // A direct static reference to a global.
8058 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), Offset);
8061 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags);
8064 if (Subtarget->isPICStyleRIPRel() &&
8065 (M == CodeModel::Small || M == CodeModel::Kernel))
8066 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
8068 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
8070 // With PIC, the address is actually $g + Offset.
8071 if (isGlobalRelativeToPICBase(OpFlags)) {
8072 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
8073 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
8077 // For globals that require a load from a stub to get the address, emit the
8079 if (isGlobalStubReference(OpFlags))
8080 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result,
8081 MachinePointerInfo::getGOT(), false, false, false, 0);
8083 // If there was a non-zero offset that we didn't fold, create an explicit
8086 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result,
8087 DAG.getConstant(Offset, getPointerTy()));
8093 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
8094 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
8095 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
8096 return LowerGlobalAddress(GV, SDLoc(Op), Offset, DAG);
8100 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
8101 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg,
8102 unsigned char OperandFlags, bool LocalDynamic = false) {
8103 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
8104 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
8106 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
8107 GA->getValueType(0),
8111 X86ISD::NodeType CallType = LocalDynamic ? X86ISD::TLSBASEADDR
8115 SDValue Ops[] = { Chain, TGA, *InFlag };
8116 Chain = DAG.getNode(CallType, dl, NodeTys, Ops, array_lengthof(Ops));
8118 SDValue Ops[] = { Chain, TGA };
8119 Chain = DAG.getNode(CallType, dl, NodeTys, Ops, array_lengthof(Ops));
8122 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
8123 MFI->setAdjustsStack(true);
8125 SDValue Flag = Chain.getValue(1);
8126 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
8129 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
8131 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
8134 SDLoc dl(GA); // ? function entry point might be better
8135 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
8136 DAG.getNode(X86ISD::GlobalBaseReg,
8137 SDLoc(), PtrVT), InFlag);
8138 InFlag = Chain.getValue(1);
8140 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
8143 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
8145 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
8147 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, NULL, PtrVT,
8148 X86::RAX, X86II::MO_TLSGD);
8151 static SDValue LowerToTLSLocalDynamicModel(GlobalAddressSDNode *GA,
8157 // Get the start address of the TLS block for this module.
8158 X86MachineFunctionInfo* MFI = DAG.getMachineFunction()
8159 .getInfo<X86MachineFunctionInfo>();
8160 MFI->incNumLocalDynamicTLSAccesses();
8164 Base = GetTLSADDR(DAG, DAG.getEntryNode(), GA, NULL, PtrVT, X86::RAX,
8165 X86II::MO_TLSLD, /*LocalDynamic=*/true);
8168 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
8169 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), InFlag);
8170 InFlag = Chain.getValue(1);
8171 Base = GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX,
8172 X86II::MO_TLSLDM, /*LocalDynamic=*/true);
8175 // Note: the CleanupLocalDynamicTLSPass will remove redundant computations
8179 unsigned char OperandFlags = X86II::MO_DTPOFF;
8180 unsigned WrapperKind = X86ISD::Wrapper;
8181 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
8182 GA->getValueType(0),
8183 GA->getOffset(), OperandFlags);
8184 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
8186 // Add x@dtpoff with the base.
8187 return DAG.getNode(ISD::ADD, dl, PtrVT, Offset, Base);
8190 // Lower ISD::GlobalTLSAddress using the "initial exec" or "local exec" model.
8191 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
8192 const EVT PtrVT, TLSModel::Model model,
8193 bool is64Bit, bool isPIC) {
8196 // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit).
8197 Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(*DAG.getContext(),
8198 is64Bit ? 257 : 256));
8200 SDValue ThreadPointer = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
8201 DAG.getIntPtrConstant(0),
8202 MachinePointerInfo(Ptr),
8203 false, false, false, 0);
8205 unsigned char OperandFlags = 0;
8206 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
8208 unsigned WrapperKind = X86ISD::Wrapper;
8209 if (model == TLSModel::LocalExec) {
8210 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
8211 } else if (model == TLSModel::InitialExec) {
8213 OperandFlags = X86II::MO_GOTTPOFF;
8214 WrapperKind = X86ISD::WrapperRIP;
8216 OperandFlags = isPIC ? X86II::MO_GOTNTPOFF : X86II::MO_INDNTPOFF;
8219 llvm_unreachable("Unexpected model");
8222 // emit "addl x@ntpoff,%eax" (local exec)
8223 // or "addl x@indntpoff,%eax" (initial exec)
8224 // or "addl x@gotntpoff(%ebx) ,%eax" (initial exec, 32-bit pic)
8225 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
8226 GA->getValueType(0),
8227 GA->getOffset(), OperandFlags);
8228 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
8230 if (model == TLSModel::InitialExec) {
8231 if (isPIC && !is64Bit) {
8232 Offset = DAG.getNode(ISD::ADD, dl, PtrVT,
8233 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT),
8237 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
8238 MachinePointerInfo::getGOT(), false, false, false,
8242 // The address of the thread local variable is the add of the thread
8243 // pointer with the offset of the variable.
8244 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
8248 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
8250 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
8251 const GlobalValue *GV = GA->getGlobal();
8253 if (Subtarget->isTargetELF()) {
8254 TLSModel::Model model = getTargetMachine().getTLSModel(GV);
8257 case TLSModel::GeneralDynamic:
8258 if (Subtarget->is64Bit())
8259 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy());
8260 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy());
8261 case TLSModel::LocalDynamic:
8262 return LowerToTLSLocalDynamicModel(GA, DAG, getPointerTy(),
8263 Subtarget->is64Bit());
8264 case TLSModel::InitialExec:
8265 case TLSModel::LocalExec:
8266 return LowerToTLSExecModel(GA, DAG, getPointerTy(), model,
8267 Subtarget->is64Bit(),
8268 getTargetMachine().getRelocationModel() == Reloc::PIC_);
8270 llvm_unreachable("Unknown TLS model.");
8273 if (Subtarget->isTargetDarwin()) {
8274 // Darwin only has one model of TLS. Lower to that.
8275 unsigned char OpFlag = 0;
8276 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ?
8277 X86ISD::WrapperRIP : X86ISD::Wrapper;
8279 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
8281 bool PIC32 = (getTargetMachine().getRelocationModel() == Reloc::PIC_) &&
8282 !Subtarget->is64Bit();
8284 OpFlag = X86II::MO_TLVP_PIC_BASE;
8286 OpFlag = X86II::MO_TLVP;
8288 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL,
8289 GA->getValueType(0),
8290 GA->getOffset(), OpFlag);
8291 SDValue Offset = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
8293 // With PIC32, the address is actually $g + Offset.
8295 Offset = DAG.getNode(ISD::ADD, DL, getPointerTy(),
8296 DAG.getNode(X86ISD::GlobalBaseReg,
8297 SDLoc(), getPointerTy()),
8300 // Lowering the machine isd will make sure everything is in the right
8302 SDValue Chain = DAG.getEntryNode();
8303 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
8304 SDValue Args[] = { Chain, Offset };
8305 Chain = DAG.getNode(X86ISD::TLSCALL, DL, NodeTys, Args, 2);
8307 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls.
8308 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
8309 MFI->setAdjustsStack(true);
8311 // And our return value (tls address) is in the standard call return value
8313 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
8314 return DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(),
8318 if (Subtarget->isTargetWindows() || Subtarget->isTargetMingw()) {
8319 // Just use the implicit TLS architecture
8320 // Need to generate someting similar to:
8321 // mov rdx, qword [gs:abs 58H]; Load pointer to ThreadLocalStorage
8323 // mov ecx, dword [rel _tls_index]: Load index (from C runtime)
8324 // mov rcx, qword [rdx+rcx*8]
8325 // mov eax, .tls$:tlsvar
8326 // [rax+rcx] contains the address
8327 // Windows 64bit: gs:0x58
8328 // Windows 32bit: fs:__tls_array
8330 // If GV is an alias then use the aliasee for determining
8331 // thread-localness.
8332 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV))
8333 GV = GA->resolveAliasedGlobal(false);
8335 SDValue Chain = DAG.getEntryNode();
8337 // Get the Thread Pointer, which is %fs:__tls_array (32-bit) or
8338 // %gs:0x58 (64-bit). On MinGW, __tls_array is not available, so directly
8339 // use its literal value of 0x2C.
8340 Value *Ptr = Constant::getNullValue(Subtarget->is64Bit()
8341 ? Type::getInt8PtrTy(*DAG.getContext(),
8343 : Type::getInt32PtrTy(*DAG.getContext(),
8346 SDValue TlsArray = Subtarget->is64Bit() ? DAG.getIntPtrConstant(0x58) :
8347 (Subtarget->isTargetMingw() ? DAG.getIntPtrConstant(0x2C) :
8348 DAG.getExternalSymbol("_tls_array", getPointerTy()));
8350 SDValue ThreadPointer = DAG.getLoad(getPointerTy(), dl, Chain, TlsArray,
8351 MachinePointerInfo(Ptr),
8352 false, false, false, 0);
8354 // Load the _tls_index variable
8355 SDValue IDX = DAG.getExternalSymbol("_tls_index", getPointerTy());
8356 if (Subtarget->is64Bit())
8357 IDX = DAG.getExtLoad(ISD::ZEXTLOAD, dl, getPointerTy(), Chain,
8358 IDX, MachinePointerInfo(), MVT::i32,
8361 IDX = DAG.getLoad(getPointerTy(), dl, Chain, IDX, MachinePointerInfo(),
8362 false, false, false, 0);
8364 SDValue Scale = DAG.getConstant(Log2_64_Ceil(TD->getPointerSize()),
8366 IDX = DAG.getNode(ISD::SHL, dl, getPointerTy(), IDX, Scale);
8368 SDValue res = DAG.getNode(ISD::ADD, dl, getPointerTy(), ThreadPointer, IDX);
8369 res = DAG.getLoad(getPointerTy(), dl, Chain, res, MachinePointerInfo(),
8370 false, false, false, 0);
8372 // Get the offset of start of .tls section
8373 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
8374 GA->getValueType(0),
8375 GA->getOffset(), X86II::MO_SECREL);
8376 SDValue Offset = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), TGA);
8378 // The address of the thread local variable is the add of the thread
8379 // pointer with the offset of the variable.
8380 return DAG.getNode(ISD::ADD, dl, getPointerTy(), res, Offset);
8383 llvm_unreachable("TLS not implemented for this target.");
8386 /// LowerShiftParts - Lower SRA_PARTS and friends, which return two i32 values
8387 /// and take a 2 x i32 value to shift plus a shift amount.
8388 SDValue X86TargetLowering::LowerShiftParts(SDValue Op, SelectionDAG &DAG) const{
8389 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
8390 EVT VT = Op.getValueType();
8391 unsigned VTBits = VT.getSizeInBits();
8393 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
8394 SDValue ShOpLo = Op.getOperand(0);
8395 SDValue ShOpHi = Op.getOperand(1);
8396 SDValue ShAmt = Op.getOperand(2);
8397 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
8398 DAG.getConstant(VTBits - 1, MVT::i8))
8399 : DAG.getConstant(0, VT);
8402 if (Op.getOpcode() == ISD::SHL_PARTS) {
8403 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
8404 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
8406 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
8407 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, ShAmt);
8410 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
8411 DAG.getConstant(VTBits, MVT::i8));
8412 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
8413 AndNode, DAG.getConstant(0, MVT::i8));
8416 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8);
8417 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
8418 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
8420 if (Op.getOpcode() == ISD::SHL_PARTS) {
8421 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
8422 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
8424 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
8425 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
8428 SDValue Ops[2] = { Lo, Hi };
8429 return DAG.getMergeValues(Ops, array_lengthof(Ops), dl);
8432 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op,
8433 SelectionDAG &DAG) const {
8434 EVT SrcVT = Op.getOperand(0).getValueType();
8436 if (SrcVT.isVector())
8439 assert(SrcVT.getSimpleVT() <= MVT::i64 && SrcVT.getSimpleVT() >= MVT::i16 &&
8440 "Unknown SINT_TO_FP to lower!");
8442 // These are really Legal; return the operand so the caller accepts it as
8444 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
8446 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
8447 Subtarget->is64Bit()) {
8452 unsigned Size = SrcVT.getSizeInBits()/8;
8453 MachineFunction &MF = DAG.getMachineFunction();
8454 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false);
8455 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
8456 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
8458 MachinePointerInfo::getFixedStack(SSFI),
8460 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
8463 SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
8465 SelectionDAG &DAG) const {
8469 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
8471 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Glue);
8473 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
8475 unsigned ByteSize = SrcVT.getSizeInBits()/8;
8477 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(StackSlot);
8478 MachineMemOperand *MMO;
8480 int SSFI = FI->getIndex();
8482 DAG.getMachineFunction()
8483 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
8484 MachineMemOperand::MOLoad, ByteSize, ByteSize);
8486 MMO = cast<LoadSDNode>(StackSlot)->getMemOperand();
8487 StackSlot = StackSlot.getOperand(1);
8489 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) };
8490 SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG :
8492 Tys, Ops, array_lengthof(Ops),
8496 Chain = Result.getValue(1);
8497 SDValue InFlag = Result.getValue(2);
8499 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
8500 // shouldn't be necessary except that RFP cannot be live across
8501 // multiple blocks. When stackifier is fixed, they can be uncoupled.
8502 MachineFunction &MF = DAG.getMachineFunction();
8503 unsigned SSFISize = Op.getValueType().getSizeInBits()/8;
8504 int SSFI = MF.getFrameInfo()->CreateStackObject(SSFISize, SSFISize, false);
8505 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
8506 Tys = DAG.getVTList(MVT::Other);
8508 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag
8510 MachineMemOperand *MMO =
8511 DAG.getMachineFunction()
8512 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
8513 MachineMemOperand::MOStore, SSFISize, SSFISize);
8515 Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys,
8516 Ops, array_lengthof(Ops),
8517 Op.getValueType(), MMO);
8518 Result = DAG.getLoad(Op.getValueType(), DL, Chain, StackSlot,
8519 MachinePointerInfo::getFixedStack(SSFI),
8520 false, false, false, 0);
8526 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
8527 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op,
8528 SelectionDAG &DAG) const {
8529 // This algorithm is not obvious. Here it is what we're trying to output:
8532 punpckldq (c0), %xmm0 // c0: (uint4){ 0x43300000U, 0x45300000U, 0U, 0U }
8533 subpd (c1), %xmm0 // c1: (double2){ 0x1.0p52, 0x1.0p52 * 0x1.0p32 }
8537 pshufd $0x4e, %xmm0, %xmm1
8543 LLVMContext *Context = DAG.getContext();
8545 // Build some magic constants.
8546 static const uint32_t CV0[] = { 0x43300000, 0x45300000, 0, 0 };
8547 Constant *C0 = ConstantDataVector::get(*Context, CV0);
8548 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16);
8550 SmallVector<Constant*,2> CV1;
8552 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
8553 APInt(64, 0x4330000000000000ULL))));
8555 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
8556 APInt(64, 0x4530000000000000ULL))));
8557 Constant *C1 = ConstantVector::get(CV1);
8558 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16);
8560 // Load the 64-bit value into an XMM register.
8561 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
8563 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
8564 MachinePointerInfo::getConstantPool(),
8565 false, false, false, 16);
8566 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32,
8567 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, XR1),
8570 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
8571 MachinePointerInfo::getConstantPool(),
8572 false, false, false, 16);
8573 SDValue XR2F = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Unpck1);
8574 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
8577 if (Subtarget->hasSSE3()) {
8578 // FIXME: The 'haddpd' instruction may be slower than 'movhlps + addsd'.
8579 Result = DAG.getNode(X86ISD::FHADD, dl, MVT::v2f64, Sub, Sub);
8581 SDValue S2F = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Sub);
8582 SDValue Shuffle = getTargetShuffleNode(X86ISD::PSHUFD, dl, MVT::v4i32,
8584 Result = DAG.getNode(ISD::FADD, dl, MVT::v2f64,
8585 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Shuffle),
8589 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Result,
8590 DAG.getIntPtrConstant(0));
8593 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
8594 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op,
8595 SelectionDAG &DAG) const {
8597 // FP constant to bias correct the final result.
8598 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
8601 // Load the 32-bit value into an XMM register.
8602 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
8605 // Zero out the upper parts of the register.
8606 Load = getShuffleVectorZeroOrUndef(Load, 0, true, Subtarget, DAG);
8608 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
8609 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Load),
8610 DAG.getIntPtrConstant(0));
8612 // Or the load with the bias.
8613 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64,
8614 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
8615 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
8617 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
8618 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
8619 MVT::v2f64, Bias)));
8620 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
8621 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or),
8622 DAG.getIntPtrConstant(0));
8624 // Subtract the bias.
8625 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
8627 // Handle final rounding.
8628 EVT DestVT = Op.getValueType();
8630 if (DestVT.bitsLT(MVT::f64))
8631 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
8632 DAG.getIntPtrConstant(0));
8633 if (DestVT.bitsGT(MVT::f64))
8634 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
8636 // Handle final rounding.
8640 SDValue X86TargetLowering::lowerUINT_TO_FP_vec(SDValue Op,
8641 SelectionDAG &DAG) const {
8642 SDValue N0 = Op.getOperand(0);
8643 EVT SVT = N0.getValueType();
8646 assert((SVT == MVT::v4i8 || SVT == MVT::v4i16 ||
8647 SVT == MVT::v8i8 || SVT == MVT::v8i16) &&
8648 "Custom UINT_TO_FP is not supported!");
8650 EVT NVT = EVT::getVectorVT(*DAG.getContext(), MVT::i32,
8651 SVT.getVectorNumElements());
8652 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
8653 DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, N0));
8656 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op,
8657 SelectionDAG &DAG) const {
8658 SDValue N0 = Op.getOperand(0);
8661 if (Op.getValueType().isVector())
8662 return lowerUINT_TO_FP_vec(Op, DAG);
8664 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't
8665 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
8666 // the optimization here.
8667 if (DAG.SignBitIsZero(N0))
8668 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
8670 EVT SrcVT = N0.getValueType();
8671 EVT DstVT = Op.getValueType();
8672 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64)
8673 return LowerUINT_TO_FP_i64(Op, DAG);
8674 if (SrcVT == MVT::i32 && X86ScalarSSEf64)
8675 return LowerUINT_TO_FP_i32(Op, DAG);
8676 if (Subtarget->is64Bit() && SrcVT == MVT::i64 && DstVT == MVT::f32)
8679 // Make a 64-bit buffer, and use it to build an FILD.
8680 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
8681 if (SrcVT == MVT::i32) {
8682 SDValue WordOff = DAG.getConstant(4, getPointerTy());
8683 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl,
8684 getPointerTy(), StackSlot, WordOff);
8685 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
8686 StackSlot, MachinePointerInfo(),
8688 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32),
8689 OffsetSlot, MachinePointerInfo(),
8691 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
8695 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP");
8696 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
8697 StackSlot, MachinePointerInfo(),
8699 // For i64 source, we need to add the appropriate power of 2 if the input
8700 // was negative. This is the same as the optimization in
8701 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here,
8702 // we must be careful to do the computation in x87 extended precision, not
8703 // in SSE. (The generic code can't know it's OK to do this, or how to.)
8704 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex();
8705 MachineMemOperand *MMO =
8706 DAG.getMachineFunction()
8707 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
8708 MachineMemOperand::MOLoad, 8, 8);
8710 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other);
8711 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) };
8712 SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops,
8713 array_lengthof(Ops), MVT::i64, MMO);
8715 APInt FF(32, 0x5F800000ULL);
8717 // Check whether the sign bit is set.
8718 SDValue SignSet = DAG.getSetCC(dl,
8719 getSetCCResultType(*DAG.getContext(), MVT::i64),
8720 Op.getOperand(0), DAG.getConstant(0, MVT::i64),
8723 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
8724 SDValue FudgePtr = DAG.getConstantPool(
8725 ConstantInt::get(*DAG.getContext(), FF.zext(64)),
8728 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
8729 SDValue Zero = DAG.getIntPtrConstant(0);
8730 SDValue Four = DAG.getIntPtrConstant(4);
8731 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
8733 FudgePtr = DAG.getNode(ISD::ADD, dl, getPointerTy(), FudgePtr, Offset);
8735 // Load the value out, extending it from f32 to f80.
8736 // FIXME: Avoid the extend by constructing the right constant pool?
8737 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, MVT::f80, DAG.getEntryNode(),
8738 FudgePtr, MachinePointerInfo::getConstantPool(),
8739 MVT::f32, false, false, 4);
8740 // Extend everything to 80 bits to force it to be done on x87.
8741 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge);
8742 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add, DAG.getIntPtrConstant(0));
8745 std::pair<SDValue,SDValue>
8746 X86TargetLowering:: FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG,
8747 bool IsSigned, bool IsReplace) const {
8750 EVT DstTy = Op.getValueType();
8752 if (!IsSigned && !isIntegerTypeFTOL(DstTy)) {
8753 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
8757 assert(DstTy.getSimpleVT() <= MVT::i64 &&
8758 DstTy.getSimpleVT() >= MVT::i16 &&
8759 "Unknown FP_TO_INT to lower!");
8761 // These are really Legal.
8762 if (DstTy == MVT::i32 &&
8763 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
8764 return std::make_pair(SDValue(), SDValue());
8765 if (Subtarget->is64Bit() &&
8766 DstTy == MVT::i64 &&
8767 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
8768 return std::make_pair(SDValue(), SDValue());
8770 // We lower FP->int64 either into FISTP64 followed by a load from a temporary
8771 // stack slot, or into the FTOL runtime function.
8772 MachineFunction &MF = DAG.getMachineFunction();
8773 unsigned MemSize = DstTy.getSizeInBits()/8;
8774 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
8775 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
8778 if (!IsSigned && isIntegerTypeFTOL(DstTy))
8779 Opc = X86ISD::WIN_FTOL;
8781 switch (DstTy.getSimpleVT().SimpleTy) {
8782 default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
8783 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
8784 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
8785 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
8788 SDValue Chain = DAG.getEntryNode();
8789 SDValue Value = Op.getOperand(0);
8790 EVT TheVT = Op.getOperand(0).getValueType();
8791 // FIXME This causes a redundant load/store if the SSE-class value is already
8792 // in memory, such as if it is on the callstack.
8793 if (isScalarFPTypeInSSEReg(TheVT)) {
8794 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
8795 Chain = DAG.getStore(Chain, DL, Value, StackSlot,
8796 MachinePointerInfo::getFixedStack(SSFI),
8798 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
8800 Chain, StackSlot, DAG.getValueType(TheVT)
8803 MachineMemOperand *MMO =
8804 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
8805 MachineMemOperand::MOLoad, MemSize, MemSize);
8806 Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops,
8807 array_lengthof(Ops), DstTy, MMO);
8808 Chain = Value.getValue(1);
8809 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
8810 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
8813 MachineMemOperand *MMO =
8814 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
8815 MachineMemOperand::MOStore, MemSize, MemSize);
8817 if (Opc != X86ISD::WIN_FTOL) {
8818 // Build the FP_TO_INT*_IN_MEM
8819 SDValue Ops[] = { Chain, Value, StackSlot };
8820 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
8821 Ops, array_lengthof(Ops), DstTy,
8823 return std::make_pair(FIST, StackSlot);
8825 SDValue ftol = DAG.getNode(X86ISD::WIN_FTOL, DL,
8826 DAG.getVTList(MVT::Other, MVT::Glue),
8828 SDValue eax = DAG.getCopyFromReg(ftol, DL, X86::EAX,
8829 MVT::i32, ftol.getValue(1));
8830 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), DL, X86::EDX,
8831 MVT::i32, eax.getValue(2));
8832 SDValue Ops[] = { eax, edx };
8833 SDValue pair = IsReplace
8834 ? DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops, array_lengthof(Ops))
8835 : DAG.getMergeValues(Ops, array_lengthof(Ops), DL);
8836 return std::make_pair(pair, SDValue());
8840 static SDValue LowerAVXExtend(SDValue Op, SelectionDAG &DAG,
8841 const X86Subtarget *Subtarget) {
8842 MVT VT = Op->getSimpleValueType(0);
8843 SDValue In = Op->getOperand(0);
8844 MVT InVT = In.getSimpleValueType();
8847 // Optimize vectors in AVX mode:
8850 // Use vpunpcklwd for 4 lower elements v8i16 -> v4i32.
8851 // Use vpunpckhwd for 4 upper elements v8i16 -> v4i32.
8852 // Concat upper and lower parts.
8855 // Use vpunpckldq for 4 lower elements v4i32 -> v2i64.
8856 // Use vpunpckhdq for 4 upper elements v4i32 -> v2i64.
8857 // Concat upper and lower parts.
8860 if (((VT != MVT::v8i32) || (InVT != MVT::v8i16)) &&
8861 ((VT != MVT::v4i64) || (InVT != MVT::v4i32)))
8864 if (Subtarget->hasInt256())
8865 return DAG.getNode(X86ISD::VZEXT_MOVL, dl, VT, In);
8867 SDValue ZeroVec = getZeroVector(InVT, Subtarget, DAG, dl);
8868 SDValue Undef = DAG.getUNDEF(InVT);
8869 bool NeedZero = Op.getOpcode() == ISD::ZERO_EXTEND;
8870 SDValue OpLo = getUnpackl(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
8871 SDValue OpHi = getUnpackh(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
8873 MVT HVT = MVT::getVectorVT(VT.getVectorElementType(),
8874 VT.getVectorNumElements()/2);
8876 OpLo = DAG.getNode(ISD::BITCAST, dl, HVT, OpLo);
8877 OpHi = DAG.getNode(ISD::BITCAST, dl, HVT, OpHi);
8879 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
8882 static SDValue LowerZERO_EXTEND_AVX512(SDValue Op,
8883 SelectionDAG &DAG) {
8884 MVT VT = Op->getValueType(0).getSimpleVT();
8885 SDValue In = Op->getOperand(0);
8886 MVT InVT = In.getValueType().getSimpleVT();
8888 unsigned int NumElts = VT.getVectorNumElements();
8889 if (NumElts != 8 && NumElts != 16)
8892 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1)
8893 return DAG.getNode(X86ISD::VZEXT, DL, VT, In);
8895 EVT ExtVT = (NumElts == 8)? MVT::v8i64 : MVT::v16i32;
8896 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
8897 // Now we have only mask extension
8898 assert(InVT.getVectorElementType() == MVT::i1);
8899 SDValue Cst = DAG.getTargetConstant(1, ExtVT.getScalarType());
8900 const Constant *C = (dyn_cast<ConstantSDNode>(Cst))->getConstantIntValue();
8901 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
8902 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
8903 SDValue Ld = DAG.getLoad(Cst.getValueType(), DL, DAG.getEntryNode(), CP,
8904 MachinePointerInfo::getConstantPool(),
8905 false, false, false, Alignment);
8907 SDValue Brcst = DAG.getNode(X86ISD::VBROADCASTM, DL, ExtVT, In, Ld);
8908 if (VT.is512BitVector())
8910 return DAG.getNode(X86ISD::VTRUNC, DL, VT, Brcst);
8913 static SDValue LowerANY_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
8914 SelectionDAG &DAG) {
8915 if (Subtarget->hasFp256()) {
8916 SDValue Res = LowerAVXExtend(Op, DAG, Subtarget);
8924 static SDValue LowerZERO_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
8925 SelectionDAG &DAG) {
8927 MVT VT = Op.getSimpleValueType();
8928 SDValue In = Op.getOperand(0);
8929 MVT SVT = In.getSimpleValueType();
8931 if (VT.is512BitVector() || SVT.getVectorElementType() == MVT::i1)
8932 return LowerZERO_EXTEND_AVX512(Op, DAG);
8934 if (Subtarget->hasFp256()) {
8935 SDValue Res = LowerAVXExtend(Op, DAG, Subtarget);
8940 if (!VT.is256BitVector() || !SVT.is128BitVector() ||
8941 VT.getVectorNumElements() != SVT.getVectorNumElements())
8944 assert(Subtarget->hasFp256() && "256-bit vector is observed without AVX!");
8946 // AVX2 has better support of integer extending.
8947 if (Subtarget->hasInt256())
8948 return DAG.getNode(X86ISD::VZEXT, DL, VT, In);
8950 SDValue Lo = DAG.getNode(X86ISD::VZEXT, DL, MVT::v4i32, In);
8951 static const int Mask[] = {4, 5, 6, 7, -1, -1, -1, -1};
8952 SDValue Hi = DAG.getNode(X86ISD::VZEXT, DL, MVT::v4i32,
8953 DAG.getVectorShuffle(MVT::v8i16, DL, In,
8954 DAG.getUNDEF(MVT::v8i16),
8957 return DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v8i32, Lo, Hi);
8960 SDValue X86TargetLowering::LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const {
8962 MVT VT = Op.getSimpleValueType();
8963 SDValue In = Op.getOperand(0);
8964 MVT InVT = In.getSimpleValueType();
8965 assert(VT.getVectorNumElements() == InVT.getVectorNumElements() &&
8966 "Invalid TRUNCATE operation");
8968 if (InVT.is512BitVector() || VT.getVectorElementType() == MVT::i1) {
8969 if (VT.getVectorElementType().getSizeInBits() >=8)
8970 return DAG.getNode(X86ISD::VTRUNC, DL, VT, In);
8972 assert(VT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
8973 unsigned NumElts = InVT.getVectorNumElements();
8974 assert ((NumElts == 8 || NumElts == 16) && "Unexpected vector type");
8975 if (InVT.getSizeInBits() < 512) {
8976 MVT ExtVT = (NumElts == 16)? MVT::v16i32 : MVT::v8i64;
8977 In = DAG.getNode(ISD::SIGN_EXTEND, DL, ExtVT, In);
8980 SDValue Cst = DAG.getTargetConstant(1, InVT.getVectorElementType());
8981 const Constant *C = (dyn_cast<ConstantSDNode>(Cst))->getConstantIntValue();
8982 SDValue CP = DAG.getConstantPool(C, getPointerTy());
8983 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
8984 SDValue Ld = DAG.getLoad(Cst.getValueType(), DL, DAG.getEntryNode(), CP,
8985 MachinePointerInfo::getConstantPool(),
8986 false, false, false, Alignment);
8987 SDValue OneV = DAG.getNode(X86ISD::VBROADCAST, DL, InVT, Ld);
8988 SDValue And = DAG.getNode(ISD::AND, DL, InVT, OneV, In);
8989 return DAG.getNode(X86ISD::TESTM, DL, VT, And, And);
8992 if ((VT == MVT::v4i32) && (InVT == MVT::v4i64)) {
8993 // On AVX2, v4i64 -> v4i32 becomes VPERMD.
8994 if (Subtarget->hasInt256()) {
8995 static const int ShufMask[] = {0, 2, 4, 6, -1, -1, -1, -1};
8996 In = DAG.getNode(ISD::BITCAST, DL, MVT::v8i32, In);
8997 In = DAG.getVectorShuffle(MVT::v8i32, DL, In, DAG.getUNDEF(MVT::v8i32),
8999 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, In,
9000 DAG.getIntPtrConstant(0));
9003 // On AVX, v4i64 -> v4i32 becomes a sequence that uses PSHUFD and MOVLHPS.
9004 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
9005 DAG.getIntPtrConstant(0));
9006 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
9007 DAG.getIntPtrConstant(2));
9009 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo);
9010 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi);
9013 static const int ShufMask1[] = {0, 2, 0, 0};
9014 SDValue Undef = DAG.getUNDEF(VT);
9015 OpLo = DAG.getVectorShuffle(VT, DL, OpLo, Undef, ShufMask1);
9016 OpHi = DAG.getVectorShuffle(VT, DL, OpHi, Undef, ShufMask1);
9018 // The MOVLHPS mask:
9019 static const int ShufMask2[] = {0, 1, 4, 5};
9020 return DAG.getVectorShuffle(VT, DL, OpLo, OpHi, ShufMask2);
9023 if ((VT == MVT::v8i16) && (InVT == MVT::v8i32)) {
9024 // On AVX2, v8i32 -> v8i16 becomed PSHUFB.
9025 if (Subtarget->hasInt256()) {
9026 In = DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, In);
9028 SmallVector<SDValue,32> pshufbMask;
9029 for (unsigned i = 0; i < 2; ++i) {
9030 pshufbMask.push_back(DAG.getConstant(0x0, MVT::i8));
9031 pshufbMask.push_back(DAG.getConstant(0x1, MVT::i8));
9032 pshufbMask.push_back(DAG.getConstant(0x4, MVT::i8));
9033 pshufbMask.push_back(DAG.getConstant(0x5, MVT::i8));
9034 pshufbMask.push_back(DAG.getConstant(0x8, MVT::i8));
9035 pshufbMask.push_back(DAG.getConstant(0x9, MVT::i8));
9036 pshufbMask.push_back(DAG.getConstant(0xc, MVT::i8));
9037 pshufbMask.push_back(DAG.getConstant(0xd, MVT::i8));
9038 for (unsigned j = 0; j < 8; ++j)
9039 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
9041 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8,
9042 &pshufbMask[0], 32);
9043 In = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v32i8, In, BV);
9044 In = DAG.getNode(ISD::BITCAST, DL, MVT::v4i64, In);
9046 static const int ShufMask[] = {0, 2, -1, -1};
9047 In = DAG.getVectorShuffle(MVT::v4i64, DL, In, DAG.getUNDEF(MVT::v4i64),
9049 In = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
9050 DAG.getIntPtrConstant(0));
9051 return DAG.getNode(ISD::BITCAST, DL, VT, In);
9054 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
9055 DAG.getIntPtrConstant(0));
9057 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
9058 DAG.getIntPtrConstant(4));
9060 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpLo);
9061 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpHi);
9064 static const int ShufMask1[] = {0, 1, 4, 5, 8, 9, 12, 13,
9065 -1, -1, -1, -1, -1, -1, -1, -1};
9067 SDValue Undef = DAG.getUNDEF(MVT::v16i8);
9068 OpLo = DAG.getVectorShuffle(MVT::v16i8, DL, OpLo, Undef, ShufMask1);
9069 OpHi = DAG.getVectorShuffle(MVT::v16i8, DL, OpHi, Undef, ShufMask1);
9071 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo);
9072 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi);
9074 // The MOVLHPS Mask:
9075 static const int ShufMask2[] = {0, 1, 4, 5};
9076 SDValue res = DAG.getVectorShuffle(MVT::v4i32, DL, OpLo, OpHi, ShufMask2);
9077 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, res);
9080 // Handle truncation of V256 to V128 using shuffles.
9081 if (!VT.is128BitVector() || !InVT.is256BitVector())
9084 assert(Subtarget->hasFp256() && "256-bit vector without AVX!");
9086 unsigned NumElems = VT.getVectorNumElements();
9087 EVT NVT = EVT::getVectorVT(*DAG.getContext(), VT.getVectorElementType(),
9090 SmallVector<int, 16> MaskVec(NumElems * 2, -1);
9091 // Prepare truncation shuffle mask
9092 for (unsigned i = 0; i != NumElems; ++i)
9094 SDValue V = DAG.getVectorShuffle(NVT, DL,
9095 DAG.getNode(ISD::BITCAST, DL, NVT, In),
9096 DAG.getUNDEF(NVT), &MaskVec[0]);
9097 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, V,
9098 DAG.getIntPtrConstant(0));
9101 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op,
9102 SelectionDAG &DAG) const {
9103 MVT VT = Op.getSimpleValueType();
9104 if (VT.isVector()) {
9105 if (VT == MVT::v8i16)
9106 return DAG.getNode(ISD::TRUNCATE, SDLoc(Op), VT,
9107 DAG.getNode(ISD::FP_TO_SINT, SDLoc(Op),
9108 MVT::v8i32, Op.getOperand(0)));
9112 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
9113 /*IsSigned=*/ true, /*IsReplace=*/ false);
9114 SDValue FIST = Vals.first, StackSlot = Vals.second;
9115 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
9116 if (FIST.getNode() == 0) return Op;
9118 if (StackSlot.getNode())
9120 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
9121 FIST, StackSlot, MachinePointerInfo(),
9122 false, false, false, 0);
9124 // The node is the result.
9128 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op,
9129 SelectionDAG &DAG) const {
9130 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
9131 /*IsSigned=*/ false, /*IsReplace=*/ false);
9132 SDValue FIST = Vals.first, StackSlot = Vals.second;
9133 assert(FIST.getNode() && "Unexpected failure");
9135 if (StackSlot.getNode())
9137 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
9138 FIST, StackSlot, MachinePointerInfo(),
9139 false, false, false, 0);
9141 // The node is the result.
9145 static SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) {
9147 MVT VT = Op.getSimpleValueType();
9148 SDValue In = Op.getOperand(0);
9149 MVT SVT = In.getSimpleValueType();
9151 assert(SVT == MVT::v2f32 && "Only customize MVT::v2f32 type legalization!");
9153 return DAG.getNode(X86ISD::VFPEXT, DL, VT,
9154 DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v4f32,
9155 In, DAG.getUNDEF(SVT)));
9158 SDValue X86TargetLowering::LowerFABS(SDValue Op, SelectionDAG &DAG) const {
9159 LLVMContext *Context = DAG.getContext();
9161 MVT VT = Op.getSimpleValueType();
9163 unsigned NumElts = VT == MVT::f64 ? 2 : 4;
9164 if (VT.isVector()) {
9165 EltVT = VT.getVectorElementType();
9166 NumElts = VT.getVectorNumElements();
9169 if (EltVT == MVT::f64)
9170 C = ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
9171 APInt(64, ~(1ULL << 63))));
9173 C = ConstantFP::get(*Context, APFloat(APFloat::IEEEsingle,
9174 APInt(32, ~(1U << 31))));
9175 C = ConstantVector::getSplat(NumElts, C);
9176 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy());
9177 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
9178 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
9179 MachinePointerInfo::getConstantPool(),
9180 false, false, false, Alignment);
9181 if (VT.isVector()) {
9182 MVT ANDVT = VT.is128BitVector() ? MVT::v2i64 : MVT::v4i64;
9183 return DAG.getNode(ISD::BITCAST, dl, VT,
9184 DAG.getNode(ISD::AND, dl, ANDVT,
9185 DAG.getNode(ISD::BITCAST, dl, ANDVT,
9187 DAG.getNode(ISD::BITCAST, dl, ANDVT, Mask)));
9189 return DAG.getNode(X86ISD::FAND, dl, VT, Op.getOperand(0), Mask);
9192 SDValue X86TargetLowering::LowerFNEG(SDValue Op, SelectionDAG &DAG) const {
9193 LLVMContext *Context = DAG.getContext();
9195 MVT VT = Op.getSimpleValueType();
9197 unsigned NumElts = VT == MVT::f64 ? 2 : 4;
9198 if (VT.isVector()) {
9199 EltVT = VT.getVectorElementType();
9200 NumElts = VT.getVectorNumElements();
9203 if (EltVT == MVT::f64)
9204 C = ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
9205 APInt(64, 1ULL << 63)));
9207 C = ConstantFP::get(*Context, APFloat(APFloat::IEEEsingle,
9208 APInt(32, 1U << 31)));
9209 C = ConstantVector::getSplat(NumElts, C);
9210 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy());
9211 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
9212 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
9213 MachinePointerInfo::getConstantPool(),
9214 false, false, false, Alignment);
9215 if (VT.isVector()) {
9216 MVT XORVT = MVT::getVectorVT(MVT::i64, VT.getSizeInBits()/64);
9217 return DAG.getNode(ISD::BITCAST, dl, VT,
9218 DAG.getNode(ISD::XOR, dl, XORVT,
9219 DAG.getNode(ISD::BITCAST, dl, XORVT,
9221 DAG.getNode(ISD::BITCAST, dl, XORVT, Mask)));
9224 return DAG.getNode(X86ISD::FXOR, dl, VT, Op.getOperand(0), Mask);
9227 SDValue X86TargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {
9228 LLVMContext *Context = DAG.getContext();
9229 SDValue Op0 = Op.getOperand(0);
9230 SDValue Op1 = Op.getOperand(1);
9232 MVT VT = Op.getSimpleValueType();
9233 MVT SrcVT = Op1.getSimpleValueType();
9235 // If second operand is smaller, extend it first.
9236 if (SrcVT.bitsLT(VT)) {
9237 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
9240 // And if it is bigger, shrink it first.
9241 if (SrcVT.bitsGT(VT)) {
9242 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1));
9246 // At this point the operands and the result should have the same
9247 // type, and that won't be f80 since that is not custom lowered.
9249 // First get the sign bit of second operand.
9250 SmallVector<Constant*,4> CV;
9251 if (SrcVT == MVT::f64) {
9252 const fltSemantics &Sem = APFloat::IEEEdouble;
9253 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 1ULL << 63))));
9254 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 0))));
9256 const fltSemantics &Sem = APFloat::IEEEsingle;
9257 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 1U << 31))));
9258 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
9259 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
9260 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
9262 Constant *C = ConstantVector::get(CV);
9263 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
9264 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx,
9265 MachinePointerInfo::getConstantPool(),
9266 false, false, false, 16);
9267 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1);
9269 // Shift sign bit right or left if the two operands have different types.
9270 if (SrcVT.bitsGT(VT)) {
9271 // Op0 is MVT::f32, Op1 is MVT::f64.
9272 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, SignBit);
9273 SignBit = DAG.getNode(X86ISD::FSRL, dl, MVT::v2f64, SignBit,
9274 DAG.getConstant(32, MVT::i32));
9275 SignBit = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, SignBit);
9276 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, SignBit,
9277 DAG.getIntPtrConstant(0));
9280 // Clear first operand sign bit.
9282 if (VT == MVT::f64) {
9283 const fltSemantics &Sem = APFloat::IEEEdouble;
9284 CV.push_back(ConstantFP::get(*Context, APFloat(Sem,
9285 APInt(64, ~(1ULL << 63)))));
9286 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 0))));
9288 const fltSemantics &Sem = APFloat::IEEEsingle;
9289 CV.push_back(ConstantFP::get(*Context, APFloat(Sem,
9290 APInt(32, ~(1U << 31)))));
9291 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
9292 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
9293 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
9295 C = ConstantVector::get(CV);
9296 CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
9297 SDValue Mask2 = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
9298 MachinePointerInfo::getConstantPool(),
9299 false, false, false, 16);
9300 SDValue Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Mask2);
9302 // Or the value with the sign bit.
9303 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit);
9306 static SDValue LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) {
9307 SDValue N0 = Op.getOperand(0);
9309 MVT VT = Op.getSimpleValueType();
9311 // Lower ISD::FGETSIGN to (AND (X86ISD::FGETSIGNx86 ...) 1).
9312 SDValue xFGETSIGN = DAG.getNode(X86ISD::FGETSIGNx86, dl, VT, N0,
9313 DAG.getConstant(1, VT));
9314 return DAG.getNode(ISD::AND, dl, VT, xFGETSIGN, DAG.getConstant(1, VT));
9317 // LowerVectorAllZeroTest - Check whether an OR'd tree is PTEST-able.
9319 static SDValue LowerVectorAllZeroTest(SDValue Op, const X86Subtarget *Subtarget,
9320 SelectionDAG &DAG) {
9321 assert(Op.getOpcode() == ISD::OR && "Only check OR'd tree.");
9323 if (!Subtarget->hasSSE41())
9326 if (!Op->hasOneUse())
9329 SDNode *N = Op.getNode();
9332 SmallVector<SDValue, 8> Opnds;
9333 DenseMap<SDValue, unsigned> VecInMap;
9334 EVT VT = MVT::Other;
9336 // Recognize a special case where a vector is casted into wide integer to
9338 Opnds.push_back(N->getOperand(0));
9339 Opnds.push_back(N->getOperand(1));
9341 for (unsigned Slot = 0, e = Opnds.size(); Slot < e; ++Slot) {
9342 SmallVectorImpl<SDValue>::const_iterator I = Opnds.begin() + Slot;
9343 // BFS traverse all OR'd operands.
9344 if (I->getOpcode() == ISD::OR) {
9345 Opnds.push_back(I->getOperand(0));
9346 Opnds.push_back(I->getOperand(1));
9347 // Re-evaluate the number of nodes to be traversed.
9348 e += 2; // 2 more nodes (LHS and RHS) are pushed.
9352 // Quit if a non-EXTRACT_VECTOR_ELT
9353 if (I->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
9356 // Quit if without a constant index.
9357 SDValue Idx = I->getOperand(1);
9358 if (!isa<ConstantSDNode>(Idx))
9361 SDValue ExtractedFromVec = I->getOperand(0);
9362 DenseMap<SDValue, unsigned>::iterator M = VecInMap.find(ExtractedFromVec);
9363 if (M == VecInMap.end()) {
9364 VT = ExtractedFromVec.getValueType();
9365 // Quit if not 128/256-bit vector.
9366 if (!VT.is128BitVector() && !VT.is256BitVector())
9368 // Quit if not the same type.
9369 if (VecInMap.begin() != VecInMap.end() &&
9370 VT != VecInMap.begin()->first.getValueType())
9372 M = VecInMap.insert(std::make_pair(ExtractedFromVec, 0)).first;
9374 M->second |= 1U << cast<ConstantSDNode>(Idx)->getZExtValue();
9377 assert((VT.is128BitVector() || VT.is256BitVector()) &&
9378 "Not extracted from 128-/256-bit vector.");
9380 unsigned FullMask = (1U << VT.getVectorNumElements()) - 1U;
9381 SmallVector<SDValue, 8> VecIns;
9383 for (DenseMap<SDValue, unsigned>::const_iterator
9384 I = VecInMap.begin(), E = VecInMap.end(); I != E; ++I) {
9385 // Quit if not all elements are used.
9386 if (I->second != FullMask)
9388 VecIns.push_back(I->first);
9391 EVT TestVT = VT.is128BitVector() ? MVT::v2i64 : MVT::v4i64;
9393 // Cast all vectors into TestVT for PTEST.
9394 for (unsigned i = 0, e = VecIns.size(); i < e; ++i)
9395 VecIns[i] = DAG.getNode(ISD::BITCAST, DL, TestVT, VecIns[i]);
9397 // If more than one full vectors are evaluated, OR them first before PTEST.
9398 for (unsigned Slot = 0, e = VecIns.size(); e - Slot > 1; Slot += 2, e += 1) {
9399 // Each iteration will OR 2 nodes and append the result until there is only
9400 // 1 node left, i.e. the final OR'd value of all vectors.
9401 SDValue LHS = VecIns[Slot];
9402 SDValue RHS = VecIns[Slot + 1];
9403 VecIns.push_back(DAG.getNode(ISD::OR, DL, TestVT, LHS, RHS));
9406 return DAG.getNode(X86ISD::PTEST, DL, MVT::i32,
9407 VecIns.back(), VecIns.back());
9410 /// Emit nodes that will be selected as "test Op0,Op0", or something
9412 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC,
9413 SelectionDAG &DAG) const {
9416 // CF and OF aren't always set the way we want. Determine which
9417 // of these we need.
9418 bool NeedCF = false;
9419 bool NeedOF = false;
9422 case X86::COND_A: case X86::COND_AE:
9423 case X86::COND_B: case X86::COND_BE:
9426 case X86::COND_G: case X86::COND_GE:
9427 case X86::COND_L: case X86::COND_LE:
9428 case X86::COND_O: case X86::COND_NO:
9433 // See if we can use the EFLAGS value from the operand instead of
9434 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
9435 // we prove that the arithmetic won't overflow, we can't use OF or CF.
9436 if (Op.getResNo() != 0 || NeedOF || NeedCF)
9437 // Emit a CMP with 0, which is the TEST pattern.
9438 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
9439 DAG.getConstant(0, Op.getValueType()));
9441 unsigned Opcode = 0;
9442 unsigned NumOperands = 0;
9444 // Truncate operations may prevent the merge of the SETCC instruction
9445 // and the arithmetic instruction before it. Attempt to truncate the operands
9446 // of the arithmetic instruction and use a reduced bit-width instruction.
9447 bool NeedTruncation = false;
9448 SDValue ArithOp = Op;
9449 if (Op->getOpcode() == ISD::TRUNCATE && Op->hasOneUse()) {
9450 SDValue Arith = Op->getOperand(0);
9451 // Both the trunc and the arithmetic op need to have one user each.
9452 if (Arith->hasOneUse())
9453 switch (Arith.getOpcode()) {
9460 NeedTruncation = true;
9466 // NOTICE: In the code below we use ArithOp to hold the arithmetic operation
9467 // which may be the result of a CAST. We use the variable 'Op', which is the
9468 // non-casted variable when we check for possible users.
9469 switch (ArithOp.getOpcode()) {
9471 // Due to an isel shortcoming, be conservative if this add is likely to be
9472 // selected as part of a load-modify-store instruction. When the root node
9473 // in a match is a store, isel doesn't know how to remap non-chain non-flag
9474 // uses of other nodes in the match, such as the ADD in this case. This
9475 // leads to the ADD being left around and reselected, with the result being
9476 // two adds in the output. Alas, even if none our users are stores, that
9477 // doesn't prove we're O.K. Ergo, if we have any parents that aren't
9478 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require
9479 // climbing the DAG back to the root, and it doesn't seem to be worth the
9481 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
9482 UE = Op.getNode()->use_end(); UI != UE; ++UI)
9483 if (UI->getOpcode() != ISD::CopyToReg &&
9484 UI->getOpcode() != ISD::SETCC &&
9485 UI->getOpcode() != ISD::STORE)
9488 if (ConstantSDNode *C =
9489 dyn_cast<ConstantSDNode>(ArithOp.getNode()->getOperand(1))) {
9490 // An add of one will be selected as an INC.
9491 if (C->getAPIntValue() == 1) {
9492 Opcode = X86ISD::INC;
9497 // An add of negative one (subtract of one) will be selected as a DEC.
9498 if (C->getAPIntValue().isAllOnesValue()) {
9499 Opcode = X86ISD::DEC;
9505 // Otherwise use a regular EFLAGS-setting add.
9506 Opcode = X86ISD::ADD;
9510 // If the primary and result isn't used, don't bother using X86ISD::AND,
9511 // because a TEST instruction will be better.
9512 bool NonFlagUse = false;
9513 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
9514 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
9516 unsigned UOpNo = UI.getOperandNo();
9517 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
9518 // Look pass truncate.
9519 UOpNo = User->use_begin().getOperandNo();
9520 User = *User->use_begin();
9523 if (User->getOpcode() != ISD::BRCOND &&
9524 User->getOpcode() != ISD::SETCC &&
9525 !(User->getOpcode() == ISD::SELECT && UOpNo == 0)) {
9538 // Due to the ISEL shortcoming noted above, be conservative if this op is
9539 // likely to be selected as part of a load-modify-store instruction.
9540 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
9541 UE = Op.getNode()->use_end(); UI != UE; ++UI)
9542 if (UI->getOpcode() == ISD::STORE)
9545 // Otherwise use a regular EFLAGS-setting instruction.
9546 switch (ArithOp.getOpcode()) {
9547 default: llvm_unreachable("unexpected operator!");
9548 case ISD::SUB: Opcode = X86ISD::SUB; break;
9549 case ISD::XOR: Opcode = X86ISD::XOR; break;
9550 case ISD::AND: Opcode = X86ISD::AND; break;
9552 if (!NeedTruncation && (X86CC == X86::COND_E || X86CC == X86::COND_NE)) {
9553 SDValue EFLAGS = LowerVectorAllZeroTest(Op, Subtarget, DAG);
9554 if (EFLAGS.getNode())
9557 Opcode = X86ISD::OR;
9571 return SDValue(Op.getNode(), 1);
9577 // If we found that truncation is beneficial, perform the truncation and
9579 if (NeedTruncation) {
9580 EVT VT = Op.getValueType();
9581 SDValue WideVal = Op->getOperand(0);
9582 EVT WideVT = WideVal.getValueType();
9583 unsigned ConvertedOp = 0;
9584 // Use a target machine opcode to prevent further DAGCombine
9585 // optimizations that may separate the arithmetic operations
9586 // from the setcc node.
9587 switch (WideVal.getOpcode()) {
9589 case ISD::ADD: ConvertedOp = X86ISD::ADD; break;
9590 case ISD::SUB: ConvertedOp = X86ISD::SUB; break;
9591 case ISD::AND: ConvertedOp = X86ISD::AND; break;
9592 case ISD::OR: ConvertedOp = X86ISD::OR; break;
9593 case ISD::XOR: ConvertedOp = X86ISD::XOR; break;
9597 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
9598 if (TLI.isOperationLegal(WideVal.getOpcode(), WideVT)) {
9599 SDValue V0 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(0));
9600 SDValue V1 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(1));
9601 Op = DAG.getNode(ConvertedOp, dl, VT, V0, V1);
9607 // Emit a CMP with 0, which is the TEST pattern.
9608 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
9609 DAG.getConstant(0, Op.getValueType()));
9611 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
9612 SmallVector<SDValue, 4> Ops;
9613 for (unsigned i = 0; i != NumOperands; ++i)
9614 Ops.push_back(Op.getOperand(i));
9616 SDValue New = DAG.getNode(Opcode, dl, VTs, &Ops[0], NumOperands);
9617 DAG.ReplaceAllUsesWith(Op, New);
9618 return SDValue(New.getNode(), 1);
9621 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
9623 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
9624 SelectionDAG &DAG) const {
9625 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1))
9626 if (C->getAPIntValue() == 0)
9627 return EmitTest(Op0, X86CC, DAG);
9630 if ((Op0.getValueType() == MVT::i8 || Op0.getValueType() == MVT::i16 ||
9631 Op0.getValueType() == MVT::i32 || Op0.getValueType() == MVT::i64)) {
9632 // Use SUB instead of CMP to enable CSE between SUB and CMP.
9633 SDVTList VTs = DAG.getVTList(Op0.getValueType(), MVT::i32);
9634 SDValue Sub = DAG.getNode(X86ISD::SUB, dl, VTs,
9636 return SDValue(Sub.getNode(), 1);
9638 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
9641 /// Convert a comparison if required by the subtarget.
9642 SDValue X86TargetLowering::ConvertCmpIfNecessary(SDValue Cmp,
9643 SelectionDAG &DAG) const {
9644 // If the subtarget does not support the FUCOMI instruction, floating-point
9645 // comparisons have to be converted.
9646 if (Subtarget->hasCMov() ||
9647 Cmp.getOpcode() != X86ISD::CMP ||
9648 !Cmp.getOperand(0).getValueType().isFloatingPoint() ||
9649 !Cmp.getOperand(1).getValueType().isFloatingPoint())
9652 // The instruction selector will select an FUCOM instruction instead of
9653 // FUCOMI, which writes the comparison result to FPSW instead of EFLAGS. Hence
9654 // build an SDNode sequence that transfers the result from FPSW into EFLAGS:
9655 // (X86sahf (trunc (srl (X86fp_stsw (trunc (X86cmp ...)), 8))))
9657 SDValue TruncFPSW = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, Cmp);
9658 SDValue FNStSW = DAG.getNode(X86ISD::FNSTSW16r, dl, MVT::i16, TruncFPSW);
9659 SDValue Srl = DAG.getNode(ISD::SRL, dl, MVT::i16, FNStSW,
9660 DAG.getConstant(8, MVT::i8));
9661 SDValue TruncSrl = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Srl);
9662 return DAG.getNode(X86ISD::SAHF, dl, MVT::i32, TruncSrl);
9665 static bool isAllOnes(SDValue V) {
9666 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
9667 return C && C->isAllOnesValue();
9670 /// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node
9671 /// if it's possible.
9672 SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC,
9673 SDLoc dl, SelectionDAG &DAG) const {
9674 SDValue Op0 = And.getOperand(0);
9675 SDValue Op1 = And.getOperand(1);
9676 if (Op0.getOpcode() == ISD::TRUNCATE)
9677 Op0 = Op0.getOperand(0);
9678 if (Op1.getOpcode() == ISD::TRUNCATE)
9679 Op1 = Op1.getOperand(0);
9682 if (Op1.getOpcode() == ISD::SHL)
9683 std::swap(Op0, Op1);
9684 if (Op0.getOpcode() == ISD::SHL) {
9685 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0)))
9686 if (And00C->getZExtValue() == 1) {
9687 // If we looked past a truncate, check that it's only truncating away
9689 unsigned BitWidth = Op0.getValueSizeInBits();
9690 unsigned AndBitWidth = And.getValueSizeInBits();
9691 if (BitWidth > AndBitWidth) {
9693 DAG.ComputeMaskedBits(Op0, Zeros, Ones);
9694 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth)
9698 RHS = Op0.getOperand(1);
9700 } else if (Op1.getOpcode() == ISD::Constant) {
9701 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1);
9702 uint64_t AndRHSVal = AndRHS->getZExtValue();
9703 SDValue AndLHS = Op0;
9705 if (AndRHSVal == 1 && AndLHS.getOpcode() == ISD::SRL) {
9706 LHS = AndLHS.getOperand(0);
9707 RHS = AndLHS.getOperand(1);
9710 // Use BT if the immediate can't be encoded in a TEST instruction.
9711 if (!isUInt<32>(AndRHSVal) && isPowerOf2_64(AndRHSVal)) {
9713 RHS = DAG.getConstant(Log2_64_Ceil(AndRHSVal), LHS.getValueType());
9717 if (LHS.getNode()) {
9718 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT
9719 // instruction. Since the shift amount is in-range-or-undefined, we know
9720 // that doing a bittest on the i32 value is ok. We extend to i32 because
9721 // the encoding for the i16 version is larger than the i32 version.
9722 // Also promote i16 to i32 for performance / code size reason.
9723 if (LHS.getValueType() == MVT::i8 ||
9724 LHS.getValueType() == MVT::i16)
9725 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
9727 // If the operand types disagree, extend the shift amount to match. Since
9728 // BT ignores high bits (like shifts) we can use anyextend.
9729 if (LHS.getValueType() != RHS.getValueType())
9730 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
9732 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
9733 X86::CondCode Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
9734 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
9735 DAG.getConstant(Cond, MVT::i8), BT);
9741 /// \brief - Turns an ISD::CondCode into a value suitable for SSE floating point
9743 static int translateX86FSETCC(ISD::CondCode SetCCOpcode, SDValue &Op0,
9748 // SSE Condition code mapping:
9757 switch (SetCCOpcode) {
9758 default: llvm_unreachable("Unexpected SETCC condition");
9760 case ISD::SETEQ: SSECC = 0; break;
9762 case ISD::SETGT: Swap = true; // Fallthrough
9764 case ISD::SETOLT: SSECC = 1; break;
9766 case ISD::SETGE: Swap = true; // Fallthrough
9768 case ISD::SETOLE: SSECC = 2; break;
9769 case ISD::SETUO: SSECC = 3; break;
9771 case ISD::SETNE: SSECC = 4; break;
9772 case ISD::SETULE: Swap = true; // Fallthrough
9773 case ISD::SETUGE: SSECC = 5; break;
9774 case ISD::SETULT: Swap = true; // Fallthrough
9775 case ISD::SETUGT: SSECC = 6; break;
9776 case ISD::SETO: SSECC = 7; break;
9778 case ISD::SETONE: SSECC = 8; break;
9781 std::swap(Op0, Op1);
9786 // Lower256IntVSETCC - Break a VSETCC 256-bit integer VSETCC into two new 128
9787 // ones, and then concatenate the result back.
9788 static SDValue Lower256IntVSETCC(SDValue Op, SelectionDAG &DAG) {
9789 MVT VT = Op.getSimpleValueType();
9791 assert(VT.is256BitVector() && Op.getOpcode() == ISD::SETCC &&
9792 "Unsupported value type for operation");
9794 unsigned NumElems = VT.getVectorNumElements();
9796 SDValue CC = Op.getOperand(2);
9798 // Extract the LHS vectors
9799 SDValue LHS = Op.getOperand(0);
9800 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
9801 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
9803 // Extract the RHS vectors
9804 SDValue RHS = Op.getOperand(1);
9805 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
9806 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
9808 // Issue the operation on the smaller types and concatenate the result back
9809 MVT EltVT = VT.getVectorElementType();
9810 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
9811 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
9812 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1, CC),
9813 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC));
9816 static SDValue LowerIntVSETCC_AVX512(SDValue Op, SelectionDAG &DAG) {
9817 SDValue Op0 = Op.getOperand(0);
9818 SDValue Op1 = Op.getOperand(1);
9819 SDValue CC = Op.getOperand(2);
9820 MVT VT = Op.getSimpleValueType();
9822 assert(Op0.getValueType().getVectorElementType().getSizeInBits() >= 32 &&
9823 Op.getValueType().getScalarType() == MVT::i1 &&
9824 "Cannot set masked compare for this operation");
9826 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
9829 bool Unsigned = false;
9831 switch (SetCCOpcode) {
9832 default: llvm_unreachable("Unexpected SETCC condition");
9833 case ISD::SETNE: SSECC = 4; break;
9834 case ISD::SETEQ: SSECC = 0; break;
9835 case ISD::SETUGT: Unsigned = true;
9836 case ISD::SETGT: SSECC = 6; break; // NLE
9837 case ISD::SETULT: Unsigned = true;
9838 case ISD::SETLT: SSECC = 1; break;
9839 case ISD::SETUGE: Unsigned = true;
9840 case ISD::SETGE: SSECC = 5; break; // NLT
9841 case ISD::SETULE: Unsigned = true;
9842 case ISD::SETLE: SSECC = 2; break;
9844 unsigned Opc = Unsigned ? X86ISD::CMPMU: X86ISD::CMPM;
9845 return DAG.getNode(Opc, dl, VT, Op0, Op1,
9846 DAG.getConstant(SSECC, MVT::i8));
9850 static SDValue LowerVSETCC(SDValue Op, const X86Subtarget *Subtarget,
9851 SelectionDAG &DAG) {
9852 SDValue Op0 = Op.getOperand(0);
9853 SDValue Op1 = Op.getOperand(1);
9854 SDValue CC = Op.getOperand(2);
9855 MVT VT = Op.getSimpleValueType();
9856 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
9857 bool isFP = Op.getOperand(1).getSimpleValueType().isFloatingPoint();
9862 MVT EltVT = Op0.getSimpleValueType().getVectorElementType();
9863 assert(EltVT == MVT::f32 || EltVT == MVT::f64);
9866 unsigned SSECC = translateX86FSETCC(SetCCOpcode, Op0, Op1);
9867 unsigned Opc = X86ISD::CMPP;
9868 if (Subtarget->hasAVX512() && VT.getVectorElementType() == MVT::i1) {
9869 assert(VT.getVectorNumElements() <= 16);
9872 // In the two special cases we can't handle, emit two comparisons.
9875 unsigned CombineOpc;
9876 if (SetCCOpcode == ISD::SETUEQ) {
9877 CC0 = 3; CC1 = 0; CombineOpc = ISD::OR;
9879 assert(SetCCOpcode == ISD::SETONE);
9880 CC0 = 7; CC1 = 4; CombineOpc = ISD::AND;
9883 SDValue Cmp0 = DAG.getNode(Opc, dl, VT, Op0, Op1,
9884 DAG.getConstant(CC0, MVT::i8));
9885 SDValue Cmp1 = DAG.getNode(Opc, dl, VT, Op0, Op1,
9886 DAG.getConstant(CC1, MVT::i8));
9887 return DAG.getNode(CombineOpc, dl, VT, Cmp0, Cmp1);
9889 // Handle all other FP comparisons here.
9890 return DAG.getNode(Opc, dl, VT, Op0, Op1,
9891 DAG.getConstant(SSECC, MVT::i8));
9894 // Break 256-bit integer vector compare into smaller ones.
9895 if (VT.is256BitVector() && !Subtarget->hasInt256())
9896 return Lower256IntVSETCC(Op, DAG);
9898 bool MaskResult = (VT.getVectorElementType() == MVT::i1);
9899 EVT OpVT = Op1.getValueType();
9900 if (Subtarget->hasAVX512()) {
9901 if (Op1.getValueType().is512BitVector() ||
9902 (MaskResult && OpVT.getVectorElementType().getSizeInBits() >= 32))
9903 return LowerIntVSETCC_AVX512(Op, DAG);
9905 // In AVX-512 architecture setcc returns mask with i1 elements,
9906 // But there is no compare instruction for i8 and i16 elements.
9907 // We are not talking about 512-bit operands in this case, these
9908 // types are illegal.
9910 (OpVT.getVectorElementType().getSizeInBits() < 32 &&
9911 OpVT.getVectorElementType().getSizeInBits() >= 8))
9912 return DAG.getNode(ISD::TRUNCATE, dl, VT,
9913 DAG.getNode(ISD::SETCC, dl, OpVT, Op0, Op1, CC));
9916 // We are handling one of the integer comparisons here. Since SSE only has
9917 // GT and EQ comparisons for integer, swapping operands and multiple
9918 // operations may be required for some comparisons.
9920 bool Swap = false, Invert = false, FlipSigns = false, MinMax = false;
9922 switch (SetCCOpcode) {
9923 default: llvm_unreachable("Unexpected SETCC condition");
9924 case ISD::SETNE: Invert = true;
9925 case ISD::SETEQ: Opc = MaskResult? X86ISD::PCMPEQM: X86ISD::PCMPEQ; break;
9926 case ISD::SETLT: Swap = true;
9927 case ISD::SETGT: Opc = MaskResult? X86ISD::PCMPGTM: X86ISD::PCMPGT; break;
9928 case ISD::SETGE: Swap = true;
9929 case ISD::SETLE: Opc = MaskResult? X86ISD::PCMPGTM: X86ISD::PCMPGT;
9930 Invert = true; break;
9931 case ISD::SETULT: Swap = true;
9932 case ISD::SETUGT: Opc = MaskResult? X86ISD::PCMPGTM: X86ISD::PCMPGT;
9933 FlipSigns = true; break;
9934 case ISD::SETUGE: Swap = true;
9935 case ISD::SETULE: Opc = MaskResult? X86ISD::PCMPGTM: X86ISD::PCMPGT;
9936 FlipSigns = true; Invert = true; break;
9939 // Special case: Use min/max operations for SETULE/SETUGE
9940 MVT VET = VT.getVectorElementType();
9942 (Subtarget->hasSSE41() && (VET >= MVT::i8 && VET <= MVT::i32))
9943 || (Subtarget->hasSSE2() && (VET == MVT::i8));
9946 switch (SetCCOpcode) {
9948 case ISD::SETULE: Opc = X86ISD::UMIN; MinMax = true; break;
9949 case ISD::SETUGE: Opc = X86ISD::UMAX; MinMax = true; break;
9952 if (MinMax) { Swap = false; Invert = false; FlipSigns = false; }
9956 std::swap(Op0, Op1);
9958 // Check that the operation in question is available (most are plain SSE2,
9959 // but PCMPGTQ and PCMPEQQ have different requirements).
9960 if (VT == MVT::v2i64) {
9961 if (Opc == X86ISD::PCMPGT && !Subtarget->hasSSE42()) {
9962 assert(Subtarget->hasSSE2() && "Don't know how to lower!");
9964 // First cast everything to the right type.
9965 Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0);
9966 Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1);
9968 // Since SSE has no unsigned integer comparisons, we need to flip the sign
9969 // bits of the inputs before performing those operations. The lower
9970 // compare is always unsigned.
9973 SB = DAG.getConstant(0x80000000U, MVT::v4i32);
9975 SDValue Sign = DAG.getConstant(0x80000000U, MVT::i32);
9976 SDValue Zero = DAG.getConstant(0x00000000U, MVT::i32);
9977 SB = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
9978 Sign, Zero, Sign, Zero);
9980 Op0 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op0, SB);
9981 Op1 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op1, SB);
9983 // Emulate PCMPGTQ with (hi1 > hi2) | ((hi1 == hi2) & (lo1 > lo2))
9984 SDValue GT = DAG.getNode(X86ISD::PCMPGT, dl, MVT::v4i32, Op0, Op1);
9985 SDValue EQ = DAG.getNode(X86ISD::PCMPEQ, dl, MVT::v4i32, Op0, Op1);
9987 // Create masks for only the low parts/high parts of the 64 bit integers.
9988 static const int MaskHi[] = { 1, 1, 3, 3 };
9989 static const int MaskLo[] = { 0, 0, 2, 2 };
9990 SDValue EQHi = DAG.getVectorShuffle(MVT::v4i32, dl, EQ, EQ, MaskHi);
9991 SDValue GTLo = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskLo);
9992 SDValue GTHi = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskHi);
9994 SDValue Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, EQHi, GTLo);
9995 Result = DAG.getNode(ISD::OR, dl, MVT::v4i32, Result, GTHi);
9998 Result = DAG.getNOT(dl, Result, MVT::v4i32);
10000 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
10003 if (Opc == X86ISD::PCMPEQ && !Subtarget->hasSSE41()) {
10004 // If pcmpeqq is missing but pcmpeqd is available synthesize pcmpeqq with
10005 // pcmpeqd + pshufd + pand.
10006 assert(Subtarget->hasSSE2() && !FlipSigns && "Don't know how to lower!");
10008 // First cast everything to the right type.
10009 Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0);
10010 Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1);
10013 SDValue Result = DAG.getNode(Opc, dl, MVT::v4i32, Op0, Op1);
10015 // Make sure the lower and upper halves are both all-ones.
10016 static const int Mask[] = { 1, 0, 3, 2 };
10017 SDValue Shuf = DAG.getVectorShuffle(MVT::v4i32, dl, Result, Result, Mask);
10018 Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, Result, Shuf);
10021 Result = DAG.getNOT(dl, Result, MVT::v4i32);
10023 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
10027 // Since SSE has no unsigned integer comparisons, we need to flip the sign
10028 // bits of the inputs before performing those operations.
10030 EVT EltVT = VT.getVectorElementType();
10031 SDValue SB = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()), VT);
10032 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SB);
10033 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SB);
10036 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
10038 // If the logical-not of the result is required, perform that now.
10040 Result = DAG.getNOT(dl, Result, VT);
10043 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Op0, Result);
10048 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
10050 MVT VT = Op.getSimpleValueType();
10052 if (VT.isVector()) return LowerVSETCC(Op, Subtarget, DAG);
10054 assert(VT == MVT::i8 && "SetCC type must be 8-bit integer");
10055 SDValue Op0 = Op.getOperand(0);
10056 SDValue Op1 = Op.getOperand(1);
10058 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
10060 // Optimize to BT if possible.
10061 // Lower (X & (1 << N)) == 0 to BT(X, N).
10062 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
10063 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
10064 if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() &&
10065 Op1.getOpcode() == ISD::Constant &&
10066 cast<ConstantSDNode>(Op1)->isNullValue() &&
10067 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
10068 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG);
10069 if (NewSetCC.getNode())
10073 // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of
10075 if (Op1.getOpcode() == ISD::Constant &&
10076 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 ||
10077 cast<ConstantSDNode>(Op1)->isNullValue()) &&
10078 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
10080 // If the input is a setcc, then reuse the input setcc or use a new one with
10081 // the inverted condition.
10082 if (Op0.getOpcode() == X86ISD::SETCC) {
10083 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0);
10084 bool Invert = (CC == ISD::SETNE) ^
10085 cast<ConstantSDNode>(Op1)->isNullValue();
10086 if (!Invert) return Op0;
10088 CCode = X86::GetOppositeBranchCondition(CCode);
10089 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
10090 DAG.getConstant(CCode, MVT::i8), Op0.getOperand(1));
10094 bool isFP = Op1.getSimpleValueType().isFloatingPoint();
10095 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG);
10096 if (X86CC == X86::COND_INVALID)
10099 SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, DAG);
10100 EFLAGS = ConvertCmpIfNecessary(EFLAGS, DAG);
10101 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
10102 DAG.getConstant(X86CC, MVT::i8), EFLAGS);
10105 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
10106 static bool isX86LogicalCmp(SDValue Op) {
10107 unsigned Opc = Op.getNode()->getOpcode();
10108 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI ||
10109 Opc == X86ISD::SAHF)
10111 if (Op.getResNo() == 1 &&
10112 (Opc == X86ISD::ADD ||
10113 Opc == X86ISD::SUB ||
10114 Opc == X86ISD::ADC ||
10115 Opc == X86ISD::SBB ||
10116 Opc == X86ISD::SMUL ||
10117 Opc == X86ISD::UMUL ||
10118 Opc == X86ISD::INC ||
10119 Opc == X86ISD::DEC ||
10120 Opc == X86ISD::OR ||
10121 Opc == X86ISD::XOR ||
10122 Opc == X86ISD::AND))
10125 if (Op.getResNo() == 2 && Opc == X86ISD::UMUL)
10131 static bool isZero(SDValue V) {
10132 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
10133 return C && C->isNullValue();
10136 static bool isTruncWithZeroHighBitsInput(SDValue V, SelectionDAG &DAG) {
10137 if (V.getOpcode() != ISD::TRUNCATE)
10140 SDValue VOp0 = V.getOperand(0);
10141 unsigned InBits = VOp0.getValueSizeInBits();
10142 unsigned Bits = V.getValueSizeInBits();
10143 return DAG.MaskedValueIsZero(VOp0, APInt::getHighBitsSet(InBits,InBits-Bits));
10146 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
10147 bool addTest = true;
10148 SDValue Cond = Op.getOperand(0);
10149 SDValue Op1 = Op.getOperand(1);
10150 SDValue Op2 = Op.getOperand(2);
10152 EVT VT = Op1.getValueType();
10155 // Lower fp selects into a CMP/AND/ANDN/OR sequence when the necessary SSE ops
10156 // are available. Otherwise fp cmovs get lowered into a less efficient branch
10157 // sequence later on.
10158 if (Cond.getOpcode() == ISD::SETCC &&
10159 ((Subtarget->hasSSE2() && (VT == MVT::f32 || VT == MVT::f64)) ||
10160 (Subtarget->hasSSE1() && VT == MVT::f32)) &&
10161 VT == Cond.getOperand(0).getValueType() && Cond->hasOneUse()) {
10162 SDValue CondOp0 = Cond.getOperand(0), CondOp1 = Cond.getOperand(1);
10163 int SSECC = translateX86FSETCC(
10164 cast<CondCodeSDNode>(Cond.getOperand(2))->get(), CondOp0, CondOp1);
10167 unsigned Opcode = VT == MVT::f32 ? X86ISD::FSETCCss : X86ISD::FSETCCsd;
10168 SDValue Cmp = DAG.getNode(Opcode, DL, VT, CondOp0, CondOp1,
10169 DAG.getConstant(SSECC, MVT::i8));
10170 SDValue AndN = DAG.getNode(X86ISD::FANDN, DL, VT, Cmp, Op2);
10171 SDValue And = DAG.getNode(X86ISD::FAND, DL, VT, Cmp, Op1);
10172 return DAG.getNode(X86ISD::FOR, DL, VT, AndN, And);
10176 if (Cond.getOpcode() == ISD::SETCC) {
10177 SDValue NewCond = LowerSETCC(Cond, DAG);
10178 if (NewCond.getNode())
10182 // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y
10183 // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y
10184 // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y
10185 // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y
10186 if (Cond.getOpcode() == X86ISD::SETCC &&
10187 Cond.getOperand(1).getOpcode() == X86ISD::CMP &&
10188 isZero(Cond.getOperand(1).getOperand(1))) {
10189 SDValue Cmp = Cond.getOperand(1);
10191 unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue();
10193 if ((isAllOnes(Op1) || isAllOnes(Op2)) &&
10194 (CondCode == X86::COND_E || CondCode == X86::COND_NE)) {
10195 SDValue Y = isAllOnes(Op2) ? Op1 : Op2;
10197 SDValue CmpOp0 = Cmp.getOperand(0);
10198 // Apply further optimizations for special cases
10199 // (select (x != 0), -1, 0) -> neg & sbb
10200 // (select (x == 0), 0, -1) -> neg & sbb
10201 if (ConstantSDNode *YC = dyn_cast<ConstantSDNode>(Y))
10202 if (YC->isNullValue() &&
10203 (isAllOnes(Op1) == (CondCode == X86::COND_NE))) {
10204 SDVTList VTs = DAG.getVTList(CmpOp0.getValueType(), MVT::i32);
10205 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, VTs,
10206 DAG.getConstant(0, CmpOp0.getValueType()),
10208 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
10209 DAG.getConstant(X86::COND_B, MVT::i8),
10210 SDValue(Neg.getNode(), 1));
10214 Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32,
10215 CmpOp0, DAG.getConstant(1, CmpOp0.getValueType()));
10216 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
10218 SDValue Res = // Res = 0 or -1.
10219 DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
10220 DAG.getConstant(X86::COND_B, MVT::i8), Cmp);
10222 if (isAllOnes(Op1) != (CondCode == X86::COND_E))
10223 Res = DAG.getNOT(DL, Res, Res.getValueType());
10225 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2);
10226 if (N2C == 0 || !N2C->isNullValue())
10227 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y);
10232 // Look past (and (setcc_carry (cmp ...)), 1).
10233 if (Cond.getOpcode() == ISD::AND &&
10234 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
10235 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
10236 if (C && C->getAPIntValue() == 1)
10237 Cond = Cond.getOperand(0);
10240 // If condition flag is set by a X86ISD::CMP, then use it as the condition
10241 // setting operand in place of the X86ISD::SETCC.
10242 unsigned CondOpcode = Cond.getOpcode();
10243 if (CondOpcode == X86ISD::SETCC ||
10244 CondOpcode == X86ISD::SETCC_CARRY) {
10245 CC = Cond.getOperand(0);
10247 SDValue Cmp = Cond.getOperand(1);
10248 unsigned Opc = Cmp.getOpcode();
10249 MVT VT = Op.getSimpleValueType();
10251 bool IllegalFPCMov = false;
10252 if (VT.isFloatingPoint() && !VT.isVector() &&
10253 !isScalarFPTypeInSSEReg(VT)) // FPStack?
10254 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
10256 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
10257 Opc == X86ISD::BT) { // FIXME
10261 } else if (CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
10262 CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
10263 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
10264 Cond.getOperand(0).getValueType() != MVT::i8)) {
10265 SDValue LHS = Cond.getOperand(0);
10266 SDValue RHS = Cond.getOperand(1);
10267 unsigned X86Opcode;
10270 switch (CondOpcode) {
10271 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
10272 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
10273 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
10274 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
10275 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
10276 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
10277 default: llvm_unreachable("unexpected overflowing operator");
10279 if (CondOpcode == ISD::UMULO)
10280 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
10283 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
10285 SDValue X86Op = DAG.getNode(X86Opcode, DL, VTs, LHS, RHS);
10287 if (CondOpcode == ISD::UMULO)
10288 Cond = X86Op.getValue(2);
10290 Cond = X86Op.getValue(1);
10292 CC = DAG.getConstant(X86Cond, MVT::i8);
10297 // Look pass the truncate if the high bits are known zero.
10298 if (isTruncWithZeroHighBitsInput(Cond, DAG))
10299 Cond = Cond.getOperand(0);
10301 // We know the result of AND is compared against zero. Try to match
10303 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
10304 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG);
10305 if (NewSetCC.getNode()) {
10306 CC = NewSetCC.getOperand(0);
10307 Cond = NewSetCC.getOperand(1);
10314 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
10315 Cond = EmitTest(Cond, X86::COND_NE, DAG);
10318 // a < b ? -1 : 0 -> RES = ~setcc_carry
10319 // a < b ? 0 : -1 -> RES = setcc_carry
10320 // a >= b ? -1 : 0 -> RES = setcc_carry
10321 // a >= b ? 0 : -1 -> RES = ~setcc_carry
10322 if (Cond.getOpcode() == X86ISD::SUB) {
10323 Cond = ConvertCmpIfNecessary(Cond, DAG);
10324 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue();
10326 if ((CondCode == X86::COND_AE || CondCode == X86::COND_B) &&
10327 (isAllOnes(Op1) || isAllOnes(Op2)) && (isZero(Op1) || isZero(Op2))) {
10328 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
10329 DAG.getConstant(X86::COND_B, MVT::i8), Cond);
10330 if (isAllOnes(Op1) != (CondCode == X86::COND_B))
10331 return DAG.getNOT(DL, Res, Res.getValueType());
10336 // X86 doesn't have an i8 cmov. If both operands are the result of a truncate
10337 // widen the cmov and push the truncate through. This avoids introducing a new
10338 // branch during isel and doesn't add any extensions.
10339 if (Op.getValueType() == MVT::i8 &&
10340 Op1.getOpcode() == ISD::TRUNCATE && Op2.getOpcode() == ISD::TRUNCATE) {
10341 SDValue T1 = Op1.getOperand(0), T2 = Op2.getOperand(0);
10342 if (T1.getValueType() == T2.getValueType() &&
10343 // Blacklist CopyFromReg to avoid partial register stalls.
10344 T1.getOpcode() != ISD::CopyFromReg && T2.getOpcode()!=ISD::CopyFromReg){
10345 SDVTList VTs = DAG.getVTList(T1.getValueType(), MVT::Glue);
10346 SDValue Cmov = DAG.getNode(X86ISD::CMOV, DL, VTs, T2, T1, CC, Cond);
10347 return DAG.getNode(ISD::TRUNCATE, DL, Op.getValueType(), Cmov);
10351 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
10352 // condition is true.
10353 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
10354 SDValue Ops[] = { Op2, Op1, CC, Cond };
10355 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops, array_lengthof(Ops));
10358 static SDValue LowerSIGN_EXTEND_AVX512(SDValue Op, SelectionDAG &DAG) {
10359 MVT VT = Op->getSimpleValueType(0);
10360 SDValue In = Op->getOperand(0);
10361 MVT InVT = In.getSimpleValueType();
10364 unsigned int NumElts = VT.getVectorNumElements();
10365 if (NumElts != 8 && NumElts != 16)
10368 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1)
10369 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
10371 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
10372 assert (InVT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
10374 MVT ExtVT = (NumElts == 8) ? MVT::v8i64 : MVT::v16i32;
10375 Constant *C = ConstantInt::get(*DAG.getContext(),
10376 APInt::getAllOnesValue(ExtVT.getScalarType().getSizeInBits()));
10378 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
10379 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
10380 SDValue Ld = DAG.getLoad(ExtVT.getScalarType(), dl, DAG.getEntryNode(), CP,
10381 MachinePointerInfo::getConstantPool(),
10382 false, false, false, Alignment);
10383 SDValue Brcst = DAG.getNode(X86ISD::VBROADCASTM, dl, ExtVT, In, Ld);
10384 if (VT.is512BitVector())
10386 return DAG.getNode(X86ISD::VTRUNC, dl, VT, Brcst);
10389 static SDValue LowerSIGN_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
10390 SelectionDAG &DAG) {
10391 MVT VT = Op->getSimpleValueType(0);
10392 SDValue In = Op->getOperand(0);
10393 MVT InVT = In.getSimpleValueType();
10396 if (VT.is512BitVector() || InVT.getVectorElementType() == MVT::i1)
10397 return LowerSIGN_EXTEND_AVX512(Op, DAG);
10399 if ((VT != MVT::v4i64 || InVT != MVT::v4i32) &&
10400 (VT != MVT::v8i32 || InVT != MVT::v8i16))
10403 if (Subtarget->hasInt256())
10404 return DAG.getNode(X86ISD::VSEXT_MOVL, dl, VT, In);
10406 // Optimize vectors in AVX mode
10407 // Sign extend v8i16 to v8i32 and
10410 // Divide input vector into two parts
10411 // for v4i32 the shuffle mask will be { 0, 1, -1, -1} {2, 3, -1, -1}
10412 // use vpmovsx instruction to extend v4i32 -> v2i64; v8i16 -> v4i32
10413 // concat the vectors to original VT
10415 unsigned NumElems = InVT.getVectorNumElements();
10416 SDValue Undef = DAG.getUNDEF(InVT);
10418 SmallVector<int,8> ShufMask1(NumElems, -1);
10419 for (unsigned i = 0; i != NumElems/2; ++i)
10422 SDValue OpLo = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask1[0]);
10424 SmallVector<int,8> ShufMask2(NumElems, -1);
10425 for (unsigned i = 0; i != NumElems/2; ++i)
10426 ShufMask2[i] = i + NumElems/2;
10428 SDValue OpHi = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask2[0]);
10430 MVT HalfVT = MVT::getVectorVT(VT.getScalarType(),
10431 VT.getVectorNumElements()/2);
10433 OpLo = DAG.getNode(X86ISD::VSEXT_MOVL, dl, HalfVT, OpLo);
10434 OpHi = DAG.getNode(X86ISD::VSEXT_MOVL, dl, HalfVT, OpHi);
10436 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
10439 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
10440 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
10441 // from the AND / OR.
10442 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
10443 Opc = Op.getOpcode();
10444 if (Opc != ISD::OR && Opc != ISD::AND)
10446 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
10447 Op.getOperand(0).hasOneUse() &&
10448 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
10449 Op.getOperand(1).hasOneUse());
10452 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
10453 // 1 and that the SETCC node has a single use.
10454 static bool isXor1OfSetCC(SDValue Op) {
10455 if (Op.getOpcode() != ISD::XOR)
10457 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
10458 if (N1C && N1C->getAPIntValue() == 1) {
10459 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
10460 Op.getOperand(0).hasOneUse();
10465 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
10466 bool addTest = true;
10467 SDValue Chain = Op.getOperand(0);
10468 SDValue Cond = Op.getOperand(1);
10469 SDValue Dest = Op.getOperand(2);
10472 bool Inverted = false;
10474 if (Cond.getOpcode() == ISD::SETCC) {
10475 // Check for setcc([su]{add,sub,mul}o == 0).
10476 if (cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETEQ &&
10477 isa<ConstantSDNode>(Cond.getOperand(1)) &&
10478 cast<ConstantSDNode>(Cond.getOperand(1))->isNullValue() &&
10479 Cond.getOperand(0).getResNo() == 1 &&
10480 (Cond.getOperand(0).getOpcode() == ISD::SADDO ||
10481 Cond.getOperand(0).getOpcode() == ISD::UADDO ||
10482 Cond.getOperand(0).getOpcode() == ISD::SSUBO ||
10483 Cond.getOperand(0).getOpcode() == ISD::USUBO ||
10484 Cond.getOperand(0).getOpcode() == ISD::SMULO ||
10485 Cond.getOperand(0).getOpcode() == ISD::UMULO)) {
10487 Cond = Cond.getOperand(0);
10489 SDValue NewCond = LowerSETCC(Cond, DAG);
10490 if (NewCond.getNode())
10495 // FIXME: LowerXALUO doesn't handle these!!
10496 else if (Cond.getOpcode() == X86ISD::ADD ||
10497 Cond.getOpcode() == X86ISD::SUB ||
10498 Cond.getOpcode() == X86ISD::SMUL ||
10499 Cond.getOpcode() == X86ISD::UMUL)
10500 Cond = LowerXALUO(Cond, DAG);
10503 // Look pass (and (setcc_carry (cmp ...)), 1).
10504 if (Cond.getOpcode() == ISD::AND &&
10505 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
10506 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
10507 if (C && C->getAPIntValue() == 1)
10508 Cond = Cond.getOperand(0);
10511 // If condition flag is set by a X86ISD::CMP, then use it as the condition
10512 // setting operand in place of the X86ISD::SETCC.
10513 unsigned CondOpcode = Cond.getOpcode();
10514 if (CondOpcode == X86ISD::SETCC ||
10515 CondOpcode == X86ISD::SETCC_CARRY) {
10516 CC = Cond.getOperand(0);
10518 SDValue Cmp = Cond.getOperand(1);
10519 unsigned Opc = Cmp.getOpcode();
10520 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
10521 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
10525 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
10529 // These can only come from an arithmetic instruction with overflow,
10530 // e.g. SADDO, UADDO.
10531 Cond = Cond.getNode()->getOperand(1);
10537 CondOpcode = Cond.getOpcode();
10538 if (CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
10539 CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
10540 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
10541 Cond.getOperand(0).getValueType() != MVT::i8)) {
10542 SDValue LHS = Cond.getOperand(0);
10543 SDValue RHS = Cond.getOperand(1);
10544 unsigned X86Opcode;
10547 switch (CondOpcode) {
10548 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
10549 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
10550 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
10551 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
10552 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
10553 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
10554 default: llvm_unreachable("unexpected overflowing operator");
10557 X86Cond = X86::GetOppositeBranchCondition((X86::CondCode)X86Cond);
10558 if (CondOpcode == ISD::UMULO)
10559 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
10562 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
10564 SDValue X86Op = DAG.getNode(X86Opcode, dl, VTs, LHS, RHS);
10566 if (CondOpcode == ISD::UMULO)
10567 Cond = X86Op.getValue(2);
10569 Cond = X86Op.getValue(1);
10571 CC = DAG.getConstant(X86Cond, MVT::i8);
10575 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
10576 SDValue Cmp = Cond.getOperand(0).getOperand(1);
10577 if (CondOpc == ISD::OR) {
10578 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
10579 // two branches instead of an explicit OR instruction with a
10581 if (Cmp == Cond.getOperand(1).getOperand(1) &&
10582 isX86LogicalCmp(Cmp)) {
10583 CC = Cond.getOperand(0).getOperand(0);
10584 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
10585 Chain, Dest, CC, Cmp);
10586 CC = Cond.getOperand(1).getOperand(0);
10590 } else { // ISD::AND
10591 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
10592 // two branches instead of an explicit AND instruction with a
10593 // separate test. However, we only do this if this block doesn't
10594 // have a fall-through edge, because this requires an explicit
10595 // jmp when the condition is false.
10596 if (Cmp == Cond.getOperand(1).getOperand(1) &&
10597 isX86LogicalCmp(Cmp) &&
10598 Op.getNode()->hasOneUse()) {
10599 X86::CondCode CCode =
10600 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
10601 CCode = X86::GetOppositeBranchCondition(CCode);
10602 CC = DAG.getConstant(CCode, MVT::i8);
10603 SDNode *User = *Op.getNode()->use_begin();
10604 // Look for an unconditional branch following this conditional branch.
10605 // We need this because we need to reverse the successors in order
10606 // to implement FCMP_OEQ.
10607 if (User->getOpcode() == ISD::BR) {
10608 SDValue FalseBB = User->getOperand(1);
10610 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
10611 assert(NewBR == User);
10615 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
10616 Chain, Dest, CC, Cmp);
10617 X86::CondCode CCode =
10618 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
10619 CCode = X86::GetOppositeBranchCondition(CCode);
10620 CC = DAG.getConstant(CCode, MVT::i8);
10626 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
10627 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
10628 // It should be transformed during dag combiner except when the condition
10629 // is set by a arithmetics with overflow node.
10630 X86::CondCode CCode =
10631 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
10632 CCode = X86::GetOppositeBranchCondition(CCode);
10633 CC = DAG.getConstant(CCode, MVT::i8);
10634 Cond = Cond.getOperand(0).getOperand(1);
10636 } else if (Cond.getOpcode() == ISD::SETCC &&
10637 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETOEQ) {
10638 // For FCMP_OEQ, we can emit
10639 // two branches instead of an explicit AND instruction with a
10640 // separate test. However, we only do this if this block doesn't
10641 // have a fall-through edge, because this requires an explicit
10642 // jmp when the condition is false.
10643 if (Op.getNode()->hasOneUse()) {
10644 SDNode *User = *Op.getNode()->use_begin();
10645 // Look for an unconditional branch following this conditional branch.
10646 // We need this because we need to reverse the successors in order
10647 // to implement FCMP_OEQ.
10648 if (User->getOpcode() == ISD::BR) {
10649 SDValue FalseBB = User->getOperand(1);
10651 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
10652 assert(NewBR == User);
10656 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
10657 Cond.getOperand(0), Cond.getOperand(1));
10658 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
10659 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
10660 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
10661 Chain, Dest, CC, Cmp);
10662 CC = DAG.getConstant(X86::COND_P, MVT::i8);
10667 } else if (Cond.getOpcode() == ISD::SETCC &&
10668 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETUNE) {
10669 // For FCMP_UNE, we can emit
10670 // two branches instead of an explicit AND instruction with a
10671 // separate test. However, we only do this if this block doesn't
10672 // have a fall-through edge, because this requires an explicit
10673 // jmp when the condition is false.
10674 if (Op.getNode()->hasOneUse()) {
10675 SDNode *User = *Op.getNode()->use_begin();
10676 // Look for an unconditional branch following this conditional branch.
10677 // We need this because we need to reverse the successors in order
10678 // to implement FCMP_UNE.
10679 if (User->getOpcode() == ISD::BR) {
10680 SDValue FalseBB = User->getOperand(1);
10682 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
10683 assert(NewBR == User);
10686 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
10687 Cond.getOperand(0), Cond.getOperand(1));
10688 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
10689 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
10690 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
10691 Chain, Dest, CC, Cmp);
10692 CC = DAG.getConstant(X86::COND_NP, MVT::i8);
10702 // Look pass the truncate if the high bits are known zero.
10703 if (isTruncWithZeroHighBitsInput(Cond, DAG))
10704 Cond = Cond.getOperand(0);
10706 // We know the result of AND is compared against zero. Try to match
10708 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
10709 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
10710 if (NewSetCC.getNode()) {
10711 CC = NewSetCC.getOperand(0);
10712 Cond = NewSetCC.getOperand(1);
10719 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
10720 Cond = EmitTest(Cond, X86::COND_NE, DAG);
10722 Cond = ConvertCmpIfNecessary(Cond, DAG);
10723 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
10724 Chain, Dest, CC, Cond);
10727 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
10728 // Calls to _alloca is needed to probe the stack when allocating more than 4k
10729 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
10730 // that the guard pages used by the OS virtual memory manager are allocated in
10731 // correct sequence.
10733 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
10734 SelectionDAG &DAG) const {
10735 assert((Subtarget->isTargetCygMing() || Subtarget->isTargetWindows() ||
10736 getTargetMachine().Options.EnableSegmentedStacks) &&
10737 "This should be used only on Windows targets or when segmented stacks "
10739 assert(!Subtarget->isTargetEnvMacho() && "Not implemented");
10743 SDValue Chain = Op.getOperand(0);
10744 SDValue Size = Op.getOperand(1);
10745 // FIXME: Ensure alignment here
10747 bool Is64Bit = Subtarget->is64Bit();
10748 EVT SPTy = Is64Bit ? MVT::i64 : MVT::i32;
10750 if (getTargetMachine().Options.EnableSegmentedStacks) {
10751 MachineFunction &MF = DAG.getMachineFunction();
10752 MachineRegisterInfo &MRI = MF.getRegInfo();
10755 // The 64 bit implementation of segmented stacks needs to clobber both r10
10756 // r11. This makes it impossible to use it along with nested parameters.
10757 const Function *F = MF.getFunction();
10759 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
10761 if (I->hasNestAttr())
10762 report_fatal_error("Cannot use segmented stacks with functions that "
10763 "have nested arguments.");
10766 const TargetRegisterClass *AddrRegClass =
10767 getRegClassFor(Subtarget->is64Bit() ? MVT::i64:MVT::i32);
10768 unsigned Vreg = MRI.createVirtualRegister(AddrRegClass);
10769 Chain = DAG.getCopyToReg(Chain, dl, Vreg, Size);
10770 SDValue Value = DAG.getNode(X86ISD::SEG_ALLOCA, dl, SPTy, Chain,
10771 DAG.getRegister(Vreg, SPTy));
10772 SDValue Ops1[2] = { Value, Chain };
10773 return DAG.getMergeValues(Ops1, 2, dl);
10776 unsigned Reg = (Subtarget->is64Bit() ? X86::RAX : X86::EAX);
10778 Chain = DAG.getCopyToReg(Chain, dl, Reg, Size, Flag);
10779 Flag = Chain.getValue(1);
10780 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
10782 Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag);
10783 Flag = Chain.getValue(1);
10785 const X86RegisterInfo *RegInfo =
10786 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
10787 Chain = DAG.getCopyFromReg(Chain, dl, RegInfo->getStackRegister(),
10790 SDValue Ops1[2] = { Chain.getValue(0), Chain };
10791 return DAG.getMergeValues(Ops1, 2, dl);
10795 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
10796 MachineFunction &MF = DAG.getMachineFunction();
10797 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
10799 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
10802 if (!Subtarget->is64Bit() || Subtarget->isTargetWin64()) {
10803 // vastart just stores the address of the VarArgsFrameIndex slot into the
10804 // memory location argument.
10805 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
10807 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
10808 MachinePointerInfo(SV), false, false, 0);
10812 // gp_offset (0 - 6 * 8)
10813 // fp_offset (48 - 48 + 8 * 16)
10814 // overflow_arg_area (point to parameters coming in memory).
10816 SmallVector<SDValue, 8> MemOps;
10817 SDValue FIN = Op.getOperand(1);
10819 SDValue Store = DAG.getStore(Op.getOperand(0), DL,
10820 DAG.getConstant(FuncInfo->getVarArgsGPOffset(),
10822 FIN, MachinePointerInfo(SV), false, false, 0);
10823 MemOps.push_back(Store);
10826 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
10827 FIN, DAG.getIntPtrConstant(4));
10828 Store = DAG.getStore(Op.getOperand(0), DL,
10829 DAG.getConstant(FuncInfo->getVarArgsFPOffset(),
10831 FIN, MachinePointerInfo(SV, 4), false, false, 0);
10832 MemOps.push_back(Store);
10834 // Store ptr to overflow_arg_area
10835 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
10836 FIN, DAG.getIntPtrConstant(4));
10837 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
10839 Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN,
10840 MachinePointerInfo(SV, 8),
10842 MemOps.push_back(Store);
10844 // Store ptr to reg_save_area.
10845 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
10846 FIN, DAG.getIntPtrConstant(8));
10847 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
10849 Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN,
10850 MachinePointerInfo(SV, 16), false, false, 0);
10851 MemOps.push_back(Store);
10852 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
10853 &MemOps[0], MemOps.size());
10856 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
10857 assert(Subtarget->is64Bit() &&
10858 "LowerVAARG only handles 64-bit va_arg!");
10859 assert((Subtarget->isTargetLinux() ||
10860 Subtarget->isTargetDarwin()) &&
10861 "Unhandled target in LowerVAARG");
10862 assert(Op.getNode()->getNumOperands() == 4);
10863 SDValue Chain = Op.getOperand(0);
10864 SDValue SrcPtr = Op.getOperand(1);
10865 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
10866 unsigned Align = Op.getConstantOperandVal(3);
10869 EVT ArgVT = Op.getNode()->getValueType(0);
10870 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
10871 uint32_t ArgSize = getDataLayout()->getTypeAllocSize(ArgTy);
10874 // Decide which area this value should be read from.
10875 // TODO: Implement the AMD64 ABI in its entirety. This simple
10876 // selection mechanism works only for the basic types.
10877 if (ArgVT == MVT::f80) {
10878 llvm_unreachable("va_arg for f80 not yet implemented");
10879 } else if (ArgVT.isFloatingPoint() && ArgSize <= 16 /*bytes*/) {
10880 ArgMode = 2; // Argument passed in XMM register. Use fp_offset.
10881 } else if (ArgVT.isInteger() && ArgSize <= 32 /*bytes*/) {
10882 ArgMode = 1; // Argument passed in GPR64 register(s). Use gp_offset.
10884 llvm_unreachable("Unhandled argument type in LowerVAARG");
10887 if (ArgMode == 2) {
10888 // Sanity Check: Make sure using fp_offset makes sense.
10889 assert(!getTargetMachine().Options.UseSoftFloat &&
10890 !(DAG.getMachineFunction()
10891 .getFunction()->getAttributes()
10892 .hasAttribute(AttributeSet::FunctionIndex,
10893 Attribute::NoImplicitFloat)) &&
10894 Subtarget->hasSSE1());
10897 // Insert VAARG_64 node into the DAG
10898 // VAARG_64 returns two values: Variable Argument Address, Chain
10899 SmallVector<SDValue, 11> InstOps;
10900 InstOps.push_back(Chain);
10901 InstOps.push_back(SrcPtr);
10902 InstOps.push_back(DAG.getConstant(ArgSize, MVT::i32));
10903 InstOps.push_back(DAG.getConstant(ArgMode, MVT::i8));
10904 InstOps.push_back(DAG.getConstant(Align, MVT::i32));
10905 SDVTList VTs = DAG.getVTList(getPointerTy(), MVT::Other);
10906 SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl,
10907 VTs, &InstOps[0], InstOps.size(),
10909 MachinePointerInfo(SV),
10911 /*Volatile=*/false,
10913 /*WriteMem=*/true);
10914 Chain = VAARG.getValue(1);
10916 // Load the next argument and return it
10917 return DAG.getLoad(ArgVT, dl,
10920 MachinePointerInfo(),
10921 false, false, false, 0);
10924 static SDValue LowerVACOPY(SDValue Op, const X86Subtarget *Subtarget,
10925 SelectionDAG &DAG) {
10926 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
10927 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
10928 SDValue Chain = Op.getOperand(0);
10929 SDValue DstPtr = Op.getOperand(1);
10930 SDValue SrcPtr = Op.getOperand(2);
10931 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
10932 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
10935 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr,
10936 DAG.getIntPtrConstant(24), 8, /*isVolatile*/false,
10938 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
10941 // getTargetVShiftNode - Handle vector element shifts where the shift amount
10942 // may or may not be a constant. Takes immediate version of shift as input.
10943 static SDValue getTargetVShiftNode(unsigned Opc, SDLoc dl, EVT VT,
10944 SDValue SrcOp, SDValue ShAmt,
10945 SelectionDAG &DAG) {
10946 assert(ShAmt.getValueType() == MVT::i32 && "ShAmt is not i32");
10948 if (isa<ConstantSDNode>(ShAmt)) {
10949 // Constant may be a TargetConstant. Use a regular constant.
10950 uint32_t ShiftAmt = cast<ConstantSDNode>(ShAmt)->getZExtValue();
10952 default: llvm_unreachable("Unknown target vector shift node");
10953 case X86ISD::VSHLI:
10954 case X86ISD::VSRLI:
10955 case X86ISD::VSRAI:
10956 return DAG.getNode(Opc, dl, VT, SrcOp,
10957 DAG.getConstant(ShiftAmt, MVT::i32));
10961 // Change opcode to non-immediate version
10963 default: llvm_unreachable("Unknown target vector shift node");
10964 case X86ISD::VSHLI: Opc = X86ISD::VSHL; break;
10965 case X86ISD::VSRLI: Opc = X86ISD::VSRL; break;
10966 case X86ISD::VSRAI: Opc = X86ISD::VSRA; break;
10969 // Need to build a vector containing shift amount
10970 // Shift amount is 32-bits, but SSE instructions read 64-bit, so fill with 0
10973 ShOps[1] = DAG.getConstant(0, MVT::i32);
10974 ShOps[2] = ShOps[3] = DAG.getUNDEF(MVT::i32);
10975 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, &ShOps[0], 4);
10977 // The return type has to be a 128-bit type with the same element
10978 // type as the input type.
10979 MVT EltVT = VT.getVectorElementType().getSimpleVT();
10980 EVT ShVT = MVT::getVectorVT(EltVT, 128/EltVT.getSizeInBits());
10982 ShAmt = DAG.getNode(ISD::BITCAST, dl, ShVT, ShAmt);
10983 return DAG.getNode(Opc, dl, VT, SrcOp, ShAmt);
10986 static SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) {
10988 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
10990 default: return SDValue(); // Don't custom lower most intrinsics.
10991 // Comparison intrinsics.
10992 case Intrinsic::x86_sse_comieq_ss:
10993 case Intrinsic::x86_sse_comilt_ss:
10994 case Intrinsic::x86_sse_comile_ss:
10995 case Intrinsic::x86_sse_comigt_ss:
10996 case Intrinsic::x86_sse_comige_ss:
10997 case Intrinsic::x86_sse_comineq_ss:
10998 case Intrinsic::x86_sse_ucomieq_ss:
10999 case Intrinsic::x86_sse_ucomilt_ss:
11000 case Intrinsic::x86_sse_ucomile_ss:
11001 case Intrinsic::x86_sse_ucomigt_ss:
11002 case Intrinsic::x86_sse_ucomige_ss:
11003 case Intrinsic::x86_sse_ucomineq_ss:
11004 case Intrinsic::x86_sse2_comieq_sd:
11005 case Intrinsic::x86_sse2_comilt_sd:
11006 case Intrinsic::x86_sse2_comile_sd:
11007 case Intrinsic::x86_sse2_comigt_sd:
11008 case Intrinsic::x86_sse2_comige_sd:
11009 case Intrinsic::x86_sse2_comineq_sd:
11010 case Intrinsic::x86_sse2_ucomieq_sd:
11011 case Intrinsic::x86_sse2_ucomilt_sd:
11012 case Intrinsic::x86_sse2_ucomile_sd:
11013 case Intrinsic::x86_sse2_ucomigt_sd:
11014 case Intrinsic::x86_sse2_ucomige_sd:
11015 case Intrinsic::x86_sse2_ucomineq_sd: {
11019 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
11020 case Intrinsic::x86_sse_comieq_ss:
11021 case Intrinsic::x86_sse2_comieq_sd:
11022 Opc = X86ISD::COMI;
11025 case Intrinsic::x86_sse_comilt_ss:
11026 case Intrinsic::x86_sse2_comilt_sd:
11027 Opc = X86ISD::COMI;
11030 case Intrinsic::x86_sse_comile_ss:
11031 case Intrinsic::x86_sse2_comile_sd:
11032 Opc = X86ISD::COMI;
11035 case Intrinsic::x86_sse_comigt_ss:
11036 case Intrinsic::x86_sse2_comigt_sd:
11037 Opc = X86ISD::COMI;
11040 case Intrinsic::x86_sse_comige_ss:
11041 case Intrinsic::x86_sse2_comige_sd:
11042 Opc = X86ISD::COMI;
11045 case Intrinsic::x86_sse_comineq_ss:
11046 case Intrinsic::x86_sse2_comineq_sd:
11047 Opc = X86ISD::COMI;
11050 case Intrinsic::x86_sse_ucomieq_ss:
11051 case Intrinsic::x86_sse2_ucomieq_sd:
11052 Opc = X86ISD::UCOMI;
11055 case Intrinsic::x86_sse_ucomilt_ss:
11056 case Intrinsic::x86_sse2_ucomilt_sd:
11057 Opc = X86ISD::UCOMI;
11060 case Intrinsic::x86_sse_ucomile_ss:
11061 case Intrinsic::x86_sse2_ucomile_sd:
11062 Opc = X86ISD::UCOMI;
11065 case Intrinsic::x86_sse_ucomigt_ss:
11066 case Intrinsic::x86_sse2_ucomigt_sd:
11067 Opc = X86ISD::UCOMI;
11070 case Intrinsic::x86_sse_ucomige_ss:
11071 case Intrinsic::x86_sse2_ucomige_sd:
11072 Opc = X86ISD::UCOMI;
11075 case Intrinsic::x86_sse_ucomineq_ss:
11076 case Intrinsic::x86_sse2_ucomineq_sd:
11077 Opc = X86ISD::UCOMI;
11082 SDValue LHS = Op.getOperand(1);
11083 SDValue RHS = Op.getOperand(2);
11084 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG);
11085 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!");
11086 SDValue Cond = DAG.getNode(Opc, dl, MVT::i32, LHS, RHS);
11087 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
11088 DAG.getConstant(X86CC, MVT::i8), Cond);
11089 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
11092 // Arithmetic intrinsics.
11093 case Intrinsic::x86_sse2_pmulu_dq:
11094 case Intrinsic::x86_avx2_pmulu_dq:
11095 return DAG.getNode(X86ISD::PMULUDQ, dl, Op.getValueType(),
11096 Op.getOperand(1), Op.getOperand(2));
11098 // SSE2/AVX2 sub with unsigned saturation intrinsics
11099 case Intrinsic::x86_sse2_psubus_b:
11100 case Intrinsic::x86_sse2_psubus_w:
11101 case Intrinsic::x86_avx2_psubus_b:
11102 case Intrinsic::x86_avx2_psubus_w:
11103 return DAG.getNode(X86ISD::SUBUS, dl, Op.getValueType(),
11104 Op.getOperand(1), Op.getOperand(2));
11106 // SSE3/AVX horizontal add/sub intrinsics
11107 case Intrinsic::x86_sse3_hadd_ps:
11108 case Intrinsic::x86_sse3_hadd_pd:
11109 case Intrinsic::x86_avx_hadd_ps_256:
11110 case Intrinsic::x86_avx_hadd_pd_256:
11111 case Intrinsic::x86_sse3_hsub_ps:
11112 case Intrinsic::x86_sse3_hsub_pd:
11113 case Intrinsic::x86_avx_hsub_ps_256:
11114 case Intrinsic::x86_avx_hsub_pd_256:
11115 case Intrinsic::x86_ssse3_phadd_w_128:
11116 case Intrinsic::x86_ssse3_phadd_d_128:
11117 case Intrinsic::x86_avx2_phadd_w:
11118 case Intrinsic::x86_avx2_phadd_d:
11119 case Intrinsic::x86_ssse3_phsub_w_128:
11120 case Intrinsic::x86_ssse3_phsub_d_128:
11121 case Intrinsic::x86_avx2_phsub_w:
11122 case Intrinsic::x86_avx2_phsub_d: {
11125 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
11126 case Intrinsic::x86_sse3_hadd_ps:
11127 case Intrinsic::x86_sse3_hadd_pd:
11128 case Intrinsic::x86_avx_hadd_ps_256:
11129 case Intrinsic::x86_avx_hadd_pd_256:
11130 Opcode = X86ISD::FHADD;
11132 case Intrinsic::x86_sse3_hsub_ps:
11133 case Intrinsic::x86_sse3_hsub_pd:
11134 case Intrinsic::x86_avx_hsub_ps_256:
11135 case Intrinsic::x86_avx_hsub_pd_256:
11136 Opcode = X86ISD::FHSUB;
11138 case Intrinsic::x86_ssse3_phadd_w_128:
11139 case Intrinsic::x86_ssse3_phadd_d_128:
11140 case Intrinsic::x86_avx2_phadd_w:
11141 case Intrinsic::x86_avx2_phadd_d:
11142 Opcode = X86ISD::HADD;
11144 case Intrinsic::x86_ssse3_phsub_w_128:
11145 case Intrinsic::x86_ssse3_phsub_d_128:
11146 case Intrinsic::x86_avx2_phsub_w:
11147 case Intrinsic::x86_avx2_phsub_d:
11148 Opcode = X86ISD::HSUB;
11151 return DAG.getNode(Opcode, dl, Op.getValueType(),
11152 Op.getOperand(1), Op.getOperand(2));
11155 // SSE2/SSE41/AVX2 integer max/min intrinsics.
11156 case Intrinsic::x86_sse2_pmaxu_b:
11157 case Intrinsic::x86_sse41_pmaxuw:
11158 case Intrinsic::x86_sse41_pmaxud:
11159 case Intrinsic::x86_avx2_pmaxu_b:
11160 case Intrinsic::x86_avx2_pmaxu_w:
11161 case Intrinsic::x86_avx2_pmaxu_d:
11162 case Intrinsic::x86_sse2_pminu_b:
11163 case Intrinsic::x86_sse41_pminuw:
11164 case Intrinsic::x86_sse41_pminud:
11165 case Intrinsic::x86_avx2_pminu_b:
11166 case Intrinsic::x86_avx2_pminu_w:
11167 case Intrinsic::x86_avx2_pminu_d:
11168 case Intrinsic::x86_sse41_pmaxsb:
11169 case Intrinsic::x86_sse2_pmaxs_w:
11170 case Intrinsic::x86_sse41_pmaxsd:
11171 case Intrinsic::x86_avx2_pmaxs_b:
11172 case Intrinsic::x86_avx2_pmaxs_w:
11173 case Intrinsic::x86_avx2_pmaxs_d:
11174 case Intrinsic::x86_sse41_pminsb:
11175 case Intrinsic::x86_sse2_pmins_w:
11176 case Intrinsic::x86_sse41_pminsd:
11177 case Intrinsic::x86_avx2_pmins_b:
11178 case Intrinsic::x86_avx2_pmins_w:
11179 case Intrinsic::x86_avx2_pmins_d: {
11182 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
11183 case Intrinsic::x86_sse2_pmaxu_b:
11184 case Intrinsic::x86_sse41_pmaxuw:
11185 case Intrinsic::x86_sse41_pmaxud:
11186 case Intrinsic::x86_avx2_pmaxu_b:
11187 case Intrinsic::x86_avx2_pmaxu_w:
11188 case Intrinsic::x86_avx2_pmaxu_d:
11189 Opcode = X86ISD::UMAX;
11191 case Intrinsic::x86_sse2_pminu_b:
11192 case Intrinsic::x86_sse41_pminuw:
11193 case Intrinsic::x86_sse41_pminud:
11194 case Intrinsic::x86_avx2_pminu_b:
11195 case Intrinsic::x86_avx2_pminu_w:
11196 case Intrinsic::x86_avx2_pminu_d:
11197 Opcode = X86ISD::UMIN;
11199 case Intrinsic::x86_sse41_pmaxsb:
11200 case Intrinsic::x86_sse2_pmaxs_w:
11201 case Intrinsic::x86_sse41_pmaxsd:
11202 case Intrinsic::x86_avx2_pmaxs_b:
11203 case Intrinsic::x86_avx2_pmaxs_w:
11204 case Intrinsic::x86_avx2_pmaxs_d:
11205 Opcode = X86ISD::SMAX;
11207 case Intrinsic::x86_sse41_pminsb:
11208 case Intrinsic::x86_sse2_pmins_w:
11209 case Intrinsic::x86_sse41_pminsd:
11210 case Intrinsic::x86_avx2_pmins_b:
11211 case Intrinsic::x86_avx2_pmins_w:
11212 case Intrinsic::x86_avx2_pmins_d:
11213 Opcode = X86ISD::SMIN;
11216 return DAG.getNode(Opcode, dl, Op.getValueType(),
11217 Op.getOperand(1), Op.getOperand(2));
11220 // SSE/SSE2/AVX floating point max/min intrinsics.
11221 case Intrinsic::x86_sse_max_ps:
11222 case Intrinsic::x86_sse2_max_pd:
11223 case Intrinsic::x86_avx_max_ps_256:
11224 case Intrinsic::x86_avx_max_pd_256:
11225 case Intrinsic::x86_avx512_max_ps_512:
11226 case Intrinsic::x86_avx512_max_pd_512:
11227 case Intrinsic::x86_sse_min_ps:
11228 case Intrinsic::x86_sse2_min_pd:
11229 case Intrinsic::x86_avx_min_ps_256:
11230 case Intrinsic::x86_avx_min_pd_256:
11231 case Intrinsic::x86_avx512_min_ps_512:
11232 case Intrinsic::x86_avx512_min_pd_512: {
11235 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
11236 case Intrinsic::x86_sse_max_ps:
11237 case Intrinsic::x86_sse2_max_pd:
11238 case Intrinsic::x86_avx_max_ps_256:
11239 case Intrinsic::x86_avx_max_pd_256:
11240 case Intrinsic::x86_avx512_max_ps_512:
11241 case Intrinsic::x86_avx512_max_pd_512:
11242 Opcode = X86ISD::FMAX;
11244 case Intrinsic::x86_sse_min_ps:
11245 case Intrinsic::x86_sse2_min_pd:
11246 case Intrinsic::x86_avx_min_ps_256:
11247 case Intrinsic::x86_avx_min_pd_256:
11248 case Intrinsic::x86_avx512_min_ps_512:
11249 case Intrinsic::x86_avx512_min_pd_512:
11250 Opcode = X86ISD::FMIN;
11253 return DAG.getNode(Opcode, dl, Op.getValueType(),
11254 Op.getOperand(1), Op.getOperand(2));
11257 // AVX2 variable shift intrinsics
11258 case Intrinsic::x86_avx2_psllv_d:
11259 case Intrinsic::x86_avx2_psllv_q:
11260 case Intrinsic::x86_avx2_psllv_d_256:
11261 case Intrinsic::x86_avx2_psllv_q_256:
11262 case Intrinsic::x86_avx2_psrlv_d:
11263 case Intrinsic::x86_avx2_psrlv_q:
11264 case Intrinsic::x86_avx2_psrlv_d_256:
11265 case Intrinsic::x86_avx2_psrlv_q_256:
11266 case Intrinsic::x86_avx2_psrav_d:
11267 case Intrinsic::x86_avx2_psrav_d_256: {
11270 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
11271 case Intrinsic::x86_avx2_psllv_d:
11272 case Intrinsic::x86_avx2_psllv_q:
11273 case Intrinsic::x86_avx2_psllv_d_256:
11274 case Intrinsic::x86_avx2_psllv_q_256:
11277 case Intrinsic::x86_avx2_psrlv_d:
11278 case Intrinsic::x86_avx2_psrlv_q:
11279 case Intrinsic::x86_avx2_psrlv_d_256:
11280 case Intrinsic::x86_avx2_psrlv_q_256:
11283 case Intrinsic::x86_avx2_psrav_d:
11284 case Intrinsic::x86_avx2_psrav_d_256:
11288 return DAG.getNode(Opcode, dl, Op.getValueType(),
11289 Op.getOperand(1), Op.getOperand(2));
11292 case Intrinsic::x86_ssse3_pshuf_b_128:
11293 case Intrinsic::x86_avx2_pshuf_b:
11294 return DAG.getNode(X86ISD::PSHUFB, dl, Op.getValueType(),
11295 Op.getOperand(1), Op.getOperand(2));
11297 case Intrinsic::x86_ssse3_psign_b_128:
11298 case Intrinsic::x86_ssse3_psign_w_128:
11299 case Intrinsic::x86_ssse3_psign_d_128:
11300 case Intrinsic::x86_avx2_psign_b:
11301 case Intrinsic::x86_avx2_psign_w:
11302 case Intrinsic::x86_avx2_psign_d:
11303 return DAG.getNode(X86ISD::PSIGN, dl, Op.getValueType(),
11304 Op.getOperand(1), Op.getOperand(2));
11306 case Intrinsic::x86_sse41_insertps:
11307 return DAG.getNode(X86ISD::INSERTPS, dl, Op.getValueType(),
11308 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
11310 case Intrinsic::x86_avx_vperm2f128_ps_256:
11311 case Intrinsic::x86_avx_vperm2f128_pd_256:
11312 case Intrinsic::x86_avx_vperm2f128_si_256:
11313 case Intrinsic::x86_avx2_vperm2i128:
11314 return DAG.getNode(X86ISD::VPERM2X128, dl, Op.getValueType(),
11315 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
11317 case Intrinsic::x86_avx2_permd:
11318 case Intrinsic::x86_avx2_permps:
11319 // Operands intentionally swapped. Mask is last operand to intrinsic,
11320 // but second operand for node/instruction.
11321 return DAG.getNode(X86ISD::VPERMV, dl, Op.getValueType(),
11322 Op.getOperand(2), Op.getOperand(1));
11324 case Intrinsic::x86_sse_sqrt_ps:
11325 case Intrinsic::x86_sse2_sqrt_pd:
11326 case Intrinsic::x86_avx_sqrt_ps_256:
11327 case Intrinsic::x86_avx_sqrt_pd_256:
11328 return DAG.getNode(ISD::FSQRT, dl, Op.getValueType(), Op.getOperand(1));
11330 // ptest and testp intrinsics. The intrinsic these come from are designed to
11331 // return an integer value, not just an instruction so lower it to the ptest
11332 // or testp pattern and a setcc for the result.
11333 case Intrinsic::x86_sse41_ptestz:
11334 case Intrinsic::x86_sse41_ptestc:
11335 case Intrinsic::x86_sse41_ptestnzc:
11336 case Intrinsic::x86_avx_ptestz_256:
11337 case Intrinsic::x86_avx_ptestc_256:
11338 case Intrinsic::x86_avx_ptestnzc_256:
11339 case Intrinsic::x86_avx_vtestz_ps:
11340 case Intrinsic::x86_avx_vtestc_ps:
11341 case Intrinsic::x86_avx_vtestnzc_ps:
11342 case Intrinsic::x86_avx_vtestz_pd:
11343 case Intrinsic::x86_avx_vtestc_pd:
11344 case Intrinsic::x86_avx_vtestnzc_pd:
11345 case Intrinsic::x86_avx_vtestz_ps_256:
11346 case Intrinsic::x86_avx_vtestc_ps_256:
11347 case Intrinsic::x86_avx_vtestnzc_ps_256:
11348 case Intrinsic::x86_avx_vtestz_pd_256:
11349 case Intrinsic::x86_avx_vtestc_pd_256:
11350 case Intrinsic::x86_avx_vtestnzc_pd_256: {
11351 bool IsTestPacked = false;
11354 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
11355 case Intrinsic::x86_avx_vtestz_ps:
11356 case Intrinsic::x86_avx_vtestz_pd:
11357 case Intrinsic::x86_avx_vtestz_ps_256:
11358 case Intrinsic::x86_avx_vtestz_pd_256:
11359 IsTestPacked = true; // Fallthrough
11360 case Intrinsic::x86_sse41_ptestz:
11361 case Intrinsic::x86_avx_ptestz_256:
11363 X86CC = X86::COND_E;
11365 case Intrinsic::x86_avx_vtestc_ps:
11366 case Intrinsic::x86_avx_vtestc_pd:
11367 case Intrinsic::x86_avx_vtestc_ps_256:
11368 case Intrinsic::x86_avx_vtestc_pd_256:
11369 IsTestPacked = true; // Fallthrough
11370 case Intrinsic::x86_sse41_ptestc:
11371 case Intrinsic::x86_avx_ptestc_256:
11373 X86CC = X86::COND_B;
11375 case Intrinsic::x86_avx_vtestnzc_ps:
11376 case Intrinsic::x86_avx_vtestnzc_pd:
11377 case Intrinsic::x86_avx_vtestnzc_ps_256:
11378 case Intrinsic::x86_avx_vtestnzc_pd_256:
11379 IsTestPacked = true; // Fallthrough
11380 case Intrinsic::x86_sse41_ptestnzc:
11381 case Intrinsic::x86_avx_ptestnzc_256:
11383 X86CC = X86::COND_A;
11387 SDValue LHS = Op.getOperand(1);
11388 SDValue RHS = Op.getOperand(2);
11389 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST;
11390 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS);
11391 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
11392 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
11393 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
11395 case Intrinsic::x86_avx512_kortestz:
11396 case Intrinsic::x86_avx512_kortestc: {
11397 unsigned X86CC = (IntNo == Intrinsic::x86_avx512_kortestz)? X86::COND_E: X86::COND_B;
11398 SDValue LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1, Op.getOperand(1));
11399 SDValue RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1, Op.getOperand(2));
11400 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
11401 SDValue Test = DAG.getNode(X86ISD::KORTEST, dl, MVT::i32, LHS, RHS);
11402 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
11403 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
11406 // SSE/AVX shift intrinsics
11407 case Intrinsic::x86_sse2_psll_w:
11408 case Intrinsic::x86_sse2_psll_d:
11409 case Intrinsic::x86_sse2_psll_q:
11410 case Intrinsic::x86_avx2_psll_w:
11411 case Intrinsic::x86_avx2_psll_d:
11412 case Intrinsic::x86_avx2_psll_q:
11413 case Intrinsic::x86_sse2_psrl_w:
11414 case Intrinsic::x86_sse2_psrl_d:
11415 case Intrinsic::x86_sse2_psrl_q:
11416 case Intrinsic::x86_avx2_psrl_w:
11417 case Intrinsic::x86_avx2_psrl_d:
11418 case Intrinsic::x86_avx2_psrl_q:
11419 case Intrinsic::x86_sse2_psra_w:
11420 case Intrinsic::x86_sse2_psra_d:
11421 case Intrinsic::x86_avx2_psra_w:
11422 case Intrinsic::x86_avx2_psra_d: {
11425 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
11426 case Intrinsic::x86_sse2_psll_w:
11427 case Intrinsic::x86_sse2_psll_d:
11428 case Intrinsic::x86_sse2_psll_q:
11429 case Intrinsic::x86_avx2_psll_w:
11430 case Intrinsic::x86_avx2_psll_d:
11431 case Intrinsic::x86_avx2_psll_q:
11432 Opcode = X86ISD::VSHL;
11434 case Intrinsic::x86_sse2_psrl_w:
11435 case Intrinsic::x86_sse2_psrl_d:
11436 case Intrinsic::x86_sse2_psrl_q:
11437 case Intrinsic::x86_avx2_psrl_w:
11438 case Intrinsic::x86_avx2_psrl_d:
11439 case Intrinsic::x86_avx2_psrl_q:
11440 Opcode = X86ISD::VSRL;
11442 case Intrinsic::x86_sse2_psra_w:
11443 case Intrinsic::x86_sse2_psra_d:
11444 case Intrinsic::x86_avx2_psra_w:
11445 case Intrinsic::x86_avx2_psra_d:
11446 Opcode = X86ISD::VSRA;
11449 return DAG.getNode(Opcode, dl, Op.getValueType(),
11450 Op.getOperand(1), Op.getOperand(2));
11453 // SSE/AVX immediate shift intrinsics
11454 case Intrinsic::x86_sse2_pslli_w:
11455 case Intrinsic::x86_sse2_pslli_d:
11456 case Intrinsic::x86_sse2_pslli_q:
11457 case Intrinsic::x86_avx2_pslli_w:
11458 case Intrinsic::x86_avx2_pslli_d:
11459 case Intrinsic::x86_avx2_pslli_q:
11460 case Intrinsic::x86_sse2_psrli_w:
11461 case Intrinsic::x86_sse2_psrli_d:
11462 case Intrinsic::x86_sse2_psrli_q:
11463 case Intrinsic::x86_avx2_psrli_w:
11464 case Intrinsic::x86_avx2_psrli_d:
11465 case Intrinsic::x86_avx2_psrli_q:
11466 case Intrinsic::x86_sse2_psrai_w:
11467 case Intrinsic::x86_sse2_psrai_d:
11468 case Intrinsic::x86_avx2_psrai_w:
11469 case Intrinsic::x86_avx2_psrai_d: {
11472 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
11473 case Intrinsic::x86_sse2_pslli_w:
11474 case Intrinsic::x86_sse2_pslli_d:
11475 case Intrinsic::x86_sse2_pslli_q:
11476 case Intrinsic::x86_avx2_pslli_w:
11477 case Intrinsic::x86_avx2_pslli_d:
11478 case Intrinsic::x86_avx2_pslli_q:
11479 Opcode = X86ISD::VSHLI;
11481 case Intrinsic::x86_sse2_psrli_w:
11482 case Intrinsic::x86_sse2_psrli_d:
11483 case Intrinsic::x86_sse2_psrli_q:
11484 case Intrinsic::x86_avx2_psrli_w:
11485 case Intrinsic::x86_avx2_psrli_d:
11486 case Intrinsic::x86_avx2_psrli_q:
11487 Opcode = X86ISD::VSRLI;
11489 case Intrinsic::x86_sse2_psrai_w:
11490 case Intrinsic::x86_sse2_psrai_d:
11491 case Intrinsic::x86_avx2_psrai_w:
11492 case Intrinsic::x86_avx2_psrai_d:
11493 Opcode = X86ISD::VSRAI;
11496 return getTargetVShiftNode(Opcode, dl, Op.getValueType(),
11497 Op.getOperand(1), Op.getOperand(2), DAG);
11500 case Intrinsic::x86_sse42_pcmpistria128:
11501 case Intrinsic::x86_sse42_pcmpestria128:
11502 case Intrinsic::x86_sse42_pcmpistric128:
11503 case Intrinsic::x86_sse42_pcmpestric128:
11504 case Intrinsic::x86_sse42_pcmpistrio128:
11505 case Intrinsic::x86_sse42_pcmpestrio128:
11506 case Intrinsic::x86_sse42_pcmpistris128:
11507 case Intrinsic::x86_sse42_pcmpestris128:
11508 case Intrinsic::x86_sse42_pcmpistriz128:
11509 case Intrinsic::x86_sse42_pcmpestriz128: {
11513 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
11514 case Intrinsic::x86_sse42_pcmpistria128:
11515 Opcode = X86ISD::PCMPISTRI;
11516 X86CC = X86::COND_A;
11518 case Intrinsic::x86_sse42_pcmpestria128:
11519 Opcode = X86ISD::PCMPESTRI;
11520 X86CC = X86::COND_A;
11522 case Intrinsic::x86_sse42_pcmpistric128:
11523 Opcode = X86ISD::PCMPISTRI;
11524 X86CC = X86::COND_B;
11526 case Intrinsic::x86_sse42_pcmpestric128:
11527 Opcode = X86ISD::PCMPESTRI;
11528 X86CC = X86::COND_B;
11530 case Intrinsic::x86_sse42_pcmpistrio128:
11531 Opcode = X86ISD::PCMPISTRI;
11532 X86CC = X86::COND_O;
11534 case Intrinsic::x86_sse42_pcmpestrio128:
11535 Opcode = X86ISD::PCMPESTRI;
11536 X86CC = X86::COND_O;
11538 case Intrinsic::x86_sse42_pcmpistris128:
11539 Opcode = X86ISD::PCMPISTRI;
11540 X86CC = X86::COND_S;
11542 case Intrinsic::x86_sse42_pcmpestris128:
11543 Opcode = X86ISD::PCMPESTRI;
11544 X86CC = X86::COND_S;
11546 case Intrinsic::x86_sse42_pcmpistriz128:
11547 Opcode = X86ISD::PCMPISTRI;
11548 X86CC = X86::COND_E;
11550 case Intrinsic::x86_sse42_pcmpestriz128:
11551 Opcode = X86ISD::PCMPESTRI;
11552 X86CC = X86::COND_E;
11555 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
11556 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
11557 SDValue PCMP = DAG.getNode(Opcode, dl, VTs, NewOps.data(), NewOps.size());
11558 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
11559 DAG.getConstant(X86CC, MVT::i8),
11560 SDValue(PCMP.getNode(), 1));
11561 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
11564 case Intrinsic::x86_sse42_pcmpistri128:
11565 case Intrinsic::x86_sse42_pcmpestri128: {
11567 if (IntNo == Intrinsic::x86_sse42_pcmpistri128)
11568 Opcode = X86ISD::PCMPISTRI;
11570 Opcode = X86ISD::PCMPESTRI;
11572 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
11573 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
11574 return DAG.getNode(Opcode, dl, VTs, NewOps.data(), NewOps.size());
11576 case Intrinsic::x86_fma_vfmadd_ps:
11577 case Intrinsic::x86_fma_vfmadd_pd:
11578 case Intrinsic::x86_fma_vfmsub_ps:
11579 case Intrinsic::x86_fma_vfmsub_pd:
11580 case Intrinsic::x86_fma_vfnmadd_ps:
11581 case Intrinsic::x86_fma_vfnmadd_pd:
11582 case Intrinsic::x86_fma_vfnmsub_ps:
11583 case Intrinsic::x86_fma_vfnmsub_pd:
11584 case Intrinsic::x86_fma_vfmaddsub_ps:
11585 case Intrinsic::x86_fma_vfmaddsub_pd:
11586 case Intrinsic::x86_fma_vfmsubadd_ps:
11587 case Intrinsic::x86_fma_vfmsubadd_pd:
11588 case Intrinsic::x86_fma_vfmadd_ps_256:
11589 case Intrinsic::x86_fma_vfmadd_pd_256:
11590 case Intrinsic::x86_fma_vfmsub_ps_256:
11591 case Intrinsic::x86_fma_vfmsub_pd_256:
11592 case Intrinsic::x86_fma_vfnmadd_ps_256:
11593 case Intrinsic::x86_fma_vfnmadd_pd_256:
11594 case Intrinsic::x86_fma_vfnmsub_ps_256:
11595 case Intrinsic::x86_fma_vfnmsub_pd_256:
11596 case Intrinsic::x86_fma_vfmaddsub_ps_256:
11597 case Intrinsic::x86_fma_vfmaddsub_pd_256:
11598 case Intrinsic::x86_fma_vfmsubadd_ps_256:
11599 case Intrinsic::x86_fma_vfmsubadd_pd_256: {
11602 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
11603 case Intrinsic::x86_fma_vfmadd_ps:
11604 case Intrinsic::x86_fma_vfmadd_pd:
11605 case Intrinsic::x86_fma_vfmadd_ps_256:
11606 case Intrinsic::x86_fma_vfmadd_pd_256:
11607 Opc = X86ISD::FMADD;
11609 case Intrinsic::x86_fma_vfmsub_ps:
11610 case Intrinsic::x86_fma_vfmsub_pd:
11611 case Intrinsic::x86_fma_vfmsub_ps_256:
11612 case Intrinsic::x86_fma_vfmsub_pd_256:
11613 Opc = X86ISD::FMSUB;
11615 case Intrinsic::x86_fma_vfnmadd_ps:
11616 case Intrinsic::x86_fma_vfnmadd_pd:
11617 case Intrinsic::x86_fma_vfnmadd_ps_256:
11618 case Intrinsic::x86_fma_vfnmadd_pd_256:
11619 Opc = X86ISD::FNMADD;
11621 case Intrinsic::x86_fma_vfnmsub_ps:
11622 case Intrinsic::x86_fma_vfnmsub_pd:
11623 case Intrinsic::x86_fma_vfnmsub_ps_256:
11624 case Intrinsic::x86_fma_vfnmsub_pd_256:
11625 Opc = X86ISD::FNMSUB;
11627 case Intrinsic::x86_fma_vfmaddsub_ps:
11628 case Intrinsic::x86_fma_vfmaddsub_pd:
11629 case Intrinsic::x86_fma_vfmaddsub_ps_256:
11630 case Intrinsic::x86_fma_vfmaddsub_pd_256:
11631 Opc = X86ISD::FMADDSUB;
11633 case Intrinsic::x86_fma_vfmsubadd_ps:
11634 case Intrinsic::x86_fma_vfmsubadd_pd:
11635 case Intrinsic::x86_fma_vfmsubadd_ps_256:
11636 case Intrinsic::x86_fma_vfmsubadd_pd_256:
11637 Opc = X86ISD::FMSUBADD;
11641 return DAG.getNode(Opc, dl, Op.getValueType(), Op.getOperand(1),
11642 Op.getOperand(2), Op.getOperand(3));
11647 static SDValue getGatherNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
11648 SDValue Base, SDValue Index,
11649 SDValue ScaleOp, SDValue Chain,
11650 const X86Subtarget * Subtarget) {
11652 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
11653 assert(C && "Invalid scale type");
11654 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
11655 SDValue Src = getZeroVector(Op.getValueType(), Subtarget, DAG, dl);
11656 EVT MaskVT = MVT::getVectorVT(MVT::i1,
11657 Index.getValueType().getVectorNumElements());
11658 SDValue MaskInReg = DAG.getConstant(~0, MaskVT);
11659 SDVTList VTs = DAG.getVTList(Op.getValueType(), MaskVT, MVT::Other);
11660 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
11661 SDValue Segment = DAG.getRegister(0, MVT::i32);
11662 SDValue Ops[] = {Src, MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
11663 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
11664 SDValue RetOps[] = { SDValue(Res, 0), SDValue(Res, 2) };
11665 return DAG.getMergeValues(RetOps, array_lengthof(RetOps), dl);
11668 static SDValue getMGatherNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
11669 SDValue Src, SDValue Mask, SDValue Base,
11670 SDValue Index, SDValue ScaleOp, SDValue Chain,
11671 const X86Subtarget * Subtarget) {
11673 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
11674 assert(C && "Invalid scale type");
11675 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
11676 EVT MaskVT = MVT::getVectorVT(MVT::i1,
11677 Index.getValueType().getVectorNumElements());
11678 SDValue MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
11679 SDVTList VTs = DAG.getVTList(Op.getValueType(), MaskVT, MVT::Other);
11680 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
11681 SDValue Segment = DAG.getRegister(0, MVT::i32);
11682 if (Src.getOpcode() == ISD::UNDEF)
11683 Src = getZeroVector(Op.getValueType(), Subtarget, DAG, dl);
11684 SDValue Ops[] = {Src, MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
11685 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
11686 SDValue RetOps[] = { SDValue(Res, 0), SDValue(Res, 2) };
11687 return DAG.getMergeValues(RetOps, array_lengthof(RetOps), dl);
11690 static SDValue getScatterNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
11691 SDValue Src, SDValue Base, SDValue Index,
11692 SDValue ScaleOp, SDValue Chain) {
11694 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
11695 assert(C && "Invalid scale type");
11696 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
11697 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
11698 SDValue Segment = DAG.getRegister(0, MVT::i32);
11699 EVT MaskVT = MVT::getVectorVT(MVT::i1,
11700 Index.getValueType().getVectorNumElements());
11701 SDValue MaskInReg = DAG.getConstant(~0, MaskVT);
11702 SDVTList VTs = DAG.getVTList(MaskVT, MVT::Other);
11703 SDValue Ops[] = {Base, Scale, Index, Disp, Segment, MaskInReg, Src, Chain};
11704 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
11705 return SDValue(Res, 1);
11708 static SDValue getMScatterNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
11709 SDValue Src, SDValue Mask, SDValue Base,
11710 SDValue Index, SDValue ScaleOp, SDValue Chain) {
11712 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
11713 assert(C && "Invalid scale type");
11714 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
11715 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
11716 SDValue Segment = DAG.getRegister(0, MVT::i32);
11717 EVT MaskVT = MVT::getVectorVT(MVT::i1,
11718 Index.getValueType().getVectorNumElements());
11719 SDValue MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
11720 SDVTList VTs = DAG.getVTList(MaskVT, MVT::Other);
11721 SDValue Ops[] = {Base, Scale, Index, Disp, Segment, MaskInReg, Src, Chain};
11722 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
11723 return SDValue(Res, 1);
11726 static SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
11727 SelectionDAG &DAG) {
11729 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
11731 default: return SDValue(); // Don't custom lower most intrinsics.
11733 // RDRAND/RDSEED intrinsics.
11734 case Intrinsic::x86_rdrand_16:
11735 case Intrinsic::x86_rdrand_32:
11736 case Intrinsic::x86_rdrand_64:
11737 case Intrinsic::x86_rdseed_16:
11738 case Intrinsic::x86_rdseed_32:
11739 case Intrinsic::x86_rdseed_64: {
11740 unsigned Opcode = (IntNo == Intrinsic::x86_rdseed_16 ||
11741 IntNo == Intrinsic::x86_rdseed_32 ||
11742 IntNo == Intrinsic::x86_rdseed_64) ? X86ISD::RDSEED :
11744 // Emit the node with the right value type.
11745 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Glue, MVT::Other);
11746 SDValue Result = DAG.getNode(Opcode, dl, VTs, Op.getOperand(0));
11748 // If the value returned by RDRAND/RDSEED was valid (CF=1), return 1.
11749 // Otherwise return the value from Rand, which is always 0, casted to i32.
11750 SDValue Ops[] = { DAG.getZExtOrTrunc(Result, dl, Op->getValueType(1)),
11751 DAG.getConstant(1, Op->getValueType(1)),
11752 DAG.getConstant(X86::COND_B, MVT::i32),
11753 SDValue(Result.getNode(), 1) };
11754 SDValue isValid = DAG.getNode(X86ISD::CMOV, dl,
11755 DAG.getVTList(Op->getValueType(1), MVT::Glue),
11756 Ops, array_lengthof(Ops));
11758 // Return { result, isValid, chain }.
11759 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(), Result, isValid,
11760 SDValue(Result.getNode(), 2));
11762 //int_gather(index, base, scale);
11763 case Intrinsic::x86_avx512_gather_qpd_512:
11764 case Intrinsic::x86_avx512_gather_qps_512:
11765 case Intrinsic::x86_avx512_gather_dpd_512:
11766 case Intrinsic::x86_avx512_gather_qpi_512:
11767 case Intrinsic::x86_avx512_gather_qpq_512:
11768 case Intrinsic::x86_avx512_gather_dpq_512:
11769 case Intrinsic::x86_avx512_gather_dps_512:
11770 case Intrinsic::x86_avx512_gather_dpi_512: {
11773 default: llvm_unreachable("Unexpected intrinsic!");
11774 case Intrinsic::x86_avx512_gather_qps_512: Opc = X86::VGATHERQPSZrm; break;
11775 case Intrinsic::x86_avx512_gather_qpd_512: Opc = X86::VGATHERQPDZrm; break;
11776 case Intrinsic::x86_avx512_gather_dpd_512: Opc = X86::VGATHERDPDZrm; break;
11777 case Intrinsic::x86_avx512_gather_dps_512: Opc = X86::VGATHERDPSZrm; break;
11778 case Intrinsic::x86_avx512_gather_qpi_512: Opc = X86::VPGATHERQDZrm; break;
11779 case Intrinsic::x86_avx512_gather_qpq_512: Opc = X86::VPGATHERQQZrm; break;
11780 case Intrinsic::x86_avx512_gather_dpi_512: Opc = X86::VPGATHERDDZrm; break;
11781 case Intrinsic::x86_avx512_gather_dpq_512: Opc = X86::VPGATHERDQZrm; break;
11783 SDValue Chain = Op.getOperand(0);
11784 SDValue Index = Op.getOperand(2);
11785 SDValue Base = Op.getOperand(3);
11786 SDValue Scale = Op.getOperand(4);
11787 return getGatherNode(Opc, Op, DAG, Base, Index, Scale, Chain, Subtarget);
11789 //int_gather_mask(v1, mask, index, base, scale);
11790 case Intrinsic::x86_avx512_gather_qps_mask_512:
11791 case Intrinsic::x86_avx512_gather_qpd_mask_512:
11792 case Intrinsic::x86_avx512_gather_dpd_mask_512:
11793 case Intrinsic::x86_avx512_gather_dps_mask_512:
11794 case Intrinsic::x86_avx512_gather_qpi_mask_512:
11795 case Intrinsic::x86_avx512_gather_qpq_mask_512:
11796 case Intrinsic::x86_avx512_gather_dpi_mask_512:
11797 case Intrinsic::x86_avx512_gather_dpq_mask_512: {
11800 default: llvm_unreachable("Unexpected intrinsic!");
11801 case Intrinsic::x86_avx512_gather_qps_mask_512:
11802 Opc = X86::VGATHERQPSZrm; break;
11803 case Intrinsic::x86_avx512_gather_qpd_mask_512:
11804 Opc = X86::VGATHERQPDZrm; break;
11805 case Intrinsic::x86_avx512_gather_dpd_mask_512:
11806 Opc = X86::VGATHERDPDZrm; break;
11807 case Intrinsic::x86_avx512_gather_dps_mask_512:
11808 Opc = X86::VGATHERDPSZrm; break;
11809 case Intrinsic::x86_avx512_gather_qpi_mask_512:
11810 Opc = X86::VPGATHERQDZrm; break;
11811 case Intrinsic::x86_avx512_gather_qpq_mask_512:
11812 Opc = X86::VPGATHERQQZrm; break;
11813 case Intrinsic::x86_avx512_gather_dpi_mask_512:
11814 Opc = X86::VPGATHERDDZrm; break;
11815 case Intrinsic::x86_avx512_gather_dpq_mask_512:
11816 Opc = X86::VPGATHERDQZrm; break;
11818 SDValue Chain = Op.getOperand(0);
11819 SDValue Src = Op.getOperand(2);
11820 SDValue Mask = Op.getOperand(3);
11821 SDValue Index = Op.getOperand(4);
11822 SDValue Base = Op.getOperand(5);
11823 SDValue Scale = Op.getOperand(6);
11824 return getMGatherNode(Opc, Op, DAG, Src, Mask, Base, Index, Scale, Chain,
11827 //int_scatter(base, index, v1, scale);
11828 case Intrinsic::x86_avx512_scatter_qpd_512:
11829 case Intrinsic::x86_avx512_scatter_qps_512:
11830 case Intrinsic::x86_avx512_scatter_dpd_512:
11831 case Intrinsic::x86_avx512_scatter_qpi_512:
11832 case Intrinsic::x86_avx512_scatter_qpq_512:
11833 case Intrinsic::x86_avx512_scatter_dpq_512:
11834 case Intrinsic::x86_avx512_scatter_dps_512:
11835 case Intrinsic::x86_avx512_scatter_dpi_512: {
11838 default: llvm_unreachable("Unexpected intrinsic!");
11839 case Intrinsic::x86_avx512_scatter_qpd_512:
11840 Opc = X86::VSCATTERQPDZmr; break;
11841 case Intrinsic::x86_avx512_scatter_qps_512:
11842 Opc = X86::VSCATTERQPSZmr; break;
11843 case Intrinsic::x86_avx512_scatter_dpd_512:
11844 Opc = X86::VSCATTERDPDZmr; break;
11845 case Intrinsic::x86_avx512_scatter_dps_512:
11846 Opc = X86::VSCATTERDPSZmr; break;
11847 case Intrinsic::x86_avx512_scatter_qpi_512:
11848 Opc = X86::VPSCATTERQDZmr; break;
11849 case Intrinsic::x86_avx512_scatter_qpq_512:
11850 Opc = X86::VPSCATTERQQZmr; break;
11851 case Intrinsic::x86_avx512_scatter_dpq_512:
11852 Opc = X86::VPSCATTERDQZmr; break;
11853 case Intrinsic::x86_avx512_scatter_dpi_512:
11854 Opc = X86::VPSCATTERDDZmr; break;
11856 SDValue Chain = Op.getOperand(0);
11857 SDValue Base = Op.getOperand(2);
11858 SDValue Index = Op.getOperand(3);
11859 SDValue Src = Op.getOperand(4);
11860 SDValue Scale = Op.getOperand(5);
11861 return getScatterNode(Opc, Op, DAG, Src, Base, Index, Scale, Chain);
11863 //int_scatter_mask(base, mask, index, v1, scale);
11864 case Intrinsic::x86_avx512_scatter_qps_mask_512:
11865 case Intrinsic::x86_avx512_scatter_qpd_mask_512:
11866 case Intrinsic::x86_avx512_scatter_dpd_mask_512:
11867 case Intrinsic::x86_avx512_scatter_dps_mask_512:
11868 case Intrinsic::x86_avx512_scatter_qpi_mask_512:
11869 case Intrinsic::x86_avx512_scatter_qpq_mask_512:
11870 case Intrinsic::x86_avx512_scatter_dpi_mask_512:
11871 case Intrinsic::x86_avx512_scatter_dpq_mask_512: {
11874 default: llvm_unreachable("Unexpected intrinsic!");
11875 case Intrinsic::x86_avx512_scatter_qpd_mask_512:
11876 Opc = X86::VSCATTERQPDZmr; break;
11877 case Intrinsic::x86_avx512_scatter_qps_mask_512:
11878 Opc = X86::VSCATTERQPSZmr; break;
11879 case Intrinsic::x86_avx512_scatter_dpd_mask_512:
11880 Opc = X86::VSCATTERDPDZmr; break;
11881 case Intrinsic::x86_avx512_scatter_dps_mask_512:
11882 Opc = X86::VSCATTERDPSZmr; break;
11883 case Intrinsic::x86_avx512_scatter_qpi_mask_512:
11884 Opc = X86::VPSCATTERQDZmr; break;
11885 case Intrinsic::x86_avx512_scatter_qpq_mask_512:
11886 Opc = X86::VPSCATTERQQZmr; break;
11887 case Intrinsic::x86_avx512_scatter_dpq_mask_512:
11888 Opc = X86::VPSCATTERDQZmr; break;
11889 case Intrinsic::x86_avx512_scatter_dpi_mask_512:
11890 Opc = X86::VPSCATTERDDZmr; break;
11892 SDValue Chain = Op.getOperand(0);
11893 SDValue Base = Op.getOperand(2);
11894 SDValue Mask = Op.getOperand(3);
11895 SDValue Index = Op.getOperand(4);
11896 SDValue Src = Op.getOperand(5);
11897 SDValue Scale = Op.getOperand(6);
11898 return getMScatterNode(Opc, Op, DAG, Src, Mask, Base, Index, Scale, Chain);
11900 // XTEST intrinsics.
11901 case Intrinsic::x86_xtest: {
11902 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
11903 SDValue InTrans = DAG.getNode(X86ISD::XTEST, dl, VTs, Op.getOperand(0));
11904 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
11905 DAG.getConstant(X86::COND_NE, MVT::i8),
11907 SDValue Ret = DAG.getNode(ISD::ZERO_EXTEND, dl, Op->getValueType(0), SetCC);
11908 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(),
11909 Ret, SDValue(InTrans.getNode(), 1));
11914 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op,
11915 SelectionDAG &DAG) const {
11916 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
11917 MFI->setReturnAddressIsTaken(true);
11919 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
11921 EVT PtrVT = getPointerTy();
11924 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
11925 const X86RegisterInfo *RegInfo =
11926 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
11927 SDValue Offset = DAG.getConstant(RegInfo->getSlotSize(), PtrVT);
11928 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
11929 DAG.getNode(ISD::ADD, dl, PtrVT,
11930 FrameAddr, Offset),
11931 MachinePointerInfo(), false, false, false, 0);
11934 // Just load the return address.
11935 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
11936 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
11937 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
11940 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
11941 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
11942 MFI->setFrameAddressIsTaken(true);
11944 EVT VT = Op.getValueType();
11945 SDLoc dl(Op); // FIXME probably not meaningful
11946 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
11947 const X86RegisterInfo *RegInfo =
11948 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
11949 unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction());
11950 assert(((FrameReg == X86::RBP && VT == MVT::i64) ||
11951 (FrameReg == X86::EBP && VT == MVT::i32)) &&
11952 "Invalid Frame Register!");
11953 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
11955 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
11956 MachinePointerInfo(),
11957 false, false, false, 0);
11961 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
11962 SelectionDAG &DAG) const {
11963 const X86RegisterInfo *RegInfo =
11964 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
11965 return DAG.getIntPtrConstant(2 * RegInfo->getSlotSize());
11968 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
11969 SDValue Chain = Op.getOperand(0);
11970 SDValue Offset = Op.getOperand(1);
11971 SDValue Handler = Op.getOperand(2);
11974 EVT PtrVT = getPointerTy();
11975 const X86RegisterInfo *RegInfo =
11976 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
11977 unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction());
11978 assert(((FrameReg == X86::RBP && PtrVT == MVT::i64) ||
11979 (FrameReg == X86::EBP && PtrVT == MVT::i32)) &&
11980 "Invalid Frame Register!");
11981 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, PtrVT);
11982 unsigned StoreAddrReg = (PtrVT == MVT::i64) ? X86::RCX : X86::ECX;
11984 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, Frame,
11985 DAG.getIntPtrConstant(RegInfo->getSlotSize()));
11986 StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, StoreAddr, Offset);
11987 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(),
11989 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
11991 return DAG.getNode(X86ISD::EH_RETURN, dl, MVT::Other, Chain,
11992 DAG.getRegister(StoreAddrReg, PtrVT));
11995 SDValue X86TargetLowering::lowerEH_SJLJ_SETJMP(SDValue Op,
11996 SelectionDAG &DAG) const {
11998 return DAG.getNode(X86ISD::EH_SJLJ_SETJMP, DL,
11999 DAG.getVTList(MVT::i32, MVT::Other),
12000 Op.getOperand(0), Op.getOperand(1));
12003 SDValue X86TargetLowering::lowerEH_SJLJ_LONGJMP(SDValue Op,
12004 SelectionDAG &DAG) const {
12006 return DAG.getNode(X86ISD::EH_SJLJ_LONGJMP, DL, MVT::Other,
12007 Op.getOperand(0), Op.getOperand(1));
12010 static SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) {
12011 return Op.getOperand(0);
12014 SDValue X86TargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
12015 SelectionDAG &DAG) const {
12016 SDValue Root = Op.getOperand(0);
12017 SDValue Trmp = Op.getOperand(1); // trampoline
12018 SDValue FPtr = Op.getOperand(2); // nested function
12019 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
12022 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
12023 const TargetRegisterInfo* TRI = getTargetMachine().getRegisterInfo();
12025 if (Subtarget->is64Bit()) {
12026 SDValue OutChains[6];
12028 // Large code-model.
12029 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode.
12030 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode.
12032 const unsigned char N86R10 = TRI->getEncodingValue(X86::R10) & 0x7;
12033 const unsigned char N86R11 = TRI->getEncodingValue(X86::R11) & 0x7;
12035 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
12037 // Load the pointer to the nested function into R11.
12038 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
12039 SDValue Addr = Trmp;
12040 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
12041 Addr, MachinePointerInfo(TrmpAddr),
12044 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
12045 DAG.getConstant(2, MVT::i64));
12046 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr,
12047 MachinePointerInfo(TrmpAddr, 2),
12050 // Load the 'nest' parameter value into R10.
12051 // R10 is specified in X86CallingConv.td
12052 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
12053 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
12054 DAG.getConstant(10, MVT::i64));
12055 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
12056 Addr, MachinePointerInfo(TrmpAddr, 10),
12059 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
12060 DAG.getConstant(12, MVT::i64));
12061 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr,
12062 MachinePointerInfo(TrmpAddr, 12),
12065 // Jump to the nested function.
12066 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
12067 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
12068 DAG.getConstant(20, MVT::i64));
12069 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
12070 Addr, MachinePointerInfo(TrmpAddr, 20),
12073 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
12074 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
12075 DAG.getConstant(22, MVT::i64));
12076 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr,
12077 MachinePointerInfo(TrmpAddr, 22),
12080 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 6);
12082 const Function *Func =
12083 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
12084 CallingConv::ID CC = Func->getCallingConv();
12089 llvm_unreachable("Unsupported calling convention");
12090 case CallingConv::C:
12091 case CallingConv::X86_StdCall: {
12092 // Pass 'nest' parameter in ECX.
12093 // Must be kept in sync with X86CallingConv.td
12094 NestReg = X86::ECX;
12096 // Check that ECX wasn't needed by an 'inreg' parameter.
12097 FunctionType *FTy = Func->getFunctionType();
12098 const AttributeSet &Attrs = Func->getAttributes();
12100 if (!Attrs.isEmpty() && !Func->isVarArg()) {
12101 unsigned InRegCount = 0;
12104 for (FunctionType::param_iterator I = FTy->param_begin(),
12105 E = FTy->param_end(); I != E; ++I, ++Idx)
12106 if (Attrs.hasAttribute(Idx, Attribute::InReg))
12107 // FIXME: should only count parameters that are lowered to integers.
12108 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32;
12110 if (InRegCount > 2) {
12111 report_fatal_error("Nest register in use - reduce number of inreg"
12117 case CallingConv::X86_FastCall:
12118 case CallingConv::X86_ThisCall:
12119 case CallingConv::Fast:
12120 // Pass 'nest' parameter in EAX.
12121 // Must be kept in sync with X86CallingConv.td
12122 NestReg = X86::EAX;
12126 SDValue OutChains[4];
12127 SDValue Addr, Disp;
12129 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
12130 DAG.getConstant(10, MVT::i32));
12131 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
12133 // This is storing the opcode for MOV32ri.
12134 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte.
12135 const unsigned char N86Reg = TRI->getEncodingValue(NestReg) & 0x7;
12136 OutChains[0] = DAG.getStore(Root, dl,
12137 DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
12138 Trmp, MachinePointerInfo(TrmpAddr),
12141 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
12142 DAG.getConstant(1, MVT::i32));
12143 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr,
12144 MachinePointerInfo(TrmpAddr, 1),
12147 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode.
12148 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
12149 DAG.getConstant(5, MVT::i32));
12150 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr,
12151 MachinePointerInfo(TrmpAddr, 5),
12154 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
12155 DAG.getConstant(6, MVT::i32));
12156 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr,
12157 MachinePointerInfo(TrmpAddr, 6),
12160 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 4);
12164 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op,
12165 SelectionDAG &DAG) const {
12167 The rounding mode is in bits 11:10 of FPSR, and has the following
12169 00 Round to nearest
12174 FLT_ROUNDS, on the other hand, expects the following:
12181 To perform the conversion, we do:
12182 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
12185 MachineFunction &MF = DAG.getMachineFunction();
12186 const TargetMachine &TM = MF.getTarget();
12187 const TargetFrameLowering &TFI = *TM.getFrameLowering();
12188 unsigned StackAlignment = TFI.getStackAlignment();
12189 EVT VT = Op.getValueType();
12192 // Save FP Control Word to stack slot
12193 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false);
12194 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
12196 MachineMemOperand *MMO =
12197 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
12198 MachineMemOperand::MOStore, 2, 2);
12200 SDValue Ops[] = { DAG.getEntryNode(), StackSlot };
12201 SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL,
12202 DAG.getVTList(MVT::Other),
12203 Ops, array_lengthof(Ops), MVT::i16,
12206 // Load FP Control Word from stack slot
12207 SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot,
12208 MachinePointerInfo(), false, false, false, 0);
12210 // Transform as necessary
12212 DAG.getNode(ISD::SRL, DL, MVT::i16,
12213 DAG.getNode(ISD::AND, DL, MVT::i16,
12214 CWD, DAG.getConstant(0x800, MVT::i16)),
12215 DAG.getConstant(11, MVT::i8));
12217 DAG.getNode(ISD::SRL, DL, MVT::i16,
12218 DAG.getNode(ISD::AND, DL, MVT::i16,
12219 CWD, DAG.getConstant(0x400, MVT::i16)),
12220 DAG.getConstant(9, MVT::i8));
12223 DAG.getNode(ISD::AND, DL, MVT::i16,
12224 DAG.getNode(ISD::ADD, DL, MVT::i16,
12225 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2),
12226 DAG.getConstant(1, MVT::i16)),
12227 DAG.getConstant(3, MVT::i16));
12229 return DAG.getNode((VT.getSizeInBits() < 16 ?
12230 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal);
12233 static SDValue LowerCTLZ(SDValue Op, SelectionDAG &DAG) {
12234 EVT VT = Op.getValueType();
12236 unsigned NumBits = VT.getSizeInBits();
12239 Op = Op.getOperand(0);
12240 if (VT == MVT::i8) {
12241 // Zero extend to i32 since there is not an i8 bsr.
12243 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
12246 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
12247 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
12248 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
12250 // If src is zero (i.e. bsr sets ZF), returns NumBits.
12253 DAG.getConstant(NumBits+NumBits-1, OpVT),
12254 DAG.getConstant(X86::COND_E, MVT::i8),
12257 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops, array_lengthof(Ops));
12259 // Finally xor with NumBits-1.
12260 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
12263 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
12267 static SDValue LowerCTLZ_ZERO_UNDEF(SDValue Op, SelectionDAG &DAG) {
12268 EVT VT = Op.getValueType();
12270 unsigned NumBits = VT.getSizeInBits();
12273 Op = Op.getOperand(0);
12274 if (VT == MVT::i8) {
12275 // Zero extend to i32 since there is not an i8 bsr.
12277 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
12280 // Issue a bsr (scan bits in reverse).
12281 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
12282 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
12284 // And xor with NumBits-1.
12285 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
12288 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
12292 static SDValue LowerCTTZ(SDValue Op, SelectionDAG &DAG) {
12293 EVT VT = Op.getValueType();
12294 unsigned NumBits = VT.getSizeInBits();
12296 Op = Op.getOperand(0);
12298 // Issue a bsf (scan bits forward) which also sets EFLAGS.
12299 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
12300 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op);
12302 // If src is zero (i.e. bsf sets ZF), returns NumBits.
12305 DAG.getConstant(NumBits, VT),
12306 DAG.getConstant(X86::COND_E, MVT::i8),
12309 return DAG.getNode(X86ISD::CMOV, dl, VT, Ops, array_lengthof(Ops));
12312 // Lower256IntArith - Break a 256-bit integer operation into two new 128-bit
12313 // ones, and then concatenate the result back.
12314 static SDValue Lower256IntArith(SDValue Op, SelectionDAG &DAG) {
12315 EVT VT = Op.getValueType();
12317 assert(VT.is256BitVector() && VT.isInteger() &&
12318 "Unsupported value type for operation");
12320 unsigned NumElems = VT.getVectorNumElements();
12323 // Extract the LHS vectors
12324 SDValue LHS = Op.getOperand(0);
12325 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
12326 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
12328 // Extract the RHS vectors
12329 SDValue RHS = Op.getOperand(1);
12330 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
12331 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
12333 MVT EltVT = VT.getVectorElementType().getSimpleVT();
12334 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
12336 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
12337 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1),
12338 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2));
12341 static SDValue LowerADD(SDValue Op, SelectionDAG &DAG) {
12342 assert(Op.getValueType().is256BitVector() &&
12343 Op.getValueType().isInteger() &&
12344 "Only handle AVX 256-bit vector integer operation");
12345 return Lower256IntArith(Op, DAG);
12348 static SDValue LowerSUB(SDValue Op, SelectionDAG &DAG) {
12349 assert(Op.getValueType().is256BitVector() &&
12350 Op.getValueType().isInteger() &&
12351 "Only handle AVX 256-bit vector integer operation");
12352 return Lower256IntArith(Op, DAG);
12355 static SDValue LowerMUL(SDValue Op, const X86Subtarget *Subtarget,
12356 SelectionDAG &DAG) {
12358 EVT VT = Op.getValueType();
12360 // Decompose 256-bit ops into smaller 128-bit ops.
12361 if (VT.is256BitVector() && !Subtarget->hasInt256())
12362 return Lower256IntArith(Op, DAG);
12364 SDValue A = Op.getOperand(0);
12365 SDValue B = Op.getOperand(1);
12367 // Lower v4i32 mul as 2x shuffle, 2x pmuludq, 2x shuffle.
12368 if (VT == MVT::v4i32) {
12369 assert(Subtarget->hasSSE2() && !Subtarget->hasSSE41() &&
12370 "Should not custom lower when pmuldq is available!");
12372 // Extract the odd parts.
12373 static const int UnpackMask[] = { 1, -1, 3, -1 };
12374 SDValue Aodds = DAG.getVectorShuffle(VT, dl, A, A, UnpackMask);
12375 SDValue Bodds = DAG.getVectorShuffle(VT, dl, B, B, UnpackMask);
12377 // Multiply the even parts.
12378 SDValue Evens = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, A, B);
12379 // Now multiply odd parts.
12380 SDValue Odds = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, Aodds, Bodds);
12382 Evens = DAG.getNode(ISD::BITCAST, dl, VT, Evens);
12383 Odds = DAG.getNode(ISD::BITCAST, dl, VT, Odds);
12385 // Merge the two vectors back together with a shuffle. This expands into 2
12387 static const int ShufMask[] = { 0, 4, 2, 6 };
12388 return DAG.getVectorShuffle(VT, dl, Evens, Odds, ShufMask);
12391 assert((VT == MVT::v2i64 || VT == MVT::v4i64) &&
12392 "Only know how to lower V2I64/V4I64 multiply");
12394 // Ahi = psrlqi(a, 32);
12395 // Bhi = psrlqi(b, 32);
12397 // AloBlo = pmuludq(a, b);
12398 // AloBhi = pmuludq(a, Bhi);
12399 // AhiBlo = pmuludq(Ahi, b);
12401 // AloBhi = psllqi(AloBhi, 32);
12402 // AhiBlo = psllqi(AhiBlo, 32);
12403 // return AloBlo + AloBhi + AhiBlo;
12405 SDValue ShAmt = DAG.getConstant(32, MVT::i32);
12407 SDValue Ahi = DAG.getNode(X86ISD::VSRLI, dl, VT, A, ShAmt);
12408 SDValue Bhi = DAG.getNode(X86ISD::VSRLI, dl, VT, B, ShAmt);
12410 // Bit cast to 32-bit vectors for MULUDQ
12411 EVT MulVT = (VT == MVT::v2i64) ? MVT::v4i32 : MVT::v8i32;
12412 A = DAG.getNode(ISD::BITCAST, dl, MulVT, A);
12413 B = DAG.getNode(ISD::BITCAST, dl, MulVT, B);
12414 Ahi = DAG.getNode(ISD::BITCAST, dl, MulVT, Ahi);
12415 Bhi = DAG.getNode(ISD::BITCAST, dl, MulVT, Bhi);
12417 SDValue AloBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, B);
12418 SDValue AloBhi = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, Bhi);
12419 SDValue AhiBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, Ahi, B);
12421 AloBhi = DAG.getNode(X86ISD::VSHLI, dl, VT, AloBhi, ShAmt);
12422 AhiBlo = DAG.getNode(X86ISD::VSHLI, dl, VT, AhiBlo, ShAmt);
12424 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
12425 return DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
12428 static SDValue LowerSDIV(SDValue Op, SelectionDAG &DAG) {
12429 EVT VT = Op.getValueType();
12430 EVT EltTy = VT.getVectorElementType();
12431 unsigned NumElts = VT.getVectorNumElements();
12432 SDValue N0 = Op.getOperand(0);
12435 // Lower sdiv X, pow2-const.
12436 BuildVectorSDNode *C = dyn_cast<BuildVectorSDNode>(Op.getOperand(1));
12440 APInt SplatValue, SplatUndef;
12441 unsigned SplatBitSize;
12443 if (!C->isConstantSplat(SplatValue, SplatUndef, SplatBitSize,
12445 EltTy.getSizeInBits() < SplatBitSize)
12448 if ((SplatValue != 0) &&
12449 (SplatValue.isPowerOf2() || (-SplatValue).isPowerOf2())) {
12450 unsigned lg2 = SplatValue.countTrailingZeros();
12451 // Splat the sign bit.
12452 SDValue Sz = DAG.getConstant(EltTy.getSizeInBits()-1, MVT::i32);
12453 SDValue SGN = getTargetVShiftNode(X86ISD::VSRAI, dl, VT, N0, Sz, DAG);
12454 // Add (N0 < 0) ? abs2 - 1 : 0;
12455 SDValue Amt = DAG.getConstant(EltTy.getSizeInBits() - lg2, MVT::i32);
12456 SDValue SRL = getTargetVShiftNode(X86ISD::VSRLI, dl, VT, SGN, Amt, DAG);
12457 SDValue ADD = DAG.getNode(ISD::ADD, dl, VT, N0, SRL);
12458 SDValue Lg2Amt = DAG.getConstant(lg2, MVT::i32);
12459 SDValue SRA = getTargetVShiftNode(X86ISD::VSRAI, dl, VT, ADD, Lg2Amt, DAG);
12461 // If we're dividing by a positive value, we're done. Otherwise, we must
12462 // negate the result.
12463 if (SplatValue.isNonNegative())
12466 SmallVector<SDValue, 16> V(NumElts, DAG.getConstant(0, EltTy));
12467 SDValue Zero = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], NumElts);
12468 return DAG.getNode(ISD::SUB, dl, VT, Zero, SRA);
12473 static SDValue LowerScalarImmediateShift(SDValue Op, SelectionDAG &DAG,
12474 const X86Subtarget *Subtarget) {
12475 EVT VT = Op.getValueType();
12477 SDValue R = Op.getOperand(0);
12478 SDValue Amt = Op.getOperand(1);
12480 // Optimize shl/srl/sra with constant shift amount.
12481 if (isSplatVector(Amt.getNode())) {
12482 SDValue SclrAmt = Amt->getOperand(0);
12483 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(SclrAmt)) {
12484 uint64_t ShiftAmt = C->getZExtValue();
12486 if (VT == MVT::v2i64 || VT == MVT::v4i32 || VT == MVT::v8i16 ||
12487 (Subtarget->hasInt256() &&
12488 (VT == MVT::v4i64 || VT == MVT::v8i32 || VT == MVT::v16i16)) ||
12489 (Subtarget->hasAVX512() &&
12490 (VT == MVT::v8i64 || VT == MVT::v16i32))) {
12491 if (Op.getOpcode() == ISD::SHL)
12492 return DAG.getNode(X86ISD::VSHLI, dl, VT, R,
12493 DAG.getConstant(ShiftAmt, MVT::i32));
12494 if (Op.getOpcode() == ISD::SRL)
12495 return DAG.getNode(X86ISD::VSRLI, dl, VT, R,
12496 DAG.getConstant(ShiftAmt, MVT::i32));
12497 if (Op.getOpcode() == ISD::SRA && VT != MVT::v2i64 && VT != MVT::v4i64)
12498 return DAG.getNode(X86ISD::VSRAI, dl, VT, R,
12499 DAG.getConstant(ShiftAmt, MVT::i32));
12502 if (VT == MVT::v16i8) {
12503 if (Op.getOpcode() == ISD::SHL) {
12504 // Make a large shift.
12505 SDValue SHL = DAG.getNode(X86ISD::VSHLI, dl, MVT::v8i16, R,
12506 DAG.getConstant(ShiftAmt, MVT::i32));
12507 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
12508 // Zero out the rightmost bits.
12509 SmallVector<SDValue, 16> V(16,
12510 DAG.getConstant(uint8_t(-1U << ShiftAmt),
12512 return DAG.getNode(ISD::AND, dl, VT, SHL,
12513 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16));
12515 if (Op.getOpcode() == ISD::SRL) {
12516 // Make a large shift.
12517 SDValue SRL = DAG.getNode(X86ISD::VSRLI, dl, MVT::v8i16, R,
12518 DAG.getConstant(ShiftAmt, MVT::i32));
12519 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
12520 // Zero out the leftmost bits.
12521 SmallVector<SDValue, 16> V(16,
12522 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
12524 return DAG.getNode(ISD::AND, dl, VT, SRL,
12525 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16));
12527 if (Op.getOpcode() == ISD::SRA) {
12528 if (ShiftAmt == 7) {
12529 // R s>> 7 === R s< 0
12530 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
12531 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
12534 // R s>> a === ((R u>> a) ^ m) - m
12535 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
12536 SmallVector<SDValue, 16> V(16, DAG.getConstant(128 >> ShiftAmt,
12538 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16);
12539 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
12540 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
12543 llvm_unreachable("Unknown shift opcode.");
12546 if (Subtarget->hasInt256() && VT == MVT::v32i8) {
12547 if (Op.getOpcode() == ISD::SHL) {
12548 // Make a large shift.
12549 SDValue SHL = DAG.getNode(X86ISD::VSHLI, dl, MVT::v16i16, R,
12550 DAG.getConstant(ShiftAmt, MVT::i32));
12551 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
12552 // Zero out the rightmost bits.
12553 SmallVector<SDValue, 32> V(32,
12554 DAG.getConstant(uint8_t(-1U << ShiftAmt),
12556 return DAG.getNode(ISD::AND, dl, VT, SHL,
12557 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32));
12559 if (Op.getOpcode() == ISD::SRL) {
12560 // Make a large shift.
12561 SDValue SRL = DAG.getNode(X86ISD::VSRLI, dl, MVT::v16i16, R,
12562 DAG.getConstant(ShiftAmt, MVT::i32));
12563 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
12564 // Zero out the leftmost bits.
12565 SmallVector<SDValue, 32> V(32,
12566 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
12568 return DAG.getNode(ISD::AND, dl, VT, SRL,
12569 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32));
12571 if (Op.getOpcode() == ISD::SRA) {
12572 if (ShiftAmt == 7) {
12573 // R s>> 7 === R s< 0
12574 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
12575 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
12578 // R s>> a === ((R u>> a) ^ m) - m
12579 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
12580 SmallVector<SDValue, 32> V(32, DAG.getConstant(128 >> ShiftAmt,
12582 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32);
12583 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
12584 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
12587 llvm_unreachable("Unknown shift opcode.");
12592 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
12593 if (!Subtarget->is64Bit() &&
12594 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64)) &&
12595 Amt.getOpcode() == ISD::BITCAST &&
12596 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
12597 Amt = Amt.getOperand(0);
12598 unsigned Ratio = Amt.getValueType().getVectorNumElements() /
12599 VT.getVectorNumElements();
12600 unsigned RatioInLog2 = Log2_32_Ceil(Ratio);
12601 uint64_t ShiftAmt = 0;
12602 for (unsigned i = 0; i != Ratio; ++i) {
12603 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Amt.getOperand(i));
12607 ShiftAmt |= C->getZExtValue() << (i * (1 << (6 - RatioInLog2)));
12609 // Check remaining shift amounts.
12610 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
12611 uint64_t ShAmt = 0;
12612 for (unsigned j = 0; j != Ratio; ++j) {
12613 ConstantSDNode *C =
12614 dyn_cast<ConstantSDNode>(Amt.getOperand(i + j));
12618 ShAmt |= C->getZExtValue() << (j * (1 << (6 - RatioInLog2)));
12620 if (ShAmt != ShiftAmt)
12623 switch (Op.getOpcode()) {
12625 llvm_unreachable("Unknown shift opcode!");
12627 return DAG.getNode(X86ISD::VSHLI, dl, VT, R,
12628 DAG.getConstant(ShiftAmt, MVT::i32));
12630 return DAG.getNode(X86ISD::VSRLI, dl, VT, R,
12631 DAG.getConstant(ShiftAmt, MVT::i32));
12633 return DAG.getNode(X86ISD::VSRAI, dl, VT, R,
12634 DAG.getConstant(ShiftAmt, MVT::i32));
12641 static SDValue LowerScalarVariableShift(SDValue Op, SelectionDAG &DAG,
12642 const X86Subtarget* Subtarget) {
12643 EVT VT = Op.getValueType();
12645 SDValue R = Op.getOperand(0);
12646 SDValue Amt = Op.getOperand(1);
12648 if ((VT == MVT::v2i64 && Op.getOpcode() != ISD::SRA) ||
12649 VT == MVT::v4i32 || VT == MVT::v8i16 ||
12650 (Subtarget->hasInt256() &&
12651 ((VT == MVT::v4i64 && Op.getOpcode() != ISD::SRA) ||
12652 VT == MVT::v8i32 || VT == MVT::v16i16)) ||
12653 (Subtarget->hasAVX512() && (VT == MVT::v8i64 || VT == MVT::v16i32))) {
12655 EVT EltVT = VT.getVectorElementType();
12657 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
12658 unsigned NumElts = VT.getVectorNumElements();
12660 for (i = 0; i != NumElts; ++i) {
12661 if (Amt.getOperand(i).getOpcode() == ISD::UNDEF)
12665 for (j = i; j != NumElts; ++j) {
12666 SDValue Arg = Amt.getOperand(j);
12667 if (Arg.getOpcode() == ISD::UNDEF) continue;
12668 if (Arg != Amt.getOperand(i))
12671 if (i != NumElts && j == NumElts)
12672 BaseShAmt = Amt.getOperand(i);
12674 if (Amt.getOpcode() == ISD::EXTRACT_SUBVECTOR)
12675 Amt = Amt.getOperand(0);
12676 if (Amt.getOpcode() == ISD::VECTOR_SHUFFLE &&
12677 cast<ShuffleVectorSDNode>(Amt)->isSplat()) {
12678 SDValue InVec = Amt.getOperand(0);
12679 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
12680 unsigned NumElts = InVec.getValueType().getVectorNumElements();
12682 for (; i != NumElts; ++i) {
12683 SDValue Arg = InVec.getOperand(i);
12684 if (Arg.getOpcode() == ISD::UNDEF) continue;
12688 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
12689 if (ConstantSDNode *C =
12690 dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
12691 unsigned SplatIdx =
12692 cast<ShuffleVectorSDNode>(Amt)->getSplatIndex();
12693 if (C->getZExtValue() == SplatIdx)
12694 BaseShAmt = InVec.getOperand(1);
12697 if (BaseShAmt.getNode() == 0)
12698 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Amt,
12699 DAG.getIntPtrConstant(0));
12703 if (BaseShAmt.getNode()) {
12704 if (EltVT.bitsGT(MVT::i32))
12705 BaseShAmt = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, BaseShAmt);
12706 else if (EltVT.bitsLT(MVT::i32))
12707 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, BaseShAmt);
12709 switch (Op.getOpcode()) {
12711 llvm_unreachable("Unknown shift opcode!");
12713 switch (VT.getSimpleVT().SimpleTy) {
12714 default: return SDValue();
12723 return getTargetVShiftNode(X86ISD::VSHLI, dl, VT, R, BaseShAmt, DAG);
12726 switch (VT.getSimpleVT().SimpleTy) {
12727 default: return SDValue();
12734 return getTargetVShiftNode(X86ISD::VSRAI, dl, VT, R, BaseShAmt, DAG);
12737 switch (VT.getSimpleVT().SimpleTy) {
12738 default: return SDValue();
12747 return getTargetVShiftNode(X86ISD::VSRLI, dl, VT, R, BaseShAmt, DAG);
12753 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
12754 if (!Subtarget->is64Bit() &&
12755 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64) ||
12756 (Subtarget->hasAVX512() && VT == MVT::v8i64)) &&
12757 Amt.getOpcode() == ISD::BITCAST &&
12758 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
12759 Amt = Amt.getOperand(0);
12760 unsigned Ratio = Amt.getValueType().getVectorNumElements() /
12761 VT.getVectorNumElements();
12762 std::vector<SDValue> Vals(Ratio);
12763 for (unsigned i = 0; i != Ratio; ++i)
12764 Vals[i] = Amt.getOperand(i);
12765 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
12766 for (unsigned j = 0; j != Ratio; ++j)
12767 if (Vals[j] != Amt.getOperand(i + j))
12770 switch (Op.getOpcode()) {
12772 llvm_unreachable("Unknown shift opcode!");
12774 return DAG.getNode(X86ISD::VSHL, dl, VT, R, Op.getOperand(1));
12776 return DAG.getNode(X86ISD::VSRL, dl, VT, R, Op.getOperand(1));
12778 return DAG.getNode(X86ISD::VSRA, dl, VT, R, Op.getOperand(1));
12785 static SDValue LowerShift(SDValue Op, const X86Subtarget* Subtarget,
12786 SelectionDAG &DAG) {
12788 EVT VT = Op.getValueType();
12790 SDValue R = Op.getOperand(0);
12791 SDValue Amt = Op.getOperand(1);
12794 if (!Subtarget->hasSSE2())
12797 V = LowerScalarImmediateShift(Op, DAG, Subtarget);
12801 V = LowerScalarVariableShift(Op, DAG, Subtarget);
12805 if (Subtarget->hasAVX512() && (VT == MVT::v16i32 || VT == MVT::v8i64))
12807 // AVX2 has VPSLLV/VPSRAV/VPSRLV.
12808 if (Subtarget->hasInt256()) {
12809 if (Op.getOpcode() == ISD::SRL &&
12810 (VT == MVT::v2i64 || VT == MVT::v4i32 ||
12811 VT == MVT::v4i64 || VT == MVT::v8i32))
12813 if (Op.getOpcode() == ISD::SHL &&
12814 (VT == MVT::v2i64 || VT == MVT::v4i32 ||
12815 VT == MVT::v4i64 || VT == MVT::v8i32))
12817 if (Op.getOpcode() == ISD::SRA && (VT == MVT::v4i32 || VT == MVT::v8i32))
12821 // Lower SHL with variable shift amount.
12822 if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) {
12823 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(23, VT));
12825 Op = DAG.getNode(ISD::ADD, dl, VT, Op, DAG.getConstant(0x3f800000U, VT));
12826 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, Op);
12827 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op);
12828 return DAG.getNode(ISD::MUL, dl, VT, Op, R);
12830 if (VT == MVT::v16i8 && Op->getOpcode() == ISD::SHL) {
12831 assert(Subtarget->hasSSE2() && "Need SSE2 for pslli/pcmpeq.");
12834 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(5, VT));
12835 Op = DAG.getNode(ISD::BITCAST, dl, VT, Op);
12837 // Turn 'a' into a mask suitable for VSELECT
12838 SDValue VSelM = DAG.getConstant(0x80, VT);
12839 SDValue OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
12840 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
12842 SDValue CM1 = DAG.getConstant(0x0f, VT);
12843 SDValue CM2 = DAG.getConstant(0x3f, VT);
12845 // r = VSELECT(r, psllw(r & (char16)15, 4), a);
12846 SDValue M = DAG.getNode(ISD::AND, dl, VT, R, CM1);
12847 M = getTargetVShiftNode(X86ISD::VSHLI, dl, MVT::v8i16, M,
12848 DAG.getConstant(4, MVT::i32), DAG);
12849 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
12850 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
12853 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
12854 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
12855 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
12857 // r = VSELECT(r, psllw(r & (char16)63, 2), a);
12858 M = DAG.getNode(ISD::AND, dl, VT, R, CM2);
12859 M = getTargetVShiftNode(X86ISD::VSHLI, dl, MVT::v8i16, M,
12860 DAG.getConstant(2, MVT::i32), DAG);
12861 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
12862 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
12865 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
12866 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
12867 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
12869 // return VSELECT(r, r+r, a);
12870 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel,
12871 DAG.getNode(ISD::ADD, dl, VT, R, R), R);
12875 // Decompose 256-bit shifts into smaller 128-bit shifts.
12876 if (VT.is256BitVector()) {
12877 unsigned NumElems = VT.getVectorNumElements();
12878 MVT EltVT = VT.getVectorElementType().getSimpleVT();
12879 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
12881 // Extract the two vectors
12882 SDValue V1 = Extract128BitVector(R, 0, DAG, dl);
12883 SDValue V2 = Extract128BitVector(R, NumElems/2, DAG, dl);
12885 // Recreate the shift amount vectors
12886 SDValue Amt1, Amt2;
12887 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
12888 // Constant shift amount
12889 SmallVector<SDValue, 4> Amt1Csts;
12890 SmallVector<SDValue, 4> Amt2Csts;
12891 for (unsigned i = 0; i != NumElems/2; ++i)
12892 Amt1Csts.push_back(Amt->getOperand(i));
12893 for (unsigned i = NumElems/2; i != NumElems; ++i)
12894 Amt2Csts.push_back(Amt->getOperand(i));
12896 Amt1 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT,
12897 &Amt1Csts[0], NumElems/2);
12898 Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT,
12899 &Amt2Csts[0], NumElems/2);
12901 // Variable shift amount
12902 Amt1 = Extract128BitVector(Amt, 0, DAG, dl);
12903 Amt2 = Extract128BitVector(Amt, NumElems/2, DAG, dl);
12906 // Issue new vector shifts for the smaller types
12907 V1 = DAG.getNode(Op.getOpcode(), dl, NewVT, V1, Amt1);
12908 V2 = DAG.getNode(Op.getOpcode(), dl, NewVT, V2, Amt2);
12910 // Concatenate the result back
12911 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, V1, V2);
12917 static SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) {
12918 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
12919 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
12920 // looks for this combo and may remove the "setcc" instruction if the "setcc"
12921 // has only one use.
12922 SDNode *N = Op.getNode();
12923 SDValue LHS = N->getOperand(0);
12924 SDValue RHS = N->getOperand(1);
12925 unsigned BaseOp = 0;
12928 switch (Op.getOpcode()) {
12929 default: llvm_unreachable("Unknown ovf instruction!");
12931 // A subtract of one will be selected as a INC. Note that INC doesn't
12932 // set CF, so we can't do this for UADDO.
12933 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
12935 BaseOp = X86ISD::INC;
12936 Cond = X86::COND_O;
12939 BaseOp = X86ISD::ADD;
12940 Cond = X86::COND_O;
12943 BaseOp = X86ISD::ADD;
12944 Cond = X86::COND_B;
12947 // A subtract of one will be selected as a DEC. Note that DEC doesn't
12948 // set CF, so we can't do this for USUBO.
12949 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
12951 BaseOp = X86ISD::DEC;
12952 Cond = X86::COND_O;
12955 BaseOp = X86ISD::SUB;
12956 Cond = X86::COND_O;
12959 BaseOp = X86ISD::SUB;
12960 Cond = X86::COND_B;
12963 BaseOp = X86ISD::SMUL;
12964 Cond = X86::COND_O;
12966 case ISD::UMULO: { // i64, i8 = umulo lhs, rhs --> i64, i64, i32 umul lhs,rhs
12967 SDVTList VTs = DAG.getVTList(N->getValueType(0), N->getValueType(0),
12969 SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS);
12972 DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
12973 DAG.getConstant(X86::COND_O, MVT::i32),
12974 SDValue(Sum.getNode(), 2));
12976 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
12980 // Also sets EFLAGS.
12981 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
12982 SDValue Sum = DAG.getNode(BaseOp, DL, VTs, LHS, RHS);
12985 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1),
12986 DAG.getConstant(Cond, MVT::i32),
12987 SDValue(Sum.getNode(), 1));
12989 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
12992 SDValue X86TargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
12993 SelectionDAG &DAG) const {
12995 EVT ExtraVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
12996 EVT VT = Op.getValueType();
12998 if (!Subtarget->hasSSE2() || !VT.isVector())
13001 unsigned BitsDiff = VT.getScalarType().getSizeInBits() -
13002 ExtraVT.getScalarType().getSizeInBits();
13003 SDValue ShAmt = DAG.getConstant(BitsDiff, MVT::i32);
13005 switch (VT.getSimpleVT().SimpleTy) {
13006 default: return SDValue();
13009 if (!Subtarget->hasFp256())
13011 if (!Subtarget->hasInt256()) {
13012 // needs to be split
13013 unsigned NumElems = VT.getVectorNumElements();
13015 // Extract the LHS vectors
13016 SDValue LHS = Op.getOperand(0);
13017 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
13018 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
13020 MVT EltVT = VT.getVectorElementType().getSimpleVT();
13021 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
13023 EVT ExtraEltVT = ExtraVT.getVectorElementType();
13024 unsigned ExtraNumElems = ExtraVT.getVectorNumElements();
13025 ExtraVT = EVT::getVectorVT(*DAG.getContext(), ExtraEltVT,
13027 SDValue Extra = DAG.getValueType(ExtraVT);
13029 LHS1 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, Extra);
13030 LHS2 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, Extra);
13032 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, LHS1, LHS2);
13037 // (sext (vzext x)) -> (vsext x)
13038 SDValue Op0 = Op.getOperand(0);
13039 SDValue Op00 = Op0.getOperand(0);
13041 // Hopefully, this VECTOR_SHUFFLE is just a VZEXT.
13042 if (Op0.getOpcode() == ISD::BITCAST &&
13043 Op00.getOpcode() == ISD::VECTOR_SHUFFLE)
13044 Tmp1 = LowerVectorIntExtend(Op00, Subtarget, DAG);
13045 if (Tmp1.getNode()) {
13046 SDValue Tmp1Op0 = Tmp1.getOperand(0);
13047 assert(Tmp1Op0.getOpcode() == X86ISD::VZEXT &&
13048 "This optimization is invalid without a VZEXT.");
13049 return DAG.getNode(X86ISD::VSEXT, dl, VT, Tmp1Op0.getOperand(0));
13052 // If the above didn't work, then just use Shift-Left + Shift-Right.
13053 Tmp1 = getTargetVShiftNode(X86ISD::VSHLI, dl, VT, Op0, ShAmt, DAG);
13054 return getTargetVShiftNode(X86ISD::VSRAI, dl, VT, Tmp1, ShAmt, DAG);
13059 static SDValue LowerATOMIC_FENCE(SDValue Op, const X86Subtarget *Subtarget,
13060 SelectionDAG &DAG) {
13062 AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>(
13063 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue());
13064 SynchronizationScope FenceScope = static_cast<SynchronizationScope>(
13065 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
13067 // The only fence that needs an instruction is a sequentially-consistent
13068 // cross-thread fence.
13069 if (FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread) {
13070 // Use mfence if we have SSE2 or we're on x86-64 (even if we asked for
13071 // no-sse2). There isn't any reason to disable it if the target processor
13073 if (Subtarget->hasSSE2() || Subtarget->is64Bit())
13074 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
13076 SDValue Chain = Op.getOperand(0);
13077 SDValue Zero = DAG.getConstant(0, MVT::i32);
13079 DAG.getRegister(X86::ESP, MVT::i32), // Base
13080 DAG.getTargetConstant(1, MVT::i8), // Scale
13081 DAG.getRegister(0, MVT::i32), // Index
13082 DAG.getTargetConstant(0, MVT::i32), // Disp
13083 DAG.getRegister(0, MVT::i32), // Segment.
13087 SDNode *Res = DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops);
13088 return SDValue(Res, 0);
13091 // MEMBARRIER is a compiler barrier; it codegens to a no-op.
13092 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
13095 static SDValue LowerCMP_SWAP(SDValue Op, const X86Subtarget *Subtarget,
13096 SelectionDAG &DAG) {
13097 EVT T = Op.getValueType();
13101 switch(T.getSimpleVT().SimpleTy) {
13102 default: llvm_unreachable("Invalid value type!");
13103 case MVT::i8: Reg = X86::AL; size = 1; break;
13104 case MVT::i16: Reg = X86::AX; size = 2; break;
13105 case MVT::i32: Reg = X86::EAX; size = 4; break;
13107 assert(Subtarget->is64Bit() && "Node not type legal!");
13108 Reg = X86::RAX; size = 8;
13111 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg,
13112 Op.getOperand(2), SDValue());
13113 SDValue Ops[] = { cpIn.getValue(0),
13116 DAG.getTargetConstant(size, MVT::i8),
13117 cpIn.getValue(1) };
13118 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
13119 MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand();
13120 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys,
13121 Ops, array_lengthof(Ops), T, MMO);
13123 DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1));
13127 static SDValue LowerREADCYCLECOUNTER(SDValue Op, const X86Subtarget *Subtarget,
13128 SelectionDAG &DAG) {
13129 assert(Subtarget->is64Bit() && "Result not type legalized?");
13130 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
13131 SDValue TheChain = Op.getOperand(0);
13133 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
13134 SDValue rax = DAG.getCopyFromReg(rd, dl, X86::RAX, MVT::i64, rd.getValue(1));
13135 SDValue rdx = DAG.getCopyFromReg(rax.getValue(1), dl, X86::RDX, MVT::i64,
13137 SDValue Tmp = DAG.getNode(ISD::SHL, dl, MVT::i64, rdx,
13138 DAG.getConstant(32, MVT::i8));
13140 DAG.getNode(ISD::OR, dl, MVT::i64, rax, Tmp),
13143 return DAG.getMergeValues(Ops, array_lengthof(Ops), dl);
13146 static SDValue LowerBITCAST(SDValue Op, const X86Subtarget *Subtarget,
13147 SelectionDAG &DAG) {
13148 MVT SrcVT = Op.getOperand(0).getSimpleValueType();
13149 MVT DstVT = Op.getSimpleValueType();
13150 assert(Subtarget->is64Bit() && !Subtarget->hasSSE2() &&
13151 Subtarget->hasMMX() && "Unexpected custom BITCAST");
13152 assert((DstVT == MVT::i64 ||
13153 (DstVT.isVector() && DstVT.getSizeInBits()==64)) &&
13154 "Unexpected custom BITCAST");
13155 // i64 <=> MMX conversions are Legal.
13156 if (SrcVT==MVT::i64 && DstVT.isVector())
13158 if (DstVT==MVT::i64 && SrcVT.isVector())
13160 // MMX <=> MMX conversions are Legal.
13161 if (SrcVT.isVector() && DstVT.isVector())
13163 // All other conversions need to be expanded.
13167 static SDValue LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) {
13168 SDNode *Node = Op.getNode();
13170 EVT T = Node->getValueType(0);
13171 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
13172 DAG.getConstant(0, T), Node->getOperand(2));
13173 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
13174 cast<AtomicSDNode>(Node)->getMemoryVT(),
13175 Node->getOperand(0),
13176 Node->getOperand(1), negOp,
13177 cast<AtomicSDNode>(Node)->getSrcValue(),
13178 cast<AtomicSDNode>(Node)->getAlignment(),
13179 cast<AtomicSDNode>(Node)->getOrdering(),
13180 cast<AtomicSDNode>(Node)->getSynchScope());
13183 static SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) {
13184 SDNode *Node = Op.getNode();
13186 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
13188 // Convert seq_cst store -> xchg
13189 // Convert wide store -> swap (-> cmpxchg8b/cmpxchg16b)
13190 // FIXME: On 32-bit, store -> fist or movq would be more efficient
13191 // (The only way to get a 16-byte store is cmpxchg16b)
13192 // FIXME: 16-byte ATOMIC_SWAP isn't actually hooked up at the moment.
13193 if (cast<AtomicSDNode>(Node)->getOrdering() == SequentiallyConsistent ||
13194 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
13195 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
13196 cast<AtomicSDNode>(Node)->getMemoryVT(),
13197 Node->getOperand(0),
13198 Node->getOperand(1), Node->getOperand(2),
13199 cast<AtomicSDNode>(Node)->getMemOperand(),
13200 cast<AtomicSDNode>(Node)->getOrdering(),
13201 cast<AtomicSDNode>(Node)->getSynchScope());
13202 return Swap.getValue(1);
13204 // Other atomic stores have a simple pattern.
13208 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
13209 EVT VT = Op.getNode()->getValueType(0);
13211 // Let legalize expand this if it isn't a legal type yet.
13212 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
13215 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
13218 bool ExtraOp = false;
13219 switch (Op.getOpcode()) {
13220 default: llvm_unreachable("Invalid code");
13221 case ISD::ADDC: Opc = X86ISD::ADD; break;
13222 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break;
13223 case ISD::SUBC: Opc = X86ISD::SUB; break;
13224 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break;
13228 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
13230 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
13231 Op.getOperand(1), Op.getOperand(2));
13234 static SDValue LowerFSINCOS(SDValue Op, const X86Subtarget *Subtarget,
13235 SelectionDAG &DAG) {
13236 assert(Subtarget->isTargetDarwin() && Subtarget->is64Bit());
13238 // For MacOSX, we want to call an alternative entry point: __sincos_stret,
13239 // which returns the values as { float, float } (in XMM0) or
13240 // { double, double } (which is returned in XMM0, XMM1).
13242 SDValue Arg = Op.getOperand(0);
13243 EVT ArgVT = Arg.getValueType();
13244 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
13246 TargetLowering::ArgListTy Args;
13247 TargetLowering::ArgListEntry Entry;
13251 Entry.isSExt = false;
13252 Entry.isZExt = false;
13253 Args.push_back(Entry);
13255 bool isF64 = ArgVT == MVT::f64;
13256 // Only optimize x86_64 for now. i386 is a bit messy. For f32,
13257 // the small struct {f32, f32} is returned in (eax, edx). For f64,
13258 // the results are returned via SRet in memory.
13259 const char *LibcallName = isF64 ? "__sincos_stret" : "__sincosf_stret";
13260 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13261 SDValue Callee = DAG.getExternalSymbol(LibcallName, TLI.getPointerTy());
13263 Type *RetTy = isF64
13264 ? (Type*)StructType::get(ArgTy, ArgTy, NULL)
13265 : (Type*)VectorType::get(ArgTy, 4);
13267 CallLoweringInfo CLI(DAG.getEntryNode(), RetTy,
13268 false, false, false, false, 0,
13269 CallingConv::C, /*isTaillCall=*/false,
13270 /*doesNotRet=*/false, /*isReturnValueUsed*/true,
13271 Callee, Args, DAG, dl);
13272 std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI);
13275 // Returned in xmm0 and xmm1.
13276 return CallResult.first;
13278 // Returned in bits 0:31 and 32:64 xmm0.
13279 SDValue SinVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
13280 CallResult.first, DAG.getIntPtrConstant(0));
13281 SDValue CosVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
13282 CallResult.first, DAG.getIntPtrConstant(1));
13283 SDVTList Tys = DAG.getVTList(ArgVT, ArgVT);
13284 return DAG.getNode(ISD::MERGE_VALUES, dl, Tys, SinVal, CosVal);
13287 /// LowerOperation - Provide custom lowering hooks for some operations.
13289 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
13290 switch (Op.getOpcode()) {
13291 default: llvm_unreachable("Should not custom lower this!");
13292 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op,DAG);
13293 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, Subtarget, DAG);
13294 case ISD::ATOMIC_CMP_SWAP: return LowerCMP_SWAP(Op, Subtarget, DAG);
13295 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
13296 case ISD::ATOMIC_STORE: return LowerATOMIC_STORE(Op,DAG);
13297 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
13298 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
13299 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
13300 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
13301 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
13302 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op,Subtarget,DAG);
13303 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, Subtarget,DAG);
13304 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
13305 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
13306 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
13307 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
13308 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
13309 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
13310 case ISD::SHL_PARTS:
13311 case ISD::SRA_PARTS:
13312 case ISD::SRL_PARTS: return LowerShiftParts(Op, DAG);
13313 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
13314 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
13315 case ISD::TRUNCATE: return LowerTRUNCATE(Op, DAG);
13316 case ISD::ZERO_EXTEND: return LowerZERO_EXTEND(Op, Subtarget, DAG);
13317 case ISD::SIGN_EXTEND: return LowerSIGN_EXTEND(Op, Subtarget, DAG);
13318 case ISD::ANY_EXTEND: return LowerANY_EXTEND(Op, Subtarget, DAG);
13319 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
13320 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
13321 case ISD::FP_EXTEND: return LowerFP_EXTEND(Op, DAG);
13322 case ISD::FABS: return LowerFABS(Op, DAG);
13323 case ISD::FNEG: return LowerFNEG(Op, DAG);
13324 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
13325 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG);
13326 case ISD::SETCC: return LowerSETCC(Op, DAG);
13327 case ISD::SELECT: return LowerSELECT(Op, DAG);
13328 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
13329 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
13330 case ISD::VASTART: return LowerVASTART(Op, DAG);
13331 case ISD::VAARG: return LowerVAARG(Op, DAG);
13332 case ISD::VACOPY: return LowerVACOPY(Op, Subtarget, DAG);
13333 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
13334 case ISD::INTRINSIC_VOID:
13335 case ISD::INTRINSIC_W_CHAIN: return LowerINTRINSIC_W_CHAIN(Op, Subtarget, DAG);
13336 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
13337 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
13338 case ISD::FRAME_TO_ARGS_OFFSET:
13339 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
13340 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
13341 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
13342 case ISD::EH_SJLJ_SETJMP: return lowerEH_SJLJ_SETJMP(Op, DAG);
13343 case ISD::EH_SJLJ_LONGJMP: return lowerEH_SJLJ_LONGJMP(Op, DAG);
13344 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
13345 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
13346 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
13347 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
13348 case ISD::CTLZ_ZERO_UNDEF: return LowerCTLZ_ZERO_UNDEF(Op, DAG);
13349 case ISD::CTTZ: return LowerCTTZ(Op, DAG);
13350 case ISD::MUL: return LowerMUL(Op, Subtarget, DAG);
13353 case ISD::SHL: return LowerShift(Op, Subtarget, DAG);
13359 case ISD::UMULO: return LowerXALUO(Op, DAG);
13360 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, Subtarget,DAG);
13361 case ISD::BITCAST: return LowerBITCAST(Op, Subtarget, DAG);
13365 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
13366 case ISD::ADD: return LowerADD(Op, DAG);
13367 case ISD::SUB: return LowerSUB(Op, DAG);
13368 case ISD::SDIV: return LowerSDIV(Op, DAG);
13369 case ISD::FSINCOS: return LowerFSINCOS(Op, Subtarget, DAG);
13373 static void ReplaceATOMIC_LOAD(SDNode *Node,
13374 SmallVectorImpl<SDValue> &Results,
13375 SelectionDAG &DAG) {
13377 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
13379 // Convert wide load -> cmpxchg8b/cmpxchg16b
13380 // FIXME: On 32-bit, load -> fild or movq would be more efficient
13381 // (The only way to get a 16-byte load is cmpxchg16b)
13382 // FIXME: 16-byte ATOMIC_CMP_SWAP isn't actually hooked up at the moment.
13383 SDValue Zero = DAG.getConstant(0, VT);
13384 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, dl, VT,
13385 Node->getOperand(0),
13386 Node->getOperand(1), Zero, Zero,
13387 cast<AtomicSDNode>(Node)->getMemOperand(),
13388 cast<AtomicSDNode>(Node)->getOrdering(),
13389 cast<AtomicSDNode>(Node)->getSynchScope());
13390 Results.push_back(Swap.getValue(0));
13391 Results.push_back(Swap.getValue(1));
13395 ReplaceATOMIC_BINARY_64(SDNode *Node, SmallVectorImpl<SDValue>&Results,
13396 SelectionDAG &DAG, unsigned NewOp) {
13398 assert (Node->getValueType(0) == MVT::i64 &&
13399 "Only know how to expand i64 atomics");
13401 SDValue Chain = Node->getOperand(0);
13402 SDValue In1 = Node->getOperand(1);
13403 SDValue In2L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
13404 Node->getOperand(2), DAG.getIntPtrConstant(0));
13405 SDValue In2H = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
13406 Node->getOperand(2), DAG.getIntPtrConstant(1));
13407 SDValue Ops[] = { Chain, In1, In2L, In2H };
13408 SDVTList Tys = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other);
13410 DAG.getMemIntrinsicNode(NewOp, dl, Tys, Ops, array_lengthof(Ops), MVT::i64,
13411 cast<MemSDNode>(Node)->getMemOperand());
13412 SDValue OpsF[] = { Result.getValue(0), Result.getValue(1)};
13413 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2));
13414 Results.push_back(Result.getValue(2));
13417 /// ReplaceNodeResults - Replace a node with an illegal result type
13418 /// with a new node built out of custom code.
13419 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
13420 SmallVectorImpl<SDValue>&Results,
13421 SelectionDAG &DAG) const {
13423 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13424 switch (N->getOpcode()) {
13426 llvm_unreachable("Do not know how to custom type legalize this operation!");
13427 case ISD::SIGN_EXTEND_INREG:
13432 // We don't want to expand or promote these.
13434 case ISD::FP_TO_SINT:
13435 case ISD::FP_TO_UINT: {
13436 bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT;
13438 if (!IsSigned && !isIntegerTypeFTOL(SDValue(N, 0).getValueType()))
13441 std::pair<SDValue,SDValue> Vals =
13442 FP_TO_INTHelper(SDValue(N, 0), DAG, IsSigned, /*IsReplace=*/ true);
13443 SDValue FIST = Vals.first, StackSlot = Vals.second;
13444 if (FIST.getNode() != 0) {
13445 EVT VT = N->getValueType(0);
13446 // Return a load from the stack slot.
13447 if (StackSlot.getNode() != 0)
13448 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot,
13449 MachinePointerInfo(),
13450 false, false, false, 0));
13452 Results.push_back(FIST);
13456 case ISD::UINT_TO_FP: {
13457 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
13458 if (N->getOperand(0).getValueType() != MVT::v2i32 ||
13459 N->getValueType(0) != MVT::v2f32)
13461 SDValue ZExtIn = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v2i64,
13463 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
13465 SDValue VBias = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2f64, Bias, Bias);
13466 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64, ZExtIn,
13467 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, VBias));
13468 Or = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or);
13469 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, Or, VBias);
13470 Results.push_back(DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, Sub));
13473 case ISD::FP_ROUND: {
13474 if (!TLI.isTypeLegal(N->getOperand(0).getValueType()))
13476 SDValue V = DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, N->getOperand(0));
13477 Results.push_back(V);
13480 case ISD::READCYCLECOUNTER: {
13481 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
13482 SDValue TheChain = N->getOperand(0);
13483 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
13484 SDValue eax = DAG.getCopyFromReg(rd, dl, X86::EAX, MVT::i32,
13486 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), dl, X86::EDX, MVT::i32,
13488 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
13489 SDValue Ops[] = { eax, edx };
13490 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Ops,
13491 array_lengthof(Ops)));
13492 Results.push_back(edx.getValue(1));
13495 case ISD::ATOMIC_CMP_SWAP: {
13496 EVT T = N->getValueType(0);
13497 assert((T == MVT::i64 || T == MVT::i128) && "can only expand cmpxchg pair");
13498 bool Regs64bit = T == MVT::i128;
13499 EVT HalfT = Regs64bit ? MVT::i64 : MVT::i32;
13500 SDValue cpInL, cpInH;
13501 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
13502 DAG.getConstant(0, HalfT));
13503 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
13504 DAG.getConstant(1, HalfT));
13505 cpInL = DAG.getCopyToReg(N->getOperand(0), dl,
13506 Regs64bit ? X86::RAX : X86::EAX,
13508 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl,
13509 Regs64bit ? X86::RDX : X86::EDX,
13510 cpInH, cpInL.getValue(1));
13511 SDValue swapInL, swapInH;
13512 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
13513 DAG.getConstant(0, HalfT));
13514 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
13515 DAG.getConstant(1, HalfT));
13516 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl,
13517 Regs64bit ? X86::RBX : X86::EBX,
13518 swapInL, cpInH.getValue(1));
13519 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl,
13520 Regs64bit ? X86::RCX : X86::ECX,
13521 swapInH, swapInL.getValue(1));
13522 SDValue Ops[] = { swapInH.getValue(0),
13524 swapInH.getValue(1) };
13525 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
13526 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand();
13527 unsigned Opcode = Regs64bit ? X86ISD::LCMPXCHG16_DAG :
13528 X86ISD::LCMPXCHG8_DAG;
13529 SDValue Result = DAG.getMemIntrinsicNode(Opcode, dl, Tys,
13530 Ops, array_lengthof(Ops), T, MMO);
13531 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl,
13532 Regs64bit ? X86::RAX : X86::EAX,
13533 HalfT, Result.getValue(1));
13534 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl,
13535 Regs64bit ? X86::RDX : X86::EDX,
13536 HalfT, cpOutL.getValue(2));
13537 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
13538 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, T, OpsF, 2));
13539 Results.push_back(cpOutH.getValue(1));
13542 case ISD::ATOMIC_LOAD_ADD:
13543 case ISD::ATOMIC_LOAD_AND:
13544 case ISD::ATOMIC_LOAD_NAND:
13545 case ISD::ATOMIC_LOAD_OR:
13546 case ISD::ATOMIC_LOAD_SUB:
13547 case ISD::ATOMIC_LOAD_XOR:
13548 case ISD::ATOMIC_LOAD_MAX:
13549 case ISD::ATOMIC_LOAD_MIN:
13550 case ISD::ATOMIC_LOAD_UMAX:
13551 case ISD::ATOMIC_LOAD_UMIN:
13552 case ISD::ATOMIC_SWAP: {
13554 switch (N->getOpcode()) {
13555 default: llvm_unreachable("Unexpected opcode");
13556 case ISD::ATOMIC_LOAD_ADD:
13557 Opc = X86ISD::ATOMADD64_DAG;
13559 case ISD::ATOMIC_LOAD_AND:
13560 Opc = X86ISD::ATOMAND64_DAG;
13562 case ISD::ATOMIC_LOAD_NAND:
13563 Opc = X86ISD::ATOMNAND64_DAG;
13565 case ISD::ATOMIC_LOAD_OR:
13566 Opc = X86ISD::ATOMOR64_DAG;
13568 case ISD::ATOMIC_LOAD_SUB:
13569 Opc = X86ISD::ATOMSUB64_DAG;
13571 case ISD::ATOMIC_LOAD_XOR:
13572 Opc = X86ISD::ATOMXOR64_DAG;
13574 case ISD::ATOMIC_LOAD_MAX:
13575 Opc = X86ISD::ATOMMAX64_DAG;
13577 case ISD::ATOMIC_LOAD_MIN:
13578 Opc = X86ISD::ATOMMIN64_DAG;
13580 case ISD::ATOMIC_LOAD_UMAX:
13581 Opc = X86ISD::ATOMUMAX64_DAG;
13583 case ISD::ATOMIC_LOAD_UMIN:
13584 Opc = X86ISD::ATOMUMIN64_DAG;
13586 case ISD::ATOMIC_SWAP:
13587 Opc = X86ISD::ATOMSWAP64_DAG;
13590 ReplaceATOMIC_BINARY_64(N, Results, DAG, Opc);
13593 case ISD::ATOMIC_LOAD:
13594 ReplaceATOMIC_LOAD(N, Results, DAG);
13598 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
13600 default: return NULL;
13601 case X86ISD::BSF: return "X86ISD::BSF";
13602 case X86ISD::BSR: return "X86ISD::BSR";
13603 case X86ISD::SHLD: return "X86ISD::SHLD";
13604 case X86ISD::SHRD: return "X86ISD::SHRD";
13605 case X86ISD::FAND: return "X86ISD::FAND";
13606 case X86ISD::FANDN: return "X86ISD::FANDN";
13607 case X86ISD::FOR: return "X86ISD::FOR";
13608 case X86ISD::FXOR: return "X86ISD::FXOR";
13609 case X86ISD::FSRL: return "X86ISD::FSRL";
13610 case X86ISD::FILD: return "X86ISD::FILD";
13611 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
13612 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
13613 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
13614 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
13615 case X86ISD::FLD: return "X86ISD::FLD";
13616 case X86ISD::FST: return "X86ISD::FST";
13617 case X86ISD::CALL: return "X86ISD::CALL";
13618 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
13619 case X86ISD::BT: return "X86ISD::BT";
13620 case X86ISD::CMP: return "X86ISD::CMP";
13621 case X86ISD::COMI: return "X86ISD::COMI";
13622 case X86ISD::UCOMI: return "X86ISD::UCOMI";
13623 case X86ISD::CMPM: return "X86ISD::CMPM";
13624 case X86ISD::CMPMU: return "X86ISD::CMPMU";
13625 case X86ISD::SETCC: return "X86ISD::SETCC";
13626 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY";
13627 case X86ISD::FSETCCsd: return "X86ISD::FSETCCsd";
13628 case X86ISD::FSETCCss: return "X86ISD::FSETCCss";
13629 case X86ISD::CMOV: return "X86ISD::CMOV";
13630 case X86ISD::BRCOND: return "X86ISD::BRCOND";
13631 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
13632 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
13633 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
13634 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
13635 case X86ISD::Wrapper: return "X86ISD::Wrapper";
13636 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
13637 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
13638 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
13639 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
13640 case X86ISD::PINSRB: return "X86ISD::PINSRB";
13641 case X86ISD::PINSRW: return "X86ISD::PINSRW";
13642 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
13643 case X86ISD::ANDNP: return "X86ISD::ANDNP";
13644 case X86ISD::PSIGN: return "X86ISD::PSIGN";
13645 case X86ISD::BLENDV: return "X86ISD::BLENDV";
13646 case X86ISD::BLENDI: return "X86ISD::BLENDI";
13647 case X86ISD::SUBUS: return "X86ISD::SUBUS";
13648 case X86ISD::HADD: return "X86ISD::HADD";
13649 case X86ISD::HSUB: return "X86ISD::HSUB";
13650 case X86ISD::FHADD: return "X86ISD::FHADD";
13651 case X86ISD::FHSUB: return "X86ISD::FHSUB";
13652 case X86ISD::UMAX: return "X86ISD::UMAX";
13653 case X86ISD::UMIN: return "X86ISD::UMIN";
13654 case X86ISD::SMAX: return "X86ISD::SMAX";
13655 case X86ISD::SMIN: return "X86ISD::SMIN";
13656 case X86ISD::FMAX: return "X86ISD::FMAX";
13657 case X86ISD::FMIN: return "X86ISD::FMIN";
13658 case X86ISD::FMAXC: return "X86ISD::FMAXC";
13659 case X86ISD::FMINC: return "X86ISD::FMINC";
13660 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
13661 case X86ISD::FRCP: return "X86ISD::FRCP";
13662 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
13663 case X86ISD::TLSBASEADDR: return "X86ISD::TLSBASEADDR";
13664 case X86ISD::TLSCALL: return "X86ISD::TLSCALL";
13665 case X86ISD::EH_SJLJ_SETJMP: return "X86ISD::EH_SJLJ_SETJMP";
13666 case X86ISD::EH_SJLJ_LONGJMP: return "X86ISD::EH_SJLJ_LONGJMP";
13667 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
13668 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
13669 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
13670 case X86ISD::FNSTSW16r: return "X86ISD::FNSTSW16r";
13671 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
13672 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
13673 case X86ISD::ATOMADD64_DAG: return "X86ISD::ATOMADD64_DAG";
13674 case X86ISD::ATOMSUB64_DAG: return "X86ISD::ATOMSUB64_DAG";
13675 case X86ISD::ATOMOR64_DAG: return "X86ISD::ATOMOR64_DAG";
13676 case X86ISD::ATOMXOR64_DAG: return "X86ISD::ATOMXOR64_DAG";
13677 case X86ISD::ATOMAND64_DAG: return "X86ISD::ATOMAND64_DAG";
13678 case X86ISD::ATOMNAND64_DAG: return "X86ISD::ATOMNAND64_DAG";
13679 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
13680 case X86ISD::VSEXT_MOVL: return "X86ISD::VSEXT_MOVL";
13681 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
13682 case X86ISD::VZEXT: return "X86ISD::VZEXT";
13683 case X86ISD::VSEXT: return "X86ISD::VSEXT";
13684 case X86ISD::VTRUNC: return "X86ISD::VTRUNC";
13685 case X86ISD::VTRUNCM: return "X86ISD::VTRUNCM";
13686 case X86ISD::VINSERT: return "X86ISD::VINSERT";
13687 case X86ISD::VFPEXT: return "X86ISD::VFPEXT";
13688 case X86ISD::VFPROUND: return "X86ISD::VFPROUND";
13689 case X86ISD::VSHLDQ: return "X86ISD::VSHLDQ";
13690 case X86ISD::VSRLDQ: return "X86ISD::VSRLDQ";
13691 case X86ISD::VSHL: return "X86ISD::VSHL";
13692 case X86ISD::VSRL: return "X86ISD::VSRL";
13693 case X86ISD::VSRA: return "X86ISD::VSRA";
13694 case X86ISD::VSHLI: return "X86ISD::VSHLI";
13695 case X86ISD::VSRLI: return "X86ISD::VSRLI";
13696 case X86ISD::VSRAI: return "X86ISD::VSRAI";
13697 case X86ISD::CMPP: return "X86ISD::CMPP";
13698 case X86ISD::PCMPEQ: return "X86ISD::PCMPEQ";
13699 case X86ISD::PCMPGT: return "X86ISD::PCMPGT";
13700 case X86ISD::PCMPEQM: return "X86ISD::PCMPEQM";
13701 case X86ISD::PCMPGTM: return "X86ISD::PCMPGTM";
13702 case X86ISD::ADD: return "X86ISD::ADD";
13703 case X86ISD::SUB: return "X86ISD::SUB";
13704 case X86ISD::ADC: return "X86ISD::ADC";
13705 case X86ISD::SBB: return "X86ISD::SBB";
13706 case X86ISD::SMUL: return "X86ISD::SMUL";
13707 case X86ISD::UMUL: return "X86ISD::UMUL";
13708 case X86ISD::INC: return "X86ISD::INC";
13709 case X86ISD::DEC: return "X86ISD::DEC";
13710 case X86ISD::OR: return "X86ISD::OR";
13711 case X86ISD::XOR: return "X86ISD::XOR";
13712 case X86ISD::AND: return "X86ISD::AND";
13713 case X86ISD::BLSI: return "X86ISD::BLSI";
13714 case X86ISD::BLSMSK: return "X86ISD::BLSMSK";
13715 case X86ISD::BLSR: return "X86ISD::BLSR";
13716 case X86ISD::BZHI: return "X86ISD::BZHI";
13717 case X86ISD::BEXTR: return "X86ISD::BEXTR";
13718 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
13719 case X86ISD::PTEST: return "X86ISD::PTEST";
13720 case X86ISD::TESTP: return "X86ISD::TESTP";
13721 case X86ISD::TESTM: return "X86ISD::TESTM";
13722 case X86ISD::KORTEST: return "X86ISD::KORTEST";
13723 case X86ISD::KTEST: return "X86ISD::KTEST";
13724 case X86ISD::PALIGNR: return "X86ISD::PALIGNR";
13725 case X86ISD::PSHUFD: return "X86ISD::PSHUFD";
13726 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW";
13727 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW";
13728 case X86ISD::SHUFP: return "X86ISD::SHUFP";
13729 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS";
13730 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD";
13731 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS";
13732 case X86ISD::MOVLPS: return "X86ISD::MOVLPS";
13733 case X86ISD::MOVLPD: return "X86ISD::MOVLPD";
13734 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP";
13735 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP";
13736 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP";
13737 case X86ISD::MOVSD: return "X86ISD::MOVSD";
13738 case X86ISD::MOVSS: return "X86ISD::MOVSS";
13739 case X86ISD::UNPCKL: return "X86ISD::UNPCKL";
13740 case X86ISD::UNPCKH: return "X86ISD::UNPCKH";
13741 case X86ISD::VBROADCAST: return "X86ISD::VBROADCAST";
13742 case X86ISD::VBROADCASTM: return "X86ISD::VBROADCASTM";
13743 case X86ISD::VPERMILP: return "X86ISD::VPERMILP";
13744 case X86ISD::VPERM2X128: return "X86ISD::VPERM2X128";
13745 case X86ISD::VPERMV: return "X86ISD::VPERMV";
13746 case X86ISD::VPERMV3: return "X86ISD::VPERMV3";
13747 case X86ISD::VPERMI: return "X86ISD::VPERMI";
13748 case X86ISD::PMULUDQ: return "X86ISD::PMULUDQ";
13749 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
13750 case X86ISD::VAARG_64: return "X86ISD::VAARG_64";
13751 case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA";
13752 case X86ISD::MEMBARRIER: return "X86ISD::MEMBARRIER";
13753 case X86ISD::SEG_ALLOCA: return "X86ISD::SEG_ALLOCA";
13754 case X86ISD::WIN_FTOL: return "X86ISD::WIN_FTOL";
13755 case X86ISD::SAHF: return "X86ISD::SAHF";
13756 case X86ISD::RDRAND: return "X86ISD::RDRAND";
13757 case X86ISD::RDSEED: return "X86ISD::RDSEED";
13758 case X86ISD::FMADD: return "X86ISD::FMADD";
13759 case X86ISD::FMSUB: return "X86ISD::FMSUB";
13760 case X86ISD::FNMADD: return "X86ISD::FNMADD";
13761 case X86ISD::FNMSUB: return "X86ISD::FNMSUB";
13762 case X86ISD::FMADDSUB: return "X86ISD::FMADDSUB";
13763 case X86ISD::FMSUBADD: return "X86ISD::FMSUBADD";
13764 case X86ISD::PCMPESTRI: return "X86ISD::PCMPESTRI";
13765 case X86ISD::PCMPISTRI: return "X86ISD::PCMPISTRI";
13766 case X86ISD::XTEST: return "X86ISD::XTEST";
13770 // isLegalAddressingMode - Return true if the addressing mode represented
13771 // by AM is legal for this target, for a load/store of the specified type.
13772 bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
13774 // X86 supports extremely general addressing modes.
13775 CodeModel::Model M = getTargetMachine().getCodeModel();
13776 Reloc::Model R = getTargetMachine().getRelocationModel();
13778 // X86 allows a sign-extended 32-bit immediate field as a displacement.
13779 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != NULL))
13784 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
13786 // If a reference to this global requires an extra load, we can't fold it.
13787 if (isGlobalStubReference(GVFlags))
13790 // If BaseGV requires a register for the PIC base, we cannot also have a
13791 // BaseReg specified.
13792 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
13795 // If lower 4G is not available, then we must use rip-relative addressing.
13796 if ((M != CodeModel::Small || R != Reloc::Static) &&
13797 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
13801 switch (AM.Scale) {
13807 // These scales always work.
13812 // These scales are formed with basereg+scalereg. Only accept if there is
13817 default: // Other stuff never works.
13824 bool X86TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
13825 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
13827 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
13828 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
13829 return NumBits1 > NumBits2;
13832 bool X86TargetLowering::allowTruncateForTailCall(Type *Ty1, Type *Ty2) const {
13833 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
13836 if (!isTypeLegal(EVT::getEVT(Ty1)))
13839 assert(Ty1->getPrimitiveSizeInBits() <= 64 && "i128 is probably not a noop");
13841 // Assuming the caller doesn't have a zeroext or signext return parameter,
13842 // truncation all the way down to i1 is valid.
13846 bool X86TargetLowering::isLegalICmpImmediate(int64_t Imm) const {
13847 return isInt<32>(Imm);
13850 bool X86TargetLowering::isLegalAddImmediate(int64_t Imm) const {
13851 // Can also use sub to handle negated immediates.
13852 return isInt<32>(Imm);
13855 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
13856 if (!VT1.isInteger() || !VT2.isInteger())
13858 unsigned NumBits1 = VT1.getSizeInBits();
13859 unsigned NumBits2 = VT2.getSizeInBits();
13860 return NumBits1 > NumBits2;
13863 bool X86TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
13864 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
13865 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit();
13868 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
13869 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
13870 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
13873 bool X86TargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
13874 EVT VT1 = Val.getValueType();
13875 if (isZExtFree(VT1, VT2))
13878 if (Val.getOpcode() != ISD::LOAD)
13881 if (!VT1.isSimple() || !VT1.isInteger() ||
13882 !VT2.isSimple() || !VT2.isInteger())
13885 switch (VT1.getSimpleVT().SimpleTy) {
13890 // X86 has 8, 16, and 32-bit zero-extending loads.
13898 X86TargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
13899 if (!(Subtarget->hasFMA() || Subtarget->hasFMA4()))
13902 VT = VT.getScalarType();
13904 if (!VT.isSimple())
13907 switch (VT.getSimpleVT().SimpleTy) {
13918 bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
13919 // i16 instructions are longer (0x66 prefix) and potentially slower.
13920 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
13923 /// isShuffleMaskLegal - Targets can use this to indicate that they only
13924 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
13925 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
13926 /// are assumed to be legal.
13928 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
13930 if (!VT.isSimple())
13933 MVT SVT = VT.getSimpleVT();
13935 // Very little shuffling can be done for 64-bit vectors right now.
13936 if (VT.getSizeInBits() == 64)
13939 // FIXME: pshufb, blends, shifts.
13940 return (SVT.getVectorNumElements() == 2 ||
13941 ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
13942 isMOVLMask(M, SVT) ||
13943 isSHUFPMask(M, SVT) ||
13944 isPSHUFDMask(M, SVT) ||
13945 isPSHUFHWMask(M, SVT, Subtarget->hasInt256()) ||
13946 isPSHUFLWMask(M, SVT, Subtarget->hasInt256()) ||
13947 isPALIGNRMask(M, SVT, Subtarget) ||
13948 isUNPCKLMask(M, SVT, Subtarget->hasInt256()) ||
13949 isUNPCKHMask(M, SVT, Subtarget->hasInt256()) ||
13950 isUNPCKL_v_undef_Mask(M, SVT, Subtarget->hasInt256()) ||
13951 isUNPCKH_v_undef_Mask(M, SVT, Subtarget->hasInt256()));
13955 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
13957 if (!VT.isSimple())
13960 MVT SVT = VT.getSimpleVT();
13961 unsigned NumElts = SVT.getVectorNumElements();
13962 // FIXME: This collection of masks seems suspect.
13965 if (NumElts == 4 && SVT.is128BitVector()) {
13966 return (isMOVLMask(Mask, SVT) ||
13967 isCommutedMOVLMask(Mask, SVT, true) ||
13968 isSHUFPMask(Mask, SVT) ||
13969 isSHUFPMask(Mask, SVT, /* Commuted */ true));
13974 //===----------------------------------------------------------------------===//
13975 // X86 Scheduler Hooks
13976 //===----------------------------------------------------------------------===//
13978 /// Utility function to emit xbegin specifying the start of an RTM region.
13979 static MachineBasicBlock *EmitXBegin(MachineInstr *MI, MachineBasicBlock *MBB,
13980 const TargetInstrInfo *TII) {
13981 DebugLoc DL = MI->getDebugLoc();
13983 const BasicBlock *BB = MBB->getBasicBlock();
13984 MachineFunction::iterator I = MBB;
13987 // For the v = xbegin(), we generate
13998 MachineBasicBlock *thisMBB = MBB;
13999 MachineFunction *MF = MBB->getParent();
14000 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
14001 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
14002 MF->insert(I, mainMBB);
14003 MF->insert(I, sinkMBB);
14005 // Transfer the remainder of BB and its successor edges to sinkMBB.
14006 sinkMBB->splice(sinkMBB->begin(), MBB,
14007 llvm::next(MachineBasicBlock::iterator(MI)), MBB->end());
14008 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
14012 // # fallthrough to mainMBB
14013 // # abortion to sinkMBB
14014 BuildMI(thisMBB, DL, TII->get(X86::XBEGIN_4)).addMBB(sinkMBB);
14015 thisMBB->addSuccessor(mainMBB);
14016 thisMBB->addSuccessor(sinkMBB);
14020 BuildMI(mainMBB, DL, TII->get(X86::MOV32ri), X86::EAX).addImm(-1);
14021 mainMBB->addSuccessor(sinkMBB);
14024 // EAX is live into the sinkMBB
14025 sinkMBB->addLiveIn(X86::EAX);
14026 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
14027 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
14030 MI->eraseFromParent();
14034 // Get CMPXCHG opcode for the specified data type.
14035 static unsigned getCmpXChgOpcode(EVT VT) {
14036 switch (VT.getSimpleVT().SimpleTy) {
14037 case MVT::i8: return X86::LCMPXCHG8;
14038 case MVT::i16: return X86::LCMPXCHG16;
14039 case MVT::i32: return X86::LCMPXCHG32;
14040 case MVT::i64: return X86::LCMPXCHG64;
14044 llvm_unreachable("Invalid operand size!");
14047 // Get LOAD opcode for the specified data type.
14048 static unsigned getLoadOpcode(EVT VT) {
14049 switch (VT.getSimpleVT().SimpleTy) {
14050 case MVT::i8: return X86::MOV8rm;
14051 case MVT::i16: return X86::MOV16rm;
14052 case MVT::i32: return X86::MOV32rm;
14053 case MVT::i64: return X86::MOV64rm;
14057 llvm_unreachable("Invalid operand size!");
14060 // Get opcode of the non-atomic one from the specified atomic instruction.
14061 static unsigned getNonAtomicOpcode(unsigned Opc) {
14063 case X86::ATOMAND8: return X86::AND8rr;
14064 case X86::ATOMAND16: return X86::AND16rr;
14065 case X86::ATOMAND32: return X86::AND32rr;
14066 case X86::ATOMAND64: return X86::AND64rr;
14067 case X86::ATOMOR8: return X86::OR8rr;
14068 case X86::ATOMOR16: return X86::OR16rr;
14069 case X86::ATOMOR32: return X86::OR32rr;
14070 case X86::ATOMOR64: return X86::OR64rr;
14071 case X86::ATOMXOR8: return X86::XOR8rr;
14072 case X86::ATOMXOR16: return X86::XOR16rr;
14073 case X86::ATOMXOR32: return X86::XOR32rr;
14074 case X86::ATOMXOR64: return X86::XOR64rr;
14076 llvm_unreachable("Unhandled atomic-load-op opcode!");
14079 // Get opcode of the non-atomic one from the specified atomic instruction with
14081 static unsigned getNonAtomicOpcodeWithExtraOpc(unsigned Opc,
14082 unsigned &ExtraOpc) {
14084 case X86::ATOMNAND8: ExtraOpc = X86::NOT8r; return X86::AND8rr;
14085 case X86::ATOMNAND16: ExtraOpc = X86::NOT16r; return X86::AND16rr;
14086 case X86::ATOMNAND32: ExtraOpc = X86::NOT32r; return X86::AND32rr;
14087 case X86::ATOMNAND64: ExtraOpc = X86::NOT64r; return X86::AND64rr;
14088 case X86::ATOMMAX8: ExtraOpc = X86::CMP8rr; return X86::CMOVL32rr;
14089 case X86::ATOMMAX16: ExtraOpc = X86::CMP16rr; return X86::CMOVL16rr;
14090 case X86::ATOMMAX32: ExtraOpc = X86::CMP32rr; return X86::CMOVL32rr;
14091 case X86::ATOMMAX64: ExtraOpc = X86::CMP64rr; return X86::CMOVL64rr;
14092 case X86::ATOMMIN8: ExtraOpc = X86::CMP8rr; return X86::CMOVG32rr;
14093 case X86::ATOMMIN16: ExtraOpc = X86::CMP16rr; return X86::CMOVG16rr;
14094 case X86::ATOMMIN32: ExtraOpc = X86::CMP32rr; return X86::CMOVG32rr;
14095 case X86::ATOMMIN64: ExtraOpc = X86::CMP64rr; return X86::CMOVG64rr;
14096 case X86::ATOMUMAX8: ExtraOpc = X86::CMP8rr; return X86::CMOVB32rr;
14097 case X86::ATOMUMAX16: ExtraOpc = X86::CMP16rr; return X86::CMOVB16rr;
14098 case X86::ATOMUMAX32: ExtraOpc = X86::CMP32rr; return X86::CMOVB32rr;
14099 case X86::ATOMUMAX64: ExtraOpc = X86::CMP64rr; return X86::CMOVB64rr;
14100 case X86::ATOMUMIN8: ExtraOpc = X86::CMP8rr; return X86::CMOVA32rr;
14101 case X86::ATOMUMIN16: ExtraOpc = X86::CMP16rr; return X86::CMOVA16rr;
14102 case X86::ATOMUMIN32: ExtraOpc = X86::CMP32rr; return X86::CMOVA32rr;
14103 case X86::ATOMUMIN64: ExtraOpc = X86::CMP64rr; return X86::CMOVA64rr;
14105 llvm_unreachable("Unhandled atomic-load-op opcode!");
14108 // Get opcode of the non-atomic one from the specified atomic instruction for
14109 // 64-bit data type on 32-bit target.
14110 static unsigned getNonAtomic6432Opcode(unsigned Opc, unsigned &HiOpc) {
14112 case X86::ATOMAND6432: HiOpc = X86::AND32rr; return X86::AND32rr;
14113 case X86::ATOMOR6432: HiOpc = X86::OR32rr; return X86::OR32rr;
14114 case X86::ATOMXOR6432: HiOpc = X86::XOR32rr; return X86::XOR32rr;
14115 case X86::ATOMADD6432: HiOpc = X86::ADC32rr; return X86::ADD32rr;
14116 case X86::ATOMSUB6432: HiOpc = X86::SBB32rr; return X86::SUB32rr;
14117 case X86::ATOMSWAP6432: HiOpc = X86::MOV32rr; return X86::MOV32rr;
14118 case X86::ATOMMAX6432: HiOpc = X86::SETLr; return X86::SETLr;
14119 case X86::ATOMMIN6432: HiOpc = X86::SETGr; return X86::SETGr;
14120 case X86::ATOMUMAX6432: HiOpc = X86::SETBr; return X86::SETBr;
14121 case X86::ATOMUMIN6432: HiOpc = X86::SETAr; return X86::SETAr;
14123 llvm_unreachable("Unhandled atomic-load-op opcode!");
14126 // Get opcode of the non-atomic one from the specified atomic instruction for
14127 // 64-bit data type on 32-bit target with extra opcode.
14128 static unsigned getNonAtomic6432OpcodeWithExtraOpc(unsigned Opc,
14130 unsigned &ExtraOpc) {
14132 case X86::ATOMNAND6432:
14133 ExtraOpc = X86::NOT32r;
14134 HiOpc = X86::AND32rr;
14135 return X86::AND32rr;
14137 llvm_unreachable("Unhandled atomic-load-op opcode!");
14140 // Get pseudo CMOV opcode from the specified data type.
14141 static unsigned getPseudoCMOVOpc(EVT VT) {
14142 switch (VT.getSimpleVT().SimpleTy) {
14143 case MVT::i8: return X86::CMOV_GR8;
14144 case MVT::i16: return X86::CMOV_GR16;
14145 case MVT::i32: return X86::CMOV_GR32;
14149 llvm_unreachable("Unknown CMOV opcode!");
14152 // EmitAtomicLoadArith - emit the code sequence for pseudo atomic instructions.
14153 // They will be translated into a spin-loop or compare-exchange loop from
14156 // dst = atomic-fetch-op MI.addr, MI.val
14162 // t1 = LOAD MI.addr
14164 // t4 = phi(t1, t3 / loop)
14165 // t2 = OP MI.val, t4
14167 // LCMPXCHG [MI.addr], t2, [EAX is implicitly used & defined]
14173 MachineBasicBlock *
14174 X86TargetLowering::EmitAtomicLoadArith(MachineInstr *MI,
14175 MachineBasicBlock *MBB) const {
14176 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
14177 DebugLoc DL = MI->getDebugLoc();
14179 MachineFunction *MF = MBB->getParent();
14180 MachineRegisterInfo &MRI = MF->getRegInfo();
14182 const BasicBlock *BB = MBB->getBasicBlock();
14183 MachineFunction::iterator I = MBB;
14186 assert(MI->getNumOperands() <= X86::AddrNumOperands + 4 &&
14187 "Unexpected number of operands");
14189 assert(MI->hasOneMemOperand() &&
14190 "Expected atomic-load-op to have one memoperand");
14192 // Memory Reference
14193 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
14194 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
14196 unsigned DstReg, SrcReg;
14197 unsigned MemOpndSlot;
14199 unsigned CurOp = 0;
14201 DstReg = MI->getOperand(CurOp++).getReg();
14202 MemOpndSlot = CurOp;
14203 CurOp += X86::AddrNumOperands;
14204 SrcReg = MI->getOperand(CurOp++).getReg();
14206 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
14207 MVT::SimpleValueType VT = *RC->vt_begin();
14208 unsigned t1 = MRI.createVirtualRegister(RC);
14209 unsigned t2 = MRI.createVirtualRegister(RC);
14210 unsigned t3 = MRI.createVirtualRegister(RC);
14211 unsigned t4 = MRI.createVirtualRegister(RC);
14212 unsigned PhyReg = getX86SubSuperRegister(X86::EAX, VT);
14214 unsigned LCMPXCHGOpc = getCmpXChgOpcode(VT);
14215 unsigned LOADOpc = getLoadOpcode(VT);
14217 // For the atomic load-arith operator, we generate
14220 // t1 = LOAD [MI.addr]
14222 // t4 = phi(t1 / thisMBB, t3 / mainMBB)
14223 // t1 = OP MI.val, EAX
14225 // LCMPXCHG [MI.addr], t1, [EAX is implicitly used & defined]
14231 MachineBasicBlock *thisMBB = MBB;
14232 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
14233 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
14234 MF->insert(I, mainMBB);
14235 MF->insert(I, sinkMBB);
14237 MachineInstrBuilder MIB;
14239 // Transfer the remainder of BB and its successor edges to sinkMBB.
14240 sinkMBB->splice(sinkMBB->begin(), MBB,
14241 llvm::next(MachineBasicBlock::iterator(MI)), MBB->end());
14242 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
14245 MIB = BuildMI(thisMBB, DL, TII->get(LOADOpc), t1);
14246 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
14247 MachineOperand NewMO = MI->getOperand(MemOpndSlot + i);
14249 NewMO.setIsKill(false);
14250 MIB.addOperand(NewMO);
14252 for (MachineInstr::mmo_iterator MMOI = MMOBegin; MMOI != MMOEnd; ++MMOI) {
14253 unsigned flags = (*MMOI)->getFlags();
14254 flags = (flags & ~MachineMemOperand::MOStore) | MachineMemOperand::MOLoad;
14255 MachineMemOperand *MMO =
14256 MF->getMachineMemOperand((*MMOI)->getPointerInfo(), flags,
14257 (*MMOI)->getSize(),
14258 (*MMOI)->getBaseAlignment(),
14259 (*MMOI)->getTBAAInfo(),
14260 (*MMOI)->getRanges());
14261 MIB.addMemOperand(MMO);
14264 thisMBB->addSuccessor(mainMBB);
14267 MachineBasicBlock *origMainMBB = mainMBB;
14270 MachineInstr *Phi = BuildMI(mainMBB, DL, TII->get(X86::PHI), t4)
14271 .addReg(t1).addMBB(thisMBB).addReg(t3).addMBB(mainMBB);
14273 unsigned Opc = MI->getOpcode();
14276 llvm_unreachable("Unhandled atomic-load-op opcode!");
14277 case X86::ATOMAND8:
14278 case X86::ATOMAND16:
14279 case X86::ATOMAND32:
14280 case X86::ATOMAND64:
14282 case X86::ATOMOR16:
14283 case X86::ATOMOR32:
14284 case X86::ATOMOR64:
14285 case X86::ATOMXOR8:
14286 case X86::ATOMXOR16:
14287 case X86::ATOMXOR32:
14288 case X86::ATOMXOR64: {
14289 unsigned ARITHOpc = getNonAtomicOpcode(Opc);
14290 BuildMI(mainMBB, DL, TII->get(ARITHOpc), t2).addReg(SrcReg)
14294 case X86::ATOMNAND8:
14295 case X86::ATOMNAND16:
14296 case X86::ATOMNAND32:
14297 case X86::ATOMNAND64: {
14298 unsigned Tmp = MRI.createVirtualRegister(RC);
14300 unsigned ANDOpc = getNonAtomicOpcodeWithExtraOpc(Opc, NOTOpc);
14301 BuildMI(mainMBB, DL, TII->get(ANDOpc), Tmp).addReg(SrcReg)
14303 BuildMI(mainMBB, DL, TII->get(NOTOpc), t2).addReg(Tmp);
14306 case X86::ATOMMAX8:
14307 case X86::ATOMMAX16:
14308 case X86::ATOMMAX32:
14309 case X86::ATOMMAX64:
14310 case X86::ATOMMIN8:
14311 case X86::ATOMMIN16:
14312 case X86::ATOMMIN32:
14313 case X86::ATOMMIN64:
14314 case X86::ATOMUMAX8:
14315 case X86::ATOMUMAX16:
14316 case X86::ATOMUMAX32:
14317 case X86::ATOMUMAX64:
14318 case X86::ATOMUMIN8:
14319 case X86::ATOMUMIN16:
14320 case X86::ATOMUMIN32:
14321 case X86::ATOMUMIN64: {
14323 unsigned CMOVOpc = getNonAtomicOpcodeWithExtraOpc(Opc, CMPOpc);
14325 BuildMI(mainMBB, DL, TII->get(CMPOpc))
14329 if (Subtarget->hasCMov()) {
14330 if (VT != MVT::i8) {
14332 BuildMI(mainMBB, DL, TII->get(CMOVOpc), t2)
14336 // Promote i8 to i32 to use CMOV32
14337 const TargetRegisterInfo* TRI = getTargetMachine().getRegisterInfo();
14338 const TargetRegisterClass *RC32 =
14339 TRI->getSubClassWithSubReg(getRegClassFor(MVT::i32), X86::sub_8bit);
14340 unsigned SrcReg32 = MRI.createVirtualRegister(RC32);
14341 unsigned AccReg32 = MRI.createVirtualRegister(RC32);
14342 unsigned Tmp = MRI.createVirtualRegister(RC32);
14344 unsigned Undef = MRI.createVirtualRegister(RC32);
14345 BuildMI(mainMBB, DL, TII->get(TargetOpcode::IMPLICIT_DEF), Undef);
14347 BuildMI(mainMBB, DL, TII->get(TargetOpcode::INSERT_SUBREG), SrcReg32)
14350 .addImm(X86::sub_8bit);
14351 BuildMI(mainMBB, DL, TII->get(TargetOpcode::INSERT_SUBREG), AccReg32)
14354 .addImm(X86::sub_8bit);
14356 BuildMI(mainMBB, DL, TII->get(CMOVOpc), Tmp)
14360 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), t2)
14361 .addReg(Tmp, 0, X86::sub_8bit);
14364 // Use pseudo select and lower them.
14365 assert((VT == MVT::i8 || VT == MVT::i16 || VT == MVT::i32) &&
14366 "Invalid atomic-load-op transformation!");
14367 unsigned SelOpc = getPseudoCMOVOpc(VT);
14368 X86::CondCode CC = X86::getCondFromCMovOpc(CMOVOpc);
14369 assert(CC != X86::COND_INVALID && "Invalid atomic-load-op transformation!");
14370 MIB = BuildMI(mainMBB, DL, TII->get(SelOpc), t2)
14371 .addReg(SrcReg).addReg(t4)
14373 mainMBB = EmitLoweredSelect(MIB, mainMBB);
14374 // Replace the original PHI node as mainMBB is changed after CMOV
14376 BuildMI(*origMainMBB, Phi, DL, TII->get(X86::PHI), t4)
14377 .addReg(t1).addMBB(thisMBB).addReg(t3).addMBB(mainMBB);
14378 Phi->eraseFromParent();
14384 // Copy PhyReg back from virtual register.
14385 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), PhyReg)
14388 MIB = BuildMI(mainMBB, DL, TII->get(LCMPXCHGOpc));
14389 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
14390 MachineOperand NewMO = MI->getOperand(MemOpndSlot + i);
14392 NewMO.setIsKill(false);
14393 MIB.addOperand(NewMO);
14396 MIB.setMemRefs(MMOBegin, MMOEnd);
14398 // Copy PhyReg back to virtual register.
14399 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), t3)
14402 BuildMI(mainMBB, DL, TII->get(X86::JNE_4)).addMBB(origMainMBB);
14404 mainMBB->addSuccessor(origMainMBB);
14405 mainMBB->addSuccessor(sinkMBB);
14408 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
14409 TII->get(TargetOpcode::COPY), DstReg)
14412 MI->eraseFromParent();
14416 // EmitAtomicLoadArith6432 - emit the code sequence for pseudo atomic
14417 // instructions. They will be translated into a spin-loop or compare-exchange
14421 // dst = atomic-fetch-op MI.addr, MI.val
14427 // t1L = LOAD [MI.addr + 0]
14428 // t1H = LOAD [MI.addr + 4]
14430 // t4L = phi(t1L, t3L / loop)
14431 // t4H = phi(t1H, t3H / loop)
14432 // t2L = OP MI.val.lo, t4L
14433 // t2H = OP MI.val.hi, t4H
14438 // LCMPXCHG8B [MI.addr], [ECX:EBX & EDX:EAX are implicitly used and EDX:EAX is implicitly defined]
14446 MachineBasicBlock *
14447 X86TargetLowering::EmitAtomicLoadArith6432(MachineInstr *MI,
14448 MachineBasicBlock *MBB) const {
14449 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
14450 DebugLoc DL = MI->getDebugLoc();
14452 MachineFunction *MF = MBB->getParent();
14453 MachineRegisterInfo &MRI = MF->getRegInfo();
14455 const BasicBlock *BB = MBB->getBasicBlock();
14456 MachineFunction::iterator I = MBB;
14459 assert(MI->getNumOperands() <= X86::AddrNumOperands + 7 &&
14460 "Unexpected number of operands");
14462 assert(MI->hasOneMemOperand() &&
14463 "Expected atomic-load-op32 to have one memoperand");
14465 // Memory Reference
14466 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
14467 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
14469 unsigned DstLoReg, DstHiReg;
14470 unsigned SrcLoReg, SrcHiReg;
14471 unsigned MemOpndSlot;
14473 unsigned CurOp = 0;
14475 DstLoReg = MI->getOperand(CurOp++).getReg();
14476 DstHiReg = MI->getOperand(CurOp++).getReg();
14477 MemOpndSlot = CurOp;
14478 CurOp += X86::AddrNumOperands;
14479 SrcLoReg = MI->getOperand(CurOp++).getReg();
14480 SrcHiReg = MI->getOperand(CurOp++).getReg();
14482 const TargetRegisterClass *RC = &X86::GR32RegClass;
14483 const TargetRegisterClass *RC8 = &X86::GR8RegClass;
14485 unsigned t1L = MRI.createVirtualRegister(RC);
14486 unsigned t1H = MRI.createVirtualRegister(RC);
14487 unsigned t2L = MRI.createVirtualRegister(RC);
14488 unsigned t2H = MRI.createVirtualRegister(RC);
14489 unsigned t3L = MRI.createVirtualRegister(RC);
14490 unsigned t3H = MRI.createVirtualRegister(RC);
14491 unsigned t4L = MRI.createVirtualRegister(RC);
14492 unsigned t4H = MRI.createVirtualRegister(RC);
14494 unsigned LCMPXCHGOpc = X86::LCMPXCHG8B;
14495 unsigned LOADOpc = X86::MOV32rm;
14497 // For the atomic load-arith operator, we generate
14500 // t1L = LOAD [MI.addr + 0]
14501 // t1H = LOAD [MI.addr + 4]
14503 // t4L = phi(t1L / thisMBB, t3L / mainMBB)
14504 // t4H = phi(t1H / thisMBB, t3H / mainMBB)
14505 // t2L = OP MI.val.lo, t4L
14506 // t2H = OP MI.val.hi, t4H
14509 // LCMPXCHG8B [MI.addr], [ECX:EBX & EDX:EAX are implicitly used and EDX:EAX is implicitly defined]
14517 MachineBasicBlock *thisMBB = MBB;
14518 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
14519 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
14520 MF->insert(I, mainMBB);
14521 MF->insert(I, sinkMBB);
14523 MachineInstrBuilder MIB;
14525 // Transfer the remainder of BB and its successor edges to sinkMBB.
14526 sinkMBB->splice(sinkMBB->begin(), MBB,
14527 llvm::next(MachineBasicBlock::iterator(MI)), MBB->end());
14528 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
14532 MIB = BuildMI(thisMBB, DL, TII->get(LOADOpc), t1L);
14533 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
14534 MachineOperand NewMO = MI->getOperand(MemOpndSlot + i);
14536 NewMO.setIsKill(false);
14537 MIB.addOperand(NewMO);
14539 for (MachineInstr::mmo_iterator MMOI = MMOBegin; MMOI != MMOEnd; ++MMOI) {
14540 unsigned flags = (*MMOI)->getFlags();
14541 flags = (flags & ~MachineMemOperand::MOStore) | MachineMemOperand::MOLoad;
14542 MachineMemOperand *MMO =
14543 MF->getMachineMemOperand((*MMOI)->getPointerInfo(), flags,
14544 (*MMOI)->getSize(),
14545 (*MMOI)->getBaseAlignment(),
14546 (*MMOI)->getTBAAInfo(),
14547 (*MMOI)->getRanges());
14548 MIB.addMemOperand(MMO);
14550 MachineInstr *LowMI = MIB;
14553 MIB = BuildMI(thisMBB, DL, TII->get(LOADOpc), t1H);
14554 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
14555 if (i == X86::AddrDisp) {
14556 MIB.addDisp(MI->getOperand(MemOpndSlot + i), 4); // 4 == sizeof(i32)
14558 MachineOperand NewMO = MI->getOperand(MemOpndSlot + i);
14560 NewMO.setIsKill(false);
14561 MIB.addOperand(NewMO);
14564 MIB.setMemRefs(LowMI->memoperands_begin(), LowMI->memoperands_end());
14566 thisMBB->addSuccessor(mainMBB);
14569 MachineBasicBlock *origMainMBB = mainMBB;
14572 MachineInstr *PhiL = BuildMI(mainMBB, DL, TII->get(X86::PHI), t4L)
14573 .addReg(t1L).addMBB(thisMBB).addReg(t3L).addMBB(mainMBB);
14574 MachineInstr *PhiH = BuildMI(mainMBB, DL, TII->get(X86::PHI), t4H)
14575 .addReg(t1H).addMBB(thisMBB).addReg(t3H).addMBB(mainMBB);
14577 unsigned Opc = MI->getOpcode();
14580 llvm_unreachable("Unhandled atomic-load-op6432 opcode!");
14581 case X86::ATOMAND6432:
14582 case X86::ATOMOR6432:
14583 case X86::ATOMXOR6432:
14584 case X86::ATOMADD6432:
14585 case X86::ATOMSUB6432: {
14587 unsigned LoOpc = getNonAtomic6432Opcode(Opc, HiOpc);
14588 BuildMI(mainMBB, DL, TII->get(LoOpc), t2L).addReg(t4L)
14590 BuildMI(mainMBB, DL, TII->get(HiOpc), t2H).addReg(t4H)
14594 case X86::ATOMNAND6432: {
14595 unsigned HiOpc, NOTOpc;
14596 unsigned LoOpc = getNonAtomic6432OpcodeWithExtraOpc(Opc, HiOpc, NOTOpc);
14597 unsigned TmpL = MRI.createVirtualRegister(RC);
14598 unsigned TmpH = MRI.createVirtualRegister(RC);
14599 BuildMI(mainMBB, DL, TII->get(LoOpc), TmpL).addReg(SrcLoReg)
14601 BuildMI(mainMBB, DL, TII->get(HiOpc), TmpH).addReg(SrcHiReg)
14603 BuildMI(mainMBB, DL, TII->get(NOTOpc), t2L).addReg(TmpL);
14604 BuildMI(mainMBB, DL, TII->get(NOTOpc), t2H).addReg(TmpH);
14607 case X86::ATOMMAX6432:
14608 case X86::ATOMMIN6432:
14609 case X86::ATOMUMAX6432:
14610 case X86::ATOMUMIN6432: {
14612 unsigned LoOpc = getNonAtomic6432Opcode(Opc, HiOpc);
14613 unsigned cL = MRI.createVirtualRegister(RC8);
14614 unsigned cH = MRI.createVirtualRegister(RC8);
14615 unsigned cL32 = MRI.createVirtualRegister(RC);
14616 unsigned cH32 = MRI.createVirtualRegister(RC);
14617 unsigned cc = MRI.createVirtualRegister(RC);
14618 // cl := cmp src_lo, lo
14619 BuildMI(mainMBB, DL, TII->get(X86::CMP32rr))
14620 .addReg(SrcLoReg).addReg(t4L);
14621 BuildMI(mainMBB, DL, TII->get(LoOpc), cL);
14622 BuildMI(mainMBB, DL, TII->get(X86::MOVZX32rr8), cL32).addReg(cL);
14623 // ch := cmp src_hi, hi
14624 BuildMI(mainMBB, DL, TII->get(X86::CMP32rr))
14625 .addReg(SrcHiReg).addReg(t4H);
14626 BuildMI(mainMBB, DL, TII->get(HiOpc), cH);
14627 BuildMI(mainMBB, DL, TII->get(X86::MOVZX32rr8), cH32).addReg(cH);
14628 // cc := if (src_hi == hi) ? cl : ch;
14629 if (Subtarget->hasCMov()) {
14630 BuildMI(mainMBB, DL, TII->get(X86::CMOVE32rr), cc)
14631 .addReg(cH32).addReg(cL32);
14633 MIB = BuildMI(mainMBB, DL, TII->get(X86::CMOV_GR32), cc)
14634 .addReg(cH32).addReg(cL32)
14635 .addImm(X86::COND_E);
14636 mainMBB = EmitLoweredSelect(MIB, mainMBB);
14638 BuildMI(mainMBB, DL, TII->get(X86::TEST32rr)).addReg(cc).addReg(cc);
14639 if (Subtarget->hasCMov()) {
14640 BuildMI(mainMBB, DL, TII->get(X86::CMOVNE32rr), t2L)
14641 .addReg(SrcLoReg).addReg(t4L);
14642 BuildMI(mainMBB, DL, TII->get(X86::CMOVNE32rr), t2H)
14643 .addReg(SrcHiReg).addReg(t4H);
14645 MIB = BuildMI(mainMBB, DL, TII->get(X86::CMOV_GR32), t2L)
14646 .addReg(SrcLoReg).addReg(t4L)
14647 .addImm(X86::COND_NE);
14648 mainMBB = EmitLoweredSelect(MIB, mainMBB);
14649 // As the lowered CMOV won't clobber EFLAGS, we could reuse it for the
14650 // 2nd CMOV lowering.
14651 mainMBB->addLiveIn(X86::EFLAGS);
14652 MIB = BuildMI(mainMBB, DL, TII->get(X86::CMOV_GR32), t2H)
14653 .addReg(SrcHiReg).addReg(t4H)
14654 .addImm(X86::COND_NE);
14655 mainMBB = EmitLoweredSelect(MIB, mainMBB);
14656 // Replace the original PHI node as mainMBB is changed after CMOV
14658 BuildMI(*origMainMBB, PhiL, DL, TII->get(X86::PHI), t4L)
14659 .addReg(t1L).addMBB(thisMBB).addReg(t3L).addMBB(mainMBB);
14660 BuildMI(*origMainMBB, PhiH, DL, TII->get(X86::PHI), t4H)
14661 .addReg(t1H).addMBB(thisMBB).addReg(t3H).addMBB(mainMBB);
14662 PhiL->eraseFromParent();
14663 PhiH->eraseFromParent();
14667 case X86::ATOMSWAP6432: {
14669 unsigned LoOpc = getNonAtomic6432Opcode(Opc, HiOpc);
14670 BuildMI(mainMBB, DL, TII->get(LoOpc), t2L).addReg(SrcLoReg);
14671 BuildMI(mainMBB, DL, TII->get(HiOpc), t2H).addReg(SrcHiReg);
14676 // Copy EDX:EAX back from HiReg:LoReg
14677 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), X86::EAX).addReg(t4L);
14678 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), X86::EDX).addReg(t4H);
14679 // Copy ECX:EBX from t1H:t1L
14680 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), X86::EBX).addReg(t2L);
14681 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), X86::ECX).addReg(t2H);
14683 MIB = BuildMI(mainMBB, DL, TII->get(LCMPXCHGOpc));
14684 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
14685 MachineOperand NewMO = MI->getOperand(MemOpndSlot + i);
14687 NewMO.setIsKill(false);
14688 MIB.addOperand(NewMO);
14690 MIB.setMemRefs(MMOBegin, MMOEnd);
14692 // Copy EDX:EAX back to t3H:t3L
14693 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), t3L).addReg(X86::EAX);
14694 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), t3H).addReg(X86::EDX);
14696 BuildMI(mainMBB, DL, TII->get(X86::JNE_4)).addMBB(origMainMBB);
14698 mainMBB->addSuccessor(origMainMBB);
14699 mainMBB->addSuccessor(sinkMBB);
14702 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
14703 TII->get(TargetOpcode::COPY), DstLoReg)
14705 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
14706 TII->get(TargetOpcode::COPY), DstHiReg)
14709 MI->eraseFromParent();
14713 // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
14714 // or XMM0_V32I8 in AVX all of this code can be replaced with that
14715 // in the .td file.
14716 static MachineBasicBlock *EmitPCMPSTRM(MachineInstr *MI, MachineBasicBlock *BB,
14717 const TargetInstrInfo *TII) {
14719 switch (MI->getOpcode()) {
14720 default: llvm_unreachable("illegal opcode!");
14721 case X86::PCMPISTRM128REG: Opc = X86::PCMPISTRM128rr; break;
14722 case X86::VPCMPISTRM128REG: Opc = X86::VPCMPISTRM128rr; break;
14723 case X86::PCMPISTRM128MEM: Opc = X86::PCMPISTRM128rm; break;
14724 case X86::VPCMPISTRM128MEM: Opc = X86::VPCMPISTRM128rm; break;
14725 case X86::PCMPESTRM128REG: Opc = X86::PCMPESTRM128rr; break;
14726 case X86::VPCMPESTRM128REG: Opc = X86::VPCMPESTRM128rr; break;
14727 case X86::PCMPESTRM128MEM: Opc = X86::PCMPESTRM128rm; break;
14728 case X86::VPCMPESTRM128MEM: Opc = X86::VPCMPESTRM128rm; break;
14731 DebugLoc dl = MI->getDebugLoc();
14732 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
14734 unsigned NumArgs = MI->getNumOperands();
14735 for (unsigned i = 1; i < NumArgs; ++i) {
14736 MachineOperand &Op = MI->getOperand(i);
14737 if (!(Op.isReg() && Op.isImplicit()))
14738 MIB.addOperand(Op);
14740 if (MI->hasOneMemOperand())
14741 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
14743 BuildMI(*BB, MI, dl,
14744 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
14745 .addReg(X86::XMM0);
14747 MI->eraseFromParent();
14751 // FIXME: Custom handling because TableGen doesn't support multiple implicit
14752 // defs in an instruction pattern
14753 static MachineBasicBlock *EmitPCMPSTRI(MachineInstr *MI, MachineBasicBlock *BB,
14754 const TargetInstrInfo *TII) {
14756 switch (MI->getOpcode()) {
14757 default: llvm_unreachable("illegal opcode!");
14758 case X86::PCMPISTRIREG: Opc = X86::PCMPISTRIrr; break;
14759 case X86::VPCMPISTRIREG: Opc = X86::VPCMPISTRIrr; break;
14760 case X86::PCMPISTRIMEM: Opc = X86::PCMPISTRIrm; break;
14761 case X86::VPCMPISTRIMEM: Opc = X86::VPCMPISTRIrm; break;
14762 case X86::PCMPESTRIREG: Opc = X86::PCMPESTRIrr; break;
14763 case X86::VPCMPESTRIREG: Opc = X86::VPCMPESTRIrr; break;
14764 case X86::PCMPESTRIMEM: Opc = X86::PCMPESTRIrm; break;
14765 case X86::VPCMPESTRIMEM: Opc = X86::VPCMPESTRIrm; break;
14768 DebugLoc dl = MI->getDebugLoc();
14769 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
14771 unsigned NumArgs = MI->getNumOperands(); // remove the results
14772 for (unsigned i = 1; i < NumArgs; ++i) {
14773 MachineOperand &Op = MI->getOperand(i);
14774 if (!(Op.isReg() && Op.isImplicit()))
14775 MIB.addOperand(Op);
14777 if (MI->hasOneMemOperand())
14778 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
14780 BuildMI(*BB, MI, dl,
14781 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
14784 MI->eraseFromParent();
14788 static MachineBasicBlock * EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB,
14789 const TargetInstrInfo *TII,
14790 const X86Subtarget* Subtarget) {
14791 DebugLoc dl = MI->getDebugLoc();
14793 // Address into RAX/EAX, other two args into ECX, EDX.
14794 unsigned MemOpc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
14795 unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
14796 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg);
14797 for (int i = 0; i < X86::AddrNumOperands; ++i)
14798 MIB.addOperand(MI->getOperand(i));
14800 unsigned ValOps = X86::AddrNumOperands;
14801 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
14802 .addReg(MI->getOperand(ValOps).getReg());
14803 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EDX)
14804 .addReg(MI->getOperand(ValOps+1).getReg());
14806 // The instruction doesn't actually take any operands though.
14807 BuildMI(*BB, MI, dl, TII->get(X86::MONITORrrr));
14809 MI->eraseFromParent(); // The pseudo is gone now.
14813 MachineBasicBlock *
14814 X86TargetLowering::EmitVAARG64WithCustomInserter(
14816 MachineBasicBlock *MBB) const {
14817 // Emit va_arg instruction on X86-64.
14819 // Operands to this pseudo-instruction:
14820 // 0 ) Output : destination address (reg)
14821 // 1-5) Input : va_list address (addr, i64mem)
14822 // 6 ) ArgSize : Size (in bytes) of vararg type
14823 // 7 ) ArgMode : 0=overflow only, 1=use gp_offset, 2=use fp_offset
14824 // 8 ) Align : Alignment of type
14825 // 9 ) EFLAGS (implicit-def)
14827 assert(MI->getNumOperands() == 10 && "VAARG_64 should have 10 operands!");
14828 assert(X86::AddrNumOperands == 5 && "VAARG_64 assumes 5 address operands");
14830 unsigned DestReg = MI->getOperand(0).getReg();
14831 MachineOperand &Base = MI->getOperand(1);
14832 MachineOperand &Scale = MI->getOperand(2);
14833 MachineOperand &Index = MI->getOperand(3);
14834 MachineOperand &Disp = MI->getOperand(4);
14835 MachineOperand &Segment = MI->getOperand(5);
14836 unsigned ArgSize = MI->getOperand(6).getImm();
14837 unsigned ArgMode = MI->getOperand(7).getImm();
14838 unsigned Align = MI->getOperand(8).getImm();
14840 // Memory Reference
14841 assert(MI->hasOneMemOperand() && "Expected VAARG_64 to have one memoperand");
14842 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
14843 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
14845 // Machine Information
14846 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
14847 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
14848 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64);
14849 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32);
14850 DebugLoc DL = MI->getDebugLoc();
14852 // struct va_list {
14855 // i64 overflow_area (address)
14856 // i64 reg_save_area (address)
14858 // sizeof(va_list) = 24
14859 // alignment(va_list) = 8
14861 unsigned TotalNumIntRegs = 6;
14862 unsigned TotalNumXMMRegs = 8;
14863 bool UseGPOffset = (ArgMode == 1);
14864 bool UseFPOffset = (ArgMode == 2);
14865 unsigned MaxOffset = TotalNumIntRegs * 8 +
14866 (UseFPOffset ? TotalNumXMMRegs * 16 : 0);
14868 /* Align ArgSize to a multiple of 8 */
14869 unsigned ArgSizeA8 = (ArgSize + 7) & ~7;
14870 bool NeedsAlign = (Align > 8);
14872 MachineBasicBlock *thisMBB = MBB;
14873 MachineBasicBlock *overflowMBB;
14874 MachineBasicBlock *offsetMBB;
14875 MachineBasicBlock *endMBB;
14877 unsigned OffsetDestReg = 0; // Argument address computed by offsetMBB
14878 unsigned OverflowDestReg = 0; // Argument address computed by overflowMBB
14879 unsigned OffsetReg = 0;
14881 if (!UseGPOffset && !UseFPOffset) {
14882 // If we only pull from the overflow region, we don't create a branch.
14883 // We don't need to alter control flow.
14884 OffsetDestReg = 0; // unused
14885 OverflowDestReg = DestReg;
14888 overflowMBB = thisMBB;
14891 // First emit code to check if gp_offset (or fp_offset) is below the bound.
14892 // If so, pull the argument from reg_save_area. (branch to offsetMBB)
14893 // If not, pull from overflow_area. (branch to overflowMBB)
14898 // offsetMBB overflowMBB
14903 // Registers for the PHI in endMBB
14904 OffsetDestReg = MRI.createVirtualRegister(AddrRegClass);
14905 OverflowDestReg = MRI.createVirtualRegister(AddrRegClass);
14907 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
14908 MachineFunction *MF = MBB->getParent();
14909 overflowMBB = MF->CreateMachineBasicBlock(LLVM_BB);
14910 offsetMBB = MF->CreateMachineBasicBlock(LLVM_BB);
14911 endMBB = MF->CreateMachineBasicBlock(LLVM_BB);
14913 MachineFunction::iterator MBBIter = MBB;
14916 // Insert the new basic blocks
14917 MF->insert(MBBIter, offsetMBB);
14918 MF->insert(MBBIter, overflowMBB);
14919 MF->insert(MBBIter, endMBB);
14921 // Transfer the remainder of MBB and its successor edges to endMBB.
14922 endMBB->splice(endMBB->begin(), thisMBB,
14923 llvm::next(MachineBasicBlock::iterator(MI)),
14925 endMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
14927 // Make offsetMBB and overflowMBB successors of thisMBB
14928 thisMBB->addSuccessor(offsetMBB);
14929 thisMBB->addSuccessor(overflowMBB);
14931 // endMBB is a successor of both offsetMBB and overflowMBB
14932 offsetMBB->addSuccessor(endMBB);
14933 overflowMBB->addSuccessor(endMBB);
14935 // Load the offset value into a register
14936 OffsetReg = MRI.createVirtualRegister(OffsetRegClass);
14937 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg)
14941 .addDisp(Disp, UseFPOffset ? 4 : 0)
14942 .addOperand(Segment)
14943 .setMemRefs(MMOBegin, MMOEnd);
14945 // Check if there is enough room left to pull this argument.
14946 BuildMI(thisMBB, DL, TII->get(X86::CMP32ri))
14948 .addImm(MaxOffset + 8 - ArgSizeA8);
14950 // Branch to "overflowMBB" if offset >= max
14951 // Fall through to "offsetMBB" otherwise
14952 BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE)))
14953 .addMBB(overflowMBB);
14956 // In offsetMBB, emit code to use the reg_save_area.
14958 assert(OffsetReg != 0);
14960 // Read the reg_save_area address.
14961 unsigned RegSaveReg = MRI.createVirtualRegister(AddrRegClass);
14962 BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg)
14967 .addOperand(Segment)
14968 .setMemRefs(MMOBegin, MMOEnd);
14970 // Zero-extend the offset
14971 unsigned OffsetReg64 = MRI.createVirtualRegister(AddrRegClass);
14972 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64)
14975 .addImm(X86::sub_32bit);
14977 // Add the offset to the reg_save_area to get the final address.
14978 BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg)
14979 .addReg(OffsetReg64)
14980 .addReg(RegSaveReg);
14982 // Compute the offset for the next argument
14983 unsigned NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass);
14984 BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg)
14986 .addImm(UseFPOffset ? 16 : 8);
14988 // Store it back into the va_list.
14989 BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr))
14993 .addDisp(Disp, UseFPOffset ? 4 : 0)
14994 .addOperand(Segment)
14995 .addReg(NextOffsetReg)
14996 .setMemRefs(MMOBegin, MMOEnd);
14999 BuildMI(offsetMBB, DL, TII->get(X86::JMP_4))
15004 // Emit code to use overflow area
15007 // Load the overflow_area address into a register.
15008 unsigned OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass);
15009 BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg)
15014 .addOperand(Segment)
15015 .setMemRefs(MMOBegin, MMOEnd);
15017 // If we need to align it, do so. Otherwise, just copy the address
15018 // to OverflowDestReg.
15020 // Align the overflow address
15021 assert((Align & (Align-1)) == 0 && "Alignment must be a power of 2");
15022 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass);
15024 // aligned_addr = (addr + (align-1)) & ~(align-1)
15025 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg)
15026 .addReg(OverflowAddrReg)
15029 BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg)
15031 .addImm(~(uint64_t)(Align-1));
15033 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg)
15034 .addReg(OverflowAddrReg);
15037 // Compute the next overflow address after this argument.
15038 // (the overflow address should be kept 8-byte aligned)
15039 unsigned NextAddrReg = MRI.createVirtualRegister(AddrRegClass);
15040 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg)
15041 .addReg(OverflowDestReg)
15042 .addImm(ArgSizeA8);
15044 // Store the new overflow address.
15045 BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr))
15050 .addOperand(Segment)
15051 .addReg(NextAddrReg)
15052 .setMemRefs(MMOBegin, MMOEnd);
15054 // If we branched, emit the PHI to the front of endMBB.
15056 BuildMI(*endMBB, endMBB->begin(), DL,
15057 TII->get(X86::PHI), DestReg)
15058 .addReg(OffsetDestReg).addMBB(offsetMBB)
15059 .addReg(OverflowDestReg).addMBB(overflowMBB);
15062 // Erase the pseudo instruction
15063 MI->eraseFromParent();
15068 MachineBasicBlock *
15069 X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
15071 MachineBasicBlock *MBB) const {
15072 // Emit code to save XMM registers to the stack. The ABI says that the
15073 // number of registers to save is given in %al, so it's theoretically
15074 // possible to do an indirect jump trick to avoid saving all of them,
15075 // however this code takes a simpler approach and just executes all
15076 // of the stores if %al is non-zero. It's less code, and it's probably
15077 // easier on the hardware branch predictor, and stores aren't all that
15078 // expensive anyway.
15080 // Create the new basic blocks. One block contains all the XMM stores,
15081 // and one block is the final destination regardless of whether any
15082 // stores were performed.
15083 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
15084 MachineFunction *F = MBB->getParent();
15085 MachineFunction::iterator MBBIter = MBB;
15087 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB);
15088 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB);
15089 F->insert(MBBIter, XMMSaveMBB);
15090 F->insert(MBBIter, EndMBB);
15092 // Transfer the remainder of MBB and its successor edges to EndMBB.
15093 EndMBB->splice(EndMBB->begin(), MBB,
15094 llvm::next(MachineBasicBlock::iterator(MI)),
15096 EndMBB->transferSuccessorsAndUpdatePHIs(MBB);
15098 // The original block will now fall through to the XMM save block.
15099 MBB->addSuccessor(XMMSaveMBB);
15100 // The XMMSaveMBB will fall through to the end block.
15101 XMMSaveMBB->addSuccessor(EndMBB);
15103 // Now add the instructions.
15104 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
15105 DebugLoc DL = MI->getDebugLoc();
15107 unsigned CountReg = MI->getOperand(0).getReg();
15108 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm();
15109 int64_t VarArgsFPOffset = MI->getOperand(2).getImm();
15111 if (!Subtarget->isTargetWin64()) {
15112 // If %al is 0, branch around the XMM save block.
15113 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
15114 BuildMI(MBB, DL, TII->get(X86::JE_4)).addMBB(EndMBB);
15115 MBB->addSuccessor(EndMBB);
15118 unsigned MOVOpc = Subtarget->hasFp256() ? X86::VMOVAPSmr : X86::MOVAPSmr;
15119 // In the XMM save block, save all the XMM argument registers.
15120 for (int i = 3, e = MI->getNumOperands(); i != e; ++i) {
15121 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
15122 MachineMemOperand *MMO =
15123 F->getMachineMemOperand(
15124 MachinePointerInfo::getFixedStack(RegSaveFrameIndex, Offset),
15125 MachineMemOperand::MOStore,
15126 /*Size=*/16, /*Align=*/16);
15127 BuildMI(XMMSaveMBB, DL, TII->get(MOVOpc))
15128 .addFrameIndex(RegSaveFrameIndex)
15129 .addImm(/*Scale=*/1)
15130 .addReg(/*IndexReg=*/0)
15131 .addImm(/*Disp=*/Offset)
15132 .addReg(/*Segment=*/0)
15133 .addReg(MI->getOperand(i).getReg())
15134 .addMemOperand(MMO);
15137 MI->eraseFromParent(); // The pseudo instruction is gone now.
15142 // The EFLAGS operand of SelectItr might be missing a kill marker
15143 // because there were multiple uses of EFLAGS, and ISel didn't know
15144 // which to mark. Figure out whether SelectItr should have had a
15145 // kill marker, and set it if it should. Returns the correct kill
15147 static bool checkAndUpdateEFLAGSKill(MachineBasicBlock::iterator SelectItr,
15148 MachineBasicBlock* BB,
15149 const TargetRegisterInfo* TRI) {
15150 // Scan forward through BB for a use/def of EFLAGS.
15151 MachineBasicBlock::iterator miI(llvm::next(SelectItr));
15152 for (MachineBasicBlock::iterator miE = BB->end(); miI != miE; ++miI) {
15153 const MachineInstr& mi = *miI;
15154 if (mi.readsRegister(X86::EFLAGS))
15156 if (mi.definesRegister(X86::EFLAGS))
15157 break; // Should have kill-flag - update below.
15160 // If we hit the end of the block, check whether EFLAGS is live into a
15162 if (miI == BB->end()) {
15163 for (MachineBasicBlock::succ_iterator sItr = BB->succ_begin(),
15164 sEnd = BB->succ_end();
15165 sItr != sEnd; ++sItr) {
15166 MachineBasicBlock* succ = *sItr;
15167 if (succ->isLiveIn(X86::EFLAGS))
15172 // We found a def, or hit the end of the basic block and EFLAGS wasn't live
15173 // out. SelectMI should have a kill flag on EFLAGS.
15174 SelectItr->addRegisterKilled(X86::EFLAGS, TRI);
15178 MachineBasicBlock *
15179 X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
15180 MachineBasicBlock *BB) const {
15181 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
15182 DebugLoc DL = MI->getDebugLoc();
15184 // To "insert" a SELECT_CC instruction, we actually have to insert the
15185 // diamond control-flow pattern. The incoming instruction knows the
15186 // destination vreg to set, the condition code register to branch on, the
15187 // true/false values to select between, and a branch opcode to use.
15188 const BasicBlock *LLVM_BB = BB->getBasicBlock();
15189 MachineFunction::iterator It = BB;
15195 // cmpTY ccX, r1, r2
15197 // fallthrough --> copy0MBB
15198 MachineBasicBlock *thisMBB = BB;
15199 MachineFunction *F = BB->getParent();
15200 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
15201 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
15202 F->insert(It, copy0MBB);
15203 F->insert(It, sinkMBB);
15205 // If the EFLAGS register isn't dead in the terminator, then claim that it's
15206 // live into the sink and copy blocks.
15207 const TargetRegisterInfo* TRI = getTargetMachine().getRegisterInfo();
15208 if (!MI->killsRegister(X86::EFLAGS) &&
15209 !checkAndUpdateEFLAGSKill(MI, BB, TRI)) {
15210 copy0MBB->addLiveIn(X86::EFLAGS);
15211 sinkMBB->addLiveIn(X86::EFLAGS);
15214 // Transfer the remainder of BB and its successor edges to sinkMBB.
15215 sinkMBB->splice(sinkMBB->begin(), BB,
15216 llvm::next(MachineBasicBlock::iterator(MI)),
15218 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
15220 // Add the true and fallthrough blocks as its successors.
15221 BB->addSuccessor(copy0MBB);
15222 BB->addSuccessor(sinkMBB);
15224 // Create the conditional branch instruction.
15226 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
15227 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
15230 // %FalseValue = ...
15231 // # fallthrough to sinkMBB
15232 copy0MBB->addSuccessor(sinkMBB);
15235 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
15237 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
15238 TII->get(X86::PHI), MI->getOperand(0).getReg())
15239 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
15240 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
15242 MI->eraseFromParent(); // The pseudo instruction is gone now.
15246 MachineBasicBlock *
15247 X86TargetLowering::EmitLoweredSegAlloca(MachineInstr *MI, MachineBasicBlock *BB,
15248 bool Is64Bit) const {
15249 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
15250 DebugLoc DL = MI->getDebugLoc();
15251 MachineFunction *MF = BB->getParent();
15252 const BasicBlock *LLVM_BB = BB->getBasicBlock();
15254 assert(getTargetMachine().Options.EnableSegmentedStacks);
15256 unsigned TlsReg = Is64Bit ? X86::FS : X86::GS;
15257 unsigned TlsOffset = Is64Bit ? 0x70 : 0x30;
15260 // ... [Till the alloca]
15261 // If stacklet is not large enough, jump to mallocMBB
15264 // Allocate by subtracting from RSP
15265 // Jump to continueMBB
15268 // Allocate by call to runtime
15272 // [rest of original BB]
15275 MachineBasicBlock *mallocMBB = MF->CreateMachineBasicBlock(LLVM_BB);
15276 MachineBasicBlock *bumpMBB = MF->CreateMachineBasicBlock(LLVM_BB);
15277 MachineBasicBlock *continueMBB = MF->CreateMachineBasicBlock(LLVM_BB);
15279 MachineRegisterInfo &MRI = MF->getRegInfo();
15280 const TargetRegisterClass *AddrRegClass =
15281 getRegClassFor(Is64Bit ? MVT::i64:MVT::i32);
15283 unsigned mallocPtrVReg = MRI.createVirtualRegister(AddrRegClass),
15284 bumpSPPtrVReg = MRI.createVirtualRegister(AddrRegClass),
15285 tmpSPVReg = MRI.createVirtualRegister(AddrRegClass),
15286 SPLimitVReg = MRI.createVirtualRegister(AddrRegClass),
15287 sizeVReg = MI->getOperand(1).getReg(),
15288 physSPReg = Is64Bit ? X86::RSP : X86::ESP;
15290 MachineFunction::iterator MBBIter = BB;
15293 MF->insert(MBBIter, bumpMBB);
15294 MF->insert(MBBIter, mallocMBB);
15295 MF->insert(MBBIter, continueMBB);
15297 continueMBB->splice(continueMBB->begin(), BB, llvm::next
15298 (MachineBasicBlock::iterator(MI)), BB->end());
15299 continueMBB->transferSuccessorsAndUpdatePHIs(BB);
15301 // Add code to the main basic block to check if the stack limit has been hit,
15302 // and if so, jump to mallocMBB otherwise to bumpMBB.
15303 BuildMI(BB, DL, TII->get(TargetOpcode::COPY), tmpSPVReg).addReg(physSPReg);
15304 BuildMI(BB, DL, TII->get(Is64Bit ? X86::SUB64rr:X86::SUB32rr), SPLimitVReg)
15305 .addReg(tmpSPVReg).addReg(sizeVReg);
15306 BuildMI(BB, DL, TII->get(Is64Bit ? X86::CMP64mr:X86::CMP32mr))
15307 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg)
15308 .addReg(SPLimitVReg);
15309 BuildMI(BB, DL, TII->get(X86::JG_4)).addMBB(mallocMBB);
15311 // bumpMBB simply decreases the stack pointer, since we know the current
15312 // stacklet has enough space.
15313 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), physSPReg)
15314 .addReg(SPLimitVReg);
15315 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), bumpSPPtrVReg)
15316 .addReg(SPLimitVReg);
15317 BuildMI(bumpMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
15319 // Calls into a routine in libgcc to allocate more space from the heap.
15320 const uint32_t *RegMask =
15321 getTargetMachine().getRegisterInfo()->getCallPreservedMask(CallingConv::C);
15323 BuildMI(mallocMBB, DL, TII->get(X86::MOV64rr), X86::RDI)
15325 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
15326 .addExternalSymbol("__morestack_allocate_stack_space")
15327 .addRegMask(RegMask)
15328 .addReg(X86::RDI, RegState::Implicit)
15329 .addReg(X86::RAX, RegState::ImplicitDefine);
15331 BuildMI(mallocMBB, DL, TII->get(X86::SUB32ri), physSPReg).addReg(physSPReg)
15333 BuildMI(mallocMBB, DL, TII->get(X86::PUSH32r)).addReg(sizeVReg);
15334 BuildMI(mallocMBB, DL, TII->get(X86::CALLpcrel32))
15335 .addExternalSymbol("__morestack_allocate_stack_space")
15336 .addRegMask(RegMask)
15337 .addReg(X86::EAX, RegState::ImplicitDefine);
15341 BuildMI(mallocMBB, DL, TII->get(X86::ADD32ri), physSPReg).addReg(physSPReg)
15344 BuildMI(mallocMBB, DL, TII->get(TargetOpcode::COPY), mallocPtrVReg)
15345 .addReg(Is64Bit ? X86::RAX : X86::EAX);
15346 BuildMI(mallocMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
15348 // Set up the CFG correctly.
15349 BB->addSuccessor(bumpMBB);
15350 BB->addSuccessor(mallocMBB);
15351 mallocMBB->addSuccessor(continueMBB);
15352 bumpMBB->addSuccessor(continueMBB);
15354 // Take care of the PHI nodes.
15355 BuildMI(*continueMBB, continueMBB->begin(), DL, TII->get(X86::PHI),
15356 MI->getOperand(0).getReg())
15357 .addReg(mallocPtrVReg).addMBB(mallocMBB)
15358 .addReg(bumpSPPtrVReg).addMBB(bumpMBB);
15360 // Delete the original pseudo instruction.
15361 MI->eraseFromParent();
15364 return continueMBB;
15367 MachineBasicBlock *
15368 X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI,
15369 MachineBasicBlock *BB) const {
15370 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
15371 DebugLoc DL = MI->getDebugLoc();
15373 assert(!Subtarget->isTargetEnvMacho());
15375 // The lowering is pretty easy: we're just emitting the call to _alloca. The
15376 // non-trivial part is impdef of ESP.
15378 if (Subtarget->isTargetWin64()) {
15379 if (Subtarget->isTargetCygMing()) {
15380 // ___chkstk(Mingw64):
15381 // Clobbers R10, R11, RAX and EFLAGS.
15383 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
15384 .addExternalSymbol("___chkstk")
15385 .addReg(X86::RAX, RegState::Implicit)
15386 .addReg(X86::RSP, RegState::Implicit)
15387 .addReg(X86::RAX, RegState::Define | RegState::Implicit)
15388 .addReg(X86::RSP, RegState::Define | RegState::Implicit)
15389 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
15391 // __chkstk(MSVCRT): does not update stack pointer.
15392 // Clobbers R10, R11 and EFLAGS.
15393 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
15394 .addExternalSymbol("__chkstk")
15395 .addReg(X86::RAX, RegState::Implicit)
15396 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
15397 // RAX has the offset to be subtracted from RSP.
15398 BuildMI(*BB, MI, DL, TII->get(X86::SUB64rr), X86::RSP)
15403 const char *StackProbeSymbol =
15404 Subtarget->isTargetWindows() ? "_chkstk" : "_alloca";
15406 BuildMI(*BB, MI, DL, TII->get(X86::CALLpcrel32))
15407 .addExternalSymbol(StackProbeSymbol)
15408 .addReg(X86::EAX, RegState::Implicit)
15409 .addReg(X86::ESP, RegState::Implicit)
15410 .addReg(X86::EAX, RegState::Define | RegState::Implicit)
15411 .addReg(X86::ESP, RegState::Define | RegState::Implicit)
15412 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
15415 MI->eraseFromParent(); // The pseudo instruction is gone now.
15419 MachineBasicBlock *
15420 X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI,
15421 MachineBasicBlock *BB) const {
15422 // This is pretty easy. We're taking the value that we received from
15423 // our load from the relocation, sticking it in either RDI (x86-64)
15424 // or EAX and doing an indirect call. The return value will then
15425 // be in the normal return register.
15426 const X86InstrInfo *TII
15427 = static_cast<const X86InstrInfo*>(getTargetMachine().getInstrInfo());
15428 DebugLoc DL = MI->getDebugLoc();
15429 MachineFunction *F = BB->getParent();
15431 assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?");
15432 assert(MI->getOperand(3).isGlobal() && "This should be a global");
15434 // Get a register mask for the lowered call.
15435 // FIXME: The 32-bit calls have non-standard calling conventions. Use a
15436 // proper register mask.
15437 const uint32_t *RegMask =
15438 getTargetMachine().getRegisterInfo()->getCallPreservedMask(CallingConv::C);
15439 if (Subtarget->is64Bit()) {
15440 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
15441 TII->get(X86::MOV64rm), X86::RDI)
15443 .addImm(0).addReg(0)
15444 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
15445 MI->getOperand(3).getTargetFlags())
15447 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m));
15448 addDirectMem(MIB, X86::RDI);
15449 MIB.addReg(X86::RAX, RegState::ImplicitDefine).addRegMask(RegMask);
15450 } else if (getTargetMachine().getRelocationModel() != Reloc::PIC_) {
15451 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
15452 TII->get(X86::MOV32rm), X86::EAX)
15454 .addImm(0).addReg(0)
15455 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
15456 MI->getOperand(3).getTargetFlags())
15458 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
15459 addDirectMem(MIB, X86::EAX);
15460 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
15462 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
15463 TII->get(X86::MOV32rm), X86::EAX)
15464 .addReg(TII->getGlobalBaseReg(F))
15465 .addImm(0).addReg(0)
15466 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
15467 MI->getOperand(3).getTargetFlags())
15469 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
15470 addDirectMem(MIB, X86::EAX);
15471 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
15474 MI->eraseFromParent(); // The pseudo instruction is gone now.
15478 MachineBasicBlock *
15479 X86TargetLowering::emitEHSjLjSetJmp(MachineInstr *MI,
15480 MachineBasicBlock *MBB) const {
15481 DebugLoc DL = MI->getDebugLoc();
15482 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
15484 MachineFunction *MF = MBB->getParent();
15485 MachineRegisterInfo &MRI = MF->getRegInfo();
15487 const BasicBlock *BB = MBB->getBasicBlock();
15488 MachineFunction::iterator I = MBB;
15491 // Memory Reference
15492 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
15493 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
15496 unsigned MemOpndSlot = 0;
15498 unsigned CurOp = 0;
15500 DstReg = MI->getOperand(CurOp++).getReg();
15501 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
15502 assert(RC->hasType(MVT::i32) && "Invalid destination!");
15503 unsigned mainDstReg = MRI.createVirtualRegister(RC);
15504 unsigned restoreDstReg = MRI.createVirtualRegister(RC);
15506 MemOpndSlot = CurOp;
15508 MVT PVT = getPointerTy();
15509 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
15510 "Invalid Pointer Size!");
15512 // For v = setjmp(buf), we generate
15515 // buf[LabelOffset] = restoreMBB
15516 // SjLjSetup restoreMBB
15522 // v = phi(main, restore)
15527 MachineBasicBlock *thisMBB = MBB;
15528 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
15529 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
15530 MachineBasicBlock *restoreMBB = MF->CreateMachineBasicBlock(BB);
15531 MF->insert(I, mainMBB);
15532 MF->insert(I, sinkMBB);
15533 MF->push_back(restoreMBB);
15535 MachineInstrBuilder MIB;
15537 // Transfer the remainder of BB and its successor edges to sinkMBB.
15538 sinkMBB->splice(sinkMBB->begin(), MBB,
15539 llvm::next(MachineBasicBlock::iterator(MI)), MBB->end());
15540 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
15543 unsigned PtrStoreOpc = 0;
15544 unsigned LabelReg = 0;
15545 const int64_t LabelOffset = 1 * PVT.getStoreSize();
15546 Reloc::Model RM = getTargetMachine().getRelocationModel();
15547 bool UseImmLabel = (getTargetMachine().getCodeModel() == CodeModel::Small) &&
15548 (RM == Reloc::Static || RM == Reloc::DynamicNoPIC);
15550 // Prepare IP either in reg or imm.
15551 if (!UseImmLabel) {
15552 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mr : X86::MOV32mr;
15553 const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
15554 LabelReg = MRI.createVirtualRegister(PtrRC);
15555 if (Subtarget->is64Bit()) {
15556 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA64r), LabelReg)
15560 .addMBB(restoreMBB)
15563 const X86InstrInfo *XII = static_cast<const X86InstrInfo*>(TII);
15564 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA32r), LabelReg)
15565 .addReg(XII->getGlobalBaseReg(MF))
15568 .addMBB(restoreMBB, Subtarget->ClassifyBlockAddressReference())
15572 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mi32 : X86::MOV32mi;
15574 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PtrStoreOpc));
15575 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
15576 if (i == X86::AddrDisp)
15577 MIB.addDisp(MI->getOperand(MemOpndSlot + i), LabelOffset);
15579 MIB.addOperand(MI->getOperand(MemOpndSlot + i));
15582 MIB.addReg(LabelReg);
15584 MIB.addMBB(restoreMBB);
15585 MIB.setMemRefs(MMOBegin, MMOEnd);
15587 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::EH_SjLj_Setup))
15588 .addMBB(restoreMBB);
15590 const X86RegisterInfo *RegInfo =
15591 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
15592 MIB.addRegMask(RegInfo->getNoPreservedMask());
15593 thisMBB->addSuccessor(mainMBB);
15594 thisMBB->addSuccessor(restoreMBB);
15598 BuildMI(mainMBB, DL, TII->get(X86::MOV32r0), mainDstReg);
15599 mainMBB->addSuccessor(sinkMBB);
15602 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
15603 TII->get(X86::PHI), DstReg)
15604 .addReg(mainDstReg).addMBB(mainMBB)
15605 .addReg(restoreDstReg).addMBB(restoreMBB);
15608 BuildMI(restoreMBB, DL, TII->get(X86::MOV32ri), restoreDstReg).addImm(1);
15609 BuildMI(restoreMBB, DL, TII->get(X86::JMP_4)).addMBB(sinkMBB);
15610 restoreMBB->addSuccessor(sinkMBB);
15612 MI->eraseFromParent();
15616 MachineBasicBlock *
15617 X86TargetLowering::emitEHSjLjLongJmp(MachineInstr *MI,
15618 MachineBasicBlock *MBB) const {
15619 DebugLoc DL = MI->getDebugLoc();
15620 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
15622 MachineFunction *MF = MBB->getParent();
15623 MachineRegisterInfo &MRI = MF->getRegInfo();
15625 // Memory Reference
15626 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
15627 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
15629 MVT PVT = getPointerTy();
15630 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
15631 "Invalid Pointer Size!");
15633 const TargetRegisterClass *RC =
15634 (PVT == MVT::i64) ? &X86::GR64RegClass : &X86::GR32RegClass;
15635 unsigned Tmp = MRI.createVirtualRegister(RC);
15636 // Since FP is only updated here but NOT referenced, it's treated as GPR.
15637 const X86RegisterInfo *RegInfo =
15638 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
15639 unsigned FP = (PVT == MVT::i64) ? X86::RBP : X86::EBP;
15640 unsigned SP = RegInfo->getStackRegister();
15642 MachineInstrBuilder MIB;
15644 const int64_t LabelOffset = 1 * PVT.getStoreSize();
15645 const int64_t SPOffset = 2 * PVT.getStoreSize();
15647 unsigned PtrLoadOpc = (PVT == MVT::i64) ? X86::MOV64rm : X86::MOV32rm;
15648 unsigned IJmpOpc = (PVT == MVT::i64) ? X86::JMP64r : X86::JMP32r;
15651 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), FP);
15652 for (unsigned i = 0; i < X86::AddrNumOperands; ++i)
15653 MIB.addOperand(MI->getOperand(i));
15654 MIB.setMemRefs(MMOBegin, MMOEnd);
15656 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), Tmp);
15657 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
15658 if (i == X86::AddrDisp)
15659 MIB.addDisp(MI->getOperand(i), LabelOffset);
15661 MIB.addOperand(MI->getOperand(i));
15663 MIB.setMemRefs(MMOBegin, MMOEnd);
15665 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), SP);
15666 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
15667 if (i == X86::AddrDisp)
15668 MIB.addDisp(MI->getOperand(i), SPOffset);
15670 MIB.addOperand(MI->getOperand(i));
15672 MIB.setMemRefs(MMOBegin, MMOEnd);
15674 BuildMI(*MBB, MI, DL, TII->get(IJmpOpc)).addReg(Tmp);
15676 MI->eraseFromParent();
15680 MachineBasicBlock *
15681 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
15682 MachineBasicBlock *BB) const {
15683 switch (MI->getOpcode()) {
15684 default: llvm_unreachable("Unexpected instr type to insert");
15685 case X86::TAILJMPd64:
15686 case X86::TAILJMPr64:
15687 case X86::TAILJMPm64:
15688 llvm_unreachable("TAILJMP64 would not be touched here.");
15689 case X86::TCRETURNdi64:
15690 case X86::TCRETURNri64:
15691 case X86::TCRETURNmi64:
15693 case X86::WIN_ALLOCA:
15694 return EmitLoweredWinAlloca(MI, BB);
15695 case X86::SEG_ALLOCA_32:
15696 return EmitLoweredSegAlloca(MI, BB, false);
15697 case X86::SEG_ALLOCA_64:
15698 return EmitLoweredSegAlloca(MI, BB, true);
15699 case X86::TLSCall_32:
15700 case X86::TLSCall_64:
15701 return EmitLoweredTLSCall(MI, BB);
15702 case X86::CMOV_GR8:
15703 case X86::CMOV_FR32:
15704 case X86::CMOV_FR64:
15705 case X86::CMOV_V4F32:
15706 case X86::CMOV_V2F64:
15707 case X86::CMOV_V2I64:
15708 case X86::CMOV_V8F32:
15709 case X86::CMOV_V4F64:
15710 case X86::CMOV_V4I64:
15711 case X86::CMOV_GR16:
15712 case X86::CMOV_GR32:
15713 case X86::CMOV_RFP32:
15714 case X86::CMOV_RFP64:
15715 case X86::CMOV_RFP80:
15716 return EmitLoweredSelect(MI, BB);
15718 case X86::FP32_TO_INT16_IN_MEM:
15719 case X86::FP32_TO_INT32_IN_MEM:
15720 case X86::FP32_TO_INT64_IN_MEM:
15721 case X86::FP64_TO_INT16_IN_MEM:
15722 case X86::FP64_TO_INT32_IN_MEM:
15723 case X86::FP64_TO_INT64_IN_MEM:
15724 case X86::FP80_TO_INT16_IN_MEM:
15725 case X86::FP80_TO_INT32_IN_MEM:
15726 case X86::FP80_TO_INT64_IN_MEM: {
15727 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
15728 DebugLoc DL = MI->getDebugLoc();
15730 // Change the floating point control register to use "round towards zero"
15731 // mode when truncating to an integer value.
15732 MachineFunction *F = BB->getParent();
15733 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false);
15734 addFrameReference(BuildMI(*BB, MI, DL,
15735 TII->get(X86::FNSTCW16m)), CWFrameIdx);
15737 // Load the old value of the high byte of the control word...
15739 F->getRegInfo().createVirtualRegister(&X86::GR16RegClass);
15740 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW),
15743 // Set the high part to be round to zero...
15744 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
15747 // Reload the modified control word now...
15748 addFrameReference(BuildMI(*BB, MI, DL,
15749 TII->get(X86::FLDCW16m)), CWFrameIdx);
15751 // Restore the memory image of control word to original value
15752 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
15755 // Get the X86 opcode to use.
15757 switch (MI->getOpcode()) {
15758 default: llvm_unreachable("illegal opcode!");
15759 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
15760 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
15761 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
15762 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
15763 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
15764 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
15765 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
15766 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
15767 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
15771 MachineOperand &Op = MI->getOperand(0);
15773 AM.BaseType = X86AddressMode::RegBase;
15774 AM.Base.Reg = Op.getReg();
15776 AM.BaseType = X86AddressMode::FrameIndexBase;
15777 AM.Base.FrameIndex = Op.getIndex();
15779 Op = MI->getOperand(1);
15781 AM.Scale = Op.getImm();
15782 Op = MI->getOperand(2);
15784 AM.IndexReg = Op.getImm();
15785 Op = MI->getOperand(3);
15786 if (Op.isGlobal()) {
15787 AM.GV = Op.getGlobal();
15789 AM.Disp = Op.getImm();
15791 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM)
15792 .addReg(MI->getOperand(X86::AddrNumOperands).getReg());
15794 // Reload the original control word now.
15795 addFrameReference(BuildMI(*BB, MI, DL,
15796 TII->get(X86::FLDCW16m)), CWFrameIdx);
15798 MI->eraseFromParent(); // The pseudo instruction is gone now.
15801 // String/text processing lowering.
15802 case X86::PCMPISTRM128REG:
15803 case X86::VPCMPISTRM128REG:
15804 case X86::PCMPISTRM128MEM:
15805 case X86::VPCMPISTRM128MEM:
15806 case X86::PCMPESTRM128REG:
15807 case X86::VPCMPESTRM128REG:
15808 case X86::PCMPESTRM128MEM:
15809 case X86::VPCMPESTRM128MEM:
15810 assert(Subtarget->hasSSE42() &&
15811 "Target must have SSE4.2 or AVX features enabled");
15812 return EmitPCMPSTRM(MI, BB, getTargetMachine().getInstrInfo());
15814 // String/text processing lowering.
15815 case X86::PCMPISTRIREG:
15816 case X86::VPCMPISTRIREG:
15817 case X86::PCMPISTRIMEM:
15818 case X86::VPCMPISTRIMEM:
15819 case X86::PCMPESTRIREG:
15820 case X86::VPCMPESTRIREG:
15821 case X86::PCMPESTRIMEM:
15822 case X86::VPCMPESTRIMEM:
15823 assert(Subtarget->hasSSE42() &&
15824 "Target must have SSE4.2 or AVX features enabled");
15825 return EmitPCMPSTRI(MI, BB, getTargetMachine().getInstrInfo());
15827 // Thread synchronization.
15829 return EmitMonitor(MI, BB, getTargetMachine().getInstrInfo(), Subtarget);
15833 return EmitXBegin(MI, BB, getTargetMachine().getInstrInfo());
15835 // Atomic Lowering.
15836 case X86::ATOMAND8:
15837 case X86::ATOMAND16:
15838 case X86::ATOMAND32:
15839 case X86::ATOMAND64:
15842 case X86::ATOMOR16:
15843 case X86::ATOMOR32:
15844 case X86::ATOMOR64:
15846 case X86::ATOMXOR16:
15847 case X86::ATOMXOR8:
15848 case X86::ATOMXOR32:
15849 case X86::ATOMXOR64:
15851 case X86::ATOMNAND8:
15852 case X86::ATOMNAND16:
15853 case X86::ATOMNAND32:
15854 case X86::ATOMNAND64:
15856 case X86::ATOMMAX8:
15857 case X86::ATOMMAX16:
15858 case X86::ATOMMAX32:
15859 case X86::ATOMMAX64:
15861 case X86::ATOMMIN8:
15862 case X86::ATOMMIN16:
15863 case X86::ATOMMIN32:
15864 case X86::ATOMMIN64:
15866 case X86::ATOMUMAX8:
15867 case X86::ATOMUMAX16:
15868 case X86::ATOMUMAX32:
15869 case X86::ATOMUMAX64:
15871 case X86::ATOMUMIN8:
15872 case X86::ATOMUMIN16:
15873 case X86::ATOMUMIN32:
15874 case X86::ATOMUMIN64:
15875 return EmitAtomicLoadArith(MI, BB);
15877 // This group does 64-bit operations on a 32-bit host.
15878 case X86::ATOMAND6432:
15879 case X86::ATOMOR6432:
15880 case X86::ATOMXOR6432:
15881 case X86::ATOMNAND6432:
15882 case X86::ATOMADD6432:
15883 case X86::ATOMSUB6432:
15884 case X86::ATOMMAX6432:
15885 case X86::ATOMMIN6432:
15886 case X86::ATOMUMAX6432:
15887 case X86::ATOMUMIN6432:
15888 case X86::ATOMSWAP6432:
15889 return EmitAtomicLoadArith6432(MI, BB);
15891 case X86::VASTART_SAVE_XMM_REGS:
15892 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
15894 case X86::VAARG_64:
15895 return EmitVAARG64WithCustomInserter(MI, BB);
15897 case X86::EH_SjLj_SetJmp32:
15898 case X86::EH_SjLj_SetJmp64:
15899 return emitEHSjLjSetJmp(MI, BB);
15901 case X86::EH_SjLj_LongJmp32:
15902 case X86::EH_SjLj_LongJmp64:
15903 return emitEHSjLjLongJmp(MI, BB);
15907 //===----------------------------------------------------------------------===//
15908 // X86 Optimization Hooks
15909 //===----------------------------------------------------------------------===//
15911 void X86TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
15914 const SelectionDAG &DAG,
15915 unsigned Depth) const {
15916 unsigned BitWidth = KnownZero.getBitWidth();
15917 unsigned Opc = Op.getOpcode();
15918 assert((Opc >= ISD::BUILTIN_OP_END ||
15919 Opc == ISD::INTRINSIC_WO_CHAIN ||
15920 Opc == ISD::INTRINSIC_W_CHAIN ||
15921 Opc == ISD::INTRINSIC_VOID) &&
15922 "Should use MaskedValueIsZero if you don't know whether Op"
15923 " is a target node!");
15925 KnownZero = KnownOne = APInt(BitWidth, 0); // Don't know anything.
15939 // These nodes' second result is a boolean.
15940 if (Op.getResNo() == 0)
15943 case X86ISD::SETCC:
15944 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1);
15946 case ISD::INTRINSIC_WO_CHAIN: {
15947 unsigned IntId = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
15948 unsigned NumLoBits = 0;
15951 case Intrinsic::x86_sse_movmsk_ps:
15952 case Intrinsic::x86_avx_movmsk_ps_256:
15953 case Intrinsic::x86_sse2_movmsk_pd:
15954 case Intrinsic::x86_avx_movmsk_pd_256:
15955 case Intrinsic::x86_mmx_pmovmskb:
15956 case Intrinsic::x86_sse2_pmovmskb_128:
15957 case Intrinsic::x86_avx2_pmovmskb: {
15958 // High bits of movmskp{s|d}, pmovmskb are known zero.
15960 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
15961 case Intrinsic::x86_sse_movmsk_ps: NumLoBits = 4; break;
15962 case Intrinsic::x86_avx_movmsk_ps_256: NumLoBits = 8; break;
15963 case Intrinsic::x86_sse2_movmsk_pd: NumLoBits = 2; break;
15964 case Intrinsic::x86_avx_movmsk_pd_256: NumLoBits = 4; break;
15965 case Intrinsic::x86_mmx_pmovmskb: NumLoBits = 8; break;
15966 case Intrinsic::x86_sse2_pmovmskb_128: NumLoBits = 16; break;
15967 case Intrinsic::x86_avx2_pmovmskb: NumLoBits = 32; break;
15969 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - NumLoBits);
15978 unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(SDValue Op,
15979 unsigned Depth) const {
15980 // SETCC_CARRY sets the dest to ~0 for true or 0 for false.
15981 if (Op.getOpcode() == X86ISD::SETCC_CARRY)
15982 return Op.getValueType().getScalarType().getSizeInBits();
15988 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
15989 /// node is a GlobalAddress + offset.
15990 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
15991 const GlobalValue* &GA,
15992 int64_t &Offset) const {
15993 if (N->getOpcode() == X86ISD::Wrapper) {
15994 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
15995 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
15996 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
16000 return TargetLowering::isGAPlusOffset(N, GA, Offset);
16003 /// isShuffleHigh128VectorInsertLow - Checks whether the shuffle node is the
16004 /// same as extracting the high 128-bit part of 256-bit vector and then
16005 /// inserting the result into the low part of a new 256-bit vector
16006 static bool isShuffleHigh128VectorInsertLow(ShuffleVectorSDNode *SVOp) {
16007 EVT VT = SVOp->getValueType(0);
16008 unsigned NumElems = VT.getVectorNumElements();
16010 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
16011 for (unsigned i = 0, j = NumElems/2; i != NumElems/2; ++i, ++j)
16012 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
16013 SVOp->getMaskElt(j) >= 0)
16019 /// isShuffleLow128VectorInsertHigh - Checks whether the shuffle node is the
16020 /// same as extracting the low 128-bit part of 256-bit vector and then
16021 /// inserting the result into the high part of a new 256-bit vector
16022 static bool isShuffleLow128VectorInsertHigh(ShuffleVectorSDNode *SVOp) {
16023 EVT VT = SVOp->getValueType(0);
16024 unsigned NumElems = VT.getVectorNumElements();
16026 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
16027 for (unsigned i = NumElems/2, j = 0; i != NumElems; ++i, ++j)
16028 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
16029 SVOp->getMaskElt(j) >= 0)
16035 /// PerformShuffleCombine256 - Performs shuffle combines for 256-bit vectors.
16036 static SDValue PerformShuffleCombine256(SDNode *N, SelectionDAG &DAG,
16037 TargetLowering::DAGCombinerInfo &DCI,
16038 const X86Subtarget* Subtarget) {
16040 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
16041 SDValue V1 = SVOp->getOperand(0);
16042 SDValue V2 = SVOp->getOperand(1);
16043 EVT VT = SVOp->getValueType(0);
16044 unsigned NumElems = VT.getVectorNumElements();
16046 if (V1.getOpcode() == ISD::CONCAT_VECTORS &&
16047 V2.getOpcode() == ISD::CONCAT_VECTORS) {
16051 // V UNDEF BUILD_VECTOR UNDEF
16053 // CONCAT_VECTOR CONCAT_VECTOR
16056 // RESULT: V + zero extended
16058 if (V2.getOperand(0).getOpcode() != ISD::BUILD_VECTOR ||
16059 V2.getOperand(1).getOpcode() != ISD::UNDEF ||
16060 V1.getOperand(1).getOpcode() != ISD::UNDEF)
16063 if (!ISD::isBuildVectorAllZeros(V2.getOperand(0).getNode()))
16066 // To match the shuffle mask, the first half of the mask should
16067 // be exactly the first vector, and all the rest a splat with the
16068 // first element of the second one.
16069 for (unsigned i = 0; i != NumElems/2; ++i)
16070 if (!isUndefOrEqual(SVOp->getMaskElt(i), i) ||
16071 !isUndefOrEqual(SVOp->getMaskElt(i+NumElems/2), NumElems))
16074 // If V1 is coming from a vector load then just fold to a VZEXT_LOAD.
16075 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(V1.getOperand(0))) {
16076 if (Ld->hasNUsesOfValue(1, 0)) {
16077 SDVTList Tys = DAG.getVTList(MVT::v4i64, MVT::Other);
16078 SDValue Ops[] = { Ld->getChain(), Ld->getBasePtr() };
16080 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops,
16081 array_lengthof(Ops),
16083 Ld->getPointerInfo(),
16084 Ld->getAlignment(),
16085 false/*isVolatile*/, true/*ReadMem*/,
16086 false/*WriteMem*/);
16088 // Make sure the newly-created LOAD is in the same position as Ld in
16089 // terms of dependency. We create a TokenFactor for Ld and ResNode,
16090 // and update uses of Ld's output chain to use the TokenFactor.
16091 if (Ld->hasAnyUseOfValue(1)) {
16092 SDValue NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
16093 SDValue(Ld, 1), SDValue(ResNode.getNode(), 1));
16094 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), NewChain);
16095 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(Ld, 1),
16096 SDValue(ResNode.getNode(), 1));
16099 return DAG.getNode(ISD::BITCAST, dl, VT, ResNode);
16103 // Emit a zeroed vector and insert the desired subvector on its
16105 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
16106 SDValue InsV = Insert128BitVector(Zeros, V1.getOperand(0), 0, DAG, dl);
16107 return DCI.CombineTo(N, InsV);
16110 //===--------------------------------------------------------------------===//
16111 // Combine some shuffles into subvector extracts and inserts:
16114 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
16115 if (isShuffleHigh128VectorInsertLow(SVOp)) {
16116 SDValue V = Extract128BitVector(V1, NumElems/2, DAG, dl);
16117 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, 0, DAG, dl);
16118 return DCI.CombineTo(N, InsV);
16121 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
16122 if (isShuffleLow128VectorInsertHigh(SVOp)) {
16123 SDValue V = Extract128BitVector(V1, 0, DAG, dl);
16124 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, NumElems/2, DAG, dl);
16125 return DCI.CombineTo(N, InsV);
16131 /// PerformShuffleCombine - Performs several different shuffle combines.
16132 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
16133 TargetLowering::DAGCombinerInfo &DCI,
16134 const X86Subtarget *Subtarget) {
16136 EVT VT = N->getValueType(0);
16138 // Don't create instructions with illegal types after legalize types has run.
16139 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
16140 if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType()))
16143 // Combine 256-bit vector shuffles. This is only profitable when in AVX mode
16144 if (Subtarget->hasFp256() && VT.is256BitVector() &&
16145 N->getOpcode() == ISD::VECTOR_SHUFFLE)
16146 return PerformShuffleCombine256(N, DAG, DCI, Subtarget);
16148 // Only handle 128 wide vector from here on.
16149 if (!VT.is128BitVector())
16152 // Combine a vector_shuffle that is equal to build_vector load1, load2, load3,
16153 // load4, <0, 1, 2, 3> into a 128-bit load if the load addresses are
16154 // consecutive, non-overlapping, and in the right order.
16155 SmallVector<SDValue, 16> Elts;
16156 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
16157 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0));
16159 return EltsFromConsecutiveLoads(VT, Elts, dl, DAG);
16162 /// PerformTruncateCombine - Converts truncate operation to
16163 /// a sequence of vector shuffle operations.
16164 /// It is possible when we truncate 256-bit vector to 128-bit vector
16165 static SDValue PerformTruncateCombine(SDNode *N, SelectionDAG &DAG,
16166 TargetLowering::DAGCombinerInfo &DCI,
16167 const X86Subtarget *Subtarget) {
16171 /// XFormVExtractWithShuffleIntoLoad - Check if a vector extract from a target
16172 /// specific shuffle of a load can be folded into a single element load.
16173 /// Similar handling for VECTOR_SHUFFLE is performed by DAGCombiner, but
16174 /// shuffles have been customed lowered so we need to handle those here.
16175 static SDValue XFormVExtractWithShuffleIntoLoad(SDNode *N, SelectionDAG &DAG,
16176 TargetLowering::DAGCombinerInfo &DCI) {
16177 if (DCI.isBeforeLegalizeOps())
16180 SDValue InVec = N->getOperand(0);
16181 SDValue EltNo = N->getOperand(1);
16183 if (!isa<ConstantSDNode>(EltNo))
16186 EVT VT = InVec.getValueType();
16188 bool HasShuffleIntoBitcast = false;
16189 if (InVec.getOpcode() == ISD::BITCAST) {
16190 // Don't duplicate a load with other uses.
16191 if (!InVec.hasOneUse())
16193 EVT BCVT = InVec.getOperand(0).getValueType();
16194 if (BCVT.getVectorNumElements() != VT.getVectorNumElements())
16196 InVec = InVec.getOperand(0);
16197 HasShuffleIntoBitcast = true;
16200 if (!isTargetShuffle(InVec.getOpcode()))
16203 // Don't duplicate a load with other uses.
16204 if (!InVec.hasOneUse())
16207 SmallVector<int, 16> ShuffleMask;
16209 if (!getTargetShuffleMask(InVec.getNode(), VT.getSimpleVT(), ShuffleMask,
16213 // Select the input vector, guarding against out of range extract vector.
16214 unsigned NumElems = VT.getVectorNumElements();
16215 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
16216 int Idx = (Elt > (int)NumElems) ? -1 : ShuffleMask[Elt];
16217 SDValue LdNode = (Idx < (int)NumElems) ? InVec.getOperand(0)
16218 : InVec.getOperand(1);
16220 // If inputs to shuffle are the same for both ops, then allow 2 uses
16221 unsigned AllowedUses = InVec.getOperand(0) == InVec.getOperand(1) ? 2 : 1;
16223 if (LdNode.getOpcode() == ISD::BITCAST) {
16224 // Don't duplicate a load with other uses.
16225 if (!LdNode.getNode()->hasNUsesOfValue(AllowedUses, 0))
16228 AllowedUses = 1; // only allow 1 load use if we have a bitcast
16229 LdNode = LdNode.getOperand(0);
16232 if (!ISD::isNormalLoad(LdNode.getNode()))
16235 LoadSDNode *LN0 = cast<LoadSDNode>(LdNode);
16237 if (!LN0 ||!LN0->hasNUsesOfValue(AllowedUses, 0) || LN0->isVolatile())
16240 if (HasShuffleIntoBitcast) {
16241 // If there's a bitcast before the shuffle, check if the load type and
16242 // alignment is valid.
16243 unsigned Align = LN0->getAlignment();
16244 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
16245 unsigned NewAlign = TLI.getDataLayout()->
16246 getABITypeAlignment(VT.getTypeForEVT(*DAG.getContext()));
16248 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, VT))
16252 // All checks match so transform back to vector_shuffle so that DAG combiner
16253 // can finish the job
16256 // Create shuffle node taking into account the case that its a unary shuffle
16257 SDValue Shuffle = (UnaryShuffle) ? DAG.getUNDEF(VT) : InVec.getOperand(1);
16258 Shuffle = DAG.getVectorShuffle(InVec.getValueType(), dl,
16259 InVec.getOperand(0), Shuffle,
16261 Shuffle = DAG.getNode(ISD::BITCAST, dl, VT, Shuffle);
16262 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, N->getValueType(0), Shuffle,
16266 /// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index
16267 /// generation and convert it from being a bunch of shuffles and extracts
16268 /// to a simple store and scalar loads to extract the elements.
16269 static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG,
16270 TargetLowering::DAGCombinerInfo &DCI) {
16271 SDValue NewOp = XFormVExtractWithShuffleIntoLoad(N, DAG, DCI);
16272 if (NewOp.getNode())
16275 SDValue InputVector = N->getOperand(0);
16276 // Detect whether we are trying to convert from mmx to i32 and the bitcast
16277 // from mmx to v2i32 has a single usage.
16278 if (InputVector.getNode()->getOpcode() == llvm::ISD::BITCAST &&
16279 InputVector.getNode()->getOperand(0).getValueType() == MVT::x86mmx &&
16280 InputVector.hasOneUse() && N->getValueType(0) == MVT::i32)
16281 return DAG.getNode(X86ISD::MMX_MOVD2W, SDLoc(InputVector),
16282 N->getValueType(0),
16283 InputVector.getNode()->getOperand(0));
16285 // Only operate on vectors of 4 elements, where the alternative shuffling
16286 // gets to be more expensive.
16287 if (InputVector.getValueType() != MVT::v4i32)
16290 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a
16291 // single use which is a sign-extend or zero-extend, and all elements are
16293 SmallVector<SDNode *, 4> Uses;
16294 unsigned ExtractedElements = 0;
16295 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(),
16296 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) {
16297 if (UI.getUse().getResNo() != InputVector.getResNo())
16300 SDNode *Extract = *UI;
16301 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
16304 if (Extract->getValueType(0) != MVT::i32)
16306 if (!Extract->hasOneUse())
16308 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND &&
16309 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND)
16311 if (!isa<ConstantSDNode>(Extract->getOperand(1)))
16314 // Record which element was extracted.
16315 ExtractedElements |=
16316 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue();
16318 Uses.push_back(Extract);
16321 // If not all the elements were used, this may not be worthwhile.
16322 if (ExtractedElements != 15)
16325 // Ok, we've now decided to do the transformation.
16326 SDLoc dl(InputVector);
16328 // Store the value to a temporary stack slot.
16329 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType());
16330 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr,
16331 MachinePointerInfo(), false, false, 0);
16333 // Replace each use (extract) with a load of the appropriate element.
16334 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(),
16335 UE = Uses.end(); UI != UE; ++UI) {
16336 SDNode *Extract = *UI;
16338 // cOMpute the element's address.
16339 SDValue Idx = Extract->getOperand(1);
16341 InputVector.getValueType().getVectorElementType().getSizeInBits()/8;
16342 uint64_t Offset = EltSize * cast<ConstantSDNode>(Idx)->getZExtValue();
16343 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
16344 SDValue OffsetVal = DAG.getConstant(Offset, TLI.getPointerTy());
16346 SDValue ScalarAddr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(),
16347 StackPtr, OffsetVal);
16349 // Load the scalar.
16350 SDValue LoadScalar = DAG.getLoad(Extract->getValueType(0), dl, Ch,
16351 ScalarAddr, MachinePointerInfo(),
16352 false, false, false, 0);
16354 // Replace the exact with the load.
16355 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), LoadScalar);
16358 // The replacement was made in place; don't return anything.
16362 /// \brief Matches a VSELECT onto min/max or return 0 if the node doesn't match.
16363 static std::pair<unsigned, bool>
16364 matchIntegerMINMAX(SDValue Cond, EVT VT, SDValue LHS, SDValue RHS,
16365 SelectionDAG &DAG, const X86Subtarget *Subtarget) {
16366 if (!VT.isVector())
16367 return std::make_pair(0, false);
16369 bool NeedSplit = false;
16370 switch (VT.getSimpleVT().SimpleTy) {
16371 default: return std::make_pair(0, false);
16375 if (!Subtarget->hasAVX2())
16377 if (!Subtarget->hasAVX())
16378 return std::make_pair(0, false);
16383 if (!Subtarget->hasSSE2())
16384 return std::make_pair(0, false);
16387 // SSE2 has only a small subset of the operations.
16388 bool hasUnsigned = Subtarget->hasSSE41() ||
16389 (Subtarget->hasSSE2() && VT == MVT::v16i8);
16390 bool hasSigned = Subtarget->hasSSE41() ||
16391 (Subtarget->hasSSE2() && VT == MVT::v8i16);
16393 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
16396 // Check for x CC y ? x : y.
16397 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
16398 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
16403 Opc = hasUnsigned ? X86ISD::UMIN : 0; break;
16406 Opc = hasUnsigned ? X86ISD::UMAX : 0; break;
16409 Opc = hasSigned ? X86ISD::SMIN : 0; break;
16412 Opc = hasSigned ? X86ISD::SMAX : 0; break;
16414 // Check for x CC y ? y : x -- a min/max with reversed arms.
16415 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
16416 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
16421 Opc = hasUnsigned ? X86ISD::UMAX : 0; break;
16424 Opc = hasUnsigned ? X86ISD::UMIN : 0; break;
16427 Opc = hasSigned ? X86ISD::SMAX : 0; break;
16430 Opc = hasSigned ? X86ISD::SMIN : 0; break;
16434 return std::make_pair(Opc, NeedSplit);
16437 /// PerformSELECTCombine - Do target-specific dag combines on SELECT and VSELECT
16439 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
16440 TargetLowering::DAGCombinerInfo &DCI,
16441 const X86Subtarget *Subtarget) {
16443 SDValue Cond = N->getOperand(0);
16444 // Get the LHS/RHS of the select.
16445 SDValue LHS = N->getOperand(1);
16446 SDValue RHS = N->getOperand(2);
16447 EVT VT = LHS.getValueType();
16448 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
16450 // If we have SSE[12] support, try to form min/max nodes. SSE min/max
16451 // instructions match the semantics of the common C idiom x<y?x:y but not
16452 // x<=y?x:y, because of how they handle negative zero (which can be
16453 // ignored in unsafe-math mode).
16454 if (Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() &&
16455 VT != MVT::f80 && TLI.isTypeLegal(VT) &&
16456 (Subtarget->hasSSE2() ||
16457 (Subtarget->hasSSE1() && VT.getScalarType() == MVT::f32))) {
16458 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
16460 unsigned Opcode = 0;
16461 // Check for x CC y ? x : y.
16462 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
16463 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
16467 // Converting this to a min would handle NaNs incorrectly, and swapping
16468 // the operands would cause it to handle comparisons between positive
16469 // and negative zero incorrectly.
16470 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
16471 if (!DAG.getTarget().Options.UnsafeFPMath &&
16472 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
16474 std::swap(LHS, RHS);
16476 Opcode = X86ISD::FMIN;
16479 // Converting this to a min would handle comparisons between positive
16480 // and negative zero incorrectly.
16481 if (!DAG.getTarget().Options.UnsafeFPMath &&
16482 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
16484 Opcode = X86ISD::FMIN;
16487 // Converting this to a min would handle both negative zeros and NaNs
16488 // incorrectly, but we can swap the operands to fix both.
16489 std::swap(LHS, RHS);
16493 Opcode = X86ISD::FMIN;
16497 // Converting this to a max would handle comparisons between positive
16498 // and negative zero incorrectly.
16499 if (!DAG.getTarget().Options.UnsafeFPMath &&
16500 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
16502 Opcode = X86ISD::FMAX;
16505 // Converting this to a max would handle NaNs incorrectly, and swapping
16506 // the operands would cause it to handle comparisons between positive
16507 // and negative zero incorrectly.
16508 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
16509 if (!DAG.getTarget().Options.UnsafeFPMath &&
16510 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
16512 std::swap(LHS, RHS);
16514 Opcode = X86ISD::FMAX;
16517 // Converting this to a max would handle both negative zeros and NaNs
16518 // incorrectly, but we can swap the operands to fix both.
16519 std::swap(LHS, RHS);
16523 Opcode = X86ISD::FMAX;
16526 // Check for x CC y ? y : x -- a min/max with reversed arms.
16527 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
16528 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
16532 // Converting this to a min would handle comparisons between positive
16533 // and negative zero incorrectly, and swapping the operands would
16534 // cause it to handle NaNs incorrectly.
16535 if (!DAG.getTarget().Options.UnsafeFPMath &&
16536 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) {
16537 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
16539 std::swap(LHS, RHS);
16541 Opcode = X86ISD::FMIN;
16544 // Converting this to a min would handle NaNs incorrectly.
16545 if (!DAG.getTarget().Options.UnsafeFPMath &&
16546 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
16548 Opcode = X86ISD::FMIN;
16551 // Converting this to a min would handle both negative zeros and NaNs
16552 // incorrectly, but we can swap the operands to fix both.
16553 std::swap(LHS, RHS);
16557 Opcode = X86ISD::FMIN;
16561 // Converting this to a max would handle NaNs incorrectly.
16562 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
16564 Opcode = X86ISD::FMAX;
16567 // Converting this to a max would handle comparisons between positive
16568 // and negative zero incorrectly, and swapping the operands would
16569 // cause it to handle NaNs incorrectly.
16570 if (!DAG.getTarget().Options.UnsafeFPMath &&
16571 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) {
16572 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
16574 std::swap(LHS, RHS);
16576 Opcode = X86ISD::FMAX;
16579 // Converting this to a max would handle both negative zeros and NaNs
16580 // incorrectly, but we can swap the operands to fix both.
16581 std::swap(LHS, RHS);
16585 Opcode = X86ISD::FMAX;
16591 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
16594 if (Subtarget->hasAVX512() && VT.isVector() &&
16595 Cond.getValueType().getVectorElementType() == MVT::i1) {
16596 // v16i8 (select v16i1, v16i8, v16i8) does not have a proper
16597 // lowering on AVX-512. In this case we convert it to
16598 // v16i8 (select v16i8, v16i8, v16i8) and use AVX instruction.
16599 // The same situation for all 128 and 256-bit vectors of i8 and i16
16600 EVT OpVT = LHS.getValueType();
16601 if ((OpVT.is128BitVector() || OpVT.is256BitVector()) &&
16602 (OpVT.getVectorElementType() == MVT::i8 ||
16603 OpVT.getVectorElementType() == MVT::i16)) {
16604 Cond = DAG.getNode(ISD::SIGN_EXTEND, DL, OpVT, Cond);
16605 DCI.AddToWorklist(Cond.getNode());
16606 return DAG.getNode(N->getOpcode(), DL, OpVT, Cond, LHS, RHS);
16609 // If this is a select between two integer constants, try to do some
16611 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
16612 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
16613 // Don't do this for crazy integer types.
16614 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
16615 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
16616 // so that TrueC (the true value) is larger than FalseC.
16617 bool NeedsCondInvert = false;
16619 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
16620 // Efficiently invertible.
16621 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
16622 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
16623 isa<ConstantSDNode>(Cond.getOperand(1))))) {
16624 NeedsCondInvert = true;
16625 std::swap(TrueC, FalseC);
16628 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
16629 if (FalseC->getAPIntValue() == 0 &&
16630 TrueC->getAPIntValue().isPowerOf2()) {
16631 if (NeedsCondInvert) // Invert the condition if needed.
16632 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
16633 DAG.getConstant(1, Cond.getValueType()));
16635 // Zero extend the condition if needed.
16636 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
16638 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
16639 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
16640 DAG.getConstant(ShAmt, MVT::i8));
16643 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
16644 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
16645 if (NeedsCondInvert) // Invert the condition if needed.
16646 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
16647 DAG.getConstant(1, Cond.getValueType()));
16649 // Zero extend the condition if needed.
16650 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
16651 FalseC->getValueType(0), Cond);
16652 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
16653 SDValue(FalseC, 0));
16656 // Optimize cases that will turn into an LEA instruction. This requires
16657 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
16658 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
16659 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
16660 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
16662 bool isFastMultiplier = false;
16664 switch ((unsigned char)Diff) {
16666 case 1: // result = add base, cond
16667 case 2: // result = lea base( , cond*2)
16668 case 3: // result = lea base(cond, cond*2)
16669 case 4: // result = lea base( , cond*4)
16670 case 5: // result = lea base(cond, cond*4)
16671 case 8: // result = lea base( , cond*8)
16672 case 9: // result = lea base(cond, cond*8)
16673 isFastMultiplier = true;
16678 if (isFastMultiplier) {
16679 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
16680 if (NeedsCondInvert) // Invert the condition if needed.
16681 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
16682 DAG.getConstant(1, Cond.getValueType()));
16684 // Zero extend the condition if needed.
16685 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
16687 // Scale the condition by the difference.
16689 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
16690 DAG.getConstant(Diff, Cond.getValueType()));
16692 // Add the base if non-zero.
16693 if (FalseC->getAPIntValue() != 0)
16694 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
16695 SDValue(FalseC, 0));
16702 // Canonicalize max and min:
16703 // (x > y) ? x : y -> (x >= y) ? x : y
16704 // (x < y) ? x : y -> (x <= y) ? x : y
16705 // This allows use of COND_S / COND_NS (see TranslateX86CC) which eliminates
16706 // the need for an extra compare
16707 // against zero. e.g.
16708 // (x - y) > 0 : (x - y) ? 0 -> (x - y) >= 0 : (x - y) ? 0
16710 // testl %edi, %edi
16712 // cmovgl %edi, %eax
16716 // cmovsl %eax, %edi
16717 if (N->getOpcode() == ISD::SELECT && Cond.getOpcode() == ISD::SETCC &&
16718 DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
16719 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
16720 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
16725 ISD::CondCode NewCC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGE;
16726 Cond = DAG.getSetCC(SDLoc(Cond), Cond.getValueType(),
16727 Cond.getOperand(0), Cond.getOperand(1), NewCC);
16728 return DAG.getNode(ISD::SELECT, DL, VT, Cond, LHS, RHS);
16733 // Early exit check
16734 if (!TLI.isTypeLegal(VT))
16737 // Match VSELECTs into subs with unsigned saturation.
16738 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC &&
16739 // psubus is available in SSE2 and AVX2 for i8 and i16 vectors.
16740 ((Subtarget->hasSSE2() && (VT == MVT::v16i8 || VT == MVT::v8i16)) ||
16741 (Subtarget->hasAVX2() && (VT == MVT::v32i8 || VT == MVT::v16i16)))) {
16742 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
16744 // Check if one of the arms of the VSELECT is a zero vector. If it's on the
16745 // left side invert the predicate to simplify logic below.
16747 if (ISD::isBuildVectorAllZeros(LHS.getNode())) {
16749 CC = ISD::getSetCCInverse(CC, true);
16750 } else if (ISD::isBuildVectorAllZeros(RHS.getNode())) {
16754 if (Other.getNode() && Other->getNumOperands() == 2 &&
16755 DAG.isEqualTo(Other->getOperand(0), Cond.getOperand(0))) {
16756 SDValue OpLHS = Other->getOperand(0), OpRHS = Other->getOperand(1);
16757 SDValue CondRHS = Cond->getOperand(1);
16759 // Look for a general sub with unsigned saturation first.
16760 // x >= y ? x-y : 0 --> subus x, y
16761 // x > y ? x-y : 0 --> subus x, y
16762 if ((CC == ISD::SETUGE || CC == ISD::SETUGT) &&
16763 Other->getOpcode() == ISD::SUB && DAG.isEqualTo(OpRHS, CondRHS))
16764 return DAG.getNode(X86ISD::SUBUS, DL, VT, OpLHS, OpRHS);
16766 // If the RHS is a constant we have to reverse the const canonicalization.
16767 // x > C-1 ? x+-C : 0 --> subus x, C
16768 if (CC == ISD::SETUGT && Other->getOpcode() == ISD::ADD &&
16769 isSplatVector(CondRHS.getNode()) && isSplatVector(OpRHS.getNode())) {
16770 APInt A = cast<ConstantSDNode>(OpRHS.getOperand(0))->getAPIntValue();
16771 if (CondRHS.getConstantOperandVal(0) == -A-1)
16772 return DAG.getNode(X86ISD::SUBUS, DL, VT, OpLHS,
16773 DAG.getConstant(-A, VT));
16776 // Another special case: If C was a sign bit, the sub has been
16777 // canonicalized into a xor.
16778 // FIXME: Would it be better to use ComputeMaskedBits to determine whether
16779 // it's safe to decanonicalize the xor?
16780 // x s< 0 ? x^C : 0 --> subus x, C
16781 if (CC == ISD::SETLT && Other->getOpcode() == ISD::XOR &&
16782 ISD::isBuildVectorAllZeros(CondRHS.getNode()) &&
16783 isSplatVector(OpRHS.getNode())) {
16784 APInt A = cast<ConstantSDNode>(OpRHS.getOperand(0))->getAPIntValue();
16786 return DAG.getNode(X86ISD::SUBUS, DL, VT, OpLHS, OpRHS);
16791 // Try to match a min/max vector operation.
16792 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC) {
16793 std::pair<unsigned, bool> ret = matchIntegerMINMAX(Cond, VT, LHS, RHS, DAG, Subtarget);
16794 unsigned Opc = ret.first;
16795 bool NeedSplit = ret.second;
16797 if (Opc && NeedSplit) {
16798 unsigned NumElems = VT.getVectorNumElements();
16799 // Extract the LHS vectors
16800 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, DL);
16801 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, DL);
16803 // Extract the RHS vectors
16804 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, DL);
16805 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, DL);
16807 // Create min/max for each subvector
16808 LHS = DAG.getNode(Opc, DL, LHS1.getValueType(), LHS1, RHS1);
16809 RHS = DAG.getNode(Opc, DL, LHS2.getValueType(), LHS2, RHS2);
16811 // Merge the result
16812 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LHS, RHS);
16814 return DAG.getNode(Opc, DL, VT, LHS, RHS);
16817 // Simplify vector selection if the selector will be produced by CMPP*/PCMP*.
16818 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC &&
16819 // Check if SETCC has already been promoted
16820 TLI.getSetCCResultType(*DAG.getContext(), VT) == Cond.getValueType()) {
16822 assert(Cond.getValueType().isVector() &&
16823 "vector select expects a vector selector!");
16825 EVT IntVT = Cond.getValueType();
16826 bool TValIsAllOnes = ISD::isBuildVectorAllOnes(LHS.getNode());
16827 bool FValIsAllZeros = ISD::isBuildVectorAllZeros(RHS.getNode());
16829 if (!TValIsAllOnes && !FValIsAllZeros) {
16830 // Try invert the condition if true value is not all 1s and false value
16832 bool TValIsAllZeros = ISD::isBuildVectorAllZeros(LHS.getNode());
16833 bool FValIsAllOnes = ISD::isBuildVectorAllOnes(RHS.getNode());
16835 if (TValIsAllZeros || FValIsAllOnes) {
16836 SDValue CC = Cond.getOperand(2);
16837 ISD::CondCode NewCC =
16838 ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
16839 Cond.getOperand(0).getValueType().isInteger());
16840 Cond = DAG.getSetCC(DL, IntVT, Cond.getOperand(0), Cond.getOperand(1), NewCC);
16841 std::swap(LHS, RHS);
16842 TValIsAllOnes = FValIsAllOnes;
16843 FValIsAllZeros = TValIsAllZeros;
16847 if (TValIsAllOnes || FValIsAllZeros) {
16850 if (TValIsAllOnes && FValIsAllZeros)
16852 else if (TValIsAllOnes)
16853 Ret = DAG.getNode(ISD::OR, DL, IntVT, Cond,
16854 DAG.getNode(ISD::BITCAST, DL, IntVT, RHS));
16855 else if (FValIsAllZeros)
16856 Ret = DAG.getNode(ISD::AND, DL, IntVT, Cond,
16857 DAG.getNode(ISD::BITCAST, DL, IntVT, LHS));
16859 return DAG.getNode(ISD::BITCAST, DL, VT, Ret);
16863 // If we know that this node is legal then we know that it is going to be
16864 // matched by one of the SSE/AVX BLEND instructions. These instructions only
16865 // depend on the highest bit in each word. Try to use SimplifyDemandedBits
16866 // to simplify previous instructions.
16867 if (N->getOpcode() == ISD::VSELECT && DCI.isBeforeLegalizeOps() &&
16868 !DCI.isBeforeLegalize() && TLI.isOperationLegal(ISD::VSELECT, VT)) {
16869 unsigned BitWidth = Cond.getValueType().getScalarType().getSizeInBits();
16871 // Don't optimize vector selects that map to mask-registers.
16875 assert(BitWidth >= 8 && BitWidth <= 64 && "Invalid mask size");
16876 APInt DemandedMask = APInt::getHighBitsSet(BitWidth, 1);
16878 APInt KnownZero, KnownOne;
16879 TargetLowering::TargetLoweringOpt TLO(DAG, DCI.isBeforeLegalize(),
16880 DCI.isBeforeLegalizeOps());
16881 if (TLO.ShrinkDemandedConstant(Cond, DemandedMask) ||
16882 TLI.SimplifyDemandedBits(Cond, DemandedMask, KnownZero, KnownOne, TLO))
16883 DCI.CommitTargetLoweringOpt(TLO);
16889 // Check whether a boolean test is testing a boolean value generated by
16890 // X86ISD::SETCC. If so, return the operand of that SETCC and proper condition
16893 // Simplify the following patterns:
16894 // (Op (CMP (SETCC Cond EFLAGS) 1) EQ) or
16895 // (Op (CMP (SETCC Cond EFLAGS) 0) NEQ)
16896 // to (Op EFLAGS Cond)
16898 // (Op (CMP (SETCC Cond EFLAGS) 0) EQ) or
16899 // (Op (CMP (SETCC Cond EFLAGS) 1) NEQ)
16900 // to (Op EFLAGS !Cond)
16902 // where Op could be BRCOND or CMOV.
16904 static SDValue checkBoolTestSetCCCombine(SDValue Cmp, X86::CondCode &CC) {
16905 // Quit if not CMP and SUB with its value result used.
16906 if (Cmp.getOpcode() != X86ISD::CMP &&
16907 (Cmp.getOpcode() != X86ISD::SUB || Cmp.getNode()->hasAnyUseOfValue(0)))
16910 // Quit if not used as a boolean value.
16911 if (CC != X86::COND_E && CC != X86::COND_NE)
16914 // Check CMP operands. One of them should be 0 or 1 and the other should be
16915 // an SetCC or extended from it.
16916 SDValue Op1 = Cmp.getOperand(0);
16917 SDValue Op2 = Cmp.getOperand(1);
16920 const ConstantSDNode* C = 0;
16921 bool needOppositeCond = (CC == X86::COND_E);
16922 bool checkAgainstTrue = false; // Is it a comparison against 1?
16924 if ((C = dyn_cast<ConstantSDNode>(Op1)))
16926 else if ((C = dyn_cast<ConstantSDNode>(Op2)))
16928 else // Quit if all operands are not constants.
16931 if (C->getZExtValue() == 1) {
16932 needOppositeCond = !needOppositeCond;
16933 checkAgainstTrue = true;
16934 } else if (C->getZExtValue() != 0)
16935 // Quit if the constant is neither 0 or 1.
16938 bool truncatedToBoolWithAnd = false;
16939 // Skip (zext $x), (trunc $x), or (and $x, 1) node.
16940 while (SetCC.getOpcode() == ISD::ZERO_EXTEND ||
16941 SetCC.getOpcode() == ISD::TRUNCATE ||
16942 SetCC.getOpcode() == ISD::AND) {
16943 if (SetCC.getOpcode() == ISD::AND) {
16945 ConstantSDNode *CS;
16946 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(0))) &&
16947 CS->getZExtValue() == 1)
16949 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(1))) &&
16950 CS->getZExtValue() == 1)
16954 SetCC = SetCC.getOperand(OpIdx);
16955 truncatedToBoolWithAnd = true;
16957 SetCC = SetCC.getOperand(0);
16960 switch (SetCC.getOpcode()) {
16961 case X86ISD::SETCC_CARRY:
16962 // Since SETCC_CARRY gives output based on R = CF ? ~0 : 0, it's unsafe to
16963 // simplify it if the result of SETCC_CARRY is not canonicalized to 0 or 1,
16964 // i.e. it's a comparison against true but the result of SETCC_CARRY is not
16965 // truncated to i1 using 'and'.
16966 if (checkAgainstTrue && !truncatedToBoolWithAnd)
16968 assert(X86::CondCode(SetCC.getConstantOperandVal(0)) == X86::COND_B &&
16969 "Invalid use of SETCC_CARRY!");
16971 case X86ISD::SETCC:
16972 // Set the condition code or opposite one if necessary.
16973 CC = X86::CondCode(SetCC.getConstantOperandVal(0));
16974 if (needOppositeCond)
16975 CC = X86::GetOppositeBranchCondition(CC);
16976 return SetCC.getOperand(1);
16977 case X86ISD::CMOV: {
16978 // Check whether false/true value has canonical one, i.e. 0 or 1.
16979 ConstantSDNode *FVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(0));
16980 ConstantSDNode *TVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(1));
16981 // Quit if true value is not a constant.
16984 // Quit if false value is not a constant.
16986 SDValue Op = SetCC.getOperand(0);
16987 // Skip 'zext' or 'trunc' node.
16988 if (Op.getOpcode() == ISD::ZERO_EXTEND ||
16989 Op.getOpcode() == ISD::TRUNCATE)
16990 Op = Op.getOperand(0);
16991 // A special case for rdrand/rdseed, where 0 is set if false cond is
16993 if ((Op.getOpcode() != X86ISD::RDRAND &&
16994 Op.getOpcode() != X86ISD::RDSEED) || Op.getResNo() != 0)
16997 // Quit if false value is not the constant 0 or 1.
16998 bool FValIsFalse = true;
16999 if (FVal && FVal->getZExtValue() != 0) {
17000 if (FVal->getZExtValue() != 1)
17002 // If FVal is 1, opposite cond is needed.
17003 needOppositeCond = !needOppositeCond;
17004 FValIsFalse = false;
17006 // Quit if TVal is not the constant opposite of FVal.
17007 if (FValIsFalse && TVal->getZExtValue() != 1)
17009 if (!FValIsFalse && TVal->getZExtValue() != 0)
17011 CC = X86::CondCode(SetCC.getConstantOperandVal(2));
17012 if (needOppositeCond)
17013 CC = X86::GetOppositeBranchCondition(CC);
17014 return SetCC.getOperand(3);
17021 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
17022 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
17023 TargetLowering::DAGCombinerInfo &DCI,
17024 const X86Subtarget *Subtarget) {
17027 // If the flag operand isn't dead, don't touch this CMOV.
17028 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
17031 SDValue FalseOp = N->getOperand(0);
17032 SDValue TrueOp = N->getOperand(1);
17033 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
17034 SDValue Cond = N->getOperand(3);
17036 if (CC == X86::COND_E || CC == X86::COND_NE) {
17037 switch (Cond.getOpcode()) {
17041 // If operand of BSR / BSF are proven never zero, then ZF cannot be set.
17042 if (DAG.isKnownNeverZero(Cond.getOperand(0)))
17043 return (CC == X86::COND_E) ? FalseOp : TrueOp;
17049 Flags = checkBoolTestSetCCCombine(Cond, CC);
17050 if (Flags.getNode() &&
17051 // Extra check as FCMOV only supports a subset of X86 cond.
17052 (FalseOp.getValueType() != MVT::f80 || hasFPCMov(CC))) {
17053 SDValue Ops[] = { FalseOp, TrueOp,
17054 DAG.getConstant(CC, MVT::i8), Flags };
17055 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList(),
17056 Ops, array_lengthof(Ops));
17059 // If this is a select between two integer constants, try to do some
17060 // optimizations. Note that the operands are ordered the opposite of SELECT
17062 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(TrueOp)) {
17063 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(FalseOp)) {
17064 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
17065 // larger than FalseC (the false value).
17066 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
17067 CC = X86::GetOppositeBranchCondition(CC);
17068 std::swap(TrueC, FalseC);
17069 std::swap(TrueOp, FalseOp);
17072 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
17073 // This is efficient for any integer data type (including i8/i16) and
17075 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
17076 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
17077 DAG.getConstant(CC, MVT::i8), Cond);
17079 // Zero extend the condition if needed.
17080 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
17082 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
17083 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
17084 DAG.getConstant(ShAmt, MVT::i8));
17085 if (N->getNumValues() == 2) // Dead flag value?
17086 return DCI.CombineTo(N, Cond, SDValue());
17090 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
17091 // for any integer data type, including i8/i16.
17092 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
17093 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
17094 DAG.getConstant(CC, MVT::i8), Cond);
17096 // Zero extend the condition if needed.
17097 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
17098 FalseC->getValueType(0), Cond);
17099 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
17100 SDValue(FalseC, 0));
17102 if (N->getNumValues() == 2) // Dead flag value?
17103 return DCI.CombineTo(N, Cond, SDValue());
17107 // Optimize cases that will turn into an LEA instruction. This requires
17108 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
17109 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
17110 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
17111 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
17113 bool isFastMultiplier = false;
17115 switch ((unsigned char)Diff) {
17117 case 1: // result = add base, cond
17118 case 2: // result = lea base( , cond*2)
17119 case 3: // result = lea base(cond, cond*2)
17120 case 4: // result = lea base( , cond*4)
17121 case 5: // result = lea base(cond, cond*4)
17122 case 8: // result = lea base( , cond*8)
17123 case 9: // result = lea base(cond, cond*8)
17124 isFastMultiplier = true;
17129 if (isFastMultiplier) {
17130 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
17131 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
17132 DAG.getConstant(CC, MVT::i8), Cond);
17133 // Zero extend the condition if needed.
17134 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
17136 // Scale the condition by the difference.
17138 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
17139 DAG.getConstant(Diff, Cond.getValueType()));
17141 // Add the base if non-zero.
17142 if (FalseC->getAPIntValue() != 0)
17143 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
17144 SDValue(FalseC, 0));
17145 if (N->getNumValues() == 2) // Dead flag value?
17146 return DCI.CombineTo(N, Cond, SDValue());
17153 // Handle these cases:
17154 // (select (x != c), e, c) -> select (x != c), e, x),
17155 // (select (x == c), c, e) -> select (x == c), x, e)
17156 // where the c is an integer constant, and the "select" is the combination
17157 // of CMOV and CMP.
17159 // The rationale for this change is that the conditional-move from a constant
17160 // needs two instructions, however, conditional-move from a register needs
17161 // only one instruction.
17163 // CAVEAT: By replacing a constant with a symbolic value, it may obscure
17164 // some instruction-combining opportunities. This opt needs to be
17165 // postponed as late as possible.
17167 if (!DCI.isBeforeLegalize() && !DCI.isBeforeLegalizeOps()) {
17168 // the DCI.xxxx conditions are provided to postpone the optimization as
17169 // late as possible.
17171 ConstantSDNode *CmpAgainst = 0;
17172 if ((Cond.getOpcode() == X86ISD::CMP || Cond.getOpcode() == X86ISD::SUB) &&
17173 (CmpAgainst = dyn_cast<ConstantSDNode>(Cond.getOperand(1))) &&
17174 !isa<ConstantSDNode>(Cond.getOperand(0))) {
17176 if (CC == X86::COND_NE &&
17177 CmpAgainst == dyn_cast<ConstantSDNode>(FalseOp)) {
17178 CC = X86::GetOppositeBranchCondition(CC);
17179 std::swap(TrueOp, FalseOp);
17182 if (CC == X86::COND_E &&
17183 CmpAgainst == dyn_cast<ConstantSDNode>(TrueOp)) {
17184 SDValue Ops[] = { FalseOp, Cond.getOperand(0),
17185 DAG.getConstant(CC, MVT::i8), Cond };
17186 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList (), Ops,
17187 array_lengthof(Ops));
17195 /// PerformMulCombine - Optimize a single multiply with constant into two
17196 /// in order to implement it with two cheaper instructions, e.g.
17197 /// LEA + SHL, LEA + LEA.
17198 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
17199 TargetLowering::DAGCombinerInfo &DCI) {
17200 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
17203 EVT VT = N->getValueType(0);
17204 if (VT != MVT::i64)
17207 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
17210 uint64_t MulAmt = C->getZExtValue();
17211 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
17214 uint64_t MulAmt1 = 0;
17215 uint64_t MulAmt2 = 0;
17216 if ((MulAmt % 9) == 0) {
17218 MulAmt2 = MulAmt / 9;
17219 } else if ((MulAmt % 5) == 0) {
17221 MulAmt2 = MulAmt / 5;
17222 } else if ((MulAmt % 3) == 0) {
17224 MulAmt2 = MulAmt / 3;
17227 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
17230 if (isPowerOf2_64(MulAmt2) &&
17231 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
17232 // If second multiplifer is pow2, issue it first. We want the multiply by
17233 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
17235 std::swap(MulAmt1, MulAmt2);
17238 if (isPowerOf2_64(MulAmt1))
17239 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
17240 DAG.getConstant(Log2_64(MulAmt1), MVT::i8));
17242 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
17243 DAG.getConstant(MulAmt1, VT));
17245 if (isPowerOf2_64(MulAmt2))
17246 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
17247 DAG.getConstant(Log2_64(MulAmt2), MVT::i8));
17249 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
17250 DAG.getConstant(MulAmt2, VT));
17252 // Do not add new nodes to DAG combiner worklist.
17253 DCI.CombineTo(N, NewMul, false);
17258 static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) {
17259 SDValue N0 = N->getOperand(0);
17260 SDValue N1 = N->getOperand(1);
17261 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
17262 EVT VT = N0.getValueType();
17264 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2))
17265 // since the result of setcc_c is all zero's or all ones.
17266 if (VT.isInteger() && !VT.isVector() &&
17267 N1C && N0.getOpcode() == ISD::AND &&
17268 N0.getOperand(1).getOpcode() == ISD::Constant) {
17269 SDValue N00 = N0.getOperand(0);
17270 if (N00.getOpcode() == X86ISD::SETCC_CARRY ||
17271 ((N00.getOpcode() == ISD::ANY_EXTEND ||
17272 N00.getOpcode() == ISD::ZERO_EXTEND) &&
17273 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY)) {
17274 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
17275 APInt ShAmt = N1C->getAPIntValue();
17276 Mask = Mask.shl(ShAmt);
17278 return DAG.getNode(ISD::AND, SDLoc(N), VT,
17279 N00, DAG.getConstant(Mask, VT));
17283 // Hardware support for vector shifts is sparse which makes us scalarize the
17284 // vector operations in many cases. Also, on sandybridge ADD is faster than
17286 // (shl V, 1) -> add V,V
17287 if (isSplatVector(N1.getNode())) {
17288 assert(N0.getValueType().isVector() && "Invalid vector shift type");
17289 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1->getOperand(0));
17290 // We shift all of the values by one. In many cases we do not have
17291 // hardware support for this operation. This is better expressed as an ADD
17293 if (N1C && (1 == N1C->getZExtValue())) {
17294 return DAG.getNode(ISD::ADD, SDLoc(N), VT, N0, N0);
17301 /// \brief Returns a vector of 0s if the node in input is a vector logical
17302 /// shift by a constant amount which is known to be bigger than or equal
17303 /// to the vector element size in bits.
17304 static SDValue performShiftToAllZeros(SDNode *N, SelectionDAG &DAG,
17305 const X86Subtarget *Subtarget) {
17306 EVT VT = N->getValueType(0);
17308 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16 &&
17309 (!Subtarget->hasInt256() ||
17310 (VT != MVT::v4i64 && VT != MVT::v8i32 && VT != MVT::v16i16)))
17313 SDValue Amt = N->getOperand(1);
17315 if (isSplatVector(Amt.getNode())) {
17316 SDValue SclrAmt = Amt->getOperand(0);
17317 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(SclrAmt)) {
17318 APInt ShiftAmt = C->getAPIntValue();
17319 unsigned MaxAmount = VT.getVectorElementType().getSizeInBits();
17321 // SSE2/AVX2 logical shifts always return a vector of 0s
17322 // if the shift amount is bigger than or equal to
17323 // the element size. The constant shift amount will be
17324 // encoded as a 8-bit immediate.
17325 if (ShiftAmt.trunc(8).uge(MaxAmount))
17326 return getZeroVector(VT, Subtarget, DAG, DL);
17333 /// PerformShiftCombine - Combine shifts.
17334 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
17335 TargetLowering::DAGCombinerInfo &DCI,
17336 const X86Subtarget *Subtarget) {
17337 if (N->getOpcode() == ISD::SHL) {
17338 SDValue V = PerformSHLCombine(N, DAG);
17339 if (V.getNode()) return V;
17342 if (N->getOpcode() != ISD::SRA) {
17343 // Try to fold this logical shift into a zero vector.
17344 SDValue V = performShiftToAllZeros(N, DAG, Subtarget);
17345 if (V.getNode()) return V;
17351 // CMPEQCombine - Recognize the distinctive (AND (setcc ...) (setcc ..))
17352 // where both setccs reference the same FP CMP, and rewrite for CMPEQSS
17353 // and friends. Likewise for OR -> CMPNEQSS.
17354 static SDValue CMPEQCombine(SDNode *N, SelectionDAG &DAG,
17355 TargetLowering::DAGCombinerInfo &DCI,
17356 const X86Subtarget *Subtarget) {
17359 // SSE1 supports CMP{eq|ne}SS, and SSE2 added CMP{eq|ne}SD, but
17360 // we're requiring SSE2 for both.
17361 if (Subtarget->hasSSE2() && isAndOrOfSetCCs(SDValue(N, 0U), opcode)) {
17362 SDValue N0 = N->getOperand(0);
17363 SDValue N1 = N->getOperand(1);
17364 SDValue CMP0 = N0->getOperand(1);
17365 SDValue CMP1 = N1->getOperand(1);
17368 // The SETCCs should both refer to the same CMP.
17369 if (CMP0.getOpcode() != X86ISD::CMP || CMP0 != CMP1)
17372 SDValue CMP00 = CMP0->getOperand(0);
17373 SDValue CMP01 = CMP0->getOperand(1);
17374 EVT VT = CMP00.getValueType();
17376 if (VT == MVT::f32 || VT == MVT::f64) {
17377 bool ExpectingFlags = false;
17378 // Check for any users that want flags:
17379 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
17380 !ExpectingFlags && UI != UE; ++UI)
17381 switch (UI->getOpcode()) {
17386 ExpectingFlags = true;
17388 case ISD::CopyToReg:
17389 case ISD::SIGN_EXTEND:
17390 case ISD::ZERO_EXTEND:
17391 case ISD::ANY_EXTEND:
17395 if (!ExpectingFlags) {
17396 enum X86::CondCode cc0 = (enum X86::CondCode)N0.getConstantOperandVal(0);
17397 enum X86::CondCode cc1 = (enum X86::CondCode)N1.getConstantOperandVal(0);
17399 if (cc1 == X86::COND_E || cc1 == X86::COND_NE) {
17400 X86::CondCode tmp = cc0;
17405 if ((cc0 == X86::COND_E && cc1 == X86::COND_NP) ||
17406 (cc0 == X86::COND_NE && cc1 == X86::COND_P)) {
17407 bool is64BitFP = (CMP00.getValueType() == MVT::f64);
17408 X86ISD::NodeType NTOperator = is64BitFP ?
17409 X86ISD::FSETCCsd : X86ISD::FSETCCss;
17410 // FIXME: need symbolic constants for these magic numbers.
17411 // See X86ATTInstPrinter.cpp:printSSECC().
17412 unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4;
17413 SDValue OnesOrZeroesF = DAG.getNode(NTOperator, DL, MVT::f32, CMP00, CMP01,
17414 DAG.getConstant(x86cc, MVT::i8));
17415 SDValue OnesOrZeroesI = DAG.getNode(ISD::BITCAST, DL, MVT::i32,
17417 SDValue ANDed = DAG.getNode(ISD::AND, DL, MVT::i32, OnesOrZeroesI,
17418 DAG.getConstant(1, MVT::i32));
17419 SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8, ANDed);
17420 return OneBitOfTruth;
17428 /// CanFoldXORWithAllOnes - Test whether the XOR operand is a AllOnes vector
17429 /// so it can be folded inside ANDNP.
17430 static bool CanFoldXORWithAllOnes(const SDNode *N) {
17431 EVT VT = N->getValueType(0);
17433 // Match direct AllOnes for 128 and 256-bit vectors
17434 if (ISD::isBuildVectorAllOnes(N))
17437 // Look through a bit convert.
17438 if (N->getOpcode() == ISD::BITCAST)
17439 N = N->getOperand(0).getNode();
17441 // Sometimes the operand may come from a insert_subvector building a 256-bit
17443 if (VT.is256BitVector() &&
17444 N->getOpcode() == ISD::INSERT_SUBVECTOR) {
17445 SDValue V1 = N->getOperand(0);
17446 SDValue V2 = N->getOperand(1);
17448 if (V1.getOpcode() == ISD::INSERT_SUBVECTOR &&
17449 V1.getOperand(0).getOpcode() == ISD::UNDEF &&
17450 ISD::isBuildVectorAllOnes(V1.getOperand(1).getNode()) &&
17451 ISD::isBuildVectorAllOnes(V2.getNode()))
17458 // On AVX/AVX2 the type v8i1 is legalized to v8i16, which is an XMM sized
17459 // register. In most cases we actually compare or select YMM-sized registers
17460 // and mixing the two types creates horrible code. This method optimizes
17461 // some of the transition sequences.
17462 static SDValue WidenMaskArithmetic(SDNode *N, SelectionDAG &DAG,
17463 TargetLowering::DAGCombinerInfo &DCI,
17464 const X86Subtarget *Subtarget) {
17465 EVT VT = N->getValueType(0);
17466 if (!VT.is256BitVector())
17469 assert((N->getOpcode() == ISD::ANY_EXTEND ||
17470 N->getOpcode() == ISD::ZERO_EXTEND ||
17471 N->getOpcode() == ISD::SIGN_EXTEND) && "Invalid Node");
17473 SDValue Narrow = N->getOperand(0);
17474 EVT NarrowVT = Narrow->getValueType(0);
17475 if (!NarrowVT.is128BitVector())
17478 if (Narrow->getOpcode() != ISD::XOR &&
17479 Narrow->getOpcode() != ISD::AND &&
17480 Narrow->getOpcode() != ISD::OR)
17483 SDValue N0 = Narrow->getOperand(0);
17484 SDValue N1 = Narrow->getOperand(1);
17487 // The Left side has to be a trunc.
17488 if (N0.getOpcode() != ISD::TRUNCATE)
17491 // The type of the truncated inputs.
17492 EVT WideVT = N0->getOperand(0)->getValueType(0);
17496 // The right side has to be a 'trunc' or a constant vector.
17497 bool RHSTrunc = N1.getOpcode() == ISD::TRUNCATE;
17498 bool RHSConst = (isSplatVector(N1.getNode()) &&
17499 isa<ConstantSDNode>(N1->getOperand(0)));
17500 if (!RHSTrunc && !RHSConst)
17503 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
17505 if (!TLI.isOperationLegalOrPromote(Narrow->getOpcode(), WideVT))
17508 // Set N0 and N1 to hold the inputs to the new wide operation.
17509 N0 = N0->getOperand(0);
17511 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, WideVT.getScalarType(),
17512 N1->getOperand(0));
17513 SmallVector<SDValue, 8> C(WideVT.getVectorNumElements(), N1);
17514 N1 = DAG.getNode(ISD::BUILD_VECTOR, DL, WideVT, &C[0], C.size());
17515 } else if (RHSTrunc) {
17516 N1 = N1->getOperand(0);
17519 // Generate the wide operation.
17520 SDValue Op = DAG.getNode(Narrow->getOpcode(), DL, WideVT, N0, N1);
17521 unsigned Opcode = N->getOpcode();
17523 case ISD::ANY_EXTEND:
17525 case ISD::ZERO_EXTEND: {
17526 unsigned InBits = NarrowVT.getScalarType().getSizeInBits();
17527 APInt Mask = APInt::getAllOnesValue(InBits);
17528 Mask = Mask.zext(VT.getScalarType().getSizeInBits());
17529 return DAG.getNode(ISD::AND, DL, VT,
17530 Op, DAG.getConstant(Mask, VT));
17532 case ISD::SIGN_EXTEND:
17533 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT,
17534 Op, DAG.getValueType(NarrowVT));
17536 llvm_unreachable("Unexpected opcode");
17540 static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG,
17541 TargetLowering::DAGCombinerInfo &DCI,
17542 const X86Subtarget *Subtarget) {
17543 EVT VT = N->getValueType(0);
17544 if (DCI.isBeforeLegalizeOps())
17547 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
17551 // Create BLSI, BLSR, and BZHI instructions
17552 // BLSI is X & (-X)
17553 // BLSR is X & (X-1)
17554 // BZHI is X & ((1 << Y) - 1)
17555 // BEXTR is ((X >> imm) & (2**size-1))
17556 if (VT == MVT::i32 || VT == MVT::i64) {
17557 SDValue N0 = N->getOperand(0);
17558 SDValue N1 = N->getOperand(1);
17561 if (Subtarget->hasBMI()) {
17562 // Check LHS for neg
17563 if (N0.getOpcode() == ISD::SUB && N0.getOperand(1) == N1 &&
17564 isZero(N0.getOperand(0)))
17565 return DAG.getNode(X86ISD::BLSI, DL, VT, N1);
17567 // Check RHS for neg
17568 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1) == N0 &&
17569 isZero(N1.getOperand(0)))
17570 return DAG.getNode(X86ISD::BLSI, DL, VT, N0);
17572 // Check LHS for X-1
17573 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1 &&
17574 isAllOnes(N0.getOperand(1)))
17575 return DAG.getNode(X86ISD::BLSR, DL, VT, N1);
17577 // Check RHS for X-1
17578 if (N1.getOpcode() == ISD::ADD && N1.getOperand(0) == N0 &&
17579 isAllOnes(N1.getOperand(1)))
17580 return DAG.getNode(X86ISD::BLSR, DL, VT, N0);
17583 if (Subtarget->hasBMI2()) {
17584 // Check for (and (add (shl 1, Y), -1), X)
17585 if (N0.getOpcode() == ISD::ADD && isAllOnes(N0.getOperand(1))) {
17586 SDValue N00 = N0.getOperand(0);
17587 if (N00.getOpcode() == ISD::SHL) {
17588 SDValue N001 = N00.getOperand(1);
17589 assert(N001.getValueType() == MVT::i8 && "unexpected type");
17590 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N00.getOperand(0));
17591 if (C && C->getZExtValue() == 1)
17592 return DAG.getNode(X86ISD::BZHI, DL, VT, N1, N001);
17596 // Check for (and X, (add (shl 1, Y), -1))
17597 if (N1.getOpcode() == ISD::ADD && isAllOnes(N1.getOperand(1))) {
17598 SDValue N10 = N1.getOperand(0);
17599 if (N10.getOpcode() == ISD::SHL) {
17600 SDValue N101 = N10.getOperand(1);
17601 assert(N101.getValueType() == MVT::i8 && "unexpected type");
17602 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N10.getOperand(0));
17603 if (C && C->getZExtValue() == 1)
17604 return DAG.getNode(X86ISD::BZHI, DL, VT, N0, N101);
17609 // Check for BEXTR.
17610 if ((Subtarget->hasBMI() || Subtarget->hasTBM()) &&
17611 (N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::SRL)) {
17612 ConstantSDNode *MaskNode = dyn_cast<ConstantSDNode>(N1);
17613 ConstantSDNode *ShiftNode = dyn_cast<ConstantSDNode>(N0.getOperand(1));
17614 if (MaskNode && ShiftNode) {
17615 uint64_t Mask = MaskNode->getZExtValue();
17616 uint64_t Shift = ShiftNode->getZExtValue();
17617 if (isMask_64(Mask)) {
17618 uint64_t MaskSize = CountPopulation_64(Mask);
17619 if (Shift + MaskSize <= VT.getSizeInBits())
17620 return DAG.getNode(X86ISD::BEXTR, DL, VT, N0.getOperand(0),
17621 DAG.getConstant(Shift | (MaskSize << 8), VT));
17629 // Want to form ANDNP nodes:
17630 // 1) In the hopes of then easily combining them with OR and AND nodes
17631 // to form PBLEND/PSIGN.
17632 // 2) To match ANDN packed intrinsics
17633 if (VT != MVT::v2i64 && VT != MVT::v4i64)
17636 SDValue N0 = N->getOperand(0);
17637 SDValue N1 = N->getOperand(1);
17640 // Check LHS for vnot
17641 if (N0.getOpcode() == ISD::XOR &&
17642 //ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode()))
17643 CanFoldXORWithAllOnes(N0.getOperand(1).getNode()))
17644 return DAG.getNode(X86ISD::ANDNP, DL, VT, N0.getOperand(0), N1);
17646 // Check RHS for vnot
17647 if (N1.getOpcode() == ISD::XOR &&
17648 //ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode()))
17649 CanFoldXORWithAllOnes(N1.getOperand(1).getNode()))
17650 return DAG.getNode(X86ISD::ANDNP, DL, VT, N1.getOperand(0), N0);
17655 static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
17656 TargetLowering::DAGCombinerInfo &DCI,
17657 const X86Subtarget *Subtarget) {
17658 EVT VT = N->getValueType(0);
17659 if (DCI.isBeforeLegalizeOps())
17662 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
17666 SDValue N0 = N->getOperand(0);
17667 SDValue N1 = N->getOperand(1);
17669 // look for psign/blend
17670 if (VT == MVT::v2i64 || VT == MVT::v4i64) {
17671 if (!Subtarget->hasSSSE3() ||
17672 (VT == MVT::v4i64 && !Subtarget->hasInt256()))
17675 // Canonicalize pandn to RHS
17676 if (N0.getOpcode() == X86ISD::ANDNP)
17678 // or (and (m, y), (pandn m, x))
17679 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::ANDNP) {
17680 SDValue Mask = N1.getOperand(0);
17681 SDValue X = N1.getOperand(1);
17683 if (N0.getOperand(0) == Mask)
17684 Y = N0.getOperand(1);
17685 if (N0.getOperand(1) == Mask)
17686 Y = N0.getOperand(0);
17688 // Check to see if the mask appeared in both the AND and ANDNP and
17692 // Validate that X, Y, and Mask are BIT_CONVERTS, and see through them.
17693 // Look through mask bitcast.
17694 if (Mask.getOpcode() == ISD::BITCAST)
17695 Mask = Mask.getOperand(0);
17696 if (X.getOpcode() == ISD::BITCAST)
17697 X = X.getOperand(0);
17698 if (Y.getOpcode() == ISD::BITCAST)
17699 Y = Y.getOperand(0);
17701 EVT MaskVT = Mask.getValueType();
17703 // Validate that the Mask operand is a vector sra node.
17704 // FIXME: what to do for bytes, since there is a psignb/pblendvb, but
17705 // there is no psrai.b
17706 unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits();
17707 unsigned SraAmt = ~0;
17708 if (Mask.getOpcode() == ISD::SRA) {
17709 SDValue Amt = Mask.getOperand(1);
17710 if (isSplatVector(Amt.getNode())) {
17711 SDValue SclrAmt = Amt->getOperand(0);
17712 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(SclrAmt))
17713 SraAmt = C->getZExtValue();
17715 } else if (Mask.getOpcode() == X86ISD::VSRAI) {
17716 SDValue SraC = Mask.getOperand(1);
17717 SraAmt = cast<ConstantSDNode>(SraC)->getZExtValue();
17719 if ((SraAmt + 1) != EltBits)
17724 // Now we know we at least have a plendvb with the mask val. See if
17725 // we can form a psignb/w/d.
17726 // psign = x.type == y.type == mask.type && y = sub(0, x);
17727 if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X &&
17728 ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) &&
17729 X.getValueType() == MaskVT && Y.getValueType() == MaskVT) {
17730 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
17731 "Unsupported VT for PSIGN");
17732 Mask = DAG.getNode(X86ISD::PSIGN, DL, MaskVT, X, Mask.getOperand(0));
17733 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
17735 // PBLENDVB only available on SSE 4.1
17736 if (!Subtarget->hasSSE41())
17739 EVT BlendVT = (VT == MVT::v4i64) ? MVT::v32i8 : MVT::v16i8;
17741 X = DAG.getNode(ISD::BITCAST, DL, BlendVT, X);
17742 Y = DAG.getNode(ISD::BITCAST, DL, BlendVT, Y);
17743 Mask = DAG.getNode(ISD::BITCAST, DL, BlendVT, Mask);
17744 Mask = DAG.getNode(ISD::VSELECT, DL, BlendVT, Mask, Y, X);
17745 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
17749 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64)
17752 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
17753 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
17755 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
17757 if (!N0.hasOneUse() || !N1.hasOneUse())
17760 SDValue ShAmt0 = N0.getOperand(1);
17761 if (ShAmt0.getValueType() != MVT::i8)
17763 SDValue ShAmt1 = N1.getOperand(1);
17764 if (ShAmt1.getValueType() != MVT::i8)
17766 if (ShAmt0.getOpcode() == ISD::TRUNCATE)
17767 ShAmt0 = ShAmt0.getOperand(0);
17768 if (ShAmt1.getOpcode() == ISD::TRUNCATE)
17769 ShAmt1 = ShAmt1.getOperand(0);
17772 unsigned Opc = X86ISD::SHLD;
17773 SDValue Op0 = N0.getOperand(0);
17774 SDValue Op1 = N1.getOperand(0);
17775 if (ShAmt0.getOpcode() == ISD::SUB) {
17776 Opc = X86ISD::SHRD;
17777 std::swap(Op0, Op1);
17778 std::swap(ShAmt0, ShAmt1);
17781 unsigned Bits = VT.getSizeInBits();
17782 if (ShAmt1.getOpcode() == ISD::SUB) {
17783 SDValue Sum = ShAmt1.getOperand(0);
17784 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) {
17785 SDValue ShAmt1Op1 = ShAmt1.getOperand(1);
17786 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE)
17787 ShAmt1Op1 = ShAmt1Op1.getOperand(0);
17788 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0)
17789 return DAG.getNode(Opc, DL, VT,
17791 DAG.getNode(ISD::TRUNCATE, DL,
17794 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) {
17795 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0);
17797 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits)
17798 return DAG.getNode(Opc, DL, VT,
17799 N0.getOperand(0), N1.getOperand(0),
17800 DAG.getNode(ISD::TRUNCATE, DL,
17807 // Generate NEG and CMOV for integer abs.
17808 static SDValue performIntegerAbsCombine(SDNode *N, SelectionDAG &DAG) {
17809 EVT VT = N->getValueType(0);
17811 // Since X86 does not have CMOV for 8-bit integer, we don't convert
17812 // 8-bit integer abs to NEG and CMOV.
17813 if (VT.isInteger() && VT.getSizeInBits() == 8)
17816 SDValue N0 = N->getOperand(0);
17817 SDValue N1 = N->getOperand(1);
17820 // Check pattern of XOR(ADD(X,Y), Y) where Y is SRA(X, size(X)-1)
17821 // and change it to SUB and CMOV.
17822 if (VT.isInteger() && N->getOpcode() == ISD::XOR &&
17823 N0.getOpcode() == ISD::ADD &&
17824 N0.getOperand(1) == N1 &&
17825 N1.getOpcode() == ISD::SRA &&
17826 N1.getOperand(0) == N0.getOperand(0))
17827 if (ConstantSDNode *Y1C = dyn_cast<ConstantSDNode>(N1.getOperand(1)))
17828 if (Y1C->getAPIntValue() == VT.getSizeInBits()-1) {
17829 // Generate SUB & CMOV.
17830 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, DAG.getVTList(VT, MVT::i32),
17831 DAG.getConstant(0, VT), N0.getOperand(0));
17833 SDValue Ops[] = { N0.getOperand(0), Neg,
17834 DAG.getConstant(X86::COND_GE, MVT::i8),
17835 SDValue(Neg.getNode(), 1) };
17836 return DAG.getNode(X86ISD::CMOV, DL, DAG.getVTList(VT, MVT::Glue),
17837 Ops, array_lengthof(Ops));
17842 // PerformXorCombine - Attempts to turn XOR nodes into BLSMSK nodes
17843 static SDValue PerformXorCombine(SDNode *N, SelectionDAG &DAG,
17844 TargetLowering::DAGCombinerInfo &DCI,
17845 const X86Subtarget *Subtarget) {
17846 EVT VT = N->getValueType(0);
17847 if (DCI.isBeforeLegalizeOps())
17850 if (Subtarget->hasCMov()) {
17851 SDValue RV = performIntegerAbsCombine(N, DAG);
17856 // Try forming BMI if it is available.
17857 if (!Subtarget->hasBMI())
17860 if (VT != MVT::i32 && VT != MVT::i64)
17863 assert(Subtarget->hasBMI() && "Creating BLSMSK requires BMI instructions");
17865 // Create BLSMSK instructions by finding X ^ (X-1)
17866 SDValue N0 = N->getOperand(0);
17867 SDValue N1 = N->getOperand(1);
17870 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1 &&
17871 isAllOnes(N0.getOperand(1)))
17872 return DAG.getNode(X86ISD::BLSMSK, DL, VT, N1);
17874 if (N1.getOpcode() == ISD::ADD && N1.getOperand(0) == N0 &&
17875 isAllOnes(N1.getOperand(1)))
17876 return DAG.getNode(X86ISD::BLSMSK, DL, VT, N0);
17881 /// PerformLOADCombine - Do target-specific dag combines on LOAD nodes.
17882 static SDValue PerformLOADCombine(SDNode *N, SelectionDAG &DAG,
17883 TargetLowering::DAGCombinerInfo &DCI,
17884 const X86Subtarget *Subtarget) {
17885 LoadSDNode *Ld = cast<LoadSDNode>(N);
17886 EVT RegVT = Ld->getValueType(0);
17887 EVT MemVT = Ld->getMemoryVT();
17889 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
17890 unsigned RegSz = RegVT.getSizeInBits();
17892 // On Sandybridge unaligned 256bit loads are inefficient.
17893 ISD::LoadExtType Ext = Ld->getExtensionType();
17894 unsigned Alignment = Ld->getAlignment();
17895 bool IsAligned = Alignment == 0 || Alignment >= MemVT.getSizeInBits()/8;
17896 if (RegVT.is256BitVector() && !Subtarget->hasInt256() &&
17897 !DCI.isBeforeLegalizeOps() && !IsAligned && Ext == ISD::NON_EXTLOAD) {
17898 unsigned NumElems = RegVT.getVectorNumElements();
17902 SDValue Ptr = Ld->getBasePtr();
17903 SDValue Increment = DAG.getConstant(16, TLI.getPointerTy());
17905 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
17907 SDValue Load1 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
17908 Ld->getPointerInfo(), Ld->isVolatile(),
17909 Ld->isNonTemporal(), Ld->isInvariant(),
17911 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
17912 SDValue Load2 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
17913 Ld->getPointerInfo(), Ld->isVolatile(),
17914 Ld->isNonTemporal(), Ld->isInvariant(),
17915 std::min(16U, Alignment));
17916 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
17918 Load2.getValue(1));
17920 SDValue NewVec = DAG.getUNDEF(RegVT);
17921 NewVec = Insert128BitVector(NewVec, Load1, 0, DAG, dl);
17922 NewVec = Insert128BitVector(NewVec, Load2, NumElems/2, DAG, dl);
17923 return DCI.CombineTo(N, NewVec, TF, true);
17926 // If this is a vector EXT Load then attempt to optimize it using a
17927 // shuffle. If SSSE3 is not available we may emit an illegal shuffle but the
17928 // expansion is still better than scalar code.
17929 // We generate X86ISD::VSEXT for SEXTLOADs if it's available, otherwise we'll
17930 // emit a shuffle and a arithmetic shift.
17931 // TODO: It is possible to support ZExt by zeroing the undef values
17932 // during the shuffle phase or after the shuffle.
17933 if (RegVT.isVector() && RegVT.isInteger() && Subtarget->hasSSE2() &&
17934 (Ext == ISD::EXTLOAD || Ext == ISD::SEXTLOAD)) {
17935 assert(MemVT != RegVT && "Cannot extend to the same type");
17936 assert(MemVT.isVector() && "Must load a vector from memory");
17938 unsigned NumElems = RegVT.getVectorNumElements();
17939 unsigned MemSz = MemVT.getSizeInBits();
17940 assert(RegSz > MemSz && "Register size must be greater than the mem size");
17942 if (Ext == ISD::SEXTLOAD && RegSz == 256 && !Subtarget->hasInt256())
17945 // All sizes must be a power of two.
17946 if (!isPowerOf2_32(RegSz * MemSz * NumElems))
17949 // Attempt to load the original value using scalar loads.
17950 // Find the largest scalar type that divides the total loaded size.
17951 MVT SclrLoadTy = MVT::i8;
17952 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
17953 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
17954 MVT Tp = (MVT::SimpleValueType)tp;
17955 if (TLI.isTypeLegal(Tp) && ((MemSz % Tp.getSizeInBits()) == 0)) {
17960 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
17961 if (TLI.isTypeLegal(MVT::f64) && SclrLoadTy.getSizeInBits() < 64 &&
17963 SclrLoadTy = MVT::f64;
17965 // Calculate the number of scalar loads that we need to perform
17966 // in order to load our vector from memory.
17967 unsigned NumLoads = MemSz / SclrLoadTy.getSizeInBits();
17968 if (Ext == ISD::SEXTLOAD && NumLoads > 1)
17971 unsigned loadRegZize = RegSz;
17972 if (Ext == ISD::SEXTLOAD && RegSz == 256)
17975 // Represent our vector as a sequence of elements which are the
17976 // largest scalar that we can load.
17977 EVT LoadUnitVecVT = EVT::getVectorVT(*DAG.getContext(), SclrLoadTy,
17978 loadRegZize/SclrLoadTy.getSizeInBits());
17980 // Represent the data using the same element type that is stored in
17981 // memory. In practice, we ''widen'' MemVT.
17983 EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
17984 loadRegZize/MemVT.getScalarType().getSizeInBits());
17986 assert(WideVecVT.getSizeInBits() == LoadUnitVecVT.getSizeInBits() &&
17987 "Invalid vector type");
17989 // We can't shuffle using an illegal type.
17990 if (!TLI.isTypeLegal(WideVecVT))
17993 SmallVector<SDValue, 8> Chains;
17994 SDValue Ptr = Ld->getBasePtr();
17995 SDValue Increment = DAG.getConstant(SclrLoadTy.getSizeInBits()/8,
17996 TLI.getPointerTy());
17997 SDValue Res = DAG.getUNDEF(LoadUnitVecVT);
17999 for (unsigned i = 0; i < NumLoads; ++i) {
18000 // Perform a single load.
18001 SDValue ScalarLoad = DAG.getLoad(SclrLoadTy, dl, Ld->getChain(),
18002 Ptr, Ld->getPointerInfo(),
18003 Ld->isVolatile(), Ld->isNonTemporal(),
18004 Ld->isInvariant(), Ld->getAlignment());
18005 Chains.push_back(ScalarLoad.getValue(1));
18006 // Create the first element type using SCALAR_TO_VECTOR in order to avoid
18007 // another round of DAGCombining.
18009 Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LoadUnitVecVT, ScalarLoad);
18011 Res = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, LoadUnitVecVT, Res,
18012 ScalarLoad, DAG.getIntPtrConstant(i));
18014 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
18017 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0],
18020 // Bitcast the loaded value to a vector of the original element type, in
18021 // the size of the target vector type.
18022 SDValue SlicedVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, Res);
18023 unsigned SizeRatio = RegSz/MemSz;
18025 if (Ext == ISD::SEXTLOAD) {
18026 // If we have SSE4.1 we can directly emit a VSEXT node.
18027 if (Subtarget->hasSSE41()) {
18028 SDValue Sext = DAG.getNode(X86ISD::VSEXT, dl, RegVT, SlicedVec);
18029 return DCI.CombineTo(N, Sext, TF, true);
18032 // Otherwise we'll shuffle the small elements in the high bits of the
18033 // larger type and perform an arithmetic shift. If the shift is not legal
18034 // it's better to scalarize.
18035 if (!TLI.isOperationLegalOrCustom(ISD::SRA, RegVT))
18038 // Redistribute the loaded elements into the different locations.
18039 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
18040 for (unsigned i = 0; i != NumElems; ++i)
18041 ShuffleVec[i*SizeRatio + SizeRatio-1] = i;
18043 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec,
18044 DAG.getUNDEF(WideVecVT),
18047 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
18049 // Build the arithmetic shift.
18050 unsigned Amt = RegVT.getVectorElementType().getSizeInBits() -
18051 MemVT.getVectorElementType().getSizeInBits();
18052 Shuff = DAG.getNode(ISD::SRA, dl, RegVT, Shuff,
18053 DAG.getConstant(Amt, RegVT));
18055 return DCI.CombineTo(N, Shuff, TF, true);
18058 // Redistribute the loaded elements into the different locations.
18059 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
18060 for (unsigned i = 0; i != NumElems; ++i)
18061 ShuffleVec[i*SizeRatio] = i;
18063 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec,
18064 DAG.getUNDEF(WideVecVT),
18067 // Bitcast to the requested type.
18068 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
18069 // Replace the original load with the new sequence
18070 // and return the new chain.
18071 return DCI.CombineTo(N, Shuff, TF, true);
18077 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
18078 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
18079 const X86Subtarget *Subtarget) {
18080 StoreSDNode *St = cast<StoreSDNode>(N);
18081 EVT VT = St->getValue().getValueType();
18082 EVT StVT = St->getMemoryVT();
18084 SDValue StoredVal = St->getOperand(1);
18085 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
18087 // If we are saving a concatenation of two XMM registers, perform two stores.
18088 // On Sandy Bridge, 256-bit memory operations are executed by two
18089 // 128-bit ports. However, on Haswell it is better to issue a single 256-bit
18090 // memory operation.
18091 unsigned Alignment = St->getAlignment();
18092 bool IsAligned = Alignment == 0 || Alignment >= VT.getSizeInBits()/8;
18093 if (VT.is256BitVector() && !Subtarget->hasInt256() &&
18094 StVT == VT && !IsAligned) {
18095 unsigned NumElems = VT.getVectorNumElements();
18099 SDValue Value0 = Extract128BitVector(StoredVal, 0, DAG, dl);
18100 SDValue Value1 = Extract128BitVector(StoredVal, NumElems/2, DAG, dl);
18102 SDValue Stride = DAG.getConstant(16, TLI.getPointerTy());
18103 SDValue Ptr0 = St->getBasePtr();
18104 SDValue Ptr1 = DAG.getNode(ISD::ADD, dl, Ptr0.getValueType(), Ptr0, Stride);
18106 SDValue Ch0 = DAG.getStore(St->getChain(), dl, Value0, Ptr0,
18107 St->getPointerInfo(), St->isVolatile(),
18108 St->isNonTemporal(), Alignment);
18109 SDValue Ch1 = DAG.getStore(St->getChain(), dl, Value1, Ptr1,
18110 St->getPointerInfo(), St->isVolatile(),
18111 St->isNonTemporal(),
18112 std::min(16U, Alignment));
18113 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ch0, Ch1);
18116 // Optimize trunc store (of multiple scalars) to shuffle and store.
18117 // First, pack all of the elements in one place. Next, store to memory
18118 // in fewer chunks.
18119 if (St->isTruncatingStore() && VT.isVector()) {
18120 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
18121 unsigned NumElems = VT.getVectorNumElements();
18122 assert(StVT != VT && "Cannot truncate to the same type");
18123 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
18124 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
18126 // From, To sizes and ElemCount must be pow of two
18127 if (!isPowerOf2_32(NumElems * FromSz * ToSz)) return SDValue();
18128 // We are going to use the original vector elt for storing.
18129 // Accumulated smaller vector elements must be a multiple of the store size.
18130 if (0 != (NumElems * FromSz) % ToSz) return SDValue();
18132 unsigned SizeRatio = FromSz / ToSz;
18134 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
18136 // Create a type on which we perform the shuffle
18137 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
18138 StVT.getScalarType(), NumElems*SizeRatio);
18140 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
18142 SDValue WideVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, St->getValue());
18143 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
18144 for (unsigned i = 0; i != NumElems; ++i)
18145 ShuffleVec[i] = i * SizeRatio;
18147 // Can't shuffle using an illegal type.
18148 if (!TLI.isTypeLegal(WideVecVT))
18151 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
18152 DAG.getUNDEF(WideVecVT),
18154 // At this point all of the data is stored at the bottom of the
18155 // register. We now need to save it to mem.
18157 // Find the largest store unit
18158 MVT StoreType = MVT::i8;
18159 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
18160 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
18161 MVT Tp = (MVT::SimpleValueType)tp;
18162 if (TLI.isTypeLegal(Tp) && Tp.getSizeInBits() <= NumElems * ToSz)
18166 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
18167 if (TLI.isTypeLegal(MVT::f64) && StoreType.getSizeInBits() < 64 &&
18168 (64 <= NumElems * ToSz))
18169 StoreType = MVT::f64;
18171 // Bitcast the original vector into a vector of store-size units
18172 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(),
18173 StoreType, VT.getSizeInBits()/StoreType.getSizeInBits());
18174 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits());
18175 SDValue ShuffWide = DAG.getNode(ISD::BITCAST, dl, StoreVecVT, Shuff);
18176 SmallVector<SDValue, 8> Chains;
18177 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits()/8,
18178 TLI.getPointerTy());
18179 SDValue Ptr = St->getBasePtr();
18181 // Perform one or more big stores into memory.
18182 for (unsigned i=0, e=(ToSz*NumElems)/StoreType.getSizeInBits(); i!=e; ++i) {
18183 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
18184 StoreType, ShuffWide,
18185 DAG.getIntPtrConstant(i));
18186 SDValue Ch = DAG.getStore(St->getChain(), dl, SubVec, Ptr,
18187 St->getPointerInfo(), St->isVolatile(),
18188 St->isNonTemporal(), St->getAlignment());
18189 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
18190 Chains.push_back(Ch);
18193 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0],
18197 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
18198 // the FP state in cases where an emms may be missing.
18199 // A preferable solution to the general problem is to figure out the right
18200 // places to insert EMMS. This qualifies as a quick hack.
18202 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
18203 if (VT.getSizeInBits() != 64)
18206 const Function *F = DAG.getMachineFunction().getFunction();
18207 bool NoImplicitFloatOps = F->getAttributes().
18208 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoImplicitFloat);
18209 bool F64IsLegal = !DAG.getTarget().Options.UseSoftFloat && !NoImplicitFloatOps
18210 && Subtarget->hasSSE2();
18211 if ((VT.isVector() ||
18212 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
18213 isa<LoadSDNode>(St->getValue()) &&
18214 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
18215 St->getChain().hasOneUse() && !St->isVolatile()) {
18216 SDNode* LdVal = St->getValue().getNode();
18217 LoadSDNode *Ld = 0;
18218 int TokenFactorIndex = -1;
18219 SmallVector<SDValue, 8> Ops;
18220 SDNode* ChainVal = St->getChain().getNode();
18221 // Must be a store of a load. We currently handle two cases: the load
18222 // is a direct child, and it's under an intervening TokenFactor. It is
18223 // possible to dig deeper under nested TokenFactors.
18224 if (ChainVal == LdVal)
18225 Ld = cast<LoadSDNode>(St->getChain());
18226 else if (St->getValue().hasOneUse() &&
18227 ChainVal->getOpcode() == ISD::TokenFactor) {
18228 for (unsigned i = 0, e = ChainVal->getNumOperands(); i != e; ++i) {
18229 if (ChainVal->getOperand(i).getNode() == LdVal) {
18230 TokenFactorIndex = i;
18231 Ld = cast<LoadSDNode>(St->getValue());
18233 Ops.push_back(ChainVal->getOperand(i));
18237 if (!Ld || !ISD::isNormalLoad(Ld))
18240 // If this is not the MMX case, i.e. we are just turning i64 load/store
18241 // into f64 load/store, avoid the transformation if there are multiple
18242 // uses of the loaded value.
18243 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
18248 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
18249 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
18251 if (Subtarget->is64Bit() || F64IsLegal) {
18252 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
18253 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(),
18254 Ld->getPointerInfo(), Ld->isVolatile(),
18255 Ld->isNonTemporal(), Ld->isInvariant(),
18256 Ld->getAlignment());
18257 SDValue NewChain = NewLd.getValue(1);
18258 if (TokenFactorIndex != -1) {
18259 Ops.push_back(NewChain);
18260 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
18263 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
18264 St->getPointerInfo(),
18265 St->isVolatile(), St->isNonTemporal(),
18266 St->getAlignment());
18269 // Otherwise, lower to two pairs of 32-bit loads / stores.
18270 SDValue LoAddr = Ld->getBasePtr();
18271 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
18272 DAG.getConstant(4, MVT::i32));
18274 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
18275 Ld->getPointerInfo(),
18276 Ld->isVolatile(), Ld->isNonTemporal(),
18277 Ld->isInvariant(), Ld->getAlignment());
18278 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
18279 Ld->getPointerInfo().getWithOffset(4),
18280 Ld->isVolatile(), Ld->isNonTemporal(),
18282 MinAlign(Ld->getAlignment(), 4));
18284 SDValue NewChain = LoLd.getValue(1);
18285 if (TokenFactorIndex != -1) {
18286 Ops.push_back(LoLd);
18287 Ops.push_back(HiLd);
18288 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
18292 LoAddr = St->getBasePtr();
18293 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
18294 DAG.getConstant(4, MVT::i32));
18296 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
18297 St->getPointerInfo(),
18298 St->isVolatile(), St->isNonTemporal(),
18299 St->getAlignment());
18300 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
18301 St->getPointerInfo().getWithOffset(4),
18303 St->isNonTemporal(),
18304 MinAlign(St->getAlignment(), 4));
18305 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
18310 /// isHorizontalBinOp - Return 'true' if this vector operation is "horizontal"
18311 /// and return the operands for the horizontal operation in LHS and RHS. A
18312 /// horizontal operation performs the binary operation on successive elements
18313 /// of its first operand, then on successive elements of its second operand,
18314 /// returning the resulting values in a vector. For example, if
18315 /// A = < float a0, float a1, float a2, float a3 >
18317 /// B = < float b0, float b1, float b2, float b3 >
18318 /// then the result of doing a horizontal operation on A and B is
18319 /// A horizontal-op B = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >.
18320 /// In short, LHS and RHS are inspected to see if LHS op RHS is of the form
18321 /// A horizontal-op B, for some already available A and B, and if so then LHS is
18322 /// set to A, RHS to B, and the routine returns 'true'.
18323 /// Note that the binary operation should have the property that if one of the
18324 /// operands is UNDEF then the result is UNDEF.
18325 static bool isHorizontalBinOp(SDValue &LHS, SDValue &RHS, bool IsCommutative) {
18326 // Look for the following pattern: if
18327 // A = < float a0, float a1, float a2, float a3 >
18328 // B = < float b0, float b1, float b2, float b3 >
18330 // LHS = VECTOR_SHUFFLE A, B, <0, 2, 4, 6>
18331 // RHS = VECTOR_SHUFFLE A, B, <1, 3, 5, 7>
18332 // then LHS op RHS = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >
18333 // which is A horizontal-op B.
18335 // At least one of the operands should be a vector shuffle.
18336 if (LHS.getOpcode() != ISD::VECTOR_SHUFFLE &&
18337 RHS.getOpcode() != ISD::VECTOR_SHUFFLE)
18340 MVT VT = LHS.getSimpleValueType();
18342 assert((VT.is128BitVector() || VT.is256BitVector()) &&
18343 "Unsupported vector type for horizontal add/sub");
18345 // Handle 128 and 256-bit vector lengths. AVX defines horizontal add/sub to
18346 // operate independently on 128-bit lanes.
18347 unsigned NumElts = VT.getVectorNumElements();
18348 unsigned NumLanes = VT.getSizeInBits()/128;
18349 unsigned NumLaneElts = NumElts / NumLanes;
18350 assert((NumLaneElts % 2 == 0) &&
18351 "Vector type should have an even number of elements in each lane");
18352 unsigned HalfLaneElts = NumLaneElts/2;
18354 // View LHS in the form
18355 // LHS = VECTOR_SHUFFLE A, B, LMask
18356 // If LHS is not a shuffle then pretend it is the shuffle
18357 // LHS = VECTOR_SHUFFLE LHS, undef, <0, 1, ..., N-1>
18358 // NOTE: in what follows a default initialized SDValue represents an UNDEF of
18361 SmallVector<int, 16> LMask(NumElts);
18362 if (LHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
18363 if (LHS.getOperand(0).getOpcode() != ISD::UNDEF)
18364 A = LHS.getOperand(0);
18365 if (LHS.getOperand(1).getOpcode() != ISD::UNDEF)
18366 B = LHS.getOperand(1);
18367 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(LHS.getNode())->getMask();
18368 std::copy(Mask.begin(), Mask.end(), LMask.begin());
18370 if (LHS.getOpcode() != ISD::UNDEF)
18372 for (unsigned i = 0; i != NumElts; ++i)
18376 // Likewise, view RHS in the form
18377 // RHS = VECTOR_SHUFFLE C, D, RMask
18379 SmallVector<int, 16> RMask(NumElts);
18380 if (RHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
18381 if (RHS.getOperand(0).getOpcode() != ISD::UNDEF)
18382 C = RHS.getOperand(0);
18383 if (RHS.getOperand(1).getOpcode() != ISD::UNDEF)
18384 D = RHS.getOperand(1);
18385 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(RHS.getNode())->getMask();
18386 std::copy(Mask.begin(), Mask.end(), RMask.begin());
18388 if (RHS.getOpcode() != ISD::UNDEF)
18390 for (unsigned i = 0; i != NumElts; ++i)
18394 // Check that the shuffles are both shuffling the same vectors.
18395 if (!(A == C && B == D) && !(A == D && B == C))
18398 // If everything is UNDEF then bail out: it would be better to fold to UNDEF.
18399 if (!A.getNode() && !B.getNode())
18402 // If A and B occur in reverse order in RHS, then "swap" them (which means
18403 // rewriting the mask).
18405 CommuteVectorShuffleMask(RMask, NumElts);
18407 // At this point LHS and RHS are equivalent to
18408 // LHS = VECTOR_SHUFFLE A, B, LMask
18409 // RHS = VECTOR_SHUFFLE A, B, RMask
18410 // Check that the masks correspond to performing a horizontal operation.
18411 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
18412 for (unsigned i = 0; i != NumLaneElts; ++i) {
18413 int LIdx = LMask[i+l], RIdx = RMask[i+l];
18415 // Ignore any UNDEF components.
18416 if (LIdx < 0 || RIdx < 0 ||
18417 (!A.getNode() && (LIdx < (int)NumElts || RIdx < (int)NumElts)) ||
18418 (!B.getNode() && (LIdx >= (int)NumElts || RIdx >= (int)NumElts)))
18421 // Check that successive elements are being operated on. If not, this is
18422 // not a horizontal operation.
18423 unsigned Src = (i/HalfLaneElts); // each lane is split between srcs
18424 int Index = 2*(i%HalfLaneElts) + NumElts*Src + l;
18425 if (!(LIdx == Index && RIdx == Index + 1) &&
18426 !(IsCommutative && LIdx == Index + 1 && RIdx == Index))
18431 LHS = A.getNode() ? A : B; // If A is 'UNDEF', use B for it.
18432 RHS = B.getNode() ? B : A; // If B is 'UNDEF', use A for it.
18436 /// PerformFADDCombine - Do target-specific dag combines on floating point adds.
18437 static SDValue PerformFADDCombine(SDNode *N, SelectionDAG &DAG,
18438 const X86Subtarget *Subtarget) {
18439 EVT VT = N->getValueType(0);
18440 SDValue LHS = N->getOperand(0);
18441 SDValue RHS = N->getOperand(1);
18443 // Try to synthesize horizontal adds from adds of shuffles.
18444 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
18445 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
18446 isHorizontalBinOp(LHS, RHS, true))
18447 return DAG.getNode(X86ISD::FHADD, SDLoc(N), VT, LHS, RHS);
18451 /// PerformFSUBCombine - Do target-specific dag combines on floating point subs.
18452 static SDValue PerformFSUBCombine(SDNode *N, SelectionDAG &DAG,
18453 const X86Subtarget *Subtarget) {
18454 EVT VT = N->getValueType(0);
18455 SDValue LHS = N->getOperand(0);
18456 SDValue RHS = N->getOperand(1);
18458 // Try to synthesize horizontal subs from subs of shuffles.
18459 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
18460 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
18461 isHorizontalBinOp(LHS, RHS, false))
18462 return DAG.getNode(X86ISD::FHSUB, SDLoc(N), VT, LHS, RHS);
18466 /// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and
18467 /// X86ISD::FXOR nodes.
18468 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
18469 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
18470 // F[X]OR(0.0, x) -> x
18471 // F[X]OR(x, 0.0) -> x
18472 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
18473 if (C->getValueAPF().isPosZero())
18474 return N->getOperand(1);
18475 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
18476 if (C->getValueAPF().isPosZero())
18477 return N->getOperand(0);
18481 /// PerformFMinFMaxCombine - Do target-specific dag combines on X86ISD::FMIN and
18482 /// X86ISD::FMAX nodes.
18483 static SDValue PerformFMinFMaxCombine(SDNode *N, SelectionDAG &DAG) {
18484 assert(N->getOpcode() == X86ISD::FMIN || N->getOpcode() == X86ISD::FMAX);
18486 // Only perform optimizations if UnsafeMath is used.
18487 if (!DAG.getTarget().Options.UnsafeFPMath)
18490 // If we run in unsafe-math mode, then convert the FMAX and FMIN nodes
18491 // into FMINC and FMAXC, which are Commutative operations.
18492 unsigned NewOp = 0;
18493 switch (N->getOpcode()) {
18494 default: llvm_unreachable("unknown opcode");
18495 case X86ISD::FMIN: NewOp = X86ISD::FMINC; break;
18496 case X86ISD::FMAX: NewOp = X86ISD::FMAXC; break;
18499 return DAG.getNode(NewOp, SDLoc(N), N->getValueType(0),
18500 N->getOperand(0), N->getOperand(1));
18503 /// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes.
18504 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
18505 // FAND(0.0, x) -> 0.0
18506 // FAND(x, 0.0) -> 0.0
18507 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
18508 if (C->getValueAPF().isPosZero())
18509 return N->getOperand(0);
18510 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
18511 if (C->getValueAPF().isPosZero())
18512 return N->getOperand(1);
18516 /// PerformFANDNCombine - Do target-specific dag combines on X86ISD::FANDN nodes
18517 static SDValue PerformFANDNCombine(SDNode *N, SelectionDAG &DAG) {
18518 // FANDN(x, 0.0) -> 0.0
18519 // FANDN(0.0, x) -> x
18520 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
18521 if (C->getValueAPF().isPosZero())
18522 return N->getOperand(1);
18523 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
18524 if (C->getValueAPF().isPosZero())
18525 return N->getOperand(1);
18529 static SDValue PerformBTCombine(SDNode *N,
18531 TargetLowering::DAGCombinerInfo &DCI) {
18532 // BT ignores high bits in the bit index operand.
18533 SDValue Op1 = N->getOperand(1);
18534 if (Op1.hasOneUse()) {
18535 unsigned BitWidth = Op1.getValueSizeInBits();
18536 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
18537 APInt KnownZero, KnownOne;
18538 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
18539 !DCI.isBeforeLegalizeOps());
18540 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
18541 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
18542 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
18543 DCI.CommitTargetLoweringOpt(TLO);
18548 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
18549 SDValue Op = N->getOperand(0);
18550 if (Op.getOpcode() == ISD::BITCAST)
18551 Op = Op.getOperand(0);
18552 EVT VT = N->getValueType(0), OpVT = Op.getValueType();
18553 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
18554 VT.getVectorElementType().getSizeInBits() ==
18555 OpVT.getVectorElementType().getSizeInBits()) {
18556 return DAG.getNode(ISD::BITCAST, SDLoc(N), VT, Op);
18561 static SDValue PerformSIGN_EXTEND_INREGCombine(SDNode *N, SelectionDAG &DAG,
18562 const X86Subtarget *Subtarget) {
18563 EVT VT = N->getValueType(0);
18564 if (!VT.isVector())
18567 SDValue N0 = N->getOperand(0);
18568 SDValue N1 = N->getOperand(1);
18569 EVT ExtraVT = cast<VTSDNode>(N1)->getVT();
18572 // The SIGN_EXTEND_INREG to v4i64 is expensive operation on the
18573 // both SSE and AVX2 since there is no sign-extended shift right
18574 // operation on a vector with 64-bit elements.
18575 //(sext_in_reg (v4i64 anyext (v4i32 x )), ExtraVT) ->
18576 // (v4i64 sext (v4i32 sext_in_reg (v4i32 x , ExtraVT)))
18577 if (VT == MVT::v4i64 && (N0.getOpcode() == ISD::ANY_EXTEND ||
18578 N0.getOpcode() == ISD::SIGN_EXTEND)) {
18579 SDValue N00 = N0.getOperand(0);
18581 // EXTLOAD has a better solution on AVX2,
18582 // it may be replaced with X86ISD::VSEXT node.
18583 if (N00.getOpcode() == ISD::LOAD && Subtarget->hasInt256())
18584 if (!ISD::isNormalLoad(N00.getNode()))
18587 if (N00.getValueType() == MVT::v4i32 && ExtraVT.getSizeInBits() < 128) {
18588 SDValue Tmp = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v4i32,
18590 return DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i64, Tmp);
18596 static SDValue PerformSExtCombine(SDNode *N, SelectionDAG &DAG,
18597 TargetLowering::DAGCombinerInfo &DCI,
18598 const X86Subtarget *Subtarget) {
18599 if (!DCI.isBeforeLegalizeOps())
18602 if (!Subtarget->hasFp256())
18605 EVT VT = N->getValueType(0);
18606 if (VT.isVector() && VT.getSizeInBits() == 256) {
18607 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget);
18615 static SDValue PerformFMACombine(SDNode *N, SelectionDAG &DAG,
18616 const X86Subtarget* Subtarget) {
18618 EVT VT = N->getValueType(0);
18620 // Let legalize expand this if it isn't a legal type yet.
18621 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
18624 EVT ScalarVT = VT.getScalarType();
18625 if ((ScalarVT != MVT::f32 && ScalarVT != MVT::f64) ||
18626 (!Subtarget->hasFMA() && !Subtarget->hasFMA4()))
18629 SDValue A = N->getOperand(0);
18630 SDValue B = N->getOperand(1);
18631 SDValue C = N->getOperand(2);
18633 bool NegA = (A.getOpcode() == ISD::FNEG);
18634 bool NegB = (B.getOpcode() == ISD::FNEG);
18635 bool NegC = (C.getOpcode() == ISD::FNEG);
18637 // Negative multiplication when NegA xor NegB
18638 bool NegMul = (NegA != NegB);
18640 A = A.getOperand(0);
18642 B = B.getOperand(0);
18644 C = C.getOperand(0);
18648 Opcode = (!NegC) ? X86ISD::FMADD : X86ISD::FMSUB;
18650 Opcode = (!NegC) ? X86ISD::FNMADD : X86ISD::FNMSUB;
18652 return DAG.getNode(Opcode, dl, VT, A, B, C);
18655 static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG,
18656 TargetLowering::DAGCombinerInfo &DCI,
18657 const X86Subtarget *Subtarget) {
18658 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) ->
18659 // (and (i32 x86isd::setcc_carry), 1)
18660 // This eliminates the zext. This transformation is necessary because
18661 // ISD::SETCC is always legalized to i8.
18663 SDValue N0 = N->getOperand(0);
18664 EVT VT = N->getValueType(0);
18666 if (N0.getOpcode() == ISD::AND &&
18668 N0.getOperand(0).hasOneUse()) {
18669 SDValue N00 = N0.getOperand(0);
18670 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
18671 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
18672 if (!C || C->getZExtValue() != 1)
18674 return DAG.getNode(ISD::AND, dl, VT,
18675 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
18676 N00.getOperand(0), N00.getOperand(1)),
18677 DAG.getConstant(1, VT));
18681 if (VT.is256BitVector()) {
18682 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget);
18690 // Optimize x == -y --> x+y == 0
18691 // x != -y --> x+y != 0
18692 static SDValue PerformISDSETCCCombine(SDNode *N, SelectionDAG &DAG) {
18693 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
18694 SDValue LHS = N->getOperand(0);
18695 SDValue RHS = N->getOperand(1);
18697 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && LHS.getOpcode() == ISD::SUB)
18698 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(LHS.getOperand(0)))
18699 if (C->getAPIntValue() == 0 && LHS.hasOneUse()) {
18700 SDValue addV = DAG.getNode(ISD::ADD, SDLoc(N),
18701 LHS.getValueType(), RHS, LHS.getOperand(1));
18702 return DAG.getSetCC(SDLoc(N), N->getValueType(0),
18703 addV, DAG.getConstant(0, addV.getValueType()), CC);
18705 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && RHS.getOpcode() == ISD::SUB)
18706 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS.getOperand(0)))
18707 if (C->getAPIntValue() == 0 && RHS.hasOneUse()) {
18708 SDValue addV = DAG.getNode(ISD::ADD, SDLoc(N),
18709 RHS.getValueType(), LHS, RHS.getOperand(1));
18710 return DAG.getSetCC(SDLoc(N), N->getValueType(0),
18711 addV, DAG.getConstant(0, addV.getValueType()), CC);
18716 // Helper function of PerformSETCCCombine. It is to materialize "setb reg"
18717 // as "sbb reg,reg", since it can be extended without zext and produces
18718 // an all-ones bit which is more useful than 0/1 in some cases.
18719 static SDValue MaterializeSETB(SDLoc DL, SDValue EFLAGS, SelectionDAG &DAG) {
18720 return DAG.getNode(ISD::AND, DL, MVT::i8,
18721 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
18722 DAG.getConstant(X86::COND_B, MVT::i8), EFLAGS),
18723 DAG.getConstant(1, MVT::i8));
18726 // Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT
18727 static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG,
18728 TargetLowering::DAGCombinerInfo &DCI,
18729 const X86Subtarget *Subtarget) {
18731 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(0));
18732 SDValue EFLAGS = N->getOperand(1);
18734 if (CC == X86::COND_A) {
18735 // Try to convert COND_A into COND_B in an attempt to facilitate
18736 // materializing "setb reg".
18738 // Do not flip "e > c", where "c" is a constant, because Cmp instruction
18739 // cannot take an immediate as its first operand.
18741 if (EFLAGS.getOpcode() == X86ISD::SUB && EFLAGS.hasOneUse() &&
18742 EFLAGS.getValueType().isInteger() &&
18743 !isa<ConstantSDNode>(EFLAGS.getOperand(1))) {
18744 SDValue NewSub = DAG.getNode(X86ISD::SUB, SDLoc(EFLAGS),
18745 EFLAGS.getNode()->getVTList(),
18746 EFLAGS.getOperand(1), EFLAGS.getOperand(0));
18747 SDValue NewEFLAGS = SDValue(NewSub.getNode(), EFLAGS.getResNo());
18748 return MaterializeSETB(DL, NewEFLAGS, DAG);
18752 // Materialize "setb reg" as "sbb reg,reg", since it can be extended without
18753 // a zext and produces an all-ones bit which is more useful than 0/1 in some
18755 if (CC == X86::COND_B)
18756 return MaterializeSETB(DL, EFLAGS, DAG);
18760 Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
18761 if (Flags.getNode()) {
18762 SDValue Cond = DAG.getConstant(CC, MVT::i8);
18763 return DAG.getNode(X86ISD::SETCC, DL, N->getVTList(), Cond, Flags);
18769 // Optimize branch condition evaluation.
18771 static SDValue PerformBrCondCombine(SDNode *N, SelectionDAG &DAG,
18772 TargetLowering::DAGCombinerInfo &DCI,
18773 const X86Subtarget *Subtarget) {
18775 SDValue Chain = N->getOperand(0);
18776 SDValue Dest = N->getOperand(1);
18777 SDValue EFLAGS = N->getOperand(3);
18778 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(2));
18782 Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
18783 if (Flags.getNode()) {
18784 SDValue Cond = DAG.getConstant(CC, MVT::i8);
18785 return DAG.getNode(X86ISD::BRCOND, DL, N->getVTList(), Chain, Dest, Cond,
18792 static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
18793 const X86TargetLowering *XTLI) {
18794 SDValue Op0 = N->getOperand(0);
18795 EVT InVT = Op0->getValueType(0);
18797 // SINT_TO_FP(v4i8) -> SINT_TO_FP(SEXT(v4i8 to v4i32))
18798 if (InVT == MVT::v8i8 || InVT == MVT::v4i8) {
18800 MVT DstVT = InVT == MVT::v4i8 ? MVT::v4i32 : MVT::v8i32;
18801 SDValue P = DAG.getNode(ISD::SIGN_EXTEND, dl, DstVT, Op0);
18802 return DAG.getNode(ISD::SINT_TO_FP, dl, N->getValueType(0), P);
18805 // Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have
18806 // a 32-bit target where SSE doesn't support i64->FP operations.
18807 if (Op0.getOpcode() == ISD::LOAD) {
18808 LoadSDNode *Ld = cast<LoadSDNode>(Op0.getNode());
18809 EVT VT = Ld->getValueType(0);
18810 if (!Ld->isVolatile() && !N->getValueType(0).isVector() &&
18811 ISD::isNON_EXTLoad(Op0.getNode()) && Op0.hasOneUse() &&
18812 !XTLI->getSubtarget()->is64Bit() &&
18813 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
18814 SDValue FILDChain = XTLI->BuildFILD(SDValue(N, 0), Ld->getValueType(0),
18815 Ld->getChain(), Op0, DAG);
18816 DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), FILDChain.getValue(1));
18823 // Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS
18824 static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG,
18825 X86TargetLowering::DAGCombinerInfo &DCI) {
18826 // If the LHS and RHS of the ADC node are zero, then it can't overflow and
18827 // the result is either zero or one (depending on the input carry bit).
18828 // Strength reduce this down to a "set on carry" aka SETCC_CARRY&1.
18829 if (X86::isZeroNode(N->getOperand(0)) &&
18830 X86::isZeroNode(N->getOperand(1)) &&
18831 // We don't have a good way to replace an EFLAGS use, so only do this when
18833 SDValue(N, 1).use_empty()) {
18835 EVT VT = N->getValueType(0);
18836 SDValue CarryOut = DAG.getConstant(0, N->getValueType(1));
18837 SDValue Res1 = DAG.getNode(ISD::AND, DL, VT,
18838 DAG.getNode(X86ISD::SETCC_CARRY, DL, VT,
18839 DAG.getConstant(X86::COND_B,MVT::i8),
18841 DAG.getConstant(1, VT));
18842 return DCI.CombineTo(N, Res1, CarryOut);
18848 // fold (add Y, (sete X, 0)) -> adc 0, Y
18849 // (add Y, (setne X, 0)) -> sbb -1, Y
18850 // (sub (sete X, 0), Y) -> sbb 0, Y
18851 // (sub (setne X, 0), Y) -> adc -1, Y
18852 static SDValue OptimizeConditionalInDecrement(SDNode *N, SelectionDAG &DAG) {
18855 // Look through ZExts.
18856 SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0);
18857 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse())
18860 SDValue SetCC = Ext.getOperand(0);
18861 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse())
18864 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0);
18865 if (CC != X86::COND_E && CC != X86::COND_NE)
18868 SDValue Cmp = SetCC.getOperand(1);
18869 if (Cmp.getOpcode() != X86ISD::CMP || !Cmp.hasOneUse() ||
18870 !X86::isZeroNode(Cmp.getOperand(1)) ||
18871 !Cmp.getOperand(0).getValueType().isInteger())
18874 SDValue CmpOp0 = Cmp.getOperand(0);
18875 SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, CmpOp0,
18876 DAG.getConstant(1, CmpOp0.getValueType()));
18878 SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1);
18879 if (CC == X86::COND_NE)
18880 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB,
18881 DL, OtherVal.getValueType(), OtherVal,
18882 DAG.getConstant(-1ULL, OtherVal.getValueType()), NewCmp);
18883 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC,
18884 DL, OtherVal.getValueType(), OtherVal,
18885 DAG.getConstant(0, OtherVal.getValueType()), NewCmp);
18888 /// PerformADDCombine - Do target-specific dag combines on integer adds.
18889 static SDValue PerformAddCombine(SDNode *N, SelectionDAG &DAG,
18890 const X86Subtarget *Subtarget) {
18891 EVT VT = N->getValueType(0);
18892 SDValue Op0 = N->getOperand(0);
18893 SDValue Op1 = N->getOperand(1);
18895 // Try to synthesize horizontal adds from adds of shuffles.
18896 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
18897 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
18898 isHorizontalBinOp(Op0, Op1, true))
18899 return DAG.getNode(X86ISD::HADD, SDLoc(N), VT, Op0, Op1);
18901 return OptimizeConditionalInDecrement(N, DAG);
18904 static SDValue PerformSubCombine(SDNode *N, SelectionDAG &DAG,
18905 const X86Subtarget *Subtarget) {
18906 SDValue Op0 = N->getOperand(0);
18907 SDValue Op1 = N->getOperand(1);
18909 // X86 can't encode an immediate LHS of a sub. See if we can push the
18910 // negation into a preceding instruction.
18911 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op0)) {
18912 // If the RHS of the sub is a XOR with one use and a constant, invert the
18913 // immediate. Then add one to the LHS of the sub so we can turn
18914 // X-Y -> X+~Y+1, saving one register.
18915 if (Op1->hasOneUse() && Op1.getOpcode() == ISD::XOR &&
18916 isa<ConstantSDNode>(Op1.getOperand(1))) {
18917 APInt XorC = cast<ConstantSDNode>(Op1.getOperand(1))->getAPIntValue();
18918 EVT VT = Op0.getValueType();
18919 SDValue NewXor = DAG.getNode(ISD::XOR, SDLoc(Op1), VT,
18921 DAG.getConstant(~XorC, VT));
18922 return DAG.getNode(ISD::ADD, SDLoc(N), VT, NewXor,
18923 DAG.getConstant(C->getAPIntValue()+1, VT));
18927 // Try to synthesize horizontal adds from adds of shuffles.
18928 EVT VT = N->getValueType(0);
18929 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
18930 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
18931 isHorizontalBinOp(Op0, Op1, true))
18932 return DAG.getNode(X86ISD::HSUB, SDLoc(N), VT, Op0, Op1);
18934 return OptimizeConditionalInDecrement(N, DAG);
18937 /// performVZEXTCombine - Performs build vector combines
18938 static SDValue performVZEXTCombine(SDNode *N, SelectionDAG &DAG,
18939 TargetLowering::DAGCombinerInfo &DCI,
18940 const X86Subtarget *Subtarget) {
18941 // (vzext (bitcast (vzext (x)) -> (vzext x)
18942 SDValue In = N->getOperand(0);
18943 while (In.getOpcode() == ISD::BITCAST)
18944 In = In.getOperand(0);
18946 if (In.getOpcode() != X86ISD::VZEXT)
18949 return DAG.getNode(X86ISD::VZEXT, SDLoc(N), N->getValueType(0),
18953 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
18954 DAGCombinerInfo &DCI) const {
18955 SelectionDAG &DAG = DCI.DAG;
18956 switch (N->getOpcode()) {
18958 case ISD::EXTRACT_VECTOR_ELT:
18959 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, DCI);
18961 case ISD::SELECT: return PerformSELECTCombine(N, DAG, DCI, Subtarget);
18962 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI, Subtarget);
18963 case ISD::ADD: return PerformAddCombine(N, DAG, Subtarget);
18964 case ISD::SUB: return PerformSubCombine(N, DAG, Subtarget);
18965 case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI);
18966 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
18969 case ISD::SRL: return PerformShiftCombine(N, DAG, DCI, Subtarget);
18970 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget);
18971 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget);
18972 case ISD::XOR: return PerformXorCombine(N, DAG, DCI, Subtarget);
18973 case ISD::LOAD: return PerformLOADCombine(N, DAG, DCI, Subtarget);
18974 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
18975 case ISD::SINT_TO_FP: return PerformSINT_TO_FPCombine(N, DAG, this);
18976 case ISD::FADD: return PerformFADDCombine(N, DAG, Subtarget);
18977 case ISD::FSUB: return PerformFSUBCombine(N, DAG, Subtarget);
18979 case X86ISD::FOR: return PerformFORCombine(N, DAG);
18981 case X86ISD::FMAX: return PerformFMinFMaxCombine(N, DAG);
18982 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
18983 case X86ISD::FANDN: return PerformFANDNCombine(N, DAG);
18984 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
18985 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
18986 case ISD::ANY_EXTEND:
18987 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG, DCI, Subtarget);
18988 case ISD::SIGN_EXTEND: return PerformSExtCombine(N, DAG, DCI, Subtarget);
18989 case ISD::SIGN_EXTEND_INREG: return PerformSIGN_EXTEND_INREGCombine(N, DAG, Subtarget);
18990 case ISD::TRUNCATE: return PerformTruncateCombine(N, DAG,DCI,Subtarget);
18991 case ISD::SETCC: return PerformISDSETCCCombine(N, DAG);
18992 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG, DCI, Subtarget);
18993 case X86ISD::BRCOND: return PerformBrCondCombine(N, DAG, DCI, Subtarget);
18994 case X86ISD::VZEXT: return performVZEXTCombine(N, DAG, DCI, Subtarget);
18995 case X86ISD::SHUFP: // Handle all target specific shuffles
18996 case X86ISD::PALIGNR:
18997 case X86ISD::UNPCKH:
18998 case X86ISD::UNPCKL:
18999 case X86ISD::MOVHLPS:
19000 case X86ISD::MOVLHPS:
19001 case X86ISD::PSHUFD:
19002 case X86ISD::PSHUFHW:
19003 case X86ISD::PSHUFLW:
19004 case X86ISD::MOVSS:
19005 case X86ISD::MOVSD:
19006 case X86ISD::VPERMILP:
19007 case X86ISD::VPERM2X128:
19008 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget);
19009 case ISD::FMA: return PerformFMACombine(N, DAG, Subtarget);
19015 /// isTypeDesirableForOp - Return true if the target has native support for
19016 /// the specified value type and it is 'desirable' to use the type for the
19017 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
19018 /// instruction encodings are longer and some i16 instructions are slow.
19019 bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const {
19020 if (!isTypeLegal(VT))
19022 if (VT != MVT::i16)
19029 case ISD::SIGN_EXTEND:
19030 case ISD::ZERO_EXTEND:
19031 case ISD::ANY_EXTEND:
19044 /// IsDesirableToPromoteOp - This method query the target whether it is
19045 /// beneficial for dag combiner to promote the specified node. If true, it
19046 /// should return the desired promotion type by reference.
19047 bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
19048 EVT VT = Op.getValueType();
19049 if (VT != MVT::i16)
19052 bool Promote = false;
19053 bool Commute = false;
19054 switch (Op.getOpcode()) {
19057 LoadSDNode *LD = cast<LoadSDNode>(Op);
19058 // If the non-extending load has a single use and it's not live out, then it
19059 // might be folded.
19060 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&&
19061 Op.hasOneUse()*/) {
19062 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
19063 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
19064 // The only case where we'd want to promote LOAD (rather then it being
19065 // promoted as an operand is when it's only use is liveout.
19066 if (UI->getOpcode() != ISD::CopyToReg)
19073 case ISD::SIGN_EXTEND:
19074 case ISD::ZERO_EXTEND:
19075 case ISD::ANY_EXTEND:
19080 SDValue N0 = Op.getOperand(0);
19081 // Look out for (store (shl (load), x)).
19082 if (MayFoldLoad(N0) && MayFoldIntoStore(Op))
19095 SDValue N0 = Op.getOperand(0);
19096 SDValue N1 = Op.getOperand(1);
19097 if (!Commute && MayFoldLoad(N1))
19099 // Avoid disabling potential load folding opportunities.
19100 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op)))
19102 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op)))
19112 //===----------------------------------------------------------------------===//
19113 // X86 Inline Assembly Support
19114 //===----------------------------------------------------------------------===//
19117 // Helper to match a string separated by whitespace.
19118 bool matchAsmImpl(StringRef s, ArrayRef<const StringRef *> args) {
19119 s = s.substr(s.find_first_not_of(" \t")); // Skip leading whitespace.
19121 for (unsigned i = 0, e = args.size(); i != e; ++i) {
19122 StringRef piece(*args[i]);
19123 if (!s.startswith(piece)) // Check if the piece matches.
19126 s = s.substr(piece.size());
19127 StringRef::size_type pos = s.find_first_not_of(" \t");
19128 if (pos == 0) // We matched a prefix.
19136 const VariadicFunction1<bool, StringRef, StringRef, matchAsmImpl> matchAsm={};
19139 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
19140 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
19142 std::string AsmStr = IA->getAsmString();
19144 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
19145 if (!Ty || Ty->getBitWidth() % 16 != 0)
19148 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
19149 SmallVector<StringRef, 4> AsmPieces;
19150 SplitString(AsmStr, AsmPieces, ";\n");
19152 switch (AsmPieces.size()) {
19153 default: return false;
19155 // FIXME: this should verify that we are targeting a 486 or better. If not,
19156 // we will turn this bswap into something that will be lowered to logical
19157 // ops instead of emitting the bswap asm. For now, we don't support 486 or
19158 // lower so don't worry about this.
19160 if (matchAsm(AsmPieces[0], "bswap", "$0") ||
19161 matchAsm(AsmPieces[0], "bswapl", "$0") ||
19162 matchAsm(AsmPieces[0], "bswapq", "$0") ||
19163 matchAsm(AsmPieces[0], "bswap", "${0:q}") ||
19164 matchAsm(AsmPieces[0], "bswapl", "${0:q}") ||
19165 matchAsm(AsmPieces[0], "bswapq", "${0:q}")) {
19166 // No need to check constraints, nothing other than the equivalent of
19167 // "=r,0" would be valid here.
19168 return IntrinsicLowering::LowerToByteSwap(CI);
19171 // rorw $$8, ${0:w} --> llvm.bswap.i16
19172 if (CI->getType()->isIntegerTy(16) &&
19173 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
19174 (matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") ||
19175 matchAsm(AsmPieces[0], "rolw", "$$8,", "${0:w}"))) {
19177 const std::string &ConstraintsStr = IA->getConstraintString();
19178 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
19179 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
19180 if (AsmPieces.size() == 4 &&
19181 AsmPieces[0] == "~{cc}" &&
19182 AsmPieces[1] == "~{dirflag}" &&
19183 AsmPieces[2] == "~{flags}" &&
19184 AsmPieces[3] == "~{fpsr}")
19185 return IntrinsicLowering::LowerToByteSwap(CI);
19189 if (CI->getType()->isIntegerTy(32) &&
19190 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
19191 matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") &&
19192 matchAsm(AsmPieces[1], "rorl", "$$16,", "$0") &&
19193 matchAsm(AsmPieces[2], "rorw", "$$8,", "${0:w}")) {
19195 const std::string &ConstraintsStr = IA->getConstraintString();
19196 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
19197 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
19198 if (AsmPieces.size() == 4 &&
19199 AsmPieces[0] == "~{cc}" &&
19200 AsmPieces[1] == "~{dirflag}" &&
19201 AsmPieces[2] == "~{flags}" &&
19202 AsmPieces[3] == "~{fpsr}")
19203 return IntrinsicLowering::LowerToByteSwap(CI);
19206 if (CI->getType()->isIntegerTy(64)) {
19207 InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints();
19208 if (Constraints.size() >= 2 &&
19209 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
19210 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
19211 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
19212 if (matchAsm(AsmPieces[0], "bswap", "%eax") &&
19213 matchAsm(AsmPieces[1], "bswap", "%edx") &&
19214 matchAsm(AsmPieces[2], "xchgl", "%eax,", "%edx"))
19215 return IntrinsicLowering::LowerToByteSwap(CI);
19223 /// getConstraintType - Given a constraint letter, return the type of
19224 /// constraint it is for this target.
19225 X86TargetLowering::ConstraintType
19226 X86TargetLowering::getConstraintType(const std::string &Constraint) const {
19227 if (Constraint.size() == 1) {
19228 switch (Constraint[0]) {
19239 return C_RegisterClass;
19263 return TargetLowering::getConstraintType(Constraint);
19266 /// Examine constraint type and operand type and determine a weight value.
19267 /// This object must already have been set up with the operand type
19268 /// and the current alternative constraint selected.
19269 TargetLowering::ConstraintWeight
19270 X86TargetLowering::getSingleConstraintMatchWeight(
19271 AsmOperandInfo &info, const char *constraint) const {
19272 ConstraintWeight weight = CW_Invalid;
19273 Value *CallOperandVal = info.CallOperandVal;
19274 // If we don't have a value, we can't do a match,
19275 // but allow it at the lowest weight.
19276 if (CallOperandVal == NULL)
19278 Type *type = CallOperandVal->getType();
19279 // Look at the constraint type.
19280 switch (*constraint) {
19282 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
19293 if (CallOperandVal->getType()->isIntegerTy())
19294 weight = CW_SpecificReg;
19299 if (type->isFloatingPointTy())
19300 weight = CW_SpecificReg;
19303 if (type->isX86_MMXTy() && Subtarget->hasMMX())
19304 weight = CW_SpecificReg;
19308 if (((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasSSE1()) ||
19309 ((type->getPrimitiveSizeInBits() == 256) && Subtarget->hasFp256()))
19310 weight = CW_Register;
19313 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) {
19314 if (C->getZExtValue() <= 31)
19315 weight = CW_Constant;
19319 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
19320 if (C->getZExtValue() <= 63)
19321 weight = CW_Constant;
19325 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
19326 if ((C->getSExtValue() >= -0x80) && (C->getSExtValue() <= 0x7f))
19327 weight = CW_Constant;
19331 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
19332 if ((C->getZExtValue() == 0xff) || (C->getZExtValue() == 0xffff))
19333 weight = CW_Constant;
19337 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
19338 if (C->getZExtValue() <= 3)
19339 weight = CW_Constant;
19343 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
19344 if (C->getZExtValue() <= 0xff)
19345 weight = CW_Constant;
19350 if (dyn_cast<ConstantFP>(CallOperandVal)) {
19351 weight = CW_Constant;
19355 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
19356 if ((C->getSExtValue() >= -0x80000000LL) &&
19357 (C->getSExtValue() <= 0x7fffffffLL))
19358 weight = CW_Constant;
19362 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
19363 if (C->getZExtValue() <= 0xffffffff)
19364 weight = CW_Constant;
19371 /// LowerXConstraint - try to replace an X constraint, which matches anything,
19372 /// with another that has more specific requirements based on the type of the
19373 /// corresponding operand.
19374 const char *X86TargetLowering::
19375 LowerXConstraint(EVT ConstraintVT) const {
19376 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
19377 // 'f' like normal targets.
19378 if (ConstraintVT.isFloatingPoint()) {
19379 if (Subtarget->hasSSE2())
19381 if (Subtarget->hasSSE1())
19385 return TargetLowering::LowerXConstraint(ConstraintVT);
19388 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
19389 /// vector. If it is invalid, don't add anything to Ops.
19390 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
19391 std::string &Constraint,
19392 std::vector<SDValue>&Ops,
19393 SelectionDAG &DAG) const {
19394 SDValue Result(0, 0);
19396 // Only support length 1 constraints for now.
19397 if (Constraint.length() > 1) return;
19399 char ConstraintLetter = Constraint[0];
19400 switch (ConstraintLetter) {
19403 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
19404 if (C->getZExtValue() <= 31) {
19405 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
19411 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
19412 if (C->getZExtValue() <= 63) {
19413 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
19419 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
19420 if (isInt<8>(C->getSExtValue())) {
19421 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
19427 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
19428 if (C->getZExtValue() <= 255) {
19429 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
19435 // 32-bit signed value
19436 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
19437 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
19438 C->getSExtValue())) {
19439 // Widen to 64 bits here to get it sign extended.
19440 Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64);
19443 // FIXME gcc accepts some relocatable values here too, but only in certain
19444 // memory models; it's complicated.
19449 // 32-bit unsigned value
19450 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
19451 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
19452 C->getZExtValue())) {
19453 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
19457 // FIXME gcc accepts some relocatable values here too, but only in certain
19458 // memory models; it's complicated.
19462 // Literal immediates are always ok.
19463 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
19464 // Widen to 64 bits here to get it sign extended.
19465 Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64);
19469 // In any sort of PIC mode addresses need to be computed at runtime by
19470 // adding in a register or some sort of table lookup. These can't
19471 // be used as immediates.
19472 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC())
19475 // If we are in non-pic codegen mode, we allow the address of a global (with
19476 // an optional displacement) to be used with 'i'.
19477 GlobalAddressSDNode *GA = 0;
19478 int64_t Offset = 0;
19480 // Match either (GA), (GA+C), (GA+C1+C2), etc.
19482 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
19483 Offset += GA->getOffset();
19485 } else if (Op.getOpcode() == ISD::ADD) {
19486 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
19487 Offset += C->getZExtValue();
19488 Op = Op.getOperand(0);
19491 } else if (Op.getOpcode() == ISD::SUB) {
19492 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
19493 Offset += -C->getZExtValue();
19494 Op = Op.getOperand(0);
19499 // Otherwise, this isn't something we can handle, reject it.
19503 const GlobalValue *GV = GA->getGlobal();
19504 // If we require an extra load to get this address, as in PIC mode, we
19505 // can't accept it.
19506 if (isGlobalStubReference(Subtarget->ClassifyGlobalReference(GV,
19507 getTargetMachine())))
19510 Result = DAG.getTargetGlobalAddress(GV, SDLoc(Op),
19511 GA->getValueType(0), Offset);
19516 if (Result.getNode()) {
19517 Ops.push_back(Result);
19520 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
19523 std::pair<unsigned, const TargetRegisterClass*>
19524 X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
19526 // First, see if this is a constraint that directly corresponds to an LLVM
19528 if (Constraint.size() == 1) {
19529 // GCC Constraint Letters
19530 switch (Constraint[0]) {
19532 // TODO: Slight differences here in allocation order and leaving
19533 // RIP in the class. Do they matter any more here than they do
19534 // in the normal allocation?
19535 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
19536 if (Subtarget->is64Bit()) {
19537 if (VT == MVT::i32 || VT == MVT::f32)
19538 return std::make_pair(0U, &X86::GR32RegClass);
19539 if (VT == MVT::i16)
19540 return std::make_pair(0U, &X86::GR16RegClass);
19541 if (VT == MVT::i8 || VT == MVT::i1)
19542 return std::make_pair(0U, &X86::GR8RegClass);
19543 if (VT == MVT::i64 || VT == MVT::f64)
19544 return std::make_pair(0U, &X86::GR64RegClass);
19547 // 32-bit fallthrough
19548 case 'Q': // Q_REGS
19549 if (VT == MVT::i32 || VT == MVT::f32)
19550 return std::make_pair(0U, &X86::GR32_ABCDRegClass);
19551 if (VT == MVT::i16)
19552 return std::make_pair(0U, &X86::GR16_ABCDRegClass);
19553 if (VT == MVT::i8 || VT == MVT::i1)
19554 return std::make_pair(0U, &X86::GR8_ABCD_LRegClass);
19555 if (VT == MVT::i64)
19556 return std::make_pair(0U, &X86::GR64_ABCDRegClass);
19558 case 'r': // GENERAL_REGS
19559 case 'l': // INDEX_REGS
19560 if (VT == MVT::i8 || VT == MVT::i1)
19561 return std::make_pair(0U, &X86::GR8RegClass);
19562 if (VT == MVT::i16)
19563 return std::make_pair(0U, &X86::GR16RegClass);
19564 if (VT == MVT::i32 || VT == MVT::f32 || !Subtarget->is64Bit())
19565 return std::make_pair(0U, &X86::GR32RegClass);
19566 return std::make_pair(0U, &X86::GR64RegClass);
19567 case 'R': // LEGACY_REGS
19568 if (VT == MVT::i8 || VT == MVT::i1)
19569 return std::make_pair(0U, &X86::GR8_NOREXRegClass);
19570 if (VT == MVT::i16)
19571 return std::make_pair(0U, &X86::GR16_NOREXRegClass);
19572 if (VT == MVT::i32 || !Subtarget->is64Bit())
19573 return std::make_pair(0U, &X86::GR32_NOREXRegClass);
19574 return std::make_pair(0U, &X86::GR64_NOREXRegClass);
19575 case 'f': // FP Stack registers.
19576 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
19577 // value to the correct fpstack register class.
19578 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
19579 return std::make_pair(0U, &X86::RFP32RegClass);
19580 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
19581 return std::make_pair(0U, &X86::RFP64RegClass);
19582 return std::make_pair(0U, &X86::RFP80RegClass);
19583 case 'y': // MMX_REGS if MMX allowed.
19584 if (!Subtarget->hasMMX()) break;
19585 return std::make_pair(0U, &X86::VR64RegClass);
19586 case 'Y': // SSE_REGS if SSE2 allowed
19587 if (!Subtarget->hasSSE2()) break;
19589 case 'x': // SSE_REGS if SSE1 allowed or AVX_REGS if AVX allowed
19590 if (!Subtarget->hasSSE1()) break;
19592 switch (VT.SimpleTy) {
19594 // Scalar SSE types.
19597 return std::make_pair(0U, &X86::FR32RegClass);
19600 return std::make_pair(0U, &X86::FR64RegClass);
19608 return std::make_pair(0U, &X86::VR128RegClass);
19616 return std::make_pair(0U, &X86::VR256RegClass);
19621 return std::make_pair(0U, &X86::VR512RegClass);
19627 // Use the default implementation in TargetLowering to convert the register
19628 // constraint into a member of a register class.
19629 std::pair<unsigned, const TargetRegisterClass*> Res;
19630 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
19632 // Not found as a standard register?
19633 if (Res.second == 0) {
19634 // Map st(0) -> st(7) -> ST0
19635 if (Constraint.size() == 7 && Constraint[0] == '{' &&
19636 tolower(Constraint[1]) == 's' &&
19637 tolower(Constraint[2]) == 't' &&
19638 Constraint[3] == '(' &&
19639 (Constraint[4] >= '0' && Constraint[4] <= '7') &&
19640 Constraint[5] == ')' &&
19641 Constraint[6] == '}') {
19643 Res.first = X86::ST0+Constraint[4]-'0';
19644 Res.second = &X86::RFP80RegClass;
19648 // GCC allows "st(0)" to be called just plain "st".
19649 if (StringRef("{st}").equals_lower(Constraint)) {
19650 Res.first = X86::ST0;
19651 Res.second = &X86::RFP80RegClass;
19656 if (StringRef("{flags}").equals_lower(Constraint)) {
19657 Res.first = X86::EFLAGS;
19658 Res.second = &X86::CCRRegClass;
19662 // 'A' means EAX + EDX.
19663 if (Constraint == "A") {
19664 Res.first = X86::EAX;
19665 Res.second = &X86::GR32_ADRegClass;
19671 // Otherwise, check to see if this is a register class of the wrong value
19672 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
19673 // turn into {ax},{dx}.
19674 if (Res.second->hasType(VT))
19675 return Res; // Correct type already, nothing to do.
19677 // All of the single-register GCC register classes map their values onto
19678 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
19679 // really want an 8-bit or 32-bit register, map to the appropriate register
19680 // class and return the appropriate register.
19681 if (Res.second == &X86::GR16RegClass) {
19682 if (VT == MVT::i8 || VT == MVT::i1) {
19683 unsigned DestReg = 0;
19684 switch (Res.first) {
19686 case X86::AX: DestReg = X86::AL; break;
19687 case X86::DX: DestReg = X86::DL; break;
19688 case X86::CX: DestReg = X86::CL; break;
19689 case X86::BX: DestReg = X86::BL; break;
19692 Res.first = DestReg;
19693 Res.second = &X86::GR8RegClass;
19695 } else if (VT == MVT::i32 || VT == MVT::f32) {
19696 unsigned DestReg = 0;
19697 switch (Res.first) {
19699 case X86::AX: DestReg = X86::EAX; break;
19700 case X86::DX: DestReg = X86::EDX; break;
19701 case X86::CX: DestReg = X86::ECX; break;
19702 case X86::BX: DestReg = X86::EBX; break;
19703 case X86::SI: DestReg = X86::ESI; break;
19704 case X86::DI: DestReg = X86::EDI; break;
19705 case X86::BP: DestReg = X86::EBP; break;
19706 case X86::SP: DestReg = X86::ESP; break;
19709 Res.first = DestReg;
19710 Res.second = &X86::GR32RegClass;
19712 } else if (VT == MVT::i64 || VT == MVT::f64) {
19713 unsigned DestReg = 0;
19714 switch (Res.first) {
19716 case X86::AX: DestReg = X86::RAX; break;
19717 case X86::DX: DestReg = X86::RDX; break;
19718 case X86::CX: DestReg = X86::RCX; break;
19719 case X86::BX: DestReg = X86::RBX; break;
19720 case X86::SI: DestReg = X86::RSI; break;
19721 case X86::DI: DestReg = X86::RDI; break;
19722 case X86::BP: DestReg = X86::RBP; break;
19723 case X86::SP: DestReg = X86::RSP; break;
19726 Res.first = DestReg;
19727 Res.second = &X86::GR64RegClass;
19730 } else if (Res.second == &X86::FR32RegClass ||
19731 Res.second == &X86::FR64RegClass ||
19732 Res.second == &X86::VR128RegClass ||
19733 Res.second == &X86::VR256RegClass ||
19734 Res.second == &X86::FR32XRegClass ||
19735 Res.second == &X86::FR64XRegClass ||
19736 Res.second == &X86::VR128XRegClass ||
19737 Res.second == &X86::VR256XRegClass ||
19738 Res.second == &X86::VR512RegClass) {
19739 // Handle references to XMM physical registers that got mapped into the
19740 // wrong class. This can happen with constraints like {xmm0} where the
19741 // target independent register mapper will just pick the first match it can
19742 // find, ignoring the required type.
19744 if (VT == MVT::f32 || VT == MVT::i32)
19745 Res.second = &X86::FR32RegClass;
19746 else if (VT == MVT::f64 || VT == MVT::i64)
19747 Res.second = &X86::FR64RegClass;
19748 else if (X86::VR128RegClass.hasType(VT))
19749 Res.second = &X86::VR128RegClass;
19750 else if (X86::VR256RegClass.hasType(VT))
19751 Res.second = &X86::VR256RegClass;
19752 else if (X86::VR512RegClass.hasType(VT))
19753 Res.second = &X86::VR512RegClass;