1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Chris Lattner and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
16 #include "X86InstrBuilder.h"
17 #include "X86ISelLowering.h"
18 #include "X86MachineFunctionInfo.h"
19 #include "X86TargetMachine.h"
20 #include "llvm/CallingConv.h"
21 #include "llvm/Constants.h"
22 #include "llvm/DerivedTypes.h"
23 #include "llvm/Function.h"
24 #include "llvm/Intrinsics.h"
25 #include "llvm/ADT/VectorExtras.h"
26 #include "llvm/Analysis/ScalarEvolutionExpressions.h"
27 #include "llvm/CodeGen/MachineFrameInfo.h"
28 #include "llvm/CodeGen/MachineFunction.h"
29 #include "llvm/CodeGen/MachineInstrBuilder.h"
30 #include "llvm/CodeGen/SelectionDAG.h"
31 #include "llvm/CodeGen/SSARegMap.h"
32 #include "llvm/Support/MathExtras.h"
33 #include "llvm/Target/TargetOptions.h"
34 #include "llvm/Support/CommandLine.h"
35 #include "llvm/ADT/StringExtras.h"
39 static cl::opt<bool> EnableFastCC("enable-x86-fastcc", cl::Hidden,
40 cl::desc("Enable fastcc on X86"));
41 X86TargetLowering::X86TargetLowering(TargetMachine &TM)
42 : TargetLowering(TM) {
43 Subtarget = &TM.getSubtarget<X86Subtarget>();
44 X86ScalarSSE = Subtarget->hasSSE2();
45 X86StackPtr = Subtarget->is64Bit() ? X86::RSP : X86::ESP;
47 // Set up the TargetLowering object.
49 // X86 is weird, it always uses i8 for shift amounts and setcc results.
50 setShiftAmountType(MVT::i8);
51 setSetCCResultType(MVT::i8);
52 setSetCCResultContents(ZeroOrOneSetCCResult);
53 setSchedulingPreference(SchedulingForRegPressure);
54 setShiftAmountFlavor(Mask); // shl X, 32 == shl X, 0
55 setStackPointerRegisterToSaveRestore(X86StackPtr);
57 if (!Subtarget->isTargetDarwin())
58 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
59 setUseUnderscoreSetJmpLongJmp(true);
61 // Add legal addressing mode scale values.
62 addLegalAddressScale(8);
63 addLegalAddressScale(4);
64 addLegalAddressScale(2);
65 // Enter the ones which require both scale + index last. These are more
67 addLegalAddressScale(9);
68 addLegalAddressScale(5);
69 addLegalAddressScale(3);
71 // Set up the register classes.
72 addRegisterClass(MVT::i8, X86::GR8RegisterClass);
73 addRegisterClass(MVT::i16, X86::GR16RegisterClass);
74 addRegisterClass(MVT::i32, X86::GR32RegisterClass);
75 if (Subtarget->is64Bit())
76 addRegisterClass(MVT::i64, X86::GR64RegisterClass);
78 setLoadXAction(ISD::SEXTLOAD, MVT::i1, Expand);
80 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
82 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
83 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
84 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
86 if (Subtarget->is64Bit()) {
87 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Expand);
88 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
91 // If SSE i64 SINT_TO_FP is not available, expand i32 UINT_TO_FP.
92 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Expand);
94 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
97 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
99 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
100 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
101 // SSE has no i16 to fp conversion, only i32
103 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
105 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
106 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
109 if (!Subtarget->is64Bit()) {
110 // Custom lower SINT_TO_FP and FP_TO_SINT from/to i64 in 32-bit mode.
111 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
112 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
115 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
117 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
118 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
121 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
123 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
124 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
127 // Handle FP_TO_UINT by promoting the destination to a larger signed
129 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
130 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
131 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
133 if (Subtarget->is64Bit()) {
134 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
135 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
137 if (X86ScalarSSE && !Subtarget->hasSSE3())
138 // Expand FP_TO_UINT into a select.
139 // FIXME: We would like to use a Custom expander here eventually to do
140 // the optimal thing for SSE vs. the default expansion in the legalizer.
141 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
143 // With SSE3 we can use fisttpll to convert to a signed i64.
144 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
147 setOperationAction(ISD::BIT_CONVERT , MVT::f32 , Expand);
148 setOperationAction(ISD::BIT_CONVERT , MVT::i32 , Expand);
150 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
151 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
152 setOperationAction(ISD::BR_CC , MVT::Other, Expand);
153 setOperationAction(ISD::SELECT_CC , MVT::Other, Expand);
154 setOperationAction(ISD::MEMMOVE , MVT::Other, Expand);
155 if (Subtarget->is64Bit())
156 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Expand);
157 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Expand);
158 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Expand);
159 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
160 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
161 setOperationAction(ISD::FREM , MVT::f64 , Expand);
163 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
164 setOperationAction(ISD::CTTZ , MVT::i8 , Expand);
165 setOperationAction(ISD::CTLZ , MVT::i8 , Expand);
166 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
167 setOperationAction(ISD::CTTZ , MVT::i16 , Expand);
168 setOperationAction(ISD::CTLZ , MVT::i16 , Expand);
169 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
170 setOperationAction(ISD::CTTZ , MVT::i32 , Expand);
171 setOperationAction(ISD::CTLZ , MVT::i32 , Expand);
172 if (Subtarget->is64Bit()) {
173 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
174 setOperationAction(ISD::CTTZ , MVT::i64 , Expand);
175 setOperationAction(ISD::CTLZ , MVT::i64 , Expand);
178 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
179 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
181 // These should be promoted to a larger select which is supported.
182 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
183 setOperationAction(ISD::SELECT , MVT::i8 , Promote);
184 // X86 wants to expand cmov itself.
185 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
186 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
187 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
188 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
189 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
190 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
191 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
192 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
193 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
194 if (Subtarget->is64Bit()) {
195 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
196 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
198 // X86 ret instruction may pop stack.
199 setOperationAction(ISD::RET , MVT::Other, Custom);
201 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
202 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
203 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
204 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
205 if (Subtarget->is64Bit()) {
206 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
207 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
208 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
209 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
211 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
212 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
213 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
214 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
215 // X86 wants to expand memset / memcpy itself.
216 setOperationAction(ISD::MEMSET , MVT::Other, Custom);
217 setOperationAction(ISD::MEMCPY , MVT::Other, Custom);
219 // We don't have line number support yet.
220 setOperationAction(ISD::LOCATION, MVT::Other, Expand);
221 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
222 // FIXME - use subtarget debug flags
223 if (!Subtarget->isTargetDarwin() &&
224 !Subtarget->isTargetELF() &&
225 !Subtarget->isTargetCygwin())
226 setOperationAction(ISD::DEBUG_LABEL, MVT::Other, Expand);
228 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
229 setOperationAction(ISD::VASTART , MVT::Other, Custom);
231 // Use the default implementation.
232 setOperationAction(ISD::VAARG , MVT::Other, Expand);
233 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
234 setOperationAction(ISD::VAEND , MVT::Other, Expand);
235 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
236 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
237 if (Subtarget->is64Bit())
238 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand);
239 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Expand);
241 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
242 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
245 // Set up the FP register classes.
246 addRegisterClass(MVT::f32, X86::FR32RegisterClass);
247 addRegisterClass(MVT::f64, X86::FR64RegisterClass);
249 // Use ANDPD to simulate FABS.
250 setOperationAction(ISD::FABS , MVT::f64, Custom);
251 setOperationAction(ISD::FABS , MVT::f32, Custom);
253 // Use XORP to simulate FNEG.
254 setOperationAction(ISD::FNEG , MVT::f64, Custom);
255 setOperationAction(ISD::FNEG , MVT::f32, Custom);
257 // We don't support sin/cos/fmod
258 setOperationAction(ISD::FSIN , MVT::f64, Expand);
259 setOperationAction(ISD::FCOS , MVT::f64, Expand);
260 setOperationAction(ISD::FREM , MVT::f64, Expand);
261 setOperationAction(ISD::FSIN , MVT::f32, Expand);
262 setOperationAction(ISD::FCOS , MVT::f32, Expand);
263 setOperationAction(ISD::FREM , MVT::f32, Expand);
265 // Expand FP immediates into loads from the stack, except for the special
267 setOperationAction(ISD::ConstantFP, MVT::f64, Expand);
268 setOperationAction(ISD::ConstantFP, MVT::f32, Expand);
269 addLegalFPImmediate(+0.0); // xorps / xorpd
271 // Set up the FP register classes.
272 addRegisterClass(MVT::f64, X86::RFPRegisterClass);
274 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
277 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
278 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
281 setOperationAction(ISD::ConstantFP, MVT::f64, Expand);
282 addLegalFPImmediate(+0.0); // FLD0
283 addLegalFPImmediate(+1.0); // FLD1
284 addLegalFPImmediate(-0.0); // FLD0/FCHS
285 addLegalFPImmediate(-1.0); // FLD1/FCHS
288 // First set operation action for all vector types to expand. Then we
289 // will selectively turn on ones that can be effectively codegen'd.
290 for (unsigned VT = (unsigned)MVT::Vector + 1;
291 VT != (unsigned)MVT::LAST_VALUETYPE; VT++) {
292 setOperationAction(ISD::ADD , (MVT::ValueType)VT, Expand);
293 setOperationAction(ISD::SUB , (MVT::ValueType)VT, Expand);
294 setOperationAction(ISD::FADD, (MVT::ValueType)VT, Expand);
295 setOperationAction(ISD::FSUB, (MVT::ValueType)VT, Expand);
296 setOperationAction(ISD::MUL , (MVT::ValueType)VT, Expand);
297 setOperationAction(ISD::FMUL, (MVT::ValueType)VT, Expand);
298 setOperationAction(ISD::SDIV, (MVT::ValueType)VT, Expand);
299 setOperationAction(ISD::UDIV, (MVT::ValueType)VT, Expand);
300 setOperationAction(ISD::FDIV, (MVT::ValueType)VT, Expand);
301 setOperationAction(ISD::SREM, (MVT::ValueType)VT, Expand);
302 setOperationAction(ISD::UREM, (MVT::ValueType)VT, Expand);
303 setOperationAction(ISD::LOAD, (MVT::ValueType)VT, Expand);
304 setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::ValueType)VT, Expand);
305 setOperationAction(ISD::EXTRACT_VECTOR_ELT, (MVT::ValueType)VT, Expand);
306 setOperationAction(ISD::INSERT_VECTOR_ELT, (MVT::ValueType)VT, Expand);
309 if (Subtarget->hasMMX()) {
310 addRegisterClass(MVT::v8i8, X86::VR64RegisterClass);
311 addRegisterClass(MVT::v4i16, X86::VR64RegisterClass);
312 addRegisterClass(MVT::v2i32, X86::VR64RegisterClass);
314 // FIXME: add MMX packed arithmetics
315 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i8, Expand);
316 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i16, Expand);
317 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i32, Expand);
320 if (Subtarget->hasSSE1()) {
321 addRegisterClass(MVT::v4f32, X86::VR128RegisterClass);
323 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
324 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
325 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
326 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
327 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
328 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
329 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
330 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
331 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
334 if (Subtarget->hasSSE2()) {
335 addRegisterClass(MVT::v2f64, X86::VR128RegisterClass);
336 addRegisterClass(MVT::v16i8, X86::VR128RegisterClass);
337 addRegisterClass(MVT::v8i16, X86::VR128RegisterClass);
338 addRegisterClass(MVT::v4i32, X86::VR128RegisterClass);
339 addRegisterClass(MVT::v2i64, X86::VR128RegisterClass);
341 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
342 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
343 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
344 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
345 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
346 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
347 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
348 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
349 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
350 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
351 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
353 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
354 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
355 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
356 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
357 // Implement v4f32 insert_vector_elt in terms of SSE2 v8i16 ones.
358 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
360 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
361 for (unsigned VT = (unsigned)MVT::v16i8; VT != (unsigned)MVT::v2i64; VT++) {
362 setOperationAction(ISD::BUILD_VECTOR, (MVT::ValueType)VT, Custom);
363 setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::ValueType)VT, Custom);
364 setOperationAction(ISD::EXTRACT_VECTOR_ELT, (MVT::ValueType)VT, Custom);
366 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
367 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
368 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
369 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
370 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
371 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
373 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
374 for (unsigned VT = (unsigned)MVT::v16i8; VT != (unsigned)MVT::v2i64; VT++) {
375 setOperationAction(ISD::AND, (MVT::ValueType)VT, Promote);
376 AddPromotedToType (ISD::AND, (MVT::ValueType)VT, MVT::v2i64);
377 setOperationAction(ISD::OR, (MVT::ValueType)VT, Promote);
378 AddPromotedToType (ISD::OR, (MVT::ValueType)VT, MVT::v2i64);
379 setOperationAction(ISD::XOR, (MVT::ValueType)VT, Promote);
380 AddPromotedToType (ISD::XOR, (MVT::ValueType)VT, MVT::v2i64);
381 setOperationAction(ISD::LOAD, (MVT::ValueType)VT, Promote);
382 AddPromotedToType (ISD::LOAD, (MVT::ValueType)VT, MVT::v2i64);
383 setOperationAction(ISD::SELECT, (MVT::ValueType)VT, Promote);
384 AddPromotedToType (ISD::SELECT, (MVT::ValueType)VT, MVT::v2i64);
387 // Custom lower v2i64 and v2f64 selects.
388 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
389 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
390 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
391 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
394 // We want to custom lower some of our intrinsics.
395 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
397 // We have target-specific dag combine patterns for the following nodes:
398 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
399 setTargetDAGCombine(ISD::SELECT);
401 computeRegisterProperties();
403 // FIXME: These should be based on subtarget info. Plus, the values should
404 // be smaller when we are in optimizing for size mode.
405 maxStoresPerMemset = 16; // For %llvm.memset -> sequence of stores
406 maxStoresPerMemcpy = 16; // For %llvm.memcpy -> sequence of stores
407 maxStoresPerMemmove = 16; // For %llvm.memmove -> sequence of stores
408 allowUnalignedMemoryAccesses = true; // x86 supports it!
411 //===----------------------------------------------------------------------===//
412 // C Calling Convention implementation
413 //===----------------------------------------------------------------------===//
415 /// AddLiveIn - This helper function adds the specified physical register to the
416 /// MachineFunction as a live in value. It also creates a corresponding virtual
418 static unsigned AddLiveIn(MachineFunction &MF, unsigned PReg,
419 TargetRegisterClass *RC) {
420 assert(RC->contains(PReg) && "Not the correct regclass!");
421 unsigned VReg = MF.getSSARegMap()->createVirtualRegister(RC);
422 MF.addLiveIn(PReg, VReg);
426 /// HowToPassCCCArgument - Returns how an formal argument of the specified type
427 /// should be passed. If it is through stack, returns the size of the stack
428 /// slot; if it is through XMM register, returns the number of XMM registers
431 HowToPassCCCArgument(MVT::ValueType ObjectVT, unsigned NumXMMRegs,
432 unsigned &ObjSize, unsigned &ObjXMMRegs) {
436 default: assert(0 && "Unhandled argument type!");
437 case MVT::i8: ObjSize = 1; break;
438 case MVT::i16: ObjSize = 2; break;
439 case MVT::i32: ObjSize = 4; break;
440 case MVT::i64: ObjSize = 8; break;
441 case MVT::f32: ObjSize = 4; break;
442 case MVT::f64: ObjSize = 8; break;
457 SDOperand X86TargetLowering::LowerCCCArguments(SDOperand Op, SelectionDAG &DAG) {
458 unsigned NumArgs = Op.Val->getNumValues() - 1;
459 MachineFunction &MF = DAG.getMachineFunction();
460 MachineFrameInfo *MFI = MF.getFrameInfo();
461 SDOperand Root = Op.getOperand(0);
462 std::vector<SDOperand> ArgValues;
464 // Add DAG nodes to load the arguments... On entry to a function on the X86,
465 // the stack frame looks like this:
467 // [ESP] -- return address
468 // [ESP + 4] -- first argument (leftmost lexically)
469 // [ESP + 8] -- second argument, if first argument is <= 4 bytes in size
472 unsigned ArgOffset = 0; // Frame mechanisms handle retaddr slot
473 unsigned NumXMMRegs = 0; // XMM regs used for parameter passing.
474 static const unsigned XMMArgRegs[] = {
475 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
477 for (unsigned i = 0; i < NumArgs; ++i) {
478 MVT::ValueType ObjectVT = Op.getValue(i).getValueType();
479 unsigned ArgIncrement = 4;
480 unsigned ObjSize = 0;
481 unsigned ObjXMMRegs = 0;
482 HowToPassCCCArgument(ObjectVT, NumXMMRegs, ObjSize, ObjXMMRegs);
484 ArgIncrement = ObjSize;
488 // Passed in a XMM register.
489 unsigned Reg = AddLiveIn(MF, XMMArgRegs[NumXMMRegs],
490 X86::VR128RegisterClass);
491 ArgValue= DAG.getCopyFromReg(Root, Reg, ObjectVT);
492 ArgValues.push_back(ArgValue);
493 NumXMMRegs += ObjXMMRegs;
495 // XMM arguments have to be aligned on 16-byte boundary.
497 ArgOffset = ((ArgOffset + 15) / 16) * 16;
498 // Create the frame index object for this incoming parameter...
499 int FI = MFI->CreateFixedObject(ObjSize, ArgOffset);
500 SDOperand FIN = DAG.getFrameIndex(FI, getPointerTy());
501 ArgValue = DAG.getLoad(Op.Val->getValueType(i), Root, FIN, NULL, 0);
502 ArgValues.push_back(ArgValue);
503 ArgOffset += ArgIncrement; // Move on to the next argument...
507 ArgValues.push_back(Root);
509 // If the function takes variable number of arguments, make a frame index for
510 // the start of the first vararg value... for expansion of llvm.va_start.
511 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
513 VarArgsFrameIndex = MFI->CreateFixedObject(1, ArgOffset);
514 RegSaveFrameIndex = 0xAAAAAAA; // X86-64 only.
515 ReturnAddrIndex = 0; // No return address slot generated yet.
516 BytesToPopOnReturn = 0; // Callee pops nothing.
517 BytesCallerReserves = ArgOffset;
519 // If this is a struct return on Darwin/X86, the callee pops the hidden struct
521 if (MF.getFunction()->getCallingConv() == CallingConv::CSRet &&
522 Subtarget->isTargetDarwin())
523 BytesToPopOnReturn = 4;
525 // Return the new list of results.
526 std::vector<MVT::ValueType> RetVTs(Op.Val->value_begin(),
527 Op.Val->value_end());
528 return DAG.getNode(ISD::MERGE_VALUES, RetVTs, &ArgValues[0],ArgValues.size());
532 SDOperand X86TargetLowering::LowerCCCCallTo(SDOperand Op, SelectionDAG &DAG) {
533 SDOperand Chain = Op.getOperand(0);
534 unsigned CallingConv= cast<ConstantSDNode>(Op.getOperand(1))->getValue();
535 bool isTailCall = cast<ConstantSDNode>(Op.getOperand(3))->getValue() != 0;
536 SDOperand Callee = Op.getOperand(4);
537 MVT::ValueType RetVT= Op.Val->getValueType(0);
538 unsigned NumOps = (Op.getNumOperands() - 5) / 2;
540 // Keep track of the number of XMM regs passed so far.
541 unsigned NumXMMRegs = 0;
542 static const unsigned XMMArgRegs[] = {
543 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
546 // Count how many bytes are to be pushed on the stack.
547 unsigned NumBytes = 0;
548 for (unsigned i = 0; i != NumOps; ++i) {
549 SDOperand Arg = Op.getOperand(5+2*i);
551 switch (Arg.getValueType()) {
552 default: assert(0 && "Unexpected ValueType for argument!");
572 // XMM arguments have to be aligned on 16-byte boundary.
573 NumBytes = ((NumBytes + 15) / 16) * 16;
580 Chain = DAG.getCALLSEQ_START(Chain,DAG.getConstant(NumBytes, getPointerTy()));
582 // Arguments go on the stack in reverse order, as specified by the ABI.
583 unsigned ArgOffset = 0;
585 std::vector<std::pair<unsigned, SDOperand> > RegsToPass;
586 std::vector<SDOperand> MemOpChains;
587 SDOperand StackPtr = DAG.getRegister(X86StackPtr, getPointerTy());
588 for (unsigned i = 0; i != NumOps; ++i) {
589 SDOperand Arg = Op.getOperand(5+2*i);
591 switch (Arg.getValueType()) {
592 default: assert(0 && "Unexpected ValueType for argument!");
595 // Promote the integer to 32 bits. If the input type is signed use a
596 // sign extend, otherwise use a zero extend.
598 dyn_cast<ConstantSDNode>(Op.getOperand(5+2*i+1))->getValue() ?
599 ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
600 Arg = DAG.getNode(ExtOp, MVT::i32, Arg);
606 SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
607 PtrOff = DAG.getNode(ISD::ADD, getPointerTy(), StackPtr, PtrOff);
608 MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0));
614 SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
615 PtrOff = DAG.getNode(ISD::ADD, getPointerTy(), StackPtr, PtrOff);
616 MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0));
626 if (NumXMMRegs < 4) {
627 RegsToPass.push_back(std::make_pair(XMMArgRegs[NumXMMRegs], Arg));
630 // XMM arguments have to be aligned on 16-byte boundary.
631 ArgOffset = ((ArgOffset + 15) / 16) * 16;
632 SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
633 PtrOff = DAG.getNode(ISD::ADD, getPointerTy(), StackPtr, PtrOff);
634 MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0));
640 if (!MemOpChains.empty())
641 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
642 &MemOpChains[0], MemOpChains.size());
644 // Build a sequence of copy-to-reg nodes chained together with token chain
645 // and flag operands which copy the outgoing args into registers.
647 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
648 Chain = DAG.getCopyToReg(Chain, RegsToPass[i].first, RegsToPass[i].second,
650 InFlag = Chain.getValue(1);
653 // If the callee is a GlobalAddress node (quite common, every direct call is)
654 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
655 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
656 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), getPointerTy());
657 else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee))
658 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy());
660 std::vector<MVT::ValueType> NodeTys;
661 NodeTys.push_back(MVT::Other); // Returns a chain
662 NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use.
663 std::vector<SDOperand> Ops;
664 Ops.push_back(Chain);
665 Ops.push_back(Callee);
667 // Add argument registers to the end of the list so that they are known live
669 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
670 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
671 RegsToPass[i].second.getValueType()));
674 Ops.push_back(InFlag);
676 Chain = DAG.getNode(isTailCall ? X86ISD::TAILCALL : X86ISD::CALL,
677 NodeTys, &Ops[0], Ops.size());
678 InFlag = Chain.getValue(1);
680 // Create the CALLSEQ_END node.
681 unsigned NumBytesForCalleeToPush = 0;
683 // If this is is a call to a struct-return function on Darwin/X86, the callee
684 // pops the hidden struct pointer, so we have to push it back.
685 if (CallingConv == CallingConv::CSRet && Subtarget->isTargetDarwin())
686 NumBytesForCalleeToPush = 4;
689 NodeTys.push_back(MVT::Other); // Returns a chain
690 if (RetVT != MVT::Other)
691 NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use.
693 Ops.push_back(Chain);
694 Ops.push_back(DAG.getConstant(NumBytes, getPointerTy()));
695 Ops.push_back(DAG.getConstant(NumBytesForCalleeToPush, getPointerTy()));
696 Ops.push_back(InFlag);
697 Chain = DAG.getNode(ISD::CALLSEQ_END, NodeTys, &Ops[0], Ops.size());
698 if (RetVT != MVT::Other)
699 InFlag = Chain.getValue(1);
701 std::vector<SDOperand> ResultVals;
704 default: assert(0 && "Unknown value type to return!");
705 case MVT::Other: break;
707 Chain = DAG.getCopyFromReg(Chain, X86::AL, MVT::i8, InFlag).getValue(1);
708 ResultVals.push_back(Chain.getValue(0));
709 NodeTys.push_back(MVT::i8);
712 Chain = DAG.getCopyFromReg(Chain, X86::AX, MVT::i16, InFlag).getValue(1);
713 ResultVals.push_back(Chain.getValue(0));
714 NodeTys.push_back(MVT::i16);
717 if (Op.Val->getValueType(1) == MVT::i32) {
718 Chain = DAG.getCopyFromReg(Chain, X86::EAX, MVT::i32, InFlag).getValue(1);
719 ResultVals.push_back(Chain.getValue(0));
720 Chain = DAG.getCopyFromReg(Chain, X86::EDX, MVT::i32,
721 Chain.getValue(2)).getValue(1);
722 ResultVals.push_back(Chain.getValue(0));
723 NodeTys.push_back(MVT::i32);
725 Chain = DAG.getCopyFromReg(Chain, X86::EAX, MVT::i32, InFlag).getValue(1);
726 ResultVals.push_back(Chain.getValue(0));
728 NodeTys.push_back(MVT::i32);
736 Chain = DAG.getCopyFromReg(Chain, X86::XMM0, RetVT, InFlag).getValue(1);
737 ResultVals.push_back(Chain.getValue(0));
738 NodeTys.push_back(RetVT);
742 std::vector<MVT::ValueType> Tys;
743 Tys.push_back(MVT::f64);
744 Tys.push_back(MVT::Other);
745 Tys.push_back(MVT::Flag);
746 std::vector<SDOperand> Ops;
747 Ops.push_back(Chain);
748 Ops.push_back(InFlag);
749 SDOperand RetVal = DAG.getNode(X86ISD::FP_GET_RESULT, Tys,
750 &Ops[0], Ops.size());
751 Chain = RetVal.getValue(1);
752 InFlag = RetVal.getValue(2);
754 // FIXME: Currently the FST is flagged to the FP_GET_RESULT. This
755 // shouldn't be necessary except that RFP cannot be live across
756 // multiple blocks. When stackifier is fixed, they can be uncoupled.
757 MachineFunction &MF = DAG.getMachineFunction();
758 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8);
759 SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
761 Tys.push_back(MVT::Other);
763 Ops.push_back(Chain);
764 Ops.push_back(RetVal);
765 Ops.push_back(StackSlot);
766 Ops.push_back(DAG.getValueType(RetVT));
767 Ops.push_back(InFlag);
768 Chain = DAG.getNode(X86ISD::FST, Tys, &Ops[0], Ops.size());
769 RetVal = DAG.getLoad(RetVT, Chain, StackSlot, NULL, 0);
770 Chain = RetVal.getValue(1);
773 if (RetVT == MVT::f32 && !X86ScalarSSE)
774 // FIXME: we would really like to remember that this FP_ROUND
775 // operation is okay to eliminate if we allow excess FP precision.
776 RetVal = DAG.getNode(ISD::FP_ROUND, MVT::f32, RetVal);
777 ResultVals.push_back(RetVal);
778 NodeTys.push_back(RetVT);
783 // If the function returns void, just return the chain.
784 if (ResultVals.empty())
787 // Otherwise, merge everything together with a MERGE_VALUES node.
788 NodeTys.push_back(MVT::Other);
789 ResultVals.push_back(Chain);
790 SDOperand Res = DAG.getNode(ISD::MERGE_VALUES, NodeTys,
791 &ResultVals[0], ResultVals.size());
792 return Res.getValue(Op.ResNo);
796 //===----------------------------------------------------------------------===//
797 // X86-64 C Calling Convention implementation
798 //===----------------------------------------------------------------------===//
800 /// HowToPassX86_64CCCArgument - Returns how an formal argument of the specified
801 /// type should be passed. If it is through stack, returns the size of the stack
802 /// slot; if it is through integer or XMM register, returns the number of
803 /// integer or XMM registers are needed.
805 HowToPassX86_64CCCArgument(MVT::ValueType ObjectVT,
806 unsigned NumIntRegs, unsigned NumXMMRegs,
807 unsigned &ObjSize, unsigned &ObjIntRegs,
808 unsigned &ObjXMMRegs) {
814 default: assert(0 && "Unhandled argument type!");
824 case MVT::i8: ObjSize = 1; break;
825 case MVT::i16: ObjSize = 2; break;
826 case MVT::i32: ObjSize = 4; break;
827 case MVT::i64: ObjSize = 8; break;
844 case MVT::f32: ObjSize = 4; break;
845 case MVT::f64: ObjSize = 8; break;
851 case MVT::v2f64: ObjSize = 16; break;
859 X86TargetLowering::LowerX86_64CCCArguments(SDOperand Op, SelectionDAG &DAG) {
860 unsigned NumArgs = Op.Val->getNumValues() - 1;
861 MachineFunction &MF = DAG.getMachineFunction();
862 MachineFrameInfo *MFI = MF.getFrameInfo();
863 SDOperand Root = Op.getOperand(0);
864 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
865 std::vector<SDOperand> ArgValues;
867 // Add DAG nodes to load the arguments... On entry to a function on the X86,
868 // the stack frame looks like this:
870 // [RSP] -- return address
871 // [RSP + 8] -- first nonreg argument (leftmost lexically)
872 // [RSP +16] -- second nonreg argument, if 1st argument is <= 8 bytes in size
875 unsigned ArgOffset = 0; // Frame mechanisms handle retaddr slot
876 unsigned NumIntRegs = 0; // Int regs used for parameter passing.
877 unsigned NumXMMRegs = 0; // XMM regs used for parameter passing.
879 static const unsigned GPR8ArgRegs[] = {
880 X86::DIL, X86::SIL, X86::DL, X86::CL, X86::R8B, X86::R9B
882 static const unsigned GPR16ArgRegs[] = {
883 X86::DI, X86::SI, X86::DX, X86::CX, X86::R8W, X86::R9W
885 static const unsigned GPR32ArgRegs[] = {
886 X86::EDI, X86::ESI, X86::EDX, X86::ECX, X86::R8D, X86::R9D
888 static const unsigned GPR64ArgRegs[] = {
889 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
891 static const unsigned XMMArgRegs[] = {
892 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
893 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
896 for (unsigned i = 0; i < NumArgs; ++i) {
897 MVT::ValueType ObjectVT = Op.getValue(i).getValueType();
898 unsigned ArgIncrement = 8;
899 unsigned ObjSize = 0;
900 unsigned ObjIntRegs = 0;
901 unsigned ObjXMMRegs = 0;
903 // FIXME: __int128 and long double support?
904 HowToPassX86_64CCCArgument(ObjectVT, NumIntRegs, NumXMMRegs,
905 ObjSize, ObjIntRegs, ObjXMMRegs);
907 ArgIncrement = ObjSize;
911 if (ObjIntRegs || ObjXMMRegs) {
913 default: assert(0 && "Unhandled argument type!");
918 TargetRegisterClass *RC = NULL;
922 RC = X86::GR8RegisterClass;
923 Reg = GPR8ArgRegs[NumIntRegs];
926 RC = X86::GR16RegisterClass;
927 Reg = GPR16ArgRegs[NumIntRegs];
930 RC = X86::GR32RegisterClass;
931 Reg = GPR32ArgRegs[NumIntRegs];
934 RC = X86::GR64RegisterClass;
935 Reg = GPR64ArgRegs[NumIntRegs];
938 Reg = AddLiveIn(MF, Reg, RC);
939 ArgValue = DAG.getCopyFromReg(Root, Reg, ObjectVT);
950 TargetRegisterClass *RC= (ObjectVT == MVT::f32) ?
951 X86::FR32RegisterClass : ((ObjectVT == MVT::f64) ?
952 X86::FR64RegisterClass : X86::VR128RegisterClass);
953 Reg = AddLiveIn(MF, XMMArgRegs[NumXMMRegs], RC);
954 ArgValue = DAG.getCopyFromReg(Root, Reg, ObjectVT);
958 NumIntRegs += ObjIntRegs;
959 NumXMMRegs += ObjXMMRegs;
960 } else if (ObjSize) {
961 // XMM arguments have to be aligned on 16-byte boundary.
963 ArgOffset = ((ArgOffset + 15) / 16) * 16;
964 // Create the SelectionDAG nodes corresponding to a load from this
966 int FI = MFI->CreateFixedObject(ObjSize, ArgOffset);
967 SDOperand FIN = DAG.getFrameIndex(FI, getPointerTy());
968 ArgValue = DAG.getLoad(Op.Val->getValueType(i), Root, FIN, NULL, 0);
969 ArgOffset += ArgIncrement; // Move on to the next argument.
972 ArgValues.push_back(ArgValue);
975 // If the function takes variable number of arguments, make a frame index for
976 // the start of the first vararg value... for expansion of llvm.va_start.
978 // For X86-64, if there are vararg parameters that are passed via
979 // registers, then we must store them to their spots on the stack so they
980 // may be loaded by deferencing the result of va_next.
981 VarArgsGPOffset = NumIntRegs * 8;
982 VarArgsFPOffset = 6 * 8 + NumXMMRegs * 16;
983 VarArgsFrameIndex = MFI->CreateFixedObject(1, ArgOffset);
984 RegSaveFrameIndex = MFI->CreateStackObject(6 * 8 + 8 * 16, 16);
986 // Store the integer parameter registers.
987 std::vector<SDOperand> MemOps;
988 SDOperand RSFIN = DAG.getFrameIndex(RegSaveFrameIndex, getPointerTy());
989 SDOperand FIN = DAG.getNode(ISD::ADD, getPointerTy(), RSFIN,
990 DAG.getConstant(VarArgsGPOffset, getPointerTy()));
991 for (; NumIntRegs != 6; ++NumIntRegs) {
992 unsigned VReg = AddLiveIn(MF, GPR64ArgRegs[NumIntRegs],
993 X86::GR64RegisterClass);
994 SDOperand Val = DAG.getCopyFromReg(Root, VReg, MVT::i64);
995 SDOperand Store = DAG.getStore(Val.getValue(1), Val, FIN, NULL, 0);
996 MemOps.push_back(Store);
997 FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN,
998 DAG.getConstant(8, getPointerTy()));
1001 // Now store the XMM (fp + vector) parameter registers.
1002 FIN = DAG.getNode(ISD::ADD, getPointerTy(), RSFIN,
1003 DAG.getConstant(VarArgsFPOffset, getPointerTy()));
1004 for (; NumXMMRegs != 8; ++NumXMMRegs) {
1005 unsigned VReg = AddLiveIn(MF, XMMArgRegs[NumXMMRegs],
1006 X86::VR128RegisterClass);
1007 SDOperand Val = DAG.getCopyFromReg(Root, VReg, MVT::v4f32);
1008 SDOperand Store = DAG.getStore(Val.getValue(1), Val, FIN, NULL, 0);
1009 MemOps.push_back(Store);
1010 FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN,
1011 DAG.getConstant(16, getPointerTy()));
1013 if (!MemOps.empty())
1014 Root = DAG.getNode(ISD::TokenFactor, MVT::Other,
1015 &MemOps[0], MemOps.size());
1018 ArgValues.push_back(Root);
1020 ReturnAddrIndex = 0; // No return address slot generated yet.
1021 BytesToPopOnReturn = 0; // Callee pops nothing.
1022 BytesCallerReserves = ArgOffset;
1024 // Return the new list of results.
1025 std::vector<MVT::ValueType> RetVTs(Op.Val->value_begin(),
1026 Op.Val->value_end());
1027 return DAG.getNode(ISD::MERGE_VALUES, RetVTs, &ArgValues[0],ArgValues.size());
1031 X86TargetLowering::LowerX86_64CCCCallTo(SDOperand Op, SelectionDAG &DAG) {
1032 SDOperand Chain = Op.getOperand(0);
1033 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
1034 bool isTailCall = cast<ConstantSDNode>(Op.getOperand(3))->getValue() != 0;
1035 SDOperand Callee = Op.getOperand(4);
1036 MVT::ValueType RetVT= Op.Val->getValueType(0);
1037 unsigned NumOps = (Op.getNumOperands() - 5) / 2;
1039 // Count how many bytes are to be pushed on the stack.
1040 unsigned NumBytes = 0;
1041 unsigned NumIntRegs = 0; // Int regs used for parameter passing.
1042 unsigned NumXMMRegs = 0; // XMM regs used for parameter passing.
1044 static const unsigned GPR8ArgRegs[] = {
1045 X86::DIL, X86::SIL, X86::DL, X86::CL, X86::R8B, X86::R9B
1047 static const unsigned GPR16ArgRegs[] = {
1048 X86::DI, X86::SI, X86::DX, X86::CX, X86::R8W, X86::R9W
1050 static const unsigned GPR32ArgRegs[] = {
1051 X86::EDI, X86::ESI, X86::EDX, X86::ECX, X86::R8D, X86::R9D
1053 static const unsigned GPR64ArgRegs[] = {
1054 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
1056 static const unsigned XMMArgRegs[] = {
1057 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
1058 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
1061 for (unsigned i = 0; i != NumOps; ++i) {
1062 SDOperand Arg = Op.getOperand(5+2*i);
1063 MVT::ValueType ArgVT = Arg.getValueType();
1066 default: assert(0 && "Unknown value type!");
1086 else if (ArgVT == MVT::f32 || ArgVT == MVT::f64)
1089 // XMM arguments have to be aligned on 16-byte boundary.
1090 NumBytes = ((NumBytes + 15) / 16) * 16;
1097 Chain = DAG.getCALLSEQ_START(Chain,DAG.getConstant(NumBytes, getPointerTy()));
1099 // Arguments go on the stack in reverse order, as specified by the ABI.
1100 unsigned ArgOffset = 0;
1103 std::vector<std::pair<unsigned, SDOperand> > RegsToPass;
1104 std::vector<SDOperand> MemOpChains;
1105 SDOperand StackPtr = DAG.getRegister(X86StackPtr, getPointerTy());
1106 for (unsigned i = 0; i != NumOps; ++i) {
1107 SDOperand Arg = Op.getOperand(5+2*i);
1108 MVT::ValueType ArgVT = Arg.getValueType();
1111 default: assert(0 && "Unexpected ValueType for argument!");
1116 if (NumIntRegs < 6) {
1120 case MVT::i8: Reg = GPR8ArgRegs[NumIntRegs]; break;
1121 case MVT::i16: Reg = GPR16ArgRegs[NumIntRegs]; break;
1122 case MVT::i32: Reg = GPR32ArgRegs[NumIntRegs]; break;
1123 case MVT::i64: Reg = GPR64ArgRegs[NumIntRegs]; break;
1125 RegsToPass.push_back(std::make_pair(Reg, Arg));
1128 SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
1129 PtrOff = DAG.getNode(ISD::ADD, getPointerTy(), StackPtr, PtrOff);
1130 MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0));
1142 if (NumXMMRegs < 8) {
1143 RegsToPass.push_back(std::make_pair(XMMArgRegs[NumXMMRegs], Arg));
1146 if (ArgVT != MVT::f32 && ArgVT != MVT::f64) {
1147 // XMM arguments have to be aligned on 16-byte boundary.
1148 ArgOffset = ((ArgOffset + 15) / 16) * 16;
1150 SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
1151 PtrOff = DAG.getNode(ISD::ADD, getPointerTy(), StackPtr, PtrOff);
1152 MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0));
1153 if (ArgVT == MVT::f32 || ArgVT == MVT::f64)
1161 if (!MemOpChains.empty())
1162 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
1163 &MemOpChains[0], MemOpChains.size());
1165 // Build a sequence of copy-to-reg nodes chained together with token chain
1166 // and flag operands which copy the outgoing args into registers.
1168 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1169 Chain = DAG.getCopyToReg(Chain, RegsToPass[i].first, RegsToPass[i].second,
1171 InFlag = Chain.getValue(1);
1175 // From AMD64 ABI document:
1176 // For calls that may call functions that use varargs or stdargs
1177 // (prototype-less calls or calls to functions containing ellipsis (...) in
1178 // the declaration) %al is used as hidden argument to specify the number
1179 // of SSE registers used. The contents of %al do not need to match exactly
1180 // the number of registers, but must be an ubound on the number of SSE
1181 // registers used and is in the range 0 - 8 inclusive.
1182 Chain = DAG.getCopyToReg(Chain, X86::AL,
1183 DAG.getConstant(NumXMMRegs, MVT::i8), InFlag);
1184 InFlag = Chain.getValue(1);
1187 // If the callee is a GlobalAddress node (quite common, every direct call is)
1188 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
1189 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
1190 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), getPointerTy());
1191 else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee))
1192 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy());
1194 std::vector<MVT::ValueType> NodeTys;
1195 NodeTys.push_back(MVT::Other); // Returns a chain
1196 NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use.
1197 std::vector<SDOperand> Ops;
1198 Ops.push_back(Chain);
1199 Ops.push_back(Callee);
1201 // Add argument registers to the end of the list so that they are known live
1203 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
1204 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
1205 RegsToPass[i].second.getValueType()));
1208 Ops.push_back(InFlag);
1210 // FIXME: Do not generate X86ISD::TAILCALL for now.
1211 Chain = DAG.getNode(isTailCall ? X86ISD::TAILCALL : X86ISD::CALL,
1212 NodeTys, &Ops[0], Ops.size());
1213 InFlag = Chain.getValue(1);
1216 NodeTys.push_back(MVT::Other); // Returns a chain
1217 if (RetVT != MVT::Other)
1218 NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use.
1220 Ops.push_back(Chain);
1221 Ops.push_back(DAG.getConstant(NumBytes, getPointerTy()));
1222 Ops.push_back(DAG.getConstant(0, getPointerTy()));
1223 Ops.push_back(InFlag);
1224 Chain = DAG.getNode(ISD::CALLSEQ_END, NodeTys, &Ops[0], Ops.size());
1225 if (RetVT != MVT::Other)
1226 InFlag = Chain.getValue(1);
1228 std::vector<SDOperand> ResultVals;
1231 default: assert(0 && "Unknown value type to return!");
1232 case MVT::Other: break;
1234 Chain = DAG.getCopyFromReg(Chain, X86::AL, MVT::i8, InFlag).getValue(1);
1235 ResultVals.push_back(Chain.getValue(0));
1236 NodeTys.push_back(MVT::i8);
1239 Chain = DAG.getCopyFromReg(Chain, X86::AX, MVT::i16, InFlag).getValue(1);
1240 ResultVals.push_back(Chain.getValue(0));
1241 NodeTys.push_back(MVT::i16);
1244 Chain = DAG.getCopyFromReg(Chain, X86::EAX, MVT::i32, InFlag).getValue(1);
1245 ResultVals.push_back(Chain.getValue(0));
1246 NodeTys.push_back(MVT::i32);
1249 if (Op.Val->getValueType(1) == MVT::i64) {
1250 // FIXME: __int128 support?
1251 Chain = DAG.getCopyFromReg(Chain, X86::RAX, MVT::i64, InFlag).getValue(1);
1252 ResultVals.push_back(Chain.getValue(0));
1253 Chain = DAG.getCopyFromReg(Chain, X86::RDX, MVT::i64,
1254 Chain.getValue(2)).getValue(1);
1255 ResultVals.push_back(Chain.getValue(0));
1256 NodeTys.push_back(MVT::i64);
1258 Chain = DAG.getCopyFromReg(Chain, X86::RAX, MVT::i64, InFlag).getValue(1);
1259 ResultVals.push_back(Chain.getValue(0));
1261 NodeTys.push_back(MVT::i64);
1271 // FIXME: long double support?
1272 Chain = DAG.getCopyFromReg(Chain, X86::XMM0, RetVT, InFlag).getValue(1);
1273 ResultVals.push_back(Chain.getValue(0));
1274 NodeTys.push_back(RetVT);
1278 // If the function returns void, just return the chain.
1279 if (ResultVals.empty())
1282 // Otherwise, merge everything together with a MERGE_VALUES node.
1283 NodeTys.push_back(MVT::Other);
1284 ResultVals.push_back(Chain);
1285 SDOperand Res = DAG.getNode(ISD::MERGE_VALUES, NodeTys,
1286 &ResultVals[0], ResultVals.size());
1287 return Res.getValue(Op.ResNo);
1290 //===----------------------------------------------------------------------===//
1291 // Fast Calling Convention implementation
1292 //===----------------------------------------------------------------------===//
1294 // The X86 'fast' calling convention passes up to two integer arguments in
1295 // registers (an appropriate portion of EAX/EDX), passes arguments in C order,
1296 // and requires that the callee pop its arguments off the stack (allowing proper
1297 // tail calls), and has the same return value conventions as C calling convs.
1299 // This calling convention always arranges for the callee pop value to be 8n+4
1300 // bytes, which is needed for tail recursion elimination and stack alignment
1303 // Note that this can be enhanced in the future to pass fp vals in registers
1304 // (when we have a global fp allocator) and do other tricks.
1307 /// HowToPassFastCCArgument - Returns how an formal argument of the specified
1308 /// type should be passed. If it is through stack, returns the size of the stack
1309 /// slot; if it is through integer or XMM register, returns the number of
1310 /// integer or XMM registers are needed.
1312 HowToPassFastCCArgument(MVT::ValueType ObjectVT,
1313 unsigned NumIntRegs, unsigned NumXMMRegs,
1314 unsigned &ObjSize, unsigned &ObjIntRegs,
1315 unsigned &ObjXMMRegs) {
1321 default: assert(0 && "Unhandled argument type!");
1323 #if FASTCC_NUM_INT_ARGS_INREGS > 0
1324 if (NumIntRegs < FASTCC_NUM_INT_ARGS_INREGS)
1331 #if FASTCC_NUM_INT_ARGS_INREGS > 0
1332 if (NumIntRegs < FASTCC_NUM_INT_ARGS_INREGS)
1339 #if FASTCC_NUM_INT_ARGS_INREGS > 0
1340 if (NumIntRegs < FASTCC_NUM_INT_ARGS_INREGS)
1347 #if FASTCC_NUM_INT_ARGS_INREGS > 0
1348 if (NumIntRegs+2 <= FASTCC_NUM_INT_ARGS_INREGS) {
1350 } else if (NumIntRegs+1 <= FASTCC_NUM_INT_ARGS_INREGS) {
1377 X86TargetLowering::LowerFastCCArguments(SDOperand Op, SelectionDAG &DAG) {
1378 unsigned NumArgs = Op.Val->getNumValues()-1;
1379 MachineFunction &MF = DAG.getMachineFunction();
1380 MachineFrameInfo *MFI = MF.getFrameInfo();
1381 SDOperand Root = Op.getOperand(0);
1382 std::vector<SDOperand> ArgValues;
1384 // Add DAG nodes to load the arguments... On entry to a function the stack
1385 // frame looks like this:
1387 // [ESP] -- return address
1388 // [ESP + 4] -- first nonreg argument (leftmost lexically)
1389 // [ESP + 8] -- second nonreg argument, if 1st argument is <= 4 bytes in size
1391 unsigned ArgOffset = 0; // Frame mechanisms handle retaddr slot
1393 // Keep track of the number of integer regs passed so far. This can be either
1394 // 0 (neither EAX or EDX used), 1 (EAX is used) or 2 (EAX and EDX are both
1396 unsigned NumIntRegs = 0;
1397 unsigned NumXMMRegs = 0; // XMM regs used for parameter passing.
1399 static const unsigned XMMArgRegs[] = {
1400 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
1403 for (unsigned i = 0; i < NumArgs; ++i) {
1404 MVT::ValueType ObjectVT = Op.getValue(i).getValueType();
1405 unsigned ArgIncrement = 4;
1406 unsigned ObjSize = 0;
1407 unsigned ObjIntRegs = 0;
1408 unsigned ObjXMMRegs = 0;
1410 HowToPassFastCCArgument(ObjectVT, NumIntRegs, NumXMMRegs,
1411 ObjSize, ObjIntRegs, ObjXMMRegs);
1413 ArgIncrement = ObjSize;
1417 if (ObjIntRegs || ObjXMMRegs) {
1419 default: assert(0 && "Unhandled argument type!");
1421 Reg = AddLiveIn(MF, NumIntRegs ? X86::DL : X86::AL,
1422 X86::GR8RegisterClass);
1423 ArgValue = DAG.getCopyFromReg(Root, Reg, MVT::i8);
1426 Reg = AddLiveIn(MF, NumIntRegs ? X86::DX : X86::AX,
1427 X86::GR16RegisterClass);
1428 ArgValue = DAG.getCopyFromReg(Root, Reg, MVT::i16);
1431 Reg = AddLiveIn(MF, NumIntRegs ? X86::EDX : X86::EAX,
1432 X86::GR32RegisterClass);
1433 ArgValue = DAG.getCopyFromReg(Root, Reg, MVT::i32);
1436 Reg = AddLiveIn(MF, NumIntRegs ? X86::EDX : X86::EAX,
1437 X86::GR32RegisterClass);
1438 ArgValue = DAG.getCopyFromReg(Root, Reg, MVT::i32);
1439 if (ObjIntRegs == 2) {
1440 Reg = AddLiveIn(MF, X86::EDX, X86::GR32RegisterClass);
1441 SDOperand ArgValue2 = DAG.getCopyFromReg(Root, Reg, MVT::i32);
1442 ArgValue= DAG.getNode(ISD::BUILD_PAIR, MVT::i64, ArgValue, ArgValue2);
1451 Reg = AddLiveIn(MF, XMMArgRegs[NumXMMRegs], X86::VR128RegisterClass);
1452 ArgValue = DAG.getCopyFromReg(Root, Reg, ObjectVT);
1455 NumIntRegs += ObjIntRegs;
1456 NumXMMRegs += ObjXMMRegs;
1460 // XMM arguments have to be aligned on 16-byte boundary.
1462 ArgOffset = ((ArgOffset + 15) / 16) * 16;
1463 // Create the SelectionDAG nodes corresponding to a load from this
1465 int FI = MFI->CreateFixedObject(ObjSize, ArgOffset);
1466 SDOperand FIN = DAG.getFrameIndex(FI, getPointerTy());
1467 if (ObjectVT == MVT::i64 && ObjIntRegs) {
1468 SDOperand ArgValue2 = DAG.getLoad(Op.Val->getValueType(i), Root, FIN,
1470 ArgValue = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, ArgValue, ArgValue2);
1472 ArgValue = DAG.getLoad(Op.Val->getValueType(i), Root, FIN, NULL, 0);
1473 ArgOffset += ArgIncrement; // Move on to the next argument.
1476 ArgValues.push_back(ArgValue);
1479 ArgValues.push_back(Root);
1481 // Make sure the instruction takes 8n+4 bytes to make sure the start of the
1482 // arguments and the arguments after the retaddr has been pushed are aligned.
1483 if ((ArgOffset & 7) == 0)
1486 VarArgsFrameIndex = 0xAAAAAAA; // fastcc functions can't have varargs.
1487 RegSaveFrameIndex = 0xAAAAAAA; // X86-64 only.
1488 ReturnAddrIndex = 0; // No return address slot generated yet.
1489 BytesToPopOnReturn = ArgOffset; // Callee pops all stack arguments.
1490 BytesCallerReserves = 0;
1492 // Finally, inform the code generator which regs we return values in.
1493 switch (getValueType(MF.getFunction()->getReturnType())) {
1494 default: assert(0 && "Unknown type!");
1495 case MVT::isVoid: break;
1500 MF.addLiveOut(X86::EAX);
1503 MF.addLiveOut(X86::EAX);
1504 MF.addLiveOut(X86::EDX);
1508 MF.addLiveOut(X86::ST0);
1516 MF.addLiveOut(X86::XMM0);
1520 // Return the new list of results.
1521 std::vector<MVT::ValueType> RetVTs(Op.Val->value_begin(),
1522 Op.Val->value_end());
1523 return DAG.getNode(ISD::MERGE_VALUES, RetVTs, &ArgValues[0],ArgValues.size());
1526 SDOperand X86TargetLowering::LowerFastCCCallTo(SDOperand Op, SelectionDAG &DAG,
1528 SDOperand Chain = Op.getOperand(0);
1529 bool isTailCall = cast<ConstantSDNode>(Op.getOperand(3))->getValue() != 0;
1530 SDOperand Callee = Op.getOperand(4);
1531 MVT::ValueType RetVT= Op.Val->getValueType(0);
1532 unsigned NumOps = (Op.getNumOperands() - 5) / 2;
1534 // Count how many bytes are to be pushed on the stack.
1535 unsigned NumBytes = 0;
1537 // Keep track of the number of integer regs passed so far. This can be either
1538 // 0 (neither EAX or EDX used), 1 (EAX is used) or 2 (EAX and EDX are both
1540 unsigned NumIntRegs = 0;
1541 unsigned NumXMMRegs = 0; // XMM regs used for parameter passing.
1543 static const unsigned GPRArgRegs[][2] = {
1544 { X86::AL, X86::DL },
1545 { X86::AX, X86::DX },
1546 { X86::EAX, X86::EDX }
1549 static const unsigned FastCallGPRArgRegs[][2] = {
1550 { X86::CL, X86::DL },
1551 { X86::CX, X86::DX },
1552 { X86::ECX, X86::EDX }
1555 static const unsigned XMMArgRegs[] = {
1556 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
1559 for (unsigned i = 0; i != NumOps; ++i) {
1560 SDOperand Arg = Op.getOperand(5+2*i);
1562 switch (Arg.getValueType()) {
1563 default: assert(0 && "Unknown value type!");
1567 unsigned MaxNumIntRegs = (isFastCall ? 2 : FASTCC_NUM_INT_ARGS_INREGS);
1568 if (NumIntRegs < MaxNumIntRegs) {
1586 assert(0 && "Unknown value type!");
1591 // XMM arguments have to be aligned on 16-byte boundary.
1592 NumBytes = ((NumBytes + 15) / 16) * 16;
1600 // Make sure the instruction takes 8n+4 bytes to make sure the start of the
1601 // arguments and the arguments after the retaddr has been pushed are aligned.
1602 if ((NumBytes & 7) == 0)
1605 Chain = DAG.getCALLSEQ_START(Chain,DAG.getConstant(NumBytes, getPointerTy()));
1607 // Arguments go on the stack in reverse order, as specified by the ABI.
1608 unsigned ArgOffset = 0;
1610 std::vector<std::pair<unsigned, SDOperand> > RegsToPass;
1611 std::vector<SDOperand> MemOpChains;
1612 SDOperand StackPtr = DAG.getRegister(X86StackPtr, getPointerTy());
1613 for (unsigned i = 0; i != NumOps; ++i) {
1614 SDOperand Arg = Op.getOperand(5+2*i);
1616 switch (Arg.getValueType()) {
1617 default: assert(0 && "Unexpected ValueType for argument!");
1621 unsigned MaxNumIntRegs = (isFastCall ? 2 : FASTCC_NUM_INT_ARGS_INREGS);
1622 if (NumIntRegs < MaxNumIntRegs) {
1623 RegsToPass.push_back(
1624 std::make_pair(GPRArgRegs[Arg.getValueType()-MVT::i8][NumIntRegs],
1631 SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
1632 PtrOff = DAG.getNode(ISD::ADD, getPointerTy(), StackPtr, PtrOff);
1633 MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0));
1638 SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
1639 PtrOff = DAG.getNode(ISD::ADD, getPointerTy(), StackPtr, PtrOff);
1640 MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0));
1651 assert(0 && "Unexpected ValueType for argument!");
1653 if (NumXMMRegs < 4) {
1654 RegsToPass.push_back(std::make_pair(XMMArgRegs[NumXMMRegs], Arg));
1657 // XMM arguments have to be aligned on 16-byte boundary.
1658 ArgOffset = ((ArgOffset + 15) / 16) * 16;
1659 SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
1660 PtrOff = DAG.getNode(ISD::ADD, getPointerTy(), StackPtr, PtrOff);
1661 MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0));
1669 if (!MemOpChains.empty())
1670 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
1671 &MemOpChains[0], MemOpChains.size());
1673 // Build a sequence of copy-to-reg nodes chained together with token chain
1674 // and flag operands which copy the outgoing args into registers.
1676 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1677 Chain = DAG.getCopyToReg(Chain, RegsToPass[i].first, RegsToPass[i].second,
1679 InFlag = Chain.getValue(1);
1682 // If the callee is a GlobalAddress node (quite common, every direct call is)
1683 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
1684 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
1685 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), getPointerTy());
1686 else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee))
1687 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy());
1689 std::vector<MVT::ValueType> NodeTys;
1690 NodeTys.push_back(MVT::Other); // Returns a chain
1691 NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use.
1692 std::vector<SDOperand> Ops;
1693 Ops.push_back(Chain);
1694 Ops.push_back(Callee);
1696 // Add argument registers to the end of the list so that they are known live
1698 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
1699 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
1700 RegsToPass[i].second.getValueType()));
1703 Ops.push_back(InFlag);
1705 // FIXME: Do not generate X86ISD::TAILCALL for now.
1706 Chain = DAG.getNode(isTailCall ? X86ISD::TAILCALL : X86ISD::CALL,
1707 NodeTys, &Ops[0], Ops.size());
1708 InFlag = Chain.getValue(1);
1711 NodeTys.push_back(MVT::Other); // Returns a chain
1712 if (RetVT != MVT::Other)
1713 NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use.
1715 Ops.push_back(Chain);
1716 Ops.push_back(DAG.getConstant(NumBytes, getPointerTy()));
1717 Ops.push_back(DAG.getConstant(NumBytes, getPointerTy()));
1718 Ops.push_back(InFlag);
1719 Chain = DAG.getNode(ISD::CALLSEQ_END, NodeTys, &Ops[0], Ops.size());
1720 if (RetVT != MVT::Other)
1721 InFlag = Chain.getValue(1);
1723 std::vector<SDOperand> ResultVals;
1726 default: assert(0 && "Unknown value type to return!");
1727 case MVT::Other: break;
1729 Chain = DAG.getCopyFromReg(Chain, X86::AL, MVT::i8, InFlag).getValue(1);
1730 ResultVals.push_back(Chain.getValue(0));
1731 NodeTys.push_back(MVT::i8);
1734 Chain = DAG.getCopyFromReg(Chain, X86::AX, MVT::i16, InFlag).getValue(1);
1735 ResultVals.push_back(Chain.getValue(0));
1736 NodeTys.push_back(MVT::i16);
1739 if (Op.Val->getValueType(1) == MVT::i32) {
1740 Chain = DAG.getCopyFromReg(Chain, X86::EAX, MVT::i32, InFlag).getValue(1);
1741 ResultVals.push_back(Chain.getValue(0));
1742 Chain = DAG.getCopyFromReg(Chain, X86::EDX, MVT::i32,
1743 Chain.getValue(2)).getValue(1);
1744 ResultVals.push_back(Chain.getValue(0));
1745 NodeTys.push_back(MVT::i32);
1747 Chain = DAG.getCopyFromReg(Chain, X86::EAX, MVT::i32, InFlag).getValue(1);
1748 ResultVals.push_back(Chain.getValue(0));
1750 NodeTys.push_back(MVT::i32);
1759 assert(0 && "Unknown value type to return!");
1761 Chain = DAG.getCopyFromReg(Chain, X86::XMM0, RetVT, InFlag).getValue(1);
1762 ResultVals.push_back(Chain.getValue(0));
1763 NodeTys.push_back(RetVT);
1768 std::vector<MVT::ValueType> Tys;
1769 Tys.push_back(MVT::f64);
1770 Tys.push_back(MVT::Other);
1771 Tys.push_back(MVT::Flag);
1772 std::vector<SDOperand> Ops;
1773 Ops.push_back(Chain);
1774 Ops.push_back(InFlag);
1775 SDOperand RetVal = DAG.getNode(X86ISD::FP_GET_RESULT, Tys,
1776 &Ops[0], Ops.size());
1777 Chain = RetVal.getValue(1);
1778 InFlag = RetVal.getValue(2);
1780 // FIXME: Currently the FST is flagged to the FP_GET_RESULT. This
1781 // shouldn't be necessary except that RFP cannot be live across
1782 // multiple blocks. When stackifier is fixed, they can be uncoupled.
1783 MachineFunction &MF = DAG.getMachineFunction();
1784 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8);
1785 SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
1787 Tys.push_back(MVT::Other);
1789 Ops.push_back(Chain);
1790 Ops.push_back(RetVal);
1791 Ops.push_back(StackSlot);
1792 Ops.push_back(DAG.getValueType(RetVT));
1793 Ops.push_back(InFlag);
1794 Chain = DAG.getNode(X86ISD::FST, Tys, &Ops[0], Ops.size());
1795 RetVal = DAG.getLoad(RetVT, Chain, StackSlot, NULL, 0);
1796 Chain = RetVal.getValue(1);
1799 if (RetVT == MVT::f32 && !X86ScalarSSE)
1800 // FIXME: we would really like to remember that this FP_ROUND
1801 // operation is okay to eliminate if we allow excess FP precision.
1802 RetVal = DAG.getNode(ISD::FP_ROUND, MVT::f32, RetVal);
1803 ResultVals.push_back(RetVal);
1804 NodeTys.push_back(RetVT);
1810 // If the function returns void, just return the chain.
1811 if (ResultVals.empty())
1814 // Otherwise, merge everything together with a MERGE_VALUES node.
1815 NodeTys.push_back(MVT::Other);
1816 ResultVals.push_back(Chain);
1817 SDOperand Res = DAG.getNode(ISD::MERGE_VALUES, NodeTys,
1818 &ResultVals[0], ResultVals.size());
1819 return Res.getValue(Op.ResNo);
1822 //===----------------------------------------------------------------------===//
1823 // StdCall Calling Convention implementation
1824 //===----------------------------------------------------------------------===//
1825 // StdCall calling convention seems to be standard for many Windows' API
1826 // routines and around. It differs from C calling convention just a little:
1827 // callee should clean up the stack, not caller. Symbols should be also
1828 // decorated in some fancy way :) It doesn't support any vector arguments.
1830 /// HowToPassStdCallCCArgument - Returns how an formal argument of the specified
1831 /// type should be passed. Returns the size of the stack slot
1833 HowToPassStdCallCCArgument(MVT::ValueType ObjectVT, unsigned &ObjSize) {
1835 default: assert(0 && "Unhandled argument type!");
1836 case MVT::i8: ObjSize = 1; break;
1837 case MVT::i16: ObjSize = 2; break;
1838 case MVT::i32: ObjSize = 4; break;
1839 case MVT::i64: ObjSize = 8; break;
1840 case MVT::f32: ObjSize = 4; break;
1841 case MVT::f64: ObjSize = 8; break;
1845 SDOperand X86TargetLowering::LowerStdCallCCArguments(SDOperand Op,
1846 SelectionDAG &DAG) {
1847 unsigned NumArgs = Op.Val->getNumValues() - 1;
1848 MachineFunction &MF = DAG.getMachineFunction();
1849 MachineFrameInfo *MFI = MF.getFrameInfo();
1850 SDOperand Root = Op.getOperand(0);
1851 std::vector<SDOperand> ArgValues;
1853 // Add DAG nodes to load the arguments... On entry to a function on the X86,
1854 // the stack frame looks like this:
1856 // [ESP] -- return address
1857 // [ESP + 4] -- first argument (leftmost lexically)
1858 // [ESP + 8] -- second argument, if first argument is <= 4 bytes in size
1861 unsigned ArgOffset = 0; // Frame mechanisms handle retaddr slot
1862 for (unsigned i = 0; i < NumArgs; ++i) {
1863 MVT::ValueType ObjectVT = Op.getValue(i).getValueType();
1864 unsigned ArgIncrement = 4;
1865 unsigned ObjSize = 0;
1866 HowToPassStdCallCCArgument(ObjectVT, ObjSize);
1868 ArgIncrement = ObjSize;
1871 // Create the frame index object for this incoming parameter...
1872 int FI = MFI->CreateFixedObject(ObjSize, ArgOffset);
1873 SDOperand FIN = DAG.getFrameIndex(FI, getPointerTy());
1874 ArgValue = DAG.getLoad(Op.Val->getValueType(i), Root, FIN, NULL, 0);
1875 ArgValues.push_back(ArgValue);
1876 ArgOffset += ArgIncrement; // Move on to the next argument...
1879 ArgValues.push_back(Root);
1881 // If the function takes variable number of arguments, make a frame index for
1882 // the start of the first vararg value... for expansion of llvm.va_start.
1883 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
1885 BytesToPopOnReturn = 0; // Callee pops nothing.
1886 BytesCallerReserves = ArgOffset;
1887 VarArgsFrameIndex = MFI->CreateFixedObject(1, ArgOffset);
1889 BytesToPopOnReturn = ArgOffset; // Callee pops everything..
1890 BytesCallerReserves = 0;
1892 RegSaveFrameIndex = 0xAAAAAAA; // X86-64 only.
1893 ReturnAddrIndex = 0; // No return address slot generated yet.
1895 MF.getInfo<X86FunctionInfo>()->setBytesToPopOnReturn(BytesToPopOnReturn);
1897 // Return the new list of results.
1898 std::vector<MVT::ValueType> RetVTs(Op.Val->value_begin(),
1899 Op.Val->value_end());
1900 return DAG.getNode(ISD::MERGE_VALUES, RetVTs, &ArgValues[0],ArgValues.size());
1904 SDOperand X86TargetLowering::LowerStdCallCCCallTo(SDOperand Op,
1905 SelectionDAG &DAG) {
1906 SDOperand Chain = Op.getOperand(0);
1907 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
1908 bool isTailCall = cast<ConstantSDNode>(Op.getOperand(3))->getValue() != 0;
1909 SDOperand Callee = Op.getOperand(4);
1910 MVT::ValueType RetVT= Op.Val->getValueType(0);
1911 unsigned NumOps = (Op.getNumOperands() - 5) / 2;
1913 // Count how many bytes are to be pushed on the stack.
1914 unsigned NumBytes = 0;
1915 for (unsigned i = 0; i != NumOps; ++i) {
1916 SDOperand Arg = Op.getOperand(5+2*i);
1918 switch (Arg.getValueType()) {
1919 default: assert(0 && "Unexpected ValueType for argument!");
1933 Chain = DAG.getCALLSEQ_START(Chain,DAG.getConstant(NumBytes, getPointerTy()));
1935 // Arguments go on the stack in reverse order, as specified by the ABI.
1936 unsigned ArgOffset = 0;
1937 std::vector<SDOperand> MemOpChains;
1938 SDOperand StackPtr = DAG.getRegister(X86StackPtr, getPointerTy());
1939 for (unsigned i = 0; i != NumOps; ++i) {
1940 SDOperand Arg = Op.getOperand(5+2*i);
1942 switch (Arg.getValueType()) {
1943 default: assert(0 && "Unexpected ValueType for argument!");
1946 // Promote the integer to 32 bits. If the input type is signed use a
1947 // sign extend, otherwise use a zero extend.
1949 dyn_cast<ConstantSDNode>(Op.getOperand(5+2*i+1))->getValue() ?
1950 ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
1951 Arg = DAG.getNode(ExtOp, MVT::i32, Arg);
1957 SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
1958 PtrOff = DAG.getNode(ISD::ADD, getPointerTy(), StackPtr, PtrOff);
1959 MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0));
1965 SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
1966 PtrOff = DAG.getNode(ISD::ADD, getPointerTy(), StackPtr, PtrOff);
1967 MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0));
1974 if (!MemOpChains.empty())
1975 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
1976 &MemOpChains[0], MemOpChains.size());
1978 // If the callee is a GlobalAddress node (quite common, every direct call is)
1979 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
1980 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
1981 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), getPointerTy());
1982 else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee))
1983 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy());
1985 std::vector<MVT::ValueType> NodeTys;
1986 NodeTys.push_back(MVT::Other); // Returns a chain
1987 NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use.
1988 std::vector<SDOperand> Ops;
1989 Ops.push_back(Chain);
1990 Ops.push_back(Callee);
1992 Chain = DAG.getNode(isTailCall ? X86ISD::TAILCALL : X86ISD::CALL,
1993 NodeTys, &Ops[0], Ops.size());
1994 SDOperand InFlag = Chain.getValue(1);
1996 // Create the CALLSEQ_END node.
1997 unsigned NumBytesForCalleeToPush;
2000 NumBytesForCalleeToPush = 0;
2002 NumBytesForCalleeToPush = NumBytes;
2006 NodeTys.push_back(MVT::Other); // Returns a chain
2007 if (RetVT != MVT::Other)
2008 NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use.
2010 Ops.push_back(Chain);
2011 Ops.push_back(DAG.getConstant(NumBytes, getPointerTy()));
2012 Ops.push_back(DAG.getConstant(NumBytesForCalleeToPush, getPointerTy()));
2013 Ops.push_back(InFlag);
2014 Chain = DAG.getNode(ISD::CALLSEQ_END, NodeTys, &Ops[0], Ops.size());
2015 if (RetVT != MVT::Other)
2016 InFlag = Chain.getValue(1);
2018 std::vector<SDOperand> ResultVals;
2021 default: assert(0 && "Unknown value type to return!");
2022 case MVT::Other: break;
2024 Chain = DAG.getCopyFromReg(Chain, X86::AL, MVT::i8, InFlag).getValue(1);
2025 ResultVals.push_back(Chain.getValue(0));
2026 NodeTys.push_back(MVT::i8);
2029 Chain = DAG.getCopyFromReg(Chain, X86::AX, MVT::i16, InFlag).getValue(1);
2030 ResultVals.push_back(Chain.getValue(0));
2031 NodeTys.push_back(MVT::i16);
2034 if (Op.Val->getValueType(1) == MVT::i32) {
2035 Chain = DAG.getCopyFromReg(Chain, X86::EAX, MVT::i32, InFlag).getValue(1);
2036 ResultVals.push_back(Chain.getValue(0));
2037 Chain = DAG.getCopyFromReg(Chain, X86::EDX, MVT::i32,
2038 Chain.getValue(2)).getValue(1);
2039 ResultVals.push_back(Chain.getValue(0));
2040 NodeTys.push_back(MVT::i32);
2042 Chain = DAG.getCopyFromReg(Chain, X86::EAX, MVT::i32, InFlag).getValue(1);
2043 ResultVals.push_back(Chain.getValue(0));
2045 NodeTys.push_back(MVT::i32);
2049 std::vector<MVT::ValueType> Tys;
2050 Tys.push_back(MVT::f64);
2051 Tys.push_back(MVT::Other);
2052 Tys.push_back(MVT::Flag);
2053 std::vector<SDOperand> Ops;
2054 Ops.push_back(Chain);
2055 Ops.push_back(InFlag);
2056 SDOperand RetVal = DAG.getNode(X86ISD::FP_GET_RESULT, Tys,
2057 &Ops[0], Ops.size());
2058 Chain = RetVal.getValue(1);
2059 InFlag = RetVal.getValue(2);
2061 // FIXME: Currently the FST is flagged to the FP_GET_RESULT. This
2062 // shouldn't be necessary except that RFP cannot be live across
2063 // multiple blocks. When stackifier is fixed, they can be uncoupled.
2064 MachineFunction &MF = DAG.getMachineFunction();
2065 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8);
2066 SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
2068 Tys.push_back(MVT::Other);
2070 Ops.push_back(Chain);
2071 Ops.push_back(RetVal);
2072 Ops.push_back(StackSlot);
2073 Ops.push_back(DAG.getValueType(RetVT));
2074 Ops.push_back(InFlag);
2075 Chain = DAG.getNode(X86ISD::FST, Tys, &Ops[0], Ops.size());
2076 RetVal = DAG.getLoad(RetVT, Chain, StackSlot, NULL, 0);
2077 Chain = RetVal.getValue(1);
2080 if (RetVT == MVT::f32 && !X86ScalarSSE)
2081 // FIXME: we would really like to remember that this FP_ROUND
2082 // operation is okay to eliminate if we allow excess FP precision.
2083 RetVal = DAG.getNode(ISD::FP_ROUND, MVT::f32, RetVal);
2084 ResultVals.push_back(RetVal);
2085 NodeTys.push_back(RetVT);
2090 // If the function returns void, just return the chain.
2091 if (ResultVals.empty())
2094 // Otherwise, merge everything together with a MERGE_VALUES node.
2095 NodeTys.push_back(MVT::Other);
2096 ResultVals.push_back(Chain);
2097 SDOperand Res = DAG.getNode(ISD::MERGE_VALUES, NodeTys,
2098 &ResultVals[0], ResultVals.size());
2099 return Res.getValue(Op.ResNo);
2102 //===----------------------------------------------------------------------===//
2103 // FastCall Calling Convention implementation
2104 //===----------------------------------------------------------------------===//
2106 // The X86 'fastcall' calling convention passes up to two integer arguments in
2107 // registers (an appropriate portion of ECX/EDX), passes arguments in C order,
2108 // and requires that the callee pop its arguments off the stack (allowing proper
2109 // tail calls), and has the same return value conventions as C calling convs.
2111 // This calling convention always arranges for the callee pop value to be 8n+4
2112 // bytes, which is needed for tail recursion elimination and stack alignment
2116 /// HowToPassFastCallCCArgument - Returns how an formal argument of the
2117 /// specified type should be passed. If it is through stack, returns the size of
2118 /// the stack slot; if it is through integer register, returns the number of
2119 /// integer registers are needed.
2121 HowToPassFastCallCCArgument(MVT::ValueType ObjectVT,
2122 unsigned NumIntRegs,
2124 unsigned &ObjIntRegs)
2130 default: assert(0 && "Unhandled argument type!");
2150 if (NumIntRegs+2 <= 2) {
2152 } else if (NumIntRegs+1 <= 2) {
2167 X86TargetLowering::LowerFastCallCCArguments(SDOperand Op, SelectionDAG &DAG) {
2168 unsigned NumArgs = Op.Val->getNumValues()-1;
2169 MachineFunction &MF = DAG.getMachineFunction();
2170 MachineFrameInfo *MFI = MF.getFrameInfo();
2171 SDOperand Root = Op.getOperand(0);
2172 std::vector<SDOperand> ArgValues;
2174 // Add DAG nodes to load the arguments... On entry to a function the stack
2175 // frame looks like this:
2177 // [ESP] -- return address
2178 // [ESP + 4] -- first nonreg argument (leftmost lexically)
2179 // [ESP + 8] -- second nonreg argument, if 1st argument is <= 4 bytes in size
2181 unsigned ArgOffset = 0; // Frame mechanisms handle retaddr slot
2183 // Keep track of the number of integer regs passed so far. This can be either
2184 // 0 (neither ECX or EDX used), 1 (ECX is used) or 2 (ECX and EDX are both
2186 unsigned NumIntRegs = 0;
2188 for (unsigned i = 0; i < NumArgs; ++i) {
2189 MVT::ValueType ObjectVT = Op.getValue(i).getValueType();
2190 unsigned ArgIncrement = 4;
2191 unsigned ObjSize = 0;
2192 unsigned ObjIntRegs = 0;
2194 HowToPassFastCallCCArgument(ObjectVT, NumIntRegs, ObjSize, ObjIntRegs);
2196 ArgIncrement = ObjSize;
2202 default: assert(0 && "Unhandled argument type!");
2204 Reg = AddLiveIn(MF, NumIntRegs ? X86::DL : X86::CL,
2205 X86::GR8RegisterClass);
2206 ArgValue = DAG.getCopyFromReg(Root, Reg, MVT::i8);
2209 Reg = AddLiveIn(MF, NumIntRegs ? X86::DX : X86::CX,
2210 X86::GR16RegisterClass);
2211 ArgValue = DAG.getCopyFromReg(Root, Reg, MVT::i16);
2214 Reg = AddLiveIn(MF, NumIntRegs ? X86::EDX : X86::ECX,
2215 X86::GR32RegisterClass);
2216 ArgValue = DAG.getCopyFromReg(Root, Reg, MVT::i32);
2219 Reg = AddLiveIn(MF, NumIntRegs ? X86::EDX : X86::ECX,
2220 X86::GR32RegisterClass);
2221 ArgValue = DAG.getCopyFromReg(Root, Reg, MVT::i32);
2222 if (ObjIntRegs == 2) {
2223 Reg = AddLiveIn(MF, X86::EDX, X86::GR32RegisterClass);
2224 SDOperand ArgValue2 = DAG.getCopyFromReg(Root, Reg, MVT::i32);
2225 ArgValue= DAG.getNode(ISD::BUILD_PAIR, MVT::i64, ArgValue, ArgValue2);
2230 NumIntRegs += ObjIntRegs;
2234 // Create the SelectionDAG nodes corresponding to a load from this
2236 int FI = MFI->CreateFixedObject(ObjSize, ArgOffset);
2237 SDOperand FIN = DAG.getFrameIndex(FI, getPointerTy());
2238 if (ObjectVT == MVT::i64 && ObjIntRegs) {
2239 SDOperand ArgValue2 = DAG.getLoad(Op.Val->getValueType(i), Root, FIN,
2241 ArgValue = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, ArgValue, ArgValue2);
2243 ArgValue = DAG.getLoad(Op.Val->getValueType(i), Root, FIN, NULL, 0);
2244 ArgOffset += ArgIncrement; // Move on to the next argument.
2247 ArgValues.push_back(ArgValue);
2250 ArgValues.push_back(Root);
2252 // Make sure the instruction takes 8n+4 bytes to make sure the start of the
2253 // arguments and the arguments after the retaddr has been pushed are aligned.
2254 if ((ArgOffset & 7) == 0)
2257 VarArgsFrameIndex = 0xAAAAAAA; // fastcc functions can't have varargs.
2258 RegSaveFrameIndex = 0xAAAAAAA; // X86-64 only.
2259 ReturnAddrIndex = 0; // No return address slot generated yet.
2260 BytesToPopOnReturn = ArgOffset; // Callee pops all stack arguments.
2261 BytesCallerReserves = 0;
2263 MF.getInfo<X86FunctionInfo>()->setBytesToPopOnReturn(BytesToPopOnReturn);
2265 // Finally, inform the code generator which regs we return values in.
2266 switch (getValueType(MF.getFunction()->getReturnType())) {
2267 default: assert(0 && "Unknown type!");
2268 case MVT::isVoid: break;
2273 MF.addLiveOut(X86::ECX);
2276 MF.addLiveOut(X86::ECX);
2277 MF.addLiveOut(X86::EDX);
2281 MF.addLiveOut(X86::ST0);
2285 // Return the new list of results.
2286 std::vector<MVT::ValueType> RetVTs(Op.Val->value_begin(),
2287 Op.Val->value_end());
2288 return DAG.getNode(ISD::MERGE_VALUES, RetVTs, &ArgValues[0],ArgValues.size());
2291 SDOperand X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) {
2292 if (ReturnAddrIndex == 0) {
2293 // Set up a frame object for the return address.
2294 MachineFunction &MF = DAG.getMachineFunction();
2295 if (Subtarget->is64Bit())
2296 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(8, -8);
2298 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(4, -4);
2301 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
2306 std::pair<SDOperand, SDOperand> X86TargetLowering::
2307 LowerFrameReturnAddress(bool isFrameAddress, SDOperand Chain, unsigned Depth,
2308 SelectionDAG &DAG) {
2310 if (Depth) // Depths > 0 not supported yet!
2311 Result = DAG.getConstant(0, getPointerTy());
2313 SDOperand RetAddrFI = getReturnAddressFrameIndex(DAG);
2314 if (!isFrameAddress)
2315 // Just load the return address
2316 Result = DAG.getLoad(getPointerTy(), DAG.getEntryNode(), RetAddrFI,
2319 Result = DAG.getNode(ISD::SUB, getPointerTy(), RetAddrFI,
2320 DAG.getConstant(4, getPointerTy()));
2322 return std::make_pair(Result, Chain);
2325 /// translateX86CC - do a one to one translation of a ISD::CondCode to the X86
2326 /// specific condition code. It returns a false if it cannot do a direct
2327 /// translation. X86CC is the translated CondCode. LHS/RHS are modified as
2329 static bool translateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
2330 unsigned &X86CC, SDOperand &LHS, SDOperand &RHS,
2331 SelectionDAG &DAG) {
2332 X86CC = X86::COND_INVALID;
2334 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
2335 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
2336 // X > -1 -> X == 0, jump !sign.
2337 RHS = DAG.getConstant(0, RHS.getValueType());
2338 X86CC = X86::COND_NS;
2340 } else if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
2341 // X < 0 -> X == 0, jump on sign.
2342 X86CC = X86::COND_S;
2347 switch (SetCCOpcode) {
2349 case ISD::SETEQ: X86CC = X86::COND_E; break;
2350 case ISD::SETGT: X86CC = X86::COND_G; break;
2351 case ISD::SETGE: X86CC = X86::COND_GE; break;
2352 case ISD::SETLT: X86CC = X86::COND_L; break;
2353 case ISD::SETLE: X86CC = X86::COND_LE; break;
2354 case ISD::SETNE: X86CC = X86::COND_NE; break;
2355 case ISD::SETULT: X86CC = X86::COND_B; break;
2356 case ISD::SETUGT: X86CC = X86::COND_A; break;
2357 case ISD::SETULE: X86CC = X86::COND_BE; break;
2358 case ISD::SETUGE: X86CC = X86::COND_AE; break;
2361 // On a floating point condition, the flags are set as follows:
2363 // 0 | 0 | 0 | X > Y
2364 // 0 | 0 | 1 | X < Y
2365 // 1 | 0 | 0 | X == Y
2366 // 1 | 1 | 1 | unordered
2368 switch (SetCCOpcode) {
2371 case ISD::SETEQ: X86CC = X86::COND_E; break;
2372 case ISD::SETOLT: Flip = true; // Fallthrough
2374 case ISD::SETGT: X86CC = X86::COND_A; break;
2375 case ISD::SETOLE: Flip = true; // Fallthrough
2377 case ISD::SETGE: X86CC = X86::COND_AE; break;
2378 case ISD::SETUGT: Flip = true; // Fallthrough
2380 case ISD::SETLT: X86CC = X86::COND_B; break;
2381 case ISD::SETUGE: Flip = true; // Fallthrough
2383 case ISD::SETLE: X86CC = X86::COND_BE; break;
2385 case ISD::SETNE: X86CC = X86::COND_NE; break;
2386 case ISD::SETUO: X86CC = X86::COND_P; break;
2387 case ISD::SETO: X86CC = X86::COND_NP; break;
2390 std::swap(LHS, RHS);
2393 return X86CC != X86::COND_INVALID;
2396 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
2397 /// code. Current x86 isa includes the following FP cmov instructions:
2398 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
2399 static bool hasFPCMov(unsigned X86CC) {
2415 /// DarwinGVRequiresExtraLoad - true if accessing the GV requires an extra
2416 /// load. For Darwin, external and weak symbols are indirect, loading the value
2417 /// at address GV rather then the value of GV itself. This means that the
2418 /// GlobalAddress must be in the base or index register of the address, not the
2419 /// GV offset field.
2420 static bool DarwinGVRequiresExtraLoad(GlobalValue *GV) {
2421 return (GV->hasWeakLinkage() || GV->hasLinkOnceLinkage() ||
2422 (GV->isExternal() && !GV->hasNotBeenReadFromBytecode()));
2425 /// WindowsGVRequiresExtraLoad - true if accessing the GV requires an extra
2426 /// load. For Windows, dllimported symbols are indirect, loading the value at
2427 /// address GV rather then the value of GV itself. This means that the
2428 /// GlobalAddress must be in the base or index register of the address, not the
2429 /// GV offset field.
2430 static bool WindowsGVRequiresExtraLoad(GlobalValue *GV) {
2431 return (GV->hasDLLImportLinkage());
2434 /// isUndefOrInRange - Op is either an undef node or a ConstantSDNode. Return
2435 /// true if Op is undef or if its value falls within the specified range (L, H].
2436 static bool isUndefOrInRange(SDOperand Op, unsigned Low, unsigned Hi) {
2437 if (Op.getOpcode() == ISD::UNDEF)
2440 unsigned Val = cast<ConstantSDNode>(Op)->getValue();
2441 return (Val >= Low && Val < Hi);
2444 /// isUndefOrEqual - Op is either an undef node or a ConstantSDNode. Return
2445 /// true if Op is undef or if its value equal to the specified value.
2446 static bool isUndefOrEqual(SDOperand Op, unsigned Val) {
2447 if (Op.getOpcode() == ISD::UNDEF)
2449 return cast<ConstantSDNode>(Op)->getValue() == Val;
2452 /// isPSHUFDMask - Return true if the specified VECTOR_SHUFFLE operand
2453 /// specifies a shuffle of elements that is suitable for input to PSHUFD.
2454 bool X86::isPSHUFDMask(SDNode *N) {
2455 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2457 if (N->getNumOperands() != 4)
2460 // Check if the value doesn't reference the second vector.
2461 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
2462 SDOperand Arg = N->getOperand(i);
2463 if (Arg.getOpcode() == ISD::UNDEF) continue;
2464 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2465 if (cast<ConstantSDNode>(Arg)->getValue() >= 4)
2472 /// isPSHUFHWMask - Return true if the specified VECTOR_SHUFFLE operand
2473 /// specifies a shuffle of elements that is suitable for input to PSHUFHW.
2474 bool X86::isPSHUFHWMask(SDNode *N) {
2475 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2477 if (N->getNumOperands() != 8)
2480 // Lower quadword copied in order.
2481 for (unsigned i = 0; i != 4; ++i) {
2482 SDOperand Arg = N->getOperand(i);
2483 if (Arg.getOpcode() == ISD::UNDEF) continue;
2484 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2485 if (cast<ConstantSDNode>(Arg)->getValue() != i)
2489 // Upper quadword shuffled.
2490 for (unsigned i = 4; i != 8; ++i) {
2491 SDOperand Arg = N->getOperand(i);
2492 if (Arg.getOpcode() == ISD::UNDEF) continue;
2493 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2494 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
2495 if (Val < 4 || Val > 7)
2502 /// isPSHUFLWMask - Return true if the specified VECTOR_SHUFFLE operand
2503 /// specifies a shuffle of elements that is suitable for input to PSHUFLW.
2504 bool X86::isPSHUFLWMask(SDNode *N) {
2505 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2507 if (N->getNumOperands() != 8)
2510 // Upper quadword copied in order.
2511 for (unsigned i = 4; i != 8; ++i)
2512 if (!isUndefOrEqual(N->getOperand(i), i))
2515 // Lower quadword shuffled.
2516 for (unsigned i = 0; i != 4; ++i)
2517 if (!isUndefOrInRange(N->getOperand(i), 0, 4))
2523 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
2524 /// specifies a shuffle of elements that is suitable for input to SHUFP*.
2525 static bool isSHUFPMask(std::vector<SDOperand> &N) {
2526 unsigned NumElems = N.size();
2527 if (NumElems != 2 && NumElems != 4) return false;
2529 unsigned Half = NumElems / 2;
2530 for (unsigned i = 0; i < Half; ++i)
2531 if (!isUndefOrInRange(N[i], 0, NumElems))
2533 for (unsigned i = Half; i < NumElems; ++i)
2534 if (!isUndefOrInRange(N[i], NumElems, NumElems*2))
2540 bool X86::isSHUFPMask(SDNode *N) {
2541 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2542 std::vector<SDOperand> Ops(N->op_begin(), N->op_end());
2543 return ::isSHUFPMask(Ops);
2546 /// isCommutedSHUFP - Returns true if the shuffle mask is except
2547 /// the reverse of what x86 shuffles want. x86 shuffles requires the lower
2548 /// half elements to come from vector 1 (which would equal the dest.) and
2549 /// the upper half to come from vector 2.
2550 static bool isCommutedSHUFP(std::vector<SDOperand> &Ops) {
2551 unsigned NumElems = Ops.size();
2552 if (NumElems != 2 && NumElems != 4) return false;
2554 unsigned Half = NumElems / 2;
2555 for (unsigned i = 0; i < Half; ++i)
2556 if (!isUndefOrInRange(Ops[i], NumElems, NumElems*2))
2558 for (unsigned i = Half; i < NumElems; ++i)
2559 if (!isUndefOrInRange(Ops[i], 0, NumElems))
2564 static bool isCommutedSHUFP(SDNode *N) {
2565 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2566 std::vector<SDOperand> Ops(N->op_begin(), N->op_end());
2567 return isCommutedSHUFP(Ops);
2570 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
2571 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
2572 bool X86::isMOVHLPSMask(SDNode *N) {
2573 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2575 if (N->getNumOperands() != 4)
2578 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3
2579 return isUndefOrEqual(N->getOperand(0), 6) &&
2580 isUndefOrEqual(N->getOperand(1), 7) &&
2581 isUndefOrEqual(N->getOperand(2), 2) &&
2582 isUndefOrEqual(N->getOperand(3), 3);
2585 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
2586 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
2588 bool X86::isMOVHLPS_v_undef_Mask(SDNode *N) {
2589 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2591 if (N->getNumOperands() != 4)
2594 // Expect bit0 == 2, bit1 == 3, bit2 == 2, bit3 == 3
2595 return isUndefOrEqual(N->getOperand(0), 2) &&
2596 isUndefOrEqual(N->getOperand(1), 3) &&
2597 isUndefOrEqual(N->getOperand(2), 2) &&
2598 isUndefOrEqual(N->getOperand(3), 3);
2601 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
2602 /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
2603 bool X86::isMOVLPMask(SDNode *N) {
2604 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2606 unsigned NumElems = N->getNumOperands();
2607 if (NumElems != 2 && NumElems != 4)
2610 for (unsigned i = 0; i < NumElems/2; ++i)
2611 if (!isUndefOrEqual(N->getOperand(i), i + NumElems))
2614 for (unsigned i = NumElems/2; i < NumElems; ++i)
2615 if (!isUndefOrEqual(N->getOperand(i), i))
2621 /// isMOVHPMask - Return true if the specified VECTOR_SHUFFLE operand
2622 /// specifies a shuffle of elements that is suitable for input to MOVHP{S|D}
2624 bool X86::isMOVHPMask(SDNode *N) {
2625 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2627 unsigned NumElems = N->getNumOperands();
2628 if (NumElems != 2 && NumElems != 4)
2631 for (unsigned i = 0; i < NumElems/2; ++i)
2632 if (!isUndefOrEqual(N->getOperand(i), i))
2635 for (unsigned i = 0; i < NumElems/2; ++i) {
2636 SDOperand Arg = N->getOperand(i + NumElems/2);
2637 if (!isUndefOrEqual(Arg, i + NumElems))
2644 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
2645 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
2646 bool static isUNPCKLMask(std::vector<SDOperand> &N, bool V2IsSplat = false) {
2647 unsigned NumElems = N.size();
2648 if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16)
2651 for (unsigned i = 0, j = 0; i != NumElems; i += 2, ++j) {
2652 SDOperand BitI = N[i];
2653 SDOperand BitI1 = N[i+1];
2654 if (!isUndefOrEqual(BitI, j))
2657 if (isUndefOrEqual(BitI1, NumElems))
2660 if (!isUndefOrEqual(BitI1, j + NumElems))
2668 bool X86::isUNPCKLMask(SDNode *N, bool V2IsSplat) {
2669 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2670 std::vector<SDOperand> Ops(N->op_begin(), N->op_end());
2671 return ::isUNPCKLMask(Ops, V2IsSplat);
2674 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
2675 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
2676 bool static isUNPCKHMask(std::vector<SDOperand> &N, bool V2IsSplat = false) {
2677 unsigned NumElems = N.size();
2678 if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16)
2681 for (unsigned i = 0, j = 0; i != NumElems; i += 2, ++j) {
2682 SDOperand BitI = N[i];
2683 SDOperand BitI1 = N[i+1];
2684 if (!isUndefOrEqual(BitI, j + NumElems/2))
2687 if (isUndefOrEqual(BitI1, NumElems))
2690 if (!isUndefOrEqual(BitI1, j + NumElems/2 + NumElems))
2698 bool X86::isUNPCKHMask(SDNode *N, bool V2IsSplat) {
2699 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2700 std::vector<SDOperand> Ops(N->op_begin(), N->op_end());
2701 return ::isUNPCKHMask(Ops, V2IsSplat);
2704 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
2705 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
2707 bool X86::isUNPCKL_v_undef_Mask(SDNode *N) {
2708 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2710 unsigned NumElems = N->getNumOperands();
2711 if (NumElems != 4 && NumElems != 8 && NumElems != 16)
2714 for (unsigned i = 0, j = 0; i != NumElems; i += 2, ++j) {
2715 SDOperand BitI = N->getOperand(i);
2716 SDOperand BitI1 = N->getOperand(i+1);
2718 if (!isUndefOrEqual(BitI, j))
2720 if (!isUndefOrEqual(BitI1, j))
2727 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
2728 /// specifies a shuffle of elements that is suitable for input to MOVSS,
2729 /// MOVSD, and MOVD, i.e. setting the lowest element.
2730 static bool isMOVLMask(std::vector<SDOperand> &N) {
2731 unsigned NumElems = N.size();
2732 if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16)
2735 if (!isUndefOrEqual(N[0], NumElems))
2738 for (unsigned i = 1; i < NumElems; ++i) {
2739 SDOperand Arg = N[i];
2740 if (!isUndefOrEqual(Arg, i))
2747 bool X86::isMOVLMask(SDNode *N) {
2748 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2749 std::vector<SDOperand> Ops(N->op_begin(), N->op_end());
2750 return ::isMOVLMask(Ops);
2753 /// isCommutedMOVL - Returns true if the shuffle mask is except the reverse
2754 /// of what x86 movss want. X86 movs requires the lowest element to be lowest
2755 /// element of vector 2 and the other elements to come from vector 1 in order.
2756 static bool isCommutedMOVL(std::vector<SDOperand> &Ops, bool V2IsSplat = false,
2757 bool V2IsUndef = false) {
2758 unsigned NumElems = Ops.size();
2759 if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16)
2762 if (!isUndefOrEqual(Ops[0], 0))
2765 for (unsigned i = 1; i < NumElems; ++i) {
2766 SDOperand Arg = Ops[i];
2767 if (!(isUndefOrEqual(Arg, i+NumElems) ||
2768 (V2IsUndef && isUndefOrInRange(Arg, NumElems, NumElems*2)) ||
2769 (V2IsSplat && isUndefOrEqual(Arg, NumElems))))
2776 static bool isCommutedMOVL(SDNode *N, bool V2IsSplat = false,
2777 bool V2IsUndef = false) {
2778 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2779 std::vector<SDOperand> Ops(N->op_begin(), N->op_end());
2780 return isCommutedMOVL(Ops, V2IsSplat, V2IsUndef);
2783 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
2784 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
2785 bool X86::isMOVSHDUPMask(SDNode *N) {
2786 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2788 if (N->getNumOperands() != 4)
2791 // Expect 1, 1, 3, 3
2792 for (unsigned i = 0; i < 2; ++i) {
2793 SDOperand Arg = N->getOperand(i);
2794 if (Arg.getOpcode() == ISD::UNDEF) continue;
2795 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2796 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
2797 if (Val != 1) return false;
2801 for (unsigned i = 2; i < 4; ++i) {
2802 SDOperand Arg = N->getOperand(i);
2803 if (Arg.getOpcode() == ISD::UNDEF) continue;
2804 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2805 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
2806 if (Val != 3) return false;
2810 // Don't use movshdup if it can be done with a shufps.
2814 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
2815 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
2816 bool X86::isMOVSLDUPMask(SDNode *N) {
2817 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2819 if (N->getNumOperands() != 4)
2822 // Expect 0, 0, 2, 2
2823 for (unsigned i = 0; i < 2; ++i) {
2824 SDOperand Arg = N->getOperand(i);
2825 if (Arg.getOpcode() == ISD::UNDEF) continue;
2826 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2827 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
2828 if (Val != 0) return false;
2832 for (unsigned i = 2; i < 4; ++i) {
2833 SDOperand Arg = N->getOperand(i);
2834 if (Arg.getOpcode() == ISD::UNDEF) continue;
2835 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2836 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
2837 if (Val != 2) return false;
2841 // Don't use movshdup if it can be done with a shufps.
2845 /// isSplatMask - Return true if the specified VECTOR_SHUFFLE operand specifies
2846 /// a splat of a single element.
2847 static bool isSplatMask(SDNode *N) {
2848 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2850 // This is a splat operation if each element of the permute is the same, and
2851 // if the value doesn't reference the second vector.
2852 unsigned NumElems = N->getNumOperands();
2853 SDOperand ElementBase;
2855 for (; i != NumElems; ++i) {
2856 SDOperand Elt = N->getOperand(i);
2857 if (isa<ConstantSDNode>(Elt)) {
2863 if (!ElementBase.Val)
2866 for (; i != NumElems; ++i) {
2867 SDOperand Arg = N->getOperand(i);
2868 if (Arg.getOpcode() == ISD::UNDEF) continue;
2869 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2870 if (Arg != ElementBase) return false;
2873 // Make sure it is a splat of the first vector operand.
2874 return cast<ConstantSDNode>(ElementBase)->getValue() < NumElems;
2877 /// isSplatMask - Return true if the specified VECTOR_SHUFFLE operand specifies
2878 /// a splat of a single element and it's a 2 or 4 element mask.
2879 bool X86::isSplatMask(SDNode *N) {
2880 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2882 // We can only splat 64-bit, and 32-bit quantities with a single instruction.
2883 if (N->getNumOperands() != 4 && N->getNumOperands() != 2)
2885 return ::isSplatMask(N);
2888 /// isSplatLoMask - Return true if the specified VECTOR_SHUFFLE operand
2889 /// specifies a splat of zero element.
2890 bool X86::isSplatLoMask(SDNode *N) {
2891 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2893 for (unsigned i = 0, e = N->getNumOperands(); i < e; ++i)
2894 if (!isUndefOrEqual(N->getOperand(i), 0))
2899 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
2900 /// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUF* and SHUFP*
2902 unsigned X86::getShuffleSHUFImmediate(SDNode *N) {
2903 unsigned NumOperands = N->getNumOperands();
2904 unsigned Shift = (NumOperands == 4) ? 2 : 1;
2906 for (unsigned i = 0; i < NumOperands; ++i) {
2908 SDOperand Arg = N->getOperand(NumOperands-i-1);
2909 if (Arg.getOpcode() != ISD::UNDEF)
2910 Val = cast<ConstantSDNode>(Arg)->getValue();
2911 if (Val >= NumOperands) Val -= NumOperands;
2913 if (i != NumOperands - 1)
2920 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
2921 /// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUFHW
2923 unsigned X86::getShufflePSHUFHWImmediate(SDNode *N) {
2925 // 8 nodes, but we only care about the last 4.
2926 for (unsigned i = 7; i >= 4; --i) {
2928 SDOperand Arg = N->getOperand(i);
2929 if (Arg.getOpcode() != ISD::UNDEF)
2930 Val = cast<ConstantSDNode>(Arg)->getValue();
2939 /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
2940 /// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUFLW
2942 unsigned X86::getShufflePSHUFLWImmediate(SDNode *N) {
2944 // 8 nodes, but we only care about the first 4.
2945 for (int i = 3; i >= 0; --i) {
2947 SDOperand Arg = N->getOperand(i);
2948 if (Arg.getOpcode() != ISD::UNDEF)
2949 Val = cast<ConstantSDNode>(Arg)->getValue();
2958 /// isPSHUFHW_PSHUFLWMask - true if the specified VECTOR_SHUFFLE operand
2959 /// specifies a 8 element shuffle that can be broken into a pair of
2960 /// PSHUFHW and PSHUFLW.
2961 static bool isPSHUFHW_PSHUFLWMask(SDNode *N) {
2962 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2964 if (N->getNumOperands() != 8)
2967 // Lower quadword shuffled.
2968 for (unsigned i = 0; i != 4; ++i) {
2969 SDOperand Arg = N->getOperand(i);
2970 if (Arg.getOpcode() == ISD::UNDEF) continue;
2971 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2972 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
2977 // Upper quadword shuffled.
2978 for (unsigned i = 4; i != 8; ++i) {
2979 SDOperand Arg = N->getOperand(i);
2980 if (Arg.getOpcode() == ISD::UNDEF) continue;
2981 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2982 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
2983 if (Val < 4 || Val > 7)
2990 /// CommuteVectorShuffle - Swap vector_shuffle operandsas well as
2991 /// values in ther permute mask.
2992 static SDOperand CommuteVectorShuffle(SDOperand Op, SDOperand &V1,
2993 SDOperand &V2, SDOperand &Mask,
2994 SelectionDAG &DAG) {
2995 MVT::ValueType VT = Op.getValueType();
2996 MVT::ValueType MaskVT = Mask.getValueType();
2997 MVT::ValueType EltVT = MVT::getVectorBaseType(MaskVT);
2998 unsigned NumElems = Mask.getNumOperands();
2999 std::vector<SDOperand> MaskVec;
3001 for (unsigned i = 0; i != NumElems; ++i) {
3002 SDOperand Arg = Mask.getOperand(i);
3003 if (Arg.getOpcode() == ISD::UNDEF) {
3004 MaskVec.push_back(DAG.getNode(ISD::UNDEF, EltVT));
3007 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
3008 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
3010 MaskVec.push_back(DAG.getConstant(Val + NumElems, EltVT));
3012 MaskVec.push_back(DAG.getConstant(Val - NumElems, EltVT));
3016 Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], MaskVec.size());
3017 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, Mask);
3020 /// ShouldXformToMOVHLPS - Return true if the node should be transformed to
3021 /// match movhlps. The lower half elements should come from upper half of
3022 /// V1 (and in order), and the upper half elements should come from the upper
3023 /// half of V2 (and in order).
3024 static bool ShouldXformToMOVHLPS(SDNode *Mask) {
3025 unsigned NumElems = Mask->getNumOperands();
3028 for (unsigned i = 0, e = 2; i != e; ++i)
3029 if (!isUndefOrEqual(Mask->getOperand(i), i+2))
3031 for (unsigned i = 2; i != 4; ++i)
3032 if (!isUndefOrEqual(Mask->getOperand(i), i+4))
3037 /// isScalarLoadToVector - Returns true if the node is a scalar load that
3038 /// is promoted to a vector.
3039 static inline bool isScalarLoadToVector(SDNode *N) {
3040 if (N->getOpcode() == ISD::SCALAR_TO_VECTOR) {
3041 N = N->getOperand(0).Val;
3042 return ISD::isNON_EXTLoad(N);
3047 /// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to
3048 /// match movlp{s|d}. The lower half elements should come from lower half of
3049 /// V1 (and in order), and the upper half elements should come from the upper
3050 /// half of V2 (and in order). And since V1 will become the source of the
3051 /// MOVLP, it must be either a vector load or a scalar load to vector.
3052 static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2, SDNode *Mask) {
3053 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1))
3055 // Is V2 is a vector load, don't do this transformation. We will try to use
3056 // load folding shufps op.
3057 if (ISD::isNON_EXTLoad(V2))
3060 unsigned NumElems = Mask->getNumOperands();
3061 if (NumElems != 2 && NumElems != 4)
3063 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
3064 if (!isUndefOrEqual(Mask->getOperand(i), i))
3066 for (unsigned i = NumElems/2; i != NumElems; ++i)
3067 if (!isUndefOrEqual(Mask->getOperand(i), i+NumElems))
3072 /// isSplatVector - Returns true if N is a BUILD_VECTOR node whose elements are
3074 static bool isSplatVector(SDNode *N) {
3075 if (N->getOpcode() != ISD::BUILD_VECTOR)
3078 SDOperand SplatValue = N->getOperand(0);
3079 for (unsigned i = 1, e = N->getNumOperands(); i != e; ++i)
3080 if (N->getOperand(i) != SplatValue)
3085 /// isUndefShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
3087 static bool isUndefShuffle(SDNode *N) {
3088 if (N->getOpcode() != ISD::BUILD_VECTOR)
3091 SDOperand V1 = N->getOperand(0);
3092 SDOperand V2 = N->getOperand(1);
3093 SDOperand Mask = N->getOperand(2);
3094 unsigned NumElems = Mask.getNumOperands();
3095 for (unsigned i = 0; i != NumElems; ++i) {
3096 SDOperand Arg = Mask.getOperand(i);
3097 if (Arg.getOpcode() != ISD::UNDEF) {
3098 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
3099 if (Val < NumElems && V1.getOpcode() != ISD::UNDEF)
3101 else if (Val >= NumElems && V2.getOpcode() != ISD::UNDEF)
3108 /// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements
3109 /// that point to V2 points to its first element.
3110 static SDOperand NormalizeMask(SDOperand Mask, SelectionDAG &DAG) {
3111 assert(Mask.getOpcode() == ISD::BUILD_VECTOR);
3113 bool Changed = false;
3114 std::vector<SDOperand> MaskVec;
3115 unsigned NumElems = Mask.getNumOperands();
3116 for (unsigned i = 0; i != NumElems; ++i) {
3117 SDOperand Arg = Mask.getOperand(i);
3118 if (Arg.getOpcode() != ISD::UNDEF) {
3119 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
3120 if (Val > NumElems) {
3121 Arg = DAG.getConstant(NumElems, Arg.getValueType());
3125 MaskVec.push_back(Arg);
3129 Mask = DAG.getNode(ISD::BUILD_VECTOR, Mask.getValueType(),
3130 &MaskVec[0], MaskVec.size());
3134 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
3135 /// operation of specified width.
3136 static SDOperand getMOVLMask(unsigned NumElems, SelectionDAG &DAG) {
3137 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(NumElems);
3138 MVT::ValueType BaseVT = MVT::getVectorBaseType(MaskVT);
3140 std::vector<SDOperand> MaskVec;
3141 MaskVec.push_back(DAG.getConstant(NumElems, BaseVT));
3142 for (unsigned i = 1; i != NumElems; ++i)
3143 MaskVec.push_back(DAG.getConstant(i, BaseVT));
3144 return DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], MaskVec.size());
3147 /// getUnpacklMask - Returns a vector_shuffle mask for an unpackl operation
3148 /// of specified width.
3149 static SDOperand getUnpacklMask(unsigned NumElems, SelectionDAG &DAG) {
3150 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(NumElems);
3151 MVT::ValueType BaseVT = MVT::getVectorBaseType(MaskVT);
3152 std::vector<SDOperand> MaskVec;
3153 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
3154 MaskVec.push_back(DAG.getConstant(i, BaseVT));
3155 MaskVec.push_back(DAG.getConstant(i + NumElems, BaseVT));
3157 return DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], MaskVec.size());
3160 /// getUnpackhMask - Returns a vector_shuffle mask for an unpackh operation
3161 /// of specified width.
3162 static SDOperand getUnpackhMask(unsigned NumElems, SelectionDAG &DAG) {
3163 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(NumElems);
3164 MVT::ValueType BaseVT = MVT::getVectorBaseType(MaskVT);
3165 unsigned Half = NumElems/2;
3166 std::vector<SDOperand> MaskVec;
3167 for (unsigned i = 0; i != Half; ++i) {
3168 MaskVec.push_back(DAG.getConstant(i + Half, BaseVT));
3169 MaskVec.push_back(DAG.getConstant(i + NumElems + Half, BaseVT));
3171 return DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], MaskVec.size());
3174 /// getZeroVector - Returns a vector of specified type with all zero elements.
3176 static SDOperand getZeroVector(MVT::ValueType VT, SelectionDAG &DAG) {
3177 assert(MVT::isVector(VT) && "Expected a vector type");
3178 unsigned NumElems = getVectorNumElements(VT);
3179 MVT::ValueType EVT = MVT::getVectorBaseType(VT);
3180 bool isFP = MVT::isFloatingPoint(EVT);
3181 SDOperand Zero = isFP ? DAG.getConstantFP(0.0, EVT) : DAG.getConstant(0, EVT);
3182 std::vector<SDOperand> ZeroVec(NumElems, Zero);
3183 return DAG.getNode(ISD::BUILD_VECTOR, VT, &ZeroVec[0], ZeroVec.size());
3186 /// PromoteSplat - Promote a splat of v8i16 or v16i8 to v4i32.
3188 static SDOperand PromoteSplat(SDOperand Op, SelectionDAG &DAG) {
3189 SDOperand V1 = Op.getOperand(0);
3190 SDOperand Mask = Op.getOperand(2);
3191 MVT::ValueType VT = Op.getValueType();
3192 unsigned NumElems = Mask.getNumOperands();
3193 Mask = getUnpacklMask(NumElems, DAG);
3194 while (NumElems != 4) {
3195 V1 = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V1, Mask);
3198 V1 = DAG.getNode(ISD::BIT_CONVERT, MVT::v4i32, V1);
3200 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(4);
3201 Mask = getZeroVector(MaskVT, DAG);
3202 SDOperand Shuffle = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v4i32, V1,
3203 DAG.getNode(ISD::UNDEF, MVT::v4i32), Mask);
3204 return DAG.getNode(ISD::BIT_CONVERT, VT, Shuffle);
3207 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
3209 static inline bool isZeroNode(SDOperand Elt) {
3210 return ((isa<ConstantSDNode>(Elt) &&
3211 cast<ConstantSDNode>(Elt)->getValue() == 0) ||
3212 (isa<ConstantFPSDNode>(Elt) &&
3213 cast<ConstantFPSDNode>(Elt)->isExactlyValue(0.0)));
3216 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
3217 /// vector and zero or undef vector.
3218 static SDOperand getShuffleVectorZeroOrUndef(SDOperand V2, MVT::ValueType VT,
3219 unsigned NumElems, unsigned Idx,
3220 bool isZero, SelectionDAG &DAG) {
3221 SDOperand V1 = isZero ? getZeroVector(VT, DAG) : DAG.getNode(ISD::UNDEF, VT);
3222 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(NumElems);
3223 MVT::ValueType EVT = MVT::getVectorBaseType(MaskVT);
3224 SDOperand Zero = DAG.getConstant(0, EVT);
3225 std::vector<SDOperand> MaskVec(NumElems, Zero);
3226 MaskVec[Idx] = DAG.getConstant(NumElems, EVT);
3227 SDOperand Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3228 &MaskVec[0], MaskVec.size());
3229 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, Mask);
3232 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
3234 static SDOperand LowerBuildVectorv16i8(SDOperand Op, unsigned NonZeros,
3235 unsigned NumNonZero, unsigned NumZero,
3236 SelectionDAG &DAG, TargetLowering &TLI) {
3242 for (unsigned i = 0; i < 16; ++i) {
3243 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
3244 if (ThisIsNonZero && First) {
3246 V = getZeroVector(MVT::v8i16, DAG);
3248 V = DAG.getNode(ISD::UNDEF, MVT::v8i16);
3253 SDOperand ThisElt(0, 0), LastElt(0, 0);
3254 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
3255 if (LastIsNonZero) {
3256 LastElt = DAG.getNode(ISD::ZERO_EXTEND, MVT::i16, Op.getOperand(i-1));
3258 if (ThisIsNonZero) {
3259 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, MVT::i16, Op.getOperand(i));
3260 ThisElt = DAG.getNode(ISD::SHL, MVT::i16,
3261 ThisElt, DAG.getConstant(8, MVT::i8));
3263 ThisElt = DAG.getNode(ISD::OR, MVT::i16, ThisElt, LastElt);
3268 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, MVT::v8i16, V, ThisElt,
3269 DAG.getConstant(i/2, TLI.getPointerTy()));
3273 return DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, V);
3276 /// LowerBuildVectorv16i8 - Custom lower build_vector of v8i16.
3278 static SDOperand LowerBuildVectorv8i16(SDOperand Op, unsigned NonZeros,
3279 unsigned NumNonZero, unsigned NumZero,
3280 SelectionDAG &DAG, TargetLowering &TLI) {
3286 for (unsigned i = 0; i < 8; ++i) {
3287 bool isNonZero = (NonZeros & (1 << i)) != 0;
3291 V = getZeroVector(MVT::v8i16, DAG);
3293 V = DAG.getNode(ISD::UNDEF, MVT::v8i16);
3296 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, MVT::v8i16, V, Op.getOperand(i),
3297 DAG.getConstant(i, TLI.getPointerTy()));
3305 X86TargetLowering::LowerBUILD_VECTOR(SDOperand Op, SelectionDAG &DAG) {
3306 // All zero's are handled with pxor.
3307 if (ISD::isBuildVectorAllZeros(Op.Val))
3310 // All one's are handled with pcmpeqd.
3311 if (ISD::isBuildVectorAllOnes(Op.Val))
3314 MVT::ValueType VT = Op.getValueType();
3315 MVT::ValueType EVT = MVT::getVectorBaseType(VT);
3316 unsigned EVTBits = MVT::getSizeInBits(EVT);
3318 unsigned NumElems = Op.getNumOperands();
3319 unsigned NumZero = 0;
3320 unsigned NumNonZero = 0;
3321 unsigned NonZeros = 0;
3322 std::set<SDOperand> Values;
3323 for (unsigned i = 0; i < NumElems; ++i) {
3324 SDOperand Elt = Op.getOperand(i);
3325 if (Elt.getOpcode() != ISD::UNDEF) {
3327 if (isZeroNode(Elt))
3330 NonZeros |= (1 << i);
3336 if (NumNonZero == 0)
3337 // Must be a mix of zero and undef. Return a zero vector.
3338 return getZeroVector(VT, DAG);
3340 // Splat is obviously ok. Let legalizer expand it to a shuffle.
3341 if (Values.size() == 1)
3344 // Special case for single non-zero element.
3345 if (NumNonZero == 1) {
3346 unsigned Idx = CountTrailingZeros_32(NonZeros);
3347 SDOperand Item = Op.getOperand(Idx);
3348 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, Item);
3350 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
3351 return getShuffleVectorZeroOrUndef(Item, VT, NumElems, Idx,
3354 if (EVTBits == 32) {
3355 // Turn it into a shuffle of zero and zero-extended scalar to vector.
3356 Item = getShuffleVectorZeroOrUndef(Item, VT, NumElems, 0, NumZero > 0,
3358 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(NumElems);
3359 MVT::ValueType MaskEVT = MVT::getVectorBaseType(MaskVT);
3360 std::vector<SDOperand> MaskVec;
3361 for (unsigned i = 0; i < NumElems; i++)
3362 MaskVec.push_back(DAG.getConstant((i == Idx) ? 0 : 1, MaskEVT));
3363 SDOperand Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3364 &MaskVec[0], MaskVec.size());
3365 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, Item,
3366 DAG.getNode(ISD::UNDEF, VT), Mask);
3370 // Let legalizer expand 2-wide build_vector's.
3374 // If element VT is < 32 bits, convert it to inserts into a zero vector.
3376 SDOperand V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
3378 if (V.Val) return V;
3381 if (EVTBits == 16) {
3382 SDOperand V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
3384 if (V.Val) return V;
3387 // If element VT is == 32 bits, turn it into a number of shuffles.
3388 std::vector<SDOperand> V(NumElems);
3389 if (NumElems == 4 && NumZero > 0) {
3390 for (unsigned i = 0; i < 4; ++i) {
3391 bool isZero = !(NonZeros & (1 << i));
3393 V[i] = getZeroVector(VT, DAG);
3395 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, Op.getOperand(i));
3398 for (unsigned i = 0; i < 2; ++i) {
3399 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
3402 V[i] = V[i*2]; // Must be a zero vector.
3405 V[i] = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V[i*2+1], V[i*2],
3406 getMOVLMask(NumElems, DAG));
3409 V[i] = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V[i*2], V[i*2+1],
3410 getMOVLMask(NumElems, DAG));
3413 V[i] = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V[i*2], V[i*2+1],
3414 getUnpacklMask(NumElems, DAG));
3419 // Take advantage of the fact GR32 to VR128 scalar_to_vector (i.e. movd)
3420 // clears the upper bits.
3421 // FIXME: we can do the same for v4f32 case when we know both parts of
3422 // the lower half come from scalar_to_vector (loadf32). We should do
3423 // that in post legalizer dag combiner with target specific hooks.
3424 if (MVT::isInteger(EVT) && (NonZeros & (0x3 << 2)) == 0)
3426 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(NumElems);
3427 MVT::ValueType EVT = MVT::getVectorBaseType(MaskVT);
3428 std::vector<SDOperand> MaskVec;
3429 bool Reverse = (NonZeros & 0x3) == 2;
3430 for (unsigned i = 0; i < 2; ++i)
3432 MaskVec.push_back(DAG.getConstant(1-i, EVT));
3434 MaskVec.push_back(DAG.getConstant(i, EVT));
3435 Reverse = ((NonZeros & (0x3 << 2)) >> 2) == 2;
3436 for (unsigned i = 0; i < 2; ++i)
3438 MaskVec.push_back(DAG.getConstant(1-i+NumElems, EVT));
3440 MaskVec.push_back(DAG.getConstant(i+NumElems, EVT));
3441 SDOperand ShufMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3442 &MaskVec[0], MaskVec.size());
3443 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V[0], V[1], ShufMask);
3446 if (Values.size() > 2) {
3447 // Expand into a number of unpckl*.
3449 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
3450 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
3451 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
3452 SDOperand UnpckMask = getUnpacklMask(NumElems, DAG);
3453 for (unsigned i = 0; i < NumElems; ++i)
3454 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, Op.getOperand(i));
3456 while (NumElems != 0) {
3457 for (unsigned i = 0; i < NumElems; ++i)
3458 V[i] = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V[i], V[i + NumElems],
3469 X86TargetLowering::LowerVECTOR_SHUFFLE(SDOperand Op, SelectionDAG &DAG) {
3470 SDOperand V1 = Op.getOperand(0);
3471 SDOperand V2 = Op.getOperand(1);
3472 SDOperand PermMask = Op.getOperand(2);
3473 MVT::ValueType VT = Op.getValueType();
3474 unsigned NumElems = PermMask.getNumOperands();
3475 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
3476 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
3477 bool V1IsSplat = false;
3478 bool V2IsSplat = false;
3480 if (isUndefShuffle(Op.Val))
3481 return DAG.getNode(ISD::UNDEF, VT);
3483 if (isSplatMask(PermMask.Val)) {
3484 if (NumElems <= 4) return Op;
3485 // Promote it to a v4i32 splat.
3486 return PromoteSplat(Op, DAG);
3489 if (X86::isMOVLMask(PermMask.Val))
3490 return (V1IsUndef) ? V2 : Op;
3492 if (X86::isMOVSHDUPMask(PermMask.Val) ||
3493 X86::isMOVSLDUPMask(PermMask.Val) ||
3494 X86::isMOVHLPSMask(PermMask.Val) ||
3495 X86::isMOVHPMask(PermMask.Val) ||
3496 X86::isMOVLPMask(PermMask.Val))
3499 if (ShouldXformToMOVHLPS(PermMask.Val) ||
3500 ShouldXformToMOVLP(V1.Val, V2.Val, PermMask.Val))
3501 return CommuteVectorShuffle(Op, V1, V2, PermMask, DAG);
3503 bool Commuted = false;
3504 V1IsSplat = isSplatVector(V1.Val);
3505 V2IsSplat = isSplatVector(V2.Val);
3506 if ((V1IsSplat || V1IsUndef) && !(V2IsSplat || V2IsUndef)) {
3507 Op = CommuteVectorShuffle(Op, V1, V2, PermMask, DAG);
3508 std::swap(V1IsSplat, V2IsSplat);
3509 std::swap(V1IsUndef, V2IsUndef);
3513 if (isCommutedMOVL(PermMask.Val, V2IsSplat, V2IsUndef)) {
3514 if (V2IsUndef) return V1;
3515 Op = CommuteVectorShuffle(Op, V1, V2, PermMask, DAG);
3517 // V2 is a splat, so the mask may be malformed. That is, it may point
3518 // to any V2 element. The instruction selectior won't like this. Get
3519 // a corrected mask and commute to form a proper MOVS{S|D}.
3520 SDOperand NewMask = getMOVLMask(NumElems, DAG);
3521 if (NewMask.Val != PermMask.Val)
3522 Op = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, NewMask);
3527 if (X86::isUNPCKL_v_undef_Mask(PermMask.Val) ||
3528 X86::isUNPCKLMask(PermMask.Val) ||
3529 X86::isUNPCKHMask(PermMask.Val))
3533 // Normalize mask so all entries that point to V2 points to its first
3534 // element then try to match unpck{h|l} again. If match, return a
3535 // new vector_shuffle with the corrected mask.
3536 SDOperand NewMask = NormalizeMask(PermMask, DAG);
3537 if (NewMask.Val != PermMask.Val) {
3538 if (X86::isUNPCKLMask(PermMask.Val, true)) {
3539 SDOperand NewMask = getUnpacklMask(NumElems, DAG);
3540 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, NewMask);
3541 } else if (X86::isUNPCKHMask(PermMask.Val, true)) {
3542 SDOperand NewMask = getUnpackhMask(NumElems, DAG);
3543 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, NewMask);
3548 // Normalize the node to match x86 shuffle ops if needed
3549 if (V2.getOpcode() != ISD::UNDEF && isCommutedSHUFP(PermMask.Val))
3550 Op = CommuteVectorShuffle(Op, V1, V2, PermMask, DAG);
3553 // Commute is back and try unpck* again.
3554 Op = CommuteVectorShuffle(Op, V1, V2, PermMask, DAG);
3555 if (X86::isUNPCKL_v_undef_Mask(PermMask.Val) ||
3556 X86::isUNPCKLMask(PermMask.Val) ||
3557 X86::isUNPCKHMask(PermMask.Val))
3561 // If VT is integer, try PSHUF* first, then SHUFP*.
3562 if (MVT::isInteger(VT)) {
3563 if (X86::isPSHUFDMask(PermMask.Val) ||
3564 X86::isPSHUFHWMask(PermMask.Val) ||
3565 X86::isPSHUFLWMask(PermMask.Val)) {
3566 if (V2.getOpcode() != ISD::UNDEF)
3567 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1,
3568 DAG.getNode(ISD::UNDEF, V1.getValueType()),PermMask);
3572 if (X86::isSHUFPMask(PermMask.Val))
3575 // Handle v8i16 shuffle high / low shuffle node pair.
3576 if (VT == MVT::v8i16 && isPSHUFHW_PSHUFLWMask(PermMask.Val)) {
3577 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(NumElems);
3578 MVT::ValueType BaseVT = MVT::getVectorBaseType(MaskVT);
3579 std::vector<SDOperand> MaskVec;
3580 for (unsigned i = 0; i != 4; ++i)
3581 MaskVec.push_back(PermMask.getOperand(i));
3582 for (unsigned i = 4; i != 8; ++i)
3583 MaskVec.push_back(DAG.getConstant(i, BaseVT));
3584 SDOperand Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3585 &MaskVec[0], MaskVec.size());
3586 V1 = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, Mask);
3588 for (unsigned i = 0; i != 4; ++i)
3589 MaskVec.push_back(DAG.getConstant(i, BaseVT));
3590 for (unsigned i = 4; i != 8; ++i)
3591 MaskVec.push_back(PermMask.getOperand(i));
3592 Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0],MaskVec.size());
3593 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, Mask);
3596 // Floating point cases in the other order.
3597 if (X86::isSHUFPMask(PermMask.Val))
3599 if (X86::isPSHUFDMask(PermMask.Val) ||
3600 X86::isPSHUFHWMask(PermMask.Val) ||
3601 X86::isPSHUFLWMask(PermMask.Val)) {
3602 if (V2.getOpcode() != ISD::UNDEF)
3603 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1,
3604 DAG.getNode(ISD::UNDEF, V1.getValueType()),PermMask);
3609 if (NumElems == 4) {
3610 MVT::ValueType MaskVT = PermMask.getValueType();
3611 MVT::ValueType MaskEVT = MVT::getVectorBaseType(MaskVT);
3612 std::vector<std::pair<int, int> > Locs;
3613 Locs.reserve(NumElems);
3614 std::vector<SDOperand> Mask1(NumElems, DAG.getNode(ISD::UNDEF, MaskEVT));
3615 std::vector<SDOperand> Mask2(NumElems, DAG.getNode(ISD::UNDEF, MaskEVT));
3618 // If no more than two elements come from either vector. This can be
3619 // implemented with two shuffles. First shuffle gather the elements.
3620 // The second shuffle, which takes the first shuffle as both of its
3621 // vector operands, put the elements into the right order.
3622 for (unsigned i = 0; i != NumElems; ++i) {
3623 SDOperand Elt = PermMask.getOperand(i);
3624 if (Elt.getOpcode() == ISD::UNDEF) {
3625 Locs[i] = std::make_pair(-1, -1);
3627 unsigned Val = cast<ConstantSDNode>(Elt)->getValue();
3628 if (Val < NumElems) {
3629 Locs[i] = std::make_pair(0, NumLo);
3633 Locs[i] = std::make_pair(1, NumHi);
3634 if (2+NumHi < NumElems)
3635 Mask1[2+NumHi] = Elt;
3640 if (NumLo <= 2 && NumHi <= 2) {
3641 V1 = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2,
3642 DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3643 &Mask1[0], Mask1.size()));
3644 for (unsigned i = 0; i != NumElems; ++i) {
3645 if (Locs[i].first == -1)
3648 unsigned Idx = (i < NumElems/2) ? 0 : NumElems;
3649 Idx += Locs[i].first * (NumElems/2) + Locs[i].second;
3650 Mask2[i] = DAG.getConstant(Idx, MaskEVT);
3654 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V1,
3655 DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3656 &Mask2[0], Mask2.size()));
3659 // Break it into (shuffle shuffle_hi, shuffle_lo).
3661 std::vector<SDOperand> LoMask(NumElems, DAG.getNode(ISD::UNDEF, MaskEVT));
3662 std::vector<SDOperand> HiMask(NumElems, DAG.getNode(ISD::UNDEF, MaskEVT));
3663 std::vector<SDOperand> *MaskPtr = &LoMask;
3664 unsigned MaskIdx = 0;
3666 unsigned HiIdx = NumElems/2;
3667 for (unsigned i = 0; i != NumElems; ++i) {
3668 if (i == NumElems/2) {
3674 SDOperand Elt = PermMask.getOperand(i);
3675 if (Elt.getOpcode() == ISD::UNDEF) {
3676 Locs[i] = std::make_pair(-1, -1);
3677 } else if (cast<ConstantSDNode>(Elt)->getValue() < NumElems) {
3678 Locs[i] = std::make_pair(MaskIdx, LoIdx);
3679 (*MaskPtr)[LoIdx] = Elt;
3682 Locs[i] = std::make_pair(MaskIdx, HiIdx);
3683 (*MaskPtr)[HiIdx] = Elt;
3688 SDOperand LoShuffle =
3689 DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2,
3690 DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3691 &LoMask[0], LoMask.size()));
3692 SDOperand HiShuffle =
3693 DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2,
3694 DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3695 &HiMask[0], HiMask.size()));
3696 std::vector<SDOperand> MaskOps;
3697 for (unsigned i = 0; i != NumElems; ++i) {
3698 if (Locs[i].first == -1) {
3699 MaskOps.push_back(DAG.getNode(ISD::UNDEF, MaskEVT));
3701 unsigned Idx = Locs[i].first * NumElems + Locs[i].second;
3702 MaskOps.push_back(DAG.getConstant(Idx, MaskEVT));
3705 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, LoShuffle, HiShuffle,
3706 DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3707 &MaskOps[0], MaskOps.size()));
3714 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDOperand Op, SelectionDAG &DAG) {
3715 if (!isa<ConstantSDNode>(Op.getOperand(1)))
3718 MVT::ValueType VT = Op.getValueType();
3719 // TODO: handle v16i8.
3720 if (MVT::getSizeInBits(VT) == 16) {
3721 // Transform it so it match pextrw which produces a 32-bit result.
3722 MVT::ValueType EVT = (MVT::ValueType)(VT+1);
3723 SDOperand Extract = DAG.getNode(X86ISD::PEXTRW, EVT,
3724 Op.getOperand(0), Op.getOperand(1));
3725 SDOperand Assert = DAG.getNode(ISD::AssertZext, EVT, Extract,
3726 DAG.getValueType(VT));
3727 return DAG.getNode(ISD::TRUNCATE, VT, Assert);
3728 } else if (MVT::getSizeInBits(VT) == 32) {
3729 SDOperand Vec = Op.getOperand(0);
3730 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getValue();
3733 // SHUFPS the element to the lowest double word, then movss.
3734 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(4);
3735 std::vector<SDOperand> IdxVec;
3736 IdxVec.push_back(DAG.getConstant(Idx, MVT::getVectorBaseType(MaskVT)));
3737 IdxVec.push_back(DAG.getNode(ISD::UNDEF, MVT::getVectorBaseType(MaskVT)));
3738 IdxVec.push_back(DAG.getNode(ISD::UNDEF, MVT::getVectorBaseType(MaskVT)));
3739 IdxVec.push_back(DAG.getNode(ISD::UNDEF, MVT::getVectorBaseType(MaskVT)));
3740 SDOperand Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3741 &IdxVec[0], IdxVec.size());
3742 Vec = DAG.getNode(ISD::VECTOR_SHUFFLE, Vec.getValueType(),
3743 Vec, DAG.getNode(ISD::UNDEF, Vec.getValueType()), Mask);
3744 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, VT, Vec,
3745 DAG.getConstant(0, getPointerTy()));
3746 } else if (MVT::getSizeInBits(VT) == 64) {
3747 SDOperand Vec = Op.getOperand(0);
3748 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getValue();
3752 // UNPCKHPD the element to the lowest double word, then movsd.
3753 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
3754 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
3755 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(4);
3756 std::vector<SDOperand> IdxVec;
3757 IdxVec.push_back(DAG.getConstant(1, MVT::getVectorBaseType(MaskVT)));
3758 IdxVec.push_back(DAG.getNode(ISD::UNDEF, MVT::getVectorBaseType(MaskVT)));
3759 SDOperand Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3760 &IdxVec[0], IdxVec.size());
3761 Vec = DAG.getNode(ISD::VECTOR_SHUFFLE, Vec.getValueType(),
3762 Vec, DAG.getNode(ISD::UNDEF, Vec.getValueType()), Mask);
3763 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, VT, Vec,
3764 DAG.getConstant(0, getPointerTy()));
3771 X86TargetLowering::LowerINSERT_VECTOR_ELT(SDOperand Op, SelectionDAG &DAG) {
3772 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
3773 // as its second argument.
3774 MVT::ValueType VT = Op.getValueType();
3775 MVT::ValueType BaseVT = MVT::getVectorBaseType(VT);
3776 SDOperand N0 = Op.getOperand(0);
3777 SDOperand N1 = Op.getOperand(1);
3778 SDOperand N2 = Op.getOperand(2);
3779 if (MVT::getSizeInBits(BaseVT) == 16) {
3780 if (N1.getValueType() != MVT::i32)
3781 N1 = DAG.getNode(ISD::ANY_EXTEND, MVT::i32, N1);
3782 if (N2.getValueType() != MVT::i32)
3783 N2 = DAG.getConstant(cast<ConstantSDNode>(N2)->getValue(), MVT::i32);
3784 return DAG.getNode(X86ISD::PINSRW, VT, N0, N1, N2);
3785 } else if (MVT::getSizeInBits(BaseVT) == 32) {
3786 unsigned Idx = cast<ConstantSDNode>(N2)->getValue();
3789 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, N1);
3790 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(4);
3791 MVT::ValueType BaseVT = MVT::getVectorBaseType(MaskVT);
3792 std::vector<SDOperand> MaskVec;
3793 MaskVec.push_back(DAG.getConstant(4, BaseVT));
3794 for (unsigned i = 1; i <= 3; ++i)
3795 MaskVec.push_back(DAG.getConstant(i, BaseVT));
3796 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, N0, N1,
3797 DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3798 &MaskVec[0], MaskVec.size()));
3800 // Use two pinsrw instructions to insert a 32 bit value.
3802 if (MVT::isFloatingPoint(N1.getValueType())) {
3803 if (ISD::isNON_EXTLoad(N1.Val)) {
3804 // Just load directly from f32mem to GR32.
3805 LoadSDNode *LD = cast<LoadSDNode>(N1);
3806 N1 = DAG.getLoad(MVT::i32, LD->getChain(), LD->getBasePtr(),
3807 LD->getSrcValue(), LD->getSrcValueOffset());
3809 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, MVT::v4f32, N1);
3810 N1 = DAG.getNode(ISD::BIT_CONVERT, MVT::v4i32, N1);
3811 N1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i32, N1,
3812 DAG.getConstant(0, getPointerTy()));
3815 N0 = DAG.getNode(ISD::BIT_CONVERT, MVT::v8i16, N0);
3816 N0 = DAG.getNode(X86ISD::PINSRW, MVT::v8i16, N0, N1,
3817 DAG.getConstant(Idx, getPointerTy()));
3818 N1 = DAG.getNode(ISD::SRL, MVT::i32, N1, DAG.getConstant(16, MVT::i8));
3819 N0 = DAG.getNode(X86ISD::PINSRW, MVT::v8i16, N0, N1,
3820 DAG.getConstant(Idx+1, getPointerTy()));
3821 return DAG.getNode(ISD::BIT_CONVERT, VT, N0);
3829 X86TargetLowering::LowerSCALAR_TO_VECTOR(SDOperand Op, SelectionDAG &DAG) {
3830 SDOperand AnyExt = DAG.getNode(ISD::ANY_EXTEND, MVT::i32, Op.getOperand(0));
3831 return DAG.getNode(X86ISD::S2VEC, Op.getValueType(), AnyExt);
3834 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
3835 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
3836 // one of the above mentioned nodes. It has to be wrapped because otherwise
3837 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
3838 // be used to form addressing mode. These wrapped nodes will be selected
3841 X86TargetLowering::LowerConstantPool(SDOperand Op, SelectionDAG &DAG) {
3842 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
3843 SDOperand Result = DAG.getNode(X86ISD::Wrapper, getPointerTy(),
3844 DAG.getTargetConstantPool(CP->getConstVal(),
3846 CP->getAlignment()));
3847 if (Subtarget->isTargetDarwin()) {
3848 // With PIC, the address is actually $g + Offset.
3849 if (!Subtarget->is64Bit() &&
3850 getTargetMachine().getRelocationModel() == Reloc::PIC_)
3851 Result = DAG.getNode(ISD::ADD, getPointerTy(),
3852 DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()), Result);
3859 X86TargetLowering::LowerGlobalAddress(SDOperand Op, SelectionDAG &DAG) {
3860 GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
3861 SDOperand Result = DAG.getNode(X86ISD::Wrapper, getPointerTy(),
3862 DAG.getTargetGlobalAddress(GV,
3864 if (Subtarget->isTargetDarwin()) {
3865 // With PIC, the address is actually $g + Offset.
3866 if (!Subtarget->is64Bit() &&
3867 getTargetMachine().getRelocationModel() == Reloc::PIC_)
3868 Result = DAG.getNode(ISD::ADD, getPointerTy(),
3869 DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()),
3872 // For Darwin, external and weak symbols are indirect, so we want to load
3873 // the value at address GV, not the value of GV itself. This means that
3874 // the GlobalAddress must be in the base or index register of the address,
3875 // not the GV offset field.
3876 if (getTargetMachine().getRelocationModel() != Reloc::Static &&
3877 DarwinGVRequiresExtraLoad(GV))
3878 Result = DAG.getLoad(getPointerTy(), DAG.getEntryNode(), Result, NULL, 0);
3879 } else if (Subtarget->isTargetCygwin() || Subtarget->isTargetWindows()) {
3880 // FIXME: What about PIC?
3881 if (WindowsGVRequiresExtraLoad(GV))
3882 Result = DAG.getLoad(getPointerTy(), DAG.getEntryNode(), Result, NULL, 0);
3890 X86TargetLowering::LowerExternalSymbol(SDOperand Op, SelectionDAG &DAG) {
3891 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
3892 SDOperand Result = DAG.getNode(X86ISD::Wrapper, getPointerTy(),
3893 DAG.getTargetExternalSymbol(Sym,
3895 if (Subtarget->isTargetDarwin()) {
3896 // With PIC, the address is actually $g + Offset.
3897 if (!Subtarget->is64Bit() &&
3898 getTargetMachine().getRelocationModel() == Reloc::PIC_)
3899 Result = DAG.getNode(ISD::ADD, getPointerTy(),
3900 DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()),
3907 SDOperand X86TargetLowering::LowerShift(SDOperand Op, SelectionDAG &DAG) {
3908 assert(Op.getNumOperands() == 3 && Op.getValueType() == MVT::i32 &&
3909 "Not an i64 shift!");
3910 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
3911 SDOperand ShOpLo = Op.getOperand(0);
3912 SDOperand ShOpHi = Op.getOperand(1);
3913 SDOperand ShAmt = Op.getOperand(2);
3914 SDOperand Tmp1 = isSRA ?
3915 DAG.getNode(ISD::SRA, MVT::i32, ShOpHi, DAG.getConstant(31, MVT::i8)) :
3916 DAG.getConstant(0, MVT::i32);
3918 SDOperand Tmp2, Tmp3;
3919 if (Op.getOpcode() == ISD::SHL_PARTS) {
3920 Tmp2 = DAG.getNode(X86ISD::SHLD, MVT::i32, ShOpHi, ShOpLo, ShAmt);
3921 Tmp3 = DAG.getNode(ISD::SHL, MVT::i32, ShOpLo, ShAmt);
3923 Tmp2 = DAG.getNode(X86ISD::SHRD, MVT::i32, ShOpLo, ShOpHi, ShAmt);
3924 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, MVT::i32, ShOpHi, ShAmt);
3927 const MVT::ValueType *VTs = DAG.getNodeValueTypes(MVT::Other, MVT::Flag);
3928 SDOperand AndNode = DAG.getNode(ISD::AND, MVT::i8, ShAmt,
3929 DAG.getConstant(32, MVT::i8));
3930 SDOperand COps[]={DAG.getEntryNode(), AndNode, DAG.getConstant(0, MVT::i8)};
3931 SDOperand InFlag = DAG.getNode(X86ISD::CMP, VTs, 2, COps, 3).getValue(1);
3934 SDOperand CC = DAG.getConstant(X86::COND_NE, MVT::i8);
3936 VTs = DAG.getNodeValueTypes(MVT::i32, MVT::Flag);
3937 SmallVector<SDOperand, 4> Ops;
3938 if (Op.getOpcode() == ISD::SHL_PARTS) {
3939 Ops.push_back(Tmp2);
3940 Ops.push_back(Tmp3);
3942 Ops.push_back(InFlag);
3943 Hi = DAG.getNode(X86ISD::CMOV, VTs, 2, &Ops[0], Ops.size());
3944 InFlag = Hi.getValue(1);
3947 Ops.push_back(Tmp3);
3948 Ops.push_back(Tmp1);
3950 Ops.push_back(InFlag);
3951 Lo = DAG.getNode(X86ISD::CMOV, VTs, 2, &Ops[0], Ops.size());
3953 Ops.push_back(Tmp2);
3954 Ops.push_back(Tmp3);
3956 Ops.push_back(InFlag);
3957 Lo = DAG.getNode(X86ISD::CMOV, VTs, 2, &Ops[0], Ops.size());
3958 InFlag = Lo.getValue(1);
3961 Ops.push_back(Tmp3);
3962 Ops.push_back(Tmp1);
3964 Ops.push_back(InFlag);
3965 Hi = DAG.getNode(X86ISD::CMOV, VTs, 2, &Ops[0], Ops.size());
3968 VTs = DAG.getNodeValueTypes(MVT::i32, MVT::i32);
3972 return DAG.getNode(ISD::MERGE_VALUES, VTs, 2, &Ops[0], Ops.size());
3975 SDOperand X86TargetLowering::LowerSINT_TO_FP(SDOperand Op, SelectionDAG &DAG) {
3976 assert(Op.getOperand(0).getValueType() <= MVT::i64 &&
3977 Op.getOperand(0).getValueType() >= MVT::i16 &&
3978 "Unknown SINT_TO_FP to lower!");
3981 MVT::ValueType SrcVT = Op.getOperand(0).getValueType();
3982 unsigned Size = MVT::getSizeInBits(SrcVT)/8;
3983 MachineFunction &MF = DAG.getMachineFunction();
3984 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size);
3985 SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
3986 SDOperand Chain = DAG.getStore(DAG.getEntryNode(), Op.getOperand(0),
3987 StackSlot, NULL, 0);
3990 std::vector<MVT::ValueType> Tys;
3991 Tys.push_back(MVT::f64);
3992 Tys.push_back(MVT::Other);
3993 if (X86ScalarSSE) Tys.push_back(MVT::Flag);
3994 std::vector<SDOperand> Ops;
3995 Ops.push_back(Chain);
3996 Ops.push_back(StackSlot);
3997 Ops.push_back(DAG.getValueType(SrcVT));
3998 Result = DAG.getNode(X86ScalarSSE ? X86ISD::FILD_FLAG :X86ISD::FILD,
3999 Tys, &Ops[0], Ops.size());
4002 Chain = Result.getValue(1);
4003 SDOperand InFlag = Result.getValue(2);
4005 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
4006 // shouldn't be necessary except that RFP cannot be live across
4007 // multiple blocks. When stackifier is fixed, they can be uncoupled.
4008 MachineFunction &MF = DAG.getMachineFunction();
4009 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8);
4010 SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
4011 std::vector<MVT::ValueType> Tys;
4012 Tys.push_back(MVT::Other);
4013 std::vector<SDOperand> Ops;
4014 Ops.push_back(Chain);
4015 Ops.push_back(Result);
4016 Ops.push_back(StackSlot);
4017 Ops.push_back(DAG.getValueType(Op.getValueType()));
4018 Ops.push_back(InFlag);
4019 Chain = DAG.getNode(X86ISD::FST, Tys, &Ops[0], Ops.size());
4020 Result = DAG.getLoad(Op.getValueType(), Chain, StackSlot, NULL, 0);
4026 SDOperand X86TargetLowering::LowerFP_TO_SINT(SDOperand Op, SelectionDAG &DAG) {
4027 assert(Op.getValueType() <= MVT::i64 && Op.getValueType() >= MVT::i16 &&
4028 "Unknown FP_TO_SINT to lower!");
4029 // We lower FP->sint64 into FISTP64, followed by a load, all to a temporary
4031 MachineFunction &MF = DAG.getMachineFunction();
4032 unsigned MemSize = MVT::getSizeInBits(Op.getValueType())/8;
4033 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize);
4034 SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
4037 switch (Op.getValueType()) {
4038 default: assert(0 && "Invalid FP_TO_SINT to lower!");
4039 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
4040 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
4041 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
4044 SDOperand Chain = DAG.getEntryNode();
4045 SDOperand Value = Op.getOperand(0);
4047 assert(Op.getValueType() == MVT::i64 && "Invalid FP_TO_SINT to lower!");
4048 Chain = DAG.getStore(Chain, Value, StackSlot, NULL, 0);
4049 std::vector<MVT::ValueType> Tys;
4050 Tys.push_back(MVT::f64);
4051 Tys.push_back(MVT::Other);
4052 std::vector<SDOperand> Ops;
4053 Ops.push_back(Chain);
4054 Ops.push_back(StackSlot);
4055 Ops.push_back(DAG.getValueType(Op.getOperand(0).getValueType()));
4056 Value = DAG.getNode(X86ISD::FLD, Tys, &Ops[0], Ops.size());
4057 Chain = Value.getValue(1);
4058 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize);
4059 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
4062 // Build the FP_TO_INT*_IN_MEM
4063 std::vector<SDOperand> Ops;
4064 Ops.push_back(Chain);
4065 Ops.push_back(Value);
4066 Ops.push_back(StackSlot);
4067 SDOperand FIST = DAG.getNode(Opc, MVT::Other, &Ops[0], Ops.size());
4070 return DAG.getLoad(Op.getValueType(), FIST, StackSlot, NULL, 0);
4073 SDOperand X86TargetLowering::LowerFABS(SDOperand Op, SelectionDAG &DAG) {
4074 MVT::ValueType VT = Op.getValueType();
4075 const Type *OpNTy = MVT::getTypeForValueType(VT);
4076 std::vector<Constant*> CV;
4077 if (VT == MVT::f64) {
4078 CV.push_back(ConstantFP::get(OpNTy, BitsToDouble(~(1ULL << 63))));
4079 CV.push_back(ConstantFP::get(OpNTy, 0.0));
4081 CV.push_back(ConstantFP::get(OpNTy, BitsToFloat(~(1U << 31))));
4082 CV.push_back(ConstantFP::get(OpNTy, 0.0));
4083 CV.push_back(ConstantFP::get(OpNTy, 0.0));
4084 CV.push_back(ConstantFP::get(OpNTy, 0.0));
4086 Constant *CS = ConstantStruct::get(CV);
4087 SDOperand CPIdx = DAG.getConstantPool(CS, getPointerTy(), 4);
4088 std::vector<MVT::ValueType> Tys;
4090 Tys.push_back(MVT::Other);
4091 SmallVector<SDOperand, 3> Ops;
4092 Ops.push_back(DAG.getEntryNode());
4093 Ops.push_back(CPIdx);
4094 Ops.push_back(DAG.getSrcValue(NULL));
4095 SDOperand Mask = DAG.getNode(X86ISD::LOAD_PACK, Tys, &Ops[0], Ops.size());
4096 return DAG.getNode(X86ISD::FAND, VT, Op.getOperand(0), Mask);
4099 SDOperand X86TargetLowering::LowerFNEG(SDOperand Op, SelectionDAG &DAG) {
4100 MVT::ValueType VT = Op.getValueType();
4101 const Type *OpNTy = MVT::getTypeForValueType(VT);
4102 std::vector<Constant*> CV;
4103 if (VT == MVT::f64) {
4104 CV.push_back(ConstantFP::get(OpNTy, BitsToDouble(1ULL << 63)));
4105 CV.push_back(ConstantFP::get(OpNTy, 0.0));
4107 CV.push_back(ConstantFP::get(OpNTy, BitsToFloat(1U << 31)));
4108 CV.push_back(ConstantFP::get(OpNTy, 0.0));
4109 CV.push_back(ConstantFP::get(OpNTy, 0.0));
4110 CV.push_back(ConstantFP::get(OpNTy, 0.0));
4112 Constant *CS = ConstantStruct::get(CV);
4113 SDOperand CPIdx = DAG.getConstantPool(CS, getPointerTy(), 4);
4114 std::vector<MVT::ValueType> Tys;
4116 Tys.push_back(MVT::Other);
4117 SmallVector<SDOperand, 3> Ops;
4118 Ops.push_back(DAG.getEntryNode());
4119 Ops.push_back(CPIdx);
4120 Ops.push_back(DAG.getSrcValue(NULL));
4121 SDOperand Mask = DAG.getNode(X86ISD::LOAD_PACK, Tys, &Ops[0], Ops.size());
4122 return DAG.getNode(X86ISD::FXOR, VT, Op.getOperand(0), Mask);
4125 SDOperand X86TargetLowering::LowerSETCC(SDOperand Op, SelectionDAG &DAG,
4127 assert(Op.getValueType() == MVT::i8 && "SetCC type must be 8-bit integer");
4129 SDOperand Op0 = Op.getOperand(0);
4130 SDOperand Op1 = Op.getOperand(1);
4131 SDOperand CC = Op.getOperand(2);
4132 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
4133 const MVT::ValueType *VTs1 = DAG.getNodeValueTypes(MVT::Other, MVT::Flag);
4134 const MVT::ValueType *VTs2 = DAG.getNodeValueTypes(MVT::i8, MVT::Flag);
4135 bool isFP = MVT::isFloatingPoint(Op.getOperand(1).getValueType());
4138 if (translateX86CC(cast<CondCodeSDNode>(CC)->get(), isFP, X86CC,
4140 SDOperand Ops1[] = { Chain, Op0, Op1 };
4141 Cond = DAG.getNode(X86ISD::CMP, VTs1, 2, Ops1, 3).getValue(1);
4142 SDOperand Ops2[] = { DAG.getConstant(X86CC, MVT::i8), Cond };
4143 return DAG.getNode(X86ISD::SETCC, VTs2, 2, Ops2, 2);
4146 assert(isFP && "Illegal integer SetCC!");
4148 SDOperand COps[] = { Chain, Op0, Op1 };
4149 Cond = DAG.getNode(X86ISD::CMP, VTs1, 2, COps, 3).getValue(1);
4151 switch (SetCCOpcode) {
4152 default: assert(false && "Illegal floating point SetCC!");
4153 case ISD::SETOEQ: { // !PF & ZF
4154 SDOperand Ops1[] = { DAG.getConstant(X86::COND_NP, MVT::i8), Cond };
4155 SDOperand Tmp1 = DAG.getNode(X86ISD::SETCC, VTs2, 2, Ops1, 2);
4156 SDOperand Ops2[] = { DAG.getConstant(X86::COND_E, MVT::i8),
4158 SDOperand Tmp2 = DAG.getNode(X86ISD::SETCC, VTs2, 2, Ops2, 2);
4159 return DAG.getNode(ISD::AND, MVT::i8, Tmp1, Tmp2);
4161 case ISD::SETUNE: { // PF | !ZF
4162 SDOperand Ops1[] = { DAG.getConstant(X86::COND_P, MVT::i8), Cond };
4163 SDOperand Tmp1 = DAG.getNode(X86ISD::SETCC, VTs2, 2, Ops1, 2);
4164 SDOperand Ops2[] = { DAG.getConstant(X86::COND_NE, MVT::i8),
4166 SDOperand Tmp2 = DAG.getNode(X86ISD::SETCC, VTs2, 2, Ops2, 2);
4167 return DAG.getNode(ISD::OR, MVT::i8, Tmp1, Tmp2);
4172 SDOperand X86TargetLowering::LowerSELECT(SDOperand Op, SelectionDAG &DAG) {
4173 bool addTest = true;
4174 SDOperand Chain = DAG.getEntryNode();
4175 SDOperand Cond = Op.getOperand(0);
4177 const MVT::ValueType *VTs = DAG.getNodeValueTypes(MVT::Other, MVT::Flag);
4179 if (Cond.getOpcode() == ISD::SETCC)
4180 Cond = LowerSETCC(Cond, DAG, Chain);
4182 if (Cond.getOpcode() == X86ISD::SETCC) {
4183 CC = Cond.getOperand(0);
4185 // If condition flag is set by a X86ISD::CMP, then make a copy of it
4186 // (since flag operand cannot be shared). Use it as the condition setting
4187 // operand in place of the X86ISD::SETCC.
4188 // If the X86ISD::SETCC has more than one use, then perhaps it's better
4189 // to use a test instead of duplicating the X86ISD::CMP (for register
4190 // pressure reason)?
4191 SDOperand Cmp = Cond.getOperand(1);
4192 unsigned Opc = Cmp.getOpcode();
4193 bool IllegalFPCMov = !X86ScalarSSE &&
4194 MVT::isFloatingPoint(Op.getValueType()) &&
4195 !hasFPCMov(cast<ConstantSDNode>(CC)->getSignExtended());
4196 if ((Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI) &&
4198 SDOperand Ops[] = { Chain, Cmp.getOperand(1), Cmp.getOperand(2) };
4199 Cond = DAG.getNode(Opc, VTs, 2, Ops, 3);
4205 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
4206 SDOperand Ops[] = { Chain, Cond, DAG.getConstant(0, MVT::i8) };
4207 Cond = DAG.getNode(X86ISD::CMP, VTs, 2, Ops, 3);
4210 VTs = DAG.getNodeValueTypes(Op.getValueType(), MVT::Flag);
4211 SmallVector<SDOperand, 4> Ops;
4212 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
4213 // condition is true.
4214 Ops.push_back(Op.getOperand(2));
4215 Ops.push_back(Op.getOperand(1));
4217 Ops.push_back(Cond.getValue(1));
4218 return DAG.getNode(X86ISD::CMOV, VTs, 2, &Ops[0], Ops.size());
4221 SDOperand X86TargetLowering::LowerBRCOND(SDOperand Op, SelectionDAG &DAG) {
4222 bool addTest = true;
4223 SDOperand Chain = Op.getOperand(0);
4224 SDOperand Cond = Op.getOperand(1);
4225 SDOperand Dest = Op.getOperand(2);
4227 const MVT::ValueType *VTs = DAG.getNodeValueTypes(MVT::Other, MVT::Flag);
4229 if (Cond.getOpcode() == ISD::SETCC)
4230 Cond = LowerSETCC(Cond, DAG, Chain);
4232 if (Cond.getOpcode() == X86ISD::SETCC) {
4233 CC = Cond.getOperand(0);
4235 // If condition flag is set by a X86ISD::CMP, then make a copy of it
4236 // (since flag operand cannot be shared). Use it as the condition setting
4237 // operand in place of the X86ISD::SETCC.
4238 // If the X86ISD::SETCC has more than one use, then perhaps it's better
4239 // to use a test instead of duplicating the X86ISD::CMP (for register
4240 // pressure reason)?
4241 SDOperand Cmp = Cond.getOperand(1);
4242 unsigned Opc = Cmp.getOpcode();
4243 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI) {
4244 SDOperand Ops[] = { Chain, Cmp.getOperand(1), Cmp.getOperand(2) };
4245 Cond = DAG.getNode(Opc, VTs, 2, Ops, 3);
4251 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
4252 SDOperand Ops[] = { Chain, Cond, DAG.getConstant(0, MVT::i8) };
4253 Cond = DAG.getNode(X86ISD::CMP, VTs, 2, Ops, 3);
4255 return DAG.getNode(X86ISD::BRCOND, Op.getValueType(),
4256 Cond, Op.getOperand(2), CC, Cond.getValue(1));
4259 SDOperand X86TargetLowering::LowerJumpTable(SDOperand Op, SelectionDAG &DAG) {
4260 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
4261 SDOperand Result = DAG.getNode(X86ISD::Wrapper, getPointerTy(),
4262 DAG.getTargetJumpTable(JT->getIndex(),
4264 if (Subtarget->isTargetDarwin()) {
4265 // With PIC, the address is actually $g + Offset.
4266 if (!Subtarget->is64Bit() &&
4267 getTargetMachine().getRelocationModel() == Reloc::PIC_)
4268 Result = DAG.getNode(ISD::ADD, getPointerTy(),
4269 DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()),
4276 SDOperand X86TargetLowering::LowerCALL(SDOperand Op, SelectionDAG &DAG) {
4277 unsigned CallingConv= cast<ConstantSDNode>(Op.getOperand(1))->getValue();
4279 if (Subtarget->is64Bit())
4280 return LowerX86_64CCCCallTo(Op, DAG);
4282 switch (CallingConv) {
4284 assert(0 && "Unsupported calling convention");
4285 case CallingConv::Fast:
4287 return LowerFastCCCallTo(Op, DAG, false);
4290 case CallingConv::C:
4291 case CallingConv::CSRet:
4292 return LowerCCCCallTo(Op, DAG);
4293 case CallingConv::X86_StdCall:
4294 return LowerStdCallCCCallTo(Op, DAG);
4295 case CallingConv::X86_FastCall:
4296 return LowerFastCCCallTo(Op, DAG, true);
4300 SDOperand X86TargetLowering::LowerRET(SDOperand Op, SelectionDAG &DAG) {
4303 switch(Op.getNumOperands()) {
4305 assert(0 && "Do not know how to return this many arguments!");
4307 case 1: // ret void.
4308 return DAG.getNode(X86ISD::RET_FLAG, MVT::Other, Op.getOperand(0),
4309 DAG.getConstant(getBytesToPopOnReturn(), MVT::i16));
4311 MVT::ValueType ArgVT = Op.getOperand(1).getValueType();
4313 if (MVT::isVector(ArgVT) ||
4314 (Subtarget->is64Bit() && MVT::isFloatingPoint(ArgVT))) {
4315 // Integer or FP vector result -> XMM0.
4316 if (DAG.getMachineFunction().liveout_empty())
4317 DAG.getMachineFunction().addLiveOut(X86::XMM0);
4318 Copy = DAG.getCopyToReg(Op.getOperand(0), X86::XMM0, Op.getOperand(1),
4320 } else if (MVT::isInteger(ArgVT)) {
4321 // Integer result -> EAX / RAX.
4322 // The C calling convention guarantees the return value has been
4323 // promoted to at least MVT::i32. The X86-64 ABI doesn't require the
4324 // value to be promoted MVT::i64. So we don't have to extend it to
4325 // 64-bit. Return the value in EAX, but mark RAX as liveout.
4326 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
4327 if (DAG.getMachineFunction().liveout_empty())
4328 DAG.getMachineFunction().addLiveOut(Reg);
4330 Reg = (ArgVT == MVT::i64) ? X86::RAX : X86::EAX;
4331 Copy = DAG.getCopyToReg(Op.getOperand(0), Reg, Op.getOperand(1),
4333 } else if (!X86ScalarSSE) {
4334 // FP return with fp-stack value.
4335 if (DAG.getMachineFunction().liveout_empty())
4336 DAG.getMachineFunction().addLiveOut(X86::ST0);
4338 std::vector<MVT::ValueType> Tys;
4339 Tys.push_back(MVT::Other);
4340 Tys.push_back(MVT::Flag);
4341 std::vector<SDOperand> Ops;
4342 Ops.push_back(Op.getOperand(0));
4343 Ops.push_back(Op.getOperand(1));
4344 Copy = DAG.getNode(X86ISD::FP_SET_RESULT, Tys, &Ops[0], Ops.size());
4346 // FP return with ScalarSSE (return on fp-stack).
4347 if (DAG.getMachineFunction().liveout_empty())
4348 DAG.getMachineFunction().addLiveOut(X86::ST0);
4351 SDOperand Chain = Op.getOperand(0);
4352 SDOperand Value = Op.getOperand(1);
4354 if (ISD::isNON_EXTLoad(Value.Val) &&
4355 (Chain == Value.getValue(1) || Chain == Value.getOperand(0))) {
4356 Chain = Value.getOperand(0);
4357 MemLoc = Value.getOperand(1);
4359 // Spill the value to memory and reload it into top of stack.
4360 unsigned Size = MVT::getSizeInBits(ArgVT)/8;
4361 MachineFunction &MF = DAG.getMachineFunction();
4362 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size);
4363 MemLoc = DAG.getFrameIndex(SSFI, getPointerTy());
4364 Chain = DAG.getStore(Op.getOperand(0), Value, MemLoc, NULL, 0);
4366 std::vector<MVT::ValueType> Tys;
4367 Tys.push_back(MVT::f64);
4368 Tys.push_back(MVT::Other);
4369 std::vector<SDOperand> Ops;
4370 Ops.push_back(Chain);
4371 Ops.push_back(MemLoc);
4372 Ops.push_back(DAG.getValueType(ArgVT));
4373 Copy = DAG.getNode(X86ISD::FLD, Tys, &Ops[0], Ops.size());
4375 Tys.push_back(MVT::Other);
4376 Tys.push_back(MVT::Flag);
4378 Ops.push_back(Copy.getValue(1));
4379 Ops.push_back(Copy);
4380 Copy = DAG.getNode(X86ISD::FP_SET_RESULT, Tys, &Ops[0], Ops.size());
4385 unsigned Reg1 = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
4386 unsigned Reg2 = Subtarget->is64Bit() ? X86::RDX : X86::EDX;
4387 if (DAG.getMachineFunction().liveout_empty()) {
4388 DAG.getMachineFunction().addLiveOut(Reg1);
4389 DAG.getMachineFunction().addLiveOut(Reg2);
4392 Copy = DAG.getCopyToReg(Op.getOperand(0), Reg2, Op.getOperand(3),
4394 Copy = DAG.getCopyToReg(Copy, Reg1, Op.getOperand(1), Copy.getValue(1));
4398 return DAG.getNode(X86ISD::RET_FLAG, MVT::Other,
4399 Copy, DAG.getConstant(getBytesToPopOnReturn(), MVT::i16),
4404 X86TargetLowering::LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG) {
4405 MachineFunction &MF = DAG.getMachineFunction();
4406 const Function* Fn = MF.getFunction();
4407 if (Fn->hasExternalLinkage() &&
4408 Subtarget->isTargetCygwin() &&
4409 Fn->getName() == "main")
4410 MF.getInfo<X86FunctionInfo>()->setForceFramePointer(true);
4412 unsigned CC = cast<ConstantSDNode>(Op.getOperand(1))->getValue();
4413 if (Subtarget->is64Bit())
4414 return LowerX86_64CCCArguments(Op, DAG);
4418 assert(0 && "Unsupported calling convention");
4419 case CallingConv::Fast:
4421 return LowerFastCCArguments(Op, DAG);
4424 case CallingConv::C:
4425 case CallingConv::CSRet:
4426 return LowerCCCArguments(Op, DAG);
4427 case CallingConv::X86_StdCall:
4428 MF.getInfo<X86FunctionInfo>()->setDecorationStyle(StdCall);
4429 return LowerStdCallCCArguments(Op, DAG);
4430 case CallingConv::X86_FastCall:
4431 MF.getInfo<X86FunctionInfo>()->setDecorationStyle(FastCall);
4432 return LowerFastCallCCArguments(Op, DAG);
4436 SDOperand X86TargetLowering::LowerMEMSET(SDOperand Op, SelectionDAG &DAG) {
4437 SDOperand InFlag(0, 0);
4438 SDOperand Chain = Op.getOperand(0);
4440 (unsigned)cast<ConstantSDNode>(Op.getOperand(4))->getValue();
4441 if (Align == 0) Align = 1;
4443 ConstantSDNode *I = dyn_cast<ConstantSDNode>(Op.getOperand(3));
4444 // If not DWORD aligned, call memset if size is less than the threshold.
4445 // It knows how to align to the right boundary first.
4446 if ((Align & 3) != 0 ||
4447 (I && I->getValue() < Subtarget->getMinRepStrSizeThreshold())) {
4448 MVT::ValueType IntPtr = getPointerTy();
4449 const Type *IntPtrTy = getTargetData()->getIntPtrType();
4450 std::vector<std::pair<SDOperand, const Type*> > Args;
4451 Args.push_back(std::make_pair(Op.getOperand(1), IntPtrTy));
4452 // Extend the ubyte argument to be an int value for the call.
4453 SDOperand Val = DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Op.getOperand(2));
4454 Args.push_back(std::make_pair(Val, IntPtrTy));
4455 Args.push_back(std::make_pair(Op.getOperand(3), IntPtrTy));
4456 std::pair<SDOperand,SDOperand> CallResult =
4457 LowerCallTo(Chain, Type::VoidTy, false, CallingConv::C, false,
4458 DAG.getExternalSymbol("memset", IntPtr), Args, DAG);
4459 return CallResult.second;
4464 ConstantSDNode *ValC = dyn_cast<ConstantSDNode>(Op.getOperand(2));
4465 unsigned BytesLeft = 0;
4466 bool TwoRepStos = false;
4469 uint64_t Val = ValC->getValue() & 255;
4471 // If the value is a constant, then we can potentially use larger sets.
4472 switch (Align & 3) {
4473 case 2: // WORD aligned
4476 Val = (Val << 8) | Val;
4478 case 0: // DWORD aligned
4481 Val = (Val << 8) | Val;
4482 Val = (Val << 16) | Val;
4483 if (Subtarget->is64Bit() && ((Align & 0xF) == 0)) { // QWORD aligned
4486 Val = (Val << 32) | Val;
4489 default: // Byte aligned
4492 Count = Op.getOperand(3);
4496 if (AVT > MVT::i8) {
4498 unsigned UBytes = MVT::getSizeInBits(AVT) / 8;
4499 Count = DAG.getConstant(I->getValue() / UBytes, getPointerTy());
4500 BytesLeft = I->getValue() % UBytes;
4502 assert(AVT >= MVT::i32 &&
4503 "Do not use rep;stos if not at least DWORD aligned");
4504 Count = DAG.getNode(ISD::SRL, Op.getOperand(3).getValueType(),
4505 Op.getOperand(3), DAG.getConstant(2, MVT::i8));
4510 Chain = DAG.getCopyToReg(Chain, ValReg, DAG.getConstant(Val, AVT),
4512 InFlag = Chain.getValue(1);
4515 Count = Op.getOperand(3);
4516 Chain = DAG.getCopyToReg(Chain, X86::AL, Op.getOperand(2), InFlag);
4517 InFlag = Chain.getValue(1);
4520 Chain = DAG.getCopyToReg(Chain, Subtarget->is64Bit() ? X86::RCX : X86::ECX,
4522 InFlag = Chain.getValue(1);
4523 Chain = DAG.getCopyToReg(Chain, Subtarget->is64Bit() ? X86::RDI : X86::EDI,
4524 Op.getOperand(1), InFlag);
4525 InFlag = Chain.getValue(1);
4527 std::vector<MVT::ValueType> Tys;
4528 Tys.push_back(MVT::Other);
4529 Tys.push_back(MVT::Flag);
4530 std::vector<SDOperand> Ops;
4531 Ops.push_back(Chain);
4532 Ops.push_back(DAG.getValueType(AVT));
4533 Ops.push_back(InFlag);
4534 Chain = DAG.getNode(X86ISD::REP_STOS, Tys, &Ops[0], Ops.size());
4537 InFlag = Chain.getValue(1);
4538 Count = Op.getOperand(3);
4539 MVT::ValueType CVT = Count.getValueType();
4540 SDOperand Left = DAG.getNode(ISD::AND, CVT, Count,
4541 DAG.getConstant((AVT == MVT::i64) ? 7 : 3, CVT));
4542 Chain = DAG.getCopyToReg(Chain, (CVT == MVT::i64) ? X86::RCX : X86::ECX,
4544 InFlag = Chain.getValue(1);
4546 Tys.push_back(MVT::Other);
4547 Tys.push_back(MVT::Flag);
4549 Ops.push_back(Chain);
4550 Ops.push_back(DAG.getValueType(MVT::i8));
4551 Ops.push_back(InFlag);
4552 Chain = DAG.getNode(X86ISD::REP_STOS, Tys, &Ops[0], Ops.size());
4553 } else if (BytesLeft) {
4554 // Issue stores for the last 1 - 7 bytes.
4556 unsigned Val = ValC->getValue() & 255;
4557 unsigned Offset = I->getValue() - BytesLeft;
4558 SDOperand DstAddr = Op.getOperand(1);
4559 MVT::ValueType AddrVT = DstAddr.getValueType();
4560 if (BytesLeft >= 4) {
4561 Val = (Val << 8) | Val;
4562 Val = (Val << 16) | Val;
4563 Value = DAG.getConstant(Val, MVT::i32);
4564 Chain = DAG.getStore(Chain, Value,
4565 DAG.getNode(ISD::ADD, AddrVT, DstAddr,
4566 DAG.getConstant(Offset, AddrVT)),
4571 if (BytesLeft >= 2) {
4572 Value = DAG.getConstant((Val << 8) | Val, MVT::i16);
4573 Chain = DAG.getStore(Chain, Value,
4574 DAG.getNode(ISD::ADD, AddrVT, DstAddr,
4575 DAG.getConstant(Offset, AddrVT)),
4580 if (BytesLeft == 1) {
4581 Value = DAG.getConstant(Val, MVT::i8);
4582 Chain = DAG.getStore(Chain, Value,
4583 DAG.getNode(ISD::ADD, AddrVT, DstAddr,
4584 DAG.getConstant(Offset, AddrVT)),
4592 SDOperand X86TargetLowering::LowerMEMCPY(SDOperand Op, SelectionDAG &DAG) {
4593 SDOperand Chain = Op.getOperand(0);
4595 (unsigned)cast<ConstantSDNode>(Op.getOperand(4))->getValue();
4596 if (Align == 0) Align = 1;
4598 ConstantSDNode *I = dyn_cast<ConstantSDNode>(Op.getOperand(3));
4599 // If not DWORD aligned, call memcpy if size is less than the threshold.
4600 // It knows how to align to the right boundary first.
4601 if ((Align & 3) != 0 ||
4602 (I && I->getValue() < Subtarget->getMinRepStrSizeThreshold())) {
4603 MVT::ValueType IntPtr = getPointerTy();
4604 const Type *IntPtrTy = getTargetData()->getIntPtrType();
4605 std::vector<std::pair<SDOperand, const Type*> > Args;
4606 Args.push_back(std::make_pair(Op.getOperand(1), IntPtrTy));
4607 Args.push_back(std::make_pair(Op.getOperand(2), IntPtrTy));
4608 Args.push_back(std::make_pair(Op.getOperand(3), IntPtrTy));
4609 std::pair<SDOperand,SDOperand> CallResult =
4610 LowerCallTo(Chain, Type::VoidTy, false, CallingConv::C, false,
4611 DAG.getExternalSymbol("memcpy", IntPtr), Args, DAG);
4612 return CallResult.second;
4617 unsigned BytesLeft = 0;
4618 bool TwoRepMovs = false;
4619 switch (Align & 3) {
4620 case 2: // WORD aligned
4623 case 0: // DWORD aligned
4625 if (Subtarget->is64Bit() && ((Align & 0xF) == 0)) // QWORD aligned
4628 default: // Byte aligned
4630 Count = Op.getOperand(3);
4634 if (AVT > MVT::i8) {
4636 unsigned UBytes = MVT::getSizeInBits(AVT) / 8;
4637 Count = DAG.getConstant(I->getValue() / UBytes, getPointerTy());
4638 BytesLeft = I->getValue() % UBytes;
4640 assert(AVT >= MVT::i32 &&
4641 "Do not use rep;movs if not at least DWORD aligned");
4642 Count = DAG.getNode(ISD::SRL, Op.getOperand(3).getValueType(),
4643 Op.getOperand(3), DAG.getConstant(2, MVT::i8));
4648 SDOperand InFlag(0, 0);
4649 Chain = DAG.getCopyToReg(Chain, Subtarget->is64Bit() ? X86::RCX : X86::ECX,
4651 InFlag = Chain.getValue(1);
4652 Chain = DAG.getCopyToReg(Chain, Subtarget->is64Bit() ? X86::RDI : X86::EDI,
4653 Op.getOperand(1), InFlag);
4654 InFlag = Chain.getValue(1);
4655 Chain = DAG.getCopyToReg(Chain, Subtarget->is64Bit() ? X86::RSI : X86::ESI,
4656 Op.getOperand(2), InFlag);
4657 InFlag = Chain.getValue(1);
4659 std::vector<MVT::ValueType> Tys;
4660 Tys.push_back(MVT::Other);
4661 Tys.push_back(MVT::Flag);
4662 std::vector<SDOperand> Ops;
4663 Ops.push_back(Chain);
4664 Ops.push_back(DAG.getValueType(AVT));
4665 Ops.push_back(InFlag);
4666 Chain = DAG.getNode(X86ISD::REP_MOVS, Tys, &Ops[0], Ops.size());
4669 InFlag = Chain.getValue(1);
4670 Count = Op.getOperand(3);
4671 MVT::ValueType CVT = Count.getValueType();
4672 SDOperand Left = DAG.getNode(ISD::AND, CVT, Count,
4673 DAG.getConstant((AVT == MVT::i64) ? 7 : 3, CVT));
4674 Chain = DAG.getCopyToReg(Chain, (CVT == MVT::i64) ? X86::RCX : X86::ECX,
4676 InFlag = Chain.getValue(1);
4678 Tys.push_back(MVT::Other);
4679 Tys.push_back(MVT::Flag);
4681 Ops.push_back(Chain);
4682 Ops.push_back(DAG.getValueType(MVT::i8));
4683 Ops.push_back(InFlag);
4684 Chain = DAG.getNode(X86ISD::REP_MOVS, Tys, &Ops[0], Ops.size());
4685 } else if (BytesLeft) {
4686 // Issue loads and stores for the last 1 - 7 bytes.
4687 unsigned Offset = I->getValue() - BytesLeft;
4688 SDOperand DstAddr = Op.getOperand(1);
4689 MVT::ValueType DstVT = DstAddr.getValueType();
4690 SDOperand SrcAddr = Op.getOperand(2);
4691 MVT::ValueType SrcVT = SrcAddr.getValueType();
4693 if (BytesLeft >= 4) {
4694 Value = DAG.getLoad(MVT::i32, Chain,
4695 DAG.getNode(ISD::ADD, SrcVT, SrcAddr,
4696 DAG.getConstant(Offset, SrcVT)),
4698 Chain = Value.getValue(1);
4699 Chain = DAG.getStore(Chain, Value,
4700 DAG.getNode(ISD::ADD, DstVT, DstAddr,
4701 DAG.getConstant(Offset, DstVT)),
4706 if (BytesLeft >= 2) {
4707 Value = DAG.getLoad(MVT::i16, Chain,
4708 DAG.getNode(ISD::ADD, SrcVT, SrcAddr,
4709 DAG.getConstant(Offset, SrcVT)),
4711 Chain = Value.getValue(1);
4712 Chain = DAG.getStore(Chain, Value,
4713 DAG.getNode(ISD::ADD, DstVT, DstAddr,
4714 DAG.getConstant(Offset, DstVT)),
4720 if (BytesLeft == 1) {
4721 Value = DAG.getLoad(MVT::i8, Chain,
4722 DAG.getNode(ISD::ADD, SrcVT, SrcAddr,
4723 DAG.getConstant(Offset, SrcVT)),
4725 Chain = Value.getValue(1);
4726 Chain = DAG.getStore(Chain, Value,
4727 DAG.getNode(ISD::ADD, DstVT, DstAddr,
4728 DAG.getConstant(Offset, DstVT)),
4737 X86TargetLowering::LowerREADCYCLCECOUNTER(SDOperand Op, SelectionDAG &DAG) {
4738 std::vector<MVT::ValueType> Tys;
4739 Tys.push_back(MVT::Other);
4740 Tys.push_back(MVT::Flag);
4741 std::vector<SDOperand> Ops;
4742 Ops.push_back(Op.getOperand(0));
4743 SDOperand rd = DAG.getNode(X86ISD::RDTSC_DAG, Tys, &Ops[0], Ops.size());
4745 Ops.push_back(DAG.getCopyFromReg(rd, X86::EAX, MVT::i32, rd.getValue(1)));
4746 Ops.push_back(DAG.getCopyFromReg(Ops[0].getValue(1), X86::EDX,
4747 MVT::i32, Ops[0].getValue(2)));
4748 Ops.push_back(Ops[1].getValue(1));
4749 Tys[0] = Tys[1] = MVT::i32;
4750 Tys.push_back(MVT::Other);
4751 return DAG.getNode(ISD::MERGE_VALUES, Tys, &Ops[0], Ops.size());
4754 SDOperand X86TargetLowering::LowerVASTART(SDOperand Op, SelectionDAG &DAG) {
4755 SrcValueSDNode *SV = cast<SrcValueSDNode>(Op.getOperand(2));
4757 if (!Subtarget->is64Bit()) {
4758 // vastart just stores the address of the VarArgsFrameIndex slot into the
4759 // memory location argument.
4760 SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, getPointerTy());
4761 return DAG.getStore(Op.getOperand(0), FR,Op.getOperand(1), SV->getValue(),
4766 // gp_offset (0 - 6 * 8)
4767 // fp_offset (48 - 48 + 8 * 16)
4768 // overflow_arg_area (point to parameters coming in memory).
4770 std::vector<SDOperand> MemOps;
4771 SDOperand FIN = Op.getOperand(1);
4773 SDOperand Store = DAG.getStore(Op.getOperand(0),
4774 DAG.getConstant(VarArgsGPOffset, MVT::i32),
4775 FIN, SV->getValue(), SV->getOffset());
4776 MemOps.push_back(Store);
4779 FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN,
4780 DAG.getConstant(4, getPointerTy()));
4781 Store = DAG.getStore(Op.getOperand(0),
4782 DAG.getConstant(VarArgsFPOffset, MVT::i32),
4783 FIN, SV->getValue(), SV->getOffset());
4784 MemOps.push_back(Store);
4786 // Store ptr to overflow_arg_area
4787 FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN,
4788 DAG.getConstant(4, getPointerTy()));
4789 SDOperand OVFIN = DAG.getFrameIndex(VarArgsFrameIndex, getPointerTy());
4790 Store = DAG.getStore(Op.getOperand(0), OVFIN, FIN, SV->getValue(),
4792 MemOps.push_back(Store);
4794 // Store ptr to reg_save_area.
4795 FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN,
4796 DAG.getConstant(8, getPointerTy()));
4797 SDOperand RSFIN = DAG.getFrameIndex(RegSaveFrameIndex, getPointerTy());
4798 Store = DAG.getStore(Op.getOperand(0), RSFIN, FIN, SV->getValue(),
4800 MemOps.push_back(Store);
4801 return DAG.getNode(ISD::TokenFactor, MVT::Other, &MemOps[0], MemOps.size());
4805 X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDOperand Op, SelectionDAG &DAG) {
4806 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getValue();
4808 default: return SDOperand(); // Don't custom lower most intrinsics.
4809 // Comparison intrinsics.
4810 case Intrinsic::x86_sse_comieq_ss:
4811 case Intrinsic::x86_sse_comilt_ss:
4812 case Intrinsic::x86_sse_comile_ss:
4813 case Intrinsic::x86_sse_comigt_ss:
4814 case Intrinsic::x86_sse_comige_ss:
4815 case Intrinsic::x86_sse_comineq_ss:
4816 case Intrinsic::x86_sse_ucomieq_ss:
4817 case Intrinsic::x86_sse_ucomilt_ss:
4818 case Intrinsic::x86_sse_ucomile_ss:
4819 case Intrinsic::x86_sse_ucomigt_ss:
4820 case Intrinsic::x86_sse_ucomige_ss:
4821 case Intrinsic::x86_sse_ucomineq_ss:
4822 case Intrinsic::x86_sse2_comieq_sd:
4823 case Intrinsic::x86_sse2_comilt_sd:
4824 case Intrinsic::x86_sse2_comile_sd:
4825 case Intrinsic::x86_sse2_comigt_sd:
4826 case Intrinsic::x86_sse2_comige_sd:
4827 case Intrinsic::x86_sse2_comineq_sd:
4828 case Intrinsic::x86_sse2_ucomieq_sd:
4829 case Intrinsic::x86_sse2_ucomilt_sd:
4830 case Intrinsic::x86_sse2_ucomile_sd:
4831 case Intrinsic::x86_sse2_ucomigt_sd:
4832 case Intrinsic::x86_sse2_ucomige_sd:
4833 case Intrinsic::x86_sse2_ucomineq_sd: {
4835 ISD::CondCode CC = ISD::SETCC_INVALID;
4838 case Intrinsic::x86_sse_comieq_ss:
4839 case Intrinsic::x86_sse2_comieq_sd:
4843 case Intrinsic::x86_sse_comilt_ss:
4844 case Intrinsic::x86_sse2_comilt_sd:
4848 case Intrinsic::x86_sse_comile_ss:
4849 case Intrinsic::x86_sse2_comile_sd:
4853 case Intrinsic::x86_sse_comigt_ss:
4854 case Intrinsic::x86_sse2_comigt_sd:
4858 case Intrinsic::x86_sse_comige_ss:
4859 case Intrinsic::x86_sse2_comige_sd:
4863 case Intrinsic::x86_sse_comineq_ss:
4864 case Intrinsic::x86_sse2_comineq_sd:
4868 case Intrinsic::x86_sse_ucomieq_ss:
4869 case Intrinsic::x86_sse2_ucomieq_sd:
4870 Opc = X86ISD::UCOMI;
4873 case Intrinsic::x86_sse_ucomilt_ss:
4874 case Intrinsic::x86_sse2_ucomilt_sd:
4875 Opc = X86ISD::UCOMI;
4878 case Intrinsic::x86_sse_ucomile_ss:
4879 case Intrinsic::x86_sse2_ucomile_sd:
4880 Opc = X86ISD::UCOMI;
4883 case Intrinsic::x86_sse_ucomigt_ss:
4884 case Intrinsic::x86_sse2_ucomigt_sd:
4885 Opc = X86ISD::UCOMI;
4888 case Intrinsic::x86_sse_ucomige_ss:
4889 case Intrinsic::x86_sse2_ucomige_sd:
4890 Opc = X86ISD::UCOMI;
4893 case Intrinsic::x86_sse_ucomineq_ss:
4894 case Intrinsic::x86_sse2_ucomineq_sd:
4895 Opc = X86ISD::UCOMI;
4901 SDOperand LHS = Op.getOperand(1);
4902 SDOperand RHS = Op.getOperand(2);
4903 translateX86CC(CC, true, X86CC, LHS, RHS, DAG);
4905 const MVT::ValueType *VTs = DAG.getNodeValueTypes(MVT::Other, MVT::Flag);
4906 SDOperand Ops1[] = { DAG.getEntryNode(), LHS, RHS };
4907 SDOperand Cond = DAG.getNode(Opc, VTs, 2, Ops1, 3);
4908 VTs = DAG.getNodeValueTypes(MVT::i8, MVT::Flag);
4909 SDOperand Ops2[] = { DAG.getConstant(X86CC, MVT::i8), Cond };
4910 SDOperand SetCC = DAG.getNode(X86ISD::SETCC, VTs, 2, Ops2, 2);
4911 return DAG.getNode(ISD::ANY_EXTEND, MVT::i32, SetCC);
4916 /// LowerOperation - Provide custom lowering hooks for some operations.
4918 SDOperand X86TargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
4919 switch (Op.getOpcode()) {
4920 default: assert(0 && "Should not custom lower this!");
4921 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
4922 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
4923 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
4924 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
4925 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
4926 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
4927 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
4928 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
4929 case ISD::SHL_PARTS:
4930 case ISD::SRA_PARTS:
4931 case ISD::SRL_PARTS: return LowerShift(Op, DAG);
4932 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
4933 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
4934 case ISD::FABS: return LowerFABS(Op, DAG);
4935 case ISD::FNEG: return LowerFNEG(Op, DAG);
4936 case ISD::SETCC: return LowerSETCC(Op, DAG, DAG.getEntryNode());
4937 case ISD::SELECT: return LowerSELECT(Op, DAG);
4938 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
4939 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
4940 case ISD::CALL: return LowerCALL(Op, DAG);
4941 case ISD::RET: return LowerRET(Op, DAG);
4942 case ISD::FORMAL_ARGUMENTS: return LowerFORMAL_ARGUMENTS(Op, DAG);
4943 case ISD::MEMSET: return LowerMEMSET(Op, DAG);
4944 case ISD::MEMCPY: return LowerMEMCPY(Op, DAG);
4945 case ISD::READCYCLECOUNTER: return LowerREADCYCLCECOUNTER(Op, DAG);
4946 case ISD::VASTART: return LowerVASTART(Op, DAG);
4947 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
4951 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
4953 default: return NULL;
4954 case X86ISD::SHLD: return "X86ISD::SHLD";
4955 case X86ISD::SHRD: return "X86ISD::SHRD";
4956 case X86ISD::FAND: return "X86ISD::FAND";
4957 case X86ISD::FXOR: return "X86ISD::FXOR";
4958 case X86ISD::FILD: return "X86ISD::FILD";
4959 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
4960 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
4961 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
4962 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
4963 case X86ISD::FLD: return "X86ISD::FLD";
4964 case X86ISD::FST: return "X86ISD::FST";
4965 case X86ISD::FP_GET_RESULT: return "X86ISD::FP_GET_RESULT";
4966 case X86ISD::FP_SET_RESULT: return "X86ISD::FP_SET_RESULT";
4967 case X86ISD::CALL: return "X86ISD::CALL";
4968 case X86ISD::TAILCALL: return "X86ISD::TAILCALL";
4969 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
4970 case X86ISD::CMP: return "X86ISD::CMP";
4971 case X86ISD::COMI: return "X86ISD::COMI";
4972 case X86ISD::UCOMI: return "X86ISD::UCOMI";
4973 case X86ISD::SETCC: return "X86ISD::SETCC";
4974 case X86ISD::CMOV: return "X86ISD::CMOV";
4975 case X86ISD::BRCOND: return "X86ISD::BRCOND";
4976 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
4977 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
4978 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
4979 case X86ISD::LOAD_PACK: return "X86ISD::LOAD_PACK";
4980 case X86ISD::LOAD_UA: return "X86ISD::LOAD_UA";
4981 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
4982 case X86ISD::Wrapper: return "X86ISD::Wrapper";
4983 case X86ISD::S2VEC: return "X86ISD::S2VEC";
4984 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
4985 case X86ISD::PINSRW: return "X86ISD::PINSRW";
4989 /// isLegalAddressImmediate - Return true if the integer value or
4990 /// GlobalValue can be used as the offset of the target addressing mode.
4991 bool X86TargetLowering::isLegalAddressImmediate(int64_t V) const {
4992 // X86 allows a sign-extended 32-bit immediate field.
4993 return (V > -(1LL << 32) && V < (1LL << 32)-1);
4996 bool X86TargetLowering::isLegalAddressImmediate(GlobalValue *GV) const {
4997 // GV is 64-bit but displacement field is 32-bit unless we are in small code
4998 // model. Mac OS X happens to support only small PIC code model.
4999 // FIXME: better support for other OS's.
5000 if (Subtarget->is64Bit() && !Subtarget->isTargetDarwin())
5002 if (Subtarget->isTargetDarwin()) {
5003 Reloc::Model RModel = getTargetMachine().getRelocationModel();
5004 if (RModel == Reloc::Static)
5006 else if (RModel == Reloc::DynamicNoPIC)
5007 return !DarwinGVRequiresExtraLoad(GV);
5014 /// isShuffleMaskLegal - Targets can use this to indicate that they only
5015 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
5016 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
5017 /// are assumed to be legal.
5019 X86TargetLowering::isShuffleMaskLegal(SDOperand Mask, MVT::ValueType VT) const {
5020 // Only do shuffles on 128-bit vector types for now.
5021 if (MVT::getSizeInBits(VT) == 64) return false;
5022 return (Mask.Val->getNumOperands() <= 4 ||
5023 isSplatMask(Mask.Val) ||
5024 isPSHUFHW_PSHUFLWMask(Mask.Val) ||
5025 X86::isUNPCKLMask(Mask.Val) ||
5026 X86::isUNPCKL_v_undef_Mask(Mask.Val) ||
5027 X86::isUNPCKHMask(Mask.Val));
5030 bool X86TargetLowering::isVectorClearMaskLegal(std::vector<SDOperand> &BVOps,
5032 SelectionDAG &DAG) const {
5033 unsigned NumElts = BVOps.size();
5034 // Only do shuffles on 128-bit vector types for now.
5035 if (MVT::getSizeInBits(EVT) * NumElts == 64) return false;
5036 if (NumElts == 2) return true;
5038 return (isMOVLMask(BVOps) || isCommutedMOVL(BVOps, true) ||
5039 isSHUFPMask(BVOps) || isCommutedSHUFP(BVOps));
5044 //===----------------------------------------------------------------------===//
5045 // X86 Scheduler Hooks
5046 //===----------------------------------------------------------------------===//
5049 X86TargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI,
5050 MachineBasicBlock *BB) {
5051 switch (MI->getOpcode()) {
5052 default: assert(false && "Unexpected instr type to insert");
5053 case X86::CMOV_FR32:
5054 case X86::CMOV_FR64:
5055 case X86::CMOV_V4F32:
5056 case X86::CMOV_V2F64:
5057 case X86::CMOV_V2I64: {
5058 // To "insert" a SELECT_CC instruction, we actually have to insert the
5059 // diamond control-flow pattern. The incoming instruction knows the
5060 // destination vreg to set, the condition code register to branch on, the
5061 // true/false values to select between, and a branch opcode to use.
5062 const BasicBlock *LLVM_BB = BB->getBasicBlock();
5063 ilist<MachineBasicBlock>::iterator It = BB;
5069 // cmpTY ccX, r1, r2
5071 // fallthrough --> copy0MBB
5072 MachineBasicBlock *thisMBB = BB;
5073 MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB);
5074 MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB);
5076 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
5077 BuildMI(BB, Opc, 1).addMBB(sinkMBB);
5078 MachineFunction *F = BB->getParent();
5079 F->getBasicBlockList().insert(It, copy0MBB);
5080 F->getBasicBlockList().insert(It, sinkMBB);
5081 // Update machine-CFG edges by first adding all successors of the current
5082 // block to the new block which will contain the Phi node for the select.
5083 for(MachineBasicBlock::succ_iterator i = BB->succ_begin(),
5084 e = BB->succ_end(); i != e; ++i)
5085 sinkMBB->addSuccessor(*i);
5086 // Next, remove all successors of the current block, and add the true
5087 // and fallthrough blocks as its successors.
5088 while(!BB->succ_empty())
5089 BB->removeSuccessor(BB->succ_begin());
5090 BB->addSuccessor(copy0MBB);
5091 BB->addSuccessor(sinkMBB);
5094 // %FalseValue = ...
5095 // # fallthrough to sinkMBB
5098 // Update machine-CFG edges
5099 BB->addSuccessor(sinkMBB);
5102 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
5105 BuildMI(BB, X86::PHI, 4, MI->getOperand(0).getReg())
5106 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
5107 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
5109 delete MI; // The pseudo instruction is gone now.
5113 case X86::FP_TO_INT16_IN_MEM:
5114 case X86::FP_TO_INT32_IN_MEM:
5115 case X86::FP_TO_INT64_IN_MEM: {
5116 // Change the floating point control register to use "round towards zero"
5117 // mode when truncating to an integer value.
5118 MachineFunction *F = BB->getParent();
5119 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2);
5120 addFrameReference(BuildMI(BB, X86::FNSTCW16m, 4), CWFrameIdx);
5122 // Load the old value of the high byte of the control word...
5124 F->getSSARegMap()->createVirtualRegister(X86::GR16RegisterClass);
5125 addFrameReference(BuildMI(BB, X86::MOV16rm, 4, OldCW), CWFrameIdx);
5127 // Set the high part to be round to zero...
5128 addFrameReference(BuildMI(BB, X86::MOV16mi, 5), CWFrameIdx).addImm(0xC7F);
5130 // Reload the modified control word now...
5131 addFrameReference(BuildMI(BB, X86::FLDCW16m, 4), CWFrameIdx);
5133 // Restore the memory image of control word to original value
5134 addFrameReference(BuildMI(BB, X86::MOV16mr, 5), CWFrameIdx).addReg(OldCW);
5136 // Get the X86 opcode to use.
5138 switch (MI->getOpcode()) {
5139 default: assert(0 && "illegal opcode!");
5140 case X86::FP_TO_INT16_IN_MEM: Opc = X86::FpIST16m; break;
5141 case X86::FP_TO_INT32_IN_MEM: Opc = X86::FpIST32m; break;
5142 case X86::FP_TO_INT64_IN_MEM: Opc = X86::FpIST64m; break;
5146 MachineOperand &Op = MI->getOperand(0);
5147 if (Op.isRegister()) {
5148 AM.BaseType = X86AddressMode::RegBase;
5149 AM.Base.Reg = Op.getReg();
5151 AM.BaseType = X86AddressMode::FrameIndexBase;
5152 AM.Base.FrameIndex = Op.getFrameIndex();
5154 Op = MI->getOperand(1);
5155 if (Op.isImmediate())
5156 AM.Scale = Op.getImm();
5157 Op = MI->getOperand(2);
5158 if (Op.isImmediate())
5159 AM.IndexReg = Op.getImm();
5160 Op = MI->getOperand(3);
5161 if (Op.isGlobalAddress()) {
5162 AM.GV = Op.getGlobal();
5164 AM.Disp = Op.getImm();
5166 addFullAddress(BuildMI(BB, Opc, 5), AM).addReg(MI->getOperand(4).getReg());
5168 // Reload the original control word now.
5169 addFrameReference(BuildMI(BB, X86::FLDCW16m, 4), CWFrameIdx);
5171 delete MI; // The pseudo instruction is gone now.
5177 //===----------------------------------------------------------------------===//
5178 // X86 Optimization Hooks
5179 //===----------------------------------------------------------------------===//
5181 void X86TargetLowering::computeMaskedBitsForTargetNode(const SDOperand Op,
5183 uint64_t &KnownZero,
5185 unsigned Depth) const {
5186 unsigned Opc = Op.getOpcode();
5187 assert((Opc >= ISD::BUILTIN_OP_END ||
5188 Opc == ISD::INTRINSIC_WO_CHAIN ||
5189 Opc == ISD::INTRINSIC_W_CHAIN ||
5190 Opc == ISD::INTRINSIC_VOID) &&
5191 "Should use MaskedValueIsZero if you don't know whether Op"
5192 " is a target node!");
5194 KnownZero = KnownOne = 0; // Don't know anything.
5198 KnownZero |= (MVT::getIntVTBitMask(Op.getValueType()) ^ 1ULL);
5203 /// getShuffleScalarElt - Returns the scalar element that will make up the ith
5204 /// element of the result of the vector shuffle.
5205 static SDOperand getShuffleScalarElt(SDNode *N, unsigned i, SelectionDAG &DAG) {
5206 MVT::ValueType VT = N->getValueType(0);
5207 SDOperand PermMask = N->getOperand(2);
5208 unsigned NumElems = PermMask.getNumOperands();
5209 SDOperand V = (i < NumElems) ? N->getOperand(0) : N->getOperand(1);
5211 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR) {
5213 ? V.getOperand(0) : DAG.getNode(ISD::UNDEF, MVT::getVectorBaseType(VT));
5214 } else if (V.getOpcode() == ISD::VECTOR_SHUFFLE) {
5215 SDOperand Idx = PermMask.getOperand(i);
5216 if (Idx.getOpcode() == ISD::UNDEF)
5217 return DAG.getNode(ISD::UNDEF, MVT::getVectorBaseType(VT));
5218 return getShuffleScalarElt(V.Val,cast<ConstantSDNode>(Idx)->getValue(),DAG);
5223 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
5224 /// node is a GlobalAddress + an offset.
5225 static bool isGAPlusOffset(SDNode *N, GlobalValue* &GA, int64_t &Offset) {
5226 if (N->getOpcode() == X86ISD::Wrapper) {
5227 if (dyn_cast<GlobalAddressSDNode>(N->getOperand(0))) {
5228 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
5231 } else if (N->getOpcode() == ISD::ADD) {
5232 SDOperand N1 = N->getOperand(0);
5233 SDOperand N2 = N->getOperand(1);
5234 if (isGAPlusOffset(N1.Val, GA, Offset)) {
5235 ConstantSDNode *V = dyn_cast<ConstantSDNode>(N2);
5237 Offset += V->getSignExtended();
5240 } else if (isGAPlusOffset(N2.Val, GA, Offset)) {
5241 ConstantSDNode *V = dyn_cast<ConstantSDNode>(N1);
5243 Offset += V->getSignExtended();
5251 /// isConsecutiveLoad - Returns true if N is loading from an address of Base
5253 static bool isConsecutiveLoad(SDNode *N, SDNode *Base, int Dist, int Size,
5254 MachineFrameInfo *MFI) {
5255 if (N->getOperand(0).Val != Base->getOperand(0).Val)
5258 SDOperand Loc = N->getOperand(1);
5259 SDOperand BaseLoc = Base->getOperand(1);
5260 if (Loc.getOpcode() == ISD::FrameIndex) {
5261 if (BaseLoc.getOpcode() != ISD::FrameIndex)
5263 int FI = dyn_cast<FrameIndexSDNode>(Loc)->getIndex();
5264 int BFI = dyn_cast<FrameIndexSDNode>(BaseLoc)->getIndex();
5265 int FS = MFI->getObjectSize(FI);
5266 int BFS = MFI->getObjectSize(BFI);
5267 if (FS != BFS || FS != Size) return false;
5268 return MFI->getObjectOffset(FI) == (MFI->getObjectOffset(BFI) + Dist*Size);
5270 GlobalValue *GV1 = NULL;
5271 GlobalValue *GV2 = NULL;
5272 int64_t Offset1 = 0;
5273 int64_t Offset2 = 0;
5274 bool isGA1 = isGAPlusOffset(Loc.Val, GV1, Offset1);
5275 bool isGA2 = isGAPlusOffset(BaseLoc.Val, GV2, Offset2);
5276 if (isGA1 && isGA2 && GV1 == GV2)
5277 return Offset1 == (Offset2 + Dist*Size);
5283 static bool isBaseAlignment16(SDNode *Base, MachineFrameInfo *MFI,
5284 const X86Subtarget *Subtarget) {
5287 if (isGAPlusOffset(Base, GV, Offset))
5288 return (GV->getAlignment() >= 16 && (Offset % 16) == 0);
5290 assert(Base->getOpcode() == ISD::FrameIndex && "Unexpected base node!");
5291 int BFI = dyn_cast<FrameIndexSDNode>(Base)->getIndex();
5293 // Fixed objects do not specify alignment, however the offsets are known.
5294 return ((Subtarget->getStackAlignment() % 16) == 0 &&
5295 (MFI->getObjectOffset(BFI) % 16) == 0);
5297 return MFI->getObjectAlignment(BFI) >= 16;
5303 /// PerformShuffleCombine - Combine a vector_shuffle that is equal to
5304 /// build_vector load1, load2, load3, load4, <0, 1, 2, 3> into a 128-bit load
5305 /// if the load addresses are consecutive, non-overlapping, and in the right
5307 static SDOperand PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
5308 const X86Subtarget *Subtarget) {
5309 MachineFunction &MF = DAG.getMachineFunction();
5310 MachineFrameInfo *MFI = MF.getFrameInfo();
5311 MVT::ValueType VT = N->getValueType(0);
5312 MVT::ValueType EVT = MVT::getVectorBaseType(VT);
5313 SDOperand PermMask = N->getOperand(2);
5314 int NumElems = (int)PermMask.getNumOperands();
5315 SDNode *Base = NULL;
5316 for (int i = 0; i < NumElems; ++i) {
5317 SDOperand Idx = PermMask.getOperand(i);
5318 if (Idx.getOpcode() == ISD::UNDEF) {
5319 if (!Base) return SDOperand();
5322 getShuffleScalarElt(N, cast<ConstantSDNode>(Idx)->getValue(), DAG);
5323 if (!Arg.Val || !ISD::isNON_EXTLoad(Arg.Val))
5327 else if (!isConsecutiveLoad(Arg.Val, Base,
5328 i, MVT::getSizeInBits(EVT)/8,MFI))
5333 bool isAlign16 = isBaseAlignment16(Base->getOperand(1).Val, MFI, Subtarget);
5335 LoadSDNode *LD = cast<LoadSDNode>(Base);
5336 return DAG.getLoad(VT, LD->getChain(), LD->getBasePtr(), LD->getSrcValue(),
5337 LD->getSrcValueOffset());
5339 // Just use movups, it's shorter.
5340 std::vector<MVT::ValueType> Tys;
5341 Tys.push_back(MVT::v4f32);
5342 Tys.push_back(MVT::Other);
5343 SmallVector<SDOperand, 3> Ops;
5344 Ops.push_back(Base->getOperand(0));
5345 Ops.push_back(Base->getOperand(1));
5346 Ops.push_back(Base->getOperand(2));
5347 return DAG.getNode(ISD::BIT_CONVERT, VT,
5348 DAG.getNode(X86ISD::LOAD_UA, Tys, &Ops[0], Ops.size()));
5352 /// PerformSELECTCombine - Do target-specific dag combines on SELECT nodes.
5353 static SDOperand PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
5354 const X86Subtarget *Subtarget) {
5355 SDOperand Cond = N->getOperand(0);
5357 // If we have SSE[12] support, try to form min/max nodes.
5358 if (Subtarget->hasSSE2() &&
5359 (N->getValueType(0) == MVT::f32 || N->getValueType(0) == MVT::f64)) {
5360 if (Cond.getOpcode() == ISD::SETCC) {
5361 // Get the LHS/RHS of the select.
5362 SDOperand LHS = N->getOperand(1);
5363 SDOperand RHS = N->getOperand(2);
5364 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
5367 if (LHS == Cond.getOperand(0) && RHS == Cond.getOperand(1)) {
5370 case ISD::SETOLE: // (X <= Y) ? X : Y -> min
5373 if (!UnsafeFPMath) break;
5375 case ISD::SETOLT: // (X olt/lt Y) ? X : Y -> min
5377 IntNo = LHS.getValueType() == MVT::f32 ? Intrinsic::x86_sse_min_ss :
5378 Intrinsic::x86_sse2_min_sd;
5381 case ISD::SETOGT: // (X > Y) ? X : Y -> max
5384 if (!UnsafeFPMath) break;
5386 case ISD::SETUGE: // (X uge/ge Y) ? X : Y -> max
5388 IntNo = LHS.getValueType() == MVT::f32 ? Intrinsic::x86_sse_max_ss :
5389 Intrinsic::x86_sse2_max_sd;
5392 } else if (LHS == Cond.getOperand(1) && RHS == Cond.getOperand(0)) {
5395 case ISD::SETOGT: // (X > Y) ? Y : X -> min
5398 if (!UnsafeFPMath) break;
5400 case ISD::SETUGE: // (X uge/ge Y) ? Y : X -> min
5402 IntNo = LHS.getValueType() == MVT::f32 ? Intrinsic::x86_sse_min_ss :
5403 Intrinsic::x86_sse2_min_sd;
5406 case ISD::SETOLE: // (X <= Y) ? Y : X -> max
5409 if (!UnsafeFPMath) break;
5411 case ISD::SETOLT: // (X olt/lt Y) ? Y : X -> max
5413 IntNo = LHS.getValueType() == MVT::f32 ? Intrinsic::x86_sse_max_ss :
5414 Intrinsic::x86_sse2_max_sd;
5419 // minss/maxss take a v4f32 operand.
5421 if (LHS.getValueType() == MVT::f32) {
5422 LHS = DAG.getNode(ISD::SCALAR_TO_VECTOR, MVT::v4f32, LHS);
5423 RHS = DAG.getNode(ISD::SCALAR_TO_VECTOR, MVT::v4f32, RHS);
5425 LHS = DAG.getNode(ISD::SCALAR_TO_VECTOR, MVT::v2f64, LHS);
5426 RHS = DAG.getNode(ISD::SCALAR_TO_VECTOR, MVT::v2f64, RHS);
5429 MVT::ValueType PtrTy = Subtarget->is64Bit() ? MVT::i64 : MVT::i32;
5430 SDOperand IntNoN = DAG.getConstant(IntNo, PtrTy);
5432 SDOperand Val = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, LHS.getValueType(),
5434 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, N->getValueType(0), Val,
5435 DAG.getConstant(0, PtrTy));
5445 SDOperand X86TargetLowering::PerformDAGCombine(SDNode *N,
5446 DAGCombinerInfo &DCI) const {
5447 SelectionDAG &DAG = DCI.DAG;
5448 switch (N->getOpcode()) {
5450 case ISD::VECTOR_SHUFFLE:
5451 return PerformShuffleCombine(N, DAG, Subtarget);
5453 return PerformSELECTCombine(N, DAG, Subtarget);
5459 //===----------------------------------------------------------------------===//
5460 // X86 Inline Assembly Support
5461 //===----------------------------------------------------------------------===//
5463 /// getConstraintType - Given a constraint letter, return the type of
5464 /// constraint it is for this target.
5465 X86TargetLowering::ConstraintType
5466 X86TargetLowering::getConstraintType(char ConstraintLetter) const {
5467 switch (ConstraintLetter) {
5476 return C_RegisterClass;
5477 default: return TargetLowering::getConstraintType(ConstraintLetter);
5481 /// isOperandValidForConstraint - Return the specified operand (possibly
5482 /// modified) if the specified SDOperand is valid for the specified target
5483 /// constraint letter, otherwise return null.
5484 SDOperand X86TargetLowering::
5485 isOperandValidForConstraint(SDOperand Op, char Constraint, SelectionDAG &DAG) {
5486 switch (Constraint) {
5489 // Literal immediates are always ok.
5490 if (isa<ConstantSDNode>(Op)) return Op;
5492 // If we are in non-pic codegen mode, we allow the address of a global to
5493 // be used with 'i'.
5494 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Op)) {
5495 if (getTargetMachine().getRelocationModel() == Reloc::PIC_)
5496 return SDOperand(0, 0);
5498 if (GA->getOpcode() != ISD::TargetGlobalAddress)
5499 Op = DAG.getTargetGlobalAddress(GA->getGlobal(), GA->getValueType(0),
5504 // Otherwise, not valid for this mode.
5505 return SDOperand(0, 0);
5507 return TargetLowering::isOperandValidForConstraint(Op, Constraint, DAG);
5511 std::vector<unsigned> X86TargetLowering::
5512 getRegClassForInlineAsmConstraint(const std::string &Constraint,
5513 MVT::ValueType VT) const {
5514 if (Constraint.size() == 1) {
5515 // FIXME: not handling fp-stack yet!
5516 // FIXME: not handling MMX registers yet ('y' constraint).
5517 switch (Constraint[0]) { // GCC X86 Constraint Letters
5518 default: break; // Unknown constraint letter
5519 case 'A': // EAX/EDX
5520 if (VT == MVT::i32 || VT == MVT::i64)
5521 return make_vector<unsigned>(X86::EAX, X86::EDX, 0);
5523 case 'r': // GENERAL_REGS
5524 case 'R': // LEGACY_REGS
5526 return make_vector<unsigned>(X86::EAX, X86::EDX, X86::ECX, X86::EBX,
5527 X86::ESI, X86::EDI, X86::EBP, X86::ESP, 0);
5528 else if (VT == MVT::i16)
5529 return make_vector<unsigned>(X86::AX, X86::DX, X86::CX, X86::BX,
5530 X86::SI, X86::DI, X86::BP, X86::SP, 0);
5531 else if (VT == MVT::i8)
5532 return make_vector<unsigned>(X86::AL, X86::DL, X86::CL, X86::DL, 0);
5534 case 'l': // INDEX_REGS
5536 return make_vector<unsigned>(X86::EAX, X86::EDX, X86::ECX, X86::EBX,
5537 X86::ESI, X86::EDI, X86::EBP, 0);
5538 else if (VT == MVT::i16)
5539 return make_vector<unsigned>(X86::AX, X86::DX, X86::CX, X86::BX,
5540 X86::SI, X86::DI, X86::BP, 0);
5541 else if (VT == MVT::i8)
5542 return make_vector<unsigned>(X86::AL, X86::DL, X86::CL, X86::DL, 0);
5544 case 'q': // Q_REGS (GENERAL_REGS in 64-bit mode)
5547 return make_vector<unsigned>(X86::EAX, X86::EDX, X86::ECX, X86::EBX, 0);
5548 else if (VT == MVT::i16)
5549 return make_vector<unsigned>(X86::AX, X86::DX, X86::CX, X86::BX, 0);
5550 else if (VT == MVT::i8)
5551 return make_vector<unsigned>(X86::AL, X86::DL, X86::CL, X86::DL, 0);
5553 case 'x': // SSE_REGS if SSE1 allowed
5554 if (Subtarget->hasSSE1())
5555 return make_vector<unsigned>(X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
5556 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7,
5558 return std::vector<unsigned>();
5559 case 'Y': // SSE_REGS if SSE2 allowed
5560 if (Subtarget->hasSSE2())
5561 return make_vector<unsigned>(X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
5562 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7,
5564 return std::vector<unsigned>();
5568 return std::vector<unsigned>();
5571 std::pair<unsigned, const TargetRegisterClass*>
5572 X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
5573 MVT::ValueType VT) const {
5574 // Use the default implementation in TargetLowering to convert the register
5575 // constraint into a member of a register class.
5576 std::pair<unsigned, const TargetRegisterClass*> Res;
5577 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
5579 // Not found as a standard register?
5580 if (Res.second == 0) {
5581 // GCC calls "st(0)" just plain "st".
5582 if (StringsEqualNoCase("{st}", Constraint)) {
5583 Res.first = X86::ST0;
5584 Res.second = X86::RSTRegisterClass;
5590 // Otherwise, check to see if this is a register class of the wrong value
5591 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
5592 // turn into {ax},{dx}.
5593 if (Res.second->hasType(VT))
5594 return Res; // Correct type already, nothing to do.
5596 // All of the single-register GCC register classes map their values onto
5597 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
5598 // really want an 8-bit or 32-bit register, map to the appropriate register
5599 // class and return the appropriate register.
5600 if (Res.second != X86::GR16RegisterClass)
5603 if (VT == MVT::i8) {
5604 unsigned DestReg = 0;
5605 switch (Res.first) {
5607 case X86::AX: DestReg = X86::AL; break;
5608 case X86::DX: DestReg = X86::DL; break;
5609 case X86::CX: DestReg = X86::CL; break;
5610 case X86::BX: DestReg = X86::BL; break;
5613 Res.first = DestReg;
5614 Res.second = Res.second = X86::GR8RegisterClass;
5616 } else if (VT == MVT::i32) {
5617 unsigned DestReg = 0;
5618 switch (Res.first) {
5620 case X86::AX: DestReg = X86::EAX; break;
5621 case X86::DX: DestReg = X86::EDX; break;
5622 case X86::CX: DestReg = X86::ECX; break;
5623 case X86::BX: DestReg = X86::EBX; break;
5624 case X86::SI: DestReg = X86::ESI; break;
5625 case X86::DI: DestReg = X86::EDI; break;
5626 case X86::BP: DestReg = X86::EBP; break;
5627 case X86::SP: DestReg = X86::ESP; break;
5630 Res.first = DestReg;
5631 Res.second = Res.second = X86::GR32RegisterClass;
5633 } else if (VT == MVT::i64) {
5634 unsigned DestReg = 0;
5635 switch (Res.first) {
5637 case X86::AX: DestReg = X86::RAX; break;
5638 case X86::DX: DestReg = X86::RDX; break;
5639 case X86::CX: DestReg = X86::RCX; break;
5640 case X86::BX: DestReg = X86::RBX; break;
5641 case X86::SI: DestReg = X86::RSI; break;
5642 case X86::DI: DestReg = X86::RDI; break;
5643 case X86::BP: DestReg = X86::RBP; break;
5644 case X86::SP: DestReg = X86::RSP; break;
5647 Res.first = DestReg;
5648 Res.second = Res.second = X86::GR64RegisterClass;