1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #include "X86ISelLowering.h"
16 #include "Utils/X86ShuffleDecode.h"
17 #include "X86CallingConv.h"
18 #include "X86InstrBuilder.h"
19 #include "X86MachineFunctionInfo.h"
20 #include "X86TargetMachine.h"
21 #include "X86TargetObjectFile.h"
22 #include "llvm/ADT/SmallBitVector.h"
23 #include "llvm/ADT/SmallSet.h"
24 #include "llvm/ADT/Statistic.h"
25 #include "llvm/ADT/StringExtras.h"
26 #include "llvm/ADT/StringSwitch.h"
27 #include "llvm/ADT/VariadicFunction.h"
28 #include "llvm/CodeGen/IntrinsicLowering.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineFunction.h"
31 #include "llvm/CodeGen/MachineInstrBuilder.h"
32 #include "llvm/CodeGen/MachineJumpTableInfo.h"
33 #include "llvm/CodeGen/MachineModuleInfo.h"
34 #include "llvm/CodeGen/MachineRegisterInfo.h"
35 #include "llvm/IR/CallSite.h"
36 #include "llvm/IR/CallingConv.h"
37 #include "llvm/IR/Constants.h"
38 #include "llvm/IR/DerivedTypes.h"
39 #include "llvm/IR/Function.h"
40 #include "llvm/IR/GlobalAlias.h"
41 #include "llvm/IR/GlobalVariable.h"
42 #include "llvm/IR/Instructions.h"
43 #include "llvm/IR/Intrinsics.h"
44 #include "llvm/MC/MCAsmInfo.h"
45 #include "llvm/MC/MCContext.h"
46 #include "llvm/MC/MCExpr.h"
47 #include "llvm/MC/MCSymbol.h"
48 #include "llvm/Support/CommandLine.h"
49 #include "llvm/Support/Debug.h"
50 #include "llvm/Support/ErrorHandling.h"
51 #include "llvm/Support/MathExtras.h"
52 #include "llvm/Target/TargetOptions.h"
53 #include "X86IntrinsicsInfo.h"
59 #define DEBUG_TYPE "x86-isel"
61 STATISTIC(NumTailCalls, "Number of tail calls");
63 static cl::opt<bool> ExperimentalVectorWideningLegalization(
64 "x86-experimental-vector-widening-legalization", cl::init(false),
65 cl::desc("Enable an experimental vector type legalization through widening "
66 "rather than promotion."),
69 static cl::opt<bool> ExperimentalVectorShuffleLowering(
70 "x86-experimental-vector-shuffle-lowering", cl::init(false),
71 cl::desc("Enable an experimental vector shuffle lowering code path."),
74 // Forward declarations.
75 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
78 static SDValue ExtractSubVector(SDValue Vec, unsigned IdxVal,
79 SelectionDAG &DAG, SDLoc dl,
80 unsigned vectorWidth) {
81 assert((vectorWidth == 128 || vectorWidth == 256) &&
82 "Unsupported vector width");
83 EVT VT = Vec.getValueType();
84 EVT ElVT = VT.getVectorElementType();
85 unsigned Factor = VT.getSizeInBits()/vectorWidth;
86 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT,
87 VT.getVectorNumElements()/Factor);
89 // Extract from UNDEF is UNDEF.
90 if (Vec.getOpcode() == ISD::UNDEF)
91 return DAG.getUNDEF(ResultVT);
93 // Extract the relevant vectorWidth bits. Generate an EXTRACT_SUBVECTOR
94 unsigned ElemsPerChunk = vectorWidth / ElVT.getSizeInBits();
96 // This is the index of the first element of the vectorWidth-bit chunk
98 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits()) / vectorWidth)
101 // If the input is a buildvector just emit a smaller one.
102 if (Vec.getOpcode() == ISD::BUILD_VECTOR)
103 return DAG.getNode(ISD::BUILD_VECTOR, dl, ResultVT,
104 makeArrayRef(Vec->op_begin()+NormalizedIdxVal,
107 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal);
108 SDValue Result = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec,
114 /// Generate a DAG to grab 128-bits from a vector > 128 bits. This
115 /// sets things up to match to an AVX VEXTRACTF128 / VEXTRACTI128
116 /// or AVX-512 VEXTRACTF32x4 / VEXTRACTI32x4
117 /// instructions or a simple subregister reference. Idx is an index in the
118 /// 128 bits we want. It need not be aligned to a 128-bit bounday. That makes
119 /// lowering EXTRACT_VECTOR_ELT operations easier.
120 static SDValue Extract128BitVector(SDValue Vec, unsigned IdxVal,
121 SelectionDAG &DAG, SDLoc dl) {
122 assert((Vec.getValueType().is256BitVector() ||
123 Vec.getValueType().is512BitVector()) && "Unexpected vector size!");
124 return ExtractSubVector(Vec, IdxVal, DAG, dl, 128);
127 /// Generate a DAG to grab 256-bits from a 512-bit vector.
128 static SDValue Extract256BitVector(SDValue Vec, unsigned IdxVal,
129 SelectionDAG &DAG, SDLoc dl) {
130 assert(Vec.getValueType().is512BitVector() && "Unexpected vector size!");
131 return ExtractSubVector(Vec, IdxVal, DAG, dl, 256);
134 static SDValue InsertSubVector(SDValue Result, SDValue Vec,
135 unsigned IdxVal, SelectionDAG &DAG,
136 SDLoc dl, unsigned vectorWidth) {
137 assert((vectorWidth == 128 || vectorWidth == 256) &&
138 "Unsupported vector width");
139 // Inserting UNDEF is Result
140 if (Vec.getOpcode() == ISD::UNDEF)
142 EVT VT = Vec.getValueType();
143 EVT ElVT = VT.getVectorElementType();
144 EVT ResultVT = Result.getValueType();
146 // Insert the relevant vectorWidth bits.
147 unsigned ElemsPerChunk = vectorWidth/ElVT.getSizeInBits();
149 // This is the index of the first element of the vectorWidth-bit chunk
151 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits())/vectorWidth)
154 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal);
155 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec,
158 /// Generate a DAG to put 128-bits into a vector > 128 bits. This
159 /// sets things up to match to an AVX VINSERTF128/VINSERTI128 or
160 /// AVX-512 VINSERTF32x4/VINSERTI32x4 instructions or a
161 /// simple superregister reference. Idx is an index in the 128 bits
162 /// we want. It need not be aligned to a 128-bit bounday. That makes
163 /// lowering INSERT_VECTOR_ELT operations easier.
164 static SDValue Insert128BitVector(SDValue Result, SDValue Vec,
165 unsigned IdxVal, SelectionDAG &DAG,
167 assert(Vec.getValueType().is128BitVector() && "Unexpected vector size!");
168 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 128);
171 static SDValue Insert256BitVector(SDValue Result, SDValue Vec,
172 unsigned IdxVal, SelectionDAG &DAG,
174 assert(Vec.getValueType().is256BitVector() && "Unexpected vector size!");
175 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 256);
178 /// Concat two 128-bit vectors into a 256 bit vector using VINSERTF128
179 /// instructions. This is used because creating CONCAT_VECTOR nodes of
180 /// BUILD_VECTORS returns a larger BUILD_VECTOR while we're trying to lower
181 /// large BUILD_VECTORS.
182 static SDValue Concat128BitVectors(SDValue V1, SDValue V2, EVT VT,
183 unsigned NumElems, SelectionDAG &DAG,
185 SDValue V = Insert128BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
186 return Insert128BitVector(V, V2, NumElems/2, DAG, dl);
189 static SDValue Concat256BitVectors(SDValue V1, SDValue V2, EVT VT,
190 unsigned NumElems, SelectionDAG &DAG,
192 SDValue V = Insert256BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
193 return Insert256BitVector(V, V2, NumElems/2, DAG, dl);
196 static TargetLoweringObjectFile *createTLOF(const Triple &TT) {
197 if (TT.isOSBinFormatMachO()) {
198 if (TT.getArch() == Triple::x86_64)
199 return new X86_64MachoTargetObjectFile();
200 return new TargetLoweringObjectFileMachO();
204 return new X86LinuxTargetObjectFile();
205 if (TT.isOSBinFormatELF())
206 return new TargetLoweringObjectFileELF();
207 if (TT.isKnownWindowsMSVCEnvironment())
208 return new X86WindowsTargetObjectFile();
209 if (TT.isOSBinFormatCOFF())
210 return new TargetLoweringObjectFileCOFF();
211 llvm_unreachable("unknown subtarget type");
214 // FIXME: This should stop caching the target machine as soon as
215 // we can remove resetOperationActions et al.
216 X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
217 : TargetLowering(TM, createTLOF(Triple(TM.getTargetTriple()))) {
218 Subtarget = &TM.getSubtarget<X86Subtarget>();
219 X86ScalarSSEf64 = Subtarget->hasSSE2();
220 X86ScalarSSEf32 = Subtarget->hasSSE1();
221 TD = getDataLayout();
223 resetOperationActions();
226 void X86TargetLowering::resetOperationActions() {
227 const TargetMachine &TM = getTargetMachine();
228 static bool FirstTimeThrough = true;
230 // If none of the target options have changed, then we don't need to reset the
231 // operation actions.
232 if (!FirstTimeThrough && TO == TM.Options) return;
234 if (!FirstTimeThrough) {
235 // Reinitialize the actions.
237 FirstTimeThrough = false;
242 // Set up the TargetLowering object.
243 static const MVT IntVTs[] = { MVT::i8, MVT::i16, MVT::i32, MVT::i64 };
245 // X86 is weird, it always uses i8 for shift amounts and setcc results.
246 setBooleanContents(ZeroOrOneBooleanContent);
247 // X86-SSE is even stranger. It uses -1 or 0 for vector masks.
248 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
250 // For 64-bit since we have so many registers use the ILP scheduler, for
251 // 32-bit code use the register pressure specific scheduling.
252 // For Atom, always use ILP scheduling.
253 if (Subtarget->isAtom())
254 setSchedulingPreference(Sched::ILP);
255 else if (Subtarget->is64Bit())
256 setSchedulingPreference(Sched::ILP);
258 setSchedulingPreference(Sched::RegPressure);
259 const X86RegisterInfo *RegInfo =
260 TM.getSubtarget<X86Subtarget>().getRegisterInfo();
261 setStackPointerRegisterToSaveRestore(RegInfo->getStackRegister());
263 // Bypass expensive divides on Atom when compiling with O2
264 if (Subtarget->hasSlowDivide() && TM.getOptLevel() >= CodeGenOpt::Default) {
265 addBypassSlowDiv(32, 8);
266 if (Subtarget->is64Bit())
267 addBypassSlowDiv(64, 16);
270 if (Subtarget->isTargetKnownWindowsMSVC()) {
271 // Setup Windows compiler runtime calls.
272 setLibcallName(RTLIB::SDIV_I64, "_alldiv");
273 setLibcallName(RTLIB::UDIV_I64, "_aulldiv");
274 setLibcallName(RTLIB::SREM_I64, "_allrem");
275 setLibcallName(RTLIB::UREM_I64, "_aullrem");
276 setLibcallName(RTLIB::MUL_I64, "_allmul");
277 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall);
278 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall);
279 setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::X86_StdCall);
280 setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::X86_StdCall);
281 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::X86_StdCall);
283 // The _ftol2 runtime function has an unusual calling conv, which
284 // is modeled by a special pseudo-instruction.
285 setLibcallName(RTLIB::FPTOUINT_F64_I64, nullptr);
286 setLibcallName(RTLIB::FPTOUINT_F32_I64, nullptr);
287 setLibcallName(RTLIB::FPTOUINT_F64_I32, nullptr);
288 setLibcallName(RTLIB::FPTOUINT_F32_I32, nullptr);
291 if (Subtarget->isTargetDarwin()) {
292 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
293 setUseUnderscoreSetJmp(false);
294 setUseUnderscoreLongJmp(false);
295 } else if (Subtarget->isTargetWindowsGNU()) {
296 // MS runtime is weird: it exports _setjmp, but longjmp!
297 setUseUnderscoreSetJmp(true);
298 setUseUnderscoreLongJmp(false);
300 setUseUnderscoreSetJmp(true);
301 setUseUnderscoreLongJmp(true);
304 // Set up the register classes.
305 addRegisterClass(MVT::i8, &X86::GR8RegClass);
306 addRegisterClass(MVT::i16, &X86::GR16RegClass);
307 addRegisterClass(MVT::i32, &X86::GR32RegClass);
308 if (Subtarget->is64Bit())
309 addRegisterClass(MVT::i64, &X86::GR64RegClass);
311 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
313 // We don't accept any truncstore of integer registers.
314 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
315 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
316 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
317 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
318 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
319 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
321 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
323 // SETOEQ and SETUNE require checking two conditions.
324 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
325 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
326 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
327 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
328 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
329 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
331 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
333 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
334 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
335 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
337 if (Subtarget->is64Bit()) {
338 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
339 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
340 } else if (!TM.Options.UseSoftFloat) {
341 // We have an algorithm for SSE2->double, and we turn this into a
342 // 64-bit FILD followed by conditional FADD for other targets.
343 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
344 // We have an algorithm for SSE2, and we turn this into a 64-bit
345 // FILD for other targets.
346 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
349 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
351 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
352 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
354 if (!TM.Options.UseSoftFloat) {
355 // SSE has no i16 to fp conversion, only i32
356 if (X86ScalarSSEf32) {
357 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
358 // f32 and f64 cases are Legal, f80 case is not
359 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
361 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
362 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
365 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
366 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
369 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
370 // are Legal, f80 is custom lowered.
371 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
372 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
374 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
376 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
377 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
379 if (X86ScalarSSEf32) {
380 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
381 // f32 and f64 cases are Legal, f80 case is not
382 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
384 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
385 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
388 // Handle FP_TO_UINT by promoting the destination to a larger signed
390 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
391 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
392 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
394 if (Subtarget->is64Bit()) {
395 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
396 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
397 } else if (!TM.Options.UseSoftFloat) {
398 // Since AVX is a superset of SSE3, only check for SSE here.
399 if (Subtarget->hasSSE1() && !Subtarget->hasSSE3())
400 // Expand FP_TO_UINT into a select.
401 // FIXME: We would like to use a Custom expander here eventually to do
402 // the optimal thing for SSE vs. the default expansion in the legalizer.
403 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
405 // With SSE3 we can use fisttpll to convert to a signed i64; without
406 // SSE, we're stuck with a fistpll.
407 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
410 if (isTargetFTOL()) {
411 // Use the _ftol2 runtime function, which has a pseudo-instruction
412 // to handle its weird calling convention.
413 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Custom);
416 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
417 if (!X86ScalarSSEf64) {
418 setOperationAction(ISD::BITCAST , MVT::f32 , Expand);
419 setOperationAction(ISD::BITCAST , MVT::i32 , Expand);
420 if (Subtarget->is64Bit()) {
421 setOperationAction(ISD::BITCAST , MVT::f64 , Expand);
422 // Without SSE, i64->f64 goes through memory.
423 setOperationAction(ISD::BITCAST , MVT::i64 , Expand);
427 // Scalar integer divide and remainder are lowered to use operations that
428 // produce two results, to match the available instructions. This exposes
429 // the two-result form to trivial CSE, which is able to combine x/y and x%y
430 // into a single instruction.
432 // Scalar integer multiply-high is also lowered to use two-result
433 // operations, to match the available instructions. However, plain multiply
434 // (low) operations are left as Legal, as there are single-result
435 // instructions for this in x86. Using the two-result multiply instructions
436 // when both high and low results are needed must be arranged by dagcombine.
437 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
439 setOperationAction(ISD::MULHS, VT, Expand);
440 setOperationAction(ISD::MULHU, VT, Expand);
441 setOperationAction(ISD::SDIV, VT, Expand);
442 setOperationAction(ISD::UDIV, VT, Expand);
443 setOperationAction(ISD::SREM, VT, Expand);
444 setOperationAction(ISD::UREM, VT, Expand);
446 // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences.
447 setOperationAction(ISD::ADDC, VT, Custom);
448 setOperationAction(ISD::ADDE, VT, Custom);
449 setOperationAction(ISD::SUBC, VT, Custom);
450 setOperationAction(ISD::SUBE, VT, Custom);
453 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
454 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
455 setOperationAction(ISD::BR_CC , MVT::f32, Expand);
456 setOperationAction(ISD::BR_CC , MVT::f64, Expand);
457 setOperationAction(ISD::BR_CC , MVT::f80, Expand);
458 setOperationAction(ISD::BR_CC , MVT::i8, Expand);
459 setOperationAction(ISD::BR_CC , MVT::i16, Expand);
460 setOperationAction(ISD::BR_CC , MVT::i32, Expand);
461 setOperationAction(ISD::BR_CC , MVT::i64, Expand);
462 setOperationAction(ISD::SELECT_CC , MVT::f32, Expand);
463 setOperationAction(ISD::SELECT_CC , MVT::f64, Expand);
464 setOperationAction(ISD::SELECT_CC , MVT::f80, Expand);
465 setOperationAction(ISD::SELECT_CC , MVT::i8, Expand);
466 setOperationAction(ISD::SELECT_CC , MVT::i16, Expand);
467 setOperationAction(ISD::SELECT_CC , MVT::i32, Expand);
468 setOperationAction(ISD::SELECT_CC , MVT::i64, Expand);
469 if (Subtarget->is64Bit())
470 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
471 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
472 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
473 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
474 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
475 setOperationAction(ISD::FREM , MVT::f32 , Expand);
476 setOperationAction(ISD::FREM , MVT::f64 , Expand);
477 setOperationAction(ISD::FREM , MVT::f80 , Expand);
478 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
480 // Promote the i8 variants and force them on up to i32 which has a shorter
482 setOperationAction(ISD::CTTZ , MVT::i8 , Promote);
483 AddPromotedToType (ISD::CTTZ , MVT::i8 , MVT::i32);
484 setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i8 , Promote);
485 AddPromotedToType (ISD::CTTZ_ZERO_UNDEF , MVT::i8 , MVT::i32);
486 if (Subtarget->hasBMI()) {
487 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16 , Expand);
488 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32 , Expand);
489 if (Subtarget->is64Bit())
490 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
492 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
493 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
494 if (Subtarget->is64Bit())
495 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
498 if (Subtarget->hasLZCNT()) {
499 // When promoting the i8 variants, force them to i32 for a shorter
501 setOperationAction(ISD::CTLZ , MVT::i8 , Promote);
502 AddPromotedToType (ISD::CTLZ , MVT::i8 , MVT::i32);
503 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Promote);
504 AddPromotedToType (ISD::CTLZ_ZERO_UNDEF, MVT::i8 , MVT::i32);
505 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Expand);
506 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Expand);
507 if (Subtarget->is64Bit())
508 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
510 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
511 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
512 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
513 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Custom);
514 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Custom);
515 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Custom);
516 if (Subtarget->is64Bit()) {
517 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
518 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom);
522 // Special handling for half-precision floating point conversions.
523 // If we don't have F16C support, then lower half float conversions
524 // into library calls.
525 if (TM.Options.UseSoftFloat || !Subtarget->hasF16C()) {
526 setOperationAction(ISD::FP16_TO_FP, MVT::f32, Expand);
527 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand);
530 // There's never any support for operations beyond MVT::f32.
531 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand);
532 setOperationAction(ISD::FP16_TO_FP, MVT::f80, Expand);
533 setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand);
534 setOperationAction(ISD::FP_TO_FP16, MVT::f80, Expand);
536 setLoadExtAction(ISD::EXTLOAD, MVT::f16, Expand);
537 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
538 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
539 setTruncStoreAction(MVT::f80, MVT::f16, Expand);
541 if (Subtarget->hasPOPCNT()) {
542 setOperationAction(ISD::CTPOP , MVT::i8 , Promote);
544 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
545 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
546 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
547 if (Subtarget->is64Bit())
548 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
551 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
553 if (!Subtarget->hasMOVBE())
554 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
556 // These should be promoted to a larger select which is supported.
557 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
558 // X86 wants to expand cmov itself.
559 setOperationAction(ISD::SELECT , MVT::i8 , Custom);
560 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
561 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
562 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
563 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
564 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
565 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
566 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
567 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
568 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
569 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
570 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
571 if (Subtarget->is64Bit()) {
572 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
573 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
575 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
576 // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support
577 // SjLj exception handling but a light-weight setjmp/longjmp replacement to
578 // support continuation, user-level threading, and etc.. As a result, no
579 // other SjLj exception interfaces are implemented and please don't build
580 // your own exception handling based on them.
581 // LLVM/Clang supports zero-cost DWARF exception handling.
582 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
583 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
586 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
587 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
588 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
589 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
590 if (Subtarget->is64Bit())
591 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
592 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
593 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom);
594 if (Subtarget->is64Bit()) {
595 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
596 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
597 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
598 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
599 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom);
601 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
602 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
603 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
604 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
605 if (Subtarget->is64Bit()) {
606 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
607 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
608 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
611 if (Subtarget->hasSSE1())
612 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
614 setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom);
616 // Expand certain atomics
617 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
619 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, VT, Custom);
620 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom);
621 setOperationAction(ISD::ATOMIC_STORE, VT, Custom);
624 if (Subtarget->hasCmpxchg16b()) {
625 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, MVT::i128, Custom);
628 // FIXME - use subtarget debug flags
629 if (!Subtarget->isTargetDarwin() && !Subtarget->isTargetELF() &&
630 !Subtarget->isTargetCygMing() && !Subtarget->isTargetWin64()) {
631 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
634 if (Subtarget->is64Bit()) {
635 setExceptionPointerRegister(X86::RAX);
636 setExceptionSelectorRegister(X86::RDX);
638 setExceptionPointerRegister(X86::EAX);
639 setExceptionSelectorRegister(X86::EDX);
641 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
642 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
644 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
645 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
647 setOperationAction(ISD::TRAP, MVT::Other, Legal);
648 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Legal);
650 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
651 setOperationAction(ISD::VASTART , MVT::Other, Custom);
652 setOperationAction(ISD::VAEND , MVT::Other, Expand);
653 if (Subtarget->is64Bit() && !Subtarget->isTargetWin64()) {
654 // TargetInfo::X86_64ABIBuiltinVaList
655 setOperationAction(ISD::VAARG , MVT::Other, Custom);
656 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
658 // TargetInfo::CharPtrBuiltinVaList
659 setOperationAction(ISD::VAARG , MVT::Other, Expand);
660 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
663 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
664 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
666 setOperationAction(ISD::DYNAMIC_STACKALLOC, getPointerTy(), Custom);
668 if (!TM.Options.UseSoftFloat && X86ScalarSSEf64) {
669 // f32 and f64 use SSE.
670 // Set up the FP register classes.
671 addRegisterClass(MVT::f32, &X86::FR32RegClass);
672 addRegisterClass(MVT::f64, &X86::FR64RegClass);
674 // Use ANDPD to simulate FABS.
675 setOperationAction(ISD::FABS , MVT::f64, Custom);
676 setOperationAction(ISD::FABS , MVT::f32, Custom);
678 // Use XORP to simulate FNEG.
679 setOperationAction(ISD::FNEG , MVT::f64, Custom);
680 setOperationAction(ISD::FNEG , MVT::f32, Custom);
682 // Use ANDPD and ORPD to simulate FCOPYSIGN.
683 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
684 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
686 // Lower this to FGETSIGNx86 plus an AND.
687 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom);
688 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom);
690 // We don't support sin/cos/fmod
691 setOperationAction(ISD::FSIN , MVT::f64, Expand);
692 setOperationAction(ISD::FCOS , MVT::f64, Expand);
693 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
694 setOperationAction(ISD::FSIN , MVT::f32, Expand);
695 setOperationAction(ISD::FCOS , MVT::f32, Expand);
696 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
698 // Expand FP immediates into loads from the stack, except for the special
700 addLegalFPImmediate(APFloat(+0.0)); // xorpd
701 addLegalFPImmediate(APFloat(+0.0f)); // xorps
702 } else if (!TM.Options.UseSoftFloat && X86ScalarSSEf32) {
703 // Use SSE for f32, x87 for f64.
704 // Set up the FP register classes.
705 addRegisterClass(MVT::f32, &X86::FR32RegClass);
706 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
708 // Use ANDPS to simulate FABS.
709 setOperationAction(ISD::FABS , MVT::f32, Custom);
711 // Use XORP to simulate FNEG.
712 setOperationAction(ISD::FNEG , MVT::f32, Custom);
714 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
716 // Use ANDPS and ORPS to simulate FCOPYSIGN.
717 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
718 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
720 // We don't support sin/cos/fmod
721 setOperationAction(ISD::FSIN , MVT::f32, Expand);
722 setOperationAction(ISD::FCOS , MVT::f32, Expand);
723 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
725 // Special cases we handle for FP constants.
726 addLegalFPImmediate(APFloat(+0.0f)); // xorps
727 addLegalFPImmediate(APFloat(+0.0)); // FLD0
728 addLegalFPImmediate(APFloat(+1.0)); // FLD1
729 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
730 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
732 if (!TM.Options.UnsafeFPMath) {
733 setOperationAction(ISD::FSIN , MVT::f64, Expand);
734 setOperationAction(ISD::FCOS , MVT::f64, Expand);
735 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
737 } else if (!TM.Options.UseSoftFloat) {
738 // f32 and f64 in x87.
739 // Set up the FP register classes.
740 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
741 addRegisterClass(MVT::f32, &X86::RFP32RegClass);
743 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
744 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
745 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
746 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
748 if (!TM.Options.UnsafeFPMath) {
749 setOperationAction(ISD::FSIN , MVT::f64, Expand);
750 setOperationAction(ISD::FSIN , MVT::f32, Expand);
751 setOperationAction(ISD::FCOS , MVT::f64, Expand);
752 setOperationAction(ISD::FCOS , MVT::f32, Expand);
753 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
754 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
756 addLegalFPImmediate(APFloat(+0.0)); // FLD0
757 addLegalFPImmediate(APFloat(+1.0)); // FLD1
758 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
759 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
760 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
761 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
762 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
763 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
766 // We don't support FMA.
767 setOperationAction(ISD::FMA, MVT::f64, Expand);
768 setOperationAction(ISD::FMA, MVT::f32, Expand);
770 // Long double always uses X87.
771 if (!TM.Options.UseSoftFloat) {
772 addRegisterClass(MVT::f80, &X86::RFP80RegClass);
773 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
774 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
776 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended);
777 addLegalFPImmediate(TmpFlt); // FLD0
779 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
782 APFloat TmpFlt2(+1.0);
783 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
785 addLegalFPImmediate(TmpFlt2); // FLD1
786 TmpFlt2.changeSign();
787 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
790 if (!TM.Options.UnsafeFPMath) {
791 setOperationAction(ISD::FSIN , MVT::f80, Expand);
792 setOperationAction(ISD::FCOS , MVT::f80, Expand);
793 setOperationAction(ISD::FSINCOS, MVT::f80, Expand);
796 setOperationAction(ISD::FFLOOR, MVT::f80, Expand);
797 setOperationAction(ISD::FCEIL, MVT::f80, Expand);
798 setOperationAction(ISD::FTRUNC, MVT::f80, Expand);
799 setOperationAction(ISD::FRINT, MVT::f80, Expand);
800 setOperationAction(ISD::FNEARBYINT, MVT::f80, Expand);
801 setOperationAction(ISD::FMA, MVT::f80, Expand);
804 // Always use a library call for pow.
805 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
806 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
807 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
809 setOperationAction(ISD::FLOG, MVT::f80, Expand);
810 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
811 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
812 setOperationAction(ISD::FEXP, MVT::f80, Expand);
813 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
815 // First set operation action for all vector types to either promote
816 // (for widening) or expand (for scalarization). Then we will selectively
817 // turn on ones that can be effectively codegen'd.
818 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
819 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
820 MVT VT = (MVT::SimpleValueType)i;
821 setOperationAction(ISD::ADD , VT, Expand);
822 setOperationAction(ISD::SUB , VT, Expand);
823 setOperationAction(ISD::FADD, VT, Expand);
824 setOperationAction(ISD::FNEG, VT, Expand);
825 setOperationAction(ISD::FSUB, VT, Expand);
826 setOperationAction(ISD::MUL , VT, Expand);
827 setOperationAction(ISD::FMUL, VT, Expand);
828 setOperationAction(ISD::SDIV, VT, Expand);
829 setOperationAction(ISD::UDIV, VT, Expand);
830 setOperationAction(ISD::FDIV, VT, Expand);
831 setOperationAction(ISD::SREM, VT, Expand);
832 setOperationAction(ISD::UREM, VT, Expand);
833 setOperationAction(ISD::LOAD, VT, Expand);
834 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);
835 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT,Expand);
836 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
837 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT,Expand);
838 setOperationAction(ISD::INSERT_SUBVECTOR, VT,Expand);
839 setOperationAction(ISD::FABS, VT, Expand);
840 setOperationAction(ISD::FSIN, VT, Expand);
841 setOperationAction(ISD::FSINCOS, VT, Expand);
842 setOperationAction(ISD::FCOS, VT, Expand);
843 setOperationAction(ISD::FSINCOS, VT, Expand);
844 setOperationAction(ISD::FREM, VT, Expand);
845 setOperationAction(ISD::FMA, VT, Expand);
846 setOperationAction(ISD::FPOWI, VT, Expand);
847 setOperationAction(ISD::FSQRT, VT, Expand);
848 setOperationAction(ISD::FCOPYSIGN, VT, Expand);
849 setOperationAction(ISD::FFLOOR, VT, Expand);
850 setOperationAction(ISD::FCEIL, VT, Expand);
851 setOperationAction(ISD::FTRUNC, VT, Expand);
852 setOperationAction(ISD::FRINT, VT, Expand);
853 setOperationAction(ISD::FNEARBYINT, VT, Expand);
854 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
855 setOperationAction(ISD::MULHS, VT, Expand);
856 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
857 setOperationAction(ISD::MULHU, VT, Expand);
858 setOperationAction(ISD::SDIVREM, VT, Expand);
859 setOperationAction(ISD::UDIVREM, VT, Expand);
860 setOperationAction(ISD::FPOW, VT, Expand);
861 setOperationAction(ISD::CTPOP, VT, Expand);
862 setOperationAction(ISD::CTTZ, VT, Expand);
863 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
864 setOperationAction(ISD::CTLZ, VT, Expand);
865 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
866 setOperationAction(ISD::SHL, VT, Expand);
867 setOperationAction(ISD::SRA, VT, Expand);
868 setOperationAction(ISD::SRL, VT, Expand);
869 setOperationAction(ISD::ROTL, VT, Expand);
870 setOperationAction(ISD::ROTR, VT, Expand);
871 setOperationAction(ISD::BSWAP, VT, Expand);
872 setOperationAction(ISD::SETCC, VT, Expand);
873 setOperationAction(ISD::FLOG, VT, Expand);
874 setOperationAction(ISD::FLOG2, VT, Expand);
875 setOperationAction(ISD::FLOG10, VT, Expand);
876 setOperationAction(ISD::FEXP, VT, Expand);
877 setOperationAction(ISD::FEXP2, VT, Expand);
878 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
879 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
880 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
881 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
882 setOperationAction(ISD::SIGN_EXTEND_INREG, VT,Expand);
883 setOperationAction(ISD::TRUNCATE, VT, Expand);
884 setOperationAction(ISD::SIGN_EXTEND, VT, Expand);
885 setOperationAction(ISD::ZERO_EXTEND, VT, Expand);
886 setOperationAction(ISD::ANY_EXTEND, VT, Expand);
887 setOperationAction(ISD::VSELECT, VT, Expand);
888 setOperationAction(ISD::SELECT_CC, VT, Expand);
889 for (int InnerVT = MVT::FIRST_VECTOR_VALUETYPE;
890 InnerVT <= MVT::LAST_VECTOR_VALUETYPE; ++InnerVT)
891 setTruncStoreAction(VT,
892 (MVT::SimpleValueType)InnerVT, Expand);
893 setLoadExtAction(ISD::SEXTLOAD, VT, Expand);
894 setLoadExtAction(ISD::ZEXTLOAD, VT, Expand);
896 // N.b. ISD::EXTLOAD legality is basically ignored except for i1-like types,
897 // we have to deal with them whether we ask for Expansion or not. Setting
898 // Expand causes its own optimisation problems though, so leave them legal.
899 if (VT.getVectorElementType() == MVT::i1)
900 setLoadExtAction(ISD::EXTLOAD, VT, Expand);
903 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
904 // with -msoft-float, disable use of MMX as well.
905 if (!TM.Options.UseSoftFloat && Subtarget->hasMMX()) {
906 addRegisterClass(MVT::x86mmx, &X86::VR64RegClass);
907 // No operations on x86mmx supported, everything uses intrinsics.
910 // MMX-sized vectors (other than x86mmx) are expected to be expanded
911 // into smaller operations.
912 setOperationAction(ISD::MULHS, MVT::v8i8, Expand);
913 setOperationAction(ISD::MULHS, MVT::v4i16, Expand);
914 setOperationAction(ISD::MULHS, MVT::v2i32, Expand);
915 setOperationAction(ISD::MULHS, MVT::v1i64, Expand);
916 setOperationAction(ISD::AND, MVT::v8i8, Expand);
917 setOperationAction(ISD::AND, MVT::v4i16, Expand);
918 setOperationAction(ISD::AND, MVT::v2i32, Expand);
919 setOperationAction(ISD::AND, MVT::v1i64, Expand);
920 setOperationAction(ISD::OR, MVT::v8i8, Expand);
921 setOperationAction(ISD::OR, MVT::v4i16, Expand);
922 setOperationAction(ISD::OR, MVT::v2i32, Expand);
923 setOperationAction(ISD::OR, MVT::v1i64, Expand);
924 setOperationAction(ISD::XOR, MVT::v8i8, Expand);
925 setOperationAction(ISD::XOR, MVT::v4i16, Expand);
926 setOperationAction(ISD::XOR, MVT::v2i32, Expand);
927 setOperationAction(ISD::XOR, MVT::v1i64, Expand);
928 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Expand);
929 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Expand);
930 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i32, Expand);
931 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Expand);
932 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand);
933 setOperationAction(ISD::SELECT, MVT::v8i8, Expand);
934 setOperationAction(ISD::SELECT, MVT::v4i16, Expand);
935 setOperationAction(ISD::SELECT, MVT::v2i32, Expand);
936 setOperationAction(ISD::SELECT, MVT::v1i64, Expand);
937 setOperationAction(ISD::BITCAST, MVT::v8i8, Expand);
938 setOperationAction(ISD::BITCAST, MVT::v4i16, Expand);
939 setOperationAction(ISD::BITCAST, MVT::v2i32, Expand);
940 setOperationAction(ISD::BITCAST, MVT::v1i64, Expand);
942 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE1()) {
943 addRegisterClass(MVT::v4f32, &X86::VR128RegClass);
945 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
946 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
947 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
948 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
949 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
950 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
951 setOperationAction(ISD::FABS, MVT::v4f32, Custom);
952 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
953 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
954 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
955 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
956 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
959 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE2()) {
960 addRegisterClass(MVT::v2f64, &X86::VR128RegClass);
962 // FIXME: Unfortunately, -soft-float and -no-implicit-float mean XMM
963 // registers cannot be used even for integer operations.
964 addRegisterClass(MVT::v16i8, &X86::VR128RegClass);
965 addRegisterClass(MVT::v8i16, &X86::VR128RegClass);
966 addRegisterClass(MVT::v4i32, &X86::VR128RegClass);
967 addRegisterClass(MVT::v2i64, &X86::VR128RegClass);
969 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
970 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
971 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
972 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
973 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
974 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
975 setOperationAction(ISD::UMUL_LOHI, MVT::v4i32, Custom);
976 setOperationAction(ISD::SMUL_LOHI, MVT::v4i32, Custom);
977 setOperationAction(ISD::MULHU, MVT::v8i16, Legal);
978 setOperationAction(ISD::MULHS, MVT::v8i16, Legal);
979 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
980 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
981 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
982 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
983 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
984 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
985 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
986 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
987 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
988 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
989 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
990 setOperationAction(ISD::FABS, MVT::v2f64, Custom);
992 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
993 setOperationAction(ISD::SETCC, MVT::v16i8, Custom);
994 setOperationAction(ISD::SETCC, MVT::v8i16, Custom);
995 setOperationAction(ISD::SETCC, MVT::v4i32, Custom);
997 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
998 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
999 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
1000 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
1001 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
1003 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
1004 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
1005 MVT VT = (MVT::SimpleValueType)i;
1006 // Do not attempt to custom lower non-power-of-2 vectors
1007 if (!isPowerOf2_32(VT.getVectorNumElements()))
1009 // Do not attempt to custom lower non-128-bit vectors
1010 if (!VT.is128BitVector())
1012 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1013 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1014 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1017 // We support custom legalizing of sext and anyext loads for specific
1018 // memory vector types which we can load as a scalar (or sequence of
1019 // scalars) and extend in-register to a legal 128-bit vector type. For sext
1020 // loads these must work with a single scalar load.
1021 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i8, Custom);
1022 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i16, Custom);
1023 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i8, Custom);
1024 setLoadExtAction(ISD::EXTLOAD, MVT::v2i8, Custom);
1025 setLoadExtAction(ISD::EXTLOAD, MVT::v2i16, Custom);
1026 setLoadExtAction(ISD::EXTLOAD, MVT::v2i32, Custom);
1027 setLoadExtAction(ISD::EXTLOAD, MVT::v4i8, Custom);
1028 setLoadExtAction(ISD::EXTLOAD, MVT::v4i16, Custom);
1029 setLoadExtAction(ISD::EXTLOAD, MVT::v8i8, Custom);
1031 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
1032 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
1033 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
1034 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
1035 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
1036 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
1038 if (Subtarget->is64Bit()) {
1039 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
1040 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
1043 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
1044 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
1045 MVT VT = (MVT::SimpleValueType)i;
1047 // Do not attempt to promote non-128-bit vectors
1048 if (!VT.is128BitVector())
1051 setOperationAction(ISD::AND, VT, Promote);
1052 AddPromotedToType (ISD::AND, VT, MVT::v2i64);
1053 setOperationAction(ISD::OR, VT, Promote);
1054 AddPromotedToType (ISD::OR, VT, MVT::v2i64);
1055 setOperationAction(ISD::XOR, VT, Promote);
1056 AddPromotedToType (ISD::XOR, VT, MVT::v2i64);
1057 setOperationAction(ISD::LOAD, VT, Promote);
1058 AddPromotedToType (ISD::LOAD, VT, MVT::v2i64);
1059 setOperationAction(ISD::SELECT, VT, Promote);
1060 AddPromotedToType (ISD::SELECT, VT, MVT::v2i64);
1063 // Custom lower v2i64 and v2f64 selects.
1064 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
1065 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
1066 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
1067 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
1069 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
1070 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
1072 setOperationAction(ISD::UINT_TO_FP, MVT::v4i8, Custom);
1073 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);
1074 // As there is no 64-bit GPR available, we need build a special custom
1075 // sequence to convert from v2i32 to v2f32.
1076 if (!Subtarget->is64Bit())
1077 setOperationAction(ISD::UINT_TO_FP, MVT::v2f32, Custom);
1079 setOperationAction(ISD::FP_EXTEND, MVT::v2f32, Custom);
1080 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Custom);
1082 setLoadExtAction(ISD::EXTLOAD, MVT::v2f32, Legal);
1084 setOperationAction(ISD::BITCAST, MVT::v2i32, Custom);
1085 setOperationAction(ISD::BITCAST, MVT::v4i16, Custom);
1086 setOperationAction(ISD::BITCAST, MVT::v8i8, Custom);
1089 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE41()) {
1090 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
1091 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
1092 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
1093 setOperationAction(ISD::FRINT, MVT::f32, Legal);
1094 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
1095 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
1096 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
1097 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
1098 setOperationAction(ISD::FRINT, MVT::f64, Legal);
1099 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
1101 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal);
1102 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal);
1103 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal);
1104 setOperationAction(ISD::FRINT, MVT::v4f32, Legal);
1105 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal);
1106 setOperationAction(ISD::FFLOOR, MVT::v2f64, Legal);
1107 setOperationAction(ISD::FCEIL, MVT::v2f64, Legal);
1108 setOperationAction(ISD::FTRUNC, MVT::v2f64, Legal);
1109 setOperationAction(ISD::FRINT, MVT::v2f64, Legal);
1110 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Legal);
1112 // FIXME: Do we need to handle scalar-to-vector here?
1113 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
1115 setOperationAction(ISD::VSELECT, MVT::v2f64, Custom);
1116 setOperationAction(ISD::VSELECT, MVT::v2i64, Custom);
1117 setOperationAction(ISD::VSELECT, MVT::v4i32, Custom);
1118 setOperationAction(ISD::VSELECT, MVT::v4f32, Custom);
1119 setOperationAction(ISD::VSELECT, MVT::v8i16, Custom);
1120 // There is no BLENDI for byte vectors. We don't need to custom lower
1121 // some vselects for now.
1122 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
1124 // SSE41 brings specific instructions for doing vector sign extend even in
1125 // cases where we don't have SRA.
1126 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i8, Custom);
1127 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i16, Custom);
1128 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i32, Custom);
1130 // i8 and i16 vectors are custom because the source register and source
1131 // source memory operand types are not the same width. f32 vectors are
1132 // custom since the immediate controlling the insert encodes additional
1134 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
1135 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
1136 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
1137 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
1139 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
1140 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
1141 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
1142 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
1144 // FIXME: these should be Legal, but that's only for the case where
1145 // the index is constant. For now custom expand to deal with that.
1146 if (Subtarget->is64Bit()) {
1147 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
1148 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
1152 if (Subtarget->hasSSE2()) {
1153 setOperationAction(ISD::SRL, MVT::v8i16, Custom);
1154 setOperationAction(ISD::SRL, MVT::v16i8, Custom);
1156 setOperationAction(ISD::SHL, MVT::v8i16, Custom);
1157 setOperationAction(ISD::SHL, MVT::v16i8, Custom);
1159 setOperationAction(ISD::SRA, MVT::v8i16, Custom);
1160 setOperationAction(ISD::SRA, MVT::v16i8, Custom);
1162 // In the customized shift lowering, the legal cases in AVX2 will be
1164 setOperationAction(ISD::SRL, MVT::v2i64, Custom);
1165 setOperationAction(ISD::SRL, MVT::v4i32, Custom);
1167 setOperationAction(ISD::SHL, MVT::v2i64, Custom);
1168 setOperationAction(ISD::SHL, MVT::v4i32, Custom);
1170 setOperationAction(ISD::SRA, MVT::v4i32, Custom);
1173 if (!TM.Options.UseSoftFloat && Subtarget->hasFp256()) {
1174 addRegisterClass(MVT::v32i8, &X86::VR256RegClass);
1175 addRegisterClass(MVT::v16i16, &X86::VR256RegClass);
1176 addRegisterClass(MVT::v8i32, &X86::VR256RegClass);
1177 addRegisterClass(MVT::v8f32, &X86::VR256RegClass);
1178 addRegisterClass(MVT::v4i64, &X86::VR256RegClass);
1179 addRegisterClass(MVT::v4f64, &X86::VR256RegClass);
1181 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
1182 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
1183 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
1185 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
1186 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
1187 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
1188 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
1189 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
1190 setOperationAction(ISD::FFLOOR, MVT::v8f32, Legal);
1191 setOperationAction(ISD::FCEIL, MVT::v8f32, Legal);
1192 setOperationAction(ISD::FTRUNC, MVT::v8f32, Legal);
1193 setOperationAction(ISD::FRINT, MVT::v8f32, Legal);
1194 setOperationAction(ISD::FNEARBYINT, MVT::v8f32, Legal);
1195 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
1196 setOperationAction(ISD::FABS, MVT::v8f32, Custom);
1198 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
1199 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
1200 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
1201 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
1202 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
1203 setOperationAction(ISD::FFLOOR, MVT::v4f64, Legal);
1204 setOperationAction(ISD::FCEIL, MVT::v4f64, Legal);
1205 setOperationAction(ISD::FTRUNC, MVT::v4f64, Legal);
1206 setOperationAction(ISD::FRINT, MVT::v4f64, Legal);
1207 setOperationAction(ISD::FNEARBYINT, MVT::v4f64, Legal);
1208 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
1209 setOperationAction(ISD::FABS, MVT::v4f64, Custom);
1211 // (fp_to_int:v8i16 (v8f32 ..)) requires the result type to be promoted
1212 // even though v8i16 is a legal type.
1213 setOperationAction(ISD::FP_TO_SINT, MVT::v8i16, Promote);
1214 setOperationAction(ISD::FP_TO_UINT, MVT::v8i16, Promote);
1215 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
1217 setOperationAction(ISD::SINT_TO_FP, MVT::v8i16, Promote);
1218 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
1219 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal);
1221 setOperationAction(ISD::UINT_TO_FP, MVT::v8i8, Custom);
1222 setOperationAction(ISD::UINT_TO_FP, MVT::v8i16, Custom);
1224 setLoadExtAction(ISD::EXTLOAD, MVT::v4f32, Legal);
1226 setOperationAction(ISD::SRL, MVT::v16i16, Custom);
1227 setOperationAction(ISD::SRL, MVT::v32i8, Custom);
1229 setOperationAction(ISD::SHL, MVT::v16i16, Custom);
1230 setOperationAction(ISD::SHL, MVT::v32i8, Custom);
1232 setOperationAction(ISD::SRA, MVT::v16i16, Custom);
1233 setOperationAction(ISD::SRA, MVT::v32i8, Custom);
1235 setOperationAction(ISD::SETCC, MVT::v32i8, Custom);
1236 setOperationAction(ISD::SETCC, MVT::v16i16, Custom);
1237 setOperationAction(ISD::SETCC, MVT::v8i32, Custom);
1238 setOperationAction(ISD::SETCC, MVT::v4i64, Custom);
1240 setOperationAction(ISD::SELECT, MVT::v4f64, Custom);
1241 setOperationAction(ISD::SELECT, MVT::v4i64, Custom);
1242 setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
1244 setOperationAction(ISD::VSELECT, MVT::v4f64, Custom);
1245 setOperationAction(ISD::VSELECT, MVT::v4i64, Custom);
1246 setOperationAction(ISD::VSELECT, MVT::v8i32, Custom);
1247 setOperationAction(ISD::VSELECT, MVT::v8f32, Custom);
1249 setOperationAction(ISD::SIGN_EXTEND, MVT::v4i64, Custom);
1250 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i32, Custom);
1251 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1252 setOperationAction(ISD::ZERO_EXTEND, MVT::v4i64, Custom);
1253 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i32, Custom);
1254 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i16, Custom);
1255 setOperationAction(ISD::ANY_EXTEND, MVT::v4i64, Custom);
1256 setOperationAction(ISD::ANY_EXTEND, MVT::v8i32, Custom);
1257 setOperationAction(ISD::ANY_EXTEND, MVT::v16i16, Custom);
1258 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1259 setOperationAction(ISD::TRUNCATE, MVT::v8i16, Custom);
1260 setOperationAction(ISD::TRUNCATE, MVT::v4i32, Custom);
1262 if (Subtarget->hasFMA() || Subtarget->hasFMA4()) {
1263 setOperationAction(ISD::FMA, MVT::v8f32, Legal);
1264 setOperationAction(ISD::FMA, MVT::v4f64, Legal);
1265 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
1266 setOperationAction(ISD::FMA, MVT::v2f64, Legal);
1267 setOperationAction(ISD::FMA, MVT::f32, Legal);
1268 setOperationAction(ISD::FMA, MVT::f64, Legal);
1271 if (Subtarget->hasInt256()) {
1272 setOperationAction(ISD::ADD, MVT::v4i64, Legal);
1273 setOperationAction(ISD::ADD, MVT::v8i32, Legal);
1274 setOperationAction(ISD::ADD, MVT::v16i16, Legal);
1275 setOperationAction(ISD::ADD, MVT::v32i8, Legal);
1277 setOperationAction(ISD::SUB, MVT::v4i64, Legal);
1278 setOperationAction(ISD::SUB, MVT::v8i32, Legal);
1279 setOperationAction(ISD::SUB, MVT::v16i16, Legal);
1280 setOperationAction(ISD::SUB, MVT::v32i8, Legal);
1282 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1283 setOperationAction(ISD::MUL, MVT::v8i32, Legal);
1284 setOperationAction(ISD::MUL, MVT::v16i16, Legal);
1285 // Don't lower v32i8 because there is no 128-bit byte mul
1287 setOperationAction(ISD::UMUL_LOHI, MVT::v8i32, Custom);
1288 setOperationAction(ISD::SMUL_LOHI, MVT::v8i32, Custom);
1289 setOperationAction(ISD::MULHU, MVT::v16i16, Legal);
1290 setOperationAction(ISD::MULHS, MVT::v16i16, Legal);
1292 setOperationAction(ISD::VSELECT, MVT::v16i16, Custom);
1293 setOperationAction(ISD::VSELECT, MVT::v32i8, Legal);
1295 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
1296 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
1297 setOperationAction(ISD::ADD, MVT::v16i16, Custom);
1298 setOperationAction(ISD::ADD, MVT::v32i8, Custom);
1300 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
1301 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
1302 setOperationAction(ISD::SUB, MVT::v16i16, Custom);
1303 setOperationAction(ISD::SUB, MVT::v32i8, Custom);
1305 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1306 setOperationAction(ISD::MUL, MVT::v8i32, Custom);
1307 setOperationAction(ISD::MUL, MVT::v16i16, Custom);
1308 // Don't lower v32i8 because there is no 128-bit byte mul
1311 // In the customized shift lowering, the legal cases in AVX2 will be
1313 setOperationAction(ISD::SRL, MVT::v4i64, Custom);
1314 setOperationAction(ISD::SRL, MVT::v8i32, Custom);
1316 setOperationAction(ISD::SHL, MVT::v4i64, Custom);
1317 setOperationAction(ISD::SHL, MVT::v8i32, Custom);
1319 setOperationAction(ISD::SRA, MVT::v8i32, Custom);
1321 // Custom lower several nodes for 256-bit types.
1322 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
1323 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
1324 MVT VT = (MVT::SimpleValueType)i;
1326 // Extract subvector is special because the value type
1327 // (result) is 128-bit but the source is 256-bit wide.
1328 if (VT.is128BitVector())
1329 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1331 // Do not attempt to custom lower other non-256-bit vectors
1332 if (!VT.is256BitVector())
1335 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1336 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1337 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1338 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1339 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1340 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1341 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom);
1344 // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64.
1345 for (int i = MVT::v32i8; i != MVT::v4i64; ++i) {
1346 MVT VT = (MVT::SimpleValueType)i;
1348 // Do not attempt to promote non-256-bit vectors
1349 if (!VT.is256BitVector())
1352 setOperationAction(ISD::AND, VT, Promote);
1353 AddPromotedToType (ISD::AND, VT, MVT::v4i64);
1354 setOperationAction(ISD::OR, VT, Promote);
1355 AddPromotedToType (ISD::OR, VT, MVT::v4i64);
1356 setOperationAction(ISD::XOR, VT, Promote);
1357 AddPromotedToType (ISD::XOR, VT, MVT::v4i64);
1358 setOperationAction(ISD::LOAD, VT, Promote);
1359 AddPromotedToType (ISD::LOAD, VT, MVT::v4i64);
1360 setOperationAction(ISD::SELECT, VT, Promote);
1361 AddPromotedToType (ISD::SELECT, VT, MVT::v4i64);
1365 if (!TM.Options.UseSoftFloat && Subtarget->hasAVX512()) {
1366 addRegisterClass(MVT::v16i32, &X86::VR512RegClass);
1367 addRegisterClass(MVT::v16f32, &X86::VR512RegClass);
1368 addRegisterClass(MVT::v8i64, &X86::VR512RegClass);
1369 addRegisterClass(MVT::v8f64, &X86::VR512RegClass);
1371 addRegisterClass(MVT::i1, &X86::VK1RegClass);
1372 addRegisterClass(MVT::v8i1, &X86::VK8RegClass);
1373 addRegisterClass(MVT::v16i1, &X86::VK16RegClass);
1375 setOperationAction(ISD::BR_CC, MVT::i1, Expand);
1376 setOperationAction(ISD::SETCC, MVT::i1, Custom);
1377 setOperationAction(ISD::XOR, MVT::i1, Legal);
1378 setOperationAction(ISD::OR, MVT::i1, Legal);
1379 setOperationAction(ISD::AND, MVT::i1, Legal);
1380 setLoadExtAction(ISD::EXTLOAD, MVT::v8f32, Legal);
1381 setOperationAction(ISD::LOAD, MVT::v16f32, Legal);
1382 setOperationAction(ISD::LOAD, MVT::v8f64, Legal);
1383 setOperationAction(ISD::LOAD, MVT::v8i64, Legal);
1384 setOperationAction(ISD::LOAD, MVT::v16i32, Legal);
1385 setOperationAction(ISD::LOAD, MVT::v16i1, Legal);
1387 setOperationAction(ISD::FADD, MVT::v16f32, Legal);
1388 setOperationAction(ISD::FSUB, MVT::v16f32, Legal);
1389 setOperationAction(ISD::FMUL, MVT::v16f32, Legal);
1390 setOperationAction(ISD::FDIV, MVT::v16f32, Legal);
1391 setOperationAction(ISD::FSQRT, MVT::v16f32, Legal);
1392 setOperationAction(ISD::FNEG, MVT::v16f32, Custom);
1394 setOperationAction(ISD::FADD, MVT::v8f64, Legal);
1395 setOperationAction(ISD::FSUB, MVT::v8f64, Legal);
1396 setOperationAction(ISD::FMUL, MVT::v8f64, Legal);
1397 setOperationAction(ISD::FDIV, MVT::v8f64, Legal);
1398 setOperationAction(ISD::FSQRT, MVT::v8f64, Legal);
1399 setOperationAction(ISD::FNEG, MVT::v8f64, Custom);
1400 setOperationAction(ISD::FMA, MVT::v8f64, Legal);
1401 setOperationAction(ISD::FMA, MVT::v16f32, Legal);
1403 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Legal);
1404 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Legal);
1405 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Legal);
1406 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Legal);
1407 if (Subtarget->is64Bit()) {
1408 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Legal);
1409 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Legal);
1410 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Legal);
1411 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Legal);
1413 setOperationAction(ISD::FP_TO_SINT, MVT::v16i32, Legal);
1414 setOperationAction(ISD::FP_TO_UINT, MVT::v16i32, Legal);
1415 setOperationAction(ISD::FP_TO_UINT, MVT::v8i32, Legal);
1416 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
1417 setOperationAction(ISD::SINT_TO_FP, MVT::v16i32, Legal);
1418 setOperationAction(ISD::UINT_TO_FP, MVT::v16i32, Legal);
1419 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Legal);
1420 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
1421 setOperationAction(ISD::FP_ROUND, MVT::v8f32, Legal);
1422 setOperationAction(ISD::FP_EXTEND, MVT::v8f32, Legal);
1424 setOperationAction(ISD::TRUNCATE, MVT::i1, Custom);
1425 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1426 setOperationAction(ISD::TRUNCATE, MVT::v8i32, Custom);
1427 setOperationAction(ISD::TRUNCATE, MVT::v8i1, Custom);
1428 setOperationAction(ISD::TRUNCATE, MVT::v16i1, Custom);
1429 setOperationAction(ISD::TRUNCATE, MVT::v16i16, Custom);
1430 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i32, Custom);
1431 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i64, Custom);
1432 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i32, Custom);
1433 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i64, Custom);
1434 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i8, Custom);
1435 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i16, Custom);
1436 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1438 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f64, Custom);
1439 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i64, Custom);
1440 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16f32, Custom);
1441 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i32, Custom);
1442 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i1, Custom);
1443 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i1, Legal);
1445 setOperationAction(ISD::SETCC, MVT::v16i1, Custom);
1446 setOperationAction(ISD::SETCC, MVT::v8i1, Custom);
1448 setOperationAction(ISD::MUL, MVT::v8i64, Custom);
1450 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i1, Custom);
1451 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i1, Custom);
1452 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i1, Custom);
1453 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i1, Custom);
1454 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i1, Custom);
1455 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i1, Custom);
1456 setOperationAction(ISD::SELECT, MVT::v8f64, Custom);
1457 setOperationAction(ISD::SELECT, MVT::v8i64, Custom);
1458 setOperationAction(ISD::SELECT, MVT::v16f32, Custom);
1460 setOperationAction(ISD::ADD, MVT::v8i64, Legal);
1461 setOperationAction(ISD::ADD, MVT::v16i32, Legal);
1463 setOperationAction(ISD::SUB, MVT::v8i64, Legal);
1464 setOperationAction(ISD::SUB, MVT::v16i32, Legal);
1466 setOperationAction(ISD::MUL, MVT::v16i32, Legal);
1468 setOperationAction(ISD::SRL, MVT::v8i64, Custom);
1469 setOperationAction(ISD::SRL, MVT::v16i32, Custom);
1471 setOperationAction(ISD::SHL, MVT::v8i64, Custom);
1472 setOperationAction(ISD::SHL, MVT::v16i32, Custom);
1474 setOperationAction(ISD::SRA, MVT::v8i64, Custom);
1475 setOperationAction(ISD::SRA, MVT::v16i32, Custom);
1477 setOperationAction(ISD::AND, MVT::v8i64, Legal);
1478 setOperationAction(ISD::OR, MVT::v8i64, Legal);
1479 setOperationAction(ISD::XOR, MVT::v8i64, Legal);
1480 setOperationAction(ISD::AND, MVT::v16i32, Legal);
1481 setOperationAction(ISD::OR, MVT::v16i32, Legal);
1482 setOperationAction(ISD::XOR, MVT::v16i32, Legal);
1484 if (Subtarget->hasCDI()) {
1485 setOperationAction(ISD::CTLZ, MVT::v8i64, Legal);
1486 setOperationAction(ISD::CTLZ, MVT::v16i32, Legal);
1489 // Custom lower several nodes.
1490 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
1491 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
1492 MVT VT = (MVT::SimpleValueType)i;
1494 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1495 // Extract subvector is special because the value type
1496 // (result) is 256/128-bit but the source is 512-bit wide.
1497 if (VT.is128BitVector() || VT.is256BitVector())
1498 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1500 if (VT.getVectorElementType() == MVT::i1)
1501 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal);
1503 // Do not attempt to custom lower other non-512-bit vectors
1504 if (!VT.is512BitVector())
1507 if ( EltSize >= 32) {
1508 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1509 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1510 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1511 setOperationAction(ISD::VSELECT, VT, Legal);
1512 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1513 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1514 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1517 for (int i = MVT::v32i8; i != MVT::v8i64; ++i) {
1518 MVT VT = (MVT::SimpleValueType)i;
1520 // Do not attempt to promote non-256-bit vectors
1521 if (!VT.is512BitVector())
1524 setOperationAction(ISD::SELECT, VT, Promote);
1525 AddPromotedToType (ISD::SELECT, VT, MVT::v8i64);
1529 if (!TM.Options.UseSoftFloat && Subtarget->hasBWI()) {
1530 addRegisterClass(MVT::v32i16, &X86::VR512RegClass);
1531 addRegisterClass(MVT::v64i8, &X86::VR512RegClass);
1533 addRegisterClass(MVT::v32i1, &X86::VK32RegClass);
1534 addRegisterClass(MVT::v64i1, &X86::VK64RegClass);
1536 setOperationAction(ISD::LOAD, MVT::v32i16, Legal);
1537 setOperationAction(ISD::LOAD, MVT::v64i8, Legal);
1538 setOperationAction(ISD::SETCC, MVT::v32i1, Custom);
1539 setOperationAction(ISD::SETCC, MVT::v64i1, Custom);
1541 for (int i = MVT::v32i8; i != MVT::v8i64; ++i) {
1542 const MVT VT = (MVT::SimpleValueType)i;
1544 const unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1546 // Do not attempt to promote non-256-bit vectors
1547 if (!VT.is512BitVector())
1550 if ( EltSize < 32) {
1551 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1552 setOperationAction(ISD::VSELECT, VT, Legal);
1557 if (!TM.Options.UseSoftFloat && Subtarget->hasVLX()) {
1558 addRegisterClass(MVT::v4i1, &X86::VK4RegClass);
1559 addRegisterClass(MVT::v2i1, &X86::VK2RegClass);
1561 setOperationAction(ISD::SETCC, MVT::v4i1, Custom);
1562 setOperationAction(ISD::SETCC, MVT::v2i1, Custom);
1565 // SIGN_EXTEND_INREGs are evaluated by the extend type. Handle the expansion
1566 // of this type with custom code.
1567 for (int VT = MVT::FIRST_VECTOR_VALUETYPE;
1568 VT != MVT::LAST_VECTOR_VALUETYPE; VT++) {
1569 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,
1573 // We want to custom lower some of our intrinsics.
1574 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
1575 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
1576 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
1577 if (!Subtarget->is64Bit())
1578 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i64, Custom);
1580 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't
1581 // handle type legalization for these operations here.
1583 // FIXME: We really should do custom legalization for addition and
1584 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better
1585 // than generic legalization for 64-bit multiplication-with-overflow, though.
1586 for (unsigned i = 0, e = 3+Subtarget->is64Bit(); i != e; ++i) {
1587 // Add/Sub/Mul with overflow operations are custom lowered.
1589 setOperationAction(ISD::SADDO, VT, Custom);
1590 setOperationAction(ISD::UADDO, VT, Custom);
1591 setOperationAction(ISD::SSUBO, VT, Custom);
1592 setOperationAction(ISD::USUBO, VT, Custom);
1593 setOperationAction(ISD::SMULO, VT, Custom);
1594 setOperationAction(ISD::UMULO, VT, Custom);
1597 // There are no 8-bit 3-address imul/mul instructions
1598 setOperationAction(ISD::SMULO, MVT::i8, Expand);
1599 setOperationAction(ISD::UMULO, MVT::i8, Expand);
1601 if (!Subtarget->is64Bit()) {
1602 // These libcalls are not available in 32-bit.
1603 setLibcallName(RTLIB::SHL_I128, nullptr);
1604 setLibcallName(RTLIB::SRL_I128, nullptr);
1605 setLibcallName(RTLIB::SRA_I128, nullptr);
1608 // Combine sin / cos into one node or libcall if possible.
1609 if (Subtarget->hasSinCos()) {
1610 setLibcallName(RTLIB::SINCOS_F32, "sincosf");
1611 setLibcallName(RTLIB::SINCOS_F64, "sincos");
1612 if (Subtarget->isTargetDarwin()) {
1613 // For MacOSX, we don't want to the normal expansion of a libcall to
1614 // sincos. We want to issue a libcall to __sincos_stret to avoid memory
1616 setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
1617 setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
1621 if (Subtarget->isTargetWin64()) {
1622 setOperationAction(ISD::SDIV, MVT::i128, Custom);
1623 setOperationAction(ISD::UDIV, MVT::i128, Custom);
1624 setOperationAction(ISD::SREM, MVT::i128, Custom);
1625 setOperationAction(ISD::UREM, MVT::i128, Custom);
1626 setOperationAction(ISD::SDIVREM, MVT::i128, Custom);
1627 setOperationAction(ISD::UDIVREM, MVT::i128, Custom);
1630 // We have target-specific dag combine patterns for the following nodes:
1631 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
1632 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
1633 setTargetDAGCombine(ISD::VSELECT);
1634 setTargetDAGCombine(ISD::SELECT);
1635 setTargetDAGCombine(ISD::SHL);
1636 setTargetDAGCombine(ISD::SRA);
1637 setTargetDAGCombine(ISD::SRL);
1638 setTargetDAGCombine(ISD::OR);
1639 setTargetDAGCombine(ISD::AND);
1640 setTargetDAGCombine(ISD::ADD);
1641 setTargetDAGCombine(ISD::FADD);
1642 setTargetDAGCombine(ISD::FSUB);
1643 setTargetDAGCombine(ISD::FMA);
1644 setTargetDAGCombine(ISD::SUB);
1645 setTargetDAGCombine(ISD::LOAD);
1646 setTargetDAGCombine(ISD::STORE);
1647 setTargetDAGCombine(ISD::ZERO_EXTEND);
1648 setTargetDAGCombine(ISD::ANY_EXTEND);
1649 setTargetDAGCombine(ISD::SIGN_EXTEND);
1650 setTargetDAGCombine(ISD::SIGN_EXTEND_INREG);
1651 setTargetDAGCombine(ISD::TRUNCATE);
1652 setTargetDAGCombine(ISD::SINT_TO_FP);
1653 setTargetDAGCombine(ISD::SETCC);
1654 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
1655 setTargetDAGCombine(ISD::BUILD_VECTOR);
1656 if (Subtarget->is64Bit())
1657 setTargetDAGCombine(ISD::MUL);
1658 setTargetDAGCombine(ISD::XOR);
1660 computeRegisterProperties();
1662 // On Darwin, -Os means optimize for size without hurting performance,
1663 // do not reduce the limit.
1664 MaxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
1665 MaxStoresPerMemsetOptSize = Subtarget->isTargetDarwin() ? 16 : 8;
1666 MaxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores
1667 MaxStoresPerMemcpyOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1668 MaxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores
1669 MaxStoresPerMemmoveOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1670 setPrefLoopAlignment(4); // 2^4 bytes.
1672 // Predictable cmov don't hurt on atom because it's in-order.
1673 PredictableSelectIsExpensive = !Subtarget->isAtom();
1675 setPrefFunctionAlignment(4); // 2^4 bytes.
1677 verifyIntrinsicTables();
1680 // This has so far only been implemented for 64-bit MachO.
1681 bool X86TargetLowering::useLoadStackGuardNode() const {
1682 return Subtarget->getTargetTriple().getObjectFormat() == Triple::MachO &&
1683 Subtarget->is64Bit();
1686 TargetLoweringBase::LegalizeTypeAction
1687 X86TargetLowering::getPreferredVectorAction(EVT VT) const {
1688 if (ExperimentalVectorWideningLegalization &&
1689 VT.getVectorNumElements() != 1 &&
1690 VT.getVectorElementType().getSimpleVT() != MVT::i1)
1691 return TypeWidenVector;
1693 return TargetLoweringBase::getPreferredVectorAction(VT);
1696 EVT X86TargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
1698 return Subtarget->hasAVX512() ? MVT::i1: MVT::i8;
1700 const unsigned NumElts = VT.getVectorNumElements();
1701 const EVT EltVT = VT.getVectorElementType();
1702 if (VT.is512BitVector()) {
1703 if (Subtarget->hasAVX512())
1704 if (EltVT == MVT::i32 || EltVT == MVT::i64 ||
1705 EltVT == MVT::f32 || EltVT == MVT::f64)
1707 case 8: return MVT::v8i1;
1708 case 16: return MVT::v16i1;
1710 if (Subtarget->hasBWI())
1711 if (EltVT == MVT::i8 || EltVT == MVT::i16)
1713 case 32: return MVT::v32i1;
1714 case 64: return MVT::v64i1;
1718 if (VT.is256BitVector() || VT.is128BitVector()) {
1719 if (Subtarget->hasVLX())
1720 if (EltVT == MVT::i32 || EltVT == MVT::i64 ||
1721 EltVT == MVT::f32 || EltVT == MVT::f64)
1723 case 2: return MVT::v2i1;
1724 case 4: return MVT::v4i1;
1725 case 8: return MVT::v8i1;
1727 if (Subtarget->hasBWI() && Subtarget->hasVLX())
1728 if (EltVT == MVT::i8 || EltVT == MVT::i16)
1730 case 8: return MVT::v8i1;
1731 case 16: return MVT::v16i1;
1732 case 32: return MVT::v32i1;
1736 return VT.changeVectorElementTypeToInteger();
1739 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
1740 /// the desired ByVal argument alignment.
1741 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) {
1744 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1745 if (VTy->getBitWidth() == 128)
1747 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1748 unsigned EltAlign = 0;
1749 getMaxByValAlign(ATy->getElementType(), EltAlign);
1750 if (EltAlign > MaxAlign)
1751 MaxAlign = EltAlign;
1752 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
1753 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
1754 unsigned EltAlign = 0;
1755 getMaxByValAlign(STy->getElementType(i), EltAlign);
1756 if (EltAlign > MaxAlign)
1757 MaxAlign = EltAlign;
1764 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1765 /// function arguments in the caller parameter area. For X86, aggregates
1766 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
1767 /// are at 4-byte boundaries.
1768 unsigned X86TargetLowering::getByValTypeAlignment(Type *Ty) const {
1769 if (Subtarget->is64Bit()) {
1770 // Max of 8 and alignment of type.
1771 unsigned TyAlign = TD->getABITypeAlignment(Ty);
1778 if (Subtarget->hasSSE1())
1779 getMaxByValAlign(Ty, Align);
1783 /// getOptimalMemOpType - Returns the target specific optimal type for load
1784 /// and store operations as a result of memset, memcpy, and memmove
1785 /// lowering. If DstAlign is zero that means it's safe to destination
1786 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
1787 /// means there isn't a need to check it against alignment requirement,
1788 /// probably because the source does not need to be loaded. If 'IsMemset' is
1789 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
1790 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
1791 /// source is constant so it does not need to be loaded.
1792 /// It returns EVT::Other if the type should be determined using generic
1793 /// target-independent logic.
1795 X86TargetLowering::getOptimalMemOpType(uint64_t Size,
1796 unsigned DstAlign, unsigned SrcAlign,
1797 bool IsMemset, bool ZeroMemset,
1799 MachineFunction &MF) const {
1800 const Function *F = MF.getFunction();
1801 if ((!IsMemset || ZeroMemset) &&
1802 !F->getAttributes().hasAttribute(AttributeSet::FunctionIndex,
1803 Attribute::NoImplicitFloat)) {
1805 (Subtarget->isUnalignedMemAccessFast() ||
1806 ((DstAlign == 0 || DstAlign >= 16) &&
1807 (SrcAlign == 0 || SrcAlign >= 16)))) {
1809 if (Subtarget->hasInt256())
1811 if (Subtarget->hasFp256())
1814 if (Subtarget->hasSSE2())
1816 if (Subtarget->hasSSE1())
1818 } else if (!MemcpyStrSrc && Size >= 8 &&
1819 !Subtarget->is64Bit() &&
1820 Subtarget->hasSSE2()) {
1821 // Do not use f64 to lower memcpy if source is string constant. It's
1822 // better to use i32 to avoid the loads.
1826 if (Subtarget->is64Bit() && Size >= 8)
1831 bool X86TargetLowering::isSafeMemOpType(MVT VT) const {
1833 return X86ScalarSSEf32;
1834 else if (VT == MVT::f64)
1835 return X86ScalarSSEf64;
1840 X86TargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
1845 *Fast = Subtarget->isUnalignedMemAccessFast();
1849 /// getJumpTableEncoding - Return the entry encoding for a jump table in the
1850 /// current function. The returned value is a member of the
1851 /// MachineJumpTableInfo::JTEntryKind enum.
1852 unsigned X86TargetLowering::getJumpTableEncoding() const {
1853 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
1855 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1856 Subtarget->isPICStyleGOT())
1857 return MachineJumpTableInfo::EK_Custom32;
1859 // Otherwise, use the normal jump table encoding heuristics.
1860 return TargetLowering::getJumpTableEncoding();
1864 X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
1865 const MachineBasicBlock *MBB,
1866 unsigned uid,MCContext &Ctx) const{
1867 assert(MBB->getParent()->getTarget().getRelocationModel() == Reloc::PIC_ &&
1868 Subtarget->isPICStyleGOT());
1869 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
1871 return MCSymbolRefExpr::Create(MBB->getSymbol(),
1872 MCSymbolRefExpr::VK_GOTOFF, Ctx);
1875 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
1877 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
1878 SelectionDAG &DAG) const {
1879 if (!Subtarget->is64Bit())
1880 // This doesn't have SDLoc associated with it, but is not really the
1881 // same as a Register.
1882 return DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), getPointerTy());
1886 /// getPICJumpTableRelocBaseExpr - This returns the relocation base for the
1887 /// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an
1889 const MCExpr *X86TargetLowering::
1890 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
1891 MCContext &Ctx) const {
1892 // X86-64 uses RIP relative addressing based on the jump table label.
1893 if (Subtarget->isPICStyleRIPRel())
1894 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
1896 // Otherwise, the reference is relative to the PIC base.
1897 return MCSymbolRefExpr::Create(MF->getPICBaseSymbol(), Ctx);
1900 // FIXME: Why this routine is here? Move to RegInfo!
1901 std::pair<const TargetRegisterClass*, uint8_t>
1902 X86TargetLowering::findRepresentativeClass(MVT VT) const{
1903 const TargetRegisterClass *RRC = nullptr;
1905 switch (VT.SimpleTy) {
1907 return TargetLowering::findRepresentativeClass(VT);
1908 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
1909 RRC = Subtarget->is64Bit() ? &X86::GR64RegClass : &X86::GR32RegClass;
1912 RRC = &X86::VR64RegClass;
1914 case MVT::f32: case MVT::f64:
1915 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
1916 case MVT::v4f32: case MVT::v2f64:
1917 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32:
1919 RRC = &X86::VR128RegClass;
1922 return std::make_pair(RRC, Cost);
1925 bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace,
1926 unsigned &Offset) const {
1927 if (!Subtarget->isTargetLinux())
1930 if (Subtarget->is64Bit()) {
1931 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs:
1933 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
1945 bool X86TargetLowering::isNoopAddrSpaceCast(unsigned SrcAS,
1946 unsigned DestAS) const {
1947 assert(SrcAS != DestAS && "Expected different address spaces!");
1949 return SrcAS < 256 && DestAS < 256;
1952 //===----------------------------------------------------------------------===//
1953 // Return Value Calling Convention Implementation
1954 //===----------------------------------------------------------------------===//
1956 #include "X86GenCallingConv.inc"
1959 X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv,
1960 MachineFunction &MF, bool isVarArg,
1961 const SmallVectorImpl<ISD::OutputArg> &Outs,
1962 LLVMContext &Context) const {
1963 SmallVector<CCValAssign, 16> RVLocs;
1964 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
1965 return CCInfo.CheckReturn(Outs, RetCC_X86);
1968 const MCPhysReg *X86TargetLowering::getScratchRegisters(CallingConv::ID) const {
1969 static const MCPhysReg ScratchRegs[] = { X86::R11, 0 };
1974 X86TargetLowering::LowerReturn(SDValue Chain,
1975 CallingConv::ID CallConv, bool isVarArg,
1976 const SmallVectorImpl<ISD::OutputArg> &Outs,
1977 const SmallVectorImpl<SDValue> &OutVals,
1978 SDLoc dl, SelectionDAG &DAG) const {
1979 MachineFunction &MF = DAG.getMachineFunction();
1980 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1982 SmallVector<CCValAssign, 16> RVLocs;
1983 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, *DAG.getContext());
1984 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
1987 SmallVector<SDValue, 6> RetOps;
1988 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
1989 // Operand #1 = Bytes To Pop
1990 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(),
1993 // Copy the result values into the output registers.
1994 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1995 CCValAssign &VA = RVLocs[i];
1996 assert(VA.isRegLoc() && "Can only return in registers!");
1997 SDValue ValToCopy = OutVals[i];
1998 EVT ValVT = ValToCopy.getValueType();
2000 // Promote values to the appropriate types
2001 if (VA.getLocInfo() == CCValAssign::SExt)
2002 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy);
2003 else if (VA.getLocInfo() == CCValAssign::ZExt)
2004 ValToCopy = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ValToCopy);
2005 else if (VA.getLocInfo() == CCValAssign::AExt)
2006 ValToCopy = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ValToCopy);
2007 else if (VA.getLocInfo() == CCValAssign::BCvt)
2008 ValToCopy = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), ValToCopy);
2010 assert(VA.getLocInfo() != CCValAssign::FPExt &&
2011 "Unexpected FP-extend for return value.");
2013 // If this is x86-64, and we disabled SSE, we can't return FP values,
2014 // or SSE or MMX vectors.
2015 if ((ValVT == MVT::f32 || ValVT == MVT::f64 ||
2016 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) &&
2017 (Subtarget->is64Bit() && !Subtarget->hasSSE1())) {
2018 report_fatal_error("SSE register return with SSE disabled");
2020 // Likewise we can't return F64 values with SSE1 only. gcc does so, but
2021 // llvm-gcc has never done it right and no one has noticed, so this
2022 // should be OK for now.
2023 if (ValVT == MVT::f64 &&
2024 (Subtarget->is64Bit() && !Subtarget->hasSSE2()))
2025 report_fatal_error("SSE2 register return with SSE2 disabled");
2027 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
2028 // the RET instruction and handled by the FP Stackifier.
2029 if (VA.getLocReg() == X86::FP0 ||
2030 VA.getLocReg() == X86::FP1) {
2031 // If this is a copy from an xmm register to ST(0), use an FPExtend to
2032 // change the value to the FP stack register class.
2033 if (isScalarFPTypeInSSEReg(VA.getValVT()))
2034 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
2035 RetOps.push_back(ValToCopy);
2036 // Don't emit a copytoreg.
2040 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
2041 // which is returned in RAX / RDX.
2042 if (Subtarget->is64Bit()) {
2043 if (ValVT == MVT::x86mmx) {
2044 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
2045 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ValToCopy);
2046 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
2048 // If we don't have SSE2 available, convert to v4f32 so the generated
2049 // register is legal.
2050 if (!Subtarget->hasSSE2())
2051 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32,ValToCopy);
2056 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
2057 Flag = Chain.getValue(1);
2058 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2061 // The x86-64 ABIs require that for returning structs by value we copy
2062 // the sret argument into %rax/%eax (depending on ABI) for the return.
2063 // Win32 requires us to put the sret argument to %eax as well.
2064 // We saved the argument into a virtual register in the entry block,
2065 // so now we copy the value out and into %rax/%eax.
2066 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr() &&
2067 (Subtarget->is64Bit() || Subtarget->isTargetKnownWindowsMSVC())) {
2068 MachineFunction &MF = DAG.getMachineFunction();
2069 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2070 unsigned Reg = FuncInfo->getSRetReturnReg();
2072 "SRetReturnReg should have been set in LowerFormalArguments().");
2073 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
2076 = (Subtarget->is64Bit() && !Subtarget->isTarget64BitILP32()) ?
2077 X86::RAX : X86::EAX;
2078 Chain = DAG.getCopyToReg(Chain, dl, RetValReg, Val, Flag);
2079 Flag = Chain.getValue(1);
2081 // RAX/EAX now acts like a return value.
2082 RetOps.push_back(DAG.getRegister(RetValReg, getPointerTy()));
2085 RetOps[0] = Chain; // Update chain.
2087 // Add the flag if we have it.
2089 RetOps.push_back(Flag);
2091 return DAG.getNode(X86ISD::RET_FLAG, dl, MVT::Other, RetOps);
2094 bool X86TargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
2095 if (N->getNumValues() != 1)
2097 if (!N->hasNUsesOfValue(1, 0))
2100 SDValue TCChain = Chain;
2101 SDNode *Copy = *N->use_begin();
2102 if (Copy->getOpcode() == ISD::CopyToReg) {
2103 // If the copy has a glue operand, we conservatively assume it isn't safe to
2104 // perform a tail call.
2105 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
2107 TCChain = Copy->getOperand(0);
2108 } else if (Copy->getOpcode() != ISD::FP_EXTEND)
2111 bool HasRet = false;
2112 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
2114 if (UI->getOpcode() != X86ISD::RET_FLAG)
2116 // If we are returning more than one value, we can definitely
2117 // not make a tail call see PR19530
2118 if (UI->getNumOperands() > 4)
2120 if (UI->getNumOperands() == 4 &&
2121 UI->getOperand(UI->getNumOperands()-1).getValueType() != MVT::Glue)
2134 X86TargetLowering::getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT,
2135 ISD::NodeType ExtendKind) const {
2137 // TODO: Is this also valid on 32-bit?
2138 if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND)
2139 ReturnMVT = MVT::i8;
2141 ReturnMVT = MVT::i32;
2143 EVT MinVT = getRegisterType(Context, ReturnMVT);
2144 return VT.bitsLT(MinVT) ? MinVT : VT;
2147 /// LowerCallResult - Lower the result values of a call into the
2148 /// appropriate copies out of appropriate physical registers.
2151 X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
2152 CallingConv::ID CallConv, bool isVarArg,
2153 const SmallVectorImpl<ISD::InputArg> &Ins,
2154 SDLoc dl, SelectionDAG &DAG,
2155 SmallVectorImpl<SDValue> &InVals) const {
2157 // Assign locations to each value returned by this call.
2158 SmallVector<CCValAssign, 16> RVLocs;
2159 bool Is64Bit = Subtarget->is64Bit();
2160 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
2162 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
2164 // Copy all of the result registers out of their specified physreg.
2165 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
2166 CCValAssign &VA = RVLocs[i];
2167 EVT CopyVT = VA.getValVT();
2169 // If this is x86-64, and we disabled SSE, we can't return FP values
2170 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
2171 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) {
2172 report_fatal_error("SSE register return with SSE disabled");
2175 // If we prefer to use the value in xmm registers, copy it out as f80 and
2176 // use a truncate to move it from fp stack reg to xmm reg.
2177 if ((VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1) &&
2178 isScalarFPTypeInSSEReg(VA.getValVT()))
2181 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
2182 CopyVT, InFlag).getValue(1);
2183 SDValue Val = Chain.getValue(0);
2185 if (CopyVT != VA.getValVT())
2186 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
2187 // This truncation won't change the value.
2188 DAG.getIntPtrConstant(1));
2190 InFlag = Chain.getValue(2);
2191 InVals.push_back(Val);
2197 //===----------------------------------------------------------------------===//
2198 // C & StdCall & Fast Calling Convention implementation
2199 //===----------------------------------------------------------------------===//
2200 // StdCall calling convention seems to be standard for many Windows' API
2201 // routines and around. It differs from C calling convention just a little:
2202 // callee should clean up the stack, not caller. Symbols should be also
2203 // decorated in some fancy way :) It doesn't support any vector arguments.
2204 // For info on fast calling convention see Fast Calling Convention (tail call)
2205 // implementation LowerX86_32FastCCCallTo.
2207 /// CallIsStructReturn - Determines whether a call uses struct return
2209 enum StructReturnType {
2214 static StructReturnType
2215 callIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
2217 return NotStructReturn;
2219 const ISD::ArgFlagsTy &Flags = Outs[0].Flags;
2220 if (!Flags.isSRet())
2221 return NotStructReturn;
2222 if (Flags.isInReg())
2223 return RegStructReturn;
2224 return StackStructReturn;
2227 /// ArgsAreStructReturn - Determines whether a function uses struct
2228 /// return semantics.
2229 static StructReturnType
2230 argsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
2232 return NotStructReturn;
2234 const ISD::ArgFlagsTy &Flags = Ins[0].Flags;
2235 if (!Flags.isSRet())
2236 return NotStructReturn;
2237 if (Flags.isInReg())
2238 return RegStructReturn;
2239 return StackStructReturn;
2242 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
2243 /// by "Src" to address "Dst" with size and alignment information specified by
2244 /// the specific parameter attribute. The copy will be passed as a byval
2245 /// function parameter.
2247 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
2248 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
2250 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
2252 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
2253 /*isVolatile*/false, /*AlwaysInline=*/true,
2254 MachinePointerInfo(), MachinePointerInfo());
2257 /// IsTailCallConvention - Return true if the calling convention is one that
2258 /// supports tail call optimization.
2259 static bool IsTailCallConvention(CallingConv::ID CC) {
2260 return (CC == CallingConv::Fast || CC == CallingConv::GHC ||
2261 CC == CallingConv::HiPE);
2264 /// \brief Return true if the calling convention is a C calling convention.
2265 static bool IsCCallConvention(CallingConv::ID CC) {
2266 return (CC == CallingConv::C || CC == CallingConv::X86_64_Win64 ||
2267 CC == CallingConv::X86_64_SysV);
2270 bool X86TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
2271 if (!CI->isTailCall() || getTargetMachine().Options.DisableTailCalls)
2275 CallingConv::ID CalleeCC = CS.getCallingConv();
2276 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
2282 /// FuncIsMadeTailCallSafe - Return true if the function is being made into
2283 /// a tailcall target by changing its ABI.
2284 static bool FuncIsMadeTailCallSafe(CallingConv::ID CC,
2285 bool GuaranteedTailCallOpt) {
2286 return GuaranteedTailCallOpt && IsTailCallConvention(CC);
2290 X86TargetLowering::LowerMemArgument(SDValue Chain,
2291 CallingConv::ID CallConv,
2292 const SmallVectorImpl<ISD::InputArg> &Ins,
2293 SDLoc dl, SelectionDAG &DAG,
2294 const CCValAssign &VA,
2295 MachineFrameInfo *MFI,
2297 // Create the nodes corresponding to a load from this parameter slot.
2298 ISD::ArgFlagsTy Flags = Ins[i].Flags;
2299 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(
2300 CallConv, DAG.getTarget().Options.GuaranteedTailCallOpt);
2301 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
2304 // If value is passed by pointer we have address passed instead of the value
2306 if (VA.getLocInfo() == CCValAssign::Indirect)
2307 ValVT = VA.getLocVT();
2309 ValVT = VA.getValVT();
2311 // FIXME: For now, all byval parameter objects are marked mutable. This can be
2312 // changed with more analysis.
2313 // In case of tail call optimization mark all arguments mutable. Since they
2314 // could be overwritten by lowering of arguments in case of a tail call.
2315 if (Flags.isByVal()) {
2316 unsigned Bytes = Flags.getByValSize();
2317 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects.
2318 int FI = MFI->CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable);
2319 return DAG.getFrameIndex(FI, getPointerTy());
2321 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
2322 VA.getLocMemOffset(), isImmutable);
2323 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2324 return DAG.getLoad(ValVT, dl, Chain, FIN,
2325 MachinePointerInfo::getFixedStack(FI),
2326 false, false, false, 0);
2330 // FIXME: Get this from tablegen.
2331 static ArrayRef<MCPhysReg> get64BitArgumentGPRs(CallingConv::ID CallConv,
2332 const X86Subtarget *Subtarget) {
2333 assert(Subtarget->is64Bit());
2335 if (Subtarget->isCallingConvWin64(CallConv)) {
2336 static const MCPhysReg GPR64ArgRegsWin64[] = {
2337 X86::RCX, X86::RDX, X86::R8, X86::R9
2339 return makeArrayRef(std::begin(GPR64ArgRegsWin64), std::end(GPR64ArgRegsWin64));
2342 static const MCPhysReg GPR64ArgRegs64Bit[] = {
2343 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
2345 return makeArrayRef(std::begin(GPR64ArgRegs64Bit), std::end(GPR64ArgRegs64Bit));
2348 // FIXME: Get this from tablegen.
2349 static ArrayRef<MCPhysReg> get64BitArgumentXMMs(MachineFunction &MF,
2350 CallingConv::ID CallConv,
2351 const X86Subtarget *Subtarget) {
2352 assert(Subtarget->is64Bit());
2353 if (Subtarget->isCallingConvWin64(CallConv)) {
2354 // The XMM registers which might contain var arg parameters are shadowed
2355 // in their paired GPR. So we only need to save the GPR to their home
2357 // TODO: __vectorcall will change this.
2361 const Function *Fn = MF.getFunction();
2362 bool NoImplicitFloatOps = Fn->getAttributes().
2363 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoImplicitFloat);
2364 assert(!(MF.getTarget().Options.UseSoftFloat && NoImplicitFloatOps) &&
2365 "SSE register cannot be used when SSE is disabled!");
2366 if (MF.getTarget().Options.UseSoftFloat || NoImplicitFloatOps ||
2367 !Subtarget->hasSSE1())
2368 // Kernel mode asks for SSE to be disabled, so there are no XMM argument
2372 static const MCPhysReg XMMArgRegs64Bit[] = {
2373 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2374 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2376 return makeArrayRef(std::begin(XMMArgRegs64Bit), std::end(XMMArgRegs64Bit));
2380 X86TargetLowering::LowerFormalArguments(SDValue Chain,
2381 CallingConv::ID CallConv,
2383 const SmallVectorImpl<ISD::InputArg> &Ins,
2386 SmallVectorImpl<SDValue> &InVals)
2388 MachineFunction &MF = DAG.getMachineFunction();
2389 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2391 const Function* Fn = MF.getFunction();
2392 if (Fn->hasExternalLinkage() &&
2393 Subtarget->isTargetCygMing() &&
2394 Fn->getName() == "main")
2395 FuncInfo->setForceFramePointer(true);
2397 MachineFrameInfo *MFI = MF.getFrameInfo();
2398 bool Is64Bit = Subtarget->is64Bit();
2399 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2401 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2402 "Var args not supported with calling convention fastcc, ghc or hipe");
2404 // Assign locations to all of the incoming arguments.
2405 SmallVector<CCValAssign, 16> ArgLocs;
2406 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
2408 // Allocate shadow area for Win64
2410 CCInfo.AllocateStack(32, 8);
2412 CCInfo.AnalyzeFormalArguments(Ins, CC_X86);
2414 unsigned LastVal = ~0U;
2416 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2417 CCValAssign &VA = ArgLocs[i];
2418 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
2420 assert(VA.getValNo() != LastVal &&
2421 "Don't support value assigned to multiple locs yet");
2423 LastVal = VA.getValNo();
2425 if (VA.isRegLoc()) {
2426 EVT RegVT = VA.getLocVT();
2427 const TargetRegisterClass *RC;
2428 if (RegVT == MVT::i32)
2429 RC = &X86::GR32RegClass;
2430 else if (Is64Bit && RegVT == MVT::i64)
2431 RC = &X86::GR64RegClass;
2432 else if (RegVT == MVT::f32)
2433 RC = &X86::FR32RegClass;
2434 else if (RegVT == MVT::f64)
2435 RC = &X86::FR64RegClass;
2436 else if (RegVT.is512BitVector())
2437 RC = &X86::VR512RegClass;
2438 else if (RegVT.is256BitVector())
2439 RC = &X86::VR256RegClass;
2440 else if (RegVT.is128BitVector())
2441 RC = &X86::VR128RegClass;
2442 else if (RegVT == MVT::x86mmx)
2443 RC = &X86::VR64RegClass;
2444 else if (RegVT == MVT::i1)
2445 RC = &X86::VK1RegClass;
2446 else if (RegVT == MVT::v8i1)
2447 RC = &X86::VK8RegClass;
2448 else if (RegVT == MVT::v16i1)
2449 RC = &X86::VK16RegClass;
2450 else if (RegVT == MVT::v32i1)
2451 RC = &X86::VK32RegClass;
2452 else if (RegVT == MVT::v64i1)
2453 RC = &X86::VK64RegClass;
2455 llvm_unreachable("Unknown argument type!");
2457 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2458 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
2460 // If this is an 8 or 16-bit value, it is really passed promoted to 32
2461 // bits. Insert an assert[sz]ext to capture this, then truncate to the
2463 if (VA.getLocInfo() == CCValAssign::SExt)
2464 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
2465 DAG.getValueType(VA.getValVT()));
2466 else if (VA.getLocInfo() == CCValAssign::ZExt)
2467 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
2468 DAG.getValueType(VA.getValVT()));
2469 else if (VA.getLocInfo() == CCValAssign::BCvt)
2470 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
2472 if (VA.isExtInLoc()) {
2473 // Handle MMX values passed in XMM regs.
2474 if (RegVT.isVector())
2475 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(), ArgValue);
2477 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
2480 assert(VA.isMemLoc());
2481 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
2484 // If value is passed via pointer - do a load.
2485 if (VA.getLocInfo() == CCValAssign::Indirect)
2486 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue,
2487 MachinePointerInfo(), false, false, false, 0);
2489 InVals.push_back(ArgValue);
2492 if (Subtarget->is64Bit() || Subtarget->isTargetKnownWindowsMSVC()) {
2493 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2494 // The x86-64 ABIs require that for returning structs by value we copy
2495 // the sret argument into %rax/%eax (depending on ABI) for the return.
2496 // Win32 requires us to put the sret argument to %eax as well.
2497 // Save the argument into a virtual register so that we can access it
2498 // from the return points.
2499 if (Ins[i].Flags.isSRet()) {
2500 unsigned Reg = FuncInfo->getSRetReturnReg();
2502 MVT PtrTy = getPointerTy();
2503 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(PtrTy));
2504 FuncInfo->setSRetReturnReg(Reg);
2506 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[i]);
2507 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
2513 unsigned StackSize = CCInfo.getNextStackOffset();
2514 // Align stack specially for tail calls.
2515 if (FuncIsMadeTailCallSafe(CallConv,
2516 MF.getTarget().Options.GuaranteedTailCallOpt))
2517 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
2519 // If the function takes variable number of arguments, make a frame index for
2520 // the start of the first vararg value... for expansion of llvm.va_start. We
2521 // can skip this if there are no va_start calls.
2522 if (MFI->hasVAStart() &&
2523 (Is64Bit || (CallConv != CallingConv::X86_FastCall &&
2524 CallConv != CallingConv::X86_ThisCall))) {
2525 FuncInfo->setVarArgsFrameIndex(
2526 MFI->CreateFixedObject(1, StackSize, true));
2529 // 64-bit calling conventions support varargs and register parameters, so we
2530 // have to do extra work to spill them in the prologue or forward them to
2532 if (Is64Bit && isVarArg &&
2533 (MFI->hasVAStart() || MFI->hasMustTailInVarArgFunc())) {
2534 // Find the first unallocated argument registers.
2535 ArrayRef<MCPhysReg> ArgGPRs = get64BitArgumentGPRs(CallConv, Subtarget);
2536 ArrayRef<MCPhysReg> ArgXMMs = get64BitArgumentXMMs(MF, CallConv, Subtarget);
2537 unsigned NumIntRegs =
2538 CCInfo.getFirstUnallocated(ArgGPRs.data(), ArgGPRs.size());
2539 unsigned NumXMMRegs =
2540 CCInfo.getFirstUnallocated(ArgXMMs.data(), ArgXMMs.size());
2541 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) &&
2542 "SSE register cannot be used when SSE is disabled!");
2544 // Gather all the live in physical registers.
2545 SmallVector<SDValue, 6> LiveGPRs;
2546 SmallVector<SDValue, 8> LiveXMMRegs;
2548 for (MCPhysReg Reg : ArgGPRs.slice(NumIntRegs)) {
2549 unsigned GPR = MF.addLiveIn(Reg, &X86::GR64RegClass);
2551 DAG.getCopyFromReg(Chain, dl, GPR, MVT::i64));
2553 if (!ArgXMMs.empty()) {
2554 unsigned AL = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
2555 ALVal = DAG.getCopyFromReg(Chain, dl, AL, MVT::i8);
2556 for (MCPhysReg Reg : ArgXMMs.slice(NumXMMRegs)) {
2557 unsigned XMMReg = MF.addLiveIn(Reg, &X86::VR128RegClass);
2558 LiveXMMRegs.push_back(
2559 DAG.getCopyFromReg(Chain, dl, XMMReg, MVT::v4f32));
2563 // Store them to the va_list returned by va_start.
2564 if (MFI->hasVAStart()) {
2566 const TargetFrameLowering &TFI = *MF.getSubtarget().getFrameLowering();
2567 // Get to the caller-allocated home save location. Add 8 to account
2568 // for the return address.
2569 int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
2570 FuncInfo->setRegSaveFrameIndex(
2571 MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false));
2572 // Fixup to set vararg frame on shadow area (4 x i64).
2574 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex());
2576 // For X86-64, if there are vararg parameters that are passed via
2577 // registers, then we must store them to their spots on the stack so
2578 // they may be loaded by deferencing the result of va_next.
2579 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8);
2580 FuncInfo->setVarArgsFPOffset(ArgGPRs.size() * 8 + NumXMMRegs * 16);
2581 FuncInfo->setRegSaveFrameIndex(MFI->CreateStackObject(
2582 ArgGPRs.size() * 8 + ArgXMMs.size() * 16, 16, false));
2585 // Store the integer parameter registers.
2586 SmallVector<SDValue, 8> MemOps;
2587 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
2589 unsigned Offset = FuncInfo->getVarArgsGPOffset();
2590 for (SDValue Val : LiveGPRs) {
2591 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN,
2592 DAG.getIntPtrConstant(Offset));
2594 DAG.getStore(Val.getValue(1), dl, Val, FIN,
2595 MachinePointerInfo::getFixedStack(
2596 FuncInfo->getRegSaveFrameIndex(), Offset),
2598 MemOps.push_back(Store);
2602 if (!ArgXMMs.empty() && NumXMMRegs != ArgXMMs.size()) {
2603 // Now store the XMM (fp + vector) parameter registers.
2604 SmallVector<SDValue, 12> SaveXMMOps;
2605 SaveXMMOps.push_back(Chain);
2606 SaveXMMOps.push_back(ALVal);
2607 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2608 FuncInfo->getRegSaveFrameIndex()));
2609 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2610 FuncInfo->getVarArgsFPOffset()));
2611 SaveXMMOps.insert(SaveXMMOps.end(), LiveXMMRegs.begin(),
2613 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
2614 MVT::Other, SaveXMMOps));
2617 if (!MemOps.empty())
2618 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
2620 // Add all GPRs, al, and XMMs to the list of forwards. We will add then
2621 // to the liveout set on a musttail call.
2622 assert(MFI->hasMustTailInVarArgFunc());
2623 auto &Forwards = FuncInfo->getForwardedMustTailRegParms();
2624 typedef X86MachineFunctionInfo::Forward Forward;
2626 for (unsigned I = 0, E = LiveGPRs.size(); I != E; ++I) {
2628 MF.getRegInfo().createVirtualRegister(&X86::GR64RegClass);
2629 Chain = DAG.getCopyToReg(Chain, dl, VReg, LiveGPRs[I]);
2630 Forwards.push_back(Forward(VReg, ArgGPRs[NumIntRegs + I], MVT::i64));
2633 if (!ArgXMMs.empty()) {
2635 MF.getRegInfo().createVirtualRegister(&X86::GR8RegClass);
2636 Chain = DAG.getCopyToReg(Chain, dl, ALVReg, ALVal);
2637 Forwards.push_back(Forward(ALVReg, X86::AL, MVT::i8));
2639 for (unsigned I = 0, E = LiveXMMRegs.size(); I != E; ++I) {
2641 MF.getRegInfo().createVirtualRegister(&X86::VR128RegClass);
2642 Chain = DAG.getCopyToReg(Chain, dl, VReg, LiveXMMRegs[I]);
2644 Forward(VReg, ArgXMMs[NumXMMRegs + I], MVT::v4f32));
2650 // Some CCs need callee pop.
2651 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2652 MF.getTarget().Options.GuaranteedTailCallOpt)) {
2653 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything.
2655 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing.
2656 // If this is an sret function, the return should pop the hidden pointer.
2657 if (!Is64Bit && !IsTailCallConvention(CallConv) &&
2658 !Subtarget->getTargetTriple().isOSMSVCRT() &&
2659 argsAreStructReturn(Ins) == StackStructReturn)
2660 FuncInfo->setBytesToPopOnReturn(4);
2664 // RegSaveFrameIndex is X86-64 only.
2665 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
2666 if (CallConv == CallingConv::X86_FastCall ||
2667 CallConv == CallingConv::X86_ThisCall)
2668 // fastcc functions can't have varargs.
2669 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA);
2672 FuncInfo->setArgumentStackSize(StackSize);
2678 X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
2679 SDValue StackPtr, SDValue Arg,
2680 SDLoc dl, SelectionDAG &DAG,
2681 const CCValAssign &VA,
2682 ISD::ArgFlagsTy Flags) const {
2683 unsigned LocMemOffset = VA.getLocMemOffset();
2684 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
2685 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
2686 if (Flags.isByVal())
2687 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
2689 return DAG.getStore(Chain, dl, Arg, PtrOff,
2690 MachinePointerInfo::getStack(LocMemOffset),
2694 /// EmitTailCallLoadRetAddr - Emit a load of return address if tail call
2695 /// optimization is performed and it is required.
2697 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
2698 SDValue &OutRetAddr, SDValue Chain,
2699 bool IsTailCall, bool Is64Bit,
2700 int FPDiff, SDLoc dl) const {
2701 // Adjust the Return address stack slot.
2702 EVT VT = getPointerTy();
2703 OutRetAddr = getReturnAddressFrameIndex(DAG);
2705 // Load the "old" Return address.
2706 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(),
2707 false, false, false, 0);
2708 return SDValue(OutRetAddr.getNode(), 1);
2711 /// EmitTailCallStoreRetAddr - Emit a store of the return address if tail call
2712 /// optimization is performed and it is required (FPDiff!=0).
2713 static SDValue EmitTailCallStoreRetAddr(SelectionDAG &DAG, MachineFunction &MF,
2714 SDValue Chain, SDValue RetAddrFrIdx,
2715 EVT PtrVT, unsigned SlotSize,
2716 int FPDiff, SDLoc dl) {
2717 // Store the return address to the appropriate stack slot.
2718 if (!FPDiff) return Chain;
2719 // Calculate the new stack slot for the return address.
2720 int NewReturnAddrFI =
2721 MF.getFrameInfo()->CreateFixedObject(SlotSize, (int64_t)FPDiff - SlotSize,
2723 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, PtrVT);
2724 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
2725 MachinePointerInfo::getFixedStack(NewReturnAddrFI),
2731 X86TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
2732 SmallVectorImpl<SDValue> &InVals) const {
2733 SelectionDAG &DAG = CLI.DAG;
2735 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
2736 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
2737 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
2738 SDValue Chain = CLI.Chain;
2739 SDValue Callee = CLI.Callee;
2740 CallingConv::ID CallConv = CLI.CallConv;
2741 bool &isTailCall = CLI.IsTailCall;
2742 bool isVarArg = CLI.IsVarArg;
2744 MachineFunction &MF = DAG.getMachineFunction();
2745 bool Is64Bit = Subtarget->is64Bit();
2746 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2747 StructReturnType SR = callIsStructReturn(Outs);
2748 bool IsSibcall = false;
2749 X86MachineFunctionInfo *X86Info = MF.getInfo<X86MachineFunctionInfo>();
2751 if (MF.getTarget().Options.DisableTailCalls)
2754 bool IsMustTail = CLI.CS && CLI.CS->isMustTailCall();
2756 // Force this to be a tail call. The verifier rules are enough to ensure
2757 // that we can lower this successfully without moving the return address
2760 } else if (isTailCall) {
2761 // Check if it's really possible to do a tail call.
2762 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
2763 isVarArg, SR != NotStructReturn,
2764 MF.getFunction()->hasStructRetAttr(), CLI.RetTy,
2765 Outs, OutVals, Ins, DAG);
2767 // Sibcalls are automatically detected tailcalls which do not require
2769 if (!MF.getTarget().Options.GuaranteedTailCallOpt && isTailCall)
2776 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2777 "Var args not supported with calling convention fastcc, ghc or hipe");
2779 // Analyze operands of the call, assigning locations to each operand.
2780 SmallVector<CCValAssign, 16> ArgLocs;
2781 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
2783 // Allocate shadow area for Win64
2785 CCInfo.AllocateStack(32, 8);
2787 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2789 // Get a count of how many bytes are to be pushed on the stack.
2790 unsigned NumBytes = CCInfo.getNextStackOffset();
2792 // This is a sibcall. The memory operands are available in caller's
2793 // own caller's stack.
2795 else if (MF.getTarget().Options.GuaranteedTailCallOpt &&
2796 IsTailCallConvention(CallConv))
2797 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
2800 if (isTailCall && !IsSibcall && !IsMustTail) {
2801 // Lower arguments at fp - stackoffset + fpdiff.
2802 unsigned NumBytesCallerPushed = X86Info->getBytesToPopOnReturn();
2804 FPDiff = NumBytesCallerPushed - NumBytes;
2806 // Set the delta of movement of the returnaddr stackslot.
2807 // But only set if delta is greater than previous delta.
2808 if (FPDiff < X86Info->getTCReturnAddrDelta())
2809 X86Info->setTCReturnAddrDelta(FPDiff);
2812 unsigned NumBytesToPush = NumBytes;
2813 unsigned NumBytesToPop = NumBytes;
2815 // If we have an inalloca argument, all stack space has already been allocated
2816 // for us and be right at the top of the stack. We don't support multiple
2817 // arguments passed in memory when using inalloca.
2818 if (!Outs.empty() && Outs.back().Flags.isInAlloca()) {
2820 if (!ArgLocs.back().isMemLoc())
2821 report_fatal_error("cannot use inalloca attribute on a register "
2823 if (ArgLocs.back().getLocMemOffset() != 0)
2824 report_fatal_error("any parameter with the inalloca attribute must be "
2825 "the only memory argument");
2829 Chain = DAG.getCALLSEQ_START(
2830 Chain, DAG.getIntPtrConstant(NumBytesToPush, true), dl);
2832 SDValue RetAddrFrIdx;
2833 // Load return address for tail calls.
2834 if (isTailCall && FPDiff)
2835 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall,
2836 Is64Bit, FPDiff, dl);
2838 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
2839 SmallVector<SDValue, 8> MemOpChains;
2842 // Walk the register/memloc assignments, inserting copies/loads. In the case
2843 // of tail call optimization arguments are handle later.
2844 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
2845 DAG.getSubtarget().getRegisterInfo());
2846 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2847 // Skip inalloca arguments, they have already been written.
2848 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2849 if (Flags.isInAlloca())
2852 CCValAssign &VA = ArgLocs[i];
2853 EVT RegVT = VA.getLocVT();
2854 SDValue Arg = OutVals[i];
2855 bool isByVal = Flags.isByVal();
2857 // Promote the value if needed.
2858 switch (VA.getLocInfo()) {
2859 default: llvm_unreachable("Unknown loc info!");
2860 case CCValAssign::Full: break;
2861 case CCValAssign::SExt:
2862 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
2864 case CCValAssign::ZExt:
2865 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
2867 case CCValAssign::AExt:
2868 if (RegVT.is128BitVector()) {
2869 // Special case: passing MMX values in XMM registers.
2870 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg);
2871 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
2872 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
2874 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
2876 case CCValAssign::BCvt:
2877 Arg = DAG.getNode(ISD::BITCAST, dl, RegVT, Arg);
2879 case CCValAssign::Indirect: {
2880 // Store the argument.
2881 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
2882 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
2883 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot,
2884 MachinePointerInfo::getFixedStack(FI),
2891 if (VA.isRegLoc()) {
2892 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2893 if (isVarArg && IsWin64) {
2894 // Win64 ABI requires argument XMM reg to be copied to the corresponding
2895 // shadow reg if callee is a varargs function.
2896 unsigned ShadowReg = 0;
2897 switch (VA.getLocReg()) {
2898 case X86::XMM0: ShadowReg = X86::RCX; break;
2899 case X86::XMM1: ShadowReg = X86::RDX; break;
2900 case X86::XMM2: ShadowReg = X86::R8; break;
2901 case X86::XMM3: ShadowReg = X86::R9; break;
2904 RegsToPass.push_back(std::make_pair(ShadowReg, Arg));
2906 } else if (!IsSibcall && (!isTailCall || isByVal)) {
2907 assert(VA.isMemLoc());
2908 if (!StackPtr.getNode())
2909 StackPtr = DAG.getCopyFromReg(Chain, dl, RegInfo->getStackRegister(),
2911 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
2912 dl, DAG, VA, Flags));
2916 if (!MemOpChains.empty())
2917 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
2919 if (Subtarget->isPICStyleGOT()) {
2920 // ELF / PIC requires GOT in the EBX register before function calls via PLT
2923 RegsToPass.push_back(std::make_pair(unsigned(X86::EBX),
2924 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), getPointerTy())));
2926 // If we are tail calling and generating PIC/GOT style code load the
2927 // address of the callee into ECX. The value in ecx is used as target of
2928 // the tail jump. This is done to circumvent the ebx/callee-saved problem
2929 // for tail calls on PIC/GOT architectures. Normally we would just put the
2930 // address of GOT into ebx and then call target@PLT. But for tail calls
2931 // ebx would be restored (since ebx is callee saved) before jumping to the
2934 // Note: The actual moving to ECX is done further down.
2935 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
2936 if (G && !G->getGlobal()->hasHiddenVisibility() &&
2937 !G->getGlobal()->hasProtectedVisibility())
2938 Callee = LowerGlobalAddress(Callee, DAG);
2939 else if (isa<ExternalSymbolSDNode>(Callee))
2940 Callee = LowerExternalSymbol(Callee, DAG);
2944 if (Is64Bit && isVarArg && !IsWin64 && !IsMustTail) {
2945 // From AMD64 ABI document:
2946 // For calls that may call functions that use varargs or stdargs
2947 // (prototype-less calls or calls to functions containing ellipsis (...) in
2948 // the declaration) %al is used as hidden argument to specify the number
2949 // of SSE registers used. The contents of %al do not need to match exactly
2950 // the number of registers, but must be an ubound on the number of SSE
2951 // registers used and is in the range 0 - 8 inclusive.
2953 // Count the number of XMM registers allocated.
2954 static const MCPhysReg XMMArgRegs[] = {
2955 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2956 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2958 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
2959 assert((Subtarget->hasSSE1() || !NumXMMRegs)
2960 && "SSE registers cannot be used when SSE is disabled");
2962 RegsToPass.push_back(std::make_pair(unsigned(X86::AL),
2963 DAG.getConstant(NumXMMRegs, MVT::i8)));
2966 if (Is64Bit && isVarArg && IsMustTail) {
2967 const auto &Forwards = X86Info->getForwardedMustTailRegParms();
2968 for (const auto &F : Forwards) {
2969 SDValue Val = DAG.getCopyFromReg(Chain, dl, F.VReg, F.VT);
2970 RegsToPass.push_back(std::make_pair(unsigned(F.PReg), Val));
2974 // For tail calls lower the arguments to the 'real' stack slots. Sibcalls
2975 // don't need this because the eligibility check rejects calls that require
2976 // shuffling arguments passed in memory.
2977 if (!IsSibcall && isTailCall) {
2978 // Force all the incoming stack arguments to be loaded from the stack
2979 // before any new outgoing arguments are stored to the stack, because the
2980 // outgoing stack slots may alias the incoming argument stack slots, and
2981 // the alias isn't otherwise explicit. This is slightly more conservative
2982 // than necessary, because it means that each store effectively depends
2983 // on every argument instead of just those arguments it would clobber.
2984 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
2986 SmallVector<SDValue, 8> MemOpChains2;
2989 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2990 CCValAssign &VA = ArgLocs[i];
2993 assert(VA.isMemLoc());
2994 SDValue Arg = OutVals[i];
2995 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2996 // Skip inalloca arguments. They don't require any work.
2997 if (Flags.isInAlloca())
2999 // Create frame index.
3000 int32_t Offset = VA.getLocMemOffset()+FPDiff;
3001 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
3002 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
3003 FIN = DAG.getFrameIndex(FI, getPointerTy());
3005 if (Flags.isByVal()) {
3006 // Copy relative to framepointer.
3007 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset());
3008 if (!StackPtr.getNode())
3009 StackPtr = DAG.getCopyFromReg(Chain, dl,
3010 RegInfo->getStackRegister(),
3012 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source);
3014 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
3018 // Store relative to framepointer.
3019 MemOpChains2.push_back(
3020 DAG.getStore(ArgChain, dl, Arg, FIN,
3021 MachinePointerInfo::getFixedStack(FI),
3026 if (!MemOpChains2.empty())
3027 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains2);
3029 // Store the return address to the appropriate stack slot.
3030 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx,
3031 getPointerTy(), RegInfo->getSlotSize(),
3035 // Build a sequence of copy-to-reg nodes chained together with token chain
3036 // and flag operands which copy the outgoing args into registers.
3038 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
3039 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
3040 RegsToPass[i].second, InFlag);
3041 InFlag = Chain.getValue(1);
3044 if (DAG.getTarget().getCodeModel() == CodeModel::Large) {
3045 assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
3046 // In the 64-bit large code model, we have to make all calls
3047 // through a register, since the call instruction's 32-bit
3048 // pc-relative offset may not be large enough to hold the whole
3050 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
3051 // If the callee is a GlobalAddress node (quite common, every direct call
3052 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
3055 // We should use extra load for direct calls to dllimported functions in
3057 const GlobalValue *GV = G->getGlobal();
3058 if (!GV->hasDLLImportStorageClass()) {
3059 unsigned char OpFlags = 0;
3060 bool ExtraLoad = false;
3061 unsigned WrapperKind = ISD::DELETED_NODE;
3063 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
3064 // external symbols most go through the PLT in PIC mode. If the symbol
3065 // has hidden or protected visibility, or if it is static or local, then
3066 // we don't need to use the PLT - we can directly call it.
3067 if (Subtarget->isTargetELF() &&
3068 DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
3069 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
3070 OpFlags = X86II::MO_PLT;
3071 } else if (Subtarget->isPICStyleStubAny() &&
3072 (GV->isDeclaration() || GV->isWeakForLinker()) &&
3073 (!Subtarget->getTargetTriple().isMacOSX() ||
3074 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
3075 // PC-relative references to external symbols should go through $stub,
3076 // unless we're building with the leopard linker or later, which
3077 // automatically synthesizes these stubs.
3078 OpFlags = X86II::MO_DARWIN_STUB;
3079 } else if (Subtarget->isPICStyleRIPRel() &&
3080 isa<Function>(GV) &&
3081 cast<Function>(GV)->getAttributes().
3082 hasAttribute(AttributeSet::FunctionIndex,
3083 Attribute::NonLazyBind)) {
3084 // If the function is marked as non-lazy, generate an indirect call
3085 // which loads from the GOT directly. This avoids runtime overhead
3086 // at the cost of eager binding (and one extra byte of encoding).
3087 OpFlags = X86II::MO_GOTPCREL;
3088 WrapperKind = X86ISD::WrapperRIP;
3092 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(),
3093 G->getOffset(), OpFlags);
3095 // Add a wrapper if needed.
3096 if (WrapperKind != ISD::DELETED_NODE)
3097 Callee = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Callee);
3098 // Add extra indirection if needed.
3100 Callee = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Callee,
3101 MachinePointerInfo::getGOT(),
3102 false, false, false, 0);
3104 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
3105 unsigned char OpFlags = 0;
3107 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to
3108 // external symbols should go through the PLT.
3109 if (Subtarget->isTargetELF() &&
3110 DAG.getTarget().getRelocationModel() == Reloc::PIC_) {
3111 OpFlags = X86II::MO_PLT;
3112 } else if (Subtarget->isPICStyleStubAny() &&
3113 (!Subtarget->getTargetTriple().isMacOSX() ||
3114 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
3115 // PC-relative references to external symbols should go through $stub,
3116 // unless we're building with the leopard linker or later, which
3117 // automatically synthesizes these stubs.
3118 OpFlags = X86II::MO_DARWIN_STUB;
3121 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(),
3123 } else if (Subtarget->isTarget64BitILP32() && Callee->getValueType(0) == MVT::i32) {
3124 // Zero-extend the 32-bit Callee address into a 64-bit according to x32 ABI
3125 Callee = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, Callee);
3128 // Returns a chain & a flag for retval copy to use.
3129 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
3130 SmallVector<SDValue, 8> Ops;
3132 if (!IsSibcall && isTailCall) {
3133 Chain = DAG.getCALLSEQ_END(Chain,
3134 DAG.getIntPtrConstant(NumBytesToPop, true),
3135 DAG.getIntPtrConstant(0, true), InFlag, dl);
3136 InFlag = Chain.getValue(1);
3139 Ops.push_back(Chain);
3140 Ops.push_back(Callee);
3143 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32));
3145 // Add argument registers to the end of the list so that they are known live
3147 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
3148 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
3149 RegsToPass[i].second.getValueType()));
3151 // Add a register mask operand representing the call-preserved registers.
3152 const TargetRegisterInfo *TRI = DAG.getSubtarget().getRegisterInfo();
3153 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv);
3154 assert(Mask && "Missing call preserved mask for calling convention");
3155 Ops.push_back(DAG.getRegisterMask(Mask));
3157 if (InFlag.getNode())
3158 Ops.push_back(InFlag);
3162 //// If this is the first return lowered for this function, add the regs
3163 //// to the liveout set for the function.
3164 // This isn't right, although it's probably harmless on x86; liveouts
3165 // should be computed from returns not tail calls. Consider a void
3166 // function making a tail call to a function returning int.
3167 return DAG.getNode(X86ISD::TC_RETURN, dl, NodeTys, Ops);
3170 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, Ops);
3171 InFlag = Chain.getValue(1);
3173 // Create the CALLSEQ_END node.
3174 unsigned NumBytesForCalleeToPop;
3175 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
3176 DAG.getTarget().Options.GuaranteedTailCallOpt))
3177 NumBytesForCalleeToPop = NumBytes; // Callee pops everything
3178 else if (!Is64Bit && !IsTailCallConvention(CallConv) &&
3179 !Subtarget->getTargetTriple().isOSMSVCRT() &&
3180 SR == StackStructReturn)
3181 // If this is a call to a struct-return function, the callee
3182 // pops the hidden struct pointer, so we have to push it back.
3183 // This is common for Darwin/X86, Linux & Mingw32 targets.
3184 // For MSVC Win32 targets, the caller pops the hidden struct pointer.
3185 NumBytesForCalleeToPop = 4;
3187 NumBytesForCalleeToPop = 0; // Callee pops nothing.
3189 // Returns a flag for retval copy to use.
3191 Chain = DAG.getCALLSEQ_END(Chain,
3192 DAG.getIntPtrConstant(NumBytesToPop, true),
3193 DAG.getIntPtrConstant(NumBytesForCalleeToPop,
3196 InFlag = Chain.getValue(1);
3199 // Handle result values, copying them out of physregs into vregs that we
3201 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
3202 Ins, dl, DAG, InVals);
3205 //===----------------------------------------------------------------------===//
3206 // Fast Calling Convention (tail call) implementation
3207 //===----------------------------------------------------------------------===//
3209 // Like std call, callee cleans arguments, convention except that ECX is
3210 // reserved for storing the tail called function address. Only 2 registers are
3211 // free for argument passing (inreg). Tail call optimization is performed
3213 // * tailcallopt is enabled
3214 // * caller/callee are fastcc
3215 // On X86_64 architecture with GOT-style position independent code only local
3216 // (within module) calls are supported at the moment.
3217 // To keep the stack aligned according to platform abi the function
3218 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
3219 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
3220 // If a tail called function callee has more arguments than the caller the
3221 // caller needs to make sure that there is room to move the RETADDR to. This is
3222 // achieved by reserving an area the size of the argument delta right after the
3223 // original RETADDR, but before the saved framepointer or the spilled registers
3224 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
3236 /// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned
3237 /// for a 16 byte align requirement.
3239 X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
3240 SelectionDAG& DAG) const {
3241 MachineFunction &MF = DAG.getMachineFunction();
3242 const TargetMachine &TM = MF.getTarget();
3243 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
3244 TM.getSubtargetImpl()->getRegisterInfo());
3245 const TargetFrameLowering &TFI = *TM.getSubtargetImpl()->getFrameLowering();
3246 unsigned StackAlignment = TFI.getStackAlignment();
3247 uint64_t AlignMask = StackAlignment - 1;
3248 int64_t Offset = StackSize;
3249 unsigned SlotSize = RegInfo->getSlotSize();
3250 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
3251 // Number smaller than 12 so just add the difference.
3252 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
3254 // Mask out lower bits, add stackalignment once plus the 12 bytes.
3255 Offset = ((~AlignMask) & Offset) + StackAlignment +
3256 (StackAlignment-SlotSize);
3261 /// MatchingStackOffset - Return true if the given stack call argument is
3262 /// already available in the same position (relatively) of the caller's
3263 /// incoming argument stack.
3265 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
3266 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
3267 const X86InstrInfo *TII) {
3268 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
3270 if (Arg.getOpcode() == ISD::CopyFromReg) {
3271 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
3272 if (!TargetRegisterInfo::isVirtualRegister(VR))
3274 MachineInstr *Def = MRI->getVRegDef(VR);
3277 if (!Flags.isByVal()) {
3278 if (!TII->isLoadFromStackSlot(Def, FI))
3281 unsigned Opcode = Def->getOpcode();
3282 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r) &&
3283 Def->getOperand(1).isFI()) {
3284 FI = Def->getOperand(1).getIndex();
3285 Bytes = Flags.getByValSize();
3289 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
3290 if (Flags.isByVal())
3291 // ByVal argument is passed in as a pointer but it's now being
3292 // dereferenced. e.g.
3293 // define @foo(%struct.X* %A) {
3294 // tail call @bar(%struct.X* byval %A)
3297 SDValue Ptr = Ld->getBasePtr();
3298 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
3301 FI = FINode->getIndex();
3302 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) {
3303 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg);
3304 FI = FINode->getIndex();
3305 Bytes = Flags.getByValSize();
3309 assert(FI != INT_MAX);
3310 if (!MFI->isFixedObjectIndex(FI))
3312 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
3315 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
3316 /// for tail call optimization. Targets which want to do tail call
3317 /// optimization should implement this function.
3319 X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
3320 CallingConv::ID CalleeCC,
3322 bool isCalleeStructRet,
3323 bool isCallerStructRet,
3325 const SmallVectorImpl<ISD::OutputArg> &Outs,
3326 const SmallVectorImpl<SDValue> &OutVals,
3327 const SmallVectorImpl<ISD::InputArg> &Ins,
3328 SelectionDAG &DAG) const {
3329 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
3332 // If -tailcallopt is specified, make fastcc functions tail-callable.
3333 const MachineFunction &MF = DAG.getMachineFunction();
3334 const Function *CallerF = MF.getFunction();
3336 // If the function return type is x86_fp80 and the callee return type is not,
3337 // then the FP_EXTEND of the call result is not a nop. It's not safe to
3338 // perform a tailcall optimization here.
3339 if (CallerF->getReturnType()->isX86_FP80Ty() && !RetTy->isX86_FP80Ty())
3342 CallingConv::ID CallerCC = CallerF->getCallingConv();
3343 bool CCMatch = CallerCC == CalleeCC;
3344 bool IsCalleeWin64 = Subtarget->isCallingConvWin64(CalleeCC);
3345 bool IsCallerWin64 = Subtarget->isCallingConvWin64(CallerCC);
3347 if (DAG.getTarget().Options.GuaranteedTailCallOpt) {
3348 if (IsTailCallConvention(CalleeCC) && CCMatch)
3353 // Look for obvious safe cases to perform tail call optimization that do not
3354 // require ABI changes. This is what gcc calls sibcall.
3356 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
3357 // emit a special epilogue.
3358 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
3359 DAG.getSubtarget().getRegisterInfo());
3360 if (RegInfo->needsStackRealignment(MF))
3363 // Also avoid sibcall optimization if either caller or callee uses struct
3364 // return semantics.
3365 if (isCalleeStructRet || isCallerStructRet)
3368 // An stdcall/thiscall caller is expected to clean up its arguments; the
3369 // callee isn't going to do that.
3370 // FIXME: this is more restrictive than needed. We could produce a tailcall
3371 // when the stack adjustment matches. For example, with a thiscall that takes
3372 // only one argument.
3373 if (!CCMatch && (CallerCC == CallingConv::X86_StdCall ||
3374 CallerCC == CallingConv::X86_ThisCall))
3377 // Do not sibcall optimize vararg calls unless all arguments are passed via
3379 if (isVarArg && !Outs.empty()) {
3381 // Optimizing for varargs on Win64 is unlikely to be safe without
3382 // additional testing.
3383 if (IsCalleeWin64 || IsCallerWin64)
3386 SmallVector<CCValAssign, 16> ArgLocs;
3387 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
3390 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3391 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
3392 if (!ArgLocs[i].isRegLoc())
3396 // If the call result is in ST0 / ST1, it needs to be popped off the x87
3397 // stack. Therefore, if it's not used by the call it is not safe to optimize
3398 // this into a sibcall.
3399 bool Unused = false;
3400 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
3407 SmallVector<CCValAssign, 16> RVLocs;
3408 CCState CCInfo(CalleeCC, false, DAG.getMachineFunction(), RVLocs,
3410 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
3411 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
3412 CCValAssign &VA = RVLocs[i];
3413 if (VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1)
3418 // If the calling conventions do not match, then we'd better make sure the
3419 // results are returned in the same way as what the caller expects.
3421 SmallVector<CCValAssign, 16> RVLocs1;
3422 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(), RVLocs1,
3424 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86);
3426 SmallVector<CCValAssign, 16> RVLocs2;
3427 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(), RVLocs2,
3429 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86);
3431 if (RVLocs1.size() != RVLocs2.size())
3433 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
3434 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
3436 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
3438 if (RVLocs1[i].isRegLoc()) {
3439 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
3442 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
3448 // If the callee takes no arguments then go on to check the results of the
3450 if (!Outs.empty()) {
3451 // Check if stack adjustment is needed. For now, do not do this if any
3452 // argument is passed on the stack.
3453 SmallVector<CCValAssign, 16> ArgLocs;
3454 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
3457 // Allocate shadow area for Win64
3459 CCInfo.AllocateStack(32, 8);
3461 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3462 if (CCInfo.getNextStackOffset()) {
3463 MachineFunction &MF = DAG.getMachineFunction();
3464 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn())
3467 // Check if the arguments are already laid out in the right way as
3468 // the caller's fixed stack objects.
3469 MachineFrameInfo *MFI = MF.getFrameInfo();
3470 const MachineRegisterInfo *MRI = &MF.getRegInfo();
3471 const X86InstrInfo *TII =
3472 static_cast<const X86InstrInfo *>(DAG.getSubtarget().getInstrInfo());
3473 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3474 CCValAssign &VA = ArgLocs[i];
3475 SDValue Arg = OutVals[i];
3476 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3477 if (VA.getLocInfo() == CCValAssign::Indirect)
3479 if (!VA.isRegLoc()) {
3480 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
3487 // If the tailcall address may be in a register, then make sure it's
3488 // possible to register allocate for it. In 32-bit, the call address can
3489 // only target EAX, EDX, or ECX since the tail call must be scheduled after
3490 // callee-saved registers are restored. These happen to be the same
3491 // registers used to pass 'inreg' arguments so watch out for those.
3492 if (!Subtarget->is64Bit() &&
3493 ((!isa<GlobalAddressSDNode>(Callee) &&
3494 !isa<ExternalSymbolSDNode>(Callee)) ||
3495 DAG.getTarget().getRelocationModel() == Reloc::PIC_)) {
3496 unsigned NumInRegs = 0;
3497 // In PIC we need an extra register to formulate the address computation
3499 unsigned MaxInRegs =
3500 (DAG.getTarget().getRelocationModel() == Reloc::PIC_) ? 2 : 3;
3502 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3503 CCValAssign &VA = ArgLocs[i];
3506 unsigned Reg = VA.getLocReg();
3509 case X86::EAX: case X86::EDX: case X86::ECX:
3510 if (++NumInRegs == MaxInRegs)
3522 X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
3523 const TargetLibraryInfo *libInfo) const {
3524 return X86::createFastISel(funcInfo, libInfo);
3527 //===----------------------------------------------------------------------===//
3528 // Other Lowering Hooks
3529 //===----------------------------------------------------------------------===//
3531 static bool MayFoldLoad(SDValue Op) {
3532 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode());
3535 static bool MayFoldIntoStore(SDValue Op) {
3536 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin());
3539 static bool isTargetShuffle(unsigned Opcode) {
3541 default: return false;
3542 case X86ISD::BLENDI:
3543 case X86ISD::PSHUFB:
3544 case X86ISD::PSHUFD:
3545 case X86ISD::PSHUFHW:
3546 case X86ISD::PSHUFLW:
3548 case X86ISD::PALIGNR:
3549 case X86ISD::MOVLHPS:
3550 case X86ISD::MOVLHPD:
3551 case X86ISD::MOVHLPS:
3552 case X86ISD::MOVLPS:
3553 case X86ISD::MOVLPD:
3554 case X86ISD::MOVSHDUP:
3555 case X86ISD::MOVSLDUP:
3556 case X86ISD::MOVDDUP:
3559 case X86ISD::UNPCKL:
3560 case X86ISD::UNPCKH:
3561 case X86ISD::VPERMILPI:
3562 case X86ISD::VPERM2X128:
3563 case X86ISD::VPERMI:
3568 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3569 SDValue V1, SelectionDAG &DAG) {
3571 default: llvm_unreachable("Unknown x86 shuffle node");
3572 case X86ISD::MOVSHDUP:
3573 case X86ISD::MOVSLDUP:
3574 case X86ISD::MOVDDUP:
3575 return DAG.getNode(Opc, dl, VT, V1);
3579 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3580 SDValue V1, unsigned TargetMask,
3581 SelectionDAG &DAG) {
3583 default: llvm_unreachable("Unknown x86 shuffle node");
3584 case X86ISD::PSHUFD:
3585 case X86ISD::PSHUFHW:
3586 case X86ISD::PSHUFLW:
3587 case X86ISD::VPERMILPI:
3588 case X86ISD::VPERMI:
3589 return DAG.getNode(Opc, dl, VT, V1, DAG.getConstant(TargetMask, MVT::i8));
3593 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3594 SDValue V1, SDValue V2, unsigned TargetMask,
3595 SelectionDAG &DAG) {
3597 default: llvm_unreachable("Unknown x86 shuffle node");
3598 case X86ISD::PALIGNR:
3599 case X86ISD::VALIGN:
3601 case X86ISD::VPERM2X128:
3602 return DAG.getNode(Opc, dl, VT, V1, V2,
3603 DAG.getConstant(TargetMask, MVT::i8));
3607 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3608 SDValue V1, SDValue V2, SelectionDAG &DAG) {
3610 default: llvm_unreachable("Unknown x86 shuffle node");
3611 case X86ISD::MOVLHPS:
3612 case X86ISD::MOVLHPD:
3613 case X86ISD::MOVHLPS:
3614 case X86ISD::MOVLPS:
3615 case X86ISD::MOVLPD:
3618 case X86ISD::UNPCKL:
3619 case X86ISD::UNPCKH:
3620 return DAG.getNode(Opc, dl, VT, V1, V2);
3624 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
3625 MachineFunction &MF = DAG.getMachineFunction();
3626 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
3627 DAG.getSubtarget().getRegisterInfo());
3628 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
3629 int ReturnAddrIndex = FuncInfo->getRAIndex();
3631 if (ReturnAddrIndex == 0) {
3632 // Set up a frame object for the return address.
3633 unsigned SlotSize = RegInfo->getSlotSize();
3634 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize,
3637 FuncInfo->setRAIndex(ReturnAddrIndex);
3640 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
3643 bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
3644 bool hasSymbolicDisplacement) {
3645 // Offset should fit into 32 bit immediate field.
3646 if (!isInt<32>(Offset))
3649 // If we don't have a symbolic displacement - we don't have any extra
3651 if (!hasSymbolicDisplacement)
3654 // FIXME: Some tweaks might be needed for medium code model.
3655 if (M != CodeModel::Small && M != CodeModel::Kernel)
3658 // For small code model we assume that latest object is 16MB before end of 31
3659 // bits boundary. We may also accept pretty large negative constants knowing
3660 // that all objects are in the positive half of address space.
3661 if (M == CodeModel::Small && Offset < 16*1024*1024)
3664 // For kernel code model we know that all object resist in the negative half
3665 // of 32bits address space. We may not accept negative offsets, since they may
3666 // be just off and we may accept pretty large positive ones.
3667 if (M == CodeModel::Kernel && Offset > 0)
3673 /// isCalleePop - Determines whether the callee is required to pop its
3674 /// own arguments. Callee pop is necessary to support tail calls.
3675 bool X86::isCalleePop(CallingConv::ID CallingConv,
3676 bool is64Bit, bool IsVarArg, bool TailCallOpt) {
3677 switch (CallingConv) {
3680 case CallingConv::X86_StdCall:
3681 case CallingConv::X86_FastCall:
3682 case CallingConv::X86_ThisCall:
3684 case CallingConv::Fast:
3685 case CallingConv::GHC:
3686 case CallingConv::HiPE:
3693 /// \brief Return true if the condition is an unsigned comparison operation.
3694 static bool isX86CCUnsigned(unsigned X86CC) {
3696 default: llvm_unreachable("Invalid integer condition!");
3697 case X86::COND_E: return true;
3698 case X86::COND_G: return false;
3699 case X86::COND_GE: return false;
3700 case X86::COND_L: return false;
3701 case X86::COND_LE: return false;
3702 case X86::COND_NE: return true;
3703 case X86::COND_B: return true;
3704 case X86::COND_A: return true;
3705 case X86::COND_BE: return true;
3706 case X86::COND_AE: return true;
3708 llvm_unreachable("covered switch fell through?!");
3711 /// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86
3712 /// specific condition code, returning the condition code and the LHS/RHS of the
3713 /// comparison to make.
3714 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
3715 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
3717 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
3718 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
3719 // X > -1 -> X == 0, jump !sign.
3720 RHS = DAG.getConstant(0, RHS.getValueType());
3721 return X86::COND_NS;
3723 if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
3724 // X < 0 -> X == 0, jump on sign.
3727 if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
3729 RHS = DAG.getConstant(0, RHS.getValueType());
3730 return X86::COND_LE;
3734 switch (SetCCOpcode) {
3735 default: llvm_unreachable("Invalid integer condition!");
3736 case ISD::SETEQ: return X86::COND_E;
3737 case ISD::SETGT: return X86::COND_G;
3738 case ISD::SETGE: return X86::COND_GE;
3739 case ISD::SETLT: return X86::COND_L;
3740 case ISD::SETLE: return X86::COND_LE;
3741 case ISD::SETNE: return X86::COND_NE;
3742 case ISD::SETULT: return X86::COND_B;
3743 case ISD::SETUGT: return X86::COND_A;
3744 case ISD::SETULE: return X86::COND_BE;
3745 case ISD::SETUGE: return X86::COND_AE;
3749 // First determine if it is required or is profitable to flip the operands.
3751 // If LHS is a foldable load, but RHS is not, flip the condition.
3752 if (ISD::isNON_EXTLoad(LHS.getNode()) &&
3753 !ISD::isNON_EXTLoad(RHS.getNode())) {
3754 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
3755 std::swap(LHS, RHS);
3758 switch (SetCCOpcode) {
3764 std::swap(LHS, RHS);
3768 // On a floating point condition, the flags are set as follows:
3770 // 0 | 0 | 0 | X > Y
3771 // 0 | 0 | 1 | X < Y
3772 // 1 | 0 | 0 | X == Y
3773 // 1 | 1 | 1 | unordered
3774 switch (SetCCOpcode) {
3775 default: llvm_unreachable("Condcode should be pre-legalized away");
3777 case ISD::SETEQ: return X86::COND_E;
3778 case ISD::SETOLT: // flipped
3780 case ISD::SETGT: return X86::COND_A;
3781 case ISD::SETOLE: // flipped
3783 case ISD::SETGE: return X86::COND_AE;
3784 case ISD::SETUGT: // flipped
3786 case ISD::SETLT: return X86::COND_B;
3787 case ISD::SETUGE: // flipped
3789 case ISD::SETLE: return X86::COND_BE;
3791 case ISD::SETNE: return X86::COND_NE;
3792 case ISD::SETUO: return X86::COND_P;
3793 case ISD::SETO: return X86::COND_NP;
3795 case ISD::SETUNE: return X86::COND_INVALID;
3799 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
3800 /// code. Current x86 isa includes the following FP cmov instructions:
3801 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
3802 static bool hasFPCMov(unsigned X86CC) {
3818 /// isFPImmLegal - Returns true if the target can instruction select the
3819 /// specified FP immediate natively. If false, the legalizer will
3820 /// materialize the FP immediate as a load from a constant pool.
3821 bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
3822 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
3823 if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
3829 /// \brief Returns true if it is beneficial to convert a load of a constant
3830 /// to just the constant itself.
3831 bool X86TargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
3833 assert(Ty->isIntegerTy());
3835 unsigned BitSize = Ty->getPrimitiveSizeInBits();
3836 if (BitSize == 0 || BitSize > 64)
3841 /// isUndefOrInRange - Return true if Val is undef or if its value falls within
3842 /// the specified range (L, H].
3843 static bool isUndefOrInRange(int Val, int Low, int Hi) {
3844 return (Val < 0) || (Val >= Low && Val < Hi);
3847 /// isUndefOrEqual - Val is either less than zero (undef) or equal to the
3848 /// specified value.
3849 static bool isUndefOrEqual(int Val, int CmpVal) {
3850 return (Val < 0 || Val == CmpVal);
3853 /// isSequentialOrUndefInRange - Return true if every element in Mask, beginning
3854 /// from position Pos and ending in Pos+Size, falls within the specified
3855 /// sequential range (L, L+Pos]. or is undef.
3856 static bool isSequentialOrUndefInRange(ArrayRef<int> Mask,
3857 unsigned Pos, unsigned Size, int Low) {
3858 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low)
3859 if (!isUndefOrEqual(Mask[i], Low))
3864 /// isPSHUFDMask - Return true if the node specifies a shuffle of elements that
3865 /// is suitable for input to PSHUFD or PSHUFW. That is, it doesn't reference
3866 /// the second operand.
3867 static bool isPSHUFDMask(ArrayRef<int> Mask, MVT VT) {
3868 if (VT == MVT::v4f32 || VT == MVT::v4i32 )
3869 return (Mask[0] < 4 && Mask[1] < 4 && Mask[2] < 4 && Mask[3] < 4);
3870 if (VT == MVT::v2f64 || VT == MVT::v2i64)
3871 return (Mask[0] < 2 && Mask[1] < 2);
3875 /// isPSHUFHWMask - Return true if the node specifies a shuffle of elements that
3876 /// is suitable for input to PSHUFHW.
3877 static bool isPSHUFHWMask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
3878 if (VT != MVT::v8i16 && (!HasInt256 || VT != MVT::v16i16))
3881 // Lower quadword copied in order or undef.
3882 if (!isSequentialOrUndefInRange(Mask, 0, 4, 0))
3885 // Upper quadword shuffled.
3886 for (unsigned i = 4; i != 8; ++i)
3887 if (!isUndefOrInRange(Mask[i], 4, 8))
3890 if (VT == MVT::v16i16) {
3891 // Lower quadword copied in order or undef.
3892 if (!isSequentialOrUndefInRange(Mask, 8, 4, 8))
3895 // Upper quadword shuffled.
3896 for (unsigned i = 12; i != 16; ++i)
3897 if (!isUndefOrInRange(Mask[i], 12, 16))
3904 /// isPSHUFLWMask - Return true if the node specifies a shuffle of elements that
3905 /// is suitable for input to PSHUFLW.
3906 static bool isPSHUFLWMask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
3907 if (VT != MVT::v8i16 && (!HasInt256 || VT != MVT::v16i16))
3910 // Upper quadword copied in order.
3911 if (!isSequentialOrUndefInRange(Mask, 4, 4, 4))
3914 // Lower quadword shuffled.
3915 for (unsigned i = 0; i != 4; ++i)
3916 if (!isUndefOrInRange(Mask[i], 0, 4))
3919 if (VT == MVT::v16i16) {
3920 // Upper quadword copied in order.
3921 if (!isSequentialOrUndefInRange(Mask, 12, 4, 12))
3924 // Lower quadword shuffled.
3925 for (unsigned i = 8; i != 12; ++i)
3926 if (!isUndefOrInRange(Mask[i], 8, 12))
3933 /// \brief Return true if the mask specifies a shuffle of elements that is
3934 /// suitable for input to intralane (palignr) or interlane (valign) vector
3936 static bool isAlignrMask(ArrayRef<int> Mask, MVT VT, bool InterLane) {
3937 unsigned NumElts = VT.getVectorNumElements();
3938 unsigned NumLanes = InterLane ? 1: VT.getSizeInBits()/128;
3939 unsigned NumLaneElts = NumElts/NumLanes;
3941 // Do not handle 64-bit element shuffles with palignr.
3942 if (NumLaneElts == 2)
3945 for (unsigned l = 0; l != NumElts; l+=NumLaneElts) {
3947 for (i = 0; i != NumLaneElts; ++i) {
3952 // Lane is all undef, go to next lane
3953 if (i == NumLaneElts)
3956 int Start = Mask[i+l];
3958 // Make sure its in this lane in one of the sources
3959 if (!isUndefOrInRange(Start, l, l+NumLaneElts) &&
3960 !isUndefOrInRange(Start, l+NumElts, l+NumElts+NumLaneElts))
3963 // If not lane 0, then we must match lane 0
3964 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Start, Mask[i]+l))
3967 // Correct second source to be contiguous with first source
3968 if (Start >= (int)NumElts)
3969 Start -= NumElts - NumLaneElts;
3971 // Make sure we're shifting in the right direction.
3972 if (Start <= (int)(i+l))
3977 // Check the rest of the elements to see if they are consecutive.
3978 for (++i; i != NumLaneElts; ++i) {
3979 int Idx = Mask[i+l];
3981 // Make sure its in this lane
3982 if (!isUndefOrInRange(Idx, l, l+NumLaneElts) &&
3983 !isUndefOrInRange(Idx, l+NumElts, l+NumElts+NumLaneElts))
3986 // If not lane 0, then we must match lane 0
3987 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Idx, Mask[i]+l))
3990 if (Idx >= (int)NumElts)
3991 Idx -= NumElts - NumLaneElts;
3993 if (!isUndefOrEqual(Idx, Start+i))
4002 /// \brief Return true if the node specifies a shuffle of elements that is
4003 /// suitable for input to PALIGNR.
4004 static bool isPALIGNRMask(ArrayRef<int> Mask, MVT VT,
4005 const X86Subtarget *Subtarget) {
4006 if ((VT.is128BitVector() && !Subtarget->hasSSSE3()) ||
4007 (VT.is256BitVector() && !Subtarget->hasInt256()) ||
4008 VT.is512BitVector())
4009 // FIXME: Add AVX512BW.
4012 return isAlignrMask(Mask, VT, false);
4015 /// \brief Return true if the node specifies a shuffle of elements that is
4016 /// suitable for input to VALIGN.
4017 static bool isVALIGNMask(ArrayRef<int> Mask, MVT VT,
4018 const X86Subtarget *Subtarget) {
4019 // FIXME: Add AVX512VL.
4020 if (!VT.is512BitVector() || !Subtarget->hasAVX512())
4022 return isAlignrMask(Mask, VT, true);
4025 /// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming
4026 /// the two vector operands have swapped position.
4027 static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask,
4028 unsigned NumElems) {
4029 for (unsigned i = 0; i != NumElems; ++i) {
4033 else if (idx < (int)NumElems)
4034 Mask[i] = idx + NumElems;
4036 Mask[i] = idx - NumElems;
4040 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
4041 /// specifies a shuffle of elements that is suitable for input to 128/256-bit
4042 /// SHUFPS and SHUFPD. If Commuted is true, then it checks for sources to be
4043 /// reverse of what x86 shuffles want.
4044 static bool isSHUFPMask(ArrayRef<int> Mask, MVT VT, bool Commuted = false) {
4046 unsigned NumElems = VT.getVectorNumElements();
4047 unsigned NumLanes = VT.getSizeInBits()/128;
4048 unsigned NumLaneElems = NumElems/NumLanes;
4050 if (NumLaneElems != 2 && NumLaneElems != 4)
4053 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4054 bool symetricMaskRequired =
4055 (VT.getSizeInBits() >= 256) && (EltSize == 32);
4057 // VSHUFPSY divides the resulting vector into 4 chunks.
4058 // The sources are also splitted into 4 chunks, and each destination
4059 // chunk must come from a different source chunk.
4061 // SRC1 => X7 X6 X5 X4 X3 X2 X1 X0
4062 // SRC2 => Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y9
4064 // DST => Y7..Y4, Y7..Y4, X7..X4, X7..X4,
4065 // Y3..Y0, Y3..Y0, X3..X0, X3..X0
4067 // VSHUFPDY divides the resulting vector into 4 chunks.
4068 // The sources are also splitted into 4 chunks, and each destination
4069 // chunk must come from a different source chunk.
4071 // SRC1 => X3 X2 X1 X0
4072 // SRC2 => Y3 Y2 Y1 Y0
4074 // DST => Y3..Y2, X3..X2, Y1..Y0, X1..X0
4076 SmallVector<int, 4> MaskVal(NumLaneElems, -1);
4077 unsigned HalfLaneElems = NumLaneElems/2;
4078 for (unsigned l = 0; l != NumElems; l += NumLaneElems) {
4079 for (unsigned i = 0; i != NumLaneElems; ++i) {
4080 int Idx = Mask[i+l];
4081 unsigned RngStart = l + ((Commuted == (i<HalfLaneElems)) ? NumElems : 0);
4082 if (!isUndefOrInRange(Idx, RngStart, RngStart+NumLaneElems))
4084 // For VSHUFPSY, the mask of the second half must be the same as the
4085 // first but with the appropriate offsets. This works in the same way as
4086 // VPERMILPS works with masks.
4087 if (!symetricMaskRequired || Idx < 0)
4089 if (MaskVal[i] < 0) {
4090 MaskVal[i] = Idx - l;
4093 if ((signed)(Idx - l) != MaskVal[i])
4101 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
4102 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
4103 static bool isMOVHLPSMask(ArrayRef<int> Mask, MVT VT) {
4104 if (!VT.is128BitVector())
4107 unsigned NumElems = VT.getVectorNumElements();
4112 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3
4113 return isUndefOrEqual(Mask[0], 6) &&
4114 isUndefOrEqual(Mask[1], 7) &&
4115 isUndefOrEqual(Mask[2], 2) &&
4116 isUndefOrEqual(Mask[3], 3);
4119 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
4120 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
4122 static bool isMOVHLPS_v_undef_Mask(ArrayRef<int> Mask, MVT VT) {
4123 if (!VT.is128BitVector())
4126 unsigned NumElems = VT.getVectorNumElements();
4131 return isUndefOrEqual(Mask[0], 2) &&
4132 isUndefOrEqual(Mask[1], 3) &&
4133 isUndefOrEqual(Mask[2], 2) &&
4134 isUndefOrEqual(Mask[3], 3);
4137 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
4138 /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
4139 static bool isMOVLPMask(ArrayRef<int> Mask, MVT VT) {
4140 if (!VT.is128BitVector())
4143 unsigned NumElems = VT.getVectorNumElements();
4145 if (NumElems != 2 && NumElems != 4)
4148 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4149 if (!isUndefOrEqual(Mask[i], i + NumElems))
4152 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i)
4153 if (!isUndefOrEqual(Mask[i], i))
4159 /// isMOVLHPSMask - Return true if the specified VECTOR_SHUFFLE operand
4160 /// specifies a shuffle of elements that is suitable for input to MOVLHPS.
4161 static bool isMOVLHPSMask(ArrayRef<int> Mask, MVT VT) {
4162 if (!VT.is128BitVector())
4165 unsigned NumElems = VT.getVectorNumElements();
4167 if (NumElems != 2 && NumElems != 4)
4170 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4171 if (!isUndefOrEqual(Mask[i], i))
4174 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4175 if (!isUndefOrEqual(Mask[i + e], i + NumElems))
4181 /// isINSERTPSMask - Return true if the specified VECTOR_SHUFFLE operand
4182 /// specifies a shuffle of elements that is suitable for input to INSERTPS.
4183 /// i. e: If all but one element come from the same vector.
4184 static bool isINSERTPSMask(ArrayRef<int> Mask, MVT VT) {
4185 // TODO: Deal with AVX's VINSERTPS
4186 if (!VT.is128BitVector() || (VT != MVT::v4f32 && VT != MVT::v4i32))
4189 unsigned CorrectPosV1 = 0;
4190 unsigned CorrectPosV2 = 0;
4191 for (int i = 0, e = (int)VT.getVectorNumElements(); i != e; ++i) {
4192 if (Mask[i] == -1) {
4200 else if (Mask[i] == i + 4)
4204 if (CorrectPosV1 == 3 || CorrectPosV2 == 3)
4205 // We have 3 elements (undefs count as elements from any vector) from one
4206 // vector, and one from another.
4213 // Some special combinations that can be optimized.
4216 SDValue Compact8x32ShuffleNode(ShuffleVectorSDNode *SVOp,
4217 SelectionDAG &DAG) {
4218 MVT VT = SVOp->getSimpleValueType(0);
4221 if (VT != MVT::v8i32 && VT != MVT::v8f32)
4224 ArrayRef<int> Mask = SVOp->getMask();
4226 // These are the special masks that may be optimized.
4227 static const int MaskToOptimizeEven[] = {0, 8, 2, 10, 4, 12, 6, 14};
4228 static const int MaskToOptimizeOdd[] = {1, 9, 3, 11, 5, 13, 7, 15};
4229 bool MatchEvenMask = true;
4230 bool MatchOddMask = true;
4231 for (int i=0; i<8; ++i) {
4232 if (!isUndefOrEqual(Mask[i], MaskToOptimizeEven[i]))
4233 MatchEvenMask = false;
4234 if (!isUndefOrEqual(Mask[i], MaskToOptimizeOdd[i]))
4235 MatchOddMask = false;
4238 if (!MatchEvenMask && !MatchOddMask)
4241 SDValue UndefNode = DAG.getNode(ISD::UNDEF, dl, VT);
4243 SDValue Op0 = SVOp->getOperand(0);
4244 SDValue Op1 = SVOp->getOperand(1);
4246 if (MatchEvenMask) {
4247 // Shift the second operand right to 32 bits.
4248 static const int ShiftRightMask[] = {-1, 0, -1, 2, -1, 4, -1, 6 };
4249 Op1 = DAG.getVectorShuffle(VT, dl, Op1, UndefNode, ShiftRightMask);
4251 // Shift the first operand left to 32 bits.
4252 static const int ShiftLeftMask[] = {1, -1, 3, -1, 5, -1, 7, -1 };
4253 Op0 = DAG.getVectorShuffle(VT, dl, Op0, UndefNode, ShiftLeftMask);
4255 static const int BlendMask[] = {0, 9, 2, 11, 4, 13, 6, 15};
4256 return DAG.getVectorShuffle(VT, dl, Op0, Op1, BlendMask);
4259 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
4260 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
4261 static bool isUNPCKLMask(ArrayRef<int> Mask, MVT VT,
4262 bool HasInt256, bool V2IsSplat = false) {
4264 assert(VT.getSizeInBits() >= 128 &&
4265 "Unsupported vector type for unpckl");
4267 unsigned NumElts = VT.getVectorNumElements();
4268 if (VT.is256BitVector() && NumElts != 4 && NumElts != 8 &&
4269 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4272 assert((!VT.is512BitVector() || VT.getScalarType().getSizeInBits() >= 32) &&
4273 "Unsupported vector type for unpckh");
4275 // AVX defines UNPCK* to operate independently on 128-bit lanes.
4276 unsigned NumLanes = VT.getSizeInBits()/128;
4277 unsigned NumLaneElts = NumElts/NumLanes;
4279 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4280 for (unsigned i = 0, j = l; i != NumLaneElts; i += 2, ++j) {
4281 int BitI = Mask[l+i];
4282 int BitI1 = Mask[l+i+1];
4283 if (!isUndefOrEqual(BitI, j))
4286 if (!isUndefOrEqual(BitI1, NumElts))
4289 if (!isUndefOrEqual(BitI1, j + NumElts))
4298 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
4299 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
4300 static bool isUNPCKHMask(ArrayRef<int> Mask, MVT VT,
4301 bool HasInt256, bool V2IsSplat = false) {
4302 assert(VT.getSizeInBits() >= 128 &&
4303 "Unsupported vector type for unpckh");
4305 unsigned NumElts = VT.getVectorNumElements();
4306 if (VT.is256BitVector() && NumElts != 4 && NumElts != 8 &&
4307 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4310 assert((!VT.is512BitVector() || VT.getScalarType().getSizeInBits() >= 32) &&
4311 "Unsupported vector type for unpckh");
4313 // AVX defines UNPCK* to operate independently on 128-bit lanes.
4314 unsigned NumLanes = VT.getSizeInBits()/128;
4315 unsigned NumLaneElts = NumElts/NumLanes;
4317 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4318 for (unsigned i = 0, j = l+NumLaneElts/2; i != NumLaneElts; i += 2, ++j) {
4319 int BitI = Mask[l+i];
4320 int BitI1 = Mask[l+i+1];
4321 if (!isUndefOrEqual(BitI, j))
4324 if (isUndefOrEqual(BitI1, NumElts))
4327 if (!isUndefOrEqual(BitI1, j+NumElts))
4335 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
4336 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
4338 static bool isUNPCKL_v_undef_Mask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
4339 unsigned NumElts = VT.getVectorNumElements();
4340 bool Is256BitVec = VT.is256BitVector();
4342 if (VT.is512BitVector())
4344 assert((VT.is128BitVector() || VT.is256BitVector()) &&
4345 "Unsupported vector type for unpckh");
4347 if (Is256BitVec && NumElts != 4 && NumElts != 8 &&
4348 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4351 // For 256-bit i64/f64, use MOVDDUPY instead, so reject the matching pattern
4352 // FIXME: Need a better way to get rid of this, there's no latency difference
4353 // between UNPCKLPD and MOVDDUP, the later should always be checked first and
4354 // the former later. We should also remove the "_undef" special mask.
4355 if (NumElts == 4 && Is256BitVec)
4358 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
4359 // independently on 128-bit lanes.
4360 unsigned NumLanes = VT.getSizeInBits()/128;
4361 unsigned NumLaneElts = NumElts/NumLanes;
4363 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4364 for (unsigned i = 0, j = l; i != NumLaneElts; i += 2, ++j) {
4365 int BitI = Mask[l+i];
4366 int BitI1 = Mask[l+i+1];
4368 if (!isUndefOrEqual(BitI, j))
4370 if (!isUndefOrEqual(BitI1, j))
4378 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
4379 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
4381 static bool isUNPCKH_v_undef_Mask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
4382 unsigned NumElts = VT.getVectorNumElements();
4384 if (VT.is512BitVector())
4387 assert((VT.is128BitVector() || VT.is256BitVector()) &&
4388 "Unsupported vector type for unpckh");
4390 if (VT.is256BitVector() && NumElts != 4 && NumElts != 8 &&
4391 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4394 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
4395 // independently on 128-bit lanes.
4396 unsigned NumLanes = VT.getSizeInBits()/128;
4397 unsigned NumLaneElts = NumElts/NumLanes;
4399 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4400 for (unsigned i = 0, j = l+NumLaneElts/2; i != NumLaneElts; i += 2, ++j) {
4401 int BitI = Mask[l+i];
4402 int BitI1 = Mask[l+i+1];
4403 if (!isUndefOrEqual(BitI, j))
4405 if (!isUndefOrEqual(BitI1, j))
4412 // Match for INSERTI64x4 INSERTF64x4 instructions (src0[0], src1[0]) or
4413 // (src1[0], src0[1]), manipulation with 256-bit sub-vectors
4414 static bool isINSERT64x4Mask(ArrayRef<int> Mask, MVT VT, unsigned int *Imm) {
4415 if (!VT.is512BitVector())
4418 unsigned NumElts = VT.getVectorNumElements();
4419 unsigned HalfSize = NumElts/2;
4420 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, 0)) {
4421 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, NumElts)) {
4426 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, NumElts)) {
4427 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, HalfSize)) {
4435 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
4436 /// specifies a shuffle of elements that is suitable for input to MOVSS,
4437 /// MOVSD, and MOVD, i.e. setting the lowest element.
4438 static bool isMOVLMask(ArrayRef<int> Mask, EVT VT) {
4439 if (VT.getVectorElementType().getSizeInBits() < 32)
4441 if (!VT.is128BitVector())
4444 unsigned NumElts = VT.getVectorNumElements();
4446 if (!isUndefOrEqual(Mask[0], NumElts))
4449 for (unsigned i = 1; i != NumElts; ++i)
4450 if (!isUndefOrEqual(Mask[i], i))
4456 /// isVPERM2X128Mask - Match 256-bit shuffles where the elements are considered
4457 /// as permutations between 128-bit chunks or halves. As an example: this
4459 /// vector_shuffle <4, 5, 6, 7, 12, 13, 14, 15>
4460 /// The first half comes from the second half of V1 and the second half from the
4461 /// the second half of V2.
4462 static bool isVPERM2X128Mask(ArrayRef<int> Mask, MVT VT, bool HasFp256) {
4463 if (!HasFp256 || !VT.is256BitVector())
4466 // The shuffle result is divided into half A and half B. In total the two
4467 // sources have 4 halves, namely: C, D, E, F. The final values of A and
4468 // B must come from C, D, E or F.
4469 unsigned HalfSize = VT.getVectorNumElements()/2;
4470 bool MatchA = false, MatchB = false;
4472 // Check if A comes from one of C, D, E, F.
4473 for (unsigned Half = 0; Half != 4; ++Half) {
4474 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, Half*HalfSize)) {
4480 // Check if B comes from one of C, D, E, F.
4481 for (unsigned Half = 0; Half != 4; ++Half) {
4482 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, Half*HalfSize)) {
4488 return MatchA && MatchB;
4491 /// getShuffleVPERM2X128Immediate - Return the appropriate immediate to shuffle
4492 /// the specified VECTOR_MASK mask with VPERM2F128/VPERM2I128 instructions.
4493 static unsigned getShuffleVPERM2X128Immediate(ShuffleVectorSDNode *SVOp) {
4494 MVT VT = SVOp->getSimpleValueType(0);
4496 unsigned HalfSize = VT.getVectorNumElements()/2;
4498 unsigned FstHalf = 0, SndHalf = 0;
4499 for (unsigned i = 0; i < HalfSize; ++i) {
4500 if (SVOp->getMaskElt(i) > 0) {
4501 FstHalf = SVOp->getMaskElt(i)/HalfSize;
4505 for (unsigned i = HalfSize; i < HalfSize*2; ++i) {
4506 if (SVOp->getMaskElt(i) > 0) {
4507 SndHalf = SVOp->getMaskElt(i)/HalfSize;
4512 return (FstHalf | (SndHalf << 4));
4515 // Symetric in-lane mask. Each lane has 4 elements (for imm8)
4516 static bool isPermImmMask(ArrayRef<int> Mask, MVT VT, unsigned& Imm8) {
4517 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4521 unsigned NumElts = VT.getVectorNumElements();
4523 if (VT.is128BitVector() || (VT.is256BitVector() && EltSize == 64)) {
4524 for (unsigned i = 0; i != NumElts; ++i) {
4527 Imm8 |= Mask[i] << (i*2);
4532 unsigned LaneSize = 4;
4533 SmallVector<int, 4> MaskVal(LaneSize, -1);
4535 for (unsigned l = 0; l != NumElts; l += LaneSize) {
4536 for (unsigned i = 0; i != LaneSize; ++i) {
4537 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize))
4541 if (MaskVal[i] < 0) {
4542 MaskVal[i] = Mask[i+l] - l;
4543 Imm8 |= MaskVal[i] << (i*2);
4546 if (Mask[i+l] != (signed)(MaskVal[i]+l))
4553 /// isVPERMILPMask - Return true if the specified VECTOR_SHUFFLE operand
4554 /// specifies a shuffle of elements that is suitable for input to VPERMILPD*.
4555 /// Note that VPERMIL mask matching is different depending whether theunderlying
4556 /// type is 32 or 64. In the VPERMILPS the high half of the mask should point
4557 /// to the same elements of the low, but to the higher half of the source.
4558 /// In VPERMILPD the two lanes could be shuffled independently of each other
4559 /// with the same restriction that lanes can't be crossed. Also handles PSHUFDY.
4560 static bool isVPERMILPMask(ArrayRef<int> Mask, MVT VT) {
4561 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4562 if (VT.getSizeInBits() < 256 || EltSize < 32)
4564 bool symetricMaskRequired = (EltSize == 32);
4565 unsigned NumElts = VT.getVectorNumElements();
4567 unsigned NumLanes = VT.getSizeInBits()/128;
4568 unsigned LaneSize = NumElts/NumLanes;
4569 // 2 or 4 elements in one lane
4571 SmallVector<int, 4> ExpectedMaskVal(LaneSize, -1);
4572 for (unsigned l = 0; l != NumElts; l += LaneSize) {
4573 for (unsigned i = 0; i != LaneSize; ++i) {
4574 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize))
4576 if (symetricMaskRequired) {
4577 if (ExpectedMaskVal[i] < 0 && Mask[i+l] >= 0) {
4578 ExpectedMaskVal[i] = Mask[i+l] - l;
4581 if (!isUndefOrEqual(Mask[i+l], ExpectedMaskVal[i]+l))
4589 /// isCommutedMOVLMask - Returns true if the shuffle mask is except the reverse
4590 /// of what x86 movss want. X86 movs requires the lowest element to be lowest
4591 /// element of vector 2 and the other elements to come from vector 1 in order.
4592 static bool isCommutedMOVLMask(ArrayRef<int> Mask, MVT VT,
4593 bool V2IsSplat = false, bool V2IsUndef = false) {
4594 if (!VT.is128BitVector())
4597 unsigned NumOps = VT.getVectorNumElements();
4598 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16)
4601 if (!isUndefOrEqual(Mask[0], 0))
4604 for (unsigned i = 1; i != NumOps; ++i)
4605 if (!(isUndefOrEqual(Mask[i], i+NumOps) ||
4606 (V2IsUndef && isUndefOrInRange(Mask[i], NumOps, NumOps*2)) ||
4607 (V2IsSplat && isUndefOrEqual(Mask[i], NumOps))))
4613 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4614 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
4615 /// Masks to match: <1, 1, 3, 3> or <1, 1, 3, 3, 5, 5, 7, 7>
4616 static bool isMOVSHDUPMask(ArrayRef<int> Mask, MVT VT,
4617 const X86Subtarget *Subtarget) {
4618 if (!Subtarget->hasSSE3())
4621 unsigned NumElems = VT.getVectorNumElements();
4623 if ((VT.is128BitVector() && NumElems != 4) ||
4624 (VT.is256BitVector() && NumElems != 8) ||
4625 (VT.is512BitVector() && NumElems != 16))
4628 // "i+1" is the value the indexed mask element must have
4629 for (unsigned i = 0; i != NumElems; i += 2)
4630 if (!isUndefOrEqual(Mask[i], i+1) ||
4631 !isUndefOrEqual(Mask[i+1], i+1))
4637 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4638 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
4639 /// Masks to match: <0, 0, 2, 2> or <0, 0, 2, 2, 4, 4, 6, 6>
4640 static bool isMOVSLDUPMask(ArrayRef<int> Mask, MVT VT,
4641 const X86Subtarget *Subtarget) {
4642 if (!Subtarget->hasSSE3())
4645 unsigned NumElems = VT.getVectorNumElements();
4647 if ((VT.is128BitVector() && NumElems != 4) ||
4648 (VT.is256BitVector() && NumElems != 8) ||
4649 (VT.is512BitVector() && NumElems != 16))
4652 // "i" is the value the indexed mask element must have
4653 for (unsigned i = 0; i != NumElems; i += 2)
4654 if (!isUndefOrEqual(Mask[i], i) ||
4655 !isUndefOrEqual(Mask[i+1], i))
4661 /// isMOVDDUPYMask - Return true if the specified VECTOR_SHUFFLE operand
4662 /// specifies a shuffle of elements that is suitable for input to 256-bit
4663 /// version of MOVDDUP.
4664 static bool isMOVDDUPYMask(ArrayRef<int> Mask, MVT VT, bool HasFp256) {
4665 if (!HasFp256 || !VT.is256BitVector())
4668 unsigned NumElts = VT.getVectorNumElements();
4672 for (unsigned i = 0; i != NumElts/2; ++i)
4673 if (!isUndefOrEqual(Mask[i], 0))
4675 for (unsigned i = NumElts/2; i != NumElts; ++i)
4676 if (!isUndefOrEqual(Mask[i], NumElts/2))
4681 /// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4682 /// specifies a shuffle of elements that is suitable for input to 128-bit
4683 /// version of MOVDDUP.
4684 static bool isMOVDDUPMask(ArrayRef<int> Mask, MVT VT) {
4685 if (!VT.is128BitVector())
4688 unsigned e = VT.getVectorNumElements() / 2;
4689 for (unsigned i = 0; i != e; ++i)
4690 if (!isUndefOrEqual(Mask[i], i))
4692 for (unsigned i = 0; i != e; ++i)
4693 if (!isUndefOrEqual(Mask[e+i], i))
4698 /// isVEXTRACTIndex - Return true if the specified
4699 /// EXTRACT_SUBVECTOR operand specifies a vector extract that is
4700 /// suitable for instruction that extract 128 or 256 bit vectors
4701 static bool isVEXTRACTIndex(SDNode *N, unsigned vecWidth) {
4702 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4703 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4706 // The index should be aligned on a vecWidth-bit boundary.
4708 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4710 MVT VT = N->getSimpleValueType(0);
4711 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4712 bool Result = (Index * ElSize) % vecWidth == 0;
4717 /// isVINSERTIndex - Return true if the specified INSERT_SUBVECTOR
4718 /// operand specifies a subvector insert that is suitable for input to
4719 /// insertion of 128 or 256-bit subvectors
4720 static bool isVINSERTIndex(SDNode *N, unsigned vecWidth) {
4721 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4722 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4724 // The index should be aligned on a vecWidth-bit boundary.
4726 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4728 MVT VT = N->getSimpleValueType(0);
4729 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4730 bool Result = (Index * ElSize) % vecWidth == 0;
4735 bool X86::isVINSERT128Index(SDNode *N) {
4736 return isVINSERTIndex(N, 128);
4739 bool X86::isVINSERT256Index(SDNode *N) {
4740 return isVINSERTIndex(N, 256);
4743 bool X86::isVEXTRACT128Index(SDNode *N) {
4744 return isVEXTRACTIndex(N, 128);
4747 bool X86::isVEXTRACT256Index(SDNode *N) {
4748 return isVEXTRACTIndex(N, 256);
4751 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
4752 /// the specified VECTOR_SHUFFLE mask with PSHUF* and SHUFP* instructions.
4753 /// Handles 128-bit and 256-bit.
4754 static unsigned getShuffleSHUFImmediate(ShuffleVectorSDNode *N) {
4755 MVT VT = N->getSimpleValueType(0);
4757 assert((VT.getSizeInBits() >= 128) &&
4758 "Unsupported vector type for PSHUF/SHUFP");
4760 // Handle 128 and 256-bit vector lengths. AVX defines PSHUF/SHUFP to operate
4761 // independently on 128-bit lanes.
4762 unsigned NumElts = VT.getVectorNumElements();
4763 unsigned NumLanes = VT.getSizeInBits()/128;
4764 unsigned NumLaneElts = NumElts/NumLanes;
4766 assert((NumLaneElts == 2 || NumLaneElts == 4 || NumLaneElts == 8) &&
4767 "Only supports 2, 4 or 8 elements per lane");
4769 unsigned Shift = (NumLaneElts >= 4) ? 1 : 0;
4771 for (unsigned i = 0; i != NumElts; ++i) {
4772 int Elt = N->getMaskElt(i);
4773 if (Elt < 0) continue;
4774 Elt &= NumLaneElts - 1;
4775 unsigned ShAmt = (i << Shift) % 8;
4776 Mask |= Elt << ShAmt;
4782 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
4783 /// the specified VECTOR_SHUFFLE mask with the PSHUFHW instruction.
4784 static unsigned getShufflePSHUFHWImmediate(ShuffleVectorSDNode *N) {
4785 MVT VT = N->getSimpleValueType(0);
4787 assert((VT == MVT::v8i16 || VT == MVT::v16i16) &&
4788 "Unsupported vector type for PSHUFHW");
4790 unsigned NumElts = VT.getVectorNumElements();
4793 for (unsigned l = 0; l != NumElts; l += 8) {
4794 // 8 nodes per lane, but we only care about the last 4.
4795 for (unsigned i = 0; i < 4; ++i) {
4796 int Elt = N->getMaskElt(l+i+4);
4797 if (Elt < 0) continue;
4798 Elt &= 0x3; // only 2-bits.
4799 Mask |= Elt << (i * 2);
4806 /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
4807 /// the specified VECTOR_SHUFFLE mask with the PSHUFLW instruction.
4808 static unsigned getShufflePSHUFLWImmediate(ShuffleVectorSDNode *N) {
4809 MVT VT = N->getSimpleValueType(0);
4811 assert((VT == MVT::v8i16 || VT == MVT::v16i16) &&
4812 "Unsupported vector type for PSHUFHW");
4814 unsigned NumElts = VT.getVectorNumElements();
4817 for (unsigned l = 0; l != NumElts; l += 8) {
4818 // 8 nodes per lane, but we only care about the first 4.
4819 for (unsigned i = 0; i < 4; ++i) {
4820 int Elt = N->getMaskElt(l+i);
4821 if (Elt < 0) continue;
4822 Elt &= 0x3; // only 2-bits
4823 Mask |= Elt << (i * 2);
4830 /// \brief Return the appropriate immediate to shuffle the specified
4831 /// VECTOR_SHUFFLE mask with the PALIGNR (if InterLane is false) or with
4832 /// VALIGN (if Interlane is true) instructions.
4833 static unsigned getShuffleAlignrImmediate(ShuffleVectorSDNode *SVOp,
4835 MVT VT = SVOp->getSimpleValueType(0);
4836 unsigned EltSize = InterLane ? 1 :
4837 VT.getVectorElementType().getSizeInBits() >> 3;
4839 unsigned NumElts = VT.getVectorNumElements();
4840 unsigned NumLanes = VT.is512BitVector() ? 1 : VT.getSizeInBits()/128;
4841 unsigned NumLaneElts = NumElts/NumLanes;
4845 for (i = 0; i != NumElts; ++i) {
4846 Val = SVOp->getMaskElt(i);
4850 if (Val >= (int)NumElts)
4851 Val -= NumElts - NumLaneElts;
4853 assert(Val - i > 0 && "PALIGNR imm should be positive");
4854 return (Val - i) * EltSize;
4857 /// \brief Return the appropriate immediate to shuffle the specified
4858 /// VECTOR_SHUFFLE mask with the PALIGNR instruction.
4859 static unsigned getShufflePALIGNRImmediate(ShuffleVectorSDNode *SVOp) {
4860 return getShuffleAlignrImmediate(SVOp, false);
4863 /// \brief Return the appropriate immediate to shuffle the specified
4864 /// VECTOR_SHUFFLE mask with the VALIGN instruction.
4865 static unsigned getShuffleVALIGNImmediate(ShuffleVectorSDNode *SVOp) {
4866 return getShuffleAlignrImmediate(SVOp, true);
4870 static unsigned getExtractVEXTRACTImmediate(SDNode *N, unsigned vecWidth) {
4871 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4872 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4873 llvm_unreachable("Illegal extract subvector for VEXTRACT");
4876 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4878 MVT VecVT = N->getOperand(0).getSimpleValueType();
4879 MVT ElVT = VecVT.getVectorElementType();
4881 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4882 return Index / NumElemsPerChunk;
4885 static unsigned getInsertVINSERTImmediate(SDNode *N, unsigned vecWidth) {
4886 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4887 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4888 llvm_unreachable("Illegal insert subvector for VINSERT");
4891 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4893 MVT VecVT = N->getSimpleValueType(0);
4894 MVT ElVT = VecVT.getVectorElementType();
4896 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4897 return Index / NumElemsPerChunk;
4900 /// getExtractVEXTRACT128Immediate - Return the appropriate immediate
4901 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF128
4902 /// and VINSERTI128 instructions.
4903 unsigned X86::getExtractVEXTRACT128Immediate(SDNode *N) {
4904 return getExtractVEXTRACTImmediate(N, 128);
4907 /// getExtractVEXTRACT256Immediate - Return the appropriate immediate
4908 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF64x4
4909 /// and VINSERTI64x4 instructions.
4910 unsigned X86::getExtractVEXTRACT256Immediate(SDNode *N) {
4911 return getExtractVEXTRACTImmediate(N, 256);
4914 /// getInsertVINSERT128Immediate - Return the appropriate immediate
4915 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF128
4916 /// and VINSERTI128 instructions.
4917 unsigned X86::getInsertVINSERT128Immediate(SDNode *N) {
4918 return getInsertVINSERTImmediate(N, 128);
4921 /// getInsertVINSERT256Immediate - Return the appropriate immediate
4922 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF46x4
4923 /// and VINSERTI64x4 instructions.
4924 unsigned X86::getInsertVINSERT256Immediate(SDNode *N) {
4925 return getInsertVINSERTImmediate(N, 256);
4928 /// isZero - Returns true if Elt is a constant integer zero
4929 static bool isZero(SDValue V) {
4930 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
4931 return C && C->isNullValue();
4934 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
4936 bool X86::isZeroNode(SDValue Elt) {
4939 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Elt))
4940 return CFP->getValueAPF().isPosZero();
4944 /// ShouldXformToMOVHLPS - Return true if the node should be transformed to
4945 /// match movhlps. The lower half elements should come from upper half of
4946 /// V1 (and in order), and the upper half elements should come from the upper
4947 /// half of V2 (and in order).
4948 static bool ShouldXformToMOVHLPS(ArrayRef<int> Mask, MVT VT) {
4949 if (!VT.is128BitVector())
4951 if (VT.getVectorNumElements() != 4)
4953 for (unsigned i = 0, e = 2; i != e; ++i)
4954 if (!isUndefOrEqual(Mask[i], i+2))
4956 for (unsigned i = 2; i != 4; ++i)
4957 if (!isUndefOrEqual(Mask[i], i+4))
4962 /// isScalarLoadToVector - Returns true if the node is a scalar load that
4963 /// is promoted to a vector. It also returns the LoadSDNode by reference if
4965 static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = nullptr) {
4966 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR)
4968 N = N->getOperand(0).getNode();
4969 if (!ISD::isNON_EXTLoad(N))
4972 *LD = cast<LoadSDNode>(N);
4976 // Test whether the given value is a vector value which will be legalized
4978 static bool WillBeConstantPoolLoad(SDNode *N) {
4979 if (N->getOpcode() != ISD::BUILD_VECTOR)
4982 // Check for any non-constant elements.
4983 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
4984 switch (N->getOperand(i).getNode()->getOpcode()) {
4986 case ISD::ConstantFP:
4993 // Vectors of all-zeros and all-ones are materialized with special
4994 // instructions rather than being loaded.
4995 return !ISD::isBuildVectorAllZeros(N) &&
4996 !ISD::isBuildVectorAllOnes(N);
4999 /// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to
5000 /// match movlp{s|d}. The lower half elements should come from lower half of
5001 /// V1 (and in order), and the upper half elements should come from the upper
5002 /// half of V2 (and in order). And since V1 will become the source of the
5003 /// MOVLP, it must be either a vector load or a scalar load to vector.
5004 static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2,
5005 ArrayRef<int> Mask, MVT VT) {
5006 if (!VT.is128BitVector())
5009 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1))
5011 // Is V2 is a vector load, don't do this transformation. We will try to use
5012 // load folding shufps op.
5013 if (ISD::isNON_EXTLoad(V2) || WillBeConstantPoolLoad(V2))
5016 unsigned NumElems = VT.getVectorNumElements();
5018 if (NumElems != 2 && NumElems != 4)
5020 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
5021 if (!isUndefOrEqual(Mask[i], i))
5023 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i)
5024 if (!isUndefOrEqual(Mask[i], i+NumElems))
5029 /// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
5030 /// to an zero vector.
5031 /// FIXME: move to dag combiner / method on ShuffleVectorSDNode
5032 static bool isZeroShuffle(ShuffleVectorSDNode *N) {
5033 SDValue V1 = N->getOperand(0);
5034 SDValue V2 = N->getOperand(1);
5035 unsigned NumElems = N->getValueType(0).getVectorNumElements();
5036 for (unsigned i = 0; i != NumElems; ++i) {
5037 int Idx = N->getMaskElt(i);
5038 if (Idx >= (int)NumElems) {
5039 unsigned Opc = V2.getOpcode();
5040 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode()))
5042 if (Opc != ISD::BUILD_VECTOR ||
5043 !X86::isZeroNode(V2.getOperand(Idx-NumElems)))
5045 } else if (Idx >= 0) {
5046 unsigned Opc = V1.getOpcode();
5047 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode()))
5049 if (Opc != ISD::BUILD_VECTOR ||
5050 !X86::isZeroNode(V1.getOperand(Idx)))
5057 /// getZeroVector - Returns a vector of specified type with all zero elements.
5059 static SDValue getZeroVector(EVT VT, const X86Subtarget *Subtarget,
5060 SelectionDAG &DAG, SDLoc dl) {
5061 assert(VT.isVector() && "Expected a vector type");
5063 // Always build SSE zero vectors as <4 x i32> bitcasted
5064 // to their dest type. This ensures they get CSE'd.
5066 if (VT.is128BitVector()) { // SSE
5067 if (Subtarget->hasSSE2()) { // SSE2
5068 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
5069 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
5071 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
5072 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
5074 } else if (VT.is256BitVector()) { // AVX
5075 if (Subtarget->hasInt256()) { // AVX2
5076 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
5077 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5078 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
5080 // 256-bit logic and arithmetic instructions in AVX are all
5081 // floating-point, no support for integer ops. Emit fp zeroed vectors.
5082 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
5083 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5084 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops);
5086 } else if (VT.is512BitVector()) { // AVX-512
5087 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
5088 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst,
5089 Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5090 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i32, Ops);
5091 } else if (VT.getScalarType() == MVT::i1) {
5092 assert(VT.getVectorNumElements() <= 16 && "Unexpected vector type");
5093 SDValue Cst = DAG.getTargetConstant(0, MVT::i1);
5094 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
5095 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
5097 llvm_unreachable("Unexpected vector type");
5099 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
5102 /// getOnesVector - Returns a vector of specified type with all bits set.
5103 /// Always build ones vectors as <4 x i32> or <8 x i32>. For 256-bit types with
5104 /// no AVX2 supprt, use two <4 x i32> inserted in a <8 x i32> appropriately.
5105 /// Then bitcast to their original type, ensuring they get CSE'd.
5106 static SDValue getOnesVector(MVT VT, bool HasInt256, SelectionDAG &DAG,
5108 assert(VT.isVector() && "Expected a vector type");
5110 SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32);
5112 if (VT.is256BitVector()) {
5113 if (HasInt256) { // AVX2
5114 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5115 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
5117 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
5118 Vec = Concat128BitVectors(Vec, Vec, MVT::v8i32, 8, DAG, dl);
5120 } else if (VT.is128BitVector()) {
5121 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
5123 llvm_unreachable("Unexpected vector type");
5125 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
5128 /// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements
5129 /// that point to V2 points to its first element.
5130 static void NormalizeMask(SmallVectorImpl<int> &Mask, unsigned NumElems) {
5131 for (unsigned i = 0; i != NumElems; ++i) {
5132 if (Mask[i] > (int)NumElems) {
5138 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
5139 /// operation of specified width.
5140 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
5142 unsigned NumElems = VT.getVectorNumElements();
5143 SmallVector<int, 8> Mask;
5144 Mask.push_back(NumElems);
5145 for (unsigned i = 1; i != NumElems; ++i)
5147 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
5150 /// getUnpackl - Returns a vector_shuffle node for an unpackl operation.
5151 static SDValue getUnpackl(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
5153 unsigned NumElems = VT.getVectorNumElements();
5154 SmallVector<int, 8> Mask;
5155 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
5157 Mask.push_back(i + NumElems);
5159 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
5162 /// getUnpackh - Returns a vector_shuffle node for an unpackh operation.
5163 static SDValue getUnpackh(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
5165 unsigned NumElems = VT.getVectorNumElements();
5166 SmallVector<int, 8> Mask;
5167 for (unsigned i = 0, Half = NumElems/2; i != Half; ++i) {
5168 Mask.push_back(i + Half);
5169 Mask.push_back(i + NumElems + Half);
5171 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
5174 // PromoteSplati8i16 - All i16 and i8 vector types can't be used directly by
5175 // a generic shuffle instruction because the target has no such instructions.
5176 // Generate shuffles which repeat i16 and i8 several times until they can be
5177 // represented by v4f32 and then be manipulated by target suported shuffles.
5178 static SDValue PromoteSplati8i16(SDValue V, SelectionDAG &DAG, int &EltNo) {
5179 MVT VT = V.getSimpleValueType();
5180 int NumElems = VT.getVectorNumElements();
5183 while (NumElems > 4) {
5184 if (EltNo < NumElems/2) {
5185 V = getUnpackl(DAG, dl, VT, V, V);
5187 V = getUnpackh(DAG, dl, VT, V, V);
5188 EltNo -= NumElems/2;
5195 /// getLegalSplat - Generate a legal splat with supported x86 shuffles
5196 static SDValue getLegalSplat(SelectionDAG &DAG, SDValue V, int EltNo) {
5197 MVT VT = V.getSimpleValueType();
5200 if (VT.is128BitVector()) {
5201 V = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V);
5202 int SplatMask[4] = { EltNo, EltNo, EltNo, EltNo };
5203 V = DAG.getVectorShuffle(MVT::v4f32, dl, V, DAG.getUNDEF(MVT::v4f32),
5205 } else if (VT.is256BitVector()) {
5206 // To use VPERMILPS to splat scalars, the second half of indicies must
5207 // refer to the higher part, which is a duplication of the lower one,
5208 // because VPERMILPS can only handle in-lane permutations.
5209 int SplatMask[8] = { EltNo, EltNo, EltNo, EltNo,
5210 EltNo+4, EltNo+4, EltNo+4, EltNo+4 };
5212 V = DAG.getNode(ISD::BITCAST, dl, MVT::v8f32, V);
5213 V = DAG.getVectorShuffle(MVT::v8f32, dl, V, DAG.getUNDEF(MVT::v8f32),
5216 llvm_unreachable("Vector size not supported");
5218 return DAG.getNode(ISD::BITCAST, dl, VT, V);
5221 /// PromoteSplat - Splat is promoted to target supported vector shuffles.
5222 static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG) {
5223 MVT SrcVT = SV->getSimpleValueType(0);
5224 SDValue V1 = SV->getOperand(0);
5227 int EltNo = SV->getSplatIndex();
5228 int NumElems = SrcVT.getVectorNumElements();
5229 bool Is256BitVec = SrcVT.is256BitVector();
5231 assert(((SrcVT.is128BitVector() && NumElems > 4) || Is256BitVec) &&
5232 "Unknown how to promote splat for type");
5234 // Extract the 128-bit part containing the splat element and update
5235 // the splat element index when it refers to the higher register.
5237 V1 = Extract128BitVector(V1, EltNo, DAG, dl);
5238 if (EltNo >= NumElems/2)
5239 EltNo -= NumElems/2;
5242 // All i16 and i8 vector types can't be used directly by a generic shuffle
5243 // instruction because the target has no such instruction. Generate shuffles
5244 // which repeat i16 and i8 several times until they fit in i32, and then can
5245 // be manipulated by target suported shuffles.
5246 MVT EltVT = SrcVT.getVectorElementType();
5247 if (EltVT == MVT::i8 || EltVT == MVT::i16)
5248 V1 = PromoteSplati8i16(V1, DAG, EltNo);
5250 // Recreate the 256-bit vector and place the same 128-bit vector
5251 // into the low and high part. This is necessary because we want
5252 // to use VPERM* to shuffle the vectors
5254 V1 = DAG.getNode(ISD::CONCAT_VECTORS, dl, SrcVT, V1, V1);
5257 return getLegalSplat(DAG, V1, EltNo);
5260 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
5261 /// vector of zero or undef vector. This produces a shuffle where the low
5262 /// element of V2 is swizzled into the zero/undef vector, landing at element
5263 /// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
5264 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
5266 const X86Subtarget *Subtarget,
5267 SelectionDAG &DAG) {
5268 MVT VT = V2.getSimpleValueType();
5270 ? getZeroVector(VT, Subtarget, DAG, SDLoc(V2)) : DAG.getUNDEF(VT);
5271 unsigned NumElems = VT.getVectorNumElements();
5272 SmallVector<int, 16> MaskVec;
5273 for (unsigned i = 0; i != NumElems; ++i)
5274 // If this is the insertion idx, put the low elt of V2 here.
5275 MaskVec.push_back(i == Idx ? NumElems : i);
5276 return DAG.getVectorShuffle(VT, SDLoc(V2), V1, V2, &MaskVec[0]);
5279 /// getTargetShuffleMask - Calculates the shuffle mask corresponding to the
5280 /// target specific opcode. Returns true if the Mask could be calculated. Sets
5281 /// IsUnary to true if only uses one source. Note that this will set IsUnary for
5282 /// shuffles which use a single input multiple times, and in those cases it will
5283 /// adjust the mask to only have indices within that single input.
5284 static bool getTargetShuffleMask(SDNode *N, MVT VT,
5285 SmallVectorImpl<int> &Mask, bool &IsUnary) {
5286 unsigned NumElems = VT.getVectorNumElements();
5290 bool IsFakeUnary = false;
5291 switch(N->getOpcode()) {
5292 case X86ISD::BLENDI:
5293 ImmN = N->getOperand(N->getNumOperands()-1);
5294 DecodeBLENDMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5297 ImmN = N->getOperand(N->getNumOperands()-1);
5298 DecodeSHUFPMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5299 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5301 case X86ISD::UNPCKH:
5302 DecodeUNPCKHMask(VT, Mask);
5303 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5305 case X86ISD::UNPCKL:
5306 DecodeUNPCKLMask(VT, Mask);
5307 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5309 case X86ISD::MOVHLPS:
5310 DecodeMOVHLPSMask(NumElems, Mask);
5311 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5313 case X86ISD::MOVLHPS:
5314 DecodeMOVLHPSMask(NumElems, Mask);
5315 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5317 case X86ISD::PALIGNR:
5318 ImmN = N->getOperand(N->getNumOperands()-1);
5319 DecodePALIGNRMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5321 case X86ISD::PSHUFD:
5322 case X86ISD::VPERMILPI:
5323 ImmN = N->getOperand(N->getNumOperands()-1);
5324 DecodePSHUFMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5327 case X86ISD::PSHUFHW:
5328 ImmN = N->getOperand(N->getNumOperands()-1);
5329 DecodePSHUFHWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5332 case X86ISD::PSHUFLW:
5333 ImmN = N->getOperand(N->getNumOperands()-1);
5334 DecodePSHUFLWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5337 case X86ISD::PSHUFB: {
5339 SDValue MaskNode = N->getOperand(1);
5340 while (MaskNode->getOpcode() == ISD::BITCAST)
5341 MaskNode = MaskNode->getOperand(0);
5343 if (MaskNode->getOpcode() == ISD::BUILD_VECTOR) {
5344 // If we have a build-vector, then things are easy.
5345 EVT VT = MaskNode.getValueType();
5346 assert(VT.isVector() &&
5347 "Can't produce a non-vector with a build_vector!");
5348 if (!VT.isInteger())
5351 int NumBytesPerElement = VT.getVectorElementType().getSizeInBits() / 8;
5353 SmallVector<uint64_t, 32> RawMask;
5354 for (int i = 0, e = MaskNode->getNumOperands(); i < e; ++i) {
5355 SDValue Op = MaskNode->getOperand(i);
5356 if (Op->getOpcode() == ISD::UNDEF) {
5357 RawMask.push_back((uint64_t)SM_SentinelUndef);
5360 auto *CN = dyn_cast<ConstantSDNode>(Op.getNode());
5363 APInt MaskElement = CN->getAPIntValue();
5365 // We now have to decode the element which could be any integer size and
5366 // extract each byte of it.
5367 for (int j = 0; j < NumBytesPerElement; ++j) {
5368 // Note that this is x86 and so always little endian: the low byte is
5369 // the first byte of the mask.
5370 RawMask.push_back(MaskElement.getLoBits(8).getZExtValue());
5371 MaskElement = MaskElement.lshr(8);
5374 DecodePSHUFBMask(RawMask, Mask);
5378 auto *MaskLoad = dyn_cast<LoadSDNode>(MaskNode);
5382 SDValue Ptr = MaskLoad->getBasePtr();
5383 if (Ptr->getOpcode() == X86ISD::Wrapper)
5384 Ptr = Ptr->getOperand(0);
5386 auto *MaskCP = dyn_cast<ConstantPoolSDNode>(Ptr);
5387 if (!MaskCP || MaskCP->isMachineConstantPoolEntry())
5390 if (auto *C = dyn_cast<Constant>(MaskCP->getConstVal())) {
5391 // FIXME: Support AVX-512 here.
5392 Type *Ty = C->getType();
5393 if (!Ty->isVectorTy() || (Ty->getVectorNumElements() != 16 &&
5394 Ty->getVectorNumElements() != 32))
5397 DecodePSHUFBMask(C, Mask);
5403 case X86ISD::VPERMI:
5404 ImmN = N->getOperand(N->getNumOperands()-1);
5405 DecodeVPERMMask(cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5409 case X86ISD::MOVSD: {
5410 // The index 0 always comes from the first element of the second source,
5411 // this is why MOVSS and MOVSD are used in the first place. The other
5412 // elements come from the other positions of the first source vector
5413 Mask.push_back(NumElems);
5414 for (unsigned i = 1; i != NumElems; ++i) {
5419 case X86ISD::VPERM2X128:
5420 ImmN = N->getOperand(N->getNumOperands()-1);
5421 DecodeVPERM2X128Mask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5422 if (Mask.empty()) return false;
5424 case X86ISD::MOVSLDUP:
5425 DecodeMOVSLDUPMask(VT, Mask);
5427 case X86ISD::MOVSHDUP:
5428 DecodeMOVSHDUPMask(VT, Mask);
5430 case X86ISD::MOVDDUP:
5431 case X86ISD::MOVLHPD:
5432 case X86ISD::MOVLPD:
5433 case X86ISD::MOVLPS:
5434 // Not yet implemented
5436 default: llvm_unreachable("unknown target shuffle node");
5439 // If we have a fake unary shuffle, the shuffle mask is spread across two
5440 // inputs that are actually the same node. Re-map the mask to always point
5441 // into the first input.
5444 if (M >= (int)Mask.size())
5450 /// getShuffleScalarElt - Returns the scalar element that will make up the ith
5451 /// element of the result of the vector shuffle.
5452 static SDValue getShuffleScalarElt(SDNode *N, unsigned Index, SelectionDAG &DAG,
5455 return SDValue(); // Limit search depth.
5457 SDValue V = SDValue(N, 0);
5458 EVT VT = V.getValueType();
5459 unsigned Opcode = V.getOpcode();
5461 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars.
5462 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) {
5463 int Elt = SV->getMaskElt(Index);
5466 return DAG.getUNDEF(VT.getVectorElementType());
5468 unsigned NumElems = VT.getVectorNumElements();
5469 SDValue NewV = (Elt < (int)NumElems) ? SV->getOperand(0)
5470 : SV->getOperand(1);
5471 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG, Depth+1);
5474 // Recurse into target specific vector shuffles to find scalars.
5475 if (isTargetShuffle(Opcode)) {
5476 MVT ShufVT = V.getSimpleValueType();
5477 unsigned NumElems = ShufVT.getVectorNumElements();
5478 SmallVector<int, 16> ShuffleMask;
5481 if (!getTargetShuffleMask(N, ShufVT, ShuffleMask, IsUnary))
5484 int Elt = ShuffleMask[Index];
5486 return DAG.getUNDEF(ShufVT.getVectorElementType());
5488 SDValue NewV = (Elt < (int)NumElems) ? N->getOperand(0)
5490 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG,
5494 // Actual nodes that may contain scalar elements
5495 if (Opcode == ISD::BITCAST) {
5496 V = V.getOperand(0);
5497 EVT SrcVT = V.getValueType();
5498 unsigned NumElems = VT.getVectorNumElements();
5500 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems)
5504 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR)
5505 return (Index == 0) ? V.getOperand(0)
5506 : DAG.getUNDEF(VT.getVectorElementType());
5508 if (V.getOpcode() == ISD::BUILD_VECTOR)
5509 return V.getOperand(Index);
5514 /// getNumOfConsecutiveZeros - Return the number of elements of a vector
5515 /// shuffle operation which come from a consecutively from a zero. The
5516 /// search can start in two different directions, from left or right.
5517 /// We count undefs as zeros until PreferredNum is reached.
5518 static unsigned getNumOfConsecutiveZeros(ShuffleVectorSDNode *SVOp,
5519 unsigned NumElems, bool ZerosFromLeft,
5521 unsigned PreferredNum = -1U) {
5522 unsigned NumZeros = 0;
5523 for (unsigned i = 0; i != NumElems; ++i) {
5524 unsigned Index = ZerosFromLeft ? i : NumElems - i - 1;
5525 SDValue Elt = getShuffleScalarElt(SVOp, Index, DAG, 0);
5529 if (X86::isZeroNode(Elt))
5531 else if (Elt.getOpcode() == ISD::UNDEF) // Undef as zero up to PreferredNum.
5532 NumZeros = std::min(NumZeros + 1, PreferredNum);
5540 /// isShuffleMaskConsecutive - Check if the shuffle mask indicies [MaskI, MaskE)
5541 /// correspond consecutively to elements from one of the vector operands,
5542 /// starting from its index OpIdx. Also tell OpNum which source vector operand.
5544 bool isShuffleMaskConsecutive(ShuffleVectorSDNode *SVOp,
5545 unsigned MaskI, unsigned MaskE, unsigned OpIdx,
5546 unsigned NumElems, unsigned &OpNum) {
5547 bool SeenV1 = false;
5548 bool SeenV2 = false;
5550 for (unsigned i = MaskI; i != MaskE; ++i, ++OpIdx) {
5551 int Idx = SVOp->getMaskElt(i);
5552 // Ignore undef indicies
5556 if (Idx < (int)NumElems)
5561 // Only accept consecutive elements from the same vector
5562 if ((Idx % NumElems != OpIdx) || (SeenV1 && SeenV2))
5566 OpNum = SeenV1 ? 0 : 1;
5570 /// isVectorShiftRight - Returns true if the shuffle can be implemented as a
5571 /// logical left shift of a vector.
5572 static bool isVectorShiftRight(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5573 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5575 SVOp->getSimpleValueType(0).getVectorNumElements();
5576 unsigned NumZeros = getNumOfConsecutiveZeros(
5577 SVOp, NumElems, false /* check zeros from right */, DAG,
5578 SVOp->getMaskElt(0));
5584 // Considering the elements in the mask that are not consecutive zeros,
5585 // check if they consecutively come from only one of the source vectors.
5587 // V1 = {X, A, B, C} 0
5589 // vector_shuffle V1, V2 <1, 2, 3, X>
5591 if (!isShuffleMaskConsecutive(SVOp,
5592 0, // Mask Start Index
5593 NumElems-NumZeros, // Mask End Index(exclusive)
5594 NumZeros, // Where to start looking in the src vector
5595 NumElems, // Number of elements in vector
5596 OpSrc)) // Which source operand ?
5601 ShVal = SVOp->getOperand(OpSrc);
5605 /// isVectorShiftLeft - Returns true if the shuffle can be implemented as a
5606 /// logical left shift of a vector.
5607 static bool isVectorShiftLeft(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5608 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5610 SVOp->getSimpleValueType(0).getVectorNumElements();
5611 unsigned NumZeros = getNumOfConsecutiveZeros(
5612 SVOp, NumElems, true /* check zeros from left */, DAG,
5613 NumElems - SVOp->getMaskElt(NumElems - 1) - 1);
5619 // Considering the elements in the mask that are not consecutive zeros,
5620 // check if they consecutively come from only one of the source vectors.
5622 // 0 { A, B, X, X } = V2
5624 // vector_shuffle V1, V2 <X, X, 4, 5>
5626 if (!isShuffleMaskConsecutive(SVOp,
5627 NumZeros, // Mask Start Index
5628 NumElems, // Mask End Index(exclusive)
5629 0, // Where to start looking in the src vector
5630 NumElems, // Number of elements in vector
5631 OpSrc)) // Which source operand ?
5636 ShVal = SVOp->getOperand(OpSrc);
5640 /// isVectorShift - Returns true if the shuffle can be implemented as a
5641 /// logical left or right shift of a vector.
5642 static bool isVectorShift(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5643 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5644 // Although the logic below support any bitwidth size, there are no
5645 // shift instructions which handle more than 128-bit vectors.
5646 if (!SVOp->getSimpleValueType(0).is128BitVector())
5649 if (isVectorShiftLeft(SVOp, DAG, isLeft, ShVal, ShAmt) ||
5650 isVectorShiftRight(SVOp, DAG, isLeft, ShVal, ShAmt))
5656 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
5658 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
5659 unsigned NumNonZero, unsigned NumZero,
5661 const X86Subtarget* Subtarget,
5662 const TargetLowering &TLI) {
5669 for (unsigned i = 0; i < 16; ++i) {
5670 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
5671 if (ThisIsNonZero && First) {
5673 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
5675 V = DAG.getUNDEF(MVT::v8i16);
5680 SDValue ThisElt, LastElt;
5681 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
5682 if (LastIsNonZero) {
5683 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
5684 MVT::i16, Op.getOperand(i-1));
5686 if (ThisIsNonZero) {
5687 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
5688 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
5689 ThisElt, DAG.getConstant(8, MVT::i8));
5691 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
5695 if (ThisElt.getNode())
5696 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
5697 DAG.getIntPtrConstant(i/2));
5701 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V);
5704 /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
5706 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
5707 unsigned NumNonZero, unsigned NumZero,
5709 const X86Subtarget* Subtarget,
5710 const TargetLowering &TLI) {
5717 for (unsigned i = 0; i < 8; ++i) {
5718 bool isNonZero = (NonZeros & (1 << i)) != 0;
5722 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
5724 V = DAG.getUNDEF(MVT::v8i16);
5727 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
5728 MVT::v8i16, V, Op.getOperand(i),
5729 DAG.getIntPtrConstant(i));
5736 /// LowerBuildVectorv4x32 - Custom lower build_vector of v4i32 or v4f32.
5737 static SDValue LowerBuildVectorv4x32(SDValue Op, unsigned NumElems,
5738 unsigned NonZeros, unsigned NumNonZero,
5739 unsigned NumZero, SelectionDAG &DAG,
5740 const X86Subtarget *Subtarget,
5741 const TargetLowering &TLI) {
5742 // We know there's at least one non-zero element
5743 unsigned FirstNonZeroIdx = 0;
5744 SDValue FirstNonZero = Op->getOperand(FirstNonZeroIdx);
5745 while (FirstNonZero.getOpcode() == ISD::UNDEF ||
5746 X86::isZeroNode(FirstNonZero)) {
5748 FirstNonZero = Op->getOperand(FirstNonZeroIdx);
5751 if (FirstNonZero.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
5752 !isa<ConstantSDNode>(FirstNonZero.getOperand(1)))
5755 SDValue V = FirstNonZero.getOperand(0);
5756 MVT VVT = V.getSimpleValueType();
5757 if (!Subtarget->hasSSE41() || (VVT != MVT::v4f32 && VVT != MVT::v4i32))
5760 unsigned FirstNonZeroDst =
5761 cast<ConstantSDNode>(FirstNonZero.getOperand(1))->getZExtValue();
5762 unsigned CorrectIdx = FirstNonZeroDst == FirstNonZeroIdx;
5763 unsigned IncorrectIdx = CorrectIdx ? -1U : FirstNonZeroIdx;
5764 unsigned IncorrectDst = CorrectIdx ? -1U : FirstNonZeroDst;
5766 for (unsigned Idx = FirstNonZeroIdx + 1; Idx < NumElems; ++Idx) {
5767 SDValue Elem = Op.getOperand(Idx);
5768 if (Elem.getOpcode() == ISD::UNDEF || X86::isZeroNode(Elem))
5771 // TODO: What else can be here? Deal with it.
5772 if (Elem.getOpcode() != ISD::EXTRACT_VECTOR_ELT)
5775 // TODO: Some optimizations are still possible here
5776 // ex: Getting one element from a vector, and the rest from another.
5777 if (Elem.getOperand(0) != V)
5780 unsigned Dst = cast<ConstantSDNode>(Elem.getOperand(1))->getZExtValue();
5783 else if (IncorrectIdx == -1U) {
5787 // There was already one element with an incorrect index.
5788 // We can't optimize this case to an insertps.
5792 if (NumNonZero == CorrectIdx || NumNonZero == CorrectIdx + 1) {
5794 EVT VT = Op.getSimpleValueType();
5795 unsigned ElementMoveMask = 0;
5796 if (IncorrectIdx == -1U)
5797 ElementMoveMask = FirstNonZeroIdx << 6 | FirstNonZeroIdx << 4;
5799 ElementMoveMask = IncorrectDst << 6 | IncorrectIdx << 4;
5801 SDValue InsertpsMask =
5802 DAG.getIntPtrConstant(ElementMoveMask | (~NonZeros & 0xf));
5803 return DAG.getNode(X86ISD::INSERTPS, dl, VT, V, V, InsertpsMask);
5809 /// getVShift - Return a vector logical shift node.
5811 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
5812 unsigned NumBits, SelectionDAG &DAG,
5813 const TargetLowering &TLI, SDLoc dl) {
5814 assert(VT.is128BitVector() && "Unknown type for VShift");
5815 EVT ShVT = MVT::v2i64;
5816 unsigned Opc = isLeft ? X86ISD::VSHLDQ : X86ISD::VSRLDQ;
5817 SrcOp = DAG.getNode(ISD::BITCAST, dl, ShVT, SrcOp);
5818 return DAG.getNode(ISD::BITCAST, dl, VT,
5819 DAG.getNode(Opc, dl, ShVT, SrcOp,
5820 DAG.getConstant(NumBits,
5821 TLI.getScalarShiftAmountTy(SrcOp.getValueType()))));
5825 LowerAsSplatVectorLoad(SDValue SrcOp, MVT VT, SDLoc dl, SelectionDAG &DAG) {
5827 // Check if the scalar load can be widened into a vector load. And if
5828 // the address is "base + cst" see if the cst can be "absorbed" into
5829 // the shuffle mask.
5830 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) {
5831 SDValue Ptr = LD->getBasePtr();
5832 if (!ISD::isNormalLoad(LD) || LD->isVolatile())
5834 EVT PVT = LD->getValueType(0);
5835 if (PVT != MVT::i32 && PVT != MVT::f32)
5840 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) {
5841 FI = FINode->getIndex();
5843 } else if (DAG.isBaseWithConstantOffset(Ptr) &&
5844 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
5845 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
5846 Offset = Ptr.getConstantOperandVal(1);
5847 Ptr = Ptr.getOperand(0);
5852 // FIXME: 256-bit vector instructions don't require a strict alignment,
5853 // improve this code to support it better.
5854 unsigned RequiredAlign = VT.getSizeInBits()/8;
5855 SDValue Chain = LD->getChain();
5856 // Make sure the stack object alignment is at least 16 or 32.
5857 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
5858 if (DAG.InferPtrAlignment(Ptr) < RequiredAlign) {
5859 if (MFI->isFixedObjectIndex(FI)) {
5860 // Can't change the alignment. FIXME: It's possible to compute
5861 // the exact stack offset and reference FI + adjust offset instead.
5862 // If someone *really* cares about this. That's the way to implement it.
5865 MFI->setObjectAlignment(FI, RequiredAlign);
5869 // (Offset % 16 or 32) must be multiple of 4. Then address is then
5870 // Ptr + (Offset & ~15).
5873 if ((Offset % RequiredAlign) & 3)
5875 int64_t StartOffset = Offset & ~(RequiredAlign-1);
5877 Ptr = DAG.getNode(ISD::ADD, SDLoc(Ptr), Ptr.getValueType(),
5878 Ptr,DAG.getConstant(StartOffset, Ptr.getValueType()));
5880 int EltNo = (Offset - StartOffset) >> 2;
5881 unsigned NumElems = VT.getVectorNumElements();
5883 EVT NVT = EVT::getVectorVT(*DAG.getContext(), PVT, NumElems);
5884 SDValue V1 = DAG.getLoad(NVT, dl, Chain, Ptr,
5885 LD->getPointerInfo().getWithOffset(StartOffset),
5886 false, false, false, 0);
5888 SmallVector<int, 8> Mask;
5889 for (unsigned i = 0; i != NumElems; ++i)
5890 Mask.push_back(EltNo);
5892 return DAG.getVectorShuffle(NVT, dl, V1, DAG.getUNDEF(NVT), &Mask[0]);
5898 /// EltsFromConsecutiveLoads - Given the initializing elements 'Elts' of a
5899 /// vector of type 'VT', see if the elements can be replaced by a single large
5900 /// load which has the same value as a build_vector whose operands are 'elts'.
5902 /// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a
5904 /// FIXME: we'd also like to handle the case where the last elements are zero
5905 /// rather than undef via VZEXT_LOAD, but we do not detect that case today.
5906 /// There's even a handy isZeroNode for that purpose.
5907 static SDValue EltsFromConsecutiveLoads(EVT VT, SmallVectorImpl<SDValue> &Elts,
5908 SDLoc &DL, SelectionDAG &DAG,
5909 bool isAfterLegalize) {
5910 EVT EltVT = VT.getVectorElementType();
5911 unsigned NumElems = Elts.size();
5913 LoadSDNode *LDBase = nullptr;
5914 unsigned LastLoadedElt = -1U;
5916 // For each element in the initializer, see if we've found a load or an undef.
5917 // If we don't find an initial load element, or later load elements are
5918 // non-consecutive, bail out.
5919 for (unsigned i = 0; i < NumElems; ++i) {
5920 SDValue Elt = Elts[i];
5922 if (!Elt.getNode() ||
5923 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
5926 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
5928 LDBase = cast<LoadSDNode>(Elt.getNode());
5932 if (Elt.getOpcode() == ISD::UNDEF)
5935 LoadSDNode *LD = cast<LoadSDNode>(Elt);
5936 if (!DAG.isConsecutiveLoad(LD, LDBase, EltVT.getSizeInBits()/8, i))
5941 // If we have found an entire vector of loads and undefs, then return a large
5942 // load of the entire vector width starting at the base pointer. If we found
5943 // consecutive loads for the low half, generate a vzext_load node.
5944 if (LastLoadedElt == NumElems - 1) {
5946 if (isAfterLegalize &&
5947 !DAG.getTargetLoweringInfo().isOperationLegal(ISD::LOAD, VT))
5950 SDValue NewLd = SDValue();
5952 if (DAG.InferPtrAlignment(LDBase->getBasePtr()) >= 16)
5953 NewLd = DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
5954 LDBase->getPointerInfo(),
5955 LDBase->isVolatile(), LDBase->isNonTemporal(),
5956 LDBase->isInvariant(), 0);
5957 NewLd = DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
5958 LDBase->getPointerInfo(),
5959 LDBase->isVolatile(), LDBase->isNonTemporal(),
5960 LDBase->isInvariant(), LDBase->getAlignment());
5962 if (LDBase->hasAnyUseOfValue(1)) {
5963 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
5965 SDValue(NewLd.getNode(), 1));
5966 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
5967 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
5968 SDValue(NewLd.getNode(), 1));
5973 if (NumElems == 4 && LastLoadedElt == 1 &&
5974 DAG.getTargetLoweringInfo().isTypeLegal(MVT::v2i64)) {
5975 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
5976 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() };
5978 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys, Ops, MVT::i64,
5979 LDBase->getPointerInfo(),
5980 LDBase->getAlignment(),
5981 false/*isVolatile*/, true/*ReadMem*/,
5984 // Make sure the newly-created LOAD is in the same position as LDBase in
5985 // terms of dependency. We create a TokenFactor for LDBase and ResNode, and
5986 // update uses of LDBase's output chain to use the TokenFactor.
5987 if (LDBase->hasAnyUseOfValue(1)) {
5988 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
5989 SDValue(LDBase, 1), SDValue(ResNode.getNode(), 1));
5990 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
5991 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
5992 SDValue(ResNode.getNode(), 1));
5995 return DAG.getNode(ISD::BITCAST, DL, VT, ResNode);
6000 /// LowerVectorBroadcast - Attempt to use the vbroadcast instruction
6001 /// to generate a splat value for the following cases:
6002 /// 1. A splat BUILD_VECTOR which uses a single scalar load, or a constant.
6003 /// 2. A splat shuffle which uses a scalar_to_vector node which comes from
6004 /// a scalar load, or a constant.
6005 /// The VBROADCAST node is returned when a pattern is found,
6006 /// or SDValue() otherwise.
6007 static SDValue LowerVectorBroadcast(SDValue Op, const X86Subtarget* Subtarget,
6008 SelectionDAG &DAG) {
6009 // VBROADCAST requires AVX.
6010 // TODO: Splats could be generated for non-AVX CPUs using SSE
6011 // instructions, but there's less potential gain for only 128-bit vectors.
6012 if (!Subtarget->hasAVX())
6015 MVT VT = Op.getSimpleValueType();
6018 assert((VT.is128BitVector() || VT.is256BitVector() || VT.is512BitVector()) &&
6019 "Unsupported vector type for broadcast.");
6024 switch (Op.getOpcode()) {
6026 // Unknown pattern found.
6029 case ISD::BUILD_VECTOR: {
6030 auto *BVOp = cast<BuildVectorSDNode>(Op.getNode());
6031 BitVector UndefElements;
6032 SDValue Splat = BVOp->getSplatValue(&UndefElements);
6034 // We need a splat of a single value to use broadcast, and it doesn't
6035 // make any sense if the value is only in one element of the vector.
6036 if (!Splat || (VT.getVectorNumElements() - UndefElements.count()) <= 1)
6040 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
6041 Ld.getOpcode() == ISD::ConstantFP);
6043 // Make sure that all of the users of a non-constant load are from the
6044 // BUILD_VECTOR node.
6045 if (!ConstSplatVal && !BVOp->isOnlyUserOf(Ld.getNode()))
6050 case ISD::VECTOR_SHUFFLE: {
6051 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6053 // Shuffles must have a splat mask where the first element is
6055 if ((!SVOp->isSplat()) || SVOp->getMaskElt(0) != 0)
6058 SDValue Sc = Op.getOperand(0);
6059 if (Sc.getOpcode() != ISD::SCALAR_TO_VECTOR &&
6060 Sc.getOpcode() != ISD::BUILD_VECTOR) {
6062 if (!Subtarget->hasInt256())
6065 // Use the register form of the broadcast instruction available on AVX2.
6066 if (VT.getSizeInBits() >= 256)
6067 Sc = Extract128BitVector(Sc, 0, DAG, dl);
6068 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Sc);
6071 Ld = Sc.getOperand(0);
6072 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
6073 Ld.getOpcode() == ISD::ConstantFP);
6075 // The scalar_to_vector node and the suspected
6076 // load node must have exactly one user.
6077 // Constants may have multiple users.
6079 // AVX-512 has register version of the broadcast
6080 bool hasRegVer = Subtarget->hasAVX512() && VT.is512BitVector() &&
6081 Ld.getValueType().getSizeInBits() >= 32;
6082 if (!ConstSplatVal && ((!Sc.hasOneUse() || !Ld.hasOneUse()) &&
6089 unsigned ScalarSize = Ld.getValueType().getSizeInBits();
6090 bool IsGE256 = (VT.getSizeInBits() >= 256);
6092 // When optimizing for size, generate up to 5 extra bytes for a broadcast
6093 // instruction to save 8 or more bytes of constant pool data.
6094 // TODO: If multiple splats are generated to load the same constant,
6095 // it may be detrimental to overall size. There needs to be a way to detect
6096 // that condition to know if this is truly a size win.
6097 const Function *F = DAG.getMachineFunction().getFunction();
6098 bool OptForSize = F->getAttributes().
6099 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
6101 // Handle broadcasting a single constant scalar from the constant pool
6103 // On Sandybridge (no AVX2), it is still better to load a constant vector
6104 // from the constant pool and not to broadcast it from a scalar.
6105 // But override that restriction when optimizing for size.
6106 // TODO: Check if splatting is recommended for other AVX-capable CPUs.
6107 if (ConstSplatVal && (Subtarget->hasAVX2() || OptForSize)) {
6108 EVT CVT = Ld.getValueType();
6109 assert(!CVT.isVector() && "Must not broadcast a vector type");
6111 // Splat f32, i32, v4f64, v4i64 in all cases with AVX2.
6112 // For size optimization, also splat v2f64 and v2i64, and for size opt
6113 // with AVX2, also splat i8 and i16.
6114 // With pattern matching, the VBROADCAST node may become a VMOVDDUP.
6115 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64) ||
6116 (OptForSize && (ScalarSize == 64 || Subtarget->hasAVX2()))) {
6117 const Constant *C = nullptr;
6118 if (ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Ld))
6119 C = CI->getConstantIntValue();
6120 else if (ConstantFPSDNode *CF = dyn_cast<ConstantFPSDNode>(Ld))
6121 C = CF->getConstantFPValue();
6123 assert(C && "Invalid constant type");
6125 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6126 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
6127 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
6128 Ld = DAG.getLoad(CVT, dl, DAG.getEntryNode(), CP,
6129 MachinePointerInfo::getConstantPool(),
6130 false, false, false, Alignment);
6132 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6136 bool IsLoad = ISD::isNormalLoad(Ld.getNode());
6138 // Handle AVX2 in-register broadcasts.
6139 if (!IsLoad && Subtarget->hasInt256() &&
6140 (ScalarSize == 32 || (IsGE256 && ScalarSize == 64)))
6141 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6143 // The scalar source must be a normal load.
6147 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64))
6148 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6150 // The integer check is needed for the 64-bit into 128-bit so it doesn't match
6151 // double since there is no vbroadcastsd xmm
6152 if (Subtarget->hasInt256() && Ld.getValueType().isInteger()) {
6153 if (ScalarSize == 8 || ScalarSize == 16 || ScalarSize == 64)
6154 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6157 // Unsupported broadcast.
6161 /// \brief For an EXTRACT_VECTOR_ELT with a constant index return the real
6162 /// underlying vector and index.
6164 /// Modifies \p ExtractedFromVec to the real vector and returns the real
6166 static int getUnderlyingExtractedFromVec(SDValue &ExtractedFromVec,
6168 int Idx = cast<ConstantSDNode>(ExtIdx)->getZExtValue();
6169 if (!isa<ShuffleVectorSDNode>(ExtractedFromVec))
6172 // For 256-bit vectors, LowerEXTRACT_VECTOR_ELT_SSE4 may have already
6174 // (extract_vector_elt (v8f32 %vreg1), Constant<6>)
6176 // (extract_vector_elt (vector_shuffle<2,u,u,u>
6177 // (extract_subvector (v8f32 %vreg0), Constant<4>),
6180 // In this case the vector is the extract_subvector expression and the index
6181 // is 2, as specified by the shuffle.
6182 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(ExtractedFromVec);
6183 SDValue ShuffleVec = SVOp->getOperand(0);
6184 MVT ShuffleVecVT = ShuffleVec.getSimpleValueType();
6185 assert(ShuffleVecVT.getVectorElementType() ==
6186 ExtractedFromVec.getSimpleValueType().getVectorElementType());
6188 int ShuffleIdx = SVOp->getMaskElt(Idx);
6189 if (isUndefOrInRange(ShuffleIdx, 0, ShuffleVecVT.getVectorNumElements())) {
6190 ExtractedFromVec = ShuffleVec;
6196 static SDValue buildFromShuffleMostly(SDValue Op, SelectionDAG &DAG) {
6197 MVT VT = Op.getSimpleValueType();
6199 // Skip if insert_vec_elt is not supported.
6200 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6201 if (!TLI.isOperationLegalOrCustom(ISD::INSERT_VECTOR_ELT, VT))
6205 unsigned NumElems = Op.getNumOperands();
6209 SmallVector<unsigned, 4> InsertIndices;
6210 SmallVector<int, 8> Mask(NumElems, -1);
6212 for (unsigned i = 0; i != NumElems; ++i) {
6213 unsigned Opc = Op.getOperand(i).getOpcode();
6215 if (Opc == ISD::UNDEF)
6218 if (Opc != ISD::EXTRACT_VECTOR_ELT) {
6219 // Quit if more than 1 elements need inserting.
6220 if (InsertIndices.size() > 1)
6223 InsertIndices.push_back(i);
6227 SDValue ExtractedFromVec = Op.getOperand(i).getOperand(0);
6228 SDValue ExtIdx = Op.getOperand(i).getOperand(1);
6229 // Quit if non-constant index.
6230 if (!isa<ConstantSDNode>(ExtIdx))
6232 int Idx = getUnderlyingExtractedFromVec(ExtractedFromVec, ExtIdx);
6234 // Quit if extracted from vector of different type.
6235 if (ExtractedFromVec.getValueType() != VT)
6238 if (!VecIn1.getNode())
6239 VecIn1 = ExtractedFromVec;
6240 else if (VecIn1 != ExtractedFromVec) {
6241 if (!VecIn2.getNode())
6242 VecIn2 = ExtractedFromVec;
6243 else if (VecIn2 != ExtractedFromVec)
6244 // Quit if more than 2 vectors to shuffle
6248 if (ExtractedFromVec == VecIn1)
6250 else if (ExtractedFromVec == VecIn2)
6251 Mask[i] = Idx + NumElems;
6254 if (!VecIn1.getNode())
6257 VecIn2 = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT);
6258 SDValue NV = DAG.getVectorShuffle(VT, DL, VecIn1, VecIn2, &Mask[0]);
6259 for (unsigned i = 0, e = InsertIndices.size(); i != e; ++i) {
6260 unsigned Idx = InsertIndices[i];
6261 NV = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VT, NV, Op.getOperand(Idx),
6262 DAG.getIntPtrConstant(Idx));
6268 // Lower BUILD_VECTOR operation for v8i1 and v16i1 types.
6270 X86TargetLowering::LowerBUILD_VECTORvXi1(SDValue Op, SelectionDAG &DAG) const {
6272 MVT VT = Op.getSimpleValueType();
6273 assert((VT.getVectorElementType() == MVT::i1) && (VT.getSizeInBits() <= 16) &&
6274 "Unexpected type in LowerBUILD_VECTORvXi1!");
6277 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
6278 SDValue Cst = DAG.getTargetConstant(0, MVT::i1);
6279 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
6280 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
6283 if (ISD::isBuildVectorAllOnes(Op.getNode())) {
6284 SDValue Cst = DAG.getTargetConstant(1, MVT::i1);
6285 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
6286 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
6289 bool AllContants = true;
6290 uint64_t Immediate = 0;
6291 int NonConstIdx = -1;
6292 bool IsSplat = true;
6293 unsigned NumNonConsts = 0;
6294 unsigned NumConsts = 0;
6295 for (unsigned idx = 0, e = Op.getNumOperands(); idx < e; ++idx) {
6296 SDValue In = Op.getOperand(idx);
6297 if (In.getOpcode() == ISD::UNDEF)
6299 if (!isa<ConstantSDNode>(In)) {
6300 AllContants = false;
6306 if (cast<ConstantSDNode>(In)->getZExtValue())
6307 Immediate |= (1ULL << idx);
6309 if (In != Op.getOperand(0))
6314 SDValue FullMask = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1,
6315 DAG.getConstant(Immediate, MVT::i16));
6316 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, FullMask,
6317 DAG.getIntPtrConstant(0));
6320 if (NumNonConsts == 1 && NonConstIdx != 0) {
6323 SDValue VecAsImm = DAG.getConstant(Immediate,
6324 MVT::getIntegerVT(VT.getSizeInBits()));
6325 DstVec = DAG.getNode(ISD::BITCAST, dl, VT, VecAsImm);
6328 DstVec = DAG.getUNDEF(VT);
6329 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, DstVec,
6330 Op.getOperand(NonConstIdx),
6331 DAG.getIntPtrConstant(NonConstIdx));
6333 if (!IsSplat && (NonConstIdx != 0))
6334 llvm_unreachable("Unsupported BUILD_VECTOR operation");
6335 MVT SelectVT = (VT == MVT::v16i1)? MVT::i16 : MVT::i8;
6338 Select = DAG.getNode(ISD::SELECT, dl, SelectVT, Op.getOperand(0),
6339 DAG.getConstant(-1, SelectVT),
6340 DAG.getConstant(0, SelectVT));
6342 Select = DAG.getNode(ISD::SELECT, dl, SelectVT, Op.getOperand(0),
6343 DAG.getConstant((Immediate | 1), SelectVT),
6344 DAG.getConstant(Immediate, SelectVT));
6345 return DAG.getNode(ISD::BITCAST, dl, VT, Select);
6348 /// \brief Return true if \p N implements a horizontal binop and return the
6349 /// operands for the horizontal binop into V0 and V1.
6351 /// This is a helper function of PerformBUILD_VECTORCombine.
6352 /// This function checks that the build_vector \p N in input implements a
6353 /// horizontal operation. Parameter \p Opcode defines the kind of horizontal
6354 /// operation to match.
6355 /// For example, if \p Opcode is equal to ISD::ADD, then this function
6356 /// checks if \p N implements a horizontal arithmetic add; if instead \p Opcode
6357 /// is equal to ISD::SUB, then this function checks if this is a horizontal
6360 /// This function only analyzes elements of \p N whose indices are
6361 /// in range [BaseIdx, LastIdx).
6362 static bool isHorizontalBinOp(const BuildVectorSDNode *N, unsigned Opcode,
6364 unsigned BaseIdx, unsigned LastIdx,
6365 SDValue &V0, SDValue &V1) {
6366 EVT VT = N->getValueType(0);
6368 assert(BaseIdx * 2 <= LastIdx && "Invalid Indices in input!");
6369 assert(VT.isVector() && VT.getVectorNumElements() >= LastIdx &&
6370 "Invalid Vector in input!");
6372 bool IsCommutable = (Opcode == ISD::ADD || Opcode == ISD::FADD);
6373 bool CanFold = true;
6374 unsigned ExpectedVExtractIdx = BaseIdx;
6375 unsigned NumElts = LastIdx - BaseIdx;
6376 V0 = DAG.getUNDEF(VT);
6377 V1 = DAG.getUNDEF(VT);
6379 // Check if N implements a horizontal binop.
6380 for (unsigned i = 0, e = NumElts; i != e && CanFold; ++i) {
6381 SDValue Op = N->getOperand(i + BaseIdx);
6384 if (Op->getOpcode() == ISD::UNDEF) {
6385 // Update the expected vector extract index.
6386 if (i * 2 == NumElts)
6387 ExpectedVExtractIdx = BaseIdx;
6388 ExpectedVExtractIdx += 2;
6392 CanFold = Op->getOpcode() == Opcode && Op->hasOneUse();
6397 SDValue Op0 = Op.getOperand(0);
6398 SDValue Op1 = Op.getOperand(1);
6400 // Try to match the following pattern:
6401 // (BINOP (extract_vector_elt A, I), (extract_vector_elt A, I+1))
6402 CanFold = (Op0.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
6403 Op1.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
6404 Op0.getOperand(0) == Op1.getOperand(0) &&
6405 isa<ConstantSDNode>(Op0.getOperand(1)) &&
6406 isa<ConstantSDNode>(Op1.getOperand(1)));
6410 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
6411 unsigned I1 = cast<ConstantSDNode>(Op1.getOperand(1))->getZExtValue();
6413 if (i * 2 < NumElts) {
6414 if (V0.getOpcode() == ISD::UNDEF)
6415 V0 = Op0.getOperand(0);
6417 if (V1.getOpcode() == ISD::UNDEF)
6418 V1 = Op0.getOperand(0);
6419 if (i * 2 == NumElts)
6420 ExpectedVExtractIdx = BaseIdx;
6423 SDValue Expected = (i * 2 < NumElts) ? V0 : V1;
6424 if (I0 == ExpectedVExtractIdx)
6425 CanFold = I1 == I0 + 1 && Op0.getOperand(0) == Expected;
6426 else if (IsCommutable && I1 == ExpectedVExtractIdx) {
6427 // Try to match the following dag sequence:
6428 // (BINOP (extract_vector_elt A, I+1), (extract_vector_elt A, I))
6429 CanFold = I0 == I1 + 1 && Op1.getOperand(0) == Expected;
6433 ExpectedVExtractIdx += 2;
6439 /// \brief Emit a sequence of two 128-bit horizontal add/sub followed by
6440 /// a concat_vector.
6442 /// This is a helper function of PerformBUILD_VECTORCombine.
6443 /// This function expects two 256-bit vectors called V0 and V1.
6444 /// At first, each vector is split into two separate 128-bit vectors.
6445 /// Then, the resulting 128-bit vectors are used to implement two
6446 /// horizontal binary operations.
6448 /// The kind of horizontal binary operation is defined by \p X86Opcode.
6450 /// \p Mode specifies how the 128-bit parts of V0 and V1 are passed in input to
6451 /// the two new horizontal binop.
6452 /// When Mode is set, the first horizontal binop dag node would take as input
6453 /// the lower 128-bit of V0 and the upper 128-bit of V0. The second
6454 /// horizontal binop dag node would take as input the lower 128-bit of V1
6455 /// and the upper 128-bit of V1.
6457 /// HADD V0_LO, V0_HI
6458 /// HADD V1_LO, V1_HI
6460 /// Otherwise, the first horizontal binop dag node takes as input the lower
6461 /// 128-bit of V0 and the lower 128-bit of V1, and the second horizontal binop
6462 /// dag node takes the the upper 128-bit of V0 and the upper 128-bit of V1.
6464 /// HADD V0_LO, V1_LO
6465 /// HADD V0_HI, V1_HI
6467 /// If \p isUndefLO is set, then the algorithm propagates UNDEF to the lower
6468 /// 128-bits of the result. If \p isUndefHI is set, then UNDEF is propagated to
6469 /// the upper 128-bits of the result.
6470 static SDValue ExpandHorizontalBinOp(const SDValue &V0, const SDValue &V1,
6471 SDLoc DL, SelectionDAG &DAG,
6472 unsigned X86Opcode, bool Mode,
6473 bool isUndefLO, bool isUndefHI) {
6474 EVT VT = V0.getValueType();
6475 assert(VT.is256BitVector() && VT == V1.getValueType() &&
6476 "Invalid nodes in input!");
6478 unsigned NumElts = VT.getVectorNumElements();
6479 SDValue V0_LO = Extract128BitVector(V0, 0, DAG, DL);
6480 SDValue V0_HI = Extract128BitVector(V0, NumElts/2, DAG, DL);
6481 SDValue V1_LO = Extract128BitVector(V1, 0, DAG, DL);
6482 SDValue V1_HI = Extract128BitVector(V1, NumElts/2, DAG, DL);
6483 EVT NewVT = V0_LO.getValueType();
6485 SDValue LO = DAG.getUNDEF(NewVT);
6486 SDValue HI = DAG.getUNDEF(NewVT);
6489 // Don't emit a horizontal binop if the result is expected to be UNDEF.
6490 if (!isUndefLO && V0->getOpcode() != ISD::UNDEF)
6491 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V0_HI);
6492 if (!isUndefHI && V1->getOpcode() != ISD::UNDEF)
6493 HI = DAG.getNode(X86Opcode, DL, NewVT, V1_LO, V1_HI);
6495 // Don't emit a horizontal binop if the result is expected to be UNDEF.
6496 if (!isUndefLO && (V0_LO->getOpcode() != ISD::UNDEF ||
6497 V1_LO->getOpcode() != ISD::UNDEF))
6498 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V1_LO);
6500 if (!isUndefHI && (V0_HI->getOpcode() != ISD::UNDEF ||
6501 V1_HI->getOpcode() != ISD::UNDEF))
6502 HI = DAG.getNode(X86Opcode, DL, NewVT, V0_HI, V1_HI);
6505 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LO, HI);
6508 /// \brief Try to fold a build_vector that performs an 'addsub' into the
6509 /// sequence of 'vadd + vsub + blendi'.
6510 static SDValue matchAddSub(const BuildVectorSDNode *BV, SelectionDAG &DAG,
6511 const X86Subtarget *Subtarget) {
6513 EVT VT = BV->getValueType(0);
6514 unsigned NumElts = VT.getVectorNumElements();
6515 SDValue InVec0 = DAG.getUNDEF(VT);
6516 SDValue InVec1 = DAG.getUNDEF(VT);
6518 assert((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v4f32 ||
6519 VT == MVT::v2f64) && "build_vector with an invalid type found!");
6521 // Odd-numbered elements in the input build vector are obtained from
6522 // adding two integer/float elements.
6523 // Even-numbered elements in the input build vector are obtained from
6524 // subtracting two integer/float elements.
6525 unsigned ExpectedOpcode = ISD::FSUB;
6526 unsigned NextExpectedOpcode = ISD::FADD;
6527 bool AddFound = false;
6528 bool SubFound = false;
6530 for (unsigned i = 0, e = NumElts; i != e; i++) {
6531 SDValue Op = BV->getOperand(i);
6533 // Skip 'undef' values.
6534 unsigned Opcode = Op.getOpcode();
6535 if (Opcode == ISD::UNDEF) {
6536 std::swap(ExpectedOpcode, NextExpectedOpcode);
6540 // Early exit if we found an unexpected opcode.
6541 if (Opcode != ExpectedOpcode)
6544 SDValue Op0 = Op.getOperand(0);
6545 SDValue Op1 = Op.getOperand(1);
6547 // Try to match the following pattern:
6548 // (BINOP (extract_vector_elt A, i), (extract_vector_elt B, i))
6549 // Early exit if we cannot match that sequence.
6550 if (Op0.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
6551 Op1.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
6552 !isa<ConstantSDNode>(Op0.getOperand(1)) ||
6553 !isa<ConstantSDNode>(Op1.getOperand(1)) ||
6554 Op0.getOperand(1) != Op1.getOperand(1))
6557 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
6561 // We found a valid add/sub node. Update the information accordingly.
6567 // Update InVec0 and InVec1.
6568 if (InVec0.getOpcode() == ISD::UNDEF)
6569 InVec0 = Op0.getOperand(0);
6570 if (InVec1.getOpcode() == ISD::UNDEF)
6571 InVec1 = Op1.getOperand(0);
6573 // Make sure that operands in input to each add/sub node always
6574 // come from a same pair of vectors.
6575 if (InVec0 != Op0.getOperand(0)) {
6576 if (ExpectedOpcode == ISD::FSUB)
6579 // FADD is commutable. Try to commute the operands
6580 // and then test again.
6581 std::swap(Op0, Op1);
6582 if (InVec0 != Op0.getOperand(0))
6586 if (InVec1 != Op1.getOperand(0))
6589 // Update the pair of expected opcodes.
6590 std::swap(ExpectedOpcode, NextExpectedOpcode);
6593 // Don't try to fold this build_vector into an ADDSUB if the inputs are undef.
6594 if (AddFound && SubFound && InVec0.getOpcode() != ISD::UNDEF &&
6595 InVec1.getOpcode() != ISD::UNDEF)
6596 return DAG.getNode(X86ISD::ADDSUB, DL, VT, InVec0, InVec1);
6601 static SDValue PerformBUILD_VECTORCombine(SDNode *N, SelectionDAG &DAG,
6602 const X86Subtarget *Subtarget) {
6604 EVT VT = N->getValueType(0);
6605 unsigned NumElts = VT.getVectorNumElements();
6606 BuildVectorSDNode *BV = cast<BuildVectorSDNode>(N);
6607 SDValue InVec0, InVec1;
6609 // Try to match an ADDSUB.
6610 if ((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
6611 (Subtarget->hasAVX() && (VT == MVT::v8f32 || VT == MVT::v4f64))) {
6612 SDValue Value = matchAddSub(BV, DAG, Subtarget);
6613 if (Value.getNode())
6617 // Try to match horizontal ADD/SUB.
6618 unsigned NumUndefsLO = 0;
6619 unsigned NumUndefsHI = 0;
6620 unsigned Half = NumElts/2;
6622 // Count the number of UNDEF operands in the build_vector in input.
6623 for (unsigned i = 0, e = Half; i != e; ++i)
6624 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
6627 for (unsigned i = Half, e = NumElts; i != e; ++i)
6628 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
6631 // Early exit if this is either a build_vector of all UNDEFs or all the
6632 // operands but one are UNDEF.
6633 if (NumUndefsLO + NumUndefsHI + 1 >= NumElts)
6636 if ((VT == MVT::v4f32 || VT == MVT::v2f64) && Subtarget->hasSSE3()) {
6637 // Try to match an SSE3 float HADD/HSUB.
6638 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
6639 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
6641 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
6642 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
6643 } else if ((VT == MVT::v4i32 || VT == MVT::v8i16) && Subtarget->hasSSSE3()) {
6644 // Try to match an SSSE3 integer HADD/HSUB.
6645 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
6646 return DAG.getNode(X86ISD::HADD, DL, VT, InVec0, InVec1);
6648 if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
6649 return DAG.getNode(X86ISD::HSUB, DL, VT, InVec0, InVec1);
6652 if (!Subtarget->hasAVX())
6655 if ((VT == MVT::v8f32 || VT == MVT::v4f64)) {
6656 // Try to match an AVX horizontal add/sub of packed single/double
6657 // precision floating point values from 256-bit vectors.
6658 SDValue InVec2, InVec3;
6659 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, Half, InVec0, InVec1) &&
6660 isHorizontalBinOp(BV, ISD::FADD, DAG, Half, NumElts, InVec2, InVec3) &&
6661 ((InVec0.getOpcode() == ISD::UNDEF ||
6662 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6663 ((InVec1.getOpcode() == ISD::UNDEF ||
6664 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6665 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
6667 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, Half, InVec0, InVec1) &&
6668 isHorizontalBinOp(BV, ISD::FSUB, DAG, Half, NumElts, InVec2, InVec3) &&
6669 ((InVec0.getOpcode() == ISD::UNDEF ||
6670 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6671 ((InVec1.getOpcode() == ISD::UNDEF ||
6672 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6673 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
6674 } else if (VT == MVT::v8i32 || VT == MVT::v16i16) {
6675 // Try to match an AVX2 horizontal add/sub of signed integers.
6676 SDValue InVec2, InVec3;
6678 bool CanFold = true;
6680 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, Half, InVec0, InVec1) &&
6681 isHorizontalBinOp(BV, ISD::ADD, DAG, Half, NumElts, InVec2, InVec3) &&
6682 ((InVec0.getOpcode() == ISD::UNDEF ||
6683 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6684 ((InVec1.getOpcode() == ISD::UNDEF ||
6685 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6686 X86Opcode = X86ISD::HADD;
6687 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, Half, InVec0, InVec1) &&
6688 isHorizontalBinOp(BV, ISD::SUB, DAG, Half, NumElts, InVec2, InVec3) &&
6689 ((InVec0.getOpcode() == ISD::UNDEF ||
6690 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6691 ((InVec1.getOpcode() == ISD::UNDEF ||
6692 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6693 X86Opcode = X86ISD::HSUB;
6698 // Fold this build_vector into a single horizontal add/sub.
6699 // Do this only if the target has AVX2.
6700 if (Subtarget->hasAVX2())
6701 return DAG.getNode(X86Opcode, DL, VT, InVec0, InVec1);
6703 // Do not try to expand this build_vector into a pair of horizontal
6704 // add/sub if we can emit a pair of scalar add/sub.
6705 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
6708 // Convert this build_vector into a pair of horizontal binop followed by
6710 bool isUndefLO = NumUndefsLO == Half;
6711 bool isUndefHI = NumUndefsHI == Half;
6712 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, false,
6713 isUndefLO, isUndefHI);
6717 if ((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v8i32 ||
6718 VT == MVT::v16i16) && Subtarget->hasAVX()) {
6720 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
6721 X86Opcode = X86ISD::HADD;
6722 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
6723 X86Opcode = X86ISD::HSUB;
6724 else if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
6725 X86Opcode = X86ISD::FHADD;
6726 else if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
6727 X86Opcode = X86ISD::FHSUB;
6731 // Don't try to expand this build_vector into a pair of horizontal add/sub
6732 // if we can simply emit a pair of scalar add/sub.
6733 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
6736 // Convert this build_vector into two horizontal add/sub followed by
6738 bool isUndefLO = NumUndefsLO == Half;
6739 bool isUndefHI = NumUndefsHI == Half;
6740 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, true,
6741 isUndefLO, isUndefHI);
6748 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
6751 MVT VT = Op.getSimpleValueType();
6752 MVT ExtVT = VT.getVectorElementType();
6753 unsigned NumElems = Op.getNumOperands();
6755 // Generate vectors for predicate vectors.
6756 if (VT.getScalarType() == MVT::i1 && Subtarget->hasAVX512())
6757 return LowerBUILD_VECTORvXi1(Op, DAG);
6759 // Vectors containing all zeros can be matched by pxor and xorps later
6760 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
6761 // Canonicalize this to <4 x i32> to 1) ensure the zero vectors are CSE'd
6762 // and 2) ensure that i64 scalars are eliminated on x86-32 hosts.
6763 if (VT == MVT::v4i32 || VT == MVT::v8i32 || VT == MVT::v16i32)
6766 return getZeroVector(VT, Subtarget, DAG, dl);
6769 // Vectors containing all ones can be matched by pcmpeqd on 128-bit width
6770 // vectors or broken into v4i32 operations on 256-bit vectors. AVX2 can use
6771 // vpcmpeqd on 256-bit vectors.
6772 if (Subtarget->hasSSE2() && ISD::isBuildVectorAllOnes(Op.getNode())) {
6773 if (VT == MVT::v4i32 || (VT == MVT::v8i32 && Subtarget->hasInt256()))
6776 if (!VT.is512BitVector())
6777 return getOnesVector(VT, Subtarget->hasInt256(), DAG, dl);
6780 SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG);
6781 if (Broadcast.getNode())
6784 unsigned EVTBits = ExtVT.getSizeInBits();
6786 unsigned NumZero = 0;
6787 unsigned NumNonZero = 0;
6788 unsigned NonZeros = 0;
6789 bool IsAllConstants = true;
6790 SmallSet<SDValue, 8> Values;
6791 for (unsigned i = 0; i < NumElems; ++i) {
6792 SDValue Elt = Op.getOperand(i);
6793 if (Elt.getOpcode() == ISD::UNDEF)
6796 if (Elt.getOpcode() != ISD::Constant &&
6797 Elt.getOpcode() != ISD::ConstantFP)
6798 IsAllConstants = false;
6799 if (X86::isZeroNode(Elt))
6802 NonZeros |= (1 << i);
6807 // All undef vector. Return an UNDEF. All zero vectors were handled above.
6808 if (NumNonZero == 0)
6809 return DAG.getUNDEF(VT);
6811 // Special case for single non-zero, non-undef, element.
6812 if (NumNonZero == 1) {
6813 unsigned Idx = countTrailingZeros(NonZeros);
6814 SDValue Item = Op.getOperand(Idx);
6816 // If this is an insertion of an i64 value on x86-32, and if the top bits of
6817 // the value are obviously zero, truncate the value to i32 and do the
6818 // insertion that way. Only do this if the value is non-constant or if the
6819 // value is a constant being inserted into element 0. It is cheaper to do
6820 // a constant pool load than it is to do a movd + shuffle.
6821 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
6822 (!IsAllConstants || Idx == 0)) {
6823 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
6825 assert(VT == MVT::v2i64 && "Expected an SSE value type!");
6826 EVT VecVT = MVT::v4i32;
6827 unsigned VecElts = 4;
6829 // Truncate the value (which may itself be a constant) to i32, and
6830 // convert it to a vector with movd (S2V+shuffle to zero extend).
6831 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
6832 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
6834 // If using the new shuffle lowering, just directly insert this.
6835 if (ExperimentalVectorShuffleLowering)
6837 ISD::BITCAST, dl, VT,
6838 getShuffleVectorZeroOrUndef(Item, Idx * 2, true, Subtarget, DAG));
6840 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6842 // Now we have our 32-bit value zero extended in the low element of
6843 // a vector. If Idx != 0, swizzle it into place.
6845 SmallVector<int, 4> Mask;
6846 Mask.push_back(Idx);
6847 for (unsigned i = 1; i != VecElts; ++i)
6849 Item = DAG.getVectorShuffle(VecVT, dl, Item, DAG.getUNDEF(VecVT),
6852 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
6856 // If we have a constant or non-constant insertion into the low element of
6857 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
6858 // the rest of the elements. This will be matched as movd/movq/movss/movsd
6859 // depending on what the source datatype is.
6862 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6864 if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
6865 (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
6866 if (VT.is256BitVector() || VT.is512BitVector()) {
6867 SDValue ZeroVec = getZeroVector(VT, Subtarget, DAG, dl);
6868 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, ZeroVec,
6869 Item, DAG.getIntPtrConstant(0));
6871 assert(VT.is128BitVector() && "Expected an SSE value type!");
6872 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6873 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
6874 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6877 if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
6878 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
6879 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
6880 if (VT.is256BitVector()) {
6881 SDValue ZeroVec = getZeroVector(MVT::v8i32, Subtarget, DAG, dl);
6882 Item = Insert128BitVector(ZeroVec, Item, 0, DAG, dl);
6884 assert(VT.is128BitVector() && "Expected an SSE value type!");
6885 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6887 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
6891 // Is it a vector logical left shift?
6892 if (NumElems == 2 && Idx == 1 &&
6893 X86::isZeroNode(Op.getOperand(0)) &&
6894 !X86::isZeroNode(Op.getOperand(1))) {
6895 unsigned NumBits = VT.getSizeInBits();
6896 return getVShift(true, VT,
6897 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
6898 VT, Op.getOperand(1)),
6899 NumBits/2, DAG, *this, dl);
6902 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
6905 // Otherwise, if this is a vector with i32 or f32 elements, and the element
6906 // is a non-constant being inserted into an element other than the low one,
6907 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
6908 // movd/movss) to move this into the low element, then shuffle it into
6910 if (EVTBits == 32) {
6911 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6913 // If using the new shuffle lowering, just directly insert this.
6914 if (ExperimentalVectorShuffleLowering)
6915 return getShuffleVectorZeroOrUndef(Item, Idx, NumZero > 0, Subtarget, DAG);
6917 // Turn it into a shuffle of zero and zero-extended scalar to vector.
6918 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0, Subtarget, DAG);
6919 SmallVector<int, 8> MaskVec;
6920 for (unsigned i = 0; i != NumElems; ++i)
6921 MaskVec.push_back(i == Idx ? 0 : 1);
6922 return DAG.getVectorShuffle(VT, dl, Item, DAG.getUNDEF(VT), &MaskVec[0]);
6926 // Splat is obviously ok. Let legalizer expand it to a shuffle.
6927 if (Values.size() == 1) {
6928 if (EVTBits == 32) {
6929 // Instead of a shuffle like this:
6930 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
6931 // Check if it's possible to issue this instead.
6932 // shuffle (vload ptr)), undef, <1, 1, 1, 1>
6933 unsigned Idx = countTrailingZeros(NonZeros);
6934 SDValue Item = Op.getOperand(Idx);
6935 if (Op.getNode()->isOnlyUserOf(Item.getNode()))
6936 return LowerAsSplatVectorLoad(Item, VT, dl, DAG);
6941 // A vector full of immediates; various special cases are already
6942 // handled, so this is best done with a single constant-pool load.
6946 // For AVX-length vectors, build the individual 128-bit pieces and use
6947 // shuffles to put them in place.
6948 if (VT.is256BitVector() || VT.is512BitVector()) {
6949 SmallVector<SDValue, 64> V;
6950 for (unsigned i = 0; i != NumElems; ++i)
6951 V.push_back(Op.getOperand(i));
6953 EVT HVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems/2);
6955 // Build both the lower and upper subvector.
6956 SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
6957 makeArrayRef(&V[0], NumElems/2));
6958 SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
6959 makeArrayRef(&V[NumElems / 2], NumElems/2));
6961 // Recreate the wider vector with the lower and upper part.
6962 if (VT.is256BitVector())
6963 return Concat128BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
6964 return Concat256BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
6967 // Let legalizer expand 2-wide build_vectors.
6968 if (EVTBits == 64) {
6969 if (NumNonZero == 1) {
6970 // One half is zero or undef.
6971 unsigned Idx = countTrailingZeros(NonZeros);
6972 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
6973 Op.getOperand(Idx));
6974 return getShuffleVectorZeroOrUndef(V2, Idx, true, Subtarget, DAG);
6979 // If element VT is < 32 bits, convert it to inserts into a zero vector.
6980 if (EVTBits == 8 && NumElems == 16) {
6981 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
6983 if (V.getNode()) return V;
6986 if (EVTBits == 16 && NumElems == 8) {
6987 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
6989 if (V.getNode()) return V;
6992 // If element VT is == 32 bits and has 4 elems, try to generate an INSERTPS
6993 if (EVTBits == 32 && NumElems == 4) {
6994 SDValue V = LowerBuildVectorv4x32(Op, NumElems, NonZeros, NumNonZero,
6995 NumZero, DAG, Subtarget, *this);
7000 // If element VT is == 32 bits, turn it into a number of shuffles.
7001 SmallVector<SDValue, 8> V(NumElems);
7002 if (NumElems == 4 && NumZero > 0) {
7003 for (unsigned i = 0; i < 4; ++i) {
7004 bool isZero = !(NonZeros & (1 << i));
7006 V[i] = getZeroVector(VT, Subtarget, DAG, dl);
7008 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
7011 for (unsigned i = 0; i < 2; ++i) {
7012 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
7015 V[i] = V[i*2]; // Must be a zero vector.
7018 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
7021 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
7024 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
7029 bool Reverse1 = (NonZeros & 0x3) == 2;
7030 bool Reverse2 = ((NonZeros & (0x3 << 2)) >> 2) == 2;
7034 static_cast<int>(Reverse2 ? NumElems+1 : NumElems),
7035 static_cast<int>(Reverse2 ? NumElems : NumElems+1)
7037 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
7040 if (Values.size() > 1 && VT.is128BitVector()) {
7041 // Check for a build vector of consecutive loads.
7042 for (unsigned i = 0; i < NumElems; ++i)
7043 V[i] = Op.getOperand(i);
7045 // Check for elements which are consecutive loads.
7046 SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG, false);
7050 // Check for a build vector from mostly shuffle plus few inserting.
7051 SDValue Sh = buildFromShuffleMostly(Op, DAG);
7055 // For SSE 4.1, use insertps to put the high elements into the low element.
7056 if (getSubtarget()->hasSSE41()) {
7058 if (Op.getOperand(0).getOpcode() != ISD::UNDEF)
7059 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0));
7061 Result = DAG.getUNDEF(VT);
7063 for (unsigned i = 1; i < NumElems; ++i) {
7064 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue;
7065 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result,
7066 Op.getOperand(i), DAG.getIntPtrConstant(i));
7071 // Otherwise, expand into a number of unpckl*, start by extending each of
7072 // our (non-undef) elements to the full vector width with the element in the
7073 // bottom slot of the vector (which generates no code for SSE).
7074 for (unsigned i = 0; i < NumElems; ++i) {
7075 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
7076 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
7078 V[i] = DAG.getUNDEF(VT);
7081 // Next, we iteratively mix elements, e.g. for v4f32:
7082 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
7083 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
7084 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
7085 unsigned EltStride = NumElems >> 1;
7086 while (EltStride != 0) {
7087 for (unsigned i = 0; i < EltStride; ++i) {
7088 // If V[i+EltStride] is undef and this is the first round of mixing,
7089 // then it is safe to just drop this shuffle: V[i] is already in the
7090 // right place, the one element (since it's the first round) being
7091 // inserted as undef can be dropped. This isn't safe for successive
7092 // rounds because they will permute elements within both vectors.
7093 if (V[i+EltStride].getOpcode() == ISD::UNDEF &&
7094 EltStride == NumElems/2)
7097 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]);
7106 // LowerAVXCONCAT_VECTORS - 256-bit AVX can use the vinsertf128 instruction
7107 // to create 256-bit vectors from two other 128-bit ones.
7108 static SDValue LowerAVXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
7110 MVT ResVT = Op.getSimpleValueType();
7112 assert((ResVT.is256BitVector() ||
7113 ResVT.is512BitVector()) && "Value type must be 256-/512-bit wide");
7115 SDValue V1 = Op.getOperand(0);
7116 SDValue V2 = Op.getOperand(1);
7117 unsigned NumElems = ResVT.getVectorNumElements();
7118 if(ResVT.is256BitVector())
7119 return Concat128BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
7121 if (Op.getNumOperands() == 4) {
7122 MVT HalfVT = MVT::getVectorVT(ResVT.getScalarType(),
7123 ResVT.getVectorNumElements()/2);
7124 SDValue V3 = Op.getOperand(2);
7125 SDValue V4 = Op.getOperand(3);
7126 return Concat256BitVectors(Concat128BitVectors(V1, V2, HalfVT, NumElems/2, DAG, dl),
7127 Concat128BitVectors(V3, V4, HalfVT, NumElems/2, DAG, dl), ResVT, NumElems, DAG, dl);
7129 return Concat256BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
7132 static SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
7133 MVT LLVM_ATTRIBUTE_UNUSED VT = Op.getSimpleValueType();
7134 assert((VT.is256BitVector() && Op.getNumOperands() == 2) ||
7135 (VT.is512BitVector() && (Op.getNumOperands() == 2 ||
7136 Op.getNumOperands() == 4)));
7138 // AVX can use the vinsertf128 instruction to create 256-bit vectors
7139 // from two other 128-bit ones.
7141 // 512-bit vector may contain 2 256-bit vectors or 4 128-bit vectors
7142 return LowerAVXCONCAT_VECTORS(Op, DAG);
7146 //===----------------------------------------------------------------------===//
7147 // Vector shuffle lowering
7149 // This is an experimental code path for lowering vector shuffles on x86. It is
7150 // designed to handle arbitrary vector shuffles and blends, gracefully
7151 // degrading performance as necessary. It works hard to recognize idiomatic
7152 // shuffles and lower them to optimal instruction patterns without leaving
7153 // a framework that allows reasonably efficient handling of all vector shuffle
7155 //===----------------------------------------------------------------------===//
7157 /// \brief Tiny helper function to identify a no-op mask.
7159 /// This is a somewhat boring predicate function. It checks whether the mask
7160 /// array input, which is assumed to be a single-input shuffle mask of the kind
7161 /// used by the X86 shuffle instructions (not a fully general
7162 /// ShuffleVectorSDNode mask) requires any shuffles to occur. Both undef and an
7163 /// in-place shuffle are 'no-op's.
7164 static bool isNoopShuffleMask(ArrayRef<int> Mask) {
7165 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7166 if (Mask[i] != -1 && Mask[i] != i)
7171 /// \brief Helper function to classify a mask as a single-input mask.
7173 /// This isn't a generic single-input test because in the vector shuffle
7174 /// lowering we canonicalize single inputs to be the first input operand. This
7175 /// means we can more quickly test for a single input by only checking whether
7176 /// an input from the second operand exists. We also assume that the size of
7177 /// mask corresponds to the size of the input vectors which isn't true in the
7178 /// fully general case.
7179 static bool isSingleInputShuffleMask(ArrayRef<int> Mask) {
7181 if (M >= (int)Mask.size())
7186 /// \brief Test whether there are elements crossing 128-bit lanes in this
7189 /// X86 divides up its shuffles into in-lane and cross-lane shuffle operations
7190 /// and we routinely test for these.
7191 static bool is128BitLaneCrossingShuffleMask(MVT VT, ArrayRef<int> Mask) {
7192 int LaneSize = 128 / VT.getScalarSizeInBits();
7193 int Size = Mask.size();
7194 for (int i = 0; i < Size; ++i)
7195 if (Mask[i] >= 0 && (Mask[i] % Size) / LaneSize != i / LaneSize)
7200 /// \brief Test whether a shuffle mask is equivalent within each 128-bit lane.
7202 /// This checks a shuffle mask to see if it is performing the same
7203 /// 128-bit lane-relative shuffle in each 128-bit lane. This trivially implies
7204 /// that it is also not lane-crossing. It may however involve a blend from the
7205 /// same lane of a second vector.
7207 /// The specific repeated shuffle mask is populated in \p RepeatedMask, as it is
7208 /// non-trivial to compute in the face of undef lanes. The representation is
7209 /// *not* suitable for use with existing 128-bit shuffles as it will contain
7210 /// entries from both V1 and V2 inputs to the wider mask.
7212 is128BitLaneRepeatedShuffleMask(MVT VT, ArrayRef<int> Mask,
7213 SmallVectorImpl<int> &RepeatedMask) {
7214 int LaneSize = 128 / VT.getScalarSizeInBits();
7215 RepeatedMask.resize(LaneSize, -1);
7216 int Size = Mask.size();
7217 for (int i = 0; i < Size; ++i) {
7220 if ((Mask[i] % Size) / LaneSize != i / LaneSize)
7221 // This entry crosses lanes, so there is no way to model this shuffle.
7224 // Ok, handle the in-lane shuffles by detecting if and when they repeat.
7225 if (RepeatedMask[i % LaneSize] == -1)
7226 // This is the first non-undef entry in this slot of a 128-bit lane.
7227 RepeatedMask[i % LaneSize] =
7228 Mask[i] < Size ? Mask[i] % LaneSize : Mask[i] % LaneSize + Size;
7229 else if (RepeatedMask[i % LaneSize] + (i / LaneSize) * LaneSize != Mask[i])
7230 // Found a mismatch with the repeated mask.
7236 // Hide this symbol with an anonymous namespace instead of 'static' so that MSVC
7237 // 2013 will allow us to use it as a non-type template parameter.
7240 /// \brief Implementation of the \c isShuffleEquivalent variadic functor.
7242 /// See its documentation for details.
7243 bool isShuffleEquivalentImpl(ArrayRef<int> Mask, ArrayRef<const int *> Args) {
7244 if (Mask.size() != Args.size())
7246 for (int i = 0, e = Mask.size(); i < e; ++i) {
7247 assert(*Args[i] >= 0 && "Arguments must be positive integers!");
7248 if (Mask[i] != -1 && Mask[i] != *Args[i])
7256 /// \brief Checks whether a shuffle mask is equivalent to an explicit list of
7259 /// This is a fast way to test a shuffle mask against a fixed pattern:
7261 /// if (isShuffleEquivalent(Mask, 3, 2, 1, 0)) { ... }
7263 /// It returns true if the mask is exactly as wide as the argument list, and
7264 /// each element of the mask is either -1 (signifying undef) or the value given
7265 /// in the argument.
7266 static const VariadicFunction1<
7267 bool, ArrayRef<int>, int, isShuffleEquivalentImpl> isShuffleEquivalent = {};
7269 /// \brief Get a 4-lane 8-bit shuffle immediate for a mask.
7271 /// This helper function produces an 8-bit shuffle immediate corresponding to
7272 /// the ubiquitous shuffle encoding scheme used in x86 instructions for
7273 /// shuffling 4 lanes. It can be used with most of the PSHUF instructions for
7276 /// NB: We rely heavily on "undef" masks preserving the input lane.
7277 static SDValue getV4X86ShuffleImm8ForMask(ArrayRef<int> Mask,
7278 SelectionDAG &DAG) {
7279 assert(Mask.size() == 4 && "Only 4-lane shuffle masks");
7280 assert(Mask[0] >= -1 && Mask[0] < 4 && "Out of bound mask element!");
7281 assert(Mask[1] >= -1 && Mask[1] < 4 && "Out of bound mask element!");
7282 assert(Mask[2] >= -1 && Mask[2] < 4 && "Out of bound mask element!");
7283 assert(Mask[3] >= -1 && Mask[3] < 4 && "Out of bound mask element!");
7286 Imm |= (Mask[0] == -1 ? 0 : Mask[0]) << 0;
7287 Imm |= (Mask[1] == -1 ? 1 : Mask[1]) << 2;
7288 Imm |= (Mask[2] == -1 ? 2 : Mask[2]) << 4;
7289 Imm |= (Mask[3] == -1 ? 3 : Mask[3]) << 6;
7290 return DAG.getConstant(Imm, MVT::i8);
7293 /// \brief Try to emit a blend instruction for a shuffle.
7295 /// This doesn't do any checks for the availability of instructions for blending
7296 /// these values. It relies on the availability of the X86ISD::BLENDI pattern to
7297 /// be matched in the backend with the type given. What it does check for is
7298 /// that the shuffle mask is in fact a blend.
7299 static SDValue lowerVectorShuffleAsBlend(SDLoc DL, MVT VT, SDValue V1,
7300 SDValue V2, ArrayRef<int> Mask,
7301 const X86Subtarget *Subtarget,
7302 SelectionDAG &DAG) {
7304 unsigned BlendMask = 0;
7305 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
7306 if (Mask[i] >= Size) {
7307 if (Mask[i] != i + Size)
7308 return SDValue(); // Shuffled V2 input!
7309 BlendMask |= 1u << i;
7312 if (Mask[i] >= 0 && Mask[i] != i)
7313 return SDValue(); // Shuffled V1 input!
7315 switch (VT.SimpleTy) {
7320 return DAG.getNode(X86ISD::BLENDI, DL, VT, V1, V2,
7321 DAG.getConstant(BlendMask, MVT::i8));
7325 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
7329 // If we have AVX2 it is faster to use VPBLENDD when the shuffle fits into
7330 // that instruction.
7331 if (Subtarget->hasAVX2()) {
7332 // Scale the blend by the number of 32-bit dwords per element.
7333 int Scale = VT.getScalarSizeInBits() / 32;
7335 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7336 if (Mask[i] >= Size)
7337 for (int j = 0; j < Scale; ++j)
7338 BlendMask |= 1u << (i * Scale + j);
7340 MVT BlendVT = VT.getSizeInBits() > 128 ? MVT::v8i32 : MVT::v4i32;
7341 V1 = DAG.getNode(ISD::BITCAST, DL, BlendVT, V1);
7342 V2 = DAG.getNode(ISD::BITCAST, DL, BlendVT, V2);
7343 return DAG.getNode(ISD::BITCAST, DL, VT,
7344 DAG.getNode(X86ISD::BLENDI, DL, BlendVT, V1, V2,
7345 DAG.getConstant(BlendMask, MVT::i8)));
7349 // For integer shuffles we need to expand the mask and cast the inputs to
7350 // v8i16s prior to blending.
7351 int Scale = 8 / VT.getVectorNumElements();
7353 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7354 if (Mask[i] >= Size)
7355 for (int j = 0; j < Scale; ++j)
7356 BlendMask |= 1u << (i * Scale + j);
7358 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1);
7359 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V2);
7360 return DAG.getNode(ISD::BITCAST, DL, VT,
7361 DAG.getNode(X86ISD::BLENDI, DL, MVT::v8i16, V1, V2,
7362 DAG.getConstant(BlendMask, MVT::i8)));
7366 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
7367 SmallVector<int, 8> RepeatedMask;
7368 if (is128BitLaneRepeatedShuffleMask(MVT::v16i16, Mask, RepeatedMask)) {
7369 // We can lower these with PBLENDW which is mirrored across 128-bit lanes.
7370 assert(RepeatedMask.size() == 8 && "Repeated mask size doesn't match!");
7372 for (int i = 0; i < 8; ++i)
7373 if (RepeatedMask[i] >= 16)
7374 BlendMask |= 1u << i;
7375 return DAG.getNode(X86ISD::BLENDI, DL, MVT::v16i16, V1, V2,
7376 DAG.getConstant(BlendMask, MVT::i8));
7381 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
7382 // Scale the blend by the number of bytes per element.
7383 int Scale = VT.getScalarSizeInBits() / 8;
7384 assert(Mask.size() * Scale == 32 && "Not a 256-bit vector!");
7386 // Compute the VSELECT mask. Note that VSELECT is really confusing in the
7387 // mix of LLVM's code generator and the x86 backend. We tell the code
7388 // generator that boolean values in the elements of an x86 vector register
7389 // are -1 for true and 0 for false. We then use the LLVM semantics of 'true'
7390 // mapping a select to operand #1, and 'false' mapping to operand #2. The
7391 // reality in x86 is that vector masks (pre-AVX-512) use only the high bit
7392 // of the element (the remaining are ignored) and 0 in that high bit would
7393 // mean operand #1 while 1 in the high bit would mean operand #2. So while
7394 // the LLVM model for boolean values in vector elements gets the relevant
7395 // bit set, it is set backwards and over constrained relative to x86's
7397 SDValue VSELECTMask[32];
7398 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7399 for (int j = 0; j < Scale; ++j)
7400 VSELECTMask[Scale * i + j] =
7401 Mask[i] < 0 ? DAG.getUNDEF(MVT::i8)
7402 : DAG.getConstant(Mask[i] < Size ? -1 : 0, MVT::i8);
7404 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, V1);
7405 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, V2);
7407 ISD::BITCAST, DL, VT,
7408 DAG.getNode(ISD::VSELECT, DL, MVT::v32i8,
7409 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, VSELECTMask),
7414 llvm_unreachable("Not a supported integer vector type!");
7418 /// \brief Generic routine to lower a shuffle and blend as a decomposed set of
7419 /// unblended shuffles followed by an unshuffled blend.
7421 /// This matches the extremely common pattern for handling combined
7422 /// shuffle+blend operations on newer X86 ISAs where we have very fast blend
7424 static SDValue lowerVectorShuffleAsDecomposedShuffleBlend(SDLoc DL, MVT VT,
7428 SelectionDAG &DAG) {
7429 // Shuffle the input elements into the desired positions in V1 and V2 and
7430 // blend them together.
7431 SmallVector<int, 32> V1Mask(Mask.size(), -1);
7432 SmallVector<int, 32> V2Mask(Mask.size(), -1);
7433 SmallVector<int, 32> BlendMask(Mask.size(), -1);
7434 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7435 if (Mask[i] >= 0 && Mask[i] < Size) {
7436 V1Mask[i] = Mask[i];
7438 } else if (Mask[i] >= Size) {
7439 V2Mask[i] = Mask[i] - Size;
7440 BlendMask[i] = i + Size;
7443 V1 = DAG.getVectorShuffle(VT, DL, V1, DAG.getUNDEF(VT), V1Mask);
7444 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Mask);
7445 return DAG.getVectorShuffle(VT, DL, V1, V2, BlendMask);
7448 /// \brief Try to lower a vector shuffle as a byte rotation.
7450 /// We have a generic PALIGNR instruction in x86 that will do an arbitrary
7451 /// byte-rotation of a the concatentation of two vectors. This routine will
7452 /// try to generically lower a vector shuffle through such an instruction. It
7453 /// does not check for the availability of PALIGNR-based lowerings, only the
7454 /// applicability of this strategy to the given mask. This matches shuffle
7455 /// vectors that look like:
7457 /// v8i16 [11, 12, 13, 14, 15, 0, 1, 2]
7459 /// Essentially it concatenates V1 and V2, shifts right by some number of
7460 /// elements, and takes the low elements as the result. Note that while this is
7461 /// specified as a *right shift* because x86 is little-endian, it is a *left
7462 /// rotate* of the vector lanes.
7464 /// Note that this only handles 128-bit vector widths currently.
7465 static SDValue lowerVectorShuffleAsByteRotate(SDLoc DL, MVT VT, SDValue V1,
7468 SelectionDAG &DAG) {
7469 assert(!isNoopShuffleMask(Mask) && "We shouldn't lower no-op shuffles!");
7471 // We need to detect various ways of spelling a rotation:
7472 // [11, 12, 13, 14, 15, 0, 1, 2]
7473 // [-1, 12, 13, 14, -1, -1, 1, -1]
7474 // [-1, -1, -1, -1, -1, -1, 1, 2]
7475 // [ 3, 4, 5, 6, 7, 8, 9, 10]
7476 // [-1, 4, 5, 6, -1, -1, 9, -1]
7477 // [-1, 4, 5, 6, -1, -1, -1, -1]
7480 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
7483 assert(Mask[i] >= 0 && "Only -1 is a valid negative mask element!");
7485 // Based on the mod-Size value of this mask element determine where
7486 // a rotated vector would have started.
7487 int StartIdx = i - (Mask[i] % Size);
7489 // The identity rotation isn't interesting, stop.
7492 // If we found the tail of a vector the rotation must be the missing
7493 // front. If we found the head of a vector, it must be how much of the head.
7494 int CandidateRotation = StartIdx < 0 ? -StartIdx : Size - StartIdx;
7497 Rotation = CandidateRotation;
7498 else if (Rotation != CandidateRotation)
7499 // The rotations don't match, so we can't match this mask.
7502 // Compute which value this mask is pointing at.
7503 SDValue MaskV = Mask[i] < Size ? V1 : V2;
7505 // Compute which of the two target values this index should be assigned to.
7506 // This reflects whether the high elements are remaining or the low elements
7508 SDValue &TargetV = StartIdx < 0 ? Hi : Lo;
7510 // Either set up this value if we've not encountered it before, or check
7511 // that it remains consistent.
7514 else if (TargetV != MaskV)
7515 // This may be a rotation, but it pulls from the inputs in some
7516 // unsupported interleaving.
7520 // Check that we successfully analyzed the mask, and normalize the results.
7521 assert(Rotation != 0 && "Failed to locate a viable rotation!");
7522 assert((Lo || Hi) && "Failed to find a rotated input vector!");
7528 // Cast the inputs to v16i8 to match PALIGNR.
7529 Lo = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Lo);
7530 Hi = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Hi);
7532 assert(VT.getSizeInBits() == 128 &&
7533 "Rotate-based lowering only supports 128-bit lowering!");
7534 assert(Mask.size() <= 16 &&
7535 "Can shuffle at most 16 bytes in a 128-bit vector!");
7536 // The actual rotate instruction rotates bytes, so we need to scale the
7537 // rotation based on how many bytes are in the vector.
7538 int Scale = 16 / Mask.size();
7540 return DAG.getNode(ISD::BITCAST, DL, VT,
7541 DAG.getNode(X86ISD::PALIGNR, DL, MVT::v16i8, Hi, Lo,
7542 DAG.getConstant(Rotation * Scale, MVT::i8)));
7545 /// \brief Compute whether each element of a shuffle is zeroable.
7547 /// A "zeroable" vector shuffle element is one which can be lowered to zero.
7548 /// Either it is an undef element in the shuffle mask, the element of the input
7549 /// referenced is undef, or the element of the input referenced is known to be
7550 /// zero. Many x86 shuffles can zero lanes cheaply and we often want to handle
7551 /// as many lanes with this technique as possible to simplify the remaining
7553 static SmallBitVector computeZeroableShuffleElements(ArrayRef<int> Mask,
7554 SDValue V1, SDValue V2) {
7555 SmallBitVector Zeroable(Mask.size(), false);
7557 bool V1IsZero = ISD::isBuildVectorAllZeros(V1.getNode());
7558 bool V2IsZero = ISD::isBuildVectorAllZeros(V2.getNode());
7560 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
7562 // Handle the easy cases.
7563 if (M < 0 || (M >= 0 && M < Size && V1IsZero) || (M >= Size && V2IsZero)) {
7568 // If this is an index into a build_vector node, dig out the input value and
7570 SDValue V = M < Size ? V1 : V2;
7571 if (V.getOpcode() != ISD::BUILD_VECTOR)
7574 SDValue Input = V.getOperand(M % Size);
7575 // The UNDEF opcode check really should be dead code here, but not quite
7576 // worth asserting on (it isn't invalid, just unexpected).
7577 if (Input.getOpcode() == ISD::UNDEF || X86::isZeroNode(Input))
7584 /// \brief Lower a vector shuffle as a zero or any extension.
7586 /// Given a specific number of elements, element bit width, and extension
7587 /// stride, produce either a zero or any extension based on the available
7588 /// features of the subtarget.
7589 static SDValue lowerVectorShuffleAsSpecificZeroOrAnyExtend(
7590 SDLoc DL, MVT VT, int NumElements, int Scale, bool AnyExt, SDValue InputV,
7591 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7592 assert(Scale > 1 && "Need a scale to extend.");
7593 int EltBits = VT.getSizeInBits() / NumElements;
7594 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
7595 "Only 8, 16, and 32 bit elements can be extended.");
7596 assert(Scale * EltBits <= 64 && "Cannot zero extend past 64 bits.");
7598 // Found a valid zext mask! Try various lowering strategies based on the
7599 // input type and available ISA extensions.
7600 if (Subtarget->hasSSE41()) {
7601 MVT InputVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits), NumElements);
7602 MVT ExtVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits * Scale),
7603 NumElements / Scale);
7604 InputV = DAG.getNode(ISD::BITCAST, DL, InputVT, InputV);
7605 return DAG.getNode(ISD::BITCAST, DL, VT,
7606 DAG.getNode(X86ISD::VZEXT, DL, ExtVT, InputV));
7609 // For any extends we can cheat for larger element sizes and use shuffle
7610 // instructions that can fold with a load and/or copy.
7611 if (AnyExt && EltBits == 32) {
7612 int PSHUFDMask[4] = {0, -1, 1, -1};
7614 ISD::BITCAST, DL, VT,
7615 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
7616 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, InputV),
7617 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
7619 if (AnyExt && EltBits == 16 && Scale > 2) {
7620 int PSHUFDMask[4] = {0, -1, 0, -1};
7621 InputV = DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
7622 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, InputV),
7623 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG));
7624 int PSHUFHWMask[4] = {1, -1, -1, -1};
7626 ISD::BITCAST, DL, VT,
7627 DAG.getNode(X86ISD::PSHUFHW, DL, MVT::v8i16,
7628 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, InputV),
7629 getV4X86ShuffleImm8ForMask(PSHUFHWMask, DAG)));
7632 // If this would require more than 2 unpack instructions to expand, use
7633 // pshufb when available. We can only use more than 2 unpack instructions
7634 // when zero extending i8 elements which also makes it easier to use pshufb.
7635 if (Scale > 4 && EltBits == 8 && Subtarget->hasSSSE3()) {
7636 assert(NumElements == 16 && "Unexpected byte vector width!");
7637 SDValue PSHUFBMask[16];
7638 for (int i = 0; i < 16; ++i)
7640 DAG.getConstant((i % Scale == 0) ? i / Scale : 0x80, MVT::i8);
7641 InputV = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, InputV);
7642 return DAG.getNode(ISD::BITCAST, DL, VT,
7643 DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, InputV,
7644 DAG.getNode(ISD::BUILD_VECTOR, DL,
7645 MVT::v16i8, PSHUFBMask)));
7648 // Otherwise emit a sequence of unpacks.
7650 MVT InputVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits), NumElements);
7651 SDValue Ext = AnyExt ? DAG.getUNDEF(InputVT)
7652 : getZeroVector(InputVT, Subtarget, DAG, DL);
7653 InputV = DAG.getNode(ISD::BITCAST, DL, InputVT, InputV);
7654 InputV = DAG.getNode(X86ISD::UNPCKL, DL, InputVT, InputV, Ext);
7658 } while (Scale > 1);
7659 return DAG.getNode(ISD::BITCAST, DL, VT, InputV);
7662 /// \brief Try to lower a vector shuffle as a zero extension on any micrarch.
7664 /// This routine will try to do everything in its power to cleverly lower
7665 /// a shuffle which happens to match the pattern of a zero extend. It doesn't
7666 /// check for the profitability of this lowering, it tries to aggressively
7667 /// match this pattern. It will use all of the micro-architectural details it
7668 /// can to emit an efficient lowering. It handles both blends with all-zero
7669 /// inputs to explicitly zero-extend and undef-lanes (sometimes undef due to
7670 /// masking out later).
7672 /// The reason we have dedicated lowering for zext-style shuffles is that they
7673 /// are both incredibly common and often quite performance sensitive.
7674 static SDValue lowerVectorShuffleAsZeroOrAnyExtend(
7675 SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
7676 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7677 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7679 int Bits = VT.getSizeInBits();
7680 int NumElements = Mask.size();
7682 // Define a helper function to check a particular ext-scale and lower to it if
7684 auto Lower = [&](int Scale) -> SDValue {
7687 for (int i = 0; i < NumElements; ++i) {
7689 continue; // Valid anywhere but doesn't tell us anything.
7690 if (i % Scale != 0) {
7691 // Each of the extend elements needs to be zeroable.
7695 // We no lorger are in the anyext case.
7700 // Each of the base elements needs to be consecutive indices into the
7701 // same input vector.
7702 SDValue V = Mask[i] < NumElements ? V1 : V2;
7705 else if (InputV != V)
7706 return SDValue(); // Flip-flopping inputs.
7708 if (Mask[i] % NumElements != i / Scale)
7709 return SDValue(); // Non-consecutive strided elemenst.
7712 // If we fail to find an input, we have a zero-shuffle which should always
7713 // have already been handled.
7714 // FIXME: Maybe handle this here in case during blending we end up with one?
7718 return lowerVectorShuffleAsSpecificZeroOrAnyExtend(
7719 DL, VT, NumElements, Scale, AnyExt, InputV, Subtarget, DAG);
7722 // The widest scale possible for extending is to a 64-bit integer.
7723 assert(Bits % 64 == 0 &&
7724 "The number of bits in a vector must be divisible by 64 on x86!");
7725 int NumExtElements = Bits / 64;
7727 // Each iteration, try extending the elements half as much, but into twice as
7729 for (; NumExtElements < NumElements; NumExtElements *= 2) {
7730 assert(NumElements % NumExtElements == 0 &&
7731 "The input vector size must be divisble by the extended size.");
7732 if (SDValue V = Lower(NumElements / NumExtElements))
7736 // No viable ext lowering found.
7740 /// \brief Try to lower insertion of a single element into a zero vector.
7742 /// This is a common pattern that we have especially efficient patterns to lower
7743 /// across all subtarget feature sets.
7744 static SDValue lowerVectorShuffleAsElementInsertion(
7745 MVT VT, SDLoc DL, SDValue V1, SDValue V2, ArrayRef<int> Mask,
7746 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7747 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7749 int V2Index = std::find_if(Mask.begin(), Mask.end(),
7750 [&Mask](int M) { return M >= (int)Mask.size(); }) -
7752 if (Mask.size() == 2) {
7753 if (!Zeroable[V2Index ^ 1]) {
7754 // For 2-wide masks we may be able to just invert the inputs. We use an xor
7755 // with 2 to flip from {2,3} to {0,1} and vice versa.
7756 int InverseMask[2] = {Mask[0] < 0 ? -1 : (Mask[0] ^ 2),
7757 Mask[1] < 0 ? -1 : (Mask[1] ^ 2)};
7758 if (Zeroable[V2Index])
7759 return lowerVectorShuffleAsElementInsertion(VT, DL, V2, V1, InverseMask,
7765 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7766 if (i != V2Index && !Zeroable[i])
7767 return SDValue(); // Not inserting into a zero vector.
7770 // Step over any bitcasts on either input so we can scan the actual
7771 // BUILD_VECTOR nodes.
7772 while (V1.getOpcode() == ISD::BITCAST)
7773 V1 = V1.getOperand(0);
7774 while (V2.getOpcode() == ISD::BITCAST)
7775 V2 = V2.getOperand(0);
7777 // Check for a single input from a SCALAR_TO_VECTOR node.
7778 // FIXME: All of this should be canonicalized into INSERT_VECTOR_ELT and
7779 // all the smarts here sunk into that routine. However, the current
7780 // lowering of BUILD_VECTOR makes that nearly impossible until the old
7781 // vector shuffle lowering is dead.
7782 if (!((V2.getOpcode() == ISD::SCALAR_TO_VECTOR &&
7783 Mask[V2Index] == (int)Mask.size()) ||
7784 V2.getOpcode() == ISD::BUILD_VECTOR))
7787 SDValue V2S = V2.getOperand(Mask[V2Index] - Mask.size());
7789 // First, we need to zext the scalar if it is smaller than an i32.
7791 MVT EltVT = VT.getVectorElementType();
7792 V2S = DAG.getNode(ISD::BITCAST, DL, EltVT, V2S);
7793 if (EltVT == MVT::i8 || EltVT == MVT::i16) {
7794 // Zero-extend directly to i32.
7796 V2S = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, V2S);
7799 V2 = DAG.getNode(X86ISD::VZEXT_MOVL, DL, ExtVT,
7800 DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, ExtVT, V2S));
7802 V2 = DAG.getNode(ISD::BITCAST, DL, VT, V2);
7805 // If we have 4 or fewer lanes we can cheaply shuffle the element into
7806 // the desired position. Otherwise it is more efficient to do a vector
7807 // shift left. We know that we can do a vector shift left because all
7808 // the inputs are zero.
7809 if (VT.isFloatingPoint() || VT.getVectorNumElements() <= 4) {
7810 SmallVector<int, 4> V2Shuffle(Mask.size(), 1);
7811 V2Shuffle[V2Index] = 0;
7812 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Shuffle);
7814 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, V2);
7816 X86ISD::VSHLDQ, DL, MVT::v2i64, V2,
7818 V2Index * EltVT.getSizeInBits(),
7819 DAG.getTargetLoweringInfo().getScalarShiftAmountTy(MVT::v2i64)));
7820 V2 = DAG.getNode(ISD::BITCAST, DL, VT, V2);
7826 /// \brief Handle lowering of 2-lane 64-bit floating point shuffles.
7828 /// This is the basis function for the 2-lane 64-bit shuffles as we have full
7829 /// support for floating point shuffles but not integer shuffles. These
7830 /// instructions will incur a domain crossing penalty on some chips though so
7831 /// it is better to avoid lowering through this for integer vectors where
7833 static SDValue lowerV2F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
7834 const X86Subtarget *Subtarget,
7835 SelectionDAG &DAG) {
7837 assert(Op.getSimpleValueType() == MVT::v2f64 && "Bad shuffle type!");
7838 assert(V1.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
7839 assert(V2.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
7840 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7841 ArrayRef<int> Mask = SVOp->getMask();
7842 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
7844 if (isSingleInputShuffleMask(Mask)) {
7845 // Straight shuffle of a single input vector. Simulate this by using the
7846 // single input as both of the "inputs" to this instruction..
7847 unsigned SHUFPDMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1);
7849 if (Subtarget->hasAVX()) {
7850 // If we have AVX, we can use VPERMILPS which will allow folding a load
7851 // into the shuffle.
7852 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v2f64, V1,
7853 DAG.getConstant(SHUFPDMask, MVT::i8));
7856 return DAG.getNode(X86ISD::SHUFP, SDLoc(Op), MVT::v2f64, V1, V1,
7857 DAG.getConstant(SHUFPDMask, MVT::i8));
7859 assert(Mask[0] >= 0 && Mask[0] < 2 && "Non-canonicalized blend!");
7860 assert(Mask[1] >= 2 && "Non-canonicalized blend!");
7862 // Use dedicated unpack instructions for masks that match their pattern.
7863 if (isShuffleEquivalent(Mask, 0, 2))
7864 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2f64, V1, V2);
7865 if (isShuffleEquivalent(Mask, 1, 3))
7866 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v2f64, V1, V2);
7868 // If we have a single input, insert that into V1 if we can do so cheaply.
7869 if ((Mask[0] >= 2) + (Mask[1] >= 2) == 1)
7870 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
7871 MVT::v2f64, DL, V1, V2, Mask, Subtarget, DAG))
7874 if (Subtarget->hasSSE41())
7875 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v2f64, V1, V2, Mask,
7879 unsigned SHUFPDMask = (Mask[0] == 1) | (((Mask[1] - 2) == 1) << 1);
7880 return DAG.getNode(X86ISD::SHUFP, SDLoc(Op), MVT::v2f64, V1, V2,
7881 DAG.getConstant(SHUFPDMask, MVT::i8));
7884 /// \brief Handle lowering of 2-lane 64-bit integer shuffles.
7886 /// Tries to lower a 2-lane 64-bit shuffle using shuffle operations provided by
7887 /// the integer unit to minimize domain crossing penalties. However, for blends
7888 /// it falls back to the floating point shuffle operation with appropriate bit
7890 static SDValue lowerV2I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
7891 const X86Subtarget *Subtarget,
7892 SelectionDAG &DAG) {
7894 assert(Op.getSimpleValueType() == MVT::v2i64 && "Bad shuffle type!");
7895 assert(V1.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
7896 assert(V2.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
7897 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7898 ArrayRef<int> Mask = SVOp->getMask();
7899 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
7901 if (isSingleInputShuffleMask(Mask)) {
7902 // Straight shuffle of a single input vector. For everything from SSE2
7903 // onward this has a single fast instruction with no scary immediates.
7904 // We have to map the mask as it is actually a v4i32 shuffle instruction.
7905 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V1);
7906 int WidenedMask[4] = {
7907 std::max(Mask[0], 0) * 2, std::max(Mask[0], 0) * 2 + 1,
7908 std::max(Mask[1], 0) * 2, std::max(Mask[1], 0) * 2 + 1};
7910 ISD::BITCAST, DL, MVT::v2i64,
7911 DAG.getNode(X86ISD::PSHUFD, SDLoc(Op), MVT::v4i32, V1,
7912 getV4X86ShuffleImm8ForMask(WidenedMask, DAG)));
7915 // Use dedicated unpack instructions for masks that match their pattern.
7916 if (isShuffleEquivalent(Mask, 0, 2))
7917 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2i64, V1, V2);
7918 if (isShuffleEquivalent(Mask, 1, 3))
7919 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v2i64, V1, V2);
7921 // If we have a single input from V2 insert that into V1 if we can do so
7923 if ((Mask[0] >= 2) + (Mask[1] >= 2) == 1)
7924 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
7925 MVT::v2i64, DL, V1, V2, Mask, Subtarget, DAG))
7928 if (Subtarget->hasSSE41())
7929 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v2i64, V1, V2, Mask,
7933 // Try to use rotation instructions if available.
7934 if (Subtarget->hasSSSE3())
7935 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
7936 DL, MVT::v2i64, V1, V2, Mask, DAG))
7939 // We implement this with SHUFPD which is pretty lame because it will likely
7940 // incur 2 cycles of stall for integer vectors on Nehalem and older chips.
7941 // However, all the alternatives are still more cycles and newer chips don't
7942 // have this problem. It would be really nice if x86 had better shuffles here.
7943 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v2f64, V1);
7944 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v2f64, V2);
7945 return DAG.getNode(ISD::BITCAST, DL, MVT::v2i64,
7946 DAG.getVectorShuffle(MVT::v2f64, DL, V1, V2, Mask));
7949 /// \brief Lower a vector shuffle using the SHUFPS instruction.
7951 /// This is a helper routine dedicated to lowering vector shuffles using SHUFPS.
7952 /// It makes no assumptions about whether this is the *best* lowering, it simply
7954 static SDValue lowerVectorShuffleWithSHUFPS(SDLoc DL, MVT VT,
7955 ArrayRef<int> Mask, SDValue V1,
7956 SDValue V2, SelectionDAG &DAG) {
7957 SDValue LowV = V1, HighV = V2;
7958 int NewMask[4] = {Mask[0], Mask[1], Mask[2], Mask[3]};
7961 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
7963 if (NumV2Elements == 1) {
7965 std::find_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; }) -
7968 // Compute the index adjacent to V2Index and in the same half by toggling
7970 int V2AdjIndex = V2Index ^ 1;
7972 if (Mask[V2AdjIndex] == -1) {
7973 // Handles all the cases where we have a single V2 element and an undef.
7974 // This will only ever happen in the high lanes because we commute the
7975 // vector otherwise.
7977 std::swap(LowV, HighV);
7978 NewMask[V2Index] -= 4;
7980 // Handle the case where the V2 element ends up adjacent to a V1 element.
7981 // To make this work, blend them together as the first step.
7982 int V1Index = V2AdjIndex;
7983 int BlendMask[4] = {Mask[V2Index] - 4, 0, Mask[V1Index], 0};
7984 V2 = DAG.getNode(X86ISD::SHUFP, DL, VT, V2, V1,
7985 getV4X86ShuffleImm8ForMask(BlendMask, DAG));
7987 // Now proceed to reconstruct the final blend as we have the necessary
7988 // high or low half formed.
7995 NewMask[V1Index] = 2; // We put the V1 element in V2[2].
7996 NewMask[V2Index] = 0; // We shifted the V2 element into V2[0].
7998 } else if (NumV2Elements == 2) {
7999 if (Mask[0] < 4 && Mask[1] < 4) {
8000 // Handle the easy case where we have V1 in the low lanes and V2 in the
8004 } else if (Mask[2] < 4 && Mask[3] < 4) {
8005 // We also handle the reversed case because this utility may get called
8006 // when we detect a SHUFPS pattern but can't easily commute the shuffle to
8007 // arrange things in the right direction.
8013 // We have a mixture of V1 and V2 in both low and high lanes. Rather than
8014 // trying to place elements directly, just blend them and set up the final
8015 // shuffle to place them.
8017 // The first two blend mask elements are for V1, the second two are for
8019 int BlendMask[4] = {Mask[0] < 4 ? Mask[0] : Mask[1],
8020 Mask[2] < 4 ? Mask[2] : Mask[3],
8021 (Mask[0] >= 4 ? Mask[0] : Mask[1]) - 4,
8022 (Mask[2] >= 4 ? Mask[2] : Mask[3]) - 4};
8023 V1 = DAG.getNode(X86ISD::SHUFP, DL, VT, V1, V2,
8024 getV4X86ShuffleImm8ForMask(BlendMask, DAG));
8026 // Now we do a normal shuffle of V1 by giving V1 as both operands to
8029 NewMask[0] = Mask[0] < 4 ? 0 : 2;
8030 NewMask[1] = Mask[0] < 4 ? 2 : 0;
8031 NewMask[2] = Mask[2] < 4 ? 1 : 3;
8032 NewMask[3] = Mask[2] < 4 ? 3 : 1;
8035 return DAG.getNode(X86ISD::SHUFP, DL, VT, LowV, HighV,
8036 getV4X86ShuffleImm8ForMask(NewMask, DAG));
8039 /// \brief Lower 4-lane 32-bit floating point shuffles.
8041 /// Uses instructions exclusively from the floating point unit to minimize
8042 /// domain crossing penalties, as these are sufficient to implement all v4f32
8044 static SDValue lowerV4F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8045 const X86Subtarget *Subtarget,
8046 SelectionDAG &DAG) {
8048 assert(Op.getSimpleValueType() == MVT::v4f32 && "Bad shuffle type!");
8049 assert(V1.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
8050 assert(V2.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
8051 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8052 ArrayRef<int> Mask = SVOp->getMask();
8053 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
8056 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
8058 if (NumV2Elements == 0) {
8059 if (Subtarget->hasAVX()) {
8060 // If we have AVX, we can use VPERMILPS which will allow folding a load
8061 // into the shuffle.
8062 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v4f32, V1,
8063 getV4X86ShuffleImm8ForMask(Mask, DAG));
8066 // Otherwise, use a straight shuffle of a single input vector. We pass the
8067 // input vector to both operands to simulate this with a SHUFPS.
8068 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f32, V1, V1,
8069 getV4X86ShuffleImm8ForMask(Mask, DAG));
8072 // Use dedicated unpack instructions for masks that match their pattern.
8073 if (isShuffleEquivalent(Mask, 0, 4, 1, 5))
8074 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f32, V1, V2);
8075 if (isShuffleEquivalent(Mask, 2, 6, 3, 7))
8076 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f32, V1, V2);
8078 // There are special ways we can lower some single-element blends. However, we
8079 // have custom ways we can lower more complex single-element blends below that
8080 // we defer to if both this and BLENDPS fail to match, so restrict this to
8081 // when the V2 input is targeting element 0 of the mask -- that is the fast
8083 if (NumV2Elements == 1 && Mask[0] >= 4)
8084 if (SDValue V = lowerVectorShuffleAsElementInsertion(MVT::v4f32, DL, V1, V2,
8085 Mask, Subtarget, DAG))
8088 if (Subtarget->hasSSE41())
8089 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4f32, V1, V2, Mask,
8093 // Check for whether we can use INSERTPS to perform the blend. We only use
8094 // INSERTPS when the V1 elements are already in the correct locations
8095 // because otherwise we can just always use two SHUFPS instructions which
8096 // are much smaller to encode than a SHUFPS and an INSERTPS.
8097 if (NumV2Elements == 1 && Subtarget->hasSSE41()) {
8099 std::find_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; }) -
8102 // When using INSERTPS we can zero any lane of the destination. Collect
8103 // the zero inputs into a mask and drop them from the lanes of V1 which
8104 // actually need to be present as inputs to the INSERTPS.
8105 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
8107 // Synthesize a shuffle mask for the non-zero and non-v2 inputs.
8108 bool InsertNeedsShuffle = false;
8110 for (int i = 0; i < 4; ++i)
8114 } else if (Mask[i] != i) {
8115 InsertNeedsShuffle = true;
8120 // We don't want to use INSERTPS or other insertion techniques if it will
8121 // require shuffling anyways.
8122 if (!InsertNeedsShuffle) {
8123 // If all of V1 is zeroable, replace it with undef.
8124 if ((ZMask | 1 << V2Index) == 0xF)
8125 V1 = DAG.getUNDEF(MVT::v4f32);
8127 unsigned InsertPSMask = (Mask[V2Index] - 4) << 6 | V2Index << 4 | ZMask;
8128 assert((InsertPSMask & ~0xFFu) == 0 && "Invalid mask!");
8130 // Insert the V2 element into the desired position.
8131 return DAG.getNode(X86ISD::INSERTPS, DL, MVT::v4f32, V1, V2,
8132 DAG.getConstant(InsertPSMask, MVT::i8));
8136 // Otherwise fall back to a SHUFPS lowering strategy.
8137 return lowerVectorShuffleWithSHUFPS(DL, MVT::v4f32, Mask, V1, V2, DAG);
8140 /// \brief Lower 4-lane i32 vector shuffles.
8142 /// We try to handle these with integer-domain shuffles where we can, but for
8143 /// blends we use the floating point domain blend instructions.
8144 static SDValue lowerV4I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8145 const X86Subtarget *Subtarget,
8146 SelectionDAG &DAG) {
8148 assert(Op.getSimpleValueType() == MVT::v4i32 && "Bad shuffle type!");
8149 assert(V1.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
8150 assert(V2.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
8151 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8152 ArrayRef<int> Mask = SVOp->getMask();
8153 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
8156 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
8158 if (NumV2Elements == 0) {
8159 // Straight shuffle of a single input vector. For everything from SSE2
8160 // onward this has a single fast instruction with no scary immediates.
8161 // We coerce the shuffle pattern to be compatible with UNPCK instructions
8162 // but we aren't actually going to use the UNPCK instruction because doing
8163 // so prevents folding a load into this instruction or making a copy.
8164 const int UnpackLoMask[] = {0, 0, 1, 1};
8165 const int UnpackHiMask[] = {2, 2, 3, 3};
8166 if (isShuffleEquivalent(Mask, 0, 0, 1, 1))
8167 Mask = UnpackLoMask;
8168 else if (isShuffleEquivalent(Mask, 2, 2, 3, 3))
8169 Mask = UnpackHiMask;
8171 return DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V1,
8172 getV4X86ShuffleImm8ForMask(Mask, DAG));
8175 // Whenever we can lower this as a zext, that instruction is strictly faster
8176 // than any alternative.
8177 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v4i32, V1, V2,
8178 Mask, Subtarget, DAG))
8181 // Use dedicated unpack instructions for masks that match their pattern.
8182 if (isShuffleEquivalent(Mask, 0, 4, 1, 5))
8183 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i32, V1, V2);
8184 if (isShuffleEquivalent(Mask, 2, 6, 3, 7))
8185 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i32, V1, V2);
8187 // There are special ways we can lower some single-element blends.
8188 if (NumV2Elements == 1)
8189 if (SDValue V = lowerVectorShuffleAsElementInsertion(MVT::v4i32, DL, V1, V2,
8190 Mask, Subtarget, DAG))
8193 if (Subtarget->hasSSE41())
8194 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4i32, V1, V2, Mask,
8198 // Try to use rotation instructions if available.
8199 if (Subtarget->hasSSSE3())
8200 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8201 DL, MVT::v4i32, V1, V2, Mask, DAG))
8204 // We implement this with SHUFPS because it can blend from two vectors.
8205 // Because we're going to eventually use SHUFPS, we use SHUFPS even to build
8206 // up the inputs, bypassing domain shift penalties that we would encur if we
8207 // directly used PSHUFD on Nehalem and older. For newer chips, this isn't
8209 return DAG.getNode(ISD::BITCAST, DL, MVT::v4i32,
8210 DAG.getVectorShuffle(
8212 DAG.getNode(ISD::BITCAST, DL, MVT::v4f32, V1),
8213 DAG.getNode(ISD::BITCAST, DL, MVT::v4f32, V2), Mask));
8216 /// \brief Lowering of single-input v8i16 shuffles is the cornerstone of SSE2
8217 /// shuffle lowering, and the most complex part.
8219 /// The lowering strategy is to try to form pairs of input lanes which are
8220 /// targeted at the same half of the final vector, and then use a dword shuffle
8221 /// to place them onto the right half, and finally unpack the paired lanes into
8222 /// their final position.
8224 /// The exact breakdown of how to form these dword pairs and align them on the
8225 /// correct sides is really tricky. See the comments within the function for
8226 /// more of the details.
8227 static SDValue lowerV8I16SingleInputVectorShuffle(
8228 SDLoc DL, SDValue V, MutableArrayRef<int> Mask,
8229 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
8230 assert(V.getSimpleValueType() == MVT::v8i16 && "Bad input type!");
8231 MutableArrayRef<int> LoMask = Mask.slice(0, 4);
8232 MutableArrayRef<int> HiMask = Mask.slice(4, 4);
8234 SmallVector<int, 4> LoInputs;
8235 std::copy_if(LoMask.begin(), LoMask.end(), std::back_inserter(LoInputs),
8236 [](int M) { return M >= 0; });
8237 std::sort(LoInputs.begin(), LoInputs.end());
8238 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()), LoInputs.end());
8239 SmallVector<int, 4> HiInputs;
8240 std::copy_if(HiMask.begin(), HiMask.end(), std::back_inserter(HiInputs),
8241 [](int M) { return M >= 0; });
8242 std::sort(HiInputs.begin(), HiInputs.end());
8243 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()), HiInputs.end());
8245 std::lower_bound(LoInputs.begin(), LoInputs.end(), 4) - LoInputs.begin();
8246 int NumHToL = LoInputs.size() - NumLToL;
8248 std::lower_bound(HiInputs.begin(), HiInputs.end(), 4) - HiInputs.begin();
8249 int NumHToH = HiInputs.size() - NumLToH;
8250 MutableArrayRef<int> LToLInputs(LoInputs.data(), NumLToL);
8251 MutableArrayRef<int> LToHInputs(HiInputs.data(), NumLToH);
8252 MutableArrayRef<int> HToLInputs(LoInputs.data() + NumLToL, NumHToL);
8253 MutableArrayRef<int> HToHInputs(HiInputs.data() + NumLToH, NumHToH);
8255 // Use dedicated unpack instructions for masks that match their pattern.
8256 if (isShuffleEquivalent(Mask, 0, 0, 1, 1, 2, 2, 3, 3))
8257 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i16, V, V);
8258 if (isShuffleEquivalent(Mask, 4, 4, 5, 5, 6, 6, 7, 7))
8259 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i16, V, V);
8261 // Try to use rotation instructions if available.
8262 if (Subtarget->hasSSSE3())
8263 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8264 DL, MVT::v8i16, V, V, Mask, DAG))
8267 // Simplify the 1-into-3 and 3-into-1 cases with a single pshufd. For all
8268 // such inputs we can swap two of the dwords across the half mark and end up
8269 // with <=2 inputs to each half in each half. Once there, we can fall through
8270 // to the generic code below. For example:
8272 // Input: [a, b, c, d, e, f, g, h] -PSHUFD[0,2,1,3]-> [a, b, e, f, c, d, g, h]
8273 // Mask: [0, 1, 2, 7, 4, 5, 6, 3] -----------------> [0, 1, 4, 7, 2, 3, 6, 5]
8275 // However in some very rare cases we have a 1-into-3 or 3-into-1 on one half
8276 // and an existing 2-into-2 on the other half. In this case we may have to
8277 // pre-shuffle the 2-into-2 half to avoid turning it into a 3-into-1 or
8278 // 1-into-3 which could cause us to cycle endlessly fixing each side in turn.
8279 // Fortunately, we don't have to handle anything but a 2-into-2 pattern
8280 // because any other situation (including a 3-into-1 or 1-into-3 in the other
8281 // half than the one we target for fixing) will be fixed when we re-enter this
8282 // path. We will also combine away any sequence of PSHUFD instructions that
8283 // result into a single instruction. Here is an example of the tricky case:
8285 // Input: [a, b, c, d, e, f, g, h] -PSHUFD[0,2,1,3]-> [a, b, e, f, c, d, g, h]
8286 // Mask: [3, 7, 1, 0, 2, 7, 3, 5] -THIS-IS-BAD!!!!-> [5, 7, 1, 0, 4, 7, 5, 3]
8288 // This now has a 1-into-3 in the high half! Instead, we do two shuffles:
8290 // Input: [a, b, c, d, e, f, g, h] PSHUFHW[0,2,1,3]-> [a, b, c, d, e, g, f, h]
8291 // Mask: [3, 7, 1, 0, 2, 7, 3, 5] -----------------> [3, 7, 1, 0, 2, 7, 3, 6]
8293 // Input: [a, b, c, d, e, g, f, h] -PSHUFD[0,2,1,3]-> [a, b, e, g, c, d, f, h]
8294 // Mask: [3, 7, 1, 0, 2, 7, 3, 6] -----------------> [5, 7, 1, 0, 4, 7, 5, 6]
8296 // The result is fine to be handled by the generic logic.
8297 auto balanceSides = [&](ArrayRef<int> AToAInputs, ArrayRef<int> BToAInputs,
8298 ArrayRef<int> BToBInputs, ArrayRef<int> AToBInputs,
8299 int AOffset, int BOffset) {
8300 assert((AToAInputs.size() == 3 || AToAInputs.size() == 1) &&
8301 "Must call this with A having 3 or 1 inputs from the A half.");
8302 assert((BToAInputs.size() == 1 || BToAInputs.size() == 3) &&
8303 "Must call this with B having 1 or 3 inputs from the B half.");
8304 assert(AToAInputs.size() + BToAInputs.size() == 4 &&
8305 "Must call this with either 3:1 or 1:3 inputs (summing to 4).");
8307 // Compute the index of dword with only one word among the three inputs in
8308 // a half by taking the sum of the half with three inputs and subtracting
8309 // the sum of the actual three inputs. The difference is the remaining
8312 int &TripleDWord = AToAInputs.size() == 3 ? ADWord : BDWord;
8313 int &OneInputDWord = AToAInputs.size() == 3 ? BDWord : ADWord;
8314 int TripleInputOffset = AToAInputs.size() == 3 ? AOffset : BOffset;
8315 ArrayRef<int> TripleInputs = AToAInputs.size() == 3 ? AToAInputs : BToAInputs;
8316 int OneInput = AToAInputs.size() == 3 ? BToAInputs[0] : AToAInputs[0];
8317 int TripleInputSum = 0 + 1 + 2 + 3 + (4 * TripleInputOffset);
8318 int TripleNonInputIdx =
8319 TripleInputSum - std::accumulate(TripleInputs.begin(), TripleInputs.end(), 0);
8320 TripleDWord = TripleNonInputIdx / 2;
8322 // We use xor with one to compute the adjacent DWord to whichever one the
8324 OneInputDWord = (OneInput / 2) ^ 1;
8326 // Check for one tricky case: We're fixing a 3<-1 or a 1<-3 shuffle for AToA
8327 // and BToA inputs. If there is also such a problem with the BToB and AToB
8328 // inputs, we don't try to fix it necessarily -- we'll recurse and see it in
8329 // the next pass. However, if we have a 2<-2 in the BToB and AToB inputs, it
8330 // is essential that we don't *create* a 3<-1 as then we might oscillate.
8331 if (BToBInputs.size() == 2 && AToBInputs.size() == 2) {
8332 // Compute how many inputs will be flipped by swapping these DWords. We
8334 // to balance this to ensure we don't form a 3-1 shuffle in the other
8336 int NumFlippedAToBInputs =
8337 std::count(AToBInputs.begin(), AToBInputs.end(), 2 * ADWord) +
8338 std::count(AToBInputs.begin(), AToBInputs.end(), 2 * ADWord + 1);
8339 int NumFlippedBToBInputs =
8340 std::count(BToBInputs.begin(), BToBInputs.end(), 2 * BDWord) +
8341 std::count(BToBInputs.begin(), BToBInputs.end(), 2 * BDWord + 1);
8342 if ((NumFlippedAToBInputs == 1 &&
8343 (NumFlippedBToBInputs == 0 || NumFlippedBToBInputs == 2)) ||
8344 (NumFlippedBToBInputs == 1 &&
8345 (NumFlippedAToBInputs == 0 || NumFlippedAToBInputs == 2))) {
8346 // We choose whether to fix the A half or B half based on whether that
8347 // half has zero flipped inputs. At zero, we may not be able to fix it
8348 // with that half. We also bias towards fixing the B half because that
8349 // will more commonly be the high half, and we have to bias one way.
8350 auto FixFlippedInputs = [&V, &DL, &Mask, &DAG](int PinnedIdx, int DWord,
8351 ArrayRef<int> Inputs) {
8352 int FixIdx = PinnedIdx ^ 1; // The adjacent slot to the pinned slot.
8353 bool IsFixIdxInput = std::find(Inputs.begin(), Inputs.end(),
8354 PinnedIdx ^ 1) != Inputs.end();
8355 // Determine whether the free index is in the flipped dword or the
8356 // unflipped dword based on where the pinned index is. We use this bit
8357 // in an xor to conditionally select the adjacent dword.
8358 int FixFreeIdx = 2 * (DWord ^ (PinnedIdx / 2 == DWord));
8359 bool IsFixFreeIdxInput = std::find(Inputs.begin(), Inputs.end(),
8360 FixFreeIdx) != Inputs.end();
8361 if (IsFixIdxInput == IsFixFreeIdxInput)
8363 IsFixFreeIdxInput = std::find(Inputs.begin(), Inputs.end(),
8364 FixFreeIdx) != Inputs.end();
8365 assert(IsFixIdxInput != IsFixFreeIdxInput &&
8366 "We need to be changing the number of flipped inputs!");
8367 int PSHUFHalfMask[] = {0, 1, 2, 3};
8368 std::swap(PSHUFHalfMask[FixFreeIdx % 4], PSHUFHalfMask[FixIdx % 4]);
8369 V = DAG.getNode(FixIdx < 4 ? X86ISD::PSHUFLW : X86ISD::PSHUFHW, DL,
8371 getV4X86ShuffleImm8ForMask(PSHUFHalfMask, DAG));
8374 if (M != -1 && M == FixIdx)
8376 else if (M != -1 && M == FixFreeIdx)
8379 if (NumFlippedBToBInputs != 0) {
8381 BToAInputs.size() == 3 ? TripleNonInputIdx : OneInput;
8382 FixFlippedInputs(BPinnedIdx, BDWord, BToBInputs);
8384 assert(NumFlippedAToBInputs != 0 && "Impossible given predicates!");
8386 AToAInputs.size() == 3 ? TripleNonInputIdx : OneInput;
8387 FixFlippedInputs(APinnedIdx, ADWord, AToBInputs);
8392 int PSHUFDMask[] = {0, 1, 2, 3};
8393 PSHUFDMask[ADWord] = BDWord;
8394 PSHUFDMask[BDWord] = ADWord;
8395 V = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
8396 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
8397 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V),
8398 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
8400 // Adjust the mask to match the new locations of A and B.
8402 if (M != -1 && M/2 == ADWord)
8403 M = 2 * BDWord + M % 2;
8404 else if (M != -1 && M/2 == BDWord)
8405 M = 2 * ADWord + M % 2;
8407 // Recurse back into this routine to re-compute state now that this isn't
8408 // a 3 and 1 problem.
8409 return DAG.getVectorShuffle(MVT::v8i16, DL, V, DAG.getUNDEF(MVT::v8i16),
8412 if ((NumLToL == 3 && NumHToL == 1) || (NumLToL == 1 && NumHToL == 3))
8413 return balanceSides(LToLInputs, HToLInputs, HToHInputs, LToHInputs, 0, 4);
8414 else if ((NumHToH == 3 && NumLToH == 1) || (NumHToH == 1 && NumLToH == 3))
8415 return balanceSides(HToHInputs, LToHInputs, LToLInputs, HToLInputs, 4, 0);
8417 // At this point there are at most two inputs to the low and high halves from
8418 // each half. That means the inputs can always be grouped into dwords and
8419 // those dwords can then be moved to the correct half with a dword shuffle.
8420 // We use at most one low and one high word shuffle to collect these paired
8421 // inputs into dwords, and finally a dword shuffle to place them.
8422 int PSHUFLMask[4] = {-1, -1, -1, -1};
8423 int PSHUFHMask[4] = {-1, -1, -1, -1};
8424 int PSHUFDMask[4] = {-1, -1, -1, -1};
8426 // First fix the masks for all the inputs that are staying in their
8427 // original halves. This will then dictate the targets of the cross-half
8429 auto fixInPlaceInputs =
8430 [&PSHUFDMask](ArrayRef<int> InPlaceInputs, ArrayRef<int> IncomingInputs,
8431 MutableArrayRef<int> SourceHalfMask,
8432 MutableArrayRef<int> HalfMask, int HalfOffset) {
8433 if (InPlaceInputs.empty())
8435 if (InPlaceInputs.size() == 1) {
8436 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
8437 InPlaceInputs[0] - HalfOffset;
8438 PSHUFDMask[InPlaceInputs[0] / 2] = InPlaceInputs[0] / 2;
8441 if (IncomingInputs.empty()) {
8442 // Just fix all of the in place inputs.
8443 for (int Input : InPlaceInputs) {
8444 SourceHalfMask[Input - HalfOffset] = Input - HalfOffset;
8445 PSHUFDMask[Input / 2] = Input / 2;
8450 assert(InPlaceInputs.size() == 2 && "Cannot handle 3 or 4 inputs!");
8451 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
8452 InPlaceInputs[0] - HalfOffset;
8453 // Put the second input next to the first so that they are packed into
8454 // a dword. We find the adjacent index by toggling the low bit.
8455 int AdjIndex = InPlaceInputs[0] ^ 1;
8456 SourceHalfMask[AdjIndex - HalfOffset] = InPlaceInputs[1] - HalfOffset;
8457 std::replace(HalfMask.begin(), HalfMask.end(), InPlaceInputs[1], AdjIndex);
8458 PSHUFDMask[AdjIndex / 2] = AdjIndex / 2;
8460 fixInPlaceInputs(LToLInputs, HToLInputs, PSHUFLMask, LoMask, 0);
8461 fixInPlaceInputs(HToHInputs, LToHInputs, PSHUFHMask, HiMask, 4);
8463 // Now gather the cross-half inputs and place them into a free dword of
8464 // their target half.
8465 // FIXME: This operation could almost certainly be simplified dramatically to
8466 // look more like the 3-1 fixing operation.
8467 auto moveInputsToRightHalf = [&PSHUFDMask](
8468 MutableArrayRef<int> IncomingInputs, ArrayRef<int> ExistingInputs,
8469 MutableArrayRef<int> SourceHalfMask, MutableArrayRef<int> HalfMask,
8470 MutableArrayRef<int> FinalSourceHalfMask, int SourceOffset,
8472 auto isWordClobbered = [](ArrayRef<int> SourceHalfMask, int Word) {
8473 return SourceHalfMask[Word] != -1 && SourceHalfMask[Word] != Word;
8475 auto isDWordClobbered = [&isWordClobbered](ArrayRef<int> SourceHalfMask,
8477 int LowWord = Word & ~1;
8478 int HighWord = Word | 1;
8479 return isWordClobbered(SourceHalfMask, LowWord) ||
8480 isWordClobbered(SourceHalfMask, HighWord);
8483 if (IncomingInputs.empty())
8486 if (ExistingInputs.empty()) {
8487 // Map any dwords with inputs from them into the right half.
8488 for (int Input : IncomingInputs) {
8489 // If the source half mask maps over the inputs, turn those into
8490 // swaps and use the swapped lane.
8491 if (isWordClobbered(SourceHalfMask, Input - SourceOffset)) {
8492 if (SourceHalfMask[SourceHalfMask[Input - SourceOffset]] == -1) {
8493 SourceHalfMask[SourceHalfMask[Input - SourceOffset]] =
8494 Input - SourceOffset;
8495 // We have to swap the uses in our half mask in one sweep.
8496 for (int &M : HalfMask)
8497 if (M == SourceHalfMask[Input - SourceOffset] + SourceOffset)
8499 else if (M == Input)
8500 M = SourceHalfMask[Input - SourceOffset] + SourceOffset;
8502 assert(SourceHalfMask[SourceHalfMask[Input - SourceOffset]] ==
8503 Input - SourceOffset &&
8504 "Previous placement doesn't match!");
8506 // Note that this correctly re-maps both when we do a swap and when
8507 // we observe the other side of the swap above. We rely on that to
8508 // avoid swapping the members of the input list directly.
8509 Input = SourceHalfMask[Input - SourceOffset] + SourceOffset;
8512 // Map the input's dword into the correct half.
8513 if (PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] == -1)
8514 PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] = Input / 2;
8516 assert(PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] ==
8518 "Previous placement doesn't match!");
8521 // And just directly shift any other-half mask elements to be same-half
8522 // as we will have mirrored the dword containing the element into the
8523 // same position within that half.
8524 for (int &M : HalfMask)
8525 if (M >= SourceOffset && M < SourceOffset + 4) {
8526 M = M - SourceOffset + DestOffset;
8527 assert(M >= 0 && "This should never wrap below zero!");
8532 // Ensure we have the input in a viable dword of its current half. This
8533 // is particularly tricky because the original position may be clobbered
8534 // by inputs being moved and *staying* in that half.
8535 if (IncomingInputs.size() == 1) {
8536 if (isWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
8537 int InputFixed = std::find(std::begin(SourceHalfMask),
8538 std::end(SourceHalfMask), -1) -
8539 std::begin(SourceHalfMask) + SourceOffset;
8540 SourceHalfMask[InputFixed - SourceOffset] =
8541 IncomingInputs[0] - SourceOffset;
8542 std::replace(HalfMask.begin(), HalfMask.end(), IncomingInputs[0],
8544 IncomingInputs[0] = InputFixed;
8546 } else if (IncomingInputs.size() == 2) {
8547 if (IncomingInputs[0] / 2 != IncomingInputs[1] / 2 ||
8548 isDWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
8549 // We have two non-adjacent or clobbered inputs we need to extract from
8550 // the source half. To do this, we need to map them into some adjacent
8551 // dword slot in the source mask.
8552 int InputsFixed[2] = {IncomingInputs[0] - SourceOffset,
8553 IncomingInputs[1] - SourceOffset};
8555 // If there is a free slot in the source half mask adjacent to one of
8556 // the inputs, place the other input in it. We use (Index XOR 1) to
8557 // compute an adjacent index.
8558 if (!isWordClobbered(SourceHalfMask, InputsFixed[0]) &&
8559 SourceHalfMask[InputsFixed[0] ^ 1] == -1) {
8560 SourceHalfMask[InputsFixed[0]] = InputsFixed[0];
8561 SourceHalfMask[InputsFixed[0] ^ 1] = InputsFixed[1];
8562 InputsFixed[1] = InputsFixed[0] ^ 1;
8563 } else if (!isWordClobbered(SourceHalfMask, InputsFixed[1]) &&
8564 SourceHalfMask[InputsFixed[1] ^ 1] == -1) {
8565 SourceHalfMask[InputsFixed[1]] = InputsFixed[1];
8566 SourceHalfMask[InputsFixed[1] ^ 1] = InputsFixed[0];
8567 InputsFixed[0] = InputsFixed[1] ^ 1;
8568 } else if (SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1)] == -1 &&
8569 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1) + 1] == -1) {
8570 // The two inputs are in the same DWord but it is clobbered and the
8571 // adjacent DWord isn't used at all. Move both inputs to the free
8573 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1)] = InputsFixed[0];
8574 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1) + 1] = InputsFixed[1];
8575 InputsFixed[0] = 2 * ((InputsFixed[0] / 2) ^ 1);
8576 InputsFixed[1] = 2 * ((InputsFixed[0] / 2) ^ 1) + 1;
8578 // The only way we hit this point is if there is no clobbering
8579 // (because there are no off-half inputs to this half) and there is no
8580 // free slot adjacent to one of the inputs. In this case, we have to
8581 // swap an input with a non-input.
8582 for (int i = 0; i < 4; ++i)
8583 assert((SourceHalfMask[i] == -1 || SourceHalfMask[i] == i) &&
8584 "We can't handle any clobbers here!");
8585 assert(InputsFixed[1] != (InputsFixed[0] ^ 1) &&
8586 "Cannot have adjacent inputs here!");
8588 SourceHalfMask[InputsFixed[0] ^ 1] = InputsFixed[1];
8589 SourceHalfMask[InputsFixed[1]] = InputsFixed[0] ^ 1;
8591 // We also have to update the final source mask in this case because
8592 // it may need to undo the above swap.
8593 for (int &M : FinalSourceHalfMask)
8594 if (M == (InputsFixed[0] ^ 1) + SourceOffset)
8595 M = InputsFixed[1] + SourceOffset;
8596 else if (M == InputsFixed[1] + SourceOffset)
8597 M = (InputsFixed[0] ^ 1) + SourceOffset;
8599 InputsFixed[1] = InputsFixed[0] ^ 1;
8602 // Point everything at the fixed inputs.
8603 for (int &M : HalfMask)
8604 if (M == IncomingInputs[0])
8605 M = InputsFixed[0] + SourceOffset;
8606 else if (M == IncomingInputs[1])
8607 M = InputsFixed[1] + SourceOffset;
8609 IncomingInputs[0] = InputsFixed[0] + SourceOffset;
8610 IncomingInputs[1] = InputsFixed[1] + SourceOffset;
8613 llvm_unreachable("Unhandled input size!");
8616 // Now hoist the DWord down to the right half.
8617 int FreeDWord = (PSHUFDMask[DestOffset / 2] == -1 ? 0 : 1) + DestOffset / 2;
8618 assert(PSHUFDMask[FreeDWord] == -1 && "DWord not free");
8619 PSHUFDMask[FreeDWord] = IncomingInputs[0] / 2;
8620 for (int &M : HalfMask)
8621 for (int Input : IncomingInputs)
8623 M = FreeDWord * 2 + Input % 2;
8625 moveInputsToRightHalf(HToLInputs, LToLInputs, PSHUFHMask, LoMask, HiMask,
8626 /*SourceOffset*/ 4, /*DestOffset*/ 0);
8627 moveInputsToRightHalf(LToHInputs, HToHInputs, PSHUFLMask, HiMask, LoMask,
8628 /*SourceOffset*/ 0, /*DestOffset*/ 4);
8630 // Now enact all the shuffles we've computed to move the inputs into their
8632 if (!isNoopShuffleMask(PSHUFLMask))
8633 V = DAG.getNode(X86ISD::PSHUFLW, DL, MVT::v8i16, V,
8634 getV4X86ShuffleImm8ForMask(PSHUFLMask, DAG));
8635 if (!isNoopShuffleMask(PSHUFHMask))
8636 V = DAG.getNode(X86ISD::PSHUFHW, DL, MVT::v8i16, V,
8637 getV4X86ShuffleImm8ForMask(PSHUFHMask, DAG));
8638 if (!isNoopShuffleMask(PSHUFDMask))
8639 V = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
8640 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
8641 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V),
8642 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
8644 // At this point, each half should contain all its inputs, and we can then
8645 // just shuffle them into their final position.
8646 assert(std::count_if(LoMask.begin(), LoMask.end(),
8647 [](int M) { return M >= 4; }) == 0 &&
8648 "Failed to lift all the high half inputs to the low mask!");
8649 assert(std::count_if(HiMask.begin(), HiMask.end(),
8650 [](int M) { return M >= 0 && M < 4; }) == 0 &&
8651 "Failed to lift all the low half inputs to the high mask!");
8653 // Do a half shuffle for the low mask.
8654 if (!isNoopShuffleMask(LoMask))
8655 V = DAG.getNode(X86ISD::PSHUFLW, DL, MVT::v8i16, V,
8656 getV4X86ShuffleImm8ForMask(LoMask, DAG));
8658 // Do a half shuffle with the high mask after shifting its values down.
8659 for (int &M : HiMask)
8662 if (!isNoopShuffleMask(HiMask))
8663 V = DAG.getNode(X86ISD::PSHUFHW, DL, MVT::v8i16, V,
8664 getV4X86ShuffleImm8ForMask(HiMask, DAG));
8669 /// \brief Detect whether the mask pattern should be lowered through
8672 /// This essentially tests whether viewing the mask as an interleaving of two
8673 /// sub-sequences reduces the cross-input traffic of a blend operation. If so,
8674 /// lowering it through interleaving is a significantly better strategy.
8675 static bool shouldLowerAsInterleaving(ArrayRef<int> Mask) {
8676 int NumEvenInputs[2] = {0, 0};
8677 int NumOddInputs[2] = {0, 0};
8678 int NumLoInputs[2] = {0, 0};
8679 int NumHiInputs[2] = {0, 0};
8680 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
8684 int InputIdx = Mask[i] >= Size;
8687 ++NumLoInputs[InputIdx];
8689 ++NumHiInputs[InputIdx];
8692 ++NumEvenInputs[InputIdx];
8694 ++NumOddInputs[InputIdx];
8697 // The minimum number of cross-input results for both the interleaved and
8698 // split cases. If interleaving results in fewer cross-input results, return
8700 int InterleavedCrosses = std::min(NumEvenInputs[1] + NumOddInputs[0],
8701 NumEvenInputs[0] + NumOddInputs[1]);
8702 int SplitCrosses = std::min(NumLoInputs[1] + NumHiInputs[0],
8703 NumLoInputs[0] + NumHiInputs[1]);
8704 return InterleavedCrosses < SplitCrosses;
8707 /// \brief Blend two v8i16 vectors using a naive unpack strategy.
8709 /// This strategy only works when the inputs from each vector fit into a single
8710 /// half of that vector, and generally there are not so many inputs as to leave
8711 /// the in-place shuffles required highly constrained (and thus expensive). It
8712 /// shifts all the inputs into a single side of both input vectors and then
8713 /// uses an unpack to interleave these inputs in a single vector. At that
8714 /// point, we will fall back on the generic single input shuffle lowering.
8715 static SDValue lowerV8I16BasicBlendVectorShuffle(SDLoc DL, SDValue V1,
8717 MutableArrayRef<int> Mask,
8718 const X86Subtarget *Subtarget,
8719 SelectionDAG &DAG) {
8720 assert(V1.getSimpleValueType() == MVT::v8i16 && "Bad input type!");
8721 assert(V2.getSimpleValueType() == MVT::v8i16 && "Bad input type!");
8722 SmallVector<int, 3> LoV1Inputs, HiV1Inputs, LoV2Inputs, HiV2Inputs;
8723 for (int i = 0; i < 8; ++i)
8724 if (Mask[i] >= 0 && Mask[i] < 4)
8725 LoV1Inputs.push_back(i);
8726 else if (Mask[i] >= 4 && Mask[i] < 8)
8727 HiV1Inputs.push_back(i);
8728 else if (Mask[i] >= 8 && Mask[i] < 12)
8729 LoV2Inputs.push_back(i);
8730 else if (Mask[i] >= 12)
8731 HiV2Inputs.push_back(i);
8733 int NumV1Inputs = LoV1Inputs.size() + HiV1Inputs.size();
8734 int NumV2Inputs = LoV2Inputs.size() + HiV2Inputs.size();
8737 assert(NumV1Inputs > 0 && NumV1Inputs <= 3 && "At most 3 inputs supported");
8738 assert(NumV2Inputs > 0 && NumV2Inputs <= 3 && "At most 3 inputs supported");
8739 assert(NumV1Inputs + NumV2Inputs <= 4 && "At most 4 combined inputs");
8741 bool MergeFromLo = LoV1Inputs.size() + LoV2Inputs.size() >=
8742 HiV1Inputs.size() + HiV2Inputs.size();
8744 auto moveInputsToHalf = [&](SDValue V, ArrayRef<int> LoInputs,
8745 ArrayRef<int> HiInputs, bool MoveToLo,
8747 ArrayRef<int> GoodInputs = MoveToLo ? LoInputs : HiInputs;
8748 ArrayRef<int> BadInputs = MoveToLo ? HiInputs : LoInputs;
8749 if (BadInputs.empty())
8752 int MoveMask[] = {-1, -1, -1, -1, -1, -1, -1, -1};
8753 int MoveOffset = MoveToLo ? 0 : 4;
8755 if (GoodInputs.empty()) {
8756 for (int BadInput : BadInputs) {
8757 MoveMask[Mask[BadInput] % 4 + MoveOffset] = Mask[BadInput] - MaskOffset;
8758 Mask[BadInput] = Mask[BadInput] % 4 + MoveOffset + MaskOffset;
8761 if (GoodInputs.size() == 2) {
8762 // If the low inputs are spread across two dwords, pack them into
8764 MoveMask[MoveOffset] = Mask[GoodInputs[0]] - MaskOffset;
8765 MoveMask[MoveOffset + 1] = Mask[GoodInputs[1]] - MaskOffset;
8766 Mask[GoodInputs[0]] = MoveOffset + MaskOffset;
8767 Mask[GoodInputs[1]] = MoveOffset + 1 + MaskOffset;
8769 // Otherwise pin the good inputs.
8770 for (int GoodInput : GoodInputs)
8771 MoveMask[Mask[GoodInput] - MaskOffset] = Mask[GoodInput] - MaskOffset;
8774 if (BadInputs.size() == 2) {
8775 // If we have two bad inputs then there may be either one or two good
8776 // inputs fixed in place. Find a fixed input, and then find the *other*
8777 // two adjacent indices by using modular arithmetic.
8779 std::find_if(std::begin(MoveMask) + MoveOffset, std::end(MoveMask),
8780 [](int M) { return M >= 0; }) -
8781 std::begin(MoveMask);
8783 ((((GoodMaskIdx - MoveOffset) & ~1) + 2) % 4) + MoveOffset;
8784 assert(MoveMask[MoveMaskIdx] == -1 && "Expected empty slot");
8785 assert(MoveMask[MoveMaskIdx + 1] == -1 && "Expected empty slot");
8786 MoveMask[MoveMaskIdx] = Mask[BadInputs[0]] - MaskOffset;
8787 MoveMask[MoveMaskIdx + 1] = Mask[BadInputs[1]] - MaskOffset;
8788 Mask[BadInputs[0]] = MoveMaskIdx + MaskOffset;
8789 Mask[BadInputs[1]] = MoveMaskIdx + 1 + MaskOffset;
8791 assert(BadInputs.size() == 1 && "All sizes handled");
8792 int MoveMaskIdx = std::find(std::begin(MoveMask) + MoveOffset,
8793 std::end(MoveMask), -1) -
8794 std::begin(MoveMask);
8795 MoveMask[MoveMaskIdx] = Mask[BadInputs[0]] - MaskOffset;
8796 Mask[BadInputs[0]] = MoveMaskIdx + MaskOffset;
8800 return DAG.getVectorShuffle(MVT::v8i16, DL, V, DAG.getUNDEF(MVT::v8i16),
8803 V1 = moveInputsToHalf(V1, LoV1Inputs, HiV1Inputs, MergeFromLo,
8805 V2 = moveInputsToHalf(V2, LoV2Inputs, HiV2Inputs, MergeFromLo,
8808 // FIXME: Select an interleaving of the merge of V1 and V2 that minimizes
8809 // cross-half traffic in the final shuffle.
8811 // Munge the mask to be a single-input mask after the unpack merges the
8815 M = 2 * (M % 4) + (M / 8);
8817 return DAG.getVectorShuffle(
8818 MVT::v8i16, DL, DAG.getNode(MergeFromLo ? X86ISD::UNPCKL : X86ISD::UNPCKH,
8819 DL, MVT::v8i16, V1, V2),
8820 DAG.getUNDEF(MVT::v8i16), Mask);
8823 /// \brief Generic lowering of 8-lane i16 shuffles.
8825 /// This handles both single-input shuffles and combined shuffle/blends with
8826 /// two inputs. The single input shuffles are immediately delegated to
8827 /// a dedicated lowering routine.
8829 /// The blends are lowered in one of three fundamental ways. If there are few
8830 /// enough inputs, it delegates to a basic UNPCK-based strategy. If the shuffle
8831 /// of the input is significantly cheaper when lowered as an interleaving of
8832 /// the two inputs, try to interleave them. Otherwise, blend the low and high
8833 /// halves of the inputs separately (making them have relatively few inputs)
8834 /// and then concatenate them.
8835 static SDValue lowerV8I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8836 const X86Subtarget *Subtarget,
8837 SelectionDAG &DAG) {
8839 assert(Op.getSimpleValueType() == MVT::v8i16 && "Bad shuffle type!");
8840 assert(V1.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
8841 assert(V2.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
8842 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8843 ArrayRef<int> OrigMask = SVOp->getMask();
8844 int MaskStorage[8] = {OrigMask[0], OrigMask[1], OrigMask[2], OrigMask[3],
8845 OrigMask[4], OrigMask[5], OrigMask[6], OrigMask[7]};
8846 MutableArrayRef<int> Mask(MaskStorage);
8848 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
8850 // Whenever we can lower this as a zext, that instruction is strictly faster
8851 // than any alternative.
8852 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(
8853 DL, MVT::v8i16, V1, V2, OrigMask, Subtarget, DAG))
8856 auto isV1 = [](int M) { return M >= 0 && M < 8; };
8857 auto isV2 = [](int M) { return M >= 8; };
8859 int NumV1Inputs = std::count_if(Mask.begin(), Mask.end(), isV1);
8860 int NumV2Inputs = std::count_if(Mask.begin(), Mask.end(), isV2);
8862 if (NumV2Inputs == 0)
8863 return lowerV8I16SingleInputVectorShuffle(DL, V1, Mask, Subtarget, DAG);
8865 assert(NumV1Inputs > 0 && "All single-input shuffles should be canonicalized "
8866 "to be V1-input shuffles.");
8868 // There are special ways we can lower some single-element blends.
8869 if (NumV2Inputs == 1)
8870 if (SDValue V = lowerVectorShuffleAsElementInsertion(MVT::v8i16, DL, V1, V2,
8871 Mask, Subtarget, DAG))
8874 if (Subtarget->hasSSE41())
8875 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8i16, V1, V2, Mask,
8879 // Try to use rotation instructions if available.
8880 if (Subtarget->hasSSSE3())
8881 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(DL, MVT::v8i16, V1, V2, Mask, DAG))
8884 if (NumV1Inputs + NumV2Inputs <= 4)
8885 return lowerV8I16BasicBlendVectorShuffle(DL, V1, V2, Mask, Subtarget, DAG);
8887 // Check whether an interleaving lowering is likely to be more efficient.
8888 // This isn't perfect but it is a strong heuristic that tends to work well on
8889 // the kinds of shuffles that show up in practice.
8891 // FIXME: Handle 1x, 2x, and 4x interleaving.
8892 if (shouldLowerAsInterleaving(Mask)) {
8893 // FIXME: Figure out whether we should pack these into the low or high
8896 int EMask[8], OMask[8];
8897 for (int i = 0; i < 4; ++i) {
8898 EMask[i] = Mask[2*i];
8899 OMask[i] = Mask[2*i + 1];
8904 SDValue Evens = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, EMask);
8905 SDValue Odds = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, OMask);
8907 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i16, Evens, Odds);
8910 int LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
8911 int HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
8913 for (int i = 0; i < 4; ++i) {
8914 LoBlendMask[i] = Mask[i];
8915 HiBlendMask[i] = Mask[i + 4];
8918 SDValue LoV = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, LoBlendMask);
8919 SDValue HiV = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, HiBlendMask);
8920 LoV = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, LoV);
8921 HiV = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, HiV);
8923 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
8924 DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2i64, LoV, HiV));
8927 /// \brief Check whether a compaction lowering can be done by dropping even
8928 /// elements and compute how many times even elements must be dropped.
8930 /// This handles shuffles which take every Nth element where N is a power of
8931 /// two. Example shuffle masks:
8933 /// N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 0, 2, 4, 6, 8, 10, 12, 14
8934 /// N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30
8935 /// N = 2: 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12
8936 /// N = 2: 0, 4, 8, 12, 16, 20, 24, 28, 0, 4, 8, 12, 16, 20, 24, 28
8937 /// N = 3: 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8
8938 /// N = 3: 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24
8940 /// Any of these lanes can of course be undef.
8942 /// This routine only supports N <= 3.
8943 /// FIXME: Evaluate whether either AVX or AVX-512 have any opportunities here
8946 /// \returns N above, or the number of times even elements must be dropped if
8947 /// there is such a number. Otherwise returns zero.
8948 static int canLowerByDroppingEvenElements(ArrayRef<int> Mask) {
8949 // Figure out whether we're looping over two inputs or just one.
8950 bool IsSingleInput = isSingleInputShuffleMask(Mask);
8952 // The modulus for the shuffle vector entries is based on whether this is
8953 // a single input or not.
8954 int ShuffleModulus = Mask.size() * (IsSingleInput ? 1 : 2);
8955 assert(isPowerOf2_32((uint32_t)ShuffleModulus) &&
8956 "We should only be called with masks with a power-of-2 size!");
8958 uint64_t ModMask = (uint64_t)ShuffleModulus - 1;
8960 // We track whether the input is viable for all power-of-2 strides 2^1, 2^2,
8961 // and 2^3 simultaneously. This is because we may have ambiguity with
8962 // partially undef inputs.
8963 bool ViableForN[3] = {true, true, true};
8965 for (int i = 0, e = Mask.size(); i < e; ++i) {
8966 // Ignore undef lanes, we'll optimistically collapse them to the pattern we
8971 bool IsAnyViable = false;
8972 for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
8973 if (ViableForN[j]) {
8976 // The shuffle mask must be equal to (i * 2^N) % M.
8977 if ((uint64_t)Mask[i] == (((uint64_t)i << N) & ModMask))
8980 ViableForN[j] = false;
8982 // Early exit if we exhaust the possible powers of two.
8987 for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
8991 // Return 0 as there is no viable power of two.
8995 /// \brief Generic lowering of v16i8 shuffles.
8997 /// This is a hybrid strategy to lower v16i8 vectors. It first attempts to
8998 /// detect any complexity reducing interleaving. If that doesn't help, it uses
8999 /// UNPCK to spread the i8 elements across two i16-element vectors, and uses
9000 /// the existing lowering for v8i16 blends on each half, finally PACK-ing them
9002 static SDValue lowerV16I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9003 const X86Subtarget *Subtarget,
9004 SelectionDAG &DAG) {
9006 assert(Op.getSimpleValueType() == MVT::v16i8 && "Bad shuffle type!");
9007 assert(V1.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
9008 assert(V2.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
9009 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9010 ArrayRef<int> OrigMask = SVOp->getMask();
9011 assert(OrigMask.size() == 16 && "Unexpected mask size for v16 shuffle!");
9013 // Try to use rotation instructions if available.
9014 if (Subtarget->hasSSSE3())
9015 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(DL, MVT::v16i8, V1, V2,
9019 // Try to use a zext lowering.
9020 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(
9021 DL, MVT::v16i8, V1, V2, OrigMask, Subtarget, DAG))
9024 int MaskStorage[16] = {
9025 OrigMask[0], OrigMask[1], OrigMask[2], OrigMask[3],
9026 OrigMask[4], OrigMask[5], OrigMask[6], OrigMask[7],
9027 OrigMask[8], OrigMask[9], OrigMask[10], OrigMask[11],
9028 OrigMask[12], OrigMask[13], OrigMask[14], OrigMask[15]};
9029 MutableArrayRef<int> Mask(MaskStorage);
9030 MutableArrayRef<int> LoMask = Mask.slice(0, 8);
9031 MutableArrayRef<int> HiMask = Mask.slice(8, 8);
9034 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 16; });
9036 // For single-input shuffles, there are some nicer lowering tricks we can use.
9037 if (NumV2Elements == 0) {
9038 // Check whether we can widen this to an i16 shuffle by duplicating bytes.
9039 // Notably, this handles splat and partial-splat shuffles more efficiently.
9040 // However, it only makes sense if the pre-duplication shuffle simplifies
9041 // things significantly. Currently, this means we need to be able to
9042 // express the pre-duplication shuffle as an i16 shuffle.
9044 // FIXME: We should check for other patterns which can be widened into an
9045 // i16 shuffle as well.
9046 auto canWidenViaDuplication = [](ArrayRef<int> Mask) {
9047 for (int i = 0; i < 16; i += 2)
9048 if (Mask[i] != -1 && Mask[i + 1] != -1 && Mask[i] != Mask[i + 1])
9053 auto tryToWidenViaDuplication = [&]() -> SDValue {
9054 if (!canWidenViaDuplication(Mask))
9056 SmallVector<int, 4> LoInputs;
9057 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(LoInputs),
9058 [](int M) { return M >= 0 && M < 8; });
9059 std::sort(LoInputs.begin(), LoInputs.end());
9060 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()),
9062 SmallVector<int, 4> HiInputs;
9063 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(HiInputs),
9064 [](int M) { return M >= 8; });
9065 std::sort(HiInputs.begin(), HiInputs.end());
9066 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()),
9069 bool TargetLo = LoInputs.size() >= HiInputs.size();
9070 ArrayRef<int> InPlaceInputs = TargetLo ? LoInputs : HiInputs;
9071 ArrayRef<int> MovingInputs = TargetLo ? HiInputs : LoInputs;
9073 int PreDupI16Shuffle[] = {-1, -1, -1, -1, -1, -1, -1, -1};
9074 SmallDenseMap<int, int, 8> LaneMap;
9075 for (int I : InPlaceInputs) {
9076 PreDupI16Shuffle[I/2] = I/2;
9079 int j = TargetLo ? 0 : 4, je = j + 4;
9080 for (int i = 0, ie = MovingInputs.size(); i < ie; ++i) {
9081 // Check if j is already a shuffle of this input. This happens when
9082 // there are two adjacent bytes after we move the low one.
9083 if (PreDupI16Shuffle[j] != MovingInputs[i] / 2) {
9084 // If we haven't yet mapped the input, search for a slot into which
9086 while (j < je && PreDupI16Shuffle[j] != -1)
9090 // We can't place the inputs into a single half with a simple i16 shuffle, so bail.
9093 // Map this input with the i16 shuffle.
9094 PreDupI16Shuffle[j] = MovingInputs[i] / 2;
9097 // Update the lane map based on the mapping we ended up with.
9098 LaneMap[MovingInputs[i]] = 2 * j + MovingInputs[i] % 2;
9101 ISD::BITCAST, DL, MVT::v16i8,
9102 DAG.getVectorShuffle(MVT::v8i16, DL,
9103 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1),
9104 DAG.getUNDEF(MVT::v8i16), PreDupI16Shuffle));
9106 // Unpack the bytes to form the i16s that will be shuffled into place.
9107 V1 = DAG.getNode(TargetLo ? X86ISD::UNPCKL : X86ISD::UNPCKH, DL,
9108 MVT::v16i8, V1, V1);
9110 int PostDupI16Shuffle[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9111 for (int i = 0; i < 16; ++i)
9112 if (Mask[i] != -1) {
9113 int MappedMask = LaneMap[Mask[i]] - (TargetLo ? 0 : 8);
9114 assert(MappedMask < 8 && "Invalid v8 shuffle mask!");
9115 if (PostDupI16Shuffle[i / 2] == -1)
9116 PostDupI16Shuffle[i / 2] = MappedMask;
9118 assert(PostDupI16Shuffle[i / 2] == MappedMask &&
9119 "Conflicting entrties in the original shuffle!");
9122 ISD::BITCAST, DL, MVT::v16i8,
9123 DAG.getVectorShuffle(MVT::v8i16, DL,
9124 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1),
9125 DAG.getUNDEF(MVT::v8i16), PostDupI16Shuffle));
9127 if (SDValue V = tryToWidenViaDuplication())
9131 // Check whether an interleaving lowering is likely to be more efficient.
9132 // This isn't perfect but it is a strong heuristic that tends to work well on
9133 // the kinds of shuffles that show up in practice.
9135 // FIXME: We need to handle other interleaving widths (i16, i32, ...).
9136 if (shouldLowerAsInterleaving(Mask)) {
9137 // FIXME: Figure out whether we should pack these into the low or high
9140 int EMask[16], OMask[16];
9141 for (int i = 0; i < 8; ++i) {
9142 EMask[i] = Mask[2*i];
9143 OMask[i] = Mask[2*i + 1];
9148 SDValue Evens = DAG.getVectorShuffle(MVT::v16i8, DL, V1, V2, EMask);
9149 SDValue Odds = DAG.getVectorShuffle(MVT::v16i8, DL, V1, V2, OMask);
9151 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i8, Evens, Odds);
9154 // Check for SSSE3 which lets us lower all v16i8 shuffles much more directly
9155 // with PSHUFB. It is important to do this before we attempt to generate any
9156 // blends but after all of the single-input lowerings. If the single input
9157 // lowerings can find an instruction sequence that is faster than a PSHUFB, we
9158 // want to preserve that and we can DAG combine any longer sequences into
9159 // a PSHUFB in the end. But once we start blending from multiple inputs,
9160 // the complexity of DAG combining bad patterns back into PSHUFB is too high,
9161 // and there are *very* few patterns that would actually be faster than the
9162 // PSHUFB approach because of its ability to zero lanes.
9164 // FIXME: The only exceptions to the above are blends which are exact
9165 // interleavings with direct instructions supporting them. We currently don't
9166 // handle those well here.
9167 if (Subtarget->hasSSSE3()) {
9170 for (int i = 0; i < 16; ++i)
9171 if (Mask[i] == -1) {
9172 V1Mask[i] = V2Mask[i] = DAG.getUNDEF(MVT::i8);
9174 V1Mask[i] = DAG.getConstant(Mask[i] < 16 ? Mask[i] : 0x80, MVT::i8);
9176 DAG.getConstant(Mask[i] < 16 ? 0x80 : Mask[i] - 16, MVT::i8);
9178 V1 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, V1,
9179 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V1Mask));
9180 if (isSingleInputShuffleMask(Mask))
9181 return V1; // Single inputs are easy.
9183 // Otherwise, blend the two.
9184 V2 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, V2,
9185 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V2Mask));
9186 return DAG.getNode(ISD::OR, DL, MVT::v16i8, V1, V2);
9189 // There are special ways we can lower some single-element blends.
9190 if (NumV2Elements == 1)
9191 if (SDValue V = lowerVectorShuffleAsElementInsertion(MVT::v16i8, DL, V1, V2,
9192 Mask, Subtarget, DAG))
9195 // Check whether a compaction lowering can be done. This handles shuffles
9196 // which take every Nth element for some even N. See the helper function for
9199 // We special case these as they can be particularly efficiently handled with
9200 // the PACKUSB instruction on x86 and they show up in common patterns of
9201 // rearranging bytes to truncate wide elements.
9202 if (int NumEvenDrops = canLowerByDroppingEvenElements(Mask)) {
9203 // NumEvenDrops is the power of two stride of the elements. Another way of
9204 // thinking about it is that we need to drop the even elements this many
9205 // times to get the original input.
9206 bool IsSingleInput = isSingleInputShuffleMask(Mask);
9208 // First we need to zero all the dropped bytes.
9209 assert(NumEvenDrops <= 3 &&
9210 "No support for dropping even elements more than 3 times.");
9211 // We use the mask type to pick which bytes are preserved based on how many
9212 // elements are dropped.
9213 MVT MaskVTs[] = { MVT::v8i16, MVT::v4i32, MVT::v2i64 };
9214 SDValue ByteClearMask =
9215 DAG.getNode(ISD::BITCAST, DL, MVT::v16i8,
9216 DAG.getConstant(0xFF, MaskVTs[NumEvenDrops - 1]));
9217 V1 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V1, ByteClearMask);
9219 V2 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V2, ByteClearMask);
9221 // Now pack things back together.
9222 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1);
9223 V2 = IsSingleInput ? V1 : DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V2);
9224 SDValue Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, V1, V2);
9225 for (int i = 1; i < NumEvenDrops; ++i) {
9226 Result = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, Result);
9227 Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, Result, Result);
9233 int V1LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9234 int V1HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9235 int V2LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9236 int V2HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9238 auto buildBlendMasks = [](MutableArrayRef<int> HalfMask,
9239 MutableArrayRef<int> V1HalfBlendMask,
9240 MutableArrayRef<int> V2HalfBlendMask) {
9241 for (int i = 0; i < 8; ++i)
9242 if (HalfMask[i] >= 0 && HalfMask[i] < 16) {
9243 V1HalfBlendMask[i] = HalfMask[i];
9245 } else if (HalfMask[i] >= 16) {
9246 V2HalfBlendMask[i] = HalfMask[i] - 16;
9247 HalfMask[i] = i + 8;
9250 buildBlendMasks(LoMask, V1LoBlendMask, V2LoBlendMask);
9251 buildBlendMasks(HiMask, V1HiBlendMask, V2HiBlendMask);
9253 SDValue Zero = getZeroVector(MVT::v8i16, Subtarget, DAG, DL);
9255 auto buildLoAndHiV8s = [&](SDValue V, MutableArrayRef<int> LoBlendMask,
9256 MutableArrayRef<int> HiBlendMask) {
9258 // Check if any of the odd lanes in the v16i8 are used. If not, we can mask
9259 // them out and avoid using UNPCK{L,H} to extract the elements of V as
9261 if (std::none_of(LoBlendMask.begin(), LoBlendMask.end(),
9262 [](int M) { return M >= 0 && M % 2 == 1; }) &&
9263 std::none_of(HiBlendMask.begin(), HiBlendMask.end(),
9264 [](int M) { return M >= 0 && M % 2 == 1; })) {
9265 // Use a mask to drop the high bytes.
9266 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V);
9267 V1 = DAG.getNode(ISD::AND, DL, MVT::v8i16, V1,
9268 DAG.getConstant(0x00FF, MVT::v8i16));
9270 // This will be a single vector shuffle instead of a blend so nuke V2.
9271 V2 = DAG.getUNDEF(MVT::v8i16);
9273 // Squash the masks to point directly into V1.
9274 for (int &M : LoBlendMask)
9277 for (int &M : HiBlendMask)
9281 // Otherwise just unpack the low half of V into V1 and the high half into
9282 // V2 so that we can blend them as i16s.
9283 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
9284 DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i8, V, Zero));
9285 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
9286 DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i8, V, Zero));
9289 SDValue BlendedLo = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, LoBlendMask);
9290 SDValue BlendedHi = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, HiBlendMask);
9291 return std::make_pair(BlendedLo, BlendedHi);
9293 SDValue V1Lo, V1Hi, V2Lo, V2Hi;
9294 std::tie(V1Lo, V1Hi) = buildLoAndHiV8s(V1, V1LoBlendMask, V1HiBlendMask);
9295 std::tie(V2Lo, V2Hi) = buildLoAndHiV8s(V2, V2LoBlendMask, V2HiBlendMask);
9297 SDValue LoV = DAG.getVectorShuffle(MVT::v8i16, DL, V1Lo, V2Lo, LoMask);
9298 SDValue HiV = DAG.getVectorShuffle(MVT::v8i16, DL, V1Hi, V2Hi, HiMask);
9300 return DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, LoV, HiV);
9303 /// \brief Dispatching routine to lower various 128-bit x86 vector shuffles.
9305 /// This routine breaks down the specific type of 128-bit shuffle and
9306 /// dispatches to the lowering routines accordingly.
9307 static SDValue lower128BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9308 MVT VT, const X86Subtarget *Subtarget,
9309 SelectionDAG &DAG) {
9310 switch (VT.SimpleTy) {
9312 return lowerV2I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9314 return lowerV2F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9316 return lowerV4I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9318 return lowerV4F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9320 return lowerV8I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
9322 return lowerV16I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
9325 llvm_unreachable("Unimplemented!");
9329 /// \brief Generic routine to split ector shuffle into half-sized shuffles.
9331 /// This routine just extracts two subvectors, shuffles them independently, and
9332 /// then concatenates them back together. This should work effectively with all
9333 /// AVX vector shuffle types.
9334 static SDValue splitAndLowerVectorShuffle(SDLoc DL, MVT VT, SDValue V1,
9335 SDValue V2, ArrayRef<int> Mask,
9336 SelectionDAG &DAG) {
9337 assert(VT.getSizeInBits() >= 256 &&
9338 "Only for 256-bit or wider vector shuffles!");
9339 assert(V1.getSimpleValueType() == VT && "Bad operand type!");
9340 assert(V2.getSimpleValueType() == VT && "Bad operand type!");
9342 ArrayRef<int> LoMask = Mask.slice(0, Mask.size() / 2);
9343 ArrayRef<int> HiMask = Mask.slice(Mask.size() / 2);
9345 int NumElements = VT.getVectorNumElements();
9346 int SplitNumElements = NumElements / 2;
9347 MVT ScalarVT = VT.getScalarType();
9348 MVT SplitVT = MVT::getVectorVT(ScalarVT, NumElements / 2);
9350 SDValue LoV1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V1,
9351 DAG.getIntPtrConstant(0));
9352 SDValue HiV1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V1,
9353 DAG.getIntPtrConstant(SplitNumElements));
9354 SDValue LoV2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V2,
9355 DAG.getIntPtrConstant(0));
9356 SDValue HiV2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V2,
9357 DAG.getIntPtrConstant(SplitNumElements));
9359 // Now create two 4-way blends of these half-width vectors.
9360 auto HalfBlend = [&](ArrayRef<int> HalfMask) {
9361 SmallVector<int, 32> V1BlendMask, V2BlendMask, BlendMask;
9362 for (int i = 0; i < SplitNumElements; ++i) {
9363 int M = HalfMask[i];
9364 if (M >= NumElements) {
9365 V2BlendMask.push_back(M - NumElements);
9366 V1BlendMask.push_back(-1);
9367 BlendMask.push_back(SplitNumElements + i);
9368 } else if (M >= 0) {
9369 V2BlendMask.push_back(-1);
9370 V1BlendMask.push_back(M);
9371 BlendMask.push_back(i);
9373 V2BlendMask.push_back(-1);
9374 V1BlendMask.push_back(-1);
9375 BlendMask.push_back(-1);
9379 DAG.getVectorShuffle(SplitVT, DL, LoV1, HiV1, V1BlendMask);
9381 DAG.getVectorShuffle(SplitVT, DL, LoV2, HiV2, V2BlendMask);
9382 return DAG.getVectorShuffle(SplitVT, DL, V1Blend, V2Blend, BlendMask);
9384 SDValue Lo = HalfBlend(LoMask);
9385 SDValue Hi = HalfBlend(HiMask);
9386 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Lo, Hi);
9389 /// \brief Lower a vector shuffle crossing multiple 128-bit lanes as
9390 /// a permutation and blend of those lanes.
9392 /// This essentially blends the out-of-lane inputs to each lane into the lane
9393 /// from a permuted copy of the vector. This lowering strategy results in four
9394 /// instructions in the worst case for a single-input cross lane shuffle which
9395 /// is lower than any other fully general cross-lane shuffle strategy I'm aware
9396 /// of. Special cases for each particular shuffle pattern should be handled
9397 /// prior to trying this lowering.
9398 static SDValue lowerVectorShuffleAsLanePermuteAndBlend(SDLoc DL, MVT VT,
9399 SDValue V1, SDValue V2,
9401 SelectionDAG &DAG) {
9402 // FIXME: This should probably be generalized for 512-bit vectors as well.
9403 assert(VT.getSizeInBits() == 256 && "Only for 256-bit vector shuffles!");
9404 int LaneSize = Mask.size() / 2;
9406 // If there are only inputs from one 128-bit lane, splitting will in fact be
9407 // less expensive. The flags track wether the given lane contains an element
9408 // that crosses to another lane.
9409 bool LaneCrossing[2] = {false, false};
9410 for (int i = 0, Size = Mask.size(); i < Size; ++i)
9411 if (Mask[i] >= 0 && (Mask[i] % Size) / LaneSize != i / LaneSize)
9412 LaneCrossing[(Mask[i] % Size) / LaneSize] = true;
9413 if (!LaneCrossing[0] || !LaneCrossing[1])
9414 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
9416 if (isSingleInputShuffleMask(Mask)) {
9417 SmallVector<int, 32> FlippedBlendMask;
9418 for (int i = 0, Size = Mask.size(); i < Size; ++i)
9419 FlippedBlendMask.push_back(
9420 Mask[i] < 0 ? -1 : (((Mask[i] % Size) / LaneSize == i / LaneSize)
9422 : Mask[i] % LaneSize +
9423 (i / LaneSize) * LaneSize + Size));
9425 // Flip the vector, and blend the results which should now be in-lane. The
9426 // VPERM2X128 mask uses the low 2 bits for the low source and bits 4 and
9427 // 5 for the high source. The value 3 selects the high half of source 2 and
9428 // the value 2 selects the low half of source 2. We only use source 2 to
9429 // allow folding it into a memory operand.
9430 unsigned PERMMask = 3 | 2 << 4;
9431 SDValue Flipped = DAG.getNode(X86ISD::VPERM2X128, DL, VT, DAG.getUNDEF(VT),
9432 V1, DAG.getConstant(PERMMask, MVT::i8));
9433 return DAG.getVectorShuffle(VT, DL, V1, Flipped, FlippedBlendMask);
9436 // This now reduces to two single-input shuffles of V1 and V2 which at worst
9437 // will be handled by the above logic and a blend of the results, much like
9438 // other patterns in AVX.
9439 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask, DAG);
9442 /// \brief Handle lowering of 4-lane 64-bit floating point shuffles.
9444 /// Also ends up handling lowering of 4-lane 64-bit integer shuffles when AVX2
9445 /// isn't available.
9446 static SDValue lowerV4F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9447 const X86Subtarget *Subtarget,
9448 SelectionDAG &DAG) {
9450 assert(V1.getSimpleValueType() == MVT::v4f64 && "Bad operand type!");
9451 assert(V2.getSimpleValueType() == MVT::v4f64 && "Bad operand type!");
9452 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9453 ArrayRef<int> Mask = SVOp->getMask();
9454 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
9456 if (isSingleInputShuffleMask(Mask)) {
9457 if (!is128BitLaneCrossingShuffleMask(MVT::v4f64, Mask)) {
9458 // Non-half-crossing single input shuffles can be lowerid with an
9459 // interleaved permutation.
9460 unsigned VPERMILPMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1) |
9461 ((Mask[2] == 3) << 2) | ((Mask[3] == 3) << 3);
9462 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v4f64, V1,
9463 DAG.getConstant(VPERMILPMask, MVT::i8));
9466 // With AVX2 we have direct support for this permutation.
9467 if (Subtarget->hasAVX2())
9468 return DAG.getNode(X86ISD::VPERMI, DL, MVT::v4f64, V1,
9469 getV4X86ShuffleImm8ForMask(Mask, DAG));
9471 // Otherwise, fall back.
9472 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v4f64, V1, V2, Mask,
9476 // X86 has dedicated unpack instructions that can handle specific blend
9477 // operations: UNPCKH and UNPCKL.
9478 if (isShuffleEquivalent(Mask, 0, 4, 2, 6))
9479 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f64, V1, V2);
9480 if (isShuffleEquivalent(Mask, 1, 5, 3, 7))
9481 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f64, V1, V2);
9483 // If we have a single input to the zero element, insert that into V1 if we
9484 // can do so cheaply.
9486 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
9487 if (NumV2Elements == 1 && Mask[0] >= 4)
9488 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
9489 MVT::v4f64, DL, V1, V2, Mask, Subtarget, DAG))
9492 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4f64, V1, V2, Mask,
9496 // Check if the blend happens to exactly fit that of SHUFPD.
9497 if ((Mask[0] == -1 || Mask[0] < 2) &&
9498 (Mask[1] == -1 || (Mask[1] >= 4 && Mask[1] < 6)) &&
9499 (Mask[2] == -1 || (Mask[2] >= 2 && Mask[2] < 4)) &&
9500 (Mask[3] == -1 || Mask[3] >= 6)) {
9501 unsigned SHUFPDMask = (Mask[0] == 1) | ((Mask[1] == 5) << 1) |
9502 ((Mask[2] == 3) << 2) | ((Mask[3] == 7) << 3);
9503 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f64, V1, V2,
9504 DAG.getConstant(SHUFPDMask, MVT::i8));
9506 if ((Mask[0] == -1 || (Mask[0] >= 4 && Mask[0] < 6)) &&
9507 (Mask[1] == -1 || Mask[1] < 2) &&
9508 (Mask[2] == -1 || Mask[2] >= 6) &&
9509 (Mask[3] == -1 || (Mask[3] >= 2 && Mask[3] < 4))) {
9510 unsigned SHUFPDMask = (Mask[0] == 5) | ((Mask[1] == 1) << 1) |
9511 ((Mask[2] == 7) << 2) | ((Mask[3] == 3) << 3);
9512 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f64, V2, V1,
9513 DAG.getConstant(SHUFPDMask, MVT::i8));
9516 // Otherwise fall back on generic blend lowering.
9517 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4f64, V1, V2,
9521 /// \brief Handle lowering of 4-lane 64-bit integer shuffles.
9523 /// This routine is only called when we have AVX2 and thus a reasonable
9524 /// instruction set for v4i64 shuffling..
9525 static SDValue lowerV4I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9526 const X86Subtarget *Subtarget,
9527 SelectionDAG &DAG) {
9529 assert(V1.getSimpleValueType() == MVT::v4i64 && "Bad operand type!");
9530 assert(V2.getSimpleValueType() == MVT::v4i64 && "Bad operand type!");
9531 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9532 ArrayRef<int> Mask = SVOp->getMask();
9533 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
9534 assert(Subtarget->hasAVX2() && "We can only lower v4i64 with AVX2!");
9536 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4i64, V1, V2, Mask,
9540 // When the shuffle is mirrored between the 128-bit lanes of the unit, we can
9541 // use lower latency instructions that will operate on both 128-bit lanes.
9542 SmallVector<int, 2> RepeatedMask;
9543 if (is128BitLaneRepeatedShuffleMask(MVT::v4i64, Mask, RepeatedMask)) {
9544 if (isSingleInputShuffleMask(Mask)) {
9545 int PSHUFDMask[] = {-1, -1, -1, -1};
9546 for (int i = 0; i < 2; ++i)
9547 if (RepeatedMask[i] >= 0) {
9548 PSHUFDMask[2 * i] = 2 * RepeatedMask[i];
9549 PSHUFDMask[2 * i + 1] = 2 * RepeatedMask[i] + 1;
9552 ISD::BITCAST, DL, MVT::v4i64,
9553 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v8i32,
9554 DAG.getNode(ISD::BITCAST, DL, MVT::v8i32, V1),
9555 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
9558 // Use dedicated unpack instructions for masks that match their pattern.
9559 if (isShuffleEquivalent(Mask, 0, 4, 2, 6))
9560 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i64, V1, V2);
9561 if (isShuffleEquivalent(Mask, 1, 5, 3, 7))
9562 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i64, V1, V2);
9565 // AVX2 provides a direct instruction for permuting a single input across
9567 if (isSingleInputShuffleMask(Mask))
9568 return DAG.getNode(X86ISD::VPERMI, DL, MVT::v4i64, V1,
9569 getV4X86ShuffleImm8ForMask(Mask, DAG));
9571 // Otherwise fall back on generic blend lowering.
9572 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4i64, V1, V2,
9576 /// \brief Handle lowering of 8-lane 32-bit floating point shuffles.
9578 /// Also ends up handling lowering of 8-lane 32-bit integer shuffles when AVX2
9579 /// isn't available.
9580 static SDValue lowerV8F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9581 const X86Subtarget *Subtarget,
9582 SelectionDAG &DAG) {
9584 assert(V1.getSimpleValueType() == MVT::v8f32 && "Bad operand type!");
9585 assert(V2.getSimpleValueType() == MVT::v8f32 && "Bad operand type!");
9586 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9587 ArrayRef<int> Mask = SVOp->getMask();
9588 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
9590 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8f32, V1, V2, Mask,
9594 // If the shuffle mask is repeated in each 128-bit lane, we have many more
9595 // options to efficiently lower the shuffle.
9596 SmallVector<int, 4> RepeatedMask;
9597 if (is128BitLaneRepeatedShuffleMask(MVT::v8f32, Mask, RepeatedMask)) {
9598 assert(RepeatedMask.size() == 4 &&
9599 "Repeated masks must be half the mask width!");
9600 if (isSingleInputShuffleMask(Mask))
9601 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v8f32, V1,
9602 getV4X86ShuffleImm8ForMask(RepeatedMask, DAG));
9604 // Use dedicated unpack instructions for masks that match their pattern.
9605 if (isShuffleEquivalent(Mask, 0, 8, 1, 9, 4, 12, 5, 13))
9606 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8f32, V1, V2);
9607 if (isShuffleEquivalent(Mask, 2, 10, 3, 11, 6, 14, 7, 15))
9608 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8f32, V1, V2);
9610 // Otherwise, fall back to a SHUFPS sequence. Here it is important that we
9611 // have already handled any direct blends. We also need to squash the
9612 // repeated mask into a simulated v4f32 mask.
9613 for (int i = 0; i < 4; ++i)
9614 if (RepeatedMask[i] >= 8)
9615 RepeatedMask[i] -= 4;
9616 return lowerVectorShuffleWithSHUFPS(DL, MVT::v8f32, RepeatedMask, V1, V2, DAG);
9619 // If we have a single input shuffle with different shuffle patterns in the
9620 // two 128-bit lanes use the variable mask to VPERMILPS.
9621 if (isSingleInputShuffleMask(Mask)) {
9622 SDValue VPermMask[8];
9623 for (int i = 0; i < 8; ++i)
9624 VPermMask[i] = Mask[i] < 0 ? DAG.getUNDEF(MVT::i32)
9625 : DAG.getConstant(Mask[i], MVT::i32);
9626 if (!is128BitLaneCrossingShuffleMask(MVT::v8f32, Mask))
9628 X86ISD::VPERMILPV, DL, MVT::v8f32, V1,
9629 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i32, VPermMask));
9631 if (Subtarget->hasAVX2())
9632 return DAG.getNode(X86ISD::VPERMV, DL, MVT::v8f32,
9633 DAG.getNode(ISD::BITCAST, DL, MVT::v8f32,
9634 DAG.getNode(ISD::BUILD_VECTOR, DL,
9635 MVT::v8i32, VPermMask)),
9638 // Otherwise, fall back.
9639 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v8f32, V1, V2, Mask,
9643 // Otherwise fall back on generic blend lowering.
9644 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8f32, V1, V2,
9648 /// \brief Handle lowering of 8-lane 32-bit integer shuffles.
9650 /// This routine is only called when we have AVX2 and thus a reasonable
9651 /// instruction set for v8i32 shuffling..
9652 static SDValue lowerV8I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9653 const X86Subtarget *Subtarget,
9654 SelectionDAG &DAG) {
9656 assert(V1.getSimpleValueType() == MVT::v8i32 && "Bad operand type!");
9657 assert(V2.getSimpleValueType() == MVT::v8i32 && "Bad operand type!");
9658 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9659 ArrayRef<int> Mask = SVOp->getMask();
9660 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
9661 assert(Subtarget->hasAVX2() && "We can only lower v8i32 with AVX2!");
9663 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8i32, V1, V2, Mask,
9667 // If the shuffle mask is repeated in each 128-bit lane we can use more
9668 // efficient instructions that mirror the shuffles across the two 128-bit
9670 SmallVector<int, 4> RepeatedMask;
9671 if (is128BitLaneRepeatedShuffleMask(MVT::v8i32, Mask, RepeatedMask)) {
9672 assert(RepeatedMask.size() == 4 && "Unexpected repeated mask size!");
9673 if (isSingleInputShuffleMask(Mask))
9674 return DAG.getNode(X86ISD::PSHUFD, DL, MVT::v8i32, V1,
9675 getV4X86ShuffleImm8ForMask(RepeatedMask, DAG));
9677 // Use dedicated unpack instructions for masks that match their pattern.
9678 if (isShuffleEquivalent(Mask, 0, 8, 1, 9, 4, 12, 5, 13))
9679 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i32, V1, V2);
9680 if (isShuffleEquivalent(Mask, 2, 10, 3, 11, 6, 14, 7, 15))
9681 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i32, V1, V2);
9684 // If the shuffle patterns aren't repeated but it is a single input, directly
9685 // generate a cross-lane VPERMD instruction.
9686 if (isSingleInputShuffleMask(Mask)) {
9687 SDValue VPermMask[8];
9688 for (int i = 0; i < 8; ++i)
9689 VPermMask[i] = Mask[i] < 0 ? DAG.getUNDEF(MVT::i32)
9690 : DAG.getConstant(Mask[i], MVT::i32);
9692 X86ISD::VPERMV, DL, MVT::v8i32,
9693 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i32, VPermMask), V1);
9696 // Otherwise fall back on generic blend lowering.
9697 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8i32, V1, V2,
9701 /// \brief Handle lowering of 16-lane 16-bit integer shuffles.
9703 /// This routine is only called when we have AVX2 and thus a reasonable
9704 /// instruction set for v16i16 shuffling..
9705 static SDValue lowerV16I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9706 const X86Subtarget *Subtarget,
9707 SelectionDAG &DAG) {
9709 assert(V1.getSimpleValueType() == MVT::v16i16 && "Bad operand type!");
9710 assert(V2.getSimpleValueType() == MVT::v16i16 && "Bad operand type!");
9711 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9712 ArrayRef<int> Mask = SVOp->getMask();
9713 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
9714 assert(Subtarget->hasAVX2() && "We can only lower v16i16 with AVX2!");
9716 // There are no generalized cross-lane shuffle operations available on i16
9718 if (is128BitLaneCrossingShuffleMask(MVT::v16i16, Mask))
9719 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v16i16, V1, V2,
9722 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v16i16, V1, V2, Mask,
9726 // Use dedicated unpack instructions for masks that match their pattern.
9727 if (isShuffleEquivalent(Mask,
9728 // First 128-bit lane:
9729 0, 16, 1, 17, 2, 18, 3, 19,
9730 // Second 128-bit lane:
9731 8, 24, 9, 25, 10, 26, 11, 27))
9732 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i16, V1, V2);
9733 if (isShuffleEquivalent(Mask,
9734 // First 128-bit lane:
9735 4, 20, 5, 21, 6, 22, 7, 23,
9736 // Second 128-bit lane:
9737 12, 28, 13, 29, 14, 30, 15, 31))
9738 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i16, V1, V2);
9740 if (isSingleInputShuffleMask(Mask)) {
9741 SDValue PSHUFBMask[32];
9742 for (int i = 0; i < 16; ++i) {
9743 if (Mask[i] == -1) {
9744 PSHUFBMask[2 * i] = PSHUFBMask[2 * i + 1] = DAG.getUNDEF(MVT::i8);
9748 int M = i < 8 ? Mask[i] : Mask[i] - 8;
9749 assert(M >= 0 && M < 8 && "Invalid single-input mask!");
9750 PSHUFBMask[2 * i] = DAG.getConstant(2 * M, MVT::i8);
9751 PSHUFBMask[2 * i + 1] = DAG.getConstant(2 * M + 1, MVT::i8);
9754 ISD::BITCAST, DL, MVT::v16i16,
9756 X86ISD::PSHUFB, DL, MVT::v32i8,
9757 DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, V1),
9758 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, PSHUFBMask)));
9761 // Otherwise fall back on generic blend lowering.
9762 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v16i16, V1, V2,
9766 /// \brief Handle lowering of 32-lane 8-bit integer shuffles.
9768 /// This routine is only called when we have AVX2 and thus a reasonable
9769 /// instruction set for v32i8 shuffling..
9770 static SDValue lowerV32I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9771 const X86Subtarget *Subtarget,
9772 SelectionDAG &DAG) {
9774 assert(V1.getSimpleValueType() == MVT::v32i8 && "Bad operand type!");
9775 assert(V2.getSimpleValueType() == MVT::v32i8 && "Bad operand type!");
9776 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9777 ArrayRef<int> Mask = SVOp->getMask();
9778 assert(Mask.size() == 32 && "Unexpected mask size for v32 shuffle!");
9779 assert(Subtarget->hasAVX2() && "We can only lower v32i8 with AVX2!");
9781 // There are no generalized cross-lane shuffle operations available on i8
9783 if (is128BitLaneCrossingShuffleMask(MVT::v32i8, Mask))
9784 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v32i8, V1, V2,
9787 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v32i8, V1, V2, Mask,
9791 // Use dedicated unpack instructions for masks that match their pattern.
9792 // Note that these are repeated 128-bit lane unpacks, not unpacks across all
9794 if (isShuffleEquivalent(
9796 // First 128-bit lane:
9797 0, 32, 1, 33, 2, 34, 3, 35, 4, 36, 5, 37, 6, 38, 7, 39,
9798 // Second 128-bit lane:
9799 16, 48, 17, 49, 18, 50, 19, 51, 20, 52, 21, 53, 22, 54, 23, 55))
9800 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v32i8, V1, V2);
9801 if (isShuffleEquivalent(
9803 // First 128-bit lane:
9804 8, 40, 9, 41, 10, 42, 11, 43, 12, 44, 13, 45, 14, 46, 15, 47,
9805 // Second 128-bit lane:
9806 24, 56, 25, 57, 26, 58, 27, 59, 28, 60, 29, 61, 30, 62, 31, 63))
9807 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v32i8, V1, V2);
9809 if (isSingleInputShuffleMask(Mask)) {
9810 SDValue PSHUFBMask[32];
9811 for (int i = 0; i < 32; ++i)
9814 ? DAG.getUNDEF(MVT::i8)
9815 : DAG.getConstant(Mask[i] < 16 ? Mask[i] : Mask[i] - 16, MVT::i8);
9818 X86ISD::PSHUFB, DL, MVT::v32i8, V1,
9819 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, PSHUFBMask));
9822 // Otherwise fall back on generic blend lowering.
9823 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v32i8, V1, V2,
9827 /// \brief High-level routine to lower various 256-bit x86 vector shuffles.
9829 /// This routine either breaks down the specific type of a 256-bit x86 vector
9830 /// shuffle or splits it into two 128-bit shuffles and fuses the results back
9831 /// together based on the available instructions.
9832 static SDValue lower256BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9833 MVT VT, const X86Subtarget *Subtarget,
9834 SelectionDAG &DAG) {
9836 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9837 ArrayRef<int> Mask = SVOp->getMask();
9839 // There is a really nice hard cut-over between AVX1 and AVX2 that means we can
9840 // check for those subtargets here and avoid much of the subtarget querying in
9841 // the per-vector-type lowering routines. With AVX1 we have essentially *zero*
9842 // ability to manipulate a 256-bit vector with integer types. Since we'll use
9843 // floating point types there eventually, just immediately cast everything to
9844 // a float and operate entirely in that domain.
9845 if (VT.isInteger() && !Subtarget->hasAVX2()) {
9846 int ElementBits = VT.getScalarSizeInBits();
9847 if (ElementBits < 32)
9848 // No floating point type available, decompose into 128-bit vectors.
9849 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
9851 MVT FpVT = MVT::getVectorVT(MVT::getFloatingPointVT(ElementBits),
9852 VT.getVectorNumElements());
9853 V1 = DAG.getNode(ISD::BITCAST, DL, FpVT, V1);
9854 V2 = DAG.getNode(ISD::BITCAST, DL, FpVT, V2);
9855 return DAG.getNode(ISD::BITCAST, DL, VT,
9856 DAG.getVectorShuffle(FpVT, DL, V1, V2, Mask));
9859 switch (VT.SimpleTy) {
9861 return lowerV4F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9863 return lowerV4I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9865 return lowerV8F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9867 return lowerV8I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9869 return lowerV16I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
9871 return lowerV32I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
9874 llvm_unreachable("Not a valid 256-bit x86 vector type!");
9878 /// \brief Handle lowering of 8-lane 64-bit floating point shuffles.
9879 static SDValue lowerV8F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9880 const X86Subtarget *Subtarget,
9881 SelectionDAG &DAG) {
9883 assert(V1.getSimpleValueType() == MVT::v8f64 && "Bad operand type!");
9884 assert(V2.getSimpleValueType() == MVT::v8f64 && "Bad operand type!");
9885 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9886 ArrayRef<int> Mask = SVOp->getMask();
9887 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
9889 // FIXME: Implement direct support for this type!
9890 return splitAndLowerVectorShuffle(DL, MVT::v8f64, V1, V2, Mask, DAG);
9893 /// \brief Handle lowering of 16-lane 32-bit floating point shuffles.
9894 static SDValue lowerV16F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9895 const X86Subtarget *Subtarget,
9896 SelectionDAG &DAG) {
9898 assert(V1.getSimpleValueType() == MVT::v16f32 && "Bad operand type!");
9899 assert(V2.getSimpleValueType() == MVT::v16f32 && "Bad operand type!");
9900 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9901 ArrayRef<int> Mask = SVOp->getMask();
9902 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
9904 // FIXME: Implement direct support for this type!
9905 return splitAndLowerVectorShuffle(DL, MVT::v16f32, V1, V2, Mask, DAG);
9908 /// \brief Handle lowering of 8-lane 64-bit integer shuffles.
9909 static SDValue lowerV8I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9910 const X86Subtarget *Subtarget,
9911 SelectionDAG &DAG) {
9913 assert(V1.getSimpleValueType() == MVT::v8i64 && "Bad operand type!");
9914 assert(V2.getSimpleValueType() == MVT::v8i64 && "Bad operand type!");
9915 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9916 ArrayRef<int> Mask = SVOp->getMask();
9917 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
9918 assert(Subtarget->hasDQI() && "We can only lower v8i64 with AVX-512-DQI");
9920 // FIXME: Implement direct support for this type!
9921 return splitAndLowerVectorShuffle(DL, MVT::v8i64, V1, V2, Mask, DAG);
9924 /// \brief Handle lowering of 16-lane 32-bit integer shuffles.
9925 static SDValue lowerV16I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9926 const X86Subtarget *Subtarget,
9927 SelectionDAG &DAG) {
9929 assert(V1.getSimpleValueType() == MVT::v16i32 && "Bad operand type!");
9930 assert(V2.getSimpleValueType() == MVT::v16i32 && "Bad operand type!");
9931 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9932 ArrayRef<int> Mask = SVOp->getMask();
9933 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
9934 assert(Subtarget->hasDQI() && "We can only lower v16i32 with AVX-512-DQI!");
9936 // FIXME: Implement direct support for this type!
9937 return splitAndLowerVectorShuffle(DL, MVT::v16i32, V1, V2, Mask, DAG);
9940 /// \brief Handle lowering of 32-lane 16-bit integer shuffles.
9941 static SDValue lowerV32I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9942 const X86Subtarget *Subtarget,
9943 SelectionDAG &DAG) {
9945 assert(V1.getSimpleValueType() == MVT::v32i16 && "Bad operand type!");
9946 assert(V2.getSimpleValueType() == MVT::v32i16 && "Bad operand type!");
9947 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9948 ArrayRef<int> Mask = SVOp->getMask();
9949 assert(Mask.size() == 32 && "Unexpected mask size for v32 shuffle!");
9950 assert(Subtarget->hasBWI() && "We can only lower v32i16 with AVX-512-BWI!");
9952 // FIXME: Implement direct support for this type!
9953 return splitAndLowerVectorShuffle(DL, MVT::v32i16, V1, V2, Mask, DAG);
9956 /// \brief Handle lowering of 64-lane 8-bit integer shuffles.
9957 static SDValue lowerV64I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9958 const X86Subtarget *Subtarget,
9959 SelectionDAG &DAG) {
9961 assert(V1.getSimpleValueType() == MVT::v64i8 && "Bad operand type!");
9962 assert(V2.getSimpleValueType() == MVT::v64i8 && "Bad operand type!");
9963 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9964 ArrayRef<int> Mask = SVOp->getMask();
9965 assert(Mask.size() == 64 && "Unexpected mask size for v64 shuffle!");
9966 assert(Subtarget->hasBWI() && "We can only lower v64i8 with AVX-512-BWI!");
9968 // FIXME: Implement direct support for this type!
9969 return splitAndLowerVectorShuffle(DL, MVT::v64i8, V1, V2, Mask, DAG);
9972 /// \brief High-level routine to lower various 512-bit x86 vector shuffles.
9974 /// This routine either breaks down the specific type of a 512-bit x86 vector
9975 /// shuffle or splits it into two 256-bit shuffles and fuses the results back
9976 /// together based on the available instructions.
9977 static SDValue lower512BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9978 MVT VT, const X86Subtarget *Subtarget,
9979 SelectionDAG &DAG) {
9981 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9982 ArrayRef<int> Mask = SVOp->getMask();
9983 assert(Subtarget->hasAVX512() &&
9984 "Cannot lower 512-bit vectors w/ basic ISA!");
9986 // Dispatch to each element type for lowering. If we don't have supprot for
9987 // specific element type shuffles at 512 bits, immediately split them and
9988 // lower them. Each lowering routine of a given type is allowed to assume that
9989 // the requisite ISA extensions for that element type are available.
9990 switch (VT.SimpleTy) {
9992 return lowerV8F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9994 return lowerV16F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9996 if (Subtarget->hasDQI())
9997 return lowerV8I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10000 if (Subtarget->hasDQI())
10001 return lowerV16I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10004 if (Subtarget->hasBWI())
10005 return lowerV32I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
10008 if (Subtarget->hasBWI())
10009 return lowerV64I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
10013 llvm_unreachable("Not a valid 512-bit x86 vector type!");
10016 // Otherwise fall back on splitting.
10017 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
10020 /// \brief Helper function to test whether a shuffle mask could be
10021 /// simplified by widening the elements being shuffled.
10023 /// Appends the mask for wider elements in WidenedMask if valid. Otherwise
10024 /// leaves it in an unspecified state.
10026 /// NOTE: This must handle normal vector shuffle masks and *target* vector
10027 /// shuffle masks. The latter have the special property of a '-2' representing
10028 /// a zero-ed lane of a vector.
10029 static bool canWidenShuffleElements(ArrayRef<int> Mask,
10030 SmallVectorImpl<int> &WidenedMask) {
10031 for (int i = 0, Size = Mask.size(); i < Size; i += 2) {
10032 // If both elements are undef, its trivial.
10033 if (Mask[i] == SM_SentinelUndef && Mask[i + 1] == SM_SentinelUndef) {
10034 WidenedMask.push_back(SM_SentinelUndef);
10038 // Check for an undef mask and a mask value properly aligned to fit with
10039 // a pair of values. If we find such a case, use the non-undef mask's value.
10040 if (Mask[i] == SM_SentinelUndef && Mask[i + 1] >= 0 && Mask[i + 1] % 2 == 1) {
10041 WidenedMask.push_back(Mask[i + 1] / 2);
10044 if (Mask[i + 1] == SM_SentinelUndef && Mask[i] >= 0 && Mask[i] % 2 == 0) {
10045 WidenedMask.push_back(Mask[i] / 2);
10049 // When zeroing, we need to spread the zeroing across both lanes to widen.
10050 if (Mask[i] == SM_SentinelZero || Mask[i + 1] == SM_SentinelZero) {
10051 if ((Mask[i] == SM_SentinelZero || Mask[i] == SM_SentinelUndef) &&
10052 (Mask[i + 1] == SM_SentinelZero || Mask[i + 1] == SM_SentinelUndef)) {
10053 WidenedMask.push_back(SM_SentinelZero);
10059 // Finally check if the two mask values are adjacent and aligned with
10061 if (Mask[i] != SM_SentinelUndef && Mask[i] % 2 == 0 && Mask[i] + 1 == Mask[i + 1]) {
10062 WidenedMask.push_back(Mask[i] / 2);
10066 // Otherwise we can't safely widen the elements used in this shuffle.
10069 assert(WidenedMask.size() == Mask.size() / 2 &&
10070 "Incorrect size of mask after widening the elements!");
10075 /// \brief Top-level lowering for x86 vector shuffles.
10077 /// This handles decomposition, canonicalization, and lowering of all x86
10078 /// vector shuffles. Most of the specific lowering strategies are encapsulated
10079 /// above in helper routines. The canonicalization attempts to widen shuffles
10080 /// to involve fewer lanes of wider elements, consolidate symmetric patterns
10081 /// s.t. only one of the two inputs needs to be tested, etc.
10082 static SDValue lowerVectorShuffle(SDValue Op, const X86Subtarget *Subtarget,
10083 SelectionDAG &DAG) {
10084 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10085 ArrayRef<int> Mask = SVOp->getMask();
10086 SDValue V1 = Op.getOperand(0);
10087 SDValue V2 = Op.getOperand(1);
10088 MVT VT = Op.getSimpleValueType();
10089 int NumElements = VT.getVectorNumElements();
10092 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
10094 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
10095 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
10096 if (V1IsUndef && V2IsUndef)
10097 return DAG.getUNDEF(VT);
10099 // When we create a shuffle node we put the UNDEF node to second operand,
10100 // but in some cases the first operand may be transformed to UNDEF.
10101 // In this case we should just commute the node.
10103 return DAG.getCommutedVectorShuffle(*SVOp);
10105 // Check for non-undef masks pointing at an undef vector and make the masks
10106 // undef as well. This makes it easier to match the shuffle based solely on
10110 if (M >= NumElements) {
10111 SmallVector<int, 8> NewMask(Mask.begin(), Mask.end());
10112 for (int &M : NewMask)
10113 if (M >= NumElements)
10115 return DAG.getVectorShuffle(VT, dl, V1, V2, NewMask);
10118 // For integer vector shuffles, try to collapse them into a shuffle of fewer
10119 // lanes but wider integers. We cap this to not form integers larger than i64
10120 // but it might be interesting to form i128 integers to handle flipping the
10121 // low and high halves of AVX 256-bit vectors.
10122 SmallVector<int, 16> WidenedMask;
10123 if (VT.isInteger() && VT.getScalarSizeInBits() < 64 &&
10124 canWidenShuffleElements(Mask, WidenedMask)) {
10126 MVT::getVectorVT(MVT::getIntegerVT(VT.getScalarSizeInBits() * 2),
10127 VT.getVectorNumElements() / 2);
10128 V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, V1);
10129 V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, V2);
10130 return DAG.getNode(ISD::BITCAST, dl, VT,
10131 DAG.getVectorShuffle(NewVT, dl, V1, V2, WidenedMask));
10134 int NumV1Elements = 0, NumUndefElements = 0, NumV2Elements = 0;
10135 for (int M : SVOp->getMask())
10137 ++NumUndefElements;
10138 else if (M < NumElements)
10143 // Commute the shuffle as needed such that more elements come from V1 than
10144 // V2. This allows us to match the shuffle pattern strictly on how many
10145 // elements come from V1 without handling the symmetric cases.
10146 if (NumV2Elements > NumV1Elements)
10147 return DAG.getCommutedVectorShuffle(*SVOp);
10149 // When the number of V1 and V2 elements are the same, try to minimize the
10150 // number of uses of V2 in the low half of the vector. When that is tied,
10151 // ensure that the sum of indices for V1 is equal to or lower than the sum
10153 if (NumV1Elements == NumV2Elements) {
10154 int LowV1Elements = 0, LowV2Elements = 0;
10155 for (int M : SVOp->getMask().slice(0, NumElements / 2))
10156 if (M >= NumElements)
10160 if (LowV2Elements > LowV1Elements) {
10161 return DAG.getCommutedVectorShuffle(*SVOp);
10162 } else if (LowV2Elements == LowV1Elements) {
10163 int SumV1Indices = 0, SumV2Indices = 0;
10164 for (int i = 0, Size = SVOp->getMask().size(); i < Size; ++i)
10165 if (SVOp->getMask()[i] >= NumElements)
10167 else if (SVOp->getMask()[i] >= 0)
10169 if (SumV2Indices < SumV1Indices)
10170 return DAG.getCommutedVectorShuffle(*SVOp);
10174 // For each vector width, delegate to a specialized lowering routine.
10175 if (VT.getSizeInBits() == 128)
10176 return lower128BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
10178 if (VT.getSizeInBits() == 256)
10179 return lower256BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
10181 // Force AVX-512 vectors to be scalarized for now.
10182 // FIXME: Implement AVX-512 support!
10183 if (VT.getSizeInBits() == 512)
10184 return lower512BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
10186 llvm_unreachable("Unimplemented!");
10190 //===----------------------------------------------------------------------===//
10191 // Legacy vector shuffle lowering
10193 // This code is the legacy code handling vector shuffles until the above
10194 // replaces its functionality and performance.
10195 //===----------------------------------------------------------------------===//
10197 static bool isBlendMask(ArrayRef<int> MaskVals, MVT VT, bool hasSSE41,
10198 bool hasInt256, unsigned *MaskOut = nullptr) {
10199 MVT EltVT = VT.getVectorElementType();
10201 // There is no blend with immediate in AVX-512.
10202 if (VT.is512BitVector())
10205 if (!hasSSE41 || EltVT == MVT::i8)
10207 if (!hasInt256 && VT == MVT::v16i16)
10210 unsigned MaskValue = 0;
10211 unsigned NumElems = VT.getVectorNumElements();
10212 // There are 2 lanes if (NumElems > 8), and 1 lane otherwise.
10213 unsigned NumLanes = (NumElems - 1) / 8 + 1;
10214 unsigned NumElemsInLane = NumElems / NumLanes;
10216 // Blend for v16i16 should be symetric for the both lanes.
10217 for (unsigned i = 0; i < NumElemsInLane; ++i) {
10219 int SndLaneEltIdx = (NumLanes == 2) ? MaskVals[i + NumElemsInLane] : -1;
10220 int EltIdx = MaskVals[i];
10222 if ((EltIdx < 0 || EltIdx == (int)i) &&
10223 (SndLaneEltIdx < 0 || SndLaneEltIdx == (int)(i + NumElemsInLane)))
10226 if (((unsigned)EltIdx == (i + NumElems)) &&
10227 (SndLaneEltIdx < 0 ||
10228 (unsigned)SndLaneEltIdx == i + NumElems + NumElemsInLane))
10229 MaskValue |= (1 << i);
10235 *MaskOut = MaskValue;
10239 // Try to lower a shuffle node into a simple blend instruction.
10240 // This function assumes isBlendMask returns true for this
10241 // SuffleVectorSDNode
10242 static SDValue LowerVECTOR_SHUFFLEtoBlend(ShuffleVectorSDNode *SVOp,
10243 unsigned MaskValue,
10244 const X86Subtarget *Subtarget,
10245 SelectionDAG &DAG) {
10246 MVT VT = SVOp->getSimpleValueType(0);
10247 MVT EltVT = VT.getVectorElementType();
10248 assert(isBlendMask(SVOp->getMask(), VT, Subtarget->hasSSE41(),
10249 Subtarget->hasInt256() && "Trying to lower a "
10250 "VECTOR_SHUFFLE to a Blend but "
10251 "with the wrong mask"));
10252 SDValue V1 = SVOp->getOperand(0);
10253 SDValue V2 = SVOp->getOperand(1);
10255 unsigned NumElems = VT.getVectorNumElements();
10257 // Convert i32 vectors to floating point if it is not AVX2.
10258 // AVX2 introduced VPBLENDD instruction for 128 and 256-bit vectors.
10260 if (EltVT == MVT::i64 || (EltVT == MVT::i32 && !Subtarget->hasInt256())) {
10261 BlendVT = MVT::getVectorVT(MVT::getFloatingPointVT(EltVT.getSizeInBits()),
10263 V1 = DAG.getNode(ISD::BITCAST, dl, VT, V1);
10264 V2 = DAG.getNode(ISD::BITCAST, dl, VT, V2);
10267 SDValue Ret = DAG.getNode(X86ISD::BLENDI, dl, BlendVT, V1, V2,
10268 DAG.getConstant(MaskValue, MVT::i32));
10269 return DAG.getNode(ISD::BITCAST, dl, VT, Ret);
10272 /// In vector type \p VT, return true if the element at index \p InputIdx
10273 /// falls on a different 128-bit lane than \p OutputIdx.
10274 static bool ShuffleCrosses128bitLane(MVT VT, unsigned InputIdx,
10275 unsigned OutputIdx) {
10276 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
10277 return InputIdx * EltSize / 128 != OutputIdx * EltSize / 128;
10280 /// Generate a PSHUFB if possible. Selects elements from \p V1 according to
10281 /// \p MaskVals. MaskVals[OutputIdx] = InputIdx specifies that we want to
10282 /// shuffle the element at InputIdx in V1 to OutputIdx in the result. If \p
10283 /// MaskVals refers to elements outside of \p V1 or is undef (-1), insert a
10285 static SDValue getPSHUFB(ArrayRef<int> MaskVals, SDValue V1, SDLoc &dl,
10286 SelectionDAG &DAG) {
10287 MVT VT = V1.getSimpleValueType();
10288 assert(VT.is128BitVector() || VT.is256BitVector());
10290 MVT EltVT = VT.getVectorElementType();
10291 unsigned EltSizeInBytes = EltVT.getSizeInBits() / 8;
10292 unsigned NumElts = VT.getVectorNumElements();
10294 SmallVector<SDValue, 32> PshufbMask;
10295 for (unsigned OutputIdx = 0; OutputIdx < NumElts; ++OutputIdx) {
10296 int InputIdx = MaskVals[OutputIdx];
10297 unsigned InputByteIdx;
10299 if (InputIdx < 0 || NumElts <= (unsigned)InputIdx)
10300 InputByteIdx = 0x80;
10302 // Cross lane is not allowed.
10303 if (ShuffleCrosses128bitLane(VT, InputIdx, OutputIdx))
10305 InputByteIdx = InputIdx * EltSizeInBytes;
10306 // Index is an byte offset within the 128-bit lane.
10307 InputByteIdx &= 0xf;
10310 for (unsigned j = 0; j < EltSizeInBytes; ++j) {
10311 PshufbMask.push_back(DAG.getConstant(InputByteIdx, MVT::i8));
10312 if (InputByteIdx != 0x80)
10317 MVT ShufVT = MVT::getVectorVT(MVT::i8, PshufbMask.size());
10319 V1 = DAG.getNode(ISD::BITCAST, dl, ShufVT, V1);
10320 return DAG.getNode(X86ISD::PSHUFB, dl, ShufVT, V1,
10321 DAG.getNode(ISD::BUILD_VECTOR, dl, ShufVT, PshufbMask));
10324 // v8i16 shuffles - Prefer shuffles in the following order:
10325 // 1. [all] pshuflw, pshufhw, optional move
10326 // 2. [ssse3] 1 x pshufb
10327 // 3. [ssse3] 2 x pshufb + 1 x por
10328 // 4. [all] mov + pshuflw + pshufhw + N x (pextrw + pinsrw)
10330 LowerVECTOR_SHUFFLEv8i16(SDValue Op, const X86Subtarget *Subtarget,
10331 SelectionDAG &DAG) {
10332 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10333 SDValue V1 = SVOp->getOperand(0);
10334 SDValue V2 = SVOp->getOperand(1);
10336 SmallVector<int, 8> MaskVals;
10338 // Determine if more than 1 of the words in each of the low and high quadwords
10339 // of the result come from the same quadword of one of the two inputs. Undef
10340 // mask values count as coming from any quadword, for better codegen.
10342 // Lo/HiQuad[i] = j indicates how many words from the ith quad of the input
10343 // feeds this quad. For i, 0 and 1 refer to V1, 2 and 3 refer to V2.
10344 unsigned LoQuad[] = { 0, 0, 0, 0 };
10345 unsigned HiQuad[] = { 0, 0, 0, 0 };
10346 // Indices of quads used.
10347 std::bitset<4> InputQuads;
10348 for (unsigned i = 0; i < 8; ++i) {
10349 unsigned *Quad = i < 4 ? LoQuad : HiQuad;
10350 int EltIdx = SVOp->getMaskElt(i);
10351 MaskVals.push_back(EltIdx);
10359 ++Quad[EltIdx / 4];
10360 InputQuads.set(EltIdx / 4);
10363 int BestLoQuad = -1;
10364 unsigned MaxQuad = 1;
10365 for (unsigned i = 0; i < 4; ++i) {
10366 if (LoQuad[i] > MaxQuad) {
10368 MaxQuad = LoQuad[i];
10372 int BestHiQuad = -1;
10374 for (unsigned i = 0; i < 4; ++i) {
10375 if (HiQuad[i] > MaxQuad) {
10377 MaxQuad = HiQuad[i];
10381 // For SSSE3, If all 8 words of the result come from only 1 quadword of each
10382 // of the two input vectors, shuffle them into one input vector so only a
10383 // single pshufb instruction is necessary. If there are more than 2 input
10384 // quads, disable the next transformation since it does not help SSSE3.
10385 bool V1Used = InputQuads[0] || InputQuads[1];
10386 bool V2Used = InputQuads[2] || InputQuads[3];
10387 if (Subtarget->hasSSSE3()) {
10388 if (InputQuads.count() == 2 && V1Used && V2Used) {
10389 BestLoQuad = InputQuads[0] ? 0 : 1;
10390 BestHiQuad = InputQuads[2] ? 2 : 3;
10392 if (InputQuads.count() > 2) {
10398 // If BestLoQuad or BestHiQuad are set, shuffle the quads together and update
10399 // the shuffle mask. If a quad is scored as -1, that means that it contains
10400 // words from all 4 input quadwords.
10402 if (BestLoQuad >= 0 || BestHiQuad >= 0) {
10404 BestLoQuad < 0 ? 0 : BestLoQuad,
10405 BestHiQuad < 0 ? 1 : BestHiQuad
10407 NewV = DAG.getVectorShuffle(MVT::v2i64, dl,
10408 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V1),
10409 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V2), &MaskV[0]);
10410 NewV = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, NewV);
10412 // Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the
10413 // source words for the shuffle, to aid later transformations.
10414 bool AllWordsInNewV = true;
10415 bool InOrder[2] = { true, true };
10416 for (unsigned i = 0; i != 8; ++i) {
10417 int idx = MaskVals[i];
10419 InOrder[i/4] = false;
10420 if (idx < 0 || (idx/4) == BestLoQuad || (idx/4) == BestHiQuad)
10422 AllWordsInNewV = false;
10426 bool pshuflw = AllWordsInNewV, pshufhw = AllWordsInNewV;
10427 if (AllWordsInNewV) {
10428 for (int i = 0; i != 8; ++i) {
10429 int idx = MaskVals[i];
10432 idx = MaskVals[i] = (idx / 4) == BestLoQuad ? (idx & 3) : (idx & 3) + 4;
10433 if ((idx != i) && idx < 4)
10435 if ((idx != i) && idx > 3)
10444 // If we've eliminated the use of V2, and the new mask is a pshuflw or
10445 // pshufhw, that's as cheap as it gets. Return the new shuffle.
10446 if ((pshufhw && InOrder[0]) || (pshuflw && InOrder[1])) {
10447 unsigned Opc = pshufhw ? X86ISD::PSHUFHW : X86ISD::PSHUFLW;
10448 unsigned TargetMask = 0;
10449 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV,
10450 DAG.getUNDEF(MVT::v8i16), &MaskVals[0]);
10451 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
10452 TargetMask = pshufhw ? getShufflePSHUFHWImmediate(SVOp):
10453 getShufflePSHUFLWImmediate(SVOp);
10454 V1 = NewV.getOperand(0);
10455 return getTargetShuffleNode(Opc, dl, MVT::v8i16, V1, TargetMask, DAG);
10459 // Promote splats to a larger type which usually leads to more efficient code.
10460 // FIXME: Is this true if pshufb is available?
10461 if (SVOp->isSplat())
10462 return PromoteSplat(SVOp, DAG);
10464 // If we have SSSE3, and all words of the result are from 1 input vector,
10465 // case 2 is generated, otherwise case 3 is generated. If no SSSE3
10466 // is present, fall back to case 4.
10467 if (Subtarget->hasSSSE3()) {
10468 SmallVector<SDValue,16> pshufbMask;
10470 // If we have elements from both input vectors, set the high bit of the
10471 // shuffle mask element to zero out elements that come from V2 in the V1
10472 // mask, and elements that come from V1 in the V2 mask, so that the two
10473 // results can be OR'd together.
10474 bool TwoInputs = V1Used && V2Used;
10475 V1 = getPSHUFB(MaskVals, V1, dl, DAG);
10477 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
10479 // Calculate the shuffle mask for the second input, shuffle it, and
10480 // OR it with the first shuffled input.
10481 CommuteVectorShuffleMask(MaskVals, 8);
10482 V2 = getPSHUFB(MaskVals, V2, dl, DAG);
10483 V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
10484 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
10487 // If BestLoQuad >= 0, generate a pshuflw to put the low elements in order,
10488 // and update MaskVals with new element order.
10489 std::bitset<8> InOrder;
10490 if (BestLoQuad >= 0) {
10491 int MaskV[] = { -1, -1, -1, -1, 4, 5, 6, 7 };
10492 for (int i = 0; i != 4; ++i) {
10493 int idx = MaskVals[i];
10496 } else if ((idx / 4) == BestLoQuad) {
10497 MaskV[i] = idx & 3;
10501 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
10504 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSE2()) {
10505 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
10506 NewV = getTargetShuffleNode(X86ISD::PSHUFLW, dl, MVT::v8i16,
10507 NewV.getOperand(0),
10508 getShufflePSHUFLWImmediate(SVOp), DAG);
10512 // If BestHi >= 0, generate a pshufhw to put the high elements in order,
10513 // and update MaskVals with the new element order.
10514 if (BestHiQuad >= 0) {
10515 int MaskV[] = { 0, 1, 2, 3, -1, -1, -1, -1 };
10516 for (unsigned i = 4; i != 8; ++i) {
10517 int idx = MaskVals[i];
10520 } else if ((idx / 4) == BestHiQuad) {
10521 MaskV[i] = (idx & 3) + 4;
10525 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
10528 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSE2()) {
10529 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
10530 NewV = getTargetShuffleNode(X86ISD::PSHUFHW, dl, MVT::v8i16,
10531 NewV.getOperand(0),
10532 getShufflePSHUFHWImmediate(SVOp), DAG);
10536 // In case BestHi & BestLo were both -1, which means each quadword has a word
10537 // from each of the four input quadwords, calculate the InOrder bitvector now
10538 // before falling through to the insert/extract cleanup.
10539 if (BestLoQuad == -1 && BestHiQuad == -1) {
10541 for (int i = 0; i != 8; ++i)
10542 if (MaskVals[i] < 0 || MaskVals[i] == i)
10546 // The other elements are put in the right place using pextrw and pinsrw.
10547 for (unsigned i = 0; i != 8; ++i) {
10550 int EltIdx = MaskVals[i];
10553 SDValue ExtOp = (EltIdx < 8) ?
10554 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1,
10555 DAG.getIntPtrConstant(EltIdx)) :
10556 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2,
10557 DAG.getIntPtrConstant(EltIdx - 8));
10558 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp,
10559 DAG.getIntPtrConstant(i));
10564 /// \brief v16i16 shuffles
10566 /// FIXME: We only support generation of a single pshufb currently. We can
10567 /// generalize the other applicable cases from LowerVECTOR_SHUFFLEv8i16 as
10568 /// well (e.g 2 x pshufb + 1 x por).
10570 LowerVECTOR_SHUFFLEv16i16(SDValue Op, SelectionDAG &DAG) {
10571 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10572 SDValue V1 = SVOp->getOperand(0);
10573 SDValue V2 = SVOp->getOperand(1);
10576 if (V2.getOpcode() != ISD::UNDEF)
10579 SmallVector<int, 16> MaskVals(SVOp->getMask().begin(), SVOp->getMask().end());
10580 return getPSHUFB(MaskVals, V1, dl, DAG);
10583 // v16i8 shuffles - Prefer shuffles in the following order:
10584 // 1. [ssse3] 1 x pshufb
10585 // 2. [ssse3] 2 x pshufb + 1 x por
10586 // 3. [all] v8i16 shuffle + N x pextrw + rotate + pinsrw
10587 static SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp,
10588 const X86Subtarget* Subtarget,
10589 SelectionDAG &DAG) {
10590 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
10591 SDValue V1 = SVOp->getOperand(0);
10592 SDValue V2 = SVOp->getOperand(1);
10594 ArrayRef<int> MaskVals = SVOp->getMask();
10596 // Promote splats to a larger type which usually leads to more efficient code.
10597 // FIXME: Is this true if pshufb is available?
10598 if (SVOp->isSplat())
10599 return PromoteSplat(SVOp, DAG);
10601 // If we have SSSE3, case 1 is generated when all result bytes come from
10602 // one of the inputs. Otherwise, case 2 is generated. If no SSSE3 is
10603 // present, fall back to case 3.
10605 // If SSSE3, use 1 pshufb instruction per vector with elements in the result.
10606 if (Subtarget->hasSSSE3()) {
10607 SmallVector<SDValue,16> pshufbMask;
10609 // If all result elements are from one input vector, then only translate
10610 // undef mask values to 0x80 (zero out result) in the pshufb mask.
10612 // Otherwise, we have elements from both input vectors, and must zero out
10613 // elements that come from V2 in the first mask, and V1 in the second mask
10614 // so that we can OR them together.
10615 for (unsigned i = 0; i != 16; ++i) {
10616 int EltIdx = MaskVals[i];
10617 if (EltIdx < 0 || EltIdx >= 16)
10619 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
10621 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
10622 DAG.getNode(ISD::BUILD_VECTOR, dl,
10623 MVT::v16i8, pshufbMask));
10625 // As PSHUFB will zero elements with negative indices, it's safe to ignore
10626 // the 2nd operand if it's undefined or zero.
10627 if (V2.getOpcode() == ISD::UNDEF ||
10628 ISD::isBuildVectorAllZeros(V2.getNode()))
10631 // Calculate the shuffle mask for the second input, shuffle it, and
10632 // OR it with the first shuffled input.
10633 pshufbMask.clear();
10634 for (unsigned i = 0; i != 16; ++i) {
10635 int EltIdx = MaskVals[i];
10636 EltIdx = (EltIdx < 16) ? 0x80 : EltIdx - 16;
10637 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
10639 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
10640 DAG.getNode(ISD::BUILD_VECTOR, dl,
10641 MVT::v16i8, pshufbMask));
10642 return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
10645 // No SSSE3 - Calculate in place words and then fix all out of place words
10646 // With 0-16 extracts & inserts. Worst case is 16 bytes out of order from
10647 // the 16 different words that comprise the two doublequadword input vectors.
10648 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
10649 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V2);
10651 for (int i = 0; i != 8; ++i) {
10652 int Elt0 = MaskVals[i*2];
10653 int Elt1 = MaskVals[i*2+1];
10655 // This word of the result is all undef, skip it.
10656 if (Elt0 < 0 && Elt1 < 0)
10659 // This word of the result is already in the correct place, skip it.
10660 if ((Elt0 == i*2) && (Elt1 == i*2+1))
10663 SDValue Elt0Src = Elt0 < 16 ? V1 : V2;
10664 SDValue Elt1Src = Elt1 < 16 ? V1 : V2;
10667 // If Elt0 and Elt1 are defined, are consecutive, and can be load
10668 // using a single extract together, load it and store it.
10669 if ((Elt0 >= 0) && ((Elt0 + 1) == Elt1) && ((Elt0 & 1) == 0)) {
10670 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
10671 DAG.getIntPtrConstant(Elt1 / 2));
10672 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
10673 DAG.getIntPtrConstant(i));
10677 // If Elt1 is defined, extract it from the appropriate source. If the
10678 // source byte is not also odd, shift the extracted word left 8 bits
10679 // otherwise clear the bottom 8 bits if we need to do an or.
10681 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
10682 DAG.getIntPtrConstant(Elt1 / 2));
10683 if ((Elt1 & 1) == 0)
10684 InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt,
10686 TLI.getShiftAmountTy(InsElt.getValueType())));
10687 else if (Elt0 >= 0)
10688 InsElt = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt,
10689 DAG.getConstant(0xFF00, MVT::i16));
10691 // If Elt0 is defined, extract it from the appropriate source. If the
10692 // source byte is not also even, shift the extracted word right 8 bits. If
10693 // Elt1 was also defined, OR the extracted values together before
10694 // inserting them in the result.
10696 SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16,
10697 Elt0Src, DAG.getIntPtrConstant(Elt0 / 2));
10698 if ((Elt0 & 1) != 0)
10699 InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0,
10701 TLI.getShiftAmountTy(InsElt0.getValueType())));
10702 else if (Elt1 >= 0)
10703 InsElt0 = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt0,
10704 DAG.getConstant(0x00FF, MVT::i16));
10705 InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0)
10708 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
10709 DAG.getIntPtrConstant(i));
10711 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, NewV);
10714 // v32i8 shuffles - Translate to VPSHUFB if possible.
10716 SDValue LowerVECTOR_SHUFFLEv32i8(ShuffleVectorSDNode *SVOp,
10717 const X86Subtarget *Subtarget,
10718 SelectionDAG &DAG) {
10719 MVT VT = SVOp->getSimpleValueType(0);
10720 SDValue V1 = SVOp->getOperand(0);
10721 SDValue V2 = SVOp->getOperand(1);
10723 SmallVector<int, 32> MaskVals(SVOp->getMask().begin(), SVOp->getMask().end());
10725 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
10726 bool V1IsAllZero = ISD::isBuildVectorAllZeros(V1.getNode());
10727 bool V2IsAllZero = ISD::isBuildVectorAllZeros(V2.getNode());
10729 // VPSHUFB may be generated if
10730 // (1) one of input vector is undefined or zeroinitializer.
10731 // The mask value 0x80 puts 0 in the corresponding slot of the vector.
10732 // And (2) the mask indexes don't cross the 128-bit lane.
10733 if (VT != MVT::v32i8 || !Subtarget->hasInt256() ||
10734 (!V2IsUndef && !V2IsAllZero && !V1IsAllZero))
10737 if (V1IsAllZero && !V2IsAllZero) {
10738 CommuteVectorShuffleMask(MaskVals, 32);
10741 return getPSHUFB(MaskVals, V1, dl, DAG);
10744 /// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide
10745 /// ones, or rewriting v4i32 / v4f32 as 2 wide ones if possible. This can be
10746 /// done when every pair / quad of shuffle mask elements point to elements in
10747 /// the right sequence. e.g.
10748 /// vector_shuffle X, Y, <2, 3, | 10, 11, | 0, 1, | 14, 15>
10750 SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp,
10751 SelectionDAG &DAG) {
10752 MVT VT = SVOp->getSimpleValueType(0);
10754 unsigned NumElems = VT.getVectorNumElements();
10757 switch (VT.SimpleTy) {
10758 default: llvm_unreachable("Unexpected!");
10761 return SDValue(SVOp, 0);
10762 case MVT::v4f32: NewVT = MVT::v2f64; Scale = 2; break;
10763 case MVT::v4i32: NewVT = MVT::v2i64; Scale = 2; break;
10764 case MVT::v8i16: NewVT = MVT::v4i32; Scale = 2; break;
10765 case MVT::v16i8: NewVT = MVT::v4i32; Scale = 4; break;
10766 case MVT::v16i16: NewVT = MVT::v8i32; Scale = 2; break;
10767 case MVT::v32i8: NewVT = MVT::v8i32; Scale = 4; break;
10770 SmallVector<int, 8> MaskVec;
10771 for (unsigned i = 0; i != NumElems; i += Scale) {
10773 for (unsigned j = 0; j != Scale; ++j) {
10774 int EltIdx = SVOp->getMaskElt(i+j);
10778 StartIdx = (EltIdx / Scale);
10779 if (EltIdx != (int)(StartIdx*Scale + j))
10782 MaskVec.push_back(StartIdx);
10785 SDValue V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(0));
10786 SDValue V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(1));
10787 return DAG.getVectorShuffle(NewVT, dl, V1, V2, &MaskVec[0]);
10790 /// getVZextMovL - Return a zero-extending vector move low node.
10792 static SDValue getVZextMovL(MVT VT, MVT OpVT,
10793 SDValue SrcOp, SelectionDAG &DAG,
10794 const X86Subtarget *Subtarget, SDLoc dl) {
10795 if (VT == MVT::v2f64 || VT == MVT::v4f32) {
10796 LoadSDNode *LD = nullptr;
10797 if (!isScalarLoadToVector(SrcOp.getNode(), &LD))
10798 LD = dyn_cast<LoadSDNode>(SrcOp);
10800 // movssrr and movsdrr do not clear top bits. Try to use movd, movq
10802 MVT ExtVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32;
10803 if ((ExtVT != MVT::i64 || Subtarget->is64Bit()) &&
10804 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR &&
10805 SrcOp.getOperand(0).getOpcode() == ISD::BITCAST &&
10806 SrcOp.getOperand(0).getOperand(0).getValueType() == ExtVT) {
10808 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32;
10809 return DAG.getNode(ISD::BITCAST, dl, VT,
10810 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
10811 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
10813 SrcOp.getOperand(0)
10819 return DAG.getNode(ISD::BITCAST, dl, VT,
10820 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
10821 DAG.getNode(ISD::BITCAST, dl,
10825 /// LowerVECTOR_SHUFFLE_256 - Handle all 256-bit wide vectors shuffles
10826 /// which could not be matched by any known target speficic shuffle
10828 LowerVECTOR_SHUFFLE_256(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
10830 SDValue NewOp = Compact8x32ShuffleNode(SVOp, DAG);
10831 if (NewOp.getNode())
10834 MVT VT = SVOp->getSimpleValueType(0);
10836 unsigned NumElems = VT.getVectorNumElements();
10837 unsigned NumLaneElems = NumElems / 2;
10840 MVT EltVT = VT.getVectorElementType();
10841 MVT NVT = MVT::getVectorVT(EltVT, NumLaneElems);
10844 SmallVector<int, 16> Mask;
10845 for (unsigned l = 0; l < 2; ++l) {
10846 // Build a shuffle mask for the output, discovering on the fly which
10847 // input vectors to use as shuffle operands (recorded in InputUsed).
10848 // If building a suitable shuffle vector proves too hard, then bail
10849 // out with UseBuildVector set.
10850 bool UseBuildVector = false;
10851 int InputUsed[2] = { -1, -1 }; // Not yet discovered.
10852 unsigned LaneStart = l * NumLaneElems;
10853 for (unsigned i = 0; i != NumLaneElems; ++i) {
10854 // The mask element. This indexes into the input.
10855 int Idx = SVOp->getMaskElt(i+LaneStart);
10857 // the mask element does not index into any input vector.
10858 Mask.push_back(-1);
10862 // The input vector this mask element indexes into.
10863 int Input = Idx / NumLaneElems;
10865 // Turn the index into an offset from the start of the input vector.
10866 Idx -= Input * NumLaneElems;
10868 // Find or create a shuffle vector operand to hold this input.
10870 for (OpNo = 0; OpNo < array_lengthof(InputUsed); ++OpNo) {
10871 if (InputUsed[OpNo] == Input)
10872 // This input vector is already an operand.
10874 if (InputUsed[OpNo] < 0) {
10875 // Create a new operand for this input vector.
10876 InputUsed[OpNo] = Input;
10881 if (OpNo >= array_lengthof(InputUsed)) {
10882 // More than two input vectors used! Give up on trying to create a
10883 // shuffle vector. Insert all elements into a BUILD_VECTOR instead.
10884 UseBuildVector = true;
10888 // Add the mask index for the new shuffle vector.
10889 Mask.push_back(Idx + OpNo * NumLaneElems);
10892 if (UseBuildVector) {
10893 SmallVector<SDValue, 16> SVOps;
10894 for (unsigned i = 0; i != NumLaneElems; ++i) {
10895 // The mask element. This indexes into the input.
10896 int Idx = SVOp->getMaskElt(i+LaneStart);
10898 SVOps.push_back(DAG.getUNDEF(EltVT));
10902 // The input vector this mask element indexes into.
10903 int Input = Idx / NumElems;
10905 // Turn the index into an offset from the start of the input vector.
10906 Idx -= Input * NumElems;
10908 // Extract the vector element by hand.
10909 SVOps.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
10910 SVOp->getOperand(Input),
10911 DAG.getIntPtrConstant(Idx)));
10914 // Construct the output using a BUILD_VECTOR.
10915 Output[l] = DAG.getNode(ISD::BUILD_VECTOR, dl, NVT, SVOps);
10916 } else if (InputUsed[0] < 0) {
10917 // No input vectors were used! The result is undefined.
10918 Output[l] = DAG.getUNDEF(NVT);
10920 SDValue Op0 = Extract128BitVector(SVOp->getOperand(InputUsed[0] / 2),
10921 (InputUsed[0] % 2) * NumLaneElems,
10923 // If only one input was used, use an undefined vector for the other.
10924 SDValue Op1 = (InputUsed[1] < 0) ? DAG.getUNDEF(NVT) :
10925 Extract128BitVector(SVOp->getOperand(InputUsed[1] / 2),
10926 (InputUsed[1] % 2) * NumLaneElems, DAG, dl);
10927 // At least one input vector was used. Create a new shuffle vector.
10928 Output[l] = DAG.getVectorShuffle(NVT, dl, Op0, Op1, &Mask[0]);
10934 // Concatenate the result back
10935 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, Output[0], Output[1]);
10938 /// LowerVECTOR_SHUFFLE_128v4 - Handle all 128-bit wide vectors with
10939 /// 4 elements, and match them with several different shuffle types.
10941 LowerVECTOR_SHUFFLE_128v4(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
10942 SDValue V1 = SVOp->getOperand(0);
10943 SDValue V2 = SVOp->getOperand(1);
10945 MVT VT = SVOp->getSimpleValueType(0);
10947 assert(VT.is128BitVector() && "Unsupported vector size");
10949 std::pair<int, int> Locs[4];
10950 int Mask1[] = { -1, -1, -1, -1 };
10951 SmallVector<int, 8> PermMask(SVOp->getMask().begin(), SVOp->getMask().end());
10953 unsigned NumHi = 0;
10954 unsigned NumLo = 0;
10955 for (unsigned i = 0; i != 4; ++i) {
10956 int Idx = PermMask[i];
10958 Locs[i] = std::make_pair(-1, -1);
10960 assert(Idx < 8 && "Invalid VECTOR_SHUFFLE index!");
10962 Locs[i] = std::make_pair(0, NumLo);
10963 Mask1[NumLo] = Idx;
10966 Locs[i] = std::make_pair(1, NumHi);
10968 Mask1[2+NumHi] = Idx;
10974 if (NumLo <= 2 && NumHi <= 2) {
10975 // If no more than two elements come from either vector. This can be
10976 // implemented with two shuffles. First shuffle gather the elements.
10977 // The second shuffle, which takes the first shuffle as both of its
10978 // vector operands, put the elements into the right order.
10979 V1 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
10981 int Mask2[] = { -1, -1, -1, -1 };
10983 for (unsigned i = 0; i != 4; ++i)
10984 if (Locs[i].first != -1) {
10985 unsigned Idx = (i < 2) ? 0 : 4;
10986 Idx += Locs[i].first * 2 + Locs[i].second;
10990 return DAG.getVectorShuffle(VT, dl, V1, V1, &Mask2[0]);
10993 if (NumLo == 3 || NumHi == 3) {
10994 // Otherwise, we must have three elements from one vector, call it X, and
10995 // one element from the other, call it Y. First, use a shufps to build an
10996 // intermediate vector with the one element from Y and the element from X
10997 // that will be in the same half in the final destination (the indexes don't
10998 // matter). Then, use a shufps to build the final vector, taking the half
10999 // containing the element from Y from the intermediate, and the other half
11002 // Normalize it so the 3 elements come from V1.
11003 CommuteVectorShuffleMask(PermMask, 4);
11007 // Find the element from V2.
11009 for (HiIndex = 0; HiIndex < 3; ++HiIndex) {
11010 int Val = PermMask[HiIndex];
11017 Mask1[0] = PermMask[HiIndex];
11019 Mask1[2] = PermMask[HiIndex^1];
11021 V2 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
11023 if (HiIndex >= 2) {
11024 Mask1[0] = PermMask[0];
11025 Mask1[1] = PermMask[1];
11026 Mask1[2] = HiIndex & 1 ? 6 : 4;
11027 Mask1[3] = HiIndex & 1 ? 4 : 6;
11028 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
11031 Mask1[0] = HiIndex & 1 ? 2 : 0;
11032 Mask1[1] = HiIndex & 1 ? 0 : 2;
11033 Mask1[2] = PermMask[2];
11034 Mask1[3] = PermMask[3];
11039 return DAG.getVectorShuffle(VT, dl, V2, V1, &Mask1[0]);
11042 // Break it into (shuffle shuffle_hi, shuffle_lo).
11043 int LoMask[] = { -1, -1, -1, -1 };
11044 int HiMask[] = { -1, -1, -1, -1 };
11046 int *MaskPtr = LoMask;
11047 unsigned MaskIdx = 0;
11048 unsigned LoIdx = 0;
11049 unsigned HiIdx = 2;
11050 for (unsigned i = 0; i != 4; ++i) {
11057 int Idx = PermMask[i];
11059 Locs[i] = std::make_pair(-1, -1);
11060 } else if (Idx < 4) {
11061 Locs[i] = std::make_pair(MaskIdx, LoIdx);
11062 MaskPtr[LoIdx] = Idx;
11065 Locs[i] = std::make_pair(MaskIdx, HiIdx);
11066 MaskPtr[HiIdx] = Idx;
11071 SDValue LoShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &LoMask[0]);
11072 SDValue HiShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &HiMask[0]);
11073 int MaskOps[] = { -1, -1, -1, -1 };
11074 for (unsigned i = 0; i != 4; ++i)
11075 if (Locs[i].first != -1)
11076 MaskOps[i] = Locs[i].first * 4 + Locs[i].second;
11077 return DAG.getVectorShuffle(VT, dl, LoShuffle, HiShuffle, &MaskOps[0]);
11080 static bool MayFoldVectorLoad(SDValue V) {
11081 while (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
11082 V = V.getOperand(0);
11084 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR)
11085 V = V.getOperand(0);
11086 if (V.hasOneUse() && V.getOpcode() == ISD::BUILD_VECTOR &&
11087 V.getNumOperands() == 2 && V.getOperand(1).getOpcode() == ISD::UNDEF)
11088 // BUILD_VECTOR (load), undef
11089 V = V.getOperand(0);
11091 return MayFoldLoad(V);
11095 SDValue getMOVDDup(SDValue &Op, SDLoc &dl, SDValue V1, SelectionDAG &DAG) {
11096 MVT VT = Op.getSimpleValueType();
11098 // Canonizalize to v2f64.
11099 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, V1);
11100 return DAG.getNode(ISD::BITCAST, dl, VT,
11101 getTargetShuffleNode(X86ISD::MOVDDUP, dl, MVT::v2f64,
11106 SDValue getMOVLowToHigh(SDValue &Op, SDLoc &dl, SelectionDAG &DAG,
11108 SDValue V1 = Op.getOperand(0);
11109 SDValue V2 = Op.getOperand(1);
11110 MVT VT = Op.getSimpleValueType();
11112 assert(VT != MVT::v2i64 && "unsupported shuffle type");
11114 if (HasSSE2 && VT == MVT::v2f64)
11115 return getTargetShuffleNode(X86ISD::MOVLHPD, dl, VT, V1, V2, DAG);
11117 // v4f32 or v4i32: canonizalized to v4f32 (which is legal for SSE1)
11118 return DAG.getNode(ISD::BITCAST, dl, VT,
11119 getTargetShuffleNode(X86ISD::MOVLHPS, dl, MVT::v4f32,
11120 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V1),
11121 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V2), DAG));
11125 SDValue getMOVHighToLow(SDValue &Op, SDLoc &dl, SelectionDAG &DAG) {
11126 SDValue V1 = Op.getOperand(0);
11127 SDValue V2 = Op.getOperand(1);
11128 MVT VT = Op.getSimpleValueType();
11130 assert((VT == MVT::v4i32 || VT == MVT::v4f32) &&
11131 "unsupported shuffle type");
11133 if (V2.getOpcode() == ISD::UNDEF)
11137 return getTargetShuffleNode(X86ISD::MOVHLPS, dl, VT, V1, V2, DAG);
11141 SDValue getMOVLP(SDValue &Op, SDLoc &dl, SelectionDAG &DAG, bool HasSSE2) {
11142 SDValue V1 = Op.getOperand(0);
11143 SDValue V2 = Op.getOperand(1);
11144 MVT VT = Op.getSimpleValueType();
11145 unsigned NumElems = VT.getVectorNumElements();
11147 // Use MOVLPS and MOVLPD in case V1 or V2 are loads. During isel, the second
11148 // operand of these instructions is only memory, so check if there's a
11149 // potencial load folding here, otherwise use SHUFPS or MOVSD to match the
11151 bool CanFoldLoad = false;
11153 // Trivial case, when V2 comes from a load.
11154 if (MayFoldVectorLoad(V2))
11155 CanFoldLoad = true;
11157 // When V1 is a load, it can be folded later into a store in isel, example:
11158 // (store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)), addr:$src1)
11160 // (MOVLPSmr addr:$src1, VR128:$src2)
11161 // So, recognize this potential and also use MOVLPS or MOVLPD
11162 else if (MayFoldVectorLoad(V1) && MayFoldIntoStore(Op))
11163 CanFoldLoad = true;
11165 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11167 if (HasSSE2 && NumElems == 2)
11168 return getTargetShuffleNode(X86ISD::MOVLPD, dl, VT, V1, V2, DAG);
11171 // If we don't care about the second element, proceed to use movss.
11172 if (SVOp->getMaskElt(1) != -1)
11173 return getTargetShuffleNode(X86ISD::MOVLPS, dl, VT, V1, V2, DAG);
11176 // movl and movlp will both match v2i64, but v2i64 is never matched by
11177 // movl earlier because we make it strict to avoid messing with the movlp load
11178 // folding logic (see the code above getMOVLP call). Match it here then,
11179 // this is horrible, but will stay like this until we move all shuffle
11180 // matching to x86 specific nodes. Note that for the 1st condition all
11181 // types are matched with movsd.
11183 // FIXME: isMOVLMask should be checked and matched before getMOVLP,
11184 // as to remove this logic from here, as much as possible
11185 if (NumElems == 2 || !isMOVLMask(SVOp->getMask(), VT))
11186 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
11187 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
11190 assert(VT != MVT::v4i32 && "unsupported shuffle type");
11192 // Invert the operand order and use SHUFPS to match it.
11193 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V2, V1,
11194 getShuffleSHUFImmediate(SVOp), DAG);
11197 static SDValue NarrowVectorLoadToElement(LoadSDNode *Load, unsigned Index,
11198 SelectionDAG &DAG) {
11200 MVT VT = Load->getSimpleValueType(0);
11201 MVT EVT = VT.getVectorElementType();
11202 SDValue Addr = Load->getOperand(1);
11203 SDValue NewAddr = DAG.getNode(
11204 ISD::ADD, dl, Addr.getSimpleValueType(), Addr,
11205 DAG.getConstant(Index * EVT.getStoreSize(), Addr.getSimpleValueType()));
11208 DAG.getLoad(EVT, dl, Load->getChain(), NewAddr,
11209 DAG.getMachineFunction().getMachineMemOperand(
11210 Load->getMemOperand(), 0, EVT.getStoreSize()));
11214 // It is only safe to call this function if isINSERTPSMask is true for
11215 // this shufflevector mask.
11216 static SDValue getINSERTPS(ShuffleVectorSDNode *SVOp, SDLoc &dl,
11217 SelectionDAG &DAG) {
11218 // Generate an insertps instruction when inserting an f32 from memory onto a
11219 // v4f32 or when copying a member from one v4f32 to another.
11220 // We also use it for transferring i32 from one register to another,
11221 // since it simply copies the same bits.
11222 // If we're transferring an i32 from memory to a specific element in a
11223 // register, we output a generic DAG that will match the PINSRD
11225 MVT VT = SVOp->getSimpleValueType(0);
11226 MVT EVT = VT.getVectorElementType();
11227 SDValue V1 = SVOp->getOperand(0);
11228 SDValue V2 = SVOp->getOperand(1);
11229 auto Mask = SVOp->getMask();
11230 assert((VT == MVT::v4f32 || VT == MVT::v4i32) &&
11231 "unsupported vector type for insertps/pinsrd");
11233 auto FromV1Predicate = [](const int &i) { return i < 4 && i > -1; };
11234 auto FromV2Predicate = [](const int &i) { return i >= 4; };
11235 int FromV1 = std::count_if(Mask.begin(), Mask.end(), FromV1Predicate);
11239 unsigned DestIndex;
11243 DestIndex = std::find_if(Mask.begin(), Mask.end(), FromV1Predicate) -
11246 // If we have 1 element from each vector, we have to check if we're
11247 // changing V1's element's place. If so, we're done. Otherwise, we
11248 // should assume we're changing V2's element's place and behave
11250 int FromV2 = std::count_if(Mask.begin(), Mask.end(), FromV2Predicate);
11251 assert(DestIndex <= INT32_MAX && "truncated destination index");
11252 if (FromV1 == FromV2 &&
11253 static_cast<int>(DestIndex) == Mask[DestIndex] % 4) {
11257 std::find_if(Mask.begin(), Mask.end(), FromV2Predicate) - Mask.begin();
11260 assert(std::count_if(Mask.begin(), Mask.end(), FromV2Predicate) == 1 &&
11261 "More than one element from V1 and from V2, or no elements from one "
11262 "of the vectors. This case should not have returned true from "
11267 std::find_if(Mask.begin(), Mask.end(), FromV2Predicate) - Mask.begin();
11270 // Get an index into the source vector in the range [0,4) (the mask is
11271 // in the range [0,8) because it can address V1 and V2)
11272 unsigned SrcIndex = Mask[DestIndex] % 4;
11273 if (MayFoldLoad(From)) {
11274 // Trivial case, when From comes from a load and is only used by the
11275 // shuffle. Make it use insertps from the vector that we need from that
11278 NarrowVectorLoadToElement(cast<LoadSDNode>(From), SrcIndex, DAG);
11279 if (!NewLoad.getNode())
11282 if (EVT == MVT::f32) {
11283 // Create this as a scalar to vector to match the instruction pattern.
11284 SDValue LoadScalarToVector =
11285 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, NewLoad);
11286 SDValue InsertpsMask = DAG.getIntPtrConstant(DestIndex << 4);
11287 return DAG.getNode(X86ISD::INSERTPS, dl, VT, To, LoadScalarToVector,
11289 } else { // EVT == MVT::i32
11290 // If we're getting an i32 from memory, use an INSERT_VECTOR_ELT
11291 // instruction, to match the PINSRD instruction, which loads an i32 to a
11292 // certain vector element.
11293 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, To, NewLoad,
11294 DAG.getConstant(DestIndex, MVT::i32));
11298 // Vector-element-to-vector
11299 SDValue InsertpsMask = DAG.getIntPtrConstant(DestIndex << 4 | SrcIndex << 6);
11300 return DAG.getNode(X86ISD::INSERTPS, dl, VT, To, From, InsertpsMask);
11303 // Reduce a vector shuffle to zext.
11304 static SDValue LowerVectorIntExtend(SDValue Op, const X86Subtarget *Subtarget,
11305 SelectionDAG &DAG) {
11306 // PMOVZX is only available from SSE41.
11307 if (!Subtarget->hasSSE41())
11310 MVT VT = Op.getSimpleValueType();
11312 // Only AVX2 support 256-bit vector integer extending.
11313 if (!Subtarget->hasInt256() && VT.is256BitVector())
11316 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11318 SDValue V1 = Op.getOperand(0);
11319 SDValue V2 = Op.getOperand(1);
11320 unsigned NumElems = VT.getVectorNumElements();
11322 // Extending is an unary operation and the element type of the source vector
11323 // won't be equal to or larger than i64.
11324 if (V2.getOpcode() != ISD::UNDEF || !VT.isInteger() ||
11325 VT.getVectorElementType() == MVT::i64)
11328 // Find the expansion ratio, e.g. expanding from i8 to i32 has a ratio of 4.
11329 unsigned Shift = 1; // Start from 2, i.e. 1 << 1.
11330 while ((1U << Shift) < NumElems) {
11331 if (SVOp->getMaskElt(1U << Shift) == 1)
11334 // The maximal ratio is 8, i.e. from i8 to i64.
11339 // Check the shuffle mask.
11340 unsigned Mask = (1U << Shift) - 1;
11341 for (unsigned i = 0; i != NumElems; ++i) {
11342 int EltIdx = SVOp->getMaskElt(i);
11343 if ((i & Mask) != 0 && EltIdx != -1)
11345 if ((i & Mask) == 0 && (unsigned)EltIdx != (i >> Shift))
11349 unsigned NBits = VT.getVectorElementType().getSizeInBits() << Shift;
11350 MVT NeVT = MVT::getIntegerVT(NBits);
11351 MVT NVT = MVT::getVectorVT(NeVT, NumElems >> Shift);
11353 if (!DAG.getTargetLoweringInfo().isTypeLegal(NVT))
11356 // Simplify the operand as it's prepared to be fed into shuffle.
11357 unsigned SignificantBits = NVT.getSizeInBits() >> Shift;
11358 if (V1.getOpcode() == ISD::BITCAST &&
11359 V1.getOperand(0).getOpcode() == ISD::SCALAR_TO_VECTOR &&
11360 V1.getOperand(0).getOperand(0).getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
11361 V1.getOperand(0).getOperand(0)
11362 .getSimpleValueType().getSizeInBits() == SignificantBits) {
11363 // (bitcast (sclr2vec (ext_vec_elt x))) -> (bitcast x)
11364 SDValue V = V1.getOperand(0).getOperand(0).getOperand(0);
11365 ConstantSDNode *CIdx =
11366 dyn_cast<ConstantSDNode>(V1.getOperand(0).getOperand(0).getOperand(1));
11367 // If it's foldable, i.e. normal load with single use, we will let code
11368 // selection to fold it. Otherwise, we will short the conversion sequence.
11369 if (CIdx && CIdx->getZExtValue() == 0 &&
11370 (!ISD::isNormalLoad(V.getNode()) || !V.hasOneUse())) {
11371 MVT FullVT = V.getSimpleValueType();
11372 MVT V1VT = V1.getSimpleValueType();
11373 if (FullVT.getSizeInBits() > V1VT.getSizeInBits()) {
11374 // The "ext_vec_elt" node is wider than the result node.
11375 // In this case we should extract subvector from V.
11376 // (bitcast (sclr2vec (ext_vec_elt x))) -> (bitcast (extract_subvector x)).
11377 unsigned Ratio = FullVT.getSizeInBits() / V1VT.getSizeInBits();
11378 MVT SubVecVT = MVT::getVectorVT(FullVT.getVectorElementType(),
11379 FullVT.getVectorNumElements()/Ratio);
11380 V = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVecVT, V,
11381 DAG.getIntPtrConstant(0));
11383 V1 = DAG.getNode(ISD::BITCAST, DL, V1VT, V);
11387 return DAG.getNode(ISD::BITCAST, DL, VT,
11388 DAG.getNode(X86ISD::VZEXT, DL, NVT, V1));
11391 static SDValue NormalizeVectorShuffle(SDValue Op, const X86Subtarget *Subtarget,
11392 SelectionDAG &DAG) {
11393 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11394 MVT VT = Op.getSimpleValueType();
11396 SDValue V1 = Op.getOperand(0);
11397 SDValue V2 = Op.getOperand(1);
11399 if (isZeroShuffle(SVOp))
11400 return getZeroVector(VT, Subtarget, DAG, dl);
11402 // Handle splat operations
11403 if (SVOp->isSplat()) {
11404 // Use vbroadcast whenever the splat comes from a foldable load
11405 SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG);
11406 if (Broadcast.getNode())
11410 // Check integer expanding shuffles.
11411 SDValue NewOp = LowerVectorIntExtend(Op, Subtarget, DAG);
11412 if (NewOp.getNode())
11415 // If the shuffle can be profitably rewritten as a narrower shuffle, then
11417 if (VT == MVT::v8i16 || VT == MVT::v16i8 || VT == MVT::v16i16 ||
11418 VT == MVT::v32i8) {
11419 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
11420 if (NewOp.getNode())
11421 return DAG.getNode(ISD::BITCAST, dl, VT, NewOp);
11422 } else if (VT.is128BitVector() && Subtarget->hasSSE2()) {
11423 // FIXME: Figure out a cleaner way to do this.
11424 if (ISD::isBuildVectorAllZeros(V2.getNode())) {
11425 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
11426 if (NewOp.getNode()) {
11427 MVT NewVT = NewOp.getSimpleValueType();
11428 if (isCommutedMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(),
11429 NewVT, true, false))
11430 return getVZextMovL(VT, NewVT, NewOp.getOperand(0), DAG, Subtarget,
11433 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) {
11434 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
11435 if (NewOp.getNode()) {
11436 MVT NewVT = NewOp.getSimpleValueType();
11437 if (isMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(), NewVT))
11438 return getVZextMovL(VT, NewVT, NewOp.getOperand(1), DAG, Subtarget,
11447 X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const {
11448 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11449 SDValue V1 = Op.getOperand(0);
11450 SDValue V2 = Op.getOperand(1);
11451 MVT VT = Op.getSimpleValueType();
11453 unsigned NumElems = VT.getVectorNumElements();
11454 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
11455 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
11456 bool V1IsSplat = false;
11457 bool V2IsSplat = false;
11458 bool HasSSE2 = Subtarget->hasSSE2();
11459 bool HasFp256 = Subtarget->hasFp256();
11460 bool HasInt256 = Subtarget->hasInt256();
11461 MachineFunction &MF = DAG.getMachineFunction();
11462 bool OptForSize = MF.getFunction()->getAttributes().
11463 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
11465 // Check if we should use the experimental vector shuffle lowering. If so,
11466 // delegate completely to that code path.
11467 if (ExperimentalVectorShuffleLowering)
11468 return lowerVectorShuffle(Op, Subtarget, DAG);
11470 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
11472 if (V1IsUndef && V2IsUndef)
11473 return DAG.getUNDEF(VT);
11475 // When we create a shuffle node we put the UNDEF node to second operand,
11476 // but in some cases the first operand may be transformed to UNDEF.
11477 // In this case we should just commute the node.
11479 return DAG.getCommutedVectorShuffle(*SVOp);
11481 // Vector shuffle lowering takes 3 steps:
11483 // 1) Normalize the input vectors. Here splats, zeroed vectors, profitable
11484 // narrowing and commutation of operands should be handled.
11485 // 2) Matching of shuffles with known shuffle masks to x86 target specific
11487 // 3) Rewriting of unmatched masks into new generic shuffle operations,
11488 // so the shuffle can be broken into other shuffles and the legalizer can
11489 // try the lowering again.
11491 // The general idea is that no vector_shuffle operation should be left to
11492 // be matched during isel, all of them must be converted to a target specific
11495 // Normalize the input vectors. Here splats, zeroed vectors, profitable
11496 // narrowing and commutation of operands should be handled. The actual code
11497 // doesn't include all of those, work in progress...
11498 SDValue NewOp = NormalizeVectorShuffle(Op, Subtarget, DAG);
11499 if (NewOp.getNode())
11502 SmallVector<int, 8> M(SVOp->getMask().begin(), SVOp->getMask().end());
11504 // NOTE: isPSHUFDMask can also match both masks below (unpckl_undef and
11505 // unpckh_undef). Only use pshufd if speed is more important than size.
11506 if (OptForSize && isUNPCKL_v_undef_Mask(M, VT, HasInt256))
11507 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
11508 if (OptForSize && isUNPCKH_v_undef_Mask(M, VT, HasInt256))
11509 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
11511 if (isMOVDDUPMask(M, VT) && Subtarget->hasSSE3() &&
11512 V2IsUndef && MayFoldVectorLoad(V1))
11513 return getMOVDDup(Op, dl, V1, DAG);
11515 if (isMOVHLPS_v_undef_Mask(M, VT))
11516 return getMOVHighToLow(Op, dl, DAG);
11518 // Use to match splats
11519 if (HasSSE2 && isUNPCKHMask(M, VT, HasInt256) && V2IsUndef &&
11520 (VT == MVT::v2f64 || VT == MVT::v2i64))
11521 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
11523 if (isPSHUFDMask(M, VT)) {
11524 // The actual implementation will match the mask in the if above and then
11525 // during isel it can match several different instructions, not only pshufd
11526 // as its name says, sad but true, emulate the behavior for now...
11527 if (isMOVDDUPMask(M, VT) && ((VT == MVT::v4f32 || VT == MVT::v2i64)))
11528 return getTargetShuffleNode(X86ISD::MOVLHPS, dl, VT, V1, V1, DAG);
11530 unsigned TargetMask = getShuffleSHUFImmediate(SVOp);
11532 if (HasSSE2 && (VT == MVT::v4f32 || VT == MVT::v4i32))
11533 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1, TargetMask, DAG);
11535 if (HasFp256 && (VT == MVT::v4f32 || VT == MVT::v2f64))
11536 return getTargetShuffleNode(X86ISD::VPERMILPI, dl, VT, V1, TargetMask,
11539 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V1,
11543 if (isPALIGNRMask(M, VT, Subtarget))
11544 return getTargetShuffleNode(X86ISD::PALIGNR, dl, VT, V1, V2,
11545 getShufflePALIGNRImmediate(SVOp),
11548 if (isVALIGNMask(M, VT, Subtarget))
11549 return getTargetShuffleNode(X86ISD::VALIGN, dl, VT, V1, V2,
11550 getShuffleVALIGNImmediate(SVOp),
11553 // Check if this can be converted into a logical shift.
11554 bool isLeft = false;
11555 unsigned ShAmt = 0;
11557 bool isShift = HasSSE2 && isVectorShift(SVOp, DAG, isLeft, ShVal, ShAmt);
11558 if (isShift && ShVal.hasOneUse()) {
11559 // If the shifted value has multiple uses, it may be cheaper to use
11560 // v_set0 + movlhps or movhlps, etc.
11561 MVT EltVT = VT.getVectorElementType();
11562 ShAmt *= EltVT.getSizeInBits();
11563 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
11566 if (isMOVLMask(M, VT)) {
11567 if (ISD::isBuildVectorAllZeros(V1.getNode()))
11568 return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl);
11569 if (!isMOVLPMask(M, VT)) {
11570 if (HasSSE2 && (VT == MVT::v2i64 || VT == MVT::v2f64))
11571 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
11573 if (VT == MVT::v4i32 || VT == MVT::v4f32)
11574 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
11578 // FIXME: fold these into legal mask.
11579 if (isMOVLHPSMask(M, VT) && !isUNPCKLMask(M, VT, HasInt256))
11580 return getMOVLowToHigh(Op, dl, DAG, HasSSE2);
11582 if (isMOVHLPSMask(M, VT))
11583 return getMOVHighToLow(Op, dl, DAG);
11585 if (V2IsUndef && isMOVSHDUPMask(M, VT, Subtarget))
11586 return getTargetShuffleNode(X86ISD::MOVSHDUP, dl, VT, V1, DAG);
11588 if (V2IsUndef && isMOVSLDUPMask(M, VT, Subtarget))
11589 return getTargetShuffleNode(X86ISD::MOVSLDUP, dl, VT, V1, DAG);
11591 if (isMOVLPMask(M, VT))
11592 return getMOVLP(Op, dl, DAG, HasSSE2);
11594 if (ShouldXformToMOVHLPS(M, VT) ||
11595 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), M, VT))
11596 return DAG.getCommutedVectorShuffle(*SVOp);
11599 // No better options. Use a vshldq / vsrldq.
11600 MVT EltVT = VT.getVectorElementType();
11601 ShAmt *= EltVT.getSizeInBits();
11602 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
11605 bool Commuted = false;
11606 // FIXME: This should also accept a bitcast of a splat? Be careful, not
11607 // 1,1,1,1 -> v8i16 though.
11608 BitVector UndefElements;
11609 if (auto *BVOp = dyn_cast<BuildVectorSDNode>(V1.getNode()))
11610 if (BVOp->getConstantSplatNode(&UndefElements) && UndefElements.none())
11612 if (auto *BVOp = dyn_cast<BuildVectorSDNode>(V2.getNode()))
11613 if (BVOp->getConstantSplatNode(&UndefElements) && UndefElements.none())
11616 // Canonicalize the splat or undef, if present, to be on the RHS.
11617 if (!V2IsUndef && V1IsSplat && !V2IsSplat) {
11618 CommuteVectorShuffleMask(M, NumElems);
11620 std::swap(V1IsSplat, V2IsSplat);
11624 if (isCommutedMOVLMask(M, VT, V2IsSplat, V2IsUndef)) {
11625 // Shuffling low element of v1 into undef, just return v1.
11628 // If V2 is a splat, the mask may be malformed such as <4,3,3,3>, which
11629 // the instruction selector will not match, so get a canonical MOVL with
11630 // swapped operands to undo the commute.
11631 return getMOVL(DAG, dl, VT, V2, V1);
11634 if (isUNPCKLMask(M, VT, HasInt256))
11635 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
11637 if (isUNPCKHMask(M, VT, HasInt256))
11638 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
11641 // Normalize mask so all entries that point to V2 points to its first
11642 // element then try to match unpck{h|l} again. If match, return a
11643 // new vector_shuffle with the corrected mask.p
11644 SmallVector<int, 8> NewMask(M.begin(), M.end());
11645 NormalizeMask(NewMask, NumElems);
11646 if (isUNPCKLMask(NewMask, VT, HasInt256, true))
11647 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
11648 if (isUNPCKHMask(NewMask, VT, HasInt256, true))
11649 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
11653 // Commute is back and try unpck* again.
11654 // FIXME: this seems wrong.
11655 CommuteVectorShuffleMask(M, NumElems);
11657 std::swap(V1IsSplat, V2IsSplat);
11659 if (isUNPCKLMask(M, VT, HasInt256))
11660 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
11662 if (isUNPCKHMask(M, VT, HasInt256))
11663 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
11666 // Normalize the node to match x86 shuffle ops if needed
11667 if (!V2IsUndef && (isSHUFPMask(M, VT, /* Commuted */ true)))
11668 return DAG.getCommutedVectorShuffle(*SVOp);
11670 // The checks below are all present in isShuffleMaskLegal, but they are
11671 // inlined here right now to enable us to directly emit target specific
11672 // nodes, and remove one by one until they don't return Op anymore.
11674 if (ShuffleVectorSDNode::isSplatMask(&M[0], VT) &&
11675 SVOp->getSplatIndex() == 0 && V2IsUndef) {
11676 if (VT == MVT::v2f64 || VT == MVT::v2i64)
11677 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
11680 if (isPSHUFHWMask(M, VT, HasInt256))
11681 return getTargetShuffleNode(X86ISD::PSHUFHW, dl, VT, V1,
11682 getShufflePSHUFHWImmediate(SVOp),
11685 if (isPSHUFLWMask(M, VT, HasInt256))
11686 return getTargetShuffleNode(X86ISD::PSHUFLW, dl, VT, V1,
11687 getShufflePSHUFLWImmediate(SVOp),
11690 unsigned MaskValue;
11691 if (isBlendMask(M, VT, Subtarget->hasSSE41(), Subtarget->hasInt256(),
11693 return LowerVECTOR_SHUFFLEtoBlend(SVOp, MaskValue, Subtarget, DAG);
11695 if (isSHUFPMask(M, VT))
11696 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V2,
11697 getShuffleSHUFImmediate(SVOp), DAG);
11699 if (isUNPCKL_v_undef_Mask(M, VT, HasInt256))
11700 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
11701 if (isUNPCKH_v_undef_Mask(M, VT, HasInt256))
11702 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
11704 //===--------------------------------------------------------------------===//
11705 // Generate target specific nodes for 128 or 256-bit shuffles only
11706 // supported in the AVX instruction set.
11709 // Handle VMOVDDUPY permutations
11710 if (V2IsUndef && isMOVDDUPYMask(M, VT, HasFp256))
11711 return getTargetShuffleNode(X86ISD::MOVDDUP, dl, VT, V1, DAG);
11713 // Handle VPERMILPS/D* permutations
11714 if (isVPERMILPMask(M, VT)) {
11715 if ((HasInt256 && VT == MVT::v8i32) || VT == MVT::v16i32)
11716 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1,
11717 getShuffleSHUFImmediate(SVOp), DAG);
11718 return getTargetShuffleNode(X86ISD::VPERMILPI, dl, VT, V1,
11719 getShuffleSHUFImmediate(SVOp), DAG);
11723 if (VT.is512BitVector() && isINSERT64x4Mask(M, VT, &Idx))
11724 return Insert256BitVector(V1, Extract256BitVector(V2, 0, DAG, dl),
11725 Idx*(NumElems/2), DAG, dl);
11727 // Handle VPERM2F128/VPERM2I128 permutations
11728 if (isVPERM2X128Mask(M, VT, HasFp256))
11729 return getTargetShuffleNode(X86ISD::VPERM2X128, dl, VT, V1,
11730 V2, getShuffleVPERM2X128Immediate(SVOp), DAG);
11732 if (Subtarget->hasSSE41() && isINSERTPSMask(M, VT))
11733 return getINSERTPS(SVOp, dl, DAG);
11736 if (V2IsUndef && HasInt256 && isPermImmMask(M, VT, Imm8))
11737 return getTargetShuffleNode(X86ISD::VPERMI, dl, VT, V1, Imm8, DAG);
11739 if ((V2IsUndef && HasInt256 && VT.is256BitVector() && NumElems == 8) ||
11740 VT.is512BitVector()) {
11741 MVT MaskEltVT = MVT::getIntegerVT(VT.getVectorElementType().getSizeInBits());
11742 MVT MaskVectorVT = MVT::getVectorVT(MaskEltVT, NumElems);
11743 SmallVector<SDValue, 16> permclMask;
11744 for (unsigned i = 0; i != NumElems; ++i) {
11745 permclMask.push_back(DAG.getConstant((M[i]>=0) ? M[i] : 0, MaskEltVT));
11748 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVectorVT, permclMask);
11750 // Bitcast is for VPERMPS since mask is v8i32 but node takes v8f32
11751 return DAG.getNode(X86ISD::VPERMV, dl, VT,
11752 DAG.getNode(ISD::BITCAST, dl, VT, Mask), V1);
11753 return DAG.getNode(X86ISD::VPERMV3, dl, VT, V1,
11754 DAG.getNode(ISD::BITCAST, dl, VT, Mask), V2);
11757 //===--------------------------------------------------------------------===//
11758 // Since no target specific shuffle was selected for this generic one,
11759 // lower it into other known shuffles. FIXME: this isn't true yet, but
11760 // this is the plan.
11763 // Handle v8i16 specifically since SSE can do byte extraction and insertion.
11764 if (VT == MVT::v8i16) {
11765 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(Op, Subtarget, DAG);
11766 if (NewOp.getNode())
11770 if (VT == MVT::v16i16 && Subtarget->hasInt256()) {
11771 SDValue NewOp = LowerVECTOR_SHUFFLEv16i16(Op, DAG);
11772 if (NewOp.getNode())
11776 if (VT == MVT::v16i8) {
11777 SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(SVOp, Subtarget, DAG);
11778 if (NewOp.getNode())
11782 if (VT == MVT::v32i8) {
11783 SDValue NewOp = LowerVECTOR_SHUFFLEv32i8(SVOp, Subtarget, DAG);
11784 if (NewOp.getNode())
11788 // Handle all 128-bit wide vectors with 4 elements, and match them with
11789 // several different shuffle types.
11790 if (NumElems == 4 && VT.is128BitVector())
11791 return LowerVECTOR_SHUFFLE_128v4(SVOp, DAG);
11793 // Handle general 256-bit shuffles
11794 if (VT.is256BitVector())
11795 return LowerVECTOR_SHUFFLE_256(SVOp, DAG);
11800 // This function assumes its argument is a BUILD_VECTOR of constants or
11801 // undef SDNodes. i.e: ISD::isBuildVectorOfConstantSDNodes(BuildVector) is
11803 static bool BUILD_VECTORtoBlendMask(BuildVectorSDNode *BuildVector,
11804 unsigned &MaskValue) {
11806 unsigned NumElems = BuildVector->getNumOperands();
11807 // There are 2 lanes if (NumElems > 8), and 1 lane otherwise.
11808 unsigned NumLanes = (NumElems - 1) / 8 + 1;
11809 unsigned NumElemsInLane = NumElems / NumLanes;
11811 // Blend for v16i16 should be symetric for the both lanes.
11812 for (unsigned i = 0; i < NumElemsInLane; ++i) {
11813 SDValue EltCond = BuildVector->getOperand(i);
11814 SDValue SndLaneEltCond =
11815 (NumLanes == 2) ? BuildVector->getOperand(i + NumElemsInLane) : EltCond;
11817 int Lane1Cond = -1, Lane2Cond = -1;
11818 if (isa<ConstantSDNode>(EltCond))
11819 Lane1Cond = !isZero(EltCond);
11820 if (isa<ConstantSDNode>(SndLaneEltCond))
11821 Lane2Cond = !isZero(SndLaneEltCond);
11823 if (Lane1Cond == Lane2Cond || Lane2Cond < 0)
11824 // Lane1Cond != 0, means we want the first argument.
11825 // Lane1Cond == 0, means we want the second argument.
11826 // The encoding of this argument is 0 for the first argument, 1
11827 // for the second. Therefore, invert the condition.
11828 MaskValue |= !Lane1Cond << i;
11829 else if (Lane1Cond < 0)
11830 MaskValue |= !Lane2Cond << i;
11837 /// \brief Try to lower a VSELECT instruction to an immediate-controlled blend
11839 static SDValue lowerVSELECTtoBLENDI(SDValue Op, const X86Subtarget *Subtarget,
11840 SelectionDAG &DAG) {
11841 SDValue Cond = Op.getOperand(0);
11842 SDValue LHS = Op.getOperand(1);
11843 SDValue RHS = Op.getOperand(2);
11845 MVT VT = Op.getSimpleValueType();
11846 MVT EltVT = VT.getVectorElementType();
11848 // There is no blend with immediate in AVX-512.
11849 if (VT.is512BitVector())
11852 // No blend instruction before SSE4.1.
11853 if (!Subtarget->hasSSE41())
11855 // There is no byte-blend immediate controlled instruction.
11856 if (EltVT == MVT::i8)
11859 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
11862 auto *CondBV = cast<BuildVectorSDNode>(Cond);
11864 unsigned BlendMask = 0;
11866 if (VT == MVT::v16i16) {
11867 // v16i16 blends are completely special. We can only do them when we have
11868 // a repeated blend across the two 128-bit halves and we have AVX2.
11869 if (!Subtarget->hasAVX2())
11872 for (int i = 0; i < 8; ++i) {
11873 SDValue Lo = CondBV->getOperand(i);
11874 SDValue Hi = CondBV->getOperand(i + 8);
11875 bool IsLoZero = X86::isZeroNode(Lo);
11876 bool IsHiZero = X86::isZeroNode(Hi);
11877 if (Lo->getOpcode() != ISD::UNDEF && Hi->getOpcode() != ISD::UNDEF &&
11878 IsLoZero != IsHiZero)
11879 // Asymmetric blends, bail.
11881 BlendMask |= (unsigned)(IsLoZero || IsHiZero) << i;
11884 // Everything else uses a generic blend mask computation with a custom type.
11885 if (VT.isInteger()) {
11886 if (VT.is256BitVector()) {
11887 // The 256-bit integer blend instructions are only available on AVX2.
11888 if (!Subtarget->hasAVX2())
11891 // We do the blend on v8i32 for 256-bit integer types.
11892 BlendVT = MVT::v8i32;
11894 // For 128-bit vectors we do the blend on v8i16 types.
11895 BlendVT = MVT::v8i16;
11898 assert(BlendVT.getVectorNumElements() <= 8 &&
11899 "Cannot blend more than 8 elements with an immediate!");
11900 // Scale the blend mask based on the number of elements in the selected
11902 int Scale = BlendVT.getVectorNumElements() / VT.getVectorNumElements();
11903 for (int i = 0, e = CondBV->getNumOperands(); i < e; ++i) {
11904 SDValue CondElement = CondBV->getOperand(i);
11905 if (CondElement->getOpcode() != ISD::UNDEF &&
11906 X86::isZeroNode(CondElement))
11907 for (int j = 0; j < Scale; ++j)
11908 BlendMask |= 1u << (i * Scale + j);
11912 LHS = DAG.getNode(ISD::BITCAST, DL, BlendVT, LHS);
11913 RHS = DAG.getNode(ISD::BITCAST, DL, BlendVT, RHS);
11915 return DAG.getNode(ISD::BITCAST, DL, VT,
11916 DAG.getNode(X86ISD::BLENDI, DL, BlendVT, LHS, RHS,
11917 DAG.getConstant(BlendMask, MVT::i8)));
11920 SDValue X86TargetLowering::LowerVSELECT(SDValue Op, SelectionDAG &DAG) const {
11921 // A vselect where all conditions and data are constants can be optimized into
11922 // a single vector load by SelectionDAGLegalize::ExpandBUILD_VECTOR().
11923 if (ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(0).getNode()) &&
11924 ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(1).getNode()) &&
11925 ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(2).getNode()))
11928 SDValue BlendOp = lowerVSELECTtoBLENDI(Op, Subtarget, DAG);
11929 if (BlendOp.getNode())
11932 // Some types for vselect were previously set to Expand, not Legal or
11933 // Custom. Return an empty SDValue so we fall-through to Expand, after
11934 // the Custom lowering phase.
11935 MVT VT = Op.getSimpleValueType();
11936 switch (VT.SimpleTy) {
11941 if (Subtarget->hasBWI() && Subtarget->hasVLX())
11946 // We couldn't create a "Blend with immediate" node.
11947 // This node should still be legal, but we'll have to emit a blendv*
11952 static SDValue LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) {
11953 MVT VT = Op.getSimpleValueType();
11956 if (!Op.getOperand(0).getSimpleValueType().is128BitVector())
11959 if (VT.getSizeInBits() == 8) {
11960 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
11961 Op.getOperand(0), Op.getOperand(1));
11962 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
11963 DAG.getValueType(VT));
11964 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
11967 if (VT.getSizeInBits() == 16) {
11968 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
11969 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
11971 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
11972 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
11973 DAG.getNode(ISD::BITCAST, dl,
11976 Op.getOperand(1)));
11977 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
11978 Op.getOperand(0), Op.getOperand(1));
11979 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
11980 DAG.getValueType(VT));
11981 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
11984 if (VT == MVT::f32) {
11985 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
11986 // the result back to FR32 register. It's only worth matching if the
11987 // result has a single use which is a store or a bitcast to i32. And in
11988 // the case of a store, it's not worth it if the index is a constant 0,
11989 // because a MOVSSmr can be used instead, which is smaller and faster.
11990 if (!Op.hasOneUse())
11992 SDNode *User = *Op.getNode()->use_begin();
11993 if ((User->getOpcode() != ISD::STORE ||
11994 (isa<ConstantSDNode>(Op.getOperand(1)) &&
11995 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
11996 (User->getOpcode() != ISD::BITCAST ||
11997 User->getValueType(0) != MVT::i32))
11999 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
12000 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32,
12003 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, Extract);
12006 if (VT == MVT::i32 || VT == MVT::i64) {
12007 // ExtractPS/pextrq works with constant index.
12008 if (isa<ConstantSDNode>(Op.getOperand(1)))
12014 /// Extract one bit from mask vector, like v16i1 or v8i1.
12015 /// AVX-512 feature.
12017 X86TargetLowering::ExtractBitFromMaskVector(SDValue Op, SelectionDAG &DAG) const {
12018 SDValue Vec = Op.getOperand(0);
12020 MVT VecVT = Vec.getSimpleValueType();
12021 SDValue Idx = Op.getOperand(1);
12022 MVT EltVT = Op.getSimpleValueType();
12024 assert((EltVT == MVT::i1) && "Unexpected operands in ExtractBitFromMaskVector");
12026 // variable index can't be handled in mask registers,
12027 // extend vector to VR512
12028 if (!isa<ConstantSDNode>(Idx)) {
12029 MVT ExtVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
12030 SDValue Ext = DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVT, Vec);
12031 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
12032 ExtVT.getVectorElementType(), Ext, Idx);
12033 return DAG.getNode(ISD::TRUNCATE, dl, EltVT, Elt);
12036 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
12037 const TargetRegisterClass* rc = getRegClassFor(VecVT);
12038 unsigned MaxSift = rc->getSize()*8 - 1;
12039 Vec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, Vec,
12040 DAG.getConstant(MaxSift - IdxVal, MVT::i8));
12041 Vec = DAG.getNode(X86ISD::VSRLI, dl, VecVT, Vec,
12042 DAG.getConstant(MaxSift, MVT::i8));
12043 return DAG.getNode(X86ISD::VEXTRACT, dl, MVT::i1, Vec,
12044 DAG.getIntPtrConstant(0));
12048 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
12049 SelectionDAG &DAG) const {
12051 SDValue Vec = Op.getOperand(0);
12052 MVT VecVT = Vec.getSimpleValueType();
12053 SDValue Idx = Op.getOperand(1);
12055 if (Op.getSimpleValueType() == MVT::i1)
12056 return ExtractBitFromMaskVector(Op, DAG);
12058 if (!isa<ConstantSDNode>(Idx)) {
12059 if (VecVT.is512BitVector() ||
12060 (VecVT.is256BitVector() && Subtarget->hasInt256() &&
12061 VecVT.getVectorElementType().getSizeInBits() == 32)) {
12064 MVT::getIntegerVT(VecVT.getVectorElementType().getSizeInBits());
12065 MVT MaskVT = MVT::getVectorVT(MaskEltVT, VecVT.getSizeInBits() /
12066 MaskEltVT.getSizeInBits());
12068 Idx = DAG.getZExtOrTrunc(Idx, dl, MaskEltVT);
12069 SDValue Mask = DAG.getNode(X86ISD::VINSERT, dl, MaskVT,
12070 getZeroVector(MaskVT, Subtarget, DAG, dl),
12071 Idx, DAG.getConstant(0, getPointerTy()));
12072 SDValue Perm = DAG.getNode(X86ISD::VPERMV, dl, VecVT, Mask, Vec);
12073 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(),
12074 Perm, DAG.getConstant(0, getPointerTy()));
12079 // If this is a 256-bit vector result, first extract the 128-bit vector and
12080 // then extract the element from the 128-bit vector.
12081 if (VecVT.is256BitVector() || VecVT.is512BitVector()) {
12083 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
12084 // Get the 128-bit vector.
12085 Vec = Extract128BitVector(Vec, IdxVal, DAG, dl);
12086 MVT EltVT = VecVT.getVectorElementType();
12088 unsigned ElemsPerChunk = 128 / EltVT.getSizeInBits();
12090 //if (IdxVal >= NumElems/2)
12091 // IdxVal -= NumElems/2;
12092 IdxVal -= (IdxVal/ElemsPerChunk)*ElemsPerChunk;
12093 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec,
12094 DAG.getConstant(IdxVal, MVT::i32));
12097 assert(VecVT.is128BitVector() && "Unexpected vector length");
12099 if (Subtarget->hasSSE41()) {
12100 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG);
12105 MVT VT = Op.getSimpleValueType();
12106 // TODO: handle v16i8.
12107 if (VT.getSizeInBits() == 16) {
12108 SDValue Vec = Op.getOperand(0);
12109 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
12111 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
12112 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
12113 DAG.getNode(ISD::BITCAST, dl,
12115 Op.getOperand(1)));
12116 // Transform it so it match pextrw which produces a 32-bit result.
12117 MVT EltVT = MVT::i32;
12118 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
12119 Op.getOperand(0), Op.getOperand(1));
12120 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
12121 DAG.getValueType(VT));
12122 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
12125 if (VT.getSizeInBits() == 32) {
12126 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
12130 // SHUFPS the element to the lowest double word, then movss.
12131 int Mask[4] = { static_cast<int>(Idx), -1, -1, -1 };
12132 MVT VVT = Op.getOperand(0).getSimpleValueType();
12133 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
12134 DAG.getUNDEF(VVT), Mask);
12135 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
12136 DAG.getIntPtrConstant(0));
12139 if (VT.getSizeInBits() == 64) {
12140 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
12141 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
12142 // to match extract_elt for f64.
12143 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
12147 // UNPCKHPD the element to the lowest double word, then movsd.
12148 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
12149 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
12150 int Mask[2] = { 1, -1 };
12151 MVT VVT = Op.getOperand(0).getSimpleValueType();
12152 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
12153 DAG.getUNDEF(VVT), Mask);
12154 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
12155 DAG.getIntPtrConstant(0));
12161 /// Insert one bit to mask vector, like v16i1 or v8i1.
12162 /// AVX-512 feature.
12164 X86TargetLowering::InsertBitToMaskVector(SDValue Op, SelectionDAG &DAG) const {
12166 SDValue Vec = Op.getOperand(0);
12167 SDValue Elt = Op.getOperand(1);
12168 SDValue Idx = Op.getOperand(2);
12169 MVT VecVT = Vec.getSimpleValueType();
12171 if (!isa<ConstantSDNode>(Idx)) {
12172 // Non constant index. Extend source and destination,
12173 // insert element and then truncate the result.
12174 MVT ExtVecVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
12175 MVT ExtEltVT = (VecVT == MVT::v8i1 ? MVT::i64 : MVT::i32);
12176 SDValue ExtOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ExtVecVT,
12177 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVecVT, Vec),
12178 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtEltVT, Elt), Idx);
12179 return DAG.getNode(ISD::TRUNCATE, dl, VecVT, ExtOp);
12182 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
12183 SDValue EltInVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Elt);
12184 if (Vec.getOpcode() == ISD::UNDEF)
12185 return DAG.getNode(X86ISD::VSHLI, dl, VecVT, EltInVec,
12186 DAG.getConstant(IdxVal, MVT::i8));
12187 const TargetRegisterClass* rc = getRegClassFor(VecVT);
12188 unsigned MaxSift = rc->getSize()*8 - 1;
12189 EltInVec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, EltInVec,
12190 DAG.getConstant(MaxSift, MVT::i8));
12191 EltInVec = DAG.getNode(X86ISD::VSRLI, dl, VecVT, EltInVec,
12192 DAG.getConstant(MaxSift - IdxVal, MVT::i8));
12193 return DAG.getNode(ISD::OR, dl, VecVT, Vec, EltInVec);
12196 SDValue X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op,
12197 SelectionDAG &DAG) const {
12198 MVT VT = Op.getSimpleValueType();
12199 MVT EltVT = VT.getVectorElementType();
12201 if (EltVT == MVT::i1)
12202 return InsertBitToMaskVector(Op, DAG);
12205 SDValue N0 = Op.getOperand(0);
12206 SDValue N1 = Op.getOperand(1);
12207 SDValue N2 = Op.getOperand(2);
12208 if (!isa<ConstantSDNode>(N2))
12210 auto *N2C = cast<ConstantSDNode>(N2);
12211 unsigned IdxVal = N2C->getZExtValue();
12213 // If the vector is wider than 128 bits, extract the 128-bit subvector, insert
12214 // into that, and then insert the subvector back into the result.
12215 if (VT.is256BitVector() || VT.is512BitVector()) {
12216 // Get the desired 128-bit vector half.
12217 SDValue V = Extract128BitVector(N0, IdxVal, DAG, dl);
12219 // Insert the element into the desired half.
12220 unsigned NumEltsIn128 = 128 / EltVT.getSizeInBits();
12221 unsigned IdxIn128 = IdxVal - (IdxVal / NumEltsIn128) * NumEltsIn128;
12223 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V, N1,
12224 DAG.getConstant(IdxIn128, MVT::i32));
12226 // Insert the changed part back to the 256-bit vector
12227 return Insert128BitVector(N0, V, IdxVal, DAG, dl);
12229 assert(VT.is128BitVector() && "Only 128-bit vector types should be left!");
12231 if (Subtarget->hasSSE41()) {
12232 if (EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) {
12234 if (VT == MVT::v8i16) {
12235 Opc = X86ISD::PINSRW;
12237 assert(VT == MVT::v16i8);
12238 Opc = X86ISD::PINSRB;
12241 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
12243 if (N1.getValueType() != MVT::i32)
12244 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
12245 if (N2.getValueType() != MVT::i32)
12246 N2 = DAG.getIntPtrConstant(IdxVal);
12247 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
12250 if (EltVT == MVT::f32) {
12251 // Bits [7:6] of the constant are the source select. This will always be
12252 // zero here. The DAG Combiner may combine an extract_elt index into
12254 // bits. For example (insert (extract, 3), 2) could be matched by
12256 // the '3' into bits [7:6] of X86ISD::INSERTPS.
12257 // Bits [5:4] of the constant are the destination select. This is the
12258 // value of the incoming immediate.
12259 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
12260 // combine either bitwise AND or insert of float 0.0 to set these bits.
12261 N2 = DAG.getIntPtrConstant(IdxVal << 4);
12262 // Create this as a scalar to vector..
12263 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
12264 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
12267 if (EltVT == MVT::i32 || EltVT == MVT::i64) {
12268 // PINSR* works with constant index.
12273 if (EltVT == MVT::i8)
12276 if (EltVT.getSizeInBits() == 16) {
12277 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
12278 // as its second argument.
12279 if (N1.getValueType() != MVT::i32)
12280 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
12281 if (N2.getValueType() != MVT::i32)
12282 N2 = DAG.getIntPtrConstant(IdxVal);
12283 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);
12288 static SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) {
12290 MVT OpVT = Op.getSimpleValueType();
12292 // If this is a 256-bit vector result, first insert into a 128-bit
12293 // vector and then insert into the 256-bit vector.
12294 if (!OpVT.is128BitVector()) {
12295 // Insert into a 128-bit vector.
12296 unsigned SizeFactor = OpVT.getSizeInBits()/128;
12297 MVT VT128 = MVT::getVectorVT(OpVT.getVectorElementType(),
12298 OpVT.getVectorNumElements() / SizeFactor);
12300 Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Op.getOperand(0));
12302 // Insert the 128-bit vector.
12303 return Insert128BitVector(DAG.getUNDEF(OpVT), Op, 0, DAG, dl);
12306 if (OpVT == MVT::v1i64 &&
12307 Op.getOperand(0).getValueType() == MVT::i64)
12308 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
12310 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
12311 assert(OpVT.is128BitVector() && "Expected an SSE type!");
12312 return DAG.getNode(ISD::BITCAST, dl, OpVT,
12313 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,AnyExt));
12316 // Lower a node with an EXTRACT_SUBVECTOR opcode. This may result in
12317 // a simple subregister reference or explicit instructions to grab
12318 // upper bits of a vector.
12319 static SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
12320 SelectionDAG &DAG) {
12322 SDValue In = Op.getOperand(0);
12323 SDValue Idx = Op.getOperand(1);
12324 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
12325 MVT ResVT = Op.getSimpleValueType();
12326 MVT InVT = In.getSimpleValueType();
12328 if (Subtarget->hasFp256()) {
12329 if (ResVT.is128BitVector() &&
12330 (InVT.is256BitVector() || InVT.is512BitVector()) &&
12331 isa<ConstantSDNode>(Idx)) {
12332 return Extract128BitVector(In, IdxVal, DAG, dl);
12334 if (ResVT.is256BitVector() && InVT.is512BitVector() &&
12335 isa<ConstantSDNode>(Idx)) {
12336 return Extract256BitVector(In, IdxVal, DAG, dl);
12342 // Lower a node with an INSERT_SUBVECTOR opcode. This may result in a
12343 // simple superregister reference or explicit instructions to insert
12344 // the upper bits of a vector.
12345 static SDValue LowerINSERT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
12346 SelectionDAG &DAG) {
12347 if (Subtarget->hasFp256()) {
12348 SDLoc dl(Op.getNode());
12349 SDValue Vec = Op.getNode()->getOperand(0);
12350 SDValue SubVec = Op.getNode()->getOperand(1);
12351 SDValue Idx = Op.getNode()->getOperand(2);
12353 if ((Op.getNode()->getSimpleValueType(0).is256BitVector() ||
12354 Op.getNode()->getSimpleValueType(0).is512BitVector()) &&
12355 SubVec.getNode()->getSimpleValueType(0).is128BitVector() &&
12356 isa<ConstantSDNode>(Idx)) {
12357 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
12358 return Insert128BitVector(Vec, SubVec, IdxVal, DAG, dl);
12361 if (Op.getNode()->getSimpleValueType(0).is512BitVector() &&
12362 SubVec.getNode()->getSimpleValueType(0).is256BitVector() &&
12363 isa<ConstantSDNode>(Idx)) {
12364 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
12365 return Insert256BitVector(Vec, SubVec, IdxVal, DAG, dl);
12371 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
12372 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
12373 // one of the above mentioned nodes. It has to be wrapped because otherwise
12374 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
12375 // be used to form addressing mode. These wrapped nodes will be selected
12378 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
12379 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
12381 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
12382 // global base reg.
12383 unsigned char OpFlag = 0;
12384 unsigned WrapperKind = X86ISD::Wrapper;
12385 CodeModel::Model M = DAG.getTarget().getCodeModel();
12387 if (Subtarget->isPICStyleRIPRel() &&
12388 (M == CodeModel::Small || M == CodeModel::Kernel))
12389 WrapperKind = X86ISD::WrapperRIP;
12390 else if (Subtarget->isPICStyleGOT())
12391 OpFlag = X86II::MO_GOTOFF;
12392 else if (Subtarget->isPICStyleStubPIC())
12393 OpFlag = X86II::MO_PIC_BASE_OFFSET;
12395 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(),
12396 CP->getAlignment(),
12397 CP->getOffset(), OpFlag);
12399 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
12400 // With PIC, the address is actually $g + Offset.
12402 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
12403 DAG.getNode(X86ISD::GlobalBaseReg,
12404 SDLoc(), getPointerTy()),
12411 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
12412 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
12414 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
12415 // global base reg.
12416 unsigned char OpFlag = 0;
12417 unsigned WrapperKind = X86ISD::Wrapper;
12418 CodeModel::Model M = DAG.getTarget().getCodeModel();
12420 if (Subtarget->isPICStyleRIPRel() &&
12421 (M == CodeModel::Small || M == CodeModel::Kernel))
12422 WrapperKind = X86ISD::WrapperRIP;
12423 else if (Subtarget->isPICStyleGOT())
12424 OpFlag = X86II::MO_GOTOFF;
12425 else if (Subtarget->isPICStyleStubPIC())
12426 OpFlag = X86II::MO_PIC_BASE_OFFSET;
12428 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(),
12431 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
12433 // With PIC, the address is actually $g + Offset.
12435 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
12436 DAG.getNode(X86ISD::GlobalBaseReg,
12437 SDLoc(), getPointerTy()),
12444 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const {
12445 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
12447 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
12448 // global base reg.
12449 unsigned char OpFlag = 0;
12450 unsigned WrapperKind = X86ISD::Wrapper;
12451 CodeModel::Model M = DAG.getTarget().getCodeModel();
12453 if (Subtarget->isPICStyleRIPRel() &&
12454 (M == CodeModel::Small || M == CodeModel::Kernel)) {
12455 if (Subtarget->isTargetDarwin() || Subtarget->isTargetELF())
12456 OpFlag = X86II::MO_GOTPCREL;
12457 WrapperKind = X86ISD::WrapperRIP;
12458 } else if (Subtarget->isPICStyleGOT()) {
12459 OpFlag = X86II::MO_GOT;
12460 } else if (Subtarget->isPICStyleStubPIC()) {
12461 OpFlag = X86II::MO_DARWIN_NONLAZY_PIC_BASE;
12462 } else if (Subtarget->isPICStyleStubNoDynamic()) {
12463 OpFlag = X86II::MO_DARWIN_NONLAZY;
12466 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag);
12469 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
12471 // With PIC, the address is actually $g + Offset.
12472 if (DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
12473 !Subtarget->is64Bit()) {
12474 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
12475 DAG.getNode(X86ISD::GlobalBaseReg,
12476 SDLoc(), getPointerTy()),
12480 // For symbols that require a load from a stub to get the address, emit the
12482 if (isGlobalStubReference(OpFlag))
12483 Result = DAG.getLoad(getPointerTy(), DL, DAG.getEntryNode(), Result,
12484 MachinePointerInfo::getGOT(), false, false, false, 0);
12490 X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
12491 // Create the TargetBlockAddressAddress node.
12492 unsigned char OpFlags =
12493 Subtarget->ClassifyBlockAddressReference();
12494 CodeModel::Model M = DAG.getTarget().getCodeModel();
12495 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
12496 int64_t Offset = cast<BlockAddressSDNode>(Op)->getOffset();
12498 SDValue Result = DAG.getTargetBlockAddress(BA, getPointerTy(), Offset,
12501 if (Subtarget->isPICStyleRIPRel() &&
12502 (M == CodeModel::Small || M == CodeModel::Kernel))
12503 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
12505 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
12507 // With PIC, the address is actually $g + Offset.
12508 if (isGlobalRelativeToPICBase(OpFlags)) {
12509 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
12510 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
12518 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, SDLoc dl,
12519 int64_t Offset, SelectionDAG &DAG) const {
12520 // Create the TargetGlobalAddress node, folding in the constant
12521 // offset if it is legal.
12522 unsigned char OpFlags =
12523 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget());
12524 CodeModel::Model M = DAG.getTarget().getCodeModel();
12526 if (OpFlags == X86II::MO_NO_FLAG &&
12527 X86::isOffsetSuitableForCodeModel(Offset, M)) {
12528 // A direct static reference to a global.
12529 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), Offset);
12532 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags);
12535 if (Subtarget->isPICStyleRIPRel() &&
12536 (M == CodeModel::Small || M == CodeModel::Kernel))
12537 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
12539 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
12541 // With PIC, the address is actually $g + Offset.
12542 if (isGlobalRelativeToPICBase(OpFlags)) {
12543 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
12544 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
12548 // For globals that require a load from a stub to get the address, emit the
12550 if (isGlobalStubReference(OpFlags))
12551 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result,
12552 MachinePointerInfo::getGOT(), false, false, false, 0);
12554 // If there was a non-zero offset that we didn't fold, create an explicit
12555 // addition for it.
12557 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result,
12558 DAG.getConstant(Offset, getPointerTy()));
12564 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
12565 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
12566 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
12567 return LowerGlobalAddress(GV, SDLoc(Op), Offset, DAG);
12571 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
12572 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg,
12573 unsigned char OperandFlags, bool LocalDynamic = false) {
12574 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
12575 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
12577 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
12578 GA->getValueType(0),
12582 X86ISD::NodeType CallType = LocalDynamic ? X86ISD::TLSBASEADDR
12586 SDValue Ops[] = { Chain, TGA, *InFlag };
12587 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
12589 SDValue Ops[] = { Chain, TGA };
12590 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
12593 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
12594 MFI->setAdjustsStack(true);
12596 SDValue Flag = Chain.getValue(1);
12597 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
12600 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
12602 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
12605 SDLoc dl(GA); // ? function entry point might be better
12606 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
12607 DAG.getNode(X86ISD::GlobalBaseReg,
12608 SDLoc(), PtrVT), InFlag);
12609 InFlag = Chain.getValue(1);
12611 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
12614 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
12616 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
12618 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT,
12619 X86::RAX, X86II::MO_TLSGD);
12622 static SDValue LowerToTLSLocalDynamicModel(GlobalAddressSDNode *GA,
12628 // Get the start address of the TLS block for this module.
12629 X86MachineFunctionInfo* MFI = DAG.getMachineFunction()
12630 .getInfo<X86MachineFunctionInfo>();
12631 MFI->incNumLocalDynamicTLSAccesses();
12635 Base = GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT, X86::RAX,
12636 X86II::MO_TLSLD, /*LocalDynamic=*/true);
12639 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
12640 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), InFlag);
12641 InFlag = Chain.getValue(1);
12642 Base = GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX,
12643 X86II::MO_TLSLDM, /*LocalDynamic=*/true);
12646 // Note: the CleanupLocalDynamicTLSPass will remove redundant computations
12650 unsigned char OperandFlags = X86II::MO_DTPOFF;
12651 unsigned WrapperKind = X86ISD::Wrapper;
12652 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
12653 GA->getValueType(0),
12654 GA->getOffset(), OperandFlags);
12655 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
12657 // Add x@dtpoff with the base.
12658 return DAG.getNode(ISD::ADD, dl, PtrVT, Offset, Base);
12661 // Lower ISD::GlobalTLSAddress using the "initial exec" or "local exec" model.
12662 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
12663 const EVT PtrVT, TLSModel::Model model,
12664 bool is64Bit, bool isPIC) {
12667 // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit).
12668 Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(*DAG.getContext(),
12669 is64Bit ? 257 : 256));
12671 SDValue ThreadPointer =
12672 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), DAG.getIntPtrConstant(0),
12673 MachinePointerInfo(Ptr), false, false, false, 0);
12675 unsigned char OperandFlags = 0;
12676 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
12678 unsigned WrapperKind = X86ISD::Wrapper;
12679 if (model == TLSModel::LocalExec) {
12680 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
12681 } else if (model == TLSModel::InitialExec) {
12683 OperandFlags = X86II::MO_GOTTPOFF;
12684 WrapperKind = X86ISD::WrapperRIP;
12686 OperandFlags = isPIC ? X86II::MO_GOTNTPOFF : X86II::MO_INDNTPOFF;
12689 llvm_unreachable("Unexpected model");
12692 // emit "addl x@ntpoff,%eax" (local exec)
12693 // or "addl x@indntpoff,%eax" (initial exec)
12694 // or "addl x@gotntpoff(%ebx) ,%eax" (initial exec, 32-bit pic)
12696 DAG.getTargetGlobalAddress(GA->getGlobal(), dl, GA->getValueType(0),
12697 GA->getOffset(), OperandFlags);
12698 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
12700 if (model == TLSModel::InitialExec) {
12701 if (isPIC && !is64Bit) {
12702 Offset = DAG.getNode(ISD::ADD, dl, PtrVT,
12703 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT),
12707 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
12708 MachinePointerInfo::getGOT(), false, false, false, 0);
12711 // The address of the thread local variable is the add of the thread
12712 // pointer with the offset of the variable.
12713 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
12717 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
12719 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
12720 const GlobalValue *GV = GA->getGlobal();
12722 if (Subtarget->isTargetELF()) {
12723 TLSModel::Model model = DAG.getTarget().getTLSModel(GV);
12726 case TLSModel::GeneralDynamic:
12727 if (Subtarget->is64Bit())
12728 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy());
12729 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy());
12730 case TLSModel::LocalDynamic:
12731 return LowerToTLSLocalDynamicModel(GA, DAG, getPointerTy(),
12732 Subtarget->is64Bit());
12733 case TLSModel::InitialExec:
12734 case TLSModel::LocalExec:
12735 return LowerToTLSExecModel(
12736 GA, DAG, getPointerTy(), model, Subtarget->is64Bit(),
12737 DAG.getTarget().getRelocationModel() == Reloc::PIC_);
12739 llvm_unreachable("Unknown TLS model.");
12742 if (Subtarget->isTargetDarwin()) {
12743 // Darwin only has one model of TLS. Lower to that.
12744 unsigned char OpFlag = 0;
12745 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ?
12746 X86ISD::WrapperRIP : X86ISD::Wrapper;
12748 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
12749 // global base reg.
12750 bool PIC32 = (DAG.getTarget().getRelocationModel() == Reloc::PIC_) &&
12751 !Subtarget->is64Bit();
12753 OpFlag = X86II::MO_TLVP_PIC_BASE;
12755 OpFlag = X86II::MO_TLVP;
12757 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL,
12758 GA->getValueType(0),
12759 GA->getOffset(), OpFlag);
12760 SDValue Offset = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
12762 // With PIC32, the address is actually $g + Offset.
12764 Offset = DAG.getNode(ISD::ADD, DL, getPointerTy(),
12765 DAG.getNode(X86ISD::GlobalBaseReg,
12766 SDLoc(), getPointerTy()),
12769 // Lowering the machine isd will make sure everything is in the right
12771 SDValue Chain = DAG.getEntryNode();
12772 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
12773 SDValue Args[] = { Chain, Offset };
12774 Chain = DAG.getNode(X86ISD::TLSCALL, DL, NodeTys, Args);
12776 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls.
12777 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
12778 MFI->setAdjustsStack(true);
12780 // And our return value (tls address) is in the standard call return value
12782 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
12783 return DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(),
12784 Chain.getValue(1));
12787 if (Subtarget->isTargetKnownWindowsMSVC() ||
12788 Subtarget->isTargetWindowsGNU()) {
12789 // Just use the implicit TLS architecture
12790 // Need to generate someting similar to:
12791 // mov rdx, qword [gs:abs 58H]; Load pointer to ThreadLocalStorage
12793 // mov ecx, dword [rel _tls_index]: Load index (from C runtime)
12794 // mov rcx, qword [rdx+rcx*8]
12795 // mov eax, .tls$:tlsvar
12796 // [rax+rcx] contains the address
12797 // Windows 64bit: gs:0x58
12798 // Windows 32bit: fs:__tls_array
12801 SDValue Chain = DAG.getEntryNode();
12803 // Get the Thread Pointer, which is %fs:__tls_array (32-bit) or
12804 // %gs:0x58 (64-bit). On MinGW, __tls_array is not available, so directly
12805 // use its literal value of 0x2C.
12806 Value *Ptr = Constant::getNullValue(Subtarget->is64Bit()
12807 ? Type::getInt8PtrTy(*DAG.getContext(),
12809 : Type::getInt32PtrTy(*DAG.getContext(),
12813 Subtarget->is64Bit()
12814 ? DAG.getIntPtrConstant(0x58)
12815 : (Subtarget->isTargetWindowsGNU()
12816 ? DAG.getIntPtrConstant(0x2C)
12817 : DAG.getExternalSymbol("_tls_array", getPointerTy()));
12819 SDValue ThreadPointer =
12820 DAG.getLoad(getPointerTy(), dl, Chain, TlsArray,
12821 MachinePointerInfo(Ptr), false, false, false, 0);
12823 // Load the _tls_index variable
12824 SDValue IDX = DAG.getExternalSymbol("_tls_index", getPointerTy());
12825 if (Subtarget->is64Bit())
12826 IDX = DAG.getExtLoad(ISD::ZEXTLOAD, dl, getPointerTy(), Chain,
12827 IDX, MachinePointerInfo(), MVT::i32,
12828 false, false, false, 0);
12830 IDX = DAG.getLoad(getPointerTy(), dl, Chain, IDX, MachinePointerInfo(),
12831 false, false, false, 0);
12833 SDValue Scale = DAG.getConstant(Log2_64_Ceil(TD->getPointerSize()),
12835 IDX = DAG.getNode(ISD::SHL, dl, getPointerTy(), IDX, Scale);
12837 SDValue res = DAG.getNode(ISD::ADD, dl, getPointerTy(), ThreadPointer, IDX);
12838 res = DAG.getLoad(getPointerTy(), dl, Chain, res, MachinePointerInfo(),
12839 false, false, false, 0);
12841 // Get the offset of start of .tls section
12842 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
12843 GA->getValueType(0),
12844 GA->getOffset(), X86II::MO_SECREL);
12845 SDValue Offset = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), TGA);
12847 // The address of the thread local variable is the add of the thread
12848 // pointer with the offset of the variable.
12849 return DAG.getNode(ISD::ADD, dl, getPointerTy(), res, Offset);
12852 llvm_unreachable("TLS not implemented for this target.");
12855 /// LowerShiftParts - Lower SRA_PARTS and friends, which return two i32 values
12856 /// and take a 2 x i32 value to shift plus a shift amount.
12857 static SDValue LowerShiftParts(SDValue Op, SelectionDAG &DAG) {
12858 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
12859 MVT VT = Op.getSimpleValueType();
12860 unsigned VTBits = VT.getSizeInBits();
12862 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
12863 SDValue ShOpLo = Op.getOperand(0);
12864 SDValue ShOpHi = Op.getOperand(1);
12865 SDValue ShAmt = Op.getOperand(2);
12866 // X86ISD::SHLD and X86ISD::SHRD have defined overflow behavior but the
12867 // generic ISD nodes haven't. Insert an AND to be safe, it's optimized away
12869 SDValue SafeShAmt = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
12870 DAG.getConstant(VTBits - 1, MVT::i8));
12871 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
12872 DAG.getConstant(VTBits - 1, MVT::i8))
12873 : DAG.getConstant(0, VT);
12875 SDValue Tmp2, Tmp3;
12876 if (Op.getOpcode() == ISD::SHL_PARTS) {
12877 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
12878 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, SafeShAmt);
12880 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
12881 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, SafeShAmt);
12884 // If the shift amount is larger or equal than the width of a part we can't
12885 // rely on the results of shld/shrd. Insert a test and select the appropriate
12886 // values for large shift amounts.
12887 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
12888 DAG.getConstant(VTBits, MVT::i8));
12889 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
12890 AndNode, DAG.getConstant(0, MVT::i8));
12893 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8);
12894 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
12895 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
12897 if (Op.getOpcode() == ISD::SHL_PARTS) {
12898 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
12899 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
12901 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
12902 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
12905 SDValue Ops[2] = { Lo, Hi };
12906 return DAG.getMergeValues(Ops, dl);
12909 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op,
12910 SelectionDAG &DAG) const {
12911 MVT SrcVT = Op.getOperand(0).getSimpleValueType();
12913 if (SrcVT.isVector())
12916 assert(SrcVT <= MVT::i64 && SrcVT >= MVT::i16 &&
12917 "Unknown SINT_TO_FP to lower!");
12919 // These are really Legal; return the operand so the caller accepts it as
12921 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
12923 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
12924 Subtarget->is64Bit()) {
12929 unsigned Size = SrcVT.getSizeInBits()/8;
12930 MachineFunction &MF = DAG.getMachineFunction();
12931 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false);
12932 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
12933 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
12935 MachinePointerInfo::getFixedStack(SSFI),
12937 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
12940 SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
12942 SelectionDAG &DAG) const {
12946 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
12948 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Glue);
12950 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
12952 unsigned ByteSize = SrcVT.getSizeInBits()/8;
12954 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(StackSlot);
12955 MachineMemOperand *MMO;
12957 int SSFI = FI->getIndex();
12959 DAG.getMachineFunction()
12960 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
12961 MachineMemOperand::MOLoad, ByteSize, ByteSize);
12963 MMO = cast<LoadSDNode>(StackSlot)->getMemOperand();
12964 StackSlot = StackSlot.getOperand(1);
12966 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) };
12967 SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG :
12969 Tys, Ops, SrcVT, MMO);
12972 Chain = Result.getValue(1);
12973 SDValue InFlag = Result.getValue(2);
12975 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
12976 // shouldn't be necessary except that RFP cannot be live across
12977 // multiple blocks. When stackifier is fixed, they can be uncoupled.
12978 MachineFunction &MF = DAG.getMachineFunction();
12979 unsigned SSFISize = Op.getValueType().getSizeInBits()/8;
12980 int SSFI = MF.getFrameInfo()->CreateStackObject(SSFISize, SSFISize, false);
12981 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
12982 Tys = DAG.getVTList(MVT::Other);
12984 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag
12986 MachineMemOperand *MMO =
12987 DAG.getMachineFunction()
12988 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
12989 MachineMemOperand::MOStore, SSFISize, SSFISize);
12991 Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys,
12992 Ops, Op.getValueType(), MMO);
12993 Result = DAG.getLoad(Op.getValueType(), DL, Chain, StackSlot,
12994 MachinePointerInfo::getFixedStack(SSFI),
12995 false, false, false, 0);
13001 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
13002 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op,
13003 SelectionDAG &DAG) const {
13004 // This algorithm is not obvious. Here it is what we're trying to output:
13007 punpckldq (c0), %xmm0 // c0: (uint4){ 0x43300000U, 0x45300000U, 0U, 0U }
13008 subpd (c1), %xmm0 // c1: (double2){ 0x1.0p52, 0x1.0p52 * 0x1.0p32 }
13010 haddpd %xmm0, %xmm0
13012 pshufd $0x4e, %xmm0, %xmm1
13018 LLVMContext *Context = DAG.getContext();
13020 // Build some magic constants.
13021 static const uint32_t CV0[] = { 0x43300000, 0x45300000, 0, 0 };
13022 Constant *C0 = ConstantDataVector::get(*Context, CV0);
13023 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16);
13025 SmallVector<Constant*,2> CV1;
13027 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
13028 APInt(64, 0x4330000000000000ULL))));
13030 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
13031 APInt(64, 0x4530000000000000ULL))));
13032 Constant *C1 = ConstantVector::get(CV1);
13033 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16);
13035 // Load the 64-bit value into an XMM register.
13036 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
13038 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
13039 MachinePointerInfo::getConstantPool(),
13040 false, false, false, 16);
13041 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32,
13042 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, XR1),
13045 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
13046 MachinePointerInfo::getConstantPool(),
13047 false, false, false, 16);
13048 SDValue XR2F = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Unpck1);
13049 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
13052 if (Subtarget->hasSSE3()) {
13053 // FIXME: The 'haddpd' instruction may be slower than 'movhlps + addsd'.
13054 Result = DAG.getNode(X86ISD::FHADD, dl, MVT::v2f64, Sub, Sub);
13056 SDValue S2F = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Sub);
13057 SDValue Shuffle = getTargetShuffleNode(X86ISD::PSHUFD, dl, MVT::v4i32,
13059 Result = DAG.getNode(ISD::FADD, dl, MVT::v2f64,
13060 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Shuffle),
13064 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Result,
13065 DAG.getIntPtrConstant(0));
13068 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
13069 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op,
13070 SelectionDAG &DAG) const {
13072 // FP constant to bias correct the final result.
13073 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
13076 // Load the 32-bit value into an XMM register.
13077 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
13080 // Zero out the upper parts of the register.
13081 Load = getShuffleVectorZeroOrUndef(Load, 0, true, Subtarget, DAG);
13083 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
13084 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Load),
13085 DAG.getIntPtrConstant(0));
13087 // Or the load with the bias.
13088 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64,
13089 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
13090 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
13091 MVT::v2f64, Load)),
13092 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
13093 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
13094 MVT::v2f64, Bias)));
13095 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
13096 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or),
13097 DAG.getIntPtrConstant(0));
13099 // Subtract the bias.
13100 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
13102 // Handle final rounding.
13103 EVT DestVT = Op.getValueType();
13105 if (DestVT.bitsLT(MVT::f64))
13106 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
13107 DAG.getIntPtrConstant(0));
13108 if (DestVT.bitsGT(MVT::f64))
13109 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
13111 // Handle final rounding.
13115 SDValue X86TargetLowering::lowerUINT_TO_FP_vec(SDValue Op,
13116 SelectionDAG &DAG) const {
13117 SDValue N0 = Op.getOperand(0);
13118 MVT SVT = N0.getSimpleValueType();
13121 assert((SVT == MVT::v4i8 || SVT == MVT::v4i16 ||
13122 SVT == MVT::v8i8 || SVT == MVT::v8i16) &&
13123 "Custom UINT_TO_FP is not supported!");
13125 MVT NVT = MVT::getVectorVT(MVT::i32, SVT.getVectorNumElements());
13126 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
13127 DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, N0));
13130 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op,
13131 SelectionDAG &DAG) const {
13132 SDValue N0 = Op.getOperand(0);
13135 if (Op.getValueType().isVector())
13136 return lowerUINT_TO_FP_vec(Op, DAG);
13138 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't
13139 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
13140 // the optimization here.
13141 if (DAG.SignBitIsZero(N0))
13142 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
13144 MVT SrcVT = N0.getSimpleValueType();
13145 MVT DstVT = Op.getSimpleValueType();
13146 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64)
13147 return LowerUINT_TO_FP_i64(Op, DAG);
13148 if (SrcVT == MVT::i32 && X86ScalarSSEf64)
13149 return LowerUINT_TO_FP_i32(Op, DAG);
13150 if (Subtarget->is64Bit() && SrcVT == MVT::i64 && DstVT == MVT::f32)
13153 // Make a 64-bit buffer, and use it to build an FILD.
13154 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
13155 if (SrcVT == MVT::i32) {
13156 SDValue WordOff = DAG.getConstant(4, getPointerTy());
13157 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl,
13158 getPointerTy(), StackSlot, WordOff);
13159 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
13160 StackSlot, MachinePointerInfo(),
13162 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32),
13163 OffsetSlot, MachinePointerInfo(),
13165 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
13169 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP");
13170 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
13171 StackSlot, MachinePointerInfo(),
13173 // For i64 source, we need to add the appropriate power of 2 if the input
13174 // was negative. This is the same as the optimization in
13175 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here,
13176 // we must be careful to do the computation in x87 extended precision, not
13177 // in SSE. (The generic code can't know it's OK to do this, or how to.)
13178 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex();
13179 MachineMemOperand *MMO =
13180 DAG.getMachineFunction()
13181 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
13182 MachineMemOperand::MOLoad, 8, 8);
13184 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other);
13185 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) };
13186 SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops,
13189 APInt FF(32, 0x5F800000ULL);
13191 // Check whether the sign bit is set.
13192 SDValue SignSet = DAG.getSetCC(dl,
13193 getSetCCResultType(*DAG.getContext(), MVT::i64),
13194 Op.getOperand(0), DAG.getConstant(0, MVT::i64),
13197 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
13198 SDValue FudgePtr = DAG.getConstantPool(
13199 ConstantInt::get(*DAG.getContext(), FF.zext(64)),
13202 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
13203 SDValue Zero = DAG.getIntPtrConstant(0);
13204 SDValue Four = DAG.getIntPtrConstant(4);
13205 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
13207 FudgePtr = DAG.getNode(ISD::ADD, dl, getPointerTy(), FudgePtr, Offset);
13209 // Load the value out, extending it from f32 to f80.
13210 // FIXME: Avoid the extend by constructing the right constant pool?
13211 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, MVT::f80, DAG.getEntryNode(),
13212 FudgePtr, MachinePointerInfo::getConstantPool(),
13213 MVT::f32, false, false, false, 4);
13214 // Extend everything to 80 bits to force it to be done on x87.
13215 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge);
13216 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add, DAG.getIntPtrConstant(0));
13219 std::pair<SDValue,SDValue>
13220 X86TargetLowering:: FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG,
13221 bool IsSigned, bool IsReplace) const {
13224 EVT DstTy = Op.getValueType();
13226 if (!IsSigned && !isIntegerTypeFTOL(DstTy)) {
13227 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
13231 assert(DstTy.getSimpleVT() <= MVT::i64 &&
13232 DstTy.getSimpleVT() >= MVT::i16 &&
13233 "Unknown FP_TO_INT to lower!");
13235 // These are really Legal.
13236 if (DstTy == MVT::i32 &&
13237 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
13238 return std::make_pair(SDValue(), SDValue());
13239 if (Subtarget->is64Bit() &&
13240 DstTy == MVT::i64 &&
13241 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
13242 return std::make_pair(SDValue(), SDValue());
13244 // We lower FP->int64 either into FISTP64 followed by a load from a temporary
13245 // stack slot, or into the FTOL runtime function.
13246 MachineFunction &MF = DAG.getMachineFunction();
13247 unsigned MemSize = DstTy.getSizeInBits()/8;
13248 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
13249 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
13252 if (!IsSigned && isIntegerTypeFTOL(DstTy))
13253 Opc = X86ISD::WIN_FTOL;
13255 switch (DstTy.getSimpleVT().SimpleTy) {
13256 default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
13257 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
13258 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
13259 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
13262 SDValue Chain = DAG.getEntryNode();
13263 SDValue Value = Op.getOperand(0);
13264 EVT TheVT = Op.getOperand(0).getValueType();
13265 // FIXME This causes a redundant load/store if the SSE-class value is already
13266 // in memory, such as if it is on the callstack.
13267 if (isScalarFPTypeInSSEReg(TheVT)) {
13268 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
13269 Chain = DAG.getStore(Chain, DL, Value, StackSlot,
13270 MachinePointerInfo::getFixedStack(SSFI),
13272 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
13274 Chain, StackSlot, DAG.getValueType(TheVT)
13277 MachineMemOperand *MMO =
13278 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
13279 MachineMemOperand::MOLoad, MemSize, MemSize);
13280 Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops, DstTy, MMO);
13281 Chain = Value.getValue(1);
13282 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
13283 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
13286 MachineMemOperand *MMO =
13287 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
13288 MachineMemOperand::MOStore, MemSize, MemSize);
13290 if (Opc != X86ISD::WIN_FTOL) {
13291 // Build the FP_TO_INT*_IN_MEM
13292 SDValue Ops[] = { Chain, Value, StackSlot };
13293 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
13295 return std::make_pair(FIST, StackSlot);
13297 SDValue ftol = DAG.getNode(X86ISD::WIN_FTOL, DL,
13298 DAG.getVTList(MVT::Other, MVT::Glue),
13300 SDValue eax = DAG.getCopyFromReg(ftol, DL, X86::EAX,
13301 MVT::i32, ftol.getValue(1));
13302 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), DL, X86::EDX,
13303 MVT::i32, eax.getValue(2));
13304 SDValue Ops[] = { eax, edx };
13305 SDValue pair = IsReplace
13306 ? DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops)
13307 : DAG.getMergeValues(Ops, DL);
13308 return std::make_pair(pair, SDValue());
13312 static SDValue LowerAVXExtend(SDValue Op, SelectionDAG &DAG,
13313 const X86Subtarget *Subtarget) {
13314 MVT VT = Op->getSimpleValueType(0);
13315 SDValue In = Op->getOperand(0);
13316 MVT InVT = In.getSimpleValueType();
13319 // Optimize vectors in AVX mode:
13322 // Use vpunpcklwd for 4 lower elements v8i16 -> v4i32.
13323 // Use vpunpckhwd for 4 upper elements v8i16 -> v4i32.
13324 // Concat upper and lower parts.
13327 // Use vpunpckldq for 4 lower elements v4i32 -> v2i64.
13328 // Use vpunpckhdq for 4 upper elements v4i32 -> v2i64.
13329 // Concat upper and lower parts.
13332 if (((VT != MVT::v16i16) || (InVT != MVT::v16i8)) &&
13333 ((VT != MVT::v8i32) || (InVT != MVT::v8i16)) &&
13334 ((VT != MVT::v4i64) || (InVT != MVT::v4i32)))
13337 if (Subtarget->hasInt256())
13338 return DAG.getNode(X86ISD::VZEXT, dl, VT, In);
13340 SDValue ZeroVec = getZeroVector(InVT, Subtarget, DAG, dl);
13341 SDValue Undef = DAG.getUNDEF(InVT);
13342 bool NeedZero = Op.getOpcode() == ISD::ZERO_EXTEND;
13343 SDValue OpLo = getUnpackl(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
13344 SDValue OpHi = getUnpackh(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
13346 MVT HVT = MVT::getVectorVT(VT.getVectorElementType(),
13347 VT.getVectorNumElements()/2);
13349 OpLo = DAG.getNode(ISD::BITCAST, dl, HVT, OpLo);
13350 OpHi = DAG.getNode(ISD::BITCAST, dl, HVT, OpHi);
13352 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
13355 static SDValue LowerZERO_EXTEND_AVX512(SDValue Op,
13356 SelectionDAG &DAG) {
13357 MVT VT = Op->getSimpleValueType(0);
13358 SDValue In = Op->getOperand(0);
13359 MVT InVT = In.getSimpleValueType();
13361 unsigned int NumElts = VT.getVectorNumElements();
13362 if (NumElts != 8 && NumElts != 16)
13365 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1)
13366 return DAG.getNode(X86ISD::VZEXT, DL, VT, In);
13368 EVT ExtVT = (NumElts == 8)? MVT::v8i64 : MVT::v16i32;
13369 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13370 // Now we have only mask extension
13371 assert(InVT.getVectorElementType() == MVT::i1);
13372 SDValue Cst = DAG.getTargetConstant(1, ExtVT.getScalarType());
13373 const Constant *C = (dyn_cast<ConstantSDNode>(Cst))->getConstantIntValue();
13374 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
13375 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
13376 SDValue Ld = DAG.getLoad(Cst.getValueType(), DL, DAG.getEntryNode(), CP,
13377 MachinePointerInfo::getConstantPool(),
13378 false, false, false, Alignment);
13380 SDValue Brcst = DAG.getNode(X86ISD::VBROADCASTM, DL, ExtVT, In, Ld);
13381 if (VT.is512BitVector())
13383 return DAG.getNode(X86ISD::VTRUNC, DL, VT, Brcst);
13386 static SDValue LowerANY_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
13387 SelectionDAG &DAG) {
13388 if (Subtarget->hasFp256()) {
13389 SDValue Res = LowerAVXExtend(Op, DAG, Subtarget);
13397 static SDValue LowerZERO_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
13398 SelectionDAG &DAG) {
13400 MVT VT = Op.getSimpleValueType();
13401 SDValue In = Op.getOperand(0);
13402 MVT SVT = In.getSimpleValueType();
13404 if (VT.is512BitVector() || SVT.getVectorElementType() == MVT::i1)
13405 return LowerZERO_EXTEND_AVX512(Op, DAG);
13407 if (Subtarget->hasFp256()) {
13408 SDValue Res = LowerAVXExtend(Op, DAG, Subtarget);
13413 assert(!VT.is256BitVector() || !SVT.is128BitVector() ||
13414 VT.getVectorNumElements() != SVT.getVectorNumElements());
13418 SDValue X86TargetLowering::LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const {
13420 MVT VT = Op.getSimpleValueType();
13421 SDValue In = Op.getOperand(0);
13422 MVT InVT = In.getSimpleValueType();
13424 if (VT == MVT::i1) {
13425 assert((InVT.isInteger() && (InVT.getSizeInBits() <= 64)) &&
13426 "Invalid scalar TRUNCATE operation");
13427 if (InVT.getSizeInBits() >= 32)
13429 In = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, In);
13430 return DAG.getNode(ISD::TRUNCATE, DL, VT, In);
13432 assert(VT.getVectorNumElements() == InVT.getVectorNumElements() &&
13433 "Invalid TRUNCATE operation");
13435 if (InVT.is512BitVector() || VT.getVectorElementType() == MVT::i1) {
13436 if (VT.getVectorElementType().getSizeInBits() >=8)
13437 return DAG.getNode(X86ISD::VTRUNC, DL, VT, In);
13439 assert(VT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
13440 unsigned NumElts = InVT.getVectorNumElements();
13441 assert ((NumElts == 8 || NumElts == 16) && "Unexpected vector type");
13442 if (InVT.getSizeInBits() < 512) {
13443 MVT ExtVT = (NumElts == 16)? MVT::v16i32 : MVT::v8i64;
13444 In = DAG.getNode(ISD::SIGN_EXTEND, DL, ExtVT, In);
13448 SDValue Cst = DAG.getTargetConstant(1, InVT.getVectorElementType());
13449 const Constant *C = (dyn_cast<ConstantSDNode>(Cst))->getConstantIntValue();
13450 SDValue CP = DAG.getConstantPool(C, getPointerTy());
13451 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
13452 SDValue Ld = DAG.getLoad(Cst.getValueType(), DL, DAG.getEntryNode(), CP,
13453 MachinePointerInfo::getConstantPool(),
13454 false, false, false, Alignment);
13455 SDValue OneV = DAG.getNode(X86ISD::VBROADCAST, DL, InVT, Ld);
13456 SDValue And = DAG.getNode(ISD::AND, DL, InVT, OneV, In);
13457 return DAG.getNode(X86ISD::TESTM, DL, VT, And, And);
13460 if ((VT == MVT::v4i32) && (InVT == MVT::v4i64)) {
13461 // On AVX2, v4i64 -> v4i32 becomes VPERMD.
13462 if (Subtarget->hasInt256()) {
13463 static const int ShufMask[] = {0, 2, 4, 6, -1, -1, -1, -1};
13464 In = DAG.getNode(ISD::BITCAST, DL, MVT::v8i32, In);
13465 In = DAG.getVectorShuffle(MVT::v8i32, DL, In, DAG.getUNDEF(MVT::v8i32),
13467 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, In,
13468 DAG.getIntPtrConstant(0));
13471 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
13472 DAG.getIntPtrConstant(0));
13473 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
13474 DAG.getIntPtrConstant(2));
13475 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo);
13476 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi);
13477 static const int ShufMask[] = {0, 2, 4, 6};
13478 return DAG.getVectorShuffle(VT, DL, OpLo, OpHi, ShufMask);
13481 if ((VT == MVT::v8i16) && (InVT == MVT::v8i32)) {
13482 // On AVX2, v8i32 -> v8i16 becomed PSHUFB.
13483 if (Subtarget->hasInt256()) {
13484 In = DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, In);
13486 SmallVector<SDValue,32> pshufbMask;
13487 for (unsigned i = 0; i < 2; ++i) {
13488 pshufbMask.push_back(DAG.getConstant(0x0, MVT::i8));
13489 pshufbMask.push_back(DAG.getConstant(0x1, MVT::i8));
13490 pshufbMask.push_back(DAG.getConstant(0x4, MVT::i8));
13491 pshufbMask.push_back(DAG.getConstant(0x5, MVT::i8));
13492 pshufbMask.push_back(DAG.getConstant(0x8, MVT::i8));
13493 pshufbMask.push_back(DAG.getConstant(0x9, MVT::i8));
13494 pshufbMask.push_back(DAG.getConstant(0xc, MVT::i8));
13495 pshufbMask.push_back(DAG.getConstant(0xd, MVT::i8));
13496 for (unsigned j = 0; j < 8; ++j)
13497 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
13499 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, pshufbMask);
13500 In = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v32i8, In, BV);
13501 In = DAG.getNode(ISD::BITCAST, DL, MVT::v4i64, In);
13503 static const int ShufMask[] = {0, 2, -1, -1};
13504 In = DAG.getVectorShuffle(MVT::v4i64, DL, In, DAG.getUNDEF(MVT::v4i64),
13506 In = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
13507 DAG.getIntPtrConstant(0));
13508 return DAG.getNode(ISD::BITCAST, DL, VT, In);
13511 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
13512 DAG.getIntPtrConstant(0));
13514 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
13515 DAG.getIntPtrConstant(4));
13517 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpLo);
13518 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpHi);
13520 // The PSHUFB mask:
13521 static const int ShufMask1[] = {0, 1, 4, 5, 8, 9, 12, 13,
13522 -1, -1, -1, -1, -1, -1, -1, -1};
13524 SDValue Undef = DAG.getUNDEF(MVT::v16i8);
13525 OpLo = DAG.getVectorShuffle(MVT::v16i8, DL, OpLo, Undef, ShufMask1);
13526 OpHi = DAG.getVectorShuffle(MVT::v16i8, DL, OpHi, Undef, ShufMask1);
13528 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo);
13529 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi);
13531 // The MOVLHPS Mask:
13532 static const int ShufMask2[] = {0, 1, 4, 5};
13533 SDValue res = DAG.getVectorShuffle(MVT::v4i32, DL, OpLo, OpHi, ShufMask2);
13534 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, res);
13537 // Handle truncation of V256 to V128 using shuffles.
13538 if (!VT.is128BitVector() || !InVT.is256BitVector())
13541 assert(Subtarget->hasFp256() && "256-bit vector without AVX!");
13543 unsigned NumElems = VT.getVectorNumElements();
13544 MVT NVT = MVT::getVectorVT(VT.getVectorElementType(), NumElems * 2);
13546 SmallVector<int, 16> MaskVec(NumElems * 2, -1);
13547 // Prepare truncation shuffle mask
13548 for (unsigned i = 0; i != NumElems; ++i)
13549 MaskVec[i] = i * 2;
13550 SDValue V = DAG.getVectorShuffle(NVT, DL,
13551 DAG.getNode(ISD::BITCAST, DL, NVT, In),
13552 DAG.getUNDEF(NVT), &MaskVec[0]);
13553 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, V,
13554 DAG.getIntPtrConstant(0));
13557 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op,
13558 SelectionDAG &DAG) const {
13559 assert(!Op.getSimpleValueType().isVector());
13561 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
13562 /*IsSigned=*/ true, /*IsReplace=*/ false);
13563 SDValue FIST = Vals.first, StackSlot = Vals.second;
13564 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
13565 if (!FIST.getNode()) return Op;
13567 if (StackSlot.getNode())
13568 // Load the result.
13569 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
13570 FIST, StackSlot, MachinePointerInfo(),
13571 false, false, false, 0);
13573 // The node is the result.
13577 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op,
13578 SelectionDAG &DAG) const {
13579 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
13580 /*IsSigned=*/ false, /*IsReplace=*/ false);
13581 SDValue FIST = Vals.first, StackSlot = Vals.second;
13582 assert(FIST.getNode() && "Unexpected failure");
13584 if (StackSlot.getNode())
13585 // Load the result.
13586 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
13587 FIST, StackSlot, MachinePointerInfo(),
13588 false, false, false, 0);
13590 // The node is the result.
13594 static SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) {
13596 MVT VT = Op.getSimpleValueType();
13597 SDValue In = Op.getOperand(0);
13598 MVT SVT = In.getSimpleValueType();
13600 assert(SVT == MVT::v2f32 && "Only customize MVT::v2f32 type legalization!");
13602 return DAG.getNode(X86ISD::VFPEXT, DL, VT,
13603 DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v4f32,
13604 In, DAG.getUNDEF(SVT)));
13607 // The only differences between FABS and FNEG are the mask and the logic op.
13608 static SDValue LowerFABSorFNEG(SDValue Op, SelectionDAG &DAG) {
13609 assert((Op.getOpcode() == ISD::FABS || Op.getOpcode() == ISD::FNEG) &&
13610 "Wrong opcode for lowering FABS or FNEG.");
13612 bool IsFABS = (Op.getOpcode() == ISD::FABS);
13614 MVT VT = Op.getSimpleValueType();
13615 // Assume scalar op for initialization; update for vector if needed.
13616 // Note that there are no scalar bitwise logical SSE/AVX instructions, so we
13617 // generate a 16-byte vector constant and logic op even for the scalar case.
13618 // Using a 16-byte mask allows folding the load of the mask with
13619 // the logic op, so it can save (~4 bytes) on code size.
13621 unsigned NumElts = VT == MVT::f64 ? 2 : 4;
13622 // FIXME: Use function attribute "OptimizeForSize" and/or CodeGenOpt::Level to
13623 // decide if we should generate a 16-byte constant mask when we only need 4 or
13624 // 8 bytes for the scalar case.
13625 if (VT.isVector()) {
13626 EltVT = VT.getVectorElementType();
13627 NumElts = VT.getVectorNumElements();
13630 unsigned EltBits = EltVT.getSizeInBits();
13631 LLVMContext *Context = DAG.getContext();
13632 // For FABS, mask is 0x7f...; for FNEG, mask is 0x80...
13634 IsFABS ? APInt::getSignedMaxValue(EltBits) : APInt::getSignBit(EltBits);
13635 Constant *C = ConstantInt::get(*Context, MaskElt);
13636 C = ConstantVector::getSplat(NumElts, C);
13637 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13638 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy());
13639 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
13640 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
13641 MachinePointerInfo::getConstantPool(),
13642 false, false, false, Alignment);
13644 if (VT.isVector()) {
13645 // For a vector, cast operands to a vector type, perform the logic op,
13646 // and cast the result back to the original value type.
13647 MVT VecVT = MVT::getVectorVT(MVT::i64, VT.getSizeInBits() / 64);
13648 SDValue Op0Casted = DAG.getNode(ISD::BITCAST, dl, VecVT, Op.getOperand(0));
13649 SDValue MaskCasted = DAG.getNode(ISD::BITCAST, dl, VecVT, Mask);
13650 unsigned LogicOp = IsFABS ? ISD::AND : ISD::XOR;
13651 return DAG.getNode(ISD::BITCAST, dl, VT,
13652 DAG.getNode(LogicOp, dl, VecVT, Op0Casted, MaskCasted));
13654 // If not vector, then scalar.
13655 unsigned LogicOp = IsFABS ? X86ISD::FAND : X86ISD::FXOR;
13656 return DAG.getNode(LogicOp, dl, VT, Op.getOperand(0), Mask);
13659 static SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) {
13660 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13661 LLVMContext *Context = DAG.getContext();
13662 SDValue Op0 = Op.getOperand(0);
13663 SDValue Op1 = Op.getOperand(1);
13665 MVT VT = Op.getSimpleValueType();
13666 MVT SrcVT = Op1.getSimpleValueType();
13668 // If second operand is smaller, extend it first.
13669 if (SrcVT.bitsLT(VT)) {
13670 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
13673 // And if it is bigger, shrink it first.
13674 if (SrcVT.bitsGT(VT)) {
13675 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1));
13679 // At this point the operands and the result should have the same
13680 // type, and that won't be f80 since that is not custom lowered.
13682 // First get the sign bit of second operand.
13683 SmallVector<Constant*,4> CV;
13684 if (SrcVT == MVT::f64) {
13685 const fltSemantics &Sem = APFloat::IEEEdouble;
13686 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 1ULL << 63))));
13687 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 0))));
13689 const fltSemantics &Sem = APFloat::IEEEsingle;
13690 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 1U << 31))));
13691 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
13692 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
13693 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
13695 Constant *C = ConstantVector::get(CV);
13696 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy(), 16);
13697 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx,
13698 MachinePointerInfo::getConstantPool(),
13699 false, false, false, 16);
13700 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1);
13702 // Shift sign bit right or left if the two operands have different types.
13703 if (SrcVT.bitsGT(VT)) {
13704 // Op0 is MVT::f32, Op1 is MVT::f64.
13705 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, SignBit);
13706 SignBit = DAG.getNode(X86ISD::FSRL, dl, MVT::v2f64, SignBit,
13707 DAG.getConstant(32, MVT::i32));
13708 SignBit = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, SignBit);
13709 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, SignBit,
13710 DAG.getIntPtrConstant(0));
13713 // Clear first operand sign bit.
13715 if (VT == MVT::f64) {
13716 const fltSemantics &Sem = APFloat::IEEEdouble;
13717 CV.push_back(ConstantFP::get(*Context, APFloat(Sem,
13718 APInt(64, ~(1ULL << 63)))));
13719 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 0))));
13721 const fltSemantics &Sem = APFloat::IEEEsingle;
13722 CV.push_back(ConstantFP::get(*Context, APFloat(Sem,
13723 APInt(32, ~(1U << 31)))));
13724 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
13725 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
13726 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
13728 C = ConstantVector::get(CV);
13729 CPIdx = DAG.getConstantPool(C, TLI.getPointerTy(), 16);
13730 SDValue Mask2 = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
13731 MachinePointerInfo::getConstantPool(),
13732 false, false, false, 16);
13733 SDValue Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Mask2);
13735 // Or the value with the sign bit.
13736 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit);
13739 static SDValue LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) {
13740 SDValue N0 = Op.getOperand(0);
13742 MVT VT = Op.getSimpleValueType();
13744 // Lower ISD::FGETSIGN to (AND (X86ISD::FGETSIGNx86 ...) 1).
13745 SDValue xFGETSIGN = DAG.getNode(X86ISD::FGETSIGNx86, dl, VT, N0,
13746 DAG.getConstant(1, VT));
13747 return DAG.getNode(ISD::AND, dl, VT, xFGETSIGN, DAG.getConstant(1, VT));
13750 // LowerVectorAllZeroTest - Check whether an OR'd tree is PTEST-able.
13752 static SDValue LowerVectorAllZeroTest(SDValue Op, const X86Subtarget *Subtarget,
13753 SelectionDAG &DAG) {
13754 assert(Op.getOpcode() == ISD::OR && "Only check OR'd tree.");
13756 if (!Subtarget->hasSSE41())
13759 if (!Op->hasOneUse())
13762 SDNode *N = Op.getNode();
13765 SmallVector<SDValue, 8> Opnds;
13766 DenseMap<SDValue, unsigned> VecInMap;
13767 SmallVector<SDValue, 8> VecIns;
13768 EVT VT = MVT::Other;
13770 // Recognize a special case where a vector is casted into wide integer to
13772 Opnds.push_back(N->getOperand(0));
13773 Opnds.push_back(N->getOperand(1));
13775 for (unsigned Slot = 0, e = Opnds.size(); Slot < e; ++Slot) {
13776 SmallVectorImpl<SDValue>::const_iterator I = Opnds.begin() + Slot;
13777 // BFS traverse all OR'd operands.
13778 if (I->getOpcode() == ISD::OR) {
13779 Opnds.push_back(I->getOperand(0));
13780 Opnds.push_back(I->getOperand(1));
13781 // Re-evaluate the number of nodes to be traversed.
13782 e += 2; // 2 more nodes (LHS and RHS) are pushed.
13786 // Quit if a non-EXTRACT_VECTOR_ELT
13787 if (I->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
13790 // Quit if without a constant index.
13791 SDValue Idx = I->getOperand(1);
13792 if (!isa<ConstantSDNode>(Idx))
13795 SDValue ExtractedFromVec = I->getOperand(0);
13796 DenseMap<SDValue, unsigned>::iterator M = VecInMap.find(ExtractedFromVec);
13797 if (M == VecInMap.end()) {
13798 VT = ExtractedFromVec.getValueType();
13799 // Quit if not 128/256-bit vector.
13800 if (!VT.is128BitVector() && !VT.is256BitVector())
13802 // Quit if not the same type.
13803 if (VecInMap.begin() != VecInMap.end() &&
13804 VT != VecInMap.begin()->first.getValueType())
13806 M = VecInMap.insert(std::make_pair(ExtractedFromVec, 0)).first;
13807 VecIns.push_back(ExtractedFromVec);
13809 M->second |= 1U << cast<ConstantSDNode>(Idx)->getZExtValue();
13812 assert((VT.is128BitVector() || VT.is256BitVector()) &&
13813 "Not extracted from 128-/256-bit vector.");
13815 unsigned FullMask = (1U << VT.getVectorNumElements()) - 1U;
13817 for (DenseMap<SDValue, unsigned>::const_iterator
13818 I = VecInMap.begin(), E = VecInMap.end(); I != E; ++I) {
13819 // Quit if not all elements are used.
13820 if (I->second != FullMask)
13824 EVT TestVT = VT.is128BitVector() ? MVT::v2i64 : MVT::v4i64;
13826 // Cast all vectors into TestVT for PTEST.
13827 for (unsigned i = 0, e = VecIns.size(); i < e; ++i)
13828 VecIns[i] = DAG.getNode(ISD::BITCAST, DL, TestVT, VecIns[i]);
13830 // If more than one full vectors are evaluated, OR them first before PTEST.
13831 for (unsigned Slot = 0, e = VecIns.size(); e - Slot > 1; Slot += 2, e += 1) {
13832 // Each iteration will OR 2 nodes and append the result until there is only
13833 // 1 node left, i.e. the final OR'd value of all vectors.
13834 SDValue LHS = VecIns[Slot];
13835 SDValue RHS = VecIns[Slot + 1];
13836 VecIns.push_back(DAG.getNode(ISD::OR, DL, TestVT, LHS, RHS));
13839 return DAG.getNode(X86ISD::PTEST, DL, MVT::i32,
13840 VecIns.back(), VecIns.back());
13843 /// \brief return true if \c Op has a use that doesn't just read flags.
13844 static bool hasNonFlagsUse(SDValue Op) {
13845 for (SDNode::use_iterator UI = Op->use_begin(), UE = Op->use_end(); UI != UE;
13847 SDNode *User = *UI;
13848 unsigned UOpNo = UI.getOperandNo();
13849 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
13850 // Look pass truncate.
13851 UOpNo = User->use_begin().getOperandNo();
13852 User = *User->use_begin();
13855 if (User->getOpcode() != ISD::BRCOND && User->getOpcode() != ISD::SETCC &&
13856 !(User->getOpcode() == ISD::SELECT && UOpNo == 0))
13862 /// Emit nodes that will be selected as "test Op0,Op0", or something
13864 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC, SDLoc dl,
13865 SelectionDAG &DAG) const {
13866 if (Op.getValueType() == MVT::i1)
13867 // KORTEST instruction should be selected
13868 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
13869 DAG.getConstant(0, Op.getValueType()));
13871 // CF and OF aren't always set the way we want. Determine which
13872 // of these we need.
13873 bool NeedCF = false;
13874 bool NeedOF = false;
13877 case X86::COND_A: case X86::COND_AE:
13878 case X86::COND_B: case X86::COND_BE:
13881 case X86::COND_G: case X86::COND_GE:
13882 case X86::COND_L: case X86::COND_LE:
13883 case X86::COND_O: case X86::COND_NO: {
13884 // Check if we really need to set the
13885 // Overflow flag. If NoSignedWrap is present
13886 // that is not actually needed.
13887 switch (Op->getOpcode()) {
13892 const BinaryWithFlagsSDNode *BinNode =
13893 cast<BinaryWithFlagsSDNode>(Op.getNode());
13894 if (BinNode->hasNoSignedWrap())
13904 // See if we can use the EFLAGS value from the operand instead of
13905 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
13906 // we prove that the arithmetic won't overflow, we can't use OF or CF.
13907 if (Op.getResNo() != 0 || NeedOF || NeedCF) {
13908 // Emit a CMP with 0, which is the TEST pattern.
13909 //if (Op.getValueType() == MVT::i1)
13910 // return DAG.getNode(X86ISD::CMP, dl, MVT::i1, Op,
13911 // DAG.getConstant(0, MVT::i1));
13912 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
13913 DAG.getConstant(0, Op.getValueType()));
13915 unsigned Opcode = 0;
13916 unsigned NumOperands = 0;
13918 // Truncate operations may prevent the merge of the SETCC instruction
13919 // and the arithmetic instruction before it. Attempt to truncate the operands
13920 // of the arithmetic instruction and use a reduced bit-width instruction.
13921 bool NeedTruncation = false;
13922 SDValue ArithOp = Op;
13923 if (Op->getOpcode() == ISD::TRUNCATE && Op->hasOneUse()) {
13924 SDValue Arith = Op->getOperand(0);
13925 // Both the trunc and the arithmetic op need to have one user each.
13926 if (Arith->hasOneUse())
13927 switch (Arith.getOpcode()) {
13934 NeedTruncation = true;
13940 // NOTICE: In the code below we use ArithOp to hold the arithmetic operation
13941 // which may be the result of a CAST. We use the variable 'Op', which is the
13942 // non-casted variable when we check for possible users.
13943 switch (ArithOp.getOpcode()) {
13945 // Due to an isel shortcoming, be conservative if this add is likely to be
13946 // selected as part of a load-modify-store instruction. When the root node
13947 // in a match is a store, isel doesn't know how to remap non-chain non-flag
13948 // uses of other nodes in the match, such as the ADD in this case. This
13949 // leads to the ADD being left around and reselected, with the result being
13950 // two adds in the output. Alas, even if none our users are stores, that
13951 // doesn't prove we're O.K. Ergo, if we have any parents that aren't
13952 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require
13953 // climbing the DAG back to the root, and it doesn't seem to be worth the
13955 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
13956 UE = Op.getNode()->use_end(); UI != UE; ++UI)
13957 if (UI->getOpcode() != ISD::CopyToReg &&
13958 UI->getOpcode() != ISD::SETCC &&
13959 UI->getOpcode() != ISD::STORE)
13962 if (ConstantSDNode *C =
13963 dyn_cast<ConstantSDNode>(ArithOp.getNode()->getOperand(1))) {
13964 // An add of one will be selected as an INC.
13965 if (C->getAPIntValue() == 1 && !Subtarget->slowIncDec()) {
13966 Opcode = X86ISD::INC;
13971 // An add of negative one (subtract of one) will be selected as a DEC.
13972 if (C->getAPIntValue().isAllOnesValue() && !Subtarget->slowIncDec()) {
13973 Opcode = X86ISD::DEC;
13979 // Otherwise use a regular EFLAGS-setting add.
13980 Opcode = X86ISD::ADD;
13985 // If we have a constant logical shift that's only used in a comparison
13986 // against zero turn it into an equivalent AND. This allows turning it into
13987 // a TEST instruction later.
13988 if ((X86CC == X86::COND_E || X86CC == X86::COND_NE) && Op->hasOneUse() &&
13989 isa<ConstantSDNode>(Op->getOperand(1)) && !hasNonFlagsUse(Op)) {
13990 EVT VT = Op.getValueType();
13991 unsigned BitWidth = VT.getSizeInBits();
13992 unsigned ShAmt = Op->getConstantOperandVal(1);
13993 if (ShAmt >= BitWidth) // Avoid undefined shifts.
13995 APInt Mask = ArithOp.getOpcode() == ISD::SRL
13996 ? APInt::getHighBitsSet(BitWidth, BitWidth - ShAmt)
13997 : APInt::getLowBitsSet(BitWidth, BitWidth - ShAmt);
13998 if (!Mask.isSignedIntN(32)) // Avoid large immediates.
14000 SDValue New = DAG.getNode(ISD::AND, dl, VT, Op->getOperand(0),
14001 DAG.getConstant(Mask, VT));
14002 DAG.ReplaceAllUsesWith(Op, New);
14008 // If the primary and result isn't used, don't bother using X86ISD::AND,
14009 // because a TEST instruction will be better.
14010 if (!hasNonFlagsUse(Op))
14016 // Due to the ISEL shortcoming noted above, be conservative if this op is
14017 // likely to be selected as part of a load-modify-store instruction.
14018 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
14019 UE = Op.getNode()->use_end(); UI != UE; ++UI)
14020 if (UI->getOpcode() == ISD::STORE)
14023 // Otherwise use a regular EFLAGS-setting instruction.
14024 switch (ArithOp.getOpcode()) {
14025 default: llvm_unreachable("unexpected operator!");
14026 case ISD::SUB: Opcode = X86ISD::SUB; break;
14027 case ISD::XOR: Opcode = X86ISD::XOR; break;
14028 case ISD::AND: Opcode = X86ISD::AND; break;
14030 if (!NeedTruncation && (X86CC == X86::COND_E || X86CC == X86::COND_NE)) {
14031 SDValue EFLAGS = LowerVectorAllZeroTest(Op, Subtarget, DAG);
14032 if (EFLAGS.getNode())
14035 Opcode = X86ISD::OR;
14049 return SDValue(Op.getNode(), 1);
14055 // If we found that truncation is beneficial, perform the truncation and
14057 if (NeedTruncation) {
14058 EVT VT = Op.getValueType();
14059 SDValue WideVal = Op->getOperand(0);
14060 EVT WideVT = WideVal.getValueType();
14061 unsigned ConvertedOp = 0;
14062 // Use a target machine opcode to prevent further DAGCombine
14063 // optimizations that may separate the arithmetic operations
14064 // from the setcc node.
14065 switch (WideVal.getOpcode()) {
14067 case ISD::ADD: ConvertedOp = X86ISD::ADD; break;
14068 case ISD::SUB: ConvertedOp = X86ISD::SUB; break;
14069 case ISD::AND: ConvertedOp = X86ISD::AND; break;
14070 case ISD::OR: ConvertedOp = X86ISD::OR; break;
14071 case ISD::XOR: ConvertedOp = X86ISD::XOR; break;
14075 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14076 if (TLI.isOperationLegal(WideVal.getOpcode(), WideVT)) {
14077 SDValue V0 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(0));
14078 SDValue V1 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(1));
14079 Op = DAG.getNode(ConvertedOp, dl, VT, V0, V1);
14085 // Emit a CMP with 0, which is the TEST pattern.
14086 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
14087 DAG.getConstant(0, Op.getValueType()));
14089 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
14090 SmallVector<SDValue, 4> Ops;
14091 for (unsigned i = 0; i != NumOperands; ++i)
14092 Ops.push_back(Op.getOperand(i));
14094 SDValue New = DAG.getNode(Opcode, dl, VTs, Ops);
14095 DAG.ReplaceAllUsesWith(Op, New);
14096 return SDValue(New.getNode(), 1);
14099 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
14101 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
14102 SDLoc dl, SelectionDAG &DAG) const {
14103 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1)) {
14104 if (C->getAPIntValue() == 0)
14105 return EmitTest(Op0, X86CC, dl, DAG);
14107 if (Op0.getValueType() == MVT::i1)
14108 llvm_unreachable("Unexpected comparison operation for MVT::i1 operands");
14111 if ((Op0.getValueType() == MVT::i8 || Op0.getValueType() == MVT::i16 ||
14112 Op0.getValueType() == MVT::i32 || Op0.getValueType() == MVT::i64)) {
14113 // Do the comparison at i32 if it's smaller, besides the Atom case.
14114 // This avoids subregister aliasing issues. Keep the smaller reference
14115 // if we're optimizing for size, however, as that'll allow better folding
14116 // of memory operations.
14117 if (Op0.getValueType() != MVT::i32 && Op0.getValueType() != MVT::i64 &&
14118 !DAG.getMachineFunction().getFunction()->getAttributes().hasAttribute(
14119 AttributeSet::FunctionIndex, Attribute::MinSize) &&
14120 !Subtarget->isAtom()) {
14121 unsigned ExtendOp =
14122 isX86CCUnsigned(X86CC) ? ISD::ZERO_EXTEND : ISD::SIGN_EXTEND;
14123 Op0 = DAG.getNode(ExtendOp, dl, MVT::i32, Op0);
14124 Op1 = DAG.getNode(ExtendOp, dl, MVT::i32, Op1);
14126 // Use SUB instead of CMP to enable CSE between SUB and CMP.
14127 SDVTList VTs = DAG.getVTList(Op0.getValueType(), MVT::i32);
14128 SDValue Sub = DAG.getNode(X86ISD::SUB, dl, VTs,
14130 return SDValue(Sub.getNode(), 1);
14132 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
14135 /// Convert a comparison if required by the subtarget.
14136 SDValue X86TargetLowering::ConvertCmpIfNecessary(SDValue Cmp,
14137 SelectionDAG &DAG) const {
14138 // If the subtarget does not support the FUCOMI instruction, floating-point
14139 // comparisons have to be converted.
14140 if (Subtarget->hasCMov() ||
14141 Cmp.getOpcode() != X86ISD::CMP ||
14142 !Cmp.getOperand(0).getValueType().isFloatingPoint() ||
14143 !Cmp.getOperand(1).getValueType().isFloatingPoint())
14146 // The instruction selector will select an FUCOM instruction instead of
14147 // FUCOMI, which writes the comparison result to FPSW instead of EFLAGS. Hence
14148 // build an SDNode sequence that transfers the result from FPSW into EFLAGS:
14149 // (X86sahf (trunc (srl (X86fp_stsw (trunc (X86cmp ...)), 8))))
14151 SDValue TruncFPSW = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, Cmp);
14152 SDValue FNStSW = DAG.getNode(X86ISD::FNSTSW16r, dl, MVT::i16, TruncFPSW);
14153 SDValue Srl = DAG.getNode(ISD::SRL, dl, MVT::i16, FNStSW,
14154 DAG.getConstant(8, MVT::i8));
14155 SDValue TruncSrl = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Srl);
14156 return DAG.getNode(X86ISD::SAHF, dl, MVT::i32, TruncSrl);
14159 static bool isAllOnes(SDValue V) {
14160 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
14161 return C && C->isAllOnesValue();
14164 /// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node
14165 /// if it's possible.
14166 SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC,
14167 SDLoc dl, SelectionDAG &DAG) const {
14168 SDValue Op0 = And.getOperand(0);
14169 SDValue Op1 = And.getOperand(1);
14170 if (Op0.getOpcode() == ISD::TRUNCATE)
14171 Op0 = Op0.getOperand(0);
14172 if (Op1.getOpcode() == ISD::TRUNCATE)
14173 Op1 = Op1.getOperand(0);
14176 if (Op1.getOpcode() == ISD::SHL)
14177 std::swap(Op0, Op1);
14178 if (Op0.getOpcode() == ISD::SHL) {
14179 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0)))
14180 if (And00C->getZExtValue() == 1) {
14181 // If we looked past a truncate, check that it's only truncating away
14183 unsigned BitWidth = Op0.getValueSizeInBits();
14184 unsigned AndBitWidth = And.getValueSizeInBits();
14185 if (BitWidth > AndBitWidth) {
14187 DAG.computeKnownBits(Op0, Zeros, Ones);
14188 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth)
14192 RHS = Op0.getOperand(1);
14194 } else if (Op1.getOpcode() == ISD::Constant) {
14195 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1);
14196 uint64_t AndRHSVal = AndRHS->getZExtValue();
14197 SDValue AndLHS = Op0;
14199 if (AndRHSVal == 1 && AndLHS.getOpcode() == ISD::SRL) {
14200 LHS = AndLHS.getOperand(0);
14201 RHS = AndLHS.getOperand(1);
14204 // Use BT if the immediate can't be encoded in a TEST instruction.
14205 if (!isUInt<32>(AndRHSVal) && isPowerOf2_64(AndRHSVal)) {
14207 RHS = DAG.getConstant(Log2_64_Ceil(AndRHSVal), LHS.getValueType());
14211 if (LHS.getNode()) {
14212 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT
14213 // instruction. Since the shift amount is in-range-or-undefined, we know
14214 // that doing a bittest on the i32 value is ok. We extend to i32 because
14215 // the encoding for the i16 version is larger than the i32 version.
14216 // Also promote i16 to i32 for performance / code size reason.
14217 if (LHS.getValueType() == MVT::i8 ||
14218 LHS.getValueType() == MVT::i16)
14219 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
14221 // If the operand types disagree, extend the shift amount to match. Since
14222 // BT ignores high bits (like shifts) we can use anyextend.
14223 if (LHS.getValueType() != RHS.getValueType())
14224 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
14226 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
14227 X86::CondCode Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
14228 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
14229 DAG.getConstant(Cond, MVT::i8), BT);
14235 /// \brief - Turns an ISD::CondCode into a value suitable for SSE floating point
14237 static int translateX86FSETCC(ISD::CondCode SetCCOpcode, SDValue &Op0,
14242 // SSE Condition code mapping:
14251 switch (SetCCOpcode) {
14252 default: llvm_unreachable("Unexpected SETCC condition");
14254 case ISD::SETEQ: SSECC = 0; break;
14256 case ISD::SETGT: Swap = true; // Fallthrough
14258 case ISD::SETOLT: SSECC = 1; break;
14260 case ISD::SETGE: Swap = true; // Fallthrough
14262 case ISD::SETOLE: SSECC = 2; break;
14263 case ISD::SETUO: SSECC = 3; break;
14265 case ISD::SETNE: SSECC = 4; break;
14266 case ISD::SETULE: Swap = true; // Fallthrough
14267 case ISD::SETUGE: SSECC = 5; break;
14268 case ISD::SETULT: Swap = true; // Fallthrough
14269 case ISD::SETUGT: SSECC = 6; break;
14270 case ISD::SETO: SSECC = 7; break;
14272 case ISD::SETONE: SSECC = 8; break;
14275 std::swap(Op0, Op1);
14280 // Lower256IntVSETCC - Break a VSETCC 256-bit integer VSETCC into two new 128
14281 // ones, and then concatenate the result back.
14282 static SDValue Lower256IntVSETCC(SDValue Op, SelectionDAG &DAG) {
14283 MVT VT = Op.getSimpleValueType();
14285 assert(VT.is256BitVector() && Op.getOpcode() == ISD::SETCC &&
14286 "Unsupported value type for operation");
14288 unsigned NumElems = VT.getVectorNumElements();
14290 SDValue CC = Op.getOperand(2);
14292 // Extract the LHS vectors
14293 SDValue LHS = Op.getOperand(0);
14294 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
14295 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
14297 // Extract the RHS vectors
14298 SDValue RHS = Op.getOperand(1);
14299 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
14300 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
14302 // Issue the operation on the smaller types and concatenate the result back
14303 MVT EltVT = VT.getVectorElementType();
14304 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
14305 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
14306 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1, CC),
14307 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC));
14310 static SDValue LowerIntVSETCC_AVX512(SDValue Op, SelectionDAG &DAG,
14311 const X86Subtarget *Subtarget) {
14312 SDValue Op0 = Op.getOperand(0);
14313 SDValue Op1 = Op.getOperand(1);
14314 SDValue CC = Op.getOperand(2);
14315 MVT VT = Op.getSimpleValueType();
14318 assert(Op0.getValueType().getVectorElementType().getSizeInBits() >= 8 &&
14319 Op.getValueType().getScalarType() == MVT::i1 &&
14320 "Cannot set masked compare for this operation");
14322 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
14324 bool Unsigned = false;
14327 switch (SetCCOpcode) {
14328 default: llvm_unreachable("Unexpected SETCC condition");
14329 case ISD::SETNE: SSECC = 4; break;
14330 case ISD::SETEQ: Opc = X86ISD::PCMPEQM; break;
14331 case ISD::SETUGT: SSECC = 6; Unsigned = true; break;
14332 case ISD::SETLT: Swap = true; //fall-through
14333 case ISD::SETGT: Opc = X86ISD::PCMPGTM; break;
14334 case ISD::SETULT: SSECC = 1; Unsigned = true; break;
14335 case ISD::SETUGE: SSECC = 5; Unsigned = true; break; //NLT
14336 case ISD::SETGE: Swap = true; SSECC = 2; break; // LE + swap
14337 case ISD::SETULE: Unsigned = true; //fall-through
14338 case ISD::SETLE: SSECC = 2; break;
14342 std::swap(Op0, Op1);
14344 return DAG.getNode(Opc, dl, VT, Op0, Op1);
14345 Opc = Unsigned ? X86ISD::CMPMU: X86ISD::CMPM;
14346 return DAG.getNode(Opc, dl, VT, Op0, Op1,
14347 DAG.getConstant(SSECC, MVT::i8));
14350 /// \brief Try to turn a VSETULT into a VSETULE by modifying its second
14351 /// operand \p Op1. If non-trivial (for example because it's not constant)
14352 /// return an empty value.
14353 static SDValue ChangeVSETULTtoVSETULE(SDLoc dl, SDValue Op1, SelectionDAG &DAG)
14355 BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(Op1.getNode());
14359 MVT VT = Op1.getSimpleValueType();
14360 MVT EVT = VT.getVectorElementType();
14361 unsigned n = VT.getVectorNumElements();
14362 SmallVector<SDValue, 8> ULTOp1;
14364 for (unsigned i = 0; i < n; ++i) {
14365 ConstantSDNode *Elt = dyn_cast<ConstantSDNode>(BV->getOperand(i));
14366 if (!Elt || Elt->isOpaque() || Elt->getValueType(0) != EVT)
14369 // Avoid underflow.
14370 APInt Val = Elt->getAPIntValue();
14374 ULTOp1.push_back(DAG.getConstant(Val - 1, EVT));
14377 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, ULTOp1);
14380 static SDValue LowerVSETCC(SDValue Op, const X86Subtarget *Subtarget,
14381 SelectionDAG &DAG) {
14382 SDValue Op0 = Op.getOperand(0);
14383 SDValue Op1 = Op.getOperand(1);
14384 SDValue CC = Op.getOperand(2);
14385 MVT VT = Op.getSimpleValueType();
14386 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
14387 bool isFP = Op.getOperand(1).getSimpleValueType().isFloatingPoint();
14392 MVT EltVT = Op0.getSimpleValueType().getVectorElementType();
14393 assert(EltVT == MVT::f32 || EltVT == MVT::f64);
14396 unsigned SSECC = translateX86FSETCC(SetCCOpcode, Op0, Op1);
14397 unsigned Opc = X86ISD::CMPP;
14398 if (Subtarget->hasAVX512() && VT.getVectorElementType() == MVT::i1) {
14399 assert(VT.getVectorNumElements() <= 16);
14400 Opc = X86ISD::CMPM;
14402 // In the two special cases we can't handle, emit two comparisons.
14405 unsigned CombineOpc;
14406 if (SetCCOpcode == ISD::SETUEQ) {
14407 CC0 = 3; CC1 = 0; CombineOpc = ISD::OR;
14409 assert(SetCCOpcode == ISD::SETONE);
14410 CC0 = 7; CC1 = 4; CombineOpc = ISD::AND;
14413 SDValue Cmp0 = DAG.getNode(Opc, dl, VT, Op0, Op1,
14414 DAG.getConstant(CC0, MVT::i8));
14415 SDValue Cmp1 = DAG.getNode(Opc, dl, VT, Op0, Op1,
14416 DAG.getConstant(CC1, MVT::i8));
14417 return DAG.getNode(CombineOpc, dl, VT, Cmp0, Cmp1);
14419 // Handle all other FP comparisons here.
14420 return DAG.getNode(Opc, dl, VT, Op0, Op1,
14421 DAG.getConstant(SSECC, MVT::i8));
14424 // Break 256-bit integer vector compare into smaller ones.
14425 if (VT.is256BitVector() && !Subtarget->hasInt256())
14426 return Lower256IntVSETCC(Op, DAG);
14428 bool MaskResult = (VT.getVectorElementType() == MVT::i1);
14429 EVT OpVT = Op1.getValueType();
14430 if (Subtarget->hasAVX512()) {
14431 if (Op1.getValueType().is512BitVector() ||
14432 (Subtarget->hasBWI() && Subtarget->hasVLX()) ||
14433 (MaskResult && OpVT.getVectorElementType().getSizeInBits() >= 32))
14434 return LowerIntVSETCC_AVX512(Op, DAG, Subtarget);
14436 // In AVX-512 architecture setcc returns mask with i1 elements,
14437 // But there is no compare instruction for i8 and i16 elements in KNL.
14438 // We are not talking about 512-bit operands in this case, these
14439 // types are illegal.
14441 (OpVT.getVectorElementType().getSizeInBits() < 32 &&
14442 OpVT.getVectorElementType().getSizeInBits() >= 8))
14443 return DAG.getNode(ISD::TRUNCATE, dl, VT,
14444 DAG.getNode(ISD::SETCC, dl, OpVT, Op0, Op1, CC));
14447 // We are handling one of the integer comparisons here. Since SSE only has
14448 // GT and EQ comparisons for integer, swapping operands and multiple
14449 // operations may be required for some comparisons.
14451 bool Swap = false, Invert = false, FlipSigns = false, MinMax = false;
14452 bool Subus = false;
14454 switch (SetCCOpcode) {
14455 default: llvm_unreachable("Unexpected SETCC condition");
14456 case ISD::SETNE: Invert = true;
14457 case ISD::SETEQ: Opc = X86ISD::PCMPEQ; break;
14458 case ISD::SETLT: Swap = true;
14459 case ISD::SETGT: Opc = X86ISD::PCMPGT; break;
14460 case ISD::SETGE: Swap = true;
14461 case ISD::SETLE: Opc = X86ISD::PCMPGT;
14462 Invert = true; break;
14463 case ISD::SETULT: Swap = true;
14464 case ISD::SETUGT: Opc = X86ISD::PCMPGT;
14465 FlipSigns = true; break;
14466 case ISD::SETUGE: Swap = true;
14467 case ISD::SETULE: Opc = X86ISD::PCMPGT;
14468 FlipSigns = true; Invert = true; break;
14471 // Special case: Use min/max operations for SETULE/SETUGE
14472 MVT VET = VT.getVectorElementType();
14474 (Subtarget->hasSSE41() && (VET >= MVT::i8 && VET <= MVT::i32))
14475 || (Subtarget->hasSSE2() && (VET == MVT::i8));
14478 switch (SetCCOpcode) {
14480 case ISD::SETULE: Opc = X86ISD::UMIN; MinMax = true; break;
14481 case ISD::SETUGE: Opc = X86ISD::UMAX; MinMax = true; break;
14484 if (MinMax) { Swap = false; Invert = false; FlipSigns = false; }
14487 bool hasSubus = Subtarget->hasSSE2() && (VET == MVT::i8 || VET == MVT::i16);
14488 if (!MinMax && hasSubus) {
14489 // As another special case, use PSUBUS[BW] when it's profitable. E.g. for
14491 // t = psubus Op0, Op1
14492 // pcmpeq t, <0..0>
14493 switch (SetCCOpcode) {
14495 case ISD::SETULT: {
14496 // If the comparison is against a constant we can turn this into a
14497 // setule. With psubus, setule does not require a swap. This is
14498 // beneficial because the constant in the register is no longer
14499 // destructed as the destination so it can be hoisted out of a loop.
14500 // Only do this pre-AVX since vpcmp* is no longer destructive.
14501 if (Subtarget->hasAVX())
14503 SDValue ULEOp1 = ChangeVSETULTtoVSETULE(dl, Op1, DAG);
14504 if (ULEOp1.getNode()) {
14506 Subus = true; Invert = false; Swap = false;
14510 // Psubus is better than flip-sign because it requires no inversion.
14511 case ISD::SETUGE: Subus = true; Invert = false; Swap = true; break;
14512 case ISD::SETULE: Subus = true; Invert = false; Swap = false; break;
14516 Opc = X86ISD::SUBUS;
14522 std::swap(Op0, Op1);
14524 // Check that the operation in question is available (most are plain SSE2,
14525 // but PCMPGTQ and PCMPEQQ have different requirements).
14526 if (VT == MVT::v2i64) {
14527 if (Opc == X86ISD::PCMPGT && !Subtarget->hasSSE42()) {
14528 assert(Subtarget->hasSSE2() && "Don't know how to lower!");
14530 // First cast everything to the right type.
14531 Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0);
14532 Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1);
14534 // Since SSE has no unsigned integer comparisons, we need to flip the sign
14535 // bits of the inputs before performing those operations. The lower
14536 // compare is always unsigned.
14539 SB = DAG.getConstant(0x80000000U, MVT::v4i32);
14541 SDValue Sign = DAG.getConstant(0x80000000U, MVT::i32);
14542 SDValue Zero = DAG.getConstant(0x00000000U, MVT::i32);
14543 SB = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
14544 Sign, Zero, Sign, Zero);
14546 Op0 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op0, SB);
14547 Op1 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op1, SB);
14549 // Emulate PCMPGTQ with (hi1 > hi2) | ((hi1 == hi2) & (lo1 > lo2))
14550 SDValue GT = DAG.getNode(X86ISD::PCMPGT, dl, MVT::v4i32, Op0, Op1);
14551 SDValue EQ = DAG.getNode(X86ISD::PCMPEQ, dl, MVT::v4i32, Op0, Op1);
14553 // Create masks for only the low parts/high parts of the 64 bit integers.
14554 static const int MaskHi[] = { 1, 1, 3, 3 };
14555 static const int MaskLo[] = { 0, 0, 2, 2 };
14556 SDValue EQHi = DAG.getVectorShuffle(MVT::v4i32, dl, EQ, EQ, MaskHi);
14557 SDValue GTLo = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskLo);
14558 SDValue GTHi = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskHi);
14560 SDValue Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, EQHi, GTLo);
14561 Result = DAG.getNode(ISD::OR, dl, MVT::v4i32, Result, GTHi);
14564 Result = DAG.getNOT(dl, Result, MVT::v4i32);
14566 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
14569 if (Opc == X86ISD::PCMPEQ && !Subtarget->hasSSE41()) {
14570 // If pcmpeqq is missing but pcmpeqd is available synthesize pcmpeqq with
14571 // pcmpeqd + pshufd + pand.
14572 assert(Subtarget->hasSSE2() && !FlipSigns && "Don't know how to lower!");
14574 // First cast everything to the right type.
14575 Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0);
14576 Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1);
14579 SDValue Result = DAG.getNode(Opc, dl, MVT::v4i32, Op0, Op1);
14581 // Make sure the lower and upper halves are both all-ones.
14582 static const int Mask[] = { 1, 0, 3, 2 };
14583 SDValue Shuf = DAG.getVectorShuffle(MVT::v4i32, dl, Result, Result, Mask);
14584 Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, Result, Shuf);
14587 Result = DAG.getNOT(dl, Result, MVT::v4i32);
14589 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
14593 // Since SSE has no unsigned integer comparisons, we need to flip the sign
14594 // bits of the inputs before performing those operations.
14596 EVT EltVT = VT.getVectorElementType();
14597 SDValue SB = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()), VT);
14598 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SB);
14599 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SB);
14602 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
14604 // If the logical-not of the result is required, perform that now.
14606 Result = DAG.getNOT(dl, Result, VT);
14609 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Op0, Result);
14612 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Result,
14613 getZeroVector(VT, Subtarget, DAG, dl));
14618 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
14620 MVT VT = Op.getSimpleValueType();
14622 if (VT.isVector()) return LowerVSETCC(Op, Subtarget, DAG);
14624 assert(((!Subtarget->hasAVX512() && VT == MVT::i8) || (VT == MVT::i1))
14625 && "SetCC type must be 8-bit or 1-bit integer");
14626 SDValue Op0 = Op.getOperand(0);
14627 SDValue Op1 = Op.getOperand(1);
14629 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
14631 // Optimize to BT if possible.
14632 // Lower (X & (1 << N)) == 0 to BT(X, N).
14633 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
14634 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
14635 if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() &&
14636 Op1.getOpcode() == ISD::Constant &&
14637 cast<ConstantSDNode>(Op1)->isNullValue() &&
14638 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
14639 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG);
14640 if (NewSetCC.getNode())
14644 // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of
14646 if (Op1.getOpcode() == ISD::Constant &&
14647 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 ||
14648 cast<ConstantSDNode>(Op1)->isNullValue()) &&
14649 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
14651 // If the input is a setcc, then reuse the input setcc or use a new one with
14652 // the inverted condition.
14653 if (Op0.getOpcode() == X86ISD::SETCC) {
14654 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0);
14655 bool Invert = (CC == ISD::SETNE) ^
14656 cast<ConstantSDNode>(Op1)->isNullValue();
14660 CCode = X86::GetOppositeBranchCondition(CCode);
14661 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
14662 DAG.getConstant(CCode, MVT::i8),
14663 Op0.getOperand(1));
14665 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
14669 if ((Op0.getValueType() == MVT::i1) && (Op1.getOpcode() == ISD::Constant) &&
14670 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1) &&
14671 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
14673 ISD::CondCode NewCC = ISD::getSetCCInverse(CC, true);
14674 return DAG.getSetCC(dl, VT, Op0, DAG.getConstant(0, MVT::i1), NewCC);
14677 bool isFP = Op1.getSimpleValueType().isFloatingPoint();
14678 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG);
14679 if (X86CC == X86::COND_INVALID)
14682 SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, dl, DAG);
14683 EFLAGS = ConvertCmpIfNecessary(EFLAGS, DAG);
14684 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
14685 DAG.getConstant(X86CC, MVT::i8), EFLAGS);
14687 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
14691 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
14692 static bool isX86LogicalCmp(SDValue Op) {
14693 unsigned Opc = Op.getNode()->getOpcode();
14694 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI ||
14695 Opc == X86ISD::SAHF)
14697 if (Op.getResNo() == 1 &&
14698 (Opc == X86ISD::ADD ||
14699 Opc == X86ISD::SUB ||
14700 Opc == X86ISD::ADC ||
14701 Opc == X86ISD::SBB ||
14702 Opc == X86ISD::SMUL ||
14703 Opc == X86ISD::UMUL ||
14704 Opc == X86ISD::INC ||
14705 Opc == X86ISD::DEC ||
14706 Opc == X86ISD::OR ||
14707 Opc == X86ISD::XOR ||
14708 Opc == X86ISD::AND))
14711 if (Op.getResNo() == 2 && Opc == X86ISD::UMUL)
14717 static bool isTruncWithZeroHighBitsInput(SDValue V, SelectionDAG &DAG) {
14718 if (V.getOpcode() != ISD::TRUNCATE)
14721 SDValue VOp0 = V.getOperand(0);
14722 unsigned InBits = VOp0.getValueSizeInBits();
14723 unsigned Bits = V.getValueSizeInBits();
14724 return DAG.MaskedValueIsZero(VOp0, APInt::getHighBitsSet(InBits,InBits-Bits));
14727 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
14728 bool addTest = true;
14729 SDValue Cond = Op.getOperand(0);
14730 SDValue Op1 = Op.getOperand(1);
14731 SDValue Op2 = Op.getOperand(2);
14733 EVT VT = Op1.getValueType();
14736 // Lower fp selects into a CMP/AND/ANDN/OR sequence when the necessary SSE ops
14737 // are available. Otherwise fp cmovs get lowered into a less efficient branch
14738 // sequence later on.
14739 if (Cond.getOpcode() == ISD::SETCC &&
14740 ((Subtarget->hasSSE2() && (VT == MVT::f32 || VT == MVT::f64)) ||
14741 (Subtarget->hasSSE1() && VT == MVT::f32)) &&
14742 VT == Cond.getOperand(0).getValueType() && Cond->hasOneUse()) {
14743 SDValue CondOp0 = Cond.getOperand(0), CondOp1 = Cond.getOperand(1);
14744 int SSECC = translateX86FSETCC(
14745 cast<CondCodeSDNode>(Cond.getOperand(2))->get(), CondOp0, CondOp1);
14748 if (Subtarget->hasAVX512()) {
14749 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CondOp0, CondOp1,
14750 DAG.getConstant(SSECC, MVT::i8));
14751 return DAG.getNode(X86ISD::SELECT, DL, VT, Cmp, Op1, Op2);
14753 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, VT, CondOp0, CondOp1,
14754 DAG.getConstant(SSECC, MVT::i8));
14755 SDValue AndN = DAG.getNode(X86ISD::FANDN, DL, VT, Cmp, Op2);
14756 SDValue And = DAG.getNode(X86ISD::FAND, DL, VT, Cmp, Op1);
14757 return DAG.getNode(X86ISD::FOR, DL, VT, AndN, And);
14761 if (Cond.getOpcode() == ISD::SETCC) {
14762 SDValue NewCond = LowerSETCC(Cond, DAG);
14763 if (NewCond.getNode())
14767 // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y
14768 // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y
14769 // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y
14770 // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y
14771 if (Cond.getOpcode() == X86ISD::SETCC &&
14772 Cond.getOperand(1).getOpcode() == X86ISD::CMP &&
14773 isZero(Cond.getOperand(1).getOperand(1))) {
14774 SDValue Cmp = Cond.getOperand(1);
14776 unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue();
14778 if ((isAllOnes(Op1) || isAllOnes(Op2)) &&
14779 (CondCode == X86::COND_E || CondCode == X86::COND_NE)) {
14780 SDValue Y = isAllOnes(Op2) ? Op1 : Op2;
14782 SDValue CmpOp0 = Cmp.getOperand(0);
14783 // Apply further optimizations for special cases
14784 // (select (x != 0), -1, 0) -> neg & sbb
14785 // (select (x == 0), 0, -1) -> neg & sbb
14786 if (ConstantSDNode *YC = dyn_cast<ConstantSDNode>(Y))
14787 if (YC->isNullValue() &&
14788 (isAllOnes(Op1) == (CondCode == X86::COND_NE))) {
14789 SDVTList VTs = DAG.getVTList(CmpOp0.getValueType(), MVT::i32);
14790 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, VTs,
14791 DAG.getConstant(0, CmpOp0.getValueType()),
14793 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
14794 DAG.getConstant(X86::COND_B, MVT::i8),
14795 SDValue(Neg.getNode(), 1));
14799 Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32,
14800 CmpOp0, DAG.getConstant(1, CmpOp0.getValueType()));
14801 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
14803 SDValue Res = // Res = 0 or -1.
14804 DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
14805 DAG.getConstant(X86::COND_B, MVT::i8), Cmp);
14807 if (isAllOnes(Op1) != (CondCode == X86::COND_E))
14808 Res = DAG.getNOT(DL, Res, Res.getValueType());
14810 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2);
14811 if (!N2C || !N2C->isNullValue())
14812 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y);
14817 // Look past (and (setcc_carry (cmp ...)), 1).
14818 if (Cond.getOpcode() == ISD::AND &&
14819 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
14820 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
14821 if (C && C->getAPIntValue() == 1)
14822 Cond = Cond.getOperand(0);
14825 // If condition flag is set by a X86ISD::CMP, then use it as the condition
14826 // setting operand in place of the X86ISD::SETCC.
14827 unsigned CondOpcode = Cond.getOpcode();
14828 if (CondOpcode == X86ISD::SETCC ||
14829 CondOpcode == X86ISD::SETCC_CARRY) {
14830 CC = Cond.getOperand(0);
14832 SDValue Cmp = Cond.getOperand(1);
14833 unsigned Opc = Cmp.getOpcode();
14834 MVT VT = Op.getSimpleValueType();
14836 bool IllegalFPCMov = false;
14837 if (VT.isFloatingPoint() && !VT.isVector() &&
14838 !isScalarFPTypeInSSEReg(VT)) // FPStack?
14839 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
14841 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
14842 Opc == X86ISD::BT) { // FIXME
14846 } else if (CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
14847 CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
14848 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
14849 Cond.getOperand(0).getValueType() != MVT::i8)) {
14850 SDValue LHS = Cond.getOperand(0);
14851 SDValue RHS = Cond.getOperand(1);
14852 unsigned X86Opcode;
14855 switch (CondOpcode) {
14856 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
14857 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
14858 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
14859 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
14860 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
14861 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
14862 default: llvm_unreachable("unexpected overflowing operator");
14864 if (CondOpcode == ISD::UMULO)
14865 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
14868 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
14870 SDValue X86Op = DAG.getNode(X86Opcode, DL, VTs, LHS, RHS);
14872 if (CondOpcode == ISD::UMULO)
14873 Cond = X86Op.getValue(2);
14875 Cond = X86Op.getValue(1);
14877 CC = DAG.getConstant(X86Cond, MVT::i8);
14882 // Look pass the truncate if the high bits are known zero.
14883 if (isTruncWithZeroHighBitsInput(Cond, DAG))
14884 Cond = Cond.getOperand(0);
14886 // We know the result of AND is compared against zero. Try to match
14888 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
14889 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG);
14890 if (NewSetCC.getNode()) {
14891 CC = NewSetCC.getOperand(0);
14892 Cond = NewSetCC.getOperand(1);
14899 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
14900 Cond = EmitTest(Cond, X86::COND_NE, DL, DAG);
14903 // a < b ? -1 : 0 -> RES = ~setcc_carry
14904 // a < b ? 0 : -1 -> RES = setcc_carry
14905 // a >= b ? -1 : 0 -> RES = setcc_carry
14906 // a >= b ? 0 : -1 -> RES = ~setcc_carry
14907 if (Cond.getOpcode() == X86ISD::SUB) {
14908 Cond = ConvertCmpIfNecessary(Cond, DAG);
14909 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue();
14911 if ((CondCode == X86::COND_AE || CondCode == X86::COND_B) &&
14912 (isAllOnes(Op1) || isAllOnes(Op2)) && (isZero(Op1) || isZero(Op2))) {
14913 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
14914 DAG.getConstant(X86::COND_B, MVT::i8), Cond);
14915 if (isAllOnes(Op1) != (CondCode == X86::COND_B))
14916 return DAG.getNOT(DL, Res, Res.getValueType());
14921 // X86 doesn't have an i8 cmov. If both operands are the result of a truncate
14922 // widen the cmov and push the truncate through. This avoids introducing a new
14923 // branch during isel and doesn't add any extensions.
14924 if (Op.getValueType() == MVT::i8 &&
14925 Op1.getOpcode() == ISD::TRUNCATE && Op2.getOpcode() == ISD::TRUNCATE) {
14926 SDValue T1 = Op1.getOperand(0), T2 = Op2.getOperand(0);
14927 if (T1.getValueType() == T2.getValueType() &&
14928 // Blacklist CopyFromReg to avoid partial register stalls.
14929 T1.getOpcode() != ISD::CopyFromReg && T2.getOpcode()!=ISD::CopyFromReg){
14930 SDVTList VTs = DAG.getVTList(T1.getValueType(), MVT::Glue);
14931 SDValue Cmov = DAG.getNode(X86ISD::CMOV, DL, VTs, T2, T1, CC, Cond);
14932 return DAG.getNode(ISD::TRUNCATE, DL, Op.getValueType(), Cmov);
14936 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
14937 // condition is true.
14938 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
14939 SDValue Ops[] = { Op2, Op1, CC, Cond };
14940 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops);
14943 static SDValue LowerSIGN_EXTEND_AVX512(SDValue Op, SelectionDAG &DAG) {
14944 MVT VT = Op->getSimpleValueType(0);
14945 SDValue In = Op->getOperand(0);
14946 MVT InVT = In.getSimpleValueType();
14949 unsigned int NumElts = VT.getVectorNumElements();
14950 if (NumElts != 8 && NumElts != 16)
14953 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1)
14954 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
14956 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14957 assert (InVT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
14959 MVT ExtVT = (NumElts == 8) ? MVT::v8i64 : MVT::v16i32;
14960 Constant *C = ConstantInt::get(*DAG.getContext(),
14961 APInt::getAllOnesValue(ExtVT.getScalarType().getSizeInBits()));
14963 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
14964 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
14965 SDValue Ld = DAG.getLoad(ExtVT.getScalarType(), dl, DAG.getEntryNode(), CP,
14966 MachinePointerInfo::getConstantPool(),
14967 false, false, false, Alignment);
14968 SDValue Brcst = DAG.getNode(X86ISD::VBROADCASTM, dl, ExtVT, In, Ld);
14969 if (VT.is512BitVector())
14971 return DAG.getNode(X86ISD::VTRUNC, dl, VT, Brcst);
14974 static SDValue LowerSIGN_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
14975 SelectionDAG &DAG) {
14976 MVT VT = Op->getSimpleValueType(0);
14977 SDValue In = Op->getOperand(0);
14978 MVT InVT = In.getSimpleValueType();
14981 if (VT.is512BitVector() || InVT.getVectorElementType() == MVT::i1)
14982 return LowerSIGN_EXTEND_AVX512(Op, DAG);
14984 if ((VT != MVT::v4i64 || InVT != MVT::v4i32) &&
14985 (VT != MVT::v8i32 || InVT != MVT::v8i16) &&
14986 (VT != MVT::v16i16 || InVT != MVT::v16i8))
14989 if (Subtarget->hasInt256())
14990 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
14992 // Optimize vectors in AVX mode
14993 // Sign extend v8i16 to v8i32 and
14996 // Divide input vector into two parts
14997 // for v4i32 the shuffle mask will be { 0, 1, -1, -1} {2, 3, -1, -1}
14998 // use vpmovsx instruction to extend v4i32 -> v2i64; v8i16 -> v4i32
14999 // concat the vectors to original VT
15001 unsigned NumElems = InVT.getVectorNumElements();
15002 SDValue Undef = DAG.getUNDEF(InVT);
15004 SmallVector<int,8> ShufMask1(NumElems, -1);
15005 for (unsigned i = 0; i != NumElems/2; ++i)
15008 SDValue OpLo = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask1[0]);
15010 SmallVector<int,8> ShufMask2(NumElems, -1);
15011 for (unsigned i = 0; i != NumElems/2; ++i)
15012 ShufMask2[i] = i + NumElems/2;
15014 SDValue OpHi = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask2[0]);
15016 MVT HalfVT = MVT::getVectorVT(VT.getScalarType(),
15017 VT.getVectorNumElements()/2);
15019 OpLo = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpLo);
15020 OpHi = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpHi);
15022 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
15025 // Lower vector extended loads using a shuffle. If SSSE3 is not available we
15026 // may emit an illegal shuffle but the expansion is still better than scalar
15027 // code. We generate X86ISD::VSEXT for SEXTLOADs if it's available, otherwise
15028 // we'll emit a shuffle and a arithmetic shift.
15029 // TODO: It is possible to support ZExt by zeroing the undef values during
15030 // the shuffle phase or after the shuffle.
15031 static SDValue LowerExtendedLoad(SDValue Op, const X86Subtarget *Subtarget,
15032 SelectionDAG &DAG) {
15033 MVT RegVT = Op.getSimpleValueType();
15034 assert(RegVT.isVector() && "We only custom lower vector sext loads.");
15035 assert(RegVT.isInteger() &&
15036 "We only custom lower integer vector sext loads.");
15038 // Nothing useful we can do without SSE2 shuffles.
15039 assert(Subtarget->hasSSE2() && "We only custom lower sext loads with SSE2.");
15041 LoadSDNode *Ld = cast<LoadSDNode>(Op.getNode());
15043 EVT MemVT = Ld->getMemoryVT();
15044 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
15045 unsigned RegSz = RegVT.getSizeInBits();
15047 ISD::LoadExtType Ext = Ld->getExtensionType();
15049 assert((Ext == ISD::EXTLOAD || Ext == ISD::SEXTLOAD)
15050 && "Only anyext and sext are currently implemented.");
15051 assert(MemVT != RegVT && "Cannot extend to the same type");
15052 assert(MemVT.isVector() && "Must load a vector from memory");
15054 unsigned NumElems = RegVT.getVectorNumElements();
15055 unsigned MemSz = MemVT.getSizeInBits();
15056 assert(RegSz > MemSz && "Register size must be greater than the mem size");
15058 if (Ext == ISD::SEXTLOAD && RegSz == 256 && !Subtarget->hasInt256()) {
15059 // The only way in which we have a legal 256-bit vector result but not the
15060 // integer 256-bit operations needed to directly lower a sextload is if we
15061 // have AVX1 but not AVX2. In that case, we can always emit a sextload to
15062 // a 128-bit vector and a normal sign_extend to 256-bits that should get
15063 // correctly legalized. We do this late to allow the canonical form of
15064 // sextload to persist throughout the rest of the DAG combiner -- it wants
15065 // to fold together any extensions it can, and so will fuse a sign_extend
15066 // of an sextload into a sextload targeting a wider value.
15068 if (MemSz == 128) {
15069 // Just switch this to a normal load.
15070 assert(TLI.isTypeLegal(MemVT) && "If the memory type is a 128-bit type, "
15071 "it must be a legal 128-bit vector "
15073 Load = DAG.getLoad(MemVT, dl, Ld->getChain(), Ld->getBasePtr(),
15074 Ld->getPointerInfo(), Ld->isVolatile(), Ld->isNonTemporal(),
15075 Ld->isInvariant(), Ld->getAlignment());
15077 assert(MemSz < 128 &&
15078 "Can't extend a type wider than 128 bits to a 256 bit vector!");
15079 // Do an sext load to a 128-bit vector type. We want to use the same
15080 // number of elements, but elements half as wide. This will end up being
15081 // recursively lowered by this routine, but will succeed as we definitely
15082 // have all the necessary features if we're using AVX1.
15084 EVT::getIntegerVT(*DAG.getContext(), RegVT.getScalarSizeInBits() / 2);
15085 EVT HalfVecVT = EVT::getVectorVT(*DAG.getContext(), HalfEltVT, NumElems);
15087 DAG.getExtLoad(Ext, dl, HalfVecVT, Ld->getChain(), Ld->getBasePtr(),
15088 Ld->getPointerInfo(), MemVT, Ld->isVolatile(),
15089 Ld->isNonTemporal(), Ld->isInvariant(),
15090 Ld->getAlignment());
15093 // Replace chain users with the new chain.
15094 assert(Load->getNumValues() == 2 && "Loads must carry a chain!");
15095 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), Load.getValue(1));
15097 // Finally, do a normal sign-extend to the desired register.
15098 return DAG.getSExtOrTrunc(Load, dl, RegVT);
15101 // All sizes must be a power of two.
15102 assert(isPowerOf2_32(RegSz * MemSz * NumElems) &&
15103 "Non-power-of-two elements are not custom lowered!");
15105 // Attempt to load the original value using scalar loads.
15106 // Find the largest scalar type that divides the total loaded size.
15107 MVT SclrLoadTy = MVT::i8;
15108 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
15109 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
15110 MVT Tp = (MVT::SimpleValueType)tp;
15111 if (TLI.isTypeLegal(Tp) && ((MemSz % Tp.getSizeInBits()) == 0)) {
15116 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
15117 if (TLI.isTypeLegal(MVT::f64) && SclrLoadTy.getSizeInBits() < 64 &&
15119 SclrLoadTy = MVT::f64;
15121 // Calculate the number of scalar loads that we need to perform
15122 // in order to load our vector from memory.
15123 unsigned NumLoads = MemSz / SclrLoadTy.getSizeInBits();
15125 assert((Ext != ISD::SEXTLOAD || NumLoads == 1) &&
15126 "Can only lower sext loads with a single scalar load!");
15128 unsigned loadRegZize = RegSz;
15129 if (Ext == ISD::SEXTLOAD && RegSz == 256)
15132 // Represent our vector as a sequence of elements which are the
15133 // largest scalar that we can load.
15134 EVT LoadUnitVecVT = EVT::getVectorVT(
15135 *DAG.getContext(), SclrLoadTy, loadRegZize / SclrLoadTy.getSizeInBits());
15137 // Represent the data using the same element type that is stored in
15138 // memory. In practice, we ''widen'' MemVT.
15140 EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
15141 loadRegZize / MemVT.getScalarType().getSizeInBits());
15143 assert(WideVecVT.getSizeInBits() == LoadUnitVecVT.getSizeInBits() &&
15144 "Invalid vector type");
15146 // We can't shuffle using an illegal type.
15147 assert(TLI.isTypeLegal(WideVecVT) &&
15148 "We only lower types that form legal widened vector types");
15150 SmallVector<SDValue, 8> Chains;
15151 SDValue Ptr = Ld->getBasePtr();
15152 SDValue Increment =
15153 DAG.getConstant(SclrLoadTy.getSizeInBits() / 8, TLI.getPointerTy());
15154 SDValue Res = DAG.getUNDEF(LoadUnitVecVT);
15156 for (unsigned i = 0; i < NumLoads; ++i) {
15157 // Perform a single load.
15158 SDValue ScalarLoad =
15159 DAG.getLoad(SclrLoadTy, dl, Ld->getChain(), Ptr, Ld->getPointerInfo(),
15160 Ld->isVolatile(), Ld->isNonTemporal(), Ld->isInvariant(),
15161 Ld->getAlignment());
15162 Chains.push_back(ScalarLoad.getValue(1));
15163 // Create the first element type using SCALAR_TO_VECTOR in order to avoid
15164 // another round of DAGCombining.
15166 Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LoadUnitVecVT, ScalarLoad);
15168 Res = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, LoadUnitVecVT, Res,
15169 ScalarLoad, DAG.getIntPtrConstant(i));
15171 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
15174 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
15176 // Bitcast the loaded value to a vector of the original element type, in
15177 // the size of the target vector type.
15178 SDValue SlicedVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, Res);
15179 unsigned SizeRatio = RegSz / MemSz;
15181 if (Ext == ISD::SEXTLOAD) {
15182 // If we have SSE4.1, we can directly emit a VSEXT node.
15183 if (Subtarget->hasSSE41()) {
15184 SDValue Sext = DAG.getNode(X86ISD::VSEXT, dl, RegVT, SlicedVec);
15185 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
15189 // Otherwise we'll shuffle the small elements in the high bits of the
15190 // larger type and perform an arithmetic shift. If the shift is not legal
15191 // it's better to scalarize.
15192 assert(TLI.isOperationLegalOrCustom(ISD::SRA, RegVT) &&
15193 "We can't implement a sext load without an arithmetic right shift!");
15195 // Redistribute the loaded elements into the different locations.
15196 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
15197 for (unsigned i = 0; i != NumElems; ++i)
15198 ShuffleVec[i * SizeRatio + SizeRatio - 1] = i;
15200 SDValue Shuff = DAG.getVectorShuffle(
15201 WideVecVT, dl, SlicedVec, DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
15203 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
15205 // Build the arithmetic shift.
15206 unsigned Amt = RegVT.getVectorElementType().getSizeInBits() -
15207 MemVT.getVectorElementType().getSizeInBits();
15209 DAG.getNode(ISD::SRA, dl, RegVT, Shuff, DAG.getConstant(Amt, RegVT));
15211 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
15215 // Redistribute the loaded elements into the different locations.
15216 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
15217 for (unsigned i = 0; i != NumElems; ++i)
15218 ShuffleVec[i * SizeRatio] = i;
15220 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec,
15221 DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
15223 // Bitcast to the requested type.
15224 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
15225 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
15229 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
15230 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
15231 // from the AND / OR.
15232 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
15233 Opc = Op.getOpcode();
15234 if (Opc != ISD::OR && Opc != ISD::AND)
15236 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
15237 Op.getOperand(0).hasOneUse() &&
15238 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
15239 Op.getOperand(1).hasOneUse());
15242 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
15243 // 1 and that the SETCC node has a single use.
15244 static bool isXor1OfSetCC(SDValue Op) {
15245 if (Op.getOpcode() != ISD::XOR)
15247 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
15248 if (N1C && N1C->getAPIntValue() == 1) {
15249 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
15250 Op.getOperand(0).hasOneUse();
15255 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
15256 bool addTest = true;
15257 SDValue Chain = Op.getOperand(0);
15258 SDValue Cond = Op.getOperand(1);
15259 SDValue Dest = Op.getOperand(2);
15262 bool Inverted = false;
15264 if (Cond.getOpcode() == ISD::SETCC) {
15265 // Check for setcc([su]{add,sub,mul}o == 0).
15266 if (cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETEQ &&
15267 isa<ConstantSDNode>(Cond.getOperand(1)) &&
15268 cast<ConstantSDNode>(Cond.getOperand(1))->isNullValue() &&
15269 Cond.getOperand(0).getResNo() == 1 &&
15270 (Cond.getOperand(0).getOpcode() == ISD::SADDO ||
15271 Cond.getOperand(0).getOpcode() == ISD::UADDO ||
15272 Cond.getOperand(0).getOpcode() == ISD::SSUBO ||
15273 Cond.getOperand(0).getOpcode() == ISD::USUBO ||
15274 Cond.getOperand(0).getOpcode() == ISD::SMULO ||
15275 Cond.getOperand(0).getOpcode() == ISD::UMULO)) {
15277 Cond = Cond.getOperand(0);
15279 SDValue NewCond = LowerSETCC(Cond, DAG);
15280 if (NewCond.getNode())
15285 // FIXME: LowerXALUO doesn't handle these!!
15286 else if (Cond.getOpcode() == X86ISD::ADD ||
15287 Cond.getOpcode() == X86ISD::SUB ||
15288 Cond.getOpcode() == X86ISD::SMUL ||
15289 Cond.getOpcode() == X86ISD::UMUL)
15290 Cond = LowerXALUO(Cond, DAG);
15293 // Look pass (and (setcc_carry (cmp ...)), 1).
15294 if (Cond.getOpcode() == ISD::AND &&
15295 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
15296 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
15297 if (C && C->getAPIntValue() == 1)
15298 Cond = Cond.getOperand(0);
15301 // If condition flag is set by a X86ISD::CMP, then use it as the condition
15302 // setting operand in place of the X86ISD::SETCC.
15303 unsigned CondOpcode = Cond.getOpcode();
15304 if (CondOpcode == X86ISD::SETCC ||
15305 CondOpcode == X86ISD::SETCC_CARRY) {
15306 CC = Cond.getOperand(0);
15308 SDValue Cmp = Cond.getOperand(1);
15309 unsigned Opc = Cmp.getOpcode();
15310 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
15311 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
15315 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
15319 // These can only come from an arithmetic instruction with overflow,
15320 // e.g. SADDO, UADDO.
15321 Cond = Cond.getNode()->getOperand(1);
15327 CondOpcode = Cond.getOpcode();
15328 if (CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
15329 CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
15330 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
15331 Cond.getOperand(0).getValueType() != MVT::i8)) {
15332 SDValue LHS = Cond.getOperand(0);
15333 SDValue RHS = Cond.getOperand(1);
15334 unsigned X86Opcode;
15337 // Keep this in sync with LowerXALUO, otherwise we might create redundant
15338 // instructions that can't be removed afterwards (i.e. X86ISD::ADD and
15340 switch (CondOpcode) {
15341 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
15343 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
15345 X86Opcode = X86ISD::INC; X86Cond = X86::COND_O;
15348 X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
15349 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
15351 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
15353 X86Opcode = X86ISD::DEC; X86Cond = X86::COND_O;
15356 X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
15357 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
15358 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
15359 default: llvm_unreachable("unexpected overflowing operator");
15362 X86Cond = X86::GetOppositeBranchCondition((X86::CondCode)X86Cond);
15363 if (CondOpcode == ISD::UMULO)
15364 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
15367 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
15369 SDValue X86Op = DAG.getNode(X86Opcode, dl, VTs, LHS, RHS);
15371 if (CondOpcode == ISD::UMULO)
15372 Cond = X86Op.getValue(2);
15374 Cond = X86Op.getValue(1);
15376 CC = DAG.getConstant(X86Cond, MVT::i8);
15380 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
15381 SDValue Cmp = Cond.getOperand(0).getOperand(1);
15382 if (CondOpc == ISD::OR) {
15383 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
15384 // two branches instead of an explicit OR instruction with a
15386 if (Cmp == Cond.getOperand(1).getOperand(1) &&
15387 isX86LogicalCmp(Cmp)) {
15388 CC = Cond.getOperand(0).getOperand(0);
15389 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15390 Chain, Dest, CC, Cmp);
15391 CC = Cond.getOperand(1).getOperand(0);
15395 } else { // ISD::AND
15396 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
15397 // two branches instead of an explicit AND instruction with a
15398 // separate test. However, we only do this if this block doesn't
15399 // have a fall-through edge, because this requires an explicit
15400 // jmp when the condition is false.
15401 if (Cmp == Cond.getOperand(1).getOperand(1) &&
15402 isX86LogicalCmp(Cmp) &&
15403 Op.getNode()->hasOneUse()) {
15404 X86::CondCode CCode =
15405 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
15406 CCode = X86::GetOppositeBranchCondition(CCode);
15407 CC = DAG.getConstant(CCode, MVT::i8);
15408 SDNode *User = *Op.getNode()->use_begin();
15409 // Look for an unconditional branch following this conditional branch.
15410 // We need this because we need to reverse the successors in order
15411 // to implement FCMP_OEQ.
15412 if (User->getOpcode() == ISD::BR) {
15413 SDValue FalseBB = User->getOperand(1);
15415 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
15416 assert(NewBR == User);
15420 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15421 Chain, Dest, CC, Cmp);
15422 X86::CondCode CCode =
15423 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
15424 CCode = X86::GetOppositeBranchCondition(CCode);
15425 CC = DAG.getConstant(CCode, MVT::i8);
15431 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
15432 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
15433 // It should be transformed during dag combiner except when the condition
15434 // is set by a arithmetics with overflow node.
15435 X86::CondCode CCode =
15436 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
15437 CCode = X86::GetOppositeBranchCondition(CCode);
15438 CC = DAG.getConstant(CCode, MVT::i8);
15439 Cond = Cond.getOperand(0).getOperand(1);
15441 } else if (Cond.getOpcode() == ISD::SETCC &&
15442 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETOEQ) {
15443 // For FCMP_OEQ, we can emit
15444 // two branches instead of an explicit AND instruction with a
15445 // separate test. However, we only do this if this block doesn't
15446 // have a fall-through edge, because this requires an explicit
15447 // jmp when the condition is false.
15448 if (Op.getNode()->hasOneUse()) {
15449 SDNode *User = *Op.getNode()->use_begin();
15450 // Look for an unconditional branch following this conditional branch.
15451 // We need this because we need to reverse the successors in order
15452 // to implement FCMP_OEQ.
15453 if (User->getOpcode() == ISD::BR) {
15454 SDValue FalseBB = User->getOperand(1);
15456 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
15457 assert(NewBR == User);
15461 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
15462 Cond.getOperand(0), Cond.getOperand(1));
15463 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
15464 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
15465 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15466 Chain, Dest, CC, Cmp);
15467 CC = DAG.getConstant(X86::COND_P, MVT::i8);
15472 } else if (Cond.getOpcode() == ISD::SETCC &&
15473 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETUNE) {
15474 // For FCMP_UNE, we can emit
15475 // two branches instead of an explicit AND instruction with a
15476 // separate test. However, we only do this if this block doesn't
15477 // have a fall-through edge, because this requires an explicit
15478 // jmp when the condition is false.
15479 if (Op.getNode()->hasOneUse()) {
15480 SDNode *User = *Op.getNode()->use_begin();
15481 // Look for an unconditional branch following this conditional branch.
15482 // We need this because we need to reverse the successors in order
15483 // to implement FCMP_UNE.
15484 if (User->getOpcode() == ISD::BR) {
15485 SDValue FalseBB = User->getOperand(1);
15487 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
15488 assert(NewBR == User);
15491 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
15492 Cond.getOperand(0), Cond.getOperand(1));
15493 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
15494 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
15495 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15496 Chain, Dest, CC, Cmp);
15497 CC = DAG.getConstant(X86::COND_NP, MVT::i8);
15507 // Look pass the truncate if the high bits are known zero.
15508 if (isTruncWithZeroHighBitsInput(Cond, DAG))
15509 Cond = Cond.getOperand(0);
15511 // We know the result of AND is compared against zero. Try to match
15513 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
15514 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
15515 if (NewSetCC.getNode()) {
15516 CC = NewSetCC.getOperand(0);
15517 Cond = NewSetCC.getOperand(1);
15524 X86::CondCode X86Cond = Inverted ? X86::COND_E : X86::COND_NE;
15525 CC = DAG.getConstant(X86Cond, MVT::i8);
15526 Cond = EmitTest(Cond, X86Cond, dl, DAG);
15528 Cond = ConvertCmpIfNecessary(Cond, DAG);
15529 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15530 Chain, Dest, CC, Cond);
15533 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
15534 // Calls to _alloca are needed to probe the stack when allocating more than 4k
15535 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
15536 // that the guard pages used by the OS virtual memory manager are allocated in
15537 // correct sequence.
15539 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
15540 SelectionDAG &DAG) const {
15541 MachineFunction &MF = DAG.getMachineFunction();
15542 bool SplitStack = MF.shouldSplitStack();
15543 bool Lower = (Subtarget->isOSWindows() && !Subtarget->isTargetMacho()) ||
15548 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
15549 SDNode* Node = Op.getNode();
15551 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
15552 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
15553 " not tell us which reg is the stack pointer!");
15554 EVT VT = Node->getValueType(0);
15555 SDValue Tmp1 = SDValue(Node, 0);
15556 SDValue Tmp2 = SDValue(Node, 1);
15557 SDValue Tmp3 = Node->getOperand(2);
15558 SDValue Chain = Tmp1.getOperand(0);
15560 // Chain the dynamic stack allocation so that it doesn't modify the stack
15561 // pointer when other instructions are using the stack.
15562 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true),
15565 SDValue Size = Tmp2.getOperand(1);
15566 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT);
15567 Chain = SP.getValue(1);
15568 unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue();
15569 const TargetFrameLowering &TFI = *DAG.getSubtarget().getFrameLowering();
15570 unsigned StackAlign = TFI.getStackAlignment();
15571 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value
15572 if (Align > StackAlign)
15573 Tmp1 = DAG.getNode(ISD::AND, dl, VT, Tmp1,
15574 DAG.getConstant(-(uint64_t)Align, VT));
15575 Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); // Output chain
15577 Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, true),
15578 DAG.getIntPtrConstant(0, true), SDValue(),
15581 SDValue Ops[2] = { Tmp1, Tmp2 };
15582 return DAG.getMergeValues(Ops, dl);
15586 SDValue Chain = Op.getOperand(0);
15587 SDValue Size = Op.getOperand(1);
15588 unsigned Align = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
15589 EVT VT = Op.getNode()->getValueType(0);
15591 bool Is64Bit = Subtarget->is64Bit();
15592 EVT SPTy = getPointerTy();
15595 MachineRegisterInfo &MRI = MF.getRegInfo();
15598 // The 64 bit implementation of segmented stacks needs to clobber both r10
15599 // r11. This makes it impossible to use it along with nested parameters.
15600 const Function *F = MF.getFunction();
15602 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
15604 if (I->hasNestAttr())
15605 report_fatal_error("Cannot use segmented stacks with functions that "
15606 "have nested arguments.");
15609 const TargetRegisterClass *AddrRegClass =
15610 getRegClassFor(getPointerTy());
15611 unsigned Vreg = MRI.createVirtualRegister(AddrRegClass);
15612 Chain = DAG.getCopyToReg(Chain, dl, Vreg, Size);
15613 SDValue Value = DAG.getNode(X86ISD::SEG_ALLOCA, dl, SPTy, Chain,
15614 DAG.getRegister(Vreg, SPTy));
15615 SDValue Ops1[2] = { Value, Chain };
15616 return DAG.getMergeValues(Ops1, dl);
15619 const unsigned Reg = (Subtarget->isTarget64BitLP64() ? X86::RAX : X86::EAX);
15621 Chain = DAG.getCopyToReg(Chain, dl, Reg, Size, Flag);
15622 Flag = Chain.getValue(1);
15623 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
15625 Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag);
15627 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
15628 DAG.getSubtarget().getRegisterInfo());
15629 unsigned SPReg = RegInfo->getStackRegister();
15630 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, SPTy);
15631 Chain = SP.getValue(1);
15634 SP = DAG.getNode(ISD::AND, dl, VT, SP.getValue(0),
15635 DAG.getConstant(-(uint64_t)Align, VT));
15636 Chain = DAG.getCopyToReg(Chain, dl, SPReg, SP);
15639 SDValue Ops1[2] = { SP, Chain };
15640 return DAG.getMergeValues(Ops1, dl);
15644 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
15645 MachineFunction &MF = DAG.getMachineFunction();
15646 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
15648 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
15651 if (!Subtarget->is64Bit() || Subtarget->isTargetWin64()) {
15652 // vastart just stores the address of the VarArgsFrameIndex slot into the
15653 // memory location argument.
15654 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
15656 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
15657 MachinePointerInfo(SV), false, false, 0);
15661 // gp_offset (0 - 6 * 8)
15662 // fp_offset (48 - 48 + 8 * 16)
15663 // overflow_arg_area (point to parameters coming in memory).
15665 SmallVector<SDValue, 8> MemOps;
15666 SDValue FIN = Op.getOperand(1);
15668 SDValue Store = DAG.getStore(Op.getOperand(0), DL,
15669 DAG.getConstant(FuncInfo->getVarArgsGPOffset(),
15671 FIN, MachinePointerInfo(SV), false, false, 0);
15672 MemOps.push_back(Store);
15675 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
15676 FIN, DAG.getIntPtrConstant(4));
15677 Store = DAG.getStore(Op.getOperand(0), DL,
15678 DAG.getConstant(FuncInfo->getVarArgsFPOffset(),
15680 FIN, MachinePointerInfo(SV, 4), false, false, 0);
15681 MemOps.push_back(Store);
15683 // Store ptr to overflow_arg_area
15684 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
15685 FIN, DAG.getIntPtrConstant(4));
15686 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
15688 Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN,
15689 MachinePointerInfo(SV, 8),
15691 MemOps.push_back(Store);
15693 // Store ptr to reg_save_area.
15694 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
15695 FIN, DAG.getIntPtrConstant(8));
15696 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
15698 Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN,
15699 MachinePointerInfo(SV, 16), false, false, 0);
15700 MemOps.push_back(Store);
15701 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps);
15704 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
15705 assert(Subtarget->is64Bit() &&
15706 "LowerVAARG only handles 64-bit va_arg!");
15707 assert((Subtarget->isTargetLinux() ||
15708 Subtarget->isTargetDarwin()) &&
15709 "Unhandled target in LowerVAARG");
15710 assert(Op.getNode()->getNumOperands() == 4);
15711 SDValue Chain = Op.getOperand(0);
15712 SDValue SrcPtr = Op.getOperand(1);
15713 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
15714 unsigned Align = Op.getConstantOperandVal(3);
15717 EVT ArgVT = Op.getNode()->getValueType(0);
15718 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
15719 uint32_t ArgSize = getDataLayout()->getTypeAllocSize(ArgTy);
15722 // Decide which area this value should be read from.
15723 // TODO: Implement the AMD64 ABI in its entirety. This simple
15724 // selection mechanism works only for the basic types.
15725 if (ArgVT == MVT::f80) {
15726 llvm_unreachable("va_arg for f80 not yet implemented");
15727 } else if (ArgVT.isFloatingPoint() && ArgSize <= 16 /*bytes*/) {
15728 ArgMode = 2; // Argument passed in XMM register. Use fp_offset.
15729 } else if (ArgVT.isInteger() && ArgSize <= 32 /*bytes*/) {
15730 ArgMode = 1; // Argument passed in GPR64 register(s). Use gp_offset.
15732 llvm_unreachable("Unhandled argument type in LowerVAARG");
15735 if (ArgMode == 2) {
15736 // Sanity Check: Make sure using fp_offset makes sense.
15737 assert(!DAG.getTarget().Options.UseSoftFloat &&
15738 !(DAG.getMachineFunction()
15739 .getFunction()->getAttributes()
15740 .hasAttribute(AttributeSet::FunctionIndex,
15741 Attribute::NoImplicitFloat)) &&
15742 Subtarget->hasSSE1());
15745 // Insert VAARG_64 node into the DAG
15746 // VAARG_64 returns two values: Variable Argument Address, Chain
15747 SmallVector<SDValue, 11> InstOps;
15748 InstOps.push_back(Chain);
15749 InstOps.push_back(SrcPtr);
15750 InstOps.push_back(DAG.getConstant(ArgSize, MVT::i32));
15751 InstOps.push_back(DAG.getConstant(ArgMode, MVT::i8));
15752 InstOps.push_back(DAG.getConstant(Align, MVT::i32));
15753 SDVTList VTs = DAG.getVTList(getPointerTy(), MVT::Other);
15754 SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl,
15755 VTs, InstOps, MVT::i64,
15756 MachinePointerInfo(SV),
15758 /*Volatile=*/false,
15760 /*WriteMem=*/true);
15761 Chain = VAARG.getValue(1);
15763 // Load the next argument and return it
15764 return DAG.getLoad(ArgVT, dl,
15767 MachinePointerInfo(),
15768 false, false, false, 0);
15771 static SDValue LowerVACOPY(SDValue Op, const X86Subtarget *Subtarget,
15772 SelectionDAG &DAG) {
15773 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
15774 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
15775 SDValue Chain = Op.getOperand(0);
15776 SDValue DstPtr = Op.getOperand(1);
15777 SDValue SrcPtr = Op.getOperand(2);
15778 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
15779 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
15782 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr,
15783 DAG.getIntPtrConstant(24), 8, /*isVolatile*/false,
15785 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
15788 // getTargetVShiftByConstNode - Handle vector element shifts where the shift
15789 // amount is a constant. Takes immediate version of shift as input.
15790 static SDValue getTargetVShiftByConstNode(unsigned Opc, SDLoc dl, MVT VT,
15791 SDValue SrcOp, uint64_t ShiftAmt,
15792 SelectionDAG &DAG) {
15793 MVT ElementType = VT.getVectorElementType();
15795 // Fold this packed shift into its first operand if ShiftAmt is 0.
15799 // Check for ShiftAmt >= element width
15800 if (ShiftAmt >= ElementType.getSizeInBits()) {
15801 if (Opc == X86ISD::VSRAI)
15802 ShiftAmt = ElementType.getSizeInBits() - 1;
15804 return DAG.getConstant(0, VT);
15807 assert((Opc == X86ISD::VSHLI || Opc == X86ISD::VSRLI || Opc == X86ISD::VSRAI)
15808 && "Unknown target vector shift-by-constant node");
15810 // Fold this packed vector shift into a build vector if SrcOp is a
15811 // vector of Constants or UNDEFs, and SrcOp valuetype is the same as VT.
15812 if (VT == SrcOp.getSimpleValueType() &&
15813 ISD::isBuildVectorOfConstantSDNodes(SrcOp.getNode())) {
15814 SmallVector<SDValue, 8> Elts;
15815 unsigned NumElts = SrcOp->getNumOperands();
15816 ConstantSDNode *ND;
15819 default: llvm_unreachable(nullptr);
15820 case X86ISD::VSHLI:
15821 for (unsigned i=0; i!=NumElts; ++i) {
15822 SDValue CurrentOp = SrcOp->getOperand(i);
15823 if (CurrentOp->getOpcode() == ISD::UNDEF) {
15824 Elts.push_back(CurrentOp);
15827 ND = cast<ConstantSDNode>(CurrentOp);
15828 const APInt &C = ND->getAPIntValue();
15829 Elts.push_back(DAG.getConstant(C.shl(ShiftAmt), ElementType));
15832 case X86ISD::VSRLI:
15833 for (unsigned i=0; i!=NumElts; ++i) {
15834 SDValue CurrentOp = SrcOp->getOperand(i);
15835 if (CurrentOp->getOpcode() == ISD::UNDEF) {
15836 Elts.push_back(CurrentOp);
15839 ND = cast<ConstantSDNode>(CurrentOp);
15840 const APInt &C = ND->getAPIntValue();
15841 Elts.push_back(DAG.getConstant(C.lshr(ShiftAmt), ElementType));
15844 case X86ISD::VSRAI:
15845 for (unsigned i=0; i!=NumElts; ++i) {
15846 SDValue CurrentOp = SrcOp->getOperand(i);
15847 if (CurrentOp->getOpcode() == ISD::UNDEF) {
15848 Elts.push_back(CurrentOp);
15851 ND = cast<ConstantSDNode>(CurrentOp);
15852 const APInt &C = ND->getAPIntValue();
15853 Elts.push_back(DAG.getConstant(C.ashr(ShiftAmt), ElementType));
15858 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
15861 return DAG.getNode(Opc, dl, VT, SrcOp, DAG.getConstant(ShiftAmt, MVT::i8));
15864 // getTargetVShiftNode - Handle vector element shifts where the shift amount
15865 // may or may not be a constant. Takes immediate version of shift as input.
15866 static SDValue getTargetVShiftNode(unsigned Opc, SDLoc dl, MVT VT,
15867 SDValue SrcOp, SDValue ShAmt,
15868 SelectionDAG &DAG) {
15869 assert(ShAmt.getValueType() == MVT::i32 && "ShAmt is not i32");
15871 // Catch shift-by-constant.
15872 if (ConstantSDNode *CShAmt = dyn_cast<ConstantSDNode>(ShAmt))
15873 return getTargetVShiftByConstNode(Opc, dl, VT, SrcOp,
15874 CShAmt->getZExtValue(), DAG);
15876 // Change opcode to non-immediate version
15878 default: llvm_unreachable("Unknown target vector shift node");
15879 case X86ISD::VSHLI: Opc = X86ISD::VSHL; break;
15880 case X86ISD::VSRLI: Opc = X86ISD::VSRL; break;
15881 case X86ISD::VSRAI: Opc = X86ISD::VSRA; break;
15884 // Need to build a vector containing shift amount
15885 // Shift amount is 32-bits, but SSE instructions read 64-bit, so fill with 0
15888 ShOps[1] = DAG.getConstant(0, MVT::i32);
15889 ShOps[2] = ShOps[3] = DAG.getUNDEF(MVT::i32);
15890 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, ShOps);
15892 // The return type has to be a 128-bit type with the same element
15893 // type as the input type.
15894 MVT EltVT = VT.getVectorElementType();
15895 EVT ShVT = MVT::getVectorVT(EltVT, 128/EltVT.getSizeInBits());
15897 ShAmt = DAG.getNode(ISD::BITCAST, dl, ShVT, ShAmt);
15898 return DAG.getNode(Opc, dl, VT, SrcOp, ShAmt);
15901 /// \brief Return (vselect \p Mask, \p Op, \p PreservedSrc) along with the
15902 /// necessary casting for \p Mask when lowering masking intrinsics.
15903 static SDValue getVectorMaskingNode(SDValue Op, SDValue Mask,
15904 SDValue PreservedSrc, SelectionDAG &DAG) {
15905 EVT VT = Op.getValueType();
15906 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(),
15907 MVT::i1, VT.getVectorNumElements());
15910 assert(MaskVT.isSimple() && "invalid mask type");
15911 return DAG.getNode(ISD::VSELECT, dl, VT,
15912 DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask),
15916 static unsigned getOpcodeForFMAIntrinsic(unsigned IntNo) {
15918 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
15919 case Intrinsic::x86_fma_vfmadd_ps:
15920 case Intrinsic::x86_fma_vfmadd_pd:
15921 case Intrinsic::x86_fma_vfmadd_ps_256:
15922 case Intrinsic::x86_fma_vfmadd_pd_256:
15923 case Intrinsic::x86_fma_mask_vfmadd_ps_512:
15924 case Intrinsic::x86_fma_mask_vfmadd_pd_512:
15925 return X86ISD::FMADD;
15926 case Intrinsic::x86_fma_vfmsub_ps:
15927 case Intrinsic::x86_fma_vfmsub_pd:
15928 case Intrinsic::x86_fma_vfmsub_ps_256:
15929 case Intrinsic::x86_fma_vfmsub_pd_256:
15930 case Intrinsic::x86_fma_mask_vfmsub_ps_512:
15931 case Intrinsic::x86_fma_mask_vfmsub_pd_512:
15932 return X86ISD::FMSUB;
15933 case Intrinsic::x86_fma_vfnmadd_ps:
15934 case Intrinsic::x86_fma_vfnmadd_pd:
15935 case Intrinsic::x86_fma_vfnmadd_ps_256:
15936 case Intrinsic::x86_fma_vfnmadd_pd_256:
15937 case Intrinsic::x86_fma_mask_vfnmadd_ps_512:
15938 case Intrinsic::x86_fma_mask_vfnmadd_pd_512:
15939 return X86ISD::FNMADD;
15940 case Intrinsic::x86_fma_vfnmsub_ps:
15941 case Intrinsic::x86_fma_vfnmsub_pd:
15942 case Intrinsic::x86_fma_vfnmsub_ps_256:
15943 case Intrinsic::x86_fma_vfnmsub_pd_256:
15944 case Intrinsic::x86_fma_mask_vfnmsub_ps_512:
15945 case Intrinsic::x86_fma_mask_vfnmsub_pd_512:
15946 return X86ISD::FNMSUB;
15947 case Intrinsic::x86_fma_vfmaddsub_ps:
15948 case Intrinsic::x86_fma_vfmaddsub_pd:
15949 case Intrinsic::x86_fma_vfmaddsub_ps_256:
15950 case Intrinsic::x86_fma_vfmaddsub_pd_256:
15951 case Intrinsic::x86_fma_mask_vfmaddsub_ps_512:
15952 case Intrinsic::x86_fma_mask_vfmaddsub_pd_512:
15953 return X86ISD::FMADDSUB;
15954 case Intrinsic::x86_fma_vfmsubadd_ps:
15955 case Intrinsic::x86_fma_vfmsubadd_pd:
15956 case Intrinsic::x86_fma_vfmsubadd_ps_256:
15957 case Intrinsic::x86_fma_vfmsubadd_pd_256:
15958 case Intrinsic::x86_fma_mask_vfmsubadd_ps_512:
15959 case Intrinsic::x86_fma_mask_vfmsubadd_pd_512:
15960 return X86ISD::FMSUBADD;
15964 static SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) {
15966 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
15968 const IntrinsicData* IntrData = getIntrinsicWithoutChain(IntNo);
15970 switch(IntrData->Type) {
15971 case INTR_TYPE_1OP:
15972 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1));
15973 case INTR_TYPE_2OP:
15974 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
15976 case INTR_TYPE_3OP:
15977 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
15978 Op.getOperand(2), Op.getOperand(3));
15979 case COMI: { // Comparison intrinsics
15980 ISD::CondCode CC = (ISD::CondCode)IntrData->Opc1;
15981 SDValue LHS = Op.getOperand(1);
15982 SDValue RHS = Op.getOperand(2);
15983 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG);
15984 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!");
15985 SDValue Cond = DAG.getNode(IntrData->Opc0, dl, MVT::i32, LHS, RHS);
15986 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
15987 DAG.getConstant(X86CC, MVT::i8), Cond);
15988 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
15991 return getTargetVShiftNode(IntrData->Opc0, dl, Op.getSimpleValueType(),
15992 Op.getOperand(1), Op.getOperand(2), DAG);
15999 default: return SDValue(); // Don't custom lower most intrinsics.
16001 // Arithmetic intrinsics.
16002 case Intrinsic::x86_sse2_pmulu_dq:
16003 case Intrinsic::x86_avx2_pmulu_dq:
16004 return DAG.getNode(X86ISD::PMULUDQ, dl, Op.getValueType(),
16005 Op.getOperand(1), Op.getOperand(2));
16007 case Intrinsic::x86_sse41_pmuldq:
16008 case Intrinsic::x86_avx2_pmul_dq:
16009 return DAG.getNode(X86ISD::PMULDQ, dl, Op.getValueType(),
16010 Op.getOperand(1), Op.getOperand(2));
16012 case Intrinsic::x86_sse2_pmulhu_w:
16013 case Intrinsic::x86_avx2_pmulhu_w:
16014 return DAG.getNode(ISD::MULHU, dl, Op.getValueType(),
16015 Op.getOperand(1), Op.getOperand(2));
16017 case Intrinsic::x86_sse2_pmulh_w:
16018 case Intrinsic::x86_avx2_pmulh_w:
16019 return DAG.getNode(ISD::MULHS, dl, Op.getValueType(),
16020 Op.getOperand(1), Op.getOperand(2));
16022 // SSE/SSE2/AVX floating point max/min intrinsics.
16023 case Intrinsic::x86_sse_max_ps:
16024 case Intrinsic::x86_sse2_max_pd:
16025 case Intrinsic::x86_avx_max_ps_256:
16026 case Intrinsic::x86_avx_max_pd_256:
16027 case Intrinsic::x86_sse_min_ps:
16028 case Intrinsic::x86_sse2_min_pd:
16029 case Intrinsic::x86_avx_min_ps_256:
16030 case Intrinsic::x86_avx_min_pd_256: {
16033 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
16034 case Intrinsic::x86_sse_max_ps:
16035 case Intrinsic::x86_sse2_max_pd:
16036 case Intrinsic::x86_avx_max_ps_256:
16037 case Intrinsic::x86_avx_max_pd_256:
16038 Opcode = X86ISD::FMAX;
16040 case Intrinsic::x86_sse_min_ps:
16041 case Intrinsic::x86_sse2_min_pd:
16042 case Intrinsic::x86_avx_min_ps_256:
16043 case Intrinsic::x86_avx_min_pd_256:
16044 Opcode = X86ISD::FMIN;
16047 return DAG.getNode(Opcode, dl, Op.getValueType(),
16048 Op.getOperand(1), Op.getOperand(2));
16051 // AVX2 variable shift intrinsics
16052 case Intrinsic::x86_avx2_psllv_d:
16053 case Intrinsic::x86_avx2_psllv_q:
16054 case Intrinsic::x86_avx2_psllv_d_256:
16055 case Intrinsic::x86_avx2_psllv_q_256:
16056 case Intrinsic::x86_avx2_psrlv_d:
16057 case Intrinsic::x86_avx2_psrlv_q:
16058 case Intrinsic::x86_avx2_psrlv_d_256:
16059 case Intrinsic::x86_avx2_psrlv_q_256:
16060 case Intrinsic::x86_avx2_psrav_d:
16061 case Intrinsic::x86_avx2_psrav_d_256: {
16064 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
16065 case Intrinsic::x86_avx2_psllv_d:
16066 case Intrinsic::x86_avx2_psllv_q:
16067 case Intrinsic::x86_avx2_psllv_d_256:
16068 case Intrinsic::x86_avx2_psllv_q_256:
16071 case Intrinsic::x86_avx2_psrlv_d:
16072 case Intrinsic::x86_avx2_psrlv_q:
16073 case Intrinsic::x86_avx2_psrlv_d_256:
16074 case Intrinsic::x86_avx2_psrlv_q_256:
16077 case Intrinsic::x86_avx2_psrav_d:
16078 case Intrinsic::x86_avx2_psrav_d_256:
16082 return DAG.getNode(Opcode, dl, Op.getValueType(),
16083 Op.getOperand(1), Op.getOperand(2));
16086 case Intrinsic::x86_sse2_packssdw_128:
16087 case Intrinsic::x86_sse2_packsswb_128:
16088 case Intrinsic::x86_avx2_packssdw:
16089 case Intrinsic::x86_avx2_packsswb:
16090 return DAG.getNode(X86ISD::PACKSS, dl, Op.getValueType(),
16091 Op.getOperand(1), Op.getOperand(2));
16093 case Intrinsic::x86_sse2_packuswb_128:
16094 case Intrinsic::x86_sse41_packusdw:
16095 case Intrinsic::x86_avx2_packuswb:
16096 case Intrinsic::x86_avx2_packusdw:
16097 return DAG.getNode(X86ISD::PACKUS, dl, Op.getValueType(),
16098 Op.getOperand(1), Op.getOperand(2));
16100 case Intrinsic::x86_ssse3_pshuf_b_128:
16101 case Intrinsic::x86_avx2_pshuf_b:
16102 return DAG.getNode(X86ISD::PSHUFB, dl, Op.getValueType(),
16103 Op.getOperand(1), Op.getOperand(2));
16105 case Intrinsic::x86_sse2_pshuf_d:
16106 return DAG.getNode(X86ISD::PSHUFD, dl, Op.getValueType(),
16107 Op.getOperand(1), Op.getOperand(2));
16109 case Intrinsic::x86_sse2_pshufl_w:
16110 return DAG.getNode(X86ISD::PSHUFLW, dl, Op.getValueType(),
16111 Op.getOperand(1), Op.getOperand(2));
16113 case Intrinsic::x86_sse2_pshufh_w:
16114 return DAG.getNode(X86ISD::PSHUFHW, dl, Op.getValueType(),
16115 Op.getOperand(1), Op.getOperand(2));
16117 case Intrinsic::x86_ssse3_psign_b_128:
16118 case Intrinsic::x86_ssse3_psign_w_128:
16119 case Intrinsic::x86_ssse3_psign_d_128:
16120 case Intrinsic::x86_avx2_psign_b:
16121 case Intrinsic::x86_avx2_psign_w:
16122 case Intrinsic::x86_avx2_psign_d:
16123 return DAG.getNode(X86ISD::PSIGN, dl, Op.getValueType(),
16124 Op.getOperand(1), Op.getOperand(2));
16126 case Intrinsic::x86_avx2_permd:
16127 case Intrinsic::x86_avx2_permps:
16128 // Operands intentionally swapped. Mask is last operand to intrinsic,
16129 // but second operand for node/instruction.
16130 return DAG.getNode(X86ISD::VPERMV, dl, Op.getValueType(),
16131 Op.getOperand(2), Op.getOperand(1));
16133 case Intrinsic::x86_avx512_mask_valign_q_512:
16134 case Intrinsic::x86_avx512_mask_valign_d_512:
16135 // Vector source operands are swapped.
16136 return getVectorMaskingNode(DAG.getNode(X86ISD::VALIGN, dl,
16137 Op.getValueType(), Op.getOperand(2),
16140 Op.getOperand(5), Op.getOperand(4), DAG);
16142 // ptest and testp intrinsics. The intrinsic these come from are designed to
16143 // return an integer value, not just an instruction so lower it to the ptest
16144 // or testp pattern and a setcc for the result.
16145 case Intrinsic::x86_sse41_ptestz:
16146 case Intrinsic::x86_sse41_ptestc:
16147 case Intrinsic::x86_sse41_ptestnzc:
16148 case Intrinsic::x86_avx_ptestz_256:
16149 case Intrinsic::x86_avx_ptestc_256:
16150 case Intrinsic::x86_avx_ptestnzc_256:
16151 case Intrinsic::x86_avx_vtestz_ps:
16152 case Intrinsic::x86_avx_vtestc_ps:
16153 case Intrinsic::x86_avx_vtestnzc_ps:
16154 case Intrinsic::x86_avx_vtestz_pd:
16155 case Intrinsic::x86_avx_vtestc_pd:
16156 case Intrinsic::x86_avx_vtestnzc_pd:
16157 case Intrinsic::x86_avx_vtestz_ps_256:
16158 case Intrinsic::x86_avx_vtestc_ps_256:
16159 case Intrinsic::x86_avx_vtestnzc_ps_256:
16160 case Intrinsic::x86_avx_vtestz_pd_256:
16161 case Intrinsic::x86_avx_vtestc_pd_256:
16162 case Intrinsic::x86_avx_vtestnzc_pd_256: {
16163 bool IsTestPacked = false;
16166 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
16167 case Intrinsic::x86_avx_vtestz_ps:
16168 case Intrinsic::x86_avx_vtestz_pd:
16169 case Intrinsic::x86_avx_vtestz_ps_256:
16170 case Intrinsic::x86_avx_vtestz_pd_256:
16171 IsTestPacked = true; // Fallthrough
16172 case Intrinsic::x86_sse41_ptestz:
16173 case Intrinsic::x86_avx_ptestz_256:
16175 X86CC = X86::COND_E;
16177 case Intrinsic::x86_avx_vtestc_ps:
16178 case Intrinsic::x86_avx_vtestc_pd:
16179 case Intrinsic::x86_avx_vtestc_ps_256:
16180 case Intrinsic::x86_avx_vtestc_pd_256:
16181 IsTestPacked = true; // Fallthrough
16182 case Intrinsic::x86_sse41_ptestc:
16183 case Intrinsic::x86_avx_ptestc_256:
16185 X86CC = X86::COND_B;
16187 case Intrinsic::x86_avx_vtestnzc_ps:
16188 case Intrinsic::x86_avx_vtestnzc_pd:
16189 case Intrinsic::x86_avx_vtestnzc_ps_256:
16190 case Intrinsic::x86_avx_vtestnzc_pd_256:
16191 IsTestPacked = true; // Fallthrough
16192 case Intrinsic::x86_sse41_ptestnzc:
16193 case Intrinsic::x86_avx_ptestnzc_256:
16195 X86CC = X86::COND_A;
16199 SDValue LHS = Op.getOperand(1);
16200 SDValue RHS = Op.getOperand(2);
16201 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST;
16202 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS);
16203 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
16204 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
16205 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
16207 case Intrinsic::x86_avx512_kortestz_w:
16208 case Intrinsic::x86_avx512_kortestc_w: {
16209 unsigned X86CC = (IntNo == Intrinsic::x86_avx512_kortestz_w)? X86::COND_E: X86::COND_B;
16210 SDValue LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1, Op.getOperand(1));
16211 SDValue RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1, Op.getOperand(2));
16212 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
16213 SDValue Test = DAG.getNode(X86ISD::KORTEST, dl, MVT::i32, LHS, RHS);
16214 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i1, CC, Test);
16215 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
16218 case Intrinsic::x86_sse42_pcmpistria128:
16219 case Intrinsic::x86_sse42_pcmpestria128:
16220 case Intrinsic::x86_sse42_pcmpistric128:
16221 case Intrinsic::x86_sse42_pcmpestric128:
16222 case Intrinsic::x86_sse42_pcmpistrio128:
16223 case Intrinsic::x86_sse42_pcmpestrio128:
16224 case Intrinsic::x86_sse42_pcmpistris128:
16225 case Intrinsic::x86_sse42_pcmpestris128:
16226 case Intrinsic::x86_sse42_pcmpistriz128:
16227 case Intrinsic::x86_sse42_pcmpestriz128: {
16231 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
16232 case Intrinsic::x86_sse42_pcmpistria128:
16233 Opcode = X86ISD::PCMPISTRI;
16234 X86CC = X86::COND_A;
16236 case Intrinsic::x86_sse42_pcmpestria128:
16237 Opcode = X86ISD::PCMPESTRI;
16238 X86CC = X86::COND_A;
16240 case Intrinsic::x86_sse42_pcmpistric128:
16241 Opcode = X86ISD::PCMPISTRI;
16242 X86CC = X86::COND_B;
16244 case Intrinsic::x86_sse42_pcmpestric128:
16245 Opcode = X86ISD::PCMPESTRI;
16246 X86CC = X86::COND_B;
16248 case Intrinsic::x86_sse42_pcmpistrio128:
16249 Opcode = X86ISD::PCMPISTRI;
16250 X86CC = X86::COND_O;
16252 case Intrinsic::x86_sse42_pcmpestrio128:
16253 Opcode = X86ISD::PCMPESTRI;
16254 X86CC = X86::COND_O;
16256 case Intrinsic::x86_sse42_pcmpistris128:
16257 Opcode = X86ISD::PCMPISTRI;
16258 X86CC = X86::COND_S;
16260 case Intrinsic::x86_sse42_pcmpestris128:
16261 Opcode = X86ISD::PCMPESTRI;
16262 X86CC = X86::COND_S;
16264 case Intrinsic::x86_sse42_pcmpistriz128:
16265 Opcode = X86ISD::PCMPISTRI;
16266 X86CC = X86::COND_E;
16268 case Intrinsic::x86_sse42_pcmpestriz128:
16269 Opcode = X86ISD::PCMPESTRI;
16270 X86CC = X86::COND_E;
16273 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
16274 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
16275 SDValue PCMP = DAG.getNode(Opcode, dl, VTs, NewOps);
16276 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
16277 DAG.getConstant(X86CC, MVT::i8),
16278 SDValue(PCMP.getNode(), 1));
16279 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
16282 case Intrinsic::x86_sse42_pcmpistri128:
16283 case Intrinsic::x86_sse42_pcmpestri128: {
16285 if (IntNo == Intrinsic::x86_sse42_pcmpistri128)
16286 Opcode = X86ISD::PCMPISTRI;
16288 Opcode = X86ISD::PCMPESTRI;
16290 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
16291 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
16292 return DAG.getNode(Opcode, dl, VTs, NewOps);
16295 case Intrinsic::x86_fma_mask_vfmadd_ps_512:
16296 case Intrinsic::x86_fma_mask_vfmadd_pd_512:
16297 case Intrinsic::x86_fma_mask_vfmsub_ps_512:
16298 case Intrinsic::x86_fma_mask_vfmsub_pd_512:
16299 case Intrinsic::x86_fma_mask_vfnmadd_ps_512:
16300 case Intrinsic::x86_fma_mask_vfnmadd_pd_512:
16301 case Intrinsic::x86_fma_mask_vfnmsub_ps_512:
16302 case Intrinsic::x86_fma_mask_vfnmsub_pd_512:
16303 case Intrinsic::x86_fma_mask_vfmaddsub_ps_512:
16304 case Intrinsic::x86_fma_mask_vfmaddsub_pd_512:
16305 case Intrinsic::x86_fma_mask_vfmsubadd_ps_512:
16306 case Intrinsic::x86_fma_mask_vfmsubadd_pd_512: {
16307 auto *SAE = cast<ConstantSDNode>(Op.getOperand(5));
16308 if (SAE->getZExtValue() == X86::STATIC_ROUNDING::CUR_DIRECTION)
16309 return getVectorMaskingNode(DAG.getNode(getOpcodeForFMAIntrinsic(IntNo),
16310 dl, Op.getValueType(),
16314 Op.getOperand(4), Op.getOperand(1), DAG);
16319 case Intrinsic::x86_fma_vfmadd_ps:
16320 case Intrinsic::x86_fma_vfmadd_pd:
16321 case Intrinsic::x86_fma_vfmsub_ps:
16322 case Intrinsic::x86_fma_vfmsub_pd:
16323 case Intrinsic::x86_fma_vfnmadd_ps:
16324 case Intrinsic::x86_fma_vfnmadd_pd:
16325 case Intrinsic::x86_fma_vfnmsub_ps:
16326 case Intrinsic::x86_fma_vfnmsub_pd:
16327 case Intrinsic::x86_fma_vfmaddsub_ps:
16328 case Intrinsic::x86_fma_vfmaddsub_pd:
16329 case Intrinsic::x86_fma_vfmsubadd_ps:
16330 case Intrinsic::x86_fma_vfmsubadd_pd:
16331 case Intrinsic::x86_fma_vfmadd_ps_256:
16332 case Intrinsic::x86_fma_vfmadd_pd_256:
16333 case Intrinsic::x86_fma_vfmsub_ps_256:
16334 case Intrinsic::x86_fma_vfmsub_pd_256:
16335 case Intrinsic::x86_fma_vfnmadd_ps_256:
16336 case Intrinsic::x86_fma_vfnmadd_pd_256:
16337 case Intrinsic::x86_fma_vfnmsub_ps_256:
16338 case Intrinsic::x86_fma_vfnmsub_pd_256:
16339 case Intrinsic::x86_fma_vfmaddsub_ps_256:
16340 case Intrinsic::x86_fma_vfmaddsub_pd_256:
16341 case Intrinsic::x86_fma_vfmsubadd_ps_256:
16342 case Intrinsic::x86_fma_vfmsubadd_pd_256:
16343 return DAG.getNode(getOpcodeForFMAIntrinsic(IntNo), dl, Op.getValueType(),
16344 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
16348 static SDValue getGatherNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
16349 SDValue Src, SDValue Mask, SDValue Base,
16350 SDValue Index, SDValue ScaleOp, SDValue Chain,
16351 const X86Subtarget * Subtarget) {
16353 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
16354 assert(C && "Invalid scale type");
16355 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
16356 EVT MaskVT = MVT::getVectorVT(MVT::i1,
16357 Index.getSimpleValueType().getVectorNumElements());
16359 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
16361 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), MaskVT);
16363 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
16364 SDVTList VTs = DAG.getVTList(Op.getValueType(), MaskVT, MVT::Other);
16365 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
16366 SDValue Segment = DAG.getRegister(0, MVT::i32);
16367 if (Src.getOpcode() == ISD::UNDEF)
16368 Src = getZeroVector(Op.getValueType(), Subtarget, DAG, dl);
16369 SDValue Ops[] = {Src, MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
16370 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
16371 SDValue RetOps[] = { SDValue(Res, 0), SDValue(Res, 2) };
16372 return DAG.getMergeValues(RetOps, dl);
16375 static SDValue getScatterNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
16376 SDValue Src, SDValue Mask, SDValue Base,
16377 SDValue Index, SDValue ScaleOp, SDValue Chain) {
16379 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
16380 assert(C && "Invalid scale type");
16381 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
16382 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
16383 SDValue Segment = DAG.getRegister(0, MVT::i32);
16384 EVT MaskVT = MVT::getVectorVT(MVT::i1,
16385 Index.getSimpleValueType().getVectorNumElements());
16387 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
16389 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), MaskVT);
16391 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
16392 SDVTList VTs = DAG.getVTList(MaskVT, MVT::Other);
16393 SDValue Ops[] = {Base, Scale, Index, Disp, Segment, MaskInReg, Src, Chain};
16394 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
16395 return SDValue(Res, 1);
16398 static SDValue getPrefetchNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
16399 SDValue Mask, SDValue Base, SDValue Index,
16400 SDValue ScaleOp, SDValue Chain) {
16402 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
16403 assert(C && "Invalid scale type");
16404 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
16405 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
16406 SDValue Segment = DAG.getRegister(0, MVT::i32);
16408 MVT::getVectorVT(MVT::i1, Index.getSimpleValueType().getVectorNumElements());
16410 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
16412 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), MaskVT);
16414 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
16415 //SDVTList VTs = DAG.getVTList(MVT::Other);
16416 SDValue Ops[] = {MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
16417 SDNode *Res = DAG.getMachineNode(Opc, dl, MVT::Other, Ops);
16418 return SDValue(Res, 0);
16421 // getReadPerformanceCounter - Handles the lowering of builtin intrinsics that
16422 // read performance monitor counters (x86_rdpmc).
16423 static void getReadPerformanceCounter(SDNode *N, SDLoc DL,
16424 SelectionDAG &DAG, const X86Subtarget *Subtarget,
16425 SmallVectorImpl<SDValue> &Results) {
16426 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
16427 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
16430 // The ECX register is used to select the index of the performance counter
16432 SDValue Chain = DAG.getCopyToReg(N->getOperand(0), DL, X86::ECX,
16434 SDValue rd = DAG.getNode(X86ISD::RDPMC_DAG, DL, Tys, Chain);
16436 // Reads the content of a 64-bit performance counter and returns it in the
16437 // registers EDX:EAX.
16438 if (Subtarget->is64Bit()) {
16439 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
16440 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
16443 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
16444 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
16447 Chain = HI.getValue(1);
16449 if (Subtarget->is64Bit()) {
16450 // The EAX register is loaded with the low-order 32 bits. The EDX register
16451 // is loaded with the supported high-order bits of the counter.
16452 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
16453 DAG.getConstant(32, MVT::i8));
16454 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
16455 Results.push_back(Chain);
16459 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
16460 SDValue Ops[] = { LO, HI };
16461 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
16462 Results.push_back(Pair);
16463 Results.push_back(Chain);
16466 // getReadTimeStampCounter - Handles the lowering of builtin intrinsics that
16467 // read the time stamp counter (x86_rdtsc and x86_rdtscp). This function is
16468 // also used to custom lower READCYCLECOUNTER nodes.
16469 static void getReadTimeStampCounter(SDNode *N, SDLoc DL, unsigned Opcode,
16470 SelectionDAG &DAG, const X86Subtarget *Subtarget,
16471 SmallVectorImpl<SDValue> &Results) {
16472 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
16473 SDValue rd = DAG.getNode(Opcode, DL, Tys, N->getOperand(0));
16476 // The processor's time-stamp counter (a 64-bit MSR) is stored into the
16477 // EDX:EAX registers. EDX is loaded with the high-order 32 bits of the MSR
16478 // and the EAX register is loaded with the low-order 32 bits.
16479 if (Subtarget->is64Bit()) {
16480 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
16481 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
16484 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
16485 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
16488 SDValue Chain = HI.getValue(1);
16490 if (Opcode == X86ISD::RDTSCP_DAG) {
16491 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
16493 // Instruction RDTSCP loads the IA32:TSC_AUX_MSR (address C000_0103H) into
16494 // the ECX register. Add 'ecx' explicitly to the chain.
16495 SDValue ecx = DAG.getCopyFromReg(Chain, DL, X86::ECX, MVT::i32,
16497 // Explicitly store the content of ECX at the location passed in input
16498 // to the 'rdtscp' intrinsic.
16499 Chain = DAG.getStore(ecx.getValue(1), DL, ecx, N->getOperand(2),
16500 MachinePointerInfo(), false, false, 0);
16503 if (Subtarget->is64Bit()) {
16504 // The EDX register is loaded with the high-order 32 bits of the MSR, and
16505 // the EAX register is loaded with the low-order 32 bits.
16506 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
16507 DAG.getConstant(32, MVT::i8));
16508 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
16509 Results.push_back(Chain);
16513 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
16514 SDValue Ops[] = { LO, HI };
16515 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
16516 Results.push_back(Pair);
16517 Results.push_back(Chain);
16520 static SDValue LowerREADCYCLECOUNTER(SDValue Op, const X86Subtarget *Subtarget,
16521 SelectionDAG &DAG) {
16522 SmallVector<SDValue, 2> Results;
16524 getReadTimeStampCounter(Op.getNode(), DL, X86ISD::RDTSC_DAG, DAG, Subtarget,
16526 return DAG.getMergeValues(Results, DL);
16530 static SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
16531 SelectionDAG &DAG) {
16532 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
16534 const IntrinsicData* IntrData = getIntrinsicWithChain(IntNo);
16539 switch(IntrData->Type) {
16541 llvm_unreachable("Unknown Intrinsic Type");
16545 // Emit the node with the right value type.
16546 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Glue, MVT::Other);
16547 SDValue Result = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(0));
16549 // If the value returned by RDRAND/RDSEED was valid (CF=1), return 1.
16550 // Otherwise return the value from Rand, which is always 0, casted to i32.
16551 SDValue Ops[] = { DAG.getZExtOrTrunc(Result, dl, Op->getValueType(1)),
16552 DAG.getConstant(1, Op->getValueType(1)),
16553 DAG.getConstant(X86::COND_B, MVT::i32),
16554 SDValue(Result.getNode(), 1) };
16555 SDValue isValid = DAG.getNode(X86ISD::CMOV, dl,
16556 DAG.getVTList(Op->getValueType(1), MVT::Glue),
16559 // Return { result, isValid, chain }.
16560 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(), Result, isValid,
16561 SDValue(Result.getNode(), 2));
16564 //gather(v1, mask, index, base, scale);
16565 SDValue Chain = Op.getOperand(0);
16566 SDValue Src = Op.getOperand(2);
16567 SDValue Base = Op.getOperand(3);
16568 SDValue Index = Op.getOperand(4);
16569 SDValue Mask = Op.getOperand(5);
16570 SDValue Scale = Op.getOperand(6);
16571 return getGatherNode(IntrData->Opc0, Op, DAG, Src, Mask, Base, Index, Scale, Chain,
16575 //scatter(base, mask, index, v1, scale);
16576 SDValue Chain = Op.getOperand(0);
16577 SDValue Base = Op.getOperand(2);
16578 SDValue Mask = Op.getOperand(3);
16579 SDValue Index = Op.getOperand(4);
16580 SDValue Src = Op.getOperand(5);
16581 SDValue Scale = Op.getOperand(6);
16582 return getScatterNode(IntrData->Opc0, Op, DAG, Src, Mask, Base, Index, Scale, Chain);
16585 SDValue Hint = Op.getOperand(6);
16587 if (dyn_cast<ConstantSDNode> (Hint) == nullptr ||
16588 (HintVal = dyn_cast<ConstantSDNode> (Hint)->getZExtValue()) > 1)
16589 llvm_unreachable("Wrong prefetch hint in intrinsic: should be 0 or 1");
16590 unsigned Opcode = (HintVal ? IntrData->Opc1 : IntrData->Opc0);
16591 SDValue Chain = Op.getOperand(0);
16592 SDValue Mask = Op.getOperand(2);
16593 SDValue Index = Op.getOperand(3);
16594 SDValue Base = Op.getOperand(4);
16595 SDValue Scale = Op.getOperand(5);
16596 return getPrefetchNode(Opcode, Op, DAG, Mask, Base, Index, Scale, Chain);
16598 // Read Time Stamp Counter (RDTSC) and Processor ID (RDTSCP).
16600 SmallVector<SDValue, 2> Results;
16601 getReadTimeStampCounter(Op.getNode(), dl, IntrData->Opc0, DAG, Subtarget, Results);
16602 return DAG.getMergeValues(Results, dl);
16604 // Read Performance Monitoring Counters.
16606 SmallVector<SDValue, 2> Results;
16607 getReadPerformanceCounter(Op.getNode(), dl, DAG, Subtarget, Results);
16608 return DAG.getMergeValues(Results, dl);
16610 // XTEST intrinsics.
16612 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
16613 SDValue InTrans = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(0));
16614 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
16615 DAG.getConstant(X86::COND_NE, MVT::i8),
16617 SDValue Ret = DAG.getNode(ISD::ZERO_EXTEND, dl, Op->getValueType(0), SetCC);
16618 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(),
16619 Ret, SDValue(InTrans.getNode(), 1));
16623 SmallVector<SDValue, 2> Results;
16624 SDVTList CFVTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
16625 SDVTList VTs = DAG.getVTList(Op.getOperand(3)->getValueType(0), MVT::Other);
16626 SDValue GenCF = DAG.getNode(X86ISD::ADD, dl, CFVTs, Op.getOperand(2),
16627 DAG.getConstant(-1, MVT::i8));
16628 SDValue Res = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(3),
16629 Op.getOperand(4), GenCF.getValue(1));
16630 SDValue Store = DAG.getStore(Op.getOperand(0), dl, Res.getValue(0),
16631 Op.getOperand(5), MachinePointerInfo(),
16633 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
16634 DAG.getConstant(X86::COND_B, MVT::i8),
16636 Results.push_back(SetCC);
16637 Results.push_back(Store);
16638 return DAG.getMergeValues(Results, dl);
16643 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op,
16644 SelectionDAG &DAG) const {
16645 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
16646 MFI->setReturnAddressIsTaken(true);
16648 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
16651 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
16653 EVT PtrVT = getPointerTy();
16656 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
16657 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
16658 DAG.getSubtarget().getRegisterInfo());
16659 SDValue Offset = DAG.getConstant(RegInfo->getSlotSize(), PtrVT);
16660 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
16661 DAG.getNode(ISD::ADD, dl, PtrVT,
16662 FrameAddr, Offset),
16663 MachinePointerInfo(), false, false, false, 0);
16666 // Just load the return address.
16667 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
16668 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
16669 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
16672 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
16673 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
16674 MFI->setFrameAddressIsTaken(true);
16676 EVT VT = Op.getValueType();
16677 SDLoc dl(Op); // FIXME probably not meaningful
16678 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
16679 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
16680 DAG.getSubtarget().getRegisterInfo());
16681 unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction());
16682 assert(((FrameReg == X86::RBP && VT == MVT::i64) ||
16683 (FrameReg == X86::EBP && VT == MVT::i32)) &&
16684 "Invalid Frame Register!");
16685 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
16687 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
16688 MachinePointerInfo(),
16689 false, false, false, 0);
16693 // FIXME? Maybe this could be a TableGen attribute on some registers and
16694 // this table could be generated automatically from RegInfo.
16695 unsigned X86TargetLowering::getRegisterByName(const char* RegName,
16697 unsigned Reg = StringSwitch<unsigned>(RegName)
16698 .Case("esp", X86::ESP)
16699 .Case("rsp", X86::RSP)
16703 report_fatal_error("Invalid register name global variable");
16706 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
16707 SelectionDAG &DAG) const {
16708 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
16709 DAG.getSubtarget().getRegisterInfo());
16710 return DAG.getIntPtrConstant(2 * RegInfo->getSlotSize());
16713 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
16714 SDValue Chain = Op.getOperand(0);
16715 SDValue Offset = Op.getOperand(1);
16716 SDValue Handler = Op.getOperand(2);
16719 EVT PtrVT = getPointerTy();
16720 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
16721 DAG.getSubtarget().getRegisterInfo());
16722 unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction());
16723 assert(((FrameReg == X86::RBP && PtrVT == MVT::i64) ||
16724 (FrameReg == X86::EBP && PtrVT == MVT::i32)) &&
16725 "Invalid Frame Register!");
16726 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, PtrVT);
16727 unsigned StoreAddrReg = (PtrVT == MVT::i64) ? X86::RCX : X86::ECX;
16729 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, Frame,
16730 DAG.getIntPtrConstant(RegInfo->getSlotSize()));
16731 StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, StoreAddr, Offset);
16732 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(),
16734 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
16736 return DAG.getNode(X86ISD::EH_RETURN, dl, MVT::Other, Chain,
16737 DAG.getRegister(StoreAddrReg, PtrVT));
16740 SDValue X86TargetLowering::lowerEH_SJLJ_SETJMP(SDValue Op,
16741 SelectionDAG &DAG) const {
16743 return DAG.getNode(X86ISD::EH_SJLJ_SETJMP, DL,
16744 DAG.getVTList(MVT::i32, MVT::Other),
16745 Op.getOperand(0), Op.getOperand(1));
16748 SDValue X86TargetLowering::lowerEH_SJLJ_LONGJMP(SDValue Op,
16749 SelectionDAG &DAG) const {
16751 return DAG.getNode(X86ISD::EH_SJLJ_LONGJMP, DL, MVT::Other,
16752 Op.getOperand(0), Op.getOperand(1));
16755 static SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) {
16756 return Op.getOperand(0);
16759 SDValue X86TargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
16760 SelectionDAG &DAG) const {
16761 SDValue Root = Op.getOperand(0);
16762 SDValue Trmp = Op.getOperand(1); // trampoline
16763 SDValue FPtr = Op.getOperand(2); // nested function
16764 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
16767 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
16768 const TargetRegisterInfo *TRI = DAG.getSubtarget().getRegisterInfo();
16770 if (Subtarget->is64Bit()) {
16771 SDValue OutChains[6];
16773 // Large code-model.
16774 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode.
16775 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode.
16777 const unsigned char N86R10 = TRI->getEncodingValue(X86::R10) & 0x7;
16778 const unsigned char N86R11 = TRI->getEncodingValue(X86::R11) & 0x7;
16780 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
16782 // Load the pointer to the nested function into R11.
16783 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
16784 SDValue Addr = Trmp;
16785 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
16786 Addr, MachinePointerInfo(TrmpAddr),
16789 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
16790 DAG.getConstant(2, MVT::i64));
16791 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr,
16792 MachinePointerInfo(TrmpAddr, 2),
16795 // Load the 'nest' parameter value into R10.
16796 // R10 is specified in X86CallingConv.td
16797 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
16798 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
16799 DAG.getConstant(10, MVT::i64));
16800 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
16801 Addr, MachinePointerInfo(TrmpAddr, 10),
16804 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
16805 DAG.getConstant(12, MVT::i64));
16806 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr,
16807 MachinePointerInfo(TrmpAddr, 12),
16810 // Jump to the nested function.
16811 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
16812 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
16813 DAG.getConstant(20, MVT::i64));
16814 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
16815 Addr, MachinePointerInfo(TrmpAddr, 20),
16818 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
16819 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
16820 DAG.getConstant(22, MVT::i64));
16821 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr,
16822 MachinePointerInfo(TrmpAddr, 22),
16825 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
16827 const Function *Func =
16828 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
16829 CallingConv::ID CC = Func->getCallingConv();
16834 llvm_unreachable("Unsupported calling convention");
16835 case CallingConv::C:
16836 case CallingConv::X86_StdCall: {
16837 // Pass 'nest' parameter in ECX.
16838 // Must be kept in sync with X86CallingConv.td
16839 NestReg = X86::ECX;
16841 // Check that ECX wasn't needed by an 'inreg' parameter.
16842 FunctionType *FTy = Func->getFunctionType();
16843 const AttributeSet &Attrs = Func->getAttributes();
16845 if (!Attrs.isEmpty() && !Func->isVarArg()) {
16846 unsigned InRegCount = 0;
16849 for (FunctionType::param_iterator I = FTy->param_begin(),
16850 E = FTy->param_end(); I != E; ++I, ++Idx)
16851 if (Attrs.hasAttribute(Idx, Attribute::InReg))
16852 // FIXME: should only count parameters that are lowered to integers.
16853 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32;
16855 if (InRegCount > 2) {
16856 report_fatal_error("Nest register in use - reduce number of inreg"
16862 case CallingConv::X86_FastCall:
16863 case CallingConv::X86_ThisCall:
16864 case CallingConv::Fast:
16865 // Pass 'nest' parameter in EAX.
16866 // Must be kept in sync with X86CallingConv.td
16867 NestReg = X86::EAX;
16871 SDValue OutChains[4];
16872 SDValue Addr, Disp;
16874 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
16875 DAG.getConstant(10, MVT::i32));
16876 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
16878 // This is storing the opcode for MOV32ri.
16879 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte.
16880 const unsigned char N86Reg = TRI->getEncodingValue(NestReg) & 0x7;
16881 OutChains[0] = DAG.getStore(Root, dl,
16882 DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
16883 Trmp, MachinePointerInfo(TrmpAddr),
16886 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
16887 DAG.getConstant(1, MVT::i32));
16888 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr,
16889 MachinePointerInfo(TrmpAddr, 1),
16892 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode.
16893 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
16894 DAG.getConstant(5, MVT::i32));
16895 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr,
16896 MachinePointerInfo(TrmpAddr, 5),
16899 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
16900 DAG.getConstant(6, MVT::i32));
16901 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr,
16902 MachinePointerInfo(TrmpAddr, 6),
16905 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
16909 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op,
16910 SelectionDAG &DAG) const {
16912 The rounding mode is in bits 11:10 of FPSR, and has the following
16914 00 Round to nearest
16919 FLT_ROUNDS, on the other hand, expects the following:
16926 To perform the conversion, we do:
16927 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
16930 MachineFunction &MF = DAG.getMachineFunction();
16931 const TargetMachine &TM = MF.getTarget();
16932 const TargetFrameLowering &TFI = *TM.getSubtargetImpl()->getFrameLowering();
16933 unsigned StackAlignment = TFI.getStackAlignment();
16934 MVT VT = Op.getSimpleValueType();
16937 // Save FP Control Word to stack slot
16938 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false);
16939 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
16941 MachineMemOperand *MMO =
16942 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
16943 MachineMemOperand::MOStore, 2, 2);
16945 SDValue Ops[] = { DAG.getEntryNode(), StackSlot };
16946 SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL,
16947 DAG.getVTList(MVT::Other),
16948 Ops, MVT::i16, MMO);
16950 // Load FP Control Word from stack slot
16951 SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot,
16952 MachinePointerInfo(), false, false, false, 0);
16954 // Transform as necessary
16956 DAG.getNode(ISD::SRL, DL, MVT::i16,
16957 DAG.getNode(ISD::AND, DL, MVT::i16,
16958 CWD, DAG.getConstant(0x800, MVT::i16)),
16959 DAG.getConstant(11, MVT::i8));
16961 DAG.getNode(ISD::SRL, DL, MVT::i16,
16962 DAG.getNode(ISD::AND, DL, MVT::i16,
16963 CWD, DAG.getConstant(0x400, MVT::i16)),
16964 DAG.getConstant(9, MVT::i8));
16967 DAG.getNode(ISD::AND, DL, MVT::i16,
16968 DAG.getNode(ISD::ADD, DL, MVT::i16,
16969 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2),
16970 DAG.getConstant(1, MVT::i16)),
16971 DAG.getConstant(3, MVT::i16));
16973 return DAG.getNode((VT.getSizeInBits() < 16 ?
16974 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal);
16977 static SDValue LowerCTLZ(SDValue Op, SelectionDAG &DAG) {
16978 MVT VT = Op.getSimpleValueType();
16980 unsigned NumBits = VT.getSizeInBits();
16983 Op = Op.getOperand(0);
16984 if (VT == MVT::i8) {
16985 // Zero extend to i32 since there is not an i8 bsr.
16987 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
16990 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
16991 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
16992 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
16994 // If src is zero (i.e. bsr sets ZF), returns NumBits.
16997 DAG.getConstant(NumBits+NumBits-1, OpVT),
16998 DAG.getConstant(X86::COND_E, MVT::i8),
17001 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops);
17003 // Finally xor with NumBits-1.
17004 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
17007 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
17011 static SDValue LowerCTLZ_ZERO_UNDEF(SDValue Op, SelectionDAG &DAG) {
17012 MVT VT = Op.getSimpleValueType();
17014 unsigned NumBits = VT.getSizeInBits();
17017 Op = Op.getOperand(0);
17018 if (VT == MVT::i8) {
17019 // Zero extend to i32 since there is not an i8 bsr.
17021 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
17024 // Issue a bsr (scan bits in reverse).
17025 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
17026 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
17028 // And xor with NumBits-1.
17029 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
17032 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
17036 static SDValue LowerCTTZ(SDValue Op, SelectionDAG &DAG) {
17037 MVT VT = Op.getSimpleValueType();
17038 unsigned NumBits = VT.getSizeInBits();
17040 Op = Op.getOperand(0);
17042 // Issue a bsf (scan bits forward) which also sets EFLAGS.
17043 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
17044 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op);
17046 // If src is zero (i.e. bsf sets ZF), returns NumBits.
17049 DAG.getConstant(NumBits, VT),
17050 DAG.getConstant(X86::COND_E, MVT::i8),
17053 return DAG.getNode(X86ISD::CMOV, dl, VT, Ops);
17056 // Lower256IntArith - Break a 256-bit integer operation into two new 128-bit
17057 // ones, and then concatenate the result back.
17058 static SDValue Lower256IntArith(SDValue Op, SelectionDAG &DAG) {
17059 MVT VT = Op.getSimpleValueType();
17061 assert(VT.is256BitVector() && VT.isInteger() &&
17062 "Unsupported value type for operation");
17064 unsigned NumElems = VT.getVectorNumElements();
17067 // Extract the LHS vectors
17068 SDValue LHS = Op.getOperand(0);
17069 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
17070 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
17072 // Extract the RHS vectors
17073 SDValue RHS = Op.getOperand(1);
17074 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
17075 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
17077 MVT EltVT = VT.getVectorElementType();
17078 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
17080 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
17081 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1),
17082 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2));
17085 static SDValue LowerADD(SDValue Op, SelectionDAG &DAG) {
17086 assert(Op.getSimpleValueType().is256BitVector() &&
17087 Op.getSimpleValueType().isInteger() &&
17088 "Only handle AVX 256-bit vector integer operation");
17089 return Lower256IntArith(Op, DAG);
17092 static SDValue LowerSUB(SDValue Op, SelectionDAG &DAG) {
17093 assert(Op.getSimpleValueType().is256BitVector() &&
17094 Op.getSimpleValueType().isInteger() &&
17095 "Only handle AVX 256-bit vector integer operation");
17096 return Lower256IntArith(Op, DAG);
17099 static SDValue LowerMUL(SDValue Op, const X86Subtarget *Subtarget,
17100 SelectionDAG &DAG) {
17102 MVT VT = Op.getSimpleValueType();
17104 // Decompose 256-bit ops into smaller 128-bit ops.
17105 if (VT.is256BitVector() && !Subtarget->hasInt256())
17106 return Lower256IntArith(Op, DAG);
17108 SDValue A = Op.getOperand(0);
17109 SDValue B = Op.getOperand(1);
17111 // Lower v4i32 mul as 2x shuffle, 2x pmuludq, 2x shuffle.
17112 if (VT == MVT::v4i32) {
17113 assert(Subtarget->hasSSE2() && !Subtarget->hasSSE41() &&
17114 "Should not custom lower when pmuldq is available!");
17116 // Extract the odd parts.
17117 static const int UnpackMask[] = { 1, -1, 3, -1 };
17118 SDValue Aodds = DAG.getVectorShuffle(VT, dl, A, A, UnpackMask);
17119 SDValue Bodds = DAG.getVectorShuffle(VT, dl, B, B, UnpackMask);
17121 // Multiply the even parts.
17122 SDValue Evens = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, A, B);
17123 // Now multiply odd parts.
17124 SDValue Odds = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, Aodds, Bodds);
17126 Evens = DAG.getNode(ISD::BITCAST, dl, VT, Evens);
17127 Odds = DAG.getNode(ISD::BITCAST, dl, VT, Odds);
17129 // Merge the two vectors back together with a shuffle. This expands into 2
17131 static const int ShufMask[] = { 0, 4, 2, 6 };
17132 return DAG.getVectorShuffle(VT, dl, Evens, Odds, ShufMask);
17135 assert((VT == MVT::v2i64 || VT == MVT::v4i64 || VT == MVT::v8i64) &&
17136 "Only know how to lower V2I64/V4I64/V8I64 multiply");
17138 // Ahi = psrlqi(a, 32);
17139 // Bhi = psrlqi(b, 32);
17141 // AloBlo = pmuludq(a, b);
17142 // AloBhi = pmuludq(a, Bhi);
17143 // AhiBlo = pmuludq(Ahi, b);
17145 // AloBhi = psllqi(AloBhi, 32);
17146 // AhiBlo = psllqi(AhiBlo, 32);
17147 // return AloBlo + AloBhi + AhiBlo;
17149 SDValue Ahi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, A, 32, DAG);
17150 SDValue Bhi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, B, 32, DAG);
17152 // Bit cast to 32-bit vectors for MULUDQ
17153 EVT MulVT = (VT == MVT::v2i64) ? MVT::v4i32 :
17154 (VT == MVT::v4i64) ? MVT::v8i32 : MVT::v16i32;
17155 A = DAG.getNode(ISD::BITCAST, dl, MulVT, A);
17156 B = DAG.getNode(ISD::BITCAST, dl, MulVT, B);
17157 Ahi = DAG.getNode(ISD::BITCAST, dl, MulVT, Ahi);
17158 Bhi = DAG.getNode(ISD::BITCAST, dl, MulVT, Bhi);
17160 SDValue AloBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, B);
17161 SDValue AloBhi = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, Bhi);
17162 SDValue AhiBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, Ahi, B);
17164 AloBhi = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AloBhi, 32, DAG);
17165 AhiBlo = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AhiBlo, 32, DAG);
17167 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
17168 return DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
17171 SDValue X86TargetLowering::LowerWin64_i128OP(SDValue Op, SelectionDAG &DAG) const {
17172 assert(Subtarget->isTargetWin64() && "Unexpected target");
17173 EVT VT = Op.getValueType();
17174 assert(VT.isInteger() && VT.getSizeInBits() == 128 &&
17175 "Unexpected return type for lowering");
17179 switch (Op->getOpcode()) {
17180 default: llvm_unreachable("Unexpected request for libcall!");
17181 case ISD::SDIV: isSigned = true; LC = RTLIB::SDIV_I128; break;
17182 case ISD::UDIV: isSigned = false; LC = RTLIB::UDIV_I128; break;
17183 case ISD::SREM: isSigned = true; LC = RTLIB::SREM_I128; break;
17184 case ISD::UREM: isSigned = false; LC = RTLIB::UREM_I128; break;
17185 case ISD::SDIVREM: isSigned = true; LC = RTLIB::SDIVREM_I128; break;
17186 case ISD::UDIVREM: isSigned = false; LC = RTLIB::UDIVREM_I128; break;
17190 SDValue InChain = DAG.getEntryNode();
17192 TargetLowering::ArgListTy Args;
17193 TargetLowering::ArgListEntry Entry;
17194 for (unsigned i = 0, e = Op->getNumOperands(); i != e; ++i) {
17195 EVT ArgVT = Op->getOperand(i).getValueType();
17196 assert(ArgVT.isInteger() && ArgVT.getSizeInBits() == 128 &&
17197 "Unexpected argument type for lowering");
17198 SDValue StackPtr = DAG.CreateStackTemporary(ArgVT, 16);
17199 Entry.Node = StackPtr;
17200 InChain = DAG.getStore(InChain, dl, Op->getOperand(i), StackPtr, MachinePointerInfo(),
17202 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
17203 Entry.Ty = PointerType::get(ArgTy,0);
17204 Entry.isSExt = false;
17205 Entry.isZExt = false;
17206 Args.push_back(Entry);
17209 SDValue Callee = DAG.getExternalSymbol(getLibcallName(LC),
17212 TargetLowering::CallLoweringInfo CLI(DAG);
17213 CLI.setDebugLoc(dl).setChain(InChain)
17214 .setCallee(getLibcallCallingConv(LC),
17215 static_cast<EVT>(MVT::v2i64).getTypeForEVT(*DAG.getContext()),
17216 Callee, std::move(Args), 0)
17217 .setInRegister().setSExtResult(isSigned).setZExtResult(!isSigned);
17219 std::pair<SDValue, SDValue> CallInfo = LowerCallTo(CLI);
17220 return DAG.getNode(ISD::BITCAST, dl, VT, CallInfo.first);
17223 static SDValue LowerMUL_LOHI(SDValue Op, const X86Subtarget *Subtarget,
17224 SelectionDAG &DAG) {
17225 SDValue Op0 = Op.getOperand(0), Op1 = Op.getOperand(1);
17226 EVT VT = Op0.getValueType();
17229 assert((VT == MVT::v4i32 && Subtarget->hasSSE2()) ||
17230 (VT == MVT::v8i32 && Subtarget->hasInt256()));
17232 // PMULxD operations multiply each even value (starting at 0) of LHS with
17233 // the related value of RHS and produce a widen result.
17234 // E.g., PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
17235 // => <2 x i64> <ae|cg>
17237 // In other word, to have all the results, we need to perform two PMULxD:
17238 // 1. one with the even values.
17239 // 2. one with the odd values.
17240 // To achieve #2, with need to place the odd values at an even position.
17242 // Place the odd value at an even position (basically, shift all values 1
17243 // step to the left):
17244 const int Mask[] = {1, -1, 3, -1, 5, -1, 7, -1};
17245 // <a|b|c|d> => <b|undef|d|undef>
17246 SDValue Odd0 = DAG.getVectorShuffle(VT, dl, Op0, Op0, Mask);
17247 // <e|f|g|h> => <f|undef|h|undef>
17248 SDValue Odd1 = DAG.getVectorShuffle(VT, dl, Op1, Op1, Mask);
17250 // Emit two multiplies, one for the lower 2 ints and one for the higher 2
17252 MVT MulVT = VT == MVT::v4i32 ? MVT::v2i64 : MVT::v4i64;
17253 bool IsSigned = Op->getOpcode() == ISD::SMUL_LOHI;
17255 (!IsSigned || !Subtarget->hasSSE41()) ? X86ISD::PMULUDQ : X86ISD::PMULDQ;
17256 // PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
17257 // => <2 x i64> <ae|cg>
17258 SDValue Mul1 = DAG.getNode(ISD::BITCAST, dl, VT,
17259 DAG.getNode(Opcode, dl, MulVT, Op0, Op1));
17260 // PMULUDQ <4 x i32> <b|undef|d|undef>, <4 x i32> <f|undef|h|undef>
17261 // => <2 x i64> <bf|dh>
17262 SDValue Mul2 = DAG.getNode(ISD::BITCAST, dl, VT,
17263 DAG.getNode(Opcode, dl, MulVT, Odd0, Odd1));
17265 // Shuffle it back into the right order.
17266 SDValue Highs, Lows;
17267 if (VT == MVT::v8i32) {
17268 const int HighMask[] = {1, 9, 3, 11, 5, 13, 7, 15};
17269 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
17270 const int LowMask[] = {0, 8, 2, 10, 4, 12, 6, 14};
17271 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
17273 const int HighMask[] = {1, 5, 3, 7};
17274 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
17275 const int LowMask[] = {0, 4, 2, 6};
17276 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
17279 // If we have a signed multiply but no PMULDQ fix up the high parts of a
17280 // unsigned multiply.
17281 if (IsSigned && !Subtarget->hasSSE41()) {
17283 DAG.getConstant(31, DAG.getTargetLoweringInfo().getShiftAmountTy(VT));
17284 SDValue T1 = DAG.getNode(ISD::AND, dl, VT,
17285 DAG.getNode(ISD::SRA, dl, VT, Op0, ShAmt), Op1);
17286 SDValue T2 = DAG.getNode(ISD::AND, dl, VT,
17287 DAG.getNode(ISD::SRA, dl, VT, Op1, ShAmt), Op0);
17289 SDValue Fixup = DAG.getNode(ISD::ADD, dl, VT, T1, T2);
17290 Highs = DAG.getNode(ISD::SUB, dl, VT, Highs, Fixup);
17293 // The first result of MUL_LOHI is actually the low value, followed by the
17295 SDValue Ops[] = {Lows, Highs};
17296 return DAG.getMergeValues(Ops, dl);
17299 static SDValue LowerScalarImmediateShift(SDValue Op, SelectionDAG &DAG,
17300 const X86Subtarget *Subtarget) {
17301 MVT VT = Op.getSimpleValueType();
17303 SDValue R = Op.getOperand(0);
17304 SDValue Amt = Op.getOperand(1);
17306 // Optimize shl/srl/sra with constant shift amount.
17307 if (auto *BVAmt = dyn_cast<BuildVectorSDNode>(Amt)) {
17308 if (auto *ShiftConst = BVAmt->getConstantSplatNode()) {
17309 uint64_t ShiftAmt = ShiftConst->getZExtValue();
17311 if (VT == MVT::v2i64 || VT == MVT::v4i32 || VT == MVT::v8i16 ||
17312 (Subtarget->hasInt256() &&
17313 (VT == MVT::v4i64 || VT == MVT::v8i32 || VT == MVT::v16i16)) ||
17314 (Subtarget->hasAVX512() &&
17315 (VT == MVT::v8i64 || VT == MVT::v16i32))) {
17316 if (Op.getOpcode() == ISD::SHL)
17317 return getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, R, ShiftAmt,
17319 if (Op.getOpcode() == ISD::SRL)
17320 return getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, R, ShiftAmt,
17322 if (Op.getOpcode() == ISD::SRA && VT != MVT::v2i64 && VT != MVT::v4i64)
17323 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, R, ShiftAmt,
17327 if (VT == MVT::v16i8) {
17328 if (Op.getOpcode() == ISD::SHL) {
17329 // Make a large shift.
17330 SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl,
17331 MVT::v8i16, R, ShiftAmt,
17333 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
17334 // Zero out the rightmost bits.
17335 SmallVector<SDValue, 16> V(16,
17336 DAG.getConstant(uint8_t(-1U << ShiftAmt),
17338 return DAG.getNode(ISD::AND, dl, VT, SHL,
17339 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
17341 if (Op.getOpcode() == ISD::SRL) {
17342 // Make a large shift.
17343 SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl,
17344 MVT::v8i16, R, ShiftAmt,
17346 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
17347 // Zero out the leftmost bits.
17348 SmallVector<SDValue, 16> V(16,
17349 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
17351 return DAG.getNode(ISD::AND, dl, VT, SRL,
17352 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
17354 if (Op.getOpcode() == ISD::SRA) {
17355 if (ShiftAmt == 7) {
17356 // R s>> 7 === R s< 0
17357 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
17358 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
17361 // R s>> a === ((R u>> a) ^ m) - m
17362 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
17363 SmallVector<SDValue, 16> V(16, DAG.getConstant(128 >> ShiftAmt,
17365 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V);
17366 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
17367 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
17370 llvm_unreachable("Unknown shift opcode.");
17373 if (Subtarget->hasInt256() && VT == MVT::v32i8) {
17374 if (Op.getOpcode() == ISD::SHL) {
17375 // Make a large shift.
17376 SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl,
17377 MVT::v16i16, R, ShiftAmt,
17379 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
17380 // Zero out the rightmost bits.
17381 SmallVector<SDValue, 32> V(32,
17382 DAG.getConstant(uint8_t(-1U << ShiftAmt),
17384 return DAG.getNode(ISD::AND, dl, VT, SHL,
17385 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
17387 if (Op.getOpcode() == ISD::SRL) {
17388 // Make a large shift.
17389 SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl,
17390 MVT::v16i16, R, ShiftAmt,
17392 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
17393 // Zero out the leftmost bits.
17394 SmallVector<SDValue, 32> V(32,
17395 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
17397 return DAG.getNode(ISD::AND, dl, VT, SRL,
17398 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
17400 if (Op.getOpcode() == ISD::SRA) {
17401 if (ShiftAmt == 7) {
17402 // R s>> 7 === R s< 0
17403 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
17404 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
17407 // R s>> a === ((R u>> a) ^ m) - m
17408 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
17409 SmallVector<SDValue, 32> V(32, DAG.getConstant(128 >> ShiftAmt,
17411 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V);
17412 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
17413 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
17416 llvm_unreachable("Unknown shift opcode.");
17421 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
17422 if (!Subtarget->is64Bit() &&
17423 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64)) &&
17424 Amt.getOpcode() == ISD::BITCAST &&
17425 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
17426 Amt = Amt.getOperand(0);
17427 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
17428 VT.getVectorNumElements();
17429 unsigned RatioInLog2 = Log2_32_Ceil(Ratio);
17430 uint64_t ShiftAmt = 0;
17431 for (unsigned i = 0; i != Ratio; ++i) {
17432 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Amt.getOperand(i));
17436 ShiftAmt |= C->getZExtValue() << (i * (1 << (6 - RatioInLog2)));
17438 // Check remaining shift amounts.
17439 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
17440 uint64_t ShAmt = 0;
17441 for (unsigned j = 0; j != Ratio; ++j) {
17442 ConstantSDNode *C =
17443 dyn_cast<ConstantSDNode>(Amt.getOperand(i + j));
17447 ShAmt |= C->getZExtValue() << (j * (1 << (6 - RatioInLog2)));
17449 if (ShAmt != ShiftAmt)
17452 switch (Op.getOpcode()) {
17454 llvm_unreachable("Unknown shift opcode!");
17456 return getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, R, ShiftAmt,
17459 return getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, R, ShiftAmt,
17462 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, R, ShiftAmt,
17470 static SDValue LowerScalarVariableShift(SDValue Op, SelectionDAG &DAG,
17471 const X86Subtarget* Subtarget) {
17472 MVT VT = Op.getSimpleValueType();
17474 SDValue R = Op.getOperand(0);
17475 SDValue Amt = Op.getOperand(1);
17477 if ((VT == MVT::v2i64 && Op.getOpcode() != ISD::SRA) ||
17478 VT == MVT::v4i32 || VT == MVT::v8i16 ||
17479 (Subtarget->hasInt256() &&
17480 ((VT == MVT::v4i64 && Op.getOpcode() != ISD::SRA) ||
17481 VT == MVT::v8i32 || VT == MVT::v16i16)) ||
17482 (Subtarget->hasAVX512() && (VT == MVT::v8i64 || VT == MVT::v16i32))) {
17484 EVT EltVT = VT.getVectorElementType();
17486 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
17487 unsigned NumElts = VT.getVectorNumElements();
17489 for (i = 0; i != NumElts; ++i) {
17490 if (Amt.getOperand(i).getOpcode() == ISD::UNDEF)
17494 for (j = i; j != NumElts; ++j) {
17495 SDValue Arg = Amt.getOperand(j);
17496 if (Arg.getOpcode() == ISD::UNDEF) continue;
17497 if (Arg != Amt.getOperand(i))
17500 if (i != NumElts && j == NumElts)
17501 BaseShAmt = Amt.getOperand(i);
17503 if (Amt.getOpcode() == ISD::EXTRACT_SUBVECTOR)
17504 Amt = Amt.getOperand(0);
17505 if (Amt.getOpcode() == ISD::VECTOR_SHUFFLE &&
17506 cast<ShuffleVectorSDNode>(Amt)->isSplat()) {
17507 SDValue InVec = Amt.getOperand(0);
17508 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
17509 unsigned NumElts = InVec.getValueType().getVectorNumElements();
17511 for (; i != NumElts; ++i) {
17512 SDValue Arg = InVec.getOperand(i);
17513 if (Arg.getOpcode() == ISD::UNDEF) continue;
17517 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
17518 if (ConstantSDNode *C =
17519 dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
17520 unsigned SplatIdx =
17521 cast<ShuffleVectorSDNode>(Amt)->getSplatIndex();
17522 if (C->getZExtValue() == SplatIdx)
17523 BaseShAmt = InVec.getOperand(1);
17526 if (!BaseShAmt.getNode())
17527 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Amt,
17528 DAG.getIntPtrConstant(0));
17532 if (BaseShAmt.getNode()) {
17533 if (EltVT.bitsGT(MVT::i32))
17534 BaseShAmt = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, BaseShAmt);
17535 else if (EltVT.bitsLT(MVT::i32))
17536 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, BaseShAmt);
17538 switch (Op.getOpcode()) {
17540 llvm_unreachable("Unknown shift opcode!");
17542 switch (VT.SimpleTy) {
17543 default: return SDValue();
17552 return getTargetVShiftNode(X86ISD::VSHLI, dl, VT, R, BaseShAmt, DAG);
17555 switch (VT.SimpleTy) {
17556 default: return SDValue();
17563 return getTargetVShiftNode(X86ISD::VSRAI, dl, VT, R, BaseShAmt, DAG);
17566 switch (VT.SimpleTy) {
17567 default: return SDValue();
17576 return getTargetVShiftNode(X86ISD::VSRLI, dl, VT, R, BaseShAmt, DAG);
17582 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
17583 if (!Subtarget->is64Bit() &&
17584 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64) ||
17585 (Subtarget->hasAVX512() && VT == MVT::v8i64)) &&
17586 Amt.getOpcode() == ISD::BITCAST &&
17587 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
17588 Amt = Amt.getOperand(0);
17589 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
17590 VT.getVectorNumElements();
17591 std::vector<SDValue> Vals(Ratio);
17592 for (unsigned i = 0; i != Ratio; ++i)
17593 Vals[i] = Amt.getOperand(i);
17594 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
17595 for (unsigned j = 0; j != Ratio; ++j)
17596 if (Vals[j] != Amt.getOperand(i + j))
17599 switch (Op.getOpcode()) {
17601 llvm_unreachable("Unknown shift opcode!");
17603 return DAG.getNode(X86ISD::VSHL, dl, VT, R, Op.getOperand(1));
17605 return DAG.getNode(X86ISD::VSRL, dl, VT, R, Op.getOperand(1));
17607 return DAG.getNode(X86ISD::VSRA, dl, VT, R, Op.getOperand(1));
17614 static SDValue LowerShift(SDValue Op, const X86Subtarget* Subtarget,
17615 SelectionDAG &DAG) {
17616 MVT VT = Op.getSimpleValueType();
17618 SDValue R = Op.getOperand(0);
17619 SDValue Amt = Op.getOperand(1);
17622 assert(VT.isVector() && "Custom lowering only for vector shifts!");
17623 assert(Subtarget->hasSSE2() && "Only custom lower when we have SSE2!");
17625 V = LowerScalarImmediateShift(Op, DAG, Subtarget);
17629 V = LowerScalarVariableShift(Op, DAG, Subtarget);
17633 if (Subtarget->hasAVX512() && (VT == MVT::v16i32 || VT == MVT::v8i64))
17635 // AVX2 has VPSLLV/VPSRAV/VPSRLV.
17636 if (Subtarget->hasInt256()) {
17637 if (Op.getOpcode() == ISD::SRL &&
17638 (VT == MVT::v2i64 || VT == MVT::v4i32 ||
17639 VT == MVT::v4i64 || VT == MVT::v8i32))
17641 if (Op.getOpcode() == ISD::SHL &&
17642 (VT == MVT::v2i64 || VT == MVT::v4i32 ||
17643 VT == MVT::v4i64 || VT == MVT::v8i32))
17645 if (Op.getOpcode() == ISD::SRA && (VT == MVT::v4i32 || VT == MVT::v8i32))
17649 // If possible, lower this packed shift into a vector multiply instead of
17650 // expanding it into a sequence of scalar shifts.
17651 // Do this only if the vector shift count is a constant build_vector.
17652 if (Op.getOpcode() == ISD::SHL &&
17653 (VT == MVT::v8i16 || VT == MVT::v4i32 ||
17654 (Subtarget->hasInt256() && VT == MVT::v16i16)) &&
17655 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
17656 SmallVector<SDValue, 8> Elts;
17657 EVT SVT = VT.getScalarType();
17658 unsigned SVTBits = SVT.getSizeInBits();
17659 const APInt &One = APInt(SVTBits, 1);
17660 unsigned NumElems = VT.getVectorNumElements();
17662 for (unsigned i=0; i !=NumElems; ++i) {
17663 SDValue Op = Amt->getOperand(i);
17664 if (Op->getOpcode() == ISD::UNDEF) {
17665 Elts.push_back(Op);
17669 ConstantSDNode *ND = cast<ConstantSDNode>(Op);
17670 const APInt &C = APInt(SVTBits, ND->getAPIntValue().getZExtValue());
17671 uint64_t ShAmt = C.getZExtValue();
17672 if (ShAmt >= SVTBits) {
17673 Elts.push_back(DAG.getUNDEF(SVT));
17676 Elts.push_back(DAG.getConstant(One.shl(ShAmt), SVT));
17678 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
17679 return DAG.getNode(ISD::MUL, dl, VT, R, BV);
17682 // Lower SHL with variable shift amount.
17683 if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) {
17684 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(23, VT));
17686 Op = DAG.getNode(ISD::ADD, dl, VT, Op, DAG.getConstant(0x3f800000U, VT));
17687 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, Op);
17688 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op);
17689 return DAG.getNode(ISD::MUL, dl, VT, Op, R);
17692 // If possible, lower this shift as a sequence of two shifts by
17693 // constant plus a MOVSS/MOVSD instead of scalarizing it.
17695 // (v4i32 (srl A, (build_vector < X, Y, Y, Y>)))
17697 // Could be rewritten as:
17698 // (v4i32 (MOVSS (srl A, <Y,Y,Y,Y>), (srl A, <X,X,X,X>)))
17700 // The advantage is that the two shifts from the example would be
17701 // lowered as X86ISD::VSRLI nodes. This would be cheaper than scalarizing
17702 // the vector shift into four scalar shifts plus four pairs of vector
17704 if ((VT == MVT::v8i16 || VT == MVT::v4i32) &&
17705 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
17706 unsigned TargetOpcode = X86ISD::MOVSS;
17707 bool CanBeSimplified;
17708 // The splat value for the first packed shift (the 'X' from the example).
17709 SDValue Amt1 = Amt->getOperand(0);
17710 // The splat value for the second packed shift (the 'Y' from the example).
17711 SDValue Amt2 = (VT == MVT::v4i32) ? Amt->getOperand(1) :
17712 Amt->getOperand(2);
17714 // See if it is possible to replace this node with a sequence of
17715 // two shifts followed by a MOVSS/MOVSD
17716 if (VT == MVT::v4i32) {
17717 // Check if it is legal to use a MOVSS.
17718 CanBeSimplified = Amt2 == Amt->getOperand(2) &&
17719 Amt2 == Amt->getOperand(3);
17720 if (!CanBeSimplified) {
17721 // Otherwise, check if we can still simplify this node using a MOVSD.
17722 CanBeSimplified = Amt1 == Amt->getOperand(1) &&
17723 Amt->getOperand(2) == Amt->getOperand(3);
17724 TargetOpcode = X86ISD::MOVSD;
17725 Amt2 = Amt->getOperand(2);
17728 // Do similar checks for the case where the machine value type
17730 CanBeSimplified = Amt1 == Amt->getOperand(1);
17731 for (unsigned i=3; i != 8 && CanBeSimplified; ++i)
17732 CanBeSimplified = Amt2 == Amt->getOperand(i);
17734 if (!CanBeSimplified) {
17735 TargetOpcode = X86ISD::MOVSD;
17736 CanBeSimplified = true;
17737 Amt2 = Amt->getOperand(4);
17738 for (unsigned i=0; i != 4 && CanBeSimplified; ++i)
17739 CanBeSimplified = Amt1 == Amt->getOperand(i);
17740 for (unsigned j=4; j != 8 && CanBeSimplified; ++j)
17741 CanBeSimplified = Amt2 == Amt->getOperand(j);
17745 if (CanBeSimplified && isa<ConstantSDNode>(Amt1) &&
17746 isa<ConstantSDNode>(Amt2)) {
17747 // Replace this node with two shifts followed by a MOVSS/MOVSD.
17748 EVT CastVT = MVT::v4i32;
17750 DAG.getConstant(cast<ConstantSDNode>(Amt1)->getAPIntValue(), VT);
17751 SDValue Shift1 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat1);
17753 DAG.getConstant(cast<ConstantSDNode>(Amt2)->getAPIntValue(), VT);
17754 SDValue Shift2 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat2);
17755 if (TargetOpcode == X86ISD::MOVSD)
17756 CastVT = MVT::v2i64;
17757 SDValue BitCast1 = DAG.getNode(ISD::BITCAST, dl, CastVT, Shift1);
17758 SDValue BitCast2 = DAG.getNode(ISD::BITCAST, dl, CastVT, Shift2);
17759 SDValue Result = getTargetShuffleNode(TargetOpcode, dl, CastVT, BitCast2,
17761 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
17765 if (VT == MVT::v16i8 && Op->getOpcode() == ISD::SHL) {
17766 assert(Subtarget->hasSSE2() && "Need SSE2 for pslli/pcmpeq.");
17769 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(5, VT));
17770 Op = DAG.getNode(ISD::BITCAST, dl, VT, Op);
17772 // Turn 'a' into a mask suitable for VSELECT
17773 SDValue VSelM = DAG.getConstant(0x80, VT);
17774 SDValue OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
17775 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
17777 SDValue CM1 = DAG.getConstant(0x0f, VT);
17778 SDValue CM2 = DAG.getConstant(0x3f, VT);
17780 // r = VSELECT(r, psllw(r & (char16)15, 4), a);
17781 SDValue M = DAG.getNode(ISD::AND, dl, VT, R, CM1);
17782 M = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, MVT::v8i16, M, 4, DAG);
17783 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
17784 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
17787 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
17788 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
17789 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
17791 // r = VSELECT(r, psllw(r & (char16)63, 2), a);
17792 M = DAG.getNode(ISD::AND, dl, VT, R, CM2);
17793 M = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, MVT::v8i16, M, 2, DAG);
17794 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
17795 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
17798 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
17799 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
17800 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
17802 // return VSELECT(r, r+r, a);
17803 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel,
17804 DAG.getNode(ISD::ADD, dl, VT, R, R), R);
17808 // It's worth extending once and using the v8i32 shifts for 16-bit types, but
17809 // the extra overheads to get from v16i8 to v8i32 make the existing SSE
17810 // solution better.
17811 if (Subtarget->hasInt256() && VT == MVT::v8i16) {
17812 MVT NewVT = VT == MVT::v8i16 ? MVT::v8i32 : MVT::v16i16;
17814 Op.getOpcode() == ISD::SRA ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
17815 R = DAG.getNode(ExtOpc, dl, NewVT, R);
17816 Amt = DAG.getNode(ISD::ANY_EXTEND, dl, NewVT, Amt);
17817 return DAG.getNode(ISD::TRUNCATE, dl, VT,
17818 DAG.getNode(Op.getOpcode(), dl, NewVT, R, Amt));
17821 // Decompose 256-bit shifts into smaller 128-bit shifts.
17822 if (VT.is256BitVector()) {
17823 unsigned NumElems = VT.getVectorNumElements();
17824 MVT EltVT = VT.getVectorElementType();
17825 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
17827 // Extract the two vectors
17828 SDValue V1 = Extract128BitVector(R, 0, DAG, dl);
17829 SDValue V2 = Extract128BitVector(R, NumElems/2, DAG, dl);
17831 // Recreate the shift amount vectors
17832 SDValue Amt1, Amt2;
17833 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
17834 // Constant shift amount
17835 SmallVector<SDValue, 4> Amt1Csts;
17836 SmallVector<SDValue, 4> Amt2Csts;
17837 for (unsigned i = 0; i != NumElems/2; ++i)
17838 Amt1Csts.push_back(Amt->getOperand(i));
17839 for (unsigned i = NumElems/2; i != NumElems; ++i)
17840 Amt2Csts.push_back(Amt->getOperand(i));
17842 Amt1 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt1Csts);
17843 Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt2Csts);
17845 // Variable shift amount
17846 Amt1 = Extract128BitVector(Amt, 0, DAG, dl);
17847 Amt2 = Extract128BitVector(Amt, NumElems/2, DAG, dl);
17850 // Issue new vector shifts for the smaller types
17851 V1 = DAG.getNode(Op.getOpcode(), dl, NewVT, V1, Amt1);
17852 V2 = DAG.getNode(Op.getOpcode(), dl, NewVT, V2, Amt2);
17854 // Concatenate the result back
17855 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, V1, V2);
17861 static SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) {
17862 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
17863 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
17864 // looks for this combo and may remove the "setcc" instruction if the "setcc"
17865 // has only one use.
17866 SDNode *N = Op.getNode();
17867 SDValue LHS = N->getOperand(0);
17868 SDValue RHS = N->getOperand(1);
17869 unsigned BaseOp = 0;
17872 switch (Op.getOpcode()) {
17873 default: llvm_unreachable("Unknown ovf instruction!");
17875 // A subtract of one will be selected as a INC. Note that INC doesn't
17876 // set CF, so we can't do this for UADDO.
17877 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
17879 BaseOp = X86ISD::INC;
17880 Cond = X86::COND_O;
17883 BaseOp = X86ISD::ADD;
17884 Cond = X86::COND_O;
17887 BaseOp = X86ISD::ADD;
17888 Cond = X86::COND_B;
17891 // A subtract of one will be selected as a DEC. Note that DEC doesn't
17892 // set CF, so we can't do this for USUBO.
17893 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
17895 BaseOp = X86ISD::DEC;
17896 Cond = X86::COND_O;
17899 BaseOp = X86ISD::SUB;
17900 Cond = X86::COND_O;
17903 BaseOp = X86ISD::SUB;
17904 Cond = X86::COND_B;
17907 BaseOp = X86ISD::SMUL;
17908 Cond = X86::COND_O;
17910 case ISD::UMULO: { // i64, i8 = umulo lhs, rhs --> i64, i64, i32 umul lhs,rhs
17911 SDVTList VTs = DAG.getVTList(N->getValueType(0), N->getValueType(0),
17913 SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS);
17916 DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
17917 DAG.getConstant(X86::COND_O, MVT::i32),
17918 SDValue(Sum.getNode(), 2));
17920 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
17924 // Also sets EFLAGS.
17925 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
17926 SDValue Sum = DAG.getNode(BaseOp, DL, VTs, LHS, RHS);
17929 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1),
17930 DAG.getConstant(Cond, MVT::i32),
17931 SDValue(Sum.getNode(), 1));
17933 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
17936 // Sign extension of the low part of vector elements. This may be used either
17937 // when sign extend instructions are not available or if the vector element
17938 // sizes already match the sign-extended size. If the vector elements are in
17939 // their pre-extended size and sign extend instructions are available, that will
17940 // be handled by LowerSIGN_EXTEND.
17941 SDValue X86TargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
17942 SelectionDAG &DAG) const {
17944 EVT ExtraVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
17945 MVT VT = Op.getSimpleValueType();
17947 if (!Subtarget->hasSSE2() || !VT.isVector())
17950 unsigned BitsDiff = VT.getScalarType().getSizeInBits() -
17951 ExtraVT.getScalarType().getSizeInBits();
17953 switch (VT.SimpleTy) {
17954 default: return SDValue();
17957 if (!Subtarget->hasFp256())
17959 if (!Subtarget->hasInt256()) {
17960 // needs to be split
17961 unsigned NumElems = VT.getVectorNumElements();
17963 // Extract the LHS vectors
17964 SDValue LHS = Op.getOperand(0);
17965 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
17966 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
17968 MVT EltVT = VT.getVectorElementType();
17969 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
17971 EVT ExtraEltVT = ExtraVT.getVectorElementType();
17972 unsigned ExtraNumElems = ExtraVT.getVectorNumElements();
17973 ExtraVT = EVT::getVectorVT(*DAG.getContext(), ExtraEltVT,
17975 SDValue Extra = DAG.getValueType(ExtraVT);
17977 LHS1 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, Extra);
17978 LHS2 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, Extra);
17980 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, LHS1, LHS2);
17985 SDValue Op0 = Op.getOperand(0);
17987 // This is a sign extension of some low part of vector elements without
17988 // changing the size of the vector elements themselves:
17989 // Shift-Left + Shift-Right-Algebraic.
17990 SDValue Shl = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, Op0,
17992 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, Shl, BitsDiff,
17998 /// Returns true if the operand type is exactly twice the native width, and
17999 /// the corresponding cmpxchg8b or cmpxchg16b instruction is available.
18000 /// Used to know whether to use cmpxchg8/16b when expanding atomic operations
18001 /// (otherwise we leave them alone to become __sync_fetch_and_... calls).
18002 bool X86TargetLowering::needsCmpXchgNb(const Type *MemType) const {
18003 const X86Subtarget &Subtarget =
18004 getTargetMachine().getSubtarget<X86Subtarget>();
18005 unsigned OpWidth = MemType->getPrimitiveSizeInBits();
18008 return !Subtarget.is64Bit(); // FIXME this should be Subtarget.hasCmpxchg8b
18009 else if (OpWidth == 128)
18010 return Subtarget.hasCmpxchg16b();
18015 bool X86TargetLowering::shouldExpandAtomicStoreInIR(StoreInst *SI) const {
18016 return needsCmpXchgNb(SI->getValueOperand()->getType());
18019 // Note: this turns large loads into lock cmpxchg8b/16b.
18020 // FIXME: On 32 bits x86, fild/movq might be faster than lock cmpxchg8b.
18021 bool X86TargetLowering::shouldExpandAtomicLoadInIR(LoadInst *LI) const {
18022 auto PTy = cast<PointerType>(LI->getPointerOperand()->getType());
18023 return needsCmpXchgNb(PTy->getElementType());
18026 bool X86TargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const {
18027 const X86Subtarget &Subtarget =
18028 getTargetMachine().getSubtarget<X86Subtarget>();
18029 unsigned NativeWidth = Subtarget.is64Bit() ? 64 : 32;
18030 const Type *MemType = AI->getType();
18032 // If the operand is too big, we must see if cmpxchg8/16b is available
18033 // and default to library calls otherwise.
18034 if (MemType->getPrimitiveSizeInBits() > NativeWidth)
18035 return needsCmpXchgNb(MemType);
18037 AtomicRMWInst::BinOp Op = AI->getOperation();
18040 llvm_unreachable("Unknown atomic operation");
18041 case AtomicRMWInst::Xchg:
18042 case AtomicRMWInst::Add:
18043 case AtomicRMWInst::Sub:
18044 // It's better to use xadd, xsub or xchg for these in all cases.
18046 case AtomicRMWInst::Or:
18047 case AtomicRMWInst::And:
18048 case AtomicRMWInst::Xor:
18049 // If the atomicrmw's result isn't actually used, we can just add a "lock"
18050 // prefix to a normal instruction for these operations.
18051 return !AI->use_empty();
18052 case AtomicRMWInst::Nand:
18053 case AtomicRMWInst::Max:
18054 case AtomicRMWInst::Min:
18055 case AtomicRMWInst::UMax:
18056 case AtomicRMWInst::UMin:
18057 // These always require a non-trivial set of data operations on x86. We must
18058 // use a cmpxchg loop.
18063 static bool hasMFENCE(const X86Subtarget& Subtarget) {
18064 // Use mfence if we have SSE2 or we're on x86-64 (even if we asked for
18065 // no-sse2). There isn't any reason to disable it if the target processor
18067 return Subtarget.hasSSE2() || Subtarget.is64Bit();
18071 X86TargetLowering::lowerIdempotentRMWIntoFencedLoad(AtomicRMWInst *AI) const {
18072 const X86Subtarget &Subtarget =
18073 getTargetMachine().getSubtarget<X86Subtarget>();
18074 unsigned NativeWidth = Subtarget.is64Bit() ? 64 : 32;
18075 const Type *MemType = AI->getType();
18076 // Accesses larger than the native width are turned into cmpxchg/libcalls, so
18077 // there is no benefit in turning such RMWs into loads, and it is actually
18078 // harmful as it introduces a mfence.
18079 if (MemType->getPrimitiveSizeInBits() > NativeWidth)
18082 auto Builder = IRBuilder<>(AI);
18083 Module *M = Builder.GetInsertBlock()->getParent()->getParent();
18084 auto SynchScope = AI->getSynchScope();
18085 // We must restrict the ordering to avoid generating loads with Release or
18086 // ReleaseAcquire orderings.
18087 auto Order = AtomicCmpXchgInst::getStrongestFailureOrdering(AI->getOrdering());
18088 auto Ptr = AI->getPointerOperand();
18090 // Before the load we need a fence. Here is an example lifted from
18091 // http://www.hpl.hp.com/techreports/2012/HPL-2012-68.pdf showing why a fence
18094 // x.store(1, relaxed);
18095 // r1 = y.fetch_add(0, release);
18097 // y.fetch_add(42, acquire);
18098 // r2 = x.load(relaxed);
18099 // r1 = r2 = 0 is impossible, but becomes possible if the idempotent rmw is
18100 // lowered to just a load without a fence. A mfence flushes the store buffer,
18101 // making the optimization clearly correct.
18102 // FIXME: it is required if isAtLeastRelease(Order) but it is not clear
18103 // otherwise, we might be able to be more agressive on relaxed idempotent
18104 // rmw. In practice, they do not look useful, so we don't try to be
18105 // especially clever.
18106 if (SynchScope == SingleThread) {
18107 // FIXME: we could just insert an X86ISD::MEMBARRIER here, except we are at
18108 // the IR level, so we must wrap it in an intrinsic.
18110 } else if (hasMFENCE(Subtarget)) {
18111 Function *MFence = llvm::Intrinsic::getDeclaration(M,
18112 Intrinsic::x86_sse2_mfence);
18113 Builder.CreateCall(MFence);
18115 // FIXME: it might make sense to use a locked operation here but on a
18116 // different cache-line to prevent cache-line bouncing. In practice it
18117 // is probably a small win, and x86 processors without mfence are rare
18118 // enough that we do not bother.
18122 // Finally we can emit the atomic load.
18123 LoadInst *Loaded = Builder.CreateAlignedLoad(Ptr,
18124 AI->getType()->getPrimitiveSizeInBits());
18125 Loaded->setAtomic(Order, SynchScope);
18126 AI->replaceAllUsesWith(Loaded);
18127 AI->eraseFromParent();
18131 static SDValue LowerATOMIC_FENCE(SDValue Op, const X86Subtarget *Subtarget,
18132 SelectionDAG &DAG) {
18134 AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>(
18135 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue());
18136 SynchronizationScope FenceScope = static_cast<SynchronizationScope>(
18137 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
18139 // The only fence that needs an instruction is a sequentially-consistent
18140 // cross-thread fence.
18141 if (FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread) {
18142 if (hasMFENCE(*Subtarget))
18143 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
18145 SDValue Chain = Op.getOperand(0);
18146 SDValue Zero = DAG.getConstant(0, MVT::i32);
18148 DAG.getRegister(X86::ESP, MVT::i32), // Base
18149 DAG.getTargetConstant(1, MVT::i8), // Scale
18150 DAG.getRegister(0, MVT::i32), // Index
18151 DAG.getTargetConstant(0, MVT::i32), // Disp
18152 DAG.getRegister(0, MVT::i32), // Segment.
18156 SDNode *Res = DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops);
18157 return SDValue(Res, 0);
18160 // MEMBARRIER is a compiler barrier; it codegens to a no-op.
18161 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
18164 static SDValue LowerCMP_SWAP(SDValue Op, const X86Subtarget *Subtarget,
18165 SelectionDAG &DAG) {
18166 MVT T = Op.getSimpleValueType();
18170 switch(T.SimpleTy) {
18171 default: llvm_unreachable("Invalid value type!");
18172 case MVT::i8: Reg = X86::AL; size = 1; break;
18173 case MVT::i16: Reg = X86::AX; size = 2; break;
18174 case MVT::i32: Reg = X86::EAX; size = 4; break;
18176 assert(Subtarget->is64Bit() && "Node not type legal!");
18177 Reg = X86::RAX; size = 8;
18180 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg,
18181 Op.getOperand(2), SDValue());
18182 SDValue Ops[] = { cpIn.getValue(0),
18185 DAG.getTargetConstant(size, MVT::i8),
18186 cpIn.getValue(1) };
18187 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
18188 MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand();
18189 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys,
18193 DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1));
18194 SDValue EFLAGS = DAG.getCopyFromReg(cpOut.getValue(1), DL, X86::EFLAGS,
18195 MVT::i32, cpOut.getValue(2));
18196 SDValue Success = DAG.getNode(X86ISD::SETCC, DL, Op->getValueType(1),
18197 DAG.getConstant(X86::COND_E, MVT::i8), EFLAGS);
18199 DAG.ReplaceAllUsesOfValueWith(Op.getValue(0), cpOut);
18200 DAG.ReplaceAllUsesOfValueWith(Op.getValue(1), Success);
18201 DAG.ReplaceAllUsesOfValueWith(Op.getValue(2), EFLAGS.getValue(1));
18205 static SDValue LowerBITCAST(SDValue Op, const X86Subtarget *Subtarget,
18206 SelectionDAG &DAG) {
18207 MVT SrcVT = Op.getOperand(0).getSimpleValueType();
18208 MVT DstVT = Op.getSimpleValueType();
18210 if (SrcVT == MVT::v2i32 || SrcVT == MVT::v4i16 || SrcVT == MVT::v8i8) {
18211 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
18212 if (DstVT != MVT::f64)
18213 // This conversion needs to be expanded.
18216 SDValue InVec = Op->getOperand(0);
18218 unsigned NumElts = SrcVT.getVectorNumElements();
18219 EVT SVT = SrcVT.getVectorElementType();
18221 // Widen the vector in input in the case of MVT::v2i32.
18222 // Example: from MVT::v2i32 to MVT::v4i32.
18223 SmallVector<SDValue, 16> Elts;
18224 for (unsigned i = 0, e = NumElts; i != e; ++i)
18225 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT, InVec,
18226 DAG.getIntPtrConstant(i)));
18228 // Explicitly mark the extra elements as Undef.
18229 SDValue Undef = DAG.getUNDEF(SVT);
18230 for (unsigned i = NumElts, e = NumElts * 2; i != e; ++i)
18231 Elts.push_back(Undef);
18233 EVT NewVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
18234 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Elts);
18235 SDValue ToV2F64 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, BV);
18236 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, ToV2F64,
18237 DAG.getIntPtrConstant(0));
18240 assert(Subtarget->is64Bit() && !Subtarget->hasSSE2() &&
18241 Subtarget->hasMMX() && "Unexpected custom BITCAST");
18242 assert((DstVT == MVT::i64 ||
18243 (DstVT.isVector() && DstVT.getSizeInBits()==64)) &&
18244 "Unexpected custom BITCAST");
18245 // i64 <=> MMX conversions are Legal.
18246 if (SrcVT==MVT::i64 && DstVT.isVector())
18248 if (DstVT==MVT::i64 && SrcVT.isVector())
18250 // MMX <=> MMX conversions are Legal.
18251 if (SrcVT.isVector() && DstVT.isVector())
18253 // All other conversions need to be expanded.
18257 static SDValue LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) {
18258 SDNode *Node = Op.getNode();
18260 EVT T = Node->getValueType(0);
18261 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
18262 DAG.getConstant(0, T), Node->getOperand(2));
18263 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
18264 cast<AtomicSDNode>(Node)->getMemoryVT(),
18265 Node->getOperand(0),
18266 Node->getOperand(1), negOp,
18267 cast<AtomicSDNode>(Node)->getMemOperand(),
18268 cast<AtomicSDNode>(Node)->getOrdering(),
18269 cast<AtomicSDNode>(Node)->getSynchScope());
18272 static SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) {
18273 SDNode *Node = Op.getNode();
18275 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
18277 // Convert seq_cst store -> xchg
18278 // Convert wide store -> swap (-> cmpxchg8b/cmpxchg16b)
18279 // FIXME: On 32-bit, store -> fist or movq would be more efficient
18280 // (The only way to get a 16-byte store is cmpxchg16b)
18281 // FIXME: 16-byte ATOMIC_SWAP isn't actually hooked up at the moment.
18282 if (cast<AtomicSDNode>(Node)->getOrdering() == SequentiallyConsistent ||
18283 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
18284 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
18285 cast<AtomicSDNode>(Node)->getMemoryVT(),
18286 Node->getOperand(0),
18287 Node->getOperand(1), Node->getOperand(2),
18288 cast<AtomicSDNode>(Node)->getMemOperand(),
18289 cast<AtomicSDNode>(Node)->getOrdering(),
18290 cast<AtomicSDNode>(Node)->getSynchScope());
18291 return Swap.getValue(1);
18293 // Other atomic stores have a simple pattern.
18297 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
18298 EVT VT = Op.getNode()->getSimpleValueType(0);
18300 // Let legalize expand this if it isn't a legal type yet.
18301 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
18304 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
18307 bool ExtraOp = false;
18308 switch (Op.getOpcode()) {
18309 default: llvm_unreachable("Invalid code");
18310 case ISD::ADDC: Opc = X86ISD::ADD; break;
18311 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break;
18312 case ISD::SUBC: Opc = X86ISD::SUB; break;
18313 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break;
18317 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
18319 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
18320 Op.getOperand(1), Op.getOperand(2));
18323 static SDValue LowerFSINCOS(SDValue Op, const X86Subtarget *Subtarget,
18324 SelectionDAG &DAG) {
18325 assert(Subtarget->isTargetDarwin() && Subtarget->is64Bit());
18327 // For MacOSX, we want to call an alternative entry point: __sincos_stret,
18328 // which returns the values as { float, float } (in XMM0) or
18329 // { double, double } (which is returned in XMM0, XMM1).
18331 SDValue Arg = Op.getOperand(0);
18332 EVT ArgVT = Arg.getValueType();
18333 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
18335 TargetLowering::ArgListTy Args;
18336 TargetLowering::ArgListEntry Entry;
18340 Entry.isSExt = false;
18341 Entry.isZExt = false;
18342 Args.push_back(Entry);
18344 bool isF64 = ArgVT == MVT::f64;
18345 // Only optimize x86_64 for now. i386 is a bit messy. For f32,
18346 // the small struct {f32, f32} is returned in (eax, edx). For f64,
18347 // the results are returned via SRet in memory.
18348 const char *LibcallName = isF64 ? "__sincos_stret" : "__sincosf_stret";
18349 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
18350 SDValue Callee = DAG.getExternalSymbol(LibcallName, TLI.getPointerTy());
18352 Type *RetTy = isF64
18353 ? (Type*)StructType::get(ArgTy, ArgTy, NULL)
18354 : (Type*)VectorType::get(ArgTy, 4);
18356 TargetLowering::CallLoweringInfo CLI(DAG);
18357 CLI.setDebugLoc(dl).setChain(DAG.getEntryNode())
18358 .setCallee(CallingConv::C, RetTy, Callee, std::move(Args), 0);
18360 std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI);
18363 // Returned in xmm0 and xmm1.
18364 return CallResult.first;
18366 // Returned in bits 0:31 and 32:64 xmm0.
18367 SDValue SinVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
18368 CallResult.first, DAG.getIntPtrConstant(0));
18369 SDValue CosVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
18370 CallResult.first, DAG.getIntPtrConstant(1));
18371 SDVTList Tys = DAG.getVTList(ArgVT, ArgVT);
18372 return DAG.getNode(ISD::MERGE_VALUES, dl, Tys, SinVal, CosVal);
18375 /// LowerOperation - Provide custom lowering hooks for some operations.
18377 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
18378 switch (Op.getOpcode()) {
18379 default: llvm_unreachable("Should not custom lower this!");
18380 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op,DAG);
18381 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, Subtarget, DAG);
18382 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS:
18383 return LowerCMP_SWAP(Op, Subtarget, DAG);
18384 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
18385 case ISD::ATOMIC_STORE: return LowerATOMIC_STORE(Op,DAG);
18386 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
18387 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
18388 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
18389 case ISD::VSELECT: return LowerVSELECT(Op, DAG);
18390 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
18391 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
18392 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op,Subtarget,DAG);
18393 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, Subtarget,DAG);
18394 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
18395 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
18396 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
18397 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
18398 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
18399 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
18400 case ISD::SHL_PARTS:
18401 case ISD::SRA_PARTS:
18402 case ISD::SRL_PARTS: return LowerShiftParts(Op, DAG);
18403 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
18404 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
18405 case ISD::TRUNCATE: return LowerTRUNCATE(Op, DAG);
18406 case ISD::ZERO_EXTEND: return LowerZERO_EXTEND(Op, Subtarget, DAG);
18407 case ISD::SIGN_EXTEND: return LowerSIGN_EXTEND(Op, Subtarget, DAG);
18408 case ISD::ANY_EXTEND: return LowerANY_EXTEND(Op, Subtarget, DAG);
18409 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
18410 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
18411 case ISD::FP_EXTEND: return LowerFP_EXTEND(Op, DAG);
18412 case ISD::LOAD: return LowerExtendedLoad(Op, Subtarget, DAG);
18414 case ISD::FNEG: return LowerFABSorFNEG(Op, DAG);
18415 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
18416 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG);
18417 case ISD::SETCC: return LowerSETCC(Op, DAG);
18418 case ISD::SELECT: return LowerSELECT(Op, DAG);
18419 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
18420 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
18421 case ISD::VASTART: return LowerVASTART(Op, DAG);
18422 case ISD::VAARG: return LowerVAARG(Op, DAG);
18423 case ISD::VACOPY: return LowerVACOPY(Op, Subtarget, DAG);
18424 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
18425 case ISD::INTRINSIC_VOID:
18426 case ISD::INTRINSIC_W_CHAIN: return LowerINTRINSIC_W_CHAIN(Op, Subtarget, DAG);
18427 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
18428 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
18429 case ISD::FRAME_TO_ARGS_OFFSET:
18430 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
18431 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
18432 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
18433 case ISD::EH_SJLJ_SETJMP: return lowerEH_SJLJ_SETJMP(Op, DAG);
18434 case ISD::EH_SJLJ_LONGJMP: return lowerEH_SJLJ_LONGJMP(Op, DAG);
18435 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
18436 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
18437 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
18438 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
18439 case ISD::CTLZ_ZERO_UNDEF: return LowerCTLZ_ZERO_UNDEF(Op, DAG);
18440 case ISD::CTTZ: return LowerCTTZ(Op, DAG);
18441 case ISD::MUL: return LowerMUL(Op, Subtarget, DAG);
18442 case ISD::UMUL_LOHI:
18443 case ISD::SMUL_LOHI: return LowerMUL_LOHI(Op, Subtarget, DAG);
18446 case ISD::SHL: return LowerShift(Op, Subtarget, DAG);
18452 case ISD::UMULO: return LowerXALUO(Op, DAG);
18453 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, Subtarget,DAG);
18454 case ISD::BITCAST: return LowerBITCAST(Op, Subtarget, DAG);
18458 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
18459 case ISD::ADD: return LowerADD(Op, DAG);
18460 case ISD::SUB: return LowerSUB(Op, DAG);
18461 case ISD::FSINCOS: return LowerFSINCOS(Op, Subtarget, DAG);
18465 /// ReplaceNodeResults - Replace a node with an illegal result type
18466 /// with a new node built out of custom code.
18467 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
18468 SmallVectorImpl<SDValue>&Results,
18469 SelectionDAG &DAG) const {
18471 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
18472 switch (N->getOpcode()) {
18474 llvm_unreachable("Do not know how to custom type legalize this operation!");
18475 case ISD::SIGN_EXTEND_INREG:
18480 // We don't want to expand or promote these.
18487 case ISD::UDIVREM: {
18488 SDValue V = LowerWin64_i128OP(SDValue(N,0), DAG);
18489 Results.push_back(V);
18492 case ISD::FP_TO_SINT:
18493 case ISD::FP_TO_UINT: {
18494 bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT;
18496 if (!IsSigned && !isIntegerTypeFTOL(SDValue(N, 0).getValueType()))
18499 std::pair<SDValue,SDValue> Vals =
18500 FP_TO_INTHelper(SDValue(N, 0), DAG, IsSigned, /*IsReplace=*/ true);
18501 SDValue FIST = Vals.first, StackSlot = Vals.second;
18502 if (FIST.getNode()) {
18503 EVT VT = N->getValueType(0);
18504 // Return a load from the stack slot.
18505 if (StackSlot.getNode())
18506 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot,
18507 MachinePointerInfo(),
18508 false, false, false, 0));
18510 Results.push_back(FIST);
18514 case ISD::UINT_TO_FP: {
18515 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
18516 if (N->getOperand(0).getValueType() != MVT::v2i32 ||
18517 N->getValueType(0) != MVT::v2f32)
18519 SDValue ZExtIn = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v2i64,
18521 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
18523 SDValue VBias = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2f64, Bias, Bias);
18524 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64, ZExtIn,
18525 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, VBias));
18526 Or = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or);
18527 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, Or, VBias);
18528 Results.push_back(DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, Sub));
18531 case ISD::FP_ROUND: {
18532 if (!TLI.isTypeLegal(N->getOperand(0).getValueType()))
18534 SDValue V = DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, N->getOperand(0));
18535 Results.push_back(V);
18538 case ISD::INTRINSIC_W_CHAIN: {
18539 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
18541 default : llvm_unreachable("Do not know how to custom type "
18542 "legalize this intrinsic operation!");
18543 case Intrinsic::x86_rdtsc:
18544 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
18546 case Intrinsic::x86_rdtscp:
18547 return getReadTimeStampCounter(N, dl, X86ISD::RDTSCP_DAG, DAG, Subtarget,
18549 case Intrinsic::x86_rdpmc:
18550 return getReadPerformanceCounter(N, dl, DAG, Subtarget, Results);
18553 case ISD::READCYCLECOUNTER: {
18554 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
18557 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS: {
18558 EVT T = N->getValueType(0);
18559 assert((T == MVT::i64 || T == MVT::i128) && "can only expand cmpxchg pair");
18560 bool Regs64bit = T == MVT::i128;
18561 EVT HalfT = Regs64bit ? MVT::i64 : MVT::i32;
18562 SDValue cpInL, cpInH;
18563 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
18564 DAG.getConstant(0, HalfT));
18565 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
18566 DAG.getConstant(1, HalfT));
18567 cpInL = DAG.getCopyToReg(N->getOperand(0), dl,
18568 Regs64bit ? X86::RAX : X86::EAX,
18570 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl,
18571 Regs64bit ? X86::RDX : X86::EDX,
18572 cpInH, cpInL.getValue(1));
18573 SDValue swapInL, swapInH;
18574 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
18575 DAG.getConstant(0, HalfT));
18576 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
18577 DAG.getConstant(1, HalfT));
18578 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl,
18579 Regs64bit ? X86::RBX : X86::EBX,
18580 swapInL, cpInH.getValue(1));
18581 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl,
18582 Regs64bit ? X86::RCX : X86::ECX,
18583 swapInH, swapInL.getValue(1));
18584 SDValue Ops[] = { swapInH.getValue(0),
18586 swapInH.getValue(1) };
18587 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
18588 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand();
18589 unsigned Opcode = Regs64bit ? X86ISD::LCMPXCHG16_DAG :
18590 X86ISD::LCMPXCHG8_DAG;
18591 SDValue Result = DAG.getMemIntrinsicNode(Opcode, dl, Tys, Ops, T, MMO);
18592 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl,
18593 Regs64bit ? X86::RAX : X86::EAX,
18594 HalfT, Result.getValue(1));
18595 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl,
18596 Regs64bit ? X86::RDX : X86::EDX,
18597 HalfT, cpOutL.getValue(2));
18598 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
18600 SDValue EFLAGS = DAG.getCopyFromReg(cpOutH.getValue(1), dl, X86::EFLAGS,
18601 MVT::i32, cpOutH.getValue(2));
18603 DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
18604 DAG.getConstant(X86::COND_E, MVT::i8), EFLAGS);
18605 Success = DAG.getZExtOrTrunc(Success, dl, N->getValueType(1));
18607 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, T, OpsF));
18608 Results.push_back(Success);
18609 Results.push_back(EFLAGS.getValue(1));
18612 case ISD::ATOMIC_SWAP:
18613 case ISD::ATOMIC_LOAD_ADD:
18614 case ISD::ATOMIC_LOAD_SUB:
18615 case ISD::ATOMIC_LOAD_AND:
18616 case ISD::ATOMIC_LOAD_OR:
18617 case ISD::ATOMIC_LOAD_XOR:
18618 case ISD::ATOMIC_LOAD_NAND:
18619 case ISD::ATOMIC_LOAD_MIN:
18620 case ISD::ATOMIC_LOAD_MAX:
18621 case ISD::ATOMIC_LOAD_UMIN:
18622 case ISD::ATOMIC_LOAD_UMAX:
18623 case ISD::ATOMIC_LOAD: {
18624 // Delegate to generic TypeLegalization. Situations we can really handle
18625 // should have already been dealt with by AtomicExpandPass.cpp.
18628 case ISD::BITCAST: {
18629 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
18630 EVT DstVT = N->getValueType(0);
18631 EVT SrcVT = N->getOperand(0)->getValueType(0);
18633 if (SrcVT != MVT::f64 ||
18634 (DstVT != MVT::v2i32 && DstVT != MVT::v4i16 && DstVT != MVT::v8i8))
18637 unsigned NumElts = DstVT.getVectorNumElements();
18638 EVT SVT = DstVT.getVectorElementType();
18639 EVT WiderVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
18640 SDValue Expanded = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
18641 MVT::v2f64, N->getOperand(0));
18642 SDValue ToVecInt = DAG.getNode(ISD::BITCAST, dl, WiderVT, Expanded);
18644 if (ExperimentalVectorWideningLegalization) {
18645 // If we are legalizing vectors by widening, we already have the desired
18646 // legal vector type, just return it.
18647 Results.push_back(ToVecInt);
18651 SmallVector<SDValue, 8> Elts;
18652 for (unsigned i = 0, e = NumElts; i != e; ++i)
18653 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT,
18654 ToVecInt, DAG.getIntPtrConstant(i)));
18656 Results.push_back(DAG.getNode(ISD::BUILD_VECTOR, dl, DstVT, Elts));
18661 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
18663 default: return nullptr;
18664 case X86ISD::BSF: return "X86ISD::BSF";
18665 case X86ISD::BSR: return "X86ISD::BSR";
18666 case X86ISD::SHLD: return "X86ISD::SHLD";
18667 case X86ISD::SHRD: return "X86ISD::SHRD";
18668 case X86ISD::FAND: return "X86ISD::FAND";
18669 case X86ISD::FANDN: return "X86ISD::FANDN";
18670 case X86ISD::FOR: return "X86ISD::FOR";
18671 case X86ISD::FXOR: return "X86ISD::FXOR";
18672 case X86ISD::FSRL: return "X86ISD::FSRL";
18673 case X86ISD::FILD: return "X86ISD::FILD";
18674 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
18675 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
18676 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
18677 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
18678 case X86ISD::FLD: return "X86ISD::FLD";
18679 case X86ISD::FST: return "X86ISD::FST";
18680 case X86ISD::CALL: return "X86ISD::CALL";
18681 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
18682 case X86ISD::RDTSCP_DAG: return "X86ISD::RDTSCP_DAG";
18683 case X86ISD::RDPMC_DAG: return "X86ISD::RDPMC_DAG";
18684 case X86ISD::BT: return "X86ISD::BT";
18685 case X86ISD::CMP: return "X86ISD::CMP";
18686 case X86ISD::COMI: return "X86ISD::COMI";
18687 case X86ISD::UCOMI: return "X86ISD::UCOMI";
18688 case X86ISD::CMPM: return "X86ISD::CMPM";
18689 case X86ISD::CMPMU: return "X86ISD::CMPMU";
18690 case X86ISD::SETCC: return "X86ISD::SETCC";
18691 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY";
18692 case X86ISD::FSETCC: return "X86ISD::FSETCC";
18693 case X86ISD::CMOV: return "X86ISD::CMOV";
18694 case X86ISD::BRCOND: return "X86ISD::BRCOND";
18695 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
18696 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
18697 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
18698 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
18699 case X86ISD::Wrapper: return "X86ISD::Wrapper";
18700 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
18701 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
18702 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
18703 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
18704 case X86ISD::PINSRB: return "X86ISD::PINSRB";
18705 case X86ISD::PINSRW: return "X86ISD::PINSRW";
18706 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
18707 case X86ISD::ANDNP: return "X86ISD::ANDNP";
18708 case X86ISD::PSIGN: return "X86ISD::PSIGN";
18709 case X86ISD::BLENDI: return "X86ISD::BLENDI";
18710 case X86ISD::SUBUS: return "X86ISD::SUBUS";
18711 case X86ISD::HADD: return "X86ISD::HADD";
18712 case X86ISD::HSUB: return "X86ISD::HSUB";
18713 case X86ISD::FHADD: return "X86ISD::FHADD";
18714 case X86ISD::FHSUB: return "X86ISD::FHSUB";
18715 case X86ISD::UMAX: return "X86ISD::UMAX";
18716 case X86ISD::UMIN: return "X86ISD::UMIN";
18717 case X86ISD::SMAX: return "X86ISD::SMAX";
18718 case X86ISD::SMIN: return "X86ISD::SMIN";
18719 case X86ISD::FMAX: return "X86ISD::FMAX";
18720 case X86ISD::FMIN: return "X86ISD::FMIN";
18721 case X86ISD::FMAXC: return "X86ISD::FMAXC";
18722 case X86ISD::FMINC: return "X86ISD::FMINC";
18723 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
18724 case X86ISD::FRCP: return "X86ISD::FRCP";
18725 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
18726 case X86ISD::TLSBASEADDR: return "X86ISD::TLSBASEADDR";
18727 case X86ISD::TLSCALL: return "X86ISD::TLSCALL";
18728 case X86ISD::EH_SJLJ_SETJMP: return "X86ISD::EH_SJLJ_SETJMP";
18729 case X86ISD::EH_SJLJ_LONGJMP: return "X86ISD::EH_SJLJ_LONGJMP";
18730 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
18731 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
18732 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
18733 case X86ISD::FNSTSW16r: return "X86ISD::FNSTSW16r";
18734 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
18735 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
18736 case X86ISD::LCMPXCHG16_DAG: return "X86ISD::LCMPXCHG16_DAG";
18737 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
18738 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
18739 case X86ISD::VZEXT: return "X86ISD::VZEXT";
18740 case X86ISD::VSEXT: return "X86ISD::VSEXT";
18741 case X86ISD::VTRUNC: return "X86ISD::VTRUNC";
18742 case X86ISD::VTRUNCM: return "X86ISD::VTRUNCM";
18743 case X86ISD::VINSERT: return "X86ISD::VINSERT";
18744 case X86ISD::VFPEXT: return "X86ISD::VFPEXT";
18745 case X86ISD::VFPROUND: return "X86ISD::VFPROUND";
18746 case X86ISD::VSHLDQ: return "X86ISD::VSHLDQ";
18747 case X86ISD::VSRLDQ: return "X86ISD::VSRLDQ";
18748 case X86ISD::VSHL: return "X86ISD::VSHL";
18749 case X86ISD::VSRL: return "X86ISD::VSRL";
18750 case X86ISD::VSRA: return "X86ISD::VSRA";
18751 case X86ISD::VSHLI: return "X86ISD::VSHLI";
18752 case X86ISD::VSRLI: return "X86ISD::VSRLI";
18753 case X86ISD::VSRAI: return "X86ISD::VSRAI";
18754 case X86ISD::CMPP: return "X86ISD::CMPP";
18755 case X86ISD::PCMPEQ: return "X86ISD::PCMPEQ";
18756 case X86ISD::PCMPGT: return "X86ISD::PCMPGT";
18757 case X86ISD::PCMPEQM: return "X86ISD::PCMPEQM";
18758 case X86ISD::PCMPGTM: return "X86ISD::PCMPGTM";
18759 case X86ISD::ADD: return "X86ISD::ADD";
18760 case X86ISD::SUB: return "X86ISD::SUB";
18761 case X86ISD::ADC: return "X86ISD::ADC";
18762 case X86ISD::SBB: return "X86ISD::SBB";
18763 case X86ISD::SMUL: return "X86ISD::SMUL";
18764 case X86ISD::UMUL: return "X86ISD::UMUL";
18765 case X86ISD::INC: return "X86ISD::INC";
18766 case X86ISD::DEC: return "X86ISD::DEC";
18767 case X86ISD::OR: return "X86ISD::OR";
18768 case X86ISD::XOR: return "X86ISD::XOR";
18769 case X86ISD::AND: return "X86ISD::AND";
18770 case X86ISD::BEXTR: return "X86ISD::BEXTR";
18771 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
18772 case X86ISD::PTEST: return "X86ISD::PTEST";
18773 case X86ISD::TESTP: return "X86ISD::TESTP";
18774 case X86ISD::TESTM: return "X86ISD::TESTM";
18775 case X86ISD::TESTNM: return "X86ISD::TESTNM";
18776 case X86ISD::KORTEST: return "X86ISD::KORTEST";
18777 case X86ISD::PACKSS: return "X86ISD::PACKSS";
18778 case X86ISD::PACKUS: return "X86ISD::PACKUS";
18779 case X86ISD::PALIGNR: return "X86ISD::PALIGNR";
18780 case X86ISD::VALIGN: return "X86ISD::VALIGN";
18781 case X86ISD::PSHUFD: return "X86ISD::PSHUFD";
18782 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW";
18783 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW";
18784 case X86ISD::SHUFP: return "X86ISD::SHUFP";
18785 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS";
18786 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD";
18787 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS";
18788 case X86ISD::MOVLPS: return "X86ISD::MOVLPS";
18789 case X86ISD::MOVLPD: return "X86ISD::MOVLPD";
18790 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP";
18791 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP";
18792 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP";
18793 case X86ISD::MOVSD: return "X86ISD::MOVSD";
18794 case X86ISD::MOVSS: return "X86ISD::MOVSS";
18795 case X86ISD::UNPCKL: return "X86ISD::UNPCKL";
18796 case X86ISD::UNPCKH: return "X86ISD::UNPCKH";
18797 case X86ISD::VBROADCAST: return "X86ISD::VBROADCAST";
18798 case X86ISD::VBROADCASTM: return "X86ISD::VBROADCASTM";
18799 case X86ISD::VEXTRACT: return "X86ISD::VEXTRACT";
18800 case X86ISD::VPERMILPI: return "X86ISD::VPERMILPI";
18801 case X86ISD::VPERM2X128: return "X86ISD::VPERM2X128";
18802 case X86ISD::VPERMV: return "X86ISD::VPERMV";
18803 case X86ISD::VPERMV3: return "X86ISD::VPERMV3";
18804 case X86ISD::VPERMIV3: return "X86ISD::VPERMIV3";
18805 case X86ISD::VPERMI: return "X86ISD::VPERMI";
18806 case X86ISD::PMULUDQ: return "X86ISD::PMULUDQ";
18807 case X86ISD::PMULDQ: return "X86ISD::PMULDQ";
18808 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
18809 case X86ISD::VAARG_64: return "X86ISD::VAARG_64";
18810 case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA";
18811 case X86ISD::MEMBARRIER: return "X86ISD::MEMBARRIER";
18812 case X86ISD::SEG_ALLOCA: return "X86ISD::SEG_ALLOCA";
18813 case X86ISD::WIN_FTOL: return "X86ISD::WIN_FTOL";
18814 case X86ISD::SAHF: return "X86ISD::SAHF";
18815 case X86ISD::RDRAND: return "X86ISD::RDRAND";
18816 case X86ISD::RDSEED: return "X86ISD::RDSEED";
18817 case X86ISD::FMADD: return "X86ISD::FMADD";
18818 case X86ISD::FMSUB: return "X86ISD::FMSUB";
18819 case X86ISD::FNMADD: return "X86ISD::FNMADD";
18820 case X86ISD::FNMSUB: return "X86ISD::FNMSUB";
18821 case X86ISD::FMADDSUB: return "X86ISD::FMADDSUB";
18822 case X86ISD::FMSUBADD: return "X86ISD::FMSUBADD";
18823 case X86ISD::PCMPESTRI: return "X86ISD::PCMPESTRI";
18824 case X86ISD::PCMPISTRI: return "X86ISD::PCMPISTRI";
18825 case X86ISD::XTEST: return "X86ISD::XTEST";
18829 // isLegalAddressingMode - Return true if the addressing mode represented
18830 // by AM is legal for this target, for a load/store of the specified type.
18831 bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
18833 // X86 supports extremely general addressing modes.
18834 CodeModel::Model M = getTargetMachine().getCodeModel();
18835 Reloc::Model R = getTargetMachine().getRelocationModel();
18837 // X86 allows a sign-extended 32-bit immediate field as a displacement.
18838 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != nullptr))
18843 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
18845 // If a reference to this global requires an extra load, we can't fold it.
18846 if (isGlobalStubReference(GVFlags))
18849 // If BaseGV requires a register for the PIC base, we cannot also have a
18850 // BaseReg specified.
18851 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
18854 // If lower 4G is not available, then we must use rip-relative addressing.
18855 if ((M != CodeModel::Small || R != Reloc::Static) &&
18856 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
18860 switch (AM.Scale) {
18866 // These scales always work.
18871 // These scales are formed with basereg+scalereg. Only accept if there is
18876 default: // Other stuff never works.
18883 bool X86TargetLowering::isVectorShiftByScalarCheap(Type *Ty) const {
18884 unsigned Bits = Ty->getScalarSizeInBits();
18886 // 8-bit shifts are always expensive, but versions with a scalar amount aren't
18887 // particularly cheaper than those without.
18891 // On AVX2 there are new vpsllv[dq] instructions (and other shifts), that make
18892 // variable shifts just as cheap as scalar ones.
18893 if (Subtarget->hasInt256() && (Bits == 32 || Bits == 64))
18896 // Otherwise, it's significantly cheaper to shift by a scalar amount than by a
18897 // fully general vector.
18901 bool X86TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
18902 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
18904 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
18905 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
18906 return NumBits1 > NumBits2;
18909 bool X86TargetLowering::allowTruncateForTailCall(Type *Ty1, Type *Ty2) const {
18910 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
18913 if (!isTypeLegal(EVT::getEVT(Ty1)))
18916 assert(Ty1->getPrimitiveSizeInBits() <= 64 && "i128 is probably not a noop");
18918 // Assuming the caller doesn't have a zeroext or signext return parameter,
18919 // truncation all the way down to i1 is valid.
18923 bool X86TargetLowering::isLegalICmpImmediate(int64_t Imm) const {
18924 return isInt<32>(Imm);
18927 bool X86TargetLowering::isLegalAddImmediate(int64_t Imm) const {
18928 // Can also use sub to handle negated immediates.
18929 return isInt<32>(Imm);
18932 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
18933 if (!VT1.isInteger() || !VT2.isInteger())
18935 unsigned NumBits1 = VT1.getSizeInBits();
18936 unsigned NumBits2 = VT2.getSizeInBits();
18937 return NumBits1 > NumBits2;
18940 bool X86TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
18941 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
18942 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit();
18945 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
18946 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
18947 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
18950 bool X86TargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
18951 EVT VT1 = Val.getValueType();
18952 if (isZExtFree(VT1, VT2))
18955 if (Val.getOpcode() != ISD::LOAD)
18958 if (!VT1.isSimple() || !VT1.isInteger() ||
18959 !VT2.isSimple() || !VT2.isInteger())
18962 switch (VT1.getSimpleVT().SimpleTy) {
18967 // X86 has 8, 16, and 32-bit zero-extending loads.
18975 X86TargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
18976 if (!(Subtarget->hasFMA() || Subtarget->hasFMA4()))
18979 VT = VT.getScalarType();
18981 if (!VT.isSimple())
18984 switch (VT.getSimpleVT().SimpleTy) {
18995 bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
18996 // i16 instructions are longer (0x66 prefix) and potentially slower.
18997 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
19000 /// isShuffleMaskLegal - Targets can use this to indicate that they only
19001 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
19002 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
19003 /// are assumed to be legal.
19005 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
19007 if (!VT.isSimple())
19010 MVT SVT = VT.getSimpleVT();
19012 // Very little shuffling can be done for 64-bit vectors right now.
19013 if (VT.getSizeInBits() == 64)
19016 // If this is a single-input shuffle with no 128 bit lane crossings we can
19017 // lower it into pshufb.
19018 if ((SVT.is128BitVector() && Subtarget->hasSSSE3()) ||
19019 (SVT.is256BitVector() && Subtarget->hasInt256())) {
19020 bool isLegal = true;
19021 for (unsigned I = 0, E = M.size(); I != E; ++I) {
19022 if (M[I] >= (int)SVT.getVectorNumElements() ||
19023 ShuffleCrosses128bitLane(SVT, I, M[I])) {
19032 // FIXME: blends, shifts.
19033 return (SVT.getVectorNumElements() == 2 ||
19034 ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
19035 isMOVLMask(M, SVT) ||
19036 isMOVHLPSMask(M, SVT) ||
19037 isSHUFPMask(M, SVT) ||
19038 isPSHUFDMask(M, SVT) ||
19039 isPSHUFHWMask(M, SVT, Subtarget->hasInt256()) ||
19040 isPSHUFLWMask(M, SVT, Subtarget->hasInt256()) ||
19041 isPALIGNRMask(M, SVT, Subtarget) ||
19042 isUNPCKLMask(M, SVT, Subtarget->hasInt256()) ||
19043 isUNPCKHMask(M, SVT, Subtarget->hasInt256()) ||
19044 isUNPCKL_v_undef_Mask(M, SVT, Subtarget->hasInt256()) ||
19045 isUNPCKH_v_undef_Mask(M, SVT, Subtarget->hasInt256()) ||
19046 isBlendMask(M, SVT, Subtarget->hasSSE41(), Subtarget->hasInt256()));
19050 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
19052 if (!VT.isSimple())
19055 MVT SVT = VT.getSimpleVT();
19056 unsigned NumElts = SVT.getVectorNumElements();
19057 // FIXME: This collection of masks seems suspect.
19060 if (NumElts == 4 && SVT.is128BitVector()) {
19061 return (isMOVLMask(Mask, SVT) ||
19062 isCommutedMOVLMask(Mask, SVT, true) ||
19063 isSHUFPMask(Mask, SVT) ||
19064 isSHUFPMask(Mask, SVT, /* Commuted */ true));
19069 //===----------------------------------------------------------------------===//
19070 // X86 Scheduler Hooks
19071 //===----------------------------------------------------------------------===//
19073 /// Utility function to emit xbegin specifying the start of an RTM region.
19074 static MachineBasicBlock *EmitXBegin(MachineInstr *MI, MachineBasicBlock *MBB,
19075 const TargetInstrInfo *TII) {
19076 DebugLoc DL = MI->getDebugLoc();
19078 const BasicBlock *BB = MBB->getBasicBlock();
19079 MachineFunction::iterator I = MBB;
19082 // For the v = xbegin(), we generate
19093 MachineBasicBlock *thisMBB = MBB;
19094 MachineFunction *MF = MBB->getParent();
19095 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
19096 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
19097 MF->insert(I, mainMBB);
19098 MF->insert(I, sinkMBB);
19100 // Transfer the remainder of BB and its successor edges to sinkMBB.
19101 sinkMBB->splice(sinkMBB->begin(), MBB,
19102 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
19103 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
19107 // # fallthrough to mainMBB
19108 // # abortion to sinkMBB
19109 BuildMI(thisMBB, DL, TII->get(X86::XBEGIN_4)).addMBB(sinkMBB);
19110 thisMBB->addSuccessor(mainMBB);
19111 thisMBB->addSuccessor(sinkMBB);
19115 BuildMI(mainMBB, DL, TII->get(X86::MOV32ri), X86::EAX).addImm(-1);
19116 mainMBB->addSuccessor(sinkMBB);
19119 // EAX is live into the sinkMBB
19120 sinkMBB->addLiveIn(X86::EAX);
19121 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
19122 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
19125 MI->eraseFromParent();
19129 // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
19130 // or XMM0_V32I8 in AVX all of this code can be replaced with that
19131 // in the .td file.
19132 static MachineBasicBlock *EmitPCMPSTRM(MachineInstr *MI, MachineBasicBlock *BB,
19133 const TargetInstrInfo *TII) {
19135 switch (MI->getOpcode()) {
19136 default: llvm_unreachable("illegal opcode!");
19137 case X86::PCMPISTRM128REG: Opc = X86::PCMPISTRM128rr; break;
19138 case X86::VPCMPISTRM128REG: Opc = X86::VPCMPISTRM128rr; break;
19139 case X86::PCMPISTRM128MEM: Opc = X86::PCMPISTRM128rm; break;
19140 case X86::VPCMPISTRM128MEM: Opc = X86::VPCMPISTRM128rm; break;
19141 case X86::PCMPESTRM128REG: Opc = X86::PCMPESTRM128rr; break;
19142 case X86::VPCMPESTRM128REG: Opc = X86::VPCMPESTRM128rr; break;
19143 case X86::PCMPESTRM128MEM: Opc = X86::PCMPESTRM128rm; break;
19144 case X86::VPCMPESTRM128MEM: Opc = X86::VPCMPESTRM128rm; break;
19147 DebugLoc dl = MI->getDebugLoc();
19148 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
19150 unsigned NumArgs = MI->getNumOperands();
19151 for (unsigned i = 1; i < NumArgs; ++i) {
19152 MachineOperand &Op = MI->getOperand(i);
19153 if (!(Op.isReg() && Op.isImplicit()))
19154 MIB.addOperand(Op);
19156 if (MI->hasOneMemOperand())
19157 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
19159 BuildMI(*BB, MI, dl,
19160 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
19161 .addReg(X86::XMM0);
19163 MI->eraseFromParent();
19167 // FIXME: Custom handling because TableGen doesn't support multiple implicit
19168 // defs in an instruction pattern
19169 static MachineBasicBlock *EmitPCMPSTRI(MachineInstr *MI, MachineBasicBlock *BB,
19170 const TargetInstrInfo *TII) {
19172 switch (MI->getOpcode()) {
19173 default: llvm_unreachable("illegal opcode!");
19174 case X86::PCMPISTRIREG: Opc = X86::PCMPISTRIrr; break;
19175 case X86::VPCMPISTRIREG: Opc = X86::VPCMPISTRIrr; break;
19176 case X86::PCMPISTRIMEM: Opc = X86::PCMPISTRIrm; break;
19177 case X86::VPCMPISTRIMEM: Opc = X86::VPCMPISTRIrm; break;
19178 case X86::PCMPESTRIREG: Opc = X86::PCMPESTRIrr; break;
19179 case X86::VPCMPESTRIREG: Opc = X86::VPCMPESTRIrr; break;
19180 case X86::PCMPESTRIMEM: Opc = X86::PCMPESTRIrm; break;
19181 case X86::VPCMPESTRIMEM: Opc = X86::VPCMPESTRIrm; break;
19184 DebugLoc dl = MI->getDebugLoc();
19185 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
19187 unsigned NumArgs = MI->getNumOperands(); // remove the results
19188 for (unsigned i = 1; i < NumArgs; ++i) {
19189 MachineOperand &Op = MI->getOperand(i);
19190 if (!(Op.isReg() && Op.isImplicit()))
19191 MIB.addOperand(Op);
19193 if (MI->hasOneMemOperand())
19194 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
19196 BuildMI(*BB, MI, dl,
19197 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
19200 MI->eraseFromParent();
19204 static MachineBasicBlock * EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB,
19205 const TargetInstrInfo *TII,
19206 const X86Subtarget* Subtarget) {
19207 DebugLoc dl = MI->getDebugLoc();
19209 // Address into RAX/EAX, other two args into ECX, EDX.
19210 unsigned MemOpc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
19211 unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
19212 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg);
19213 for (int i = 0; i < X86::AddrNumOperands; ++i)
19214 MIB.addOperand(MI->getOperand(i));
19216 unsigned ValOps = X86::AddrNumOperands;
19217 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
19218 .addReg(MI->getOperand(ValOps).getReg());
19219 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EDX)
19220 .addReg(MI->getOperand(ValOps+1).getReg());
19222 // The instruction doesn't actually take any operands though.
19223 BuildMI(*BB, MI, dl, TII->get(X86::MONITORrrr));
19225 MI->eraseFromParent(); // The pseudo is gone now.
19229 MachineBasicBlock *
19230 X86TargetLowering::EmitVAARG64WithCustomInserter(
19232 MachineBasicBlock *MBB) const {
19233 // Emit va_arg instruction on X86-64.
19235 // Operands to this pseudo-instruction:
19236 // 0 ) Output : destination address (reg)
19237 // 1-5) Input : va_list address (addr, i64mem)
19238 // 6 ) ArgSize : Size (in bytes) of vararg type
19239 // 7 ) ArgMode : 0=overflow only, 1=use gp_offset, 2=use fp_offset
19240 // 8 ) Align : Alignment of type
19241 // 9 ) EFLAGS (implicit-def)
19243 assert(MI->getNumOperands() == 10 && "VAARG_64 should have 10 operands!");
19244 assert(X86::AddrNumOperands == 5 && "VAARG_64 assumes 5 address operands");
19246 unsigned DestReg = MI->getOperand(0).getReg();
19247 MachineOperand &Base = MI->getOperand(1);
19248 MachineOperand &Scale = MI->getOperand(2);
19249 MachineOperand &Index = MI->getOperand(3);
19250 MachineOperand &Disp = MI->getOperand(4);
19251 MachineOperand &Segment = MI->getOperand(5);
19252 unsigned ArgSize = MI->getOperand(6).getImm();
19253 unsigned ArgMode = MI->getOperand(7).getImm();
19254 unsigned Align = MI->getOperand(8).getImm();
19256 // Memory Reference
19257 assert(MI->hasOneMemOperand() && "Expected VAARG_64 to have one memoperand");
19258 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
19259 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
19261 // Machine Information
19262 const TargetInstrInfo *TII = MBB->getParent()->getSubtarget().getInstrInfo();
19263 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
19264 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64);
19265 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32);
19266 DebugLoc DL = MI->getDebugLoc();
19268 // struct va_list {
19271 // i64 overflow_area (address)
19272 // i64 reg_save_area (address)
19274 // sizeof(va_list) = 24
19275 // alignment(va_list) = 8
19277 unsigned TotalNumIntRegs = 6;
19278 unsigned TotalNumXMMRegs = 8;
19279 bool UseGPOffset = (ArgMode == 1);
19280 bool UseFPOffset = (ArgMode == 2);
19281 unsigned MaxOffset = TotalNumIntRegs * 8 +
19282 (UseFPOffset ? TotalNumXMMRegs * 16 : 0);
19284 /* Align ArgSize to a multiple of 8 */
19285 unsigned ArgSizeA8 = (ArgSize + 7) & ~7;
19286 bool NeedsAlign = (Align > 8);
19288 MachineBasicBlock *thisMBB = MBB;
19289 MachineBasicBlock *overflowMBB;
19290 MachineBasicBlock *offsetMBB;
19291 MachineBasicBlock *endMBB;
19293 unsigned OffsetDestReg = 0; // Argument address computed by offsetMBB
19294 unsigned OverflowDestReg = 0; // Argument address computed by overflowMBB
19295 unsigned OffsetReg = 0;
19297 if (!UseGPOffset && !UseFPOffset) {
19298 // If we only pull from the overflow region, we don't create a branch.
19299 // We don't need to alter control flow.
19300 OffsetDestReg = 0; // unused
19301 OverflowDestReg = DestReg;
19303 offsetMBB = nullptr;
19304 overflowMBB = thisMBB;
19307 // First emit code to check if gp_offset (or fp_offset) is below the bound.
19308 // If so, pull the argument from reg_save_area. (branch to offsetMBB)
19309 // If not, pull from overflow_area. (branch to overflowMBB)
19314 // offsetMBB overflowMBB
19319 // Registers for the PHI in endMBB
19320 OffsetDestReg = MRI.createVirtualRegister(AddrRegClass);
19321 OverflowDestReg = MRI.createVirtualRegister(AddrRegClass);
19323 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
19324 MachineFunction *MF = MBB->getParent();
19325 overflowMBB = MF->CreateMachineBasicBlock(LLVM_BB);
19326 offsetMBB = MF->CreateMachineBasicBlock(LLVM_BB);
19327 endMBB = MF->CreateMachineBasicBlock(LLVM_BB);
19329 MachineFunction::iterator MBBIter = MBB;
19332 // Insert the new basic blocks
19333 MF->insert(MBBIter, offsetMBB);
19334 MF->insert(MBBIter, overflowMBB);
19335 MF->insert(MBBIter, endMBB);
19337 // Transfer the remainder of MBB and its successor edges to endMBB.
19338 endMBB->splice(endMBB->begin(), thisMBB,
19339 std::next(MachineBasicBlock::iterator(MI)), thisMBB->end());
19340 endMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
19342 // Make offsetMBB and overflowMBB successors of thisMBB
19343 thisMBB->addSuccessor(offsetMBB);
19344 thisMBB->addSuccessor(overflowMBB);
19346 // endMBB is a successor of both offsetMBB and overflowMBB
19347 offsetMBB->addSuccessor(endMBB);
19348 overflowMBB->addSuccessor(endMBB);
19350 // Load the offset value into a register
19351 OffsetReg = MRI.createVirtualRegister(OffsetRegClass);
19352 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg)
19356 .addDisp(Disp, UseFPOffset ? 4 : 0)
19357 .addOperand(Segment)
19358 .setMemRefs(MMOBegin, MMOEnd);
19360 // Check if there is enough room left to pull this argument.
19361 BuildMI(thisMBB, DL, TII->get(X86::CMP32ri))
19363 .addImm(MaxOffset + 8 - ArgSizeA8);
19365 // Branch to "overflowMBB" if offset >= max
19366 // Fall through to "offsetMBB" otherwise
19367 BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE)))
19368 .addMBB(overflowMBB);
19371 // In offsetMBB, emit code to use the reg_save_area.
19373 assert(OffsetReg != 0);
19375 // Read the reg_save_area address.
19376 unsigned RegSaveReg = MRI.createVirtualRegister(AddrRegClass);
19377 BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg)
19382 .addOperand(Segment)
19383 .setMemRefs(MMOBegin, MMOEnd);
19385 // Zero-extend the offset
19386 unsigned OffsetReg64 = MRI.createVirtualRegister(AddrRegClass);
19387 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64)
19390 .addImm(X86::sub_32bit);
19392 // Add the offset to the reg_save_area to get the final address.
19393 BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg)
19394 .addReg(OffsetReg64)
19395 .addReg(RegSaveReg);
19397 // Compute the offset for the next argument
19398 unsigned NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass);
19399 BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg)
19401 .addImm(UseFPOffset ? 16 : 8);
19403 // Store it back into the va_list.
19404 BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr))
19408 .addDisp(Disp, UseFPOffset ? 4 : 0)
19409 .addOperand(Segment)
19410 .addReg(NextOffsetReg)
19411 .setMemRefs(MMOBegin, MMOEnd);
19414 BuildMI(offsetMBB, DL, TII->get(X86::JMP_4))
19419 // Emit code to use overflow area
19422 // Load the overflow_area address into a register.
19423 unsigned OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass);
19424 BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg)
19429 .addOperand(Segment)
19430 .setMemRefs(MMOBegin, MMOEnd);
19432 // If we need to align it, do so. Otherwise, just copy the address
19433 // to OverflowDestReg.
19435 // Align the overflow address
19436 assert((Align & (Align-1)) == 0 && "Alignment must be a power of 2");
19437 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass);
19439 // aligned_addr = (addr + (align-1)) & ~(align-1)
19440 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg)
19441 .addReg(OverflowAddrReg)
19444 BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg)
19446 .addImm(~(uint64_t)(Align-1));
19448 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg)
19449 .addReg(OverflowAddrReg);
19452 // Compute the next overflow address after this argument.
19453 // (the overflow address should be kept 8-byte aligned)
19454 unsigned NextAddrReg = MRI.createVirtualRegister(AddrRegClass);
19455 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg)
19456 .addReg(OverflowDestReg)
19457 .addImm(ArgSizeA8);
19459 // Store the new overflow address.
19460 BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr))
19465 .addOperand(Segment)
19466 .addReg(NextAddrReg)
19467 .setMemRefs(MMOBegin, MMOEnd);
19469 // If we branched, emit the PHI to the front of endMBB.
19471 BuildMI(*endMBB, endMBB->begin(), DL,
19472 TII->get(X86::PHI), DestReg)
19473 .addReg(OffsetDestReg).addMBB(offsetMBB)
19474 .addReg(OverflowDestReg).addMBB(overflowMBB);
19477 // Erase the pseudo instruction
19478 MI->eraseFromParent();
19483 MachineBasicBlock *
19484 X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
19486 MachineBasicBlock *MBB) const {
19487 // Emit code to save XMM registers to the stack. The ABI says that the
19488 // number of registers to save is given in %al, so it's theoretically
19489 // possible to do an indirect jump trick to avoid saving all of them,
19490 // however this code takes a simpler approach and just executes all
19491 // of the stores if %al is non-zero. It's less code, and it's probably
19492 // easier on the hardware branch predictor, and stores aren't all that
19493 // expensive anyway.
19495 // Create the new basic blocks. One block contains all the XMM stores,
19496 // and one block is the final destination regardless of whether any
19497 // stores were performed.
19498 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
19499 MachineFunction *F = MBB->getParent();
19500 MachineFunction::iterator MBBIter = MBB;
19502 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB);
19503 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB);
19504 F->insert(MBBIter, XMMSaveMBB);
19505 F->insert(MBBIter, EndMBB);
19507 // Transfer the remainder of MBB and its successor edges to EndMBB.
19508 EndMBB->splice(EndMBB->begin(), MBB,
19509 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
19510 EndMBB->transferSuccessorsAndUpdatePHIs(MBB);
19512 // The original block will now fall through to the XMM save block.
19513 MBB->addSuccessor(XMMSaveMBB);
19514 // The XMMSaveMBB will fall through to the end block.
19515 XMMSaveMBB->addSuccessor(EndMBB);
19517 // Now add the instructions.
19518 const TargetInstrInfo *TII = MBB->getParent()->getSubtarget().getInstrInfo();
19519 DebugLoc DL = MI->getDebugLoc();
19521 unsigned CountReg = MI->getOperand(0).getReg();
19522 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm();
19523 int64_t VarArgsFPOffset = MI->getOperand(2).getImm();
19525 if (!Subtarget->isTargetWin64()) {
19526 // If %al is 0, branch around the XMM save block.
19527 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
19528 BuildMI(MBB, DL, TII->get(X86::JE_4)).addMBB(EndMBB);
19529 MBB->addSuccessor(EndMBB);
19532 // Make sure the last operand is EFLAGS, which gets clobbered by the branch
19533 // that was just emitted, but clearly shouldn't be "saved".
19534 assert((MI->getNumOperands() <= 3 ||
19535 !MI->getOperand(MI->getNumOperands() - 1).isReg() ||
19536 MI->getOperand(MI->getNumOperands() - 1).getReg() == X86::EFLAGS)
19537 && "Expected last argument to be EFLAGS");
19538 unsigned MOVOpc = Subtarget->hasFp256() ? X86::VMOVAPSmr : X86::MOVAPSmr;
19539 // In the XMM save block, save all the XMM argument registers.
19540 for (int i = 3, e = MI->getNumOperands() - 1; i != e; ++i) {
19541 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
19542 MachineMemOperand *MMO =
19543 F->getMachineMemOperand(
19544 MachinePointerInfo::getFixedStack(RegSaveFrameIndex, Offset),
19545 MachineMemOperand::MOStore,
19546 /*Size=*/16, /*Align=*/16);
19547 BuildMI(XMMSaveMBB, DL, TII->get(MOVOpc))
19548 .addFrameIndex(RegSaveFrameIndex)
19549 .addImm(/*Scale=*/1)
19550 .addReg(/*IndexReg=*/0)
19551 .addImm(/*Disp=*/Offset)
19552 .addReg(/*Segment=*/0)
19553 .addReg(MI->getOperand(i).getReg())
19554 .addMemOperand(MMO);
19557 MI->eraseFromParent(); // The pseudo instruction is gone now.
19562 // The EFLAGS operand of SelectItr might be missing a kill marker
19563 // because there were multiple uses of EFLAGS, and ISel didn't know
19564 // which to mark. Figure out whether SelectItr should have had a
19565 // kill marker, and set it if it should. Returns the correct kill
19567 static bool checkAndUpdateEFLAGSKill(MachineBasicBlock::iterator SelectItr,
19568 MachineBasicBlock* BB,
19569 const TargetRegisterInfo* TRI) {
19570 // Scan forward through BB for a use/def of EFLAGS.
19571 MachineBasicBlock::iterator miI(std::next(SelectItr));
19572 for (MachineBasicBlock::iterator miE = BB->end(); miI != miE; ++miI) {
19573 const MachineInstr& mi = *miI;
19574 if (mi.readsRegister(X86::EFLAGS))
19576 if (mi.definesRegister(X86::EFLAGS))
19577 break; // Should have kill-flag - update below.
19580 // If we hit the end of the block, check whether EFLAGS is live into a
19582 if (miI == BB->end()) {
19583 for (MachineBasicBlock::succ_iterator sItr = BB->succ_begin(),
19584 sEnd = BB->succ_end();
19585 sItr != sEnd; ++sItr) {
19586 MachineBasicBlock* succ = *sItr;
19587 if (succ->isLiveIn(X86::EFLAGS))
19592 // We found a def, or hit the end of the basic block and EFLAGS wasn't live
19593 // out. SelectMI should have a kill flag on EFLAGS.
19594 SelectItr->addRegisterKilled(X86::EFLAGS, TRI);
19598 MachineBasicBlock *
19599 X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
19600 MachineBasicBlock *BB) const {
19601 const TargetInstrInfo *TII = BB->getParent()->getSubtarget().getInstrInfo();
19602 DebugLoc DL = MI->getDebugLoc();
19604 // To "insert" a SELECT_CC instruction, we actually have to insert the
19605 // diamond control-flow pattern. The incoming instruction knows the
19606 // destination vreg to set, the condition code register to branch on, the
19607 // true/false values to select between, and a branch opcode to use.
19608 const BasicBlock *LLVM_BB = BB->getBasicBlock();
19609 MachineFunction::iterator It = BB;
19615 // cmpTY ccX, r1, r2
19617 // fallthrough --> copy0MBB
19618 MachineBasicBlock *thisMBB = BB;
19619 MachineFunction *F = BB->getParent();
19620 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
19621 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
19622 F->insert(It, copy0MBB);
19623 F->insert(It, sinkMBB);
19625 // If the EFLAGS register isn't dead in the terminator, then claim that it's
19626 // live into the sink and copy blocks.
19627 const TargetRegisterInfo *TRI =
19628 BB->getParent()->getSubtarget().getRegisterInfo();
19629 if (!MI->killsRegister(X86::EFLAGS) &&
19630 !checkAndUpdateEFLAGSKill(MI, BB, TRI)) {
19631 copy0MBB->addLiveIn(X86::EFLAGS);
19632 sinkMBB->addLiveIn(X86::EFLAGS);
19635 // Transfer the remainder of BB and its successor edges to sinkMBB.
19636 sinkMBB->splice(sinkMBB->begin(), BB,
19637 std::next(MachineBasicBlock::iterator(MI)), BB->end());
19638 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
19640 // Add the true and fallthrough blocks as its successors.
19641 BB->addSuccessor(copy0MBB);
19642 BB->addSuccessor(sinkMBB);
19644 // Create the conditional branch instruction.
19646 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
19647 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
19650 // %FalseValue = ...
19651 // # fallthrough to sinkMBB
19652 copy0MBB->addSuccessor(sinkMBB);
19655 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
19657 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
19658 TII->get(X86::PHI), MI->getOperand(0).getReg())
19659 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
19660 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
19662 MI->eraseFromParent(); // The pseudo instruction is gone now.
19666 MachineBasicBlock *
19667 X86TargetLowering::EmitLoweredSegAlloca(MachineInstr *MI,
19668 MachineBasicBlock *BB) const {
19669 MachineFunction *MF = BB->getParent();
19670 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
19671 DebugLoc DL = MI->getDebugLoc();
19672 const BasicBlock *LLVM_BB = BB->getBasicBlock();
19674 assert(MF->shouldSplitStack());
19676 const bool Is64Bit = Subtarget->is64Bit();
19677 const bool IsLP64 = Subtarget->isTarget64BitLP64();
19679 const unsigned TlsReg = Is64Bit ? X86::FS : X86::GS;
19680 const unsigned TlsOffset = IsLP64 ? 0x70 : Is64Bit ? 0x40 : 0x30;
19683 // ... [Till the alloca]
19684 // If stacklet is not large enough, jump to mallocMBB
19687 // Allocate by subtracting from RSP
19688 // Jump to continueMBB
19691 // Allocate by call to runtime
19695 // [rest of original BB]
19698 MachineBasicBlock *mallocMBB = MF->CreateMachineBasicBlock(LLVM_BB);
19699 MachineBasicBlock *bumpMBB = MF->CreateMachineBasicBlock(LLVM_BB);
19700 MachineBasicBlock *continueMBB = MF->CreateMachineBasicBlock(LLVM_BB);
19702 MachineRegisterInfo &MRI = MF->getRegInfo();
19703 const TargetRegisterClass *AddrRegClass =
19704 getRegClassFor(getPointerTy());
19706 unsigned mallocPtrVReg = MRI.createVirtualRegister(AddrRegClass),
19707 bumpSPPtrVReg = MRI.createVirtualRegister(AddrRegClass),
19708 tmpSPVReg = MRI.createVirtualRegister(AddrRegClass),
19709 SPLimitVReg = MRI.createVirtualRegister(AddrRegClass),
19710 sizeVReg = MI->getOperand(1).getReg(),
19711 physSPReg = IsLP64 || Subtarget->isTargetNaCl64() ? X86::RSP : X86::ESP;
19713 MachineFunction::iterator MBBIter = BB;
19716 MF->insert(MBBIter, bumpMBB);
19717 MF->insert(MBBIter, mallocMBB);
19718 MF->insert(MBBIter, continueMBB);
19720 continueMBB->splice(continueMBB->begin(), BB,
19721 std::next(MachineBasicBlock::iterator(MI)), BB->end());
19722 continueMBB->transferSuccessorsAndUpdatePHIs(BB);
19724 // Add code to the main basic block to check if the stack limit has been hit,
19725 // and if so, jump to mallocMBB otherwise to bumpMBB.
19726 BuildMI(BB, DL, TII->get(TargetOpcode::COPY), tmpSPVReg).addReg(physSPReg);
19727 BuildMI(BB, DL, TII->get(IsLP64 ? X86::SUB64rr:X86::SUB32rr), SPLimitVReg)
19728 .addReg(tmpSPVReg).addReg(sizeVReg);
19729 BuildMI(BB, DL, TII->get(IsLP64 ? X86::CMP64mr:X86::CMP32mr))
19730 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg)
19731 .addReg(SPLimitVReg);
19732 BuildMI(BB, DL, TII->get(X86::JG_4)).addMBB(mallocMBB);
19734 // bumpMBB simply decreases the stack pointer, since we know the current
19735 // stacklet has enough space.
19736 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), physSPReg)
19737 .addReg(SPLimitVReg);
19738 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), bumpSPPtrVReg)
19739 .addReg(SPLimitVReg);
19740 BuildMI(bumpMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
19742 // Calls into a routine in libgcc to allocate more space from the heap.
19743 const uint32_t *RegMask = MF->getTarget()
19744 .getSubtargetImpl()
19745 ->getRegisterInfo()
19746 ->getCallPreservedMask(CallingConv::C);
19748 BuildMI(mallocMBB, DL, TII->get(X86::MOV64rr), X86::RDI)
19750 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
19751 .addExternalSymbol("__morestack_allocate_stack_space")
19752 .addRegMask(RegMask)
19753 .addReg(X86::RDI, RegState::Implicit)
19754 .addReg(X86::RAX, RegState::ImplicitDefine);
19755 } else if (Is64Bit) {
19756 BuildMI(mallocMBB, DL, TII->get(X86::MOV32rr), X86::EDI)
19758 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
19759 .addExternalSymbol("__morestack_allocate_stack_space")
19760 .addRegMask(RegMask)
19761 .addReg(X86::EDI, RegState::Implicit)
19762 .addReg(X86::EAX, RegState::ImplicitDefine);
19764 BuildMI(mallocMBB, DL, TII->get(X86::SUB32ri), physSPReg).addReg(physSPReg)
19766 BuildMI(mallocMBB, DL, TII->get(X86::PUSH32r)).addReg(sizeVReg);
19767 BuildMI(mallocMBB, DL, TII->get(X86::CALLpcrel32))
19768 .addExternalSymbol("__morestack_allocate_stack_space")
19769 .addRegMask(RegMask)
19770 .addReg(X86::EAX, RegState::ImplicitDefine);
19774 BuildMI(mallocMBB, DL, TII->get(X86::ADD32ri), physSPReg).addReg(physSPReg)
19777 BuildMI(mallocMBB, DL, TII->get(TargetOpcode::COPY), mallocPtrVReg)
19778 .addReg(IsLP64 ? X86::RAX : X86::EAX);
19779 BuildMI(mallocMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
19781 // Set up the CFG correctly.
19782 BB->addSuccessor(bumpMBB);
19783 BB->addSuccessor(mallocMBB);
19784 mallocMBB->addSuccessor(continueMBB);
19785 bumpMBB->addSuccessor(continueMBB);
19787 // Take care of the PHI nodes.
19788 BuildMI(*continueMBB, continueMBB->begin(), DL, TII->get(X86::PHI),
19789 MI->getOperand(0).getReg())
19790 .addReg(mallocPtrVReg).addMBB(mallocMBB)
19791 .addReg(bumpSPPtrVReg).addMBB(bumpMBB);
19793 // Delete the original pseudo instruction.
19794 MI->eraseFromParent();
19797 return continueMBB;
19800 MachineBasicBlock *
19801 X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI,
19802 MachineBasicBlock *BB) const {
19803 const TargetInstrInfo *TII = BB->getParent()->getSubtarget().getInstrInfo();
19804 DebugLoc DL = MI->getDebugLoc();
19806 assert(!Subtarget->isTargetMacho());
19808 // The lowering is pretty easy: we're just emitting the call to _alloca. The
19809 // non-trivial part is impdef of ESP.
19811 if (Subtarget->isTargetWin64()) {
19812 if (Subtarget->isTargetCygMing()) {
19813 // ___chkstk(Mingw64):
19814 // Clobbers R10, R11, RAX and EFLAGS.
19816 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
19817 .addExternalSymbol("___chkstk")
19818 .addReg(X86::RAX, RegState::Implicit)
19819 .addReg(X86::RSP, RegState::Implicit)
19820 .addReg(X86::RAX, RegState::Define | RegState::Implicit)
19821 .addReg(X86::RSP, RegState::Define | RegState::Implicit)
19822 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
19824 // __chkstk(MSVCRT): does not update stack pointer.
19825 // Clobbers R10, R11 and EFLAGS.
19826 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
19827 .addExternalSymbol("__chkstk")
19828 .addReg(X86::RAX, RegState::Implicit)
19829 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
19830 // RAX has the offset to be subtracted from RSP.
19831 BuildMI(*BB, MI, DL, TII->get(X86::SUB64rr), X86::RSP)
19836 const char *StackProbeSymbol =
19837 Subtarget->isTargetKnownWindowsMSVC() ? "_chkstk" : "_alloca";
19839 BuildMI(*BB, MI, DL, TII->get(X86::CALLpcrel32))
19840 .addExternalSymbol(StackProbeSymbol)
19841 .addReg(X86::EAX, RegState::Implicit)
19842 .addReg(X86::ESP, RegState::Implicit)
19843 .addReg(X86::EAX, RegState::Define | RegState::Implicit)
19844 .addReg(X86::ESP, RegState::Define | RegState::Implicit)
19845 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
19848 MI->eraseFromParent(); // The pseudo instruction is gone now.
19852 MachineBasicBlock *
19853 X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI,
19854 MachineBasicBlock *BB) const {
19855 // This is pretty easy. We're taking the value that we received from
19856 // our load from the relocation, sticking it in either RDI (x86-64)
19857 // or EAX and doing an indirect call. The return value will then
19858 // be in the normal return register.
19859 MachineFunction *F = BB->getParent();
19860 const X86InstrInfo *TII =
19861 static_cast<const X86InstrInfo *>(F->getSubtarget().getInstrInfo());
19862 DebugLoc DL = MI->getDebugLoc();
19864 assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?");
19865 assert(MI->getOperand(3).isGlobal() && "This should be a global");
19867 // Get a register mask for the lowered call.
19868 // FIXME: The 32-bit calls have non-standard calling conventions. Use a
19869 // proper register mask.
19870 const uint32_t *RegMask = F->getTarget()
19871 .getSubtargetImpl()
19872 ->getRegisterInfo()
19873 ->getCallPreservedMask(CallingConv::C);
19874 if (Subtarget->is64Bit()) {
19875 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
19876 TII->get(X86::MOV64rm), X86::RDI)
19878 .addImm(0).addReg(0)
19879 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
19880 MI->getOperand(3).getTargetFlags())
19882 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m));
19883 addDirectMem(MIB, X86::RDI);
19884 MIB.addReg(X86::RAX, RegState::ImplicitDefine).addRegMask(RegMask);
19885 } else if (F->getTarget().getRelocationModel() != Reloc::PIC_) {
19886 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
19887 TII->get(X86::MOV32rm), X86::EAX)
19889 .addImm(0).addReg(0)
19890 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
19891 MI->getOperand(3).getTargetFlags())
19893 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
19894 addDirectMem(MIB, X86::EAX);
19895 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
19897 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
19898 TII->get(X86::MOV32rm), X86::EAX)
19899 .addReg(TII->getGlobalBaseReg(F))
19900 .addImm(0).addReg(0)
19901 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
19902 MI->getOperand(3).getTargetFlags())
19904 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
19905 addDirectMem(MIB, X86::EAX);
19906 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
19909 MI->eraseFromParent(); // The pseudo instruction is gone now.
19913 MachineBasicBlock *
19914 X86TargetLowering::emitEHSjLjSetJmp(MachineInstr *MI,
19915 MachineBasicBlock *MBB) const {
19916 DebugLoc DL = MI->getDebugLoc();
19917 MachineFunction *MF = MBB->getParent();
19918 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
19919 MachineRegisterInfo &MRI = MF->getRegInfo();
19921 const BasicBlock *BB = MBB->getBasicBlock();
19922 MachineFunction::iterator I = MBB;
19925 // Memory Reference
19926 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
19927 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
19930 unsigned MemOpndSlot = 0;
19932 unsigned CurOp = 0;
19934 DstReg = MI->getOperand(CurOp++).getReg();
19935 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
19936 assert(RC->hasType(MVT::i32) && "Invalid destination!");
19937 unsigned mainDstReg = MRI.createVirtualRegister(RC);
19938 unsigned restoreDstReg = MRI.createVirtualRegister(RC);
19940 MemOpndSlot = CurOp;
19942 MVT PVT = getPointerTy();
19943 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
19944 "Invalid Pointer Size!");
19946 // For v = setjmp(buf), we generate
19949 // buf[LabelOffset] = restoreMBB
19950 // SjLjSetup restoreMBB
19956 // v = phi(main, restore)
19961 MachineBasicBlock *thisMBB = MBB;
19962 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
19963 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
19964 MachineBasicBlock *restoreMBB = MF->CreateMachineBasicBlock(BB);
19965 MF->insert(I, mainMBB);
19966 MF->insert(I, sinkMBB);
19967 MF->push_back(restoreMBB);
19969 MachineInstrBuilder MIB;
19971 // Transfer the remainder of BB and its successor edges to sinkMBB.
19972 sinkMBB->splice(sinkMBB->begin(), MBB,
19973 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
19974 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
19977 unsigned PtrStoreOpc = 0;
19978 unsigned LabelReg = 0;
19979 const int64_t LabelOffset = 1 * PVT.getStoreSize();
19980 Reloc::Model RM = MF->getTarget().getRelocationModel();
19981 bool UseImmLabel = (MF->getTarget().getCodeModel() == CodeModel::Small) &&
19982 (RM == Reloc::Static || RM == Reloc::DynamicNoPIC);
19984 // Prepare IP either in reg or imm.
19985 if (!UseImmLabel) {
19986 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mr : X86::MOV32mr;
19987 const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
19988 LabelReg = MRI.createVirtualRegister(PtrRC);
19989 if (Subtarget->is64Bit()) {
19990 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA64r), LabelReg)
19994 .addMBB(restoreMBB)
19997 const X86InstrInfo *XII = static_cast<const X86InstrInfo*>(TII);
19998 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA32r), LabelReg)
19999 .addReg(XII->getGlobalBaseReg(MF))
20002 .addMBB(restoreMBB, Subtarget->ClassifyBlockAddressReference())
20006 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mi32 : X86::MOV32mi;
20008 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PtrStoreOpc));
20009 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
20010 if (i == X86::AddrDisp)
20011 MIB.addDisp(MI->getOperand(MemOpndSlot + i), LabelOffset);
20013 MIB.addOperand(MI->getOperand(MemOpndSlot + i));
20016 MIB.addReg(LabelReg);
20018 MIB.addMBB(restoreMBB);
20019 MIB.setMemRefs(MMOBegin, MMOEnd);
20021 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::EH_SjLj_Setup))
20022 .addMBB(restoreMBB);
20024 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
20025 MF->getSubtarget().getRegisterInfo());
20026 MIB.addRegMask(RegInfo->getNoPreservedMask());
20027 thisMBB->addSuccessor(mainMBB);
20028 thisMBB->addSuccessor(restoreMBB);
20032 BuildMI(mainMBB, DL, TII->get(X86::MOV32r0), mainDstReg);
20033 mainMBB->addSuccessor(sinkMBB);
20036 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
20037 TII->get(X86::PHI), DstReg)
20038 .addReg(mainDstReg).addMBB(mainMBB)
20039 .addReg(restoreDstReg).addMBB(restoreMBB);
20042 BuildMI(restoreMBB, DL, TII->get(X86::MOV32ri), restoreDstReg).addImm(1);
20043 BuildMI(restoreMBB, DL, TII->get(X86::JMP_4)).addMBB(sinkMBB);
20044 restoreMBB->addSuccessor(sinkMBB);
20046 MI->eraseFromParent();
20050 MachineBasicBlock *
20051 X86TargetLowering::emitEHSjLjLongJmp(MachineInstr *MI,
20052 MachineBasicBlock *MBB) const {
20053 DebugLoc DL = MI->getDebugLoc();
20054 MachineFunction *MF = MBB->getParent();
20055 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
20056 MachineRegisterInfo &MRI = MF->getRegInfo();
20058 // Memory Reference
20059 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
20060 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
20062 MVT PVT = getPointerTy();
20063 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
20064 "Invalid Pointer Size!");
20066 const TargetRegisterClass *RC =
20067 (PVT == MVT::i64) ? &X86::GR64RegClass : &X86::GR32RegClass;
20068 unsigned Tmp = MRI.createVirtualRegister(RC);
20069 // Since FP is only updated here but NOT referenced, it's treated as GPR.
20070 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
20071 MF->getSubtarget().getRegisterInfo());
20072 unsigned FP = (PVT == MVT::i64) ? X86::RBP : X86::EBP;
20073 unsigned SP = RegInfo->getStackRegister();
20075 MachineInstrBuilder MIB;
20077 const int64_t LabelOffset = 1 * PVT.getStoreSize();
20078 const int64_t SPOffset = 2 * PVT.getStoreSize();
20080 unsigned PtrLoadOpc = (PVT == MVT::i64) ? X86::MOV64rm : X86::MOV32rm;
20081 unsigned IJmpOpc = (PVT == MVT::i64) ? X86::JMP64r : X86::JMP32r;
20084 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), FP);
20085 for (unsigned i = 0; i < X86::AddrNumOperands; ++i)
20086 MIB.addOperand(MI->getOperand(i));
20087 MIB.setMemRefs(MMOBegin, MMOEnd);
20089 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), Tmp);
20090 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
20091 if (i == X86::AddrDisp)
20092 MIB.addDisp(MI->getOperand(i), LabelOffset);
20094 MIB.addOperand(MI->getOperand(i));
20096 MIB.setMemRefs(MMOBegin, MMOEnd);
20098 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), SP);
20099 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
20100 if (i == X86::AddrDisp)
20101 MIB.addDisp(MI->getOperand(i), SPOffset);
20103 MIB.addOperand(MI->getOperand(i));
20105 MIB.setMemRefs(MMOBegin, MMOEnd);
20107 BuildMI(*MBB, MI, DL, TII->get(IJmpOpc)).addReg(Tmp);
20109 MI->eraseFromParent();
20113 // Replace 213-type (isel default) FMA3 instructions with 231-type for
20114 // accumulator loops. Writing back to the accumulator allows the coalescer
20115 // to remove extra copies in the loop.
20116 MachineBasicBlock *
20117 X86TargetLowering::emitFMA3Instr(MachineInstr *MI,
20118 MachineBasicBlock *MBB) const {
20119 MachineOperand &AddendOp = MI->getOperand(3);
20121 // Bail out early if the addend isn't a register - we can't switch these.
20122 if (!AddendOp.isReg())
20125 MachineFunction &MF = *MBB->getParent();
20126 MachineRegisterInfo &MRI = MF.getRegInfo();
20128 // Check whether the addend is defined by a PHI:
20129 assert(MRI.hasOneDef(AddendOp.getReg()) && "Multiple defs in SSA?");
20130 MachineInstr &AddendDef = *MRI.def_instr_begin(AddendOp.getReg());
20131 if (!AddendDef.isPHI())
20134 // Look for the following pattern:
20136 // %addend = phi [%entry, 0], [%loop, %result]
20138 // %result<tied1> = FMA213 %m2<tied0>, %m1, %addend
20142 // %addend = phi [%entry, 0], [%loop, %result]
20144 // %result<tied1> = FMA231 %addend<tied0>, %m1, %m2
20146 for (unsigned i = 1, e = AddendDef.getNumOperands(); i < e; i += 2) {
20147 assert(AddendDef.getOperand(i).isReg());
20148 MachineOperand PHISrcOp = AddendDef.getOperand(i);
20149 MachineInstr &PHISrcInst = *MRI.def_instr_begin(PHISrcOp.getReg());
20150 if (&PHISrcInst == MI) {
20151 // Found a matching instruction.
20152 unsigned NewFMAOpc = 0;
20153 switch (MI->getOpcode()) {
20154 case X86::VFMADDPDr213r: NewFMAOpc = X86::VFMADDPDr231r; break;
20155 case X86::VFMADDPSr213r: NewFMAOpc = X86::VFMADDPSr231r; break;
20156 case X86::VFMADDSDr213r: NewFMAOpc = X86::VFMADDSDr231r; break;
20157 case X86::VFMADDSSr213r: NewFMAOpc = X86::VFMADDSSr231r; break;
20158 case X86::VFMSUBPDr213r: NewFMAOpc = X86::VFMSUBPDr231r; break;
20159 case X86::VFMSUBPSr213r: NewFMAOpc = X86::VFMSUBPSr231r; break;
20160 case X86::VFMSUBSDr213r: NewFMAOpc = X86::VFMSUBSDr231r; break;
20161 case X86::VFMSUBSSr213r: NewFMAOpc = X86::VFMSUBSSr231r; break;
20162 case X86::VFNMADDPDr213r: NewFMAOpc = X86::VFNMADDPDr231r; break;
20163 case X86::VFNMADDPSr213r: NewFMAOpc = X86::VFNMADDPSr231r; break;
20164 case X86::VFNMADDSDr213r: NewFMAOpc = X86::VFNMADDSDr231r; break;
20165 case X86::VFNMADDSSr213r: NewFMAOpc = X86::VFNMADDSSr231r; break;
20166 case X86::VFNMSUBPDr213r: NewFMAOpc = X86::VFNMSUBPDr231r; break;
20167 case X86::VFNMSUBPSr213r: NewFMAOpc = X86::VFNMSUBPSr231r; break;
20168 case X86::VFNMSUBSDr213r: NewFMAOpc = X86::VFNMSUBSDr231r; break;
20169 case X86::VFNMSUBSSr213r: NewFMAOpc = X86::VFNMSUBSSr231r; break;
20170 case X86::VFMADDPDr213rY: NewFMAOpc = X86::VFMADDPDr231rY; break;
20171 case X86::VFMADDPSr213rY: NewFMAOpc = X86::VFMADDPSr231rY; break;
20172 case X86::VFMSUBPDr213rY: NewFMAOpc = X86::VFMSUBPDr231rY; break;
20173 case X86::VFMSUBPSr213rY: NewFMAOpc = X86::VFMSUBPSr231rY; break;
20174 case X86::VFNMADDPDr213rY: NewFMAOpc = X86::VFNMADDPDr231rY; break;
20175 case X86::VFNMADDPSr213rY: NewFMAOpc = X86::VFNMADDPSr231rY; break;
20176 case X86::VFNMSUBPDr213rY: NewFMAOpc = X86::VFNMSUBPDr231rY; break;
20177 case X86::VFNMSUBPSr213rY: NewFMAOpc = X86::VFNMSUBPSr231rY; break;
20178 default: llvm_unreachable("Unrecognized FMA variant.");
20181 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
20182 MachineInstrBuilder MIB =
20183 BuildMI(MF, MI->getDebugLoc(), TII.get(NewFMAOpc))
20184 .addOperand(MI->getOperand(0))
20185 .addOperand(MI->getOperand(3))
20186 .addOperand(MI->getOperand(2))
20187 .addOperand(MI->getOperand(1));
20188 MBB->insert(MachineBasicBlock::iterator(MI), MIB);
20189 MI->eraseFromParent();
20196 MachineBasicBlock *
20197 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
20198 MachineBasicBlock *BB) const {
20199 switch (MI->getOpcode()) {
20200 default: llvm_unreachable("Unexpected instr type to insert");
20201 case X86::TAILJMPd64:
20202 case X86::TAILJMPr64:
20203 case X86::TAILJMPm64:
20204 llvm_unreachable("TAILJMP64 would not be touched here.");
20205 case X86::TCRETURNdi64:
20206 case X86::TCRETURNri64:
20207 case X86::TCRETURNmi64:
20209 case X86::WIN_ALLOCA:
20210 return EmitLoweredWinAlloca(MI, BB);
20211 case X86::SEG_ALLOCA_32:
20212 case X86::SEG_ALLOCA_64:
20213 return EmitLoweredSegAlloca(MI, BB);
20214 case X86::TLSCall_32:
20215 case X86::TLSCall_64:
20216 return EmitLoweredTLSCall(MI, BB);
20217 case X86::CMOV_GR8:
20218 case X86::CMOV_FR32:
20219 case X86::CMOV_FR64:
20220 case X86::CMOV_V4F32:
20221 case X86::CMOV_V2F64:
20222 case X86::CMOV_V2I64:
20223 case X86::CMOV_V8F32:
20224 case X86::CMOV_V4F64:
20225 case X86::CMOV_V4I64:
20226 case X86::CMOV_V16F32:
20227 case X86::CMOV_V8F64:
20228 case X86::CMOV_V8I64:
20229 case X86::CMOV_GR16:
20230 case X86::CMOV_GR32:
20231 case X86::CMOV_RFP32:
20232 case X86::CMOV_RFP64:
20233 case X86::CMOV_RFP80:
20234 return EmitLoweredSelect(MI, BB);
20236 case X86::FP32_TO_INT16_IN_MEM:
20237 case X86::FP32_TO_INT32_IN_MEM:
20238 case X86::FP32_TO_INT64_IN_MEM:
20239 case X86::FP64_TO_INT16_IN_MEM:
20240 case X86::FP64_TO_INT32_IN_MEM:
20241 case X86::FP64_TO_INT64_IN_MEM:
20242 case X86::FP80_TO_INT16_IN_MEM:
20243 case X86::FP80_TO_INT32_IN_MEM:
20244 case X86::FP80_TO_INT64_IN_MEM: {
20245 MachineFunction *F = BB->getParent();
20246 const TargetInstrInfo *TII = F->getSubtarget().getInstrInfo();
20247 DebugLoc DL = MI->getDebugLoc();
20249 // Change the floating point control register to use "round towards zero"
20250 // mode when truncating to an integer value.
20251 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false);
20252 addFrameReference(BuildMI(*BB, MI, DL,
20253 TII->get(X86::FNSTCW16m)), CWFrameIdx);
20255 // Load the old value of the high byte of the control word...
20257 F->getRegInfo().createVirtualRegister(&X86::GR16RegClass);
20258 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW),
20261 // Set the high part to be round to zero...
20262 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
20265 // Reload the modified control word now...
20266 addFrameReference(BuildMI(*BB, MI, DL,
20267 TII->get(X86::FLDCW16m)), CWFrameIdx);
20269 // Restore the memory image of control word to original value
20270 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
20273 // Get the X86 opcode to use.
20275 switch (MI->getOpcode()) {
20276 default: llvm_unreachable("illegal opcode!");
20277 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
20278 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
20279 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
20280 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
20281 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
20282 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
20283 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
20284 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
20285 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
20289 MachineOperand &Op = MI->getOperand(0);
20291 AM.BaseType = X86AddressMode::RegBase;
20292 AM.Base.Reg = Op.getReg();
20294 AM.BaseType = X86AddressMode::FrameIndexBase;
20295 AM.Base.FrameIndex = Op.getIndex();
20297 Op = MI->getOperand(1);
20299 AM.Scale = Op.getImm();
20300 Op = MI->getOperand(2);
20302 AM.IndexReg = Op.getImm();
20303 Op = MI->getOperand(3);
20304 if (Op.isGlobal()) {
20305 AM.GV = Op.getGlobal();
20307 AM.Disp = Op.getImm();
20309 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM)
20310 .addReg(MI->getOperand(X86::AddrNumOperands).getReg());
20312 // Reload the original control word now.
20313 addFrameReference(BuildMI(*BB, MI, DL,
20314 TII->get(X86::FLDCW16m)), CWFrameIdx);
20316 MI->eraseFromParent(); // The pseudo instruction is gone now.
20319 // String/text processing lowering.
20320 case X86::PCMPISTRM128REG:
20321 case X86::VPCMPISTRM128REG:
20322 case X86::PCMPISTRM128MEM:
20323 case X86::VPCMPISTRM128MEM:
20324 case X86::PCMPESTRM128REG:
20325 case X86::VPCMPESTRM128REG:
20326 case X86::PCMPESTRM128MEM:
20327 case X86::VPCMPESTRM128MEM:
20328 assert(Subtarget->hasSSE42() &&
20329 "Target must have SSE4.2 or AVX features enabled");
20330 return EmitPCMPSTRM(MI, BB, BB->getParent()->getSubtarget().getInstrInfo());
20332 // String/text processing lowering.
20333 case X86::PCMPISTRIREG:
20334 case X86::VPCMPISTRIREG:
20335 case X86::PCMPISTRIMEM:
20336 case X86::VPCMPISTRIMEM:
20337 case X86::PCMPESTRIREG:
20338 case X86::VPCMPESTRIREG:
20339 case X86::PCMPESTRIMEM:
20340 case X86::VPCMPESTRIMEM:
20341 assert(Subtarget->hasSSE42() &&
20342 "Target must have SSE4.2 or AVX features enabled");
20343 return EmitPCMPSTRI(MI, BB, BB->getParent()->getSubtarget().getInstrInfo());
20345 // Thread synchronization.
20347 return EmitMonitor(MI, BB, BB->getParent()->getSubtarget().getInstrInfo(),
20352 return EmitXBegin(MI, BB, BB->getParent()->getSubtarget().getInstrInfo());
20354 case X86::VASTART_SAVE_XMM_REGS:
20355 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
20357 case X86::VAARG_64:
20358 return EmitVAARG64WithCustomInserter(MI, BB);
20360 case X86::EH_SjLj_SetJmp32:
20361 case X86::EH_SjLj_SetJmp64:
20362 return emitEHSjLjSetJmp(MI, BB);
20364 case X86::EH_SjLj_LongJmp32:
20365 case X86::EH_SjLj_LongJmp64:
20366 return emitEHSjLjLongJmp(MI, BB);
20368 case TargetOpcode::STACKMAP:
20369 case TargetOpcode::PATCHPOINT:
20370 return emitPatchPoint(MI, BB);
20372 case X86::VFMADDPDr213r:
20373 case X86::VFMADDPSr213r:
20374 case X86::VFMADDSDr213r:
20375 case X86::VFMADDSSr213r:
20376 case X86::VFMSUBPDr213r:
20377 case X86::VFMSUBPSr213r:
20378 case X86::VFMSUBSDr213r:
20379 case X86::VFMSUBSSr213r:
20380 case X86::VFNMADDPDr213r:
20381 case X86::VFNMADDPSr213r:
20382 case X86::VFNMADDSDr213r:
20383 case X86::VFNMADDSSr213r:
20384 case X86::VFNMSUBPDr213r:
20385 case X86::VFNMSUBPSr213r:
20386 case X86::VFNMSUBSDr213r:
20387 case X86::VFNMSUBSSr213r:
20388 case X86::VFMADDPDr213rY:
20389 case X86::VFMADDPSr213rY:
20390 case X86::VFMSUBPDr213rY:
20391 case X86::VFMSUBPSr213rY:
20392 case X86::VFNMADDPDr213rY:
20393 case X86::VFNMADDPSr213rY:
20394 case X86::VFNMSUBPDr213rY:
20395 case X86::VFNMSUBPSr213rY:
20396 return emitFMA3Instr(MI, BB);
20400 //===----------------------------------------------------------------------===//
20401 // X86 Optimization Hooks
20402 //===----------------------------------------------------------------------===//
20404 void X86TargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
20407 const SelectionDAG &DAG,
20408 unsigned Depth) const {
20409 unsigned BitWidth = KnownZero.getBitWidth();
20410 unsigned Opc = Op.getOpcode();
20411 assert((Opc >= ISD::BUILTIN_OP_END ||
20412 Opc == ISD::INTRINSIC_WO_CHAIN ||
20413 Opc == ISD::INTRINSIC_W_CHAIN ||
20414 Opc == ISD::INTRINSIC_VOID) &&
20415 "Should use MaskedValueIsZero if you don't know whether Op"
20416 " is a target node!");
20418 KnownZero = KnownOne = APInt(BitWidth, 0); // Don't know anything.
20432 // These nodes' second result is a boolean.
20433 if (Op.getResNo() == 0)
20436 case X86ISD::SETCC:
20437 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1);
20439 case ISD::INTRINSIC_WO_CHAIN: {
20440 unsigned IntId = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
20441 unsigned NumLoBits = 0;
20444 case Intrinsic::x86_sse_movmsk_ps:
20445 case Intrinsic::x86_avx_movmsk_ps_256:
20446 case Intrinsic::x86_sse2_movmsk_pd:
20447 case Intrinsic::x86_avx_movmsk_pd_256:
20448 case Intrinsic::x86_mmx_pmovmskb:
20449 case Intrinsic::x86_sse2_pmovmskb_128:
20450 case Intrinsic::x86_avx2_pmovmskb: {
20451 // High bits of movmskp{s|d}, pmovmskb are known zero.
20453 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
20454 case Intrinsic::x86_sse_movmsk_ps: NumLoBits = 4; break;
20455 case Intrinsic::x86_avx_movmsk_ps_256: NumLoBits = 8; break;
20456 case Intrinsic::x86_sse2_movmsk_pd: NumLoBits = 2; break;
20457 case Intrinsic::x86_avx_movmsk_pd_256: NumLoBits = 4; break;
20458 case Intrinsic::x86_mmx_pmovmskb: NumLoBits = 8; break;
20459 case Intrinsic::x86_sse2_pmovmskb_128: NumLoBits = 16; break;
20460 case Intrinsic::x86_avx2_pmovmskb: NumLoBits = 32; break;
20462 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - NumLoBits);
20471 unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(
20473 const SelectionDAG &,
20474 unsigned Depth) const {
20475 // SETCC_CARRY sets the dest to ~0 for true or 0 for false.
20476 if (Op.getOpcode() == X86ISD::SETCC_CARRY)
20477 return Op.getValueType().getScalarType().getSizeInBits();
20483 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
20484 /// node is a GlobalAddress + offset.
20485 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
20486 const GlobalValue* &GA,
20487 int64_t &Offset) const {
20488 if (N->getOpcode() == X86ISD::Wrapper) {
20489 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
20490 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
20491 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
20495 return TargetLowering::isGAPlusOffset(N, GA, Offset);
20498 /// isShuffleHigh128VectorInsertLow - Checks whether the shuffle node is the
20499 /// same as extracting the high 128-bit part of 256-bit vector and then
20500 /// inserting the result into the low part of a new 256-bit vector
20501 static bool isShuffleHigh128VectorInsertLow(ShuffleVectorSDNode *SVOp) {
20502 EVT VT = SVOp->getValueType(0);
20503 unsigned NumElems = VT.getVectorNumElements();
20505 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
20506 for (unsigned i = 0, j = NumElems/2; i != NumElems/2; ++i, ++j)
20507 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
20508 SVOp->getMaskElt(j) >= 0)
20514 /// isShuffleLow128VectorInsertHigh - Checks whether the shuffle node is the
20515 /// same as extracting the low 128-bit part of 256-bit vector and then
20516 /// inserting the result into the high part of a new 256-bit vector
20517 static bool isShuffleLow128VectorInsertHigh(ShuffleVectorSDNode *SVOp) {
20518 EVT VT = SVOp->getValueType(0);
20519 unsigned NumElems = VT.getVectorNumElements();
20521 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
20522 for (unsigned i = NumElems/2, j = 0; i != NumElems; ++i, ++j)
20523 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
20524 SVOp->getMaskElt(j) >= 0)
20530 /// PerformShuffleCombine256 - Performs shuffle combines for 256-bit vectors.
20531 static SDValue PerformShuffleCombine256(SDNode *N, SelectionDAG &DAG,
20532 TargetLowering::DAGCombinerInfo &DCI,
20533 const X86Subtarget* Subtarget) {
20535 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
20536 SDValue V1 = SVOp->getOperand(0);
20537 SDValue V2 = SVOp->getOperand(1);
20538 EVT VT = SVOp->getValueType(0);
20539 unsigned NumElems = VT.getVectorNumElements();
20541 if (V1.getOpcode() == ISD::CONCAT_VECTORS &&
20542 V2.getOpcode() == ISD::CONCAT_VECTORS) {
20546 // V UNDEF BUILD_VECTOR UNDEF
20548 // CONCAT_VECTOR CONCAT_VECTOR
20551 // RESULT: V + zero extended
20553 if (V2.getOperand(0).getOpcode() != ISD::BUILD_VECTOR ||
20554 V2.getOperand(1).getOpcode() != ISD::UNDEF ||
20555 V1.getOperand(1).getOpcode() != ISD::UNDEF)
20558 if (!ISD::isBuildVectorAllZeros(V2.getOperand(0).getNode()))
20561 // To match the shuffle mask, the first half of the mask should
20562 // be exactly the first vector, and all the rest a splat with the
20563 // first element of the second one.
20564 for (unsigned i = 0; i != NumElems/2; ++i)
20565 if (!isUndefOrEqual(SVOp->getMaskElt(i), i) ||
20566 !isUndefOrEqual(SVOp->getMaskElt(i+NumElems/2), NumElems))
20569 // If V1 is coming from a vector load then just fold to a VZEXT_LOAD.
20570 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(V1.getOperand(0))) {
20571 if (Ld->hasNUsesOfValue(1, 0)) {
20572 SDVTList Tys = DAG.getVTList(MVT::v4i64, MVT::Other);
20573 SDValue Ops[] = { Ld->getChain(), Ld->getBasePtr() };
20575 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops,
20577 Ld->getPointerInfo(),
20578 Ld->getAlignment(),
20579 false/*isVolatile*/, true/*ReadMem*/,
20580 false/*WriteMem*/);
20582 // Make sure the newly-created LOAD is in the same position as Ld in
20583 // terms of dependency. We create a TokenFactor for Ld and ResNode,
20584 // and update uses of Ld's output chain to use the TokenFactor.
20585 if (Ld->hasAnyUseOfValue(1)) {
20586 SDValue NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
20587 SDValue(Ld, 1), SDValue(ResNode.getNode(), 1));
20588 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), NewChain);
20589 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(Ld, 1),
20590 SDValue(ResNode.getNode(), 1));
20593 return DAG.getNode(ISD::BITCAST, dl, VT, ResNode);
20597 // Emit a zeroed vector and insert the desired subvector on its
20599 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
20600 SDValue InsV = Insert128BitVector(Zeros, V1.getOperand(0), 0, DAG, dl);
20601 return DCI.CombineTo(N, InsV);
20604 //===--------------------------------------------------------------------===//
20605 // Combine some shuffles into subvector extracts and inserts:
20608 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
20609 if (isShuffleHigh128VectorInsertLow(SVOp)) {
20610 SDValue V = Extract128BitVector(V1, NumElems/2, DAG, dl);
20611 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, 0, DAG, dl);
20612 return DCI.CombineTo(N, InsV);
20615 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
20616 if (isShuffleLow128VectorInsertHigh(SVOp)) {
20617 SDValue V = Extract128BitVector(V1, 0, DAG, dl);
20618 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, NumElems/2, DAG, dl);
20619 return DCI.CombineTo(N, InsV);
20625 /// \brief Combine an arbitrary chain of shuffles into a single instruction if
20628 /// This is the leaf of the recursive combinine below. When we have found some
20629 /// chain of single-use x86 shuffle instructions and accumulated the combined
20630 /// shuffle mask represented by them, this will try to pattern match that mask
20631 /// into either a single instruction if there is a special purpose instruction
20632 /// for this operation, or into a PSHUFB instruction which is a fully general
20633 /// instruction but should only be used to replace chains over a certain depth.
20634 static bool combineX86ShuffleChain(SDValue Op, SDValue Root, ArrayRef<int> Mask,
20635 int Depth, bool HasPSHUFB, SelectionDAG &DAG,
20636 TargetLowering::DAGCombinerInfo &DCI,
20637 const X86Subtarget *Subtarget) {
20638 assert(!Mask.empty() && "Cannot combine an empty shuffle mask!");
20640 // Find the operand that enters the chain. Note that multiple uses are OK
20641 // here, we're not going to remove the operand we find.
20642 SDValue Input = Op.getOperand(0);
20643 while (Input.getOpcode() == ISD::BITCAST)
20644 Input = Input.getOperand(0);
20646 MVT VT = Input.getSimpleValueType();
20647 MVT RootVT = Root.getSimpleValueType();
20650 // Just remove no-op shuffle masks.
20651 if (Mask.size() == 1) {
20652 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Input),
20657 // Use the float domain if the operand type is a floating point type.
20658 bool FloatDomain = VT.isFloatingPoint();
20660 // For floating point shuffles, we don't have free copies in the shuffle
20661 // instructions or the ability to load as part of the instruction, so
20662 // canonicalize their shuffles to UNPCK or MOV variants.
20664 // Note that even with AVX we prefer the PSHUFD form of shuffle for integer
20665 // vectors because it can have a load folded into it that UNPCK cannot. This
20666 // doesn't preclude something switching to the shorter encoding post-RA.
20668 if (Mask.equals(0, 0) || Mask.equals(1, 1)) {
20669 bool Lo = Mask.equals(0, 0);
20672 // Check if we have SSE3 which will let us use MOVDDUP. That instruction
20673 // is no slower than UNPCKLPD but has the option to fold the input operand
20674 // into even an unaligned memory load.
20675 if (Lo && Subtarget->hasSSE3()) {
20676 Shuffle = X86ISD::MOVDDUP;
20677 ShuffleVT = MVT::v2f64;
20679 // We have MOVLHPS and MOVHLPS throughout SSE and they encode smaller
20680 // than the UNPCK variants.
20681 Shuffle = Lo ? X86ISD::MOVLHPS : X86ISD::MOVHLPS;
20682 ShuffleVT = MVT::v4f32;
20684 if (Depth == 1 && Root->getOpcode() == Shuffle)
20685 return false; // Nothing to do!
20686 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
20687 DCI.AddToWorklist(Op.getNode());
20688 if (Shuffle == X86ISD::MOVDDUP)
20689 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op);
20691 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
20692 DCI.AddToWorklist(Op.getNode());
20693 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
20697 if (Subtarget->hasSSE3() &&
20698 (Mask.equals(0, 0, 2, 2) || Mask.equals(1, 1, 3, 3))) {
20699 bool Lo = Mask.equals(0, 0, 2, 2);
20700 unsigned Shuffle = Lo ? X86ISD::MOVSLDUP : X86ISD::MOVSHDUP;
20701 MVT ShuffleVT = MVT::v4f32;
20702 if (Depth == 1 && Root->getOpcode() == Shuffle)
20703 return false; // Nothing to do!
20704 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
20705 DCI.AddToWorklist(Op.getNode());
20706 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op);
20707 DCI.AddToWorklist(Op.getNode());
20708 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
20712 if (Mask.equals(0, 0, 1, 1) || Mask.equals(2, 2, 3, 3)) {
20713 bool Lo = Mask.equals(0, 0, 1, 1);
20714 unsigned Shuffle = Lo ? X86ISD::UNPCKL : X86ISD::UNPCKH;
20715 MVT ShuffleVT = MVT::v4f32;
20716 if (Depth == 1 && Root->getOpcode() == Shuffle)
20717 return false; // Nothing to do!
20718 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
20719 DCI.AddToWorklist(Op.getNode());
20720 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
20721 DCI.AddToWorklist(Op.getNode());
20722 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
20728 // We always canonicalize the 8 x i16 and 16 x i8 shuffles into their UNPCK
20729 // variants as none of these have single-instruction variants that are
20730 // superior to the UNPCK formulation.
20731 if (!FloatDomain &&
20732 (Mask.equals(0, 0, 1, 1, 2, 2, 3, 3) ||
20733 Mask.equals(4, 4, 5, 5, 6, 6, 7, 7) ||
20734 Mask.equals(0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7) ||
20735 Mask.equals(8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15,
20737 bool Lo = Mask[0] == 0;
20738 unsigned Shuffle = Lo ? X86ISD::UNPCKL : X86ISD::UNPCKH;
20739 if (Depth == 1 && Root->getOpcode() == Shuffle)
20740 return false; // Nothing to do!
20742 switch (Mask.size()) {
20744 ShuffleVT = MVT::v8i16;
20747 ShuffleVT = MVT::v16i8;
20750 llvm_unreachable("Impossible mask size!");
20752 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
20753 DCI.AddToWorklist(Op.getNode());
20754 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
20755 DCI.AddToWorklist(Op.getNode());
20756 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
20761 // Don't try to re-form single instruction chains under any circumstances now
20762 // that we've done encoding canonicalization for them.
20766 // If we have 3 or more shuffle instructions or a chain involving PSHUFB, we
20767 // can replace them with a single PSHUFB instruction profitably. Intel's
20768 // manuals suggest only using PSHUFB if doing so replacing 5 instructions, but
20769 // in practice PSHUFB tends to be *very* fast so we're more aggressive.
20770 if ((Depth >= 3 || HasPSHUFB) && Subtarget->hasSSSE3()) {
20771 SmallVector<SDValue, 16> PSHUFBMask;
20772 assert(Mask.size() <= 16 && "Can't shuffle elements smaller than bytes!");
20773 int Ratio = 16 / Mask.size();
20774 for (unsigned i = 0; i < 16; ++i) {
20775 if (Mask[i / Ratio] == SM_SentinelUndef) {
20776 PSHUFBMask.push_back(DAG.getUNDEF(MVT::i8));
20779 int M = Mask[i / Ratio] != SM_SentinelZero
20780 ? Ratio * Mask[i / Ratio] + i % Ratio
20782 PSHUFBMask.push_back(DAG.getConstant(M, MVT::i8));
20784 Op = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Input);
20785 DCI.AddToWorklist(Op.getNode());
20786 SDValue PSHUFBMaskOp =
20787 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, PSHUFBMask);
20788 DCI.AddToWorklist(PSHUFBMaskOp.getNode());
20789 Op = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, Op, PSHUFBMaskOp);
20790 DCI.AddToWorklist(Op.getNode());
20791 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
20796 // Failed to find any combines.
20800 /// \brief Fully generic combining of x86 shuffle instructions.
20802 /// This should be the last combine run over the x86 shuffle instructions. Once
20803 /// they have been fully optimized, this will recursively consider all chains
20804 /// of single-use shuffle instructions, build a generic model of the cumulative
20805 /// shuffle operation, and check for simpler instructions which implement this
20806 /// operation. We use this primarily for two purposes:
20808 /// 1) Collapse generic shuffles to specialized single instructions when
20809 /// equivalent. In most cases, this is just an encoding size win, but
20810 /// sometimes we will collapse multiple generic shuffles into a single
20811 /// special-purpose shuffle.
20812 /// 2) Look for sequences of shuffle instructions with 3 or more total
20813 /// instructions, and replace them with the slightly more expensive SSSE3
20814 /// PSHUFB instruction if available. We do this as the last combining step
20815 /// to ensure we avoid using PSHUFB if we can implement the shuffle with
20816 /// a suitable short sequence of other instructions. The PHUFB will either
20817 /// use a register or have to read from memory and so is slightly (but only
20818 /// slightly) more expensive than the other shuffle instructions.
20820 /// Because this is inherently a quadratic operation (for each shuffle in
20821 /// a chain, we recurse up the chain), the depth is limited to 8 instructions.
20822 /// This should never be an issue in practice as the shuffle lowering doesn't
20823 /// produce sequences of more than 8 instructions.
20825 /// FIXME: We will currently miss some cases where the redundant shuffling
20826 /// would simplify under the threshold for PSHUFB formation because of
20827 /// combine-ordering. To fix this, we should do the redundant instruction
20828 /// combining in this recursive walk.
20829 static bool combineX86ShufflesRecursively(SDValue Op, SDValue Root,
20830 ArrayRef<int> RootMask,
20831 int Depth, bool HasPSHUFB,
20833 TargetLowering::DAGCombinerInfo &DCI,
20834 const X86Subtarget *Subtarget) {
20835 // Bound the depth of our recursive combine because this is ultimately
20836 // quadratic in nature.
20840 // Directly rip through bitcasts to find the underlying operand.
20841 while (Op.getOpcode() == ISD::BITCAST && Op.getOperand(0).hasOneUse())
20842 Op = Op.getOperand(0);
20844 MVT VT = Op.getSimpleValueType();
20845 if (!VT.isVector())
20846 return false; // Bail if we hit a non-vector.
20847 // FIXME: This routine should be taught about 256-bit shuffles, or a 256-bit
20848 // version should be added.
20849 if (VT.getSizeInBits() != 128)
20852 assert(Root.getSimpleValueType().isVector() &&
20853 "Shuffles operate on vector types!");
20854 assert(VT.getSizeInBits() == Root.getSimpleValueType().getSizeInBits() &&
20855 "Can only combine shuffles of the same vector register size.");
20857 if (!isTargetShuffle(Op.getOpcode()))
20859 SmallVector<int, 16> OpMask;
20861 bool HaveMask = getTargetShuffleMask(Op.getNode(), VT, OpMask, IsUnary);
20862 // We only can combine unary shuffles which we can decode the mask for.
20863 if (!HaveMask || !IsUnary)
20866 assert(VT.getVectorNumElements() == OpMask.size() &&
20867 "Different mask size from vector size!");
20868 assert(((RootMask.size() > OpMask.size() &&
20869 RootMask.size() % OpMask.size() == 0) ||
20870 (OpMask.size() > RootMask.size() &&
20871 OpMask.size() % RootMask.size() == 0) ||
20872 OpMask.size() == RootMask.size()) &&
20873 "The smaller number of elements must divide the larger.");
20874 int RootRatio = std::max<int>(1, OpMask.size() / RootMask.size());
20875 int OpRatio = std::max<int>(1, RootMask.size() / OpMask.size());
20876 assert(((RootRatio == 1 && OpRatio == 1) ||
20877 (RootRatio == 1) != (OpRatio == 1)) &&
20878 "Must not have a ratio for both incoming and op masks!");
20880 SmallVector<int, 16> Mask;
20881 Mask.reserve(std::max(OpMask.size(), RootMask.size()));
20883 // Merge this shuffle operation's mask into our accumulated mask. Note that
20884 // this shuffle's mask will be the first applied to the input, followed by the
20885 // root mask to get us all the way to the root value arrangement. The reason
20886 // for this order is that we are recursing up the operation chain.
20887 for (int i = 0, e = std::max(OpMask.size(), RootMask.size()); i < e; ++i) {
20888 int RootIdx = i / RootRatio;
20889 if (RootMask[RootIdx] < 0) {
20890 // This is a zero or undef lane, we're done.
20891 Mask.push_back(RootMask[RootIdx]);
20895 int RootMaskedIdx = RootMask[RootIdx] * RootRatio + i % RootRatio;
20896 int OpIdx = RootMaskedIdx / OpRatio;
20897 if (OpMask[OpIdx] < 0) {
20898 // The incoming lanes are zero or undef, it doesn't matter which ones we
20900 Mask.push_back(OpMask[OpIdx]);
20904 // Ok, we have non-zero lanes, map them through.
20905 Mask.push_back(OpMask[OpIdx] * OpRatio +
20906 RootMaskedIdx % OpRatio);
20909 // See if we can recurse into the operand to combine more things.
20910 switch (Op.getOpcode()) {
20911 case X86ISD::PSHUFB:
20913 case X86ISD::PSHUFD:
20914 case X86ISD::PSHUFHW:
20915 case X86ISD::PSHUFLW:
20916 if (Op.getOperand(0).hasOneUse() &&
20917 combineX86ShufflesRecursively(Op.getOperand(0), Root, Mask, Depth + 1,
20918 HasPSHUFB, DAG, DCI, Subtarget))
20922 case X86ISD::UNPCKL:
20923 case X86ISD::UNPCKH:
20924 assert(Op.getOperand(0) == Op.getOperand(1) && "We only combine unary shuffles!");
20925 // We can't check for single use, we have to check that this shuffle is the only user.
20926 if (Op->isOnlyUserOf(Op.getOperand(0).getNode()) &&
20927 combineX86ShufflesRecursively(Op.getOperand(0), Root, Mask, Depth + 1,
20928 HasPSHUFB, DAG, DCI, Subtarget))
20933 // Minor canonicalization of the accumulated shuffle mask to make it easier
20934 // to match below. All this does is detect masks with squential pairs of
20935 // elements, and shrink them to the half-width mask. It does this in a loop
20936 // so it will reduce the size of the mask to the minimal width mask which
20937 // performs an equivalent shuffle.
20938 SmallVector<int, 16> WidenedMask;
20939 while (Mask.size() > 1 && canWidenShuffleElements(Mask, WidenedMask)) {
20940 Mask = std::move(WidenedMask);
20941 WidenedMask.clear();
20944 return combineX86ShuffleChain(Op, Root, Mask, Depth, HasPSHUFB, DAG, DCI,
20948 /// \brief Get the PSHUF-style mask from PSHUF node.
20950 /// This is a very minor wrapper around getTargetShuffleMask to easy forming v4
20951 /// PSHUF-style masks that can be reused with such instructions.
20952 static SmallVector<int, 4> getPSHUFShuffleMask(SDValue N) {
20953 SmallVector<int, 4> Mask;
20955 bool HaveMask = getTargetShuffleMask(N.getNode(), N.getSimpleValueType(), Mask, IsUnary);
20959 switch (N.getOpcode()) {
20960 case X86ISD::PSHUFD:
20962 case X86ISD::PSHUFLW:
20965 case X86ISD::PSHUFHW:
20966 Mask.erase(Mask.begin(), Mask.begin() + 4);
20967 for (int &M : Mask)
20971 llvm_unreachable("No valid shuffle instruction found!");
20975 /// \brief Search for a combinable shuffle across a chain ending in pshufd.
20977 /// We walk up the chain and look for a combinable shuffle, skipping over
20978 /// shuffles that we could hoist this shuffle's transformation past without
20979 /// altering anything.
20981 combineRedundantDWordShuffle(SDValue N, MutableArrayRef<int> Mask,
20983 TargetLowering::DAGCombinerInfo &DCI) {
20984 assert(N.getOpcode() == X86ISD::PSHUFD &&
20985 "Called with something other than an x86 128-bit half shuffle!");
20988 // Walk up a single-use chain looking for a combinable shuffle. Keep a stack
20989 // of the shuffles in the chain so that we can form a fresh chain to replace
20991 SmallVector<SDValue, 8> Chain;
20992 SDValue V = N.getOperand(0);
20993 for (; V.hasOneUse(); V = V.getOperand(0)) {
20994 switch (V.getOpcode()) {
20996 return SDValue(); // Nothing combined!
20999 // Skip bitcasts as we always know the type for the target specific
21003 case X86ISD::PSHUFD:
21004 // Found another dword shuffle.
21007 case X86ISD::PSHUFLW:
21008 // Check that the low words (being shuffled) are the identity in the
21009 // dword shuffle, and the high words are self-contained.
21010 if (Mask[0] != 0 || Mask[1] != 1 ||
21011 !(Mask[2] >= 2 && Mask[2] < 4 && Mask[3] >= 2 && Mask[3] < 4))
21014 Chain.push_back(V);
21017 case X86ISD::PSHUFHW:
21018 // Check that the high words (being shuffled) are the identity in the
21019 // dword shuffle, and the low words are self-contained.
21020 if (Mask[2] != 2 || Mask[3] != 3 ||
21021 !(Mask[0] >= 0 && Mask[0] < 2 && Mask[1] >= 0 && Mask[1] < 2))
21024 Chain.push_back(V);
21027 case X86ISD::UNPCKL:
21028 case X86ISD::UNPCKH:
21029 // For either i8 -> i16 or i16 -> i32 unpacks, we can combine a dword
21030 // shuffle into a preceding word shuffle.
21031 if (V.getValueType() != MVT::v16i8 && V.getValueType() != MVT::v8i16)
21034 // Search for a half-shuffle which we can combine with.
21035 unsigned CombineOp =
21036 V.getOpcode() == X86ISD::UNPCKL ? X86ISD::PSHUFLW : X86ISD::PSHUFHW;
21037 if (V.getOperand(0) != V.getOperand(1) ||
21038 !V->isOnlyUserOf(V.getOperand(0).getNode()))
21040 Chain.push_back(V);
21041 V = V.getOperand(0);
21043 switch (V.getOpcode()) {
21045 return SDValue(); // Nothing to combine.
21047 case X86ISD::PSHUFLW:
21048 case X86ISD::PSHUFHW:
21049 if (V.getOpcode() == CombineOp)
21052 Chain.push_back(V);
21056 V = V.getOperand(0);
21060 } while (V.hasOneUse());
21063 // Break out of the loop if we break out of the switch.
21067 if (!V.hasOneUse())
21068 // We fell out of the loop without finding a viable combining instruction.
21071 // Merge this node's mask and our incoming mask.
21072 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
21073 for (int &M : Mask)
21075 V = DAG.getNode(V.getOpcode(), DL, V.getValueType(), V.getOperand(0),
21076 getV4X86ShuffleImm8ForMask(Mask, DAG));
21078 // Rebuild the chain around this new shuffle.
21079 while (!Chain.empty()) {
21080 SDValue W = Chain.pop_back_val();
21082 if (V.getValueType() != W.getOperand(0).getValueType())
21083 V = DAG.getNode(ISD::BITCAST, DL, W.getOperand(0).getValueType(), V);
21085 switch (W.getOpcode()) {
21087 llvm_unreachable("Only PSHUF and UNPCK instructions get here!");
21089 case X86ISD::UNPCKL:
21090 case X86ISD::UNPCKH:
21091 V = DAG.getNode(W.getOpcode(), DL, W.getValueType(), V, V);
21094 case X86ISD::PSHUFD:
21095 case X86ISD::PSHUFLW:
21096 case X86ISD::PSHUFHW:
21097 V = DAG.getNode(W.getOpcode(), DL, W.getValueType(), V, W.getOperand(1));
21101 if (V.getValueType() != N.getValueType())
21102 V = DAG.getNode(ISD::BITCAST, DL, N.getValueType(), V);
21104 // Return the new chain to replace N.
21108 /// \brief Search for a combinable shuffle across a chain ending in pshuflw or pshufhw.
21110 /// We walk up the chain, skipping shuffles of the other half and looking
21111 /// through shuffles which switch halves trying to find a shuffle of the same
21112 /// pair of dwords.
21113 static bool combineRedundantHalfShuffle(SDValue N, MutableArrayRef<int> Mask,
21115 TargetLowering::DAGCombinerInfo &DCI) {
21117 (N.getOpcode() == X86ISD::PSHUFLW || N.getOpcode() == X86ISD::PSHUFHW) &&
21118 "Called with something other than an x86 128-bit half shuffle!");
21120 unsigned CombineOpcode = N.getOpcode();
21122 // Walk up a single-use chain looking for a combinable shuffle.
21123 SDValue V = N.getOperand(0);
21124 for (; V.hasOneUse(); V = V.getOperand(0)) {
21125 switch (V.getOpcode()) {
21127 return false; // Nothing combined!
21130 // Skip bitcasts as we always know the type for the target specific
21134 case X86ISD::PSHUFLW:
21135 case X86ISD::PSHUFHW:
21136 if (V.getOpcode() == CombineOpcode)
21139 // Other-half shuffles are no-ops.
21142 // Break out of the loop if we break out of the switch.
21146 if (!V.hasOneUse())
21147 // We fell out of the loop without finding a viable combining instruction.
21150 // Combine away the bottom node as its shuffle will be accumulated into
21151 // a preceding shuffle.
21152 DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
21154 // Record the old value.
21157 // Merge this node's mask and our incoming mask (adjusted to account for all
21158 // the pshufd instructions encountered).
21159 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
21160 for (int &M : Mask)
21162 V = DAG.getNode(V.getOpcode(), DL, MVT::v8i16, V.getOperand(0),
21163 getV4X86ShuffleImm8ForMask(Mask, DAG));
21165 // Check that the shuffles didn't cancel each other out. If not, we need to
21166 // combine to the new one.
21168 // Replace the combinable shuffle with the combined one, updating all users
21169 // so that we re-evaluate the chain here.
21170 DCI.CombineTo(Old.getNode(), V, /*AddTo*/ true);
21175 /// \brief Try to combine x86 target specific shuffles.
21176 static SDValue PerformTargetShuffleCombine(SDValue N, SelectionDAG &DAG,
21177 TargetLowering::DAGCombinerInfo &DCI,
21178 const X86Subtarget *Subtarget) {
21180 MVT VT = N.getSimpleValueType();
21181 SmallVector<int, 4> Mask;
21183 switch (N.getOpcode()) {
21184 case X86ISD::PSHUFD:
21185 case X86ISD::PSHUFLW:
21186 case X86ISD::PSHUFHW:
21187 Mask = getPSHUFShuffleMask(N);
21188 assert(Mask.size() == 4);
21194 // Nuke no-op shuffles that show up after combining.
21195 if (isNoopShuffleMask(Mask))
21196 return DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
21198 // Look for simplifications involving one or two shuffle instructions.
21199 SDValue V = N.getOperand(0);
21200 switch (N.getOpcode()) {
21203 case X86ISD::PSHUFLW:
21204 case X86ISD::PSHUFHW:
21205 assert(VT == MVT::v8i16);
21208 if (combineRedundantHalfShuffle(N, Mask, DAG, DCI))
21209 return SDValue(); // We combined away this shuffle, so we're done.
21211 // See if this reduces to a PSHUFD which is no more expensive and can
21212 // combine with more operations. Note that it has to at least flip the
21213 // dwords as otherwise it would have been removed as a no-op.
21214 if (Mask[0] == 2 && Mask[1] == 3 && Mask[2] == 0 && Mask[3] == 1) {
21215 int DMask[] = {0, 1, 2, 3};
21216 int DOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 2;
21217 DMask[DOffset + 0] = DOffset + 1;
21218 DMask[DOffset + 1] = DOffset + 0;
21219 V = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V);
21220 DCI.AddToWorklist(V.getNode());
21221 V = DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V,
21222 getV4X86ShuffleImm8ForMask(DMask, DAG));
21223 DCI.AddToWorklist(V.getNode());
21224 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V);
21227 // Look for shuffle patterns which can be implemented as a single unpack.
21228 // FIXME: This doesn't handle the location of the PSHUFD generically, and
21229 // only works when we have a PSHUFD followed by two half-shuffles.
21230 if (Mask[0] == Mask[1] && Mask[2] == Mask[3] &&
21231 (V.getOpcode() == X86ISD::PSHUFLW ||
21232 V.getOpcode() == X86ISD::PSHUFHW) &&
21233 V.getOpcode() != N.getOpcode() &&
21235 SDValue D = V.getOperand(0);
21236 while (D.getOpcode() == ISD::BITCAST && D.hasOneUse())
21237 D = D.getOperand(0);
21238 if (D.getOpcode() == X86ISD::PSHUFD && D.hasOneUse()) {
21239 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
21240 SmallVector<int, 4> DMask = getPSHUFShuffleMask(D);
21241 int NOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
21242 int VOffset = V.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
21244 for (int i = 0; i < 4; ++i) {
21245 WordMask[i + NOffset] = Mask[i] + NOffset;
21246 WordMask[i + VOffset] = VMask[i] + VOffset;
21248 // Map the word mask through the DWord mask.
21250 for (int i = 0; i < 8; ++i)
21251 MappedMask[i] = 2 * DMask[WordMask[i] / 2] + WordMask[i] % 2;
21252 const int UnpackLoMask[] = {0, 0, 1, 1, 2, 2, 3, 3};
21253 const int UnpackHiMask[] = {4, 4, 5, 5, 6, 6, 7, 7};
21254 if (std::equal(std::begin(MappedMask), std::end(MappedMask),
21255 std::begin(UnpackLoMask)) ||
21256 std::equal(std::begin(MappedMask), std::end(MappedMask),
21257 std::begin(UnpackHiMask))) {
21258 // We can replace all three shuffles with an unpack.
21259 V = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, D.getOperand(0));
21260 DCI.AddToWorklist(V.getNode());
21261 return DAG.getNode(MappedMask[0] == 0 ? X86ISD::UNPCKL
21263 DL, MVT::v8i16, V, V);
21270 case X86ISD::PSHUFD:
21271 if (SDValue NewN = combineRedundantDWordShuffle(N, Mask, DAG, DCI))
21280 /// \brief Try to combine a shuffle into a target-specific add-sub node.
21282 /// We combine this directly on the abstract vector shuffle nodes so it is
21283 /// easier to generically match. We also insert dummy vector shuffle nodes for
21284 /// the operands which explicitly discard the lanes which are unused by this
21285 /// operation to try to flow through the rest of the combiner the fact that
21286 /// they're unused.
21287 static SDValue combineShuffleToAddSub(SDNode *N, SelectionDAG &DAG) {
21289 EVT VT = N->getValueType(0);
21291 // We only handle target-independent shuffles.
21292 // FIXME: It would be easy and harmless to use the target shuffle mask
21293 // extraction tool to support more.
21294 if (N->getOpcode() != ISD::VECTOR_SHUFFLE)
21297 auto *SVN = cast<ShuffleVectorSDNode>(N);
21298 ArrayRef<int> Mask = SVN->getMask();
21299 SDValue V1 = N->getOperand(0);
21300 SDValue V2 = N->getOperand(1);
21302 // We require the first shuffle operand to be the SUB node, and the second to
21303 // be the ADD node.
21304 // FIXME: We should support the commuted patterns.
21305 if (V1->getOpcode() != ISD::FSUB || V2->getOpcode() != ISD::FADD)
21308 // If there are other uses of these operations we can't fold them.
21309 if (!V1->hasOneUse() || !V2->hasOneUse())
21312 // Ensure that both operations have the same operands. Note that we can
21313 // commute the FADD operands.
21314 SDValue LHS = V1->getOperand(0), RHS = V1->getOperand(1);
21315 if ((V2->getOperand(0) != LHS || V2->getOperand(1) != RHS) &&
21316 (V2->getOperand(0) != RHS || V2->getOperand(1) != LHS))
21319 // We're looking for blends between FADD and FSUB nodes. We insist on these
21320 // nodes being lined up in a specific expected pattern.
21321 if (!(isShuffleEquivalent(Mask, 0, 3) ||
21322 isShuffleEquivalent(Mask, 0, 5, 2, 7) ||
21323 isShuffleEquivalent(Mask, 0, 9, 2, 11, 4, 13, 6, 15)))
21326 // Only specific types are legal at this point, assert so we notice if and
21327 // when these change.
21328 assert((VT == MVT::v4f32 || VT == MVT::v2f64 || VT == MVT::v8f32 ||
21329 VT == MVT::v4f64) &&
21330 "Unknown vector type encountered!");
21332 return DAG.getNode(X86ISD::ADDSUB, DL, VT, LHS, RHS);
21335 /// PerformShuffleCombine - Performs several different shuffle combines.
21336 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
21337 TargetLowering::DAGCombinerInfo &DCI,
21338 const X86Subtarget *Subtarget) {
21340 SDValue N0 = N->getOperand(0);
21341 SDValue N1 = N->getOperand(1);
21342 EVT VT = N->getValueType(0);
21344 // Don't create instructions with illegal types after legalize types has run.
21345 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
21346 if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType()))
21349 // If we have legalized the vector types, look for blends of FADD and FSUB
21350 // nodes that we can fuse into an ADDSUB node.
21351 if (TLI.isTypeLegal(VT) && Subtarget->hasSSE3())
21352 if (SDValue AddSub = combineShuffleToAddSub(N, DAG))
21355 // Combine 256-bit vector shuffles. This is only profitable when in AVX mode
21356 if (Subtarget->hasFp256() && VT.is256BitVector() &&
21357 N->getOpcode() == ISD::VECTOR_SHUFFLE)
21358 return PerformShuffleCombine256(N, DAG, DCI, Subtarget);
21360 // During Type Legalization, when promoting illegal vector types,
21361 // the backend might introduce new shuffle dag nodes and bitcasts.
21363 // This code performs the following transformation:
21364 // fold: (shuffle (bitcast (BINOP A, B)), Undef, <Mask>) ->
21365 // (shuffle (BINOP (bitcast A), (bitcast B)), Undef, <Mask>)
21367 // We do this only if both the bitcast and the BINOP dag nodes have
21368 // one use. Also, perform this transformation only if the new binary
21369 // operation is legal. This is to avoid introducing dag nodes that
21370 // potentially need to be further expanded (or custom lowered) into a
21371 // less optimal sequence of dag nodes.
21372 if (!DCI.isBeforeLegalize() && DCI.isBeforeLegalizeOps() &&
21373 N1.getOpcode() == ISD::UNDEF && N0.hasOneUse() &&
21374 N0.getOpcode() == ISD::BITCAST) {
21375 SDValue BC0 = N0.getOperand(0);
21376 EVT SVT = BC0.getValueType();
21377 unsigned Opcode = BC0.getOpcode();
21378 unsigned NumElts = VT.getVectorNumElements();
21380 if (BC0.hasOneUse() && SVT.isVector() &&
21381 SVT.getVectorNumElements() * 2 == NumElts &&
21382 TLI.isOperationLegal(Opcode, VT)) {
21383 bool CanFold = false;
21395 unsigned SVTNumElts = SVT.getVectorNumElements();
21396 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
21397 for (unsigned i = 0, e = SVTNumElts; i != e && CanFold; ++i)
21398 CanFold = SVOp->getMaskElt(i) == (int)(i * 2);
21399 for (unsigned i = SVTNumElts, e = NumElts; i != e && CanFold; ++i)
21400 CanFold = SVOp->getMaskElt(i) < 0;
21403 SDValue BC00 = DAG.getNode(ISD::BITCAST, dl, VT, BC0.getOperand(0));
21404 SDValue BC01 = DAG.getNode(ISD::BITCAST, dl, VT, BC0.getOperand(1));
21405 SDValue NewBinOp = DAG.getNode(BC0.getOpcode(), dl, VT, BC00, BC01);
21406 return DAG.getVectorShuffle(VT, dl, NewBinOp, N1, &SVOp->getMask()[0]);
21411 // Only handle 128 wide vector from here on.
21412 if (!VT.is128BitVector())
21415 // Combine a vector_shuffle that is equal to build_vector load1, load2, load3,
21416 // load4, <0, 1, 2, 3> into a 128-bit load if the load addresses are
21417 // consecutive, non-overlapping, and in the right order.
21418 SmallVector<SDValue, 16> Elts;
21419 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
21420 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0));
21422 SDValue LD = EltsFromConsecutiveLoads(VT, Elts, dl, DAG, true);
21426 if (isTargetShuffle(N->getOpcode())) {
21428 PerformTargetShuffleCombine(SDValue(N, 0), DAG, DCI, Subtarget);
21429 if (Shuffle.getNode())
21432 // Try recursively combining arbitrary sequences of x86 shuffle
21433 // instructions into higher-order shuffles. We do this after combining
21434 // specific PSHUF instruction sequences into their minimal form so that we
21435 // can evaluate how many specialized shuffle instructions are involved in
21436 // a particular chain.
21437 SmallVector<int, 1> NonceMask; // Just a placeholder.
21438 NonceMask.push_back(0);
21439 if (combineX86ShufflesRecursively(SDValue(N, 0), SDValue(N, 0), NonceMask,
21440 /*Depth*/ 1, /*HasPSHUFB*/ false, DAG,
21442 return SDValue(); // This routine will use CombineTo to replace N.
21448 /// PerformTruncateCombine - Converts truncate operation to
21449 /// a sequence of vector shuffle operations.
21450 /// It is possible when we truncate 256-bit vector to 128-bit vector
21451 static SDValue PerformTruncateCombine(SDNode *N, SelectionDAG &DAG,
21452 TargetLowering::DAGCombinerInfo &DCI,
21453 const X86Subtarget *Subtarget) {
21457 /// XFormVExtractWithShuffleIntoLoad - Check if a vector extract from a target
21458 /// specific shuffle of a load can be folded into a single element load.
21459 /// Similar handling for VECTOR_SHUFFLE is performed by DAGCombiner, but
21460 /// shuffles have been customed lowered so we need to handle those here.
21461 static SDValue XFormVExtractWithShuffleIntoLoad(SDNode *N, SelectionDAG &DAG,
21462 TargetLowering::DAGCombinerInfo &DCI) {
21463 if (DCI.isBeforeLegalizeOps())
21466 SDValue InVec = N->getOperand(0);
21467 SDValue EltNo = N->getOperand(1);
21469 if (!isa<ConstantSDNode>(EltNo))
21472 EVT VT = InVec.getValueType();
21474 if (InVec.getOpcode() == ISD::BITCAST) {
21475 // Don't duplicate a load with other uses.
21476 if (!InVec.hasOneUse())
21478 EVT BCVT = InVec.getOperand(0).getValueType();
21479 if (BCVT.getVectorNumElements() != VT.getVectorNumElements())
21481 InVec = InVec.getOperand(0);
21484 if (!isTargetShuffle(InVec.getOpcode()))
21487 // Don't duplicate a load with other uses.
21488 if (!InVec.hasOneUse())
21491 SmallVector<int, 16> ShuffleMask;
21493 if (!getTargetShuffleMask(InVec.getNode(), VT.getSimpleVT(), ShuffleMask,
21497 // Select the input vector, guarding against out of range extract vector.
21498 unsigned NumElems = VT.getVectorNumElements();
21499 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
21500 int Idx = (Elt > (int)NumElems) ? -1 : ShuffleMask[Elt];
21501 SDValue LdNode = (Idx < (int)NumElems) ? InVec.getOperand(0)
21502 : InVec.getOperand(1);
21504 // If inputs to shuffle are the same for both ops, then allow 2 uses
21505 unsigned AllowedUses = InVec.getOperand(0) == InVec.getOperand(1) ? 2 : 1;
21507 if (LdNode.getOpcode() == ISD::BITCAST) {
21508 // Don't duplicate a load with other uses.
21509 if (!LdNode.getNode()->hasNUsesOfValue(AllowedUses, 0))
21512 AllowedUses = 1; // only allow 1 load use if we have a bitcast
21513 LdNode = LdNode.getOperand(0);
21516 if (!ISD::isNormalLoad(LdNode.getNode()))
21519 LoadSDNode *LN0 = cast<LoadSDNode>(LdNode);
21521 if (!LN0 ||!LN0->hasNUsesOfValue(AllowedUses, 0) || LN0->isVolatile())
21524 EVT EltVT = N->getValueType(0);
21525 // If there's a bitcast before the shuffle, check if the load type and
21526 // alignment is valid.
21527 unsigned Align = LN0->getAlignment();
21528 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
21529 unsigned NewAlign = TLI.getDataLayout()->getABITypeAlignment(
21530 EltVT.getTypeForEVT(*DAG.getContext()));
21532 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, EltVT))
21535 // All checks match so transform back to vector_shuffle so that DAG combiner
21536 // can finish the job
21539 // Create shuffle node taking into account the case that its a unary shuffle
21540 SDValue Shuffle = (UnaryShuffle) ? DAG.getUNDEF(VT) : InVec.getOperand(1);
21541 Shuffle = DAG.getVectorShuffle(InVec.getValueType(), dl,
21542 InVec.getOperand(0), Shuffle,
21544 Shuffle = DAG.getNode(ISD::BITCAST, dl, VT, Shuffle);
21545 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, N->getValueType(0), Shuffle,
21549 /// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index
21550 /// generation and convert it from being a bunch of shuffles and extracts
21551 /// to a simple store and scalar loads to extract the elements.
21552 static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG,
21553 TargetLowering::DAGCombinerInfo &DCI) {
21554 SDValue NewOp = XFormVExtractWithShuffleIntoLoad(N, DAG, DCI);
21555 if (NewOp.getNode())
21558 SDValue InputVector = N->getOperand(0);
21560 // Detect whether we are trying to convert from mmx to i32 and the bitcast
21561 // from mmx to v2i32 has a single usage.
21562 if (InputVector.getNode()->getOpcode() == llvm::ISD::BITCAST &&
21563 InputVector.getNode()->getOperand(0).getValueType() == MVT::x86mmx &&
21564 InputVector.hasOneUse() && N->getValueType(0) == MVT::i32)
21565 return DAG.getNode(X86ISD::MMX_MOVD2W, SDLoc(InputVector),
21566 N->getValueType(0),
21567 InputVector.getNode()->getOperand(0));
21569 // Only operate on vectors of 4 elements, where the alternative shuffling
21570 // gets to be more expensive.
21571 if (InputVector.getValueType() != MVT::v4i32)
21574 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a
21575 // single use which is a sign-extend or zero-extend, and all elements are
21577 SmallVector<SDNode *, 4> Uses;
21578 unsigned ExtractedElements = 0;
21579 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(),
21580 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) {
21581 if (UI.getUse().getResNo() != InputVector.getResNo())
21584 SDNode *Extract = *UI;
21585 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
21588 if (Extract->getValueType(0) != MVT::i32)
21590 if (!Extract->hasOneUse())
21592 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND &&
21593 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND)
21595 if (!isa<ConstantSDNode>(Extract->getOperand(1)))
21598 // Record which element was extracted.
21599 ExtractedElements |=
21600 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue();
21602 Uses.push_back(Extract);
21605 // If not all the elements were used, this may not be worthwhile.
21606 if (ExtractedElements != 15)
21609 // Ok, we've now decided to do the transformation.
21610 SDLoc dl(InputVector);
21612 // Store the value to a temporary stack slot.
21613 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType());
21614 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr,
21615 MachinePointerInfo(), false, false, 0);
21617 // Replace each use (extract) with a load of the appropriate element.
21618 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(),
21619 UE = Uses.end(); UI != UE; ++UI) {
21620 SDNode *Extract = *UI;
21622 // cOMpute the element's address.
21623 SDValue Idx = Extract->getOperand(1);
21625 InputVector.getValueType().getVectorElementType().getSizeInBits()/8;
21626 uint64_t Offset = EltSize * cast<ConstantSDNode>(Idx)->getZExtValue();
21627 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
21628 SDValue OffsetVal = DAG.getConstant(Offset, TLI.getPointerTy());
21630 SDValue ScalarAddr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(),
21631 StackPtr, OffsetVal);
21633 // Load the scalar.
21634 SDValue LoadScalar = DAG.getLoad(Extract->getValueType(0), dl, Ch,
21635 ScalarAddr, MachinePointerInfo(),
21636 false, false, false, 0);
21638 // Replace the exact with the load.
21639 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), LoadScalar);
21642 // The replacement was made in place; don't return anything.
21646 /// \brief Matches a VSELECT onto min/max or return 0 if the node doesn't match.
21647 static std::pair<unsigned, bool>
21648 matchIntegerMINMAX(SDValue Cond, EVT VT, SDValue LHS, SDValue RHS,
21649 SelectionDAG &DAG, const X86Subtarget *Subtarget) {
21650 if (!VT.isVector())
21651 return std::make_pair(0, false);
21653 bool NeedSplit = false;
21654 switch (VT.getSimpleVT().SimpleTy) {
21655 default: return std::make_pair(0, false);
21659 if (!Subtarget->hasAVX2())
21661 if (!Subtarget->hasAVX())
21662 return std::make_pair(0, false);
21667 if (!Subtarget->hasSSE2())
21668 return std::make_pair(0, false);
21671 // SSE2 has only a small subset of the operations.
21672 bool hasUnsigned = Subtarget->hasSSE41() ||
21673 (Subtarget->hasSSE2() && VT == MVT::v16i8);
21674 bool hasSigned = Subtarget->hasSSE41() ||
21675 (Subtarget->hasSSE2() && VT == MVT::v8i16);
21677 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
21680 // Check for x CC y ? x : y.
21681 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
21682 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
21687 Opc = hasUnsigned ? X86ISD::UMIN : 0; break;
21690 Opc = hasUnsigned ? X86ISD::UMAX : 0; break;
21693 Opc = hasSigned ? X86ISD::SMIN : 0; break;
21696 Opc = hasSigned ? X86ISD::SMAX : 0; break;
21698 // Check for x CC y ? y : x -- a min/max with reversed arms.
21699 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
21700 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
21705 Opc = hasUnsigned ? X86ISD::UMAX : 0; break;
21708 Opc = hasUnsigned ? X86ISD::UMIN : 0; break;
21711 Opc = hasSigned ? X86ISD::SMAX : 0; break;
21714 Opc = hasSigned ? X86ISD::SMIN : 0; break;
21718 return std::make_pair(Opc, NeedSplit);
21722 TransformVSELECTtoBlendVECTOR_SHUFFLE(SDNode *N, SelectionDAG &DAG,
21723 const X86Subtarget *Subtarget) {
21725 SDValue Cond = N->getOperand(0);
21726 SDValue LHS = N->getOperand(1);
21727 SDValue RHS = N->getOperand(2);
21729 if (Cond.getOpcode() == ISD::SIGN_EXTEND) {
21730 SDValue CondSrc = Cond->getOperand(0);
21731 if (CondSrc->getOpcode() == ISD::SIGN_EXTEND_INREG)
21732 Cond = CondSrc->getOperand(0);
21735 MVT VT = N->getSimpleValueType(0);
21736 MVT EltVT = VT.getVectorElementType();
21737 unsigned NumElems = VT.getVectorNumElements();
21738 // There is no blend with immediate in AVX-512.
21739 if (VT.is512BitVector())
21742 if (!Subtarget->hasSSE41() || EltVT == MVT::i8)
21744 if (!Subtarget->hasInt256() && VT == MVT::v16i16)
21747 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
21750 // A vselect where all conditions and data are constants can be optimized into
21751 // a single vector load by SelectionDAGLegalize::ExpandBUILD_VECTOR().
21752 if (ISD::isBuildVectorOfConstantSDNodes(LHS.getNode()) &&
21753 ISD::isBuildVectorOfConstantSDNodes(RHS.getNode()))
21756 unsigned MaskValue = 0;
21757 if (!BUILD_VECTORtoBlendMask(cast<BuildVectorSDNode>(Cond), MaskValue))
21760 SmallVector<int, 8> ShuffleMask(NumElems, -1);
21761 for (unsigned i = 0; i < NumElems; ++i) {
21762 // Be sure we emit undef where we can.
21763 if (Cond.getOperand(i)->getOpcode() == ISD::UNDEF)
21764 ShuffleMask[i] = -1;
21766 ShuffleMask[i] = i + NumElems * ((MaskValue >> i) & 1);
21769 return DAG.getVectorShuffle(VT, dl, LHS, RHS, &ShuffleMask[0]);
21772 /// PerformSELECTCombine - Do target-specific dag combines on SELECT and VSELECT
21774 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
21775 TargetLowering::DAGCombinerInfo &DCI,
21776 const X86Subtarget *Subtarget) {
21778 SDValue Cond = N->getOperand(0);
21779 // Get the LHS/RHS of the select.
21780 SDValue LHS = N->getOperand(1);
21781 SDValue RHS = N->getOperand(2);
21782 EVT VT = LHS.getValueType();
21783 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
21785 // If we have SSE[12] support, try to form min/max nodes. SSE min/max
21786 // instructions match the semantics of the common C idiom x<y?x:y but not
21787 // x<=y?x:y, because of how they handle negative zero (which can be
21788 // ignored in unsafe-math mode).
21789 if (Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() &&
21790 VT != MVT::f80 && TLI.isTypeLegal(VT) &&
21791 (Subtarget->hasSSE2() ||
21792 (Subtarget->hasSSE1() && VT.getScalarType() == MVT::f32))) {
21793 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
21795 unsigned Opcode = 0;
21796 // Check for x CC y ? x : y.
21797 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
21798 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
21802 // Converting this to a min would handle NaNs incorrectly, and swapping
21803 // the operands would cause it to handle comparisons between positive
21804 // and negative zero incorrectly.
21805 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
21806 if (!DAG.getTarget().Options.UnsafeFPMath &&
21807 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
21809 std::swap(LHS, RHS);
21811 Opcode = X86ISD::FMIN;
21814 // Converting this to a min would handle comparisons between positive
21815 // and negative zero incorrectly.
21816 if (!DAG.getTarget().Options.UnsafeFPMath &&
21817 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
21819 Opcode = X86ISD::FMIN;
21822 // Converting this to a min would handle both negative zeros and NaNs
21823 // incorrectly, but we can swap the operands to fix both.
21824 std::swap(LHS, RHS);
21828 Opcode = X86ISD::FMIN;
21832 // Converting this to a max would handle comparisons between positive
21833 // and negative zero incorrectly.
21834 if (!DAG.getTarget().Options.UnsafeFPMath &&
21835 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
21837 Opcode = X86ISD::FMAX;
21840 // Converting this to a max would handle NaNs incorrectly, and swapping
21841 // the operands would cause it to handle comparisons between positive
21842 // and negative zero incorrectly.
21843 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
21844 if (!DAG.getTarget().Options.UnsafeFPMath &&
21845 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
21847 std::swap(LHS, RHS);
21849 Opcode = X86ISD::FMAX;
21852 // Converting this to a max would handle both negative zeros and NaNs
21853 // incorrectly, but we can swap the operands to fix both.
21854 std::swap(LHS, RHS);
21858 Opcode = X86ISD::FMAX;
21861 // Check for x CC y ? y : x -- a min/max with reversed arms.
21862 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
21863 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
21867 // Converting this to a min would handle comparisons between positive
21868 // and negative zero incorrectly, and swapping the operands would
21869 // cause it to handle NaNs incorrectly.
21870 if (!DAG.getTarget().Options.UnsafeFPMath &&
21871 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) {
21872 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
21874 std::swap(LHS, RHS);
21876 Opcode = X86ISD::FMIN;
21879 // Converting this to a min would handle NaNs incorrectly.
21880 if (!DAG.getTarget().Options.UnsafeFPMath &&
21881 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
21883 Opcode = X86ISD::FMIN;
21886 // Converting this to a min would handle both negative zeros and NaNs
21887 // incorrectly, but we can swap the operands to fix both.
21888 std::swap(LHS, RHS);
21892 Opcode = X86ISD::FMIN;
21896 // Converting this to a max would handle NaNs incorrectly.
21897 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
21899 Opcode = X86ISD::FMAX;
21902 // Converting this to a max would handle comparisons between positive
21903 // and negative zero incorrectly, and swapping the operands would
21904 // cause it to handle NaNs incorrectly.
21905 if (!DAG.getTarget().Options.UnsafeFPMath &&
21906 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) {
21907 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
21909 std::swap(LHS, RHS);
21911 Opcode = X86ISD::FMAX;
21914 // Converting this to a max would handle both negative zeros and NaNs
21915 // incorrectly, but we can swap the operands to fix both.
21916 std::swap(LHS, RHS);
21920 Opcode = X86ISD::FMAX;
21926 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
21929 EVT CondVT = Cond.getValueType();
21930 if (Subtarget->hasAVX512() && VT.isVector() && CondVT.isVector() &&
21931 CondVT.getVectorElementType() == MVT::i1) {
21932 // v16i8 (select v16i1, v16i8, v16i8) does not have a proper
21933 // lowering on KNL. In this case we convert it to
21934 // v16i8 (select v16i8, v16i8, v16i8) and use AVX instruction.
21935 // The same situation for all 128 and 256-bit vectors of i8 and i16.
21936 // Since SKX these selects have a proper lowering.
21937 EVT OpVT = LHS.getValueType();
21938 if ((OpVT.is128BitVector() || OpVT.is256BitVector()) &&
21939 (OpVT.getVectorElementType() == MVT::i8 ||
21940 OpVT.getVectorElementType() == MVT::i16) &&
21941 !(Subtarget->hasBWI() && Subtarget->hasVLX())) {
21942 Cond = DAG.getNode(ISD::SIGN_EXTEND, DL, OpVT, Cond);
21943 DCI.AddToWorklist(Cond.getNode());
21944 return DAG.getNode(N->getOpcode(), DL, OpVT, Cond, LHS, RHS);
21947 // If this is a select between two integer constants, try to do some
21949 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
21950 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
21951 // Don't do this for crazy integer types.
21952 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
21953 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
21954 // so that TrueC (the true value) is larger than FalseC.
21955 bool NeedsCondInvert = false;
21957 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
21958 // Efficiently invertible.
21959 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
21960 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
21961 isa<ConstantSDNode>(Cond.getOperand(1))))) {
21962 NeedsCondInvert = true;
21963 std::swap(TrueC, FalseC);
21966 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
21967 if (FalseC->getAPIntValue() == 0 &&
21968 TrueC->getAPIntValue().isPowerOf2()) {
21969 if (NeedsCondInvert) // Invert the condition if needed.
21970 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
21971 DAG.getConstant(1, Cond.getValueType()));
21973 // Zero extend the condition if needed.
21974 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
21976 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
21977 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
21978 DAG.getConstant(ShAmt, MVT::i8));
21981 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
21982 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
21983 if (NeedsCondInvert) // Invert the condition if needed.
21984 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
21985 DAG.getConstant(1, Cond.getValueType()));
21987 // Zero extend the condition if needed.
21988 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
21989 FalseC->getValueType(0), Cond);
21990 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
21991 SDValue(FalseC, 0));
21994 // Optimize cases that will turn into an LEA instruction. This requires
21995 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
21996 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
21997 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
21998 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
22000 bool isFastMultiplier = false;
22002 switch ((unsigned char)Diff) {
22004 case 1: // result = add base, cond
22005 case 2: // result = lea base( , cond*2)
22006 case 3: // result = lea base(cond, cond*2)
22007 case 4: // result = lea base( , cond*4)
22008 case 5: // result = lea base(cond, cond*4)
22009 case 8: // result = lea base( , cond*8)
22010 case 9: // result = lea base(cond, cond*8)
22011 isFastMultiplier = true;
22016 if (isFastMultiplier) {
22017 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
22018 if (NeedsCondInvert) // Invert the condition if needed.
22019 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
22020 DAG.getConstant(1, Cond.getValueType()));
22022 // Zero extend the condition if needed.
22023 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
22025 // Scale the condition by the difference.
22027 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
22028 DAG.getConstant(Diff, Cond.getValueType()));
22030 // Add the base if non-zero.
22031 if (FalseC->getAPIntValue() != 0)
22032 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
22033 SDValue(FalseC, 0));
22040 // Canonicalize max and min:
22041 // (x > y) ? x : y -> (x >= y) ? x : y
22042 // (x < y) ? x : y -> (x <= y) ? x : y
22043 // This allows use of COND_S / COND_NS (see TranslateX86CC) which eliminates
22044 // the need for an extra compare
22045 // against zero. e.g.
22046 // (x - y) > 0 : (x - y) ? 0 -> (x - y) >= 0 : (x - y) ? 0
22048 // testl %edi, %edi
22050 // cmovgl %edi, %eax
22054 // cmovsl %eax, %edi
22055 if (N->getOpcode() == ISD::SELECT && Cond.getOpcode() == ISD::SETCC &&
22056 DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
22057 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
22058 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
22063 ISD::CondCode NewCC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGE;
22064 Cond = DAG.getSetCC(SDLoc(Cond), Cond.getValueType(),
22065 Cond.getOperand(0), Cond.getOperand(1), NewCC);
22066 return DAG.getNode(ISD::SELECT, DL, VT, Cond, LHS, RHS);
22071 // Early exit check
22072 if (!TLI.isTypeLegal(VT))
22075 // Match VSELECTs into subs with unsigned saturation.
22076 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC &&
22077 // psubus is available in SSE2 and AVX2 for i8 and i16 vectors.
22078 ((Subtarget->hasSSE2() && (VT == MVT::v16i8 || VT == MVT::v8i16)) ||
22079 (Subtarget->hasAVX2() && (VT == MVT::v32i8 || VT == MVT::v16i16)))) {
22080 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
22082 // Check if one of the arms of the VSELECT is a zero vector. If it's on the
22083 // left side invert the predicate to simplify logic below.
22085 if (ISD::isBuildVectorAllZeros(LHS.getNode())) {
22087 CC = ISD::getSetCCInverse(CC, true);
22088 } else if (ISD::isBuildVectorAllZeros(RHS.getNode())) {
22092 if (Other.getNode() && Other->getNumOperands() == 2 &&
22093 DAG.isEqualTo(Other->getOperand(0), Cond.getOperand(0))) {
22094 SDValue OpLHS = Other->getOperand(0), OpRHS = Other->getOperand(1);
22095 SDValue CondRHS = Cond->getOperand(1);
22097 // Look for a general sub with unsigned saturation first.
22098 // x >= y ? x-y : 0 --> subus x, y
22099 // x > y ? x-y : 0 --> subus x, y
22100 if ((CC == ISD::SETUGE || CC == ISD::SETUGT) &&
22101 Other->getOpcode() == ISD::SUB && DAG.isEqualTo(OpRHS, CondRHS))
22102 return DAG.getNode(X86ISD::SUBUS, DL, VT, OpLHS, OpRHS);
22104 if (auto *OpRHSBV = dyn_cast<BuildVectorSDNode>(OpRHS))
22105 if (auto *OpRHSConst = OpRHSBV->getConstantSplatNode()) {
22106 if (auto *CondRHSBV = dyn_cast<BuildVectorSDNode>(CondRHS))
22107 if (auto *CondRHSConst = CondRHSBV->getConstantSplatNode())
22108 // If the RHS is a constant we have to reverse the const
22109 // canonicalization.
22110 // x > C-1 ? x+-C : 0 --> subus x, C
22111 if (CC == ISD::SETUGT && Other->getOpcode() == ISD::ADD &&
22112 CondRHSConst->getAPIntValue() ==
22113 (-OpRHSConst->getAPIntValue() - 1))
22114 return DAG.getNode(
22115 X86ISD::SUBUS, DL, VT, OpLHS,
22116 DAG.getConstant(-OpRHSConst->getAPIntValue(), VT));
22118 // Another special case: If C was a sign bit, the sub has been
22119 // canonicalized into a xor.
22120 // FIXME: Would it be better to use computeKnownBits to determine
22121 // whether it's safe to decanonicalize the xor?
22122 // x s< 0 ? x^C : 0 --> subus x, C
22123 if (CC == ISD::SETLT && Other->getOpcode() == ISD::XOR &&
22124 ISD::isBuildVectorAllZeros(CondRHS.getNode()) &&
22125 OpRHSConst->getAPIntValue().isSignBit())
22126 // Note that we have to rebuild the RHS constant here to ensure we
22127 // don't rely on particular values of undef lanes.
22128 return DAG.getNode(
22129 X86ISD::SUBUS, DL, VT, OpLHS,
22130 DAG.getConstant(OpRHSConst->getAPIntValue(), VT));
22135 // Try to match a min/max vector operation.
22136 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC) {
22137 std::pair<unsigned, bool> ret = matchIntegerMINMAX(Cond, VT, LHS, RHS, DAG, Subtarget);
22138 unsigned Opc = ret.first;
22139 bool NeedSplit = ret.second;
22141 if (Opc && NeedSplit) {
22142 unsigned NumElems = VT.getVectorNumElements();
22143 // Extract the LHS vectors
22144 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, DL);
22145 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, DL);
22147 // Extract the RHS vectors
22148 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, DL);
22149 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, DL);
22151 // Create min/max for each subvector
22152 LHS = DAG.getNode(Opc, DL, LHS1.getValueType(), LHS1, RHS1);
22153 RHS = DAG.getNode(Opc, DL, LHS2.getValueType(), LHS2, RHS2);
22155 // Merge the result
22156 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LHS, RHS);
22158 return DAG.getNode(Opc, DL, VT, LHS, RHS);
22161 // Simplify vector selection if the selector will be produced by CMPP*/PCMP*.
22162 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC &&
22163 // Check if SETCC has already been promoted
22164 TLI.getSetCCResultType(*DAG.getContext(), VT) == CondVT &&
22165 // Check that condition value type matches vselect operand type
22168 assert(Cond.getValueType().isVector() &&
22169 "vector select expects a vector selector!");
22171 bool TValIsAllOnes = ISD::isBuildVectorAllOnes(LHS.getNode());
22172 bool FValIsAllZeros = ISD::isBuildVectorAllZeros(RHS.getNode());
22174 if (!TValIsAllOnes && !FValIsAllZeros) {
22175 // Try invert the condition if true value is not all 1s and false value
22177 bool TValIsAllZeros = ISD::isBuildVectorAllZeros(LHS.getNode());
22178 bool FValIsAllOnes = ISD::isBuildVectorAllOnes(RHS.getNode());
22180 if (TValIsAllZeros || FValIsAllOnes) {
22181 SDValue CC = Cond.getOperand(2);
22182 ISD::CondCode NewCC =
22183 ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
22184 Cond.getOperand(0).getValueType().isInteger());
22185 Cond = DAG.getSetCC(DL, CondVT, Cond.getOperand(0), Cond.getOperand(1), NewCC);
22186 std::swap(LHS, RHS);
22187 TValIsAllOnes = FValIsAllOnes;
22188 FValIsAllZeros = TValIsAllZeros;
22192 if (TValIsAllOnes || FValIsAllZeros) {
22195 if (TValIsAllOnes && FValIsAllZeros)
22197 else if (TValIsAllOnes)
22198 Ret = DAG.getNode(ISD::OR, DL, CondVT, Cond,
22199 DAG.getNode(ISD::BITCAST, DL, CondVT, RHS));
22200 else if (FValIsAllZeros)
22201 Ret = DAG.getNode(ISD::AND, DL, CondVT, Cond,
22202 DAG.getNode(ISD::BITCAST, DL, CondVT, LHS));
22204 return DAG.getNode(ISD::BITCAST, DL, VT, Ret);
22208 // Try to fold this VSELECT into a MOVSS/MOVSD
22209 if (N->getOpcode() == ISD::VSELECT &&
22210 Cond.getOpcode() == ISD::BUILD_VECTOR && !DCI.isBeforeLegalize()) {
22211 if (VT == MVT::v4i32 || VT == MVT::v4f32 ||
22212 (Subtarget->hasSSE2() && (VT == MVT::v2i64 || VT == MVT::v2f64))) {
22213 bool CanFold = false;
22214 unsigned NumElems = Cond.getNumOperands();
22218 if (isZero(Cond.getOperand(0))) {
22221 // fold (vselect <0,-1,-1,-1>, A, B) -> (movss A, B)
22222 // fold (vselect <0,-1> -> (movsd A, B)
22223 for (unsigned i = 1, e = NumElems; i != e && CanFold; ++i)
22224 CanFold = isAllOnes(Cond.getOperand(i));
22225 } else if (isAllOnes(Cond.getOperand(0))) {
22229 // fold (vselect <-1,0,0,0>, A, B) -> (movss B, A)
22230 // fold (vselect <-1,0> -> (movsd B, A)
22231 for (unsigned i = 1, e = NumElems; i != e && CanFold; ++i)
22232 CanFold = isZero(Cond.getOperand(i));
22236 if (VT == MVT::v4i32 || VT == MVT::v4f32)
22237 return getTargetShuffleNode(X86ISD::MOVSS, DL, VT, A, B, DAG);
22238 return getTargetShuffleNode(X86ISD::MOVSD, DL, VT, A, B, DAG);
22241 if (Subtarget->hasSSE2() && (VT == MVT::v4i32 || VT == MVT::v4f32)) {
22242 // fold (v4i32: vselect <0,0,-1,-1>, A, B) ->
22243 // (v4i32 (bitcast (movsd (v2i64 (bitcast A)),
22244 // (v2i64 (bitcast B)))))
22246 // fold (v4f32: vselect <0,0,-1,-1>, A, B) ->
22247 // (v4f32 (bitcast (movsd (v2f64 (bitcast A)),
22248 // (v2f64 (bitcast B)))))
22250 // fold (v4i32: vselect <-1,-1,0,0>, A, B) ->
22251 // (v4i32 (bitcast (movsd (v2i64 (bitcast B)),
22252 // (v2i64 (bitcast A)))))
22254 // fold (v4f32: vselect <-1,-1,0,0>, A, B) ->
22255 // (v4f32 (bitcast (movsd (v2f64 (bitcast B)),
22256 // (v2f64 (bitcast A)))))
22258 CanFold = (isZero(Cond.getOperand(0)) &&
22259 isZero(Cond.getOperand(1)) &&
22260 isAllOnes(Cond.getOperand(2)) &&
22261 isAllOnes(Cond.getOperand(3)));
22263 if (!CanFold && isAllOnes(Cond.getOperand(0)) &&
22264 isAllOnes(Cond.getOperand(1)) &&
22265 isZero(Cond.getOperand(2)) &&
22266 isZero(Cond.getOperand(3))) {
22268 std::swap(LHS, RHS);
22272 EVT NVT = (VT == MVT::v4i32) ? MVT::v2i64 : MVT::v2f64;
22273 SDValue NewA = DAG.getNode(ISD::BITCAST, DL, NVT, LHS);
22274 SDValue NewB = DAG.getNode(ISD::BITCAST, DL, NVT, RHS);
22275 SDValue Select = getTargetShuffleNode(X86ISD::MOVSD, DL, NVT, NewA,
22277 return DAG.getNode(ISD::BITCAST, DL, VT, Select);
22283 // If we know that this node is legal then we know that it is going to be
22284 // matched by one of the SSE/AVX BLEND instructions. These instructions only
22285 // depend on the highest bit in each word. Try to use SimplifyDemandedBits
22286 // to simplify previous instructions.
22287 if (N->getOpcode() == ISD::VSELECT && DCI.isBeforeLegalizeOps() &&
22288 !DCI.isBeforeLegalize() &&
22289 // We explicitly check against v8i16 and v16i16 because, although
22290 // they're marked as Custom, they might only be legal when Cond is a
22291 // build_vector of constants. This will be taken care in a later
22293 (TLI.isOperationLegalOrCustom(ISD::VSELECT, VT) && VT != MVT::v16i16 &&
22294 VT != MVT::v8i16)) {
22295 unsigned BitWidth = Cond.getValueType().getScalarType().getSizeInBits();
22297 // Don't optimize vector selects that map to mask-registers.
22301 // Check all uses of that condition operand to check whether it will be
22302 // consumed by non-BLEND instructions, which may depend on all bits are set
22304 for (SDNode::use_iterator I = Cond->use_begin(),
22305 E = Cond->use_end(); I != E; ++I)
22306 if (I->getOpcode() != ISD::VSELECT)
22307 // TODO: Add other opcodes eventually lowered into BLEND.
22310 assert(BitWidth >= 8 && BitWidth <= 64 && "Invalid mask size");
22311 APInt DemandedMask = APInt::getHighBitsSet(BitWidth, 1);
22313 APInt KnownZero, KnownOne;
22314 TargetLowering::TargetLoweringOpt TLO(DAG, DCI.isBeforeLegalize(),
22315 DCI.isBeforeLegalizeOps());
22316 if (TLO.ShrinkDemandedConstant(Cond, DemandedMask) ||
22317 TLI.SimplifyDemandedBits(Cond, DemandedMask, KnownZero, KnownOne, TLO))
22318 DCI.CommitTargetLoweringOpt(TLO);
22321 // We should generate an X86ISD::BLENDI from a vselect if its argument
22322 // is a sign_extend_inreg of an any_extend of a BUILD_VECTOR of
22323 // constants. This specific pattern gets generated when we split a
22324 // selector for a 512 bit vector in a machine without AVX512 (but with
22325 // 256-bit vectors), during legalization:
22327 // (vselect (sign_extend (any_extend (BUILD_VECTOR)) i1) LHS RHS)
22329 // Iff we find this pattern and the build_vectors are built from
22330 // constants, we translate the vselect into a shuffle_vector that we
22331 // know will be matched by LowerVECTOR_SHUFFLEtoBlend.
22332 if (N->getOpcode() == ISD::VSELECT && !DCI.isBeforeLegalize()) {
22333 SDValue Shuffle = TransformVSELECTtoBlendVECTOR_SHUFFLE(N, DAG, Subtarget);
22334 if (Shuffle.getNode())
22341 // Check whether a boolean test is testing a boolean value generated by
22342 // X86ISD::SETCC. If so, return the operand of that SETCC and proper condition
22345 // Simplify the following patterns:
22346 // (Op (CMP (SETCC Cond EFLAGS) 1) EQ) or
22347 // (Op (CMP (SETCC Cond EFLAGS) 0) NEQ)
22348 // to (Op EFLAGS Cond)
22350 // (Op (CMP (SETCC Cond EFLAGS) 0) EQ) or
22351 // (Op (CMP (SETCC Cond EFLAGS) 1) NEQ)
22352 // to (Op EFLAGS !Cond)
22354 // where Op could be BRCOND or CMOV.
22356 static SDValue checkBoolTestSetCCCombine(SDValue Cmp, X86::CondCode &CC) {
22357 // Quit if not CMP and SUB with its value result used.
22358 if (Cmp.getOpcode() != X86ISD::CMP &&
22359 (Cmp.getOpcode() != X86ISD::SUB || Cmp.getNode()->hasAnyUseOfValue(0)))
22362 // Quit if not used as a boolean value.
22363 if (CC != X86::COND_E && CC != X86::COND_NE)
22366 // Check CMP operands. One of them should be 0 or 1 and the other should be
22367 // an SetCC or extended from it.
22368 SDValue Op1 = Cmp.getOperand(0);
22369 SDValue Op2 = Cmp.getOperand(1);
22372 const ConstantSDNode* C = nullptr;
22373 bool needOppositeCond = (CC == X86::COND_E);
22374 bool checkAgainstTrue = false; // Is it a comparison against 1?
22376 if ((C = dyn_cast<ConstantSDNode>(Op1)))
22378 else if ((C = dyn_cast<ConstantSDNode>(Op2)))
22380 else // Quit if all operands are not constants.
22383 if (C->getZExtValue() == 1) {
22384 needOppositeCond = !needOppositeCond;
22385 checkAgainstTrue = true;
22386 } else if (C->getZExtValue() != 0)
22387 // Quit if the constant is neither 0 or 1.
22390 bool truncatedToBoolWithAnd = false;
22391 // Skip (zext $x), (trunc $x), or (and $x, 1) node.
22392 while (SetCC.getOpcode() == ISD::ZERO_EXTEND ||
22393 SetCC.getOpcode() == ISD::TRUNCATE ||
22394 SetCC.getOpcode() == ISD::AND) {
22395 if (SetCC.getOpcode() == ISD::AND) {
22397 ConstantSDNode *CS;
22398 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(0))) &&
22399 CS->getZExtValue() == 1)
22401 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(1))) &&
22402 CS->getZExtValue() == 1)
22406 SetCC = SetCC.getOperand(OpIdx);
22407 truncatedToBoolWithAnd = true;
22409 SetCC = SetCC.getOperand(0);
22412 switch (SetCC.getOpcode()) {
22413 case X86ISD::SETCC_CARRY:
22414 // Since SETCC_CARRY gives output based on R = CF ? ~0 : 0, it's unsafe to
22415 // simplify it if the result of SETCC_CARRY is not canonicalized to 0 or 1,
22416 // i.e. it's a comparison against true but the result of SETCC_CARRY is not
22417 // truncated to i1 using 'and'.
22418 if (checkAgainstTrue && !truncatedToBoolWithAnd)
22420 assert(X86::CondCode(SetCC.getConstantOperandVal(0)) == X86::COND_B &&
22421 "Invalid use of SETCC_CARRY!");
22423 case X86ISD::SETCC:
22424 // Set the condition code or opposite one if necessary.
22425 CC = X86::CondCode(SetCC.getConstantOperandVal(0));
22426 if (needOppositeCond)
22427 CC = X86::GetOppositeBranchCondition(CC);
22428 return SetCC.getOperand(1);
22429 case X86ISD::CMOV: {
22430 // Check whether false/true value has canonical one, i.e. 0 or 1.
22431 ConstantSDNode *FVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(0));
22432 ConstantSDNode *TVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(1));
22433 // Quit if true value is not a constant.
22436 // Quit if false value is not a constant.
22438 SDValue Op = SetCC.getOperand(0);
22439 // Skip 'zext' or 'trunc' node.
22440 if (Op.getOpcode() == ISD::ZERO_EXTEND ||
22441 Op.getOpcode() == ISD::TRUNCATE)
22442 Op = Op.getOperand(0);
22443 // A special case for rdrand/rdseed, where 0 is set if false cond is
22445 if ((Op.getOpcode() != X86ISD::RDRAND &&
22446 Op.getOpcode() != X86ISD::RDSEED) || Op.getResNo() != 0)
22449 // Quit if false value is not the constant 0 or 1.
22450 bool FValIsFalse = true;
22451 if (FVal && FVal->getZExtValue() != 0) {
22452 if (FVal->getZExtValue() != 1)
22454 // If FVal is 1, opposite cond is needed.
22455 needOppositeCond = !needOppositeCond;
22456 FValIsFalse = false;
22458 // Quit if TVal is not the constant opposite of FVal.
22459 if (FValIsFalse && TVal->getZExtValue() != 1)
22461 if (!FValIsFalse && TVal->getZExtValue() != 0)
22463 CC = X86::CondCode(SetCC.getConstantOperandVal(2));
22464 if (needOppositeCond)
22465 CC = X86::GetOppositeBranchCondition(CC);
22466 return SetCC.getOperand(3);
22473 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
22474 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
22475 TargetLowering::DAGCombinerInfo &DCI,
22476 const X86Subtarget *Subtarget) {
22479 // If the flag operand isn't dead, don't touch this CMOV.
22480 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
22483 SDValue FalseOp = N->getOperand(0);
22484 SDValue TrueOp = N->getOperand(1);
22485 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
22486 SDValue Cond = N->getOperand(3);
22488 if (CC == X86::COND_E || CC == X86::COND_NE) {
22489 switch (Cond.getOpcode()) {
22493 // If operand of BSR / BSF are proven never zero, then ZF cannot be set.
22494 if (DAG.isKnownNeverZero(Cond.getOperand(0)))
22495 return (CC == X86::COND_E) ? FalseOp : TrueOp;
22501 Flags = checkBoolTestSetCCCombine(Cond, CC);
22502 if (Flags.getNode() &&
22503 // Extra check as FCMOV only supports a subset of X86 cond.
22504 (FalseOp.getValueType() != MVT::f80 || hasFPCMov(CC))) {
22505 SDValue Ops[] = { FalseOp, TrueOp,
22506 DAG.getConstant(CC, MVT::i8), Flags };
22507 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), Ops);
22510 // If this is a select between two integer constants, try to do some
22511 // optimizations. Note that the operands are ordered the opposite of SELECT
22513 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(TrueOp)) {
22514 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(FalseOp)) {
22515 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
22516 // larger than FalseC (the false value).
22517 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
22518 CC = X86::GetOppositeBranchCondition(CC);
22519 std::swap(TrueC, FalseC);
22520 std::swap(TrueOp, FalseOp);
22523 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
22524 // This is efficient for any integer data type (including i8/i16) and
22526 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
22527 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
22528 DAG.getConstant(CC, MVT::i8), Cond);
22530 // Zero extend the condition if needed.
22531 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
22533 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
22534 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
22535 DAG.getConstant(ShAmt, MVT::i8));
22536 if (N->getNumValues() == 2) // Dead flag value?
22537 return DCI.CombineTo(N, Cond, SDValue());
22541 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
22542 // for any integer data type, including i8/i16.
22543 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
22544 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
22545 DAG.getConstant(CC, MVT::i8), Cond);
22547 // Zero extend the condition if needed.
22548 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
22549 FalseC->getValueType(0), Cond);
22550 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
22551 SDValue(FalseC, 0));
22553 if (N->getNumValues() == 2) // Dead flag value?
22554 return DCI.CombineTo(N, Cond, SDValue());
22558 // Optimize cases that will turn into an LEA instruction. This requires
22559 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
22560 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
22561 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
22562 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
22564 bool isFastMultiplier = false;
22566 switch ((unsigned char)Diff) {
22568 case 1: // result = add base, cond
22569 case 2: // result = lea base( , cond*2)
22570 case 3: // result = lea base(cond, cond*2)
22571 case 4: // result = lea base( , cond*4)
22572 case 5: // result = lea base(cond, cond*4)
22573 case 8: // result = lea base( , cond*8)
22574 case 9: // result = lea base(cond, cond*8)
22575 isFastMultiplier = true;
22580 if (isFastMultiplier) {
22581 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
22582 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
22583 DAG.getConstant(CC, MVT::i8), Cond);
22584 // Zero extend the condition if needed.
22585 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
22587 // Scale the condition by the difference.
22589 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
22590 DAG.getConstant(Diff, Cond.getValueType()));
22592 // Add the base if non-zero.
22593 if (FalseC->getAPIntValue() != 0)
22594 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
22595 SDValue(FalseC, 0));
22596 if (N->getNumValues() == 2) // Dead flag value?
22597 return DCI.CombineTo(N, Cond, SDValue());
22604 // Handle these cases:
22605 // (select (x != c), e, c) -> select (x != c), e, x),
22606 // (select (x == c), c, e) -> select (x == c), x, e)
22607 // where the c is an integer constant, and the "select" is the combination
22608 // of CMOV and CMP.
22610 // The rationale for this change is that the conditional-move from a constant
22611 // needs two instructions, however, conditional-move from a register needs
22612 // only one instruction.
22614 // CAVEAT: By replacing a constant with a symbolic value, it may obscure
22615 // some instruction-combining opportunities. This opt needs to be
22616 // postponed as late as possible.
22618 if (!DCI.isBeforeLegalize() && !DCI.isBeforeLegalizeOps()) {
22619 // the DCI.xxxx conditions are provided to postpone the optimization as
22620 // late as possible.
22622 ConstantSDNode *CmpAgainst = nullptr;
22623 if ((Cond.getOpcode() == X86ISD::CMP || Cond.getOpcode() == X86ISD::SUB) &&
22624 (CmpAgainst = dyn_cast<ConstantSDNode>(Cond.getOperand(1))) &&
22625 !isa<ConstantSDNode>(Cond.getOperand(0))) {
22627 if (CC == X86::COND_NE &&
22628 CmpAgainst == dyn_cast<ConstantSDNode>(FalseOp)) {
22629 CC = X86::GetOppositeBranchCondition(CC);
22630 std::swap(TrueOp, FalseOp);
22633 if (CC == X86::COND_E &&
22634 CmpAgainst == dyn_cast<ConstantSDNode>(TrueOp)) {
22635 SDValue Ops[] = { FalseOp, Cond.getOperand(0),
22636 DAG.getConstant(CC, MVT::i8), Cond };
22637 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList (), Ops);
22645 static SDValue PerformINTRINSIC_WO_CHAINCombine(SDNode *N, SelectionDAG &DAG,
22646 const X86Subtarget *Subtarget) {
22647 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
22649 default: return SDValue();
22650 // SSE/AVX/AVX2 blend intrinsics.
22651 case Intrinsic::x86_avx2_pblendvb:
22652 case Intrinsic::x86_avx2_pblendw:
22653 case Intrinsic::x86_avx2_pblendd_128:
22654 case Intrinsic::x86_avx2_pblendd_256:
22655 // Don't try to simplify this intrinsic if we don't have AVX2.
22656 if (!Subtarget->hasAVX2())
22659 case Intrinsic::x86_avx_blend_pd_256:
22660 case Intrinsic::x86_avx_blend_ps_256:
22661 case Intrinsic::x86_avx_blendv_pd_256:
22662 case Intrinsic::x86_avx_blendv_ps_256:
22663 // Don't try to simplify this intrinsic if we don't have AVX.
22664 if (!Subtarget->hasAVX())
22667 case Intrinsic::x86_sse41_pblendw:
22668 case Intrinsic::x86_sse41_blendpd:
22669 case Intrinsic::x86_sse41_blendps:
22670 case Intrinsic::x86_sse41_blendvps:
22671 case Intrinsic::x86_sse41_blendvpd:
22672 case Intrinsic::x86_sse41_pblendvb: {
22673 SDValue Op0 = N->getOperand(1);
22674 SDValue Op1 = N->getOperand(2);
22675 SDValue Mask = N->getOperand(3);
22677 // Don't try to simplify this intrinsic if we don't have SSE4.1.
22678 if (!Subtarget->hasSSE41())
22681 // fold (blend A, A, Mask) -> A
22684 // fold (blend A, B, allZeros) -> A
22685 if (ISD::isBuildVectorAllZeros(Mask.getNode()))
22687 // fold (blend A, B, allOnes) -> B
22688 if (ISD::isBuildVectorAllOnes(Mask.getNode()))
22691 // Simplify the case where the mask is a constant i32 value.
22692 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Mask)) {
22693 if (C->isNullValue())
22695 if (C->isAllOnesValue())
22702 // Packed SSE2/AVX2 arithmetic shift immediate intrinsics.
22703 case Intrinsic::x86_sse2_psrai_w:
22704 case Intrinsic::x86_sse2_psrai_d:
22705 case Intrinsic::x86_avx2_psrai_w:
22706 case Intrinsic::x86_avx2_psrai_d:
22707 case Intrinsic::x86_sse2_psra_w:
22708 case Intrinsic::x86_sse2_psra_d:
22709 case Intrinsic::x86_avx2_psra_w:
22710 case Intrinsic::x86_avx2_psra_d: {
22711 SDValue Op0 = N->getOperand(1);
22712 SDValue Op1 = N->getOperand(2);
22713 EVT VT = Op0.getValueType();
22714 assert(VT.isVector() && "Expected a vector type!");
22716 if (isa<BuildVectorSDNode>(Op1))
22717 Op1 = Op1.getOperand(0);
22719 if (!isa<ConstantSDNode>(Op1))
22722 EVT SVT = VT.getVectorElementType();
22723 unsigned SVTBits = SVT.getSizeInBits();
22725 ConstantSDNode *CND = cast<ConstantSDNode>(Op1);
22726 const APInt &C = APInt(SVTBits, CND->getAPIntValue().getZExtValue());
22727 uint64_t ShAmt = C.getZExtValue();
22729 // Don't try to convert this shift into a ISD::SRA if the shift
22730 // count is bigger than or equal to the element size.
22731 if (ShAmt >= SVTBits)
22734 // Trivial case: if the shift count is zero, then fold this
22735 // into the first operand.
22739 // Replace this packed shift intrinsic with a target independent
22741 SDValue Splat = DAG.getConstant(C, VT);
22742 return DAG.getNode(ISD::SRA, SDLoc(N), VT, Op0, Splat);
22747 /// PerformMulCombine - Optimize a single multiply with constant into two
22748 /// in order to implement it with two cheaper instructions, e.g.
22749 /// LEA + SHL, LEA + LEA.
22750 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
22751 TargetLowering::DAGCombinerInfo &DCI) {
22752 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
22755 EVT VT = N->getValueType(0);
22756 if (VT != MVT::i64)
22759 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
22762 uint64_t MulAmt = C->getZExtValue();
22763 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
22766 uint64_t MulAmt1 = 0;
22767 uint64_t MulAmt2 = 0;
22768 if ((MulAmt % 9) == 0) {
22770 MulAmt2 = MulAmt / 9;
22771 } else if ((MulAmt % 5) == 0) {
22773 MulAmt2 = MulAmt / 5;
22774 } else if ((MulAmt % 3) == 0) {
22776 MulAmt2 = MulAmt / 3;
22779 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
22782 if (isPowerOf2_64(MulAmt2) &&
22783 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
22784 // If second multiplifer is pow2, issue it first. We want the multiply by
22785 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
22787 std::swap(MulAmt1, MulAmt2);
22790 if (isPowerOf2_64(MulAmt1))
22791 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
22792 DAG.getConstant(Log2_64(MulAmt1), MVT::i8));
22794 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
22795 DAG.getConstant(MulAmt1, VT));
22797 if (isPowerOf2_64(MulAmt2))
22798 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
22799 DAG.getConstant(Log2_64(MulAmt2), MVT::i8));
22801 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
22802 DAG.getConstant(MulAmt2, VT));
22804 // Do not add new nodes to DAG combiner worklist.
22805 DCI.CombineTo(N, NewMul, false);
22810 static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) {
22811 SDValue N0 = N->getOperand(0);
22812 SDValue N1 = N->getOperand(1);
22813 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
22814 EVT VT = N0.getValueType();
22816 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2))
22817 // since the result of setcc_c is all zero's or all ones.
22818 if (VT.isInteger() && !VT.isVector() &&
22819 N1C && N0.getOpcode() == ISD::AND &&
22820 N0.getOperand(1).getOpcode() == ISD::Constant) {
22821 SDValue N00 = N0.getOperand(0);
22822 if (N00.getOpcode() == X86ISD::SETCC_CARRY ||
22823 ((N00.getOpcode() == ISD::ANY_EXTEND ||
22824 N00.getOpcode() == ISD::ZERO_EXTEND) &&
22825 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY)) {
22826 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
22827 APInt ShAmt = N1C->getAPIntValue();
22828 Mask = Mask.shl(ShAmt);
22830 return DAG.getNode(ISD::AND, SDLoc(N), VT,
22831 N00, DAG.getConstant(Mask, VT));
22835 // Hardware support for vector shifts is sparse which makes us scalarize the
22836 // vector operations in many cases. Also, on sandybridge ADD is faster than
22838 // (shl V, 1) -> add V,V
22839 if (auto *N1BV = dyn_cast<BuildVectorSDNode>(N1))
22840 if (auto *N1SplatC = N1BV->getConstantSplatNode()) {
22841 assert(N0.getValueType().isVector() && "Invalid vector shift type");
22842 // We shift all of the values by one. In many cases we do not have
22843 // hardware support for this operation. This is better expressed as an ADD
22845 if (N1SplatC->getZExtValue() == 1)
22846 return DAG.getNode(ISD::ADD, SDLoc(N), VT, N0, N0);
22852 /// \brief Returns a vector of 0s if the node in input is a vector logical
22853 /// shift by a constant amount which is known to be bigger than or equal
22854 /// to the vector element size in bits.
22855 static SDValue performShiftToAllZeros(SDNode *N, SelectionDAG &DAG,
22856 const X86Subtarget *Subtarget) {
22857 EVT VT = N->getValueType(0);
22859 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16 &&
22860 (!Subtarget->hasInt256() ||
22861 (VT != MVT::v4i64 && VT != MVT::v8i32 && VT != MVT::v16i16)))
22864 SDValue Amt = N->getOperand(1);
22866 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Amt))
22867 if (auto *AmtSplat = AmtBV->getConstantSplatNode()) {
22868 APInt ShiftAmt = AmtSplat->getAPIntValue();
22869 unsigned MaxAmount = VT.getVectorElementType().getSizeInBits();
22871 // SSE2/AVX2 logical shifts always return a vector of 0s
22872 // if the shift amount is bigger than or equal to
22873 // the element size. The constant shift amount will be
22874 // encoded as a 8-bit immediate.
22875 if (ShiftAmt.trunc(8).uge(MaxAmount))
22876 return getZeroVector(VT, Subtarget, DAG, DL);
22882 /// PerformShiftCombine - Combine shifts.
22883 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
22884 TargetLowering::DAGCombinerInfo &DCI,
22885 const X86Subtarget *Subtarget) {
22886 if (N->getOpcode() == ISD::SHL) {
22887 SDValue V = PerformSHLCombine(N, DAG);
22888 if (V.getNode()) return V;
22891 if (N->getOpcode() != ISD::SRA) {
22892 // Try to fold this logical shift into a zero vector.
22893 SDValue V = performShiftToAllZeros(N, DAG, Subtarget);
22894 if (V.getNode()) return V;
22900 // CMPEQCombine - Recognize the distinctive (AND (setcc ...) (setcc ..))
22901 // where both setccs reference the same FP CMP, and rewrite for CMPEQSS
22902 // and friends. Likewise for OR -> CMPNEQSS.
22903 static SDValue CMPEQCombine(SDNode *N, SelectionDAG &DAG,
22904 TargetLowering::DAGCombinerInfo &DCI,
22905 const X86Subtarget *Subtarget) {
22908 // SSE1 supports CMP{eq|ne}SS, and SSE2 added CMP{eq|ne}SD, but
22909 // we're requiring SSE2 for both.
22910 if (Subtarget->hasSSE2() && isAndOrOfSetCCs(SDValue(N, 0U), opcode)) {
22911 SDValue N0 = N->getOperand(0);
22912 SDValue N1 = N->getOperand(1);
22913 SDValue CMP0 = N0->getOperand(1);
22914 SDValue CMP1 = N1->getOperand(1);
22917 // The SETCCs should both refer to the same CMP.
22918 if (CMP0.getOpcode() != X86ISD::CMP || CMP0 != CMP1)
22921 SDValue CMP00 = CMP0->getOperand(0);
22922 SDValue CMP01 = CMP0->getOperand(1);
22923 EVT VT = CMP00.getValueType();
22925 if (VT == MVT::f32 || VT == MVT::f64) {
22926 bool ExpectingFlags = false;
22927 // Check for any users that want flags:
22928 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
22929 !ExpectingFlags && UI != UE; ++UI)
22930 switch (UI->getOpcode()) {
22935 ExpectingFlags = true;
22937 case ISD::CopyToReg:
22938 case ISD::SIGN_EXTEND:
22939 case ISD::ZERO_EXTEND:
22940 case ISD::ANY_EXTEND:
22944 if (!ExpectingFlags) {
22945 enum X86::CondCode cc0 = (enum X86::CondCode)N0.getConstantOperandVal(0);
22946 enum X86::CondCode cc1 = (enum X86::CondCode)N1.getConstantOperandVal(0);
22948 if (cc1 == X86::COND_E || cc1 == X86::COND_NE) {
22949 X86::CondCode tmp = cc0;
22954 if ((cc0 == X86::COND_E && cc1 == X86::COND_NP) ||
22955 (cc0 == X86::COND_NE && cc1 == X86::COND_P)) {
22956 // FIXME: need symbolic constants for these magic numbers.
22957 // See X86ATTInstPrinter.cpp:printSSECC().
22958 unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4;
22959 if (Subtarget->hasAVX512()) {
22960 SDValue FSetCC = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CMP00,
22961 CMP01, DAG.getConstant(x86cc, MVT::i8));
22962 if (N->getValueType(0) != MVT::i1)
22963 return DAG.getNode(ISD::ZERO_EXTEND, DL, N->getValueType(0),
22967 SDValue OnesOrZeroesF = DAG.getNode(X86ISD::FSETCC, DL,
22968 CMP00.getValueType(), CMP00, CMP01,
22969 DAG.getConstant(x86cc, MVT::i8));
22971 bool is64BitFP = (CMP00.getValueType() == MVT::f64);
22972 MVT IntVT = is64BitFP ? MVT::i64 : MVT::i32;
22974 if (is64BitFP && !Subtarget->is64Bit()) {
22975 // On a 32-bit target, we cannot bitcast the 64-bit float to a
22976 // 64-bit integer, since that's not a legal type. Since
22977 // OnesOrZeroesF is all ones of all zeroes, we don't need all the
22978 // bits, but can do this little dance to extract the lowest 32 bits
22979 // and work with those going forward.
22980 SDValue Vector64 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2f64,
22982 SDValue Vector32 = DAG.getNode(ISD::BITCAST, DL, MVT::v4f32,
22984 OnesOrZeroesF = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32,
22985 Vector32, DAG.getIntPtrConstant(0));
22989 SDValue OnesOrZeroesI = DAG.getNode(ISD::BITCAST, DL, IntVT, OnesOrZeroesF);
22990 SDValue ANDed = DAG.getNode(ISD::AND, DL, IntVT, OnesOrZeroesI,
22991 DAG.getConstant(1, IntVT));
22992 SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8, ANDed);
22993 return OneBitOfTruth;
23001 /// CanFoldXORWithAllOnes - Test whether the XOR operand is a AllOnes vector
23002 /// so it can be folded inside ANDNP.
23003 static bool CanFoldXORWithAllOnes(const SDNode *N) {
23004 EVT VT = N->getValueType(0);
23006 // Match direct AllOnes for 128 and 256-bit vectors
23007 if (ISD::isBuildVectorAllOnes(N))
23010 // Look through a bit convert.
23011 if (N->getOpcode() == ISD::BITCAST)
23012 N = N->getOperand(0).getNode();
23014 // Sometimes the operand may come from a insert_subvector building a 256-bit
23016 if (VT.is256BitVector() &&
23017 N->getOpcode() == ISD::INSERT_SUBVECTOR) {
23018 SDValue V1 = N->getOperand(0);
23019 SDValue V2 = N->getOperand(1);
23021 if (V1.getOpcode() == ISD::INSERT_SUBVECTOR &&
23022 V1.getOperand(0).getOpcode() == ISD::UNDEF &&
23023 ISD::isBuildVectorAllOnes(V1.getOperand(1).getNode()) &&
23024 ISD::isBuildVectorAllOnes(V2.getNode()))
23031 // On AVX/AVX2 the type v8i1 is legalized to v8i16, which is an XMM sized
23032 // register. In most cases we actually compare or select YMM-sized registers
23033 // and mixing the two types creates horrible code. This method optimizes
23034 // some of the transition sequences.
23035 static SDValue WidenMaskArithmetic(SDNode *N, SelectionDAG &DAG,
23036 TargetLowering::DAGCombinerInfo &DCI,
23037 const X86Subtarget *Subtarget) {
23038 EVT VT = N->getValueType(0);
23039 if (!VT.is256BitVector())
23042 assert((N->getOpcode() == ISD::ANY_EXTEND ||
23043 N->getOpcode() == ISD::ZERO_EXTEND ||
23044 N->getOpcode() == ISD::SIGN_EXTEND) && "Invalid Node");
23046 SDValue Narrow = N->getOperand(0);
23047 EVT NarrowVT = Narrow->getValueType(0);
23048 if (!NarrowVT.is128BitVector())
23051 if (Narrow->getOpcode() != ISD::XOR &&
23052 Narrow->getOpcode() != ISD::AND &&
23053 Narrow->getOpcode() != ISD::OR)
23056 SDValue N0 = Narrow->getOperand(0);
23057 SDValue N1 = Narrow->getOperand(1);
23060 // The Left side has to be a trunc.
23061 if (N0.getOpcode() != ISD::TRUNCATE)
23064 // The type of the truncated inputs.
23065 EVT WideVT = N0->getOperand(0)->getValueType(0);
23069 // The right side has to be a 'trunc' or a constant vector.
23070 bool RHSTrunc = N1.getOpcode() == ISD::TRUNCATE;
23071 ConstantSDNode *RHSConstSplat = nullptr;
23072 if (auto *RHSBV = dyn_cast<BuildVectorSDNode>(N1))
23073 RHSConstSplat = RHSBV->getConstantSplatNode();
23074 if (!RHSTrunc && !RHSConstSplat)
23077 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23079 if (!TLI.isOperationLegalOrPromote(Narrow->getOpcode(), WideVT))
23082 // Set N0 and N1 to hold the inputs to the new wide operation.
23083 N0 = N0->getOperand(0);
23084 if (RHSConstSplat) {
23085 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, WideVT.getScalarType(),
23086 SDValue(RHSConstSplat, 0));
23087 SmallVector<SDValue, 8> C(WideVT.getVectorNumElements(), N1);
23088 N1 = DAG.getNode(ISD::BUILD_VECTOR, DL, WideVT, C);
23089 } else if (RHSTrunc) {
23090 N1 = N1->getOperand(0);
23093 // Generate the wide operation.
23094 SDValue Op = DAG.getNode(Narrow->getOpcode(), DL, WideVT, N0, N1);
23095 unsigned Opcode = N->getOpcode();
23097 case ISD::ANY_EXTEND:
23099 case ISD::ZERO_EXTEND: {
23100 unsigned InBits = NarrowVT.getScalarType().getSizeInBits();
23101 APInt Mask = APInt::getAllOnesValue(InBits);
23102 Mask = Mask.zext(VT.getScalarType().getSizeInBits());
23103 return DAG.getNode(ISD::AND, DL, VT,
23104 Op, DAG.getConstant(Mask, VT));
23106 case ISD::SIGN_EXTEND:
23107 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT,
23108 Op, DAG.getValueType(NarrowVT));
23110 llvm_unreachable("Unexpected opcode");
23114 static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG,
23115 TargetLowering::DAGCombinerInfo &DCI,
23116 const X86Subtarget *Subtarget) {
23117 EVT VT = N->getValueType(0);
23118 if (DCI.isBeforeLegalizeOps())
23121 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
23125 // Create BEXTR instructions
23126 // BEXTR is ((X >> imm) & (2**size-1))
23127 if (VT == MVT::i32 || VT == MVT::i64) {
23128 SDValue N0 = N->getOperand(0);
23129 SDValue N1 = N->getOperand(1);
23132 // Check for BEXTR.
23133 if ((Subtarget->hasBMI() || Subtarget->hasTBM()) &&
23134 (N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::SRL)) {
23135 ConstantSDNode *MaskNode = dyn_cast<ConstantSDNode>(N1);
23136 ConstantSDNode *ShiftNode = dyn_cast<ConstantSDNode>(N0.getOperand(1));
23137 if (MaskNode && ShiftNode) {
23138 uint64_t Mask = MaskNode->getZExtValue();
23139 uint64_t Shift = ShiftNode->getZExtValue();
23140 if (isMask_64(Mask)) {
23141 uint64_t MaskSize = CountPopulation_64(Mask);
23142 if (Shift + MaskSize <= VT.getSizeInBits())
23143 return DAG.getNode(X86ISD::BEXTR, DL, VT, N0.getOperand(0),
23144 DAG.getConstant(Shift | (MaskSize << 8), VT));
23152 // Want to form ANDNP nodes:
23153 // 1) In the hopes of then easily combining them with OR and AND nodes
23154 // to form PBLEND/PSIGN.
23155 // 2) To match ANDN packed intrinsics
23156 if (VT != MVT::v2i64 && VT != MVT::v4i64)
23159 SDValue N0 = N->getOperand(0);
23160 SDValue N1 = N->getOperand(1);
23163 // Check LHS for vnot
23164 if (N0.getOpcode() == ISD::XOR &&
23165 //ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode()))
23166 CanFoldXORWithAllOnes(N0.getOperand(1).getNode()))
23167 return DAG.getNode(X86ISD::ANDNP, DL, VT, N0.getOperand(0), N1);
23169 // Check RHS for vnot
23170 if (N1.getOpcode() == ISD::XOR &&
23171 //ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode()))
23172 CanFoldXORWithAllOnes(N1.getOperand(1).getNode()))
23173 return DAG.getNode(X86ISD::ANDNP, DL, VT, N1.getOperand(0), N0);
23178 static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
23179 TargetLowering::DAGCombinerInfo &DCI,
23180 const X86Subtarget *Subtarget) {
23181 if (DCI.isBeforeLegalizeOps())
23184 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
23188 SDValue N0 = N->getOperand(0);
23189 SDValue N1 = N->getOperand(1);
23190 EVT VT = N->getValueType(0);
23192 // look for psign/blend
23193 if (VT == MVT::v2i64 || VT == MVT::v4i64) {
23194 if (!Subtarget->hasSSSE3() ||
23195 (VT == MVT::v4i64 && !Subtarget->hasInt256()))
23198 // Canonicalize pandn to RHS
23199 if (N0.getOpcode() == X86ISD::ANDNP)
23201 // or (and (m, y), (pandn m, x))
23202 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::ANDNP) {
23203 SDValue Mask = N1.getOperand(0);
23204 SDValue X = N1.getOperand(1);
23206 if (N0.getOperand(0) == Mask)
23207 Y = N0.getOperand(1);
23208 if (N0.getOperand(1) == Mask)
23209 Y = N0.getOperand(0);
23211 // Check to see if the mask appeared in both the AND and ANDNP and
23215 // Validate that X, Y, and Mask are BIT_CONVERTS, and see through them.
23216 // Look through mask bitcast.
23217 if (Mask.getOpcode() == ISD::BITCAST)
23218 Mask = Mask.getOperand(0);
23219 if (X.getOpcode() == ISD::BITCAST)
23220 X = X.getOperand(0);
23221 if (Y.getOpcode() == ISD::BITCAST)
23222 Y = Y.getOperand(0);
23224 EVT MaskVT = Mask.getValueType();
23226 // Validate that the Mask operand is a vector sra node.
23227 // FIXME: what to do for bytes, since there is a psignb/pblendvb, but
23228 // there is no psrai.b
23229 unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits();
23230 unsigned SraAmt = ~0;
23231 if (Mask.getOpcode() == ISD::SRA) {
23232 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Mask.getOperand(1)))
23233 if (auto *AmtConst = AmtBV->getConstantSplatNode())
23234 SraAmt = AmtConst->getZExtValue();
23235 } else if (Mask.getOpcode() == X86ISD::VSRAI) {
23236 SDValue SraC = Mask.getOperand(1);
23237 SraAmt = cast<ConstantSDNode>(SraC)->getZExtValue();
23239 if ((SraAmt + 1) != EltBits)
23244 // Now we know we at least have a plendvb with the mask val. See if
23245 // we can form a psignb/w/d.
23246 // psign = x.type == y.type == mask.type && y = sub(0, x);
23247 if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X &&
23248 ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) &&
23249 X.getValueType() == MaskVT && Y.getValueType() == MaskVT) {
23250 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
23251 "Unsupported VT for PSIGN");
23252 Mask = DAG.getNode(X86ISD::PSIGN, DL, MaskVT, X, Mask.getOperand(0));
23253 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
23255 // PBLENDVB only available on SSE 4.1
23256 if (!Subtarget->hasSSE41())
23259 EVT BlendVT = (VT == MVT::v4i64) ? MVT::v32i8 : MVT::v16i8;
23261 X = DAG.getNode(ISD::BITCAST, DL, BlendVT, X);
23262 Y = DAG.getNode(ISD::BITCAST, DL, BlendVT, Y);
23263 Mask = DAG.getNode(ISD::BITCAST, DL, BlendVT, Mask);
23264 Mask = DAG.getNode(ISD::VSELECT, DL, BlendVT, Mask, Y, X);
23265 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
23269 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64)
23272 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
23273 MachineFunction &MF = DAG.getMachineFunction();
23274 bool OptForSize = MF.getFunction()->getAttributes().
23275 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
23277 // SHLD/SHRD instructions have lower register pressure, but on some
23278 // platforms they have higher latency than the equivalent
23279 // series of shifts/or that would otherwise be generated.
23280 // Don't fold (or (x << c) | (y >> (64 - c))) if SHLD/SHRD instructions
23281 // have higher latencies and we are not optimizing for size.
23282 if (!OptForSize && Subtarget->isSHLDSlow())
23285 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
23287 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
23289 if (!N0.hasOneUse() || !N1.hasOneUse())
23292 SDValue ShAmt0 = N0.getOperand(1);
23293 if (ShAmt0.getValueType() != MVT::i8)
23295 SDValue ShAmt1 = N1.getOperand(1);
23296 if (ShAmt1.getValueType() != MVT::i8)
23298 if (ShAmt0.getOpcode() == ISD::TRUNCATE)
23299 ShAmt0 = ShAmt0.getOperand(0);
23300 if (ShAmt1.getOpcode() == ISD::TRUNCATE)
23301 ShAmt1 = ShAmt1.getOperand(0);
23304 unsigned Opc = X86ISD::SHLD;
23305 SDValue Op0 = N0.getOperand(0);
23306 SDValue Op1 = N1.getOperand(0);
23307 if (ShAmt0.getOpcode() == ISD::SUB) {
23308 Opc = X86ISD::SHRD;
23309 std::swap(Op0, Op1);
23310 std::swap(ShAmt0, ShAmt1);
23313 unsigned Bits = VT.getSizeInBits();
23314 if (ShAmt1.getOpcode() == ISD::SUB) {
23315 SDValue Sum = ShAmt1.getOperand(0);
23316 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) {
23317 SDValue ShAmt1Op1 = ShAmt1.getOperand(1);
23318 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE)
23319 ShAmt1Op1 = ShAmt1Op1.getOperand(0);
23320 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0)
23321 return DAG.getNode(Opc, DL, VT,
23323 DAG.getNode(ISD::TRUNCATE, DL,
23326 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) {
23327 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0);
23329 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits)
23330 return DAG.getNode(Opc, DL, VT,
23331 N0.getOperand(0), N1.getOperand(0),
23332 DAG.getNode(ISD::TRUNCATE, DL,
23339 // Generate NEG and CMOV for integer abs.
23340 static SDValue performIntegerAbsCombine(SDNode *N, SelectionDAG &DAG) {
23341 EVT VT = N->getValueType(0);
23343 // Since X86 does not have CMOV for 8-bit integer, we don't convert
23344 // 8-bit integer abs to NEG and CMOV.
23345 if (VT.isInteger() && VT.getSizeInBits() == 8)
23348 SDValue N0 = N->getOperand(0);
23349 SDValue N1 = N->getOperand(1);
23352 // Check pattern of XOR(ADD(X,Y), Y) where Y is SRA(X, size(X)-1)
23353 // and change it to SUB and CMOV.
23354 if (VT.isInteger() && N->getOpcode() == ISD::XOR &&
23355 N0.getOpcode() == ISD::ADD &&
23356 N0.getOperand(1) == N1 &&
23357 N1.getOpcode() == ISD::SRA &&
23358 N1.getOperand(0) == N0.getOperand(0))
23359 if (ConstantSDNode *Y1C = dyn_cast<ConstantSDNode>(N1.getOperand(1)))
23360 if (Y1C->getAPIntValue() == VT.getSizeInBits()-1) {
23361 // Generate SUB & CMOV.
23362 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, DAG.getVTList(VT, MVT::i32),
23363 DAG.getConstant(0, VT), N0.getOperand(0));
23365 SDValue Ops[] = { N0.getOperand(0), Neg,
23366 DAG.getConstant(X86::COND_GE, MVT::i8),
23367 SDValue(Neg.getNode(), 1) };
23368 return DAG.getNode(X86ISD::CMOV, DL, DAG.getVTList(VT, MVT::Glue), Ops);
23373 // PerformXorCombine - Attempts to turn XOR nodes into BLSMSK nodes
23374 static SDValue PerformXorCombine(SDNode *N, SelectionDAG &DAG,
23375 TargetLowering::DAGCombinerInfo &DCI,
23376 const X86Subtarget *Subtarget) {
23377 if (DCI.isBeforeLegalizeOps())
23380 if (Subtarget->hasCMov()) {
23381 SDValue RV = performIntegerAbsCombine(N, DAG);
23389 /// PerformLOADCombine - Do target-specific dag combines on LOAD nodes.
23390 static SDValue PerformLOADCombine(SDNode *N, SelectionDAG &DAG,
23391 TargetLowering::DAGCombinerInfo &DCI,
23392 const X86Subtarget *Subtarget) {
23393 LoadSDNode *Ld = cast<LoadSDNode>(N);
23394 EVT RegVT = Ld->getValueType(0);
23395 EVT MemVT = Ld->getMemoryVT();
23397 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23399 // On Sandybridge unaligned 256bit loads are inefficient.
23400 ISD::LoadExtType Ext = Ld->getExtensionType();
23401 unsigned Alignment = Ld->getAlignment();
23402 bool IsAligned = Alignment == 0 || Alignment >= MemVT.getSizeInBits()/8;
23403 if (RegVT.is256BitVector() && !Subtarget->hasInt256() &&
23404 !DCI.isBeforeLegalizeOps() && !IsAligned && Ext == ISD::NON_EXTLOAD) {
23405 unsigned NumElems = RegVT.getVectorNumElements();
23409 SDValue Ptr = Ld->getBasePtr();
23410 SDValue Increment = DAG.getConstant(16, TLI.getPointerTy());
23412 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
23414 SDValue Load1 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
23415 Ld->getPointerInfo(), Ld->isVolatile(),
23416 Ld->isNonTemporal(), Ld->isInvariant(),
23418 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
23419 SDValue Load2 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
23420 Ld->getPointerInfo(), Ld->isVolatile(),
23421 Ld->isNonTemporal(), Ld->isInvariant(),
23422 std::min(16U, Alignment));
23423 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
23425 Load2.getValue(1));
23427 SDValue NewVec = DAG.getUNDEF(RegVT);
23428 NewVec = Insert128BitVector(NewVec, Load1, 0, DAG, dl);
23429 NewVec = Insert128BitVector(NewVec, Load2, NumElems/2, DAG, dl);
23430 return DCI.CombineTo(N, NewVec, TF, true);
23436 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
23437 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
23438 const X86Subtarget *Subtarget) {
23439 StoreSDNode *St = cast<StoreSDNode>(N);
23440 EVT VT = St->getValue().getValueType();
23441 EVT StVT = St->getMemoryVT();
23443 SDValue StoredVal = St->getOperand(1);
23444 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23446 // If we are saving a concatenation of two XMM registers, perform two stores.
23447 // On Sandy Bridge, 256-bit memory operations are executed by two
23448 // 128-bit ports. However, on Haswell it is better to issue a single 256-bit
23449 // memory operation.
23450 unsigned Alignment = St->getAlignment();
23451 bool IsAligned = Alignment == 0 || Alignment >= VT.getSizeInBits()/8;
23452 if (VT.is256BitVector() && !Subtarget->hasInt256() &&
23453 StVT == VT && !IsAligned) {
23454 unsigned NumElems = VT.getVectorNumElements();
23458 SDValue Value0 = Extract128BitVector(StoredVal, 0, DAG, dl);
23459 SDValue Value1 = Extract128BitVector(StoredVal, NumElems/2, DAG, dl);
23461 SDValue Stride = DAG.getConstant(16, TLI.getPointerTy());
23462 SDValue Ptr0 = St->getBasePtr();
23463 SDValue Ptr1 = DAG.getNode(ISD::ADD, dl, Ptr0.getValueType(), Ptr0, Stride);
23465 SDValue Ch0 = DAG.getStore(St->getChain(), dl, Value0, Ptr0,
23466 St->getPointerInfo(), St->isVolatile(),
23467 St->isNonTemporal(), Alignment);
23468 SDValue Ch1 = DAG.getStore(St->getChain(), dl, Value1, Ptr1,
23469 St->getPointerInfo(), St->isVolatile(),
23470 St->isNonTemporal(),
23471 std::min(16U, Alignment));
23472 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ch0, Ch1);
23475 // Optimize trunc store (of multiple scalars) to shuffle and store.
23476 // First, pack all of the elements in one place. Next, store to memory
23477 // in fewer chunks.
23478 if (St->isTruncatingStore() && VT.isVector()) {
23479 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23480 unsigned NumElems = VT.getVectorNumElements();
23481 assert(StVT != VT && "Cannot truncate to the same type");
23482 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
23483 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
23485 // From, To sizes and ElemCount must be pow of two
23486 if (!isPowerOf2_32(NumElems * FromSz * ToSz)) return SDValue();
23487 // We are going to use the original vector elt for storing.
23488 // Accumulated smaller vector elements must be a multiple of the store size.
23489 if (0 != (NumElems * FromSz) % ToSz) return SDValue();
23491 unsigned SizeRatio = FromSz / ToSz;
23493 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
23495 // Create a type on which we perform the shuffle
23496 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
23497 StVT.getScalarType(), NumElems*SizeRatio);
23499 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
23501 SDValue WideVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, St->getValue());
23502 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
23503 for (unsigned i = 0; i != NumElems; ++i)
23504 ShuffleVec[i] = i * SizeRatio;
23506 // Can't shuffle using an illegal type.
23507 if (!TLI.isTypeLegal(WideVecVT))
23510 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
23511 DAG.getUNDEF(WideVecVT),
23513 // At this point all of the data is stored at the bottom of the
23514 // register. We now need to save it to mem.
23516 // Find the largest store unit
23517 MVT StoreType = MVT::i8;
23518 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
23519 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
23520 MVT Tp = (MVT::SimpleValueType)tp;
23521 if (TLI.isTypeLegal(Tp) && Tp.getSizeInBits() <= NumElems * ToSz)
23525 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
23526 if (TLI.isTypeLegal(MVT::f64) && StoreType.getSizeInBits() < 64 &&
23527 (64 <= NumElems * ToSz))
23528 StoreType = MVT::f64;
23530 // Bitcast the original vector into a vector of store-size units
23531 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(),
23532 StoreType, VT.getSizeInBits()/StoreType.getSizeInBits());
23533 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits());
23534 SDValue ShuffWide = DAG.getNode(ISD::BITCAST, dl, StoreVecVT, Shuff);
23535 SmallVector<SDValue, 8> Chains;
23536 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits()/8,
23537 TLI.getPointerTy());
23538 SDValue Ptr = St->getBasePtr();
23540 // Perform one or more big stores into memory.
23541 for (unsigned i=0, e=(ToSz*NumElems)/StoreType.getSizeInBits(); i!=e; ++i) {
23542 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
23543 StoreType, ShuffWide,
23544 DAG.getIntPtrConstant(i));
23545 SDValue Ch = DAG.getStore(St->getChain(), dl, SubVec, Ptr,
23546 St->getPointerInfo(), St->isVolatile(),
23547 St->isNonTemporal(), St->getAlignment());
23548 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
23549 Chains.push_back(Ch);
23552 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
23555 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
23556 // the FP state in cases where an emms may be missing.
23557 // A preferable solution to the general problem is to figure out the right
23558 // places to insert EMMS. This qualifies as a quick hack.
23560 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
23561 if (VT.getSizeInBits() != 64)
23564 const Function *F = DAG.getMachineFunction().getFunction();
23565 bool NoImplicitFloatOps = F->getAttributes().
23566 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoImplicitFloat);
23567 bool F64IsLegal = !DAG.getTarget().Options.UseSoftFloat && !NoImplicitFloatOps
23568 && Subtarget->hasSSE2();
23569 if ((VT.isVector() ||
23570 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
23571 isa<LoadSDNode>(St->getValue()) &&
23572 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
23573 St->getChain().hasOneUse() && !St->isVolatile()) {
23574 SDNode* LdVal = St->getValue().getNode();
23575 LoadSDNode *Ld = nullptr;
23576 int TokenFactorIndex = -1;
23577 SmallVector<SDValue, 8> Ops;
23578 SDNode* ChainVal = St->getChain().getNode();
23579 // Must be a store of a load. We currently handle two cases: the load
23580 // is a direct child, and it's under an intervening TokenFactor. It is
23581 // possible to dig deeper under nested TokenFactors.
23582 if (ChainVal == LdVal)
23583 Ld = cast<LoadSDNode>(St->getChain());
23584 else if (St->getValue().hasOneUse() &&
23585 ChainVal->getOpcode() == ISD::TokenFactor) {
23586 for (unsigned i = 0, e = ChainVal->getNumOperands(); i != e; ++i) {
23587 if (ChainVal->getOperand(i).getNode() == LdVal) {
23588 TokenFactorIndex = i;
23589 Ld = cast<LoadSDNode>(St->getValue());
23591 Ops.push_back(ChainVal->getOperand(i));
23595 if (!Ld || !ISD::isNormalLoad(Ld))
23598 // If this is not the MMX case, i.e. we are just turning i64 load/store
23599 // into f64 load/store, avoid the transformation if there are multiple
23600 // uses of the loaded value.
23601 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
23606 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
23607 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
23609 if (Subtarget->is64Bit() || F64IsLegal) {
23610 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
23611 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(),
23612 Ld->getPointerInfo(), Ld->isVolatile(),
23613 Ld->isNonTemporal(), Ld->isInvariant(),
23614 Ld->getAlignment());
23615 SDValue NewChain = NewLd.getValue(1);
23616 if (TokenFactorIndex != -1) {
23617 Ops.push_back(NewChain);
23618 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
23620 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
23621 St->getPointerInfo(),
23622 St->isVolatile(), St->isNonTemporal(),
23623 St->getAlignment());
23626 // Otherwise, lower to two pairs of 32-bit loads / stores.
23627 SDValue LoAddr = Ld->getBasePtr();
23628 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
23629 DAG.getConstant(4, MVT::i32));
23631 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
23632 Ld->getPointerInfo(),
23633 Ld->isVolatile(), Ld->isNonTemporal(),
23634 Ld->isInvariant(), Ld->getAlignment());
23635 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
23636 Ld->getPointerInfo().getWithOffset(4),
23637 Ld->isVolatile(), Ld->isNonTemporal(),
23639 MinAlign(Ld->getAlignment(), 4));
23641 SDValue NewChain = LoLd.getValue(1);
23642 if (TokenFactorIndex != -1) {
23643 Ops.push_back(LoLd);
23644 Ops.push_back(HiLd);
23645 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
23648 LoAddr = St->getBasePtr();
23649 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
23650 DAG.getConstant(4, MVT::i32));
23652 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
23653 St->getPointerInfo(),
23654 St->isVolatile(), St->isNonTemporal(),
23655 St->getAlignment());
23656 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
23657 St->getPointerInfo().getWithOffset(4),
23659 St->isNonTemporal(),
23660 MinAlign(St->getAlignment(), 4));
23661 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
23666 /// isHorizontalBinOp - Return 'true' if this vector operation is "horizontal"
23667 /// and return the operands for the horizontal operation in LHS and RHS. A
23668 /// horizontal operation performs the binary operation on successive elements
23669 /// of its first operand, then on successive elements of its second operand,
23670 /// returning the resulting values in a vector. For example, if
23671 /// A = < float a0, float a1, float a2, float a3 >
23673 /// B = < float b0, float b1, float b2, float b3 >
23674 /// then the result of doing a horizontal operation on A and B is
23675 /// A horizontal-op B = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >.
23676 /// In short, LHS and RHS are inspected to see if LHS op RHS is of the form
23677 /// A horizontal-op B, for some already available A and B, and if so then LHS is
23678 /// set to A, RHS to B, and the routine returns 'true'.
23679 /// Note that the binary operation should have the property that if one of the
23680 /// operands is UNDEF then the result is UNDEF.
23681 static bool isHorizontalBinOp(SDValue &LHS, SDValue &RHS, bool IsCommutative) {
23682 // Look for the following pattern: if
23683 // A = < float a0, float a1, float a2, float a3 >
23684 // B = < float b0, float b1, float b2, float b3 >
23686 // LHS = VECTOR_SHUFFLE A, B, <0, 2, 4, 6>
23687 // RHS = VECTOR_SHUFFLE A, B, <1, 3, 5, 7>
23688 // then LHS op RHS = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >
23689 // which is A horizontal-op B.
23691 // At least one of the operands should be a vector shuffle.
23692 if (LHS.getOpcode() != ISD::VECTOR_SHUFFLE &&
23693 RHS.getOpcode() != ISD::VECTOR_SHUFFLE)
23696 MVT VT = LHS.getSimpleValueType();
23698 assert((VT.is128BitVector() || VT.is256BitVector()) &&
23699 "Unsupported vector type for horizontal add/sub");
23701 // Handle 128 and 256-bit vector lengths. AVX defines horizontal add/sub to
23702 // operate independently on 128-bit lanes.
23703 unsigned NumElts = VT.getVectorNumElements();
23704 unsigned NumLanes = VT.getSizeInBits()/128;
23705 unsigned NumLaneElts = NumElts / NumLanes;
23706 assert((NumLaneElts % 2 == 0) &&
23707 "Vector type should have an even number of elements in each lane");
23708 unsigned HalfLaneElts = NumLaneElts/2;
23710 // View LHS in the form
23711 // LHS = VECTOR_SHUFFLE A, B, LMask
23712 // If LHS is not a shuffle then pretend it is the shuffle
23713 // LHS = VECTOR_SHUFFLE LHS, undef, <0, 1, ..., N-1>
23714 // NOTE: in what follows a default initialized SDValue represents an UNDEF of
23717 SmallVector<int, 16> LMask(NumElts);
23718 if (LHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
23719 if (LHS.getOperand(0).getOpcode() != ISD::UNDEF)
23720 A = LHS.getOperand(0);
23721 if (LHS.getOperand(1).getOpcode() != ISD::UNDEF)
23722 B = LHS.getOperand(1);
23723 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(LHS.getNode())->getMask();
23724 std::copy(Mask.begin(), Mask.end(), LMask.begin());
23726 if (LHS.getOpcode() != ISD::UNDEF)
23728 for (unsigned i = 0; i != NumElts; ++i)
23732 // Likewise, view RHS in the form
23733 // RHS = VECTOR_SHUFFLE C, D, RMask
23735 SmallVector<int, 16> RMask(NumElts);
23736 if (RHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
23737 if (RHS.getOperand(0).getOpcode() != ISD::UNDEF)
23738 C = RHS.getOperand(0);
23739 if (RHS.getOperand(1).getOpcode() != ISD::UNDEF)
23740 D = RHS.getOperand(1);
23741 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(RHS.getNode())->getMask();
23742 std::copy(Mask.begin(), Mask.end(), RMask.begin());
23744 if (RHS.getOpcode() != ISD::UNDEF)
23746 for (unsigned i = 0; i != NumElts; ++i)
23750 // Check that the shuffles are both shuffling the same vectors.
23751 if (!(A == C && B == D) && !(A == D && B == C))
23754 // If everything is UNDEF then bail out: it would be better to fold to UNDEF.
23755 if (!A.getNode() && !B.getNode())
23758 // If A and B occur in reverse order in RHS, then "swap" them (which means
23759 // rewriting the mask).
23761 CommuteVectorShuffleMask(RMask, NumElts);
23763 // At this point LHS and RHS are equivalent to
23764 // LHS = VECTOR_SHUFFLE A, B, LMask
23765 // RHS = VECTOR_SHUFFLE A, B, RMask
23766 // Check that the masks correspond to performing a horizontal operation.
23767 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
23768 for (unsigned i = 0; i != NumLaneElts; ++i) {
23769 int LIdx = LMask[i+l], RIdx = RMask[i+l];
23771 // Ignore any UNDEF components.
23772 if (LIdx < 0 || RIdx < 0 ||
23773 (!A.getNode() && (LIdx < (int)NumElts || RIdx < (int)NumElts)) ||
23774 (!B.getNode() && (LIdx >= (int)NumElts || RIdx >= (int)NumElts)))
23777 // Check that successive elements are being operated on. If not, this is
23778 // not a horizontal operation.
23779 unsigned Src = (i/HalfLaneElts); // each lane is split between srcs
23780 int Index = 2*(i%HalfLaneElts) + NumElts*Src + l;
23781 if (!(LIdx == Index && RIdx == Index + 1) &&
23782 !(IsCommutative && LIdx == Index + 1 && RIdx == Index))
23787 LHS = A.getNode() ? A : B; // If A is 'UNDEF', use B for it.
23788 RHS = B.getNode() ? B : A; // If B is 'UNDEF', use A for it.
23792 /// PerformFADDCombine - Do target-specific dag combines on floating point adds.
23793 static SDValue PerformFADDCombine(SDNode *N, SelectionDAG &DAG,
23794 const X86Subtarget *Subtarget) {
23795 EVT VT = N->getValueType(0);
23796 SDValue LHS = N->getOperand(0);
23797 SDValue RHS = N->getOperand(1);
23799 // Try to synthesize horizontal adds from adds of shuffles.
23800 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
23801 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
23802 isHorizontalBinOp(LHS, RHS, true))
23803 return DAG.getNode(X86ISD::FHADD, SDLoc(N), VT, LHS, RHS);
23807 /// PerformFSUBCombine - Do target-specific dag combines on floating point subs.
23808 static SDValue PerformFSUBCombine(SDNode *N, SelectionDAG &DAG,
23809 const X86Subtarget *Subtarget) {
23810 EVT VT = N->getValueType(0);
23811 SDValue LHS = N->getOperand(0);
23812 SDValue RHS = N->getOperand(1);
23814 // Try to synthesize horizontal subs from subs of shuffles.
23815 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
23816 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
23817 isHorizontalBinOp(LHS, RHS, false))
23818 return DAG.getNode(X86ISD::FHSUB, SDLoc(N), VT, LHS, RHS);
23822 /// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and
23823 /// X86ISD::FXOR nodes.
23824 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
23825 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
23826 // F[X]OR(0.0, x) -> x
23827 // F[X]OR(x, 0.0) -> x
23828 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
23829 if (C->getValueAPF().isPosZero())
23830 return N->getOperand(1);
23831 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
23832 if (C->getValueAPF().isPosZero())
23833 return N->getOperand(0);
23837 /// PerformFMinFMaxCombine - Do target-specific dag combines on X86ISD::FMIN and
23838 /// X86ISD::FMAX nodes.
23839 static SDValue PerformFMinFMaxCombine(SDNode *N, SelectionDAG &DAG) {
23840 assert(N->getOpcode() == X86ISD::FMIN || N->getOpcode() == X86ISD::FMAX);
23842 // Only perform optimizations if UnsafeMath is used.
23843 if (!DAG.getTarget().Options.UnsafeFPMath)
23846 // If we run in unsafe-math mode, then convert the FMAX and FMIN nodes
23847 // into FMINC and FMAXC, which are Commutative operations.
23848 unsigned NewOp = 0;
23849 switch (N->getOpcode()) {
23850 default: llvm_unreachable("unknown opcode");
23851 case X86ISD::FMIN: NewOp = X86ISD::FMINC; break;
23852 case X86ISD::FMAX: NewOp = X86ISD::FMAXC; break;
23855 return DAG.getNode(NewOp, SDLoc(N), N->getValueType(0),
23856 N->getOperand(0), N->getOperand(1));
23859 /// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes.
23860 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
23861 // FAND(0.0, x) -> 0.0
23862 // FAND(x, 0.0) -> 0.0
23863 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
23864 if (C->getValueAPF().isPosZero())
23865 return N->getOperand(0);
23866 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
23867 if (C->getValueAPF().isPosZero())
23868 return N->getOperand(1);
23872 /// PerformFANDNCombine - Do target-specific dag combines on X86ISD::FANDN nodes
23873 static SDValue PerformFANDNCombine(SDNode *N, SelectionDAG &DAG) {
23874 // FANDN(x, 0.0) -> 0.0
23875 // FANDN(0.0, x) -> x
23876 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
23877 if (C->getValueAPF().isPosZero())
23878 return N->getOperand(1);
23879 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
23880 if (C->getValueAPF().isPosZero())
23881 return N->getOperand(1);
23885 static SDValue PerformBTCombine(SDNode *N,
23887 TargetLowering::DAGCombinerInfo &DCI) {
23888 // BT ignores high bits in the bit index operand.
23889 SDValue Op1 = N->getOperand(1);
23890 if (Op1.hasOneUse()) {
23891 unsigned BitWidth = Op1.getValueSizeInBits();
23892 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
23893 APInt KnownZero, KnownOne;
23894 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
23895 !DCI.isBeforeLegalizeOps());
23896 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23897 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
23898 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
23899 DCI.CommitTargetLoweringOpt(TLO);
23904 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
23905 SDValue Op = N->getOperand(0);
23906 if (Op.getOpcode() == ISD::BITCAST)
23907 Op = Op.getOperand(0);
23908 EVT VT = N->getValueType(0), OpVT = Op.getValueType();
23909 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
23910 VT.getVectorElementType().getSizeInBits() ==
23911 OpVT.getVectorElementType().getSizeInBits()) {
23912 return DAG.getNode(ISD::BITCAST, SDLoc(N), VT, Op);
23917 static SDValue PerformSIGN_EXTEND_INREGCombine(SDNode *N, SelectionDAG &DAG,
23918 const X86Subtarget *Subtarget) {
23919 EVT VT = N->getValueType(0);
23920 if (!VT.isVector())
23923 SDValue N0 = N->getOperand(0);
23924 SDValue N1 = N->getOperand(1);
23925 EVT ExtraVT = cast<VTSDNode>(N1)->getVT();
23928 // The SIGN_EXTEND_INREG to v4i64 is expensive operation on the
23929 // both SSE and AVX2 since there is no sign-extended shift right
23930 // operation on a vector with 64-bit elements.
23931 //(sext_in_reg (v4i64 anyext (v4i32 x )), ExtraVT) ->
23932 // (v4i64 sext (v4i32 sext_in_reg (v4i32 x , ExtraVT)))
23933 if (VT == MVT::v4i64 && (N0.getOpcode() == ISD::ANY_EXTEND ||
23934 N0.getOpcode() == ISD::SIGN_EXTEND)) {
23935 SDValue N00 = N0.getOperand(0);
23937 // EXTLOAD has a better solution on AVX2,
23938 // it may be replaced with X86ISD::VSEXT node.
23939 if (N00.getOpcode() == ISD::LOAD && Subtarget->hasInt256())
23940 if (!ISD::isNormalLoad(N00.getNode()))
23943 if (N00.getValueType() == MVT::v4i32 && ExtraVT.getSizeInBits() < 128) {
23944 SDValue Tmp = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v4i32,
23946 return DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i64, Tmp);
23952 static SDValue PerformSExtCombine(SDNode *N, SelectionDAG &DAG,
23953 TargetLowering::DAGCombinerInfo &DCI,
23954 const X86Subtarget *Subtarget) {
23955 if (!DCI.isBeforeLegalizeOps())
23958 if (!Subtarget->hasFp256())
23961 EVT VT = N->getValueType(0);
23962 if (VT.isVector() && VT.getSizeInBits() == 256) {
23963 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget);
23971 static SDValue PerformFMACombine(SDNode *N, SelectionDAG &DAG,
23972 const X86Subtarget* Subtarget) {
23974 EVT VT = N->getValueType(0);
23976 // Let legalize expand this if it isn't a legal type yet.
23977 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
23980 EVT ScalarVT = VT.getScalarType();
23981 if ((ScalarVT != MVT::f32 && ScalarVT != MVT::f64) ||
23982 (!Subtarget->hasFMA() && !Subtarget->hasFMA4()))
23985 SDValue A = N->getOperand(0);
23986 SDValue B = N->getOperand(1);
23987 SDValue C = N->getOperand(2);
23989 bool NegA = (A.getOpcode() == ISD::FNEG);
23990 bool NegB = (B.getOpcode() == ISD::FNEG);
23991 bool NegC = (C.getOpcode() == ISD::FNEG);
23993 // Negative multiplication when NegA xor NegB
23994 bool NegMul = (NegA != NegB);
23996 A = A.getOperand(0);
23998 B = B.getOperand(0);
24000 C = C.getOperand(0);
24004 Opcode = (!NegC) ? X86ISD::FMADD : X86ISD::FMSUB;
24006 Opcode = (!NegC) ? X86ISD::FNMADD : X86ISD::FNMSUB;
24008 return DAG.getNode(Opcode, dl, VT, A, B, C);
24011 static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG,
24012 TargetLowering::DAGCombinerInfo &DCI,
24013 const X86Subtarget *Subtarget) {
24014 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) ->
24015 // (and (i32 x86isd::setcc_carry), 1)
24016 // This eliminates the zext. This transformation is necessary because
24017 // ISD::SETCC is always legalized to i8.
24019 SDValue N0 = N->getOperand(0);
24020 EVT VT = N->getValueType(0);
24022 if (N0.getOpcode() == ISD::AND &&
24024 N0.getOperand(0).hasOneUse()) {
24025 SDValue N00 = N0.getOperand(0);
24026 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
24027 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
24028 if (!C || C->getZExtValue() != 1)
24030 return DAG.getNode(ISD::AND, dl, VT,
24031 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
24032 N00.getOperand(0), N00.getOperand(1)),
24033 DAG.getConstant(1, VT));
24037 if (N0.getOpcode() == ISD::TRUNCATE &&
24039 N0.getOperand(0).hasOneUse()) {
24040 SDValue N00 = N0.getOperand(0);
24041 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
24042 return DAG.getNode(ISD::AND, dl, VT,
24043 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
24044 N00.getOperand(0), N00.getOperand(1)),
24045 DAG.getConstant(1, VT));
24048 if (VT.is256BitVector()) {
24049 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget);
24057 // Optimize x == -y --> x+y == 0
24058 // x != -y --> x+y != 0
24059 static SDValue PerformISDSETCCCombine(SDNode *N, SelectionDAG &DAG,
24060 const X86Subtarget* Subtarget) {
24061 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
24062 SDValue LHS = N->getOperand(0);
24063 SDValue RHS = N->getOperand(1);
24064 EVT VT = N->getValueType(0);
24067 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && LHS.getOpcode() == ISD::SUB)
24068 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(LHS.getOperand(0)))
24069 if (C->getAPIntValue() == 0 && LHS.hasOneUse()) {
24070 SDValue addV = DAG.getNode(ISD::ADD, SDLoc(N),
24071 LHS.getValueType(), RHS, LHS.getOperand(1));
24072 return DAG.getSetCC(SDLoc(N), N->getValueType(0),
24073 addV, DAG.getConstant(0, addV.getValueType()), CC);
24075 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && RHS.getOpcode() == ISD::SUB)
24076 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS.getOperand(0)))
24077 if (C->getAPIntValue() == 0 && RHS.hasOneUse()) {
24078 SDValue addV = DAG.getNode(ISD::ADD, SDLoc(N),
24079 RHS.getValueType(), LHS, RHS.getOperand(1));
24080 return DAG.getSetCC(SDLoc(N), N->getValueType(0),
24081 addV, DAG.getConstant(0, addV.getValueType()), CC);
24084 if (VT.getScalarType() == MVT::i1) {
24085 bool IsSEXT0 = (LHS.getOpcode() == ISD::SIGN_EXTEND) &&
24086 (LHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
24087 bool IsVZero0 = ISD::isBuildVectorAllZeros(LHS.getNode());
24088 if (!IsSEXT0 && !IsVZero0)
24090 bool IsSEXT1 = (RHS.getOpcode() == ISD::SIGN_EXTEND) &&
24091 (RHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
24092 bool IsVZero1 = ISD::isBuildVectorAllZeros(RHS.getNode());
24094 if (!IsSEXT1 && !IsVZero1)
24097 if (IsSEXT0 && IsVZero1) {
24098 assert(VT == LHS.getOperand(0).getValueType() && "Uexpected operand type");
24099 if (CC == ISD::SETEQ)
24100 return DAG.getNOT(DL, LHS.getOperand(0), VT);
24101 return LHS.getOperand(0);
24103 if (IsSEXT1 && IsVZero0) {
24104 assert(VT == RHS.getOperand(0).getValueType() && "Uexpected operand type");
24105 if (CC == ISD::SETEQ)
24106 return DAG.getNOT(DL, RHS.getOperand(0), VT);
24107 return RHS.getOperand(0);
24114 static SDValue PerformINSERTPSCombine(SDNode *N, SelectionDAG &DAG,
24115 const X86Subtarget *Subtarget) {
24117 MVT VT = N->getOperand(1)->getSimpleValueType(0);
24118 assert((VT == MVT::v4f32 || VT == MVT::v4i32) &&
24119 "X86insertps is only defined for v4x32");
24121 SDValue Ld = N->getOperand(1);
24122 if (MayFoldLoad(Ld)) {
24123 // Extract the countS bits from the immediate so we can get the proper
24124 // address when narrowing the vector load to a specific element.
24125 // When the second source op is a memory address, interps doesn't use
24126 // countS and just gets an f32 from that address.
24127 unsigned DestIndex =
24128 cast<ConstantSDNode>(N->getOperand(2))->getZExtValue() >> 6;
24129 Ld = NarrowVectorLoadToElement(cast<LoadSDNode>(Ld), DestIndex, DAG);
24133 // Create this as a scalar to vector to match the instruction pattern.
24134 SDValue LoadScalarToVector = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Ld);
24135 // countS bits are ignored when loading from memory on insertps, which
24136 // means we don't need to explicitly set them to 0.
24137 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N->getOperand(0),
24138 LoadScalarToVector, N->getOperand(2));
24141 // Helper function of PerformSETCCCombine. It is to materialize "setb reg"
24142 // as "sbb reg,reg", since it can be extended without zext and produces
24143 // an all-ones bit which is more useful than 0/1 in some cases.
24144 static SDValue MaterializeSETB(SDLoc DL, SDValue EFLAGS, SelectionDAG &DAG,
24147 return DAG.getNode(ISD::AND, DL, VT,
24148 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
24149 DAG.getConstant(X86::COND_B, MVT::i8), EFLAGS),
24150 DAG.getConstant(1, VT));
24151 assert (VT == MVT::i1 && "Unexpected type for SECCC node");
24152 return DAG.getNode(ISD::TRUNCATE, DL, MVT::i1,
24153 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
24154 DAG.getConstant(X86::COND_B, MVT::i8), EFLAGS));
24157 // Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT
24158 static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG,
24159 TargetLowering::DAGCombinerInfo &DCI,
24160 const X86Subtarget *Subtarget) {
24162 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(0));
24163 SDValue EFLAGS = N->getOperand(1);
24165 if (CC == X86::COND_A) {
24166 // Try to convert COND_A into COND_B in an attempt to facilitate
24167 // materializing "setb reg".
24169 // Do not flip "e > c", where "c" is a constant, because Cmp instruction
24170 // cannot take an immediate as its first operand.
24172 if (EFLAGS.getOpcode() == X86ISD::SUB && EFLAGS.hasOneUse() &&
24173 EFLAGS.getValueType().isInteger() &&
24174 !isa<ConstantSDNode>(EFLAGS.getOperand(1))) {
24175 SDValue NewSub = DAG.getNode(X86ISD::SUB, SDLoc(EFLAGS),
24176 EFLAGS.getNode()->getVTList(),
24177 EFLAGS.getOperand(1), EFLAGS.getOperand(0));
24178 SDValue NewEFLAGS = SDValue(NewSub.getNode(), EFLAGS.getResNo());
24179 return MaterializeSETB(DL, NewEFLAGS, DAG, N->getSimpleValueType(0));
24183 // Materialize "setb reg" as "sbb reg,reg", since it can be extended without
24184 // a zext and produces an all-ones bit which is more useful than 0/1 in some
24186 if (CC == X86::COND_B)
24187 return MaterializeSETB(DL, EFLAGS, DAG, N->getSimpleValueType(0));
24191 Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
24192 if (Flags.getNode()) {
24193 SDValue Cond = DAG.getConstant(CC, MVT::i8);
24194 return DAG.getNode(X86ISD::SETCC, DL, N->getVTList(), Cond, Flags);
24200 // Optimize branch condition evaluation.
24202 static SDValue PerformBrCondCombine(SDNode *N, SelectionDAG &DAG,
24203 TargetLowering::DAGCombinerInfo &DCI,
24204 const X86Subtarget *Subtarget) {
24206 SDValue Chain = N->getOperand(0);
24207 SDValue Dest = N->getOperand(1);
24208 SDValue EFLAGS = N->getOperand(3);
24209 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(2));
24213 Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
24214 if (Flags.getNode()) {
24215 SDValue Cond = DAG.getConstant(CC, MVT::i8);
24216 return DAG.getNode(X86ISD::BRCOND, DL, N->getVTList(), Chain, Dest, Cond,
24223 static SDValue performVectorCompareAndMaskUnaryOpCombine(SDNode *N,
24224 SelectionDAG &DAG) {
24225 // Take advantage of vector comparisons producing 0 or -1 in each lane to
24226 // optimize away operation when it's from a constant.
24228 // The general transformation is:
24229 // UNARYOP(AND(VECTOR_CMP(x,y), constant)) -->
24230 // AND(VECTOR_CMP(x,y), constant2)
24231 // constant2 = UNARYOP(constant)
24233 // Early exit if this isn't a vector operation, the operand of the
24234 // unary operation isn't a bitwise AND, or if the sizes of the operations
24235 // aren't the same.
24236 EVT VT = N->getValueType(0);
24237 if (!VT.isVector() || N->getOperand(0)->getOpcode() != ISD::AND ||
24238 N->getOperand(0)->getOperand(0)->getOpcode() != ISD::SETCC ||
24239 VT.getSizeInBits() != N->getOperand(0)->getValueType(0).getSizeInBits())
24242 // Now check that the other operand of the AND is a constant. We could
24243 // make the transformation for non-constant splats as well, but it's unclear
24244 // that would be a benefit as it would not eliminate any operations, just
24245 // perform one more step in scalar code before moving to the vector unit.
24246 if (BuildVectorSDNode *BV =
24247 dyn_cast<BuildVectorSDNode>(N->getOperand(0)->getOperand(1))) {
24248 // Bail out if the vector isn't a constant.
24249 if (!BV->isConstant())
24252 // Everything checks out. Build up the new and improved node.
24254 EVT IntVT = BV->getValueType(0);
24255 // Create a new constant of the appropriate type for the transformed
24257 SDValue SourceConst = DAG.getNode(N->getOpcode(), DL, VT, SDValue(BV, 0));
24258 // The AND node needs bitcasts to/from an integer vector type around it.
24259 SDValue MaskConst = DAG.getNode(ISD::BITCAST, DL, IntVT, SourceConst);
24260 SDValue NewAnd = DAG.getNode(ISD::AND, DL, IntVT,
24261 N->getOperand(0)->getOperand(0), MaskConst);
24262 SDValue Res = DAG.getNode(ISD::BITCAST, DL, VT, NewAnd);
24269 static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
24270 const X86TargetLowering *XTLI) {
24271 // First try to optimize away the conversion entirely when it's
24272 // conditionally from a constant. Vectors only.
24273 SDValue Res = performVectorCompareAndMaskUnaryOpCombine(N, DAG);
24274 if (Res != SDValue())
24277 // Now move on to more general possibilities.
24278 SDValue Op0 = N->getOperand(0);
24279 EVT InVT = Op0->getValueType(0);
24281 // SINT_TO_FP(v4i8) -> SINT_TO_FP(SEXT(v4i8 to v4i32))
24282 if (InVT == MVT::v8i8 || InVT == MVT::v4i8) {
24284 MVT DstVT = InVT == MVT::v4i8 ? MVT::v4i32 : MVT::v8i32;
24285 SDValue P = DAG.getNode(ISD::SIGN_EXTEND, dl, DstVT, Op0);
24286 return DAG.getNode(ISD::SINT_TO_FP, dl, N->getValueType(0), P);
24289 // Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have
24290 // a 32-bit target where SSE doesn't support i64->FP operations.
24291 if (Op0.getOpcode() == ISD::LOAD) {
24292 LoadSDNode *Ld = cast<LoadSDNode>(Op0.getNode());
24293 EVT VT = Ld->getValueType(0);
24294 if (!Ld->isVolatile() && !N->getValueType(0).isVector() &&
24295 ISD::isNON_EXTLoad(Op0.getNode()) && Op0.hasOneUse() &&
24296 !XTLI->getSubtarget()->is64Bit() &&
24298 SDValue FILDChain = XTLI->BuildFILD(SDValue(N, 0), Ld->getValueType(0),
24299 Ld->getChain(), Op0, DAG);
24300 DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), FILDChain.getValue(1));
24307 // Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS
24308 static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG,
24309 X86TargetLowering::DAGCombinerInfo &DCI) {
24310 // If the LHS and RHS of the ADC node are zero, then it can't overflow and
24311 // the result is either zero or one (depending on the input carry bit).
24312 // Strength reduce this down to a "set on carry" aka SETCC_CARRY&1.
24313 if (X86::isZeroNode(N->getOperand(0)) &&
24314 X86::isZeroNode(N->getOperand(1)) &&
24315 // We don't have a good way to replace an EFLAGS use, so only do this when
24317 SDValue(N, 1).use_empty()) {
24319 EVT VT = N->getValueType(0);
24320 SDValue CarryOut = DAG.getConstant(0, N->getValueType(1));
24321 SDValue Res1 = DAG.getNode(ISD::AND, DL, VT,
24322 DAG.getNode(X86ISD::SETCC_CARRY, DL, VT,
24323 DAG.getConstant(X86::COND_B,MVT::i8),
24325 DAG.getConstant(1, VT));
24326 return DCI.CombineTo(N, Res1, CarryOut);
24332 // fold (add Y, (sete X, 0)) -> adc 0, Y
24333 // (add Y, (setne X, 0)) -> sbb -1, Y
24334 // (sub (sete X, 0), Y) -> sbb 0, Y
24335 // (sub (setne X, 0), Y) -> adc -1, Y
24336 static SDValue OptimizeConditionalInDecrement(SDNode *N, SelectionDAG &DAG) {
24339 // Look through ZExts.
24340 SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0);
24341 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse())
24344 SDValue SetCC = Ext.getOperand(0);
24345 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse())
24348 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0);
24349 if (CC != X86::COND_E && CC != X86::COND_NE)
24352 SDValue Cmp = SetCC.getOperand(1);
24353 if (Cmp.getOpcode() != X86ISD::CMP || !Cmp.hasOneUse() ||
24354 !X86::isZeroNode(Cmp.getOperand(1)) ||
24355 !Cmp.getOperand(0).getValueType().isInteger())
24358 SDValue CmpOp0 = Cmp.getOperand(0);
24359 SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, CmpOp0,
24360 DAG.getConstant(1, CmpOp0.getValueType()));
24362 SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1);
24363 if (CC == X86::COND_NE)
24364 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB,
24365 DL, OtherVal.getValueType(), OtherVal,
24366 DAG.getConstant(-1ULL, OtherVal.getValueType()), NewCmp);
24367 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC,
24368 DL, OtherVal.getValueType(), OtherVal,
24369 DAG.getConstant(0, OtherVal.getValueType()), NewCmp);
24372 /// PerformADDCombine - Do target-specific dag combines on integer adds.
24373 static SDValue PerformAddCombine(SDNode *N, SelectionDAG &DAG,
24374 const X86Subtarget *Subtarget) {
24375 EVT VT = N->getValueType(0);
24376 SDValue Op0 = N->getOperand(0);
24377 SDValue Op1 = N->getOperand(1);
24379 // Try to synthesize horizontal adds from adds of shuffles.
24380 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
24381 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
24382 isHorizontalBinOp(Op0, Op1, true))
24383 return DAG.getNode(X86ISD::HADD, SDLoc(N), VT, Op0, Op1);
24385 return OptimizeConditionalInDecrement(N, DAG);
24388 static SDValue PerformSubCombine(SDNode *N, SelectionDAG &DAG,
24389 const X86Subtarget *Subtarget) {
24390 SDValue Op0 = N->getOperand(0);
24391 SDValue Op1 = N->getOperand(1);
24393 // X86 can't encode an immediate LHS of a sub. See if we can push the
24394 // negation into a preceding instruction.
24395 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op0)) {
24396 // If the RHS of the sub is a XOR with one use and a constant, invert the
24397 // immediate. Then add one to the LHS of the sub so we can turn
24398 // X-Y -> X+~Y+1, saving one register.
24399 if (Op1->hasOneUse() && Op1.getOpcode() == ISD::XOR &&
24400 isa<ConstantSDNode>(Op1.getOperand(1))) {
24401 APInt XorC = cast<ConstantSDNode>(Op1.getOperand(1))->getAPIntValue();
24402 EVT VT = Op0.getValueType();
24403 SDValue NewXor = DAG.getNode(ISD::XOR, SDLoc(Op1), VT,
24405 DAG.getConstant(~XorC, VT));
24406 return DAG.getNode(ISD::ADD, SDLoc(N), VT, NewXor,
24407 DAG.getConstant(C->getAPIntValue()+1, VT));
24411 // Try to synthesize horizontal adds from adds of shuffles.
24412 EVT VT = N->getValueType(0);
24413 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
24414 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
24415 isHorizontalBinOp(Op0, Op1, true))
24416 return DAG.getNode(X86ISD::HSUB, SDLoc(N), VT, Op0, Op1);
24418 return OptimizeConditionalInDecrement(N, DAG);
24421 /// performVZEXTCombine - Performs build vector combines
24422 static SDValue performVZEXTCombine(SDNode *N, SelectionDAG &DAG,
24423 TargetLowering::DAGCombinerInfo &DCI,
24424 const X86Subtarget *Subtarget) {
24425 // (vzext (bitcast (vzext (x)) -> (vzext x)
24426 SDValue In = N->getOperand(0);
24427 while (In.getOpcode() == ISD::BITCAST)
24428 In = In.getOperand(0);
24430 if (In.getOpcode() != X86ISD::VZEXT)
24433 return DAG.getNode(X86ISD::VZEXT, SDLoc(N), N->getValueType(0),
24437 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
24438 DAGCombinerInfo &DCI) const {
24439 SelectionDAG &DAG = DCI.DAG;
24440 switch (N->getOpcode()) {
24442 case ISD::EXTRACT_VECTOR_ELT:
24443 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, DCI);
24445 case ISD::SELECT: return PerformSELECTCombine(N, DAG, DCI, Subtarget);
24446 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI, Subtarget);
24447 case ISD::ADD: return PerformAddCombine(N, DAG, Subtarget);
24448 case ISD::SUB: return PerformSubCombine(N, DAG, Subtarget);
24449 case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI);
24450 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
24453 case ISD::SRL: return PerformShiftCombine(N, DAG, DCI, Subtarget);
24454 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget);
24455 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget);
24456 case ISD::XOR: return PerformXorCombine(N, DAG, DCI, Subtarget);
24457 case ISD::LOAD: return PerformLOADCombine(N, DAG, DCI, Subtarget);
24458 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
24459 case ISD::SINT_TO_FP: return PerformSINT_TO_FPCombine(N, DAG, this);
24460 case ISD::FADD: return PerformFADDCombine(N, DAG, Subtarget);
24461 case ISD::FSUB: return PerformFSUBCombine(N, DAG, Subtarget);
24463 case X86ISD::FOR: return PerformFORCombine(N, DAG);
24465 case X86ISD::FMAX: return PerformFMinFMaxCombine(N, DAG);
24466 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
24467 case X86ISD::FANDN: return PerformFANDNCombine(N, DAG);
24468 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
24469 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
24470 case ISD::ANY_EXTEND:
24471 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG, DCI, Subtarget);
24472 case ISD::SIGN_EXTEND: return PerformSExtCombine(N, DAG, DCI, Subtarget);
24473 case ISD::SIGN_EXTEND_INREG:
24474 return PerformSIGN_EXTEND_INREGCombine(N, DAG, Subtarget);
24475 case ISD::TRUNCATE: return PerformTruncateCombine(N, DAG,DCI,Subtarget);
24476 case ISD::SETCC: return PerformISDSETCCCombine(N, DAG, Subtarget);
24477 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG, DCI, Subtarget);
24478 case X86ISD::BRCOND: return PerformBrCondCombine(N, DAG, DCI, Subtarget);
24479 case X86ISD::VZEXT: return performVZEXTCombine(N, DAG, DCI, Subtarget);
24480 case X86ISD::SHUFP: // Handle all target specific shuffles
24481 case X86ISD::PALIGNR:
24482 case X86ISD::UNPCKH:
24483 case X86ISD::UNPCKL:
24484 case X86ISD::MOVHLPS:
24485 case X86ISD::MOVLHPS:
24486 case X86ISD::PSHUFB:
24487 case X86ISD::PSHUFD:
24488 case X86ISD::PSHUFHW:
24489 case X86ISD::PSHUFLW:
24490 case X86ISD::MOVSS:
24491 case X86ISD::MOVSD:
24492 case X86ISD::VPERMILPI:
24493 case X86ISD::VPERM2X128:
24494 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget);
24495 case ISD::FMA: return PerformFMACombine(N, DAG, Subtarget);
24496 case ISD::INTRINSIC_WO_CHAIN:
24497 return PerformINTRINSIC_WO_CHAINCombine(N, DAG, Subtarget);
24498 case X86ISD::INSERTPS:
24499 return PerformINSERTPSCombine(N, DAG, Subtarget);
24500 case ISD::BUILD_VECTOR: return PerformBUILD_VECTORCombine(N, DAG, Subtarget);
24506 /// isTypeDesirableForOp - Return true if the target has native support for
24507 /// the specified value type and it is 'desirable' to use the type for the
24508 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
24509 /// instruction encodings are longer and some i16 instructions are slow.
24510 bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const {
24511 if (!isTypeLegal(VT))
24513 if (VT != MVT::i16)
24520 case ISD::SIGN_EXTEND:
24521 case ISD::ZERO_EXTEND:
24522 case ISD::ANY_EXTEND:
24535 /// IsDesirableToPromoteOp - This method query the target whether it is
24536 /// beneficial for dag combiner to promote the specified node. If true, it
24537 /// should return the desired promotion type by reference.
24538 bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
24539 EVT VT = Op.getValueType();
24540 if (VT != MVT::i16)
24543 bool Promote = false;
24544 bool Commute = false;
24545 switch (Op.getOpcode()) {
24548 LoadSDNode *LD = cast<LoadSDNode>(Op);
24549 // If the non-extending load has a single use and it's not live out, then it
24550 // might be folded.
24551 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&&
24552 Op.hasOneUse()*/) {
24553 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
24554 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
24555 // The only case where we'd want to promote LOAD (rather then it being
24556 // promoted as an operand is when it's only use is liveout.
24557 if (UI->getOpcode() != ISD::CopyToReg)
24564 case ISD::SIGN_EXTEND:
24565 case ISD::ZERO_EXTEND:
24566 case ISD::ANY_EXTEND:
24571 SDValue N0 = Op.getOperand(0);
24572 // Look out for (store (shl (load), x)).
24573 if (MayFoldLoad(N0) && MayFoldIntoStore(Op))
24586 SDValue N0 = Op.getOperand(0);
24587 SDValue N1 = Op.getOperand(1);
24588 if (!Commute && MayFoldLoad(N1))
24590 // Avoid disabling potential load folding opportunities.
24591 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op)))
24593 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op)))
24603 //===----------------------------------------------------------------------===//
24604 // X86 Inline Assembly Support
24605 //===----------------------------------------------------------------------===//
24608 // Helper to match a string separated by whitespace.
24609 bool matchAsmImpl(StringRef s, ArrayRef<const StringRef *> args) {
24610 s = s.substr(s.find_first_not_of(" \t")); // Skip leading whitespace.
24612 for (unsigned i = 0, e = args.size(); i != e; ++i) {
24613 StringRef piece(*args[i]);
24614 if (!s.startswith(piece)) // Check if the piece matches.
24617 s = s.substr(piece.size());
24618 StringRef::size_type pos = s.find_first_not_of(" \t");
24619 if (pos == 0) // We matched a prefix.
24627 const VariadicFunction1<bool, StringRef, StringRef, matchAsmImpl> matchAsm={};
24630 static bool clobbersFlagRegisters(const SmallVector<StringRef, 4> &AsmPieces) {
24632 if (AsmPieces.size() == 3 || AsmPieces.size() == 4) {
24633 if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{cc}") &&
24634 std::count(AsmPieces.begin(), AsmPieces.end(), "~{flags}") &&
24635 std::count(AsmPieces.begin(), AsmPieces.end(), "~{fpsr}")) {
24637 if (AsmPieces.size() == 3)
24639 else if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{dirflag}"))
24646 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
24647 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
24649 std::string AsmStr = IA->getAsmString();
24651 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
24652 if (!Ty || Ty->getBitWidth() % 16 != 0)
24655 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
24656 SmallVector<StringRef, 4> AsmPieces;
24657 SplitString(AsmStr, AsmPieces, ";\n");
24659 switch (AsmPieces.size()) {
24660 default: return false;
24662 // FIXME: this should verify that we are targeting a 486 or better. If not,
24663 // we will turn this bswap into something that will be lowered to logical
24664 // ops instead of emitting the bswap asm. For now, we don't support 486 or
24665 // lower so don't worry about this.
24667 if (matchAsm(AsmPieces[0], "bswap", "$0") ||
24668 matchAsm(AsmPieces[0], "bswapl", "$0") ||
24669 matchAsm(AsmPieces[0], "bswapq", "$0") ||
24670 matchAsm(AsmPieces[0], "bswap", "${0:q}") ||
24671 matchAsm(AsmPieces[0], "bswapl", "${0:q}") ||
24672 matchAsm(AsmPieces[0], "bswapq", "${0:q}")) {
24673 // No need to check constraints, nothing other than the equivalent of
24674 // "=r,0" would be valid here.
24675 return IntrinsicLowering::LowerToByteSwap(CI);
24678 // rorw $$8, ${0:w} --> llvm.bswap.i16
24679 if (CI->getType()->isIntegerTy(16) &&
24680 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
24681 (matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") ||
24682 matchAsm(AsmPieces[0], "rolw", "$$8,", "${0:w}"))) {
24684 const std::string &ConstraintsStr = IA->getConstraintString();
24685 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
24686 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
24687 if (clobbersFlagRegisters(AsmPieces))
24688 return IntrinsicLowering::LowerToByteSwap(CI);
24692 if (CI->getType()->isIntegerTy(32) &&
24693 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
24694 matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") &&
24695 matchAsm(AsmPieces[1], "rorl", "$$16,", "$0") &&
24696 matchAsm(AsmPieces[2], "rorw", "$$8,", "${0:w}")) {
24698 const std::string &ConstraintsStr = IA->getConstraintString();
24699 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
24700 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
24701 if (clobbersFlagRegisters(AsmPieces))
24702 return IntrinsicLowering::LowerToByteSwap(CI);
24705 if (CI->getType()->isIntegerTy(64)) {
24706 InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints();
24707 if (Constraints.size() >= 2 &&
24708 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
24709 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
24710 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
24711 if (matchAsm(AsmPieces[0], "bswap", "%eax") &&
24712 matchAsm(AsmPieces[1], "bswap", "%edx") &&
24713 matchAsm(AsmPieces[2], "xchgl", "%eax,", "%edx"))
24714 return IntrinsicLowering::LowerToByteSwap(CI);
24722 /// getConstraintType - Given a constraint letter, return the type of
24723 /// constraint it is for this target.
24724 X86TargetLowering::ConstraintType
24725 X86TargetLowering::getConstraintType(const std::string &Constraint) const {
24726 if (Constraint.size() == 1) {
24727 switch (Constraint[0]) {
24738 return C_RegisterClass;
24762 return TargetLowering::getConstraintType(Constraint);
24765 /// Examine constraint type and operand type and determine a weight value.
24766 /// This object must already have been set up with the operand type
24767 /// and the current alternative constraint selected.
24768 TargetLowering::ConstraintWeight
24769 X86TargetLowering::getSingleConstraintMatchWeight(
24770 AsmOperandInfo &info, const char *constraint) const {
24771 ConstraintWeight weight = CW_Invalid;
24772 Value *CallOperandVal = info.CallOperandVal;
24773 // If we don't have a value, we can't do a match,
24774 // but allow it at the lowest weight.
24775 if (!CallOperandVal)
24777 Type *type = CallOperandVal->getType();
24778 // Look at the constraint type.
24779 switch (*constraint) {
24781 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
24792 if (CallOperandVal->getType()->isIntegerTy())
24793 weight = CW_SpecificReg;
24798 if (type->isFloatingPointTy())
24799 weight = CW_SpecificReg;
24802 if (type->isX86_MMXTy() && Subtarget->hasMMX())
24803 weight = CW_SpecificReg;
24807 if (((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasSSE1()) ||
24808 ((type->getPrimitiveSizeInBits() == 256) && Subtarget->hasFp256()))
24809 weight = CW_Register;
24812 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) {
24813 if (C->getZExtValue() <= 31)
24814 weight = CW_Constant;
24818 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
24819 if (C->getZExtValue() <= 63)
24820 weight = CW_Constant;
24824 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
24825 if ((C->getSExtValue() >= -0x80) && (C->getSExtValue() <= 0x7f))
24826 weight = CW_Constant;
24830 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
24831 if ((C->getZExtValue() == 0xff) || (C->getZExtValue() == 0xffff))
24832 weight = CW_Constant;
24836 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
24837 if (C->getZExtValue() <= 3)
24838 weight = CW_Constant;
24842 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
24843 if (C->getZExtValue() <= 0xff)
24844 weight = CW_Constant;
24849 if (dyn_cast<ConstantFP>(CallOperandVal)) {
24850 weight = CW_Constant;
24854 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
24855 if ((C->getSExtValue() >= -0x80000000LL) &&
24856 (C->getSExtValue() <= 0x7fffffffLL))
24857 weight = CW_Constant;
24861 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
24862 if (C->getZExtValue() <= 0xffffffff)
24863 weight = CW_Constant;
24870 /// LowerXConstraint - try to replace an X constraint, which matches anything,
24871 /// with another that has more specific requirements based on the type of the
24872 /// corresponding operand.
24873 const char *X86TargetLowering::
24874 LowerXConstraint(EVT ConstraintVT) const {
24875 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
24876 // 'f' like normal targets.
24877 if (ConstraintVT.isFloatingPoint()) {
24878 if (Subtarget->hasSSE2())
24880 if (Subtarget->hasSSE1())
24884 return TargetLowering::LowerXConstraint(ConstraintVT);
24887 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
24888 /// vector. If it is invalid, don't add anything to Ops.
24889 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
24890 std::string &Constraint,
24891 std::vector<SDValue>&Ops,
24892 SelectionDAG &DAG) const {
24895 // Only support length 1 constraints for now.
24896 if (Constraint.length() > 1) return;
24898 char ConstraintLetter = Constraint[0];
24899 switch (ConstraintLetter) {
24902 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
24903 if (C->getZExtValue() <= 31) {
24904 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
24910 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
24911 if (C->getZExtValue() <= 63) {
24912 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
24918 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
24919 if (isInt<8>(C->getSExtValue())) {
24920 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
24926 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
24927 if (C->getZExtValue() <= 255) {
24928 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
24934 // 32-bit signed value
24935 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
24936 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
24937 C->getSExtValue())) {
24938 // Widen to 64 bits here to get it sign extended.
24939 Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64);
24942 // FIXME gcc accepts some relocatable values here too, but only in certain
24943 // memory models; it's complicated.
24948 // 32-bit unsigned value
24949 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
24950 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
24951 C->getZExtValue())) {
24952 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
24956 // FIXME gcc accepts some relocatable values here too, but only in certain
24957 // memory models; it's complicated.
24961 // Literal immediates are always ok.
24962 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
24963 // Widen to 64 bits here to get it sign extended.
24964 Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64);
24968 // In any sort of PIC mode addresses need to be computed at runtime by
24969 // adding in a register or some sort of table lookup. These can't
24970 // be used as immediates.
24971 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC())
24974 // If we are in non-pic codegen mode, we allow the address of a global (with
24975 // an optional displacement) to be used with 'i'.
24976 GlobalAddressSDNode *GA = nullptr;
24977 int64_t Offset = 0;
24979 // Match either (GA), (GA+C), (GA+C1+C2), etc.
24981 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
24982 Offset += GA->getOffset();
24984 } else if (Op.getOpcode() == ISD::ADD) {
24985 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
24986 Offset += C->getZExtValue();
24987 Op = Op.getOperand(0);
24990 } else if (Op.getOpcode() == ISD::SUB) {
24991 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
24992 Offset += -C->getZExtValue();
24993 Op = Op.getOperand(0);
24998 // Otherwise, this isn't something we can handle, reject it.
25002 const GlobalValue *GV = GA->getGlobal();
25003 // If we require an extra load to get this address, as in PIC mode, we
25004 // can't accept it.
25005 if (isGlobalStubReference(
25006 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget())))
25009 Result = DAG.getTargetGlobalAddress(GV, SDLoc(Op),
25010 GA->getValueType(0), Offset);
25015 if (Result.getNode()) {
25016 Ops.push_back(Result);
25019 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
25022 std::pair<unsigned, const TargetRegisterClass*>
25023 X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
25025 // First, see if this is a constraint that directly corresponds to an LLVM
25027 if (Constraint.size() == 1) {
25028 // GCC Constraint Letters
25029 switch (Constraint[0]) {
25031 // TODO: Slight differences here in allocation order and leaving
25032 // RIP in the class. Do they matter any more here than they do
25033 // in the normal allocation?
25034 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
25035 if (Subtarget->is64Bit()) {
25036 if (VT == MVT::i32 || VT == MVT::f32)
25037 return std::make_pair(0U, &X86::GR32RegClass);
25038 if (VT == MVT::i16)
25039 return std::make_pair(0U, &X86::GR16RegClass);
25040 if (VT == MVT::i8 || VT == MVT::i1)
25041 return std::make_pair(0U, &X86::GR8RegClass);
25042 if (VT == MVT::i64 || VT == MVT::f64)
25043 return std::make_pair(0U, &X86::GR64RegClass);
25046 // 32-bit fallthrough
25047 case 'Q': // Q_REGS
25048 if (VT == MVT::i32 || VT == MVT::f32)
25049 return std::make_pair(0U, &X86::GR32_ABCDRegClass);
25050 if (VT == MVT::i16)
25051 return std::make_pair(0U, &X86::GR16_ABCDRegClass);
25052 if (VT == MVT::i8 || VT == MVT::i1)
25053 return std::make_pair(0U, &X86::GR8_ABCD_LRegClass);
25054 if (VT == MVT::i64)
25055 return std::make_pair(0U, &X86::GR64_ABCDRegClass);
25057 case 'r': // GENERAL_REGS
25058 case 'l': // INDEX_REGS
25059 if (VT == MVT::i8 || VT == MVT::i1)
25060 return std::make_pair(0U, &X86::GR8RegClass);
25061 if (VT == MVT::i16)
25062 return std::make_pair(0U, &X86::GR16RegClass);
25063 if (VT == MVT::i32 || VT == MVT::f32 || !Subtarget->is64Bit())
25064 return std::make_pair(0U, &X86::GR32RegClass);
25065 return std::make_pair(0U, &X86::GR64RegClass);
25066 case 'R': // LEGACY_REGS
25067 if (VT == MVT::i8 || VT == MVT::i1)
25068 return std::make_pair(0U, &X86::GR8_NOREXRegClass);
25069 if (VT == MVT::i16)
25070 return std::make_pair(0U, &X86::GR16_NOREXRegClass);
25071 if (VT == MVT::i32 || !Subtarget->is64Bit())
25072 return std::make_pair(0U, &X86::GR32_NOREXRegClass);
25073 return std::make_pair(0U, &X86::GR64_NOREXRegClass);
25074 case 'f': // FP Stack registers.
25075 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
25076 // value to the correct fpstack register class.
25077 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
25078 return std::make_pair(0U, &X86::RFP32RegClass);
25079 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
25080 return std::make_pair(0U, &X86::RFP64RegClass);
25081 return std::make_pair(0U, &X86::RFP80RegClass);
25082 case 'y': // MMX_REGS if MMX allowed.
25083 if (!Subtarget->hasMMX()) break;
25084 return std::make_pair(0U, &X86::VR64RegClass);
25085 case 'Y': // SSE_REGS if SSE2 allowed
25086 if (!Subtarget->hasSSE2()) break;
25088 case 'x': // SSE_REGS if SSE1 allowed or AVX_REGS if AVX allowed
25089 if (!Subtarget->hasSSE1()) break;
25091 switch (VT.SimpleTy) {
25093 // Scalar SSE types.
25096 return std::make_pair(0U, &X86::FR32RegClass);
25099 return std::make_pair(0U, &X86::FR64RegClass);
25107 return std::make_pair(0U, &X86::VR128RegClass);
25115 return std::make_pair(0U, &X86::VR256RegClass);
25120 return std::make_pair(0U, &X86::VR512RegClass);
25126 // Use the default implementation in TargetLowering to convert the register
25127 // constraint into a member of a register class.
25128 std::pair<unsigned, const TargetRegisterClass*> Res;
25129 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
25131 // Not found as a standard register?
25133 // Map st(0) -> st(7) -> ST0
25134 if (Constraint.size() == 7 && Constraint[0] == '{' &&
25135 tolower(Constraint[1]) == 's' &&
25136 tolower(Constraint[2]) == 't' &&
25137 Constraint[3] == '(' &&
25138 (Constraint[4] >= '0' && Constraint[4] <= '7') &&
25139 Constraint[5] == ')' &&
25140 Constraint[6] == '}') {
25142 Res.first = X86::FP0+Constraint[4]-'0';
25143 Res.second = &X86::RFP80RegClass;
25147 // GCC allows "st(0)" to be called just plain "st".
25148 if (StringRef("{st}").equals_lower(Constraint)) {
25149 Res.first = X86::FP0;
25150 Res.second = &X86::RFP80RegClass;
25155 if (StringRef("{flags}").equals_lower(Constraint)) {
25156 Res.first = X86::EFLAGS;
25157 Res.second = &X86::CCRRegClass;
25161 // 'A' means EAX + EDX.
25162 if (Constraint == "A") {
25163 Res.first = X86::EAX;
25164 Res.second = &X86::GR32_ADRegClass;
25170 // Otherwise, check to see if this is a register class of the wrong value
25171 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
25172 // turn into {ax},{dx}.
25173 if (Res.second->hasType(VT))
25174 return Res; // Correct type already, nothing to do.
25176 // All of the single-register GCC register classes map their values onto
25177 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
25178 // really want an 8-bit or 32-bit register, map to the appropriate register
25179 // class and return the appropriate register.
25180 if (Res.second == &X86::GR16RegClass) {
25181 if (VT == MVT::i8 || VT == MVT::i1) {
25182 unsigned DestReg = 0;
25183 switch (Res.first) {
25185 case X86::AX: DestReg = X86::AL; break;
25186 case X86::DX: DestReg = X86::DL; break;
25187 case X86::CX: DestReg = X86::CL; break;
25188 case X86::BX: DestReg = X86::BL; break;
25191 Res.first = DestReg;
25192 Res.second = &X86::GR8RegClass;
25194 } else if (VT == MVT::i32 || VT == MVT::f32) {
25195 unsigned DestReg = 0;
25196 switch (Res.first) {
25198 case X86::AX: DestReg = X86::EAX; break;
25199 case X86::DX: DestReg = X86::EDX; break;
25200 case X86::CX: DestReg = X86::ECX; break;
25201 case X86::BX: DestReg = X86::EBX; break;
25202 case X86::SI: DestReg = X86::ESI; break;
25203 case X86::DI: DestReg = X86::EDI; break;
25204 case X86::BP: DestReg = X86::EBP; break;
25205 case X86::SP: DestReg = X86::ESP; break;
25208 Res.first = DestReg;
25209 Res.second = &X86::GR32RegClass;
25211 } else if (VT == MVT::i64 || VT == MVT::f64) {
25212 unsigned DestReg = 0;
25213 switch (Res.first) {
25215 case X86::AX: DestReg = X86::RAX; break;
25216 case X86::DX: DestReg = X86::RDX; break;
25217 case X86::CX: DestReg = X86::RCX; break;
25218 case X86::BX: DestReg = X86::RBX; break;
25219 case X86::SI: DestReg = X86::RSI; break;
25220 case X86::DI: DestReg = X86::RDI; break;
25221 case X86::BP: DestReg = X86::RBP; break;
25222 case X86::SP: DestReg = X86::RSP; break;
25225 Res.first = DestReg;
25226 Res.second = &X86::GR64RegClass;
25229 } else if (Res.second == &X86::FR32RegClass ||
25230 Res.second == &X86::FR64RegClass ||
25231 Res.second == &X86::VR128RegClass ||
25232 Res.second == &X86::VR256RegClass ||
25233 Res.second == &X86::FR32XRegClass ||
25234 Res.second == &X86::FR64XRegClass ||
25235 Res.second == &X86::VR128XRegClass ||
25236 Res.second == &X86::VR256XRegClass ||
25237 Res.second == &X86::VR512RegClass) {
25238 // Handle references to XMM physical registers that got mapped into the
25239 // wrong class. This can happen with constraints like {xmm0} where the
25240 // target independent register mapper will just pick the first match it can
25241 // find, ignoring the required type.
25243 if (VT == MVT::f32 || VT == MVT::i32)
25244 Res.second = &X86::FR32RegClass;
25245 else if (VT == MVT::f64 || VT == MVT::i64)
25246 Res.second = &X86::FR64RegClass;
25247 else if (X86::VR128RegClass.hasType(VT))
25248 Res.second = &X86::VR128RegClass;
25249 else if (X86::VR256RegClass.hasType(VT))
25250 Res.second = &X86::VR256RegClass;
25251 else if (X86::VR512RegClass.hasType(VT))
25252 Res.second = &X86::VR512RegClass;
25258 int X86TargetLowering::getScalingFactorCost(const AddrMode &AM,
25260 // Scaling factors are not free at all.
25261 // An indexed folded instruction, i.e., inst (reg1, reg2, scale),
25262 // will take 2 allocations in the out of order engine instead of 1
25263 // for plain addressing mode, i.e. inst (reg1).
25265 // vaddps (%rsi,%drx), %ymm0, %ymm1
25266 // Requires two allocations (one for the load, one for the computation)
25268 // vaddps (%rsi), %ymm0, %ymm1
25269 // Requires just 1 allocation, i.e., freeing allocations for other operations
25270 // and having less micro operations to execute.
25272 // For some X86 architectures, this is even worse because for instance for
25273 // stores, the complex addressing mode forces the instruction to use the
25274 // "load" ports instead of the dedicated "store" port.
25275 // E.g., on Haswell:
25276 // vmovaps %ymm1, (%r8, %rdi) can use port 2 or 3.
25277 // vmovaps %ymm1, (%r8) can use port 2, 3, or 7.
25278 if (isLegalAddressingMode(AM, Ty))
25279 // Scale represents reg2 * scale, thus account for 1
25280 // as soon as we use a second register.
25281 return AM.Scale != 0;
25285 bool X86TargetLowering::isTargetFTOL() const {
25286 return Subtarget->isTargetKnownWindowsMSVC() && !Subtarget->is64Bit();