1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #include "X86ISelLowering.h"
16 #include "Utils/X86ShuffleDecode.h"
17 #include "X86CallingConv.h"
18 #include "X86FrameLowering.h"
19 #include "X86InstrBuilder.h"
20 #include "X86MachineFunctionInfo.h"
21 #include "X86TargetMachine.h"
22 #include "X86TargetObjectFile.h"
23 #include "llvm/ADT/SmallBitVector.h"
24 #include "llvm/ADT/SmallSet.h"
25 #include "llvm/ADT/Statistic.h"
26 #include "llvm/ADT/StringExtras.h"
27 #include "llvm/ADT/StringSwitch.h"
28 #include "llvm/CodeGen/IntrinsicLowering.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineFunction.h"
31 #include "llvm/CodeGen/MachineInstrBuilder.h"
32 #include "llvm/CodeGen/MachineJumpTableInfo.h"
33 #include "llvm/CodeGen/MachineModuleInfo.h"
34 #include "llvm/CodeGen/MachineRegisterInfo.h"
35 #include "llvm/CodeGen/WinEHFuncInfo.h"
36 #include "llvm/IR/CallSite.h"
37 #include "llvm/IR/CallingConv.h"
38 #include "llvm/IR/Constants.h"
39 #include "llvm/IR/DerivedTypes.h"
40 #include "llvm/IR/Function.h"
41 #include "llvm/IR/GlobalAlias.h"
42 #include "llvm/IR/GlobalVariable.h"
43 #include "llvm/IR/Instructions.h"
44 #include "llvm/IR/Intrinsics.h"
45 #include "llvm/MC/MCAsmInfo.h"
46 #include "llvm/MC/MCContext.h"
47 #include "llvm/MC/MCExpr.h"
48 #include "llvm/MC/MCSymbol.h"
49 #include "llvm/Support/CommandLine.h"
50 #include "llvm/Support/Debug.h"
51 #include "llvm/Support/ErrorHandling.h"
52 #include "llvm/Support/MathExtras.h"
53 #include "llvm/Target/TargetOptions.h"
54 #include "X86IntrinsicsInfo.h"
60 #define DEBUG_TYPE "x86-isel"
62 STATISTIC(NumTailCalls, "Number of tail calls");
64 static cl::opt<bool> ExperimentalVectorWideningLegalization(
65 "x86-experimental-vector-widening-legalization", cl::init(false),
66 cl::desc("Enable an experimental vector type legalization through widening "
67 "rather than promotion."),
70 X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
71 const X86Subtarget &STI)
72 : TargetLowering(TM), Subtarget(&STI) {
73 X86ScalarSSEf64 = Subtarget->hasSSE2();
74 X86ScalarSSEf32 = Subtarget->hasSSE1();
75 MVT PtrVT = MVT::getIntegerVT(8 * TM.getPointerSize());
77 // Set up the TargetLowering object.
79 // X86 is weird. It always uses i8 for shift amounts and setcc results.
80 setBooleanContents(ZeroOrOneBooleanContent);
81 // X86-SSE is even stranger. It uses -1 or 0 for vector masks.
82 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
84 // For 64-bit, since we have so many registers, use the ILP scheduler.
85 // For 32-bit, use the register pressure specific scheduling.
86 // For Atom, always use ILP scheduling.
87 if (Subtarget->isAtom())
88 setSchedulingPreference(Sched::ILP);
89 else if (Subtarget->is64Bit())
90 setSchedulingPreference(Sched::ILP);
92 setSchedulingPreference(Sched::RegPressure);
93 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
94 setStackPointerRegisterToSaveRestore(RegInfo->getStackRegister());
96 // Bypass expensive divides on Atom when compiling with O2.
97 if (TM.getOptLevel() >= CodeGenOpt::Default) {
98 if (Subtarget->hasSlowDivide32())
99 addBypassSlowDiv(32, 8);
100 if (Subtarget->hasSlowDivide64() && Subtarget->is64Bit())
101 addBypassSlowDiv(64, 16);
104 if (Subtarget->isTargetKnownWindowsMSVC()) {
105 // Setup Windows compiler runtime calls.
106 setLibcallName(RTLIB::SDIV_I64, "_alldiv");
107 setLibcallName(RTLIB::UDIV_I64, "_aulldiv");
108 setLibcallName(RTLIB::SREM_I64, "_allrem");
109 setLibcallName(RTLIB::UREM_I64, "_aullrem");
110 setLibcallName(RTLIB::MUL_I64, "_allmul");
111 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall);
112 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall);
113 setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::X86_StdCall);
114 setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::X86_StdCall);
115 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::X86_StdCall);
118 if (Subtarget->isTargetDarwin()) {
119 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
120 setUseUnderscoreSetJmp(false);
121 setUseUnderscoreLongJmp(false);
122 } else if (Subtarget->isTargetWindowsGNU()) {
123 // MS runtime is weird: it exports _setjmp, but longjmp!
124 setUseUnderscoreSetJmp(true);
125 setUseUnderscoreLongJmp(false);
127 setUseUnderscoreSetJmp(true);
128 setUseUnderscoreLongJmp(true);
131 // Set up the register classes.
132 addRegisterClass(MVT::i8, &X86::GR8RegClass);
133 addRegisterClass(MVT::i16, &X86::GR16RegClass);
134 addRegisterClass(MVT::i32, &X86::GR32RegClass);
135 if (Subtarget->is64Bit())
136 addRegisterClass(MVT::i64, &X86::GR64RegClass);
138 for (MVT VT : MVT::integer_valuetypes())
139 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
141 // We don't accept any truncstore of integer registers.
142 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
143 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
144 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
145 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
146 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
147 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
149 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
151 // SETOEQ and SETUNE require checking two conditions.
152 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
153 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
154 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
155 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
156 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
157 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
159 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
161 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
162 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
163 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
165 if (Subtarget->is64Bit()) {
166 if (!Subtarget->useSoftFloat() && Subtarget->hasAVX512())
167 // f32/f64 are legal, f80 is custom.
168 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
170 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
171 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
172 } else if (!Subtarget->useSoftFloat()) {
173 // We have an algorithm for SSE2->double, and we turn this into a
174 // 64-bit FILD followed by conditional FADD for other targets.
175 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
176 // We have an algorithm for SSE2, and we turn this into a 64-bit
177 // FILD or VCVTUSI2SS/SD for other targets.
178 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
181 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
183 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
184 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
186 if (!Subtarget->useSoftFloat()) {
187 // SSE has no i16 to fp conversion, only i32
188 if (X86ScalarSSEf32) {
189 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
190 // f32 and f64 cases are Legal, f80 case is not
191 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
193 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
194 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
197 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
198 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
201 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
202 // are Legal, f80 is custom lowered.
203 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
204 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
206 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
208 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
209 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
211 if (X86ScalarSSEf32) {
212 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
213 // f32 and f64 cases are Legal, f80 case is not
214 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
216 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
217 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
220 // Handle FP_TO_UINT by promoting the destination to a larger signed
222 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
223 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
224 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
226 if (Subtarget->is64Bit()) {
227 if (!Subtarget->useSoftFloat() && Subtarget->hasAVX512()) {
228 // FP_TO_UINT-i32/i64 is legal for f32/f64, but custom for f80.
229 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
230 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Custom);
232 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
233 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
235 } else if (!Subtarget->useSoftFloat()) {
236 // Since AVX is a superset of SSE3, only check for SSE here.
237 if (Subtarget->hasSSE1() && !Subtarget->hasSSE3())
238 // Expand FP_TO_UINT into a select.
239 // FIXME: We would like to use a Custom expander here eventually to do
240 // the optimal thing for SSE vs. the default expansion in the legalizer.
241 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
243 // With AVX512 we can use vcvts[ds]2usi for f32/f64->i32, f80 is custom.
244 // With SSE3 we can use fisttpll to convert to a signed i64; without
245 // SSE, we're stuck with a fistpll.
246 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
248 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Custom);
251 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
252 if (!X86ScalarSSEf64) {
253 setOperationAction(ISD::BITCAST , MVT::f32 , Expand);
254 setOperationAction(ISD::BITCAST , MVT::i32 , Expand);
255 if (Subtarget->is64Bit()) {
256 setOperationAction(ISD::BITCAST , MVT::f64 , Expand);
257 // Without SSE, i64->f64 goes through memory.
258 setOperationAction(ISD::BITCAST , MVT::i64 , Expand);
262 // Scalar integer divide and remainder are lowered to use operations that
263 // produce two results, to match the available instructions. This exposes
264 // the two-result form to trivial CSE, which is able to combine x/y and x%y
265 // into a single instruction.
267 // Scalar integer multiply-high is also lowered to use two-result
268 // operations, to match the available instructions. However, plain multiply
269 // (low) operations are left as Legal, as there are single-result
270 // instructions for this in x86. Using the two-result multiply instructions
271 // when both high and low results are needed must be arranged by dagcombine.
272 for (auto VT : { MVT::i8, MVT::i16, MVT::i32, MVT::i64 }) {
273 setOperationAction(ISD::MULHS, VT, Expand);
274 setOperationAction(ISD::MULHU, VT, Expand);
275 setOperationAction(ISD::SDIV, VT, Expand);
276 setOperationAction(ISD::UDIV, VT, Expand);
277 setOperationAction(ISD::SREM, VT, Expand);
278 setOperationAction(ISD::UREM, VT, Expand);
280 // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences.
281 setOperationAction(ISD::ADDC, VT, Custom);
282 setOperationAction(ISD::ADDE, VT, Custom);
283 setOperationAction(ISD::SUBC, VT, Custom);
284 setOperationAction(ISD::SUBE, VT, Custom);
287 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
288 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
289 setOperationAction(ISD::BR_CC , MVT::f32, Expand);
290 setOperationAction(ISD::BR_CC , MVT::f64, Expand);
291 setOperationAction(ISD::BR_CC , MVT::f80, Expand);
292 setOperationAction(ISD::BR_CC , MVT::i8, Expand);
293 setOperationAction(ISD::BR_CC , MVT::i16, Expand);
294 setOperationAction(ISD::BR_CC , MVT::i32, Expand);
295 setOperationAction(ISD::BR_CC , MVT::i64, Expand);
296 setOperationAction(ISD::SELECT_CC , MVT::f32, Expand);
297 setOperationAction(ISD::SELECT_CC , MVT::f64, Expand);
298 setOperationAction(ISD::SELECT_CC , MVT::f80, Expand);
299 setOperationAction(ISD::SELECT_CC , MVT::i8, Expand);
300 setOperationAction(ISD::SELECT_CC , MVT::i16, Expand);
301 setOperationAction(ISD::SELECT_CC , MVT::i32, Expand);
302 setOperationAction(ISD::SELECT_CC , MVT::i64, Expand);
303 if (Subtarget->is64Bit())
304 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
305 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
306 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
307 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
308 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
310 if (Subtarget->is32Bit() && Subtarget->isTargetKnownWindowsMSVC()) {
311 // On 32 bit MSVC, `fmodf(f32)` is not defined - only `fmod(f64)`
312 // is. We should promote the value to 64-bits to solve this.
313 // This is what the CRT headers do - `fmodf` is an inline header
314 // function casting to f64 and calling `fmod`.
315 setOperationAction(ISD::FREM , MVT::f32 , Promote);
317 setOperationAction(ISD::FREM , MVT::f32 , Expand);
320 setOperationAction(ISD::FREM , MVT::f64 , Expand);
321 setOperationAction(ISD::FREM , MVT::f80 , Expand);
322 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
324 // Promote the i8 variants and force them on up to i32 which has a shorter
326 setOperationAction(ISD::CTTZ , MVT::i8 , Promote);
327 AddPromotedToType (ISD::CTTZ , MVT::i8 , MVT::i32);
328 setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i8 , Promote);
329 AddPromotedToType (ISD::CTTZ_ZERO_UNDEF , MVT::i8 , MVT::i32);
330 if (Subtarget->hasBMI()) {
331 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16 , Expand);
332 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32 , Expand);
333 if (Subtarget->is64Bit())
334 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
336 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
337 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
338 if (Subtarget->is64Bit())
339 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
342 if (Subtarget->hasLZCNT()) {
343 // When promoting the i8 variants, force them to i32 for a shorter
345 setOperationAction(ISD::CTLZ , MVT::i8 , Promote);
346 AddPromotedToType (ISD::CTLZ , MVT::i8 , MVT::i32);
347 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Promote);
348 AddPromotedToType (ISD::CTLZ_ZERO_UNDEF, MVT::i8 , MVT::i32);
349 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Expand);
350 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Expand);
351 if (Subtarget->is64Bit())
352 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
354 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
355 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
356 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
357 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Custom);
358 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Custom);
359 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Custom);
360 if (Subtarget->is64Bit()) {
361 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
362 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom);
366 // Special handling for half-precision floating point conversions.
367 // If we don't have F16C support, then lower half float conversions
368 // into library calls.
369 if (Subtarget->useSoftFloat() || !Subtarget->hasF16C()) {
370 setOperationAction(ISD::FP16_TO_FP, MVT::f32, Expand);
371 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand);
374 // There's never any support for operations beyond MVT::f32.
375 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand);
376 setOperationAction(ISD::FP16_TO_FP, MVT::f80, Expand);
377 setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand);
378 setOperationAction(ISD::FP_TO_FP16, MVT::f80, Expand);
380 setLoadExtAction(ISD::EXTLOAD, MVT::f32, MVT::f16, Expand);
381 setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f16, Expand);
382 setLoadExtAction(ISD::EXTLOAD, MVT::f80, MVT::f16, Expand);
383 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
384 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
385 setTruncStoreAction(MVT::f80, MVT::f16, Expand);
387 if (Subtarget->hasPOPCNT()) {
388 setOperationAction(ISD::CTPOP , MVT::i8 , Promote);
390 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
391 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
392 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
393 if (Subtarget->is64Bit())
394 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
397 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
399 if (!Subtarget->hasMOVBE())
400 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
402 // These should be promoted to a larger select which is supported.
403 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
404 // X86 wants to expand cmov itself.
405 setOperationAction(ISD::SELECT , MVT::i8 , Custom);
406 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
407 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
408 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
409 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
410 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
411 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
412 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
413 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
414 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
415 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
416 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
417 if (Subtarget->is64Bit()) {
418 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
419 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
421 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
422 // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support
423 // SjLj exception handling but a light-weight setjmp/longjmp replacement to
424 // support continuation, user-level threading, and etc.. As a result, no
425 // other SjLj exception interfaces are implemented and please don't build
426 // your own exception handling based on them.
427 // LLVM/Clang supports zero-cost DWARF exception handling.
428 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
429 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
432 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
433 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
434 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
435 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
436 if (Subtarget->is64Bit())
437 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
438 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
439 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom);
440 if (Subtarget->is64Bit()) {
441 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
442 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
443 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
444 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
445 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom);
447 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
448 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
449 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
450 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
451 if (Subtarget->is64Bit()) {
452 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
453 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
454 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
457 if (Subtarget->hasSSE1())
458 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
460 setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom);
462 // Expand certain atomics
463 for (auto VT : { MVT::i8, MVT::i16, MVT::i32, MVT::i64 }) {
464 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, VT, Custom);
465 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom);
466 setOperationAction(ISD::ATOMIC_STORE, VT, Custom);
469 if (Subtarget->hasCmpxchg16b()) {
470 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, MVT::i128, Custom);
473 // FIXME - use subtarget debug flags
474 if (!Subtarget->isTargetDarwin() && !Subtarget->isTargetELF() &&
475 !Subtarget->isTargetCygMing() && !Subtarget->isTargetWin64()) {
476 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
479 if (Subtarget->isTarget64BitLP64()) {
480 setExceptionPointerRegister(X86::RAX);
481 setExceptionSelectorRegister(X86::RDX);
483 setExceptionPointerRegister(X86::EAX);
484 setExceptionSelectorRegister(X86::EDX);
486 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
487 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
489 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
490 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
492 setOperationAction(ISD::TRAP, MVT::Other, Legal);
493 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Legal);
495 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
496 setOperationAction(ISD::VASTART , MVT::Other, Custom);
497 setOperationAction(ISD::VAEND , MVT::Other, Expand);
498 if (Subtarget->is64Bit()) {
499 setOperationAction(ISD::VAARG , MVT::Other, Custom);
500 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
502 // TargetInfo::CharPtrBuiltinVaList
503 setOperationAction(ISD::VAARG , MVT::Other, Expand);
504 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
507 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
508 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
510 setOperationAction(ISD::DYNAMIC_STACKALLOC, PtrVT, Custom);
512 // GC_TRANSITION_START and GC_TRANSITION_END need custom lowering.
513 setOperationAction(ISD::GC_TRANSITION_START, MVT::Other, Custom);
514 setOperationAction(ISD::GC_TRANSITION_END, MVT::Other, Custom);
516 if (!Subtarget->useSoftFloat() && X86ScalarSSEf64) {
517 // f32 and f64 use SSE.
518 // Set up the FP register classes.
519 addRegisterClass(MVT::f32, &X86::FR32RegClass);
520 addRegisterClass(MVT::f64, &X86::FR64RegClass);
522 // Use ANDPD to simulate FABS.
523 setOperationAction(ISD::FABS , MVT::f64, Custom);
524 setOperationAction(ISD::FABS , MVT::f32, Custom);
526 // Use XORP to simulate FNEG.
527 setOperationAction(ISD::FNEG , MVT::f64, Custom);
528 setOperationAction(ISD::FNEG , MVT::f32, Custom);
530 // Use ANDPD and ORPD to simulate FCOPYSIGN.
531 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
532 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
534 // Lower this to FGETSIGNx86 plus an AND.
535 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom);
536 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom);
538 // We don't support sin/cos/fmod
539 setOperationAction(ISD::FSIN , MVT::f64, Expand);
540 setOperationAction(ISD::FCOS , MVT::f64, Expand);
541 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
542 setOperationAction(ISD::FSIN , MVT::f32, Expand);
543 setOperationAction(ISD::FCOS , MVT::f32, Expand);
544 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
546 // Expand FP immediates into loads from the stack, except for the special
548 addLegalFPImmediate(APFloat(+0.0)); // xorpd
549 addLegalFPImmediate(APFloat(+0.0f)); // xorps
550 } else if (!Subtarget->useSoftFloat() && X86ScalarSSEf32) {
551 // Use SSE for f32, x87 for f64.
552 // Set up the FP register classes.
553 addRegisterClass(MVT::f32, &X86::FR32RegClass);
554 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
556 // Use ANDPS to simulate FABS.
557 setOperationAction(ISD::FABS , MVT::f32, Custom);
559 // Use XORP to simulate FNEG.
560 setOperationAction(ISD::FNEG , MVT::f32, Custom);
562 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
564 // Use ANDPS and ORPS to simulate FCOPYSIGN.
565 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
566 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
568 // We don't support sin/cos/fmod
569 setOperationAction(ISD::FSIN , MVT::f32, Expand);
570 setOperationAction(ISD::FCOS , MVT::f32, Expand);
571 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
573 // Special cases we handle for FP constants.
574 addLegalFPImmediate(APFloat(+0.0f)); // xorps
575 addLegalFPImmediate(APFloat(+0.0)); // FLD0
576 addLegalFPImmediate(APFloat(+1.0)); // FLD1
577 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
578 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
580 if (!TM.Options.UnsafeFPMath) {
581 setOperationAction(ISD::FSIN , MVT::f64, Expand);
582 setOperationAction(ISD::FCOS , MVT::f64, Expand);
583 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
585 } else if (!Subtarget->useSoftFloat()) {
586 // f32 and f64 in x87.
587 // Set up the FP register classes.
588 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
589 addRegisterClass(MVT::f32, &X86::RFP32RegClass);
591 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
592 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
593 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
594 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
596 if (!TM.Options.UnsafeFPMath) {
597 setOperationAction(ISD::FSIN , MVT::f64, Expand);
598 setOperationAction(ISD::FSIN , MVT::f32, Expand);
599 setOperationAction(ISD::FCOS , MVT::f64, Expand);
600 setOperationAction(ISD::FCOS , MVT::f32, Expand);
601 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
602 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
604 addLegalFPImmediate(APFloat(+0.0)); // FLD0
605 addLegalFPImmediate(APFloat(+1.0)); // FLD1
606 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
607 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
608 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
609 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
610 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
611 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
614 // We don't support FMA.
615 setOperationAction(ISD::FMA, MVT::f64, Expand);
616 setOperationAction(ISD::FMA, MVT::f32, Expand);
618 // Long double always uses X87.
619 if (!Subtarget->useSoftFloat()) {
620 addRegisterClass(MVT::f80, &X86::RFP80RegClass);
621 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
622 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
624 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended);
625 addLegalFPImmediate(TmpFlt); // FLD0
627 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
630 APFloat TmpFlt2(+1.0);
631 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
633 addLegalFPImmediate(TmpFlt2); // FLD1
634 TmpFlt2.changeSign();
635 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
638 if (!TM.Options.UnsafeFPMath) {
639 setOperationAction(ISD::FSIN , MVT::f80, Expand);
640 setOperationAction(ISD::FCOS , MVT::f80, Expand);
641 setOperationAction(ISD::FSINCOS, MVT::f80, Expand);
644 setOperationAction(ISD::FFLOOR, MVT::f80, Expand);
645 setOperationAction(ISD::FCEIL, MVT::f80, Expand);
646 setOperationAction(ISD::FTRUNC, MVT::f80, Expand);
647 setOperationAction(ISD::FRINT, MVT::f80, Expand);
648 setOperationAction(ISD::FNEARBYINT, MVT::f80, Expand);
649 setOperationAction(ISD::FMA, MVT::f80, Expand);
652 // Always use a library call for pow.
653 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
654 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
655 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
657 setOperationAction(ISD::FLOG, MVT::f80, Expand);
658 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
659 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
660 setOperationAction(ISD::FEXP, MVT::f80, Expand);
661 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
662 setOperationAction(ISD::FMINNUM, MVT::f80, Expand);
663 setOperationAction(ISD::FMAXNUM, MVT::f80, Expand);
665 // First set operation action for all vector types to either promote
666 // (for widening) or expand (for scalarization). Then we will selectively
667 // turn on ones that can be effectively codegen'd.
668 for (MVT VT : MVT::vector_valuetypes()) {
669 setOperationAction(ISD::ADD , VT, Expand);
670 setOperationAction(ISD::SUB , VT, Expand);
671 setOperationAction(ISD::FADD, VT, Expand);
672 setOperationAction(ISD::FNEG, VT, Expand);
673 setOperationAction(ISD::FSUB, VT, Expand);
674 setOperationAction(ISD::MUL , VT, Expand);
675 setOperationAction(ISD::FMUL, VT, Expand);
676 setOperationAction(ISD::SDIV, VT, Expand);
677 setOperationAction(ISD::UDIV, VT, Expand);
678 setOperationAction(ISD::FDIV, VT, Expand);
679 setOperationAction(ISD::SREM, VT, Expand);
680 setOperationAction(ISD::UREM, VT, Expand);
681 setOperationAction(ISD::LOAD, VT, Expand);
682 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);
683 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT,Expand);
684 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
685 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT,Expand);
686 setOperationAction(ISD::INSERT_SUBVECTOR, VT,Expand);
687 setOperationAction(ISD::FABS, VT, Expand);
688 setOperationAction(ISD::FSIN, VT, Expand);
689 setOperationAction(ISD::FSINCOS, VT, Expand);
690 setOperationAction(ISD::FCOS, VT, Expand);
691 setOperationAction(ISD::FSINCOS, VT, Expand);
692 setOperationAction(ISD::FREM, VT, Expand);
693 setOperationAction(ISD::FMA, VT, Expand);
694 setOperationAction(ISD::FPOWI, VT, Expand);
695 setOperationAction(ISD::FSQRT, VT, Expand);
696 setOperationAction(ISD::FCOPYSIGN, VT, Expand);
697 setOperationAction(ISD::FFLOOR, VT, Expand);
698 setOperationAction(ISD::FCEIL, VT, Expand);
699 setOperationAction(ISD::FTRUNC, VT, Expand);
700 setOperationAction(ISD::FRINT, VT, Expand);
701 setOperationAction(ISD::FNEARBYINT, VT, Expand);
702 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
703 setOperationAction(ISD::MULHS, VT, Expand);
704 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
705 setOperationAction(ISD::MULHU, VT, Expand);
706 setOperationAction(ISD::SDIVREM, VT, Expand);
707 setOperationAction(ISD::UDIVREM, VT, Expand);
708 setOperationAction(ISD::FPOW, VT, Expand);
709 setOperationAction(ISD::CTPOP, VT, Expand);
710 setOperationAction(ISD::CTTZ, VT, Expand);
711 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
712 setOperationAction(ISD::CTLZ, VT, Expand);
713 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
714 setOperationAction(ISD::SHL, VT, Expand);
715 setOperationAction(ISD::SRA, VT, Expand);
716 setOperationAction(ISD::SRL, VT, Expand);
717 setOperationAction(ISD::ROTL, VT, Expand);
718 setOperationAction(ISD::ROTR, VT, Expand);
719 setOperationAction(ISD::BSWAP, VT, Expand);
720 setOperationAction(ISD::SETCC, VT, Expand);
721 setOperationAction(ISD::FLOG, VT, Expand);
722 setOperationAction(ISD::FLOG2, VT, Expand);
723 setOperationAction(ISD::FLOG10, VT, Expand);
724 setOperationAction(ISD::FEXP, VT, Expand);
725 setOperationAction(ISD::FEXP2, VT, Expand);
726 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
727 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
728 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
729 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
730 setOperationAction(ISD::SIGN_EXTEND_INREG, VT,Expand);
731 setOperationAction(ISD::TRUNCATE, VT, Expand);
732 setOperationAction(ISD::SIGN_EXTEND, VT, Expand);
733 setOperationAction(ISD::ZERO_EXTEND, VT, Expand);
734 setOperationAction(ISD::ANY_EXTEND, VT, Expand);
735 setOperationAction(ISD::VSELECT, VT, Expand);
736 setOperationAction(ISD::SELECT_CC, VT, Expand);
737 for (MVT InnerVT : MVT::vector_valuetypes()) {
738 setTruncStoreAction(InnerVT, VT, Expand);
740 setLoadExtAction(ISD::SEXTLOAD, InnerVT, VT, Expand);
741 setLoadExtAction(ISD::ZEXTLOAD, InnerVT, VT, Expand);
743 // N.b. ISD::EXTLOAD legality is basically ignored except for i1-like
744 // types, we have to deal with them whether we ask for Expansion or not.
745 // Setting Expand causes its own optimisation problems though, so leave
747 if (VT.getVectorElementType() == MVT::i1)
748 setLoadExtAction(ISD::EXTLOAD, InnerVT, VT, Expand);
750 // EXTLOAD for MVT::f16 vectors is not legal because f16 vectors are
751 // split/scalarized right now.
752 if (VT.getVectorElementType() == MVT::f16)
753 setLoadExtAction(ISD::EXTLOAD, InnerVT, VT, Expand);
757 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
758 // with -msoft-float, disable use of MMX as well.
759 if (!Subtarget->useSoftFloat() && Subtarget->hasMMX()) {
760 addRegisterClass(MVT::x86mmx, &X86::VR64RegClass);
761 // No operations on x86mmx supported, everything uses intrinsics.
764 // MMX-sized vectors (other than x86mmx) are expected to be expanded
765 // into smaller operations.
766 for (MVT MMXTy : {MVT::v8i8, MVT::v4i16, MVT::v2i32, MVT::v1i64}) {
767 setOperationAction(ISD::MULHS, MMXTy, Expand);
768 setOperationAction(ISD::AND, MMXTy, Expand);
769 setOperationAction(ISD::OR, MMXTy, Expand);
770 setOperationAction(ISD::XOR, MMXTy, Expand);
771 setOperationAction(ISD::SCALAR_TO_VECTOR, MMXTy, Expand);
772 setOperationAction(ISD::SELECT, MMXTy, Expand);
773 setOperationAction(ISD::BITCAST, MMXTy, Expand);
775 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand);
777 if (!Subtarget->useSoftFloat() && Subtarget->hasSSE1()) {
778 addRegisterClass(MVT::v4f32, &X86::VR128RegClass);
780 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
781 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
782 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
783 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
784 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
785 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
786 setOperationAction(ISD::FABS, MVT::v4f32, Custom);
787 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
788 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
789 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
790 setOperationAction(ISD::VSELECT, MVT::v4f32, Custom);
791 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
792 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
793 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Custom);
796 if (!Subtarget->useSoftFloat() && Subtarget->hasSSE2()) {
797 addRegisterClass(MVT::v2f64, &X86::VR128RegClass);
799 // FIXME: Unfortunately, -soft-float and -no-implicit-float mean XMM
800 // registers cannot be used even for integer operations.
801 addRegisterClass(MVT::v16i8, &X86::VR128RegClass);
802 addRegisterClass(MVT::v8i16, &X86::VR128RegClass);
803 addRegisterClass(MVT::v4i32, &X86::VR128RegClass);
804 addRegisterClass(MVT::v2i64, &X86::VR128RegClass);
806 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
807 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
808 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
809 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
810 setOperationAction(ISD::MUL, MVT::v16i8, Custom);
811 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
812 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
813 setOperationAction(ISD::UMUL_LOHI, MVT::v4i32, Custom);
814 setOperationAction(ISD::SMUL_LOHI, MVT::v4i32, Custom);
815 setOperationAction(ISD::MULHU, MVT::v8i16, Legal);
816 setOperationAction(ISD::MULHS, MVT::v8i16, Legal);
817 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
818 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
819 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
820 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
821 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
822 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
823 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
824 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
825 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
826 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
827 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
828 setOperationAction(ISD::FABS, MVT::v2f64, Custom);
830 setOperationAction(ISD::SMAX, MVT::v8i16, Legal);
831 setOperationAction(ISD::UMAX, MVT::v16i8, Legal);
832 setOperationAction(ISD::SMIN, MVT::v8i16, Legal);
833 setOperationAction(ISD::UMIN, MVT::v16i8, Legal);
835 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
836 setOperationAction(ISD::SETCC, MVT::v16i8, Custom);
837 setOperationAction(ISD::SETCC, MVT::v8i16, Custom);
838 setOperationAction(ISD::SETCC, MVT::v4i32, Custom);
840 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
841 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
842 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
843 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
844 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
846 setOperationAction(ISD::CTPOP, MVT::v16i8, Custom);
847 setOperationAction(ISD::CTPOP, MVT::v8i16, Custom);
848 setOperationAction(ISD::CTPOP, MVT::v4i32, Custom);
849 setOperationAction(ISD::CTPOP, MVT::v2i64, Custom);
851 setOperationAction(ISD::CTTZ, MVT::v16i8, Custom);
852 setOperationAction(ISD::CTTZ, MVT::v8i16, Custom);
853 setOperationAction(ISD::CTTZ, MVT::v4i32, Custom);
854 // ISD::CTTZ v2i64 - scalarization is faster.
855 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v16i8, Custom);
856 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v8i16, Custom);
857 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v4i32, Custom);
858 // ISD::CTTZ_ZERO_UNDEF v2i64 - scalarization is faster.
860 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
861 for (auto VT : { MVT::v16i8, MVT::v8i16, MVT::v4i32 }) {
862 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
863 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
864 setOperationAction(ISD::VSELECT, VT, Custom);
865 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
868 // We support custom legalizing of sext and anyext loads for specific
869 // memory vector types which we can load as a scalar (or sequence of
870 // scalars) and extend in-register to a legal 128-bit vector type. For sext
871 // loads these must work with a single scalar load.
872 for (MVT VT : MVT::integer_vector_valuetypes()) {
873 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v4i8, Custom);
874 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v4i16, Custom);
875 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v8i8, Custom);
876 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i8, Custom);
877 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i16, Custom);
878 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i32, Custom);
879 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4i8, Custom);
880 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4i16, Custom);
881 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v8i8, Custom);
884 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
885 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
886 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
887 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
888 setOperationAction(ISD::VSELECT, MVT::v2f64, Custom);
889 setOperationAction(ISD::VSELECT, MVT::v2i64, Custom);
890 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
891 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
893 if (Subtarget->is64Bit()) {
894 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
895 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
898 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
899 for (auto VT : { MVT::v16i8, MVT::v8i16, MVT::v4i32 }) {
900 setOperationAction(ISD::AND, VT, Promote);
901 AddPromotedToType (ISD::AND, VT, MVT::v2i64);
902 setOperationAction(ISD::OR, VT, Promote);
903 AddPromotedToType (ISD::OR, VT, MVT::v2i64);
904 setOperationAction(ISD::XOR, VT, Promote);
905 AddPromotedToType (ISD::XOR, VT, MVT::v2i64);
906 setOperationAction(ISD::LOAD, VT, Promote);
907 AddPromotedToType (ISD::LOAD, VT, MVT::v2i64);
908 setOperationAction(ISD::SELECT, VT, Promote);
909 AddPromotedToType (ISD::SELECT, VT, MVT::v2i64);
912 // Custom lower v2i64 and v2f64 selects.
913 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
914 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
915 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
916 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
918 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
919 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
921 setOperationAction(ISD::SINT_TO_FP, MVT::v2i32, Custom);
923 setOperationAction(ISD::UINT_TO_FP, MVT::v4i8, Custom);
924 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);
925 // As there is no 64-bit GPR available, we need build a special custom
926 // sequence to convert from v2i32 to v2f32.
927 if (!Subtarget->is64Bit())
928 setOperationAction(ISD::UINT_TO_FP, MVT::v2f32, Custom);
930 setOperationAction(ISD::FP_EXTEND, MVT::v2f32, Custom);
931 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Custom);
933 for (MVT VT : MVT::fp_vector_valuetypes())
934 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2f32, Legal);
936 setOperationAction(ISD::BITCAST, MVT::v2i32, Custom);
937 setOperationAction(ISD::BITCAST, MVT::v4i16, Custom);
938 setOperationAction(ISD::BITCAST, MVT::v8i8, Custom);
941 if (!Subtarget->useSoftFloat() && Subtarget->hasSSE41()) {
942 for (MVT RoundedTy : {MVT::f32, MVT::f64, MVT::v4f32, MVT::v2f64}) {
943 setOperationAction(ISD::FFLOOR, RoundedTy, Legal);
944 setOperationAction(ISD::FCEIL, RoundedTy, Legal);
945 setOperationAction(ISD::FTRUNC, RoundedTy, Legal);
946 setOperationAction(ISD::FRINT, RoundedTy, Legal);
947 setOperationAction(ISD::FNEARBYINT, RoundedTy, Legal);
950 setOperationAction(ISD::SMAX, MVT::v16i8, Legal);
951 setOperationAction(ISD::SMAX, MVT::v4i32, Legal);
952 setOperationAction(ISD::UMAX, MVT::v8i16, Legal);
953 setOperationAction(ISD::UMAX, MVT::v4i32, Legal);
954 setOperationAction(ISD::SMIN, MVT::v16i8, Legal);
955 setOperationAction(ISD::SMIN, MVT::v4i32, Legal);
956 setOperationAction(ISD::UMIN, MVT::v8i16, Legal);
957 setOperationAction(ISD::UMIN, MVT::v4i32, Legal);
959 // FIXME: Do we need to handle scalar-to-vector here?
960 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
962 // We directly match byte blends in the backend as they match the VSELECT
964 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
966 // SSE41 brings specific instructions for doing vector sign extend even in
967 // cases where we don't have SRA.
968 for (MVT VT : MVT::integer_vector_valuetypes()) {
969 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i8, Custom);
970 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i16, Custom);
971 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i32, Custom);
974 // SSE41 also has vector sign/zero extending loads, PMOV[SZ]X
975 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i16, MVT::v8i8, Legal);
976 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i32, MVT::v4i8, Legal);
977 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i64, MVT::v2i8, Legal);
978 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i32, MVT::v4i16, Legal);
979 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i64, MVT::v2i16, Legal);
980 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i64, MVT::v2i32, Legal);
982 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i16, MVT::v8i8, Legal);
983 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i32, MVT::v4i8, Legal);
984 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i64, MVT::v2i8, Legal);
985 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i32, MVT::v4i16, Legal);
986 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i64, MVT::v2i16, Legal);
987 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i64, MVT::v2i32, Legal);
989 // i8 and i16 vectors are custom because the source register and source
990 // source memory operand types are not the same width. f32 vectors are
991 // custom since the immediate controlling the insert encodes additional
993 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
994 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
995 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
996 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
998 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
999 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
1000 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
1001 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
1003 // FIXME: these should be Legal, but that's only for the case where
1004 // the index is constant. For now custom expand to deal with that.
1005 if (Subtarget->is64Bit()) {
1006 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
1007 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
1011 if (Subtarget->hasSSE2()) {
1012 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v2i64, Custom);
1013 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v4i32, Custom);
1014 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v8i16, Custom);
1016 setOperationAction(ISD::SRL, MVT::v8i16, Custom);
1017 setOperationAction(ISD::SRL, MVT::v16i8, Custom);
1019 setOperationAction(ISD::SHL, MVT::v8i16, Custom);
1020 setOperationAction(ISD::SHL, MVT::v16i8, Custom);
1022 setOperationAction(ISD::SRA, MVT::v8i16, Custom);
1023 setOperationAction(ISD::SRA, MVT::v16i8, Custom);
1025 // In the customized shift lowering, the legal cases in AVX2 will be
1027 setOperationAction(ISD::SRL, MVT::v2i64, Custom);
1028 setOperationAction(ISD::SRL, MVT::v4i32, Custom);
1030 setOperationAction(ISD::SHL, MVT::v2i64, Custom);
1031 setOperationAction(ISD::SHL, MVT::v4i32, Custom);
1033 setOperationAction(ISD::SRA, MVT::v2i64, Custom);
1034 setOperationAction(ISD::SRA, MVT::v4i32, Custom);
1037 if (Subtarget->hasXOP()) {
1038 setOperationAction(ISD::ROTL, MVT::v16i8, Custom);
1039 setOperationAction(ISD::ROTL, MVT::v8i16, Custom);
1040 setOperationAction(ISD::ROTL, MVT::v4i32, Custom);
1041 setOperationAction(ISD::ROTL, MVT::v2i64, Custom);
1042 setOperationAction(ISD::ROTL, MVT::v32i8, Custom);
1043 setOperationAction(ISD::ROTL, MVT::v16i16, Custom);
1044 setOperationAction(ISD::ROTL, MVT::v8i32, Custom);
1045 setOperationAction(ISD::ROTL, MVT::v4i64, Custom);
1048 if (!Subtarget->useSoftFloat() && Subtarget->hasFp256()) {
1049 addRegisterClass(MVT::v32i8, &X86::VR256RegClass);
1050 addRegisterClass(MVT::v16i16, &X86::VR256RegClass);
1051 addRegisterClass(MVT::v8i32, &X86::VR256RegClass);
1052 addRegisterClass(MVT::v8f32, &X86::VR256RegClass);
1053 addRegisterClass(MVT::v4i64, &X86::VR256RegClass);
1054 addRegisterClass(MVT::v4f64, &X86::VR256RegClass);
1056 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
1057 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
1058 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
1060 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
1061 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
1062 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
1063 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
1064 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
1065 setOperationAction(ISD::FFLOOR, MVT::v8f32, Legal);
1066 setOperationAction(ISD::FCEIL, MVT::v8f32, Legal);
1067 setOperationAction(ISD::FTRUNC, MVT::v8f32, Legal);
1068 setOperationAction(ISD::FRINT, MVT::v8f32, Legal);
1069 setOperationAction(ISD::FNEARBYINT, MVT::v8f32, Legal);
1070 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
1071 setOperationAction(ISD::FABS, MVT::v8f32, Custom);
1073 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
1074 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
1075 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
1076 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
1077 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
1078 setOperationAction(ISD::FFLOOR, MVT::v4f64, Legal);
1079 setOperationAction(ISD::FCEIL, MVT::v4f64, Legal);
1080 setOperationAction(ISD::FTRUNC, MVT::v4f64, Legal);
1081 setOperationAction(ISD::FRINT, MVT::v4f64, Legal);
1082 setOperationAction(ISD::FNEARBYINT, MVT::v4f64, Legal);
1083 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
1084 setOperationAction(ISD::FABS, MVT::v4f64, Custom);
1086 // (fp_to_int:v8i16 (v8f32 ..)) requires the result type to be promoted
1087 // even though v8i16 is a legal type.
1088 setOperationAction(ISD::FP_TO_SINT, MVT::v8i16, Promote);
1089 setOperationAction(ISD::FP_TO_UINT, MVT::v8i16, Promote);
1090 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
1092 setOperationAction(ISD::SINT_TO_FP, MVT::v8i16, Promote);
1093 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
1094 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal);
1096 setOperationAction(ISD::UINT_TO_FP, MVT::v8i8, Custom);
1097 setOperationAction(ISD::UINT_TO_FP, MVT::v8i16, Custom);
1099 for (MVT VT : MVT::fp_vector_valuetypes())
1100 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4f32, Legal);
1102 setOperationAction(ISD::SRL, MVT::v16i16, Custom);
1103 setOperationAction(ISD::SRL, MVT::v32i8, Custom);
1105 setOperationAction(ISD::SHL, MVT::v16i16, Custom);
1106 setOperationAction(ISD::SHL, MVT::v32i8, Custom);
1108 setOperationAction(ISD::SRA, MVT::v16i16, Custom);
1109 setOperationAction(ISD::SRA, MVT::v32i8, Custom);
1111 setOperationAction(ISD::SETCC, MVT::v32i8, Custom);
1112 setOperationAction(ISD::SETCC, MVT::v16i16, Custom);
1113 setOperationAction(ISD::SETCC, MVT::v8i32, Custom);
1114 setOperationAction(ISD::SETCC, MVT::v4i64, Custom);
1116 setOperationAction(ISD::SELECT, MVT::v4f64, Custom);
1117 setOperationAction(ISD::SELECT, MVT::v4i64, Custom);
1118 setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
1120 setOperationAction(ISD::SIGN_EXTEND, MVT::v4i64, Custom);
1121 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i32, Custom);
1122 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1123 setOperationAction(ISD::ZERO_EXTEND, MVT::v4i64, Custom);
1124 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i32, Custom);
1125 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i16, Custom);
1126 setOperationAction(ISD::ANY_EXTEND, MVT::v4i64, Custom);
1127 setOperationAction(ISD::ANY_EXTEND, MVT::v8i32, Custom);
1128 setOperationAction(ISD::ANY_EXTEND, MVT::v16i16, Custom);
1129 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1130 setOperationAction(ISD::TRUNCATE, MVT::v8i16, Custom);
1131 setOperationAction(ISD::TRUNCATE, MVT::v4i32, Custom);
1133 setOperationAction(ISD::CTPOP, MVT::v32i8, Custom);
1134 setOperationAction(ISD::CTPOP, MVT::v16i16, Custom);
1135 setOperationAction(ISD::CTPOP, MVT::v8i32, Custom);
1136 setOperationAction(ISD::CTPOP, MVT::v4i64, Custom);
1138 setOperationAction(ISD::CTTZ, MVT::v32i8, Custom);
1139 setOperationAction(ISD::CTTZ, MVT::v16i16, Custom);
1140 setOperationAction(ISD::CTTZ, MVT::v8i32, Custom);
1141 setOperationAction(ISD::CTTZ, MVT::v4i64, Custom);
1142 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v32i8, Custom);
1143 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v16i16, Custom);
1144 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v8i32, Custom);
1145 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v4i64, Custom);
1147 if (Subtarget->hasFMA() || Subtarget->hasFMA4() || Subtarget->hasAVX512()) {
1148 setOperationAction(ISD::FMA, MVT::v8f32, Legal);
1149 setOperationAction(ISD::FMA, MVT::v4f64, Legal);
1150 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
1151 setOperationAction(ISD::FMA, MVT::v2f64, Legal);
1152 setOperationAction(ISD::FMA, MVT::f32, Legal);
1153 setOperationAction(ISD::FMA, MVT::f64, Legal);
1156 if (Subtarget->hasInt256()) {
1157 setOperationAction(ISD::ADD, MVT::v4i64, Legal);
1158 setOperationAction(ISD::ADD, MVT::v8i32, Legal);
1159 setOperationAction(ISD::ADD, MVT::v16i16, Legal);
1160 setOperationAction(ISD::ADD, MVT::v32i8, Legal);
1162 setOperationAction(ISD::SUB, MVT::v4i64, Legal);
1163 setOperationAction(ISD::SUB, MVT::v8i32, Legal);
1164 setOperationAction(ISD::SUB, MVT::v16i16, Legal);
1165 setOperationAction(ISD::SUB, MVT::v32i8, Legal);
1167 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1168 setOperationAction(ISD::MUL, MVT::v8i32, Legal);
1169 setOperationAction(ISD::MUL, MVT::v16i16, Legal);
1170 setOperationAction(ISD::MUL, MVT::v32i8, Custom);
1172 setOperationAction(ISD::UMUL_LOHI, MVT::v8i32, Custom);
1173 setOperationAction(ISD::SMUL_LOHI, MVT::v8i32, Custom);
1174 setOperationAction(ISD::MULHU, MVT::v16i16, Legal);
1175 setOperationAction(ISD::MULHS, MVT::v16i16, Legal);
1177 setOperationAction(ISD::SMAX, MVT::v32i8, Legal);
1178 setOperationAction(ISD::SMAX, MVT::v16i16, Legal);
1179 setOperationAction(ISD::SMAX, MVT::v8i32, Legal);
1180 setOperationAction(ISD::UMAX, MVT::v32i8, Legal);
1181 setOperationAction(ISD::UMAX, MVT::v16i16, Legal);
1182 setOperationAction(ISD::UMAX, MVT::v8i32, Legal);
1183 setOperationAction(ISD::SMIN, MVT::v32i8, Legal);
1184 setOperationAction(ISD::SMIN, MVT::v16i16, Legal);
1185 setOperationAction(ISD::SMIN, MVT::v8i32, Legal);
1186 setOperationAction(ISD::UMIN, MVT::v32i8, Legal);
1187 setOperationAction(ISD::UMIN, MVT::v16i16, Legal);
1188 setOperationAction(ISD::UMIN, MVT::v8i32, Legal);
1190 // The custom lowering for UINT_TO_FP for v8i32 becomes interesting
1191 // when we have a 256bit-wide blend with immediate.
1192 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Custom);
1194 // AVX2 also has wider vector sign/zero extending loads, VPMOV[SZ]X
1195 setLoadExtAction(ISD::SEXTLOAD, MVT::v16i16, MVT::v16i8, Legal);
1196 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i32, MVT::v8i8, Legal);
1197 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i64, MVT::v4i8, Legal);
1198 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i32, MVT::v8i16, Legal);
1199 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i64, MVT::v4i16, Legal);
1200 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i64, MVT::v4i32, Legal);
1202 setLoadExtAction(ISD::ZEXTLOAD, MVT::v16i16, MVT::v16i8, Legal);
1203 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i32, MVT::v8i8, Legal);
1204 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i64, MVT::v4i8, Legal);
1205 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i32, MVT::v8i16, Legal);
1206 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i64, MVT::v4i16, Legal);
1207 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i64, MVT::v4i32, Legal);
1209 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
1210 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
1211 setOperationAction(ISD::ADD, MVT::v16i16, Custom);
1212 setOperationAction(ISD::ADD, MVT::v32i8, Custom);
1214 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
1215 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
1216 setOperationAction(ISD::SUB, MVT::v16i16, Custom);
1217 setOperationAction(ISD::SUB, MVT::v32i8, Custom);
1219 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1220 setOperationAction(ISD::MUL, MVT::v8i32, Custom);
1221 setOperationAction(ISD::MUL, MVT::v16i16, Custom);
1222 setOperationAction(ISD::MUL, MVT::v32i8, Custom);
1224 setOperationAction(ISD::SMAX, MVT::v32i8, Custom);
1225 setOperationAction(ISD::SMAX, MVT::v16i16, Custom);
1226 setOperationAction(ISD::SMAX, MVT::v8i32, Custom);
1227 setOperationAction(ISD::UMAX, MVT::v32i8, Custom);
1228 setOperationAction(ISD::UMAX, MVT::v16i16, Custom);
1229 setOperationAction(ISD::UMAX, MVT::v8i32, Custom);
1230 setOperationAction(ISD::SMIN, MVT::v32i8, Custom);
1231 setOperationAction(ISD::SMIN, MVT::v16i16, Custom);
1232 setOperationAction(ISD::SMIN, MVT::v8i32, Custom);
1233 setOperationAction(ISD::UMIN, MVT::v32i8, Custom);
1234 setOperationAction(ISD::UMIN, MVT::v16i16, Custom);
1235 setOperationAction(ISD::UMIN, MVT::v8i32, Custom);
1238 // In the customized shift lowering, the legal cases in AVX2 will be
1240 setOperationAction(ISD::SRL, MVT::v4i64, Custom);
1241 setOperationAction(ISD::SRL, MVT::v8i32, Custom);
1243 setOperationAction(ISD::SHL, MVT::v4i64, Custom);
1244 setOperationAction(ISD::SHL, MVT::v8i32, Custom);
1246 setOperationAction(ISD::SRA, MVT::v4i64, Custom);
1247 setOperationAction(ISD::SRA, MVT::v8i32, Custom);
1249 // Custom lower several nodes for 256-bit types.
1250 for (MVT VT : MVT::vector_valuetypes()) {
1251 if (VT.getScalarSizeInBits() >= 32) {
1252 setOperationAction(ISD::MLOAD, VT, Legal);
1253 setOperationAction(ISD::MSTORE, VT, Legal);
1255 // Extract subvector is special because the value type
1256 // (result) is 128-bit but the source is 256-bit wide.
1257 if (VT.is128BitVector()) {
1258 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1260 // Do not attempt to custom lower other non-256-bit vectors
1261 if (!VT.is256BitVector())
1264 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1265 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1266 setOperationAction(ISD::VSELECT, VT, Custom);
1267 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1268 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1269 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1270 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1271 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom);
1274 if (Subtarget->hasInt256())
1275 setOperationAction(ISD::VSELECT, MVT::v32i8, Legal);
1277 // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64.
1278 for (auto VT : { MVT::v32i8, MVT::v16i16, MVT::v8i32 }) {
1279 setOperationAction(ISD::AND, VT, Promote);
1280 AddPromotedToType (ISD::AND, VT, MVT::v4i64);
1281 setOperationAction(ISD::OR, VT, Promote);
1282 AddPromotedToType (ISD::OR, VT, MVT::v4i64);
1283 setOperationAction(ISD::XOR, VT, Promote);
1284 AddPromotedToType (ISD::XOR, VT, MVT::v4i64);
1285 setOperationAction(ISD::LOAD, VT, Promote);
1286 AddPromotedToType (ISD::LOAD, VT, MVT::v4i64);
1287 setOperationAction(ISD::SELECT, VT, Promote);
1288 AddPromotedToType (ISD::SELECT, VT, MVT::v4i64);
1292 if (!Subtarget->useSoftFloat() && Subtarget->hasAVX512()) {
1293 addRegisterClass(MVT::v16i32, &X86::VR512RegClass);
1294 addRegisterClass(MVT::v16f32, &X86::VR512RegClass);
1295 addRegisterClass(MVT::v8i64, &X86::VR512RegClass);
1296 addRegisterClass(MVT::v8f64, &X86::VR512RegClass);
1298 addRegisterClass(MVT::i1, &X86::VK1RegClass);
1299 addRegisterClass(MVT::v8i1, &X86::VK8RegClass);
1300 addRegisterClass(MVT::v16i1, &X86::VK16RegClass);
1302 for (MVT VT : MVT::fp_vector_valuetypes())
1303 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v8f32, Legal);
1305 setLoadExtAction(ISD::ZEXTLOAD, MVT::v16i32, MVT::v16i8, Legal);
1306 setLoadExtAction(ISD::SEXTLOAD, MVT::v16i32, MVT::v16i8, Legal);
1307 setLoadExtAction(ISD::ZEXTLOAD, MVT::v16i32, MVT::v16i16, Legal);
1308 setLoadExtAction(ISD::SEXTLOAD, MVT::v16i32, MVT::v16i16, Legal);
1309 setLoadExtAction(ISD::ZEXTLOAD, MVT::v32i16, MVT::v32i8, Legal);
1310 setLoadExtAction(ISD::SEXTLOAD, MVT::v32i16, MVT::v32i8, Legal);
1311 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i64, MVT::v8i8, Legal);
1312 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i64, MVT::v8i8, Legal);
1313 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i64, MVT::v8i16, Legal);
1314 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i64, MVT::v8i16, Legal);
1315 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i64, MVT::v8i32, Legal);
1316 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i64, MVT::v8i32, Legal);
1318 setOperationAction(ISD::BR_CC, MVT::i1, Expand);
1319 setOperationAction(ISD::SETCC, MVT::i1, Custom);
1320 setOperationAction(ISD::SELECT_CC, MVT::i1, Expand);
1321 setOperationAction(ISD::XOR, MVT::i1, Legal);
1322 setOperationAction(ISD::OR, MVT::i1, Legal);
1323 setOperationAction(ISD::AND, MVT::i1, Legal);
1324 setOperationAction(ISD::SUB, MVT::i1, Custom);
1325 setOperationAction(ISD::ADD, MVT::i1, Custom);
1326 setOperationAction(ISD::MUL, MVT::i1, Custom);
1327 setOperationAction(ISD::LOAD, MVT::v16f32, Legal);
1328 setOperationAction(ISD::LOAD, MVT::v8f64, Legal);
1329 setOperationAction(ISD::LOAD, MVT::v8i64, Legal);
1330 setOperationAction(ISD::LOAD, MVT::v16i32, Legal);
1331 setOperationAction(ISD::LOAD, MVT::v16i1, Legal);
1333 setOperationAction(ISD::FADD, MVT::v16f32, Legal);
1334 setOperationAction(ISD::FSUB, MVT::v16f32, Legal);
1335 setOperationAction(ISD::FMUL, MVT::v16f32, Legal);
1336 setOperationAction(ISD::FDIV, MVT::v16f32, Legal);
1337 setOperationAction(ISD::FSQRT, MVT::v16f32, Legal);
1338 setOperationAction(ISD::FNEG, MVT::v16f32, Custom);
1340 setOperationAction(ISD::FADD, MVT::v8f64, Legal);
1341 setOperationAction(ISD::FSUB, MVT::v8f64, Legal);
1342 setOperationAction(ISD::FMUL, MVT::v8f64, Legal);
1343 setOperationAction(ISD::FDIV, MVT::v8f64, Legal);
1344 setOperationAction(ISD::FSQRT, MVT::v8f64, Legal);
1345 setOperationAction(ISD::FNEG, MVT::v8f64, Custom);
1346 setOperationAction(ISD::FMA, MVT::v8f64, Legal);
1347 setOperationAction(ISD::FMA, MVT::v16f32, Legal);
1349 setOperationAction(ISD::FP_TO_SINT, MVT::v16i32, Legal);
1350 setOperationAction(ISD::FP_TO_UINT, MVT::v16i32, Legal);
1351 setOperationAction(ISD::FP_TO_UINT, MVT::v8i32, Legal);
1352 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
1353 setOperationAction(ISD::SINT_TO_FP, MVT::v16i32, Legal);
1354 setOperationAction(ISD::SINT_TO_FP, MVT::v8i1, Custom);
1355 setOperationAction(ISD::SINT_TO_FP, MVT::v16i1, Custom);
1356 setOperationAction(ISD::SINT_TO_FP, MVT::v16i8, Promote);
1357 setOperationAction(ISD::SINT_TO_FP, MVT::v16i16, Promote);
1358 setOperationAction(ISD::UINT_TO_FP, MVT::v16i32, Legal);
1359 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Legal);
1360 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
1361 setOperationAction(ISD::UINT_TO_FP, MVT::v16i8, Custom);
1362 setOperationAction(ISD::UINT_TO_FP, MVT::v16i16, Custom);
1363 setOperationAction(ISD::FP_ROUND, MVT::v8f32, Legal);
1364 setOperationAction(ISD::FP_EXTEND, MVT::v8f32, Legal);
1366 setTruncStoreAction(MVT::v8i64, MVT::v8i8, Legal);
1367 setTruncStoreAction(MVT::v8i64, MVT::v8i16, Legal);
1368 setTruncStoreAction(MVT::v8i64, MVT::v8i32, Legal);
1369 setTruncStoreAction(MVT::v16i32, MVT::v16i8, Legal);
1370 setTruncStoreAction(MVT::v16i32, MVT::v16i16, Legal);
1371 if (Subtarget->hasVLX()){
1372 setTruncStoreAction(MVT::v4i64, MVT::v4i8, Legal);
1373 setTruncStoreAction(MVT::v4i64, MVT::v4i16, Legal);
1374 setTruncStoreAction(MVT::v4i64, MVT::v4i32, Legal);
1375 setTruncStoreAction(MVT::v8i32, MVT::v8i8, Legal);
1376 setTruncStoreAction(MVT::v8i32, MVT::v8i16, Legal);
1378 setTruncStoreAction(MVT::v2i64, MVT::v2i8, Legal);
1379 setTruncStoreAction(MVT::v2i64, MVT::v2i16, Legal);
1380 setTruncStoreAction(MVT::v2i64, MVT::v2i32, Legal);
1381 setTruncStoreAction(MVT::v4i32, MVT::v4i8, Legal);
1382 setTruncStoreAction(MVT::v4i32, MVT::v4i16, Legal);
1384 setOperationAction(ISD::TRUNCATE, MVT::i1, Custom);
1385 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1386 setOperationAction(ISD::TRUNCATE, MVT::v8i32, Custom);
1387 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i1, Custom);
1388 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i1, Custom);
1389 if (Subtarget->hasDQI()) {
1390 setOperationAction(ISD::TRUNCATE, MVT::v2i1, Custom);
1391 setOperationAction(ISD::TRUNCATE, MVT::v4i1, Custom);
1393 setOperationAction(ISD::SINT_TO_FP, MVT::v8i64, Legal);
1394 setOperationAction(ISD::UINT_TO_FP, MVT::v8i64, Legal);
1395 setOperationAction(ISD::FP_TO_SINT, MVT::v8i64, Legal);
1396 setOperationAction(ISD::FP_TO_UINT, MVT::v8i64, Legal);
1397 if (Subtarget->hasVLX()) {
1398 setOperationAction(ISD::SINT_TO_FP, MVT::v4i64, Legal);
1399 setOperationAction(ISD::SINT_TO_FP, MVT::v2i64, Legal);
1400 setOperationAction(ISD::UINT_TO_FP, MVT::v4i64, Legal);
1401 setOperationAction(ISD::UINT_TO_FP, MVT::v2i64, Legal);
1402 setOperationAction(ISD::FP_TO_SINT, MVT::v4i64, Legal);
1403 setOperationAction(ISD::FP_TO_SINT, MVT::v2i64, Legal);
1404 setOperationAction(ISD::FP_TO_UINT, MVT::v4i64, Legal);
1405 setOperationAction(ISD::FP_TO_UINT, MVT::v2i64, Legal);
1408 if (Subtarget->hasVLX()) {
1409 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
1410 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Legal);
1411 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
1412 setOperationAction(ISD::FP_TO_UINT, MVT::v8i32, Legal);
1413 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
1414 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
1415 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
1416 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
1418 setOperationAction(ISD::TRUNCATE, MVT::v8i1, Custom);
1419 setOperationAction(ISD::TRUNCATE, MVT::v16i1, Custom);
1420 setOperationAction(ISD::TRUNCATE, MVT::v16i16, Custom);
1421 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i32, Custom);
1422 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i64, Custom);
1423 setOperationAction(ISD::ANY_EXTEND, MVT::v16i32, Custom);
1424 setOperationAction(ISD::ANY_EXTEND, MVT::v8i64, Custom);
1425 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i32, Custom);
1426 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i64, Custom);
1427 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i8, Custom);
1428 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i16, Custom);
1429 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1430 if (Subtarget->hasDQI()) {
1431 setOperationAction(ISD::SIGN_EXTEND, MVT::v4i32, Custom);
1432 setOperationAction(ISD::SIGN_EXTEND, MVT::v2i64, Custom);
1434 setOperationAction(ISD::FFLOOR, MVT::v16f32, Legal);
1435 setOperationAction(ISD::FFLOOR, MVT::v8f64, Legal);
1436 setOperationAction(ISD::FCEIL, MVT::v16f32, Legal);
1437 setOperationAction(ISD::FCEIL, MVT::v8f64, Legal);
1438 setOperationAction(ISD::FTRUNC, MVT::v16f32, Legal);
1439 setOperationAction(ISD::FTRUNC, MVT::v8f64, Legal);
1440 setOperationAction(ISD::FRINT, MVT::v16f32, Legal);
1441 setOperationAction(ISD::FRINT, MVT::v8f64, Legal);
1442 setOperationAction(ISD::FNEARBYINT, MVT::v16f32, Legal);
1443 setOperationAction(ISD::FNEARBYINT, MVT::v8f64, Legal);
1445 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f64, Custom);
1446 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i64, Custom);
1447 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16f32, Custom);
1448 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i32, Custom);
1449 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i1, Legal);
1451 setOperationAction(ISD::SETCC, MVT::v16i1, Custom);
1452 setOperationAction(ISD::SETCC, MVT::v8i1, Custom);
1454 setOperationAction(ISD::MUL, MVT::v8i64, Custom);
1456 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i1, Custom);
1457 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i1, Custom);
1458 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i1, Custom);
1459 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i1, Custom);
1460 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i1, Custom);
1461 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i1, Custom);
1462 setOperationAction(ISD::SELECT, MVT::v8f64, Custom);
1463 setOperationAction(ISD::SELECT, MVT::v8i64, Custom);
1464 setOperationAction(ISD::SELECT, MVT::v16f32, Custom);
1465 setOperationAction(ISD::SELECT, MVT::v16i1, Custom);
1466 setOperationAction(ISD::SELECT, MVT::v8i1, Custom);
1468 setOperationAction(ISD::SMAX, MVT::v16i32, Legal);
1469 setOperationAction(ISD::SMAX, MVT::v8i64, Legal);
1470 setOperationAction(ISD::UMAX, MVT::v16i32, Legal);
1471 setOperationAction(ISD::UMAX, MVT::v8i64, Legal);
1472 setOperationAction(ISD::SMIN, MVT::v16i32, Legal);
1473 setOperationAction(ISD::SMIN, MVT::v8i64, Legal);
1474 setOperationAction(ISD::UMIN, MVT::v16i32, Legal);
1475 setOperationAction(ISD::UMIN, MVT::v8i64, Legal);
1477 setOperationAction(ISD::ADD, MVT::v8i64, Legal);
1478 setOperationAction(ISD::ADD, MVT::v16i32, Legal);
1480 setOperationAction(ISD::SUB, MVT::v8i64, Legal);
1481 setOperationAction(ISD::SUB, MVT::v16i32, Legal);
1483 setOperationAction(ISD::MUL, MVT::v16i32, Legal);
1485 setOperationAction(ISD::SRL, MVT::v8i64, Custom);
1486 setOperationAction(ISD::SRL, MVT::v16i32, Custom);
1488 setOperationAction(ISD::SHL, MVT::v8i64, Custom);
1489 setOperationAction(ISD::SHL, MVT::v16i32, Custom);
1491 setOperationAction(ISD::SRA, MVT::v8i64, Custom);
1492 setOperationAction(ISD::SRA, MVT::v16i32, Custom);
1494 setOperationAction(ISD::AND, MVT::v8i64, Legal);
1495 setOperationAction(ISD::OR, MVT::v8i64, Legal);
1496 setOperationAction(ISD::XOR, MVT::v8i64, Legal);
1497 setOperationAction(ISD::AND, MVT::v16i32, Legal);
1498 setOperationAction(ISD::OR, MVT::v16i32, Legal);
1499 setOperationAction(ISD::XOR, MVT::v16i32, Legal);
1501 if (Subtarget->hasCDI()) {
1502 setOperationAction(ISD::CTLZ, MVT::v8i64, Legal);
1503 setOperationAction(ISD::CTLZ, MVT::v16i32, Legal);
1504 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v8i64, Legal);
1505 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v16i32, Legal);
1507 setOperationAction(ISD::CTLZ, MVT::v8i16, Custom);
1508 setOperationAction(ISD::CTLZ, MVT::v16i8, Custom);
1509 setOperationAction(ISD::CTLZ, MVT::v16i16, Custom);
1510 setOperationAction(ISD::CTLZ, MVT::v32i8, Custom);
1511 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v8i16, Custom);
1512 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v16i8, Custom);
1513 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v16i16, Custom);
1514 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v32i8, Custom);
1516 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v8i64, Custom);
1517 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v16i32, Custom);
1519 if (Subtarget->hasVLX()) {
1520 setOperationAction(ISD::CTLZ, MVT::v4i64, Legal);
1521 setOperationAction(ISD::CTLZ, MVT::v8i32, Legal);
1522 setOperationAction(ISD::CTLZ, MVT::v2i64, Legal);
1523 setOperationAction(ISD::CTLZ, MVT::v4i32, Legal);
1524 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v4i64, Legal);
1525 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v8i32, Legal);
1526 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v2i64, Legal);
1527 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v4i32, Legal);
1529 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v4i64, Custom);
1530 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v8i32, Custom);
1531 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v2i64, Custom);
1532 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v4i32, Custom);
1534 setOperationAction(ISD::CTLZ, MVT::v4i64, Custom);
1535 setOperationAction(ISD::CTLZ, MVT::v8i32, Custom);
1536 setOperationAction(ISD::CTLZ, MVT::v2i64, Custom);
1537 setOperationAction(ISD::CTLZ, MVT::v4i32, Custom);
1538 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v4i64, Custom);
1539 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v8i32, Custom);
1540 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v2i64, Custom);
1541 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v4i32, Custom);
1543 } // Subtarget->hasCDI()
1545 if (Subtarget->hasDQI()) {
1546 setOperationAction(ISD::MUL, MVT::v2i64, Legal);
1547 setOperationAction(ISD::MUL, MVT::v4i64, Legal);
1548 setOperationAction(ISD::MUL, MVT::v8i64, Legal);
1550 // Custom lower several nodes.
1551 for (MVT VT : MVT::vector_valuetypes()) {
1552 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1554 setOperationAction(ISD::AND, VT, Legal);
1555 setOperationAction(ISD::OR, VT, Legal);
1556 setOperationAction(ISD::XOR, VT, Legal);
1558 if (EltSize >= 32 && VT.getSizeInBits() <= 512) {
1559 setOperationAction(ISD::MGATHER, VT, Custom);
1560 setOperationAction(ISD::MSCATTER, VT, Custom);
1562 // Extract subvector is special because the value type
1563 // (result) is 256/128-bit but the source is 512-bit wide.
1564 if (VT.is128BitVector() || VT.is256BitVector()) {
1565 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1567 if (VT.getVectorElementType() == MVT::i1)
1568 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal);
1570 // Do not attempt to custom lower other non-512-bit vectors
1571 if (!VT.is512BitVector())
1574 if (EltSize >= 32) {
1575 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1576 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1577 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1578 setOperationAction(ISD::VSELECT, VT, Legal);
1579 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1580 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1581 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1582 setOperationAction(ISD::MLOAD, VT, Legal);
1583 setOperationAction(ISD::MSTORE, VT, Legal);
1586 for (auto VT : { MVT::v64i8, MVT::v32i16, MVT::v16i32 }) {
1587 setOperationAction(ISD::SELECT, VT, Promote);
1588 AddPromotedToType (ISD::SELECT, VT, MVT::v8i64);
1592 if (!Subtarget->useSoftFloat() && Subtarget->hasBWI()) {
1593 addRegisterClass(MVT::v32i16, &X86::VR512RegClass);
1594 addRegisterClass(MVT::v64i8, &X86::VR512RegClass);
1596 addRegisterClass(MVT::v32i1, &X86::VK32RegClass);
1597 addRegisterClass(MVT::v64i1, &X86::VK64RegClass);
1599 setOperationAction(ISD::LOAD, MVT::v32i16, Legal);
1600 setOperationAction(ISD::LOAD, MVT::v64i8, Legal);
1601 setOperationAction(ISD::SETCC, MVT::v32i1, Custom);
1602 setOperationAction(ISD::SETCC, MVT::v64i1, Custom);
1603 setOperationAction(ISD::ADD, MVT::v32i16, Legal);
1604 setOperationAction(ISD::ADD, MVT::v64i8, Legal);
1605 setOperationAction(ISD::SUB, MVT::v32i16, Legal);
1606 setOperationAction(ISD::SUB, MVT::v64i8, Legal);
1607 setOperationAction(ISD::MUL, MVT::v32i16, Legal);
1608 setOperationAction(ISD::MULHS, MVT::v32i16, Legal);
1609 setOperationAction(ISD::MULHU, MVT::v32i16, Legal);
1610 setOperationAction(ISD::CONCAT_VECTORS, MVT::v32i1, Legal);
1611 setOperationAction(ISD::CONCAT_VECTORS, MVT::v64i1, Legal);
1612 setOperationAction(ISD::CONCAT_VECTORS, MVT::v32i16, Custom);
1613 setOperationAction(ISD::CONCAT_VECTORS, MVT::v64i8, Custom);
1614 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v32i1, Custom);
1615 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v64i1, Custom);
1616 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v32i16, Custom);
1617 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v64i8, Custom);
1618 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v32i16, Custom);
1619 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v64i8, Custom);
1620 setOperationAction(ISD::SELECT, MVT::v32i1, Custom);
1621 setOperationAction(ISD::SELECT, MVT::v64i1, Custom);
1622 setOperationAction(ISD::SIGN_EXTEND, MVT::v32i8, Custom);
1623 setOperationAction(ISD::ZERO_EXTEND, MVT::v32i8, Custom);
1624 setOperationAction(ISD::SIGN_EXTEND, MVT::v32i16, Custom);
1625 setOperationAction(ISD::ZERO_EXTEND, MVT::v32i16, Custom);
1626 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v32i16, Custom);
1627 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v64i8, Custom);
1628 setOperationAction(ISD::SIGN_EXTEND, MVT::v64i8, Custom);
1629 setOperationAction(ISD::ZERO_EXTEND, MVT::v64i8, Custom);
1630 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v32i1, Custom);
1631 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v64i1, Custom);
1632 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v32i16, Custom);
1633 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v64i8, Custom);
1634 setOperationAction(ISD::VSELECT, MVT::v32i16, Legal);
1635 setOperationAction(ISD::VSELECT, MVT::v64i8, Legal);
1636 setOperationAction(ISD::TRUNCATE, MVT::v32i1, Custom);
1637 setOperationAction(ISD::TRUNCATE, MVT::v64i1, Custom);
1638 setOperationAction(ISD::TRUNCATE, MVT::v32i8, Custom);
1639 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v32i1, Custom);
1640 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v64i1, Custom);
1642 setOperationAction(ISD::SMAX, MVT::v64i8, Legal);
1643 setOperationAction(ISD::SMAX, MVT::v32i16, Legal);
1644 setOperationAction(ISD::UMAX, MVT::v64i8, Legal);
1645 setOperationAction(ISD::UMAX, MVT::v32i16, Legal);
1646 setOperationAction(ISD::SMIN, MVT::v64i8, Legal);
1647 setOperationAction(ISD::SMIN, MVT::v32i16, Legal);
1648 setOperationAction(ISD::UMIN, MVT::v64i8, Legal);
1649 setOperationAction(ISD::UMIN, MVT::v32i16, Legal);
1651 setTruncStoreAction(MVT::v32i16, MVT::v32i8, Legal);
1652 setTruncStoreAction(MVT::v16i16, MVT::v16i8, Legal);
1653 if (Subtarget->hasVLX())
1654 setTruncStoreAction(MVT::v8i16, MVT::v8i8, Legal);
1656 if (Subtarget->hasCDI()) {
1657 setOperationAction(ISD::CTLZ, MVT::v32i16, Custom);
1658 setOperationAction(ISD::CTLZ, MVT::v64i8, Custom);
1659 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v32i16, Custom);
1660 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v64i8, Custom);
1663 for (auto VT : { MVT::v64i8, MVT::v32i16 }) {
1664 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1665 setOperationAction(ISD::VSELECT, VT, Legal);
1669 if (!Subtarget->useSoftFloat() && Subtarget->hasVLX()) {
1670 addRegisterClass(MVT::v4i1, &X86::VK4RegClass);
1671 addRegisterClass(MVT::v2i1, &X86::VK2RegClass);
1673 setOperationAction(ISD::SETCC, MVT::v4i1, Custom);
1674 setOperationAction(ISD::SETCC, MVT::v2i1, Custom);
1675 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i1, Custom);
1676 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i1, Custom);
1677 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v8i1, Custom);
1678 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v4i1, Custom);
1679 setOperationAction(ISD::SELECT, MVT::v4i1, Custom);
1680 setOperationAction(ISD::SELECT, MVT::v2i1, Custom);
1681 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i1, Custom);
1682 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i1, Custom);
1683 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i1, Custom);
1684 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i1, Custom);
1686 setOperationAction(ISD::AND, MVT::v8i32, Legal);
1687 setOperationAction(ISD::OR, MVT::v8i32, Legal);
1688 setOperationAction(ISD::XOR, MVT::v8i32, Legal);
1689 setOperationAction(ISD::AND, MVT::v4i32, Legal);
1690 setOperationAction(ISD::OR, MVT::v4i32, Legal);
1691 setOperationAction(ISD::XOR, MVT::v4i32, Legal);
1692 setOperationAction(ISD::SRA, MVT::v2i64, Custom);
1693 setOperationAction(ISD::SRA, MVT::v4i64, Custom);
1695 setOperationAction(ISD::SMAX, MVT::v2i64, Legal);
1696 setOperationAction(ISD::SMAX, MVT::v4i64, Legal);
1697 setOperationAction(ISD::UMAX, MVT::v2i64, Legal);
1698 setOperationAction(ISD::UMAX, MVT::v4i64, Legal);
1699 setOperationAction(ISD::SMIN, MVT::v2i64, Legal);
1700 setOperationAction(ISD::SMIN, MVT::v4i64, Legal);
1701 setOperationAction(ISD::UMIN, MVT::v2i64, Legal);
1702 setOperationAction(ISD::UMIN, MVT::v4i64, Legal);
1705 // We want to custom lower some of our intrinsics.
1706 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
1707 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
1708 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
1709 if (!Subtarget->is64Bit())
1710 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i64, Custom);
1712 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't
1713 // handle type legalization for these operations here.
1715 // FIXME: We really should do custom legalization for addition and
1716 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better
1717 // than generic legalization for 64-bit multiplication-with-overflow, though.
1718 for (auto VT : { MVT::i8, MVT::i16, MVT::i32, MVT::i64 }) {
1719 if (VT == MVT::i64 && !Subtarget->is64Bit())
1721 // Add/Sub/Mul with overflow operations are custom lowered.
1722 setOperationAction(ISD::SADDO, VT, Custom);
1723 setOperationAction(ISD::UADDO, VT, Custom);
1724 setOperationAction(ISD::SSUBO, VT, Custom);
1725 setOperationAction(ISD::USUBO, VT, Custom);
1726 setOperationAction(ISD::SMULO, VT, Custom);
1727 setOperationAction(ISD::UMULO, VT, Custom);
1730 if (!Subtarget->is64Bit()) {
1731 // These libcalls are not available in 32-bit.
1732 setLibcallName(RTLIB::SHL_I128, nullptr);
1733 setLibcallName(RTLIB::SRL_I128, nullptr);
1734 setLibcallName(RTLIB::SRA_I128, nullptr);
1737 // Combine sin / cos into one node or libcall if possible.
1738 if (Subtarget->hasSinCos()) {
1739 setLibcallName(RTLIB::SINCOS_F32, "sincosf");
1740 setLibcallName(RTLIB::SINCOS_F64, "sincos");
1741 if (Subtarget->isTargetDarwin()) {
1742 // For MacOSX, we don't want the normal expansion of a libcall to sincos.
1743 // We want to issue a libcall to __sincos_stret to avoid memory traffic.
1744 setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
1745 setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
1749 if (Subtarget->isTargetWin64()) {
1750 setOperationAction(ISD::SDIV, MVT::i128, Custom);
1751 setOperationAction(ISD::UDIV, MVT::i128, Custom);
1752 setOperationAction(ISD::SREM, MVT::i128, Custom);
1753 setOperationAction(ISD::UREM, MVT::i128, Custom);
1754 setOperationAction(ISD::SDIVREM, MVT::i128, Custom);
1755 setOperationAction(ISD::UDIVREM, MVT::i128, Custom);
1758 // We have target-specific dag combine patterns for the following nodes:
1759 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
1760 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
1761 setTargetDAGCombine(ISD::BITCAST);
1762 setTargetDAGCombine(ISD::VSELECT);
1763 setTargetDAGCombine(ISD::SELECT);
1764 setTargetDAGCombine(ISD::SHL);
1765 setTargetDAGCombine(ISD::SRA);
1766 setTargetDAGCombine(ISD::SRL);
1767 setTargetDAGCombine(ISD::OR);
1768 setTargetDAGCombine(ISD::AND);
1769 setTargetDAGCombine(ISD::ADD);
1770 setTargetDAGCombine(ISD::FADD);
1771 setTargetDAGCombine(ISD::FSUB);
1772 setTargetDAGCombine(ISD::FMA);
1773 setTargetDAGCombine(ISD::SUB);
1774 setTargetDAGCombine(ISD::LOAD);
1775 setTargetDAGCombine(ISD::MLOAD);
1776 setTargetDAGCombine(ISD::STORE);
1777 setTargetDAGCombine(ISD::MSTORE);
1778 setTargetDAGCombine(ISD::ZERO_EXTEND);
1779 setTargetDAGCombine(ISD::ANY_EXTEND);
1780 setTargetDAGCombine(ISD::SIGN_EXTEND);
1781 setTargetDAGCombine(ISD::SIGN_EXTEND_INREG);
1782 setTargetDAGCombine(ISD::SINT_TO_FP);
1783 setTargetDAGCombine(ISD::UINT_TO_FP);
1784 setTargetDAGCombine(ISD::SETCC);
1785 setTargetDAGCombine(ISD::BUILD_VECTOR);
1786 setTargetDAGCombine(ISD::MUL);
1787 setTargetDAGCombine(ISD::XOR);
1789 computeRegisterProperties(Subtarget->getRegisterInfo());
1791 MaxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
1792 MaxStoresPerMemsetOptSize = 8;
1793 MaxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores
1794 MaxStoresPerMemcpyOptSize = 4;
1795 MaxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores
1796 MaxStoresPerMemmoveOptSize = 4;
1797 setPrefLoopAlignment(4); // 2^4 bytes.
1799 // A predictable cmov does not hurt on an in-order CPU.
1800 // FIXME: Use a CPU attribute to trigger this, not a CPU model.
1801 PredictableSelectIsExpensive = !Subtarget->isAtom();
1802 EnableExtLdPromotion = true;
1803 setPrefFunctionAlignment(4); // 2^4 bytes.
1805 verifyIntrinsicTables();
1808 // This has so far only been implemented for 64-bit MachO.
1809 bool X86TargetLowering::useLoadStackGuardNode() const {
1810 return Subtarget->isTargetMachO() && Subtarget->is64Bit();
1813 TargetLoweringBase::LegalizeTypeAction
1814 X86TargetLowering::getPreferredVectorAction(EVT VT) const {
1815 if (ExperimentalVectorWideningLegalization &&
1816 VT.getVectorNumElements() != 1 &&
1817 VT.getVectorElementType().getSimpleVT() != MVT::i1)
1818 return TypeWidenVector;
1820 return TargetLoweringBase::getPreferredVectorAction(VT);
1823 EVT X86TargetLowering::getSetCCResultType(const DataLayout &DL, LLVMContext &,
1826 return Subtarget->hasAVX512() ? MVT::i1: MVT::i8;
1828 if (VT.isSimple()) {
1829 MVT VVT = VT.getSimpleVT();
1830 const unsigned NumElts = VVT.getVectorNumElements();
1831 const MVT EltVT = VVT.getVectorElementType();
1832 if (VVT.is512BitVector()) {
1833 if (Subtarget->hasAVX512())
1834 if (EltVT == MVT::i32 || EltVT == MVT::i64 ||
1835 EltVT == MVT::f32 || EltVT == MVT::f64)
1837 case 8: return MVT::v8i1;
1838 case 16: return MVT::v16i1;
1840 if (Subtarget->hasBWI())
1841 if (EltVT == MVT::i8 || EltVT == MVT::i16)
1843 case 32: return MVT::v32i1;
1844 case 64: return MVT::v64i1;
1848 if (VVT.is256BitVector() || VVT.is128BitVector()) {
1849 if (Subtarget->hasVLX())
1850 if (EltVT == MVT::i32 || EltVT == MVT::i64 ||
1851 EltVT == MVT::f32 || EltVT == MVT::f64)
1853 case 2: return MVT::v2i1;
1854 case 4: return MVT::v4i1;
1855 case 8: return MVT::v8i1;
1857 if (Subtarget->hasBWI() && Subtarget->hasVLX())
1858 if (EltVT == MVT::i8 || EltVT == MVT::i16)
1860 case 8: return MVT::v8i1;
1861 case 16: return MVT::v16i1;
1862 case 32: return MVT::v32i1;
1867 return VT.changeVectorElementTypeToInteger();
1870 /// Helper for getByValTypeAlignment to determine
1871 /// the desired ByVal argument alignment.
1872 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) {
1875 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1876 if (VTy->getBitWidth() == 128)
1878 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1879 unsigned EltAlign = 0;
1880 getMaxByValAlign(ATy->getElementType(), EltAlign);
1881 if (EltAlign > MaxAlign)
1882 MaxAlign = EltAlign;
1883 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
1884 for (auto *EltTy : STy->elements()) {
1885 unsigned EltAlign = 0;
1886 getMaxByValAlign(EltTy, EltAlign);
1887 if (EltAlign > MaxAlign)
1888 MaxAlign = EltAlign;
1895 /// Return the desired alignment for ByVal aggregate
1896 /// function arguments in the caller parameter area. For X86, aggregates
1897 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
1898 /// are at 4-byte boundaries.
1899 unsigned X86TargetLowering::getByValTypeAlignment(Type *Ty,
1900 const DataLayout &DL) const {
1901 if (Subtarget->is64Bit()) {
1902 // Max of 8 and alignment of type.
1903 unsigned TyAlign = DL.getABITypeAlignment(Ty);
1910 if (Subtarget->hasSSE1())
1911 getMaxByValAlign(Ty, Align);
1915 /// Returns the target specific optimal type for load
1916 /// and store operations as a result of memset, memcpy, and memmove
1917 /// lowering. If DstAlign is zero that means it's safe to destination
1918 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
1919 /// means there isn't a need to check it against alignment requirement,
1920 /// probably because the source does not need to be loaded. If 'IsMemset' is
1921 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
1922 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
1923 /// source is constant so it does not need to be loaded.
1924 /// It returns EVT::Other if the type should be determined using generic
1925 /// target-independent logic.
1927 X86TargetLowering::getOptimalMemOpType(uint64_t Size,
1928 unsigned DstAlign, unsigned SrcAlign,
1929 bool IsMemset, bool ZeroMemset,
1931 MachineFunction &MF) const {
1932 const Function *F = MF.getFunction();
1933 if ((!IsMemset || ZeroMemset) &&
1934 !F->hasFnAttribute(Attribute::NoImplicitFloat)) {
1936 (!Subtarget->isUnalignedMem16Slow() ||
1937 ((DstAlign == 0 || DstAlign >= 16) &&
1938 (SrcAlign == 0 || SrcAlign >= 16)))) {
1940 // FIXME: Check if unaligned 32-byte accesses are slow.
1941 if (Subtarget->hasInt256())
1943 if (Subtarget->hasFp256())
1946 if (Subtarget->hasSSE2())
1948 if (Subtarget->hasSSE1())
1950 } else if (!MemcpyStrSrc && Size >= 8 &&
1951 !Subtarget->is64Bit() &&
1952 Subtarget->hasSSE2()) {
1953 // Do not use f64 to lower memcpy if source is string constant. It's
1954 // better to use i32 to avoid the loads.
1958 // This is a compromise. If we reach here, unaligned accesses may be slow on
1959 // this target. However, creating smaller, aligned accesses could be even
1960 // slower and would certainly be a lot more code.
1961 if (Subtarget->is64Bit() && Size >= 8)
1966 bool X86TargetLowering::isSafeMemOpType(MVT VT) const {
1968 return X86ScalarSSEf32;
1969 else if (VT == MVT::f64)
1970 return X86ScalarSSEf64;
1975 X86TargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
1980 switch (VT.getSizeInBits()) {
1982 // 8-byte and under are always assumed to be fast.
1986 *Fast = !Subtarget->isUnalignedMem16Slow();
1989 *Fast = !Subtarget->isUnalignedMem32Slow();
1991 // TODO: What about AVX-512 (512-bit) accesses?
1994 // Misaligned accesses of any size are always allowed.
1998 /// Return the entry encoding for a jump table in the
1999 /// current function. The returned value is a member of the
2000 /// MachineJumpTableInfo::JTEntryKind enum.
2001 unsigned X86TargetLowering::getJumpTableEncoding() const {
2002 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
2004 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
2005 Subtarget->isPICStyleGOT())
2006 return MachineJumpTableInfo::EK_Custom32;
2008 // Otherwise, use the normal jump table encoding heuristics.
2009 return TargetLowering::getJumpTableEncoding();
2012 bool X86TargetLowering::useSoftFloat() const {
2013 return Subtarget->useSoftFloat();
2017 X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
2018 const MachineBasicBlock *MBB,
2019 unsigned uid,MCContext &Ctx) const{
2020 assert(MBB->getParent()->getTarget().getRelocationModel() == Reloc::PIC_ &&
2021 Subtarget->isPICStyleGOT());
2022 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
2024 return MCSymbolRefExpr::create(MBB->getSymbol(),
2025 MCSymbolRefExpr::VK_GOTOFF, Ctx);
2028 /// Returns relocation base for the given PIC jumptable.
2029 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
2030 SelectionDAG &DAG) const {
2031 if (!Subtarget->is64Bit())
2032 // This doesn't have SDLoc associated with it, but is not really the
2033 // same as a Register.
2034 return DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(),
2035 getPointerTy(DAG.getDataLayout()));
2039 /// This returns the relocation base for the given PIC jumptable,
2040 /// the same as getPICJumpTableRelocBase, but as an MCExpr.
2041 const MCExpr *X86TargetLowering::
2042 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
2043 MCContext &Ctx) const {
2044 // X86-64 uses RIP relative addressing based on the jump table label.
2045 if (Subtarget->isPICStyleRIPRel())
2046 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
2048 // Otherwise, the reference is relative to the PIC base.
2049 return MCSymbolRefExpr::create(MF->getPICBaseSymbol(), Ctx);
2052 std::pair<const TargetRegisterClass *, uint8_t>
2053 X86TargetLowering::findRepresentativeClass(const TargetRegisterInfo *TRI,
2055 const TargetRegisterClass *RRC = nullptr;
2057 switch (VT.SimpleTy) {
2059 return TargetLowering::findRepresentativeClass(TRI, VT);
2060 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
2061 RRC = Subtarget->is64Bit() ? &X86::GR64RegClass : &X86::GR32RegClass;
2064 RRC = &X86::VR64RegClass;
2066 case MVT::f32: case MVT::f64:
2067 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
2068 case MVT::v4f32: case MVT::v2f64:
2069 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32:
2071 RRC = &X86::VR128RegClass;
2074 return std::make_pair(RRC, Cost);
2077 bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace,
2078 unsigned &Offset) const {
2079 if (!Subtarget->isTargetLinux())
2082 if (Subtarget->is64Bit()) {
2083 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs:
2085 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
2097 Value *X86TargetLowering::getSafeStackPointerLocation(IRBuilder<> &IRB) const {
2098 if (!Subtarget->isTargetAndroid())
2099 return TargetLowering::getSafeStackPointerLocation(IRB);
2101 // Android provides a fixed TLS slot for the SafeStack pointer. See the
2102 // definition of TLS_SLOT_SAFESTACK in
2103 // https://android.googlesource.com/platform/bionic/+/master/libc/private/bionic_tls.h
2104 unsigned AddressSpace, Offset;
2105 if (Subtarget->is64Bit()) {
2106 // %fs:0x48, unless we're using a Kernel code model, in which case it's %gs:
2108 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
2118 return ConstantExpr::getIntToPtr(
2119 ConstantInt::get(Type::getInt32Ty(IRB.getContext()), Offset),
2120 Type::getInt8PtrTy(IRB.getContext())->getPointerTo(AddressSpace));
2123 bool X86TargetLowering::isNoopAddrSpaceCast(unsigned SrcAS,
2124 unsigned DestAS) const {
2125 assert(SrcAS != DestAS && "Expected different address spaces!");
2127 return SrcAS < 256 && DestAS < 256;
2130 //===----------------------------------------------------------------------===//
2131 // Return Value Calling Convention Implementation
2132 //===----------------------------------------------------------------------===//
2134 #include "X86GenCallingConv.inc"
2136 bool X86TargetLowering::CanLowerReturn(
2137 CallingConv::ID CallConv, MachineFunction &MF, bool isVarArg,
2138 const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context) const {
2139 SmallVector<CCValAssign, 16> RVLocs;
2140 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
2141 return CCInfo.CheckReturn(Outs, RetCC_X86);
2144 const MCPhysReg *X86TargetLowering::getScratchRegisters(CallingConv::ID) const {
2145 static const MCPhysReg ScratchRegs[] = { X86::R11, 0 };
2150 X86TargetLowering::LowerReturn(SDValue Chain,
2151 CallingConv::ID CallConv, bool isVarArg,
2152 const SmallVectorImpl<ISD::OutputArg> &Outs,
2153 const SmallVectorImpl<SDValue> &OutVals,
2154 SDLoc dl, SelectionDAG &DAG) const {
2155 MachineFunction &MF = DAG.getMachineFunction();
2156 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2158 SmallVector<CCValAssign, 16> RVLocs;
2159 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, *DAG.getContext());
2160 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
2163 SmallVector<SDValue, 6> RetOps;
2164 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
2165 // Operand #1 = Bytes To Pop
2166 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(), dl,
2169 // Copy the result values into the output registers.
2170 for (unsigned i = 0; i != RVLocs.size(); ++i) {
2171 CCValAssign &VA = RVLocs[i];
2172 assert(VA.isRegLoc() && "Can only return in registers!");
2173 SDValue ValToCopy = OutVals[i];
2174 EVT ValVT = ValToCopy.getValueType();
2176 // Promote values to the appropriate types.
2177 if (VA.getLocInfo() == CCValAssign::SExt)
2178 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy);
2179 else if (VA.getLocInfo() == CCValAssign::ZExt)
2180 ValToCopy = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ValToCopy);
2181 else if (VA.getLocInfo() == CCValAssign::AExt) {
2182 if (ValVT.isVector() && ValVT.getScalarType() == MVT::i1)
2183 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy);
2185 ValToCopy = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ValToCopy);
2187 else if (VA.getLocInfo() == CCValAssign::BCvt)
2188 ValToCopy = DAG.getBitcast(VA.getLocVT(), ValToCopy);
2190 assert(VA.getLocInfo() != CCValAssign::FPExt &&
2191 "Unexpected FP-extend for return value.");
2193 // If this is x86-64, and we disabled SSE, we can't return FP values,
2194 // or SSE or MMX vectors.
2195 if ((ValVT == MVT::f32 || ValVT == MVT::f64 ||
2196 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) &&
2197 (Subtarget->is64Bit() && !Subtarget->hasSSE1())) {
2198 report_fatal_error("SSE register return with SSE disabled");
2200 // Likewise we can't return F64 values with SSE1 only. gcc does so, but
2201 // llvm-gcc has never done it right and no one has noticed, so this
2202 // should be OK for now.
2203 if (ValVT == MVT::f64 &&
2204 (Subtarget->is64Bit() && !Subtarget->hasSSE2()))
2205 report_fatal_error("SSE2 register return with SSE2 disabled");
2207 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
2208 // the RET instruction and handled by the FP Stackifier.
2209 if (VA.getLocReg() == X86::FP0 ||
2210 VA.getLocReg() == X86::FP1) {
2211 // If this is a copy from an xmm register to ST(0), use an FPExtend to
2212 // change the value to the FP stack register class.
2213 if (isScalarFPTypeInSSEReg(VA.getValVT()))
2214 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
2215 RetOps.push_back(ValToCopy);
2216 // Don't emit a copytoreg.
2220 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
2221 // which is returned in RAX / RDX.
2222 if (Subtarget->is64Bit()) {
2223 if (ValVT == MVT::x86mmx) {
2224 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
2225 ValToCopy = DAG.getBitcast(MVT::i64, ValToCopy);
2226 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
2228 // If we don't have SSE2 available, convert to v4f32 so the generated
2229 // register is legal.
2230 if (!Subtarget->hasSSE2())
2231 ValToCopy = DAG.getBitcast(MVT::v4f32, ValToCopy);
2236 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
2237 Flag = Chain.getValue(1);
2238 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2241 // All x86 ABIs require that for returning structs by value we copy
2242 // the sret argument into %rax/%eax (depending on ABI) for the return.
2243 // We saved the argument into a virtual register in the entry block,
2244 // so now we copy the value out and into %rax/%eax.
2246 // Checking Function.hasStructRetAttr() here is insufficient because the IR
2247 // may not have an explicit sret argument. If FuncInfo.CanLowerReturn is
2248 // false, then an sret argument may be implicitly inserted in the SelDAG. In
2249 // either case FuncInfo->setSRetReturnReg() will have been called.
2250 if (unsigned SRetReg = FuncInfo->getSRetReturnReg()) {
2251 SDValue Val = DAG.getCopyFromReg(Chain, dl, SRetReg,
2252 getPointerTy(MF.getDataLayout()));
2255 = (Subtarget->is64Bit() && !Subtarget->isTarget64BitILP32()) ?
2256 X86::RAX : X86::EAX;
2257 Chain = DAG.getCopyToReg(Chain, dl, RetValReg, Val, Flag);
2258 Flag = Chain.getValue(1);
2260 // RAX/EAX now acts like a return value.
2262 DAG.getRegister(RetValReg, getPointerTy(DAG.getDataLayout())));
2265 RetOps[0] = Chain; // Update chain.
2267 // Add the flag if we have it.
2269 RetOps.push_back(Flag);
2271 return DAG.getNode(X86ISD::RET_FLAG, dl, MVT::Other, RetOps);
2274 bool X86TargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
2275 if (N->getNumValues() != 1)
2277 if (!N->hasNUsesOfValue(1, 0))
2280 SDValue TCChain = Chain;
2281 SDNode *Copy = *N->use_begin();
2282 if (Copy->getOpcode() == ISD::CopyToReg) {
2283 // If the copy has a glue operand, we conservatively assume it isn't safe to
2284 // perform a tail call.
2285 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
2287 TCChain = Copy->getOperand(0);
2288 } else if (Copy->getOpcode() != ISD::FP_EXTEND)
2291 bool HasRet = false;
2292 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
2294 if (UI->getOpcode() != X86ISD::RET_FLAG)
2296 // If we are returning more than one value, we can definitely
2297 // not make a tail call see PR19530
2298 if (UI->getNumOperands() > 4)
2300 if (UI->getNumOperands() == 4 &&
2301 UI->getOperand(UI->getNumOperands()-1).getValueType() != MVT::Glue)
2314 X86TargetLowering::getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT,
2315 ISD::NodeType ExtendKind) const {
2317 // TODO: Is this also valid on 32-bit?
2318 if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND)
2319 ReturnMVT = MVT::i8;
2321 ReturnMVT = MVT::i32;
2323 EVT MinVT = getRegisterType(Context, ReturnMVT);
2324 return VT.bitsLT(MinVT) ? MinVT : VT;
2327 /// Lower the result values of a call into the
2328 /// appropriate copies out of appropriate physical registers.
2331 X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
2332 CallingConv::ID CallConv, bool isVarArg,
2333 const SmallVectorImpl<ISD::InputArg> &Ins,
2334 SDLoc dl, SelectionDAG &DAG,
2335 SmallVectorImpl<SDValue> &InVals) const {
2337 // Assign locations to each value returned by this call.
2338 SmallVector<CCValAssign, 16> RVLocs;
2339 bool Is64Bit = Subtarget->is64Bit();
2340 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
2342 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
2344 // Copy all of the result registers out of their specified physreg.
2345 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
2346 CCValAssign &VA = RVLocs[i];
2347 EVT CopyVT = VA.getLocVT();
2349 // If this is x86-64, and we disabled SSE, we can't return FP values
2350 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
2351 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) {
2352 report_fatal_error("SSE register return with SSE disabled");
2355 // If we prefer to use the value in xmm registers, copy it out as f80 and
2356 // use a truncate to move it from fp stack reg to xmm reg.
2357 bool RoundAfterCopy = false;
2358 if ((VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1) &&
2359 isScalarFPTypeInSSEReg(VA.getValVT())) {
2361 RoundAfterCopy = (CopyVT != VA.getLocVT());
2364 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
2365 CopyVT, InFlag).getValue(1);
2366 SDValue Val = Chain.getValue(0);
2369 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
2370 // This truncation won't change the value.
2371 DAG.getIntPtrConstant(1, dl));
2373 if (VA.isExtInLoc() && VA.getValVT().getScalarType() == MVT::i1)
2374 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
2376 InFlag = Chain.getValue(2);
2377 InVals.push_back(Val);
2383 //===----------------------------------------------------------------------===//
2384 // C & StdCall & Fast Calling Convention implementation
2385 //===----------------------------------------------------------------------===//
2386 // StdCall calling convention seems to be standard for many Windows' API
2387 // routines and around. It differs from C calling convention just a little:
2388 // callee should clean up the stack, not caller. Symbols should be also
2389 // decorated in some fancy way :) It doesn't support any vector arguments.
2390 // For info on fast calling convention see Fast Calling Convention (tail call)
2391 // implementation LowerX86_32FastCCCallTo.
2393 /// CallIsStructReturn - Determines whether a call uses struct return
2395 enum StructReturnType {
2400 static StructReturnType
2401 callIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
2403 return NotStructReturn;
2405 const ISD::ArgFlagsTy &Flags = Outs[0].Flags;
2406 if (!Flags.isSRet())
2407 return NotStructReturn;
2408 if (Flags.isInReg())
2409 return RegStructReturn;
2410 return StackStructReturn;
2413 /// Determines whether a function uses struct return semantics.
2414 static StructReturnType
2415 argsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
2417 return NotStructReturn;
2419 const ISD::ArgFlagsTy &Flags = Ins[0].Flags;
2420 if (!Flags.isSRet())
2421 return NotStructReturn;
2422 if (Flags.isInReg())
2423 return RegStructReturn;
2424 return StackStructReturn;
2427 /// Make a copy of an aggregate at address specified by "Src" to address
2428 /// "Dst" with size and alignment information specified by the specific
2429 /// parameter attribute. The copy will be passed as a byval function parameter.
2431 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
2432 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
2434 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), dl, MVT::i32);
2436 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
2437 /*isVolatile*/false, /*AlwaysInline=*/true,
2438 /*isTailCall*/false,
2439 MachinePointerInfo(), MachinePointerInfo());
2442 /// Return true if the calling convention is one that we can guarantee TCO for.
2443 static bool canGuaranteeTCO(CallingConv::ID CC) {
2444 return (CC == CallingConv::Fast || CC == CallingConv::GHC ||
2445 CC == CallingConv::HiPE || CC == CallingConv::HHVM);
2448 /// Return true if we might ever do TCO for calls with this calling convention.
2449 static bool mayTailCallThisCC(CallingConv::ID CC) {
2451 // C calling conventions:
2452 case CallingConv::C:
2453 case CallingConv::X86_64_Win64:
2454 case CallingConv::X86_64_SysV:
2455 // Callee pop conventions:
2456 case CallingConv::X86_ThisCall:
2457 case CallingConv::X86_StdCall:
2458 case CallingConv::X86_VectorCall:
2459 case CallingConv::X86_FastCall:
2462 return canGuaranteeTCO(CC);
2466 /// Return true if the function is being made into a tailcall target by
2467 /// changing its ABI.
2468 static bool shouldGuaranteeTCO(CallingConv::ID CC, bool GuaranteedTailCallOpt) {
2469 return GuaranteedTailCallOpt && canGuaranteeTCO(CC);
2472 bool X86TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
2474 CI->getParent()->getParent()->getFnAttribute("disable-tail-calls");
2475 if (!CI->isTailCall() || Attr.getValueAsString() == "true")
2479 CallingConv::ID CalleeCC = CS.getCallingConv();
2480 if (!mayTailCallThisCC(CalleeCC))
2487 X86TargetLowering::LowerMemArgument(SDValue Chain,
2488 CallingConv::ID CallConv,
2489 const SmallVectorImpl<ISD::InputArg> &Ins,
2490 SDLoc dl, SelectionDAG &DAG,
2491 const CCValAssign &VA,
2492 MachineFrameInfo *MFI,
2494 // Create the nodes corresponding to a load from this parameter slot.
2495 ISD::ArgFlagsTy Flags = Ins[i].Flags;
2496 bool AlwaysUseMutable = shouldGuaranteeTCO(
2497 CallConv, DAG.getTarget().Options.GuaranteedTailCallOpt);
2498 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
2501 // If value is passed by pointer we have address passed instead of the value
2503 bool ExtendedInMem = VA.isExtInLoc() &&
2504 VA.getValVT().getScalarType() == MVT::i1;
2506 if (VA.getLocInfo() == CCValAssign::Indirect || ExtendedInMem)
2507 ValVT = VA.getLocVT();
2509 ValVT = VA.getValVT();
2511 // FIXME: For now, all byval parameter objects are marked mutable. This can be
2512 // changed with more analysis.
2513 // In case of tail call optimization mark all arguments mutable. Since they
2514 // could be overwritten by lowering of arguments in case of a tail call.
2515 if (Flags.isByVal()) {
2516 unsigned Bytes = Flags.getByValSize();
2517 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects.
2518 int FI = MFI->CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable);
2519 return DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
2521 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
2522 VA.getLocMemOffset(), isImmutable);
2523 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
2524 SDValue Val = DAG.getLoad(
2525 ValVT, dl, Chain, FIN,
2526 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI), false,
2528 return ExtendedInMem ?
2529 DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val) : Val;
2533 // FIXME: Get this from tablegen.
2534 static ArrayRef<MCPhysReg> get64BitArgumentGPRs(CallingConv::ID CallConv,
2535 const X86Subtarget *Subtarget) {
2536 assert(Subtarget->is64Bit());
2538 if (Subtarget->isCallingConvWin64(CallConv)) {
2539 static const MCPhysReg GPR64ArgRegsWin64[] = {
2540 X86::RCX, X86::RDX, X86::R8, X86::R9
2542 return makeArrayRef(std::begin(GPR64ArgRegsWin64), std::end(GPR64ArgRegsWin64));
2545 static const MCPhysReg GPR64ArgRegs64Bit[] = {
2546 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
2548 return makeArrayRef(std::begin(GPR64ArgRegs64Bit), std::end(GPR64ArgRegs64Bit));
2551 // FIXME: Get this from tablegen.
2552 static ArrayRef<MCPhysReg> get64BitArgumentXMMs(MachineFunction &MF,
2553 CallingConv::ID CallConv,
2554 const X86Subtarget *Subtarget) {
2555 assert(Subtarget->is64Bit());
2556 if (Subtarget->isCallingConvWin64(CallConv)) {
2557 // The XMM registers which might contain var arg parameters are shadowed
2558 // in their paired GPR. So we only need to save the GPR to their home
2560 // TODO: __vectorcall will change this.
2564 const Function *Fn = MF.getFunction();
2565 bool NoImplicitFloatOps = Fn->hasFnAttribute(Attribute::NoImplicitFloat);
2566 bool isSoftFloat = Subtarget->useSoftFloat();
2567 assert(!(isSoftFloat && NoImplicitFloatOps) &&
2568 "SSE register cannot be used when SSE is disabled!");
2569 if (isSoftFloat || NoImplicitFloatOps || !Subtarget->hasSSE1())
2570 // Kernel mode asks for SSE to be disabled, so there are no XMM argument
2574 static const MCPhysReg XMMArgRegs64Bit[] = {
2575 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2576 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2578 return makeArrayRef(std::begin(XMMArgRegs64Bit), std::end(XMMArgRegs64Bit));
2581 SDValue X86TargetLowering::LowerFormalArguments(
2582 SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
2583 const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc dl, SelectionDAG &DAG,
2584 SmallVectorImpl<SDValue> &InVals) const {
2585 MachineFunction &MF = DAG.getMachineFunction();
2586 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2587 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
2589 const Function* Fn = MF.getFunction();
2590 if (Fn->hasExternalLinkage() &&
2591 Subtarget->isTargetCygMing() &&
2592 Fn->getName() == "main")
2593 FuncInfo->setForceFramePointer(true);
2595 MachineFrameInfo *MFI = MF.getFrameInfo();
2596 bool Is64Bit = Subtarget->is64Bit();
2597 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2599 assert(!(isVarArg && canGuaranteeTCO(CallConv)) &&
2600 "Var args not supported with calling convention fastcc, ghc or hipe");
2602 // Assign locations to all of the incoming arguments.
2603 SmallVector<CCValAssign, 16> ArgLocs;
2604 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
2606 // Allocate shadow area for Win64
2608 CCInfo.AllocateStack(32, 8);
2610 CCInfo.AnalyzeFormalArguments(Ins, CC_X86);
2612 unsigned LastVal = ~0U;
2614 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2615 CCValAssign &VA = ArgLocs[i];
2616 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
2618 assert(VA.getValNo() != LastVal &&
2619 "Don't support value assigned to multiple locs yet");
2621 LastVal = VA.getValNo();
2623 if (VA.isRegLoc()) {
2624 EVT RegVT = VA.getLocVT();
2625 const TargetRegisterClass *RC;
2626 if (RegVT == MVT::i32)
2627 RC = &X86::GR32RegClass;
2628 else if (Is64Bit && RegVT == MVT::i64)
2629 RC = &X86::GR64RegClass;
2630 else if (RegVT == MVT::f32)
2631 RC = &X86::FR32RegClass;
2632 else if (RegVT == MVT::f64)
2633 RC = &X86::FR64RegClass;
2634 else if (RegVT.is512BitVector())
2635 RC = &X86::VR512RegClass;
2636 else if (RegVT.is256BitVector())
2637 RC = &X86::VR256RegClass;
2638 else if (RegVT.is128BitVector())
2639 RC = &X86::VR128RegClass;
2640 else if (RegVT == MVT::x86mmx)
2641 RC = &X86::VR64RegClass;
2642 else if (RegVT == MVT::i1)
2643 RC = &X86::VK1RegClass;
2644 else if (RegVT == MVT::v8i1)
2645 RC = &X86::VK8RegClass;
2646 else if (RegVT == MVT::v16i1)
2647 RC = &X86::VK16RegClass;
2648 else if (RegVT == MVT::v32i1)
2649 RC = &X86::VK32RegClass;
2650 else if (RegVT == MVT::v64i1)
2651 RC = &X86::VK64RegClass;
2653 llvm_unreachable("Unknown argument type!");
2655 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2656 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
2658 // If this is an 8 or 16-bit value, it is really passed promoted to 32
2659 // bits. Insert an assert[sz]ext to capture this, then truncate to the
2661 if (VA.getLocInfo() == CCValAssign::SExt)
2662 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
2663 DAG.getValueType(VA.getValVT()));
2664 else if (VA.getLocInfo() == CCValAssign::ZExt)
2665 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
2666 DAG.getValueType(VA.getValVT()));
2667 else if (VA.getLocInfo() == CCValAssign::BCvt)
2668 ArgValue = DAG.getBitcast(VA.getValVT(), ArgValue);
2670 if (VA.isExtInLoc()) {
2671 // Handle MMX values passed in XMM regs.
2672 if (RegVT.isVector() && VA.getValVT().getScalarType() != MVT::i1)
2673 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(), ArgValue);
2675 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
2678 assert(VA.isMemLoc());
2679 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
2682 // If value is passed via pointer - do a load.
2683 if (VA.getLocInfo() == CCValAssign::Indirect)
2684 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue,
2685 MachinePointerInfo(), false, false, false, 0);
2687 InVals.push_back(ArgValue);
2690 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2691 // All x86 ABIs require that for returning structs by value we copy the
2692 // sret argument into %rax/%eax (depending on ABI) for the return. Save
2693 // the argument into a virtual register so that we can access it from the
2695 if (Ins[i].Flags.isSRet()) {
2696 unsigned Reg = FuncInfo->getSRetReturnReg();
2698 MVT PtrTy = getPointerTy(DAG.getDataLayout());
2699 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(PtrTy));
2700 FuncInfo->setSRetReturnReg(Reg);
2702 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[i]);
2703 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
2708 unsigned StackSize = CCInfo.getNextStackOffset();
2709 // Align stack specially for tail calls.
2710 if (shouldGuaranteeTCO(CallConv,
2711 MF.getTarget().Options.GuaranteedTailCallOpt))
2712 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
2714 // If the function takes variable number of arguments, make a frame index for
2715 // the start of the first vararg value... for expansion of llvm.va_start. We
2716 // can skip this if there are no va_start calls.
2717 if (MFI->hasVAStart() &&
2718 (Is64Bit || (CallConv != CallingConv::X86_FastCall &&
2719 CallConv != CallingConv::X86_ThisCall))) {
2720 FuncInfo->setVarArgsFrameIndex(
2721 MFI->CreateFixedObject(1, StackSize, true));
2724 MachineModuleInfo &MMI = MF.getMMI();
2726 // Figure out if XMM registers are in use.
2727 assert(!(Subtarget->useSoftFloat() &&
2728 Fn->hasFnAttribute(Attribute::NoImplicitFloat)) &&
2729 "SSE register cannot be used when SSE is disabled!");
2731 // 64-bit calling conventions support varargs and register parameters, so we
2732 // have to do extra work to spill them in the prologue.
2733 if (Is64Bit && isVarArg && MFI->hasVAStart()) {
2734 // Find the first unallocated argument registers.
2735 ArrayRef<MCPhysReg> ArgGPRs = get64BitArgumentGPRs(CallConv, Subtarget);
2736 ArrayRef<MCPhysReg> ArgXMMs = get64BitArgumentXMMs(MF, CallConv, Subtarget);
2737 unsigned NumIntRegs = CCInfo.getFirstUnallocated(ArgGPRs);
2738 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(ArgXMMs);
2739 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) &&
2740 "SSE register cannot be used when SSE is disabled!");
2742 // Gather all the live in physical registers.
2743 SmallVector<SDValue, 6> LiveGPRs;
2744 SmallVector<SDValue, 8> LiveXMMRegs;
2746 for (MCPhysReg Reg : ArgGPRs.slice(NumIntRegs)) {
2747 unsigned GPR = MF.addLiveIn(Reg, &X86::GR64RegClass);
2749 DAG.getCopyFromReg(Chain, dl, GPR, MVT::i64));
2751 if (!ArgXMMs.empty()) {
2752 unsigned AL = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
2753 ALVal = DAG.getCopyFromReg(Chain, dl, AL, MVT::i8);
2754 for (MCPhysReg Reg : ArgXMMs.slice(NumXMMRegs)) {
2755 unsigned XMMReg = MF.addLiveIn(Reg, &X86::VR128RegClass);
2756 LiveXMMRegs.push_back(
2757 DAG.getCopyFromReg(Chain, dl, XMMReg, MVT::v4f32));
2762 // Get to the caller-allocated home save location. Add 8 to account
2763 // for the return address.
2764 int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
2765 FuncInfo->setRegSaveFrameIndex(
2766 MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false));
2767 // Fixup to set vararg frame on shadow area (4 x i64).
2769 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex());
2771 // For X86-64, if there are vararg parameters that are passed via
2772 // registers, then we must store them to their spots on the stack so
2773 // they may be loaded by deferencing the result of va_next.
2774 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8);
2775 FuncInfo->setVarArgsFPOffset(ArgGPRs.size() * 8 + NumXMMRegs * 16);
2776 FuncInfo->setRegSaveFrameIndex(MFI->CreateStackObject(
2777 ArgGPRs.size() * 8 + ArgXMMs.size() * 16, 16, false));
2780 // Store the integer parameter registers.
2781 SmallVector<SDValue, 8> MemOps;
2782 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
2783 getPointerTy(DAG.getDataLayout()));
2784 unsigned Offset = FuncInfo->getVarArgsGPOffset();
2785 for (SDValue Val : LiveGPRs) {
2786 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(DAG.getDataLayout()),
2787 RSFIN, DAG.getIntPtrConstant(Offset, dl));
2789 DAG.getStore(Val.getValue(1), dl, Val, FIN,
2790 MachinePointerInfo::getFixedStack(
2791 DAG.getMachineFunction(),
2792 FuncInfo->getRegSaveFrameIndex(), Offset),
2794 MemOps.push_back(Store);
2798 if (!ArgXMMs.empty() && NumXMMRegs != ArgXMMs.size()) {
2799 // Now store the XMM (fp + vector) parameter registers.
2800 SmallVector<SDValue, 12> SaveXMMOps;
2801 SaveXMMOps.push_back(Chain);
2802 SaveXMMOps.push_back(ALVal);
2803 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2804 FuncInfo->getRegSaveFrameIndex(), dl));
2805 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2806 FuncInfo->getVarArgsFPOffset(), dl));
2807 SaveXMMOps.insert(SaveXMMOps.end(), LiveXMMRegs.begin(),
2809 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
2810 MVT::Other, SaveXMMOps));
2813 if (!MemOps.empty())
2814 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
2817 if (isVarArg && MFI->hasMustTailInVarArgFunc()) {
2818 // Find the largest legal vector type.
2819 MVT VecVT = MVT::Other;
2820 // FIXME: Only some x86_32 calling conventions support AVX512.
2821 if (Subtarget->hasAVX512() &&
2822 (Is64Bit || (CallConv == CallingConv::X86_VectorCall ||
2823 CallConv == CallingConv::Intel_OCL_BI)))
2824 VecVT = MVT::v16f32;
2825 else if (Subtarget->hasAVX())
2827 else if (Subtarget->hasSSE2())
2830 // We forward some GPRs and some vector types.
2831 SmallVector<MVT, 2> RegParmTypes;
2832 MVT IntVT = Is64Bit ? MVT::i64 : MVT::i32;
2833 RegParmTypes.push_back(IntVT);
2834 if (VecVT != MVT::Other)
2835 RegParmTypes.push_back(VecVT);
2837 // Compute the set of forwarded registers. The rest are scratch.
2838 SmallVectorImpl<ForwardedRegister> &Forwards =
2839 FuncInfo->getForwardedMustTailRegParms();
2840 CCInfo.analyzeMustTailForwardedRegisters(Forwards, RegParmTypes, CC_X86);
2842 // Conservatively forward AL on x86_64, since it might be used for varargs.
2843 if (Is64Bit && !CCInfo.isAllocated(X86::AL)) {
2844 unsigned ALVReg = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
2845 Forwards.push_back(ForwardedRegister(ALVReg, X86::AL, MVT::i8));
2848 // Copy all forwards from physical to virtual registers.
2849 for (ForwardedRegister &F : Forwards) {
2850 // FIXME: Can we use a less constrained schedule?
2851 SDValue RegVal = DAG.getCopyFromReg(Chain, dl, F.VReg, F.VT);
2852 F.VReg = MF.getRegInfo().createVirtualRegister(getRegClassFor(F.VT));
2853 Chain = DAG.getCopyToReg(Chain, dl, F.VReg, RegVal);
2857 // Some CCs need callee pop.
2858 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2859 MF.getTarget().Options.GuaranteedTailCallOpt)) {
2860 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything.
2862 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing.
2863 // If this is an sret function, the return should pop the hidden pointer.
2864 if (!Is64Bit && !canGuaranteeTCO(CallConv) &&
2865 !Subtarget->getTargetTriple().isOSMSVCRT() &&
2866 argsAreStructReturn(Ins) == StackStructReturn)
2867 FuncInfo->setBytesToPopOnReturn(4);
2871 // RegSaveFrameIndex is X86-64 only.
2872 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
2873 if (CallConv == CallingConv::X86_FastCall ||
2874 CallConv == CallingConv::X86_ThisCall)
2875 // fastcc functions can't have varargs.
2876 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA);
2879 FuncInfo->setArgumentStackSize(StackSize);
2881 if (MMI.hasWinEHFuncInfo(Fn)) {
2883 int UnwindHelpFI = MFI->CreateStackObject(8, 8, /*isSS=*/false);
2884 SDValue StackSlot = DAG.getFrameIndex(UnwindHelpFI, MVT::i64);
2885 MMI.getWinEHFuncInfo(MF.getFunction()).UnwindHelpFrameIdx = UnwindHelpFI;
2886 SDValue Neg2 = DAG.getConstant(-2, dl, MVT::i64);
2887 Chain = DAG.getStore(Chain, dl, Neg2, StackSlot,
2888 MachinePointerInfo::getFixedStack(
2889 DAG.getMachineFunction(), UnwindHelpFI),
2890 /*isVolatile=*/true,
2891 /*isNonTemporal=*/false, /*Alignment=*/0);
2893 // Functions using Win32 EH are considered to have opaque SP adjustments
2894 // to force local variables to be addressed from the frame or base
2896 MFI->setHasOpaqueSPAdjustment(true);
2904 X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
2905 SDValue StackPtr, SDValue Arg,
2906 SDLoc dl, SelectionDAG &DAG,
2907 const CCValAssign &VA,
2908 ISD::ArgFlagsTy Flags) const {
2909 unsigned LocMemOffset = VA.getLocMemOffset();
2910 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset, dl);
2911 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(DAG.getDataLayout()),
2913 if (Flags.isByVal())
2914 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
2916 return DAG.getStore(
2917 Chain, dl, Arg, PtrOff,
2918 MachinePointerInfo::getStack(DAG.getMachineFunction(), LocMemOffset),
2922 /// Emit a load of return address if tail call
2923 /// optimization is performed and it is required.
2925 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
2926 SDValue &OutRetAddr, SDValue Chain,
2927 bool IsTailCall, bool Is64Bit,
2928 int FPDiff, SDLoc dl) const {
2929 // Adjust the Return address stack slot.
2930 EVT VT = getPointerTy(DAG.getDataLayout());
2931 OutRetAddr = getReturnAddressFrameIndex(DAG);
2933 // Load the "old" Return address.
2934 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(),
2935 false, false, false, 0);
2936 return SDValue(OutRetAddr.getNode(), 1);
2939 /// Emit a store of the return address if tail call
2940 /// optimization is performed and it is required (FPDiff!=0).
2941 static SDValue EmitTailCallStoreRetAddr(SelectionDAG &DAG, MachineFunction &MF,
2942 SDValue Chain, SDValue RetAddrFrIdx,
2943 EVT PtrVT, unsigned SlotSize,
2944 int FPDiff, SDLoc dl) {
2945 // Store the return address to the appropriate stack slot.
2946 if (!FPDiff) return Chain;
2947 // Calculate the new stack slot for the return address.
2948 int NewReturnAddrFI =
2949 MF.getFrameInfo()->CreateFixedObject(SlotSize, (int64_t)FPDiff - SlotSize,
2951 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, PtrVT);
2952 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
2953 MachinePointerInfo::getFixedStack(
2954 DAG.getMachineFunction(), NewReturnAddrFI),
2959 /// Returns a vector_shuffle mask for an movs{s|d}, movd
2960 /// operation of specified width.
2961 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
2963 unsigned NumElems = VT.getVectorNumElements();
2964 SmallVector<int, 8> Mask;
2965 Mask.push_back(NumElems);
2966 for (unsigned i = 1; i != NumElems; ++i)
2968 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
2972 X86TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
2973 SmallVectorImpl<SDValue> &InVals) const {
2974 SelectionDAG &DAG = CLI.DAG;
2976 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
2977 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
2978 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
2979 SDValue Chain = CLI.Chain;
2980 SDValue Callee = CLI.Callee;
2981 CallingConv::ID CallConv = CLI.CallConv;
2982 bool &isTailCall = CLI.IsTailCall;
2983 bool isVarArg = CLI.IsVarArg;
2985 MachineFunction &MF = DAG.getMachineFunction();
2986 bool Is64Bit = Subtarget->is64Bit();
2987 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2988 StructReturnType SR = callIsStructReturn(Outs);
2989 bool IsSibcall = false;
2990 X86MachineFunctionInfo *X86Info = MF.getInfo<X86MachineFunctionInfo>();
2991 auto Attr = MF.getFunction()->getFnAttribute("disable-tail-calls");
2993 if (Attr.getValueAsString() == "true")
2996 if (Subtarget->isPICStyleGOT() &&
2997 !MF.getTarget().Options.GuaranteedTailCallOpt) {
2998 // If we are using a GOT, disable tail calls to external symbols with
2999 // default visibility. Tail calling such a symbol requires using a GOT
3000 // relocation, which forces early binding of the symbol. This breaks code
3001 // that require lazy function symbol resolution. Using musttail or
3002 // GuaranteedTailCallOpt will override this.
3003 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
3004 if (!G || (!G->getGlobal()->hasLocalLinkage() &&
3005 G->getGlobal()->hasDefaultVisibility()))
3009 bool IsMustTail = CLI.CS && CLI.CS->isMustTailCall();
3011 // Force this to be a tail call. The verifier rules are enough to ensure
3012 // that we can lower this successfully without moving the return address
3015 } else if (isTailCall) {
3016 // Check if it's really possible to do a tail call.
3017 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
3018 isVarArg, SR != NotStructReturn,
3019 MF.getFunction()->hasStructRetAttr(), CLI.RetTy,
3020 Outs, OutVals, Ins, DAG);
3022 // Sibcalls are automatically detected tailcalls which do not require
3024 if (!MF.getTarget().Options.GuaranteedTailCallOpt && isTailCall)
3031 assert(!(isVarArg && canGuaranteeTCO(CallConv)) &&
3032 "Var args not supported with calling convention fastcc, ghc or hipe");
3034 // Analyze operands of the call, assigning locations to each operand.
3035 SmallVector<CCValAssign, 16> ArgLocs;
3036 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
3038 // Allocate shadow area for Win64
3040 CCInfo.AllocateStack(32, 8);
3042 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3044 // Get a count of how many bytes are to be pushed on the stack.
3045 unsigned NumBytes = CCInfo.getAlignedCallFrameSize();
3047 // This is a sibcall. The memory operands are available in caller's
3048 // own caller's stack.
3050 else if (MF.getTarget().Options.GuaranteedTailCallOpt &&
3051 canGuaranteeTCO(CallConv))
3052 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
3055 if (isTailCall && !IsSibcall && !IsMustTail) {
3056 // Lower arguments at fp - stackoffset + fpdiff.
3057 unsigned NumBytesCallerPushed = X86Info->getBytesToPopOnReturn();
3059 FPDiff = NumBytesCallerPushed - NumBytes;
3061 // Set the delta of movement of the returnaddr stackslot.
3062 // But only set if delta is greater than previous delta.
3063 if (FPDiff < X86Info->getTCReturnAddrDelta())
3064 X86Info->setTCReturnAddrDelta(FPDiff);
3067 unsigned NumBytesToPush = NumBytes;
3068 unsigned NumBytesToPop = NumBytes;
3070 // If we have an inalloca argument, all stack space has already been allocated
3071 // for us and be right at the top of the stack. We don't support multiple
3072 // arguments passed in memory when using inalloca.
3073 if (!Outs.empty() && Outs.back().Flags.isInAlloca()) {
3075 if (!ArgLocs.back().isMemLoc())
3076 report_fatal_error("cannot use inalloca attribute on a register "
3078 if (ArgLocs.back().getLocMemOffset() != 0)
3079 report_fatal_error("any parameter with the inalloca attribute must be "
3080 "the only memory argument");
3084 Chain = DAG.getCALLSEQ_START(
3085 Chain, DAG.getIntPtrConstant(NumBytesToPush, dl, true), dl);
3087 SDValue RetAddrFrIdx;
3088 // Load return address for tail calls.
3089 if (isTailCall && FPDiff)
3090 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall,
3091 Is64Bit, FPDiff, dl);
3093 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
3094 SmallVector<SDValue, 8> MemOpChains;
3097 // Walk the register/memloc assignments, inserting copies/loads. In the case
3098 // of tail call optimization arguments are handle later.
3099 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
3100 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3101 // Skip inalloca arguments, they have already been written.
3102 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3103 if (Flags.isInAlloca())
3106 CCValAssign &VA = ArgLocs[i];
3107 EVT RegVT = VA.getLocVT();
3108 SDValue Arg = OutVals[i];
3109 bool isByVal = Flags.isByVal();
3111 // Promote the value if needed.
3112 switch (VA.getLocInfo()) {
3113 default: llvm_unreachable("Unknown loc info!");
3114 case CCValAssign::Full: break;
3115 case CCValAssign::SExt:
3116 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
3118 case CCValAssign::ZExt:
3119 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
3121 case CCValAssign::AExt:
3122 if (Arg.getValueType().isVector() &&
3123 Arg.getValueType().getScalarType() == MVT::i1)
3124 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
3125 else if (RegVT.is128BitVector()) {
3126 // Special case: passing MMX values in XMM registers.
3127 Arg = DAG.getBitcast(MVT::i64, Arg);
3128 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
3129 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
3131 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
3133 case CCValAssign::BCvt:
3134 Arg = DAG.getBitcast(RegVT, Arg);
3136 case CCValAssign::Indirect: {
3137 // Store the argument.
3138 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
3139 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
3140 Chain = DAG.getStore(
3141 Chain, dl, Arg, SpillSlot,
3142 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI),
3149 if (VA.isRegLoc()) {
3150 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
3151 if (isVarArg && IsWin64) {
3152 // Win64 ABI requires argument XMM reg to be copied to the corresponding
3153 // shadow reg if callee is a varargs function.
3154 unsigned ShadowReg = 0;
3155 switch (VA.getLocReg()) {
3156 case X86::XMM0: ShadowReg = X86::RCX; break;
3157 case X86::XMM1: ShadowReg = X86::RDX; break;
3158 case X86::XMM2: ShadowReg = X86::R8; break;
3159 case X86::XMM3: ShadowReg = X86::R9; break;
3162 RegsToPass.push_back(std::make_pair(ShadowReg, Arg));
3164 } else if (!IsSibcall && (!isTailCall || isByVal)) {
3165 assert(VA.isMemLoc());
3166 if (!StackPtr.getNode())
3167 StackPtr = DAG.getCopyFromReg(Chain, dl, RegInfo->getStackRegister(),
3168 getPointerTy(DAG.getDataLayout()));
3169 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
3170 dl, DAG, VA, Flags));
3174 if (!MemOpChains.empty())
3175 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
3177 if (Subtarget->isPICStyleGOT()) {
3178 // ELF / PIC requires GOT in the EBX register before function calls via PLT
3181 RegsToPass.push_back(std::make_pair(
3182 unsigned(X86::EBX), DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(),
3183 getPointerTy(DAG.getDataLayout()))));
3185 // If we are tail calling and generating PIC/GOT style code load the
3186 // address of the callee into ECX. The value in ecx is used as target of
3187 // the tail jump. This is done to circumvent the ebx/callee-saved problem
3188 // for tail calls on PIC/GOT architectures. Normally we would just put the
3189 // address of GOT into ebx and then call target@PLT. But for tail calls
3190 // ebx would be restored (since ebx is callee saved) before jumping to the
3193 // Note: The actual moving to ECX is done further down.
3194 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
3195 if (G && !G->getGlobal()->hasLocalLinkage() &&
3196 G->getGlobal()->hasDefaultVisibility())
3197 Callee = LowerGlobalAddress(Callee, DAG);
3198 else if (isa<ExternalSymbolSDNode>(Callee))
3199 Callee = LowerExternalSymbol(Callee, DAG);
3203 if (Is64Bit && isVarArg && !IsWin64 && !IsMustTail) {
3204 // From AMD64 ABI document:
3205 // For calls that may call functions that use varargs or stdargs
3206 // (prototype-less calls or calls to functions containing ellipsis (...) in
3207 // the declaration) %al is used as hidden argument to specify the number
3208 // of SSE registers used. The contents of %al do not need to match exactly
3209 // the number of registers, but must be an ubound on the number of SSE
3210 // registers used and is in the range 0 - 8 inclusive.
3212 // Count the number of XMM registers allocated.
3213 static const MCPhysReg XMMArgRegs[] = {
3214 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
3215 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
3217 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs);
3218 assert((Subtarget->hasSSE1() || !NumXMMRegs)
3219 && "SSE registers cannot be used when SSE is disabled");
3221 RegsToPass.push_back(std::make_pair(unsigned(X86::AL),
3222 DAG.getConstant(NumXMMRegs, dl,
3226 if (isVarArg && IsMustTail) {
3227 const auto &Forwards = X86Info->getForwardedMustTailRegParms();
3228 for (const auto &F : Forwards) {
3229 SDValue Val = DAG.getCopyFromReg(Chain, dl, F.VReg, F.VT);
3230 RegsToPass.push_back(std::make_pair(unsigned(F.PReg), Val));
3234 // For tail calls lower the arguments to the 'real' stack slots. Sibcalls
3235 // don't need this because the eligibility check rejects calls that require
3236 // shuffling arguments passed in memory.
3237 if (!IsSibcall && isTailCall) {
3238 // Force all the incoming stack arguments to be loaded from the stack
3239 // before any new outgoing arguments are stored to the stack, because the
3240 // outgoing stack slots may alias the incoming argument stack slots, and
3241 // the alias isn't otherwise explicit. This is slightly more conservative
3242 // than necessary, because it means that each store effectively depends
3243 // on every argument instead of just those arguments it would clobber.
3244 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
3246 SmallVector<SDValue, 8> MemOpChains2;
3249 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3250 CCValAssign &VA = ArgLocs[i];
3253 assert(VA.isMemLoc());
3254 SDValue Arg = OutVals[i];
3255 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3256 // Skip inalloca arguments. They don't require any work.
3257 if (Flags.isInAlloca())
3259 // Create frame index.
3260 int32_t Offset = VA.getLocMemOffset()+FPDiff;
3261 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
3262 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
3263 FIN = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
3265 if (Flags.isByVal()) {
3266 // Copy relative to framepointer.
3267 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset(), dl);
3268 if (!StackPtr.getNode())
3269 StackPtr = DAG.getCopyFromReg(Chain, dl, RegInfo->getStackRegister(),
3270 getPointerTy(DAG.getDataLayout()));
3271 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(DAG.getDataLayout()),
3274 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
3278 // Store relative to framepointer.
3279 MemOpChains2.push_back(DAG.getStore(
3280 ArgChain, dl, Arg, FIN,
3281 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI),
3286 if (!MemOpChains2.empty())
3287 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains2);
3289 // Store the return address to the appropriate stack slot.
3290 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx,
3291 getPointerTy(DAG.getDataLayout()),
3292 RegInfo->getSlotSize(), FPDiff, dl);
3295 // Build a sequence of copy-to-reg nodes chained together with token chain
3296 // and flag operands which copy the outgoing args into registers.
3298 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
3299 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
3300 RegsToPass[i].second, InFlag);
3301 InFlag = Chain.getValue(1);
3304 if (DAG.getTarget().getCodeModel() == CodeModel::Large) {
3305 assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
3306 // In the 64-bit large code model, we have to make all calls
3307 // through a register, since the call instruction's 32-bit
3308 // pc-relative offset may not be large enough to hold the whole
3310 } else if (Callee->getOpcode() == ISD::GlobalAddress) {
3311 // If the callee is a GlobalAddress node (quite common, every direct call
3312 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
3314 GlobalAddressSDNode* G = cast<GlobalAddressSDNode>(Callee);
3316 // We should use extra load for direct calls to dllimported functions in
3318 const GlobalValue *GV = G->getGlobal();
3319 if (!GV->hasDLLImportStorageClass()) {
3320 unsigned char OpFlags = 0;
3321 bool ExtraLoad = false;
3322 unsigned WrapperKind = ISD::DELETED_NODE;
3324 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
3325 // external symbols most go through the PLT in PIC mode. If the symbol
3326 // has hidden or protected visibility, or if it is static or local, then
3327 // we don't need to use the PLT - we can directly call it.
3328 if (Subtarget->isTargetELF() &&
3329 DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
3330 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
3331 OpFlags = X86II::MO_PLT;
3332 } else if (Subtarget->isPICStyleStubAny() &&
3333 !GV->isStrongDefinitionForLinker() &&
3334 (!Subtarget->getTargetTriple().isMacOSX() ||
3335 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
3336 // PC-relative references to external symbols should go through $stub,
3337 // unless we're building with the leopard linker or later, which
3338 // automatically synthesizes these stubs.
3339 OpFlags = X86II::MO_DARWIN_STUB;
3340 } else if (Subtarget->isPICStyleRIPRel() && isa<Function>(GV) &&
3341 cast<Function>(GV)->hasFnAttribute(Attribute::NonLazyBind)) {
3342 // If the function is marked as non-lazy, generate an indirect call
3343 // which loads from the GOT directly. This avoids runtime overhead
3344 // at the cost of eager binding (and one extra byte of encoding).
3345 OpFlags = X86II::MO_GOTPCREL;
3346 WrapperKind = X86ISD::WrapperRIP;
3350 Callee = DAG.getTargetGlobalAddress(
3351 GV, dl, getPointerTy(DAG.getDataLayout()), G->getOffset(), OpFlags);
3353 // Add a wrapper if needed.
3354 if (WrapperKind != ISD::DELETED_NODE)
3355 Callee = DAG.getNode(X86ISD::WrapperRIP, dl,
3356 getPointerTy(DAG.getDataLayout()), Callee);
3357 // Add extra indirection if needed.
3359 Callee = DAG.getLoad(
3360 getPointerTy(DAG.getDataLayout()), dl, DAG.getEntryNode(), Callee,
3361 MachinePointerInfo::getGOT(DAG.getMachineFunction()), false, false,
3364 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
3365 unsigned char OpFlags = 0;
3367 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to
3368 // external symbols should go through the PLT.
3369 if (Subtarget->isTargetELF() &&
3370 DAG.getTarget().getRelocationModel() == Reloc::PIC_) {
3371 OpFlags = X86II::MO_PLT;
3372 } else if (Subtarget->isPICStyleStubAny() &&
3373 (!Subtarget->getTargetTriple().isMacOSX() ||
3374 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
3375 // PC-relative references to external symbols should go through $stub,
3376 // unless we're building with the leopard linker or later, which
3377 // automatically synthesizes these stubs.
3378 OpFlags = X86II::MO_DARWIN_STUB;
3381 Callee = DAG.getTargetExternalSymbol(
3382 S->getSymbol(), getPointerTy(DAG.getDataLayout()), OpFlags);
3383 } else if (Subtarget->isTarget64BitILP32() &&
3384 Callee->getValueType(0) == MVT::i32) {
3385 // Zero-extend the 32-bit Callee address into a 64-bit according to x32 ABI
3386 Callee = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, Callee);
3389 // Returns a chain & a flag for retval copy to use.
3390 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
3391 SmallVector<SDValue, 8> Ops;
3393 if (!IsSibcall && isTailCall) {
3394 Chain = DAG.getCALLSEQ_END(Chain,
3395 DAG.getIntPtrConstant(NumBytesToPop, dl, true),
3396 DAG.getIntPtrConstant(0, dl, true), InFlag, dl);
3397 InFlag = Chain.getValue(1);
3400 Ops.push_back(Chain);
3401 Ops.push_back(Callee);
3404 Ops.push_back(DAG.getConstant(FPDiff, dl, MVT::i32));
3406 // Add argument registers to the end of the list so that they are known live
3408 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
3409 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
3410 RegsToPass[i].second.getValueType()));
3412 // Add a register mask operand representing the call-preserved registers.
3413 const uint32_t *Mask = RegInfo->getCallPreservedMask(MF, CallConv);
3414 assert(Mask && "Missing call preserved mask for calling convention");
3416 // If this is an invoke in a 32-bit function using a funclet-based
3417 // personality, assume the function clobbers all registers. If an exception
3418 // is thrown, the runtime will not restore CSRs.
3419 // FIXME: Model this more precisely so that we can register allocate across
3420 // the normal edge and spill and fill across the exceptional edge.
3421 if (!Is64Bit && CLI.CS && CLI.CS->isInvoke()) {
3422 const Function *CallerFn = MF.getFunction();
3423 EHPersonality Pers =
3424 CallerFn->hasPersonalityFn()
3425 ? classifyEHPersonality(CallerFn->getPersonalityFn())
3426 : EHPersonality::Unknown;
3427 if (isFuncletEHPersonality(Pers))
3428 Mask = RegInfo->getNoPreservedMask();
3431 Ops.push_back(DAG.getRegisterMask(Mask));
3433 if (InFlag.getNode())
3434 Ops.push_back(InFlag);
3438 //// If this is the first return lowered for this function, add the regs
3439 //// to the liveout set for the function.
3440 // This isn't right, although it's probably harmless on x86; liveouts
3441 // should be computed from returns not tail calls. Consider a void
3442 // function making a tail call to a function returning int.
3443 MF.getFrameInfo()->setHasTailCall();
3444 return DAG.getNode(X86ISD::TC_RETURN, dl, NodeTys, Ops);
3447 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, Ops);
3448 InFlag = Chain.getValue(1);
3450 // Create the CALLSEQ_END node.
3451 unsigned NumBytesForCalleeToPop;
3452 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
3453 DAG.getTarget().Options.GuaranteedTailCallOpt))
3454 NumBytesForCalleeToPop = NumBytes; // Callee pops everything
3455 else if (!Is64Bit && !canGuaranteeTCO(CallConv) &&
3456 !Subtarget->getTargetTriple().isOSMSVCRT() &&
3457 SR == StackStructReturn)
3458 // If this is a call to a struct-return function, the callee
3459 // pops the hidden struct pointer, so we have to push it back.
3460 // This is common for Darwin/X86, Linux & Mingw32 targets.
3461 // For MSVC Win32 targets, the caller pops the hidden struct pointer.
3462 NumBytesForCalleeToPop = 4;
3464 NumBytesForCalleeToPop = 0; // Callee pops nothing.
3466 // Returns a flag for retval copy to use.
3468 Chain = DAG.getCALLSEQ_END(Chain,
3469 DAG.getIntPtrConstant(NumBytesToPop, dl, true),
3470 DAG.getIntPtrConstant(NumBytesForCalleeToPop, dl,
3473 InFlag = Chain.getValue(1);
3476 // Handle result values, copying them out of physregs into vregs that we
3478 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
3479 Ins, dl, DAG, InVals);
3482 //===----------------------------------------------------------------------===//
3483 // Fast Calling Convention (tail call) implementation
3484 //===----------------------------------------------------------------------===//
3486 // Like std call, callee cleans arguments, convention except that ECX is
3487 // reserved for storing the tail called function address. Only 2 registers are
3488 // free for argument passing (inreg). Tail call optimization is performed
3490 // * tailcallopt is enabled
3491 // * caller/callee are fastcc
3492 // On X86_64 architecture with GOT-style position independent code only local
3493 // (within module) calls are supported at the moment.
3494 // To keep the stack aligned according to platform abi the function
3495 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
3496 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
3497 // If a tail called function callee has more arguments than the caller the
3498 // caller needs to make sure that there is room to move the RETADDR to. This is
3499 // achieved by reserving an area the size of the argument delta right after the
3500 // original RETADDR, but before the saved framepointer or the spilled registers
3501 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
3513 /// Make the stack size align e.g 16n + 12 aligned for a 16-byte align
3516 X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
3517 SelectionDAG& DAG) const {
3518 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
3519 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
3520 unsigned StackAlignment = TFI.getStackAlignment();
3521 uint64_t AlignMask = StackAlignment - 1;
3522 int64_t Offset = StackSize;
3523 unsigned SlotSize = RegInfo->getSlotSize();
3524 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
3525 // Number smaller than 12 so just add the difference.
3526 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
3528 // Mask out lower bits, add stackalignment once plus the 12 bytes.
3529 Offset = ((~AlignMask) & Offset) + StackAlignment +
3530 (StackAlignment-SlotSize);
3535 /// Return true if the given stack call argument is already available in the
3536 /// same position (relatively) of the caller's incoming argument stack.
3538 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
3539 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
3540 const X86InstrInfo *TII) {
3541 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
3543 if (Arg.getOpcode() == ISD::CopyFromReg) {
3544 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
3545 if (!TargetRegisterInfo::isVirtualRegister(VR))
3547 MachineInstr *Def = MRI->getVRegDef(VR);
3550 if (!Flags.isByVal()) {
3551 if (!TII->isLoadFromStackSlot(Def, FI))
3554 unsigned Opcode = Def->getOpcode();
3555 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r ||
3556 Opcode == X86::LEA64_32r) &&
3557 Def->getOperand(1).isFI()) {
3558 FI = Def->getOperand(1).getIndex();
3559 Bytes = Flags.getByValSize();
3563 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
3564 if (Flags.isByVal())
3565 // ByVal argument is passed in as a pointer but it's now being
3566 // dereferenced. e.g.
3567 // define @foo(%struct.X* %A) {
3568 // tail call @bar(%struct.X* byval %A)
3571 SDValue Ptr = Ld->getBasePtr();
3572 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
3575 FI = FINode->getIndex();
3576 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) {
3577 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg);
3578 FI = FINode->getIndex();
3579 Bytes = Flags.getByValSize();
3583 assert(FI != INT_MAX);
3584 if (!MFI->isFixedObjectIndex(FI))
3586 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
3589 /// Check whether the call is eligible for tail call optimization. Targets
3590 /// that want to do tail call optimization should implement this function.
3591 bool X86TargetLowering::IsEligibleForTailCallOptimization(
3592 SDValue Callee, CallingConv::ID CalleeCC, bool isVarArg,
3593 bool isCalleeStructRet, bool isCallerStructRet, Type *RetTy,
3594 const SmallVectorImpl<ISD::OutputArg> &Outs,
3595 const SmallVectorImpl<SDValue> &OutVals,
3596 const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG &DAG) const {
3597 if (!mayTailCallThisCC(CalleeCC))
3600 // If -tailcallopt is specified, make fastcc functions tail-callable.
3601 MachineFunction &MF = DAG.getMachineFunction();
3602 const Function *CallerF = MF.getFunction();
3604 // If the function return type is x86_fp80 and the callee return type is not,
3605 // then the FP_EXTEND of the call result is not a nop. It's not safe to
3606 // perform a tailcall optimization here.
3607 if (CallerF->getReturnType()->isX86_FP80Ty() && !RetTy->isX86_FP80Ty())
3610 CallingConv::ID CallerCC = CallerF->getCallingConv();
3611 bool CCMatch = CallerCC == CalleeCC;
3612 bool IsCalleeWin64 = Subtarget->isCallingConvWin64(CalleeCC);
3613 bool IsCallerWin64 = Subtarget->isCallingConvWin64(CallerCC);
3615 // Win64 functions have extra shadow space for argument homing. Don't do the
3616 // sibcall if the caller and callee have mismatched expectations for this
3618 if (IsCalleeWin64 != IsCallerWin64)
3621 if (DAG.getTarget().Options.GuaranteedTailCallOpt) {
3622 if (canGuaranteeTCO(CalleeCC) && CCMatch)
3627 // Look for obvious safe cases to perform tail call optimization that do not
3628 // require ABI changes. This is what gcc calls sibcall.
3630 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
3631 // emit a special epilogue.
3632 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
3633 if (RegInfo->needsStackRealignment(MF))
3636 // Also avoid sibcall optimization if either caller or callee uses struct
3637 // return semantics.
3638 if (isCalleeStructRet || isCallerStructRet)
3641 // Do not sibcall optimize vararg calls unless all arguments are passed via
3643 if (isVarArg && !Outs.empty()) {
3644 // Optimizing for varargs on Win64 is unlikely to be safe without
3645 // additional testing.
3646 if (IsCalleeWin64 || IsCallerWin64)
3649 SmallVector<CCValAssign, 16> ArgLocs;
3650 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
3653 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3654 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
3655 if (!ArgLocs[i].isRegLoc())
3659 // If the call result is in ST0 / ST1, it needs to be popped off the x87
3660 // stack. Therefore, if it's not used by the call it is not safe to optimize
3661 // this into a sibcall.
3662 bool Unused = false;
3663 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
3670 SmallVector<CCValAssign, 16> RVLocs;
3671 CCState CCInfo(CalleeCC, false, DAG.getMachineFunction(), RVLocs,
3673 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
3674 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
3675 CCValAssign &VA = RVLocs[i];
3676 if (VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1)
3681 // If the calling conventions do not match, then we'd better make sure the
3682 // results are returned in the same way as what the caller expects.
3684 SmallVector<CCValAssign, 16> RVLocs1;
3685 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(), RVLocs1,
3687 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86);
3689 SmallVector<CCValAssign, 16> RVLocs2;
3690 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(), RVLocs2,
3692 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86);
3694 if (RVLocs1.size() != RVLocs2.size())
3696 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
3697 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
3699 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
3701 if (RVLocs1[i].isRegLoc()) {
3702 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
3705 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
3711 unsigned StackArgsSize = 0;
3713 // If the callee takes no arguments then go on to check the results of the
3715 if (!Outs.empty()) {
3716 // Check if stack adjustment is needed. For now, do not do this if any
3717 // argument is passed on the stack.
3718 SmallVector<CCValAssign, 16> ArgLocs;
3719 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
3722 // Allocate shadow area for Win64
3724 CCInfo.AllocateStack(32, 8);
3726 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3727 StackArgsSize = CCInfo.getNextStackOffset();
3729 if (CCInfo.getNextStackOffset()) {
3730 // Check if the arguments are already laid out in the right way as
3731 // the caller's fixed stack objects.
3732 MachineFrameInfo *MFI = MF.getFrameInfo();
3733 const MachineRegisterInfo *MRI = &MF.getRegInfo();
3734 const X86InstrInfo *TII = Subtarget->getInstrInfo();
3735 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3736 CCValAssign &VA = ArgLocs[i];
3737 SDValue Arg = OutVals[i];
3738 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3739 if (VA.getLocInfo() == CCValAssign::Indirect)
3741 if (!VA.isRegLoc()) {
3742 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
3749 // If the tailcall address may be in a register, then make sure it's
3750 // possible to register allocate for it. In 32-bit, the call address can
3751 // only target EAX, EDX, or ECX since the tail call must be scheduled after
3752 // callee-saved registers are restored. These happen to be the same
3753 // registers used to pass 'inreg' arguments so watch out for those.
3754 if (!Subtarget->is64Bit() &&
3755 ((!isa<GlobalAddressSDNode>(Callee) &&
3756 !isa<ExternalSymbolSDNode>(Callee)) ||
3757 DAG.getTarget().getRelocationModel() == Reloc::PIC_)) {
3758 unsigned NumInRegs = 0;
3759 // In PIC we need an extra register to formulate the address computation
3761 unsigned MaxInRegs =
3762 (DAG.getTarget().getRelocationModel() == Reloc::PIC_) ? 2 : 3;
3764 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3765 CCValAssign &VA = ArgLocs[i];
3768 unsigned Reg = VA.getLocReg();
3771 case X86::EAX: case X86::EDX: case X86::ECX:
3772 if (++NumInRegs == MaxInRegs)
3780 bool CalleeWillPop =
3781 X86::isCalleePop(CalleeCC, Subtarget->is64Bit(), isVarArg,
3782 MF.getTarget().Options.GuaranteedTailCallOpt);
3784 if (unsigned BytesToPop =
3785 MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn()) {
3786 // If we have bytes to pop, the callee must pop them.
3787 bool CalleePopMatches = CalleeWillPop && BytesToPop == StackArgsSize;
3788 if (!CalleePopMatches)
3790 } else if (CalleeWillPop && StackArgsSize > 0) {
3791 // If we don't have bytes to pop, make sure the callee doesn't pop any.
3799 X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
3800 const TargetLibraryInfo *libInfo) const {
3801 return X86::createFastISel(funcInfo, libInfo);
3804 //===----------------------------------------------------------------------===//
3805 // Other Lowering Hooks
3806 //===----------------------------------------------------------------------===//
3808 static bool MayFoldLoad(SDValue Op) {
3809 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode());
3812 static bool MayFoldIntoStore(SDValue Op) {
3813 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin());
3816 static bool isTargetShuffle(unsigned Opcode) {
3818 default: return false;
3819 case X86ISD::BLENDI:
3820 case X86ISD::PSHUFB:
3821 case X86ISD::PSHUFD:
3822 case X86ISD::PSHUFHW:
3823 case X86ISD::PSHUFLW:
3825 case X86ISD::PALIGNR:
3826 case X86ISD::MOVLHPS:
3827 case X86ISD::MOVLHPD:
3828 case X86ISD::MOVHLPS:
3829 case X86ISD::MOVLPS:
3830 case X86ISD::MOVLPD:
3831 case X86ISD::MOVSHDUP:
3832 case X86ISD::MOVSLDUP:
3833 case X86ISD::MOVDDUP:
3836 case X86ISD::UNPCKL:
3837 case X86ISD::UNPCKH:
3838 case X86ISD::VPERMILPI:
3839 case X86ISD::VPERM2X128:
3840 case X86ISD::VPERMI:
3841 case X86ISD::VPERMV:
3842 case X86ISD::VPERMV3:
3847 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3848 SDValue V1, unsigned TargetMask,
3849 SelectionDAG &DAG) {
3851 default: llvm_unreachable("Unknown x86 shuffle node");
3852 case X86ISD::PSHUFD:
3853 case X86ISD::PSHUFHW:
3854 case X86ISD::PSHUFLW:
3855 case X86ISD::VPERMILPI:
3856 case X86ISD::VPERMI:
3857 return DAG.getNode(Opc, dl, VT, V1,
3858 DAG.getConstant(TargetMask, dl, MVT::i8));
3862 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3863 SDValue V1, SDValue V2, SelectionDAG &DAG) {
3865 default: llvm_unreachable("Unknown x86 shuffle node");
3866 case X86ISD::MOVLHPS:
3867 case X86ISD::MOVLHPD:
3868 case X86ISD::MOVHLPS:
3869 case X86ISD::MOVLPS:
3870 case X86ISD::MOVLPD:
3873 case X86ISD::UNPCKL:
3874 case X86ISD::UNPCKH:
3875 return DAG.getNode(Opc, dl, VT, V1, V2);
3879 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
3880 MachineFunction &MF = DAG.getMachineFunction();
3881 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
3882 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
3883 int ReturnAddrIndex = FuncInfo->getRAIndex();
3885 if (ReturnAddrIndex == 0) {
3886 // Set up a frame object for the return address.
3887 unsigned SlotSize = RegInfo->getSlotSize();
3888 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize,
3891 FuncInfo->setRAIndex(ReturnAddrIndex);
3894 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy(DAG.getDataLayout()));
3897 bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
3898 bool hasSymbolicDisplacement) {
3899 // Offset should fit into 32 bit immediate field.
3900 if (!isInt<32>(Offset))
3903 // If we don't have a symbolic displacement - we don't have any extra
3905 if (!hasSymbolicDisplacement)
3908 // FIXME: Some tweaks might be needed for medium code model.
3909 if (M != CodeModel::Small && M != CodeModel::Kernel)
3912 // For small code model we assume that latest object is 16MB before end of 31
3913 // bits boundary. We may also accept pretty large negative constants knowing
3914 // that all objects are in the positive half of address space.
3915 if (M == CodeModel::Small && Offset < 16*1024*1024)
3918 // For kernel code model we know that all object resist in the negative half
3919 // of 32bits address space. We may not accept negative offsets, since they may
3920 // be just off and we may accept pretty large positive ones.
3921 if (M == CodeModel::Kernel && Offset >= 0)
3927 /// Determines whether the callee is required to pop its own arguments.
3928 /// Callee pop is necessary to support tail calls.
3929 bool X86::isCalleePop(CallingConv::ID CallingConv,
3930 bool is64Bit, bool IsVarArg, bool GuaranteeTCO) {
3931 // If GuaranteeTCO is true, we force some calls to be callee pop so that we
3932 // can guarantee TCO.
3933 if (!IsVarArg && shouldGuaranteeTCO(CallingConv, GuaranteeTCO))
3936 switch (CallingConv) {
3939 case CallingConv::X86_StdCall:
3940 case CallingConv::X86_FastCall:
3941 case CallingConv::X86_ThisCall:
3942 case CallingConv::X86_VectorCall:
3947 /// \brief Return true if the condition is an unsigned comparison operation.
3948 static bool isX86CCUnsigned(unsigned X86CC) {
3950 default: llvm_unreachable("Invalid integer condition!");
3951 case X86::COND_E: return true;
3952 case X86::COND_G: return false;
3953 case X86::COND_GE: return false;
3954 case X86::COND_L: return false;
3955 case X86::COND_LE: return false;
3956 case X86::COND_NE: return true;
3957 case X86::COND_B: return true;
3958 case X86::COND_A: return true;
3959 case X86::COND_BE: return true;
3960 case X86::COND_AE: return true;
3962 llvm_unreachable("covered switch fell through?!");
3965 /// Do a one-to-one translation of a ISD::CondCode to the X86-specific
3966 /// condition code, returning the condition code and the LHS/RHS of the
3967 /// comparison to make.
3968 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, SDLoc DL, bool isFP,
3969 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
3971 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
3972 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
3973 // X > -1 -> X == 0, jump !sign.
3974 RHS = DAG.getConstant(0, DL, RHS.getValueType());
3975 return X86::COND_NS;
3977 if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
3978 // X < 0 -> X == 0, jump on sign.
3981 if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
3983 RHS = DAG.getConstant(0, DL, RHS.getValueType());
3984 return X86::COND_LE;
3988 switch (SetCCOpcode) {
3989 default: llvm_unreachable("Invalid integer condition!");
3990 case ISD::SETEQ: return X86::COND_E;
3991 case ISD::SETGT: return X86::COND_G;
3992 case ISD::SETGE: return X86::COND_GE;
3993 case ISD::SETLT: return X86::COND_L;
3994 case ISD::SETLE: return X86::COND_LE;
3995 case ISD::SETNE: return X86::COND_NE;
3996 case ISD::SETULT: return X86::COND_B;
3997 case ISD::SETUGT: return X86::COND_A;
3998 case ISD::SETULE: return X86::COND_BE;
3999 case ISD::SETUGE: return X86::COND_AE;
4003 // First determine if it is required or is profitable to flip the operands.
4005 // If LHS is a foldable load, but RHS is not, flip the condition.
4006 if (ISD::isNON_EXTLoad(LHS.getNode()) &&
4007 !ISD::isNON_EXTLoad(RHS.getNode())) {
4008 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
4009 std::swap(LHS, RHS);
4012 switch (SetCCOpcode) {
4018 std::swap(LHS, RHS);
4022 // On a floating point condition, the flags are set as follows:
4024 // 0 | 0 | 0 | X > Y
4025 // 0 | 0 | 1 | X < Y
4026 // 1 | 0 | 0 | X == Y
4027 // 1 | 1 | 1 | unordered
4028 switch (SetCCOpcode) {
4029 default: llvm_unreachable("Condcode should be pre-legalized away");
4031 case ISD::SETEQ: return X86::COND_E;
4032 case ISD::SETOLT: // flipped
4034 case ISD::SETGT: return X86::COND_A;
4035 case ISD::SETOLE: // flipped
4037 case ISD::SETGE: return X86::COND_AE;
4038 case ISD::SETUGT: // flipped
4040 case ISD::SETLT: return X86::COND_B;
4041 case ISD::SETUGE: // flipped
4043 case ISD::SETLE: return X86::COND_BE;
4045 case ISD::SETNE: return X86::COND_NE;
4046 case ISD::SETUO: return X86::COND_P;
4047 case ISD::SETO: return X86::COND_NP;
4049 case ISD::SETUNE: return X86::COND_INVALID;
4053 /// Is there a floating point cmov for the specific X86 condition code?
4054 /// Current x86 isa includes the following FP cmov instructions:
4055 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
4056 static bool hasFPCMov(unsigned X86CC) {
4072 /// Returns true if the target can instruction select the
4073 /// specified FP immediate natively. If false, the legalizer will
4074 /// materialize the FP immediate as a load from a constant pool.
4075 bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
4076 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
4077 if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
4083 bool X86TargetLowering::shouldReduceLoadWidth(SDNode *Load,
4084 ISD::LoadExtType ExtTy,
4086 // "ELF Handling for Thread-Local Storage" specifies that R_X86_64_GOTTPOFF
4087 // relocation target a movq or addq instruction: don't let the load shrink.
4088 SDValue BasePtr = cast<LoadSDNode>(Load)->getBasePtr();
4089 if (BasePtr.getOpcode() == X86ISD::WrapperRIP)
4090 if (const auto *GA = dyn_cast<GlobalAddressSDNode>(BasePtr.getOperand(0)))
4091 return GA->getTargetFlags() != X86II::MO_GOTTPOFF;
4095 /// \brief Returns true if it is beneficial to convert a load of a constant
4096 /// to just the constant itself.
4097 bool X86TargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
4099 assert(Ty->isIntegerTy());
4101 unsigned BitSize = Ty->getPrimitiveSizeInBits();
4102 if (BitSize == 0 || BitSize > 64)
4107 bool X86TargetLowering::isExtractSubvectorCheap(EVT ResVT,
4108 unsigned Index) const {
4109 if (!isOperationLegalOrCustom(ISD::EXTRACT_SUBVECTOR, ResVT))
4112 return (Index == 0 || Index == ResVT.getVectorNumElements());
4115 bool X86TargetLowering::isCheapToSpeculateCttz() const {
4116 // Speculate cttz only if we can directly use TZCNT.
4117 return Subtarget->hasBMI();
4120 bool X86TargetLowering::isCheapToSpeculateCtlz() const {
4121 // Speculate ctlz only if we can directly use LZCNT.
4122 return Subtarget->hasLZCNT();
4125 /// Return true if every element in Mask, beginning
4126 /// from position Pos and ending in Pos+Size is undef.
4127 static bool isUndefInRange(ArrayRef<int> Mask, unsigned Pos, unsigned Size) {
4128 for (unsigned i = Pos, e = Pos + Size; i != e; ++i)
4134 /// Return true if Val is undef or if its value falls within the
4135 /// specified range (L, H].
4136 static bool isUndefOrInRange(int Val, int Low, int Hi) {
4137 return (Val < 0) || (Val >= Low && Val < Hi);
4140 /// Val is either less than zero (undef) or equal to the specified value.
4141 static bool isUndefOrEqual(int Val, int CmpVal) {
4142 return (Val < 0 || Val == CmpVal);
4145 /// Return true if every element in Mask, beginning
4146 /// from position Pos and ending in Pos+Size, falls within the specified
4147 /// sequential range (Low, Low+Size]. or is undef.
4148 static bool isSequentialOrUndefInRange(ArrayRef<int> Mask,
4149 unsigned Pos, unsigned Size, int Low) {
4150 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low)
4151 if (!isUndefOrEqual(Mask[i], Low))
4156 /// Return true if the specified EXTRACT_SUBVECTOR operand specifies a vector
4157 /// extract that is suitable for instruction that extract 128 or 256 bit vectors
4158 static bool isVEXTRACTIndex(SDNode *N, unsigned vecWidth) {
4159 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4160 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4163 // The index should be aligned on a vecWidth-bit boundary.
4165 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4167 MVT VT = N->getSimpleValueType(0);
4168 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4169 bool Result = (Index * ElSize) % vecWidth == 0;
4174 /// Return true if the specified INSERT_SUBVECTOR
4175 /// operand specifies a subvector insert that is suitable for input to
4176 /// insertion of 128 or 256-bit subvectors
4177 static bool isVINSERTIndex(SDNode *N, unsigned vecWidth) {
4178 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4179 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4181 // The index should be aligned on a vecWidth-bit boundary.
4183 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4185 MVT VT = N->getSimpleValueType(0);
4186 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4187 bool Result = (Index * ElSize) % vecWidth == 0;
4192 bool X86::isVINSERT128Index(SDNode *N) {
4193 return isVINSERTIndex(N, 128);
4196 bool X86::isVINSERT256Index(SDNode *N) {
4197 return isVINSERTIndex(N, 256);
4200 bool X86::isVEXTRACT128Index(SDNode *N) {
4201 return isVEXTRACTIndex(N, 128);
4204 bool X86::isVEXTRACT256Index(SDNode *N) {
4205 return isVEXTRACTIndex(N, 256);
4208 static unsigned getExtractVEXTRACTImmediate(SDNode *N, unsigned vecWidth) {
4209 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4210 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4211 llvm_unreachable("Illegal extract subvector for VEXTRACT");
4214 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4216 MVT VecVT = N->getOperand(0).getSimpleValueType();
4217 MVT ElVT = VecVT.getVectorElementType();
4219 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4220 return Index / NumElemsPerChunk;
4223 static unsigned getInsertVINSERTImmediate(SDNode *N, unsigned vecWidth) {
4224 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4225 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4226 llvm_unreachable("Illegal insert subvector for VINSERT");
4229 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4231 MVT VecVT = N->getSimpleValueType(0);
4232 MVT ElVT = VecVT.getVectorElementType();
4234 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4235 return Index / NumElemsPerChunk;
4238 /// Return the appropriate immediate to extract the specified
4239 /// EXTRACT_SUBVECTOR index with VEXTRACTF128 and VINSERTI128 instructions.
4240 unsigned X86::getExtractVEXTRACT128Immediate(SDNode *N) {
4241 return getExtractVEXTRACTImmediate(N, 128);
4244 /// Return the appropriate immediate to extract the specified
4245 /// EXTRACT_SUBVECTOR index with VEXTRACTF64x4 and VINSERTI64x4 instructions.
4246 unsigned X86::getExtractVEXTRACT256Immediate(SDNode *N) {
4247 return getExtractVEXTRACTImmediate(N, 256);
4250 /// Return the appropriate immediate to insert at the specified
4251 /// INSERT_SUBVECTOR index with VINSERTF128 and VINSERTI128 instructions.
4252 unsigned X86::getInsertVINSERT128Immediate(SDNode *N) {
4253 return getInsertVINSERTImmediate(N, 128);
4256 /// Return the appropriate immediate to insert at the specified
4257 /// INSERT_SUBVECTOR index with VINSERTF46x4 and VINSERTI64x4 instructions.
4258 unsigned X86::getInsertVINSERT256Immediate(SDNode *N) {
4259 return getInsertVINSERTImmediate(N, 256);
4262 /// Returns true if V is a constant integer zero.
4263 static bool isZero(SDValue V) {
4264 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
4265 return C && C->isNullValue();
4268 /// Returns true if Elt is a constant zero or a floating point constant +0.0.
4269 bool X86::isZeroNode(SDValue Elt) {
4272 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Elt))
4273 return CFP->getValueAPF().isPosZero();
4277 // Build a vector of constants
4278 // Use an UNDEF node if MaskElt == -1.
4279 // Spilt 64-bit constants in the 32-bit mode.
4280 static SDValue getConstVector(ArrayRef<int> Values, EVT VT,
4282 SDLoc dl, bool IsMask = false) {
4284 SmallVector<SDValue, 32> Ops;
4287 EVT ConstVecVT = VT;
4288 unsigned NumElts = VT.getVectorNumElements();
4289 bool In64BitMode = DAG.getTargetLoweringInfo().isTypeLegal(MVT::i64);
4290 if (!In64BitMode && VT.getScalarType() == MVT::i64) {
4291 ConstVecVT = MVT::getVectorVT(MVT::i32, NumElts * 2);
4295 EVT EltVT = ConstVecVT.getScalarType();
4296 for (unsigned i = 0; i < NumElts; ++i) {
4297 bool IsUndef = Values[i] < 0 && IsMask;
4298 SDValue OpNode = IsUndef ? DAG.getUNDEF(EltVT) :
4299 DAG.getConstant(Values[i], dl, EltVT);
4300 Ops.push_back(OpNode);
4302 Ops.push_back(IsUndef ? DAG.getUNDEF(EltVT) :
4303 DAG.getConstant(0, dl, EltVT));
4305 SDValue ConstsNode = DAG.getNode(ISD::BUILD_VECTOR, dl, ConstVecVT, Ops);
4307 ConstsNode = DAG.getBitcast(VT, ConstsNode);
4311 /// Returns a vector of specified type with all zero elements.
4312 static SDValue getZeroVector(EVT VT, const X86Subtarget *Subtarget,
4313 SelectionDAG &DAG, SDLoc dl) {
4314 assert(VT.isVector() && "Expected a vector type");
4316 // Always build SSE zero vectors as <4 x i32> bitcasted
4317 // to their dest type. This ensures they get CSE'd.
4319 if (VT.is128BitVector()) { // SSE
4320 if (Subtarget->hasSSE2()) { // SSE2
4321 SDValue Cst = DAG.getConstant(0, dl, MVT::i32);
4322 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4324 SDValue Cst = DAG.getConstantFP(+0.0, dl, MVT::f32);
4325 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
4327 } else if (VT.is256BitVector()) { // AVX
4328 if (Subtarget->hasInt256()) { // AVX2
4329 SDValue Cst = DAG.getConstant(0, dl, MVT::i32);
4330 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4331 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
4333 // 256-bit logic and arithmetic instructions in AVX are all
4334 // floating-point, no support for integer ops. Emit fp zeroed vectors.
4335 SDValue Cst = DAG.getConstantFP(+0.0, dl, MVT::f32);
4336 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4337 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops);
4339 } else if (VT.is512BitVector()) { // AVX-512
4340 SDValue Cst = DAG.getConstant(0, dl, MVT::i32);
4341 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst,
4342 Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4343 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i32, Ops);
4344 } else if (VT.getScalarType() == MVT::i1) {
4346 assert((Subtarget->hasBWI() || VT.getVectorNumElements() <= 16)
4347 && "Unexpected vector type");
4348 assert((Subtarget->hasVLX() || VT.getVectorNumElements() >= 8)
4349 && "Unexpected vector type");
4350 SDValue Cst = DAG.getConstant(0, dl, MVT::i1);
4351 SmallVector<SDValue, 64> Ops(VT.getVectorNumElements(), Cst);
4352 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
4354 llvm_unreachable("Unexpected vector type");
4356 return DAG.getBitcast(VT, Vec);
4359 static SDValue ExtractSubVector(SDValue Vec, unsigned IdxVal,
4360 SelectionDAG &DAG, SDLoc dl,
4361 unsigned vectorWidth) {
4362 assert((vectorWidth == 128 || vectorWidth == 256) &&
4363 "Unsupported vector width");
4364 EVT VT = Vec.getValueType();
4365 EVT ElVT = VT.getVectorElementType();
4366 unsigned Factor = VT.getSizeInBits()/vectorWidth;
4367 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT,
4368 VT.getVectorNumElements()/Factor);
4370 // Extract from UNDEF is UNDEF.
4371 if (Vec.getOpcode() == ISD::UNDEF)
4372 return DAG.getUNDEF(ResultVT);
4374 // Extract the relevant vectorWidth bits. Generate an EXTRACT_SUBVECTOR
4375 unsigned ElemsPerChunk = vectorWidth / ElVT.getSizeInBits();
4377 // This is the index of the first element of the vectorWidth-bit chunk
4379 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits()) / vectorWidth)
4382 // If the input is a buildvector just emit a smaller one.
4383 if (Vec.getOpcode() == ISD::BUILD_VECTOR)
4384 return DAG.getNode(ISD::BUILD_VECTOR, dl, ResultVT,
4385 makeArrayRef(Vec->op_begin() + NormalizedIdxVal,
4388 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal, dl);
4389 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec, VecIdx);
4392 /// Generate a DAG to grab 128-bits from a vector > 128 bits. This
4393 /// sets things up to match to an AVX VEXTRACTF128 / VEXTRACTI128
4394 /// or AVX-512 VEXTRACTF32x4 / VEXTRACTI32x4
4395 /// instructions or a simple subregister reference. Idx is an index in the
4396 /// 128 bits we want. It need not be aligned to a 128-bit boundary. That makes
4397 /// lowering EXTRACT_VECTOR_ELT operations easier.
4398 static SDValue Extract128BitVector(SDValue Vec, unsigned IdxVal,
4399 SelectionDAG &DAG, SDLoc dl) {
4400 assert((Vec.getValueType().is256BitVector() ||
4401 Vec.getValueType().is512BitVector()) && "Unexpected vector size!");
4402 return ExtractSubVector(Vec, IdxVal, DAG, dl, 128);
4405 /// Generate a DAG to grab 256-bits from a 512-bit vector.
4406 static SDValue Extract256BitVector(SDValue Vec, unsigned IdxVal,
4407 SelectionDAG &DAG, SDLoc dl) {
4408 assert(Vec.getValueType().is512BitVector() && "Unexpected vector size!");
4409 return ExtractSubVector(Vec, IdxVal, DAG, dl, 256);
4412 static SDValue InsertSubVector(SDValue Result, SDValue Vec,
4413 unsigned IdxVal, SelectionDAG &DAG,
4414 SDLoc dl, unsigned vectorWidth) {
4415 assert((vectorWidth == 128 || vectorWidth == 256) &&
4416 "Unsupported vector width");
4417 // Inserting UNDEF is Result
4418 if (Vec.getOpcode() == ISD::UNDEF)
4420 EVT VT = Vec.getValueType();
4421 EVT ElVT = VT.getVectorElementType();
4422 EVT ResultVT = Result.getValueType();
4424 // Insert the relevant vectorWidth bits.
4425 unsigned ElemsPerChunk = vectorWidth/ElVT.getSizeInBits();
4427 // This is the index of the first element of the vectorWidth-bit chunk
4429 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits())/vectorWidth)
4432 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal, dl);
4433 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec, VecIdx);
4436 /// Generate a DAG to put 128-bits into a vector > 128 bits. This
4437 /// sets things up to match to an AVX VINSERTF128/VINSERTI128 or
4438 /// AVX-512 VINSERTF32x4/VINSERTI32x4 instructions or a
4439 /// simple superregister reference. Idx is an index in the 128 bits
4440 /// we want. It need not be aligned to a 128-bit boundary. That makes
4441 /// lowering INSERT_VECTOR_ELT operations easier.
4442 static SDValue Insert128BitVector(SDValue Result, SDValue Vec, unsigned IdxVal,
4443 SelectionDAG &DAG, SDLoc dl) {
4444 assert(Vec.getValueType().is128BitVector() && "Unexpected vector size!");
4446 // For insertion into the zero index (low half) of a 256-bit vector, it is
4447 // more efficient to generate a blend with immediate instead of an insert*128.
4448 // We are still creating an INSERT_SUBVECTOR below with an undef node to
4449 // extend the subvector to the size of the result vector. Make sure that
4450 // we are not recursing on that node by checking for undef here.
4451 if (IdxVal == 0 && Result.getValueType().is256BitVector() &&
4452 Result.getOpcode() != ISD::UNDEF) {
4453 EVT ResultVT = Result.getValueType();
4454 SDValue ZeroIndex = DAG.getIntPtrConstant(0, dl);
4455 SDValue Undef = DAG.getUNDEF(ResultVT);
4456 SDValue Vec256 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Undef,
4459 // The blend instruction, and therefore its mask, depend on the data type.
4460 MVT ScalarType = ResultVT.getScalarType().getSimpleVT();
4461 if (ScalarType.isFloatingPoint()) {
4462 // Choose either vblendps (float) or vblendpd (double).
4463 unsigned ScalarSize = ScalarType.getSizeInBits();
4464 assert((ScalarSize == 64 || ScalarSize == 32) && "Unknown float type");
4465 unsigned MaskVal = (ScalarSize == 64) ? 0x03 : 0x0f;
4466 SDValue Mask = DAG.getConstant(MaskVal, dl, MVT::i8);
4467 return DAG.getNode(X86ISD::BLENDI, dl, ResultVT, Result, Vec256, Mask);
4470 const X86Subtarget &Subtarget =
4471 static_cast<const X86Subtarget &>(DAG.getSubtarget());
4473 // AVX2 is needed for 256-bit integer blend support.
4474 // Integers must be cast to 32-bit because there is only vpblendd;
4475 // vpblendw can't be used for this because it has a handicapped mask.
4477 // If we don't have AVX2, then cast to float. Using a wrong domain blend
4478 // is still more efficient than using the wrong domain vinsertf128 that
4479 // will be created by InsertSubVector().
4480 MVT CastVT = Subtarget.hasAVX2() ? MVT::v8i32 : MVT::v8f32;
4482 SDValue Mask = DAG.getConstant(0x0f, dl, MVT::i8);
4483 Vec256 = DAG.getBitcast(CastVT, Vec256);
4484 Vec256 = DAG.getNode(X86ISD::BLENDI, dl, CastVT, Result, Vec256, Mask);
4485 return DAG.getBitcast(ResultVT, Vec256);
4488 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 128);
4491 static SDValue Insert256BitVector(SDValue Result, SDValue Vec, unsigned IdxVal,
4492 SelectionDAG &DAG, SDLoc dl) {
4493 assert(Vec.getValueType().is256BitVector() && "Unexpected vector size!");
4494 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 256);
4497 /// Concat two 128-bit vectors into a 256 bit vector using VINSERTF128
4498 /// instructions. This is used because creating CONCAT_VECTOR nodes of
4499 /// BUILD_VECTORS returns a larger BUILD_VECTOR while we're trying to lower
4500 /// large BUILD_VECTORS.
4501 static SDValue Concat128BitVectors(SDValue V1, SDValue V2, EVT VT,
4502 unsigned NumElems, SelectionDAG &DAG,
4504 SDValue V = Insert128BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
4505 return Insert128BitVector(V, V2, NumElems/2, DAG, dl);
4508 static SDValue Concat256BitVectors(SDValue V1, SDValue V2, EVT VT,
4509 unsigned NumElems, SelectionDAG &DAG,
4511 SDValue V = Insert256BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
4512 return Insert256BitVector(V, V2, NumElems/2, DAG, dl);
4515 /// Returns a vector of specified type with all bits set.
4516 /// Always build ones vectors as <4 x i32> or <8 x i32>. For 256-bit types with
4517 /// no AVX2 supprt, use two <4 x i32> inserted in a <8 x i32> appropriately.
4518 /// Then bitcast to their original type, ensuring they get CSE'd.
4519 static SDValue getOnesVector(EVT VT, const X86Subtarget *Subtarget,
4520 SelectionDAG &DAG, SDLoc dl) {
4521 assert(VT.isVector() && "Expected a vector type");
4523 SDValue Cst = DAG.getConstant(~0U, dl, MVT::i32);
4525 if (VT.is512BitVector()) {
4526 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst,
4527 Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4528 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i32, Ops);
4529 } else if (VT.is256BitVector()) {
4530 if (Subtarget->hasInt256()) { // AVX2
4531 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4532 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
4534 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4535 Vec = Concat128BitVectors(Vec, Vec, MVT::v8i32, 8, DAG, dl);
4537 } else if (VT.is128BitVector()) {
4538 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4540 llvm_unreachable("Unexpected vector type");
4542 return DAG.getBitcast(VT, Vec);
4545 /// Returns a vector_shuffle node for an unpackl operation.
4546 static SDValue getUnpackl(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
4548 unsigned NumElems = VT.getVectorNumElements();
4549 SmallVector<int, 8> Mask;
4550 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
4552 Mask.push_back(i + NumElems);
4554 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4557 /// Returns a vector_shuffle node for an unpackh operation.
4558 static SDValue getUnpackh(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
4560 unsigned NumElems = VT.getVectorNumElements();
4561 SmallVector<int, 8> Mask;
4562 for (unsigned i = 0, Half = NumElems/2; i != Half; ++i) {
4563 Mask.push_back(i + Half);
4564 Mask.push_back(i + NumElems + Half);
4566 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4569 /// Return a vector_shuffle of the specified vector of zero or undef vector.
4570 /// This produces a shuffle where the low element of V2 is swizzled into the
4571 /// zero/undef vector, landing at element Idx.
4572 /// This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
4573 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
4575 const X86Subtarget *Subtarget,
4576 SelectionDAG &DAG) {
4577 MVT VT = V2.getSimpleValueType();
4579 ? getZeroVector(VT, Subtarget, DAG, SDLoc(V2)) : DAG.getUNDEF(VT);
4580 unsigned NumElems = VT.getVectorNumElements();
4581 SmallVector<int, 16> MaskVec;
4582 for (unsigned i = 0; i != NumElems; ++i)
4583 // If this is the insertion idx, put the low elt of V2 here.
4584 MaskVec.push_back(i == Idx ? NumElems : i);
4585 return DAG.getVectorShuffle(VT, SDLoc(V2), V1, V2, &MaskVec[0]);
4588 /// Calculates the shuffle mask corresponding to the target-specific opcode.
4589 /// Returns true if the Mask could be calculated. Sets IsUnary to true if only
4590 /// uses one source. Note that this will set IsUnary for shuffles which use a
4591 /// single input multiple times, and in those cases it will
4592 /// adjust the mask to only have indices within that single input.
4593 /// FIXME: Add support for Decode*Mask functions that return SM_SentinelZero.
4594 static bool getTargetShuffleMask(SDNode *N, MVT VT,
4595 SmallVectorImpl<int> &Mask, bool &IsUnary) {
4596 unsigned NumElems = VT.getVectorNumElements();
4600 bool IsFakeUnary = false;
4601 switch(N->getOpcode()) {
4602 case X86ISD::BLENDI:
4603 ImmN = N->getOperand(N->getNumOperands()-1);
4604 DecodeBLENDMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4607 ImmN = N->getOperand(N->getNumOperands()-1);
4608 DecodeSHUFPMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4609 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4611 case X86ISD::UNPCKH:
4612 DecodeUNPCKHMask(VT, Mask);
4613 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4615 case X86ISD::UNPCKL:
4616 DecodeUNPCKLMask(VT, Mask);
4617 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4619 case X86ISD::MOVHLPS:
4620 DecodeMOVHLPSMask(NumElems, Mask);
4621 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4623 case X86ISD::MOVLHPS:
4624 DecodeMOVLHPSMask(NumElems, Mask);
4625 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4627 case X86ISD::PALIGNR:
4628 ImmN = N->getOperand(N->getNumOperands()-1);
4629 DecodePALIGNRMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4631 case X86ISD::PSHUFD:
4632 case X86ISD::VPERMILPI:
4633 ImmN = N->getOperand(N->getNumOperands()-1);
4634 DecodePSHUFMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4637 case X86ISD::PSHUFHW:
4638 ImmN = N->getOperand(N->getNumOperands()-1);
4639 DecodePSHUFHWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4642 case X86ISD::PSHUFLW:
4643 ImmN = N->getOperand(N->getNumOperands()-1);
4644 DecodePSHUFLWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4647 case X86ISD::PSHUFB: {
4649 SDValue MaskNode = N->getOperand(1);
4650 while (MaskNode->getOpcode() == ISD::BITCAST)
4651 MaskNode = MaskNode->getOperand(0);
4653 if (MaskNode->getOpcode() == ISD::BUILD_VECTOR) {
4654 // If we have a build-vector, then things are easy.
4655 EVT VT = MaskNode.getValueType();
4656 assert(VT.isVector() &&
4657 "Can't produce a non-vector with a build_vector!");
4658 if (!VT.isInteger())
4661 int NumBytesPerElement = VT.getVectorElementType().getSizeInBits() / 8;
4663 SmallVector<uint64_t, 32> RawMask;
4664 for (int i = 0, e = MaskNode->getNumOperands(); i < e; ++i) {
4665 SDValue Op = MaskNode->getOperand(i);
4666 if (Op->getOpcode() == ISD::UNDEF) {
4667 RawMask.push_back((uint64_t)SM_SentinelUndef);
4670 auto *CN = dyn_cast<ConstantSDNode>(Op.getNode());
4673 APInt MaskElement = CN->getAPIntValue();
4675 // We now have to decode the element which could be any integer size and
4676 // extract each byte of it.
4677 for (int j = 0; j < NumBytesPerElement; ++j) {
4678 // Note that this is x86 and so always little endian: the low byte is
4679 // the first byte of the mask.
4680 RawMask.push_back(MaskElement.getLoBits(8).getZExtValue());
4681 MaskElement = MaskElement.lshr(8);
4684 DecodePSHUFBMask(RawMask, Mask);
4688 auto *MaskLoad = dyn_cast<LoadSDNode>(MaskNode);
4692 SDValue Ptr = MaskLoad->getBasePtr();
4693 if (Ptr->getOpcode() == X86ISD::Wrapper ||
4694 Ptr->getOpcode() == X86ISD::WrapperRIP)
4695 Ptr = Ptr->getOperand(0);
4697 auto *MaskCP = dyn_cast<ConstantPoolSDNode>(Ptr);
4698 if (!MaskCP || MaskCP->isMachineConstantPoolEntry())
4701 if (auto *C = dyn_cast<Constant>(MaskCP->getConstVal())) {
4702 DecodePSHUFBMask(C, Mask);
4710 case X86ISD::VPERMI:
4711 ImmN = N->getOperand(N->getNumOperands()-1);
4712 DecodeVPERMMask(cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4717 DecodeScalarMoveMask(VT, /* IsLoad */ false, Mask);
4719 case X86ISD::VPERM2X128:
4720 ImmN = N->getOperand(N->getNumOperands()-1);
4721 DecodeVPERM2X128Mask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4722 if (Mask.empty()) return false;
4723 // Mask only contains negative index if an element is zero.
4724 if (std::any_of(Mask.begin(), Mask.end(),
4725 [](int M){ return M == SM_SentinelZero; }))
4728 case X86ISD::MOVSLDUP:
4729 DecodeMOVSLDUPMask(VT, Mask);
4732 case X86ISD::MOVSHDUP:
4733 DecodeMOVSHDUPMask(VT, Mask);
4736 case X86ISD::MOVDDUP:
4737 DecodeMOVDDUPMask(VT, Mask);
4740 case X86ISD::MOVLHPD:
4741 case X86ISD::MOVLPD:
4742 case X86ISD::MOVLPS:
4743 // Not yet implemented
4745 case X86ISD::VPERMV: {
4747 SDValue MaskNode = N->getOperand(0);
4748 while (MaskNode->getOpcode() == ISD::BITCAST)
4749 MaskNode = MaskNode->getOperand(0);
4751 unsigned MaskLoBits = Log2_64(VT.getVectorNumElements());
4752 SmallVector<uint64_t, 32> RawMask;
4753 if (MaskNode->getOpcode() == ISD::BUILD_VECTOR) {
4754 // If we have a build-vector, then things are easy.
4755 assert(MaskNode.getValueType().isInteger() &&
4756 MaskNode.getValueType().getVectorNumElements() ==
4757 VT.getVectorNumElements());
4759 for (unsigned i = 0; i < MaskNode->getNumOperands(); ++i) {
4760 SDValue Op = MaskNode->getOperand(i);
4761 if (Op->getOpcode() == ISD::UNDEF)
4762 RawMask.push_back((uint64_t)SM_SentinelUndef);
4763 else if (isa<ConstantSDNode>(Op)) {
4764 APInt MaskElement = cast<ConstantSDNode>(Op)->getAPIntValue();
4765 RawMask.push_back(MaskElement.getLoBits(MaskLoBits).getZExtValue());
4769 DecodeVPERMVMask(RawMask, Mask);
4772 if (MaskNode->getOpcode() == X86ISD::VBROADCAST) {
4773 unsigned NumEltsInMask = MaskNode->getNumOperands();
4774 MaskNode = MaskNode->getOperand(0);
4775 auto *CN = dyn_cast<ConstantSDNode>(MaskNode);
4777 APInt MaskEltValue = CN->getAPIntValue();
4778 for (unsigned i = 0; i < NumEltsInMask; ++i)
4779 RawMask.push_back(MaskEltValue.getLoBits(MaskLoBits).getZExtValue());
4780 DecodeVPERMVMask(RawMask, Mask);
4783 // It may be a scalar load
4786 auto *MaskLoad = dyn_cast<LoadSDNode>(MaskNode);
4790 SDValue Ptr = MaskLoad->getBasePtr();
4791 if (Ptr->getOpcode() == X86ISD::Wrapper ||
4792 Ptr->getOpcode() == X86ISD::WrapperRIP)
4793 Ptr = Ptr->getOperand(0);
4795 auto *MaskCP = dyn_cast<ConstantPoolSDNode>(Ptr);
4796 if (!MaskCP || MaskCP->isMachineConstantPoolEntry())
4799 auto *C = dyn_cast<Constant>(MaskCP->getConstVal());
4801 DecodeVPERMVMask(C, VT, Mask);
4808 case X86ISD::VPERMV3: {
4810 SDValue MaskNode = N->getOperand(1);
4811 while (MaskNode->getOpcode() == ISD::BITCAST)
4812 MaskNode = MaskNode->getOperand(1);
4814 if (MaskNode->getOpcode() == ISD::BUILD_VECTOR) {
4815 // If we have a build-vector, then things are easy.
4816 assert(MaskNode.getValueType().isInteger() &&
4817 MaskNode.getValueType().getVectorNumElements() ==
4818 VT.getVectorNumElements());
4820 SmallVector<uint64_t, 32> RawMask;
4821 unsigned MaskLoBits = Log2_64(VT.getVectorNumElements()*2);
4823 for (unsigned i = 0; i < MaskNode->getNumOperands(); ++i) {
4824 SDValue Op = MaskNode->getOperand(i);
4825 if (Op->getOpcode() == ISD::UNDEF)
4826 RawMask.push_back((uint64_t)SM_SentinelUndef);
4828 auto *CN = dyn_cast<ConstantSDNode>(Op.getNode());
4831 APInt MaskElement = CN->getAPIntValue();
4832 RawMask.push_back(MaskElement.getLoBits(MaskLoBits).getZExtValue());
4835 DecodeVPERMV3Mask(RawMask, Mask);
4839 auto *MaskLoad = dyn_cast<LoadSDNode>(MaskNode);
4843 SDValue Ptr = MaskLoad->getBasePtr();
4844 if (Ptr->getOpcode() == X86ISD::Wrapper ||
4845 Ptr->getOpcode() == X86ISD::WrapperRIP)
4846 Ptr = Ptr->getOperand(0);
4848 auto *MaskCP = dyn_cast<ConstantPoolSDNode>(Ptr);
4849 if (!MaskCP || MaskCP->isMachineConstantPoolEntry())
4852 auto *C = dyn_cast<Constant>(MaskCP->getConstVal());
4854 DecodeVPERMV3Mask(C, VT, Mask);
4861 default: llvm_unreachable("unknown target shuffle node");
4864 // If we have a fake unary shuffle, the shuffle mask is spread across two
4865 // inputs that are actually the same node. Re-map the mask to always point
4866 // into the first input.
4869 if (M >= (int)Mask.size())
4875 /// Returns the scalar element that will make up the ith
4876 /// element of the result of the vector shuffle.
4877 static SDValue getShuffleScalarElt(SDNode *N, unsigned Index, SelectionDAG &DAG,
4880 return SDValue(); // Limit search depth.
4882 SDValue V = SDValue(N, 0);
4883 EVT VT = V.getValueType();
4884 unsigned Opcode = V.getOpcode();
4886 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars.
4887 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) {
4888 int Elt = SV->getMaskElt(Index);
4891 return DAG.getUNDEF(VT.getVectorElementType());
4893 unsigned NumElems = VT.getVectorNumElements();
4894 SDValue NewV = (Elt < (int)NumElems) ? SV->getOperand(0)
4895 : SV->getOperand(1);
4896 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG, Depth+1);
4899 // Recurse into target specific vector shuffles to find scalars.
4900 if (isTargetShuffle(Opcode)) {
4901 MVT ShufVT = V.getSimpleValueType();
4902 unsigned NumElems = ShufVT.getVectorNumElements();
4903 SmallVector<int, 16> ShuffleMask;
4906 if (!getTargetShuffleMask(N, ShufVT, ShuffleMask, IsUnary))
4909 int Elt = ShuffleMask[Index];
4911 return DAG.getUNDEF(ShufVT.getVectorElementType());
4913 SDValue NewV = (Elt < (int)NumElems) ? N->getOperand(0)
4915 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG,
4919 // Actual nodes that may contain scalar elements
4920 if (Opcode == ISD::BITCAST) {
4921 V = V.getOperand(0);
4922 EVT SrcVT = V.getValueType();
4923 unsigned NumElems = VT.getVectorNumElements();
4925 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems)
4929 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR)
4930 return (Index == 0) ? V.getOperand(0)
4931 : DAG.getUNDEF(VT.getVectorElementType());
4933 if (V.getOpcode() == ISD::BUILD_VECTOR)
4934 return V.getOperand(Index);
4939 /// Custom lower build_vector of v16i8.
4940 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
4941 unsigned NumNonZero, unsigned NumZero,
4943 const X86Subtarget* Subtarget,
4944 const TargetLowering &TLI) {
4952 // SSE4.1 - use PINSRB to insert each byte directly.
4953 if (Subtarget->hasSSE41()) {
4954 for (unsigned i = 0; i < 16; ++i) {
4955 bool isNonZero = (NonZeros & (1 << i)) != 0;
4959 V = getZeroVector(MVT::v16i8, Subtarget, DAG, dl);
4961 V = DAG.getUNDEF(MVT::v16i8);
4964 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
4965 MVT::v16i8, V, Op.getOperand(i),
4966 DAG.getIntPtrConstant(i, dl));
4973 // Pre-SSE4.1 - merge byte pairs and insert with PINSRW.
4974 for (unsigned i = 0; i < 16; ++i) {
4975 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
4976 if (ThisIsNonZero && First) {
4978 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
4980 V = DAG.getUNDEF(MVT::v8i16);
4985 SDValue ThisElt, LastElt;
4986 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
4987 if (LastIsNonZero) {
4988 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
4989 MVT::i16, Op.getOperand(i-1));
4991 if (ThisIsNonZero) {
4992 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
4993 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
4994 ThisElt, DAG.getConstant(8, dl, MVT::i8));
4996 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
5000 if (ThisElt.getNode())
5001 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
5002 DAG.getIntPtrConstant(i/2, dl));
5006 return DAG.getBitcast(MVT::v16i8, V);
5009 /// Custom lower build_vector of v8i16.
5010 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
5011 unsigned NumNonZero, unsigned NumZero,
5013 const X86Subtarget* Subtarget,
5014 const TargetLowering &TLI) {
5021 for (unsigned i = 0; i < 8; ++i) {
5022 bool isNonZero = (NonZeros & (1 << i)) != 0;
5026 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
5028 V = DAG.getUNDEF(MVT::v8i16);
5031 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
5032 MVT::v8i16, V, Op.getOperand(i),
5033 DAG.getIntPtrConstant(i, dl));
5040 /// Custom lower build_vector of v4i32 or v4f32.
5041 static SDValue LowerBuildVectorv4x32(SDValue Op, SelectionDAG &DAG,
5042 const X86Subtarget *Subtarget,
5043 const TargetLowering &TLI) {
5044 // Find all zeroable elements.
5045 std::bitset<4> Zeroable;
5046 for (int i=0; i < 4; ++i) {
5047 SDValue Elt = Op->getOperand(i);
5048 Zeroable[i] = (Elt.getOpcode() == ISD::UNDEF || X86::isZeroNode(Elt));
5050 assert(Zeroable.size() - Zeroable.count() > 1 &&
5051 "We expect at least two non-zero elements!");
5053 // We only know how to deal with build_vector nodes where elements are either
5054 // zeroable or extract_vector_elt with constant index.
5055 SDValue FirstNonZero;
5056 unsigned FirstNonZeroIdx;
5057 for (unsigned i=0; i < 4; ++i) {
5060 SDValue Elt = Op->getOperand(i);
5061 if (Elt.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
5062 !isa<ConstantSDNode>(Elt.getOperand(1)))
5064 // Make sure that this node is extracting from a 128-bit vector.
5065 MVT VT = Elt.getOperand(0).getSimpleValueType();
5066 if (!VT.is128BitVector())
5068 if (!FirstNonZero.getNode()) {
5070 FirstNonZeroIdx = i;
5074 assert(FirstNonZero.getNode() && "Unexpected build vector of all zeros!");
5075 SDValue V1 = FirstNonZero.getOperand(0);
5076 MVT VT = V1.getSimpleValueType();
5078 // See if this build_vector can be lowered as a blend with zero.
5080 unsigned EltMaskIdx, EltIdx;
5082 for (EltIdx = 0; EltIdx < 4; ++EltIdx) {
5083 if (Zeroable[EltIdx]) {
5084 // The zero vector will be on the right hand side.
5085 Mask[EltIdx] = EltIdx+4;
5089 Elt = Op->getOperand(EltIdx);
5090 // By construction, Elt is a EXTRACT_VECTOR_ELT with constant index.
5091 EltMaskIdx = cast<ConstantSDNode>(Elt.getOperand(1))->getZExtValue();
5092 if (Elt.getOperand(0) != V1 || EltMaskIdx != EltIdx)
5094 Mask[EltIdx] = EltIdx;
5098 // Let the shuffle legalizer deal with blend operations.
5099 SDValue VZero = getZeroVector(VT, Subtarget, DAG, SDLoc(Op));
5100 if (V1.getSimpleValueType() != VT)
5101 V1 = DAG.getNode(ISD::BITCAST, SDLoc(V1), VT, V1);
5102 return DAG.getVectorShuffle(VT, SDLoc(V1), V1, VZero, &Mask[0]);
5105 // See if we can lower this build_vector to a INSERTPS.
5106 if (!Subtarget->hasSSE41())
5109 SDValue V2 = Elt.getOperand(0);
5110 if (Elt == FirstNonZero && EltIdx == FirstNonZeroIdx)
5113 bool CanFold = true;
5114 for (unsigned i = EltIdx + 1; i < 4 && CanFold; ++i) {
5118 SDValue Current = Op->getOperand(i);
5119 SDValue SrcVector = Current->getOperand(0);
5122 CanFold = SrcVector == V1 &&
5123 cast<ConstantSDNode>(Current.getOperand(1))->getZExtValue() == i;
5129 assert(V1.getNode() && "Expected at least two non-zero elements!");
5130 if (V1.getSimpleValueType() != MVT::v4f32)
5131 V1 = DAG.getNode(ISD::BITCAST, SDLoc(V1), MVT::v4f32, V1);
5132 if (V2.getSimpleValueType() != MVT::v4f32)
5133 V2 = DAG.getNode(ISD::BITCAST, SDLoc(V2), MVT::v4f32, V2);
5135 // Ok, we can emit an INSERTPS instruction.
5136 unsigned ZMask = Zeroable.to_ulong();
5138 unsigned InsertPSMask = EltMaskIdx << 6 | EltIdx << 4 | ZMask;
5139 assert((InsertPSMask & ~0xFFu) == 0 && "Invalid mask!");
5141 SDValue Result = DAG.getNode(X86ISD::INSERTPS, DL, MVT::v4f32, V1, V2,
5142 DAG.getIntPtrConstant(InsertPSMask, DL));
5143 return DAG.getBitcast(VT, Result);
5146 /// Return a vector logical shift node.
5147 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
5148 unsigned NumBits, SelectionDAG &DAG,
5149 const TargetLowering &TLI, SDLoc dl) {
5150 assert(VT.is128BitVector() && "Unknown type for VShift");
5151 MVT ShVT = MVT::v2i64;
5152 unsigned Opc = isLeft ? X86ISD::VSHLDQ : X86ISD::VSRLDQ;
5153 SrcOp = DAG.getBitcast(ShVT, SrcOp);
5154 MVT ScalarShiftTy = TLI.getScalarShiftAmountTy(DAG.getDataLayout(), VT);
5155 assert(NumBits % 8 == 0 && "Only support byte sized shifts");
5156 SDValue ShiftVal = DAG.getConstant(NumBits/8, dl, ScalarShiftTy);
5157 return DAG.getBitcast(VT, DAG.getNode(Opc, dl, ShVT, SrcOp, ShiftVal));
5161 LowerAsSplatVectorLoad(SDValue SrcOp, MVT VT, SDLoc dl, SelectionDAG &DAG) {
5163 // Check if the scalar load can be widened into a vector load. And if
5164 // the address is "base + cst" see if the cst can be "absorbed" into
5165 // the shuffle mask.
5166 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) {
5167 SDValue Ptr = LD->getBasePtr();
5168 if (!ISD::isNormalLoad(LD) || LD->isVolatile())
5170 EVT PVT = LD->getValueType(0);
5171 if (PVT != MVT::i32 && PVT != MVT::f32)
5176 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) {
5177 FI = FINode->getIndex();
5179 } else if (DAG.isBaseWithConstantOffset(Ptr) &&
5180 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
5181 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
5182 Offset = Ptr.getConstantOperandVal(1);
5183 Ptr = Ptr.getOperand(0);
5188 // FIXME: 256-bit vector instructions don't require a strict alignment,
5189 // improve this code to support it better.
5190 unsigned RequiredAlign = VT.getSizeInBits()/8;
5191 SDValue Chain = LD->getChain();
5192 // Make sure the stack object alignment is at least 16 or 32.
5193 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
5194 if (DAG.InferPtrAlignment(Ptr) < RequiredAlign) {
5195 if (MFI->isFixedObjectIndex(FI)) {
5196 // Can't change the alignment. FIXME: It's possible to compute
5197 // the exact stack offset and reference FI + adjust offset instead.
5198 // If someone *really* cares about this. That's the way to implement it.
5201 MFI->setObjectAlignment(FI, RequiredAlign);
5205 // (Offset % 16 or 32) must be multiple of 4. Then address is then
5206 // Ptr + (Offset & ~15).
5209 if ((Offset % RequiredAlign) & 3)
5211 int64_t StartOffset = Offset & ~int64_t(RequiredAlign - 1);
5214 Ptr = DAG.getNode(ISD::ADD, DL, Ptr.getValueType(), Ptr,
5215 DAG.getConstant(StartOffset, DL, Ptr.getValueType()));
5218 int EltNo = (Offset - StartOffset) >> 2;
5219 unsigned NumElems = VT.getVectorNumElements();
5221 EVT NVT = EVT::getVectorVT(*DAG.getContext(), PVT, NumElems);
5222 SDValue V1 = DAG.getLoad(NVT, dl, Chain, Ptr,
5223 LD->getPointerInfo().getWithOffset(StartOffset),
5224 false, false, false, 0);
5226 SmallVector<int, 8> Mask(NumElems, EltNo);
5228 return DAG.getVectorShuffle(NVT, dl, V1, DAG.getUNDEF(NVT), &Mask[0]);
5234 /// Given the initializing elements 'Elts' of a vector of type 'VT', see if the
5235 /// elements can be replaced by a single large load which has the same value as
5236 /// a build_vector or insert_subvector whose loaded operands are 'Elts'.
5238 /// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a
5240 /// FIXME: we'd also like to handle the case where the last elements are zero
5241 /// rather than undef via VZEXT_LOAD, but we do not detect that case today.
5242 /// There's even a handy isZeroNode for that purpose.
5243 static SDValue EltsFromConsecutiveLoads(EVT VT, ArrayRef<SDValue> Elts,
5244 SDLoc &DL, SelectionDAG &DAG,
5245 bool isAfterLegalize) {
5246 unsigned NumElems = Elts.size();
5248 LoadSDNode *LDBase = nullptr;
5249 unsigned LastLoadedElt = -1U;
5251 // For each element in the initializer, see if we've found a load or an undef.
5252 // If we don't find an initial load element, or later load elements are
5253 // non-consecutive, bail out.
5254 for (unsigned i = 0; i < NumElems; ++i) {
5255 SDValue Elt = Elts[i];
5256 // Look through a bitcast.
5257 if (Elt.getNode() && Elt.getOpcode() == ISD::BITCAST)
5258 Elt = Elt.getOperand(0);
5259 if (!Elt.getNode() ||
5260 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
5263 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
5265 LDBase = cast<LoadSDNode>(Elt.getNode());
5269 if (Elt.getOpcode() == ISD::UNDEF)
5272 LoadSDNode *LD = cast<LoadSDNode>(Elt);
5273 EVT LdVT = Elt.getValueType();
5274 // Each loaded element must be the correct fractional portion of the
5275 // requested vector load.
5276 if (LdVT.getSizeInBits() != VT.getSizeInBits() / NumElems)
5278 if (!DAG.isConsecutiveLoad(LD, LDBase, LdVT.getSizeInBits() / 8, i))
5283 // If we have found an entire vector of loads and undefs, then return a large
5284 // load of the entire vector width starting at the base pointer. If we found
5285 // consecutive loads for the low half, generate a vzext_load node.
5286 if (LastLoadedElt == NumElems - 1) {
5287 assert(LDBase && "Did not find base load for merging consecutive loads");
5288 EVT EltVT = LDBase->getValueType(0);
5289 // Ensure that the input vector size for the merged loads matches the
5290 // cumulative size of the input elements.
5291 if (VT.getSizeInBits() != EltVT.getSizeInBits() * NumElems)
5294 if (isAfterLegalize &&
5295 !DAG.getTargetLoweringInfo().isOperationLegal(ISD::LOAD, VT))
5298 SDValue NewLd = SDValue();
5300 NewLd = DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
5301 LDBase->getPointerInfo(), LDBase->isVolatile(),
5302 LDBase->isNonTemporal(), LDBase->isInvariant(),
5303 LDBase->getAlignment());
5305 if (LDBase->hasAnyUseOfValue(1)) {
5306 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
5308 SDValue(NewLd.getNode(), 1));
5309 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
5310 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
5311 SDValue(NewLd.getNode(), 1));
5317 //TODO: The code below fires only for for loading the low v2i32 / v2f32
5318 //of a v4i32 / v4f32. It's probably worth generalizing.
5319 EVT EltVT = VT.getVectorElementType();
5320 if (NumElems == 4 && LastLoadedElt == 1 && (EltVT.getSizeInBits() == 32) &&
5321 DAG.getTargetLoweringInfo().isTypeLegal(MVT::v2i64)) {
5322 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
5323 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() };
5325 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys, Ops, MVT::i64,
5326 LDBase->getPointerInfo(),
5327 LDBase->getAlignment(),
5328 false/*isVolatile*/, true/*ReadMem*/,
5331 // Make sure the newly-created LOAD is in the same position as LDBase in
5332 // terms of dependency. We create a TokenFactor for LDBase and ResNode, and
5333 // update uses of LDBase's output chain to use the TokenFactor.
5334 if (LDBase->hasAnyUseOfValue(1)) {
5335 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
5336 SDValue(LDBase, 1), SDValue(ResNode.getNode(), 1));
5337 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
5338 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
5339 SDValue(ResNode.getNode(), 1));
5342 return DAG.getBitcast(VT, ResNode);
5347 /// LowerVectorBroadcast - Attempt to use the vbroadcast instruction
5348 /// to generate a splat value for the following cases:
5349 /// 1. A splat BUILD_VECTOR which uses a single scalar load, or a constant.
5350 /// 2. A splat shuffle which uses a scalar_to_vector node which comes from
5351 /// a scalar load, or a constant.
5352 /// The VBROADCAST node is returned when a pattern is found,
5353 /// or SDValue() otherwise.
5354 static SDValue LowerVectorBroadcast(SDValue Op, const X86Subtarget* Subtarget,
5355 SelectionDAG &DAG) {
5356 // VBROADCAST requires AVX.
5357 // TODO: Splats could be generated for non-AVX CPUs using SSE
5358 // instructions, but there's less potential gain for only 128-bit vectors.
5359 if (!Subtarget->hasAVX())
5362 MVT VT = Op.getSimpleValueType();
5365 assert((VT.is128BitVector() || VT.is256BitVector() || VT.is512BitVector()) &&
5366 "Unsupported vector type for broadcast.");
5371 switch (Op.getOpcode()) {
5373 // Unknown pattern found.
5376 case ISD::BUILD_VECTOR: {
5377 auto *BVOp = cast<BuildVectorSDNode>(Op.getNode());
5378 BitVector UndefElements;
5379 SDValue Splat = BVOp->getSplatValue(&UndefElements);
5381 // We need a splat of a single value to use broadcast, and it doesn't
5382 // make any sense if the value is only in one element of the vector.
5383 if (!Splat || (VT.getVectorNumElements() - UndefElements.count()) <= 1)
5387 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
5388 Ld.getOpcode() == ISD::ConstantFP);
5390 // Make sure that all of the users of a non-constant load are from the
5391 // BUILD_VECTOR node.
5392 if (!ConstSplatVal && !BVOp->isOnlyUserOf(Ld.getNode()))
5397 case ISD::VECTOR_SHUFFLE: {
5398 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
5400 // Shuffles must have a splat mask where the first element is
5402 if ((!SVOp->isSplat()) || SVOp->getMaskElt(0) != 0)
5405 SDValue Sc = Op.getOperand(0);
5406 if (Sc.getOpcode() != ISD::SCALAR_TO_VECTOR &&
5407 Sc.getOpcode() != ISD::BUILD_VECTOR) {
5409 if (!Subtarget->hasInt256())
5412 // Use the register form of the broadcast instruction available on AVX2.
5413 if (VT.getSizeInBits() >= 256)
5414 Sc = Extract128BitVector(Sc, 0, DAG, dl);
5415 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Sc);
5418 Ld = Sc.getOperand(0);
5419 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
5420 Ld.getOpcode() == ISD::ConstantFP);
5422 // The scalar_to_vector node and the suspected
5423 // load node must have exactly one user.
5424 // Constants may have multiple users.
5426 // AVX-512 has register version of the broadcast
5427 bool hasRegVer = Subtarget->hasAVX512() && VT.is512BitVector() &&
5428 Ld.getValueType().getSizeInBits() >= 32;
5429 if (!ConstSplatVal && ((!Sc.hasOneUse() || !Ld.hasOneUse()) &&
5436 unsigned ScalarSize = Ld.getValueType().getSizeInBits();
5437 bool IsGE256 = (VT.getSizeInBits() >= 256);
5439 // When optimizing for size, generate up to 5 extra bytes for a broadcast
5440 // instruction to save 8 or more bytes of constant pool data.
5441 // TODO: If multiple splats are generated to load the same constant,
5442 // it may be detrimental to overall size. There needs to be a way to detect
5443 // that condition to know if this is truly a size win.
5444 bool OptForSize = DAG.getMachineFunction().getFunction()->optForSize();
5446 // Handle broadcasting a single constant scalar from the constant pool
5448 // On Sandybridge (no AVX2), it is still better to load a constant vector
5449 // from the constant pool and not to broadcast it from a scalar.
5450 // But override that restriction when optimizing for size.
5451 // TODO: Check if splatting is recommended for other AVX-capable CPUs.
5452 if (ConstSplatVal && (Subtarget->hasAVX2() || OptForSize)) {
5453 EVT CVT = Ld.getValueType();
5454 assert(!CVT.isVector() && "Must not broadcast a vector type");
5456 // Splat f32, i32, v4f64, v4i64 in all cases with AVX2.
5457 // For size optimization, also splat v2f64 and v2i64, and for size opt
5458 // with AVX2, also splat i8 and i16.
5459 // With pattern matching, the VBROADCAST node may become a VMOVDDUP.
5460 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64) ||
5461 (OptForSize && (ScalarSize == 64 || Subtarget->hasAVX2()))) {
5462 const Constant *C = nullptr;
5463 if (ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Ld))
5464 C = CI->getConstantIntValue();
5465 else if (ConstantFPSDNode *CF = dyn_cast<ConstantFPSDNode>(Ld))
5466 C = CF->getConstantFPValue();
5468 assert(C && "Invalid constant type");
5470 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5472 DAG.getConstantPool(C, TLI.getPointerTy(DAG.getDataLayout()));
5473 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
5475 CVT, dl, DAG.getEntryNode(), CP,
5476 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()), false,
5477 false, false, Alignment);
5479 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5483 bool IsLoad = ISD::isNormalLoad(Ld.getNode());
5485 // Handle AVX2 in-register broadcasts.
5486 if (!IsLoad && Subtarget->hasInt256() &&
5487 (ScalarSize == 32 || (IsGE256 && ScalarSize == 64)))
5488 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5490 // The scalar source must be a normal load.
5494 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64) ||
5495 (Subtarget->hasVLX() && ScalarSize == 64))
5496 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5498 // The integer check is needed for the 64-bit into 128-bit so it doesn't match
5499 // double since there is no vbroadcastsd xmm
5500 if (Subtarget->hasInt256() && Ld.getValueType().isInteger()) {
5501 if (ScalarSize == 8 || ScalarSize == 16 || ScalarSize == 64)
5502 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5505 // Unsupported broadcast.
5509 /// \brief For an EXTRACT_VECTOR_ELT with a constant index return the real
5510 /// underlying vector and index.
5512 /// Modifies \p ExtractedFromVec to the real vector and returns the real
5514 static int getUnderlyingExtractedFromVec(SDValue &ExtractedFromVec,
5516 int Idx = cast<ConstantSDNode>(ExtIdx)->getZExtValue();
5517 if (!isa<ShuffleVectorSDNode>(ExtractedFromVec))
5520 // For 256-bit vectors, LowerEXTRACT_VECTOR_ELT_SSE4 may have already
5522 // (extract_vector_elt (v8f32 %vreg1), Constant<6>)
5524 // (extract_vector_elt (vector_shuffle<2,u,u,u>
5525 // (extract_subvector (v8f32 %vreg0), Constant<4>),
5528 // In this case the vector is the extract_subvector expression and the index
5529 // is 2, as specified by the shuffle.
5530 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(ExtractedFromVec);
5531 SDValue ShuffleVec = SVOp->getOperand(0);
5532 MVT ShuffleVecVT = ShuffleVec.getSimpleValueType();
5533 assert(ShuffleVecVT.getVectorElementType() ==
5534 ExtractedFromVec.getSimpleValueType().getVectorElementType());
5536 int ShuffleIdx = SVOp->getMaskElt(Idx);
5537 if (isUndefOrInRange(ShuffleIdx, 0, ShuffleVecVT.getVectorNumElements())) {
5538 ExtractedFromVec = ShuffleVec;
5544 static SDValue buildFromShuffleMostly(SDValue Op, SelectionDAG &DAG) {
5545 MVT VT = Op.getSimpleValueType();
5547 // Skip if insert_vec_elt is not supported.
5548 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5549 if (!TLI.isOperationLegalOrCustom(ISD::INSERT_VECTOR_ELT, VT))
5553 unsigned NumElems = Op.getNumOperands();
5557 SmallVector<unsigned, 4> InsertIndices;
5558 SmallVector<int, 8> Mask(NumElems, -1);
5560 for (unsigned i = 0; i != NumElems; ++i) {
5561 unsigned Opc = Op.getOperand(i).getOpcode();
5563 if (Opc == ISD::UNDEF)
5566 if (Opc != ISD::EXTRACT_VECTOR_ELT) {
5567 // Quit if more than 1 elements need inserting.
5568 if (InsertIndices.size() > 1)
5571 InsertIndices.push_back(i);
5575 SDValue ExtractedFromVec = Op.getOperand(i).getOperand(0);
5576 SDValue ExtIdx = Op.getOperand(i).getOperand(1);
5577 // Quit if non-constant index.
5578 if (!isa<ConstantSDNode>(ExtIdx))
5580 int Idx = getUnderlyingExtractedFromVec(ExtractedFromVec, ExtIdx);
5582 // Quit if extracted from vector of different type.
5583 if (ExtractedFromVec.getValueType() != VT)
5586 if (!VecIn1.getNode())
5587 VecIn1 = ExtractedFromVec;
5588 else if (VecIn1 != ExtractedFromVec) {
5589 if (!VecIn2.getNode())
5590 VecIn2 = ExtractedFromVec;
5591 else if (VecIn2 != ExtractedFromVec)
5592 // Quit if more than 2 vectors to shuffle
5596 if (ExtractedFromVec == VecIn1)
5598 else if (ExtractedFromVec == VecIn2)
5599 Mask[i] = Idx + NumElems;
5602 if (!VecIn1.getNode())
5605 VecIn2 = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT);
5606 SDValue NV = DAG.getVectorShuffle(VT, DL, VecIn1, VecIn2, &Mask[0]);
5607 for (unsigned i = 0, e = InsertIndices.size(); i != e; ++i) {
5608 unsigned Idx = InsertIndices[i];
5609 NV = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VT, NV, Op.getOperand(Idx),
5610 DAG.getIntPtrConstant(Idx, DL));
5616 static SDValue ConvertI1VectorToInteger(SDValue Op, SelectionDAG &DAG) {
5617 assert(ISD::isBuildVectorOfConstantSDNodes(Op.getNode()) &&
5618 Op.getScalarValueSizeInBits() == 1 &&
5619 "Can not convert non-constant vector");
5620 uint64_t Immediate = 0;
5621 for (unsigned idx = 0, e = Op.getNumOperands(); idx < e; ++idx) {
5622 SDValue In = Op.getOperand(idx);
5623 if (In.getOpcode() != ISD::UNDEF)
5624 Immediate |= cast<ConstantSDNode>(In)->getZExtValue() << idx;
5628 MVT::getIntegerVT(std::max((int)Op.getValueType().getSizeInBits(), 8));
5629 return DAG.getConstant(Immediate, dl, VT);
5631 // Lower BUILD_VECTOR operation for v8i1 and v16i1 types.
5633 X86TargetLowering::LowerBUILD_VECTORvXi1(SDValue Op, SelectionDAG &DAG) const {
5635 MVT VT = Op.getSimpleValueType();
5636 assert((VT.getVectorElementType() == MVT::i1) &&
5637 "Unexpected type in LowerBUILD_VECTORvXi1!");
5640 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
5641 SDValue Cst = DAG.getTargetConstant(0, dl, MVT::i1);
5642 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
5643 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
5646 if (ISD::isBuildVectorAllOnes(Op.getNode())) {
5647 SDValue Cst = DAG.getTargetConstant(1, dl, MVT::i1);
5648 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
5649 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
5652 if (ISD::isBuildVectorOfConstantSDNodes(Op.getNode())) {
5653 SDValue Imm = ConvertI1VectorToInteger(Op, DAG);
5654 if (Imm.getValueSizeInBits() == VT.getSizeInBits())
5655 return DAG.getBitcast(VT, Imm);
5656 SDValue ExtVec = DAG.getBitcast(MVT::v8i1, Imm);
5657 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, ExtVec,
5658 DAG.getIntPtrConstant(0, dl));
5661 // Vector has one or more non-const elements
5662 uint64_t Immediate = 0;
5663 SmallVector<unsigned, 16> NonConstIdx;
5664 bool IsSplat = true;
5665 bool HasConstElts = false;
5667 for (unsigned idx = 0, e = Op.getNumOperands(); idx < e; ++idx) {
5668 SDValue In = Op.getOperand(idx);
5669 if (In.getOpcode() == ISD::UNDEF)
5671 if (!isa<ConstantSDNode>(In))
5672 NonConstIdx.push_back(idx);
5674 Immediate |= cast<ConstantSDNode>(In)->getZExtValue() << idx;
5675 HasConstElts = true;
5679 else if (In != Op.getOperand(SplatIdx))
5683 // for splat use " (select i1 splat_elt, all-ones, all-zeroes)"
5685 return DAG.getNode(ISD::SELECT, dl, VT, Op.getOperand(SplatIdx),
5686 DAG.getConstant(1, dl, VT),
5687 DAG.getConstant(0, dl, VT));
5689 // insert elements one by one
5693 MVT ImmVT = MVT::getIntegerVT(std::max((int)VT.getSizeInBits(), 8));
5694 Imm = DAG.getConstant(Immediate, dl, ImmVT);
5696 else if (HasConstElts)
5697 Imm = DAG.getConstant(0, dl, VT);
5699 Imm = DAG.getUNDEF(VT);
5700 if (Imm.getValueSizeInBits() == VT.getSizeInBits())
5701 DstVec = DAG.getBitcast(VT, Imm);
5703 SDValue ExtVec = DAG.getBitcast(MVT::v8i1, Imm);
5704 DstVec = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, ExtVec,
5705 DAG.getIntPtrConstant(0, dl));
5708 for (unsigned i = 0; i < NonConstIdx.size(); ++i) {
5709 unsigned InsertIdx = NonConstIdx[i];
5710 DstVec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, DstVec,
5711 Op.getOperand(InsertIdx),
5712 DAG.getIntPtrConstant(InsertIdx, dl));
5717 /// \brief Return true if \p N implements a horizontal binop and return the
5718 /// operands for the horizontal binop into V0 and V1.
5720 /// This is a helper function of LowerToHorizontalOp().
5721 /// This function checks that the build_vector \p N in input implements a
5722 /// horizontal operation. Parameter \p Opcode defines the kind of horizontal
5723 /// operation to match.
5724 /// For example, if \p Opcode is equal to ISD::ADD, then this function
5725 /// checks if \p N implements a horizontal arithmetic add; if instead \p Opcode
5726 /// is equal to ISD::SUB, then this function checks if this is a horizontal
5729 /// This function only analyzes elements of \p N whose indices are
5730 /// in range [BaseIdx, LastIdx).
5731 static bool isHorizontalBinOp(const BuildVectorSDNode *N, unsigned Opcode,
5733 unsigned BaseIdx, unsigned LastIdx,
5734 SDValue &V0, SDValue &V1) {
5735 EVT VT = N->getValueType(0);
5737 assert(BaseIdx * 2 <= LastIdx && "Invalid Indices in input!");
5738 assert(VT.isVector() && VT.getVectorNumElements() >= LastIdx &&
5739 "Invalid Vector in input!");
5741 bool IsCommutable = (Opcode == ISD::ADD || Opcode == ISD::FADD);
5742 bool CanFold = true;
5743 unsigned ExpectedVExtractIdx = BaseIdx;
5744 unsigned NumElts = LastIdx - BaseIdx;
5745 V0 = DAG.getUNDEF(VT);
5746 V1 = DAG.getUNDEF(VT);
5748 // Check if N implements a horizontal binop.
5749 for (unsigned i = 0, e = NumElts; i != e && CanFold; ++i) {
5750 SDValue Op = N->getOperand(i + BaseIdx);
5753 if (Op->getOpcode() == ISD::UNDEF) {
5754 // Update the expected vector extract index.
5755 if (i * 2 == NumElts)
5756 ExpectedVExtractIdx = BaseIdx;
5757 ExpectedVExtractIdx += 2;
5761 CanFold = Op->getOpcode() == Opcode && Op->hasOneUse();
5766 SDValue Op0 = Op.getOperand(0);
5767 SDValue Op1 = Op.getOperand(1);
5769 // Try to match the following pattern:
5770 // (BINOP (extract_vector_elt A, I), (extract_vector_elt A, I+1))
5771 CanFold = (Op0.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
5772 Op1.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
5773 Op0.getOperand(0) == Op1.getOperand(0) &&
5774 isa<ConstantSDNode>(Op0.getOperand(1)) &&
5775 isa<ConstantSDNode>(Op1.getOperand(1)));
5779 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
5780 unsigned I1 = cast<ConstantSDNode>(Op1.getOperand(1))->getZExtValue();
5782 if (i * 2 < NumElts) {
5783 if (V0.getOpcode() == ISD::UNDEF) {
5784 V0 = Op0.getOperand(0);
5785 if (V0.getValueType() != VT)
5789 if (V1.getOpcode() == ISD::UNDEF) {
5790 V1 = Op0.getOperand(0);
5791 if (V1.getValueType() != VT)
5794 if (i * 2 == NumElts)
5795 ExpectedVExtractIdx = BaseIdx;
5798 SDValue Expected = (i * 2 < NumElts) ? V0 : V1;
5799 if (I0 == ExpectedVExtractIdx)
5800 CanFold = I1 == I0 + 1 && Op0.getOperand(0) == Expected;
5801 else if (IsCommutable && I1 == ExpectedVExtractIdx) {
5802 // Try to match the following dag sequence:
5803 // (BINOP (extract_vector_elt A, I+1), (extract_vector_elt A, I))
5804 CanFold = I0 == I1 + 1 && Op1.getOperand(0) == Expected;
5808 ExpectedVExtractIdx += 2;
5814 /// \brief Emit a sequence of two 128-bit horizontal add/sub followed by
5815 /// a concat_vector.
5817 /// This is a helper function of LowerToHorizontalOp().
5818 /// This function expects two 256-bit vectors called V0 and V1.
5819 /// At first, each vector is split into two separate 128-bit vectors.
5820 /// Then, the resulting 128-bit vectors are used to implement two
5821 /// horizontal binary operations.
5823 /// The kind of horizontal binary operation is defined by \p X86Opcode.
5825 /// \p Mode specifies how the 128-bit parts of V0 and V1 are passed in input to
5826 /// the two new horizontal binop.
5827 /// When Mode is set, the first horizontal binop dag node would take as input
5828 /// the lower 128-bit of V0 and the upper 128-bit of V0. The second
5829 /// horizontal binop dag node would take as input the lower 128-bit of V1
5830 /// and the upper 128-bit of V1.
5832 /// HADD V0_LO, V0_HI
5833 /// HADD V1_LO, V1_HI
5835 /// Otherwise, the first horizontal binop dag node takes as input the lower
5836 /// 128-bit of V0 and the lower 128-bit of V1, and the second horizontal binop
5837 /// dag node takes the upper 128-bit of V0 and the upper 128-bit of V1.
5839 /// HADD V0_LO, V1_LO
5840 /// HADD V0_HI, V1_HI
5842 /// If \p isUndefLO is set, then the algorithm propagates UNDEF to the lower
5843 /// 128-bits of the result. If \p isUndefHI is set, then UNDEF is propagated to
5844 /// the upper 128-bits of the result.
5845 static SDValue ExpandHorizontalBinOp(const SDValue &V0, const SDValue &V1,
5846 SDLoc DL, SelectionDAG &DAG,
5847 unsigned X86Opcode, bool Mode,
5848 bool isUndefLO, bool isUndefHI) {
5849 EVT VT = V0.getValueType();
5850 assert(VT.is256BitVector() && VT == V1.getValueType() &&
5851 "Invalid nodes in input!");
5853 unsigned NumElts = VT.getVectorNumElements();
5854 SDValue V0_LO = Extract128BitVector(V0, 0, DAG, DL);
5855 SDValue V0_HI = Extract128BitVector(V0, NumElts/2, DAG, DL);
5856 SDValue V1_LO = Extract128BitVector(V1, 0, DAG, DL);
5857 SDValue V1_HI = Extract128BitVector(V1, NumElts/2, DAG, DL);
5858 EVT NewVT = V0_LO.getValueType();
5860 SDValue LO = DAG.getUNDEF(NewVT);
5861 SDValue HI = DAG.getUNDEF(NewVT);
5864 // Don't emit a horizontal binop if the result is expected to be UNDEF.
5865 if (!isUndefLO && V0->getOpcode() != ISD::UNDEF)
5866 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V0_HI);
5867 if (!isUndefHI && V1->getOpcode() != ISD::UNDEF)
5868 HI = DAG.getNode(X86Opcode, DL, NewVT, V1_LO, V1_HI);
5870 // Don't emit a horizontal binop if the result is expected to be UNDEF.
5871 if (!isUndefLO && (V0_LO->getOpcode() != ISD::UNDEF ||
5872 V1_LO->getOpcode() != ISD::UNDEF))
5873 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V1_LO);
5875 if (!isUndefHI && (V0_HI->getOpcode() != ISD::UNDEF ||
5876 V1_HI->getOpcode() != ISD::UNDEF))
5877 HI = DAG.getNode(X86Opcode, DL, NewVT, V0_HI, V1_HI);
5880 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LO, HI);
5883 /// Try to fold a build_vector that performs an 'addsub' to an X86ISD::ADDSUB
5885 static SDValue LowerToAddSub(const BuildVectorSDNode *BV,
5886 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
5887 EVT VT = BV->getValueType(0);
5888 if ((!Subtarget->hasSSE3() || (VT != MVT::v4f32 && VT != MVT::v2f64)) &&
5889 (!Subtarget->hasAVX() || (VT != MVT::v8f32 && VT != MVT::v4f64)))
5893 unsigned NumElts = VT.getVectorNumElements();
5894 SDValue InVec0 = DAG.getUNDEF(VT);
5895 SDValue InVec1 = DAG.getUNDEF(VT);
5897 assert((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v4f32 ||
5898 VT == MVT::v2f64) && "build_vector with an invalid type found!");
5900 // Odd-numbered elements in the input build vector are obtained from
5901 // adding two integer/float elements.
5902 // Even-numbered elements in the input build vector are obtained from
5903 // subtracting two integer/float elements.
5904 unsigned ExpectedOpcode = ISD::FSUB;
5905 unsigned NextExpectedOpcode = ISD::FADD;
5906 bool AddFound = false;
5907 bool SubFound = false;
5909 for (unsigned i = 0, e = NumElts; i != e; ++i) {
5910 SDValue Op = BV->getOperand(i);
5912 // Skip 'undef' values.
5913 unsigned Opcode = Op.getOpcode();
5914 if (Opcode == ISD::UNDEF) {
5915 std::swap(ExpectedOpcode, NextExpectedOpcode);
5919 // Early exit if we found an unexpected opcode.
5920 if (Opcode != ExpectedOpcode)
5923 SDValue Op0 = Op.getOperand(0);
5924 SDValue Op1 = Op.getOperand(1);
5926 // Try to match the following pattern:
5927 // (BINOP (extract_vector_elt A, i), (extract_vector_elt B, i))
5928 // Early exit if we cannot match that sequence.
5929 if (Op0.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
5930 Op1.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
5931 !isa<ConstantSDNode>(Op0.getOperand(1)) ||
5932 !isa<ConstantSDNode>(Op1.getOperand(1)) ||
5933 Op0.getOperand(1) != Op1.getOperand(1))
5936 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
5940 // We found a valid add/sub node. Update the information accordingly.
5946 // Update InVec0 and InVec1.
5947 if (InVec0.getOpcode() == ISD::UNDEF) {
5948 InVec0 = Op0.getOperand(0);
5949 if (InVec0.getValueType() != VT)
5952 if (InVec1.getOpcode() == ISD::UNDEF) {
5953 InVec1 = Op1.getOperand(0);
5954 if (InVec1.getValueType() != VT)
5958 // Make sure that operands in input to each add/sub node always
5959 // come from a same pair of vectors.
5960 if (InVec0 != Op0.getOperand(0)) {
5961 if (ExpectedOpcode == ISD::FSUB)
5964 // FADD is commutable. Try to commute the operands
5965 // and then test again.
5966 std::swap(Op0, Op1);
5967 if (InVec0 != Op0.getOperand(0))
5971 if (InVec1 != Op1.getOperand(0))
5974 // Update the pair of expected opcodes.
5975 std::swap(ExpectedOpcode, NextExpectedOpcode);
5978 // Don't try to fold this build_vector into an ADDSUB if the inputs are undef.
5979 if (AddFound && SubFound && InVec0.getOpcode() != ISD::UNDEF &&
5980 InVec1.getOpcode() != ISD::UNDEF)
5981 return DAG.getNode(X86ISD::ADDSUB, DL, VT, InVec0, InVec1);
5986 /// Lower BUILD_VECTOR to a horizontal add/sub operation if possible.
5987 static SDValue LowerToHorizontalOp(const BuildVectorSDNode *BV,
5988 const X86Subtarget *Subtarget,
5989 SelectionDAG &DAG) {
5990 EVT VT = BV->getValueType(0);
5991 unsigned NumElts = VT.getVectorNumElements();
5992 unsigned NumUndefsLO = 0;
5993 unsigned NumUndefsHI = 0;
5994 unsigned Half = NumElts/2;
5996 // Count the number of UNDEF operands in the build_vector in input.
5997 for (unsigned i = 0, e = Half; i != e; ++i)
5998 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
6001 for (unsigned i = Half, e = NumElts; i != e; ++i)
6002 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
6005 // Early exit if this is either a build_vector of all UNDEFs or all the
6006 // operands but one are UNDEF.
6007 if (NumUndefsLO + NumUndefsHI + 1 >= NumElts)
6011 SDValue InVec0, InVec1;
6012 if ((VT == MVT::v4f32 || VT == MVT::v2f64) && Subtarget->hasSSE3()) {
6013 // Try to match an SSE3 float HADD/HSUB.
6014 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
6015 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
6017 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
6018 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
6019 } else if ((VT == MVT::v4i32 || VT == MVT::v8i16) && Subtarget->hasSSSE3()) {
6020 // Try to match an SSSE3 integer HADD/HSUB.
6021 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
6022 return DAG.getNode(X86ISD::HADD, DL, VT, InVec0, InVec1);
6024 if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
6025 return DAG.getNode(X86ISD::HSUB, DL, VT, InVec0, InVec1);
6028 if (!Subtarget->hasAVX())
6031 if ((VT == MVT::v8f32 || VT == MVT::v4f64)) {
6032 // Try to match an AVX horizontal add/sub of packed single/double
6033 // precision floating point values from 256-bit vectors.
6034 SDValue InVec2, InVec3;
6035 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, Half, InVec0, InVec1) &&
6036 isHorizontalBinOp(BV, ISD::FADD, DAG, Half, NumElts, InVec2, InVec3) &&
6037 ((InVec0.getOpcode() == ISD::UNDEF ||
6038 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6039 ((InVec1.getOpcode() == ISD::UNDEF ||
6040 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6041 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
6043 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, Half, InVec0, InVec1) &&
6044 isHorizontalBinOp(BV, ISD::FSUB, DAG, Half, NumElts, InVec2, InVec3) &&
6045 ((InVec0.getOpcode() == ISD::UNDEF ||
6046 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6047 ((InVec1.getOpcode() == ISD::UNDEF ||
6048 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6049 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
6050 } else if (VT == MVT::v8i32 || VT == MVT::v16i16) {
6051 // Try to match an AVX2 horizontal add/sub of signed integers.
6052 SDValue InVec2, InVec3;
6054 bool CanFold = true;
6056 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, Half, InVec0, InVec1) &&
6057 isHorizontalBinOp(BV, ISD::ADD, DAG, Half, NumElts, InVec2, InVec3) &&
6058 ((InVec0.getOpcode() == ISD::UNDEF ||
6059 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6060 ((InVec1.getOpcode() == ISD::UNDEF ||
6061 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6062 X86Opcode = X86ISD::HADD;
6063 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, Half, InVec0, InVec1) &&
6064 isHorizontalBinOp(BV, ISD::SUB, DAG, Half, NumElts, InVec2, InVec3) &&
6065 ((InVec0.getOpcode() == ISD::UNDEF ||
6066 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6067 ((InVec1.getOpcode() == ISD::UNDEF ||
6068 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6069 X86Opcode = X86ISD::HSUB;
6074 // Fold this build_vector into a single horizontal add/sub.
6075 // Do this only if the target has AVX2.
6076 if (Subtarget->hasAVX2())
6077 return DAG.getNode(X86Opcode, DL, VT, InVec0, InVec1);
6079 // Do not try to expand this build_vector into a pair of horizontal
6080 // add/sub if we can emit a pair of scalar add/sub.
6081 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
6084 // Convert this build_vector into a pair of horizontal binop followed by
6086 bool isUndefLO = NumUndefsLO == Half;
6087 bool isUndefHI = NumUndefsHI == Half;
6088 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, false,
6089 isUndefLO, isUndefHI);
6093 if ((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v8i32 ||
6094 VT == MVT::v16i16) && Subtarget->hasAVX()) {
6096 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
6097 X86Opcode = X86ISD::HADD;
6098 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
6099 X86Opcode = X86ISD::HSUB;
6100 else if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
6101 X86Opcode = X86ISD::FHADD;
6102 else if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
6103 X86Opcode = X86ISD::FHSUB;
6107 // Don't try to expand this build_vector into a pair of horizontal add/sub
6108 // if we can simply emit a pair of scalar add/sub.
6109 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
6112 // Convert this build_vector into two horizontal add/sub followed by
6114 bool isUndefLO = NumUndefsLO == Half;
6115 bool isUndefHI = NumUndefsHI == Half;
6116 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, true,
6117 isUndefLO, isUndefHI);
6124 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
6127 MVT VT = Op.getSimpleValueType();
6128 MVT ExtVT = VT.getVectorElementType();
6129 unsigned NumElems = Op.getNumOperands();
6131 // Generate vectors for predicate vectors.
6132 if (VT.getScalarType() == MVT::i1 && Subtarget->hasAVX512())
6133 return LowerBUILD_VECTORvXi1(Op, DAG);
6135 // Vectors containing all zeros can be matched by pxor and xorps later
6136 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
6137 // Canonicalize this to <4 x i32> to 1) ensure the zero vectors are CSE'd
6138 // and 2) ensure that i64 scalars are eliminated on x86-32 hosts.
6139 if (VT == MVT::v4i32 || VT == MVT::v8i32 || VT == MVT::v16i32)
6142 return getZeroVector(VT, Subtarget, DAG, dl);
6145 // Vectors containing all ones can be matched by pcmpeqd on 128-bit width
6146 // vectors or broken into v4i32 operations on 256-bit vectors. AVX2 can use
6147 // vpcmpeqd on 256-bit vectors.
6148 if (Subtarget->hasSSE2() && ISD::isBuildVectorAllOnes(Op.getNode())) {
6149 if (VT == MVT::v4i32 || (VT == MVT::v8i32 && Subtarget->hasInt256()))
6152 if (!VT.is512BitVector())
6153 return getOnesVector(VT, Subtarget, DAG, dl);
6156 BuildVectorSDNode *BV = cast<BuildVectorSDNode>(Op.getNode());
6157 if (SDValue AddSub = LowerToAddSub(BV, Subtarget, DAG))
6159 if (SDValue HorizontalOp = LowerToHorizontalOp(BV, Subtarget, DAG))
6160 return HorizontalOp;
6161 if (SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG))
6164 unsigned EVTBits = ExtVT.getSizeInBits();
6166 unsigned NumZero = 0;
6167 unsigned NumNonZero = 0;
6168 unsigned NonZeros = 0;
6169 bool IsAllConstants = true;
6170 SmallSet<SDValue, 8> Values;
6171 for (unsigned i = 0; i < NumElems; ++i) {
6172 SDValue Elt = Op.getOperand(i);
6173 if (Elt.getOpcode() == ISD::UNDEF)
6176 if (Elt.getOpcode() != ISD::Constant &&
6177 Elt.getOpcode() != ISD::ConstantFP)
6178 IsAllConstants = false;
6179 if (X86::isZeroNode(Elt))
6182 NonZeros |= (1 << i);
6187 // All undef vector. Return an UNDEF. All zero vectors were handled above.
6188 if (NumNonZero == 0)
6189 return DAG.getUNDEF(VT);
6191 // Special case for single non-zero, non-undef, element.
6192 if (NumNonZero == 1) {
6193 unsigned Idx = countTrailingZeros(NonZeros);
6194 SDValue Item = Op.getOperand(Idx);
6196 // If this is an insertion of an i64 value on x86-32, and if the top bits of
6197 // the value are obviously zero, truncate the value to i32 and do the
6198 // insertion that way. Only do this if the value is non-constant or if the
6199 // value is a constant being inserted into element 0. It is cheaper to do
6200 // a constant pool load than it is to do a movd + shuffle.
6201 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
6202 (!IsAllConstants || Idx == 0)) {
6203 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
6205 assert(VT == MVT::v2i64 && "Expected an SSE value type!");
6206 EVT VecVT = MVT::v4i32;
6208 // Truncate the value (which may itself be a constant) to i32, and
6209 // convert it to a vector with movd (S2V+shuffle to zero extend).
6210 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
6211 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
6212 return DAG.getBitcast(VT, getShuffleVectorZeroOrUndef(
6213 Item, Idx * 2, true, Subtarget, DAG));
6217 // If we have a constant or non-constant insertion into the low element of
6218 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
6219 // the rest of the elements. This will be matched as movd/movq/movss/movsd
6220 // depending on what the source datatype is.
6223 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6225 if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
6226 (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
6227 if (VT.is512BitVector()) {
6228 SDValue ZeroVec = getZeroVector(VT, Subtarget, DAG, dl);
6229 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, ZeroVec,
6230 Item, DAG.getIntPtrConstant(0, dl));
6232 assert((VT.is128BitVector() || VT.is256BitVector()) &&
6233 "Expected an SSE value type!");
6234 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6235 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
6236 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6239 // We can't directly insert an i8 or i16 into a vector, so zero extend
6241 if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
6242 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
6243 if (VT.is256BitVector()) {
6244 if (Subtarget->hasAVX()) {
6245 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v8i32, Item);
6246 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6248 // Without AVX, we need to extend to a 128-bit vector and then
6249 // insert into the 256-bit vector.
6250 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
6251 SDValue ZeroVec = getZeroVector(MVT::v8i32, Subtarget, DAG, dl);
6252 Item = Insert128BitVector(ZeroVec, Item, 0, DAG, dl);
6255 assert(VT.is128BitVector() && "Expected an SSE value type!");
6256 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
6257 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6259 return DAG.getBitcast(VT, Item);
6263 // Is it a vector logical left shift?
6264 if (NumElems == 2 && Idx == 1 &&
6265 X86::isZeroNode(Op.getOperand(0)) &&
6266 !X86::isZeroNode(Op.getOperand(1))) {
6267 unsigned NumBits = VT.getSizeInBits();
6268 return getVShift(true, VT,
6269 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
6270 VT, Op.getOperand(1)),
6271 NumBits/2, DAG, *this, dl);
6274 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
6277 // Otherwise, if this is a vector with i32 or f32 elements, and the element
6278 // is a non-constant being inserted into an element other than the low one,
6279 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
6280 // movd/movss) to move this into the low element, then shuffle it into
6282 if (EVTBits == 32) {
6283 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6284 return getShuffleVectorZeroOrUndef(Item, Idx, NumZero > 0, Subtarget, DAG);
6288 // Splat is obviously ok. Let legalizer expand it to a shuffle.
6289 if (Values.size() == 1) {
6290 if (EVTBits == 32) {
6291 // Instead of a shuffle like this:
6292 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
6293 // Check if it's possible to issue this instead.
6294 // shuffle (vload ptr)), undef, <1, 1, 1, 1>
6295 unsigned Idx = countTrailingZeros(NonZeros);
6296 SDValue Item = Op.getOperand(Idx);
6297 if (Op.getNode()->isOnlyUserOf(Item.getNode()))
6298 return LowerAsSplatVectorLoad(Item, VT, dl, DAG);
6303 // A vector full of immediates; various special cases are already
6304 // handled, so this is best done with a single constant-pool load.
6308 // For AVX-length vectors, see if we can use a vector load to get all of the
6309 // elements, otherwise build the individual 128-bit pieces and use
6310 // shuffles to put them in place.
6311 if (VT.is256BitVector() || VT.is512BitVector()) {
6312 SmallVector<SDValue, 64> V(Op->op_begin(), Op->op_begin() + NumElems);
6314 // Check for a build vector of consecutive loads.
6315 if (SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG, false))
6318 EVT HVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems/2);
6320 // Build both the lower and upper subvector.
6321 SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
6322 makeArrayRef(&V[0], NumElems/2));
6323 SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
6324 makeArrayRef(&V[NumElems / 2], NumElems/2));
6326 // Recreate the wider vector with the lower and upper part.
6327 if (VT.is256BitVector())
6328 return Concat128BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
6329 return Concat256BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
6332 // Let legalizer expand 2-wide build_vectors.
6333 if (EVTBits == 64) {
6334 if (NumNonZero == 1) {
6335 // One half is zero or undef.
6336 unsigned Idx = countTrailingZeros(NonZeros);
6337 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
6338 Op.getOperand(Idx));
6339 return getShuffleVectorZeroOrUndef(V2, Idx, true, Subtarget, DAG);
6344 // If element VT is < 32 bits, convert it to inserts into a zero vector.
6345 if (EVTBits == 8 && NumElems == 16)
6346 if (SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
6350 if (EVTBits == 16 && NumElems == 8)
6351 if (SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
6355 // If element VT is == 32 bits and has 4 elems, try to generate an INSERTPS
6356 if (EVTBits == 32 && NumElems == 4)
6357 if (SDValue V = LowerBuildVectorv4x32(Op, DAG, Subtarget, *this))
6360 // If element VT is == 32 bits, turn it into a number of shuffles.
6361 SmallVector<SDValue, 8> V(NumElems);
6362 if (NumElems == 4 && NumZero > 0) {
6363 for (unsigned i = 0; i < 4; ++i) {
6364 bool isZero = !(NonZeros & (1 << i));
6366 V[i] = getZeroVector(VT, Subtarget, DAG, dl);
6368 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
6371 for (unsigned i = 0; i < 2; ++i) {
6372 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
6375 V[i] = V[i*2]; // Must be a zero vector.
6378 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
6381 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
6384 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
6389 bool Reverse1 = (NonZeros & 0x3) == 2;
6390 bool Reverse2 = ((NonZeros & (0x3 << 2)) >> 2) == 2;
6394 static_cast<int>(Reverse2 ? NumElems+1 : NumElems),
6395 static_cast<int>(Reverse2 ? NumElems : NumElems+1)
6397 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
6400 if (Values.size() > 1 && VT.is128BitVector()) {
6401 // Check for a build vector of consecutive loads.
6402 for (unsigned i = 0; i < NumElems; ++i)
6403 V[i] = Op.getOperand(i);
6405 // Check for elements which are consecutive loads.
6406 if (SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG, false))
6409 // Check for a build vector from mostly shuffle plus few inserting.
6410 if (SDValue Sh = buildFromShuffleMostly(Op, DAG))
6413 // For SSE 4.1, use insertps to put the high elements into the low element.
6414 if (Subtarget->hasSSE41()) {
6416 if (Op.getOperand(0).getOpcode() != ISD::UNDEF)
6417 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0));
6419 Result = DAG.getUNDEF(VT);
6421 for (unsigned i = 1; i < NumElems; ++i) {
6422 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue;
6423 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result,
6424 Op.getOperand(i), DAG.getIntPtrConstant(i, dl));
6429 // Otherwise, expand into a number of unpckl*, start by extending each of
6430 // our (non-undef) elements to the full vector width with the element in the
6431 // bottom slot of the vector (which generates no code for SSE).
6432 for (unsigned i = 0; i < NumElems; ++i) {
6433 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
6434 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
6436 V[i] = DAG.getUNDEF(VT);
6439 // Next, we iteratively mix elements, e.g. for v4f32:
6440 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
6441 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
6442 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
6443 unsigned EltStride = NumElems >> 1;
6444 while (EltStride != 0) {
6445 for (unsigned i = 0; i < EltStride; ++i) {
6446 // If V[i+EltStride] is undef and this is the first round of mixing,
6447 // then it is safe to just drop this shuffle: V[i] is already in the
6448 // right place, the one element (since it's the first round) being
6449 // inserted as undef can be dropped. This isn't safe for successive
6450 // rounds because they will permute elements within both vectors.
6451 if (V[i+EltStride].getOpcode() == ISD::UNDEF &&
6452 EltStride == NumElems/2)
6455 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]);
6464 // 256-bit AVX can use the vinsertf128 instruction
6465 // to create 256-bit vectors from two other 128-bit ones.
6466 static SDValue LowerAVXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
6468 MVT ResVT = Op.getSimpleValueType();
6470 assert((ResVT.is256BitVector() ||
6471 ResVT.is512BitVector()) && "Value type must be 256-/512-bit wide");
6473 SDValue V1 = Op.getOperand(0);
6474 SDValue V2 = Op.getOperand(1);
6475 unsigned NumElems = ResVT.getVectorNumElements();
6476 if (ResVT.is256BitVector())
6477 return Concat128BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
6479 if (Op.getNumOperands() == 4) {
6480 MVT HalfVT = MVT::getVectorVT(ResVT.getScalarType(),
6481 ResVT.getVectorNumElements()/2);
6482 SDValue V3 = Op.getOperand(2);
6483 SDValue V4 = Op.getOperand(3);
6484 return Concat256BitVectors(Concat128BitVectors(V1, V2, HalfVT, NumElems/2, DAG, dl),
6485 Concat128BitVectors(V3, V4, HalfVT, NumElems/2, DAG, dl), ResVT, NumElems, DAG, dl);
6487 return Concat256BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
6490 static SDValue LowerCONCAT_VECTORSvXi1(SDValue Op,
6491 const X86Subtarget *Subtarget,
6492 SelectionDAG & DAG) {
6494 MVT ResVT = Op.getSimpleValueType();
6495 unsigned NumOfOperands = Op.getNumOperands();
6497 assert(isPowerOf2_32(NumOfOperands) &&
6498 "Unexpected number of operands in CONCAT_VECTORS");
6500 if (NumOfOperands > 2) {
6501 MVT HalfVT = MVT::getVectorVT(ResVT.getScalarType(),
6502 ResVT.getVectorNumElements()/2);
6503 SmallVector<SDValue, 2> Ops;
6504 for (unsigned i = 0; i < NumOfOperands/2; i++)
6505 Ops.push_back(Op.getOperand(i));
6506 SDValue Lo = DAG.getNode(ISD::CONCAT_VECTORS, dl, HalfVT, Ops);
6508 for (unsigned i = NumOfOperands/2; i < NumOfOperands; i++)
6509 Ops.push_back(Op.getOperand(i));
6510 SDValue Hi = DAG.getNode(ISD::CONCAT_VECTORS, dl, HalfVT, Ops);
6511 return DAG.getNode(ISD::CONCAT_VECTORS, dl, ResVT, Lo, Hi);
6514 SDValue V1 = Op.getOperand(0);
6515 SDValue V2 = Op.getOperand(1);
6516 bool IsZeroV1 = ISD::isBuildVectorAllZeros(V1.getNode());
6517 bool IsZeroV2 = ISD::isBuildVectorAllZeros(V2.getNode());
6519 if (IsZeroV1 && IsZeroV2)
6520 return getZeroVector(ResVT, Subtarget, DAG, dl);
6522 SDValue ZeroIdx = DAG.getIntPtrConstant(0, dl);
6523 SDValue Undef = DAG.getUNDEF(ResVT);
6524 unsigned NumElems = ResVT.getVectorNumElements();
6525 SDValue ShiftBits = DAG.getConstant(NumElems/2, dl, MVT::i8);
6527 V2 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, Undef, V2, ZeroIdx);
6528 V2 = DAG.getNode(X86ISD::VSHLI, dl, ResVT, V2, ShiftBits);
6532 V1 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, Undef, V1, ZeroIdx);
6533 // Zero the upper bits of V1
6534 V1 = DAG.getNode(X86ISD::VSHLI, dl, ResVT, V1, ShiftBits);
6535 V1 = DAG.getNode(X86ISD::VSRLI, dl, ResVT, V1, ShiftBits);
6538 return DAG.getNode(ISD::OR, dl, ResVT, V1, V2);
6541 static SDValue LowerCONCAT_VECTORS(SDValue Op,
6542 const X86Subtarget *Subtarget,
6543 SelectionDAG &DAG) {
6544 MVT VT = Op.getSimpleValueType();
6545 if (VT.getVectorElementType() == MVT::i1)
6546 return LowerCONCAT_VECTORSvXi1(Op, Subtarget, DAG);
6548 assert((VT.is256BitVector() && Op.getNumOperands() == 2) ||
6549 (VT.is512BitVector() && (Op.getNumOperands() == 2 ||
6550 Op.getNumOperands() == 4)));
6552 // AVX can use the vinsertf128 instruction to create 256-bit vectors
6553 // from two other 128-bit ones.
6555 // 512-bit vector may contain 2 256-bit vectors or 4 128-bit vectors
6556 return LowerAVXCONCAT_VECTORS(Op, DAG);
6559 //===----------------------------------------------------------------------===//
6560 // Vector shuffle lowering
6562 // This is an experimental code path for lowering vector shuffles on x86. It is
6563 // designed to handle arbitrary vector shuffles and blends, gracefully
6564 // degrading performance as necessary. It works hard to recognize idiomatic
6565 // shuffles and lower them to optimal instruction patterns without leaving
6566 // a framework that allows reasonably efficient handling of all vector shuffle
6568 //===----------------------------------------------------------------------===//
6570 /// \brief Tiny helper function to identify a no-op mask.
6572 /// This is a somewhat boring predicate function. It checks whether the mask
6573 /// array input, which is assumed to be a single-input shuffle mask of the kind
6574 /// used by the X86 shuffle instructions (not a fully general
6575 /// ShuffleVectorSDNode mask) requires any shuffles to occur. Both undef and an
6576 /// in-place shuffle are 'no-op's.
6577 static bool isNoopShuffleMask(ArrayRef<int> Mask) {
6578 for (int i = 0, Size = Mask.size(); i < Size; ++i)
6579 if (Mask[i] != -1 && Mask[i] != i)
6584 /// \brief Helper function to classify a mask as a single-input mask.
6586 /// This isn't a generic single-input test because in the vector shuffle
6587 /// lowering we canonicalize single inputs to be the first input operand. This
6588 /// means we can more quickly test for a single input by only checking whether
6589 /// an input from the second operand exists. We also assume that the size of
6590 /// mask corresponds to the size of the input vectors which isn't true in the
6591 /// fully general case.
6592 static bool isSingleInputShuffleMask(ArrayRef<int> Mask) {
6594 if (M >= (int)Mask.size())
6599 /// \brief Test whether there are elements crossing 128-bit lanes in this
6602 /// X86 divides up its shuffles into in-lane and cross-lane shuffle operations
6603 /// and we routinely test for these.
6604 static bool is128BitLaneCrossingShuffleMask(MVT VT, ArrayRef<int> Mask) {
6605 int LaneSize = 128 / VT.getScalarSizeInBits();
6606 int Size = Mask.size();
6607 for (int i = 0; i < Size; ++i)
6608 if (Mask[i] >= 0 && (Mask[i] % Size) / LaneSize != i / LaneSize)
6613 /// \brief Test whether a shuffle mask is equivalent within each 128-bit lane.
6615 /// This checks a shuffle mask to see if it is performing the same
6616 /// 128-bit lane-relative shuffle in each 128-bit lane. This trivially implies
6617 /// that it is also not lane-crossing. It may however involve a blend from the
6618 /// same lane of a second vector.
6620 /// The specific repeated shuffle mask is populated in \p RepeatedMask, as it is
6621 /// non-trivial to compute in the face of undef lanes. The representation is
6622 /// *not* suitable for use with existing 128-bit shuffles as it will contain
6623 /// entries from both V1 and V2 inputs to the wider mask.
6625 is128BitLaneRepeatedShuffleMask(MVT VT, ArrayRef<int> Mask,
6626 SmallVectorImpl<int> &RepeatedMask) {
6627 int LaneSize = 128 / VT.getScalarSizeInBits();
6628 RepeatedMask.resize(LaneSize, -1);
6629 int Size = Mask.size();
6630 for (int i = 0; i < Size; ++i) {
6633 if ((Mask[i] % Size) / LaneSize != i / LaneSize)
6634 // This entry crosses lanes, so there is no way to model this shuffle.
6637 // Ok, handle the in-lane shuffles by detecting if and when they repeat.
6638 if (RepeatedMask[i % LaneSize] == -1)
6639 // This is the first non-undef entry in this slot of a 128-bit lane.
6640 RepeatedMask[i % LaneSize] =
6641 Mask[i] < Size ? Mask[i] % LaneSize : Mask[i] % LaneSize + Size;
6642 else if (RepeatedMask[i % LaneSize] + (i / LaneSize) * LaneSize != Mask[i])
6643 // Found a mismatch with the repeated mask.
6649 /// \brief Checks whether a shuffle mask is equivalent to an explicit list of
6652 /// This is a fast way to test a shuffle mask against a fixed pattern:
6654 /// if (isShuffleEquivalent(Mask, 3, 2, {1, 0})) { ... }
6656 /// It returns true if the mask is exactly as wide as the argument list, and
6657 /// each element of the mask is either -1 (signifying undef) or the value given
6658 /// in the argument.
6659 static bool isShuffleEquivalent(SDValue V1, SDValue V2, ArrayRef<int> Mask,
6660 ArrayRef<int> ExpectedMask) {
6661 if (Mask.size() != ExpectedMask.size())
6664 int Size = Mask.size();
6666 // If the values are build vectors, we can look through them to find
6667 // equivalent inputs that make the shuffles equivalent.
6668 auto *BV1 = dyn_cast<BuildVectorSDNode>(V1);
6669 auto *BV2 = dyn_cast<BuildVectorSDNode>(V2);
6671 for (int i = 0; i < Size; ++i)
6672 if (Mask[i] != -1 && Mask[i] != ExpectedMask[i]) {
6673 auto *MaskBV = Mask[i] < Size ? BV1 : BV2;
6674 auto *ExpectedBV = ExpectedMask[i] < Size ? BV1 : BV2;
6675 if (!MaskBV || !ExpectedBV ||
6676 MaskBV->getOperand(Mask[i] % Size) !=
6677 ExpectedBV->getOperand(ExpectedMask[i] % Size))
6684 /// \brief Get a 4-lane 8-bit shuffle immediate for a mask.
6686 /// This helper function produces an 8-bit shuffle immediate corresponding to
6687 /// the ubiquitous shuffle encoding scheme used in x86 instructions for
6688 /// shuffling 4 lanes. It can be used with most of the PSHUF instructions for
6691 /// NB: We rely heavily on "undef" masks preserving the input lane.
6692 static SDValue getV4X86ShuffleImm8ForMask(ArrayRef<int> Mask, SDLoc DL,
6693 SelectionDAG &DAG) {
6694 assert(Mask.size() == 4 && "Only 4-lane shuffle masks");
6695 assert(Mask[0] >= -1 && Mask[0] < 4 && "Out of bound mask element!");
6696 assert(Mask[1] >= -1 && Mask[1] < 4 && "Out of bound mask element!");
6697 assert(Mask[2] >= -1 && Mask[2] < 4 && "Out of bound mask element!");
6698 assert(Mask[3] >= -1 && Mask[3] < 4 && "Out of bound mask element!");
6701 Imm |= (Mask[0] == -1 ? 0 : Mask[0]) << 0;
6702 Imm |= (Mask[1] == -1 ? 1 : Mask[1]) << 2;
6703 Imm |= (Mask[2] == -1 ? 2 : Mask[2]) << 4;
6704 Imm |= (Mask[3] == -1 ? 3 : Mask[3]) << 6;
6705 return DAG.getConstant(Imm, DL, MVT::i8);
6708 /// \brief Compute whether each element of a shuffle is zeroable.
6710 /// A "zeroable" vector shuffle element is one which can be lowered to zero.
6711 /// Either it is an undef element in the shuffle mask, the element of the input
6712 /// referenced is undef, or the element of the input referenced is known to be
6713 /// zero. Many x86 shuffles can zero lanes cheaply and we often want to handle
6714 /// as many lanes with this technique as possible to simplify the remaining
6716 static SmallBitVector computeZeroableShuffleElements(ArrayRef<int> Mask,
6717 SDValue V1, SDValue V2) {
6718 SmallBitVector Zeroable(Mask.size(), false);
6720 while (V1.getOpcode() == ISD::BITCAST)
6721 V1 = V1->getOperand(0);
6722 while (V2.getOpcode() == ISD::BITCAST)
6723 V2 = V2->getOperand(0);
6725 bool V1IsZero = ISD::isBuildVectorAllZeros(V1.getNode());
6726 bool V2IsZero = ISD::isBuildVectorAllZeros(V2.getNode());
6728 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6730 // Handle the easy cases.
6731 if (M < 0 || (M >= 0 && M < Size && V1IsZero) || (M >= Size && V2IsZero)) {
6736 // If this is an index into a build_vector node (which has the same number
6737 // of elements), dig out the input value and use it.
6738 SDValue V = M < Size ? V1 : V2;
6739 if (V.getOpcode() != ISD::BUILD_VECTOR || Size != (int)V.getNumOperands())
6742 SDValue Input = V.getOperand(M % Size);
6743 // The UNDEF opcode check really should be dead code here, but not quite
6744 // worth asserting on (it isn't invalid, just unexpected).
6745 if (Input.getOpcode() == ISD::UNDEF || X86::isZeroNode(Input))
6752 // X86 has dedicated unpack instructions that can handle specific blend
6753 // operations: UNPCKH and UNPCKL.
6754 static SDValue lowerVectorShuffleWithUNPCK(SDLoc DL, MVT VT, ArrayRef<int> Mask,
6755 SDValue V1, SDValue V2,
6756 SelectionDAG &DAG) {
6757 int NumElts = VT.getVectorNumElements();
6758 int NumEltsInLane = 128 / VT.getScalarSizeInBits();
6759 SmallVector<int, 8> Unpckl;
6760 SmallVector<int, 8> Unpckh;
6762 for (int i = 0; i < NumElts; ++i) {
6763 unsigned LaneStart = (i / NumEltsInLane) * NumEltsInLane;
6764 int LoPos = (i % NumEltsInLane) / 2 + LaneStart + NumElts * (i % 2);
6765 int HiPos = LoPos + NumEltsInLane / 2;
6766 Unpckl.push_back(LoPos);
6767 Unpckh.push_back(HiPos);
6770 if (isShuffleEquivalent(V1, V2, Mask, Unpckl))
6771 return DAG.getNode(X86ISD::UNPCKL, DL, VT, V1, V2);
6772 if (isShuffleEquivalent(V1, V2, Mask, Unpckh))
6773 return DAG.getNode(X86ISD::UNPCKH, DL, VT, V1, V2);
6775 // Commute and try again.
6776 ShuffleVectorSDNode::commuteMask(Unpckl);
6777 if (isShuffleEquivalent(V1, V2, Mask, Unpckl))
6778 return DAG.getNode(X86ISD::UNPCKL, DL, VT, V2, V1);
6780 ShuffleVectorSDNode::commuteMask(Unpckh);
6781 if (isShuffleEquivalent(V1, V2, Mask, Unpckh))
6782 return DAG.getNode(X86ISD::UNPCKH, DL, VT, V2, V1);
6787 /// \brief Try to emit a bitmask instruction for a shuffle.
6789 /// This handles cases where we can model a blend exactly as a bitmask due to
6790 /// one of the inputs being zeroable.
6791 static SDValue lowerVectorShuffleAsBitMask(SDLoc DL, MVT VT, SDValue V1,
6792 SDValue V2, ArrayRef<int> Mask,
6793 SelectionDAG &DAG) {
6794 MVT EltVT = VT.getScalarType();
6795 int NumEltBits = EltVT.getSizeInBits();
6796 MVT IntEltVT = MVT::getIntegerVT(NumEltBits);
6797 SDValue Zero = DAG.getConstant(0, DL, IntEltVT);
6798 SDValue AllOnes = DAG.getConstant(APInt::getAllOnesValue(NumEltBits), DL,
6800 if (EltVT.isFloatingPoint()) {
6801 Zero = DAG.getBitcast(EltVT, Zero);
6802 AllOnes = DAG.getBitcast(EltVT, AllOnes);
6804 SmallVector<SDValue, 16> VMaskOps(Mask.size(), Zero);
6805 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
6807 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6810 if (Mask[i] % Size != i)
6811 return SDValue(); // Not a blend.
6813 V = Mask[i] < Size ? V1 : V2;
6814 else if (V != (Mask[i] < Size ? V1 : V2))
6815 return SDValue(); // Can only let one input through the mask.
6817 VMaskOps[i] = AllOnes;
6820 return SDValue(); // No non-zeroable elements!
6822 SDValue VMask = DAG.getNode(ISD::BUILD_VECTOR, DL, VT, VMaskOps);
6823 V = DAG.getNode(VT.isFloatingPoint()
6824 ? (unsigned) X86ISD::FAND : (unsigned) ISD::AND,
6829 /// \brief Try to emit a blend instruction for a shuffle using bit math.
6831 /// This is used as a fallback approach when first class blend instructions are
6832 /// unavailable. Currently it is only suitable for integer vectors, but could
6833 /// be generalized for floating point vectors if desirable.
6834 static SDValue lowerVectorShuffleAsBitBlend(SDLoc DL, MVT VT, SDValue V1,
6835 SDValue V2, ArrayRef<int> Mask,
6836 SelectionDAG &DAG) {
6837 assert(VT.isInteger() && "Only supports integer vector types!");
6838 MVT EltVT = VT.getScalarType();
6839 int NumEltBits = EltVT.getSizeInBits();
6840 SDValue Zero = DAG.getConstant(0, DL, EltVT);
6841 SDValue AllOnes = DAG.getConstant(APInt::getAllOnesValue(NumEltBits), DL,
6843 SmallVector<SDValue, 16> MaskOps;
6844 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6845 if (Mask[i] != -1 && Mask[i] != i && Mask[i] != i + Size)
6846 return SDValue(); // Shuffled input!
6847 MaskOps.push_back(Mask[i] < Size ? AllOnes : Zero);
6850 SDValue V1Mask = DAG.getNode(ISD::BUILD_VECTOR, DL, VT, MaskOps);
6851 V1 = DAG.getNode(ISD::AND, DL, VT, V1, V1Mask);
6852 // We have to cast V2 around.
6853 MVT MaskVT = MVT::getVectorVT(MVT::i64, VT.getSizeInBits() / 64);
6854 V2 = DAG.getBitcast(VT, DAG.getNode(X86ISD::ANDNP, DL, MaskVT,
6855 DAG.getBitcast(MaskVT, V1Mask),
6856 DAG.getBitcast(MaskVT, V2)));
6857 return DAG.getNode(ISD::OR, DL, VT, V1, V2);
6860 /// \brief Try to emit a blend instruction for a shuffle.
6862 /// This doesn't do any checks for the availability of instructions for blending
6863 /// these values. It relies on the availability of the X86ISD::BLENDI pattern to
6864 /// be matched in the backend with the type given. What it does check for is
6865 /// that the shuffle mask is a blend, or convertible into a blend with zero.
6866 static SDValue lowerVectorShuffleAsBlend(SDLoc DL, MVT VT, SDValue V1,
6867 SDValue V2, ArrayRef<int> Original,
6868 const X86Subtarget *Subtarget,
6869 SelectionDAG &DAG) {
6870 bool V1IsZero = ISD::isBuildVectorAllZeros(V1.getNode());
6871 bool V2IsZero = ISD::isBuildVectorAllZeros(V2.getNode());
6872 SmallVector<int, 8> Mask(Original.begin(), Original.end());
6873 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
6874 bool ForceV1Zero = false, ForceV2Zero = false;
6876 // Attempt to generate the binary blend mask. If an input is zero then
6877 // we can use any lane.
6878 // TODO: generalize the zero matching to any scalar like isShuffleEquivalent.
6879 unsigned BlendMask = 0;
6880 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6886 if (M == i + Size) {
6887 BlendMask |= 1u << i;
6898 BlendMask |= 1u << i;
6903 return SDValue(); // Shuffled input!
6906 // Create a REAL zero vector - ISD::isBuildVectorAllZeros allows UNDEFs.
6908 V1 = getZeroVector(VT, Subtarget, DAG, DL);
6910 V2 = getZeroVector(VT, Subtarget, DAG, DL);
6912 auto ScaleBlendMask = [](unsigned BlendMask, int Size, int Scale) {
6913 unsigned ScaledMask = 0;
6914 for (int i = 0; i != Size; ++i)
6915 if (BlendMask & (1u << i))
6916 for (int j = 0; j != Scale; ++j)
6917 ScaledMask |= 1u << (i * Scale + j);
6921 switch (VT.SimpleTy) {
6926 return DAG.getNode(X86ISD::BLENDI, DL, VT, V1, V2,
6927 DAG.getConstant(BlendMask, DL, MVT::i8));
6931 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
6935 // If we have AVX2 it is faster to use VPBLENDD when the shuffle fits into
6936 // that instruction.
6937 if (Subtarget->hasAVX2()) {
6938 // Scale the blend by the number of 32-bit dwords per element.
6939 int Scale = VT.getScalarSizeInBits() / 32;
6940 BlendMask = ScaleBlendMask(BlendMask, Mask.size(), Scale);
6941 MVT BlendVT = VT.getSizeInBits() > 128 ? MVT::v8i32 : MVT::v4i32;
6942 V1 = DAG.getBitcast(BlendVT, V1);
6943 V2 = DAG.getBitcast(BlendVT, V2);
6944 return DAG.getBitcast(
6945 VT, DAG.getNode(X86ISD::BLENDI, DL, BlendVT, V1, V2,
6946 DAG.getConstant(BlendMask, DL, MVT::i8)));
6950 // For integer shuffles we need to expand the mask and cast the inputs to
6951 // v8i16s prior to blending.
6952 int Scale = 8 / VT.getVectorNumElements();
6953 BlendMask = ScaleBlendMask(BlendMask, Mask.size(), Scale);
6954 V1 = DAG.getBitcast(MVT::v8i16, V1);
6955 V2 = DAG.getBitcast(MVT::v8i16, V2);
6956 return DAG.getBitcast(VT,
6957 DAG.getNode(X86ISD::BLENDI, DL, MVT::v8i16, V1, V2,
6958 DAG.getConstant(BlendMask, DL, MVT::i8)));
6962 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
6963 SmallVector<int, 8> RepeatedMask;
6964 if (is128BitLaneRepeatedShuffleMask(MVT::v16i16, Mask, RepeatedMask)) {
6965 // We can lower these with PBLENDW which is mirrored across 128-bit lanes.
6966 assert(RepeatedMask.size() == 8 && "Repeated mask size doesn't match!");
6968 for (int i = 0; i < 8; ++i)
6969 if (RepeatedMask[i] >= 16)
6970 BlendMask |= 1u << i;
6971 return DAG.getNode(X86ISD::BLENDI, DL, MVT::v16i16, V1, V2,
6972 DAG.getConstant(BlendMask, DL, MVT::i8));
6978 assert((VT.getSizeInBits() == 128 || Subtarget->hasAVX2()) &&
6979 "256-bit byte-blends require AVX2 support!");
6981 // Attempt to lower to a bitmask if we can. VPAND is faster than VPBLENDVB.
6982 if (SDValue Masked = lowerVectorShuffleAsBitMask(DL, VT, V1, V2, Mask, DAG))
6985 // Scale the blend by the number of bytes per element.
6986 int Scale = VT.getScalarSizeInBits() / 8;
6988 // This form of blend is always done on bytes. Compute the byte vector
6990 MVT BlendVT = MVT::getVectorVT(MVT::i8, VT.getSizeInBits() / 8);
6992 // Compute the VSELECT mask. Note that VSELECT is really confusing in the
6993 // mix of LLVM's code generator and the x86 backend. We tell the code
6994 // generator that boolean values in the elements of an x86 vector register
6995 // are -1 for true and 0 for false. We then use the LLVM semantics of 'true'
6996 // mapping a select to operand #1, and 'false' mapping to operand #2. The
6997 // reality in x86 is that vector masks (pre-AVX-512) use only the high bit
6998 // of the element (the remaining are ignored) and 0 in that high bit would
6999 // mean operand #1 while 1 in the high bit would mean operand #2. So while
7000 // the LLVM model for boolean values in vector elements gets the relevant
7001 // bit set, it is set backwards and over constrained relative to x86's
7003 SmallVector<SDValue, 32> VSELECTMask;
7004 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7005 for (int j = 0; j < Scale; ++j)
7006 VSELECTMask.push_back(
7007 Mask[i] < 0 ? DAG.getUNDEF(MVT::i8)
7008 : DAG.getConstant(Mask[i] < Size ? -1 : 0, DL,
7011 V1 = DAG.getBitcast(BlendVT, V1);
7012 V2 = DAG.getBitcast(BlendVT, V2);
7013 return DAG.getBitcast(VT, DAG.getNode(ISD::VSELECT, DL, BlendVT,
7014 DAG.getNode(ISD::BUILD_VECTOR, DL,
7015 BlendVT, VSELECTMask),
7020 llvm_unreachable("Not a supported integer vector type!");
7024 /// \brief Try to lower as a blend of elements from two inputs followed by
7025 /// a single-input permutation.
7027 /// This matches the pattern where we can blend elements from two inputs and
7028 /// then reduce the shuffle to a single-input permutation.
7029 static SDValue lowerVectorShuffleAsBlendAndPermute(SDLoc DL, MVT VT, SDValue V1,
7032 SelectionDAG &DAG) {
7033 // We build up the blend mask while checking whether a blend is a viable way
7034 // to reduce the shuffle.
7035 SmallVector<int, 32> BlendMask(Mask.size(), -1);
7036 SmallVector<int, 32> PermuteMask(Mask.size(), -1);
7038 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
7042 assert(Mask[i] < Size * 2 && "Shuffle input is out of bounds.");
7044 if (BlendMask[Mask[i] % Size] == -1)
7045 BlendMask[Mask[i] % Size] = Mask[i];
7046 else if (BlendMask[Mask[i] % Size] != Mask[i])
7047 return SDValue(); // Can't blend in the needed input!
7049 PermuteMask[i] = Mask[i] % Size;
7052 SDValue V = DAG.getVectorShuffle(VT, DL, V1, V2, BlendMask);
7053 return DAG.getVectorShuffle(VT, DL, V, DAG.getUNDEF(VT), PermuteMask);
7056 /// \brief Generic routine to decompose a shuffle and blend into indepndent
7057 /// blends and permutes.
7059 /// This matches the extremely common pattern for handling combined
7060 /// shuffle+blend operations on newer X86 ISAs where we have very fast blend
7061 /// operations. It will try to pick the best arrangement of shuffles and
7063 static SDValue lowerVectorShuffleAsDecomposedShuffleBlend(SDLoc DL, MVT VT,
7067 SelectionDAG &DAG) {
7068 // Shuffle the input elements into the desired positions in V1 and V2 and
7069 // blend them together.
7070 SmallVector<int, 32> V1Mask(Mask.size(), -1);
7071 SmallVector<int, 32> V2Mask(Mask.size(), -1);
7072 SmallVector<int, 32> BlendMask(Mask.size(), -1);
7073 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7074 if (Mask[i] >= 0 && Mask[i] < Size) {
7075 V1Mask[i] = Mask[i];
7077 } else if (Mask[i] >= Size) {
7078 V2Mask[i] = Mask[i] - Size;
7079 BlendMask[i] = i + Size;
7082 // Try to lower with the simpler initial blend strategy unless one of the
7083 // input shuffles would be a no-op. We prefer to shuffle inputs as the
7084 // shuffle may be able to fold with a load or other benefit. However, when
7085 // we'll have to do 2x as many shuffles in order to achieve this, blending
7086 // first is a better strategy.
7087 if (!isNoopShuffleMask(V1Mask) && !isNoopShuffleMask(V2Mask))
7088 if (SDValue BlendPerm =
7089 lowerVectorShuffleAsBlendAndPermute(DL, VT, V1, V2, Mask, DAG))
7092 V1 = DAG.getVectorShuffle(VT, DL, V1, DAG.getUNDEF(VT), V1Mask);
7093 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Mask);
7094 return DAG.getVectorShuffle(VT, DL, V1, V2, BlendMask);
7097 /// \brief Try to lower a vector shuffle as a byte rotation.
7099 /// SSSE3 has a generic PALIGNR instruction in x86 that will do an arbitrary
7100 /// byte-rotation of the concatenation of two vectors; pre-SSSE3 can use
7101 /// a PSRLDQ/PSLLDQ/POR pattern to get a similar effect. This routine will
7102 /// try to generically lower a vector shuffle through such an pattern. It
7103 /// does not check for the profitability of lowering either as PALIGNR or
7104 /// PSRLDQ/PSLLDQ/POR, only whether the mask is valid to lower in that form.
7105 /// This matches shuffle vectors that look like:
7107 /// v8i16 [11, 12, 13, 14, 15, 0, 1, 2]
7109 /// Essentially it concatenates V1 and V2, shifts right by some number of
7110 /// elements, and takes the low elements as the result. Note that while this is
7111 /// specified as a *right shift* because x86 is little-endian, it is a *left
7112 /// rotate* of the vector lanes.
7113 static SDValue lowerVectorShuffleAsByteRotate(SDLoc DL, MVT VT, SDValue V1,
7116 const X86Subtarget *Subtarget,
7117 SelectionDAG &DAG) {
7118 assert(!isNoopShuffleMask(Mask) && "We shouldn't lower no-op shuffles!");
7120 int NumElts = Mask.size();
7121 int NumLanes = VT.getSizeInBits() / 128;
7122 int NumLaneElts = NumElts / NumLanes;
7124 // We need to detect various ways of spelling a rotation:
7125 // [11, 12, 13, 14, 15, 0, 1, 2]
7126 // [-1, 12, 13, 14, -1, -1, 1, -1]
7127 // [-1, -1, -1, -1, -1, -1, 1, 2]
7128 // [ 3, 4, 5, 6, 7, 8, 9, 10]
7129 // [-1, 4, 5, 6, -1, -1, 9, -1]
7130 // [-1, 4, 5, 6, -1, -1, -1, -1]
7133 for (int l = 0; l < NumElts; l += NumLaneElts) {
7134 for (int i = 0; i < NumLaneElts; ++i) {
7135 if (Mask[l + i] == -1)
7137 assert(Mask[l + i] >= 0 && "Only -1 is a valid negative mask element!");
7139 // Get the mod-Size index and lane correct it.
7140 int LaneIdx = (Mask[l + i] % NumElts) - l;
7141 // Make sure it was in this lane.
7142 if (LaneIdx < 0 || LaneIdx >= NumLaneElts)
7145 // Determine where a rotated vector would have started.
7146 int StartIdx = i - LaneIdx;
7148 // The identity rotation isn't interesting, stop.
7151 // If we found the tail of a vector the rotation must be the missing
7152 // front. If we found the head of a vector, it must be how much of the
7154 int CandidateRotation = StartIdx < 0 ? -StartIdx : NumLaneElts - StartIdx;
7157 Rotation = CandidateRotation;
7158 else if (Rotation != CandidateRotation)
7159 // The rotations don't match, so we can't match this mask.
7162 // Compute which value this mask is pointing at.
7163 SDValue MaskV = Mask[l + i] < NumElts ? V1 : V2;
7165 // Compute which of the two target values this index should be assigned
7166 // to. This reflects whether the high elements are remaining or the low
7167 // elements are remaining.
7168 SDValue &TargetV = StartIdx < 0 ? Hi : Lo;
7170 // Either set up this value if we've not encountered it before, or check
7171 // that it remains consistent.
7174 else if (TargetV != MaskV)
7175 // This may be a rotation, but it pulls from the inputs in some
7176 // unsupported interleaving.
7181 // Check that we successfully analyzed the mask, and normalize the results.
7182 assert(Rotation != 0 && "Failed to locate a viable rotation!");
7183 assert((Lo || Hi) && "Failed to find a rotated input vector!");
7189 // The actual rotate instruction rotates bytes, so we need to scale the
7190 // rotation based on how many bytes are in the vector lane.
7191 int Scale = 16 / NumLaneElts;
7193 // SSSE3 targets can use the palignr instruction.
7194 if (Subtarget->hasSSSE3()) {
7195 // Cast the inputs to i8 vector of correct length to match PALIGNR.
7196 MVT AlignVT = MVT::getVectorVT(MVT::i8, 16 * NumLanes);
7197 Lo = DAG.getBitcast(AlignVT, Lo);
7198 Hi = DAG.getBitcast(AlignVT, Hi);
7200 return DAG.getBitcast(
7201 VT, DAG.getNode(X86ISD::PALIGNR, DL, AlignVT, Lo, Hi,
7202 DAG.getConstant(Rotation * Scale, DL, MVT::i8)));
7205 assert(VT.getSizeInBits() == 128 &&
7206 "Rotate-based lowering only supports 128-bit lowering!");
7207 assert(Mask.size() <= 16 &&
7208 "Can shuffle at most 16 bytes in a 128-bit vector!");
7210 // Default SSE2 implementation
7211 int LoByteShift = 16 - Rotation * Scale;
7212 int HiByteShift = Rotation * Scale;
7214 // Cast the inputs to v2i64 to match PSLLDQ/PSRLDQ.
7215 Lo = DAG.getBitcast(MVT::v2i64, Lo);
7216 Hi = DAG.getBitcast(MVT::v2i64, Hi);
7218 SDValue LoShift = DAG.getNode(X86ISD::VSHLDQ, DL, MVT::v2i64, Lo,
7219 DAG.getConstant(LoByteShift, DL, MVT::i8));
7220 SDValue HiShift = DAG.getNode(X86ISD::VSRLDQ, DL, MVT::v2i64, Hi,
7221 DAG.getConstant(HiByteShift, DL, MVT::i8));
7222 return DAG.getBitcast(VT,
7223 DAG.getNode(ISD::OR, DL, MVT::v2i64, LoShift, HiShift));
7226 /// \brief Try to lower a vector shuffle as a bit shift (shifts in zeros).
7228 /// Attempts to match a shuffle mask against the PSLL(W/D/Q/DQ) and
7229 /// PSRL(W/D/Q/DQ) SSE2 and AVX2 logical bit-shift instructions. The function
7230 /// matches elements from one of the input vectors shuffled to the left or
7231 /// right with zeroable elements 'shifted in'. It handles both the strictly
7232 /// bit-wise element shifts and the byte shift across an entire 128-bit double
7235 /// PSHL : (little-endian) left bit shift.
7236 /// [ zz, 0, zz, 2 ]
7237 /// [ -1, 4, zz, -1 ]
7238 /// PSRL : (little-endian) right bit shift.
7240 /// [ -1, -1, 7, zz]
7241 /// PSLLDQ : (little-endian) left byte shift
7242 /// [ zz, 0, 1, 2, 3, 4, 5, 6]
7243 /// [ zz, zz, -1, -1, 2, 3, 4, -1]
7244 /// [ zz, zz, zz, zz, zz, zz, -1, 1]
7245 /// PSRLDQ : (little-endian) right byte shift
7246 /// [ 5, 6, 7, zz, zz, zz, zz, zz]
7247 /// [ -1, 5, 6, 7, zz, zz, zz, zz]
7248 /// [ 1, 2, -1, -1, -1, -1, zz, zz]
7249 static SDValue lowerVectorShuffleAsShift(SDLoc DL, MVT VT, SDValue V1,
7250 SDValue V2, ArrayRef<int> Mask,
7251 SelectionDAG &DAG) {
7252 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7254 int Size = Mask.size();
7255 assert(Size == (int)VT.getVectorNumElements() && "Unexpected mask size");
7257 auto CheckZeros = [&](int Shift, int Scale, bool Left) {
7258 for (int i = 0; i < Size; i += Scale)
7259 for (int j = 0; j < Shift; ++j)
7260 if (!Zeroable[i + j + (Left ? 0 : (Scale - Shift))])
7266 auto MatchShift = [&](int Shift, int Scale, bool Left, SDValue V) {
7267 for (int i = 0; i != Size; i += Scale) {
7268 unsigned Pos = Left ? i + Shift : i;
7269 unsigned Low = Left ? i : i + Shift;
7270 unsigned Len = Scale - Shift;
7271 if (!isSequentialOrUndefInRange(Mask, Pos, Len,
7272 Low + (V == V1 ? 0 : Size)))
7276 int ShiftEltBits = VT.getScalarSizeInBits() * Scale;
7277 bool ByteShift = ShiftEltBits > 64;
7278 unsigned OpCode = Left ? (ByteShift ? X86ISD::VSHLDQ : X86ISD::VSHLI)
7279 : (ByteShift ? X86ISD::VSRLDQ : X86ISD::VSRLI);
7280 int ShiftAmt = Shift * VT.getScalarSizeInBits() / (ByteShift ? 8 : 1);
7282 // Normalize the scale for byte shifts to still produce an i64 element
7284 Scale = ByteShift ? Scale / 2 : Scale;
7286 // We need to round trip through the appropriate type for the shift.
7287 MVT ShiftSVT = MVT::getIntegerVT(VT.getScalarSizeInBits() * Scale);
7288 MVT ShiftVT = MVT::getVectorVT(ShiftSVT, Size / Scale);
7289 assert(DAG.getTargetLoweringInfo().isTypeLegal(ShiftVT) &&
7290 "Illegal integer vector type");
7291 V = DAG.getBitcast(ShiftVT, V);
7293 V = DAG.getNode(OpCode, DL, ShiftVT, V,
7294 DAG.getConstant(ShiftAmt, DL, MVT::i8));
7295 return DAG.getBitcast(VT, V);
7298 // SSE/AVX supports logical shifts up to 64-bit integers - so we can just
7299 // keep doubling the size of the integer elements up to that. We can
7300 // then shift the elements of the integer vector by whole multiples of
7301 // their width within the elements of the larger integer vector. Test each
7302 // multiple to see if we can find a match with the moved element indices
7303 // and that the shifted in elements are all zeroable.
7304 for (int Scale = 2; Scale * VT.getScalarSizeInBits() <= 128; Scale *= 2)
7305 for (int Shift = 1; Shift != Scale; ++Shift)
7306 for (bool Left : {true, false})
7307 if (CheckZeros(Shift, Scale, Left))
7308 for (SDValue V : {V1, V2})
7309 if (SDValue Match = MatchShift(Shift, Scale, Left, V))
7316 /// \brief Try to lower a vector shuffle using SSE4a EXTRQ/INSERTQ.
7317 static SDValue lowerVectorShuffleWithSSE4A(SDLoc DL, MVT VT, SDValue V1,
7318 SDValue V2, ArrayRef<int> Mask,
7319 SelectionDAG &DAG) {
7320 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7321 assert(!Zeroable.all() && "Fully zeroable shuffle mask");
7323 int Size = Mask.size();
7324 int HalfSize = Size / 2;
7325 assert(Size == (int)VT.getVectorNumElements() && "Unexpected mask size");
7327 // Upper half must be undefined.
7328 if (!isUndefInRange(Mask, HalfSize, HalfSize))
7331 // EXTRQ: Extract Len elements from lower half of source, starting at Idx.
7332 // Remainder of lower half result is zero and upper half is all undef.
7333 auto LowerAsEXTRQ = [&]() {
7334 // Determine the extraction length from the part of the
7335 // lower half that isn't zeroable.
7337 for (; Len > 0; --Len)
7338 if (!Zeroable[Len - 1])
7340 assert(Len > 0 && "Zeroable shuffle mask");
7342 // Attempt to match first Len sequential elements from the lower half.
7345 for (int i = 0; i != Len; ++i) {
7349 SDValue &V = (M < Size ? V1 : V2);
7352 // All mask elements must be in the lower half.
7356 if (Idx < 0 || (Src == V && Idx == (M - i))) {
7367 assert((Idx + Len) <= HalfSize && "Illegal extraction mask");
7368 int BitLen = (Len * VT.getScalarSizeInBits()) & 0x3f;
7369 int BitIdx = (Idx * VT.getScalarSizeInBits()) & 0x3f;
7370 return DAG.getNode(X86ISD::EXTRQI, DL, VT, Src,
7371 DAG.getConstant(BitLen, DL, MVT::i8),
7372 DAG.getConstant(BitIdx, DL, MVT::i8));
7375 if (SDValue ExtrQ = LowerAsEXTRQ())
7378 // INSERTQ: Extract lowest Len elements from lower half of second source and
7379 // insert over first source, starting at Idx.
7380 // { A[0], .., A[Idx-1], B[0], .., B[Len-1], A[Idx+Len], .., UNDEF, ... }
7381 auto LowerAsInsertQ = [&]() {
7382 for (int Idx = 0; Idx != HalfSize; ++Idx) {
7385 // Attempt to match first source from mask before insertion point.
7386 if (isUndefInRange(Mask, 0, Idx)) {
7388 } else if (isSequentialOrUndefInRange(Mask, 0, Idx, 0)) {
7390 } else if (isSequentialOrUndefInRange(Mask, 0, Idx, Size)) {
7396 // Extend the extraction length looking to match both the insertion of
7397 // the second source and the remaining elements of the first.
7398 for (int Hi = Idx + 1; Hi <= HalfSize; ++Hi) {
7403 if (isSequentialOrUndefInRange(Mask, Idx, Len, 0)) {
7405 } else if (isSequentialOrUndefInRange(Mask, Idx, Len, Size)) {
7411 // Match the remaining elements of the lower half.
7412 if (isUndefInRange(Mask, Hi, HalfSize - Hi)) {
7414 } else if ((!Base || (Base == V1)) &&
7415 isSequentialOrUndefInRange(Mask, Hi, HalfSize - Hi, Hi)) {
7417 } else if ((!Base || (Base == V2)) &&
7418 isSequentialOrUndefInRange(Mask, Hi, HalfSize - Hi,
7425 // We may not have a base (first source) - this can safely be undefined.
7427 Base = DAG.getUNDEF(VT);
7429 int BitLen = (Len * VT.getScalarSizeInBits()) & 0x3f;
7430 int BitIdx = (Idx * VT.getScalarSizeInBits()) & 0x3f;
7431 return DAG.getNode(X86ISD::INSERTQI, DL, VT, Base, Insert,
7432 DAG.getConstant(BitLen, DL, MVT::i8),
7433 DAG.getConstant(BitIdx, DL, MVT::i8));
7440 if (SDValue InsertQ = LowerAsInsertQ())
7446 /// \brief Lower a vector shuffle as a zero or any extension.
7448 /// Given a specific number of elements, element bit width, and extension
7449 /// stride, produce either a zero or any extension based on the available
7450 /// features of the subtarget. The extended elements are consecutive and
7451 /// begin and can start from an offseted element index in the input; to
7452 /// avoid excess shuffling the offset must either being in the bottom lane
7453 /// or at the start of a higher lane. All extended elements must be from
7455 static SDValue lowerVectorShuffleAsSpecificZeroOrAnyExtend(
7456 SDLoc DL, MVT VT, int Scale, int Offset, bool AnyExt, SDValue InputV,
7457 ArrayRef<int> Mask, const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7458 assert(Scale > 1 && "Need a scale to extend.");
7459 int EltBits = VT.getScalarSizeInBits();
7460 int NumElements = VT.getVectorNumElements();
7461 int NumEltsPerLane = 128 / EltBits;
7462 int OffsetLane = Offset / NumEltsPerLane;
7463 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
7464 "Only 8, 16, and 32 bit elements can be extended.");
7465 assert(Scale * EltBits <= 64 && "Cannot zero extend past 64 bits.");
7466 assert(0 <= Offset && "Extension offset must be positive.");
7467 assert((Offset < NumEltsPerLane || Offset % NumEltsPerLane == 0) &&
7468 "Extension offset must be in the first lane or start an upper lane.");
7470 // Check that an index is in same lane as the base offset.
7471 auto SafeOffset = [&](int Idx) {
7472 return OffsetLane == (Idx / NumEltsPerLane);
7475 // Shift along an input so that the offset base moves to the first element.
7476 auto ShuffleOffset = [&](SDValue V) {
7480 SmallVector<int, 8> ShMask((unsigned)NumElements, -1);
7481 for (int i = 0; i * Scale < NumElements; ++i) {
7482 int SrcIdx = i + Offset;
7483 ShMask[i] = SafeOffset(SrcIdx) ? SrcIdx : -1;
7485 return DAG.getVectorShuffle(VT, DL, V, DAG.getUNDEF(VT), ShMask);
7488 // Found a valid zext mask! Try various lowering strategies based on the
7489 // input type and available ISA extensions.
7490 if (Subtarget->hasSSE41()) {
7491 // Not worth offseting 128-bit vectors if scale == 2, a pattern using
7492 // PUNPCK will catch this in a later shuffle match.
7493 if (Offset && Scale == 2 && VT.getSizeInBits() == 128)
7495 MVT ExtVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits * Scale),
7496 NumElements / Scale);
7497 InputV = DAG.getNode(X86ISD::VZEXT, DL, ExtVT, ShuffleOffset(InputV));
7498 return DAG.getBitcast(VT, InputV);
7501 assert(VT.getSizeInBits() == 128 && "Only 128-bit vectors can be extended.");
7503 // For any extends we can cheat for larger element sizes and use shuffle
7504 // instructions that can fold with a load and/or copy.
7505 if (AnyExt && EltBits == 32) {
7506 int PSHUFDMask[4] = {Offset, -1, SafeOffset(Offset + 1) ? Offset + 1 : -1,
7508 return DAG.getBitcast(
7509 VT, DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
7510 DAG.getBitcast(MVT::v4i32, InputV),
7511 getV4X86ShuffleImm8ForMask(PSHUFDMask, DL, DAG)));
7513 if (AnyExt && EltBits == 16 && Scale > 2) {
7514 int PSHUFDMask[4] = {Offset / 2, -1,
7515 SafeOffset(Offset + 1) ? (Offset + 1) / 2 : -1, -1};
7516 InputV = DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
7517 DAG.getBitcast(MVT::v4i32, InputV),
7518 getV4X86ShuffleImm8ForMask(PSHUFDMask, DL, DAG));
7519 int PSHUFWMask[4] = {1, -1, -1, -1};
7520 unsigned OddEvenOp = (Offset & 1 ? X86ISD::PSHUFLW : X86ISD::PSHUFHW);
7521 return DAG.getBitcast(
7522 VT, DAG.getNode(OddEvenOp, DL, MVT::v8i16,
7523 DAG.getBitcast(MVT::v8i16, InputV),
7524 getV4X86ShuffleImm8ForMask(PSHUFWMask, DL, DAG)));
7527 // The SSE4A EXTRQ instruction can efficiently extend the first 2 lanes
7529 if ((Scale * EltBits) == 64 && EltBits < 32 && Subtarget->hasSSE4A()) {
7530 assert(NumElements == (int)Mask.size() && "Unexpected shuffle mask size!");
7531 assert(VT.getSizeInBits() == 128 && "Unexpected vector width!");
7533 int LoIdx = Offset * EltBits;
7534 SDValue Lo = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64,
7535 DAG.getNode(X86ISD::EXTRQI, DL, VT, InputV,
7536 DAG.getConstant(EltBits, DL, MVT::i8),
7537 DAG.getConstant(LoIdx, DL, MVT::i8)));
7539 if (isUndefInRange(Mask, NumElements / 2, NumElements / 2) ||
7540 !SafeOffset(Offset + 1))
7541 return DAG.getNode(ISD::BITCAST, DL, VT, Lo);
7543 int HiIdx = (Offset + 1) * EltBits;
7544 SDValue Hi = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64,
7545 DAG.getNode(X86ISD::EXTRQI, DL, VT, InputV,
7546 DAG.getConstant(EltBits, DL, MVT::i8),
7547 DAG.getConstant(HiIdx, DL, MVT::i8)));
7548 return DAG.getNode(ISD::BITCAST, DL, VT,
7549 DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2i64, Lo, Hi));
7552 // If this would require more than 2 unpack instructions to expand, use
7553 // pshufb when available. We can only use more than 2 unpack instructions
7554 // when zero extending i8 elements which also makes it easier to use pshufb.
7555 if (Scale > 4 && EltBits == 8 && Subtarget->hasSSSE3()) {
7556 assert(NumElements == 16 && "Unexpected byte vector width!");
7557 SDValue PSHUFBMask[16];
7558 for (int i = 0; i < 16; ++i) {
7559 int Idx = Offset + (i / Scale);
7560 PSHUFBMask[i] = DAG.getConstant(
7561 (i % Scale == 0 && SafeOffset(Idx)) ? Idx : 0x80, DL, MVT::i8);
7563 InputV = DAG.getBitcast(MVT::v16i8, InputV);
7564 return DAG.getBitcast(VT,
7565 DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, InputV,
7566 DAG.getNode(ISD::BUILD_VECTOR, DL,
7567 MVT::v16i8, PSHUFBMask)));
7570 // If we are extending from an offset, ensure we start on a boundary that
7571 // we can unpack from.
7572 int AlignToUnpack = Offset % (NumElements / Scale);
7573 if (AlignToUnpack) {
7574 SmallVector<int, 8> ShMask((unsigned)NumElements, -1);
7575 for (int i = AlignToUnpack; i < NumElements; ++i)
7576 ShMask[i - AlignToUnpack] = i;
7577 InputV = DAG.getVectorShuffle(VT, DL, InputV, DAG.getUNDEF(VT), ShMask);
7578 Offset -= AlignToUnpack;
7581 // Otherwise emit a sequence of unpacks.
7583 unsigned UnpackLoHi = X86ISD::UNPCKL;
7584 if (Offset >= (NumElements / 2)) {
7585 UnpackLoHi = X86ISD::UNPCKH;
7586 Offset -= (NumElements / 2);
7589 MVT InputVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits), NumElements);
7590 SDValue Ext = AnyExt ? DAG.getUNDEF(InputVT)
7591 : getZeroVector(InputVT, Subtarget, DAG, DL);
7592 InputV = DAG.getBitcast(InputVT, InputV);
7593 InputV = DAG.getNode(UnpackLoHi, DL, InputVT, InputV, Ext);
7597 } while (Scale > 1);
7598 return DAG.getBitcast(VT, InputV);
7601 /// \brief Try to lower a vector shuffle as a zero extension on any microarch.
7603 /// This routine will try to do everything in its power to cleverly lower
7604 /// a shuffle which happens to match the pattern of a zero extend. It doesn't
7605 /// check for the profitability of this lowering, it tries to aggressively
7606 /// match this pattern. It will use all of the micro-architectural details it
7607 /// can to emit an efficient lowering. It handles both blends with all-zero
7608 /// inputs to explicitly zero-extend and undef-lanes (sometimes undef due to
7609 /// masking out later).
7611 /// The reason we have dedicated lowering for zext-style shuffles is that they
7612 /// are both incredibly common and often quite performance sensitive.
7613 static SDValue lowerVectorShuffleAsZeroOrAnyExtend(
7614 SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
7615 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7616 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7618 int Bits = VT.getSizeInBits();
7619 int NumLanes = Bits / 128;
7620 int NumElements = VT.getVectorNumElements();
7621 int NumEltsPerLane = NumElements / NumLanes;
7622 assert(VT.getScalarSizeInBits() <= 32 &&
7623 "Exceeds 32-bit integer zero extension limit");
7624 assert((int)Mask.size() == NumElements && "Unexpected shuffle mask size");
7626 // Define a helper function to check a particular ext-scale and lower to it if
7628 auto Lower = [&](int Scale) -> SDValue {
7633 for (int i = 0; i < NumElements; ++i) {
7636 continue; // Valid anywhere but doesn't tell us anything.
7637 if (i % Scale != 0) {
7638 // Each of the extended elements need to be zeroable.
7642 // We no longer are in the anyext case.
7647 // Each of the base elements needs to be consecutive indices into the
7648 // same input vector.
7649 SDValue V = M < NumElements ? V1 : V2;
7650 M = M % NumElements;
7653 Offset = M - (i / Scale);
7654 } else if (InputV != V)
7655 return SDValue(); // Flip-flopping inputs.
7657 // Offset must start in the lowest 128-bit lane or at the start of an
7659 // FIXME: Is it ever worth allowing a negative base offset?
7660 if (!((0 <= Offset && Offset < NumEltsPerLane) ||
7661 (Offset % NumEltsPerLane) == 0))
7664 // If we are offsetting, all referenced entries must come from the same
7666 if (Offset && (Offset / NumEltsPerLane) != (M / NumEltsPerLane))
7669 if ((M % NumElements) != (Offset + (i / Scale)))
7670 return SDValue(); // Non-consecutive strided elements.
7674 // If we fail to find an input, we have a zero-shuffle which should always
7675 // have already been handled.
7676 // FIXME: Maybe handle this here in case during blending we end up with one?
7680 // If we are offsetting, don't extend if we only match a single input, we
7681 // can always do better by using a basic PSHUF or PUNPCK.
7682 if (Offset != 0 && Matches < 2)
7685 return lowerVectorShuffleAsSpecificZeroOrAnyExtend(
7686 DL, VT, Scale, Offset, AnyExt, InputV, Mask, Subtarget, DAG);
7689 // The widest scale possible for extending is to a 64-bit integer.
7690 assert(Bits % 64 == 0 &&
7691 "The number of bits in a vector must be divisible by 64 on x86!");
7692 int NumExtElements = Bits / 64;
7694 // Each iteration, try extending the elements half as much, but into twice as
7696 for (; NumExtElements < NumElements; NumExtElements *= 2) {
7697 assert(NumElements % NumExtElements == 0 &&
7698 "The input vector size must be divisible by the extended size.");
7699 if (SDValue V = Lower(NumElements / NumExtElements))
7703 // General extends failed, but 128-bit vectors may be able to use MOVQ.
7707 // Returns one of the source operands if the shuffle can be reduced to a
7708 // MOVQ, copying the lower 64-bits and zero-extending to the upper 64-bits.
7709 auto CanZExtLowHalf = [&]() {
7710 for (int i = NumElements / 2; i != NumElements; ++i)
7713 if (isSequentialOrUndefInRange(Mask, 0, NumElements / 2, 0))
7715 if (isSequentialOrUndefInRange(Mask, 0, NumElements / 2, NumElements))
7720 if (SDValue V = CanZExtLowHalf()) {
7721 V = DAG.getBitcast(MVT::v2i64, V);
7722 V = DAG.getNode(X86ISD::VZEXT_MOVL, DL, MVT::v2i64, V);
7723 return DAG.getBitcast(VT, V);
7726 // No viable ext lowering found.
7730 /// \brief Try to get a scalar value for a specific element of a vector.
7732 /// Looks through BUILD_VECTOR and SCALAR_TO_VECTOR nodes to find a scalar.
7733 static SDValue getScalarValueForVectorElement(SDValue V, int Idx,
7734 SelectionDAG &DAG) {
7735 MVT VT = V.getSimpleValueType();
7736 MVT EltVT = VT.getVectorElementType();
7737 while (V.getOpcode() == ISD::BITCAST)
7738 V = V.getOperand(0);
7739 // If the bitcasts shift the element size, we can't extract an equivalent
7741 MVT NewVT = V.getSimpleValueType();
7742 if (!NewVT.isVector() || NewVT.getScalarSizeInBits() != VT.getScalarSizeInBits())
7745 if (V.getOpcode() == ISD::BUILD_VECTOR ||
7746 (Idx == 0 && V.getOpcode() == ISD::SCALAR_TO_VECTOR)) {
7747 // Ensure the scalar operand is the same size as the destination.
7748 // FIXME: Add support for scalar truncation where possible.
7749 SDValue S = V.getOperand(Idx);
7750 if (EltVT.getSizeInBits() == S.getSimpleValueType().getSizeInBits())
7751 return DAG.getNode(ISD::BITCAST, SDLoc(V), EltVT, S);
7757 /// \brief Helper to test for a load that can be folded with x86 shuffles.
7759 /// This is particularly important because the set of instructions varies
7760 /// significantly based on whether the operand is a load or not.
7761 static bool isShuffleFoldableLoad(SDValue V) {
7762 while (V.getOpcode() == ISD::BITCAST)
7763 V = V.getOperand(0);
7765 return ISD::isNON_EXTLoad(V.getNode());
7768 /// \brief Try to lower insertion of a single element into a zero vector.
7770 /// This is a common pattern that we have especially efficient patterns to lower
7771 /// across all subtarget feature sets.
7772 static SDValue lowerVectorShuffleAsElementInsertion(
7773 SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
7774 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7775 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7777 MVT EltVT = VT.getVectorElementType();
7779 int V2Index = std::find_if(Mask.begin(), Mask.end(),
7780 [&Mask](int M) { return M >= (int)Mask.size(); }) -
7782 bool IsV1Zeroable = true;
7783 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7784 if (i != V2Index && !Zeroable[i]) {
7785 IsV1Zeroable = false;
7789 // Check for a single input from a SCALAR_TO_VECTOR node.
7790 // FIXME: All of this should be canonicalized into INSERT_VECTOR_ELT and
7791 // all the smarts here sunk into that routine. However, the current
7792 // lowering of BUILD_VECTOR makes that nearly impossible until the old
7793 // vector shuffle lowering is dead.
7794 SDValue V2S = getScalarValueForVectorElement(V2, Mask[V2Index] - Mask.size(),
7796 if (V2S && DAG.getTargetLoweringInfo().isTypeLegal(V2S.getValueType())) {
7797 // We need to zext the scalar if it is smaller than an i32.
7798 V2S = DAG.getBitcast(EltVT, V2S);
7799 if (EltVT == MVT::i8 || EltVT == MVT::i16) {
7800 // Using zext to expand a narrow element won't work for non-zero
7805 // Zero-extend directly to i32.
7807 V2S = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, V2S);
7809 V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, ExtVT, V2S);
7810 } else if (Mask[V2Index] != (int)Mask.size() || EltVT == MVT::i8 ||
7811 EltVT == MVT::i16) {
7812 // Either not inserting from the low element of the input or the input
7813 // element size is too small to use VZEXT_MOVL to clear the high bits.
7817 if (!IsV1Zeroable) {
7818 // If V1 can't be treated as a zero vector we have fewer options to lower
7819 // this. We can't support integer vectors or non-zero targets cheaply, and
7820 // the V1 elements can't be permuted in any way.
7821 assert(VT == ExtVT && "Cannot change extended type when non-zeroable!");
7822 if (!VT.isFloatingPoint() || V2Index != 0)
7824 SmallVector<int, 8> V1Mask(Mask.begin(), Mask.end());
7825 V1Mask[V2Index] = -1;
7826 if (!isNoopShuffleMask(V1Mask))
7828 // This is essentially a special case blend operation, but if we have
7829 // general purpose blend operations, they are always faster. Bail and let
7830 // the rest of the lowering handle these as blends.
7831 if (Subtarget->hasSSE41())
7834 // Otherwise, use MOVSD or MOVSS.
7835 assert((EltVT == MVT::f32 || EltVT == MVT::f64) &&
7836 "Only two types of floating point element types to handle!");
7837 return DAG.getNode(EltVT == MVT::f32 ? X86ISD::MOVSS : X86ISD::MOVSD, DL,
7841 // This lowering only works for the low element with floating point vectors.
7842 if (VT.isFloatingPoint() && V2Index != 0)
7845 V2 = DAG.getNode(X86ISD::VZEXT_MOVL, DL, ExtVT, V2);
7847 V2 = DAG.getBitcast(VT, V2);
7850 // If we have 4 or fewer lanes we can cheaply shuffle the element into
7851 // the desired position. Otherwise it is more efficient to do a vector
7852 // shift left. We know that we can do a vector shift left because all
7853 // the inputs are zero.
7854 if (VT.isFloatingPoint() || VT.getVectorNumElements() <= 4) {
7855 SmallVector<int, 4> V2Shuffle(Mask.size(), 1);
7856 V2Shuffle[V2Index] = 0;
7857 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Shuffle);
7859 V2 = DAG.getBitcast(MVT::v2i64, V2);
7861 X86ISD::VSHLDQ, DL, MVT::v2i64, V2,
7862 DAG.getConstant(V2Index * EltVT.getSizeInBits() / 8, DL,
7863 DAG.getTargetLoweringInfo().getScalarShiftAmountTy(
7864 DAG.getDataLayout(), VT)));
7865 V2 = DAG.getBitcast(VT, V2);
7871 /// \brief Try to lower broadcast of a single element.
7873 /// For convenience, this code also bundles all of the subtarget feature set
7874 /// filtering. While a little annoying to re-dispatch on type here, there isn't
7875 /// a convenient way to factor it out.
7876 static SDValue lowerVectorShuffleAsBroadcast(SDLoc DL, MVT VT, SDValue V,
7878 const X86Subtarget *Subtarget,
7879 SelectionDAG &DAG) {
7880 if (!Subtarget->hasAVX())
7882 if (VT.isInteger() && !Subtarget->hasAVX2())
7885 // Check that the mask is a broadcast.
7886 int BroadcastIdx = -1;
7888 if (M >= 0 && BroadcastIdx == -1)
7890 else if (M >= 0 && M != BroadcastIdx)
7893 assert(BroadcastIdx < (int)Mask.size() && "We only expect to be called with "
7894 "a sorted mask where the broadcast "
7897 // Go up the chain of (vector) values to find a scalar load that we can
7898 // combine with the broadcast.
7900 switch (V.getOpcode()) {
7901 case ISD::CONCAT_VECTORS: {
7902 int OperandSize = Mask.size() / V.getNumOperands();
7903 V = V.getOperand(BroadcastIdx / OperandSize);
7904 BroadcastIdx %= OperandSize;
7908 case ISD::INSERT_SUBVECTOR: {
7909 SDValue VOuter = V.getOperand(0), VInner = V.getOperand(1);
7910 auto ConstantIdx = dyn_cast<ConstantSDNode>(V.getOperand(2));
7914 int BeginIdx = (int)ConstantIdx->getZExtValue();
7916 BeginIdx + (int)VInner.getValueType().getVectorNumElements();
7917 if (BroadcastIdx >= BeginIdx && BroadcastIdx < EndIdx) {
7918 BroadcastIdx -= BeginIdx;
7929 // Check if this is a broadcast of a scalar. We special case lowering
7930 // for scalars so that we can more effectively fold with loads.
7931 // First, look through bitcast: if the original value has a larger element
7932 // type than the shuffle, the broadcast element is in essence truncated.
7933 // Make that explicit to ease folding.
7934 if (V.getOpcode() == ISD::BITCAST && VT.isInteger()) {
7935 EVT EltVT = VT.getVectorElementType();
7936 SDValue V0 = V.getOperand(0);
7937 EVT V0VT = V0.getValueType();
7939 if (V0VT.isInteger() && V0VT.getVectorElementType().bitsGT(EltVT) &&
7940 ((V0.getOpcode() == ISD::BUILD_VECTOR ||
7941 (V0.getOpcode() == ISD::SCALAR_TO_VECTOR && BroadcastIdx == 0)))) {
7942 V = DAG.getNode(ISD::TRUNCATE, DL, EltVT, V0.getOperand(BroadcastIdx));
7947 // Also check the simpler case, where we can directly reuse the scalar.
7948 if (V.getOpcode() == ISD::BUILD_VECTOR ||
7949 (V.getOpcode() == ISD::SCALAR_TO_VECTOR && BroadcastIdx == 0)) {
7950 V = V.getOperand(BroadcastIdx);
7952 // If the scalar isn't a load, we can't broadcast from it in AVX1.
7953 // Only AVX2 has register broadcasts.
7954 if (!Subtarget->hasAVX2() && !isShuffleFoldableLoad(V))
7956 } else if (BroadcastIdx != 0 || !Subtarget->hasAVX2()) {
7957 // We can't broadcast from a vector register without AVX2, and we can only
7958 // broadcast from the zero-element of a vector register.
7962 return DAG.getNode(X86ISD::VBROADCAST, DL, VT, V);
7965 // Check for whether we can use INSERTPS to perform the shuffle. We only use
7966 // INSERTPS when the V1 elements are already in the correct locations
7967 // because otherwise we can just always use two SHUFPS instructions which
7968 // are much smaller to encode than a SHUFPS and an INSERTPS. We can also
7969 // perform INSERTPS if a single V1 element is out of place and all V2
7970 // elements are zeroable.
7971 static SDValue lowerVectorShuffleAsInsertPS(SDValue Op, SDValue V1, SDValue V2,
7973 SelectionDAG &DAG) {
7974 assert(Op.getSimpleValueType() == MVT::v4f32 && "Bad shuffle type!");
7975 assert(V1.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
7976 assert(V2.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
7977 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
7979 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7982 int V1DstIndex = -1;
7983 int V2DstIndex = -1;
7984 bool V1UsedInPlace = false;
7986 for (int i = 0; i < 4; ++i) {
7987 // Synthesize a zero mask from the zeroable elements (includes undefs).
7993 // Flag if we use any V1 inputs in place.
7995 V1UsedInPlace = true;
7999 // We can only insert a single non-zeroable element.
8000 if (V1DstIndex != -1 || V2DstIndex != -1)
8004 // V1 input out of place for insertion.
8007 // V2 input for insertion.
8012 // Don't bother if we have no (non-zeroable) element for insertion.
8013 if (V1DstIndex == -1 && V2DstIndex == -1)
8016 // Determine element insertion src/dst indices. The src index is from the
8017 // start of the inserted vector, not the start of the concatenated vector.
8018 unsigned V2SrcIndex = 0;
8019 if (V1DstIndex != -1) {
8020 // If we have a V1 input out of place, we use V1 as the V2 element insertion
8021 // and don't use the original V2 at all.
8022 V2SrcIndex = Mask[V1DstIndex];
8023 V2DstIndex = V1DstIndex;
8026 V2SrcIndex = Mask[V2DstIndex] - 4;
8029 // If no V1 inputs are used in place, then the result is created only from
8030 // the zero mask and the V2 insertion - so remove V1 dependency.
8032 V1 = DAG.getUNDEF(MVT::v4f32);
8034 unsigned InsertPSMask = V2SrcIndex << 6 | V2DstIndex << 4 | ZMask;
8035 assert((InsertPSMask & ~0xFFu) == 0 && "Invalid mask!");
8037 // Insert the V2 element into the desired position.
8039 return DAG.getNode(X86ISD::INSERTPS, DL, MVT::v4f32, V1, V2,
8040 DAG.getConstant(InsertPSMask, DL, MVT::i8));
8043 /// \brief Try to lower a shuffle as a permute of the inputs followed by an
8044 /// UNPCK instruction.
8046 /// This specifically targets cases where we end up with alternating between
8047 /// the two inputs, and so can permute them into something that feeds a single
8048 /// UNPCK instruction. Note that this routine only targets integer vectors
8049 /// because for floating point vectors we have a generalized SHUFPS lowering
8050 /// strategy that handles everything that doesn't *exactly* match an unpack,
8051 /// making this clever lowering unnecessary.
8052 static SDValue lowerVectorShuffleAsPermuteAndUnpack(SDLoc DL, MVT VT,
8053 SDValue V1, SDValue V2,
8055 SelectionDAG &DAG) {
8056 assert(!VT.isFloatingPoint() &&
8057 "This routine only supports integer vectors.");
8058 assert(!isSingleInputShuffleMask(Mask) &&
8059 "This routine should only be used when blending two inputs.");
8060 assert(Mask.size() >= 2 && "Single element masks are invalid.");
8062 int Size = Mask.size();
8064 int NumLoInputs = std::count_if(Mask.begin(), Mask.end(), [Size](int M) {
8065 return M >= 0 && M % Size < Size / 2;
8067 int NumHiInputs = std::count_if(
8068 Mask.begin(), Mask.end(), [Size](int M) { return M % Size >= Size / 2; });
8070 bool UnpackLo = NumLoInputs >= NumHiInputs;
8072 auto TryUnpack = [&](MVT UnpackVT, int Scale) {
8073 SmallVector<int, 32> V1Mask(Mask.size(), -1);
8074 SmallVector<int, 32> V2Mask(Mask.size(), -1);
8076 for (int i = 0; i < Size; ++i) {
8080 // Each element of the unpack contains Scale elements from this mask.
8081 int UnpackIdx = i / Scale;
8083 // We only handle the case where V1 feeds the first slots of the unpack.
8084 // We rely on canonicalization to ensure this is the case.
8085 if ((UnpackIdx % 2 == 0) != (Mask[i] < Size))
8088 // Setup the mask for this input. The indexing is tricky as we have to
8089 // handle the unpack stride.
8090 SmallVectorImpl<int> &VMask = (UnpackIdx % 2 == 0) ? V1Mask : V2Mask;
8091 VMask[(UnpackIdx / 2) * Scale + i % Scale + (UnpackLo ? 0 : Size / 2)] =
8095 // If we will have to shuffle both inputs to use the unpack, check whether
8096 // we can just unpack first and shuffle the result. If so, skip this unpack.
8097 if ((NumLoInputs == 0 || NumHiInputs == 0) && !isNoopShuffleMask(V1Mask) &&
8098 !isNoopShuffleMask(V2Mask))
8101 // Shuffle the inputs into place.
8102 V1 = DAG.getVectorShuffle(VT, DL, V1, DAG.getUNDEF(VT), V1Mask);
8103 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Mask);
8105 // Cast the inputs to the type we will use to unpack them.
8106 V1 = DAG.getBitcast(UnpackVT, V1);
8107 V2 = DAG.getBitcast(UnpackVT, V2);
8109 // Unpack the inputs and cast the result back to the desired type.
8110 return DAG.getBitcast(
8111 VT, DAG.getNode(UnpackLo ? X86ISD::UNPCKL : X86ISD::UNPCKH, DL,
8115 // We try each unpack from the largest to the smallest to try and find one
8116 // that fits this mask.
8117 int OrigNumElements = VT.getVectorNumElements();
8118 int OrigScalarSize = VT.getScalarSizeInBits();
8119 for (int ScalarSize = 64; ScalarSize >= OrigScalarSize; ScalarSize /= 2) {
8120 int Scale = ScalarSize / OrigScalarSize;
8121 int NumElements = OrigNumElements / Scale;
8122 MVT UnpackVT = MVT::getVectorVT(MVT::getIntegerVT(ScalarSize), NumElements);
8123 if (SDValue Unpack = TryUnpack(UnpackVT, Scale))
8127 // If none of the unpack-rooted lowerings worked (or were profitable) try an
8129 if (NumLoInputs == 0 || NumHiInputs == 0) {
8130 assert((NumLoInputs > 0 || NumHiInputs > 0) &&
8131 "We have to have *some* inputs!");
8132 int HalfOffset = NumLoInputs == 0 ? Size / 2 : 0;
8134 // FIXME: We could consider the total complexity of the permute of each
8135 // possible unpacking. Or at the least we should consider how many
8136 // half-crossings are created.
8137 // FIXME: We could consider commuting the unpacks.
8139 SmallVector<int, 32> PermMask;
8140 PermMask.assign(Size, -1);
8141 for (int i = 0; i < Size; ++i) {
8145 assert(Mask[i] % Size >= HalfOffset && "Found input from wrong half!");
8148 2 * ((Mask[i] % Size) - HalfOffset) + (Mask[i] < Size ? 0 : 1);
8150 return DAG.getVectorShuffle(
8151 VT, DL, DAG.getNode(NumLoInputs == 0 ? X86ISD::UNPCKH : X86ISD::UNPCKL,
8153 DAG.getUNDEF(VT), PermMask);
8159 /// \brief Handle lowering of 2-lane 64-bit floating point shuffles.
8161 /// This is the basis function for the 2-lane 64-bit shuffles as we have full
8162 /// support for floating point shuffles but not integer shuffles. These
8163 /// instructions will incur a domain crossing penalty on some chips though so
8164 /// it is better to avoid lowering through this for integer vectors where
8166 static SDValue lowerV2F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8167 const X86Subtarget *Subtarget,
8168 SelectionDAG &DAG) {
8170 assert(Op.getSimpleValueType() == MVT::v2f64 && "Bad shuffle type!");
8171 assert(V1.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
8172 assert(V2.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
8173 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8174 ArrayRef<int> Mask = SVOp->getMask();
8175 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
8177 if (isSingleInputShuffleMask(Mask)) {
8178 // Use low duplicate instructions for masks that match their pattern.
8179 if (Subtarget->hasSSE3())
8180 if (isShuffleEquivalent(V1, V2, Mask, {0, 0}))
8181 return DAG.getNode(X86ISD::MOVDDUP, DL, MVT::v2f64, V1);
8183 // Straight shuffle of a single input vector. Simulate this by using the
8184 // single input as both of the "inputs" to this instruction..
8185 unsigned SHUFPDMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1);
8187 if (Subtarget->hasAVX()) {
8188 // If we have AVX, we can use VPERMILPS which will allow folding a load
8189 // into the shuffle.
8190 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v2f64, V1,
8191 DAG.getConstant(SHUFPDMask, DL, MVT::i8));
8194 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v2f64, V1, V1,
8195 DAG.getConstant(SHUFPDMask, DL, MVT::i8));
8197 assert(Mask[0] >= 0 && Mask[0] < 2 && "Non-canonicalized blend!");
8198 assert(Mask[1] >= 2 && "Non-canonicalized blend!");
8200 // If we have a single input, insert that into V1 if we can do so cheaply.
8201 if ((Mask[0] >= 2) + (Mask[1] >= 2) == 1) {
8202 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8203 DL, MVT::v2f64, V1, V2, Mask, Subtarget, DAG))
8205 // Try inverting the insertion since for v2 masks it is easy to do and we
8206 // can't reliably sort the mask one way or the other.
8207 int InverseMask[2] = {Mask[0] < 0 ? -1 : (Mask[0] ^ 2),
8208 Mask[1] < 0 ? -1 : (Mask[1] ^ 2)};
8209 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8210 DL, MVT::v2f64, V2, V1, InverseMask, Subtarget, DAG))
8214 // Try to use one of the special instruction patterns to handle two common
8215 // blend patterns if a zero-blend above didn't work.
8216 if (isShuffleEquivalent(V1, V2, Mask, {0, 3}) ||
8217 isShuffleEquivalent(V1, V2, Mask, {1, 3}))
8218 if (SDValue V1S = getScalarValueForVectorElement(V1, Mask[0], DAG))
8219 // We can either use a special instruction to load over the low double or
8220 // to move just the low double.
8222 isShuffleFoldableLoad(V1S) ? X86ISD::MOVLPD : X86ISD::MOVSD,
8224 DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2f64, V1S));
8226 if (Subtarget->hasSSE41())
8227 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v2f64, V1, V2, Mask,
8231 // Use dedicated unpack instructions for masks that match their pattern.
8233 lowerVectorShuffleWithUNPCK(DL, MVT::v2f64, Mask, V1, V2, DAG))
8236 unsigned SHUFPDMask = (Mask[0] == 1) | (((Mask[1] - 2) == 1) << 1);
8237 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v2f64, V1, V2,
8238 DAG.getConstant(SHUFPDMask, DL, MVT::i8));
8241 /// \brief Handle lowering of 2-lane 64-bit integer shuffles.
8243 /// Tries to lower a 2-lane 64-bit shuffle using shuffle operations provided by
8244 /// the integer unit to minimize domain crossing penalties. However, for blends
8245 /// it falls back to the floating point shuffle operation with appropriate bit
8247 static SDValue lowerV2I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8248 const X86Subtarget *Subtarget,
8249 SelectionDAG &DAG) {
8251 assert(Op.getSimpleValueType() == MVT::v2i64 && "Bad shuffle type!");
8252 assert(V1.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
8253 assert(V2.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
8254 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8255 ArrayRef<int> Mask = SVOp->getMask();
8256 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
8258 if (isSingleInputShuffleMask(Mask)) {
8259 // Check for being able to broadcast a single element.
8260 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v2i64, V1,
8261 Mask, Subtarget, DAG))
8264 // Straight shuffle of a single input vector. For everything from SSE2
8265 // onward this has a single fast instruction with no scary immediates.
8266 // We have to map the mask as it is actually a v4i32 shuffle instruction.
8267 V1 = DAG.getBitcast(MVT::v4i32, V1);
8268 int WidenedMask[4] = {
8269 std::max(Mask[0], 0) * 2, std::max(Mask[0], 0) * 2 + 1,
8270 std::max(Mask[1], 0) * 2, std::max(Mask[1], 0) * 2 + 1};
8271 return DAG.getBitcast(
8273 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V1,
8274 getV4X86ShuffleImm8ForMask(WidenedMask, DL, DAG)));
8276 assert(Mask[0] != -1 && "No undef lanes in multi-input v2 shuffles!");
8277 assert(Mask[1] != -1 && "No undef lanes in multi-input v2 shuffles!");
8278 assert(Mask[0] < 2 && "We sort V1 to be the first input.");
8279 assert(Mask[1] >= 2 && "We sort V2 to be the second input.");
8281 // If we have a blend of two PACKUS operations an the blend aligns with the
8282 // low and half halves, we can just merge the PACKUS operations. This is
8283 // particularly important as it lets us merge shuffles that this routine itself
8285 auto GetPackNode = [](SDValue V) {
8286 while (V.getOpcode() == ISD::BITCAST)
8287 V = V.getOperand(0);
8289 return V.getOpcode() == X86ISD::PACKUS ? V : SDValue();
8291 if (SDValue V1Pack = GetPackNode(V1))
8292 if (SDValue V2Pack = GetPackNode(V2))
8293 return DAG.getBitcast(MVT::v2i64,
8294 DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8,
8295 Mask[0] == 0 ? V1Pack.getOperand(0)
8296 : V1Pack.getOperand(1),
8297 Mask[1] == 2 ? V2Pack.getOperand(0)
8298 : V2Pack.getOperand(1)));
8300 // Try to use shift instructions.
8302 lowerVectorShuffleAsShift(DL, MVT::v2i64, V1, V2, Mask, DAG))
8305 // When loading a scalar and then shuffling it into a vector we can often do
8306 // the insertion cheaply.
8307 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8308 DL, MVT::v2i64, V1, V2, Mask, Subtarget, DAG))
8310 // Try inverting the insertion since for v2 masks it is easy to do and we
8311 // can't reliably sort the mask one way or the other.
8312 int InverseMask[2] = {Mask[0] ^ 2, Mask[1] ^ 2};
8313 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8314 DL, MVT::v2i64, V2, V1, InverseMask, Subtarget, DAG))
8317 // We have different paths for blend lowering, but they all must use the
8318 // *exact* same predicate.
8319 bool IsBlendSupported = Subtarget->hasSSE41();
8320 if (IsBlendSupported)
8321 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v2i64, V1, V2, Mask,
8325 // Use dedicated unpack instructions for masks that match their pattern.
8327 lowerVectorShuffleWithUNPCK(DL, MVT::v2i64, Mask, V1, V2, DAG))
8330 // Try to use byte rotation instructions.
8331 // Its more profitable for pre-SSSE3 to use shuffles/unpacks.
8332 if (Subtarget->hasSSSE3())
8333 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8334 DL, MVT::v2i64, V1, V2, Mask, Subtarget, DAG))
8337 // If we have direct support for blends, we should lower by decomposing into
8338 // a permute. That will be faster than the domain cross.
8339 if (IsBlendSupported)
8340 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v2i64, V1, V2,
8343 // We implement this with SHUFPD which is pretty lame because it will likely
8344 // incur 2 cycles of stall for integer vectors on Nehalem and older chips.
8345 // However, all the alternatives are still more cycles and newer chips don't
8346 // have this problem. It would be really nice if x86 had better shuffles here.
8347 V1 = DAG.getBitcast(MVT::v2f64, V1);
8348 V2 = DAG.getBitcast(MVT::v2f64, V2);
8349 return DAG.getBitcast(MVT::v2i64,
8350 DAG.getVectorShuffle(MVT::v2f64, DL, V1, V2, Mask));
8353 /// \brief Test whether this can be lowered with a single SHUFPS instruction.
8355 /// This is used to disable more specialized lowerings when the shufps lowering
8356 /// will happen to be efficient.
8357 static bool isSingleSHUFPSMask(ArrayRef<int> Mask) {
8358 // This routine only handles 128-bit shufps.
8359 assert(Mask.size() == 4 && "Unsupported mask size!");
8361 // To lower with a single SHUFPS we need to have the low half and high half
8362 // each requiring a single input.
8363 if (Mask[0] != -1 && Mask[1] != -1 && (Mask[0] < 4) != (Mask[1] < 4))
8365 if (Mask[2] != -1 && Mask[3] != -1 && (Mask[2] < 4) != (Mask[3] < 4))
8371 /// \brief Lower a vector shuffle using the SHUFPS instruction.
8373 /// This is a helper routine dedicated to lowering vector shuffles using SHUFPS.
8374 /// It makes no assumptions about whether this is the *best* lowering, it simply
8376 static SDValue lowerVectorShuffleWithSHUFPS(SDLoc DL, MVT VT,
8377 ArrayRef<int> Mask, SDValue V1,
8378 SDValue V2, SelectionDAG &DAG) {
8379 SDValue LowV = V1, HighV = V2;
8380 int NewMask[4] = {Mask[0], Mask[1], Mask[2], Mask[3]};
8383 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
8385 if (NumV2Elements == 1) {
8387 std::find_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; }) -
8390 // Compute the index adjacent to V2Index and in the same half by toggling
8392 int V2AdjIndex = V2Index ^ 1;
8394 if (Mask[V2AdjIndex] == -1) {
8395 // Handles all the cases where we have a single V2 element and an undef.
8396 // This will only ever happen in the high lanes because we commute the
8397 // vector otherwise.
8399 std::swap(LowV, HighV);
8400 NewMask[V2Index] -= 4;
8402 // Handle the case where the V2 element ends up adjacent to a V1 element.
8403 // To make this work, blend them together as the first step.
8404 int V1Index = V2AdjIndex;
8405 int BlendMask[4] = {Mask[V2Index] - 4, 0, Mask[V1Index], 0};
8406 V2 = DAG.getNode(X86ISD::SHUFP, DL, VT, V2, V1,
8407 getV4X86ShuffleImm8ForMask(BlendMask, DL, DAG));
8409 // Now proceed to reconstruct the final blend as we have the necessary
8410 // high or low half formed.
8417 NewMask[V1Index] = 2; // We put the V1 element in V2[2].
8418 NewMask[V2Index] = 0; // We shifted the V2 element into V2[0].
8420 } else if (NumV2Elements == 2) {
8421 if (Mask[0] < 4 && Mask[1] < 4) {
8422 // Handle the easy case where we have V1 in the low lanes and V2 in the
8426 } else if (Mask[2] < 4 && Mask[3] < 4) {
8427 // We also handle the reversed case because this utility may get called
8428 // when we detect a SHUFPS pattern but can't easily commute the shuffle to
8429 // arrange things in the right direction.
8435 // We have a mixture of V1 and V2 in both low and high lanes. Rather than
8436 // trying to place elements directly, just blend them and set up the final
8437 // shuffle to place them.
8439 // The first two blend mask elements are for V1, the second two are for
8441 int BlendMask[4] = {Mask[0] < 4 ? Mask[0] : Mask[1],
8442 Mask[2] < 4 ? Mask[2] : Mask[3],
8443 (Mask[0] >= 4 ? Mask[0] : Mask[1]) - 4,
8444 (Mask[2] >= 4 ? Mask[2] : Mask[3]) - 4};
8445 V1 = DAG.getNode(X86ISD::SHUFP, DL, VT, V1, V2,
8446 getV4X86ShuffleImm8ForMask(BlendMask, DL, DAG));
8448 // Now we do a normal shuffle of V1 by giving V1 as both operands to
8451 NewMask[0] = Mask[0] < 4 ? 0 : 2;
8452 NewMask[1] = Mask[0] < 4 ? 2 : 0;
8453 NewMask[2] = Mask[2] < 4 ? 1 : 3;
8454 NewMask[3] = Mask[2] < 4 ? 3 : 1;
8457 return DAG.getNode(X86ISD::SHUFP, DL, VT, LowV, HighV,
8458 getV4X86ShuffleImm8ForMask(NewMask, DL, DAG));
8461 /// \brief Lower 4-lane 32-bit floating point shuffles.
8463 /// Uses instructions exclusively from the floating point unit to minimize
8464 /// domain crossing penalties, as these are sufficient to implement all v4f32
8466 static SDValue lowerV4F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8467 const X86Subtarget *Subtarget,
8468 SelectionDAG &DAG) {
8470 assert(Op.getSimpleValueType() == MVT::v4f32 && "Bad shuffle type!");
8471 assert(V1.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
8472 assert(V2.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
8473 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8474 ArrayRef<int> Mask = SVOp->getMask();
8475 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
8478 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
8480 if (NumV2Elements == 0) {
8481 // Check for being able to broadcast a single element.
8482 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v4f32, V1,
8483 Mask, Subtarget, DAG))
8486 // Use even/odd duplicate instructions for masks that match their pattern.
8487 if (Subtarget->hasSSE3()) {
8488 if (isShuffleEquivalent(V1, V2, Mask, {0, 0, 2, 2}))
8489 return DAG.getNode(X86ISD::MOVSLDUP, DL, MVT::v4f32, V1);
8490 if (isShuffleEquivalent(V1, V2, Mask, {1, 1, 3, 3}))
8491 return DAG.getNode(X86ISD::MOVSHDUP, DL, MVT::v4f32, V1);
8494 if (Subtarget->hasAVX()) {
8495 // If we have AVX, we can use VPERMILPS which will allow folding a load
8496 // into the shuffle.
8497 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v4f32, V1,
8498 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
8501 // Otherwise, use a straight shuffle of a single input vector. We pass the
8502 // input vector to both operands to simulate this with a SHUFPS.
8503 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f32, V1, V1,
8504 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
8507 // There are special ways we can lower some single-element blends. However, we
8508 // have custom ways we can lower more complex single-element blends below that
8509 // we defer to if both this and BLENDPS fail to match, so restrict this to
8510 // when the V2 input is targeting element 0 of the mask -- that is the fast
8512 if (NumV2Elements == 1 && Mask[0] >= 4)
8513 if (SDValue V = lowerVectorShuffleAsElementInsertion(DL, MVT::v4f32, V1, V2,
8514 Mask, Subtarget, DAG))
8517 if (Subtarget->hasSSE41()) {
8518 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4f32, V1, V2, Mask,
8522 // Use INSERTPS if we can complete the shuffle efficiently.
8523 if (SDValue V = lowerVectorShuffleAsInsertPS(Op, V1, V2, Mask, DAG))
8526 if (!isSingleSHUFPSMask(Mask))
8527 if (SDValue BlendPerm = lowerVectorShuffleAsBlendAndPermute(
8528 DL, MVT::v4f32, V1, V2, Mask, DAG))
8532 // Use dedicated unpack instructions for masks that match their pattern.
8534 lowerVectorShuffleWithUNPCK(DL, MVT::v4f32, Mask, V1, V2, DAG))
8537 // Otherwise fall back to a SHUFPS lowering strategy.
8538 return lowerVectorShuffleWithSHUFPS(DL, MVT::v4f32, Mask, V1, V2, DAG);
8541 /// \brief Lower 4-lane i32 vector shuffles.
8543 /// We try to handle these with integer-domain shuffles where we can, but for
8544 /// blends we use the floating point domain blend instructions.
8545 static SDValue lowerV4I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8546 const X86Subtarget *Subtarget,
8547 SelectionDAG &DAG) {
8549 assert(Op.getSimpleValueType() == MVT::v4i32 && "Bad shuffle type!");
8550 assert(V1.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
8551 assert(V2.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
8552 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8553 ArrayRef<int> Mask = SVOp->getMask();
8554 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
8556 // Whenever we can lower this as a zext, that instruction is strictly faster
8557 // than any alternative. It also allows us to fold memory operands into the
8558 // shuffle in many cases.
8559 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v4i32, V1, V2,
8560 Mask, Subtarget, DAG))
8564 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
8566 if (NumV2Elements == 0) {
8567 // Check for being able to broadcast a single element.
8568 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v4i32, V1,
8569 Mask, Subtarget, DAG))
8572 // Straight shuffle of a single input vector. For everything from SSE2
8573 // onward this has a single fast instruction with no scary immediates.
8574 // We coerce the shuffle pattern to be compatible with UNPCK instructions
8575 // but we aren't actually going to use the UNPCK instruction because doing
8576 // so prevents folding a load into this instruction or making a copy.
8577 const int UnpackLoMask[] = {0, 0, 1, 1};
8578 const int UnpackHiMask[] = {2, 2, 3, 3};
8579 if (isShuffleEquivalent(V1, V2, Mask, {0, 0, 1, 1}))
8580 Mask = UnpackLoMask;
8581 else if (isShuffleEquivalent(V1, V2, Mask, {2, 2, 3, 3}))
8582 Mask = UnpackHiMask;
8584 return DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V1,
8585 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
8588 // Try to use shift instructions.
8590 lowerVectorShuffleAsShift(DL, MVT::v4i32, V1, V2, Mask, DAG))
8593 // There are special ways we can lower some single-element blends.
8594 if (NumV2Elements == 1)
8595 if (SDValue V = lowerVectorShuffleAsElementInsertion(DL, MVT::v4i32, V1, V2,
8596 Mask, Subtarget, DAG))
8599 // We have different paths for blend lowering, but they all must use the
8600 // *exact* same predicate.
8601 bool IsBlendSupported = Subtarget->hasSSE41();
8602 if (IsBlendSupported)
8603 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4i32, V1, V2, Mask,
8607 if (SDValue Masked =
8608 lowerVectorShuffleAsBitMask(DL, MVT::v4i32, V1, V2, Mask, DAG))
8611 // Use dedicated unpack instructions for masks that match their pattern.
8613 lowerVectorShuffleWithUNPCK(DL, MVT::v4i32, Mask, V1, V2, DAG))
8616 // Try to use byte rotation instructions.
8617 // Its more profitable for pre-SSSE3 to use shuffles/unpacks.
8618 if (Subtarget->hasSSSE3())
8619 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8620 DL, MVT::v4i32, V1, V2, Mask, Subtarget, DAG))
8623 // If we have direct support for blends, we should lower by decomposing into
8624 // a permute. That will be faster than the domain cross.
8625 if (IsBlendSupported)
8626 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4i32, V1, V2,
8629 // Try to lower by permuting the inputs into an unpack instruction.
8630 if (SDValue Unpack = lowerVectorShuffleAsPermuteAndUnpack(DL, MVT::v4i32, V1,
8634 // We implement this with SHUFPS because it can blend from two vectors.
8635 // Because we're going to eventually use SHUFPS, we use SHUFPS even to build
8636 // up the inputs, bypassing domain shift penalties that we would encur if we
8637 // directly used PSHUFD on Nehalem and older. For newer chips, this isn't
8639 return DAG.getBitcast(
8641 DAG.getVectorShuffle(MVT::v4f32, DL, DAG.getBitcast(MVT::v4f32, V1),
8642 DAG.getBitcast(MVT::v4f32, V2), Mask));
8645 /// \brief Lowering of single-input v8i16 shuffles is the cornerstone of SSE2
8646 /// shuffle lowering, and the most complex part.
8648 /// The lowering strategy is to try to form pairs of input lanes which are
8649 /// targeted at the same half of the final vector, and then use a dword shuffle
8650 /// to place them onto the right half, and finally unpack the paired lanes into
8651 /// their final position.
8653 /// The exact breakdown of how to form these dword pairs and align them on the
8654 /// correct sides is really tricky. See the comments within the function for
8655 /// more of the details.
8657 /// This code also handles repeated 128-bit lanes of v8i16 shuffles, but each
8658 /// lane must shuffle the *exact* same way. In fact, you must pass a v8 Mask to
8659 /// this routine for it to work correctly. To shuffle a 256-bit or 512-bit i16
8660 /// vector, form the analogous 128-bit 8-element Mask.
8661 static SDValue lowerV8I16GeneralSingleInputVectorShuffle(
8662 SDLoc DL, MVT VT, SDValue V, MutableArrayRef<int> Mask,
8663 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
8664 assert(VT.getScalarType() == MVT::i16 && "Bad input type!");
8665 MVT PSHUFDVT = MVT::getVectorVT(MVT::i32, VT.getVectorNumElements() / 2);
8667 assert(Mask.size() == 8 && "Shuffle mask length doen't match!");
8668 MutableArrayRef<int> LoMask = Mask.slice(0, 4);
8669 MutableArrayRef<int> HiMask = Mask.slice(4, 4);
8671 SmallVector<int, 4> LoInputs;
8672 std::copy_if(LoMask.begin(), LoMask.end(), std::back_inserter(LoInputs),
8673 [](int M) { return M >= 0; });
8674 std::sort(LoInputs.begin(), LoInputs.end());
8675 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()), LoInputs.end());
8676 SmallVector<int, 4> HiInputs;
8677 std::copy_if(HiMask.begin(), HiMask.end(), std::back_inserter(HiInputs),
8678 [](int M) { return M >= 0; });
8679 std::sort(HiInputs.begin(), HiInputs.end());
8680 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()), HiInputs.end());
8682 std::lower_bound(LoInputs.begin(), LoInputs.end(), 4) - LoInputs.begin();
8683 int NumHToL = LoInputs.size() - NumLToL;
8685 std::lower_bound(HiInputs.begin(), HiInputs.end(), 4) - HiInputs.begin();
8686 int NumHToH = HiInputs.size() - NumLToH;
8687 MutableArrayRef<int> LToLInputs(LoInputs.data(), NumLToL);
8688 MutableArrayRef<int> LToHInputs(HiInputs.data(), NumLToH);
8689 MutableArrayRef<int> HToLInputs(LoInputs.data() + NumLToL, NumHToL);
8690 MutableArrayRef<int> HToHInputs(HiInputs.data() + NumLToH, NumHToH);
8692 // Simplify the 1-into-3 and 3-into-1 cases with a single pshufd. For all
8693 // such inputs we can swap two of the dwords across the half mark and end up
8694 // with <=2 inputs to each half in each half. Once there, we can fall through
8695 // to the generic code below. For example:
8697 // Input: [a, b, c, d, e, f, g, h] -PSHUFD[0,2,1,3]-> [a, b, e, f, c, d, g, h]
8698 // Mask: [0, 1, 2, 7, 4, 5, 6, 3] -----------------> [0, 1, 4, 7, 2, 3, 6, 5]
8700 // However in some very rare cases we have a 1-into-3 or 3-into-1 on one half
8701 // and an existing 2-into-2 on the other half. In this case we may have to
8702 // pre-shuffle the 2-into-2 half to avoid turning it into a 3-into-1 or
8703 // 1-into-3 which could cause us to cycle endlessly fixing each side in turn.
8704 // Fortunately, we don't have to handle anything but a 2-into-2 pattern
8705 // because any other situation (including a 3-into-1 or 1-into-3 in the other
8706 // half than the one we target for fixing) will be fixed when we re-enter this
8707 // path. We will also combine away any sequence of PSHUFD instructions that
8708 // result into a single instruction. Here is an example of the tricky case:
8710 // Input: [a, b, c, d, e, f, g, h] -PSHUFD[0,2,1,3]-> [a, b, e, f, c, d, g, h]
8711 // Mask: [3, 7, 1, 0, 2, 7, 3, 5] -THIS-IS-BAD!!!!-> [5, 7, 1, 0, 4, 7, 5, 3]
8713 // This now has a 1-into-3 in the high half! Instead, we do two shuffles:
8715 // Input: [a, b, c, d, e, f, g, h] PSHUFHW[0,2,1,3]-> [a, b, c, d, e, g, f, h]
8716 // Mask: [3, 7, 1, 0, 2, 7, 3, 5] -----------------> [3, 7, 1, 0, 2, 7, 3, 6]
8718 // Input: [a, b, c, d, e, g, f, h] -PSHUFD[0,2,1,3]-> [a, b, e, g, c, d, f, h]
8719 // Mask: [3, 7, 1, 0, 2, 7, 3, 6] -----------------> [5, 7, 1, 0, 4, 7, 5, 6]
8721 // The result is fine to be handled by the generic logic.
8722 auto balanceSides = [&](ArrayRef<int> AToAInputs, ArrayRef<int> BToAInputs,
8723 ArrayRef<int> BToBInputs, ArrayRef<int> AToBInputs,
8724 int AOffset, int BOffset) {
8725 assert((AToAInputs.size() == 3 || AToAInputs.size() == 1) &&
8726 "Must call this with A having 3 or 1 inputs from the A half.");
8727 assert((BToAInputs.size() == 1 || BToAInputs.size() == 3) &&
8728 "Must call this with B having 1 or 3 inputs from the B half.");
8729 assert(AToAInputs.size() + BToAInputs.size() == 4 &&
8730 "Must call this with either 3:1 or 1:3 inputs (summing to 4).");
8732 bool ThreeAInputs = AToAInputs.size() == 3;
8734 // Compute the index of dword with only one word among the three inputs in
8735 // a half by taking the sum of the half with three inputs and subtracting
8736 // the sum of the actual three inputs. The difference is the remaining
8739 int &TripleDWord = ThreeAInputs ? ADWord : BDWord;
8740 int &OneInputDWord = ThreeAInputs ? BDWord : ADWord;
8741 int TripleInputOffset = ThreeAInputs ? AOffset : BOffset;
8742 ArrayRef<int> TripleInputs = ThreeAInputs ? AToAInputs : BToAInputs;
8743 int OneInput = ThreeAInputs ? BToAInputs[0] : AToAInputs[0];
8744 int TripleInputSum = 0 + 1 + 2 + 3 + (4 * TripleInputOffset);
8745 int TripleNonInputIdx =
8746 TripleInputSum - std::accumulate(TripleInputs.begin(), TripleInputs.end(), 0);
8747 TripleDWord = TripleNonInputIdx / 2;
8749 // We use xor with one to compute the adjacent DWord to whichever one the
8751 OneInputDWord = (OneInput / 2) ^ 1;
8753 // Check for one tricky case: We're fixing a 3<-1 or a 1<-3 shuffle for AToA
8754 // and BToA inputs. If there is also such a problem with the BToB and AToB
8755 // inputs, we don't try to fix it necessarily -- we'll recurse and see it in
8756 // the next pass. However, if we have a 2<-2 in the BToB and AToB inputs, it
8757 // is essential that we don't *create* a 3<-1 as then we might oscillate.
8758 if (BToBInputs.size() == 2 && AToBInputs.size() == 2) {
8759 // Compute how many inputs will be flipped by swapping these DWords. We
8761 // to balance this to ensure we don't form a 3-1 shuffle in the other
8763 int NumFlippedAToBInputs =
8764 std::count(AToBInputs.begin(), AToBInputs.end(), 2 * ADWord) +
8765 std::count(AToBInputs.begin(), AToBInputs.end(), 2 * ADWord + 1);
8766 int NumFlippedBToBInputs =
8767 std::count(BToBInputs.begin(), BToBInputs.end(), 2 * BDWord) +
8768 std::count(BToBInputs.begin(), BToBInputs.end(), 2 * BDWord + 1);
8769 if ((NumFlippedAToBInputs == 1 &&
8770 (NumFlippedBToBInputs == 0 || NumFlippedBToBInputs == 2)) ||
8771 (NumFlippedBToBInputs == 1 &&
8772 (NumFlippedAToBInputs == 0 || NumFlippedAToBInputs == 2))) {
8773 // We choose whether to fix the A half or B half based on whether that
8774 // half has zero flipped inputs. At zero, we may not be able to fix it
8775 // with that half. We also bias towards fixing the B half because that
8776 // will more commonly be the high half, and we have to bias one way.
8777 auto FixFlippedInputs = [&V, &DL, &Mask, &DAG](int PinnedIdx, int DWord,
8778 ArrayRef<int> Inputs) {
8779 int FixIdx = PinnedIdx ^ 1; // The adjacent slot to the pinned slot.
8780 bool IsFixIdxInput = std::find(Inputs.begin(), Inputs.end(),
8781 PinnedIdx ^ 1) != Inputs.end();
8782 // Determine whether the free index is in the flipped dword or the
8783 // unflipped dword based on where the pinned index is. We use this bit
8784 // in an xor to conditionally select the adjacent dword.
8785 int FixFreeIdx = 2 * (DWord ^ (PinnedIdx / 2 == DWord));
8786 bool IsFixFreeIdxInput = std::find(Inputs.begin(), Inputs.end(),
8787 FixFreeIdx) != Inputs.end();
8788 if (IsFixIdxInput == IsFixFreeIdxInput)
8790 IsFixFreeIdxInput = std::find(Inputs.begin(), Inputs.end(),
8791 FixFreeIdx) != Inputs.end();
8792 assert(IsFixIdxInput != IsFixFreeIdxInput &&
8793 "We need to be changing the number of flipped inputs!");
8794 int PSHUFHalfMask[] = {0, 1, 2, 3};
8795 std::swap(PSHUFHalfMask[FixFreeIdx % 4], PSHUFHalfMask[FixIdx % 4]);
8796 V = DAG.getNode(FixIdx < 4 ? X86ISD::PSHUFLW : X86ISD::PSHUFHW, DL,
8798 getV4X86ShuffleImm8ForMask(PSHUFHalfMask, DL, DAG));
8801 if (M != -1 && M == FixIdx)
8803 else if (M != -1 && M == FixFreeIdx)
8806 if (NumFlippedBToBInputs != 0) {
8808 BToAInputs.size() == 3 ? TripleNonInputIdx : OneInput;
8809 FixFlippedInputs(BPinnedIdx, BDWord, BToBInputs);
8811 assert(NumFlippedAToBInputs != 0 && "Impossible given predicates!");
8812 int APinnedIdx = ThreeAInputs ? TripleNonInputIdx : OneInput;
8813 FixFlippedInputs(APinnedIdx, ADWord, AToBInputs);
8818 int PSHUFDMask[] = {0, 1, 2, 3};
8819 PSHUFDMask[ADWord] = BDWord;
8820 PSHUFDMask[BDWord] = ADWord;
8823 DAG.getNode(X86ISD::PSHUFD, DL, PSHUFDVT, DAG.getBitcast(PSHUFDVT, V),
8824 getV4X86ShuffleImm8ForMask(PSHUFDMask, DL, DAG)));
8826 // Adjust the mask to match the new locations of A and B.
8828 if (M != -1 && M/2 == ADWord)
8829 M = 2 * BDWord + M % 2;
8830 else if (M != -1 && M/2 == BDWord)
8831 M = 2 * ADWord + M % 2;
8833 // Recurse back into this routine to re-compute state now that this isn't
8834 // a 3 and 1 problem.
8835 return lowerV8I16GeneralSingleInputVectorShuffle(DL, VT, V, Mask, Subtarget,
8838 if ((NumLToL == 3 && NumHToL == 1) || (NumLToL == 1 && NumHToL == 3))
8839 return balanceSides(LToLInputs, HToLInputs, HToHInputs, LToHInputs, 0, 4);
8840 else if ((NumHToH == 3 && NumLToH == 1) || (NumHToH == 1 && NumLToH == 3))
8841 return balanceSides(HToHInputs, LToHInputs, LToLInputs, HToLInputs, 4, 0);
8843 // At this point there are at most two inputs to the low and high halves from
8844 // each half. That means the inputs can always be grouped into dwords and
8845 // those dwords can then be moved to the correct half with a dword shuffle.
8846 // We use at most one low and one high word shuffle to collect these paired
8847 // inputs into dwords, and finally a dword shuffle to place them.
8848 int PSHUFLMask[4] = {-1, -1, -1, -1};
8849 int PSHUFHMask[4] = {-1, -1, -1, -1};
8850 int PSHUFDMask[4] = {-1, -1, -1, -1};
8852 // First fix the masks for all the inputs that are staying in their
8853 // original halves. This will then dictate the targets of the cross-half
8855 auto fixInPlaceInputs =
8856 [&PSHUFDMask](ArrayRef<int> InPlaceInputs, ArrayRef<int> IncomingInputs,
8857 MutableArrayRef<int> SourceHalfMask,
8858 MutableArrayRef<int> HalfMask, int HalfOffset) {
8859 if (InPlaceInputs.empty())
8861 if (InPlaceInputs.size() == 1) {
8862 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
8863 InPlaceInputs[0] - HalfOffset;
8864 PSHUFDMask[InPlaceInputs[0] / 2] = InPlaceInputs[0] / 2;
8867 if (IncomingInputs.empty()) {
8868 // Just fix all of the in place inputs.
8869 for (int Input : InPlaceInputs) {
8870 SourceHalfMask[Input - HalfOffset] = Input - HalfOffset;
8871 PSHUFDMask[Input / 2] = Input / 2;
8876 assert(InPlaceInputs.size() == 2 && "Cannot handle 3 or 4 inputs!");
8877 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
8878 InPlaceInputs[0] - HalfOffset;
8879 // Put the second input next to the first so that they are packed into
8880 // a dword. We find the adjacent index by toggling the low bit.
8881 int AdjIndex = InPlaceInputs[0] ^ 1;
8882 SourceHalfMask[AdjIndex - HalfOffset] = InPlaceInputs[1] - HalfOffset;
8883 std::replace(HalfMask.begin(), HalfMask.end(), InPlaceInputs[1], AdjIndex);
8884 PSHUFDMask[AdjIndex / 2] = AdjIndex / 2;
8886 fixInPlaceInputs(LToLInputs, HToLInputs, PSHUFLMask, LoMask, 0);
8887 fixInPlaceInputs(HToHInputs, LToHInputs, PSHUFHMask, HiMask, 4);
8889 // Now gather the cross-half inputs and place them into a free dword of
8890 // their target half.
8891 // FIXME: This operation could almost certainly be simplified dramatically to
8892 // look more like the 3-1 fixing operation.
8893 auto moveInputsToRightHalf = [&PSHUFDMask](
8894 MutableArrayRef<int> IncomingInputs, ArrayRef<int> ExistingInputs,
8895 MutableArrayRef<int> SourceHalfMask, MutableArrayRef<int> HalfMask,
8896 MutableArrayRef<int> FinalSourceHalfMask, int SourceOffset,
8898 auto isWordClobbered = [](ArrayRef<int> SourceHalfMask, int Word) {
8899 return SourceHalfMask[Word] != -1 && SourceHalfMask[Word] != Word;
8901 auto isDWordClobbered = [&isWordClobbered](ArrayRef<int> SourceHalfMask,
8903 int LowWord = Word & ~1;
8904 int HighWord = Word | 1;
8905 return isWordClobbered(SourceHalfMask, LowWord) ||
8906 isWordClobbered(SourceHalfMask, HighWord);
8909 if (IncomingInputs.empty())
8912 if (ExistingInputs.empty()) {
8913 // Map any dwords with inputs from them into the right half.
8914 for (int Input : IncomingInputs) {
8915 // If the source half mask maps over the inputs, turn those into
8916 // swaps and use the swapped lane.
8917 if (isWordClobbered(SourceHalfMask, Input - SourceOffset)) {
8918 if (SourceHalfMask[SourceHalfMask[Input - SourceOffset]] == -1) {
8919 SourceHalfMask[SourceHalfMask[Input - SourceOffset]] =
8920 Input - SourceOffset;
8921 // We have to swap the uses in our half mask in one sweep.
8922 for (int &M : HalfMask)
8923 if (M == SourceHalfMask[Input - SourceOffset] + SourceOffset)
8925 else if (M == Input)
8926 M = SourceHalfMask[Input - SourceOffset] + SourceOffset;
8928 assert(SourceHalfMask[SourceHalfMask[Input - SourceOffset]] ==
8929 Input - SourceOffset &&
8930 "Previous placement doesn't match!");
8932 // Note that this correctly re-maps both when we do a swap and when
8933 // we observe the other side of the swap above. We rely on that to
8934 // avoid swapping the members of the input list directly.
8935 Input = SourceHalfMask[Input - SourceOffset] + SourceOffset;
8938 // Map the input's dword into the correct half.
8939 if (PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] == -1)
8940 PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] = Input / 2;
8942 assert(PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] ==
8944 "Previous placement doesn't match!");
8947 // And just directly shift any other-half mask elements to be same-half
8948 // as we will have mirrored the dword containing the element into the
8949 // same position within that half.
8950 for (int &M : HalfMask)
8951 if (M >= SourceOffset && M < SourceOffset + 4) {
8952 M = M - SourceOffset + DestOffset;
8953 assert(M >= 0 && "This should never wrap below zero!");
8958 // Ensure we have the input in a viable dword of its current half. This
8959 // is particularly tricky because the original position may be clobbered
8960 // by inputs being moved and *staying* in that half.
8961 if (IncomingInputs.size() == 1) {
8962 if (isWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
8963 int InputFixed = std::find(std::begin(SourceHalfMask),
8964 std::end(SourceHalfMask), -1) -
8965 std::begin(SourceHalfMask) + SourceOffset;
8966 SourceHalfMask[InputFixed - SourceOffset] =
8967 IncomingInputs[0] - SourceOffset;
8968 std::replace(HalfMask.begin(), HalfMask.end(), IncomingInputs[0],
8970 IncomingInputs[0] = InputFixed;
8972 } else if (IncomingInputs.size() == 2) {
8973 if (IncomingInputs[0] / 2 != IncomingInputs[1] / 2 ||
8974 isDWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
8975 // We have two non-adjacent or clobbered inputs we need to extract from
8976 // the source half. To do this, we need to map them into some adjacent
8977 // dword slot in the source mask.
8978 int InputsFixed[2] = {IncomingInputs[0] - SourceOffset,
8979 IncomingInputs[1] - SourceOffset};
8981 // If there is a free slot in the source half mask adjacent to one of
8982 // the inputs, place the other input in it. We use (Index XOR 1) to
8983 // compute an adjacent index.
8984 if (!isWordClobbered(SourceHalfMask, InputsFixed[0]) &&
8985 SourceHalfMask[InputsFixed[0] ^ 1] == -1) {
8986 SourceHalfMask[InputsFixed[0]] = InputsFixed[0];
8987 SourceHalfMask[InputsFixed[0] ^ 1] = InputsFixed[1];
8988 InputsFixed[1] = InputsFixed[0] ^ 1;
8989 } else if (!isWordClobbered(SourceHalfMask, InputsFixed[1]) &&
8990 SourceHalfMask[InputsFixed[1] ^ 1] == -1) {
8991 SourceHalfMask[InputsFixed[1]] = InputsFixed[1];
8992 SourceHalfMask[InputsFixed[1] ^ 1] = InputsFixed[0];
8993 InputsFixed[0] = InputsFixed[1] ^ 1;
8994 } else if (SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1)] == -1 &&
8995 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1) + 1] == -1) {
8996 // The two inputs are in the same DWord but it is clobbered and the
8997 // adjacent DWord isn't used at all. Move both inputs to the free
8999 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1)] = InputsFixed[0];
9000 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1) + 1] = InputsFixed[1];
9001 InputsFixed[0] = 2 * ((InputsFixed[0] / 2) ^ 1);
9002 InputsFixed[1] = 2 * ((InputsFixed[0] / 2) ^ 1) + 1;
9004 // The only way we hit this point is if there is no clobbering
9005 // (because there are no off-half inputs to this half) and there is no
9006 // free slot adjacent to one of the inputs. In this case, we have to
9007 // swap an input with a non-input.
9008 for (int i = 0; i < 4; ++i)
9009 assert((SourceHalfMask[i] == -1 || SourceHalfMask[i] == i) &&
9010 "We can't handle any clobbers here!");
9011 assert(InputsFixed[1] != (InputsFixed[0] ^ 1) &&
9012 "Cannot have adjacent inputs here!");
9014 SourceHalfMask[InputsFixed[0] ^ 1] = InputsFixed[1];
9015 SourceHalfMask[InputsFixed[1]] = InputsFixed[0] ^ 1;
9017 // We also have to update the final source mask in this case because
9018 // it may need to undo the above swap.
9019 for (int &M : FinalSourceHalfMask)
9020 if (M == (InputsFixed[0] ^ 1) + SourceOffset)
9021 M = InputsFixed[1] + SourceOffset;
9022 else if (M == InputsFixed[1] + SourceOffset)
9023 M = (InputsFixed[0] ^ 1) + SourceOffset;
9025 InputsFixed[1] = InputsFixed[0] ^ 1;
9028 // Point everything at the fixed inputs.
9029 for (int &M : HalfMask)
9030 if (M == IncomingInputs[0])
9031 M = InputsFixed[0] + SourceOffset;
9032 else if (M == IncomingInputs[1])
9033 M = InputsFixed[1] + SourceOffset;
9035 IncomingInputs[0] = InputsFixed[0] + SourceOffset;
9036 IncomingInputs[1] = InputsFixed[1] + SourceOffset;
9039 llvm_unreachable("Unhandled input size!");
9042 // Now hoist the DWord down to the right half.
9043 int FreeDWord = (PSHUFDMask[DestOffset / 2] == -1 ? 0 : 1) + DestOffset / 2;
9044 assert(PSHUFDMask[FreeDWord] == -1 && "DWord not free");
9045 PSHUFDMask[FreeDWord] = IncomingInputs[0] / 2;
9046 for (int &M : HalfMask)
9047 for (int Input : IncomingInputs)
9049 M = FreeDWord * 2 + Input % 2;
9051 moveInputsToRightHalf(HToLInputs, LToLInputs, PSHUFHMask, LoMask, HiMask,
9052 /*SourceOffset*/ 4, /*DestOffset*/ 0);
9053 moveInputsToRightHalf(LToHInputs, HToHInputs, PSHUFLMask, HiMask, LoMask,
9054 /*SourceOffset*/ 0, /*DestOffset*/ 4);
9056 // Now enact all the shuffles we've computed to move the inputs into their
9058 if (!isNoopShuffleMask(PSHUFLMask))
9059 V = DAG.getNode(X86ISD::PSHUFLW, DL, VT, V,
9060 getV4X86ShuffleImm8ForMask(PSHUFLMask, DL, DAG));
9061 if (!isNoopShuffleMask(PSHUFHMask))
9062 V = DAG.getNode(X86ISD::PSHUFHW, DL, VT, V,
9063 getV4X86ShuffleImm8ForMask(PSHUFHMask, DL, DAG));
9064 if (!isNoopShuffleMask(PSHUFDMask))
9067 DAG.getNode(X86ISD::PSHUFD, DL, PSHUFDVT, DAG.getBitcast(PSHUFDVT, V),
9068 getV4X86ShuffleImm8ForMask(PSHUFDMask, DL, DAG)));
9070 // At this point, each half should contain all its inputs, and we can then
9071 // just shuffle them into their final position.
9072 assert(std::count_if(LoMask.begin(), LoMask.end(),
9073 [](int M) { return M >= 4; }) == 0 &&
9074 "Failed to lift all the high half inputs to the low mask!");
9075 assert(std::count_if(HiMask.begin(), HiMask.end(),
9076 [](int M) { return M >= 0 && M < 4; }) == 0 &&
9077 "Failed to lift all the low half inputs to the high mask!");
9079 // Do a half shuffle for the low mask.
9080 if (!isNoopShuffleMask(LoMask))
9081 V = DAG.getNode(X86ISD::PSHUFLW, DL, VT, V,
9082 getV4X86ShuffleImm8ForMask(LoMask, DL, DAG));
9084 // Do a half shuffle with the high mask after shifting its values down.
9085 for (int &M : HiMask)
9088 if (!isNoopShuffleMask(HiMask))
9089 V = DAG.getNode(X86ISD::PSHUFHW, DL, VT, V,
9090 getV4X86ShuffleImm8ForMask(HiMask, DL, DAG));
9095 /// \brief Helper to form a PSHUFB-based shuffle+blend.
9096 static SDValue lowerVectorShuffleAsPSHUFB(SDLoc DL, MVT VT, SDValue V1,
9097 SDValue V2, ArrayRef<int> Mask,
9098 SelectionDAG &DAG, bool &V1InUse,
9100 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
9106 int Size = Mask.size();
9107 int Scale = 16 / Size;
9108 for (int i = 0; i < 16; ++i) {
9109 if (Mask[i / Scale] == -1) {
9110 V1Mask[i] = V2Mask[i] = DAG.getUNDEF(MVT::i8);
9112 const int ZeroMask = 0x80;
9113 int V1Idx = Mask[i / Scale] < Size ? Mask[i / Scale] * Scale + i % Scale
9115 int V2Idx = Mask[i / Scale] < Size
9117 : (Mask[i / Scale] - Size) * Scale + i % Scale;
9118 if (Zeroable[i / Scale])
9119 V1Idx = V2Idx = ZeroMask;
9120 V1Mask[i] = DAG.getConstant(V1Idx, DL, MVT::i8);
9121 V2Mask[i] = DAG.getConstant(V2Idx, DL, MVT::i8);
9122 V1InUse |= (ZeroMask != V1Idx);
9123 V2InUse |= (ZeroMask != V2Idx);
9128 V1 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8,
9129 DAG.getBitcast(MVT::v16i8, V1),
9130 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V1Mask));
9132 V2 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8,
9133 DAG.getBitcast(MVT::v16i8, V2),
9134 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V2Mask));
9136 // If we need shuffled inputs from both, blend the two.
9138 if (V1InUse && V2InUse)
9139 V = DAG.getNode(ISD::OR, DL, MVT::v16i8, V1, V2);
9141 V = V1InUse ? V1 : V2;
9143 // Cast the result back to the correct type.
9144 return DAG.getBitcast(VT, V);
9147 /// \brief Generic lowering of 8-lane i16 shuffles.
9149 /// This handles both single-input shuffles and combined shuffle/blends with
9150 /// two inputs. The single input shuffles are immediately delegated to
9151 /// a dedicated lowering routine.
9153 /// The blends are lowered in one of three fundamental ways. If there are few
9154 /// enough inputs, it delegates to a basic UNPCK-based strategy. If the shuffle
9155 /// of the input is significantly cheaper when lowered as an interleaving of
9156 /// the two inputs, try to interleave them. Otherwise, blend the low and high
9157 /// halves of the inputs separately (making them have relatively few inputs)
9158 /// and then concatenate them.
9159 static SDValue lowerV8I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9160 const X86Subtarget *Subtarget,
9161 SelectionDAG &DAG) {
9163 assert(Op.getSimpleValueType() == MVT::v8i16 && "Bad shuffle type!");
9164 assert(V1.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
9165 assert(V2.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
9166 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9167 ArrayRef<int> OrigMask = SVOp->getMask();
9168 int MaskStorage[8] = {OrigMask[0], OrigMask[1], OrigMask[2], OrigMask[3],
9169 OrigMask[4], OrigMask[5], OrigMask[6], OrigMask[7]};
9170 MutableArrayRef<int> Mask(MaskStorage);
9172 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
9174 // Whenever we can lower this as a zext, that instruction is strictly faster
9175 // than any alternative.
9176 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(
9177 DL, MVT::v8i16, V1, V2, OrigMask, Subtarget, DAG))
9180 auto isV1 = [](int M) { return M >= 0 && M < 8; };
9182 auto isV2 = [](int M) { return M >= 8; };
9184 int NumV2Inputs = std::count_if(Mask.begin(), Mask.end(), isV2);
9186 if (NumV2Inputs == 0) {
9187 // Check for being able to broadcast a single element.
9188 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v8i16, V1,
9189 Mask, Subtarget, DAG))
9192 // Try to use shift instructions.
9194 lowerVectorShuffleAsShift(DL, MVT::v8i16, V1, V1, Mask, DAG))
9197 // Use dedicated unpack instructions for masks that match their pattern.
9199 lowerVectorShuffleWithUNPCK(DL, MVT::v8i16, Mask, V1, V2, DAG))
9202 // Try to use byte rotation instructions.
9203 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(DL, MVT::v8i16, V1, V1,
9204 Mask, Subtarget, DAG))
9207 return lowerV8I16GeneralSingleInputVectorShuffle(DL, MVT::v8i16, V1, Mask,
9211 assert(std::any_of(Mask.begin(), Mask.end(), isV1) &&
9212 "All single-input shuffles should be canonicalized to be V1-input "
9215 // Try to use shift instructions.
9217 lowerVectorShuffleAsShift(DL, MVT::v8i16, V1, V2, Mask, DAG))
9220 // See if we can use SSE4A Extraction / Insertion.
9221 if (Subtarget->hasSSE4A())
9222 if (SDValue V = lowerVectorShuffleWithSSE4A(DL, MVT::v8i16, V1, V2, Mask, DAG))
9225 // There are special ways we can lower some single-element blends.
9226 if (NumV2Inputs == 1)
9227 if (SDValue V = lowerVectorShuffleAsElementInsertion(DL, MVT::v8i16, V1, V2,
9228 Mask, Subtarget, DAG))
9231 // We have different paths for blend lowering, but they all must use the
9232 // *exact* same predicate.
9233 bool IsBlendSupported = Subtarget->hasSSE41();
9234 if (IsBlendSupported)
9235 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8i16, V1, V2, Mask,
9239 if (SDValue Masked =
9240 lowerVectorShuffleAsBitMask(DL, MVT::v8i16, V1, V2, Mask, DAG))
9243 // Use dedicated unpack instructions for masks that match their pattern.
9245 lowerVectorShuffleWithUNPCK(DL, MVT::v8i16, Mask, V1, V2, DAG))
9248 // Try to use byte rotation instructions.
9249 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
9250 DL, MVT::v8i16, V1, V2, Mask, Subtarget, DAG))
9253 if (SDValue BitBlend =
9254 lowerVectorShuffleAsBitBlend(DL, MVT::v8i16, V1, V2, Mask, DAG))
9257 if (SDValue Unpack = lowerVectorShuffleAsPermuteAndUnpack(DL, MVT::v8i16, V1,
9261 // If we can't directly blend but can use PSHUFB, that will be better as it
9262 // can both shuffle and set up the inefficient blend.
9263 if (!IsBlendSupported && Subtarget->hasSSSE3()) {
9264 bool V1InUse, V2InUse;
9265 return lowerVectorShuffleAsPSHUFB(DL, MVT::v8i16, V1, V2, Mask, DAG,
9269 // We can always bit-blend if we have to so the fallback strategy is to
9270 // decompose into single-input permutes and blends.
9271 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8i16, V1, V2,
9275 /// \brief Check whether a compaction lowering can be done by dropping even
9276 /// elements and compute how many times even elements must be dropped.
9278 /// This handles shuffles which take every Nth element where N is a power of
9279 /// two. Example shuffle masks:
9281 /// N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 0, 2, 4, 6, 8, 10, 12, 14
9282 /// N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30
9283 /// N = 2: 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12
9284 /// N = 2: 0, 4, 8, 12, 16, 20, 24, 28, 0, 4, 8, 12, 16, 20, 24, 28
9285 /// N = 3: 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8
9286 /// N = 3: 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24
9288 /// Any of these lanes can of course be undef.
9290 /// This routine only supports N <= 3.
9291 /// FIXME: Evaluate whether either AVX or AVX-512 have any opportunities here
9294 /// \returns N above, or the number of times even elements must be dropped if
9295 /// there is such a number. Otherwise returns zero.
9296 static int canLowerByDroppingEvenElements(ArrayRef<int> Mask) {
9297 // Figure out whether we're looping over two inputs or just one.
9298 bool IsSingleInput = isSingleInputShuffleMask(Mask);
9300 // The modulus for the shuffle vector entries is based on whether this is
9301 // a single input or not.
9302 int ShuffleModulus = Mask.size() * (IsSingleInput ? 1 : 2);
9303 assert(isPowerOf2_32((uint32_t)ShuffleModulus) &&
9304 "We should only be called with masks with a power-of-2 size!");
9306 uint64_t ModMask = (uint64_t)ShuffleModulus - 1;
9308 // We track whether the input is viable for all power-of-2 strides 2^1, 2^2,
9309 // and 2^3 simultaneously. This is because we may have ambiguity with
9310 // partially undef inputs.
9311 bool ViableForN[3] = {true, true, true};
9313 for (int i = 0, e = Mask.size(); i < e; ++i) {
9314 // Ignore undef lanes, we'll optimistically collapse them to the pattern we
9319 bool IsAnyViable = false;
9320 for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
9321 if (ViableForN[j]) {
9324 // The shuffle mask must be equal to (i * 2^N) % M.
9325 if ((uint64_t)Mask[i] == (((uint64_t)i << N) & ModMask))
9328 ViableForN[j] = false;
9330 // Early exit if we exhaust the possible powers of two.
9335 for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
9339 // Return 0 as there is no viable power of two.
9343 /// \brief Generic lowering of v16i8 shuffles.
9345 /// This is a hybrid strategy to lower v16i8 vectors. It first attempts to
9346 /// detect any complexity reducing interleaving. If that doesn't help, it uses
9347 /// UNPCK to spread the i8 elements across two i16-element vectors, and uses
9348 /// the existing lowering for v8i16 blends on each half, finally PACK-ing them
9350 static SDValue lowerV16I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9351 const X86Subtarget *Subtarget,
9352 SelectionDAG &DAG) {
9354 assert(Op.getSimpleValueType() == MVT::v16i8 && "Bad shuffle type!");
9355 assert(V1.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
9356 assert(V2.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
9357 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9358 ArrayRef<int> Mask = SVOp->getMask();
9359 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
9361 // Try to use shift instructions.
9363 lowerVectorShuffleAsShift(DL, MVT::v16i8, V1, V2, Mask, DAG))
9366 // Try to use byte rotation instructions.
9367 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
9368 DL, MVT::v16i8, V1, V2, Mask, Subtarget, DAG))
9371 // Try to use a zext lowering.
9372 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(
9373 DL, MVT::v16i8, V1, V2, Mask, Subtarget, DAG))
9376 // See if we can use SSE4A Extraction / Insertion.
9377 if (Subtarget->hasSSE4A())
9378 if (SDValue V = lowerVectorShuffleWithSSE4A(DL, MVT::v16i8, V1, V2, Mask, DAG))
9382 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 16; });
9384 // For single-input shuffles, there are some nicer lowering tricks we can use.
9385 if (NumV2Elements == 0) {
9386 // Check for being able to broadcast a single element.
9387 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v16i8, V1,
9388 Mask, Subtarget, DAG))
9391 // Check whether we can widen this to an i16 shuffle by duplicating bytes.
9392 // Notably, this handles splat and partial-splat shuffles more efficiently.
9393 // However, it only makes sense if the pre-duplication shuffle simplifies
9394 // things significantly. Currently, this means we need to be able to
9395 // express the pre-duplication shuffle as an i16 shuffle.
9397 // FIXME: We should check for other patterns which can be widened into an
9398 // i16 shuffle as well.
9399 auto canWidenViaDuplication = [](ArrayRef<int> Mask) {
9400 for (int i = 0; i < 16; i += 2)
9401 if (Mask[i] != -1 && Mask[i + 1] != -1 && Mask[i] != Mask[i + 1])
9406 auto tryToWidenViaDuplication = [&]() -> SDValue {
9407 if (!canWidenViaDuplication(Mask))
9409 SmallVector<int, 4> LoInputs;
9410 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(LoInputs),
9411 [](int M) { return M >= 0 && M < 8; });
9412 std::sort(LoInputs.begin(), LoInputs.end());
9413 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()),
9415 SmallVector<int, 4> HiInputs;
9416 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(HiInputs),
9417 [](int M) { return M >= 8; });
9418 std::sort(HiInputs.begin(), HiInputs.end());
9419 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()),
9422 bool TargetLo = LoInputs.size() >= HiInputs.size();
9423 ArrayRef<int> InPlaceInputs = TargetLo ? LoInputs : HiInputs;
9424 ArrayRef<int> MovingInputs = TargetLo ? HiInputs : LoInputs;
9426 int PreDupI16Shuffle[] = {-1, -1, -1, -1, -1, -1, -1, -1};
9427 SmallDenseMap<int, int, 8> LaneMap;
9428 for (int I : InPlaceInputs) {
9429 PreDupI16Shuffle[I/2] = I/2;
9432 int j = TargetLo ? 0 : 4, je = j + 4;
9433 for (int i = 0, ie = MovingInputs.size(); i < ie; ++i) {
9434 // Check if j is already a shuffle of this input. This happens when
9435 // there are two adjacent bytes after we move the low one.
9436 if (PreDupI16Shuffle[j] != MovingInputs[i] / 2) {
9437 // If we haven't yet mapped the input, search for a slot into which
9439 while (j < je && PreDupI16Shuffle[j] != -1)
9443 // We can't place the inputs into a single half with a simple i16 shuffle, so bail.
9446 // Map this input with the i16 shuffle.
9447 PreDupI16Shuffle[j] = MovingInputs[i] / 2;
9450 // Update the lane map based on the mapping we ended up with.
9451 LaneMap[MovingInputs[i]] = 2 * j + MovingInputs[i] % 2;
9453 V1 = DAG.getBitcast(
9455 DAG.getVectorShuffle(MVT::v8i16, DL, DAG.getBitcast(MVT::v8i16, V1),
9456 DAG.getUNDEF(MVT::v8i16), PreDupI16Shuffle));
9458 // Unpack the bytes to form the i16s that will be shuffled into place.
9459 V1 = DAG.getNode(TargetLo ? X86ISD::UNPCKL : X86ISD::UNPCKH, DL,
9460 MVT::v16i8, V1, V1);
9462 int PostDupI16Shuffle[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9463 for (int i = 0; i < 16; ++i)
9464 if (Mask[i] != -1) {
9465 int MappedMask = LaneMap[Mask[i]] - (TargetLo ? 0 : 8);
9466 assert(MappedMask < 8 && "Invalid v8 shuffle mask!");
9467 if (PostDupI16Shuffle[i / 2] == -1)
9468 PostDupI16Shuffle[i / 2] = MappedMask;
9470 assert(PostDupI16Shuffle[i / 2] == MappedMask &&
9471 "Conflicting entrties in the original shuffle!");
9473 return DAG.getBitcast(
9475 DAG.getVectorShuffle(MVT::v8i16, DL, DAG.getBitcast(MVT::v8i16, V1),
9476 DAG.getUNDEF(MVT::v8i16), PostDupI16Shuffle));
9478 if (SDValue V = tryToWidenViaDuplication())
9482 if (SDValue Masked =
9483 lowerVectorShuffleAsBitMask(DL, MVT::v16i8, V1, V2, Mask, DAG))
9486 // Use dedicated unpack instructions for masks that match their pattern.
9488 lowerVectorShuffleWithUNPCK(DL, MVT::v16i8, Mask, V1, V2, DAG))
9491 // Check for SSSE3 which lets us lower all v16i8 shuffles much more directly
9492 // with PSHUFB. It is important to do this before we attempt to generate any
9493 // blends but after all of the single-input lowerings. If the single input
9494 // lowerings can find an instruction sequence that is faster than a PSHUFB, we
9495 // want to preserve that and we can DAG combine any longer sequences into
9496 // a PSHUFB in the end. But once we start blending from multiple inputs,
9497 // the complexity of DAG combining bad patterns back into PSHUFB is too high,
9498 // and there are *very* few patterns that would actually be faster than the
9499 // PSHUFB approach because of its ability to zero lanes.
9501 // FIXME: The only exceptions to the above are blends which are exact
9502 // interleavings with direct instructions supporting them. We currently don't
9503 // handle those well here.
9504 if (Subtarget->hasSSSE3()) {
9505 bool V1InUse = false;
9506 bool V2InUse = false;
9508 SDValue PSHUFB = lowerVectorShuffleAsPSHUFB(DL, MVT::v16i8, V1, V2, Mask,
9509 DAG, V1InUse, V2InUse);
9511 // If both V1 and V2 are in use and we can use a direct blend or an unpack,
9512 // do so. This avoids using them to handle blends-with-zero which is
9513 // important as a single pshufb is significantly faster for that.
9514 if (V1InUse && V2InUse) {
9515 if (Subtarget->hasSSE41())
9516 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v16i8, V1, V2,
9517 Mask, Subtarget, DAG))
9520 // We can use an unpack to do the blending rather than an or in some
9521 // cases. Even though the or may be (very minorly) more efficient, we
9522 // preference this lowering because there are common cases where part of
9523 // the complexity of the shuffles goes away when we do the final blend as
9525 // FIXME: It might be worth trying to detect if the unpack-feeding
9526 // shuffles will both be pshufb, in which case we shouldn't bother with
9528 if (SDValue Unpack = lowerVectorShuffleAsPermuteAndUnpack(
9529 DL, MVT::v16i8, V1, V2, Mask, DAG))
9536 // There are special ways we can lower some single-element blends.
9537 if (NumV2Elements == 1)
9538 if (SDValue V = lowerVectorShuffleAsElementInsertion(DL, MVT::v16i8, V1, V2,
9539 Mask, Subtarget, DAG))
9542 if (SDValue BitBlend =
9543 lowerVectorShuffleAsBitBlend(DL, MVT::v16i8, V1, V2, Mask, DAG))
9546 // Check whether a compaction lowering can be done. This handles shuffles
9547 // which take every Nth element for some even N. See the helper function for
9550 // We special case these as they can be particularly efficiently handled with
9551 // the PACKUSB instruction on x86 and they show up in common patterns of
9552 // rearranging bytes to truncate wide elements.
9553 if (int NumEvenDrops = canLowerByDroppingEvenElements(Mask)) {
9554 // NumEvenDrops is the power of two stride of the elements. Another way of
9555 // thinking about it is that we need to drop the even elements this many
9556 // times to get the original input.
9557 bool IsSingleInput = isSingleInputShuffleMask(Mask);
9559 // First we need to zero all the dropped bytes.
9560 assert(NumEvenDrops <= 3 &&
9561 "No support for dropping even elements more than 3 times.");
9562 // We use the mask type to pick which bytes are preserved based on how many
9563 // elements are dropped.
9564 MVT MaskVTs[] = { MVT::v8i16, MVT::v4i32, MVT::v2i64 };
9565 SDValue ByteClearMask = DAG.getBitcast(
9566 MVT::v16i8, DAG.getConstant(0xFF, DL, MaskVTs[NumEvenDrops - 1]));
9567 V1 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V1, ByteClearMask);
9569 V2 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V2, ByteClearMask);
9571 // Now pack things back together.
9572 V1 = DAG.getBitcast(MVT::v8i16, V1);
9573 V2 = IsSingleInput ? V1 : DAG.getBitcast(MVT::v8i16, V2);
9574 SDValue Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, V1, V2);
9575 for (int i = 1; i < NumEvenDrops; ++i) {
9576 Result = DAG.getBitcast(MVT::v8i16, Result);
9577 Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, Result, Result);
9583 // Handle multi-input cases by blending single-input shuffles.
9584 if (NumV2Elements > 0)
9585 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v16i8, V1, V2,
9588 // The fallback path for single-input shuffles widens this into two v8i16
9589 // vectors with unpacks, shuffles those, and then pulls them back together
9593 int LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9594 int HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9595 for (int i = 0; i < 16; ++i)
9597 (i < 8 ? LoBlendMask[i] : HiBlendMask[i % 8]) = Mask[i];
9599 SDValue Zero = getZeroVector(MVT::v8i16, Subtarget, DAG, DL);
9601 SDValue VLoHalf, VHiHalf;
9602 // Check if any of the odd lanes in the v16i8 are used. If not, we can mask
9603 // them out and avoid using UNPCK{L,H} to extract the elements of V as
9605 if (std::none_of(std::begin(LoBlendMask), std::end(LoBlendMask),
9606 [](int M) { return M >= 0 && M % 2 == 1; }) &&
9607 std::none_of(std::begin(HiBlendMask), std::end(HiBlendMask),
9608 [](int M) { return M >= 0 && M % 2 == 1; })) {
9609 // Use a mask to drop the high bytes.
9610 VLoHalf = DAG.getBitcast(MVT::v8i16, V);
9611 VLoHalf = DAG.getNode(ISD::AND, DL, MVT::v8i16, VLoHalf,
9612 DAG.getConstant(0x00FF, DL, MVT::v8i16));
9614 // This will be a single vector shuffle instead of a blend so nuke VHiHalf.
9615 VHiHalf = DAG.getUNDEF(MVT::v8i16);
9617 // Squash the masks to point directly into VLoHalf.
9618 for (int &M : LoBlendMask)
9621 for (int &M : HiBlendMask)
9625 // Otherwise just unpack the low half of V into VLoHalf and the high half into
9626 // VHiHalf so that we can blend them as i16s.
9627 VLoHalf = DAG.getBitcast(
9628 MVT::v8i16, DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i8, V, Zero));
9629 VHiHalf = DAG.getBitcast(
9630 MVT::v8i16, DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i8, V, Zero));
9633 SDValue LoV = DAG.getVectorShuffle(MVT::v8i16, DL, VLoHalf, VHiHalf, LoBlendMask);
9634 SDValue HiV = DAG.getVectorShuffle(MVT::v8i16, DL, VLoHalf, VHiHalf, HiBlendMask);
9636 return DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, LoV, HiV);
9639 /// \brief Dispatching routine to lower various 128-bit x86 vector shuffles.
9641 /// This routine breaks down the specific type of 128-bit shuffle and
9642 /// dispatches to the lowering routines accordingly.
9643 static SDValue lower128BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9644 MVT VT, const X86Subtarget *Subtarget,
9645 SelectionDAG &DAG) {
9646 switch (VT.SimpleTy) {
9648 return lowerV2I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9650 return lowerV2F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9652 return lowerV4I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9654 return lowerV4F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9656 return lowerV8I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
9658 return lowerV16I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
9661 llvm_unreachable("Unimplemented!");
9665 /// \brief Helper function to test whether a shuffle mask could be
9666 /// simplified by widening the elements being shuffled.
9668 /// Appends the mask for wider elements in WidenedMask if valid. Otherwise
9669 /// leaves it in an unspecified state.
9671 /// NOTE: This must handle normal vector shuffle masks and *target* vector
9672 /// shuffle masks. The latter have the special property of a '-2' representing
9673 /// a zero-ed lane of a vector.
9674 static bool canWidenShuffleElements(ArrayRef<int> Mask,
9675 SmallVectorImpl<int> &WidenedMask) {
9676 for (int i = 0, Size = Mask.size(); i < Size; i += 2) {
9677 // If both elements are undef, its trivial.
9678 if (Mask[i] == SM_SentinelUndef && Mask[i + 1] == SM_SentinelUndef) {
9679 WidenedMask.push_back(SM_SentinelUndef);
9683 // Check for an undef mask and a mask value properly aligned to fit with
9684 // a pair of values. If we find such a case, use the non-undef mask's value.
9685 if (Mask[i] == SM_SentinelUndef && Mask[i + 1] >= 0 && Mask[i + 1] % 2 == 1) {
9686 WidenedMask.push_back(Mask[i + 1] / 2);
9689 if (Mask[i + 1] == SM_SentinelUndef && Mask[i] >= 0 && Mask[i] % 2 == 0) {
9690 WidenedMask.push_back(Mask[i] / 2);
9694 // When zeroing, we need to spread the zeroing across both lanes to widen.
9695 if (Mask[i] == SM_SentinelZero || Mask[i + 1] == SM_SentinelZero) {
9696 if ((Mask[i] == SM_SentinelZero || Mask[i] == SM_SentinelUndef) &&
9697 (Mask[i + 1] == SM_SentinelZero || Mask[i + 1] == SM_SentinelUndef)) {
9698 WidenedMask.push_back(SM_SentinelZero);
9704 // Finally check if the two mask values are adjacent and aligned with
9706 if (Mask[i] != SM_SentinelUndef && Mask[i] % 2 == 0 && Mask[i] + 1 == Mask[i + 1]) {
9707 WidenedMask.push_back(Mask[i] / 2);
9711 // Otherwise we can't safely widen the elements used in this shuffle.
9714 assert(WidenedMask.size() == Mask.size() / 2 &&
9715 "Incorrect size of mask after widening the elements!");
9720 /// \brief Generic routine to split vector shuffle into half-sized shuffles.
9722 /// This routine just extracts two subvectors, shuffles them independently, and
9723 /// then concatenates them back together. This should work effectively with all
9724 /// AVX vector shuffle types.
9725 static SDValue splitAndLowerVectorShuffle(SDLoc DL, MVT VT, SDValue V1,
9726 SDValue V2, ArrayRef<int> Mask,
9727 SelectionDAG &DAG) {
9728 assert(VT.getSizeInBits() >= 256 &&
9729 "Only for 256-bit or wider vector shuffles!");
9730 assert(V1.getSimpleValueType() == VT && "Bad operand type!");
9731 assert(V2.getSimpleValueType() == VT && "Bad operand type!");
9733 ArrayRef<int> LoMask = Mask.slice(0, Mask.size() / 2);
9734 ArrayRef<int> HiMask = Mask.slice(Mask.size() / 2);
9736 int NumElements = VT.getVectorNumElements();
9737 int SplitNumElements = NumElements / 2;
9738 MVT ScalarVT = VT.getScalarType();
9739 MVT SplitVT = MVT::getVectorVT(ScalarVT, NumElements / 2);
9741 // Rather than splitting build-vectors, just build two narrower build
9742 // vectors. This helps shuffling with splats and zeros.
9743 auto SplitVector = [&](SDValue V) {
9744 while (V.getOpcode() == ISD::BITCAST)
9745 V = V->getOperand(0);
9747 MVT OrigVT = V.getSimpleValueType();
9748 int OrigNumElements = OrigVT.getVectorNumElements();
9749 int OrigSplitNumElements = OrigNumElements / 2;
9750 MVT OrigScalarVT = OrigVT.getScalarType();
9751 MVT OrigSplitVT = MVT::getVectorVT(OrigScalarVT, OrigNumElements / 2);
9755 auto *BV = dyn_cast<BuildVectorSDNode>(V);
9757 LoV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, OrigSplitVT, V,
9758 DAG.getIntPtrConstant(0, DL));
9759 HiV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, OrigSplitVT, V,
9760 DAG.getIntPtrConstant(OrigSplitNumElements, DL));
9763 SmallVector<SDValue, 16> LoOps, HiOps;
9764 for (int i = 0; i < OrigSplitNumElements; ++i) {
9765 LoOps.push_back(BV->getOperand(i));
9766 HiOps.push_back(BV->getOperand(i + OrigSplitNumElements));
9768 LoV = DAG.getNode(ISD::BUILD_VECTOR, DL, OrigSplitVT, LoOps);
9769 HiV = DAG.getNode(ISD::BUILD_VECTOR, DL, OrigSplitVT, HiOps);
9771 return std::make_pair(DAG.getBitcast(SplitVT, LoV),
9772 DAG.getBitcast(SplitVT, HiV));
9775 SDValue LoV1, HiV1, LoV2, HiV2;
9776 std::tie(LoV1, HiV1) = SplitVector(V1);
9777 std::tie(LoV2, HiV2) = SplitVector(V2);
9779 // Now create two 4-way blends of these half-width vectors.
9780 auto HalfBlend = [&](ArrayRef<int> HalfMask) {
9781 bool UseLoV1 = false, UseHiV1 = false, UseLoV2 = false, UseHiV2 = false;
9782 SmallVector<int, 32> V1BlendMask, V2BlendMask, BlendMask;
9783 for (int i = 0; i < SplitNumElements; ++i) {
9784 int M = HalfMask[i];
9785 if (M >= NumElements) {
9786 if (M >= NumElements + SplitNumElements)
9790 V2BlendMask.push_back(M - NumElements);
9791 V1BlendMask.push_back(-1);
9792 BlendMask.push_back(SplitNumElements + i);
9793 } else if (M >= 0) {
9794 if (M >= SplitNumElements)
9798 V2BlendMask.push_back(-1);
9799 V1BlendMask.push_back(M);
9800 BlendMask.push_back(i);
9802 V2BlendMask.push_back(-1);
9803 V1BlendMask.push_back(-1);
9804 BlendMask.push_back(-1);
9808 // Because the lowering happens after all combining takes place, we need to
9809 // manually combine these blend masks as much as possible so that we create
9810 // a minimal number of high-level vector shuffle nodes.
9812 // First try just blending the halves of V1 or V2.
9813 if (!UseLoV1 && !UseHiV1 && !UseLoV2 && !UseHiV2)
9814 return DAG.getUNDEF(SplitVT);
9815 if (!UseLoV2 && !UseHiV2)
9816 return DAG.getVectorShuffle(SplitVT, DL, LoV1, HiV1, V1BlendMask);
9817 if (!UseLoV1 && !UseHiV1)
9818 return DAG.getVectorShuffle(SplitVT, DL, LoV2, HiV2, V2BlendMask);
9820 SDValue V1Blend, V2Blend;
9821 if (UseLoV1 && UseHiV1) {
9823 DAG.getVectorShuffle(SplitVT, DL, LoV1, HiV1, V1BlendMask);
9825 // We only use half of V1 so map the usage down into the final blend mask.
9826 V1Blend = UseLoV1 ? LoV1 : HiV1;
9827 for (int i = 0; i < SplitNumElements; ++i)
9828 if (BlendMask[i] >= 0 && BlendMask[i] < SplitNumElements)
9829 BlendMask[i] = V1BlendMask[i] - (UseLoV1 ? 0 : SplitNumElements);
9831 if (UseLoV2 && UseHiV2) {
9833 DAG.getVectorShuffle(SplitVT, DL, LoV2, HiV2, V2BlendMask);
9835 // We only use half of V2 so map the usage down into the final blend mask.
9836 V2Blend = UseLoV2 ? LoV2 : HiV2;
9837 for (int i = 0; i < SplitNumElements; ++i)
9838 if (BlendMask[i] >= SplitNumElements)
9839 BlendMask[i] = V2BlendMask[i] + (UseLoV2 ? SplitNumElements : 0);
9841 return DAG.getVectorShuffle(SplitVT, DL, V1Blend, V2Blend, BlendMask);
9843 SDValue Lo = HalfBlend(LoMask);
9844 SDValue Hi = HalfBlend(HiMask);
9845 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Lo, Hi);
9848 /// \brief Either split a vector in halves or decompose the shuffles and the
9851 /// This is provided as a good fallback for many lowerings of non-single-input
9852 /// shuffles with more than one 128-bit lane. In those cases, we want to select
9853 /// between splitting the shuffle into 128-bit components and stitching those
9854 /// back together vs. extracting the single-input shuffles and blending those
9856 static SDValue lowerVectorShuffleAsSplitOrBlend(SDLoc DL, MVT VT, SDValue V1,
9857 SDValue V2, ArrayRef<int> Mask,
9858 SelectionDAG &DAG) {
9859 assert(!isSingleInputShuffleMask(Mask) && "This routine must not be used to "
9860 "lower single-input shuffles as it "
9861 "could then recurse on itself.");
9862 int Size = Mask.size();
9864 // If this can be modeled as a broadcast of two elements followed by a blend,
9865 // prefer that lowering. This is especially important because broadcasts can
9866 // often fold with memory operands.
9867 auto DoBothBroadcast = [&] {
9868 int V1BroadcastIdx = -1, V2BroadcastIdx = -1;
9871 if (V2BroadcastIdx == -1)
9872 V2BroadcastIdx = M - Size;
9873 else if (M - Size != V2BroadcastIdx)
9875 } else if (M >= 0) {
9876 if (V1BroadcastIdx == -1)
9878 else if (M != V1BroadcastIdx)
9883 if (DoBothBroadcast())
9884 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask,
9887 // If the inputs all stem from a single 128-bit lane of each input, then we
9888 // split them rather than blending because the split will decompose to
9889 // unusually few instructions.
9890 int LaneCount = VT.getSizeInBits() / 128;
9891 int LaneSize = Size / LaneCount;
9892 SmallBitVector LaneInputs[2];
9893 LaneInputs[0].resize(LaneCount, false);
9894 LaneInputs[1].resize(LaneCount, false);
9895 for (int i = 0; i < Size; ++i)
9897 LaneInputs[Mask[i] / Size][(Mask[i] % Size) / LaneSize] = true;
9898 if (LaneInputs[0].count() <= 1 && LaneInputs[1].count() <= 1)
9899 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
9901 // Otherwise, just fall back to decomposed shuffles and a blend. This requires
9902 // that the decomposed single-input shuffles don't end up here.
9903 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask, DAG);
9906 /// \brief Lower a vector shuffle crossing multiple 128-bit lanes as
9907 /// a permutation and blend of those lanes.
9909 /// This essentially blends the out-of-lane inputs to each lane into the lane
9910 /// from a permuted copy of the vector. This lowering strategy results in four
9911 /// instructions in the worst case for a single-input cross lane shuffle which
9912 /// is lower than any other fully general cross-lane shuffle strategy I'm aware
9913 /// of. Special cases for each particular shuffle pattern should be handled
9914 /// prior to trying this lowering.
9915 static SDValue lowerVectorShuffleAsLanePermuteAndBlend(SDLoc DL, MVT VT,
9916 SDValue V1, SDValue V2,
9918 SelectionDAG &DAG) {
9919 // FIXME: This should probably be generalized for 512-bit vectors as well.
9920 assert(VT.getSizeInBits() == 256 && "Only for 256-bit vector shuffles!");
9921 int LaneSize = Mask.size() / 2;
9923 // If there are only inputs from one 128-bit lane, splitting will in fact be
9924 // less expensive. The flags track whether the given lane contains an element
9925 // that crosses to another lane.
9926 bool LaneCrossing[2] = {false, false};
9927 for (int i = 0, Size = Mask.size(); i < Size; ++i)
9928 if (Mask[i] >= 0 && (Mask[i] % Size) / LaneSize != i / LaneSize)
9929 LaneCrossing[(Mask[i] % Size) / LaneSize] = true;
9930 if (!LaneCrossing[0] || !LaneCrossing[1])
9931 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
9933 if (isSingleInputShuffleMask(Mask)) {
9934 SmallVector<int, 32> FlippedBlendMask;
9935 for (int i = 0, Size = Mask.size(); i < Size; ++i)
9936 FlippedBlendMask.push_back(
9937 Mask[i] < 0 ? -1 : (((Mask[i] % Size) / LaneSize == i / LaneSize)
9939 : Mask[i] % LaneSize +
9940 (i / LaneSize) * LaneSize + Size));
9942 // Flip the vector, and blend the results which should now be in-lane. The
9943 // VPERM2X128 mask uses the low 2 bits for the low source and bits 4 and
9944 // 5 for the high source. The value 3 selects the high half of source 2 and
9945 // the value 2 selects the low half of source 2. We only use source 2 to
9946 // allow folding it into a memory operand.
9947 unsigned PERMMask = 3 | 2 << 4;
9948 SDValue Flipped = DAG.getNode(X86ISD::VPERM2X128, DL, VT, DAG.getUNDEF(VT),
9949 V1, DAG.getConstant(PERMMask, DL, MVT::i8));
9950 return DAG.getVectorShuffle(VT, DL, V1, Flipped, FlippedBlendMask);
9953 // This now reduces to two single-input shuffles of V1 and V2 which at worst
9954 // will be handled by the above logic and a blend of the results, much like
9955 // other patterns in AVX.
9956 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask, DAG);
9959 /// \brief Handle lowering 2-lane 128-bit shuffles.
9960 static SDValue lowerV2X128VectorShuffle(SDLoc DL, MVT VT, SDValue V1,
9961 SDValue V2, ArrayRef<int> Mask,
9962 const X86Subtarget *Subtarget,
9963 SelectionDAG &DAG) {
9964 // TODO: If minimizing size and one of the inputs is a zero vector and the
9965 // the zero vector has only one use, we could use a VPERM2X128 to save the
9966 // instruction bytes needed to explicitly generate the zero vector.
9968 // Blends are faster and handle all the non-lane-crossing cases.
9969 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, VT, V1, V2, Mask,
9973 bool IsV1Zero = ISD::isBuildVectorAllZeros(V1.getNode());
9974 bool IsV2Zero = ISD::isBuildVectorAllZeros(V2.getNode());
9976 // If either input operand is a zero vector, use VPERM2X128 because its mask
9977 // allows us to replace the zero input with an implicit zero.
9978 if (!IsV1Zero && !IsV2Zero) {
9979 // Check for patterns which can be matched with a single insert of a 128-bit
9981 bool OnlyUsesV1 = isShuffleEquivalent(V1, V2, Mask, {0, 1, 0, 1});
9982 if (OnlyUsesV1 || isShuffleEquivalent(V1, V2, Mask, {0, 1, 4, 5})) {
9983 MVT SubVT = MVT::getVectorVT(VT.getVectorElementType(),
9984 VT.getVectorNumElements() / 2);
9985 SDValue LoV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT, V1,
9986 DAG.getIntPtrConstant(0, DL));
9987 SDValue HiV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT,
9988 OnlyUsesV1 ? V1 : V2,
9989 DAG.getIntPtrConstant(0, DL));
9990 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LoV, HiV);
9994 // Otherwise form a 128-bit permutation. After accounting for undefs,
9995 // convert the 64-bit shuffle mask selection values into 128-bit
9996 // selection bits by dividing the indexes by 2 and shifting into positions
9997 // defined by a vperm2*128 instruction's immediate control byte.
9999 // The immediate permute control byte looks like this:
10000 // [1:0] - select 128 bits from sources for low half of destination
10002 // [3] - zero low half of destination
10003 // [5:4] - select 128 bits from sources for high half of destination
10005 // [7] - zero high half of destination
10007 int MaskLO = Mask[0];
10008 if (MaskLO == SM_SentinelUndef)
10009 MaskLO = Mask[1] == SM_SentinelUndef ? 0 : Mask[1];
10011 int MaskHI = Mask[2];
10012 if (MaskHI == SM_SentinelUndef)
10013 MaskHI = Mask[3] == SM_SentinelUndef ? 0 : Mask[3];
10015 unsigned PermMask = MaskLO / 2 | (MaskHI / 2) << 4;
10017 // If either input is a zero vector, replace it with an undef input.
10018 // Shuffle mask values < 4 are selecting elements of V1.
10019 // Shuffle mask values >= 4 are selecting elements of V2.
10020 // Adjust each half of the permute mask by clearing the half that was
10021 // selecting the zero vector and setting the zero mask bit.
10023 V1 = DAG.getUNDEF(VT);
10025 PermMask = (PermMask & 0xf0) | 0x08;
10027 PermMask = (PermMask & 0x0f) | 0x80;
10030 V2 = DAG.getUNDEF(VT);
10032 PermMask = (PermMask & 0xf0) | 0x08;
10034 PermMask = (PermMask & 0x0f) | 0x80;
10037 return DAG.getNode(X86ISD::VPERM2X128, DL, VT, V1, V2,
10038 DAG.getConstant(PermMask, DL, MVT::i8));
10041 /// \brief Lower a vector shuffle by first fixing the 128-bit lanes and then
10042 /// shuffling each lane.
10044 /// This will only succeed when the result of fixing the 128-bit lanes results
10045 /// in a single-input non-lane-crossing shuffle with a repeating shuffle mask in
10046 /// each 128-bit lanes. This handles many cases where we can quickly blend away
10047 /// the lane crosses early and then use simpler shuffles within each lane.
10049 /// FIXME: It might be worthwhile at some point to support this without
10050 /// requiring the 128-bit lane-relative shuffles to be repeating, but currently
10051 /// in x86 only floating point has interesting non-repeating shuffles, and even
10052 /// those are still *marginally* more expensive.
10053 static SDValue lowerVectorShuffleByMerging128BitLanes(
10054 SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
10055 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
10056 assert(!isSingleInputShuffleMask(Mask) &&
10057 "This is only useful with multiple inputs.");
10059 int Size = Mask.size();
10060 int LaneSize = 128 / VT.getScalarSizeInBits();
10061 int NumLanes = Size / LaneSize;
10062 assert(NumLanes > 1 && "Only handles 256-bit and wider shuffles.");
10064 // See if we can build a hypothetical 128-bit lane-fixing shuffle mask. Also
10065 // check whether the in-128-bit lane shuffles share a repeating pattern.
10066 SmallVector<int, 4> Lanes;
10067 Lanes.resize(NumLanes, -1);
10068 SmallVector<int, 4> InLaneMask;
10069 InLaneMask.resize(LaneSize, -1);
10070 for (int i = 0; i < Size; ++i) {
10074 int j = i / LaneSize;
10076 if (Lanes[j] < 0) {
10077 // First entry we've seen for this lane.
10078 Lanes[j] = Mask[i] / LaneSize;
10079 } else if (Lanes[j] != Mask[i] / LaneSize) {
10080 // This doesn't match the lane selected previously!
10084 // Check that within each lane we have a consistent shuffle mask.
10085 int k = i % LaneSize;
10086 if (InLaneMask[k] < 0) {
10087 InLaneMask[k] = Mask[i] % LaneSize;
10088 } else if (InLaneMask[k] != Mask[i] % LaneSize) {
10089 // This doesn't fit a repeating in-lane mask.
10094 // First shuffle the lanes into place.
10095 MVT LaneVT = MVT::getVectorVT(VT.isFloatingPoint() ? MVT::f64 : MVT::i64,
10096 VT.getSizeInBits() / 64);
10097 SmallVector<int, 8> LaneMask;
10098 LaneMask.resize(NumLanes * 2, -1);
10099 for (int i = 0; i < NumLanes; ++i)
10100 if (Lanes[i] >= 0) {
10101 LaneMask[2 * i + 0] = 2*Lanes[i] + 0;
10102 LaneMask[2 * i + 1] = 2*Lanes[i] + 1;
10105 V1 = DAG.getBitcast(LaneVT, V1);
10106 V2 = DAG.getBitcast(LaneVT, V2);
10107 SDValue LaneShuffle = DAG.getVectorShuffle(LaneVT, DL, V1, V2, LaneMask);
10109 // Cast it back to the type we actually want.
10110 LaneShuffle = DAG.getBitcast(VT, LaneShuffle);
10112 // Now do a simple shuffle that isn't lane crossing.
10113 SmallVector<int, 8> NewMask;
10114 NewMask.resize(Size, -1);
10115 for (int i = 0; i < Size; ++i)
10117 NewMask[i] = (i / LaneSize) * LaneSize + Mask[i] % LaneSize;
10118 assert(!is128BitLaneCrossingShuffleMask(VT, NewMask) &&
10119 "Must not introduce lane crosses at this point!");
10121 return DAG.getVectorShuffle(VT, DL, LaneShuffle, DAG.getUNDEF(VT), NewMask);
10124 /// \brief Test whether the specified input (0 or 1) is in-place blended by the
10127 /// This returns true if the elements from a particular input are already in the
10128 /// slot required by the given mask and require no permutation.
10129 static bool isShuffleMaskInputInPlace(int Input, ArrayRef<int> Mask) {
10130 assert((Input == 0 || Input == 1) && "Only two inputs to shuffles.");
10131 int Size = Mask.size();
10132 for (int i = 0; i < Size; ++i)
10133 if (Mask[i] >= 0 && Mask[i] / Size == Input && Mask[i] % Size != i)
10139 static SDValue lowerVectorShuffleWithSHUFPD(SDLoc DL, MVT VT,
10140 ArrayRef<int> Mask, SDValue V1,
10141 SDValue V2, SelectionDAG &DAG) {
10143 // Mask for V8F64: 0/1, 8/9, 2/3, 10/11, 4/5, ..
10144 // Mask for V4F64; 0/1, 4/5, 2/3, 6/7..
10145 assert(VT.getScalarSizeInBits() == 64 && "Unexpected data type for VSHUFPD");
10146 int NumElts = VT.getVectorNumElements();
10147 bool ShufpdMask = true;
10148 bool CommutableMask = true;
10149 unsigned Immediate = 0;
10150 for (int i = 0; i < NumElts; ++i) {
10153 int Val = (i & 6) + NumElts * (i & 1);
10154 int CommutVal = (i & 0xe) + NumElts * ((i & 1)^1);
10155 if (Mask[i] < Val || Mask[i] > Val + 1)
10156 ShufpdMask = false;
10157 if (Mask[i] < CommutVal || Mask[i] > CommutVal + 1)
10158 CommutableMask = false;
10159 Immediate |= (Mask[i] % 2) << i;
10162 return DAG.getNode(X86ISD::SHUFP, DL, VT, V1, V2,
10163 DAG.getConstant(Immediate, DL, MVT::i8));
10164 if (CommutableMask)
10165 return DAG.getNode(X86ISD::SHUFP, DL, VT, V2, V1,
10166 DAG.getConstant(Immediate, DL, MVT::i8));
10170 /// \brief Handle lowering of 4-lane 64-bit floating point shuffles.
10172 /// Also ends up handling lowering of 4-lane 64-bit integer shuffles when AVX2
10173 /// isn't available.
10174 static SDValue lowerV4F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10175 const X86Subtarget *Subtarget,
10176 SelectionDAG &DAG) {
10178 assert(V1.getSimpleValueType() == MVT::v4f64 && "Bad operand type!");
10179 assert(V2.getSimpleValueType() == MVT::v4f64 && "Bad operand type!");
10180 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10181 ArrayRef<int> Mask = SVOp->getMask();
10182 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
10184 SmallVector<int, 4> WidenedMask;
10185 if (canWidenShuffleElements(Mask, WidenedMask))
10186 return lowerV2X128VectorShuffle(DL, MVT::v4f64, V1, V2, Mask, Subtarget,
10189 if (isSingleInputShuffleMask(Mask)) {
10190 // Check for being able to broadcast a single element.
10191 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v4f64, V1,
10192 Mask, Subtarget, DAG))
10195 // Use low duplicate instructions for masks that match their pattern.
10196 if (isShuffleEquivalent(V1, V2, Mask, {0, 0, 2, 2}))
10197 return DAG.getNode(X86ISD::MOVDDUP, DL, MVT::v4f64, V1);
10199 if (!is128BitLaneCrossingShuffleMask(MVT::v4f64, Mask)) {
10200 // Non-half-crossing single input shuffles can be lowerid with an
10201 // interleaved permutation.
10202 unsigned VPERMILPMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1) |
10203 ((Mask[2] == 3) << 2) | ((Mask[3] == 3) << 3);
10204 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v4f64, V1,
10205 DAG.getConstant(VPERMILPMask, DL, MVT::i8));
10208 // With AVX2 we have direct support for this permutation.
10209 if (Subtarget->hasAVX2())
10210 return DAG.getNode(X86ISD::VPERMI, DL, MVT::v4f64, V1,
10211 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
10213 // Otherwise, fall back.
10214 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v4f64, V1, V2, Mask,
10218 // Use dedicated unpack instructions for masks that match their pattern.
10220 lowerVectorShuffleWithUNPCK(DL, MVT::v4f64, Mask, V1, V2, DAG))
10223 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4f64, V1, V2, Mask,
10227 // Check if the blend happens to exactly fit that of SHUFPD.
10229 lowerVectorShuffleWithSHUFPD(DL, MVT::v4f64, Mask, V1, V2, DAG))
10232 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10233 // shuffle. However, if we have AVX2 and either inputs are already in place,
10234 // we will be able to shuffle even across lanes the other input in a single
10235 // instruction so skip this pattern.
10236 if (!(Subtarget->hasAVX2() && (isShuffleMaskInputInPlace(0, Mask) ||
10237 isShuffleMaskInputInPlace(1, Mask))))
10238 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10239 DL, MVT::v4f64, V1, V2, Mask, Subtarget, DAG))
10242 // If we have AVX2 then we always want to lower with a blend because an v4 we
10243 // can fully permute the elements.
10244 if (Subtarget->hasAVX2())
10245 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4f64, V1, V2,
10248 // Otherwise fall back on generic lowering.
10249 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v4f64, V1, V2, Mask, DAG);
10252 /// \brief Handle lowering of 4-lane 64-bit integer shuffles.
10254 /// This routine is only called when we have AVX2 and thus a reasonable
10255 /// instruction set for v4i64 shuffling..
10256 static SDValue lowerV4I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10257 const X86Subtarget *Subtarget,
10258 SelectionDAG &DAG) {
10260 assert(V1.getSimpleValueType() == MVT::v4i64 && "Bad operand type!");
10261 assert(V2.getSimpleValueType() == MVT::v4i64 && "Bad operand type!");
10262 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10263 ArrayRef<int> Mask = SVOp->getMask();
10264 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
10265 assert(Subtarget->hasAVX2() && "We can only lower v4i64 with AVX2!");
10267 SmallVector<int, 4> WidenedMask;
10268 if (canWidenShuffleElements(Mask, WidenedMask))
10269 return lowerV2X128VectorShuffle(DL, MVT::v4i64, V1, V2, Mask, Subtarget,
10272 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4i64, V1, V2, Mask,
10276 // Check for being able to broadcast a single element.
10277 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v4i64, V1,
10278 Mask, Subtarget, DAG))
10281 // When the shuffle is mirrored between the 128-bit lanes of the unit, we can
10282 // use lower latency instructions that will operate on both 128-bit lanes.
10283 SmallVector<int, 2> RepeatedMask;
10284 if (is128BitLaneRepeatedShuffleMask(MVT::v4i64, Mask, RepeatedMask)) {
10285 if (isSingleInputShuffleMask(Mask)) {
10286 int PSHUFDMask[] = {-1, -1, -1, -1};
10287 for (int i = 0; i < 2; ++i)
10288 if (RepeatedMask[i] >= 0) {
10289 PSHUFDMask[2 * i] = 2 * RepeatedMask[i];
10290 PSHUFDMask[2 * i + 1] = 2 * RepeatedMask[i] + 1;
10292 return DAG.getBitcast(
10294 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v8i32,
10295 DAG.getBitcast(MVT::v8i32, V1),
10296 getV4X86ShuffleImm8ForMask(PSHUFDMask, DL, DAG)));
10300 // AVX2 provides a direct instruction for permuting a single input across
10302 if (isSingleInputShuffleMask(Mask))
10303 return DAG.getNode(X86ISD::VPERMI, DL, MVT::v4i64, V1,
10304 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
10306 // Try to use shift instructions.
10307 if (SDValue Shift =
10308 lowerVectorShuffleAsShift(DL, MVT::v4i64, V1, V2, Mask, DAG))
10311 // Use dedicated unpack instructions for masks that match their pattern.
10313 lowerVectorShuffleWithUNPCK(DL, MVT::v4i64, Mask, V1, V2, DAG))
10316 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10317 // shuffle. However, if we have AVX2 and either inputs are already in place,
10318 // we will be able to shuffle even across lanes the other input in a single
10319 // instruction so skip this pattern.
10320 if (!(Subtarget->hasAVX2() && (isShuffleMaskInputInPlace(0, Mask) ||
10321 isShuffleMaskInputInPlace(1, Mask))))
10322 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10323 DL, MVT::v4i64, V1, V2, Mask, Subtarget, DAG))
10326 // Otherwise fall back on generic blend lowering.
10327 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4i64, V1, V2,
10331 /// \brief Handle lowering of 8-lane 32-bit floating point shuffles.
10333 /// Also ends up handling lowering of 8-lane 32-bit integer shuffles when AVX2
10334 /// isn't available.
10335 static SDValue lowerV8F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10336 const X86Subtarget *Subtarget,
10337 SelectionDAG &DAG) {
10339 assert(V1.getSimpleValueType() == MVT::v8f32 && "Bad operand type!");
10340 assert(V2.getSimpleValueType() == MVT::v8f32 && "Bad operand type!");
10341 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10342 ArrayRef<int> Mask = SVOp->getMask();
10343 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10345 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8f32, V1, V2, Mask,
10349 // Check for being able to broadcast a single element.
10350 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v8f32, V1,
10351 Mask, Subtarget, DAG))
10354 // If the shuffle mask is repeated in each 128-bit lane, we have many more
10355 // options to efficiently lower the shuffle.
10356 SmallVector<int, 4> RepeatedMask;
10357 if (is128BitLaneRepeatedShuffleMask(MVT::v8f32, Mask, RepeatedMask)) {
10358 assert(RepeatedMask.size() == 4 &&
10359 "Repeated masks must be half the mask width!");
10361 // Use even/odd duplicate instructions for masks that match their pattern.
10362 if (isShuffleEquivalent(V1, V2, Mask, {0, 0, 2, 2, 4, 4, 6, 6}))
10363 return DAG.getNode(X86ISD::MOVSLDUP, DL, MVT::v8f32, V1);
10364 if (isShuffleEquivalent(V1, V2, Mask, {1, 1, 3, 3, 5, 5, 7, 7}))
10365 return DAG.getNode(X86ISD::MOVSHDUP, DL, MVT::v8f32, V1);
10367 if (isSingleInputShuffleMask(Mask))
10368 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v8f32, V1,
10369 getV4X86ShuffleImm8ForMask(RepeatedMask, DL, DAG));
10371 // Use dedicated unpack instructions for masks that match their pattern.
10373 lowerVectorShuffleWithUNPCK(DL, MVT::v8f32, Mask, V1, V2, DAG))
10376 // Otherwise, fall back to a SHUFPS sequence. Here it is important that we
10377 // have already handled any direct blends. We also need to squash the
10378 // repeated mask into a simulated v4f32 mask.
10379 for (int i = 0; i < 4; ++i)
10380 if (RepeatedMask[i] >= 8)
10381 RepeatedMask[i] -= 4;
10382 return lowerVectorShuffleWithSHUFPS(DL, MVT::v8f32, RepeatedMask, V1, V2, DAG);
10385 // If we have a single input shuffle with different shuffle patterns in the
10386 // two 128-bit lanes use the variable mask to VPERMILPS.
10387 if (isSingleInputShuffleMask(Mask)) {
10388 SDValue VPermMask[8];
10389 for (int i = 0; i < 8; ++i)
10390 VPermMask[i] = Mask[i] < 0 ? DAG.getUNDEF(MVT::i32)
10391 : DAG.getConstant(Mask[i], DL, MVT::i32);
10392 if (!is128BitLaneCrossingShuffleMask(MVT::v8f32, Mask))
10393 return DAG.getNode(
10394 X86ISD::VPERMILPV, DL, MVT::v8f32, V1,
10395 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i32, VPermMask));
10397 if (Subtarget->hasAVX2())
10398 return DAG.getNode(
10399 X86ISD::VPERMV, DL, MVT::v8f32,
10400 DAG.getBitcast(MVT::v8f32, DAG.getNode(ISD::BUILD_VECTOR, DL,
10401 MVT::v8i32, VPermMask)),
10404 // Otherwise, fall back.
10405 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v8f32, V1, V2, Mask,
10409 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10411 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10412 DL, MVT::v8f32, V1, V2, Mask, Subtarget, DAG))
10415 // If we have AVX2 then we always want to lower with a blend because at v8 we
10416 // can fully permute the elements.
10417 if (Subtarget->hasAVX2())
10418 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8f32, V1, V2,
10421 // Otherwise fall back on generic lowering.
10422 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v8f32, V1, V2, Mask, DAG);
10425 /// \brief Handle lowering of 8-lane 32-bit integer shuffles.
10427 /// This routine is only called when we have AVX2 and thus a reasonable
10428 /// instruction set for v8i32 shuffling..
10429 static SDValue lowerV8I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10430 const X86Subtarget *Subtarget,
10431 SelectionDAG &DAG) {
10433 assert(V1.getSimpleValueType() == MVT::v8i32 && "Bad operand type!");
10434 assert(V2.getSimpleValueType() == MVT::v8i32 && "Bad operand type!");
10435 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10436 ArrayRef<int> Mask = SVOp->getMask();
10437 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10438 assert(Subtarget->hasAVX2() && "We can only lower v8i32 with AVX2!");
10440 // Whenever we can lower this as a zext, that instruction is strictly faster
10441 // than any alternative. It also allows us to fold memory operands into the
10442 // shuffle in many cases.
10443 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v8i32, V1, V2,
10444 Mask, Subtarget, DAG))
10447 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8i32, V1, V2, Mask,
10451 // Check for being able to broadcast a single element.
10452 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v8i32, V1,
10453 Mask, Subtarget, DAG))
10456 // If the shuffle mask is repeated in each 128-bit lane we can use more
10457 // efficient instructions that mirror the shuffles across the two 128-bit
10459 SmallVector<int, 4> RepeatedMask;
10460 if (is128BitLaneRepeatedShuffleMask(MVT::v8i32, Mask, RepeatedMask)) {
10461 assert(RepeatedMask.size() == 4 && "Unexpected repeated mask size!");
10462 if (isSingleInputShuffleMask(Mask))
10463 return DAG.getNode(X86ISD::PSHUFD, DL, MVT::v8i32, V1,
10464 getV4X86ShuffleImm8ForMask(RepeatedMask, DL, DAG));
10466 // Use dedicated unpack instructions for masks that match their pattern.
10468 lowerVectorShuffleWithUNPCK(DL, MVT::v8i32, Mask, V1, V2, DAG))
10472 // Try to use shift instructions.
10473 if (SDValue Shift =
10474 lowerVectorShuffleAsShift(DL, MVT::v8i32, V1, V2, Mask, DAG))
10477 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
10478 DL, MVT::v8i32, V1, V2, Mask, Subtarget, DAG))
10481 // If the shuffle patterns aren't repeated but it is a single input, directly
10482 // generate a cross-lane VPERMD instruction.
10483 if (isSingleInputShuffleMask(Mask)) {
10484 SDValue VPermMask[8];
10485 for (int i = 0; i < 8; ++i)
10486 VPermMask[i] = Mask[i] < 0 ? DAG.getUNDEF(MVT::i32)
10487 : DAG.getConstant(Mask[i], DL, MVT::i32);
10488 return DAG.getNode(
10489 X86ISD::VPERMV, DL, MVT::v8i32,
10490 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i32, VPermMask), V1);
10493 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10495 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10496 DL, MVT::v8i32, V1, V2, Mask, Subtarget, DAG))
10499 // Otherwise fall back on generic blend lowering.
10500 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8i32, V1, V2,
10504 /// \brief Handle lowering of 16-lane 16-bit integer shuffles.
10506 /// This routine is only called when we have AVX2 and thus a reasonable
10507 /// instruction set for v16i16 shuffling..
10508 static SDValue lowerV16I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10509 const X86Subtarget *Subtarget,
10510 SelectionDAG &DAG) {
10512 assert(V1.getSimpleValueType() == MVT::v16i16 && "Bad operand type!");
10513 assert(V2.getSimpleValueType() == MVT::v16i16 && "Bad operand type!");
10514 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10515 ArrayRef<int> Mask = SVOp->getMask();
10516 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
10517 assert(Subtarget->hasAVX2() && "We can only lower v16i16 with AVX2!");
10519 // Whenever we can lower this as a zext, that instruction is strictly faster
10520 // than any alternative. It also allows us to fold memory operands into the
10521 // shuffle in many cases.
10522 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v16i16, V1, V2,
10523 Mask, Subtarget, DAG))
10526 // Check for being able to broadcast a single element.
10527 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v16i16, V1,
10528 Mask, Subtarget, DAG))
10531 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v16i16, V1, V2, Mask,
10535 // Use dedicated unpack instructions for masks that match their pattern.
10537 lowerVectorShuffleWithUNPCK(DL, MVT::v16i16, Mask, V1, V2, DAG))
10540 // Try to use shift instructions.
10541 if (SDValue Shift =
10542 lowerVectorShuffleAsShift(DL, MVT::v16i16, V1, V2, Mask, DAG))
10545 // Try to use byte rotation instructions.
10546 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
10547 DL, MVT::v16i16, V1, V2, Mask, Subtarget, DAG))
10550 if (isSingleInputShuffleMask(Mask)) {
10551 // There are no generalized cross-lane shuffle operations available on i16
10553 if (is128BitLaneCrossingShuffleMask(MVT::v16i16, Mask))
10554 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v16i16, V1, V2,
10557 SmallVector<int, 8> RepeatedMask;
10558 if (is128BitLaneRepeatedShuffleMask(MVT::v16i16, Mask, RepeatedMask)) {
10559 // As this is a single-input shuffle, the repeated mask should be
10560 // a strictly valid v8i16 mask that we can pass through to the v8i16
10561 // lowering to handle even the v16 case.
10562 return lowerV8I16GeneralSingleInputVectorShuffle(
10563 DL, MVT::v16i16, V1, RepeatedMask, Subtarget, DAG);
10566 SDValue PSHUFBMask[32];
10567 for (int i = 0; i < 16; ++i) {
10568 if (Mask[i] == -1) {
10569 PSHUFBMask[2 * i] = PSHUFBMask[2 * i + 1] = DAG.getUNDEF(MVT::i8);
10573 int M = i < 8 ? Mask[i] : Mask[i] - 8;
10574 assert(M >= 0 && M < 8 && "Invalid single-input mask!");
10575 PSHUFBMask[2 * i] = DAG.getConstant(2 * M, DL, MVT::i8);
10576 PSHUFBMask[2 * i + 1] = DAG.getConstant(2 * M + 1, DL, MVT::i8);
10578 return DAG.getBitcast(MVT::v16i16,
10579 DAG.getNode(X86ISD::PSHUFB, DL, MVT::v32i8,
10580 DAG.getBitcast(MVT::v32i8, V1),
10581 DAG.getNode(ISD::BUILD_VECTOR, DL,
10582 MVT::v32i8, PSHUFBMask)));
10585 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10587 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10588 DL, MVT::v16i16, V1, V2, Mask, Subtarget, DAG))
10591 // Otherwise fall back on generic lowering.
10592 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v16i16, V1, V2, Mask, DAG);
10595 /// \brief Handle lowering of 32-lane 8-bit integer shuffles.
10597 /// This routine is only called when we have AVX2 and thus a reasonable
10598 /// instruction set for v32i8 shuffling..
10599 static SDValue lowerV32I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10600 const X86Subtarget *Subtarget,
10601 SelectionDAG &DAG) {
10603 assert(V1.getSimpleValueType() == MVT::v32i8 && "Bad operand type!");
10604 assert(V2.getSimpleValueType() == MVT::v32i8 && "Bad operand type!");
10605 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10606 ArrayRef<int> Mask = SVOp->getMask();
10607 assert(Mask.size() == 32 && "Unexpected mask size for v32 shuffle!");
10608 assert(Subtarget->hasAVX2() && "We can only lower v32i8 with AVX2!");
10610 // Whenever we can lower this as a zext, that instruction is strictly faster
10611 // than any alternative. It also allows us to fold memory operands into the
10612 // shuffle in many cases.
10613 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v32i8, V1, V2,
10614 Mask, Subtarget, DAG))
10617 // Check for being able to broadcast a single element.
10618 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v32i8, V1,
10619 Mask, Subtarget, DAG))
10622 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v32i8, V1, V2, Mask,
10626 // Use dedicated unpack instructions for masks that match their pattern.
10628 lowerVectorShuffleWithUNPCK(DL, MVT::v32i8, Mask, V1, V2, DAG))
10631 // Try to use shift instructions.
10632 if (SDValue Shift =
10633 lowerVectorShuffleAsShift(DL, MVT::v32i8, V1, V2, Mask, DAG))
10636 // Try to use byte rotation instructions.
10637 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
10638 DL, MVT::v32i8, V1, V2, Mask, Subtarget, DAG))
10641 if (isSingleInputShuffleMask(Mask)) {
10642 // There are no generalized cross-lane shuffle operations available on i8
10644 if (is128BitLaneCrossingShuffleMask(MVT::v32i8, Mask))
10645 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v32i8, V1, V2,
10648 SDValue PSHUFBMask[32];
10649 for (int i = 0; i < 32; ++i)
10652 ? DAG.getUNDEF(MVT::i8)
10653 : DAG.getConstant(Mask[i] < 16 ? Mask[i] : Mask[i] - 16, DL,
10656 return DAG.getNode(
10657 X86ISD::PSHUFB, DL, MVT::v32i8, V1,
10658 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, PSHUFBMask));
10661 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10663 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10664 DL, MVT::v32i8, V1, V2, Mask, Subtarget, DAG))
10667 // Otherwise fall back on generic lowering.
10668 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v32i8, V1, V2, Mask, DAG);
10671 /// \brief High-level routine to lower various 256-bit x86 vector shuffles.
10673 /// This routine either breaks down the specific type of a 256-bit x86 vector
10674 /// shuffle or splits it into two 128-bit shuffles and fuses the results back
10675 /// together based on the available instructions.
10676 static SDValue lower256BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10677 MVT VT, const X86Subtarget *Subtarget,
10678 SelectionDAG &DAG) {
10680 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10681 ArrayRef<int> Mask = SVOp->getMask();
10683 // If we have a single input to the zero element, insert that into V1 if we
10684 // can do so cheaply.
10685 int NumElts = VT.getVectorNumElements();
10686 int NumV2Elements = std::count_if(Mask.begin(), Mask.end(), [NumElts](int M) {
10687 return M >= NumElts;
10690 if (NumV2Elements == 1 && Mask[0] >= NumElts)
10691 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
10692 DL, VT, V1, V2, Mask, Subtarget, DAG))
10695 // There is a really nice hard cut-over between AVX1 and AVX2 that means we
10696 // can check for those subtargets here and avoid much of the subtarget
10697 // querying in the per-vector-type lowering routines. With AVX1 we have
10698 // essentially *zero* ability to manipulate a 256-bit vector with integer
10699 // types. Since we'll use floating point types there eventually, just
10700 // immediately cast everything to a float and operate entirely in that domain.
10701 if (VT.isInteger() && !Subtarget->hasAVX2()) {
10702 int ElementBits = VT.getScalarSizeInBits();
10703 if (ElementBits < 32)
10704 // No floating point type available, decompose into 128-bit vectors.
10705 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
10707 MVT FpVT = MVT::getVectorVT(MVT::getFloatingPointVT(ElementBits),
10708 VT.getVectorNumElements());
10709 V1 = DAG.getBitcast(FpVT, V1);
10710 V2 = DAG.getBitcast(FpVT, V2);
10711 return DAG.getBitcast(VT, DAG.getVectorShuffle(FpVT, DL, V1, V2, Mask));
10714 switch (VT.SimpleTy) {
10716 return lowerV4F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10718 return lowerV4I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10720 return lowerV8F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10722 return lowerV8I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10724 return lowerV16I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
10726 return lowerV32I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
10729 llvm_unreachable("Not a valid 256-bit x86 vector type!");
10733 /// \brief Try to lower a vector shuffle as a 128-bit shuffles.
10734 static SDValue lowerV4X128VectorShuffle(SDLoc DL, MVT VT,
10735 ArrayRef<int> Mask,
10736 SDValue V1, SDValue V2,
10737 SelectionDAG &DAG) {
10738 assert(VT.getScalarSizeInBits() == 64 &&
10739 "Unexpected element type size for 128bit shuffle.");
10741 // To handle 256 bit vector requires VLX and most probably
10742 // function lowerV2X128VectorShuffle() is better solution.
10743 assert(VT.getSizeInBits() == 512 &&
10744 "Unexpected vector size for 128bit shuffle.");
10746 SmallVector<int, 4> WidenedMask;
10747 if (!canWidenShuffleElements(Mask, WidenedMask))
10750 // Form a 128-bit permutation.
10751 // Convert the 64-bit shuffle mask selection values into 128-bit selection
10752 // bits defined by a vshuf64x2 instruction's immediate control byte.
10753 unsigned PermMask = 0, Imm = 0;
10754 unsigned ControlBitsNum = WidenedMask.size() / 2;
10756 for (int i = 0, Size = WidenedMask.size(); i < Size; ++i) {
10757 if (WidenedMask[i] == SM_SentinelZero)
10760 // Use first element in place of undef mask.
10761 Imm = (WidenedMask[i] == SM_SentinelUndef) ? 0 : WidenedMask[i];
10762 PermMask |= (Imm % WidenedMask.size()) << (i * ControlBitsNum);
10765 return DAG.getNode(X86ISD::SHUF128, DL, VT, V1, V2,
10766 DAG.getConstant(PermMask, DL, MVT::i8));
10769 static SDValue lowerVectorShuffleWithPERMV(SDLoc DL, MVT VT,
10770 ArrayRef<int> Mask, SDValue V1,
10771 SDValue V2, SelectionDAG &DAG) {
10773 assert(VT.getScalarSizeInBits() >= 16 && "Unexpected data type for PERMV");
10775 MVT MaskEltVT = MVT::getIntegerVT(VT.getScalarSizeInBits());
10776 MVT MaskVecVT = MVT::getVectorVT(MaskEltVT, VT.getVectorNumElements());
10778 SDValue MaskNode = getConstVector(Mask, MaskVecVT, DAG, DL, true);
10779 if (isSingleInputShuffleMask(Mask))
10780 return DAG.getNode(X86ISD::VPERMV, DL, VT, MaskNode, V1);
10782 return DAG.getNode(X86ISD::VPERMV3, DL, VT, V1, MaskNode, V2);
10785 /// \brief Handle lowering of 8-lane 64-bit floating point shuffles.
10786 static SDValue lowerV8F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10787 const X86Subtarget *Subtarget,
10788 SelectionDAG &DAG) {
10790 assert(V1.getSimpleValueType() == MVT::v8f64 && "Bad operand type!");
10791 assert(V2.getSimpleValueType() == MVT::v8f64 && "Bad operand type!");
10792 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10793 ArrayRef<int> Mask = SVOp->getMask();
10794 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10796 if (SDValue Shuf128 =
10797 lowerV4X128VectorShuffle(DL, MVT::v8f64, Mask, V1, V2, DAG))
10800 if (SDValue Unpck =
10801 lowerVectorShuffleWithUNPCK(DL, MVT::v8f64, Mask, V1, V2, DAG))
10804 return lowerVectorShuffleWithPERMV(DL, MVT::v8f64, Mask, V1, V2, DAG);
10807 /// \brief Handle lowering of 16-lane 32-bit floating point shuffles.
10808 static SDValue lowerV16F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10809 const X86Subtarget *Subtarget,
10810 SelectionDAG &DAG) {
10812 assert(V1.getSimpleValueType() == MVT::v16f32 && "Bad operand type!");
10813 assert(V2.getSimpleValueType() == MVT::v16f32 && "Bad operand type!");
10814 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10815 ArrayRef<int> Mask = SVOp->getMask();
10816 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
10818 if (SDValue Unpck =
10819 lowerVectorShuffleWithUNPCK(DL, MVT::v16f32, Mask, V1, V2, DAG))
10822 return lowerVectorShuffleWithPERMV(DL, MVT::v16f32, Mask, V1, V2, DAG);
10825 /// \brief Handle lowering of 8-lane 64-bit integer shuffles.
10826 static SDValue lowerV8I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10827 const X86Subtarget *Subtarget,
10828 SelectionDAG &DAG) {
10830 assert(V1.getSimpleValueType() == MVT::v8i64 && "Bad operand type!");
10831 assert(V2.getSimpleValueType() == MVT::v8i64 && "Bad operand type!");
10832 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10833 ArrayRef<int> Mask = SVOp->getMask();
10834 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10836 if (SDValue Shuf128 =
10837 lowerV4X128VectorShuffle(DL, MVT::v8i64, Mask, V1, V2, DAG))
10840 if (SDValue Unpck =
10841 lowerVectorShuffleWithUNPCK(DL, MVT::v8i64, Mask, V1, V2, DAG))
10844 return lowerVectorShuffleWithPERMV(DL, MVT::v8i64, Mask, V1, V2, DAG);
10847 /// \brief Handle lowering of 16-lane 32-bit integer shuffles.
10848 static SDValue lowerV16I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10849 const X86Subtarget *Subtarget,
10850 SelectionDAG &DAG) {
10852 assert(V1.getSimpleValueType() == MVT::v16i32 && "Bad operand type!");
10853 assert(V2.getSimpleValueType() == MVT::v16i32 && "Bad operand type!");
10854 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10855 ArrayRef<int> Mask = SVOp->getMask();
10856 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
10858 if (SDValue Unpck =
10859 lowerVectorShuffleWithUNPCK(DL, MVT::v16i32, Mask, V1, V2, DAG))
10862 return lowerVectorShuffleWithPERMV(DL, MVT::v16i32, Mask, V1, V2, DAG);
10865 /// \brief Handle lowering of 32-lane 16-bit integer shuffles.
10866 static SDValue lowerV32I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10867 const X86Subtarget *Subtarget,
10868 SelectionDAG &DAG) {
10870 assert(V1.getSimpleValueType() == MVT::v32i16 && "Bad operand type!");
10871 assert(V2.getSimpleValueType() == MVT::v32i16 && "Bad operand type!");
10872 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10873 ArrayRef<int> Mask = SVOp->getMask();
10874 assert(Mask.size() == 32 && "Unexpected mask size for v32 shuffle!");
10875 assert(Subtarget->hasBWI() && "We can only lower v32i16 with AVX-512-BWI!");
10877 return lowerVectorShuffleWithPERMV(DL, MVT::v32i16, Mask, V1, V2, DAG);
10880 /// \brief Handle lowering of 64-lane 8-bit integer shuffles.
10881 static SDValue lowerV64I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10882 const X86Subtarget *Subtarget,
10883 SelectionDAG &DAG) {
10885 assert(V1.getSimpleValueType() == MVT::v64i8 && "Bad operand type!");
10886 assert(V2.getSimpleValueType() == MVT::v64i8 && "Bad operand type!");
10887 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10888 ArrayRef<int> Mask = SVOp->getMask();
10889 assert(Mask.size() == 64 && "Unexpected mask size for v64 shuffle!");
10890 assert(Subtarget->hasBWI() && "We can only lower v64i8 with AVX-512-BWI!");
10892 // FIXME: Implement direct support for this type!
10893 return splitAndLowerVectorShuffle(DL, MVT::v64i8, V1, V2, Mask, DAG);
10896 /// \brief High-level routine to lower various 512-bit x86 vector shuffles.
10898 /// This routine either breaks down the specific type of a 512-bit x86 vector
10899 /// shuffle or splits it into two 256-bit shuffles and fuses the results back
10900 /// together based on the available instructions.
10901 static SDValue lower512BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10902 MVT VT, const X86Subtarget *Subtarget,
10903 SelectionDAG &DAG) {
10905 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10906 ArrayRef<int> Mask = SVOp->getMask();
10907 assert(Subtarget->hasAVX512() &&
10908 "Cannot lower 512-bit vectors w/ basic ISA!");
10910 // Check for being able to broadcast a single element.
10911 if (SDValue Broadcast =
10912 lowerVectorShuffleAsBroadcast(DL, VT, V1, Mask, Subtarget, DAG))
10915 // Dispatch to each element type for lowering. If we don't have supprot for
10916 // specific element type shuffles at 512 bits, immediately split them and
10917 // lower them. Each lowering routine of a given type is allowed to assume that
10918 // the requisite ISA extensions for that element type are available.
10919 switch (VT.SimpleTy) {
10921 return lowerV8F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10923 return lowerV16F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10925 return lowerV8I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10927 return lowerV16I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10929 if (Subtarget->hasBWI())
10930 return lowerV32I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
10933 if (Subtarget->hasBWI())
10934 return lowerV64I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
10938 llvm_unreachable("Not a valid 512-bit x86 vector type!");
10941 // Otherwise fall back on splitting.
10942 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
10945 // Lower vXi1 vector shuffles.
10946 // There is no a dedicated instruction on AVX-512 that shuffles the masks.
10947 // The only way to shuffle bits is to sign-extend the mask vector to SIMD
10948 // vector, shuffle and then truncate it back.
10949 static SDValue lower1BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10950 MVT VT, const X86Subtarget *Subtarget,
10951 SelectionDAG &DAG) {
10953 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10954 ArrayRef<int> Mask = SVOp->getMask();
10955 assert(Subtarget->hasAVX512() &&
10956 "Cannot lower 512-bit vectors w/o basic ISA!");
10958 switch (VT.SimpleTy) {
10960 llvm_unreachable("Expected a vector of i1 elements");
10962 ExtVT = MVT::v2i64;
10965 ExtVT = MVT::v4i32;
10968 ExtVT = MVT::v8i64; // Take 512-bit type, more shuffles on KNL
10971 ExtVT = MVT::v16i32;
10974 ExtVT = MVT::v32i16;
10977 ExtVT = MVT::v64i8;
10981 if (ISD::isBuildVectorAllZeros(V1.getNode()))
10982 V1 = getZeroVector(ExtVT, Subtarget, DAG, DL);
10983 else if (ISD::isBuildVectorAllOnes(V1.getNode()))
10984 V1 = getOnesVector(ExtVT, Subtarget, DAG, DL);
10986 V1 = DAG.getNode(ISD::SIGN_EXTEND, DL, ExtVT, V1);
10989 V2 = DAG.getUNDEF(ExtVT);
10990 else if (ISD::isBuildVectorAllZeros(V2.getNode()))
10991 V2 = getZeroVector(ExtVT, Subtarget, DAG, DL);
10992 else if (ISD::isBuildVectorAllOnes(V2.getNode()))
10993 V2 = getOnesVector(ExtVT, Subtarget, DAG, DL);
10995 V2 = DAG.getNode(ISD::SIGN_EXTEND, DL, ExtVT, V2);
10996 return DAG.getNode(ISD::TRUNCATE, DL, VT,
10997 DAG.getVectorShuffle(ExtVT, DL, V1, V2, Mask));
10999 /// \brief Top-level lowering for x86 vector shuffles.
11001 /// This handles decomposition, canonicalization, and lowering of all x86
11002 /// vector shuffles. Most of the specific lowering strategies are encapsulated
11003 /// above in helper routines. The canonicalization attempts to widen shuffles
11004 /// to involve fewer lanes of wider elements, consolidate symmetric patterns
11005 /// s.t. only one of the two inputs needs to be tested, etc.
11006 static SDValue lowerVectorShuffle(SDValue Op, const X86Subtarget *Subtarget,
11007 SelectionDAG &DAG) {
11008 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11009 ArrayRef<int> Mask = SVOp->getMask();
11010 SDValue V1 = Op.getOperand(0);
11011 SDValue V2 = Op.getOperand(1);
11012 MVT VT = Op.getSimpleValueType();
11013 int NumElements = VT.getVectorNumElements();
11015 bool Is1BitVector = (VT.getScalarType() == MVT::i1);
11017 assert((VT.getSizeInBits() != 64 || Is1BitVector) &&
11018 "Can't lower MMX shuffles");
11020 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
11021 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
11022 if (V1IsUndef && V2IsUndef)
11023 return DAG.getUNDEF(VT);
11025 // When we create a shuffle node we put the UNDEF node to second operand,
11026 // but in some cases the first operand may be transformed to UNDEF.
11027 // In this case we should just commute the node.
11029 return DAG.getCommutedVectorShuffle(*SVOp);
11031 // Check for non-undef masks pointing at an undef vector and make the masks
11032 // undef as well. This makes it easier to match the shuffle based solely on
11036 if (M >= NumElements) {
11037 SmallVector<int, 8> NewMask(Mask.begin(), Mask.end());
11038 for (int &M : NewMask)
11039 if (M >= NumElements)
11041 return DAG.getVectorShuffle(VT, dl, V1, V2, NewMask);
11044 // We actually see shuffles that are entirely re-arrangements of a set of
11045 // zero inputs. This mostly happens while decomposing complex shuffles into
11046 // simple ones. Directly lower these as a buildvector of zeros.
11047 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
11048 if (Zeroable.all())
11049 return getZeroVector(VT, Subtarget, DAG, dl);
11051 // Try to collapse shuffles into using a vector type with fewer elements but
11052 // wider element types. We cap this to not form integers or floating point
11053 // elements wider than 64 bits, but it might be interesting to form i128
11054 // integers to handle flipping the low and high halves of AVX 256-bit vectors.
11055 SmallVector<int, 16> WidenedMask;
11056 if (VT.getScalarSizeInBits() < 64 && !Is1BitVector &&
11057 canWidenShuffleElements(Mask, WidenedMask)) {
11058 MVT NewEltVT = VT.isFloatingPoint()
11059 ? MVT::getFloatingPointVT(VT.getScalarSizeInBits() * 2)
11060 : MVT::getIntegerVT(VT.getScalarSizeInBits() * 2);
11061 MVT NewVT = MVT::getVectorVT(NewEltVT, VT.getVectorNumElements() / 2);
11062 // Make sure that the new vector type is legal. For example, v2f64 isn't
11064 if (DAG.getTargetLoweringInfo().isTypeLegal(NewVT)) {
11065 V1 = DAG.getBitcast(NewVT, V1);
11066 V2 = DAG.getBitcast(NewVT, V2);
11067 return DAG.getBitcast(
11068 VT, DAG.getVectorShuffle(NewVT, dl, V1, V2, WidenedMask));
11072 int NumV1Elements = 0, NumUndefElements = 0, NumV2Elements = 0;
11073 for (int M : SVOp->getMask())
11075 ++NumUndefElements;
11076 else if (M < NumElements)
11081 // Commute the shuffle as needed such that more elements come from V1 than
11082 // V2. This allows us to match the shuffle pattern strictly on how many
11083 // elements come from V1 without handling the symmetric cases.
11084 if (NumV2Elements > NumV1Elements)
11085 return DAG.getCommutedVectorShuffle(*SVOp);
11087 // When the number of V1 and V2 elements are the same, try to minimize the
11088 // number of uses of V2 in the low half of the vector. When that is tied,
11089 // ensure that the sum of indices for V1 is equal to or lower than the sum
11090 // indices for V2. When those are equal, try to ensure that the number of odd
11091 // indices for V1 is lower than the number of odd indices for V2.
11092 if (NumV1Elements == NumV2Elements) {
11093 int LowV1Elements = 0, LowV2Elements = 0;
11094 for (int M : SVOp->getMask().slice(0, NumElements / 2))
11095 if (M >= NumElements)
11099 if (LowV2Elements > LowV1Elements) {
11100 return DAG.getCommutedVectorShuffle(*SVOp);
11101 } else if (LowV2Elements == LowV1Elements) {
11102 int SumV1Indices = 0, SumV2Indices = 0;
11103 for (int i = 0, Size = SVOp->getMask().size(); i < Size; ++i)
11104 if (SVOp->getMask()[i] >= NumElements)
11106 else if (SVOp->getMask()[i] >= 0)
11108 if (SumV2Indices < SumV1Indices) {
11109 return DAG.getCommutedVectorShuffle(*SVOp);
11110 } else if (SumV2Indices == SumV1Indices) {
11111 int NumV1OddIndices = 0, NumV2OddIndices = 0;
11112 for (int i = 0, Size = SVOp->getMask().size(); i < Size; ++i)
11113 if (SVOp->getMask()[i] >= NumElements)
11114 NumV2OddIndices += i % 2;
11115 else if (SVOp->getMask()[i] >= 0)
11116 NumV1OddIndices += i % 2;
11117 if (NumV2OddIndices < NumV1OddIndices)
11118 return DAG.getCommutedVectorShuffle(*SVOp);
11123 // For each vector width, delegate to a specialized lowering routine.
11124 if (VT.getSizeInBits() == 128)
11125 return lower128BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
11127 if (VT.getSizeInBits() == 256)
11128 return lower256BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
11130 if (VT.getSizeInBits() == 512)
11131 return lower512BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
11134 return lower1BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
11135 llvm_unreachable("Unimplemented!");
11138 // This function assumes its argument is a BUILD_VECTOR of constants or
11139 // undef SDNodes. i.e: ISD::isBuildVectorOfConstantSDNodes(BuildVector) is
11141 static bool BUILD_VECTORtoBlendMask(BuildVectorSDNode *BuildVector,
11142 unsigned &MaskValue) {
11144 unsigned NumElems = BuildVector->getNumOperands();
11146 // There are 2 lanes if (NumElems > 8), and 1 lane otherwise.
11147 // We don't handle the >2 lanes case right now.
11148 unsigned NumLanes = (NumElems - 1) / 8 + 1;
11152 unsigned NumElemsInLane = NumElems / NumLanes;
11154 // Blend for v16i16 should be symmetric for the both lanes.
11155 for (unsigned i = 0; i < NumElemsInLane; ++i) {
11156 SDValue EltCond = BuildVector->getOperand(i);
11157 SDValue SndLaneEltCond =
11158 (NumLanes == 2) ? BuildVector->getOperand(i + NumElemsInLane) : EltCond;
11160 int Lane1Cond = -1, Lane2Cond = -1;
11161 if (isa<ConstantSDNode>(EltCond))
11162 Lane1Cond = !isZero(EltCond);
11163 if (isa<ConstantSDNode>(SndLaneEltCond))
11164 Lane2Cond = !isZero(SndLaneEltCond);
11166 unsigned LaneMask = 0;
11167 if (Lane1Cond == Lane2Cond || Lane2Cond < 0)
11168 // Lane1Cond != 0, means we want the first argument.
11169 // Lane1Cond == 0, means we want the second argument.
11170 // The encoding of this argument is 0 for the first argument, 1
11171 // for the second. Therefore, invert the condition.
11172 LaneMask = !Lane1Cond << i;
11173 else if (Lane1Cond < 0)
11174 LaneMask = !Lane2Cond << i;
11178 MaskValue |= LaneMask;
11180 MaskValue |= LaneMask << NumElemsInLane;
11185 /// \brief Try to lower a VSELECT instruction to a vector shuffle.
11186 static SDValue lowerVSELECTtoVectorShuffle(SDValue Op,
11187 const X86Subtarget *Subtarget,
11188 SelectionDAG &DAG) {
11189 SDValue Cond = Op.getOperand(0);
11190 SDValue LHS = Op.getOperand(1);
11191 SDValue RHS = Op.getOperand(2);
11193 MVT VT = Op.getSimpleValueType();
11195 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
11197 auto *CondBV = cast<BuildVectorSDNode>(Cond);
11199 // Only non-legal VSELECTs reach this lowering, convert those into generic
11200 // shuffles and re-use the shuffle lowering path for blends.
11201 SmallVector<int, 32> Mask;
11202 for (int i = 0, Size = VT.getVectorNumElements(); i < Size; ++i) {
11203 SDValue CondElt = CondBV->getOperand(i);
11205 isa<ConstantSDNode>(CondElt) ? i + (isZero(CondElt) ? Size : 0) : -1);
11207 return DAG.getVectorShuffle(VT, dl, LHS, RHS, Mask);
11210 SDValue X86TargetLowering::LowerVSELECT(SDValue Op, SelectionDAG &DAG) const {
11211 // A vselect where all conditions and data are constants can be optimized into
11212 // a single vector load by SelectionDAGLegalize::ExpandBUILD_VECTOR().
11213 if (ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(0).getNode()) &&
11214 ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(1).getNode()) &&
11215 ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(2).getNode()))
11218 // Try to lower this to a blend-style vector shuffle. This can handle all
11219 // constant condition cases.
11220 if (SDValue BlendOp = lowerVSELECTtoVectorShuffle(Op, Subtarget, DAG))
11223 // Variable blends are only legal from SSE4.1 onward.
11224 if (!Subtarget->hasSSE41())
11227 // Only some types will be legal on some subtargets. If we can emit a legal
11228 // VSELECT-matching blend, return Op, and but if we need to expand, return
11230 switch (Op.getSimpleValueType().SimpleTy) {
11232 // Most of the vector types have blends past SSE4.1.
11236 // The byte blends for AVX vectors were introduced only in AVX2.
11237 if (Subtarget->hasAVX2())
11244 // AVX-512 BWI and VLX features support VSELECT with i16 elements.
11245 if (Subtarget->hasBWI() && Subtarget->hasVLX())
11248 // FIXME: We should custom lower this by fixing the condition and using i8
11254 static SDValue LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) {
11255 MVT VT = Op.getSimpleValueType();
11258 if (!Op.getOperand(0).getSimpleValueType().is128BitVector())
11261 if (VT.getSizeInBits() == 8) {
11262 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
11263 Op.getOperand(0), Op.getOperand(1));
11264 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
11265 DAG.getValueType(VT));
11266 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
11269 if (VT.getSizeInBits() == 16) {
11270 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
11271 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
11273 return DAG.getNode(
11274 ISD::TRUNCATE, dl, MVT::i16,
11275 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
11276 DAG.getBitcast(MVT::v4i32, Op.getOperand(0)),
11277 Op.getOperand(1)));
11278 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
11279 Op.getOperand(0), Op.getOperand(1));
11280 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
11281 DAG.getValueType(VT));
11282 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
11285 if (VT == MVT::f32) {
11286 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
11287 // the result back to FR32 register. It's only worth matching if the
11288 // result has a single use which is a store or a bitcast to i32. And in
11289 // the case of a store, it's not worth it if the index is a constant 0,
11290 // because a MOVSSmr can be used instead, which is smaller and faster.
11291 if (!Op.hasOneUse())
11293 SDNode *User = *Op.getNode()->use_begin();
11294 if ((User->getOpcode() != ISD::STORE ||
11295 (isa<ConstantSDNode>(Op.getOperand(1)) &&
11296 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
11297 (User->getOpcode() != ISD::BITCAST ||
11298 User->getValueType(0) != MVT::i32))
11300 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
11301 DAG.getBitcast(MVT::v4i32, Op.getOperand(0)),
11303 return DAG.getBitcast(MVT::f32, Extract);
11306 if (VT == MVT::i32 || VT == MVT::i64) {
11307 // ExtractPS/pextrq works with constant index.
11308 if (isa<ConstantSDNode>(Op.getOperand(1)))
11314 /// Extract one bit from mask vector, like v16i1 or v8i1.
11315 /// AVX-512 feature.
11317 X86TargetLowering::ExtractBitFromMaskVector(SDValue Op, SelectionDAG &DAG) const {
11318 SDValue Vec = Op.getOperand(0);
11320 MVT VecVT = Vec.getSimpleValueType();
11321 SDValue Idx = Op.getOperand(1);
11322 MVT EltVT = Op.getSimpleValueType();
11324 assert((EltVT == MVT::i1) && "Unexpected operands in ExtractBitFromMaskVector");
11325 assert((VecVT.getVectorNumElements() <= 16 || Subtarget->hasBWI()) &&
11326 "Unexpected vector type in ExtractBitFromMaskVector");
11328 // variable index can't be handled in mask registers,
11329 // extend vector to VR512
11330 if (!isa<ConstantSDNode>(Idx)) {
11331 MVT ExtVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
11332 SDValue Ext = DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVT, Vec);
11333 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
11334 ExtVT.getVectorElementType(), Ext, Idx);
11335 return DAG.getNode(ISD::TRUNCATE, dl, EltVT, Elt);
11338 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
11339 const TargetRegisterClass* rc = getRegClassFor(VecVT);
11340 if (!Subtarget->hasDQI() && (VecVT.getVectorNumElements() <= 8))
11341 rc = getRegClassFor(MVT::v16i1);
11342 unsigned MaxSift = rc->getSize()*8 - 1;
11343 Vec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, Vec,
11344 DAG.getConstant(MaxSift - IdxVal, dl, MVT::i8));
11345 Vec = DAG.getNode(X86ISD::VSRLI, dl, VecVT, Vec,
11346 DAG.getConstant(MaxSift, dl, MVT::i8));
11347 return DAG.getNode(X86ISD::VEXTRACT, dl, MVT::i1, Vec,
11348 DAG.getIntPtrConstant(0, dl));
11352 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
11353 SelectionDAG &DAG) const {
11355 SDValue Vec = Op.getOperand(0);
11356 MVT VecVT = Vec.getSimpleValueType();
11357 SDValue Idx = Op.getOperand(1);
11359 if (Op.getSimpleValueType() == MVT::i1)
11360 return ExtractBitFromMaskVector(Op, DAG);
11362 if (!isa<ConstantSDNode>(Idx)) {
11363 if (VecVT.is512BitVector() ||
11364 (VecVT.is256BitVector() && Subtarget->hasInt256() &&
11365 VecVT.getVectorElementType().getSizeInBits() == 32)) {
11368 MVT::getIntegerVT(VecVT.getVectorElementType().getSizeInBits());
11369 MVT MaskVT = MVT::getVectorVT(MaskEltVT, VecVT.getSizeInBits() /
11370 MaskEltVT.getSizeInBits());
11372 Idx = DAG.getZExtOrTrunc(Idx, dl, MaskEltVT);
11373 auto PtrVT = getPointerTy(DAG.getDataLayout());
11374 SDValue Mask = DAG.getNode(X86ISD::VINSERT, dl, MaskVT,
11375 getZeroVector(MaskVT, Subtarget, DAG, dl), Idx,
11376 DAG.getConstant(0, dl, PtrVT));
11377 SDValue Perm = DAG.getNode(X86ISD::VPERMV, dl, VecVT, Mask, Vec);
11378 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Perm,
11379 DAG.getConstant(0, dl, PtrVT));
11384 // If this is a 256-bit vector result, first extract the 128-bit vector and
11385 // then extract the element from the 128-bit vector.
11386 if (VecVT.is256BitVector() || VecVT.is512BitVector()) {
11388 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
11389 // Get the 128-bit vector.
11390 Vec = Extract128BitVector(Vec, IdxVal, DAG, dl);
11391 MVT EltVT = VecVT.getVectorElementType();
11393 unsigned ElemsPerChunk = 128 / EltVT.getSizeInBits();
11395 //if (IdxVal >= NumElems/2)
11396 // IdxVal -= NumElems/2;
11397 IdxVal -= (IdxVal/ElemsPerChunk)*ElemsPerChunk;
11398 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec,
11399 DAG.getConstant(IdxVal, dl, MVT::i32));
11402 assert(VecVT.is128BitVector() && "Unexpected vector length");
11404 if (Subtarget->hasSSE41())
11405 if (SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG))
11408 MVT VT = Op.getSimpleValueType();
11409 // TODO: handle v16i8.
11410 if (VT.getSizeInBits() == 16) {
11411 SDValue Vec = Op.getOperand(0);
11412 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
11414 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
11415 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
11416 DAG.getBitcast(MVT::v4i32, Vec),
11417 Op.getOperand(1)));
11418 // Transform it so it match pextrw which produces a 32-bit result.
11419 MVT EltVT = MVT::i32;
11420 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
11421 Op.getOperand(0), Op.getOperand(1));
11422 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
11423 DAG.getValueType(VT));
11424 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
11427 if (VT.getSizeInBits() == 32) {
11428 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
11432 // SHUFPS the element to the lowest double word, then movss.
11433 int Mask[4] = { static_cast<int>(Idx), -1, -1, -1 };
11434 MVT VVT = Op.getOperand(0).getSimpleValueType();
11435 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
11436 DAG.getUNDEF(VVT), Mask);
11437 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
11438 DAG.getIntPtrConstant(0, dl));
11441 if (VT.getSizeInBits() == 64) {
11442 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
11443 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
11444 // to match extract_elt for f64.
11445 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
11449 // UNPCKHPD the element to the lowest double word, then movsd.
11450 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
11451 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
11452 int Mask[2] = { 1, -1 };
11453 MVT VVT = Op.getOperand(0).getSimpleValueType();
11454 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
11455 DAG.getUNDEF(VVT), Mask);
11456 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
11457 DAG.getIntPtrConstant(0, dl));
11463 /// Insert one bit to mask vector, like v16i1 or v8i1.
11464 /// AVX-512 feature.
11466 X86TargetLowering::InsertBitToMaskVector(SDValue Op, SelectionDAG &DAG) const {
11468 SDValue Vec = Op.getOperand(0);
11469 SDValue Elt = Op.getOperand(1);
11470 SDValue Idx = Op.getOperand(2);
11471 MVT VecVT = Vec.getSimpleValueType();
11473 if (!isa<ConstantSDNode>(Idx)) {
11474 // Non constant index. Extend source and destination,
11475 // insert element and then truncate the result.
11476 MVT ExtVecVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
11477 MVT ExtEltVT = (VecVT == MVT::v8i1 ? MVT::i64 : MVT::i32);
11478 SDValue ExtOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ExtVecVT,
11479 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVecVT, Vec),
11480 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtEltVT, Elt), Idx);
11481 return DAG.getNode(ISD::TRUNCATE, dl, VecVT, ExtOp);
11484 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
11485 SDValue EltInVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Elt);
11487 EltInVec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, EltInVec,
11488 DAG.getConstant(IdxVal, dl, MVT::i8));
11489 if (Vec.getOpcode() == ISD::UNDEF)
11491 return DAG.getNode(ISD::OR, dl, VecVT, Vec, EltInVec);
11494 SDValue X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op,
11495 SelectionDAG &DAG) const {
11496 MVT VT = Op.getSimpleValueType();
11497 MVT EltVT = VT.getVectorElementType();
11499 if (EltVT == MVT::i1)
11500 return InsertBitToMaskVector(Op, DAG);
11503 SDValue N0 = Op.getOperand(0);
11504 SDValue N1 = Op.getOperand(1);
11505 SDValue N2 = Op.getOperand(2);
11506 if (!isa<ConstantSDNode>(N2))
11508 auto *N2C = cast<ConstantSDNode>(N2);
11509 unsigned IdxVal = N2C->getZExtValue();
11511 // If the vector is wider than 128 bits, extract the 128-bit subvector, insert
11512 // into that, and then insert the subvector back into the result.
11513 if (VT.is256BitVector() || VT.is512BitVector()) {
11514 // With a 256-bit vector, we can insert into the zero element efficiently
11515 // using a blend if we have AVX or AVX2 and the right data type.
11516 if (VT.is256BitVector() && IdxVal == 0) {
11517 // TODO: It is worthwhile to cast integer to floating point and back
11518 // and incur a domain crossing penalty if that's what we'll end up
11519 // doing anyway after extracting to a 128-bit vector.
11520 if ((Subtarget->hasAVX() && (EltVT == MVT::f64 || EltVT == MVT::f32)) ||
11521 (Subtarget->hasAVX2() && EltVT == MVT::i32)) {
11522 SDValue N1Vec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, N1);
11523 N2 = DAG.getIntPtrConstant(1, dl);
11524 return DAG.getNode(X86ISD::BLENDI, dl, VT, N0, N1Vec, N2);
11528 // Get the desired 128-bit vector chunk.
11529 SDValue V = Extract128BitVector(N0, IdxVal, DAG, dl);
11531 // Insert the element into the desired chunk.
11532 unsigned NumEltsIn128 = 128 / EltVT.getSizeInBits();
11533 unsigned IdxIn128 = IdxVal - (IdxVal / NumEltsIn128) * NumEltsIn128;
11535 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V, N1,
11536 DAG.getConstant(IdxIn128, dl, MVT::i32));
11538 // Insert the changed part back into the bigger vector
11539 return Insert128BitVector(N0, V, IdxVal, DAG, dl);
11541 assert(VT.is128BitVector() && "Only 128-bit vector types should be left!");
11543 if (Subtarget->hasSSE41()) {
11544 if (EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) {
11546 if (VT == MVT::v8i16) {
11547 Opc = X86ISD::PINSRW;
11549 assert(VT == MVT::v16i8);
11550 Opc = X86ISD::PINSRB;
11553 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
11555 if (N1.getValueType() != MVT::i32)
11556 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
11557 if (N2.getValueType() != MVT::i32)
11558 N2 = DAG.getIntPtrConstant(IdxVal, dl);
11559 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
11562 if (EltVT == MVT::f32) {
11563 // Bits [7:6] of the constant are the source select. This will always be
11564 // zero here. The DAG Combiner may combine an extract_elt index into
11565 // these bits. For example (insert (extract, 3), 2) could be matched by
11566 // putting the '3' into bits [7:6] of X86ISD::INSERTPS.
11567 // Bits [5:4] of the constant are the destination select. This is the
11568 // value of the incoming immediate.
11569 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
11570 // combine either bitwise AND or insert of float 0.0 to set these bits.
11572 bool MinSize = DAG.getMachineFunction().getFunction()->optForMinSize();
11573 if (IdxVal == 0 && (!MinSize || !MayFoldLoad(N1))) {
11574 // If this is an insertion of 32-bits into the low 32-bits of
11575 // a vector, we prefer to generate a blend with immediate rather
11576 // than an insertps. Blends are simpler operations in hardware and so
11577 // will always have equal or better performance than insertps.
11578 // But if optimizing for size and there's a load folding opportunity,
11579 // generate insertps because blendps does not have a 32-bit memory
11581 N2 = DAG.getIntPtrConstant(1, dl);
11582 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
11583 return DAG.getNode(X86ISD::BLENDI, dl, VT, N0, N1, N2);
11585 N2 = DAG.getIntPtrConstant(IdxVal << 4, dl);
11586 // Create this as a scalar to vector..
11587 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
11588 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
11591 if (EltVT == MVT::i32 || EltVT == MVT::i64) {
11592 // PINSR* works with constant index.
11597 if (EltVT == MVT::i8)
11600 if (EltVT.getSizeInBits() == 16) {
11601 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
11602 // as its second argument.
11603 if (N1.getValueType() != MVT::i32)
11604 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
11605 if (N2.getValueType() != MVT::i32)
11606 N2 = DAG.getIntPtrConstant(IdxVal, dl);
11607 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);
11612 static SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) {
11614 MVT OpVT = Op.getSimpleValueType();
11616 // If this is a 256-bit vector result, first insert into a 128-bit
11617 // vector and then insert into the 256-bit vector.
11618 if (!OpVT.is128BitVector()) {
11619 // Insert into a 128-bit vector.
11620 unsigned SizeFactor = OpVT.getSizeInBits()/128;
11621 MVT VT128 = MVT::getVectorVT(OpVT.getVectorElementType(),
11622 OpVT.getVectorNumElements() / SizeFactor);
11624 Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Op.getOperand(0));
11626 // Insert the 128-bit vector.
11627 return Insert128BitVector(DAG.getUNDEF(OpVT), Op, 0, DAG, dl);
11630 if (OpVT == MVT::v1i64 &&
11631 Op.getOperand(0).getValueType() == MVT::i64)
11632 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
11634 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
11635 assert(OpVT.is128BitVector() && "Expected an SSE type!");
11636 return DAG.getBitcast(
11637 OpVT, DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, AnyExt));
11640 // Lower a node with an EXTRACT_SUBVECTOR opcode. This may result in
11641 // a simple subregister reference or explicit instructions to grab
11642 // upper bits of a vector.
11643 static SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
11644 SelectionDAG &DAG) {
11646 SDValue In = Op.getOperand(0);
11647 SDValue Idx = Op.getOperand(1);
11648 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
11649 MVT ResVT = Op.getSimpleValueType();
11650 MVT InVT = In.getSimpleValueType();
11652 if (Subtarget->hasFp256()) {
11653 if (ResVT.is128BitVector() &&
11654 (InVT.is256BitVector() || InVT.is512BitVector()) &&
11655 isa<ConstantSDNode>(Idx)) {
11656 return Extract128BitVector(In, IdxVal, DAG, dl);
11658 if (ResVT.is256BitVector() && InVT.is512BitVector() &&
11659 isa<ConstantSDNode>(Idx)) {
11660 return Extract256BitVector(In, IdxVal, DAG, dl);
11666 // Lower a node with an INSERT_SUBVECTOR opcode. This may result in a
11667 // simple superregister reference or explicit instructions to insert
11668 // the upper bits of a vector.
11669 static SDValue LowerINSERT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
11670 SelectionDAG &DAG) {
11671 if (!Subtarget->hasAVX())
11675 SDValue Vec = Op.getOperand(0);
11676 SDValue SubVec = Op.getOperand(1);
11677 SDValue Idx = Op.getOperand(2);
11679 if (!isa<ConstantSDNode>(Idx))
11682 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
11683 MVT OpVT = Op.getSimpleValueType();
11684 MVT SubVecVT = SubVec.getSimpleValueType();
11686 // Fold two 16-byte subvector loads into one 32-byte load:
11687 // (insert_subvector (insert_subvector undef, (load addr), 0),
11688 // (load addr + 16), Elts/2)
11690 if ((IdxVal == OpVT.getVectorNumElements() / 2) &&
11691 Vec.getOpcode() == ISD::INSERT_SUBVECTOR &&
11692 OpVT.is256BitVector() && SubVecVT.is128BitVector()) {
11693 auto *Idx2 = dyn_cast<ConstantSDNode>(Vec.getOperand(2));
11694 if (Idx2 && Idx2->getZExtValue() == 0) {
11695 SDValue SubVec2 = Vec.getOperand(1);
11696 // If needed, look through a bitcast to get to the load.
11697 if (SubVec2.getNode() && SubVec2.getOpcode() == ISD::BITCAST)
11698 SubVec2 = SubVec2.getOperand(0);
11700 if (auto *FirstLd = dyn_cast<LoadSDNode>(SubVec2)) {
11702 unsigned Alignment = FirstLd->getAlignment();
11703 unsigned AS = FirstLd->getAddressSpace();
11704 const X86TargetLowering *TLI = Subtarget->getTargetLowering();
11705 if (TLI->allowsMemoryAccess(*DAG.getContext(), DAG.getDataLayout(),
11706 OpVT, AS, Alignment, &Fast) && Fast) {
11707 SDValue Ops[] = { SubVec2, SubVec };
11708 if (SDValue Ld = EltsFromConsecutiveLoads(OpVT, Ops, dl, DAG, false))
11715 if ((OpVT.is256BitVector() || OpVT.is512BitVector()) &&
11716 SubVecVT.is128BitVector())
11717 return Insert128BitVector(Vec, SubVec, IdxVal, DAG, dl);
11719 if (OpVT.is512BitVector() && SubVecVT.is256BitVector())
11720 return Insert256BitVector(Vec, SubVec, IdxVal, DAG, dl);
11722 if (OpVT.getVectorElementType() == MVT::i1) {
11723 if (IdxVal == 0 && Vec.getOpcode() == ISD::UNDEF) // the operation is legal
11725 SDValue ZeroIdx = DAG.getIntPtrConstant(0, dl);
11726 SDValue Undef = DAG.getUNDEF(OpVT);
11727 unsigned NumElems = OpVT.getVectorNumElements();
11728 SDValue ShiftBits = DAG.getConstant(NumElems/2, dl, MVT::i8);
11730 if (IdxVal == OpVT.getVectorNumElements() / 2) {
11731 // Zero upper bits of the Vec
11732 Vec = DAG.getNode(X86ISD::VSHLI, dl, OpVT, Vec, ShiftBits);
11733 Vec = DAG.getNode(X86ISD::VSRLI, dl, OpVT, Vec, ShiftBits);
11735 SDValue Vec2 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, OpVT, Undef,
11737 Vec2 = DAG.getNode(X86ISD::VSHLI, dl, OpVT, Vec2, ShiftBits);
11738 return DAG.getNode(ISD::OR, dl, OpVT, Vec, Vec2);
11741 SDValue Vec2 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, OpVT, Undef,
11743 // Zero upper bits of the Vec2
11744 Vec2 = DAG.getNode(X86ISD::VSHLI, dl, OpVT, Vec2, ShiftBits);
11745 Vec2 = DAG.getNode(X86ISD::VSRLI, dl, OpVT, Vec2, ShiftBits);
11746 // Zero lower bits of the Vec
11747 Vec = DAG.getNode(X86ISD::VSRLI, dl, OpVT, Vec, ShiftBits);
11748 Vec = DAG.getNode(X86ISD::VSHLI, dl, OpVT, Vec, ShiftBits);
11749 // Merge them together
11750 return DAG.getNode(ISD::OR, dl, OpVT, Vec, Vec2);
11756 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
11757 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
11758 // one of the above mentioned nodes. It has to be wrapped because otherwise
11759 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
11760 // be used to form addressing mode. These wrapped nodes will be selected
11763 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
11764 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
11766 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
11767 // global base reg.
11768 unsigned char OpFlag = 0;
11769 unsigned WrapperKind = X86ISD::Wrapper;
11770 CodeModel::Model M = DAG.getTarget().getCodeModel();
11772 if (Subtarget->isPICStyleRIPRel() &&
11773 (M == CodeModel::Small || M == CodeModel::Kernel))
11774 WrapperKind = X86ISD::WrapperRIP;
11775 else if (Subtarget->isPICStyleGOT())
11776 OpFlag = X86II::MO_GOTOFF;
11777 else if (Subtarget->isPICStyleStubPIC())
11778 OpFlag = X86II::MO_PIC_BASE_OFFSET;
11780 auto PtrVT = getPointerTy(DAG.getDataLayout());
11781 SDValue Result = DAG.getTargetConstantPool(
11782 CP->getConstVal(), PtrVT, CP->getAlignment(), CP->getOffset(), OpFlag);
11784 Result = DAG.getNode(WrapperKind, DL, PtrVT, Result);
11785 // With PIC, the address is actually $g + Offset.
11788 DAG.getNode(ISD::ADD, DL, PtrVT,
11789 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), Result);
11795 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
11796 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
11798 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
11799 // global base reg.
11800 unsigned char OpFlag = 0;
11801 unsigned WrapperKind = X86ISD::Wrapper;
11802 CodeModel::Model M = DAG.getTarget().getCodeModel();
11804 if (Subtarget->isPICStyleRIPRel() &&
11805 (M == CodeModel::Small || M == CodeModel::Kernel))
11806 WrapperKind = X86ISD::WrapperRIP;
11807 else if (Subtarget->isPICStyleGOT())
11808 OpFlag = X86II::MO_GOTOFF;
11809 else if (Subtarget->isPICStyleStubPIC())
11810 OpFlag = X86II::MO_PIC_BASE_OFFSET;
11812 auto PtrVT = getPointerTy(DAG.getDataLayout());
11813 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, OpFlag);
11815 Result = DAG.getNode(WrapperKind, DL, PtrVT, Result);
11817 // With PIC, the address is actually $g + Offset.
11820 DAG.getNode(ISD::ADD, DL, PtrVT,
11821 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), Result);
11827 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const {
11828 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
11830 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
11831 // global base reg.
11832 unsigned char OpFlag = 0;
11833 unsigned WrapperKind = X86ISD::Wrapper;
11834 CodeModel::Model M = DAG.getTarget().getCodeModel();
11836 if (Subtarget->isPICStyleRIPRel() &&
11837 (M == CodeModel::Small || M == CodeModel::Kernel)) {
11838 if (Subtarget->isTargetDarwin() || Subtarget->isTargetELF())
11839 OpFlag = X86II::MO_GOTPCREL;
11840 WrapperKind = X86ISD::WrapperRIP;
11841 } else if (Subtarget->isPICStyleGOT()) {
11842 OpFlag = X86II::MO_GOT;
11843 } else if (Subtarget->isPICStyleStubPIC()) {
11844 OpFlag = X86II::MO_DARWIN_NONLAZY_PIC_BASE;
11845 } else if (Subtarget->isPICStyleStubNoDynamic()) {
11846 OpFlag = X86II::MO_DARWIN_NONLAZY;
11849 auto PtrVT = getPointerTy(DAG.getDataLayout());
11850 SDValue Result = DAG.getTargetExternalSymbol(Sym, PtrVT, OpFlag);
11853 Result = DAG.getNode(WrapperKind, DL, PtrVT, Result);
11855 // With PIC, the address is actually $g + Offset.
11856 if (DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
11857 !Subtarget->is64Bit()) {
11859 DAG.getNode(ISD::ADD, DL, PtrVT,
11860 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), Result);
11863 // For symbols that require a load from a stub to get the address, emit the
11865 if (isGlobalStubReference(OpFlag))
11866 Result = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), Result,
11867 MachinePointerInfo::getGOT(DAG.getMachineFunction()),
11868 false, false, false, 0);
11874 X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
11875 // Create the TargetBlockAddressAddress node.
11876 unsigned char OpFlags =
11877 Subtarget->ClassifyBlockAddressReference();
11878 CodeModel::Model M = DAG.getTarget().getCodeModel();
11879 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
11880 int64_t Offset = cast<BlockAddressSDNode>(Op)->getOffset();
11882 auto PtrVT = getPointerTy(DAG.getDataLayout());
11883 SDValue Result = DAG.getTargetBlockAddress(BA, PtrVT, Offset, OpFlags);
11885 if (Subtarget->isPICStyleRIPRel() &&
11886 (M == CodeModel::Small || M == CodeModel::Kernel))
11887 Result = DAG.getNode(X86ISD::WrapperRIP, dl, PtrVT, Result);
11889 Result = DAG.getNode(X86ISD::Wrapper, dl, PtrVT, Result);
11891 // With PIC, the address is actually $g + Offset.
11892 if (isGlobalRelativeToPICBase(OpFlags)) {
11893 Result = DAG.getNode(ISD::ADD, dl, PtrVT,
11894 DAG.getNode(X86ISD::GlobalBaseReg, dl, PtrVT), Result);
11901 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, SDLoc dl,
11902 int64_t Offset, SelectionDAG &DAG) const {
11903 // Create the TargetGlobalAddress node, folding in the constant
11904 // offset if it is legal.
11905 unsigned char OpFlags =
11906 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget());
11907 CodeModel::Model M = DAG.getTarget().getCodeModel();
11908 auto PtrVT = getPointerTy(DAG.getDataLayout());
11910 if (OpFlags == X86II::MO_NO_FLAG &&
11911 X86::isOffsetSuitableForCodeModel(Offset, M)) {
11912 // A direct static reference to a global.
11913 Result = DAG.getTargetGlobalAddress(GV, dl, PtrVT, Offset);
11916 Result = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, OpFlags);
11919 if (Subtarget->isPICStyleRIPRel() &&
11920 (M == CodeModel::Small || M == CodeModel::Kernel))
11921 Result = DAG.getNode(X86ISD::WrapperRIP, dl, PtrVT, Result);
11923 Result = DAG.getNode(X86ISD::Wrapper, dl, PtrVT, Result);
11925 // With PIC, the address is actually $g + Offset.
11926 if (isGlobalRelativeToPICBase(OpFlags)) {
11927 Result = DAG.getNode(ISD::ADD, dl, PtrVT,
11928 DAG.getNode(X86ISD::GlobalBaseReg, dl, PtrVT), Result);
11931 // For globals that require a load from a stub to get the address, emit the
11933 if (isGlobalStubReference(OpFlags))
11934 Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Result,
11935 MachinePointerInfo::getGOT(DAG.getMachineFunction()),
11936 false, false, false, 0);
11938 // If there was a non-zero offset that we didn't fold, create an explicit
11939 // addition for it.
11941 Result = DAG.getNode(ISD::ADD, dl, PtrVT, Result,
11942 DAG.getConstant(Offset, dl, PtrVT));
11948 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
11949 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
11950 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
11951 return LowerGlobalAddress(GV, SDLoc(Op), Offset, DAG);
11955 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
11956 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg,
11957 unsigned char OperandFlags, bool LocalDynamic = false) {
11958 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
11959 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
11961 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
11962 GA->getValueType(0),
11966 X86ISD::NodeType CallType = LocalDynamic ? X86ISD::TLSBASEADDR
11970 SDValue Ops[] = { Chain, TGA, *InFlag };
11971 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
11973 SDValue Ops[] = { Chain, TGA };
11974 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
11977 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
11978 MFI->setAdjustsStack(true);
11979 MFI->setHasCalls(true);
11981 SDValue Flag = Chain.getValue(1);
11982 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
11985 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
11987 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
11990 SDLoc dl(GA); // ? function entry point might be better
11991 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
11992 DAG.getNode(X86ISD::GlobalBaseReg,
11993 SDLoc(), PtrVT), InFlag);
11994 InFlag = Chain.getValue(1);
11996 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
11999 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
12001 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
12003 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT,
12004 X86::RAX, X86II::MO_TLSGD);
12007 static SDValue LowerToTLSLocalDynamicModel(GlobalAddressSDNode *GA,
12013 // Get the start address of the TLS block for this module.
12014 X86MachineFunctionInfo* MFI = DAG.getMachineFunction()
12015 .getInfo<X86MachineFunctionInfo>();
12016 MFI->incNumLocalDynamicTLSAccesses();
12020 Base = GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT, X86::RAX,
12021 X86II::MO_TLSLD, /*LocalDynamic=*/true);
12024 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
12025 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), InFlag);
12026 InFlag = Chain.getValue(1);
12027 Base = GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX,
12028 X86II::MO_TLSLDM, /*LocalDynamic=*/true);
12031 // Note: the CleanupLocalDynamicTLSPass will remove redundant computations
12035 unsigned char OperandFlags = X86II::MO_DTPOFF;
12036 unsigned WrapperKind = X86ISD::Wrapper;
12037 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
12038 GA->getValueType(0),
12039 GA->getOffset(), OperandFlags);
12040 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
12042 // Add x@dtpoff with the base.
12043 return DAG.getNode(ISD::ADD, dl, PtrVT, Offset, Base);
12046 // Lower ISD::GlobalTLSAddress using the "initial exec" or "local exec" model.
12047 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
12048 const EVT PtrVT, TLSModel::Model model,
12049 bool is64Bit, bool isPIC) {
12052 // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit).
12053 Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(*DAG.getContext(),
12054 is64Bit ? 257 : 256));
12056 SDValue ThreadPointer =
12057 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), DAG.getIntPtrConstant(0, dl),
12058 MachinePointerInfo(Ptr), false, false, false, 0);
12060 unsigned char OperandFlags = 0;
12061 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
12063 unsigned WrapperKind = X86ISD::Wrapper;
12064 if (model == TLSModel::LocalExec) {
12065 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
12066 } else if (model == TLSModel::InitialExec) {
12068 OperandFlags = X86II::MO_GOTTPOFF;
12069 WrapperKind = X86ISD::WrapperRIP;
12071 OperandFlags = isPIC ? X86II::MO_GOTNTPOFF : X86II::MO_INDNTPOFF;
12074 llvm_unreachable("Unexpected model");
12077 // emit "addl x@ntpoff,%eax" (local exec)
12078 // or "addl x@indntpoff,%eax" (initial exec)
12079 // or "addl x@gotntpoff(%ebx) ,%eax" (initial exec, 32-bit pic)
12081 DAG.getTargetGlobalAddress(GA->getGlobal(), dl, GA->getValueType(0),
12082 GA->getOffset(), OperandFlags);
12083 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
12085 if (model == TLSModel::InitialExec) {
12086 if (isPIC && !is64Bit) {
12087 Offset = DAG.getNode(ISD::ADD, dl, PtrVT,
12088 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT),
12092 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
12093 MachinePointerInfo::getGOT(DAG.getMachineFunction()),
12094 false, false, false, 0);
12097 // The address of the thread local variable is the add of the thread
12098 // pointer with the offset of the variable.
12099 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
12103 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
12105 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
12106 const GlobalValue *GV = GA->getGlobal();
12107 auto PtrVT = getPointerTy(DAG.getDataLayout());
12109 if (Subtarget->isTargetELF()) {
12110 if (DAG.getTarget().Options.EmulatedTLS)
12111 return LowerToTLSEmulatedModel(GA, DAG);
12112 TLSModel::Model model = DAG.getTarget().getTLSModel(GV);
12114 case TLSModel::GeneralDynamic:
12115 if (Subtarget->is64Bit())
12116 return LowerToTLSGeneralDynamicModel64(GA, DAG, PtrVT);
12117 return LowerToTLSGeneralDynamicModel32(GA, DAG, PtrVT);
12118 case TLSModel::LocalDynamic:
12119 return LowerToTLSLocalDynamicModel(GA, DAG, PtrVT,
12120 Subtarget->is64Bit());
12121 case TLSModel::InitialExec:
12122 case TLSModel::LocalExec:
12123 return LowerToTLSExecModel(GA, DAG, PtrVT, model, Subtarget->is64Bit(),
12124 DAG.getTarget().getRelocationModel() ==
12127 llvm_unreachable("Unknown TLS model.");
12130 if (Subtarget->isTargetDarwin()) {
12131 // Darwin only has one model of TLS. Lower to that.
12132 unsigned char OpFlag = 0;
12133 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ?
12134 X86ISD::WrapperRIP : X86ISD::Wrapper;
12136 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
12137 // global base reg.
12138 bool PIC32 = (DAG.getTarget().getRelocationModel() == Reloc::PIC_) &&
12139 !Subtarget->is64Bit();
12141 OpFlag = X86II::MO_TLVP_PIC_BASE;
12143 OpFlag = X86II::MO_TLVP;
12145 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL,
12146 GA->getValueType(0),
12147 GA->getOffset(), OpFlag);
12148 SDValue Offset = DAG.getNode(WrapperKind, DL, PtrVT, Result);
12150 // With PIC32, the address is actually $g + Offset.
12152 Offset = DAG.getNode(ISD::ADD, DL, PtrVT,
12153 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT),
12156 // Lowering the machine isd will make sure everything is in the right
12158 SDValue Chain = DAG.getEntryNode();
12159 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
12160 SDValue Args[] = { Chain, Offset };
12161 Chain = DAG.getNode(X86ISD::TLSCALL, DL, NodeTys, Args);
12163 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls.
12164 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
12165 MFI->setAdjustsStack(true);
12167 // And our return value (tls address) is in the standard call return value
12169 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
12170 return DAG.getCopyFromReg(Chain, DL, Reg, PtrVT, Chain.getValue(1));
12173 if (Subtarget->isTargetKnownWindowsMSVC() ||
12174 Subtarget->isTargetWindowsGNU()) {
12175 // Just use the implicit TLS architecture
12176 // Need to generate someting similar to:
12177 // mov rdx, qword [gs:abs 58H]; Load pointer to ThreadLocalStorage
12179 // mov ecx, dword [rel _tls_index]: Load index (from C runtime)
12180 // mov rcx, qword [rdx+rcx*8]
12181 // mov eax, .tls$:tlsvar
12182 // [rax+rcx] contains the address
12183 // Windows 64bit: gs:0x58
12184 // Windows 32bit: fs:__tls_array
12187 SDValue Chain = DAG.getEntryNode();
12189 // Get the Thread Pointer, which is %fs:__tls_array (32-bit) or
12190 // %gs:0x58 (64-bit). On MinGW, __tls_array is not available, so directly
12191 // use its literal value of 0x2C.
12192 Value *Ptr = Constant::getNullValue(Subtarget->is64Bit()
12193 ? Type::getInt8PtrTy(*DAG.getContext(),
12195 : Type::getInt32PtrTy(*DAG.getContext(),
12198 SDValue TlsArray = Subtarget->is64Bit()
12199 ? DAG.getIntPtrConstant(0x58, dl)
12200 : (Subtarget->isTargetWindowsGNU()
12201 ? DAG.getIntPtrConstant(0x2C, dl)
12202 : DAG.getExternalSymbol("_tls_array", PtrVT));
12204 SDValue ThreadPointer =
12205 DAG.getLoad(PtrVT, dl, Chain, TlsArray, MachinePointerInfo(Ptr), false,
12209 if (GV->getThreadLocalMode() == GlobalVariable::LocalExecTLSModel) {
12210 res = ThreadPointer;
12212 // Load the _tls_index variable
12213 SDValue IDX = DAG.getExternalSymbol("_tls_index", PtrVT);
12214 if (Subtarget->is64Bit())
12215 IDX = DAG.getExtLoad(ISD::ZEXTLOAD, dl, PtrVT, Chain, IDX,
12216 MachinePointerInfo(), MVT::i32, false, false,
12219 IDX = DAG.getLoad(PtrVT, dl, Chain, IDX, MachinePointerInfo(), false,
12222 auto &DL = DAG.getDataLayout();
12224 DAG.getConstant(Log2_64_Ceil(DL.getPointerSize()), dl, PtrVT);
12225 IDX = DAG.getNode(ISD::SHL, dl, PtrVT, IDX, Scale);
12227 res = DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, IDX);
12230 res = DAG.getLoad(PtrVT, dl, Chain, res, MachinePointerInfo(), false, false,
12233 // Get the offset of start of .tls section
12234 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
12235 GA->getValueType(0),
12236 GA->getOffset(), X86II::MO_SECREL);
12237 SDValue Offset = DAG.getNode(X86ISD::Wrapper, dl, PtrVT, TGA);
12239 // The address of the thread local variable is the add of the thread
12240 // pointer with the offset of the variable.
12241 return DAG.getNode(ISD::ADD, dl, PtrVT, res, Offset);
12244 llvm_unreachable("TLS not implemented for this target.");
12247 /// LowerShiftParts - Lower SRA_PARTS and friends, which return two i32 values
12248 /// and take a 2 x i32 value to shift plus a shift amount.
12249 static SDValue LowerShiftParts(SDValue Op, SelectionDAG &DAG) {
12250 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
12251 MVT VT = Op.getSimpleValueType();
12252 unsigned VTBits = VT.getSizeInBits();
12254 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
12255 SDValue ShOpLo = Op.getOperand(0);
12256 SDValue ShOpHi = Op.getOperand(1);
12257 SDValue ShAmt = Op.getOperand(2);
12258 // X86ISD::SHLD and X86ISD::SHRD have defined overflow behavior but the
12259 // generic ISD nodes haven't. Insert an AND to be safe, it's optimized away
12261 SDValue SafeShAmt = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
12262 DAG.getConstant(VTBits - 1, dl, MVT::i8));
12263 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
12264 DAG.getConstant(VTBits - 1, dl, MVT::i8))
12265 : DAG.getConstant(0, dl, VT);
12267 SDValue Tmp2, Tmp3;
12268 if (Op.getOpcode() == ISD::SHL_PARTS) {
12269 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
12270 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, SafeShAmt);
12272 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
12273 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, SafeShAmt);
12276 // If the shift amount is larger or equal than the width of a part we can't
12277 // rely on the results of shld/shrd. Insert a test and select the appropriate
12278 // values for large shift amounts.
12279 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
12280 DAG.getConstant(VTBits, dl, MVT::i8));
12281 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
12282 AndNode, DAG.getConstant(0, dl, MVT::i8));
12285 SDValue CC = DAG.getConstant(X86::COND_NE, dl, MVT::i8);
12286 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
12287 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
12289 if (Op.getOpcode() == ISD::SHL_PARTS) {
12290 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
12291 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
12293 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
12294 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
12297 SDValue Ops[2] = { Lo, Hi };
12298 return DAG.getMergeValues(Ops, dl);
12301 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op,
12302 SelectionDAG &DAG) const {
12303 SDValue Src = Op.getOperand(0);
12304 MVT SrcVT = Src.getSimpleValueType();
12305 MVT VT = Op.getSimpleValueType();
12308 if (SrcVT.isVector()) {
12309 if (SrcVT == MVT::v2i32 && VT == MVT::v2f64) {
12310 return DAG.getNode(X86ISD::CVTDQ2PD, dl, VT,
12311 DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v4i32, Src,
12312 DAG.getUNDEF(SrcVT)));
12314 if (SrcVT.getVectorElementType() == MVT::i1) {
12315 MVT IntegerVT = MVT::getVectorVT(MVT::i32, SrcVT.getVectorNumElements());
12316 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
12317 DAG.getNode(ISD::SIGN_EXTEND, dl, IntegerVT, Src));
12322 assert(SrcVT <= MVT::i64 && SrcVT >= MVT::i16 &&
12323 "Unknown SINT_TO_FP to lower!");
12325 // These are really Legal; return the operand so the caller accepts it as
12327 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
12329 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
12330 Subtarget->is64Bit()) {
12334 unsigned Size = SrcVT.getSizeInBits()/8;
12335 MachineFunction &MF = DAG.getMachineFunction();
12336 auto PtrVT = getPointerTy(MF.getDataLayout());
12337 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false);
12338 SDValue StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
12339 SDValue Chain = DAG.getStore(
12340 DAG.getEntryNode(), dl, Op.getOperand(0), StackSlot,
12341 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SSFI), false,
12343 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
12346 SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
12348 SelectionDAG &DAG) const {
12352 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
12354 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Glue);
12356 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
12358 unsigned ByteSize = SrcVT.getSizeInBits()/8;
12360 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(StackSlot);
12361 MachineMemOperand *MMO;
12363 int SSFI = FI->getIndex();
12364 MMO = DAG.getMachineFunction().getMachineMemOperand(
12365 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SSFI),
12366 MachineMemOperand::MOLoad, ByteSize, ByteSize);
12368 MMO = cast<LoadSDNode>(StackSlot)->getMemOperand();
12369 StackSlot = StackSlot.getOperand(1);
12371 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) };
12372 SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG :
12374 Tys, Ops, SrcVT, MMO);
12377 Chain = Result.getValue(1);
12378 SDValue InFlag = Result.getValue(2);
12380 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
12381 // shouldn't be necessary except that RFP cannot be live across
12382 // multiple blocks. When stackifier is fixed, they can be uncoupled.
12383 MachineFunction &MF = DAG.getMachineFunction();
12384 unsigned SSFISize = Op.getValueType().getSizeInBits()/8;
12385 int SSFI = MF.getFrameInfo()->CreateStackObject(SSFISize, SSFISize, false);
12386 auto PtrVT = getPointerTy(MF.getDataLayout());
12387 SDValue StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
12388 Tys = DAG.getVTList(MVT::Other);
12390 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag
12392 MachineMemOperand *MMO = DAG.getMachineFunction().getMachineMemOperand(
12393 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SSFI),
12394 MachineMemOperand::MOStore, SSFISize, SSFISize);
12396 Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys,
12397 Ops, Op.getValueType(), MMO);
12398 Result = DAG.getLoad(
12399 Op.getValueType(), DL, Chain, StackSlot,
12400 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SSFI),
12401 false, false, false, 0);
12407 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
12408 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op,
12409 SelectionDAG &DAG) const {
12410 // This algorithm is not obvious. Here it is what we're trying to output:
12413 punpckldq (c0), %xmm0 // c0: (uint4){ 0x43300000U, 0x45300000U, 0U, 0U }
12414 subpd (c1), %xmm0 // c1: (double2){ 0x1.0p52, 0x1.0p52 * 0x1.0p32 }
12416 haddpd %xmm0, %xmm0
12418 pshufd $0x4e, %xmm0, %xmm1
12424 LLVMContext *Context = DAG.getContext();
12426 // Build some magic constants.
12427 static const uint32_t CV0[] = { 0x43300000, 0x45300000, 0, 0 };
12428 Constant *C0 = ConstantDataVector::get(*Context, CV0);
12429 auto PtrVT = getPointerTy(DAG.getDataLayout());
12430 SDValue CPIdx0 = DAG.getConstantPool(C0, PtrVT, 16);
12432 SmallVector<Constant*,2> CV1;
12434 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
12435 APInt(64, 0x4330000000000000ULL))));
12437 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
12438 APInt(64, 0x4530000000000000ULL))));
12439 Constant *C1 = ConstantVector::get(CV1);
12440 SDValue CPIdx1 = DAG.getConstantPool(C1, PtrVT, 16);
12442 // Load the 64-bit value into an XMM register.
12443 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
12446 DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
12447 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()),
12448 false, false, false, 16);
12450 getUnpackl(DAG, dl, MVT::v4i32, DAG.getBitcast(MVT::v4i32, XR1), CLod0);
12453 DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
12454 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()),
12455 false, false, false, 16);
12456 SDValue XR2F = DAG.getBitcast(MVT::v2f64, Unpck1);
12457 // TODO: Are there any fast-math-flags to propagate here?
12458 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
12461 if (Subtarget->hasSSE3()) {
12462 // FIXME: The 'haddpd' instruction may be slower than 'movhlps + addsd'.
12463 Result = DAG.getNode(X86ISD::FHADD, dl, MVT::v2f64, Sub, Sub);
12465 SDValue S2F = DAG.getBitcast(MVT::v4i32, Sub);
12466 SDValue Shuffle = getTargetShuffleNode(X86ISD::PSHUFD, dl, MVT::v4i32,
12468 Result = DAG.getNode(ISD::FADD, dl, MVT::v2f64,
12469 DAG.getBitcast(MVT::v2f64, Shuffle), Sub);
12472 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Result,
12473 DAG.getIntPtrConstant(0, dl));
12476 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
12477 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op,
12478 SelectionDAG &DAG) const {
12480 // FP constant to bias correct the final result.
12481 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL), dl,
12484 // Load the 32-bit value into an XMM register.
12485 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
12488 // Zero out the upper parts of the register.
12489 Load = getShuffleVectorZeroOrUndef(Load, 0, true, Subtarget, DAG);
12491 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
12492 DAG.getBitcast(MVT::v2f64, Load),
12493 DAG.getIntPtrConstant(0, dl));
12495 // Or the load with the bias.
12496 SDValue Or = DAG.getNode(
12497 ISD::OR, dl, MVT::v2i64,
12498 DAG.getBitcast(MVT::v2i64,
12499 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, Load)),
12500 DAG.getBitcast(MVT::v2i64,
12501 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, Bias)));
12503 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
12504 DAG.getBitcast(MVT::v2f64, Or), DAG.getIntPtrConstant(0, dl));
12506 // Subtract the bias.
12507 // TODO: Are there any fast-math-flags to propagate here?
12508 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
12510 // Handle final rounding.
12511 EVT DestVT = Op.getValueType();
12513 if (DestVT.bitsLT(MVT::f64))
12514 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
12515 DAG.getIntPtrConstant(0, dl));
12516 if (DestVT.bitsGT(MVT::f64))
12517 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
12519 // Handle final rounding.
12523 static SDValue lowerUINT_TO_FP_vXi32(SDValue Op, SelectionDAG &DAG,
12524 const X86Subtarget &Subtarget) {
12525 // The algorithm is the following:
12526 // #ifdef __SSE4_1__
12527 // uint4 lo = _mm_blend_epi16( v, (uint4) 0x4b000000, 0xaa);
12528 // uint4 hi = _mm_blend_epi16( _mm_srli_epi32(v,16),
12529 // (uint4) 0x53000000, 0xaa);
12531 // uint4 lo = (v & (uint4) 0xffff) | (uint4) 0x4b000000;
12532 // uint4 hi = (v >> 16) | (uint4) 0x53000000;
12534 // float4 fhi = (float4) hi - (0x1.0p39f + 0x1.0p23f);
12535 // return (float4) lo + fhi;
12537 // We shouldn't use it when unsafe-fp-math is enabled though: we might later
12538 // reassociate the two FADDs, and if we do that, the algorithm fails
12539 // spectacularly (PR24512).
12540 // FIXME: If we ever have some kind of Machine FMF, this should be marked
12541 // as non-fast and always be enabled. Why isn't SDAG FMF enough? Because
12542 // there's also the MachineCombiner reassociations happening on Machine IR.
12543 if (DAG.getTarget().Options.UnsafeFPMath)
12547 SDValue V = Op->getOperand(0);
12548 EVT VecIntVT = V.getValueType();
12549 bool Is128 = VecIntVT == MVT::v4i32;
12550 EVT VecFloatVT = Is128 ? MVT::v4f32 : MVT::v8f32;
12551 // If we convert to something else than the supported type, e.g., to v4f64,
12553 if (VecFloatVT != Op->getValueType(0))
12556 unsigned NumElts = VecIntVT.getVectorNumElements();
12557 assert((VecIntVT == MVT::v4i32 || VecIntVT == MVT::v8i32) &&
12558 "Unsupported custom type");
12559 assert(NumElts <= 8 && "The size of the constant array must be fixed");
12561 // In the #idef/#else code, we have in common:
12562 // - The vector of constants:
12568 // Create the splat vector for 0x4b000000.
12569 SDValue CstLow = DAG.getConstant(0x4b000000, DL, MVT::i32);
12570 SDValue CstLowArray[] = {CstLow, CstLow, CstLow, CstLow,
12571 CstLow, CstLow, CstLow, CstLow};
12572 SDValue VecCstLow = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
12573 makeArrayRef(&CstLowArray[0], NumElts));
12574 // Create the splat vector for 0x53000000.
12575 SDValue CstHigh = DAG.getConstant(0x53000000, DL, MVT::i32);
12576 SDValue CstHighArray[] = {CstHigh, CstHigh, CstHigh, CstHigh,
12577 CstHigh, CstHigh, CstHigh, CstHigh};
12578 SDValue VecCstHigh = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
12579 makeArrayRef(&CstHighArray[0], NumElts));
12581 // Create the right shift.
12582 SDValue CstShift = DAG.getConstant(16, DL, MVT::i32);
12583 SDValue CstShiftArray[] = {CstShift, CstShift, CstShift, CstShift,
12584 CstShift, CstShift, CstShift, CstShift};
12585 SDValue VecCstShift = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
12586 makeArrayRef(&CstShiftArray[0], NumElts));
12587 SDValue HighShift = DAG.getNode(ISD::SRL, DL, VecIntVT, V, VecCstShift);
12590 if (Subtarget.hasSSE41()) {
12591 EVT VecI16VT = Is128 ? MVT::v8i16 : MVT::v16i16;
12592 // uint4 lo = _mm_blend_epi16( v, (uint4) 0x4b000000, 0xaa);
12593 SDValue VecCstLowBitcast = DAG.getBitcast(VecI16VT, VecCstLow);
12594 SDValue VecBitcast = DAG.getBitcast(VecI16VT, V);
12595 // Low will be bitcasted right away, so do not bother bitcasting back to its
12597 Low = DAG.getNode(X86ISD::BLENDI, DL, VecI16VT, VecBitcast,
12598 VecCstLowBitcast, DAG.getConstant(0xaa, DL, MVT::i32));
12599 // uint4 hi = _mm_blend_epi16( _mm_srli_epi32(v,16),
12600 // (uint4) 0x53000000, 0xaa);
12601 SDValue VecCstHighBitcast = DAG.getBitcast(VecI16VT, VecCstHigh);
12602 SDValue VecShiftBitcast = DAG.getBitcast(VecI16VT, HighShift);
12603 // High will be bitcasted right away, so do not bother bitcasting back to
12604 // its original type.
12605 High = DAG.getNode(X86ISD::BLENDI, DL, VecI16VT, VecShiftBitcast,
12606 VecCstHighBitcast, DAG.getConstant(0xaa, DL, MVT::i32));
12608 SDValue CstMask = DAG.getConstant(0xffff, DL, MVT::i32);
12609 SDValue VecCstMask = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT, CstMask,
12610 CstMask, CstMask, CstMask);
12611 // uint4 lo = (v & (uint4) 0xffff) | (uint4) 0x4b000000;
12612 SDValue LowAnd = DAG.getNode(ISD::AND, DL, VecIntVT, V, VecCstMask);
12613 Low = DAG.getNode(ISD::OR, DL, VecIntVT, LowAnd, VecCstLow);
12615 // uint4 hi = (v >> 16) | (uint4) 0x53000000;
12616 High = DAG.getNode(ISD::OR, DL, VecIntVT, HighShift, VecCstHigh);
12619 // Create the vector constant for -(0x1.0p39f + 0x1.0p23f).
12620 SDValue CstFAdd = DAG.getConstantFP(
12621 APFloat(APFloat::IEEEsingle, APInt(32, 0xD3000080)), DL, MVT::f32);
12622 SDValue CstFAddArray[] = {CstFAdd, CstFAdd, CstFAdd, CstFAdd,
12623 CstFAdd, CstFAdd, CstFAdd, CstFAdd};
12624 SDValue VecCstFAdd = DAG.getNode(ISD::BUILD_VECTOR, DL, VecFloatVT,
12625 makeArrayRef(&CstFAddArray[0], NumElts));
12627 // float4 fhi = (float4) hi - (0x1.0p39f + 0x1.0p23f);
12628 SDValue HighBitcast = DAG.getBitcast(VecFloatVT, High);
12629 // TODO: Are there any fast-math-flags to propagate here?
12631 DAG.getNode(ISD::FADD, DL, VecFloatVT, HighBitcast, VecCstFAdd);
12632 // return (float4) lo + fhi;
12633 SDValue LowBitcast = DAG.getBitcast(VecFloatVT, Low);
12634 return DAG.getNode(ISD::FADD, DL, VecFloatVT, LowBitcast, FHigh);
12637 SDValue X86TargetLowering::lowerUINT_TO_FP_vec(SDValue Op,
12638 SelectionDAG &DAG) const {
12639 SDValue N0 = Op.getOperand(0);
12640 MVT SVT = N0.getSimpleValueType();
12643 switch (SVT.SimpleTy) {
12645 llvm_unreachable("Custom UINT_TO_FP is not supported!");
12650 MVT NVT = MVT::getVectorVT(MVT::i32, SVT.getVectorNumElements());
12651 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
12652 DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, N0));
12656 return lowerUINT_TO_FP_vXi32(Op, DAG, *Subtarget);
12659 if (Subtarget->hasAVX512())
12660 return DAG.getNode(ISD::UINT_TO_FP, dl, Op.getValueType(),
12661 DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v16i32, N0));
12663 llvm_unreachable(nullptr);
12666 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op,
12667 SelectionDAG &DAG) const {
12668 SDValue N0 = Op.getOperand(0);
12670 auto PtrVT = getPointerTy(DAG.getDataLayout());
12672 if (Op.getValueType().isVector())
12673 return lowerUINT_TO_FP_vec(Op, DAG);
12675 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't
12676 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
12677 // the optimization here.
12678 if (DAG.SignBitIsZero(N0))
12679 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
12681 MVT SrcVT = N0.getSimpleValueType();
12682 MVT DstVT = Op.getSimpleValueType();
12684 if (Subtarget->hasAVX512() && isScalarFPTypeInSSEReg(DstVT) &&
12685 (SrcVT == MVT::i32 || (SrcVT == MVT::i64 && Subtarget->is64Bit()))) {
12686 // Conversions from unsigned i32 to f32/f64 are legal,
12687 // using VCVTUSI2SS/SD. Same for i64 in 64-bit mode.
12691 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64)
12692 return LowerUINT_TO_FP_i64(Op, DAG);
12693 if (SrcVT == MVT::i32 && X86ScalarSSEf64)
12694 return LowerUINT_TO_FP_i32(Op, DAG);
12695 if (Subtarget->is64Bit() && SrcVT == MVT::i64 && DstVT == MVT::f32)
12698 // Make a 64-bit buffer, and use it to build an FILD.
12699 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
12700 if (SrcVT == MVT::i32) {
12701 SDValue WordOff = DAG.getConstant(4, dl, PtrVT);
12702 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl, PtrVT, StackSlot, WordOff);
12703 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
12704 StackSlot, MachinePointerInfo(),
12706 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, dl, MVT::i32),
12707 OffsetSlot, MachinePointerInfo(),
12709 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
12713 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP");
12714 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
12715 StackSlot, MachinePointerInfo(),
12717 // For i64 source, we need to add the appropriate power of 2 if the input
12718 // was negative. This is the same as the optimization in
12719 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here,
12720 // we must be careful to do the computation in x87 extended precision, not
12721 // in SSE. (The generic code can't know it's OK to do this, or how to.)
12722 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex();
12723 MachineMemOperand *MMO = DAG.getMachineFunction().getMachineMemOperand(
12724 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SSFI),
12725 MachineMemOperand::MOLoad, 8, 8);
12727 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other);
12728 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) };
12729 SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops,
12732 APInt FF(32, 0x5F800000ULL);
12734 // Check whether the sign bit is set.
12735 SDValue SignSet = DAG.getSetCC(
12736 dl, getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), MVT::i64),
12737 Op.getOperand(0), DAG.getConstant(0, dl, MVT::i64), ISD::SETLT);
12739 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
12740 SDValue FudgePtr = DAG.getConstantPool(
12741 ConstantInt::get(*DAG.getContext(), FF.zext(64)), PtrVT);
12743 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
12744 SDValue Zero = DAG.getIntPtrConstant(0, dl);
12745 SDValue Four = DAG.getIntPtrConstant(4, dl);
12746 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
12748 FudgePtr = DAG.getNode(ISD::ADD, dl, PtrVT, FudgePtr, Offset);
12750 // Load the value out, extending it from f32 to f80.
12751 // FIXME: Avoid the extend by constructing the right constant pool?
12752 SDValue Fudge = DAG.getExtLoad(
12753 ISD::EXTLOAD, dl, MVT::f80, DAG.getEntryNode(), FudgePtr,
12754 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()), MVT::f32,
12755 false, false, false, 4);
12756 // Extend everything to 80 bits to force it to be done on x87.
12757 // TODO: Are there any fast-math-flags to propagate here?
12758 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge);
12759 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add,
12760 DAG.getIntPtrConstant(0, dl));
12763 // If the given FP_TO_SINT (IsSigned) or FP_TO_UINT (!IsSigned) operation
12764 // is legal, or has an fp128 or f16 source (which needs to be promoted to f32),
12765 // just return an <SDValue(), SDValue()> pair.
12766 // Otherwise it is assumed to be a conversion from one of f32, f64 or f80
12767 // to i16, i32 or i64, and we lower it to a legal sequence.
12768 // If lowered to the final integer result we return a <result, SDValue()> pair.
12769 // Otherwise we lower it to a sequence ending with a FIST, return a
12770 // <FIST, StackSlot> pair, and the caller is responsible for loading
12771 // the final integer result from StackSlot.
12772 std::pair<SDValue,SDValue>
12773 X86TargetLowering::FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG,
12774 bool IsSigned, bool IsReplace) const {
12777 EVT DstTy = Op.getValueType();
12778 EVT TheVT = Op.getOperand(0).getValueType();
12779 auto PtrVT = getPointerTy(DAG.getDataLayout());
12781 if (TheVT != MVT::f32 && TheVT != MVT::f64 && TheVT != MVT::f80) {
12782 // f16 must be promoted before using the lowering in this routine.
12783 // fp128 does not use this lowering.
12784 return std::make_pair(SDValue(), SDValue());
12787 // If using FIST to compute an unsigned i64, we'll need some fixup
12788 // to handle values above the maximum signed i64. A FIST is always
12789 // used for the 32-bit subtarget, but also for f80 on a 64-bit target.
12790 bool UnsignedFixup = !IsSigned &&
12791 DstTy == MVT::i64 &&
12792 (!Subtarget->is64Bit() ||
12793 !isScalarFPTypeInSSEReg(TheVT));
12795 if (!IsSigned && DstTy != MVT::i64 && !Subtarget->hasAVX512()) {
12796 // Replace the fp-to-uint32 operation with an fp-to-sint64 FIST.
12797 // The low 32 bits of the fist result will have the correct uint32 result.
12798 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
12802 assert(DstTy.getSimpleVT() <= MVT::i64 &&
12803 DstTy.getSimpleVT() >= MVT::i16 &&
12804 "Unknown FP_TO_INT to lower!");
12806 // These are really Legal.
12807 if (DstTy == MVT::i32 &&
12808 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
12809 return std::make_pair(SDValue(), SDValue());
12810 if (Subtarget->is64Bit() &&
12811 DstTy == MVT::i64 &&
12812 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
12813 return std::make_pair(SDValue(), SDValue());
12815 // We lower FP->int64 into FISTP64 followed by a load from a temporary
12817 MachineFunction &MF = DAG.getMachineFunction();
12818 unsigned MemSize = DstTy.getSizeInBits()/8;
12819 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
12820 SDValue StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
12823 switch (DstTy.getSimpleVT().SimpleTy) {
12824 default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
12825 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
12826 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
12827 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
12830 SDValue Chain = DAG.getEntryNode();
12831 SDValue Value = Op.getOperand(0);
12832 SDValue Adjust; // 0x0 or 0x80000000, for result sign bit adjustment.
12834 if (UnsignedFixup) {
12836 // Conversion to unsigned i64 is implemented with a select,
12837 // depending on whether the source value fits in the range
12838 // of a signed i64. Let Thresh be the FP equivalent of
12839 // 0x8000000000000000ULL.
12841 // Adjust i32 = (Value < Thresh) ? 0 : 0x80000000;
12842 // FistSrc = (Value < Thresh) ? Value : (Value - Thresh);
12843 // Fist-to-mem64 FistSrc
12844 // Add 0 or 0x800...0ULL to the 64-bit result, which is equivalent
12845 // to XOR'ing the high 32 bits with Adjust.
12847 // Being a power of 2, Thresh is exactly representable in all FP formats.
12848 // For X87 we'd like to use the smallest FP type for this constant, but
12849 // for DAG type consistency we have to match the FP operand type.
12851 APFloat Thresh(APFloat::IEEEsingle, APInt(32, 0x5f000000));
12852 LLVM_ATTRIBUTE_UNUSED APFloat::opStatus Status = APFloat::opOK;
12853 bool LosesInfo = false;
12854 if (TheVT == MVT::f64)
12855 // The rounding mode is irrelevant as the conversion should be exact.
12856 Status = Thresh.convert(APFloat::IEEEdouble, APFloat::rmNearestTiesToEven,
12858 else if (TheVT == MVT::f80)
12859 Status = Thresh.convert(APFloat::x87DoubleExtended,
12860 APFloat::rmNearestTiesToEven, &LosesInfo);
12862 assert(Status == APFloat::opOK && !LosesInfo &&
12863 "FP conversion should have been exact");
12865 SDValue ThreshVal = DAG.getConstantFP(Thresh, DL, TheVT);
12867 SDValue Cmp = DAG.getSetCC(DL,
12868 getSetCCResultType(DAG.getDataLayout(),
12869 *DAG.getContext(), TheVT),
12870 Value, ThreshVal, ISD::SETLT);
12871 Adjust = DAG.getSelect(DL, MVT::i32, Cmp,
12872 DAG.getConstant(0, DL, MVT::i32),
12873 DAG.getConstant(0x80000000, DL, MVT::i32));
12874 SDValue Sub = DAG.getNode(ISD::FSUB, DL, TheVT, Value, ThreshVal);
12875 Cmp = DAG.getSetCC(DL, getSetCCResultType(DAG.getDataLayout(),
12876 *DAG.getContext(), TheVT),
12877 Value, ThreshVal, ISD::SETLT);
12878 Value = DAG.getSelect(DL, TheVT, Cmp, Value, Sub);
12881 // FIXME This causes a redundant load/store if the SSE-class value is already
12882 // in memory, such as if it is on the callstack.
12883 if (isScalarFPTypeInSSEReg(TheVT)) {
12884 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
12885 Chain = DAG.getStore(Chain, DL, Value, StackSlot,
12886 MachinePointerInfo::getFixedStack(MF, SSFI), false,
12888 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
12890 Chain, StackSlot, DAG.getValueType(TheVT)
12893 MachineMemOperand *MMO =
12894 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(MF, SSFI),
12895 MachineMemOperand::MOLoad, MemSize, MemSize);
12896 Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops, DstTy, MMO);
12897 Chain = Value.getValue(1);
12898 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
12899 StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
12902 MachineMemOperand *MMO =
12903 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(MF, SSFI),
12904 MachineMemOperand::MOStore, MemSize, MemSize);
12906 if (UnsignedFixup) {
12908 // Insert the FIST, load its result as two i32's,
12909 // and XOR the high i32 with Adjust.
12911 SDValue FistOps[] = { Chain, Value, StackSlot };
12912 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
12913 FistOps, DstTy, MMO);
12915 SDValue Low32 = DAG.getLoad(MVT::i32, DL, FIST, StackSlot,
12916 MachinePointerInfo(),
12917 false, false, false, 0);
12918 SDValue HighAddr = DAG.getNode(ISD::ADD, DL, PtrVT, StackSlot,
12919 DAG.getConstant(4, DL, PtrVT));
12921 SDValue High32 = DAG.getLoad(MVT::i32, DL, FIST, HighAddr,
12922 MachinePointerInfo(),
12923 false, false, false, 0);
12924 High32 = DAG.getNode(ISD::XOR, DL, MVT::i32, High32, Adjust);
12926 if (Subtarget->is64Bit()) {
12927 // Join High32 and Low32 into a 64-bit result.
12928 // (High32 << 32) | Low32
12929 Low32 = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64, Low32);
12930 High32 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, High32);
12931 High32 = DAG.getNode(ISD::SHL, DL, MVT::i64, High32,
12932 DAG.getConstant(32, DL, MVT::i8));
12933 SDValue Result = DAG.getNode(ISD::OR, DL, MVT::i64, High32, Low32);
12934 return std::make_pair(Result, SDValue());
12937 SDValue ResultOps[] = { Low32, High32 };
12939 SDValue pair = IsReplace
12940 ? DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, ResultOps)
12941 : DAG.getMergeValues(ResultOps, DL);
12942 return std::make_pair(pair, SDValue());
12944 // Build the FP_TO_INT*_IN_MEM
12945 SDValue Ops[] = { Chain, Value, StackSlot };
12946 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
12948 return std::make_pair(FIST, StackSlot);
12952 static SDValue LowerAVXExtend(SDValue Op, SelectionDAG &DAG,
12953 const X86Subtarget *Subtarget) {
12954 MVT VT = Op->getSimpleValueType(0);
12955 SDValue In = Op->getOperand(0);
12956 MVT InVT = In.getSimpleValueType();
12959 if (VT.is512BitVector() || InVT.getScalarType() == MVT::i1)
12960 return DAG.getNode(ISD::ZERO_EXTEND, dl, VT, In);
12962 // Optimize vectors in AVX mode:
12965 // Use vpunpcklwd for 4 lower elements v8i16 -> v4i32.
12966 // Use vpunpckhwd for 4 upper elements v8i16 -> v4i32.
12967 // Concat upper and lower parts.
12970 // Use vpunpckldq for 4 lower elements v4i32 -> v2i64.
12971 // Use vpunpckhdq for 4 upper elements v4i32 -> v2i64.
12972 // Concat upper and lower parts.
12975 if (((VT != MVT::v16i16) || (InVT != MVT::v16i8)) &&
12976 ((VT != MVT::v8i32) || (InVT != MVT::v8i16)) &&
12977 ((VT != MVT::v4i64) || (InVT != MVT::v4i32)))
12980 if (Subtarget->hasInt256())
12981 return DAG.getNode(X86ISD::VZEXT, dl, VT, In);
12983 SDValue ZeroVec = getZeroVector(InVT, Subtarget, DAG, dl);
12984 SDValue Undef = DAG.getUNDEF(InVT);
12985 bool NeedZero = Op.getOpcode() == ISD::ZERO_EXTEND;
12986 SDValue OpLo = getUnpackl(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
12987 SDValue OpHi = getUnpackh(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
12989 MVT HVT = MVT::getVectorVT(VT.getVectorElementType(),
12990 VT.getVectorNumElements()/2);
12992 OpLo = DAG.getBitcast(HVT, OpLo);
12993 OpHi = DAG.getBitcast(HVT, OpHi);
12995 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
12998 static SDValue LowerZERO_EXTEND_AVX512(SDValue Op,
12999 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
13000 MVT VT = Op->getSimpleValueType(0);
13001 SDValue In = Op->getOperand(0);
13002 MVT InVT = In.getSimpleValueType();
13004 unsigned int NumElts = VT.getVectorNumElements();
13005 if (NumElts != 8 && NumElts != 16 && !Subtarget->hasBWI())
13008 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1)
13009 return DAG.getNode(X86ISD::VZEXT, DL, VT, In);
13011 assert(InVT.getVectorElementType() == MVT::i1);
13012 MVT ExtVT = NumElts == 8 ? MVT::v8i64 : MVT::v16i32;
13014 DAG.getConstant(APInt(ExtVT.getScalarSizeInBits(), 1), DL, ExtVT);
13016 DAG.getConstant(APInt::getNullValue(ExtVT.getScalarSizeInBits()), DL, ExtVT);
13018 SDValue V = DAG.getNode(ISD::VSELECT, DL, ExtVT, In, One, Zero);
13019 if (VT.is512BitVector())
13021 return DAG.getNode(X86ISD::VTRUNC, DL, VT, V);
13024 static SDValue LowerANY_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
13025 SelectionDAG &DAG) {
13026 if (Subtarget->hasFp256())
13027 if (SDValue Res = LowerAVXExtend(Op, DAG, Subtarget))
13033 static SDValue LowerZERO_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
13034 SelectionDAG &DAG) {
13036 MVT VT = Op.getSimpleValueType();
13037 SDValue In = Op.getOperand(0);
13038 MVT SVT = In.getSimpleValueType();
13040 if (VT.is512BitVector() || SVT.getVectorElementType() == MVT::i1)
13041 return LowerZERO_EXTEND_AVX512(Op, Subtarget, DAG);
13043 if (Subtarget->hasFp256())
13044 if (SDValue Res = LowerAVXExtend(Op, DAG, Subtarget))
13047 assert(!VT.is256BitVector() || !SVT.is128BitVector() ||
13048 VT.getVectorNumElements() != SVT.getVectorNumElements());
13052 SDValue X86TargetLowering::LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const {
13054 MVT VT = Op.getSimpleValueType();
13055 SDValue In = Op.getOperand(0);
13056 MVT InVT = In.getSimpleValueType();
13058 if (VT == MVT::i1) {
13059 assert((InVT.isInteger() && (InVT.getSizeInBits() <= 64)) &&
13060 "Invalid scalar TRUNCATE operation");
13061 if (InVT.getSizeInBits() >= 32)
13063 In = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, In);
13064 return DAG.getNode(ISD::TRUNCATE, DL, VT, In);
13066 assert(VT.getVectorNumElements() == InVT.getVectorNumElements() &&
13067 "Invalid TRUNCATE operation");
13069 // move vector to mask - truncate solution for SKX
13070 if (VT.getVectorElementType() == MVT::i1) {
13071 if (InVT.is512BitVector() && InVT.getScalarSizeInBits() <= 16 &&
13072 Subtarget->hasBWI())
13073 return Op; // legal, will go to VPMOVB2M, VPMOVW2M
13074 if ((InVT.is256BitVector() || InVT.is128BitVector())
13075 && InVT.getScalarSizeInBits() <= 16 &&
13076 Subtarget->hasBWI() && Subtarget->hasVLX())
13077 return Op; // legal, will go to VPMOVB2M, VPMOVW2M
13078 if (InVT.is512BitVector() && InVT.getScalarSizeInBits() >= 32 &&
13079 Subtarget->hasDQI())
13080 return Op; // legal, will go to VPMOVD2M, VPMOVQ2M
13081 if ((InVT.is256BitVector() || InVT.is128BitVector())
13082 && InVT.getScalarSizeInBits() >= 32 &&
13083 Subtarget->hasDQI() && Subtarget->hasVLX())
13084 return Op; // legal, will go to VPMOVB2M, VPMOVQ2M
13087 if (VT.getVectorElementType() == MVT::i1) {
13088 assert(VT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
13089 unsigned NumElts = InVT.getVectorNumElements();
13090 assert ((NumElts == 8 || NumElts == 16) && "Unexpected vector type");
13091 if (InVT.getSizeInBits() < 512) {
13092 MVT ExtVT = (NumElts == 16)? MVT::v16i32 : MVT::v8i64;
13093 In = DAG.getNode(ISD::SIGN_EXTEND, DL, ExtVT, In);
13098 DAG.getConstant(APInt::getSignBit(InVT.getScalarSizeInBits()), DL, InVT);
13099 SDValue And = DAG.getNode(ISD::AND, DL, InVT, OneV, In);
13100 return DAG.getNode(X86ISD::TESTM, DL, VT, And, And);
13103 // vpmovqb/w/d, vpmovdb/w, vpmovwb
13104 if (((!InVT.is512BitVector() && Subtarget->hasVLX()) || InVT.is512BitVector()) &&
13105 (InVT.getVectorElementType() != MVT::i16 || Subtarget->hasBWI()))
13106 return DAG.getNode(X86ISD::VTRUNC, DL, VT, In);
13108 if ((VT == MVT::v4i32) && (InVT == MVT::v4i64)) {
13109 // On AVX2, v4i64 -> v4i32 becomes VPERMD.
13110 if (Subtarget->hasInt256()) {
13111 static const int ShufMask[] = {0, 2, 4, 6, -1, -1, -1, -1};
13112 In = DAG.getBitcast(MVT::v8i32, In);
13113 In = DAG.getVectorShuffle(MVT::v8i32, DL, In, DAG.getUNDEF(MVT::v8i32),
13115 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, In,
13116 DAG.getIntPtrConstant(0, DL));
13119 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
13120 DAG.getIntPtrConstant(0, DL));
13121 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
13122 DAG.getIntPtrConstant(2, DL));
13123 OpLo = DAG.getBitcast(MVT::v4i32, OpLo);
13124 OpHi = DAG.getBitcast(MVT::v4i32, OpHi);
13125 static const int ShufMask[] = {0, 2, 4, 6};
13126 return DAG.getVectorShuffle(VT, DL, OpLo, OpHi, ShufMask);
13129 if ((VT == MVT::v8i16) && (InVT == MVT::v8i32)) {
13130 // On AVX2, v8i32 -> v8i16 becomed PSHUFB.
13131 if (Subtarget->hasInt256()) {
13132 In = DAG.getBitcast(MVT::v32i8, In);
13134 SmallVector<SDValue,32> pshufbMask;
13135 for (unsigned i = 0; i < 2; ++i) {
13136 pshufbMask.push_back(DAG.getConstant(0x0, DL, MVT::i8));
13137 pshufbMask.push_back(DAG.getConstant(0x1, DL, MVT::i8));
13138 pshufbMask.push_back(DAG.getConstant(0x4, DL, MVT::i8));
13139 pshufbMask.push_back(DAG.getConstant(0x5, DL, MVT::i8));
13140 pshufbMask.push_back(DAG.getConstant(0x8, DL, MVT::i8));
13141 pshufbMask.push_back(DAG.getConstant(0x9, DL, MVT::i8));
13142 pshufbMask.push_back(DAG.getConstant(0xc, DL, MVT::i8));
13143 pshufbMask.push_back(DAG.getConstant(0xd, DL, MVT::i8));
13144 for (unsigned j = 0; j < 8; ++j)
13145 pshufbMask.push_back(DAG.getConstant(0x80, DL, MVT::i8));
13147 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, pshufbMask);
13148 In = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v32i8, In, BV);
13149 In = DAG.getBitcast(MVT::v4i64, In);
13151 static const int ShufMask[] = {0, 2, -1, -1};
13152 In = DAG.getVectorShuffle(MVT::v4i64, DL, In, DAG.getUNDEF(MVT::v4i64),
13154 In = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
13155 DAG.getIntPtrConstant(0, DL));
13156 return DAG.getBitcast(VT, In);
13159 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
13160 DAG.getIntPtrConstant(0, DL));
13162 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
13163 DAG.getIntPtrConstant(4, DL));
13165 OpLo = DAG.getBitcast(MVT::v16i8, OpLo);
13166 OpHi = DAG.getBitcast(MVT::v16i8, OpHi);
13168 // The PSHUFB mask:
13169 static const int ShufMask1[] = {0, 1, 4, 5, 8, 9, 12, 13,
13170 -1, -1, -1, -1, -1, -1, -1, -1};
13172 SDValue Undef = DAG.getUNDEF(MVT::v16i8);
13173 OpLo = DAG.getVectorShuffle(MVT::v16i8, DL, OpLo, Undef, ShufMask1);
13174 OpHi = DAG.getVectorShuffle(MVT::v16i8, DL, OpHi, Undef, ShufMask1);
13176 OpLo = DAG.getBitcast(MVT::v4i32, OpLo);
13177 OpHi = DAG.getBitcast(MVT::v4i32, OpHi);
13179 // The MOVLHPS Mask:
13180 static const int ShufMask2[] = {0, 1, 4, 5};
13181 SDValue res = DAG.getVectorShuffle(MVT::v4i32, DL, OpLo, OpHi, ShufMask2);
13182 return DAG.getBitcast(MVT::v8i16, res);
13185 // Handle truncation of V256 to V128 using shuffles.
13186 if (!VT.is128BitVector() || !InVT.is256BitVector())
13189 assert(Subtarget->hasFp256() && "256-bit vector without AVX!");
13191 unsigned NumElems = VT.getVectorNumElements();
13192 MVT NVT = MVT::getVectorVT(VT.getVectorElementType(), NumElems * 2);
13194 SmallVector<int, 16> MaskVec(NumElems * 2, -1);
13195 // Prepare truncation shuffle mask
13196 for (unsigned i = 0; i != NumElems; ++i)
13197 MaskVec[i] = i * 2;
13198 SDValue V = DAG.getVectorShuffle(NVT, DL, DAG.getBitcast(NVT, In),
13199 DAG.getUNDEF(NVT), &MaskVec[0]);
13200 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, V,
13201 DAG.getIntPtrConstant(0, DL));
13204 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op,
13205 SelectionDAG &DAG) const {
13206 assert(!Op.getSimpleValueType().isVector());
13208 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
13209 /*IsSigned=*/ true, /*IsReplace=*/ false);
13210 SDValue FIST = Vals.first, StackSlot = Vals.second;
13211 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
13212 if (!FIST.getNode())
13215 if (StackSlot.getNode())
13216 // Load the result.
13217 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
13218 FIST, StackSlot, MachinePointerInfo(),
13219 false, false, false, 0);
13221 // The node is the result.
13225 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op,
13226 SelectionDAG &DAG) const {
13227 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
13228 /*IsSigned=*/ false, /*IsReplace=*/ false);
13229 SDValue FIST = Vals.first, StackSlot = Vals.second;
13230 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
13231 if (!FIST.getNode())
13234 if (StackSlot.getNode())
13235 // Load the result.
13236 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
13237 FIST, StackSlot, MachinePointerInfo(),
13238 false, false, false, 0);
13240 // The node is the result.
13244 static SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) {
13246 MVT VT = Op.getSimpleValueType();
13247 SDValue In = Op.getOperand(0);
13248 MVT SVT = In.getSimpleValueType();
13250 assert(SVT == MVT::v2f32 && "Only customize MVT::v2f32 type legalization!");
13252 return DAG.getNode(X86ISD::VFPEXT, DL, VT,
13253 DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v4f32,
13254 In, DAG.getUNDEF(SVT)));
13257 /// The only differences between FABS and FNEG are the mask and the logic op.
13258 /// FNEG also has a folding opportunity for FNEG(FABS(x)).
13259 static SDValue LowerFABSorFNEG(SDValue Op, SelectionDAG &DAG) {
13260 assert((Op.getOpcode() == ISD::FABS || Op.getOpcode() == ISD::FNEG) &&
13261 "Wrong opcode for lowering FABS or FNEG.");
13263 bool IsFABS = (Op.getOpcode() == ISD::FABS);
13265 // If this is a FABS and it has an FNEG user, bail out to fold the combination
13266 // into an FNABS. We'll lower the FABS after that if it is still in use.
13268 for (SDNode *User : Op->uses())
13269 if (User->getOpcode() == ISD::FNEG)
13273 MVT VT = Op.getSimpleValueType();
13275 // FIXME: Use function attribute "OptimizeForSize" and/or CodeGenOpt::Level to
13276 // decide if we should generate a 16-byte constant mask when we only need 4 or
13277 // 8 bytes for the scalar case.
13283 if (VT.isVector()) {
13285 EltVT = VT.getVectorElementType();
13286 NumElts = VT.getVectorNumElements();
13288 // There are no scalar bitwise logical SSE/AVX instructions, so we
13289 // generate a 16-byte vector constant and logic op even for the scalar case.
13290 // Using a 16-byte mask allows folding the load of the mask with
13291 // the logic op, so it can save (~4 bytes) on code size.
13292 LogicVT = (VT == MVT::f64) ? MVT::v2f64 : MVT::v4f32;
13294 NumElts = (VT == MVT::f64) ? 2 : 4;
13297 unsigned EltBits = EltVT.getSizeInBits();
13298 LLVMContext *Context = DAG.getContext();
13299 // For FABS, mask is 0x7f...; for FNEG, mask is 0x80...
13301 IsFABS ? APInt::getSignedMaxValue(EltBits) : APInt::getSignBit(EltBits);
13302 Constant *C = ConstantInt::get(*Context, MaskElt);
13303 C = ConstantVector::getSplat(NumElts, C);
13304 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13305 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy(DAG.getDataLayout()));
13306 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
13308 DAG.getLoad(LogicVT, dl, DAG.getEntryNode(), CPIdx,
13309 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()),
13310 false, false, false, Alignment);
13312 SDValue Op0 = Op.getOperand(0);
13313 bool IsFNABS = !IsFABS && (Op0.getOpcode() == ISD::FABS);
13315 IsFABS ? X86ISD::FAND : IsFNABS ? X86ISD::FOR : X86ISD::FXOR;
13316 SDValue Operand = IsFNABS ? Op0.getOperand(0) : Op0;
13319 return DAG.getNode(LogicOp, dl, LogicVT, Operand, Mask);
13321 // For the scalar case extend to a 128-bit vector, perform the logic op,
13322 // and extract the scalar result back out.
13323 Operand = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LogicVT, Operand);
13324 SDValue LogicNode = DAG.getNode(LogicOp, dl, LogicVT, Operand, Mask);
13325 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, LogicNode,
13326 DAG.getIntPtrConstant(0, dl));
13329 static SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) {
13330 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13331 LLVMContext *Context = DAG.getContext();
13332 SDValue Op0 = Op.getOperand(0);
13333 SDValue Op1 = Op.getOperand(1);
13335 MVT VT = Op.getSimpleValueType();
13336 MVT SrcVT = Op1.getSimpleValueType();
13338 // If second operand is smaller, extend it first.
13339 if (SrcVT.bitsLT(VT)) {
13340 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
13343 // And if it is bigger, shrink it first.
13344 if (SrcVT.bitsGT(VT)) {
13345 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1, dl));
13349 // At this point the operands and the result should have the same
13350 // type, and that won't be f80 since that is not custom lowered.
13352 const fltSemantics &Sem =
13353 VT == MVT::f64 ? APFloat::IEEEdouble : APFloat::IEEEsingle;
13354 const unsigned SizeInBits = VT.getSizeInBits();
13356 SmallVector<Constant *, 4> CV(
13357 VT == MVT::f64 ? 2 : 4,
13358 ConstantFP::get(*Context, APFloat(Sem, APInt(SizeInBits, 0))));
13360 // First, clear all bits but the sign bit from the second operand (sign).
13361 CV[0] = ConstantFP::get(*Context,
13362 APFloat(Sem, APInt::getHighBitsSet(SizeInBits, 1)));
13363 Constant *C = ConstantVector::get(CV);
13364 auto PtrVT = TLI.getPointerTy(DAG.getDataLayout());
13365 SDValue CPIdx = DAG.getConstantPool(C, PtrVT, 16);
13367 // Perform all logic operations as 16-byte vectors because there are no
13368 // scalar FP logic instructions in SSE. This allows load folding of the
13369 // constants into the logic instructions.
13370 MVT LogicVT = (VT == MVT::f64) ? MVT::v2f64 : MVT::v4f32;
13372 DAG.getLoad(LogicVT, dl, DAG.getEntryNode(), CPIdx,
13373 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()),
13374 false, false, false, 16);
13375 Op1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LogicVT, Op1);
13376 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, LogicVT, Op1, Mask1);
13378 // Next, clear the sign bit from the first operand (magnitude).
13379 // If it's a constant, we can clear it here.
13380 if (ConstantFPSDNode *Op0CN = dyn_cast<ConstantFPSDNode>(Op0)) {
13381 APFloat APF = Op0CN->getValueAPF();
13382 // If the magnitude is a positive zero, the sign bit alone is enough.
13383 if (APF.isPosZero())
13384 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SrcVT, SignBit,
13385 DAG.getIntPtrConstant(0, dl));
13387 CV[0] = ConstantFP::get(*Context, APF);
13389 CV[0] = ConstantFP::get(
13391 APFloat(Sem, APInt::getLowBitsSet(SizeInBits, SizeInBits - 1)));
13393 C = ConstantVector::get(CV);
13394 CPIdx = DAG.getConstantPool(C, PtrVT, 16);
13396 DAG.getLoad(LogicVT, dl, DAG.getEntryNode(), CPIdx,
13397 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()),
13398 false, false, false, 16);
13399 // If the magnitude operand wasn't a constant, we need to AND out the sign.
13400 if (!isa<ConstantFPSDNode>(Op0)) {
13401 Op0 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LogicVT, Op0);
13402 Val = DAG.getNode(X86ISD::FAND, dl, LogicVT, Op0, Val);
13404 // OR the magnitude value with the sign bit.
13405 Val = DAG.getNode(X86ISD::FOR, dl, LogicVT, Val, SignBit);
13406 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SrcVT, Val,
13407 DAG.getIntPtrConstant(0, dl));
13410 static SDValue LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) {
13411 SDValue N0 = Op.getOperand(0);
13413 MVT VT = Op.getSimpleValueType();
13415 // Lower ISD::FGETSIGN to (AND (X86ISD::FGETSIGNx86 ...) 1).
13416 SDValue xFGETSIGN = DAG.getNode(X86ISD::FGETSIGNx86, dl, VT, N0,
13417 DAG.getConstant(1, dl, VT));
13418 return DAG.getNode(ISD::AND, dl, VT, xFGETSIGN, DAG.getConstant(1, dl, VT));
13421 // Check whether an OR'd tree is PTEST-able.
13422 static SDValue LowerVectorAllZeroTest(SDValue Op, const X86Subtarget *Subtarget,
13423 SelectionDAG &DAG) {
13424 assert(Op.getOpcode() == ISD::OR && "Only check OR'd tree.");
13426 if (!Subtarget->hasSSE41())
13429 if (!Op->hasOneUse())
13432 SDNode *N = Op.getNode();
13435 SmallVector<SDValue, 8> Opnds;
13436 DenseMap<SDValue, unsigned> VecInMap;
13437 SmallVector<SDValue, 8> VecIns;
13438 EVT VT = MVT::Other;
13440 // Recognize a special case where a vector is casted into wide integer to
13442 Opnds.push_back(N->getOperand(0));
13443 Opnds.push_back(N->getOperand(1));
13445 for (unsigned Slot = 0, e = Opnds.size(); Slot < e; ++Slot) {
13446 SmallVectorImpl<SDValue>::const_iterator I = Opnds.begin() + Slot;
13447 // BFS traverse all OR'd operands.
13448 if (I->getOpcode() == ISD::OR) {
13449 Opnds.push_back(I->getOperand(0));
13450 Opnds.push_back(I->getOperand(1));
13451 // Re-evaluate the number of nodes to be traversed.
13452 e += 2; // 2 more nodes (LHS and RHS) are pushed.
13456 // Quit if a non-EXTRACT_VECTOR_ELT
13457 if (I->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
13460 // Quit if without a constant index.
13461 SDValue Idx = I->getOperand(1);
13462 if (!isa<ConstantSDNode>(Idx))
13465 SDValue ExtractedFromVec = I->getOperand(0);
13466 DenseMap<SDValue, unsigned>::iterator M = VecInMap.find(ExtractedFromVec);
13467 if (M == VecInMap.end()) {
13468 VT = ExtractedFromVec.getValueType();
13469 // Quit if not 128/256-bit vector.
13470 if (!VT.is128BitVector() && !VT.is256BitVector())
13472 // Quit if not the same type.
13473 if (VecInMap.begin() != VecInMap.end() &&
13474 VT != VecInMap.begin()->first.getValueType())
13476 M = VecInMap.insert(std::make_pair(ExtractedFromVec, 0)).first;
13477 VecIns.push_back(ExtractedFromVec);
13479 M->second |= 1U << cast<ConstantSDNode>(Idx)->getZExtValue();
13482 assert((VT.is128BitVector() || VT.is256BitVector()) &&
13483 "Not extracted from 128-/256-bit vector.");
13485 unsigned FullMask = (1U << VT.getVectorNumElements()) - 1U;
13487 for (DenseMap<SDValue, unsigned>::const_iterator
13488 I = VecInMap.begin(), E = VecInMap.end(); I != E; ++I) {
13489 // Quit if not all elements are used.
13490 if (I->second != FullMask)
13494 EVT TestVT = VT.is128BitVector() ? MVT::v2i64 : MVT::v4i64;
13496 // Cast all vectors into TestVT for PTEST.
13497 for (unsigned i = 0, e = VecIns.size(); i < e; ++i)
13498 VecIns[i] = DAG.getBitcast(TestVT, VecIns[i]);
13500 // If more than one full vectors are evaluated, OR them first before PTEST.
13501 for (unsigned Slot = 0, e = VecIns.size(); e - Slot > 1; Slot += 2, e += 1) {
13502 // Each iteration will OR 2 nodes and append the result until there is only
13503 // 1 node left, i.e. the final OR'd value of all vectors.
13504 SDValue LHS = VecIns[Slot];
13505 SDValue RHS = VecIns[Slot + 1];
13506 VecIns.push_back(DAG.getNode(ISD::OR, DL, TestVT, LHS, RHS));
13509 return DAG.getNode(X86ISD::PTEST, DL, MVT::i32,
13510 VecIns.back(), VecIns.back());
13513 /// \brief return true if \c Op has a use that doesn't just read flags.
13514 static bool hasNonFlagsUse(SDValue Op) {
13515 for (SDNode::use_iterator UI = Op->use_begin(), UE = Op->use_end(); UI != UE;
13517 SDNode *User = *UI;
13518 unsigned UOpNo = UI.getOperandNo();
13519 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
13520 // Look pass truncate.
13521 UOpNo = User->use_begin().getOperandNo();
13522 User = *User->use_begin();
13525 if (User->getOpcode() != ISD::BRCOND && User->getOpcode() != ISD::SETCC &&
13526 !(User->getOpcode() == ISD::SELECT && UOpNo == 0))
13532 /// Emit nodes that will be selected as "test Op0,Op0", or something
13534 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC, SDLoc dl,
13535 SelectionDAG &DAG) const {
13536 if (Op.getValueType() == MVT::i1) {
13537 SDValue ExtOp = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i8, Op);
13538 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, ExtOp,
13539 DAG.getConstant(0, dl, MVT::i8));
13541 // CF and OF aren't always set the way we want. Determine which
13542 // of these we need.
13543 bool NeedCF = false;
13544 bool NeedOF = false;
13547 case X86::COND_A: case X86::COND_AE:
13548 case X86::COND_B: case X86::COND_BE:
13551 case X86::COND_G: case X86::COND_GE:
13552 case X86::COND_L: case X86::COND_LE:
13553 case X86::COND_O: case X86::COND_NO: {
13554 // Check if we really need to set the
13555 // Overflow flag. If NoSignedWrap is present
13556 // that is not actually needed.
13557 switch (Op->getOpcode()) {
13562 const auto *BinNode = cast<BinaryWithFlagsSDNode>(Op.getNode());
13563 if (BinNode->Flags.hasNoSignedWrap())
13573 // See if we can use the EFLAGS value from the operand instead of
13574 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
13575 // we prove that the arithmetic won't overflow, we can't use OF or CF.
13576 if (Op.getResNo() != 0 || NeedOF || NeedCF) {
13577 // Emit a CMP with 0, which is the TEST pattern.
13578 //if (Op.getValueType() == MVT::i1)
13579 // return DAG.getNode(X86ISD::CMP, dl, MVT::i1, Op,
13580 // DAG.getConstant(0, MVT::i1));
13581 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
13582 DAG.getConstant(0, dl, Op.getValueType()));
13584 unsigned Opcode = 0;
13585 unsigned NumOperands = 0;
13587 // Truncate operations may prevent the merge of the SETCC instruction
13588 // and the arithmetic instruction before it. Attempt to truncate the operands
13589 // of the arithmetic instruction and use a reduced bit-width instruction.
13590 bool NeedTruncation = false;
13591 SDValue ArithOp = Op;
13592 if (Op->getOpcode() == ISD::TRUNCATE && Op->hasOneUse()) {
13593 SDValue Arith = Op->getOperand(0);
13594 // Both the trunc and the arithmetic op need to have one user each.
13595 if (Arith->hasOneUse())
13596 switch (Arith.getOpcode()) {
13603 NeedTruncation = true;
13609 // NOTICE: In the code below we use ArithOp to hold the arithmetic operation
13610 // which may be the result of a CAST. We use the variable 'Op', which is the
13611 // non-casted variable when we check for possible users.
13612 switch (ArithOp.getOpcode()) {
13614 // Due to an isel shortcoming, be conservative if this add is likely to be
13615 // selected as part of a load-modify-store instruction. When the root node
13616 // in a match is a store, isel doesn't know how to remap non-chain non-flag
13617 // uses of other nodes in the match, such as the ADD in this case. This
13618 // leads to the ADD being left around and reselected, with the result being
13619 // two adds in the output. Alas, even if none our users are stores, that
13620 // doesn't prove we're O.K. Ergo, if we have any parents that aren't
13621 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require
13622 // climbing the DAG back to the root, and it doesn't seem to be worth the
13624 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
13625 UE = Op.getNode()->use_end(); UI != UE; ++UI)
13626 if (UI->getOpcode() != ISD::CopyToReg &&
13627 UI->getOpcode() != ISD::SETCC &&
13628 UI->getOpcode() != ISD::STORE)
13631 if (ConstantSDNode *C =
13632 dyn_cast<ConstantSDNode>(ArithOp.getNode()->getOperand(1))) {
13633 // An add of one will be selected as an INC.
13634 if (C->getAPIntValue() == 1 && !Subtarget->slowIncDec()) {
13635 Opcode = X86ISD::INC;
13640 // An add of negative one (subtract of one) will be selected as a DEC.
13641 if (C->getAPIntValue().isAllOnesValue() && !Subtarget->slowIncDec()) {
13642 Opcode = X86ISD::DEC;
13648 // Otherwise use a regular EFLAGS-setting add.
13649 Opcode = X86ISD::ADD;
13654 // If we have a constant logical shift that's only used in a comparison
13655 // against zero turn it into an equivalent AND. This allows turning it into
13656 // a TEST instruction later.
13657 if ((X86CC == X86::COND_E || X86CC == X86::COND_NE) && Op->hasOneUse() &&
13658 isa<ConstantSDNode>(Op->getOperand(1)) && !hasNonFlagsUse(Op)) {
13659 EVT VT = Op.getValueType();
13660 unsigned BitWidth = VT.getSizeInBits();
13661 unsigned ShAmt = Op->getConstantOperandVal(1);
13662 if (ShAmt >= BitWidth) // Avoid undefined shifts.
13664 APInt Mask = ArithOp.getOpcode() == ISD::SRL
13665 ? APInt::getHighBitsSet(BitWidth, BitWidth - ShAmt)
13666 : APInt::getLowBitsSet(BitWidth, BitWidth - ShAmt);
13667 if (!Mask.isSignedIntN(32)) // Avoid large immediates.
13669 SDValue New = DAG.getNode(ISD::AND, dl, VT, Op->getOperand(0),
13670 DAG.getConstant(Mask, dl, VT));
13671 DAG.ReplaceAllUsesWith(Op, New);
13677 // If the primary and result isn't used, don't bother using X86ISD::AND,
13678 // because a TEST instruction will be better.
13679 if (!hasNonFlagsUse(Op))
13685 // Due to the ISEL shortcoming noted above, be conservative if this op is
13686 // likely to be selected as part of a load-modify-store instruction.
13687 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
13688 UE = Op.getNode()->use_end(); UI != UE; ++UI)
13689 if (UI->getOpcode() == ISD::STORE)
13692 // Otherwise use a regular EFLAGS-setting instruction.
13693 switch (ArithOp.getOpcode()) {
13694 default: llvm_unreachable("unexpected operator!");
13695 case ISD::SUB: Opcode = X86ISD::SUB; break;
13696 case ISD::XOR: Opcode = X86ISD::XOR; break;
13697 case ISD::AND: Opcode = X86ISD::AND; break;
13699 if (!NeedTruncation && (X86CC == X86::COND_E || X86CC == X86::COND_NE)) {
13700 SDValue EFLAGS = LowerVectorAllZeroTest(Op, Subtarget, DAG);
13701 if (EFLAGS.getNode())
13704 Opcode = X86ISD::OR;
13718 return SDValue(Op.getNode(), 1);
13724 // If we found that truncation is beneficial, perform the truncation and
13726 if (NeedTruncation) {
13727 EVT VT = Op.getValueType();
13728 SDValue WideVal = Op->getOperand(0);
13729 EVT WideVT = WideVal.getValueType();
13730 unsigned ConvertedOp = 0;
13731 // Use a target machine opcode to prevent further DAGCombine
13732 // optimizations that may separate the arithmetic operations
13733 // from the setcc node.
13734 switch (WideVal.getOpcode()) {
13736 case ISD::ADD: ConvertedOp = X86ISD::ADD; break;
13737 case ISD::SUB: ConvertedOp = X86ISD::SUB; break;
13738 case ISD::AND: ConvertedOp = X86ISD::AND; break;
13739 case ISD::OR: ConvertedOp = X86ISD::OR; break;
13740 case ISD::XOR: ConvertedOp = X86ISD::XOR; break;
13744 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13745 if (TLI.isOperationLegal(WideVal.getOpcode(), WideVT)) {
13746 SDValue V0 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(0));
13747 SDValue V1 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(1));
13748 Op = DAG.getNode(ConvertedOp, dl, VT, V0, V1);
13754 // Emit a CMP with 0, which is the TEST pattern.
13755 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
13756 DAG.getConstant(0, dl, Op.getValueType()));
13758 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
13759 SmallVector<SDValue, 4> Ops(Op->op_begin(), Op->op_begin() + NumOperands);
13761 SDValue New = DAG.getNode(Opcode, dl, VTs, Ops);
13762 DAG.ReplaceAllUsesWith(Op, New);
13763 return SDValue(New.getNode(), 1);
13766 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
13768 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
13769 SDLoc dl, SelectionDAG &DAG) const {
13770 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1)) {
13771 if (C->getAPIntValue() == 0)
13772 return EmitTest(Op0, X86CC, dl, DAG);
13774 if (Op0.getValueType() == MVT::i1)
13775 llvm_unreachable("Unexpected comparison operation for MVT::i1 operands");
13778 if ((Op0.getValueType() == MVT::i8 || Op0.getValueType() == MVT::i16 ||
13779 Op0.getValueType() == MVT::i32 || Op0.getValueType() == MVT::i64)) {
13780 // Do the comparison at i32 if it's smaller, besides the Atom case.
13781 // This avoids subregister aliasing issues. Keep the smaller reference
13782 // if we're optimizing for size, however, as that'll allow better folding
13783 // of memory operations.
13784 if (Op0.getValueType() != MVT::i32 && Op0.getValueType() != MVT::i64 &&
13785 !DAG.getMachineFunction().getFunction()->optForMinSize() &&
13786 !Subtarget->isAtom()) {
13787 unsigned ExtendOp =
13788 isX86CCUnsigned(X86CC) ? ISD::ZERO_EXTEND : ISD::SIGN_EXTEND;
13789 Op0 = DAG.getNode(ExtendOp, dl, MVT::i32, Op0);
13790 Op1 = DAG.getNode(ExtendOp, dl, MVT::i32, Op1);
13792 // Use SUB instead of CMP to enable CSE between SUB and CMP.
13793 SDVTList VTs = DAG.getVTList(Op0.getValueType(), MVT::i32);
13794 SDValue Sub = DAG.getNode(X86ISD::SUB, dl, VTs,
13796 return SDValue(Sub.getNode(), 1);
13798 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
13801 /// Convert a comparison if required by the subtarget.
13802 SDValue X86TargetLowering::ConvertCmpIfNecessary(SDValue Cmp,
13803 SelectionDAG &DAG) const {
13804 // If the subtarget does not support the FUCOMI instruction, floating-point
13805 // comparisons have to be converted.
13806 if (Subtarget->hasCMov() ||
13807 Cmp.getOpcode() != X86ISD::CMP ||
13808 !Cmp.getOperand(0).getValueType().isFloatingPoint() ||
13809 !Cmp.getOperand(1).getValueType().isFloatingPoint())
13812 // The instruction selector will select an FUCOM instruction instead of
13813 // FUCOMI, which writes the comparison result to FPSW instead of EFLAGS. Hence
13814 // build an SDNode sequence that transfers the result from FPSW into EFLAGS:
13815 // (X86sahf (trunc (srl (X86fp_stsw (trunc (X86cmp ...)), 8))))
13817 SDValue TruncFPSW = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, Cmp);
13818 SDValue FNStSW = DAG.getNode(X86ISD::FNSTSW16r, dl, MVT::i16, TruncFPSW);
13819 SDValue Srl = DAG.getNode(ISD::SRL, dl, MVT::i16, FNStSW,
13820 DAG.getConstant(8, dl, MVT::i8));
13821 SDValue TruncSrl = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Srl);
13822 return DAG.getNode(X86ISD::SAHF, dl, MVT::i32, TruncSrl);
13825 /// The minimum architected relative accuracy is 2^-12. We need one
13826 /// Newton-Raphson step to have a good float result (24 bits of precision).
13827 SDValue X86TargetLowering::getRsqrtEstimate(SDValue Op,
13828 DAGCombinerInfo &DCI,
13829 unsigned &RefinementSteps,
13830 bool &UseOneConstNR) const {
13831 EVT VT = Op.getValueType();
13832 const char *RecipOp;
13834 // SSE1 has rsqrtss and rsqrtps. AVX adds a 256-bit variant for rsqrtps.
13835 // TODO: Add support for AVX512 (v16f32).
13836 // It is likely not profitable to do this for f64 because a double-precision
13837 // rsqrt estimate with refinement on x86 prior to FMA requires at least 16
13838 // instructions: convert to single, rsqrtss, convert back to double, refine
13839 // (3 steps = at least 13 insts). If an 'rsqrtsd' variant was added to the ISA
13840 // along with FMA, this could be a throughput win.
13841 if (VT == MVT::f32 && Subtarget->hasSSE1())
13843 else if ((VT == MVT::v4f32 && Subtarget->hasSSE1()) ||
13844 (VT == MVT::v8f32 && Subtarget->hasAVX()))
13845 RecipOp = "vec-sqrtf";
13849 TargetRecip Recips = DCI.DAG.getTarget().Options.Reciprocals;
13850 if (!Recips.isEnabled(RecipOp))
13853 RefinementSteps = Recips.getRefinementSteps(RecipOp);
13854 UseOneConstNR = false;
13855 return DCI.DAG.getNode(X86ISD::FRSQRT, SDLoc(Op), VT, Op);
13858 /// The minimum architected relative accuracy is 2^-12. We need one
13859 /// Newton-Raphson step to have a good float result (24 bits of precision).
13860 SDValue X86TargetLowering::getRecipEstimate(SDValue Op,
13861 DAGCombinerInfo &DCI,
13862 unsigned &RefinementSteps) const {
13863 EVT VT = Op.getValueType();
13864 const char *RecipOp;
13866 // SSE1 has rcpss and rcpps. AVX adds a 256-bit variant for rcpps.
13867 // TODO: Add support for AVX512 (v16f32).
13868 // It is likely not profitable to do this for f64 because a double-precision
13869 // reciprocal estimate with refinement on x86 prior to FMA requires
13870 // 15 instructions: convert to single, rcpss, convert back to double, refine
13871 // (3 steps = 12 insts). If an 'rcpsd' variant was added to the ISA
13872 // along with FMA, this could be a throughput win.
13873 if (VT == MVT::f32 && Subtarget->hasSSE1())
13875 else if ((VT == MVT::v4f32 && Subtarget->hasSSE1()) ||
13876 (VT == MVT::v8f32 && Subtarget->hasAVX()))
13877 RecipOp = "vec-divf";
13881 TargetRecip Recips = DCI.DAG.getTarget().Options.Reciprocals;
13882 if (!Recips.isEnabled(RecipOp))
13885 RefinementSteps = Recips.getRefinementSteps(RecipOp);
13886 return DCI.DAG.getNode(X86ISD::FRCP, SDLoc(Op), VT, Op);
13889 /// If we have at least two divisions that use the same divisor, convert to
13890 /// multplication by a reciprocal. This may need to be adjusted for a given
13891 /// CPU if a division's cost is not at least twice the cost of a multiplication.
13892 /// This is because we still need one division to calculate the reciprocal and
13893 /// then we need two multiplies by that reciprocal as replacements for the
13894 /// original divisions.
13895 unsigned X86TargetLowering::combineRepeatedFPDivisors() const {
13899 static bool isAllOnes(SDValue V) {
13900 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
13901 return C && C->isAllOnesValue();
13904 /// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node
13905 /// if it's possible.
13906 SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC,
13907 SDLoc dl, SelectionDAG &DAG) const {
13908 SDValue Op0 = And.getOperand(0);
13909 SDValue Op1 = And.getOperand(1);
13910 if (Op0.getOpcode() == ISD::TRUNCATE)
13911 Op0 = Op0.getOperand(0);
13912 if (Op1.getOpcode() == ISD::TRUNCATE)
13913 Op1 = Op1.getOperand(0);
13916 if (Op1.getOpcode() == ISD::SHL)
13917 std::swap(Op0, Op1);
13918 if (Op0.getOpcode() == ISD::SHL) {
13919 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0)))
13920 if (And00C->getZExtValue() == 1) {
13921 // If we looked past a truncate, check that it's only truncating away
13923 unsigned BitWidth = Op0.getValueSizeInBits();
13924 unsigned AndBitWidth = And.getValueSizeInBits();
13925 if (BitWidth > AndBitWidth) {
13927 DAG.computeKnownBits(Op0, Zeros, Ones);
13928 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth)
13932 RHS = Op0.getOperand(1);
13934 } else if (Op1.getOpcode() == ISD::Constant) {
13935 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1);
13936 uint64_t AndRHSVal = AndRHS->getZExtValue();
13937 SDValue AndLHS = Op0;
13939 if (AndRHSVal == 1 && AndLHS.getOpcode() == ISD::SRL) {
13940 LHS = AndLHS.getOperand(0);
13941 RHS = AndLHS.getOperand(1);
13944 // Use BT if the immediate can't be encoded in a TEST instruction.
13945 if (!isUInt<32>(AndRHSVal) && isPowerOf2_64(AndRHSVal)) {
13947 RHS = DAG.getConstant(Log2_64_Ceil(AndRHSVal), dl, LHS.getValueType());
13951 if (LHS.getNode()) {
13952 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT
13953 // instruction. Since the shift amount is in-range-or-undefined, we know
13954 // that doing a bittest on the i32 value is ok. We extend to i32 because
13955 // the encoding for the i16 version is larger than the i32 version.
13956 // Also promote i16 to i32 for performance / code size reason.
13957 if (LHS.getValueType() == MVT::i8 ||
13958 LHS.getValueType() == MVT::i16)
13959 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
13961 // If the operand types disagree, extend the shift amount to match. Since
13962 // BT ignores high bits (like shifts) we can use anyextend.
13963 if (LHS.getValueType() != RHS.getValueType())
13964 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
13966 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
13967 X86::CondCode Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
13968 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
13969 DAG.getConstant(Cond, dl, MVT::i8), BT);
13975 /// \brief - Turns an ISD::CondCode into a value suitable for SSE floating point
13977 static int translateX86FSETCC(ISD::CondCode SetCCOpcode, SDValue &Op0,
13982 // SSE Condition code mapping:
13991 switch (SetCCOpcode) {
13992 default: llvm_unreachable("Unexpected SETCC condition");
13994 case ISD::SETEQ: SSECC = 0; break;
13996 case ISD::SETGT: Swap = true; // Fallthrough
13998 case ISD::SETOLT: SSECC = 1; break;
14000 case ISD::SETGE: Swap = true; // Fallthrough
14002 case ISD::SETOLE: SSECC = 2; break;
14003 case ISD::SETUO: SSECC = 3; break;
14005 case ISD::SETNE: SSECC = 4; break;
14006 case ISD::SETULE: Swap = true; // Fallthrough
14007 case ISD::SETUGE: SSECC = 5; break;
14008 case ISD::SETULT: Swap = true; // Fallthrough
14009 case ISD::SETUGT: SSECC = 6; break;
14010 case ISD::SETO: SSECC = 7; break;
14012 case ISD::SETONE: SSECC = 8; break;
14015 std::swap(Op0, Op1);
14020 // Lower256IntVSETCC - Break a VSETCC 256-bit integer VSETCC into two new 128
14021 // ones, and then concatenate the result back.
14022 static SDValue Lower256IntVSETCC(SDValue Op, SelectionDAG &DAG) {
14023 MVT VT = Op.getSimpleValueType();
14025 assert(VT.is256BitVector() && Op.getOpcode() == ISD::SETCC &&
14026 "Unsupported value type for operation");
14028 unsigned NumElems = VT.getVectorNumElements();
14030 SDValue CC = Op.getOperand(2);
14032 // Extract the LHS vectors
14033 SDValue LHS = Op.getOperand(0);
14034 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
14035 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
14037 // Extract the RHS vectors
14038 SDValue RHS = Op.getOperand(1);
14039 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
14040 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
14042 // Issue the operation on the smaller types and concatenate the result back
14043 MVT EltVT = VT.getVectorElementType();
14044 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
14045 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
14046 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1, CC),
14047 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC));
14050 static SDValue LowerBoolVSETCC_AVX512(SDValue Op, SelectionDAG &DAG) {
14051 SDValue Op0 = Op.getOperand(0);
14052 SDValue Op1 = Op.getOperand(1);
14053 SDValue CC = Op.getOperand(2);
14054 MVT VT = Op.getSimpleValueType();
14057 assert(Op0.getValueType().getVectorElementType() == MVT::i1 &&
14058 "Unexpected type for boolean compare operation");
14059 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
14060 SDValue NotOp0 = DAG.getNode(ISD::XOR, dl, VT, Op0,
14061 DAG.getConstant(-1, dl, VT));
14062 SDValue NotOp1 = DAG.getNode(ISD::XOR, dl, VT, Op1,
14063 DAG.getConstant(-1, dl, VT));
14064 switch (SetCCOpcode) {
14065 default: llvm_unreachable("Unexpected SETCC condition");
14067 // (x == y) -> ~(x ^ y)
14068 return DAG.getNode(ISD::XOR, dl, VT,
14069 DAG.getNode(ISD::XOR, dl, VT, Op0, Op1),
14070 DAG.getConstant(-1, dl, VT));
14072 // (x != y) -> (x ^ y)
14073 return DAG.getNode(ISD::XOR, dl, VT, Op0, Op1);
14076 // (x > y) -> (x & ~y)
14077 return DAG.getNode(ISD::AND, dl, VT, Op0, NotOp1);
14080 // (x < y) -> (~x & y)
14081 return DAG.getNode(ISD::AND, dl, VT, NotOp0, Op1);
14084 // (x <= y) -> (~x | y)
14085 return DAG.getNode(ISD::OR, dl, VT, NotOp0, Op1);
14088 // (x >=y) -> (x | ~y)
14089 return DAG.getNode(ISD::OR, dl, VT, Op0, NotOp1);
14093 static SDValue LowerIntVSETCC_AVX512(SDValue Op, SelectionDAG &DAG,
14094 const X86Subtarget *Subtarget) {
14095 SDValue Op0 = Op.getOperand(0);
14096 SDValue Op1 = Op.getOperand(1);
14097 SDValue CC = Op.getOperand(2);
14098 MVT VT = Op.getSimpleValueType();
14101 assert(Op0.getValueType().getVectorElementType().getSizeInBits() >= 8 &&
14102 Op.getValueType().getScalarType() == MVT::i1 &&
14103 "Cannot set masked compare for this operation");
14105 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
14107 bool Unsigned = false;
14110 switch (SetCCOpcode) {
14111 default: llvm_unreachable("Unexpected SETCC condition");
14112 case ISD::SETNE: SSECC = 4; break;
14113 case ISD::SETEQ: Opc = X86ISD::PCMPEQM; break;
14114 case ISD::SETUGT: SSECC = 6; Unsigned = true; break;
14115 case ISD::SETLT: Swap = true; //fall-through
14116 case ISD::SETGT: Opc = X86ISD::PCMPGTM; break;
14117 case ISD::SETULT: SSECC = 1; Unsigned = true; break;
14118 case ISD::SETUGE: SSECC = 5; Unsigned = true; break; //NLT
14119 case ISD::SETGE: Swap = true; SSECC = 2; break; // LE + swap
14120 case ISD::SETULE: Unsigned = true; //fall-through
14121 case ISD::SETLE: SSECC = 2; break;
14125 std::swap(Op0, Op1);
14127 return DAG.getNode(Opc, dl, VT, Op0, Op1);
14128 Opc = Unsigned ? X86ISD::CMPMU: X86ISD::CMPM;
14129 return DAG.getNode(Opc, dl, VT, Op0, Op1,
14130 DAG.getConstant(SSECC, dl, MVT::i8));
14133 /// \brief Try to turn a VSETULT into a VSETULE by modifying its second
14134 /// operand \p Op1. If non-trivial (for example because it's not constant)
14135 /// return an empty value.
14136 static SDValue ChangeVSETULTtoVSETULE(SDLoc dl, SDValue Op1, SelectionDAG &DAG)
14138 BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(Op1.getNode());
14142 MVT VT = Op1.getSimpleValueType();
14143 MVT EVT = VT.getVectorElementType();
14144 unsigned n = VT.getVectorNumElements();
14145 SmallVector<SDValue, 8> ULTOp1;
14147 for (unsigned i = 0; i < n; ++i) {
14148 ConstantSDNode *Elt = dyn_cast<ConstantSDNode>(BV->getOperand(i));
14149 if (!Elt || Elt->isOpaque() || Elt->getValueType(0) != EVT)
14152 // Avoid underflow.
14153 APInt Val = Elt->getAPIntValue();
14157 ULTOp1.push_back(DAG.getConstant(Val - 1, dl, EVT));
14160 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, ULTOp1);
14163 static SDValue LowerVSETCC(SDValue Op, const X86Subtarget *Subtarget,
14164 SelectionDAG &DAG) {
14165 SDValue Op0 = Op.getOperand(0);
14166 SDValue Op1 = Op.getOperand(1);
14167 SDValue CC = Op.getOperand(2);
14168 MVT VT = Op.getSimpleValueType();
14169 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
14170 bool isFP = Op.getOperand(1).getSimpleValueType().isFloatingPoint();
14175 MVT EltVT = Op0.getSimpleValueType().getVectorElementType();
14176 assert(EltVT == MVT::f32 || EltVT == MVT::f64);
14179 unsigned SSECC = translateX86FSETCC(SetCCOpcode, Op0, Op1);
14180 unsigned Opc = X86ISD::CMPP;
14181 if (Subtarget->hasAVX512() && VT.getVectorElementType() == MVT::i1) {
14182 assert(VT.getVectorNumElements() <= 16);
14183 Opc = X86ISD::CMPM;
14185 // In the two special cases we can't handle, emit two comparisons.
14188 unsigned CombineOpc;
14189 if (SetCCOpcode == ISD::SETUEQ) {
14190 CC0 = 3; CC1 = 0; CombineOpc = ISD::OR;
14192 assert(SetCCOpcode == ISD::SETONE);
14193 CC0 = 7; CC1 = 4; CombineOpc = ISD::AND;
14196 SDValue Cmp0 = DAG.getNode(Opc, dl, VT, Op0, Op1,
14197 DAG.getConstant(CC0, dl, MVT::i8));
14198 SDValue Cmp1 = DAG.getNode(Opc, dl, VT, Op0, Op1,
14199 DAG.getConstant(CC1, dl, MVT::i8));
14200 return DAG.getNode(CombineOpc, dl, VT, Cmp0, Cmp1);
14202 // Handle all other FP comparisons here.
14203 return DAG.getNode(Opc, dl, VT, Op0, Op1,
14204 DAG.getConstant(SSECC, dl, MVT::i8));
14207 MVT VTOp0 = Op0.getSimpleValueType();
14208 assert(VTOp0 == Op1.getSimpleValueType() &&
14209 "Expected operands with same type!");
14210 assert(VT.getVectorNumElements() == VTOp0.getVectorNumElements() &&
14211 "Invalid number of packed elements for source and destination!");
14213 if (VT.is128BitVector() && VTOp0.is256BitVector()) {
14214 // On non-AVX512 targets, a vector of MVT::i1 is promoted by the type
14215 // legalizer to a wider vector type. In the case of 'vsetcc' nodes, the
14216 // legalizer firstly checks if the first operand in input to the setcc has
14217 // a legal type. If so, then it promotes the return type to that same type.
14218 // Otherwise, the return type is promoted to the 'next legal type' which,
14219 // for a vector of MVT::i1 is always a 128-bit integer vector type.
14221 // We reach this code only if the following two conditions are met:
14222 // 1. Both return type and operand type have been promoted to wider types
14223 // by the type legalizer.
14224 // 2. The original operand type has been promoted to a 256-bit vector.
14226 // Note that condition 2. only applies for AVX targets.
14227 SDValue NewOp = DAG.getSetCC(dl, VTOp0, Op0, Op1, SetCCOpcode);
14228 return DAG.getZExtOrTrunc(NewOp, dl, VT);
14231 // The non-AVX512 code below works under the assumption that source and
14232 // destination types are the same.
14233 assert((Subtarget->hasAVX512() || (VT == VTOp0)) &&
14234 "Value types for source and destination must be the same!");
14236 // Break 256-bit integer vector compare into smaller ones.
14237 if (VT.is256BitVector() && !Subtarget->hasInt256())
14238 return Lower256IntVSETCC(Op, DAG);
14240 EVT OpVT = Op1.getValueType();
14241 if (OpVT.getVectorElementType() == MVT::i1)
14242 return LowerBoolVSETCC_AVX512(Op, DAG);
14244 bool MaskResult = (VT.getVectorElementType() == MVT::i1);
14245 if (Subtarget->hasAVX512()) {
14246 if (Op1.getValueType().is512BitVector() ||
14247 (Subtarget->hasBWI() && Subtarget->hasVLX()) ||
14248 (MaskResult && OpVT.getVectorElementType().getSizeInBits() >= 32))
14249 return LowerIntVSETCC_AVX512(Op, DAG, Subtarget);
14251 // In AVX-512 architecture setcc returns mask with i1 elements,
14252 // But there is no compare instruction for i8 and i16 elements in KNL.
14253 // We are not talking about 512-bit operands in this case, these
14254 // types are illegal.
14256 (OpVT.getVectorElementType().getSizeInBits() < 32 &&
14257 OpVT.getVectorElementType().getSizeInBits() >= 8))
14258 return DAG.getNode(ISD::TRUNCATE, dl, VT,
14259 DAG.getNode(ISD::SETCC, dl, OpVT, Op0, Op1, CC));
14262 // Lower using XOP integer comparisons.
14263 if ((VT == MVT::v16i8 || VT == MVT::v8i16 ||
14264 VT == MVT::v4i32 || VT == MVT::v2i64) && Subtarget->hasXOP()) {
14265 // Translate compare code to XOP PCOM compare mode.
14266 unsigned CmpMode = 0;
14267 switch (SetCCOpcode) {
14268 default: llvm_unreachable("Unexpected SETCC condition");
14270 case ISD::SETLT: CmpMode = 0x00; break;
14272 case ISD::SETLE: CmpMode = 0x01; break;
14274 case ISD::SETGT: CmpMode = 0x02; break;
14276 case ISD::SETGE: CmpMode = 0x03; break;
14277 case ISD::SETEQ: CmpMode = 0x04; break;
14278 case ISD::SETNE: CmpMode = 0x05; break;
14281 // Are we comparing unsigned or signed integers?
14282 unsigned Opc = ISD::isUnsignedIntSetCC(SetCCOpcode)
14283 ? X86ISD::VPCOMU : X86ISD::VPCOM;
14285 return DAG.getNode(Opc, dl, VT, Op0, Op1,
14286 DAG.getConstant(CmpMode, dl, MVT::i8));
14289 // We are handling one of the integer comparisons here. Since SSE only has
14290 // GT and EQ comparisons for integer, swapping operands and multiple
14291 // operations may be required for some comparisons.
14293 bool Swap = false, Invert = false, FlipSigns = false, MinMax = false;
14294 bool Subus = false;
14296 switch (SetCCOpcode) {
14297 default: llvm_unreachable("Unexpected SETCC condition");
14298 case ISD::SETNE: Invert = true;
14299 case ISD::SETEQ: Opc = X86ISD::PCMPEQ; break;
14300 case ISD::SETLT: Swap = true;
14301 case ISD::SETGT: Opc = X86ISD::PCMPGT; break;
14302 case ISD::SETGE: Swap = true;
14303 case ISD::SETLE: Opc = X86ISD::PCMPGT;
14304 Invert = true; break;
14305 case ISD::SETULT: Swap = true;
14306 case ISD::SETUGT: Opc = X86ISD::PCMPGT;
14307 FlipSigns = true; break;
14308 case ISD::SETUGE: Swap = true;
14309 case ISD::SETULE: Opc = X86ISD::PCMPGT;
14310 FlipSigns = true; Invert = true; break;
14313 // Special case: Use min/max operations for SETULE/SETUGE
14314 MVT VET = VT.getVectorElementType();
14316 (Subtarget->hasSSE41() && (VET >= MVT::i8 && VET <= MVT::i32))
14317 || (Subtarget->hasSSE2() && (VET == MVT::i8));
14320 switch (SetCCOpcode) {
14322 case ISD::SETULE: Opc = ISD::UMIN; MinMax = true; break;
14323 case ISD::SETUGE: Opc = ISD::UMAX; MinMax = true; break;
14326 if (MinMax) { Swap = false; Invert = false; FlipSigns = false; }
14329 bool hasSubus = Subtarget->hasSSE2() && (VET == MVT::i8 || VET == MVT::i16);
14330 if (!MinMax && hasSubus) {
14331 // As another special case, use PSUBUS[BW] when it's profitable. E.g. for
14333 // t = psubus Op0, Op1
14334 // pcmpeq t, <0..0>
14335 switch (SetCCOpcode) {
14337 case ISD::SETULT: {
14338 // If the comparison is against a constant we can turn this into a
14339 // setule. With psubus, setule does not require a swap. This is
14340 // beneficial because the constant in the register is no longer
14341 // destructed as the destination so it can be hoisted out of a loop.
14342 // Only do this pre-AVX since vpcmp* is no longer destructive.
14343 if (Subtarget->hasAVX())
14345 SDValue ULEOp1 = ChangeVSETULTtoVSETULE(dl, Op1, DAG);
14346 if (ULEOp1.getNode()) {
14348 Subus = true; Invert = false; Swap = false;
14352 // Psubus is better than flip-sign because it requires no inversion.
14353 case ISD::SETUGE: Subus = true; Invert = false; Swap = true; break;
14354 case ISD::SETULE: Subus = true; Invert = false; Swap = false; break;
14358 Opc = X86ISD::SUBUS;
14364 std::swap(Op0, Op1);
14366 // Check that the operation in question is available (most are plain SSE2,
14367 // but PCMPGTQ and PCMPEQQ have different requirements).
14368 if (VT == MVT::v2i64) {
14369 if (Opc == X86ISD::PCMPGT && !Subtarget->hasSSE42()) {
14370 assert(Subtarget->hasSSE2() && "Don't know how to lower!");
14372 // First cast everything to the right type.
14373 Op0 = DAG.getBitcast(MVT::v4i32, Op0);
14374 Op1 = DAG.getBitcast(MVT::v4i32, Op1);
14376 // Since SSE has no unsigned integer comparisons, we need to flip the sign
14377 // bits of the inputs before performing those operations. The lower
14378 // compare is always unsigned.
14381 SB = DAG.getConstant(0x80000000U, dl, MVT::v4i32);
14383 SDValue Sign = DAG.getConstant(0x80000000U, dl, MVT::i32);
14384 SDValue Zero = DAG.getConstant(0x00000000U, dl, MVT::i32);
14385 SB = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
14386 Sign, Zero, Sign, Zero);
14388 Op0 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op0, SB);
14389 Op1 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op1, SB);
14391 // Emulate PCMPGTQ with (hi1 > hi2) | ((hi1 == hi2) & (lo1 > lo2))
14392 SDValue GT = DAG.getNode(X86ISD::PCMPGT, dl, MVT::v4i32, Op0, Op1);
14393 SDValue EQ = DAG.getNode(X86ISD::PCMPEQ, dl, MVT::v4i32, Op0, Op1);
14395 // Create masks for only the low parts/high parts of the 64 bit integers.
14396 static const int MaskHi[] = { 1, 1, 3, 3 };
14397 static const int MaskLo[] = { 0, 0, 2, 2 };
14398 SDValue EQHi = DAG.getVectorShuffle(MVT::v4i32, dl, EQ, EQ, MaskHi);
14399 SDValue GTLo = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskLo);
14400 SDValue GTHi = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskHi);
14402 SDValue Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, EQHi, GTLo);
14403 Result = DAG.getNode(ISD::OR, dl, MVT::v4i32, Result, GTHi);
14406 Result = DAG.getNOT(dl, Result, MVT::v4i32);
14408 return DAG.getBitcast(VT, Result);
14411 if (Opc == X86ISD::PCMPEQ && !Subtarget->hasSSE41()) {
14412 // If pcmpeqq is missing but pcmpeqd is available synthesize pcmpeqq with
14413 // pcmpeqd + pshufd + pand.
14414 assert(Subtarget->hasSSE2() && !FlipSigns && "Don't know how to lower!");
14416 // First cast everything to the right type.
14417 Op0 = DAG.getBitcast(MVT::v4i32, Op0);
14418 Op1 = DAG.getBitcast(MVT::v4i32, Op1);
14421 SDValue Result = DAG.getNode(Opc, dl, MVT::v4i32, Op0, Op1);
14423 // Make sure the lower and upper halves are both all-ones.
14424 static const int Mask[] = { 1, 0, 3, 2 };
14425 SDValue Shuf = DAG.getVectorShuffle(MVT::v4i32, dl, Result, Result, Mask);
14426 Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, Result, Shuf);
14429 Result = DAG.getNOT(dl, Result, MVT::v4i32);
14431 return DAG.getBitcast(VT, Result);
14435 // Since SSE has no unsigned integer comparisons, we need to flip the sign
14436 // bits of the inputs before performing those operations.
14438 MVT EltVT = VT.getVectorElementType();
14439 SDValue SB = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()), dl,
14441 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SB);
14442 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SB);
14445 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
14447 // If the logical-not of the result is required, perform that now.
14449 Result = DAG.getNOT(dl, Result, VT);
14452 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Op0, Result);
14455 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Result,
14456 getZeroVector(VT, Subtarget, DAG, dl));
14461 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
14463 MVT VT = Op.getSimpleValueType();
14465 if (VT.isVector()) return LowerVSETCC(Op, Subtarget, DAG);
14467 assert(((!Subtarget->hasAVX512() && VT == MVT::i8) || (VT == MVT::i1))
14468 && "SetCC type must be 8-bit or 1-bit integer");
14469 SDValue Op0 = Op.getOperand(0);
14470 SDValue Op1 = Op.getOperand(1);
14472 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
14474 // Optimize to BT if possible.
14475 // Lower (X & (1 << N)) == 0 to BT(X, N).
14476 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
14477 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
14478 if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() &&
14479 Op1.getOpcode() == ISD::Constant &&
14480 cast<ConstantSDNode>(Op1)->isNullValue() &&
14481 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
14482 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG);
14483 if (NewSetCC.getNode()) {
14485 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, NewSetCC);
14490 // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of
14492 if (Op1.getOpcode() == ISD::Constant &&
14493 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 ||
14494 cast<ConstantSDNode>(Op1)->isNullValue()) &&
14495 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
14497 // If the input is a setcc, then reuse the input setcc or use a new one with
14498 // the inverted condition.
14499 if (Op0.getOpcode() == X86ISD::SETCC) {
14500 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0);
14501 bool Invert = (CC == ISD::SETNE) ^
14502 cast<ConstantSDNode>(Op1)->isNullValue();
14506 CCode = X86::GetOppositeBranchCondition(CCode);
14507 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
14508 DAG.getConstant(CCode, dl, MVT::i8),
14509 Op0.getOperand(1));
14511 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
14515 if ((Op0.getValueType() == MVT::i1) && (Op1.getOpcode() == ISD::Constant) &&
14516 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1) &&
14517 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
14519 ISD::CondCode NewCC = ISD::getSetCCInverse(CC, true);
14520 return DAG.getSetCC(dl, VT, Op0, DAG.getConstant(0, dl, MVT::i1), NewCC);
14523 bool isFP = Op1.getSimpleValueType().isFloatingPoint();
14524 unsigned X86CC = TranslateX86CC(CC, dl, isFP, Op0, Op1, DAG);
14525 if (X86CC == X86::COND_INVALID)
14528 SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, dl, DAG);
14529 EFLAGS = ConvertCmpIfNecessary(EFLAGS, DAG);
14530 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
14531 DAG.getConstant(X86CC, dl, MVT::i8), EFLAGS);
14533 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
14537 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
14538 static bool isX86LogicalCmp(SDValue Op) {
14539 unsigned Opc = Op.getNode()->getOpcode();
14540 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI ||
14541 Opc == X86ISD::SAHF)
14543 if (Op.getResNo() == 1 &&
14544 (Opc == X86ISD::ADD ||
14545 Opc == X86ISD::SUB ||
14546 Opc == X86ISD::ADC ||
14547 Opc == X86ISD::SBB ||
14548 Opc == X86ISD::SMUL ||
14549 Opc == X86ISD::UMUL ||
14550 Opc == X86ISD::INC ||
14551 Opc == X86ISD::DEC ||
14552 Opc == X86ISD::OR ||
14553 Opc == X86ISD::XOR ||
14554 Opc == X86ISD::AND))
14557 if (Op.getResNo() == 2 && Opc == X86ISD::UMUL)
14563 static bool isTruncWithZeroHighBitsInput(SDValue V, SelectionDAG &DAG) {
14564 if (V.getOpcode() != ISD::TRUNCATE)
14567 SDValue VOp0 = V.getOperand(0);
14568 unsigned InBits = VOp0.getValueSizeInBits();
14569 unsigned Bits = V.getValueSizeInBits();
14570 return DAG.MaskedValueIsZero(VOp0, APInt::getHighBitsSet(InBits,InBits-Bits));
14573 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
14574 bool addTest = true;
14575 SDValue Cond = Op.getOperand(0);
14576 SDValue Op1 = Op.getOperand(1);
14577 SDValue Op2 = Op.getOperand(2);
14579 EVT VT = Op1.getValueType();
14582 // Lower FP selects into a CMP/AND/ANDN/OR sequence when the necessary SSE ops
14583 // are available or VBLENDV if AVX is available.
14584 // Otherwise FP cmovs get lowered into a less efficient branch sequence later.
14585 if (Cond.getOpcode() == ISD::SETCC &&
14586 ((Subtarget->hasSSE2() && (VT == MVT::f32 || VT == MVT::f64)) ||
14587 (Subtarget->hasSSE1() && VT == MVT::f32)) &&
14588 VT == Cond.getOperand(0).getValueType() && Cond->hasOneUse()) {
14589 SDValue CondOp0 = Cond.getOperand(0), CondOp1 = Cond.getOperand(1);
14590 int SSECC = translateX86FSETCC(
14591 cast<CondCodeSDNode>(Cond.getOperand(2))->get(), CondOp0, CondOp1);
14594 if (Subtarget->hasAVX512()) {
14595 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CondOp0, CondOp1,
14596 DAG.getConstant(SSECC, DL, MVT::i8));
14597 return DAG.getNode(X86ISD::SELECT, DL, VT, Cmp, Op1, Op2);
14600 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, VT, CondOp0, CondOp1,
14601 DAG.getConstant(SSECC, DL, MVT::i8));
14603 // If we have AVX, we can use a variable vector select (VBLENDV) instead
14604 // of 3 logic instructions for size savings and potentially speed.
14605 // Unfortunately, there is no scalar form of VBLENDV.
14607 // If either operand is a constant, don't try this. We can expect to
14608 // optimize away at least one of the logic instructions later in that
14609 // case, so that sequence would be faster than a variable blend.
14611 // BLENDV was introduced with SSE 4.1, but the 2 register form implicitly
14612 // uses XMM0 as the selection register. That may need just as many
14613 // instructions as the AND/ANDN/OR sequence due to register moves, so
14616 if (Subtarget->hasAVX() &&
14617 !isa<ConstantFPSDNode>(Op1) && !isa<ConstantFPSDNode>(Op2)) {
14619 // Convert to vectors, do a VSELECT, and convert back to scalar.
14620 // All of the conversions should be optimized away.
14622 EVT VecVT = VT == MVT::f32 ? MVT::v4f32 : MVT::v2f64;
14623 SDValue VOp1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VecVT, Op1);
14624 SDValue VOp2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VecVT, Op2);
14625 SDValue VCmp = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VecVT, Cmp);
14627 EVT VCmpVT = VT == MVT::f32 ? MVT::v4i32 : MVT::v2i64;
14628 VCmp = DAG.getBitcast(VCmpVT, VCmp);
14630 SDValue VSel = DAG.getNode(ISD::VSELECT, DL, VecVT, VCmp, VOp1, VOp2);
14632 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT,
14633 VSel, DAG.getIntPtrConstant(0, DL));
14635 SDValue AndN = DAG.getNode(X86ISD::FANDN, DL, VT, Cmp, Op2);
14636 SDValue And = DAG.getNode(X86ISD::FAND, DL, VT, Cmp, Op1);
14637 return DAG.getNode(X86ISD::FOR, DL, VT, AndN, And);
14641 if (VT.isVector() && VT.getScalarType() == MVT::i1) {
14643 if (ISD::isBuildVectorOfConstantSDNodes(Op1.getNode()))
14644 Op1Scalar = ConvertI1VectorToInteger(Op1, DAG);
14645 else if (Op1.getOpcode() == ISD::BITCAST && Op1.getOperand(0))
14646 Op1Scalar = Op1.getOperand(0);
14648 if (ISD::isBuildVectorOfConstantSDNodes(Op2.getNode()))
14649 Op2Scalar = ConvertI1VectorToInteger(Op2, DAG);
14650 else if (Op2.getOpcode() == ISD::BITCAST && Op2.getOperand(0))
14651 Op2Scalar = Op2.getOperand(0);
14652 if (Op1Scalar.getNode() && Op2Scalar.getNode()) {
14653 SDValue newSelect = DAG.getNode(ISD::SELECT, DL,
14654 Op1Scalar.getValueType(),
14655 Cond, Op1Scalar, Op2Scalar);
14656 if (newSelect.getValueSizeInBits() == VT.getSizeInBits())
14657 return DAG.getBitcast(VT, newSelect);
14658 SDValue ExtVec = DAG.getBitcast(MVT::v8i1, newSelect);
14659 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, ExtVec,
14660 DAG.getIntPtrConstant(0, DL));
14664 if (VT == MVT::v4i1 || VT == MVT::v2i1) {
14665 SDValue zeroConst = DAG.getIntPtrConstant(0, DL);
14666 Op1 = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, MVT::v8i1,
14667 DAG.getUNDEF(MVT::v8i1), Op1, zeroConst);
14668 Op2 = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, MVT::v8i1,
14669 DAG.getUNDEF(MVT::v8i1), Op2, zeroConst);
14670 SDValue newSelect = DAG.getNode(ISD::SELECT, DL, MVT::v8i1,
14672 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, newSelect, zeroConst);
14675 if (Cond.getOpcode() == ISD::SETCC) {
14676 SDValue NewCond = LowerSETCC(Cond, DAG);
14677 if (NewCond.getNode())
14681 // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y
14682 // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y
14683 // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y
14684 // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y
14685 if (Cond.getOpcode() == X86ISD::SETCC &&
14686 Cond.getOperand(1).getOpcode() == X86ISD::CMP &&
14687 isZero(Cond.getOperand(1).getOperand(1))) {
14688 SDValue Cmp = Cond.getOperand(1);
14690 unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue();
14692 if ((isAllOnes(Op1) || isAllOnes(Op2)) &&
14693 (CondCode == X86::COND_E || CondCode == X86::COND_NE)) {
14694 SDValue Y = isAllOnes(Op2) ? Op1 : Op2;
14696 SDValue CmpOp0 = Cmp.getOperand(0);
14697 // Apply further optimizations for special cases
14698 // (select (x != 0), -1, 0) -> neg & sbb
14699 // (select (x == 0), 0, -1) -> neg & sbb
14700 if (ConstantSDNode *YC = dyn_cast<ConstantSDNode>(Y))
14701 if (YC->isNullValue() &&
14702 (isAllOnes(Op1) == (CondCode == X86::COND_NE))) {
14703 SDVTList VTs = DAG.getVTList(CmpOp0.getValueType(), MVT::i32);
14704 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, VTs,
14705 DAG.getConstant(0, DL,
14706 CmpOp0.getValueType()),
14708 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
14709 DAG.getConstant(X86::COND_B, DL, MVT::i8),
14710 SDValue(Neg.getNode(), 1));
14714 Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32,
14715 CmpOp0, DAG.getConstant(1, DL, CmpOp0.getValueType()));
14716 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
14718 SDValue Res = // Res = 0 or -1.
14719 DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
14720 DAG.getConstant(X86::COND_B, DL, MVT::i8), Cmp);
14722 if (isAllOnes(Op1) != (CondCode == X86::COND_E))
14723 Res = DAG.getNOT(DL, Res, Res.getValueType());
14725 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2);
14726 if (!N2C || !N2C->isNullValue())
14727 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y);
14732 // Look past (and (setcc_carry (cmp ...)), 1).
14733 if (Cond.getOpcode() == ISD::AND &&
14734 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
14735 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
14736 if (C && C->getAPIntValue() == 1)
14737 Cond = Cond.getOperand(0);
14740 // If condition flag is set by a X86ISD::CMP, then use it as the condition
14741 // setting operand in place of the X86ISD::SETCC.
14742 unsigned CondOpcode = Cond.getOpcode();
14743 if (CondOpcode == X86ISD::SETCC ||
14744 CondOpcode == X86ISD::SETCC_CARRY) {
14745 CC = Cond.getOperand(0);
14747 SDValue Cmp = Cond.getOperand(1);
14748 unsigned Opc = Cmp.getOpcode();
14749 MVT VT = Op.getSimpleValueType();
14751 bool IllegalFPCMov = false;
14752 if (VT.isFloatingPoint() && !VT.isVector() &&
14753 !isScalarFPTypeInSSEReg(VT)) // FPStack?
14754 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
14756 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
14757 Opc == X86ISD::BT) { // FIXME
14761 } else if (CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
14762 CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
14763 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
14764 Cond.getOperand(0).getValueType() != MVT::i8)) {
14765 SDValue LHS = Cond.getOperand(0);
14766 SDValue RHS = Cond.getOperand(1);
14767 unsigned X86Opcode;
14770 switch (CondOpcode) {
14771 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
14772 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
14773 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
14774 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
14775 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
14776 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
14777 default: llvm_unreachable("unexpected overflowing operator");
14779 if (CondOpcode == ISD::UMULO)
14780 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
14783 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
14785 SDValue X86Op = DAG.getNode(X86Opcode, DL, VTs, LHS, RHS);
14787 if (CondOpcode == ISD::UMULO)
14788 Cond = X86Op.getValue(2);
14790 Cond = X86Op.getValue(1);
14792 CC = DAG.getConstant(X86Cond, DL, MVT::i8);
14797 // Look past the truncate if the high bits are known zero.
14798 if (isTruncWithZeroHighBitsInput(Cond, DAG))
14799 Cond = Cond.getOperand(0);
14801 // We know the result of AND is compared against zero. Try to match
14803 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
14804 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG);
14805 if (NewSetCC.getNode()) {
14806 CC = NewSetCC.getOperand(0);
14807 Cond = NewSetCC.getOperand(1);
14814 CC = DAG.getConstant(X86::COND_NE, DL, MVT::i8);
14815 Cond = EmitTest(Cond, X86::COND_NE, DL, DAG);
14818 // a < b ? -1 : 0 -> RES = ~setcc_carry
14819 // a < b ? 0 : -1 -> RES = setcc_carry
14820 // a >= b ? -1 : 0 -> RES = setcc_carry
14821 // a >= b ? 0 : -1 -> RES = ~setcc_carry
14822 if (Cond.getOpcode() == X86ISD::SUB) {
14823 Cond = ConvertCmpIfNecessary(Cond, DAG);
14824 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue();
14826 if ((CondCode == X86::COND_AE || CondCode == X86::COND_B) &&
14827 (isAllOnes(Op1) || isAllOnes(Op2)) && (isZero(Op1) || isZero(Op2))) {
14828 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
14829 DAG.getConstant(X86::COND_B, DL, MVT::i8),
14831 if (isAllOnes(Op1) != (CondCode == X86::COND_B))
14832 return DAG.getNOT(DL, Res, Res.getValueType());
14837 // X86 doesn't have an i8 cmov. If both operands are the result of a truncate
14838 // widen the cmov and push the truncate through. This avoids introducing a new
14839 // branch during isel and doesn't add any extensions.
14840 if (Op.getValueType() == MVT::i8 &&
14841 Op1.getOpcode() == ISD::TRUNCATE && Op2.getOpcode() == ISD::TRUNCATE) {
14842 SDValue T1 = Op1.getOperand(0), T2 = Op2.getOperand(0);
14843 if (T1.getValueType() == T2.getValueType() &&
14844 // Blacklist CopyFromReg to avoid partial register stalls.
14845 T1.getOpcode() != ISD::CopyFromReg && T2.getOpcode()!=ISD::CopyFromReg){
14846 SDVTList VTs = DAG.getVTList(T1.getValueType(), MVT::Glue);
14847 SDValue Cmov = DAG.getNode(X86ISD::CMOV, DL, VTs, T2, T1, CC, Cond);
14848 return DAG.getNode(ISD::TRUNCATE, DL, Op.getValueType(), Cmov);
14852 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
14853 // condition is true.
14854 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
14855 SDValue Ops[] = { Op2, Op1, CC, Cond };
14856 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops);
14859 static SDValue LowerSIGN_EXTEND_AVX512(SDValue Op,
14860 const X86Subtarget *Subtarget,
14861 SelectionDAG &DAG) {
14862 MVT VT = Op->getSimpleValueType(0);
14863 SDValue In = Op->getOperand(0);
14864 MVT InVT = In.getSimpleValueType();
14865 MVT VTElt = VT.getVectorElementType();
14866 MVT InVTElt = InVT.getVectorElementType();
14870 if ((InVTElt == MVT::i1) &&
14871 (((Subtarget->hasBWI() && Subtarget->hasVLX() &&
14872 VT.getSizeInBits() <= 256 && VTElt.getSizeInBits() <= 16)) ||
14874 ((Subtarget->hasBWI() && VT.is512BitVector() &&
14875 VTElt.getSizeInBits() <= 16)) ||
14877 ((Subtarget->hasDQI() && Subtarget->hasVLX() &&
14878 VT.getSizeInBits() <= 256 && VTElt.getSizeInBits() >= 32)) ||
14880 ((Subtarget->hasDQI() && VT.is512BitVector() &&
14881 VTElt.getSizeInBits() >= 32))))
14882 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
14884 unsigned int NumElts = VT.getVectorNumElements();
14886 if (NumElts != 8 && NumElts != 16 && !Subtarget->hasBWI())
14889 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1) {
14890 if (In.getOpcode() == X86ISD::VSEXT || In.getOpcode() == X86ISD::VZEXT)
14891 return DAG.getNode(In.getOpcode(), dl, VT, In.getOperand(0));
14892 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
14895 assert (InVT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
14896 MVT ExtVT = NumElts == 8 ? MVT::v8i64 : MVT::v16i32;
14898 DAG.getConstant(APInt::getAllOnesValue(ExtVT.getScalarSizeInBits()), dl,
14901 DAG.getConstant(APInt::getNullValue(ExtVT.getScalarSizeInBits()), dl, ExtVT);
14903 SDValue V = DAG.getNode(ISD::VSELECT, dl, ExtVT, In, NegOne, Zero);
14904 if (VT.is512BitVector())
14906 return DAG.getNode(X86ISD::VTRUNC, dl, VT, V);
14909 static SDValue LowerSIGN_EXTEND_VECTOR_INREG(SDValue Op,
14910 const X86Subtarget *Subtarget,
14911 SelectionDAG &DAG) {
14912 SDValue In = Op->getOperand(0);
14913 MVT VT = Op->getSimpleValueType(0);
14914 MVT InVT = In.getSimpleValueType();
14915 assert(VT.getSizeInBits() == InVT.getSizeInBits());
14917 MVT InSVT = InVT.getScalarType();
14918 assert(VT.getScalarType().getScalarSizeInBits() > InSVT.getScalarSizeInBits());
14920 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16)
14922 if (InSVT != MVT::i32 && InSVT != MVT::i16 && InSVT != MVT::i8)
14927 // SSE41 targets can use the pmovsx* instructions directly.
14928 if (Subtarget->hasSSE41())
14929 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
14931 // pre-SSE41 targets unpack lower lanes and then sign-extend using SRAI.
14935 // As SRAI is only available on i16/i32 types, we expand only up to i32
14936 // and handle i64 separately.
14937 while (CurrVT != VT && CurrVT.getScalarType() != MVT::i32) {
14938 Curr = DAG.getNode(X86ISD::UNPCKL, dl, CurrVT, DAG.getUNDEF(CurrVT), Curr);
14939 MVT CurrSVT = MVT::getIntegerVT(CurrVT.getScalarSizeInBits() * 2);
14940 CurrVT = MVT::getVectorVT(CurrSVT, CurrVT.getVectorNumElements() / 2);
14941 Curr = DAG.getBitcast(CurrVT, Curr);
14944 SDValue SignExt = Curr;
14945 if (CurrVT != InVT) {
14946 unsigned SignExtShift =
14947 CurrVT.getScalarSizeInBits() - InSVT.getScalarSizeInBits();
14948 SignExt = DAG.getNode(X86ISD::VSRAI, dl, CurrVT, Curr,
14949 DAG.getConstant(SignExtShift, dl, MVT::i8));
14955 if (VT == MVT::v2i64 && CurrVT == MVT::v4i32) {
14956 SDValue Sign = DAG.getNode(X86ISD::VSRAI, dl, CurrVT, Curr,
14957 DAG.getConstant(31, dl, MVT::i8));
14958 SDValue Ext = DAG.getVectorShuffle(CurrVT, dl, SignExt, Sign, {0, 4, 1, 5});
14959 return DAG.getBitcast(VT, Ext);
14965 static SDValue LowerSIGN_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
14966 SelectionDAG &DAG) {
14967 MVT VT = Op->getSimpleValueType(0);
14968 SDValue In = Op->getOperand(0);
14969 MVT InVT = In.getSimpleValueType();
14972 if (VT.is512BitVector() || InVT.getVectorElementType() == MVT::i1)
14973 return LowerSIGN_EXTEND_AVX512(Op, Subtarget, DAG);
14975 if ((VT != MVT::v4i64 || InVT != MVT::v4i32) &&
14976 (VT != MVT::v8i32 || InVT != MVT::v8i16) &&
14977 (VT != MVT::v16i16 || InVT != MVT::v16i8))
14980 if (Subtarget->hasInt256())
14981 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
14983 // Optimize vectors in AVX mode
14984 // Sign extend v8i16 to v8i32 and
14987 // Divide input vector into two parts
14988 // for v4i32 the shuffle mask will be { 0, 1, -1, -1} {2, 3, -1, -1}
14989 // use vpmovsx instruction to extend v4i32 -> v2i64; v8i16 -> v4i32
14990 // concat the vectors to original VT
14992 unsigned NumElems = InVT.getVectorNumElements();
14993 SDValue Undef = DAG.getUNDEF(InVT);
14995 SmallVector<int,8> ShufMask1(NumElems, -1);
14996 for (unsigned i = 0; i != NumElems/2; ++i)
14999 SDValue OpLo = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask1[0]);
15001 SmallVector<int,8> ShufMask2(NumElems, -1);
15002 for (unsigned i = 0; i != NumElems/2; ++i)
15003 ShufMask2[i] = i + NumElems/2;
15005 SDValue OpHi = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask2[0]);
15007 MVT HalfVT = MVT::getVectorVT(VT.getScalarType(),
15008 VT.getVectorNumElements()/2);
15010 OpLo = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpLo);
15011 OpHi = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpHi);
15013 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
15016 // Lower vector extended loads using a shuffle. If SSSE3 is not available we
15017 // may emit an illegal shuffle but the expansion is still better than scalar
15018 // code. We generate X86ISD::VSEXT for SEXTLOADs if it's available, otherwise
15019 // we'll emit a shuffle and a arithmetic shift.
15020 // FIXME: Is the expansion actually better than scalar code? It doesn't seem so.
15021 // TODO: It is possible to support ZExt by zeroing the undef values during
15022 // the shuffle phase or after the shuffle.
15023 static SDValue LowerExtendedLoad(SDValue Op, const X86Subtarget *Subtarget,
15024 SelectionDAG &DAG) {
15025 MVT RegVT = Op.getSimpleValueType();
15026 assert(RegVT.isVector() && "We only custom lower vector sext loads.");
15027 assert(RegVT.isInteger() &&
15028 "We only custom lower integer vector sext loads.");
15030 // Nothing useful we can do without SSE2 shuffles.
15031 assert(Subtarget->hasSSE2() && "We only custom lower sext loads with SSE2.");
15033 LoadSDNode *Ld = cast<LoadSDNode>(Op.getNode());
15035 EVT MemVT = Ld->getMemoryVT();
15036 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
15037 unsigned RegSz = RegVT.getSizeInBits();
15039 ISD::LoadExtType Ext = Ld->getExtensionType();
15041 assert((Ext == ISD::EXTLOAD || Ext == ISD::SEXTLOAD)
15042 && "Only anyext and sext are currently implemented.");
15043 assert(MemVT != RegVT && "Cannot extend to the same type");
15044 assert(MemVT.isVector() && "Must load a vector from memory");
15046 unsigned NumElems = RegVT.getVectorNumElements();
15047 unsigned MemSz = MemVT.getSizeInBits();
15048 assert(RegSz > MemSz && "Register size must be greater than the mem size");
15050 if (Ext == ISD::SEXTLOAD && RegSz == 256 && !Subtarget->hasInt256()) {
15051 // The only way in which we have a legal 256-bit vector result but not the
15052 // integer 256-bit operations needed to directly lower a sextload is if we
15053 // have AVX1 but not AVX2. In that case, we can always emit a sextload to
15054 // a 128-bit vector and a normal sign_extend to 256-bits that should get
15055 // correctly legalized. We do this late to allow the canonical form of
15056 // sextload to persist throughout the rest of the DAG combiner -- it wants
15057 // to fold together any extensions it can, and so will fuse a sign_extend
15058 // of an sextload into a sextload targeting a wider value.
15060 if (MemSz == 128) {
15061 // Just switch this to a normal load.
15062 assert(TLI.isTypeLegal(MemVT) && "If the memory type is a 128-bit type, "
15063 "it must be a legal 128-bit vector "
15065 Load = DAG.getLoad(MemVT, dl, Ld->getChain(), Ld->getBasePtr(),
15066 Ld->getPointerInfo(), Ld->isVolatile(), Ld->isNonTemporal(),
15067 Ld->isInvariant(), Ld->getAlignment());
15069 assert(MemSz < 128 &&
15070 "Can't extend a type wider than 128 bits to a 256 bit vector!");
15071 // Do an sext load to a 128-bit vector type. We want to use the same
15072 // number of elements, but elements half as wide. This will end up being
15073 // recursively lowered by this routine, but will succeed as we definitely
15074 // have all the necessary features if we're using AVX1.
15076 EVT::getIntegerVT(*DAG.getContext(), RegVT.getScalarSizeInBits() / 2);
15077 EVT HalfVecVT = EVT::getVectorVT(*DAG.getContext(), HalfEltVT, NumElems);
15079 DAG.getExtLoad(Ext, dl, HalfVecVT, Ld->getChain(), Ld->getBasePtr(),
15080 Ld->getPointerInfo(), MemVT, Ld->isVolatile(),
15081 Ld->isNonTemporal(), Ld->isInvariant(),
15082 Ld->getAlignment());
15085 // Replace chain users with the new chain.
15086 assert(Load->getNumValues() == 2 && "Loads must carry a chain!");
15087 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), Load.getValue(1));
15089 // Finally, do a normal sign-extend to the desired register.
15090 return DAG.getSExtOrTrunc(Load, dl, RegVT);
15093 // All sizes must be a power of two.
15094 assert(isPowerOf2_32(RegSz * MemSz * NumElems) &&
15095 "Non-power-of-two elements are not custom lowered!");
15097 // Attempt to load the original value using scalar loads.
15098 // Find the largest scalar type that divides the total loaded size.
15099 MVT SclrLoadTy = MVT::i8;
15100 for (MVT Tp : MVT::integer_valuetypes()) {
15101 if (TLI.isTypeLegal(Tp) && ((MemSz % Tp.getSizeInBits()) == 0)) {
15106 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
15107 if (TLI.isTypeLegal(MVT::f64) && SclrLoadTy.getSizeInBits() < 64 &&
15109 SclrLoadTy = MVT::f64;
15111 // Calculate the number of scalar loads that we need to perform
15112 // in order to load our vector from memory.
15113 unsigned NumLoads = MemSz / SclrLoadTy.getSizeInBits();
15115 assert((Ext != ISD::SEXTLOAD || NumLoads == 1) &&
15116 "Can only lower sext loads with a single scalar load!");
15118 unsigned loadRegZize = RegSz;
15119 if (Ext == ISD::SEXTLOAD && RegSz >= 256)
15122 // Represent our vector as a sequence of elements which are the
15123 // largest scalar that we can load.
15124 EVT LoadUnitVecVT = EVT::getVectorVT(
15125 *DAG.getContext(), SclrLoadTy, loadRegZize / SclrLoadTy.getSizeInBits());
15127 // Represent the data using the same element type that is stored in
15128 // memory. In practice, we ''widen'' MemVT.
15130 EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
15131 loadRegZize / MemVT.getScalarType().getSizeInBits());
15133 assert(WideVecVT.getSizeInBits() == LoadUnitVecVT.getSizeInBits() &&
15134 "Invalid vector type");
15136 // We can't shuffle using an illegal type.
15137 assert(TLI.isTypeLegal(WideVecVT) &&
15138 "We only lower types that form legal widened vector types");
15140 SmallVector<SDValue, 8> Chains;
15141 SDValue Ptr = Ld->getBasePtr();
15142 SDValue Increment = DAG.getConstant(SclrLoadTy.getSizeInBits() / 8, dl,
15143 TLI.getPointerTy(DAG.getDataLayout()));
15144 SDValue Res = DAG.getUNDEF(LoadUnitVecVT);
15146 for (unsigned i = 0; i < NumLoads; ++i) {
15147 // Perform a single load.
15148 SDValue ScalarLoad =
15149 DAG.getLoad(SclrLoadTy, dl, Ld->getChain(), Ptr, Ld->getPointerInfo(),
15150 Ld->isVolatile(), Ld->isNonTemporal(), Ld->isInvariant(),
15151 Ld->getAlignment());
15152 Chains.push_back(ScalarLoad.getValue(1));
15153 // Create the first element type using SCALAR_TO_VECTOR in order to avoid
15154 // another round of DAGCombining.
15156 Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LoadUnitVecVT, ScalarLoad);
15158 Res = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, LoadUnitVecVT, Res,
15159 ScalarLoad, DAG.getIntPtrConstant(i, dl));
15161 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
15164 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
15166 // Bitcast the loaded value to a vector of the original element type, in
15167 // the size of the target vector type.
15168 SDValue SlicedVec = DAG.getBitcast(WideVecVT, Res);
15169 unsigned SizeRatio = RegSz / MemSz;
15171 if (Ext == ISD::SEXTLOAD) {
15172 // If we have SSE4.1, we can directly emit a VSEXT node.
15173 if (Subtarget->hasSSE41()) {
15174 SDValue Sext = DAG.getNode(X86ISD::VSEXT, dl, RegVT, SlicedVec);
15175 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
15179 // Otherwise we'll use SIGN_EXTEND_VECTOR_INREG to sign extend the lowest
15181 assert(TLI.isOperationLegalOrCustom(ISD::SIGN_EXTEND_VECTOR_INREG, RegVT) &&
15182 "We can't implement a sext load without SIGN_EXTEND_VECTOR_INREG!");
15184 SDValue Shuff = DAG.getSignExtendVectorInReg(SlicedVec, dl, RegVT);
15185 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
15189 // Redistribute the loaded elements into the different locations.
15190 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
15191 for (unsigned i = 0; i != NumElems; ++i)
15192 ShuffleVec[i * SizeRatio] = i;
15194 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec,
15195 DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
15197 // Bitcast to the requested type.
15198 Shuff = DAG.getBitcast(RegVT, Shuff);
15199 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
15203 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
15204 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
15205 // from the AND / OR.
15206 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
15207 Opc = Op.getOpcode();
15208 if (Opc != ISD::OR && Opc != ISD::AND)
15210 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
15211 Op.getOperand(0).hasOneUse() &&
15212 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
15213 Op.getOperand(1).hasOneUse());
15216 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
15217 // 1 and that the SETCC node has a single use.
15218 static bool isXor1OfSetCC(SDValue Op) {
15219 if (Op.getOpcode() != ISD::XOR)
15221 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
15222 if (N1C && N1C->getAPIntValue() == 1) {
15223 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
15224 Op.getOperand(0).hasOneUse();
15229 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
15230 bool addTest = true;
15231 SDValue Chain = Op.getOperand(0);
15232 SDValue Cond = Op.getOperand(1);
15233 SDValue Dest = Op.getOperand(2);
15236 bool Inverted = false;
15238 if (Cond.getOpcode() == ISD::SETCC) {
15239 // Check for setcc([su]{add,sub,mul}o == 0).
15240 if (cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETEQ &&
15241 isa<ConstantSDNode>(Cond.getOperand(1)) &&
15242 cast<ConstantSDNode>(Cond.getOperand(1))->isNullValue() &&
15243 Cond.getOperand(0).getResNo() == 1 &&
15244 (Cond.getOperand(0).getOpcode() == ISD::SADDO ||
15245 Cond.getOperand(0).getOpcode() == ISD::UADDO ||
15246 Cond.getOperand(0).getOpcode() == ISD::SSUBO ||
15247 Cond.getOperand(0).getOpcode() == ISD::USUBO ||
15248 Cond.getOperand(0).getOpcode() == ISD::SMULO ||
15249 Cond.getOperand(0).getOpcode() == ISD::UMULO)) {
15251 Cond = Cond.getOperand(0);
15253 SDValue NewCond = LowerSETCC(Cond, DAG);
15254 if (NewCond.getNode())
15259 // FIXME: LowerXALUO doesn't handle these!!
15260 else if (Cond.getOpcode() == X86ISD::ADD ||
15261 Cond.getOpcode() == X86ISD::SUB ||
15262 Cond.getOpcode() == X86ISD::SMUL ||
15263 Cond.getOpcode() == X86ISD::UMUL)
15264 Cond = LowerXALUO(Cond, DAG);
15267 // Look pass (and (setcc_carry (cmp ...)), 1).
15268 if (Cond.getOpcode() == ISD::AND &&
15269 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
15270 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
15271 if (C && C->getAPIntValue() == 1)
15272 Cond = Cond.getOperand(0);
15275 // If condition flag is set by a X86ISD::CMP, then use it as the condition
15276 // setting operand in place of the X86ISD::SETCC.
15277 unsigned CondOpcode = Cond.getOpcode();
15278 if (CondOpcode == X86ISD::SETCC ||
15279 CondOpcode == X86ISD::SETCC_CARRY) {
15280 CC = Cond.getOperand(0);
15282 SDValue Cmp = Cond.getOperand(1);
15283 unsigned Opc = Cmp.getOpcode();
15284 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
15285 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
15289 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
15293 // These can only come from an arithmetic instruction with overflow,
15294 // e.g. SADDO, UADDO.
15295 Cond = Cond.getNode()->getOperand(1);
15301 CondOpcode = Cond.getOpcode();
15302 if (CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
15303 CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
15304 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
15305 Cond.getOperand(0).getValueType() != MVT::i8)) {
15306 SDValue LHS = Cond.getOperand(0);
15307 SDValue RHS = Cond.getOperand(1);
15308 unsigned X86Opcode;
15311 // Keep this in sync with LowerXALUO, otherwise we might create redundant
15312 // instructions that can't be removed afterwards (i.e. X86ISD::ADD and
15314 switch (CondOpcode) {
15315 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
15317 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
15319 X86Opcode = X86ISD::INC; X86Cond = X86::COND_O;
15322 X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
15323 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
15325 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
15327 X86Opcode = X86ISD::DEC; X86Cond = X86::COND_O;
15330 X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
15331 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
15332 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
15333 default: llvm_unreachable("unexpected overflowing operator");
15336 X86Cond = X86::GetOppositeBranchCondition((X86::CondCode)X86Cond);
15337 if (CondOpcode == ISD::UMULO)
15338 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
15341 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
15343 SDValue X86Op = DAG.getNode(X86Opcode, dl, VTs, LHS, RHS);
15345 if (CondOpcode == ISD::UMULO)
15346 Cond = X86Op.getValue(2);
15348 Cond = X86Op.getValue(1);
15350 CC = DAG.getConstant(X86Cond, dl, MVT::i8);
15354 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
15355 SDValue Cmp = Cond.getOperand(0).getOperand(1);
15356 if (CondOpc == ISD::OR) {
15357 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
15358 // two branches instead of an explicit OR instruction with a
15360 if (Cmp == Cond.getOperand(1).getOperand(1) &&
15361 isX86LogicalCmp(Cmp)) {
15362 CC = Cond.getOperand(0).getOperand(0);
15363 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15364 Chain, Dest, CC, Cmp);
15365 CC = Cond.getOperand(1).getOperand(0);
15369 } else { // ISD::AND
15370 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
15371 // two branches instead of an explicit AND instruction with a
15372 // separate test. However, we only do this if this block doesn't
15373 // have a fall-through edge, because this requires an explicit
15374 // jmp when the condition is false.
15375 if (Cmp == Cond.getOperand(1).getOperand(1) &&
15376 isX86LogicalCmp(Cmp) &&
15377 Op.getNode()->hasOneUse()) {
15378 X86::CondCode CCode =
15379 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
15380 CCode = X86::GetOppositeBranchCondition(CCode);
15381 CC = DAG.getConstant(CCode, dl, MVT::i8);
15382 SDNode *User = *Op.getNode()->use_begin();
15383 // Look for an unconditional branch following this conditional branch.
15384 // We need this because we need to reverse the successors in order
15385 // to implement FCMP_OEQ.
15386 if (User->getOpcode() == ISD::BR) {
15387 SDValue FalseBB = User->getOperand(1);
15389 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
15390 assert(NewBR == User);
15394 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15395 Chain, Dest, CC, Cmp);
15396 X86::CondCode CCode =
15397 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
15398 CCode = X86::GetOppositeBranchCondition(CCode);
15399 CC = DAG.getConstant(CCode, dl, MVT::i8);
15405 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
15406 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
15407 // It should be transformed during dag combiner except when the condition
15408 // is set by a arithmetics with overflow node.
15409 X86::CondCode CCode =
15410 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
15411 CCode = X86::GetOppositeBranchCondition(CCode);
15412 CC = DAG.getConstant(CCode, dl, MVT::i8);
15413 Cond = Cond.getOperand(0).getOperand(1);
15415 } else if (Cond.getOpcode() == ISD::SETCC &&
15416 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETOEQ) {
15417 // For FCMP_OEQ, we can emit
15418 // two branches instead of an explicit AND instruction with a
15419 // separate test. However, we only do this if this block doesn't
15420 // have a fall-through edge, because this requires an explicit
15421 // jmp when the condition is false.
15422 if (Op.getNode()->hasOneUse()) {
15423 SDNode *User = *Op.getNode()->use_begin();
15424 // Look for an unconditional branch following this conditional branch.
15425 // We need this because we need to reverse the successors in order
15426 // to implement FCMP_OEQ.
15427 if (User->getOpcode() == ISD::BR) {
15428 SDValue FalseBB = User->getOperand(1);
15430 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
15431 assert(NewBR == User);
15435 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
15436 Cond.getOperand(0), Cond.getOperand(1));
15437 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
15438 CC = DAG.getConstant(X86::COND_NE, dl, MVT::i8);
15439 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15440 Chain, Dest, CC, Cmp);
15441 CC = DAG.getConstant(X86::COND_P, dl, MVT::i8);
15446 } else if (Cond.getOpcode() == ISD::SETCC &&
15447 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETUNE) {
15448 // For FCMP_UNE, we can emit
15449 // two branches instead of an explicit AND instruction with a
15450 // separate test. However, we only do this if this block doesn't
15451 // have a fall-through edge, because this requires an explicit
15452 // jmp when the condition is false.
15453 if (Op.getNode()->hasOneUse()) {
15454 SDNode *User = *Op.getNode()->use_begin();
15455 // Look for an unconditional branch following this conditional branch.
15456 // We need this because we need to reverse the successors in order
15457 // to implement FCMP_UNE.
15458 if (User->getOpcode() == ISD::BR) {
15459 SDValue FalseBB = User->getOperand(1);
15461 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
15462 assert(NewBR == User);
15465 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
15466 Cond.getOperand(0), Cond.getOperand(1));
15467 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
15468 CC = DAG.getConstant(X86::COND_NE, dl, MVT::i8);
15469 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15470 Chain, Dest, CC, Cmp);
15471 CC = DAG.getConstant(X86::COND_NP, dl, MVT::i8);
15481 // Look pass the truncate if the high bits are known zero.
15482 if (isTruncWithZeroHighBitsInput(Cond, DAG))
15483 Cond = Cond.getOperand(0);
15485 // We know the result of AND is compared against zero. Try to match
15487 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
15488 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
15489 if (NewSetCC.getNode()) {
15490 CC = NewSetCC.getOperand(0);
15491 Cond = NewSetCC.getOperand(1);
15498 X86::CondCode X86Cond = Inverted ? X86::COND_E : X86::COND_NE;
15499 CC = DAG.getConstant(X86Cond, dl, MVT::i8);
15500 Cond = EmitTest(Cond, X86Cond, dl, DAG);
15502 Cond = ConvertCmpIfNecessary(Cond, DAG);
15503 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15504 Chain, Dest, CC, Cond);
15507 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
15508 // Calls to _alloca are needed to probe the stack when allocating more than 4k
15509 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
15510 // that the guard pages used by the OS virtual memory manager are allocated in
15511 // correct sequence.
15513 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
15514 SelectionDAG &DAG) const {
15515 MachineFunction &MF = DAG.getMachineFunction();
15516 bool SplitStack = MF.shouldSplitStack();
15517 bool Lower = (Subtarget->isOSWindows() && !Subtarget->isTargetMachO()) ||
15522 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
15523 SDNode* Node = Op.getNode();
15525 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
15526 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
15527 " not tell us which reg is the stack pointer!");
15528 EVT VT = Node->getValueType(0);
15529 SDValue Tmp1 = SDValue(Node, 0);
15530 SDValue Tmp2 = SDValue(Node, 1);
15531 SDValue Tmp3 = Node->getOperand(2);
15532 SDValue Chain = Tmp1.getOperand(0);
15534 // Chain the dynamic stack allocation so that it doesn't modify the stack
15535 // pointer when other instructions are using the stack.
15536 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, dl, true),
15539 SDValue Size = Tmp2.getOperand(1);
15540 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT);
15541 Chain = SP.getValue(1);
15542 unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue();
15543 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
15544 unsigned StackAlign = TFI.getStackAlignment();
15545 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value
15546 if (Align > StackAlign)
15547 Tmp1 = DAG.getNode(ISD::AND, dl, VT, Tmp1,
15548 DAG.getConstant(-(uint64_t)Align, dl, VT));
15549 Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); // Output chain
15551 Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, dl, true),
15552 DAG.getIntPtrConstant(0, dl, true), SDValue(),
15555 SDValue Ops[2] = { Tmp1, Tmp2 };
15556 return DAG.getMergeValues(Ops, dl);
15560 SDValue Chain = Op.getOperand(0);
15561 SDValue Size = Op.getOperand(1);
15562 unsigned Align = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
15563 EVT VT = Op.getNode()->getValueType(0);
15565 bool Is64Bit = Subtarget->is64Bit();
15566 MVT SPTy = getPointerTy(DAG.getDataLayout());
15569 MachineRegisterInfo &MRI = MF.getRegInfo();
15572 // The 64 bit implementation of segmented stacks needs to clobber both r10
15573 // r11. This makes it impossible to use it along with nested parameters.
15574 const Function *F = MF.getFunction();
15576 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
15578 if (I->hasNestAttr())
15579 report_fatal_error("Cannot use segmented stacks with functions that "
15580 "have nested arguments.");
15583 const TargetRegisterClass *AddrRegClass = getRegClassFor(SPTy);
15584 unsigned Vreg = MRI.createVirtualRegister(AddrRegClass);
15585 Chain = DAG.getCopyToReg(Chain, dl, Vreg, Size);
15586 SDValue Value = DAG.getNode(X86ISD::SEG_ALLOCA, dl, SPTy, Chain,
15587 DAG.getRegister(Vreg, SPTy));
15588 SDValue Ops1[2] = { Value, Chain };
15589 return DAG.getMergeValues(Ops1, dl);
15592 const unsigned Reg = (Subtarget->isTarget64BitLP64() ? X86::RAX : X86::EAX);
15594 Chain = DAG.getCopyToReg(Chain, dl, Reg, Size, Flag);
15595 Flag = Chain.getValue(1);
15596 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
15598 Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag);
15600 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
15601 unsigned SPReg = RegInfo->getStackRegister();
15602 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, SPTy);
15603 Chain = SP.getValue(1);
15606 SP = DAG.getNode(ISD::AND, dl, VT, SP.getValue(0),
15607 DAG.getConstant(-(uint64_t)Align, dl, VT));
15608 Chain = DAG.getCopyToReg(Chain, dl, SPReg, SP);
15611 SDValue Ops1[2] = { SP, Chain };
15612 return DAG.getMergeValues(Ops1, dl);
15616 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
15617 MachineFunction &MF = DAG.getMachineFunction();
15618 auto PtrVT = getPointerTy(MF.getDataLayout());
15619 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
15621 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
15624 if (!Subtarget->is64Bit() ||
15625 Subtarget->isCallingConvWin64(MF.getFunction()->getCallingConv())) {
15626 // vastart just stores the address of the VarArgsFrameIndex slot into the
15627 // memory location argument.
15628 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
15629 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
15630 MachinePointerInfo(SV), false, false, 0);
15634 // gp_offset (0 - 6 * 8)
15635 // fp_offset (48 - 48 + 8 * 16)
15636 // overflow_arg_area (point to parameters coming in memory).
15638 SmallVector<SDValue, 8> MemOps;
15639 SDValue FIN = Op.getOperand(1);
15641 SDValue Store = DAG.getStore(Op.getOperand(0), DL,
15642 DAG.getConstant(FuncInfo->getVarArgsGPOffset(),
15644 FIN, MachinePointerInfo(SV), false, false, 0);
15645 MemOps.push_back(Store);
15648 FIN = DAG.getNode(ISD::ADD, DL, PtrVT, FIN, DAG.getIntPtrConstant(4, DL));
15649 Store = DAG.getStore(Op.getOperand(0), DL,
15650 DAG.getConstant(FuncInfo->getVarArgsFPOffset(), DL,
15652 FIN, MachinePointerInfo(SV, 4), false, false, 0);
15653 MemOps.push_back(Store);
15655 // Store ptr to overflow_arg_area
15656 FIN = DAG.getNode(ISD::ADD, DL, PtrVT, FIN, DAG.getIntPtrConstant(4, DL));
15657 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
15658 Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN,
15659 MachinePointerInfo(SV, 8),
15661 MemOps.push_back(Store);
15663 // Store ptr to reg_save_area.
15664 FIN = DAG.getNode(ISD::ADD, DL, PtrVT, FIN, DAG.getIntPtrConstant(
15665 Subtarget->isTarget64BitLP64() ? 8 : 4, DL));
15666 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(), PtrVT);
15667 Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN, MachinePointerInfo(
15668 SV, Subtarget->isTarget64BitLP64() ? 16 : 12), false, false, 0);
15669 MemOps.push_back(Store);
15670 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps);
15673 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
15674 assert(Subtarget->is64Bit() &&
15675 "LowerVAARG only handles 64-bit va_arg!");
15676 assert(Op.getNode()->getNumOperands() == 4);
15678 MachineFunction &MF = DAG.getMachineFunction();
15679 if (Subtarget->isCallingConvWin64(MF.getFunction()->getCallingConv()))
15680 // The Win64 ABI uses char* instead of a structure.
15681 return DAG.expandVAArg(Op.getNode());
15683 SDValue Chain = Op.getOperand(0);
15684 SDValue SrcPtr = Op.getOperand(1);
15685 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
15686 unsigned Align = Op.getConstantOperandVal(3);
15689 EVT ArgVT = Op.getNode()->getValueType(0);
15690 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
15691 uint32_t ArgSize = DAG.getDataLayout().getTypeAllocSize(ArgTy);
15694 // Decide which area this value should be read from.
15695 // TODO: Implement the AMD64 ABI in its entirety. This simple
15696 // selection mechanism works only for the basic types.
15697 if (ArgVT == MVT::f80) {
15698 llvm_unreachable("va_arg for f80 not yet implemented");
15699 } else if (ArgVT.isFloatingPoint() && ArgSize <= 16 /*bytes*/) {
15700 ArgMode = 2; // Argument passed in XMM register. Use fp_offset.
15701 } else if (ArgVT.isInteger() && ArgSize <= 32 /*bytes*/) {
15702 ArgMode = 1; // Argument passed in GPR64 register(s). Use gp_offset.
15704 llvm_unreachable("Unhandled argument type in LowerVAARG");
15707 if (ArgMode == 2) {
15708 // Sanity Check: Make sure using fp_offset makes sense.
15709 assert(!Subtarget->useSoftFloat() &&
15710 !(MF.getFunction()->hasFnAttribute(Attribute::NoImplicitFloat)) &&
15711 Subtarget->hasSSE1());
15714 // Insert VAARG_64 node into the DAG
15715 // VAARG_64 returns two values: Variable Argument Address, Chain
15716 SDValue InstOps[] = {Chain, SrcPtr, DAG.getConstant(ArgSize, dl, MVT::i32),
15717 DAG.getConstant(ArgMode, dl, MVT::i8),
15718 DAG.getConstant(Align, dl, MVT::i32)};
15719 SDVTList VTs = DAG.getVTList(getPointerTy(DAG.getDataLayout()), MVT::Other);
15720 SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl,
15721 VTs, InstOps, MVT::i64,
15722 MachinePointerInfo(SV),
15724 /*Volatile=*/false,
15726 /*WriteMem=*/true);
15727 Chain = VAARG.getValue(1);
15729 // Load the next argument and return it
15730 return DAG.getLoad(ArgVT, dl,
15733 MachinePointerInfo(),
15734 false, false, false, 0);
15737 static SDValue LowerVACOPY(SDValue Op, const X86Subtarget *Subtarget,
15738 SelectionDAG &DAG) {
15739 // X86-64 va_list is a struct { i32, i32, i8*, i8* }, except on Windows,
15740 // where a va_list is still an i8*.
15741 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
15742 if (Subtarget->isCallingConvWin64(
15743 DAG.getMachineFunction().getFunction()->getCallingConv()))
15744 // Probably a Win64 va_copy.
15745 return DAG.expandVACopy(Op.getNode());
15747 SDValue Chain = Op.getOperand(0);
15748 SDValue DstPtr = Op.getOperand(1);
15749 SDValue SrcPtr = Op.getOperand(2);
15750 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
15751 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
15754 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr,
15755 DAG.getIntPtrConstant(24, DL), 8, /*isVolatile*/false,
15757 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
15760 // getTargetVShiftByConstNode - Handle vector element shifts where the shift
15761 // amount is a constant. Takes immediate version of shift as input.
15762 static SDValue getTargetVShiftByConstNode(unsigned Opc, SDLoc dl, MVT VT,
15763 SDValue SrcOp, uint64_t ShiftAmt,
15764 SelectionDAG &DAG) {
15765 MVT ElementType = VT.getVectorElementType();
15767 // Fold this packed shift into its first operand if ShiftAmt is 0.
15771 // Check for ShiftAmt >= element width
15772 if (ShiftAmt >= ElementType.getSizeInBits()) {
15773 if (Opc == X86ISD::VSRAI)
15774 ShiftAmt = ElementType.getSizeInBits() - 1;
15776 return DAG.getConstant(0, dl, VT);
15779 assert((Opc == X86ISD::VSHLI || Opc == X86ISD::VSRLI || Opc == X86ISD::VSRAI)
15780 && "Unknown target vector shift-by-constant node");
15782 // Fold this packed vector shift into a build vector if SrcOp is a
15783 // vector of Constants or UNDEFs, and SrcOp valuetype is the same as VT.
15784 if (VT == SrcOp.getSimpleValueType() &&
15785 ISD::isBuildVectorOfConstantSDNodes(SrcOp.getNode())) {
15786 SmallVector<SDValue, 8> Elts;
15787 unsigned NumElts = SrcOp->getNumOperands();
15788 ConstantSDNode *ND;
15791 default: llvm_unreachable(nullptr);
15792 case X86ISD::VSHLI:
15793 for (unsigned i=0; i!=NumElts; ++i) {
15794 SDValue CurrentOp = SrcOp->getOperand(i);
15795 if (CurrentOp->getOpcode() == ISD::UNDEF) {
15796 Elts.push_back(CurrentOp);
15799 ND = cast<ConstantSDNode>(CurrentOp);
15800 const APInt &C = ND->getAPIntValue();
15801 Elts.push_back(DAG.getConstant(C.shl(ShiftAmt), dl, ElementType));
15804 case X86ISD::VSRLI:
15805 for (unsigned i=0; i!=NumElts; ++i) {
15806 SDValue CurrentOp = SrcOp->getOperand(i);
15807 if (CurrentOp->getOpcode() == ISD::UNDEF) {
15808 Elts.push_back(CurrentOp);
15811 ND = cast<ConstantSDNode>(CurrentOp);
15812 const APInt &C = ND->getAPIntValue();
15813 Elts.push_back(DAG.getConstant(C.lshr(ShiftAmt), dl, ElementType));
15816 case X86ISD::VSRAI:
15817 for (unsigned i=0; i!=NumElts; ++i) {
15818 SDValue CurrentOp = SrcOp->getOperand(i);
15819 if (CurrentOp->getOpcode() == ISD::UNDEF) {
15820 Elts.push_back(CurrentOp);
15823 ND = cast<ConstantSDNode>(CurrentOp);
15824 const APInt &C = ND->getAPIntValue();
15825 Elts.push_back(DAG.getConstant(C.ashr(ShiftAmt), dl, ElementType));
15830 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
15833 return DAG.getNode(Opc, dl, VT, SrcOp,
15834 DAG.getConstant(ShiftAmt, dl, MVT::i8));
15837 // getTargetVShiftNode - Handle vector element shifts where the shift amount
15838 // may or may not be a constant. Takes immediate version of shift as input.
15839 static SDValue getTargetVShiftNode(unsigned Opc, SDLoc dl, MVT VT,
15840 SDValue SrcOp, SDValue ShAmt,
15841 SelectionDAG &DAG) {
15842 MVT SVT = ShAmt.getSimpleValueType();
15843 assert((SVT == MVT::i32 || SVT == MVT::i64) && "Unexpected value type!");
15845 // Catch shift-by-constant.
15846 if (ConstantSDNode *CShAmt = dyn_cast<ConstantSDNode>(ShAmt))
15847 return getTargetVShiftByConstNode(Opc, dl, VT, SrcOp,
15848 CShAmt->getZExtValue(), DAG);
15850 // Change opcode to non-immediate version
15852 default: llvm_unreachable("Unknown target vector shift node");
15853 case X86ISD::VSHLI: Opc = X86ISD::VSHL; break;
15854 case X86ISD::VSRLI: Opc = X86ISD::VSRL; break;
15855 case X86ISD::VSRAI: Opc = X86ISD::VSRA; break;
15858 const X86Subtarget &Subtarget =
15859 static_cast<const X86Subtarget &>(DAG.getSubtarget());
15860 if (Subtarget.hasSSE41() && ShAmt.getOpcode() == ISD::ZERO_EXTEND &&
15861 ShAmt.getOperand(0).getSimpleValueType() == MVT::i16) {
15862 // Let the shuffle legalizer expand this shift amount node.
15863 SDValue Op0 = ShAmt.getOperand(0);
15864 Op0 = DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(Op0), MVT::v8i16, Op0);
15865 ShAmt = getShuffleVectorZeroOrUndef(Op0, 0, true, &Subtarget, DAG);
15867 // Need to build a vector containing shift amount.
15868 // SSE/AVX packed shifts only use the lower 64-bit of the shift count.
15869 SmallVector<SDValue, 4> ShOps;
15870 ShOps.push_back(ShAmt);
15871 if (SVT == MVT::i32) {
15872 ShOps.push_back(DAG.getConstant(0, dl, SVT));
15873 ShOps.push_back(DAG.getUNDEF(SVT));
15875 ShOps.push_back(DAG.getUNDEF(SVT));
15877 MVT BVT = SVT == MVT::i32 ? MVT::v4i32 : MVT::v2i64;
15878 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, BVT, ShOps);
15881 // The return type has to be a 128-bit type with the same element
15882 // type as the input type.
15883 MVT EltVT = VT.getVectorElementType();
15884 EVT ShVT = MVT::getVectorVT(EltVT, 128/EltVT.getSizeInBits());
15886 ShAmt = DAG.getBitcast(ShVT, ShAmt);
15887 return DAG.getNode(Opc, dl, VT, SrcOp, ShAmt);
15890 /// \brief Return (and \p Op, \p Mask) for compare instructions or
15891 /// (vselect \p Mask, \p Op, \p PreservedSrc) for others along with the
15892 /// necessary casting or extending for \p Mask when lowering masking intrinsics
15893 static SDValue getVectorMaskingNode(SDValue Op, SDValue Mask,
15894 SDValue PreservedSrc,
15895 const X86Subtarget *Subtarget,
15896 SelectionDAG &DAG) {
15897 EVT VT = Op.getValueType();
15898 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(),
15899 MVT::i1, VT.getVectorNumElements());
15900 SDValue VMask = SDValue();
15901 unsigned OpcodeSelect = ISD::VSELECT;
15904 assert(MaskVT.isSimple() && "invalid mask type");
15906 if (isAllOnes(Mask))
15909 if (MaskVT.bitsGT(Mask.getValueType())) {
15910 EVT newMaskVT = EVT::getIntegerVT(*DAG.getContext(),
15911 MaskVT.getSizeInBits());
15912 VMask = DAG.getBitcast(MaskVT,
15913 DAG.getNode(ISD::ANY_EXTEND, dl, newMaskVT, Mask));
15915 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
15916 Mask.getValueType().getSizeInBits());
15917 // In case when MaskVT equals v2i1 or v4i1, low 2 or 4 elements
15918 // are extracted by EXTRACT_SUBVECTOR.
15919 VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
15920 DAG.getBitcast(BitcastVT, Mask),
15921 DAG.getIntPtrConstant(0, dl));
15924 switch (Op.getOpcode()) {
15926 case X86ISD::PCMPEQM:
15927 case X86ISD::PCMPGTM:
15929 case X86ISD::CMPMU:
15930 return DAG.getNode(ISD::AND, dl, VT, Op, VMask);
15931 case X86ISD::VFPCLASS:
15932 return DAG.getNode(ISD::OR, dl, VT, Op, VMask);
15933 case X86ISD::VTRUNC:
15934 case X86ISD::VTRUNCS:
15935 case X86ISD::VTRUNCUS:
15936 // We can't use ISD::VSELECT here because it is not always "Legal"
15937 // for the destination type. For example vpmovqb require only AVX512
15938 // and vselect that can operate on byte element type require BWI
15939 OpcodeSelect = X86ISD::SELECT;
15942 if (PreservedSrc.getOpcode() == ISD::UNDEF)
15943 PreservedSrc = getZeroVector(VT, Subtarget, DAG, dl);
15944 return DAG.getNode(OpcodeSelect, dl, VT, VMask, Op, PreservedSrc);
15947 /// \brief Creates an SDNode for a predicated scalar operation.
15948 /// \returns (X86vselect \p Mask, \p Op, \p PreservedSrc).
15949 /// The mask is coming as MVT::i8 and it should be truncated
15950 /// to MVT::i1 while lowering masking intrinsics.
15951 /// The main difference between ScalarMaskingNode and VectorMaskingNode is using
15952 /// "X86select" instead of "vselect". We just can't create the "vselect" node
15953 /// for a scalar instruction.
15954 static SDValue getScalarMaskingNode(SDValue Op, SDValue Mask,
15955 SDValue PreservedSrc,
15956 const X86Subtarget *Subtarget,
15957 SelectionDAG &DAG) {
15958 if (isAllOnes(Mask))
15961 EVT VT = Op.getValueType();
15963 // The mask should be of type MVT::i1
15964 SDValue IMask = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, Mask);
15966 if (Op.getOpcode() == X86ISD::FSETCC)
15967 return DAG.getNode(ISD::AND, dl, VT, Op, IMask);
15968 if (Op.getOpcode() == X86ISD::VFPCLASS)
15969 return DAG.getNode(ISD::OR, dl, VT, Op, IMask);
15971 if (PreservedSrc.getOpcode() == ISD::UNDEF)
15972 PreservedSrc = getZeroVector(VT, Subtarget, DAG, dl);
15973 return DAG.getNode(X86ISD::SELECT, dl, VT, IMask, Op, PreservedSrc);
15976 static int getSEHRegistrationNodeSize(const Function *Fn) {
15977 if (!Fn->hasPersonalityFn())
15978 report_fatal_error(
15979 "querying registration node size for function without personality");
15980 // The RegNodeSize is 6 32-bit words for SEH and 4 for C++ EH. See
15981 // WinEHStatePass for the full struct definition.
15982 switch (classifyEHPersonality(Fn->getPersonalityFn())) {
15983 case EHPersonality::MSVC_X86SEH: return 24;
15984 case EHPersonality::MSVC_CXX: return 16;
15987 report_fatal_error("can only recover FP for MSVC EH personality functions");
15990 /// When the 32-bit MSVC runtime transfers control to us, either to an outlined
15991 /// function or when returning to a parent frame after catching an exception, we
15992 /// recover the parent frame pointer by doing arithmetic on the incoming EBP.
15993 /// Here's the math:
15994 /// RegNodeBase = EntryEBP - RegNodeSize
15995 /// ParentFP = RegNodeBase - RegNodeFrameOffset
15996 /// Subtracting RegNodeSize takes us to the offset of the registration node, and
15997 /// subtracting the offset (negative on x86) takes us back to the parent FP.
15998 static SDValue recoverFramePointer(SelectionDAG &DAG, const Function *Fn,
15999 SDValue EntryEBP) {
16000 MachineFunction &MF = DAG.getMachineFunction();
16003 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
16004 MVT PtrVT = TLI.getPointerTy(DAG.getDataLayout());
16006 // It's possible that the parent function no longer has a personality function
16007 // if the exceptional code was optimized away, in which case we just return
16008 // the incoming EBP.
16009 if (!Fn->hasPersonalityFn())
16012 int RegNodeSize = getSEHRegistrationNodeSize(Fn);
16014 // Get an MCSymbol that will ultimately resolve to the frame offset of the EH
16016 MCSymbol *OffsetSym =
16017 MF.getMMI().getContext().getOrCreateParentFrameOffsetSymbol(
16018 GlobalValue::getRealLinkageName(Fn->getName()));
16019 SDValue OffsetSymVal = DAG.getMCSymbol(OffsetSym, PtrVT);
16020 SDValue RegNodeFrameOffset =
16021 DAG.getNode(ISD::LOCAL_RECOVER, dl, PtrVT, OffsetSymVal);
16023 // RegNodeBase = EntryEBP - RegNodeSize
16024 // ParentFP = RegNodeBase - RegNodeFrameOffset
16025 SDValue RegNodeBase = DAG.getNode(ISD::SUB, dl, PtrVT, EntryEBP,
16026 DAG.getConstant(RegNodeSize, dl, PtrVT));
16027 return DAG.getNode(ISD::SUB, dl, PtrVT, RegNodeBase, RegNodeFrameOffset);
16030 static SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
16031 SelectionDAG &DAG) {
16033 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
16034 EVT VT = Op.getValueType();
16035 const IntrinsicData* IntrData = getIntrinsicWithoutChain(IntNo);
16037 switch(IntrData->Type) {
16038 case INTR_TYPE_1OP:
16039 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1));
16040 case INTR_TYPE_2OP:
16041 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
16043 case INTR_TYPE_2OP_IMM8:
16044 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
16045 DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op.getOperand(2)));
16046 case INTR_TYPE_3OP:
16047 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
16048 Op.getOperand(2), Op.getOperand(3));
16049 case INTR_TYPE_4OP:
16050 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
16051 Op.getOperand(2), Op.getOperand(3), Op.getOperand(4));
16052 case INTR_TYPE_1OP_MASK_RM: {
16053 SDValue Src = Op.getOperand(1);
16054 SDValue PassThru = Op.getOperand(2);
16055 SDValue Mask = Op.getOperand(3);
16056 SDValue RoundingMode;
16057 // We allways add rounding mode to the Node.
16058 // If the rounding mode is not specified, we add the
16059 // "current direction" mode.
16060 if (Op.getNumOperands() == 4)
16062 DAG.getConstant(X86::STATIC_ROUNDING::CUR_DIRECTION, dl, MVT::i32);
16064 RoundingMode = Op.getOperand(4);
16065 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1;
16066 if (IntrWithRoundingModeOpcode != 0)
16067 if (cast<ConstantSDNode>(RoundingMode)->getZExtValue() !=
16068 X86::STATIC_ROUNDING::CUR_DIRECTION)
16069 return getVectorMaskingNode(DAG.getNode(IntrWithRoundingModeOpcode,
16070 dl, Op.getValueType(), Src, RoundingMode),
16071 Mask, PassThru, Subtarget, DAG);
16072 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src,
16074 Mask, PassThru, Subtarget, DAG);
16076 case INTR_TYPE_1OP_MASK: {
16077 SDValue Src = Op.getOperand(1);
16078 SDValue PassThru = Op.getOperand(2);
16079 SDValue Mask = Op.getOperand(3);
16080 // We add rounding mode to the Node when
16081 // - RM Opcode is specified and
16082 // - RM is not "current direction".
16083 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1;
16084 if (IntrWithRoundingModeOpcode != 0) {
16085 SDValue Rnd = Op.getOperand(4);
16086 unsigned Round = cast<ConstantSDNode>(Rnd)->getZExtValue();
16087 if (Round != X86::STATIC_ROUNDING::CUR_DIRECTION) {
16088 return getVectorMaskingNode(DAG.getNode(IntrWithRoundingModeOpcode,
16089 dl, Op.getValueType(),
16091 Mask, PassThru, Subtarget, DAG);
16094 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src),
16095 Mask, PassThru, Subtarget, DAG);
16097 case INTR_TYPE_SCALAR_MASK: {
16098 SDValue Src1 = Op.getOperand(1);
16099 SDValue Src2 = Op.getOperand(2);
16100 SDValue passThru = Op.getOperand(3);
16101 SDValue Mask = Op.getOperand(4);
16102 return getScalarMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src1, Src2),
16103 Mask, passThru, Subtarget, DAG);
16105 case INTR_TYPE_SCALAR_MASK_RM: {
16106 SDValue Src1 = Op.getOperand(1);
16107 SDValue Src2 = Op.getOperand(2);
16108 SDValue Src0 = Op.getOperand(3);
16109 SDValue Mask = Op.getOperand(4);
16110 // There are 2 kinds of intrinsics in this group:
16111 // (1) With suppress-all-exceptions (sae) or rounding mode- 6 operands
16112 // (2) With rounding mode and sae - 7 operands.
16113 if (Op.getNumOperands() == 6) {
16114 SDValue Sae = Op.getOperand(5);
16115 unsigned Opc = IntrData->Opc1 ? IntrData->Opc1 : IntrData->Opc0;
16116 return getScalarMaskingNode(DAG.getNode(Opc, dl, VT, Src1, Src2,
16118 Mask, Src0, Subtarget, DAG);
16120 assert(Op.getNumOperands() == 7 && "Unexpected intrinsic form");
16121 SDValue RoundingMode = Op.getOperand(5);
16122 SDValue Sae = Op.getOperand(6);
16123 return getScalarMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src1, Src2,
16124 RoundingMode, Sae),
16125 Mask, Src0, Subtarget, DAG);
16127 case INTR_TYPE_2OP_MASK:
16128 case INTR_TYPE_2OP_IMM8_MASK: {
16129 SDValue Src1 = Op.getOperand(1);
16130 SDValue Src2 = Op.getOperand(2);
16131 SDValue PassThru = Op.getOperand(3);
16132 SDValue Mask = Op.getOperand(4);
16134 if (IntrData->Type == INTR_TYPE_2OP_IMM8_MASK)
16135 Src2 = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Src2);
16137 // We specify 2 possible opcodes for intrinsics with rounding modes.
16138 // First, we check if the intrinsic may have non-default rounding mode,
16139 // (IntrData->Opc1 != 0), then we check the rounding mode operand.
16140 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1;
16141 if (IntrWithRoundingModeOpcode != 0) {
16142 SDValue Rnd = Op.getOperand(5);
16143 unsigned Round = cast<ConstantSDNode>(Rnd)->getZExtValue();
16144 if (Round != X86::STATIC_ROUNDING::CUR_DIRECTION) {
16145 return getVectorMaskingNode(DAG.getNode(IntrWithRoundingModeOpcode,
16146 dl, Op.getValueType(),
16148 Mask, PassThru, Subtarget, DAG);
16151 // TODO: Intrinsics should have fast-math-flags to propagate.
16152 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT,Src1,Src2),
16153 Mask, PassThru, Subtarget, DAG);
16155 case INTR_TYPE_2OP_MASK_RM: {
16156 SDValue Src1 = Op.getOperand(1);
16157 SDValue Src2 = Op.getOperand(2);
16158 SDValue PassThru = Op.getOperand(3);
16159 SDValue Mask = Op.getOperand(4);
16160 // We specify 2 possible modes for intrinsics, with/without rounding
16162 // First, we check if the intrinsic have rounding mode (6 operands),
16163 // if not, we set rounding mode to "current".
16165 if (Op.getNumOperands() == 6)
16166 Rnd = Op.getOperand(5);
16168 Rnd = DAG.getConstant(X86::STATIC_ROUNDING::CUR_DIRECTION, dl, MVT::i32);
16169 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT,
16171 Mask, PassThru, Subtarget, DAG);
16173 case INTR_TYPE_3OP_SCALAR_MASK_RM: {
16174 SDValue Src1 = Op.getOperand(1);
16175 SDValue Src2 = Op.getOperand(2);
16176 SDValue Src3 = Op.getOperand(3);
16177 SDValue PassThru = Op.getOperand(4);
16178 SDValue Mask = Op.getOperand(5);
16179 SDValue Sae = Op.getOperand(6);
16181 return getScalarMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src1,
16183 Mask, PassThru, Subtarget, DAG);
16185 case INTR_TYPE_3OP_MASK_RM: {
16186 SDValue Src1 = Op.getOperand(1);
16187 SDValue Src2 = Op.getOperand(2);
16188 SDValue Imm = Op.getOperand(3);
16189 SDValue PassThru = Op.getOperand(4);
16190 SDValue Mask = Op.getOperand(5);
16191 // We specify 2 possible modes for intrinsics, with/without rounding
16193 // First, we check if the intrinsic have rounding mode (7 operands),
16194 // if not, we set rounding mode to "current".
16196 if (Op.getNumOperands() == 7)
16197 Rnd = Op.getOperand(6);
16199 Rnd = DAG.getConstant(X86::STATIC_ROUNDING::CUR_DIRECTION, dl, MVT::i32);
16200 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT,
16201 Src1, Src2, Imm, Rnd),
16202 Mask, PassThru, Subtarget, DAG);
16204 case INTR_TYPE_3OP_IMM8_MASK:
16205 case INTR_TYPE_3OP_MASK:
16206 case INSERT_SUBVEC: {
16207 SDValue Src1 = Op.getOperand(1);
16208 SDValue Src2 = Op.getOperand(2);
16209 SDValue Src3 = Op.getOperand(3);
16210 SDValue PassThru = Op.getOperand(4);
16211 SDValue Mask = Op.getOperand(5);
16213 if (IntrData->Type == INTR_TYPE_3OP_IMM8_MASK)
16214 Src3 = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Src3);
16215 else if (IntrData->Type == INSERT_SUBVEC) {
16216 // imm should be adapted to ISD::INSERT_SUBVECTOR behavior
16217 assert(isa<ConstantSDNode>(Src3) && "Expected a ConstantSDNode here!");
16218 unsigned Imm = cast<ConstantSDNode>(Src3)->getZExtValue();
16219 Imm *= Src2.getValueType().getVectorNumElements();
16220 Src3 = DAG.getTargetConstant(Imm, dl, MVT::i32);
16223 // We specify 2 possible opcodes for intrinsics with rounding modes.
16224 // First, we check if the intrinsic may have non-default rounding mode,
16225 // (IntrData->Opc1 != 0), then we check the rounding mode operand.
16226 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1;
16227 if (IntrWithRoundingModeOpcode != 0) {
16228 SDValue Rnd = Op.getOperand(6);
16229 unsigned Round = cast<ConstantSDNode>(Rnd)->getZExtValue();
16230 if (Round != X86::STATIC_ROUNDING::CUR_DIRECTION) {
16231 return getVectorMaskingNode(DAG.getNode(IntrWithRoundingModeOpcode,
16232 dl, Op.getValueType(),
16233 Src1, Src2, Src3, Rnd),
16234 Mask, PassThru, Subtarget, DAG);
16237 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT,
16239 Mask, PassThru, Subtarget, DAG);
16241 case VPERM_3OP_MASKZ:
16242 case VPERM_3OP_MASK:
16245 case FMA_OP_MASK: {
16246 SDValue Src1 = Op.getOperand(1);
16247 SDValue Src2 = Op.getOperand(2);
16248 SDValue Src3 = Op.getOperand(3);
16249 SDValue Mask = Op.getOperand(4);
16250 EVT VT = Op.getValueType();
16251 SDValue PassThru = SDValue();
16253 // set PassThru element
16254 if (IntrData->Type == VPERM_3OP_MASKZ || IntrData->Type == FMA_OP_MASKZ)
16255 PassThru = getZeroVector(VT, Subtarget, DAG, dl);
16256 else if (IntrData->Type == FMA_OP_MASK3)
16261 // We specify 2 possible opcodes for intrinsics with rounding modes.
16262 // First, we check if the intrinsic may have non-default rounding mode,
16263 // (IntrData->Opc1 != 0), then we check the rounding mode operand.
16264 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1;
16265 if (IntrWithRoundingModeOpcode != 0) {
16266 SDValue Rnd = Op.getOperand(5);
16267 if (cast<ConstantSDNode>(Rnd)->getZExtValue() !=
16268 X86::STATIC_ROUNDING::CUR_DIRECTION)
16269 return getVectorMaskingNode(DAG.getNode(IntrWithRoundingModeOpcode,
16270 dl, Op.getValueType(),
16271 Src1, Src2, Src3, Rnd),
16272 Mask, PassThru, Subtarget, DAG);
16274 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0,
16275 dl, Op.getValueType(),
16277 Mask, PassThru, Subtarget, DAG);
16279 case TERLOG_OP_MASK:
16280 case TERLOG_OP_MASKZ: {
16281 SDValue Src1 = Op.getOperand(1);
16282 SDValue Src2 = Op.getOperand(2);
16283 SDValue Src3 = Op.getOperand(3);
16284 SDValue Src4 = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op.getOperand(4));
16285 SDValue Mask = Op.getOperand(5);
16286 EVT VT = Op.getValueType();
16287 SDValue PassThru = Src1;
16288 // Set PassThru element.
16289 if (IntrData->Type == TERLOG_OP_MASKZ)
16290 PassThru = getZeroVector(VT, Subtarget, DAG, dl);
16292 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT,
16293 Src1, Src2, Src3, Src4),
16294 Mask, PassThru, Subtarget, DAG);
16297 // FPclass intrinsics with mask
16298 SDValue Src1 = Op.getOperand(1);
16299 EVT VT = Src1.getValueType();
16300 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16301 VT.getVectorNumElements());
16302 SDValue Imm = Op.getOperand(2);
16303 SDValue Mask = Op.getOperand(3);
16304 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16305 Mask.getValueType().getSizeInBits());
16306 SDValue FPclass = DAG.getNode(IntrData->Opc0, dl, MaskVT, Src1, Imm);
16307 SDValue FPclassMask = getVectorMaskingNode(FPclass, Mask,
16308 DAG.getTargetConstant(0, dl, MaskVT),
16310 SDValue Res = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, BitcastVT,
16311 DAG.getUNDEF(BitcastVT), FPclassMask,
16312 DAG.getIntPtrConstant(0, dl));
16313 return DAG.getBitcast(Op.getValueType(), Res);
16316 SDValue Src1 = Op.getOperand(1);
16317 SDValue Imm = Op.getOperand(2);
16318 SDValue Mask = Op.getOperand(3);
16319 SDValue FPclass = DAG.getNode(IntrData->Opc0, dl, MVT::i1, Src1, Imm);
16320 SDValue FPclassMask = getScalarMaskingNode(FPclass, Mask,
16321 DAG.getTargetConstant(0, dl, MVT::i1), Subtarget, DAG);
16322 return DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i8, FPclassMask);
16325 case CMP_MASK_CC: {
16326 // Comparison intrinsics with masks.
16327 // Example of transformation:
16328 // (i8 (int_x86_avx512_mask_pcmpeq_q_128
16329 // (v2i64 %a), (v2i64 %b), (i8 %mask))) ->
16331 // (v8i1 (insert_subvector undef,
16332 // (v2i1 (and (PCMPEQM %a, %b),
16333 // (extract_subvector
16334 // (v8i1 (bitcast %mask)), 0))), 0))))
16335 EVT VT = Op.getOperand(1).getValueType();
16336 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16337 VT.getVectorNumElements());
16338 SDValue Mask = Op.getOperand((IntrData->Type == CMP_MASK_CC) ? 4 : 3);
16339 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16340 Mask.getValueType().getSizeInBits());
16342 if (IntrData->Type == CMP_MASK_CC) {
16343 SDValue CC = Op.getOperand(3);
16344 CC = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, CC);
16345 // We specify 2 possible opcodes for intrinsics with rounding modes.
16346 // First, we check if the intrinsic may have non-default rounding mode,
16347 // (IntrData->Opc1 != 0), then we check the rounding mode operand.
16348 if (IntrData->Opc1 != 0) {
16349 SDValue Rnd = Op.getOperand(5);
16350 if (cast<ConstantSDNode>(Rnd)->getZExtValue() !=
16351 X86::STATIC_ROUNDING::CUR_DIRECTION)
16352 Cmp = DAG.getNode(IntrData->Opc1, dl, MaskVT, Op.getOperand(1),
16353 Op.getOperand(2), CC, Rnd);
16355 //default rounding mode
16357 Cmp = DAG.getNode(IntrData->Opc0, dl, MaskVT, Op.getOperand(1),
16358 Op.getOperand(2), CC);
16361 assert(IntrData->Type == CMP_MASK && "Unexpected intrinsic type!");
16362 Cmp = DAG.getNode(IntrData->Opc0, dl, MaskVT, Op.getOperand(1),
16365 SDValue CmpMask = getVectorMaskingNode(Cmp, Mask,
16366 DAG.getTargetConstant(0, dl,
16369 SDValue Res = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, BitcastVT,
16370 DAG.getUNDEF(BitcastVT), CmpMask,
16371 DAG.getIntPtrConstant(0, dl));
16372 return DAG.getBitcast(Op.getValueType(), Res);
16374 case CMP_MASK_SCALAR_CC: {
16375 SDValue Src1 = Op.getOperand(1);
16376 SDValue Src2 = Op.getOperand(2);
16377 SDValue CC = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op.getOperand(3));
16378 SDValue Mask = Op.getOperand(4);
16381 if (IntrData->Opc1 != 0) {
16382 SDValue Rnd = Op.getOperand(5);
16383 if (cast<ConstantSDNode>(Rnd)->getZExtValue() !=
16384 X86::STATIC_ROUNDING::CUR_DIRECTION)
16385 Cmp = DAG.getNode(IntrData->Opc1, dl, MVT::i1, Src1, Src2, CC, Rnd);
16387 //default rounding mode
16389 Cmp = DAG.getNode(IntrData->Opc0, dl, MVT::i1, Src1, Src2, CC);
16391 SDValue CmpMask = getScalarMaskingNode(Cmp, Mask,
16392 DAG.getTargetConstant(0, dl,
16396 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::i8,
16397 DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i8, CmpMask),
16398 DAG.getValueType(MVT::i1));
16400 case COMI: { // Comparison intrinsics
16401 ISD::CondCode CC = (ISD::CondCode)IntrData->Opc1;
16402 SDValue LHS = Op.getOperand(1);
16403 SDValue RHS = Op.getOperand(2);
16404 unsigned X86CC = TranslateX86CC(CC, dl, true, LHS, RHS, DAG);
16405 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!");
16406 SDValue Cond = DAG.getNode(IntrData->Opc0, dl, MVT::i32, LHS, RHS);
16407 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
16408 DAG.getConstant(X86CC, dl, MVT::i8), Cond);
16409 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
16412 return getTargetVShiftNode(IntrData->Opc0, dl, Op.getSimpleValueType(),
16413 Op.getOperand(1), Op.getOperand(2), DAG);
16415 return getVectorMaskingNode(getTargetVShiftNode(IntrData->Opc0, dl,
16416 Op.getSimpleValueType(),
16418 Op.getOperand(2), DAG),
16419 Op.getOperand(4), Op.getOperand(3), Subtarget,
16421 case COMPRESS_EXPAND_IN_REG: {
16422 SDValue Mask = Op.getOperand(3);
16423 SDValue DataToCompress = Op.getOperand(1);
16424 SDValue PassThru = Op.getOperand(2);
16425 if (isAllOnes(Mask)) // return data as is
16426 return Op.getOperand(1);
16428 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT,
16430 Mask, PassThru, Subtarget, DAG);
16433 SDValue Mask = Op.getOperand(3);
16434 EVT VT = Op.getValueType();
16435 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16436 VT.getVectorNumElements());
16437 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16438 Mask.getValueType().getSizeInBits());
16440 SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
16441 DAG.getBitcast(BitcastVT, Mask),
16442 DAG.getIntPtrConstant(0, dl));
16443 return DAG.getNode(IntrData->Opc0, dl, VT, VMask, Op.getOperand(1),
16452 default: return SDValue(); // Don't custom lower most intrinsics.
16454 case Intrinsic::x86_avx2_permd:
16455 case Intrinsic::x86_avx2_permps:
16456 // Operands intentionally swapped. Mask is last operand to intrinsic,
16457 // but second operand for node/instruction.
16458 return DAG.getNode(X86ISD::VPERMV, dl, Op.getValueType(),
16459 Op.getOperand(2), Op.getOperand(1));
16461 // ptest and testp intrinsics. The intrinsic these come from are designed to
16462 // return an integer value, not just an instruction so lower it to the ptest
16463 // or testp pattern and a setcc for the result.
16464 case Intrinsic::x86_sse41_ptestz:
16465 case Intrinsic::x86_sse41_ptestc:
16466 case Intrinsic::x86_sse41_ptestnzc:
16467 case Intrinsic::x86_avx_ptestz_256:
16468 case Intrinsic::x86_avx_ptestc_256:
16469 case Intrinsic::x86_avx_ptestnzc_256:
16470 case Intrinsic::x86_avx_vtestz_ps:
16471 case Intrinsic::x86_avx_vtestc_ps:
16472 case Intrinsic::x86_avx_vtestnzc_ps:
16473 case Intrinsic::x86_avx_vtestz_pd:
16474 case Intrinsic::x86_avx_vtestc_pd:
16475 case Intrinsic::x86_avx_vtestnzc_pd:
16476 case Intrinsic::x86_avx_vtestz_ps_256:
16477 case Intrinsic::x86_avx_vtestc_ps_256:
16478 case Intrinsic::x86_avx_vtestnzc_ps_256:
16479 case Intrinsic::x86_avx_vtestz_pd_256:
16480 case Intrinsic::x86_avx_vtestc_pd_256:
16481 case Intrinsic::x86_avx_vtestnzc_pd_256: {
16482 bool IsTestPacked = false;
16485 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
16486 case Intrinsic::x86_avx_vtestz_ps:
16487 case Intrinsic::x86_avx_vtestz_pd:
16488 case Intrinsic::x86_avx_vtestz_ps_256:
16489 case Intrinsic::x86_avx_vtestz_pd_256:
16490 IsTestPacked = true; // Fallthrough
16491 case Intrinsic::x86_sse41_ptestz:
16492 case Intrinsic::x86_avx_ptestz_256:
16494 X86CC = X86::COND_E;
16496 case Intrinsic::x86_avx_vtestc_ps:
16497 case Intrinsic::x86_avx_vtestc_pd:
16498 case Intrinsic::x86_avx_vtestc_ps_256:
16499 case Intrinsic::x86_avx_vtestc_pd_256:
16500 IsTestPacked = true; // Fallthrough
16501 case Intrinsic::x86_sse41_ptestc:
16502 case Intrinsic::x86_avx_ptestc_256:
16504 X86CC = X86::COND_B;
16506 case Intrinsic::x86_avx_vtestnzc_ps:
16507 case Intrinsic::x86_avx_vtestnzc_pd:
16508 case Intrinsic::x86_avx_vtestnzc_ps_256:
16509 case Intrinsic::x86_avx_vtestnzc_pd_256:
16510 IsTestPacked = true; // Fallthrough
16511 case Intrinsic::x86_sse41_ptestnzc:
16512 case Intrinsic::x86_avx_ptestnzc_256:
16514 X86CC = X86::COND_A;
16518 SDValue LHS = Op.getOperand(1);
16519 SDValue RHS = Op.getOperand(2);
16520 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST;
16521 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS);
16522 SDValue CC = DAG.getConstant(X86CC, dl, MVT::i8);
16523 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
16524 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
16526 case Intrinsic::x86_avx512_kortestz_w:
16527 case Intrinsic::x86_avx512_kortestc_w: {
16528 unsigned X86CC = (IntNo == Intrinsic::x86_avx512_kortestz_w)? X86::COND_E: X86::COND_B;
16529 SDValue LHS = DAG.getBitcast(MVT::v16i1, Op.getOperand(1));
16530 SDValue RHS = DAG.getBitcast(MVT::v16i1, Op.getOperand(2));
16531 SDValue CC = DAG.getConstant(X86CC, dl, MVT::i8);
16532 SDValue Test = DAG.getNode(X86ISD::KORTEST, dl, MVT::i32, LHS, RHS);
16533 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i1, CC, Test);
16534 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
16537 case Intrinsic::x86_sse42_pcmpistria128:
16538 case Intrinsic::x86_sse42_pcmpestria128:
16539 case Intrinsic::x86_sse42_pcmpistric128:
16540 case Intrinsic::x86_sse42_pcmpestric128:
16541 case Intrinsic::x86_sse42_pcmpistrio128:
16542 case Intrinsic::x86_sse42_pcmpestrio128:
16543 case Intrinsic::x86_sse42_pcmpistris128:
16544 case Intrinsic::x86_sse42_pcmpestris128:
16545 case Intrinsic::x86_sse42_pcmpistriz128:
16546 case Intrinsic::x86_sse42_pcmpestriz128: {
16550 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
16551 case Intrinsic::x86_sse42_pcmpistria128:
16552 Opcode = X86ISD::PCMPISTRI;
16553 X86CC = X86::COND_A;
16555 case Intrinsic::x86_sse42_pcmpestria128:
16556 Opcode = X86ISD::PCMPESTRI;
16557 X86CC = X86::COND_A;
16559 case Intrinsic::x86_sse42_pcmpistric128:
16560 Opcode = X86ISD::PCMPISTRI;
16561 X86CC = X86::COND_B;
16563 case Intrinsic::x86_sse42_pcmpestric128:
16564 Opcode = X86ISD::PCMPESTRI;
16565 X86CC = X86::COND_B;
16567 case Intrinsic::x86_sse42_pcmpistrio128:
16568 Opcode = X86ISD::PCMPISTRI;
16569 X86CC = X86::COND_O;
16571 case Intrinsic::x86_sse42_pcmpestrio128:
16572 Opcode = X86ISD::PCMPESTRI;
16573 X86CC = X86::COND_O;
16575 case Intrinsic::x86_sse42_pcmpistris128:
16576 Opcode = X86ISD::PCMPISTRI;
16577 X86CC = X86::COND_S;
16579 case Intrinsic::x86_sse42_pcmpestris128:
16580 Opcode = X86ISD::PCMPESTRI;
16581 X86CC = X86::COND_S;
16583 case Intrinsic::x86_sse42_pcmpistriz128:
16584 Opcode = X86ISD::PCMPISTRI;
16585 X86CC = X86::COND_E;
16587 case Intrinsic::x86_sse42_pcmpestriz128:
16588 Opcode = X86ISD::PCMPESTRI;
16589 X86CC = X86::COND_E;
16592 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
16593 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
16594 SDValue PCMP = DAG.getNode(Opcode, dl, VTs, NewOps);
16595 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
16596 DAG.getConstant(X86CC, dl, MVT::i8),
16597 SDValue(PCMP.getNode(), 1));
16598 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
16601 case Intrinsic::x86_sse42_pcmpistri128:
16602 case Intrinsic::x86_sse42_pcmpestri128: {
16604 if (IntNo == Intrinsic::x86_sse42_pcmpistri128)
16605 Opcode = X86ISD::PCMPISTRI;
16607 Opcode = X86ISD::PCMPESTRI;
16609 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
16610 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
16611 return DAG.getNode(Opcode, dl, VTs, NewOps);
16614 case Intrinsic::x86_seh_lsda: {
16615 // Compute the symbol for the LSDA. We know it'll get emitted later.
16616 MachineFunction &MF = DAG.getMachineFunction();
16617 SDValue Op1 = Op.getOperand(1);
16618 auto *Fn = cast<Function>(cast<GlobalAddressSDNode>(Op1)->getGlobal());
16619 MCSymbol *LSDASym = MF.getMMI().getContext().getOrCreateLSDASymbol(
16620 GlobalValue::getRealLinkageName(Fn->getName()));
16622 // Generate a simple absolute symbol reference. This intrinsic is only
16623 // supported on 32-bit Windows, which isn't PIC.
16624 SDValue Result = DAG.getMCSymbol(LSDASym, VT);
16625 return DAG.getNode(X86ISD::Wrapper, dl, VT, Result);
16628 case Intrinsic::x86_seh_recoverfp: {
16629 SDValue FnOp = Op.getOperand(1);
16630 SDValue IncomingFPOp = Op.getOperand(2);
16631 GlobalAddressSDNode *GSD = dyn_cast<GlobalAddressSDNode>(FnOp);
16632 auto *Fn = dyn_cast_or_null<Function>(GSD ? GSD->getGlobal() : nullptr);
16634 report_fatal_error(
16635 "llvm.x86.seh.recoverfp must take a function as the first argument");
16636 return recoverFramePointer(DAG, Fn, IncomingFPOp);
16639 case Intrinsic::localaddress: {
16640 // Returns one of the stack, base, or frame pointer registers, depending on
16641 // which is used to reference local variables.
16642 MachineFunction &MF = DAG.getMachineFunction();
16643 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
16645 if (RegInfo->hasBasePointer(MF))
16646 Reg = RegInfo->getBaseRegister();
16647 else // This function handles the SP or FP case.
16648 Reg = RegInfo->getPtrSizedFrameRegister(MF);
16649 return DAG.getCopyFromReg(DAG.getEntryNode(), dl, Reg, VT);
16654 static SDValue getGatherNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
16655 SDValue Src, SDValue Mask, SDValue Base,
16656 SDValue Index, SDValue ScaleOp, SDValue Chain,
16657 const X86Subtarget * Subtarget) {
16659 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
16661 llvm_unreachable("Invalid scale type");
16662 unsigned ScaleVal = C->getZExtValue();
16663 if (ScaleVal > 2 && ScaleVal != 4 && ScaleVal != 8)
16664 llvm_unreachable("Valid scale values are 1, 2, 4, 8");
16666 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), dl, MVT::i8);
16667 EVT MaskVT = MVT::getVectorVT(MVT::i1,
16668 Index.getSimpleValueType().getVectorNumElements());
16670 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
16672 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), dl, MaskVT);
16674 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16675 Mask.getValueType().getSizeInBits());
16677 // In case when MaskVT equals v2i1 or v4i1, low 2 or 4 elements
16678 // are extracted by EXTRACT_SUBVECTOR.
16679 MaskInReg = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
16680 DAG.getBitcast(BitcastVT, Mask),
16681 DAG.getIntPtrConstant(0, dl));
16683 SDVTList VTs = DAG.getVTList(Op.getValueType(), MaskVT, MVT::Other);
16684 SDValue Disp = DAG.getTargetConstant(0, dl, MVT::i32);
16685 SDValue Segment = DAG.getRegister(0, MVT::i32);
16686 if (Src.getOpcode() == ISD::UNDEF)
16687 Src = getZeroVector(Op.getValueType(), Subtarget, DAG, dl);
16688 SDValue Ops[] = {Src, MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
16689 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
16690 SDValue RetOps[] = { SDValue(Res, 0), SDValue(Res, 2) };
16691 return DAG.getMergeValues(RetOps, dl);
16694 static SDValue getScatterNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
16695 SDValue Src, SDValue Mask, SDValue Base,
16696 SDValue Index, SDValue ScaleOp, SDValue Chain) {
16698 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
16700 llvm_unreachable("Invalid scale type");
16701 unsigned ScaleVal = C->getZExtValue();
16702 if (ScaleVal > 2 && ScaleVal != 4 && ScaleVal != 8)
16703 llvm_unreachable("Valid scale values are 1, 2, 4, 8");
16705 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), dl, MVT::i8);
16706 SDValue Disp = DAG.getTargetConstant(0, dl, MVT::i32);
16707 SDValue Segment = DAG.getRegister(0, MVT::i32);
16708 EVT MaskVT = MVT::getVectorVT(MVT::i1,
16709 Index.getSimpleValueType().getVectorNumElements());
16711 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
16713 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), dl, MaskVT);
16715 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16716 Mask.getValueType().getSizeInBits());
16718 // In case when MaskVT equals v2i1 or v4i1, low 2 or 4 elements
16719 // are extracted by EXTRACT_SUBVECTOR.
16720 MaskInReg = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
16721 DAG.getBitcast(BitcastVT, Mask),
16722 DAG.getIntPtrConstant(0, dl));
16724 SDVTList VTs = DAG.getVTList(MaskVT, MVT::Other);
16725 SDValue Ops[] = {Base, Scale, Index, Disp, Segment, MaskInReg, Src, Chain};
16726 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
16727 return SDValue(Res, 1);
16730 static SDValue getPrefetchNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
16731 SDValue Mask, SDValue Base, SDValue Index,
16732 SDValue ScaleOp, SDValue Chain) {
16734 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
16735 assert(C && "Invalid scale type");
16736 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), dl, MVT::i8);
16737 SDValue Disp = DAG.getTargetConstant(0, dl, MVT::i32);
16738 SDValue Segment = DAG.getRegister(0, MVT::i32);
16740 MVT::getVectorVT(MVT::i1, Index.getSimpleValueType().getVectorNumElements());
16742 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
16744 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), dl, MaskVT);
16746 MaskInReg = DAG.getBitcast(MaskVT, Mask);
16747 //SDVTList VTs = DAG.getVTList(MVT::Other);
16748 SDValue Ops[] = {MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
16749 SDNode *Res = DAG.getMachineNode(Opc, dl, MVT::Other, Ops);
16750 return SDValue(Res, 0);
16753 // getReadPerformanceCounter - Handles the lowering of builtin intrinsics that
16754 // read performance monitor counters (x86_rdpmc).
16755 static void getReadPerformanceCounter(SDNode *N, SDLoc DL,
16756 SelectionDAG &DAG, const X86Subtarget *Subtarget,
16757 SmallVectorImpl<SDValue> &Results) {
16758 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
16759 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
16762 // The ECX register is used to select the index of the performance counter
16764 SDValue Chain = DAG.getCopyToReg(N->getOperand(0), DL, X86::ECX,
16766 SDValue rd = DAG.getNode(X86ISD::RDPMC_DAG, DL, Tys, Chain);
16768 // Reads the content of a 64-bit performance counter and returns it in the
16769 // registers EDX:EAX.
16770 if (Subtarget->is64Bit()) {
16771 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
16772 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
16775 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
16776 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
16779 Chain = HI.getValue(1);
16781 if (Subtarget->is64Bit()) {
16782 // The EAX register is loaded with the low-order 32 bits. The EDX register
16783 // is loaded with the supported high-order bits of the counter.
16784 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
16785 DAG.getConstant(32, DL, MVT::i8));
16786 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
16787 Results.push_back(Chain);
16791 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
16792 SDValue Ops[] = { LO, HI };
16793 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
16794 Results.push_back(Pair);
16795 Results.push_back(Chain);
16798 // getReadTimeStampCounter - Handles the lowering of builtin intrinsics that
16799 // read the time stamp counter (x86_rdtsc and x86_rdtscp). This function is
16800 // also used to custom lower READCYCLECOUNTER nodes.
16801 static void getReadTimeStampCounter(SDNode *N, SDLoc DL, unsigned Opcode,
16802 SelectionDAG &DAG, const X86Subtarget *Subtarget,
16803 SmallVectorImpl<SDValue> &Results) {
16804 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
16805 SDValue rd = DAG.getNode(Opcode, DL, Tys, N->getOperand(0));
16808 // The processor's time-stamp counter (a 64-bit MSR) is stored into the
16809 // EDX:EAX registers. EDX is loaded with the high-order 32 bits of the MSR
16810 // and the EAX register is loaded with the low-order 32 bits.
16811 if (Subtarget->is64Bit()) {
16812 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
16813 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
16816 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
16817 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
16820 SDValue Chain = HI.getValue(1);
16822 if (Opcode == X86ISD::RDTSCP_DAG) {
16823 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
16825 // Instruction RDTSCP loads the IA32:TSC_AUX_MSR (address C000_0103H) into
16826 // the ECX register. Add 'ecx' explicitly to the chain.
16827 SDValue ecx = DAG.getCopyFromReg(Chain, DL, X86::ECX, MVT::i32,
16829 // Explicitly store the content of ECX at the location passed in input
16830 // to the 'rdtscp' intrinsic.
16831 Chain = DAG.getStore(ecx.getValue(1), DL, ecx, N->getOperand(2),
16832 MachinePointerInfo(), false, false, 0);
16835 if (Subtarget->is64Bit()) {
16836 // The EDX register is loaded with the high-order 32 bits of the MSR, and
16837 // the EAX register is loaded with the low-order 32 bits.
16838 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
16839 DAG.getConstant(32, DL, MVT::i8));
16840 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
16841 Results.push_back(Chain);
16845 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
16846 SDValue Ops[] = { LO, HI };
16847 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
16848 Results.push_back(Pair);
16849 Results.push_back(Chain);
16852 static SDValue LowerREADCYCLECOUNTER(SDValue Op, const X86Subtarget *Subtarget,
16853 SelectionDAG &DAG) {
16854 SmallVector<SDValue, 2> Results;
16856 getReadTimeStampCounter(Op.getNode(), DL, X86ISD::RDTSC_DAG, DAG, Subtarget,
16858 return DAG.getMergeValues(Results, DL);
16861 static SDValue LowerSEHRESTOREFRAME(SDValue Op, const X86Subtarget *Subtarget,
16862 SelectionDAG &DAG) {
16863 MachineFunction &MF = DAG.getMachineFunction();
16864 const Function *Fn = MF.getFunction();
16866 SDValue Chain = Op.getOperand(0);
16868 assert(Subtarget->getFrameLowering()->hasFP(MF) &&
16869 "using llvm.x86.seh.restoreframe requires a frame pointer");
16871 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
16872 MVT VT = TLI.getPointerTy(DAG.getDataLayout());
16874 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
16875 unsigned FrameReg =
16876 RegInfo->getPtrSizedFrameRegister(DAG.getMachineFunction());
16877 unsigned SPReg = RegInfo->getStackRegister();
16878 unsigned SlotSize = RegInfo->getSlotSize();
16880 // Get incoming EBP.
16881 SDValue IncomingEBP =
16882 DAG.getCopyFromReg(Chain, dl, FrameReg, VT);
16884 // SP is saved in the first field of every registration node, so load
16885 // [EBP-RegNodeSize] into SP.
16886 int RegNodeSize = getSEHRegistrationNodeSize(Fn);
16887 SDValue SPAddr = DAG.getNode(ISD::ADD, dl, VT, IncomingEBP,
16888 DAG.getConstant(-RegNodeSize, dl, VT));
16890 DAG.getLoad(VT, dl, Chain, SPAddr, MachinePointerInfo(), false, false,
16891 false, VT.getScalarSizeInBits() / 8);
16892 Chain = DAG.getCopyToReg(Chain, dl, SPReg, NewSP);
16894 if (!RegInfo->needsStackRealignment(MF)) {
16895 // Adjust EBP to point back to the original frame position.
16896 SDValue NewFP = recoverFramePointer(DAG, Fn, IncomingEBP);
16897 Chain = DAG.getCopyToReg(Chain, dl, FrameReg, NewFP);
16899 assert(RegInfo->hasBasePointer(MF) &&
16900 "functions with Win32 EH must use frame or base pointer register");
16902 // Reload the base pointer (ESI) with the adjusted incoming EBP.
16903 SDValue NewBP = recoverFramePointer(DAG, Fn, IncomingEBP);
16904 Chain = DAG.getCopyToReg(Chain, dl, RegInfo->getBaseRegister(), NewBP);
16906 // Reload the spilled EBP value, now that the stack and base pointers are
16908 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
16909 X86FI->setHasSEHFramePtrSave(true);
16910 int FI = MF.getFrameInfo()->CreateSpillStackObject(SlotSize, SlotSize);
16911 X86FI->setSEHFramePtrSaveIndex(FI);
16912 SDValue NewFP = DAG.getLoad(VT, dl, Chain, DAG.getFrameIndex(FI, VT),
16913 MachinePointerInfo(), false, false, false,
16914 VT.getScalarSizeInBits() / 8);
16915 Chain = DAG.getCopyToReg(NewFP, dl, FrameReg, NewFP);
16921 /// \brief Lower intrinsics for TRUNCATE_TO_MEM case
16922 /// return truncate Store/MaskedStore Node
16923 static SDValue LowerINTRINSIC_TRUNCATE_TO_MEM(const SDValue & Op,
16927 SDValue Mask = Op.getOperand(4);
16928 SDValue DataToTruncate = Op.getOperand(3);
16929 SDValue Addr = Op.getOperand(2);
16930 SDValue Chain = Op.getOperand(0);
16932 EVT VT = DataToTruncate.getValueType();
16933 EVT SVT = EVT::getVectorVT(*DAG.getContext(),
16934 ElementType, VT.getVectorNumElements());
16936 if (isAllOnes(Mask)) // return just a truncate store
16937 return DAG.getTruncStore(Chain, dl, DataToTruncate, Addr,
16938 MachinePointerInfo(), SVT, false, false,
16939 SVT.getScalarSizeInBits()/8);
16941 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(),
16942 MVT::i1, VT.getVectorNumElements());
16943 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16944 Mask.getValueType().getSizeInBits());
16945 // In case when MaskVT equals v2i1 or v4i1, low 2 or 4 elements
16946 // are extracted by EXTRACT_SUBVECTOR.
16947 SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
16948 DAG.getBitcast(BitcastVT, Mask),
16949 DAG.getIntPtrConstant(0, dl));
16951 MachineMemOperand *MMO = DAG.getMachineFunction().
16952 getMachineMemOperand(MachinePointerInfo(),
16953 MachineMemOperand::MOStore, SVT.getStoreSize(),
16954 SVT.getScalarSizeInBits()/8);
16956 return DAG.getMaskedStore(Chain, dl, DataToTruncate, Addr,
16957 VMask, SVT, MMO, true);
16960 static SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
16961 SelectionDAG &DAG) {
16962 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
16964 const IntrinsicData* IntrData = getIntrinsicWithChain(IntNo);
16966 if (IntNo == llvm::Intrinsic::x86_seh_restoreframe)
16967 return LowerSEHRESTOREFRAME(Op, Subtarget, DAG);
16972 switch(IntrData->Type) {
16974 llvm_unreachable("Unknown Intrinsic Type");
16978 // Emit the node with the right value type.
16979 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Glue, MVT::Other);
16980 SDValue Result = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(0));
16982 // If the value returned by RDRAND/RDSEED was valid (CF=1), return 1.
16983 // Otherwise return the value from Rand, which is always 0, casted to i32.
16984 SDValue Ops[] = { DAG.getZExtOrTrunc(Result, dl, Op->getValueType(1)),
16985 DAG.getConstant(1, dl, Op->getValueType(1)),
16986 DAG.getConstant(X86::COND_B, dl, MVT::i32),
16987 SDValue(Result.getNode(), 1) };
16988 SDValue isValid = DAG.getNode(X86ISD::CMOV, dl,
16989 DAG.getVTList(Op->getValueType(1), MVT::Glue),
16992 // Return { result, isValid, chain }.
16993 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(), Result, isValid,
16994 SDValue(Result.getNode(), 2));
16997 //gather(v1, mask, index, base, scale);
16998 SDValue Chain = Op.getOperand(0);
16999 SDValue Src = Op.getOperand(2);
17000 SDValue Base = Op.getOperand(3);
17001 SDValue Index = Op.getOperand(4);
17002 SDValue Mask = Op.getOperand(5);
17003 SDValue Scale = Op.getOperand(6);
17004 return getGatherNode(IntrData->Opc0, Op, DAG, Src, Mask, Base, Index, Scale,
17008 //scatter(base, mask, index, v1, scale);
17009 SDValue Chain = Op.getOperand(0);
17010 SDValue Base = Op.getOperand(2);
17011 SDValue Mask = Op.getOperand(3);
17012 SDValue Index = Op.getOperand(4);
17013 SDValue Src = Op.getOperand(5);
17014 SDValue Scale = Op.getOperand(6);
17015 return getScatterNode(IntrData->Opc0, Op, DAG, Src, Mask, Base, Index,
17019 SDValue Hint = Op.getOperand(6);
17020 unsigned HintVal = cast<ConstantSDNode>(Hint)->getZExtValue();
17021 assert(HintVal < 2 && "Wrong prefetch hint in intrinsic: should be 0 or 1");
17022 unsigned Opcode = (HintVal ? IntrData->Opc1 : IntrData->Opc0);
17023 SDValue Chain = Op.getOperand(0);
17024 SDValue Mask = Op.getOperand(2);
17025 SDValue Index = Op.getOperand(3);
17026 SDValue Base = Op.getOperand(4);
17027 SDValue Scale = Op.getOperand(5);
17028 return getPrefetchNode(Opcode, Op, DAG, Mask, Base, Index, Scale, Chain);
17030 // Read Time Stamp Counter (RDTSC) and Processor ID (RDTSCP).
17032 SmallVector<SDValue, 2> Results;
17033 getReadTimeStampCounter(Op.getNode(), dl, IntrData->Opc0, DAG, Subtarget,
17035 return DAG.getMergeValues(Results, dl);
17037 // Read Performance Monitoring Counters.
17039 SmallVector<SDValue, 2> Results;
17040 getReadPerformanceCounter(Op.getNode(), dl, DAG, Subtarget, Results);
17041 return DAG.getMergeValues(Results, dl);
17043 // XTEST intrinsics.
17045 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
17046 SDValue InTrans = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(0));
17047 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
17048 DAG.getConstant(X86::COND_NE, dl, MVT::i8),
17050 SDValue Ret = DAG.getNode(ISD::ZERO_EXTEND, dl, Op->getValueType(0), SetCC);
17051 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(),
17052 Ret, SDValue(InTrans.getNode(), 1));
17056 SmallVector<SDValue, 2> Results;
17057 SDVTList CFVTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
17058 SDVTList VTs = DAG.getVTList(Op.getOperand(3)->getValueType(0), MVT::Other);
17059 SDValue GenCF = DAG.getNode(X86ISD::ADD, dl, CFVTs, Op.getOperand(2),
17060 DAG.getConstant(-1, dl, MVT::i8));
17061 SDValue Res = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(3),
17062 Op.getOperand(4), GenCF.getValue(1));
17063 SDValue Store = DAG.getStore(Op.getOperand(0), dl, Res.getValue(0),
17064 Op.getOperand(5), MachinePointerInfo(),
17066 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
17067 DAG.getConstant(X86::COND_B, dl, MVT::i8),
17069 Results.push_back(SetCC);
17070 Results.push_back(Store);
17071 return DAG.getMergeValues(Results, dl);
17073 case COMPRESS_TO_MEM: {
17075 SDValue Mask = Op.getOperand(4);
17076 SDValue DataToCompress = Op.getOperand(3);
17077 SDValue Addr = Op.getOperand(2);
17078 SDValue Chain = Op.getOperand(0);
17080 EVT VT = DataToCompress.getValueType();
17081 if (isAllOnes(Mask)) // return just a store
17082 return DAG.getStore(Chain, dl, DataToCompress, Addr,
17083 MachinePointerInfo(), false, false,
17084 VT.getScalarSizeInBits()/8);
17086 SDValue Compressed =
17087 getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, DataToCompress),
17088 Mask, DAG.getUNDEF(VT), Subtarget, DAG);
17089 return DAG.getStore(Chain, dl, Compressed, Addr,
17090 MachinePointerInfo(), false, false,
17091 VT.getScalarSizeInBits()/8);
17093 case TRUNCATE_TO_MEM_VI8:
17094 return LowerINTRINSIC_TRUNCATE_TO_MEM(Op, DAG, MVT::i8);
17095 case TRUNCATE_TO_MEM_VI16:
17096 return LowerINTRINSIC_TRUNCATE_TO_MEM(Op, DAG, MVT::i16);
17097 case TRUNCATE_TO_MEM_VI32:
17098 return LowerINTRINSIC_TRUNCATE_TO_MEM(Op, DAG, MVT::i32);
17099 case EXPAND_FROM_MEM: {
17101 SDValue Mask = Op.getOperand(4);
17102 SDValue PassThru = Op.getOperand(3);
17103 SDValue Addr = Op.getOperand(2);
17104 SDValue Chain = Op.getOperand(0);
17105 EVT VT = Op.getValueType();
17107 if (isAllOnes(Mask)) // return just a load
17108 return DAG.getLoad(VT, dl, Chain, Addr, MachinePointerInfo(), false, false,
17109 false, VT.getScalarSizeInBits()/8);
17111 SDValue DataToExpand = DAG.getLoad(VT, dl, Chain, Addr, MachinePointerInfo(),
17112 false, false, false,
17113 VT.getScalarSizeInBits()/8);
17115 SDValue Results[] = {
17116 getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, DataToExpand),
17117 Mask, PassThru, Subtarget, DAG), Chain};
17118 return DAG.getMergeValues(Results, dl);
17123 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op,
17124 SelectionDAG &DAG) const {
17125 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
17126 MFI->setReturnAddressIsTaken(true);
17128 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
17131 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
17133 EVT PtrVT = getPointerTy(DAG.getDataLayout());
17136 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
17137 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
17138 SDValue Offset = DAG.getConstant(RegInfo->getSlotSize(), dl, PtrVT);
17139 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
17140 DAG.getNode(ISD::ADD, dl, PtrVT,
17141 FrameAddr, Offset),
17142 MachinePointerInfo(), false, false, false, 0);
17145 // Just load the return address.
17146 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
17147 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
17148 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
17151 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
17152 MachineFunction &MF = DAG.getMachineFunction();
17153 MachineFrameInfo *MFI = MF.getFrameInfo();
17154 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
17155 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
17156 EVT VT = Op.getValueType();
17158 MFI->setFrameAddressIsTaken(true);
17160 if (MF.getTarget().getMCAsmInfo()->usesWindowsCFI()) {
17161 // Depth > 0 makes no sense on targets which use Windows unwind codes. It
17162 // is not possible to crawl up the stack without looking at the unwind codes
17164 int FrameAddrIndex = FuncInfo->getFAIndex();
17165 if (!FrameAddrIndex) {
17166 // Set up a frame object for the return address.
17167 unsigned SlotSize = RegInfo->getSlotSize();
17168 FrameAddrIndex = MF.getFrameInfo()->CreateFixedObject(
17169 SlotSize, /*Offset=*/0, /*IsImmutable=*/false);
17170 FuncInfo->setFAIndex(FrameAddrIndex);
17172 return DAG.getFrameIndex(FrameAddrIndex, VT);
17175 unsigned FrameReg =
17176 RegInfo->getPtrSizedFrameRegister(DAG.getMachineFunction());
17177 SDLoc dl(Op); // FIXME probably not meaningful
17178 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
17179 assert(((FrameReg == X86::RBP && VT == MVT::i64) ||
17180 (FrameReg == X86::EBP && VT == MVT::i32)) &&
17181 "Invalid Frame Register!");
17182 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
17184 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
17185 MachinePointerInfo(),
17186 false, false, false, 0);
17190 // FIXME? Maybe this could be a TableGen attribute on some registers and
17191 // this table could be generated automatically from RegInfo.
17192 unsigned X86TargetLowering::getRegisterByName(const char* RegName, EVT VT,
17193 SelectionDAG &DAG) const {
17194 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
17195 const MachineFunction &MF = DAG.getMachineFunction();
17197 unsigned Reg = StringSwitch<unsigned>(RegName)
17198 .Case("esp", X86::ESP)
17199 .Case("rsp", X86::RSP)
17200 .Case("ebp", X86::EBP)
17201 .Case("rbp", X86::RBP)
17204 if (Reg == X86::EBP || Reg == X86::RBP) {
17205 if (!TFI.hasFP(MF))
17206 report_fatal_error("register " + StringRef(RegName) +
17207 " is allocatable: function has no frame pointer");
17210 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
17211 unsigned FrameReg =
17212 RegInfo->getPtrSizedFrameRegister(DAG.getMachineFunction());
17213 assert((FrameReg == X86::EBP || FrameReg == X86::RBP) &&
17214 "Invalid Frame Register!");
17222 report_fatal_error("Invalid register name global variable");
17225 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
17226 SelectionDAG &DAG) const {
17227 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
17228 return DAG.getIntPtrConstant(2 * RegInfo->getSlotSize(), SDLoc(Op));
17231 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
17232 SDValue Chain = Op.getOperand(0);
17233 SDValue Offset = Op.getOperand(1);
17234 SDValue Handler = Op.getOperand(2);
17237 EVT PtrVT = getPointerTy(DAG.getDataLayout());
17238 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
17239 unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction());
17240 assert(((FrameReg == X86::RBP && PtrVT == MVT::i64) ||
17241 (FrameReg == X86::EBP && PtrVT == MVT::i32)) &&
17242 "Invalid Frame Register!");
17243 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, PtrVT);
17244 unsigned StoreAddrReg = (PtrVT == MVT::i64) ? X86::RCX : X86::ECX;
17246 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, Frame,
17247 DAG.getIntPtrConstant(RegInfo->getSlotSize(),
17249 StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, StoreAddr, Offset);
17250 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(),
17252 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
17254 return DAG.getNode(X86ISD::EH_RETURN, dl, MVT::Other, Chain,
17255 DAG.getRegister(StoreAddrReg, PtrVT));
17258 SDValue X86TargetLowering::lowerEH_SJLJ_SETJMP(SDValue Op,
17259 SelectionDAG &DAG) const {
17261 return DAG.getNode(X86ISD::EH_SJLJ_SETJMP, DL,
17262 DAG.getVTList(MVT::i32, MVT::Other),
17263 Op.getOperand(0), Op.getOperand(1));
17266 SDValue X86TargetLowering::lowerEH_SJLJ_LONGJMP(SDValue Op,
17267 SelectionDAG &DAG) const {
17269 return DAG.getNode(X86ISD::EH_SJLJ_LONGJMP, DL, MVT::Other,
17270 Op.getOperand(0), Op.getOperand(1));
17273 static SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) {
17274 return Op.getOperand(0);
17277 SDValue X86TargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
17278 SelectionDAG &DAG) const {
17279 SDValue Root = Op.getOperand(0);
17280 SDValue Trmp = Op.getOperand(1); // trampoline
17281 SDValue FPtr = Op.getOperand(2); // nested function
17282 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
17285 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
17286 const TargetRegisterInfo *TRI = Subtarget->getRegisterInfo();
17288 if (Subtarget->is64Bit()) {
17289 SDValue OutChains[6];
17291 // Large code-model.
17292 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode.
17293 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode.
17295 const unsigned char N86R10 = TRI->getEncodingValue(X86::R10) & 0x7;
17296 const unsigned char N86R11 = TRI->getEncodingValue(X86::R11) & 0x7;
17298 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
17300 // Load the pointer to the nested function into R11.
17301 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
17302 SDValue Addr = Trmp;
17303 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, dl, MVT::i16),
17304 Addr, MachinePointerInfo(TrmpAddr),
17307 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17308 DAG.getConstant(2, dl, MVT::i64));
17309 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr,
17310 MachinePointerInfo(TrmpAddr, 2),
17313 // Load the 'nest' parameter value into R10.
17314 // R10 is specified in X86CallingConv.td
17315 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
17316 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17317 DAG.getConstant(10, dl, MVT::i64));
17318 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, dl, MVT::i16),
17319 Addr, MachinePointerInfo(TrmpAddr, 10),
17322 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17323 DAG.getConstant(12, dl, MVT::i64));
17324 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr,
17325 MachinePointerInfo(TrmpAddr, 12),
17328 // Jump to the nested function.
17329 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
17330 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17331 DAG.getConstant(20, dl, MVT::i64));
17332 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, dl, MVT::i16),
17333 Addr, MachinePointerInfo(TrmpAddr, 20),
17336 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
17337 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17338 DAG.getConstant(22, dl, MVT::i64));
17339 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, dl, MVT::i8),
17340 Addr, MachinePointerInfo(TrmpAddr, 22),
17343 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
17345 const Function *Func =
17346 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
17347 CallingConv::ID CC = Func->getCallingConv();
17352 llvm_unreachable("Unsupported calling convention");
17353 case CallingConv::C:
17354 case CallingConv::X86_StdCall: {
17355 // Pass 'nest' parameter in ECX.
17356 // Must be kept in sync with X86CallingConv.td
17357 NestReg = X86::ECX;
17359 // Check that ECX wasn't needed by an 'inreg' parameter.
17360 FunctionType *FTy = Func->getFunctionType();
17361 const AttributeSet &Attrs = Func->getAttributes();
17363 if (!Attrs.isEmpty() && !Func->isVarArg()) {
17364 unsigned InRegCount = 0;
17367 for (FunctionType::param_iterator I = FTy->param_begin(),
17368 E = FTy->param_end(); I != E; ++I, ++Idx)
17369 if (Attrs.hasAttribute(Idx, Attribute::InReg)) {
17370 auto &DL = DAG.getDataLayout();
17371 // FIXME: should only count parameters that are lowered to integers.
17372 InRegCount += (DL.getTypeSizeInBits(*I) + 31) / 32;
17375 if (InRegCount > 2) {
17376 report_fatal_error("Nest register in use - reduce number of inreg"
17382 case CallingConv::X86_FastCall:
17383 case CallingConv::X86_ThisCall:
17384 case CallingConv::Fast:
17385 // Pass 'nest' parameter in EAX.
17386 // Must be kept in sync with X86CallingConv.td
17387 NestReg = X86::EAX;
17391 SDValue OutChains[4];
17392 SDValue Addr, Disp;
17394 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17395 DAG.getConstant(10, dl, MVT::i32));
17396 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
17398 // This is storing the opcode for MOV32ri.
17399 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte.
17400 const unsigned char N86Reg = TRI->getEncodingValue(NestReg) & 0x7;
17401 OutChains[0] = DAG.getStore(Root, dl,
17402 DAG.getConstant(MOV32ri|N86Reg, dl, MVT::i8),
17403 Trmp, MachinePointerInfo(TrmpAddr),
17406 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17407 DAG.getConstant(1, dl, MVT::i32));
17408 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr,
17409 MachinePointerInfo(TrmpAddr, 1),
17412 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode.
17413 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17414 DAG.getConstant(5, dl, MVT::i32));
17415 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, dl, MVT::i8),
17416 Addr, MachinePointerInfo(TrmpAddr, 5),
17419 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17420 DAG.getConstant(6, dl, MVT::i32));
17421 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr,
17422 MachinePointerInfo(TrmpAddr, 6),
17425 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
17429 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op,
17430 SelectionDAG &DAG) const {
17432 The rounding mode is in bits 11:10 of FPSR, and has the following
17434 00 Round to nearest
17439 FLT_ROUNDS, on the other hand, expects the following:
17446 To perform the conversion, we do:
17447 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
17450 MachineFunction &MF = DAG.getMachineFunction();
17451 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
17452 unsigned StackAlignment = TFI.getStackAlignment();
17453 MVT VT = Op.getSimpleValueType();
17456 // Save FP Control Word to stack slot
17457 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false);
17458 SDValue StackSlot =
17459 DAG.getFrameIndex(SSFI, getPointerTy(DAG.getDataLayout()));
17461 MachineMemOperand *MMO =
17462 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(MF, SSFI),
17463 MachineMemOperand::MOStore, 2, 2);
17465 SDValue Ops[] = { DAG.getEntryNode(), StackSlot };
17466 SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL,
17467 DAG.getVTList(MVT::Other),
17468 Ops, MVT::i16, MMO);
17470 // Load FP Control Word from stack slot
17471 SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot,
17472 MachinePointerInfo(), false, false, false, 0);
17474 // Transform as necessary
17476 DAG.getNode(ISD::SRL, DL, MVT::i16,
17477 DAG.getNode(ISD::AND, DL, MVT::i16,
17478 CWD, DAG.getConstant(0x800, DL, MVT::i16)),
17479 DAG.getConstant(11, DL, MVT::i8));
17481 DAG.getNode(ISD::SRL, DL, MVT::i16,
17482 DAG.getNode(ISD::AND, DL, MVT::i16,
17483 CWD, DAG.getConstant(0x400, DL, MVT::i16)),
17484 DAG.getConstant(9, DL, MVT::i8));
17487 DAG.getNode(ISD::AND, DL, MVT::i16,
17488 DAG.getNode(ISD::ADD, DL, MVT::i16,
17489 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2),
17490 DAG.getConstant(1, DL, MVT::i16)),
17491 DAG.getConstant(3, DL, MVT::i16));
17493 return DAG.getNode((VT.getSizeInBits() < 16 ?
17494 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal);
17497 /// \brief Lower a vector CTLZ using native supported vector CTLZ instruction.
17499 // 1. i32/i64 128/256-bit vector (native support require VLX) are expended
17500 // to 512-bit vector.
17501 // 2. i8/i16 vector implemented using dword LZCNT vector instruction
17502 // ( sub(trunc(lzcnt(zext32(x)))) ). In case zext32(x) is illegal,
17503 // split the vector, perform operation on it's Lo a Hi part and
17504 // concatenate the results.
17505 static SDValue LowerVectorCTLZ_AVX512(SDValue Op, SelectionDAG &DAG) {
17507 MVT VT = Op.getSimpleValueType();
17508 MVT EltVT = VT.getVectorElementType();
17509 unsigned NumElems = VT.getVectorNumElements();
17511 if (EltVT == MVT::i64 || EltVT == MVT::i32) {
17512 // Extend to 512 bit vector.
17513 assert((VT.is256BitVector() || VT.is128BitVector()) &&
17514 "Unsupported value type for operation");
17516 MVT NewVT = MVT::getVectorVT(EltVT, 512 / VT.getScalarSizeInBits());
17517 SDValue Vec512 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, NewVT,
17518 DAG.getUNDEF(NewVT),
17520 DAG.getIntPtrConstant(0, dl));
17521 SDValue CtlzNode = DAG.getNode(ISD::CTLZ, dl, NewVT, Vec512);
17523 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, CtlzNode,
17524 DAG.getIntPtrConstant(0, dl));
17527 assert((EltVT == MVT::i8 || EltVT == MVT::i16) &&
17528 "Unsupported element type");
17530 if (16 < NumElems) {
17531 // Split vector, it's Lo and Hi parts will be handled in next iteration.
17533 std::tie(Lo, Hi) = DAG.SplitVector(Op.getOperand(0), dl);
17534 MVT OutVT = MVT::getVectorVT(EltVT, NumElems/2);
17536 Lo = DAG.getNode(Op.getOpcode(), dl, OutVT, Lo);
17537 Hi = DAG.getNode(Op.getOpcode(), dl, OutVT, Hi);
17539 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, Lo, Hi);
17542 MVT NewVT = MVT::getVectorVT(MVT::i32, NumElems);
17544 assert((NewVT.is256BitVector() || NewVT.is512BitVector()) &&
17545 "Unsupported value type for operation");
17547 // Use native supported vector instruction vplzcntd.
17548 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, NewVT, Op.getOperand(0));
17549 SDValue CtlzNode = DAG.getNode(ISD::CTLZ, dl, NewVT, Op);
17550 SDValue TruncNode = DAG.getNode(ISD::TRUNCATE, dl, VT, CtlzNode);
17551 SDValue Delta = DAG.getConstant(32 - EltVT.getSizeInBits(), dl, VT);
17553 return DAG.getNode(ISD::SUB, dl, VT, TruncNode, Delta);
17556 static SDValue LowerCTLZ(SDValue Op, const X86Subtarget *Subtarget,
17557 SelectionDAG &DAG) {
17558 MVT VT = Op.getSimpleValueType();
17560 unsigned NumBits = VT.getSizeInBits();
17563 if (VT.isVector() && Subtarget->hasAVX512())
17564 return LowerVectorCTLZ_AVX512(Op, DAG);
17566 Op = Op.getOperand(0);
17567 if (VT == MVT::i8) {
17568 // Zero extend to i32 since there is not an i8 bsr.
17570 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
17573 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
17574 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
17575 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
17577 // If src is zero (i.e. bsr sets ZF), returns NumBits.
17580 DAG.getConstant(NumBits + NumBits - 1, dl, OpVT),
17581 DAG.getConstant(X86::COND_E, dl, MVT::i8),
17584 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops);
17586 // Finally xor with NumBits-1.
17587 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op,
17588 DAG.getConstant(NumBits - 1, dl, OpVT));
17591 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
17595 static SDValue LowerCTLZ_ZERO_UNDEF(SDValue Op, const X86Subtarget *Subtarget,
17596 SelectionDAG &DAG) {
17597 MVT VT = Op.getSimpleValueType();
17599 unsigned NumBits = VT.getSizeInBits();
17602 if (VT.isVector() && Subtarget->hasAVX512())
17603 return LowerVectorCTLZ_AVX512(Op, DAG);
17605 Op = Op.getOperand(0);
17606 if (VT == MVT::i8) {
17607 // Zero extend to i32 since there is not an i8 bsr.
17609 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
17612 // Issue a bsr (scan bits in reverse).
17613 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
17614 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
17616 // And xor with NumBits-1.
17617 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op,
17618 DAG.getConstant(NumBits - 1, dl, OpVT));
17621 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
17625 static SDValue LowerCTTZ(SDValue Op, SelectionDAG &DAG) {
17626 MVT VT = Op.getSimpleValueType();
17627 unsigned NumBits = VT.getScalarSizeInBits();
17630 if (VT.isVector()) {
17631 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
17633 SDValue N0 = Op.getOperand(0);
17634 SDValue Zero = DAG.getConstant(0, dl, VT);
17636 // lsb(x) = (x & -x)
17637 SDValue LSB = DAG.getNode(ISD::AND, dl, VT, N0,
17638 DAG.getNode(ISD::SUB, dl, VT, Zero, N0));
17640 // cttz_undef(x) = (width - 1) - ctlz(lsb)
17641 if (Op.getOpcode() == ISD::CTTZ_ZERO_UNDEF &&
17642 TLI.isOperationLegal(ISD::CTLZ, VT)) {
17643 SDValue WidthMinusOne = DAG.getConstant(NumBits - 1, dl, VT);
17644 return DAG.getNode(ISD::SUB, dl, VT, WidthMinusOne,
17645 DAG.getNode(ISD::CTLZ, dl, VT, LSB));
17648 // cttz(x) = ctpop(lsb - 1)
17649 SDValue One = DAG.getConstant(1, dl, VT);
17650 return DAG.getNode(ISD::CTPOP, dl, VT,
17651 DAG.getNode(ISD::SUB, dl, VT, LSB, One));
17654 assert(Op.getOpcode() == ISD::CTTZ &&
17655 "Only scalar CTTZ requires custom lowering");
17657 // Issue a bsf (scan bits forward) which also sets EFLAGS.
17658 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
17659 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op.getOperand(0));
17661 // If src is zero (i.e. bsf sets ZF), returns NumBits.
17664 DAG.getConstant(NumBits, dl, VT),
17665 DAG.getConstant(X86::COND_E, dl, MVT::i8),
17668 return DAG.getNode(X86ISD::CMOV, dl, VT, Ops);
17671 // Lower256IntArith - Break a 256-bit integer operation into two new 128-bit
17672 // ones, and then concatenate the result back.
17673 static SDValue Lower256IntArith(SDValue Op, SelectionDAG &DAG) {
17674 MVT VT = Op.getSimpleValueType();
17676 assert(VT.is256BitVector() && VT.isInteger() &&
17677 "Unsupported value type for operation");
17679 unsigned NumElems = VT.getVectorNumElements();
17682 // Extract the LHS vectors
17683 SDValue LHS = Op.getOperand(0);
17684 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
17685 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
17687 // Extract the RHS vectors
17688 SDValue RHS = Op.getOperand(1);
17689 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
17690 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
17692 MVT EltVT = VT.getVectorElementType();
17693 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
17695 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
17696 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1),
17697 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2));
17700 static SDValue LowerADD(SDValue Op, SelectionDAG &DAG) {
17701 if (Op.getValueType() == MVT::i1)
17702 return DAG.getNode(ISD::XOR, SDLoc(Op), Op.getValueType(),
17703 Op.getOperand(0), Op.getOperand(1));
17704 assert(Op.getSimpleValueType().is256BitVector() &&
17705 Op.getSimpleValueType().isInteger() &&
17706 "Only handle AVX 256-bit vector integer operation");
17707 return Lower256IntArith(Op, DAG);
17710 static SDValue LowerSUB(SDValue Op, SelectionDAG &DAG) {
17711 if (Op.getValueType() == MVT::i1)
17712 return DAG.getNode(ISD::XOR, SDLoc(Op), Op.getValueType(),
17713 Op.getOperand(0), Op.getOperand(1));
17714 assert(Op.getSimpleValueType().is256BitVector() &&
17715 Op.getSimpleValueType().isInteger() &&
17716 "Only handle AVX 256-bit vector integer operation");
17717 return Lower256IntArith(Op, DAG);
17720 static SDValue LowerMINMAX(SDValue Op, SelectionDAG &DAG) {
17721 assert(Op.getSimpleValueType().is256BitVector() &&
17722 Op.getSimpleValueType().isInteger() &&
17723 "Only handle AVX 256-bit vector integer operation");
17724 return Lower256IntArith(Op, DAG);
17727 static SDValue LowerMUL(SDValue Op, const X86Subtarget *Subtarget,
17728 SelectionDAG &DAG) {
17730 MVT VT = Op.getSimpleValueType();
17733 return DAG.getNode(ISD::AND, dl, VT, Op.getOperand(0), Op.getOperand(1));
17735 // Decompose 256-bit ops into smaller 128-bit ops.
17736 if (VT.is256BitVector() && !Subtarget->hasInt256())
17737 return Lower256IntArith(Op, DAG);
17739 SDValue A = Op.getOperand(0);
17740 SDValue B = Op.getOperand(1);
17742 // Lower v16i8/v32i8 mul as promotion to v8i16/v16i16 vector
17743 // pairs, multiply and truncate.
17744 if (VT == MVT::v16i8 || VT == MVT::v32i8) {
17745 if (Subtarget->hasInt256()) {
17746 if (VT == MVT::v32i8) {
17747 MVT SubVT = MVT::getVectorVT(MVT::i8, VT.getVectorNumElements() / 2);
17748 SDValue Lo = DAG.getIntPtrConstant(0, dl);
17749 SDValue Hi = DAG.getIntPtrConstant(VT.getVectorNumElements() / 2, dl);
17750 SDValue ALo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, A, Lo);
17751 SDValue BLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, B, Lo);
17752 SDValue AHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, A, Hi);
17753 SDValue BHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, B, Hi);
17754 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
17755 DAG.getNode(ISD::MUL, dl, SubVT, ALo, BLo),
17756 DAG.getNode(ISD::MUL, dl, SubVT, AHi, BHi));
17759 MVT ExVT = MVT::getVectorVT(MVT::i16, VT.getVectorNumElements());
17760 return DAG.getNode(
17761 ISD::TRUNCATE, dl, VT,
17762 DAG.getNode(ISD::MUL, dl, ExVT,
17763 DAG.getNode(ISD::SIGN_EXTEND, dl, ExVT, A),
17764 DAG.getNode(ISD::SIGN_EXTEND, dl, ExVT, B)));
17767 assert(VT == MVT::v16i8 &&
17768 "Pre-AVX2 support only supports v16i8 multiplication");
17769 MVT ExVT = MVT::v8i16;
17771 // Extract the lo parts and sign extend to i16
17773 if (Subtarget->hasSSE41()) {
17774 ALo = DAG.getNode(X86ISD::VSEXT, dl, ExVT, A);
17775 BLo = DAG.getNode(X86ISD::VSEXT, dl, ExVT, B);
17777 const int ShufMask[] = {-1, 0, -1, 1, -1, 2, -1, 3,
17778 -1, 4, -1, 5, -1, 6, -1, 7};
17779 ALo = DAG.getVectorShuffle(VT, dl, A, A, ShufMask);
17780 BLo = DAG.getVectorShuffle(VT, dl, B, B, ShufMask);
17781 ALo = DAG.getBitcast(ExVT, ALo);
17782 BLo = DAG.getBitcast(ExVT, BLo);
17783 ALo = DAG.getNode(ISD::SRA, dl, ExVT, ALo, DAG.getConstant(8, dl, ExVT));
17784 BLo = DAG.getNode(ISD::SRA, dl, ExVT, BLo, DAG.getConstant(8, dl, ExVT));
17787 // Extract the hi parts and sign extend to i16
17789 if (Subtarget->hasSSE41()) {
17790 const int ShufMask[] = {8, 9, 10, 11, 12, 13, 14, 15,
17791 -1, -1, -1, -1, -1, -1, -1, -1};
17792 AHi = DAG.getVectorShuffle(VT, dl, A, A, ShufMask);
17793 BHi = DAG.getVectorShuffle(VT, dl, B, B, ShufMask);
17794 AHi = DAG.getNode(X86ISD::VSEXT, dl, ExVT, AHi);
17795 BHi = DAG.getNode(X86ISD::VSEXT, dl, ExVT, BHi);
17797 const int ShufMask[] = {-1, 8, -1, 9, -1, 10, -1, 11,
17798 -1, 12, -1, 13, -1, 14, -1, 15};
17799 AHi = DAG.getVectorShuffle(VT, dl, A, A, ShufMask);
17800 BHi = DAG.getVectorShuffle(VT, dl, B, B, ShufMask);
17801 AHi = DAG.getBitcast(ExVT, AHi);
17802 BHi = DAG.getBitcast(ExVT, BHi);
17803 AHi = DAG.getNode(ISD::SRA, dl, ExVT, AHi, DAG.getConstant(8, dl, ExVT));
17804 BHi = DAG.getNode(ISD::SRA, dl, ExVT, BHi, DAG.getConstant(8, dl, ExVT));
17807 // Multiply, mask the lower 8bits of the lo/hi results and pack
17808 SDValue RLo = DAG.getNode(ISD::MUL, dl, ExVT, ALo, BLo);
17809 SDValue RHi = DAG.getNode(ISD::MUL, dl, ExVT, AHi, BHi);
17810 RLo = DAG.getNode(ISD::AND, dl, ExVT, RLo, DAG.getConstant(255, dl, ExVT));
17811 RHi = DAG.getNode(ISD::AND, dl, ExVT, RHi, DAG.getConstant(255, dl, ExVT));
17812 return DAG.getNode(X86ISD::PACKUS, dl, VT, RLo, RHi);
17815 // Lower v4i32 mul as 2x shuffle, 2x pmuludq, 2x shuffle.
17816 if (VT == MVT::v4i32) {
17817 assert(Subtarget->hasSSE2() && !Subtarget->hasSSE41() &&
17818 "Should not custom lower when pmuldq is available!");
17820 // Extract the odd parts.
17821 static const int UnpackMask[] = { 1, -1, 3, -1 };
17822 SDValue Aodds = DAG.getVectorShuffle(VT, dl, A, A, UnpackMask);
17823 SDValue Bodds = DAG.getVectorShuffle(VT, dl, B, B, UnpackMask);
17825 // Multiply the even parts.
17826 SDValue Evens = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, A, B);
17827 // Now multiply odd parts.
17828 SDValue Odds = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, Aodds, Bodds);
17830 Evens = DAG.getBitcast(VT, Evens);
17831 Odds = DAG.getBitcast(VT, Odds);
17833 // Merge the two vectors back together with a shuffle. This expands into 2
17835 static const int ShufMask[] = { 0, 4, 2, 6 };
17836 return DAG.getVectorShuffle(VT, dl, Evens, Odds, ShufMask);
17839 assert((VT == MVT::v2i64 || VT == MVT::v4i64 || VT == MVT::v8i64) &&
17840 "Only know how to lower V2I64/V4I64/V8I64 multiply");
17842 // Ahi = psrlqi(a, 32);
17843 // Bhi = psrlqi(b, 32);
17845 // AloBlo = pmuludq(a, b);
17846 // AloBhi = pmuludq(a, Bhi);
17847 // AhiBlo = pmuludq(Ahi, b);
17849 // AloBhi = psllqi(AloBhi, 32);
17850 // AhiBlo = psllqi(AhiBlo, 32);
17851 // return AloBlo + AloBhi + AhiBlo;
17853 SDValue Ahi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, A, 32, DAG);
17854 SDValue Bhi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, B, 32, DAG);
17856 SDValue AhiBlo = Ahi;
17857 SDValue AloBhi = Bhi;
17858 // Bit cast to 32-bit vectors for MULUDQ
17859 EVT MulVT = (VT == MVT::v2i64) ? MVT::v4i32 :
17860 (VT == MVT::v4i64) ? MVT::v8i32 : MVT::v16i32;
17861 A = DAG.getBitcast(MulVT, A);
17862 B = DAG.getBitcast(MulVT, B);
17863 Ahi = DAG.getBitcast(MulVT, Ahi);
17864 Bhi = DAG.getBitcast(MulVT, Bhi);
17866 SDValue AloBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, B);
17867 // After shifting right const values the result may be all-zero.
17868 if (!ISD::isBuildVectorAllZeros(Ahi.getNode())) {
17869 AhiBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, Ahi, B);
17870 AhiBlo = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AhiBlo, 32, DAG);
17872 if (!ISD::isBuildVectorAllZeros(Bhi.getNode())) {
17873 AloBhi = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, Bhi);
17874 AloBhi = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AloBhi, 32, DAG);
17877 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
17878 return DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
17881 SDValue X86TargetLowering::LowerWin64_i128OP(SDValue Op, SelectionDAG &DAG) const {
17882 assert(Subtarget->isTargetWin64() && "Unexpected target");
17883 EVT VT = Op.getValueType();
17884 assert(VT.isInteger() && VT.getSizeInBits() == 128 &&
17885 "Unexpected return type for lowering");
17889 switch (Op->getOpcode()) {
17890 default: llvm_unreachable("Unexpected request for libcall!");
17891 case ISD::SDIV: isSigned = true; LC = RTLIB::SDIV_I128; break;
17892 case ISD::UDIV: isSigned = false; LC = RTLIB::UDIV_I128; break;
17893 case ISD::SREM: isSigned = true; LC = RTLIB::SREM_I128; break;
17894 case ISD::UREM: isSigned = false; LC = RTLIB::UREM_I128; break;
17895 case ISD::SDIVREM: isSigned = true; LC = RTLIB::SDIVREM_I128; break;
17896 case ISD::UDIVREM: isSigned = false; LC = RTLIB::UDIVREM_I128; break;
17900 SDValue InChain = DAG.getEntryNode();
17902 TargetLowering::ArgListTy Args;
17903 TargetLowering::ArgListEntry Entry;
17904 for (unsigned i = 0, e = Op->getNumOperands(); i != e; ++i) {
17905 EVT ArgVT = Op->getOperand(i).getValueType();
17906 assert(ArgVT.isInteger() && ArgVT.getSizeInBits() == 128 &&
17907 "Unexpected argument type for lowering");
17908 SDValue StackPtr = DAG.CreateStackTemporary(ArgVT, 16);
17909 Entry.Node = StackPtr;
17910 InChain = DAG.getStore(InChain, dl, Op->getOperand(i), StackPtr, MachinePointerInfo(),
17912 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
17913 Entry.Ty = PointerType::get(ArgTy,0);
17914 Entry.isSExt = false;
17915 Entry.isZExt = false;
17916 Args.push_back(Entry);
17919 SDValue Callee = DAG.getExternalSymbol(getLibcallName(LC),
17920 getPointerTy(DAG.getDataLayout()));
17922 TargetLowering::CallLoweringInfo CLI(DAG);
17923 CLI.setDebugLoc(dl).setChain(InChain)
17924 .setCallee(getLibcallCallingConv(LC),
17925 static_cast<EVT>(MVT::v2i64).getTypeForEVT(*DAG.getContext()),
17926 Callee, std::move(Args), 0)
17927 .setInRegister().setSExtResult(isSigned).setZExtResult(!isSigned);
17929 std::pair<SDValue, SDValue> CallInfo = LowerCallTo(CLI);
17930 return DAG.getBitcast(VT, CallInfo.first);
17933 static SDValue LowerMUL_LOHI(SDValue Op, const X86Subtarget *Subtarget,
17934 SelectionDAG &DAG) {
17935 SDValue Op0 = Op.getOperand(0), Op1 = Op.getOperand(1);
17936 EVT VT = Op0.getValueType();
17939 assert((VT == MVT::v4i32 && Subtarget->hasSSE2()) ||
17940 (VT == MVT::v8i32 && Subtarget->hasInt256()));
17942 // PMULxD operations multiply each even value (starting at 0) of LHS with
17943 // the related value of RHS and produce a widen result.
17944 // E.g., PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
17945 // => <2 x i64> <ae|cg>
17947 // In other word, to have all the results, we need to perform two PMULxD:
17948 // 1. one with the even values.
17949 // 2. one with the odd values.
17950 // To achieve #2, with need to place the odd values at an even position.
17952 // Place the odd value at an even position (basically, shift all values 1
17953 // step to the left):
17954 const int Mask[] = {1, -1, 3, -1, 5, -1, 7, -1};
17955 // <a|b|c|d> => <b|undef|d|undef>
17956 SDValue Odd0 = DAG.getVectorShuffle(VT, dl, Op0, Op0, Mask);
17957 // <e|f|g|h> => <f|undef|h|undef>
17958 SDValue Odd1 = DAG.getVectorShuffle(VT, dl, Op1, Op1, Mask);
17960 // Emit two multiplies, one for the lower 2 ints and one for the higher 2
17962 MVT MulVT = VT == MVT::v4i32 ? MVT::v2i64 : MVT::v4i64;
17963 bool IsSigned = Op->getOpcode() == ISD::SMUL_LOHI;
17965 (!IsSigned || !Subtarget->hasSSE41()) ? X86ISD::PMULUDQ : X86ISD::PMULDQ;
17966 // PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
17967 // => <2 x i64> <ae|cg>
17968 SDValue Mul1 = DAG.getBitcast(VT, DAG.getNode(Opcode, dl, MulVT, Op0, Op1));
17969 // PMULUDQ <4 x i32> <b|undef|d|undef>, <4 x i32> <f|undef|h|undef>
17970 // => <2 x i64> <bf|dh>
17971 SDValue Mul2 = DAG.getBitcast(VT, DAG.getNode(Opcode, dl, MulVT, Odd0, Odd1));
17973 // Shuffle it back into the right order.
17974 SDValue Highs, Lows;
17975 if (VT == MVT::v8i32) {
17976 const int HighMask[] = {1, 9, 3, 11, 5, 13, 7, 15};
17977 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
17978 const int LowMask[] = {0, 8, 2, 10, 4, 12, 6, 14};
17979 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
17981 const int HighMask[] = {1, 5, 3, 7};
17982 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
17983 const int LowMask[] = {0, 4, 2, 6};
17984 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
17987 // If we have a signed multiply but no PMULDQ fix up the high parts of a
17988 // unsigned multiply.
17989 if (IsSigned && !Subtarget->hasSSE41()) {
17990 SDValue ShAmt = DAG.getConstant(
17992 DAG.getTargetLoweringInfo().getShiftAmountTy(VT, DAG.getDataLayout()));
17993 SDValue T1 = DAG.getNode(ISD::AND, dl, VT,
17994 DAG.getNode(ISD::SRA, dl, VT, Op0, ShAmt), Op1);
17995 SDValue T2 = DAG.getNode(ISD::AND, dl, VT,
17996 DAG.getNode(ISD::SRA, dl, VT, Op1, ShAmt), Op0);
17998 SDValue Fixup = DAG.getNode(ISD::ADD, dl, VT, T1, T2);
17999 Highs = DAG.getNode(ISD::SUB, dl, VT, Highs, Fixup);
18002 // The first result of MUL_LOHI is actually the low value, followed by the
18004 SDValue Ops[] = {Lows, Highs};
18005 return DAG.getMergeValues(Ops, dl);
18008 // Return true if the required (according to Opcode) shift-imm form is natively
18009 // supported by the Subtarget
18010 static bool SupportedVectorShiftWithImm(MVT VT, const X86Subtarget *Subtarget,
18012 if (VT.getScalarSizeInBits() < 16)
18015 if (VT.is512BitVector() &&
18016 (VT.getScalarSizeInBits() > 16 || Subtarget->hasBWI()))
18019 bool LShift = VT.is128BitVector() ||
18020 (VT.is256BitVector() && Subtarget->hasInt256());
18022 bool AShift = LShift && (Subtarget->hasVLX() ||
18023 (VT != MVT::v2i64 && VT != MVT::v4i64));
18024 return (Opcode == ISD::SRA) ? AShift : LShift;
18027 // The shift amount is a variable, but it is the same for all vector lanes.
18028 // These instructions are defined together with shift-immediate.
18030 bool SupportedVectorShiftWithBaseAmnt(MVT VT, const X86Subtarget *Subtarget,
18032 return SupportedVectorShiftWithImm(VT, Subtarget, Opcode);
18035 // Return true if the required (according to Opcode) variable-shift form is
18036 // natively supported by the Subtarget
18037 static bool SupportedVectorVarShift(MVT VT, const X86Subtarget *Subtarget,
18040 if (!Subtarget->hasInt256() || VT.getScalarSizeInBits() < 16)
18043 // vXi16 supported only on AVX-512, BWI
18044 if (VT.getScalarSizeInBits() == 16 && !Subtarget->hasBWI())
18047 if (VT.is512BitVector() || Subtarget->hasVLX())
18050 bool LShift = VT.is128BitVector() || VT.is256BitVector();
18051 bool AShift = LShift && VT != MVT::v2i64 && VT != MVT::v4i64;
18052 return (Opcode == ISD::SRA) ? AShift : LShift;
18055 static SDValue LowerScalarImmediateShift(SDValue Op, SelectionDAG &DAG,
18056 const X86Subtarget *Subtarget) {
18057 MVT VT = Op.getSimpleValueType();
18059 SDValue R = Op.getOperand(0);
18060 SDValue Amt = Op.getOperand(1);
18062 unsigned X86Opc = (Op.getOpcode() == ISD::SHL) ? X86ISD::VSHLI :
18063 (Op.getOpcode() == ISD::SRL) ? X86ISD::VSRLI : X86ISD::VSRAI;
18065 auto ArithmeticShiftRight64 = [&](uint64_t ShiftAmt) {
18066 assert((VT == MVT::v2i64 || VT == MVT::v4i64) && "Unexpected SRA type");
18067 MVT ExVT = MVT::getVectorVT(MVT::i32, VT.getVectorNumElements() * 2);
18068 SDValue Ex = DAG.getBitcast(ExVT, R);
18070 if (ShiftAmt >= 32) {
18071 // Splat sign to upper i32 dst, and SRA upper i32 src to lower i32.
18073 getTargetVShiftByConstNode(X86ISD::VSRAI, dl, ExVT, Ex, 31, DAG);
18074 SDValue Lower = getTargetVShiftByConstNode(X86ISD::VSRAI, dl, ExVT, Ex,
18075 ShiftAmt - 32, DAG);
18076 if (VT == MVT::v2i64)
18077 Ex = DAG.getVectorShuffle(ExVT, dl, Upper, Lower, {5, 1, 7, 3});
18078 if (VT == MVT::v4i64)
18079 Ex = DAG.getVectorShuffle(ExVT, dl, Upper, Lower,
18080 {9, 1, 11, 3, 13, 5, 15, 7});
18082 // SRA upper i32, SHL whole i64 and select lower i32.
18083 SDValue Upper = getTargetVShiftByConstNode(X86ISD::VSRAI, dl, ExVT, Ex,
18086 getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, R, ShiftAmt, DAG);
18087 Lower = DAG.getBitcast(ExVT, Lower);
18088 if (VT == MVT::v2i64)
18089 Ex = DAG.getVectorShuffle(ExVT, dl, Upper, Lower, {4, 1, 6, 3});
18090 if (VT == MVT::v4i64)
18091 Ex = DAG.getVectorShuffle(ExVT, dl, Upper, Lower,
18092 {8, 1, 10, 3, 12, 5, 14, 7});
18094 return DAG.getBitcast(VT, Ex);
18097 // Optimize shl/srl/sra with constant shift amount.
18098 if (auto *BVAmt = dyn_cast<BuildVectorSDNode>(Amt)) {
18099 if (auto *ShiftConst = BVAmt->getConstantSplatNode()) {
18100 uint64_t ShiftAmt = ShiftConst->getZExtValue();
18102 if (SupportedVectorShiftWithImm(VT, Subtarget, Op.getOpcode()))
18103 return getTargetVShiftByConstNode(X86Opc, dl, VT, R, ShiftAmt, DAG);
18105 // i64 SRA needs to be performed as partial shifts.
18106 if ((VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64)) &&
18107 Op.getOpcode() == ISD::SRA && !Subtarget->hasXOP())
18108 return ArithmeticShiftRight64(ShiftAmt);
18110 if (VT == MVT::v16i8 || (Subtarget->hasInt256() && VT == MVT::v32i8)) {
18111 unsigned NumElts = VT.getVectorNumElements();
18112 MVT ShiftVT = MVT::getVectorVT(MVT::i16, NumElts / 2);
18114 // Simple i8 add case
18115 if (Op.getOpcode() == ISD::SHL && ShiftAmt == 1)
18116 return DAG.getNode(ISD::ADD, dl, VT, R, R);
18118 // ashr(R, 7) === cmp_slt(R, 0)
18119 if (Op.getOpcode() == ISD::SRA && ShiftAmt == 7) {
18120 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
18121 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
18124 // XOP can shift v16i8 directly instead of as shift v8i16 + mask.
18125 if (VT == MVT::v16i8 && Subtarget->hasXOP())
18128 if (Op.getOpcode() == ISD::SHL) {
18129 // Make a large shift.
18130 SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, ShiftVT,
18132 SHL = DAG.getBitcast(VT, SHL);
18133 // Zero out the rightmost bits.
18134 SmallVector<SDValue, 32> V(
18135 NumElts, DAG.getConstant(uint8_t(-1U << ShiftAmt), dl, MVT::i8));
18136 return DAG.getNode(ISD::AND, dl, VT, SHL,
18137 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
18139 if (Op.getOpcode() == ISD::SRL) {
18140 // Make a large shift.
18141 SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, ShiftVT,
18143 SRL = DAG.getBitcast(VT, SRL);
18144 // Zero out the leftmost bits.
18145 SmallVector<SDValue, 32> V(
18146 NumElts, DAG.getConstant(uint8_t(-1U) >> ShiftAmt, dl, MVT::i8));
18147 return DAG.getNode(ISD::AND, dl, VT, SRL,
18148 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
18150 if (Op.getOpcode() == ISD::SRA) {
18151 // ashr(R, Amt) === sub(xor(lshr(R, Amt), Mask), Mask)
18152 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
18153 SmallVector<SDValue, 32> V(NumElts,
18154 DAG.getConstant(128 >> ShiftAmt, dl,
18156 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V);
18157 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
18158 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
18161 llvm_unreachable("Unknown shift opcode.");
18166 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
18167 if (!Subtarget->is64Bit() && !Subtarget->hasXOP() &&
18168 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64))) {
18170 // Peek through any splat that was introduced for i64 shift vectorization.
18171 int SplatIndex = -1;
18172 if (ShuffleVectorSDNode *SVN = dyn_cast<ShuffleVectorSDNode>(Amt.getNode()))
18173 if (SVN->isSplat()) {
18174 SplatIndex = SVN->getSplatIndex();
18175 Amt = Amt.getOperand(0);
18176 assert(SplatIndex < (int)VT.getVectorNumElements() &&
18177 "Splat shuffle referencing second operand");
18180 if (Amt.getOpcode() != ISD::BITCAST ||
18181 Amt.getOperand(0).getOpcode() != ISD::BUILD_VECTOR)
18184 Amt = Amt.getOperand(0);
18185 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
18186 VT.getVectorNumElements();
18187 unsigned RatioInLog2 = Log2_32_Ceil(Ratio);
18188 uint64_t ShiftAmt = 0;
18189 unsigned BaseOp = (SplatIndex < 0 ? 0 : SplatIndex * Ratio);
18190 for (unsigned i = 0; i != Ratio; ++i) {
18191 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Amt.getOperand(i + BaseOp));
18195 ShiftAmt |= C->getZExtValue() << (i * (1 << (6 - RatioInLog2)));
18198 // Check remaining shift amounts (if not a splat).
18199 if (SplatIndex < 0) {
18200 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
18201 uint64_t ShAmt = 0;
18202 for (unsigned j = 0; j != Ratio; ++j) {
18203 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Amt.getOperand(i + j));
18207 ShAmt |= C->getZExtValue() << (j * (1 << (6 - RatioInLog2)));
18209 if (ShAmt != ShiftAmt)
18214 if (SupportedVectorShiftWithImm(VT, Subtarget, Op.getOpcode()))
18215 return getTargetVShiftByConstNode(X86Opc, dl, VT, R, ShiftAmt, DAG);
18217 if (Op.getOpcode() == ISD::SRA)
18218 return ArithmeticShiftRight64(ShiftAmt);
18224 static SDValue LowerScalarVariableShift(SDValue Op, SelectionDAG &DAG,
18225 const X86Subtarget* Subtarget) {
18226 MVT VT = Op.getSimpleValueType();
18228 SDValue R = Op.getOperand(0);
18229 SDValue Amt = Op.getOperand(1);
18231 unsigned X86OpcI = (Op.getOpcode() == ISD::SHL) ? X86ISD::VSHLI :
18232 (Op.getOpcode() == ISD::SRL) ? X86ISD::VSRLI : X86ISD::VSRAI;
18234 unsigned X86OpcV = (Op.getOpcode() == ISD::SHL) ? X86ISD::VSHL :
18235 (Op.getOpcode() == ISD::SRL) ? X86ISD::VSRL : X86ISD::VSRA;
18237 if (SupportedVectorShiftWithBaseAmnt(VT, Subtarget, Op.getOpcode())) {
18239 MVT EltVT = VT.getVectorElementType();
18241 if (BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(Amt)) {
18242 // Check if this build_vector node is doing a splat.
18243 // If so, then set BaseShAmt equal to the splat value.
18244 BaseShAmt = BV->getSplatValue();
18245 if (BaseShAmt && BaseShAmt.getOpcode() == ISD::UNDEF)
18246 BaseShAmt = SDValue();
18248 if (Amt.getOpcode() == ISD::EXTRACT_SUBVECTOR)
18249 Amt = Amt.getOperand(0);
18251 ShuffleVectorSDNode *SVN = dyn_cast<ShuffleVectorSDNode>(Amt);
18252 if (SVN && SVN->isSplat()) {
18253 unsigned SplatIdx = (unsigned)SVN->getSplatIndex();
18254 SDValue InVec = Amt.getOperand(0);
18255 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
18256 assert((SplatIdx < InVec.getValueType().getVectorNumElements()) &&
18257 "Unexpected shuffle index found!");
18258 BaseShAmt = InVec.getOperand(SplatIdx);
18259 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
18260 if (ConstantSDNode *C =
18261 dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
18262 if (C->getZExtValue() == SplatIdx)
18263 BaseShAmt = InVec.getOperand(1);
18268 // Avoid introducing an extract element from a shuffle.
18269 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InVec,
18270 DAG.getIntPtrConstant(SplatIdx, dl));
18274 if (BaseShAmt.getNode()) {
18275 assert(EltVT.bitsLE(MVT::i64) && "Unexpected element type!");
18276 if (EltVT != MVT::i64 && EltVT.bitsGT(MVT::i32))
18277 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, BaseShAmt);
18278 else if (EltVT.bitsLT(MVT::i32))
18279 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, BaseShAmt);
18281 return getTargetVShiftNode(X86OpcI, dl, VT, R, BaseShAmt, DAG);
18285 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
18286 if (!Subtarget->is64Bit() && VT == MVT::v2i64 &&
18287 Amt.getOpcode() == ISD::BITCAST &&
18288 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
18289 Amt = Amt.getOperand(0);
18290 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
18291 VT.getVectorNumElements();
18292 std::vector<SDValue> Vals(Ratio);
18293 for (unsigned i = 0; i != Ratio; ++i)
18294 Vals[i] = Amt.getOperand(i);
18295 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
18296 for (unsigned j = 0; j != Ratio; ++j)
18297 if (Vals[j] != Amt.getOperand(i + j))
18301 if (SupportedVectorShiftWithBaseAmnt(VT, Subtarget, Op.getOpcode()))
18302 return DAG.getNode(X86OpcV, dl, VT, R, Op.getOperand(1));
18307 static SDValue LowerShift(SDValue Op, const X86Subtarget* Subtarget,
18308 SelectionDAG &DAG) {
18309 MVT VT = Op.getSimpleValueType();
18311 SDValue R = Op.getOperand(0);
18312 SDValue Amt = Op.getOperand(1);
18314 assert(VT.isVector() && "Custom lowering only for vector shifts!");
18315 assert(Subtarget->hasSSE2() && "Only custom lower when we have SSE2!");
18317 if (SDValue V = LowerScalarImmediateShift(Op, DAG, Subtarget))
18320 if (SDValue V = LowerScalarVariableShift(Op, DAG, Subtarget))
18323 if (SupportedVectorVarShift(VT, Subtarget, Op.getOpcode()))
18326 // XOP has 128-bit variable logical/arithmetic shifts.
18327 // +ve/-ve Amt = shift left/right.
18328 if (Subtarget->hasXOP() &&
18329 (VT == MVT::v2i64 || VT == MVT::v4i32 ||
18330 VT == MVT::v8i16 || VT == MVT::v16i8)) {
18331 if (Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SRA) {
18332 SDValue Zero = getZeroVector(VT, Subtarget, DAG, dl);
18333 Amt = DAG.getNode(ISD::SUB, dl, VT, Zero, Amt);
18335 if (Op.getOpcode() == ISD::SHL || Op.getOpcode() == ISD::SRL)
18336 return DAG.getNode(X86ISD::VPSHL, dl, VT, R, Amt);
18337 if (Op.getOpcode() == ISD::SRA)
18338 return DAG.getNode(X86ISD::VPSHA, dl, VT, R, Amt);
18341 // 2i64 vector logical shifts can efficiently avoid scalarization - do the
18342 // shifts per-lane and then shuffle the partial results back together.
18343 if (VT == MVT::v2i64 && Op.getOpcode() != ISD::SRA) {
18344 // Splat the shift amounts so the scalar shifts above will catch it.
18345 SDValue Amt0 = DAG.getVectorShuffle(VT, dl, Amt, Amt, {0, 0});
18346 SDValue Amt1 = DAG.getVectorShuffle(VT, dl, Amt, Amt, {1, 1});
18347 SDValue R0 = DAG.getNode(Op->getOpcode(), dl, VT, R, Amt0);
18348 SDValue R1 = DAG.getNode(Op->getOpcode(), dl, VT, R, Amt1);
18349 return DAG.getVectorShuffle(VT, dl, R0, R1, {0, 3});
18352 // i64 vector arithmetic shift can be emulated with the transform:
18353 // M = lshr(SIGN_BIT, Amt)
18354 // ashr(R, Amt) === sub(xor(lshr(R, Amt), M), M)
18355 if ((VT == MVT::v2i64 || (VT == MVT::v4i64 && Subtarget->hasInt256())) &&
18356 Op.getOpcode() == ISD::SRA) {
18357 SDValue S = DAG.getConstant(APInt::getSignBit(64), dl, VT);
18358 SDValue M = DAG.getNode(ISD::SRL, dl, VT, S, Amt);
18359 R = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
18360 R = DAG.getNode(ISD::XOR, dl, VT, R, M);
18361 R = DAG.getNode(ISD::SUB, dl, VT, R, M);
18365 // If possible, lower this packed shift into a vector multiply instead of
18366 // expanding it into a sequence of scalar shifts.
18367 // Do this only if the vector shift count is a constant build_vector.
18368 if (Op.getOpcode() == ISD::SHL &&
18369 (VT == MVT::v8i16 || VT == MVT::v4i32 ||
18370 (Subtarget->hasInt256() && VT == MVT::v16i16)) &&
18371 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
18372 SmallVector<SDValue, 8> Elts;
18373 EVT SVT = VT.getScalarType();
18374 unsigned SVTBits = SVT.getSizeInBits();
18375 const APInt &One = APInt(SVTBits, 1);
18376 unsigned NumElems = VT.getVectorNumElements();
18378 for (unsigned i=0; i !=NumElems; ++i) {
18379 SDValue Op = Amt->getOperand(i);
18380 if (Op->getOpcode() == ISD::UNDEF) {
18381 Elts.push_back(Op);
18385 ConstantSDNode *ND = cast<ConstantSDNode>(Op);
18386 const APInt &C = APInt(SVTBits, ND->getAPIntValue().getZExtValue());
18387 uint64_t ShAmt = C.getZExtValue();
18388 if (ShAmt >= SVTBits) {
18389 Elts.push_back(DAG.getUNDEF(SVT));
18392 Elts.push_back(DAG.getConstant(One.shl(ShAmt), dl, SVT));
18394 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
18395 return DAG.getNode(ISD::MUL, dl, VT, R, BV);
18398 // Lower SHL with variable shift amount.
18399 if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) {
18400 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(23, dl, VT));
18402 Op = DAG.getNode(ISD::ADD, dl, VT, Op,
18403 DAG.getConstant(0x3f800000U, dl, VT));
18404 Op = DAG.getBitcast(MVT::v4f32, Op);
18405 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op);
18406 return DAG.getNode(ISD::MUL, dl, VT, Op, R);
18409 // If possible, lower this shift as a sequence of two shifts by
18410 // constant plus a MOVSS/MOVSD instead of scalarizing it.
18412 // (v4i32 (srl A, (build_vector < X, Y, Y, Y>)))
18414 // Could be rewritten as:
18415 // (v4i32 (MOVSS (srl A, <Y,Y,Y,Y>), (srl A, <X,X,X,X>)))
18417 // The advantage is that the two shifts from the example would be
18418 // lowered as X86ISD::VSRLI nodes. This would be cheaper than scalarizing
18419 // the vector shift into four scalar shifts plus four pairs of vector
18421 if ((VT == MVT::v8i16 || VT == MVT::v4i32) &&
18422 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
18423 unsigned TargetOpcode = X86ISD::MOVSS;
18424 bool CanBeSimplified;
18425 // The splat value for the first packed shift (the 'X' from the example).
18426 SDValue Amt1 = Amt->getOperand(0);
18427 // The splat value for the second packed shift (the 'Y' from the example).
18428 SDValue Amt2 = (VT == MVT::v4i32) ? Amt->getOperand(1) :
18429 Amt->getOperand(2);
18431 // See if it is possible to replace this node with a sequence of
18432 // two shifts followed by a MOVSS/MOVSD
18433 if (VT == MVT::v4i32) {
18434 // Check if it is legal to use a MOVSS.
18435 CanBeSimplified = Amt2 == Amt->getOperand(2) &&
18436 Amt2 == Amt->getOperand(3);
18437 if (!CanBeSimplified) {
18438 // Otherwise, check if we can still simplify this node using a MOVSD.
18439 CanBeSimplified = Amt1 == Amt->getOperand(1) &&
18440 Amt->getOperand(2) == Amt->getOperand(3);
18441 TargetOpcode = X86ISD::MOVSD;
18442 Amt2 = Amt->getOperand(2);
18445 // Do similar checks for the case where the machine value type
18447 CanBeSimplified = Amt1 == Amt->getOperand(1);
18448 for (unsigned i=3; i != 8 && CanBeSimplified; ++i)
18449 CanBeSimplified = Amt2 == Amt->getOperand(i);
18451 if (!CanBeSimplified) {
18452 TargetOpcode = X86ISD::MOVSD;
18453 CanBeSimplified = true;
18454 Amt2 = Amt->getOperand(4);
18455 for (unsigned i=0; i != 4 && CanBeSimplified; ++i)
18456 CanBeSimplified = Amt1 == Amt->getOperand(i);
18457 for (unsigned j=4; j != 8 && CanBeSimplified; ++j)
18458 CanBeSimplified = Amt2 == Amt->getOperand(j);
18462 if (CanBeSimplified && isa<ConstantSDNode>(Amt1) &&
18463 isa<ConstantSDNode>(Amt2)) {
18464 // Replace this node with two shifts followed by a MOVSS/MOVSD.
18465 EVT CastVT = MVT::v4i32;
18467 DAG.getConstant(cast<ConstantSDNode>(Amt1)->getAPIntValue(), dl, VT);
18468 SDValue Shift1 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat1);
18470 DAG.getConstant(cast<ConstantSDNode>(Amt2)->getAPIntValue(), dl, VT);
18471 SDValue Shift2 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat2);
18472 if (TargetOpcode == X86ISD::MOVSD)
18473 CastVT = MVT::v2i64;
18474 SDValue BitCast1 = DAG.getBitcast(CastVT, Shift1);
18475 SDValue BitCast2 = DAG.getBitcast(CastVT, Shift2);
18476 SDValue Result = getTargetShuffleNode(TargetOpcode, dl, CastVT, BitCast2,
18478 return DAG.getBitcast(VT, Result);
18482 // v4i32 Non Uniform Shifts.
18483 // If the shift amount is constant we can shift each lane using the SSE2
18484 // immediate shifts, else we need to zero-extend each lane to the lower i64
18485 // and shift using the SSE2 variable shifts.
18486 // The separate results can then be blended together.
18487 if (VT == MVT::v4i32) {
18488 unsigned Opc = Op.getOpcode();
18489 SDValue Amt0, Amt1, Amt2, Amt3;
18490 if (ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
18491 Amt0 = DAG.getVectorShuffle(VT, dl, Amt, DAG.getUNDEF(VT), {0, 0, 0, 0});
18492 Amt1 = DAG.getVectorShuffle(VT, dl, Amt, DAG.getUNDEF(VT), {1, 1, 1, 1});
18493 Amt2 = DAG.getVectorShuffle(VT, dl, Amt, DAG.getUNDEF(VT), {2, 2, 2, 2});
18494 Amt3 = DAG.getVectorShuffle(VT, dl, Amt, DAG.getUNDEF(VT), {3, 3, 3, 3});
18496 // ISD::SHL is handled above but we include it here for completeness.
18499 llvm_unreachable("Unknown target vector shift node");
18501 Opc = X86ISD::VSHL;
18504 Opc = X86ISD::VSRL;
18507 Opc = X86ISD::VSRA;
18510 // The SSE2 shifts use the lower i64 as the same shift amount for
18511 // all lanes and the upper i64 is ignored. These shuffle masks
18512 // optimally zero-extend each lanes on SSE2/SSE41/AVX targets.
18513 SDValue Z = getZeroVector(VT, Subtarget, DAG, dl);
18514 Amt0 = DAG.getVectorShuffle(VT, dl, Amt, Z, {0, 4, -1, -1});
18515 Amt1 = DAG.getVectorShuffle(VT, dl, Amt, Z, {1, 5, -1, -1});
18516 Amt2 = DAG.getVectorShuffle(VT, dl, Amt, Z, {2, 6, -1, -1});
18517 Amt3 = DAG.getVectorShuffle(VT, dl, Amt, Z, {3, 7, -1, -1});
18520 SDValue R0 = DAG.getNode(Opc, dl, VT, R, Amt0);
18521 SDValue R1 = DAG.getNode(Opc, dl, VT, R, Amt1);
18522 SDValue R2 = DAG.getNode(Opc, dl, VT, R, Amt2);
18523 SDValue R3 = DAG.getNode(Opc, dl, VT, R, Amt3);
18524 SDValue R02 = DAG.getVectorShuffle(VT, dl, R0, R2, {0, -1, 6, -1});
18525 SDValue R13 = DAG.getVectorShuffle(VT, dl, R1, R3, {-1, 1, -1, 7});
18526 return DAG.getVectorShuffle(VT, dl, R02, R13, {0, 5, 2, 7});
18529 if (VT == MVT::v16i8 ||
18530 (VT == MVT::v32i8 && Subtarget->hasInt256() && !Subtarget->hasXOP())) {
18531 MVT ExtVT = MVT::getVectorVT(MVT::i16, VT.getVectorNumElements() / 2);
18532 unsigned ShiftOpcode = Op->getOpcode();
18534 auto SignBitSelect = [&](MVT SelVT, SDValue Sel, SDValue V0, SDValue V1) {
18535 // On SSE41 targets we make use of the fact that VSELECT lowers
18536 // to PBLENDVB which selects bytes based just on the sign bit.
18537 if (Subtarget->hasSSE41()) {
18538 V0 = DAG.getBitcast(VT, V0);
18539 V1 = DAG.getBitcast(VT, V1);
18540 Sel = DAG.getBitcast(VT, Sel);
18541 return DAG.getBitcast(SelVT,
18542 DAG.getNode(ISD::VSELECT, dl, VT, Sel, V0, V1));
18544 // On pre-SSE41 targets we test for the sign bit by comparing to
18545 // zero - a negative value will set all bits of the lanes to true
18546 // and VSELECT uses that in its OR(AND(V0,C),AND(V1,~C)) lowering.
18547 SDValue Z = getZeroVector(SelVT, Subtarget, DAG, dl);
18548 SDValue C = DAG.getNode(X86ISD::PCMPGT, dl, SelVT, Z, Sel);
18549 return DAG.getNode(ISD::VSELECT, dl, SelVT, C, V0, V1);
18552 // Turn 'a' into a mask suitable for VSELECT: a = a << 5;
18553 // We can safely do this using i16 shifts as we're only interested in
18554 // the 3 lower bits of each byte.
18555 Amt = DAG.getBitcast(ExtVT, Amt);
18556 Amt = DAG.getNode(ISD::SHL, dl, ExtVT, Amt, DAG.getConstant(5, dl, ExtVT));
18557 Amt = DAG.getBitcast(VT, Amt);
18559 if (Op->getOpcode() == ISD::SHL || Op->getOpcode() == ISD::SRL) {
18560 // r = VSELECT(r, shift(r, 4), a);
18562 DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(4, dl, VT));
18563 R = SignBitSelect(VT, Amt, M, R);
18566 Amt = DAG.getNode(ISD::ADD, dl, VT, Amt, Amt);
18568 // r = VSELECT(r, shift(r, 2), a);
18569 M = DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(2, dl, VT));
18570 R = SignBitSelect(VT, Amt, M, R);
18573 Amt = DAG.getNode(ISD::ADD, dl, VT, Amt, Amt);
18575 // return VSELECT(r, shift(r, 1), a);
18576 M = DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(1, dl, VT));
18577 R = SignBitSelect(VT, Amt, M, R);
18581 if (Op->getOpcode() == ISD::SRA) {
18582 // For SRA we need to unpack each byte to the higher byte of a i16 vector
18583 // so we can correctly sign extend. We don't care what happens to the
18585 SDValue ALo = DAG.getNode(X86ISD::UNPCKL, dl, VT, DAG.getUNDEF(VT), Amt);
18586 SDValue AHi = DAG.getNode(X86ISD::UNPCKH, dl, VT, DAG.getUNDEF(VT), Amt);
18587 SDValue RLo = DAG.getNode(X86ISD::UNPCKL, dl, VT, DAG.getUNDEF(VT), R);
18588 SDValue RHi = DAG.getNode(X86ISD::UNPCKH, dl, VT, DAG.getUNDEF(VT), R);
18589 ALo = DAG.getBitcast(ExtVT, ALo);
18590 AHi = DAG.getBitcast(ExtVT, AHi);
18591 RLo = DAG.getBitcast(ExtVT, RLo);
18592 RHi = DAG.getBitcast(ExtVT, RHi);
18594 // r = VSELECT(r, shift(r, 4), a);
18595 SDValue MLo = DAG.getNode(ShiftOpcode, dl, ExtVT, RLo,
18596 DAG.getConstant(4, dl, ExtVT));
18597 SDValue MHi = DAG.getNode(ShiftOpcode, dl, ExtVT, RHi,
18598 DAG.getConstant(4, dl, ExtVT));
18599 RLo = SignBitSelect(ExtVT, ALo, MLo, RLo);
18600 RHi = SignBitSelect(ExtVT, AHi, MHi, RHi);
18603 ALo = DAG.getNode(ISD::ADD, dl, ExtVT, ALo, ALo);
18604 AHi = DAG.getNode(ISD::ADD, dl, ExtVT, AHi, AHi);
18606 // r = VSELECT(r, shift(r, 2), a);
18607 MLo = DAG.getNode(ShiftOpcode, dl, ExtVT, RLo,
18608 DAG.getConstant(2, dl, ExtVT));
18609 MHi = DAG.getNode(ShiftOpcode, dl, ExtVT, RHi,
18610 DAG.getConstant(2, dl, ExtVT));
18611 RLo = SignBitSelect(ExtVT, ALo, MLo, RLo);
18612 RHi = SignBitSelect(ExtVT, AHi, MHi, RHi);
18615 ALo = DAG.getNode(ISD::ADD, dl, ExtVT, ALo, ALo);
18616 AHi = DAG.getNode(ISD::ADD, dl, ExtVT, AHi, AHi);
18618 // r = VSELECT(r, shift(r, 1), a);
18619 MLo = DAG.getNode(ShiftOpcode, dl, ExtVT, RLo,
18620 DAG.getConstant(1, dl, ExtVT));
18621 MHi = DAG.getNode(ShiftOpcode, dl, ExtVT, RHi,
18622 DAG.getConstant(1, dl, ExtVT));
18623 RLo = SignBitSelect(ExtVT, ALo, MLo, RLo);
18624 RHi = SignBitSelect(ExtVT, AHi, MHi, RHi);
18626 // Logical shift the result back to the lower byte, leaving a zero upper
18628 // meaning that we can safely pack with PACKUSWB.
18630 DAG.getNode(ISD::SRL, dl, ExtVT, RLo, DAG.getConstant(8, dl, ExtVT));
18632 DAG.getNode(ISD::SRL, dl, ExtVT, RHi, DAG.getConstant(8, dl, ExtVT));
18633 return DAG.getNode(X86ISD::PACKUS, dl, VT, RLo, RHi);
18637 // It's worth extending once and using the v8i32 shifts for 16-bit types, but
18638 // the extra overheads to get from v16i8 to v8i32 make the existing SSE
18639 // solution better.
18640 if (Subtarget->hasInt256() && VT == MVT::v8i16) {
18641 MVT ExtVT = MVT::v8i32;
18643 Op.getOpcode() == ISD::SRA ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
18644 R = DAG.getNode(ExtOpc, dl, ExtVT, R);
18645 Amt = DAG.getNode(ISD::ANY_EXTEND, dl, ExtVT, Amt);
18646 return DAG.getNode(ISD::TRUNCATE, dl, VT,
18647 DAG.getNode(Op.getOpcode(), dl, ExtVT, R, Amt));
18650 if (Subtarget->hasInt256() && !Subtarget->hasXOP() && VT == MVT::v16i16) {
18651 MVT ExtVT = MVT::v8i32;
18652 SDValue Z = getZeroVector(VT, Subtarget, DAG, dl);
18653 SDValue ALo = DAG.getNode(X86ISD::UNPCKL, dl, VT, Amt, Z);
18654 SDValue AHi = DAG.getNode(X86ISD::UNPCKH, dl, VT, Amt, Z);
18655 SDValue RLo = DAG.getNode(X86ISD::UNPCKL, dl, VT, R, R);
18656 SDValue RHi = DAG.getNode(X86ISD::UNPCKH, dl, VT, R, R);
18657 ALo = DAG.getBitcast(ExtVT, ALo);
18658 AHi = DAG.getBitcast(ExtVT, AHi);
18659 RLo = DAG.getBitcast(ExtVT, RLo);
18660 RHi = DAG.getBitcast(ExtVT, RHi);
18661 SDValue Lo = DAG.getNode(Op.getOpcode(), dl, ExtVT, RLo, ALo);
18662 SDValue Hi = DAG.getNode(Op.getOpcode(), dl, ExtVT, RHi, AHi);
18663 Lo = DAG.getNode(ISD::SRL, dl, ExtVT, Lo, DAG.getConstant(16, dl, ExtVT));
18664 Hi = DAG.getNode(ISD::SRL, dl, ExtVT, Hi, DAG.getConstant(16, dl, ExtVT));
18665 return DAG.getNode(X86ISD::PACKUS, dl, VT, Lo, Hi);
18668 if (VT == MVT::v8i16) {
18669 unsigned ShiftOpcode = Op->getOpcode();
18671 auto SignBitSelect = [&](SDValue Sel, SDValue V0, SDValue V1) {
18672 // On SSE41 targets we make use of the fact that VSELECT lowers
18673 // to PBLENDVB which selects bytes based just on the sign bit.
18674 if (Subtarget->hasSSE41()) {
18675 MVT ExtVT = MVT::getVectorVT(MVT::i8, VT.getVectorNumElements() * 2);
18676 V0 = DAG.getBitcast(ExtVT, V0);
18677 V1 = DAG.getBitcast(ExtVT, V1);
18678 Sel = DAG.getBitcast(ExtVT, Sel);
18679 return DAG.getBitcast(
18680 VT, DAG.getNode(ISD::VSELECT, dl, ExtVT, Sel, V0, V1));
18682 // On pre-SSE41 targets we splat the sign bit - a negative value will
18683 // set all bits of the lanes to true and VSELECT uses that in
18684 // its OR(AND(V0,C),AND(V1,~C)) lowering.
18686 DAG.getNode(ISD::SRA, dl, VT, Sel, DAG.getConstant(15, dl, VT));
18687 return DAG.getNode(ISD::VSELECT, dl, VT, C, V0, V1);
18690 // Turn 'a' into a mask suitable for VSELECT: a = a << 12;
18691 if (Subtarget->hasSSE41()) {
18692 // On SSE41 targets we need to replicate the shift mask in both
18693 // bytes for PBLENDVB.
18696 DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(4, dl, VT)),
18697 DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(12, dl, VT)));
18699 Amt = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(12, dl, VT));
18702 // r = VSELECT(r, shift(r, 8), a);
18703 SDValue M = DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(8, dl, VT));
18704 R = SignBitSelect(Amt, M, R);
18707 Amt = DAG.getNode(ISD::ADD, dl, VT, Amt, Amt);
18709 // r = VSELECT(r, shift(r, 4), a);
18710 M = DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(4, dl, VT));
18711 R = SignBitSelect(Amt, M, R);
18714 Amt = DAG.getNode(ISD::ADD, dl, VT, Amt, Amt);
18716 // r = VSELECT(r, shift(r, 2), a);
18717 M = DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(2, dl, VT));
18718 R = SignBitSelect(Amt, M, R);
18721 Amt = DAG.getNode(ISD::ADD, dl, VT, Amt, Amt);
18723 // return VSELECT(r, shift(r, 1), a);
18724 M = DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(1, dl, VT));
18725 R = SignBitSelect(Amt, M, R);
18729 // Decompose 256-bit shifts into smaller 128-bit shifts.
18730 if (VT.is256BitVector()) {
18731 unsigned NumElems = VT.getVectorNumElements();
18732 MVT EltVT = VT.getVectorElementType();
18733 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
18735 // Extract the two vectors
18736 SDValue V1 = Extract128BitVector(R, 0, DAG, dl);
18737 SDValue V2 = Extract128BitVector(R, NumElems/2, DAG, dl);
18739 // Recreate the shift amount vectors
18740 SDValue Amt1, Amt2;
18741 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
18742 // Constant shift amount
18743 SmallVector<SDValue, 8> Ops(Amt->op_begin(), Amt->op_begin() + NumElems);
18744 ArrayRef<SDValue> Amt1Csts = makeArrayRef(Ops).slice(0, NumElems / 2);
18745 ArrayRef<SDValue> Amt2Csts = makeArrayRef(Ops).slice(NumElems / 2);
18747 Amt1 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt1Csts);
18748 Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt2Csts);
18750 // Variable shift amount
18751 Amt1 = Extract128BitVector(Amt, 0, DAG, dl);
18752 Amt2 = Extract128BitVector(Amt, NumElems/2, DAG, dl);
18755 // Issue new vector shifts for the smaller types
18756 V1 = DAG.getNode(Op.getOpcode(), dl, NewVT, V1, Amt1);
18757 V2 = DAG.getNode(Op.getOpcode(), dl, NewVT, V2, Amt2);
18759 // Concatenate the result back
18760 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, V1, V2);
18766 static SDValue LowerRotate(SDValue Op, const X86Subtarget *Subtarget,
18767 SelectionDAG &DAG) {
18768 MVT VT = Op.getSimpleValueType();
18770 SDValue R = Op.getOperand(0);
18771 SDValue Amt = Op.getOperand(1);
18773 assert(VT.isVector() && "Custom lowering only for vector rotates!");
18774 assert(Subtarget->hasXOP() && "XOP support required for vector rotates!");
18775 assert((Op.getOpcode() == ISD::ROTL) && "Only ROTL supported");
18777 // XOP has 128-bit vector variable + immediate rotates.
18778 // +ve/-ve Amt = rotate left/right.
18780 // Split 256-bit integers.
18781 if (VT.getSizeInBits() == 256)
18782 return Lower256IntArith(Op, DAG);
18784 assert(VT.getSizeInBits() == 128 && "Only rotate 128-bit vectors!");
18786 // Attempt to rotate by immediate.
18787 if (auto *BVAmt = dyn_cast<BuildVectorSDNode>(Amt)) {
18788 if (auto *RotateConst = BVAmt->getConstantSplatNode()) {
18789 uint64_t RotateAmt = RotateConst->getAPIntValue().getZExtValue();
18790 assert(RotateAmt < VT.getScalarSizeInBits() && "Rotation out of range");
18791 return DAG.getNode(X86ISD::VPROTI, DL, VT, R,
18792 DAG.getConstant(RotateAmt, DL, MVT::i8));
18796 // Use general rotate by variable (per-element).
18797 return DAG.getNode(X86ISD::VPROT, DL, VT, R, Amt);
18800 static SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) {
18801 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
18802 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
18803 // looks for this combo and may remove the "setcc" instruction if the "setcc"
18804 // has only one use.
18805 SDNode *N = Op.getNode();
18806 SDValue LHS = N->getOperand(0);
18807 SDValue RHS = N->getOperand(1);
18808 unsigned BaseOp = 0;
18811 switch (Op.getOpcode()) {
18812 default: llvm_unreachable("Unknown ovf instruction!");
18814 // A subtract of one will be selected as a INC. Note that INC doesn't
18815 // set CF, so we can't do this for UADDO.
18816 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
18818 BaseOp = X86ISD::INC;
18819 Cond = X86::COND_O;
18822 BaseOp = X86ISD::ADD;
18823 Cond = X86::COND_O;
18826 BaseOp = X86ISD::ADD;
18827 Cond = X86::COND_B;
18830 // A subtract of one will be selected as a DEC. Note that DEC doesn't
18831 // set CF, so we can't do this for USUBO.
18832 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
18834 BaseOp = X86ISD::DEC;
18835 Cond = X86::COND_O;
18838 BaseOp = X86ISD::SUB;
18839 Cond = X86::COND_O;
18842 BaseOp = X86ISD::SUB;
18843 Cond = X86::COND_B;
18846 BaseOp = N->getValueType(0) == MVT::i8 ? X86ISD::SMUL8 : X86ISD::SMUL;
18847 Cond = X86::COND_O;
18849 case ISD::UMULO: { // i64, i8 = umulo lhs, rhs --> i64, i64, i32 umul lhs,rhs
18850 if (N->getValueType(0) == MVT::i8) {
18851 BaseOp = X86ISD::UMUL8;
18852 Cond = X86::COND_O;
18855 SDVTList VTs = DAG.getVTList(N->getValueType(0), N->getValueType(0),
18857 SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS);
18860 DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
18861 DAG.getConstant(X86::COND_O, DL, MVT::i32),
18862 SDValue(Sum.getNode(), 2));
18864 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
18868 // Also sets EFLAGS.
18869 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
18870 SDValue Sum = DAG.getNode(BaseOp, DL, VTs, LHS, RHS);
18873 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1),
18874 DAG.getConstant(Cond, DL, MVT::i32),
18875 SDValue(Sum.getNode(), 1));
18877 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
18880 /// Returns true if the operand type is exactly twice the native width, and
18881 /// the corresponding cmpxchg8b or cmpxchg16b instruction is available.
18882 /// Used to know whether to use cmpxchg8/16b when expanding atomic operations
18883 /// (otherwise we leave them alone to become __sync_fetch_and_... calls).
18884 bool X86TargetLowering::needsCmpXchgNb(Type *MemType) const {
18885 unsigned OpWidth = MemType->getPrimitiveSizeInBits();
18888 return !Subtarget->is64Bit(); // FIXME this should be Subtarget.hasCmpxchg8b
18889 else if (OpWidth == 128)
18890 return Subtarget->hasCmpxchg16b();
18895 bool X86TargetLowering::shouldExpandAtomicStoreInIR(StoreInst *SI) const {
18896 return needsCmpXchgNb(SI->getValueOperand()->getType());
18899 // Note: this turns large loads into lock cmpxchg8b/16b.
18900 // FIXME: On 32 bits x86, fild/movq might be faster than lock cmpxchg8b.
18901 TargetLowering::AtomicExpansionKind
18902 X86TargetLowering::shouldExpandAtomicLoadInIR(LoadInst *LI) const {
18903 auto PTy = cast<PointerType>(LI->getPointerOperand()->getType());
18904 return needsCmpXchgNb(PTy->getElementType()) ? AtomicExpansionKind::CmpXChg
18905 : AtomicExpansionKind::None;
18908 TargetLowering::AtomicExpansionKind
18909 X86TargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const {
18910 unsigned NativeWidth = Subtarget->is64Bit() ? 64 : 32;
18911 Type *MemType = AI->getType();
18913 // If the operand is too big, we must see if cmpxchg8/16b is available
18914 // and default to library calls otherwise.
18915 if (MemType->getPrimitiveSizeInBits() > NativeWidth) {
18916 return needsCmpXchgNb(MemType) ? AtomicExpansionKind::CmpXChg
18917 : AtomicExpansionKind::None;
18920 AtomicRMWInst::BinOp Op = AI->getOperation();
18923 llvm_unreachable("Unknown atomic operation");
18924 case AtomicRMWInst::Xchg:
18925 case AtomicRMWInst::Add:
18926 case AtomicRMWInst::Sub:
18927 // It's better to use xadd, xsub or xchg for these in all cases.
18928 return AtomicExpansionKind::None;
18929 case AtomicRMWInst::Or:
18930 case AtomicRMWInst::And:
18931 case AtomicRMWInst::Xor:
18932 // If the atomicrmw's result isn't actually used, we can just add a "lock"
18933 // prefix to a normal instruction for these operations.
18934 return !AI->use_empty() ? AtomicExpansionKind::CmpXChg
18935 : AtomicExpansionKind::None;
18936 case AtomicRMWInst::Nand:
18937 case AtomicRMWInst::Max:
18938 case AtomicRMWInst::Min:
18939 case AtomicRMWInst::UMax:
18940 case AtomicRMWInst::UMin:
18941 // These always require a non-trivial set of data operations on x86. We must
18942 // use a cmpxchg loop.
18943 return AtomicExpansionKind::CmpXChg;
18947 static bool hasMFENCE(const X86Subtarget& Subtarget) {
18948 // Use mfence if we have SSE2 or we're on x86-64 (even if we asked for
18949 // no-sse2). There isn't any reason to disable it if the target processor
18951 return Subtarget.hasSSE2() || Subtarget.is64Bit();
18955 X86TargetLowering::lowerIdempotentRMWIntoFencedLoad(AtomicRMWInst *AI) const {
18956 unsigned NativeWidth = Subtarget->is64Bit() ? 64 : 32;
18957 Type *MemType = AI->getType();
18958 // Accesses larger than the native width are turned into cmpxchg/libcalls, so
18959 // there is no benefit in turning such RMWs into loads, and it is actually
18960 // harmful as it introduces a mfence.
18961 if (MemType->getPrimitiveSizeInBits() > NativeWidth)
18964 auto Builder = IRBuilder<>(AI);
18965 Module *M = Builder.GetInsertBlock()->getParent()->getParent();
18966 auto SynchScope = AI->getSynchScope();
18967 // We must restrict the ordering to avoid generating loads with Release or
18968 // ReleaseAcquire orderings.
18969 auto Order = AtomicCmpXchgInst::getStrongestFailureOrdering(AI->getOrdering());
18970 auto Ptr = AI->getPointerOperand();
18972 // Before the load we need a fence. Here is an example lifted from
18973 // http://www.hpl.hp.com/techreports/2012/HPL-2012-68.pdf showing why a fence
18976 // x.store(1, relaxed);
18977 // r1 = y.fetch_add(0, release);
18979 // y.fetch_add(42, acquire);
18980 // r2 = x.load(relaxed);
18981 // r1 = r2 = 0 is impossible, but becomes possible if the idempotent rmw is
18982 // lowered to just a load without a fence. A mfence flushes the store buffer,
18983 // making the optimization clearly correct.
18984 // FIXME: it is required if isAtLeastRelease(Order) but it is not clear
18985 // otherwise, we might be able to be more aggressive on relaxed idempotent
18986 // rmw. In practice, they do not look useful, so we don't try to be
18987 // especially clever.
18988 if (SynchScope == SingleThread)
18989 // FIXME: we could just insert an X86ISD::MEMBARRIER here, except we are at
18990 // the IR level, so we must wrap it in an intrinsic.
18993 if (!hasMFENCE(*Subtarget))
18994 // FIXME: it might make sense to use a locked operation here but on a
18995 // different cache-line to prevent cache-line bouncing. In practice it
18996 // is probably a small win, and x86 processors without mfence are rare
18997 // enough that we do not bother.
19001 llvm::Intrinsic::getDeclaration(M, Intrinsic::x86_sse2_mfence);
19002 Builder.CreateCall(MFence, {});
19004 // Finally we can emit the atomic load.
19005 LoadInst *Loaded = Builder.CreateAlignedLoad(Ptr,
19006 AI->getType()->getPrimitiveSizeInBits());
19007 Loaded->setAtomic(Order, SynchScope);
19008 AI->replaceAllUsesWith(Loaded);
19009 AI->eraseFromParent();
19013 static SDValue LowerATOMIC_FENCE(SDValue Op, const X86Subtarget *Subtarget,
19014 SelectionDAG &DAG) {
19016 AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>(
19017 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue());
19018 SynchronizationScope FenceScope = static_cast<SynchronizationScope>(
19019 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
19021 // The only fence that needs an instruction is a sequentially-consistent
19022 // cross-thread fence.
19023 if (FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread) {
19024 if (hasMFENCE(*Subtarget))
19025 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
19027 SDValue Chain = Op.getOperand(0);
19028 SDValue Zero = DAG.getConstant(0, dl, MVT::i32);
19030 DAG.getRegister(X86::ESP, MVT::i32), // Base
19031 DAG.getTargetConstant(1, dl, MVT::i8), // Scale
19032 DAG.getRegister(0, MVT::i32), // Index
19033 DAG.getTargetConstant(0, dl, MVT::i32), // Disp
19034 DAG.getRegister(0, MVT::i32), // Segment.
19038 SDNode *Res = DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops);
19039 return SDValue(Res, 0);
19042 // MEMBARRIER is a compiler barrier; it codegens to a no-op.
19043 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
19046 static SDValue LowerCMP_SWAP(SDValue Op, const X86Subtarget *Subtarget,
19047 SelectionDAG &DAG) {
19048 MVT T = Op.getSimpleValueType();
19052 switch(T.SimpleTy) {
19053 default: llvm_unreachable("Invalid value type!");
19054 case MVT::i8: Reg = X86::AL; size = 1; break;
19055 case MVT::i16: Reg = X86::AX; size = 2; break;
19056 case MVT::i32: Reg = X86::EAX; size = 4; break;
19058 assert(Subtarget->is64Bit() && "Node not type legal!");
19059 Reg = X86::RAX; size = 8;
19062 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg,
19063 Op.getOperand(2), SDValue());
19064 SDValue Ops[] = { cpIn.getValue(0),
19067 DAG.getTargetConstant(size, DL, MVT::i8),
19068 cpIn.getValue(1) };
19069 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
19070 MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand();
19071 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys,
19075 DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1));
19076 SDValue EFLAGS = DAG.getCopyFromReg(cpOut.getValue(1), DL, X86::EFLAGS,
19077 MVT::i32, cpOut.getValue(2));
19078 SDValue Success = DAG.getNode(X86ISD::SETCC, DL, Op->getValueType(1),
19079 DAG.getConstant(X86::COND_E, DL, MVT::i8),
19082 DAG.ReplaceAllUsesOfValueWith(Op.getValue(0), cpOut);
19083 DAG.ReplaceAllUsesOfValueWith(Op.getValue(1), Success);
19084 DAG.ReplaceAllUsesOfValueWith(Op.getValue(2), EFLAGS.getValue(1));
19088 static SDValue LowerBITCAST(SDValue Op, const X86Subtarget *Subtarget,
19089 SelectionDAG &DAG) {
19090 MVT SrcVT = Op.getOperand(0).getSimpleValueType();
19091 MVT DstVT = Op.getSimpleValueType();
19093 if (SrcVT == MVT::v2i32 || SrcVT == MVT::v4i16 || SrcVT == MVT::v8i8) {
19094 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
19095 if (DstVT != MVT::f64)
19096 // This conversion needs to be expanded.
19099 SDValue InVec = Op->getOperand(0);
19101 unsigned NumElts = SrcVT.getVectorNumElements();
19102 MVT SVT = SrcVT.getVectorElementType();
19104 // Widen the vector in input in the case of MVT::v2i32.
19105 // Example: from MVT::v2i32 to MVT::v4i32.
19106 SmallVector<SDValue, 16> Elts;
19107 for (unsigned i = 0, e = NumElts; i != e; ++i)
19108 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT, InVec,
19109 DAG.getIntPtrConstant(i, dl)));
19111 // Explicitly mark the extra elements as Undef.
19112 Elts.append(NumElts, DAG.getUNDEF(SVT));
19114 EVT NewVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
19115 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Elts);
19116 SDValue ToV2F64 = DAG.getBitcast(MVT::v2f64, BV);
19117 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, ToV2F64,
19118 DAG.getIntPtrConstant(0, dl));
19121 assert(Subtarget->is64Bit() && !Subtarget->hasSSE2() &&
19122 Subtarget->hasMMX() && "Unexpected custom BITCAST");
19123 assert((DstVT == MVT::i64 ||
19124 (DstVT.isVector() && DstVT.getSizeInBits()==64)) &&
19125 "Unexpected custom BITCAST");
19126 // i64 <=> MMX conversions are Legal.
19127 if (SrcVT==MVT::i64 && DstVT.isVector())
19129 if (DstVT==MVT::i64 && SrcVT.isVector())
19131 // MMX <=> MMX conversions are Legal.
19132 if (SrcVT.isVector() && DstVT.isVector())
19134 // All other conversions need to be expanded.
19138 /// Compute the horizontal sum of bytes in V for the elements of VT.
19140 /// Requires V to be a byte vector and VT to be an integer vector type with
19141 /// wider elements than V's type. The width of the elements of VT determines
19142 /// how many bytes of V are summed horizontally to produce each element of the
19144 static SDValue LowerHorizontalByteSum(SDValue V, MVT VT,
19145 const X86Subtarget *Subtarget,
19146 SelectionDAG &DAG) {
19148 MVT ByteVecVT = V.getSimpleValueType();
19149 MVT EltVT = VT.getVectorElementType();
19150 int NumElts = VT.getVectorNumElements();
19151 assert(ByteVecVT.getVectorElementType() == MVT::i8 &&
19152 "Expected value to have byte element type.");
19153 assert(EltVT != MVT::i8 &&
19154 "Horizontal byte sum only makes sense for wider elements!");
19155 unsigned VecSize = VT.getSizeInBits();
19156 assert(ByteVecVT.getSizeInBits() == VecSize && "Cannot change vector size!");
19158 // PSADBW instruction horizontally add all bytes and leave the result in i64
19159 // chunks, thus directly computes the pop count for v2i64 and v4i64.
19160 if (EltVT == MVT::i64) {
19161 SDValue Zeros = getZeroVector(ByteVecVT, Subtarget, DAG, DL);
19162 V = DAG.getNode(X86ISD::PSADBW, DL, ByteVecVT, V, Zeros);
19163 return DAG.getBitcast(VT, V);
19166 if (EltVT == MVT::i32) {
19167 // We unpack the low half and high half into i32s interleaved with zeros so
19168 // that we can use PSADBW to horizontally sum them. The most useful part of
19169 // this is that it lines up the results of two PSADBW instructions to be
19170 // two v2i64 vectors which concatenated are the 4 population counts. We can
19171 // then use PACKUSWB to shrink and concatenate them into a v4i32 again.
19172 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, DL);
19173 SDValue Low = DAG.getNode(X86ISD::UNPCKL, DL, VT, V, Zeros);
19174 SDValue High = DAG.getNode(X86ISD::UNPCKH, DL, VT, V, Zeros);
19176 // Do the horizontal sums into two v2i64s.
19177 Zeros = getZeroVector(ByteVecVT, Subtarget, DAG, DL);
19178 Low = DAG.getNode(X86ISD::PSADBW, DL, ByteVecVT,
19179 DAG.getBitcast(ByteVecVT, Low), Zeros);
19180 High = DAG.getNode(X86ISD::PSADBW, DL, ByteVecVT,
19181 DAG.getBitcast(ByteVecVT, High), Zeros);
19183 // Merge them together.
19184 MVT ShortVecVT = MVT::getVectorVT(MVT::i16, VecSize / 16);
19185 V = DAG.getNode(X86ISD::PACKUS, DL, ByteVecVT,
19186 DAG.getBitcast(ShortVecVT, Low),
19187 DAG.getBitcast(ShortVecVT, High));
19189 return DAG.getBitcast(VT, V);
19192 // The only element type left is i16.
19193 assert(EltVT == MVT::i16 && "Unknown how to handle type");
19195 // To obtain pop count for each i16 element starting from the pop count for
19196 // i8 elements, shift the i16s left by 8, sum as i8s, and then shift as i16s
19197 // right by 8. It is important to shift as i16s as i8 vector shift isn't
19198 // directly supported.
19199 SmallVector<SDValue, 16> Shifters(NumElts, DAG.getConstant(8, DL, EltVT));
19200 SDValue Shifter = DAG.getNode(ISD::BUILD_VECTOR, DL, VT, Shifters);
19201 SDValue Shl = DAG.getNode(ISD::SHL, DL, VT, DAG.getBitcast(VT, V), Shifter);
19202 V = DAG.getNode(ISD::ADD, DL, ByteVecVT, DAG.getBitcast(ByteVecVT, Shl),
19203 DAG.getBitcast(ByteVecVT, V));
19204 return DAG.getNode(ISD::SRL, DL, VT, DAG.getBitcast(VT, V), Shifter);
19207 static SDValue LowerVectorCTPOPInRegLUT(SDValue Op, SDLoc DL,
19208 const X86Subtarget *Subtarget,
19209 SelectionDAG &DAG) {
19210 MVT VT = Op.getSimpleValueType();
19211 MVT EltVT = VT.getVectorElementType();
19212 unsigned VecSize = VT.getSizeInBits();
19214 // Implement a lookup table in register by using an algorithm based on:
19215 // http://wm.ite.pl/articles/sse-popcount.html
19217 // The general idea is that every lower byte nibble in the input vector is an
19218 // index into a in-register pre-computed pop count table. We then split up the
19219 // input vector in two new ones: (1) a vector with only the shifted-right
19220 // higher nibbles for each byte and (2) a vector with the lower nibbles (and
19221 // masked out higher ones) for each byte. PSHUB is used separately with both
19222 // to index the in-register table. Next, both are added and the result is a
19223 // i8 vector where each element contains the pop count for input byte.
19225 // To obtain the pop count for elements != i8, we follow up with the same
19226 // approach and use additional tricks as described below.
19228 const int LUT[16] = {/* 0 */ 0, /* 1 */ 1, /* 2 */ 1, /* 3 */ 2,
19229 /* 4 */ 1, /* 5 */ 2, /* 6 */ 2, /* 7 */ 3,
19230 /* 8 */ 1, /* 9 */ 2, /* a */ 2, /* b */ 3,
19231 /* c */ 2, /* d */ 3, /* e */ 3, /* f */ 4};
19233 int NumByteElts = VecSize / 8;
19234 MVT ByteVecVT = MVT::getVectorVT(MVT::i8, NumByteElts);
19235 SDValue In = DAG.getBitcast(ByteVecVT, Op);
19236 SmallVector<SDValue, 16> LUTVec;
19237 for (int i = 0; i < NumByteElts; ++i)
19238 LUTVec.push_back(DAG.getConstant(LUT[i % 16], DL, MVT::i8));
19239 SDValue InRegLUT = DAG.getNode(ISD::BUILD_VECTOR, DL, ByteVecVT, LUTVec);
19240 SmallVector<SDValue, 16> Mask0F(NumByteElts,
19241 DAG.getConstant(0x0F, DL, MVT::i8));
19242 SDValue M0F = DAG.getNode(ISD::BUILD_VECTOR, DL, ByteVecVT, Mask0F);
19245 SmallVector<SDValue, 16> Four(NumByteElts, DAG.getConstant(4, DL, MVT::i8));
19246 SDValue FourV = DAG.getNode(ISD::BUILD_VECTOR, DL, ByteVecVT, Four);
19247 SDValue HighNibbles = DAG.getNode(ISD::SRL, DL, ByteVecVT, In, FourV);
19250 SDValue LowNibbles = DAG.getNode(ISD::AND, DL, ByteVecVT, In, M0F);
19252 // The input vector is used as the shuffle mask that index elements into the
19253 // LUT. After counting low and high nibbles, add the vector to obtain the
19254 // final pop count per i8 element.
19255 SDValue HighPopCnt =
19256 DAG.getNode(X86ISD::PSHUFB, DL, ByteVecVT, InRegLUT, HighNibbles);
19257 SDValue LowPopCnt =
19258 DAG.getNode(X86ISD::PSHUFB, DL, ByteVecVT, InRegLUT, LowNibbles);
19259 SDValue PopCnt = DAG.getNode(ISD::ADD, DL, ByteVecVT, HighPopCnt, LowPopCnt);
19261 if (EltVT == MVT::i8)
19264 return LowerHorizontalByteSum(PopCnt, VT, Subtarget, DAG);
19267 static SDValue LowerVectorCTPOPBitmath(SDValue Op, SDLoc DL,
19268 const X86Subtarget *Subtarget,
19269 SelectionDAG &DAG) {
19270 MVT VT = Op.getSimpleValueType();
19271 assert(VT.is128BitVector() &&
19272 "Only 128-bit vector bitmath lowering supported.");
19274 int VecSize = VT.getSizeInBits();
19275 MVT EltVT = VT.getVectorElementType();
19276 int Len = EltVT.getSizeInBits();
19278 // This is the vectorized version of the "best" algorithm from
19279 // http://graphics.stanford.edu/~seander/bithacks.html#CountBitsSetParallel
19280 // with a minor tweak to use a series of adds + shifts instead of vector
19281 // multiplications. Implemented for all integer vector types. We only use
19282 // this when we don't have SSSE3 which allows a LUT-based lowering that is
19283 // much faster, even faster than using native popcnt instructions.
19285 auto GetShift = [&](unsigned OpCode, SDValue V, int Shifter) {
19286 MVT VT = V.getSimpleValueType();
19287 SmallVector<SDValue, 32> Shifters(
19288 VT.getVectorNumElements(),
19289 DAG.getConstant(Shifter, DL, VT.getVectorElementType()));
19290 return DAG.getNode(OpCode, DL, VT, V,
19291 DAG.getNode(ISD::BUILD_VECTOR, DL, VT, Shifters));
19293 auto GetMask = [&](SDValue V, APInt Mask) {
19294 MVT VT = V.getSimpleValueType();
19295 SmallVector<SDValue, 32> Masks(
19296 VT.getVectorNumElements(),
19297 DAG.getConstant(Mask, DL, VT.getVectorElementType()));
19298 return DAG.getNode(ISD::AND, DL, VT, V,
19299 DAG.getNode(ISD::BUILD_VECTOR, DL, VT, Masks));
19302 // We don't want to incur the implicit masks required to SRL vNi8 vectors on
19303 // x86, so set the SRL type to have elements at least i16 wide. This is
19304 // correct because all of our SRLs are followed immediately by a mask anyways
19305 // that handles any bits that sneak into the high bits of the byte elements.
19306 MVT SrlVT = Len > 8 ? VT : MVT::getVectorVT(MVT::i16, VecSize / 16);
19310 // v = v - ((v >> 1) & 0x55555555...)
19312 DAG.getBitcast(VT, GetShift(ISD::SRL, DAG.getBitcast(SrlVT, V), 1));
19313 SDValue And = GetMask(Srl, APInt::getSplat(Len, APInt(8, 0x55)));
19314 V = DAG.getNode(ISD::SUB, DL, VT, V, And);
19316 // v = (v & 0x33333333...) + ((v >> 2) & 0x33333333...)
19317 SDValue AndLHS = GetMask(V, APInt::getSplat(Len, APInt(8, 0x33)));
19318 Srl = DAG.getBitcast(VT, GetShift(ISD::SRL, DAG.getBitcast(SrlVT, V), 2));
19319 SDValue AndRHS = GetMask(Srl, APInt::getSplat(Len, APInt(8, 0x33)));
19320 V = DAG.getNode(ISD::ADD, DL, VT, AndLHS, AndRHS);
19322 // v = (v + (v >> 4)) & 0x0F0F0F0F...
19323 Srl = DAG.getBitcast(VT, GetShift(ISD::SRL, DAG.getBitcast(SrlVT, V), 4));
19324 SDValue Add = DAG.getNode(ISD::ADD, DL, VT, V, Srl);
19325 V = GetMask(Add, APInt::getSplat(Len, APInt(8, 0x0F)));
19327 // At this point, V contains the byte-wise population count, and we are
19328 // merely doing a horizontal sum if necessary to get the wider element
19330 if (EltVT == MVT::i8)
19333 return LowerHorizontalByteSum(
19334 DAG.getBitcast(MVT::getVectorVT(MVT::i8, VecSize / 8), V), VT, Subtarget,
19338 static SDValue LowerVectorCTPOP(SDValue Op, const X86Subtarget *Subtarget,
19339 SelectionDAG &DAG) {
19340 MVT VT = Op.getSimpleValueType();
19341 // FIXME: Need to add AVX-512 support here!
19342 assert((VT.is256BitVector() || VT.is128BitVector()) &&
19343 "Unknown CTPOP type to handle");
19344 SDLoc DL(Op.getNode());
19345 SDValue Op0 = Op.getOperand(0);
19347 if (!Subtarget->hasSSSE3()) {
19348 // We can't use the fast LUT approach, so fall back on vectorized bitmath.
19349 assert(VT.is128BitVector() && "Only 128-bit vectors supported in SSE!");
19350 return LowerVectorCTPOPBitmath(Op0, DL, Subtarget, DAG);
19353 if (VT.is256BitVector() && !Subtarget->hasInt256()) {
19354 unsigned NumElems = VT.getVectorNumElements();
19356 // Extract each 128-bit vector, compute pop count and concat the result.
19357 SDValue LHS = Extract128BitVector(Op0, 0, DAG, DL);
19358 SDValue RHS = Extract128BitVector(Op0, NumElems/2, DAG, DL);
19360 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT,
19361 LowerVectorCTPOPInRegLUT(LHS, DL, Subtarget, DAG),
19362 LowerVectorCTPOPInRegLUT(RHS, DL, Subtarget, DAG));
19365 return LowerVectorCTPOPInRegLUT(Op0, DL, Subtarget, DAG);
19368 static SDValue LowerCTPOP(SDValue Op, const X86Subtarget *Subtarget,
19369 SelectionDAG &DAG) {
19370 assert(Op.getValueType().isVector() &&
19371 "We only do custom lowering for vector population count.");
19372 return LowerVectorCTPOP(Op, Subtarget, DAG);
19375 static SDValue LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) {
19376 SDNode *Node = Op.getNode();
19378 EVT T = Node->getValueType(0);
19379 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
19380 DAG.getConstant(0, dl, T), Node->getOperand(2));
19381 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
19382 cast<AtomicSDNode>(Node)->getMemoryVT(),
19383 Node->getOperand(0),
19384 Node->getOperand(1), negOp,
19385 cast<AtomicSDNode>(Node)->getMemOperand(),
19386 cast<AtomicSDNode>(Node)->getOrdering(),
19387 cast<AtomicSDNode>(Node)->getSynchScope());
19390 static SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) {
19391 SDNode *Node = Op.getNode();
19393 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
19395 // Convert seq_cst store -> xchg
19396 // Convert wide store -> swap (-> cmpxchg8b/cmpxchg16b)
19397 // FIXME: On 32-bit, store -> fist or movq would be more efficient
19398 // (The only way to get a 16-byte store is cmpxchg16b)
19399 // FIXME: 16-byte ATOMIC_SWAP isn't actually hooked up at the moment.
19400 if (cast<AtomicSDNode>(Node)->getOrdering() == SequentiallyConsistent ||
19401 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
19402 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
19403 cast<AtomicSDNode>(Node)->getMemoryVT(),
19404 Node->getOperand(0),
19405 Node->getOperand(1), Node->getOperand(2),
19406 cast<AtomicSDNode>(Node)->getMemOperand(),
19407 cast<AtomicSDNode>(Node)->getOrdering(),
19408 cast<AtomicSDNode>(Node)->getSynchScope());
19409 return Swap.getValue(1);
19411 // Other atomic stores have a simple pattern.
19415 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
19416 EVT VT = Op.getNode()->getSimpleValueType(0);
19418 // Let legalize expand this if it isn't a legal type yet.
19419 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
19422 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
19425 bool ExtraOp = false;
19426 switch (Op.getOpcode()) {
19427 default: llvm_unreachable("Invalid code");
19428 case ISD::ADDC: Opc = X86ISD::ADD; break;
19429 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break;
19430 case ISD::SUBC: Opc = X86ISD::SUB; break;
19431 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break;
19435 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
19437 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
19438 Op.getOperand(1), Op.getOperand(2));
19441 static SDValue LowerFSINCOS(SDValue Op, const X86Subtarget *Subtarget,
19442 SelectionDAG &DAG) {
19443 assert(Subtarget->isTargetDarwin() && Subtarget->is64Bit());
19445 // For MacOSX, we want to call an alternative entry point: __sincos_stret,
19446 // which returns the values as { float, float } (in XMM0) or
19447 // { double, double } (which is returned in XMM0, XMM1).
19449 SDValue Arg = Op.getOperand(0);
19450 EVT ArgVT = Arg.getValueType();
19451 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
19453 TargetLowering::ArgListTy Args;
19454 TargetLowering::ArgListEntry Entry;
19458 Entry.isSExt = false;
19459 Entry.isZExt = false;
19460 Args.push_back(Entry);
19462 bool isF64 = ArgVT == MVT::f64;
19463 // Only optimize x86_64 for now. i386 is a bit messy. For f32,
19464 // the small struct {f32, f32} is returned in (eax, edx). For f64,
19465 // the results are returned via SRet in memory.
19466 const char *LibcallName = isF64 ? "__sincos_stret" : "__sincosf_stret";
19467 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
19469 DAG.getExternalSymbol(LibcallName, TLI.getPointerTy(DAG.getDataLayout()));
19471 Type *RetTy = isF64
19472 ? (Type*)StructType::get(ArgTy, ArgTy, nullptr)
19473 : (Type*)VectorType::get(ArgTy, 4);
19475 TargetLowering::CallLoweringInfo CLI(DAG);
19476 CLI.setDebugLoc(dl).setChain(DAG.getEntryNode())
19477 .setCallee(CallingConv::C, RetTy, Callee, std::move(Args), 0);
19479 std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI);
19482 // Returned in xmm0 and xmm1.
19483 return CallResult.first;
19485 // Returned in bits 0:31 and 32:64 xmm0.
19486 SDValue SinVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
19487 CallResult.first, DAG.getIntPtrConstant(0, dl));
19488 SDValue CosVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
19489 CallResult.first, DAG.getIntPtrConstant(1, dl));
19490 SDVTList Tys = DAG.getVTList(ArgVT, ArgVT);
19491 return DAG.getNode(ISD::MERGE_VALUES, dl, Tys, SinVal, CosVal);
19494 static SDValue LowerMSCATTER(SDValue Op, const X86Subtarget *Subtarget,
19495 SelectionDAG &DAG) {
19496 assert(Subtarget->hasAVX512() &&
19497 "MGATHER/MSCATTER are supported on AVX-512 arch only");
19499 MaskedScatterSDNode *N = cast<MaskedScatterSDNode>(Op.getNode());
19500 EVT VT = N->getValue().getValueType();
19501 assert(VT.getScalarSizeInBits() >= 32 && "Unsupported scatter op");
19504 // X86 scatter kills mask register, so its type should be added to
19505 // the list of return values
19506 if (N->getNumValues() == 1) {
19507 SDValue Index = N->getIndex();
19508 if (!Subtarget->hasVLX() && !VT.is512BitVector() &&
19509 !Index.getValueType().is512BitVector())
19510 Index = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i64, Index);
19512 SDVTList VTs = DAG.getVTList(N->getMask().getValueType(), MVT::Other);
19513 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), N->getOperand(2),
19514 N->getOperand(3), Index };
19516 SDValue NewScatter = DAG.getMaskedScatter(VTs, VT, dl, Ops, N->getMemOperand());
19517 DAG.ReplaceAllUsesWith(Op, SDValue(NewScatter.getNode(), 1));
19518 return SDValue(NewScatter.getNode(), 0);
19523 static SDValue LowerMGATHER(SDValue Op, const X86Subtarget *Subtarget,
19524 SelectionDAG &DAG) {
19525 assert(Subtarget->hasAVX512() &&
19526 "MGATHER/MSCATTER are supported on AVX-512 arch only");
19528 MaskedGatherSDNode *N = cast<MaskedGatherSDNode>(Op.getNode());
19529 EVT VT = Op.getValueType();
19530 assert(VT.getScalarSizeInBits() >= 32 && "Unsupported gather op");
19533 SDValue Index = N->getIndex();
19534 if (!Subtarget->hasVLX() && !VT.is512BitVector() &&
19535 !Index.getValueType().is512BitVector()) {
19536 Index = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i64, Index);
19537 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), N->getOperand(2),
19538 N->getOperand(3), Index };
19539 DAG.UpdateNodeOperands(N, Ops);
19544 SDValue X86TargetLowering::LowerGC_TRANSITION_START(SDValue Op,
19545 SelectionDAG &DAG) const {
19546 // TODO: Eventually, the lowering of these nodes should be informed by or
19547 // deferred to the GC strategy for the function in which they appear. For
19548 // now, however, they must be lowered to something. Since they are logically
19549 // no-ops in the case of a null GC strategy (or a GC strategy which does not
19550 // require special handling for these nodes), lower them as literal NOOPs for
19552 SmallVector<SDValue, 2> Ops;
19554 Ops.push_back(Op.getOperand(0));
19555 if (Op->getGluedNode())
19556 Ops.push_back(Op->getOperand(Op->getNumOperands() - 1));
19559 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
19560 SDValue NOOP(DAG.getMachineNode(X86::NOOP, SDLoc(Op), VTs, Ops), 0);
19565 SDValue X86TargetLowering::LowerGC_TRANSITION_END(SDValue Op,
19566 SelectionDAG &DAG) const {
19567 // TODO: Eventually, the lowering of these nodes should be informed by or
19568 // deferred to the GC strategy for the function in which they appear. For
19569 // now, however, they must be lowered to something. Since they are logically
19570 // no-ops in the case of a null GC strategy (or a GC strategy which does not
19571 // require special handling for these nodes), lower them as literal NOOPs for
19573 SmallVector<SDValue, 2> Ops;
19575 Ops.push_back(Op.getOperand(0));
19576 if (Op->getGluedNode())
19577 Ops.push_back(Op->getOperand(Op->getNumOperands() - 1));
19580 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
19581 SDValue NOOP(DAG.getMachineNode(X86::NOOP, SDLoc(Op), VTs, Ops), 0);
19586 /// LowerOperation - Provide custom lowering hooks for some operations.
19588 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
19589 switch (Op.getOpcode()) {
19590 default: llvm_unreachable("Should not custom lower this!");
19591 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, Subtarget, DAG);
19592 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS:
19593 return LowerCMP_SWAP(Op, Subtarget, DAG);
19594 case ISD::CTPOP: return LowerCTPOP(Op, Subtarget, DAG);
19595 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
19596 case ISD::ATOMIC_STORE: return LowerATOMIC_STORE(Op,DAG);
19597 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
19598 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, Subtarget, DAG);
19599 case ISD::VECTOR_SHUFFLE: return lowerVectorShuffle(Op, Subtarget, DAG);
19600 case ISD::VSELECT: return LowerVSELECT(Op, DAG);
19601 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
19602 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
19603 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op,Subtarget,DAG);
19604 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, Subtarget,DAG);
19605 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
19606 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
19607 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
19608 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
19609 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
19610 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
19611 case ISD::SHL_PARTS:
19612 case ISD::SRA_PARTS:
19613 case ISD::SRL_PARTS: return LowerShiftParts(Op, DAG);
19614 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
19615 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
19616 case ISD::TRUNCATE: return LowerTRUNCATE(Op, DAG);
19617 case ISD::ZERO_EXTEND: return LowerZERO_EXTEND(Op, Subtarget, DAG);
19618 case ISD::SIGN_EXTEND: return LowerSIGN_EXTEND(Op, Subtarget, DAG);
19619 case ISD::ANY_EXTEND: return LowerANY_EXTEND(Op, Subtarget, DAG);
19620 case ISD::SIGN_EXTEND_VECTOR_INREG:
19621 return LowerSIGN_EXTEND_VECTOR_INREG(Op, Subtarget, DAG);
19622 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
19623 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
19624 case ISD::FP_EXTEND: return LowerFP_EXTEND(Op, DAG);
19625 case ISD::LOAD: return LowerExtendedLoad(Op, Subtarget, DAG);
19627 case ISD::FNEG: return LowerFABSorFNEG(Op, DAG);
19628 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
19629 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG);
19630 case ISD::SETCC: return LowerSETCC(Op, DAG);
19631 case ISD::SELECT: return LowerSELECT(Op, DAG);
19632 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
19633 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
19634 case ISD::VASTART: return LowerVASTART(Op, DAG);
19635 case ISD::VAARG: return LowerVAARG(Op, DAG);
19636 case ISD::VACOPY: return LowerVACOPY(Op, Subtarget, DAG);
19637 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, Subtarget, DAG);
19638 case ISD::INTRINSIC_VOID:
19639 case ISD::INTRINSIC_W_CHAIN: return LowerINTRINSIC_W_CHAIN(Op, Subtarget, DAG);
19640 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
19641 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
19642 case ISD::FRAME_TO_ARGS_OFFSET:
19643 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
19644 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
19645 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
19646 case ISD::EH_SJLJ_SETJMP: return lowerEH_SJLJ_SETJMP(Op, DAG);
19647 case ISD::EH_SJLJ_LONGJMP: return lowerEH_SJLJ_LONGJMP(Op, DAG);
19648 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
19649 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
19650 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
19651 case ISD::CTLZ: return LowerCTLZ(Op, Subtarget, DAG);
19652 case ISD::CTLZ_ZERO_UNDEF: return LowerCTLZ_ZERO_UNDEF(Op, Subtarget, DAG);
19654 case ISD::CTTZ_ZERO_UNDEF: return LowerCTTZ(Op, DAG);
19655 case ISD::MUL: return LowerMUL(Op, Subtarget, DAG);
19656 case ISD::UMUL_LOHI:
19657 case ISD::SMUL_LOHI: return LowerMUL_LOHI(Op, Subtarget, DAG);
19658 case ISD::ROTL: return LowerRotate(Op, Subtarget, DAG);
19661 case ISD::SHL: return LowerShift(Op, Subtarget, DAG);
19667 case ISD::UMULO: return LowerXALUO(Op, DAG);
19668 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, Subtarget,DAG);
19669 case ISD::BITCAST: return LowerBITCAST(Op, Subtarget, DAG);
19673 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
19674 case ISD::ADD: return LowerADD(Op, DAG);
19675 case ISD::SUB: return LowerSUB(Op, DAG);
19679 case ISD::UMIN: return LowerMINMAX(Op, DAG);
19680 case ISD::FSINCOS: return LowerFSINCOS(Op, Subtarget, DAG);
19681 case ISD::MGATHER: return LowerMGATHER(Op, Subtarget, DAG);
19682 case ISD::MSCATTER: return LowerMSCATTER(Op, Subtarget, DAG);
19683 case ISD::GC_TRANSITION_START:
19684 return LowerGC_TRANSITION_START(Op, DAG);
19685 case ISD::GC_TRANSITION_END: return LowerGC_TRANSITION_END(Op, DAG);
19689 /// ReplaceNodeResults - Replace a node with an illegal result type
19690 /// with a new node built out of custom code.
19691 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
19692 SmallVectorImpl<SDValue>&Results,
19693 SelectionDAG &DAG) const {
19695 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
19696 switch (N->getOpcode()) {
19698 llvm_unreachable("Do not know how to custom type legalize this operation!");
19699 // We might have generated v2f32 FMIN/FMAX operations. Widen them to v4f32.
19700 case X86ISD::FMINC:
19702 case X86ISD::FMAXC:
19703 case X86ISD::FMAX: {
19704 EVT VT = N->getValueType(0);
19705 if (VT != MVT::v2f32)
19706 llvm_unreachable("Unexpected type (!= v2f32) on FMIN/FMAX.");
19707 SDValue UNDEF = DAG.getUNDEF(VT);
19708 SDValue LHS = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v4f32,
19709 N->getOperand(0), UNDEF);
19710 SDValue RHS = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v4f32,
19711 N->getOperand(1), UNDEF);
19712 Results.push_back(DAG.getNode(N->getOpcode(), dl, MVT::v4f32, LHS, RHS));
19715 case ISD::SIGN_EXTEND_INREG:
19720 // We don't want to expand or promote these.
19727 case ISD::UDIVREM: {
19728 SDValue V = LowerWin64_i128OP(SDValue(N,0), DAG);
19729 Results.push_back(V);
19732 case ISD::FP_TO_SINT:
19733 case ISD::FP_TO_UINT: {
19734 bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT;
19736 std::pair<SDValue,SDValue> Vals =
19737 FP_TO_INTHelper(SDValue(N, 0), DAG, IsSigned, /*IsReplace=*/ true);
19738 SDValue FIST = Vals.first, StackSlot = Vals.second;
19739 if (FIST.getNode()) {
19740 EVT VT = N->getValueType(0);
19741 // Return a load from the stack slot.
19742 if (StackSlot.getNode())
19743 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot,
19744 MachinePointerInfo(),
19745 false, false, false, 0));
19747 Results.push_back(FIST);
19751 case ISD::UINT_TO_FP: {
19752 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
19753 if (N->getOperand(0).getValueType() != MVT::v2i32 ||
19754 N->getValueType(0) != MVT::v2f32)
19756 SDValue ZExtIn = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v2i64,
19758 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL), dl,
19760 SDValue VBias = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2f64, Bias, Bias);
19761 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64, ZExtIn,
19762 DAG.getBitcast(MVT::v2i64, VBias));
19763 Or = DAG.getBitcast(MVT::v2f64, Or);
19764 // TODO: Are there any fast-math-flags to propagate here?
19765 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, Or, VBias);
19766 Results.push_back(DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, Sub));
19769 case ISD::FP_ROUND: {
19770 if (!TLI.isTypeLegal(N->getOperand(0).getValueType()))
19772 SDValue V = DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, N->getOperand(0));
19773 Results.push_back(V);
19776 case ISD::FP_EXTEND: {
19777 // Right now, only MVT::v2f32 has OperationAction for FP_EXTEND.
19778 // No other ValueType for FP_EXTEND should reach this point.
19779 assert(N->getValueType(0) == MVT::v2f32 &&
19780 "Do not know how to legalize this Node");
19783 case ISD::INTRINSIC_W_CHAIN: {
19784 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
19786 default : llvm_unreachable("Do not know how to custom type "
19787 "legalize this intrinsic operation!");
19788 case Intrinsic::x86_rdtsc:
19789 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
19791 case Intrinsic::x86_rdtscp:
19792 return getReadTimeStampCounter(N, dl, X86ISD::RDTSCP_DAG, DAG, Subtarget,
19794 case Intrinsic::x86_rdpmc:
19795 return getReadPerformanceCounter(N, dl, DAG, Subtarget, Results);
19798 case ISD::READCYCLECOUNTER: {
19799 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
19802 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS: {
19803 EVT T = N->getValueType(0);
19804 assert((T == MVT::i64 || T == MVT::i128) && "can only expand cmpxchg pair");
19805 bool Regs64bit = T == MVT::i128;
19806 EVT HalfT = Regs64bit ? MVT::i64 : MVT::i32;
19807 SDValue cpInL, cpInH;
19808 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
19809 DAG.getConstant(0, dl, HalfT));
19810 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
19811 DAG.getConstant(1, dl, HalfT));
19812 cpInL = DAG.getCopyToReg(N->getOperand(0), dl,
19813 Regs64bit ? X86::RAX : X86::EAX,
19815 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl,
19816 Regs64bit ? X86::RDX : X86::EDX,
19817 cpInH, cpInL.getValue(1));
19818 SDValue swapInL, swapInH;
19819 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
19820 DAG.getConstant(0, dl, HalfT));
19821 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
19822 DAG.getConstant(1, dl, HalfT));
19823 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl,
19824 Regs64bit ? X86::RBX : X86::EBX,
19825 swapInL, cpInH.getValue(1));
19826 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl,
19827 Regs64bit ? X86::RCX : X86::ECX,
19828 swapInH, swapInL.getValue(1));
19829 SDValue Ops[] = { swapInH.getValue(0),
19831 swapInH.getValue(1) };
19832 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
19833 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand();
19834 unsigned Opcode = Regs64bit ? X86ISD::LCMPXCHG16_DAG :
19835 X86ISD::LCMPXCHG8_DAG;
19836 SDValue Result = DAG.getMemIntrinsicNode(Opcode, dl, Tys, Ops, T, MMO);
19837 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl,
19838 Regs64bit ? X86::RAX : X86::EAX,
19839 HalfT, Result.getValue(1));
19840 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl,
19841 Regs64bit ? X86::RDX : X86::EDX,
19842 HalfT, cpOutL.getValue(2));
19843 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
19845 SDValue EFLAGS = DAG.getCopyFromReg(cpOutH.getValue(1), dl, X86::EFLAGS,
19846 MVT::i32, cpOutH.getValue(2));
19848 DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
19849 DAG.getConstant(X86::COND_E, dl, MVT::i8), EFLAGS);
19850 Success = DAG.getZExtOrTrunc(Success, dl, N->getValueType(1));
19852 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, T, OpsF));
19853 Results.push_back(Success);
19854 Results.push_back(EFLAGS.getValue(1));
19857 case ISD::ATOMIC_SWAP:
19858 case ISD::ATOMIC_LOAD_ADD:
19859 case ISD::ATOMIC_LOAD_SUB:
19860 case ISD::ATOMIC_LOAD_AND:
19861 case ISD::ATOMIC_LOAD_OR:
19862 case ISD::ATOMIC_LOAD_XOR:
19863 case ISD::ATOMIC_LOAD_NAND:
19864 case ISD::ATOMIC_LOAD_MIN:
19865 case ISD::ATOMIC_LOAD_MAX:
19866 case ISD::ATOMIC_LOAD_UMIN:
19867 case ISD::ATOMIC_LOAD_UMAX:
19868 case ISD::ATOMIC_LOAD: {
19869 // Delegate to generic TypeLegalization. Situations we can really handle
19870 // should have already been dealt with by AtomicExpandPass.cpp.
19873 case ISD::BITCAST: {
19874 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
19875 EVT DstVT = N->getValueType(0);
19876 EVT SrcVT = N->getOperand(0)->getValueType(0);
19878 if (SrcVT != MVT::f64 ||
19879 (DstVT != MVT::v2i32 && DstVT != MVT::v4i16 && DstVT != MVT::v8i8))
19882 unsigned NumElts = DstVT.getVectorNumElements();
19883 EVT SVT = DstVT.getVectorElementType();
19884 EVT WiderVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
19885 SDValue Expanded = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
19886 MVT::v2f64, N->getOperand(0));
19887 SDValue ToVecInt = DAG.getBitcast(WiderVT, Expanded);
19889 if (ExperimentalVectorWideningLegalization) {
19890 // If we are legalizing vectors by widening, we already have the desired
19891 // legal vector type, just return it.
19892 Results.push_back(ToVecInt);
19896 SmallVector<SDValue, 8> Elts;
19897 for (unsigned i = 0, e = NumElts; i != e; ++i)
19898 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT,
19899 ToVecInt, DAG.getIntPtrConstant(i, dl)));
19901 Results.push_back(DAG.getNode(ISD::BUILD_VECTOR, dl, DstVT, Elts));
19906 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
19907 switch ((X86ISD::NodeType)Opcode) {
19908 case X86ISD::FIRST_NUMBER: break;
19909 case X86ISD::BSF: return "X86ISD::BSF";
19910 case X86ISD::BSR: return "X86ISD::BSR";
19911 case X86ISD::SHLD: return "X86ISD::SHLD";
19912 case X86ISD::SHRD: return "X86ISD::SHRD";
19913 case X86ISD::FAND: return "X86ISD::FAND";
19914 case X86ISD::FANDN: return "X86ISD::FANDN";
19915 case X86ISD::FOR: return "X86ISD::FOR";
19916 case X86ISD::FXOR: return "X86ISD::FXOR";
19917 case X86ISD::FILD: return "X86ISD::FILD";
19918 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
19919 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
19920 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
19921 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
19922 case X86ISD::FLD: return "X86ISD::FLD";
19923 case X86ISD::FST: return "X86ISD::FST";
19924 case X86ISD::CALL: return "X86ISD::CALL";
19925 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
19926 case X86ISD::RDTSCP_DAG: return "X86ISD::RDTSCP_DAG";
19927 case X86ISD::RDPMC_DAG: return "X86ISD::RDPMC_DAG";
19928 case X86ISD::BT: return "X86ISD::BT";
19929 case X86ISD::CMP: return "X86ISD::CMP";
19930 case X86ISD::COMI: return "X86ISD::COMI";
19931 case X86ISD::UCOMI: return "X86ISD::UCOMI";
19932 case X86ISD::CMPM: return "X86ISD::CMPM";
19933 case X86ISD::CMPMU: return "X86ISD::CMPMU";
19934 case X86ISD::CMPM_RND: return "X86ISD::CMPM_RND";
19935 case X86ISD::SETCC: return "X86ISD::SETCC";
19936 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY";
19937 case X86ISD::FSETCC: return "X86ISD::FSETCC";
19938 case X86ISD::FGETSIGNx86: return "X86ISD::FGETSIGNx86";
19939 case X86ISD::CMOV: return "X86ISD::CMOV";
19940 case X86ISD::BRCOND: return "X86ISD::BRCOND";
19941 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
19942 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
19943 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
19944 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
19945 case X86ISD::Wrapper: return "X86ISD::Wrapper";
19946 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
19947 case X86ISD::MOVDQ2Q: return "X86ISD::MOVDQ2Q";
19948 case X86ISD::MMX_MOVD2W: return "X86ISD::MMX_MOVD2W";
19949 case X86ISD::MMX_MOVW2D: return "X86ISD::MMX_MOVW2D";
19950 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
19951 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
19952 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
19953 case X86ISD::PINSRB: return "X86ISD::PINSRB";
19954 case X86ISD::PINSRW: return "X86ISD::PINSRW";
19955 case X86ISD::MMX_PINSRW: return "X86ISD::MMX_PINSRW";
19956 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
19957 case X86ISD::ANDNP: return "X86ISD::ANDNP";
19958 case X86ISD::PSIGN: return "X86ISD::PSIGN";
19959 case X86ISD::BLENDI: return "X86ISD::BLENDI";
19960 case X86ISD::SHRUNKBLEND: return "X86ISD::SHRUNKBLEND";
19961 case X86ISD::ADDUS: return "X86ISD::ADDUS";
19962 case X86ISD::SUBUS: return "X86ISD::SUBUS";
19963 case X86ISD::HADD: return "X86ISD::HADD";
19964 case X86ISD::HSUB: return "X86ISD::HSUB";
19965 case X86ISD::FHADD: return "X86ISD::FHADD";
19966 case X86ISD::FHSUB: return "X86ISD::FHSUB";
19967 case X86ISD::ABS: return "X86ISD::ABS";
19968 case X86ISD::CONFLICT: return "X86ISD::CONFLICT";
19969 case X86ISD::FMAX: return "X86ISD::FMAX";
19970 case X86ISD::FMAX_RND: return "X86ISD::FMAX_RND";
19971 case X86ISD::FMIN: return "X86ISD::FMIN";
19972 case X86ISD::FMIN_RND: return "X86ISD::FMIN_RND";
19973 case X86ISD::FMAXC: return "X86ISD::FMAXC";
19974 case X86ISD::FMINC: return "X86ISD::FMINC";
19975 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
19976 case X86ISD::FRCP: return "X86ISD::FRCP";
19977 case X86ISD::EXTRQI: return "X86ISD::EXTRQI";
19978 case X86ISD::INSERTQI: return "X86ISD::INSERTQI";
19979 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
19980 case X86ISD::TLSBASEADDR: return "X86ISD::TLSBASEADDR";
19981 case X86ISD::TLSCALL: return "X86ISD::TLSCALL";
19982 case X86ISD::EH_SJLJ_SETJMP: return "X86ISD::EH_SJLJ_SETJMP";
19983 case X86ISD::EH_SJLJ_LONGJMP: return "X86ISD::EH_SJLJ_LONGJMP";
19984 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
19985 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
19986 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
19987 case X86ISD::FNSTSW16r: return "X86ISD::FNSTSW16r";
19988 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
19989 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
19990 case X86ISD::LCMPXCHG16_DAG: return "X86ISD::LCMPXCHG16_DAG";
19991 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
19992 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
19993 case X86ISD::VZEXT: return "X86ISD::VZEXT";
19994 case X86ISD::VSEXT: return "X86ISD::VSEXT";
19995 case X86ISD::VTRUNC: return "X86ISD::VTRUNC";
19996 case X86ISD::VTRUNCS: return "X86ISD::VTRUNCS";
19997 case X86ISD::VTRUNCUS: return "X86ISD::VTRUNCUS";
19998 case X86ISD::VINSERT: return "X86ISD::VINSERT";
19999 case X86ISD::VFPEXT: return "X86ISD::VFPEXT";
20000 case X86ISD::VFPROUND: return "X86ISD::VFPROUND";
20001 case X86ISD::CVTDQ2PD: return "X86ISD::CVTDQ2PD";
20002 case X86ISD::CVTUDQ2PD: return "X86ISD::CVTUDQ2PD";
20003 case X86ISD::VSHLDQ: return "X86ISD::VSHLDQ";
20004 case X86ISD::VSRLDQ: return "X86ISD::VSRLDQ";
20005 case X86ISD::VSHL: return "X86ISD::VSHL";
20006 case X86ISD::VSRL: return "X86ISD::VSRL";
20007 case X86ISD::VSRA: return "X86ISD::VSRA";
20008 case X86ISD::VSHLI: return "X86ISD::VSHLI";
20009 case X86ISD::VSRLI: return "X86ISD::VSRLI";
20010 case X86ISD::VSRAI: return "X86ISD::VSRAI";
20011 case X86ISD::CMPP: return "X86ISD::CMPP";
20012 case X86ISD::PCMPEQ: return "X86ISD::PCMPEQ";
20013 case X86ISD::PCMPGT: return "X86ISD::PCMPGT";
20014 case X86ISD::PCMPEQM: return "X86ISD::PCMPEQM";
20015 case X86ISD::PCMPGTM: return "X86ISD::PCMPGTM";
20016 case X86ISD::ADD: return "X86ISD::ADD";
20017 case X86ISD::SUB: return "X86ISD::SUB";
20018 case X86ISD::ADC: return "X86ISD::ADC";
20019 case X86ISD::SBB: return "X86ISD::SBB";
20020 case X86ISD::SMUL: return "X86ISD::SMUL";
20021 case X86ISD::UMUL: return "X86ISD::UMUL";
20022 case X86ISD::SMUL8: return "X86ISD::SMUL8";
20023 case X86ISD::UMUL8: return "X86ISD::UMUL8";
20024 case X86ISD::SDIVREM8_SEXT_HREG: return "X86ISD::SDIVREM8_SEXT_HREG";
20025 case X86ISD::UDIVREM8_ZEXT_HREG: return "X86ISD::UDIVREM8_ZEXT_HREG";
20026 case X86ISD::INC: return "X86ISD::INC";
20027 case X86ISD::DEC: return "X86ISD::DEC";
20028 case X86ISD::OR: return "X86ISD::OR";
20029 case X86ISD::XOR: return "X86ISD::XOR";
20030 case X86ISD::AND: return "X86ISD::AND";
20031 case X86ISD::BEXTR: return "X86ISD::BEXTR";
20032 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
20033 case X86ISD::PTEST: return "X86ISD::PTEST";
20034 case X86ISD::TESTP: return "X86ISD::TESTP";
20035 case X86ISD::TESTM: return "X86ISD::TESTM";
20036 case X86ISD::TESTNM: return "X86ISD::TESTNM";
20037 case X86ISD::KORTEST: return "X86ISD::KORTEST";
20038 case X86ISD::KTEST: return "X86ISD::KTEST";
20039 case X86ISD::PACKSS: return "X86ISD::PACKSS";
20040 case X86ISD::PACKUS: return "X86ISD::PACKUS";
20041 case X86ISD::PALIGNR: return "X86ISD::PALIGNR";
20042 case X86ISD::VALIGN: return "X86ISD::VALIGN";
20043 case X86ISD::PSHUFD: return "X86ISD::PSHUFD";
20044 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW";
20045 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW";
20046 case X86ISD::SHUFP: return "X86ISD::SHUFP";
20047 case X86ISD::SHUF128: return "X86ISD::SHUF128";
20048 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS";
20049 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD";
20050 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS";
20051 case X86ISD::MOVLPS: return "X86ISD::MOVLPS";
20052 case X86ISD::MOVLPD: return "X86ISD::MOVLPD";
20053 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP";
20054 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP";
20055 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP";
20056 case X86ISD::MOVSD: return "X86ISD::MOVSD";
20057 case X86ISD::MOVSS: return "X86ISD::MOVSS";
20058 case X86ISD::UNPCKL: return "X86ISD::UNPCKL";
20059 case X86ISD::UNPCKH: return "X86ISD::UNPCKH";
20060 case X86ISD::VBROADCAST: return "X86ISD::VBROADCAST";
20061 case X86ISD::SUBV_BROADCAST: return "X86ISD::SUBV_BROADCAST";
20062 case X86ISD::VEXTRACT: return "X86ISD::VEXTRACT";
20063 case X86ISD::VPERMILPV: return "X86ISD::VPERMILPV";
20064 case X86ISD::VPERMILPI: return "X86ISD::VPERMILPI";
20065 case X86ISD::VPERM2X128: return "X86ISD::VPERM2X128";
20066 case X86ISD::VPERMV: return "X86ISD::VPERMV";
20067 case X86ISD::VPERMV3: return "X86ISD::VPERMV3";
20068 case X86ISD::VPERMIV3: return "X86ISD::VPERMIV3";
20069 case X86ISD::VPERMI: return "X86ISD::VPERMI";
20070 case X86ISD::VPTERNLOG: return "X86ISD::VPTERNLOG";
20071 case X86ISD::VFIXUPIMM: return "X86ISD::VFIXUPIMM";
20072 case X86ISD::VRANGE: return "X86ISD::VRANGE";
20073 case X86ISD::PMULUDQ: return "X86ISD::PMULUDQ";
20074 case X86ISD::PMULDQ: return "X86ISD::PMULDQ";
20075 case X86ISD::PSADBW: return "X86ISD::PSADBW";
20076 case X86ISD::DBPSADBW: return "X86ISD::DBPSADBW";
20077 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
20078 case X86ISD::VAARG_64: return "X86ISD::VAARG_64";
20079 case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA";
20080 case X86ISD::MEMBARRIER: return "X86ISD::MEMBARRIER";
20081 case X86ISD::MFENCE: return "X86ISD::MFENCE";
20082 case X86ISD::SFENCE: return "X86ISD::SFENCE";
20083 case X86ISD::LFENCE: return "X86ISD::LFENCE";
20084 case X86ISD::SEG_ALLOCA: return "X86ISD::SEG_ALLOCA";
20085 case X86ISD::SAHF: return "X86ISD::SAHF";
20086 case X86ISD::RDRAND: return "X86ISD::RDRAND";
20087 case X86ISD::RDSEED: return "X86ISD::RDSEED";
20088 case X86ISD::VPMADDUBSW: return "X86ISD::VPMADDUBSW";
20089 case X86ISD::VPMADDWD: return "X86ISD::VPMADDWD";
20090 case X86ISD::VPROT: return "X86ISD::VPROT";
20091 case X86ISD::VPROTI: return "X86ISD::VPROTI";
20092 case X86ISD::VPSHA: return "X86ISD::VPSHA";
20093 case X86ISD::VPSHL: return "X86ISD::VPSHL";
20094 case X86ISD::VPCOM: return "X86ISD::VPCOM";
20095 case X86ISD::VPCOMU: return "X86ISD::VPCOMU";
20096 case X86ISD::FMADD: return "X86ISD::FMADD";
20097 case X86ISD::FMSUB: return "X86ISD::FMSUB";
20098 case X86ISD::FNMADD: return "X86ISD::FNMADD";
20099 case X86ISD::FNMSUB: return "X86ISD::FNMSUB";
20100 case X86ISD::FMADDSUB: return "X86ISD::FMADDSUB";
20101 case X86ISD::FMSUBADD: return "X86ISD::FMSUBADD";
20102 case X86ISD::FMADD_RND: return "X86ISD::FMADD_RND";
20103 case X86ISD::FNMADD_RND: return "X86ISD::FNMADD_RND";
20104 case X86ISD::FMSUB_RND: return "X86ISD::FMSUB_RND";
20105 case X86ISD::FNMSUB_RND: return "X86ISD::FNMSUB_RND";
20106 case X86ISD::FMADDSUB_RND: return "X86ISD::FMADDSUB_RND";
20107 case X86ISD::FMSUBADD_RND: return "X86ISD::FMSUBADD_RND";
20108 case X86ISD::VRNDSCALE: return "X86ISD::VRNDSCALE";
20109 case X86ISD::VREDUCE: return "X86ISD::VREDUCE";
20110 case X86ISD::VGETMANT: return "X86ISD::VGETMANT";
20111 case X86ISD::PCMPESTRI: return "X86ISD::PCMPESTRI";
20112 case X86ISD::PCMPISTRI: return "X86ISD::PCMPISTRI";
20113 case X86ISD::XTEST: return "X86ISD::XTEST";
20114 case X86ISD::COMPRESS: return "X86ISD::COMPRESS";
20115 case X86ISD::EXPAND: return "X86ISD::EXPAND";
20116 case X86ISD::SELECT: return "X86ISD::SELECT";
20117 case X86ISD::ADDSUB: return "X86ISD::ADDSUB";
20118 case X86ISD::RCP28: return "X86ISD::RCP28";
20119 case X86ISD::EXP2: return "X86ISD::EXP2";
20120 case X86ISD::RSQRT28: return "X86ISD::RSQRT28";
20121 case X86ISD::FADD_RND: return "X86ISD::FADD_RND";
20122 case X86ISD::FSUB_RND: return "X86ISD::FSUB_RND";
20123 case X86ISD::FMUL_RND: return "X86ISD::FMUL_RND";
20124 case X86ISD::FDIV_RND: return "X86ISD::FDIV_RND";
20125 case X86ISD::FSQRT_RND: return "X86ISD::FSQRT_RND";
20126 case X86ISD::FGETEXP_RND: return "X86ISD::FGETEXP_RND";
20127 case X86ISD::SCALEF: return "X86ISD::SCALEF";
20128 case X86ISD::ADDS: return "X86ISD::ADDS";
20129 case X86ISD::SUBS: return "X86ISD::SUBS";
20130 case X86ISD::AVG: return "X86ISD::AVG";
20131 case X86ISD::MULHRS: return "X86ISD::MULHRS";
20132 case X86ISD::SINT_TO_FP_RND: return "X86ISD::SINT_TO_FP_RND";
20133 case X86ISD::UINT_TO_FP_RND: return "X86ISD::UINT_TO_FP_RND";
20134 case X86ISD::FP_TO_SINT_RND: return "X86ISD::FP_TO_SINT_RND";
20135 case X86ISD::FP_TO_UINT_RND: return "X86ISD::FP_TO_UINT_RND";
20136 case X86ISD::VFPCLASS: return "X86ISD::VFPCLASS";
20141 // isLegalAddressingMode - Return true if the addressing mode represented
20142 // by AM is legal for this target, for a load/store of the specified type.
20143 bool X86TargetLowering::isLegalAddressingMode(const DataLayout &DL,
20144 const AddrMode &AM, Type *Ty,
20145 unsigned AS) const {
20146 // X86 supports extremely general addressing modes.
20147 CodeModel::Model M = getTargetMachine().getCodeModel();
20148 Reloc::Model R = getTargetMachine().getRelocationModel();
20150 // X86 allows a sign-extended 32-bit immediate field as a displacement.
20151 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != nullptr))
20156 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
20158 // If a reference to this global requires an extra load, we can't fold it.
20159 if (isGlobalStubReference(GVFlags))
20162 // If BaseGV requires a register for the PIC base, we cannot also have a
20163 // BaseReg specified.
20164 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
20167 // If lower 4G is not available, then we must use rip-relative addressing.
20168 if ((M != CodeModel::Small || R != Reloc::Static) &&
20169 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
20173 switch (AM.Scale) {
20179 // These scales always work.
20184 // These scales are formed with basereg+scalereg. Only accept if there is
20189 default: // Other stuff never works.
20196 bool X86TargetLowering::isVectorShiftByScalarCheap(Type *Ty) const {
20197 unsigned Bits = Ty->getScalarSizeInBits();
20199 // 8-bit shifts are always expensive, but versions with a scalar amount aren't
20200 // particularly cheaper than those without.
20204 // On AVX2 there are new vpsllv[dq] instructions (and other shifts), that make
20205 // variable shifts just as cheap as scalar ones.
20206 if (Subtarget->hasInt256() && (Bits == 32 || Bits == 64))
20209 // Otherwise, it's significantly cheaper to shift by a scalar amount than by a
20210 // fully general vector.
20214 bool X86TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
20215 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
20217 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
20218 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
20219 return NumBits1 > NumBits2;
20222 bool X86TargetLowering::allowTruncateForTailCall(Type *Ty1, Type *Ty2) const {
20223 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
20226 if (!isTypeLegal(EVT::getEVT(Ty1)))
20229 assert(Ty1->getPrimitiveSizeInBits() <= 64 && "i128 is probably not a noop");
20231 // Assuming the caller doesn't have a zeroext or signext return parameter,
20232 // truncation all the way down to i1 is valid.
20236 bool X86TargetLowering::isLegalICmpImmediate(int64_t Imm) const {
20237 return isInt<32>(Imm);
20240 bool X86TargetLowering::isLegalAddImmediate(int64_t Imm) const {
20241 // Can also use sub to handle negated immediates.
20242 return isInt<32>(Imm);
20245 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
20246 if (!VT1.isInteger() || !VT2.isInteger())
20248 unsigned NumBits1 = VT1.getSizeInBits();
20249 unsigned NumBits2 = VT2.getSizeInBits();
20250 return NumBits1 > NumBits2;
20253 bool X86TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
20254 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
20255 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit();
20258 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
20259 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
20260 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
20263 bool X86TargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
20264 EVT VT1 = Val.getValueType();
20265 if (isZExtFree(VT1, VT2))
20268 if (Val.getOpcode() != ISD::LOAD)
20271 if (!VT1.isSimple() || !VT1.isInteger() ||
20272 !VT2.isSimple() || !VT2.isInteger())
20275 switch (VT1.getSimpleVT().SimpleTy) {
20280 // X86 has 8, 16, and 32-bit zero-extending loads.
20287 bool X86TargetLowering::isVectorLoadExtDesirable(SDValue) const { return true; }
20290 X86TargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
20291 if (!(Subtarget->hasFMA() || Subtarget->hasFMA4() || Subtarget->hasAVX512()))
20294 VT = VT.getScalarType();
20296 if (!VT.isSimple())
20299 switch (VT.getSimpleVT().SimpleTy) {
20310 bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
20311 // i16 instructions are longer (0x66 prefix) and potentially slower.
20312 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
20315 /// isShuffleMaskLegal - Targets can use this to indicate that they only
20316 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
20317 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
20318 /// are assumed to be legal.
20320 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
20322 if (!VT.isSimple())
20325 // Not for i1 vectors
20326 if (VT.getScalarType() == MVT::i1)
20329 // Very little shuffling can be done for 64-bit vectors right now.
20330 if (VT.getSizeInBits() == 64)
20333 // We only care that the types being shuffled are legal. The lowering can
20334 // handle any possible shuffle mask that results.
20335 return isTypeLegal(VT.getSimpleVT());
20339 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
20341 // Just delegate to the generic legality, clear masks aren't special.
20342 return isShuffleMaskLegal(Mask, VT);
20345 //===----------------------------------------------------------------------===//
20346 // X86 Scheduler Hooks
20347 //===----------------------------------------------------------------------===//
20349 /// Utility function to emit xbegin specifying the start of an RTM region.
20350 static MachineBasicBlock *EmitXBegin(MachineInstr *MI, MachineBasicBlock *MBB,
20351 const TargetInstrInfo *TII) {
20352 DebugLoc DL = MI->getDebugLoc();
20354 const BasicBlock *BB = MBB->getBasicBlock();
20355 MachineFunction::iterator I = ++MBB->getIterator();
20357 // For the v = xbegin(), we generate
20368 MachineBasicBlock *thisMBB = MBB;
20369 MachineFunction *MF = MBB->getParent();
20370 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
20371 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
20372 MF->insert(I, mainMBB);
20373 MF->insert(I, sinkMBB);
20375 // Transfer the remainder of BB and its successor edges to sinkMBB.
20376 sinkMBB->splice(sinkMBB->begin(), MBB,
20377 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
20378 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
20382 // # fallthrough to mainMBB
20383 // # abortion to sinkMBB
20384 BuildMI(thisMBB, DL, TII->get(X86::XBEGIN_4)).addMBB(sinkMBB);
20385 thisMBB->addSuccessor(mainMBB);
20386 thisMBB->addSuccessor(sinkMBB);
20390 BuildMI(mainMBB, DL, TII->get(X86::MOV32ri), X86::EAX).addImm(-1);
20391 mainMBB->addSuccessor(sinkMBB);
20394 // EAX is live into the sinkMBB
20395 sinkMBB->addLiveIn(X86::EAX);
20396 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
20397 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
20400 MI->eraseFromParent();
20404 // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
20405 // or XMM0_V32I8 in AVX all of this code can be replaced with that
20406 // in the .td file.
20407 static MachineBasicBlock *EmitPCMPSTRM(MachineInstr *MI, MachineBasicBlock *BB,
20408 const TargetInstrInfo *TII) {
20410 switch (MI->getOpcode()) {
20411 default: llvm_unreachable("illegal opcode!");
20412 case X86::PCMPISTRM128REG: Opc = X86::PCMPISTRM128rr; break;
20413 case X86::VPCMPISTRM128REG: Opc = X86::VPCMPISTRM128rr; break;
20414 case X86::PCMPISTRM128MEM: Opc = X86::PCMPISTRM128rm; break;
20415 case X86::VPCMPISTRM128MEM: Opc = X86::VPCMPISTRM128rm; break;
20416 case X86::PCMPESTRM128REG: Opc = X86::PCMPESTRM128rr; break;
20417 case X86::VPCMPESTRM128REG: Opc = X86::VPCMPESTRM128rr; break;
20418 case X86::PCMPESTRM128MEM: Opc = X86::PCMPESTRM128rm; break;
20419 case X86::VPCMPESTRM128MEM: Opc = X86::VPCMPESTRM128rm; break;
20422 DebugLoc dl = MI->getDebugLoc();
20423 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
20425 unsigned NumArgs = MI->getNumOperands();
20426 for (unsigned i = 1; i < NumArgs; ++i) {
20427 MachineOperand &Op = MI->getOperand(i);
20428 if (!(Op.isReg() && Op.isImplicit()))
20429 MIB.addOperand(Op);
20431 if (MI->hasOneMemOperand())
20432 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
20434 BuildMI(*BB, MI, dl,
20435 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
20436 .addReg(X86::XMM0);
20438 MI->eraseFromParent();
20442 // FIXME: Custom handling because TableGen doesn't support multiple implicit
20443 // defs in an instruction pattern
20444 static MachineBasicBlock *EmitPCMPSTRI(MachineInstr *MI, MachineBasicBlock *BB,
20445 const TargetInstrInfo *TII) {
20447 switch (MI->getOpcode()) {
20448 default: llvm_unreachable("illegal opcode!");
20449 case X86::PCMPISTRIREG: Opc = X86::PCMPISTRIrr; break;
20450 case X86::VPCMPISTRIREG: Opc = X86::VPCMPISTRIrr; break;
20451 case X86::PCMPISTRIMEM: Opc = X86::PCMPISTRIrm; break;
20452 case X86::VPCMPISTRIMEM: Opc = X86::VPCMPISTRIrm; break;
20453 case X86::PCMPESTRIREG: Opc = X86::PCMPESTRIrr; break;
20454 case X86::VPCMPESTRIREG: Opc = X86::VPCMPESTRIrr; break;
20455 case X86::PCMPESTRIMEM: Opc = X86::PCMPESTRIrm; break;
20456 case X86::VPCMPESTRIMEM: Opc = X86::VPCMPESTRIrm; break;
20459 DebugLoc dl = MI->getDebugLoc();
20460 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
20462 unsigned NumArgs = MI->getNumOperands(); // remove the results
20463 for (unsigned i = 1; i < NumArgs; ++i) {
20464 MachineOperand &Op = MI->getOperand(i);
20465 if (!(Op.isReg() && Op.isImplicit()))
20466 MIB.addOperand(Op);
20468 if (MI->hasOneMemOperand())
20469 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
20471 BuildMI(*BB, MI, dl,
20472 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
20475 MI->eraseFromParent();
20479 static MachineBasicBlock *EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB,
20480 const X86Subtarget *Subtarget) {
20481 DebugLoc dl = MI->getDebugLoc();
20482 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
20483 // Address into RAX/EAX, other two args into ECX, EDX.
20484 unsigned MemOpc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
20485 unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
20486 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg);
20487 for (int i = 0; i < X86::AddrNumOperands; ++i)
20488 MIB.addOperand(MI->getOperand(i));
20490 unsigned ValOps = X86::AddrNumOperands;
20491 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
20492 .addReg(MI->getOperand(ValOps).getReg());
20493 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EDX)
20494 .addReg(MI->getOperand(ValOps+1).getReg());
20496 // The instruction doesn't actually take any operands though.
20497 BuildMI(*BB, MI, dl, TII->get(X86::MONITORrrr));
20499 MI->eraseFromParent(); // The pseudo is gone now.
20503 MachineBasicBlock *
20504 X86TargetLowering::EmitVAARG64WithCustomInserter(MachineInstr *MI,
20505 MachineBasicBlock *MBB) const {
20506 // Emit va_arg instruction on X86-64.
20508 // Operands to this pseudo-instruction:
20509 // 0 ) Output : destination address (reg)
20510 // 1-5) Input : va_list address (addr, i64mem)
20511 // 6 ) ArgSize : Size (in bytes) of vararg type
20512 // 7 ) ArgMode : 0=overflow only, 1=use gp_offset, 2=use fp_offset
20513 // 8 ) Align : Alignment of type
20514 // 9 ) EFLAGS (implicit-def)
20516 assert(MI->getNumOperands() == 10 && "VAARG_64 should have 10 operands!");
20517 static_assert(X86::AddrNumOperands == 5,
20518 "VAARG_64 assumes 5 address operands");
20520 unsigned DestReg = MI->getOperand(0).getReg();
20521 MachineOperand &Base = MI->getOperand(1);
20522 MachineOperand &Scale = MI->getOperand(2);
20523 MachineOperand &Index = MI->getOperand(3);
20524 MachineOperand &Disp = MI->getOperand(4);
20525 MachineOperand &Segment = MI->getOperand(5);
20526 unsigned ArgSize = MI->getOperand(6).getImm();
20527 unsigned ArgMode = MI->getOperand(7).getImm();
20528 unsigned Align = MI->getOperand(8).getImm();
20530 // Memory Reference
20531 assert(MI->hasOneMemOperand() && "Expected VAARG_64 to have one memoperand");
20532 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
20533 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
20535 // Machine Information
20536 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
20537 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
20538 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64);
20539 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32);
20540 DebugLoc DL = MI->getDebugLoc();
20542 // struct va_list {
20545 // i64 overflow_area (address)
20546 // i64 reg_save_area (address)
20548 // sizeof(va_list) = 24
20549 // alignment(va_list) = 8
20551 unsigned TotalNumIntRegs = 6;
20552 unsigned TotalNumXMMRegs = 8;
20553 bool UseGPOffset = (ArgMode == 1);
20554 bool UseFPOffset = (ArgMode == 2);
20555 unsigned MaxOffset = TotalNumIntRegs * 8 +
20556 (UseFPOffset ? TotalNumXMMRegs * 16 : 0);
20558 /* Align ArgSize to a multiple of 8 */
20559 unsigned ArgSizeA8 = (ArgSize + 7) & ~7;
20560 bool NeedsAlign = (Align > 8);
20562 MachineBasicBlock *thisMBB = MBB;
20563 MachineBasicBlock *overflowMBB;
20564 MachineBasicBlock *offsetMBB;
20565 MachineBasicBlock *endMBB;
20567 unsigned OffsetDestReg = 0; // Argument address computed by offsetMBB
20568 unsigned OverflowDestReg = 0; // Argument address computed by overflowMBB
20569 unsigned OffsetReg = 0;
20571 if (!UseGPOffset && !UseFPOffset) {
20572 // If we only pull from the overflow region, we don't create a branch.
20573 // We don't need to alter control flow.
20574 OffsetDestReg = 0; // unused
20575 OverflowDestReg = DestReg;
20577 offsetMBB = nullptr;
20578 overflowMBB = thisMBB;
20581 // First emit code to check if gp_offset (or fp_offset) is below the bound.
20582 // If so, pull the argument from reg_save_area. (branch to offsetMBB)
20583 // If not, pull from overflow_area. (branch to overflowMBB)
20588 // offsetMBB overflowMBB
20593 // Registers for the PHI in endMBB
20594 OffsetDestReg = MRI.createVirtualRegister(AddrRegClass);
20595 OverflowDestReg = MRI.createVirtualRegister(AddrRegClass);
20597 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
20598 MachineFunction *MF = MBB->getParent();
20599 overflowMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20600 offsetMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20601 endMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20603 MachineFunction::iterator MBBIter = ++MBB->getIterator();
20605 // Insert the new basic blocks
20606 MF->insert(MBBIter, offsetMBB);
20607 MF->insert(MBBIter, overflowMBB);
20608 MF->insert(MBBIter, endMBB);
20610 // Transfer the remainder of MBB and its successor edges to endMBB.
20611 endMBB->splice(endMBB->begin(), thisMBB,
20612 std::next(MachineBasicBlock::iterator(MI)), thisMBB->end());
20613 endMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
20615 // Make offsetMBB and overflowMBB successors of thisMBB
20616 thisMBB->addSuccessor(offsetMBB);
20617 thisMBB->addSuccessor(overflowMBB);
20619 // endMBB is a successor of both offsetMBB and overflowMBB
20620 offsetMBB->addSuccessor(endMBB);
20621 overflowMBB->addSuccessor(endMBB);
20623 // Load the offset value into a register
20624 OffsetReg = MRI.createVirtualRegister(OffsetRegClass);
20625 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg)
20629 .addDisp(Disp, UseFPOffset ? 4 : 0)
20630 .addOperand(Segment)
20631 .setMemRefs(MMOBegin, MMOEnd);
20633 // Check if there is enough room left to pull this argument.
20634 BuildMI(thisMBB, DL, TII->get(X86::CMP32ri))
20636 .addImm(MaxOffset + 8 - ArgSizeA8);
20638 // Branch to "overflowMBB" if offset >= max
20639 // Fall through to "offsetMBB" otherwise
20640 BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE)))
20641 .addMBB(overflowMBB);
20644 // In offsetMBB, emit code to use the reg_save_area.
20646 assert(OffsetReg != 0);
20648 // Read the reg_save_area address.
20649 unsigned RegSaveReg = MRI.createVirtualRegister(AddrRegClass);
20650 BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg)
20655 .addOperand(Segment)
20656 .setMemRefs(MMOBegin, MMOEnd);
20658 // Zero-extend the offset
20659 unsigned OffsetReg64 = MRI.createVirtualRegister(AddrRegClass);
20660 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64)
20663 .addImm(X86::sub_32bit);
20665 // Add the offset to the reg_save_area to get the final address.
20666 BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg)
20667 .addReg(OffsetReg64)
20668 .addReg(RegSaveReg);
20670 // Compute the offset for the next argument
20671 unsigned NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass);
20672 BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg)
20674 .addImm(UseFPOffset ? 16 : 8);
20676 // Store it back into the va_list.
20677 BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr))
20681 .addDisp(Disp, UseFPOffset ? 4 : 0)
20682 .addOperand(Segment)
20683 .addReg(NextOffsetReg)
20684 .setMemRefs(MMOBegin, MMOEnd);
20687 BuildMI(offsetMBB, DL, TII->get(X86::JMP_1))
20692 // Emit code to use overflow area
20695 // Load the overflow_area address into a register.
20696 unsigned OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass);
20697 BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg)
20702 .addOperand(Segment)
20703 .setMemRefs(MMOBegin, MMOEnd);
20705 // If we need to align it, do so. Otherwise, just copy the address
20706 // to OverflowDestReg.
20708 // Align the overflow address
20709 assert((Align & (Align-1)) == 0 && "Alignment must be a power of 2");
20710 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass);
20712 // aligned_addr = (addr + (align-1)) & ~(align-1)
20713 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg)
20714 .addReg(OverflowAddrReg)
20717 BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg)
20719 .addImm(~(uint64_t)(Align-1));
20721 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg)
20722 .addReg(OverflowAddrReg);
20725 // Compute the next overflow address after this argument.
20726 // (the overflow address should be kept 8-byte aligned)
20727 unsigned NextAddrReg = MRI.createVirtualRegister(AddrRegClass);
20728 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg)
20729 .addReg(OverflowDestReg)
20730 .addImm(ArgSizeA8);
20732 // Store the new overflow address.
20733 BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr))
20738 .addOperand(Segment)
20739 .addReg(NextAddrReg)
20740 .setMemRefs(MMOBegin, MMOEnd);
20742 // If we branched, emit the PHI to the front of endMBB.
20744 BuildMI(*endMBB, endMBB->begin(), DL,
20745 TII->get(X86::PHI), DestReg)
20746 .addReg(OffsetDestReg).addMBB(offsetMBB)
20747 .addReg(OverflowDestReg).addMBB(overflowMBB);
20750 // Erase the pseudo instruction
20751 MI->eraseFromParent();
20756 MachineBasicBlock *
20757 X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
20759 MachineBasicBlock *MBB) const {
20760 // Emit code to save XMM registers to the stack. The ABI says that the
20761 // number of registers to save is given in %al, so it's theoretically
20762 // possible to do an indirect jump trick to avoid saving all of them,
20763 // however this code takes a simpler approach and just executes all
20764 // of the stores if %al is non-zero. It's less code, and it's probably
20765 // easier on the hardware branch predictor, and stores aren't all that
20766 // expensive anyway.
20768 // Create the new basic blocks. One block contains all the XMM stores,
20769 // and one block is the final destination regardless of whether any
20770 // stores were performed.
20771 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
20772 MachineFunction *F = MBB->getParent();
20773 MachineFunction::iterator MBBIter = ++MBB->getIterator();
20774 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB);
20775 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB);
20776 F->insert(MBBIter, XMMSaveMBB);
20777 F->insert(MBBIter, EndMBB);
20779 // Transfer the remainder of MBB and its successor edges to EndMBB.
20780 EndMBB->splice(EndMBB->begin(), MBB,
20781 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
20782 EndMBB->transferSuccessorsAndUpdatePHIs(MBB);
20784 // The original block will now fall through to the XMM save block.
20785 MBB->addSuccessor(XMMSaveMBB);
20786 // The XMMSaveMBB will fall through to the end block.
20787 XMMSaveMBB->addSuccessor(EndMBB);
20789 // Now add the instructions.
20790 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
20791 DebugLoc DL = MI->getDebugLoc();
20793 unsigned CountReg = MI->getOperand(0).getReg();
20794 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm();
20795 int64_t VarArgsFPOffset = MI->getOperand(2).getImm();
20797 if (!Subtarget->isCallingConvWin64(F->getFunction()->getCallingConv())) {
20798 // If %al is 0, branch around the XMM save block.
20799 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
20800 BuildMI(MBB, DL, TII->get(X86::JE_1)).addMBB(EndMBB);
20801 MBB->addSuccessor(EndMBB);
20804 // Make sure the last operand is EFLAGS, which gets clobbered by the branch
20805 // that was just emitted, but clearly shouldn't be "saved".
20806 assert((MI->getNumOperands() <= 3 ||
20807 !MI->getOperand(MI->getNumOperands() - 1).isReg() ||
20808 MI->getOperand(MI->getNumOperands() - 1).getReg() == X86::EFLAGS)
20809 && "Expected last argument to be EFLAGS");
20810 unsigned MOVOpc = Subtarget->hasFp256() ? X86::VMOVAPSmr : X86::MOVAPSmr;
20811 // In the XMM save block, save all the XMM argument registers.
20812 for (int i = 3, e = MI->getNumOperands() - 1; i != e; ++i) {
20813 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
20814 MachineMemOperand *MMO = F->getMachineMemOperand(
20815 MachinePointerInfo::getFixedStack(*F, RegSaveFrameIndex, Offset),
20816 MachineMemOperand::MOStore,
20817 /*Size=*/16, /*Align=*/16);
20818 BuildMI(XMMSaveMBB, DL, TII->get(MOVOpc))
20819 .addFrameIndex(RegSaveFrameIndex)
20820 .addImm(/*Scale=*/1)
20821 .addReg(/*IndexReg=*/0)
20822 .addImm(/*Disp=*/Offset)
20823 .addReg(/*Segment=*/0)
20824 .addReg(MI->getOperand(i).getReg())
20825 .addMemOperand(MMO);
20828 MI->eraseFromParent(); // The pseudo instruction is gone now.
20833 // The EFLAGS operand of SelectItr might be missing a kill marker
20834 // because there were multiple uses of EFLAGS, and ISel didn't know
20835 // which to mark. Figure out whether SelectItr should have had a
20836 // kill marker, and set it if it should. Returns the correct kill
20838 static bool checkAndUpdateEFLAGSKill(MachineBasicBlock::iterator SelectItr,
20839 MachineBasicBlock* BB,
20840 const TargetRegisterInfo* TRI) {
20841 // Scan forward through BB for a use/def of EFLAGS.
20842 MachineBasicBlock::iterator miI(std::next(SelectItr));
20843 for (MachineBasicBlock::iterator miE = BB->end(); miI != miE; ++miI) {
20844 const MachineInstr& mi = *miI;
20845 if (mi.readsRegister(X86::EFLAGS))
20847 if (mi.definesRegister(X86::EFLAGS))
20848 break; // Should have kill-flag - update below.
20851 // If we hit the end of the block, check whether EFLAGS is live into a
20853 if (miI == BB->end()) {
20854 for (MachineBasicBlock::succ_iterator sItr = BB->succ_begin(),
20855 sEnd = BB->succ_end();
20856 sItr != sEnd; ++sItr) {
20857 MachineBasicBlock* succ = *sItr;
20858 if (succ->isLiveIn(X86::EFLAGS))
20863 // We found a def, or hit the end of the basic block and EFLAGS wasn't live
20864 // out. SelectMI should have a kill flag on EFLAGS.
20865 SelectItr->addRegisterKilled(X86::EFLAGS, TRI);
20869 // Return true if it is OK for this CMOV pseudo-opcode to be cascaded
20870 // together with other CMOV pseudo-opcodes into a single basic-block with
20871 // conditional jump around it.
20872 static bool isCMOVPseudo(MachineInstr *MI) {
20873 switch (MI->getOpcode()) {
20874 case X86::CMOV_FR32:
20875 case X86::CMOV_FR64:
20876 case X86::CMOV_GR8:
20877 case X86::CMOV_GR16:
20878 case X86::CMOV_GR32:
20879 case X86::CMOV_RFP32:
20880 case X86::CMOV_RFP64:
20881 case X86::CMOV_RFP80:
20882 case X86::CMOV_V2F64:
20883 case X86::CMOV_V2I64:
20884 case X86::CMOV_V4F32:
20885 case X86::CMOV_V4F64:
20886 case X86::CMOV_V4I64:
20887 case X86::CMOV_V16F32:
20888 case X86::CMOV_V8F32:
20889 case X86::CMOV_V8F64:
20890 case X86::CMOV_V8I64:
20891 case X86::CMOV_V8I1:
20892 case X86::CMOV_V16I1:
20893 case X86::CMOV_V32I1:
20894 case X86::CMOV_V64I1:
20902 MachineBasicBlock *
20903 X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
20904 MachineBasicBlock *BB) const {
20905 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
20906 DebugLoc DL = MI->getDebugLoc();
20908 // To "insert" a SELECT_CC instruction, we actually have to insert the
20909 // diamond control-flow pattern. The incoming instruction knows the
20910 // destination vreg to set, the condition code register to branch on, the
20911 // true/false values to select between, and a branch opcode to use.
20912 const BasicBlock *LLVM_BB = BB->getBasicBlock();
20913 MachineFunction::iterator It = ++BB->getIterator();
20918 // cmpTY ccX, r1, r2
20920 // fallthrough --> copy0MBB
20921 MachineBasicBlock *thisMBB = BB;
20922 MachineFunction *F = BB->getParent();
20924 // This code lowers all pseudo-CMOV instructions. Generally it lowers these
20925 // as described above, by inserting a BB, and then making a PHI at the join
20926 // point to select the true and false operands of the CMOV in the PHI.
20928 // The code also handles two different cases of multiple CMOV opcodes
20932 // In this case, there are multiple CMOVs in a row, all which are based on
20933 // the same condition setting (or the exact opposite condition setting).
20934 // In this case we can lower all the CMOVs using a single inserted BB, and
20935 // then make a number of PHIs at the join point to model the CMOVs. The only
20936 // trickiness here, is that in a case like:
20938 // t2 = CMOV cond1 t1, f1
20939 // t3 = CMOV cond1 t2, f2
20941 // when rewriting this into PHIs, we have to perform some renaming on the
20942 // temps since you cannot have a PHI operand refer to a PHI result earlier
20943 // in the same block. The "simple" but wrong lowering would be:
20945 // t2 = PHI t1(BB1), f1(BB2)
20946 // t3 = PHI t2(BB1), f2(BB2)
20948 // but clearly t2 is not defined in BB1, so that is incorrect. The proper
20949 // renaming is to note that on the path through BB1, t2 is really just a
20950 // copy of t1, and do that renaming, properly generating:
20952 // t2 = PHI t1(BB1), f1(BB2)
20953 // t3 = PHI t1(BB1), f2(BB2)
20955 // Case 2, we lower cascaded CMOVs such as
20957 // (CMOV (CMOV F, T, cc1), T, cc2)
20959 // to two successives branches. For that, we look for another CMOV as the
20960 // following instruction.
20962 // Without this, we would add a PHI between the two jumps, which ends up
20963 // creating a few copies all around. For instance, for
20965 // (sitofp (zext (fcmp une)))
20967 // we would generate:
20969 // ucomiss %xmm1, %xmm0
20970 // movss <1.0f>, %xmm0
20971 // movaps %xmm0, %xmm1
20973 // xorps %xmm1, %xmm1
20976 // movaps %xmm1, %xmm0
20980 // because this custom-inserter would have generated:
20992 // A: X = ...; Y = ...
20994 // C: Z = PHI [X, A], [Y, B]
20996 // E: PHI [X, C], [Z, D]
20998 // If we lower both CMOVs in a single step, we can instead generate:
21010 // A: X = ...; Y = ...
21012 // E: PHI [X, A], [X, C], [Y, D]
21014 // Which, in our sitofp/fcmp example, gives us something like:
21016 // ucomiss %xmm1, %xmm0
21017 // movss <1.0f>, %xmm0
21020 // xorps %xmm0, %xmm0
21024 MachineInstr *CascadedCMOV = nullptr;
21025 MachineInstr *LastCMOV = MI;
21026 X86::CondCode CC = X86::CondCode(MI->getOperand(3).getImm());
21027 X86::CondCode OppCC = X86::GetOppositeBranchCondition(CC);
21028 MachineBasicBlock::iterator NextMIIt =
21029 std::next(MachineBasicBlock::iterator(MI));
21031 // Check for case 1, where there are multiple CMOVs with the same condition
21032 // first. Of the two cases of multiple CMOV lowerings, case 1 reduces the
21033 // number of jumps the most.
21035 if (isCMOVPseudo(MI)) {
21036 // See if we have a string of CMOVS with the same condition.
21037 while (NextMIIt != BB->end() &&
21038 isCMOVPseudo(NextMIIt) &&
21039 (NextMIIt->getOperand(3).getImm() == CC ||
21040 NextMIIt->getOperand(3).getImm() == OppCC)) {
21041 LastCMOV = &*NextMIIt;
21046 // This checks for case 2, but only do this if we didn't already find
21047 // case 1, as indicated by LastCMOV == MI.
21048 if (LastCMOV == MI &&
21049 NextMIIt != BB->end() && NextMIIt->getOpcode() == MI->getOpcode() &&
21050 NextMIIt->getOperand(2).getReg() == MI->getOperand(2).getReg() &&
21051 NextMIIt->getOperand(1).getReg() == MI->getOperand(0).getReg()) {
21052 CascadedCMOV = &*NextMIIt;
21055 MachineBasicBlock *jcc1MBB = nullptr;
21057 // If we have a cascaded CMOV, we lower it to two successive branches to
21058 // the same block. EFLAGS is used by both, so mark it as live in the second.
21059 if (CascadedCMOV) {
21060 jcc1MBB = F->CreateMachineBasicBlock(LLVM_BB);
21061 F->insert(It, jcc1MBB);
21062 jcc1MBB->addLiveIn(X86::EFLAGS);
21065 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
21066 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
21067 F->insert(It, copy0MBB);
21068 F->insert(It, sinkMBB);
21070 // If the EFLAGS register isn't dead in the terminator, then claim that it's
21071 // live into the sink and copy blocks.
21072 const TargetRegisterInfo *TRI = Subtarget->getRegisterInfo();
21074 MachineInstr *LastEFLAGSUser = CascadedCMOV ? CascadedCMOV : LastCMOV;
21075 if (!LastEFLAGSUser->killsRegister(X86::EFLAGS) &&
21076 !checkAndUpdateEFLAGSKill(LastEFLAGSUser, BB, TRI)) {
21077 copy0MBB->addLiveIn(X86::EFLAGS);
21078 sinkMBB->addLiveIn(X86::EFLAGS);
21081 // Transfer the remainder of BB and its successor edges to sinkMBB.
21082 sinkMBB->splice(sinkMBB->begin(), BB,
21083 std::next(MachineBasicBlock::iterator(LastCMOV)), BB->end());
21084 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
21086 // Add the true and fallthrough blocks as its successors.
21087 if (CascadedCMOV) {
21088 // The fallthrough block may be jcc1MBB, if we have a cascaded CMOV.
21089 BB->addSuccessor(jcc1MBB);
21091 // In that case, jcc1MBB will itself fallthrough the copy0MBB, and
21092 // jump to the sinkMBB.
21093 jcc1MBB->addSuccessor(copy0MBB);
21094 jcc1MBB->addSuccessor(sinkMBB);
21096 BB->addSuccessor(copy0MBB);
21099 // The true block target of the first (or only) branch is always sinkMBB.
21100 BB->addSuccessor(sinkMBB);
21102 // Create the conditional branch instruction.
21103 unsigned Opc = X86::GetCondBranchFromCond(CC);
21104 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
21106 if (CascadedCMOV) {
21107 unsigned Opc2 = X86::GetCondBranchFromCond(
21108 (X86::CondCode)CascadedCMOV->getOperand(3).getImm());
21109 BuildMI(jcc1MBB, DL, TII->get(Opc2)).addMBB(sinkMBB);
21113 // %FalseValue = ...
21114 // # fallthrough to sinkMBB
21115 copy0MBB->addSuccessor(sinkMBB);
21118 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
21120 MachineBasicBlock::iterator MIItBegin = MachineBasicBlock::iterator(MI);
21121 MachineBasicBlock::iterator MIItEnd =
21122 std::next(MachineBasicBlock::iterator(LastCMOV));
21123 MachineBasicBlock::iterator SinkInsertionPoint = sinkMBB->begin();
21124 DenseMap<unsigned, std::pair<unsigned, unsigned>> RegRewriteTable;
21125 MachineInstrBuilder MIB;
21127 // As we are creating the PHIs, we have to be careful if there is more than
21128 // one. Later CMOVs may reference the results of earlier CMOVs, but later
21129 // PHIs have to reference the individual true/false inputs from earlier PHIs.
21130 // That also means that PHI construction must work forward from earlier to
21131 // later, and that the code must maintain a mapping from earlier PHI's
21132 // destination registers, and the registers that went into the PHI.
21134 for (MachineBasicBlock::iterator MIIt = MIItBegin; MIIt != MIItEnd; ++MIIt) {
21135 unsigned DestReg = MIIt->getOperand(0).getReg();
21136 unsigned Op1Reg = MIIt->getOperand(1).getReg();
21137 unsigned Op2Reg = MIIt->getOperand(2).getReg();
21139 // If this CMOV we are generating is the opposite condition from
21140 // the jump we generated, then we have to swap the operands for the
21141 // PHI that is going to be generated.
21142 if (MIIt->getOperand(3).getImm() == OppCC)
21143 std::swap(Op1Reg, Op2Reg);
21145 if (RegRewriteTable.find(Op1Reg) != RegRewriteTable.end())
21146 Op1Reg = RegRewriteTable[Op1Reg].first;
21148 if (RegRewriteTable.find(Op2Reg) != RegRewriteTable.end())
21149 Op2Reg = RegRewriteTable[Op2Reg].second;
21151 MIB = BuildMI(*sinkMBB, SinkInsertionPoint, DL,
21152 TII->get(X86::PHI), DestReg)
21153 .addReg(Op1Reg).addMBB(copy0MBB)
21154 .addReg(Op2Reg).addMBB(thisMBB);
21156 // Add this PHI to the rewrite table.
21157 RegRewriteTable[DestReg] = std::make_pair(Op1Reg, Op2Reg);
21160 // If we have a cascaded CMOV, the second Jcc provides the same incoming
21161 // value as the first Jcc (the True operand of the SELECT_CC/CMOV nodes).
21162 if (CascadedCMOV) {
21163 MIB.addReg(MI->getOperand(2).getReg()).addMBB(jcc1MBB);
21164 // Copy the PHI result to the register defined by the second CMOV.
21165 BuildMI(*sinkMBB, std::next(MachineBasicBlock::iterator(MIB.getInstr())),
21166 DL, TII->get(TargetOpcode::COPY),
21167 CascadedCMOV->getOperand(0).getReg())
21168 .addReg(MI->getOperand(0).getReg());
21169 CascadedCMOV->eraseFromParent();
21172 // Now remove the CMOV(s).
21173 for (MachineBasicBlock::iterator MIIt = MIItBegin; MIIt != MIItEnd; )
21174 (MIIt++)->eraseFromParent();
21179 MachineBasicBlock *
21180 X86TargetLowering::EmitLoweredAtomicFP(MachineInstr *MI,
21181 MachineBasicBlock *BB) const {
21182 // Combine the following atomic floating-point modification pattern:
21183 // a.store(reg OP a.load(acquire), release)
21184 // Transform them into:
21185 // OPss (%gpr), %xmm
21186 // movss %xmm, (%gpr)
21187 // Or sd equivalent for 64-bit operations.
21189 switch (MI->getOpcode()) {
21190 default: llvm_unreachable("unexpected instr type for EmitLoweredAtomicFP");
21191 case X86::RELEASE_FADD32mr: MOp = X86::MOVSSmr; FOp = X86::ADDSSrm; break;
21192 case X86::RELEASE_FADD64mr: MOp = X86::MOVSDmr; FOp = X86::ADDSDrm; break;
21194 const X86InstrInfo *TII = Subtarget->getInstrInfo();
21195 DebugLoc DL = MI->getDebugLoc();
21196 MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
21197 MachineOperand MSrc = MI->getOperand(0);
21198 unsigned VSrc = MI->getOperand(5).getReg();
21199 const MachineOperand &Disp = MI->getOperand(3);
21200 MachineOperand ZeroDisp = MachineOperand::CreateImm(0);
21201 bool hasDisp = Disp.isGlobal() || Disp.isImm();
21202 if (hasDisp && MSrc.isReg())
21203 MSrc.setIsKill(false);
21204 MachineInstrBuilder MIM = BuildMI(*BB, MI, DL, TII->get(MOp))
21205 .addOperand(/*Base=*/MSrc)
21206 .addImm(/*Scale=*/1)
21207 .addReg(/*Index=*/0)
21208 .addDisp(hasDisp ? Disp : ZeroDisp, /*off=*/0)
21210 MachineInstr *MIO = BuildMI(*BB, (MachineInstr *)MIM, DL, TII->get(FOp),
21211 MRI.createVirtualRegister(MRI.getRegClass(VSrc)))
21213 .addOperand(/*Base=*/MSrc)
21214 .addImm(/*Scale=*/1)
21215 .addReg(/*Index=*/0)
21216 .addDisp(hasDisp ? Disp : ZeroDisp, /*off=*/0)
21217 .addReg(/*Segment=*/0);
21218 MIM.addReg(MIO->getOperand(0).getReg(), RegState::Kill);
21219 MI->eraseFromParent(); // The pseudo instruction is gone now.
21223 MachineBasicBlock *
21224 X86TargetLowering::EmitLoweredSegAlloca(MachineInstr *MI,
21225 MachineBasicBlock *BB) const {
21226 MachineFunction *MF = BB->getParent();
21227 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
21228 DebugLoc DL = MI->getDebugLoc();
21229 const BasicBlock *LLVM_BB = BB->getBasicBlock();
21231 assert(MF->shouldSplitStack());
21233 const bool Is64Bit = Subtarget->is64Bit();
21234 const bool IsLP64 = Subtarget->isTarget64BitLP64();
21236 const unsigned TlsReg = Is64Bit ? X86::FS : X86::GS;
21237 const unsigned TlsOffset = IsLP64 ? 0x70 : Is64Bit ? 0x40 : 0x30;
21240 // ... [Till the alloca]
21241 // If stacklet is not large enough, jump to mallocMBB
21244 // Allocate by subtracting from RSP
21245 // Jump to continueMBB
21248 // Allocate by call to runtime
21252 // [rest of original BB]
21255 MachineBasicBlock *mallocMBB = MF->CreateMachineBasicBlock(LLVM_BB);
21256 MachineBasicBlock *bumpMBB = MF->CreateMachineBasicBlock(LLVM_BB);
21257 MachineBasicBlock *continueMBB = MF->CreateMachineBasicBlock(LLVM_BB);
21259 MachineRegisterInfo &MRI = MF->getRegInfo();
21260 const TargetRegisterClass *AddrRegClass =
21261 getRegClassFor(getPointerTy(MF->getDataLayout()));
21263 unsigned mallocPtrVReg = MRI.createVirtualRegister(AddrRegClass),
21264 bumpSPPtrVReg = MRI.createVirtualRegister(AddrRegClass),
21265 tmpSPVReg = MRI.createVirtualRegister(AddrRegClass),
21266 SPLimitVReg = MRI.createVirtualRegister(AddrRegClass),
21267 sizeVReg = MI->getOperand(1).getReg(),
21268 physSPReg = IsLP64 || Subtarget->isTargetNaCl64() ? X86::RSP : X86::ESP;
21270 MachineFunction::iterator MBBIter = ++BB->getIterator();
21272 MF->insert(MBBIter, bumpMBB);
21273 MF->insert(MBBIter, mallocMBB);
21274 MF->insert(MBBIter, continueMBB);
21276 continueMBB->splice(continueMBB->begin(), BB,
21277 std::next(MachineBasicBlock::iterator(MI)), BB->end());
21278 continueMBB->transferSuccessorsAndUpdatePHIs(BB);
21280 // Add code to the main basic block to check if the stack limit has been hit,
21281 // and if so, jump to mallocMBB otherwise to bumpMBB.
21282 BuildMI(BB, DL, TII->get(TargetOpcode::COPY), tmpSPVReg).addReg(physSPReg);
21283 BuildMI(BB, DL, TII->get(IsLP64 ? X86::SUB64rr:X86::SUB32rr), SPLimitVReg)
21284 .addReg(tmpSPVReg).addReg(sizeVReg);
21285 BuildMI(BB, DL, TII->get(IsLP64 ? X86::CMP64mr:X86::CMP32mr))
21286 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg)
21287 .addReg(SPLimitVReg);
21288 BuildMI(BB, DL, TII->get(X86::JG_1)).addMBB(mallocMBB);
21290 // bumpMBB simply decreases the stack pointer, since we know the current
21291 // stacklet has enough space.
21292 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), physSPReg)
21293 .addReg(SPLimitVReg);
21294 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), bumpSPPtrVReg)
21295 .addReg(SPLimitVReg);
21296 BuildMI(bumpMBB, DL, TII->get(X86::JMP_1)).addMBB(continueMBB);
21298 // Calls into a routine in libgcc to allocate more space from the heap.
21299 const uint32_t *RegMask =
21300 Subtarget->getRegisterInfo()->getCallPreservedMask(*MF, CallingConv::C);
21302 BuildMI(mallocMBB, DL, TII->get(X86::MOV64rr), X86::RDI)
21304 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
21305 .addExternalSymbol("__morestack_allocate_stack_space")
21306 .addRegMask(RegMask)
21307 .addReg(X86::RDI, RegState::Implicit)
21308 .addReg(X86::RAX, RegState::ImplicitDefine);
21309 } else if (Is64Bit) {
21310 BuildMI(mallocMBB, DL, TII->get(X86::MOV32rr), X86::EDI)
21312 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
21313 .addExternalSymbol("__morestack_allocate_stack_space")
21314 .addRegMask(RegMask)
21315 .addReg(X86::EDI, RegState::Implicit)
21316 .addReg(X86::EAX, RegState::ImplicitDefine);
21318 BuildMI(mallocMBB, DL, TII->get(X86::SUB32ri), physSPReg).addReg(physSPReg)
21320 BuildMI(mallocMBB, DL, TII->get(X86::PUSH32r)).addReg(sizeVReg);
21321 BuildMI(mallocMBB, DL, TII->get(X86::CALLpcrel32))
21322 .addExternalSymbol("__morestack_allocate_stack_space")
21323 .addRegMask(RegMask)
21324 .addReg(X86::EAX, RegState::ImplicitDefine);
21328 BuildMI(mallocMBB, DL, TII->get(X86::ADD32ri), physSPReg).addReg(physSPReg)
21331 BuildMI(mallocMBB, DL, TII->get(TargetOpcode::COPY), mallocPtrVReg)
21332 .addReg(IsLP64 ? X86::RAX : X86::EAX);
21333 BuildMI(mallocMBB, DL, TII->get(X86::JMP_1)).addMBB(continueMBB);
21335 // Set up the CFG correctly.
21336 BB->addSuccessor(bumpMBB);
21337 BB->addSuccessor(mallocMBB);
21338 mallocMBB->addSuccessor(continueMBB);
21339 bumpMBB->addSuccessor(continueMBB);
21341 // Take care of the PHI nodes.
21342 BuildMI(*continueMBB, continueMBB->begin(), DL, TII->get(X86::PHI),
21343 MI->getOperand(0).getReg())
21344 .addReg(mallocPtrVReg).addMBB(mallocMBB)
21345 .addReg(bumpSPPtrVReg).addMBB(bumpMBB);
21347 // Delete the original pseudo instruction.
21348 MI->eraseFromParent();
21351 return continueMBB;
21354 MachineBasicBlock *
21355 X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI,
21356 MachineBasicBlock *BB) const {
21357 DebugLoc DL = MI->getDebugLoc();
21359 assert(!Subtarget->isTargetMachO());
21361 Subtarget->getFrameLowering()->emitStackProbeCall(*BB->getParent(), *BB, MI,
21364 MI->eraseFromParent(); // The pseudo instruction is gone now.
21368 MachineBasicBlock *
21369 X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI,
21370 MachineBasicBlock *BB) const {
21371 // This is pretty easy. We're taking the value that we received from
21372 // our load from the relocation, sticking it in either RDI (x86-64)
21373 // or EAX and doing an indirect call. The return value will then
21374 // be in the normal return register.
21375 MachineFunction *F = BB->getParent();
21376 const X86InstrInfo *TII = Subtarget->getInstrInfo();
21377 DebugLoc DL = MI->getDebugLoc();
21379 assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?");
21380 assert(MI->getOperand(3).isGlobal() && "This should be a global");
21382 // Get a register mask for the lowered call.
21383 // FIXME: The 32-bit calls have non-standard calling conventions. Use a
21384 // proper register mask.
21385 const uint32_t *RegMask =
21386 Subtarget->getRegisterInfo()->getCallPreservedMask(*F, CallingConv::C);
21387 if (Subtarget->is64Bit()) {
21388 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
21389 TII->get(X86::MOV64rm), X86::RDI)
21391 .addImm(0).addReg(0)
21392 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
21393 MI->getOperand(3).getTargetFlags())
21395 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m));
21396 addDirectMem(MIB, X86::RDI);
21397 MIB.addReg(X86::RAX, RegState::ImplicitDefine).addRegMask(RegMask);
21398 } else if (F->getTarget().getRelocationModel() != Reloc::PIC_) {
21399 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
21400 TII->get(X86::MOV32rm), X86::EAX)
21402 .addImm(0).addReg(0)
21403 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
21404 MI->getOperand(3).getTargetFlags())
21406 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
21407 addDirectMem(MIB, X86::EAX);
21408 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
21410 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
21411 TII->get(X86::MOV32rm), X86::EAX)
21412 .addReg(TII->getGlobalBaseReg(F))
21413 .addImm(0).addReg(0)
21414 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
21415 MI->getOperand(3).getTargetFlags())
21417 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
21418 addDirectMem(MIB, X86::EAX);
21419 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
21422 MI->eraseFromParent(); // The pseudo instruction is gone now.
21426 MachineBasicBlock *
21427 X86TargetLowering::emitEHSjLjSetJmp(MachineInstr *MI,
21428 MachineBasicBlock *MBB) const {
21429 DebugLoc DL = MI->getDebugLoc();
21430 MachineFunction *MF = MBB->getParent();
21431 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
21432 MachineRegisterInfo &MRI = MF->getRegInfo();
21434 const BasicBlock *BB = MBB->getBasicBlock();
21435 MachineFunction::iterator I = ++MBB->getIterator();
21437 // Memory Reference
21438 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
21439 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
21442 unsigned MemOpndSlot = 0;
21444 unsigned CurOp = 0;
21446 DstReg = MI->getOperand(CurOp++).getReg();
21447 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
21448 assert(RC->hasType(MVT::i32) && "Invalid destination!");
21449 unsigned mainDstReg = MRI.createVirtualRegister(RC);
21450 unsigned restoreDstReg = MRI.createVirtualRegister(RC);
21452 MemOpndSlot = CurOp;
21454 MVT PVT = getPointerTy(MF->getDataLayout());
21455 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
21456 "Invalid Pointer Size!");
21458 // For v = setjmp(buf), we generate
21461 // buf[LabelOffset] = restoreMBB <-- takes address of restoreMBB
21462 // SjLjSetup restoreMBB
21468 // v = phi(main, restore)
21471 // if base pointer being used, load it from frame
21474 MachineBasicBlock *thisMBB = MBB;
21475 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
21476 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
21477 MachineBasicBlock *restoreMBB = MF->CreateMachineBasicBlock(BB);
21478 MF->insert(I, mainMBB);
21479 MF->insert(I, sinkMBB);
21480 MF->push_back(restoreMBB);
21481 restoreMBB->setHasAddressTaken();
21483 MachineInstrBuilder MIB;
21485 // Transfer the remainder of BB and its successor edges to sinkMBB.
21486 sinkMBB->splice(sinkMBB->begin(), MBB,
21487 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
21488 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
21491 unsigned PtrStoreOpc = 0;
21492 unsigned LabelReg = 0;
21493 const int64_t LabelOffset = 1 * PVT.getStoreSize();
21494 Reloc::Model RM = MF->getTarget().getRelocationModel();
21495 bool UseImmLabel = (MF->getTarget().getCodeModel() == CodeModel::Small) &&
21496 (RM == Reloc::Static || RM == Reloc::DynamicNoPIC);
21498 // Prepare IP either in reg or imm.
21499 if (!UseImmLabel) {
21500 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mr : X86::MOV32mr;
21501 const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
21502 LabelReg = MRI.createVirtualRegister(PtrRC);
21503 if (Subtarget->is64Bit()) {
21504 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA64r), LabelReg)
21508 .addMBB(restoreMBB)
21511 const X86InstrInfo *XII = static_cast<const X86InstrInfo*>(TII);
21512 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA32r), LabelReg)
21513 .addReg(XII->getGlobalBaseReg(MF))
21516 .addMBB(restoreMBB, Subtarget->ClassifyBlockAddressReference())
21520 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mi32 : X86::MOV32mi;
21522 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PtrStoreOpc));
21523 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
21524 if (i == X86::AddrDisp)
21525 MIB.addDisp(MI->getOperand(MemOpndSlot + i), LabelOffset);
21527 MIB.addOperand(MI->getOperand(MemOpndSlot + i));
21530 MIB.addReg(LabelReg);
21532 MIB.addMBB(restoreMBB);
21533 MIB.setMemRefs(MMOBegin, MMOEnd);
21535 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::EH_SjLj_Setup))
21536 .addMBB(restoreMBB);
21538 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
21539 MIB.addRegMask(RegInfo->getNoPreservedMask());
21540 thisMBB->addSuccessor(mainMBB);
21541 thisMBB->addSuccessor(restoreMBB);
21545 BuildMI(mainMBB, DL, TII->get(X86::MOV32r0), mainDstReg);
21546 mainMBB->addSuccessor(sinkMBB);
21549 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
21550 TII->get(X86::PHI), DstReg)
21551 .addReg(mainDstReg).addMBB(mainMBB)
21552 .addReg(restoreDstReg).addMBB(restoreMBB);
21555 if (RegInfo->hasBasePointer(*MF)) {
21556 const bool Uses64BitFramePtr =
21557 Subtarget->isTarget64BitLP64() || Subtarget->isTargetNaCl64();
21558 X86MachineFunctionInfo *X86FI = MF->getInfo<X86MachineFunctionInfo>();
21559 X86FI->setRestoreBasePointer(MF);
21560 unsigned FramePtr = RegInfo->getFrameRegister(*MF);
21561 unsigned BasePtr = RegInfo->getBaseRegister();
21562 unsigned Opm = Uses64BitFramePtr ? X86::MOV64rm : X86::MOV32rm;
21563 addRegOffset(BuildMI(restoreMBB, DL, TII->get(Opm), BasePtr),
21564 FramePtr, true, X86FI->getRestoreBasePointerOffset())
21565 .setMIFlag(MachineInstr::FrameSetup);
21567 BuildMI(restoreMBB, DL, TII->get(X86::MOV32ri), restoreDstReg).addImm(1);
21568 BuildMI(restoreMBB, DL, TII->get(X86::JMP_1)).addMBB(sinkMBB);
21569 restoreMBB->addSuccessor(sinkMBB);
21571 MI->eraseFromParent();
21575 MachineBasicBlock *
21576 X86TargetLowering::emitEHSjLjLongJmp(MachineInstr *MI,
21577 MachineBasicBlock *MBB) const {
21578 DebugLoc DL = MI->getDebugLoc();
21579 MachineFunction *MF = MBB->getParent();
21580 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
21581 MachineRegisterInfo &MRI = MF->getRegInfo();
21583 // Memory Reference
21584 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
21585 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
21587 MVT PVT = getPointerTy(MF->getDataLayout());
21588 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
21589 "Invalid Pointer Size!");
21591 const TargetRegisterClass *RC =
21592 (PVT == MVT::i64) ? &X86::GR64RegClass : &X86::GR32RegClass;
21593 unsigned Tmp = MRI.createVirtualRegister(RC);
21594 // Since FP is only updated here but NOT referenced, it's treated as GPR.
21595 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
21596 unsigned FP = (PVT == MVT::i64) ? X86::RBP : X86::EBP;
21597 unsigned SP = RegInfo->getStackRegister();
21599 MachineInstrBuilder MIB;
21601 const int64_t LabelOffset = 1 * PVT.getStoreSize();
21602 const int64_t SPOffset = 2 * PVT.getStoreSize();
21604 unsigned PtrLoadOpc = (PVT == MVT::i64) ? X86::MOV64rm : X86::MOV32rm;
21605 unsigned IJmpOpc = (PVT == MVT::i64) ? X86::JMP64r : X86::JMP32r;
21608 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), FP);
21609 for (unsigned i = 0; i < X86::AddrNumOperands; ++i)
21610 MIB.addOperand(MI->getOperand(i));
21611 MIB.setMemRefs(MMOBegin, MMOEnd);
21613 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), Tmp);
21614 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
21615 if (i == X86::AddrDisp)
21616 MIB.addDisp(MI->getOperand(i), LabelOffset);
21618 MIB.addOperand(MI->getOperand(i));
21620 MIB.setMemRefs(MMOBegin, MMOEnd);
21622 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), SP);
21623 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
21624 if (i == X86::AddrDisp)
21625 MIB.addDisp(MI->getOperand(i), SPOffset);
21627 MIB.addOperand(MI->getOperand(i));
21629 MIB.setMemRefs(MMOBegin, MMOEnd);
21631 BuildMI(*MBB, MI, DL, TII->get(IJmpOpc)).addReg(Tmp);
21633 MI->eraseFromParent();
21637 // Replace 213-type (isel default) FMA3 instructions with 231-type for
21638 // accumulator loops. Writing back to the accumulator allows the coalescer
21639 // to remove extra copies in the loop.
21640 // FIXME: Do this on AVX512. We don't support 231 variants yet (PR23937).
21641 MachineBasicBlock *
21642 X86TargetLowering::emitFMA3Instr(MachineInstr *MI,
21643 MachineBasicBlock *MBB) const {
21644 MachineOperand &AddendOp = MI->getOperand(3);
21646 // Bail out early if the addend isn't a register - we can't switch these.
21647 if (!AddendOp.isReg())
21650 MachineFunction &MF = *MBB->getParent();
21651 MachineRegisterInfo &MRI = MF.getRegInfo();
21653 // Check whether the addend is defined by a PHI:
21654 assert(MRI.hasOneDef(AddendOp.getReg()) && "Multiple defs in SSA?");
21655 MachineInstr &AddendDef = *MRI.def_instr_begin(AddendOp.getReg());
21656 if (!AddendDef.isPHI())
21659 // Look for the following pattern:
21661 // %addend = phi [%entry, 0], [%loop, %result]
21663 // %result<tied1> = FMA213 %m2<tied0>, %m1, %addend
21667 // %addend = phi [%entry, 0], [%loop, %result]
21669 // %result<tied1> = FMA231 %addend<tied0>, %m1, %m2
21671 for (unsigned i = 1, e = AddendDef.getNumOperands(); i < e; i += 2) {
21672 assert(AddendDef.getOperand(i).isReg());
21673 MachineOperand PHISrcOp = AddendDef.getOperand(i);
21674 MachineInstr &PHISrcInst = *MRI.def_instr_begin(PHISrcOp.getReg());
21675 if (&PHISrcInst == MI) {
21676 // Found a matching instruction.
21677 unsigned NewFMAOpc = 0;
21678 switch (MI->getOpcode()) {
21679 case X86::VFMADDPDr213r: NewFMAOpc = X86::VFMADDPDr231r; break;
21680 case X86::VFMADDPSr213r: NewFMAOpc = X86::VFMADDPSr231r; break;
21681 case X86::VFMADDSDr213r: NewFMAOpc = X86::VFMADDSDr231r; break;
21682 case X86::VFMADDSSr213r: NewFMAOpc = X86::VFMADDSSr231r; break;
21683 case X86::VFMSUBPDr213r: NewFMAOpc = X86::VFMSUBPDr231r; break;
21684 case X86::VFMSUBPSr213r: NewFMAOpc = X86::VFMSUBPSr231r; break;
21685 case X86::VFMSUBSDr213r: NewFMAOpc = X86::VFMSUBSDr231r; break;
21686 case X86::VFMSUBSSr213r: NewFMAOpc = X86::VFMSUBSSr231r; break;
21687 case X86::VFNMADDPDr213r: NewFMAOpc = X86::VFNMADDPDr231r; break;
21688 case X86::VFNMADDPSr213r: NewFMAOpc = X86::VFNMADDPSr231r; break;
21689 case X86::VFNMADDSDr213r: NewFMAOpc = X86::VFNMADDSDr231r; break;
21690 case X86::VFNMADDSSr213r: NewFMAOpc = X86::VFNMADDSSr231r; break;
21691 case X86::VFNMSUBPDr213r: NewFMAOpc = X86::VFNMSUBPDr231r; break;
21692 case X86::VFNMSUBPSr213r: NewFMAOpc = X86::VFNMSUBPSr231r; break;
21693 case X86::VFNMSUBSDr213r: NewFMAOpc = X86::VFNMSUBSDr231r; break;
21694 case X86::VFNMSUBSSr213r: NewFMAOpc = X86::VFNMSUBSSr231r; break;
21695 case X86::VFMADDSUBPDr213r: NewFMAOpc = X86::VFMADDSUBPDr231r; break;
21696 case X86::VFMADDSUBPSr213r: NewFMAOpc = X86::VFMADDSUBPSr231r; break;
21697 case X86::VFMSUBADDPDr213r: NewFMAOpc = X86::VFMSUBADDPDr231r; break;
21698 case X86::VFMSUBADDPSr213r: NewFMAOpc = X86::VFMSUBADDPSr231r; break;
21700 case X86::VFMADDPDr213rY: NewFMAOpc = X86::VFMADDPDr231rY; break;
21701 case X86::VFMADDPSr213rY: NewFMAOpc = X86::VFMADDPSr231rY; break;
21702 case X86::VFMSUBPDr213rY: NewFMAOpc = X86::VFMSUBPDr231rY; break;
21703 case X86::VFMSUBPSr213rY: NewFMAOpc = X86::VFMSUBPSr231rY; break;
21704 case X86::VFNMADDPDr213rY: NewFMAOpc = X86::VFNMADDPDr231rY; break;
21705 case X86::VFNMADDPSr213rY: NewFMAOpc = X86::VFNMADDPSr231rY; break;
21706 case X86::VFNMSUBPDr213rY: NewFMAOpc = X86::VFNMSUBPDr231rY; break;
21707 case X86::VFNMSUBPSr213rY: NewFMAOpc = X86::VFNMSUBPSr231rY; break;
21708 case X86::VFMADDSUBPDr213rY: NewFMAOpc = X86::VFMADDSUBPDr231rY; break;
21709 case X86::VFMADDSUBPSr213rY: NewFMAOpc = X86::VFMADDSUBPSr231rY; break;
21710 case X86::VFMSUBADDPDr213rY: NewFMAOpc = X86::VFMSUBADDPDr231rY; break;
21711 case X86::VFMSUBADDPSr213rY: NewFMAOpc = X86::VFMSUBADDPSr231rY; break;
21712 default: llvm_unreachable("Unrecognized FMA variant.");
21715 const TargetInstrInfo &TII = *Subtarget->getInstrInfo();
21716 MachineInstrBuilder MIB =
21717 BuildMI(MF, MI->getDebugLoc(), TII.get(NewFMAOpc))
21718 .addOperand(MI->getOperand(0))
21719 .addOperand(MI->getOperand(3))
21720 .addOperand(MI->getOperand(2))
21721 .addOperand(MI->getOperand(1));
21722 MBB->insert(MachineBasicBlock::iterator(MI), MIB);
21723 MI->eraseFromParent();
21730 MachineBasicBlock *
21731 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
21732 MachineBasicBlock *BB) const {
21733 switch (MI->getOpcode()) {
21734 default: llvm_unreachable("Unexpected instr type to insert");
21735 case X86::TAILJMPd64:
21736 case X86::TAILJMPr64:
21737 case X86::TAILJMPm64:
21738 case X86::TAILJMPd64_REX:
21739 case X86::TAILJMPr64_REX:
21740 case X86::TAILJMPm64_REX:
21741 llvm_unreachable("TAILJMP64 would not be touched here.");
21742 case X86::TCRETURNdi64:
21743 case X86::TCRETURNri64:
21744 case X86::TCRETURNmi64:
21746 case X86::WIN_ALLOCA:
21747 return EmitLoweredWinAlloca(MI, BB);
21748 case X86::SEG_ALLOCA_32:
21749 case X86::SEG_ALLOCA_64:
21750 return EmitLoweredSegAlloca(MI, BB);
21751 case X86::TLSCall_32:
21752 case X86::TLSCall_64:
21753 return EmitLoweredTLSCall(MI, BB);
21754 case X86::CMOV_FR32:
21755 case X86::CMOV_FR64:
21756 case X86::CMOV_GR8:
21757 case X86::CMOV_GR16:
21758 case X86::CMOV_GR32:
21759 case X86::CMOV_RFP32:
21760 case X86::CMOV_RFP64:
21761 case X86::CMOV_RFP80:
21762 case X86::CMOV_V2F64:
21763 case X86::CMOV_V2I64:
21764 case X86::CMOV_V4F32:
21765 case X86::CMOV_V4F64:
21766 case X86::CMOV_V4I64:
21767 case X86::CMOV_V16F32:
21768 case X86::CMOV_V8F32:
21769 case X86::CMOV_V8F64:
21770 case X86::CMOV_V8I64:
21771 case X86::CMOV_V8I1:
21772 case X86::CMOV_V16I1:
21773 case X86::CMOV_V32I1:
21774 case X86::CMOV_V64I1:
21775 return EmitLoweredSelect(MI, BB);
21777 case X86::RELEASE_FADD32mr:
21778 case X86::RELEASE_FADD64mr:
21779 return EmitLoweredAtomicFP(MI, BB);
21781 case X86::FP32_TO_INT16_IN_MEM:
21782 case X86::FP32_TO_INT32_IN_MEM:
21783 case X86::FP32_TO_INT64_IN_MEM:
21784 case X86::FP64_TO_INT16_IN_MEM:
21785 case X86::FP64_TO_INT32_IN_MEM:
21786 case X86::FP64_TO_INT64_IN_MEM:
21787 case X86::FP80_TO_INT16_IN_MEM:
21788 case X86::FP80_TO_INT32_IN_MEM:
21789 case X86::FP80_TO_INT64_IN_MEM: {
21790 MachineFunction *F = BB->getParent();
21791 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
21792 DebugLoc DL = MI->getDebugLoc();
21794 // Change the floating point control register to use "round towards zero"
21795 // mode when truncating to an integer value.
21796 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false);
21797 addFrameReference(BuildMI(*BB, MI, DL,
21798 TII->get(X86::FNSTCW16m)), CWFrameIdx);
21800 // Load the old value of the high byte of the control word...
21802 F->getRegInfo().createVirtualRegister(&X86::GR16RegClass);
21803 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW),
21806 // Set the high part to be round to zero...
21807 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
21810 // Reload the modified control word now...
21811 addFrameReference(BuildMI(*BB, MI, DL,
21812 TII->get(X86::FLDCW16m)), CWFrameIdx);
21814 // Restore the memory image of control word to original value
21815 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
21818 // Get the X86 opcode to use.
21820 switch (MI->getOpcode()) {
21821 default: llvm_unreachable("illegal opcode!");
21822 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
21823 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
21824 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
21825 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
21826 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
21827 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
21828 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
21829 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
21830 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
21834 MachineOperand &Op = MI->getOperand(0);
21836 AM.BaseType = X86AddressMode::RegBase;
21837 AM.Base.Reg = Op.getReg();
21839 AM.BaseType = X86AddressMode::FrameIndexBase;
21840 AM.Base.FrameIndex = Op.getIndex();
21842 Op = MI->getOperand(1);
21844 AM.Scale = Op.getImm();
21845 Op = MI->getOperand(2);
21847 AM.IndexReg = Op.getImm();
21848 Op = MI->getOperand(3);
21849 if (Op.isGlobal()) {
21850 AM.GV = Op.getGlobal();
21852 AM.Disp = Op.getImm();
21854 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM)
21855 .addReg(MI->getOperand(X86::AddrNumOperands).getReg());
21857 // Reload the original control word now.
21858 addFrameReference(BuildMI(*BB, MI, DL,
21859 TII->get(X86::FLDCW16m)), CWFrameIdx);
21861 MI->eraseFromParent(); // The pseudo instruction is gone now.
21864 // String/text processing lowering.
21865 case X86::PCMPISTRM128REG:
21866 case X86::VPCMPISTRM128REG:
21867 case X86::PCMPISTRM128MEM:
21868 case X86::VPCMPISTRM128MEM:
21869 case X86::PCMPESTRM128REG:
21870 case X86::VPCMPESTRM128REG:
21871 case X86::PCMPESTRM128MEM:
21872 case X86::VPCMPESTRM128MEM:
21873 assert(Subtarget->hasSSE42() &&
21874 "Target must have SSE4.2 or AVX features enabled");
21875 return EmitPCMPSTRM(MI, BB, Subtarget->getInstrInfo());
21877 // String/text processing lowering.
21878 case X86::PCMPISTRIREG:
21879 case X86::VPCMPISTRIREG:
21880 case X86::PCMPISTRIMEM:
21881 case X86::VPCMPISTRIMEM:
21882 case X86::PCMPESTRIREG:
21883 case X86::VPCMPESTRIREG:
21884 case X86::PCMPESTRIMEM:
21885 case X86::VPCMPESTRIMEM:
21886 assert(Subtarget->hasSSE42() &&
21887 "Target must have SSE4.2 or AVX features enabled");
21888 return EmitPCMPSTRI(MI, BB, Subtarget->getInstrInfo());
21890 // Thread synchronization.
21892 return EmitMonitor(MI, BB, Subtarget);
21896 return EmitXBegin(MI, BB, Subtarget->getInstrInfo());
21898 case X86::VASTART_SAVE_XMM_REGS:
21899 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
21901 case X86::VAARG_64:
21902 return EmitVAARG64WithCustomInserter(MI, BB);
21904 case X86::EH_SjLj_SetJmp32:
21905 case X86::EH_SjLj_SetJmp64:
21906 return emitEHSjLjSetJmp(MI, BB);
21908 case X86::EH_SjLj_LongJmp32:
21909 case X86::EH_SjLj_LongJmp64:
21910 return emitEHSjLjLongJmp(MI, BB);
21912 case TargetOpcode::STATEPOINT:
21913 // As an implementation detail, STATEPOINT shares the STACKMAP format at
21914 // this point in the process. We diverge later.
21915 return emitPatchPoint(MI, BB);
21917 case TargetOpcode::STACKMAP:
21918 case TargetOpcode::PATCHPOINT:
21919 return emitPatchPoint(MI, BB);
21921 case X86::VFMADDPDr213r:
21922 case X86::VFMADDPSr213r:
21923 case X86::VFMADDSDr213r:
21924 case X86::VFMADDSSr213r:
21925 case X86::VFMSUBPDr213r:
21926 case X86::VFMSUBPSr213r:
21927 case X86::VFMSUBSDr213r:
21928 case X86::VFMSUBSSr213r:
21929 case X86::VFNMADDPDr213r:
21930 case X86::VFNMADDPSr213r:
21931 case X86::VFNMADDSDr213r:
21932 case X86::VFNMADDSSr213r:
21933 case X86::VFNMSUBPDr213r:
21934 case X86::VFNMSUBPSr213r:
21935 case X86::VFNMSUBSDr213r:
21936 case X86::VFNMSUBSSr213r:
21937 case X86::VFMADDSUBPDr213r:
21938 case X86::VFMADDSUBPSr213r:
21939 case X86::VFMSUBADDPDr213r:
21940 case X86::VFMSUBADDPSr213r:
21941 case X86::VFMADDPDr213rY:
21942 case X86::VFMADDPSr213rY:
21943 case X86::VFMSUBPDr213rY:
21944 case X86::VFMSUBPSr213rY:
21945 case X86::VFNMADDPDr213rY:
21946 case X86::VFNMADDPSr213rY:
21947 case X86::VFNMSUBPDr213rY:
21948 case X86::VFNMSUBPSr213rY:
21949 case X86::VFMADDSUBPDr213rY:
21950 case X86::VFMADDSUBPSr213rY:
21951 case X86::VFMSUBADDPDr213rY:
21952 case X86::VFMSUBADDPSr213rY:
21953 return emitFMA3Instr(MI, BB);
21957 //===----------------------------------------------------------------------===//
21958 // X86 Optimization Hooks
21959 //===----------------------------------------------------------------------===//
21961 void X86TargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
21964 const SelectionDAG &DAG,
21965 unsigned Depth) const {
21966 unsigned BitWidth = KnownZero.getBitWidth();
21967 unsigned Opc = Op.getOpcode();
21968 assert((Opc >= ISD::BUILTIN_OP_END ||
21969 Opc == ISD::INTRINSIC_WO_CHAIN ||
21970 Opc == ISD::INTRINSIC_W_CHAIN ||
21971 Opc == ISD::INTRINSIC_VOID) &&
21972 "Should use MaskedValueIsZero if you don't know whether Op"
21973 " is a target node!");
21975 KnownZero = KnownOne = APInt(BitWidth, 0); // Don't know anything.
21989 // These nodes' second result is a boolean.
21990 if (Op.getResNo() == 0)
21993 case X86ISD::SETCC:
21994 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1);
21996 case ISD::INTRINSIC_WO_CHAIN: {
21997 unsigned IntId = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
21998 unsigned NumLoBits = 0;
22001 case Intrinsic::x86_sse_movmsk_ps:
22002 case Intrinsic::x86_avx_movmsk_ps_256:
22003 case Intrinsic::x86_sse2_movmsk_pd:
22004 case Intrinsic::x86_avx_movmsk_pd_256:
22005 case Intrinsic::x86_mmx_pmovmskb:
22006 case Intrinsic::x86_sse2_pmovmskb_128:
22007 case Intrinsic::x86_avx2_pmovmskb: {
22008 // High bits of movmskp{s|d}, pmovmskb are known zero.
22010 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
22011 case Intrinsic::x86_sse_movmsk_ps: NumLoBits = 4; break;
22012 case Intrinsic::x86_avx_movmsk_ps_256: NumLoBits = 8; break;
22013 case Intrinsic::x86_sse2_movmsk_pd: NumLoBits = 2; break;
22014 case Intrinsic::x86_avx_movmsk_pd_256: NumLoBits = 4; break;
22015 case Intrinsic::x86_mmx_pmovmskb: NumLoBits = 8; break;
22016 case Intrinsic::x86_sse2_pmovmskb_128: NumLoBits = 16; break;
22017 case Intrinsic::x86_avx2_pmovmskb: NumLoBits = 32; break;
22019 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - NumLoBits);
22028 unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(
22030 const SelectionDAG &,
22031 unsigned Depth) const {
22032 // SETCC_CARRY sets the dest to ~0 for true or 0 for false.
22033 if (Op.getOpcode() == X86ISD::SETCC_CARRY)
22034 return Op.getValueType().getScalarType().getSizeInBits();
22040 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
22041 /// node is a GlobalAddress + offset.
22042 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
22043 const GlobalValue* &GA,
22044 int64_t &Offset) const {
22045 if (N->getOpcode() == X86ISD::Wrapper) {
22046 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
22047 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
22048 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
22052 return TargetLowering::isGAPlusOffset(N, GA, Offset);
22055 /// isShuffleHigh128VectorInsertLow - Checks whether the shuffle node is the
22056 /// same as extracting the high 128-bit part of 256-bit vector and then
22057 /// inserting the result into the low part of a new 256-bit vector
22058 static bool isShuffleHigh128VectorInsertLow(ShuffleVectorSDNode *SVOp) {
22059 EVT VT = SVOp->getValueType(0);
22060 unsigned NumElems = VT.getVectorNumElements();
22062 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
22063 for (unsigned i = 0, j = NumElems/2; i != NumElems/2; ++i, ++j)
22064 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
22065 SVOp->getMaskElt(j) >= 0)
22071 /// isShuffleLow128VectorInsertHigh - Checks whether the shuffle node is the
22072 /// same as extracting the low 128-bit part of 256-bit vector and then
22073 /// inserting the result into the high part of a new 256-bit vector
22074 static bool isShuffleLow128VectorInsertHigh(ShuffleVectorSDNode *SVOp) {
22075 EVT VT = SVOp->getValueType(0);
22076 unsigned NumElems = VT.getVectorNumElements();
22078 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
22079 for (unsigned i = NumElems/2, j = 0; i != NumElems; ++i, ++j)
22080 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
22081 SVOp->getMaskElt(j) >= 0)
22087 /// PerformShuffleCombine256 - Performs shuffle combines for 256-bit vectors.
22088 static SDValue PerformShuffleCombine256(SDNode *N, SelectionDAG &DAG,
22089 TargetLowering::DAGCombinerInfo &DCI,
22090 const X86Subtarget* Subtarget) {
22092 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
22093 SDValue V1 = SVOp->getOperand(0);
22094 SDValue V2 = SVOp->getOperand(1);
22095 EVT VT = SVOp->getValueType(0);
22096 unsigned NumElems = VT.getVectorNumElements();
22098 if (V1.getOpcode() == ISD::CONCAT_VECTORS &&
22099 V2.getOpcode() == ISD::CONCAT_VECTORS) {
22103 // V UNDEF BUILD_VECTOR UNDEF
22105 // CONCAT_VECTOR CONCAT_VECTOR
22108 // RESULT: V + zero extended
22110 if (V2.getOperand(0).getOpcode() != ISD::BUILD_VECTOR ||
22111 V2.getOperand(1).getOpcode() != ISD::UNDEF ||
22112 V1.getOperand(1).getOpcode() != ISD::UNDEF)
22115 if (!ISD::isBuildVectorAllZeros(V2.getOperand(0).getNode()))
22118 // To match the shuffle mask, the first half of the mask should
22119 // be exactly the first vector, and all the rest a splat with the
22120 // first element of the second one.
22121 for (unsigned i = 0; i != NumElems/2; ++i)
22122 if (!isUndefOrEqual(SVOp->getMaskElt(i), i) ||
22123 !isUndefOrEqual(SVOp->getMaskElt(i+NumElems/2), NumElems))
22126 // If V1 is coming from a vector load then just fold to a VZEXT_LOAD.
22127 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(V1.getOperand(0))) {
22128 if (Ld->hasNUsesOfValue(1, 0)) {
22129 SDVTList Tys = DAG.getVTList(MVT::v4i64, MVT::Other);
22130 SDValue Ops[] = { Ld->getChain(), Ld->getBasePtr() };
22132 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops,
22134 Ld->getPointerInfo(),
22135 Ld->getAlignment(),
22136 false/*isVolatile*/, true/*ReadMem*/,
22137 false/*WriteMem*/);
22139 // Make sure the newly-created LOAD is in the same position as Ld in
22140 // terms of dependency. We create a TokenFactor for Ld and ResNode,
22141 // and update uses of Ld's output chain to use the TokenFactor.
22142 if (Ld->hasAnyUseOfValue(1)) {
22143 SDValue NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
22144 SDValue(Ld, 1), SDValue(ResNode.getNode(), 1));
22145 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), NewChain);
22146 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(Ld, 1),
22147 SDValue(ResNode.getNode(), 1));
22150 return DAG.getBitcast(VT, ResNode);
22154 // Emit a zeroed vector and insert the desired subvector on its
22156 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
22157 SDValue InsV = Insert128BitVector(Zeros, V1.getOperand(0), 0, DAG, dl);
22158 return DCI.CombineTo(N, InsV);
22161 //===--------------------------------------------------------------------===//
22162 // Combine some shuffles into subvector extracts and inserts:
22165 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
22166 if (isShuffleHigh128VectorInsertLow(SVOp)) {
22167 SDValue V = Extract128BitVector(V1, NumElems/2, DAG, dl);
22168 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, 0, DAG, dl);
22169 return DCI.CombineTo(N, InsV);
22172 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
22173 if (isShuffleLow128VectorInsertHigh(SVOp)) {
22174 SDValue V = Extract128BitVector(V1, 0, DAG, dl);
22175 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, NumElems/2, DAG, dl);
22176 return DCI.CombineTo(N, InsV);
22182 /// \brief Combine an arbitrary chain of shuffles into a single instruction if
22185 /// This is the leaf of the recursive combinine below. When we have found some
22186 /// chain of single-use x86 shuffle instructions and accumulated the combined
22187 /// shuffle mask represented by them, this will try to pattern match that mask
22188 /// into either a single instruction if there is a special purpose instruction
22189 /// for this operation, or into a PSHUFB instruction which is a fully general
22190 /// instruction but should only be used to replace chains over a certain depth.
22191 static bool combineX86ShuffleChain(SDValue Op, SDValue Root, ArrayRef<int> Mask,
22192 int Depth, bool HasPSHUFB, SelectionDAG &DAG,
22193 TargetLowering::DAGCombinerInfo &DCI,
22194 const X86Subtarget *Subtarget) {
22195 assert(!Mask.empty() && "Cannot combine an empty shuffle mask!");
22197 // Find the operand that enters the chain. Note that multiple uses are OK
22198 // here, we're not going to remove the operand we find.
22199 SDValue Input = Op.getOperand(0);
22200 while (Input.getOpcode() == ISD::BITCAST)
22201 Input = Input.getOperand(0);
22203 MVT VT = Input.getSimpleValueType();
22204 MVT RootVT = Root.getSimpleValueType();
22207 if (Mask.size() == 1) {
22208 int Index = Mask[0];
22209 assert((Index >= 0 || Index == SM_SentinelUndef ||
22210 Index == SM_SentinelZero) &&
22211 "Invalid shuffle index found!");
22213 // We may end up with an accumulated mask of size 1 as a result of
22214 // widening of shuffle operands (see function canWidenShuffleElements).
22215 // If the only shuffle index is equal to SM_SentinelZero then propagate
22216 // a zero vector. Otherwise, the combine shuffle mask is a no-op shuffle
22217 // mask, and therefore the entire chain of shuffles can be folded away.
22218 if (Index == SM_SentinelZero)
22219 DCI.CombineTo(Root.getNode(), getZeroVector(RootVT, Subtarget, DAG, DL));
22221 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Input),
22226 // Use the float domain if the operand type is a floating point type.
22227 bool FloatDomain = VT.isFloatingPoint();
22229 // For floating point shuffles, we don't have free copies in the shuffle
22230 // instructions or the ability to load as part of the instruction, so
22231 // canonicalize their shuffles to UNPCK or MOV variants.
22233 // Note that even with AVX we prefer the PSHUFD form of shuffle for integer
22234 // vectors because it can have a load folded into it that UNPCK cannot. This
22235 // doesn't preclude something switching to the shorter encoding post-RA.
22237 // FIXME: Should teach these routines about AVX vector widths.
22238 if (FloatDomain && VT.getSizeInBits() == 128) {
22239 if (Mask.equals({0, 0}) || Mask.equals({1, 1})) {
22240 bool Lo = Mask.equals({0, 0});
22243 // Check if we have SSE3 which will let us use MOVDDUP. That instruction
22244 // is no slower than UNPCKLPD but has the option to fold the input operand
22245 // into even an unaligned memory load.
22246 if (Lo && Subtarget->hasSSE3()) {
22247 Shuffle = X86ISD::MOVDDUP;
22248 ShuffleVT = MVT::v2f64;
22250 // We have MOVLHPS and MOVHLPS throughout SSE and they encode smaller
22251 // than the UNPCK variants.
22252 Shuffle = Lo ? X86ISD::MOVLHPS : X86ISD::MOVHLPS;
22253 ShuffleVT = MVT::v4f32;
22255 if (Depth == 1 && Root->getOpcode() == Shuffle)
22256 return false; // Nothing to do!
22257 Op = DAG.getBitcast(ShuffleVT, Input);
22258 DCI.AddToWorklist(Op.getNode());
22259 if (Shuffle == X86ISD::MOVDDUP)
22260 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op);
22262 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
22263 DCI.AddToWorklist(Op.getNode());
22264 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Op),
22268 if (Subtarget->hasSSE3() &&
22269 (Mask.equals({0, 0, 2, 2}) || Mask.equals({1, 1, 3, 3}))) {
22270 bool Lo = Mask.equals({0, 0, 2, 2});
22271 unsigned Shuffle = Lo ? X86ISD::MOVSLDUP : X86ISD::MOVSHDUP;
22272 MVT ShuffleVT = MVT::v4f32;
22273 if (Depth == 1 && Root->getOpcode() == Shuffle)
22274 return false; // Nothing to do!
22275 Op = DAG.getBitcast(ShuffleVT, Input);
22276 DCI.AddToWorklist(Op.getNode());
22277 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op);
22278 DCI.AddToWorklist(Op.getNode());
22279 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Op),
22283 if (Mask.equals({0, 0, 1, 1}) || Mask.equals({2, 2, 3, 3})) {
22284 bool Lo = Mask.equals({0, 0, 1, 1});
22285 unsigned Shuffle = Lo ? X86ISD::UNPCKL : X86ISD::UNPCKH;
22286 MVT ShuffleVT = MVT::v4f32;
22287 if (Depth == 1 && Root->getOpcode() == Shuffle)
22288 return false; // Nothing to do!
22289 Op = DAG.getBitcast(ShuffleVT, Input);
22290 DCI.AddToWorklist(Op.getNode());
22291 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
22292 DCI.AddToWorklist(Op.getNode());
22293 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Op),
22299 // We always canonicalize the 8 x i16 and 16 x i8 shuffles into their UNPCK
22300 // variants as none of these have single-instruction variants that are
22301 // superior to the UNPCK formulation.
22302 if (!FloatDomain && VT.getSizeInBits() == 128 &&
22303 (Mask.equals({0, 0, 1, 1, 2, 2, 3, 3}) ||
22304 Mask.equals({4, 4, 5, 5, 6, 6, 7, 7}) ||
22305 Mask.equals({0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7}) ||
22307 {8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}))) {
22308 bool Lo = Mask[0] == 0;
22309 unsigned Shuffle = Lo ? X86ISD::UNPCKL : X86ISD::UNPCKH;
22310 if (Depth == 1 && Root->getOpcode() == Shuffle)
22311 return false; // Nothing to do!
22313 switch (Mask.size()) {
22315 ShuffleVT = MVT::v8i16;
22318 ShuffleVT = MVT::v16i8;
22321 llvm_unreachable("Impossible mask size!");
22323 Op = DAG.getBitcast(ShuffleVT, Input);
22324 DCI.AddToWorklist(Op.getNode());
22325 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
22326 DCI.AddToWorklist(Op.getNode());
22327 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Op),
22332 // Don't try to re-form single instruction chains under any circumstances now
22333 // that we've done encoding canonicalization for them.
22337 // If we have 3 or more shuffle instructions or a chain involving PSHUFB, we
22338 // can replace them with a single PSHUFB instruction profitably. Intel's
22339 // manuals suggest only using PSHUFB if doing so replacing 5 instructions, but
22340 // in practice PSHUFB tends to be *very* fast so we're more aggressive.
22341 if ((Depth >= 3 || HasPSHUFB) && Subtarget->hasSSSE3()) {
22342 SmallVector<SDValue, 16> PSHUFBMask;
22343 int NumBytes = VT.getSizeInBits() / 8;
22344 int Ratio = NumBytes / Mask.size();
22345 for (int i = 0; i < NumBytes; ++i) {
22346 if (Mask[i / Ratio] == SM_SentinelUndef) {
22347 PSHUFBMask.push_back(DAG.getUNDEF(MVT::i8));
22350 int M = Mask[i / Ratio] != SM_SentinelZero
22351 ? Ratio * Mask[i / Ratio] + i % Ratio
22353 PSHUFBMask.push_back(DAG.getConstant(M, DL, MVT::i8));
22355 MVT ByteVT = MVT::getVectorVT(MVT::i8, NumBytes);
22356 Op = DAG.getBitcast(ByteVT, Input);
22357 DCI.AddToWorklist(Op.getNode());
22358 SDValue PSHUFBMaskOp =
22359 DAG.getNode(ISD::BUILD_VECTOR, DL, ByteVT, PSHUFBMask);
22360 DCI.AddToWorklist(PSHUFBMaskOp.getNode());
22361 Op = DAG.getNode(X86ISD::PSHUFB, DL, ByteVT, Op, PSHUFBMaskOp);
22362 DCI.AddToWorklist(Op.getNode());
22363 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Op),
22368 // Failed to find any combines.
22372 /// \brief Fully generic combining of x86 shuffle instructions.
22374 /// This should be the last combine run over the x86 shuffle instructions. Once
22375 /// they have been fully optimized, this will recursively consider all chains
22376 /// of single-use shuffle instructions, build a generic model of the cumulative
22377 /// shuffle operation, and check for simpler instructions which implement this
22378 /// operation. We use this primarily for two purposes:
22380 /// 1) Collapse generic shuffles to specialized single instructions when
22381 /// equivalent. In most cases, this is just an encoding size win, but
22382 /// sometimes we will collapse multiple generic shuffles into a single
22383 /// special-purpose shuffle.
22384 /// 2) Look for sequences of shuffle instructions with 3 or more total
22385 /// instructions, and replace them with the slightly more expensive SSSE3
22386 /// PSHUFB instruction if available. We do this as the last combining step
22387 /// to ensure we avoid using PSHUFB if we can implement the shuffle with
22388 /// a suitable short sequence of other instructions. The PHUFB will either
22389 /// use a register or have to read from memory and so is slightly (but only
22390 /// slightly) more expensive than the other shuffle instructions.
22392 /// Because this is inherently a quadratic operation (for each shuffle in
22393 /// a chain, we recurse up the chain), the depth is limited to 8 instructions.
22394 /// This should never be an issue in practice as the shuffle lowering doesn't
22395 /// produce sequences of more than 8 instructions.
22397 /// FIXME: We will currently miss some cases where the redundant shuffling
22398 /// would simplify under the threshold for PSHUFB formation because of
22399 /// combine-ordering. To fix this, we should do the redundant instruction
22400 /// combining in this recursive walk.
22401 static bool combineX86ShufflesRecursively(SDValue Op, SDValue Root,
22402 ArrayRef<int> RootMask,
22403 int Depth, bool HasPSHUFB,
22405 TargetLowering::DAGCombinerInfo &DCI,
22406 const X86Subtarget *Subtarget) {
22407 // Bound the depth of our recursive combine because this is ultimately
22408 // quadratic in nature.
22412 // Directly rip through bitcasts to find the underlying operand.
22413 while (Op.getOpcode() == ISD::BITCAST && Op.getOperand(0).hasOneUse())
22414 Op = Op.getOperand(0);
22416 MVT VT = Op.getSimpleValueType();
22417 if (!VT.isVector())
22418 return false; // Bail if we hit a non-vector.
22420 assert(Root.getSimpleValueType().isVector() &&
22421 "Shuffles operate on vector types!");
22422 assert(VT.getSizeInBits() == Root.getSimpleValueType().getSizeInBits() &&
22423 "Can only combine shuffles of the same vector register size.");
22425 if (!isTargetShuffle(Op.getOpcode()))
22427 SmallVector<int, 16> OpMask;
22429 bool HaveMask = getTargetShuffleMask(Op.getNode(), VT, OpMask, IsUnary);
22430 // We only can combine unary shuffles which we can decode the mask for.
22431 if (!HaveMask || !IsUnary)
22434 assert(VT.getVectorNumElements() == OpMask.size() &&
22435 "Different mask size from vector size!");
22436 assert(((RootMask.size() > OpMask.size() &&
22437 RootMask.size() % OpMask.size() == 0) ||
22438 (OpMask.size() > RootMask.size() &&
22439 OpMask.size() % RootMask.size() == 0) ||
22440 OpMask.size() == RootMask.size()) &&
22441 "The smaller number of elements must divide the larger.");
22442 int RootRatio = std::max<int>(1, OpMask.size() / RootMask.size());
22443 int OpRatio = std::max<int>(1, RootMask.size() / OpMask.size());
22444 assert(((RootRatio == 1 && OpRatio == 1) ||
22445 (RootRatio == 1) != (OpRatio == 1)) &&
22446 "Must not have a ratio for both incoming and op masks!");
22448 SmallVector<int, 16> Mask;
22449 Mask.reserve(std::max(OpMask.size(), RootMask.size()));
22451 // Merge this shuffle operation's mask into our accumulated mask. Note that
22452 // this shuffle's mask will be the first applied to the input, followed by the
22453 // root mask to get us all the way to the root value arrangement. The reason
22454 // for this order is that we are recursing up the operation chain.
22455 for (int i = 0, e = std::max(OpMask.size(), RootMask.size()); i < e; ++i) {
22456 int RootIdx = i / RootRatio;
22457 if (RootMask[RootIdx] < 0) {
22458 // This is a zero or undef lane, we're done.
22459 Mask.push_back(RootMask[RootIdx]);
22463 int RootMaskedIdx = RootMask[RootIdx] * RootRatio + i % RootRatio;
22464 int OpIdx = RootMaskedIdx / OpRatio;
22465 if (OpMask[OpIdx] < 0) {
22466 // The incoming lanes are zero or undef, it doesn't matter which ones we
22468 Mask.push_back(OpMask[OpIdx]);
22472 // Ok, we have non-zero lanes, map them through.
22473 Mask.push_back(OpMask[OpIdx] * OpRatio +
22474 RootMaskedIdx % OpRatio);
22477 // See if we can recurse into the operand to combine more things.
22478 switch (Op.getOpcode()) {
22479 case X86ISD::PSHUFB:
22481 case X86ISD::PSHUFD:
22482 case X86ISD::PSHUFHW:
22483 case X86ISD::PSHUFLW:
22484 if (Op.getOperand(0).hasOneUse() &&
22485 combineX86ShufflesRecursively(Op.getOperand(0), Root, Mask, Depth + 1,
22486 HasPSHUFB, DAG, DCI, Subtarget))
22490 case X86ISD::UNPCKL:
22491 case X86ISD::UNPCKH:
22492 assert(Op.getOperand(0) == Op.getOperand(1) &&
22493 "We only combine unary shuffles!");
22494 // We can't check for single use, we have to check that this shuffle is the
22496 if (Op->isOnlyUserOf(Op.getOperand(0).getNode()) &&
22497 combineX86ShufflesRecursively(Op.getOperand(0), Root, Mask, Depth + 1,
22498 HasPSHUFB, DAG, DCI, Subtarget))
22503 // Minor canonicalization of the accumulated shuffle mask to make it easier
22504 // to match below. All this does is detect masks with squential pairs of
22505 // elements, and shrink them to the half-width mask. It does this in a loop
22506 // so it will reduce the size of the mask to the minimal width mask which
22507 // performs an equivalent shuffle.
22508 SmallVector<int, 16> WidenedMask;
22509 while (Mask.size() > 1 && canWidenShuffleElements(Mask, WidenedMask)) {
22510 Mask = std::move(WidenedMask);
22511 WidenedMask.clear();
22514 return combineX86ShuffleChain(Op, Root, Mask, Depth, HasPSHUFB, DAG, DCI,
22518 /// \brief Get the PSHUF-style mask from PSHUF node.
22520 /// This is a very minor wrapper around getTargetShuffleMask to easy forming v4
22521 /// PSHUF-style masks that can be reused with such instructions.
22522 static SmallVector<int, 4> getPSHUFShuffleMask(SDValue N) {
22523 MVT VT = N.getSimpleValueType();
22524 SmallVector<int, 4> Mask;
22526 bool HaveMask = getTargetShuffleMask(N.getNode(), VT, Mask, IsUnary);
22530 // If we have more than 128-bits, only the low 128-bits of shuffle mask
22531 // matter. Check that the upper masks are repeats and remove them.
22532 if (VT.getSizeInBits() > 128) {
22533 int LaneElts = 128 / VT.getScalarSizeInBits();
22535 for (int i = 1, NumLanes = VT.getSizeInBits() / 128; i < NumLanes; ++i)
22536 for (int j = 0; j < LaneElts; ++j)
22537 assert(Mask[j] == Mask[i * LaneElts + j] - (LaneElts * i) &&
22538 "Mask doesn't repeat in high 128-bit lanes!");
22540 Mask.resize(LaneElts);
22543 switch (N.getOpcode()) {
22544 case X86ISD::PSHUFD:
22546 case X86ISD::PSHUFLW:
22549 case X86ISD::PSHUFHW:
22550 Mask.erase(Mask.begin(), Mask.begin() + 4);
22551 for (int &M : Mask)
22555 llvm_unreachable("No valid shuffle instruction found!");
22559 /// \brief Search for a combinable shuffle across a chain ending in pshufd.
22561 /// We walk up the chain and look for a combinable shuffle, skipping over
22562 /// shuffles that we could hoist this shuffle's transformation past without
22563 /// altering anything.
22565 combineRedundantDWordShuffle(SDValue N, MutableArrayRef<int> Mask,
22567 TargetLowering::DAGCombinerInfo &DCI) {
22568 assert(N.getOpcode() == X86ISD::PSHUFD &&
22569 "Called with something other than an x86 128-bit half shuffle!");
22572 // Walk up a single-use chain looking for a combinable shuffle. Keep a stack
22573 // of the shuffles in the chain so that we can form a fresh chain to replace
22575 SmallVector<SDValue, 8> Chain;
22576 SDValue V = N.getOperand(0);
22577 for (; V.hasOneUse(); V = V.getOperand(0)) {
22578 switch (V.getOpcode()) {
22580 return SDValue(); // Nothing combined!
22583 // Skip bitcasts as we always know the type for the target specific
22587 case X86ISD::PSHUFD:
22588 // Found another dword shuffle.
22591 case X86ISD::PSHUFLW:
22592 // Check that the low words (being shuffled) are the identity in the
22593 // dword shuffle, and the high words are self-contained.
22594 if (Mask[0] != 0 || Mask[1] != 1 ||
22595 !(Mask[2] >= 2 && Mask[2] < 4 && Mask[3] >= 2 && Mask[3] < 4))
22598 Chain.push_back(V);
22601 case X86ISD::PSHUFHW:
22602 // Check that the high words (being shuffled) are the identity in the
22603 // dword shuffle, and the low words are self-contained.
22604 if (Mask[2] != 2 || Mask[3] != 3 ||
22605 !(Mask[0] >= 0 && Mask[0] < 2 && Mask[1] >= 0 && Mask[1] < 2))
22608 Chain.push_back(V);
22611 case X86ISD::UNPCKL:
22612 case X86ISD::UNPCKH:
22613 // For either i8 -> i16 or i16 -> i32 unpacks, we can combine a dword
22614 // shuffle into a preceding word shuffle.
22615 if (V.getSimpleValueType().getScalarType() != MVT::i8 &&
22616 V.getSimpleValueType().getScalarType() != MVT::i16)
22619 // Search for a half-shuffle which we can combine with.
22620 unsigned CombineOp =
22621 V.getOpcode() == X86ISD::UNPCKL ? X86ISD::PSHUFLW : X86ISD::PSHUFHW;
22622 if (V.getOperand(0) != V.getOperand(1) ||
22623 !V->isOnlyUserOf(V.getOperand(0).getNode()))
22625 Chain.push_back(V);
22626 V = V.getOperand(0);
22628 switch (V.getOpcode()) {
22630 return SDValue(); // Nothing to combine.
22632 case X86ISD::PSHUFLW:
22633 case X86ISD::PSHUFHW:
22634 if (V.getOpcode() == CombineOp)
22637 Chain.push_back(V);
22641 V = V.getOperand(0);
22645 } while (V.hasOneUse());
22648 // Break out of the loop if we break out of the switch.
22652 if (!V.hasOneUse())
22653 // We fell out of the loop without finding a viable combining instruction.
22656 // Merge this node's mask and our incoming mask.
22657 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
22658 for (int &M : Mask)
22660 V = DAG.getNode(V.getOpcode(), DL, V.getValueType(), V.getOperand(0),
22661 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
22663 // Rebuild the chain around this new shuffle.
22664 while (!Chain.empty()) {
22665 SDValue W = Chain.pop_back_val();
22667 if (V.getValueType() != W.getOperand(0).getValueType())
22668 V = DAG.getBitcast(W.getOperand(0).getValueType(), V);
22670 switch (W.getOpcode()) {
22672 llvm_unreachable("Only PSHUF and UNPCK instructions get here!");
22674 case X86ISD::UNPCKL:
22675 case X86ISD::UNPCKH:
22676 V = DAG.getNode(W.getOpcode(), DL, W.getValueType(), V, V);
22679 case X86ISD::PSHUFD:
22680 case X86ISD::PSHUFLW:
22681 case X86ISD::PSHUFHW:
22682 V = DAG.getNode(W.getOpcode(), DL, W.getValueType(), V, W.getOperand(1));
22686 if (V.getValueType() != N.getValueType())
22687 V = DAG.getBitcast(N.getValueType(), V);
22689 // Return the new chain to replace N.
22693 /// \brief Search for a combinable shuffle across a chain ending in pshuflw or
22696 /// We walk up the chain, skipping shuffles of the other half and looking
22697 /// through shuffles which switch halves trying to find a shuffle of the same
22698 /// pair of dwords.
22699 static bool combineRedundantHalfShuffle(SDValue N, MutableArrayRef<int> Mask,
22701 TargetLowering::DAGCombinerInfo &DCI) {
22703 (N.getOpcode() == X86ISD::PSHUFLW || N.getOpcode() == X86ISD::PSHUFHW) &&
22704 "Called with something other than an x86 128-bit half shuffle!");
22706 unsigned CombineOpcode = N.getOpcode();
22708 // Walk up a single-use chain looking for a combinable shuffle.
22709 SDValue V = N.getOperand(0);
22710 for (; V.hasOneUse(); V = V.getOperand(0)) {
22711 switch (V.getOpcode()) {
22713 return false; // Nothing combined!
22716 // Skip bitcasts as we always know the type for the target specific
22720 case X86ISD::PSHUFLW:
22721 case X86ISD::PSHUFHW:
22722 if (V.getOpcode() == CombineOpcode)
22725 // Other-half shuffles are no-ops.
22728 // Break out of the loop if we break out of the switch.
22732 if (!V.hasOneUse())
22733 // We fell out of the loop without finding a viable combining instruction.
22736 // Combine away the bottom node as its shuffle will be accumulated into
22737 // a preceding shuffle.
22738 DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
22740 // Record the old value.
22743 // Merge this node's mask and our incoming mask (adjusted to account for all
22744 // the pshufd instructions encountered).
22745 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
22746 for (int &M : Mask)
22748 V = DAG.getNode(V.getOpcode(), DL, MVT::v8i16, V.getOperand(0),
22749 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
22751 // Check that the shuffles didn't cancel each other out. If not, we need to
22752 // combine to the new one.
22754 // Replace the combinable shuffle with the combined one, updating all users
22755 // so that we re-evaluate the chain here.
22756 DCI.CombineTo(Old.getNode(), V, /*AddTo*/ true);
22761 /// \brief Try to combine x86 target specific shuffles.
22762 static SDValue PerformTargetShuffleCombine(SDValue N, SelectionDAG &DAG,
22763 TargetLowering::DAGCombinerInfo &DCI,
22764 const X86Subtarget *Subtarget) {
22766 MVT VT = N.getSimpleValueType();
22767 SmallVector<int, 4> Mask;
22769 switch (N.getOpcode()) {
22770 case X86ISD::PSHUFD:
22771 case X86ISD::PSHUFLW:
22772 case X86ISD::PSHUFHW:
22773 Mask = getPSHUFShuffleMask(N);
22774 assert(Mask.size() == 4);
22780 // Nuke no-op shuffles that show up after combining.
22781 if (isNoopShuffleMask(Mask))
22782 return DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
22784 // Look for simplifications involving one or two shuffle instructions.
22785 SDValue V = N.getOperand(0);
22786 switch (N.getOpcode()) {
22789 case X86ISD::PSHUFLW:
22790 case X86ISD::PSHUFHW:
22791 assert(VT.getScalarType() == MVT::i16 && "Bad word shuffle type!");
22793 if (combineRedundantHalfShuffle(N, Mask, DAG, DCI))
22794 return SDValue(); // We combined away this shuffle, so we're done.
22796 // See if this reduces to a PSHUFD which is no more expensive and can
22797 // combine with more operations. Note that it has to at least flip the
22798 // dwords as otherwise it would have been removed as a no-op.
22799 if (makeArrayRef(Mask).equals({2, 3, 0, 1})) {
22800 int DMask[] = {0, 1, 2, 3};
22801 int DOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 2;
22802 DMask[DOffset + 0] = DOffset + 1;
22803 DMask[DOffset + 1] = DOffset + 0;
22804 MVT DVT = MVT::getVectorVT(MVT::i32, VT.getVectorNumElements() / 2);
22805 V = DAG.getBitcast(DVT, V);
22806 DCI.AddToWorklist(V.getNode());
22807 V = DAG.getNode(X86ISD::PSHUFD, DL, DVT, V,
22808 getV4X86ShuffleImm8ForMask(DMask, DL, DAG));
22809 DCI.AddToWorklist(V.getNode());
22810 return DAG.getBitcast(VT, V);
22813 // Look for shuffle patterns which can be implemented as a single unpack.
22814 // FIXME: This doesn't handle the location of the PSHUFD generically, and
22815 // only works when we have a PSHUFD followed by two half-shuffles.
22816 if (Mask[0] == Mask[1] && Mask[2] == Mask[3] &&
22817 (V.getOpcode() == X86ISD::PSHUFLW ||
22818 V.getOpcode() == X86ISD::PSHUFHW) &&
22819 V.getOpcode() != N.getOpcode() &&
22821 SDValue D = V.getOperand(0);
22822 while (D.getOpcode() == ISD::BITCAST && D.hasOneUse())
22823 D = D.getOperand(0);
22824 if (D.getOpcode() == X86ISD::PSHUFD && D.hasOneUse()) {
22825 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
22826 SmallVector<int, 4> DMask = getPSHUFShuffleMask(D);
22827 int NOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
22828 int VOffset = V.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
22830 for (int i = 0; i < 4; ++i) {
22831 WordMask[i + NOffset] = Mask[i] + NOffset;
22832 WordMask[i + VOffset] = VMask[i] + VOffset;
22834 // Map the word mask through the DWord mask.
22836 for (int i = 0; i < 8; ++i)
22837 MappedMask[i] = 2 * DMask[WordMask[i] / 2] + WordMask[i] % 2;
22838 if (makeArrayRef(MappedMask).equals({0, 0, 1, 1, 2, 2, 3, 3}) ||
22839 makeArrayRef(MappedMask).equals({4, 4, 5, 5, 6, 6, 7, 7})) {
22840 // We can replace all three shuffles with an unpack.
22841 V = DAG.getBitcast(VT, D.getOperand(0));
22842 DCI.AddToWorklist(V.getNode());
22843 return DAG.getNode(MappedMask[0] == 0 ? X86ISD::UNPCKL
22852 case X86ISD::PSHUFD:
22853 if (SDValue NewN = combineRedundantDWordShuffle(N, Mask, DAG, DCI))
22862 /// \brief Try to combine a shuffle into a target-specific add-sub node.
22864 /// We combine this directly on the abstract vector shuffle nodes so it is
22865 /// easier to generically match. We also insert dummy vector shuffle nodes for
22866 /// the operands which explicitly discard the lanes which are unused by this
22867 /// operation to try to flow through the rest of the combiner the fact that
22868 /// they're unused.
22869 static SDValue combineShuffleToAddSub(SDNode *N, SelectionDAG &DAG) {
22871 EVT VT = N->getValueType(0);
22873 // We only handle target-independent shuffles.
22874 // FIXME: It would be easy and harmless to use the target shuffle mask
22875 // extraction tool to support more.
22876 if (N->getOpcode() != ISD::VECTOR_SHUFFLE)
22879 auto *SVN = cast<ShuffleVectorSDNode>(N);
22880 ArrayRef<int> Mask = SVN->getMask();
22881 SDValue V1 = N->getOperand(0);
22882 SDValue V2 = N->getOperand(1);
22884 // We require the first shuffle operand to be the SUB node, and the second to
22885 // be the ADD node.
22886 // FIXME: We should support the commuted patterns.
22887 if (V1->getOpcode() != ISD::FSUB || V2->getOpcode() != ISD::FADD)
22890 // If there are other uses of these operations we can't fold them.
22891 if (!V1->hasOneUse() || !V2->hasOneUse())
22894 // Ensure that both operations have the same operands. Note that we can
22895 // commute the FADD operands.
22896 SDValue LHS = V1->getOperand(0), RHS = V1->getOperand(1);
22897 if ((V2->getOperand(0) != LHS || V2->getOperand(1) != RHS) &&
22898 (V2->getOperand(0) != RHS || V2->getOperand(1) != LHS))
22901 // We're looking for blends between FADD and FSUB nodes. We insist on these
22902 // nodes being lined up in a specific expected pattern.
22903 if (!(isShuffleEquivalent(V1, V2, Mask, {0, 3}) ||
22904 isShuffleEquivalent(V1, V2, Mask, {0, 5, 2, 7}) ||
22905 isShuffleEquivalent(V1, V2, Mask, {0, 9, 2, 11, 4, 13, 6, 15})))
22908 // Only specific types are legal at this point, assert so we notice if and
22909 // when these change.
22910 assert((VT == MVT::v4f32 || VT == MVT::v2f64 || VT == MVT::v8f32 ||
22911 VT == MVT::v4f64) &&
22912 "Unknown vector type encountered!");
22914 return DAG.getNode(X86ISD::ADDSUB, DL, VT, LHS, RHS);
22917 /// PerformShuffleCombine - Performs several different shuffle combines.
22918 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
22919 TargetLowering::DAGCombinerInfo &DCI,
22920 const X86Subtarget *Subtarget) {
22922 SDValue N0 = N->getOperand(0);
22923 SDValue N1 = N->getOperand(1);
22924 EVT VT = N->getValueType(0);
22926 // Don't create instructions with illegal types after legalize types has run.
22927 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22928 if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType()))
22931 // If we have legalized the vector types, look for blends of FADD and FSUB
22932 // nodes that we can fuse into an ADDSUB node.
22933 if (TLI.isTypeLegal(VT) && Subtarget->hasSSE3())
22934 if (SDValue AddSub = combineShuffleToAddSub(N, DAG))
22937 // Combine 256-bit vector shuffles. This is only profitable when in AVX mode
22938 if (Subtarget->hasFp256() && VT.is256BitVector() &&
22939 N->getOpcode() == ISD::VECTOR_SHUFFLE)
22940 return PerformShuffleCombine256(N, DAG, DCI, Subtarget);
22942 // During Type Legalization, when promoting illegal vector types,
22943 // the backend might introduce new shuffle dag nodes and bitcasts.
22945 // This code performs the following transformation:
22946 // fold: (shuffle (bitcast (BINOP A, B)), Undef, <Mask>) ->
22947 // (shuffle (BINOP (bitcast A), (bitcast B)), Undef, <Mask>)
22949 // We do this only if both the bitcast and the BINOP dag nodes have
22950 // one use. Also, perform this transformation only if the new binary
22951 // operation is legal. This is to avoid introducing dag nodes that
22952 // potentially need to be further expanded (or custom lowered) into a
22953 // less optimal sequence of dag nodes.
22954 if (!DCI.isBeforeLegalize() && DCI.isBeforeLegalizeOps() &&
22955 N1.getOpcode() == ISD::UNDEF && N0.hasOneUse() &&
22956 N0.getOpcode() == ISD::BITCAST) {
22957 SDValue BC0 = N0.getOperand(0);
22958 EVT SVT = BC0.getValueType();
22959 unsigned Opcode = BC0.getOpcode();
22960 unsigned NumElts = VT.getVectorNumElements();
22962 if (BC0.hasOneUse() && SVT.isVector() &&
22963 SVT.getVectorNumElements() * 2 == NumElts &&
22964 TLI.isOperationLegal(Opcode, VT)) {
22965 bool CanFold = false;
22977 unsigned SVTNumElts = SVT.getVectorNumElements();
22978 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
22979 for (unsigned i = 0, e = SVTNumElts; i != e && CanFold; ++i)
22980 CanFold = SVOp->getMaskElt(i) == (int)(i * 2);
22981 for (unsigned i = SVTNumElts, e = NumElts; i != e && CanFold; ++i)
22982 CanFold = SVOp->getMaskElt(i) < 0;
22985 SDValue BC00 = DAG.getBitcast(VT, BC0.getOperand(0));
22986 SDValue BC01 = DAG.getBitcast(VT, BC0.getOperand(1));
22987 SDValue NewBinOp = DAG.getNode(BC0.getOpcode(), dl, VT, BC00, BC01);
22988 return DAG.getVectorShuffle(VT, dl, NewBinOp, N1, &SVOp->getMask()[0]);
22993 // Combine a vector_shuffle that is equal to build_vector load1, load2, load3,
22994 // load4, <0, 1, 2, 3> into a 128-bit load if the load addresses are
22995 // consecutive, non-overlapping, and in the right order.
22996 SmallVector<SDValue, 16> Elts;
22997 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
22998 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0));
23000 if (SDValue LD = EltsFromConsecutiveLoads(VT, Elts, dl, DAG, true))
23003 if (isTargetShuffle(N->getOpcode())) {
23005 PerformTargetShuffleCombine(SDValue(N, 0), DAG, DCI, Subtarget);
23006 if (Shuffle.getNode())
23009 // Try recursively combining arbitrary sequences of x86 shuffle
23010 // instructions into higher-order shuffles. We do this after combining
23011 // specific PSHUF instruction sequences into their minimal form so that we
23012 // can evaluate how many specialized shuffle instructions are involved in
23013 // a particular chain.
23014 SmallVector<int, 1> NonceMask; // Just a placeholder.
23015 NonceMask.push_back(0);
23016 if (combineX86ShufflesRecursively(SDValue(N, 0), SDValue(N, 0), NonceMask,
23017 /*Depth*/ 1, /*HasPSHUFB*/ false, DAG,
23019 return SDValue(); // This routine will use CombineTo to replace N.
23025 /// XFormVExtractWithShuffleIntoLoad - Check if a vector extract from a target
23026 /// specific shuffle of a load can be folded into a single element load.
23027 /// Similar handling for VECTOR_SHUFFLE is performed by DAGCombiner, but
23028 /// shuffles have been custom lowered so we need to handle those here.
23029 static SDValue XFormVExtractWithShuffleIntoLoad(SDNode *N, SelectionDAG &DAG,
23030 TargetLowering::DAGCombinerInfo &DCI) {
23031 if (DCI.isBeforeLegalizeOps())
23034 SDValue InVec = N->getOperand(0);
23035 SDValue EltNo = N->getOperand(1);
23037 if (!isa<ConstantSDNode>(EltNo))
23040 EVT OriginalVT = InVec.getValueType();
23042 if (InVec.getOpcode() == ISD::BITCAST) {
23043 // Don't duplicate a load with other uses.
23044 if (!InVec.hasOneUse())
23046 EVT BCVT = InVec.getOperand(0).getValueType();
23047 if (!BCVT.isVector() ||
23048 BCVT.getVectorNumElements() != OriginalVT.getVectorNumElements())
23050 InVec = InVec.getOperand(0);
23053 EVT CurrentVT = InVec.getValueType();
23055 if (!isTargetShuffle(InVec.getOpcode()))
23058 // Don't duplicate a load with other uses.
23059 if (!InVec.hasOneUse())
23062 SmallVector<int, 16> ShuffleMask;
23064 if (!getTargetShuffleMask(InVec.getNode(), CurrentVT.getSimpleVT(),
23065 ShuffleMask, UnaryShuffle))
23068 // Select the input vector, guarding against out of range extract vector.
23069 unsigned NumElems = CurrentVT.getVectorNumElements();
23070 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
23071 int Idx = (Elt > (int)NumElems) ? -1 : ShuffleMask[Elt];
23072 SDValue LdNode = (Idx < (int)NumElems) ? InVec.getOperand(0)
23073 : InVec.getOperand(1);
23075 // If inputs to shuffle are the same for both ops, then allow 2 uses
23076 unsigned AllowedUses = InVec.getNumOperands() > 1 &&
23077 InVec.getOperand(0) == InVec.getOperand(1) ? 2 : 1;
23079 if (LdNode.getOpcode() == ISD::BITCAST) {
23080 // Don't duplicate a load with other uses.
23081 if (!LdNode.getNode()->hasNUsesOfValue(AllowedUses, 0))
23084 AllowedUses = 1; // only allow 1 load use if we have a bitcast
23085 LdNode = LdNode.getOperand(0);
23088 if (!ISD::isNormalLoad(LdNode.getNode()))
23091 LoadSDNode *LN0 = cast<LoadSDNode>(LdNode);
23093 if (!LN0 ||!LN0->hasNUsesOfValue(AllowedUses, 0) || LN0->isVolatile())
23096 EVT EltVT = N->getValueType(0);
23097 // If there's a bitcast before the shuffle, check if the load type and
23098 // alignment is valid.
23099 unsigned Align = LN0->getAlignment();
23100 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23101 unsigned NewAlign = DAG.getDataLayout().getABITypeAlignment(
23102 EltVT.getTypeForEVT(*DAG.getContext()));
23104 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, EltVT))
23107 // All checks match so transform back to vector_shuffle so that DAG combiner
23108 // can finish the job
23111 // Create shuffle node taking into account the case that its a unary shuffle
23112 SDValue Shuffle = (UnaryShuffle) ? DAG.getUNDEF(CurrentVT)
23113 : InVec.getOperand(1);
23114 Shuffle = DAG.getVectorShuffle(CurrentVT, dl,
23115 InVec.getOperand(0), Shuffle,
23117 Shuffle = DAG.getBitcast(OriginalVT, Shuffle);
23118 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, N->getValueType(0), Shuffle,
23122 static SDValue PerformBITCASTCombine(SDNode *N, SelectionDAG &DAG,
23123 const X86Subtarget *Subtarget) {
23124 SDValue N0 = N->getOperand(0);
23125 EVT VT = N->getValueType(0);
23127 // Detect bitcasts between i32 to x86mmx low word. Since MMX types are
23128 // special and don't usually play with other vector types, it's better to
23129 // handle them early to be sure we emit efficient code by avoiding
23130 // store-load conversions.
23131 if (VT == MVT::x86mmx && N0.getOpcode() == ISD::BUILD_VECTOR &&
23132 N0.getValueType() == MVT::v2i32 &&
23133 isa<ConstantSDNode>(N0.getOperand(1))) {
23134 SDValue N00 = N0->getOperand(0);
23135 if (N0.getConstantOperandVal(1) == 0 && N00.getValueType() == MVT::i32)
23136 return DAG.getNode(X86ISD::MMX_MOVW2D, SDLoc(N00), VT, N00);
23139 // Convert a bitcasted integer logic operation that has one bitcasted
23140 // floating-point operand and one constant operand into a floating-point
23141 // logic operation. This may create a load of the constant, but that is
23142 // cheaper than materializing the constant in an integer register and
23143 // transferring it to an SSE register or transferring the SSE operand to
23144 // integer register and back.
23146 switch (N0.getOpcode()) {
23147 case ISD::AND: FPOpcode = X86ISD::FAND; break;
23148 case ISD::OR: FPOpcode = X86ISD::FOR; break;
23149 case ISD::XOR: FPOpcode = X86ISD::FXOR; break;
23150 default: return SDValue();
23152 if (((Subtarget->hasSSE1() && VT == MVT::f32) ||
23153 (Subtarget->hasSSE2() && VT == MVT::f64)) &&
23154 isa<ConstantSDNode>(N0.getOperand(1)) &&
23155 N0.getOperand(0).getOpcode() == ISD::BITCAST &&
23156 N0.getOperand(0).getOperand(0).getValueType() == VT) {
23157 SDValue N000 = N0.getOperand(0).getOperand(0);
23158 SDValue FPConst = DAG.getBitcast(VT, N0.getOperand(1));
23159 return DAG.getNode(FPOpcode, SDLoc(N0), VT, N000, FPConst);
23165 /// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index
23166 /// generation and convert it from being a bunch of shuffles and extracts
23167 /// into a somewhat faster sequence. For i686, the best sequence is apparently
23168 /// storing the value and loading scalars back, while for x64 we should
23169 /// use 64-bit extracts and shifts.
23170 static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG,
23171 TargetLowering::DAGCombinerInfo &DCI) {
23172 if (SDValue NewOp = XFormVExtractWithShuffleIntoLoad(N, DAG, DCI))
23175 SDValue InputVector = N->getOperand(0);
23176 SDLoc dl(InputVector);
23177 // Detect mmx to i32 conversion through a v2i32 elt extract.
23178 if (InputVector.getOpcode() == ISD::BITCAST && InputVector.hasOneUse() &&
23179 N->getValueType(0) == MVT::i32 &&
23180 InputVector.getValueType() == MVT::v2i32) {
23182 // The bitcast source is a direct mmx result.
23183 SDValue MMXSrc = InputVector.getNode()->getOperand(0);
23184 if (MMXSrc.getValueType() == MVT::x86mmx)
23185 return DAG.getNode(X86ISD::MMX_MOVD2W, SDLoc(InputVector),
23186 N->getValueType(0),
23187 InputVector.getNode()->getOperand(0));
23189 // The mmx is indirect: (i64 extract_elt (v1i64 bitcast (x86mmx ...))).
23190 if (MMXSrc.getOpcode() == ISD::EXTRACT_VECTOR_ELT && MMXSrc.hasOneUse() &&
23191 MMXSrc.getValueType() == MVT::i64) {
23192 SDValue MMXSrcOp = MMXSrc.getOperand(0);
23193 if (MMXSrcOp.hasOneUse() && MMXSrcOp.getOpcode() == ISD::BITCAST &&
23194 MMXSrcOp.getValueType() == MVT::v1i64 &&
23195 MMXSrcOp.getOperand(0).getValueType() == MVT::x86mmx)
23196 return DAG.getNode(X86ISD::MMX_MOVD2W, SDLoc(InputVector),
23197 N->getValueType(0), MMXSrcOp.getOperand(0));
23201 EVT VT = N->getValueType(0);
23203 if (VT == MVT::i1 && dyn_cast<ConstantSDNode>(N->getOperand(1)) &&
23204 InputVector.getOpcode() == ISD::BITCAST &&
23205 dyn_cast<ConstantSDNode>(InputVector.getOperand(0))) {
23206 uint64_t ExtractedElt =
23207 cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
23208 uint64_t InputValue =
23209 cast<ConstantSDNode>(InputVector.getOperand(0))->getZExtValue();
23210 uint64_t Res = (InputValue >> ExtractedElt) & 1;
23211 return DAG.getConstant(Res, dl, MVT::i1);
23213 // Only operate on vectors of 4 elements, where the alternative shuffling
23214 // gets to be more expensive.
23215 if (InputVector.getValueType() != MVT::v4i32)
23218 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a
23219 // single use which is a sign-extend or zero-extend, and all elements are
23221 SmallVector<SDNode *, 4> Uses;
23222 unsigned ExtractedElements = 0;
23223 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(),
23224 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) {
23225 if (UI.getUse().getResNo() != InputVector.getResNo())
23228 SDNode *Extract = *UI;
23229 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
23232 if (Extract->getValueType(0) != MVT::i32)
23234 if (!Extract->hasOneUse())
23236 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND &&
23237 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND)
23239 if (!isa<ConstantSDNode>(Extract->getOperand(1)))
23242 // Record which element was extracted.
23243 ExtractedElements |=
23244 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue();
23246 Uses.push_back(Extract);
23249 // If not all the elements were used, this may not be worthwhile.
23250 if (ExtractedElements != 15)
23253 // Ok, we've now decided to do the transformation.
23254 // If 64-bit shifts are legal, use the extract-shift sequence,
23255 // otherwise bounce the vector off the cache.
23256 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23259 if (TLI.isOperationLegal(ISD::SRA, MVT::i64)) {
23260 SDValue Cst = DAG.getBitcast(MVT::v2i64, InputVector);
23261 auto &DL = DAG.getDataLayout();
23262 EVT VecIdxTy = DAG.getTargetLoweringInfo().getVectorIdxTy(DL);
23263 SDValue BottomHalf = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64, Cst,
23264 DAG.getConstant(0, dl, VecIdxTy));
23265 SDValue TopHalf = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64, Cst,
23266 DAG.getConstant(1, dl, VecIdxTy));
23268 SDValue ShAmt = DAG.getConstant(
23269 32, dl, DAG.getTargetLoweringInfo().getShiftAmountTy(MVT::i64, DL));
23270 Vals[0] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, BottomHalf);
23271 Vals[1] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32,
23272 DAG.getNode(ISD::SRA, dl, MVT::i64, BottomHalf, ShAmt));
23273 Vals[2] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, TopHalf);
23274 Vals[3] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32,
23275 DAG.getNode(ISD::SRA, dl, MVT::i64, TopHalf, ShAmt));
23277 // Store the value to a temporary stack slot.
23278 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType());
23279 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr,
23280 MachinePointerInfo(), false, false, 0);
23282 EVT ElementType = InputVector.getValueType().getVectorElementType();
23283 unsigned EltSize = ElementType.getSizeInBits() / 8;
23285 // Replace each use (extract) with a load of the appropriate element.
23286 for (unsigned i = 0; i < 4; ++i) {
23287 uint64_t Offset = EltSize * i;
23288 auto PtrVT = TLI.getPointerTy(DAG.getDataLayout());
23289 SDValue OffsetVal = DAG.getConstant(Offset, dl, PtrVT);
23291 SDValue ScalarAddr =
23292 DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, OffsetVal);
23294 // Load the scalar.
23295 Vals[i] = DAG.getLoad(ElementType, dl, Ch,
23296 ScalarAddr, MachinePointerInfo(),
23297 false, false, false, 0);
23302 // Replace the extracts
23303 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(),
23304 UE = Uses.end(); UI != UE; ++UI) {
23305 SDNode *Extract = *UI;
23307 SDValue Idx = Extract->getOperand(1);
23308 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
23309 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), Vals[IdxVal]);
23312 // The replacement was made in place; don't return anything.
23317 transformVSELECTtoBlendVECTOR_SHUFFLE(SDNode *N, SelectionDAG &DAG,
23318 const X86Subtarget *Subtarget) {
23320 SDValue Cond = N->getOperand(0);
23321 SDValue LHS = N->getOperand(1);
23322 SDValue RHS = N->getOperand(2);
23324 if (Cond.getOpcode() == ISD::SIGN_EXTEND) {
23325 SDValue CondSrc = Cond->getOperand(0);
23326 if (CondSrc->getOpcode() == ISD::SIGN_EXTEND_INREG)
23327 Cond = CondSrc->getOperand(0);
23330 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
23333 // A vselect where all conditions and data are constants can be optimized into
23334 // a single vector load by SelectionDAGLegalize::ExpandBUILD_VECTOR().
23335 if (ISD::isBuildVectorOfConstantSDNodes(LHS.getNode()) &&
23336 ISD::isBuildVectorOfConstantSDNodes(RHS.getNode()))
23339 unsigned MaskValue = 0;
23340 if (!BUILD_VECTORtoBlendMask(cast<BuildVectorSDNode>(Cond), MaskValue))
23343 MVT VT = N->getSimpleValueType(0);
23344 unsigned NumElems = VT.getVectorNumElements();
23345 SmallVector<int, 8> ShuffleMask(NumElems, -1);
23346 for (unsigned i = 0; i < NumElems; ++i) {
23347 // Be sure we emit undef where we can.
23348 if (Cond.getOperand(i)->getOpcode() == ISD::UNDEF)
23349 ShuffleMask[i] = -1;
23351 ShuffleMask[i] = i + NumElems * ((MaskValue >> i) & 1);
23354 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23355 if (!TLI.isShuffleMaskLegal(ShuffleMask, VT))
23357 return DAG.getVectorShuffle(VT, dl, LHS, RHS, &ShuffleMask[0]);
23360 /// PerformSELECTCombine - Do target-specific dag combines on SELECT and VSELECT
23362 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
23363 TargetLowering::DAGCombinerInfo &DCI,
23364 const X86Subtarget *Subtarget) {
23366 SDValue Cond = N->getOperand(0);
23367 // Get the LHS/RHS of the select.
23368 SDValue LHS = N->getOperand(1);
23369 SDValue RHS = N->getOperand(2);
23370 EVT VT = LHS.getValueType();
23371 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23373 // If we have SSE[12] support, try to form min/max nodes. SSE min/max
23374 // instructions match the semantics of the common C idiom x<y?x:y but not
23375 // x<=y?x:y, because of how they handle negative zero (which can be
23376 // ignored in unsafe-math mode).
23377 // We also try to create v2f32 min/max nodes, which we later widen to v4f32.
23378 if (Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() &&
23379 VT != MVT::f80 && (TLI.isTypeLegal(VT) || VT == MVT::v2f32) &&
23380 (Subtarget->hasSSE2() ||
23381 (Subtarget->hasSSE1() && VT.getScalarType() == MVT::f32))) {
23382 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
23384 unsigned Opcode = 0;
23385 // Check for x CC y ? x : y.
23386 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
23387 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
23391 // Converting this to a min would handle NaNs incorrectly, and swapping
23392 // the operands would cause it to handle comparisons between positive
23393 // and negative zero incorrectly.
23394 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
23395 if (!DAG.getTarget().Options.UnsafeFPMath &&
23396 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
23398 std::swap(LHS, RHS);
23400 Opcode = X86ISD::FMIN;
23403 // Converting this to a min would handle comparisons between positive
23404 // and negative zero incorrectly.
23405 if (!DAG.getTarget().Options.UnsafeFPMath &&
23406 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
23408 Opcode = X86ISD::FMIN;
23411 // Converting this to a min would handle both negative zeros and NaNs
23412 // incorrectly, but we can swap the operands to fix both.
23413 std::swap(LHS, RHS);
23417 Opcode = X86ISD::FMIN;
23421 // Converting this to a max would handle comparisons between positive
23422 // and negative zero incorrectly.
23423 if (!DAG.getTarget().Options.UnsafeFPMath &&
23424 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
23426 Opcode = X86ISD::FMAX;
23429 // Converting this to a max would handle NaNs incorrectly, and swapping
23430 // the operands would cause it to handle comparisons between positive
23431 // and negative zero incorrectly.
23432 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
23433 if (!DAG.getTarget().Options.UnsafeFPMath &&
23434 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
23436 std::swap(LHS, RHS);
23438 Opcode = X86ISD::FMAX;
23441 // Converting this to a max would handle both negative zeros and NaNs
23442 // incorrectly, but we can swap the operands to fix both.
23443 std::swap(LHS, RHS);
23447 Opcode = X86ISD::FMAX;
23450 // Check for x CC y ? y : x -- a min/max with reversed arms.
23451 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
23452 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
23456 // Converting this to a min would handle comparisons between positive
23457 // and negative zero incorrectly, and swapping the operands would
23458 // cause it to handle NaNs incorrectly.
23459 if (!DAG.getTarget().Options.UnsafeFPMath &&
23460 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) {
23461 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
23463 std::swap(LHS, RHS);
23465 Opcode = X86ISD::FMIN;
23468 // Converting this to a min would handle NaNs incorrectly.
23469 if (!DAG.getTarget().Options.UnsafeFPMath &&
23470 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
23472 Opcode = X86ISD::FMIN;
23475 // Converting this to a min would handle both negative zeros and NaNs
23476 // incorrectly, but we can swap the operands to fix both.
23477 std::swap(LHS, RHS);
23481 Opcode = X86ISD::FMIN;
23485 // Converting this to a max would handle NaNs incorrectly.
23486 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
23488 Opcode = X86ISD::FMAX;
23491 // Converting this to a max would handle comparisons between positive
23492 // and negative zero incorrectly, and swapping the operands would
23493 // cause it to handle NaNs incorrectly.
23494 if (!DAG.getTarget().Options.UnsafeFPMath &&
23495 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) {
23496 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
23498 std::swap(LHS, RHS);
23500 Opcode = X86ISD::FMAX;
23503 // Converting this to a max would handle both negative zeros and NaNs
23504 // incorrectly, but we can swap the operands to fix both.
23505 std::swap(LHS, RHS);
23509 Opcode = X86ISD::FMAX;
23515 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
23518 EVT CondVT = Cond.getValueType();
23519 if (Subtarget->hasAVX512() && VT.isVector() && CondVT.isVector() &&
23520 CondVT.getVectorElementType() == MVT::i1) {
23521 // v16i8 (select v16i1, v16i8, v16i8) does not have a proper
23522 // lowering on KNL. In this case we convert it to
23523 // v16i8 (select v16i8, v16i8, v16i8) and use AVX instruction.
23524 // The same situation for all 128 and 256-bit vectors of i8 and i16.
23525 // Since SKX these selects have a proper lowering.
23526 EVT OpVT = LHS.getValueType();
23527 if ((OpVT.is128BitVector() || OpVT.is256BitVector()) &&
23528 (OpVT.getVectorElementType() == MVT::i8 ||
23529 OpVT.getVectorElementType() == MVT::i16) &&
23530 !(Subtarget->hasBWI() && Subtarget->hasVLX())) {
23531 Cond = DAG.getNode(ISD::SIGN_EXTEND, DL, OpVT, Cond);
23532 DCI.AddToWorklist(Cond.getNode());
23533 return DAG.getNode(N->getOpcode(), DL, OpVT, Cond, LHS, RHS);
23536 // If this is a select between two integer constants, try to do some
23538 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
23539 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
23540 // Don't do this for crazy integer types.
23541 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
23542 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
23543 // so that TrueC (the true value) is larger than FalseC.
23544 bool NeedsCondInvert = false;
23546 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
23547 // Efficiently invertible.
23548 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
23549 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
23550 isa<ConstantSDNode>(Cond.getOperand(1))))) {
23551 NeedsCondInvert = true;
23552 std::swap(TrueC, FalseC);
23555 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
23556 if (FalseC->getAPIntValue() == 0 &&
23557 TrueC->getAPIntValue().isPowerOf2()) {
23558 if (NeedsCondInvert) // Invert the condition if needed.
23559 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
23560 DAG.getConstant(1, DL, Cond.getValueType()));
23562 // Zero extend the condition if needed.
23563 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
23565 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
23566 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
23567 DAG.getConstant(ShAmt, DL, MVT::i8));
23570 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
23571 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
23572 if (NeedsCondInvert) // Invert the condition if needed.
23573 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
23574 DAG.getConstant(1, DL, Cond.getValueType()));
23576 // Zero extend the condition if needed.
23577 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
23578 FalseC->getValueType(0), Cond);
23579 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
23580 SDValue(FalseC, 0));
23583 // Optimize cases that will turn into an LEA instruction. This requires
23584 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
23585 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
23586 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
23587 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
23589 bool isFastMultiplier = false;
23591 switch ((unsigned char)Diff) {
23593 case 1: // result = add base, cond
23594 case 2: // result = lea base( , cond*2)
23595 case 3: // result = lea base(cond, cond*2)
23596 case 4: // result = lea base( , cond*4)
23597 case 5: // result = lea base(cond, cond*4)
23598 case 8: // result = lea base( , cond*8)
23599 case 9: // result = lea base(cond, cond*8)
23600 isFastMultiplier = true;
23605 if (isFastMultiplier) {
23606 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
23607 if (NeedsCondInvert) // Invert the condition if needed.
23608 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
23609 DAG.getConstant(1, DL, Cond.getValueType()));
23611 // Zero extend the condition if needed.
23612 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
23614 // Scale the condition by the difference.
23616 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
23617 DAG.getConstant(Diff, DL,
23618 Cond.getValueType()));
23620 // Add the base if non-zero.
23621 if (FalseC->getAPIntValue() != 0)
23622 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
23623 SDValue(FalseC, 0));
23630 // Canonicalize max and min:
23631 // (x > y) ? x : y -> (x >= y) ? x : y
23632 // (x < y) ? x : y -> (x <= y) ? x : y
23633 // This allows use of COND_S / COND_NS (see TranslateX86CC) which eliminates
23634 // the need for an extra compare
23635 // against zero. e.g.
23636 // (x - y) > 0 : (x - y) ? 0 -> (x - y) >= 0 : (x - y) ? 0
23638 // testl %edi, %edi
23640 // cmovgl %edi, %eax
23644 // cmovsl %eax, %edi
23645 if (N->getOpcode() == ISD::SELECT && Cond.getOpcode() == ISD::SETCC &&
23646 DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
23647 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
23648 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
23653 ISD::CondCode NewCC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGE;
23654 Cond = DAG.getSetCC(SDLoc(Cond), Cond.getValueType(),
23655 Cond.getOperand(0), Cond.getOperand(1), NewCC);
23656 return DAG.getNode(ISD::SELECT, DL, VT, Cond, LHS, RHS);
23661 // Early exit check
23662 if (!TLI.isTypeLegal(VT))
23665 // Match VSELECTs into subs with unsigned saturation.
23666 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC &&
23667 // psubus is available in SSE2 and AVX2 for i8 and i16 vectors.
23668 ((Subtarget->hasSSE2() && (VT == MVT::v16i8 || VT == MVT::v8i16)) ||
23669 (Subtarget->hasAVX2() && (VT == MVT::v32i8 || VT == MVT::v16i16)))) {
23670 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
23672 // Check if one of the arms of the VSELECT is a zero vector. If it's on the
23673 // left side invert the predicate to simplify logic below.
23675 if (ISD::isBuildVectorAllZeros(LHS.getNode())) {
23677 CC = ISD::getSetCCInverse(CC, true);
23678 } else if (ISD::isBuildVectorAllZeros(RHS.getNode())) {
23682 if (Other.getNode() && Other->getNumOperands() == 2 &&
23683 DAG.isEqualTo(Other->getOperand(0), Cond.getOperand(0))) {
23684 SDValue OpLHS = Other->getOperand(0), OpRHS = Other->getOperand(1);
23685 SDValue CondRHS = Cond->getOperand(1);
23687 // Look for a general sub with unsigned saturation first.
23688 // x >= y ? x-y : 0 --> subus x, y
23689 // x > y ? x-y : 0 --> subus x, y
23690 if ((CC == ISD::SETUGE || CC == ISD::SETUGT) &&
23691 Other->getOpcode() == ISD::SUB && DAG.isEqualTo(OpRHS, CondRHS))
23692 return DAG.getNode(X86ISD::SUBUS, DL, VT, OpLHS, OpRHS);
23694 if (auto *OpRHSBV = dyn_cast<BuildVectorSDNode>(OpRHS))
23695 if (auto *OpRHSConst = OpRHSBV->getConstantSplatNode()) {
23696 if (auto *CondRHSBV = dyn_cast<BuildVectorSDNode>(CondRHS))
23697 if (auto *CondRHSConst = CondRHSBV->getConstantSplatNode())
23698 // If the RHS is a constant we have to reverse the const
23699 // canonicalization.
23700 // x > C-1 ? x+-C : 0 --> subus x, C
23701 if (CC == ISD::SETUGT && Other->getOpcode() == ISD::ADD &&
23702 CondRHSConst->getAPIntValue() ==
23703 (-OpRHSConst->getAPIntValue() - 1))
23704 return DAG.getNode(
23705 X86ISD::SUBUS, DL, VT, OpLHS,
23706 DAG.getConstant(-OpRHSConst->getAPIntValue(), DL, VT));
23708 // Another special case: If C was a sign bit, the sub has been
23709 // canonicalized into a xor.
23710 // FIXME: Would it be better to use computeKnownBits to determine
23711 // whether it's safe to decanonicalize the xor?
23712 // x s< 0 ? x^C : 0 --> subus x, C
23713 if (CC == ISD::SETLT && Other->getOpcode() == ISD::XOR &&
23714 ISD::isBuildVectorAllZeros(CondRHS.getNode()) &&
23715 OpRHSConst->getAPIntValue().isSignBit())
23716 // Note that we have to rebuild the RHS constant here to ensure we
23717 // don't rely on particular values of undef lanes.
23718 return DAG.getNode(
23719 X86ISD::SUBUS, DL, VT, OpLHS,
23720 DAG.getConstant(OpRHSConst->getAPIntValue(), DL, VT));
23725 // Simplify vector selection if condition value type matches vselect
23727 if (N->getOpcode() == ISD::VSELECT && CondVT == VT) {
23728 assert(Cond.getValueType().isVector() &&
23729 "vector select expects a vector selector!");
23731 bool TValIsAllOnes = ISD::isBuildVectorAllOnes(LHS.getNode());
23732 bool FValIsAllZeros = ISD::isBuildVectorAllZeros(RHS.getNode());
23734 // Try invert the condition if true value is not all 1s and false value
23736 if (!TValIsAllOnes && !FValIsAllZeros &&
23737 // Check if the selector will be produced by CMPP*/PCMP*
23738 Cond.getOpcode() == ISD::SETCC &&
23739 // Check if SETCC has already been promoted
23740 TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT) ==
23742 bool TValIsAllZeros = ISD::isBuildVectorAllZeros(LHS.getNode());
23743 bool FValIsAllOnes = ISD::isBuildVectorAllOnes(RHS.getNode());
23745 if (TValIsAllZeros || FValIsAllOnes) {
23746 SDValue CC = Cond.getOperand(2);
23747 ISD::CondCode NewCC =
23748 ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
23749 Cond.getOperand(0).getValueType().isInteger());
23750 Cond = DAG.getSetCC(DL, CondVT, Cond.getOperand(0), Cond.getOperand(1), NewCC);
23751 std::swap(LHS, RHS);
23752 TValIsAllOnes = FValIsAllOnes;
23753 FValIsAllZeros = TValIsAllZeros;
23757 if (TValIsAllOnes || FValIsAllZeros) {
23760 if (TValIsAllOnes && FValIsAllZeros)
23762 else if (TValIsAllOnes)
23764 DAG.getNode(ISD::OR, DL, CondVT, Cond, DAG.getBitcast(CondVT, RHS));
23765 else if (FValIsAllZeros)
23766 Ret = DAG.getNode(ISD::AND, DL, CondVT, Cond,
23767 DAG.getBitcast(CondVT, LHS));
23769 return DAG.getBitcast(VT, Ret);
23773 // We should generate an X86ISD::BLENDI from a vselect if its argument
23774 // is a sign_extend_inreg of an any_extend of a BUILD_VECTOR of
23775 // constants. This specific pattern gets generated when we split a
23776 // selector for a 512 bit vector in a machine without AVX512 (but with
23777 // 256-bit vectors), during legalization:
23779 // (vselect (sign_extend (any_extend (BUILD_VECTOR)) i1) LHS RHS)
23781 // Iff we find this pattern and the build_vectors are built from
23782 // constants, we translate the vselect into a shuffle_vector that we
23783 // know will be matched by LowerVECTOR_SHUFFLEtoBlend.
23784 if ((N->getOpcode() == ISD::VSELECT ||
23785 N->getOpcode() == X86ISD::SHRUNKBLEND) &&
23786 !DCI.isBeforeLegalize() && !VT.is512BitVector()) {
23787 SDValue Shuffle = transformVSELECTtoBlendVECTOR_SHUFFLE(N, DAG, Subtarget);
23788 if (Shuffle.getNode())
23792 // If this is a *dynamic* select (non-constant condition) and we can match
23793 // this node with one of the variable blend instructions, restructure the
23794 // condition so that the blends can use the high bit of each element and use
23795 // SimplifyDemandedBits to simplify the condition operand.
23796 if (N->getOpcode() == ISD::VSELECT && DCI.isBeforeLegalizeOps() &&
23797 !DCI.isBeforeLegalize() &&
23798 !ISD::isBuildVectorOfConstantSDNodes(Cond.getNode())) {
23799 unsigned BitWidth = Cond.getValueType().getScalarType().getSizeInBits();
23801 // Don't optimize vector selects that map to mask-registers.
23805 // We can only handle the cases where VSELECT is directly legal on the
23806 // subtarget. We custom lower VSELECT nodes with constant conditions and
23807 // this makes it hard to see whether a dynamic VSELECT will correctly
23808 // lower, so we both check the operation's status and explicitly handle the
23809 // cases where a *dynamic* blend will fail even though a constant-condition
23810 // blend could be custom lowered.
23811 // FIXME: We should find a better way to handle this class of problems.
23812 // Potentially, we should combine constant-condition vselect nodes
23813 // pre-legalization into shuffles and not mark as many types as custom
23815 if (!TLI.isOperationLegalOrCustom(ISD::VSELECT, VT))
23817 // FIXME: We don't support i16-element blends currently. We could and
23818 // should support them by making *all* the bits in the condition be set
23819 // rather than just the high bit and using an i8-element blend.
23820 if (VT.getScalarType() == MVT::i16)
23822 // Dynamic blending was only available from SSE4.1 onward.
23823 if (VT.getSizeInBits() == 128 && !Subtarget->hasSSE41())
23825 // Byte blends are only available in AVX2
23826 if (VT.getSizeInBits() == 256 && VT.getScalarType() == MVT::i8 &&
23827 !Subtarget->hasAVX2())
23830 assert(BitWidth >= 8 && BitWidth <= 64 && "Invalid mask size");
23831 APInt DemandedMask = APInt::getHighBitsSet(BitWidth, 1);
23833 APInt KnownZero, KnownOne;
23834 TargetLowering::TargetLoweringOpt TLO(DAG, DCI.isBeforeLegalize(),
23835 DCI.isBeforeLegalizeOps());
23836 if (TLO.ShrinkDemandedConstant(Cond, DemandedMask) ||
23837 TLI.SimplifyDemandedBits(Cond, DemandedMask, KnownZero, KnownOne,
23839 // If we changed the computation somewhere in the DAG, this change
23840 // will affect all users of Cond.
23841 // Make sure it is fine and update all the nodes so that we do not
23842 // use the generic VSELECT anymore. Otherwise, we may perform
23843 // wrong optimizations as we messed up with the actual expectation
23844 // for the vector boolean values.
23845 if (Cond != TLO.Old) {
23846 // Check all uses of that condition operand to check whether it will be
23847 // consumed by non-BLEND instructions, which may depend on all bits are
23849 for (SDNode::use_iterator I = Cond->use_begin(), E = Cond->use_end();
23851 if (I->getOpcode() != ISD::VSELECT)
23852 // TODO: Add other opcodes eventually lowered into BLEND.
23855 // Update all the users of the condition, before committing the change,
23856 // so that the VSELECT optimizations that expect the correct vector
23857 // boolean value will not be triggered.
23858 for (SDNode::use_iterator I = Cond->use_begin(), E = Cond->use_end();
23860 DAG.ReplaceAllUsesOfValueWith(
23862 DAG.getNode(X86ISD::SHRUNKBLEND, SDLoc(*I), I->getValueType(0),
23863 Cond, I->getOperand(1), I->getOperand(2)));
23864 DCI.CommitTargetLoweringOpt(TLO);
23867 // At this point, only Cond is changed. Change the condition
23868 // just for N to keep the opportunity to optimize all other
23869 // users their own way.
23870 DAG.ReplaceAllUsesOfValueWith(
23872 DAG.getNode(X86ISD::SHRUNKBLEND, SDLoc(N), N->getValueType(0),
23873 TLO.New, N->getOperand(1), N->getOperand(2)));
23881 // Check whether a boolean test is testing a boolean value generated by
23882 // X86ISD::SETCC. If so, return the operand of that SETCC and proper condition
23885 // Simplify the following patterns:
23886 // (Op (CMP (SETCC Cond EFLAGS) 1) EQ) or
23887 // (Op (CMP (SETCC Cond EFLAGS) 0) NEQ)
23888 // to (Op EFLAGS Cond)
23890 // (Op (CMP (SETCC Cond EFLAGS) 0) EQ) or
23891 // (Op (CMP (SETCC Cond EFLAGS) 1) NEQ)
23892 // to (Op EFLAGS !Cond)
23894 // where Op could be BRCOND or CMOV.
23896 static SDValue checkBoolTestSetCCCombine(SDValue Cmp, X86::CondCode &CC) {
23897 // Quit if not CMP and SUB with its value result used.
23898 if (Cmp.getOpcode() != X86ISD::CMP &&
23899 (Cmp.getOpcode() != X86ISD::SUB || Cmp.getNode()->hasAnyUseOfValue(0)))
23902 // Quit if not used as a boolean value.
23903 if (CC != X86::COND_E && CC != X86::COND_NE)
23906 // Check CMP operands. One of them should be 0 or 1 and the other should be
23907 // an SetCC or extended from it.
23908 SDValue Op1 = Cmp.getOperand(0);
23909 SDValue Op2 = Cmp.getOperand(1);
23912 const ConstantSDNode* C = nullptr;
23913 bool needOppositeCond = (CC == X86::COND_E);
23914 bool checkAgainstTrue = false; // Is it a comparison against 1?
23916 if ((C = dyn_cast<ConstantSDNode>(Op1)))
23918 else if ((C = dyn_cast<ConstantSDNode>(Op2)))
23920 else // Quit if all operands are not constants.
23923 if (C->getZExtValue() == 1) {
23924 needOppositeCond = !needOppositeCond;
23925 checkAgainstTrue = true;
23926 } else if (C->getZExtValue() != 0)
23927 // Quit if the constant is neither 0 or 1.
23930 bool truncatedToBoolWithAnd = false;
23931 // Skip (zext $x), (trunc $x), or (and $x, 1) node.
23932 while (SetCC.getOpcode() == ISD::ZERO_EXTEND ||
23933 SetCC.getOpcode() == ISD::TRUNCATE ||
23934 SetCC.getOpcode() == ISD::AND) {
23935 if (SetCC.getOpcode() == ISD::AND) {
23937 ConstantSDNode *CS;
23938 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(0))) &&
23939 CS->getZExtValue() == 1)
23941 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(1))) &&
23942 CS->getZExtValue() == 1)
23946 SetCC = SetCC.getOperand(OpIdx);
23947 truncatedToBoolWithAnd = true;
23949 SetCC = SetCC.getOperand(0);
23952 switch (SetCC.getOpcode()) {
23953 case X86ISD::SETCC_CARRY:
23954 // Since SETCC_CARRY gives output based on R = CF ? ~0 : 0, it's unsafe to
23955 // simplify it if the result of SETCC_CARRY is not canonicalized to 0 or 1,
23956 // i.e. it's a comparison against true but the result of SETCC_CARRY is not
23957 // truncated to i1 using 'and'.
23958 if (checkAgainstTrue && !truncatedToBoolWithAnd)
23960 assert(X86::CondCode(SetCC.getConstantOperandVal(0)) == X86::COND_B &&
23961 "Invalid use of SETCC_CARRY!");
23963 case X86ISD::SETCC:
23964 // Set the condition code or opposite one if necessary.
23965 CC = X86::CondCode(SetCC.getConstantOperandVal(0));
23966 if (needOppositeCond)
23967 CC = X86::GetOppositeBranchCondition(CC);
23968 return SetCC.getOperand(1);
23969 case X86ISD::CMOV: {
23970 // Check whether false/true value has canonical one, i.e. 0 or 1.
23971 ConstantSDNode *FVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(0));
23972 ConstantSDNode *TVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(1));
23973 // Quit if true value is not a constant.
23976 // Quit if false value is not a constant.
23978 SDValue Op = SetCC.getOperand(0);
23979 // Skip 'zext' or 'trunc' node.
23980 if (Op.getOpcode() == ISD::ZERO_EXTEND ||
23981 Op.getOpcode() == ISD::TRUNCATE)
23982 Op = Op.getOperand(0);
23983 // A special case for rdrand/rdseed, where 0 is set if false cond is
23985 if ((Op.getOpcode() != X86ISD::RDRAND &&
23986 Op.getOpcode() != X86ISD::RDSEED) || Op.getResNo() != 0)
23989 // Quit if false value is not the constant 0 or 1.
23990 bool FValIsFalse = true;
23991 if (FVal && FVal->getZExtValue() != 0) {
23992 if (FVal->getZExtValue() != 1)
23994 // If FVal is 1, opposite cond is needed.
23995 needOppositeCond = !needOppositeCond;
23996 FValIsFalse = false;
23998 // Quit if TVal is not the constant opposite of FVal.
23999 if (FValIsFalse && TVal->getZExtValue() != 1)
24001 if (!FValIsFalse && TVal->getZExtValue() != 0)
24003 CC = X86::CondCode(SetCC.getConstantOperandVal(2));
24004 if (needOppositeCond)
24005 CC = X86::GetOppositeBranchCondition(CC);
24006 return SetCC.getOperand(3);
24013 /// Check whether Cond is an AND/OR of SETCCs off of the same EFLAGS.
24015 /// (X86or (X86setcc) (X86setcc))
24016 /// (X86cmp (and (X86setcc) (X86setcc)), 0)
24017 static bool checkBoolTestAndOrSetCCCombine(SDValue Cond, X86::CondCode &CC0,
24018 X86::CondCode &CC1, SDValue &Flags,
24020 if (Cond->getOpcode() == X86ISD::CMP) {
24021 ConstantSDNode *CondOp1C = dyn_cast<ConstantSDNode>(Cond->getOperand(1));
24022 if (!CondOp1C || !CondOp1C->isNullValue())
24025 Cond = Cond->getOperand(0);
24030 SDValue SetCC0, SetCC1;
24031 switch (Cond->getOpcode()) {
24032 default: return false;
24039 SetCC0 = Cond->getOperand(0);
24040 SetCC1 = Cond->getOperand(1);
24044 // Make sure we have SETCC nodes, using the same flags value.
24045 if (SetCC0.getOpcode() != X86ISD::SETCC ||
24046 SetCC1.getOpcode() != X86ISD::SETCC ||
24047 SetCC0->getOperand(1) != SetCC1->getOperand(1))
24050 CC0 = (X86::CondCode)SetCC0->getConstantOperandVal(0);
24051 CC1 = (X86::CondCode)SetCC1->getConstantOperandVal(0);
24052 Flags = SetCC0->getOperand(1);
24056 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
24057 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
24058 TargetLowering::DAGCombinerInfo &DCI,
24059 const X86Subtarget *Subtarget) {
24062 // If the flag operand isn't dead, don't touch this CMOV.
24063 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
24066 SDValue FalseOp = N->getOperand(0);
24067 SDValue TrueOp = N->getOperand(1);
24068 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
24069 SDValue Cond = N->getOperand(3);
24071 if (CC == X86::COND_E || CC == X86::COND_NE) {
24072 switch (Cond.getOpcode()) {
24076 // If operand of BSR / BSF are proven never zero, then ZF cannot be set.
24077 if (DAG.isKnownNeverZero(Cond.getOperand(0)))
24078 return (CC == X86::COND_E) ? FalseOp : TrueOp;
24084 Flags = checkBoolTestSetCCCombine(Cond, CC);
24085 if (Flags.getNode() &&
24086 // Extra check as FCMOV only supports a subset of X86 cond.
24087 (FalseOp.getValueType() != MVT::f80 || hasFPCMov(CC))) {
24088 SDValue Ops[] = { FalseOp, TrueOp,
24089 DAG.getConstant(CC, DL, MVT::i8), Flags };
24090 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), Ops);
24093 // If this is a select between two integer constants, try to do some
24094 // optimizations. Note that the operands are ordered the opposite of SELECT
24096 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(TrueOp)) {
24097 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(FalseOp)) {
24098 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
24099 // larger than FalseC (the false value).
24100 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
24101 CC = X86::GetOppositeBranchCondition(CC);
24102 std::swap(TrueC, FalseC);
24103 std::swap(TrueOp, FalseOp);
24106 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
24107 // This is efficient for any integer data type (including i8/i16) and
24109 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
24110 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
24111 DAG.getConstant(CC, DL, MVT::i8), Cond);
24113 // Zero extend the condition if needed.
24114 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
24116 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
24117 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
24118 DAG.getConstant(ShAmt, DL, MVT::i8));
24119 if (N->getNumValues() == 2) // Dead flag value?
24120 return DCI.CombineTo(N, Cond, SDValue());
24124 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
24125 // for any integer data type, including i8/i16.
24126 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
24127 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
24128 DAG.getConstant(CC, DL, MVT::i8), Cond);
24130 // Zero extend the condition if needed.
24131 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
24132 FalseC->getValueType(0), Cond);
24133 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
24134 SDValue(FalseC, 0));
24136 if (N->getNumValues() == 2) // Dead flag value?
24137 return DCI.CombineTo(N, Cond, SDValue());
24141 // Optimize cases that will turn into an LEA instruction. This requires
24142 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
24143 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
24144 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
24145 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
24147 bool isFastMultiplier = false;
24149 switch ((unsigned char)Diff) {
24151 case 1: // result = add base, cond
24152 case 2: // result = lea base( , cond*2)
24153 case 3: // result = lea base(cond, cond*2)
24154 case 4: // result = lea base( , cond*4)
24155 case 5: // result = lea base(cond, cond*4)
24156 case 8: // result = lea base( , cond*8)
24157 case 9: // result = lea base(cond, cond*8)
24158 isFastMultiplier = true;
24163 if (isFastMultiplier) {
24164 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
24165 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
24166 DAG.getConstant(CC, DL, MVT::i8), Cond);
24167 // Zero extend the condition if needed.
24168 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
24170 // Scale the condition by the difference.
24172 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
24173 DAG.getConstant(Diff, DL, Cond.getValueType()));
24175 // Add the base if non-zero.
24176 if (FalseC->getAPIntValue() != 0)
24177 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
24178 SDValue(FalseC, 0));
24179 if (N->getNumValues() == 2) // Dead flag value?
24180 return DCI.CombineTo(N, Cond, SDValue());
24187 // Handle these cases:
24188 // (select (x != c), e, c) -> select (x != c), e, x),
24189 // (select (x == c), c, e) -> select (x == c), x, e)
24190 // where the c is an integer constant, and the "select" is the combination
24191 // of CMOV and CMP.
24193 // The rationale for this change is that the conditional-move from a constant
24194 // needs two instructions, however, conditional-move from a register needs
24195 // only one instruction.
24197 // CAVEAT: By replacing a constant with a symbolic value, it may obscure
24198 // some instruction-combining opportunities. This opt needs to be
24199 // postponed as late as possible.
24201 if (!DCI.isBeforeLegalize() && !DCI.isBeforeLegalizeOps()) {
24202 // the DCI.xxxx conditions are provided to postpone the optimization as
24203 // late as possible.
24205 ConstantSDNode *CmpAgainst = nullptr;
24206 if ((Cond.getOpcode() == X86ISD::CMP || Cond.getOpcode() == X86ISD::SUB) &&
24207 (CmpAgainst = dyn_cast<ConstantSDNode>(Cond.getOperand(1))) &&
24208 !isa<ConstantSDNode>(Cond.getOperand(0))) {
24210 if (CC == X86::COND_NE &&
24211 CmpAgainst == dyn_cast<ConstantSDNode>(FalseOp)) {
24212 CC = X86::GetOppositeBranchCondition(CC);
24213 std::swap(TrueOp, FalseOp);
24216 if (CC == X86::COND_E &&
24217 CmpAgainst == dyn_cast<ConstantSDNode>(TrueOp)) {
24218 SDValue Ops[] = { FalseOp, Cond.getOperand(0),
24219 DAG.getConstant(CC, DL, MVT::i8), Cond };
24220 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList (), Ops);
24225 // Fold and/or of setcc's to double CMOV:
24226 // (CMOV F, T, ((cc1 | cc2) != 0)) -> (CMOV (CMOV F, T, cc1), T, cc2)
24227 // (CMOV F, T, ((cc1 & cc2) != 0)) -> (CMOV (CMOV T, F, !cc1), F, !cc2)
24229 // This combine lets us generate:
24230 // cmovcc1 (jcc1 if we don't have CMOV)
24236 // cmovne (jne if we don't have CMOV)
24237 // When we can't use the CMOV instruction, it might increase branch
24239 // When we can use CMOV, or when there is no mispredict, this improves
24240 // throughput and reduces register pressure.
24242 if (CC == X86::COND_NE) {
24244 X86::CondCode CC0, CC1;
24246 if (checkBoolTestAndOrSetCCCombine(Cond, CC0, CC1, Flags, isAndSetCC)) {
24248 std::swap(FalseOp, TrueOp);
24249 CC0 = X86::GetOppositeBranchCondition(CC0);
24250 CC1 = X86::GetOppositeBranchCondition(CC1);
24253 SDValue LOps[] = {FalseOp, TrueOp, DAG.getConstant(CC0, DL, MVT::i8),
24255 SDValue LCMOV = DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), LOps);
24256 SDValue Ops[] = {LCMOV, TrueOp, DAG.getConstant(CC1, DL, MVT::i8), Flags};
24257 SDValue CMOV = DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), Ops);
24258 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), SDValue(CMOV.getNode(), 1));
24266 /// PerformMulCombine - Optimize a single multiply with constant into two
24267 /// in order to implement it with two cheaper instructions, e.g.
24268 /// LEA + SHL, LEA + LEA.
24269 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
24270 TargetLowering::DAGCombinerInfo &DCI) {
24271 // An imul is usually smaller than the alternative sequence.
24272 if (DAG.getMachineFunction().getFunction()->optForMinSize())
24275 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
24278 EVT VT = N->getValueType(0);
24279 if (VT != MVT::i64 && VT != MVT::i32)
24282 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
24285 uint64_t MulAmt = C->getZExtValue();
24286 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
24289 uint64_t MulAmt1 = 0;
24290 uint64_t MulAmt2 = 0;
24291 if ((MulAmt % 9) == 0) {
24293 MulAmt2 = MulAmt / 9;
24294 } else if ((MulAmt % 5) == 0) {
24296 MulAmt2 = MulAmt / 5;
24297 } else if ((MulAmt % 3) == 0) {
24299 MulAmt2 = MulAmt / 3;
24302 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
24305 if (isPowerOf2_64(MulAmt2) &&
24306 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
24307 // If second multiplifer is pow2, issue it first. We want the multiply by
24308 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
24310 std::swap(MulAmt1, MulAmt2);
24313 if (isPowerOf2_64(MulAmt1))
24314 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
24315 DAG.getConstant(Log2_64(MulAmt1), DL, MVT::i8));
24317 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
24318 DAG.getConstant(MulAmt1, DL, VT));
24320 if (isPowerOf2_64(MulAmt2))
24321 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
24322 DAG.getConstant(Log2_64(MulAmt2), DL, MVT::i8));
24324 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
24325 DAG.getConstant(MulAmt2, DL, VT));
24327 // Do not add new nodes to DAG combiner worklist.
24328 DCI.CombineTo(N, NewMul, false);
24333 static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) {
24334 SDValue N0 = N->getOperand(0);
24335 SDValue N1 = N->getOperand(1);
24336 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
24337 EVT VT = N0.getValueType();
24339 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2))
24340 // since the result of setcc_c is all zero's or all ones.
24341 if (VT.isInteger() && !VT.isVector() &&
24342 N1C && N0.getOpcode() == ISD::AND &&
24343 N0.getOperand(1).getOpcode() == ISD::Constant) {
24344 SDValue N00 = N0.getOperand(0);
24345 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
24346 APInt ShAmt = N1C->getAPIntValue();
24347 Mask = Mask.shl(ShAmt);
24348 bool MaskOK = false;
24349 // We can handle cases concerning bit-widening nodes containing setcc_c if
24350 // we carefully interrogate the mask to make sure we are semantics
24352 // The transform is not safe if the result of C1 << C2 exceeds the bitwidth
24353 // of the underlying setcc_c operation if the setcc_c was zero extended.
24354 // Consider the following example:
24355 // zext(setcc_c) -> i32 0x0000FFFF
24356 // c1 -> i32 0x0000FFFF
24357 // c2 -> i32 0x00000001
24358 // (shl (and (setcc_c), c1), c2) -> i32 0x0001FFFE
24359 // (and setcc_c, (c1 << c2)) -> i32 0x0000FFFE
24360 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
24362 } else if (N00.getOpcode() == ISD::SIGN_EXTEND &&
24363 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
24365 } else if ((N00.getOpcode() == ISD::ZERO_EXTEND ||
24366 N00.getOpcode() == ISD::ANY_EXTEND) &&
24367 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
24368 MaskOK = Mask.isIntN(N00.getOperand(0).getValueSizeInBits());
24370 if (MaskOK && Mask != 0) {
24372 return DAG.getNode(ISD::AND, DL, VT, N00, DAG.getConstant(Mask, DL, VT));
24376 // Hardware support for vector shifts is sparse which makes us scalarize the
24377 // vector operations in many cases. Also, on sandybridge ADD is faster than
24379 // (shl V, 1) -> add V,V
24380 if (auto *N1BV = dyn_cast<BuildVectorSDNode>(N1))
24381 if (auto *N1SplatC = N1BV->getConstantSplatNode()) {
24382 assert(N0.getValueType().isVector() && "Invalid vector shift type");
24383 // We shift all of the values by one. In many cases we do not have
24384 // hardware support for this operation. This is better expressed as an ADD
24386 if (N1SplatC->getAPIntValue() == 1)
24387 return DAG.getNode(ISD::ADD, SDLoc(N), VT, N0, N0);
24393 /// \brief Returns a vector of 0s if the node in input is a vector logical
24394 /// shift by a constant amount which is known to be bigger than or equal
24395 /// to the vector element size in bits.
24396 static SDValue performShiftToAllZeros(SDNode *N, SelectionDAG &DAG,
24397 const X86Subtarget *Subtarget) {
24398 EVT VT = N->getValueType(0);
24400 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16 &&
24401 (!Subtarget->hasInt256() ||
24402 (VT != MVT::v4i64 && VT != MVT::v8i32 && VT != MVT::v16i16)))
24405 SDValue Amt = N->getOperand(1);
24407 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Amt))
24408 if (auto *AmtSplat = AmtBV->getConstantSplatNode()) {
24409 APInt ShiftAmt = AmtSplat->getAPIntValue();
24410 unsigned MaxAmount =
24411 VT.getSimpleVT().getVectorElementType().getSizeInBits();
24413 // SSE2/AVX2 logical shifts always return a vector of 0s
24414 // if the shift amount is bigger than or equal to
24415 // the element size. The constant shift amount will be
24416 // encoded as a 8-bit immediate.
24417 if (ShiftAmt.trunc(8).uge(MaxAmount))
24418 return getZeroVector(VT, Subtarget, DAG, DL);
24424 /// PerformShiftCombine - Combine shifts.
24425 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
24426 TargetLowering::DAGCombinerInfo &DCI,
24427 const X86Subtarget *Subtarget) {
24428 if (N->getOpcode() == ISD::SHL)
24429 if (SDValue V = PerformSHLCombine(N, DAG))
24432 // Try to fold this logical shift into a zero vector.
24433 if (N->getOpcode() != ISD::SRA)
24434 if (SDValue V = performShiftToAllZeros(N, DAG, Subtarget))
24440 // CMPEQCombine - Recognize the distinctive (AND (setcc ...) (setcc ..))
24441 // where both setccs reference the same FP CMP, and rewrite for CMPEQSS
24442 // and friends. Likewise for OR -> CMPNEQSS.
24443 static SDValue CMPEQCombine(SDNode *N, SelectionDAG &DAG,
24444 TargetLowering::DAGCombinerInfo &DCI,
24445 const X86Subtarget *Subtarget) {
24448 // SSE1 supports CMP{eq|ne}SS, and SSE2 added CMP{eq|ne}SD, but
24449 // we're requiring SSE2 for both.
24450 if (Subtarget->hasSSE2() && isAndOrOfSetCCs(SDValue(N, 0U), opcode)) {
24451 SDValue N0 = N->getOperand(0);
24452 SDValue N1 = N->getOperand(1);
24453 SDValue CMP0 = N0->getOperand(1);
24454 SDValue CMP1 = N1->getOperand(1);
24457 // The SETCCs should both refer to the same CMP.
24458 if (CMP0.getOpcode() != X86ISD::CMP || CMP0 != CMP1)
24461 SDValue CMP00 = CMP0->getOperand(0);
24462 SDValue CMP01 = CMP0->getOperand(1);
24463 EVT VT = CMP00.getValueType();
24465 if (VT == MVT::f32 || VT == MVT::f64) {
24466 bool ExpectingFlags = false;
24467 // Check for any users that want flags:
24468 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
24469 !ExpectingFlags && UI != UE; ++UI)
24470 switch (UI->getOpcode()) {
24475 ExpectingFlags = true;
24477 case ISD::CopyToReg:
24478 case ISD::SIGN_EXTEND:
24479 case ISD::ZERO_EXTEND:
24480 case ISD::ANY_EXTEND:
24484 if (!ExpectingFlags) {
24485 enum X86::CondCode cc0 = (enum X86::CondCode)N0.getConstantOperandVal(0);
24486 enum X86::CondCode cc1 = (enum X86::CondCode)N1.getConstantOperandVal(0);
24488 if (cc1 == X86::COND_E || cc1 == X86::COND_NE) {
24489 X86::CondCode tmp = cc0;
24494 if ((cc0 == X86::COND_E && cc1 == X86::COND_NP) ||
24495 (cc0 == X86::COND_NE && cc1 == X86::COND_P)) {
24496 // FIXME: need symbolic constants for these magic numbers.
24497 // See X86ATTInstPrinter.cpp:printSSECC().
24498 unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4;
24499 if (Subtarget->hasAVX512()) {
24500 SDValue FSetCC = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CMP00,
24502 DAG.getConstant(x86cc, DL, MVT::i8));
24503 if (N->getValueType(0) != MVT::i1)
24504 return DAG.getNode(ISD::ZERO_EXTEND, DL, N->getValueType(0),
24508 SDValue OnesOrZeroesF = DAG.getNode(X86ISD::FSETCC, DL,
24509 CMP00.getValueType(), CMP00, CMP01,
24510 DAG.getConstant(x86cc, DL,
24513 bool is64BitFP = (CMP00.getValueType() == MVT::f64);
24514 MVT IntVT = is64BitFP ? MVT::i64 : MVT::i32;
24516 if (is64BitFP && !Subtarget->is64Bit()) {
24517 // On a 32-bit target, we cannot bitcast the 64-bit float to a
24518 // 64-bit integer, since that's not a legal type. Since
24519 // OnesOrZeroesF is all ones of all zeroes, we don't need all the
24520 // bits, but can do this little dance to extract the lowest 32 bits
24521 // and work with those going forward.
24522 SDValue Vector64 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2f64,
24524 SDValue Vector32 = DAG.getBitcast(MVT::v4f32, Vector64);
24525 OnesOrZeroesF = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32,
24526 Vector32, DAG.getIntPtrConstant(0, DL));
24530 SDValue OnesOrZeroesI = DAG.getBitcast(IntVT, OnesOrZeroesF);
24531 SDValue ANDed = DAG.getNode(ISD::AND, DL, IntVT, OnesOrZeroesI,
24532 DAG.getConstant(1, DL, IntVT));
24533 SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8,
24535 return OneBitOfTruth;
24543 /// CanFoldXORWithAllOnes - Test whether the XOR operand is a AllOnes vector
24544 /// so it can be folded inside ANDNP.
24545 static bool CanFoldXORWithAllOnes(const SDNode *N) {
24546 EVT VT = N->getValueType(0);
24548 // Match direct AllOnes for 128 and 256-bit vectors
24549 if (ISD::isBuildVectorAllOnes(N))
24552 // Look through a bit convert.
24553 if (N->getOpcode() == ISD::BITCAST)
24554 N = N->getOperand(0).getNode();
24556 // Sometimes the operand may come from a insert_subvector building a 256-bit
24558 if (VT.is256BitVector() &&
24559 N->getOpcode() == ISD::INSERT_SUBVECTOR) {
24560 SDValue V1 = N->getOperand(0);
24561 SDValue V2 = N->getOperand(1);
24563 if (V1.getOpcode() == ISD::INSERT_SUBVECTOR &&
24564 V1.getOperand(0).getOpcode() == ISD::UNDEF &&
24565 ISD::isBuildVectorAllOnes(V1.getOperand(1).getNode()) &&
24566 ISD::isBuildVectorAllOnes(V2.getNode()))
24573 // On AVX/AVX2 the type v8i1 is legalized to v8i16, which is an XMM sized
24574 // register. In most cases we actually compare or select YMM-sized registers
24575 // and mixing the two types creates horrible code. This method optimizes
24576 // some of the transition sequences.
24577 static SDValue WidenMaskArithmetic(SDNode *N, SelectionDAG &DAG,
24578 TargetLowering::DAGCombinerInfo &DCI,
24579 const X86Subtarget *Subtarget) {
24580 EVT VT = N->getValueType(0);
24581 if (!VT.is256BitVector())
24584 assert((N->getOpcode() == ISD::ANY_EXTEND ||
24585 N->getOpcode() == ISD::ZERO_EXTEND ||
24586 N->getOpcode() == ISD::SIGN_EXTEND) && "Invalid Node");
24588 SDValue Narrow = N->getOperand(0);
24589 EVT NarrowVT = Narrow->getValueType(0);
24590 if (!NarrowVT.is128BitVector())
24593 if (Narrow->getOpcode() != ISD::XOR &&
24594 Narrow->getOpcode() != ISD::AND &&
24595 Narrow->getOpcode() != ISD::OR)
24598 SDValue N0 = Narrow->getOperand(0);
24599 SDValue N1 = Narrow->getOperand(1);
24602 // The Left side has to be a trunc.
24603 if (N0.getOpcode() != ISD::TRUNCATE)
24606 // The type of the truncated inputs.
24607 EVT WideVT = N0->getOperand(0)->getValueType(0);
24611 // The right side has to be a 'trunc' or a constant vector.
24612 bool RHSTrunc = N1.getOpcode() == ISD::TRUNCATE;
24613 ConstantSDNode *RHSConstSplat = nullptr;
24614 if (auto *RHSBV = dyn_cast<BuildVectorSDNode>(N1))
24615 RHSConstSplat = RHSBV->getConstantSplatNode();
24616 if (!RHSTrunc && !RHSConstSplat)
24619 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
24621 if (!TLI.isOperationLegalOrPromote(Narrow->getOpcode(), WideVT))
24624 // Set N0 and N1 to hold the inputs to the new wide operation.
24625 N0 = N0->getOperand(0);
24626 if (RHSConstSplat) {
24627 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, WideVT.getScalarType(),
24628 SDValue(RHSConstSplat, 0));
24629 SmallVector<SDValue, 8> C(WideVT.getVectorNumElements(), N1);
24630 N1 = DAG.getNode(ISD::BUILD_VECTOR, DL, WideVT, C);
24631 } else if (RHSTrunc) {
24632 N1 = N1->getOperand(0);
24635 // Generate the wide operation.
24636 SDValue Op = DAG.getNode(Narrow->getOpcode(), DL, WideVT, N0, N1);
24637 unsigned Opcode = N->getOpcode();
24639 case ISD::ANY_EXTEND:
24641 case ISD::ZERO_EXTEND: {
24642 unsigned InBits = NarrowVT.getScalarType().getSizeInBits();
24643 APInt Mask = APInt::getAllOnesValue(InBits);
24644 Mask = Mask.zext(VT.getScalarType().getSizeInBits());
24645 return DAG.getNode(ISD::AND, DL, VT,
24646 Op, DAG.getConstant(Mask, DL, VT));
24648 case ISD::SIGN_EXTEND:
24649 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT,
24650 Op, DAG.getValueType(NarrowVT));
24652 llvm_unreachable("Unexpected opcode");
24656 static SDValue VectorZextCombine(SDNode *N, SelectionDAG &DAG,
24657 TargetLowering::DAGCombinerInfo &DCI,
24658 const X86Subtarget *Subtarget) {
24659 SDValue N0 = N->getOperand(0);
24660 SDValue N1 = N->getOperand(1);
24663 // A vector zext_in_reg may be represented as a shuffle,
24664 // feeding into a bitcast (this represents anyext) feeding into
24665 // an and with a mask.
24666 // We'd like to try to combine that into a shuffle with zero
24667 // plus a bitcast, removing the and.
24668 if (N0.getOpcode() != ISD::BITCAST ||
24669 N0.getOperand(0).getOpcode() != ISD::VECTOR_SHUFFLE)
24672 // The other side of the AND should be a splat of 2^C, where C
24673 // is the number of bits in the source type.
24674 if (N1.getOpcode() == ISD::BITCAST)
24675 N1 = N1.getOperand(0);
24676 if (N1.getOpcode() != ISD::BUILD_VECTOR)
24678 BuildVectorSDNode *Vector = cast<BuildVectorSDNode>(N1);
24680 ShuffleVectorSDNode *Shuffle = cast<ShuffleVectorSDNode>(N0.getOperand(0));
24681 EVT SrcType = Shuffle->getValueType(0);
24683 // We expect a single-source shuffle
24684 if (Shuffle->getOperand(1)->getOpcode() != ISD::UNDEF)
24687 unsigned SrcSize = SrcType.getScalarSizeInBits();
24689 APInt SplatValue, SplatUndef;
24690 unsigned SplatBitSize;
24692 if (!Vector->isConstantSplat(SplatValue, SplatUndef,
24693 SplatBitSize, HasAnyUndefs))
24696 unsigned ResSize = N1.getValueType().getScalarSizeInBits();
24697 // Make sure the splat matches the mask we expect
24698 if (SplatBitSize > ResSize ||
24699 (SplatValue + 1).exactLogBase2() != (int)SrcSize)
24702 // Make sure the input and output size make sense
24703 if (SrcSize >= ResSize || ResSize % SrcSize)
24706 // We expect a shuffle of the form <0, u, u, u, 1, u, u, u...>
24707 // The number of u's between each two values depends on the ratio between
24708 // the source and dest type.
24709 unsigned ZextRatio = ResSize / SrcSize;
24710 bool IsZext = true;
24711 for (unsigned i = 0; i < SrcType.getVectorNumElements(); ++i) {
24712 if (i % ZextRatio) {
24713 if (Shuffle->getMaskElt(i) > 0) {
24719 if (Shuffle->getMaskElt(i) != (int)(i / ZextRatio)) {
24720 // Expected element number
24730 // Ok, perform the transformation - replace the shuffle with
24731 // a shuffle of the form <0, k, k, k, 1, k, k, k> with zero
24732 // (instead of undef) where the k elements come from the zero vector.
24733 SmallVector<int, 8> Mask;
24734 unsigned NumElems = SrcType.getVectorNumElements();
24735 for (unsigned i = 0; i < NumElems; ++i)
24737 Mask.push_back(NumElems);
24739 Mask.push_back(i / ZextRatio);
24741 SDValue NewShuffle = DAG.getVectorShuffle(Shuffle->getValueType(0), DL,
24742 Shuffle->getOperand(0), DAG.getConstant(0, DL, SrcType), Mask);
24743 return DAG.getBitcast(N0.getValueType(), NewShuffle);
24746 /// If both input operands of a logic op are being cast from floating point
24747 /// types, try to convert this into a floating point logic node to avoid
24748 /// unnecessary moves from SSE to integer registers.
24749 static SDValue convertIntLogicToFPLogic(SDNode *N, SelectionDAG &DAG,
24750 const X86Subtarget *Subtarget) {
24751 unsigned FPOpcode = ISD::DELETED_NODE;
24752 if (N->getOpcode() == ISD::AND)
24753 FPOpcode = X86ISD::FAND;
24754 else if (N->getOpcode() == ISD::OR)
24755 FPOpcode = X86ISD::FOR;
24756 else if (N->getOpcode() == ISD::XOR)
24757 FPOpcode = X86ISD::FXOR;
24759 assert(FPOpcode != ISD::DELETED_NODE &&
24760 "Unexpected input node for FP logic conversion");
24762 EVT VT = N->getValueType(0);
24763 SDValue N0 = N->getOperand(0);
24764 SDValue N1 = N->getOperand(1);
24766 if (N0.getOpcode() == ISD::BITCAST && N1.getOpcode() == ISD::BITCAST &&
24767 ((Subtarget->hasSSE1() && VT == MVT::i32) ||
24768 (Subtarget->hasSSE2() && VT == MVT::i64))) {
24769 SDValue N00 = N0.getOperand(0);
24770 SDValue N10 = N1.getOperand(0);
24771 EVT N00Type = N00.getValueType();
24772 EVT N10Type = N10.getValueType();
24773 if (N00Type.isFloatingPoint() && N10Type.isFloatingPoint()) {
24774 SDValue FPLogic = DAG.getNode(FPOpcode, DL, N00Type, N00, N10);
24775 return DAG.getBitcast(VT, FPLogic);
24781 static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG,
24782 TargetLowering::DAGCombinerInfo &DCI,
24783 const X86Subtarget *Subtarget) {
24784 if (DCI.isBeforeLegalizeOps())
24787 if (SDValue Zext = VectorZextCombine(N, DAG, DCI, Subtarget))
24790 if (SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget))
24793 if (SDValue FPLogic = convertIntLogicToFPLogic(N, DAG, Subtarget))
24796 EVT VT = N->getValueType(0);
24797 SDValue N0 = N->getOperand(0);
24798 SDValue N1 = N->getOperand(1);
24801 // Create BEXTR instructions
24802 // BEXTR is ((X >> imm) & (2**size-1))
24803 if (VT == MVT::i32 || VT == MVT::i64) {
24804 // Check for BEXTR.
24805 if ((Subtarget->hasBMI() || Subtarget->hasTBM()) &&
24806 (N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::SRL)) {
24807 ConstantSDNode *MaskNode = dyn_cast<ConstantSDNode>(N1);
24808 ConstantSDNode *ShiftNode = dyn_cast<ConstantSDNode>(N0.getOperand(1));
24809 if (MaskNode && ShiftNode) {
24810 uint64_t Mask = MaskNode->getZExtValue();
24811 uint64_t Shift = ShiftNode->getZExtValue();
24812 if (isMask_64(Mask)) {
24813 uint64_t MaskSize = countPopulation(Mask);
24814 if (Shift + MaskSize <= VT.getSizeInBits())
24815 return DAG.getNode(X86ISD::BEXTR, DL, VT, N0.getOperand(0),
24816 DAG.getConstant(Shift | (MaskSize << 8), DL,
24825 // Want to form ANDNP nodes:
24826 // 1) In the hopes of then easily combining them with OR and AND nodes
24827 // to form PBLEND/PSIGN.
24828 // 2) To match ANDN packed intrinsics
24829 if (VT != MVT::v2i64 && VT != MVT::v4i64)
24832 // Check LHS for vnot
24833 if (N0.getOpcode() == ISD::XOR &&
24834 //ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode()))
24835 CanFoldXORWithAllOnes(N0.getOperand(1).getNode()))
24836 return DAG.getNode(X86ISD::ANDNP, DL, VT, N0.getOperand(0), N1);
24838 // Check RHS for vnot
24839 if (N1.getOpcode() == ISD::XOR &&
24840 //ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode()))
24841 CanFoldXORWithAllOnes(N1.getOperand(1).getNode()))
24842 return DAG.getNode(X86ISD::ANDNP, DL, VT, N1.getOperand(0), N0);
24847 static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
24848 TargetLowering::DAGCombinerInfo &DCI,
24849 const X86Subtarget *Subtarget) {
24850 if (DCI.isBeforeLegalizeOps())
24853 if (SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget))
24856 if (SDValue FPLogic = convertIntLogicToFPLogic(N, DAG, Subtarget))
24859 SDValue N0 = N->getOperand(0);
24860 SDValue N1 = N->getOperand(1);
24861 EVT VT = N->getValueType(0);
24863 // look for psign/blend
24864 if (VT == MVT::v2i64 || VT == MVT::v4i64) {
24865 if (!Subtarget->hasSSSE3() ||
24866 (VT == MVT::v4i64 && !Subtarget->hasInt256()))
24869 // Canonicalize pandn to RHS
24870 if (N0.getOpcode() == X86ISD::ANDNP)
24872 // or (and (m, y), (pandn m, x))
24873 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::ANDNP) {
24874 SDValue Mask = N1.getOperand(0);
24875 SDValue X = N1.getOperand(1);
24877 if (N0.getOperand(0) == Mask)
24878 Y = N0.getOperand(1);
24879 if (N0.getOperand(1) == Mask)
24880 Y = N0.getOperand(0);
24882 // Check to see if the mask appeared in both the AND and ANDNP and
24886 // Validate that X, Y, and Mask are BIT_CONVERTS, and see through them.
24887 // Look through mask bitcast.
24888 if (Mask.getOpcode() == ISD::BITCAST)
24889 Mask = Mask.getOperand(0);
24890 if (X.getOpcode() == ISD::BITCAST)
24891 X = X.getOperand(0);
24892 if (Y.getOpcode() == ISD::BITCAST)
24893 Y = Y.getOperand(0);
24895 EVT MaskVT = Mask.getValueType();
24897 // Validate that the Mask operand is a vector sra node.
24898 // FIXME: what to do for bytes, since there is a psignb/pblendvb, but
24899 // there is no psrai.b
24900 unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits();
24901 unsigned SraAmt = ~0;
24902 if (Mask.getOpcode() == ISD::SRA) {
24903 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Mask.getOperand(1)))
24904 if (auto *AmtConst = AmtBV->getConstantSplatNode())
24905 SraAmt = AmtConst->getZExtValue();
24906 } else if (Mask.getOpcode() == X86ISD::VSRAI) {
24907 SDValue SraC = Mask.getOperand(1);
24908 SraAmt = cast<ConstantSDNode>(SraC)->getZExtValue();
24910 if ((SraAmt + 1) != EltBits)
24915 // Now we know we at least have a plendvb with the mask val. See if
24916 // we can form a psignb/w/d.
24917 // psign = x.type == y.type == mask.type && y = sub(0, x);
24918 if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X &&
24919 ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) &&
24920 X.getValueType() == MaskVT && Y.getValueType() == MaskVT) {
24921 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
24922 "Unsupported VT for PSIGN");
24923 Mask = DAG.getNode(X86ISD::PSIGN, DL, MaskVT, X, Mask.getOperand(0));
24924 return DAG.getBitcast(VT, Mask);
24926 // PBLENDVB only available on SSE 4.1
24927 if (!Subtarget->hasSSE41())
24930 EVT BlendVT = (VT == MVT::v4i64) ? MVT::v32i8 : MVT::v16i8;
24932 X = DAG.getBitcast(BlendVT, X);
24933 Y = DAG.getBitcast(BlendVT, Y);
24934 Mask = DAG.getBitcast(BlendVT, Mask);
24935 Mask = DAG.getNode(ISD::VSELECT, DL, BlendVT, Mask, Y, X);
24936 return DAG.getBitcast(VT, Mask);
24940 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64)
24943 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
24944 bool OptForSize = DAG.getMachineFunction().getFunction()->optForSize();
24946 // SHLD/SHRD instructions have lower register pressure, but on some
24947 // platforms they have higher latency than the equivalent
24948 // series of shifts/or that would otherwise be generated.
24949 // Don't fold (or (x << c) | (y >> (64 - c))) if SHLD/SHRD instructions
24950 // have higher latencies and we are not optimizing for size.
24951 if (!OptForSize && Subtarget->isSHLDSlow())
24954 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
24956 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
24958 if (!N0.hasOneUse() || !N1.hasOneUse())
24961 SDValue ShAmt0 = N0.getOperand(1);
24962 if (ShAmt0.getValueType() != MVT::i8)
24964 SDValue ShAmt1 = N1.getOperand(1);
24965 if (ShAmt1.getValueType() != MVT::i8)
24967 if (ShAmt0.getOpcode() == ISD::TRUNCATE)
24968 ShAmt0 = ShAmt0.getOperand(0);
24969 if (ShAmt1.getOpcode() == ISD::TRUNCATE)
24970 ShAmt1 = ShAmt1.getOperand(0);
24973 unsigned Opc = X86ISD::SHLD;
24974 SDValue Op0 = N0.getOperand(0);
24975 SDValue Op1 = N1.getOperand(0);
24976 if (ShAmt0.getOpcode() == ISD::SUB) {
24977 Opc = X86ISD::SHRD;
24978 std::swap(Op0, Op1);
24979 std::swap(ShAmt0, ShAmt1);
24982 unsigned Bits = VT.getSizeInBits();
24983 if (ShAmt1.getOpcode() == ISD::SUB) {
24984 SDValue Sum = ShAmt1.getOperand(0);
24985 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) {
24986 SDValue ShAmt1Op1 = ShAmt1.getOperand(1);
24987 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE)
24988 ShAmt1Op1 = ShAmt1Op1.getOperand(0);
24989 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0)
24990 return DAG.getNode(Opc, DL, VT,
24992 DAG.getNode(ISD::TRUNCATE, DL,
24995 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) {
24996 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0);
24998 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits)
24999 return DAG.getNode(Opc, DL, VT,
25000 N0.getOperand(0), N1.getOperand(0),
25001 DAG.getNode(ISD::TRUNCATE, DL,
25008 // Generate NEG and CMOV for integer abs.
25009 static SDValue performIntegerAbsCombine(SDNode *N, SelectionDAG &DAG) {
25010 EVT VT = N->getValueType(0);
25012 // Since X86 does not have CMOV for 8-bit integer, we don't convert
25013 // 8-bit integer abs to NEG and CMOV.
25014 if (VT.isInteger() && VT.getSizeInBits() == 8)
25017 SDValue N0 = N->getOperand(0);
25018 SDValue N1 = N->getOperand(1);
25021 // Check pattern of XOR(ADD(X,Y), Y) where Y is SRA(X, size(X)-1)
25022 // and change it to SUB and CMOV.
25023 if (VT.isInteger() && N->getOpcode() == ISD::XOR &&
25024 N0.getOpcode() == ISD::ADD &&
25025 N0.getOperand(1) == N1 &&
25026 N1.getOpcode() == ISD::SRA &&
25027 N1.getOperand(0) == N0.getOperand(0))
25028 if (ConstantSDNode *Y1C = dyn_cast<ConstantSDNode>(N1.getOperand(1)))
25029 if (Y1C->getAPIntValue() == VT.getSizeInBits()-1) {
25030 // Generate SUB & CMOV.
25031 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, DAG.getVTList(VT, MVT::i32),
25032 DAG.getConstant(0, DL, VT), N0.getOperand(0));
25034 SDValue Ops[] = { N0.getOperand(0), Neg,
25035 DAG.getConstant(X86::COND_GE, DL, MVT::i8),
25036 SDValue(Neg.getNode(), 1) };
25037 return DAG.getNode(X86ISD::CMOV, DL, DAG.getVTList(VT, MVT::Glue), Ops);
25042 // Try to turn tests against the signbit in the form of:
25043 // XOR(TRUNCATE(SRL(X, size(X)-1)), 1)
25046 static SDValue foldXorTruncShiftIntoCmp(SDNode *N, SelectionDAG &DAG) {
25047 // This is only worth doing if the output type is i8.
25048 if (N->getValueType(0) != MVT::i8)
25051 SDValue N0 = N->getOperand(0);
25052 SDValue N1 = N->getOperand(1);
25054 // We should be performing an xor against a truncated shift.
25055 if (N0.getOpcode() != ISD::TRUNCATE || !N0.hasOneUse())
25058 // Make sure we are performing an xor against one.
25059 if (!isa<ConstantSDNode>(N1) || !cast<ConstantSDNode>(N1)->isOne())
25062 // SetCC on x86 zero extends so only act on this if it's a logical shift.
25063 SDValue Shift = N0.getOperand(0);
25064 if (Shift.getOpcode() != ISD::SRL || !Shift.hasOneUse())
25067 // Make sure we are truncating from one of i16, i32 or i64.
25068 EVT ShiftTy = Shift.getValueType();
25069 if (ShiftTy != MVT::i16 && ShiftTy != MVT::i32 && ShiftTy != MVT::i64)
25072 // Make sure the shift amount extracts the sign bit.
25073 if (!isa<ConstantSDNode>(Shift.getOperand(1)) ||
25074 Shift.getConstantOperandVal(1) != ShiftTy.getSizeInBits() - 1)
25077 // Create a greater-than comparison against -1.
25078 // N.B. Using SETGE against 0 works but we want a canonical looking
25079 // comparison, using SETGT matches up with what TranslateX86CC.
25081 SDValue ShiftOp = Shift.getOperand(0);
25082 EVT ShiftOpTy = ShiftOp.getValueType();
25083 SDValue Cond = DAG.getSetCC(DL, MVT::i8, ShiftOp,
25084 DAG.getConstant(-1, DL, ShiftOpTy), ISD::SETGT);
25088 static SDValue PerformXorCombine(SDNode *N, SelectionDAG &DAG,
25089 TargetLowering::DAGCombinerInfo &DCI,
25090 const X86Subtarget *Subtarget) {
25091 if (DCI.isBeforeLegalizeOps())
25094 if (SDValue RV = foldXorTruncShiftIntoCmp(N, DAG))
25097 if (Subtarget->hasCMov())
25098 if (SDValue RV = performIntegerAbsCombine(N, DAG))
25101 if (SDValue FPLogic = convertIntLogicToFPLogic(N, DAG, Subtarget))
25107 /// PerformLOADCombine - Do target-specific dag combines on LOAD nodes.
25108 static SDValue PerformLOADCombine(SDNode *N, SelectionDAG &DAG,
25109 TargetLowering::DAGCombinerInfo &DCI,
25110 const X86Subtarget *Subtarget) {
25111 LoadSDNode *Ld = cast<LoadSDNode>(N);
25112 EVT RegVT = Ld->getValueType(0);
25113 EVT MemVT = Ld->getMemoryVT();
25115 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
25117 // For chips with slow 32-byte unaligned loads, break the 32-byte operation
25118 // into two 16-byte operations.
25119 ISD::LoadExtType Ext = Ld->getExtensionType();
25121 unsigned AddressSpace = Ld->getAddressSpace();
25122 unsigned Alignment = Ld->getAlignment();
25123 if (RegVT.is256BitVector() && !DCI.isBeforeLegalizeOps() &&
25124 Ext == ISD::NON_EXTLOAD &&
25125 TLI.allowsMemoryAccess(*DAG.getContext(), DAG.getDataLayout(), RegVT,
25126 AddressSpace, Alignment, &Fast) && !Fast) {
25127 unsigned NumElems = RegVT.getVectorNumElements();
25131 SDValue Ptr = Ld->getBasePtr();
25132 SDValue Increment =
25133 DAG.getConstant(16, dl, TLI.getPointerTy(DAG.getDataLayout()));
25135 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
25137 SDValue Load1 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
25138 Ld->getPointerInfo(), Ld->isVolatile(),
25139 Ld->isNonTemporal(), Ld->isInvariant(),
25141 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
25142 SDValue Load2 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
25143 Ld->getPointerInfo(), Ld->isVolatile(),
25144 Ld->isNonTemporal(), Ld->isInvariant(),
25145 std::min(16U, Alignment));
25146 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
25148 Load2.getValue(1));
25150 SDValue NewVec = DAG.getUNDEF(RegVT);
25151 NewVec = Insert128BitVector(NewVec, Load1, 0, DAG, dl);
25152 NewVec = Insert128BitVector(NewVec, Load2, NumElems/2, DAG, dl);
25153 return DCI.CombineTo(N, NewVec, TF, true);
25159 /// PerformMLOADCombine - Resolve extending loads
25160 static SDValue PerformMLOADCombine(SDNode *N, SelectionDAG &DAG,
25161 TargetLowering::DAGCombinerInfo &DCI,
25162 const X86Subtarget *Subtarget) {
25163 MaskedLoadSDNode *Mld = cast<MaskedLoadSDNode>(N);
25164 if (Mld->getExtensionType() != ISD::SEXTLOAD)
25167 EVT VT = Mld->getValueType(0);
25168 unsigned NumElems = VT.getVectorNumElements();
25169 EVT LdVT = Mld->getMemoryVT();
25172 assert(LdVT != VT && "Cannot extend to the same type");
25173 unsigned ToSz = VT.getVectorElementType().getSizeInBits();
25174 unsigned FromSz = LdVT.getVectorElementType().getSizeInBits();
25175 // From, To sizes and ElemCount must be pow of two
25176 assert (isPowerOf2_32(NumElems * FromSz * ToSz) &&
25177 "Unexpected size for extending masked load");
25179 unsigned SizeRatio = ToSz / FromSz;
25180 assert(SizeRatio * NumElems * FromSz == VT.getSizeInBits());
25182 // Create a type on which we perform the shuffle
25183 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
25184 LdVT.getScalarType(), NumElems*SizeRatio);
25185 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
25187 // Convert Src0 value
25188 SDValue WideSrc0 = DAG.getBitcast(WideVecVT, Mld->getSrc0());
25189 if (Mld->getSrc0().getOpcode() != ISD::UNDEF) {
25190 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
25191 for (unsigned i = 0; i != NumElems; ++i)
25192 ShuffleVec[i] = i * SizeRatio;
25194 // Can't shuffle using an illegal type.
25195 assert(DAG.getTargetLoweringInfo().isTypeLegal(WideVecVT) &&
25196 "WideVecVT should be legal");
25197 WideSrc0 = DAG.getVectorShuffle(WideVecVT, dl, WideSrc0,
25198 DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
25200 // Prepare the new mask
25202 SDValue Mask = Mld->getMask();
25203 if (Mask.getValueType() == VT) {
25204 // Mask and original value have the same type
25205 NewMask = DAG.getBitcast(WideVecVT, Mask);
25206 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
25207 for (unsigned i = 0; i != NumElems; ++i)
25208 ShuffleVec[i] = i * SizeRatio;
25209 for (unsigned i = NumElems; i != NumElems*SizeRatio; ++i)
25210 ShuffleVec[i] = NumElems*SizeRatio;
25211 NewMask = DAG.getVectorShuffle(WideVecVT, dl, NewMask,
25212 DAG.getConstant(0, dl, WideVecVT),
25216 assert(Mask.getValueType().getVectorElementType() == MVT::i1);
25217 unsigned WidenNumElts = NumElems*SizeRatio;
25218 unsigned MaskNumElts = VT.getVectorNumElements();
25219 EVT NewMaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
25222 unsigned NumConcat = WidenNumElts / MaskNumElts;
25223 SmallVector<SDValue, 16> Ops(NumConcat);
25224 SDValue ZeroVal = DAG.getConstant(0, dl, Mask.getValueType());
25226 for (unsigned i = 1; i != NumConcat; ++i)
25229 NewMask = DAG.getNode(ISD::CONCAT_VECTORS, dl, NewMaskVT, Ops);
25232 SDValue WideLd = DAG.getMaskedLoad(WideVecVT, dl, Mld->getChain(),
25233 Mld->getBasePtr(), NewMask, WideSrc0,
25234 Mld->getMemoryVT(), Mld->getMemOperand(),
25236 SDValue NewVec = DAG.getNode(X86ISD::VSEXT, dl, VT, WideLd);
25237 return DCI.CombineTo(N, NewVec, WideLd.getValue(1), true);
25239 /// PerformMSTORECombine - Resolve truncating stores
25240 static SDValue PerformMSTORECombine(SDNode *N, SelectionDAG &DAG,
25241 const X86Subtarget *Subtarget) {
25242 MaskedStoreSDNode *Mst = cast<MaskedStoreSDNode>(N);
25243 if (!Mst->isTruncatingStore())
25246 EVT VT = Mst->getValue().getValueType();
25247 unsigned NumElems = VT.getVectorNumElements();
25248 EVT StVT = Mst->getMemoryVT();
25251 assert(StVT != VT && "Cannot truncate to the same type");
25252 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
25253 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
25255 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
25257 // The truncating store is legal in some cases. For example
25258 // vpmovqb, vpmovqw, vpmovqd, vpmovdb, vpmovdw
25259 // are designated for truncate store.
25260 // In this case we don't need any further transformations.
25261 if (TLI.isTruncStoreLegal(VT, StVT))
25264 // From, To sizes and ElemCount must be pow of two
25265 assert (isPowerOf2_32(NumElems * FromSz * ToSz) &&
25266 "Unexpected size for truncating masked store");
25267 // We are going to use the original vector elt for storing.
25268 // Accumulated smaller vector elements must be a multiple of the store size.
25269 assert (((NumElems * FromSz) % ToSz) == 0 &&
25270 "Unexpected ratio for truncating masked store");
25272 unsigned SizeRatio = FromSz / ToSz;
25273 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
25275 // Create a type on which we perform the shuffle
25276 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
25277 StVT.getScalarType(), NumElems*SizeRatio);
25279 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
25281 SDValue WideVec = DAG.getBitcast(WideVecVT, Mst->getValue());
25282 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
25283 for (unsigned i = 0; i != NumElems; ++i)
25284 ShuffleVec[i] = i * SizeRatio;
25286 // Can't shuffle using an illegal type.
25287 assert(DAG.getTargetLoweringInfo().isTypeLegal(WideVecVT) &&
25288 "WideVecVT should be legal");
25290 SDValue TruncatedVal = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
25291 DAG.getUNDEF(WideVecVT),
25295 SDValue Mask = Mst->getMask();
25296 if (Mask.getValueType() == VT) {
25297 // Mask and original value have the same type
25298 NewMask = DAG.getBitcast(WideVecVT, Mask);
25299 for (unsigned i = 0; i != NumElems; ++i)
25300 ShuffleVec[i] = i * SizeRatio;
25301 for (unsigned i = NumElems; i != NumElems*SizeRatio; ++i)
25302 ShuffleVec[i] = NumElems*SizeRatio;
25303 NewMask = DAG.getVectorShuffle(WideVecVT, dl, NewMask,
25304 DAG.getConstant(0, dl, WideVecVT),
25308 assert(Mask.getValueType().getVectorElementType() == MVT::i1);
25309 unsigned WidenNumElts = NumElems*SizeRatio;
25310 unsigned MaskNumElts = VT.getVectorNumElements();
25311 EVT NewMaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
25314 unsigned NumConcat = WidenNumElts / MaskNumElts;
25315 SmallVector<SDValue, 16> Ops(NumConcat);
25316 SDValue ZeroVal = DAG.getConstant(0, dl, Mask.getValueType());
25318 for (unsigned i = 1; i != NumConcat; ++i)
25321 NewMask = DAG.getNode(ISD::CONCAT_VECTORS, dl, NewMaskVT, Ops);
25324 return DAG.getMaskedStore(Mst->getChain(), dl, TruncatedVal, Mst->getBasePtr(),
25325 NewMask, StVT, Mst->getMemOperand(), false);
25327 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
25328 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
25329 const X86Subtarget *Subtarget) {
25330 StoreSDNode *St = cast<StoreSDNode>(N);
25331 EVT VT = St->getValue().getValueType();
25332 EVT StVT = St->getMemoryVT();
25334 SDValue StoredVal = St->getOperand(1);
25335 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
25337 // If we are saving a concatenation of two XMM registers and 32-byte stores
25338 // are slow, such as on Sandy Bridge, perform two 16-byte stores.
25340 unsigned AddressSpace = St->getAddressSpace();
25341 unsigned Alignment = St->getAlignment();
25342 if (VT.is256BitVector() && StVT == VT &&
25343 TLI.allowsMemoryAccess(*DAG.getContext(), DAG.getDataLayout(), VT,
25344 AddressSpace, Alignment, &Fast) && !Fast) {
25345 unsigned NumElems = VT.getVectorNumElements();
25349 SDValue Value0 = Extract128BitVector(StoredVal, 0, DAG, dl);
25350 SDValue Value1 = Extract128BitVector(StoredVal, NumElems/2, DAG, dl);
25353 DAG.getConstant(16, dl, TLI.getPointerTy(DAG.getDataLayout()));
25354 SDValue Ptr0 = St->getBasePtr();
25355 SDValue Ptr1 = DAG.getNode(ISD::ADD, dl, Ptr0.getValueType(), Ptr0, Stride);
25357 SDValue Ch0 = DAG.getStore(St->getChain(), dl, Value0, Ptr0,
25358 St->getPointerInfo(), St->isVolatile(),
25359 St->isNonTemporal(), Alignment);
25360 SDValue Ch1 = DAG.getStore(St->getChain(), dl, Value1, Ptr1,
25361 St->getPointerInfo(), St->isVolatile(),
25362 St->isNonTemporal(),
25363 std::min(16U, Alignment));
25364 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ch0, Ch1);
25367 // Optimize trunc store (of multiple scalars) to shuffle and store.
25368 // First, pack all of the elements in one place. Next, store to memory
25369 // in fewer chunks.
25370 if (St->isTruncatingStore() && VT.isVector()) {
25371 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
25372 unsigned NumElems = VT.getVectorNumElements();
25373 assert(StVT != VT && "Cannot truncate to the same type");
25374 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
25375 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
25377 // The truncating store is legal in some cases. For example
25378 // vpmovqb, vpmovqw, vpmovqd, vpmovdb, vpmovdw
25379 // are designated for truncate store.
25380 // In this case we don't need any further transformations.
25381 if (TLI.isTruncStoreLegal(VT, StVT))
25384 // From, To sizes and ElemCount must be pow of two
25385 if (!isPowerOf2_32(NumElems * FromSz * ToSz)) return SDValue();
25386 // We are going to use the original vector elt for storing.
25387 // Accumulated smaller vector elements must be a multiple of the store size.
25388 if (0 != (NumElems * FromSz) % ToSz) return SDValue();
25390 unsigned SizeRatio = FromSz / ToSz;
25392 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
25394 // Create a type on which we perform the shuffle
25395 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
25396 StVT.getScalarType(), NumElems*SizeRatio);
25398 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
25400 SDValue WideVec = DAG.getBitcast(WideVecVT, St->getValue());
25401 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
25402 for (unsigned i = 0; i != NumElems; ++i)
25403 ShuffleVec[i] = i * SizeRatio;
25405 // Can't shuffle using an illegal type.
25406 if (!TLI.isTypeLegal(WideVecVT))
25409 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
25410 DAG.getUNDEF(WideVecVT),
25412 // At this point all of the data is stored at the bottom of the
25413 // register. We now need to save it to mem.
25415 // Find the largest store unit
25416 MVT StoreType = MVT::i8;
25417 for (MVT Tp : MVT::integer_valuetypes()) {
25418 if (TLI.isTypeLegal(Tp) && Tp.getSizeInBits() <= NumElems * ToSz)
25422 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
25423 if (TLI.isTypeLegal(MVT::f64) && StoreType.getSizeInBits() < 64 &&
25424 (64 <= NumElems * ToSz))
25425 StoreType = MVT::f64;
25427 // Bitcast the original vector into a vector of store-size units
25428 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(),
25429 StoreType, VT.getSizeInBits()/StoreType.getSizeInBits());
25430 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits());
25431 SDValue ShuffWide = DAG.getBitcast(StoreVecVT, Shuff);
25432 SmallVector<SDValue, 8> Chains;
25433 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits() / 8, dl,
25434 TLI.getPointerTy(DAG.getDataLayout()));
25435 SDValue Ptr = St->getBasePtr();
25437 // Perform one or more big stores into memory.
25438 for (unsigned i=0, e=(ToSz*NumElems)/StoreType.getSizeInBits(); i!=e; ++i) {
25439 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
25440 StoreType, ShuffWide,
25441 DAG.getIntPtrConstant(i, dl));
25442 SDValue Ch = DAG.getStore(St->getChain(), dl, SubVec, Ptr,
25443 St->getPointerInfo(), St->isVolatile(),
25444 St->isNonTemporal(), St->getAlignment());
25445 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
25446 Chains.push_back(Ch);
25449 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
25452 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
25453 // the FP state in cases where an emms may be missing.
25454 // A preferable solution to the general problem is to figure out the right
25455 // places to insert EMMS. This qualifies as a quick hack.
25457 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
25458 if (VT.getSizeInBits() != 64)
25461 const Function *F = DAG.getMachineFunction().getFunction();
25462 bool NoImplicitFloatOps = F->hasFnAttribute(Attribute::NoImplicitFloat);
25464 !Subtarget->useSoftFloat() && !NoImplicitFloatOps && Subtarget->hasSSE2();
25465 if ((VT.isVector() ||
25466 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
25467 isa<LoadSDNode>(St->getValue()) &&
25468 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
25469 St->getChain().hasOneUse() && !St->isVolatile()) {
25470 SDNode* LdVal = St->getValue().getNode();
25471 LoadSDNode *Ld = nullptr;
25472 int TokenFactorIndex = -1;
25473 SmallVector<SDValue, 8> Ops;
25474 SDNode* ChainVal = St->getChain().getNode();
25475 // Must be a store of a load. We currently handle two cases: the load
25476 // is a direct child, and it's under an intervening TokenFactor. It is
25477 // possible to dig deeper under nested TokenFactors.
25478 if (ChainVal == LdVal)
25479 Ld = cast<LoadSDNode>(St->getChain());
25480 else if (St->getValue().hasOneUse() &&
25481 ChainVal->getOpcode() == ISD::TokenFactor) {
25482 for (unsigned i = 0, e = ChainVal->getNumOperands(); i != e; ++i) {
25483 if (ChainVal->getOperand(i).getNode() == LdVal) {
25484 TokenFactorIndex = i;
25485 Ld = cast<LoadSDNode>(St->getValue());
25487 Ops.push_back(ChainVal->getOperand(i));
25491 if (!Ld || !ISD::isNormalLoad(Ld))
25494 // If this is not the MMX case, i.e. we are just turning i64 load/store
25495 // into f64 load/store, avoid the transformation if there are multiple
25496 // uses of the loaded value.
25497 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
25502 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
25503 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
25505 if (Subtarget->is64Bit() || F64IsLegal) {
25506 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
25507 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(),
25508 Ld->getPointerInfo(), Ld->isVolatile(),
25509 Ld->isNonTemporal(), Ld->isInvariant(),
25510 Ld->getAlignment());
25511 SDValue NewChain = NewLd.getValue(1);
25512 if (TokenFactorIndex != -1) {
25513 Ops.push_back(NewChain);
25514 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
25516 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
25517 St->getPointerInfo(),
25518 St->isVolatile(), St->isNonTemporal(),
25519 St->getAlignment());
25522 // Otherwise, lower to two pairs of 32-bit loads / stores.
25523 SDValue LoAddr = Ld->getBasePtr();
25524 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
25525 DAG.getConstant(4, LdDL, MVT::i32));
25527 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
25528 Ld->getPointerInfo(),
25529 Ld->isVolatile(), Ld->isNonTemporal(),
25530 Ld->isInvariant(), Ld->getAlignment());
25531 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
25532 Ld->getPointerInfo().getWithOffset(4),
25533 Ld->isVolatile(), Ld->isNonTemporal(),
25535 MinAlign(Ld->getAlignment(), 4));
25537 SDValue NewChain = LoLd.getValue(1);
25538 if (TokenFactorIndex != -1) {
25539 Ops.push_back(LoLd);
25540 Ops.push_back(HiLd);
25541 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
25544 LoAddr = St->getBasePtr();
25545 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
25546 DAG.getConstant(4, StDL, MVT::i32));
25548 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
25549 St->getPointerInfo(),
25550 St->isVolatile(), St->isNonTemporal(),
25551 St->getAlignment());
25552 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
25553 St->getPointerInfo().getWithOffset(4),
25555 St->isNonTemporal(),
25556 MinAlign(St->getAlignment(), 4));
25557 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
25560 // This is similar to the above case, but here we handle a scalar 64-bit
25561 // integer store that is extracted from a vector on a 32-bit target.
25562 // If we have SSE2, then we can treat it like a floating-point double
25563 // to get past legalization. The execution dependencies fixup pass will
25564 // choose the optimal machine instruction for the store if this really is
25565 // an integer or v2f32 rather than an f64.
25566 if (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit() &&
25567 St->getOperand(1).getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
25568 SDValue OldExtract = St->getOperand(1);
25569 SDValue ExtOp0 = OldExtract.getOperand(0);
25570 unsigned VecSize = ExtOp0.getValueSizeInBits();
25571 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), MVT::f64, VecSize / 64);
25572 SDValue BitCast = DAG.getBitcast(VecVT, ExtOp0);
25573 SDValue NewExtract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
25574 BitCast, OldExtract.getOperand(1));
25575 return DAG.getStore(St->getChain(), dl, NewExtract, St->getBasePtr(),
25576 St->getPointerInfo(), St->isVolatile(),
25577 St->isNonTemporal(), St->getAlignment());
25583 /// Return 'true' if this vector operation is "horizontal"
25584 /// and return the operands for the horizontal operation in LHS and RHS. A
25585 /// horizontal operation performs the binary operation on successive elements
25586 /// of its first operand, then on successive elements of its second operand,
25587 /// returning the resulting values in a vector. For example, if
25588 /// A = < float a0, float a1, float a2, float a3 >
25590 /// B = < float b0, float b1, float b2, float b3 >
25591 /// then the result of doing a horizontal operation on A and B is
25592 /// A horizontal-op B = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >.
25593 /// In short, LHS and RHS are inspected to see if LHS op RHS is of the form
25594 /// A horizontal-op B, for some already available A and B, and if so then LHS is
25595 /// set to A, RHS to B, and the routine returns 'true'.
25596 /// Note that the binary operation should have the property that if one of the
25597 /// operands is UNDEF then the result is UNDEF.
25598 static bool isHorizontalBinOp(SDValue &LHS, SDValue &RHS, bool IsCommutative) {
25599 // Look for the following pattern: if
25600 // A = < float a0, float a1, float a2, float a3 >
25601 // B = < float b0, float b1, float b2, float b3 >
25603 // LHS = VECTOR_SHUFFLE A, B, <0, 2, 4, 6>
25604 // RHS = VECTOR_SHUFFLE A, B, <1, 3, 5, 7>
25605 // then LHS op RHS = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >
25606 // which is A horizontal-op B.
25608 // At least one of the operands should be a vector shuffle.
25609 if (LHS.getOpcode() != ISD::VECTOR_SHUFFLE &&
25610 RHS.getOpcode() != ISD::VECTOR_SHUFFLE)
25613 MVT VT = LHS.getSimpleValueType();
25615 assert((VT.is128BitVector() || VT.is256BitVector()) &&
25616 "Unsupported vector type for horizontal add/sub");
25618 // Handle 128 and 256-bit vector lengths. AVX defines horizontal add/sub to
25619 // operate independently on 128-bit lanes.
25620 unsigned NumElts = VT.getVectorNumElements();
25621 unsigned NumLanes = VT.getSizeInBits()/128;
25622 unsigned NumLaneElts = NumElts / NumLanes;
25623 assert((NumLaneElts % 2 == 0) &&
25624 "Vector type should have an even number of elements in each lane");
25625 unsigned HalfLaneElts = NumLaneElts/2;
25627 // View LHS in the form
25628 // LHS = VECTOR_SHUFFLE A, B, LMask
25629 // If LHS is not a shuffle then pretend it is the shuffle
25630 // LHS = VECTOR_SHUFFLE LHS, undef, <0, 1, ..., N-1>
25631 // NOTE: in what follows a default initialized SDValue represents an UNDEF of
25634 SmallVector<int, 16> LMask(NumElts);
25635 if (LHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
25636 if (LHS.getOperand(0).getOpcode() != ISD::UNDEF)
25637 A = LHS.getOperand(0);
25638 if (LHS.getOperand(1).getOpcode() != ISD::UNDEF)
25639 B = LHS.getOperand(1);
25640 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(LHS.getNode())->getMask();
25641 std::copy(Mask.begin(), Mask.end(), LMask.begin());
25643 if (LHS.getOpcode() != ISD::UNDEF)
25645 for (unsigned i = 0; i != NumElts; ++i)
25649 // Likewise, view RHS in the form
25650 // RHS = VECTOR_SHUFFLE C, D, RMask
25652 SmallVector<int, 16> RMask(NumElts);
25653 if (RHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
25654 if (RHS.getOperand(0).getOpcode() != ISD::UNDEF)
25655 C = RHS.getOperand(0);
25656 if (RHS.getOperand(1).getOpcode() != ISD::UNDEF)
25657 D = RHS.getOperand(1);
25658 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(RHS.getNode())->getMask();
25659 std::copy(Mask.begin(), Mask.end(), RMask.begin());
25661 if (RHS.getOpcode() != ISD::UNDEF)
25663 for (unsigned i = 0; i != NumElts; ++i)
25667 // Check that the shuffles are both shuffling the same vectors.
25668 if (!(A == C && B == D) && !(A == D && B == C))
25671 // If everything is UNDEF then bail out: it would be better to fold to UNDEF.
25672 if (!A.getNode() && !B.getNode())
25675 // If A and B occur in reverse order in RHS, then "swap" them (which means
25676 // rewriting the mask).
25678 ShuffleVectorSDNode::commuteMask(RMask);
25680 // At this point LHS and RHS are equivalent to
25681 // LHS = VECTOR_SHUFFLE A, B, LMask
25682 // RHS = VECTOR_SHUFFLE A, B, RMask
25683 // Check that the masks correspond to performing a horizontal operation.
25684 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
25685 for (unsigned i = 0; i != NumLaneElts; ++i) {
25686 int LIdx = LMask[i+l], RIdx = RMask[i+l];
25688 // Ignore any UNDEF components.
25689 if (LIdx < 0 || RIdx < 0 ||
25690 (!A.getNode() && (LIdx < (int)NumElts || RIdx < (int)NumElts)) ||
25691 (!B.getNode() && (LIdx >= (int)NumElts || RIdx >= (int)NumElts)))
25694 // Check that successive elements are being operated on. If not, this is
25695 // not a horizontal operation.
25696 unsigned Src = (i/HalfLaneElts); // each lane is split between srcs
25697 int Index = 2*(i%HalfLaneElts) + NumElts*Src + l;
25698 if (!(LIdx == Index && RIdx == Index + 1) &&
25699 !(IsCommutative && LIdx == Index + 1 && RIdx == Index))
25704 LHS = A.getNode() ? A : B; // If A is 'UNDEF', use B for it.
25705 RHS = B.getNode() ? B : A; // If B is 'UNDEF', use A for it.
25709 /// Do target-specific dag combines on floating point adds.
25710 static SDValue PerformFADDCombine(SDNode *N, SelectionDAG &DAG,
25711 const X86Subtarget *Subtarget) {
25712 EVT VT = N->getValueType(0);
25713 SDValue LHS = N->getOperand(0);
25714 SDValue RHS = N->getOperand(1);
25716 // Try to synthesize horizontal adds from adds of shuffles.
25717 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
25718 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
25719 isHorizontalBinOp(LHS, RHS, true))
25720 return DAG.getNode(X86ISD::FHADD, SDLoc(N), VT, LHS, RHS);
25724 /// Do target-specific dag combines on floating point subs.
25725 static SDValue PerformFSUBCombine(SDNode *N, SelectionDAG &DAG,
25726 const X86Subtarget *Subtarget) {
25727 EVT VT = N->getValueType(0);
25728 SDValue LHS = N->getOperand(0);
25729 SDValue RHS = N->getOperand(1);
25731 // Try to synthesize horizontal subs from subs of shuffles.
25732 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
25733 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
25734 isHorizontalBinOp(LHS, RHS, false))
25735 return DAG.getNode(X86ISD::FHSUB, SDLoc(N), VT, LHS, RHS);
25739 /// Do target-specific dag combines on X86ISD::FOR and X86ISD::FXOR nodes.
25740 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG,
25741 const X86Subtarget *Subtarget) {
25742 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
25744 // F[X]OR(0.0, x) -> x
25745 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
25746 if (C->getValueAPF().isPosZero())
25747 return N->getOperand(1);
25749 // F[X]OR(x, 0.0) -> x
25750 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
25751 if (C->getValueAPF().isPosZero())
25752 return N->getOperand(0);
25754 EVT VT = N->getValueType(0);
25755 if (VT.is512BitVector() && !Subtarget->hasDQI()) {
25757 MVT IntScalar = MVT::getIntegerVT(VT.getScalarSizeInBits());
25758 MVT IntVT = MVT::getVectorVT(IntScalar, VT.getVectorNumElements());
25760 SDValue Op0 = DAG.getNode(ISD::BITCAST, dl, IntVT, N->getOperand(0));
25761 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, IntVT, N->getOperand(1));
25762 unsigned IntOpcode = (N->getOpcode() == X86ISD::FOR) ? ISD::OR : ISD::XOR;
25763 SDValue IntOp = DAG.getNode(IntOpcode, dl, IntVT, Op0, Op1);
25764 return DAG.getNode(ISD::BITCAST, dl, VT, IntOp);
25769 /// Do target-specific dag combines on X86ISD::FMIN and X86ISD::FMAX nodes.
25770 static SDValue PerformFMinFMaxCombine(SDNode *N, SelectionDAG &DAG) {
25771 assert(N->getOpcode() == X86ISD::FMIN || N->getOpcode() == X86ISD::FMAX);
25773 // Only perform optimizations if UnsafeMath is used.
25774 if (!DAG.getTarget().Options.UnsafeFPMath)
25777 // If we run in unsafe-math mode, then convert the FMAX and FMIN nodes
25778 // into FMINC and FMAXC, which are Commutative operations.
25779 unsigned NewOp = 0;
25780 switch (N->getOpcode()) {
25781 default: llvm_unreachable("unknown opcode");
25782 case X86ISD::FMIN: NewOp = X86ISD::FMINC; break;
25783 case X86ISD::FMAX: NewOp = X86ISD::FMAXC; break;
25786 return DAG.getNode(NewOp, SDLoc(N), N->getValueType(0),
25787 N->getOperand(0), N->getOperand(1));
25790 /// Do target-specific dag combines on X86ISD::FAND nodes.
25791 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
25792 // FAND(0.0, x) -> 0.0
25793 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
25794 if (C->getValueAPF().isPosZero())
25795 return N->getOperand(0);
25797 // FAND(x, 0.0) -> 0.0
25798 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
25799 if (C->getValueAPF().isPosZero())
25800 return N->getOperand(1);
25805 /// Do target-specific dag combines on X86ISD::FANDN nodes
25806 static SDValue PerformFANDNCombine(SDNode *N, SelectionDAG &DAG) {
25807 // FANDN(0.0, x) -> x
25808 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
25809 if (C->getValueAPF().isPosZero())
25810 return N->getOperand(1);
25812 // FANDN(x, 0.0) -> 0.0
25813 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
25814 if (C->getValueAPF().isPosZero())
25815 return N->getOperand(1);
25820 static SDValue PerformBTCombine(SDNode *N,
25822 TargetLowering::DAGCombinerInfo &DCI) {
25823 // BT ignores high bits in the bit index operand.
25824 SDValue Op1 = N->getOperand(1);
25825 if (Op1.hasOneUse()) {
25826 unsigned BitWidth = Op1.getValueSizeInBits();
25827 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
25828 APInt KnownZero, KnownOne;
25829 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
25830 !DCI.isBeforeLegalizeOps());
25831 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
25832 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
25833 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
25834 DCI.CommitTargetLoweringOpt(TLO);
25839 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
25840 SDValue Op = N->getOperand(0);
25841 if (Op.getOpcode() == ISD::BITCAST)
25842 Op = Op.getOperand(0);
25843 EVT VT = N->getValueType(0), OpVT = Op.getValueType();
25844 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
25845 VT.getVectorElementType().getSizeInBits() ==
25846 OpVT.getVectorElementType().getSizeInBits()) {
25847 return DAG.getNode(ISD::BITCAST, SDLoc(N), VT, Op);
25852 static SDValue PerformSIGN_EXTEND_INREGCombine(SDNode *N, SelectionDAG &DAG,
25853 const X86Subtarget *Subtarget) {
25854 EVT VT = N->getValueType(0);
25855 if (!VT.isVector())
25858 SDValue N0 = N->getOperand(0);
25859 SDValue N1 = N->getOperand(1);
25860 EVT ExtraVT = cast<VTSDNode>(N1)->getVT();
25863 // The SIGN_EXTEND_INREG to v4i64 is expensive operation on the
25864 // both SSE and AVX2 since there is no sign-extended shift right
25865 // operation on a vector with 64-bit elements.
25866 //(sext_in_reg (v4i64 anyext (v4i32 x )), ExtraVT) ->
25867 // (v4i64 sext (v4i32 sext_in_reg (v4i32 x , ExtraVT)))
25868 if (VT == MVT::v4i64 && (N0.getOpcode() == ISD::ANY_EXTEND ||
25869 N0.getOpcode() == ISD::SIGN_EXTEND)) {
25870 SDValue N00 = N0.getOperand(0);
25872 // EXTLOAD has a better solution on AVX2,
25873 // it may be replaced with X86ISD::VSEXT node.
25874 if (N00.getOpcode() == ISD::LOAD && Subtarget->hasInt256())
25875 if (!ISD::isNormalLoad(N00.getNode()))
25878 if (N00.getValueType() == MVT::v4i32 && ExtraVT.getSizeInBits() < 128) {
25879 SDValue Tmp = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v4i32,
25881 return DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i64, Tmp);
25887 /// sext(add_nsw(x, C)) --> add(sext(x), C_sext)
25888 /// Promoting a sign extension ahead of an 'add nsw' exposes opportunities
25889 /// to combine math ops, use an LEA, or use a complex addressing mode. This can
25890 /// eliminate extend, add, and shift instructions.
25891 static SDValue promoteSextBeforeAddNSW(SDNode *Sext, SelectionDAG &DAG,
25892 const X86Subtarget *Subtarget) {
25893 // TODO: This should be valid for other integer types.
25894 EVT VT = Sext->getValueType(0);
25895 if (VT != MVT::i64)
25898 // We need an 'add nsw' feeding into the 'sext'.
25899 SDValue Add = Sext->getOperand(0);
25900 if (Add.getOpcode() != ISD::ADD || !Add->getFlags()->hasNoSignedWrap())
25903 // Having a constant operand to the 'add' ensures that we are not increasing
25904 // the instruction count because the constant is extended for free below.
25905 // A constant operand can also become the displacement field of an LEA.
25906 auto *AddOp1 = dyn_cast<ConstantSDNode>(Add.getOperand(1));
25910 // Don't make the 'add' bigger if there's no hope of combining it with some
25911 // other 'add' or 'shl' instruction.
25912 // TODO: It may be profitable to generate simpler LEA instructions in place
25913 // of single 'add' instructions, but the cost model for selecting an LEA
25914 // currently has a high threshold.
25915 bool HasLEAPotential = false;
25916 for (auto *User : Sext->uses()) {
25917 if (User->getOpcode() == ISD::ADD || User->getOpcode() == ISD::SHL) {
25918 HasLEAPotential = true;
25922 if (!HasLEAPotential)
25925 // Everything looks good, so pull the 'sext' ahead of the 'add'.
25926 int64_t AddConstant = AddOp1->getSExtValue();
25927 SDValue AddOp0 = Add.getOperand(0);
25928 SDValue NewSext = DAG.getNode(ISD::SIGN_EXTEND, SDLoc(Sext), VT, AddOp0);
25929 SDValue NewConstant = DAG.getConstant(AddConstant, SDLoc(Add), VT);
25931 // The wider add is guaranteed to not wrap because both operands are
25934 Flags.setNoSignedWrap(true);
25935 return DAG.getNode(ISD::ADD, SDLoc(Add), VT, NewSext, NewConstant, &Flags);
25938 static SDValue PerformSExtCombine(SDNode *N, SelectionDAG &DAG,
25939 TargetLowering::DAGCombinerInfo &DCI,
25940 const X86Subtarget *Subtarget) {
25941 SDValue N0 = N->getOperand(0);
25942 EVT VT = N->getValueType(0);
25943 EVT SVT = VT.getScalarType();
25944 EVT InVT = N0.getValueType();
25945 EVT InSVT = InVT.getScalarType();
25948 // (i8,i32 sext (sdivrem (i8 x, i8 y)) ->
25949 // (i8,i32 (sdivrem_sext_hreg (i8 x, i8 y)
25950 // This exposes the sext to the sdivrem lowering, so that it directly extends
25951 // from AH (which we otherwise need to do contortions to access).
25952 if (N0.getOpcode() == ISD::SDIVREM && N0.getResNo() == 1 &&
25953 InVT == MVT::i8 && VT == MVT::i32) {
25954 SDVTList NodeTys = DAG.getVTList(MVT::i8, VT);
25955 SDValue R = DAG.getNode(X86ISD::SDIVREM8_SEXT_HREG, DL, NodeTys,
25956 N0.getOperand(0), N0.getOperand(1));
25957 DAG.ReplaceAllUsesOfValueWith(N0.getValue(0), R.getValue(0));
25958 return R.getValue(1);
25961 if (!DCI.isBeforeLegalizeOps()) {
25962 if (InVT == MVT::i1) {
25963 SDValue Zero = DAG.getConstant(0, DL, VT);
25965 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), DL, VT);
25966 return DAG.getNode(ISD::SELECT, DL, VT, N0, AllOnes, Zero);
25971 if (VT.isVector() && Subtarget->hasSSE2()) {
25972 auto ExtendVecSize = [&DAG](SDLoc DL, SDValue N, unsigned Size) {
25973 EVT InVT = N.getValueType();
25974 EVT OutVT = EVT::getVectorVT(*DAG.getContext(), InVT.getScalarType(),
25975 Size / InVT.getScalarSizeInBits());
25976 SmallVector<SDValue, 8> Opnds(Size / InVT.getSizeInBits(),
25977 DAG.getUNDEF(InVT));
25979 return DAG.getNode(ISD::CONCAT_VECTORS, DL, OutVT, Opnds);
25982 // If target-size is less than 128-bits, extend to a type that would extend
25983 // to 128 bits, extend that and extract the original target vector.
25984 if (VT.getSizeInBits() < 128 && !(128 % VT.getSizeInBits()) &&
25985 (SVT == MVT::i64 || SVT == MVT::i32 || SVT == MVT::i16) &&
25986 (InSVT == MVT::i32 || InSVT == MVT::i16 || InSVT == MVT::i8)) {
25987 unsigned Scale = 128 / VT.getSizeInBits();
25989 EVT::getVectorVT(*DAG.getContext(), SVT, 128 / SVT.getSizeInBits());
25990 SDValue Ex = ExtendVecSize(DL, N0, Scale * InVT.getSizeInBits());
25991 SDValue SExt = DAG.getNode(ISD::SIGN_EXTEND, DL, ExVT, Ex);
25992 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, SExt,
25993 DAG.getIntPtrConstant(0, DL));
25996 // If target-size is 128-bits, then convert to ISD::SIGN_EXTEND_VECTOR_INREG
25997 // which ensures lowering to X86ISD::VSEXT (pmovsx*).
25998 if (VT.getSizeInBits() == 128 &&
25999 (SVT == MVT::i64 || SVT == MVT::i32 || SVT == MVT::i16) &&
26000 (InSVT == MVT::i32 || InSVT == MVT::i16 || InSVT == MVT::i8)) {
26001 SDValue ExOp = ExtendVecSize(DL, N0, 128);
26002 return DAG.getSignExtendVectorInReg(ExOp, DL, VT);
26005 // On pre-AVX2 targets, split into 128-bit nodes of
26006 // ISD::SIGN_EXTEND_VECTOR_INREG.
26007 if (!Subtarget->hasInt256() && !(VT.getSizeInBits() % 128) &&
26008 (SVT == MVT::i64 || SVT == MVT::i32 || SVT == MVT::i16) &&
26009 (InSVT == MVT::i32 || InSVT == MVT::i16 || InSVT == MVT::i8)) {
26010 unsigned NumVecs = VT.getSizeInBits() / 128;
26011 unsigned NumSubElts = 128 / SVT.getSizeInBits();
26012 EVT SubVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumSubElts);
26013 EVT InSubVT = EVT::getVectorVT(*DAG.getContext(), InSVT, NumSubElts);
26015 SmallVector<SDValue, 8> Opnds;
26016 for (unsigned i = 0, Offset = 0; i != NumVecs;
26017 ++i, Offset += NumSubElts) {
26018 SDValue SrcVec = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InSubVT, N0,
26019 DAG.getIntPtrConstant(Offset, DL));
26020 SrcVec = ExtendVecSize(DL, SrcVec, 128);
26021 SrcVec = DAG.getSignExtendVectorInReg(SrcVec, DL, SubVT);
26022 Opnds.push_back(SrcVec);
26024 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Opnds);
26028 if (Subtarget->hasAVX() && VT.isVector() && VT.getSizeInBits() == 256)
26029 if (SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget))
26032 if (SDValue NewAdd = promoteSextBeforeAddNSW(N, DAG, Subtarget))
26038 static SDValue PerformFMACombine(SDNode *N, SelectionDAG &DAG,
26039 const X86Subtarget* Subtarget) {
26041 EVT VT = N->getValueType(0);
26043 // Let legalize expand this if it isn't a legal type yet.
26044 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
26047 EVT ScalarVT = VT.getScalarType();
26048 if ((ScalarVT != MVT::f32 && ScalarVT != MVT::f64) ||
26049 (!Subtarget->hasFMA() && !Subtarget->hasFMA4() &&
26050 !Subtarget->hasAVX512()))
26053 SDValue A = N->getOperand(0);
26054 SDValue B = N->getOperand(1);
26055 SDValue C = N->getOperand(2);
26057 bool NegA = (A.getOpcode() == ISD::FNEG);
26058 bool NegB = (B.getOpcode() == ISD::FNEG);
26059 bool NegC = (C.getOpcode() == ISD::FNEG);
26061 // Negative multiplication when NegA xor NegB
26062 bool NegMul = (NegA != NegB);
26064 A = A.getOperand(0);
26066 B = B.getOperand(0);
26068 C = C.getOperand(0);
26072 Opcode = (!NegC) ? X86ISD::FMADD : X86ISD::FMSUB;
26074 Opcode = (!NegC) ? X86ISD::FNMADD : X86ISD::FNMSUB;
26076 return DAG.getNode(Opcode, dl, VT, A, B, C);
26079 static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG,
26080 TargetLowering::DAGCombinerInfo &DCI,
26081 const X86Subtarget *Subtarget) {
26082 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) ->
26083 // (and (i32 x86isd::setcc_carry), 1)
26084 // This eliminates the zext. This transformation is necessary because
26085 // ISD::SETCC is always legalized to i8.
26087 SDValue N0 = N->getOperand(0);
26088 EVT VT = N->getValueType(0);
26090 if (N0.getOpcode() == ISD::AND &&
26092 N0.getOperand(0).hasOneUse()) {
26093 SDValue N00 = N0.getOperand(0);
26094 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
26095 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
26096 if (!C || C->getZExtValue() != 1)
26098 return DAG.getNode(ISD::AND, dl, VT,
26099 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
26100 N00.getOperand(0), N00.getOperand(1)),
26101 DAG.getConstant(1, dl, VT));
26105 if (N0.getOpcode() == ISD::TRUNCATE &&
26107 N0.getOperand(0).hasOneUse()) {
26108 SDValue N00 = N0.getOperand(0);
26109 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
26110 return DAG.getNode(ISD::AND, dl, VT,
26111 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
26112 N00.getOperand(0), N00.getOperand(1)),
26113 DAG.getConstant(1, dl, VT));
26117 if (VT.is256BitVector())
26118 if (SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget))
26121 // (i8,i32 zext (udivrem (i8 x, i8 y)) ->
26122 // (i8,i32 (udivrem_zext_hreg (i8 x, i8 y)
26123 // This exposes the zext to the udivrem lowering, so that it directly extends
26124 // from AH (which we otherwise need to do contortions to access).
26125 if (N0.getOpcode() == ISD::UDIVREM &&
26126 N0.getResNo() == 1 && N0.getValueType() == MVT::i8 &&
26127 (VT == MVT::i32 || VT == MVT::i64)) {
26128 SDVTList NodeTys = DAG.getVTList(MVT::i8, VT);
26129 SDValue R = DAG.getNode(X86ISD::UDIVREM8_ZEXT_HREG, dl, NodeTys,
26130 N0.getOperand(0), N0.getOperand(1));
26131 DAG.ReplaceAllUsesOfValueWith(N0.getValue(0), R.getValue(0));
26132 return R.getValue(1);
26138 // Optimize x == -y --> x+y == 0
26139 // x != -y --> x+y != 0
26140 static SDValue PerformISDSETCCCombine(SDNode *N, SelectionDAG &DAG,
26141 const X86Subtarget* Subtarget) {
26142 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
26143 SDValue LHS = N->getOperand(0);
26144 SDValue RHS = N->getOperand(1);
26145 EVT VT = N->getValueType(0);
26148 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && LHS.getOpcode() == ISD::SUB)
26149 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(LHS.getOperand(0)))
26150 if (C->getAPIntValue() == 0 && LHS.hasOneUse()) {
26151 SDValue addV = DAG.getNode(ISD::ADD, DL, LHS.getValueType(), RHS,
26152 LHS.getOperand(1));
26153 return DAG.getSetCC(DL, N->getValueType(0), addV,
26154 DAG.getConstant(0, DL, addV.getValueType()), CC);
26156 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && RHS.getOpcode() == ISD::SUB)
26157 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS.getOperand(0)))
26158 if (C->getAPIntValue() == 0 && RHS.hasOneUse()) {
26159 SDValue addV = DAG.getNode(ISD::ADD, DL, RHS.getValueType(), LHS,
26160 RHS.getOperand(1));
26161 return DAG.getSetCC(DL, N->getValueType(0), addV,
26162 DAG.getConstant(0, DL, addV.getValueType()), CC);
26165 if (VT.getScalarType() == MVT::i1 &&
26166 (CC == ISD::SETNE || CC == ISD::SETEQ || ISD::isSignedIntSetCC(CC))) {
26168 (LHS.getOpcode() == ISD::SIGN_EXTEND) &&
26169 (LHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
26170 bool IsVZero1 = ISD::isBuildVectorAllZeros(RHS.getNode());
26172 if (!IsSEXT0 || !IsVZero1) {
26173 // Swap the operands and update the condition code.
26174 std::swap(LHS, RHS);
26175 CC = ISD::getSetCCSwappedOperands(CC);
26177 IsSEXT0 = (LHS.getOpcode() == ISD::SIGN_EXTEND) &&
26178 (LHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
26179 IsVZero1 = ISD::isBuildVectorAllZeros(RHS.getNode());
26182 if (IsSEXT0 && IsVZero1) {
26183 assert(VT == LHS.getOperand(0).getValueType() &&
26184 "Uexpected operand type");
26185 if (CC == ISD::SETGT)
26186 return DAG.getConstant(0, DL, VT);
26187 if (CC == ISD::SETLE)
26188 return DAG.getConstant(1, DL, VT);
26189 if (CC == ISD::SETEQ || CC == ISD::SETGE)
26190 return DAG.getNOT(DL, LHS.getOperand(0), VT);
26192 assert((CC == ISD::SETNE || CC == ISD::SETLT) &&
26193 "Unexpected condition code!");
26194 return LHS.getOperand(0);
26201 static SDValue NarrowVectorLoadToElement(LoadSDNode *Load, unsigned Index,
26202 SelectionDAG &DAG) {
26204 MVT VT = Load->getSimpleValueType(0);
26205 MVT EVT = VT.getVectorElementType();
26206 SDValue Addr = Load->getOperand(1);
26207 SDValue NewAddr = DAG.getNode(
26208 ISD::ADD, dl, Addr.getSimpleValueType(), Addr,
26209 DAG.getConstant(Index * EVT.getStoreSize(), dl,
26210 Addr.getSimpleValueType()));
26213 DAG.getLoad(EVT, dl, Load->getChain(), NewAddr,
26214 DAG.getMachineFunction().getMachineMemOperand(
26215 Load->getMemOperand(), 0, EVT.getStoreSize()));
26219 static SDValue PerformINSERTPSCombine(SDNode *N, SelectionDAG &DAG,
26220 const X86Subtarget *Subtarget) {
26222 MVT VT = N->getOperand(1)->getSimpleValueType(0);
26223 assert((VT == MVT::v4f32 || VT == MVT::v4i32) &&
26224 "X86insertps is only defined for v4x32");
26226 SDValue Ld = N->getOperand(1);
26227 if (MayFoldLoad(Ld)) {
26228 // Extract the countS bits from the immediate so we can get the proper
26229 // address when narrowing the vector load to a specific element.
26230 // When the second source op is a memory address, insertps doesn't use
26231 // countS and just gets an f32 from that address.
26232 unsigned DestIndex =
26233 cast<ConstantSDNode>(N->getOperand(2))->getZExtValue() >> 6;
26235 Ld = NarrowVectorLoadToElement(cast<LoadSDNode>(Ld), DestIndex, DAG);
26237 // Create this as a scalar to vector to match the instruction pattern.
26238 SDValue LoadScalarToVector = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Ld);
26239 // countS bits are ignored when loading from memory on insertps, which
26240 // means we don't need to explicitly set them to 0.
26241 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N->getOperand(0),
26242 LoadScalarToVector, N->getOperand(2));
26247 static SDValue PerformBLENDICombine(SDNode *N, SelectionDAG &DAG) {
26248 SDValue V0 = N->getOperand(0);
26249 SDValue V1 = N->getOperand(1);
26251 EVT VT = N->getValueType(0);
26253 // Canonicalize a v2f64 blend with a mask of 2 by swapping the vector
26254 // operands and changing the mask to 1. This saves us a bunch of
26255 // pattern-matching possibilities related to scalar math ops in SSE/AVX.
26256 // x86InstrInfo knows how to commute this back after instruction selection
26257 // if it would help register allocation.
26259 // TODO: If optimizing for size or a processor that doesn't suffer from
26260 // partial register update stalls, this should be transformed into a MOVSD
26261 // instruction because a MOVSD is 1-2 bytes smaller than a BLENDPD.
26263 if (VT == MVT::v2f64)
26264 if (auto *Mask = dyn_cast<ConstantSDNode>(N->getOperand(2)))
26265 if (Mask->getZExtValue() == 2 && !isShuffleFoldableLoad(V0)) {
26266 SDValue NewMask = DAG.getConstant(1, DL, MVT::i8);
26267 return DAG.getNode(X86ISD::BLENDI, DL, VT, V1, V0, NewMask);
26273 // Helper function of PerformSETCCCombine. It is to materialize "setb reg"
26274 // as "sbb reg,reg", since it can be extended without zext and produces
26275 // an all-ones bit which is more useful than 0/1 in some cases.
26276 static SDValue MaterializeSETB(SDLoc DL, SDValue EFLAGS, SelectionDAG &DAG,
26279 return DAG.getNode(ISD::AND, DL, VT,
26280 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
26281 DAG.getConstant(X86::COND_B, DL, MVT::i8),
26283 DAG.getConstant(1, DL, VT));
26284 assert (VT == MVT::i1 && "Unexpected type for SECCC node");
26285 return DAG.getNode(ISD::TRUNCATE, DL, MVT::i1,
26286 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
26287 DAG.getConstant(X86::COND_B, DL, MVT::i8),
26291 // Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT
26292 static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG,
26293 TargetLowering::DAGCombinerInfo &DCI,
26294 const X86Subtarget *Subtarget) {
26296 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(0));
26297 SDValue EFLAGS = N->getOperand(1);
26299 if (CC == X86::COND_A) {
26300 // Try to convert COND_A into COND_B in an attempt to facilitate
26301 // materializing "setb reg".
26303 // Do not flip "e > c", where "c" is a constant, because Cmp instruction
26304 // cannot take an immediate as its first operand.
26306 if (EFLAGS.getOpcode() == X86ISD::SUB && EFLAGS.hasOneUse() &&
26307 EFLAGS.getValueType().isInteger() &&
26308 !isa<ConstantSDNode>(EFLAGS.getOperand(1))) {
26309 SDValue NewSub = DAG.getNode(X86ISD::SUB, SDLoc(EFLAGS),
26310 EFLAGS.getNode()->getVTList(),
26311 EFLAGS.getOperand(1), EFLAGS.getOperand(0));
26312 SDValue NewEFLAGS = SDValue(NewSub.getNode(), EFLAGS.getResNo());
26313 return MaterializeSETB(DL, NewEFLAGS, DAG, N->getSimpleValueType(0));
26317 // Materialize "setb reg" as "sbb reg,reg", since it can be extended without
26318 // a zext and produces an all-ones bit which is more useful than 0/1 in some
26320 if (CC == X86::COND_B)
26321 return MaterializeSETB(DL, EFLAGS, DAG, N->getSimpleValueType(0));
26323 if (SDValue Flags = checkBoolTestSetCCCombine(EFLAGS, CC)) {
26324 SDValue Cond = DAG.getConstant(CC, DL, MVT::i8);
26325 return DAG.getNode(X86ISD::SETCC, DL, N->getVTList(), Cond, Flags);
26331 // Optimize branch condition evaluation.
26333 static SDValue PerformBrCondCombine(SDNode *N, SelectionDAG &DAG,
26334 TargetLowering::DAGCombinerInfo &DCI,
26335 const X86Subtarget *Subtarget) {
26337 SDValue Chain = N->getOperand(0);
26338 SDValue Dest = N->getOperand(1);
26339 SDValue EFLAGS = N->getOperand(3);
26340 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(2));
26342 if (SDValue Flags = checkBoolTestSetCCCombine(EFLAGS, CC)) {
26343 SDValue Cond = DAG.getConstant(CC, DL, MVT::i8);
26344 return DAG.getNode(X86ISD::BRCOND, DL, N->getVTList(), Chain, Dest, Cond,
26351 static SDValue performVectorCompareAndMaskUnaryOpCombine(SDNode *N,
26352 SelectionDAG &DAG) {
26353 // Take advantage of vector comparisons producing 0 or -1 in each lane to
26354 // optimize away operation when it's from a constant.
26356 // The general transformation is:
26357 // UNARYOP(AND(VECTOR_CMP(x,y), constant)) -->
26358 // AND(VECTOR_CMP(x,y), constant2)
26359 // constant2 = UNARYOP(constant)
26361 // Early exit if this isn't a vector operation, the operand of the
26362 // unary operation isn't a bitwise AND, or if the sizes of the operations
26363 // aren't the same.
26364 EVT VT = N->getValueType(0);
26365 if (!VT.isVector() || N->getOperand(0)->getOpcode() != ISD::AND ||
26366 N->getOperand(0)->getOperand(0)->getOpcode() != ISD::SETCC ||
26367 VT.getSizeInBits() != N->getOperand(0)->getValueType(0).getSizeInBits())
26370 // Now check that the other operand of the AND is a constant. We could
26371 // make the transformation for non-constant splats as well, but it's unclear
26372 // that would be a benefit as it would not eliminate any operations, just
26373 // perform one more step in scalar code before moving to the vector unit.
26374 if (BuildVectorSDNode *BV =
26375 dyn_cast<BuildVectorSDNode>(N->getOperand(0)->getOperand(1))) {
26376 // Bail out if the vector isn't a constant.
26377 if (!BV->isConstant())
26380 // Everything checks out. Build up the new and improved node.
26382 EVT IntVT = BV->getValueType(0);
26383 // Create a new constant of the appropriate type for the transformed
26385 SDValue SourceConst = DAG.getNode(N->getOpcode(), DL, VT, SDValue(BV, 0));
26386 // The AND node needs bitcasts to/from an integer vector type around it.
26387 SDValue MaskConst = DAG.getBitcast(IntVT, SourceConst);
26388 SDValue NewAnd = DAG.getNode(ISD::AND, DL, IntVT,
26389 N->getOperand(0)->getOperand(0), MaskConst);
26390 SDValue Res = DAG.getBitcast(VT, NewAnd);
26397 static SDValue PerformUINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
26398 const X86Subtarget *Subtarget) {
26399 SDValue Op0 = N->getOperand(0);
26400 EVT VT = N->getValueType(0);
26401 EVT InVT = Op0.getValueType();
26402 EVT InSVT = InVT.getScalarType();
26403 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
26405 // UINT_TO_FP(vXi8) -> SINT_TO_FP(ZEXT(vXi8 to vXi32))
26406 // UINT_TO_FP(vXi16) -> SINT_TO_FP(ZEXT(vXi16 to vXi32))
26407 if (InVT.isVector() && (InSVT == MVT::i8 || InSVT == MVT::i16)) {
26409 EVT DstVT = EVT::getVectorVT(*DAG.getContext(), MVT::i32,
26410 InVT.getVectorNumElements());
26411 SDValue P = DAG.getNode(ISD::ZERO_EXTEND, dl, DstVT, Op0);
26413 if (TLI.isOperationLegal(ISD::UINT_TO_FP, DstVT))
26414 return DAG.getNode(ISD::UINT_TO_FP, dl, VT, P);
26416 return DAG.getNode(ISD::SINT_TO_FP, dl, VT, P);
26422 static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
26423 const X86Subtarget *Subtarget) {
26424 // First try to optimize away the conversion entirely when it's
26425 // conditionally from a constant. Vectors only.
26426 if (SDValue Res = performVectorCompareAndMaskUnaryOpCombine(N, DAG))
26429 // Now move on to more general possibilities.
26430 SDValue Op0 = N->getOperand(0);
26431 EVT VT = N->getValueType(0);
26432 EVT InVT = Op0.getValueType();
26433 EVT InSVT = InVT.getScalarType();
26435 // SINT_TO_FP(vXi8) -> SINT_TO_FP(SEXT(vXi8 to vXi32))
26436 // SINT_TO_FP(vXi16) -> SINT_TO_FP(SEXT(vXi16 to vXi32))
26437 if (InVT.isVector() && (InSVT == MVT::i8 || InSVT == MVT::i16)) {
26439 EVT DstVT = EVT::getVectorVT(*DAG.getContext(), MVT::i32,
26440 InVT.getVectorNumElements());
26441 SDValue P = DAG.getNode(ISD::SIGN_EXTEND, dl, DstVT, Op0);
26442 return DAG.getNode(ISD::SINT_TO_FP, dl, VT, P);
26445 // Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have
26446 // a 32-bit target where SSE doesn't support i64->FP operations.
26447 if (Op0.getOpcode() == ISD::LOAD) {
26448 LoadSDNode *Ld = cast<LoadSDNode>(Op0.getNode());
26449 EVT LdVT = Ld->getValueType(0);
26451 // This transformation is not supported if the result type is f16
26452 if (VT == MVT::f16)
26455 if (!Ld->isVolatile() && !VT.isVector() &&
26456 ISD::isNON_EXTLoad(Op0.getNode()) && Op0.hasOneUse() &&
26457 !Subtarget->is64Bit() && LdVT == MVT::i64) {
26458 SDValue FILDChain = Subtarget->getTargetLowering()->BuildFILD(
26459 SDValue(N, 0), LdVT, Ld->getChain(), Op0, DAG);
26460 DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), FILDChain.getValue(1));
26467 // Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS
26468 static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG,
26469 X86TargetLowering::DAGCombinerInfo &DCI) {
26470 // If the LHS and RHS of the ADC node are zero, then it can't overflow and
26471 // the result is either zero or one (depending on the input carry bit).
26472 // Strength reduce this down to a "set on carry" aka SETCC_CARRY&1.
26473 if (X86::isZeroNode(N->getOperand(0)) &&
26474 X86::isZeroNode(N->getOperand(1)) &&
26475 // We don't have a good way to replace an EFLAGS use, so only do this when
26477 SDValue(N, 1).use_empty()) {
26479 EVT VT = N->getValueType(0);
26480 SDValue CarryOut = DAG.getConstant(0, DL, N->getValueType(1));
26481 SDValue Res1 = DAG.getNode(ISD::AND, DL, VT,
26482 DAG.getNode(X86ISD::SETCC_CARRY, DL, VT,
26483 DAG.getConstant(X86::COND_B, DL,
26486 DAG.getConstant(1, DL, VT));
26487 return DCI.CombineTo(N, Res1, CarryOut);
26493 // fold (add Y, (sete X, 0)) -> adc 0, Y
26494 // (add Y, (setne X, 0)) -> sbb -1, Y
26495 // (sub (sete X, 0), Y) -> sbb 0, Y
26496 // (sub (setne X, 0), Y) -> adc -1, Y
26497 static SDValue OptimizeConditionalInDecrement(SDNode *N, SelectionDAG &DAG) {
26500 // Look through ZExts.
26501 SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0);
26502 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse())
26505 SDValue SetCC = Ext.getOperand(0);
26506 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse())
26509 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0);
26510 if (CC != X86::COND_E && CC != X86::COND_NE)
26513 SDValue Cmp = SetCC.getOperand(1);
26514 if (Cmp.getOpcode() != X86ISD::CMP || !Cmp.hasOneUse() ||
26515 !X86::isZeroNode(Cmp.getOperand(1)) ||
26516 !Cmp.getOperand(0).getValueType().isInteger())
26519 SDValue CmpOp0 = Cmp.getOperand(0);
26520 SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, CmpOp0,
26521 DAG.getConstant(1, DL, CmpOp0.getValueType()));
26523 SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1);
26524 if (CC == X86::COND_NE)
26525 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB,
26526 DL, OtherVal.getValueType(), OtherVal,
26527 DAG.getConstant(-1ULL, DL, OtherVal.getValueType()),
26529 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC,
26530 DL, OtherVal.getValueType(), OtherVal,
26531 DAG.getConstant(0, DL, OtherVal.getValueType()), NewCmp);
26534 /// PerformADDCombine - Do target-specific dag combines on integer adds.
26535 static SDValue PerformAddCombine(SDNode *N, SelectionDAG &DAG,
26536 const X86Subtarget *Subtarget) {
26537 EVT VT = N->getValueType(0);
26538 SDValue Op0 = N->getOperand(0);
26539 SDValue Op1 = N->getOperand(1);
26541 // Try to synthesize horizontal adds from adds of shuffles.
26542 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
26543 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
26544 isHorizontalBinOp(Op0, Op1, true))
26545 return DAG.getNode(X86ISD::HADD, SDLoc(N), VT, Op0, Op1);
26547 return OptimizeConditionalInDecrement(N, DAG);
26550 static SDValue PerformSubCombine(SDNode *N, SelectionDAG &DAG,
26551 const X86Subtarget *Subtarget) {
26552 SDValue Op0 = N->getOperand(0);
26553 SDValue Op1 = N->getOperand(1);
26555 // X86 can't encode an immediate LHS of a sub. See if we can push the
26556 // negation into a preceding instruction.
26557 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op0)) {
26558 // If the RHS of the sub is a XOR with one use and a constant, invert the
26559 // immediate. Then add one to the LHS of the sub so we can turn
26560 // X-Y -> X+~Y+1, saving one register.
26561 if (Op1->hasOneUse() && Op1.getOpcode() == ISD::XOR &&
26562 isa<ConstantSDNode>(Op1.getOperand(1))) {
26563 APInt XorC = cast<ConstantSDNode>(Op1.getOperand(1))->getAPIntValue();
26564 EVT VT = Op0.getValueType();
26565 SDValue NewXor = DAG.getNode(ISD::XOR, SDLoc(Op1), VT,
26567 DAG.getConstant(~XorC, SDLoc(Op1), VT));
26568 return DAG.getNode(ISD::ADD, SDLoc(N), VT, NewXor,
26569 DAG.getConstant(C->getAPIntValue() + 1, SDLoc(N), VT));
26573 // Try to synthesize horizontal adds from adds of shuffles.
26574 EVT VT = N->getValueType(0);
26575 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
26576 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
26577 isHorizontalBinOp(Op0, Op1, true))
26578 return DAG.getNode(X86ISD::HSUB, SDLoc(N), VT, Op0, Op1);
26580 return OptimizeConditionalInDecrement(N, DAG);
26583 /// performVZEXTCombine - Performs build vector combines
26584 static SDValue performVZEXTCombine(SDNode *N, SelectionDAG &DAG,
26585 TargetLowering::DAGCombinerInfo &DCI,
26586 const X86Subtarget *Subtarget) {
26588 MVT VT = N->getSimpleValueType(0);
26589 SDValue Op = N->getOperand(0);
26590 MVT OpVT = Op.getSimpleValueType();
26591 MVT OpEltVT = OpVT.getVectorElementType();
26592 unsigned InputBits = OpEltVT.getSizeInBits() * VT.getVectorNumElements();
26594 // (vzext (bitcast (vzext (x)) -> (vzext x)
26596 while (V.getOpcode() == ISD::BITCAST)
26597 V = V.getOperand(0);
26599 if (V != Op && V.getOpcode() == X86ISD::VZEXT) {
26600 MVT InnerVT = V.getSimpleValueType();
26601 MVT InnerEltVT = InnerVT.getVectorElementType();
26603 // If the element sizes match exactly, we can just do one larger vzext. This
26604 // is always an exact type match as vzext operates on integer types.
26605 if (OpEltVT == InnerEltVT) {
26606 assert(OpVT == InnerVT && "Types must match for vzext!");
26607 return DAG.getNode(X86ISD::VZEXT, DL, VT, V.getOperand(0));
26610 // The only other way we can combine them is if only a single element of the
26611 // inner vzext is used in the input to the outer vzext.
26612 if (InnerEltVT.getSizeInBits() < InputBits)
26615 // In this case, the inner vzext is completely dead because we're going to
26616 // only look at bits inside of the low element. Just do the outer vzext on
26617 // a bitcast of the input to the inner.
26618 return DAG.getNode(X86ISD::VZEXT, DL, VT, DAG.getBitcast(OpVT, V));
26621 // Check if we can bypass extracting and re-inserting an element of an input
26622 // vector. Essentially:
26623 // (bitcast (sclr2vec (ext_vec_elt x))) -> (bitcast x)
26624 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR &&
26625 V.getOperand(0).getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
26626 V.getOperand(0).getSimpleValueType().getSizeInBits() == InputBits) {
26627 SDValue ExtractedV = V.getOperand(0);
26628 SDValue OrigV = ExtractedV.getOperand(0);
26629 if (auto *ExtractIdx = dyn_cast<ConstantSDNode>(ExtractedV.getOperand(1)))
26630 if (ExtractIdx->getZExtValue() == 0) {
26631 MVT OrigVT = OrigV.getSimpleValueType();
26632 // Extract a subvector if necessary...
26633 if (OrigVT.getSizeInBits() > OpVT.getSizeInBits()) {
26634 int Ratio = OrigVT.getSizeInBits() / OpVT.getSizeInBits();
26635 OrigVT = MVT::getVectorVT(OrigVT.getVectorElementType(),
26636 OrigVT.getVectorNumElements() / Ratio);
26637 OrigV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, OrigVT, OrigV,
26638 DAG.getIntPtrConstant(0, DL));
26640 Op = DAG.getBitcast(OpVT, OrigV);
26641 return DAG.getNode(X86ISD::VZEXT, DL, VT, Op);
26648 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
26649 DAGCombinerInfo &DCI) const {
26650 SelectionDAG &DAG = DCI.DAG;
26651 switch (N->getOpcode()) {
26653 case ISD::EXTRACT_VECTOR_ELT:
26654 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, DCI);
26657 case X86ISD::SHRUNKBLEND:
26658 return PerformSELECTCombine(N, DAG, DCI, Subtarget);
26659 case ISD::BITCAST: return PerformBITCASTCombine(N, DAG, Subtarget);
26660 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI, Subtarget);
26661 case ISD::ADD: return PerformAddCombine(N, DAG, Subtarget);
26662 case ISD::SUB: return PerformSubCombine(N, DAG, Subtarget);
26663 case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI);
26664 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
26667 case ISD::SRL: return PerformShiftCombine(N, DAG, DCI, Subtarget);
26668 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget);
26669 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget);
26670 case ISD::XOR: return PerformXorCombine(N, DAG, DCI, Subtarget);
26671 case ISD::LOAD: return PerformLOADCombine(N, DAG, DCI, Subtarget);
26672 case ISD::MLOAD: return PerformMLOADCombine(N, DAG, DCI, Subtarget);
26673 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
26674 case ISD::MSTORE: return PerformMSTORECombine(N, DAG, Subtarget);
26675 case ISD::SINT_TO_FP: return PerformSINT_TO_FPCombine(N, DAG, Subtarget);
26676 case ISD::UINT_TO_FP: return PerformUINT_TO_FPCombine(N, DAG, Subtarget);
26677 case ISD::FADD: return PerformFADDCombine(N, DAG, Subtarget);
26678 case ISD::FSUB: return PerformFSUBCombine(N, DAG, Subtarget);
26680 case X86ISD::FOR: return PerformFORCombine(N, DAG, Subtarget);
26682 case X86ISD::FMAX: return PerformFMinFMaxCombine(N, DAG);
26683 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
26684 case X86ISD::FANDN: return PerformFANDNCombine(N, DAG);
26685 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
26686 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
26687 case ISD::ANY_EXTEND:
26688 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG, DCI, Subtarget);
26689 case ISD::SIGN_EXTEND: return PerformSExtCombine(N, DAG, DCI, Subtarget);
26690 case ISD::SIGN_EXTEND_INREG:
26691 return PerformSIGN_EXTEND_INREGCombine(N, DAG, Subtarget);
26692 case ISD::SETCC: return PerformISDSETCCCombine(N, DAG, Subtarget);
26693 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG, DCI, Subtarget);
26694 case X86ISD::BRCOND: return PerformBrCondCombine(N, DAG, DCI, Subtarget);
26695 case X86ISD::VZEXT: return performVZEXTCombine(N, DAG, DCI, Subtarget);
26696 case X86ISD::SHUFP: // Handle all target specific shuffles
26697 case X86ISD::PALIGNR:
26698 case X86ISD::UNPCKH:
26699 case X86ISD::UNPCKL:
26700 case X86ISD::MOVHLPS:
26701 case X86ISD::MOVLHPS:
26702 case X86ISD::PSHUFB:
26703 case X86ISD::PSHUFD:
26704 case X86ISD::PSHUFHW:
26705 case X86ISD::PSHUFLW:
26706 case X86ISD::MOVSS:
26707 case X86ISD::MOVSD:
26708 case X86ISD::VPERMILPI:
26709 case X86ISD::VPERM2X128:
26710 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget);
26711 case ISD::FMA: return PerformFMACombine(N, DAG, Subtarget);
26712 case X86ISD::INSERTPS: {
26713 if (getTargetMachine().getOptLevel() > CodeGenOpt::None)
26714 return PerformINSERTPSCombine(N, DAG, Subtarget);
26717 case X86ISD::BLENDI: return PerformBLENDICombine(N, DAG);
26723 /// isTypeDesirableForOp - Return true if the target has native support for
26724 /// the specified value type and it is 'desirable' to use the type for the
26725 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
26726 /// instruction encodings are longer and some i16 instructions are slow.
26727 bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const {
26728 if (!isTypeLegal(VT))
26730 if (VT != MVT::i16)
26737 case ISD::SIGN_EXTEND:
26738 case ISD::ZERO_EXTEND:
26739 case ISD::ANY_EXTEND:
26752 /// IsDesirableToPromoteOp - This method query the target whether it is
26753 /// beneficial for dag combiner to promote the specified node. If true, it
26754 /// should return the desired promotion type by reference.
26755 bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
26756 EVT VT = Op.getValueType();
26757 if (VT != MVT::i16)
26760 bool Promote = false;
26761 bool Commute = false;
26762 switch (Op.getOpcode()) {
26765 LoadSDNode *LD = cast<LoadSDNode>(Op);
26766 // If the non-extending load has a single use and it's not live out, then it
26767 // might be folded.
26768 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&&
26769 Op.hasOneUse()*/) {
26770 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
26771 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
26772 // The only case where we'd want to promote LOAD (rather then it being
26773 // promoted as an operand is when it's only use is liveout.
26774 if (UI->getOpcode() != ISD::CopyToReg)
26781 case ISD::SIGN_EXTEND:
26782 case ISD::ZERO_EXTEND:
26783 case ISD::ANY_EXTEND:
26788 SDValue N0 = Op.getOperand(0);
26789 // Look out for (store (shl (load), x)).
26790 if (MayFoldLoad(N0) && MayFoldIntoStore(Op))
26803 SDValue N0 = Op.getOperand(0);
26804 SDValue N1 = Op.getOperand(1);
26805 if (!Commute && MayFoldLoad(N1))
26807 // Avoid disabling potential load folding opportunities.
26808 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op)))
26810 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op)))
26820 //===----------------------------------------------------------------------===//
26821 // X86 Inline Assembly Support
26822 //===----------------------------------------------------------------------===//
26824 // Helper to match a string separated by whitespace.
26825 static bool matchAsm(StringRef S, ArrayRef<const char *> Pieces) {
26826 S = S.substr(S.find_first_not_of(" \t")); // Skip leading whitespace.
26828 for (StringRef Piece : Pieces) {
26829 if (!S.startswith(Piece)) // Check if the piece matches.
26832 S = S.substr(Piece.size());
26833 StringRef::size_type Pos = S.find_first_not_of(" \t");
26834 if (Pos == 0) // We matched a prefix.
26843 static bool clobbersFlagRegisters(const SmallVector<StringRef, 4> &AsmPieces) {
26845 if (AsmPieces.size() == 3 || AsmPieces.size() == 4) {
26846 if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{cc}") &&
26847 std::count(AsmPieces.begin(), AsmPieces.end(), "~{flags}") &&
26848 std::count(AsmPieces.begin(), AsmPieces.end(), "~{fpsr}")) {
26850 if (AsmPieces.size() == 3)
26852 else if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{dirflag}"))
26859 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
26860 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
26862 std::string AsmStr = IA->getAsmString();
26864 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
26865 if (!Ty || Ty->getBitWidth() % 16 != 0)
26868 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
26869 SmallVector<StringRef, 4> AsmPieces;
26870 SplitString(AsmStr, AsmPieces, ";\n");
26872 switch (AsmPieces.size()) {
26873 default: return false;
26875 // FIXME: this should verify that we are targeting a 486 or better. If not,
26876 // we will turn this bswap into something that will be lowered to logical
26877 // ops instead of emitting the bswap asm. For now, we don't support 486 or
26878 // lower so don't worry about this.
26880 if (matchAsm(AsmPieces[0], {"bswap", "$0"}) ||
26881 matchAsm(AsmPieces[0], {"bswapl", "$0"}) ||
26882 matchAsm(AsmPieces[0], {"bswapq", "$0"}) ||
26883 matchAsm(AsmPieces[0], {"bswap", "${0:q}"}) ||
26884 matchAsm(AsmPieces[0], {"bswapl", "${0:q}"}) ||
26885 matchAsm(AsmPieces[0], {"bswapq", "${0:q}"})) {
26886 // No need to check constraints, nothing other than the equivalent of
26887 // "=r,0" would be valid here.
26888 return IntrinsicLowering::LowerToByteSwap(CI);
26891 // rorw $$8, ${0:w} --> llvm.bswap.i16
26892 if (CI->getType()->isIntegerTy(16) &&
26893 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
26894 (matchAsm(AsmPieces[0], {"rorw", "$$8,", "${0:w}"}) ||
26895 matchAsm(AsmPieces[0], {"rolw", "$$8,", "${0:w}"}))) {
26897 StringRef ConstraintsStr = IA->getConstraintString();
26898 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
26899 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
26900 if (clobbersFlagRegisters(AsmPieces))
26901 return IntrinsicLowering::LowerToByteSwap(CI);
26905 if (CI->getType()->isIntegerTy(32) &&
26906 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
26907 matchAsm(AsmPieces[0], {"rorw", "$$8,", "${0:w}"}) &&
26908 matchAsm(AsmPieces[1], {"rorl", "$$16,", "$0"}) &&
26909 matchAsm(AsmPieces[2], {"rorw", "$$8,", "${0:w}"})) {
26911 StringRef ConstraintsStr = IA->getConstraintString();
26912 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
26913 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
26914 if (clobbersFlagRegisters(AsmPieces))
26915 return IntrinsicLowering::LowerToByteSwap(CI);
26918 if (CI->getType()->isIntegerTy(64)) {
26919 InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints();
26920 if (Constraints.size() >= 2 &&
26921 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
26922 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
26923 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
26924 if (matchAsm(AsmPieces[0], {"bswap", "%eax"}) &&
26925 matchAsm(AsmPieces[1], {"bswap", "%edx"}) &&
26926 matchAsm(AsmPieces[2], {"xchgl", "%eax,", "%edx"}))
26927 return IntrinsicLowering::LowerToByteSwap(CI);
26935 /// getConstraintType - Given a constraint letter, return the type of
26936 /// constraint it is for this target.
26937 X86TargetLowering::ConstraintType
26938 X86TargetLowering::getConstraintType(StringRef Constraint) const {
26939 if (Constraint.size() == 1) {
26940 switch (Constraint[0]) {
26951 return C_RegisterClass;
26975 return TargetLowering::getConstraintType(Constraint);
26978 /// Examine constraint type and operand type and determine a weight value.
26979 /// This object must already have been set up with the operand type
26980 /// and the current alternative constraint selected.
26981 TargetLowering::ConstraintWeight
26982 X86TargetLowering::getSingleConstraintMatchWeight(
26983 AsmOperandInfo &info, const char *constraint) const {
26984 ConstraintWeight weight = CW_Invalid;
26985 Value *CallOperandVal = info.CallOperandVal;
26986 // If we don't have a value, we can't do a match,
26987 // but allow it at the lowest weight.
26988 if (!CallOperandVal)
26990 Type *type = CallOperandVal->getType();
26991 // Look at the constraint type.
26992 switch (*constraint) {
26994 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
27005 if (CallOperandVal->getType()->isIntegerTy())
27006 weight = CW_SpecificReg;
27011 if (type->isFloatingPointTy())
27012 weight = CW_SpecificReg;
27015 if (type->isX86_MMXTy() && Subtarget->hasMMX())
27016 weight = CW_SpecificReg;
27020 if (((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasSSE1()) ||
27021 ((type->getPrimitiveSizeInBits() == 256) && Subtarget->hasFp256()))
27022 weight = CW_Register;
27025 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) {
27026 if (C->getZExtValue() <= 31)
27027 weight = CW_Constant;
27031 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
27032 if (C->getZExtValue() <= 63)
27033 weight = CW_Constant;
27037 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
27038 if ((C->getSExtValue() >= -0x80) && (C->getSExtValue() <= 0x7f))
27039 weight = CW_Constant;
27043 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
27044 if ((C->getZExtValue() == 0xff) || (C->getZExtValue() == 0xffff))
27045 weight = CW_Constant;
27049 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
27050 if (C->getZExtValue() <= 3)
27051 weight = CW_Constant;
27055 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
27056 if (C->getZExtValue() <= 0xff)
27057 weight = CW_Constant;
27062 if (isa<ConstantFP>(CallOperandVal)) {
27063 weight = CW_Constant;
27067 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
27068 if ((C->getSExtValue() >= -0x80000000LL) &&
27069 (C->getSExtValue() <= 0x7fffffffLL))
27070 weight = CW_Constant;
27074 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
27075 if (C->getZExtValue() <= 0xffffffff)
27076 weight = CW_Constant;
27083 /// LowerXConstraint - try to replace an X constraint, which matches anything,
27084 /// with another that has more specific requirements based on the type of the
27085 /// corresponding operand.
27086 const char *X86TargetLowering::
27087 LowerXConstraint(EVT ConstraintVT) const {
27088 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
27089 // 'f' like normal targets.
27090 if (ConstraintVT.isFloatingPoint()) {
27091 if (Subtarget->hasSSE2())
27093 if (Subtarget->hasSSE1())
27097 return TargetLowering::LowerXConstraint(ConstraintVT);
27100 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
27101 /// vector. If it is invalid, don't add anything to Ops.
27102 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
27103 std::string &Constraint,
27104 std::vector<SDValue>&Ops,
27105 SelectionDAG &DAG) const {
27108 // Only support length 1 constraints for now.
27109 if (Constraint.length() > 1) return;
27111 char ConstraintLetter = Constraint[0];
27112 switch (ConstraintLetter) {
27115 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
27116 if (C->getZExtValue() <= 31) {
27117 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
27118 Op.getValueType());
27124 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
27125 if (C->getZExtValue() <= 63) {
27126 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
27127 Op.getValueType());
27133 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
27134 if (isInt<8>(C->getSExtValue())) {
27135 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
27136 Op.getValueType());
27142 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
27143 if (C->getZExtValue() == 0xff || C->getZExtValue() == 0xffff ||
27144 (Subtarget->is64Bit() && C->getZExtValue() == 0xffffffff)) {
27145 Result = DAG.getTargetConstant(C->getSExtValue(), SDLoc(Op),
27146 Op.getValueType());
27152 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
27153 if (C->getZExtValue() <= 3) {
27154 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
27155 Op.getValueType());
27161 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
27162 if (C->getZExtValue() <= 255) {
27163 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
27164 Op.getValueType());
27170 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
27171 if (C->getZExtValue() <= 127) {
27172 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
27173 Op.getValueType());
27179 // 32-bit signed value
27180 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
27181 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
27182 C->getSExtValue())) {
27183 // Widen to 64 bits here to get it sign extended.
27184 Result = DAG.getTargetConstant(C->getSExtValue(), SDLoc(Op), MVT::i64);
27187 // FIXME gcc accepts some relocatable values here too, but only in certain
27188 // memory models; it's complicated.
27193 // 32-bit unsigned value
27194 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
27195 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
27196 C->getZExtValue())) {
27197 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
27198 Op.getValueType());
27202 // FIXME gcc accepts some relocatable values here too, but only in certain
27203 // memory models; it's complicated.
27207 // Literal immediates are always ok.
27208 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
27209 // Widen to 64 bits here to get it sign extended.
27210 Result = DAG.getTargetConstant(CST->getSExtValue(), SDLoc(Op), MVT::i64);
27214 // In any sort of PIC mode addresses need to be computed at runtime by
27215 // adding in a register or some sort of table lookup. These can't
27216 // be used as immediates.
27217 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC())
27220 // If we are in non-pic codegen mode, we allow the address of a global (with
27221 // an optional displacement) to be used with 'i'.
27222 GlobalAddressSDNode *GA = nullptr;
27223 int64_t Offset = 0;
27225 // Match either (GA), (GA+C), (GA+C1+C2), etc.
27227 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
27228 Offset += GA->getOffset();
27230 } else if (Op.getOpcode() == ISD::ADD) {
27231 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
27232 Offset += C->getZExtValue();
27233 Op = Op.getOperand(0);
27236 } else if (Op.getOpcode() == ISD::SUB) {
27237 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
27238 Offset += -C->getZExtValue();
27239 Op = Op.getOperand(0);
27244 // Otherwise, this isn't something we can handle, reject it.
27248 const GlobalValue *GV = GA->getGlobal();
27249 // If we require an extra load to get this address, as in PIC mode, we
27250 // can't accept it.
27251 if (isGlobalStubReference(
27252 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget())))
27255 Result = DAG.getTargetGlobalAddress(GV, SDLoc(Op),
27256 GA->getValueType(0), Offset);
27261 if (Result.getNode()) {
27262 Ops.push_back(Result);
27265 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
27268 std::pair<unsigned, const TargetRegisterClass *>
27269 X86TargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
27270 StringRef Constraint,
27272 // First, see if this is a constraint that directly corresponds to an LLVM
27274 if (Constraint.size() == 1) {
27275 // GCC Constraint Letters
27276 switch (Constraint[0]) {
27278 // TODO: Slight differences here in allocation order and leaving
27279 // RIP in the class. Do they matter any more here than they do
27280 // in the normal allocation?
27281 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
27282 if (Subtarget->is64Bit()) {
27283 if (VT == MVT::i32 || VT == MVT::f32)
27284 return std::make_pair(0U, &X86::GR32RegClass);
27285 if (VT == MVT::i16)
27286 return std::make_pair(0U, &X86::GR16RegClass);
27287 if (VT == MVT::i8 || VT == MVT::i1)
27288 return std::make_pair(0U, &X86::GR8RegClass);
27289 if (VT == MVT::i64 || VT == MVT::f64)
27290 return std::make_pair(0U, &X86::GR64RegClass);
27293 // 32-bit fallthrough
27294 case 'Q': // Q_REGS
27295 if (VT == MVT::i32 || VT == MVT::f32)
27296 return std::make_pair(0U, &X86::GR32_ABCDRegClass);
27297 if (VT == MVT::i16)
27298 return std::make_pair(0U, &X86::GR16_ABCDRegClass);
27299 if (VT == MVT::i8 || VT == MVT::i1)
27300 return std::make_pair(0U, &X86::GR8_ABCD_LRegClass);
27301 if (VT == MVT::i64)
27302 return std::make_pair(0U, &X86::GR64_ABCDRegClass);
27304 case 'r': // GENERAL_REGS
27305 case 'l': // INDEX_REGS
27306 if (VT == MVT::i8 || VT == MVT::i1)
27307 return std::make_pair(0U, &X86::GR8RegClass);
27308 if (VT == MVT::i16)
27309 return std::make_pair(0U, &X86::GR16RegClass);
27310 if (VT == MVT::i32 || VT == MVT::f32 || !Subtarget->is64Bit())
27311 return std::make_pair(0U, &X86::GR32RegClass);
27312 return std::make_pair(0U, &X86::GR64RegClass);
27313 case 'R': // LEGACY_REGS
27314 if (VT == MVT::i8 || VT == MVT::i1)
27315 return std::make_pair(0U, &X86::GR8_NOREXRegClass);
27316 if (VT == MVT::i16)
27317 return std::make_pair(0U, &X86::GR16_NOREXRegClass);
27318 if (VT == MVT::i32 || !Subtarget->is64Bit())
27319 return std::make_pair(0U, &X86::GR32_NOREXRegClass);
27320 return std::make_pair(0U, &X86::GR64_NOREXRegClass);
27321 case 'f': // FP Stack registers.
27322 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
27323 // value to the correct fpstack register class.
27324 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
27325 return std::make_pair(0U, &X86::RFP32RegClass);
27326 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
27327 return std::make_pair(0U, &X86::RFP64RegClass);
27328 return std::make_pair(0U, &X86::RFP80RegClass);
27329 case 'y': // MMX_REGS if MMX allowed.
27330 if (!Subtarget->hasMMX()) break;
27331 return std::make_pair(0U, &X86::VR64RegClass);
27332 case 'Y': // SSE_REGS if SSE2 allowed
27333 if (!Subtarget->hasSSE2()) break;
27335 case 'x': // SSE_REGS if SSE1 allowed or AVX_REGS if AVX allowed
27336 if (!Subtarget->hasSSE1()) break;
27338 switch (VT.SimpleTy) {
27340 // Scalar SSE types.
27343 return std::make_pair(0U, &X86::FR32RegClass);
27346 return std::make_pair(0U, &X86::FR64RegClass);
27354 return std::make_pair(0U, &X86::VR128RegClass);
27362 return std::make_pair(0U, &X86::VR256RegClass);
27367 return std::make_pair(0U, &X86::VR512RegClass);
27373 // Use the default implementation in TargetLowering to convert the register
27374 // constraint into a member of a register class.
27375 std::pair<unsigned, const TargetRegisterClass*> Res;
27376 Res = TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
27378 // Not found as a standard register?
27380 // Map st(0) -> st(7) -> ST0
27381 if (Constraint.size() == 7 && Constraint[0] == '{' &&
27382 tolower(Constraint[1]) == 's' &&
27383 tolower(Constraint[2]) == 't' &&
27384 Constraint[3] == '(' &&
27385 (Constraint[4] >= '0' && Constraint[4] <= '7') &&
27386 Constraint[5] == ')' &&
27387 Constraint[6] == '}') {
27389 Res.first = X86::FP0+Constraint[4]-'0';
27390 Res.second = &X86::RFP80RegClass;
27394 // GCC allows "st(0)" to be called just plain "st".
27395 if (StringRef("{st}").equals_lower(Constraint)) {
27396 Res.first = X86::FP0;
27397 Res.second = &X86::RFP80RegClass;
27402 if (StringRef("{flags}").equals_lower(Constraint)) {
27403 Res.first = X86::EFLAGS;
27404 Res.second = &X86::CCRRegClass;
27408 // 'A' means EAX + EDX.
27409 if (Constraint == "A") {
27410 Res.first = X86::EAX;
27411 Res.second = &X86::GR32_ADRegClass;
27417 // Otherwise, check to see if this is a register class of the wrong value
27418 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
27419 // turn into {ax},{dx}.
27420 // MVT::Other is used to specify clobber names.
27421 if (Res.second->hasType(VT) || VT == MVT::Other)
27422 return Res; // Correct type already, nothing to do.
27424 // Get a matching integer of the correct size. i.e. "ax" with MVT::32 should
27425 // return "eax". This should even work for things like getting 64bit integer
27426 // registers when given an f64 type.
27427 const TargetRegisterClass *Class = Res.second;
27428 if (Class == &X86::GR8RegClass || Class == &X86::GR16RegClass ||
27429 Class == &X86::GR32RegClass || Class == &X86::GR64RegClass) {
27430 unsigned Size = VT.getSizeInBits();
27431 MVT::SimpleValueType SimpleTy = Size == 1 || Size == 8 ? MVT::i8
27432 : Size == 16 ? MVT::i16
27433 : Size == 32 ? MVT::i32
27434 : Size == 64 ? MVT::i64
27436 unsigned DestReg = getX86SubSuperRegisterOrZero(Res.first, SimpleTy);
27438 Res.first = DestReg;
27439 Res.second = SimpleTy == MVT::i8 ? &X86::GR8RegClass
27440 : SimpleTy == MVT::i16 ? &X86::GR16RegClass
27441 : SimpleTy == MVT::i32 ? &X86::GR32RegClass
27442 : &X86::GR64RegClass;
27443 assert(Res.second->contains(Res.first) && "Register in register class");
27445 // No register found/type mismatch.
27447 Res.second = nullptr;
27449 } else if (Class == &X86::FR32RegClass || Class == &X86::FR64RegClass ||
27450 Class == &X86::VR128RegClass || Class == &X86::VR256RegClass ||
27451 Class == &X86::FR32XRegClass || Class == &X86::FR64XRegClass ||
27452 Class == &X86::VR128XRegClass || Class == &X86::VR256XRegClass ||
27453 Class == &X86::VR512RegClass) {
27454 // Handle references to XMM physical registers that got mapped into the
27455 // wrong class. This can happen with constraints like {xmm0} where the
27456 // target independent register mapper will just pick the first match it can
27457 // find, ignoring the required type.
27459 if (VT == MVT::f32 || VT == MVT::i32)
27460 Res.second = &X86::FR32RegClass;
27461 else if (VT == MVT::f64 || VT == MVT::i64)
27462 Res.second = &X86::FR64RegClass;
27463 else if (X86::VR128RegClass.hasType(VT))
27464 Res.second = &X86::VR128RegClass;
27465 else if (X86::VR256RegClass.hasType(VT))
27466 Res.second = &X86::VR256RegClass;
27467 else if (X86::VR512RegClass.hasType(VT))
27468 Res.second = &X86::VR512RegClass;
27470 // Type mismatch and not a clobber: Return an error;
27472 Res.second = nullptr;
27479 int X86TargetLowering::getScalingFactorCost(const DataLayout &DL,
27480 const AddrMode &AM, Type *Ty,
27481 unsigned AS) const {
27482 // Scaling factors are not free at all.
27483 // An indexed folded instruction, i.e., inst (reg1, reg2, scale),
27484 // will take 2 allocations in the out of order engine instead of 1
27485 // for plain addressing mode, i.e. inst (reg1).
27487 // vaddps (%rsi,%drx), %ymm0, %ymm1
27488 // Requires two allocations (one for the load, one for the computation)
27490 // vaddps (%rsi), %ymm0, %ymm1
27491 // Requires just 1 allocation, i.e., freeing allocations for other operations
27492 // and having less micro operations to execute.
27494 // For some X86 architectures, this is even worse because for instance for
27495 // stores, the complex addressing mode forces the instruction to use the
27496 // "load" ports instead of the dedicated "store" port.
27497 // E.g., on Haswell:
27498 // vmovaps %ymm1, (%r8, %rdi) can use port 2 or 3.
27499 // vmovaps %ymm1, (%r8) can use port 2, 3, or 7.
27500 if (isLegalAddressingMode(DL, AM, Ty, AS))
27501 // Scale represents reg2 * scale, thus account for 1
27502 // as soon as we use a second register.
27503 return AM.Scale != 0;
27507 bool X86TargetLowering::isIntDivCheap(EVT VT, AttributeSet Attr) const {
27508 // Integer division on x86 is expensive. However, when aggressively optimizing
27509 // for code size, we prefer to use a div instruction, as it is usually smaller
27510 // than the alternative sequence.
27511 // The exception to this is vector division. Since x86 doesn't have vector
27512 // integer division, leaving the division as-is is a loss even in terms of
27513 // size, because it will have to be scalarized, while the alternative code
27514 // sequence can be performed in vector form.
27515 bool OptSize = Attr.hasAttribute(AttributeSet::FunctionIndex,
27516 Attribute::MinSize);
27517 return OptSize && !VT.isVector();
27520 void X86TargetLowering::markInRegArguments(SelectionDAG &DAG,
27521 TargetLowering::ArgListTy& Args) const {
27522 // The MCU psABI requires some arguments to be passed in-register.
27523 // For regular calls, the inreg arguments are marked by the front-end.
27524 // However, for compiler generated library calls, we have to patch this
27526 if (!Subtarget->isTargetMCU() || !Args.size())
27529 unsigned FreeRegs = 3;
27530 for (auto &Arg : Args) {
27531 // For library functions, we do not expect any fancy types.
27532 unsigned Size = DAG.getDataLayout().getTypeSizeInBits(Arg.Ty);
27533 unsigned SizeInRegs = (Size + 31) / 32;
27534 if (SizeInRegs > 2 || SizeInRegs > FreeRegs)
27537 Arg.isInReg = true;
27538 FreeRegs -= SizeInRegs;