1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
16 #include "X86InstrBuilder.h"
17 #include "X86ISelLowering.h"
18 #include "X86MachineFunctionInfo.h"
19 #include "X86TargetMachine.h"
20 #include "llvm/CallingConv.h"
21 #include "llvm/Constants.h"
22 #include "llvm/DerivedTypes.h"
23 #include "llvm/GlobalVariable.h"
24 #include "llvm/Function.h"
25 #include "llvm/Intrinsics.h"
26 #include "llvm/ADT/BitVector.h"
27 #include "llvm/ADT/VectorExtras.h"
28 #include "llvm/CodeGen/CallingConvLower.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineFunction.h"
31 #include "llvm/CodeGen/MachineInstrBuilder.h"
32 #include "llvm/CodeGen/MachineModuleInfo.h"
33 #include "llvm/CodeGen/MachineRegisterInfo.h"
34 #include "llvm/CodeGen/PseudoSourceValue.h"
35 #include "llvm/CodeGen/SelectionDAG.h"
36 #include "llvm/Support/MathExtras.h"
37 #include "llvm/Support/Debug.h"
38 #include "llvm/Target/TargetOptions.h"
39 #include "llvm/ADT/SmallSet.h"
40 #include "llvm/ADT/StringExtras.h"
43 // Forward declarations.
44 static SDOperand getMOVLMask(unsigned NumElems, SelectionDAG &DAG);
46 X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
47 : TargetLowering(TM) {
48 Subtarget = &TM.getSubtarget<X86Subtarget>();
49 X86ScalarSSEf64 = Subtarget->hasSSE2();
50 X86ScalarSSEf32 = Subtarget->hasSSE1();
51 X86StackPtr = Subtarget->is64Bit() ? X86::RSP : X86::ESP;
55 RegInfo = TM.getRegisterInfo();
57 // Set up the TargetLowering object.
59 // X86 is weird, it always uses i8 for shift amounts and setcc results.
60 setShiftAmountType(MVT::i8);
61 setSetCCResultContents(ZeroOrOneSetCCResult);
62 setSchedulingPreference(SchedulingForRegPressure);
63 setShiftAmountFlavor(Mask); // shl X, 32 == shl X, 0
64 setStackPointerRegisterToSaveRestore(X86StackPtr);
66 if (Subtarget->isTargetDarwin()) {
67 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
68 setUseUnderscoreSetJmp(false);
69 setUseUnderscoreLongJmp(false);
70 } else if (Subtarget->isTargetMingw()) {
71 // MS runtime is weird: it exports _setjmp, but longjmp!
72 setUseUnderscoreSetJmp(true);
73 setUseUnderscoreLongJmp(false);
75 setUseUnderscoreSetJmp(true);
76 setUseUnderscoreLongJmp(true);
79 // Set up the register classes.
80 addRegisterClass(MVT::i8, X86::GR8RegisterClass);
81 addRegisterClass(MVT::i16, X86::GR16RegisterClass);
82 addRegisterClass(MVT::i32, X86::GR32RegisterClass);
83 if (Subtarget->is64Bit())
84 addRegisterClass(MVT::i64, X86::GR64RegisterClass);
86 setLoadXAction(ISD::SEXTLOAD, MVT::i1, Promote);
88 // We don't accept any truncstore of integer registers.
89 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
90 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
91 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
92 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
93 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
94 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
96 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
98 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
99 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
100 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
102 if (Subtarget->is64Bit()) {
103 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Expand);
104 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
107 // If SSE i64 SINT_TO_FP is not available, expand i32 UINT_TO_FP.
108 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Expand);
110 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
113 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
115 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
116 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
117 // SSE has no i16 to fp conversion, only i32
118 if (X86ScalarSSEf32) {
119 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
120 // f32 and f64 cases are Legal, f80 case is not
121 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
123 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
124 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
127 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
128 // are Legal, f80 is custom lowered.
129 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
130 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
132 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
134 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
135 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
137 if (X86ScalarSSEf32) {
138 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
139 // f32 and f64 cases are Legal, f80 case is not
140 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
142 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
143 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
146 // Handle FP_TO_UINT by promoting the destination to a larger signed
148 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
149 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
150 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
152 if (Subtarget->is64Bit()) {
153 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
154 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
156 if (X86ScalarSSEf32 && !Subtarget->hasSSE3())
157 // Expand FP_TO_UINT into a select.
158 // FIXME: We would like to use a Custom expander here eventually to do
159 // the optimal thing for SSE vs. the default expansion in the legalizer.
160 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
162 // With SSE3 we can use fisttpll to convert to a signed i64.
163 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
166 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
167 if (!X86ScalarSSEf64) {
168 setOperationAction(ISD::BIT_CONVERT , MVT::f32 , Expand);
169 setOperationAction(ISD::BIT_CONVERT , MVT::i32 , Expand);
172 // Scalar integer divide and remainder are lowered to use operations that
173 // produce two results, to match the available instructions. This exposes
174 // the two-result form to trivial CSE, which is able to combine x/y and x%y
175 // into a single instruction.
177 // Scalar integer multiply-high is also lowered to use two-result
178 // operations, to match the available instructions. However, plain multiply
179 // (low) operations are left as Legal, as there are single-result
180 // instructions for this in x86. Using the two-result multiply instructions
181 // when both high and low results are needed must be arranged by dagcombine.
182 setOperationAction(ISD::MULHS , MVT::i8 , Expand);
183 setOperationAction(ISD::MULHU , MVT::i8 , Expand);
184 setOperationAction(ISD::SDIV , MVT::i8 , Expand);
185 setOperationAction(ISD::UDIV , MVT::i8 , Expand);
186 setOperationAction(ISD::SREM , MVT::i8 , Expand);
187 setOperationAction(ISD::UREM , MVT::i8 , Expand);
188 setOperationAction(ISD::MULHS , MVT::i16 , Expand);
189 setOperationAction(ISD::MULHU , MVT::i16 , Expand);
190 setOperationAction(ISD::SDIV , MVT::i16 , Expand);
191 setOperationAction(ISD::UDIV , MVT::i16 , Expand);
192 setOperationAction(ISD::SREM , MVT::i16 , Expand);
193 setOperationAction(ISD::UREM , MVT::i16 , Expand);
194 setOperationAction(ISD::MULHS , MVT::i32 , Expand);
195 setOperationAction(ISD::MULHU , MVT::i32 , Expand);
196 setOperationAction(ISD::SDIV , MVT::i32 , Expand);
197 setOperationAction(ISD::UDIV , MVT::i32 , Expand);
198 setOperationAction(ISD::SREM , MVT::i32 , Expand);
199 setOperationAction(ISD::UREM , MVT::i32 , Expand);
200 setOperationAction(ISD::MULHS , MVT::i64 , Expand);
201 setOperationAction(ISD::MULHU , MVT::i64 , Expand);
202 setOperationAction(ISD::SDIV , MVT::i64 , Expand);
203 setOperationAction(ISD::UDIV , MVT::i64 , Expand);
204 setOperationAction(ISD::SREM , MVT::i64 , Expand);
205 setOperationAction(ISD::UREM , MVT::i64 , Expand);
207 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
208 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
209 setOperationAction(ISD::BR_CC , MVT::Other, Expand);
210 setOperationAction(ISD::SELECT_CC , MVT::Other, Expand);
211 if (Subtarget->is64Bit())
212 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
213 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
214 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
215 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
216 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
217 setOperationAction(ISD::FREM , MVT::f32 , Expand);
218 setOperationAction(ISD::FREM , MVT::f64 , Expand);
219 setOperationAction(ISD::FREM , MVT::f80 , Expand);
220 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
222 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
223 setOperationAction(ISD::CTTZ , MVT::i8 , Custom);
224 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
225 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
226 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
227 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
228 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
229 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
230 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
231 if (Subtarget->is64Bit()) {
232 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
233 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
234 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
237 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
238 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
240 // These should be promoted to a larger select which is supported.
241 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
242 setOperationAction(ISD::SELECT , MVT::i8 , Promote);
243 // X86 wants to expand cmov itself.
244 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
245 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
246 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
247 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
248 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
249 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
250 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
251 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
252 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
253 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
254 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
255 if (Subtarget->is64Bit()) {
256 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
257 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
259 // X86 ret instruction may pop stack.
260 setOperationAction(ISD::RET , MVT::Other, Custom);
261 if (!Subtarget->is64Bit())
262 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
265 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
266 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
267 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
268 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
269 if (Subtarget->is64Bit())
270 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
271 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
272 if (Subtarget->is64Bit()) {
273 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
274 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
275 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
276 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
278 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
279 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
280 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
281 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
282 if (Subtarget->is64Bit()) {
283 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
284 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
285 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
288 if (Subtarget->hasSSE1())
289 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
291 if (!Subtarget->hasSSE2())
292 setOperationAction(ISD::MEMBARRIER , MVT::Other, Expand);
294 // Expand certain atomics
295 setOperationAction(ISD::ATOMIC_CMP_SWAP , MVT::i8, Custom);
296 setOperationAction(ISD::ATOMIC_CMP_SWAP , MVT::i16, Custom);
297 setOperationAction(ISD::ATOMIC_CMP_SWAP , MVT::i32, Custom);
298 setOperationAction(ISD::ATOMIC_CMP_SWAP , MVT::i64, Custom);
299 setOperationAction(ISD::ATOMIC_LOAD_SUB , MVT::i32, Expand);
301 // Use the default ISD::DBG_STOPPOINT, ISD::DECLARE expansion.
302 setOperationAction(ISD::DBG_STOPPOINT, MVT::Other, Expand);
303 // FIXME - use subtarget debug flags
304 if (!Subtarget->isTargetDarwin() &&
305 !Subtarget->isTargetELF() &&
306 !Subtarget->isTargetCygMing()) {
307 setOperationAction(ISD::DBG_LABEL, MVT::Other, Expand);
308 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
311 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand);
312 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand);
313 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
314 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
315 if (Subtarget->is64Bit()) {
317 setExceptionPointerRegister(X86::RAX);
318 setExceptionSelectorRegister(X86::RDX);
320 setExceptionPointerRegister(X86::EAX);
321 setExceptionSelectorRegister(X86::EDX);
323 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
325 setOperationAction(ISD::TRAMPOLINE, MVT::Other, Custom);
327 setOperationAction(ISD::TRAP, MVT::Other, Legal);
329 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
330 setOperationAction(ISD::VASTART , MVT::Other, Custom);
331 setOperationAction(ISD::VAEND , MVT::Other, Expand);
332 if (Subtarget->is64Bit()) {
333 setOperationAction(ISD::VAARG , MVT::Other, Custom);
334 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
336 setOperationAction(ISD::VAARG , MVT::Other, Expand);
337 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
340 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
341 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
342 if (Subtarget->is64Bit())
343 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand);
344 if (Subtarget->isTargetCygMing())
345 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom);
347 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
349 if (X86ScalarSSEf64) {
350 // f32 and f64 use SSE.
351 // Set up the FP register classes.
352 addRegisterClass(MVT::f32, X86::FR32RegisterClass);
353 addRegisterClass(MVT::f64, X86::FR64RegisterClass);
355 // Use ANDPD to simulate FABS.
356 setOperationAction(ISD::FABS , MVT::f64, Custom);
357 setOperationAction(ISD::FABS , MVT::f32, Custom);
359 // Use XORP to simulate FNEG.
360 setOperationAction(ISD::FNEG , MVT::f64, Custom);
361 setOperationAction(ISD::FNEG , MVT::f32, Custom);
363 // Use ANDPD and ORPD to simulate FCOPYSIGN.
364 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
365 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
367 // We don't support sin/cos/fmod
368 setOperationAction(ISD::FSIN , MVT::f64, Expand);
369 setOperationAction(ISD::FCOS , MVT::f64, Expand);
370 setOperationAction(ISD::FSIN , MVT::f32, Expand);
371 setOperationAction(ISD::FCOS , MVT::f32, Expand);
373 // Expand FP immediates into loads from the stack, except for the special
375 addLegalFPImmediate(APFloat(+0.0)); // xorpd
376 addLegalFPImmediate(APFloat(+0.0f)); // xorps
378 // Floating truncations from f80 and extensions to f80 go through memory.
379 // If optimizing, we lie about this though and handle it in
380 // InstructionSelectPreprocess so that dagcombine2 can hack on these.
382 setConvertAction(MVT::f32, MVT::f80, Expand);
383 setConvertAction(MVT::f64, MVT::f80, Expand);
384 setConvertAction(MVT::f80, MVT::f32, Expand);
385 setConvertAction(MVT::f80, MVT::f64, Expand);
387 } else if (X86ScalarSSEf32) {
388 // Use SSE for f32, x87 for f64.
389 // Set up the FP register classes.
390 addRegisterClass(MVT::f32, X86::FR32RegisterClass);
391 addRegisterClass(MVT::f64, X86::RFP64RegisterClass);
393 // Use ANDPS to simulate FABS.
394 setOperationAction(ISD::FABS , MVT::f32, Custom);
396 // Use XORP to simulate FNEG.
397 setOperationAction(ISD::FNEG , MVT::f32, Custom);
399 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
401 // Use ANDPS and ORPS to simulate FCOPYSIGN.
402 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
403 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
405 // We don't support sin/cos/fmod
406 setOperationAction(ISD::FSIN , MVT::f32, Expand);
407 setOperationAction(ISD::FCOS , MVT::f32, Expand);
409 // Special cases we handle for FP constants.
410 addLegalFPImmediate(APFloat(+0.0f)); // xorps
411 addLegalFPImmediate(APFloat(+0.0)); // FLD0
412 addLegalFPImmediate(APFloat(+1.0)); // FLD1
413 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
414 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
416 // SSE <-> X87 conversions go through memory. If optimizing, we lie about
417 // this though and handle it in InstructionSelectPreprocess so that
418 // dagcombine2 can hack on these.
420 setConvertAction(MVT::f32, MVT::f64, Expand);
421 setConvertAction(MVT::f32, MVT::f80, Expand);
422 setConvertAction(MVT::f80, MVT::f32, Expand);
423 setConvertAction(MVT::f64, MVT::f32, Expand);
424 // And x87->x87 truncations also.
425 setConvertAction(MVT::f80, MVT::f64, Expand);
429 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
430 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
433 // f32 and f64 in x87.
434 // Set up the FP register classes.
435 addRegisterClass(MVT::f64, X86::RFP64RegisterClass);
436 addRegisterClass(MVT::f32, X86::RFP32RegisterClass);
438 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
439 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
440 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
441 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
443 // Floating truncations go through memory. If optimizing, we lie about
444 // this though and handle it in InstructionSelectPreprocess so that
445 // dagcombine2 can hack on these.
447 setConvertAction(MVT::f80, MVT::f32, Expand);
448 setConvertAction(MVT::f64, MVT::f32, Expand);
449 setConvertAction(MVT::f80, MVT::f64, Expand);
453 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
454 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
456 addLegalFPImmediate(APFloat(+0.0)); // FLD0
457 addLegalFPImmediate(APFloat(+1.0)); // FLD1
458 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
459 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
460 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
461 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
462 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
463 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
466 // Long double always uses X87.
467 addRegisterClass(MVT::f80, X86::RFP80RegisterClass);
468 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
469 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
471 APFloat TmpFlt(+0.0);
472 TmpFlt.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven);
473 addLegalFPImmediate(TmpFlt); // FLD0
475 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
476 APFloat TmpFlt2(+1.0);
477 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven);
478 addLegalFPImmediate(TmpFlt2); // FLD1
479 TmpFlt2.changeSign();
480 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
484 setOperationAction(ISD::FSIN , MVT::f80 , Expand);
485 setOperationAction(ISD::FCOS , MVT::f80 , Expand);
488 // Always use a library call for pow.
489 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
490 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
491 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
493 // First set operation action for all vector types to expand. Then we
494 // will selectively turn on ones that can be effectively codegen'd.
495 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
496 VT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) {
497 setOperationAction(ISD::ADD , (MVT::SimpleValueType)VT, Expand);
498 setOperationAction(ISD::SUB , (MVT::SimpleValueType)VT, Expand);
499 setOperationAction(ISD::FADD, (MVT::SimpleValueType)VT, Expand);
500 setOperationAction(ISD::FNEG, (MVT::SimpleValueType)VT, Expand);
501 setOperationAction(ISD::FSUB, (MVT::SimpleValueType)VT, Expand);
502 setOperationAction(ISD::MUL , (MVT::SimpleValueType)VT, Expand);
503 setOperationAction(ISD::FMUL, (MVT::SimpleValueType)VT, Expand);
504 setOperationAction(ISD::SDIV, (MVT::SimpleValueType)VT, Expand);
505 setOperationAction(ISD::UDIV, (MVT::SimpleValueType)VT, Expand);
506 setOperationAction(ISD::FDIV, (MVT::SimpleValueType)VT, Expand);
507 setOperationAction(ISD::SREM, (MVT::SimpleValueType)VT, Expand);
508 setOperationAction(ISD::UREM, (MVT::SimpleValueType)VT, Expand);
509 setOperationAction(ISD::LOAD, (MVT::SimpleValueType)VT, Expand);
510 setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::SimpleValueType)VT, Expand);
511 setOperationAction(ISD::EXTRACT_VECTOR_ELT, (MVT::SimpleValueType)VT, Expand);
512 setOperationAction(ISD::INSERT_VECTOR_ELT, (MVT::SimpleValueType)VT, Expand);
513 setOperationAction(ISD::FABS, (MVT::SimpleValueType)VT, Expand);
514 setOperationAction(ISD::FSIN, (MVT::SimpleValueType)VT, Expand);
515 setOperationAction(ISD::FCOS, (MVT::SimpleValueType)VT, Expand);
516 setOperationAction(ISD::FREM, (MVT::SimpleValueType)VT, Expand);
517 setOperationAction(ISD::FPOWI, (MVT::SimpleValueType)VT, Expand);
518 setOperationAction(ISD::FSQRT, (MVT::SimpleValueType)VT, Expand);
519 setOperationAction(ISD::FCOPYSIGN, (MVT::SimpleValueType)VT, Expand);
520 setOperationAction(ISD::SMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
521 setOperationAction(ISD::UMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
522 setOperationAction(ISD::SDIVREM, (MVT::SimpleValueType)VT, Expand);
523 setOperationAction(ISD::UDIVREM, (MVT::SimpleValueType)VT, Expand);
524 setOperationAction(ISD::FPOW, (MVT::SimpleValueType)VT, Expand);
525 setOperationAction(ISD::CTPOP, (MVT::SimpleValueType)VT, Expand);
526 setOperationAction(ISD::CTTZ, (MVT::SimpleValueType)VT, Expand);
527 setOperationAction(ISD::CTLZ, (MVT::SimpleValueType)VT, Expand);
528 setOperationAction(ISD::SHL, (MVT::SimpleValueType)VT, Expand);
529 setOperationAction(ISD::SRA, (MVT::SimpleValueType)VT, Expand);
530 setOperationAction(ISD::SRL, (MVT::SimpleValueType)VT, Expand);
531 setOperationAction(ISD::ROTL, (MVT::SimpleValueType)VT, Expand);
532 setOperationAction(ISD::ROTR, (MVT::SimpleValueType)VT, Expand);
533 setOperationAction(ISD::BSWAP, (MVT::SimpleValueType)VT, Expand);
534 setOperationAction(ISD::VSETCC, (MVT::SimpleValueType)VT, Expand);
537 if (Subtarget->hasMMX()) {
538 addRegisterClass(MVT::v8i8, X86::VR64RegisterClass);
539 addRegisterClass(MVT::v4i16, X86::VR64RegisterClass);
540 addRegisterClass(MVT::v2i32, X86::VR64RegisterClass);
541 addRegisterClass(MVT::v2f32, X86::VR64RegisterClass);
542 addRegisterClass(MVT::v1i64, X86::VR64RegisterClass);
544 // FIXME: add MMX packed arithmetics
546 setOperationAction(ISD::ADD, MVT::v8i8, Legal);
547 setOperationAction(ISD::ADD, MVT::v4i16, Legal);
548 setOperationAction(ISD::ADD, MVT::v2i32, Legal);
549 setOperationAction(ISD::ADD, MVT::v1i64, Legal);
551 setOperationAction(ISD::SUB, MVT::v8i8, Legal);
552 setOperationAction(ISD::SUB, MVT::v4i16, Legal);
553 setOperationAction(ISD::SUB, MVT::v2i32, Legal);
554 setOperationAction(ISD::SUB, MVT::v1i64, Legal);
556 setOperationAction(ISD::MULHS, MVT::v4i16, Legal);
557 setOperationAction(ISD::MUL, MVT::v4i16, Legal);
559 setOperationAction(ISD::AND, MVT::v8i8, Promote);
560 AddPromotedToType (ISD::AND, MVT::v8i8, MVT::v1i64);
561 setOperationAction(ISD::AND, MVT::v4i16, Promote);
562 AddPromotedToType (ISD::AND, MVT::v4i16, MVT::v1i64);
563 setOperationAction(ISD::AND, MVT::v2i32, Promote);
564 AddPromotedToType (ISD::AND, MVT::v2i32, MVT::v1i64);
565 setOperationAction(ISD::AND, MVT::v1i64, Legal);
567 setOperationAction(ISD::OR, MVT::v8i8, Promote);
568 AddPromotedToType (ISD::OR, MVT::v8i8, MVT::v1i64);
569 setOperationAction(ISD::OR, MVT::v4i16, Promote);
570 AddPromotedToType (ISD::OR, MVT::v4i16, MVT::v1i64);
571 setOperationAction(ISD::OR, MVT::v2i32, Promote);
572 AddPromotedToType (ISD::OR, MVT::v2i32, MVT::v1i64);
573 setOperationAction(ISD::OR, MVT::v1i64, Legal);
575 setOperationAction(ISD::XOR, MVT::v8i8, Promote);
576 AddPromotedToType (ISD::XOR, MVT::v8i8, MVT::v1i64);
577 setOperationAction(ISD::XOR, MVT::v4i16, Promote);
578 AddPromotedToType (ISD::XOR, MVT::v4i16, MVT::v1i64);
579 setOperationAction(ISD::XOR, MVT::v2i32, Promote);
580 AddPromotedToType (ISD::XOR, MVT::v2i32, MVT::v1i64);
581 setOperationAction(ISD::XOR, MVT::v1i64, Legal);
583 setOperationAction(ISD::LOAD, MVT::v8i8, Promote);
584 AddPromotedToType (ISD::LOAD, MVT::v8i8, MVT::v1i64);
585 setOperationAction(ISD::LOAD, MVT::v4i16, Promote);
586 AddPromotedToType (ISD::LOAD, MVT::v4i16, MVT::v1i64);
587 setOperationAction(ISD::LOAD, MVT::v2i32, Promote);
588 AddPromotedToType (ISD::LOAD, MVT::v2i32, MVT::v1i64);
589 setOperationAction(ISD::LOAD, MVT::v2f32, Promote);
590 AddPromotedToType (ISD::LOAD, MVT::v2f32, MVT::v1i64);
591 setOperationAction(ISD::LOAD, MVT::v1i64, Legal);
593 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i8, Custom);
594 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i16, Custom);
595 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i32, Custom);
596 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f32, Custom);
597 setOperationAction(ISD::BUILD_VECTOR, MVT::v1i64, Custom);
599 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i8, Custom);
600 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i16, Custom);
601 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i32, Custom);
602 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v1i64, Custom);
604 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Custom);
605 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Custom);
606 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Custom);
609 if (Subtarget->hasSSE1()) {
610 addRegisterClass(MVT::v4f32, X86::VR128RegisterClass);
612 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
613 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
614 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
615 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
616 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
617 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
618 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
619 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
620 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
621 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
622 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
623 setOperationAction(ISD::VSETCC, MVT::v4f32, Legal);
626 if (Subtarget->hasSSE2()) {
627 addRegisterClass(MVT::v2f64, X86::VR128RegisterClass);
628 addRegisterClass(MVT::v16i8, X86::VR128RegisterClass);
629 addRegisterClass(MVT::v8i16, X86::VR128RegisterClass);
630 addRegisterClass(MVT::v4i32, X86::VR128RegisterClass);
631 addRegisterClass(MVT::v2i64, X86::VR128RegisterClass);
633 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
634 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
635 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
636 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
637 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
638 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
639 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
640 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
641 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
642 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
643 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
644 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
645 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
646 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
647 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
649 setOperationAction(ISD::VSETCC, MVT::v2f64, Legal);
650 setOperationAction(ISD::VSETCC, MVT::v16i8, Legal);
651 setOperationAction(ISD::VSETCC, MVT::v8i16, Legal);
652 setOperationAction(ISD::VSETCC, MVT::v4i32, Legal);
653 setOperationAction(ISD::VSETCC, MVT::v2i64, Legal);
655 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
656 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
657 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
658 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
659 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
661 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
662 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; ++i) {
663 MVT VT = (MVT::SimpleValueType)i;
664 // Do not attempt to custom lower non-power-of-2 vectors
665 if (!isPowerOf2_32(VT.getVectorNumElements()))
667 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
668 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
669 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
671 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
672 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
673 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
674 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
675 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
676 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
677 if (Subtarget->is64Bit()) {
678 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
679 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
682 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
683 for (unsigned VT = (unsigned)MVT::v16i8; VT != (unsigned)MVT::v2i64; VT++) {
684 setOperationAction(ISD::AND, (MVT::SimpleValueType)VT, Promote);
685 AddPromotedToType (ISD::AND, (MVT::SimpleValueType)VT, MVT::v2i64);
686 setOperationAction(ISD::OR, (MVT::SimpleValueType)VT, Promote);
687 AddPromotedToType (ISD::OR, (MVT::SimpleValueType)VT, MVT::v2i64);
688 setOperationAction(ISD::XOR, (MVT::SimpleValueType)VT, Promote);
689 AddPromotedToType (ISD::XOR, (MVT::SimpleValueType)VT, MVT::v2i64);
690 setOperationAction(ISD::LOAD, (MVT::SimpleValueType)VT, Promote);
691 AddPromotedToType (ISD::LOAD, (MVT::SimpleValueType)VT, MVT::v2i64);
692 setOperationAction(ISD::SELECT, (MVT::SimpleValueType)VT, Promote);
693 AddPromotedToType (ISD::SELECT, (MVT::SimpleValueType)VT, MVT::v2i64);
696 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
698 // Custom lower v2i64 and v2f64 selects.
699 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
700 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
701 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
702 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
706 if (Subtarget->hasSSE41()) {
707 // FIXME: Do we need to handle scalar-to-vector here?
708 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
709 setOperationAction(ISD::MUL, MVT::v2i64, Legal);
711 // i8 and i16 vectors are custom , because the source register and source
712 // source memory operand types are not the same width. f32 vectors are
713 // custom since the immediate controlling the insert encodes additional
715 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
716 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
717 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Legal);
718 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
720 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
721 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
722 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Legal);
723 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
725 if (Subtarget->is64Bit()) {
726 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Legal);
727 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Legal);
731 // We want to custom lower some of our intrinsics.
732 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
734 // We have target-specific dag combine patterns for the following nodes:
735 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
736 setTargetDAGCombine(ISD::BUILD_VECTOR);
737 setTargetDAGCombine(ISD::SELECT);
738 setTargetDAGCombine(ISD::STORE);
740 computeRegisterProperties();
742 // FIXME: These should be based on subtarget info. Plus, the values should
743 // be smaller when we are in optimizing for size mode.
744 maxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
745 maxStoresPerMemcpy = 16; // For @llvm.memcpy -> sequence of stores
746 maxStoresPerMemmove = 3; // For @llvm.memmove -> sequence of stores
747 allowUnalignedMemoryAccesses = true; // x86 supports it!
748 setPrefLoopAlignment(16);
752 MVT X86TargetLowering::getSetCCResultType(const SDOperand &) const {
757 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
758 /// the desired ByVal argument alignment.
759 static void getMaxByValAlign(const Type *Ty, unsigned &MaxAlign) {
762 if (const VectorType *VTy = dyn_cast<VectorType>(Ty)) {
763 if (VTy->getBitWidth() == 128)
765 } else if (const ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
766 unsigned EltAlign = 0;
767 getMaxByValAlign(ATy->getElementType(), EltAlign);
768 if (EltAlign > MaxAlign)
770 } else if (const StructType *STy = dyn_cast<StructType>(Ty)) {
771 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
772 unsigned EltAlign = 0;
773 getMaxByValAlign(STy->getElementType(i), EltAlign);
774 if (EltAlign > MaxAlign)
783 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
784 /// function arguments in the caller parameter area. For X86, aggregates
785 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
786 /// are at 4-byte boundaries.
787 unsigned X86TargetLowering::getByValTypeAlignment(const Type *Ty) const {
788 if (Subtarget->is64Bit())
789 return getTargetData()->getABITypeAlignment(Ty);
791 if (Subtarget->hasSSE1())
792 getMaxByValAlign(Ty, Align);
796 /// getOptimalMemOpType - Returns the target specific optimal type for load
797 /// and store operations as a result of memset, memcpy, and memmove
798 /// lowering. It returns MVT::iAny if SelectionDAG should be responsible for
801 X86TargetLowering::getOptimalMemOpType(uint64_t Size, unsigned Align,
802 bool isSrcConst, bool isSrcStr) const {
803 if ((isSrcConst || isSrcStr) && Subtarget->hasSSE2() && Size >= 16)
805 if ((isSrcConst || isSrcStr) && Subtarget->hasSSE1() && Size >= 16)
807 if (Subtarget->is64Bit() && Size >= 8)
813 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
815 SDOperand X86TargetLowering::getPICJumpTableRelocBase(SDOperand Table,
816 SelectionDAG &DAG) const {
817 if (usesGlobalOffsetTable())
818 return DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, getPointerTy());
819 if (!Subtarget->isPICStyleRIPRel())
820 return DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy());
824 //===----------------------------------------------------------------------===//
825 // Return Value Calling Convention Implementation
826 //===----------------------------------------------------------------------===//
828 #include "X86GenCallingConv.inc"
830 /// LowerRET - Lower an ISD::RET node.
831 SDOperand X86TargetLowering::LowerRET(SDOperand Op, SelectionDAG &DAG) {
832 assert((Op.getNumOperands() & 1) == 1 && "ISD::RET should have odd # args");
834 SmallVector<CCValAssign, 16> RVLocs;
835 unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv();
836 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
837 CCState CCInfo(CC, isVarArg, getTargetMachine(), RVLocs);
838 CCInfo.AnalyzeReturn(Op.Val, RetCC_X86);
840 // If this is the first return lowered for this function, add the regs to the
841 // liveout set for the function.
842 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
843 for (unsigned i = 0; i != RVLocs.size(); ++i)
844 if (RVLocs[i].isRegLoc())
845 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
847 SDOperand Chain = Op.getOperand(0);
849 // Handle tail call return.
850 Chain = GetPossiblePreceedingTailCall(Chain, X86ISD::TAILCALL);
851 if (Chain.getOpcode() == X86ISD::TAILCALL) {
852 SDOperand TailCall = Chain;
853 SDOperand TargetAddress = TailCall.getOperand(1);
854 SDOperand StackAdjustment = TailCall.getOperand(2);
855 assert(((TargetAddress.getOpcode() == ISD::Register &&
856 (cast<RegisterSDNode>(TargetAddress)->getReg() == X86::ECX ||
857 cast<RegisterSDNode>(TargetAddress)->getReg() == X86::R9)) ||
858 TargetAddress.getOpcode() == ISD::TargetExternalSymbol ||
859 TargetAddress.getOpcode() == ISD::TargetGlobalAddress) &&
860 "Expecting an global address, external symbol, or register");
861 assert(StackAdjustment.getOpcode() == ISD::Constant &&
862 "Expecting a const value");
864 SmallVector<SDOperand,8> Operands;
865 Operands.push_back(Chain.getOperand(0));
866 Operands.push_back(TargetAddress);
867 Operands.push_back(StackAdjustment);
868 // Copy registers used by the call. Last operand is a flag so it is not
870 for (unsigned i=3; i < TailCall.getNumOperands()-1; i++) {
871 Operands.push_back(Chain.getOperand(i));
873 return DAG.getNode(X86ISD::TC_RETURN, MVT::Other, &Operands[0],
880 SmallVector<SDOperand, 6> RetOps;
881 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
882 // Operand #1 = Bytes To Pop
883 RetOps.push_back(DAG.getConstant(getBytesToPopOnReturn(), MVT::i16));
885 // Copy the result values into the output registers.
886 for (unsigned i = 0; i != RVLocs.size(); ++i) {
887 CCValAssign &VA = RVLocs[i];
888 assert(VA.isRegLoc() && "Can only return in registers!");
889 SDOperand ValToCopy = Op.getOperand(i*2+1);
891 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
892 // the RET instruction and handled by the FP Stackifier.
893 if (RVLocs[i].getLocReg() == X86::ST0 ||
894 RVLocs[i].getLocReg() == X86::ST1) {
895 // If this is a copy from an xmm register to ST(0), use an FPExtend to
896 // change the value to the FP stack register class.
897 if (isScalarFPTypeInSSEReg(RVLocs[i].getValVT()))
898 ValToCopy = DAG.getNode(ISD::FP_EXTEND, MVT::f80, ValToCopy);
899 RetOps.push_back(ValToCopy);
900 // Don't emit a copytoreg.
904 Chain = DAG.getCopyToReg(Chain, VA.getLocReg(), ValToCopy, Flag);
905 Flag = Chain.getValue(1);
908 // The x86-64 ABI for returning structs by value requires that we copy
909 // the sret argument into %rax for the return. We saved the argument into
910 // a virtual register in the entry block, so now we copy the value out
912 if (Subtarget->is64Bit() &&
913 DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
914 MachineFunction &MF = DAG.getMachineFunction();
915 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
916 unsigned Reg = FuncInfo->getSRetReturnReg();
918 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64));
919 FuncInfo->setSRetReturnReg(Reg);
921 SDOperand Val = DAG.getCopyFromReg(Chain, Reg, getPointerTy());
923 Chain = DAG.getCopyToReg(Chain, X86::RAX, Val, Flag);
924 Flag = Chain.getValue(1);
927 RetOps[0] = Chain; // Update chain.
929 // Add the flag if we have it.
931 RetOps.push_back(Flag);
933 return DAG.getNode(X86ISD::RET_FLAG, MVT::Other, &RetOps[0], RetOps.size());
937 /// LowerCallResult - Lower the result values of an ISD::CALL into the
938 /// appropriate copies out of appropriate physical registers. This assumes that
939 /// Chain/InFlag are the input chain/flag to use, and that TheCall is the call
940 /// being lowered. The returns a SDNode with the same number of values as the
942 SDNode *X86TargetLowering::
943 LowerCallResult(SDOperand Chain, SDOperand InFlag, SDNode *TheCall,
944 unsigned CallingConv, SelectionDAG &DAG) {
946 // Assign locations to each value returned by this call.
947 SmallVector<CCValAssign, 16> RVLocs;
948 bool isVarArg = cast<ConstantSDNode>(TheCall->getOperand(2))->getValue() != 0;
949 CCState CCInfo(CallingConv, isVarArg, getTargetMachine(), RVLocs);
950 CCInfo.AnalyzeCallResult(TheCall, RetCC_X86);
952 SmallVector<SDOperand, 8> ResultVals;
954 // Copy all of the result registers out of their specified physreg.
955 for (unsigned i = 0; i != RVLocs.size(); ++i) {
956 MVT CopyVT = RVLocs[i].getValVT();
958 // If this is a call to a function that returns an fp value on the floating
959 // point stack, but where we prefer to use the value in xmm registers, copy
960 // it out as F80 and use a truncate to move it from fp stack reg to xmm reg.
961 if (RVLocs[i].getLocReg() == X86::ST0 &&
962 isScalarFPTypeInSSEReg(RVLocs[i].getValVT())) {
966 Chain = DAG.getCopyFromReg(Chain, RVLocs[i].getLocReg(),
967 CopyVT, InFlag).getValue(1);
968 SDOperand Val = Chain.getValue(0);
969 InFlag = Chain.getValue(2);
971 if (CopyVT != RVLocs[i].getValVT()) {
972 // Round the F80 the right size, which also moves to the appropriate xmm
974 Val = DAG.getNode(ISD::FP_ROUND, RVLocs[i].getValVT(), Val,
975 // This truncation won't change the value.
976 DAG.getIntPtrConstant(1));
979 ResultVals.push_back(Val);
982 // Merge everything together with a MERGE_VALUES node.
983 ResultVals.push_back(Chain);
984 return DAG.getMergeValues(TheCall->getVTList(), &ResultVals[0],
985 ResultVals.size()).Val;
989 //===----------------------------------------------------------------------===//
990 // C & StdCall & Fast Calling Convention implementation
991 //===----------------------------------------------------------------------===//
992 // StdCall calling convention seems to be standard for many Windows' API
993 // routines and around. It differs from C calling convention just a little:
994 // callee should clean up the stack, not caller. Symbols should be also
995 // decorated in some fancy way :) It doesn't support any vector arguments.
996 // For info on fast calling convention see Fast Calling Convention (tail call)
997 // implementation LowerX86_32FastCCCallTo.
999 /// AddLiveIn - This helper function adds the specified physical register to the
1000 /// MachineFunction as a live in value. It also creates a corresponding virtual
1001 /// register for it.
1002 static unsigned AddLiveIn(MachineFunction &MF, unsigned PReg,
1003 const TargetRegisterClass *RC) {
1004 assert(RC->contains(PReg) && "Not the correct regclass!");
1005 unsigned VReg = MF.getRegInfo().createVirtualRegister(RC);
1006 MF.getRegInfo().addLiveIn(PReg, VReg);
1010 /// CallIsStructReturn - Determines whether a CALL node uses struct return
1012 static bool CallIsStructReturn(SDOperand Op) {
1013 unsigned NumOps = (Op.getNumOperands() - 5) / 2;
1017 return cast<ARG_FLAGSSDNode>(Op.getOperand(6))->getArgFlags().isSRet();
1020 /// ArgsAreStructReturn - Determines whether a FORMAL_ARGUMENTS node uses struct
1021 /// return semantics.
1022 static bool ArgsAreStructReturn(SDOperand Op) {
1023 unsigned NumArgs = Op.Val->getNumValues() - 1;
1027 return cast<ARG_FLAGSSDNode>(Op.getOperand(3))->getArgFlags().isSRet();
1030 /// IsCalleePop - Determines whether a CALL or FORMAL_ARGUMENTS node requires
1031 /// the callee to pop its own arguments. Callee pop is necessary to support tail
1033 bool X86TargetLowering::IsCalleePop(SDOperand Op) {
1034 bool IsVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
1038 switch (cast<ConstantSDNode>(Op.getOperand(1))->getValue()) {
1041 case CallingConv::X86_StdCall:
1042 return !Subtarget->is64Bit();
1043 case CallingConv::X86_FastCall:
1044 return !Subtarget->is64Bit();
1045 case CallingConv::Fast:
1046 return PerformTailCallOpt;
1050 /// CCAssignFnForNode - Selects the correct CCAssignFn for a CALL or
1051 /// FORMAL_ARGUMENTS node.
1052 CCAssignFn *X86TargetLowering::CCAssignFnForNode(SDOperand Op) const {
1053 unsigned CC = cast<ConstantSDNode>(Op.getOperand(1))->getValue();
1055 if (Subtarget->is64Bit()) {
1056 if (Subtarget->isTargetWin64())
1057 return CC_X86_Win64_C;
1059 if (CC == CallingConv::Fast && PerformTailCallOpt)
1060 return CC_X86_64_TailCall;
1066 if (CC == CallingConv::X86_FastCall)
1067 return CC_X86_32_FastCall;
1068 else if (CC == CallingConv::Fast && PerformTailCallOpt)
1069 return CC_X86_32_TailCall;
1074 /// NameDecorationForFORMAL_ARGUMENTS - Selects the appropriate decoration to
1075 /// apply to a MachineFunction containing a given FORMAL_ARGUMENTS node.
1077 X86TargetLowering::NameDecorationForFORMAL_ARGUMENTS(SDOperand Op) {
1078 unsigned CC = cast<ConstantSDNode>(Op.getOperand(1))->getValue();
1079 if (CC == CallingConv::X86_FastCall)
1081 else if (CC == CallingConv::X86_StdCall)
1087 /// CallRequiresGOTInRegister - Check whether the call requires the GOT pointer
1088 /// in a register before calling.
1089 bool X86TargetLowering::CallRequiresGOTPtrInReg(bool Is64Bit, bool IsTailCall) {
1090 return !IsTailCall && !Is64Bit &&
1091 getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1092 Subtarget->isPICStyleGOT();
1095 /// CallRequiresFnAddressInReg - Check whether the call requires the function
1096 /// address to be loaded in a register.
1098 X86TargetLowering::CallRequiresFnAddressInReg(bool Is64Bit, bool IsTailCall) {
1099 return !Is64Bit && IsTailCall &&
1100 getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1101 Subtarget->isPICStyleGOT();
1104 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
1105 /// by "Src" to address "Dst" with size and alignment information specified by
1106 /// the specific parameter attribute. The copy will be passed as a byval
1107 /// function parameter.
1109 CreateCopyOfByValArgument(SDOperand Src, SDOperand Dst, SDOperand Chain,
1110 ISD::ArgFlagsTy Flags, SelectionDAG &DAG) {
1111 SDOperand SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
1112 return DAG.getMemcpy(Chain, Dst, Src, SizeNode, Flags.getByValAlign(),
1113 /*AlwaysInline=*/true, NULL, 0, NULL, 0);
1116 SDOperand X86TargetLowering::LowerMemArgument(SDOperand Op, SelectionDAG &DAG,
1117 const CCValAssign &VA,
1118 MachineFrameInfo *MFI,
1120 SDOperand Root, unsigned i) {
1121 // Create the nodes corresponding to a load from this parameter slot.
1122 ISD::ArgFlagsTy Flags =
1123 cast<ARG_FLAGSSDNode>(Op.getOperand(3 + i))->getArgFlags();
1124 bool AlwaysUseMutable = (CC==CallingConv::Fast) && PerformTailCallOpt;
1125 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
1127 // FIXME: For now, all byval parameter objects are marked mutable. This can be
1128 // changed with more analysis.
1129 // In case of tail call optimization mark all arguments mutable. Since they
1130 // could be overwritten by lowering of arguments in case of a tail call.
1131 int FI = MFI->CreateFixedObject(VA.getValVT().getSizeInBits()/8,
1132 VA.getLocMemOffset(), isImmutable);
1133 SDOperand FIN = DAG.getFrameIndex(FI, getPointerTy());
1134 if (Flags.isByVal())
1136 return DAG.getLoad(VA.getValVT(), Root, FIN,
1137 PseudoSourceValue::getFixedStack(), FI);
1141 X86TargetLowering::LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG) {
1142 MachineFunction &MF = DAG.getMachineFunction();
1143 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1145 const Function* Fn = MF.getFunction();
1146 if (Fn->hasExternalLinkage() &&
1147 Subtarget->isTargetCygMing() &&
1148 Fn->getName() == "main")
1149 FuncInfo->setForceFramePointer(true);
1151 // Decorate the function name.
1152 FuncInfo->setDecorationStyle(NameDecorationForFORMAL_ARGUMENTS(Op));
1154 MachineFrameInfo *MFI = MF.getFrameInfo();
1155 SDOperand Root = Op.getOperand(0);
1156 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
1157 unsigned CC = MF.getFunction()->getCallingConv();
1158 bool Is64Bit = Subtarget->is64Bit();
1159 bool IsWin64 = Subtarget->isTargetWin64();
1161 assert(!(isVarArg && CC == CallingConv::Fast) &&
1162 "Var args not supported with calling convention fastcc");
1164 // Assign locations to all of the incoming arguments.
1165 SmallVector<CCValAssign, 16> ArgLocs;
1166 CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs);
1167 CCInfo.AnalyzeFormalArguments(Op.Val, CCAssignFnForNode(Op));
1169 SmallVector<SDOperand, 8> ArgValues;
1170 unsigned LastVal = ~0U;
1171 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1172 CCValAssign &VA = ArgLocs[i];
1173 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
1175 assert(VA.getValNo() != LastVal &&
1176 "Don't support value assigned to multiple locs yet");
1177 LastVal = VA.getValNo();
1179 if (VA.isRegLoc()) {
1180 MVT RegVT = VA.getLocVT();
1181 TargetRegisterClass *RC;
1182 if (RegVT == MVT::i32)
1183 RC = X86::GR32RegisterClass;
1184 else if (Is64Bit && RegVT == MVT::i64)
1185 RC = X86::GR64RegisterClass;
1186 else if (RegVT == MVT::f32)
1187 RC = X86::FR32RegisterClass;
1188 else if (RegVT == MVT::f64)
1189 RC = X86::FR64RegisterClass;
1190 else if (RegVT.isVector() && RegVT.getSizeInBits() == 128)
1191 RC = X86::VR128RegisterClass;
1192 else if (RegVT.isVector()) {
1193 assert(RegVT.getSizeInBits() == 64);
1195 RC = X86::VR64RegisterClass; // MMX values are passed in MMXs.
1197 // Darwin calling convention passes MMX values in either GPRs or
1198 // XMMs in x86-64. Other targets pass them in memory.
1199 if (RegVT != MVT::v1i64 && Subtarget->hasSSE2()) {
1200 RC = X86::VR128RegisterClass; // MMX values are passed in XMMs.
1203 RC = X86::GR64RegisterClass; // v1i64 values are passed in GPRs.
1208 assert(0 && "Unknown argument type!");
1211 unsigned Reg = AddLiveIn(DAG.getMachineFunction(), VA.getLocReg(), RC);
1212 SDOperand ArgValue = DAG.getCopyFromReg(Root, Reg, RegVT);
1214 // If this is an 8 or 16-bit value, it is really passed promoted to 32
1215 // bits. Insert an assert[sz]ext to capture this, then truncate to the
1217 if (VA.getLocInfo() == CCValAssign::SExt)
1218 ArgValue = DAG.getNode(ISD::AssertSext, RegVT, ArgValue,
1219 DAG.getValueType(VA.getValVT()));
1220 else if (VA.getLocInfo() == CCValAssign::ZExt)
1221 ArgValue = DAG.getNode(ISD::AssertZext, RegVT, ArgValue,
1222 DAG.getValueType(VA.getValVT()));
1224 if (VA.getLocInfo() != CCValAssign::Full)
1225 ArgValue = DAG.getNode(ISD::TRUNCATE, VA.getValVT(), ArgValue);
1227 // Handle MMX values passed in GPRs.
1228 if (Is64Bit && RegVT != VA.getLocVT()) {
1229 if (RegVT.getSizeInBits() == 64 && RC == X86::GR64RegisterClass)
1230 ArgValue = DAG.getNode(ISD::BIT_CONVERT, VA.getLocVT(), ArgValue);
1231 else if (RC == X86::VR128RegisterClass) {
1232 ArgValue = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i64, ArgValue,
1233 DAG.getConstant(0, MVT::i64));
1234 ArgValue = DAG.getNode(ISD::BIT_CONVERT, VA.getLocVT(), ArgValue);
1238 ArgValues.push_back(ArgValue);
1240 assert(VA.isMemLoc());
1241 ArgValues.push_back(LowerMemArgument(Op, DAG, VA, MFI, CC, Root, i));
1245 // The x86-64 ABI for returning structs by value requires that we copy
1246 // the sret argument into %rax for the return. Save the argument into
1247 // a virtual register so that we can access it from the return points.
1248 if (Is64Bit && DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
1249 MachineFunction &MF = DAG.getMachineFunction();
1250 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1251 unsigned Reg = FuncInfo->getSRetReturnReg();
1253 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64));
1254 FuncInfo->setSRetReturnReg(Reg);
1256 SDOperand Copy = DAG.getCopyToReg(DAG.getEntryNode(), Reg, ArgValues[0]);
1257 Root = DAG.getNode(ISD::TokenFactor, MVT::Other, Copy, Root);
1260 unsigned StackSize = CCInfo.getNextStackOffset();
1261 // align stack specially for tail calls
1262 if (CC == CallingConv::Fast)
1263 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
1265 // If the function takes variable number of arguments, make a frame index for
1266 // the start of the first vararg value... for expansion of llvm.va_start.
1268 if (Is64Bit || CC != CallingConv::X86_FastCall) {
1269 VarArgsFrameIndex = MFI->CreateFixedObject(1, StackSize);
1272 unsigned TotalNumIntRegs = 0, TotalNumXMMRegs = 0;
1274 // FIXME: We should really autogenerate these arrays
1275 static const unsigned GPR64ArgRegsWin64[] = {
1276 X86::RCX, X86::RDX, X86::R8, X86::R9
1278 static const unsigned XMMArgRegsWin64[] = {
1279 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
1281 static const unsigned GPR64ArgRegs64Bit[] = {
1282 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
1284 static const unsigned XMMArgRegs64Bit[] = {
1285 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
1286 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
1288 const unsigned *GPR64ArgRegs, *XMMArgRegs;
1291 TotalNumIntRegs = 4; TotalNumXMMRegs = 4;
1292 GPR64ArgRegs = GPR64ArgRegsWin64;
1293 XMMArgRegs = XMMArgRegsWin64;
1295 TotalNumIntRegs = 6; TotalNumXMMRegs = 8;
1296 GPR64ArgRegs = GPR64ArgRegs64Bit;
1297 XMMArgRegs = XMMArgRegs64Bit;
1299 unsigned NumIntRegs = CCInfo.getFirstUnallocated(GPR64ArgRegs,
1301 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs,
1304 // For X86-64, if there are vararg parameters that are passed via
1305 // registers, then we must store them to their spots on the stack so they
1306 // may be loaded by deferencing the result of va_next.
1307 VarArgsGPOffset = NumIntRegs * 8;
1308 VarArgsFPOffset = TotalNumIntRegs * 8 + NumXMMRegs * 16;
1309 RegSaveFrameIndex = MFI->CreateStackObject(TotalNumIntRegs * 8 +
1310 TotalNumXMMRegs * 16, 16);
1312 // Store the integer parameter registers.
1313 SmallVector<SDOperand, 8> MemOps;
1314 SDOperand RSFIN = DAG.getFrameIndex(RegSaveFrameIndex, getPointerTy());
1315 SDOperand FIN = DAG.getNode(ISD::ADD, getPointerTy(), RSFIN,
1316 DAG.getIntPtrConstant(VarArgsGPOffset));
1317 for (; NumIntRegs != TotalNumIntRegs; ++NumIntRegs) {
1318 unsigned VReg = AddLiveIn(MF, GPR64ArgRegs[NumIntRegs],
1319 X86::GR64RegisterClass);
1320 SDOperand Val = DAG.getCopyFromReg(Root, VReg, MVT::i64);
1322 DAG.getStore(Val.getValue(1), Val, FIN,
1323 PseudoSourceValue::getFixedStack(),
1325 MemOps.push_back(Store);
1326 FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN,
1327 DAG.getIntPtrConstant(8));
1330 // Now store the XMM (fp + vector) parameter registers.
1331 FIN = DAG.getNode(ISD::ADD, getPointerTy(), RSFIN,
1332 DAG.getIntPtrConstant(VarArgsFPOffset));
1333 for (; NumXMMRegs != TotalNumXMMRegs; ++NumXMMRegs) {
1334 unsigned VReg = AddLiveIn(MF, XMMArgRegs[NumXMMRegs],
1335 X86::VR128RegisterClass);
1336 SDOperand Val = DAG.getCopyFromReg(Root, VReg, MVT::v4f32);
1338 DAG.getStore(Val.getValue(1), Val, FIN,
1339 PseudoSourceValue::getFixedStack(),
1341 MemOps.push_back(Store);
1342 FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN,
1343 DAG.getIntPtrConstant(16));
1345 if (!MemOps.empty())
1346 Root = DAG.getNode(ISD::TokenFactor, MVT::Other,
1347 &MemOps[0], MemOps.size());
1351 // Make sure the instruction takes 8n+4 bytes to make sure the start of the
1352 // arguments and the arguments after the retaddr has been pushed are
1354 if (!Is64Bit && CC == CallingConv::X86_FastCall &&
1355 !Subtarget->isTargetCygMing() && !Subtarget->isTargetWindows() &&
1356 (StackSize & 7) == 0)
1359 ArgValues.push_back(Root);
1361 // Some CCs need callee pop.
1362 if (IsCalleePop(Op)) {
1363 BytesToPopOnReturn = StackSize; // Callee pops everything.
1364 BytesCallerReserves = 0;
1366 BytesToPopOnReturn = 0; // Callee pops nothing.
1367 // If this is an sret function, the return should pop the hidden pointer.
1368 if (!Is64Bit && ArgsAreStructReturn(Op))
1369 BytesToPopOnReturn = 4;
1370 BytesCallerReserves = StackSize;
1374 RegSaveFrameIndex = 0xAAAAAAA; // RegSaveFrameIndex is X86-64 only.
1375 if (CC == CallingConv::X86_FastCall)
1376 VarArgsFrameIndex = 0xAAAAAAA; // fastcc functions can't have varargs.
1379 FuncInfo->setBytesToPopOnReturn(BytesToPopOnReturn);
1381 // Return the new list of results.
1382 return DAG.getMergeValues(Op.Val->getVTList(), &ArgValues[0],
1383 ArgValues.size()).getValue(Op.ResNo);
1387 X86TargetLowering::LowerMemOpCallTo(SDOperand Op, SelectionDAG &DAG,
1388 const SDOperand &StackPtr,
1389 const CCValAssign &VA,
1392 unsigned LocMemOffset = VA.getLocMemOffset();
1393 SDOperand PtrOff = DAG.getIntPtrConstant(LocMemOffset);
1394 PtrOff = DAG.getNode(ISD::ADD, getPointerTy(), StackPtr, PtrOff);
1395 ISD::ArgFlagsTy Flags =
1396 cast<ARG_FLAGSSDNode>(Op.getOperand(6+2*VA.getValNo()))->getArgFlags();
1397 if (Flags.isByVal()) {
1398 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG);
1400 return DAG.getStore(Chain, Arg, PtrOff,
1401 PseudoSourceValue::getStack(), LocMemOffset);
1404 /// EmitTailCallLoadRetAddr - Emit a load of return adress if tail call
1405 /// optimization is performed and it is required.
1407 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
1408 SDOperand &OutRetAddr,
1413 if (!IsTailCall || FPDiff==0) return Chain;
1415 // Adjust the Return address stack slot.
1416 MVT VT = getPointerTy();
1417 OutRetAddr = getReturnAddressFrameIndex(DAG);
1418 // Load the "old" Return address.
1419 OutRetAddr = DAG.getLoad(VT, Chain,OutRetAddr, NULL, 0);
1420 return SDOperand(OutRetAddr.Val, 1);
1423 /// EmitTailCallStoreRetAddr - Emit a store of the return adress if tail call
1424 /// optimization is performed and it is required (FPDiff!=0).
1426 EmitTailCallStoreRetAddr(SelectionDAG & DAG, MachineFunction &MF,
1427 SDOperand Chain, SDOperand RetAddrFrIdx,
1428 bool Is64Bit, int FPDiff) {
1429 // Store the return address to the appropriate stack slot.
1430 if (!FPDiff) return Chain;
1431 // Calculate the new stack slot for the return address.
1432 int SlotSize = Is64Bit ? 8 : 4;
1433 int NewReturnAddrFI =
1434 MF.getFrameInfo()->CreateFixedObject(SlotSize, FPDiff-SlotSize);
1435 MVT VT = Is64Bit ? MVT::i64 : MVT::i32;
1436 SDOperand NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, VT);
1437 Chain = DAG.getStore(Chain, RetAddrFrIdx, NewRetAddrFrIdx,
1438 PseudoSourceValue::getFixedStack(), NewReturnAddrFI);
1442 SDOperand X86TargetLowering::LowerCALL(SDOperand Op, SelectionDAG &DAG) {
1443 MachineFunction &MF = DAG.getMachineFunction();
1444 SDOperand Chain = Op.getOperand(0);
1445 unsigned CC = cast<ConstantSDNode>(Op.getOperand(1))->getValue();
1446 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
1447 bool IsTailCall = cast<ConstantSDNode>(Op.getOperand(3))->getValue() != 0
1448 && CC == CallingConv::Fast && PerformTailCallOpt;
1449 SDOperand Callee = Op.getOperand(4);
1450 bool Is64Bit = Subtarget->is64Bit();
1451 bool IsStructRet = CallIsStructReturn(Op);
1453 assert(!(isVarArg && CC == CallingConv::Fast) &&
1454 "Var args not supported with calling convention fastcc");
1456 // Analyze operands of the call, assigning locations to each operand.
1457 SmallVector<CCValAssign, 16> ArgLocs;
1458 CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs);
1459 CCInfo.AnalyzeCallOperands(Op.Val, CCAssignFnForNode(Op));
1461 // Get a count of how many bytes are to be pushed on the stack.
1462 unsigned NumBytes = CCInfo.getNextStackOffset();
1463 if (CC == CallingConv::Fast)
1464 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
1466 // Make sure the instruction takes 8n+4 bytes to make sure the start of the
1467 // arguments and the arguments after the retaddr has been pushed are aligned.
1468 if (!Is64Bit && CC == CallingConv::X86_FastCall &&
1469 !Subtarget->isTargetCygMing() && !Subtarget->isTargetWindows() &&
1470 (NumBytes & 7) == 0)
1475 // Lower arguments at fp - stackoffset + fpdiff.
1476 unsigned NumBytesCallerPushed =
1477 MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn();
1478 FPDiff = NumBytesCallerPushed - NumBytes;
1480 // Set the delta of movement of the returnaddr stackslot.
1481 // But only set if delta is greater than previous delta.
1482 if (FPDiff < (MF.getInfo<X86MachineFunctionInfo>()->getTCReturnAddrDelta()))
1483 MF.getInfo<X86MachineFunctionInfo>()->setTCReturnAddrDelta(FPDiff);
1486 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes));
1488 SDOperand RetAddrFrIdx;
1489 // Load return adress for tail calls.
1490 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, IsTailCall, Is64Bit,
1493 SmallVector<std::pair<unsigned, SDOperand>, 8> RegsToPass;
1494 SmallVector<SDOperand, 8> MemOpChains;
1497 // Walk the register/memloc assignments, inserting copies/loads. In the case
1498 // of tail call optimization arguments are handle later.
1499 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1500 CCValAssign &VA = ArgLocs[i];
1501 SDOperand Arg = Op.getOperand(5+2*VA.getValNo());
1502 bool isByVal = cast<ARG_FLAGSSDNode>(Op.getOperand(6+2*VA.getValNo()))->
1503 getArgFlags().isByVal();
1505 // Promote the value if needed.
1506 switch (VA.getLocInfo()) {
1507 default: assert(0 && "Unknown loc info!");
1508 case CCValAssign::Full: break;
1509 case CCValAssign::SExt:
1510 Arg = DAG.getNode(ISD::SIGN_EXTEND, VA.getLocVT(), Arg);
1512 case CCValAssign::ZExt:
1513 Arg = DAG.getNode(ISD::ZERO_EXTEND, VA.getLocVT(), Arg);
1515 case CCValAssign::AExt:
1516 Arg = DAG.getNode(ISD::ANY_EXTEND, VA.getLocVT(), Arg);
1520 if (VA.isRegLoc()) {
1522 MVT RegVT = VA.getLocVT();
1523 if (RegVT.isVector() && RegVT.getSizeInBits() == 64)
1524 switch (VA.getLocReg()) {
1527 case X86::RDI: case X86::RSI: case X86::RDX: case X86::RCX:
1529 // Special case: passing MMX values in GPR registers.
1530 Arg = DAG.getNode(ISD::BIT_CONVERT, MVT::i64, Arg);
1533 case X86::XMM0: case X86::XMM1: case X86::XMM2: case X86::XMM3:
1534 case X86::XMM4: case X86::XMM5: case X86::XMM6: case X86::XMM7: {
1535 // Special case: passing MMX values in XMM registers.
1536 Arg = DAG.getNode(ISD::BIT_CONVERT, MVT::i64, Arg);
1537 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, MVT::v2i64, Arg);
1538 Arg = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v2i64,
1539 DAG.getNode(ISD::UNDEF, MVT::v2i64), Arg,
1540 getMOVLMask(2, DAG));
1545 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
1547 if (!IsTailCall || (IsTailCall && isByVal)) {
1548 assert(VA.isMemLoc());
1549 if (StackPtr.Val == 0)
1550 StackPtr = DAG.getCopyFromReg(Chain, X86StackPtr, getPointerTy());
1552 MemOpChains.push_back(LowerMemOpCallTo(Op, DAG, StackPtr, VA, Chain,
1558 if (!MemOpChains.empty())
1559 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
1560 &MemOpChains[0], MemOpChains.size());
1562 // Build a sequence of copy-to-reg nodes chained together with token chain
1563 // and flag operands which copy the outgoing args into registers.
1565 // Tail call byval lowering might overwrite argument registers so in case of
1566 // tail call optimization the copies to registers are lowered later.
1568 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1569 Chain = DAG.getCopyToReg(Chain, RegsToPass[i].first, RegsToPass[i].second,
1571 InFlag = Chain.getValue(1);
1574 // ELF / PIC requires GOT in the EBX register before function calls via PLT
1576 if (CallRequiresGOTPtrInReg(Is64Bit, IsTailCall)) {
1577 Chain = DAG.getCopyToReg(Chain, X86::EBX,
1578 DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()),
1580 InFlag = Chain.getValue(1);
1582 // If we are tail calling and generating PIC/GOT style code load the address
1583 // of the callee into ecx. The value in ecx is used as target of the tail
1584 // jump. This is done to circumvent the ebx/callee-saved problem for tail
1585 // calls on PIC/GOT architectures. Normally we would just put the address of
1586 // GOT into ebx and then call target@PLT. But for tail callss ebx would be
1587 // restored (since ebx is callee saved) before jumping to the target@PLT.
1588 if (CallRequiresFnAddressInReg(Is64Bit, IsTailCall)) {
1589 // Note: The actual moving to ecx is done further down.
1590 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
1591 if (G && !G->getGlobal()->hasHiddenVisibility() &&
1592 !G->getGlobal()->hasProtectedVisibility())
1593 Callee = LowerGlobalAddress(Callee, DAG);
1594 else if (isa<ExternalSymbolSDNode>(Callee))
1595 Callee = LowerExternalSymbol(Callee,DAG);
1598 if (Is64Bit && isVarArg) {
1599 // From AMD64 ABI document:
1600 // For calls that may call functions that use varargs or stdargs
1601 // (prototype-less calls or calls to functions containing ellipsis (...) in
1602 // the declaration) %al is used as hidden argument to specify the number
1603 // of SSE registers used. The contents of %al do not need to match exactly
1604 // the number of registers, but must be an ubound on the number of SSE
1605 // registers used and is in the range 0 - 8 inclusive.
1607 // FIXME: Verify this on Win64
1608 // Count the number of XMM registers allocated.
1609 static const unsigned XMMArgRegs[] = {
1610 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
1611 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
1613 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
1615 Chain = DAG.getCopyToReg(Chain, X86::AL,
1616 DAG.getConstant(NumXMMRegs, MVT::i8), InFlag);
1617 InFlag = Chain.getValue(1);
1621 // For tail calls lower the arguments to the 'real' stack slot.
1623 SmallVector<SDOperand, 8> MemOpChains2;
1626 // Do not flag preceeding copytoreg stuff together with the following stuff.
1627 InFlag = SDOperand();
1628 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1629 CCValAssign &VA = ArgLocs[i];
1630 if (!VA.isRegLoc()) {
1631 assert(VA.isMemLoc());
1632 SDOperand Arg = Op.getOperand(5+2*VA.getValNo());
1633 SDOperand FlagsOp = Op.getOperand(6+2*VA.getValNo());
1634 ISD::ArgFlagsTy Flags =
1635 cast<ARG_FLAGSSDNode>(FlagsOp)->getArgFlags();
1636 // Create frame index.
1637 int32_t Offset = VA.getLocMemOffset()+FPDiff;
1638 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
1639 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset);
1640 FIN = DAG.getFrameIndex(FI, getPointerTy());
1642 if (Flags.isByVal()) {
1643 // Copy relative to framepointer.
1644 SDOperand Source = DAG.getIntPtrConstant(VA.getLocMemOffset());
1645 if (StackPtr.Val == 0)
1646 StackPtr = DAG.getCopyFromReg(Chain, X86StackPtr, getPointerTy());
1647 Source = DAG.getNode(ISD::ADD, getPointerTy(), StackPtr, Source);
1649 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN, Chain,
1652 // Store relative to framepointer.
1653 MemOpChains2.push_back(
1654 DAG.getStore(Chain, Arg, FIN,
1655 PseudoSourceValue::getFixedStack(), FI));
1660 if (!MemOpChains2.empty())
1661 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
1662 &MemOpChains2[0], MemOpChains2.size());
1664 // Copy arguments to their registers.
1665 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1666 Chain = DAG.getCopyToReg(Chain, RegsToPass[i].first, RegsToPass[i].second,
1668 InFlag = Chain.getValue(1);
1670 InFlag =SDOperand();
1672 // Store the return address to the appropriate stack slot.
1673 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx, Is64Bit,
1677 // If the callee is a GlobalAddress node (quite common, every direct call is)
1678 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
1679 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1680 // We should use extra load for direct calls to dllimported functions in
1682 if ((IsTailCall || !Is64Bit ||
1683 getTargetMachine().getCodeModel() != CodeModel::Large)
1684 && !Subtarget->GVRequiresExtraLoad(G->getGlobal(),
1685 getTargetMachine(), true))
1686 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), getPointerTy());
1687 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
1688 if (IsTailCall || !Is64Bit ||
1689 getTargetMachine().getCodeModel() != CodeModel::Large)
1690 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy());
1691 } else if (IsTailCall) {
1692 unsigned Opc = Is64Bit ? X86::R9 : X86::ECX;
1694 Chain = DAG.getCopyToReg(Chain,
1695 DAG.getRegister(Opc, getPointerTy()),
1697 Callee = DAG.getRegister(Opc, getPointerTy());
1698 // Add register as live out.
1699 DAG.getMachineFunction().getRegInfo().addLiveOut(Opc);
1702 // Returns a chain & a flag for retval copy to use.
1703 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
1704 SmallVector<SDOperand, 8> Ops;
1707 Ops.push_back(Chain);
1708 Ops.push_back(DAG.getIntPtrConstant(NumBytes));
1709 Ops.push_back(DAG.getIntPtrConstant(0));
1711 Ops.push_back(InFlag);
1712 Chain = DAG.getNode(ISD::CALLSEQ_END, NodeTys, &Ops[0], Ops.size());
1713 InFlag = Chain.getValue(1);
1715 // Returns a chain & a flag for retval copy to use.
1716 NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
1720 Ops.push_back(Chain);
1721 Ops.push_back(Callee);
1724 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32));
1726 // Add argument registers to the end of the list so that they are known live
1728 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
1729 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
1730 RegsToPass[i].second.getValueType()));
1732 // Add an implicit use GOT pointer in EBX.
1733 if (!IsTailCall && !Is64Bit &&
1734 getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1735 Subtarget->isPICStyleGOT())
1736 Ops.push_back(DAG.getRegister(X86::EBX, getPointerTy()));
1738 // Add an implicit use of AL for x86 vararg functions.
1739 if (Is64Bit && isVarArg)
1740 Ops.push_back(DAG.getRegister(X86::AL, MVT::i8));
1743 Ops.push_back(InFlag);
1746 assert(InFlag.Val &&
1747 "Flag must be set. Depend on flag being set in LowerRET");
1748 Chain = DAG.getNode(X86ISD::TAILCALL,
1749 Op.Val->getVTList(), &Ops[0], Ops.size());
1751 return SDOperand(Chain.Val, Op.ResNo);
1754 Chain = DAG.getNode(X86ISD::CALL, NodeTys, &Ops[0], Ops.size());
1755 InFlag = Chain.getValue(1);
1757 // Create the CALLSEQ_END node.
1758 unsigned NumBytesForCalleeToPush;
1759 if (IsCalleePop(Op))
1760 NumBytesForCalleeToPush = NumBytes; // Callee pops everything
1761 else if (!Is64Bit && IsStructRet)
1762 // If this is is a call to a struct-return function, the callee
1763 // pops the hidden struct pointer, so we have to push it back.
1764 // This is common for Darwin/X86, Linux & Mingw32 targets.
1765 NumBytesForCalleeToPush = 4;
1767 NumBytesForCalleeToPush = 0; // Callee pops nothing.
1769 // Returns a flag for retval copy to use.
1770 Chain = DAG.getCALLSEQ_END(Chain,
1771 DAG.getIntPtrConstant(NumBytes),
1772 DAG.getIntPtrConstant(NumBytesForCalleeToPush),
1774 InFlag = Chain.getValue(1);
1776 // Handle result values, copying them out of physregs into vregs that we
1778 return SDOperand(LowerCallResult(Chain, InFlag, Op.Val, CC, DAG), Op.ResNo);
1782 //===----------------------------------------------------------------------===//
1783 // Fast Calling Convention (tail call) implementation
1784 //===----------------------------------------------------------------------===//
1786 // Like std call, callee cleans arguments, convention except that ECX is
1787 // reserved for storing the tail called function address. Only 2 registers are
1788 // free for argument passing (inreg). Tail call optimization is performed
1790 // * tailcallopt is enabled
1791 // * caller/callee are fastcc
1792 // On X86_64 architecture with GOT-style position independent code only local
1793 // (within module) calls are supported at the moment.
1794 // To keep the stack aligned according to platform abi the function
1795 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
1796 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
1797 // If a tail called function callee has more arguments than the caller the
1798 // caller needs to make sure that there is room to move the RETADDR to. This is
1799 // achieved by reserving an area the size of the argument delta right after the
1800 // original REtADDR, but before the saved framepointer or the spilled registers
1801 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
1813 /// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned
1814 /// for a 16 byte align requirement.
1815 unsigned X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
1816 SelectionDAG& DAG) {
1817 if (PerformTailCallOpt) {
1818 MachineFunction &MF = DAG.getMachineFunction();
1819 const TargetMachine &TM = MF.getTarget();
1820 const TargetFrameInfo &TFI = *TM.getFrameInfo();
1821 unsigned StackAlignment = TFI.getStackAlignment();
1822 uint64_t AlignMask = StackAlignment - 1;
1823 int64_t Offset = StackSize;
1824 unsigned SlotSize = Subtarget->is64Bit() ? 8 : 4;
1825 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
1826 // Number smaller than 12 so just add the difference.
1827 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
1829 // Mask out lower bits, add stackalignment once plus the 12 bytes.
1830 Offset = ((~AlignMask) & Offset) + StackAlignment +
1831 (StackAlignment-SlotSize);
1838 /// IsEligibleForTailCallElimination - Check to see whether the next instruction
1839 /// following the call is a return. A function is eligible if caller/callee
1840 /// calling conventions match, currently only fastcc supports tail calls, and
1841 /// the function CALL is immediatly followed by a RET.
1842 bool X86TargetLowering::IsEligibleForTailCallOptimization(SDOperand Call,
1844 SelectionDAG& DAG) const {
1845 if (!PerformTailCallOpt)
1848 if (CheckTailCallReturnConstraints(Call, Ret)) {
1849 MachineFunction &MF = DAG.getMachineFunction();
1850 unsigned CallerCC = MF.getFunction()->getCallingConv();
1851 unsigned CalleeCC = cast<ConstantSDNode>(Call.getOperand(1))->getValue();
1852 if (CalleeCC == CallingConv::Fast && CallerCC == CalleeCC) {
1853 SDOperand Callee = Call.getOperand(4);
1854 // On x86/32Bit PIC/GOT tail calls are supported.
1855 if (getTargetMachine().getRelocationModel() != Reloc::PIC_ ||
1856 !Subtarget->isPICStyleGOT()|| !Subtarget->is64Bit())
1859 // Can only do local tail calls (in same module, hidden or protected) on
1860 // x86_64 PIC/GOT at the moment.
1861 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
1862 return G->getGlobal()->hasHiddenVisibility()
1863 || G->getGlobal()->hasProtectedVisibility();
1870 //===----------------------------------------------------------------------===//
1871 // Other Lowering Hooks
1872 //===----------------------------------------------------------------------===//
1875 SDOperand X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) {
1876 MachineFunction &MF = DAG.getMachineFunction();
1877 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1878 int ReturnAddrIndex = FuncInfo->getRAIndex();
1880 if (ReturnAddrIndex == 0) {
1881 // Set up a frame object for the return address.
1882 if (Subtarget->is64Bit())
1883 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(8, -8);
1885 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(4, -4);
1887 FuncInfo->setRAIndex(ReturnAddrIndex);
1890 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
1895 /// translateX86CC - do a one to one translation of a ISD::CondCode to the X86
1896 /// specific condition code. It returns a false if it cannot do a direct
1897 /// translation. X86CC is the translated CondCode. LHS/RHS are modified as
1899 static bool translateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
1900 unsigned &X86CC, SDOperand &LHS, SDOperand &RHS,
1901 SelectionDAG &DAG) {
1902 X86CC = X86::COND_INVALID;
1904 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
1905 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
1906 // X > -1 -> X == 0, jump !sign.
1907 RHS = DAG.getConstant(0, RHS.getValueType());
1908 X86CC = X86::COND_NS;
1910 } else if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
1911 // X < 0 -> X == 0, jump on sign.
1912 X86CC = X86::COND_S;
1914 } else if (SetCCOpcode == ISD::SETLT && RHSC->getValue() == 1) {
1916 RHS = DAG.getConstant(0, RHS.getValueType());
1917 X86CC = X86::COND_LE;
1922 switch (SetCCOpcode) {
1924 case ISD::SETEQ: X86CC = X86::COND_E; break;
1925 case ISD::SETGT: X86CC = X86::COND_G; break;
1926 case ISD::SETGE: X86CC = X86::COND_GE; break;
1927 case ISD::SETLT: X86CC = X86::COND_L; break;
1928 case ISD::SETLE: X86CC = X86::COND_LE; break;
1929 case ISD::SETNE: X86CC = X86::COND_NE; break;
1930 case ISD::SETULT: X86CC = X86::COND_B; break;
1931 case ISD::SETUGT: X86CC = X86::COND_A; break;
1932 case ISD::SETULE: X86CC = X86::COND_BE; break;
1933 case ISD::SETUGE: X86CC = X86::COND_AE; break;
1936 // On a floating point condition, the flags are set as follows:
1938 // 0 | 0 | 0 | X > Y
1939 // 0 | 0 | 1 | X < Y
1940 // 1 | 0 | 0 | X == Y
1941 // 1 | 1 | 1 | unordered
1943 switch (SetCCOpcode) {
1946 case ISD::SETEQ: X86CC = X86::COND_E; break;
1947 case ISD::SETOLT: Flip = true; // Fallthrough
1949 case ISD::SETGT: X86CC = X86::COND_A; break;
1950 case ISD::SETOLE: Flip = true; // Fallthrough
1952 case ISD::SETGE: X86CC = X86::COND_AE; break;
1953 case ISD::SETUGT: Flip = true; // Fallthrough
1955 case ISD::SETLT: X86CC = X86::COND_B; break;
1956 case ISD::SETUGE: Flip = true; // Fallthrough
1958 case ISD::SETLE: X86CC = X86::COND_BE; break;
1960 case ISD::SETNE: X86CC = X86::COND_NE; break;
1961 case ISD::SETUO: X86CC = X86::COND_P; break;
1962 case ISD::SETO: X86CC = X86::COND_NP; break;
1965 std::swap(LHS, RHS);
1968 return X86CC != X86::COND_INVALID;
1971 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
1972 /// code. Current x86 isa includes the following FP cmov instructions:
1973 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
1974 static bool hasFPCMov(unsigned X86CC) {
1990 /// isUndefOrInRange - Op is either an undef node or a ConstantSDNode. Return
1991 /// true if Op is undef or if its value falls within the specified range (L, H].
1992 static bool isUndefOrInRange(SDOperand Op, unsigned Low, unsigned Hi) {
1993 if (Op.getOpcode() == ISD::UNDEF)
1996 unsigned Val = cast<ConstantSDNode>(Op)->getValue();
1997 return (Val >= Low && Val < Hi);
2000 /// isUndefOrEqual - Op is either an undef node or a ConstantSDNode. Return
2001 /// true if Op is undef or if its value equal to the specified value.
2002 static bool isUndefOrEqual(SDOperand Op, unsigned Val) {
2003 if (Op.getOpcode() == ISD::UNDEF)
2005 return cast<ConstantSDNode>(Op)->getValue() == Val;
2008 /// isPSHUFDMask - Return true if the specified VECTOR_SHUFFLE operand
2009 /// specifies a shuffle of elements that is suitable for input to PSHUFD.
2010 bool X86::isPSHUFDMask(SDNode *N) {
2011 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2013 if (N->getNumOperands() != 2 && N->getNumOperands() != 4)
2016 // Check if the value doesn't reference the second vector.
2017 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
2018 SDOperand Arg = N->getOperand(i);
2019 if (Arg.getOpcode() == ISD::UNDEF) continue;
2020 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2021 if (cast<ConstantSDNode>(Arg)->getValue() >= e)
2028 /// isPSHUFHWMask - Return true if the specified VECTOR_SHUFFLE operand
2029 /// specifies a shuffle of elements that is suitable for input to PSHUFHW.
2030 bool X86::isPSHUFHWMask(SDNode *N) {
2031 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2033 if (N->getNumOperands() != 8)
2036 // Lower quadword copied in order.
2037 for (unsigned i = 0; i != 4; ++i) {
2038 SDOperand Arg = N->getOperand(i);
2039 if (Arg.getOpcode() == ISD::UNDEF) continue;
2040 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2041 if (cast<ConstantSDNode>(Arg)->getValue() != i)
2045 // Upper quadword shuffled.
2046 for (unsigned i = 4; i != 8; ++i) {
2047 SDOperand Arg = N->getOperand(i);
2048 if (Arg.getOpcode() == ISD::UNDEF) continue;
2049 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2050 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
2051 if (Val < 4 || Val > 7)
2058 /// isPSHUFLWMask - Return true if the specified VECTOR_SHUFFLE operand
2059 /// specifies a shuffle of elements that is suitable for input to PSHUFLW.
2060 bool X86::isPSHUFLWMask(SDNode *N) {
2061 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2063 if (N->getNumOperands() != 8)
2066 // Upper quadword copied in order.
2067 for (unsigned i = 4; i != 8; ++i)
2068 if (!isUndefOrEqual(N->getOperand(i), i))
2071 // Lower quadword shuffled.
2072 for (unsigned i = 0; i != 4; ++i)
2073 if (!isUndefOrInRange(N->getOperand(i), 0, 4))
2079 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
2080 /// specifies a shuffle of elements that is suitable for input to SHUFP*.
2081 static bool isSHUFPMask(SDOperandPtr Elems, unsigned NumElems) {
2082 if (NumElems != 2 && NumElems != 4) return false;
2084 unsigned Half = NumElems / 2;
2085 for (unsigned i = 0; i < Half; ++i)
2086 if (!isUndefOrInRange(Elems[i], 0, NumElems))
2088 for (unsigned i = Half; i < NumElems; ++i)
2089 if (!isUndefOrInRange(Elems[i], NumElems, NumElems*2))
2095 bool X86::isSHUFPMask(SDNode *N) {
2096 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2097 return ::isSHUFPMask(N->op_begin(), N->getNumOperands());
2100 /// isCommutedSHUFP - Returns true if the shuffle mask is exactly
2101 /// the reverse of what x86 shuffles want. x86 shuffles requires the lower
2102 /// half elements to come from vector 1 (which would equal the dest.) and
2103 /// the upper half to come from vector 2.
2104 static bool isCommutedSHUFP(SDOperandPtr Ops, unsigned NumOps) {
2105 if (NumOps != 2 && NumOps != 4) return false;
2107 unsigned Half = NumOps / 2;
2108 for (unsigned i = 0; i < Half; ++i)
2109 if (!isUndefOrInRange(Ops[i], NumOps, NumOps*2))
2111 for (unsigned i = Half; i < NumOps; ++i)
2112 if (!isUndefOrInRange(Ops[i], 0, NumOps))
2117 static bool isCommutedSHUFP(SDNode *N) {
2118 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2119 return isCommutedSHUFP(N->op_begin(), N->getNumOperands());
2122 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
2123 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
2124 bool X86::isMOVHLPSMask(SDNode *N) {
2125 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2127 if (N->getNumOperands() != 4)
2130 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3
2131 return isUndefOrEqual(N->getOperand(0), 6) &&
2132 isUndefOrEqual(N->getOperand(1), 7) &&
2133 isUndefOrEqual(N->getOperand(2), 2) &&
2134 isUndefOrEqual(N->getOperand(3), 3);
2137 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
2138 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
2140 bool X86::isMOVHLPS_v_undef_Mask(SDNode *N) {
2141 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2143 if (N->getNumOperands() != 4)
2146 // Expect bit0 == 2, bit1 == 3, bit2 == 2, bit3 == 3
2147 return isUndefOrEqual(N->getOperand(0), 2) &&
2148 isUndefOrEqual(N->getOperand(1), 3) &&
2149 isUndefOrEqual(N->getOperand(2), 2) &&
2150 isUndefOrEqual(N->getOperand(3), 3);
2153 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
2154 /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
2155 bool X86::isMOVLPMask(SDNode *N) {
2156 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2158 unsigned NumElems = N->getNumOperands();
2159 if (NumElems != 2 && NumElems != 4)
2162 for (unsigned i = 0; i < NumElems/2; ++i)
2163 if (!isUndefOrEqual(N->getOperand(i), i + NumElems))
2166 for (unsigned i = NumElems/2; i < NumElems; ++i)
2167 if (!isUndefOrEqual(N->getOperand(i), i))
2173 /// isMOVHPMask - Return true if the specified VECTOR_SHUFFLE operand
2174 /// specifies a shuffle of elements that is suitable for input to MOVHP{S|D}
2176 bool X86::isMOVHPMask(SDNode *N) {
2177 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2179 unsigned NumElems = N->getNumOperands();
2180 if (NumElems != 2 && NumElems != 4)
2183 for (unsigned i = 0; i < NumElems/2; ++i)
2184 if (!isUndefOrEqual(N->getOperand(i), i))
2187 for (unsigned i = 0; i < NumElems/2; ++i) {
2188 SDOperand Arg = N->getOperand(i + NumElems/2);
2189 if (!isUndefOrEqual(Arg, i + NumElems))
2196 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
2197 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
2198 bool static isUNPCKLMask(SDOperandPtr Elts, unsigned NumElts,
2199 bool V2IsSplat = false) {
2200 if (NumElts != 2 && NumElts != 4 && NumElts != 8 && NumElts != 16)
2203 for (unsigned i = 0, j = 0; i != NumElts; i += 2, ++j) {
2204 SDOperand BitI = Elts[i];
2205 SDOperand BitI1 = Elts[i+1];
2206 if (!isUndefOrEqual(BitI, j))
2209 if (isUndefOrEqual(BitI1, NumElts))
2212 if (!isUndefOrEqual(BitI1, j + NumElts))
2220 bool X86::isUNPCKLMask(SDNode *N, bool V2IsSplat) {
2221 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2222 return ::isUNPCKLMask(N->op_begin(), N->getNumOperands(), V2IsSplat);
2225 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
2226 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
2227 bool static isUNPCKHMask(SDOperandPtr Elts, unsigned NumElts,
2228 bool V2IsSplat = false) {
2229 if (NumElts != 2 && NumElts != 4 && NumElts != 8 && NumElts != 16)
2232 for (unsigned i = 0, j = 0; i != NumElts; i += 2, ++j) {
2233 SDOperand BitI = Elts[i];
2234 SDOperand BitI1 = Elts[i+1];
2235 if (!isUndefOrEqual(BitI, j + NumElts/2))
2238 if (isUndefOrEqual(BitI1, NumElts))
2241 if (!isUndefOrEqual(BitI1, j + NumElts/2 + NumElts))
2249 bool X86::isUNPCKHMask(SDNode *N, bool V2IsSplat) {
2250 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2251 return ::isUNPCKHMask(N->op_begin(), N->getNumOperands(), V2IsSplat);
2254 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
2255 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
2257 bool X86::isUNPCKL_v_undef_Mask(SDNode *N) {
2258 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2260 unsigned NumElems = N->getNumOperands();
2261 if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16)
2264 for (unsigned i = 0, j = 0; i != NumElems; i += 2, ++j) {
2265 SDOperand BitI = N->getOperand(i);
2266 SDOperand BitI1 = N->getOperand(i+1);
2268 if (!isUndefOrEqual(BitI, j))
2270 if (!isUndefOrEqual(BitI1, j))
2277 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
2278 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
2280 bool X86::isUNPCKH_v_undef_Mask(SDNode *N) {
2281 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2283 unsigned NumElems = N->getNumOperands();
2284 if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16)
2287 for (unsigned i = 0, j = NumElems / 2; i != NumElems; i += 2, ++j) {
2288 SDOperand BitI = N->getOperand(i);
2289 SDOperand BitI1 = N->getOperand(i + 1);
2291 if (!isUndefOrEqual(BitI, j))
2293 if (!isUndefOrEqual(BitI1, j))
2300 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
2301 /// specifies a shuffle of elements that is suitable for input to MOVSS,
2302 /// MOVSD, and MOVD, i.e. setting the lowest element.
2303 static bool isMOVLMask(SDOperandPtr Elts, unsigned NumElts) {
2304 if (NumElts != 2 && NumElts != 4)
2307 if (!isUndefOrEqual(Elts[0], NumElts))
2310 for (unsigned i = 1; i < NumElts; ++i) {
2311 if (!isUndefOrEqual(Elts[i], i))
2318 bool X86::isMOVLMask(SDNode *N) {
2319 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2320 return ::isMOVLMask(N->op_begin(), N->getNumOperands());
2323 /// isCommutedMOVL - Returns true if the shuffle mask is except the reverse
2324 /// of what x86 movss want. X86 movs requires the lowest element to be lowest
2325 /// element of vector 2 and the other elements to come from vector 1 in order.
2326 static bool isCommutedMOVL(SDOperandPtr Ops, unsigned NumOps,
2327 bool V2IsSplat = false,
2328 bool V2IsUndef = false) {
2329 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16)
2332 if (!isUndefOrEqual(Ops[0], 0))
2335 for (unsigned i = 1; i < NumOps; ++i) {
2336 SDOperand Arg = Ops[i];
2337 if (!(isUndefOrEqual(Arg, i+NumOps) ||
2338 (V2IsUndef && isUndefOrInRange(Arg, NumOps, NumOps*2)) ||
2339 (V2IsSplat && isUndefOrEqual(Arg, NumOps))))
2346 static bool isCommutedMOVL(SDNode *N, bool V2IsSplat = false,
2347 bool V2IsUndef = false) {
2348 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2349 return isCommutedMOVL(N->op_begin(), N->getNumOperands(),
2350 V2IsSplat, V2IsUndef);
2353 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
2354 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
2355 bool X86::isMOVSHDUPMask(SDNode *N) {
2356 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2358 if (N->getNumOperands() != 4)
2361 // Expect 1, 1, 3, 3
2362 for (unsigned i = 0; i < 2; ++i) {
2363 SDOperand Arg = N->getOperand(i);
2364 if (Arg.getOpcode() == ISD::UNDEF) continue;
2365 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2366 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
2367 if (Val != 1) return false;
2371 for (unsigned i = 2; i < 4; ++i) {
2372 SDOperand Arg = N->getOperand(i);
2373 if (Arg.getOpcode() == ISD::UNDEF) continue;
2374 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2375 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
2376 if (Val != 3) return false;
2380 // Don't use movshdup if it can be done with a shufps.
2384 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
2385 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
2386 bool X86::isMOVSLDUPMask(SDNode *N) {
2387 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2389 if (N->getNumOperands() != 4)
2392 // Expect 0, 0, 2, 2
2393 for (unsigned i = 0; i < 2; ++i) {
2394 SDOperand Arg = N->getOperand(i);
2395 if (Arg.getOpcode() == ISD::UNDEF) continue;
2396 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2397 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
2398 if (Val != 0) return false;
2402 for (unsigned i = 2; i < 4; ++i) {
2403 SDOperand Arg = N->getOperand(i);
2404 if (Arg.getOpcode() == ISD::UNDEF) continue;
2405 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2406 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
2407 if (Val != 2) return false;
2411 // Don't use movshdup if it can be done with a shufps.
2415 /// isIdentityMask - Return true if the specified VECTOR_SHUFFLE operand
2416 /// specifies a identity operation on the LHS or RHS.
2417 static bool isIdentityMask(SDNode *N, bool RHS = false) {
2418 unsigned NumElems = N->getNumOperands();
2419 for (unsigned i = 0; i < NumElems; ++i)
2420 if (!isUndefOrEqual(N->getOperand(i), i + (RHS ? NumElems : 0)))
2425 /// isSplatMask - Return true if the specified VECTOR_SHUFFLE operand specifies
2426 /// a splat of a single element.
2427 static bool isSplatMask(SDNode *N) {
2428 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2430 // This is a splat operation if each element of the permute is the same, and
2431 // if the value doesn't reference the second vector.
2432 unsigned NumElems = N->getNumOperands();
2433 SDOperand ElementBase;
2435 for (; i != NumElems; ++i) {
2436 SDOperand Elt = N->getOperand(i);
2437 if (isa<ConstantSDNode>(Elt)) {
2443 if (!ElementBase.Val)
2446 for (; i != NumElems; ++i) {
2447 SDOperand Arg = N->getOperand(i);
2448 if (Arg.getOpcode() == ISD::UNDEF) continue;
2449 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2450 if (Arg != ElementBase) return false;
2453 // Make sure it is a splat of the first vector operand.
2454 return cast<ConstantSDNode>(ElementBase)->getValue() < NumElems;
2457 /// isSplatMask - Return true if the specified VECTOR_SHUFFLE operand specifies
2458 /// a splat of a single element and it's a 2 or 4 element mask.
2459 bool X86::isSplatMask(SDNode *N) {
2460 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2462 // We can only splat 64-bit, and 32-bit quantities with a single instruction.
2463 if (N->getNumOperands() != 4 && N->getNumOperands() != 2)
2465 return ::isSplatMask(N);
2468 /// isSplatLoMask - Return true if the specified VECTOR_SHUFFLE operand
2469 /// specifies a splat of zero element.
2470 bool X86::isSplatLoMask(SDNode *N) {
2471 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2473 for (unsigned i = 0, e = N->getNumOperands(); i < e; ++i)
2474 if (!isUndefOrEqual(N->getOperand(i), 0))
2479 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
2480 /// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUF* and SHUFP*
2482 unsigned X86::getShuffleSHUFImmediate(SDNode *N) {
2483 unsigned NumOperands = N->getNumOperands();
2484 unsigned Shift = (NumOperands == 4) ? 2 : 1;
2486 for (unsigned i = 0; i < NumOperands; ++i) {
2488 SDOperand Arg = N->getOperand(NumOperands-i-1);
2489 if (Arg.getOpcode() != ISD::UNDEF)
2490 Val = cast<ConstantSDNode>(Arg)->getValue();
2491 if (Val >= NumOperands) Val -= NumOperands;
2493 if (i != NumOperands - 1)
2500 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
2501 /// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUFHW
2503 unsigned X86::getShufflePSHUFHWImmediate(SDNode *N) {
2505 // 8 nodes, but we only care about the last 4.
2506 for (unsigned i = 7; i >= 4; --i) {
2508 SDOperand Arg = N->getOperand(i);
2509 if (Arg.getOpcode() != ISD::UNDEF)
2510 Val = cast<ConstantSDNode>(Arg)->getValue();
2519 /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
2520 /// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUFLW
2522 unsigned X86::getShufflePSHUFLWImmediate(SDNode *N) {
2524 // 8 nodes, but we only care about the first 4.
2525 for (int i = 3; i >= 0; --i) {
2527 SDOperand Arg = N->getOperand(i);
2528 if (Arg.getOpcode() != ISD::UNDEF)
2529 Val = cast<ConstantSDNode>(Arg)->getValue();
2538 /// isPSHUFHW_PSHUFLWMask - true if the specified VECTOR_SHUFFLE operand
2539 /// specifies a 8 element shuffle that can be broken into a pair of
2540 /// PSHUFHW and PSHUFLW.
2541 static bool isPSHUFHW_PSHUFLWMask(SDNode *N) {
2542 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2544 if (N->getNumOperands() != 8)
2547 // Lower quadword shuffled.
2548 for (unsigned i = 0; i != 4; ++i) {
2549 SDOperand Arg = N->getOperand(i);
2550 if (Arg.getOpcode() == ISD::UNDEF) continue;
2551 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2552 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
2557 // Upper quadword shuffled.
2558 for (unsigned i = 4; i != 8; ++i) {
2559 SDOperand Arg = N->getOperand(i);
2560 if (Arg.getOpcode() == ISD::UNDEF) continue;
2561 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2562 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
2563 if (Val < 4 || Val > 7)
2570 /// CommuteVectorShuffle - Swap vector_shuffle operands as well as
2571 /// values in ther permute mask.
2572 static SDOperand CommuteVectorShuffle(SDOperand Op, SDOperand &V1,
2573 SDOperand &V2, SDOperand &Mask,
2574 SelectionDAG &DAG) {
2575 MVT VT = Op.getValueType();
2576 MVT MaskVT = Mask.getValueType();
2577 MVT EltVT = MaskVT.getVectorElementType();
2578 unsigned NumElems = Mask.getNumOperands();
2579 SmallVector<SDOperand, 8> MaskVec;
2581 for (unsigned i = 0; i != NumElems; ++i) {
2582 SDOperand Arg = Mask.getOperand(i);
2583 if (Arg.getOpcode() == ISD::UNDEF) {
2584 MaskVec.push_back(DAG.getNode(ISD::UNDEF, EltVT));
2587 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2588 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
2590 MaskVec.push_back(DAG.getConstant(Val + NumElems, EltVT));
2592 MaskVec.push_back(DAG.getConstant(Val - NumElems, EltVT));
2596 Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], NumElems);
2597 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, Mask);
2600 /// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming
2601 /// the two vector operands have swapped position.
2603 SDOperand CommuteVectorShuffleMask(SDOperand Mask, SelectionDAG &DAG) {
2604 MVT MaskVT = Mask.getValueType();
2605 MVT EltVT = MaskVT.getVectorElementType();
2606 unsigned NumElems = Mask.getNumOperands();
2607 SmallVector<SDOperand, 8> MaskVec;
2608 for (unsigned i = 0; i != NumElems; ++i) {
2609 SDOperand Arg = Mask.getOperand(i);
2610 if (Arg.getOpcode() == ISD::UNDEF) {
2611 MaskVec.push_back(DAG.getNode(ISD::UNDEF, EltVT));
2614 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2615 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
2617 MaskVec.push_back(DAG.getConstant(Val + NumElems, EltVT));
2619 MaskVec.push_back(DAG.getConstant(Val - NumElems, EltVT));
2621 return DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], NumElems);
2625 /// ShouldXformToMOVHLPS - Return true if the node should be transformed to
2626 /// match movhlps. The lower half elements should come from upper half of
2627 /// V1 (and in order), and the upper half elements should come from the upper
2628 /// half of V2 (and in order).
2629 static bool ShouldXformToMOVHLPS(SDNode *Mask) {
2630 unsigned NumElems = Mask->getNumOperands();
2633 for (unsigned i = 0, e = 2; i != e; ++i)
2634 if (!isUndefOrEqual(Mask->getOperand(i), i+2))
2636 for (unsigned i = 2; i != 4; ++i)
2637 if (!isUndefOrEqual(Mask->getOperand(i), i+4))
2642 /// isScalarLoadToVector - Returns true if the node is a scalar load that
2643 /// is promoted to a vector. It also returns the LoadSDNode by reference if
2645 static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = NULL) {
2646 if (N->getOpcode() == ISD::SCALAR_TO_VECTOR) {
2647 N = N->getOperand(0).Val;
2648 if (ISD::isNON_EXTLoad(N)) {
2650 *LD = cast<LoadSDNode>(N);
2657 /// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to
2658 /// match movlp{s|d}. The lower half elements should come from lower half of
2659 /// V1 (and in order), and the upper half elements should come from the upper
2660 /// half of V2 (and in order). And since V1 will become the source of the
2661 /// MOVLP, it must be either a vector load or a scalar load to vector.
2662 static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2, SDNode *Mask) {
2663 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1))
2665 // Is V2 is a vector load, don't do this transformation. We will try to use
2666 // load folding shufps op.
2667 if (ISD::isNON_EXTLoad(V2))
2670 unsigned NumElems = Mask->getNumOperands();
2671 if (NumElems != 2 && NumElems != 4)
2673 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
2674 if (!isUndefOrEqual(Mask->getOperand(i), i))
2676 for (unsigned i = NumElems/2; i != NumElems; ++i)
2677 if (!isUndefOrEqual(Mask->getOperand(i), i+NumElems))
2682 /// isSplatVector - Returns true if N is a BUILD_VECTOR node whose elements are
2684 static bool isSplatVector(SDNode *N) {
2685 if (N->getOpcode() != ISD::BUILD_VECTOR)
2688 SDOperand SplatValue = N->getOperand(0);
2689 for (unsigned i = 1, e = N->getNumOperands(); i != e; ++i)
2690 if (N->getOperand(i) != SplatValue)
2695 /// isUndefShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
2697 static bool isUndefShuffle(SDNode *N) {
2698 if (N->getOpcode() != ISD::VECTOR_SHUFFLE)
2701 SDOperand V1 = N->getOperand(0);
2702 SDOperand V2 = N->getOperand(1);
2703 SDOperand Mask = N->getOperand(2);
2704 unsigned NumElems = Mask.getNumOperands();
2705 for (unsigned i = 0; i != NumElems; ++i) {
2706 SDOperand Arg = Mask.getOperand(i);
2707 if (Arg.getOpcode() != ISD::UNDEF) {
2708 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
2709 if (Val < NumElems && V1.getOpcode() != ISD::UNDEF)
2711 else if (Val >= NumElems && V2.getOpcode() != ISD::UNDEF)
2718 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
2720 static inline bool isZeroNode(SDOperand Elt) {
2721 return ((isa<ConstantSDNode>(Elt) &&
2722 cast<ConstantSDNode>(Elt)->getValue() == 0) ||
2723 (isa<ConstantFPSDNode>(Elt) &&
2724 cast<ConstantFPSDNode>(Elt)->getValueAPF().isPosZero()));
2727 /// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
2728 /// to an zero vector.
2729 static bool isZeroShuffle(SDNode *N) {
2730 if (N->getOpcode() != ISD::VECTOR_SHUFFLE)
2733 SDOperand V1 = N->getOperand(0);
2734 SDOperand V2 = N->getOperand(1);
2735 SDOperand Mask = N->getOperand(2);
2736 unsigned NumElems = Mask.getNumOperands();
2737 for (unsigned i = 0; i != NumElems; ++i) {
2738 SDOperand Arg = Mask.getOperand(i);
2739 if (Arg.getOpcode() == ISD::UNDEF)
2742 unsigned Idx = cast<ConstantSDNode>(Arg)->getValue();
2743 if (Idx < NumElems) {
2744 unsigned Opc = V1.Val->getOpcode();
2745 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.Val))
2747 if (Opc != ISD::BUILD_VECTOR ||
2748 !isZeroNode(V1.Val->getOperand(Idx)))
2750 } else if (Idx >= NumElems) {
2751 unsigned Opc = V2.Val->getOpcode();
2752 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.Val))
2754 if (Opc != ISD::BUILD_VECTOR ||
2755 !isZeroNode(V2.Val->getOperand(Idx - NumElems)))
2762 /// getZeroVector - Returns a vector of specified type with all zero elements.
2764 static SDOperand getZeroVector(MVT VT, bool HasSSE2, SelectionDAG &DAG) {
2765 assert(VT.isVector() && "Expected a vector type");
2767 // Always build zero vectors as <4 x i32> or <2 x i32> bitcasted to their dest
2768 // type. This ensures they get CSE'd.
2770 if (VT.getSizeInBits() == 64) { // MMX
2771 SDOperand Cst = DAG.getTargetConstant(0, MVT::i32);
2772 Vec = DAG.getNode(ISD::BUILD_VECTOR, MVT::v2i32, Cst, Cst);
2773 } else if (HasSSE2) { // SSE2
2774 SDOperand Cst = DAG.getTargetConstant(0, MVT::i32);
2775 Vec = DAG.getNode(ISD::BUILD_VECTOR, MVT::v4i32, Cst, Cst, Cst, Cst);
2777 SDOperand Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
2778 Vec = DAG.getNode(ISD::BUILD_VECTOR, MVT::v4f32, Cst, Cst, Cst, Cst);
2780 return DAG.getNode(ISD::BIT_CONVERT, VT, Vec);
2783 /// getOnesVector - Returns a vector of specified type with all bits set.
2785 static SDOperand getOnesVector(MVT VT, SelectionDAG &DAG) {
2786 assert(VT.isVector() && "Expected a vector type");
2788 // Always build ones vectors as <4 x i32> or <2 x i32> bitcasted to their dest
2789 // type. This ensures they get CSE'd.
2790 SDOperand Cst = DAG.getTargetConstant(~0U, MVT::i32);
2792 if (VT.getSizeInBits() == 64) // MMX
2793 Vec = DAG.getNode(ISD::BUILD_VECTOR, MVT::v2i32, Cst, Cst);
2795 Vec = DAG.getNode(ISD::BUILD_VECTOR, MVT::v4i32, Cst, Cst, Cst, Cst);
2796 return DAG.getNode(ISD::BIT_CONVERT, VT, Vec);
2800 /// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements
2801 /// that point to V2 points to its first element.
2802 static SDOperand NormalizeMask(SDOperand Mask, SelectionDAG &DAG) {
2803 assert(Mask.getOpcode() == ISD::BUILD_VECTOR);
2805 bool Changed = false;
2806 SmallVector<SDOperand, 8> MaskVec;
2807 unsigned NumElems = Mask.getNumOperands();
2808 for (unsigned i = 0; i != NumElems; ++i) {
2809 SDOperand Arg = Mask.getOperand(i);
2810 if (Arg.getOpcode() != ISD::UNDEF) {
2811 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
2812 if (Val > NumElems) {
2813 Arg = DAG.getConstant(NumElems, Arg.getValueType());
2817 MaskVec.push_back(Arg);
2821 Mask = DAG.getNode(ISD::BUILD_VECTOR, Mask.getValueType(),
2822 &MaskVec[0], MaskVec.size());
2826 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
2827 /// operation of specified width.
2828 static SDOperand getMOVLMask(unsigned NumElems, SelectionDAG &DAG) {
2829 MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems);
2830 MVT BaseVT = MaskVT.getVectorElementType();
2832 SmallVector<SDOperand, 8> MaskVec;
2833 MaskVec.push_back(DAG.getConstant(NumElems, BaseVT));
2834 for (unsigned i = 1; i != NumElems; ++i)
2835 MaskVec.push_back(DAG.getConstant(i, BaseVT));
2836 return DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], MaskVec.size());
2839 /// getUnpacklMask - Returns a vector_shuffle mask for an unpackl operation
2840 /// of specified width.
2841 static SDOperand getUnpacklMask(unsigned NumElems, SelectionDAG &DAG) {
2842 MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems);
2843 MVT BaseVT = MaskVT.getVectorElementType();
2844 SmallVector<SDOperand, 8> MaskVec;
2845 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
2846 MaskVec.push_back(DAG.getConstant(i, BaseVT));
2847 MaskVec.push_back(DAG.getConstant(i + NumElems, BaseVT));
2849 return DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], MaskVec.size());
2852 /// getUnpackhMask - Returns a vector_shuffle mask for an unpackh operation
2853 /// of specified width.
2854 static SDOperand getUnpackhMask(unsigned NumElems, SelectionDAG &DAG) {
2855 MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems);
2856 MVT BaseVT = MaskVT.getVectorElementType();
2857 unsigned Half = NumElems/2;
2858 SmallVector<SDOperand, 8> MaskVec;
2859 for (unsigned i = 0; i != Half; ++i) {
2860 MaskVec.push_back(DAG.getConstant(i + Half, BaseVT));
2861 MaskVec.push_back(DAG.getConstant(i + NumElems + Half, BaseVT));
2863 return DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], MaskVec.size());
2866 /// getSwapEltZeroMask - Returns a vector_shuffle mask for a shuffle that swaps
2867 /// element #0 of a vector with the specified index, leaving the rest of the
2868 /// elements in place.
2869 static SDOperand getSwapEltZeroMask(unsigned NumElems, unsigned DestElt,
2870 SelectionDAG &DAG) {
2871 MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems);
2872 MVT BaseVT = MaskVT.getVectorElementType();
2873 SmallVector<SDOperand, 8> MaskVec;
2874 // Element #0 of the result gets the elt we are replacing.
2875 MaskVec.push_back(DAG.getConstant(DestElt, BaseVT));
2876 for (unsigned i = 1; i != NumElems; ++i)
2877 MaskVec.push_back(DAG.getConstant(i == DestElt ? 0 : i, BaseVT));
2878 return DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], MaskVec.size());
2881 /// PromoteSplat - Promote a splat of v4f32, v8i16 or v16i8 to v4i32.
2882 static SDOperand PromoteSplat(SDOperand Op, SelectionDAG &DAG, bool HasSSE2) {
2883 MVT PVT = HasSSE2 ? MVT::v4i32 : MVT::v4f32;
2884 MVT VT = Op.getValueType();
2887 SDOperand V1 = Op.getOperand(0);
2888 SDOperand Mask = Op.getOperand(2);
2889 unsigned NumElems = Mask.getNumOperands();
2890 // Special handling of v4f32 -> v4i32.
2891 if (VT != MVT::v4f32) {
2892 Mask = getUnpacklMask(NumElems, DAG);
2893 while (NumElems > 4) {
2894 V1 = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V1, Mask);
2897 Mask = getZeroVector(MVT::v4i32, true, DAG);
2900 V1 = DAG.getNode(ISD::BIT_CONVERT, PVT, V1);
2901 SDOperand Shuffle = DAG.getNode(ISD::VECTOR_SHUFFLE, PVT, V1,
2902 DAG.getNode(ISD::UNDEF, PVT), Mask);
2903 return DAG.getNode(ISD::BIT_CONVERT, VT, Shuffle);
2906 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
2907 /// vector of zero or undef vector. This produces a shuffle where the low
2908 /// element of V2 is swizzled into the zero/undef vector, landing at element
2909 /// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
2910 static SDOperand getShuffleVectorZeroOrUndef(SDOperand V2, unsigned Idx,
2911 bool isZero, bool HasSSE2,
2912 SelectionDAG &DAG) {
2913 MVT VT = V2.getValueType();
2914 SDOperand V1 = isZero
2915 ? getZeroVector(VT, HasSSE2, DAG) : DAG.getNode(ISD::UNDEF, VT);
2916 unsigned NumElems = V2.getValueType().getVectorNumElements();
2917 MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems);
2918 MVT EVT = MaskVT.getVectorElementType();
2919 SmallVector<SDOperand, 16> MaskVec;
2920 for (unsigned i = 0; i != NumElems; ++i)
2921 if (i == Idx) // If this is the insertion idx, put the low elt of V2 here.
2922 MaskVec.push_back(DAG.getConstant(NumElems, EVT));
2924 MaskVec.push_back(DAG.getConstant(i, EVT));
2925 SDOperand Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
2926 &MaskVec[0], MaskVec.size());
2927 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, Mask);
2930 /// getNumOfConsecutiveZeros - Return the number of elements in a result of
2931 /// a shuffle that is zero.
2933 unsigned getNumOfConsecutiveZeros(SDOperand Op, SDOperand Mask,
2934 unsigned NumElems, bool Low,
2935 SelectionDAG &DAG) {
2936 unsigned NumZeros = 0;
2937 for (unsigned i = 0; i < NumElems; ++i) {
2938 unsigned Index = Low ? i : NumElems-i-1;
2939 SDOperand Idx = Mask.getOperand(Index);
2940 if (Idx.getOpcode() == ISD::UNDEF) {
2944 SDOperand Elt = DAG.getShuffleScalarElt(Op.Val, Index);
2945 if (Elt.Val && isZeroNode(Elt))
2953 /// isVectorShift - Returns true if the shuffle can be implemented as a
2954 /// logical left or right shift of a vector.
2955 static bool isVectorShift(SDOperand Op, SDOperand Mask, SelectionDAG &DAG,
2956 bool &isLeft, SDOperand &ShVal, unsigned &ShAmt) {
2957 unsigned NumElems = Mask.getNumOperands();
2960 unsigned NumZeros= getNumOfConsecutiveZeros(Op, Mask, NumElems, true, DAG);
2963 NumZeros = getNumOfConsecutiveZeros(Op, Mask, NumElems, false, DAG);
2968 bool SeenV1 = false;
2969 bool SeenV2 = false;
2970 for (unsigned i = NumZeros; i < NumElems; ++i) {
2971 unsigned Val = isLeft ? (i - NumZeros) : i;
2972 SDOperand Idx = Mask.getOperand(isLeft ? i : (i - NumZeros));
2973 if (Idx.getOpcode() == ISD::UNDEF)
2975 unsigned Index = cast<ConstantSDNode>(Idx)->getValue();
2976 if (Index < NumElems)
2985 if (SeenV1 && SeenV2)
2988 ShVal = SeenV1 ? Op.getOperand(0) : Op.getOperand(1);
2994 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
2996 static SDOperand LowerBuildVectorv16i8(SDOperand Op, unsigned NonZeros,
2997 unsigned NumNonZero, unsigned NumZero,
2998 SelectionDAG &DAG, TargetLowering &TLI) {
3004 for (unsigned i = 0; i < 16; ++i) {
3005 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
3006 if (ThisIsNonZero && First) {
3008 V = getZeroVector(MVT::v8i16, true, DAG);
3010 V = DAG.getNode(ISD::UNDEF, MVT::v8i16);
3015 SDOperand ThisElt(0, 0), LastElt(0, 0);
3016 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
3017 if (LastIsNonZero) {
3018 LastElt = DAG.getNode(ISD::ZERO_EXTEND, MVT::i16, Op.getOperand(i-1));
3020 if (ThisIsNonZero) {
3021 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, MVT::i16, Op.getOperand(i));
3022 ThisElt = DAG.getNode(ISD::SHL, MVT::i16,
3023 ThisElt, DAG.getConstant(8, MVT::i8));
3025 ThisElt = DAG.getNode(ISD::OR, MVT::i16, ThisElt, LastElt);
3030 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, MVT::v8i16, V, ThisElt,
3031 DAG.getIntPtrConstant(i/2));
3035 return DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, V);
3038 /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
3040 static SDOperand LowerBuildVectorv8i16(SDOperand Op, unsigned NonZeros,
3041 unsigned NumNonZero, unsigned NumZero,
3042 SelectionDAG &DAG, TargetLowering &TLI) {
3048 for (unsigned i = 0; i < 8; ++i) {
3049 bool isNonZero = (NonZeros & (1 << i)) != 0;
3053 V = getZeroVector(MVT::v8i16, true, DAG);
3055 V = DAG.getNode(ISD::UNDEF, MVT::v8i16);
3058 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, MVT::v8i16, V, Op.getOperand(i),
3059 DAG.getIntPtrConstant(i));
3066 /// getVShift - Return a vector logical shift node.
3068 static SDOperand getVShift(bool isLeft, MVT VT, SDOperand SrcOp,
3069 unsigned NumBits, SelectionDAG &DAG,
3070 const TargetLowering &TLI) {
3071 bool isMMX = VT.getSizeInBits() == 64;
3072 MVT ShVT = isMMX ? MVT::v1i64 : MVT::v2i64;
3073 unsigned Opc = isLeft ? X86ISD::VSHL : X86ISD::VSRL;
3074 SrcOp = DAG.getNode(ISD::BIT_CONVERT, ShVT, SrcOp);
3075 return DAG.getNode(ISD::BIT_CONVERT, VT,
3076 DAG.getNode(Opc, ShVT, SrcOp,
3077 DAG.getConstant(NumBits, TLI.getShiftAmountTy())));
3081 X86TargetLowering::LowerBUILD_VECTOR(SDOperand Op, SelectionDAG &DAG) {
3082 // All zero's are handled with pxor, all one's are handled with pcmpeqd.
3083 if (ISD::isBuildVectorAllZeros(Op.Val) || ISD::isBuildVectorAllOnes(Op.Val)) {
3084 // Canonicalize this to either <4 x i32> or <2 x i32> (SSE vs MMX) to
3085 // 1) ensure the zero vectors are CSE'd, and 2) ensure that i64 scalars are
3086 // eliminated on x86-32 hosts.
3087 if (Op.getValueType() == MVT::v4i32 || Op.getValueType() == MVT::v2i32)
3090 if (ISD::isBuildVectorAllOnes(Op.Val))
3091 return getOnesVector(Op.getValueType(), DAG);
3092 return getZeroVector(Op.getValueType(), Subtarget->hasSSE2(), DAG);
3095 MVT VT = Op.getValueType();
3096 MVT EVT = VT.getVectorElementType();
3097 unsigned EVTBits = EVT.getSizeInBits();
3099 unsigned NumElems = Op.getNumOperands();
3100 unsigned NumZero = 0;
3101 unsigned NumNonZero = 0;
3102 unsigned NonZeros = 0;
3103 bool IsAllConstants = true;
3104 SmallSet<SDOperand, 8> Values;
3105 for (unsigned i = 0; i < NumElems; ++i) {
3106 SDOperand Elt = Op.getOperand(i);
3107 if (Elt.getOpcode() == ISD::UNDEF)
3110 if (Elt.getOpcode() != ISD::Constant &&
3111 Elt.getOpcode() != ISD::ConstantFP)
3112 IsAllConstants = false;
3113 if (isZeroNode(Elt))
3116 NonZeros |= (1 << i);
3121 if (NumNonZero == 0) {
3122 // All undef vector. Return an UNDEF. All zero vectors were handled above.
3123 return DAG.getNode(ISD::UNDEF, VT);
3126 // Special case for single non-zero, non-undef, element.
3127 if (NumNonZero == 1 && NumElems <= 4) {
3128 unsigned Idx = CountTrailingZeros_32(NonZeros);
3129 SDOperand Item = Op.getOperand(Idx);
3131 // If this is an insertion of an i64 value on x86-32, and if the top bits of
3132 // the value are obviously zero, truncate the value to i32 and do the
3133 // insertion that way. Only do this if the value is non-constant or if the
3134 // value is a constant being inserted into element 0. It is cheaper to do
3135 // a constant pool load than it is to do a movd + shuffle.
3136 if (EVT == MVT::i64 && !Subtarget->is64Bit() &&
3137 (!IsAllConstants || Idx == 0)) {
3138 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
3139 // Handle MMX and SSE both.
3140 MVT VecVT = VT == MVT::v2i64 ? MVT::v4i32 : MVT::v2i32;
3141 unsigned VecElts = VT == MVT::v2i64 ? 4 : 2;
3143 // Truncate the value (which may itself be a constant) to i32, and
3144 // convert it to a vector with movd (S2V+shuffle to zero extend).
3145 Item = DAG.getNode(ISD::TRUNCATE, MVT::i32, Item);
3146 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, VecVT, Item);
3147 Item = getShuffleVectorZeroOrUndef(Item, 0, true,
3148 Subtarget->hasSSE2(), DAG);
3150 // Now we have our 32-bit value zero extended in the low element of
3151 // a vector. If Idx != 0, swizzle it into place.
3154 Item, DAG.getNode(ISD::UNDEF, Item.getValueType()),
3155 getSwapEltZeroMask(VecElts, Idx, DAG)
3157 Item = DAG.getNode(ISD::VECTOR_SHUFFLE, VecVT, Ops, 3);
3159 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Item);
3163 // If we have a constant or non-constant insertion into the low element of
3164 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
3165 // the rest of the elements. This will be matched as movd/movq/movss/movsd
3166 // depending on what the source datatype is. Because we can only get here
3167 // when NumElems <= 4, this only needs to handle i32/f32/i64/f64.
3169 // Don't do this for i64 values on x86-32.
3170 (EVT != MVT::i64 || Subtarget->is64Bit())) {
3171 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, Item);
3172 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
3173 return getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0,
3174 Subtarget->hasSSE2(), DAG);
3177 // Is it a vector logical left shift?
3178 if (NumElems == 2 && Idx == 1 &&
3179 isZeroNode(Op.getOperand(0)) && !isZeroNode(Op.getOperand(1))) {
3180 unsigned NumBits = VT.getSizeInBits();
3181 return getVShift(true, VT,
3182 DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, Op.getOperand(1)),
3183 NumBits/2, DAG, *this);
3186 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
3189 // Otherwise, if this is a vector with i32 or f32 elements, and the element
3190 // is a non-constant being inserted into an element other than the low one,
3191 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
3192 // movd/movss) to move this into the low element, then shuffle it into
3194 if (EVTBits == 32) {
3195 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, Item);
3197 // Turn it into a shuffle of zero and zero-extended scalar to vector.
3198 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0,
3199 Subtarget->hasSSE2(), DAG);
3200 MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems);
3201 MVT MaskEVT = MaskVT.getVectorElementType();
3202 SmallVector<SDOperand, 8> MaskVec;
3203 for (unsigned i = 0; i < NumElems; i++)
3204 MaskVec.push_back(DAG.getConstant((i == Idx) ? 0 : 1, MaskEVT));
3205 SDOperand Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3206 &MaskVec[0], MaskVec.size());
3207 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, Item,
3208 DAG.getNode(ISD::UNDEF, VT), Mask);
3212 // Splat is obviously ok. Let legalizer expand it to a shuffle.
3213 if (Values.size() == 1)
3216 // A vector full of immediates; various special cases are already
3217 // handled, so this is best done with a single constant-pool load.
3221 // Let legalizer expand 2-wide build_vectors.
3222 if (EVTBits == 64) {
3223 if (NumNonZero == 1) {
3224 // One half is zero or undef.
3225 unsigned Idx = CountTrailingZeros_32(NonZeros);
3226 SDOperand V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, VT,
3227 Op.getOperand(Idx));
3228 return getShuffleVectorZeroOrUndef(V2, Idx, true,
3229 Subtarget->hasSSE2(), DAG);
3234 // If element VT is < 32 bits, convert it to inserts into a zero vector.
3235 if (EVTBits == 8 && NumElems == 16) {
3236 SDOperand V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
3238 if (V.Val) return V;
3241 if (EVTBits == 16 && NumElems == 8) {
3242 SDOperand V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
3244 if (V.Val) return V;
3247 // If element VT is == 32 bits, turn it into a number of shuffles.
3248 SmallVector<SDOperand, 8> V;
3250 if (NumElems == 4 && NumZero > 0) {
3251 for (unsigned i = 0; i < 4; ++i) {
3252 bool isZero = !(NonZeros & (1 << i));
3254 V[i] = getZeroVector(VT, Subtarget->hasSSE2(), DAG);
3256 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, Op.getOperand(i));
3259 for (unsigned i = 0; i < 2; ++i) {
3260 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
3263 V[i] = V[i*2]; // Must be a zero vector.
3266 V[i] = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V[i*2+1], V[i*2],
3267 getMOVLMask(NumElems, DAG));
3270 V[i] = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V[i*2], V[i*2+1],
3271 getMOVLMask(NumElems, DAG));
3274 V[i] = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V[i*2], V[i*2+1],
3275 getUnpacklMask(NumElems, DAG));
3280 MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems);
3281 MVT EVT = MaskVT.getVectorElementType();
3282 SmallVector<SDOperand, 8> MaskVec;
3283 bool Reverse = (NonZeros & 0x3) == 2;
3284 for (unsigned i = 0; i < 2; ++i)
3286 MaskVec.push_back(DAG.getConstant(1-i, EVT));
3288 MaskVec.push_back(DAG.getConstant(i, EVT));
3289 Reverse = ((NonZeros & (0x3 << 2)) >> 2) == 2;
3290 for (unsigned i = 0; i < 2; ++i)
3292 MaskVec.push_back(DAG.getConstant(1-i+NumElems, EVT));
3294 MaskVec.push_back(DAG.getConstant(i+NumElems, EVT));
3295 SDOperand ShufMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3296 &MaskVec[0], MaskVec.size());
3297 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V[0], V[1], ShufMask);
3300 if (Values.size() > 2) {
3301 // Expand into a number of unpckl*.
3303 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
3304 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
3305 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
3306 SDOperand UnpckMask = getUnpacklMask(NumElems, DAG);
3307 for (unsigned i = 0; i < NumElems; ++i)
3308 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, Op.getOperand(i));
3310 while (NumElems != 0) {
3311 for (unsigned i = 0; i < NumElems; ++i)
3312 V[i] = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V[i], V[i + NumElems],
3323 SDOperand LowerVECTOR_SHUFFLEv8i16(SDOperand V1, SDOperand V2,
3324 SDOperand PermMask, SelectionDAG &DAG,
3325 TargetLowering &TLI) {
3327 MVT MaskVT = MVT::getIntVectorWithNumElements(8);
3328 MVT MaskEVT = MaskVT.getVectorElementType();
3329 MVT PtrVT = TLI.getPointerTy();
3330 SmallVector<SDOperand, 8> MaskElts(PermMask.Val->op_begin(),
3331 PermMask.Val->op_end());
3333 // First record which half of which vector the low elements come from.
3334 SmallVector<unsigned, 4> LowQuad(4);
3335 for (unsigned i = 0; i < 4; ++i) {
3336 SDOperand Elt = MaskElts[i];
3337 if (Elt.getOpcode() == ISD::UNDEF)
3339 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getValue();
3340 int QuadIdx = EltIdx / 4;
3343 int BestLowQuad = -1;
3344 unsigned MaxQuad = 1;
3345 for (unsigned i = 0; i < 4; ++i) {
3346 if (LowQuad[i] > MaxQuad) {
3348 MaxQuad = LowQuad[i];
3352 // Record which half of which vector the high elements come from.
3353 SmallVector<unsigned, 4> HighQuad(4);
3354 for (unsigned i = 4; i < 8; ++i) {
3355 SDOperand Elt = MaskElts[i];
3356 if (Elt.getOpcode() == ISD::UNDEF)
3358 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getValue();
3359 int QuadIdx = EltIdx / 4;
3360 ++HighQuad[QuadIdx];
3362 int BestHighQuad = -1;
3364 for (unsigned i = 0; i < 4; ++i) {
3365 if (HighQuad[i] > MaxQuad) {
3367 MaxQuad = HighQuad[i];
3371 // If it's possible to sort parts of either half with PSHUF{H|L}W, then do it.
3372 if (BestLowQuad != -1 || BestHighQuad != -1) {
3373 // First sort the 4 chunks in order using shufpd.
3374 SmallVector<SDOperand, 8> MaskVec;
3375 if (BestLowQuad != -1)
3376 MaskVec.push_back(DAG.getConstant(BestLowQuad, MVT::i32));
3378 MaskVec.push_back(DAG.getConstant(0, MVT::i32));
3379 if (BestHighQuad != -1)
3380 MaskVec.push_back(DAG.getConstant(BestHighQuad, MVT::i32));
3382 MaskVec.push_back(DAG.getConstant(1, MVT::i32));
3383 SDOperand Mask= DAG.getNode(ISD::BUILD_VECTOR, MVT::v2i32, &MaskVec[0],2);
3384 NewV = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v2i64,
3385 DAG.getNode(ISD::BIT_CONVERT, MVT::v2i64, V1),
3386 DAG.getNode(ISD::BIT_CONVERT, MVT::v2i64, V2), Mask);
3387 NewV = DAG.getNode(ISD::BIT_CONVERT, MVT::v8i16, NewV);
3389 // Now sort high and low parts separately.
3390 BitVector InOrder(8);
3391 if (BestLowQuad != -1) {
3392 // Sort lower half in order using PSHUFLW.
3394 bool AnyOutOrder = false;
3395 for (unsigned i = 0; i != 4; ++i) {
3396 SDOperand Elt = MaskElts[i];
3397 if (Elt.getOpcode() == ISD::UNDEF) {
3398 MaskVec.push_back(Elt);
3401 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getValue();
3404 MaskVec.push_back(DAG.getConstant(EltIdx % 4, MaskEVT));
3405 // If this element is in the right place after this shuffle, then
3407 if ((int)(EltIdx / 4) == BestLowQuad)
3412 for (unsigned i = 4; i != 8; ++i)
3413 MaskVec.push_back(DAG.getConstant(i, MaskEVT));
3414 SDOperand Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], 8);
3415 NewV = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v8i16, NewV, NewV, Mask);
3419 if (BestHighQuad != -1) {
3420 // Sort high half in order using PSHUFHW if possible.
3422 for (unsigned i = 0; i != 4; ++i)
3423 MaskVec.push_back(DAG.getConstant(i, MaskEVT));
3424 bool AnyOutOrder = false;
3425 for (unsigned i = 4; i != 8; ++i) {
3426 SDOperand Elt = MaskElts[i];
3427 if (Elt.getOpcode() == ISD::UNDEF) {
3428 MaskVec.push_back(Elt);
3431 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getValue();
3434 MaskVec.push_back(DAG.getConstant((EltIdx % 4) + 4, MaskEVT));
3435 // If this element is in the right place after this shuffle, then
3437 if ((int)(EltIdx / 4) == BestHighQuad)
3442 SDOperand Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], 8);
3443 NewV = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v8i16, NewV, NewV, Mask);
3447 // The other elements are put in the right place using pextrw and pinsrw.
3448 for (unsigned i = 0; i != 8; ++i) {
3451 SDOperand Elt = MaskElts[i];
3452 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getValue();
3453 SDOperand ExtOp = (EltIdx < 8)
3454 ? DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i16, V1,
3455 DAG.getConstant(EltIdx, PtrVT))
3456 : DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i16, V2,
3457 DAG.getConstant(EltIdx - 8, PtrVT));
3458 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, MVT::v8i16, NewV, ExtOp,
3459 DAG.getConstant(i, PtrVT));
3464 // PSHUF{H|L}W are not used. Lower into extracts and inserts but try to use
3465 ///as few as possible.
3466 // First, let's find out how many elements are already in the right order.
3467 unsigned V1InOrder = 0;
3468 unsigned V1FromV1 = 0;
3469 unsigned V2InOrder = 0;
3470 unsigned V2FromV2 = 0;
3471 SmallVector<SDOperand, 8> V1Elts;
3472 SmallVector<SDOperand, 8> V2Elts;
3473 for (unsigned i = 0; i < 8; ++i) {
3474 SDOperand Elt = MaskElts[i];
3475 if (Elt.getOpcode() == ISD::UNDEF) {
3476 V1Elts.push_back(Elt);
3477 V2Elts.push_back(Elt);
3482 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getValue();
3484 V1Elts.push_back(Elt);
3485 V2Elts.push_back(DAG.getConstant(i+8, MaskEVT));
3487 } else if (EltIdx == i+8) {
3488 V1Elts.push_back(Elt);
3489 V2Elts.push_back(DAG.getConstant(i, MaskEVT));
3491 } else if (EltIdx < 8) {
3492 V1Elts.push_back(Elt);
3495 V2Elts.push_back(DAG.getConstant(EltIdx-8, MaskEVT));
3500 if (V2InOrder > V1InOrder) {
3501 PermMask = CommuteVectorShuffleMask(PermMask, DAG);
3503 std::swap(V1Elts, V2Elts);
3504 std::swap(V1FromV1, V2FromV2);
3507 if ((V1FromV1 + V1InOrder) != 8) {
3508 // Some elements are from V2.
3510 // If there are elements that are from V1 but out of place,
3511 // then first sort them in place
3512 SmallVector<SDOperand, 8> MaskVec;
3513 for (unsigned i = 0; i < 8; ++i) {
3514 SDOperand Elt = V1Elts[i];
3515 if (Elt.getOpcode() == ISD::UNDEF) {
3516 MaskVec.push_back(DAG.getNode(ISD::UNDEF, MaskEVT));
3519 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getValue();
3521 MaskVec.push_back(DAG.getNode(ISD::UNDEF, MaskEVT));
3523 MaskVec.push_back(DAG.getConstant(EltIdx, MaskEVT));
3525 SDOperand Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], 8);
3526 V1 = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v8i16, V1, V1, Mask);
3530 for (unsigned i = 0; i < 8; ++i) {
3531 SDOperand Elt = V1Elts[i];
3532 if (Elt.getOpcode() == ISD::UNDEF)
3534 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getValue();
3537 SDOperand ExtOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i16, V2,
3538 DAG.getConstant(EltIdx - 8, PtrVT));
3539 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, MVT::v8i16, NewV, ExtOp,
3540 DAG.getConstant(i, PtrVT));
3544 // All elements are from V1.
3546 for (unsigned i = 0; i < 8; ++i) {
3547 SDOperand Elt = V1Elts[i];
3548 if (Elt.getOpcode() == ISD::UNDEF)
3550 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getValue();
3551 SDOperand ExtOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i16, V1,
3552 DAG.getConstant(EltIdx, PtrVT));
3553 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, MVT::v8i16, NewV, ExtOp,
3554 DAG.getConstant(i, PtrVT));
3560 /// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide
3561 /// ones, or rewriting v4i32 / v2f32 as 2 wide ones if possible. This can be
3562 /// done when every pair / quad of shuffle mask elements point to elements in
3563 /// the right sequence. e.g.
3564 /// vector_shuffle <>, <>, < 3, 4, | 10, 11, | 0, 1, | 14, 15>
3566 SDOperand RewriteAsNarrowerShuffle(SDOperand V1, SDOperand V2,
3568 SDOperand PermMask, SelectionDAG &DAG,
3569 TargetLowering &TLI) {
3570 unsigned NumElems = PermMask.getNumOperands();
3571 unsigned NewWidth = (NumElems == 4) ? 2 : 4;
3572 MVT MaskVT = MVT::getIntVectorWithNumElements(NewWidth);
3574 switch (VT.getSimpleVT()) {
3575 default: assert(false && "Unexpected!");
3576 case MVT::v4f32: NewVT = MVT::v2f64; break;
3577 case MVT::v4i32: NewVT = MVT::v2i64; break;
3578 case MVT::v8i16: NewVT = MVT::v4i32; break;
3579 case MVT::v16i8: NewVT = MVT::v4i32; break;
3582 if (NewWidth == 2) {
3588 unsigned Scale = NumElems / NewWidth;
3589 SmallVector<SDOperand, 8> MaskVec;
3590 for (unsigned i = 0; i < NumElems; i += Scale) {
3591 unsigned StartIdx = ~0U;
3592 for (unsigned j = 0; j < Scale; ++j) {
3593 SDOperand Elt = PermMask.getOperand(i+j);
3594 if (Elt.getOpcode() == ISD::UNDEF)
3596 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getValue();
3597 if (StartIdx == ~0U)
3598 StartIdx = EltIdx - (EltIdx % Scale);
3599 if (EltIdx != StartIdx + j)
3602 if (StartIdx == ~0U)
3603 MaskVec.push_back(DAG.getNode(ISD::UNDEF, MVT::i32));
3605 MaskVec.push_back(DAG.getConstant(StartIdx / Scale, MVT::i32));
3608 V1 = DAG.getNode(ISD::BIT_CONVERT, NewVT, V1);
3609 V2 = DAG.getNode(ISD::BIT_CONVERT, NewVT, V2);
3610 return DAG.getNode(ISD::VECTOR_SHUFFLE, NewVT, V1, V2,
3611 DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3612 &MaskVec[0], MaskVec.size()));
3615 /// getVZextMovL - Return a zero-extending vector move low node.
3617 static SDOperand getVZextMovL(MVT VT, MVT OpVT,
3618 SDOperand SrcOp, SelectionDAG &DAG,
3619 const X86Subtarget *Subtarget) {
3620 if (VT == MVT::v2f64 || VT == MVT::v4f32) {
3621 LoadSDNode *LD = NULL;
3622 if (!isScalarLoadToVector(SrcOp.Val, &LD))
3623 LD = dyn_cast<LoadSDNode>(SrcOp);
3625 // movssrr and movsdrr do not clear top bits. Try to use movd, movq
3627 MVT EVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32;
3628 if ((EVT != MVT::i64 || Subtarget->is64Bit()) &&
3629 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR &&
3630 SrcOp.getOperand(0).getOpcode() == ISD::BIT_CONVERT &&
3631 SrcOp.getOperand(0).getOperand(0).getValueType() == EVT) {
3633 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32;
3634 return DAG.getNode(ISD::BIT_CONVERT, VT,
3635 DAG.getNode(X86ISD::VZEXT_MOVL, OpVT,
3636 DAG.getNode(ISD::SCALAR_TO_VECTOR, OpVT,
3637 SrcOp.getOperand(0).getOperand(0))));
3642 return DAG.getNode(ISD::BIT_CONVERT, VT,
3643 DAG.getNode(X86ISD::VZEXT_MOVL, OpVT,
3644 DAG.getNode(ISD::BIT_CONVERT, OpVT, SrcOp)));
3648 X86TargetLowering::LowerVECTOR_SHUFFLE(SDOperand Op, SelectionDAG &DAG) {
3649 SDOperand V1 = Op.getOperand(0);
3650 SDOperand V2 = Op.getOperand(1);
3651 SDOperand PermMask = Op.getOperand(2);
3652 MVT VT = Op.getValueType();
3653 unsigned NumElems = PermMask.getNumOperands();
3654 bool isMMX = VT.getSizeInBits() == 64;
3655 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
3656 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
3657 bool V1IsSplat = false;
3658 bool V2IsSplat = false;
3660 if (isUndefShuffle(Op.Val))
3661 return DAG.getNode(ISD::UNDEF, VT);
3663 if (isZeroShuffle(Op.Val))
3664 return getZeroVector(VT, Subtarget->hasSSE2(), DAG);
3666 if (isIdentityMask(PermMask.Val))
3668 else if (isIdentityMask(PermMask.Val, true))
3671 if (isSplatMask(PermMask.Val)) {
3672 if (isMMX || NumElems < 4) return Op;
3673 // Promote it to a v4{if}32 splat.
3674 return PromoteSplat(Op, DAG, Subtarget->hasSSE2());
3677 // If the shuffle can be profitably rewritten as a narrower shuffle, then
3679 if (VT == MVT::v8i16 || VT == MVT::v16i8) {
3680 SDOperand NewOp= RewriteAsNarrowerShuffle(V1, V2, VT, PermMask, DAG, *this);
3682 return DAG.getNode(ISD::BIT_CONVERT, VT, LowerVECTOR_SHUFFLE(NewOp, DAG));
3683 } else if ((VT == MVT::v4i32 || (VT == MVT::v4f32 && Subtarget->hasSSE2()))) {
3684 // FIXME: Figure out a cleaner way to do this.
3685 // Try to make use of movq to zero out the top part.
3686 if (ISD::isBuildVectorAllZeros(V2.Val)) {
3687 SDOperand NewOp = RewriteAsNarrowerShuffle(V1, V2, VT, PermMask,
3690 SDOperand NewV1 = NewOp.getOperand(0);
3691 SDOperand NewV2 = NewOp.getOperand(1);
3692 SDOperand NewMask = NewOp.getOperand(2);
3693 if (isCommutedMOVL(NewMask.Val, true, false)) {
3694 NewOp = CommuteVectorShuffle(NewOp, NewV1, NewV2, NewMask, DAG);
3695 return getVZextMovL(VT, NewOp.getValueType(), NewV2, DAG, Subtarget);
3698 } else if (ISD::isBuildVectorAllZeros(V1.Val)) {
3699 SDOperand NewOp= RewriteAsNarrowerShuffle(V1, V2, VT, PermMask,
3701 if (NewOp.Val && X86::isMOVLMask(NewOp.getOperand(2).Val))
3702 return getVZextMovL(VT, NewOp.getValueType(), NewOp.getOperand(1),
3707 // Check if this can be converted into a logical shift.
3708 bool isLeft = false;
3711 bool isShift = isVectorShift(Op, PermMask, DAG, isLeft, ShVal, ShAmt);
3712 if (isShift && ShVal.hasOneUse()) {
3713 // If the shifted value has multiple uses, it may be cheaper to use
3714 // v_set0 + movlhps or movhlps, etc.
3715 MVT EVT = VT.getVectorElementType();
3716 ShAmt *= EVT.getSizeInBits();
3717 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this);
3720 if (X86::isMOVLMask(PermMask.Val)) {
3723 if (ISD::isBuildVectorAllZeros(V1.Val))
3724 return getVZextMovL(VT, VT, V2, DAG, Subtarget);
3728 if (X86::isMOVSHDUPMask(PermMask.Val) ||
3729 X86::isMOVSLDUPMask(PermMask.Val) ||
3730 X86::isMOVHLPSMask(PermMask.Val) ||
3731 X86::isMOVHPMask(PermMask.Val) ||
3732 X86::isMOVLPMask(PermMask.Val))
3735 if (ShouldXformToMOVHLPS(PermMask.Val) ||
3736 ShouldXformToMOVLP(V1.Val, V2.Val, PermMask.Val))
3737 return CommuteVectorShuffle(Op, V1, V2, PermMask, DAG);
3740 // No better options. Use a vshl / vsrl.
3741 MVT EVT = VT.getVectorElementType();
3742 ShAmt *= EVT.getSizeInBits();
3743 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this);
3746 bool Commuted = false;
3747 // FIXME: This should also accept a bitcast of a splat? Be careful, not
3748 // 1,1,1,1 -> v8i16 though.
3749 V1IsSplat = isSplatVector(V1.Val);
3750 V2IsSplat = isSplatVector(V2.Val);
3752 // Canonicalize the splat or undef, if present, to be on the RHS.
3753 if ((V1IsSplat || V1IsUndef) && !(V2IsSplat || V2IsUndef)) {
3754 Op = CommuteVectorShuffle(Op, V1, V2, PermMask, DAG);
3755 std::swap(V1IsSplat, V2IsSplat);
3756 std::swap(V1IsUndef, V2IsUndef);
3760 // FIXME: Figure out a cleaner way to do this.
3761 if (isCommutedMOVL(PermMask.Val, V2IsSplat, V2IsUndef)) {
3762 if (V2IsUndef) return V1;
3763 Op = CommuteVectorShuffle(Op, V1, V2, PermMask, DAG);
3765 // V2 is a splat, so the mask may be malformed. That is, it may point
3766 // to any V2 element. The instruction selectior won't like this. Get
3767 // a corrected mask and commute to form a proper MOVS{S|D}.
3768 SDOperand NewMask = getMOVLMask(NumElems, DAG);
3769 if (NewMask.Val != PermMask.Val)
3770 Op = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, NewMask);
3775 if (X86::isUNPCKL_v_undef_Mask(PermMask.Val) ||
3776 X86::isUNPCKH_v_undef_Mask(PermMask.Val) ||
3777 X86::isUNPCKLMask(PermMask.Val) ||
3778 X86::isUNPCKHMask(PermMask.Val))
3782 // Normalize mask so all entries that point to V2 points to its first
3783 // element then try to match unpck{h|l} again. If match, return a
3784 // new vector_shuffle with the corrected mask.
3785 SDOperand NewMask = NormalizeMask(PermMask, DAG);
3786 if (NewMask.Val != PermMask.Val) {
3787 if (X86::isUNPCKLMask(PermMask.Val, true)) {
3788 SDOperand NewMask = getUnpacklMask(NumElems, DAG);
3789 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, NewMask);
3790 } else if (X86::isUNPCKHMask(PermMask.Val, true)) {
3791 SDOperand NewMask = getUnpackhMask(NumElems, DAG);
3792 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, NewMask);
3797 // Normalize the node to match x86 shuffle ops if needed
3798 if (V2.getOpcode() != ISD::UNDEF && isCommutedSHUFP(PermMask.Val))
3799 Op = CommuteVectorShuffle(Op, V1, V2, PermMask, DAG);
3802 // Commute is back and try unpck* again.
3803 Op = CommuteVectorShuffle(Op, V1, V2, PermMask, DAG);
3804 if (X86::isUNPCKL_v_undef_Mask(PermMask.Val) ||
3805 X86::isUNPCKH_v_undef_Mask(PermMask.Val) ||
3806 X86::isUNPCKLMask(PermMask.Val) ||
3807 X86::isUNPCKHMask(PermMask.Val))
3811 // Try PSHUF* first, then SHUFP*.
3812 // MMX doesn't have PSHUFD but it does have PSHUFW. While it's theoretically
3813 // possible to shuffle a v2i32 using PSHUFW, that's not yet implemented.
3814 if (isMMX && NumElems == 4 && X86::isPSHUFDMask(PermMask.Val)) {
3815 if (V2.getOpcode() != ISD::UNDEF)
3816 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1,
3817 DAG.getNode(ISD::UNDEF, VT), PermMask);
3822 if (Subtarget->hasSSE2() &&
3823 (X86::isPSHUFDMask(PermMask.Val) ||
3824 X86::isPSHUFHWMask(PermMask.Val) ||
3825 X86::isPSHUFLWMask(PermMask.Val))) {
3827 if (VT == MVT::v4f32) {
3829 Op = DAG.getNode(ISD::VECTOR_SHUFFLE, RVT,
3830 DAG.getNode(ISD::BIT_CONVERT, RVT, V1),
3831 DAG.getNode(ISD::UNDEF, RVT), PermMask);
3832 } else if (V2.getOpcode() != ISD::UNDEF)
3833 Op = DAG.getNode(ISD::VECTOR_SHUFFLE, RVT, V1,
3834 DAG.getNode(ISD::UNDEF, RVT), PermMask);
3836 Op = DAG.getNode(ISD::BIT_CONVERT, VT, Op);
3840 // Binary or unary shufps.
3841 if (X86::isSHUFPMask(PermMask.Val) ||
3842 (V2.getOpcode() == ISD::UNDEF && X86::isPSHUFDMask(PermMask.Val)))
3846 // Handle v8i16 specifically since SSE can do byte extraction and insertion.
3847 if (VT == MVT::v8i16) {
3848 SDOperand NewOp = LowerVECTOR_SHUFFLEv8i16(V1, V2, PermMask, DAG, *this);
3853 // Handle all 4 wide cases with a number of shuffles.
3854 if (NumElems == 4 && !isMMX) {
3855 // Don't do this for MMX.
3856 MVT MaskVT = PermMask.getValueType();
3857 MVT MaskEVT = MaskVT.getVectorElementType();
3858 SmallVector<std::pair<int, int>, 8> Locs;
3859 Locs.reserve(NumElems);
3860 SmallVector<SDOperand, 8> Mask1(NumElems,
3861 DAG.getNode(ISD::UNDEF, MaskEVT));
3862 SmallVector<SDOperand, 8> Mask2(NumElems,
3863 DAG.getNode(ISD::UNDEF, MaskEVT));
3866 // If no more than two elements come from either vector. This can be
3867 // implemented with two shuffles. First shuffle gather the elements.
3868 // The second shuffle, which takes the first shuffle as both of its
3869 // vector operands, put the elements into the right order.
3870 for (unsigned i = 0; i != NumElems; ++i) {
3871 SDOperand Elt = PermMask.getOperand(i);
3872 if (Elt.getOpcode() == ISD::UNDEF) {
3873 Locs[i] = std::make_pair(-1, -1);
3875 unsigned Val = cast<ConstantSDNode>(Elt)->getValue();
3876 if (Val < NumElems) {
3877 Locs[i] = std::make_pair(0, NumLo);
3881 Locs[i] = std::make_pair(1, NumHi);
3882 if (2+NumHi < NumElems)
3883 Mask1[2+NumHi] = Elt;
3888 if (NumLo <= 2 && NumHi <= 2) {
3889 V1 = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2,
3890 DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3891 &Mask1[0], Mask1.size()));
3892 for (unsigned i = 0; i != NumElems; ++i) {
3893 if (Locs[i].first == -1)
3896 unsigned Idx = (i < NumElems/2) ? 0 : NumElems;
3897 Idx += Locs[i].first * (NumElems/2) + Locs[i].second;
3898 Mask2[i] = DAG.getConstant(Idx, MaskEVT);
3902 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V1,
3903 DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3904 &Mask2[0], Mask2.size()));
3907 // Break it into (shuffle shuffle_hi, shuffle_lo).
3909 SmallVector<SDOperand,8> LoMask(NumElems, DAG.getNode(ISD::UNDEF, MaskEVT));
3910 SmallVector<SDOperand,8> HiMask(NumElems, DAG.getNode(ISD::UNDEF, MaskEVT));
3911 SmallVector<SDOperand,8> *MaskPtr = &LoMask;
3912 unsigned MaskIdx = 0;
3914 unsigned HiIdx = NumElems/2;
3915 for (unsigned i = 0; i != NumElems; ++i) {
3916 if (i == NumElems/2) {
3922 SDOperand Elt = PermMask.getOperand(i);
3923 if (Elt.getOpcode() == ISD::UNDEF) {
3924 Locs[i] = std::make_pair(-1, -1);
3925 } else if (cast<ConstantSDNode>(Elt)->getValue() < NumElems) {
3926 Locs[i] = std::make_pair(MaskIdx, LoIdx);
3927 (*MaskPtr)[LoIdx] = Elt;
3930 Locs[i] = std::make_pair(MaskIdx, HiIdx);
3931 (*MaskPtr)[HiIdx] = Elt;
3936 SDOperand LoShuffle =
3937 DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2,
3938 DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3939 &LoMask[0], LoMask.size()));
3940 SDOperand HiShuffle =
3941 DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2,
3942 DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3943 &HiMask[0], HiMask.size()));
3944 SmallVector<SDOperand, 8> MaskOps;
3945 for (unsigned i = 0; i != NumElems; ++i) {
3946 if (Locs[i].first == -1) {
3947 MaskOps.push_back(DAG.getNode(ISD::UNDEF, MaskEVT));
3949 unsigned Idx = Locs[i].first * NumElems + Locs[i].second;
3950 MaskOps.push_back(DAG.getConstant(Idx, MaskEVT));
3953 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, LoShuffle, HiShuffle,
3954 DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3955 &MaskOps[0], MaskOps.size()));
3962 X86TargetLowering::LowerEXTRACT_VECTOR_ELT_SSE4(SDOperand Op,
3963 SelectionDAG &DAG) {
3964 MVT VT = Op.getValueType();
3965 if (VT.getSizeInBits() == 8) {
3966 SDOperand Extract = DAG.getNode(X86ISD::PEXTRB, MVT::i32,
3967 Op.getOperand(0), Op.getOperand(1));
3968 SDOperand Assert = DAG.getNode(ISD::AssertZext, MVT::i32, Extract,
3969 DAG.getValueType(VT));
3970 return DAG.getNode(ISD::TRUNCATE, VT, Assert);
3971 } else if (VT.getSizeInBits() == 16) {
3972 SDOperand Extract = DAG.getNode(X86ISD::PEXTRW, MVT::i32,
3973 Op.getOperand(0), Op.getOperand(1));
3974 SDOperand Assert = DAG.getNode(ISD::AssertZext, MVT::i32, Extract,
3975 DAG.getValueType(VT));
3976 return DAG.getNode(ISD::TRUNCATE, VT, Assert);
3977 } else if (VT == MVT::f32) {
3978 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
3979 // the result back to FR32 register. It's only worth matching if the
3980 // result has a single use which is a store or a bitcast to i32.
3981 if (!Op.hasOneUse())
3983 SDNode *User = Op.Val->use_begin()->getUser();
3984 if (User->getOpcode() != ISD::STORE &&
3985 (User->getOpcode() != ISD::BIT_CONVERT ||
3986 User->getValueType(0) != MVT::i32))
3988 SDOperand Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i32,
3989 DAG.getNode(ISD::BIT_CONVERT, MVT::v4i32, Op.getOperand(0)),
3991 return DAG.getNode(ISD::BIT_CONVERT, MVT::f32, Extract);
3998 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDOperand Op, SelectionDAG &DAG) {
3999 if (!isa<ConstantSDNode>(Op.getOperand(1)))
4002 if (Subtarget->hasSSE41()) {
4003 SDOperand Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG);
4008 MVT VT = Op.getValueType();
4009 // TODO: handle v16i8.
4010 if (VT.getSizeInBits() == 16) {
4011 SDOperand Vec = Op.getOperand(0);
4012 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getValue();
4014 return DAG.getNode(ISD::TRUNCATE, MVT::i16,
4015 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i32,
4016 DAG.getNode(ISD::BIT_CONVERT, MVT::v4i32, Vec),
4018 // Transform it so it match pextrw which produces a 32-bit result.
4019 MVT EVT = (MVT::SimpleValueType)(VT.getSimpleVT()+1);
4020 SDOperand Extract = DAG.getNode(X86ISD::PEXTRW, EVT,
4021 Op.getOperand(0), Op.getOperand(1));
4022 SDOperand Assert = DAG.getNode(ISD::AssertZext, EVT, Extract,
4023 DAG.getValueType(VT));
4024 return DAG.getNode(ISD::TRUNCATE, VT, Assert);
4025 } else if (VT.getSizeInBits() == 32) {
4026 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getValue();
4029 // SHUFPS the element to the lowest double word, then movss.
4030 MVT MaskVT = MVT::getIntVectorWithNumElements(4);
4031 SmallVector<SDOperand, 8> IdxVec;
4033 push_back(DAG.getConstant(Idx, MaskVT.getVectorElementType()));
4035 push_back(DAG.getNode(ISD::UNDEF, MaskVT.getVectorElementType()));
4037 push_back(DAG.getNode(ISD::UNDEF, MaskVT.getVectorElementType()));
4039 push_back(DAG.getNode(ISD::UNDEF, MaskVT.getVectorElementType()));
4040 SDOperand Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
4041 &IdxVec[0], IdxVec.size());
4042 SDOperand Vec = Op.getOperand(0);
4043 Vec = DAG.getNode(ISD::VECTOR_SHUFFLE, Vec.getValueType(),
4044 Vec, DAG.getNode(ISD::UNDEF, Vec.getValueType()), Mask);
4045 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, VT, Vec,
4046 DAG.getIntPtrConstant(0));
4047 } else if (VT.getSizeInBits() == 64) {
4048 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
4049 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
4050 // to match extract_elt for f64.
4051 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getValue();
4055 // UNPCKHPD the element to the lowest double word, then movsd.
4056 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
4057 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
4058 MVT MaskVT = MVT::getIntVectorWithNumElements(4);
4059 SmallVector<SDOperand, 8> IdxVec;
4060 IdxVec.push_back(DAG.getConstant(1, MaskVT.getVectorElementType()));
4062 push_back(DAG.getNode(ISD::UNDEF, MaskVT.getVectorElementType()));
4063 SDOperand Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
4064 &IdxVec[0], IdxVec.size());
4065 SDOperand Vec = Op.getOperand(0);
4066 Vec = DAG.getNode(ISD::VECTOR_SHUFFLE, Vec.getValueType(),
4067 Vec, DAG.getNode(ISD::UNDEF, Vec.getValueType()), Mask);
4068 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, VT, Vec,
4069 DAG.getIntPtrConstant(0));
4076 X86TargetLowering::LowerINSERT_VECTOR_ELT_SSE4(SDOperand Op, SelectionDAG &DAG){
4077 MVT VT = Op.getValueType();
4078 MVT EVT = VT.getVectorElementType();
4080 SDOperand N0 = Op.getOperand(0);
4081 SDOperand N1 = Op.getOperand(1);
4082 SDOperand N2 = Op.getOperand(2);
4084 if ((EVT.getSizeInBits() == 8) || (EVT.getSizeInBits() == 16)) {
4085 unsigned Opc = (EVT.getSizeInBits() == 8) ? X86ISD::PINSRB
4087 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
4089 if (N1.getValueType() != MVT::i32)
4090 N1 = DAG.getNode(ISD::ANY_EXTEND, MVT::i32, N1);
4091 if (N2.getValueType() != MVT::i32)
4092 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getValue());
4093 return DAG.getNode(Opc, VT, N0, N1, N2);
4094 } else if (EVT == MVT::f32) {
4095 // Bits [7:6] of the constant are the source select. This will always be
4096 // zero here. The DAG Combiner may combine an extract_elt index into these
4097 // bits. For example (insert (extract, 3), 2) could be matched by putting
4098 // the '3' into bits [7:6] of X86ISD::INSERTPS.
4099 // Bits [5:4] of the constant are the destination select. This is the
4100 // value of the incoming immediate.
4101 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
4102 // combine either bitwise AND or insert of float 0.0 to set these bits.
4103 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getValue() << 4);
4104 return DAG.getNode(X86ISD::INSERTPS, VT, N0, N1, N2);
4110 X86TargetLowering::LowerINSERT_VECTOR_ELT(SDOperand Op, SelectionDAG &DAG) {
4111 MVT VT = Op.getValueType();
4112 MVT EVT = VT.getVectorElementType();
4114 if (Subtarget->hasSSE41())
4115 return LowerINSERT_VECTOR_ELT_SSE4(Op, DAG);
4120 SDOperand N0 = Op.getOperand(0);
4121 SDOperand N1 = Op.getOperand(1);
4122 SDOperand N2 = Op.getOperand(2);
4124 if (EVT.getSizeInBits() == 16) {
4125 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
4126 // as its second argument.
4127 if (N1.getValueType() != MVT::i32)
4128 N1 = DAG.getNode(ISD::ANY_EXTEND, MVT::i32, N1);
4129 if (N2.getValueType() != MVT::i32)
4130 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getValue());
4131 return DAG.getNode(X86ISD::PINSRW, VT, N0, N1, N2);
4137 X86TargetLowering::LowerSCALAR_TO_VECTOR(SDOperand Op, SelectionDAG &DAG) {
4138 SDOperand AnyExt = DAG.getNode(ISD::ANY_EXTEND, MVT::i32, Op.getOperand(0));
4139 MVT VT = MVT::v2i32;
4140 switch (Op.getValueType().getSimpleVT()) {
4147 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(),
4148 DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, AnyExt));
4151 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
4152 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
4153 // one of the above mentioned nodes. It has to be wrapped because otherwise
4154 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
4155 // be used to form addressing mode. These wrapped nodes will be selected
4158 X86TargetLowering::LowerConstantPool(SDOperand Op, SelectionDAG &DAG) {
4159 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
4160 SDOperand Result = DAG.getTargetConstantPool(CP->getConstVal(),
4162 CP->getAlignment());
4163 Result = DAG.getNode(X86ISD::Wrapper, getPointerTy(), Result);
4164 // With PIC, the address is actually $g + Offset.
4165 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
4166 !Subtarget->isPICStyleRIPRel()) {
4167 Result = DAG.getNode(ISD::ADD, getPointerTy(),
4168 DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()),
4176 X86TargetLowering::LowerGlobalAddress(SDOperand Op, SelectionDAG &DAG) {
4177 GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
4178 SDOperand Result = DAG.getTargetGlobalAddress(GV, getPointerTy());
4179 Result = DAG.getNode(X86ISD::Wrapper, getPointerTy(), Result);
4180 // With PIC, the address is actually $g + Offset.
4181 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
4182 !Subtarget->isPICStyleRIPRel()) {
4183 Result = DAG.getNode(ISD::ADD, getPointerTy(),
4184 DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()),
4188 // For Darwin & Mingw32, external and weak symbols are indirect, so we want to
4189 // load the value at address GV, not the value of GV itself. This means that
4190 // the GlobalAddress must be in the base or index register of the address, not
4191 // the GV offset field. Platform check is inside GVRequiresExtraLoad() call
4192 // The same applies for external symbols during PIC codegen
4193 if (Subtarget->GVRequiresExtraLoad(GV, getTargetMachine(), false))
4194 Result = DAG.getLoad(getPointerTy(), DAG.getEntryNode(), Result,
4195 PseudoSourceValue::getGOT(), 0);
4200 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
4202 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
4205 SDOperand Chain = DAG.getCopyToReg(DAG.getEntryNode(), X86::EBX,
4206 DAG.getNode(X86ISD::GlobalBaseReg,
4208 InFlag = Chain.getValue(1);
4210 // emit leal symbol@TLSGD(,%ebx,1), %eax
4211 SDVTList NodeTys = DAG.getVTList(PtrVT, MVT::Other, MVT::Flag);
4212 SDOperand TGA = DAG.getTargetGlobalAddress(GA->getGlobal(),
4213 GA->getValueType(0),
4215 SDOperand Ops[] = { Chain, TGA, InFlag };
4216 SDOperand Result = DAG.getNode(X86ISD::TLSADDR, NodeTys, Ops, 3);
4217 InFlag = Result.getValue(2);
4218 Chain = Result.getValue(1);
4220 // call ___tls_get_addr. This function receives its argument in
4221 // the register EAX.
4222 Chain = DAG.getCopyToReg(Chain, X86::EAX, Result, InFlag);
4223 InFlag = Chain.getValue(1);
4225 NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
4226 SDOperand Ops1[] = { Chain,
4227 DAG.getTargetExternalSymbol("___tls_get_addr",
4229 DAG.getRegister(X86::EAX, PtrVT),
4230 DAG.getRegister(X86::EBX, PtrVT),
4232 Chain = DAG.getNode(X86ISD::CALL, NodeTys, Ops1, 5);
4233 InFlag = Chain.getValue(1);
4235 return DAG.getCopyFromReg(Chain, X86::EAX, PtrVT, InFlag);
4238 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
4240 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
4242 SDOperand InFlag, Chain;
4244 // emit leaq symbol@TLSGD(%rip), %rdi
4245 SDVTList NodeTys = DAG.getVTList(PtrVT, MVT::Other, MVT::Flag);
4246 SDOperand TGA = DAG.getTargetGlobalAddress(GA->getGlobal(),
4247 GA->getValueType(0),
4249 SDOperand Ops[] = { DAG.getEntryNode(), TGA};
4250 SDOperand Result = DAG.getNode(X86ISD::TLSADDR, NodeTys, Ops, 2);
4251 Chain = Result.getValue(1);
4252 InFlag = Result.getValue(2);
4254 // call ___tls_get_addr. This function receives its argument in
4255 // the register RDI.
4256 Chain = DAG.getCopyToReg(Chain, X86::RDI, Result, InFlag);
4257 InFlag = Chain.getValue(1);
4259 NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
4260 SDOperand Ops1[] = { Chain,
4261 DAG.getTargetExternalSymbol("___tls_get_addr",
4263 DAG.getRegister(X86::RDI, PtrVT),
4265 Chain = DAG.getNode(X86ISD::CALL, NodeTys, Ops1, 4);
4266 InFlag = Chain.getValue(1);
4268 return DAG.getCopyFromReg(Chain, X86::RAX, PtrVT, InFlag);
4271 // Lower ISD::GlobalTLSAddress using the "initial exec" (for no-pic) or
4272 // "local exec" model.
4273 static SDOperand LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
4275 // Get the Thread Pointer
4276 SDOperand ThreadPointer = DAG.getNode(X86ISD::THREAD_POINTER, PtrVT);
4277 // emit "addl x@ntpoff,%eax" (local exec) or "addl x@indntpoff,%eax" (initial
4279 SDOperand TGA = DAG.getTargetGlobalAddress(GA->getGlobal(),
4280 GA->getValueType(0),
4282 SDOperand Offset = DAG.getNode(X86ISD::Wrapper, PtrVT, TGA);
4284 if (GA->getGlobal()->isDeclaration()) // initial exec TLS model
4285 Offset = DAG.getLoad(PtrVT, DAG.getEntryNode(), Offset,
4286 PseudoSourceValue::getGOT(), 0);
4288 // The address of the thread local variable is the add of the thread
4289 // pointer with the offset of the variable.
4290 return DAG.getNode(ISD::ADD, PtrVT, ThreadPointer, Offset);
4294 X86TargetLowering::LowerGlobalTLSAddress(SDOperand Op, SelectionDAG &DAG) {
4295 // TODO: implement the "local dynamic" model
4296 // TODO: implement the "initial exec"model for pic executables
4297 assert(Subtarget->isTargetELF() &&
4298 "TLS not implemented for non-ELF targets");
4299 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
4300 // If the relocation model is PIC, use the "General Dynamic" TLS Model,
4301 // otherwise use the "Local Exec"TLS Model
4302 if (Subtarget->is64Bit()) {
4303 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy());
4305 if (getTargetMachine().getRelocationModel() == Reloc::PIC_)
4306 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy());
4308 return LowerToTLSExecModel(GA, DAG, getPointerTy());
4313 X86TargetLowering::LowerExternalSymbol(SDOperand Op, SelectionDAG &DAG) {
4314 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
4315 SDOperand Result = DAG.getTargetExternalSymbol(Sym, getPointerTy());
4316 Result = DAG.getNode(X86ISD::Wrapper, getPointerTy(), Result);
4317 // With PIC, the address is actually $g + Offset.
4318 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
4319 !Subtarget->isPICStyleRIPRel()) {
4320 Result = DAG.getNode(ISD::ADD, getPointerTy(),
4321 DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()),
4328 SDOperand X86TargetLowering::LowerJumpTable(SDOperand Op, SelectionDAG &DAG) {
4329 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
4330 SDOperand Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy());
4331 Result = DAG.getNode(X86ISD::Wrapper, getPointerTy(), Result);
4332 // With PIC, the address is actually $g + Offset.
4333 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
4334 !Subtarget->isPICStyleRIPRel()) {
4335 Result = DAG.getNode(ISD::ADD, getPointerTy(),
4336 DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()),
4343 /// LowerShift - Lower SRA_PARTS and friends, which return two i32 values and
4344 /// take a 2 x i32 value to shift plus a shift amount.
4345 SDOperand X86TargetLowering::LowerShift(SDOperand Op, SelectionDAG &DAG) {
4346 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
4347 MVT VT = Op.getValueType();
4348 unsigned VTBits = VT.getSizeInBits();
4349 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
4350 SDOperand ShOpLo = Op.getOperand(0);
4351 SDOperand ShOpHi = Op.getOperand(1);
4352 SDOperand ShAmt = Op.getOperand(2);
4353 SDOperand Tmp1 = isSRA ?
4354 DAG.getNode(ISD::SRA, VT, ShOpHi, DAG.getConstant(VTBits - 1, MVT::i8)) :
4355 DAG.getConstant(0, VT);
4357 SDOperand Tmp2, Tmp3;
4358 if (Op.getOpcode() == ISD::SHL_PARTS) {
4359 Tmp2 = DAG.getNode(X86ISD::SHLD, VT, ShOpHi, ShOpLo, ShAmt);
4360 Tmp3 = DAG.getNode(ISD::SHL, VT, ShOpLo, ShAmt);
4362 Tmp2 = DAG.getNode(X86ISD::SHRD, VT, ShOpLo, ShOpHi, ShAmt);
4363 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, VT, ShOpHi, ShAmt);
4366 SDOperand AndNode = DAG.getNode(ISD::AND, MVT::i8, ShAmt,
4367 DAG.getConstant(VTBits, MVT::i8));
4368 SDOperand Cond = DAG.getNode(X86ISD::CMP, VT,
4369 AndNode, DAG.getConstant(0, MVT::i8));
4372 SDOperand CC = DAG.getConstant(X86::COND_NE, MVT::i8);
4373 SDOperand Ops0[4] = { Tmp2, Tmp3, CC, Cond };
4374 SDOperand Ops1[4] = { Tmp3, Tmp1, CC, Cond };
4376 if (Op.getOpcode() == ISD::SHL_PARTS) {
4377 Hi = DAG.getNode(X86ISD::CMOV, VT, Ops0, 4);
4378 Lo = DAG.getNode(X86ISD::CMOV, VT, Ops1, 4);
4380 Lo = DAG.getNode(X86ISD::CMOV, VT, Ops0, 4);
4381 Hi = DAG.getNode(X86ISD::CMOV, VT, Ops1, 4);
4384 SDOperand Ops[2] = { Lo, Hi };
4385 return DAG.getMergeValues(Ops, 2);
4388 SDOperand X86TargetLowering::LowerSINT_TO_FP(SDOperand Op, SelectionDAG &DAG) {
4389 MVT SrcVT = Op.getOperand(0).getValueType();
4390 assert(SrcVT.getSimpleVT() <= MVT::i64 && SrcVT.getSimpleVT() >= MVT::i16 &&
4391 "Unknown SINT_TO_FP to lower!");
4393 // These are really Legal; caller falls through into that case.
4394 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
4396 if (SrcVT == MVT::i64 && Op.getValueType() != MVT::f80 &&
4397 Subtarget->is64Bit())
4400 unsigned Size = SrcVT.getSizeInBits()/8;
4401 MachineFunction &MF = DAG.getMachineFunction();
4402 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size);
4403 SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
4404 SDOperand Chain = DAG.getStore(DAG.getEntryNode(), Op.getOperand(0),
4406 PseudoSourceValue::getFixedStack(),
4411 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
4413 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Flag);
4415 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
4416 SmallVector<SDOperand, 8> Ops;
4417 Ops.push_back(Chain);
4418 Ops.push_back(StackSlot);
4419 Ops.push_back(DAG.getValueType(SrcVT));
4420 SDOperand Result = DAG.getNode(useSSE ? X86ISD::FILD_FLAG : X86ISD::FILD,
4421 Tys, &Ops[0], Ops.size());
4424 Chain = Result.getValue(1);
4425 SDOperand InFlag = Result.getValue(2);
4427 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
4428 // shouldn't be necessary except that RFP cannot be live across
4429 // multiple blocks. When stackifier is fixed, they can be uncoupled.
4430 MachineFunction &MF = DAG.getMachineFunction();
4431 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8);
4432 SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
4433 Tys = DAG.getVTList(MVT::Other);
4434 SmallVector<SDOperand, 8> Ops;
4435 Ops.push_back(Chain);
4436 Ops.push_back(Result);
4437 Ops.push_back(StackSlot);
4438 Ops.push_back(DAG.getValueType(Op.getValueType()));
4439 Ops.push_back(InFlag);
4440 Chain = DAG.getNode(X86ISD::FST, Tys, &Ops[0], Ops.size());
4441 Result = DAG.getLoad(Op.getValueType(), Chain, StackSlot,
4442 PseudoSourceValue::getFixedStack(), SSFI);
4448 std::pair<SDOperand,SDOperand> X86TargetLowering::
4449 FP_TO_SINTHelper(SDOperand Op, SelectionDAG &DAG) {
4450 assert(Op.getValueType().getSimpleVT() <= MVT::i64 &&
4451 Op.getValueType().getSimpleVT() >= MVT::i16 &&
4452 "Unknown FP_TO_SINT to lower!");
4454 // These are really Legal.
4455 if (Op.getValueType() == MVT::i32 &&
4456 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
4457 return std::make_pair(SDOperand(), SDOperand());
4458 if (Subtarget->is64Bit() &&
4459 Op.getValueType() == MVT::i64 &&
4460 Op.getOperand(0).getValueType() != MVT::f80)
4461 return std::make_pair(SDOperand(), SDOperand());
4463 // We lower FP->sint64 into FISTP64, followed by a load, all to a temporary
4465 MachineFunction &MF = DAG.getMachineFunction();
4466 unsigned MemSize = Op.getValueType().getSizeInBits()/8;
4467 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize);
4468 SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
4470 switch (Op.getValueType().getSimpleVT()) {
4471 default: assert(0 && "Invalid FP_TO_SINT to lower!");
4472 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
4473 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
4474 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
4477 SDOperand Chain = DAG.getEntryNode();
4478 SDOperand Value = Op.getOperand(0);
4479 if (isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType())) {
4480 assert(Op.getValueType() == MVT::i64 && "Invalid FP_TO_SINT to lower!");
4481 Chain = DAG.getStore(Chain, Value, StackSlot,
4482 PseudoSourceValue::getFixedStack(), SSFI);
4483 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
4485 Chain, StackSlot, DAG.getValueType(Op.getOperand(0).getValueType())
4487 Value = DAG.getNode(X86ISD::FLD, Tys, Ops, 3);
4488 Chain = Value.getValue(1);
4489 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize);
4490 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
4493 // Build the FP_TO_INT*_IN_MEM
4494 SDOperand Ops[] = { Chain, Value, StackSlot };
4495 SDOperand FIST = DAG.getNode(Opc, MVT::Other, Ops, 3);
4497 return std::make_pair(FIST, StackSlot);
4500 SDOperand X86TargetLowering::LowerFP_TO_SINT(SDOperand Op, SelectionDAG &DAG) {
4501 std::pair<SDOperand,SDOperand> Vals = FP_TO_SINTHelper(Op, DAG);
4502 SDOperand FIST = Vals.first, StackSlot = Vals.second;
4503 if (FIST.Val == 0) return SDOperand();
4506 return DAG.getLoad(Op.getValueType(), FIST, StackSlot, NULL, 0);
4509 SDNode *X86TargetLowering::ExpandFP_TO_SINT(SDNode *N, SelectionDAG &DAG) {
4510 std::pair<SDOperand,SDOperand> Vals = FP_TO_SINTHelper(SDOperand(N, 0), DAG);
4511 SDOperand FIST = Vals.first, StackSlot = Vals.second;
4512 if (FIST.Val == 0) return 0;
4514 MVT VT = N->getValueType(0);
4516 // Return a load from the stack slot.
4517 SDOperand Res = DAG.getLoad(VT, FIST, StackSlot, NULL, 0);
4519 // Use MERGE_VALUES to drop the chain result value and get a node with one
4520 // result. This requires turning off getMergeValues simplification, since
4521 // otherwise it will give us Res back.
4522 return DAG.getMergeValues(&Res, 1, false).Val;
4525 SDOperand X86TargetLowering::LowerFABS(SDOperand Op, SelectionDAG &DAG) {
4526 MVT VT = Op.getValueType();
4529 EltVT = VT.getVectorElementType();
4530 std::vector<Constant*> CV;
4531 if (EltVT == MVT::f64) {
4532 Constant *C = ConstantFP::get(APFloat(APInt(64, ~(1ULL << 63))));
4536 Constant *C = ConstantFP::get(APFloat(APInt(32, ~(1U << 31))));
4542 Constant *C = ConstantVector::get(CV);
4543 SDOperand CPIdx = DAG.getConstantPool(C, getPointerTy(), 4);
4544 SDOperand Mask = DAG.getLoad(VT, DAG.getEntryNode(), CPIdx,
4545 PseudoSourceValue::getConstantPool(), 0,
4547 return DAG.getNode(X86ISD::FAND, VT, Op.getOperand(0), Mask);
4550 SDOperand X86TargetLowering::LowerFNEG(SDOperand Op, SelectionDAG &DAG) {
4551 MVT VT = Op.getValueType();
4553 unsigned EltNum = 1;
4554 if (VT.isVector()) {
4555 EltVT = VT.getVectorElementType();
4556 EltNum = VT.getVectorNumElements();
4558 std::vector<Constant*> CV;
4559 if (EltVT == MVT::f64) {
4560 Constant *C = ConstantFP::get(APFloat(APInt(64, 1ULL << 63)));
4564 Constant *C = ConstantFP::get(APFloat(APInt(32, 1U << 31)));
4570 Constant *C = ConstantVector::get(CV);
4571 SDOperand CPIdx = DAG.getConstantPool(C, getPointerTy(), 4);
4572 SDOperand Mask = DAG.getLoad(VT, DAG.getEntryNode(), CPIdx,
4573 PseudoSourceValue::getConstantPool(), 0,
4575 if (VT.isVector()) {
4576 return DAG.getNode(ISD::BIT_CONVERT, VT,
4577 DAG.getNode(ISD::XOR, MVT::v2i64,
4578 DAG.getNode(ISD::BIT_CONVERT, MVT::v2i64, Op.getOperand(0)),
4579 DAG.getNode(ISD::BIT_CONVERT, MVT::v2i64, Mask)));
4581 return DAG.getNode(X86ISD::FXOR, VT, Op.getOperand(0), Mask);
4585 SDOperand X86TargetLowering::LowerFCOPYSIGN(SDOperand Op, SelectionDAG &DAG) {
4586 SDOperand Op0 = Op.getOperand(0);
4587 SDOperand Op1 = Op.getOperand(1);
4588 MVT VT = Op.getValueType();
4589 MVT SrcVT = Op1.getValueType();
4591 // If second operand is smaller, extend it first.
4592 if (SrcVT.bitsLT(VT)) {
4593 Op1 = DAG.getNode(ISD::FP_EXTEND, VT, Op1);
4596 // And if it is bigger, shrink it first.
4597 if (SrcVT.bitsGT(VT)) {
4598 Op1 = DAG.getNode(ISD::FP_ROUND, VT, Op1, DAG.getIntPtrConstant(1));
4602 // At this point the operands and the result should have the same
4603 // type, and that won't be f80 since that is not custom lowered.
4605 // First get the sign bit of second operand.
4606 std::vector<Constant*> CV;
4607 if (SrcVT == MVT::f64) {
4608 CV.push_back(ConstantFP::get(APFloat(APInt(64, 1ULL << 63))));
4609 CV.push_back(ConstantFP::get(APFloat(APInt(64, 0))));
4611 CV.push_back(ConstantFP::get(APFloat(APInt(32, 1U << 31))));
4612 CV.push_back(ConstantFP::get(APFloat(APInt(32, 0))));
4613 CV.push_back(ConstantFP::get(APFloat(APInt(32, 0))));
4614 CV.push_back(ConstantFP::get(APFloat(APInt(32, 0))));
4616 Constant *C = ConstantVector::get(CV);
4617 SDOperand CPIdx = DAG.getConstantPool(C, getPointerTy(), 4);
4618 SDOperand Mask1 = DAG.getLoad(SrcVT, DAG.getEntryNode(), CPIdx,
4619 PseudoSourceValue::getConstantPool(), 0,
4621 SDOperand SignBit = DAG.getNode(X86ISD::FAND, SrcVT, Op1, Mask1);
4623 // Shift sign bit right or left if the two operands have different types.
4624 if (SrcVT.bitsGT(VT)) {
4625 // Op0 is MVT::f32, Op1 is MVT::f64.
4626 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, MVT::v2f64, SignBit);
4627 SignBit = DAG.getNode(X86ISD::FSRL, MVT::v2f64, SignBit,
4628 DAG.getConstant(32, MVT::i32));
4629 SignBit = DAG.getNode(ISD::BIT_CONVERT, MVT::v4f32, SignBit);
4630 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::f32, SignBit,
4631 DAG.getIntPtrConstant(0));
4634 // Clear first operand sign bit.
4636 if (VT == MVT::f64) {
4637 CV.push_back(ConstantFP::get(APFloat(APInt(64, ~(1ULL << 63)))));
4638 CV.push_back(ConstantFP::get(APFloat(APInt(64, 0))));
4640 CV.push_back(ConstantFP::get(APFloat(APInt(32, ~(1U << 31)))));
4641 CV.push_back(ConstantFP::get(APFloat(APInt(32, 0))));
4642 CV.push_back(ConstantFP::get(APFloat(APInt(32, 0))));
4643 CV.push_back(ConstantFP::get(APFloat(APInt(32, 0))));
4645 C = ConstantVector::get(CV);
4646 CPIdx = DAG.getConstantPool(C, getPointerTy(), 4);
4647 SDOperand Mask2 = DAG.getLoad(VT, DAG.getEntryNode(), CPIdx,
4648 PseudoSourceValue::getConstantPool(), 0,
4650 SDOperand Val = DAG.getNode(X86ISD::FAND, VT, Op0, Mask2);
4652 // Or the value with the sign bit.
4653 return DAG.getNode(X86ISD::FOR, VT, Val, SignBit);
4656 SDOperand X86TargetLowering::LowerSETCC(SDOperand Op, SelectionDAG &DAG) {
4657 assert(Op.getValueType() == MVT::i8 && "SetCC type must be 8-bit integer");
4659 SDOperand Op0 = Op.getOperand(0);
4660 SDOperand Op1 = Op.getOperand(1);
4661 SDOperand CC = Op.getOperand(2);
4662 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
4663 bool isFP = Op.getOperand(1).getValueType().isFloatingPoint();
4666 if (translateX86CC(cast<CondCodeSDNode>(CC)->get(), isFP, X86CC,
4668 Cond = DAG.getNode(X86ISD::CMP, MVT::i32, Op0, Op1);
4669 return DAG.getNode(X86ISD::SETCC, MVT::i8,
4670 DAG.getConstant(X86CC, MVT::i8), Cond);
4673 assert(isFP && "Illegal integer SetCC!");
4675 Cond = DAG.getNode(X86ISD::CMP, MVT::i32, Op0, Op1);
4676 switch (SetCCOpcode) {
4677 default: assert(false && "Illegal floating point SetCC!");
4678 case ISD::SETOEQ: { // !PF & ZF
4679 SDOperand Tmp1 = DAG.getNode(X86ISD::SETCC, MVT::i8,
4680 DAG.getConstant(X86::COND_NP, MVT::i8), Cond);
4681 SDOperand Tmp2 = DAG.getNode(X86ISD::SETCC, MVT::i8,
4682 DAG.getConstant(X86::COND_E, MVT::i8), Cond);
4683 return DAG.getNode(ISD::AND, MVT::i8, Tmp1, Tmp2);
4685 case ISD::SETUNE: { // PF | !ZF
4686 SDOperand Tmp1 = DAG.getNode(X86ISD::SETCC, MVT::i8,
4687 DAG.getConstant(X86::COND_P, MVT::i8), Cond);
4688 SDOperand Tmp2 = DAG.getNode(X86ISD::SETCC, MVT::i8,
4689 DAG.getConstant(X86::COND_NE, MVT::i8), Cond);
4690 return DAG.getNode(ISD::OR, MVT::i8, Tmp1, Tmp2);
4696 SDOperand X86TargetLowering::LowerSELECT(SDOperand Op, SelectionDAG &DAG) {
4697 bool addTest = true;
4698 SDOperand Cond = Op.getOperand(0);
4701 if (Cond.getOpcode() == ISD::SETCC)
4702 Cond = LowerSETCC(Cond, DAG);
4704 // If condition flag is set by a X86ISD::CMP, then use it as the condition
4705 // setting operand in place of the X86ISD::SETCC.
4706 if (Cond.getOpcode() == X86ISD::SETCC) {
4707 CC = Cond.getOperand(0);
4709 SDOperand Cmp = Cond.getOperand(1);
4710 unsigned Opc = Cmp.getOpcode();
4711 MVT VT = Op.getValueType();
4713 bool IllegalFPCMov = false;
4714 if (VT.isFloatingPoint() && !VT.isVector() &&
4715 !isScalarFPTypeInSSEReg(VT)) // FPStack?
4716 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSignExtended());
4718 if ((Opc == X86ISD::CMP ||
4719 Opc == X86ISD::COMI ||
4720 Opc == X86ISD::UCOMI) && !IllegalFPCMov) {
4727 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
4728 Cond= DAG.getNode(X86ISD::CMP, MVT::i32, Cond, DAG.getConstant(0, MVT::i8));
4731 const MVT *VTs = DAG.getNodeValueTypes(Op.getValueType(),
4733 SmallVector<SDOperand, 4> Ops;
4734 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
4735 // condition is true.
4736 Ops.push_back(Op.getOperand(2));
4737 Ops.push_back(Op.getOperand(1));
4739 Ops.push_back(Cond);
4740 return DAG.getNode(X86ISD::CMOV, VTs, 2, &Ops[0], Ops.size());
4743 SDOperand X86TargetLowering::LowerBRCOND(SDOperand Op, SelectionDAG &DAG) {
4744 bool addTest = true;
4745 SDOperand Chain = Op.getOperand(0);
4746 SDOperand Cond = Op.getOperand(1);
4747 SDOperand Dest = Op.getOperand(2);
4750 if (Cond.getOpcode() == ISD::SETCC)
4751 Cond = LowerSETCC(Cond, DAG);
4753 // If condition flag is set by a X86ISD::CMP, then use it as the condition
4754 // setting operand in place of the X86ISD::SETCC.
4755 if (Cond.getOpcode() == X86ISD::SETCC) {
4756 CC = Cond.getOperand(0);
4758 SDOperand Cmp = Cond.getOperand(1);
4759 unsigned Opc = Cmp.getOpcode();
4760 if (Opc == X86ISD::CMP ||
4761 Opc == X86ISD::COMI ||
4762 Opc == X86ISD::UCOMI) {
4769 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
4770 Cond= DAG.getNode(X86ISD::CMP, MVT::i32, Cond, DAG.getConstant(0, MVT::i8));
4772 return DAG.getNode(X86ISD::BRCOND, Op.getValueType(),
4773 Chain, Op.getOperand(2), CC, Cond);
4777 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
4778 // Calls to _alloca is needed to probe the stack when allocating more than 4k
4779 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
4780 // that the guard pages used by the OS virtual memory manager are allocated in
4781 // correct sequence.
4783 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDOperand Op,
4784 SelectionDAG &DAG) {
4785 assert(Subtarget->isTargetCygMing() &&
4786 "This should be used only on Cygwin/Mingw targets");
4789 SDOperand Chain = Op.getOperand(0);
4790 SDOperand Size = Op.getOperand(1);
4791 // FIXME: Ensure alignment here
4795 MVT IntPtr = getPointerTy();
4796 MVT SPTy = Subtarget->is64Bit() ? MVT::i64 : MVT::i32;
4798 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0));
4800 Chain = DAG.getCopyToReg(Chain, X86::EAX, Size, Flag);
4801 Flag = Chain.getValue(1);
4803 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
4804 SDOperand Ops[] = { Chain,
4805 DAG.getTargetExternalSymbol("_alloca", IntPtr),
4806 DAG.getRegister(X86::EAX, IntPtr),
4807 DAG.getRegister(X86StackPtr, SPTy),
4809 Chain = DAG.getNode(X86ISD::CALL, NodeTys, Ops, 5);
4810 Flag = Chain.getValue(1);
4812 Chain = DAG.getCALLSEQ_END(Chain,
4813 DAG.getIntPtrConstant(0),
4814 DAG.getIntPtrConstant(0),
4817 Chain = DAG.getCopyFromReg(Chain, X86StackPtr, SPTy).getValue(1);
4819 SDOperand Ops1[2] = { Chain.getValue(0), Chain };
4820 return DAG.getMergeValues(Ops1, 2);
4824 X86TargetLowering::EmitTargetCodeForMemset(SelectionDAG &DAG,
4826 SDOperand Dst, SDOperand Src,
4827 SDOperand Size, unsigned Align,
4828 const Value *DstSV, uint64_t DstSVOff) {
4829 ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size);
4831 /// If not DWORD aligned or size is more than the threshold, call the library.
4832 /// The libc version is likely to be faster for these cases. It can use the
4833 /// address value and run time information about the CPU.
4834 if ((Align & 3) == 0 ||
4836 ConstantSize->getValue() > getSubtarget()->getMaxInlineSizeThreshold()) {
4837 SDOperand InFlag(0, 0);
4839 // Check to see if there is a specialized entry-point for memory zeroing.
4840 ConstantSDNode *V = dyn_cast<ConstantSDNode>(Src);
4841 if (const char *bzeroEntry =
4842 V && V->isNullValue() ? Subtarget->getBZeroEntry() : 0) {
4843 MVT IntPtr = getPointerTy();
4844 const Type *IntPtrTy = getTargetData()->getIntPtrType();
4845 TargetLowering::ArgListTy Args;
4846 TargetLowering::ArgListEntry Entry;
4848 Entry.Ty = IntPtrTy;
4849 Args.push_back(Entry);
4851 Args.push_back(Entry);
4852 std::pair<SDOperand,SDOperand> CallResult =
4853 LowerCallTo(Chain, Type::VoidTy, false, false, false, CallingConv::C,
4854 false, DAG.getExternalSymbol(bzeroEntry, IntPtr),
4856 return CallResult.second;
4859 // Otherwise have the target-independent code call memset.
4863 uint64_t SizeVal = ConstantSize->getValue();
4864 SDOperand InFlag(0, 0);
4867 ConstantSDNode *ValC = dyn_cast<ConstantSDNode>(Src);
4868 unsigned BytesLeft = 0;
4869 bool TwoRepStos = false;
4872 uint64_t Val = ValC->getValue() & 255;
4874 // If the value is a constant, then we can potentially use larger sets.
4875 switch (Align & 3) {
4876 case 2: // WORD aligned
4879 Val = (Val << 8) | Val;
4881 case 0: // DWORD aligned
4884 Val = (Val << 8) | Val;
4885 Val = (Val << 16) | Val;
4886 if (Subtarget->is64Bit() && ((Align & 0x7) == 0)) { // QWORD aligned
4889 Val = (Val << 32) | Val;
4892 default: // Byte aligned
4895 Count = DAG.getIntPtrConstant(SizeVal);
4899 if (AVT.bitsGT(MVT::i8)) {
4900 unsigned UBytes = AVT.getSizeInBits() / 8;
4901 Count = DAG.getIntPtrConstant(SizeVal / UBytes);
4902 BytesLeft = SizeVal % UBytes;
4905 Chain = DAG.getCopyToReg(Chain, ValReg, DAG.getConstant(Val, AVT),
4907 InFlag = Chain.getValue(1);
4910 Count = DAG.getIntPtrConstant(SizeVal);
4911 Chain = DAG.getCopyToReg(Chain, X86::AL, Src, InFlag);
4912 InFlag = Chain.getValue(1);
4915 Chain = DAG.getCopyToReg(Chain, Subtarget->is64Bit() ? X86::RCX : X86::ECX,
4917 InFlag = Chain.getValue(1);
4918 Chain = DAG.getCopyToReg(Chain, Subtarget->is64Bit() ? X86::RDI : X86::EDI,
4920 InFlag = Chain.getValue(1);
4922 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
4923 SmallVector<SDOperand, 8> Ops;
4924 Ops.push_back(Chain);
4925 Ops.push_back(DAG.getValueType(AVT));
4926 Ops.push_back(InFlag);
4927 Chain = DAG.getNode(X86ISD::REP_STOS, Tys, &Ops[0], Ops.size());
4930 InFlag = Chain.getValue(1);
4932 MVT CVT = Count.getValueType();
4933 SDOperand Left = DAG.getNode(ISD::AND, CVT, Count,
4934 DAG.getConstant((AVT == MVT::i64) ? 7 : 3, CVT));
4935 Chain = DAG.getCopyToReg(Chain, (CVT == MVT::i64) ? X86::RCX : X86::ECX,
4937 InFlag = Chain.getValue(1);
4938 Tys = DAG.getVTList(MVT::Other, MVT::Flag);
4940 Ops.push_back(Chain);
4941 Ops.push_back(DAG.getValueType(MVT::i8));
4942 Ops.push_back(InFlag);
4943 Chain = DAG.getNode(X86ISD::REP_STOS, Tys, &Ops[0], Ops.size());
4944 } else if (BytesLeft) {
4945 // Handle the last 1 - 7 bytes.
4946 unsigned Offset = SizeVal - BytesLeft;
4947 MVT AddrVT = Dst.getValueType();
4948 MVT SizeVT = Size.getValueType();
4950 Chain = DAG.getMemset(Chain,
4951 DAG.getNode(ISD::ADD, AddrVT, Dst,
4952 DAG.getConstant(Offset, AddrVT)),
4954 DAG.getConstant(BytesLeft, SizeVT),
4955 Align, DstSV, DstSVOff + Offset);
4958 // TODO: Use a Tokenfactor, as in memcpy, instead of a single chain.
4963 X86TargetLowering::EmitTargetCodeForMemcpy(SelectionDAG &DAG,
4965 SDOperand Dst, SDOperand Src,
4966 SDOperand Size, unsigned Align,
4968 const Value *DstSV, uint64_t DstSVOff,
4969 const Value *SrcSV, uint64_t SrcSVOff){
4971 // This requires the copy size to be a constant, preferrably
4972 // within a subtarget-specific limit.
4973 ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size);
4976 uint64_t SizeVal = ConstantSize->getValue();
4977 if (!AlwaysInline && SizeVal > getSubtarget()->getMaxInlineSizeThreshold())
4981 unsigned BytesLeft = 0;
4982 if (Align >= 8 && Subtarget->is64Bit())
4984 else if (Align >= 4)
4986 else if (Align >= 2)
4991 unsigned UBytes = AVT.getSizeInBits() / 8;
4992 unsigned CountVal = SizeVal / UBytes;
4993 SDOperand Count = DAG.getIntPtrConstant(CountVal);
4994 BytesLeft = SizeVal % UBytes;
4996 SDOperand InFlag(0, 0);
4997 Chain = DAG.getCopyToReg(Chain, Subtarget->is64Bit() ? X86::RCX : X86::ECX,
4999 InFlag = Chain.getValue(1);
5000 Chain = DAG.getCopyToReg(Chain, Subtarget->is64Bit() ? X86::RDI : X86::EDI,
5002 InFlag = Chain.getValue(1);
5003 Chain = DAG.getCopyToReg(Chain, Subtarget->is64Bit() ? X86::RSI : X86::ESI,
5005 InFlag = Chain.getValue(1);
5007 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
5008 SmallVector<SDOperand, 8> Ops;
5009 Ops.push_back(Chain);
5010 Ops.push_back(DAG.getValueType(AVT));
5011 Ops.push_back(InFlag);
5012 SDOperand RepMovs = DAG.getNode(X86ISD::REP_MOVS, Tys, &Ops[0], Ops.size());
5014 SmallVector<SDOperand, 4> Results;
5015 Results.push_back(RepMovs);
5017 // Handle the last 1 - 7 bytes.
5018 unsigned Offset = SizeVal - BytesLeft;
5019 MVT DstVT = Dst.getValueType();
5020 MVT SrcVT = Src.getValueType();
5021 MVT SizeVT = Size.getValueType();
5022 Results.push_back(DAG.getMemcpy(Chain,
5023 DAG.getNode(ISD::ADD, DstVT, Dst,
5024 DAG.getConstant(Offset, DstVT)),
5025 DAG.getNode(ISD::ADD, SrcVT, Src,
5026 DAG.getConstant(Offset, SrcVT)),
5027 DAG.getConstant(BytesLeft, SizeVT),
5028 Align, AlwaysInline,
5029 DstSV, DstSVOff + Offset,
5030 SrcSV, SrcSVOff + Offset));
5033 return DAG.getNode(ISD::TokenFactor, MVT::Other, &Results[0], Results.size());
5036 /// Expand the result of: i64,outchain = READCYCLECOUNTER inchain
5037 SDNode *X86TargetLowering::ExpandREADCYCLECOUNTER(SDNode *N, SelectionDAG &DAG){
5038 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
5039 SDOperand TheChain = N->getOperand(0);
5040 SDOperand rd = DAG.getNode(X86ISD::RDTSC_DAG, Tys, &TheChain, 1);
5041 if (Subtarget->is64Bit()) {
5042 SDOperand rax = DAG.getCopyFromReg(rd, X86::RAX, MVT::i64, rd.getValue(1));
5043 SDOperand rdx = DAG.getCopyFromReg(rax.getValue(1), X86::RDX,
5044 MVT::i64, rax.getValue(2));
5045 SDOperand Tmp = DAG.getNode(ISD::SHL, MVT::i64, rdx,
5046 DAG.getConstant(32, MVT::i8));
5048 DAG.getNode(ISD::OR, MVT::i64, rax, Tmp), rdx.getValue(1)
5051 return DAG.getMergeValues(Ops, 2).Val;
5054 SDOperand eax = DAG.getCopyFromReg(rd, X86::EAX, MVT::i32, rd.getValue(1));
5055 SDOperand edx = DAG.getCopyFromReg(eax.getValue(1), X86::EDX,
5056 MVT::i32, eax.getValue(2));
5057 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
5058 SDOperand Ops[] = { eax, edx };
5059 Ops[0] = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Ops, 2);
5061 // Use a MERGE_VALUES to return the value and chain.
5062 Ops[1] = edx.getValue(1);
5063 return DAG.getMergeValues(Ops, 2).Val;
5066 SDOperand X86TargetLowering::LowerVASTART(SDOperand Op, SelectionDAG &DAG) {
5067 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
5069 if (!Subtarget->is64Bit()) {
5070 // vastart just stores the address of the VarArgsFrameIndex slot into the
5071 // memory location argument.
5072 SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, getPointerTy());
5073 return DAG.getStore(Op.getOperand(0), FR,Op.getOperand(1), SV, 0);
5077 // gp_offset (0 - 6 * 8)
5078 // fp_offset (48 - 48 + 8 * 16)
5079 // overflow_arg_area (point to parameters coming in memory).
5081 SmallVector<SDOperand, 8> MemOps;
5082 SDOperand FIN = Op.getOperand(1);
5084 SDOperand Store = DAG.getStore(Op.getOperand(0),
5085 DAG.getConstant(VarArgsGPOffset, MVT::i32),
5087 MemOps.push_back(Store);
5090 FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN, DAG.getIntPtrConstant(4));
5091 Store = DAG.getStore(Op.getOperand(0),
5092 DAG.getConstant(VarArgsFPOffset, MVT::i32),
5094 MemOps.push_back(Store);
5096 // Store ptr to overflow_arg_area
5097 FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN, DAG.getIntPtrConstant(4));
5098 SDOperand OVFIN = DAG.getFrameIndex(VarArgsFrameIndex, getPointerTy());
5099 Store = DAG.getStore(Op.getOperand(0), OVFIN, FIN, SV, 0);
5100 MemOps.push_back(Store);
5102 // Store ptr to reg_save_area.
5103 FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN, DAG.getIntPtrConstant(8));
5104 SDOperand RSFIN = DAG.getFrameIndex(RegSaveFrameIndex, getPointerTy());
5105 Store = DAG.getStore(Op.getOperand(0), RSFIN, FIN, SV, 0);
5106 MemOps.push_back(Store);
5107 return DAG.getNode(ISD::TokenFactor, MVT::Other, &MemOps[0], MemOps.size());
5110 SDOperand X86TargetLowering::LowerVAARG(SDOperand Op, SelectionDAG &DAG) {
5111 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
5112 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_arg!");
5113 SDOperand Chain = Op.getOperand(0);
5114 SDOperand SrcPtr = Op.getOperand(1);
5115 SDOperand SrcSV = Op.getOperand(2);
5117 assert(0 && "VAArgInst is not yet implemented for x86-64!");
5122 SDOperand X86TargetLowering::LowerVACOPY(SDOperand Op, SelectionDAG &DAG) {
5123 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
5124 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
5125 SDOperand Chain = Op.getOperand(0);
5126 SDOperand DstPtr = Op.getOperand(1);
5127 SDOperand SrcPtr = Op.getOperand(2);
5128 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
5129 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
5131 return DAG.getMemcpy(Chain, DstPtr, SrcPtr,
5132 DAG.getIntPtrConstant(24), 8, false,
5133 DstSV, 0, SrcSV, 0);
5137 X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDOperand Op, SelectionDAG &DAG) {
5138 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getValue();
5140 default: return SDOperand(); // Don't custom lower most intrinsics.
5141 // Comparison intrinsics.
5142 case Intrinsic::x86_sse_comieq_ss:
5143 case Intrinsic::x86_sse_comilt_ss:
5144 case Intrinsic::x86_sse_comile_ss:
5145 case Intrinsic::x86_sse_comigt_ss:
5146 case Intrinsic::x86_sse_comige_ss:
5147 case Intrinsic::x86_sse_comineq_ss:
5148 case Intrinsic::x86_sse_ucomieq_ss:
5149 case Intrinsic::x86_sse_ucomilt_ss:
5150 case Intrinsic::x86_sse_ucomile_ss:
5151 case Intrinsic::x86_sse_ucomigt_ss:
5152 case Intrinsic::x86_sse_ucomige_ss:
5153 case Intrinsic::x86_sse_ucomineq_ss:
5154 case Intrinsic::x86_sse2_comieq_sd:
5155 case Intrinsic::x86_sse2_comilt_sd:
5156 case Intrinsic::x86_sse2_comile_sd:
5157 case Intrinsic::x86_sse2_comigt_sd:
5158 case Intrinsic::x86_sse2_comige_sd:
5159 case Intrinsic::x86_sse2_comineq_sd:
5160 case Intrinsic::x86_sse2_ucomieq_sd:
5161 case Intrinsic::x86_sse2_ucomilt_sd:
5162 case Intrinsic::x86_sse2_ucomile_sd:
5163 case Intrinsic::x86_sse2_ucomigt_sd:
5164 case Intrinsic::x86_sse2_ucomige_sd:
5165 case Intrinsic::x86_sse2_ucomineq_sd: {
5167 ISD::CondCode CC = ISD::SETCC_INVALID;
5170 case Intrinsic::x86_sse_comieq_ss:
5171 case Intrinsic::x86_sse2_comieq_sd:
5175 case Intrinsic::x86_sse_comilt_ss:
5176 case Intrinsic::x86_sse2_comilt_sd:
5180 case Intrinsic::x86_sse_comile_ss:
5181 case Intrinsic::x86_sse2_comile_sd:
5185 case Intrinsic::x86_sse_comigt_ss:
5186 case Intrinsic::x86_sse2_comigt_sd:
5190 case Intrinsic::x86_sse_comige_ss:
5191 case Intrinsic::x86_sse2_comige_sd:
5195 case Intrinsic::x86_sse_comineq_ss:
5196 case Intrinsic::x86_sse2_comineq_sd:
5200 case Intrinsic::x86_sse_ucomieq_ss:
5201 case Intrinsic::x86_sse2_ucomieq_sd:
5202 Opc = X86ISD::UCOMI;
5205 case Intrinsic::x86_sse_ucomilt_ss:
5206 case Intrinsic::x86_sse2_ucomilt_sd:
5207 Opc = X86ISD::UCOMI;
5210 case Intrinsic::x86_sse_ucomile_ss:
5211 case Intrinsic::x86_sse2_ucomile_sd:
5212 Opc = X86ISD::UCOMI;
5215 case Intrinsic::x86_sse_ucomigt_ss:
5216 case Intrinsic::x86_sse2_ucomigt_sd:
5217 Opc = X86ISD::UCOMI;
5220 case Intrinsic::x86_sse_ucomige_ss:
5221 case Intrinsic::x86_sse2_ucomige_sd:
5222 Opc = X86ISD::UCOMI;
5225 case Intrinsic::x86_sse_ucomineq_ss:
5226 case Intrinsic::x86_sse2_ucomineq_sd:
5227 Opc = X86ISD::UCOMI;
5233 SDOperand LHS = Op.getOperand(1);
5234 SDOperand RHS = Op.getOperand(2);
5235 translateX86CC(CC, true, X86CC, LHS, RHS, DAG);
5237 SDOperand Cond = DAG.getNode(Opc, MVT::i32, LHS, RHS);
5238 SDOperand SetCC = DAG.getNode(X86ISD::SETCC, MVT::i8,
5239 DAG.getConstant(X86CC, MVT::i8), Cond);
5240 return DAG.getNode(ISD::ANY_EXTEND, MVT::i32, SetCC);
5243 // Fix vector shift instructions where the last operand is a non-immediate
5245 case Intrinsic::x86_sse2_pslli_w:
5246 case Intrinsic::x86_sse2_pslli_d:
5247 case Intrinsic::x86_sse2_pslli_q:
5248 case Intrinsic::x86_sse2_psrli_w:
5249 case Intrinsic::x86_sse2_psrli_d:
5250 case Intrinsic::x86_sse2_psrli_q:
5251 case Intrinsic::x86_sse2_psrai_w:
5252 case Intrinsic::x86_sse2_psrai_d:
5253 case Intrinsic::x86_mmx_pslli_w:
5254 case Intrinsic::x86_mmx_pslli_d:
5255 case Intrinsic::x86_mmx_pslli_q:
5256 case Intrinsic::x86_mmx_psrli_w:
5257 case Intrinsic::x86_mmx_psrli_d:
5258 case Intrinsic::x86_mmx_psrli_q:
5259 case Intrinsic::x86_mmx_psrai_w:
5260 case Intrinsic::x86_mmx_psrai_d: {
5261 SDOperand ShAmt = Op.getOperand(2);
5262 if (isa<ConstantSDNode>(ShAmt))
5265 unsigned NewIntNo = 0;
5266 MVT ShAmtVT = MVT::v4i32;
5268 case Intrinsic::x86_sse2_pslli_w:
5269 NewIntNo = Intrinsic::x86_sse2_psll_w;
5271 case Intrinsic::x86_sse2_pslli_d:
5272 NewIntNo = Intrinsic::x86_sse2_psll_d;
5274 case Intrinsic::x86_sse2_pslli_q:
5275 NewIntNo = Intrinsic::x86_sse2_psll_q;
5277 case Intrinsic::x86_sse2_psrli_w:
5278 NewIntNo = Intrinsic::x86_sse2_psrl_w;
5280 case Intrinsic::x86_sse2_psrli_d:
5281 NewIntNo = Intrinsic::x86_sse2_psrl_d;
5283 case Intrinsic::x86_sse2_psrli_q:
5284 NewIntNo = Intrinsic::x86_sse2_psrl_q;
5286 case Intrinsic::x86_sse2_psrai_w:
5287 NewIntNo = Intrinsic::x86_sse2_psra_w;
5289 case Intrinsic::x86_sse2_psrai_d:
5290 NewIntNo = Intrinsic::x86_sse2_psra_d;
5293 ShAmtVT = MVT::v2i32;
5295 case Intrinsic::x86_mmx_pslli_w:
5296 NewIntNo = Intrinsic::x86_mmx_psll_w;
5298 case Intrinsic::x86_mmx_pslli_d:
5299 NewIntNo = Intrinsic::x86_mmx_psll_d;
5301 case Intrinsic::x86_mmx_pslli_q:
5302 NewIntNo = Intrinsic::x86_mmx_psll_q;
5304 case Intrinsic::x86_mmx_psrli_w:
5305 NewIntNo = Intrinsic::x86_mmx_psrl_w;
5307 case Intrinsic::x86_mmx_psrli_d:
5308 NewIntNo = Intrinsic::x86_mmx_psrl_d;
5310 case Intrinsic::x86_mmx_psrli_q:
5311 NewIntNo = Intrinsic::x86_mmx_psrl_q;
5313 case Intrinsic::x86_mmx_psrai_w:
5314 NewIntNo = Intrinsic::x86_mmx_psra_w;
5316 case Intrinsic::x86_mmx_psrai_d:
5317 NewIntNo = Intrinsic::x86_mmx_psra_d;
5319 default: abort(); // Can't reach here.
5324 MVT VT = Op.getValueType();
5325 ShAmt = DAG.getNode(ISD::BIT_CONVERT, VT,
5326 DAG.getNode(ISD::SCALAR_TO_VECTOR, ShAmtVT, ShAmt));
5327 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, VT,
5328 DAG.getConstant(NewIntNo, MVT::i32),
5329 Op.getOperand(1), ShAmt);
5334 SDOperand X86TargetLowering::LowerRETURNADDR(SDOperand Op, SelectionDAG &DAG) {
5335 // Depths > 0 not supported yet!
5336 if (cast<ConstantSDNode>(Op.getOperand(0))->getValue() > 0)
5339 // Just load the return address
5340 SDOperand RetAddrFI = getReturnAddressFrameIndex(DAG);
5341 return DAG.getLoad(getPointerTy(), DAG.getEntryNode(), RetAddrFI, NULL, 0);
5344 SDOperand X86TargetLowering::LowerFRAMEADDR(SDOperand Op, SelectionDAG &DAG) {
5345 // Depths > 0 not supported yet!
5346 if (cast<ConstantSDNode>(Op.getOperand(0))->getValue() > 0)
5349 SDOperand RetAddrFI = getReturnAddressFrameIndex(DAG);
5350 return DAG.getNode(ISD::SUB, getPointerTy(), RetAddrFI,
5351 DAG.getIntPtrConstant(!Subtarget->is64Bit() ? 4 : 8));
5354 SDOperand X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDOperand Op,
5355 SelectionDAG &DAG) {
5356 // Is not yet supported on x86-64
5357 if (Subtarget->is64Bit())
5360 return DAG.getIntPtrConstant(8);
5363 SDOperand X86TargetLowering::LowerEH_RETURN(SDOperand Op, SelectionDAG &DAG)
5365 assert(!Subtarget->is64Bit() &&
5366 "Lowering of eh_return builtin is not supported yet on x86-64");
5368 MachineFunction &MF = DAG.getMachineFunction();
5369 SDOperand Chain = Op.getOperand(0);
5370 SDOperand Offset = Op.getOperand(1);
5371 SDOperand Handler = Op.getOperand(2);
5373 SDOperand Frame = DAG.getRegister(RegInfo->getFrameRegister(MF),
5376 SDOperand StoreAddr = DAG.getNode(ISD::SUB, getPointerTy(), Frame,
5377 DAG.getIntPtrConstant(-4UL));
5378 StoreAddr = DAG.getNode(ISD::ADD, getPointerTy(), StoreAddr, Offset);
5379 Chain = DAG.getStore(Chain, Handler, StoreAddr, NULL, 0);
5380 Chain = DAG.getCopyToReg(Chain, X86::ECX, StoreAddr);
5381 MF.getRegInfo().addLiveOut(X86::ECX);
5383 return DAG.getNode(X86ISD::EH_RETURN, MVT::Other,
5384 Chain, DAG.getRegister(X86::ECX, getPointerTy()));
5387 SDOperand X86TargetLowering::LowerTRAMPOLINE(SDOperand Op,
5388 SelectionDAG &DAG) {
5389 SDOperand Root = Op.getOperand(0);
5390 SDOperand Trmp = Op.getOperand(1); // trampoline
5391 SDOperand FPtr = Op.getOperand(2); // nested function
5392 SDOperand Nest = Op.getOperand(3); // 'nest' parameter value
5394 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
5396 const X86InstrInfo *TII =
5397 ((X86TargetMachine&)getTargetMachine()).getInstrInfo();
5399 if (Subtarget->is64Bit()) {
5400 SDOperand OutChains[6];
5402 // Large code-model.
5404 const unsigned char JMP64r = TII->getBaseOpcodeFor(X86::JMP64r);
5405 const unsigned char MOV64ri = TII->getBaseOpcodeFor(X86::MOV64ri);
5407 const unsigned char N86R10 = RegInfo->getX86RegNum(X86::R10);
5408 const unsigned char N86R11 = RegInfo->getX86RegNum(X86::R11);
5410 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
5412 // Load the pointer to the nested function into R11.
5413 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
5414 SDOperand Addr = Trmp;
5415 OutChains[0] = DAG.getStore(Root, DAG.getConstant(OpCode, MVT::i16), Addr,
5418 Addr = DAG.getNode(ISD::ADD, MVT::i64, Trmp, DAG.getConstant(2, MVT::i64));
5419 OutChains[1] = DAG.getStore(Root, FPtr, Addr, TrmpAddr, 2, false, 2);
5421 // Load the 'nest' parameter value into R10.
5422 // R10 is specified in X86CallingConv.td
5423 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
5424 Addr = DAG.getNode(ISD::ADD, MVT::i64, Trmp, DAG.getConstant(10, MVT::i64));
5425 OutChains[2] = DAG.getStore(Root, DAG.getConstant(OpCode, MVT::i16), Addr,
5428 Addr = DAG.getNode(ISD::ADD, MVT::i64, Trmp, DAG.getConstant(12, MVT::i64));
5429 OutChains[3] = DAG.getStore(Root, Nest, Addr, TrmpAddr, 12, false, 2);
5431 // Jump to the nested function.
5432 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
5433 Addr = DAG.getNode(ISD::ADD, MVT::i64, Trmp, DAG.getConstant(20, MVT::i64));
5434 OutChains[4] = DAG.getStore(Root, DAG.getConstant(OpCode, MVT::i16), Addr,
5437 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
5438 Addr = DAG.getNode(ISD::ADD, MVT::i64, Trmp, DAG.getConstant(22, MVT::i64));
5439 OutChains[5] = DAG.getStore(Root, DAG.getConstant(ModRM, MVT::i8), Addr,
5443 { Trmp, DAG.getNode(ISD::TokenFactor, MVT::Other, OutChains, 6) };
5444 return DAG.getMergeValues(Ops, 2);
5446 const Function *Func =
5447 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
5448 unsigned CC = Func->getCallingConv();
5453 assert(0 && "Unsupported calling convention");
5454 case CallingConv::C:
5455 case CallingConv::X86_StdCall: {
5456 // Pass 'nest' parameter in ECX.
5457 // Must be kept in sync with X86CallingConv.td
5460 // Check that ECX wasn't needed by an 'inreg' parameter.
5461 const FunctionType *FTy = Func->getFunctionType();
5462 const PAListPtr &Attrs = Func->getParamAttrs();
5464 if (!Attrs.isEmpty() && !Func->isVarArg()) {
5465 unsigned InRegCount = 0;
5468 for (FunctionType::param_iterator I = FTy->param_begin(),
5469 E = FTy->param_end(); I != E; ++I, ++Idx)
5470 if (Attrs.paramHasAttr(Idx, ParamAttr::InReg))
5471 // FIXME: should only count parameters that are lowered to integers.
5472 InRegCount += (getTargetData()->getTypeSizeInBits(*I) + 31) / 32;
5474 if (InRegCount > 2) {
5475 cerr << "Nest register in use - reduce number of inreg parameters!\n";
5481 case CallingConv::X86_FastCall:
5482 // Pass 'nest' parameter in EAX.
5483 // Must be kept in sync with X86CallingConv.td
5488 SDOperand OutChains[4];
5489 SDOperand Addr, Disp;
5491 Addr = DAG.getNode(ISD::ADD, MVT::i32, Trmp, DAG.getConstant(10, MVT::i32));
5492 Disp = DAG.getNode(ISD::SUB, MVT::i32, FPtr, Addr);
5494 const unsigned char MOV32ri = TII->getBaseOpcodeFor(X86::MOV32ri);
5495 const unsigned char N86Reg = RegInfo->getX86RegNum(NestReg);
5496 OutChains[0] = DAG.getStore(Root, DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
5499 Addr = DAG.getNode(ISD::ADD, MVT::i32, Trmp, DAG.getConstant(1, MVT::i32));
5500 OutChains[1] = DAG.getStore(Root, Nest, Addr, TrmpAddr, 1, false, 1);
5502 const unsigned char JMP = TII->getBaseOpcodeFor(X86::JMP);
5503 Addr = DAG.getNode(ISD::ADD, MVT::i32, Trmp, DAG.getConstant(5, MVT::i32));
5504 OutChains[2] = DAG.getStore(Root, DAG.getConstant(JMP, MVT::i8), Addr,
5505 TrmpAddr, 5, false, 1);
5507 Addr = DAG.getNode(ISD::ADD, MVT::i32, Trmp, DAG.getConstant(6, MVT::i32));
5508 OutChains[3] = DAG.getStore(Root, Disp, Addr, TrmpAddr, 6, false, 1);
5511 { Trmp, DAG.getNode(ISD::TokenFactor, MVT::Other, OutChains, 4) };
5512 return DAG.getMergeValues(Ops, 2);
5516 SDOperand X86TargetLowering::LowerFLT_ROUNDS_(SDOperand Op, SelectionDAG &DAG) {
5518 The rounding mode is in bits 11:10 of FPSR, and has the following
5525 FLT_ROUNDS, on the other hand, expects the following:
5532 To perform the conversion, we do:
5533 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
5536 MachineFunction &MF = DAG.getMachineFunction();
5537 const TargetMachine &TM = MF.getTarget();
5538 const TargetFrameInfo &TFI = *TM.getFrameInfo();
5539 unsigned StackAlignment = TFI.getStackAlignment();
5540 MVT VT = Op.getValueType();
5542 // Save FP Control Word to stack slot
5543 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment);
5544 SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
5546 SDOperand Chain = DAG.getNode(X86ISD::FNSTCW16m, MVT::Other,
5547 DAG.getEntryNode(), StackSlot);
5549 // Load FP Control Word from stack slot
5550 SDOperand CWD = DAG.getLoad(MVT::i16, Chain, StackSlot, NULL, 0);
5552 // Transform as necessary
5554 DAG.getNode(ISD::SRL, MVT::i16,
5555 DAG.getNode(ISD::AND, MVT::i16,
5556 CWD, DAG.getConstant(0x800, MVT::i16)),
5557 DAG.getConstant(11, MVT::i8));
5559 DAG.getNode(ISD::SRL, MVT::i16,
5560 DAG.getNode(ISD::AND, MVT::i16,
5561 CWD, DAG.getConstant(0x400, MVT::i16)),
5562 DAG.getConstant(9, MVT::i8));
5565 DAG.getNode(ISD::AND, MVT::i16,
5566 DAG.getNode(ISD::ADD, MVT::i16,
5567 DAG.getNode(ISD::OR, MVT::i16, CWD1, CWD2),
5568 DAG.getConstant(1, MVT::i16)),
5569 DAG.getConstant(3, MVT::i16));
5572 return DAG.getNode((VT.getSizeInBits() < 16 ?
5573 ISD::TRUNCATE : ISD::ZERO_EXTEND), VT, RetVal);
5576 SDOperand X86TargetLowering::LowerCTLZ(SDOperand Op, SelectionDAG &DAG) {
5577 MVT VT = Op.getValueType();
5579 unsigned NumBits = VT.getSizeInBits();
5581 Op = Op.getOperand(0);
5582 if (VT == MVT::i8) {
5583 // Zero extend to i32 since there is not an i8 bsr.
5585 Op = DAG.getNode(ISD::ZERO_EXTEND, OpVT, Op);
5588 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
5589 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
5590 Op = DAG.getNode(X86ISD::BSR, VTs, Op);
5592 // If src is zero (i.e. bsr sets ZF), returns NumBits.
5593 SmallVector<SDOperand, 4> Ops;
5595 Ops.push_back(DAG.getConstant(NumBits+NumBits-1, OpVT));
5596 Ops.push_back(DAG.getConstant(X86::COND_E, MVT::i8));
5597 Ops.push_back(Op.getValue(1));
5598 Op = DAG.getNode(X86ISD::CMOV, OpVT, &Ops[0], 4);
5600 // Finally xor with NumBits-1.
5601 Op = DAG.getNode(ISD::XOR, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
5604 Op = DAG.getNode(ISD::TRUNCATE, MVT::i8, Op);
5608 SDOperand X86TargetLowering::LowerCTTZ(SDOperand Op, SelectionDAG &DAG) {
5609 MVT VT = Op.getValueType();
5611 unsigned NumBits = VT.getSizeInBits();
5613 Op = Op.getOperand(0);
5614 if (VT == MVT::i8) {
5616 Op = DAG.getNode(ISD::ZERO_EXTEND, OpVT, Op);
5619 // Issue a bsf (scan bits forward) which also sets EFLAGS.
5620 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
5621 Op = DAG.getNode(X86ISD::BSF, VTs, Op);
5623 // If src is zero (i.e. bsf sets ZF), returns NumBits.
5624 SmallVector<SDOperand, 4> Ops;
5626 Ops.push_back(DAG.getConstant(NumBits, OpVT));
5627 Ops.push_back(DAG.getConstant(X86::COND_E, MVT::i8));
5628 Ops.push_back(Op.getValue(1));
5629 Op = DAG.getNode(X86ISD::CMOV, OpVT, &Ops[0], 4);
5632 Op = DAG.getNode(ISD::TRUNCATE, MVT::i8, Op);
5636 SDOperand X86TargetLowering::LowerCMP_SWAP(SDOperand Op, SelectionDAG &DAG) {
5637 MVT T = Op.getValueType();
5640 switch(T.getSimpleVT()) {
5642 assert(false && "Invalid value type!");
5643 case MVT::i8: Reg = X86::AL; size = 1; break;
5644 case MVT::i16: Reg = X86::AX; size = 2; break;
5645 case MVT::i32: Reg = X86::EAX; size = 4; break;
5647 if (Subtarget->is64Bit()) {
5648 Reg = X86::RAX; size = 8;
5649 } else //Should go away when LowerType stuff lands
5650 return SDOperand(ExpandATOMIC_CMP_SWAP(Op.Val, DAG), 0);
5653 SDOperand cpIn = DAG.getCopyToReg(Op.getOperand(0), Reg,
5654 Op.getOperand(3), SDOperand());
5655 SDOperand Ops[] = { cpIn.getValue(0),
5658 DAG.getTargetConstant(size, MVT::i8),
5660 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
5661 SDOperand Result = DAG.getNode(X86ISD::LCMPXCHG_DAG, Tys, Ops, 5);
5663 DAG.getCopyFromReg(Result.getValue(0), Reg, T, Result.getValue(1));
5667 SDNode* X86TargetLowering::ExpandATOMIC_CMP_SWAP(SDNode* Op, SelectionDAG &DAG) {
5668 MVT T = Op->getValueType(0);
5669 assert (T == MVT::i64 && "Only know how to expand i64 Cmp and Swap");
5670 SDOperand cpInL, cpInH;
5671 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op->getOperand(3),
5672 DAG.getConstant(0, MVT::i32));
5673 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op->getOperand(3),
5674 DAG.getConstant(1, MVT::i32));
5675 cpInL = DAG.getCopyToReg(Op->getOperand(0), X86::EAX,
5676 cpInL, SDOperand());
5677 cpInH = DAG.getCopyToReg(cpInL.getValue(0), X86::EDX,
5678 cpInH, cpInL.getValue(1));
5679 SDOperand swapInL, swapInH;
5680 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op->getOperand(2),
5681 DAG.getConstant(0, MVT::i32));
5682 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op->getOperand(2),
5683 DAG.getConstant(1, MVT::i32));
5684 swapInL = DAG.getCopyToReg(cpInH.getValue(0), X86::EBX,
5685 swapInL, cpInH.getValue(1));
5686 swapInH = DAG.getCopyToReg(swapInL.getValue(0), X86::ECX,
5687 swapInH, swapInL.getValue(1));
5688 SDOperand Ops[] = { swapInH.getValue(0),
5690 swapInH.getValue(1)};
5691 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
5692 SDOperand Result = DAG.getNode(X86ISD::LCMPXCHG8_DAG, Tys, Ops, 3);
5693 SDOperand cpOutL = DAG.getCopyFromReg(Result.getValue(0), X86::EAX, MVT::i32,
5694 Result.getValue(1));
5695 SDOperand cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), X86::EDX, MVT::i32,
5696 cpOutL.getValue(2));
5697 SDOperand OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
5698 SDOperand ResultVal = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, OpsF, 2);
5699 SDOperand Vals[2] = { ResultVal, cpOutH.getValue(1) };
5700 return DAG.getMergeValues(Vals, 2).Val;
5703 SDNode* X86TargetLowering::ExpandATOMIC_LOAD_SUB(SDNode* Op, SelectionDAG &DAG) {
5704 MVT T = Op->getValueType(0);
5705 assert (T == MVT::i32 && "Only know how to expand i32 Atomic Load Sub");
5706 SDOperand negOp = DAG.getNode(ISD::SUB, T,
5707 DAG.getConstant(0, T), Op->getOperand(2));
5708 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, Op->getOperand(0),
5709 Op->getOperand(1), negOp,
5710 cast<AtomicSDNode>(Op)->getSrcValue(),
5711 cast<AtomicSDNode>(Op)->getAlignment()).Val;
5714 /// LowerOperation - Provide custom lowering hooks for some operations.
5716 SDOperand X86TargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
5717 switch (Op.getOpcode()) {
5718 default: assert(0 && "Should not custom lower this!");
5719 case ISD::ATOMIC_CMP_SWAP: return LowerCMP_SWAP(Op,DAG);
5720 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
5721 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
5722 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
5723 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
5724 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
5725 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
5726 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
5727 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
5728 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
5729 case ISD::SHL_PARTS:
5730 case ISD::SRA_PARTS:
5731 case ISD::SRL_PARTS: return LowerShift(Op, DAG);
5732 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
5733 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
5734 case ISD::FABS: return LowerFABS(Op, DAG);
5735 case ISD::FNEG: return LowerFNEG(Op, DAG);
5736 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
5737 case ISD::SETCC: return LowerSETCC(Op, DAG);
5738 case ISD::SELECT: return LowerSELECT(Op, DAG);
5739 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
5740 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
5741 case ISD::CALL: return LowerCALL(Op, DAG);
5742 case ISD::RET: return LowerRET(Op, DAG);
5743 case ISD::FORMAL_ARGUMENTS: return LowerFORMAL_ARGUMENTS(Op, DAG);
5744 case ISD::VASTART: return LowerVASTART(Op, DAG);
5745 case ISD::VAARG: return LowerVAARG(Op, DAG);
5746 case ISD::VACOPY: return LowerVACOPY(Op, DAG);
5747 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
5748 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
5749 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
5750 case ISD::FRAME_TO_ARGS_OFFSET:
5751 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
5752 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
5753 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
5754 case ISD::TRAMPOLINE: return LowerTRAMPOLINE(Op, DAG);
5755 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
5756 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
5757 case ISD::CTTZ: return LowerCTTZ(Op, DAG);
5759 // FIXME: REMOVE THIS WHEN LegalizeDAGTypes lands.
5760 case ISD::READCYCLECOUNTER:
5761 return SDOperand(ExpandREADCYCLECOUNTER(Op.Val, DAG), 0);
5765 /// ReplaceNodeResults - Replace a node with an illegal result type
5766 /// with a new node built out of custom code.
5767 SDNode *X86TargetLowering::ReplaceNodeResults(SDNode *N, SelectionDAG &DAG) {
5768 switch (N->getOpcode()) {
5769 default: assert(0 && "Should not custom lower this!");
5770 case ISD::FP_TO_SINT: return ExpandFP_TO_SINT(N, DAG);
5771 case ISD::READCYCLECOUNTER: return ExpandREADCYCLECOUNTER(N, DAG);
5772 case ISD::ATOMIC_CMP_SWAP: return ExpandATOMIC_CMP_SWAP(N, DAG);
5773 case ISD::ATOMIC_LOAD_SUB: return ExpandATOMIC_LOAD_SUB(N,DAG);
5777 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
5779 default: return NULL;
5780 case X86ISD::BSF: return "X86ISD::BSF";
5781 case X86ISD::BSR: return "X86ISD::BSR";
5782 case X86ISD::SHLD: return "X86ISD::SHLD";
5783 case X86ISD::SHRD: return "X86ISD::SHRD";
5784 case X86ISD::FAND: return "X86ISD::FAND";
5785 case X86ISD::FOR: return "X86ISD::FOR";
5786 case X86ISD::FXOR: return "X86ISD::FXOR";
5787 case X86ISD::FSRL: return "X86ISD::FSRL";
5788 case X86ISD::FILD: return "X86ISD::FILD";
5789 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
5790 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
5791 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
5792 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
5793 case X86ISD::FLD: return "X86ISD::FLD";
5794 case X86ISD::FST: return "X86ISD::FST";
5795 case X86ISD::CALL: return "X86ISD::CALL";
5796 case X86ISD::TAILCALL: return "X86ISD::TAILCALL";
5797 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
5798 case X86ISD::CMP: return "X86ISD::CMP";
5799 case X86ISD::COMI: return "X86ISD::COMI";
5800 case X86ISD::UCOMI: return "X86ISD::UCOMI";
5801 case X86ISD::SETCC: return "X86ISD::SETCC";
5802 case X86ISD::CMOV: return "X86ISD::CMOV";
5803 case X86ISD::BRCOND: return "X86ISD::BRCOND";
5804 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
5805 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
5806 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
5807 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
5808 case X86ISD::Wrapper: return "X86ISD::Wrapper";
5809 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
5810 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
5811 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
5812 case X86ISD::PINSRB: return "X86ISD::PINSRB";
5813 case X86ISD::PINSRW: return "X86ISD::PINSRW";
5814 case X86ISD::FMAX: return "X86ISD::FMAX";
5815 case X86ISD::FMIN: return "X86ISD::FMIN";
5816 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
5817 case X86ISD::FRCP: return "X86ISD::FRCP";
5818 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
5819 case X86ISD::THREAD_POINTER: return "X86ISD::THREAD_POINTER";
5820 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
5821 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
5822 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
5823 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
5824 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
5825 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
5826 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
5827 case X86ISD::VSHL: return "X86ISD::VSHL";
5828 case X86ISD::VSRL: return "X86ISD::VSRL";
5832 // isLegalAddressingMode - Return true if the addressing mode represented
5833 // by AM is legal for this target, for a load/store of the specified type.
5834 bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
5835 const Type *Ty) const {
5836 // X86 supports extremely general addressing modes.
5838 // X86 allows a sign-extended 32-bit immediate field as a displacement.
5839 if (AM.BaseOffs <= -(1LL << 32) || AM.BaseOffs >= (1LL << 32)-1)
5843 // We can only fold this if we don't need an extra load.
5844 if (Subtarget->GVRequiresExtraLoad(AM.BaseGV, getTargetMachine(), false))
5847 // X86-64 only supports addr of globals in small code model.
5848 if (Subtarget->is64Bit()) {
5849 if (getTargetMachine().getCodeModel() != CodeModel::Small)
5851 // If lower 4G is not available, then we must use rip-relative addressing.
5852 if (AM.BaseOffs || AM.Scale > 1)
5863 // These scales always work.
5868 // These scales are formed with basereg+scalereg. Only accept if there is
5873 default: // Other stuff never works.
5881 bool X86TargetLowering::isTruncateFree(const Type *Ty1, const Type *Ty2) const {
5882 if (!Ty1->isInteger() || !Ty2->isInteger())
5884 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
5885 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
5886 if (NumBits1 <= NumBits2)
5888 return Subtarget->is64Bit() || NumBits1 < 64;
5891 bool X86TargetLowering::isTruncateFree(MVT VT1, MVT VT2) const {
5892 if (!VT1.isInteger() || !VT2.isInteger())
5894 unsigned NumBits1 = VT1.getSizeInBits();
5895 unsigned NumBits2 = VT2.getSizeInBits();
5896 if (NumBits1 <= NumBits2)
5898 return Subtarget->is64Bit() || NumBits1 < 64;
5901 /// isShuffleMaskLegal - Targets can use this to indicate that they only
5902 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
5903 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
5904 /// are assumed to be legal.
5906 X86TargetLowering::isShuffleMaskLegal(SDOperand Mask, MVT VT) const {
5907 // Only do shuffles on 128-bit vector types for now.
5908 if (VT.getSizeInBits() == 64) return false;
5909 return (Mask.Val->getNumOperands() <= 4 ||
5910 isIdentityMask(Mask.Val) ||
5911 isIdentityMask(Mask.Val, true) ||
5912 isSplatMask(Mask.Val) ||
5913 isPSHUFHW_PSHUFLWMask(Mask.Val) ||
5914 X86::isUNPCKLMask(Mask.Val) ||
5915 X86::isUNPCKHMask(Mask.Val) ||
5916 X86::isUNPCKL_v_undef_Mask(Mask.Val) ||
5917 X86::isUNPCKH_v_undef_Mask(Mask.Val));
5921 X86TargetLowering::isVectorClearMaskLegal(const std::vector<SDOperand> &BVOps,
5922 MVT EVT, SelectionDAG &DAG) const {
5923 unsigned NumElts = BVOps.size();
5924 // Only do shuffles on 128-bit vector types for now.
5925 if (EVT.getSizeInBits() * NumElts == 64) return false;
5926 if (NumElts == 2) return true;
5928 return (isMOVLMask(&BVOps[0], 4) ||
5929 isCommutedMOVL(&BVOps[0], 4, true) ||
5930 isSHUFPMask(&BVOps[0], 4) ||
5931 isCommutedSHUFP(&BVOps[0], 4));
5936 //===----------------------------------------------------------------------===//
5937 // X86 Scheduler Hooks
5938 //===----------------------------------------------------------------------===//
5940 // private utility function
5942 X86TargetLowering::EmitAtomicBitwiseWithCustomInserter(MachineInstr *bInstr,
5943 MachineBasicBlock *MBB,
5947 // For the atomic bitwise operator, we generate
5950 // ld t1 = [bitinstr.addr]
5951 // op t2 = t1, [bitinstr.val]
5953 // lcs dest = [bitinstr.addr], t2 [EAX is implicit]
5955 // fallthrough -->nextMBB
5956 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
5957 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
5958 MachineFunction::iterator MBBIter = MBB;
5961 /// First build the CFG
5962 MachineFunction *F = MBB->getParent();
5963 MachineBasicBlock *thisMBB = MBB;
5964 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
5965 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
5966 F->insert(MBBIter, newMBB);
5967 F->insert(MBBIter, nextMBB);
5969 // Move all successors to thisMBB to nextMBB
5970 nextMBB->transferSuccessors(thisMBB);
5972 // Update thisMBB to fall through to newMBB
5973 thisMBB->addSuccessor(newMBB);
5975 // newMBB jumps to itself and fall through to nextMBB
5976 newMBB->addSuccessor(nextMBB);
5977 newMBB->addSuccessor(newMBB);
5979 // Insert instructions into newMBB based on incoming instruction
5980 assert(bInstr->getNumOperands() < 8 && "unexpected number of operands");
5981 MachineOperand& destOper = bInstr->getOperand(0);
5982 MachineOperand* argOpers[6];
5983 int numArgs = bInstr->getNumOperands() - 1;
5984 for (int i=0; i < numArgs; ++i)
5985 argOpers[i] = &bInstr->getOperand(i+1);
5987 // x86 address has 4 operands: base, index, scale, and displacement
5988 int lastAddrIndx = 3; // [0,3]
5991 unsigned t1 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
5992 MachineInstrBuilder MIB = BuildMI(newMBB, TII->get(X86::MOV32rm), t1);
5993 for (int i=0; i <= lastAddrIndx; ++i)
5994 (*MIB).addOperand(*argOpers[i]);
5996 unsigned tt = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
5998 MIB = BuildMI(newMBB, TII->get(X86::NOT32r), tt).addReg(t1);
6003 unsigned t2 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
6004 assert( (argOpers[valArgIndx]->isReg() || argOpers[valArgIndx]->isImm())
6005 && "invalid operand");
6006 if (argOpers[valArgIndx]->isReg())
6007 MIB = BuildMI(newMBB, TII->get(regOpc), t2);
6009 MIB = BuildMI(newMBB, TII->get(immOpc), t2);
6011 (*MIB).addOperand(*argOpers[valArgIndx]);
6013 MIB = BuildMI(newMBB, TII->get(X86::MOV32rr), X86::EAX);
6016 MIB = BuildMI(newMBB, TII->get(X86::LCMPXCHG32));
6017 for (int i=0; i <= lastAddrIndx; ++i)
6018 (*MIB).addOperand(*argOpers[i]);
6021 MIB = BuildMI(newMBB, TII->get(X86::MOV32rr), destOper.getReg());
6022 MIB.addReg(X86::EAX);
6025 BuildMI(newMBB, TII->get(X86::JNE)).addMBB(newMBB);
6027 F->DeleteMachineInstr(bInstr); // The pseudo instruction is gone now.
6031 // private utility function
6033 X86TargetLowering::EmitAtomicMinMaxWithCustomInserter(MachineInstr *mInstr,
6034 MachineBasicBlock *MBB,
6036 // For the atomic min/max operator, we generate
6039 // ld t1 = [min/max.addr]
6040 // mov t2 = [min/max.val]
6042 // cmov[cond] t2 = t1
6044 // lcs dest = [bitinstr.addr], t2 [EAX is implicit]
6046 // fallthrough -->nextMBB
6048 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
6049 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
6050 MachineFunction::iterator MBBIter = MBB;
6053 /// First build the CFG
6054 MachineFunction *F = MBB->getParent();
6055 MachineBasicBlock *thisMBB = MBB;
6056 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
6057 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
6058 F->insert(MBBIter, newMBB);
6059 F->insert(MBBIter, nextMBB);
6061 // Move all successors to thisMBB to nextMBB
6062 nextMBB->transferSuccessors(thisMBB);
6064 // Update thisMBB to fall through to newMBB
6065 thisMBB->addSuccessor(newMBB);
6067 // newMBB jumps to newMBB and fall through to nextMBB
6068 newMBB->addSuccessor(nextMBB);
6069 newMBB->addSuccessor(newMBB);
6071 // Insert instructions into newMBB based on incoming instruction
6072 assert(mInstr->getNumOperands() < 8 && "unexpected number of operands");
6073 MachineOperand& destOper = mInstr->getOperand(0);
6074 MachineOperand* argOpers[6];
6075 int numArgs = mInstr->getNumOperands() - 1;
6076 for (int i=0; i < numArgs; ++i)
6077 argOpers[i] = &mInstr->getOperand(i+1);
6079 // x86 address has 4 operands: base, index, scale, and displacement
6080 int lastAddrIndx = 3; // [0,3]
6083 unsigned t1 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
6084 MachineInstrBuilder MIB = BuildMI(newMBB, TII->get(X86::MOV32rm), t1);
6085 for (int i=0; i <= lastAddrIndx; ++i)
6086 (*MIB).addOperand(*argOpers[i]);
6088 // We only support register and immediate values
6089 assert( (argOpers[valArgIndx]->isReg() || argOpers[valArgIndx]->isImm())
6090 && "invalid operand");
6092 unsigned t2 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
6093 if (argOpers[valArgIndx]->isReg())
6094 MIB = BuildMI(newMBB, TII->get(X86::MOV32rr), t2);
6096 MIB = BuildMI(newMBB, TII->get(X86::MOV32rr), t2);
6097 (*MIB).addOperand(*argOpers[valArgIndx]);
6099 MIB = BuildMI(newMBB, TII->get(X86::MOV32rr), X86::EAX);
6102 MIB = BuildMI(newMBB, TII->get(X86::CMP32rr));
6107 unsigned t3 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
6108 MIB = BuildMI(newMBB, TII->get(cmovOpc),t3);
6112 // Cmp and exchange if none has modified the memory location
6113 MIB = BuildMI(newMBB, TII->get(X86::LCMPXCHG32));
6114 for (int i=0; i <= lastAddrIndx; ++i)
6115 (*MIB).addOperand(*argOpers[i]);
6118 MIB = BuildMI(newMBB, TII->get(X86::MOV32rr), destOper.getReg());
6119 MIB.addReg(X86::EAX);
6122 BuildMI(newMBB, TII->get(X86::JNE)).addMBB(newMBB);
6124 F->DeleteMachineInstr(mInstr); // The pseudo instruction is gone now.
6130 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
6131 MachineBasicBlock *BB) {
6132 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
6133 switch (MI->getOpcode()) {
6134 default: assert(false && "Unexpected instr type to insert");
6135 case X86::CMOV_FR32:
6136 case X86::CMOV_FR64:
6137 case X86::CMOV_V4F32:
6138 case X86::CMOV_V2F64:
6139 case X86::CMOV_V2I64: {
6140 // To "insert" a SELECT_CC instruction, we actually have to insert the
6141 // diamond control-flow pattern. The incoming instruction knows the
6142 // destination vreg to set, the condition code register to branch on, the
6143 // true/false values to select between, and a branch opcode to use.
6144 const BasicBlock *LLVM_BB = BB->getBasicBlock();
6145 MachineFunction::iterator It = BB;
6151 // cmpTY ccX, r1, r2
6153 // fallthrough --> copy0MBB
6154 MachineBasicBlock *thisMBB = BB;
6155 MachineFunction *F = BB->getParent();
6156 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
6157 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
6159 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
6160 BuildMI(BB, TII->get(Opc)).addMBB(sinkMBB);
6161 F->insert(It, copy0MBB);
6162 F->insert(It, sinkMBB);
6163 // Update machine-CFG edges by transferring all successors of the current
6164 // block to the new block which will contain the Phi node for the select.
6165 sinkMBB->transferSuccessors(BB);
6167 // Add the true and fallthrough blocks as its successors.
6168 BB->addSuccessor(copy0MBB);
6169 BB->addSuccessor(sinkMBB);
6172 // %FalseValue = ...
6173 // # fallthrough to sinkMBB
6176 // Update machine-CFG edges
6177 BB->addSuccessor(sinkMBB);
6180 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
6183 BuildMI(BB, TII->get(X86::PHI), MI->getOperand(0).getReg())
6184 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
6185 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
6187 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
6191 case X86::FP32_TO_INT16_IN_MEM:
6192 case X86::FP32_TO_INT32_IN_MEM:
6193 case X86::FP32_TO_INT64_IN_MEM:
6194 case X86::FP64_TO_INT16_IN_MEM:
6195 case X86::FP64_TO_INT32_IN_MEM:
6196 case X86::FP64_TO_INT64_IN_MEM:
6197 case X86::FP80_TO_INT16_IN_MEM:
6198 case X86::FP80_TO_INT32_IN_MEM:
6199 case X86::FP80_TO_INT64_IN_MEM: {
6200 // Change the floating point control register to use "round towards zero"
6201 // mode when truncating to an integer value.
6202 MachineFunction *F = BB->getParent();
6203 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2);
6204 addFrameReference(BuildMI(BB, TII->get(X86::FNSTCW16m)), CWFrameIdx);
6206 // Load the old value of the high byte of the control word...
6208 F->getRegInfo().createVirtualRegister(X86::GR16RegisterClass);
6209 addFrameReference(BuildMI(BB, TII->get(X86::MOV16rm), OldCW), CWFrameIdx);
6211 // Set the high part to be round to zero...
6212 addFrameReference(BuildMI(BB, TII->get(X86::MOV16mi)), CWFrameIdx)
6215 // Reload the modified control word now...
6216 addFrameReference(BuildMI(BB, TII->get(X86::FLDCW16m)), CWFrameIdx);
6218 // Restore the memory image of control word to original value
6219 addFrameReference(BuildMI(BB, TII->get(X86::MOV16mr)), CWFrameIdx)
6222 // Get the X86 opcode to use.
6224 switch (MI->getOpcode()) {
6225 default: assert(0 && "illegal opcode!");
6226 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
6227 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
6228 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
6229 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
6230 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
6231 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
6232 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
6233 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
6234 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
6238 MachineOperand &Op = MI->getOperand(0);
6239 if (Op.isRegister()) {
6240 AM.BaseType = X86AddressMode::RegBase;
6241 AM.Base.Reg = Op.getReg();
6243 AM.BaseType = X86AddressMode::FrameIndexBase;
6244 AM.Base.FrameIndex = Op.getIndex();
6246 Op = MI->getOperand(1);
6247 if (Op.isImmediate())
6248 AM.Scale = Op.getImm();
6249 Op = MI->getOperand(2);
6250 if (Op.isImmediate())
6251 AM.IndexReg = Op.getImm();
6252 Op = MI->getOperand(3);
6253 if (Op.isGlobalAddress()) {
6254 AM.GV = Op.getGlobal();
6256 AM.Disp = Op.getImm();
6258 addFullAddress(BuildMI(BB, TII->get(Opc)), AM)
6259 .addReg(MI->getOperand(4).getReg());
6261 // Reload the original control word now.
6262 addFrameReference(BuildMI(BB, TII->get(X86::FLDCW16m)), CWFrameIdx);
6264 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
6267 case X86::ATOMAND32:
6268 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr,
6271 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR32rr,
6273 case X86::ATOMXOR32:
6274 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR32rr,
6276 case X86::ATOMNAND32:
6277 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr,
6278 X86::AND32ri, true);
6279 case X86::ATOMMIN32:
6280 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL32rr);
6281 case X86::ATOMMAX32:
6282 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG32rr);
6283 case X86::ATOMUMIN32:
6284 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB32rr);
6285 case X86::ATOMUMAX32:
6286 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA32rr);
6290 //===----------------------------------------------------------------------===//
6291 // X86 Optimization Hooks
6292 //===----------------------------------------------------------------------===//
6294 void X86TargetLowering::computeMaskedBitsForTargetNode(const SDOperand Op,
6298 const SelectionDAG &DAG,
6299 unsigned Depth) const {
6300 unsigned Opc = Op.getOpcode();
6301 assert((Opc >= ISD::BUILTIN_OP_END ||
6302 Opc == ISD::INTRINSIC_WO_CHAIN ||
6303 Opc == ISD::INTRINSIC_W_CHAIN ||
6304 Opc == ISD::INTRINSIC_VOID) &&
6305 "Should use MaskedValueIsZero if you don't know whether Op"
6306 " is a target node!");
6308 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0); // Don't know anything.
6312 KnownZero |= APInt::getHighBitsSet(Mask.getBitWidth(),
6313 Mask.getBitWidth() - 1);
6318 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
6319 /// node is a GlobalAddress + offset.
6320 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
6321 GlobalValue* &GA, int64_t &Offset) const{
6322 if (N->getOpcode() == X86ISD::Wrapper) {
6323 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
6324 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
6328 return TargetLowering::isGAPlusOffset(N, GA, Offset);
6331 static bool isBaseAlignmentOfN(unsigned N, SDNode *Base,
6332 const TargetLowering &TLI) {
6335 if (TLI.isGAPlusOffset(Base, GV, Offset))
6336 return (GV->getAlignment() >= N && (Offset % N) == 0);
6337 // DAG combine handles the stack object case.
6341 static bool EltsFromConsecutiveLoads(SDNode *N, SDOperand PermMask,
6342 unsigned NumElems, MVT EVT,
6344 SelectionDAG &DAG, MachineFrameInfo *MFI,
6345 const TargetLowering &TLI) {
6347 for (unsigned i = 0; i < NumElems; ++i) {
6348 SDOperand Idx = PermMask.getOperand(i);
6349 if (Idx.getOpcode() == ISD::UNDEF) {
6355 SDOperand Elt = DAG.getShuffleScalarElt(N, i);
6357 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.Val)))
6361 if (Base->getOpcode() == ISD::UNDEF)
6365 if (Elt.getOpcode() == ISD::UNDEF)
6368 if (!TLI.isConsecutiveLoad(Elt.Val, Base,
6369 EVT.getSizeInBits()/8, i, MFI))
6375 /// PerformShuffleCombine - Combine a vector_shuffle that is equal to
6376 /// build_vector load1, load2, load3, load4, <0, 1, 2, 3> into a 128-bit load
6377 /// if the load addresses are consecutive, non-overlapping, and in the right
6379 static SDOperand PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
6380 const TargetLowering &TLI) {
6381 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
6382 MVT VT = N->getValueType(0);
6383 MVT EVT = VT.getVectorElementType();
6384 SDOperand PermMask = N->getOperand(2);
6385 unsigned NumElems = PermMask.getNumOperands();
6386 SDNode *Base = NULL;
6387 if (!EltsFromConsecutiveLoads(N, PermMask, NumElems, EVT, Base,
6391 LoadSDNode *LD = cast<LoadSDNode>(Base);
6392 if (isBaseAlignmentOfN(16, Base->getOperand(1).Val, TLI))
6393 return DAG.getLoad(VT, LD->getChain(), LD->getBasePtr(), LD->getSrcValue(),
6394 LD->getSrcValueOffset(), LD->isVolatile());
6395 return DAG.getLoad(VT, LD->getChain(), LD->getBasePtr(), LD->getSrcValue(),
6396 LD->getSrcValueOffset(), LD->isVolatile(),
6397 LD->getAlignment());
6400 /// PerformBuildVectorCombine - build_vector 0,(load i64 / f64) -> movq / movsd.
6401 static SDOperand PerformBuildVectorCombine(SDNode *N, SelectionDAG &DAG,
6402 const X86Subtarget *Subtarget,
6403 const TargetLowering &TLI) {
6404 unsigned NumOps = N->getNumOperands();
6406 // Ignore single operand BUILD_VECTOR.
6410 MVT VT = N->getValueType(0);
6411 MVT EVT = VT.getVectorElementType();
6412 if ((EVT != MVT::i64 && EVT != MVT::f64) || Subtarget->is64Bit())
6413 // We are looking for load i64 and zero extend. We want to transform
6414 // it before legalizer has a chance to expand it. Also look for i64
6415 // BUILD_PAIR bit casted to f64.
6417 // This must be an insertion into a zero vector.
6418 SDOperand HighElt = N->getOperand(1);
6419 if (!isZeroNode(HighElt))
6422 // Value must be a load.
6423 SDNode *Base = N->getOperand(0).Val;
6424 if (!isa<LoadSDNode>(Base)) {
6425 if (Base->getOpcode() != ISD::BIT_CONVERT)
6427 Base = Base->getOperand(0).Val;
6428 if (!isa<LoadSDNode>(Base))
6432 // Transform it into VZEXT_LOAD addr.
6433 LoadSDNode *LD = cast<LoadSDNode>(Base);
6435 // Load must not be an extload.
6436 if (LD->getExtensionType() != ISD::NON_EXTLOAD)
6439 return DAG.getNode(X86ISD::VZEXT_LOAD, VT, LD->getChain(), LD->getBasePtr());
6442 /// PerformSELECTCombine - Do target-specific dag combines on SELECT nodes.
6443 static SDOperand PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
6444 const X86Subtarget *Subtarget) {
6445 SDOperand Cond = N->getOperand(0);
6447 // If we have SSE[12] support, try to form min/max nodes.
6448 if (Subtarget->hasSSE2() &&
6449 (N->getValueType(0) == MVT::f32 || N->getValueType(0) == MVT::f64)) {
6450 if (Cond.getOpcode() == ISD::SETCC) {
6451 // Get the LHS/RHS of the select.
6452 SDOperand LHS = N->getOperand(1);
6453 SDOperand RHS = N->getOperand(2);
6454 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
6456 unsigned Opcode = 0;
6457 if (LHS == Cond.getOperand(0) && RHS == Cond.getOperand(1)) {
6460 case ISD::SETOLE: // (X <= Y) ? X : Y -> min
6463 if (!UnsafeFPMath) break;
6465 case ISD::SETOLT: // (X olt/lt Y) ? X : Y -> min
6467 Opcode = X86ISD::FMIN;
6470 case ISD::SETOGT: // (X > Y) ? X : Y -> max
6473 if (!UnsafeFPMath) break;
6475 case ISD::SETUGE: // (X uge/ge Y) ? X : Y -> max
6477 Opcode = X86ISD::FMAX;
6480 } else if (LHS == Cond.getOperand(1) && RHS == Cond.getOperand(0)) {
6483 case ISD::SETOGT: // (X > Y) ? Y : X -> min
6486 if (!UnsafeFPMath) break;
6488 case ISD::SETUGE: // (X uge/ge Y) ? Y : X -> min
6490 Opcode = X86ISD::FMIN;
6493 case ISD::SETOLE: // (X <= Y) ? Y : X -> max
6496 if (!UnsafeFPMath) break;
6498 case ISD::SETOLT: // (X olt/lt Y) ? Y : X -> max
6500 Opcode = X86ISD::FMAX;
6506 return DAG.getNode(Opcode, N->getValueType(0), LHS, RHS);
6514 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
6515 static SDOperand PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
6516 const X86Subtarget *Subtarget) {
6517 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
6518 // the FP state in cases where an emms may be missing.
6519 // A preferable solution to the general problem is to figure out the right
6520 // places to insert EMMS. This qualifies as a quick hack.
6521 StoreSDNode *St = cast<StoreSDNode>(N);
6522 if (St->getValue().getValueType().isVector() &&
6523 St->getValue().getValueType().getSizeInBits() == 64 &&
6524 isa<LoadSDNode>(St->getValue()) &&
6525 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
6526 St->getChain().hasOneUse() && !St->isVolatile()) {
6527 SDNode* LdVal = St->getValue().Val;
6529 int TokenFactorIndex = -1;
6530 SmallVector<SDOperand, 8> Ops;
6531 SDNode* ChainVal = St->getChain().Val;
6532 // Must be a store of a load. We currently handle two cases: the load
6533 // is a direct child, and it's under an intervening TokenFactor. It is
6534 // possible to dig deeper under nested TokenFactors.
6535 if (ChainVal == LdVal)
6536 Ld = cast<LoadSDNode>(St->getChain());
6537 else if (St->getValue().hasOneUse() &&
6538 ChainVal->getOpcode() == ISD::TokenFactor) {
6539 for (unsigned i=0, e = ChainVal->getNumOperands(); i != e; ++i) {
6540 if (ChainVal->getOperand(i).Val == LdVal) {
6541 TokenFactorIndex = i;
6542 Ld = cast<LoadSDNode>(St->getValue());
6544 Ops.push_back(ChainVal->getOperand(i));
6548 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
6549 if (Subtarget->is64Bit()) {
6550 SDOperand NewLd = DAG.getLoad(MVT::i64, Ld->getChain(),
6551 Ld->getBasePtr(), Ld->getSrcValue(),
6552 Ld->getSrcValueOffset(), Ld->isVolatile(),
6553 Ld->getAlignment());
6554 SDOperand NewChain = NewLd.getValue(1);
6555 if (TokenFactorIndex != -1) {
6556 Ops.push_back(NewChain);
6557 NewChain = DAG.getNode(ISD::TokenFactor, MVT::Other, &Ops[0],
6560 return DAG.getStore(NewChain, NewLd, St->getBasePtr(),
6561 St->getSrcValue(), St->getSrcValueOffset(),
6562 St->isVolatile(), St->getAlignment());
6565 // Otherwise, lower to two 32-bit copies.
6566 SDOperand LoAddr = Ld->getBasePtr();
6567 SDOperand HiAddr = DAG.getNode(ISD::ADD, MVT::i32, LoAddr,
6568 DAG.getConstant(4, MVT::i32));
6570 SDOperand LoLd = DAG.getLoad(MVT::i32, Ld->getChain(), LoAddr,
6571 Ld->getSrcValue(), Ld->getSrcValueOffset(),
6572 Ld->isVolatile(), Ld->getAlignment());
6573 SDOperand HiLd = DAG.getLoad(MVT::i32, Ld->getChain(), HiAddr,
6574 Ld->getSrcValue(), Ld->getSrcValueOffset()+4,
6576 MinAlign(Ld->getAlignment(), 4));
6578 SDOperand NewChain = LoLd.getValue(1);
6579 if (TokenFactorIndex != -1) {
6580 Ops.push_back(LoLd);
6581 Ops.push_back(HiLd);
6582 NewChain = DAG.getNode(ISD::TokenFactor, MVT::Other, &Ops[0],
6586 LoAddr = St->getBasePtr();
6587 HiAddr = DAG.getNode(ISD::ADD, MVT::i32, LoAddr,
6588 DAG.getConstant(4, MVT::i32));
6590 SDOperand LoSt = DAG.getStore(NewChain, LoLd, LoAddr,
6591 St->getSrcValue(), St->getSrcValueOffset(),
6592 St->isVolatile(), St->getAlignment());
6593 SDOperand HiSt = DAG.getStore(NewChain, HiLd, HiAddr,
6594 St->getSrcValue(), St->getSrcValueOffset()+4,
6596 MinAlign(St->getAlignment(), 4));
6597 return DAG.getNode(ISD::TokenFactor, MVT::Other, LoSt, HiSt);
6603 /// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and
6604 /// X86ISD::FXOR nodes.
6605 static SDOperand PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
6606 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
6607 // F[X]OR(0.0, x) -> x
6608 // F[X]OR(x, 0.0) -> x
6609 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
6610 if (C->getValueAPF().isPosZero())
6611 return N->getOperand(1);
6612 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
6613 if (C->getValueAPF().isPosZero())
6614 return N->getOperand(0);
6618 /// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes.
6619 static SDOperand PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
6620 // FAND(0.0, x) -> 0.0
6621 // FAND(x, 0.0) -> 0.0
6622 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
6623 if (C->getValueAPF().isPosZero())
6624 return N->getOperand(0);
6625 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
6626 if (C->getValueAPF().isPosZero())
6627 return N->getOperand(1);
6632 SDOperand X86TargetLowering::PerformDAGCombine(SDNode *N,
6633 DAGCombinerInfo &DCI) const {
6634 SelectionDAG &DAG = DCI.DAG;
6635 switch (N->getOpcode()) {
6637 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, *this);
6638 case ISD::BUILD_VECTOR:
6639 return PerformBuildVectorCombine(N, DAG, Subtarget, *this);
6640 case ISD::SELECT: return PerformSELECTCombine(N, DAG, Subtarget);
6641 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
6643 case X86ISD::FOR: return PerformFORCombine(N, DAG);
6644 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
6650 //===----------------------------------------------------------------------===//
6651 // X86 Inline Assembly Support
6652 //===----------------------------------------------------------------------===//
6654 /// getConstraintType - Given a constraint letter, return the type of
6655 /// constraint it is for this target.
6656 X86TargetLowering::ConstraintType
6657 X86TargetLowering::getConstraintType(const std::string &Constraint) const {
6658 if (Constraint.size() == 1) {
6659 switch (Constraint[0]) {
6670 return C_RegisterClass;
6675 return TargetLowering::getConstraintType(Constraint);
6678 /// LowerXConstraint - try to replace an X constraint, which matches anything,
6679 /// with another that has more specific requirements based on the type of the
6680 /// corresponding operand.
6681 const char *X86TargetLowering::
6682 LowerXConstraint(MVT ConstraintVT) const {
6683 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
6684 // 'f' like normal targets.
6685 if (ConstraintVT.isFloatingPoint()) {
6686 if (Subtarget->hasSSE2())
6688 if (Subtarget->hasSSE1())
6692 return TargetLowering::LowerXConstraint(ConstraintVT);
6695 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
6696 /// vector. If it is invalid, don't add anything to Ops.
6697 void X86TargetLowering::LowerAsmOperandForConstraint(SDOperand Op,
6699 std::vector<SDOperand>&Ops,
6700 SelectionDAG &DAG) const {
6701 SDOperand Result(0, 0);
6703 switch (Constraint) {
6706 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
6707 if (C->getValue() <= 31) {
6708 Result = DAG.getTargetConstant(C->getValue(), Op.getValueType());
6714 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
6715 if (C->getValue() <= 255) {
6716 Result = DAG.getTargetConstant(C->getValue(), Op.getValueType());
6722 // Literal immediates are always ok.
6723 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
6724 Result = DAG.getTargetConstant(CST->getValue(), Op.getValueType());
6728 // If we are in non-pic codegen mode, we allow the address of a global (with
6729 // an optional displacement) to be used with 'i'.
6730 GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Op);
6733 // Match either (GA) or (GA+C)
6735 Offset = GA->getOffset();
6736 } else if (Op.getOpcode() == ISD::ADD) {
6737 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
6738 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(0));
6740 Offset = GA->getOffset()+C->getValue();
6742 C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
6743 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(0));
6745 Offset = GA->getOffset()+C->getValue();
6752 // If addressing this global requires a load (e.g. in PIC mode), we can't
6754 if (Subtarget->GVRequiresExtraLoad(GA->getGlobal(), getTargetMachine(),
6758 Op = DAG.getTargetGlobalAddress(GA->getGlobal(), GA->getValueType(0),
6764 // Otherwise, not valid for this mode.
6770 Ops.push_back(Result);
6773 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
6776 std::vector<unsigned> X86TargetLowering::
6777 getRegClassForInlineAsmConstraint(const std::string &Constraint,
6779 if (Constraint.size() == 1) {
6780 // FIXME: not handling fp-stack yet!
6781 switch (Constraint[0]) { // GCC X86 Constraint Letters
6782 default: break; // Unknown constraint letter
6783 case 'A': // EAX/EDX
6784 if (VT == MVT::i32 || VT == MVT::i64)
6785 return make_vector<unsigned>(X86::EAX, X86::EDX, 0);
6787 case 'q': // Q_REGS (GENERAL_REGS in 64-bit mode)
6790 return make_vector<unsigned>(X86::EAX, X86::EDX, X86::ECX, X86::EBX, 0);
6791 else if (VT == MVT::i16)
6792 return make_vector<unsigned>(X86::AX, X86::DX, X86::CX, X86::BX, 0);
6793 else if (VT == MVT::i8)
6794 return make_vector<unsigned>(X86::AL, X86::DL, X86::CL, X86::BL, 0);
6795 else if (VT == MVT::i64)
6796 return make_vector<unsigned>(X86::RAX, X86::RDX, X86::RCX, X86::RBX, 0);
6801 return std::vector<unsigned>();
6804 std::pair<unsigned, const TargetRegisterClass*>
6805 X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
6807 // First, see if this is a constraint that directly corresponds to an LLVM
6809 if (Constraint.size() == 1) {
6810 // GCC Constraint Letters
6811 switch (Constraint[0]) {
6813 case 'r': // GENERAL_REGS
6814 case 'R': // LEGACY_REGS
6815 case 'l': // INDEX_REGS
6816 if (VT == MVT::i64 && Subtarget->is64Bit())
6817 return std::make_pair(0U, X86::GR64RegisterClass);
6819 return std::make_pair(0U, X86::GR32RegisterClass);
6820 else if (VT == MVT::i16)
6821 return std::make_pair(0U, X86::GR16RegisterClass);
6822 else if (VT == MVT::i8)
6823 return std::make_pair(0U, X86::GR8RegisterClass);
6825 case 'f': // FP Stack registers.
6826 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
6827 // value to the correct fpstack register class.
6828 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
6829 return std::make_pair(0U, X86::RFP32RegisterClass);
6830 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
6831 return std::make_pair(0U, X86::RFP64RegisterClass);
6832 return std::make_pair(0U, X86::RFP80RegisterClass);
6833 case 'y': // MMX_REGS if MMX allowed.
6834 if (!Subtarget->hasMMX()) break;
6835 return std::make_pair(0U, X86::VR64RegisterClass);
6837 case 'Y': // SSE_REGS if SSE2 allowed
6838 if (!Subtarget->hasSSE2()) break;
6840 case 'x': // SSE_REGS if SSE1 allowed
6841 if (!Subtarget->hasSSE1()) break;
6843 switch (VT.getSimpleVT()) {
6845 // Scalar SSE types.
6848 return std::make_pair(0U, X86::FR32RegisterClass);
6851 return std::make_pair(0U, X86::FR64RegisterClass);
6859 return std::make_pair(0U, X86::VR128RegisterClass);
6865 // Use the default implementation in TargetLowering to convert the register
6866 // constraint into a member of a register class.
6867 std::pair<unsigned, const TargetRegisterClass*> Res;
6868 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
6870 // Not found as a standard register?
6871 if (Res.second == 0) {
6872 // GCC calls "st(0)" just plain "st".
6873 if (StringsEqualNoCase("{st}", Constraint)) {
6874 Res.first = X86::ST0;
6875 Res.second = X86::RFP80RegisterClass;
6881 // Otherwise, check to see if this is a register class of the wrong value
6882 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
6883 // turn into {ax},{dx}.
6884 if (Res.second->hasType(VT))
6885 return Res; // Correct type already, nothing to do.
6887 // All of the single-register GCC register classes map their values onto
6888 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
6889 // really want an 8-bit or 32-bit register, map to the appropriate register
6890 // class and return the appropriate register.
6891 if (Res.second != X86::GR16RegisterClass)
6894 if (VT == MVT::i8) {
6895 unsigned DestReg = 0;
6896 switch (Res.first) {
6898 case X86::AX: DestReg = X86::AL; break;
6899 case X86::DX: DestReg = X86::DL; break;
6900 case X86::CX: DestReg = X86::CL; break;
6901 case X86::BX: DestReg = X86::BL; break;
6904 Res.first = DestReg;
6905 Res.second = Res.second = X86::GR8RegisterClass;
6907 } else if (VT == MVT::i32) {
6908 unsigned DestReg = 0;
6909 switch (Res.first) {
6911 case X86::AX: DestReg = X86::EAX; break;
6912 case X86::DX: DestReg = X86::EDX; break;
6913 case X86::CX: DestReg = X86::ECX; break;
6914 case X86::BX: DestReg = X86::EBX; break;
6915 case X86::SI: DestReg = X86::ESI; break;
6916 case X86::DI: DestReg = X86::EDI; break;
6917 case X86::BP: DestReg = X86::EBP; break;
6918 case X86::SP: DestReg = X86::ESP; break;
6921 Res.first = DestReg;
6922 Res.second = Res.second = X86::GR32RegisterClass;
6924 } else if (VT == MVT::i64) {
6925 unsigned DestReg = 0;
6926 switch (Res.first) {
6928 case X86::AX: DestReg = X86::RAX; break;
6929 case X86::DX: DestReg = X86::RDX; break;
6930 case X86::CX: DestReg = X86::RCX; break;
6931 case X86::BX: DestReg = X86::RBX; break;
6932 case X86::SI: DestReg = X86::RSI; break;
6933 case X86::DI: DestReg = X86::RDI; break;
6934 case X86::BP: DestReg = X86::RBP; break;
6935 case X86::SP: DestReg = X86::RSP; break;
6938 Res.first = DestReg;
6939 Res.second = Res.second = X86::GR64RegisterClass;