1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #include "X86ISelLowering.h"
16 #include "Utils/X86ShuffleDecode.h"
17 #include "X86CallingConv.h"
18 #include "X86InstrBuilder.h"
19 #include "X86MachineFunctionInfo.h"
20 #include "X86TargetMachine.h"
21 #include "X86TargetObjectFile.h"
22 #include "llvm/ADT/SmallSet.h"
23 #include "llvm/ADT/Statistic.h"
24 #include "llvm/ADT/StringExtras.h"
25 #include "llvm/ADT/StringSwitch.h"
26 #include "llvm/ADT/VariadicFunction.h"
27 #include "llvm/CodeGen/IntrinsicLowering.h"
28 #include "llvm/CodeGen/MachineFrameInfo.h"
29 #include "llvm/CodeGen/MachineFunction.h"
30 #include "llvm/CodeGen/MachineInstrBuilder.h"
31 #include "llvm/CodeGen/MachineJumpTableInfo.h"
32 #include "llvm/CodeGen/MachineModuleInfo.h"
33 #include "llvm/CodeGen/MachineRegisterInfo.h"
34 #include "llvm/IR/CallSite.h"
35 #include "llvm/IR/CallingConv.h"
36 #include "llvm/IR/Constants.h"
37 #include "llvm/IR/DerivedTypes.h"
38 #include "llvm/IR/Function.h"
39 #include "llvm/IR/GlobalAlias.h"
40 #include "llvm/IR/GlobalVariable.h"
41 #include "llvm/IR/Instructions.h"
42 #include "llvm/IR/Intrinsics.h"
43 #include "llvm/MC/MCAsmInfo.h"
44 #include "llvm/MC/MCContext.h"
45 #include "llvm/MC/MCExpr.h"
46 #include "llvm/MC/MCSymbol.h"
47 #include "llvm/Support/CommandLine.h"
48 #include "llvm/Support/Debug.h"
49 #include "llvm/Support/ErrorHandling.h"
50 #include "llvm/Support/MathExtras.h"
51 #include "llvm/Target/TargetOptions.h"
57 #define DEBUG_TYPE "x86-isel"
59 STATISTIC(NumTailCalls, "Number of tail calls");
61 static cl::opt<bool> ExperimentalVectorWideningLegalization(
62 "x86-experimental-vector-widening-legalization", cl::init(false),
63 cl::desc("Enable an experimental vector type legalization through widening "
64 "rather than promotion."),
67 static cl::opt<bool> ExperimentalVectorShuffleLowering(
68 "x86-experimental-vector-shuffle-lowering", cl::init(false),
69 cl::desc("Enable an experimental vector shuffle lowering code path."),
72 // Forward declarations.
73 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
76 static SDValue ExtractSubVector(SDValue Vec, unsigned IdxVal,
77 SelectionDAG &DAG, SDLoc dl,
78 unsigned vectorWidth) {
79 assert((vectorWidth == 128 || vectorWidth == 256) &&
80 "Unsupported vector width");
81 EVT VT = Vec.getValueType();
82 EVT ElVT = VT.getVectorElementType();
83 unsigned Factor = VT.getSizeInBits()/vectorWidth;
84 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT,
85 VT.getVectorNumElements()/Factor);
87 // Extract from UNDEF is UNDEF.
88 if (Vec.getOpcode() == ISD::UNDEF)
89 return DAG.getUNDEF(ResultVT);
91 // Extract the relevant vectorWidth bits. Generate an EXTRACT_SUBVECTOR
92 unsigned ElemsPerChunk = vectorWidth / ElVT.getSizeInBits();
94 // This is the index of the first element of the vectorWidth-bit chunk
96 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits()) / vectorWidth)
99 // If the input is a buildvector just emit a smaller one.
100 if (Vec.getOpcode() == ISD::BUILD_VECTOR)
101 return DAG.getNode(ISD::BUILD_VECTOR, dl, ResultVT,
102 makeArrayRef(Vec->op_begin()+NormalizedIdxVal,
105 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal);
106 SDValue Result = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec,
112 /// Generate a DAG to grab 128-bits from a vector > 128 bits. This
113 /// sets things up to match to an AVX VEXTRACTF128 / VEXTRACTI128
114 /// or AVX-512 VEXTRACTF32x4 / VEXTRACTI32x4
115 /// instructions or a simple subregister reference. Idx is an index in the
116 /// 128 bits we want. It need not be aligned to a 128-bit bounday. That makes
117 /// lowering EXTRACT_VECTOR_ELT operations easier.
118 static SDValue Extract128BitVector(SDValue Vec, unsigned IdxVal,
119 SelectionDAG &DAG, SDLoc dl) {
120 assert((Vec.getValueType().is256BitVector() ||
121 Vec.getValueType().is512BitVector()) && "Unexpected vector size!");
122 return ExtractSubVector(Vec, IdxVal, DAG, dl, 128);
125 /// Generate a DAG to grab 256-bits from a 512-bit vector.
126 static SDValue Extract256BitVector(SDValue Vec, unsigned IdxVal,
127 SelectionDAG &DAG, SDLoc dl) {
128 assert(Vec.getValueType().is512BitVector() && "Unexpected vector size!");
129 return ExtractSubVector(Vec, IdxVal, DAG, dl, 256);
132 static SDValue InsertSubVector(SDValue Result, SDValue Vec,
133 unsigned IdxVal, SelectionDAG &DAG,
134 SDLoc dl, unsigned vectorWidth) {
135 assert((vectorWidth == 128 || vectorWidth == 256) &&
136 "Unsupported vector width");
137 // Inserting UNDEF is Result
138 if (Vec.getOpcode() == ISD::UNDEF)
140 EVT VT = Vec.getValueType();
141 EVT ElVT = VT.getVectorElementType();
142 EVT ResultVT = Result.getValueType();
144 // Insert the relevant vectorWidth bits.
145 unsigned ElemsPerChunk = vectorWidth/ElVT.getSizeInBits();
147 // This is the index of the first element of the vectorWidth-bit chunk
149 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits())/vectorWidth)
152 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal);
153 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec,
156 /// Generate a DAG to put 128-bits into a vector > 128 bits. This
157 /// sets things up to match to an AVX VINSERTF128/VINSERTI128 or
158 /// AVX-512 VINSERTF32x4/VINSERTI32x4 instructions or a
159 /// simple superregister reference. Idx is an index in the 128 bits
160 /// we want. It need not be aligned to a 128-bit bounday. That makes
161 /// lowering INSERT_VECTOR_ELT operations easier.
162 static SDValue Insert128BitVector(SDValue Result, SDValue Vec,
163 unsigned IdxVal, SelectionDAG &DAG,
165 assert(Vec.getValueType().is128BitVector() && "Unexpected vector size!");
166 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 128);
169 static SDValue Insert256BitVector(SDValue Result, SDValue Vec,
170 unsigned IdxVal, SelectionDAG &DAG,
172 assert(Vec.getValueType().is256BitVector() && "Unexpected vector size!");
173 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 256);
176 /// Concat two 128-bit vectors into a 256 bit vector using VINSERTF128
177 /// instructions. This is used because creating CONCAT_VECTOR nodes of
178 /// BUILD_VECTORS returns a larger BUILD_VECTOR while we're trying to lower
179 /// large BUILD_VECTORS.
180 static SDValue Concat128BitVectors(SDValue V1, SDValue V2, EVT VT,
181 unsigned NumElems, SelectionDAG &DAG,
183 SDValue V = Insert128BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
184 return Insert128BitVector(V, V2, NumElems/2, DAG, dl);
187 static SDValue Concat256BitVectors(SDValue V1, SDValue V2, EVT VT,
188 unsigned NumElems, SelectionDAG &DAG,
190 SDValue V = Insert256BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
191 return Insert256BitVector(V, V2, NumElems/2, DAG, dl);
194 static TargetLoweringObjectFile *createTLOF(const Triple &TT) {
195 if (TT.isOSBinFormatMachO()) {
196 if (TT.getArch() == Triple::x86_64)
197 return new X86_64MachoTargetObjectFile();
198 return new TargetLoweringObjectFileMachO();
202 return new X86LinuxTargetObjectFile();
203 if (TT.isOSBinFormatELF())
204 return new TargetLoweringObjectFileELF();
205 if (TT.isKnownWindowsMSVCEnvironment())
206 return new X86WindowsTargetObjectFile();
207 if (TT.isOSBinFormatCOFF())
208 return new TargetLoweringObjectFileCOFF();
209 llvm_unreachable("unknown subtarget type");
212 // FIXME: This should stop caching the target machine as soon as
213 // we can remove resetOperationActions et al.
214 X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
215 : TargetLowering(TM, createTLOF(Triple(TM.getTargetTriple()))) {
216 Subtarget = &TM.getSubtarget<X86Subtarget>();
217 X86ScalarSSEf64 = Subtarget->hasSSE2();
218 X86ScalarSSEf32 = Subtarget->hasSSE1();
219 TD = getDataLayout();
221 resetOperationActions();
224 void X86TargetLowering::resetOperationActions() {
225 const TargetMachine &TM = getTargetMachine();
226 static bool FirstTimeThrough = true;
228 // If none of the target options have changed, then we don't need to reset the
229 // operation actions.
230 if (!FirstTimeThrough && TO == TM.Options) return;
232 if (!FirstTimeThrough) {
233 // Reinitialize the actions.
235 FirstTimeThrough = false;
240 // Set up the TargetLowering object.
241 static const MVT IntVTs[] = { MVT::i8, MVT::i16, MVT::i32, MVT::i64 };
243 // X86 is weird, it always uses i8 for shift amounts and setcc results.
244 setBooleanContents(ZeroOrOneBooleanContent);
245 // X86-SSE is even stranger. It uses -1 or 0 for vector masks.
246 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
248 // For 64-bit since we have so many registers use the ILP scheduler, for
249 // 32-bit code use the register pressure specific scheduling.
250 // For Atom, always use ILP scheduling.
251 if (Subtarget->isAtom())
252 setSchedulingPreference(Sched::ILP);
253 else if (Subtarget->is64Bit())
254 setSchedulingPreference(Sched::ILP);
256 setSchedulingPreference(Sched::RegPressure);
257 const X86RegisterInfo *RegInfo =
258 TM.getSubtarget<X86Subtarget>().getRegisterInfo();
259 setStackPointerRegisterToSaveRestore(RegInfo->getStackRegister());
261 // Bypass expensive divides on Atom when compiling with O2
262 if (Subtarget->hasSlowDivide() && TM.getOptLevel() >= CodeGenOpt::Default) {
263 addBypassSlowDiv(32, 8);
264 if (Subtarget->is64Bit())
265 addBypassSlowDiv(64, 16);
268 if (Subtarget->isTargetKnownWindowsMSVC()) {
269 // Setup Windows compiler runtime calls.
270 setLibcallName(RTLIB::SDIV_I64, "_alldiv");
271 setLibcallName(RTLIB::UDIV_I64, "_aulldiv");
272 setLibcallName(RTLIB::SREM_I64, "_allrem");
273 setLibcallName(RTLIB::UREM_I64, "_aullrem");
274 setLibcallName(RTLIB::MUL_I64, "_allmul");
275 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall);
276 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall);
277 setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::X86_StdCall);
278 setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::X86_StdCall);
279 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::X86_StdCall);
281 // The _ftol2 runtime function has an unusual calling conv, which
282 // is modeled by a special pseudo-instruction.
283 setLibcallName(RTLIB::FPTOUINT_F64_I64, nullptr);
284 setLibcallName(RTLIB::FPTOUINT_F32_I64, nullptr);
285 setLibcallName(RTLIB::FPTOUINT_F64_I32, nullptr);
286 setLibcallName(RTLIB::FPTOUINT_F32_I32, nullptr);
289 if (Subtarget->isTargetDarwin()) {
290 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
291 setUseUnderscoreSetJmp(false);
292 setUseUnderscoreLongJmp(false);
293 } else if (Subtarget->isTargetWindowsGNU()) {
294 // MS runtime is weird: it exports _setjmp, but longjmp!
295 setUseUnderscoreSetJmp(true);
296 setUseUnderscoreLongJmp(false);
298 setUseUnderscoreSetJmp(true);
299 setUseUnderscoreLongJmp(true);
302 // Set up the register classes.
303 addRegisterClass(MVT::i8, &X86::GR8RegClass);
304 addRegisterClass(MVT::i16, &X86::GR16RegClass);
305 addRegisterClass(MVT::i32, &X86::GR32RegClass);
306 if (Subtarget->is64Bit())
307 addRegisterClass(MVT::i64, &X86::GR64RegClass);
309 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
311 // We don't accept any truncstore of integer registers.
312 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
313 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
314 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
315 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
316 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
317 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
319 // SETOEQ and SETUNE require checking two conditions.
320 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
321 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
322 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
323 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
324 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
325 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
327 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
329 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
330 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
331 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
333 if (Subtarget->is64Bit()) {
334 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
335 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
336 } else if (!TM.Options.UseSoftFloat) {
337 // We have an algorithm for SSE2->double, and we turn this into a
338 // 64-bit FILD followed by conditional FADD for other targets.
339 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
340 // We have an algorithm for SSE2, and we turn this into a 64-bit
341 // FILD for other targets.
342 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
345 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
347 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
348 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
350 if (!TM.Options.UseSoftFloat) {
351 // SSE has no i16 to fp conversion, only i32
352 if (X86ScalarSSEf32) {
353 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
354 // f32 and f64 cases are Legal, f80 case is not
355 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
357 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
358 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
361 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
362 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
365 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
366 // are Legal, f80 is custom lowered.
367 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
368 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
370 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
372 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
373 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
375 if (X86ScalarSSEf32) {
376 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
377 // f32 and f64 cases are Legal, f80 case is not
378 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
380 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
381 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
384 // Handle FP_TO_UINT by promoting the destination to a larger signed
386 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
387 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
388 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
390 if (Subtarget->is64Bit()) {
391 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
392 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
393 } else if (!TM.Options.UseSoftFloat) {
394 // Since AVX is a superset of SSE3, only check for SSE here.
395 if (Subtarget->hasSSE1() && !Subtarget->hasSSE3())
396 // Expand FP_TO_UINT into a select.
397 // FIXME: We would like to use a Custom expander here eventually to do
398 // the optimal thing for SSE vs. the default expansion in the legalizer.
399 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
401 // With SSE3 we can use fisttpll to convert to a signed i64; without
402 // SSE, we're stuck with a fistpll.
403 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
406 if (isTargetFTOL()) {
407 // Use the _ftol2 runtime function, which has a pseudo-instruction
408 // to handle its weird calling convention.
409 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Custom);
412 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
413 if (!X86ScalarSSEf64) {
414 setOperationAction(ISD::BITCAST , MVT::f32 , Expand);
415 setOperationAction(ISD::BITCAST , MVT::i32 , Expand);
416 if (Subtarget->is64Bit()) {
417 setOperationAction(ISD::BITCAST , MVT::f64 , Expand);
418 // Without SSE, i64->f64 goes through memory.
419 setOperationAction(ISD::BITCAST , MVT::i64 , Expand);
423 // Scalar integer divide and remainder are lowered to use operations that
424 // produce two results, to match the available instructions. This exposes
425 // the two-result form to trivial CSE, which is able to combine x/y and x%y
426 // into a single instruction.
428 // Scalar integer multiply-high is also lowered to use two-result
429 // operations, to match the available instructions. However, plain multiply
430 // (low) operations are left as Legal, as there are single-result
431 // instructions for this in x86. Using the two-result multiply instructions
432 // when both high and low results are needed must be arranged by dagcombine.
433 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
435 setOperationAction(ISD::MULHS, VT, Expand);
436 setOperationAction(ISD::MULHU, VT, Expand);
437 setOperationAction(ISD::SDIV, VT, Expand);
438 setOperationAction(ISD::UDIV, VT, Expand);
439 setOperationAction(ISD::SREM, VT, Expand);
440 setOperationAction(ISD::UREM, VT, Expand);
442 // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences.
443 setOperationAction(ISD::ADDC, VT, Custom);
444 setOperationAction(ISD::ADDE, VT, Custom);
445 setOperationAction(ISD::SUBC, VT, Custom);
446 setOperationAction(ISD::SUBE, VT, Custom);
449 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
450 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
451 setOperationAction(ISD::BR_CC , MVT::f32, Expand);
452 setOperationAction(ISD::BR_CC , MVT::f64, Expand);
453 setOperationAction(ISD::BR_CC , MVT::f80, Expand);
454 setOperationAction(ISD::BR_CC , MVT::i8, Expand);
455 setOperationAction(ISD::BR_CC , MVT::i16, Expand);
456 setOperationAction(ISD::BR_CC , MVT::i32, Expand);
457 setOperationAction(ISD::BR_CC , MVT::i64, Expand);
458 setOperationAction(ISD::SELECT_CC , MVT::f32, Expand);
459 setOperationAction(ISD::SELECT_CC , MVT::f64, Expand);
460 setOperationAction(ISD::SELECT_CC , MVT::f80, Expand);
461 setOperationAction(ISD::SELECT_CC , MVT::i8, Expand);
462 setOperationAction(ISD::SELECT_CC , MVT::i16, Expand);
463 setOperationAction(ISD::SELECT_CC , MVT::i32, Expand);
464 setOperationAction(ISD::SELECT_CC , MVT::i64, Expand);
465 if (Subtarget->is64Bit())
466 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
467 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
468 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
469 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
470 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
471 setOperationAction(ISD::FREM , MVT::f32 , Expand);
472 setOperationAction(ISD::FREM , MVT::f64 , Expand);
473 setOperationAction(ISD::FREM , MVT::f80 , Expand);
474 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
476 // Promote the i8 variants and force them on up to i32 which has a shorter
478 setOperationAction(ISD::CTTZ , MVT::i8 , Promote);
479 AddPromotedToType (ISD::CTTZ , MVT::i8 , MVT::i32);
480 setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i8 , Promote);
481 AddPromotedToType (ISD::CTTZ_ZERO_UNDEF , MVT::i8 , MVT::i32);
482 if (Subtarget->hasBMI()) {
483 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16 , Expand);
484 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32 , Expand);
485 if (Subtarget->is64Bit())
486 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
488 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
489 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
490 if (Subtarget->is64Bit())
491 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
494 if (Subtarget->hasLZCNT()) {
495 // When promoting the i8 variants, force them to i32 for a shorter
497 setOperationAction(ISD::CTLZ , MVT::i8 , Promote);
498 AddPromotedToType (ISD::CTLZ , MVT::i8 , MVT::i32);
499 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Promote);
500 AddPromotedToType (ISD::CTLZ_ZERO_UNDEF, MVT::i8 , MVT::i32);
501 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Expand);
502 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Expand);
503 if (Subtarget->is64Bit())
504 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
506 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
507 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
508 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
509 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Custom);
510 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Custom);
511 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Custom);
512 if (Subtarget->is64Bit()) {
513 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
514 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom);
518 // Special handling for half-precision floating point conversions.
519 // If we don't have F16C support, then lower half float conversions
520 // into library calls.
521 if (TM.Options.UseSoftFloat || !Subtarget->hasF16C()) {
522 setOperationAction(ISD::FP16_TO_FP, MVT::f32, Expand);
523 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand);
526 // There's never any support for operations beyond MVT::f32.
527 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand);
528 setOperationAction(ISD::FP16_TO_FP, MVT::f80, Expand);
529 setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand);
530 setOperationAction(ISD::FP_TO_FP16, MVT::f80, Expand);
532 setLoadExtAction(ISD::EXTLOAD, MVT::f16, Expand);
533 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
534 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
535 setTruncStoreAction(MVT::f80, MVT::f16, Expand);
537 if (Subtarget->hasPOPCNT()) {
538 setOperationAction(ISD::CTPOP , MVT::i8 , Promote);
540 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
541 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
542 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
543 if (Subtarget->is64Bit())
544 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
547 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
549 if (!Subtarget->hasMOVBE())
550 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
552 // These should be promoted to a larger select which is supported.
553 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
554 // X86 wants to expand cmov itself.
555 setOperationAction(ISD::SELECT , MVT::i8 , Custom);
556 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
557 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
558 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
559 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
560 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
561 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
562 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
563 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
564 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
565 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
566 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
567 if (Subtarget->is64Bit()) {
568 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
569 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
571 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
572 // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support
573 // SjLj exception handling but a light-weight setjmp/longjmp replacement to
574 // support continuation, user-level threading, and etc.. As a result, no
575 // other SjLj exception interfaces are implemented and please don't build
576 // your own exception handling based on them.
577 // LLVM/Clang supports zero-cost DWARF exception handling.
578 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
579 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
582 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
583 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
584 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
585 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
586 if (Subtarget->is64Bit())
587 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
588 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
589 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom);
590 if (Subtarget->is64Bit()) {
591 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
592 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
593 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
594 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
595 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom);
597 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
598 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
599 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
600 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
601 if (Subtarget->is64Bit()) {
602 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
603 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
604 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
607 if (Subtarget->hasSSE1())
608 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
610 setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom);
612 // Expand certain atomics
613 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
615 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, VT, Custom);
616 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom);
617 setOperationAction(ISD::ATOMIC_STORE, VT, Custom);
620 if (Subtarget->hasCmpxchg16b()) {
621 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, MVT::i128, Custom);
624 // FIXME - use subtarget debug flags
625 if (!Subtarget->isTargetDarwin() && !Subtarget->isTargetELF() &&
626 !Subtarget->isTargetCygMing() && !Subtarget->isTargetWin64()) {
627 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
630 if (Subtarget->is64Bit()) {
631 setExceptionPointerRegister(X86::RAX);
632 setExceptionSelectorRegister(X86::RDX);
634 setExceptionPointerRegister(X86::EAX);
635 setExceptionSelectorRegister(X86::EDX);
637 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
638 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
640 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
641 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
643 setOperationAction(ISD::TRAP, MVT::Other, Legal);
644 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Legal);
646 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
647 setOperationAction(ISD::VASTART , MVT::Other, Custom);
648 setOperationAction(ISD::VAEND , MVT::Other, Expand);
649 if (Subtarget->is64Bit() && !Subtarget->isTargetWin64()) {
650 // TargetInfo::X86_64ABIBuiltinVaList
651 setOperationAction(ISD::VAARG , MVT::Other, Custom);
652 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
654 // TargetInfo::CharPtrBuiltinVaList
655 setOperationAction(ISD::VAARG , MVT::Other, Expand);
656 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
659 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
660 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
662 setOperationAction(ISD::DYNAMIC_STACKALLOC, getPointerTy(), Custom);
664 if (!TM.Options.UseSoftFloat && X86ScalarSSEf64) {
665 // f32 and f64 use SSE.
666 // Set up the FP register classes.
667 addRegisterClass(MVT::f32, &X86::FR32RegClass);
668 addRegisterClass(MVT::f64, &X86::FR64RegClass);
670 // Use ANDPD to simulate FABS.
671 setOperationAction(ISD::FABS , MVT::f64, Custom);
672 setOperationAction(ISD::FABS , MVT::f32, Custom);
674 // Use XORP to simulate FNEG.
675 setOperationAction(ISD::FNEG , MVT::f64, Custom);
676 setOperationAction(ISD::FNEG , MVT::f32, Custom);
678 // Use ANDPD and ORPD to simulate FCOPYSIGN.
679 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
680 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
682 // Lower this to FGETSIGNx86 plus an AND.
683 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom);
684 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom);
686 // We don't support sin/cos/fmod
687 setOperationAction(ISD::FSIN , MVT::f64, Expand);
688 setOperationAction(ISD::FCOS , MVT::f64, Expand);
689 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
690 setOperationAction(ISD::FSIN , MVT::f32, Expand);
691 setOperationAction(ISD::FCOS , MVT::f32, Expand);
692 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
694 // Expand FP immediates into loads from the stack, except for the special
696 addLegalFPImmediate(APFloat(+0.0)); // xorpd
697 addLegalFPImmediate(APFloat(+0.0f)); // xorps
698 } else if (!TM.Options.UseSoftFloat && X86ScalarSSEf32) {
699 // Use SSE for f32, x87 for f64.
700 // Set up the FP register classes.
701 addRegisterClass(MVT::f32, &X86::FR32RegClass);
702 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
704 // Use ANDPS to simulate FABS.
705 setOperationAction(ISD::FABS , MVT::f32, Custom);
707 // Use XORP to simulate FNEG.
708 setOperationAction(ISD::FNEG , MVT::f32, Custom);
710 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
712 // Use ANDPS and ORPS to simulate FCOPYSIGN.
713 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
714 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
716 // We don't support sin/cos/fmod
717 setOperationAction(ISD::FSIN , MVT::f32, Expand);
718 setOperationAction(ISD::FCOS , MVT::f32, Expand);
719 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
721 // Special cases we handle for FP constants.
722 addLegalFPImmediate(APFloat(+0.0f)); // xorps
723 addLegalFPImmediate(APFloat(+0.0)); // FLD0
724 addLegalFPImmediate(APFloat(+1.0)); // FLD1
725 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
726 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
728 if (!TM.Options.UnsafeFPMath) {
729 setOperationAction(ISD::FSIN , MVT::f64, Expand);
730 setOperationAction(ISD::FCOS , MVT::f64, Expand);
731 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
733 } else if (!TM.Options.UseSoftFloat) {
734 // f32 and f64 in x87.
735 // Set up the FP register classes.
736 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
737 addRegisterClass(MVT::f32, &X86::RFP32RegClass);
739 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
740 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
741 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
742 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
744 if (!TM.Options.UnsafeFPMath) {
745 setOperationAction(ISD::FSIN , MVT::f64, Expand);
746 setOperationAction(ISD::FSIN , MVT::f32, Expand);
747 setOperationAction(ISD::FCOS , MVT::f64, Expand);
748 setOperationAction(ISD::FCOS , MVT::f32, Expand);
749 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
750 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
752 addLegalFPImmediate(APFloat(+0.0)); // FLD0
753 addLegalFPImmediate(APFloat(+1.0)); // FLD1
754 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
755 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
756 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
757 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
758 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
759 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
762 // We don't support FMA.
763 setOperationAction(ISD::FMA, MVT::f64, Expand);
764 setOperationAction(ISD::FMA, MVT::f32, Expand);
766 // Long double always uses X87.
767 if (!TM.Options.UseSoftFloat) {
768 addRegisterClass(MVT::f80, &X86::RFP80RegClass);
769 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
770 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
772 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended);
773 addLegalFPImmediate(TmpFlt); // FLD0
775 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
778 APFloat TmpFlt2(+1.0);
779 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
781 addLegalFPImmediate(TmpFlt2); // FLD1
782 TmpFlt2.changeSign();
783 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
786 if (!TM.Options.UnsafeFPMath) {
787 setOperationAction(ISD::FSIN , MVT::f80, Expand);
788 setOperationAction(ISD::FCOS , MVT::f80, Expand);
789 setOperationAction(ISD::FSINCOS, MVT::f80, Expand);
792 setOperationAction(ISD::FFLOOR, MVT::f80, Expand);
793 setOperationAction(ISD::FCEIL, MVT::f80, Expand);
794 setOperationAction(ISD::FTRUNC, MVT::f80, Expand);
795 setOperationAction(ISD::FRINT, MVT::f80, Expand);
796 setOperationAction(ISD::FNEARBYINT, MVT::f80, Expand);
797 setOperationAction(ISD::FMA, MVT::f80, Expand);
800 // Always use a library call for pow.
801 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
802 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
803 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
805 setOperationAction(ISD::FLOG, MVT::f80, Expand);
806 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
807 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
808 setOperationAction(ISD::FEXP, MVT::f80, Expand);
809 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
811 // First set operation action for all vector types to either promote
812 // (for widening) or expand (for scalarization). Then we will selectively
813 // turn on ones that can be effectively codegen'd.
814 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
815 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
816 MVT VT = (MVT::SimpleValueType)i;
817 setOperationAction(ISD::ADD , VT, Expand);
818 setOperationAction(ISD::SUB , VT, Expand);
819 setOperationAction(ISD::FADD, VT, Expand);
820 setOperationAction(ISD::FNEG, VT, Expand);
821 setOperationAction(ISD::FSUB, VT, Expand);
822 setOperationAction(ISD::MUL , VT, Expand);
823 setOperationAction(ISD::FMUL, VT, Expand);
824 setOperationAction(ISD::SDIV, VT, Expand);
825 setOperationAction(ISD::UDIV, VT, Expand);
826 setOperationAction(ISD::FDIV, VT, Expand);
827 setOperationAction(ISD::SREM, VT, Expand);
828 setOperationAction(ISD::UREM, VT, Expand);
829 setOperationAction(ISD::LOAD, VT, Expand);
830 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);
831 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT,Expand);
832 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
833 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT,Expand);
834 setOperationAction(ISD::INSERT_SUBVECTOR, VT,Expand);
835 setOperationAction(ISD::FABS, VT, Expand);
836 setOperationAction(ISD::FSIN, VT, Expand);
837 setOperationAction(ISD::FSINCOS, VT, Expand);
838 setOperationAction(ISD::FCOS, VT, Expand);
839 setOperationAction(ISD::FSINCOS, VT, Expand);
840 setOperationAction(ISD::FREM, VT, Expand);
841 setOperationAction(ISD::FMA, VT, Expand);
842 setOperationAction(ISD::FPOWI, VT, Expand);
843 setOperationAction(ISD::FSQRT, VT, Expand);
844 setOperationAction(ISD::FCOPYSIGN, VT, Expand);
845 setOperationAction(ISD::FFLOOR, VT, Expand);
846 setOperationAction(ISD::FCEIL, VT, Expand);
847 setOperationAction(ISD::FTRUNC, VT, Expand);
848 setOperationAction(ISD::FRINT, VT, Expand);
849 setOperationAction(ISD::FNEARBYINT, VT, Expand);
850 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
851 setOperationAction(ISD::MULHS, VT, Expand);
852 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
853 setOperationAction(ISD::MULHU, VT, Expand);
854 setOperationAction(ISD::SDIVREM, VT, Expand);
855 setOperationAction(ISD::UDIVREM, VT, Expand);
856 setOperationAction(ISD::FPOW, VT, Expand);
857 setOperationAction(ISD::CTPOP, VT, Expand);
858 setOperationAction(ISD::CTTZ, VT, Expand);
859 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
860 setOperationAction(ISD::CTLZ, VT, Expand);
861 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
862 setOperationAction(ISD::SHL, VT, Expand);
863 setOperationAction(ISD::SRA, VT, Expand);
864 setOperationAction(ISD::SRL, VT, Expand);
865 setOperationAction(ISD::ROTL, VT, Expand);
866 setOperationAction(ISD::ROTR, VT, Expand);
867 setOperationAction(ISD::BSWAP, VT, Expand);
868 setOperationAction(ISD::SETCC, VT, Expand);
869 setOperationAction(ISD::FLOG, VT, Expand);
870 setOperationAction(ISD::FLOG2, VT, Expand);
871 setOperationAction(ISD::FLOG10, VT, Expand);
872 setOperationAction(ISD::FEXP, VT, Expand);
873 setOperationAction(ISD::FEXP2, VT, Expand);
874 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
875 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
876 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
877 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
878 setOperationAction(ISD::SIGN_EXTEND_INREG, VT,Expand);
879 setOperationAction(ISD::TRUNCATE, VT, Expand);
880 setOperationAction(ISD::SIGN_EXTEND, VT, Expand);
881 setOperationAction(ISD::ZERO_EXTEND, VT, Expand);
882 setOperationAction(ISD::ANY_EXTEND, VT, Expand);
883 setOperationAction(ISD::VSELECT, VT, Expand);
884 setOperationAction(ISD::SELECT_CC, VT, Expand);
885 for (int InnerVT = MVT::FIRST_VECTOR_VALUETYPE;
886 InnerVT <= MVT::LAST_VECTOR_VALUETYPE; ++InnerVT)
887 setTruncStoreAction(VT,
888 (MVT::SimpleValueType)InnerVT, Expand);
889 setLoadExtAction(ISD::SEXTLOAD, VT, Expand);
890 setLoadExtAction(ISD::ZEXTLOAD, VT, Expand);
892 // N.b. ISD::EXTLOAD legality is basically ignored except for i1-like types,
893 // we have to deal with them whether we ask for Expansion or not. Setting
894 // Expand causes its own optimisation problems though, so leave them legal.
895 if (VT.getVectorElementType() == MVT::i1)
896 setLoadExtAction(ISD::EXTLOAD, VT, Expand);
899 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
900 // with -msoft-float, disable use of MMX as well.
901 if (!TM.Options.UseSoftFloat && Subtarget->hasMMX()) {
902 addRegisterClass(MVT::x86mmx, &X86::VR64RegClass);
903 // No operations on x86mmx supported, everything uses intrinsics.
906 // MMX-sized vectors (other than x86mmx) are expected to be expanded
907 // into smaller operations.
908 setOperationAction(ISD::MULHS, MVT::v8i8, Expand);
909 setOperationAction(ISD::MULHS, MVT::v4i16, Expand);
910 setOperationAction(ISD::MULHS, MVT::v2i32, Expand);
911 setOperationAction(ISD::MULHS, MVT::v1i64, Expand);
912 setOperationAction(ISD::AND, MVT::v8i8, Expand);
913 setOperationAction(ISD::AND, MVT::v4i16, Expand);
914 setOperationAction(ISD::AND, MVT::v2i32, Expand);
915 setOperationAction(ISD::AND, MVT::v1i64, Expand);
916 setOperationAction(ISD::OR, MVT::v8i8, Expand);
917 setOperationAction(ISD::OR, MVT::v4i16, Expand);
918 setOperationAction(ISD::OR, MVT::v2i32, Expand);
919 setOperationAction(ISD::OR, MVT::v1i64, Expand);
920 setOperationAction(ISD::XOR, MVT::v8i8, Expand);
921 setOperationAction(ISD::XOR, MVT::v4i16, Expand);
922 setOperationAction(ISD::XOR, MVT::v2i32, Expand);
923 setOperationAction(ISD::XOR, MVT::v1i64, Expand);
924 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Expand);
925 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Expand);
926 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i32, Expand);
927 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Expand);
928 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand);
929 setOperationAction(ISD::SELECT, MVT::v8i8, Expand);
930 setOperationAction(ISD::SELECT, MVT::v4i16, Expand);
931 setOperationAction(ISD::SELECT, MVT::v2i32, Expand);
932 setOperationAction(ISD::SELECT, MVT::v1i64, Expand);
933 setOperationAction(ISD::BITCAST, MVT::v8i8, Expand);
934 setOperationAction(ISD::BITCAST, MVT::v4i16, Expand);
935 setOperationAction(ISD::BITCAST, MVT::v2i32, Expand);
936 setOperationAction(ISD::BITCAST, MVT::v1i64, Expand);
938 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE1()) {
939 addRegisterClass(MVT::v4f32, &X86::VR128RegClass);
941 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
942 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
943 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
944 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
945 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
946 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
947 setOperationAction(ISD::FABS, MVT::v4f32, Custom);
948 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
949 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
950 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
951 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
952 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
955 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE2()) {
956 addRegisterClass(MVT::v2f64, &X86::VR128RegClass);
958 // FIXME: Unfortunately -soft-float and -no-implicit-float means XMM
959 // registers cannot be used even for integer operations.
960 addRegisterClass(MVT::v16i8, &X86::VR128RegClass);
961 addRegisterClass(MVT::v8i16, &X86::VR128RegClass);
962 addRegisterClass(MVT::v4i32, &X86::VR128RegClass);
963 addRegisterClass(MVT::v2i64, &X86::VR128RegClass);
965 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
966 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
967 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
968 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
969 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
970 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
971 setOperationAction(ISD::UMUL_LOHI, MVT::v4i32, Custom);
972 setOperationAction(ISD::SMUL_LOHI, MVT::v4i32, Custom);
973 setOperationAction(ISD::MULHU, MVT::v8i16, Legal);
974 setOperationAction(ISD::MULHS, MVT::v8i16, Legal);
975 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
976 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
977 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
978 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
979 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
980 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
981 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
982 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
983 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
984 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
985 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
986 setOperationAction(ISD::FABS, MVT::v2f64, Custom);
988 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
989 setOperationAction(ISD::SETCC, MVT::v16i8, Custom);
990 setOperationAction(ISD::SETCC, MVT::v8i16, Custom);
991 setOperationAction(ISD::SETCC, MVT::v4i32, Custom);
993 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
994 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
995 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
996 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
997 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
999 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
1000 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
1001 MVT VT = (MVT::SimpleValueType)i;
1002 // Do not attempt to custom lower non-power-of-2 vectors
1003 if (!isPowerOf2_32(VT.getVectorNumElements()))
1005 // Do not attempt to custom lower non-128-bit vectors
1006 if (!VT.is128BitVector())
1008 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1009 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1010 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1013 // We support custom legalizing of sext and anyext loads for specific
1014 // memory vector types which we can load as a scalar (or sequence of
1015 // scalars) and extend in-register to a legal 128-bit vector type. For sext
1016 // loads these must work with a single scalar load.
1017 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i8, Custom);
1018 if (Subtarget->is64Bit()) {
1019 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i16, Custom);
1020 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i8, Custom);
1022 setLoadExtAction(ISD::EXTLOAD, MVT::v2i8, Custom);
1023 setLoadExtAction(ISD::EXTLOAD, MVT::v2i16, Custom);
1024 setLoadExtAction(ISD::EXTLOAD, MVT::v2i32, Custom);
1025 setLoadExtAction(ISD::EXTLOAD, MVT::v4i8, Custom);
1026 setLoadExtAction(ISD::EXTLOAD, MVT::v4i16, Custom);
1027 setLoadExtAction(ISD::EXTLOAD, MVT::v8i8, Custom);
1029 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
1030 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
1031 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
1032 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
1033 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
1034 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
1036 if (Subtarget->is64Bit()) {
1037 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
1038 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
1041 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
1042 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
1043 MVT VT = (MVT::SimpleValueType)i;
1045 // Do not attempt to promote non-128-bit vectors
1046 if (!VT.is128BitVector())
1049 setOperationAction(ISD::AND, VT, Promote);
1050 AddPromotedToType (ISD::AND, VT, MVT::v2i64);
1051 setOperationAction(ISD::OR, VT, Promote);
1052 AddPromotedToType (ISD::OR, VT, MVT::v2i64);
1053 setOperationAction(ISD::XOR, VT, Promote);
1054 AddPromotedToType (ISD::XOR, VT, MVT::v2i64);
1055 setOperationAction(ISD::LOAD, VT, Promote);
1056 AddPromotedToType (ISD::LOAD, VT, MVT::v2i64);
1057 setOperationAction(ISD::SELECT, VT, Promote);
1058 AddPromotedToType (ISD::SELECT, VT, MVT::v2i64);
1061 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
1063 // Custom lower v2i64 and v2f64 selects.
1064 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
1065 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
1066 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
1067 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
1069 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
1070 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
1072 setOperationAction(ISD::UINT_TO_FP, MVT::v4i8, Custom);
1073 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);
1074 // As there is no 64-bit GPR available, we need build a special custom
1075 // sequence to convert from v2i32 to v2f32.
1076 if (!Subtarget->is64Bit())
1077 setOperationAction(ISD::UINT_TO_FP, MVT::v2f32, Custom);
1079 setOperationAction(ISD::FP_EXTEND, MVT::v2f32, Custom);
1080 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Custom);
1082 setLoadExtAction(ISD::EXTLOAD, MVT::v2f32, Legal);
1084 setOperationAction(ISD::BITCAST, MVT::v2i32, Custom);
1085 setOperationAction(ISD::BITCAST, MVT::v4i16, Custom);
1086 setOperationAction(ISD::BITCAST, MVT::v8i8, Custom);
1089 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE41()) {
1090 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
1091 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
1092 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
1093 setOperationAction(ISD::FRINT, MVT::f32, Legal);
1094 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
1095 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
1096 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
1097 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
1098 setOperationAction(ISD::FRINT, MVT::f64, Legal);
1099 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
1101 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal);
1102 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal);
1103 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal);
1104 setOperationAction(ISD::FRINT, MVT::v4f32, Legal);
1105 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal);
1106 setOperationAction(ISD::FFLOOR, MVT::v2f64, Legal);
1107 setOperationAction(ISD::FCEIL, MVT::v2f64, Legal);
1108 setOperationAction(ISD::FTRUNC, MVT::v2f64, Legal);
1109 setOperationAction(ISD::FRINT, MVT::v2f64, Legal);
1110 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Legal);
1112 // FIXME: Do we need to handle scalar-to-vector here?
1113 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
1115 setOperationAction(ISD::VSELECT, MVT::v2f64, Custom);
1116 setOperationAction(ISD::VSELECT, MVT::v2i64, Custom);
1117 setOperationAction(ISD::VSELECT, MVT::v4i32, Custom);
1118 setOperationAction(ISD::VSELECT, MVT::v4f32, Custom);
1119 setOperationAction(ISD::VSELECT, MVT::v8i16, Custom);
1120 // There is no BLENDI for byte vectors. We don't need to custom lower
1121 // some vselects for now.
1122 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
1124 // SSE41 brings specific instructions for doing vector sign extend even in
1125 // cases where we don't have SRA.
1126 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i8, Custom);
1127 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i16, Custom);
1128 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i32, Custom);
1130 // i8 and i16 vectors are custom because the source register and source
1131 // source memory operand types are not the same width. f32 vectors are
1132 // custom since the immediate controlling the insert encodes additional
1134 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
1135 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
1136 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
1137 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
1139 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
1140 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
1141 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
1142 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
1144 // FIXME: these should be Legal, but that's only for the case where
1145 // the index is constant. For now custom expand to deal with that.
1146 if (Subtarget->is64Bit()) {
1147 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
1148 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
1152 if (Subtarget->hasSSE2()) {
1153 setOperationAction(ISD::SRL, MVT::v8i16, Custom);
1154 setOperationAction(ISD::SRL, MVT::v16i8, Custom);
1156 setOperationAction(ISD::SHL, MVT::v8i16, Custom);
1157 setOperationAction(ISD::SHL, MVT::v16i8, Custom);
1159 setOperationAction(ISD::SRA, MVT::v8i16, Custom);
1160 setOperationAction(ISD::SRA, MVT::v16i8, Custom);
1162 // In the customized shift lowering, the legal cases in AVX2 will be
1164 setOperationAction(ISD::SRL, MVT::v2i64, Custom);
1165 setOperationAction(ISD::SRL, MVT::v4i32, Custom);
1167 setOperationAction(ISD::SHL, MVT::v2i64, Custom);
1168 setOperationAction(ISD::SHL, MVT::v4i32, Custom);
1170 setOperationAction(ISD::SRA, MVT::v4i32, Custom);
1173 if (!TM.Options.UseSoftFloat && Subtarget->hasFp256()) {
1174 addRegisterClass(MVT::v32i8, &X86::VR256RegClass);
1175 addRegisterClass(MVT::v16i16, &X86::VR256RegClass);
1176 addRegisterClass(MVT::v8i32, &X86::VR256RegClass);
1177 addRegisterClass(MVT::v8f32, &X86::VR256RegClass);
1178 addRegisterClass(MVT::v4i64, &X86::VR256RegClass);
1179 addRegisterClass(MVT::v4f64, &X86::VR256RegClass);
1181 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
1182 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
1183 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
1185 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
1186 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
1187 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
1188 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
1189 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
1190 setOperationAction(ISD::FFLOOR, MVT::v8f32, Legal);
1191 setOperationAction(ISD::FCEIL, MVT::v8f32, Legal);
1192 setOperationAction(ISD::FTRUNC, MVT::v8f32, Legal);
1193 setOperationAction(ISD::FRINT, MVT::v8f32, Legal);
1194 setOperationAction(ISD::FNEARBYINT, MVT::v8f32, Legal);
1195 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
1196 setOperationAction(ISD::FABS, MVT::v8f32, Custom);
1198 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
1199 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
1200 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
1201 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
1202 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
1203 setOperationAction(ISD::FFLOOR, MVT::v4f64, Legal);
1204 setOperationAction(ISD::FCEIL, MVT::v4f64, Legal);
1205 setOperationAction(ISD::FTRUNC, MVT::v4f64, Legal);
1206 setOperationAction(ISD::FRINT, MVT::v4f64, Legal);
1207 setOperationAction(ISD::FNEARBYINT, MVT::v4f64, Legal);
1208 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
1209 setOperationAction(ISD::FABS, MVT::v4f64, Custom);
1211 // (fp_to_int:v8i16 (v8f32 ..)) requires the result type to be promoted
1212 // even though v8i16 is a legal type.
1213 setOperationAction(ISD::FP_TO_SINT, MVT::v8i16, Promote);
1214 setOperationAction(ISD::FP_TO_UINT, MVT::v8i16, Promote);
1215 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
1217 setOperationAction(ISD::SINT_TO_FP, MVT::v8i16, Promote);
1218 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
1219 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal);
1221 setOperationAction(ISD::UINT_TO_FP, MVT::v8i8, Custom);
1222 setOperationAction(ISD::UINT_TO_FP, MVT::v8i16, Custom);
1224 setLoadExtAction(ISD::EXTLOAD, MVT::v4f32, Legal);
1226 setOperationAction(ISD::SRL, MVT::v16i16, Custom);
1227 setOperationAction(ISD::SRL, MVT::v32i8, Custom);
1229 setOperationAction(ISD::SHL, MVT::v16i16, Custom);
1230 setOperationAction(ISD::SHL, MVT::v32i8, Custom);
1232 setOperationAction(ISD::SRA, MVT::v16i16, Custom);
1233 setOperationAction(ISD::SRA, MVT::v32i8, Custom);
1235 setOperationAction(ISD::SETCC, MVT::v32i8, Custom);
1236 setOperationAction(ISD::SETCC, MVT::v16i16, Custom);
1237 setOperationAction(ISD::SETCC, MVT::v8i32, Custom);
1238 setOperationAction(ISD::SETCC, MVT::v4i64, Custom);
1240 setOperationAction(ISD::SELECT, MVT::v4f64, Custom);
1241 setOperationAction(ISD::SELECT, MVT::v4i64, Custom);
1242 setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
1244 setOperationAction(ISD::VSELECT, MVT::v4f64, Custom);
1245 setOperationAction(ISD::VSELECT, MVT::v4i64, Custom);
1246 setOperationAction(ISD::VSELECT, MVT::v8i32, Custom);
1247 setOperationAction(ISD::VSELECT, MVT::v8f32, Custom);
1249 setOperationAction(ISD::SIGN_EXTEND, MVT::v4i64, Custom);
1250 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i32, Custom);
1251 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1252 setOperationAction(ISD::ZERO_EXTEND, MVT::v4i64, Custom);
1253 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i32, Custom);
1254 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i16, Custom);
1255 setOperationAction(ISD::ANY_EXTEND, MVT::v4i64, Custom);
1256 setOperationAction(ISD::ANY_EXTEND, MVT::v8i32, Custom);
1257 setOperationAction(ISD::ANY_EXTEND, MVT::v16i16, Custom);
1258 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1259 setOperationAction(ISD::TRUNCATE, MVT::v8i16, Custom);
1260 setOperationAction(ISD::TRUNCATE, MVT::v4i32, Custom);
1262 if (Subtarget->hasFMA() || Subtarget->hasFMA4()) {
1263 setOperationAction(ISD::FMA, MVT::v8f32, Legal);
1264 setOperationAction(ISD::FMA, MVT::v4f64, Legal);
1265 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
1266 setOperationAction(ISD::FMA, MVT::v2f64, Legal);
1267 setOperationAction(ISD::FMA, MVT::f32, Legal);
1268 setOperationAction(ISD::FMA, MVT::f64, Legal);
1271 if (Subtarget->hasInt256()) {
1272 setOperationAction(ISD::ADD, MVT::v4i64, Legal);
1273 setOperationAction(ISD::ADD, MVT::v8i32, Legal);
1274 setOperationAction(ISD::ADD, MVT::v16i16, Legal);
1275 setOperationAction(ISD::ADD, MVT::v32i8, Legal);
1277 setOperationAction(ISD::SUB, MVT::v4i64, Legal);
1278 setOperationAction(ISD::SUB, MVT::v8i32, Legal);
1279 setOperationAction(ISD::SUB, MVT::v16i16, Legal);
1280 setOperationAction(ISD::SUB, MVT::v32i8, Legal);
1282 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1283 setOperationAction(ISD::MUL, MVT::v8i32, Legal);
1284 setOperationAction(ISD::MUL, MVT::v16i16, Legal);
1285 // Don't lower v32i8 because there is no 128-bit byte mul
1287 setOperationAction(ISD::UMUL_LOHI, MVT::v8i32, Custom);
1288 setOperationAction(ISD::SMUL_LOHI, MVT::v8i32, Custom);
1289 setOperationAction(ISD::MULHU, MVT::v16i16, Legal);
1290 setOperationAction(ISD::MULHS, MVT::v16i16, Legal);
1292 setOperationAction(ISD::VSELECT, MVT::v16i16, Custom);
1293 setOperationAction(ISD::VSELECT, MVT::v32i8, Legal);
1295 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
1296 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
1297 setOperationAction(ISD::ADD, MVT::v16i16, Custom);
1298 setOperationAction(ISD::ADD, MVT::v32i8, Custom);
1300 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
1301 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
1302 setOperationAction(ISD::SUB, MVT::v16i16, Custom);
1303 setOperationAction(ISD::SUB, MVT::v32i8, Custom);
1305 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1306 setOperationAction(ISD::MUL, MVT::v8i32, Custom);
1307 setOperationAction(ISD::MUL, MVT::v16i16, Custom);
1308 // Don't lower v32i8 because there is no 128-bit byte mul
1311 // In the customized shift lowering, the legal cases in AVX2 will be
1313 setOperationAction(ISD::SRL, MVT::v4i64, Custom);
1314 setOperationAction(ISD::SRL, MVT::v8i32, Custom);
1316 setOperationAction(ISD::SHL, MVT::v4i64, Custom);
1317 setOperationAction(ISD::SHL, MVT::v8i32, Custom);
1319 setOperationAction(ISD::SRA, MVT::v8i32, Custom);
1321 // Custom lower several nodes for 256-bit types.
1322 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
1323 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
1324 MVT VT = (MVT::SimpleValueType)i;
1326 // Extract subvector is special because the value type
1327 // (result) is 128-bit but the source is 256-bit wide.
1328 if (VT.is128BitVector())
1329 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1331 // Do not attempt to custom lower other non-256-bit vectors
1332 if (!VT.is256BitVector())
1335 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1336 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1337 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1338 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1339 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1340 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1341 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom);
1344 // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64.
1345 for (int i = MVT::v32i8; i != MVT::v4i64; ++i) {
1346 MVT VT = (MVT::SimpleValueType)i;
1348 // Do not attempt to promote non-256-bit vectors
1349 if (!VT.is256BitVector())
1352 setOperationAction(ISD::AND, VT, Promote);
1353 AddPromotedToType (ISD::AND, VT, MVT::v4i64);
1354 setOperationAction(ISD::OR, VT, Promote);
1355 AddPromotedToType (ISD::OR, VT, MVT::v4i64);
1356 setOperationAction(ISD::XOR, VT, Promote);
1357 AddPromotedToType (ISD::XOR, VT, MVT::v4i64);
1358 setOperationAction(ISD::LOAD, VT, Promote);
1359 AddPromotedToType (ISD::LOAD, VT, MVT::v4i64);
1360 setOperationAction(ISD::SELECT, VT, Promote);
1361 AddPromotedToType (ISD::SELECT, VT, MVT::v4i64);
1365 if (!TM.Options.UseSoftFloat && Subtarget->hasAVX512()) {
1366 addRegisterClass(MVT::v16i32, &X86::VR512RegClass);
1367 addRegisterClass(MVT::v16f32, &X86::VR512RegClass);
1368 addRegisterClass(MVT::v8i64, &X86::VR512RegClass);
1369 addRegisterClass(MVT::v8f64, &X86::VR512RegClass);
1371 addRegisterClass(MVT::i1, &X86::VK1RegClass);
1372 addRegisterClass(MVT::v8i1, &X86::VK8RegClass);
1373 addRegisterClass(MVT::v16i1, &X86::VK16RegClass);
1375 setOperationAction(ISD::BR_CC, MVT::i1, Expand);
1376 setOperationAction(ISD::SETCC, MVT::i1, Custom);
1377 setOperationAction(ISD::XOR, MVT::i1, Legal);
1378 setOperationAction(ISD::OR, MVT::i1, Legal);
1379 setOperationAction(ISD::AND, MVT::i1, Legal);
1380 setLoadExtAction(ISD::EXTLOAD, MVT::v8f32, Legal);
1381 setOperationAction(ISD::LOAD, MVT::v16f32, Legal);
1382 setOperationAction(ISD::LOAD, MVT::v8f64, Legal);
1383 setOperationAction(ISD::LOAD, MVT::v8i64, Legal);
1384 setOperationAction(ISD::LOAD, MVT::v16i32, Legal);
1385 setOperationAction(ISD::LOAD, MVT::v16i1, Legal);
1387 setOperationAction(ISD::FADD, MVT::v16f32, Legal);
1388 setOperationAction(ISD::FSUB, MVT::v16f32, Legal);
1389 setOperationAction(ISD::FMUL, MVT::v16f32, Legal);
1390 setOperationAction(ISD::FDIV, MVT::v16f32, Legal);
1391 setOperationAction(ISD::FSQRT, MVT::v16f32, Legal);
1392 setOperationAction(ISD::FNEG, MVT::v16f32, Custom);
1394 setOperationAction(ISD::FADD, MVT::v8f64, Legal);
1395 setOperationAction(ISD::FSUB, MVT::v8f64, Legal);
1396 setOperationAction(ISD::FMUL, MVT::v8f64, Legal);
1397 setOperationAction(ISD::FDIV, MVT::v8f64, Legal);
1398 setOperationAction(ISD::FSQRT, MVT::v8f64, Legal);
1399 setOperationAction(ISD::FNEG, MVT::v8f64, Custom);
1400 setOperationAction(ISD::FMA, MVT::v8f64, Legal);
1401 setOperationAction(ISD::FMA, MVT::v16f32, Legal);
1403 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Legal);
1404 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Legal);
1405 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Legal);
1406 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Legal);
1407 if (Subtarget->is64Bit()) {
1408 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Legal);
1409 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Legal);
1410 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Legal);
1411 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Legal);
1413 setOperationAction(ISD::FP_TO_SINT, MVT::v16i32, Legal);
1414 setOperationAction(ISD::FP_TO_UINT, MVT::v16i32, Legal);
1415 setOperationAction(ISD::FP_TO_UINT, MVT::v8i32, Legal);
1416 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
1417 setOperationAction(ISD::SINT_TO_FP, MVT::v16i32, Legal);
1418 setOperationAction(ISD::UINT_TO_FP, MVT::v16i32, Legal);
1419 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Legal);
1420 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
1421 setOperationAction(ISD::FP_ROUND, MVT::v8f32, Legal);
1422 setOperationAction(ISD::FP_EXTEND, MVT::v8f32, Legal);
1424 setOperationAction(ISD::TRUNCATE, MVT::i1, Custom);
1425 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1426 setOperationAction(ISD::TRUNCATE, MVT::v8i32, Custom);
1427 setOperationAction(ISD::TRUNCATE, MVT::v8i1, Custom);
1428 setOperationAction(ISD::TRUNCATE, MVT::v16i1, Custom);
1429 setOperationAction(ISD::TRUNCATE, MVT::v16i16, Custom);
1430 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i32, Custom);
1431 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i64, Custom);
1432 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i32, Custom);
1433 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i64, Custom);
1434 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i8, Custom);
1435 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i16, Custom);
1436 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1438 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f64, Custom);
1439 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i64, Custom);
1440 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16f32, Custom);
1441 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i32, Custom);
1442 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i1, Custom);
1443 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i1, Legal);
1445 setOperationAction(ISD::SETCC, MVT::v16i1, Custom);
1446 setOperationAction(ISD::SETCC, MVT::v8i1, Custom);
1448 setOperationAction(ISD::MUL, MVT::v8i64, Custom);
1450 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i1, Custom);
1451 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i1, Custom);
1452 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i1, Custom);
1453 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i1, Custom);
1454 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i1, Custom);
1455 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i1, Custom);
1456 setOperationAction(ISD::SELECT, MVT::v8f64, Custom);
1457 setOperationAction(ISD::SELECT, MVT::v8i64, Custom);
1458 setOperationAction(ISD::SELECT, MVT::v16f32, Custom);
1460 setOperationAction(ISD::ADD, MVT::v8i64, Legal);
1461 setOperationAction(ISD::ADD, MVT::v16i32, Legal);
1463 setOperationAction(ISD::SUB, MVT::v8i64, Legal);
1464 setOperationAction(ISD::SUB, MVT::v16i32, Legal);
1466 setOperationAction(ISD::MUL, MVT::v16i32, Legal);
1468 setOperationAction(ISD::SRL, MVT::v8i64, Custom);
1469 setOperationAction(ISD::SRL, MVT::v16i32, Custom);
1471 setOperationAction(ISD::SHL, MVT::v8i64, Custom);
1472 setOperationAction(ISD::SHL, MVT::v16i32, Custom);
1474 setOperationAction(ISD::SRA, MVT::v8i64, Custom);
1475 setOperationAction(ISD::SRA, MVT::v16i32, Custom);
1477 setOperationAction(ISD::AND, MVT::v8i64, Legal);
1478 setOperationAction(ISD::OR, MVT::v8i64, Legal);
1479 setOperationAction(ISD::XOR, MVT::v8i64, Legal);
1480 setOperationAction(ISD::AND, MVT::v16i32, Legal);
1481 setOperationAction(ISD::OR, MVT::v16i32, Legal);
1482 setOperationAction(ISD::XOR, MVT::v16i32, Legal);
1484 if (Subtarget->hasCDI()) {
1485 setOperationAction(ISD::CTLZ, MVT::v8i64, Legal);
1486 setOperationAction(ISD::CTLZ, MVT::v16i32, Legal);
1489 // Custom lower several nodes.
1490 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
1491 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
1492 MVT VT = (MVT::SimpleValueType)i;
1494 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1495 // Extract subvector is special because the value type
1496 // (result) is 256/128-bit but the source is 512-bit wide.
1497 if (VT.is128BitVector() || VT.is256BitVector())
1498 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1500 if (VT.getVectorElementType() == MVT::i1)
1501 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal);
1503 // Do not attempt to custom lower other non-512-bit vectors
1504 if (!VT.is512BitVector())
1507 if ( EltSize >= 32) {
1508 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1509 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1510 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1511 setOperationAction(ISD::VSELECT, VT, Legal);
1512 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1513 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1514 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1517 for (int i = MVT::v32i8; i != MVT::v8i64; ++i) {
1518 MVT VT = (MVT::SimpleValueType)i;
1520 // Do not attempt to promote non-256-bit vectors
1521 if (!VT.is512BitVector())
1524 setOperationAction(ISD::SELECT, VT, Promote);
1525 AddPromotedToType (ISD::SELECT, VT, MVT::v8i64);
1529 if (!TM.Options.UseSoftFloat && Subtarget->hasBWI()) {
1530 addRegisterClass(MVT::v32i1, &X86::VK32RegClass);
1531 addRegisterClass(MVT::v64i1, &X86::VK64RegClass);
1534 // SIGN_EXTEND_INREGs are evaluated by the extend type. Handle the expansion
1535 // of this type with custom code.
1536 for (int VT = MVT::FIRST_VECTOR_VALUETYPE;
1537 VT != MVT::LAST_VECTOR_VALUETYPE; VT++) {
1538 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,
1542 // We want to custom lower some of our intrinsics.
1543 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
1544 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
1545 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
1546 if (!Subtarget->is64Bit())
1547 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i64, Custom);
1549 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't
1550 // handle type legalization for these operations here.
1552 // FIXME: We really should do custom legalization for addition and
1553 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better
1554 // than generic legalization for 64-bit multiplication-with-overflow, though.
1555 for (unsigned i = 0, e = 3+Subtarget->is64Bit(); i != e; ++i) {
1556 // Add/Sub/Mul with overflow operations are custom lowered.
1558 setOperationAction(ISD::SADDO, VT, Custom);
1559 setOperationAction(ISD::UADDO, VT, Custom);
1560 setOperationAction(ISD::SSUBO, VT, Custom);
1561 setOperationAction(ISD::USUBO, VT, Custom);
1562 setOperationAction(ISD::SMULO, VT, Custom);
1563 setOperationAction(ISD::UMULO, VT, Custom);
1566 // There are no 8-bit 3-address imul/mul instructions
1567 setOperationAction(ISD::SMULO, MVT::i8, Expand);
1568 setOperationAction(ISD::UMULO, MVT::i8, Expand);
1570 if (!Subtarget->is64Bit()) {
1571 // These libcalls are not available in 32-bit.
1572 setLibcallName(RTLIB::SHL_I128, nullptr);
1573 setLibcallName(RTLIB::SRL_I128, nullptr);
1574 setLibcallName(RTLIB::SRA_I128, nullptr);
1577 // Combine sin / cos into one node or libcall if possible.
1578 if (Subtarget->hasSinCos()) {
1579 setLibcallName(RTLIB::SINCOS_F32, "sincosf");
1580 setLibcallName(RTLIB::SINCOS_F64, "sincos");
1581 if (Subtarget->isTargetDarwin()) {
1582 // For MacOSX, we don't want to the normal expansion of a libcall to
1583 // sincos. We want to issue a libcall to __sincos_stret to avoid memory
1585 setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
1586 setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
1590 if (Subtarget->isTargetWin64()) {
1591 setOperationAction(ISD::SDIV, MVT::i128, Custom);
1592 setOperationAction(ISD::UDIV, MVT::i128, Custom);
1593 setOperationAction(ISD::SREM, MVT::i128, Custom);
1594 setOperationAction(ISD::UREM, MVT::i128, Custom);
1595 setOperationAction(ISD::SDIVREM, MVT::i128, Custom);
1596 setOperationAction(ISD::UDIVREM, MVT::i128, Custom);
1599 // We have target-specific dag combine patterns for the following nodes:
1600 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
1601 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
1602 setTargetDAGCombine(ISD::VSELECT);
1603 setTargetDAGCombine(ISD::SELECT);
1604 setTargetDAGCombine(ISD::SHL);
1605 setTargetDAGCombine(ISD::SRA);
1606 setTargetDAGCombine(ISD::SRL);
1607 setTargetDAGCombine(ISD::OR);
1608 setTargetDAGCombine(ISD::AND);
1609 setTargetDAGCombine(ISD::ADD);
1610 setTargetDAGCombine(ISD::FADD);
1611 setTargetDAGCombine(ISD::FSUB);
1612 setTargetDAGCombine(ISD::FMA);
1613 setTargetDAGCombine(ISD::SUB);
1614 setTargetDAGCombine(ISD::LOAD);
1615 setTargetDAGCombine(ISD::STORE);
1616 setTargetDAGCombine(ISD::ZERO_EXTEND);
1617 setTargetDAGCombine(ISD::ANY_EXTEND);
1618 setTargetDAGCombine(ISD::SIGN_EXTEND);
1619 setTargetDAGCombine(ISD::SIGN_EXTEND_INREG);
1620 setTargetDAGCombine(ISD::TRUNCATE);
1621 setTargetDAGCombine(ISD::SINT_TO_FP);
1622 setTargetDAGCombine(ISD::SETCC);
1623 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
1624 setTargetDAGCombine(ISD::BUILD_VECTOR);
1625 if (Subtarget->is64Bit())
1626 setTargetDAGCombine(ISD::MUL);
1627 setTargetDAGCombine(ISD::XOR);
1629 computeRegisterProperties();
1631 // On Darwin, -Os means optimize for size without hurting performance,
1632 // do not reduce the limit.
1633 MaxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
1634 MaxStoresPerMemsetOptSize = Subtarget->isTargetDarwin() ? 16 : 8;
1635 MaxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores
1636 MaxStoresPerMemcpyOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1637 MaxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores
1638 MaxStoresPerMemmoveOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1639 setPrefLoopAlignment(4); // 2^4 bytes.
1641 // Predictable cmov don't hurt on atom because it's in-order.
1642 PredictableSelectIsExpensive = !Subtarget->isAtom();
1644 setPrefFunctionAlignment(4); // 2^4 bytes.
1647 // This has so far only been implemented for 64-bit MachO.
1648 bool X86TargetLowering::useLoadStackGuardNode() const {
1649 return Subtarget->getTargetTriple().getObjectFormat() == Triple::MachO &&
1650 Subtarget->is64Bit();
1653 TargetLoweringBase::LegalizeTypeAction
1654 X86TargetLowering::getPreferredVectorAction(EVT VT) const {
1655 if (ExperimentalVectorWideningLegalization &&
1656 VT.getVectorNumElements() != 1 &&
1657 VT.getVectorElementType().getSimpleVT() != MVT::i1)
1658 return TypeWidenVector;
1660 return TargetLoweringBase::getPreferredVectorAction(VT);
1663 EVT X86TargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
1665 return Subtarget->hasAVX512() ? MVT::i1: MVT::i8;
1667 if (Subtarget->hasAVX512())
1668 switch(VT.getVectorNumElements()) {
1669 case 8: return MVT::v8i1;
1670 case 16: return MVT::v16i1;
1673 return VT.changeVectorElementTypeToInteger();
1676 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
1677 /// the desired ByVal argument alignment.
1678 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) {
1681 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1682 if (VTy->getBitWidth() == 128)
1684 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1685 unsigned EltAlign = 0;
1686 getMaxByValAlign(ATy->getElementType(), EltAlign);
1687 if (EltAlign > MaxAlign)
1688 MaxAlign = EltAlign;
1689 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
1690 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
1691 unsigned EltAlign = 0;
1692 getMaxByValAlign(STy->getElementType(i), EltAlign);
1693 if (EltAlign > MaxAlign)
1694 MaxAlign = EltAlign;
1701 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1702 /// function arguments in the caller parameter area. For X86, aggregates
1703 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
1704 /// are at 4-byte boundaries.
1705 unsigned X86TargetLowering::getByValTypeAlignment(Type *Ty) const {
1706 if (Subtarget->is64Bit()) {
1707 // Max of 8 and alignment of type.
1708 unsigned TyAlign = TD->getABITypeAlignment(Ty);
1715 if (Subtarget->hasSSE1())
1716 getMaxByValAlign(Ty, Align);
1720 /// getOptimalMemOpType - Returns the target specific optimal type for load
1721 /// and store operations as a result of memset, memcpy, and memmove
1722 /// lowering. If DstAlign is zero that means it's safe to destination
1723 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
1724 /// means there isn't a need to check it against alignment requirement,
1725 /// probably because the source does not need to be loaded. If 'IsMemset' is
1726 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
1727 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
1728 /// source is constant so it does not need to be loaded.
1729 /// It returns EVT::Other if the type should be determined using generic
1730 /// target-independent logic.
1732 X86TargetLowering::getOptimalMemOpType(uint64_t Size,
1733 unsigned DstAlign, unsigned SrcAlign,
1734 bool IsMemset, bool ZeroMemset,
1736 MachineFunction &MF) const {
1737 const Function *F = MF.getFunction();
1738 if ((!IsMemset || ZeroMemset) &&
1739 !F->getAttributes().hasAttribute(AttributeSet::FunctionIndex,
1740 Attribute::NoImplicitFloat)) {
1742 (Subtarget->isUnalignedMemAccessFast() ||
1743 ((DstAlign == 0 || DstAlign >= 16) &&
1744 (SrcAlign == 0 || SrcAlign >= 16)))) {
1746 if (Subtarget->hasInt256())
1748 if (Subtarget->hasFp256())
1751 if (Subtarget->hasSSE2())
1753 if (Subtarget->hasSSE1())
1755 } else if (!MemcpyStrSrc && Size >= 8 &&
1756 !Subtarget->is64Bit() &&
1757 Subtarget->hasSSE2()) {
1758 // Do not use f64 to lower memcpy if source is string constant. It's
1759 // better to use i32 to avoid the loads.
1763 if (Subtarget->is64Bit() && Size >= 8)
1768 bool X86TargetLowering::isSafeMemOpType(MVT VT) const {
1770 return X86ScalarSSEf32;
1771 else if (VT == MVT::f64)
1772 return X86ScalarSSEf64;
1777 X86TargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
1782 *Fast = Subtarget->isUnalignedMemAccessFast();
1786 /// getJumpTableEncoding - Return the entry encoding for a jump table in the
1787 /// current function. The returned value is a member of the
1788 /// MachineJumpTableInfo::JTEntryKind enum.
1789 unsigned X86TargetLowering::getJumpTableEncoding() const {
1790 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
1792 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1793 Subtarget->isPICStyleGOT())
1794 return MachineJumpTableInfo::EK_Custom32;
1796 // Otherwise, use the normal jump table encoding heuristics.
1797 return TargetLowering::getJumpTableEncoding();
1801 X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
1802 const MachineBasicBlock *MBB,
1803 unsigned uid,MCContext &Ctx) const{
1804 assert(MBB->getParent()->getTarget().getRelocationModel() == Reloc::PIC_ &&
1805 Subtarget->isPICStyleGOT());
1806 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
1808 return MCSymbolRefExpr::Create(MBB->getSymbol(),
1809 MCSymbolRefExpr::VK_GOTOFF, Ctx);
1812 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
1814 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
1815 SelectionDAG &DAG) const {
1816 if (!Subtarget->is64Bit())
1817 // This doesn't have SDLoc associated with it, but is not really the
1818 // same as a Register.
1819 return DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), getPointerTy());
1823 /// getPICJumpTableRelocBaseExpr - This returns the relocation base for the
1824 /// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an
1826 const MCExpr *X86TargetLowering::
1827 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
1828 MCContext &Ctx) const {
1829 // X86-64 uses RIP relative addressing based on the jump table label.
1830 if (Subtarget->isPICStyleRIPRel())
1831 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
1833 // Otherwise, the reference is relative to the PIC base.
1834 return MCSymbolRefExpr::Create(MF->getPICBaseSymbol(), Ctx);
1837 // FIXME: Why this routine is here? Move to RegInfo!
1838 std::pair<const TargetRegisterClass*, uint8_t>
1839 X86TargetLowering::findRepresentativeClass(MVT VT) const{
1840 const TargetRegisterClass *RRC = nullptr;
1842 switch (VT.SimpleTy) {
1844 return TargetLowering::findRepresentativeClass(VT);
1845 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
1846 RRC = Subtarget->is64Bit() ?
1847 (const TargetRegisterClass*)&X86::GR64RegClass :
1848 (const TargetRegisterClass*)&X86::GR32RegClass;
1851 RRC = &X86::VR64RegClass;
1853 case MVT::f32: case MVT::f64:
1854 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
1855 case MVT::v4f32: case MVT::v2f64:
1856 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32:
1858 RRC = &X86::VR128RegClass;
1861 return std::make_pair(RRC, Cost);
1864 bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace,
1865 unsigned &Offset) const {
1866 if (!Subtarget->isTargetLinux())
1869 if (Subtarget->is64Bit()) {
1870 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs:
1872 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
1884 bool X86TargetLowering::isNoopAddrSpaceCast(unsigned SrcAS,
1885 unsigned DestAS) const {
1886 assert(SrcAS != DestAS && "Expected different address spaces!");
1888 return SrcAS < 256 && DestAS < 256;
1891 //===----------------------------------------------------------------------===//
1892 // Return Value Calling Convention Implementation
1893 //===----------------------------------------------------------------------===//
1895 #include "X86GenCallingConv.inc"
1898 X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv,
1899 MachineFunction &MF, bool isVarArg,
1900 const SmallVectorImpl<ISD::OutputArg> &Outs,
1901 LLVMContext &Context) const {
1902 SmallVector<CCValAssign, 16> RVLocs;
1903 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
1904 return CCInfo.CheckReturn(Outs, RetCC_X86);
1907 const MCPhysReg *X86TargetLowering::getScratchRegisters(CallingConv::ID) const {
1908 static const MCPhysReg ScratchRegs[] = { X86::R11, 0 };
1913 X86TargetLowering::LowerReturn(SDValue Chain,
1914 CallingConv::ID CallConv, bool isVarArg,
1915 const SmallVectorImpl<ISD::OutputArg> &Outs,
1916 const SmallVectorImpl<SDValue> &OutVals,
1917 SDLoc dl, SelectionDAG &DAG) const {
1918 MachineFunction &MF = DAG.getMachineFunction();
1919 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1921 SmallVector<CCValAssign, 16> RVLocs;
1922 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, *DAG.getContext());
1923 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
1926 SmallVector<SDValue, 6> RetOps;
1927 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
1928 // Operand #1 = Bytes To Pop
1929 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(),
1932 // Copy the result values into the output registers.
1933 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1934 CCValAssign &VA = RVLocs[i];
1935 assert(VA.isRegLoc() && "Can only return in registers!");
1936 SDValue ValToCopy = OutVals[i];
1937 EVT ValVT = ValToCopy.getValueType();
1939 // Promote values to the appropriate types
1940 if (VA.getLocInfo() == CCValAssign::SExt)
1941 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy);
1942 else if (VA.getLocInfo() == CCValAssign::ZExt)
1943 ValToCopy = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ValToCopy);
1944 else if (VA.getLocInfo() == CCValAssign::AExt)
1945 ValToCopy = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ValToCopy);
1946 else if (VA.getLocInfo() == CCValAssign::BCvt)
1947 ValToCopy = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), ValToCopy);
1949 assert(VA.getLocInfo() != CCValAssign::FPExt &&
1950 "Unexpected FP-extend for return value.");
1952 // If this is x86-64, and we disabled SSE, we can't return FP values,
1953 // or SSE or MMX vectors.
1954 if ((ValVT == MVT::f32 || ValVT == MVT::f64 ||
1955 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) &&
1956 (Subtarget->is64Bit() && !Subtarget->hasSSE1())) {
1957 report_fatal_error("SSE register return with SSE disabled");
1959 // Likewise we can't return F64 values with SSE1 only. gcc does so, but
1960 // llvm-gcc has never done it right and no one has noticed, so this
1961 // should be OK for now.
1962 if (ValVT == MVT::f64 &&
1963 (Subtarget->is64Bit() && !Subtarget->hasSSE2()))
1964 report_fatal_error("SSE2 register return with SSE2 disabled");
1966 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
1967 // the RET instruction and handled by the FP Stackifier.
1968 if (VA.getLocReg() == X86::FP0 ||
1969 VA.getLocReg() == X86::FP1) {
1970 // If this is a copy from an xmm register to ST(0), use an FPExtend to
1971 // change the value to the FP stack register class.
1972 if (isScalarFPTypeInSSEReg(VA.getValVT()))
1973 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
1974 RetOps.push_back(ValToCopy);
1975 // Don't emit a copytoreg.
1979 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
1980 // which is returned in RAX / RDX.
1981 if (Subtarget->is64Bit()) {
1982 if (ValVT == MVT::x86mmx) {
1983 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
1984 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ValToCopy);
1985 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
1987 // If we don't have SSE2 available, convert to v4f32 so the generated
1988 // register is legal.
1989 if (!Subtarget->hasSSE2())
1990 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32,ValToCopy);
1995 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
1996 Flag = Chain.getValue(1);
1997 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2000 // The x86-64 ABIs require that for returning structs by value we copy
2001 // the sret argument into %rax/%eax (depending on ABI) for the return.
2002 // Win32 requires us to put the sret argument to %eax as well.
2003 // We saved the argument into a virtual register in the entry block,
2004 // so now we copy the value out and into %rax/%eax.
2005 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr() &&
2006 (Subtarget->is64Bit() || Subtarget->isTargetKnownWindowsMSVC())) {
2007 MachineFunction &MF = DAG.getMachineFunction();
2008 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2009 unsigned Reg = FuncInfo->getSRetReturnReg();
2011 "SRetReturnReg should have been set in LowerFormalArguments().");
2012 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
2015 = (Subtarget->is64Bit() && !Subtarget->isTarget64BitILP32()) ?
2016 X86::RAX : X86::EAX;
2017 Chain = DAG.getCopyToReg(Chain, dl, RetValReg, Val, Flag);
2018 Flag = Chain.getValue(1);
2020 // RAX/EAX now acts like a return value.
2021 RetOps.push_back(DAG.getRegister(RetValReg, getPointerTy()));
2024 RetOps[0] = Chain; // Update chain.
2026 // Add the flag if we have it.
2028 RetOps.push_back(Flag);
2030 return DAG.getNode(X86ISD::RET_FLAG, dl, MVT::Other, RetOps);
2033 bool X86TargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
2034 if (N->getNumValues() != 1)
2036 if (!N->hasNUsesOfValue(1, 0))
2039 SDValue TCChain = Chain;
2040 SDNode *Copy = *N->use_begin();
2041 if (Copy->getOpcode() == ISD::CopyToReg) {
2042 // If the copy has a glue operand, we conservatively assume it isn't safe to
2043 // perform a tail call.
2044 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
2046 TCChain = Copy->getOperand(0);
2047 } else if (Copy->getOpcode() != ISD::FP_EXTEND)
2050 bool HasRet = false;
2051 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
2053 if (UI->getOpcode() != X86ISD::RET_FLAG)
2066 X86TargetLowering::getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT,
2067 ISD::NodeType ExtendKind) const {
2069 // TODO: Is this also valid on 32-bit?
2070 if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND)
2071 ReturnMVT = MVT::i8;
2073 ReturnMVT = MVT::i32;
2075 EVT MinVT = getRegisterType(Context, ReturnMVT);
2076 return VT.bitsLT(MinVT) ? MinVT : VT;
2079 /// LowerCallResult - Lower the result values of a call into the
2080 /// appropriate copies out of appropriate physical registers.
2083 X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
2084 CallingConv::ID CallConv, bool isVarArg,
2085 const SmallVectorImpl<ISD::InputArg> &Ins,
2086 SDLoc dl, SelectionDAG &DAG,
2087 SmallVectorImpl<SDValue> &InVals) const {
2089 // Assign locations to each value returned by this call.
2090 SmallVector<CCValAssign, 16> RVLocs;
2091 bool Is64Bit = Subtarget->is64Bit();
2092 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
2094 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
2096 // Copy all of the result registers out of their specified physreg.
2097 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
2098 CCValAssign &VA = RVLocs[i];
2099 EVT CopyVT = VA.getValVT();
2101 // If this is x86-64, and we disabled SSE, we can't return FP values
2102 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
2103 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) {
2104 report_fatal_error("SSE register return with SSE disabled");
2107 // If we prefer to use the value in xmm registers, copy it out as f80 and
2108 // use a truncate to move it from fp stack reg to xmm reg.
2109 if ((VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1) &&
2110 isScalarFPTypeInSSEReg(VA.getValVT()))
2113 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
2114 CopyVT, InFlag).getValue(1);
2115 SDValue Val = Chain.getValue(0);
2117 if (CopyVT != VA.getValVT())
2118 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
2119 // This truncation won't change the value.
2120 DAG.getIntPtrConstant(1));
2122 InFlag = Chain.getValue(2);
2123 InVals.push_back(Val);
2129 //===----------------------------------------------------------------------===//
2130 // C & StdCall & Fast Calling Convention implementation
2131 //===----------------------------------------------------------------------===//
2132 // StdCall calling convention seems to be standard for many Windows' API
2133 // routines and around. It differs from C calling convention just a little:
2134 // callee should clean up the stack, not caller. Symbols should be also
2135 // decorated in some fancy way :) It doesn't support any vector arguments.
2136 // For info on fast calling convention see Fast Calling Convention (tail call)
2137 // implementation LowerX86_32FastCCCallTo.
2139 /// CallIsStructReturn - Determines whether a call uses struct return
2141 enum StructReturnType {
2146 static StructReturnType
2147 callIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
2149 return NotStructReturn;
2151 const ISD::ArgFlagsTy &Flags = Outs[0].Flags;
2152 if (!Flags.isSRet())
2153 return NotStructReturn;
2154 if (Flags.isInReg())
2155 return RegStructReturn;
2156 return StackStructReturn;
2159 /// ArgsAreStructReturn - Determines whether a function uses struct
2160 /// return semantics.
2161 static StructReturnType
2162 argsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
2164 return NotStructReturn;
2166 const ISD::ArgFlagsTy &Flags = Ins[0].Flags;
2167 if (!Flags.isSRet())
2168 return NotStructReturn;
2169 if (Flags.isInReg())
2170 return RegStructReturn;
2171 return StackStructReturn;
2174 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
2175 /// by "Src" to address "Dst" with size and alignment information specified by
2176 /// the specific parameter attribute. The copy will be passed as a byval
2177 /// function parameter.
2179 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
2180 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
2182 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
2184 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
2185 /*isVolatile*/false, /*AlwaysInline=*/true,
2186 MachinePointerInfo(), MachinePointerInfo());
2189 /// IsTailCallConvention - Return true if the calling convention is one that
2190 /// supports tail call optimization.
2191 static bool IsTailCallConvention(CallingConv::ID CC) {
2192 return (CC == CallingConv::Fast || CC == CallingConv::GHC ||
2193 CC == CallingConv::HiPE);
2196 /// \brief Return true if the calling convention is a C calling convention.
2197 static bool IsCCallConvention(CallingConv::ID CC) {
2198 return (CC == CallingConv::C || CC == CallingConv::X86_64_Win64 ||
2199 CC == CallingConv::X86_64_SysV);
2202 bool X86TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
2203 if (!CI->isTailCall() || getTargetMachine().Options.DisableTailCalls)
2207 CallingConv::ID CalleeCC = CS.getCallingConv();
2208 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
2214 /// FuncIsMadeTailCallSafe - Return true if the function is being made into
2215 /// a tailcall target by changing its ABI.
2216 static bool FuncIsMadeTailCallSafe(CallingConv::ID CC,
2217 bool GuaranteedTailCallOpt) {
2218 return GuaranteedTailCallOpt && IsTailCallConvention(CC);
2222 X86TargetLowering::LowerMemArgument(SDValue Chain,
2223 CallingConv::ID CallConv,
2224 const SmallVectorImpl<ISD::InputArg> &Ins,
2225 SDLoc dl, SelectionDAG &DAG,
2226 const CCValAssign &VA,
2227 MachineFrameInfo *MFI,
2229 // Create the nodes corresponding to a load from this parameter slot.
2230 ISD::ArgFlagsTy Flags = Ins[i].Flags;
2231 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(
2232 CallConv, DAG.getTarget().Options.GuaranteedTailCallOpt);
2233 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
2236 // If value is passed by pointer we have address passed instead of the value
2238 if (VA.getLocInfo() == CCValAssign::Indirect)
2239 ValVT = VA.getLocVT();
2241 ValVT = VA.getValVT();
2243 // FIXME: For now, all byval parameter objects are marked mutable. This can be
2244 // changed with more analysis.
2245 // In case of tail call optimization mark all arguments mutable. Since they
2246 // could be overwritten by lowering of arguments in case of a tail call.
2247 if (Flags.isByVal()) {
2248 unsigned Bytes = Flags.getByValSize();
2249 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects.
2250 int FI = MFI->CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable);
2251 return DAG.getFrameIndex(FI, getPointerTy());
2253 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
2254 VA.getLocMemOffset(), isImmutable);
2255 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2256 return DAG.getLoad(ValVT, dl, Chain, FIN,
2257 MachinePointerInfo::getFixedStack(FI),
2258 false, false, false, 0);
2263 X86TargetLowering::LowerFormalArguments(SDValue Chain,
2264 CallingConv::ID CallConv,
2266 const SmallVectorImpl<ISD::InputArg> &Ins,
2269 SmallVectorImpl<SDValue> &InVals)
2271 MachineFunction &MF = DAG.getMachineFunction();
2272 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2274 const Function* Fn = MF.getFunction();
2275 if (Fn->hasExternalLinkage() &&
2276 Subtarget->isTargetCygMing() &&
2277 Fn->getName() == "main")
2278 FuncInfo->setForceFramePointer(true);
2280 MachineFrameInfo *MFI = MF.getFrameInfo();
2281 bool Is64Bit = Subtarget->is64Bit();
2282 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2284 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2285 "Var args not supported with calling convention fastcc, ghc or hipe");
2287 // Assign locations to all of the incoming arguments.
2288 SmallVector<CCValAssign, 16> ArgLocs;
2289 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
2291 // Allocate shadow area for Win64
2293 CCInfo.AllocateStack(32, 8);
2295 CCInfo.AnalyzeFormalArguments(Ins, CC_X86);
2297 unsigned LastVal = ~0U;
2299 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2300 CCValAssign &VA = ArgLocs[i];
2301 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
2303 assert(VA.getValNo() != LastVal &&
2304 "Don't support value assigned to multiple locs yet");
2306 LastVal = VA.getValNo();
2308 if (VA.isRegLoc()) {
2309 EVT RegVT = VA.getLocVT();
2310 const TargetRegisterClass *RC;
2311 if (RegVT == MVT::i32)
2312 RC = &X86::GR32RegClass;
2313 else if (Is64Bit && RegVT == MVT::i64)
2314 RC = &X86::GR64RegClass;
2315 else if (RegVT == MVT::f32)
2316 RC = &X86::FR32RegClass;
2317 else if (RegVT == MVT::f64)
2318 RC = &X86::FR64RegClass;
2319 else if (RegVT.is512BitVector())
2320 RC = &X86::VR512RegClass;
2321 else if (RegVT.is256BitVector())
2322 RC = &X86::VR256RegClass;
2323 else if (RegVT.is128BitVector())
2324 RC = &X86::VR128RegClass;
2325 else if (RegVT == MVT::x86mmx)
2326 RC = &X86::VR64RegClass;
2327 else if (RegVT == MVT::i1)
2328 RC = &X86::VK1RegClass;
2329 else if (RegVT == MVT::v8i1)
2330 RC = &X86::VK8RegClass;
2331 else if (RegVT == MVT::v16i1)
2332 RC = &X86::VK16RegClass;
2333 else if (RegVT == MVT::v32i1)
2334 RC = &X86::VK32RegClass;
2335 else if (RegVT == MVT::v64i1)
2336 RC = &X86::VK64RegClass;
2338 llvm_unreachable("Unknown argument type!");
2340 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2341 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
2343 // If this is an 8 or 16-bit value, it is really passed promoted to 32
2344 // bits. Insert an assert[sz]ext to capture this, then truncate to the
2346 if (VA.getLocInfo() == CCValAssign::SExt)
2347 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
2348 DAG.getValueType(VA.getValVT()));
2349 else if (VA.getLocInfo() == CCValAssign::ZExt)
2350 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
2351 DAG.getValueType(VA.getValVT()));
2352 else if (VA.getLocInfo() == CCValAssign::BCvt)
2353 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
2355 if (VA.isExtInLoc()) {
2356 // Handle MMX values passed in XMM regs.
2357 if (RegVT.isVector())
2358 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(), ArgValue);
2360 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
2363 assert(VA.isMemLoc());
2364 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
2367 // If value is passed via pointer - do a load.
2368 if (VA.getLocInfo() == CCValAssign::Indirect)
2369 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue,
2370 MachinePointerInfo(), false, false, false, 0);
2372 InVals.push_back(ArgValue);
2375 if (Subtarget->is64Bit() || Subtarget->isTargetKnownWindowsMSVC()) {
2376 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2377 // The x86-64 ABIs require that for returning structs by value we copy
2378 // the sret argument into %rax/%eax (depending on ABI) for the return.
2379 // Win32 requires us to put the sret argument to %eax as well.
2380 // Save the argument into a virtual register so that we can access it
2381 // from the return points.
2382 if (Ins[i].Flags.isSRet()) {
2383 unsigned Reg = FuncInfo->getSRetReturnReg();
2385 MVT PtrTy = getPointerTy();
2386 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(PtrTy));
2387 FuncInfo->setSRetReturnReg(Reg);
2389 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[i]);
2390 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
2396 unsigned StackSize = CCInfo.getNextStackOffset();
2397 // Align stack specially for tail calls.
2398 if (FuncIsMadeTailCallSafe(CallConv,
2399 MF.getTarget().Options.GuaranteedTailCallOpt))
2400 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
2402 // If the function takes variable number of arguments, make a frame index for
2403 // the start of the first vararg value... for expansion of llvm.va_start.
2405 if (Is64Bit || (CallConv != CallingConv::X86_FastCall &&
2406 CallConv != CallingConv::X86_ThisCall)) {
2407 FuncInfo->setVarArgsFrameIndex(MFI->CreateFixedObject(1, StackSize,true));
2410 unsigned TotalNumIntRegs = 0, TotalNumXMMRegs = 0;
2412 // FIXME: We should really autogenerate these arrays
2413 static const MCPhysReg GPR64ArgRegsWin64[] = {
2414 X86::RCX, X86::RDX, X86::R8, X86::R9
2416 static const MCPhysReg GPR64ArgRegs64Bit[] = {
2417 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
2419 static const MCPhysReg XMMArgRegs64Bit[] = {
2420 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2421 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2423 const MCPhysReg *GPR64ArgRegs;
2424 unsigned NumXMMRegs = 0;
2427 // The XMM registers which might contain var arg parameters are shadowed
2428 // in their paired GPR. So we only need to save the GPR to their home
2430 TotalNumIntRegs = 4;
2431 GPR64ArgRegs = GPR64ArgRegsWin64;
2433 TotalNumIntRegs = 6; TotalNumXMMRegs = 8;
2434 GPR64ArgRegs = GPR64ArgRegs64Bit;
2436 NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs64Bit,
2439 unsigned NumIntRegs = CCInfo.getFirstUnallocated(GPR64ArgRegs,
2442 bool NoImplicitFloatOps = Fn->getAttributes().
2443 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoImplicitFloat);
2444 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) &&
2445 "SSE register cannot be used when SSE is disabled!");
2446 assert(!(NumXMMRegs && MF.getTarget().Options.UseSoftFloat &&
2447 NoImplicitFloatOps) &&
2448 "SSE register cannot be used when SSE is disabled!");
2449 if (MF.getTarget().Options.UseSoftFloat || NoImplicitFloatOps ||
2450 !Subtarget->hasSSE1())
2451 // Kernel mode asks for SSE to be disabled, so don't push them
2453 TotalNumXMMRegs = 0;
2456 const TargetFrameLowering &TFI = *MF.getSubtarget().getFrameLowering();
2457 // Get to the caller-allocated home save location. Add 8 to account
2458 // for the return address.
2459 int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
2460 FuncInfo->setRegSaveFrameIndex(
2461 MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false));
2462 // Fixup to set vararg frame on shadow area (4 x i64).
2464 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex());
2466 // For X86-64, if there are vararg parameters that are passed via
2467 // registers, then we must store them to their spots on the stack so
2468 // they may be loaded by deferencing the result of va_next.
2469 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8);
2470 FuncInfo->setVarArgsFPOffset(TotalNumIntRegs * 8 + NumXMMRegs * 16);
2471 FuncInfo->setRegSaveFrameIndex(
2472 MFI->CreateStackObject(TotalNumIntRegs * 8 + TotalNumXMMRegs * 16, 16,
2476 // Store the integer parameter registers.
2477 SmallVector<SDValue, 8> MemOps;
2478 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
2480 unsigned Offset = FuncInfo->getVarArgsGPOffset();
2481 for (; NumIntRegs != TotalNumIntRegs; ++NumIntRegs) {
2482 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN,
2483 DAG.getIntPtrConstant(Offset));
2484 unsigned VReg = MF.addLiveIn(GPR64ArgRegs[NumIntRegs],
2485 &X86::GR64RegClass);
2486 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
2488 DAG.getStore(Val.getValue(1), dl, Val, FIN,
2489 MachinePointerInfo::getFixedStack(
2490 FuncInfo->getRegSaveFrameIndex(), Offset),
2492 MemOps.push_back(Store);
2496 if (TotalNumXMMRegs != 0 && NumXMMRegs != TotalNumXMMRegs) {
2497 // Now store the XMM (fp + vector) parameter registers.
2498 SmallVector<SDValue, 12> SaveXMMOps;
2499 SaveXMMOps.push_back(Chain);
2501 unsigned AL = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
2502 SDValue ALVal = DAG.getCopyFromReg(DAG.getEntryNode(), dl, AL, MVT::i8);
2503 SaveXMMOps.push_back(ALVal);
2505 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2506 FuncInfo->getRegSaveFrameIndex()));
2507 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2508 FuncInfo->getVarArgsFPOffset()));
2510 for (; NumXMMRegs != TotalNumXMMRegs; ++NumXMMRegs) {
2511 unsigned VReg = MF.addLiveIn(XMMArgRegs64Bit[NumXMMRegs],
2512 &X86::VR128RegClass);
2513 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::v4f32);
2514 SaveXMMOps.push_back(Val);
2516 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
2517 MVT::Other, SaveXMMOps));
2520 if (!MemOps.empty())
2521 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
2525 // Some CCs need callee pop.
2526 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2527 MF.getTarget().Options.GuaranteedTailCallOpt)) {
2528 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything.
2530 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing.
2531 // If this is an sret function, the return should pop the hidden pointer.
2532 if (!Is64Bit && !IsTailCallConvention(CallConv) &&
2533 !Subtarget->getTargetTriple().isOSMSVCRT() &&
2534 argsAreStructReturn(Ins) == StackStructReturn)
2535 FuncInfo->setBytesToPopOnReturn(4);
2539 // RegSaveFrameIndex is X86-64 only.
2540 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
2541 if (CallConv == CallingConv::X86_FastCall ||
2542 CallConv == CallingConv::X86_ThisCall)
2543 // fastcc functions can't have varargs.
2544 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA);
2547 FuncInfo->setArgumentStackSize(StackSize);
2553 X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
2554 SDValue StackPtr, SDValue Arg,
2555 SDLoc dl, SelectionDAG &DAG,
2556 const CCValAssign &VA,
2557 ISD::ArgFlagsTy Flags) const {
2558 unsigned LocMemOffset = VA.getLocMemOffset();
2559 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
2560 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
2561 if (Flags.isByVal())
2562 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
2564 return DAG.getStore(Chain, dl, Arg, PtrOff,
2565 MachinePointerInfo::getStack(LocMemOffset),
2569 /// EmitTailCallLoadRetAddr - Emit a load of return address if tail call
2570 /// optimization is performed and it is required.
2572 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
2573 SDValue &OutRetAddr, SDValue Chain,
2574 bool IsTailCall, bool Is64Bit,
2575 int FPDiff, SDLoc dl) const {
2576 // Adjust the Return address stack slot.
2577 EVT VT = getPointerTy();
2578 OutRetAddr = getReturnAddressFrameIndex(DAG);
2580 // Load the "old" Return address.
2581 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(),
2582 false, false, false, 0);
2583 return SDValue(OutRetAddr.getNode(), 1);
2586 /// EmitTailCallStoreRetAddr - Emit a store of the return address if tail call
2587 /// optimization is performed and it is required (FPDiff!=0).
2588 static SDValue EmitTailCallStoreRetAddr(SelectionDAG &DAG, MachineFunction &MF,
2589 SDValue Chain, SDValue RetAddrFrIdx,
2590 EVT PtrVT, unsigned SlotSize,
2591 int FPDiff, SDLoc dl) {
2592 // Store the return address to the appropriate stack slot.
2593 if (!FPDiff) return Chain;
2594 // Calculate the new stack slot for the return address.
2595 int NewReturnAddrFI =
2596 MF.getFrameInfo()->CreateFixedObject(SlotSize, (int64_t)FPDiff - SlotSize,
2598 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, PtrVT);
2599 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
2600 MachinePointerInfo::getFixedStack(NewReturnAddrFI),
2606 X86TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
2607 SmallVectorImpl<SDValue> &InVals) const {
2608 SelectionDAG &DAG = CLI.DAG;
2610 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
2611 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
2612 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
2613 SDValue Chain = CLI.Chain;
2614 SDValue Callee = CLI.Callee;
2615 CallingConv::ID CallConv = CLI.CallConv;
2616 bool &isTailCall = CLI.IsTailCall;
2617 bool isVarArg = CLI.IsVarArg;
2619 MachineFunction &MF = DAG.getMachineFunction();
2620 bool Is64Bit = Subtarget->is64Bit();
2621 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2622 StructReturnType SR = callIsStructReturn(Outs);
2623 bool IsSibcall = false;
2625 if (MF.getTarget().Options.DisableTailCalls)
2628 bool IsMustTail = CLI.CS && CLI.CS->isMustTailCall();
2630 // Force this to be a tail call. The verifier rules are enough to ensure
2631 // that we can lower this successfully without moving the return address
2634 } else if (isTailCall) {
2635 // Check if it's really possible to do a tail call.
2636 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
2637 isVarArg, SR != NotStructReturn,
2638 MF.getFunction()->hasStructRetAttr(), CLI.RetTy,
2639 Outs, OutVals, Ins, DAG);
2641 // Sibcalls are automatically detected tailcalls which do not require
2643 if (!MF.getTarget().Options.GuaranteedTailCallOpt && isTailCall)
2650 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2651 "Var args not supported with calling convention fastcc, ghc or hipe");
2653 // Analyze operands of the call, assigning locations to each operand.
2654 SmallVector<CCValAssign, 16> ArgLocs;
2655 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
2657 // Allocate shadow area for Win64
2659 CCInfo.AllocateStack(32, 8);
2661 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2663 // Get a count of how many bytes are to be pushed on the stack.
2664 unsigned NumBytes = CCInfo.getNextStackOffset();
2666 // This is a sibcall. The memory operands are available in caller's
2667 // own caller's stack.
2669 else if (MF.getTarget().Options.GuaranteedTailCallOpt &&
2670 IsTailCallConvention(CallConv))
2671 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
2674 if (isTailCall && !IsSibcall && !IsMustTail) {
2675 // Lower arguments at fp - stackoffset + fpdiff.
2676 X86MachineFunctionInfo *X86Info = MF.getInfo<X86MachineFunctionInfo>();
2677 unsigned NumBytesCallerPushed = X86Info->getBytesToPopOnReturn();
2679 FPDiff = NumBytesCallerPushed - NumBytes;
2681 // Set the delta of movement of the returnaddr stackslot.
2682 // But only set if delta is greater than previous delta.
2683 if (FPDiff < X86Info->getTCReturnAddrDelta())
2684 X86Info->setTCReturnAddrDelta(FPDiff);
2687 unsigned NumBytesToPush = NumBytes;
2688 unsigned NumBytesToPop = NumBytes;
2690 // If we have an inalloca argument, all stack space has already been allocated
2691 // for us and be right at the top of the stack. We don't support multiple
2692 // arguments passed in memory when using inalloca.
2693 if (!Outs.empty() && Outs.back().Flags.isInAlloca()) {
2695 if (!ArgLocs.back().isMemLoc())
2696 report_fatal_error("cannot use inalloca attribute on a register "
2698 if (ArgLocs.back().getLocMemOffset() != 0)
2699 report_fatal_error("any parameter with the inalloca attribute must be "
2700 "the only memory argument");
2704 Chain = DAG.getCALLSEQ_START(
2705 Chain, DAG.getIntPtrConstant(NumBytesToPush, true), dl);
2707 SDValue RetAddrFrIdx;
2708 // Load return address for tail calls.
2709 if (isTailCall && FPDiff)
2710 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall,
2711 Is64Bit, FPDiff, dl);
2713 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
2714 SmallVector<SDValue, 8> MemOpChains;
2717 // Walk the register/memloc assignments, inserting copies/loads. In the case
2718 // of tail call optimization arguments are handle later.
2719 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
2720 DAG.getSubtarget().getRegisterInfo());
2721 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2722 // Skip inalloca arguments, they have already been written.
2723 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2724 if (Flags.isInAlloca())
2727 CCValAssign &VA = ArgLocs[i];
2728 EVT RegVT = VA.getLocVT();
2729 SDValue Arg = OutVals[i];
2730 bool isByVal = Flags.isByVal();
2732 // Promote the value if needed.
2733 switch (VA.getLocInfo()) {
2734 default: llvm_unreachable("Unknown loc info!");
2735 case CCValAssign::Full: break;
2736 case CCValAssign::SExt:
2737 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
2739 case CCValAssign::ZExt:
2740 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
2742 case CCValAssign::AExt:
2743 if (RegVT.is128BitVector()) {
2744 // Special case: passing MMX values in XMM registers.
2745 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg);
2746 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
2747 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
2749 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
2751 case CCValAssign::BCvt:
2752 Arg = DAG.getNode(ISD::BITCAST, dl, RegVT, Arg);
2754 case CCValAssign::Indirect: {
2755 // Store the argument.
2756 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
2757 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
2758 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot,
2759 MachinePointerInfo::getFixedStack(FI),
2766 if (VA.isRegLoc()) {
2767 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2768 if (isVarArg && IsWin64) {
2769 // Win64 ABI requires argument XMM reg to be copied to the corresponding
2770 // shadow reg if callee is a varargs function.
2771 unsigned ShadowReg = 0;
2772 switch (VA.getLocReg()) {
2773 case X86::XMM0: ShadowReg = X86::RCX; break;
2774 case X86::XMM1: ShadowReg = X86::RDX; break;
2775 case X86::XMM2: ShadowReg = X86::R8; break;
2776 case X86::XMM3: ShadowReg = X86::R9; break;
2779 RegsToPass.push_back(std::make_pair(ShadowReg, Arg));
2781 } else if (!IsSibcall && (!isTailCall || isByVal)) {
2782 assert(VA.isMemLoc());
2783 if (!StackPtr.getNode())
2784 StackPtr = DAG.getCopyFromReg(Chain, dl, RegInfo->getStackRegister(),
2786 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
2787 dl, DAG, VA, Flags));
2791 if (!MemOpChains.empty())
2792 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
2794 if (Subtarget->isPICStyleGOT()) {
2795 // ELF / PIC requires GOT in the EBX register before function calls via PLT
2798 RegsToPass.push_back(std::make_pair(unsigned(X86::EBX),
2799 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), getPointerTy())));
2801 // If we are tail calling and generating PIC/GOT style code load the
2802 // address of the callee into ECX. The value in ecx is used as target of
2803 // the tail jump. This is done to circumvent the ebx/callee-saved problem
2804 // for tail calls on PIC/GOT architectures. Normally we would just put the
2805 // address of GOT into ebx and then call target@PLT. But for tail calls
2806 // ebx would be restored (since ebx is callee saved) before jumping to the
2809 // Note: The actual moving to ECX is done further down.
2810 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
2811 if (G && !G->getGlobal()->hasHiddenVisibility() &&
2812 !G->getGlobal()->hasProtectedVisibility())
2813 Callee = LowerGlobalAddress(Callee, DAG);
2814 else if (isa<ExternalSymbolSDNode>(Callee))
2815 Callee = LowerExternalSymbol(Callee, DAG);
2819 if (Is64Bit && isVarArg && !IsWin64) {
2820 // From AMD64 ABI document:
2821 // For calls that may call functions that use varargs or stdargs
2822 // (prototype-less calls or calls to functions containing ellipsis (...) in
2823 // the declaration) %al is used as hidden argument to specify the number
2824 // of SSE registers used. The contents of %al do not need to match exactly
2825 // the number of registers, but must be an ubound on the number of SSE
2826 // registers used and is in the range 0 - 8 inclusive.
2828 // Count the number of XMM registers allocated.
2829 static const MCPhysReg XMMArgRegs[] = {
2830 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2831 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2833 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
2834 assert((Subtarget->hasSSE1() || !NumXMMRegs)
2835 && "SSE registers cannot be used when SSE is disabled");
2837 RegsToPass.push_back(std::make_pair(unsigned(X86::AL),
2838 DAG.getConstant(NumXMMRegs, MVT::i8)));
2841 // For tail calls lower the arguments to the 'real' stack slots. Sibcalls
2842 // don't need this because the eligibility check rejects calls that require
2843 // shuffling arguments passed in memory.
2844 if (!IsSibcall && isTailCall) {
2845 // Force all the incoming stack arguments to be loaded from the stack
2846 // before any new outgoing arguments are stored to the stack, because the
2847 // outgoing stack slots may alias the incoming argument stack slots, and
2848 // the alias isn't otherwise explicit. This is slightly more conservative
2849 // than necessary, because it means that each store effectively depends
2850 // on every argument instead of just those arguments it would clobber.
2851 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
2853 SmallVector<SDValue, 8> MemOpChains2;
2856 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2857 CCValAssign &VA = ArgLocs[i];
2860 assert(VA.isMemLoc());
2861 SDValue Arg = OutVals[i];
2862 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2863 // Skip inalloca arguments. They don't require any work.
2864 if (Flags.isInAlloca())
2866 // Create frame index.
2867 int32_t Offset = VA.getLocMemOffset()+FPDiff;
2868 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
2869 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
2870 FIN = DAG.getFrameIndex(FI, getPointerTy());
2872 if (Flags.isByVal()) {
2873 // Copy relative to framepointer.
2874 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset());
2875 if (!StackPtr.getNode())
2876 StackPtr = DAG.getCopyFromReg(Chain, dl,
2877 RegInfo->getStackRegister(),
2879 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source);
2881 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
2885 // Store relative to framepointer.
2886 MemOpChains2.push_back(
2887 DAG.getStore(ArgChain, dl, Arg, FIN,
2888 MachinePointerInfo::getFixedStack(FI),
2893 if (!MemOpChains2.empty())
2894 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains2);
2896 // Store the return address to the appropriate stack slot.
2897 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx,
2898 getPointerTy(), RegInfo->getSlotSize(),
2902 // Build a sequence of copy-to-reg nodes chained together with token chain
2903 // and flag operands which copy the outgoing args into registers.
2905 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2906 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
2907 RegsToPass[i].second, InFlag);
2908 InFlag = Chain.getValue(1);
2911 if (DAG.getTarget().getCodeModel() == CodeModel::Large) {
2912 assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
2913 // In the 64-bit large code model, we have to make all calls
2914 // through a register, since the call instruction's 32-bit
2915 // pc-relative offset may not be large enough to hold the whole
2917 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2918 // If the callee is a GlobalAddress node (quite common, every direct call
2919 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
2922 // We should use extra load for direct calls to dllimported functions in
2924 const GlobalValue *GV = G->getGlobal();
2925 if (!GV->hasDLLImportStorageClass()) {
2926 unsigned char OpFlags = 0;
2927 bool ExtraLoad = false;
2928 unsigned WrapperKind = ISD::DELETED_NODE;
2930 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
2931 // external symbols most go through the PLT in PIC mode. If the symbol
2932 // has hidden or protected visibility, or if it is static or local, then
2933 // we don't need to use the PLT - we can directly call it.
2934 if (Subtarget->isTargetELF() &&
2935 DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
2936 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
2937 OpFlags = X86II::MO_PLT;
2938 } else if (Subtarget->isPICStyleStubAny() &&
2939 (GV->isDeclaration() || GV->isWeakForLinker()) &&
2940 (!Subtarget->getTargetTriple().isMacOSX() ||
2941 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
2942 // PC-relative references to external symbols should go through $stub,
2943 // unless we're building with the leopard linker or later, which
2944 // automatically synthesizes these stubs.
2945 OpFlags = X86II::MO_DARWIN_STUB;
2946 } else if (Subtarget->isPICStyleRIPRel() &&
2947 isa<Function>(GV) &&
2948 cast<Function>(GV)->getAttributes().
2949 hasAttribute(AttributeSet::FunctionIndex,
2950 Attribute::NonLazyBind)) {
2951 // If the function is marked as non-lazy, generate an indirect call
2952 // which loads from the GOT directly. This avoids runtime overhead
2953 // at the cost of eager binding (and one extra byte of encoding).
2954 OpFlags = X86II::MO_GOTPCREL;
2955 WrapperKind = X86ISD::WrapperRIP;
2959 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(),
2960 G->getOffset(), OpFlags);
2962 // Add a wrapper if needed.
2963 if (WrapperKind != ISD::DELETED_NODE)
2964 Callee = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Callee);
2965 // Add extra indirection if needed.
2967 Callee = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Callee,
2968 MachinePointerInfo::getGOT(),
2969 false, false, false, 0);
2971 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
2972 unsigned char OpFlags = 0;
2974 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to
2975 // external symbols should go through the PLT.
2976 if (Subtarget->isTargetELF() &&
2977 DAG.getTarget().getRelocationModel() == Reloc::PIC_) {
2978 OpFlags = X86II::MO_PLT;
2979 } else if (Subtarget->isPICStyleStubAny() &&
2980 (!Subtarget->getTargetTriple().isMacOSX() ||
2981 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
2982 // PC-relative references to external symbols should go through $stub,
2983 // unless we're building with the leopard linker or later, which
2984 // automatically synthesizes these stubs.
2985 OpFlags = X86II::MO_DARWIN_STUB;
2988 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(),
2992 // Returns a chain & a flag for retval copy to use.
2993 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
2994 SmallVector<SDValue, 8> Ops;
2996 if (!IsSibcall && isTailCall) {
2997 Chain = DAG.getCALLSEQ_END(Chain,
2998 DAG.getIntPtrConstant(NumBytesToPop, true),
2999 DAG.getIntPtrConstant(0, true), InFlag, dl);
3000 InFlag = Chain.getValue(1);
3003 Ops.push_back(Chain);
3004 Ops.push_back(Callee);
3007 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32));
3009 // Add argument registers to the end of the list so that they are known live
3011 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
3012 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
3013 RegsToPass[i].second.getValueType()));
3015 // Add a register mask operand representing the call-preserved registers.
3016 const TargetRegisterInfo *TRI = DAG.getSubtarget().getRegisterInfo();
3017 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv);
3018 assert(Mask && "Missing call preserved mask for calling convention");
3019 Ops.push_back(DAG.getRegisterMask(Mask));
3021 if (InFlag.getNode())
3022 Ops.push_back(InFlag);
3026 //// If this is the first return lowered for this function, add the regs
3027 //// to the liveout set for the function.
3028 // This isn't right, although it's probably harmless on x86; liveouts
3029 // should be computed from returns not tail calls. Consider a void
3030 // function making a tail call to a function returning int.
3031 return DAG.getNode(X86ISD::TC_RETURN, dl, NodeTys, Ops);
3034 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, Ops);
3035 InFlag = Chain.getValue(1);
3037 // Create the CALLSEQ_END node.
3038 unsigned NumBytesForCalleeToPop;
3039 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
3040 DAG.getTarget().Options.GuaranteedTailCallOpt))
3041 NumBytesForCalleeToPop = NumBytes; // Callee pops everything
3042 else if (!Is64Bit && !IsTailCallConvention(CallConv) &&
3043 !Subtarget->getTargetTriple().isOSMSVCRT() &&
3044 SR == StackStructReturn)
3045 // If this is a call to a struct-return function, the callee
3046 // pops the hidden struct pointer, so we have to push it back.
3047 // This is common for Darwin/X86, Linux & Mingw32 targets.
3048 // For MSVC Win32 targets, the caller pops the hidden struct pointer.
3049 NumBytesForCalleeToPop = 4;
3051 NumBytesForCalleeToPop = 0; // Callee pops nothing.
3053 // Returns a flag for retval copy to use.
3055 Chain = DAG.getCALLSEQ_END(Chain,
3056 DAG.getIntPtrConstant(NumBytesToPop, true),
3057 DAG.getIntPtrConstant(NumBytesForCalleeToPop,
3060 InFlag = Chain.getValue(1);
3063 // Handle result values, copying them out of physregs into vregs that we
3065 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
3066 Ins, dl, DAG, InVals);
3069 //===----------------------------------------------------------------------===//
3070 // Fast Calling Convention (tail call) implementation
3071 //===----------------------------------------------------------------------===//
3073 // Like std call, callee cleans arguments, convention except that ECX is
3074 // reserved for storing the tail called function address. Only 2 registers are
3075 // free for argument passing (inreg). Tail call optimization is performed
3077 // * tailcallopt is enabled
3078 // * caller/callee are fastcc
3079 // On X86_64 architecture with GOT-style position independent code only local
3080 // (within module) calls are supported at the moment.
3081 // To keep the stack aligned according to platform abi the function
3082 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
3083 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
3084 // If a tail called function callee has more arguments than the caller the
3085 // caller needs to make sure that there is room to move the RETADDR to. This is
3086 // achieved by reserving an area the size of the argument delta right after the
3087 // original RETADDR, but before the saved framepointer or the spilled registers
3088 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
3100 /// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned
3101 /// for a 16 byte align requirement.
3103 X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
3104 SelectionDAG& DAG) const {
3105 MachineFunction &MF = DAG.getMachineFunction();
3106 const TargetMachine &TM = MF.getTarget();
3107 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
3108 TM.getSubtargetImpl()->getRegisterInfo());
3109 const TargetFrameLowering &TFI = *TM.getSubtargetImpl()->getFrameLowering();
3110 unsigned StackAlignment = TFI.getStackAlignment();
3111 uint64_t AlignMask = StackAlignment - 1;
3112 int64_t Offset = StackSize;
3113 unsigned SlotSize = RegInfo->getSlotSize();
3114 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
3115 // Number smaller than 12 so just add the difference.
3116 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
3118 // Mask out lower bits, add stackalignment once plus the 12 bytes.
3119 Offset = ((~AlignMask) & Offset) + StackAlignment +
3120 (StackAlignment-SlotSize);
3125 /// MatchingStackOffset - Return true if the given stack call argument is
3126 /// already available in the same position (relatively) of the caller's
3127 /// incoming argument stack.
3129 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
3130 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
3131 const X86InstrInfo *TII) {
3132 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
3134 if (Arg.getOpcode() == ISD::CopyFromReg) {
3135 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
3136 if (!TargetRegisterInfo::isVirtualRegister(VR))
3138 MachineInstr *Def = MRI->getVRegDef(VR);
3141 if (!Flags.isByVal()) {
3142 if (!TII->isLoadFromStackSlot(Def, FI))
3145 unsigned Opcode = Def->getOpcode();
3146 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r) &&
3147 Def->getOperand(1).isFI()) {
3148 FI = Def->getOperand(1).getIndex();
3149 Bytes = Flags.getByValSize();
3153 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
3154 if (Flags.isByVal())
3155 // ByVal argument is passed in as a pointer but it's now being
3156 // dereferenced. e.g.
3157 // define @foo(%struct.X* %A) {
3158 // tail call @bar(%struct.X* byval %A)
3161 SDValue Ptr = Ld->getBasePtr();
3162 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
3165 FI = FINode->getIndex();
3166 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) {
3167 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg);
3168 FI = FINode->getIndex();
3169 Bytes = Flags.getByValSize();
3173 assert(FI != INT_MAX);
3174 if (!MFI->isFixedObjectIndex(FI))
3176 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
3179 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
3180 /// for tail call optimization. Targets which want to do tail call
3181 /// optimization should implement this function.
3183 X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
3184 CallingConv::ID CalleeCC,
3186 bool isCalleeStructRet,
3187 bool isCallerStructRet,
3189 const SmallVectorImpl<ISD::OutputArg> &Outs,
3190 const SmallVectorImpl<SDValue> &OutVals,
3191 const SmallVectorImpl<ISD::InputArg> &Ins,
3192 SelectionDAG &DAG) const {
3193 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
3196 // If -tailcallopt is specified, make fastcc functions tail-callable.
3197 const MachineFunction &MF = DAG.getMachineFunction();
3198 const Function *CallerF = MF.getFunction();
3200 // If the function return type is x86_fp80 and the callee return type is not,
3201 // then the FP_EXTEND of the call result is not a nop. It's not safe to
3202 // perform a tailcall optimization here.
3203 if (CallerF->getReturnType()->isX86_FP80Ty() && !RetTy->isX86_FP80Ty())
3206 CallingConv::ID CallerCC = CallerF->getCallingConv();
3207 bool CCMatch = CallerCC == CalleeCC;
3208 bool IsCalleeWin64 = Subtarget->isCallingConvWin64(CalleeCC);
3209 bool IsCallerWin64 = Subtarget->isCallingConvWin64(CallerCC);
3211 if (DAG.getTarget().Options.GuaranteedTailCallOpt) {
3212 if (IsTailCallConvention(CalleeCC) && CCMatch)
3217 // Look for obvious safe cases to perform tail call optimization that do not
3218 // require ABI changes. This is what gcc calls sibcall.
3220 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
3221 // emit a special epilogue.
3222 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
3223 DAG.getSubtarget().getRegisterInfo());
3224 if (RegInfo->needsStackRealignment(MF))
3227 // Also avoid sibcall optimization if either caller or callee uses struct
3228 // return semantics.
3229 if (isCalleeStructRet || isCallerStructRet)
3232 // An stdcall/thiscall caller is expected to clean up its arguments; the
3233 // callee isn't going to do that.
3234 // FIXME: this is more restrictive than needed. We could produce a tailcall
3235 // when the stack adjustment matches. For example, with a thiscall that takes
3236 // only one argument.
3237 if (!CCMatch && (CallerCC == CallingConv::X86_StdCall ||
3238 CallerCC == CallingConv::X86_ThisCall))
3241 // Do not sibcall optimize vararg calls unless all arguments are passed via
3243 if (isVarArg && !Outs.empty()) {
3245 // Optimizing for varargs on Win64 is unlikely to be safe without
3246 // additional testing.
3247 if (IsCalleeWin64 || IsCallerWin64)
3250 SmallVector<CCValAssign, 16> ArgLocs;
3251 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
3254 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3255 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
3256 if (!ArgLocs[i].isRegLoc())
3260 // If the call result is in ST0 / ST1, it needs to be popped off the x87
3261 // stack. Therefore, if it's not used by the call it is not safe to optimize
3262 // this into a sibcall.
3263 bool Unused = false;
3264 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
3271 SmallVector<CCValAssign, 16> RVLocs;
3272 CCState CCInfo(CalleeCC, false, DAG.getMachineFunction(), RVLocs,
3274 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
3275 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
3276 CCValAssign &VA = RVLocs[i];
3277 if (VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1)
3282 // If the calling conventions do not match, then we'd better make sure the
3283 // results are returned in the same way as what the caller expects.
3285 SmallVector<CCValAssign, 16> RVLocs1;
3286 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(), RVLocs1,
3288 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86);
3290 SmallVector<CCValAssign, 16> RVLocs2;
3291 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(), RVLocs2,
3293 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86);
3295 if (RVLocs1.size() != RVLocs2.size())
3297 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
3298 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
3300 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
3302 if (RVLocs1[i].isRegLoc()) {
3303 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
3306 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
3312 // If the callee takes no arguments then go on to check the results of the
3314 if (!Outs.empty()) {
3315 // Check if stack adjustment is needed. For now, do not do this if any
3316 // argument is passed on the stack.
3317 SmallVector<CCValAssign, 16> ArgLocs;
3318 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
3321 // Allocate shadow area for Win64
3323 CCInfo.AllocateStack(32, 8);
3325 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3326 if (CCInfo.getNextStackOffset()) {
3327 MachineFunction &MF = DAG.getMachineFunction();
3328 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn())
3331 // Check if the arguments are already laid out in the right way as
3332 // the caller's fixed stack objects.
3333 MachineFrameInfo *MFI = MF.getFrameInfo();
3334 const MachineRegisterInfo *MRI = &MF.getRegInfo();
3335 const X86InstrInfo *TII =
3336 static_cast<const X86InstrInfo *>(DAG.getSubtarget().getInstrInfo());
3337 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3338 CCValAssign &VA = ArgLocs[i];
3339 SDValue Arg = OutVals[i];
3340 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3341 if (VA.getLocInfo() == CCValAssign::Indirect)
3343 if (!VA.isRegLoc()) {
3344 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
3351 // If the tailcall address may be in a register, then make sure it's
3352 // possible to register allocate for it. In 32-bit, the call address can
3353 // only target EAX, EDX, or ECX since the tail call must be scheduled after
3354 // callee-saved registers are restored. These happen to be the same
3355 // registers used to pass 'inreg' arguments so watch out for those.
3356 if (!Subtarget->is64Bit() &&
3357 ((!isa<GlobalAddressSDNode>(Callee) &&
3358 !isa<ExternalSymbolSDNode>(Callee)) ||
3359 DAG.getTarget().getRelocationModel() == Reloc::PIC_)) {
3360 unsigned NumInRegs = 0;
3361 // In PIC we need an extra register to formulate the address computation
3363 unsigned MaxInRegs =
3364 (DAG.getTarget().getRelocationModel() == Reloc::PIC_) ? 2 : 3;
3366 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3367 CCValAssign &VA = ArgLocs[i];
3370 unsigned Reg = VA.getLocReg();
3373 case X86::EAX: case X86::EDX: case X86::ECX:
3374 if (++NumInRegs == MaxInRegs)
3386 X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
3387 const TargetLibraryInfo *libInfo) const {
3388 return X86::createFastISel(funcInfo, libInfo);
3391 //===----------------------------------------------------------------------===//
3392 // Other Lowering Hooks
3393 //===----------------------------------------------------------------------===//
3395 static bool MayFoldLoad(SDValue Op) {
3396 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode());
3399 static bool MayFoldIntoStore(SDValue Op) {
3400 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin());
3403 static bool isTargetShuffle(unsigned Opcode) {
3405 default: return false;
3406 case X86ISD::PSHUFB:
3407 case X86ISD::PSHUFD:
3408 case X86ISD::PSHUFHW:
3409 case X86ISD::PSHUFLW:
3411 case X86ISD::PALIGNR:
3412 case X86ISD::MOVLHPS:
3413 case X86ISD::MOVLHPD:
3414 case X86ISD::MOVHLPS:
3415 case X86ISD::MOVLPS:
3416 case X86ISD::MOVLPD:
3417 case X86ISD::MOVSHDUP:
3418 case X86ISD::MOVSLDUP:
3419 case X86ISD::MOVDDUP:
3422 case X86ISD::UNPCKL:
3423 case X86ISD::UNPCKH:
3424 case X86ISD::VPERMILP:
3425 case X86ISD::VPERM2X128:
3426 case X86ISD::VPERMI:
3431 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3432 SDValue V1, SelectionDAG &DAG) {
3434 default: llvm_unreachable("Unknown x86 shuffle node");
3435 case X86ISD::MOVSHDUP:
3436 case X86ISD::MOVSLDUP:
3437 case X86ISD::MOVDDUP:
3438 return DAG.getNode(Opc, dl, VT, V1);
3442 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3443 SDValue V1, unsigned TargetMask,
3444 SelectionDAG &DAG) {
3446 default: llvm_unreachable("Unknown x86 shuffle node");
3447 case X86ISD::PSHUFD:
3448 case X86ISD::PSHUFHW:
3449 case X86ISD::PSHUFLW:
3450 case X86ISD::VPERMILP:
3451 case X86ISD::VPERMI:
3452 return DAG.getNode(Opc, dl, VT, V1, DAG.getConstant(TargetMask, MVT::i8));
3456 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3457 SDValue V1, SDValue V2, unsigned TargetMask,
3458 SelectionDAG &DAG) {
3460 default: llvm_unreachable("Unknown x86 shuffle node");
3461 case X86ISD::PALIGNR:
3462 case X86ISD::VALIGN:
3464 case X86ISD::VPERM2X128:
3465 return DAG.getNode(Opc, dl, VT, V1, V2,
3466 DAG.getConstant(TargetMask, MVT::i8));
3470 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3471 SDValue V1, SDValue V2, SelectionDAG &DAG) {
3473 default: llvm_unreachable("Unknown x86 shuffle node");
3474 case X86ISD::MOVLHPS:
3475 case X86ISD::MOVLHPD:
3476 case X86ISD::MOVHLPS:
3477 case X86ISD::MOVLPS:
3478 case X86ISD::MOVLPD:
3481 case X86ISD::UNPCKL:
3482 case X86ISD::UNPCKH:
3483 return DAG.getNode(Opc, dl, VT, V1, V2);
3487 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
3488 MachineFunction &MF = DAG.getMachineFunction();
3489 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
3490 DAG.getSubtarget().getRegisterInfo());
3491 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
3492 int ReturnAddrIndex = FuncInfo->getRAIndex();
3494 if (ReturnAddrIndex == 0) {
3495 // Set up a frame object for the return address.
3496 unsigned SlotSize = RegInfo->getSlotSize();
3497 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize,
3500 FuncInfo->setRAIndex(ReturnAddrIndex);
3503 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
3506 bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
3507 bool hasSymbolicDisplacement) {
3508 // Offset should fit into 32 bit immediate field.
3509 if (!isInt<32>(Offset))
3512 // If we don't have a symbolic displacement - we don't have any extra
3514 if (!hasSymbolicDisplacement)
3517 // FIXME: Some tweaks might be needed for medium code model.
3518 if (M != CodeModel::Small && M != CodeModel::Kernel)
3521 // For small code model we assume that latest object is 16MB before end of 31
3522 // bits boundary. We may also accept pretty large negative constants knowing
3523 // that all objects are in the positive half of address space.
3524 if (M == CodeModel::Small && Offset < 16*1024*1024)
3527 // For kernel code model we know that all object resist in the negative half
3528 // of 32bits address space. We may not accept negative offsets, since they may
3529 // be just off and we may accept pretty large positive ones.
3530 if (M == CodeModel::Kernel && Offset > 0)
3536 /// isCalleePop - Determines whether the callee is required to pop its
3537 /// own arguments. Callee pop is necessary to support tail calls.
3538 bool X86::isCalleePop(CallingConv::ID CallingConv,
3539 bool is64Bit, bool IsVarArg, bool TailCallOpt) {
3543 switch (CallingConv) {
3546 case CallingConv::X86_StdCall:
3548 case CallingConv::X86_FastCall:
3550 case CallingConv::X86_ThisCall:
3552 case CallingConv::Fast:
3554 case CallingConv::GHC:
3556 case CallingConv::HiPE:
3561 /// \brief Return true if the condition is an unsigned comparison operation.
3562 static bool isX86CCUnsigned(unsigned X86CC) {
3564 default: llvm_unreachable("Invalid integer condition!");
3565 case X86::COND_E: return true;
3566 case X86::COND_G: return false;
3567 case X86::COND_GE: return false;
3568 case X86::COND_L: return false;
3569 case X86::COND_LE: return false;
3570 case X86::COND_NE: return true;
3571 case X86::COND_B: return true;
3572 case X86::COND_A: return true;
3573 case X86::COND_BE: return true;
3574 case X86::COND_AE: return true;
3576 llvm_unreachable("covered switch fell through?!");
3579 /// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86
3580 /// specific condition code, returning the condition code and the LHS/RHS of the
3581 /// comparison to make.
3582 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
3583 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
3585 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
3586 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
3587 // X > -1 -> X == 0, jump !sign.
3588 RHS = DAG.getConstant(0, RHS.getValueType());
3589 return X86::COND_NS;
3591 if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
3592 // X < 0 -> X == 0, jump on sign.
3595 if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
3597 RHS = DAG.getConstant(0, RHS.getValueType());
3598 return X86::COND_LE;
3602 switch (SetCCOpcode) {
3603 default: llvm_unreachable("Invalid integer condition!");
3604 case ISD::SETEQ: return X86::COND_E;
3605 case ISD::SETGT: return X86::COND_G;
3606 case ISD::SETGE: return X86::COND_GE;
3607 case ISD::SETLT: return X86::COND_L;
3608 case ISD::SETLE: return X86::COND_LE;
3609 case ISD::SETNE: return X86::COND_NE;
3610 case ISD::SETULT: return X86::COND_B;
3611 case ISD::SETUGT: return X86::COND_A;
3612 case ISD::SETULE: return X86::COND_BE;
3613 case ISD::SETUGE: return X86::COND_AE;
3617 // First determine if it is required or is profitable to flip the operands.
3619 // If LHS is a foldable load, but RHS is not, flip the condition.
3620 if (ISD::isNON_EXTLoad(LHS.getNode()) &&
3621 !ISD::isNON_EXTLoad(RHS.getNode())) {
3622 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
3623 std::swap(LHS, RHS);
3626 switch (SetCCOpcode) {
3632 std::swap(LHS, RHS);
3636 // On a floating point condition, the flags are set as follows:
3638 // 0 | 0 | 0 | X > Y
3639 // 0 | 0 | 1 | X < Y
3640 // 1 | 0 | 0 | X == Y
3641 // 1 | 1 | 1 | unordered
3642 switch (SetCCOpcode) {
3643 default: llvm_unreachable("Condcode should be pre-legalized away");
3645 case ISD::SETEQ: return X86::COND_E;
3646 case ISD::SETOLT: // flipped
3648 case ISD::SETGT: return X86::COND_A;
3649 case ISD::SETOLE: // flipped
3651 case ISD::SETGE: return X86::COND_AE;
3652 case ISD::SETUGT: // flipped
3654 case ISD::SETLT: return X86::COND_B;
3655 case ISD::SETUGE: // flipped
3657 case ISD::SETLE: return X86::COND_BE;
3659 case ISD::SETNE: return X86::COND_NE;
3660 case ISD::SETUO: return X86::COND_P;
3661 case ISD::SETO: return X86::COND_NP;
3663 case ISD::SETUNE: return X86::COND_INVALID;
3667 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
3668 /// code. Current x86 isa includes the following FP cmov instructions:
3669 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
3670 static bool hasFPCMov(unsigned X86CC) {
3686 /// isFPImmLegal - Returns true if the target can instruction select the
3687 /// specified FP immediate natively. If false, the legalizer will
3688 /// materialize the FP immediate as a load from a constant pool.
3689 bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
3690 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
3691 if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
3697 /// \brief Returns true if it is beneficial to convert a load of a constant
3698 /// to just the constant itself.
3699 bool X86TargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
3701 assert(Ty->isIntegerTy());
3703 unsigned BitSize = Ty->getPrimitiveSizeInBits();
3704 if (BitSize == 0 || BitSize > 64)
3709 /// isUndefOrInRange - Return true if Val is undef or if its value falls within
3710 /// the specified range (L, H].
3711 static bool isUndefOrInRange(int Val, int Low, int Hi) {
3712 return (Val < 0) || (Val >= Low && Val < Hi);
3715 /// isUndefOrEqual - Val is either less than zero (undef) or equal to the
3716 /// specified value.
3717 static bool isUndefOrEqual(int Val, int CmpVal) {
3718 return (Val < 0 || Val == CmpVal);
3721 /// isSequentialOrUndefInRange - Return true if every element in Mask, beginning
3722 /// from position Pos and ending in Pos+Size, falls within the specified
3723 /// sequential range (L, L+Pos]. or is undef.
3724 static bool isSequentialOrUndefInRange(ArrayRef<int> Mask,
3725 unsigned Pos, unsigned Size, int Low) {
3726 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low)
3727 if (!isUndefOrEqual(Mask[i], Low))
3732 /// isPSHUFDMask - Return true if the node specifies a shuffle of elements that
3733 /// is suitable for input to PSHUFD or PSHUFW. That is, it doesn't reference
3734 /// the second operand.
3735 static bool isPSHUFDMask(ArrayRef<int> Mask, MVT VT) {
3736 if (VT == MVT::v4f32 || VT == MVT::v4i32 )
3737 return (Mask[0] < 4 && Mask[1] < 4 && Mask[2] < 4 && Mask[3] < 4);
3738 if (VT == MVT::v2f64 || VT == MVT::v2i64)
3739 return (Mask[0] < 2 && Mask[1] < 2);
3743 /// isPSHUFHWMask - Return true if the node specifies a shuffle of elements that
3744 /// is suitable for input to PSHUFHW.
3745 static bool isPSHUFHWMask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
3746 if (VT != MVT::v8i16 && (!HasInt256 || VT != MVT::v16i16))
3749 // Lower quadword copied in order or undef.
3750 if (!isSequentialOrUndefInRange(Mask, 0, 4, 0))
3753 // Upper quadword shuffled.
3754 for (unsigned i = 4; i != 8; ++i)
3755 if (!isUndefOrInRange(Mask[i], 4, 8))
3758 if (VT == MVT::v16i16) {
3759 // Lower quadword copied in order or undef.
3760 if (!isSequentialOrUndefInRange(Mask, 8, 4, 8))
3763 // Upper quadword shuffled.
3764 for (unsigned i = 12; i != 16; ++i)
3765 if (!isUndefOrInRange(Mask[i], 12, 16))
3772 /// isPSHUFLWMask - Return true if the node specifies a shuffle of elements that
3773 /// is suitable for input to PSHUFLW.
3774 static bool isPSHUFLWMask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
3775 if (VT != MVT::v8i16 && (!HasInt256 || VT != MVT::v16i16))
3778 // Upper quadword copied in order.
3779 if (!isSequentialOrUndefInRange(Mask, 4, 4, 4))
3782 // Lower quadword shuffled.
3783 for (unsigned i = 0; i != 4; ++i)
3784 if (!isUndefOrInRange(Mask[i], 0, 4))
3787 if (VT == MVT::v16i16) {
3788 // Upper quadword copied in order.
3789 if (!isSequentialOrUndefInRange(Mask, 12, 4, 12))
3792 // Lower quadword shuffled.
3793 for (unsigned i = 8; i != 12; ++i)
3794 if (!isUndefOrInRange(Mask[i], 8, 12))
3801 /// \brief Return true if the mask specifies a shuffle of elements that is
3802 /// suitable for input to intralane (palignr) or interlane (valign) vector
3804 static bool isAlignrMask(ArrayRef<int> Mask, MVT VT, bool InterLane) {
3805 unsigned NumElts = VT.getVectorNumElements();
3806 unsigned NumLanes = InterLane ? 1: VT.getSizeInBits()/128;
3807 unsigned NumLaneElts = NumElts/NumLanes;
3809 // Do not handle 64-bit element shuffles with palignr.
3810 if (NumLaneElts == 2)
3813 for (unsigned l = 0; l != NumElts; l+=NumLaneElts) {
3815 for (i = 0; i != NumLaneElts; ++i) {
3820 // Lane is all undef, go to next lane
3821 if (i == NumLaneElts)
3824 int Start = Mask[i+l];
3826 // Make sure its in this lane in one of the sources
3827 if (!isUndefOrInRange(Start, l, l+NumLaneElts) &&
3828 !isUndefOrInRange(Start, l+NumElts, l+NumElts+NumLaneElts))
3831 // If not lane 0, then we must match lane 0
3832 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Start, Mask[i]+l))
3835 // Correct second source to be contiguous with first source
3836 if (Start >= (int)NumElts)
3837 Start -= NumElts - NumLaneElts;
3839 // Make sure we're shifting in the right direction.
3840 if (Start <= (int)(i+l))
3845 // Check the rest of the elements to see if they are consecutive.
3846 for (++i; i != NumLaneElts; ++i) {
3847 int Idx = Mask[i+l];
3849 // Make sure its in this lane
3850 if (!isUndefOrInRange(Idx, l, l+NumLaneElts) &&
3851 !isUndefOrInRange(Idx, l+NumElts, l+NumElts+NumLaneElts))
3854 // If not lane 0, then we must match lane 0
3855 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Idx, Mask[i]+l))
3858 if (Idx >= (int)NumElts)
3859 Idx -= NumElts - NumLaneElts;
3861 if (!isUndefOrEqual(Idx, Start+i))
3870 /// \brief Return true if the node specifies a shuffle of elements that is
3871 /// suitable for input to PALIGNR.
3872 static bool isPALIGNRMask(ArrayRef<int> Mask, MVT VT,
3873 const X86Subtarget *Subtarget) {
3874 if ((VT.is128BitVector() && !Subtarget->hasSSSE3()) ||
3875 (VT.is256BitVector() && !Subtarget->hasInt256()) ||
3876 VT.is512BitVector())
3877 // FIXME: Add AVX512BW.
3880 return isAlignrMask(Mask, VT, false);
3883 /// \brief Return true if the node specifies a shuffle of elements that is
3884 /// suitable for input to VALIGN.
3885 static bool isVALIGNMask(ArrayRef<int> Mask, MVT VT,
3886 const X86Subtarget *Subtarget) {
3887 // FIXME: Add AVX512VL.
3888 if (!VT.is512BitVector() || !Subtarget->hasAVX512())
3890 return isAlignrMask(Mask, VT, true);
3893 /// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming
3894 /// the two vector operands have swapped position.
3895 static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask,
3896 unsigned NumElems) {
3897 for (unsigned i = 0; i != NumElems; ++i) {
3901 else if (idx < (int)NumElems)
3902 Mask[i] = idx + NumElems;
3904 Mask[i] = idx - NumElems;
3908 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
3909 /// specifies a shuffle of elements that is suitable for input to 128/256-bit
3910 /// SHUFPS and SHUFPD. If Commuted is true, then it checks for sources to be
3911 /// reverse of what x86 shuffles want.
3912 static bool isSHUFPMask(ArrayRef<int> Mask, MVT VT, bool Commuted = false) {
3914 unsigned NumElems = VT.getVectorNumElements();
3915 unsigned NumLanes = VT.getSizeInBits()/128;
3916 unsigned NumLaneElems = NumElems/NumLanes;
3918 if (NumLaneElems != 2 && NumLaneElems != 4)
3921 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
3922 bool symetricMaskRequired =
3923 (VT.getSizeInBits() >= 256) && (EltSize == 32);
3925 // VSHUFPSY divides the resulting vector into 4 chunks.
3926 // The sources are also splitted into 4 chunks, and each destination
3927 // chunk must come from a different source chunk.
3929 // SRC1 => X7 X6 X5 X4 X3 X2 X1 X0
3930 // SRC2 => Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y9
3932 // DST => Y7..Y4, Y7..Y4, X7..X4, X7..X4,
3933 // Y3..Y0, Y3..Y0, X3..X0, X3..X0
3935 // VSHUFPDY divides the resulting vector into 4 chunks.
3936 // The sources are also splitted into 4 chunks, and each destination
3937 // chunk must come from a different source chunk.
3939 // SRC1 => X3 X2 X1 X0
3940 // SRC2 => Y3 Y2 Y1 Y0
3942 // DST => Y3..Y2, X3..X2, Y1..Y0, X1..X0
3944 SmallVector<int, 4> MaskVal(NumLaneElems, -1);
3945 unsigned HalfLaneElems = NumLaneElems/2;
3946 for (unsigned l = 0; l != NumElems; l += NumLaneElems) {
3947 for (unsigned i = 0; i != NumLaneElems; ++i) {
3948 int Idx = Mask[i+l];
3949 unsigned RngStart = l + ((Commuted == (i<HalfLaneElems)) ? NumElems : 0);
3950 if (!isUndefOrInRange(Idx, RngStart, RngStart+NumLaneElems))
3952 // For VSHUFPSY, the mask of the second half must be the same as the
3953 // first but with the appropriate offsets. This works in the same way as
3954 // VPERMILPS works with masks.
3955 if (!symetricMaskRequired || Idx < 0)
3957 if (MaskVal[i] < 0) {
3958 MaskVal[i] = Idx - l;
3961 if ((signed)(Idx - l) != MaskVal[i])
3969 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
3970 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
3971 static bool isMOVHLPSMask(ArrayRef<int> Mask, MVT VT) {
3972 if (!VT.is128BitVector())
3975 unsigned NumElems = VT.getVectorNumElements();
3980 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3
3981 return isUndefOrEqual(Mask[0], 6) &&
3982 isUndefOrEqual(Mask[1], 7) &&
3983 isUndefOrEqual(Mask[2], 2) &&
3984 isUndefOrEqual(Mask[3], 3);
3987 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
3988 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
3990 static bool isMOVHLPS_v_undef_Mask(ArrayRef<int> Mask, MVT VT) {
3991 if (!VT.is128BitVector())
3994 unsigned NumElems = VT.getVectorNumElements();
3999 return isUndefOrEqual(Mask[0], 2) &&
4000 isUndefOrEqual(Mask[1], 3) &&
4001 isUndefOrEqual(Mask[2], 2) &&
4002 isUndefOrEqual(Mask[3], 3);
4005 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
4006 /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
4007 static bool isMOVLPMask(ArrayRef<int> Mask, MVT VT) {
4008 if (!VT.is128BitVector())
4011 unsigned NumElems = VT.getVectorNumElements();
4013 if (NumElems != 2 && NumElems != 4)
4016 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4017 if (!isUndefOrEqual(Mask[i], i + NumElems))
4020 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i)
4021 if (!isUndefOrEqual(Mask[i], i))
4027 /// isMOVLHPSMask - Return true if the specified VECTOR_SHUFFLE operand
4028 /// specifies a shuffle of elements that is suitable for input to MOVLHPS.
4029 static bool isMOVLHPSMask(ArrayRef<int> Mask, MVT VT) {
4030 if (!VT.is128BitVector())
4033 unsigned NumElems = VT.getVectorNumElements();
4035 if (NumElems != 2 && NumElems != 4)
4038 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4039 if (!isUndefOrEqual(Mask[i], i))
4042 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4043 if (!isUndefOrEqual(Mask[i + e], i + NumElems))
4049 /// isINSERTPSMask - Return true if the specified VECTOR_SHUFFLE operand
4050 /// specifies a shuffle of elements that is suitable for input to INSERTPS.
4051 /// i. e: If all but one element come from the same vector.
4052 static bool isINSERTPSMask(ArrayRef<int> Mask, MVT VT) {
4053 // TODO: Deal with AVX's VINSERTPS
4054 if (!VT.is128BitVector() || (VT != MVT::v4f32 && VT != MVT::v4i32))
4057 unsigned CorrectPosV1 = 0;
4058 unsigned CorrectPosV2 = 0;
4059 for (int i = 0, e = (int)VT.getVectorNumElements(); i != e; ++i) {
4060 if (Mask[i] == -1) {
4068 else if (Mask[i] == i + 4)
4072 if (CorrectPosV1 == 3 || CorrectPosV2 == 3)
4073 // We have 3 elements (undefs count as elements from any vector) from one
4074 // vector, and one from another.
4081 // Some special combinations that can be optimized.
4084 SDValue Compact8x32ShuffleNode(ShuffleVectorSDNode *SVOp,
4085 SelectionDAG &DAG) {
4086 MVT VT = SVOp->getSimpleValueType(0);
4089 if (VT != MVT::v8i32 && VT != MVT::v8f32)
4092 ArrayRef<int> Mask = SVOp->getMask();
4094 // These are the special masks that may be optimized.
4095 static const int MaskToOptimizeEven[] = {0, 8, 2, 10, 4, 12, 6, 14};
4096 static const int MaskToOptimizeOdd[] = {1, 9, 3, 11, 5, 13, 7, 15};
4097 bool MatchEvenMask = true;
4098 bool MatchOddMask = true;
4099 for (int i=0; i<8; ++i) {
4100 if (!isUndefOrEqual(Mask[i], MaskToOptimizeEven[i]))
4101 MatchEvenMask = false;
4102 if (!isUndefOrEqual(Mask[i], MaskToOptimizeOdd[i]))
4103 MatchOddMask = false;
4106 if (!MatchEvenMask && !MatchOddMask)
4109 SDValue UndefNode = DAG.getNode(ISD::UNDEF, dl, VT);
4111 SDValue Op0 = SVOp->getOperand(0);
4112 SDValue Op1 = SVOp->getOperand(1);
4114 if (MatchEvenMask) {
4115 // Shift the second operand right to 32 bits.
4116 static const int ShiftRightMask[] = {-1, 0, -1, 2, -1, 4, -1, 6 };
4117 Op1 = DAG.getVectorShuffle(VT, dl, Op1, UndefNode, ShiftRightMask);
4119 // Shift the first operand left to 32 bits.
4120 static const int ShiftLeftMask[] = {1, -1, 3, -1, 5, -1, 7, -1 };
4121 Op0 = DAG.getVectorShuffle(VT, dl, Op0, UndefNode, ShiftLeftMask);
4123 static const int BlendMask[] = {0, 9, 2, 11, 4, 13, 6, 15};
4124 return DAG.getVectorShuffle(VT, dl, Op0, Op1, BlendMask);
4127 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
4128 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
4129 static bool isUNPCKLMask(ArrayRef<int> Mask, MVT VT,
4130 bool HasInt256, bool V2IsSplat = false) {
4132 assert(VT.getSizeInBits() >= 128 &&
4133 "Unsupported vector type for unpckl");
4135 // AVX defines UNPCK* to operate independently on 128-bit lanes.
4137 unsigned NumOf256BitLanes;
4138 unsigned NumElts = VT.getVectorNumElements();
4139 if (VT.is256BitVector()) {
4140 if (NumElts != 4 && NumElts != 8 &&
4141 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4144 NumOf256BitLanes = 1;
4145 } else if (VT.is512BitVector()) {
4146 assert(VT.getScalarType().getSizeInBits() >= 32 &&
4147 "Unsupported vector type for unpckh");
4149 NumOf256BitLanes = 2;
4152 NumOf256BitLanes = 1;
4155 unsigned NumEltsInStride = NumElts/NumOf256BitLanes;
4156 unsigned NumLaneElts = NumEltsInStride/NumLanes;
4158 for (unsigned l256 = 0; l256 < NumOf256BitLanes; l256 += 1) {
4159 for (unsigned l = 0; l != NumEltsInStride; l += NumLaneElts) {
4160 for (unsigned i = 0, j = l; i != NumLaneElts; i += 2, ++j) {
4161 int BitI = Mask[l256*NumEltsInStride+l+i];
4162 int BitI1 = Mask[l256*NumEltsInStride+l+i+1];
4163 if (!isUndefOrEqual(BitI, j+l256*NumElts))
4165 if (V2IsSplat && !isUndefOrEqual(BitI1, NumElts))
4167 if (!isUndefOrEqual(BitI1, j+l256*NumElts+NumEltsInStride))
4175 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
4176 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
4177 static bool isUNPCKHMask(ArrayRef<int> Mask, MVT VT,
4178 bool HasInt256, bool V2IsSplat = false) {
4179 assert(VT.getSizeInBits() >= 128 &&
4180 "Unsupported vector type for unpckh");
4182 // AVX defines UNPCK* to operate independently on 128-bit lanes.
4184 unsigned NumOf256BitLanes;
4185 unsigned NumElts = VT.getVectorNumElements();
4186 if (VT.is256BitVector()) {
4187 if (NumElts != 4 && NumElts != 8 &&
4188 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4191 NumOf256BitLanes = 1;
4192 } else if (VT.is512BitVector()) {
4193 assert(VT.getScalarType().getSizeInBits() >= 32 &&
4194 "Unsupported vector type for unpckh");
4196 NumOf256BitLanes = 2;
4199 NumOf256BitLanes = 1;
4202 unsigned NumEltsInStride = NumElts/NumOf256BitLanes;
4203 unsigned NumLaneElts = NumEltsInStride/NumLanes;
4205 for (unsigned l256 = 0; l256 < NumOf256BitLanes; l256 += 1) {
4206 for (unsigned l = 0; l != NumEltsInStride; l += NumLaneElts) {
4207 for (unsigned i = 0, j = l+NumLaneElts/2; i != NumLaneElts; i += 2, ++j) {
4208 int BitI = Mask[l256*NumEltsInStride+l+i];
4209 int BitI1 = Mask[l256*NumEltsInStride+l+i+1];
4210 if (!isUndefOrEqual(BitI, j+l256*NumElts))
4212 if (V2IsSplat && !isUndefOrEqual(BitI1, NumElts))
4214 if (!isUndefOrEqual(BitI1, j+l256*NumElts+NumEltsInStride))
4222 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
4223 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
4225 static bool isUNPCKL_v_undef_Mask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
4226 unsigned NumElts = VT.getVectorNumElements();
4227 bool Is256BitVec = VT.is256BitVector();
4229 if (VT.is512BitVector())
4231 assert((VT.is128BitVector() || VT.is256BitVector()) &&
4232 "Unsupported vector type for unpckh");
4234 if (Is256BitVec && NumElts != 4 && NumElts != 8 &&
4235 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4238 // For 256-bit i64/f64, use MOVDDUPY instead, so reject the matching pattern
4239 // FIXME: Need a better way to get rid of this, there's no latency difference
4240 // between UNPCKLPD and MOVDDUP, the later should always be checked first and
4241 // the former later. We should also remove the "_undef" special mask.
4242 if (NumElts == 4 && Is256BitVec)
4245 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
4246 // independently on 128-bit lanes.
4247 unsigned NumLanes = VT.getSizeInBits()/128;
4248 unsigned NumLaneElts = NumElts/NumLanes;
4250 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4251 for (unsigned i = 0, j = l; i != NumLaneElts; i += 2, ++j) {
4252 int BitI = Mask[l+i];
4253 int BitI1 = Mask[l+i+1];
4255 if (!isUndefOrEqual(BitI, j))
4257 if (!isUndefOrEqual(BitI1, j))
4265 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
4266 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
4268 static bool isUNPCKH_v_undef_Mask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
4269 unsigned NumElts = VT.getVectorNumElements();
4271 if (VT.is512BitVector())
4274 assert((VT.is128BitVector() || VT.is256BitVector()) &&
4275 "Unsupported vector type for unpckh");
4277 if (VT.is256BitVector() && NumElts != 4 && NumElts != 8 &&
4278 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4281 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
4282 // independently on 128-bit lanes.
4283 unsigned NumLanes = VT.getSizeInBits()/128;
4284 unsigned NumLaneElts = NumElts/NumLanes;
4286 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4287 for (unsigned i = 0, j = l+NumLaneElts/2; i != NumLaneElts; i += 2, ++j) {
4288 int BitI = Mask[l+i];
4289 int BitI1 = Mask[l+i+1];
4290 if (!isUndefOrEqual(BitI, j))
4292 if (!isUndefOrEqual(BitI1, j))
4299 // Match for INSERTI64x4 INSERTF64x4 instructions (src0[0], src1[0]) or
4300 // (src1[0], src0[1]), manipulation with 256-bit sub-vectors
4301 static bool isINSERT64x4Mask(ArrayRef<int> Mask, MVT VT, unsigned int *Imm) {
4302 if (!VT.is512BitVector())
4305 unsigned NumElts = VT.getVectorNumElements();
4306 unsigned HalfSize = NumElts/2;
4307 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, 0)) {
4308 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, NumElts)) {
4313 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, NumElts)) {
4314 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, HalfSize)) {
4322 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
4323 /// specifies a shuffle of elements that is suitable for input to MOVSS,
4324 /// MOVSD, and MOVD, i.e. setting the lowest element.
4325 static bool isMOVLMask(ArrayRef<int> Mask, EVT VT) {
4326 if (VT.getVectorElementType().getSizeInBits() < 32)
4328 if (!VT.is128BitVector())
4331 unsigned NumElts = VT.getVectorNumElements();
4333 if (!isUndefOrEqual(Mask[0], NumElts))
4336 for (unsigned i = 1; i != NumElts; ++i)
4337 if (!isUndefOrEqual(Mask[i], i))
4343 /// isVPERM2X128Mask - Match 256-bit shuffles where the elements are considered
4344 /// as permutations between 128-bit chunks or halves. As an example: this
4346 /// vector_shuffle <4, 5, 6, 7, 12, 13, 14, 15>
4347 /// The first half comes from the second half of V1 and the second half from the
4348 /// the second half of V2.
4349 static bool isVPERM2X128Mask(ArrayRef<int> Mask, MVT VT, bool HasFp256) {
4350 if (!HasFp256 || !VT.is256BitVector())
4353 // The shuffle result is divided into half A and half B. In total the two
4354 // sources have 4 halves, namely: C, D, E, F. The final values of A and
4355 // B must come from C, D, E or F.
4356 unsigned HalfSize = VT.getVectorNumElements()/2;
4357 bool MatchA = false, MatchB = false;
4359 // Check if A comes from one of C, D, E, F.
4360 for (unsigned Half = 0; Half != 4; ++Half) {
4361 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, Half*HalfSize)) {
4367 // Check if B comes from one of C, D, E, F.
4368 for (unsigned Half = 0; Half != 4; ++Half) {
4369 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, Half*HalfSize)) {
4375 return MatchA && MatchB;
4378 /// getShuffleVPERM2X128Immediate - Return the appropriate immediate to shuffle
4379 /// the specified VECTOR_MASK mask with VPERM2F128/VPERM2I128 instructions.
4380 static unsigned getShuffleVPERM2X128Immediate(ShuffleVectorSDNode *SVOp) {
4381 MVT VT = SVOp->getSimpleValueType(0);
4383 unsigned HalfSize = VT.getVectorNumElements()/2;
4385 unsigned FstHalf = 0, SndHalf = 0;
4386 for (unsigned i = 0; i < HalfSize; ++i) {
4387 if (SVOp->getMaskElt(i) > 0) {
4388 FstHalf = SVOp->getMaskElt(i)/HalfSize;
4392 for (unsigned i = HalfSize; i < HalfSize*2; ++i) {
4393 if (SVOp->getMaskElt(i) > 0) {
4394 SndHalf = SVOp->getMaskElt(i)/HalfSize;
4399 return (FstHalf | (SndHalf << 4));
4402 // Symetric in-lane mask. Each lane has 4 elements (for imm8)
4403 static bool isPermImmMask(ArrayRef<int> Mask, MVT VT, unsigned& Imm8) {
4404 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4408 unsigned NumElts = VT.getVectorNumElements();
4410 if (VT.is128BitVector() || (VT.is256BitVector() && EltSize == 64)) {
4411 for (unsigned i = 0; i != NumElts; ++i) {
4414 Imm8 |= Mask[i] << (i*2);
4419 unsigned LaneSize = 4;
4420 SmallVector<int, 4> MaskVal(LaneSize, -1);
4422 for (unsigned l = 0; l != NumElts; l += LaneSize) {
4423 for (unsigned i = 0; i != LaneSize; ++i) {
4424 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize))
4428 if (MaskVal[i] < 0) {
4429 MaskVal[i] = Mask[i+l] - l;
4430 Imm8 |= MaskVal[i] << (i*2);
4433 if (Mask[i+l] != (signed)(MaskVal[i]+l))
4440 /// isVPERMILPMask - Return true if the specified VECTOR_SHUFFLE operand
4441 /// specifies a shuffle of elements that is suitable for input to VPERMILPD*.
4442 /// Note that VPERMIL mask matching is different depending whether theunderlying
4443 /// type is 32 or 64. In the VPERMILPS the high half of the mask should point
4444 /// to the same elements of the low, but to the higher half of the source.
4445 /// In VPERMILPD the two lanes could be shuffled independently of each other
4446 /// with the same restriction that lanes can't be crossed. Also handles PSHUFDY.
4447 static bool isVPERMILPMask(ArrayRef<int> Mask, MVT VT) {
4448 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4449 if (VT.getSizeInBits() < 256 || EltSize < 32)
4451 bool symetricMaskRequired = (EltSize == 32);
4452 unsigned NumElts = VT.getVectorNumElements();
4454 unsigned NumLanes = VT.getSizeInBits()/128;
4455 unsigned LaneSize = NumElts/NumLanes;
4456 // 2 or 4 elements in one lane
4458 SmallVector<int, 4> ExpectedMaskVal(LaneSize, -1);
4459 for (unsigned l = 0; l != NumElts; l += LaneSize) {
4460 for (unsigned i = 0; i != LaneSize; ++i) {
4461 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize))
4463 if (symetricMaskRequired) {
4464 if (ExpectedMaskVal[i] < 0 && Mask[i+l] >= 0) {
4465 ExpectedMaskVal[i] = Mask[i+l] - l;
4468 if (!isUndefOrEqual(Mask[i+l], ExpectedMaskVal[i]+l))
4476 /// isCommutedMOVLMask - Returns true if the shuffle mask is except the reverse
4477 /// of what x86 movss want. X86 movs requires the lowest element to be lowest
4478 /// element of vector 2 and the other elements to come from vector 1 in order.
4479 static bool isCommutedMOVLMask(ArrayRef<int> Mask, MVT VT,
4480 bool V2IsSplat = false, bool V2IsUndef = false) {
4481 if (!VT.is128BitVector())
4484 unsigned NumOps = VT.getVectorNumElements();
4485 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16)
4488 if (!isUndefOrEqual(Mask[0], 0))
4491 for (unsigned i = 1; i != NumOps; ++i)
4492 if (!(isUndefOrEqual(Mask[i], i+NumOps) ||
4493 (V2IsUndef && isUndefOrInRange(Mask[i], NumOps, NumOps*2)) ||
4494 (V2IsSplat && isUndefOrEqual(Mask[i], NumOps))))
4500 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4501 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
4502 /// Masks to match: <1, 1, 3, 3> or <1, 1, 3, 3, 5, 5, 7, 7>
4503 static bool isMOVSHDUPMask(ArrayRef<int> Mask, MVT VT,
4504 const X86Subtarget *Subtarget) {
4505 if (!Subtarget->hasSSE3())
4508 unsigned NumElems = VT.getVectorNumElements();
4510 if ((VT.is128BitVector() && NumElems != 4) ||
4511 (VT.is256BitVector() && NumElems != 8) ||
4512 (VT.is512BitVector() && NumElems != 16))
4515 // "i+1" is the value the indexed mask element must have
4516 for (unsigned i = 0; i != NumElems; i += 2)
4517 if (!isUndefOrEqual(Mask[i], i+1) ||
4518 !isUndefOrEqual(Mask[i+1], i+1))
4524 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4525 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
4526 /// Masks to match: <0, 0, 2, 2> or <0, 0, 2, 2, 4, 4, 6, 6>
4527 static bool isMOVSLDUPMask(ArrayRef<int> Mask, MVT VT,
4528 const X86Subtarget *Subtarget) {
4529 if (!Subtarget->hasSSE3())
4532 unsigned NumElems = VT.getVectorNumElements();
4534 if ((VT.is128BitVector() && NumElems != 4) ||
4535 (VT.is256BitVector() && NumElems != 8) ||
4536 (VT.is512BitVector() && NumElems != 16))
4539 // "i" is the value the indexed mask element must have
4540 for (unsigned i = 0; i != NumElems; i += 2)
4541 if (!isUndefOrEqual(Mask[i], i) ||
4542 !isUndefOrEqual(Mask[i+1], i))
4548 /// isMOVDDUPYMask - Return true if the specified VECTOR_SHUFFLE operand
4549 /// specifies a shuffle of elements that is suitable for input to 256-bit
4550 /// version of MOVDDUP.
4551 static bool isMOVDDUPYMask(ArrayRef<int> Mask, MVT VT, bool HasFp256) {
4552 if (!HasFp256 || !VT.is256BitVector())
4555 unsigned NumElts = VT.getVectorNumElements();
4559 for (unsigned i = 0; i != NumElts/2; ++i)
4560 if (!isUndefOrEqual(Mask[i], 0))
4562 for (unsigned i = NumElts/2; i != NumElts; ++i)
4563 if (!isUndefOrEqual(Mask[i], NumElts/2))
4568 /// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4569 /// specifies a shuffle of elements that is suitable for input to 128-bit
4570 /// version of MOVDDUP.
4571 static bool isMOVDDUPMask(ArrayRef<int> Mask, MVT VT) {
4572 if (!VT.is128BitVector())
4575 unsigned e = VT.getVectorNumElements() / 2;
4576 for (unsigned i = 0; i != e; ++i)
4577 if (!isUndefOrEqual(Mask[i], i))
4579 for (unsigned i = 0; i != e; ++i)
4580 if (!isUndefOrEqual(Mask[e+i], i))
4585 /// isVEXTRACTIndex - Return true if the specified
4586 /// EXTRACT_SUBVECTOR operand specifies a vector extract that is
4587 /// suitable for instruction that extract 128 or 256 bit vectors
4588 static bool isVEXTRACTIndex(SDNode *N, unsigned vecWidth) {
4589 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4590 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4593 // The index should be aligned on a vecWidth-bit boundary.
4595 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4597 MVT VT = N->getSimpleValueType(0);
4598 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4599 bool Result = (Index * ElSize) % vecWidth == 0;
4604 /// isVINSERTIndex - Return true if the specified INSERT_SUBVECTOR
4605 /// operand specifies a subvector insert that is suitable for input to
4606 /// insertion of 128 or 256-bit subvectors
4607 static bool isVINSERTIndex(SDNode *N, unsigned vecWidth) {
4608 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4609 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4611 // The index should be aligned on a vecWidth-bit boundary.
4613 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4615 MVT VT = N->getSimpleValueType(0);
4616 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4617 bool Result = (Index * ElSize) % vecWidth == 0;
4622 bool X86::isVINSERT128Index(SDNode *N) {
4623 return isVINSERTIndex(N, 128);
4626 bool X86::isVINSERT256Index(SDNode *N) {
4627 return isVINSERTIndex(N, 256);
4630 bool X86::isVEXTRACT128Index(SDNode *N) {
4631 return isVEXTRACTIndex(N, 128);
4634 bool X86::isVEXTRACT256Index(SDNode *N) {
4635 return isVEXTRACTIndex(N, 256);
4638 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
4639 /// the specified VECTOR_SHUFFLE mask with PSHUF* and SHUFP* instructions.
4640 /// Handles 128-bit and 256-bit.
4641 static unsigned getShuffleSHUFImmediate(ShuffleVectorSDNode *N) {
4642 MVT VT = N->getSimpleValueType(0);
4644 assert((VT.getSizeInBits() >= 128) &&
4645 "Unsupported vector type for PSHUF/SHUFP");
4647 // Handle 128 and 256-bit vector lengths. AVX defines PSHUF/SHUFP to operate
4648 // independently on 128-bit lanes.
4649 unsigned NumElts = VT.getVectorNumElements();
4650 unsigned NumLanes = VT.getSizeInBits()/128;
4651 unsigned NumLaneElts = NumElts/NumLanes;
4653 assert((NumLaneElts == 2 || NumLaneElts == 4 || NumLaneElts == 8) &&
4654 "Only supports 2, 4 or 8 elements per lane");
4656 unsigned Shift = (NumLaneElts >= 4) ? 1 : 0;
4658 for (unsigned i = 0; i != NumElts; ++i) {
4659 int Elt = N->getMaskElt(i);
4660 if (Elt < 0) continue;
4661 Elt &= NumLaneElts - 1;
4662 unsigned ShAmt = (i << Shift) % 8;
4663 Mask |= Elt << ShAmt;
4669 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
4670 /// the specified VECTOR_SHUFFLE mask with the PSHUFHW instruction.
4671 static unsigned getShufflePSHUFHWImmediate(ShuffleVectorSDNode *N) {
4672 MVT VT = N->getSimpleValueType(0);
4674 assert((VT == MVT::v8i16 || VT == MVT::v16i16) &&
4675 "Unsupported vector type for PSHUFHW");
4677 unsigned NumElts = VT.getVectorNumElements();
4680 for (unsigned l = 0; l != NumElts; l += 8) {
4681 // 8 nodes per lane, but we only care about the last 4.
4682 for (unsigned i = 0; i < 4; ++i) {
4683 int Elt = N->getMaskElt(l+i+4);
4684 if (Elt < 0) continue;
4685 Elt &= 0x3; // only 2-bits.
4686 Mask |= Elt << (i * 2);
4693 /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
4694 /// the specified VECTOR_SHUFFLE mask with the PSHUFLW instruction.
4695 static unsigned getShufflePSHUFLWImmediate(ShuffleVectorSDNode *N) {
4696 MVT VT = N->getSimpleValueType(0);
4698 assert((VT == MVT::v8i16 || VT == MVT::v16i16) &&
4699 "Unsupported vector type for PSHUFHW");
4701 unsigned NumElts = VT.getVectorNumElements();
4704 for (unsigned l = 0; l != NumElts; l += 8) {
4705 // 8 nodes per lane, but we only care about the first 4.
4706 for (unsigned i = 0; i < 4; ++i) {
4707 int Elt = N->getMaskElt(l+i);
4708 if (Elt < 0) continue;
4709 Elt &= 0x3; // only 2-bits
4710 Mask |= Elt << (i * 2);
4717 /// \brief Return the appropriate immediate to shuffle the specified
4718 /// VECTOR_SHUFFLE mask with the PALIGNR (if InterLane is false) or with
4719 /// VALIGN (if Interlane is true) instructions.
4720 static unsigned getShuffleAlignrImmediate(ShuffleVectorSDNode *SVOp,
4722 MVT VT = SVOp->getSimpleValueType(0);
4723 unsigned EltSize = InterLane ? 1 :
4724 VT.getVectorElementType().getSizeInBits() >> 3;
4726 unsigned NumElts = VT.getVectorNumElements();
4727 unsigned NumLanes = VT.is512BitVector() ? 1 : VT.getSizeInBits()/128;
4728 unsigned NumLaneElts = NumElts/NumLanes;
4732 for (i = 0; i != NumElts; ++i) {
4733 Val = SVOp->getMaskElt(i);
4737 if (Val >= (int)NumElts)
4738 Val -= NumElts - NumLaneElts;
4740 assert(Val - i > 0 && "PALIGNR imm should be positive");
4741 return (Val - i) * EltSize;
4744 /// \brief Return the appropriate immediate to shuffle the specified
4745 /// VECTOR_SHUFFLE mask with the PALIGNR instruction.
4746 static unsigned getShufflePALIGNRImmediate(ShuffleVectorSDNode *SVOp) {
4747 return getShuffleAlignrImmediate(SVOp, false);
4750 /// \brief Return the appropriate immediate to shuffle the specified
4751 /// VECTOR_SHUFFLE mask with the VALIGN instruction.
4752 static unsigned getShuffleVALIGNImmediate(ShuffleVectorSDNode *SVOp) {
4753 return getShuffleAlignrImmediate(SVOp, true);
4757 static unsigned getExtractVEXTRACTImmediate(SDNode *N, unsigned vecWidth) {
4758 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4759 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4760 llvm_unreachable("Illegal extract subvector for VEXTRACT");
4763 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4765 MVT VecVT = N->getOperand(0).getSimpleValueType();
4766 MVT ElVT = VecVT.getVectorElementType();
4768 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4769 return Index / NumElemsPerChunk;
4772 static unsigned getInsertVINSERTImmediate(SDNode *N, unsigned vecWidth) {
4773 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4774 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4775 llvm_unreachable("Illegal insert subvector for VINSERT");
4778 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4780 MVT VecVT = N->getSimpleValueType(0);
4781 MVT ElVT = VecVT.getVectorElementType();
4783 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4784 return Index / NumElemsPerChunk;
4787 /// getExtractVEXTRACT128Immediate - Return the appropriate immediate
4788 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF128
4789 /// and VINSERTI128 instructions.
4790 unsigned X86::getExtractVEXTRACT128Immediate(SDNode *N) {
4791 return getExtractVEXTRACTImmediate(N, 128);
4794 /// getExtractVEXTRACT256Immediate - Return the appropriate immediate
4795 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF64x4
4796 /// and VINSERTI64x4 instructions.
4797 unsigned X86::getExtractVEXTRACT256Immediate(SDNode *N) {
4798 return getExtractVEXTRACTImmediate(N, 256);
4801 /// getInsertVINSERT128Immediate - Return the appropriate immediate
4802 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF128
4803 /// and VINSERTI128 instructions.
4804 unsigned X86::getInsertVINSERT128Immediate(SDNode *N) {
4805 return getInsertVINSERTImmediate(N, 128);
4808 /// getInsertVINSERT256Immediate - Return the appropriate immediate
4809 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF46x4
4810 /// and VINSERTI64x4 instructions.
4811 unsigned X86::getInsertVINSERT256Immediate(SDNode *N) {
4812 return getInsertVINSERTImmediate(N, 256);
4815 /// isZero - Returns true if Elt is a constant integer zero
4816 static bool isZero(SDValue V) {
4817 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
4818 return C && C->isNullValue();
4821 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
4823 bool X86::isZeroNode(SDValue Elt) {
4826 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Elt))
4827 return CFP->getValueAPF().isPosZero();
4831 /// ShouldXformToMOVHLPS - Return true if the node should be transformed to
4832 /// match movhlps. The lower half elements should come from upper half of
4833 /// V1 (and in order), and the upper half elements should come from the upper
4834 /// half of V2 (and in order).
4835 static bool ShouldXformToMOVHLPS(ArrayRef<int> Mask, MVT VT) {
4836 if (!VT.is128BitVector())
4838 if (VT.getVectorNumElements() != 4)
4840 for (unsigned i = 0, e = 2; i != e; ++i)
4841 if (!isUndefOrEqual(Mask[i], i+2))
4843 for (unsigned i = 2; i != 4; ++i)
4844 if (!isUndefOrEqual(Mask[i], i+4))
4849 /// isScalarLoadToVector - Returns true if the node is a scalar load that
4850 /// is promoted to a vector. It also returns the LoadSDNode by reference if
4852 static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = nullptr) {
4853 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR)
4855 N = N->getOperand(0).getNode();
4856 if (!ISD::isNON_EXTLoad(N))
4859 *LD = cast<LoadSDNode>(N);
4863 // Test whether the given value is a vector value which will be legalized
4865 static bool WillBeConstantPoolLoad(SDNode *N) {
4866 if (N->getOpcode() != ISD::BUILD_VECTOR)
4869 // Check for any non-constant elements.
4870 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
4871 switch (N->getOperand(i).getNode()->getOpcode()) {
4873 case ISD::ConstantFP:
4880 // Vectors of all-zeros and all-ones are materialized with special
4881 // instructions rather than being loaded.
4882 return !ISD::isBuildVectorAllZeros(N) &&
4883 !ISD::isBuildVectorAllOnes(N);
4886 /// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to
4887 /// match movlp{s|d}. The lower half elements should come from lower half of
4888 /// V1 (and in order), and the upper half elements should come from the upper
4889 /// half of V2 (and in order). And since V1 will become the source of the
4890 /// MOVLP, it must be either a vector load or a scalar load to vector.
4891 static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2,
4892 ArrayRef<int> Mask, MVT VT) {
4893 if (!VT.is128BitVector())
4896 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1))
4898 // Is V2 is a vector load, don't do this transformation. We will try to use
4899 // load folding shufps op.
4900 if (ISD::isNON_EXTLoad(V2) || WillBeConstantPoolLoad(V2))
4903 unsigned NumElems = VT.getVectorNumElements();
4905 if (NumElems != 2 && NumElems != 4)
4907 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4908 if (!isUndefOrEqual(Mask[i], i))
4910 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i)
4911 if (!isUndefOrEqual(Mask[i], i+NumElems))
4916 /// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
4917 /// to an zero vector.
4918 /// FIXME: move to dag combiner / method on ShuffleVectorSDNode
4919 static bool isZeroShuffle(ShuffleVectorSDNode *N) {
4920 SDValue V1 = N->getOperand(0);
4921 SDValue V2 = N->getOperand(1);
4922 unsigned NumElems = N->getValueType(0).getVectorNumElements();
4923 for (unsigned i = 0; i != NumElems; ++i) {
4924 int Idx = N->getMaskElt(i);
4925 if (Idx >= (int)NumElems) {
4926 unsigned Opc = V2.getOpcode();
4927 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode()))
4929 if (Opc != ISD::BUILD_VECTOR ||
4930 !X86::isZeroNode(V2.getOperand(Idx-NumElems)))
4932 } else if (Idx >= 0) {
4933 unsigned Opc = V1.getOpcode();
4934 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode()))
4936 if (Opc != ISD::BUILD_VECTOR ||
4937 !X86::isZeroNode(V1.getOperand(Idx)))
4944 /// getZeroVector - Returns a vector of specified type with all zero elements.
4946 static SDValue getZeroVector(EVT VT, const X86Subtarget *Subtarget,
4947 SelectionDAG &DAG, SDLoc dl) {
4948 assert(VT.isVector() && "Expected a vector type");
4950 // Always build SSE zero vectors as <4 x i32> bitcasted
4951 // to their dest type. This ensures they get CSE'd.
4953 if (VT.is128BitVector()) { // SSE
4954 if (Subtarget->hasSSE2()) { // SSE2
4955 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
4956 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4958 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
4959 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
4961 } else if (VT.is256BitVector()) { // AVX
4962 if (Subtarget->hasInt256()) { // AVX2
4963 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
4964 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4965 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
4967 // 256-bit logic and arithmetic instructions in AVX are all
4968 // floating-point, no support for integer ops. Emit fp zeroed vectors.
4969 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
4970 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4971 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops);
4973 } else if (VT.is512BitVector()) { // AVX-512
4974 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
4975 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst,
4976 Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4977 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i32, Ops);
4978 } else if (VT.getScalarType() == MVT::i1) {
4979 assert(VT.getVectorNumElements() <= 16 && "Unexpected vector type");
4980 SDValue Cst = DAG.getTargetConstant(0, MVT::i1);
4981 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
4982 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
4984 llvm_unreachable("Unexpected vector type");
4986 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
4989 /// getOnesVector - Returns a vector of specified type with all bits set.
4990 /// Always build ones vectors as <4 x i32> or <8 x i32>. For 256-bit types with
4991 /// no AVX2 supprt, use two <4 x i32> inserted in a <8 x i32> appropriately.
4992 /// Then bitcast to their original type, ensuring they get CSE'd.
4993 static SDValue getOnesVector(MVT VT, bool HasInt256, SelectionDAG &DAG,
4995 assert(VT.isVector() && "Expected a vector type");
4997 SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32);
4999 if (VT.is256BitVector()) {
5000 if (HasInt256) { // AVX2
5001 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5002 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
5004 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
5005 Vec = Concat128BitVectors(Vec, Vec, MVT::v8i32, 8, DAG, dl);
5007 } else if (VT.is128BitVector()) {
5008 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
5010 llvm_unreachable("Unexpected vector type");
5012 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
5015 /// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements
5016 /// that point to V2 points to its first element.
5017 static void NormalizeMask(SmallVectorImpl<int> &Mask, unsigned NumElems) {
5018 for (unsigned i = 0; i != NumElems; ++i) {
5019 if (Mask[i] > (int)NumElems) {
5025 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
5026 /// operation of specified width.
5027 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
5029 unsigned NumElems = VT.getVectorNumElements();
5030 SmallVector<int, 8> Mask;
5031 Mask.push_back(NumElems);
5032 for (unsigned i = 1; i != NumElems; ++i)
5034 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
5037 /// getUnpackl - Returns a vector_shuffle node for an unpackl operation.
5038 static SDValue getUnpackl(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
5040 unsigned NumElems = VT.getVectorNumElements();
5041 SmallVector<int, 8> Mask;
5042 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
5044 Mask.push_back(i + NumElems);
5046 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
5049 /// getUnpackh - Returns a vector_shuffle node for an unpackh operation.
5050 static SDValue getUnpackh(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
5052 unsigned NumElems = VT.getVectorNumElements();
5053 SmallVector<int, 8> Mask;
5054 for (unsigned i = 0, Half = NumElems/2; i != Half; ++i) {
5055 Mask.push_back(i + Half);
5056 Mask.push_back(i + NumElems + Half);
5058 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
5061 // PromoteSplati8i16 - All i16 and i8 vector types can't be used directly by
5062 // a generic shuffle instruction because the target has no such instructions.
5063 // Generate shuffles which repeat i16 and i8 several times until they can be
5064 // represented by v4f32 and then be manipulated by target suported shuffles.
5065 static SDValue PromoteSplati8i16(SDValue V, SelectionDAG &DAG, int &EltNo) {
5066 MVT VT = V.getSimpleValueType();
5067 int NumElems = VT.getVectorNumElements();
5070 while (NumElems > 4) {
5071 if (EltNo < NumElems/2) {
5072 V = getUnpackl(DAG, dl, VT, V, V);
5074 V = getUnpackh(DAG, dl, VT, V, V);
5075 EltNo -= NumElems/2;
5082 /// getLegalSplat - Generate a legal splat with supported x86 shuffles
5083 static SDValue getLegalSplat(SelectionDAG &DAG, SDValue V, int EltNo) {
5084 MVT VT = V.getSimpleValueType();
5087 if (VT.is128BitVector()) {
5088 V = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V);
5089 int SplatMask[4] = { EltNo, EltNo, EltNo, EltNo };
5090 V = DAG.getVectorShuffle(MVT::v4f32, dl, V, DAG.getUNDEF(MVT::v4f32),
5092 } else if (VT.is256BitVector()) {
5093 // To use VPERMILPS to splat scalars, the second half of indicies must
5094 // refer to the higher part, which is a duplication of the lower one,
5095 // because VPERMILPS can only handle in-lane permutations.
5096 int SplatMask[8] = { EltNo, EltNo, EltNo, EltNo,
5097 EltNo+4, EltNo+4, EltNo+4, EltNo+4 };
5099 V = DAG.getNode(ISD::BITCAST, dl, MVT::v8f32, V);
5100 V = DAG.getVectorShuffle(MVT::v8f32, dl, V, DAG.getUNDEF(MVT::v8f32),
5103 llvm_unreachable("Vector size not supported");
5105 return DAG.getNode(ISD::BITCAST, dl, VT, V);
5108 /// PromoteSplat - Splat is promoted to target supported vector shuffles.
5109 static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG) {
5110 MVT SrcVT = SV->getSimpleValueType(0);
5111 SDValue V1 = SV->getOperand(0);
5114 int EltNo = SV->getSplatIndex();
5115 int NumElems = SrcVT.getVectorNumElements();
5116 bool Is256BitVec = SrcVT.is256BitVector();
5118 assert(((SrcVT.is128BitVector() && NumElems > 4) || Is256BitVec) &&
5119 "Unknown how to promote splat for type");
5121 // Extract the 128-bit part containing the splat element and update
5122 // the splat element index when it refers to the higher register.
5124 V1 = Extract128BitVector(V1, EltNo, DAG, dl);
5125 if (EltNo >= NumElems/2)
5126 EltNo -= NumElems/2;
5129 // All i16 and i8 vector types can't be used directly by a generic shuffle
5130 // instruction because the target has no such instruction. Generate shuffles
5131 // which repeat i16 and i8 several times until they fit in i32, and then can
5132 // be manipulated by target suported shuffles.
5133 MVT EltVT = SrcVT.getVectorElementType();
5134 if (EltVT == MVT::i8 || EltVT == MVT::i16)
5135 V1 = PromoteSplati8i16(V1, DAG, EltNo);
5137 // Recreate the 256-bit vector and place the same 128-bit vector
5138 // into the low and high part. This is necessary because we want
5139 // to use VPERM* to shuffle the vectors
5141 V1 = DAG.getNode(ISD::CONCAT_VECTORS, dl, SrcVT, V1, V1);
5144 return getLegalSplat(DAG, V1, EltNo);
5147 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
5148 /// vector of zero or undef vector. This produces a shuffle where the low
5149 /// element of V2 is swizzled into the zero/undef vector, landing at element
5150 /// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
5151 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
5153 const X86Subtarget *Subtarget,
5154 SelectionDAG &DAG) {
5155 MVT VT = V2.getSimpleValueType();
5157 ? getZeroVector(VT, Subtarget, DAG, SDLoc(V2)) : DAG.getUNDEF(VT);
5158 unsigned NumElems = VT.getVectorNumElements();
5159 SmallVector<int, 16> MaskVec;
5160 for (unsigned i = 0; i != NumElems; ++i)
5161 // If this is the insertion idx, put the low elt of V2 here.
5162 MaskVec.push_back(i == Idx ? NumElems : i);
5163 return DAG.getVectorShuffle(VT, SDLoc(V2), V1, V2, &MaskVec[0]);
5166 /// getTargetShuffleMask - Calculates the shuffle mask corresponding to the
5167 /// target specific opcode. Returns true if the Mask could be calculated. Sets
5168 /// IsUnary to true if only uses one source. Note that this will set IsUnary for
5169 /// shuffles which use a single input multiple times, and in those cases it will
5170 /// adjust the mask to only have indices within that single input.
5171 static bool getTargetShuffleMask(SDNode *N, MVT VT,
5172 SmallVectorImpl<int> &Mask, bool &IsUnary) {
5173 unsigned NumElems = VT.getVectorNumElements();
5177 bool IsFakeUnary = false;
5178 switch(N->getOpcode()) {
5180 ImmN = N->getOperand(N->getNumOperands()-1);
5181 DecodeSHUFPMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5182 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5184 case X86ISD::UNPCKH:
5185 DecodeUNPCKHMask(VT, Mask);
5186 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5188 case X86ISD::UNPCKL:
5189 DecodeUNPCKLMask(VT, Mask);
5190 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5192 case X86ISD::MOVHLPS:
5193 DecodeMOVHLPSMask(NumElems, Mask);
5194 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5196 case X86ISD::MOVLHPS:
5197 DecodeMOVLHPSMask(NumElems, Mask);
5198 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5200 case X86ISD::PALIGNR:
5201 ImmN = N->getOperand(N->getNumOperands()-1);
5202 DecodePALIGNRMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5204 case X86ISD::PSHUFD:
5205 case X86ISD::VPERMILP:
5206 ImmN = N->getOperand(N->getNumOperands()-1);
5207 DecodePSHUFMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5210 case X86ISD::PSHUFHW:
5211 ImmN = N->getOperand(N->getNumOperands()-1);
5212 DecodePSHUFHWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5215 case X86ISD::PSHUFLW:
5216 ImmN = N->getOperand(N->getNumOperands()-1);
5217 DecodePSHUFLWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5220 case X86ISD::PSHUFB: {
5222 SDValue MaskNode = N->getOperand(1);
5223 while (MaskNode->getOpcode() == ISD::BITCAST)
5224 MaskNode = MaskNode->getOperand(0);
5226 if (MaskNode->getOpcode() == ISD::BUILD_VECTOR) {
5227 // If we have a build-vector, then things are easy.
5228 EVT VT = MaskNode.getValueType();
5229 assert(VT.isVector() &&
5230 "Can't produce a non-vector with a build_vector!");
5231 if (!VT.isInteger())
5234 int NumBytesPerElement = VT.getVectorElementType().getSizeInBits() / 8;
5236 SmallVector<uint64_t, 32> RawMask;
5237 for (int i = 0, e = MaskNode->getNumOperands(); i < e; ++i) {
5238 auto *CN = dyn_cast<ConstantSDNode>(MaskNode->getOperand(i));
5241 APInt MaskElement = CN->getAPIntValue();
5243 // We now have to decode the element which could be any integer size and
5244 // extract each byte of it.
5245 for (int j = 0; j < NumBytesPerElement; ++j) {
5246 // Note that this is x86 and so always little endian: the low byte is
5247 // the first byte of the mask.
5248 RawMask.push_back(MaskElement.getLoBits(8).getZExtValue());
5249 MaskElement = MaskElement.lshr(8);
5252 DecodePSHUFBMask(RawMask, Mask);
5256 auto *MaskLoad = dyn_cast<LoadSDNode>(MaskNode);
5260 SDValue Ptr = MaskLoad->getBasePtr();
5261 if (Ptr->getOpcode() == X86ISD::Wrapper)
5262 Ptr = Ptr->getOperand(0);
5264 auto *MaskCP = dyn_cast<ConstantPoolSDNode>(Ptr);
5265 if (!MaskCP || MaskCP->isMachineConstantPoolEntry())
5268 if (auto *C = dyn_cast<ConstantDataSequential>(MaskCP->getConstVal())) {
5269 // FIXME: Support AVX-512 here.
5270 if (!C->getType()->isVectorTy() ||
5271 (C->getNumElements() != 16 && C->getNumElements() != 32))
5274 assert(C->getType()->isVectorTy() && "Expected a vector constant.");
5275 DecodePSHUFBMask(C, Mask);
5281 case X86ISD::VPERMI:
5282 ImmN = N->getOperand(N->getNumOperands()-1);
5283 DecodeVPERMMask(cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5287 case X86ISD::MOVSD: {
5288 // The index 0 always comes from the first element of the second source,
5289 // this is why MOVSS and MOVSD are used in the first place. The other
5290 // elements come from the other positions of the first source vector
5291 Mask.push_back(NumElems);
5292 for (unsigned i = 1; i != NumElems; ++i) {
5297 case X86ISD::VPERM2X128:
5298 ImmN = N->getOperand(N->getNumOperands()-1);
5299 DecodeVPERM2X128Mask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5300 if (Mask.empty()) return false;
5302 case X86ISD::MOVDDUP:
5303 case X86ISD::MOVLHPD:
5304 case X86ISD::MOVLPD:
5305 case X86ISD::MOVLPS:
5306 case X86ISD::MOVSHDUP:
5307 case X86ISD::MOVSLDUP:
5308 // Not yet implemented
5310 default: llvm_unreachable("unknown target shuffle node");
5313 // If we have a fake unary shuffle, the shuffle mask is spread across two
5314 // inputs that are actually the same node. Re-map the mask to always point
5315 // into the first input.
5318 if (M >= (int)Mask.size())
5324 /// getShuffleScalarElt - Returns the scalar element that will make up the ith
5325 /// element of the result of the vector shuffle.
5326 static SDValue getShuffleScalarElt(SDNode *N, unsigned Index, SelectionDAG &DAG,
5329 return SDValue(); // Limit search depth.
5331 SDValue V = SDValue(N, 0);
5332 EVT VT = V.getValueType();
5333 unsigned Opcode = V.getOpcode();
5335 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars.
5336 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) {
5337 int Elt = SV->getMaskElt(Index);
5340 return DAG.getUNDEF(VT.getVectorElementType());
5342 unsigned NumElems = VT.getVectorNumElements();
5343 SDValue NewV = (Elt < (int)NumElems) ? SV->getOperand(0)
5344 : SV->getOperand(1);
5345 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG, Depth+1);
5348 // Recurse into target specific vector shuffles to find scalars.
5349 if (isTargetShuffle(Opcode)) {
5350 MVT ShufVT = V.getSimpleValueType();
5351 unsigned NumElems = ShufVT.getVectorNumElements();
5352 SmallVector<int, 16> ShuffleMask;
5355 if (!getTargetShuffleMask(N, ShufVT, ShuffleMask, IsUnary))
5358 int Elt = ShuffleMask[Index];
5360 return DAG.getUNDEF(ShufVT.getVectorElementType());
5362 SDValue NewV = (Elt < (int)NumElems) ? N->getOperand(0)
5364 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG,
5368 // Actual nodes that may contain scalar elements
5369 if (Opcode == ISD::BITCAST) {
5370 V = V.getOperand(0);
5371 EVT SrcVT = V.getValueType();
5372 unsigned NumElems = VT.getVectorNumElements();
5374 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems)
5378 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR)
5379 return (Index == 0) ? V.getOperand(0)
5380 : DAG.getUNDEF(VT.getVectorElementType());
5382 if (V.getOpcode() == ISD::BUILD_VECTOR)
5383 return V.getOperand(Index);
5388 /// getNumOfConsecutiveZeros - Return the number of elements of a vector
5389 /// shuffle operation which come from a consecutively from a zero. The
5390 /// search can start in two different directions, from left or right.
5391 /// We count undefs as zeros until PreferredNum is reached.
5392 static unsigned getNumOfConsecutiveZeros(ShuffleVectorSDNode *SVOp,
5393 unsigned NumElems, bool ZerosFromLeft,
5395 unsigned PreferredNum = -1U) {
5396 unsigned NumZeros = 0;
5397 for (unsigned i = 0; i != NumElems; ++i) {
5398 unsigned Index = ZerosFromLeft ? i : NumElems - i - 1;
5399 SDValue Elt = getShuffleScalarElt(SVOp, Index, DAG, 0);
5403 if (X86::isZeroNode(Elt))
5405 else if (Elt.getOpcode() == ISD::UNDEF) // Undef as zero up to PreferredNum.
5406 NumZeros = std::min(NumZeros + 1, PreferredNum);
5414 /// isShuffleMaskConsecutive - Check if the shuffle mask indicies [MaskI, MaskE)
5415 /// correspond consecutively to elements from one of the vector operands,
5416 /// starting from its index OpIdx. Also tell OpNum which source vector operand.
5418 bool isShuffleMaskConsecutive(ShuffleVectorSDNode *SVOp,
5419 unsigned MaskI, unsigned MaskE, unsigned OpIdx,
5420 unsigned NumElems, unsigned &OpNum) {
5421 bool SeenV1 = false;
5422 bool SeenV2 = false;
5424 for (unsigned i = MaskI; i != MaskE; ++i, ++OpIdx) {
5425 int Idx = SVOp->getMaskElt(i);
5426 // Ignore undef indicies
5430 if (Idx < (int)NumElems)
5435 // Only accept consecutive elements from the same vector
5436 if ((Idx % NumElems != OpIdx) || (SeenV1 && SeenV2))
5440 OpNum = SeenV1 ? 0 : 1;
5444 /// isVectorShiftRight - Returns true if the shuffle can be implemented as a
5445 /// logical left shift of a vector.
5446 static bool isVectorShiftRight(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5447 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5449 SVOp->getSimpleValueType(0).getVectorNumElements();
5450 unsigned NumZeros = getNumOfConsecutiveZeros(
5451 SVOp, NumElems, false /* check zeros from right */, DAG,
5452 SVOp->getMaskElt(0));
5458 // Considering the elements in the mask that are not consecutive zeros,
5459 // check if they consecutively come from only one of the source vectors.
5461 // V1 = {X, A, B, C} 0
5463 // vector_shuffle V1, V2 <1, 2, 3, X>
5465 if (!isShuffleMaskConsecutive(SVOp,
5466 0, // Mask Start Index
5467 NumElems-NumZeros, // Mask End Index(exclusive)
5468 NumZeros, // Where to start looking in the src vector
5469 NumElems, // Number of elements in vector
5470 OpSrc)) // Which source operand ?
5475 ShVal = SVOp->getOperand(OpSrc);
5479 /// isVectorShiftLeft - Returns true if the shuffle can be implemented as a
5480 /// logical left shift of a vector.
5481 static bool isVectorShiftLeft(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5482 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5484 SVOp->getSimpleValueType(0).getVectorNumElements();
5485 unsigned NumZeros = getNumOfConsecutiveZeros(
5486 SVOp, NumElems, true /* check zeros from left */, DAG,
5487 NumElems - SVOp->getMaskElt(NumElems - 1) - 1);
5493 // Considering the elements in the mask that are not consecutive zeros,
5494 // check if they consecutively come from only one of the source vectors.
5496 // 0 { A, B, X, X } = V2
5498 // vector_shuffle V1, V2 <X, X, 4, 5>
5500 if (!isShuffleMaskConsecutive(SVOp,
5501 NumZeros, // Mask Start Index
5502 NumElems, // Mask End Index(exclusive)
5503 0, // Where to start looking in the src vector
5504 NumElems, // Number of elements in vector
5505 OpSrc)) // Which source operand ?
5510 ShVal = SVOp->getOperand(OpSrc);
5514 /// isVectorShift - Returns true if the shuffle can be implemented as a
5515 /// logical left or right shift of a vector.
5516 static bool isVectorShift(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5517 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5518 // Although the logic below support any bitwidth size, there are no
5519 // shift instructions which handle more than 128-bit vectors.
5520 if (!SVOp->getSimpleValueType(0).is128BitVector())
5523 if (isVectorShiftLeft(SVOp, DAG, isLeft, ShVal, ShAmt) ||
5524 isVectorShiftRight(SVOp, DAG, isLeft, ShVal, ShAmt))
5530 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
5532 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
5533 unsigned NumNonZero, unsigned NumZero,
5535 const X86Subtarget* Subtarget,
5536 const TargetLowering &TLI) {
5543 for (unsigned i = 0; i < 16; ++i) {
5544 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
5545 if (ThisIsNonZero && First) {
5547 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
5549 V = DAG.getUNDEF(MVT::v8i16);
5554 SDValue ThisElt, LastElt;
5555 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
5556 if (LastIsNonZero) {
5557 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
5558 MVT::i16, Op.getOperand(i-1));
5560 if (ThisIsNonZero) {
5561 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
5562 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
5563 ThisElt, DAG.getConstant(8, MVT::i8));
5565 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
5569 if (ThisElt.getNode())
5570 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
5571 DAG.getIntPtrConstant(i/2));
5575 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V);
5578 /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
5580 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
5581 unsigned NumNonZero, unsigned NumZero,
5583 const X86Subtarget* Subtarget,
5584 const TargetLowering &TLI) {
5591 for (unsigned i = 0; i < 8; ++i) {
5592 bool isNonZero = (NonZeros & (1 << i)) != 0;
5596 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
5598 V = DAG.getUNDEF(MVT::v8i16);
5601 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
5602 MVT::v8i16, V, Op.getOperand(i),
5603 DAG.getIntPtrConstant(i));
5610 /// LowerBuildVectorv4x32 - Custom lower build_vector of v4i32 or v4f32.
5611 static SDValue LowerBuildVectorv4x32(SDValue Op, unsigned NumElems,
5612 unsigned NonZeros, unsigned NumNonZero,
5613 unsigned NumZero, SelectionDAG &DAG,
5614 const X86Subtarget *Subtarget,
5615 const TargetLowering &TLI) {
5616 // We know there's at least one non-zero element
5617 unsigned FirstNonZeroIdx = 0;
5618 SDValue FirstNonZero = Op->getOperand(FirstNonZeroIdx);
5619 while (FirstNonZero.getOpcode() == ISD::UNDEF ||
5620 X86::isZeroNode(FirstNonZero)) {
5622 FirstNonZero = Op->getOperand(FirstNonZeroIdx);
5625 if (FirstNonZero.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
5626 !isa<ConstantSDNode>(FirstNonZero.getOperand(1)))
5629 SDValue V = FirstNonZero.getOperand(0);
5630 MVT VVT = V.getSimpleValueType();
5631 if (!Subtarget->hasSSE41() || (VVT != MVT::v4f32 && VVT != MVT::v4i32))
5634 unsigned FirstNonZeroDst =
5635 cast<ConstantSDNode>(FirstNonZero.getOperand(1))->getZExtValue();
5636 unsigned CorrectIdx = FirstNonZeroDst == FirstNonZeroIdx;
5637 unsigned IncorrectIdx = CorrectIdx ? -1U : FirstNonZeroIdx;
5638 unsigned IncorrectDst = CorrectIdx ? -1U : FirstNonZeroDst;
5640 for (unsigned Idx = FirstNonZeroIdx + 1; Idx < NumElems; ++Idx) {
5641 SDValue Elem = Op.getOperand(Idx);
5642 if (Elem.getOpcode() == ISD::UNDEF || X86::isZeroNode(Elem))
5645 // TODO: What else can be here? Deal with it.
5646 if (Elem.getOpcode() != ISD::EXTRACT_VECTOR_ELT)
5649 // TODO: Some optimizations are still possible here
5650 // ex: Getting one element from a vector, and the rest from another.
5651 if (Elem.getOperand(0) != V)
5654 unsigned Dst = cast<ConstantSDNode>(Elem.getOperand(1))->getZExtValue();
5657 else if (IncorrectIdx == -1U) {
5661 // There was already one element with an incorrect index.
5662 // We can't optimize this case to an insertps.
5666 if (NumNonZero == CorrectIdx || NumNonZero == CorrectIdx + 1) {
5668 EVT VT = Op.getSimpleValueType();
5669 unsigned ElementMoveMask = 0;
5670 if (IncorrectIdx == -1U)
5671 ElementMoveMask = FirstNonZeroIdx << 6 | FirstNonZeroIdx << 4;
5673 ElementMoveMask = IncorrectDst << 6 | IncorrectIdx << 4;
5675 SDValue InsertpsMask =
5676 DAG.getIntPtrConstant(ElementMoveMask | (~NonZeros & 0xf));
5677 return DAG.getNode(X86ISD::INSERTPS, dl, VT, V, V, InsertpsMask);
5683 /// getVShift - Return a vector logical shift node.
5685 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
5686 unsigned NumBits, SelectionDAG &DAG,
5687 const TargetLowering &TLI, SDLoc dl) {
5688 assert(VT.is128BitVector() && "Unknown type for VShift");
5689 EVT ShVT = MVT::v2i64;
5690 unsigned Opc = isLeft ? X86ISD::VSHLDQ : X86ISD::VSRLDQ;
5691 SrcOp = DAG.getNode(ISD::BITCAST, dl, ShVT, SrcOp);
5692 return DAG.getNode(ISD::BITCAST, dl, VT,
5693 DAG.getNode(Opc, dl, ShVT, SrcOp,
5694 DAG.getConstant(NumBits,
5695 TLI.getScalarShiftAmountTy(SrcOp.getValueType()))));
5699 LowerAsSplatVectorLoad(SDValue SrcOp, MVT VT, SDLoc dl, SelectionDAG &DAG) {
5701 // Check if the scalar load can be widened into a vector load. And if
5702 // the address is "base + cst" see if the cst can be "absorbed" into
5703 // the shuffle mask.
5704 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) {
5705 SDValue Ptr = LD->getBasePtr();
5706 if (!ISD::isNormalLoad(LD) || LD->isVolatile())
5708 EVT PVT = LD->getValueType(0);
5709 if (PVT != MVT::i32 && PVT != MVT::f32)
5714 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) {
5715 FI = FINode->getIndex();
5717 } else if (DAG.isBaseWithConstantOffset(Ptr) &&
5718 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
5719 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
5720 Offset = Ptr.getConstantOperandVal(1);
5721 Ptr = Ptr.getOperand(0);
5726 // FIXME: 256-bit vector instructions don't require a strict alignment,
5727 // improve this code to support it better.
5728 unsigned RequiredAlign = VT.getSizeInBits()/8;
5729 SDValue Chain = LD->getChain();
5730 // Make sure the stack object alignment is at least 16 or 32.
5731 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
5732 if (DAG.InferPtrAlignment(Ptr) < RequiredAlign) {
5733 if (MFI->isFixedObjectIndex(FI)) {
5734 // Can't change the alignment. FIXME: It's possible to compute
5735 // the exact stack offset and reference FI + adjust offset instead.
5736 // If someone *really* cares about this. That's the way to implement it.
5739 MFI->setObjectAlignment(FI, RequiredAlign);
5743 // (Offset % 16 or 32) must be multiple of 4. Then address is then
5744 // Ptr + (Offset & ~15).
5747 if ((Offset % RequiredAlign) & 3)
5749 int64_t StartOffset = Offset & ~(RequiredAlign-1);
5751 Ptr = DAG.getNode(ISD::ADD, SDLoc(Ptr), Ptr.getValueType(),
5752 Ptr,DAG.getConstant(StartOffset, Ptr.getValueType()));
5754 int EltNo = (Offset - StartOffset) >> 2;
5755 unsigned NumElems = VT.getVectorNumElements();
5757 EVT NVT = EVT::getVectorVT(*DAG.getContext(), PVT, NumElems);
5758 SDValue V1 = DAG.getLoad(NVT, dl, Chain, Ptr,
5759 LD->getPointerInfo().getWithOffset(StartOffset),
5760 false, false, false, 0);
5762 SmallVector<int, 8> Mask;
5763 for (unsigned i = 0; i != NumElems; ++i)
5764 Mask.push_back(EltNo);
5766 return DAG.getVectorShuffle(NVT, dl, V1, DAG.getUNDEF(NVT), &Mask[0]);
5772 /// EltsFromConsecutiveLoads - Given the initializing elements 'Elts' of a
5773 /// vector of type 'VT', see if the elements can be replaced by a single large
5774 /// load which has the same value as a build_vector whose operands are 'elts'.
5776 /// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a
5778 /// FIXME: we'd also like to handle the case where the last elements are zero
5779 /// rather than undef via VZEXT_LOAD, but we do not detect that case today.
5780 /// There's even a handy isZeroNode for that purpose.
5781 static SDValue EltsFromConsecutiveLoads(EVT VT, SmallVectorImpl<SDValue> &Elts,
5782 SDLoc &DL, SelectionDAG &DAG,
5783 bool isAfterLegalize) {
5784 EVT EltVT = VT.getVectorElementType();
5785 unsigned NumElems = Elts.size();
5787 LoadSDNode *LDBase = nullptr;
5788 unsigned LastLoadedElt = -1U;
5790 // For each element in the initializer, see if we've found a load or an undef.
5791 // If we don't find an initial load element, or later load elements are
5792 // non-consecutive, bail out.
5793 for (unsigned i = 0; i < NumElems; ++i) {
5794 SDValue Elt = Elts[i];
5796 if (!Elt.getNode() ||
5797 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
5800 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
5802 LDBase = cast<LoadSDNode>(Elt.getNode());
5806 if (Elt.getOpcode() == ISD::UNDEF)
5809 LoadSDNode *LD = cast<LoadSDNode>(Elt);
5810 if (!DAG.isConsecutiveLoad(LD, LDBase, EltVT.getSizeInBits()/8, i))
5815 // If we have found an entire vector of loads and undefs, then return a large
5816 // load of the entire vector width starting at the base pointer. If we found
5817 // consecutive loads for the low half, generate a vzext_load node.
5818 if (LastLoadedElt == NumElems - 1) {
5820 if (isAfterLegalize &&
5821 !DAG.getTargetLoweringInfo().isOperationLegal(ISD::LOAD, VT))
5824 SDValue NewLd = SDValue();
5826 if (DAG.InferPtrAlignment(LDBase->getBasePtr()) >= 16)
5827 NewLd = DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
5828 LDBase->getPointerInfo(),
5829 LDBase->isVolatile(), LDBase->isNonTemporal(),
5830 LDBase->isInvariant(), 0);
5831 NewLd = DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
5832 LDBase->getPointerInfo(),
5833 LDBase->isVolatile(), LDBase->isNonTemporal(),
5834 LDBase->isInvariant(), LDBase->getAlignment());
5836 if (LDBase->hasAnyUseOfValue(1)) {
5837 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
5839 SDValue(NewLd.getNode(), 1));
5840 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
5841 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
5842 SDValue(NewLd.getNode(), 1));
5847 if (NumElems == 4 && LastLoadedElt == 1 &&
5848 DAG.getTargetLoweringInfo().isTypeLegal(MVT::v2i64)) {
5849 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
5850 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() };
5852 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys, Ops, MVT::i64,
5853 LDBase->getPointerInfo(),
5854 LDBase->getAlignment(),
5855 false/*isVolatile*/, true/*ReadMem*/,
5858 // Make sure the newly-created LOAD is in the same position as LDBase in
5859 // terms of dependency. We create a TokenFactor for LDBase and ResNode, and
5860 // update uses of LDBase's output chain to use the TokenFactor.
5861 if (LDBase->hasAnyUseOfValue(1)) {
5862 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
5863 SDValue(LDBase, 1), SDValue(ResNode.getNode(), 1));
5864 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
5865 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
5866 SDValue(ResNode.getNode(), 1));
5869 return DAG.getNode(ISD::BITCAST, DL, VT, ResNode);
5874 /// LowerVectorBroadcast - Attempt to use the vbroadcast instruction
5875 /// to generate a splat value for the following cases:
5876 /// 1. A splat BUILD_VECTOR which uses a single scalar load, or a constant.
5877 /// 2. A splat shuffle which uses a scalar_to_vector node which comes from
5878 /// a scalar load, or a constant.
5879 /// The VBROADCAST node is returned when a pattern is found,
5880 /// or SDValue() otherwise.
5881 static SDValue LowerVectorBroadcast(SDValue Op, const X86Subtarget* Subtarget,
5882 SelectionDAG &DAG) {
5883 if (!Subtarget->hasFp256())
5886 MVT VT = Op.getSimpleValueType();
5889 assert((VT.is128BitVector() || VT.is256BitVector() || VT.is512BitVector()) &&
5890 "Unsupported vector type for broadcast.");
5895 switch (Op.getOpcode()) {
5897 // Unknown pattern found.
5900 case ISD::BUILD_VECTOR: {
5901 auto *BVOp = cast<BuildVectorSDNode>(Op.getNode());
5902 BitVector UndefElements;
5903 SDValue Splat = BVOp->getSplatValue(&UndefElements);
5905 // We need a splat of a single value to use broadcast, and it doesn't
5906 // make any sense if the value is only in one element of the vector.
5907 if (!Splat || (VT.getVectorNumElements() - UndefElements.count()) <= 1)
5911 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
5912 Ld.getOpcode() == ISD::ConstantFP);
5914 // Make sure that all of the users of a non-constant load are from the
5915 // BUILD_VECTOR node.
5916 if (!ConstSplatVal && !BVOp->isOnlyUserOf(Ld.getNode()))
5921 case ISD::VECTOR_SHUFFLE: {
5922 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
5924 // Shuffles must have a splat mask where the first element is
5926 if ((!SVOp->isSplat()) || SVOp->getMaskElt(0) != 0)
5929 SDValue Sc = Op.getOperand(0);
5930 if (Sc.getOpcode() != ISD::SCALAR_TO_VECTOR &&
5931 Sc.getOpcode() != ISD::BUILD_VECTOR) {
5933 if (!Subtarget->hasInt256())
5936 // Use the register form of the broadcast instruction available on AVX2.
5937 if (VT.getSizeInBits() >= 256)
5938 Sc = Extract128BitVector(Sc, 0, DAG, dl);
5939 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Sc);
5942 Ld = Sc.getOperand(0);
5943 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
5944 Ld.getOpcode() == ISD::ConstantFP);
5946 // The scalar_to_vector node and the suspected
5947 // load node must have exactly one user.
5948 // Constants may have multiple users.
5950 // AVX-512 has register version of the broadcast
5951 bool hasRegVer = Subtarget->hasAVX512() && VT.is512BitVector() &&
5952 Ld.getValueType().getSizeInBits() >= 32;
5953 if (!ConstSplatVal && ((!Sc.hasOneUse() || !Ld.hasOneUse()) &&
5960 bool IsGE256 = (VT.getSizeInBits() >= 256);
5962 // Handle the broadcasting a single constant scalar from the constant pool
5963 // into a vector. On Sandybridge it is still better to load a constant vector
5964 // from the constant pool and not to broadcast it from a scalar.
5965 if (ConstSplatVal && Subtarget->hasInt256()) {
5966 EVT CVT = Ld.getValueType();
5967 assert(!CVT.isVector() && "Must not broadcast a vector type");
5968 unsigned ScalarSize = CVT.getSizeInBits();
5970 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64)) {
5971 const Constant *C = nullptr;
5972 if (ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Ld))
5973 C = CI->getConstantIntValue();
5974 else if (ConstantFPSDNode *CF = dyn_cast<ConstantFPSDNode>(Ld))
5975 C = CF->getConstantFPValue();
5977 assert(C && "Invalid constant type");
5979 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5980 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
5981 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
5982 Ld = DAG.getLoad(CVT, dl, DAG.getEntryNode(), CP,
5983 MachinePointerInfo::getConstantPool(),
5984 false, false, false, Alignment);
5986 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5990 bool IsLoad = ISD::isNormalLoad(Ld.getNode());
5991 unsigned ScalarSize = Ld.getValueType().getSizeInBits();
5993 // Handle AVX2 in-register broadcasts.
5994 if (!IsLoad && Subtarget->hasInt256() &&
5995 (ScalarSize == 32 || (IsGE256 && ScalarSize == 64)))
5996 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5998 // The scalar source must be a normal load.
6002 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64))
6003 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6005 // The integer check is needed for the 64-bit into 128-bit so it doesn't match
6006 // double since there is no vbroadcastsd xmm
6007 if (Subtarget->hasInt256() && Ld.getValueType().isInteger()) {
6008 if (ScalarSize == 8 || ScalarSize == 16 || ScalarSize == 64)
6009 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6012 // Unsupported broadcast.
6016 /// \brief For an EXTRACT_VECTOR_ELT with a constant index return the real
6017 /// underlying vector and index.
6019 /// Modifies \p ExtractedFromVec to the real vector and returns the real
6021 static int getUnderlyingExtractedFromVec(SDValue &ExtractedFromVec,
6023 int Idx = cast<ConstantSDNode>(ExtIdx)->getZExtValue();
6024 if (!isa<ShuffleVectorSDNode>(ExtractedFromVec))
6027 // For 256-bit vectors, LowerEXTRACT_VECTOR_ELT_SSE4 may have already
6029 // (extract_vector_elt (v8f32 %vreg1), Constant<6>)
6031 // (extract_vector_elt (vector_shuffle<2,u,u,u>
6032 // (extract_subvector (v8f32 %vreg0), Constant<4>),
6035 // In this case the vector is the extract_subvector expression and the index
6036 // is 2, as specified by the shuffle.
6037 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(ExtractedFromVec);
6038 SDValue ShuffleVec = SVOp->getOperand(0);
6039 MVT ShuffleVecVT = ShuffleVec.getSimpleValueType();
6040 assert(ShuffleVecVT.getVectorElementType() ==
6041 ExtractedFromVec.getSimpleValueType().getVectorElementType());
6043 int ShuffleIdx = SVOp->getMaskElt(Idx);
6044 if (isUndefOrInRange(ShuffleIdx, 0, ShuffleVecVT.getVectorNumElements())) {
6045 ExtractedFromVec = ShuffleVec;
6051 static SDValue buildFromShuffleMostly(SDValue Op, SelectionDAG &DAG) {
6052 MVT VT = Op.getSimpleValueType();
6054 // Skip if insert_vec_elt is not supported.
6055 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6056 if (!TLI.isOperationLegalOrCustom(ISD::INSERT_VECTOR_ELT, VT))
6060 unsigned NumElems = Op.getNumOperands();
6064 SmallVector<unsigned, 4> InsertIndices;
6065 SmallVector<int, 8> Mask(NumElems, -1);
6067 for (unsigned i = 0; i != NumElems; ++i) {
6068 unsigned Opc = Op.getOperand(i).getOpcode();
6070 if (Opc == ISD::UNDEF)
6073 if (Opc != ISD::EXTRACT_VECTOR_ELT) {
6074 // Quit if more than 1 elements need inserting.
6075 if (InsertIndices.size() > 1)
6078 InsertIndices.push_back(i);
6082 SDValue ExtractedFromVec = Op.getOperand(i).getOperand(0);
6083 SDValue ExtIdx = Op.getOperand(i).getOperand(1);
6084 // Quit if non-constant index.
6085 if (!isa<ConstantSDNode>(ExtIdx))
6087 int Idx = getUnderlyingExtractedFromVec(ExtractedFromVec, ExtIdx);
6089 // Quit if extracted from vector of different type.
6090 if (ExtractedFromVec.getValueType() != VT)
6093 if (!VecIn1.getNode())
6094 VecIn1 = ExtractedFromVec;
6095 else if (VecIn1 != ExtractedFromVec) {
6096 if (!VecIn2.getNode())
6097 VecIn2 = ExtractedFromVec;
6098 else if (VecIn2 != ExtractedFromVec)
6099 // Quit if more than 2 vectors to shuffle
6103 if (ExtractedFromVec == VecIn1)
6105 else if (ExtractedFromVec == VecIn2)
6106 Mask[i] = Idx + NumElems;
6109 if (!VecIn1.getNode())
6112 VecIn2 = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT);
6113 SDValue NV = DAG.getVectorShuffle(VT, DL, VecIn1, VecIn2, &Mask[0]);
6114 for (unsigned i = 0, e = InsertIndices.size(); i != e; ++i) {
6115 unsigned Idx = InsertIndices[i];
6116 NV = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VT, NV, Op.getOperand(Idx),
6117 DAG.getIntPtrConstant(Idx));
6123 // Lower BUILD_VECTOR operation for v8i1 and v16i1 types.
6125 X86TargetLowering::LowerBUILD_VECTORvXi1(SDValue Op, SelectionDAG &DAG) const {
6127 MVT VT = Op.getSimpleValueType();
6128 assert((VT.getVectorElementType() == MVT::i1) && (VT.getSizeInBits() <= 16) &&
6129 "Unexpected type in LowerBUILD_VECTORvXi1!");
6132 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
6133 SDValue Cst = DAG.getTargetConstant(0, MVT::i1);
6134 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
6135 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
6138 if (ISD::isBuildVectorAllOnes(Op.getNode())) {
6139 SDValue Cst = DAG.getTargetConstant(1, MVT::i1);
6140 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
6141 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
6144 bool AllContants = true;
6145 uint64_t Immediate = 0;
6146 int NonConstIdx = -1;
6147 bool IsSplat = true;
6148 unsigned NumNonConsts = 0;
6149 unsigned NumConsts = 0;
6150 for (unsigned idx = 0, e = Op.getNumOperands(); idx < e; ++idx) {
6151 SDValue In = Op.getOperand(idx);
6152 if (In.getOpcode() == ISD::UNDEF)
6154 if (!isa<ConstantSDNode>(In)) {
6155 AllContants = false;
6161 if (cast<ConstantSDNode>(In)->getZExtValue())
6162 Immediate |= (1ULL << idx);
6164 if (In != Op.getOperand(0))
6169 SDValue FullMask = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1,
6170 DAG.getConstant(Immediate, MVT::i16));
6171 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, FullMask,
6172 DAG.getIntPtrConstant(0));
6175 if (NumNonConsts == 1 && NonConstIdx != 0) {
6178 SDValue VecAsImm = DAG.getConstant(Immediate,
6179 MVT::getIntegerVT(VT.getSizeInBits()));
6180 DstVec = DAG.getNode(ISD::BITCAST, dl, VT, VecAsImm);
6183 DstVec = DAG.getUNDEF(VT);
6184 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, DstVec,
6185 Op.getOperand(NonConstIdx),
6186 DAG.getIntPtrConstant(NonConstIdx));
6188 if (!IsSplat && (NonConstIdx != 0))
6189 llvm_unreachable("Unsupported BUILD_VECTOR operation");
6190 MVT SelectVT = (VT == MVT::v16i1)? MVT::i16 : MVT::i8;
6193 Select = DAG.getNode(ISD::SELECT, dl, SelectVT, Op.getOperand(0),
6194 DAG.getConstant(-1, SelectVT),
6195 DAG.getConstant(0, SelectVT));
6197 Select = DAG.getNode(ISD::SELECT, dl, SelectVT, Op.getOperand(0),
6198 DAG.getConstant((Immediate | 1), SelectVT),
6199 DAG.getConstant(Immediate, SelectVT));
6200 return DAG.getNode(ISD::BITCAST, dl, VT, Select);
6203 /// \brief Return true if \p N implements a horizontal binop and return the
6204 /// operands for the horizontal binop into V0 and V1.
6206 /// This is a helper function of PerformBUILD_VECTORCombine.
6207 /// This function checks that the build_vector \p N in input implements a
6208 /// horizontal operation. Parameter \p Opcode defines the kind of horizontal
6209 /// operation to match.
6210 /// For example, if \p Opcode is equal to ISD::ADD, then this function
6211 /// checks if \p N implements a horizontal arithmetic add; if instead \p Opcode
6212 /// is equal to ISD::SUB, then this function checks if this is a horizontal
6215 /// This function only analyzes elements of \p N whose indices are
6216 /// in range [BaseIdx, LastIdx).
6217 static bool isHorizontalBinOp(const BuildVectorSDNode *N, unsigned Opcode,
6219 unsigned BaseIdx, unsigned LastIdx,
6220 SDValue &V0, SDValue &V1) {
6221 EVT VT = N->getValueType(0);
6223 assert(BaseIdx * 2 <= LastIdx && "Invalid Indices in input!");
6224 assert(VT.isVector() && VT.getVectorNumElements() >= LastIdx &&
6225 "Invalid Vector in input!");
6227 bool IsCommutable = (Opcode == ISD::ADD || Opcode == ISD::FADD);
6228 bool CanFold = true;
6229 unsigned ExpectedVExtractIdx = BaseIdx;
6230 unsigned NumElts = LastIdx - BaseIdx;
6231 V0 = DAG.getUNDEF(VT);
6232 V1 = DAG.getUNDEF(VT);
6234 // Check if N implements a horizontal binop.
6235 for (unsigned i = 0, e = NumElts; i != e && CanFold; ++i) {
6236 SDValue Op = N->getOperand(i + BaseIdx);
6239 if (Op->getOpcode() == ISD::UNDEF) {
6240 // Update the expected vector extract index.
6241 if (i * 2 == NumElts)
6242 ExpectedVExtractIdx = BaseIdx;
6243 ExpectedVExtractIdx += 2;
6247 CanFold = Op->getOpcode() == Opcode && Op->hasOneUse();
6252 SDValue Op0 = Op.getOperand(0);
6253 SDValue Op1 = Op.getOperand(1);
6255 // Try to match the following pattern:
6256 // (BINOP (extract_vector_elt A, I), (extract_vector_elt A, I+1))
6257 CanFold = (Op0.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
6258 Op1.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
6259 Op0.getOperand(0) == Op1.getOperand(0) &&
6260 isa<ConstantSDNode>(Op0.getOperand(1)) &&
6261 isa<ConstantSDNode>(Op1.getOperand(1)));
6265 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
6266 unsigned I1 = cast<ConstantSDNode>(Op1.getOperand(1))->getZExtValue();
6268 if (i * 2 < NumElts) {
6269 if (V0.getOpcode() == ISD::UNDEF)
6270 V0 = Op0.getOperand(0);
6272 if (V1.getOpcode() == ISD::UNDEF)
6273 V1 = Op0.getOperand(0);
6274 if (i * 2 == NumElts)
6275 ExpectedVExtractIdx = BaseIdx;
6278 SDValue Expected = (i * 2 < NumElts) ? V0 : V1;
6279 if (I0 == ExpectedVExtractIdx)
6280 CanFold = I1 == I0 + 1 && Op0.getOperand(0) == Expected;
6281 else if (IsCommutable && I1 == ExpectedVExtractIdx) {
6282 // Try to match the following dag sequence:
6283 // (BINOP (extract_vector_elt A, I+1), (extract_vector_elt A, I))
6284 CanFold = I0 == I1 + 1 && Op1.getOperand(0) == Expected;
6288 ExpectedVExtractIdx += 2;
6294 /// \brief Emit a sequence of two 128-bit horizontal add/sub followed by
6295 /// a concat_vector.
6297 /// This is a helper function of PerformBUILD_VECTORCombine.
6298 /// This function expects two 256-bit vectors called V0 and V1.
6299 /// At first, each vector is split into two separate 128-bit vectors.
6300 /// Then, the resulting 128-bit vectors are used to implement two
6301 /// horizontal binary operations.
6303 /// The kind of horizontal binary operation is defined by \p X86Opcode.
6305 /// \p Mode specifies how the 128-bit parts of V0 and V1 are passed in input to
6306 /// the two new horizontal binop.
6307 /// When Mode is set, the first horizontal binop dag node would take as input
6308 /// the lower 128-bit of V0 and the upper 128-bit of V0. The second
6309 /// horizontal binop dag node would take as input the lower 128-bit of V1
6310 /// and the upper 128-bit of V1.
6312 /// HADD V0_LO, V0_HI
6313 /// HADD V1_LO, V1_HI
6315 /// Otherwise, the first horizontal binop dag node takes as input the lower
6316 /// 128-bit of V0 and the lower 128-bit of V1, and the second horizontal binop
6317 /// dag node takes the the upper 128-bit of V0 and the upper 128-bit of V1.
6319 /// HADD V0_LO, V1_LO
6320 /// HADD V0_HI, V1_HI
6322 /// If \p isUndefLO is set, then the algorithm propagates UNDEF to the lower
6323 /// 128-bits of the result. If \p isUndefHI is set, then UNDEF is propagated to
6324 /// the upper 128-bits of the result.
6325 static SDValue ExpandHorizontalBinOp(const SDValue &V0, const SDValue &V1,
6326 SDLoc DL, SelectionDAG &DAG,
6327 unsigned X86Opcode, bool Mode,
6328 bool isUndefLO, bool isUndefHI) {
6329 EVT VT = V0.getValueType();
6330 assert(VT.is256BitVector() && VT == V1.getValueType() &&
6331 "Invalid nodes in input!");
6333 unsigned NumElts = VT.getVectorNumElements();
6334 SDValue V0_LO = Extract128BitVector(V0, 0, DAG, DL);
6335 SDValue V0_HI = Extract128BitVector(V0, NumElts/2, DAG, DL);
6336 SDValue V1_LO = Extract128BitVector(V1, 0, DAG, DL);
6337 SDValue V1_HI = Extract128BitVector(V1, NumElts/2, DAG, DL);
6338 EVT NewVT = V0_LO.getValueType();
6340 SDValue LO = DAG.getUNDEF(NewVT);
6341 SDValue HI = DAG.getUNDEF(NewVT);
6344 // Don't emit a horizontal binop if the result is expected to be UNDEF.
6345 if (!isUndefLO && V0->getOpcode() != ISD::UNDEF)
6346 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V0_HI);
6347 if (!isUndefHI && V1->getOpcode() != ISD::UNDEF)
6348 HI = DAG.getNode(X86Opcode, DL, NewVT, V1_LO, V1_HI);
6350 // Don't emit a horizontal binop if the result is expected to be UNDEF.
6351 if (!isUndefLO && (V0_LO->getOpcode() != ISD::UNDEF ||
6352 V1_LO->getOpcode() != ISD::UNDEF))
6353 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V1_LO);
6355 if (!isUndefHI && (V0_HI->getOpcode() != ISD::UNDEF ||
6356 V1_HI->getOpcode() != ISD::UNDEF))
6357 HI = DAG.getNode(X86Opcode, DL, NewVT, V0_HI, V1_HI);
6360 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LO, HI);
6363 /// \brief Try to fold a build_vector that performs an 'addsub' into the
6364 /// sequence of 'vadd + vsub + blendi'.
6365 static SDValue matchAddSub(const BuildVectorSDNode *BV, SelectionDAG &DAG,
6366 const X86Subtarget *Subtarget) {
6368 EVT VT = BV->getValueType(0);
6369 unsigned NumElts = VT.getVectorNumElements();
6370 SDValue InVec0 = DAG.getUNDEF(VT);
6371 SDValue InVec1 = DAG.getUNDEF(VT);
6373 assert((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v4f32 ||
6374 VT == MVT::v2f64) && "build_vector with an invalid type found!");
6376 // Don't try to emit a VSELECT that cannot be lowered into a blend.
6377 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6378 if (!TLI.isOperationLegalOrCustom(ISD::VSELECT, VT))
6381 // Odd-numbered elements in the input build vector are obtained from
6382 // adding two integer/float elements.
6383 // Even-numbered elements in the input build vector are obtained from
6384 // subtracting two integer/float elements.
6385 unsigned ExpectedOpcode = ISD::FSUB;
6386 unsigned NextExpectedOpcode = ISD::FADD;
6387 bool AddFound = false;
6388 bool SubFound = false;
6390 for (unsigned i = 0, e = NumElts; i != e; i++) {
6391 SDValue Op = BV->getOperand(i);
6393 // Skip 'undef' values.
6394 unsigned Opcode = Op.getOpcode();
6395 if (Opcode == ISD::UNDEF) {
6396 std::swap(ExpectedOpcode, NextExpectedOpcode);
6400 // Early exit if we found an unexpected opcode.
6401 if (Opcode != ExpectedOpcode)
6404 SDValue Op0 = Op.getOperand(0);
6405 SDValue Op1 = Op.getOperand(1);
6407 // Try to match the following pattern:
6408 // (BINOP (extract_vector_elt A, i), (extract_vector_elt B, i))
6409 // Early exit if we cannot match that sequence.
6410 if (Op0.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
6411 Op1.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
6412 !isa<ConstantSDNode>(Op0.getOperand(1)) ||
6413 !isa<ConstantSDNode>(Op1.getOperand(1)) ||
6414 Op0.getOperand(1) != Op1.getOperand(1))
6417 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
6421 // We found a valid add/sub node. Update the information accordingly.
6427 // Update InVec0 and InVec1.
6428 if (InVec0.getOpcode() == ISD::UNDEF)
6429 InVec0 = Op0.getOperand(0);
6430 if (InVec1.getOpcode() == ISD::UNDEF)
6431 InVec1 = Op1.getOperand(0);
6433 // Make sure that operands in input to each add/sub node always
6434 // come from a same pair of vectors.
6435 if (InVec0 != Op0.getOperand(0)) {
6436 if (ExpectedOpcode == ISD::FSUB)
6439 // FADD is commutable. Try to commute the operands
6440 // and then test again.
6441 std::swap(Op0, Op1);
6442 if (InVec0 != Op0.getOperand(0))
6446 if (InVec1 != Op1.getOperand(0))
6449 // Update the pair of expected opcodes.
6450 std::swap(ExpectedOpcode, NextExpectedOpcode);
6453 // Don't try to fold this build_vector into a VSELECT if it has
6454 // too many UNDEF operands.
6455 if (AddFound && SubFound && InVec0.getOpcode() != ISD::UNDEF &&
6456 InVec1.getOpcode() != ISD::UNDEF) {
6457 // Emit a sequence of vector add and sub followed by a VSELECT.
6458 // The new VSELECT will be lowered into a BLENDI.
6459 // At ISel stage, we pattern-match the sequence 'add + sub + BLENDI'
6460 // and emit a single ADDSUB instruction.
6461 SDValue Sub = DAG.getNode(ExpectedOpcode, DL, VT, InVec0, InVec1);
6462 SDValue Add = DAG.getNode(NextExpectedOpcode, DL, VT, InVec0, InVec1);
6464 // Construct the VSELECT mask.
6465 EVT MaskVT = VT.changeVectorElementTypeToInteger();
6466 EVT SVT = MaskVT.getVectorElementType();
6467 unsigned SVTBits = SVT.getSizeInBits();
6468 SmallVector<SDValue, 8> Ops;
6470 for (unsigned i = 0, e = NumElts; i != e; ++i) {
6471 APInt Value = i & 1 ? APInt::getNullValue(SVTBits) :
6472 APInt::getAllOnesValue(SVTBits);
6473 SDValue Constant = DAG.getConstant(Value, SVT);
6474 Ops.push_back(Constant);
6477 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, DL, MaskVT, Ops);
6478 return DAG.getSelect(DL, VT, Mask, Sub, Add);
6484 static SDValue PerformBUILD_VECTORCombine(SDNode *N, SelectionDAG &DAG,
6485 const X86Subtarget *Subtarget) {
6487 EVT VT = N->getValueType(0);
6488 unsigned NumElts = VT.getVectorNumElements();
6489 BuildVectorSDNode *BV = cast<BuildVectorSDNode>(N);
6490 SDValue InVec0, InVec1;
6492 // Try to match an ADDSUB.
6493 if ((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
6494 (Subtarget->hasAVX() && (VT == MVT::v8f32 || VT == MVT::v4f64))) {
6495 SDValue Value = matchAddSub(BV, DAG, Subtarget);
6496 if (Value.getNode())
6500 // Try to match horizontal ADD/SUB.
6501 unsigned NumUndefsLO = 0;
6502 unsigned NumUndefsHI = 0;
6503 unsigned Half = NumElts/2;
6505 // Count the number of UNDEF operands in the build_vector in input.
6506 for (unsigned i = 0, e = Half; i != e; ++i)
6507 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
6510 for (unsigned i = Half, e = NumElts; i != e; ++i)
6511 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
6514 // Early exit if this is either a build_vector of all UNDEFs or all the
6515 // operands but one are UNDEF.
6516 if (NumUndefsLO + NumUndefsHI + 1 >= NumElts)
6519 if ((VT == MVT::v4f32 || VT == MVT::v2f64) && Subtarget->hasSSE3()) {
6520 // Try to match an SSE3 float HADD/HSUB.
6521 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
6522 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
6524 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
6525 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
6526 } else if ((VT == MVT::v4i32 || VT == MVT::v8i16) && Subtarget->hasSSSE3()) {
6527 // Try to match an SSSE3 integer HADD/HSUB.
6528 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
6529 return DAG.getNode(X86ISD::HADD, DL, VT, InVec0, InVec1);
6531 if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
6532 return DAG.getNode(X86ISD::HSUB, DL, VT, InVec0, InVec1);
6535 if (!Subtarget->hasAVX())
6538 if ((VT == MVT::v8f32 || VT == MVT::v4f64)) {
6539 // Try to match an AVX horizontal add/sub of packed single/double
6540 // precision floating point values from 256-bit vectors.
6541 SDValue InVec2, InVec3;
6542 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, Half, InVec0, InVec1) &&
6543 isHorizontalBinOp(BV, ISD::FADD, DAG, Half, NumElts, InVec2, InVec3) &&
6544 ((InVec0.getOpcode() == ISD::UNDEF ||
6545 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6546 ((InVec1.getOpcode() == ISD::UNDEF ||
6547 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6548 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
6550 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, Half, InVec0, InVec1) &&
6551 isHorizontalBinOp(BV, ISD::FSUB, DAG, Half, NumElts, InVec2, InVec3) &&
6552 ((InVec0.getOpcode() == ISD::UNDEF ||
6553 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6554 ((InVec1.getOpcode() == ISD::UNDEF ||
6555 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6556 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
6557 } else if (VT == MVT::v8i32 || VT == MVT::v16i16) {
6558 // Try to match an AVX2 horizontal add/sub of signed integers.
6559 SDValue InVec2, InVec3;
6561 bool CanFold = true;
6563 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, Half, InVec0, InVec1) &&
6564 isHorizontalBinOp(BV, ISD::ADD, DAG, Half, NumElts, InVec2, InVec3) &&
6565 ((InVec0.getOpcode() == ISD::UNDEF ||
6566 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6567 ((InVec1.getOpcode() == ISD::UNDEF ||
6568 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6569 X86Opcode = X86ISD::HADD;
6570 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, Half, InVec0, InVec1) &&
6571 isHorizontalBinOp(BV, ISD::SUB, DAG, Half, NumElts, InVec2, InVec3) &&
6572 ((InVec0.getOpcode() == ISD::UNDEF ||
6573 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6574 ((InVec1.getOpcode() == ISD::UNDEF ||
6575 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6576 X86Opcode = X86ISD::HSUB;
6581 // Fold this build_vector into a single horizontal add/sub.
6582 // Do this only if the target has AVX2.
6583 if (Subtarget->hasAVX2())
6584 return DAG.getNode(X86Opcode, DL, VT, InVec0, InVec1);
6586 // Do not try to expand this build_vector into a pair of horizontal
6587 // add/sub if we can emit a pair of scalar add/sub.
6588 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
6591 // Convert this build_vector into a pair of horizontal binop followed by
6593 bool isUndefLO = NumUndefsLO == Half;
6594 bool isUndefHI = NumUndefsHI == Half;
6595 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, false,
6596 isUndefLO, isUndefHI);
6600 if ((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v8i32 ||
6601 VT == MVT::v16i16) && Subtarget->hasAVX()) {
6603 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
6604 X86Opcode = X86ISD::HADD;
6605 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
6606 X86Opcode = X86ISD::HSUB;
6607 else if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
6608 X86Opcode = X86ISD::FHADD;
6609 else if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
6610 X86Opcode = X86ISD::FHSUB;
6614 // Don't try to expand this build_vector into a pair of horizontal add/sub
6615 // if we can simply emit a pair of scalar add/sub.
6616 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
6619 // Convert this build_vector into two horizontal add/sub followed by
6621 bool isUndefLO = NumUndefsLO == Half;
6622 bool isUndefHI = NumUndefsHI == Half;
6623 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, true,
6624 isUndefLO, isUndefHI);
6631 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
6634 MVT VT = Op.getSimpleValueType();
6635 MVT ExtVT = VT.getVectorElementType();
6636 unsigned NumElems = Op.getNumOperands();
6638 // Generate vectors for predicate vectors.
6639 if (VT.getScalarType() == MVT::i1 && Subtarget->hasAVX512())
6640 return LowerBUILD_VECTORvXi1(Op, DAG);
6642 // Vectors containing all zeros can be matched by pxor and xorps later
6643 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
6644 // Canonicalize this to <4 x i32> to 1) ensure the zero vectors are CSE'd
6645 // and 2) ensure that i64 scalars are eliminated on x86-32 hosts.
6646 if (VT == MVT::v4i32 || VT == MVT::v8i32 || VT == MVT::v16i32)
6649 return getZeroVector(VT, Subtarget, DAG, dl);
6652 // Vectors containing all ones can be matched by pcmpeqd on 128-bit width
6653 // vectors or broken into v4i32 operations on 256-bit vectors. AVX2 can use
6654 // vpcmpeqd on 256-bit vectors.
6655 if (Subtarget->hasSSE2() && ISD::isBuildVectorAllOnes(Op.getNode())) {
6656 if (VT == MVT::v4i32 || (VT == MVT::v8i32 && Subtarget->hasInt256()))
6659 if (!VT.is512BitVector())
6660 return getOnesVector(VT, Subtarget->hasInt256(), DAG, dl);
6663 SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG);
6664 if (Broadcast.getNode())
6667 unsigned EVTBits = ExtVT.getSizeInBits();
6669 unsigned NumZero = 0;
6670 unsigned NumNonZero = 0;
6671 unsigned NonZeros = 0;
6672 bool IsAllConstants = true;
6673 SmallSet<SDValue, 8> Values;
6674 for (unsigned i = 0; i < NumElems; ++i) {
6675 SDValue Elt = Op.getOperand(i);
6676 if (Elt.getOpcode() == ISD::UNDEF)
6679 if (Elt.getOpcode() != ISD::Constant &&
6680 Elt.getOpcode() != ISD::ConstantFP)
6681 IsAllConstants = false;
6682 if (X86::isZeroNode(Elt))
6685 NonZeros |= (1 << i);
6690 // All undef vector. Return an UNDEF. All zero vectors were handled above.
6691 if (NumNonZero == 0)
6692 return DAG.getUNDEF(VT);
6694 // Special case for single non-zero, non-undef, element.
6695 if (NumNonZero == 1) {
6696 unsigned Idx = countTrailingZeros(NonZeros);
6697 SDValue Item = Op.getOperand(Idx);
6699 // If this is an insertion of an i64 value on x86-32, and if the top bits of
6700 // the value are obviously zero, truncate the value to i32 and do the
6701 // insertion that way. Only do this if the value is non-constant or if the
6702 // value is a constant being inserted into element 0. It is cheaper to do
6703 // a constant pool load than it is to do a movd + shuffle.
6704 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
6705 (!IsAllConstants || Idx == 0)) {
6706 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
6708 assert(VT == MVT::v2i64 && "Expected an SSE value type!");
6709 EVT VecVT = MVT::v4i32;
6710 unsigned VecElts = 4;
6712 // Truncate the value (which may itself be a constant) to i32, and
6713 // convert it to a vector with movd (S2V+shuffle to zero extend).
6714 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
6715 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
6716 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6718 // Now we have our 32-bit value zero extended in the low element of
6719 // a vector. If Idx != 0, swizzle it into place.
6721 SmallVector<int, 4> Mask;
6722 Mask.push_back(Idx);
6723 for (unsigned i = 1; i != VecElts; ++i)
6725 Item = DAG.getVectorShuffle(VecVT, dl, Item, DAG.getUNDEF(VecVT),
6728 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
6732 // If we have a constant or non-constant insertion into the low element of
6733 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
6734 // the rest of the elements. This will be matched as movd/movq/movss/movsd
6735 // depending on what the source datatype is.
6738 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6740 if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
6741 (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
6742 if (VT.is256BitVector() || VT.is512BitVector()) {
6743 SDValue ZeroVec = getZeroVector(VT, Subtarget, DAG, dl);
6744 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, ZeroVec,
6745 Item, DAG.getIntPtrConstant(0));
6747 assert(VT.is128BitVector() && "Expected an SSE value type!");
6748 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6749 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
6750 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6753 if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
6754 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
6755 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
6756 if (VT.is256BitVector()) {
6757 SDValue ZeroVec = getZeroVector(MVT::v8i32, Subtarget, DAG, dl);
6758 Item = Insert128BitVector(ZeroVec, Item, 0, DAG, dl);
6760 assert(VT.is128BitVector() && "Expected an SSE value type!");
6761 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6763 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
6767 // Is it a vector logical left shift?
6768 if (NumElems == 2 && Idx == 1 &&
6769 X86::isZeroNode(Op.getOperand(0)) &&
6770 !X86::isZeroNode(Op.getOperand(1))) {
6771 unsigned NumBits = VT.getSizeInBits();
6772 return getVShift(true, VT,
6773 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
6774 VT, Op.getOperand(1)),
6775 NumBits/2, DAG, *this, dl);
6778 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
6781 // Otherwise, if this is a vector with i32 or f32 elements, and the element
6782 // is a non-constant being inserted into an element other than the low one,
6783 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
6784 // movd/movss) to move this into the low element, then shuffle it into
6786 if (EVTBits == 32) {
6787 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6789 // Turn it into a shuffle of zero and zero-extended scalar to vector.
6790 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0, Subtarget, DAG);
6791 SmallVector<int, 8> MaskVec;
6792 for (unsigned i = 0; i != NumElems; ++i)
6793 MaskVec.push_back(i == Idx ? 0 : 1);
6794 return DAG.getVectorShuffle(VT, dl, Item, DAG.getUNDEF(VT), &MaskVec[0]);
6798 // Splat is obviously ok. Let legalizer expand it to a shuffle.
6799 if (Values.size() == 1) {
6800 if (EVTBits == 32) {
6801 // Instead of a shuffle like this:
6802 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
6803 // Check if it's possible to issue this instead.
6804 // shuffle (vload ptr)), undef, <1, 1, 1, 1>
6805 unsigned Idx = countTrailingZeros(NonZeros);
6806 SDValue Item = Op.getOperand(Idx);
6807 if (Op.getNode()->isOnlyUserOf(Item.getNode()))
6808 return LowerAsSplatVectorLoad(Item, VT, dl, DAG);
6813 // A vector full of immediates; various special cases are already
6814 // handled, so this is best done with a single constant-pool load.
6818 // For AVX-length vectors, build the individual 128-bit pieces and use
6819 // shuffles to put them in place.
6820 if (VT.is256BitVector() || VT.is512BitVector()) {
6821 SmallVector<SDValue, 64> V;
6822 for (unsigned i = 0; i != NumElems; ++i)
6823 V.push_back(Op.getOperand(i));
6825 EVT HVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems/2);
6827 // Build both the lower and upper subvector.
6828 SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
6829 makeArrayRef(&V[0], NumElems/2));
6830 SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
6831 makeArrayRef(&V[NumElems / 2], NumElems/2));
6833 // Recreate the wider vector with the lower and upper part.
6834 if (VT.is256BitVector())
6835 return Concat128BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
6836 return Concat256BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
6839 // Let legalizer expand 2-wide build_vectors.
6840 if (EVTBits == 64) {
6841 if (NumNonZero == 1) {
6842 // One half is zero or undef.
6843 unsigned Idx = countTrailingZeros(NonZeros);
6844 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
6845 Op.getOperand(Idx));
6846 return getShuffleVectorZeroOrUndef(V2, Idx, true, Subtarget, DAG);
6851 // If element VT is < 32 bits, convert it to inserts into a zero vector.
6852 if (EVTBits == 8 && NumElems == 16) {
6853 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
6855 if (V.getNode()) return V;
6858 if (EVTBits == 16 && NumElems == 8) {
6859 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
6861 if (V.getNode()) return V;
6864 // If element VT is == 32 bits and has 4 elems, try to generate an INSERTPS
6865 if (EVTBits == 32 && NumElems == 4) {
6866 SDValue V = LowerBuildVectorv4x32(Op, NumElems, NonZeros, NumNonZero,
6867 NumZero, DAG, Subtarget, *this);
6872 // If element VT is == 32 bits, turn it into a number of shuffles.
6873 SmallVector<SDValue, 8> V(NumElems);
6874 if (NumElems == 4 && NumZero > 0) {
6875 for (unsigned i = 0; i < 4; ++i) {
6876 bool isZero = !(NonZeros & (1 << i));
6878 V[i] = getZeroVector(VT, Subtarget, DAG, dl);
6880 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
6883 for (unsigned i = 0; i < 2; ++i) {
6884 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
6887 V[i] = V[i*2]; // Must be a zero vector.
6890 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
6893 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
6896 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
6901 bool Reverse1 = (NonZeros & 0x3) == 2;
6902 bool Reverse2 = ((NonZeros & (0x3 << 2)) >> 2) == 2;
6906 static_cast<int>(Reverse2 ? NumElems+1 : NumElems),
6907 static_cast<int>(Reverse2 ? NumElems : NumElems+1)
6909 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
6912 if (Values.size() > 1 && VT.is128BitVector()) {
6913 // Check for a build vector of consecutive loads.
6914 for (unsigned i = 0; i < NumElems; ++i)
6915 V[i] = Op.getOperand(i);
6917 // Check for elements which are consecutive loads.
6918 SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG, false);
6922 // Check for a build vector from mostly shuffle plus few inserting.
6923 SDValue Sh = buildFromShuffleMostly(Op, DAG);
6927 // For SSE 4.1, use insertps to put the high elements into the low element.
6928 if (getSubtarget()->hasSSE41()) {
6930 if (Op.getOperand(0).getOpcode() != ISD::UNDEF)
6931 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0));
6933 Result = DAG.getUNDEF(VT);
6935 for (unsigned i = 1; i < NumElems; ++i) {
6936 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue;
6937 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result,
6938 Op.getOperand(i), DAG.getIntPtrConstant(i));
6943 // Otherwise, expand into a number of unpckl*, start by extending each of
6944 // our (non-undef) elements to the full vector width with the element in the
6945 // bottom slot of the vector (which generates no code for SSE).
6946 for (unsigned i = 0; i < NumElems; ++i) {
6947 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
6948 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
6950 V[i] = DAG.getUNDEF(VT);
6953 // Next, we iteratively mix elements, e.g. for v4f32:
6954 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
6955 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
6956 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
6957 unsigned EltStride = NumElems >> 1;
6958 while (EltStride != 0) {
6959 for (unsigned i = 0; i < EltStride; ++i) {
6960 // If V[i+EltStride] is undef and this is the first round of mixing,
6961 // then it is safe to just drop this shuffle: V[i] is already in the
6962 // right place, the one element (since it's the first round) being
6963 // inserted as undef can be dropped. This isn't safe for successive
6964 // rounds because they will permute elements within both vectors.
6965 if (V[i+EltStride].getOpcode() == ISD::UNDEF &&
6966 EltStride == NumElems/2)
6969 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]);
6978 // LowerAVXCONCAT_VECTORS - 256-bit AVX can use the vinsertf128 instruction
6979 // to create 256-bit vectors from two other 128-bit ones.
6980 static SDValue LowerAVXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
6982 MVT ResVT = Op.getSimpleValueType();
6984 assert((ResVT.is256BitVector() ||
6985 ResVT.is512BitVector()) && "Value type must be 256-/512-bit wide");
6987 SDValue V1 = Op.getOperand(0);
6988 SDValue V2 = Op.getOperand(1);
6989 unsigned NumElems = ResVT.getVectorNumElements();
6990 if(ResVT.is256BitVector())
6991 return Concat128BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
6993 if (Op.getNumOperands() == 4) {
6994 MVT HalfVT = MVT::getVectorVT(ResVT.getScalarType(),
6995 ResVT.getVectorNumElements()/2);
6996 SDValue V3 = Op.getOperand(2);
6997 SDValue V4 = Op.getOperand(3);
6998 return Concat256BitVectors(Concat128BitVectors(V1, V2, HalfVT, NumElems/2, DAG, dl),
6999 Concat128BitVectors(V3, V4, HalfVT, NumElems/2, DAG, dl), ResVT, NumElems, DAG, dl);
7001 return Concat256BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
7004 static SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
7005 MVT LLVM_ATTRIBUTE_UNUSED VT = Op.getSimpleValueType();
7006 assert((VT.is256BitVector() && Op.getNumOperands() == 2) ||
7007 (VT.is512BitVector() && (Op.getNumOperands() == 2 ||
7008 Op.getNumOperands() == 4)));
7010 // AVX can use the vinsertf128 instruction to create 256-bit vectors
7011 // from two other 128-bit ones.
7013 // 512-bit vector may contain 2 256-bit vectors or 4 128-bit vectors
7014 return LowerAVXCONCAT_VECTORS(Op, DAG);
7018 //===----------------------------------------------------------------------===//
7019 // Vector shuffle lowering
7021 // This is an experimental code path for lowering vector shuffles on x86. It is
7022 // designed to handle arbitrary vector shuffles and blends, gracefully
7023 // degrading performance as necessary. It works hard to recognize idiomatic
7024 // shuffles and lower them to optimal instruction patterns without leaving
7025 // a framework that allows reasonably efficient handling of all vector shuffle
7027 //===----------------------------------------------------------------------===//
7029 /// \brief Tiny helper function to identify a no-op mask.
7031 /// This is a somewhat boring predicate function. It checks whether the mask
7032 /// array input, which is assumed to be a single-input shuffle mask of the kind
7033 /// used by the X86 shuffle instructions (not a fully general
7034 /// ShuffleVectorSDNode mask) requires any shuffles to occur. Both undef and an
7035 /// in-place shuffle are 'no-op's.
7036 static bool isNoopShuffleMask(ArrayRef<int> Mask) {
7037 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7038 if (Mask[i] != -1 && Mask[i] != i)
7043 /// \brief Helper function to classify a mask as a single-input mask.
7045 /// This isn't a generic single-input test because in the vector shuffle
7046 /// lowering we canonicalize single inputs to be the first input operand. This
7047 /// means we can more quickly test for a single input by only checking whether
7048 /// an input from the second operand exists. We also assume that the size of
7049 /// mask corresponds to the size of the input vectors which isn't true in the
7050 /// fully general case.
7051 static bool isSingleInputShuffleMask(ArrayRef<int> Mask) {
7053 if (M >= (int)Mask.size())
7058 // Hide this symbol with an anonymous namespace instead of 'static' so that MSVC
7059 // 2013 will allow us to use it as a non-type template parameter.
7062 /// \brief Implementation of the \c isShuffleEquivalent variadic functor.
7064 /// See its documentation for details.
7065 bool isShuffleEquivalentImpl(ArrayRef<int> Mask, ArrayRef<const int *> Args) {
7066 if (Mask.size() != Args.size())
7068 for (int i = 0, e = Mask.size(); i < e; ++i) {
7069 assert(*Args[i] >= 0 && "Arguments must be positive integers!");
7070 assert(*Args[i] < (int)Args.size() * 2 &&
7071 "Argument outside the range of possible shuffle inputs!");
7072 if (Mask[i] != -1 && Mask[i] != *Args[i])
7080 /// \brief Checks whether a shuffle mask is equivalent to an explicit list of
7083 /// This is a fast way to test a shuffle mask against a fixed pattern:
7085 /// if (isShuffleEquivalent(Mask, 3, 2, 1, 0)) { ... }
7087 /// It returns true if the mask is exactly as wide as the argument list, and
7088 /// each element of the mask is either -1 (signifying undef) or the value given
7089 /// in the argument.
7090 static const VariadicFunction1<
7091 bool, ArrayRef<int>, int, isShuffleEquivalentImpl> isShuffleEquivalent = {};
7093 /// \brief Get a 4-lane 8-bit shuffle immediate for a mask.
7095 /// This helper function produces an 8-bit shuffle immediate corresponding to
7096 /// the ubiquitous shuffle encoding scheme used in x86 instructions for
7097 /// shuffling 4 lanes. It can be used with most of the PSHUF instructions for
7100 /// NB: We rely heavily on "undef" masks preserving the input lane.
7101 static SDValue getV4X86ShuffleImm8ForMask(ArrayRef<int> Mask,
7102 SelectionDAG &DAG) {
7103 assert(Mask.size() == 4 && "Only 4-lane shuffle masks");
7104 assert(Mask[0] >= -1 && Mask[0] < 4 && "Out of bound mask element!");
7105 assert(Mask[1] >= -1 && Mask[1] < 4 && "Out of bound mask element!");
7106 assert(Mask[2] >= -1 && Mask[2] < 4 && "Out of bound mask element!");
7107 assert(Mask[3] >= -1 && Mask[3] < 4 && "Out of bound mask element!");
7110 Imm |= (Mask[0] == -1 ? 0 : Mask[0]) << 0;
7111 Imm |= (Mask[1] == -1 ? 1 : Mask[1]) << 2;
7112 Imm |= (Mask[2] == -1 ? 2 : Mask[2]) << 4;
7113 Imm |= (Mask[3] == -1 ? 3 : Mask[3]) << 6;
7114 return DAG.getConstant(Imm, MVT::i8);
7117 /// \brief Handle lowering of 2-lane 64-bit floating point shuffles.
7119 /// This is the basis function for the 2-lane 64-bit shuffles as we have full
7120 /// support for floating point shuffles but not integer shuffles. These
7121 /// instructions will incur a domain crossing penalty on some chips though so
7122 /// it is better to avoid lowering through this for integer vectors where
7124 static SDValue lowerV2F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
7125 const X86Subtarget *Subtarget,
7126 SelectionDAG &DAG) {
7128 assert(Op.getSimpleValueType() == MVT::v2f64 && "Bad shuffle type!");
7129 assert(V1.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
7130 assert(V2.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
7131 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7132 ArrayRef<int> Mask = SVOp->getMask();
7133 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
7135 if (isSingleInputShuffleMask(Mask)) {
7136 // Straight shuffle of a single input vector. Simulate this by using the
7137 // single input as both of the "inputs" to this instruction..
7138 unsigned SHUFPDMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1);
7139 return DAG.getNode(X86ISD::SHUFP, SDLoc(Op), MVT::v2f64, V1, V1,
7140 DAG.getConstant(SHUFPDMask, MVT::i8));
7142 assert(Mask[0] >= 0 && Mask[0] < 2 && "Non-canonicalized blend!");
7143 assert(Mask[1] >= 2 && "Non-canonicalized blend!");
7145 unsigned SHUFPDMask = (Mask[0] == 1) | (((Mask[1] - 2) == 1) << 1);
7146 return DAG.getNode(X86ISD::SHUFP, SDLoc(Op), MVT::v2f64, V1, V2,
7147 DAG.getConstant(SHUFPDMask, MVT::i8));
7150 /// \brief Handle lowering of 2-lane 64-bit integer shuffles.
7152 /// Tries to lower a 2-lane 64-bit shuffle using shuffle operations provided by
7153 /// the integer unit to minimize domain crossing penalties. However, for blends
7154 /// it falls back to the floating point shuffle operation with appropriate bit
7156 static SDValue lowerV2I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
7157 const X86Subtarget *Subtarget,
7158 SelectionDAG &DAG) {
7160 assert(Op.getSimpleValueType() == MVT::v2i64 && "Bad shuffle type!");
7161 assert(V1.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
7162 assert(V2.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
7163 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7164 ArrayRef<int> Mask = SVOp->getMask();
7165 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
7167 if (isSingleInputShuffleMask(Mask)) {
7168 // Straight shuffle of a single input vector. For everything from SSE2
7169 // onward this has a single fast instruction with no scary immediates.
7170 // We have to map the mask as it is actually a v4i32 shuffle instruction.
7171 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V1);
7172 int WidenedMask[4] = {
7173 std::max(Mask[0], 0) * 2, std::max(Mask[0], 0) * 2 + 1,
7174 std::max(Mask[1], 0) * 2, std::max(Mask[1], 0) * 2 + 1};
7176 ISD::BITCAST, DL, MVT::v2i64,
7177 DAG.getNode(X86ISD::PSHUFD, SDLoc(Op), MVT::v4i32, V1,
7178 getV4X86ShuffleImm8ForMask(WidenedMask, DAG)));
7181 // We implement this with SHUFPD which is pretty lame because it will likely
7182 // incur 2 cycles of stall for integer vectors on Nehalem and older chips.
7183 // However, all the alternatives are still more cycles and newer chips don't
7184 // have this problem. It would be really nice if x86 had better shuffles here.
7185 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v2f64, V1);
7186 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v2f64, V2);
7187 return DAG.getNode(ISD::BITCAST, DL, MVT::v2i64,
7188 DAG.getVectorShuffle(MVT::v2f64, DL, V1, V2, Mask));
7191 /// \brief Lower 4-lane 32-bit floating point shuffles.
7193 /// Uses instructions exclusively from the floating point unit to minimize
7194 /// domain crossing penalties, as these are sufficient to implement all v4f32
7196 static SDValue lowerV4F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
7197 const X86Subtarget *Subtarget,
7198 SelectionDAG &DAG) {
7200 assert(Op.getSimpleValueType() == MVT::v4f32 && "Bad shuffle type!");
7201 assert(V1.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
7202 assert(V2.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
7203 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7204 ArrayRef<int> Mask = SVOp->getMask();
7205 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
7207 SDValue LowV = V1, HighV = V2;
7208 int NewMask[4] = {Mask[0], Mask[1], Mask[2], Mask[3]};
7211 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
7213 if (NumV2Elements == 0)
7214 // Straight shuffle of a single input vector. We pass the input vector to
7215 // both operands to simulate this with a SHUFPS.
7216 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f32, V1, V1,
7217 getV4X86ShuffleImm8ForMask(Mask, DAG));
7219 if (NumV2Elements == 1) {
7221 std::find_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; }) -
7223 // Compute the index adjacent to V2Index and in the same half by toggling
7225 int V2AdjIndex = V2Index ^ 1;
7227 if (Mask[V2AdjIndex] == -1) {
7228 // Handles all the cases where we have a single V2 element and an undef.
7229 // This will only ever happen in the high lanes because we commute the
7230 // vector otherwise.
7232 std::swap(LowV, HighV);
7233 NewMask[V2Index] -= 4;
7235 // Handle the case where the V2 element ends up adjacent to a V1 element.
7236 // To make this work, blend them together as the first step.
7237 int V1Index = V2AdjIndex;
7238 int BlendMask[4] = {Mask[V2Index] - 4, 0, Mask[V1Index], 0};
7239 V2 = DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f32, V2, V1,
7240 getV4X86ShuffleImm8ForMask(BlendMask, DAG));
7242 // Now proceed to reconstruct the final blend as we have the necessary
7243 // high or low half formed.
7250 NewMask[V1Index] = 2; // We put the V1 element in V2[2].
7251 NewMask[V2Index] = 0; // We shifted the V2 element into V2[0].
7253 } else if (NumV2Elements == 2) {
7254 if (Mask[0] < 4 && Mask[1] < 4) {
7255 // Handle the easy case where we have V1 in the low lanes and V2 in the
7256 // high lanes. We never see this reversed because we sort the shuffle.
7260 // We have a mixture of V1 and V2 in both low and high lanes. Rather than
7261 // trying to place elements directly, just blend them and set up the final
7262 // shuffle to place them.
7264 // The first two blend mask elements are for V1, the second two are for
7266 int BlendMask[4] = {Mask[0] < 4 ? Mask[0] : Mask[1],
7267 Mask[2] < 4 ? Mask[2] : Mask[3],
7268 (Mask[0] >= 4 ? Mask[0] : Mask[1]) - 4,
7269 (Mask[2] >= 4 ? Mask[2] : Mask[3]) - 4};
7270 V1 = DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f32, V1, V2,
7271 getV4X86ShuffleImm8ForMask(BlendMask, DAG));
7273 // Now we do a normal shuffle of V1 by giving V1 as both operands to
7276 NewMask[0] = Mask[0] < 4 ? 0 : 2;
7277 NewMask[1] = Mask[0] < 4 ? 2 : 0;
7278 NewMask[2] = Mask[2] < 4 ? 1 : 3;
7279 NewMask[3] = Mask[2] < 4 ? 3 : 1;
7282 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f32, LowV, HighV,
7283 getV4X86ShuffleImm8ForMask(NewMask, DAG));
7286 /// \brief Lower 4-lane i32 vector shuffles.
7288 /// We try to handle these with integer-domain shuffles where we can, but for
7289 /// blends we use the floating point domain blend instructions.
7290 static SDValue lowerV4I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
7291 const X86Subtarget *Subtarget,
7292 SelectionDAG &DAG) {
7294 assert(Op.getSimpleValueType() == MVT::v4i32 && "Bad shuffle type!");
7295 assert(V1.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
7296 assert(V2.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
7297 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7298 ArrayRef<int> Mask = SVOp->getMask();
7299 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
7301 if (isSingleInputShuffleMask(Mask))
7302 // Straight shuffle of a single input vector. For everything from SSE2
7303 // onward this has a single fast instruction with no scary immediates.
7304 return DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V1,
7305 getV4X86ShuffleImm8ForMask(Mask, DAG));
7307 // We implement this with SHUFPS because it can blend from two vectors.
7308 // Because we're going to eventually use SHUFPS, we use SHUFPS even to build
7309 // up the inputs, bypassing domain shift penalties that we would encur if we
7310 // directly used PSHUFD on Nehalem and older. For newer chips, this isn't
7312 return DAG.getNode(ISD::BITCAST, DL, MVT::v4i32,
7313 DAG.getVectorShuffle(
7315 DAG.getNode(ISD::BITCAST, DL, MVT::v4f32, V1),
7316 DAG.getNode(ISD::BITCAST, DL, MVT::v4f32, V2), Mask));
7319 /// \brief Lowering of single-input v8i16 shuffles is the cornerstone of SSE2
7320 /// shuffle lowering, and the most complex part.
7322 /// The lowering strategy is to try to form pairs of input lanes which are
7323 /// targeted at the same half of the final vector, and then use a dword shuffle
7324 /// to place them onto the right half, and finally unpack the paired lanes into
7325 /// their final position.
7327 /// The exact breakdown of how to form these dword pairs and align them on the
7328 /// correct sides is really tricky. See the comments within the function for
7329 /// more of the details.
7330 static SDValue lowerV8I16SingleInputVectorShuffle(
7331 SDLoc DL, SDValue V, MutableArrayRef<int> Mask,
7332 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7333 assert(V.getSimpleValueType() == MVT::v8i16 && "Bad input type!");
7334 MutableArrayRef<int> LoMask = Mask.slice(0, 4);
7335 MutableArrayRef<int> HiMask = Mask.slice(4, 4);
7337 SmallVector<int, 4> LoInputs;
7338 std::copy_if(LoMask.begin(), LoMask.end(), std::back_inserter(LoInputs),
7339 [](int M) { return M >= 0; });
7340 std::sort(LoInputs.begin(), LoInputs.end());
7341 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()), LoInputs.end());
7342 SmallVector<int, 4> HiInputs;
7343 std::copy_if(HiMask.begin(), HiMask.end(), std::back_inserter(HiInputs),
7344 [](int M) { return M >= 0; });
7345 std::sort(HiInputs.begin(), HiInputs.end());
7346 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()), HiInputs.end());
7348 std::lower_bound(LoInputs.begin(), LoInputs.end(), 4) - LoInputs.begin();
7349 int NumHToL = LoInputs.size() - NumLToL;
7351 std::lower_bound(HiInputs.begin(), HiInputs.end(), 4) - HiInputs.begin();
7352 int NumHToH = HiInputs.size() - NumLToH;
7353 MutableArrayRef<int> LToLInputs(LoInputs.data(), NumLToL);
7354 MutableArrayRef<int> LToHInputs(HiInputs.data(), NumLToH);
7355 MutableArrayRef<int> HToLInputs(LoInputs.data() + NumLToL, NumHToL);
7356 MutableArrayRef<int> HToHInputs(HiInputs.data() + NumLToH, NumHToH);
7358 // Simplify the 1-into-3 and 3-into-1 cases with a single pshufd. For all
7359 // such inputs we can swap two of the dwords across the half mark and end up
7360 // with <=2 inputs to each half in each half. Once there, we can fall through
7361 // to the generic code below. For example:
7363 // Input: [a, b, c, d, e, f, g, h] -PSHUFD[0,2,1,3]-> [a, b, e, f, c, d, g, h]
7364 // Mask: [0, 1, 2, 7, 4, 5, 6, 3] -----------------> [0, 1, 4, 7, 2, 3, 6, 5]
7366 // However in some very rare cases we have a 1-into-3 or 3-into-1 on one half
7367 // and an existing 2-into-2 on the other half. In this case we may have to
7368 // pre-shuffle the 2-into-2 half to avoid turning it into a 3-into-1 or
7369 // 1-into-3 which could cause us to cycle endlessly fixing each side in turn.
7370 // Fortunately, we don't have to handle anything but a 2-into-2 pattern
7371 // because any other situation (including a 3-into-1 or 1-into-3 in the other
7372 // half than the one we target for fixing) will be fixed when we re-enter this
7373 // path. We will also combine away any sequence of PSHUFD instructions that
7374 // result into a single instruction. Here is an example of the tricky case:
7376 // Input: [a, b, c, d, e, f, g, h] -PSHUFD[0,2,1,3]-> [a, b, e, f, c, d, g, h]
7377 // Mask: [3, 7, 1, 0, 2, 7, 3, 5] -THIS-IS-BAD!!!!-> [5, 7, 1, 0, 4, 7, 5, 3]
7379 // This now has a 1-into-3 in the high half! Instead, we do two shuffles:
7381 // Input: [a, b, c, d, e, f, g, h] PSHUFHW[0,2,1,3]-> [a, b, c, d, e, g, f, h]
7382 // Mask: [3, 7, 1, 0, 2, 7, 3, 5] -----------------> [3, 7, 1, 0, 2, 7, 3, 6]
7384 // Input: [a, b, c, d, e, g, f, h] -PSHUFD[0,2,1,3]-> [a, b, e, g, c, d, f, h]
7385 // Mask: [3, 7, 1, 0, 2, 7, 3, 6] -----------------> [5, 7, 1, 0, 4, 7, 5, 6]
7387 // The result is fine to be handled by the generic logic.
7388 auto balanceSides = [&](ArrayRef<int> AToAInputs, ArrayRef<int> BToAInputs,
7389 ArrayRef<int> BToBInputs, ArrayRef<int> AToBInputs,
7390 int AOffset, int BOffset) {
7391 assert((AToAInputs.size() == 3 || AToAInputs.size() == 1) &&
7392 "Must call this with A having 3 or 1 inputs from the A half.");
7393 assert((BToAInputs.size() == 1 || BToAInputs.size() == 3) &&
7394 "Must call this with B having 1 or 3 inputs from the B half.");
7395 assert(AToAInputs.size() + BToAInputs.size() == 4 &&
7396 "Must call this with either 3:1 or 1:3 inputs (summing to 4).");
7398 // Compute the index of dword with only one word among the three inputs in
7399 // a half by taking the sum of the half with three inputs and subtracting
7400 // the sum of the actual three inputs. The difference is the remaining
7403 int &TripleDWord = AToAInputs.size() == 3 ? ADWord : BDWord;
7404 int &OneInputDWord = AToAInputs.size() == 3 ? BDWord : ADWord;
7405 int TripleInputOffset = AToAInputs.size() == 3 ? AOffset : BOffset;
7406 ArrayRef<int> TripleInputs = AToAInputs.size() == 3 ? AToAInputs : BToAInputs;
7407 int OneInput = AToAInputs.size() == 3 ? BToAInputs[0] : AToAInputs[0];
7408 int TripleInputSum = 0 + 1 + 2 + 3 + (4 * TripleInputOffset);
7409 int TripleNonInputIdx =
7410 TripleInputSum - std::accumulate(TripleInputs.begin(), TripleInputs.end(), 0);
7411 TripleDWord = TripleNonInputIdx / 2;
7413 // We use xor with one to compute the adjacent DWord to whichever one the
7415 OneInputDWord = (OneInput / 2) ^ 1;
7417 // Check for one tricky case: We're fixing a 3<-1 or a 1<-3 shuffle for AToA
7418 // and BToA inputs. If there is also such a problem with the BToB and AToB
7419 // inputs, we don't try to fix it necessarily -- we'll recurse and see it in
7420 // the next pass. However, if we have a 2<-2 in the BToB and AToB inputs, it
7421 // is essential that we don't *create* a 3<-1 as then we might oscillate.
7422 if (BToBInputs.size() == 2 && AToBInputs.size() == 2) {
7423 // Compute how many inputs will be flipped by swapping these DWords. We
7425 // to balance this to ensure we don't form a 3-1 shuffle in the other
7427 int NumFlippedAToBInputs =
7428 std::count(AToBInputs.begin(), AToBInputs.end(), 2 * ADWord) +
7429 std::count(AToBInputs.begin(), AToBInputs.end(), 2 * ADWord + 1);
7430 int NumFlippedBToBInputs =
7431 std::count(BToBInputs.begin(), BToBInputs.end(), 2 * BDWord) +
7432 std::count(BToBInputs.begin(), BToBInputs.end(), 2 * BDWord + 1);
7433 if ((NumFlippedAToBInputs == 1 &&
7434 (NumFlippedBToBInputs == 0 || NumFlippedBToBInputs == 2)) ||
7435 (NumFlippedBToBInputs == 1 &&
7436 (NumFlippedAToBInputs == 0 || NumFlippedAToBInputs == 2))) {
7437 // We choose whether to fix the A half or B half based on whether that
7438 // half has zero flipped inputs. At zero, we may not be able to fix it
7439 // with that half. We also bias towards fixing the B half because that
7440 // will more commonly be the high half, and we have to bias one way.
7441 auto FixFlippedInputs = [&V, &DL, &Mask, &DAG](int PinnedIdx, int DWord,
7442 ArrayRef<int> Inputs) {
7443 int FixIdx = PinnedIdx ^ 1; // The adjacent slot to the pinned slot.
7444 bool IsFixIdxInput = std::find(Inputs.begin(), Inputs.end(),
7445 PinnedIdx ^ 1) != Inputs.end();
7446 // Determine whether the free index is in the flipped dword or the
7447 // unflipped dword based on where the pinned index is. We use this bit
7448 // in an xor to conditionally select the adjacent dword.
7449 int FixFreeIdx = 2 * (DWord ^ (PinnedIdx / 2 == DWord));
7450 bool IsFixFreeIdxInput = std::find(Inputs.begin(), Inputs.end(),
7451 FixFreeIdx) != Inputs.end();
7452 if (IsFixIdxInput == IsFixFreeIdxInput)
7454 IsFixFreeIdxInput = std::find(Inputs.begin(), Inputs.end(),
7455 FixFreeIdx) != Inputs.end();
7456 assert(IsFixIdxInput != IsFixFreeIdxInput &&
7457 "We need to be changing the number of flipped inputs!");
7458 int PSHUFHalfMask[] = {0, 1, 2, 3};
7459 std::swap(PSHUFHalfMask[FixFreeIdx % 4], PSHUFHalfMask[FixIdx % 4]);
7460 V = DAG.getNode(FixIdx < 4 ? X86ISD::PSHUFLW : X86ISD::PSHUFHW, DL,
7462 getV4X86ShuffleImm8ForMask(PSHUFHalfMask, DAG));
7465 if (M != -1 && M == FixIdx)
7467 else if (M != -1 && M == FixFreeIdx)
7470 if (NumFlippedBToBInputs != 0) {
7472 BToAInputs.size() == 3 ? TripleNonInputIdx : OneInput;
7473 FixFlippedInputs(BPinnedIdx, BDWord, BToBInputs);
7475 assert(NumFlippedAToBInputs != 0 && "Impossible given predicates!");
7477 AToAInputs.size() == 3 ? TripleNonInputIdx : OneInput;
7478 FixFlippedInputs(APinnedIdx, ADWord, AToBInputs);
7483 int PSHUFDMask[] = {0, 1, 2, 3};
7484 PSHUFDMask[ADWord] = BDWord;
7485 PSHUFDMask[BDWord] = ADWord;
7486 V = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
7487 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
7488 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V),
7489 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
7491 // Adjust the mask to match the new locations of A and B.
7493 if (M != -1 && M/2 == ADWord)
7494 M = 2 * BDWord + M % 2;
7495 else if (M != -1 && M/2 == BDWord)
7496 M = 2 * ADWord + M % 2;
7498 // Recurse back into this routine to re-compute state now that this isn't
7499 // a 3 and 1 problem.
7500 return DAG.getVectorShuffle(MVT::v8i16, DL, V, DAG.getUNDEF(MVT::v8i16),
7503 if ((NumLToL == 3 && NumHToL == 1) || (NumLToL == 1 && NumHToL == 3))
7504 return balanceSides(LToLInputs, HToLInputs, HToHInputs, LToHInputs, 0, 4);
7505 else if ((NumHToH == 3 && NumLToH == 1) || (NumHToH == 1 && NumLToH == 3))
7506 return balanceSides(HToHInputs, LToHInputs, LToLInputs, HToLInputs, 4, 0);
7508 // At this point there are at most two inputs to the low and high halves from
7509 // each half. That means the inputs can always be grouped into dwords and
7510 // those dwords can then be moved to the correct half with a dword shuffle.
7511 // We use at most one low and one high word shuffle to collect these paired
7512 // inputs into dwords, and finally a dword shuffle to place them.
7513 int PSHUFLMask[4] = {-1, -1, -1, -1};
7514 int PSHUFHMask[4] = {-1, -1, -1, -1};
7515 int PSHUFDMask[4] = {-1, -1, -1, -1};
7517 // First fix the masks for all the inputs that are staying in their
7518 // original halves. This will then dictate the targets of the cross-half
7520 auto fixInPlaceInputs =
7521 [&PSHUFDMask](ArrayRef<int> InPlaceInputs, ArrayRef<int> IncomingInputs,
7522 MutableArrayRef<int> SourceHalfMask,
7523 MutableArrayRef<int> HalfMask, int HalfOffset) {
7524 if (InPlaceInputs.empty())
7526 if (InPlaceInputs.size() == 1) {
7527 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
7528 InPlaceInputs[0] - HalfOffset;
7529 PSHUFDMask[InPlaceInputs[0] / 2] = InPlaceInputs[0] / 2;
7532 if (IncomingInputs.empty()) {
7533 // Just fix all of the in place inputs.
7534 for (int Input : InPlaceInputs) {
7535 SourceHalfMask[Input - HalfOffset] = Input - HalfOffset;
7536 PSHUFDMask[Input / 2] = Input / 2;
7541 assert(InPlaceInputs.size() == 2 && "Cannot handle 3 or 4 inputs!");
7542 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
7543 InPlaceInputs[0] - HalfOffset;
7544 // Put the second input next to the first so that they are packed into
7545 // a dword. We find the adjacent index by toggling the low bit.
7546 int AdjIndex = InPlaceInputs[0] ^ 1;
7547 SourceHalfMask[AdjIndex - HalfOffset] = InPlaceInputs[1] - HalfOffset;
7548 std::replace(HalfMask.begin(), HalfMask.end(), InPlaceInputs[1], AdjIndex);
7549 PSHUFDMask[AdjIndex / 2] = AdjIndex / 2;
7551 fixInPlaceInputs(LToLInputs, HToLInputs, PSHUFLMask, LoMask, 0);
7552 fixInPlaceInputs(HToHInputs, LToHInputs, PSHUFHMask, HiMask, 4);
7554 // Now gather the cross-half inputs and place them into a free dword of
7555 // their target half.
7556 // FIXME: This operation could almost certainly be simplified dramatically to
7557 // look more like the 3-1 fixing operation.
7558 auto moveInputsToRightHalf = [&PSHUFDMask](
7559 MutableArrayRef<int> IncomingInputs, ArrayRef<int> ExistingInputs,
7560 MutableArrayRef<int> SourceHalfMask, MutableArrayRef<int> HalfMask,
7561 MutableArrayRef<int> FinalSourceHalfMask, int SourceOffset,
7563 auto isWordClobbered = [](ArrayRef<int> SourceHalfMask, int Word) {
7564 return SourceHalfMask[Word] != -1 && SourceHalfMask[Word] != Word;
7566 auto isDWordClobbered = [&isWordClobbered](ArrayRef<int> SourceHalfMask,
7568 int LowWord = Word & ~1;
7569 int HighWord = Word | 1;
7570 return isWordClobbered(SourceHalfMask, LowWord) ||
7571 isWordClobbered(SourceHalfMask, HighWord);
7574 if (IncomingInputs.empty())
7577 if (ExistingInputs.empty()) {
7578 // Map any dwords with inputs from them into the right half.
7579 for (int Input : IncomingInputs) {
7580 // If the source half mask maps over the inputs, turn those into
7581 // swaps and use the swapped lane.
7582 if (isWordClobbered(SourceHalfMask, Input - SourceOffset)) {
7583 if (SourceHalfMask[SourceHalfMask[Input - SourceOffset]] == -1) {
7584 SourceHalfMask[SourceHalfMask[Input - SourceOffset]] =
7585 Input - SourceOffset;
7586 // We have to swap the uses in our half mask in one sweep.
7587 for (int &M : HalfMask)
7588 if (M == SourceHalfMask[Input - SourceOffset] + SourceOffset)
7590 else if (M == Input)
7591 M = SourceHalfMask[Input - SourceOffset] + SourceOffset;
7593 assert(SourceHalfMask[SourceHalfMask[Input - SourceOffset]] ==
7594 Input - SourceOffset &&
7595 "Previous placement doesn't match!");
7597 // Note that this correctly re-maps both when we do a swap and when
7598 // we observe the other side of the swap above. We rely on that to
7599 // avoid swapping the members of the input list directly.
7600 Input = SourceHalfMask[Input - SourceOffset] + SourceOffset;
7603 // Map the input's dword into the correct half.
7604 if (PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] == -1)
7605 PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] = Input / 2;
7607 assert(PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] ==
7609 "Previous placement doesn't match!");
7612 // And just directly shift any other-half mask elements to be same-half
7613 // as we will have mirrored the dword containing the element into the
7614 // same position within that half.
7615 for (int &M : HalfMask)
7616 if (M >= SourceOffset && M < SourceOffset + 4) {
7617 M = M - SourceOffset + DestOffset;
7618 assert(M >= 0 && "This should never wrap below zero!");
7623 // Ensure we have the input in a viable dword of its current half. This
7624 // is particularly tricky because the original position may be clobbered
7625 // by inputs being moved and *staying* in that half.
7626 if (IncomingInputs.size() == 1) {
7627 if (isWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
7628 int InputFixed = std::find(std::begin(SourceHalfMask),
7629 std::end(SourceHalfMask), -1) -
7630 std::begin(SourceHalfMask) + SourceOffset;
7631 SourceHalfMask[InputFixed - SourceOffset] =
7632 IncomingInputs[0] - SourceOffset;
7633 std::replace(HalfMask.begin(), HalfMask.end(), IncomingInputs[0],
7635 IncomingInputs[0] = InputFixed;
7637 } else if (IncomingInputs.size() == 2) {
7638 if (IncomingInputs[0] / 2 != IncomingInputs[1] / 2 ||
7639 isDWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
7640 // We have two non-adjacent or clobbered inputs we need to extract from
7641 // the source half. To do this, we need to map them into some adjacent
7642 // dword slot in the source mask.
7643 int InputsFixed[2] = {IncomingInputs[0] - SourceOffset,
7644 IncomingInputs[1] - SourceOffset};
7646 // If there is a free slot in the source half mask adjacent to one of
7647 // the inputs, place the other input in it. We use (Index XOR 1) to
7648 // compute an adjacent index.
7649 if (!isWordClobbered(SourceHalfMask, InputsFixed[0]) &&
7650 SourceHalfMask[InputsFixed[0] ^ 1] == -1) {
7651 SourceHalfMask[InputsFixed[0]] = InputsFixed[0];
7652 SourceHalfMask[InputsFixed[0] ^ 1] = InputsFixed[1];
7653 InputsFixed[1] = InputsFixed[0] ^ 1;
7654 } else if (!isWordClobbered(SourceHalfMask, InputsFixed[1]) &&
7655 SourceHalfMask[InputsFixed[1] ^ 1] == -1) {
7656 SourceHalfMask[InputsFixed[1]] = InputsFixed[1];
7657 SourceHalfMask[InputsFixed[1] ^ 1] = InputsFixed[0];
7658 InputsFixed[0] = InputsFixed[1] ^ 1;
7659 } else if (SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1)] == -1 &&
7660 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1) + 1] == -1) {
7661 // The two inputs are in the same DWord but it is clobbered and the
7662 // adjacent DWord isn't used at all. Move both inputs to the free
7664 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1)] = InputsFixed[0];
7665 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1) + 1] = InputsFixed[1];
7666 InputsFixed[0] = 2 * ((InputsFixed[0] / 2) ^ 1);
7667 InputsFixed[1] = 2 * ((InputsFixed[0] / 2) ^ 1) + 1;
7669 // The only way we hit this point is if there is no clobbering
7670 // (because there are no off-half inputs to this half) and there is no
7671 // free slot adjacent to one of the inputs. In this case, we have to
7672 // swap an input with a non-input.
7673 for (int i = 0; i < 4; ++i)
7674 assert((SourceHalfMask[i] == -1 || SourceHalfMask[i] == i) &&
7675 "We can't handle any clobbers here!");
7676 assert(InputsFixed[1] != (InputsFixed[0] ^ 1) &&
7677 "Cannot have adjacent inputs here!");
7679 SourceHalfMask[InputsFixed[0] ^ 1] = InputsFixed[1];
7680 SourceHalfMask[InputsFixed[1]] = InputsFixed[0] ^ 1;
7682 // We also have to update the final source mask in this case because
7683 // it may need to undo the above swap.
7684 for (int &M : FinalSourceHalfMask)
7685 if (M == (InputsFixed[0] ^ 1) + SourceOffset)
7686 M = InputsFixed[1] + SourceOffset;
7687 else if (M == InputsFixed[1] + SourceOffset)
7688 M = (InputsFixed[0] ^ 1) + SourceOffset;
7690 InputsFixed[1] = InputsFixed[0] ^ 1;
7693 // Point everything at the fixed inputs.
7694 for (int &M : HalfMask)
7695 if (M == IncomingInputs[0])
7696 M = InputsFixed[0] + SourceOffset;
7697 else if (M == IncomingInputs[1])
7698 M = InputsFixed[1] + SourceOffset;
7700 IncomingInputs[0] = InputsFixed[0] + SourceOffset;
7701 IncomingInputs[1] = InputsFixed[1] + SourceOffset;
7704 llvm_unreachable("Unhandled input size!");
7707 // Now hoist the DWord down to the right half.
7708 int FreeDWord = (PSHUFDMask[DestOffset / 2] == -1 ? 0 : 1) + DestOffset / 2;
7709 assert(PSHUFDMask[FreeDWord] == -1 && "DWord not free");
7710 PSHUFDMask[FreeDWord] = IncomingInputs[0] / 2;
7711 for (int &M : HalfMask)
7712 for (int Input : IncomingInputs)
7714 M = FreeDWord * 2 + Input % 2;
7716 moveInputsToRightHalf(HToLInputs, LToLInputs, PSHUFHMask, LoMask, HiMask,
7717 /*SourceOffset*/ 4, /*DestOffset*/ 0);
7718 moveInputsToRightHalf(LToHInputs, HToHInputs, PSHUFLMask, HiMask, LoMask,
7719 /*SourceOffset*/ 0, /*DestOffset*/ 4);
7721 // Now enact all the shuffles we've computed to move the inputs into their
7723 if (!isNoopShuffleMask(PSHUFLMask))
7724 V = DAG.getNode(X86ISD::PSHUFLW, DL, MVT::v8i16, V,
7725 getV4X86ShuffleImm8ForMask(PSHUFLMask, DAG));
7726 if (!isNoopShuffleMask(PSHUFHMask))
7727 V = DAG.getNode(X86ISD::PSHUFHW, DL, MVT::v8i16, V,
7728 getV4X86ShuffleImm8ForMask(PSHUFHMask, DAG));
7729 if (!isNoopShuffleMask(PSHUFDMask))
7730 V = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
7731 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
7732 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V),
7733 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
7735 // At this point, each half should contain all its inputs, and we can then
7736 // just shuffle them into their final position.
7737 assert(std::count_if(LoMask.begin(), LoMask.end(),
7738 [](int M) { return M >= 4; }) == 0 &&
7739 "Failed to lift all the high half inputs to the low mask!");
7740 assert(std::count_if(HiMask.begin(), HiMask.end(),
7741 [](int M) { return M >= 0 && M < 4; }) == 0 &&
7742 "Failed to lift all the low half inputs to the high mask!");
7744 // Do a half shuffle for the low mask.
7745 if (!isNoopShuffleMask(LoMask))
7746 V = DAG.getNode(X86ISD::PSHUFLW, DL, MVT::v8i16, V,
7747 getV4X86ShuffleImm8ForMask(LoMask, DAG));
7749 // Do a half shuffle with the high mask after shifting its values down.
7750 for (int &M : HiMask)
7753 if (!isNoopShuffleMask(HiMask))
7754 V = DAG.getNode(X86ISD::PSHUFHW, DL, MVT::v8i16, V,
7755 getV4X86ShuffleImm8ForMask(HiMask, DAG));
7760 /// \brief Detect whether the mask pattern should be lowered through
7763 /// This essentially tests whether viewing the mask as an interleaving of two
7764 /// sub-sequences reduces the cross-input traffic of a blend operation. If so,
7765 /// lowering it through interleaving is a significantly better strategy.
7766 static bool shouldLowerAsInterleaving(ArrayRef<int> Mask) {
7767 int NumEvenInputs[2] = {0, 0};
7768 int NumOddInputs[2] = {0, 0};
7769 int NumLoInputs[2] = {0, 0};
7770 int NumHiInputs[2] = {0, 0};
7771 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
7775 int InputIdx = Mask[i] >= Size;
7778 ++NumLoInputs[InputIdx];
7780 ++NumHiInputs[InputIdx];
7783 ++NumEvenInputs[InputIdx];
7785 ++NumOddInputs[InputIdx];
7788 // The minimum number of cross-input results for both the interleaved and
7789 // split cases. If interleaving results in fewer cross-input results, return
7791 int InterleavedCrosses = std::min(NumEvenInputs[1] + NumOddInputs[0],
7792 NumEvenInputs[0] + NumOddInputs[1]);
7793 int SplitCrosses = std::min(NumLoInputs[1] + NumHiInputs[0],
7794 NumLoInputs[0] + NumHiInputs[1]);
7795 return InterleavedCrosses < SplitCrosses;
7798 /// \brief Blend two v8i16 vectors using a naive unpack strategy.
7800 /// This strategy only works when the inputs from each vector fit into a single
7801 /// half of that vector, and generally there are not so many inputs as to leave
7802 /// the in-place shuffles required highly constrained (and thus expensive). It
7803 /// shifts all the inputs into a single side of both input vectors and then
7804 /// uses an unpack to interleave these inputs in a single vector. At that
7805 /// point, we will fall back on the generic single input shuffle lowering.
7806 static SDValue lowerV8I16BasicBlendVectorShuffle(SDLoc DL, SDValue V1,
7808 MutableArrayRef<int> Mask,
7809 const X86Subtarget *Subtarget,
7810 SelectionDAG &DAG) {
7811 assert(V1.getSimpleValueType() == MVT::v8i16 && "Bad input type!");
7812 assert(V2.getSimpleValueType() == MVT::v8i16 && "Bad input type!");
7813 SmallVector<int, 3> LoV1Inputs, HiV1Inputs, LoV2Inputs, HiV2Inputs;
7814 for (int i = 0; i < 8; ++i)
7815 if (Mask[i] >= 0 && Mask[i] < 4)
7816 LoV1Inputs.push_back(i);
7817 else if (Mask[i] >= 4 && Mask[i] < 8)
7818 HiV1Inputs.push_back(i);
7819 else if (Mask[i] >= 8 && Mask[i] < 12)
7820 LoV2Inputs.push_back(i);
7821 else if (Mask[i] >= 12)
7822 HiV2Inputs.push_back(i);
7824 int NumV1Inputs = LoV1Inputs.size() + HiV1Inputs.size();
7825 int NumV2Inputs = LoV2Inputs.size() + HiV2Inputs.size();
7828 assert(NumV1Inputs > 0 && NumV1Inputs <= 3 && "At most 3 inputs supported");
7829 assert(NumV2Inputs > 0 && NumV2Inputs <= 3 && "At most 3 inputs supported");
7830 assert(NumV1Inputs + NumV2Inputs <= 4 && "At most 4 combined inputs");
7832 bool MergeFromLo = LoV1Inputs.size() + LoV2Inputs.size() >=
7833 HiV1Inputs.size() + HiV2Inputs.size();
7835 auto moveInputsToHalf = [&](SDValue V, ArrayRef<int> LoInputs,
7836 ArrayRef<int> HiInputs, bool MoveToLo,
7838 ArrayRef<int> GoodInputs = MoveToLo ? LoInputs : HiInputs;
7839 ArrayRef<int> BadInputs = MoveToLo ? HiInputs : LoInputs;
7840 if (BadInputs.empty())
7843 int MoveMask[] = {-1, -1, -1, -1, -1, -1, -1, -1};
7844 int MoveOffset = MoveToLo ? 0 : 4;
7846 if (GoodInputs.empty()) {
7847 for (int BadInput : BadInputs) {
7848 MoveMask[Mask[BadInput] % 4 + MoveOffset] = Mask[BadInput] - MaskOffset;
7849 Mask[BadInput] = Mask[BadInput] % 4 + MoveOffset + MaskOffset;
7852 if (GoodInputs.size() == 2) {
7853 // If the low inputs are spread across two dwords, pack them into
7855 MoveMask[MoveOffset] = Mask[GoodInputs[0]] - MaskOffset;
7856 MoveMask[MoveOffset + 1] = Mask[GoodInputs[1]] - MaskOffset;
7857 Mask[GoodInputs[0]] = MoveOffset + MaskOffset;
7858 Mask[GoodInputs[1]] = MoveOffset + 1 + MaskOffset;
7860 // Otherwise pin the good inputs.
7861 for (int GoodInput : GoodInputs)
7862 MoveMask[Mask[GoodInput] - MaskOffset] = Mask[GoodInput] - MaskOffset;
7865 if (BadInputs.size() == 2) {
7866 // If we have two bad inputs then there may be either one or two good
7867 // inputs fixed in place. Find a fixed input, and then find the *other*
7868 // two adjacent indices by using modular arithmetic.
7870 std::find_if(std::begin(MoveMask) + MoveOffset, std::end(MoveMask),
7871 [](int M) { return M >= 0; }) -
7872 std::begin(MoveMask);
7874 ((((GoodMaskIdx - MoveOffset) & ~1) + 2) % 4) + MoveOffset;
7875 assert(MoveMask[MoveMaskIdx] == -1 && "Expected empty slot");
7876 assert(MoveMask[MoveMaskIdx + 1] == -1 && "Expected empty slot");
7877 MoveMask[MoveMaskIdx] = Mask[BadInputs[0]] - MaskOffset;
7878 MoveMask[MoveMaskIdx + 1] = Mask[BadInputs[1]] - MaskOffset;
7879 Mask[BadInputs[0]] = MoveMaskIdx + MaskOffset;
7880 Mask[BadInputs[1]] = MoveMaskIdx + 1 + MaskOffset;
7882 assert(BadInputs.size() == 1 && "All sizes handled");
7883 int MoveMaskIdx = std::find(std::begin(MoveMask) + MoveOffset,
7884 std::end(MoveMask), -1) -
7885 std::begin(MoveMask);
7886 MoveMask[MoveMaskIdx] = Mask[BadInputs[0]] - MaskOffset;
7887 Mask[BadInputs[0]] = MoveMaskIdx + MaskOffset;
7891 return DAG.getVectorShuffle(MVT::v8i16, DL, V, DAG.getUNDEF(MVT::v8i16),
7894 V1 = moveInputsToHalf(V1, LoV1Inputs, HiV1Inputs, MergeFromLo,
7896 V2 = moveInputsToHalf(V2, LoV2Inputs, HiV2Inputs, MergeFromLo,
7899 // FIXME: Select an interleaving of the merge of V1 and V2 that minimizes
7900 // cross-half traffic in the final shuffle.
7902 // Munge the mask to be a single-input mask after the unpack merges the
7906 M = 2 * (M % 4) + (M / 8);
7908 return DAG.getVectorShuffle(
7909 MVT::v8i16, DL, DAG.getNode(MergeFromLo ? X86ISD::UNPCKL : X86ISD::UNPCKH,
7910 DL, MVT::v8i16, V1, V2),
7911 DAG.getUNDEF(MVT::v8i16), Mask);
7914 /// \brief Generic lowering of 8-lane i16 shuffles.
7916 /// This handles both single-input shuffles and combined shuffle/blends with
7917 /// two inputs. The single input shuffles are immediately delegated to
7918 /// a dedicated lowering routine.
7920 /// The blends are lowered in one of three fundamental ways. If there are few
7921 /// enough inputs, it delegates to a basic UNPCK-based strategy. If the shuffle
7922 /// of the input is significantly cheaper when lowered as an interleaving of
7923 /// the two inputs, try to interleave them. Otherwise, blend the low and high
7924 /// halves of the inputs separately (making them have relatively few inputs)
7925 /// and then concatenate them.
7926 static SDValue lowerV8I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
7927 const X86Subtarget *Subtarget,
7928 SelectionDAG &DAG) {
7930 assert(Op.getSimpleValueType() == MVT::v8i16 && "Bad shuffle type!");
7931 assert(V1.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
7932 assert(V2.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
7933 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7934 ArrayRef<int> OrigMask = SVOp->getMask();
7935 int MaskStorage[8] = {OrigMask[0], OrigMask[1], OrigMask[2], OrigMask[3],
7936 OrigMask[4], OrigMask[5], OrigMask[6], OrigMask[7]};
7937 MutableArrayRef<int> Mask(MaskStorage);
7939 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
7941 auto isV1 = [](int M) { return M >= 0 && M < 8; };
7942 auto isV2 = [](int M) { return M >= 8; };
7944 int NumV1Inputs = std::count_if(Mask.begin(), Mask.end(), isV1);
7945 int NumV2Inputs = std::count_if(Mask.begin(), Mask.end(), isV2);
7947 if (NumV2Inputs == 0)
7948 return lowerV8I16SingleInputVectorShuffle(DL, V1, Mask, Subtarget, DAG);
7950 assert(NumV1Inputs > 0 && "All single-input shuffles should be canonicalized "
7951 "to be V1-input shuffles.");
7953 if (NumV1Inputs + NumV2Inputs <= 4)
7954 return lowerV8I16BasicBlendVectorShuffle(DL, V1, V2, Mask, Subtarget, DAG);
7956 // Check whether an interleaving lowering is likely to be more efficient.
7957 // This isn't perfect but it is a strong heuristic that tends to work well on
7958 // the kinds of shuffles that show up in practice.
7960 // FIXME: Handle 1x, 2x, and 4x interleaving.
7961 if (shouldLowerAsInterleaving(Mask)) {
7962 // FIXME: Figure out whether we should pack these into the low or high
7965 int EMask[8], OMask[8];
7966 for (int i = 0; i < 4; ++i) {
7967 EMask[i] = Mask[2*i];
7968 OMask[i] = Mask[2*i + 1];
7973 SDValue Evens = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, EMask);
7974 SDValue Odds = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, OMask);
7976 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i16, Evens, Odds);
7979 int LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
7980 int HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
7982 for (int i = 0; i < 4; ++i) {
7983 LoBlendMask[i] = Mask[i];
7984 HiBlendMask[i] = Mask[i + 4];
7987 SDValue LoV = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, LoBlendMask);
7988 SDValue HiV = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, HiBlendMask);
7989 LoV = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, LoV);
7990 HiV = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, HiV);
7992 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
7993 DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2i64, LoV, HiV));
7996 /// \brief Check whether a compaction lowering can be done by dropping even
7997 /// elements and compute how many times even elements must be dropped.
7999 /// This handles shuffles which take every Nth element where N is a power of
8000 /// two. Example shuffle masks:
8002 /// N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 0, 2, 4, 6, 8, 10, 12, 14
8003 /// N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30
8004 /// N = 2: 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12
8005 /// N = 2: 0, 4, 8, 12, 16, 20, 24, 28, 0, 4, 8, 12, 16, 20, 24, 28
8006 /// N = 3: 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8
8007 /// N = 3: 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24
8009 /// Any of these lanes can of course be undef.
8011 /// This routine only supports N <= 3.
8012 /// FIXME: Evaluate whether either AVX or AVX-512 have any opportunities here
8015 /// \returns N above, or the number of times even elements must be dropped if
8016 /// there is such a number. Otherwise returns zero.
8017 static int canLowerByDroppingEvenElements(ArrayRef<int> Mask) {
8018 // Figure out whether we're looping over two inputs or just one.
8019 bool IsSingleInput = isSingleInputShuffleMask(Mask);
8021 // The modulus for the shuffle vector entries is based on whether this is
8022 // a single input or not.
8023 int ShuffleModulus = Mask.size() * (IsSingleInput ? 1 : 2);
8024 assert(isPowerOf2_32((uint32_t)ShuffleModulus) &&
8025 "We should only be called with masks with a power-of-2 size!");
8027 uint64_t ModMask = (uint64_t)ShuffleModulus - 1;
8029 // We track whether the input is viable for all power-of-2 strides 2^1, 2^2,
8030 // and 2^3 simultaneously. This is because we may have ambiguity with
8031 // partially undef inputs.
8032 bool ViableForN[3] = {true, true, true};
8034 for (int i = 0, e = Mask.size(); i < e; ++i) {
8035 // Ignore undef lanes, we'll optimistically collapse them to the pattern we
8040 bool IsAnyViable = false;
8041 for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
8042 if (ViableForN[j]) {
8045 // The shuffle mask must be equal to (i * 2^N) % M.
8046 if ((uint64_t)Mask[i] == (((uint64_t)i << N) & ModMask))
8049 ViableForN[j] = false;
8051 // Early exit if we exhaust the possible powers of two.
8056 for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
8060 // Return 0 as there is no viable power of two.
8064 /// \brief Generic lowering of v16i8 shuffles.
8066 /// This is a hybrid strategy to lower v16i8 vectors. It first attempts to
8067 /// detect any complexity reducing interleaving. If that doesn't help, it uses
8068 /// UNPCK to spread the i8 elements across two i16-element vectors, and uses
8069 /// the existing lowering for v8i16 blends on each half, finally PACK-ing them
8071 static SDValue lowerV16I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8072 const X86Subtarget *Subtarget,
8073 SelectionDAG &DAG) {
8075 assert(Op.getSimpleValueType() == MVT::v16i8 && "Bad shuffle type!");
8076 assert(V1.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
8077 assert(V2.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
8078 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8079 ArrayRef<int> OrigMask = SVOp->getMask();
8080 assert(OrigMask.size() == 16 && "Unexpected mask size for v16 shuffle!");
8081 int MaskStorage[16] = {
8082 OrigMask[0], OrigMask[1], OrigMask[2], OrigMask[3],
8083 OrigMask[4], OrigMask[5], OrigMask[6], OrigMask[7],
8084 OrigMask[8], OrigMask[9], OrigMask[10], OrigMask[11],
8085 OrigMask[12], OrigMask[13], OrigMask[14], OrigMask[15]};
8086 MutableArrayRef<int> Mask(MaskStorage);
8087 MutableArrayRef<int> LoMask = Mask.slice(0, 8);
8088 MutableArrayRef<int> HiMask = Mask.slice(8, 8);
8090 // For single-input shuffles, there are some nicer lowering tricks we can use.
8091 if (isSingleInputShuffleMask(Mask)) {
8092 // Check whether we can widen this to an i16 shuffle by duplicating bytes.
8093 // Notably, this handles splat and partial-splat shuffles more efficiently.
8094 // However, it only makes sense if the pre-duplication shuffle simplifies
8095 // things significantly. Currently, this means we need to be able to
8096 // express the pre-duplication shuffle as an i16 shuffle.
8098 // FIXME: We should check for other patterns which can be widened into an
8099 // i16 shuffle as well.
8100 auto canWidenViaDuplication = [](ArrayRef<int> Mask) {
8101 for (int i = 0; i < 16; i += 2) {
8102 if (Mask[i] != Mask[i + 1])
8107 auto tryToWidenViaDuplication = [&]() -> SDValue {
8108 if (!canWidenViaDuplication(Mask))
8110 SmallVector<int, 4> LoInputs;
8111 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(LoInputs),
8112 [](int M) { return M >= 0 && M < 8; });
8113 std::sort(LoInputs.begin(), LoInputs.end());
8114 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()),
8116 SmallVector<int, 4> HiInputs;
8117 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(HiInputs),
8118 [](int M) { return M >= 8; });
8119 std::sort(HiInputs.begin(), HiInputs.end());
8120 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()),
8123 bool TargetLo = LoInputs.size() >= HiInputs.size();
8124 ArrayRef<int> InPlaceInputs = TargetLo ? LoInputs : HiInputs;
8125 ArrayRef<int> MovingInputs = TargetLo ? HiInputs : LoInputs;
8127 int PreDupI16Shuffle[] = {-1, -1, -1, -1, -1, -1, -1, -1};
8128 SmallDenseMap<int, int, 8> LaneMap;
8129 for (int I : InPlaceInputs) {
8130 PreDupI16Shuffle[I/2] = I/2;
8133 int j = TargetLo ? 0 : 4, je = j + 4;
8134 for (int i = 0, ie = MovingInputs.size(); i < ie; ++i) {
8135 // Check if j is already a shuffle of this input. This happens when
8136 // there are two adjacent bytes after we move the low one.
8137 if (PreDupI16Shuffle[j] != MovingInputs[i] / 2) {
8138 // If we haven't yet mapped the input, search for a slot into which
8140 while (j < je && PreDupI16Shuffle[j] != -1)
8144 // We can't place the inputs into a single half with a simple i16 shuffle, so bail.
8147 // Map this input with the i16 shuffle.
8148 PreDupI16Shuffle[j] = MovingInputs[i] / 2;
8151 // Update the lane map based on the mapping we ended up with.
8152 LaneMap[MovingInputs[i]] = 2 * j + MovingInputs[i] % 2;
8155 ISD::BITCAST, DL, MVT::v16i8,
8156 DAG.getVectorShuffle(MVT::v8i16, DL,
8157 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1),
8158 DAG.getUNDEF(MVT::v8i16), PreDupI16Shuffle));
8160 // Unpack the bytes to form the i16s that will be shuffled into place.
8161 V1 = DAG.getNode(TargetLo ? X86ISD::UNPCKL : X86ISD::UNPCKH, DL,
8162 MVT::v16i8, V1, V1);
8164 int PostDupI16Shuffle[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
8165 for (int i = 0; i < 16; i += 2) {
8167 PostDupI16Shuffle[i / 2] = LaneMap[Mask[i]] - (TargetLo ? 0 : 8);
8168 assert(PostDupI16Shuffle[i / 2] < 8 && "Invalid v8 shuffle mask!");
8171 ISD::BITCAST, DL, MVT::v16i8,
8172 DAG.getVectorShuffle(MVT::v8i16, DL,
8173 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1),
8174 DAG.getUNDEF(MVT::v8i16), PostDupI16Shuffle));
8176 if (SDValue V = tryToWidenViaDuplication())
8180 // Check whether an interleaving lowering is likely to be more efficient.
8181 // This isn't perfect but it is a strong heuristic that tends to work well on
8182 // the kinds of shuffles that show up in practice.
8184 // FIXME: We need to handle other interleaving widths (i16, i32, ...).
8185 if (shouldLowerAsInterleaving(Mask)) {
8186 // FIXME: Figure out whether we should pack these into the low or high
8189 int EMask[16], OMask[16];
8190 for (int i = 0; i < 8; ++i) {
8191 EMask[i] = Mask[2*i];
8192 OMask[i] = Mask[2*i + 1];
8197 SDValue Evens = DAG.getVectorShuffle(MVT::v16i8, DL, V1, V2, EMask);
8198 SDValue Odds = DAG.getVectorShuffle(MVT::v16i8, DL, V1, V2, OMask);
8200 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i8, Evens, Odds);
8203 // Check for SSSE3 which lets us lower all v16i8 shuffles much more directly
8204 // with PSHUFB. It is important to do this before we attempt to generate any
8205 // blends but after all of the single-input lowerings. If the single input
8206 // lowerings can find an instruction sequence that is faster than a PSHUFB, we
8207 // want to preserve that and we can DAG combine any longer sequences into
8208 // a PSHUFB in the end. But once we start blending from multiple inputs,
8209 // the complexity of DAG combining bad patterns back into PSHUFB is too high,
8210 // and there are *very* few patterns that would actually be faster than the
8211 // PSHUFB approach because of its ability to zero lanes.
8213 // FIXME: The only exceptions to the above are blends which are exact
8214 // interleavings with direct instructions supporting them. We currently don't
8215 // handle those well here.
8216 if (Subtarget->hasSSSE3()) {
8219 for (int i = 0; i < 16; ++i)
8220 if (Mask[i] == -1) {
8221 V1Mask[i] = V2Mask[i] = DAG.getConstant(0x80, MVT::i8);
8223 V1Mask[i] = DAG.getConstant(Mask[i] < 16 ? Mask[i] : 0x80, MVT::i8);
8225 DAG.getConstant(Mask[i] < 16 ? 0x80 : Mask[i] - 16, MVT::i8);
8227 V1 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, V1,
8228 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V1Mask));
8229 if (isSingleInputShuffleMask(Mask))
8230 return V1; // Single inputs are easy.
8232 // Otherwise, blend the two.
8233 V2 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, V2,
8234 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V2Mask));
8235 return DAG.getNode(ISD::OR, DL, MVT::v16i8, V1, V2);
8238 // Check whether a compaction lowering can be done. This handles shuffles
8239 // which take every Nth element for some even N. See the helper function for
8242 // We special case these as they can be particularly efficiently handled with
8243 // the PACKUSB instruction on x86 and they show up in common patterns of
8244 // rearranging bytes to truncate wide elements.
8245 if (int NumEvenDrops = canLowerByDroppingEvenElements(Mask)) {
8246 // NumEvenDrops is the power of two stride of the elements. Another way of
8247 // thinking about it is that we need to drop the even elements this many
8248 // times to get the original input.
8249 bool IsSingleInput = isSingleInputShuffleMask(Mask);
8251 // First we need to zero all the dropped bytes.
8252 assert(NumEvenDrops <= 3 &&
8253 "No support for dropping even elements more than 3 times.");
8254 // We use the mask type to pick which bytes are preserved based on how many
8255 // elements are dropped.
8256 MVT MaskVTs[] = { MVT::v8i16, MVT::v4i32, MVT::v2i64 };
8257 SDValue ByteClearMask =
8258 DAG.getNode(ISD::BITCAST, DL, MVT::v16i8,
8259 DAG.getConstant(0xFF, MaskVTs[NumEvenDrops - 1]));
8260 V1 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V1, ByteClearMask);
8262 V2 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V2, ByteClearMask);
8264 // Now pack things back together.
8265 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1);
8266 V2 = IsSingleInput ? V1 : DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V2);
8267 SDValue Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, V1, V2);
8268 for (int i = 1; i < NumEvenDrops; ++i) {
8269 Result = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, Result);
8270 Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, Result, Result);
8276 int V1LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
8277 int V1HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
8278 int V2LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
8279 int V2HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
8281 auto buildBlendMasks = [](MutableArrayRef<int> HalfMask,
8282 MutableArrayRef<int> V1HalfBlendMask,
8283 MutableArrayRef<int> V2HalfBlendMask) {
8284 for (int i = 0; i < 8; ++i)
8285 if (HalfMask[i] >= 0 && HalfMask[i] < 16) {
8286 V1HalfBlendMask[i] = HalfMask[i];
8288 } else if (HalfMask[i] >= 16) {
8289 V2HalfBlendMask[i] = HalfMask[i] - 16;
8290 HalfMask[i] = i + 8;
8293 buildBlendMasks(LoMask, V1LoBlendMask, V2LoBlendMask);
8294 buildBlendMasks(HiMask, V1HiBlendMask, V2HiBlendMask);
8296 SDValue Zero = getZeroVector(MVT::v8i16, Subtarget, DAG, DL);
8298 auto buildLoAndHiV8s = [&](SDValue V, MutableArrayRef<int> LoBlendMask,
8299 MutableArrayRef<int> HiBlendMask) {
8301 // Check if any of the odd lanes in the v16i8 are used. If not, we can mask
8302 // them out and avoid using UNPCK{L,H} to extract the elements of V as
8304 if (std::none_of(LoBlendMask.begin(), LoBlendMask.end(),
8305 [](int M) { return M >= 0 && M % 2 == 1; }) &&
8306 std::none_of(HiBlendMask.begin(), HiBlendMask.end(),
8307 [](int M) { return M >= 0 && M % 2 == 1; })) {
8308 // Use a mask to drop the high bytes.
8309 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V);
8310 V1 = DAG.getNode(ISD::AND, DL, MVT::v8i16, V1,
8311 DAG.getConstant(0x00FF, MVT::v8i16));
8313 // This will be a single vector shuffle instead of a blend so nuke V2.
8314 V2 = DAG.getUNDEF(MVT::v8i16);
8316 // Squash the masks to point directly into V1.
8317 for (int &M : LoBlendMask)
8320 for (int &M : HiBlendMask)
8324 // Otherwise just unpack the low half of V into V1 and the high half into
8325 // V2 so that we can blend them as i16s.
8326 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
8327 DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i8, V, Zero));
8328 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
8329 DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i8, V, Zero));
8332 SDValue BlendedLo = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, LoBlendMask);
8333 SDValue BlendedHi = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, HiBlendMask);
8334 return std::make_pair(BlendedLo, BlendedHi);
8336 SDValue V1Lo, V1Hi, V2Lo, V2Hi;
8337 std::tie(V1Lo, V1Hi) = buildLoAndHiV8s(V1, V1LoBlendMask, V1HiBlendMask);
8338 std::tie(V2Lo, V2Hi) = buildLoAndHiV8s(V2, V2LoBlendMask, V2HiBlendMask);
8340 SDValue LoV = DAG.getVectorShuffle(MVT::v8i16, DL, V1Lo, V2Lo, LoMask);
8341 SDValue HiV = DAG.getVectorShuffle(MVT::v8i16, DL, V1Hi, V2Hi, HiMask);
8343 return DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, LoV, HiV);
8346 /// \brief Dispatching routine to lower various 128-bit x86 vector shuffles.
8348 /// This routine breaks down the specific type of 128-bit shuffle and
8349 /// dispatches to the lowering routines accordingly.
8350 static SDValue lower128BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8351 MVT VT, const X86Subtarget *Subtarget,
8352 SelectionDAG &DAG) {
8353 switch (VT.SimpleTy) {
8355 return lowerV2I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
8357 return lowerV2F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
8359 return lowerV4I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
8361 return lowerV4F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
8363 return lowerV8I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
8365 return lowerV16I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
8368 llvm_unreachable("Unimplemented!");
8372 static bool isHalfCrossingShuffleMask(ArrayRef<int> Mask) {
8373 int Size = Mask.size();
8374 for (int M : Mask.slice(0, Size / 2))
8375 if (M >= 0 && (M % Size) >= Size / 2)
8377 for (int M : Mask.slice(Size / 2, Size / 2))
8378 if (M >= 0 && (M % Size) < Size / 2)
8383 /// \brief Generic routine to split a 256-bit vector shuffle into 128-bit
8386 /// There is a severely limited set of shuffles available in AVX1 for 256-bit
8387 /// vectors resulting in routinely needing to split the shuffle into two 128-bit
8388 /// shuffles. This can be done generically for any 256-bit vector shuffle and so
8389 /// we encode the logic here for specific shuffle lowering routines to bail to
8390 /// when they exhaust the features avaible to more directly handle the shuffle.
8391 static SDValue splitAndLower256BitVectorShuffle(SDValue Op, SDValue V1,
8393 const X86Subtarget *Subtarget,
8394 SelectionDAG &DAG) {
8396 MVT VT = Op.getSimpleValueType();
8397 assert(VT.getSizeInBits() == 256 && "Only for 256-bit vector shuffles!");
8398 assert(V1.getSimpleValueType() == VT && "Bad operand type!");
8399 assert(V2.getSimpleValueType() == VT && "Bad operand type!");
8400 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8401 ArrayRef<int> Mask = SVOp->getMask();
8403 ArrayRef<int> LoMask = Mask.slice(0, Mask.size()/2);
8404 ArrayRef<int> HiMask = Mask.slice(Mask.size()/2);
8406 int NumElements = VT.getVectorNumElements();
8407 int SplitNumElements = NumElements / 2;
8408 MVT ScalarVT = VT.getScalarType();
8409 MVT SplitVT = MVT::getVectorVT(ScalarVT, NumElements / 2);
8411 SDValue LoV1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V1,
8412 DAG.getIntPtrConstant(0));
8413 SDValue HiV1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V1,
8414 DAG.getIntPtrConstant(SplitNumElements));
8415 SDValue LoV2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V2,
8416 DAG.getIntPtrConstant(0));
8417 SDValue HiV2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V2,
8418 DAG.getIntPtrConstant(SplitNumElements));
8420 // Now create two 4-way blends of these half-width vectors.
8421 auto HalfBlend = [&](ArrayRef<int> HalfMask) {
8422 SmallVector<int, 16> V1BlendMask, V2BlendMask, BlendMask;
8423 for (int i = 0; i < SplitNumElements; ++i) {
8424 int M = HalfMask[i];
8425 if (M >= NumElements) {
8426 V2BlendMask.push_back(M - NumElements);
8427 V1BlendMask.push_back(-1);
8428 BlendMask.push_back(SplitNumElements + i);
8429 } else if (M >= 0) {
8430 V2BlendMask.push_back(-1);
8431 V1BlendMask.push_back(M);
8432 BlendMask.push_back(i);
8434 V2BlendMask.push_back(-1);
8435 V1BlendMask.push_back(-1);
8436 BlendMask.push_back(-1);
8439 SDValue V1Blend = DAG.getVectorShuffle(SplitVT, DL, LoV1, HiV1, V1BlendMask);
8440 SDValue V2Blend = DAG.getVectorShuffle(SplitVT, DL, LoV2, HiV2, V2BlendMask);
8441 return DAG.getVectorShuffle(SplitVT, DL, V1Blend, V2Blend, BlendMask);
8443 SDValue Lo = HalfBlend(LoMask);
8444 SDValue Hi = HalfBlend(HiMask);
8445 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Lo, Hi);
8448 /// \brief Handle lowering of 4-lane 64-bit floating point shuffles.
8450 /// Also ends up handling lowering of 4-lane 64-bit integer shuffles when AVX2
8451 /// isn't available.
8452 static SDValue lowerV4F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8453 const X86Subtarget *Subtarget,
8454 SelectionDAG &DAG) {
8456 assert(V1.getSimpleValueType() == MVT::v4f64 && "Bad operand type!");
8457 assert(V2.getSimpleValueType() == MVT::v4f64 && "Bad operand type!");
8458 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8459 ArrayRef<int> Mask = SVOp->getMask();
8460 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
8462 // FIXME: If we have AVX2, we should delegate to generic code as crossing
8463 // shuffles aren't a problem and FP and int have the same patterns.
8465 // FIXME: We can handle these more cleverly than splitting for v4f64.
8466 if (isHalfCrossingShuffleMask(Mask))
8467 return splitAndLower256BitVectorShuffle(Op, V1, V2, Subtarget, DAG);
8469 if (isSingleInputShuffleMask(Mask)) {
8470 // Non-half-crossing single input shuffles can be lowerid with an
8471 // interleaved permutation.
8472 unsigned VPERMILPMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1) |
8473 ((Mask[2] == 3) << 2) | ((Mask[3] == 3) << 3);
8474 return DAG.getNode(X86ISD::VPERMILP, DL, MVT::v4f64, V1,
8475 DAG.getConstant(VPERMILPMask, MVT::i8));
8478 // X86 has dedicated unpack instructions that can handle specific blend
8479 // operations: UNPCKH and UNPCKL.
8480 if (isShuffleEquivalent(Mask, 0, 4, 2, 6))
8481 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f64, V1, V2);
8482 if (isShuffleEquivalent(Mask, 1, 5, 3, 7))
8483 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f64, V1, V2);
8484 // FIXME: It would be nice to find a way to get canonicalization to commute
8486 if (isShuffleEquivalent(Mask, 4, 0, 6, 2))
8487 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f64, V2, V1);
8488 if (isShuffleEquivalent(Mask, 5, 1, 7, 3))
8489 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f64, V2, V1);
8491 // Check if the blend happens to exactly fit that of SHUFPD.
8492 if (Mask[0] < 4 && (Mask[1] == -1 || Mask[1] >= 4) &&
8493 Mask[2] < 4 && (Mask[3] == -1 || Mask[3] >= 4)) {
8494 unsigned SHUFPDMask = (Mask[0] == 1) | ((Mask[1] == 5) << 1) |
8495 ((Mask[2] == 3) << 2) | ((Mask[3] == 7) << 3);
8496 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f64, V1, V2,
8497 DAG.getConstant(SHUFPDMask, MVT::i8));
8499 if ((Mask[0] == -1 || Mask[0] >= 4) && Mask[1] < 4 &&
8500 (Mask[2] == -1 || Mask[2] >= 4) && Mask[3] < 4) {
8501 unsigned SHUFPDMask = (Mask[0] == 5) | ((Mask[1] == 1) << 1) |
8502 ((Mask[2] == 7) << 2) | ((Mask[3] == 3) << 3);
8503 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f64, V2, V1,
8504 DAG.getConstant(SHUFPDMask, MVT::i8));
8507 // Shuffle the input elements into the desired positions in V1 and V2 and
8508 // blend them together.
8509 int V1Mask[] = {-1, -1, -1, -1};
8510 int V2Mask[] = {-1, -1, -1, -1};
8511 for (int i = 0; i < 4; ++i)
8512 if (Mask[i] >= 0 && Mask[i] < 4)
8513 V1Mask[i] = Mask[i];
8514 else if (Mask[i] >= 4)
8515 V2Mask[i] = Mask[i] - 4;
8517 V1 = DAG.getVectorShuffle(MVT::v4f64, DL, V1, DAG.getUNDEF(MVT::v4f64), V1Mask);
8518 V2 = DAG.getVectorShuffle(MVT::v4f64, DL, V2, DAG.getUNDEF(MVT::v4f64), V2Mask);
8520 unsigned BlendMask = 0;
8521 for (int i = 0; i < 4; ++i)
8523 BlendMask |= 1 << i;
8525 return DAG.getNode(X86ISD::BLENDI, DL, MVT::v4f64, V1, V2,
8526 DAG.getConstant(BlendMask, MVT::i8));
8529 /// \brief Handle lowering of 4-lane 64-bit integer shuffles.
8531 /// Largely delegates to common code when we have AVX2 and to the floating-point
8532 /// code when we only have AVX.
8533 static SDValue lowerV4I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8534 const X86Subtarget *Subtarget,
8535 SelectionDAG &DAG) {
8537 assert(Op.getSimpleValueType() == MVT::v4i64 && "Bad shuffle type!");
8538 assert(V1.getSimpleValueType() == MVT::v4i64 && "Bad operand type!");
8539 assert(V2.getSimpleValueType() == MVT::v4i64 && "Bad operand type!");
8540 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8541 ArrayRef<int> Mask = SVOp->getMask();
8542 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
8544 // FIXME: If we have AVX2, we should delegate to generic code as crossing
8545 // shuffles aren't a problem and FP and int have the same patterns.
8547 if (isHalfCrossingShuffleMask(Mask))
8548 return splitAndLower256BitVectorShuffle(Op, V1, V2, Subtarget, DAG);
8550 // AVX1 doesn't provide any facilities for v4i64 shuffles, bitcast and
8551 // delegate to floating point code.
8552 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v4f64, V1);
8553 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v4f64, V2);
8554 return DAG.getNode(ISD::BITCAST, DL, MVT::v4i64,
8555 lowerV4F64VectorShuffle(Op, V1, V2, Subtarget, DAG));
8558 /// \brief High-level routine to lower various 256-bit x86 vector shuffles.
8560 /// This routine either breaks down the specific type of a 256-bit x86 vector
8561 /// shuffle or splits it into two 128-bit shuffles and fuses the results back
8562 /// together based on the available instructions.
8563 static SDValue lower256BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8564 MVT VT, const X86Subtarget *Subtarget,
8565 SelectionDAG &DAG) {
8566 switch (VT.SimpleTy) {
8568 return lowerV4F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
8570 return lowerV4I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
8575 // Fall back to the basic pattern of extracting the high half and forming
8577 // FIXME: Add targeted lowering for each type that can document rationale
8578 // for delegating to this when necessary.
8579 return splitAndLower256BitVectorShuffle(Op, V1, V2, Subtarget, DAG);
8582 llvm_unreachable("Not a valid 256-bit x86 vector type!");
8586 /// \brief Tiny helper function to test whether a shuffle mask could be
8587 /// simplified by widening the elements being shuffled.
8588 static bool canWidenShuffleElements(ArrayRef<int> Mask) {
8589 for (int i = 0, Size = Mask.size(); i < Size; i += 2)
8590 if (Mask[i] % 2 != 0 || Mask[i] + 1 != Mask[i+1])
8596 /// \brief Top-level lowering for x86 vector shuffles.
8598 /// This handles decomposition, canonicalization, and lowering of all x86
8599 /// vector shuffles. Most of the specific lowering strategies are encapsulated
8600 /// above in helper routines. The canonicalization attempts to widen shuffles
8601 /// to involve fewer lanes of wider elements, consolidate symmetric patterns
8602 /// s.t. only one of the two inputs needs to be tested, etc.
8603 static SDValue lowerVectorShuffle(SDValue Op, const X86Subtarget *Subtarget,
8604 SelectionDAG &DAG) {
8605 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8606 ArrayRef<int> Mask = SVOp->getMask();
8607 SDValue V1 = Op.getOperand(0);
8608 SDValue V2 = Op.getOperand(1);
8609 MVT VT = Op.getSimpleValueType();
8610 int NumElements = VT.getVectorNumElements();
8613 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
8615 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
8616 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
8617 if (V1IsUndef && V2IsUndef)
8618 return DAG.getUNDEF(VT);
8620 // When we create a shuffle node we put the UNDEF node to second operand,
8621 // but in some cases the first operand may be transformed to UNDEF.
8622 // In this case we should just commute the node.
8624 return DAG.getCommutedVectorShuffle(*SVOp);
8626 // Check for non-undef masks pointing at an undef vector and make the masks
8627 // undef as well. This makes it easier to match the shuffle based solely on
8631 if (M >= NumElements) {
8632 SmallVector<int, 8> NewMask(Mask.begin(), Mask.end());
8633 for (int &M : NewMask)
8634 if (M >= NumElements)
8636 return DAG.getVectorShuffle(VT, dl, V1, V2, NewMask);
8639 // For integer vector shuffles, try to collapse them into a shuffle of fewer
8640 // lanes but wider integers. We cap this to not form integers larger than i64
8641 // but it might be interesting to form i128 integers to handle flipping the
8642 // low and high halves of AVX 256-bit vectors.
8643 if (VT.isInteger() && VT.getScalarSizeInBits() < 64 &&
8644 canWidenShuffleElements(Mask)) {
8645 SmallVector<int, 8> NewMask;
8646 for (int i = 0, Size = Mask.size(); i < Size; i += 2)
8647 NewMask.push_back(Mask[i] / 2);
8649 MVT::getVectorVT(MVT::getIntegerVT(VT.getScalarSizeInBits() * 2),
8650 VT.getVectorNumElements() / 2);
8651 V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, V1);
8652 V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, V2);
8653 return DAG.getNode(ISD::BITCAST, dl, VT,
8654 DAG.getVectorShuffle(NewVT, dl, V1, V2, NewMask));
8657 int NumV1Elements = 0, NumUndefElements = 0, NumV2Elements = 0;
8658 for (int M : SVOp->getMask())
8661 else if (M < NumElements)
8666 // Commute the shuffle as needed such that more elements come from V1 than
8667 // V2. This allows us to match the shuffle pattern strictly on how many
8668 // elements come from V1 without handling the symmetric cases.
8669 if (NumV2Elements > NumV1Elements)
8670 return DAG.getCommutedVectorShuffle(*SVOp);
8672 // When the number of V1 and V2 elements are the same, try to minimize the
8673 // number of uses of V2 in the low half of the vector.
8674 if (NumV1Elements == NumV2Elements) {
8675 int LowV1Elements = 0, LowV2Elements = 0;
8676 for (int M : SVOp->getMask().slice(0, NumElements / 2))
8677 if (M >= NumElements)
8681 if (LowV2Elements > LowV1Elements)
8682 return DAG.getCommutedVectorShuffle(*SVOp);
8685 // For each vector width, delegate to a specialized lowering routine.
8686 if (VT.getSizeInBits() == 128)
8687 return lower128BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
8689 if (VT.getSizeInBits() == 256)
8690 return lower256BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
8692 llvm_unreachable("Unimplemented!");
8696 //===----------------------------------------------------------------------===//
8697 // Legacy vector shuffle lowering
8699 // This code is the legacy code handling vector shuffles until the above
8700 // replaces its functionality and performance.
8701 //===----------------------------------------------------------------------===//
8703 static bool isBlendMask(ArrayRef<int> MaskVals, MVT VT, bool hasSSE41,
8704 bool hasInt256, unsigned *MaskOut = nullptr) {
8705 MVT EltVT = VT.getVectorElementType();
8707 // There is no blend with immediate in AVX-512.
8708 if (VT.is512BitVector())
8711 if (!hasSSE41 || EltVT == MVT::i8)
8713 if (!hasInt256 && VT == MVT::v16i16)
8716 unsigned MaskValue = 0;
8717 unsigned NumElems = VT.getVectorNumElements();
8718 // There are 2 lanes if (NumElems > 8), and 1 lane otherwise.
8719 unsigned NumLanes = (NumElems - 1) / 8 + 1;
8720 unsigned NumElemsInLane = NumElems / NumLanes;
8722 // Blend for v16i16 should be symetric for the both lanes.
8723 for (unsigned i = 0; i < NumElemsInLane; ++i) {
8725 int SndLaneEltIdx = (NumLanes == 2) ? MaskVals[i + NumElemsInLane] : -1;
8726 int EltIdx = MaskVals[i];
8728 if ((EltIdx < 0 || EltIdx == (int)i) &&
8729 (SndLaneEltIdx < 0 || SndLaneEltIdx == (int)(i + NumElemsInLane)))
8732 if (((unsigned)EltIdx == (i + NumElems)) &&
8733 (SndLaneEltIdx < 0 ||
8734 (unsigned)SndLaneEltIdx == i + NumElems + NumElemsInLane))
8735 MaskValue |= (1 << i);
8741 *MaskOut = MaskValue;
8745 // Try to lower a shuffle node into a simple blend instruction.
8746 // This function assumes isBlendMask returns true for this
8747 // SuffleVectorSDNode
8748 static SDValue LowerVECTOR_SHUFFLEtoBlend(ShuffleVectorSDNode *SVOp,
8750 const X86Subtarget *Subtarget,
8751 SelectionDAG &DAG) {
8752 MVT VT = SVOp->getSimpleValueType(0);
8753 MVT EltVT = VT.getVectorElementType();
8754 assert(isBlendMask(SVOp->getMask(), VT, Subtarget->hasSSE41(),
8755 Subtarget->hasInt256() && "Trying to lower a "
8756 "VECTOR_SHUFFLE to a Blend but "
8757 "with the wrong mask"));
8758 SDValue V1 = SVOp->getOperand(0);
8759 SDValue V2 = SVOp->getOperand(1);
8761 unsigned NumElems = VT.getVectorNumElements();
8763 // Convert i32 vectors to floating point if it is not AVX2.
8764 // AVX2 introduced VPBLENDD instruction for 128 and 256-bit vectors.
8766 if (EltVT == MVT::i64 || (EltVT == MVT::i32 && !Subtarget->hasInt256())) {
8767 BlendVT = MVT::getVectorVT(MVT::getFloatingPointVT(EltVT.getSizeInBits()),
8769 V1 = DAG.getNode(ISD::BITCAST, dl, VT, V1);
8770 V2 = DAG.getNode(ISD::BITCAST, dl, VT, V2);
8773 SDValue Ret = DAG.getNode(X86ISD::BLENDI, dl, BlendVT, V1, V2,
8774 DAG.getConstant(MaskValue, MVT::i32));
8775 return DAG.getNode(ISD::BITCAST, dl, VT, Ret);
8778 /// In vector type \p VT, return true if the element at index \p InputIdx
8779 /// falls on a different 128-bit lane than \p OutputIdx.
8780 static bool ShuffleCrosses128bitLane(MVT VT, unsigned InputIdx,
8781 unsigned OutputIdx) {
8782 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
8783 return InputIdx * EltSize / 128 != OutputIdx * EltSize / 128;
8786 /// Generate a PSHUFB if possible. Selects elements from \p V1 according to
8787 /// \p MaskVals. MaskVals[OutputIdx] = InputIdx specifies that we want to
8788 /// shuffle the element at InputIdx in V1 to OutputIdx in the result. If \p
8789 /// MaskVals refers to elements outside of \p V1 or is undef (-1), insert a
8791 static SDValue getPSHUFB(ArrayRef<int> MaskVals, SDValue V1, SDLoc &dl,
8792 SelectionDAG &DAG) {
8793 MVT VT = V1.getSimpleValueType();
8794 assert(VT.is128BitVector() || VT.is256BitVector());
8796 MVT EltVT = VT.getVectorElementType();
8797 unsigned EltSizeInBytes = EltVT.getSizeInBits() / 8;
8798 unsigned NumElts = VT.getVectorNumElements();
8800 SmallVector<SDValue, 32> PshufbMask;
8801 for (unsigned OutputIdx = 0; OutputIdx < NumElts; ++OutputIdx) {
8802 int InputIdx = MaskVals[OutputIdx];
8803 unsigned InputByteIdx;
8805 if (InputIdx < 0 || NumElts <= (unsigned)InputIdx)
8806 InputByteIdx = 0x80;
8808 // Cross lane is not allowed.
8809 if (ShuffleCrosses128bitLane(VT, InputIdx, OutputIdx))
8811 InputByteIdx = InputIdx * EltSizeInBytes;
8812 // Index is an byte offset within the 128-bit lane.
8813 InputByteIdx &= 0xf;
8816 for (unsigned j = 0; j < EltSizeInBytes; ++j) {
8817 PshufbMask.push_back(DAG.getConstant(InputByteIdx, MVT::i8));
8818 if (InputByteIdx != 0x80)
8823 MVT ShufVT = MVT::getVectorVT(MVT::i8, PshufbMask.size());
8825 V1 = DAG.getNode(ISD::BITCAST, dl, ShufVT, V1);
8826 return DAG.getNode(X86ISD::PSHUFB, dl, ShufVT, V1,
8827 DAG.getNode(ISD::BUILD_VECTOR, dl, ShufVT, PshufbMask));
8830 // v8i16 shuffles - Prefer shuffles in the following order:
8831 // 1. [all] pshuflw, pshufhw, optional move
8832 // 2. [ssse3] 1 x pshufb
8833 // 3. [ssse3] 2 x pshufb + 1 x por
8834 // 4. [all] mov + pshuflw + pshufhw + N x (pextrw + pinsrw)
8836 LowerVECTOR_SHUFFLEv8i16(SDValue Op, const X86Subtarget *Subtarget,
8837 SelectionDAG &DAG) {
8838 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8839 SDValue V1 = SVOp->getOperand(0);
8840 SDValue V2 = SVOp->getOperand(1);
8842 SmallVector<int, 8> MaskVals;
8844 // Determine if more than 1 of the words in each of the low and high quadwords
8845 // of the result come from the same quadword of one of the two inputs. Undef
8846 // mask values count as coming from any quadword, for better codegen.
8848 // Lo/HiQuad[i] = j indicates how many words from the ith quad of the input
8849 // feeds this quad. For i, 0 and 1 refer to V1, 2 and 3 refer to V2.
8850 unsigned LoQuad[] = { 0, 0, 0, 0 };
8851 unsigned HiQuad[] = { 0, 0, 0, 0 };
8852 // Indices of quads used.
8853 std::bitset<4> InputQuads;
8854 for (unsigned i = 0; i < 8; ++i) {
8855 unsigned *Quad = i < 4 ? LoQuad : HiQuad;
8856 int EltIdx = SVOp->getMaskElt(i);
8857 MaskVals.push_back(EltIdx);
8866 InputQuads.set(EltIdx / 4);
8869 int BestLoQuad = -1;
8870 unsigned MaxQuad = 1;
8871 for (unsigned i = 0; i < 4; ++i) {
8872 if (LoQuad[i] > MaxQuad) {
8874 MaxQuad = LoQuad[i];
8878 int BestHiQuad = -1;
8880 for (unsigned i = 0; i < 4; ++i) {
8881 if (HiQuad[i] > MaxQuad) {
8883 MaxQuad = HiQuad[i];
8887 // For SSSE3, If all 8 words of the result come from only 1 quadword of each
8888 // of the two input vectors, shuffle them into one input vector so only a
8889 // single pshufb instruction is necessary. If there are more than 2 input
8890 // quads, disable the next transformation since it does not help SSSE3.
8891 bool V1Used = InputQuads[0] || InputQuads[1];
8892 bool V2Used = InputQuads[2] || InputQuads[3];
8893 if (Subtarget->hasSSSE3()) {
8894 if (InputQuads.count() == 2 && V1Used && V2Used) {
8895 BestLoQuad = InputQuads[0] ? 0 : 1;
8896 BestHiQuad = InputQuads[2] ? 2 : 3;
8898 if (InputQuads.count() > 2) {
8904 // If BestLoQuad or BestHiQuad are set, shuffle the quads together and update
8905 // the shuffle mask. If a quad is scored as -1, that means that it contains
8906 // words from all 4 input quadwords.
8908 if (BestLoQuad >= 0 || BestHiQuad >= 0) {
8910 BestLoQuad < 0 ? 0 : BestLoQuad,
8911 BestHiQuad < 0 ? 1 : BestHiQuad
8913 NewV = DAG.getVectorShuffle(MVT::v2i64, dl,
8914 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V1),
8915 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V2), &MaskV[0]);
8916 NewV = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, NewV);
8918 // Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the
8919 // source words for the shuffle, to aid later transformations.
8920 bool AllWordsInNewV = true;
8921 bool InOrder[2] = { true, true };
8922 for (unsigned i = 0; i != 8; ++i) {
8923 int idx = MaskVals[i];
8925 InOrder[i/4] = false;
8926 if (idx < 0 || (idx/4) == BestLoQuad || (idx/4) == BestHiQuad)
8928 AllWordsInNewV = false;
8932 bool pshuflw = AllWordsInNewV, pshufhw = AllWordsInNewV;
8933 if (AllWordsInNewV) {
8934 for (int i = 0; i != 8; ++i) {
8935 int idx = MaskVals[i];
8938 idx = MaskVals[i] = (idx / 4) == BestLoQuad ? (idx & 3) : (idx & 3) + 4;
8939 if ((idx != i) && idx < 4)
8941 if ((idx != i) && idx > 3)
8950 // If we've eliminated the use of V2, and the new mask is a pshuflw or
8951 // pshufhw, that's as cheap as it gets. Return the new shuffle.
8952 if ((pshufhw && InOrder[0]) || (pshuflw && InOrder[1])) {
8953 unsigned Opc = pshufhw ? X86ISD::PSHUFHW : X86ISD::PSHUFLW;
8954 unsigned TargetMask = 0;
8955 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV,
8956 DAG.getUNDEF(MVT::v8i16), &MaskVals[0]);
8957 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
8958 TargetMask = pshufhw ? getShufflePSHUFHWImmediate(SVOp):
8959 getShufflePSHUFLWImmediate(SVOp);
8960 V1 = NewV.getOperand(0);
8961 return getTargetShuffleNode(Opc, dl, MVT::v8i16, V1, TargetMask, DAG);
8965 // Promote splats to a larger type which usually leads to more efficient code.
8966 // FIXME: Is this true if pshufb is available?
8967 if (SVOp->isSplat())
8968 return PromoteSplat(SVOp, DAG);
8970 // If we have SSSE3, and all words of the result are from 1 input vector,
8971 // case 2 is generated, otherwise case 3 is generated. If no SSSE3
8972 // is present, fall back to case 4.
8973 if (Subtarget->hasSSSE3()) {
8974 SmallVector<SDValue,16> pshufbMask;
8976 // If we have elements from both input vectors, set the high bit of the
8977 // shuffle mask element to zero out elements that come from V2 in the V1
8978 // mask, and elements that come from V1 in the V2 mask, so that the two
8979 // results can be OR'd together.
8980 bool TwoInputs = V1Used && V2Used;
8981 V1 = getPSHUFB(MaskVals, V1, dl, DAG);
8983 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
8985 // Calculate the shuffle mask for the second input, shuffle it, and
8986 // OR it with the first shuffled input.
8987 CommuteVectorShuffleMask(MaskVals, 8);
8988 V2 = getPSHUFB(MaskVals, V2, dl, DAG);
8989 V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
8990 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
8993 // If BestLoQuad >= 0, generate a pshuflw to put the low elements in order,
8994 // and update MaskVals with new element order.
8995 std::bitset<8> InOrder;
8996 if (BestLoQuad >= 0) {
8997 int MaskV[] = { -1, -1, -1, -1, 4, 5, 6, 7 };
8998 for (int i = 0; i != 4; ++i) {
8999 int idx = MaskVals[i];
9002 } else if ((idx / 4) == BestLoQuad) {
9007 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
9010 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSE2()) {
9011 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
9012 NewV = getTargetShuffleNode(X86ISD::PSHUFLW, dl, MVT::v8i16,
9014 getShufflePSHUFLWImmediate(SVOp), DAG);
9018 // If BestHi >= 0, generate a pshufhw to put the high elements in order,
9019 // and update MaskVals with the new element order.
9020 if (BestHiQuad >= 0) {
9021 int MaskV[] = { 0, 1, 2, 3, -1, -1, -1, -1 };
9022 for (unsigned i = 4; i != 8; ++i) {
9023 int idx = MaskVals[i];
9026 } else if ((idx / 4) == BestHiQuad) {
9027 MaskV[i] = (idx & 3) + 4;
9031 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
9034 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSE2()) {
9035 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
9036 NewV = getTargetShuffleNode(X86ISD::PSHUFHW, dl, MVT::v8i16,
9038 getShufflePSHUFHWImmediate(SVOp), DAG);
9042 // In case BestHi & BestLo were both -1, which means each quadword has a word
9043 // from each of the four input quadwords, calculate the InOrder bitvector now
9044 // before falling through to the insert/extract cleanup.
9045 if (BestLoQuad == -1 && BestHiQuad == -1) {
9047 for (int i = 0; i != 8; ++i)
9048 if (MaskVals[i] < 0 || MaskVals[i] == i)
9052 // The other elements are put in the right place using pextrw and pinsrw.
9053 for (unsigned i = 0; i != 8; ++i) {
9056 int EltIdx = MaskVals[i];
9059 SDValue ExtOp = (EltIdx < 8) ?
9060 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1,
9061 DAG.getIntPtrConstant(EltIdx)) :
9062 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2,
9063 DAG.getIntPtrConstant(EltIdx - 8));
9064 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp,
9065 DAG.getIntPtrConstant(i));
9070 /// \brief v16i16 shuffles
9072 /// FIXME: We only support generation of a single pshufb currently. We can
9073 /// generalize the other applicable cases from LowerVECTOR_SHUFFLEv8i16 as
9074 /// well (e.g 2 x pshufb + 1 x por).
9076 LowerVECTOR_SHUFFLEv16i16(SDValue Op, SelectionDAG &DAG) {
9077 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9078 SDValue V1 = SVOp->getOperand(0);
9079 SDValue V2 = SVOp->getOperand(1);
9082 if (V2.getOpcode() != ISD::UNDEF)
9085 SmallVector<int, 16> MaskVals(SVOp->getMask().begin(), SVOp->getMask().end());
9086 return getPSHUFB(MaskVals, V1, dl, DAG);
9089 // v16i8 shuffles - Prefer shuffles in the following order:
9090 // 1. [ssse3] 1 x pshufb
9091 // 2. [ssse3] 2 x pshufb + 1 x por
9092 // 3. [all] v8i16 shuffle + N x pextrw + rotate + pinsrw
9093 static SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp,
9094 const X86Subtarget* Subtarget,
9095 SelectionDAG &DAG) {
9096 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
9097 SDValue V1 = SVOp->getOperand(0);
9098 SDValue V2 = SVOp->getOperand(1);
9100 ArrayRef<int> MaskVals = SVOp->getMask();
9102 // Promote splats to a larger type which usually leads to more efficient code.
9103 // FIXME: Is this true if pshufb is available?
9104 if (SVOp->isSplat())
9105 return PromoteSplat(SVOp, DAG);
9107 // If we have SSSE3, case 1 is generated when all result bytes come from
9108 // one of the inputs. Otherwise, case 2 is generated. If no SSSE3 is
9109 // present, fall back to case 3.
9111 // If SSSE3, use 1 pshufb instruction per vector with elements in the result.
9112 if (Subtarget->hasSSSE3()) {
9113 SmallVector<SDValue,16> pshufbMask;
9115 // If all result elements are from one input vector, then only translate
9116 // undef mask values to 0x80 (zero out result) in the pshufb mask.
9118 // Otherwise, we have elements from both input vectors, and must zero out
9119 // elements that come from V2 in the first mask, and V1 in the second mask
9120 // so that we can OR them together.
9121 for (unsigned i = 0; i != 16; ++i) {
9122 int EltIdx = MaskVals[i];
9123 if (EltIdx < 0 || EltIdx >= 16)
9125 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
9127 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
9128 DAG.getNode(ISD::BUILD_VECTOR, dl,
9129 MVT::v16i8, pshufbMask));
9131 // As PSHUFB will zero elements with negative indices, it's safe to ignore
9132 // the 2nd operand if it's undefined or zero.
9133 if (V2.getOpcode() == ISD::UNDEF ||
9134 ISD::isBuildVectorAllZeros(V2.getNode()))
9137 // Calculate the shuffle mask for the second input, shuffle it, and
9138 // OR it with the first shuffled input.
9140 for (unsigned i = 0; i != 16; ++i) {
9141 int EltIdx = MaskVals[i];
9142 EltIdx = (EltIdx < 16) ? 0x80 : EltIdx - 16;
9143 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
9145 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
9146 DAG.getNode(ISD::BUILD_VECTOR, dl,
9147 MVT::v16i8, pshufbMask));
9148 return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
9151 // No SSSE3 - Calculate in place words and then fix all out of place words
9152 // With 0-16 extracts & inserts. Worst case is 16 bytes out of order from
9153 // the 16 different words that comprise the two doublequadword input vectors.
9154 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
9155 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V2);
9157 for (int i = 0; i != 8; ++i) {
9158 int Elt0 = MaskVals[i*2];
9159 int Elt1 = MaskVals[i*2+1];
9161 // This word of the result is all undef, skip it.
9162 if (Elt0 < 0 && Elt1 < 0)
9165 // This word of the result is already in the correct place, skip it.
9166 if ((Elt0 == i*2) && (Elt1 == i*2+1))
9169 SDValue Elt0Src = Elt0 < 16 ? V1 : V2;
9170 SDValue Elt1Src = Elt1 < 16 ? V1 : V2;
9173 // If Elt0 and Elt1 are defined, are consecutive, and can be load
9174 // using a single extract together, load it and store it.
9175 if ((Elt0 >= 0) && ((Elt0 + 1) == Elt1) && ((Elt0 & 1) == 0)) {
9176 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
9177 DAG.getIntPtrConstant(Elt1 / 2));
9178 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
9179 DAG.getIntPtrConstant(i));
9183 // If Elt1 is defined, extract it from the appropriate source. If the
9184 // source byte is not also odd, shift the extracted word left 8 bits
9185 // otherwise clear the bottom 8 bits if we need to do an or.
9187 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
9188 DAG.getIntPtrConstant(Elt1 / 2));
9189 if ((Elt1 & 1) == 0)
9190 InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt,
9192 TLI.getShiftAmountTy(InsElt.getValueType())));
9194 InsElt = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt,
9195 DAG.getConstant(0xFF00, MVT::i16));
9197 // If Elt0 is defined, extract it from the appropriate source. If the
9198 // source byte is not also even, shift the extracted word right 8 bits. If
9199 // Elt1 was also defined, OR the extracted values together before
9200 // inserting them in the result.
9202 SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16,
9203 Elt0Src, DAG.getIntPtrConstant(Elt0 / 2));
9204 if ((Elt0 & 1) != 0)
9205 InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0,
9207 TLI.getShiftAmountTy(InsElt0.getValueType())));
9209 InsElt0 = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt0,
9210 DAG.getConstant(0x00FF, MVT::i16));
9211 InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0)
9214 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
9215 DAG.getIntPtrConstant(i));
9217 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, NewV);
9220 // v32i8 shuffles - Translate to VPSHUFB if possible.
9222 SDValue LowerVECTOR_SHUFFLEv32i8(ShuffleVectorSDNode *SVOp,
9223 const X86Subtarget *Subtarget,
9224 SelectionDAG &DAG) {
9225 MVT VT = SVOp->getSimpleValueType(0);
9226 SDValue V1 = SVOp->getOperand(0);
9227 SDValue V2 = SVOp->getOperand(1);
9229 SmallVector<int, 32> MaskVals(SVOp->getMask().begin(), SVOp->getMask().end());
9231 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
9232 bool V1IsAllZero = ISD::isBuildVectorAllZeros(V1.getNode());
9233 bool V2IsAllZero = ISD::isBuildVectorAllZeros(V2.getNode());
9235 // VPSHUFB may be generated if
9236 // (1) one of input vector is undefined or zeroinitializer.
9237 // The mask value 0x80 puts 0 in the corresponding slot of the vector.
9238 // And (2) the mask indexes don't cross the 128-bit lane.
9239 if (VT != MVT::v32i8 || !Subtarget->hasInt256() ||
9240 (!V2IsUndef && !V2IsAllZero && !V1IsAllZero))
9243 if (V1IsAllZero && !V2IsAllZero) {
9244 CommuteVectorShuffleMask(MaskVals, 32);
9247 return getPSHUFB(MaskVals, V1, dl, DAG);
9250 /// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide
9251 /// ones, or rewriting v4i32 / v4f32 as 2 wide ones if possible. This can be
9252 /// done when every pair / quad of shuffle mask elements point to elements in
9253 /// the right sequence. e.g.
9254 /// vector_shuffle X, Y, <2, 3, | 10, 11, | 0, 1, | 14, 15>
9256 SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp,
9257 SelectionDAG &DAG) {
9258 MVT VT = SVOp->getSimpleValueType(0);
9260 unsigned NumElems = VT.getVectorNumElements();
9263 switch (VT.SimpleTy) {
9264 default: llvm_unreachable("Unexpected!");
9267 return SDValue(SVOp, 0);
9268 case MVT::v4f32: NewVT = MVT::v2f64; Scale = 2; break;
9269 case MVT::v4i32: NewVT = MVT::v2i64; Scale = 2; break;
9270 case MVT::v8i16: NewVT = MVT::v4i32; Scale = 2; break;
9271 case MVT::v16i8: NewVT = MVT::v4i32; Scale = 4; break;
9272 case MVT::v16i16: NewVT = MVT::v8i32; Scale = 2; break;
9273 case MVT::v32i8: NewVT = MVT::v8i32; Scale = 4; break;
9276 SmallVector<int, 8> MaskVec;
9277 for (unsigned i = 0; i != NumElems; i += Scale) {
9279 for (unsigned j = 0; j != Scale; ++j) {
9280 int EltIdx = SVOp->getMaskElt(i+j);
9284 StartIdx = (EltIdx / Scale);
9285 if (EltIdx != (int)(StartIdx*Scale + j))
9288 MaskVec.push_back(StartIdx);
9291 SDValue V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(0));
9292 SDValue V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(1));
9293 return DAG.getVectorShuffle(NewVT, dl, V1, V2, &MaskVec[0]);
9296 /// getVZextMovL - Return a zero-extending vector move low node.
9298 static SDValue getVZextMovL(MVT VT, MVT OpVT,
9299 SDValue SrcOp, SelectionDAG &DAG,
9300 const X86Subtarget *Subtarget, SDLoc dl) {
9301 if (VT == MVT::v2f64 || VT == MVT::v4f32) {
9302 LoadSDNode *LD = nullptr;
9303 if (!isScalarLoadToVector(SrcOp.getNode(), &LD))
9304 LD = dyn_cast<LoadSDNode>(SrcOp);
9306 // movssrr and movsdrr do not clear top bits. Try to use movd, movq
9308 MVT ExtVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32;
9309 if ((ExtVT != MVT::i64 || Subtarget->is64Bit()) &&
9310 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR &&
9311 SrcOp.getOperand(0).getOpcode() == ISD::BITCAST &&
9312 SrcOp.getOperand(0).getOperand(0).getValueType() == ExtVT) {
9314 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32;
9315 return DAG.getNode(ISD::BITCAST, dl, VT,
9316 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
9317 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
9325 return DAG.getNode(ISD::BITCAST, dl, VT,
9326 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
9327 DAG.getNode(ISD::BITCAST, dl,
9331 /// LowerVECTOR_SHUFFLE_256 - Handle all 256-bit wide vectors shuffles
9332 /// which could not be matched by any known target speficic shuffle
9334 LowerVECTOR_SHUFFLE_256(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
9336 SDValue NewOp = Compact8x32ShuffleNode(SVOp, DAG);
9337 if (NewOp.getNode())
9340 MVT VT = SVOp->getSimpleValueType(0);
9342 unsigned NumElems = VT.getVectorNumElements();
9343 unsigned NumLaneElems = NumElems / 2;
9346 MVT EltVT = VT.getVectorElementType();
9347 MVT NVT = MVT::getVectorVT(EltVT, NumLaneElems);
9350 SmallVector<int, 16> Mask;
9351 for (unsigned l = 0; l < 2; ++l) {
9352 // Build a shuffle mask for the output, discovering on the fly which
9353 // input vectors to use as shuffle operands (recorded in InputUsed).
9354 // If building a suitable shuffle vector proves too hard, then bail
9355 // out with UseBuildVector set.
9356 bool UseBuildVector = false;
9357 int InputUsed[2] = { -1, -1 }; // Not yet discovered.
9358 unsigned LaneStart = l * NumLaneElems;
9359 for (unsigned i = 0; i != NumLaneElems; ++i) {
9360 // The mask element. This indexes into the input.
9361 int Idx = SVOp->getMaskElt(i+LaneStart);
9363 // the mask element does not index into any input vector.
9368 // The input vector this mask element indexes into.
9369 int Input = Idx / NumLaneElems;
9371 // Turn the index into an offset from the start of the input vector.
9372 Idx -= Input * NumLaneElems;
9374 // Find or create a shuffle vector operand to hold this input.
9376 for (OpNo = 0; OpNo < array_lengthof(InputUsed); ++OpNo) {
9377 if (InputUsed[OpNo] == Input)
9378 // This input vector is already an operand.
9380 if (InputUsed[OpNo] < 0) {
9381 // Create a new operand for this input vector.
9382 InputUsed[OpNo] = Input;
9387 if (OpNo >= array_lengthof(InputUsed)) {
9388 // More than two input vectors used! Give up on trying to create a
9389 // shuffle vector. Insert all elements into a BUILD_VECTOR instead.
9390 UseBuildVector = true;
9394 // Add the mask index for the new shuffle vector.
9395 Mask.push_back(Idx + OpNo * NumLaneElems);
9398 if (UseBuildVector) {
9399 SmallVector<SDValue, 16> SVOps;
9400 for (unsigned i = 0; i != NumLaneElems; ++i) {
9401 // The mask element. This indexes into the input.
9402 int Idx = SVOp->getMaskElt(i+LaneStart);
9404 SVOps.push_back(DAG.getUNDEF(EltVT));
9408 // The input vector this mask element indexes into.
9409 int Input = Idx / NumElems;
9411 // Turn the index into an offset from the start of the input vector.
9412 Idx -= Input * NumElems;
9414 // Extract the vector element by hand.
9415 SVOps.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
9416 SVOp->getOperand(Input),
9417 DAG.getIntPtrConstant(Idx)));
9420 // Construct the output using a BUILD_VECTOR.
9421 Output[l] = DAG.getNode(ISD::BUILD_VECTOR, dl, NVT, SVOps);
9422 } else if (InputUsed[0] < 0) {
9423 // No input vectors were used! The result is undefined.
9424 Output[l] = DAG.getUNDEF(NVT);
9426 SDValue Op0 = Extract128BitVector(SVOp->getOperand(InputUsed[0] / 2),
9427 (InputUsed[0] % 2) * NumLaneElems,
9429 // If only one input was used, use an undefined vector for the other.
9430 SDValue Op1 = (InputUsed[1] < 0) ? DAG.getUNDEF(NVT) :
9431 Extract128BitVector(SVOp->getOperand(InputUsed[1] / 2),
9432 (InputUsed[1] % 2) * NumLaneElems, DAG, dl);
9433 // At least one input vector was used. Create a new shuffle vector.
9434 Output[l] = DAG.getVectorShuffle(NVT, dl, Op0, Op1, &Mask[0]);
9440 // Concatenate the result back
9441 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, Output[0], Output[1]);
9444 /// LowerVECTOR_SHUFFLE_128v4 - Handle all 128-bit wide vectors with
9445 /// 4 elements, and match them with several different shuffle types.
9447 LowerVECTOR_SHUFFLE_128v4(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
9448 SDValue V1 = SVOp->getOperand(0);
9449 SDValue V2 = SVOp->getOperand(1);
9451 MVT VT = SVOp->getSimpleValueType(0);
9453 assert(VT.is128BitVector() && "Unsupported vector size");
9455 std::pair<int, int> Locs[4];
9456 int Mask1[] = { -1, -1, -1, -1 };
9457 SmallVector<int, 8> PermMask(SVOp->getMask().begin(), SVOp->getMask().end());
9461 for (unsigned i = 0; i != 4; ++i) {
9462 int Idx = PermMask[i];
9464 Locs[i] = std::make_pair(-1, -1);
9466 assert(Idx < 8 && "Invalid VECTOR_SHUFFLE index!");
9468 Locs[i] = std::make_pair(0, NumLo);
9472 Locs[i] = std::make_pair(1, NumHi);
9474 Mask1[2+NumHi] = Idx;
9480 if (NumLo <= 2 && NumHi <= 2) {
9481 // If no more than two elements come from either vector. This can be
9482 // implemented with two shuffles. First shuffle gather the elements.
9483 // The second shuffle, which takes the first shuffle as both of its
9484 // vector operands, put the elements into the right order.
9485 V1 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
9487 int Mask2[] = { -1, -1, -1, -1 };
9489 for (unsigned i = 0; i != 4; ++i)
9490 if (Locs[i].first != -1) {
9491 unsigned Idx = (i < 2) ? 0 : 4;
9492 Idx += Locs[i].first * 2 + Locs[i].second;
9496 return DAG.getVectorShuffle(VT, dl, V1, V1, &Mask2[0]);
9499 if (NumLo == 3 || NumHi == 3) {
9500 // Otherwise, we must have three elements from one vector, call it X, and
9501 // one element from the other, call it Y. First, use a shufps to build an
9502 // intermediate vector with the one element from Y and the element from X
9503 // that will be in the same half in the final destination (the indexes don't
9504 // matter). Then, use a shufps to build the final vector, taking the half
9505 // containing the element from Y from the intermediate, and the other half
9508 // Normalize it so the 3 elements come from V1.
9509 CommuteVectorShuffleMask(PermMask, 4);
9513 // Find the element from V2.
9515 for (HiIndex = 0; HiIndex < 3; ++HiIndex) {
9516 int Val = PermMask[HiIndex];
9523 Mask1[0] = PermMask[HiIndex];
9525 Mask1[2] = PermMask[HiIndex^1];
9527 V2 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
9530 Mask1[0] = PermMask[0];
9531 Mask1[1] = PermMask[1];
9532 Mask1[2] = HiIndex & 1 ? 6 : 4;
9533 Mask1[3] = HiIndex & 1 ? 4 : 6;
9534 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
9537 Mask1[0] = HiIndex & 1 ? 2 : 0;
9538 Mask1[1] = HiIndex & 1 ? 0 : 2;
9539 Mask1[2] = PermMask[2];
9540 Mask1[3] = PermMask[3];
9545 return DAG.getVectorShuffle(VT, dl, V2, V1, &Mask1[0]);
9548 // Break it into (shuffle shuffle_hi, shuffle_lo).
9549 int LoMask[] = { -1, -1, -1, -1 };
9550 int HiMask[] = { -1, -1, -1, -1 };
9552 int *MaskPtr = LoMask;
9553 unsigned MaskIdx = 0;
9556 for (unsigned i = 0; i != 4; ++i) {
9563 int Idx = PermMask[i];
9565 Locs[i] = std::make_pair(-1, -1);
9566 } else if (Idx < 4) {
9567 Locs[i] = std::make_pair(MaskIdx, LoIdx);
9568 MaskPtr[LoIdx] = Idx;
9571 Locs[i] = std::make_pair(MaskIdx, HiIdx);
9572 MaskPtr[HiIdx] = Idx;
9577 SDValue LoShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &LoMask[0]);
9578 SDValue HiShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &HiMask[0]);
9579 int MaskOps[] = { -1, -1, -1, -1 };
9580 for (unsigned i = 0; i != 4; ++i)
9581 if (Locs[i].first != -1)
9582 MaskOps[i] = Locs[i].first * 4 + Locs[i].second;
9583 return DAG.getVectorShuffle(VT, dl, LoShuffle, HiShuffle, &MaskOps[0]);
9586 static bool MayFoldVectorLoad(SDValue V) {
9587 while (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
9588 V = V.getOperand(0);
9590 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR)
9591 V = V.getOperand(0);
9592 if (V.hasOneUse() && V.getOpcode() == ISD::BUILD_VECTOR &&
9593 V.getNumOperands() == 2 && V.getOperand(1).getOpcode() == ISD::UNDEF)
9594 // BUILD_VECTOR (load), undef
9595 V = V.getOperand(0);
9597 return MayFoldLoad(V);
9601 SDValue getMOVDDup(SDValue &Op, SDLoc &dl, SDValue V1, SelectionDAG &DAG) {
9602 MVT VT = Op.getSimpleValueType();
9604 // Canonizalize to v2f64.
9605 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, V1);
9606 return DAG.getNode(ISD::BITCAST, dl, VT,
9607 getTargetShuffleNode(X86ISD::MOVDDUP, dl, MVT::v2f64,
9612 SDValue getMOVLowToHigh(SDValue &Op, SDLoc &dl, SelectionDAG &DAG,
9614 SDValue V1 = Op.getOperand(0);
9615 SDValue V2 = Op.getOperand(1);
9616 MVT VT = Op.getSimpleValueType();
9618 assert(VT != MVT::v2i64 && "unsupported shuffle type");
9620 if (HasSSE2 && VT == MVT::v2f64)
9621 return getTargetShuffleNode(X86ISD::MOVLHPD, dl, VT, V1, V2, DAG);
9623 // v4f32 or v4i32: canonizalized to v4f32 (which is legal for SSE1)
9624 return DAG.getNode(ISD::BITCAST, dl, VT,
9625 getTargetShuffleNode(X86ISD::MOVLHPS, dl, MVT::v4f32,
9626 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V1),
9627 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V2), DAG));
9631 SDValue getMOVHighToLow(SDValue &Op, SDLoc &dl, SelectionDAG &DAG) {
9632 SDValue V1 = Op.getOperand(0);
9633 SDValue V2 = Op.getOperand(1);
9634 MVT VT = Op.getSimpleValueType();
9636 assert((VT == MVT::v4i32 || VT == MVT::v4f32) &&
9637 "unsupported shuffle type");
9639 if (V2.getOpcode() == ISD::UNDEF)
9643 return getTargetShuffleNode(X86ISD::MOVHLPS, dl, VT, V1, V2, DAG);
9647 SDValue getMOVLP(SDValue &Op, SDLoc &dl, SelectionDAG &DAG, bool HasSSE2) {
9648 SDValue V1 = Op.getOperand(0);
9649 SDValue V2 = Op.getOperand(1);
9650 MVT VT = Op.getSimpleValueType();
9651 unsigned NumElems = VT.getVectorNumElements();
9653 // Use MOVLPS and MOVLPD in case V1 or V2 are loads. During isel, the second
9654 // operand of these instructions is only memory, so check if there's a
9655 // potencial load folding here, otherwise use SHUFPS or MOVSD to match the
9657 bool CanFoldLoad = false;
9659 // Trivial case, when V2 comes from a load.
9660 if (MayFoldVectorLoad(V2))
9663 // When V1 is a load, it can be folded later into a store in isel, example:
9664 // (store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)), addr:$src1)
9666 // (MOVLPSmr addr:$src1, VR128:$src2)
9667 // So, recognize this potential and also use MOVLPS or MOVLPD
9668 else if (MayFoldVectorLoad(V1) && MayFoldIntoStore(Op))
9671 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9673 if (HasSSE2 && NumElems == 2)
9674 return getTargetShuffleNode(X86ISD::MOVLPD, dl, VT, V1, V2, DAG);
9677 // If we don't care about the second element, proceed to use movss.
9678 if (SVOp->getMaskElt(1) != -1)
9679 return getTargetShuffleNode(X86ISD::MOVLPS, dl, VT, V1, V2, DAG);
9682 // movl and movlp will both match v2i64, but v2i64 is never matched by
9683 // movl earlier because we make it strict to avoid messing with the movlp load
9684 // folding logic (see the code above getMOVLP call). Match it here then,
9685 // this is horrible, but will stay like this until we move all shuffle
9686 // matching to x86 specific nodes. Note that for the 1st condition all
9687 // types are matched with movsd.
9689 // FIXME: isMOVLMask should be checked and matched before getMOVLP,
9690 // as to remove this logic from here, as much as possible
9691 if (NumElems == 2 || !isMOVLMask(SVOp->getMask(), VT))
9692 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
9693 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
9696 assert(VT != MVT::v4i32 && "unsupported shuffle type");
9698 // Invert the operand order and use SHUFPS to match it.
9699 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V2, V1,
9700 getShuffleSHUFImmediate(SVOp), DAG);
9703 static SDValue NarrowVectorLoadToElement(LoadSDNode *Load, unsigned Index,
9704 SelectionDAG &DAG) {
9706 MVT VT = Load->getSimpleValueType(0);
9707 MVT EVT = VT.getVectorElementType();
9708 SDValue Addr = Load->getOperand(1);
9709 SDValue NewAddr = DAG.getNode(
9710 ISD::ADD, dl, Addr.getSimpleValueType(), Addr,
9711 DAG.getConstant(Index * EVT.getStoreSize(), Addr.getSimpleValueType()));
9714 DAG.getLoad(EVT, dl, Load->getChain(), NewAddr,
9715 DAG.getMachineFunction().getMachineMemOperand(
9716 Load->getMemOperand(), 0, EVT.getStoreSize()));
9720 // It is only safe to call this function if isINSERTPSMask is true for
9721 // this shufflevector mask.
9722 static SDValue getINSERTPS(ShuffleVectorSDNode *SVOp, SDLoc &dl,
9723 SelectionDAG &DAG) {
9724 // Generate an insertps instruction when inserting an f32 from memory onto a
9725 // v4f32 or when copying a member from one v4f32 to another.
9726 // We also use it for transferring i32 from one register to another,
9727 // since it simply copies the same bits.
9728 // If we're transferring an i32 from memory to a specific element in a
9729 // register, we output a generic DAG that will match the PINSRD
9731 MVT VT = SVOp->getSimpleValueType(0);
9732 MVT EVT = VT.getVectorElementType();
9733 SDValue V1 = SVOp->getOperand(0);
9734 SDValue V2 = SVOp->getOperand(1);
9735 auto Mask = SVOp->getMask();
9736 assert((VT == MVT::v4f32 || VT == MVT::v4i32) &&
9737 "unsupported vector type for insertps/pinsrd");
9739 auto FromV1Predicate = [](const int &i) { return i < 4 && i > -1; };
9740 auto FromV2Predicate = [](const int &i) { return i >= 4; };
9741 int FromV1 = std::count_if(Mask.begin(), Mask.end(), FromV1Predicate);
9749 DestIndex = std::find_if(Mask.begin(), Mask.end(), FromV1Predicate) -
9752 // If we have 1 element from each vector, we have to check if we're
9753 // changing V1's element's place. If so, we're done. Otherwise, we
9754 // should assume we're changing V2's element's place and behave
9756 int FromV2 = std::count_if(Mask.begin(), Mask.end(), FromV2Predicate);
9757 assert(DestIndex <= INT32_MAX && "truncated destination index");
9758 if (FromV1 == FromV2 &&
9759 static_cast<int>(DestIndex) == Mask[DestIndex] % 4) {
9763 std::find_if(Mask.begin(), Mask.end(), FromV2Predicate) - Mask.begin();
9766 assert(std::count_if(Mask.begin(), Mask.end(), FromV2Predicate) == 1 &&
9767 "More than one element from V1 and from V2, or no elements from one "
9768 "of the vectors. This case should not have returned true from "
9773 std::find_if(Mask.begin(), Mask.end(), FromV2Predicate) - Mask.begin();
9776 // Get an index into the source vector in the range [0,4) (the mask is
9777 // in the range [0,8) because it can address V1 and V2)
9778 unsigned SrcIndex = Mask[DestIndex] % 4;
9779 if (MayFoldLoad(From)) {
9780 // Trivial case, when From comes from a load and is only used by the
9781 // shuffle. Make it use insertps from the vector that we need from that
9784 NarrowVectorLoadToElement(cast<LoadSDNode>(From), SrcIndex, DAG);
9785 if (!NewLoad.getNode())
9788 if (EVT == MVT::f32) {
9789 // Create this as a scalar to vector to match the instruction pattern.
9790 SDValue LoadScalarToVector =
9791 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, NewLoad);
9792 SDValue InsertpsMask = DAG.getIntPtrConstant(DestIndex << 4);
9793 return DAG.getNode(X86ISD::INSERTPS, dl, VT, To, LoadScalarToVector,
9795 } else { // EVT == MVT::i32
9796 // If we're getting an i32 from memory, use an INSERT_VECTOR_ELT
9797 // instruction, to match the PINSRD instruction, which loads an i32 to a
9798 // certain vector element.
9799 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, To, NewLoad,
9800 DAG.getConstant(DestIndex, MVT::i32));
9804 // Vector-element-to-vector
9805 SDValue InsertpsMask = DAG.getIntPtrConstant(DestIndex << 4 | SrcIndex << 6);
9806 return DAG.getNode(X86ISD::INSERTPS, dl, VT, To, From, InsertpsMask);
9809 // Reduce a vector shuffle to zext.
9810 static SDValue LowerVectorIntExtend(SDValue Op, const X86Subtarget *Subtarget,
9811 SelectionDAG &DAG) {
9812 // PMOVZX is only available from SSE41.
9813 if (!Subtarget->hasSSE41())
9816 MVT VT = Op.getSimpleValueType();
9818 // Only AVX2 support 256-bit vector integer extending.
9819 if (!Subtarget->hasInt256() && VT.is256BitVector())
9822 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9824 SDValue V1 = Op.getOperand(0);
9825 SDValue V2 = Op.getOperand(1);
9826 unsigned NumElems = VT.getVectorNumElements();
9828 // Extending is an unary operation and the element type of the source vector
9829 // won't be equal to or larger than i64.
9830 if (V2.getOpcode() != ISD::UNDEF || !VT.isInteger() ||
9831 VT.getVectorElementType() == MVT::i64)
9834 // Find the expansion ratio, e.g. expanding from i8 to i32 has a ratio of 4.
9835 unsigned Shift = 1; // Start from 2, i.e. 1 << 1.
9836 while ((1U << Shift) < NumElems) {
9837 if (SVOp->getMaskElt(1U << Shift) == 1)
9840 // The maximal ratio is 8, i.e. from i8 to i64.
9845 // Check the shuffle mask.
9846 unsigned Mask = (1U << Shift) - 1;
9847 for (unsigned i = 0; i != NumElems; ++i) {
9848 int EltIdx = SVOp->getMaskElt(i);
9849 if ((i & Mask) != 0 && EltIdx != -1)
9851 if ((i & Mask) == 0 && (unsigned)EltIdx != (i >> Shift))
9855 unsigned NBits = VT.getVectorElementType().getSizeInBits() << Shift;
9856 MVT NeVT = MVT::getIntegerVT(NBits);
9857 MVT NVT = MVT::getVectorVT(NeVT, NumElems >> Shift);
9859 if (!DAG.getTargetLoweringInfo().isTypeLegal(NVT))
9862 // Simplify the operand as it's prepared to be fed into shuffle.
9863 unsigned SignificantBits = NVT.getSizeInBits() >> Shift;
9864 if (V1.getOpcode() == ISD::BITCAST &&
9865 V1.getOperand(0).getOpcode() == ISD::SCALAR_TO_VECTOR &&
9866 V1.getOperand(0).getOperand(0).getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
9867 V1.getOperand(0).getOperand(0)
9868 .getSimpleValueType().getSizeInBits() == SignificantBits) {
9869 // (bitcast (sclr2vec (ext_vec_elt x))) -> (bitcast x)
9870 SDValue V = V1.getOperand(0).getOperand(0).getOperand(0);
9871 ConstantSDNode *CIdx =
9872 dyn_cast<ConstantSDNode>(V1.getOperand(0).getOperand(0).getOperand(1));
9873 // If it's foldable, i.e. normal load with single use, we will let code
9874 // selection to fold it. Otherwise, we will short the conversion sequence.
9875 if (CIdx && CIdx->getZExtValue() == 0 &&
9876 (!ISD::isNormalLoad(V.getNode()) || !V.hasOneUse())) {
9877 MVT FullVT = V.getSimpleValueType();
9878 MVT V1VT = V1.getSimpleValueType();
9879 if (FullVT.getSizeInBits() > V1VT.getSizeInBits()) {
9880 // The "ext_vec_elt" node is wider than the result node.
9881 // In this case we should extract subvector from V.
9882 // (bitcast (sclr2vec (ext_vec_elt x))) -> (bitcast (extract_subvector x)).
9883 unsigned Ratio = FullVT.getSizeInBits() / V1VT.getSizeInBits();
9884 MVT SubVecVT = MVT::getVectorVT(FullVT.getVectorElementType(),
9885 FullVT.getVectorNumElements()/Ratio);
9886 V = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVecVT, V,
9887 DAG.getIntPtrConstant(0));
9889 V1 = DAG.getNode(ISD::BITCAST, DL, V1VT, V);
9893 return DAG.getNode(ISD::BITCAST, DL, VT,
9894 DAG.getNode(X86ISD::VZEXT, DL, NVT, V1));
9897 static SDValue NormalizeVectorShuffle(SDValue Op, const X86Subtarget *Subtarget,
9898 SelectionDAG &DAG) {
9899 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9900 MVT VT = Op.getSimpleValueType();
9902 SDValue V1 = Op.getOperand(0);
9903 SDValue V2 = Op.getOperand(1);
9905 if (isZeroShuffle(SVOp))
9906 return getZeroVector(VT, Subtarget, DAG, dl);
9908 // Handle splat operations
9909 if (SVOp->isSplat()) {
9910 // Use vbroadcast whenever the splat comes from a foldable load
9911 SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG);
9912 if (Broadcast.getNode())
9916 // Check integer expanding shuffles.
9917 SDValue NewOp = LowerVectorIntExtend(Op, Subtarget, DAG);
9918 if (NewOp.getNode())
9921 // If the shuffle can be profitably rewritten as a narrower shuffle, then
9923 if (VT == MVT::v8i16 || VT == MVT::v16i8 || VT == MVT::v16i16 ||
9925 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
9926 if (NewOp.getNode())
9927 return DAG.getNode(ISD::BITCAST, dl, VT, NewOp);
9928 } else if (VT.is128BitVector() && Subtarget->hasSSE2()) {
9929 // FIXME: Figure out a cleaner way to do this.
9930 if (ISD::isBuildVectorAllZeros(V2.getNode())) {
9931 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
9932 if (NewOp.getNode()) {
9933 MVT NewVT = NewOp.getSimpleValueType();
9934 if (isCommutedMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(),
9935 NewVT, true, false))
9936 return getVZextMovL(VT, NewVT, NewOp.getOperand(0), DAG, Subtarget,
9939 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) {
9940 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
9941 if (NewOp.getNode()) {
9942 MVT NewVT = NewOp.getSimpleValueType();
9943 if (isMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(), NewVT))
9944 return getVZextMovL(VT, NewVT, NewOp.getOperand(1), DAG, Subtarget,
9953 X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const {
9954 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9955 SDValue V1 = Op.getOperand(0);
9956 SDValue V2 = Op.getOperand(1);
9957 MVT VT = Op.getSimpleValueType();
9959 unsigned NumElems = VT.getVectorNumElements();
9960 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
9961 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
9962 bool V1IsSplat = false;
9963 bool V2IsSplat = false;
9964 bool HasSSE2 = Subtarget->hasSSE2();
9965 bool HasFp256 = Subtarget->hasFp256();
9966 bool HasInt256 = Subtarget->hasInt256();
9967 MachineFunction &MF = DAG.getMachineFunction();
9968 bool OptForSize = MF.getFunction()->getAttributes().
9969 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
9971 // Check if we should use the experimental vector shuffle lowering. If so,
9972 // delegate completely to that code path.
9973 if (ExperimentalVectorShuffleLowering)
9974 return lowerVectorShuffle(Op, Subtarget, DAG);
9976 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
9978 if (V1IsUndef && V2IsUndef)
9979 return DAG.getUNDEF(VT);
9981 // When we create a shuffle node we put the UNDEF node to second operand,
9982 // but in some cases the first operand may be transformed to UNDEF.
9983 // In this case we should just commute the node.
9985 return DAG.getCommutedVectorShuffle(*SVOp);
9987 // Vector shuffle lowering takes 3 steps:
9989 // 1) Normalize the input vectors. Here splats, zeroed vectors, profitable
9990 // narrowing and commutation of operands should be handled.
9991 // 2) Matching of shuffles with known shuffle masks to x86 target specific
9993 // 3) Rewriting of unmatched masks into new generic shuffle operations,
9994 // so the shuffle can be broken into other shuffles and the legalizer can
9995 // try the lowering again.
9997 // The general idea is that no vector_shuffle operation should be left to
9998 // be matched during isel, all of them must be converted to a target specific
10001 // Normalize the input vectors. Here splats, zeroed vectors, profitable
10002 // narrowing and commutation of operands should be handled. The actual code
10003 // doesn't include all of those, work in progress...
10004 SDValue NewOp = NormalizeVectorShuffle(Op, Subtarget, DAG);
10005 if (NewOp.getNode())
10008 SmallVector<int, 8> M(SVOp->getMask().begin(), SVOp->getMask().end());
10010 // NOTE: isPSHUFDMask can also match both masks below (unpckl_undef and
10011 // unpckh_undef). Only use pshufd if speed is more important than size.
10012 if (OptForSize && isUNPCKL_v_undef_Mask(M, VT, HasInt256))
10013 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
10014 if (OptForSize && isUNPCKH_v_undef_Mask(M, VT, HasInt256))
10015 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
10017 if (isMOVDDUPMask(M, VT) && Subtarget->hasSSE3() &&
10018 V2IsUndef && MayFoldVectorLoad(V1))
10019 return getMOVDDup(Op, dl, V1, DAG);
10021 if (isMOVHLPS_v_undef_Mask(M, VT))
10022 return getMOVHighToLow(Op, dl, DAG);
10024 // Use to match splats
10025 if (HasSSE2 && isUNPCKHMask(M, VT, HasInt256) && V2IsUndef &&
10026 (VT == MVT::v2f64 || VT == MVT::v2i64))
10027 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
10029 if (isPSHUFDMask(M, VT)) {
10030 // The actual implementation will match the mask in the if above and then
10031 // during isel it can match several different instructions, not only pshufd
10032 // as its name says, sad but true, emulate the behavior for now...
10033 if (isMOVDDUPMask(M, VT) && ((VT == MVT::v4f32 || VT == MVT::v2i64)))
10034 return getTargetShuffleNode(X86ISD::MOVLHPS, dl, VT, V1, V1, DAG);
10036 unsigned TargetMask = getShuffleSHUFImmediate(SVOp);
10038 if (HasSSE2 && (VT == MVT::v4f32 || VT == MVT::v4i32))
10039 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1, TargetMask, DAG);
10041 if (HasFp256 && (VT == MVT::v4f32 || VT == MVT::v2f64))
10042 return getTargetShuffleNode(X86ISD::VPERMILP, dl, VT, V1, TargetMask,
10045 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V1,
10049 if (isPALIGNRMask(M, VT, Subtarget))
10050 return getTargetShuffleNode(X86ISD::PALIGNR, dl, VT, V1, V2,
10051 getShufflePALIGNRImmediate(SVOp),
10054 if (isVALIGNMask(M, VT, Subtarget))
10055 return getTargetShuffleNode(X86ISD::VALIGN, dl, VT, V1, V2,
10056 getShuffleVALIGNImmediate(SVOp),
10059 // Check if this can be converted into a logical shift.
10060 bool isLeft = false;
10061 unsigned ShAmt = 0;
10063 bool isShift = HasSSE2 && isVectorShift(SVOp, DAG, isLeft, ShVal, ShAmt);
10064 if (isShift && ShVal.hasOneUse()) {
10065 // If the shifted value has multiple uses, it may be cheaper to use
10066 // v_set0 + movlhps or movhlps, etc.
10067 MVT EltVT = VT.getVectorElementType();
10068 ShAmt *= EltVT.getSizeInBits();
10069 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
10072 if (isMOVLMask(M, VT)) {
10073 if (ISD::isBuildVectorAllZeros(V1.getNode()))
10074 return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl);
10075 if (!isMOVLPMask(M, VT)) {
10076 if (HasSSE2 && (VT == MVT::v2i64 || VT == MVT::v2f64))
10077 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
10079 if (VT == MVT::v4i32 || VT == MVT::v4f32)
10080 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
10084 // FIXME: fold these into legal mask.
10085 if (isMOVLHPSMask(M, VT) && !isUNPCKLMask(M, VT, HasInt256))
10086 return getMOVLowToHigh(Op, dl, DAG, HasSSE2);
10088 if (isMOVHLPSMask(M, VT))
10089 return getMOVHighToLow(Op, dl, DAG);
10091 if (V2IsUndef && isMOVSHDUPMask(M, VT, Subtarget))
10092 return getTargetShuffleNode(X86ISD::MOVSHDUP, dl, VT, V1, DAG);
10094 if (V2IsUndef && isMOVSLDUPMask(M, VT, Subtarget))
10095 return getTargetShuffleNode(X86ISD::MOVSLDUP, dl, VT, V1, DAG);
10097 if (isMOVLPMask(M, VT))
10098 return getMOVLP(Op, dl, DAG, HasSSE2);
10100 if (ShouldXformToMOVHLPS(M, VT) ||
10101 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), M, VT))
10102 return DAG.getCommutedVectorShuffle(*SVOp);
10105 // No better options. Use a vshldq / vsrldq.
10106 MVT EltVT = VT.getVectorElementType();
10107 ShAmt *= EltVT.getSizeInBits();
10108 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
10111 bool Commuted = false;
10112 // FIXME: This should also accept a bitcast of a splat? Be careful, not
10113 // 1,1,1,1 -> v8i16 though.
10114 BitVector UndefElements;
10115 if (auto *BVOp = dyn_cast<BuildVectorSDNode>(V1.getNode()))
10116 if (BVOp->getConstantSplatNode(&UndefElements) && UndefElements.none())
10118 if (auto *BVOp = dyn_cast<BuildVectorSDNode>(V2.getNode()))
10119 if (BVOp->getConstantSplatNode(&UndefElements) && UndefElements.none())
10122 // Canonicalize the splat or undef, if present, to be on the RHS.
10123 if (!V2IsUndef && V1IsSplat && !V2IsSplat) {
10124 CommuteVectorShuffleMask(M, NumElems);
10126 std::swap(V1IsSplat, V2IsSplat);
10130 if (isCommutedMOVLMask(M, VT, V2IsSplat, V2IsUndef)) {
10131 // Shuffling low element of v1 into undef, just return v1.
10134 // If V2 is a splat, the mask may be malformed such as <4,3,3,3>, which
10135 // the instruction selector will not match, so get a canonical MOVL with
10136 // swapped operands to undo the commute.
10137 return getMOVL(DAG, dl, VT, V2, V1);
10140 if (isUNPCKLMask(M, VT, HasInt256))
10141 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
10143 if (isUNPCKHMask(M, VT, HasInt256))
10144 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
10147 // Normalize mask so all entries that point to V2 points to its first
10148 // element then try to match unpck{h|l} again. If match, return a
10149 // new vector_shuffle with the corrected mask.p
10150 SmallVector<int, 8> NewMask(M.begin(), M.end());
10151 NormalizeMask(NewMask, NumElems);
10152 if (isUNPCKLMask(NewMask, VT, HasInt256, true))
10153 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
10154 if (isUNPCKHMask(NewMask, VT, HasInt256, true))
10155 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
10159 // Commute is back and try unpck* again.
10160 // FIXME: this seems wrong.
10161 CommuteVectorShuffleMask(M, NumElems);
10163 std::swap(V1IsSplat, V2IsSplat);
10165 if (isUNPCKLMask(M, VT, HasInt256))
10166 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
10168 if (isUNPCKHMask(M, VT, HasInt256))
10169 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
10172 // Normalize the node to match x86 shuffle ops if needed
10173 if (!V2IsUndef && (isSHUFPMask(M, VT, /* Commuted */ true)))
10174 return DAG.getCommutedVectorShuffle(*SVOp);
10176 // The checks below are all present in isShuffleMaskLegal, but they are
10177 // inlined here right now to enable us to directly emit target specific
10178 // nodes, and remove one by one until they don't return Op anymore.
10180 if (ShuffleVectorSDNode::isSplatMask(&M[0], VT) &&
10181 SVOp->getSplatIndex() == 0 && V2IsUndef) {
10182 if (VT == MVT::v2f64 || VT == MVT::v2i64)
10183 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
10186 if (isPSHUFHWMask(M, VT, HasInt256))
10187 return getTargetShuffleNode(X86ISD::PSHUFHW, dl, VT, V1,
10188 getShufflePSHUFHWImmediate(SVOp),
10191 if (isPSHUFLWMask(M, VT, HasInt256))
10192 return getTargetShuffleNode(X86ISD::PSHUFLW, dl, VT, V1,
10193 getShufflePSHUFLWImmediate(SVOp),
10196 unsigned MaskValue;
10197 if (isBlendMask(M, VT, Subtarget->hasSSE41(), Subtarget->hasInt256(),
10199 return LowerVECTOR_SHUFFLEtoBlend(SVOp, MaskValue, Subtarget, DAG);
10201 if (isSHUFPMask(M, VT))
10202 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V2,
10203 getShuffleSHUFImmediate(SVOp), DAG);
10205 if (isUNPCKL_v_undef_Mask(M, VT, HasInt256))
10206 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
10207 if (isUNPCKH_v_undef_Mask(M, VT, HasInt256))
10208 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
10210 //===--------------------------------------------------------------------===//
10211 // Generate target specific nodes for 128 or 256-bit shuffles only
10212 // supported in the AVX instruction set.
10215 // Handle VMOVDDUPY permutations
10216 if (V2IsUndef && isMOVDDUPYMask(M, VT, HasFp256))
10217 return getTargetShuffleNode(X86ISD::MOVDDUP, dl, VT, V1, DAG);
10219 // Handle VPERMILPS/D* permutations
10220 if (isVPERMILPMask(M, VT)) {
10221 if ((HasInt256 && VT == MVT::v8i32) || VT == MVT::v16i32)
10222 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1,
10223 getShuffleSHUFImmediate(SVOp), DAG);
10224 return getTargetShuffleNode(X86ISD::VPERMILP, dl, VT, V1,
10225 getShuffleSHUFImmediate(SVOp), DAG);
10229 if (VT.is512BitVector() && isINSERT64x4Mask(M, VT, &Idx))
10230 return Insert256BitVector(V1, Extract256BitVector(V2, 0, DAG, dl),
10231 Idx*(NumElems/2), DAG, dl);
10233 // Handle VPERM2F128/VPERM2I128 permutations
10234 if (isVPERM2X128Mask(M, VT, HasFp256))
10235 return getTargetShuffleNode(X86ISD::VPERM2X128, dl, VT, V1,
10236 V2, getShuffleVPERM2X128Immediate(SVOp), DAG);
10238 if (Subtarget->hasSSE41() && isINSERTPSMask(M, VT))
10239 return getINSERTPS(SVOp, dl, DAG);
10242 if (V2IsUndef && HasInt256 && isPermImmMask(M, VT, Imm8))
10243 return getTargetShuffleNode(X86ISD::VPERMI, dl, VT, V1, Imm8, DAG);
10245 if ((V2IsUndef && HasInt256 && VT.is256BitVector() && NumElems == 8) ||
10246 VT.is512BitVector()) {
10247 MVT MaskEltVT = MVT::getIntegerVT(VT.getVectorElementType().getSizeInBits());
10248 MVT MaskVectorVT = MVT::getVectorVT(MaskEltVT, NumElems);
10249 SmallVector<SDValue, 16> permclMask;
10250 for (unsigned i = 0; i != NumElems; ++i) {
10251 permclMask.push_back(DAG.getConstant((M[i]>=0) ? M[i] : 0, MaskEltVT));
10254 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVectorVT, permclMask);
10256 // Bitcast is for VPERMPS since mask is v8i32 but node takes v8f32
10257 return DAG.getNode(X86ISD::VPERMV, dl, VT,
10258 DAG.getNode(ISD::BITCAST, dl, VT, Mask), V1);
10259 return DAG.getNode(X86ISD::VPERMV3, dl, VT, V1,
10260 DAG.getNode(ISD::BITCAST, dl, VT, Mask), V2);
10263 //===--------------------------------------------------------------------===//
10264 // Since no target specific shuffle was selected for this generic one,
10265 // lower it into other known shuffles. FIXME: this isn't true yet, but
10266 // this is the plan.
10269 // Handle v8i16 specifically since SSE can do byte extraction and insertion.
10270 if (VT == MVT::v8i16) {
10271 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(Op, Subtarget, DAG);
10272 if (NewOp.getNode())
10276 if (VT == MVT::v16i16 && Subtarget->hasInt256()) {
10277 SDValue NewOp = LowerVECTOR_SHUFFLEv16i16(Op, DAG);
10278 if (NewOp.getNode())
10282 if (VT == MVT::v16i8) {
10283 SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(SVOp, Subtarget, DAG);
10284 if (NewOp.getNode())
10288 if (VT == MVT::v32i8) {
10289 SDValue NewOp = LowerVECTOR_SHUFFLEv32i8(SVOp, Subtarget, DAG);
10290 if (NewOp.getNode())
10294 // Handle all 128-bit wide vectors with 4 elements, and match them with
10295 // several different shuffle types.
10296 if (NumElems == 4 && VT.is128BitVector())
10297 return LowerVECTOR_SHUFFLE_128v4(SVOp, DAG);
10299 // Handle general 256-bit shuffles
10300 if (VT.is256BitVector())
10301 return LowerVECTOR_SHUFFLE_256(SVOp, DAG);
10306 // This function assumes its argument is a BUILD_VECTOR of constants or
10307 // undef SDNodes. i.e: ISD::isBuildVectorOfConstantSDNodes(BuildVector) is
10309 static bool BUILD_VECTORtoBlendMask(BuildVectorSDNode *BuildVector,
10310 unsigned &MaskValue) {
10312 unsigned NumElems = BuildVector->getNumOperands();
10313 // There are 2 lanes if (NumElems > 8), and 1 lane otherwise.
10314 unsigned NumLanes = (NumElems - 1) / 8 + 1;
10315 unsigned NumElemsInLane = NumElems / NumLanes;
10317 // Blend for v16i16 should be symetric for the both lanes.
10318 for (unsigned i = 0; i < NumElemsInLane; ++i) {
10319 SDValue EltCond = BuildVector->getOperand(i);
10320 SDValue SndLaneEltCond =
10321 (NumLanes == 2) ? BuildVector->getOperand(i + NumElemsInLane) : EltCond;
10323 int Lane1Cond = -1, Lane2Cond = -1;
10324 if (isa<ConstantSDNode>(EltCond))
10325 Lane1Cond = !isZero(EltCond);
10326 if (isa<ConstantSDNode>(SndLaneEltCond))
10327 Lane2Cond = !isZero(SndLaneEltCond);
10329 if (Lane1Cond == Lane2Cond || Lane2Cond < 0)
10330 // Lane1Cond != 0, means we want the first argument.
10331 // Lane1Cond == 0, means we want the second argument.
10332 // The encoding of this argument is 0 for the first argument, 1
10333 // for the second. Therefore, invert the condition.
10334 MaskValue |= !Lane1Cond << i;
10335 else if (Lane1Cond < 0)
10336 MaskValue |= !Lane2Cond << i;
10343 // Try to lower a vselect node into a simple blend instruction.
10344 static SDValue LowerVSELECTtoBlend(SDValue Op, const X86Subtarget *Subtarget,
10345 SelectionDAG &DAG) {
10346 SDValue Cond = Op.getOperand(0);
10347 SDValue LHS = Op.getOperand(1);
10348 SDValue RHS = Op.getOperand(2);
10350 MVT VT = Op.getSimpleValueType();
10351 MVT EltVT = VT.getVectorElementType();
10352 unsigned NumElems = VT.getVectorNumElements();
10354 // There is no blend with immediate in AVX-512.
10355 if (VT.is512BitVector())
10358 if (!Subtarget->hasSSE41() || EltVT == MVT::i8)
10360 if (!Subtarget->hasInt256() && VT == MVT::v16i16)
10363 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
10366 // Check the mask for BLEND and build the value.
10367 unsigned MaskValue = 0;
10368 if (!BUILD_VECTORtoBlendMask(cast<BuildVectorSDNode>(Cond), MaskValue))
10371 // Convert i32 vectors to floating point if it is not AVX2.
10372 // AVX2 introduced VPBLENDD instruction for 128 and 256-bit vectors.
10374 if (EltVT == MVT::i64 || (EltVT == MVT::i32 && !Subtarget->hasInt256())) {
10375 BlendVT = MVT::getVectorVT(MVT::getFloatingPointVT(EltVT.getSizeInBits()),
10377 LHS = DAG.getNode(ISD::BITCAST, dl, VT, LHS);
10378 RHS = DAG.getNode(ISD::BITCAST, dl, VT, RHS);
10381 SDValue Ret = DAG.getNode(X86ISD::BLENDI, dl, BlendVT, LHS, RHS,
10382 DAG.getConstant(MaskValue, MVT::i32));
10383 return DAG.getNode(ISD::BITCAST, dl, VT, Ret);
10386 SDValue X86TargetLowering::LowerVSELECT(SDValue Op, SelectionDAG &DAG) const {
10387 SDValue BlendOp = LowerVSELECTtoBlend(Op, Subtarget, DAG);
10388 if (BlendOp.getNode())
10391 // Some types for vselect were previously set to Expand, not Legal or
10392 // Custom. Return an empty SDValue so we fall-through to Expand, after
10393 // the Custom lowering phase.
10394 MVT VT = Op.getSimpleValueType();
10395 switch (VT.SimpleTy) {
10403 // We couldn't create a "Blend with immediate" node.
10404 // This node should still be legal, but we'll have to emit a blendv*
10409 static SDValue LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) {
10410 MVT VT = Op.getSimpleValueType();
10413 if (!Op.getOperand(0).getSimpleValueType().is128BitVector())
10416 if (VT.getSizeInBits() == 8) {
10417 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
10418 Op.getOperand(0), Op.getOperand(1));
10419 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
10420 DAG.getValueType(VT));
10421 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
10424 if (VT.getSizeInBits() == 16) {
10425 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
10426 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
10428 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
10429 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
10430 DAG.getNode(ISD::BITCAST, dl,
10433 Op.getOperand(1)));
10434 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
10435 Op.getOperand(0), Op.getOperand(1));
10436 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
10437 DAG.getValueType(VT));
10438 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
10441 if (VT == MVT::f32) {
10442 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
10443 // the result back to FR32 register. It's only worth matching if the
10444 // result has a single use which is a store or a bitcast to i32. And in
10445 // the case of a store, it's not worth it if the index is a constant 0,
10446 // because a MOVSSmr can be used instead, which is smaller and faster.
10447 if (!Op.hasOneUse())
10449 SDNode *User = *Op.getNode()->use_begin();
10450 if ((User->getOpcode() != ISD::STORE ||
10451 (isa<ConstantSDNode>(Op.getOperand(1)) &&
10452 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
10453 (User->getOpcode() != ISD::BITCAST ||
10454 User->getValueType(0) != MVT::i32))
10456 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
10457 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32,
10460 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, Extract);
10463 if (VT == MVT::i32 || VT == MVT::i64) {
10464 // ExtractPS/pextrq works with constant index.
10465 if (isa<ConstantSDNode>(Op.getOperand(1)))
10471 /// Extract one bit from mask vector, like v16i1 or v8i1.
10472 /// AVX-512 feature.
10474 X86TargetLowering::ExtractBitFromMaskVector(SDValue Op, SelectionDAG &DAG) const {
10475 SDValue Vec = Op.getOperand(0);
10477 MVT VecVT = Vec.getSimpleValueType();
10478 SDValue Idx = Op.getOperand(1);
10479 MVT EltVT = Op.getSimpleValueType();
10481 assert((EltVT == MVT::i1) && "Unexpected operands in ExtractBitFromMaskVector");
10483 // variable index can't be handled in mask registers,
10484 // extend vector to VR512
10485 if (!isa<ConstantSDNode>(Idx)) {
10486 MVT ExtVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
10487 SDValue Ext = DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVT, Vec);
10488 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
10489 ExtVT.getVectorElementType(), Ext, Idx);
10490 return DAG.getNode(ISD::TRUNCATE, dl, EltVT, Elt);
10493 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
10494 const TargetRegisterClass* rc = getRegClassFor(VecVT);
10495 unsigned MaxSift = rc->getSize()*8 - 1;
10496 Vec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, Vec,
10497 DAG.getConstant(MaxSift - IdxVal, MVT::i8));
10498 Vec = DAG.getNode(X86ISD::VSRLI, dl, VecVT, Vec,
10499 DAG.getConstant(MaxSift, MVT::i8));
10500 return DAG.getNode(X86ISD::VEXTRACT, dl, MVT::i1, Vec,
10501 DAG.getIntPtrConstant(0));
10505 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
10506 SelectionDAG &DAG) const {
10508 SDValue Vec = Op.getOperand(0);
10509 MVT VecVT = Vec.getSimpleValueType();
10510 SDValue Idx = Op.getOperand(1);
10512 if (Op.getSimpleValueType() == MVT::i1)
10513 return ExtractBitFromMaskVector(Op, DAG);
10515 if (!isa<ConstantSDNode>(Idx)) {
10516 if (VecVT.is512BitVector() ||
10517 (VecVT.is256BitVector() && Subtarget->hasInt256() &&
10518 VecVT.getVectorElementType().getSizeInBits() == 32)) {
10521 MVT::getIntegerVT(VecVT.getVectorElementType().getSizeInBits());
10522 MVT MaskVT = MVT::getVectorVT(MaskEltVT, VecVT.getSizeInBits() /
10523 MaskEltVT.getSizeInBits());
10525 Idx = DAG.getZExtOrTrunc(Idx, dl, MaskEltVT);
10526 SDValue Mask = DAG.getNode(X86ISD::VINSERT, dl, MaskVT,
10527 getZeroVector(MaskVT, Subtarget, DAG, dl),
10528 Idx, DAG.getConstant(0, getPointerTy()));
10529 SDValue Perm = DAG.getNode(X86ISD::VPERMV, dl, VecVT, Mask, Vec);
10530 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(),
10531 Perm, DAG.getConstant(0, getPointerTy()));
10536 // If this is a 256-bit vector result, first extract the 128-bit vector and
10537 // then extract the element from the 128-bit vector.
10538 if (VecVT.is256BitVector() || VecVT.is512BitVector()) {
10540 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
10541 // Get the 128-bit vector.
10542 Vec = Extract128BitVector(Vec, IdxVal, DAG, dl);
10543 MVT EltVT = VecVT.getVectorElementType();
10545 unsigned ElemsPerChunk = 128 / EltVT.getSizeInBits();
10547 //if (IdxVal >= NumElems/2)
10548 // IdxVal -= NumElems/2;
10549 IdxVal -= (IdxVal/ElemsPerChunk)*ElemsPerChunk;
10550 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec,
10551 DAG.getConstant(IdxVal, MVT::i32));
10554 assert(VecVT.is128BitVector() && "Unexpected vector length");
10556 if (Subtarget->hasSSE41()) {
10557 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG);
10562 MVT VT = Op.getSimpleValueType();
10563 // TODO: handle v16i8.
10564 if (VT.getSizeInBits() == 16) {
10565 SDValue Vec = Op.getOperand(0);
10566 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
10568 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
10569 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
10570 DAG.getNode(ISD::BITCAST, dl,
10572 Op.getOperand(1)));
10573 // Transform it so it match pextrw which produces a 32-bit result.
10574 MVT EltVT = MVT::i32;
10575 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
10576 Op.getOperand(0), Op.getOperand(1));
10577 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
10578 DAG.getValueType(VT));
10579 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
10582 if (VT.getSizeInBits() == 32) {
10583 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
10587 // SHUFPS the element to the lowest double word, then movss.
10588 int Mask[4] = { static_cast<int>(Idx), -1, -1, -1 };
10589 MVT VVT = Op.getOperand(0).getSimpleValueType();
10590 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
10591 DAG.getUNDEF(VVT), Mask);
10592 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
10593 DAG.getIntPtrConstant(0));
10596 if (VT.getSizeInBits() == 64) {
10597 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
10598 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
10599 // to match extract_elt for f64.
10600 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
10604 // UNPCKHPD the element to the lowest double word, then movsd.
10605 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
10606 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
10607 int Mask[2] = { 1, -1 };
10608 MVT VVT = Op.getOperand(0).getSimpleValueType();
10609 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
10610 DAG.getUNDEF(VVT), Mask);
10611 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
10612 DAG.getIntPtrConstant(0));
10618 static SDValue LowerINSERT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) {
10619 MVT VT = Op.getSimpleValueType();
10620 MVT EltVT = VT.getVectorElementType();
10623 SDValue N0 = Op.getOperand(0);
10624 SDValue N1 = Op.getOperand(1);
10625 SDValue N2 = Op.getOperand(2);
10627 if (!VT.is128BitVector())
10630 if ((EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) &&
10631 isa<ConstantSDNode>(N2)) {
10633 if (VT == MVT::v8i16)
10634 Opc = X86ISD::PINSRW;
10635 else if (VT == MVT::v16i8)
10636 Opc = X86ISD::PINSRB;
10638 Opc = X86ISD::PINSRB;
10640 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
10642 if (N1.getValueType() != MVT::i32)
10643 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
10644 if (N2.getValueType() != MVT::i32)
10645 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
10646 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
10649 if (EltVT == MVT::f32 && isa<ConstantSDNode>(N2)) {
10650 // Bits [7:6] of the constant are the source select. This will always be
10651 // zero here. The DAG Combiner may combine an extract_elt index into these
10652 // bits. For example (insert (extract, 3), 2) could be matched by putting
10653 // the '3' into bits [7:6] of X86ISD::INSERTPS.
10654 // Bits [5:4] of the constant are the destination select. This is the
10655 // value of the incoming immediate.
10656 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
10657 // combine either bitwise AND or insert of float 0.0 to set these bits.
10658 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue() << 4);
10659 // Create this as a scalar to vector..
10660 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
10661 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
10664 if ((EltVT == MVT::i32 || EltVT == MVT::i64) && isa<ConstantSDNode>(N2)) {
10665 // PINSR* works with constant index.
10671 /// Insert one bit to mask vector, like v16i1 or v8i1.
10672 /// AVX-512 feature.
10674 X86TargetLowering::InsertBitToMaskVector(SDValue Op, SelectionDAG &DAG) const {
10676 SDValue Vec = Op.getOperand(0);
10677 SDValue Elt = Op.getOperand(1);
10678 SDValue Idx = Op.getOperand(2);
10679 MVT VecVT = Vec.getSimpleValueType();
10681 if (!isa<ConstantSDNode>(Idx)) {
10682 // Non constant index. Extend source and destination,
10683 // insert element and then truncate the result.
10684 MVT ExtVecVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
10685 MVT ExtEltVT = (VecVT == MVT::v8i1 ? MVT::i64 : MVT::i32);
10686 SDValue ExtOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ExtVecVT,
10687 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVecVT, Vec),
10688 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtEltVT, Elt), Idx);
10689 return DAG.getNode(ISD::TRUNCATE, dl, VecVT, ExtOp);
10692 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
10693 SDValue EltInVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Elt);
10694 if (Vec.getOpcode() == ISD::UNDEF)
10695 return DAG.getNode(X86ISD::VSHLI, dl, VecVT, EltInVec,
10696 DAG.getConstant(IdxVal, MVT::i8));
10697 const TargetRegisterClass* rc = getRegClassFor(VecVT);
10698 unsigned MaxSift = rc->getSize()*8 - 1;
10699 EltInVec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, EltInVec,
10700 DAG.getConstant(MaxSift, MVT::i8));
10701 EltInVec = DAG.getNode(X86ISD::VSRLI, dl, VecVT, EltInVec,
10702 DAG.getConstant(MaxSift - IdxVal, MVT::i8));
10703 return DAG.getNode(ISD::OR, dl, VecVT, Vec, EltInVec);
10706 X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const {
10707 MVT VT = Op.getSimpleValueType();
10708 MVT EltVT = VT.getVectorElementType();
10710 if (EltVT == MVT::i1)
10711 return InsertBitToMaskVector(Op, DAG);
10714 SDValue N0 = Op.getOperand(0);
10715 SDValue N1 = Op.getOperand(1);
10716 SDValue N2 = Op.getOperand(2);
10718 // If this is a 256-bit vector result, first extract the 128-bit vector,
10719 // insert the element into the extracted half and then place it back.
10720 if (VT.is256BitVector() || VT.is512BitVector()) {
10721 if (!isa<ConstantSDNode>(N2))
10724 // Get the desired 128-bit vector half.
10725 unsigned IdxVal = cast<ConstantSDNode>(N2)->getZExtValue();
10726 SDValue V = Extract128BitVector(N0, IdxVal, DAG, dl);
10728 // Insert the element into the desired half.
10729 unsigned NumEltsIn128 = 128/EltVT.getSizeInBits();
10730 unsigned IdxIn128 = IdxVal - (IdxVal/NumEltsIn128) * NumEltsIn128;
10732 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V, N1,
10733 DAG.getConstant(IdxIn128, MVT::i32));
10735 // Insert the changed part back to the 256-bit vector
10736 return Insert128BitVector(N0, V, IdxVal, DAG, dl);
10739 if (Subtarget->hasSSE41())
10740 return LowerINSERT_VECTOR_ELT_SSE4(Op, DAG);
10742 if (EltVT == MVT::i8)
10745 if (EltVT.getSizeInBits() == 16 && isa<ConstantSDNode>(N2)) {
10746 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
10747 // as its second argument.
10748 if (N1.getValueType() != MVT::i32)
10749 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
10750 if (N2.getValueType() != MVT::i32)
10751 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
10752 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);
10757 static SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) {
10759 MVT OpVT = Op.getSimpleValueType();
10761 // If this is a 256-bit vector result, first insert into a 128-bit
10762 // vector and then insert into the 256-bit vector.
10763 if (!OpVT.is128BitVector()) {
10764 // Insert into a 128-bit vector.
10765 unsigned SizeFactor = OpVT.getSizeInBits()/128;
10766 MVT VT128 = MVT::getVectorVT(OpVT.getVectorElementType(),
10767 OpVT.getVectorNumElements() / SizeFactor);
10769 Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Op.getOperand(0));
10771 // Insert the 128-bit vector.
10772 return Insert128BitVector(DAG.getUNDEF(OpVT), Op, 0, DAG, dl);
10775 if (OpVT == MVT::v1i64 &&
10776 Op.getOperand(0).getValueType() == MVT::i64)
10777 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
10779 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
10780 assert(OpVT.is128BitVector() && "Expected an SSE type!");
10781 return DAG.getNode(ISD::BITCAST, dl, OpVT,
10782 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,AnyExt));
10785 // Lower a node with an EXTRACT_SUBVECTOR opcode. This may result in
10786 // a simple subregister reference or explicit instructions to grab
10787 // upper bits of a vector.
10788 static SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
10789 SelectionDAG &DAG) {
10791 SDValue In = Op.getOperand(0);
10792 SDValue Idx = Op.getOperand(1);
10793 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
10794 MVT ResVT = Op.getSimpleValueType();
10795 MVT InVT = In.getSimpleValueType();
10797 if (Subtarget->hasFp256()) {
10798 if (ResVT.is128BitVector() &&
10799 (InVT.is256BitVector() || InVT.is512BitVector()) &&
10800 isa<ConstantSDNode>(Idx)) {
10801 return Extract128BitVector(In, IdxVal, DAG, dl);
10803 if (ResVT.is256BitVector() && InVT.is512BitVector() &&
10804 isa<ConstantSDNode>(Idx)) {
10805 return Extract256BitVector(In, IdxVal, DAG, dl);
10811 // Lower a node with an INSERT_SUBVECTOR opcode. This may result in a
10812 // simple superregister reference or explicit instructions to insert
10813 // the upper bits of a vector.
10814 static SDValue LowerINSERT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
10815 SelectionDAG &DAG) {
10816 if (Subtarget->hasFp256()) {
10817 SDLoc dl(Op.getNode());
10818 SDValue Vec = Op.getNode()->getOperand(0);
10819 SDValue SubVec = Op.getNode()->getOperand(1);
10820 SDValue Idx = Op.getNode()->getOperand(2);
10822 if ((Op.getNode()->getSimpleValueType(0).is256BitVector() ||
10823 Op.getNode()->getSimpleValueType(0).is512BitVector()) &&
10824 SubVec.getNode()->getSimpleValueType(0).is128BitVector() &&
10825 isa<ConstantSDNode>(Idx)) {
10826 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
10827 return Insert128BitVector(Vec, SubVec, IdxVal, DAG, dl);
10830 if (Op.getNode()->getSimpleValueType(0).is512BitVector() &&
10831 SubVec.getNode()->getSimpleValueType(0).is256BitVector() &&
10832 isa<ConstantSDNode>(Idx)) {
10833 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
10834 return Insert256BitVector(Vec, SubVec, IdxVal, DAG, dl);
10840 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
10841 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
10842 // one of the above mentioned nodes. It has to be wrapped because otherwise
10843 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
10844 // be used to form addressing mode. These wrapped nodes will be selected
10847 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
10848 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
10850 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
10851 // global base reg.
10852 unsigned char OpFlag = 0;
10853 unsigned WrapperKind = X86ISD::Wrapper;
10854 CodeModel::Model M = DAG.getTarget().getCodeModel();
10856 if (Subtarget->isPICStyleRIPRel() &&
10857 (M == CodeModel::Small || M == CodeModel::Kernel))
10858 WrapperKind = X86ISD::WrapperRIP;
10859 else if (Subtarget->isPICStyleGOT())
10860 OpFlag = X86II::MO_GOTOFF;
10861 else if (Subtarget->isPICStyleStubPIC())
10862 OpFlag = X86II::MO_PIC_BASE_OFFSET;
10864 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(),
10865 CP->getAlignment(),
10866 CP->getOffset(), OpFlag);
10868 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
10869 // With PIC, the address is actually $g + Offset.
10871 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
10872 DAG.getNode(X86ISD::GlobalBaseReg,
10873 SDLoc(), getPointerTy()),
10880 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
10881 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
10883 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
10884 // global base reg.
10885 unsigned char OpFlag = 0;
10886 unsigned WrapperKind = X86ISD::Wrapper;
10887 CodeModel::Model M = DAG.getTarget().getCodeModel();
10889 if (Subtarget->isPICStyleRIPRel() &&
10890 (M == CodeModel::Small || M == CodeModel::Kernel))
10891 WrapperKind = X86ISD::WrapperRIP;
10892 else if (Subtarget->isPICStyleGOT())
10893 OpFlag = X86II::MO_GOTOFF;
10894 else if (Subtarget->isPICStyleStubPIC())
10895 OpFlag = X86II::MO_PIC_BASE_OFFSET;
10897 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(),
10900 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
10902 // With PIC, the address is actually $g + Offset.
10904 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
10905 DAG.getNode(X86ISD::GlobalBaseReg,
10906 SDLoc(), getPointerTy()),
10913 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const {
10914 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
10916 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
10917 // global base reg.
10918 unsigned char OpFlag = 0;
10919 unsigned WrapperKind = X86ISD::Wrapper;
10920 CodeModel::Model M = DAG.getTarget().getCodeModel();
10922 if (Subtarget->isPICStyleRIPRel() &&
10923 (M == CodeModel::Small || M == CodeModel::Kernel)) {
10924 if (Subtarget->isTargetDarwin() || Subtarget->isTargetELF())
10925 OpFlag = X86II::MO_GOTPCREL;
10926 WrapperKind = X86ISD::WrapperRIP;
10927 } else if (Subtarget->isPICStyleGOT()) {
10928 OpFlag = X86II::MO_GOT;
10929 } else if (Subtarget->isPICStyleStubPIC()) {
10930 OpFlag = X86II::MO_DARWIN_NONLAZY_PIC_BASE;
10931 } else if (Subtarget->isPICStyleStubNoDynamic()) {
10932 OpFlag = X86II::MO_DARWIN_NONLAZY;
10935 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag);
10938 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
10940 // With PIC, the address is actually $g + Offset.
10941 if (DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
10942 !Subtarget->is64Bit()) {
10943 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
10944 DAG.getNode(X86ISD::GlobalBaseReg,
10945 SDLoc(), getPointerTy()),
10949 // For symbols that require a load from a stub to get the address, emit the
10951 if (isGlobalStubReference(OpFlag))
10952 Result = DAG.getLoad(getPointerTy(), DL, DAG.getEntryNode(), Result,
10953 MachinePointerInfo::getGOT(), false, false, false, 0);
10959 X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
10960 // Create the TargetBlockAddressAddress node.
10961 unsigned char OpFlags =
10962 Subtarget->ClassifyBlockAddressReference();
10963 CodeModel::Model M = DAG.getTarget().getCodeModel();
10964 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
10965 int64_t Offset = cast<BlockAddressSDNode>(Op)->getOffset();
10967 SDValue Result = DAG.getTargetBlockAddress(BA, getPointerTy(), Offset,
10970 if (Subtarget->isPICStyleRIPRel() &&
10971 (M == CodeModel::Small || M == CodeModel::Kernel))
10972 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
10974 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
10976 // With PIC, the address is actually $g + Offset.
10977 if (isGlobalRelativeToPICBase(OpFlags)) {
10978 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
10979 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
10987 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, SDLoc dl,
10988 int64_t Offset, SelectionDAG &DAG) const {
10989 // Create the TargetGlobalAddress node, folding in the constant
10990 // offset if it is legal.
10991 unsigned char OpFlags =
10992 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget());
10993 CodeModel::Model M = DAG.getTarget().getCodeModel();
10995 if (OpFlags == X86II::MO_NO_FLAG &&
10996 X86::isOffsetSuitableForCodeModel(Offset, M)) {
10997 // A direct static reference to a global.
10998 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), Offset);
11001 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags);
11004 if (Subtarget->isPICStyleRIPRel() &&
11005 (M == CodeModel::Small || M == CodeModel::Kernel))
11006 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
11008 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
11010 // With PIC, the address is actually $g + Offset.
11011 if (isGlobalRelativeToPICBase(OpFlags)) {
11012 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
11013 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
11017 // For globals that require a load from a stub to get the address, emit the
11019 if (isGlobalStubReference(OpFlags))
11020 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result,
11021 MachinePointerInfo::getGOT(), false, false, false, 0);
11023 // If there was a non-zero offset that we didn't fold, create an explicit
11024 // addition for it.
11026 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result,
11027 DAG.getConstant(Offset, getPointerTy()));
11033 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
11034 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
11035 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
11036 return LowerGlobalAddress(GV, SDLoc(Op), Offset, DAG);
11040 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
11041 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg,
11042 unsigned char OperandFlags, bool LocalDynamic = false) {
11043 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
11044 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
11046 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
11047 GA->getValueType(0),
11051 X86ISD::NodeType CallType = LocalDynamic ? X86ISD::TLSBASEADDR
11055 SDValue Ops[] = { Chain, TGA, *InFlag };
11056 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
11058 SDValue Ops[] = { Chain, TGA };
11059 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
11062 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
11063 MFI->setAdjustsStack(true);
11065 SDValue Flag = Chain.getValue(1);
11066 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
11069 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
11071 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
11074 SDLoc dl(GA); // ? function entry point might be better
11075 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
11076 DAG.getNode(X86ISD::GlobalBaseReg,
11077 SDLoc(), PtrVT), InFlag);
11078 InFlag = Chain.getValue(1);
11080 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
11083 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
11085 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
11087 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT,
11088 X86::RAX, X86II::MO_TLSGD);
11091 static SDValue LowerToTLSLocalDynamicModel(GlobalAddressSDNode *GA,
11097 // Get the start address of the TLS block for this module.
11098 X86MachineFunctionInfo* MFI = DAG.getMachineFunction()
11099 .getInfo<X86MachineFunctionInfo>();
11100 MFI->incNumLocalDynamicTLSAccesses();
11104 Base = GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT, X86::RAX,
11105 X86II::MO_TLSLD, /*LocalDynamic=*/true);
11108 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
11109 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), InFlag);
11110 InFlag = Chain.getValue(1);
11111 Base = GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX,
11112 X86II::MO_TLSLDM, /*LocalDynamic=*/true);
11115 // Note: the CleanupLocalDynamicTLSPass will remove redundant computations
11119 unsigned char OperandFlags = X86II::MO_DTPOFF;
11120 unsigned WrapperKind = X86ISD::Wrapper;
11121 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
11122 GA->getValueType(0),
11123 GA->getOffset(), OperandFlags);
11124 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
11126 // Add x@dtpoff with the base.
11127 return DAG.getNode(ISD::ADD, dl, PtrVT, Offset, Base);
11130 // Lower ISD::GlobalTLSAddress using the "initial exec" or "local exec" model.
11131 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
11132 const EVT PtrVT, TLSModel::Model model,
11133 bool is64Bit, bool isPIC) {
11136 // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit).
11137 Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(*DAG.getContext(),
11138 is64Bit ? 257 : 256));
11140 SDValue ThreadPointer =
11141 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), DAG.getIntPtrConstant(0),
11142 MachinePointerInfo(Ptr), false, false, false, 0);
11144 unsigned char OperandFlags = 0;
11145 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
11147 unsigned WrapperKind = X86ISD::Wrapper;
11148 if (model == TLSModel::LocalExec) {
11149 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
11150 } else if (model == TLSModel::InitialExec) {
11152 OperandFlags = X86II::MO_GOTTPOFF;
11153 WrapperKind = X86ISD::WrapperRIP;
11155 OperandFlags = isPIC ? X86II::MO_GOTNTPOFF : X86II::MO_INDNTPOFF;
11158 llvm_unreachable("Unexpected model");
11161 // emit "addl x@ntpoff,%eax" (local exec)
11162 // or "addl x@indntpoff,%eax" (initial exec)
11163 // or "addl x@gotntpoff(%ebx) ,%eax" (initial exec, 32-bit pic)
11165 DAG.getTargetGlobalAddress(GA->getGlobal(), dl, GA->getValueType(0),
11166 GA->getOffset(), OperandFlags);
11167 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
11169 if (model == TLSModel::InitialExec) {
11170 if (isPIC && !is64Bit) {
11171 Offset = DAG.getNode(ISD::ADD, dl, PtrVT,
11172 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT),
11176 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
11177 MachinePointerInfo::getGOT(), false, false, false, 0);
11180 // The address of the thread local variable is the add of the thread
11181 // pointer with the offset of the variable.
11182 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
11186 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
11188 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
11189 const GlobalValue *GV = GA->getGlobal();
11191 if (Subtarget->isTargetELF()) {
11192 TLSModel::Model model = DAG.getTarget().getTLSModel(GV);
11195 case TLSModel::GeneralDynamic:
11196 if (Subtarget->is64Bit())
11197 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy());
11198 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy());
11199 case TLSModel::LocalDynamic:
11200 return LowerToTLSLocalDynamicModel(GA, DAG, getPointerTy(),
11201 Subtarget->is64Bit());
11202 case TLSModel::InitialExec:
11203 case TLSModel::LocalExec:
11204 return LowerToTLSExecModel(
11205 GA, DAG, getPointerTy(), model, Subtarget->is64Bit(),
11206 DAG.getTarget().getRelocationModel() == Reloc::PIC_);
11208 llvm_unreachable("Unknown TLS model.");
11211 if (Subtarget->isTargetDarwin()) {
11212 // Darwin only has one model of TLS. Lower to that.
11213 unsigned char OpFlag = 0;
11214 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ?
11215 X86ISD::WrapperRIP : X86ISD::Wrapper;
11217 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
11218 // global base reg.
11219 bool PIC32 = (DAG.getTarget().getRelocationModel() == Reloc::PIC_) &&
11220 !Subtarget->is64Bit();
11222 OpFlag = X86II::MO_TLVP_PIC_BASE;
11224 OpFlag = X86II::MO_TLVP;
11226 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL,
11227 GA->getValueType(0),
11228 GA->getOffset(), OpFlag);
11229 SDValue Offset = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
11231 // With PIC32, the address is actually $g + Offset.
11233 Offset = DAG.getNode(ISD::ADD, DL, getPointerTy(),
11234 DAG.getNode(X86ISD::GlobalBaseReg,
11235 SDLoc(), getPointerTy()),
11238 // Lowering the machine isd will make sure everything is in the right
11240 SDValue Chain = DAG.getEntryNode();
11241 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
11242 SDValue Args[] = { Chain, Offset };
11243 Chain = DAG.getNode(X86ISD::TLSCALL, DL, NodeTys, Args);
11245 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls.
11246 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
11247 MFI->setAdjustsStack(true);
11249 // And our return value (tls address) is in the standard call return value
11251 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
11252 return DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(),
11253 Chain.getValue(1));
11256 if (Subtarget->isTargetKnownWindowsMSVC() ||
11257 Subtarget->isTargetWindowsGNU()) {
11258 // Just use the implicit TLS architecture
11259 // Need to generate someting similar to:
11260 // mov rdx, qword [gs:abs 58H]; Load pointer to ThreadLocalStorage
11262 // mov ecx, dword [rel _tls_index]: Load index (from C runtime)
11263 // mov rcx, qword [rdx+rcx*8]
11264 // mov eax, .tls$:tlsvar
11265 // [rax+rcx] contains the address
11266 // Windows 64bit: gs:0x58
11267 // Windows 32bit: fs:__tls_array
11270 SDValue Chain = DAG.getEntryNode();
11272 // Get the Thread Pointer, which is %fs:__tls_array (32-bit) or
11273 // %gs:0x58 (64-bit). On MinGW, __tls_array is not available, so directly
11274 // use its literal value of 0x2C.
11275 Value *Ptr = Constant::getNullValue(Subtarget->is64Bit()
11276 ? Type::getInt8PtrTy(*DAG.getContext(),
11278 : Type::getInt32PtrTy(*DAG.getContext(),
11282 Subtarget->is64Bit()
11283 ? DAG.getIntPtrConstant(0x58)
11284 : (Subtarget->isTargetWindowsGNU()
11285 ? DAG.getIntPtrConstant(0x2C)
11286 : DAG.getExternalSymbol("_tls_array", getPointerTy()));
11288 SDValue ThreadPointer =
11289 DAG.getLoad(getPointerTy(), dl, Chain, TlsArray,
11290 MachinePointerInfo(Ptr), false, false, false, 0);
11292 // Load the _tls_index variable
11293 SDValue IDX = DAG.getExternalSymbol("_tls_index", getPointerTy());
11294 if (Subtarget->is64Bit())
11295 IDX = DAG.getExtLoad(ISD::ZEXTLOAD, dl, getPointerTy(), Chain,
11296 IDX, MachinePointerInfo(), MVT::i32,
11297 false, false, false, 0);
11299 IDX = DAG.getLoad(getPointerTy(), dl, Chain, IDX, MachinePointerInfo(),
11300 false, false, false, 0);
11302 SDValue Scale = DAG.getConstant(Log2_64_Ceil(TD->getPointerSize()),
11304 IDX = DAG.getNode(ISD::SHL, dl, getPointerTy(), IDX, Scale);
11306 SDValue res = DAG.getNode(ISD::ADD, dl, getPointerTy(), ThreadPointer, IDX);
11307 res = DAG.getLoad(getPointerTy(), dl, Chain, res, MachinePointerInfo(),
11308 false, false, false, 0);
11310 // Get the offset of start of .tls section
11311 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
11312 GA->getValueType(0),
11313 GA->getOffset(), X86II::MO_SECREL);
11314 SDValue Offset = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), TGA);
11316 // The address of the thread local variable is the add of the thread
11317 // pointer with the offset of the variable.
11318 return DAG.getNode(ISD::ADD, dl, getPointerTy(), res, Offset);
11321 llvm_unreachable("TLS not implemented for this target.");
11324 /// LowerShiftParts - Lower SRA_PARTS and friends, which return two i32 values
11325 /// and take a 2 x i32 value to shift plus a shift amount.
11326 static SDValue LowerShiftParts(SDValue Op, SelectionDAG &DAG) {
11327 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
11328 MVT VT = Op.getSimpleValueType();
11329 unsigned VTBits = VT.getSizeInBits();
11331 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
11332 SDValue ShOpLo = Op.getOperand(0);
11333 SDValue ShOpHi = Op.getOperand(1);
11334 SDValue ShAmt = Op.getOperand(2);
11335 // X86ISD::SHLD and X86ISD::SHRD have defined overflow behavior but the
11336 // generic ISD nodes haven't. Insert an AND to be safe, it's optimized away
11338 SDValue SafeShAmt = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
11339 DAG.getConstant(VTBits - 1, MVT::i8));
11340 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
11341 DAG.getConstant(VTBits - 1, MVT::i8))
11342 : DAG.getConstant(0, VT);
11344 SDValue Tmp2, Tmp3;
11345 if (Op.getOpcode() == ISD::SHL_PARTS) {
11346 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
11347 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, SafeShAmt);
11349 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
11350 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, SafeShAmt);
11353 // If the shift amount is larger or equal than the width of a part we can't
11354 // rely on the results of shld/shrd. Insert a test and select the appropriate
11355 // values for large shift amounts.
11356 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
11357 DAG.getConstant(VTBits, MVT::i8));
11358 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
11359 AndNode, DAG.getConstant(0, MVT::i8));
11362 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8);
11363 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
11364 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
11366 if (Op.getOpcode() == ISD::SHL_PARTS) {
11367 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
11368 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
11370 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
11371 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
11374 SDValue Ops[2] = { Lo, Hi };
11375 return DAG.getMergeValues(Ops, dl);
11378 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op,
11379 SelectionDAG &DAG) const {
11380 MVT SrcVT = Op.getOperand(0).getSimpleValueType();
11382 if (SrcVT.isVector())
11385 assert(SrcVT <= MVT::i64 && SrcVT >= MVT::i16 &&
11386 "Unknown SINT_TO_FP to lower!");
11388 // These are really Legal; return the operand so the caller accepts it as
11390 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
11392 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
11393 Subtarget->is64Bit()) {
11398 unsigned Size = SrcVT.getSizeInBits()/8;
11399 MachineFunction &MF = DAG.getMachineFunction();
11400 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false);
11401 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
11402 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
11404 MachinePointerInfo::getFixedStack(SSFI),
11406 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
11409 SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
11411 SelectionDAG &DAG) const {
11415 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
11417 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Glue);
11419 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
11421 unsigned ByteSize = SrcVT.getSizeInBits()/8;
11423 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(StackSlot);
11424 MachineMemOperand *MMO;
11426 int SSFI = FI->getIndex();
11428 DAG.getMachineFunction()
11429 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
11430 MachineMemOperand::MOLoad, ByteSize, ByteSize);
11432 MMO = cast<LoadSDNode>(StackSlot)->getMemOperand();
11433 StackSlot = StackSlot.getOperand(1);
11435 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) };
11436 SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG :
11438 Tys, Ops, SrcVT, MMO);
11441 Chain = Result.getValue(1);
11442 SDValue InFlag = Result.getValue(2);
11444 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
11445 // shouldn't be necessary except that RFP cannot be live across
11446 // multiple blocks. When stackifier is fixed, they can be uncoupled.
11447 MachineFunction &MF = DAG.getMachineFunction();
11448 unsigned SSFISize = Op.getValueType().getSizeInBits()/8;
11449 int SSFI = MF.getFrameInfo()->CreateStackObject(SSFISize, SSFISize, false);
11450 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
11451 Tys = DAG.getVTList(MVT::Other);
11453 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag
11455 MachineMemOperand *MMO =
11456 DAG.getMachineFunction()
11457 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
11458 MachineMemOperand::MOStore, SSFISize, SSFISize);
11460 Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys,
11461 Ops, Op.getValueType(), MMO);
11462 Result = DAG.getLoad(Op.getValueType(), DL, Chain, StackSlot,
11463 MachinePointerInfo::getFixedStack(SSFI),
11464 false, false, false, 0);
11470 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
11471 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op,
11472 SelectionDAG &DAG) const {
11473 // This algorithm is not obvious. Here it is what we're trying to output:
11476 punpckldq (c0), %xmm0 // c0: (uint4){ 0x43300000U, 0x45300000U, 0U, 0U }
11477 subpd (c1), %xmm0 // c1: (double2){ 0x1.0p52, 0x1.0p52 * 0x1.0p32 }
11479 haddpd %xmm0, %xmm0
11481 pshufd $0x4e, %xmm0, %xmm1
11487 LLVMContext *Context = DAG.getContext();
11489 // Build some magic constants.
11490 static const uint32_t CV0[] = { 0x43300000, 0x45300000, 0, 0 };
11491 Constant *C0 = ConstantDataVector::get(*Context, CV0);
11492 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16);
11494 SmallVector<Constant*,2> CV1;
11496 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
11497 APInt(64, 0x4330000000000000ULL))));
11499 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
11500 APInt(64, 0x4530000000000000ULL))));
11501 Constant *C1 = ConstantVector::get(CV1);
11502 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16);
11504 // Load the 64-bit value into an XMM register.
11505 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
11507 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
11508 MachinePointerInfo::getConstantPool(),
11509 false, false, false, 16);
11510 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32,
11511 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, XR1),
11514 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
11515 MachinePointerInfo::getConstantPool(),
11516 false, false, false, 16);
11517 SDValue XR2F = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Unpck1);
11518 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
11521 if (Subtarget->hasSSE3()) {
11522 // FIXME: The 'haddpd' instruction may be slower than 'movhlps + addsd'.
11523 Result = DAG.getNode(X86ISD::FHADD, dl, MVT::v2f64, Sub, Sub);
11525 SDValue S2F = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Sub);
11526 SDValue Shuffle = getTargetShuffleNode(X86ISD::PSHUFD, dl, MVT::v4i32,
11528 Result = DAG.getNode(ISD::FADD, dl, MVT::v2f64,
11529 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Shuffle),
11533 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Result,
11534 DAG.getIntPtrConstant(0));
11537 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
11538 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op,
11539 SelectionDAG &DAG) const {
11541 // FP constant to bias correct the final result.
11542 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
11545 // Load the 32-bit value into an XMM register.
11546 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
11549 // Zero out the upper parts of the register.
11550 Load = getShuffleVectorZeroOrUndef(Load, 0, true, Subtarget, DAG);
11552 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
11553 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Load),
11554 DAG.getIntPtrConstant(0));
11556 // Or the load with the bias.
11557 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64,
11558 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
11559 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
11560 MVT::v2f64, Load)),
11561 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
11562 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
11563 MVT::v2f64, Bias)));
11564 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
11565 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or),
11566 DAG.getIntPtrConstant(0));
11568 // Subtract the bias.
11569 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
11571 // Handle final rounding.
11572 EVT DestVT = Op.getValueType();
11574 if (DestVT.bitsLT(MVT::f64))
11575 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
11576 DAG.getIntPtrConstant(0));
11577 if (DestVT.bitsGT(MVT::f64))
11578 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
11580 // Handle final rounding.
11584 SDValue X86TargetLowering::lowerUINT_TO_FP_vec(SDValue Op,
11585 SelectionDAG &DAG) const {
11586 SDValue N0 = Op.getOperand(0);
11587 MVT SVT = N0.getSimpleValueType();
11590 assert((SVT == MVT::v4i8 || SVT == MVT::v4i16 ||
11591 SVT == MVT::v8i8 || SVT == MVT::v8i16) &&
11592 "Custom UINT_TO_FP is not supported!");
11594 MVT NVT = MVT::getVectorVT(MVT::i32, SVT.getVectorNumElements());
11595 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
11596 DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, N0));
11599 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op,
11600 SelectionDAG &DAG) const {
11601 SDValue N0 = Op.getOperand(0);
11604 if (Op.getValueType().isVector())
11605 return lowerUINT_TO_FP_vec(Op, DAG);
11607 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't
11608 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
11609 // the optimization here.
11610 if (DAG.SignBitIsZero(N0))
11611 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
11613 MVT SrcVT = N0.getSimpleValueType();
11614 MVT DstVT = Op.getSimpleValueType();
11615 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64)
11616 return LowerUINT_TO_FP_i64(Op, DAG);
11617 if (SrcVT == MVT::i32 && X86ScalarSSEf64)
11618 return LowerUINT_TO_FP_i32(Op, DAG);
11619 if (Subtarget->is64Bit() && SrcVT == MVT::i64 && DstVT == MVT::f32)
11622 // Make a 64-bit buffer, and use it to build an FILD.
11623 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
11624 if (SrcVT == MVT::i32) {
11625 SDValue WordOff = DAG.getConstant(4, getPointerTy());
11626 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl,
11627 getPointerTy(), StackSlot, WordOff);
11628 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
11629 StackSlot, MachinePointerInfo(),
11631 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32),
11632 OffsetSlot, MachinePointerInfo(),
11634 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
11638 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP");
11639 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
11640 StackSlot, MachinePointerInfo(),
11642 // For i64 source, we need to add the appropriate power of 2 if the input
11643 // was negative. This is the same as the optimization in
11644 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here,
11645 // we must be careful to do the computation in x87 extended precision, not
11646 // in SSE. (The generic code can't know it's OK to do this, or how to.)
11647 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex();
11648 MachineMemOperand *MMO =
11649 DAG.getMachineFunction()
11650 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
11651 MachineMemOperand::MOLoad, 8, 8);
11653 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other);
11654 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) };
11655 SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops,
11658 APInt FF(32, 0x5F800000ULL);
11660 // Check whether the sign bit is set.
11661 SDValue SignSet = DAG.getSetCC(dl,
11662 getSetCCResultType(*DAG.getContext(), MVT::i64),
11663 Op.getOperand(0), DAG.getConstant(0, MVT::i64),
11666 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
11667 SDValue FudgePtr = DAG.getConstantPool(
11668 ConstantInt::get(*DAG.getContext(), FF.zext(64)),
11671 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
11672 SDValue Zero = DAG.getIntPtrConstant(0);
11673 SDValue Four = DAG.getIntPtrConstant(4);
11674 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
11676 FudgePtr = DAG.getNode(ISD::ADD, dl, getPointerTy(), FudgePtr, Offset);
11678 // Load the value out, extending it from f32 to f80.
11679 // FIXME: Avoid the extend by constructing the right constant pool?
11680 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, MVT::f80, DAG.getEntryNode(),
11681 FudgePtr, MachinePointerInfo::getConstantPool(),
11682 MVT::f32, false, false, false, 4);
11683 // Extend everything to 80 bits to force it to be done on x87.
11684 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge);
11685 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add, DAG.getIntPtrConstant(0));
11688 std::pair<SDValue,SDValue>
11689 X86TargetLowering:: FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG,
11690 bool IsSigned, bool IsReplace) const {
11693 EVT DstTy = Op.getValueType();
11695 if (!IsSigned && !isIntegerTypeFTOL(DstTy)) {
11696 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
11700 assert(DstTy.getSimpleVT() <= MVT::i64 &&
11701 DstTy.getSimpleVT() >= MVT::i16 &&
11702 "Unknown FP_TO_INT to lower!");
11704 // These are really Legal.
11705 if (DstTy == MVT::i32 &&
11706 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
11707 return std::make_pair(SDValue(), SDValue());
11708 if (Subtarget->is64Bit() &&
11709 DstTy == MVT::i64 &&
11710 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
11711 return std::make_pair(SDValue(), SDValue());
11713 // We lower FP->int64 either into FISTP64 followed by a load from a temporary
11714 // stack slot, or into the FTOL runtime function.
11715 MachineFunction &MF = DAG.getMachineFunction();
11716 unsigned MemSize = DstTy.getSizeInBits()/8;
11717 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
11718 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
11721 if (!IsSigned && isIntegerTypeFTOL(DstTy))
11722 Opc = X86ISD::WIN_FTOL;
11724 switch (DstTy.getSimpleVT().SimpleTy) {
11725 default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
11726 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
11727 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
11728 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
11731 SDValue Chain = DAG.getEntryNode();
11732 SDValue Value = Op.getOperand(0);
11733 EVT TheVT = Op.getOperand(0).getValueType();
11734 // FIXME This causes a redundant load/store if the SSE-class value is already
11735 // in memory, such as if it is on the callstack.
11736 if (isScalarFPTypeInSSEReg(TheVT)) {
11737 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
11738 Chain = DAG.getStore(Chain, DL, Value, StackSlot,
11739 MachinePointerInfo::getFixedStack(SSFI),
11741 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
11743 Chain, StackSlot, DAG.getValueType(TheVT)
11746 MachineMemOperand *MMO =
11747 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
11748 MachineMemOperand::MOLoad, MemSize, MemSize);
11749 Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops, DstTy, MMO);
11750 Chain = Value.getValue(1);
11751 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
11752 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
11755 MachineMemOperand *MMO =
11756 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
11757 MachineMemOperand::MOStore, MemSize, MemSize);
11759 if (Opc != X86ISD::WIN_FTOL) {
11760 // Build the FP_TO_INT*_IN_MEM
11761 SDValue Ops[] = { Chain, Value, StackSlot };
11762 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
11764 return std::make_pair(FIST, StackSlot);
11766 SDValue ftol = DAG.getNode(X86ISD::WIN_FTOL, DL,
11767 DAG.getVTList(MVT::Other, MVT::Glue),
11769 SDValue eax = DAG.getCopyFromReg(ftol, DL, X86::EAX,
11770 MVT::i32, ftol.getValue(1));
11771 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), DL, X86::EDX,
11772 MVT::i32, eax.getValue(2));
11773 SDValue Ops[] = { eax, edx };
11774 SDValue pair = IsReplace
11775 ? DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops)
11776 : DAG.getMergeValues(Ops, DL);
11777 return std::make_pair(pair, SDValue());
11781 static SDValue LowerAVXExtend(SDValue Op, SelectionDAG &DAG,
11782 const X86Subtarget *Subtarget) {
11783 MVT VT = Op->getSimpleValueType(0);
11784 SDValue In = Op->getOperand(0);
11785 MVT InVT = In.getSimpleValueType();
11788 // Optimize vectors in AVX mode:
11791 // Use vpunpcklwd for 4 lower elements v8i16 -> v4i32.
11792 // Use vpunpckhwd for 4 upper elements v8i16 -> v4i32.
11793 // Concat upper and lower parts.
11796 // Use vpunpckldq for 4 lower elements v4i32 -> v2i64.
11797 // Use vpunpckhdq for 4 upper elements v4i32 -> v2i64.
11798 // Concat upper and lower parts.
11801 if (((VT != MVT::v16i16) || (InVT != MVT::v16i8)) &&
11802 ((VT != MVT::v8i32) || (InVT != MVT::v8i16)) &&
11803 ((VT != MVT::v4i64) || (InVT != MVT::v4i32)))
11806 if (Subtarget->hasInt256())
11807 return DAG.getNode(X86ISD::VZEXT, dl, VT, In);
11809 SDValue ZeroVec = getZeroVector(InVT, Subtarget, DAG, dl);
11810 SDValue Undef = DAG.getUNDEF(InVT);
11811 bool NeedZero = Op.getOpcode() == ISD::ZERO_EXTEND;
11812 SDValue OpLo = getUnpackl(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
11813 SDValue OpHi = getUnpackh(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
11815 MVT HVT = MVT::getVectorVT(VT.getVectorElementType(),
11816 VT.getVectorNumElements()/2);
11818 OpLo = DAG.getNode(ISD::BITCAST, dl, HVT, OpLo);
11819 OpHi = DAG.getNode(ISD::BITCAST, dl, HVT, OpHi);
11821 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
11824 static SDValue LowerZERO_EXTEND_AVX512(SDValue Op,
11825 SelectionDAG &DAG) {
11826 MVT VT = Op->getSimpleValueType(0);
11827 SDValue In = Op->getOperand(0);
11828 MVT InVT = In.getSimpleValueType();
11830 unsigned int NumElts = VT.getVectorNumElements();
11831 if (NumElts != 8 && NumElts != 16)
11834 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1)
11835 return DAG.getNode(X86ISD::VZEXT, DL, VT, In);
11837 EVT ExtVT = (NumElts == 8)? MVT::v8i64 : MVT::v16i32;
11838 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
11839 // Now we have only mask extension
11840 assert(InVT.getVectorElementType() == MVT::i1);
11841 SDValue Cst = DAG.getTargetConstant(1, ExtVT.getScalarType());
11842 const Constant *C = (dyn_cast<ConstantSDNode>(Cst))->getConstantIntValue();
11843 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
11844 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
11845 SDValue Ld = DAG.getLoad(Cst.getValueType(), DL, DAG.getEntryNode(), CP,
11846 MachinePointerInfo::getConstantPool(),
11847 false, false, false, Alignment);
11849 SDValue Brcst = DAG.getNode(X86ISD::VBROADCASTM, DL, ExtVT, In, Ld);
11850 if (VT.is512BitVector())
11852 return DAG.getNode(X86ISD::VTRUNC, DL, VT, Brcst);
11855 static SDValue LowerANY_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
11856 SelectionDAG &DAG) {
11857 if (Subtarget->hasFp256()) {
11858 SDValue Res = LowerAVXExtend(Op, DAG, Subtarget);
11866 static SDValue LowerZERO_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
11867 SelectionDAG &DAG) {
11869 MVT VT = Op.getSimpleValueType();
11870 SDValue In = Op.getOperand(0);
11871 MVT SVT = In.getSimpleValueType();
11873 if (VT.is512BitVector() || SVT.getVectorElementType() == MVT::i1)
11874 return LowerZERO_EXTEND_AVX512(Op, DAG);
11876 if (Subtarget->hasFp256()) {
11877 SDValue Res = LowerAVXExtend(Op, DAG, Subtarget);
11882 assert(!VT.is256BitVector() || !SVT.is128BitVector() ||
11883 VT.getVectorNumElements() != SVT.getVectorNumElements());
11887 SDValue X86TargetLowering::LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const {
11889 MVT VT = Op.getSimpleValueType();
11890 SDValue In = Op.getOperand(0);
11891 MVT InVT = In.getSimpleValueType();
11893 if (VT == MVT::i1) {
11894 assert((InVT.isInteger() && (InVT.getSizeInBits() <= 64)) &&
11895 "Invalid scalar TRUNCATE operation");
11896 if (InVT == MVT::i32)
11898 if (InVT.getSizeInBits() == 64)
11899 In = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::i32, In);
11900 else if (InVT.getSizeInBits() < 32)
11901 In = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, In);
11902 return DAG.getNode(ISD::TRUNCATE, DL, VT, In);
11904 assert(VT.getVectorNumElements() == InVT.getVectorNumElements() &&
11905 "Invalid TRUNCATE operation");
11907 if (InVT.is512BitVector() || VT.getVectorElementType() == MVT::i1) {
11908 if (VT.getVectorElementType().getSizeInBits() >=8)
11909 return DAG.getNode(X86ISD::VTRUNC, DL, VT, In);
11911 assert(VT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
11912 unsigned NumElts = InVT.getVectorNumElements();
11913 assert ((NumElts == 8 || NumElts == 16) && "Unexpected vector type");
11914 if (InVT.getSizeInBits() < 512) {
11915 MVT ExtVT = (NumElts == 16)? MVT::v16i32 : MVT::v8i64;
11916 In = DAG.getNode(ISD::SIGN_EXTEND, DL, ExtVT, In);
11920 SDValue Cst = DAG.getTargetConstant(1, InVT.getVectorElementType());
11921 const Constant *C = (dyn_cast<ConstantSDNode>(Cst))->getConstantIntValue();
11922 SDValue CP = DAG.getConstantPool(C, getPointerTy());
11923 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
11924 SDValue Ld = DAG.getLoad(Cst.getValueType(), DL, DAG.getEntryNode(), CP,
11925 MachinePointerInfo::getConstantPool(),
11926 false, false, false, Alignment);
11927 SDValue OneV = DAG.getNode(X86ISD::VBROADCAST, DL, InVT, Ld);
11928 SDValue And = DAG.getNode(ISD::AND, DL, InVT, OneV, In);
11929 return DAG.getNode(X86ISD::TESTM, DL, VT, And, And);
11932 if ((VT == MVT::v4i32) && (InVT == MVT::v4i64)) {
11933 // On AVX2, v4i64 -> v4i32 becomes VPERMD.
11934 if (Subtarget->hasInt256()) {
11935 static const int ShufMask[] = {0, 2, 4, 6, -1, -1, -1, -1};
11936 In = DAG.getNode(ISD::BITCAST, DL, MVT::v8i32, In);
11937 In = DAG.getVectorShuffle(MVT::v8i32, DL, In, DAG.getUNDEF(MVT::v8i32),
11939 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, In,
11940 DAG.getIntPtrConstant(0));
11943 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
11944 DAG.getIntPtrConstant(0));
11945 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
11946 DAG.getIntPtrConstant(2));
11947 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo);
11948 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi);
11949 static const int ShufMask[] = {0, 2, 4, 6};
11950 return DAG.getVectorShuffle(VT, DL, OpLo, OpHi, ShufMask);
11953 if ((VT == MVT::v8i16) && (InVT == MVT::v8i32)) {
11954 // On AVX2, v8i32 -> v8i16 becomed PSHUFB.
11955 if (Subtarget->hasInt256()) {
11956 In = DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, In);
11958 SmallVector<SDValue,32> pshufbMask;
11959 for (unsigned i = 0; i < 2; ++i) {
11960 pshufbMask.push_back(DAG.getConstant(0x0, MVT::i8));
11961 pshufbMask.push_back(DAG.getConstant(0x1, MVT::i8));
11962 pshufbMask.push_back(DAG.getConstant(0x4, MVT::i8));
11963 pshufbMask.push_back(DAG.getConstant(0x5, MVT::i8));
11964 pshufbMask.push_back(DAG.getConstant(0x8, MVT::i8));
11965 pshufbMask.push_back(DAG.getConstant(0x9, MVT::i8));
11966 pshufbMask.push_back(DAG.getConstant(0xc, MVT::i8));
11967 pshufbMask.push_back(DAG.getConstant(0xd, MVT::i8));
11968 for (unsigned j = 0; j < 8; ++j)
11969 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
11971 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, pshufbMask);
11972 In = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v32i8, In, BV);
11973 In = DAG.getNode(ISD::BITCAST, DL, MVT::v4i64, In);
11975 static const int ShufMask[] = {0, 2, -1, -1};
11976 In = DAG.getVectorShuffle(MVT::v4i64, DL, In, DAG.getUNDEF(MVT::v4i64),
11978 In = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
11979 DAG.getIntPtrConstant(0));
11980 return DAG.getNode(ISD::BITCAST, DL, VT, In);
11983 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
11984 DAG.getIntPtrConstant(0));
11986 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
11987 DAG.getIntPtrConstant(4));
11989 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpLo);
11990 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpHi);
11992 // The PSHUFB mask:
11993 static const int ShufMask1[] = {0, 1, 4, 5, 8, 9, 12, 13,
11994 -1, -1, -1, -1, -1, -1, -1, -1};
11996 SDValue Undef = DAG.getUNDEF(MVT::v16i8);
11997 OpLo = DAG.getVectorShuffle(MVT::v16i8, DL, OpLo, Undef, ShufMask1);
11998 OpHi = DAG.getVectorShuffle(MVT::v16i8, DL, OpHi, Undef, ShufMask1);
12000 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo);
12001 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi);
12003 // The MOVLHPS Mask:
12004 static const int ShufMask2[] = {0, 1, 4, 5};
12005 SDValue res = DAG.getVectorShuffle(MVT::v4i32, DL, OpLo, OpHi, ShufMask2);
12006 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, res);
12009 // Handle truncation of V256 to V128 using shuffles.
12010 if (!VT.is128BitVector() || !InVT.is256BitVector())
12013 assert(Subtarget->hasFp256() && "256-bit vector without AVX!");
12015 unsigned NumElems = VT.getVectorNumElements();
12016 MVT NVT = MVT::getVectorVT(VT.getVectorElementType(), NumElems * 2);
12018 SmallVector<int, 16> MaskVec(NumElems * 2, -1);
12019 // Prepare truncation shuffle mask
12020 for (unsigned i = 0; i != NumElems; ++i)
12021 MaskVec[i] = i * 2;
12022 SDValue V = DAG.getVectorShuffle(NVT, DL,
12023 DAG.getNode(ISD::BITCAST, DL, NVT, In),
12024 DAG.getUNDEF(NVT), &MaskVec[0]);
12025 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, V,
12026 DAG.getIntPtrConstant(0));
12029 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op,
12030 SelectionDAG &DAG) const {
12031 assert(!Op.getSimpleValueType().isVector());
12033 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
12034 /*IsSigned=*/ true, /*IsReplace=*/ false);
12035 SDValue FIST = Vals.first, StackSlot = Vals.second;
12036 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
12037 if (!FIST.getNode()) return Op;
12039 if (StackSlot.getNode())
12040 // Load the result.
12041 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
12042 FIST, StackSlot, MachinePointerInfo(),
12043 false, false, false, 0);
12045 // The node is the result.
12049 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op,
12050 SelectionDAG &DAG) const {
12051 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
12052 /*IsSigned=*/ false, /*IsReplace=*/ false);
12053 SDValue FIST = Vals.first, StackSlot = Vals.second;
12054 assert(FIST.getNode() && "Unexpected failure");
12056 if (StackSlot.getNode())
12057 // Load the result.
12058 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
12059 FIST, StackSlot, MachinePointerInfo(),
12060 false, false, false, 0);
12062 // The node is the result.
12066 static SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) {
12068 MVT VT = Op.getSimpleValueType();
12069 SDValue In = Op.getOperand(0);
12070 MVT SVT = In.getSimpleValueType();
12072 assert(SVT == MVT::v2f32 && "Only customize MVT::v2f32 type legalization!");
12074 return DAG.getNode(X86ISD::VFPEXT, DL, VT,
12075 DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v4f32,
12076 In, DAG.getUNDEF(SVT)));
12079 static SDValue LowerFABS(SDValue Op, SelectionDAG &DAG) {
12080 LLVMContext *Context = DAG.getContext();
12082 MVT VT = Op.getSimpleValueType();
12084 unsigned NumElts = VT == MVT::f64 ? 2 : 4;
12085 if (VT.isVector()) {
12086 EltVT = VT.getVectorElementType();
12087 NumElts = VT.getVectorNumElements();
12090 if (EltVT == MVT::f64)
12091 C = ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
12092 APInt(64, ~(1ULL << 63))));
12094 C = ConstantFP::get(*Context, APFloat(APFloat::IEEEsingle,
12095 APInt(32, ~(1U << 31))));
12096 C = ConstantVector::getSplat(NumElts, C);
12097 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
12098 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy());
12099 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
12100 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
12101 MachinePointerInfo::getConstantPool(),
12102 false, false, false, Alignment);
12103 if (VT.isVector()) {
12104 MVT ANDVT = VT.is128BitVector() ? MVT::v2i64 : MVT::v4i64;
12105 return DAG.getNode(ISD::BITCAST, dl, VT,
12106 DAG.getNode(ISD::AND, dl, ANDVT,
12107 DAG.getNode(ISD::BITCAST, dl, ANDVT,
12109 DAG.getNode(ISD::BITCAST, dl, ANDVT, Mask)));
12111 return DAG.getNode(X86ISD::FAND, dl, VT, Op.getOperand(0), Mask);
12114 static SDValue LowerFNEG(SDValue Op, SelectionDAG &DAG) {
12115 LLVMContext *Context = DAG.getContext();
12117 MVT VT = Op.getSimpleValueType();
12119 unsigned NumElts = VT == MVT::f64 ? 2 : 4;
12120 if (VT.isVector()) {
12121 EltVT = VT.getVectorElementType();
12122 NumElts = VT.getVectorNumElements();
12125 if (EltVT == MVT::f64)
12126 C = ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
12127 APInt(64, 1ULL << 63)));
12129 C = ConstantFP::get(*Context, APFloat(APFloat::IEEEsingle,
12130 APInt(32, 1U << 31)));
12131 C = ConstantVector::getSplat(NumElts, C);
12132 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
12133 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy());
12134 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
12135 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
12136 MachinePointerInfo::getConstantPool(),
12137 false, false, false, Alignment);
12138 if (VT.isVector()) {
12139 MVT XORVT = MVT::getVectorVT(MVT::i64, VT.getSizeInBits()/64);
12140 return DAG.getNode(ISD::BITCAST, dl, VT,
12141 DAG.getNode(ISD::XOR, dl, XORVT,
12142 DAG.getNode(ISD::BITCAST, dl, XORVT,
12144 DAG.getNode(ISD::BITCAST, dl, XORVT, Mask)));
12147 return DAG.getNode(X86ISD::FXOR, dl, VT, Op.getOperand(0), Mask);
12150 static SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) {
12151 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
12152 LLVMContext *Context = DAG.getContext();
12153 SDValue Op0 = Op.getOperand(0);
12154 SDValue Op1 = Op.getOperand(1);
12156 MVT VT = Op.getSimpleValueType();
12157 MVT SrcVT = Op1.getSimpleValueType();
12159 // If second operand is smaller, extend it first.
12160 if (SrcVT.bitsLT(VT)) {
12161 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
12164 // And if it is bigger, shrink it first.
12165 if (SrcVT.bitsGT(VT)) {
12166 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1));
12170 // At this point the operands and the result should have the same
12171 // type, and that won't be f80 since that is not custom lowered.
12173 // First get the sign bit of second operand.
12174 SmallVector<Constant*,4> CV;
12175 if (SrcVT == MVT::f64) {
12176 const fltSemantics &Sem = APFloat::IEEEdouble;
12177 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 1ULL << 63))));
12178 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 0))));
12180 const fltSemantics &Sem = APFloat::IEEEsingle;
12181 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 1U << 31))));
12182 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
12183 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
12184 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
12186 Constant *C = ConstantVector::get(CV);
12187 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy(), 16);
12188 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx,
12189 MachinePointerInfo::getConstantPool(),
12190 false, false, false, 16);
12191 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1);
12193 // Shift sign bit right or left if the two operands have different types.
12194 if (SrcVT.bitsGT(VT)) {
12195 // Op0 is MVT::f32, Op1 is MVT::f64.
12196 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, SignBit);
12197 SignBit = DAG.getNode(X86ISD::FSRL, dl, MVT::v2f64, SignBit,
12198 DAG.getConstant(32, MVT::i32));
12199 SignBit = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, SignBit);
12200 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, SignBit,
12201 DAG.getIntPtrConstant(0));
12204 // Clear first operand sign bit.
12206 if (VT == MVT::f64) {
12207 const fltSemantics &Sem = APFloat::IEEEdouble;
12208 CV.push_back(ConstantFP::get(*Context, APFloat(Sem,
12209 APInt(64, ~(1ULL << 63)))));
12210 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 0))));
12212 const fltSemantics &Sem = APFloat::IEEEsingle;
12213 CV.push_back(ConstantFP::get(*Context, APFloat(Sem,
12214 APInt(32, ~(1U << 31)))));
12215 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
12216 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
12217 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
12219 C = ConstantVector::get(CV);
12220 CPIdx = DAG.getConstantPool(C, TLI.getPointerTy(), 16);
12221 SDValue Mask2 = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
12222 MachinePointerInfo::getConstantPool(),
12223 false, false, false, 16);
12224 SDValue Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Mask2);
12226 // Or the value with the sign bit.
12227 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit);
12230 static SDValue LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) {
12231 SDValue N0 = Op.getOperand(0);
12233 MVT VT = Op.getSimpleValueType();
12235 // Lower ISD::FGETSIGN to (AND (X86ISD::FGETSIGNx86 ...) 1).
12236 SDValue xFGETSIGN = DAG.getNode(X86ISD::FGETSIGNx86, dl, VT, N0,
12237 DAG.getConstant(1, VT));
12238 return DAG.getNode(ISD::AND, dl, VT, xFGETSIGN, DAG.getConstant(1, VT));
12241 // LowerVectorAllZeroTest - Check whether an OR'd tree is PTEST-able.
12243 static SDValue LowerVectorAllZeroTest(SDValue Op, const X86Subtarget *Subtarget,
12244 SelectionDAG &DAG) {
12245 assert(Op.getOpcode() == ISD::OR && "Only check OR'd tree.");
12247 if (!Subtarget->hasSSE41())
12250 if (!Op->hasOneUse())
12253 SDNode *N = Op.getNode();
12256 SmallVector<SDValue, 8> Opnds;
12257 DenseMap<SDValue, unsigned> VecInMap;
12258 SmallVector<SDValue, 8> VecIns;
12259 EVT VT = MVT::Other;
12261 // Recognize a special case where a vector is casted into wide integer to
12263 Opnds.push_back(N->getOperand(0));
12264 Opnds.push_back(N->getOperand(1));
12266 for (unsigned Slot = 0, e = Opnds.size(); Slot < e; ++Slot) {
12267 SmallVectorImpl<SDValue>::const_iterator I = Opnds.begin() + Slot;
12268 // BFS traverse all OR'd operands.
12269 if (I->getOpcode() == ISD::OR) {
12270 Opnds.push_back(I->getOperand(0));
12271 Opnds.push_back(I->getOperand(1));
12272 // Re-evaluate the number of nodes to be traversed.
12273 e += 2; // 2 more nodes (LHS and RHS) are pushed.
12277 // Quit if a non-EXTRACT_VECTOR_ELT
12278 if (I->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
12281 // Quit if without a constant index.
12282 SDValue Idx = I->getOperand(1);
12283 if (!isa<ConstantSDNode>(Idx))
12286 SDValue ExtractedFromVec = I->getOperand(0);
12287 DenseMap<SDValue, unsigned>::iterator M = VecInMap.find(ExtractedFromVec);
12288 if (M == VecInMap.end()) {
12289 VT = ExtractedFromVec.getValueType();
12290 // Quit if not 128/256-bit vector.
12291 if (!VT.is128BitVector() && !VT.is256BitVector())
12293 // Quit if not the same type.
12294 if (VecInMap.begin() != VecInMap.end() &&
12295 VT != VecInMap.begin()->first.getValueType())
12297 M = VecInMap.insert(std::make_pair(ExtractedFromVec, 0)).first;
12298 VecIns.push_back(ExtractedFromVec);
12300 M->second |= 1U << cast<ConstantSDNode>(Idx)->getZExtValue();
12303 assert((VT.is128BitVector() || VT.is256BitVector()) &&
12304 "Not extracted from 128-/256-bit vector.");
12306 unsigned FullMask = (1U << VT.getVectorNumElements()) - 1U;
12308 for (DenseMap<SDValue, unsigned>::const_iterator
12309 I = VecInMap.begin(), E = VecInMap.end(); I != E; ++I) {
12310 // Quit if not all elements are used.
12311 if (I->second != FullMask)
12315 EVT TestVT = VT.is128BitVector() ? MVT::v2i64 : MVT::v4i64;
12317 // Cast all vectors into TestVT for PTEST.
12318 for (unsigned i = 0, e = VecIns.size(); i < e; ++i)
12319 VecIns[i] = DAG.getNode(ISD::BITCAST, DL, TestVT, VecIns[i]);
12321 // If more than one full vectors are evaluated, OR them first before PTEST.
12322 for (unsigned Slot = 0, e = VecIns.size(); e - Slot > 1; Slot += 2, e += 1) {
12323 // Each iteration will OR 2 nodes and append the result until there is only
12324 // 1 node left, i.e. the final OR'd value of all vectors.
12325 SDValue LHS = VecIns[Slot];
12326 SDValue RHS = VecIns[Slot + 1];
12327 VecIns.push_back(DAG.getNode(ISD::OR, DL, TestVT, LHS, RHS));
12330 return DAG.getNode(X86ISD::PTEST, DL, MVT::i32,
12331 VecIns.back(), VecIns.back());
12334 /// \brief return true if \c Op has a use that doesn't just read flags.
12335 static bool hasNonFlagsUse(SDValue Op) {
12336 for (SDNode::use_iterator UI = Op->use_begin(), UE = Op->use_end(); UI != UE;
12338 SDNode *User = *UI;
12339 unsigned UOpNo = UI.getOperandNo();
12340 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
12341 // Look pass truncate.
12342 UOpNo = User->use_begin().getOperandNo();
12343 User = *User->use_begin();
12346 if (User->getOpcode() != ISD::BRCOND && User->getOpcode() != ISD::SETCC &&
12347 !(User->getOpcode() == ISD::SELECT && UOpNo == 0))
12353 /// Emit nodes that will be selected as "test Op0,Op0", or something
12355 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC, SDLoc dl,
12356 SelectionDAG &DAG) const {
12357 if (Op.getValueType() == MVT::i1)
12358 // KORTEST instruction should be selected
12359 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
12360 DAG.getConstant(0, Op.getValueType()));
12362 // CF and OF aren't always set the way we want. Determine which
12363 // of these we need.
12364 bool NeedCF = false;
12365 bool NeedOF = false;
12368 case X86::COND_A: case X86::COND_AE:
12369 case X86::COND_B: case X86::COND_BE:
12372 case X86::COND_G: case X86::COND_GE:
12373 case X86::COND_L: case X86::COND_LE:
12374 case X86::COND_O: case X86::COND_NO: {
12375 // Check if we really need to set the
12376 // Overflow flag. If NoSignedWrap is present
12377 // that is not actually needed.
12378 switch (Op->getOpcode()) {
12383 const BinaryWithFlagsSDNode *BinNode =
12384 cast<BinaryWithFlagsSDNode>(Op.getNode());
12385 if (BinNode->hasNoSignedWrap())
12395 // See if we can use the EFLAGS value from the operand instead of
12396 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
12397 // we prove that the arithmetic won't overflow, we can't use OF or CF.
12398 if (Op.getResNo() != 0 || NeedOF || NeedCF) {
12399 // Emit a CMP with 0, which is the TEST pattern.
12400 //if (Op.getValueType() == MVT::i1)
12401 // return DAG.getNode(X86ISD::CMP, dl, MVT::i1, Op,
12402 // DAG.getConstant(0, MVT::i1));
12403 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
12404 DAG.getConstant(0, Op.getValueType()));
12406 unsigned Opcode = 0;
12407 unsigned NumOperands = 0;
12409 // Truncate operations may prevent the merge of the SETCC instruction
12410 // and the arithmetic instruction before it. Attempt to truncate the operands
12411 // of the arithmetic instruction and use a reduced bit-width instruction.
12412 bool NeedTruncation = false;
12413 SDValue ArithOp = Op;
12414 if (Op->getOpcode() == ISD::TRUNCATE && Op->hasOneUse()) {
12415 SDValue Arith = Op->getOperand(0);
12416 // Both the trunc and the arithmetic op need to have one user each.
12417 if (Arith->hasOneUse())
12418 switch (Arith.getOpcode()) {
12425 NeedTruncation = true;
12431 // NOTICE: In the code below we use ArithOp to hold the arithmetic operation
12432 // which may be the result of a CAST. We use the variable 'Op', which is the
12433 // non-casted variable when we check for possible users.
12434 switch (ArithOp.getOpcode()) {
12436 // Due to an isel shortcoming, be conservative if this add is likely to be
12437 // selected as part of a load-modify-store instruction. When the root node
12438 // in a match is a store, isel doesn't know how to remap non-chain non-flag
12439 // uses of other nodes in the match, such as the ADD in this case. This
12440 // leads to the ADD being left around and reselected, with the result being
12441 // two adds in the output. Alas, even if none our users are stores, that
12442 // doesn't prove we're O.K. Ergo, if we have any parents that aren't
12443 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require
12444 // climbing the DAG back to the root, and it doesn't seem to be worth the
12446 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
12447 UE = Op.getNode()->use_end(); UI != UE; ++UI)
12448 if (UI->getOpcode() != ISD::CopyToReg &&
12449 UI->getOpcode() != ISD::SETCC &&
12450 UI->getOpcode() != ISD::STORE)
12453 if (ConstantSDNode *C =
12454 dyn_cast<ConstantSDNode>(ArithOp.getNode()->getOperand(1))) {
12455 // An add of one will be selected as an INC.
12456 if (C->getAPIntValue() == 1 && !Subtarget->slowIncDec()) {
12457 Opcode = X86ISD::INC;
12462 // An add of negative one (subtract of one) will be selected as a DEC.
12463 if (C->getAPIntValue().isAllOnesValue() && !Subtarget->slowIncDec()) {
12464 Opcode = X86ISD::DEC;
12470 // Otherwise use a regular EFLAGS-setting add.
12471 Opcode = X86ISD::ADD;
12476 // If we have a constant logical shift that's only used in a comparison
12477 // against zero turn it into an equivalent AND. This allows turning it into
12478 // a TEST instruction later.
12479 if ((X86CC == X86::COND_E || X86CC == X86::COND_NE) && Op->hasOneUse() &&
12480 isa<ConstantSDNode>(Op->getOperand(1)) && !hasNonFlagsUse(Op)) {
12481 EVT VT = Op.getValueType();
12482 unsigned BitWidth = VT.getSizeInBits();
12483 unsigned ShAmt = Op->getConstantOperandVal(1);
12484 if (ShAmt >= BitWidth) // Avoid undefined shifts.
12486 APInt Mask = ArithOp.getOpcode() == ISD::SRL
12487 ? APInt::getHighBitsSet(BitWidth, BitWidth - ShAmt)
12488 : APInt::getLowBitsSet(BitWidth, BitWidth - ShAmt);
12489 if (!Mask.isSignedIntN(32)) // Avoid large immediates.
12491 SDValue New = DAG.getNode(ISD::AND, dl, VT, Op->getOperand(0),
12492 DAG.getConstant(Mask, VT));
12493 DAG.ReplaceAllUsesWith(Op, New);
12499 // If the primary and result isn't used, don't bother using X86ISD::AND,
12500 // because a TEST instruction will be better.
12501 if (!hasNonFlagsUse(Op))
12507 // Due to the ISEL shortcoming noted above, be conservative if this op is
12508 // likely to be selected as part of a load-modify-store instruction.
12509 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
12510 UE = Op.getNode()->use_end(); UI != UE; ++UI)
12511 if (UI->getOpcode() == ISD::STORE)
12514 // Otherwise use a regular EFLAGS-setting instruction.
12515 switch (ArithOp.getOpcode()) {
12516 default: llvm_unreachable("unexpected operator!");
12517 case ISD::SUB: Opcode = X86ISD::SUB; break;
12518 case ISD::XOR: Opcode = X86ISD::XOR; break;
12519 case ISD::AND: Opcode = X86ISD::AND; break;
12521 if (!NeedTruncation && (X86CC == X86::COND_E || X86CC == X86::COND_NE)) {
12522 SDValue EFLAGS = LowerVectorAllZeroTest(Op, Subtarget, DAG);
12523 if (EFLAGS.getNode())
12526 Opcode = X86ISD::OR;
12540 return SDValue(Op.getNode(), 1);
12546 // If we found that truncation is beneficial, perform the truncation and
12548 if (NeedTruncation) {
12549 EVT VT = Op.getValueType();
12550 SDValue WideVal = Op->getOperand(0);
12551 EVT WideVT = WideVal.getValueType();
12552 unsigned ConvertedOp = 0;
12553 // Use a target machine opcode to prevent further DAGCombine
12554 // optimizations that may separate the arithmetic operations
12555 // from the setcc node.
12556 switch (WideVal.getOpcode()) {
12558 case ISD::ADD: ConvertedOp = X86ISD::ADD; break;
12559 case ISD::SUB: ConvertedOp = X86ISD::SUB; break;
12560 case ISD::AND: ConvertedOp = X86ISD::AND; break;
12561 case ISD::OR: ConvertedOp = X86ISD::OR; break;
12562 case ISD::XOR: ConvertedOp = X86ISD::XOR; break;
12566 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
12567 if (TLI.isOperationLegal(WideVal.getOpcode(), WideVT)) {
12568 SDValue V0 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(0));
12569 SDValue V1 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(1));
12570 Op = DAG.getNode(ConvertedOp, dl, VT, V0, V1);
12576 // Emit a CMP with 0, which is the TEST pattern.
12577 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
12578 DAG.getConstant(0, Op.getValueType()));
12580 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
12581 SmallVector<SDValue, 4> Ops;
12582 for (unsigned i = 0; i != NumOperands; ++i)
12583 Ops.push_back(Op.getOperand(i));
12585 SDValue New = DAG.getNode(Opcode, dl, VTs, Ops);
12586 DAG.ReplaceAllUsesWith(Op, New);
12587 return SDValue(New.getNode(), 1);
12590 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
12592 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
12593 SDLoc dl, SelectionDAG &DAG) const {
12594 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1)) {
12595 if (C->getAPIntValue() == 0)
12596 return EmitTest(Op0, X86CC, dl, DAG);
12598 if (Op0.getValueType() == MVT::i1)
12599 llvm_unreachable("Unexpected comparison operation for MVT::i1 operands");
12602 if ((Op0.getValueType() == MVT::i8 || Op0.getValueType() == MVT::i16 ||
12603 Op0.getValueType() == MVT::i32 || Op0.getValueType() == MVT::i64)) {
12604 // Do the comparison at i32 if it's smaller, besides the Atom case.
12605 // This avoids subregister aliasing issues. Keep the smaller reference
12606 // if we're optimizing for size, however, as that'll allow better folding
12607 // of memory operations.
12608 if (Op0.getValueType() != MVT::i32 && Op0.getValueType() != MVT::i64 &&
12609 !DAG.getMachineFunction().getFunction()->getAttributes().hasAttribute(
12610 AttributeSet::FunctionIndex, Attribute::MinSize) &&
12611 !Subtarget->isAtom()) {
12612 unsigned ExtendOp =
12613 isX86CCUnsigned(X86CC) ? ISD::ZERO_EXTEND : ISD::SIGN_EXTEND;
12614 Op0 = DAG.getNode(ExtendOp, dl, MVT::i32, Op0);
12615 Op1 = DAG.getNode(ExtendOp, dl, MVT::i32, Op1);
12617 // Use SUB instead of CMP to enable CSE between SUB and CMP.
12618 SDVTList VTs = DAG.getVTList(Op0.getValueType(), MVT::i32);
12619 SDValue Sub = DAG.getNode(X86ISD::SUB, dl, VTs,
12621 return SDValue(Sub.getNode(), 1);
12623 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
12626 /// Convert a comparison if required by the subtarget.
12627 SDValue X86TargetLowering::ConvertCmpIfNecessary(SDValue Cmp,
12628 SelectionDAG &DAG) const {
12629 // If the subtarget does not support the FUCOMI instruction, floating-point
12630 // comparisons have to be converted.
12631 if (Subtarget->hasCMov() ||
12632 Cmp.getOpcode() != X86ISD::CMP ||
12633 !Cmp.getOperand(0).getValueType().isFloatingPoint() ||
12634 !Cmp.getOperand(1).getValueType().isFloatingPoint())
12637 // The instruction selector will select an FUCOM instruction instead of
12638 // FUCOMI, which writes the comparison result to FPSW instead of EFLAGS. Hence
12639 // build an SDNode sequence that transfers the result from FPSW into EFLAGS:
12640 // (X86sahf (trunc (srl (X86fp_stsw (trunc (X86cmp ...)), 8))))
12642 SDValue TruncFPSW = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, Cmp);
12643 SDValue FNStSW = DAG.getNode(X86ISD::FNSTSW16r, dl, MVT::i16, TruncFPSW);
12644 SDValue Srl = DAG.getNode(ISD::SRL, dl, MVT::i16, FNStSW,
12645 DAG.getConstant(8, MVT::i8));
12646 SDValue TruncSrl = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Srl);
12647 return DAG.getNode(X86ISD::SAHF, dl, MVT::i32, TruncSrl);
12650 static bool isAllOnes(SDValue V) {
12651 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
12652 return C && C->isAllOnesValue();
12655 /// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node
12656 /// if it's possible.
12657 SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC,
12658 SDLoc dl, SelectionDAG &DAG) const {
12659 SDValue Op0 = And.getOperand(0);
12660 SDValue Op1 = And.getOperand(1);
12661 if (Op0.getOpcode() == ISD::TRUNCATE)
12662 Op0 = Op0.getOperand(0);
12663 if (Op1.getOpcode() == ISD::TRUNCATE)
12664 Op1 = Op1.getOperand(0);
12667 if (Op1.getOpcode() == ISD::SHL)
12668 std::swap(Op0, Op1);
12669 if (Op0.getOpcode() == ISD::SHL) {
12670 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0)))
12671 if (And00C->getZExtValue() == 1) {
12672 // If we looked past a truncate, check that it's only truncating away
12674 unsigned BitWidth = Op0.getValueSizeInBits();
12675 unsigned AndBitWidth = And.getValueSizeInBits();
12676 if (BitWidth > AndBitWidth) {
12678 DAG.computeKnownBits(Op0, Zeros, Ones);
12679 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth)
12683 RHS = Op0.getOperand(1);
12685 } else if (Op1.getOpcode() == ISD::Constant) {
12686 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1);
12687 uint64_t AndRHSVal = AndRHS->getZExtValue();
12688 SDValue AndLHS = Op0;
12690 if (AndRHSVal == 1 && AndLHS.getOpcode() == ISD::SRL) {
12691 LHS = AndLHS.getOperand(0);
12692 RHS = AndLHS.getOperand(1);
12695 // Use BT if the immediate can't be encoded in a TEST instruction.
12696 if (!isUInt<32>(AndRHSVal) && isPowerOf2_64(AndRHSVal)) {
12698 RHS = DAG.getConstant(Log2_64_Ceil(AndRHSVal), LHS.getValueType());
12702 if (LHS.getNode()) {
12703 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT
12704 // instruction. Since the shift amount is in-range-or-undefined, we know
12705 // that doing a bittest on the i32 value is ok. We extend to i32 because
12706 // the encoding for the i16 version is larger than the i32 version.
12707 // Also promote i16 to i32 for performance / code size reason.
12708 if (LHS.getValueType() == MVT::i8 ||
12709 LHS.getValueType() == MVT::i16)
12710 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
12712 // If the operand types disagree, extend the shift amount to match. Since
12713 // BT ignores high bits (like shifts) we can use anyextend.
12714 if (LHS.getValueType() != RHS.getValueType())
12715 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
12717 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
12718 X86::CondCode Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
12719 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
12720 DAG.getConstant(Cond, MVT::i8), BT);
12726 /// \brief - Turns an ISD::CondCode into a value suitable for SSE floating point
12728 static int translateX86FSETCC(ISD::CondCode SetCCOpcode, SDValue &Op0,
12733 // SSE Condition code mapping:
12742 switch (SetCCOpcode) {
12743 default: llvm_unreachable("Unexpected SETCC condition");
12745 case ISD::SETEQ: SSECC = 0; break;
12747 case ISD::SETGT: Swap = true; // Fallthrough
12749 case ISD::SETOLT: SSECC = 1; break;
12751 case ISD::SETGE: Swap = true; // Fallthrough
12753 case ISD::SETOLE: SSECC = 2; break;
12754 case ISD::SETUO: SSECC = 3; break;
12756 case ISD::SETNE: SSECC = 4; break;
12757 case ISD::SETULE: Swap = true; // Fallthrough
12758 case ISD::SETUGE: SSECC = 5; break;
12759 case ISD::SETULT: Swap = true; // Fallthrough
12760 case ISD::SETUGT: SSECC = 6; break;
12761 case ISD::SETO: SSECC = 7; break;
12763 case ISD::SETONE: SSECC = 8; break;
12766 std::swap(Op0, Op1);
12771 // Lower256IntVSETCC - Break a VSETCC 256-bit integer VSETCC into two new 128
12772 // ones, and then concatenate the result back.
12773 static SDValue Lower256IntVSETCC(SDValue Op, SelectionDAG &DAG) {
12774 MVT VT = Op.getSimpleValueType();
12776 assert(VT.is256BitVector() && Op.getOpcode() == ISD::SETCC &&
12777 "Unsupported value type for operation");
12779 unsigned NumElems = VT.getVectorNumElements();
12781 SDValue CC = Op.getOperand(2);
12783 // Extract the LHS vectors
12784 SDValue LHS = Op.getOperand(0);
12785 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
12786 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
12788 // Extract the RHS vectors
12789 SDValue RHS = Op.getOperand(1);
12790 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
12791 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
12793 // Issue the operation on the smaller types and concatenate the result back
12794 MVT EltVT = VT.getVectorElementType();
12795 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
12796 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
12797 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1, CC),
12798 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC));
12801 static SDValue LowerIntVSETCC_AVX512(SDValue Op, SelectionDAG &DAG,
12802 const X86Subtarget *Subtarget) {
12803 SDValue Op0 = Op.getOperand(0);
12804 SDValue Op1 = Op.getOperand(1);
12805 SDValue CC = Op.getOperand(2);
12806 MVT VT = Op.getSimpleValueType();
12809 assert(Op0.getValueType().getVectorElementType().getSizeInBits() >= 32 &&
12810 Op.getValueType().getScalarType() == MVT::i1 &&
12811 "Cannot set masked compare for this operation");
12813 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
12815 bool Unsigned = false;
12818 switch (SetCCOpcode) {
12819 default: llvm_unreachable("Unexpected SETCC condition");
12820 case ISD::SETNE: SSECC = 4; break;
12821 case ISD::SETEQ: Opc = X86ISD::PCMPEQM; break;
12822 case ISD::SETUGT: SSECC = 6; Unsigned = true; break;
12823 case ISD::SETLT: Swap = true; //fall-through
12824 case ISD::SETGT: Opc = X86ISD::PCMPGTM; break;
12825 case ISD::SETULT: SSECC = 1; Unsigned = true; break;
12826 case ISD::SETUGE: SSECC = 5; Unsigned = true; break; //NLT
12827 case ISD::SETGE: Swap = true; SSECC = 2; break; // LE + swap
12828 case ISD::SETULE: Unsigned = true; //fall-through
12829 case ISD::SETLE: SSECC = 2; break;
12833 std::swap(Op0, Op1);
12835 return DAG.getNode(Opc, dl, VT, Op0, Op1);
12836 Opc = Unsigned ? X86ISD::CMPMU: X86ISD::CMPM;
12837 return DAG.getNode(Opc, dl, VT, Op0, Op1,
12838 DAG.getConstant(SSECC, MVT::i8));
12841 /// \brief Try to turn a VSETULT into a VSETULE by modifying its second
12842 /// operand \p Op1. If non-trivial (for example because it's not constant)
12843 /// return an empty value.
12844 static SDValue ChangeVSETULTtoVSETULE(SDLoc dl, SDValue Op1, SelectionDAG &DAG)
12846 BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(Op1.getNode());
12850 MVT VT = Op1.getSimpleValueType();
12851 MVT EVT = VT.getVectorElementType();
12852 unsigned n = VT.getVectorNumElements();
12853 SmallVector<SDValue, 8> ULTOp1;
12855 for (unsigned i = 0; i < n; ++i) {
12856 ConstantSDNode *Elt = dyn_cast<ConstantSDNode>(BV->getOperand(i));
12857 if (!Elt || Elt->isOpaque() || Elt->getValueType(0) != EVT)
12860 // Avoid underflow.
12861 APInt Val = Elt->getAPIntValue();
12865 ULTOp1.push_back(DAG.getConstant(Val - 1, EVT));
12868 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, ULTOp1);
12871 static SDValue LowerVSETCC(SDValue Op, const X86Subtarget *Subtarget,
12872 SelectionDAG &DAG) {
12873 SDValue Op0 = Op.getOperand(0);
12874 SDValue Op1 = Op.getOperand(1);
12875 SDValue CC = Op.getOperand(2);
12876 MVT VT = Op.getSimpleValueType();
12877 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
12878 bool isFP = Op.getOperand(1).getSimpleValueType().isFloatingPoint();
12883 MVT EltVT = Op0.getSimpleValueType().getVectorElementType();
12884 assert(EltVT == MVT::f32 || EltVT == MVT::f64);
12887 unsigned SSECC = translateX86FSETCC(SetCCOpcode, Op0, Op1);
12888 unsigned Opc = X86ISD::CMPP;
12889 if (Subtarget->hasAVX512() && VT.getVectorElementType() == MVT::i1) {
12890 assert(VT.getVectorNumElements() <= 16);
12891 Opc = X86ISD::CMPM;
12893 // In the two special cases we can't handle, emit two comparisons.
12896 unsigned CombineOpc;
12897 if (SetCCOpcode == ISD::SETUEQ) {
12898 CC0 = 3; CC1 = 0; CombineOpc = ISD::OR;
12900 assert(SetCCOpcode == ISD::SETONE);
12901 CC0 = 7; CC1 = 4; CombineOpc = ISD::AND;
12904 SDValue Cmp0 = DAG.getNode(Opc, dl, VT, Op0, Op1,
12905 DAG.getConstant(CC0, MVT::i8));
12906 SDValue Cmp1 = DAG.getNode(Opc, dl, VT, Op0, Op1,
12907 DAG.getConstant(CC1, MVT::i8));
12908 return DAG.getNode(CombineOpc, dl, VT, Cmp0, Cmp1);
12910 // Handle all other FP comparisons here.
12911 return DAG.getNode(Opc, dl, VT, Op0, Op1,
12912 DAG.getConstant(SSECC, MVT::i8));
12915 // Break 256-bit integer vector compare into smaller ones.
12916 if (VT.is256BitVector() && !Subtarget->hasInt256())
12917 return Lower256IntVSETCC(Op, DAG);
12919 bool MaskResult = (VT.getVectorElementType() == MVT::i1);
12920 EVT OpVT = Op1.getValueType();
12921 if (Subtarget->hasAVX512()) {
12922 if (Op1.getValueType().is512BitVector() ||
12923 (MaskResult && OpVT.getVectorElementType().getSizeInBits() >= 32))
12924 return LowerIntVSETCC_AVX512(Op, DAG, Subtarget);
12926 // In AVX-512 architecture setcc returns mask with i1 elements,
12927 // But there is no compare instruction for i8 and i16 elements.
12928 // We are not talking about 512-bit operands in this case, these
12929 // types are illegal.
12931 (OpVT.getVectorElementType().getSizeInBits() < 32 &&
12932 OpVT.getVectorElementType().getSizeInBits() >= 8))
12933 return DAG.getNode(ISD::TRUNCATE, dl, VT,
12934 DAG.getNode(ISD::SETCC, dl, OpVT, Op0, Op1, CC));
12937 // We are handling one of the integer comparisons here. Since SSE only has
12938 // GT and EQ comparisons for integer, swapping operands and multiple
12939 // operations may be required for some comparisons.
12941 bool Swap = false, Invert = false, FlipSigns = false, MinMax = false;
12942 bool Subus = false;
12944 switch (SetCCOpcode) {
12945 default: llvm_unreachable("Unexpected SETCC condition");
12946 case ISD::SETNE: Invert = true;
12947 case ISD::SETEQ: Opc = X86ISD::PCMPEQ; break;
12948 case ISD::SETLT: Swap = true;
12949 case ISD::SETGT: Opc = X86ISD::PCMPGT; break;
12950 case ISD::SETGE: Swap = true;
12951 case ISD::SETLE: Opc = X86ISD::PCMPGT;
12952 Invert = true; break;
12953 case ISD::SETULT: Swap = true;
12954 case ISD::SETUGT: Opc = X86ISD::PCMPGT;
12955 FlipSigns = true; break;
12956 case ISD::SETUGE: Swap = true;
12957 case ISD::SETULE: Opc = X86ISD::PCMPGT;
12958 FlipSigns = true; Invert = true; break;
12961 // Special case: Use min/max operations for SETULE/SETUGE
12962 MVT VET = VT.getVectorElementType();
12964 (Subtarget->hasSSE41() && (VET >= MVT::i8 && VET <= MVT::i32))
12965 || (Subtarget->hasSSE2() && (VET == MVT::i8));
12968 switch (SetCCOpcode) {
12970 case ISD::SETULE: Opc = X86ISD::UMIN; MinMax = true; break;
12971 case ISD::SETUGE: Opc = X86ISD::UMAX; MinMax = true; break;
12974 if (MinMax) { Swap = false; Invert = false; FlipSigns = false; }
12977 bool hasSubus = Subtarget->hasSSE2() && (VET == MVT::i8 || VET == MVT::i16);
12978 if (!MinMax && hasSubus) {
12979 // As another special case, use PSUBUS[BW] when it's profitable. E.g. for
12981 // t = psubus Op0, Op1
12982 // pcmpeq t, <0..0>
12983 switch (SetCCOpcode) {
12985 case ISD::SETULT: {
12986 // If the comparison is against a constant we can turn this into a
12987 // setule. With psubus, setule does not require a swap. This is
12988 // beneficial because the constant in the register is no longer
12989 // destructed as the destination so it can be hoisted out of a loop.
12990 // Only do this pre-AVX since vpcmp* is no longer destructive.
12991 if (Subtarget->hasAVX())
12993 SDValue ULEOp1 = ChangeVSETULTtoVSETULE(dl, Op1, DAG);
12994 if (ULEOp1.getNode()) {
12996 Subus = true; Invert = false; Swap = false;
13000 // Psubus is better than flip-sign because it requires no inversion.
13001 case ISD::SETUGE: Subus = true; Invert = false; Swap = true; break;
13002 case ISD::SETULE: Subus = true; Invert = false; Swap = false; break;
13006 Opc = X86ISD::SUBUS;
13012 std::swap(Op0, Op1);
13014 // Check that the operation in question is available (most are plain SSE2,
13015 // but PCMPGTQ and PCMPEQQ have different requirements).
13016 if (VT == MVT::v2i64) {
13017 if (Opc == X86ISD::PCMPGT && !Subtarget->hasSSE42()) {
13018 assert(Subtarget->hasSSE2() && "Don't know how to lower!");
13020 // First cast everything to the right type.
13021 Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0);
13022 Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1);
13024 // Since SSE has no unsigned integer comparisons, we need to flip the sign
13025 // bits of the inputs before performing those operations. The lower
13026 // compare is always unsigned.
13029 SB = DAG.getConstant(0x80000000U, MVT::v4i32);
13031 SDValue Sign = DAG.getConstant(0x80000000U, MVT::i32);
13032 SDValue Zero = DAG.getConstant(0x00000000U, MVT::i32);
13033 SB = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
13034 Sign, Zero, Sign, Zero);
13036 Op0 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op0, SB);
13037 Op1 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op1, SB);
13039 // Emulate PCMPGTQ with (hi1 > hi2) | ((hi1 == hi2) & (lo1 > lo2))
13040 SDValue GT = DAG.getNode(X86ISD::PCMPGT, dl, MVT::v4i32, Op0, Op1);
13041 SDValue EQ = DAG.getNode(X86ISD::PCMPEQ, dl, MVT::v4i32, Op0, Op1);
13043 // Create masks for only the low parts/high parts of the 64 bit integers.
13044 static const int MaskHi[] = { 1, 1, 3, 3 };
13045 static const int MaskLo[] = { 0, 0, 2, 2 };
13046 SDValue EQHi = DAG.getVectorShuffle(MVT::v4i32, dl, EQ, EQ, MaskHi);
13047 SDValue GTLo = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskLo);
13048 SDValue GTHi = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskHi);
13050 SDValue Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, EQHi, GTLo);
13051 Result = DAG.getNode(ISD::OR, dl, MVT::v4i32, Result, GTHi);
13054 Result = DAG.getNOT(dl, Result, MVT::v4i32);
13056 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
13059 if (Opc == X86ISD::PCMPEQ && !Subtarget->hasSSE41()) {
13060 // If pcmpeqq is missing but pcmpeqd is available synthesize pcmpeqq with
13061 // pcmpeqd + pshufd + pand.
13062 assert(Subtarget->hasSSE2() && !FlipSigns && "Don't know how to lower!");
13064 // First cast everything to the right type.
13065 Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0);
13066 Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1);
13069 SDValue Result = DAG.getNode(Opc, dl, MVT::v4i32, Op0, Op1);
13071 // Make sure the lower and upper halves are both all-ones.
13072 static const int Mask[] = { 1, 0, 3, 2 };
13073 SDValue Shuf = DAG.getVectorShuffle(MVT::v4i32, dl, Result, Result, Mask);
13074 Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, Result, Shuf);
13077 Result = DAG.getNOT(dl, Result, MVT::v4i32);
13079 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
13083 // Since SSE has no unsigned integer comparisons, we need to flip the sign
13084 // bits of the inputs before performing those operations.
13086 EVT EltVT = VT.getVectorElementType();
13087 SDValue SB = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()), VT);
13088 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SB);
13089 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SB);
13092 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
13094 // If the logical-not of the result is required, perform that now.
13096 Result = DAG.getNOT(dl, Result, VT);
13099 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Op0, Result);
13102 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Result,
13103 getZeroVector(VT, Subtarget, DAG, dl));
13108 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
13110 MVT VT = Op.getSimpleValueType();
13112 if (VT.isVector()) return LowerVSETCC(Op, Subtarget, DAG);
13114 assert(((!Subtarget->hasAVX512() && VT == MVT::i8) || (VT == MVT::i1))
13115 && "SetCC type must be 8-bit or 1-bit integer");
13116 SDValue Op0 = Op.getOperand(0);
13117 SDValue Op1 = Op.getOperand(1);
13119 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
13121 // Optimize to BT if possible.
13122 // Lower (X & (1 << N)) == 0 to BT(X, N).
13123 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
13124 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
13125 if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() &&
13126 Op1.getOpcode() == ISD::Constant &&
13127 cast<ConstantSDNode>(Op1)->isNullValue() &&
13128 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
13129 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG);
13130 if (NewSetCC.getNode())
13134 // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of
13136 if (Op1.getOpcode() == ISD::Constant &&
13137 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 ||
13138 cast<ConstantSDNode>(Op1)->isNullValue()) &&
13139 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
13141 // If the input is a setcc, then reuse the input setcc or use a new one with
13142 // the inverted condition.
13143 if (Op0.getOpcode() == X86ISD::SETCC) {
13144 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0);
13145 bool Invert = (CC == ISD::SETNE) ^
13146 cast<ConstantSDNode>(Op1)->isNullValue();
13150 CCode = X86::GetOppositeBranchCondition(CCode);
13151 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
13152 DAG.getConstant(CCode, MVT::i8),
13153 Op0.getOperand(1));
13155 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
13159 if ((Op0.getValueType() == MVT::i1) && (Op1.getOpcode() == ISD::Constant) &&
13160 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1) &&
13161 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
13163 ISD::CondCode NewCC = ISD::getSetCCInverse(CC, true);
13164 return DAG.getSetCC(dl, VT, Op0, DAG.getConstant(0, MVT::i1), NewCC);
13167 bool isFP = Op1.getSimpleValueType().isFloatingPoint();
13168 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG);
13169 if (X86CC == X86::COND_INVALID)
13172 SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, dl, DAG);
13173 EFLAGS = ConvertCmpIfNecessary(EFLAGS, DAG);
13174 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
13175 DAG.getConstant(X86CC, MVT::i8), EFLAGS);
13177 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
13181 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
13182 static bool isX86LogicalCmp(SDValue Op) {
13183 unsigned Opc = Op.getNode()->getOpcode();
13184 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI ||
13185 Opc == X86ISD::SAHF)
13187 if (Op.getResNo() == 1 &&
13188 (Opc == X86ISD::ADD ||
13189 Opc == X86ISD::SUB ||
13190 Opc == X86ISD::ADC ||
13191 Opc == X86ISD::SBB ||
13192 Opc == X86ISD::SMUL ||
13193 Opc == X86ISD::UMUL ||
13194 Opc == X86ISD::INC ||
13195 Opc == X86ISD::DEC ||
13196 Opc == X86ISD::OR ||
13197 Opc == X86ISD::XOR ||
13198 Opc == X86ISD::AND))
13201 if (Op.getResNo() == 2 && Opc == X86ISD::UMUL)
13207 static bool isTruncWithZeroHighBitsInput(SDValue V, SelectionDAG &DAG) {
13208 if (V.getOpcode() != ISD::TRUNCATE)
13211 SDValue VOp0 = V.getOperand(0);
13212 unsigned InBits = VOp0.getValueSizeInBits();
13213 unsigned Bits = V.getValueSizeInBits();
13214 return DAG.MaskedValueIsZero(VOp0, APInt::getHighBitsSet(InBits,InBits-Bits));
13217 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
13218 bool addTest = true;
13219 SDValue Cond = Op.getOperand(0);
13220 SDValue Op1 = Op.getOperand(1);
13221 SDValue Op2 = Op.getOperand(2);
13223 EVT VT = Op1.getValueType();
13226 // Lower fp selects into a CMP/AND/ANDN/OR sequence when the necessary SSE ops
13227 // are available. Otherwise fp cmovs get lowered into a less efficient branch
13228 // sequence later on.
13229 if (Cond.getOpcode() == ISD::SETCC &&
13230 ((Subtarget->hasSSE2() && (VT == MVT::f32 || VT == MVT::f64)) ||
13231 (Subtarget->hasSSE1() && VT == MVT::f32)) &&
13232 VT == Cond.getOperand(0).getValueType() && Cond->hasOneUse()) {
13233 SDValue CondOp0 = Cond.getOperand(0), CondOp1 = Cond.getOperand(1);
13234 int SSECC = translateX86FSETCC(
13235 cast<CondCodeSDNode>(Cond.getOperand(2))->get(), CondOp0, CondOp1);
13238 if (Subtarget->hasAVX512()) {
13239 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CondOp0, CondOp1,
13240 DAG.getConstant(SSECC, MVT::i8));
13241 return DAG.getNode(X86ISD::SELECT, DL, VT, Cmp, Op1, Op2);
13243 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, VT, CondOp0, CondOp1,
13244 DAG.getConstant(SSECC, MVT::i8));
13245 SDValue AndN = DAG.getNode(X86ISD::FANDN, DL, VT, Cmp, Op2);
13246 SDValue And = DAG.getNode(X86ISD::FAND, DL, VT, Cmp, Op1);
13247 return DAG.getNode(X86ISD::FOR, DL, VT, AndN, And);
13251 if (Cond.getOpcode() == ISD::SETCC) {
13252 SDValue NewCond = LowerSETCC(Cond, DAG);
13253 if (NewCond.getNode())
13257 // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y
13258 // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y
13259 // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y
13260 // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y
13261 if (Cond.getOpcode() == X86ISD::SETCC &&
13262 Cond.getOperand(1).getOpcode() == X86ISD::CMP &&
13263 isZero(Cond.getOperand(1).getOperand(1))) {
13264 SDValue Cmp = Cond.getOperand(1);
13266 unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue();
13268 if ((isAllOnes(Op1) || isAllOnes(Op2)) &&
13269 (CondCode == X86::COND_E || CondCode == X86::COND_NE)) {
13270 SDValue Y = isAllOnes(Op2) ? Op1 : Op2;
13272 SDValue CmpOp0 = Cmp.getOperand(0);
13273 // Apply further optimizations for special cases
13274 // (select (x != 0), -1, 0) -> neg & sbb
13275 // (select (x == 0), 0, -1) -> neg & sbb
13276 if (ConstantSDNode *YC = dyn_cast<ConstantSDNode>(Y))
13277 if (YC->isNullValue() &&
13278 (isAllOnes(Op1) == (CondCode == X86::COND_NE))) {
13279 SDVTList VTs = DAG.getVTList(CmpOp0.getValueType(), MVT::i32);
13280 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, VTs,
13281 DAG.getConstant(0, CmpOp0.getValueType()),
13283 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
13284 DAG.getConstant(X86::COND_B, MVT::i8),
13285 SDValue(Neg.getNode(), 1));
13289 Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32,
13290 CmpOp0, DAG.getConstant(1, CmpOp0.getValueType()));
13291 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
13293 SDValue Res = // Res = 0 or -1.
13294 DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
13295 DAG.getConstant(X86::COND_B, MVT::i8), Cmp);
13297 if (isAllOnes(Op1) != (CondCode == X86::COND_E))
13298 Res = DAG.getNOT(DL, Res, Res.getValueType());
13300 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2);
13301 if (!N2C || !N2C->isNullValue())
13302 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y);
13307 // Look past (and (setcc_carry (cmp ...)), 1).
13308 if (Cond.getOpcode() == ISD::AND &&
13309 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
13310 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
13311 if (C && C->getAPIntValue() == 1)
13312 Cond = Cond.getOperand(0);
13315 // If condition flag is set by a X86ISD::CMP, then use it as the condition
13316 // setting operand in place of the X86ISD::SETCC.
13317 unsigned CondOpcode = Cond.getOpcode();
13318 if (CondOpcode == X86ISD::SETCC ||
13319 CondOpcode == X86ISD::SETCC_CARRY) {
13320 CC = Cond.getOperand(0);
13322 SDValue Cmp = Cond.getOperand(1);
13323 unsigned Opc = Cmp.getOpcode();
13324 MVT VT = Op.getSimpleValueType();
13326 bool IllegalFPCMov = false;
13327 if (VT.isFloatingPoint() && !VT.isVector() &&
13328 !isScalarFPTypeInSSEReg(VT)) // FPStack?
13329 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
13331 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
13332 Opc == X86ISD::BT) { // FIXME
13336 } else if (CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
13337 CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
13338 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
13339 Cond.getOperand(0).getValueType() != MVT::i8)) {
13340 SDValue LHS = Cond.getOperand(0);
13341 SDValue RHS = Cond.getOperand(1);
13342 unsigned X86Opcode;
13345 switch (CondOpcode) {
13346 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
13347 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
13348 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
13349 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
13350 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
13351 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
13352 default: llvm_unreachable("unexpected overflowing operator");
13354 if (CondOpcode == ISD::UMULO)
13355 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
13358 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
13360 SDValue X86Op = DAG.getNode(X86Opcode, DL, VTs, LHS, RHS);
13362 if (CondOpcode == ISD::UMULO)
13363 Cond = X86Op.getValue(2);
13365 Cond = X86Op.getValue(1);
13367 CC = DAG.getConstant(X86Cond, MVT::i8);
13372 // Look pass the truncate if the high bits are known zero.
13373 if (isTruncWithZeroHighBitsInput(Cond, DAG))
13374 Cond = Cond.getOperand(0);
13376 // We know the result of AND is compared against zero. Try to match
13378 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
13379 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG);
13380 if (NewSetCC.getNode()) {
13381 CC = NewSetCC.getOperand(0);
13382 Cond = NewSetCC.getOperand(1);
13389 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
13390 Cond = EmitTest(Cond, X86::COND_NE, DL, DAG);
13393 // a < b ? -1 : 0 -> RES = ~setcc_carry
13394 // a < b ? 0 : -1 -> RES = setcc_carry
13395 // a >= b ? -1 : 0 -> RES = setcc_carry
13396 // a >= b ? 0 : -1 -> RES = ~setcc_carry
13397 if (Cond.getOpcode() == X86ISD::SUB) {
13398 Cond = ConvertCmpIfNecessary(Cond, DAG);
13399 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue();
13401 if ((CondCode == X86::COND_AE || CondCode == X86::COND_B) &&
13402 (isAllOnes(Op1) || isAllOnes(Op2)) && (isZero(Op1) || isZero(Op2))) {
13403 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
13404 DAG.getConstant(X86::COND_B, MVT::i8), Cond);
13405 if (isAllOnes(Op1) != (CondCode == X86::COND_B))
13406 return DAG.getNOT(DL, Res, Res.getValueType());
13411 // X86 doesn't have an i8 cmov. If both operands are the result of a truncate
13412 // widen the cmov and push the truncate through. This avoids introducing a new
13413 // branch during isel and doesn't add any extensions.
13414 if (Op.getValueType() == MVT::i8 &&
13415 Op1.getOpcode() == ISD::TRUNCATE && Op2.getOpcode() == ISD::TRUNCATE) {
13416 SDValue T1 = Op1.getOperand(0), T2 = Op2.getOperand(0);
13417 if (T1.getValueType() == T2.getValueType() &&
13418 // Blacklist CopyFromReg to avoid partial register stalls.
13419 T1.getOpcode() != ISD::CopyFromReg && T2.getOpcode()!=ISD::CopyFromReg){
13420 SDVTList VTs = DAG.getVTList(T1.getValueType(), MVT::Glue);
13421 SDValue Cmov = DAG.getNode(X86ISD::CMOV, DL, VTs, T2, T1, CC, Cond);
13422 return DAG.getNode(ISD::TRUNCATE, DL, Op.getValueType(), Cmov);
13426 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
13427 // condition is true.
13428 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
13429 SDValue Ops[] = { Op2, Op1, CC, Cond };
13430 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops);
13433 static SDValue LowerSIGN_EXTEND_AVX512(SDValue Op, SelectionDAG &DAG) {
13434 MVT VT = Op->getSimpleValueType(0);
13435 SDValue In = Op->getOperand(0);
13436 MVT InVT = In.getSimpleValueType();
13439 unsigned int NumElts = VT.getVectorNumElements();
13440 if (NumElts != 8 && NumElts != 16)
13443 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1)
13444 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
13446 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13447 assert (InVT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
13449 MVT ExtVT = (NumElts == 8) ? MVT::v8i64 : MVT::v16i32;
13450 Constant *C = ConstantInt::get(*DAG.getContext(),
13451 APInt::getAllOnesValue(ExtVT.getScalarType().getSizeInBits()));
13453 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
13454 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
13455 SDValue Ld = DAG.getLoad(ExtVT.getScalarType(), dl, DAG.getEntryNode(), CP,
13456 MachinePointerInfo::getConstantPool(),
13457 false, false, false, Alignment);
13458 SDValue Brcst = DAG.getNode(X86ISD::VBROADCASTM, dl, ExtVT, In, Ld);
13459 if (VT.is512BitVector())
13461 return DAG.getNode(X86ISD::VTRUNC, dl, VT, Brcst);
13464 static SDValue LowerSIGN_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
13465 SelectionDAG &DAG) {
13466 MVT VT = Op->getSimpleValueType(0);
13467 SDValue In = Op->getOperand(0);
13468 MVT InVT = In.getSimpleValueType();
13471 if (VT.is512BitVector() || InVT.getVectorElementType() == MVT::i1)
13472 return LowerSIGN_EXTEND_AVX512(Op, DAG);
13474 if ((VT != MVT::v4i64 || InVT != MVT::v4i32) &&
13475 (VT != MVT::v8i32 || InVT != MVT::v8i16) &&
13476 (VT != MVT::v16i16 || InVT != MVT::v16i8))
13479 if (Subtarget->hasInt256())
13480 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
13482 // Optimize vectors in AVX mode
13483 // Sign extend v8i16 to v8i32 and
13486 // Divide input vector into two parts
13487 // for v4i32 the shuffle mask will be { 0, 1, -1, -1} {2, 3, -1, -1}
13488 // use vpmovsx instruction to extend v4i32 -> v2i64; v8i16 -> v4i32
13489 // concat the vectors to original VT
13491 unsigned NumElems = InVT.getVectorNumElements();
13492 SDValue Undef = DAG.getUNDEF(InVT);
13494 SmallVector<int,8> ShufMask1(NumElems, -1);
13495 for (unsigned i = 0; i != NumElems/2; ++i)
13498 SDValue OpLo = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask1[0]);
13500 SmallVector<int,8> ShufMask2(NumElems, -1);
13501 for (unsigned i = 0; i != NumElems/2; ++i)
13502 ShufMask2[i] = i + NumElems/2;
13504 SDValue OpHi = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask2[0]);
13506 MVT HalfVT = MVT::getVectorVT(VT.getScalarType(),
13507 VT.getVectorNumElements()/2);
13509 OpLo = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpLo);
13510 OpHi = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpHi);
13512 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
13515 // Lower vector extended loads using a shuffle. If SSSE3 is not available we
13516 // may emit an illegal shuffle but the expansion is still better than scalar
13517 // code. We generate X86ISD::VSEXT for SEXTLOADs if it's available, otherwise
13518 // we'll emit a shuffle and a arithmetic shift.
13519 // TODO: It is possible to support ZExt by zeroing the undef values during
13520 // the shuffle phase or after the shuffle.
13521 static SDValue LowerExtendedLoad(SDValue Op, const X86Subtarget *Subtarget,
13522 SelectionDAG &DAG) {
13523 MVT RegVT = Op.getSimpleValueType();
13524 assert(RegVT.isVector() && "We only custom lower vector sext loads.");
13525 assert(RegVT.isInteger() &&
13526 "We only custom lower integer vector sext loads.");
13528 // Nothing useful we can do without SSE2 shuffles.
13529 assert(Subtarget->hasSSE2() && "We only custom lower sext loads with SSE2.");
13531 LoadSDNode *Ld = cast<LoadSDNode>(Op.getNode());
13533 EVT MemVT = Ld->getMemoryVT();
13534 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13535 unsigned RegSz = RegVT.getSizeInBits();
13537 ISD::LoadExtType Ext = Ld->getExtensionType();
13539 assert((Ext == ISD::EXTLOAD || Ext == ISD::SEXTLOAD)
13540 && "Only anyext and sext are currently implemented.");
13541 assert(MemVT != RegVT && "Cannot extend to the same type");
13542 assert(MemVT.isVector() && "Must load a vector from memory");
13544 unsigned NumElems = RegVT.getVectorNumElements();
13545 unsigned MemSz = MemVT.getSizeInBits();
13546 assert(RegSz > MemSz && "Register size must be greater than the mem size");
13548 if (Ext == ISD::SEXTLOAD && RegSz == 256 && !Subtarget->hasInt256()) {
13549 // The only way in which we have a legal 256-bit vector result but not the
13550 // integer 256-bit operations needed to directly lower a sextload is if we
13551 // have AVX1 but not AVX2. In that case, we can always emit a sextload to
13552 // a 128-bit vector and a normal sign_extend to 256-bits that should get
13553 // correctly legalized. We do this late to allow the canonical form of
13554 // sextload to persist throughout the rest of the DAG combiner -- it wants
13555 // to fold together any extensions it can, and so will fuse a sign_extend
13556 // of an sextload into a sextload targeting a wider value.
13558 if (MemSz == 128) {
13559 // Just switch this to a normal load.
13560 assert(TLI.isTypeLegal(MemVT) && "If the memory type is a 128-bit type, "
13561 "it must be a legal 128-bit vector "
13563 Load = DAG.getLoad(MemVT, dl, Ld->getChain(), Ld->getBasePtr(),
13564 Ld->getPointerInfo(), Ld->isVolatile(), Ld->isNonTemporal(),
13565 Ld->isInvariant(), Ld->getAlignment());
13567 assert(MemSz < 128 &&
13568 "Can't extend a type wider than 128 bits to a 256 bit vector!");
13569 // Do an sext load to a 128-bit vector type. We want to use the same
13570 // number of elements, but elements half as wide. This will end up being
13571 // recursively lowered by this routine, but will succeed as we definitely
13572 // have all the necessary features if we're using AVX1.
13574 EVT::getIntegerVT(*DAG.getContext(), RegVT.getScalarSizeInBits() / 2);
13575 EVT HalfVecVT = EVT::getVectorVT(*DAG.getContext(), HalfEltVT, NumElems);
13577 DAG.getExtLoad(Ext, dl, HalfVecVT, Ld->getChain(), Ld->getBasePtr(),
13578 Ld->getPointerInfo(), MemVT, Ld->isVolatile(),
13579 Ld->isNonTemporal(), Ld->isInvariant(),
13580 Ld->getAlignment());
13583 // Replace chain users with the new chain.
13584 assert(Load->getNumValues() == 2 && "Loads must carry a chain!");
13585 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), Load.getValue(1));
13587 // Finally, do a normal sign-extend to the desired register.
13588 return DAG.getSExtOrTrunc(Load, dl, RegVT);
13591 // All sizes must be a power of two.
13592 assert(isPowerOf2_32(RegSz * MemSz * NumElems) &&
13593 "Non-power-of-two elements are not custom lowered!");
13595 // Attempt to load the original value using scalar loads.
13596 // Find the largest scalar type that divides the total loaded size.
13597 MVT SclrLoadTy = MVT::i8;
13598 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
13599 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
13600 MVT Tp = (MVT::SimpleValueType)tp;
13601 if (TLI.isTypeLegal(Tp) && ((MemSz % Tp.getSizeInBits()) == 0)) {
13606 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
13607 if (TLI.isTypeLegal(MVT::f64) && SclrLoadTy.getSizeInBits() < 64 &&
13609 SclrLoadTy = MVT::f64;
13611 // Calculate the number of scalar loads that we need to perform
13612 // in order to load our vector from memory.
13613 unsigned NumLoads = MemSz / SclrLoadTy.getSizeInBits();
13615 assert((Ext != ISD::SEXTLOAD || NumLoads == 1) &&
13616 "Can only lower sext loads with a single scalar load!");
13618 unsigned loadRegZize = RegSz;
13619 if (Ext == ISD::SEXTLOAD && RegSz == 256)
13622 // Represent our vector as a sequence of elements which are the
13623 // largest scalar that we can load.
13624 EVT LoadUnitVecVT = EVT::getVectorVT(
13625 *DAG.getContext(), SclrLoadTy, loadRegZize / SclrLoadTy.getSizeInBits());
13627 // Represent the data using the same element type that is stored in
13628 // memory. In practice, we ''widen'' MemVT.
13630 EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
13631 loadRegZize / MemVT.getScalarType().getSizeInBits());
13633 assert(WideVecVT.getSizeInBits() == LoadUnitVecVT.getSizeInBits() &&
13634 "Invalid vector type");
13636 // We can't shuffle using an illegal type.
13637 assert(TLI.isTypeLegal(WideVecVT) &&
13638 "We only lower types that form legal widened vector types");
13640 SmallVector<SDValue, 8> Chains;
13641 SDValue Ptr = Ld->getBasePtr();
13642 SDValue Increment =
13643 DAG.getConstant(SclrLoadTy.getSizeInBits() / 8, TLI.getPointerTy());
13644 SDValue Res = DAG.getUNDEF(LoadUnitVecVT);
13646 for (unsigned i = 0; i < NumLoads; ++i) {
13647 // Perform a single load.
13648 SDValue ScalarLoad =
13649 DAG.getLoad(SclrLoadTy, dl, Ld->getChain(), Ptr, Ld->getPointerInfo(),
13650 Ld->isVolatile(), Ld->isNonTemporal(), Ld->isInvariant(),
13651 Ld->getAlignment());
13652 Chains.push_back(ScalarLoad.getValue(1));
13653 // Create the first element type using SCALAR_TO_VECTOR in order to avoid
13654 // another round of DAGCombining.
13656 Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LoadUnitVecVT, ScalarLoad);
13658 Res = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, LoadUnitVecVT, Res,
13659 ScalarLoad, DAG.getIntPtrConstant(i));
13661 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
13664 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
13666 // Bitcast the loaded value to a vector of the original element type, in
13667 // the size of the target vector type.
13668 SDValue SlicedVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, Res);
13669 unsigned SizeRatio = RegSz / MemSz;
13671 if (Ext == ISD::SEXTLOAD) {
13672 // If we have SSE4.1, we can directly emit a VSEXT node.
13673 if (Subtarget->hasSSE41()) {
13674 SDValue Sext = DAG.getNode(X86ISD::VSEXT, dl, RegVT, SlicedVec);
13675 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
13679 // Otherwise we'll shuffle the small elements in the high bits of the
13680 // larger type and perform an arithmetic shift. If the shift is not legal
13681 // it's better to scalarize.
13682 assert(TLI.isOperationLegalOrCustom(ISD::SRA, RegVT) &&
13683 "We can't implement a sext load without an arithmetic right shift!");
13685 // Redistribute the loaded elements into the different locations.
13686 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
13687 for (unsigned i = 0; i != NumElems; ++i)
13688 ShuffleVec[i * SizeRatio + SizeRatio - 1] = i;
13690 SDValue Shuff = DAG.getVectorShuffle(
13691 WideVecVT, dl, SlicedVec, DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
13693 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
13695 // Build the arithmetic shift.
13696 unsigned Amt = RegVT.getVectorElementType().getSizeInBits() -
13697 MemVT.getVectorElementType().getSizeInBits();
13699 DAG.getNode(ISD::SRA, dl, RegVT, Shuff, DAG.getConstant(Amt, RegVT));
13701 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
13705 // Redistribute the loaded elements into the different locations.
13706 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
13707 for (unsigned i = 0; i != NumElems; ++i)
13708 ShuffleVec[i * SizeRatio] = i;
13710 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec,
13711 DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
13713 // Bitcast to the requested type.
13714 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
13715 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
13719 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
13720 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
13721 // from the AND / OR.
13722 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
13723 Opc = Op.getOpcode();
13724 if (Opc != ISD::OR && Opc != ISD::AND)
13726 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
13727 Op.getOperand(0).hasOneUse() &&
13728 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
13729 Op.getOperand(1).hasOneUse());
13732 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
13733 // 1 and that the SETCC node has a single use.
13734 static bool isXor1OfSetCC(SDValue Op) {
13735 if (Op.getOpcode() != ISD::XOR)
13737 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
13738 if (N1C && N1C->getAPIntValue() == 1) {
13739 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
13740 Op.getOperand(0).hasOneUse();
13745 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
13746 bool addTest = true;
13747 SDValue Chain = Op.getOperand(0);
13748 SDValue Cond = Op.getOperand(1);
13749 SDValue Dest = Op.getOperand(2);
13752 bool Inverted = false;
13754 if (Cond.getOpcode() == ISD::SETCC) {
13755 // Check for setcc([su]{add,sub,mul}o == 0).
13756 if (cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETEQ &&
13757 isa<ConstantSDNode>(Cond.getOperand(1)) &&
13758 cast<ConstantSDNode>(Cond.getOperand(1))->isNullValue() &&
13759 Cond.getOperand(0).getResNo() == 1 &&
13760 (Cond.getOperand(0).getOpcode() == ISD::SADDO ||
13761 Cond.getOperand(0).getOpcode() == ISD::UADDO ||
13762 Cond.getOperand(0).getOpcode() == ISD::SSUBO ||
13763 Cond.getOperand(0).getOpcode() == ISD::USUBO ||
13764 Cond.getOperand(0).getOpcode() == ISD::SMULO ||
13765 Cond.getOperand(0).getOpcode() == ISD::UMULO)) {
13767 Cond = Cond.getOperand(0);
13769 SDValue NewCond = LowerSETCC(Cond, DAG);
13770 if (NewCond.getNode())
13775 // FIXME: LowerXALUO doesn't handle these!!
13776 else if (Cond.getOpcode() == X86ISD::ADD ||
13777 Cond.getOpcode() == X86ISD::SUB ||
13778 Cond.getOpcode() == X86ISD::SMUL ||
13779 Cond.getOpcode() == X86ISD::UMUL)
13780 Cond = LowerXALUO(Cond, DAG);
13783 // Look pass (and (setcc_carry (cmp ...)), 1).
13784 if (Cond.getOpcode() == ISD::AND &&
13785 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
13786 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
13787 if (C && C->getAPIntValue() == 1)
13788 Cond = Cond.getOperand(0);
13791 // If condition flag is set by a X86ISD::CMP, then use it as the condition
13792 // setting operand in place of the X86ISD::SETCC.
13793 unsigned CondOpcode = Cond.getOpcode();
13794 if (CondOpcode == X86ISD::SETCC ||
13795 CondOpcode == X86ISD::SETCC_CARRY) {
13796 CC = Cond.getOperand(0);
13798 SDValue Cmp = Cond.getOperand(1);
13799 unsigned Opc = Cmp.getOpcode();
13800 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
13801 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
13805 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
13809 // These can only come from an arithmetic instruction with overflow,
13810 // e.g. SADDO, UADDO.
13811 Cond = Cond.getNode()->getOperand(1);
13817 CondOpcode = Cond.getOpcode();
13818 if (CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
13819 CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
13820 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
13821 Cond.getOperand(0).getValueType() != MVT::i8)) {
13822 SDValue LHS = Cond.getOperand(0);
13823 SDValue RHS = Cond.getOperand(1);
13824 unsigned X86Opcode;
13827 // Keep this in sync with LowerXALUO, otherwise we might create redundant
13828 // instructions that can't be removed afterwards (i.e. X86ISD::ADD and
13830 switch (CondOpcode) {
13831 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
13833 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
13835 X86Opcode = X86ISD::INC; X86Cond = X86::COND_O;
13838 X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
13839 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
13841 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
13843 X86Opcode = X86ISD::DEC; X86Cond = X86::COND_O;
13846 X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
13847 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
13848 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
13849 default: llvm_unreachable("unexpected overflowing operator");
13852 X86Cond = X86::GetOppositeBranchCondition((X86::CondCode)X86Cond);
13853 if (CondOpcode == ISD::UMULO)
13854 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
13857 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
13859 SDValue X86Op = DAG.getNode(X86Opcode, dl, VTs, LHS, RHS);
13861 if (CondOpcode == ISD::UMULO)
13862 Cond = X86Op.getValue(2);
13864 Cond = X86Op.getValue(1);
13866 CC = DAG.getConstant(X86Cond, MVT::i8);
13870 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
13871 SDValue Cmp = Cond.getOperand(0).getOperand(1);
13872 if (CondOpc == ISD::OR) {
13873 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
13874 // two branches instead of an explicit OR instruction with a
13876 if (Cmp == Cond.getOperand(1).getOperand(1) &&
13877 isX86LogicalCmp(Cmp)) {
13878 CC = Cond.getOperand(0).getOperand(0);
13879 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
13880 Chain, Dest, CC, Cmp);
13881 CC = Cond.getOperand(1).getOperand(0);
13885 } else { // ISD::AND
13886 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
13887 // two branches instead of an explicit AND instruction with a
13888 // separate test. However, we only do this if this block doesn't
13889 // have a fall-through edge, because this requires an explicit
13890 // jmp when the condition is false.
13891 if (Cmp == Cond.getOperand(1).getOperand(1) &&
13892 isX86LogicalCmp(Cmp) &&
13893 Op.getNode()->hasOneUse()) {
13894 X86::CondCode CCode =
13895 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
13896 CCode = X86::GetOppositeBranchCondition(CCode);
13897 CC = DAG.getConstant(CCode, MVT::i8);
13898 SDNode *User = *Op.getNode()->use_begin();
13899 // Look for an unconditional branch following this conditional branch.
13900 // We need this because we need to reverse the successors in order
13901 // to implement FCMP_OEQ.
13902 if (User->getOpcode() == ISD::BR) {
13903 SDValue FalseBB = User->getOperand(1);
13905 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
13906 assert(NewBR == User);
13910 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
13911 Chain, Dest, CC, Cmp);
13912 X86::CondCode CCode =
13913 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
13914 CCode = X86::GetOppositeBranchCondition(CCode);
13915 CC = DAG.getConstant(CCode, MVT::i8);
13921 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
13922 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
13923 // It should be transformed during dag combiner except when the condition
13924 // is set by a arithmetics with overflow node.
13925 X86::CondCode CCode =
13926 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
13927 CCode = X86::GetOppositeBranchCondition(CCode);
13928 CC = DAG.getConstant(CCode, MVT::i8);
13929 Cond = Cond.getOperand(0).getOperand(1);
13931 } else if (Cond.getOpcode() == ISD::SETCC &&
13932 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETOEQ) {
13933 // For FCMP_OEQ, we can emit
13934 // two branches instead of an explicit AND instruction with a
13935 // separate test. However, we only do this if this block doesn't
13936 // have a fall-through edge, because this requires an explicit
13937 // jmp when the condition is false.
13938 if (Op.getNode()->hasOneUse()) {
13939 SDNode *User = *Op.getNode()->use_begin();
13940 // Look for an unconditional branch following this conditional branch.
13941 // We need this because we need to reverse the successors in order
13942 // to implement FCMP_OEQ.
13943 if (User->getOpcode() == ISD::BR) {
13944 SDValue FalseBB = User->getOperand(1);
13946 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
13947 assert(NewBR == User);
13951 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
13952 Cond.getOperand(0), Cond.getOperand(1));
13953 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
13954 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
13955 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
13956 Chain, Dest, CC, Cmp);
13957 CC = DAG.getConstant(X86::COND_P, MVT::i8);
13962 } else if (Cond.getOpcode() == ISD::SETCC &&
13963 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETUNE) {
13964 // For FCMP_UNE, we can emit
13965 // two branches instead of an explicit AND instruction with a
13966 // separate test. However, we only do this if this block doesn't
13967 // have a fall-through edge, because this requires an explicit
13968 // jmp when the condition is false.
13969 if (Op.getNode()->hasOneUse()) {
13970 SDNode *User = *Op.getNode()->use_begin();
13971 // Look for an unconditional branch following this conditional branch.
13972 // We need this because we need to reverse the successors in order
13973 // to implement FCMP_UNE.
13974 if (User->getOpcode() == ISD::BR) {
13975 SDValue FalseBB = User->getOperand(1);
13977 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
13978 assert(NewBR == User);
13981 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
13982 Cond.getOperand(0), Cond.getOperand(1));
13983 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
13984 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
13985 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
13986 Chain, Dest, CC, Cmp);
13987 CC = DAG.getConstant(X86::COND_NP, MVT::i8);
13997 // Look pass the truncate if the high bits are known zero.
13998 if (isTruncWithZeroHighBitsInput(Cond, DAG))
13999 Cond = Cond.getOperand(0);
14001 // We know the result of AND is compared against zero. Try to match
14003 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
14004 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
14005 if (NewSetCC.getNode()) {
14006 CC = NewSetCC.getOperand(0);
14007 Cond = NewSetCC.getOperand(1);
14014 X86::CondCode X86Cond = Inverted ? X86::COND_E : X86::COND_NE;
14015 CC = DAG.getConstant(X86Cond, MVT::i8);
14016 Cond = EmitTest(Cond, X86Cond, dl, DAG);
14018 Cond = ConvertCmpIfNecessary(Cond, DAG);
14019 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
14020 Chain, Dest, CC, Cond);
14023 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
14024 // Calls to _alloca are needed to probe the stack when allocating more than 4k
14025 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
14026 // that the guard pages used by the OS virtual memory manager are allocated in
14027 // correct sequence.
14029 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
14030 SelectionDAG &DAG) const {
14031 MachineFunction &MF = DAG.getMachineFunction();
14032 bool SplitStack = MF.shouldSplitStack();
14033 bool Lower = (Subtarget->isOSWindows() && !Subtarget->isTargetMacho()) ||
14038 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14039 SDNode* Node = Op.getNode();
14041 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
14042 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
14043 " not tell us which reg is the stack pointer!");
14044 EVT VT = Node->getValueType(0);
14045 SDValue Tmp1 = SDValue(Node, 0);
14046 SDValue Tmp2 = SDValue(Node, 1);
14047 SDValue Tmp3 = Node->getOperand(2);
14048 SDValue Chain = Tmp1.getOperand(0);
14050 // Chain the dynamic stack allocation so that it doesn't modify the stack
14051 // pointer when other instructions are using the stack.
14052 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true),
14055 SDValue Size = Tmp2.getOperand(1);
14056 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT);
14057 Chain = SP.getValue(1);
14058 unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue();
14059 const TargetFrameLowering &TFI = *DAG.getSubtarget().getFrameLowering();
14060 unsigned StackAlign = TFI.getStackAlignment();
14061 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value
14062 if (Align > StackAlign)
14063 Tmp1 = DAG.getNode(ISD::AND, dl, VT, Tmp1,
14064 DAG.getConstant(-(uint64_t)Align, VT));
14065 Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); // Output chain
14067 Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, true),
14068 DAG.getIntPtrConstant(0, true), SDValue(),
14071 SDValue Ops[2] = { Tmp1, Tmp2 };
14072 return DAG.getMergeValues(Ops, dl);
14076 SDValue Chain = Op.getOperand(0);
14077 SDValue Size = Op.getOperand(1);
14078 unsigned Align = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
14079 EVT VT = Op.getNode()->getValueType(0);
14081 bool Is64Bit = Subtarget->is64Bit();
14082 EVT SPTy = Is64Bit ? MVT::i64 : MVT::i32;
14085 MachineRegisterInfo &MRI = MF.getRegInfo();
14088 // The 64 bit implementation of segmented stacks needs to clobber both r10
14089 // r11. This makes it impossible to use it along with nested parameters.
14090 const Function *F = MF.getFunction();
14092 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
14094 if (I->hasNestAttr())
14095 report_fatal_error("Cannot use segmented stacks with functions that "
14096 "have nested arguments.");
14099 const TargetRegisterClass *AddrRegClass =
14100 getRegClassFor(Subtarget->is64Bit() ? MVT::i64:MVT::i32);
14101 unsigned Vreg = MRI.createVirtualRegister(AddrRegClass);
14102 Chain = DAG.getCopyToReg(Chain, dl, Vreg, Size);
14103 SDValue Value = DAG.getNode(X86ISD::SEG_ALLOCA, dl, SPTy, Chain,
14104 DAG.getRegister(Vreg, SPTy));
14105 SDValue Ops1[2] = { Value, Chain };
14106 return DAG.getMergeValues(Ops1, dl);
14109 unsigned Reg = (Subtarget->is64Bit() ? X86::RAX : X86::EAX);
14111 Chain = DAG.getCopyToReg(Chain, dl, Reg, Size, Flag);
14112 Flag = Chain.getValue(1);
14113 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
14115 Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag);
14117 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
14118 DAG.getSubtarget().getRegisterInfo());
14119 unsigned SPReg = RegInfo->getStackRegister();
14120 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, SPTy);
14121 Chain = SP.getValue(1);
14124 SP = DAG.getNode(ISD::AND, dl, VT, SP.getValue(0),
14125 DAG.getConstant(-(uint64_t)Align, VT));
14126 Chain = DAG.getCopyToReg(Chain, dl, SPReg, SP);
14129 SDValue Ops1[2] = { SP, Chain };
14130 return DAG.getMergeValues(Ops1, dl);
14134 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
14135 MachineFunction &MF = DAG.getMachineFunction();
14136 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
14138 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
14141 if (!Subtarget->is64Bit() || Subtarget->isTargetWin64()) {
14142 // vastart just stores the address of the VarArgsFrameIndex slot into the
14143 // memory location argument.
14144 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
14146 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
14147 MachinePointerInfo(SV), false, false, 0);
14151 // gp_offset (0 - 6 * 8)
14152 // fp_offset (48 - 48 + 8 * 16)
14153 // overflow_arg_area (point to parameters coming in memory).
14155 SmallVector<SDValue, 8> MemOps;
14156 SDValue FIN = Op.getOperand(1);
14158 SDValue Store = DAG.getStore(Op.getOperand(0), DL,
14159 DAG.getConstant(FuncInfo->getVarArgsGPOffset(),
14161 FIN, MachinePointerInfo(SV), false, false, 0);
14162 MemOps.push_back(Store);
14165 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
14166 FIN, DAG.getIntPtrConstant(4));
14167 Store = DAG.getStore(Op.getOperand(0), DL,
14168 DAG.getConstant(FuncInfo->getVarArgsFPOffset(),
14170 FIN, MachinePointerInfo(SV, 4), false, false, 0);
14171 MemOps.push_back(Store);
14173 // Store ptr to overflow_arg_area
14174 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
14175 FIN, DAG.getIntPtrConstant(4));
14176 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
14178 Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN,
14179 MachinePointerInfo(SV, 8),
14181 MemOps.push_back(Store);
14183 // Store ptr to reg_save_area.
14184 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
14185 FIN, DAG.getIntPtrConstant(8));
14186 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
14188 Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN,
14189 MachinePointerInfo(SV, 16), false, false, 0);
14190 MemOps.push_back(Store);
14191 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps);
14194 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
14195 assert(Subtarget->is64Bit() &&
14196 "LowerVAARG only handles 64-bit va_arg!");
14197 assert((Subtarget->isTargetLinux() ||
14198 Subtarget->isTargetDarwin()) &&
14199 "Unhandled target in LowerVAARG");
14200 assert(Op.getNode()->getNumOperands() == 4);
14201 SDValue Chain = Op.getOperand(0);
14202 SDValue SrcPtr = Op.getOperand(1);
14203 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
14204 unsigned Align = Op.getConstantOperandVal(3);
14207 EVT ArgVT = Op.getNode()->getValueType(0);
14208 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
14209 uint32_t ArgSize = getDataLayout()->getTypeAllocSize(ArgTy);
14212 // Decide which area this value should be read from.
14213 // TODO: Implement the AMD64 ABI in its entirety. This simple
14214 // selection mechanism works only for the basic types.
14215 if (ArgVT == MVT::f80) {
14216 llvm_unreachable("va_arg for f80 not yet implemented");
14217 } else if (ArgVT.isFloatingPoint() && ArgSize <= 16 /*bytes*/) {
14218 ArgMode = 2; // Argument passed in XMM register. Use fp_offset.
14219 } else if (ArgVT.isInteger() && ArgSize <= 32 /*bytes*/) {
14220 ArgMode = 1; // Argument passed in GPR64 register(s). Use gp_offset.
14222 llvm_unreachable("Unhandled argument type in LowerVAARG");
14225 if (ArgMode == 2) {
14226 // Sanity Check: Make sure using fp_offset makes sense.
14227 assert(!DAG.getTarget().Options.UseSoftFloat &&
14228 !(DAG.getMachineFunction()
14229 .getFunction()->getAttributes()
14230 .hasAttribute(AttributeSet::FunctionIndex,
14231 Attribute::NoImplicitFloat)) &&
14232 Subtarget->hasSSE1());
14235 // Insert VAARG_64 node into the DAG
14236 // VAARG_64 returns two values: Variable Argument Address, Chain
14237 SmallVector<SDValue, 11> InstOps;
14238 InstOps.push_back(Chain);
14239 InstOps.push_back(SrcPtr);
14240 InstOps.push_back(DAG.getConstant(ArgSize, MVT::i32));
14241 InstOps.push_back(DAG.getConstant(ArgMode, MVT::i8));
14242 InstOps.push_back(DAG.getConstant(Align, MVT::i32));
14243 SDVTList VTs = DAG.getVTList(getPointerTy(), MVT::Other);
14244 SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl,
14245 VTs, InstOps, MVT::i64,
14246 MachinePointerInfo(SV),
14248 /*Volatile=*/false,
14250 /*WriteMem=*/true);
14251 Chain = VAARG.getValue(1);
14253 // Load the next argument and return it
14254 return DAG.getLoad(ArgVT, dl,
14257 MachinePointerInfo(),
14258 false, false, false, 0);
14261 static SDValue LowerVACOPY(SDValue Op, const X86Subtarget *Subtarget,
14262 SelectionDAG &DAG) {
14263 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
14264 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
14265 SDValue Chain = Op.getOperand(0);
14266 SDValue DstPtr = Op.getOperand(1);
14267 SDValue SrcPtr = Op.getOperand(2);
14268 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
14269 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
14272 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr,
14273 DAG.getIntPtrConstant(24), 8, /*isVolatile*/false,
14275 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
14278 // getTargetVShiftByConstNode - Handle vector element shifts where the shift
14279 // amount is a constant. Takes immediate version of shift as input.
14280 static SDValue getTargetVShiftByConstNode(unsigned Opc, SDLoc dl, MVT VT,
14281 SDValue SrcOp, uint64_t ShiftAmt,
14282 SelectionDAG &DAG) {
14283 MVT ElementType = VT.getVectorElementType();
14285 // Fold this packed shift into its first operand if ShiftAmt is 0.
14289 // Check for ShiftAmt >= element width
14290 if (ShiftAmt >= ElementType.getSizeInBits()) {
14291 if (Opc == X86ISD::VSRAI)
14292 ShiftAmt = ElementType.getSizeInBits() - 1;
14294 return DAG.getConstant(0, VT);
14297 assert((Opc == X86ISD::VSHLI || Opc == X86ISD::VSRLI || Opc == X86ISD::VSRAI)
14298 && "Unknown target vector shift-by-constant node");
14300 // Fold this packed vector shift into a build vector if SrcOp is a
14301 // vector of Constants or UNDEFs, and SrcOp valuetype is the same as VT.
14302 if (VT == SrcOp.getSimpleValueType() &&
14303 ISD::isBuildVectorOfConstantSDNodes(SrcOp.getNode())) {
14304 SmallVector<SDValue, 8> Elts;
14305 unsigned NumElts = SrcOp->getNumOperands();
14306 ConstantSDNode *ND;
14309 default: llvm_unreachable(nullptr);
14310 case X86ISD::VSHLI:
14311 for (unsigned i=0; i!=NumElts; ++i) {
14312 SDValue CurrentOp = SrcOp->getOperand(i);
14313 if (CurrentOp->getOpcode() == ISD::UNDEF) {
14314 Elts.push_back(CurrentOp);
14317 ND = cast<ConstantSDNode>(CurrentOp);
14318 const APInt &C = ND->getAPIntValue();
14319 Elts.push_back(DAG.getConstant(C.shl(ShiftAmt), ElementType));
14322 case X86ISD::VSRLI:
14323 for (unsigned i=0; i!=NumElts; ++i) {
14324 SDValue CurrentOp = SrcOp->getOperand(i);
14325 if (CurrentOp->getOpcode() == ISD::UNDEF) {
14326 Elts.push_back(CurrentOp);
14329 ND = cast<ConstantSDNode>(CurrentOp);
14330 const APInt &C = ND->getAPIntValue();
14331 Elts.push_back(DAG.getConstant(C.lshr(ShiftAmt), ElementType));
14334 case X86ISD::VSRAI:
14335 for (unsigned i=0; i!=NumElts; ++i) {
14336 SDValue CurrentOp = SrcOp->getOperand(i);
14337 if (CurrentOp->getOpcode() == ISD::UNDEF) {
14338 Elts.push_back(CurrentOp);
14341 ND = cast<ConstantSDNode>(CurrentOp);
14342 const APInt &C = ND->getAPIntValue();
14343 Elts.push_back(DAG.getConstant(C.ashr(ShiftAmt), ElementType));
14348 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
14351 return DAG.getNode(Opc, dl, VT, SrcOp, DAG.getConstant(ShiftAmt, MVT::i8));
14354 // getTargetVShiftNode - Handle vector element shifts where the shift amount
14355 // may or may not be a constant. Takes immediate version of shift as input.
14356 static SDValue getTargetVShiftNode(unsigned Opc, SDLoc dl, MVT VT,
14357 SDValue SrcOp, SDValue ShAmt,
14358 SelectionDAG &DAG) {
14359 assert(ShAmt.getValueType() == MVT::i32 && "ShAmt is not i32");
14361 // Catch shift-by-constant.
14362 if (ConstantSDNode *CShAmt = dyn_cast<ConstantSDNode>(ShAmt))
14363 return getTargetVShiftByConstNode(Opc, dl, VT, SrcOp,
14364 CShAmt->getZExtValue(), DAG);
14366 // Change opcode to non-immediate version
14368 default: llvm_unreachable("Unknown target vector shift node");
14369 case X86ISD::VSHLI: Opc = X86ISD::VSHL; break;
14370 case X86ISD::VSRLI: Opc = X86ISD::VSRL; break;
14371 case X86ISD::VSRAI: Opc = X86ISD::VSRA; break;
14374 // Need to build a vector containing shift amount
14375 // Shift amount is 32-bits, but SSE instructions read 64-bit, so fill with 0
14378 ShOps[1] = DAG.getConstant(0, MVT::i32);
14379 ShOps[2] = ShOps[3] = DAG.getUNDEF(MVT::i32);
14380 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, ShOps);
14382 // The return type has to be a 128-bit type with the same element
14383 // type as the input type.
14384 MVT EltVT = VT.getVectorElementType();
14385 EVT ShVT = MVT::getVectorVT(EltVT, 128/EltVT.getSizeInBits());
14387 ShAmt = DAG.getNode(ISD::BITCAST, dl, ShVT, ShAmt);
14388 return DAG.getNode(Opc, dl, VT, SrcOp, ShAmt);
14391 /// \brief Return (vselect \p Mask, \p Op, \p PreservedSrc) along with the
14392 /// necessary casting for \p Mask when lowering masking intrinsics.
14393 static SDValue getVectorMaskingNode(SDValue Op, SDValue Mask,
14394 SDValue PreservedSrc, SelectionDAG &DAG) {
14395 EVT VT = Op.getValueType();
14396 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(),
14397 MVT::i1, VT.getVectorNumElements());
14400 assert(MaskVT.isSimple() && "invalid mask type");
14401 return DAG.getNode(ISD::VSELECT, dl, VT,
14402 DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask),
14406 static unsigned getOpcodeForFMAIntrinsic(unsigned IntNo) {
14408 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
14409 case Intrinsic::x86_fma_vfmadd_ps:
14410 case Intrinsic::x86_fma_vfmadd_pd:
14411 case Intrinsic::x86_fma_vfmadd_ps_256:
14412 case Intrinsic::x86_fma_vfmadd_pd_256:
14413 case Intrinsic::x86_fma_mask_vfmadd_ps_512:
14414 case Intrinsic::x86_fma_mask_vfmadd_pd_512:
14415 return X86ISD::FMADD;
14416 case Intrinsic::x86_fma_vfmsub_ps:
14417 case Intrinsic::x86_fma_vfmsub_pd:
14418 case Intrinsic::x86_fma_vfmsub_ps_256:
14419 case Intrinsic::x86_fma_vfmsub_pd_256:
14420 case Intrinsic::x86_fma_mask_vfmsub_ps_512:
14421 case Intrinsic::x86_fma_mask_vfmsub_pd_512:
14422 return X86ISD::FMSUB;
14423 case Intrinsic::x86_fma_vfnmadd_ps:
14424 case Intrinsic::x86_fma_vfnmadd_pd:
14425 case Intrinsic::x86_fma_vfnmadd_ps_256:
14426 case Intrinsic::x86_fma_vfnmadd_pd_256:
14427 case Intrinsic::x86_fma_mask_vfnmadd_ps_512:
14428 case Intrinsic::x86_fma_mask_vfnmadd_pd_512:
14429 return X86ISD::FNMADD;
14430 case Intrinsic::x86_fma_vfnmsub_ps:
14431 case Intrinsic::x86_fma_vfnmsub_pd:
14432 case Intrinsic::x86_fma_vfnmsub_ps_256:
14433 case Intrinsic::x86_fma_vfnmsub_pd_256:
14434 case Intrinsic::x86_fma_mask_vfnmsub_ps_512:
14435 case Intrinsic::x86_fma_mask_vfnmsub_pd_512:
14436 return X86ISD::FNMSUB;
14437 case Intrinsic::x86_fma_vfmaddsub_ps:
14438 case Intrinsic::x86_fma_vfmaddsub_pd:
14439 case Intrinsic::x86_fma_vfmaddsub_ps_256:
14440 case Intrinsic::x86_fma_vfmaddsub_pd_256:
14441 case Intrinsic::x86_fma_mask_vfmaddsub_ps_512:
14442 case Intrinsic::x86_fma_mask_vfmaddsub_pd_512:
14443 return X86ISD::FMADDSUB;
14444 case Intrinsic::x86_fma_vfmsubadd_ps:
14445 case Intrinsic::x86_fma_vfmsubadd_pd:
14446 case Intrinsic::x86_fma_vfmsubadd_ps_256:
14447 case Intrinsic::x86_fma_vfmsubadd_pd_256:
14448 case Intrinsic::x86_fma_mask_vfmsubadd_ps_512:
14449 case Intrinsic::x86_fma_mask_vfmsubadd_pd_512:
14450 return X86ISD::FMSUBADD;
14454 static SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) {
14456 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
14458 default: return SDValue(); // Don't custom lower most intrinsics.
14459 // Comparison intrinsics.
14460 case Intrinsic::x86_sse_comieq_ss:
14461 case Intrinsic::x86_sse_comilt_ss:
14462 case Intrinsic::x86_sse_comile_ss:
14463 case Intrinsic::x86_sse_comigt_ss:
14464 case Intrinsic::x86_sse_comige_ss:
14465 case Intrinsic::x86_sse_comineq_ss:
14466 case Intrinsic::x86_sse_ucomieq_ss:
14467 case Intrinsic::x86_sse_ucomilt_ss:
14468 case Intrinsic::x86_sse_ucomile_ss:
14469 case Intrinsic::x86_sse_ucomigt_ss:
14470 case Intrinsic::x86_sse_ucomige_ss:
14471 case Intrinsic::x86_sse_ucomineq_ss:
14472 case Intrinsic::x86_sse2_comieq_sd:
14473 case Intrinsic::x86_sse2_comilt_sd:
14474 case Intrinsic::x86_sse2_comile_sd:
14475 case Intrinsic::x86_sse2_comigt_sd:
14476 case Intrinsic::x86_sse2_comige_sd:
14477 case Intrinsic::x86_sse2_comineq_sd:
14478 case Intrinsic::x86_sse2_ucomieq_sd:
14479 case Intrinsic::x86_sse2_ucomilt_sd:
14480 case Intrinsic::x86_sse2_ucomile_sd:
14481 case Intrinsic::x86_sse2_ucomigt_sd:
14482 case Intrinsic::x86_sse2_ucomige_sd:
14483 case Intrinsic::x86_sse2_ucomineq_sd: {
14487 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
14488 case Intrinsic::x86_sse_comieq_ss:
14489 case Intrinsic::x86_sse2_comieq_sd:
14490 Opc = X86ISD::COMI;
14493 case Intrinsic::x86_sse_comilt_ss:
14494 case Intrinsic::x86_sse2_comilt_sd:
14495 Opc = X86ISD::COMI;
14498 case Intrinsic::x86_sse_comile_ss:
14499 case Intrinsic::x86_sse2_comile_sd:
14500 Opc = X86ISD::COMI;
14503 case Intrinsic::x86_sse_comigt_ss:
14504 case Intrinsic::x86_sse2_comigt_sd:
14505 Opc = X86ISD::COMI;
14508 case Intrinsic::x86_sse_comige_ss:
14509 case Intrinsic::x86_sse2_comige_sd:
14510 Opc = X86ISD::COMI;
14513 case Intrinsic::x86_sse_comineq_ss:
14514 case Intrinsic::x86_sse2_comineq_sd:
14515 Opc = X86ISD::COMI;
14518 case Intrinsic::x86_sse_ucomieq_ss:
14519 case Intrinsic::x86_sse2_ucomieq_sd:
14520 Opc = X86ISD::UCOMI;
14523 case Intrinsic::x86_sse_ucomilt_ss:
14524 case Intrinsic::x86_sse2_ucomilt_sd:
14525 Opc = X86ISD::UCOMI;
14528 case Intrinsic::x86_sse_ucomile_ss:
14529 case Intrinsic::x86_sse2_ucomile_sd:
14530 Opc = X86ISD::UCOMI;
14533 case Intrinsic::x86_sse_ucomigt_ss:
14534 case Intrinsic::x86_sse2_ucomigt_sd:
14535 Opc = X86ISD::UCOMI;
14538 case Intrinsic::x86_sse_ucomige_ss:
14539 case Intrinsic::x86_sse2_ucomige_sd:
14540 Opc = X86ISD::UCOMI;
14543 case Intrinsic::x86_sse_ucomineq_ss:
14544 case Intrinsic::x86_sse2_ucomineq_sd:
14545 Opc = X86ISD::UCOMI;
14550 SDValue LHS = Op.getOperand(1);
14551 SDValue RHS = Op.getOperand(2);
14552 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG);
14553 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!");
14554 SDValue Cond = DAG.getNode(Opc, dl, MVT::i32, LHS, RHS);
14555 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
14556 DAG.getConstant(X86CC, MVT::i8), Cond);
14557 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
14560 // Arithmetic intrinsics.
14561 case Intrinsic::x86_sse2_pmulu_dq:
14562 case Intrinsic::x86_avx2_pmulu_dq:
14563 return DAG.getNode(X86ISD::PMULUDQ, dl, Op.getValueType(),
14564 Op.getOperand(1), Op.getOperand(2));
14566 case Intrinsic::x86_sse41_pmuldq:
14567 case Intrinsic::x86_avx2_pmul_dq:
14568 return DAG.getNode(X86ISD::PMULDQ, dl, Op.getValueType(),
14569 Op.getOperand(1), Op.getOperand(2));
14571 case Intrinsic::x86_sse2_pmulhu_w:
14572 case Intrinsic::x86_avx2_pmulhu_w:
14573 return DAG.getNode(ISD::MULHU, dl, Op.getValueType(),
14574 Op.getOperand(1), Op.getOperand(2));
14576 case Intrinsic::x86_sse2_pmulh_w:
14577 case Intrinsic::x86_avx2_pmulh_w:
14578 return DAG.getNode(ISD::MULHS, dl, Op.getValueType(),
14579 Op.getOperand(1), Op.getOperand(2));
14581 // SSE2/AVX2 sub with unsigned saturation intrinsics
14582 case Intrinsic::x86_sse2_psubus_b:
14583 case Intrinsic::x86_sse2_psubus_w:
14584 case Intrinsic::x86_avx2_psubus_b:
14585 case Intrinsic::x86_avx2_psubus_w:
14586 return DAG.getNode(X86ISD::SUBUS, dl, Op.getValueType(),
14587 Op.getOperand(1), Op.getOperand(2));
14589 // SSE3/AVX horizontal add/sub intrinsics
14590 case Intrinsic::x86_sse3_hadd_ps:
14591 case Intrinsic::x86_sse3_hadd_pd:
14592 case Intrinsic::x86_avx_hadd_ps_256:
14593 case Intrinsic::x86_avx_hadd_pd_256:
14594 case Intrinsic::x86_sse3_hsub_ps:
14595 case Intrinsic::x86_sse3_hsub_pd:
14596 case Intrinsic::x86_avx_hsub_ps_256:
14597 case Intrinsic::x86_avx_hsub_pd_256:
14598 case Intrinsic::x86_ssse3_phadd_w_128:
14599 case Intrinsic::x86_ssse3_phadd_d_128:
14600 case Intrinsic::x86_avx2_phadd_w:
14601 case Intrinsic::x86_avx2_phadd_d:
14602 case Intrinsic::x86_ssse3_phsub_w_128:
14603 case Intrinsic::x86_ssse3_phsub_d_128:
14604 case Intrinsic::x86_avx2_phsub_w:
14605 case Intrinsic::x86_avx2_phsub_d: {
14608 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
14609 case Intrinsic::x86_sse3_hadd_ps:
14610 case Intrinsic::x86_sse3_hadd_pd:
14611 case Intrinsic::x86_avx_hadd_ps_256:
14612 case Intrinsic::x86_avx_hadd_pd_256:
14613 Opcode = X86ISD::FHADD;
14615 case Intrinsic::x86_sse3_hsub_ps:
14616 case Intrinsic::x86_sse3_hsub_pd:
14617 case Intrinsic::x86_avx_hsub_ps_256:
14618 case Intrinsic::x86_avx_hsub_pd_256:
14619 Opcode = X86ISD::FHSUB;
14621 case Intrinsic::x86_ssse3_phadd_w_128:
14622 case Intrinsic::x86_ssse3_phadd_d_128:
14623 case Intrinsic::x86_avx2_phadd_w:
14624 case Intrinsic::x86_avx2_phadd_d:
14625 Opcode = X86ISD::HADD;
14627 case Intrinsic::x86_ssse3_phsub_w_128:
14628 case Intrinsic::x86_ssse3_phsub_d_128:
14629 case Intrinsic::x86_avx2_phsub_w:
14630 case Intrinsic::x86_avx2_phsub_d:
14631 Opcode = X86ISD::HSUB;
14634 return DAG.getNode(Opcode, dl, Op.getValueType(),
14635 Op.getOperand(1), Op.getOperand(2));
14638 // SSE2/SSE41/AVX2 integer max/min intrinsics.
14639 case Intrinsic::x86_sse2_pmaxu_b:
14640 case Intrinsic::x86_sse41_pmaxuw:
14641 case Intrinsic::x86_sse41_pmaxud:
14642 case Intrinsic::x86_avx2_pmaxu_b:
14643 case Intrinsic::x86_avx2_pmaxu_w:
14644 case Intrinsic::x86_avx2_pmaxu_d:
14645 case Intrinsic::x86_sse2_pminu_b:
14646 case Intrinsic::x86_sse41_pminuw:
14647 case Intrinsic::x86_sse41_pminud:
14648 case Intrinsic::x86_avx2_pminu_b:
14649 case Intrinsic::x86_avx2_pminu_w:
14650 case Intrinsic::x86_avx2_pminu_d:
14651 case Intrinsic::x86_sse41_pmaxsb:
14652 case Intrinsic::x86_sse2_pmaxs_w:
14653 case Intrinsic::x86_sse41_pmaxsd:
14654 case Intrinsic::x86_avx2_pmaxs_b:
14655 case Intrinsic::x86_avx2_pmaxs_w:
14656 case Intrinsic::x86_avx2_pmaxs_d:
14657 case Intrinsic::x86_sse41_pminsb:
14658 case Intrinsic::x86_sse2_pmins_w:
14659 case Intrinsic::x86_sse41_pminsd:
14660 case Intrinsic::x86_avx2_pmins_b:
14661 case Intrinsic::x86_avx2_pmins_w:
14662 case Intrinsic::x86_avx2_pmins_d: {
14665 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
14666 case Intrinsic::x86_sse2_pmaxu_b:
14667 case Intrinsic::x86_sse41_pmaxuw:
14668 case Intrinsic::x86_sse41_pmaxud:
14669 case Intrinsic::x86_avx2_pmaxu_b:
14670 case Intrinsic::x86_avx2_pmaxu_w:
14671 case Intrinsic::x86_avx2_pmaxu_d:
14672 Opcode = X86ISD::UMAX;
14674 case Intrinsic::x86_sse2_pminu_b:
14675 case Intrinsic::x86_sse41_pminuw:
14676 case Intrinsic::x86_sse41_pminud:
14677 case Intrinsic::x86_avx2_pminu_b:
14678 case Intrinsic::x86_avx2_pminu_w:
14679 case Intrinsic::x86_avx2_pminu_d:
14680 Opcode = X86ISD::UMIN;
14682 case Intrinsic::x86_sse41_pmaxsb:
14683 case Intrinsic::x86_sse2_pmaxs_w:
14684 case Intrinsic::x86_sse41_pmaxsd:
14685 case Intrinsic::x86_avx2_pmaxs_b:
14686 case Intrinsic::x86_avx2_pmaxs_w:
14687 case Intrinsic::x86_avx2_pmaxs_d:
14688 Opcode = X86ISD::SMAX;
14690 case Intrinsic::x86_sse41_pminsb:
14691 case Intrinsic::x86_sse2_pmins_w:
14692 case Intrinsic::x86_sse41_pminsd:
14693 case Intrinsic::x86_avx2_pmins_b:
14694 case Intrinsic::x86_avx2_pmins_w:
14695 case Intrinsic::x86_avx2_pmins_d:
14696 Opcode = X86ISD::SMIN;
14699 return DAG.getNode(Opcode, dl, Op.getValueType(),
14700 Op.getOperand(1), Op.getOperand(2));
14703 // SSE/SSE2/AVX floating point max/min intrinsics.
14704 case Intrinsic::x86_sse_max_ps:
14705 case Intrinsic::x86_sse2_max_pd:
14706 case Intrinsic::x86_avx_max_ps_256:
14707 case Intrinsic::x86_avx_max_pd_256:
14708 case Intrinsic::x86_sse_min_ps:
14709 case Intrinsic::x86_sse2_min_pd:
14710 case Intrinsic::x86_avx_min_ps_256:
14711 case Intrinsic::x86_avx_min_pd_256: {
14714 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
14715 case Intrinsic::x86_sse_max_ps:
14716 case Intrinsic::x86_sse2_max_pd:
14717 case Intrinsic::x86_avx_max_ps_256:
14718 case Intrinsic::x86_avx_max_pd_256:
14719 Opcode = X86ISD::FMAX;
14721 case Intrinsic::x86_sse_min_ps:
14722 case Intrinsic::x86_sse2_min_pd:
14723 case Intrinsic::x86_avx_min_ps_256:
14724 case Intrinsic::x86_avx_min_pd_256:
14725 Opcode = X86ISD::FMIN;
14728 return DAG.getNode(Opcode, dl, Op.getValueType(),
14729 Op.getOperand(1), Op.getOperand(2));
14732 // AVX2 variable shift intrinsics
14733 case Intrinsic::x86_avx2_psllv_d:
14734 case Intrinsic::x86_avx2_psllv_q:
14735 case Intrinsic::x86_avx2_psllv_d_256:
14736 case Intrinsic::x86_avx2_psllv_q_256:
14737 case Intrinsic::x86_avx2_psrlv_d:
14738 case Intrinsic::x86_avx2_psrlv_q:
14739 case Intrinsic::x86_avx2_psrlv_d_256:
14740 case Intrinsic::x86_avx2_psrlv_q_256:
14741 case Intrinsic::x86_avx2_psrav_d:
14742 case Intrinsic::x86_avx2_psrav_d_256: {
14745 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
14746 case Intrinsic::x86_avx2_psllv_d:
14747 case Intrinsic::x86_avx2_psllv_q:
14748 case Intrinsic::x86_avx2_psllv_d_256:
14749 case Intrinsic::x86_avx2_psllv_q_256:
14752 case Intrinsic::x86_avx2_psrlv_d:
14753 case Intrinsic::x86_avx2_psrlv_q:
14754 case Intrinsic::x86_avx2_psrlv_d_256:
14755 case Intrinsic::x86_avx2_psrlv_q_256:
14758 case Intrinsic::x86_avx2_psrav_d:
14759 case Intrinsic::x86_avx2_psrav_d_256:
14763 return DAG.getNode(Opcode, dl, Op.getValueType(),
14764 Op.getOperand(1), Op.getOperand(2));
14767 case Intrinsic::x86_sse2_packssdw_128:
14768 case Intrinsic::x86_sse2_packsswb_128:
14769 case Intrinsic::x86_avx2_packssdw:
14770 case Intrinsic::x86_avx2_packsswb:
14771 return DAG.getNode(X86ISD::PACKSS, dl, Op.getValueType(),
14772 Op.getOperand(1), Op.getOperand(2));
14774 case Intrinsic::x86_sse2_packuswb_128:
14775 case Intrinsic::x86_sse41_packusdw:
14776 case Intrinsic::x86_avx2_packuswb:
14777 case Intrinsic::x86_avx2_packusdw:
14778 return DAG.getNode(X86ISD::PACKUS, dl, Op.getValueType(),
14779 Op.getOperand(1), Op.getOperand(2));
14781 case Intrinsic::x86_ssse3_pshuf_b_128:
14782 case Intrinsic::x86_avx2_pshuf_b:
14783 return DAG.getNode(X86ISD::PSHUFB, dl, Op.getValueType(),
14784 Op.getOperand(1), Op.getOperand(2));
14786 case Intrinsic::x86_sse2_pshuf_d:
14787 return DAG.getNode(X86ISD::PSHUFD, dl, Op.getValueType(),
14788 Op.getOperand(1), Op.getOperand(2));
14790 case Intrinsic::x86_sse2_pshufl_w:
14791 return DAG.getNode(X86ISD::PSHUFLW, dl, Op.getValueType(),
14792 Op.getOperand(1), Op.getOperand(2));
14794 case Intrinsic::x86_sse2_pshufh_w:
14795 return DAG.getNode(X86ISD::PSHUFHW, dl, Op.getValueType(),
14796 Op.getOperand(1), Op.getOperand(2));
14798 case Intrinsic::x86_ssse3_psign_b_128:
14799 case Intrinsic::x86_ssse3_psign_w_128:
14800 case Intrinsic::x86_ssse3_psign_d_128:
14801 case Intrinsic::x86_avx2_psign_b:
14802 case Intrinsic::x86_avx2_psign_w:
14803 case Intrinsic::x86_avx2_psign_d:
14804 return DAG.getNode(X86ISD::PSIGN, dl, Op.getValueType(),
14805 Op.getOperand(1), Op.getOperand(2));
14807 case Intrinsic::x86_sse41_insertps:
14808 return DAG.getNode(X86ISD::INSERTPS, dl, Op.getValueType(),
14809 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
14811 case Intrinsic::x86_avx_vperm2f128_ps_256:
14812 case Intrinsic::x86_avx_vperm2f128_pd_256:
14813 case Intrinsic::x86_avx_vperm2f128_si_256:
14814 case Intrinsic::x86_avx2_vperm2i128:
14815 return DAG.getNode(X86ISD::VPERM2X128, dl, Op.getValueType(),
14816 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
14818 case Intrinsic::x86_avx2_permd:
14819 case Intrinsic::x86_avx2_permps:
14820 // Operands intentionally swapped. Mask is last operand to intrinsic,
14821 // but second operand for node/instruction.
14822 return DAG.getNode(X86ISD::VPERMV, dl, Op.getValueType(),
14823 Op.getOperand(2), Op.getOperand(1));
14825 case Intrinsic::x86_sse_sqrt_ps:
14826 case Intrinsic::x86_sse2_sqrt_pd:
14827 case Intrinsic::x86_avx_sqrt_ps_256:
14828 case Intrinsic::x86_avx_sqrt_pd_256:
14829 return DAG.getNode(ISD::FSQRT, dl, Op.getValueType(), Op.getOperand(1));
14831 case Intrinsic::x86_avx512_mask_valign_q_512:
14832 case Intrinsic::x86_avx512_mask_valign_d_512:
14833 // Vector source operands are swapped.
14834 return getVectorMaskingNode(DAG.getNode(X86ISD::VALIGN, dl,
14835 Op.getValueType(), Op.getOperand(2),
14838 Op.getOperand(5), Op.getOperand(4), DAG);
14840 // ptest and testp intrinsics. The intrinsic these come from are designed to
14841 // return an integer value, not just an instruction so lower it to the ptest
14842 // or testp pattern and a setcc for the result.
14843 case Intrinsic::x86_sse41_ptestz:
14844 case Intrinsic::x86_sse41_ptestc:
14845 case Intrinsic::x86_sse41_ptestnzc:
14846 case Intrinsic::x86_avx_ptestz_256:
14847 case Intrinsic::x86_avx_ptestc_256:
14848 case Intrinsic::x86_avx_ptestnzc_256:
14849 case Intrinsic::x86_avx_vtestz_ps:
14850 case Intrinsic::x86_avx_vtestc_ps:
14851 case Intrinsic::x86_avx_vtestnzc_ps:
14852 case Intrinsic::x86_avx_vtestz_pd:
14853 case Intrinsic::x86_avx_vtestc_pd:
14854 case Intrinsic::x86_avx_vtestnzc_pd:
14855 case Intrinsic::x86_avx_vtestz_ps_256:
14856 case Intrinsic::x86_avx_vtestc_ps_256:
14857 case Intrinsic::x86_avx_vtestnzc_ps_256:
14858 case Intrinsic::x86_avx_vtestz_pd_256:
14859 case Intrinsic::x86_avx_vtestc_pd_256:
14860 case Intrinsic::x86_avx_vtestnzc_pd_256: {
14861 bool IsTestPacked = false;
14864 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
14865 case Intrinsic::x86_avx_vtestz_ps:
14866 case Intrinsic::x86_avx_vtestz_pd:
14867 case Intrinsic::x86_avx_vtestz_ps_256:
14868 case Intrinsic::x86_avx_vtestz_pd_256:
14869 IsTestPacked = true; // Fallthrough
14870 case Intrinsic::x86_sse41_ptestz:
14871 case Intrinsic::x86_avx_ptestz_256:
14873 X86CC = X86::COND_E;
14875 case Intrinsic::x86_avx_vtestc_ps:
14876 case Intrinsic::x86_avx_vtestc_pd:
14877 case Intrinsic::x86_avx_vtestc_ps_256:
14878 case Intrinsic::x86_avx_vtestc_pd_256:
14879 IsTestPacked = true; // Fallthrough
14880 case Intrinsic::x86_sse41_ptestc:
14881 case Intrinsic::x86_avx_ptestc_256:
14883 X86CC = X86::COND_B;
14885 case Intrinsic::x86_avx_vtestnzc_ps:
14886 case Intrinsic::x86_avx_vtestnzc_pd:
14887 case Intrinsic::x86_avx_vtestnzc_ps_256:
14888 case Intrinsic::x86_avx_vtestnzc_pd_256:
14889 IsTestPacked = true; // Fallthrough
14890 case Intrinsic::x86_sse41_ptestnzc:
14891 case Intrinsic::x86_avx_ptestnzc_256:
14893 X86CC = X86::COND_A;
14897 SDValue LHS = Op.getOperand(1);
14898 SDValue RHS = Op.getOperand(2);
14899 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST;
14900 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS);
14901 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
14902 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
14903 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
14905 case Intrinsic::x86_avx512_kortestz_w:
14906 case Intrinsic::x86_avx512_kortestc_w: {
14907 unsigned X86CC = (IntNo == Intrinsic::x86_avx512_kortestz_w)? X86::COND_E: X86::COND_B;
14908 SDValue LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1, Op.getOperand(1));
14909 SDValue RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1, Op.getOperand(2));
14910 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
14911 SDValue Test = DAG.getNode(X86ISD::KORTEST, dl, MVT::i32, LHS, RHS);
14912 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i1, CC, Test);
14913 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
14916 // SSE/AVX shift intrinsics
14917 case Intrinsic::x86_sse2_psll_w:
14918 case Intrinsic::x86_sse2_psll_d:
14919 case Intrinsic::x86_sse2_psll_q:
14920 case Intrinsic::x86_avx2_psll_w:
14921 case Intrinsic::x86_avx2_psll_d:
14922 case Intrinsic::x86_avx2_psll_q:
14923 case Intrinsic::x86_sse2_psrl_w:
14924 case Intrinsic::x86_sse2_psrl_d:
14925 case Intrinsic::x86_sse2_psrl_q:
14926 case Intrinsic::x86_avx2_psrl_w:
14927 case Intrinsic::x86_avx2_psrl_d:
14928 case Intrinsic::x86_avx2_psrl_q:
14929 case Intrinsic::x86_sse2_psra_w:
14930 case Intrinsic::x86_sse2_psra_d:
14931 case Intrinsic::x86_avx2_psra_w:
14932 case Intrinsic::x86_avx2_psra_d: {
14935 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
14936 case Intrinsic::x86_sse2_psll_w:
14937 case Intrinsic::x86_sse2_psll_d:
14938 case Intrinsic::x86_sse2_psll_q:
14939 case Intrinsic::x86_avx2_psll_w:
14940 case Intrinsic::x86_avx2_psll_d:
14941 case Intrinsic::x86_avx2_psll_q:
14942 Opcode = X86ISD::VSHL;
14944 case Intrinsic::x86_sse2_psrl_w:
14945 case Intrinsic::x86_sse2_psrl_d:
14946 case Intrinsic::x86_sse2_psrl_q:
14947 case Intrinsic::x86_avx2_psrl_w:
14948 case Intrinsic::x86_avx2_psrl_d:
14949 case Intrinsic::x86_avx2_psrl_q:
14950 Opcode = X86ISD::VSRL;
14952 case Intrinsic::x86_sse2_psra_w:
14953 case Intrinsic::x86_sse2_psra_d:
14954 case Intrinsic::x86_avx2_psra_w:
14955 case Intrinsic::x86_avx2_psra_d:
14956 Opcode = X86ISD::VSRA;
14959 return DAG.getNode(Opcode, dl, Op.getValueType(),
14960 Op.getOperand(1), Op.getOperand(2));
14963 // SSE/AVX immediate shift intrinsics
14964 case Intrinsic::x86_sse2_pslli_w:
14965 case Intrinsic::x86_sse2_pslli_d:
14966 case Intrinsic::x86_sse2_pslli_q:
14967 case Intrinsic::x86_avx2_pslli_w:
14968 case Intrinsic::x86_avx2_pslli_d:
14969 case Intrinsic::x86_avx2_pslli_q:
14970 case Intrinsic::x86_sse2_psrli_w:
14971 case Intrinsic::x86_sse2_psrli_d:
14972 case Intrinsic::x86_sse2_psrli_q:
14973 case Intrinsic::x86_avx2_psrli_w:
14974 case Intrinsic::x86_avx2_psrli_d:
14975 case Intrinsic::x86_avx2_psrli_q:
14976 case Intrinsic::x86_sse2_psrai_w:
14977 case Intrinsic::x86_sse2_psrai_d:
14978 case Intrinsic::x86_avx2_psrai_w:
14979 case Intrinsic::x86_avx2_psrai_d: {
14982 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
14983 case Intrinsic::x86_sse2_pslli_w:
14984 case Intrinsic::x86_sse2_pslli_d:
14985 case Intrinsic::x86_sse2_pslli_q:
14986 case Intrinsic::x86_avx2_pslli_w:
14987 case Intrinsic::x86_avx2_pslli_d:
14988 case Intrinsic::x86_avx2_pslli_q:
14989 Opcode = X86ISD::VSHLI;
14991 case Intrinsic::x86_sse2_psrli_w:
14992 case Intrinsic::x86_sse2_psrli_d:
14993 case Intrinsic::x86_sse2_psrli_q:
14994 case Intrinsic::x86_avx2_psrli_w:
14995 case Intrinsic::x86_avx2_psrli_d:
14996 case Intrinsic::x86_avx2_psrli_q:
14997 Opcode = X86ISD::VSRLI;
14999 case Intrinsic::x86_sse2_psrai_w:
15000 case Intrinsic::x86_sse2_psrai_d:
15001 case Intrinsic::x86_avx2_psrai_w:
15002 case Intrinsic::x86_avx2_psrai_d:
15003 Opcode = X86ISD::VSRAI;
15006 return getTargetVShiftNode(Opcode, dl, Op.getSimpleValueType(),
15007 Op.getOperand(1), Op.getOperand(2), DAG);
15010 case Intrinsic::x86_sse42_pcmpistria128:
15011 case Intrinsic::x86_sse42_pcmpestria128:
15012 case Intrinsic::x86_sse42_pcmpistric128:
15013 case Intrinsic::x86_sse42_pcmpestric128:
15014 case Intrinsic::x86_sse42_pcmpistrio128:
15015 case Intrinsic::x86_sse42_pcmpestrio128:
15016 case Intrinsic::x86_sse42_pcmpistris128:
15017 case Intrinsic::x86_sse42_pcmpestris128:
15018 case Intrinsic::x86_sse42_pcmpistriz128:
15019 case Intrinsic::x86_sse42_pcmpestriz128: {
15023 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
15024 case Intrinsic::x86_sse42_pcmpistria128:
15025 Opcode = X86ISD::PCMPISTRI;
15026 X86CC = X86::COND_A;
15028 case Intrinsic::x86_sse42_pcmpestria128:
15029 Opcode = X86ISD::PCMPESTRI;
15030 X86CC = X86::COND_A;
15032 case Intrinsic::x86_sse42_pcmpistric128:
15033 Opcode = X86ISD::PCMPISTRI;
15034 X86CC = X86::COND_B;
15036 case Intrinsic::x86_sse42_pcmpestric128:
15037 Opcode = X86ISD::PCMPESTRI;
15038 X86CC = X86::COND_B;
15040 case Intrinsic::x86_sse42_pcmpistrio128:
15041 Opcode = X86ISD::PCMPISTRI;
15042 X86CC = X86::COND_O;
15044 case Intrinsic::x86_sse42_pcmpestrio128:
15045 Opcode = X86ISD::PCMPESTRI;
15046 X86CC = X86::COND_O;
15048 case Intrinsic::x86_sse42_pcmpistris128:
15049 Opcode = X86ISD::PCMPISTRI;
15050 X86CC = X86::COND_S;
15052 case Intrinsic::x86_sse42_pcmpestris128:
15053 Opcode = X86ISD::PCMPESTRI;
15054 X86CC = X86::COND_S;
15056 case Intrinsic::x86_sse42_pcmpistriz128:
15057 Opcode = X86ISD::PCMPISTRI;
15058 X86CC = X86::COND_E;
15060 case Intrinsic::x86_sse42_pcmpestriz128:
15061 Opcode = X86ISD::PCMPESTRI;
15062 X86CC = X86::COND_E;
15065 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
15066 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
15067 SDValue PCMP = DAG.getNode(Opcode, dl, VTs, NewOps);
15068 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
15069 DAG.getConstant(X86CC, MVT::i8),
15070 SDValue(PCMP.getNode(), 1));
15071 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
15074 case Intrinsic::x86_sse42_pcmpistri128:
15075 case Intrinsic::x86_sse42_pcmpestri128: {
15077 if (IntNo == Intrinsic::x86_sse42_pcmpistri128)
15078 Opcode = X86ISD::PCMPISTRI;
15080 Opcode = X86ISD::PCMPESTRI;
15082 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
15083 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
15084 return DAG.getNode(Opcode, dl, VTs, NewOps);
15087 case Intrinsic::x86_fma_mask_vfmadd_ps_512:
15088 case Intrinsic::x86_fma_mask_vfmadd_pd_512:
15089 case Intrinsic::x86_fma_mask_vfmsub_ps_512:
15090 case Intrinsic::x86_fma_mask_vfmsub_pd_512:
15091 case Intrinsic::x86_fma_mask_vfnmadd_ps_512:
15092 case Intrinsic::x86_fma_mask_vfnmadd_pd_512:
15093 case Intrinsic::x86_fma_mask_vfnmsub_ps_512:
15094 case Intrinsic::x86_fma_mask_vfnmsub_pd_512:
15095 case Intrinsic::x86_fma_mask_vfmaddsub_ps_512:
15096 case Intrinsic::x86_fma_mask_vfmaddsub_pd_512:
15097 case Intrinsic::x86_fma_mask_vfmsubadd_ps_512:
15098 case Intrinsic::x86_fma_mask_vfmsubadd_pd_512: {
15099 auto *SAE = cast<ConstantSDNode>(Op.getOperand(5));
15100 if (SAE->getZExtValue() == X86::STATIC_ROUNDING::CUR_DIRECTION)
15101 return getVectorMaskingNode(DAG.getNode(getOpcodeForFMAIntrinsic(IntNo),
15102 dl, Op.getValueType(),
15106 Op.getOperand(4), Op.getOperand(1), DAG);
15111 case Intrinsic::x86_fma_vfmadd_ps:
15112 case Intrinsic::x86_fma_vfmadd_pd:
15113 case Intrinsic::x86_fma_vfmsub_ps:
15114 case Intrinsic::x86_fma_vfmsub_pd:
15115 case Intrinsic::x86_fma_vfnmadd_ps:
15116 case Intrinsic::x86_fma_vfnmadd_pd:
15117 case Intrinsic::x86_fma_vfnmsub_ps:
15118 case Intrinsic::x86_fma_vfnmsub_pd:
15119 case Intrinsic::x86_fma_vfmaddsub_ps:
15120 case Intrinsic::x86_fma_vfmaddsub_pd:
15121 case Intrinsic::x86_fma_vfmsubadd_ps:
15122 case Intrinsic::x86_fma_vfmsubadd_pd:
15123 case Intrinsic::x86_fma_vfmadd_ps_256:
15124 case Intrinsic::x86_fma_vfmadd_pd_256:
15125 case Intrinsic::x86_fma_vfmsub_ps_256:
15126 case Intrinsic::x86_fma_vfmsub_pd_256:
15127 case Intrinsic::x86_fma_vfnmadd_ps_256:
15128 case Intrinsic::x86_fma_vfnmadd_pd_256:
15129 case Intrinsic::x86_fma_vfnmsub_ps_256:
15130 case Intrinsic::x86_fma_vfnmsub_pd_256:
15131 case Intrinsic::x86_fma_vfmaddsub_ps_256:
15132 case Intrinsic::x86_fma_vfmaddsub_pd_256:
15133 case Intrinsic::x86_fma_vfmsubadd_ps_256:
15134 case Intrinsic::x86_fma_vfmsubadd_pd_256:
15135 return DAG.getNode(getOpcodeForFMAIntrinsic(IntNo), dl, Op.getValueType(),
15136 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
15140 static SDValue getGatherNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
15141 SDValue Src, SDValue Mask, SDValue Base,
15142 SDValue Index, SDValue ScaleOp, SDValue Chain,
15143 const X86Subtarget * Subtarget) {
15145 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
15146 assert(C && "Invalid scale type");
15147 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
15148 EVT MaskVT = MVT::getVectorVT(MVT::i1,
15149 Index.getSimpleValueType().getVectorNumElements());
15151 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
15153 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), MaskVT);
15155 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
15156 SDVTList VTs = DAG.getVTList(Op.getValueType(), MaskVT, MVT::Other);
15157 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
15158 SDValue Segment = DAG.getRegister(0, MVT::i32);
15159 if (Src.getOpcode() == ISD::UNDEF)
15160 Src = getZeroVector(Op.getValueType(), Subtarget, DAG, dl);
15161 SDValue Ops[] = {Src, MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
15162 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
15163 SDValue RetOps[] = { SDValue(Res, 0), SDValue(Res, 2) };
15164 return DAG.getMergeValues(RetOps, dl);
15167 static SDValue getScatterNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
15168 SDValue Src, SDValue Mask, SDValue Base,
15169 SDValue Index, SDValue ScaleOp, SDValue Chain) {
15171 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
15172 assert(C && "Invalid scale type");
15173 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
15174 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
15175 SDValue Segment = DAG.getRegister(0, MVT::i32);
15176 EVT MaskVT = MVT::getVectorVT(MVT::i1,
15177 Index.getSimpleValueType().getVectorNumElements());
15179 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
15181 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), MaskVT);
15183 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
15184 SDVTList VTs = DAG.getVTList(MaskVT, MVT::Other);
15185 SDValue Ops[] = {Base, Scale, Index, Disp, Segment, MaskInReg, Src, Chain};
15186 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
15187 return SDValue(Res, 1);
15190 static SDValue getPrefetchNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
15191 SDValue Mask, SDValue Base, SDValue Index,
15192 SDValue ScaleOp, SDValue Chain) {
15194 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
15195 assert(C && "Invalid scale type");
15196 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
15197 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
15198 SDValue Segment = DAG.getRegister(0, MVT::i32);
15200 MVT::getVectorVT(MVT::i1, Index.getSimpleValueType().getVectorNumElements());
15202 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
15204 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), MaskVT);
15206 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
15207 //SDVTList VTs = DAG.getVTList(MVT::Other);
15208 SDValue Ops[] = {MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
15209 SDNode *Res = DAG.getMachineNode(Opc, dl, MVT::Other, Ops);
15210 return SDValue(Res, 0);
15213 // getReadPerformanceCounter - Handles the lowering of builtin intrinsics that
15214 // read performance monitor counters (x86_rdpmc).
15215 static void getReadPerformanceCounter(SDNode *N, SDLoc DL,
15216 SelectionDAG &DAG, const X86Subtarget *Subtarget,
15217 SmallVectorImpl<SDValue> &Results) {
15218 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
15219 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
15222 // The ECX register is used to select the index of the performance counter
15224 SDValue Chain = DAG.getCopyToReg(N->getOperand(0), DL, X86::ECX,
15226 SDValue rd = DAG.getNode(X86ISD::RDPMC_DAG, DL, Tys, Chain);
15228 // Reads the content of a 64-bit performance counter and returns it in the
15229 // registers EDX:EAX.
15230 if (Subtarget->is64Bit()) {
15231 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
15232 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
15235 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
15236 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
15239 Chain = HI.getValue(1);
15241 if (Subtarget->is64Bit()) {
15242 // The EAX register is loaded with the low-order 32 bits. The EDX register
15243 // is loaded with the supported high-order bits of the counter.
15244 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
15245 DAG.getConstant(32, MVT::i8));
15246 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
15247 Results.push_back(Chain);
15251 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
15252 SDValue Ops[] = { LO, HI };
15253 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
15254 Results.push_back(Pair);
15255 Results.push_back(Chain);
15258 // getReadTimeStampCounter - Handles the lowering of builtin intrinsics that
15259 // read the time stamp counter (x86_rdtsc and x86_rdtscp). This function is
15260 // also used to custom lower READCYCLECOUNTER nodes.
15261 static void getReadTimeStampCounter(SDNode *N, SDLoc DL, unsigned Opcode,
15262 SelectionDAG &DAG, const X86Subtarget *Subtarget,
15263 SmallVectorImpl<SDValue> &Results) {
15264 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
15265 SDValue rd = DAG.getNode(Opcode, DL, Tys, N->getOperand(0));
15268 // The processor's time-stamp counter (a 64-bit MSR) is stored into the
15269 // EDX:EAX registers. EDX is loaded with the high-order 32 bits of the MSR
15270 // and the EAX register is loaded with the low-order 32 bits.
15271 if (Subtarget->is64Bit()) {
15272 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
15273 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
15276 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
15277 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
15280 SDValue Chain = HI.getValue(1);
15282 if (Opcode == X86ISD::RDTSCP_DAG) {
15283 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
15285 // Instruction RDTSCP loads the IA32:TSC_AUX_MSR (address C000_0103H) into
15286 // the ECX register. Add 'ecx' explicitly to the chain.
15287 SDValue ecx = DAG.getCopyFromReg(Chain, DL, X86::ECX, MVT::i32,
15289 // Explicitly store the content of ECX at the location passed in input
15290 // to the 'rdtscp' intrinsic.
15291 Chain = DAG.getStore(ecx.getValue(1), DL, ecx, N->getOperand(2),
15292 MachinePointerInfo(), false, false, 0);
15295 if (Subtarget->is64Bit()) {
15296 // The EDX register is loaded with the high-order 32 bits of the MSR, and
15297 // the EAX register is loaded with the low-order 32 bits.
15298 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
15299 DAG.getConstant(32, MVT::i8));
15300 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
15301 Results.push_back(Chain);
15305 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
15306 SDValue Ops[] = { LO, HI };
15307 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
15308 Results.push_back(Pair);
15309 Results.push_back(Chain);
15312 static SDValue LowerREADCYCLECOUNTER(SDValue Op, const X86Subtarget *Subtarget,
15313 SelectionDAG &DAG) {
15314 SmallVector<SDValue, 2> Results;
15316 getReadTimeStampCounter(Op.getNode(), DL, X86ISD::RDTSC_DAG, DAG, Subtarget,
15318 return DAG.getMergeValues(Results, DL);
15321 enum IntrinsicType {
15322 GATHER, SCATTER, PREFETCH, RDSEED, RDRAND, RDPMC, RDTSC, XTEST
15325 struct IntrinsicData {
15326 IntrinsicData(IntrinsicType IType, unsigned IOpc0, unsigned IOpc1)
15327 :Type(IType), Opc0(IOpc0), Opc1(IOpc1) {}
15328 IntrinsicType Type;
15333 std::map < unsigned, IntrinsicData> IntrMap;
15334 static void InitIntinsicsMap() {
15335 static bool Initialized = false;
15338 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_gather_qps_512,
15339 IntrinsicData(GATHER, X86::VGATHERQPSZrm, 0)));
15340 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_gather_qps_512,
15341 IntrinsicData(GATHER, X86::VGATHERQPSZrm, 0)));
15342 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_gather_qpd_512,
15343 IntrinsicData(GATHER, X86::VGATHERQPDZrm, 0)));
15344 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_gather_dpd_512,
15345 IntrinsicData(GATHER, X86::VGATHERDPDZrm, 0)));
15346 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_gather_dps_512,
15347 IntrinsicData(GATHER, X86::VGATHERDPSZrm, 0)));
15348 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_gather_qpi_512,
15349 IntrinsicData(GATHER, X86::VPGATHERQDZrm, 0)));
15350 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_gather_qpq_512,
15351 IntrinsicData(GATHER, X86::VPGATHERQQZrm, 0)));
15352 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_gather_dpi_512,
15353 IntrinsicData(GATHER, X86::VPGATHERDDZrm, 0)));
15354 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_gather_dpq_512,
15355 IntrinsicData(GATHER, X86::VPGATHERDQZrm, 0)));
15357 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_scatter_qps_512,
15358 IntrinsicData(SCATTER, X86::VSCATTERQPSZmr, 0)));
15359 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_scatter_qpd_512,
15360 IntrinsicData(SCATTER, X86::VSCATTERQPDZmr, 0)));
15361 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_scatter_dpd_512,
15362 IntrinsicData(SCATTER, X86::VSCATTERDPDZmr, 0)));
15363 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_scatter_dps_512,
15364 IntrinsicData(SCATTER, X86::VSCATTERDPSZmr, 0)));
15365 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_scatter_qpi_512,
15366 IntrinsicData(SCATTER, X86::VPSCATTERQDZmr, 0)));
15367 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_scatter_qpq_512,
15368 IntrinsicData(SCATTER, X86::VPSCATTERQQZmr, 0)));
15369 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_scatter_dpi_512,
15370 IntrinsicData(SCATTER, X86::VPSCATTERDDZmr, 0)));
15371 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_scatter_dpq_512,
15372 IntrinsicData(SCATTER, X86::VPSCATTERDQZmr, 0)));
15374 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_gatherpf_qps_512,
15375 IntrinsicData(PREFETCH, X86::VGATHERPF0QPSm,
15376 X86::VGATHERPF1QPSm)));
15377 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_gatherpf_qpd_512,
15378 IntrinsicData(PREFETCH, X86::VGATHERPF0QPDm,
15379 X86::VGATHERPF1QPDm)));
15380 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_gatherpf_dpd_512,
15381 IntrinsicData(PREFETCH, X86::VGATHERPF0DPDm,
15382 X86::VGATHERPF1DPDm)));
15383 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_gatherpf_dps_512,
15384 IntrinsicData(PREFETCH, X86::VGATHERPF0DPSm,
15385 X86::VGATHERPF1DPSm)));
15386 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_scatterpf_qps_512,
15387 IntrinsicData(PREFETCH, X86::VSCATTERPF0QPSm,
15388 X86::VSCATTERPF1QPSm)));
15389 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_scatterpf_qpd_512,
15390 IntrinsicData(PREFETCH, X86::VSCATTERPF0QPDm,
15391 X86::VSCATTERPF1QPDm)));
15392 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_scatterpf_dpd_512,
15393 IntrinsicData(PREFETCH, X86::VSCATTERPF0DPDm,
15394 X86::VSCATTERPF1DPDm)));
15395 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_scatterpf_dps_512,
15396 IntrinsicData(PREFETCH, X86::VSCATTERPF0DPSm,
15397 X86::VSCATTERPF1DPSm)));
15398 IntrMap.insert(std::make_pair(Intrinsic::x86_rdrand_16,
15399 IntrinsicData(RDRAND, X86ISD::RDRAND, 0)));
15400 IntrMap.insert(std::make_pair(Intrinsic::x86_rdrand_32,
15401 IntrinsicData(RDRAND, X86ISD::RDRAND, 0)));
15402 IntrMap.insert(std::make_pair(Intrinsic::x86_rdrand_64,
15403 IntrinsicData(RDRAND, X86ISD::RDRAND, 0)));
15404 IntrMap.insert(std::make_pair(Intrinsic::x86_rdseed_16,
15405 IntrinsicData(RDSEED, X86ISD::RDSEED, 0)));
15406 IntrMap.insert(std::make_pair(Intrinsic::x86_rdseed_32,
15407 IntrinsicData(RDSEED, X86ISD::RDSEED, 0)));
15408 IntrMap.insert(std::make_pair(Intrinsic::x86_rdseed_64,
15409 IntrinsicData(RDSEED, X86ISD::RDSEED, 0)));
15410 IntrMap.insert(std::make_pair(Intrinsic::x86_xtest,
15411 IntrinsicData(XTEST, X86ISD::XTEST, 0)));
15412 IntrMap.insert(std::make_pair(Intrinsic::x86_rdtsc,
15413 IntrinsicData(RDTSC, X86ISD::RDTSC_DAG, 0)));
15414 IntrMap.insert(std::make_pair(Intrinsic::x86_rdtscp,
15415 IntrinsicData(RDTSC, X86ISD::RDTSCP_DAG, 0)));
15416 IntrMap.insert(std::make_pair(Intrinsic::x86_rdpmc,
15417 IntrinsicData(RDPMC, X86ISD::RDPMC_DAG, 0)));
15418 Initialized = true;
15421 static SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
15422 SelectionDAG &DAG) {
15423 InitIntinsicsMap();
15424 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
15425 std::map < unsigned, IntrinsicData>::const_iterator itr = IntrMap.find(IntNo);
15426 if (itr == IntrMap.end())
15430 IntrinsicData Intr = itr->second;
15431 switch(Intr.Type) {
15434 // Emit the node with the right value type.
15435 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Glue, MVT::Other);
15436 SDValue Result = DAG.getNode(Intr.Opc0, dl, VTs, Op.getOperand(0));
15438 // If the value returned by RDRAND/RDSEED was valid (CF=1), return 1.
15439 // Otherwise return the value from Rand, which is always 0, casted to i32.
15440 SDValue Ops[] = { DAG.getZExtOrTrunc(Result, dl, Op->getValueType(1)),
15441 DAG.getConstant(1, Op->getValueType(1)),
15442 DAG.getConstant(X86::COND_B, MVT::i32),
15443 SDValue(Result.getNode(), 1) };
15444 SDValue isValid = DAG.getNode(X86ISD::CMOV, dl,
15445 DAG.getVTList(Op->getValueType(1), MVT::Glue),
15448 // Return { result, isValid, chain }.
15449 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(), Result, isValid,
15450 SDValue(Result.getNode(), 2));
15453 //gather(v1, mask, index, base, scale);
15454 SDValue Chain = Op.getOperand(0);
15455 SDValue Src = Op.getOperand(2);
15456 SDValue Base = Op.getOperand(3);
15457 SDValue Index = Op.getOperand(4);
15458 SDValue Mask = Op.getOperand(5);
15459 SDValue Scale = Op.getOperand(6);
15460 return getGatherNode(Intr.Opc0, Op, DAG, Src, Mask, Base, Index, Scale, Chain,
15464 //scatter(base, mask, index, v1, scale);
15465 SDValue Chain = Op.getOperand(0);
15466 SDValue Base = Op.getOperand(2);
15467 SDValue Mask = Op.getOperand(3);
15468 SDValue Index = Op.getOperand(4);
15469 SDValue Src = Op.getOperand(5);
15470 SDValue Scale = Op.getOperand(6);
15471 return getScatterNode(Intr.Opc0, Op, DAG, Src, Mask, Base, Index, Scale, Chain);
15474 SDValue Hint = Op.getOperand(6);
15476 if (dyn_cast<ConstantSDNode> (Hint) == nullptr ||
15477 (HintVal = dyn_cast<ConstantSDNode> (Hint)->getZExtValue()) > 1)
15478 llvm_unreachable("Wrong prefetch hint in intrinsic: should be 0 or 1");
15479 unsigned Opcode = (HintVal ? Intr.Opc1 : Intr.Opc0);
15480 SDValue Chain = Op.getOperand(0);
15481 SDValue Mask = Op.getOperand(2);
15482 SDValue Index = Op.getOperand(3);
15483 SDValue Base = Op.getOperand(4);
15484 SDValue Scale = Op.getOperand(5);
15485 return getPrefetchNode(Opcode, Op, DAG, Mask, Base, Index, Scale, Chain);
15487 // Read Time Stamp Counter (RDTSC) and Processor ID (RDTSCP).
15489 SmallVector<SDValue, 2> Results;
15490 getReadTimeStampCounter(Op.getNode(), dl, Intr.Opc0, DAG, Subtarget, Results);
15491 return DAG.getMergeValues(Results, dl);
15493 // Read Performance Monitoring Counters.
15495 SmallVector<SDValue, 2> Results;
15496 getReadPerformanceCounter(Op.getNode(), dl, DAG, Subtarget, Results);
15497 return DAG.getMergeValues(Results, dl);
15499 // XTEST intrinsics.
15501 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
15502 SDValue InTrans = DAG.getNode(X86ISD::XTEST, dl, VTs, Op.getOperand(0));
15503 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
15504 DAG.getConstant(X86::COND_NE, MVT::i8),
15506 SDValue Ret = DAG.getNode(ISD::ZERO_EXTEND, dl, Op->getValueType(0), SetCC);
15507 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(),
15508 Ret, SDValue(InTrans.getNode(), 1));
15511 llvm_unreachable("Unknown Intrinsic Type");
15514 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op,
15515 SelectionDAG &DAG) const {
15516 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
15517 MFI->setReturnAddressIsTaken(true);
15519 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
15522 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
15524 EVT PtrVT = getPointerTy();
15527 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
15528 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
15529 DAG.getSubtarget().getRegisterInfo());
15530 SDValue Offset = DAG.getConstant(RegInfo->getSlotSize(), PtrVT);
15531 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
15532 DAG.getNode(ISD::ADD, dl, PtrVT,
15533 FrameAddr, Offset),
15534 MachinePointerInfo(), false, false, false, 0);
15537 // Just load the return address.
15538 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
15539 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
15540 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
15543 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
15544 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
15545 MFI->setFrameAddressIsTaken(true);
15547 EVT VT = Op.getValueType();
15548 SDLoc dl(Op); // FIXME probably not meaningful
15549 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
15550 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
15551 DAG.getSubtarget().getRegisterInfo());
15552 unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction());
15553 assert(((FrameReg == X86::RBP && VT == MVT::i64) ||
15554 (FrameReg == X86::EBP && VT == MVT::i32)) &&
15555 "Invalid Frame Register!");
15556 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
15558 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
15559 MachinePointerInfo(),
15560 false, false, false, 0);
15564 // FIXME? Maybe this could be a TableGen attribute on some registers and
15565 // this table could be generated automatically from RegInfo.
15566 unsigned X86TargetLowering::getRegisterByName(const char* RegName,
15568 unsigned Reg = StringSwitch<unsigned>(RegName)
15569 .Case("esp", X86::ESP)
15570 .Case("rsp", X86::RSP)
15574 report_fatal_error("Invalid register name global variable");
15577 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
15578 SelectionDAG &DAG) const {
15579 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
15580 DAG.getSubtarget().getRegisterInfo());
15581 return DAG.getIntPtrConstant(2 * RegInfo->getSlotSize());
15584 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
15585 SDValue Chain = Op.getOperand(0);
15586 SDValue Offset = Op.getOperand(1);
15587 SDValue Handler = Op.getOperand(2);
15590 EVT PtrVT = getPointerTy();
15591 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
15592 DAG.getSubtarget().getRegisterInfo());
15593 unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction());
15594 assert(((FrameReg == X86::RBP && PtrVT == MVT::i64) ||
15595 (FrameReg == X86::EBP && PtrVT == MVT::i32)) &&
15596 "Invalid Frame Register!");
15597 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, PtrVT);
15598 unsigned StoreAddrReg = (PtrVT == MVT::i64) ? X86::RCX : X86::ECX;
15600 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, Frame,
15601 DAG.getIntPtrConstant(RegInfo->getSlotSize()));
15602 StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, StoreAddr, Offset);
15603 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(),
15605 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
15607 return DAG.getNode(X86ISD::EH_RETURN, dl, MVT::Other, Chain,
15608 DAG.getRegister(StoreAddrReg, PtrVT));
15611 SDValue X86TargetLowering::lowerEH_SJLJ_SETJMP(SDValue Op,
15612 SelectionDAG &DAG) const {
15614 return DAG.getNode(X86ISD::EH_SJLJ_SETJMP, DL,
15615 DAG.getVTList(MVT::i32, MVT::Other),
15616 Op.getOperand(0), Op.getOperand(1));
15619 SDValue X86TargetLowering::lowerEH_SJLJ_LONGJMP(SDValue Op,
15620 SelectionDAG &DAG) const {
15622 return DAG.getNode(X86ISD::EH_SJLJ_LONGJMP, DL, MVT::Other,
15623 Op.getOperand(0), Op.getOperand(1));
15626 static SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) {
15627 return Op.getOperand(0);
15630 SDValue X86TargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
15631 SelectionDAG &DAG) const {
15632 SDValue Root = Op.getOperand(0);
15633 SDValue Trmp = Op.getOperand(1); // trampoline
15634 SDValue FPtr = Op.getOperand(2); // nested function
15635 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
15638 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
15639 const TargetRegisterInfo *TRI = DAG.getSubtarget().getRegisterInfo();
15641 if (Subtarget->is64Bit()) {
15642 SDValue OutChains[6];
15644 // Large code-model.
15645 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode.
15646 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode.
15648 const unsigned char N86R10 = TRI->getEncodingValue(X86::R10) & 0x7;
15649 const unsigned char N86R11 = TRI->getEncodingValue(X86::R11) & 0x7;
15651 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
15653 // Load the pointer to the nested function into R11.
15654 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
15655 SDValue Addr = Trmp;
15656 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
15657 Addr, MachinePointerInfo(TrmpAddr),
15660 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
15661 DAG.getConstant(2, MVT::i64));
15662 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr,
15663 MachinePointerInfo(TrmpAddr, 2),
15666 // Load the 'nest' parameter value into R10.
15667 // R10 is specified in X86CallingConv.td
15668 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
15669 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
15670 DAG.getConstant(10, MVT::i64));
15671 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
15672 Addr, MachinePointerInfo(TrmpAddr, 10),
15675 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
15676 DAG.getConstant(12, MVT::i64));
15677 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr,
15678 MachinePointerInfo(TrmpAddr, 12),
15681 // Jump to the nested function.
15682 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
15683 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
15684 DAG.getConstant(20, MVT::i64));
15685 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
15686 Addr, MachinePointerInfo(TrmpAddr, 20),
15689 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
15690 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
15691 DAG.getConstant(22, MVT::i64));
15692 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr,
15693 MachinePointerInfo(TrmpAddr, 22),
15696 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
15698 const Function *Func =
15699 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
15700 CallingConv::ID CC = Func->getCallingConv();
15705 llvm_unreachable("Unsupported calling convention");
15706 case CallingConv::C:
15707 case CallingConv::X86_StdCall: {
15708 // Pass 'nest' parameter in ECX.
15709 // Must be kept in sync with X86CallingConv.td
15710 NestReg = X86::ECX;
15712 // Check that ECX wasn't needed by an 'inreg' parameter.
15713 FunctionType *FTy = Func->getFunctionType();
15714 const AttributeSet &Attrs = Func->getAttributes();
15716 if (!Attrs.isEmpty() && !Func->isVarArg()) {
15717 unsigned InRegCount = 0;
15720 for (FunctionType::param_iterator I = FTy->param_begin(),
15721 E = FTy->param_end(); I != E; ++I, ++Idx)
15722 if (Attrs.hasAttribute(Idx, Attribute::InReg))
15723 // FIXME: should only count parameters that are lowered to integers.
15724 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32;
15726 if (InRegCount > 2) {
15727 report_fatal_error("Nest register in use - reduce number of inreg"
15733 case CallingConv::X86_FastCall:
15734 case CallingConv::X86_ThisCall:
15735 case CallingConv::Fast:
15736 // Pass 'nest' parameter in EAX.
15737 // Must be kept in sync with X86CallingConv.td
15738 NestReg = X86::EAX;
15742 SDValue OutChains[4];
15743 SDValue Addr, Disp;
15745 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
15746 DAG.getConstant(10, MVT::i32));
15747 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
15749 // This is storing the opcode for MOV32ri.
15750 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte.
15751 const unsigned char N86Reg = TRI->getEncodingValue(NestReg) & 0x7;
15752 OutChains[0] = DAG.getStore(Root, dl,
15753 DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
15754 Trmp, MachinePointerInfo(TrmpAddr),
15757 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
15758 DAG.getConstant(1, MVT::i32));
15759 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr,
15760 MachinePointerInfo(TrmpAddr, 1),
15763 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode.
15764 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
15765 DAG.getConstant(5, MVT::i32));
15766 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr,
15767 MachinePointerInfo(TrmpAddr, 5),
15770 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
15771 DAG.getConstant(6, MVT::i32));
15772 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr,
15773 MachinePointerInfo(TrmpAddr, 6),
15776 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
15780 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op,
15781 SelectionDAG &DAG) const {
15783 The rounding mode is in bits 11:10 of FPSR, and has the following
15785 00 Round to nearest
15790 FLT_ROUNDS, on the other hand, expects the following:
15797 To perform the conversion, we do:
15798 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
15801 MachineFunction &MF = DAG.getMachineFunction();
15802 const TargetMachine &TM = MF.getTarget();
15803 const TargetFrameLowering &TFI = *TM.getSubtargetImpl()->getFrameLowering();
15804 unsigned StackAlignment = TFI.getStackAlignment();
15805 MVT VT = Op.getSimpleValueType();
15808 // Save FP Control Word to stack slot
15809 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false);
15810 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
15812 MachineMemOperand *MMO =
15813 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
15814 MachineMemOperand::MOStore, 2, 2);
15816 SDValue Ops[] = { DAG.getEntryNode(), StackSlot };
15817 SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL,
15818 DAG.getVTList(MVT::Other),
15819 Ops, MVT::i16, MMO);
15821 // Load FP Control Word from stack slot
15822 SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot,
15823 MachinePointerInfo(), false, false, false, 0);
15825 // Transform as necessary
15827 DAG.getNode(ISD::SRL, DL, MVT::i16,
15828 DAG.getNode(ISD::AND, DL, MVT::i16,
15829 CWD, DAG.getConstant(0x800, MVT::i16)),
15830 DAG.getConstant(11, MVT::i8));
15832 DAG.getNode(ISD::SRL, DL, MVT::i16,
15833 DAG.getNode(ISD::AND, DL, MVT::i16,
15834 CWD, DAG.getConstant(0x400, MVT::i16)),
15835 DAG.getConstant(9, MVT::i8));
15838 DAG.getNode(ISD::AND, DL, MVT::i16,
15839 DAG.getNode(ISD::ADD, DL, MVT::i16,
15840 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2),
15841 DAG.getConstant(1, MVT::i16)),
15842 DAG.getConstant(3, MVT::i16));
15844 return DAG.getNode((VT.getSizeInBits() < 16 ?
15845 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal);
15848 static SDValue LowerCTLZ(SDValue Op, SelectionDAG &DAG) {
15849 MVT VT = Op.getSimpleValueType();
15851 unsigned NumBits = VT.getSizeInBits();
15854 Op = Op.getOperand(0);
15855 if (VT == MVT::i8) {
15856 // Zero extend to i32 since there is not an i8 bsr.
15858 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
15861 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
15862 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
15863 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
15865 // If src is zero (i.e. bsr sets ZF), returns NumBits.
15868 DAG.getConstant(NumBits+NumBits-1, OpVT),
15869 DAG.getConstant(X86::COND_E, MVT::i8),
15872 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops);
15874 // Finally xor with NumBits-1.
15875 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
15878 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
15882 static SDValue LowerCTLZ_ZERO_UNDEF(SDValue Op, SelectionDAG &DAG) {
15883 MVT VT = Op.getSimpleValueType();
15885 unsigned NumBits = VT.getSizeInBits();
15888 Op = Op.getOperand(0);
15889 if (VT == MVT::i8) {
15890 // Zero extend to i32 since there is not an i8 bsr.
15892 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
15895 // Issue a bsr (scan bits in reverse).
15896 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
15897 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
15899 // And xor with NumBits-1.
15900 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
15903 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
15907 static SDValue LowerCTTZ(SDValue Op, SelectionDAG &DAG) {
15908 MVT VT = Op.getSimpleValueType();
15909 unsigned NumBits = VT.getSizeInBits();
15911 Op = Op.getOperand(0);
15913 // Issue a bsf (scan bits forward) which also sets EFLAGS.
15914 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
15915 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op);
15917 // If src is zero (i.e. bsf sets ZF), returns NumBits.
15920 DAG.getConstant(NumBits, VT),
15921 DAG.getConstant(X86::COND_E, MVT::i8),
15924 return DAG.getNode(X86ISD::CMOV, dl, VT, Ops);
15927 // Lower256IntArith - Break a 256-bit integer operation into two new 128-bit
15928 // ones, and then concatenate the result back.
15929 static SDValue Lower256IntArith(SDValue Op, SelectionDAG &DAG) {
15930 MVT VT = Op.getSimpleValueType();
15932 assert(VT.is256BitVector() && VT.isInteger() &&
15933 "Unsupported value type for operation");
15935 unsigned NumElems = VT.getVectorNumElements();
15938 // Extract the LHS vectors
15939 SDValue LHS = Op.getOperand(0);
15940 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
15941 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
15943 // Extract the RHS vectors
15944 SDValue RHS = Op.getOperand(1);
15945 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
15946 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
15948 MVT EltVT = VT.getVectorElementType();
15949 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
15951 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
15952 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1),
15953 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2));
15956 static SDValue LowerADD(SDValue Op, SelectionDAG &DAG) {
15957 assert(Op.getSimpleValueType().is256BitVector() &&
15958 Op.getSimpleValueType().isInteger() &&
15959 "Only handle AVX 256-bit vector integer operation");
15960 return Lower256IntArith(Op, DAG);
15963 static SDValue LowerSUB(SDValue Op, SelectionDAG &DAG) {
15964 assert(Op.getSimpleValueType().is256BitVector() &&
15965 Op.getSimpleValueType().isInteger() &&
15966 "Only handle AVX 256-bit vector integer operation");
15967 return Lower256IntArith(Op, DAG);
15970 static SDValue LowerMUL(SDValue Op, const X86Subtarget *Subtarget,
15971 SelectionDAG &DAG) {
15973 MVT VT = Op.getSimpleValueType();
15975 // Decompose 256-bit ops into smaller 128-bit ops.
15976 if (VT.is256BitVector() && !Subtarget->hasInt256())
15977 return Lower256IntArith(Op, DAG);
15979 SDValue A = Op.getOperand(0);
15980 SDValue B = Op.getOperand(1);
15982 // Lower v4i32 mul as 2x shuffle, 2x pmuludq, 2x shuffle.
15983 if (VT == MVT::v4i32) {
15984 assert(Subtarget->hasSSE2() && !Subtarget->hasSSE41() &&
15985 "Should not custom lower when pmuldq is available!");
15987 // Extract the odd parts.
15988 static const int UnpackMask[] = { 1, -1, 3, -1 };
15989 SDValue Aodds = DAG.getVectorShuffle(VT, dl, A, A, UnpackMask);
15990 SDValue Bodds = DAG.getVectorShuffle(VT, dl, B, B, UnpackMask);
15992 // Multiply the even parts.
15993 SDValue Evens = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, A, B);
15994 // Now multiply odd parts.
15995 SDValue Odds = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, Aodds, Bodds);
15997 Evens = DAG.getNode(ISD::BITCAST, dl, VT, Evens);
15998 Odds = DAG.getNode(ISD::BITCAST, dl, VT, Odds);
16000 // Merge the two vectors back together with a shuffle. This expands into 2
16002 static const int ShufMask[] = { 0, 4, 2, 6 };
16003 return DAG.getVectorShuffle(VT, dl, Evens, Odds, ShufMask);
16006 assert((VT == MVT::v2i64 || VT == MVT::v4i64 || VT == MVT::v8i64) &&
16007 "Only know how to lower V2I64/V4I64/V8I64 multiply");
16009 // Ahi = psrlqi(a, 32);
16010 // Bhi = psrlqi(b, 32);
16012 // AloBlo = pmuludq(a, b);
16013 // AloBhi = pmuludq(a, Bhi);
16014 // AhiBlo = pmuludq(Ahi, b);
16016 // AloBhi = psllqi(AloBhi, 32);
16017 // AhiBlo = psllqi(AhiBlo, 32);
16018 // return AloBlo + AloBhi + AhiBlo;
16020 SDValue Ahi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, A, 32, DAG);
16021 SDValue Bhi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, B, 32, DAG);
16023 // Bit cast to 32-bit vectors for MULUDQ
16024 EVT MulVT = (VT == MVT::v2i64) ? MVT::v4i32 :
16025 (VT == MVT::v4i64) ? MVT::v8i32 : MVT::v16i32;
16026 A = DAG.getNode(ISD::BITCAST, dl, MulVT, A);
16027 B = DAG.getNode(ISD::BITCAST, dl, MulVT, B);
16028 Ahi = DAG.getNode(ISD::BITCAST, dl, MulVT, Ahi);
16029 Bhi = DAG.getNode(ISD::BITCAST, dl, MulVT, Bhi);
16031 SDValue AloBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, B);
16032 SDValue AloBhi = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, Bhi);
16033 SDValue AhiBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, Ahi, B);
16035 AloBhi = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AloBhi, 32, DAG);
16036 AhiBlo = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AhiBlo, 32, DAG);
16038 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
16039 return DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
16042 SDValue X86TargetLowering::LowerWin64_i128OP(SDValue Op, SelectionDAG &DAG) const {
16043 assert(Subtarget->isTargetWin64() && "Unexpected target");
16044 EVT VT = Op.getValueType();
16045 assert(VT.isInteger() && VT.getSizeInBits() == 128 &&
16046 "Unexpected return type for lowering");
16050 switch (Op->getOpcode()) {
16051 default: llvm_unreachable("Unexpected request for libcall!");
16052 case ISD::SDIV: isSigned = true; LC = RTLIB::SDIV_I128; break;
16053 case ISD::UDIV: isSigned = false; LC = RTLIB::UDIV_I128; break;
16054 case ISD::SREM: isSigned = true; LC = RTLIB::SREM_I128; break;
16055 case ISD::UREM: isSigned = false; LC = RTLIB::UREM_I128; break;
16056 case ISD::SDIVREM: isSigned = true; LC = RTLIB::SDIVREM_I128; break;
16057 case ISD::UDIVREM: isSigned = false; LC = RTLIB::UDIVREM_I128; break;
16061 SDValue InChain = DAG.getEntryNode();
16063 TargetLowering::ArgListTy Args;
16064 TargetLowering::ArgListEntry Entry;
16065 for (unsigned i = 0, e = Op->getNumOperands(); i != e; ++i) {
16066 EVT ArgVT = Op->getOperand(i).getValueType();
16067 assert(ArgVT.isInteger() && ArgVT.getSizeInBits() == 128 &&
16068 "Unexpected argument type for lowering");
16069 SDValue StackPtr = DAG.CreateStackTemporary(ArgVT, 16);
16070 Entry.Node = StackPtr;
16071 InChain = DAG.getStore(InChain, dl, Op->getOperand(i), StackPtr, MachinePointerInfo(),
16073 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
16074 Entry.Ty = PointerType::get(ArgTy,0);
16075 Entry.isSExt = false;
16076 Entry.isZExt = false;
16077 Args.push_back(Entry);
16080 SDValue Callee = DAG.getExternalSymbol(getLibcallName(LC),
16083 TargetLowering::CallLoweringInfo CLI(DAG);
16084 CLI.setDebugLoc(dl).setChain(InChain)
16085 .setCallee(getLibcallCallingConv(LC),
16086 static_cast<EVT>(MVT::v2i64).getTypeForEVT(*DAG.getContext()),
16087 Callee, std::move(Args), 0)
16088 .setInRegister().setSExtResult(isSigned).setZExtResult(!isSigned);
16090 std::pair<SDValue, SDValue> CallInfo = LowerCallTo(CLI);
16091 return DAG.getNode(ISD::BITCAST, dl, VT, CallInfo.first);
16094 static SDValue LowerMUL_LOHI(SDValue Op, const X86Subtarget *Subtarget,
16095 SelectionDAG &DAG) {
16096 SDValue Op0 = Op.getOperand(0), Op1 = Op.getOperand(1);
16097 EVT VT = Op0.getValueType();
16100 assert((VT == MVT::v4i32 && Subtarget->hasSSE2()) ||
16101 (VT == MVT::v8i32 && Subtarget->hasInt256()));
16103 // PMULxD operations multiply each even value (starting at 0) of LHS with
16104 // the related value of RHS and produce a widen result.
16105 // E.g., PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
16106 // => <2 x i64> <ae|cg>
16108 // In other word, to have all the results, we need to perform two PMULxD:
16109 // 1. one with the even values.
16110 // 2. one with the odd values.
16111 // To achieve #2, with need to place the odd values at an even position.
16113 // Place the odd value at an even position (basically, shift all values 1
16114 // step to the left):
16115 const int Mask[] = {1, -1, 3, -1, 5, -1, 7, -1};
16116 // <a|b|c|d> => <b|undef|d|undef>
16117 SDValue Odd0 = DAG.getVectorShuffle(VT, dl, Op0, Op0, Mask);
16118 // <e|f|g|h> => <f|undef|h|undef>
16119 SDValue Odd1 = DAG.getVectorShuffle(VT, dl, Op1, Op1, Mask);
16121 // Emit two multiplies, one for the lower 2 ints and one for the higher 2
16123 MVT MulVT = VT == MVT::v4i32 ? MVT::v2i64 : MVT::v4i64;
16124 bool IsSigned = Op->getOpcode() == ISD::SMUL_LOHI;
16126 (!IsSigned || !Subtarget->hasSSE41()) ? X86ISD::PMULUDQ : X86ISD::PMULDQ;
16127 // PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
16128 // => <2 x i64> <ae|cg>
16129 SDValue Mul1 = DAG.getNode(ISD::BITCAST, dl, VT,
16130 DAG.getNode(Opcode, dl, MulVT, Op0, Op1));
16131 // PMULUDQ <4 x i32> <b|undef|d|undef>, <4 x i32> <f|undef|h|undef>
16132 // => <2 x i64> <bf|dh>
16133 SDValue Mul2 = DAG.getNode(ISD::BITCAST, dl, VT,
16134 DAG.getNode(Opcode, dl, MulVT, Odd0, Odd1));
16136 // Shuffle it back into the right order.
16137 SDValue Highs, Lows;
16138 if (VT == MVT::v8i32) {
16139 const int HighMask[] = {1, 9, 3, 11, 5, 13, 7, 15};
16140 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
16141 const int LowMask[] = {0, 8, 2, 10, 4, 12, 6, 14};
16142 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
16144 const int HighMask[] = {1, 5, 3, 7};
16145 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
16146 const int LowMask[] = {0, 4, 2, 6};
16147 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
16150 // If we have a signed multiply but no PMULDQ fix up the high parts of a
16151 // unsigned multiply.
16152 if (IsSigned && !Subtarget->hasSSE41()) {
16154 DAG.getConstant(31, DAG.getTargetLoweringInfo().getShiftAmountTy(VT));
16155 SDValue T1 = DAG.getNode(ISD::AND, dl, VT,
16156 DAG.getNode(ISD::SRA, dl, VT, Op0, ShAmt), Op1);
16157 SDValue T2 = DAG.getNode(ISD::AND, dl, VT,
16158 DAG.getNode(ISD::SRA, dl, VT, Op1, ShAmt), Op0);
16160 SDValue Fixup = DAG.getNode(ISD::ADD, dl, VT, T1, T2);
16161 Highs = DAG.getNode(ISD::SUB, dl, VT, Highs, Fixup);
16164 // The first result of MUL_LOHI is actually the low value, followed by the
16166 SDValue Ops[] = {Lows, Highs};
16167 return DAG.getMergeValues(Ops, dl);
16170 static SDValue LowerScalarImmediateShift(SDValue Op, SelectionDAG &DAG,
16171 const X86Subtarget *Subtarget) {
16172 MVT VT = Op.getSimpleValueType();
16174 SDValue R = Op.getOperand(0);
16175 SDValue Amt = Op.getOperand(1);
16177 // Optimize shl/srl/sra with constant shift amount.
16178 if (auto *BVAmt = dyn_cast<BuildVectorSDNode>(Amt)) {
16179 if (auto *ShiftConst = BVAmt->getConstantSplatNode()) {
16180 uint64_t ShiftAmt = ShiftConst->getZExtValue();
16182 if (VT == MVT::v2i64 || VT == MVT::v4i32 || VT == MVT::v8i16 ||
16183 (Subtarget->hasInt256() &&
16184 (VT == MVT::v4i64 || VT == MVT::v8i32 || VT == MVT::v16i16)) ||
16185 (Subtarget->hasAVX512() &&
16186 (VT == MVT::v8i64 || VT == MVT::v16i32))) {
16187 if (Op.getOpcode() == ISD::SHL)
16188 return getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, R, ShiftAmt,
16190 if (Op.getOpcode() == ISD::SRL)
16191 return getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, R, ShiftAmt,
16193 if (Op.getOpcode() == ISD::SRA && VT != MVT::v2i64 && VT != MVT::v4i64)
16194 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, R, ShiftAmt,
16198 if (VT == MVT::v16i8) {
16199 if (Op.getOpcode() == ISD::SHL) {
16200 // Make a large shift.
16201 SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl,
16202 MVT::v8i16, R, ShiftAmt,
16204 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
16205 // Zero out the rightmost bits.
16206 SmallVector<SDValue, 16> V(16,
16207 DAG.getConstant(uint8_t(-1U << ShiftAmt),
16209 return DAG.getNode(ISD::AND, dl, VT, SHL,
16210 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
16212 if (Op.getOpcode() == ISD::SRL) {
16213 // Make a large shift.
16214 SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl,
16215 MVT::v8i16, R, ShiftAmt,
16217 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
16218 // Zero out the leftmost bits.
16219 SmallVector<SDValue, 16> V(16,
16220 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
16222 return DAG.getNode(ISD::AND, dl, VT, SRL,
16223 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
16225 if (Op.getOpcode() == ISD::SRA) {
16226 if (ShiftAmt == 7) {
16227 // R s>> 7 === R s< 0
16228 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
16229 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
16232 // R s>> a === ((R u>> a) ^ m) - m
16233 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
16234 SmallVector<SDValue, 16> V(16, DAG.getConstant(128 >> ShiftAmt,
16236 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V);
16237 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
16238 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
16241 llvm_unreachable("Unknown shift opcode.");
16244 if (Subtarget->hasInt256() && VT == MVT::v32i8) {
16245 if (Op.getOpcode() == ISD::SHL) {
16246 // Make a large shift.
16247 SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl,
16248 MVT::v16i16, R, ShiftAmt,
16250 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
16251 // Zero out the rightmost bits.
16252 SmallVector<SDValue, 32> V(32,
16253 DAG.getConstant(uint8_t(-1U << ShiftAmt),
16255 return DAG.getNode(ISD::AND, dl, VT, SHL,
16256 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
16258 if (Op.getOpcode() == ISD::SRL) {
16259 // Make a large shift.
16260 SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl,
16261 MVT::v16i16, R, ShiftAmt,
16263 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
16264 // Zero out the leftmost bits.
16265 SmallVector<SDValue, 32> V(32,
16266 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
16268 return DAG.getNode(ISD::AND, dl, VT, SRL,
16269 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
16271 if (Op.getOpcode() == ISD::SRA) {
16272 if (ShiftAmt == 7) {
16273 // R s>> 7 === R s< 0
16274 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
16275 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
16278 // R s>> a === ((R u>> a) ^ m) - m
16279 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
16280 SmallVector<SDValue, 32> V(32, DAG.getConstant(128 >> ShiftAmt,
16282 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V);
16283 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
16284 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
16287 llvm_unreachable("Unknown shift opcode.");
16292 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
16293 if (!Subtarget->is64Bit() &&
16294 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64)) &&
16295 Amt.getOpcode() == ISD::BITCAST &&
16296 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
16297 Amt = Amt.getOperand(0);
16298 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
16299 VT.getVectorNumElements();
16300 unsigned RatioInLog2 = Log2_32_Ceil(Ratio);
16301 uint64_t ShiftAmt = 0;
16302 for (unsigned i = 0; i != Ratio; ++i) {
16303 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Amt.getOperand(i));
16307 ShiftAmt |= C->getZExtValue() << (i * (1 << (6 - RatioInLog2)));
16309 // Check remaining shift amounts.
16310 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
16311 uint64_t ShAmt = 0;
16312 for (unsigned j = 0; j != Ratio; ++j) {
16313 ConstantSDNode *C =
16314 dyn_cast<ConstantSDNode>(Amt.getOperand(i + j));
16318 ShAmt |= C->getZExtValue() << (j * (1 << (6 - RatioInLog2)));
16320 if (ShAmt != ShiftAmt)
16323 switch (Op.getOpcode()) {
16325 llvm_unreachable("Unknown shift opcode!");
16327 return getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, R, ShiftAmt,
16330 return getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, R, ShiftAmt,
16333 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, R, ShiftAmt,
16341 static SDValue LowerScalarVariableShift(SDValue Op, SelectionDAG &DAG,
16342 const X86Subtarget* Subtarget) {
16343 MVT VT = Op.getSimpleValueType();
16345 SDValue R = Op.getOperand(0);
16346 SDValue Amt = Op.getOperand(1);
16348 if ((VT == MVT::v2i64 && Op.getOpcode() != ISD::SRA) ||
16349 VT == MVT::v4i32 || VT == MVT::v8i16 ||
16350 (Subtarget->hasInt256() &&
16351 ((VT == MVT::v4i64 && Op.getOpcode() != ISD::SRA) ||
16352 VT == MVT::v8i32 || VT == MVT::v16i16)) ||
16353 (Subtarget->hasAVX512() && (VT == MVT::v8i64 || VT == MVT::v16i32))) {
16355 EVT EltVT = VT.getVectorElementType();
16357 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
16358 unsigned NumElts = VT.getVectorNumElements();
16360 for (i = 0; i != NumElts; ++i) {
16361 if (Amt.getOperand(i).getOpcode() == ISD::UNDEF)
16365 for (j = i; j != NumElts; ++j) {
16366 SDValue Arg = Amt.getOperand(j);
16367 if (Arg.getOpcode() == ISD::UNDEF) continue;
16368 if (Arg != Amt.getOperand(i))
16371 if (i != NumElts && j == NumElts)
16372 BaseShAmt = Amt.getOperand(i);
16374 if (Amt.getOpcode() == ISD::EXTRACT_SUBVECTOR)
16375 Amt = Amt.getOperand(0);
16376 if (Amt.getOpcode() == ISD::VECTOR_SHUFFLE &&
16377 cast<ShuffleVectorSDNode>(Amt)->isSplat()) {
16378 SDValue InVec = Amt.getOperand(0);
16379 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
16380 unsigned NumElts = InVec.getValueType().getVectorNumElements();
16382 for (; i != NumElts; ++i) {
16383 SDValue Arg = InVec.getOperand(i);
16384 if (Arg.getOpcode() == ISD::UNDEF) continue;
16388 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
16389 if (ConstantSDNode *C =
16390 dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
16391 unsigned SplatIdx =
16392 cast<ShuffleVectorSDNode>(Amt)->getSplatIndex();
16393 if (C->getZExtValue() == SplatIdx)
16394 BaseShAmt = InVec.getOperand(1);
16397 if (!BaseShAmt.getNode())
16398 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Amt,
16399 DAG.getIntPtrConstant(0));
16403 if (BaseShAmt.getNode()) {
16404 if (EltVT.bitsGT(MVT::i32))
16405 BaseShAmt = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, BaseShAmt);
16406 else if (EltVT.bitsLT(MVT::i32))
16407 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, BaseShAmt);
16409 switch (Op.getOpcode()) {
16411 llvm_unreachable("Unknown shift opcode!");
16413 switch (VT.SimpleTy) {
16414 default: return SDValue();
16423 return getTargetVShiftNode(X86ISD::VSHLI, dl, VT, R, BaseShAmt, DAG);
16426 switch (VT.SimpleTy) {
16427 default: return SDValue();
16434 return getTargetVShiftNode(X86ISD::VSRAI, dl, VT, R, BaseShAmt, DAG);
16437 switch (VT.SimpleTy) {
16438 default: return SDValue();
16447 return getTargetVShiftNode(X86ISD::VSRLI, dl, VT, R, BaseShAmt, DAG);
16453 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
16454 if (!Subtarget->is64Bit() &&
16455 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64) ||
16456 (Subtarget->hasAVX512() && VT == MVT::v8i64)) &&
16457 Amt.getOpcode() == ISD::BITCAST &&
16458 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
16459 Amt = Amt.getOperand(0);
16460 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
16461 VT.getVectorNumElements();
16462 std::vector<SDValue> Vals(Ratio);
16463 for (unsigned i = 0; i != Ratio; ++i)
16464 Vals[i] = Amt.getOperand(i);
16465 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
16466 for (unsigned j = 0; j != Ratio; ++j)
16467 if (Vals[j] != Amt.getOperand(i + j))
16470 switch (Op.getOpcode()) {
16472 llvm_unreachable("Unknown shift opcode!");
16474 return DAG.getNode(X86ISD::VSHL, dl, VT, R, Op.getOperand(1));
16476 return DAG.getNode(X86ISD::VSRL, dl, VT, R, Op.getOperand(1));
16478 return DAG.getNode(X86ISD::VSRA, dl, VT, R, Op.getOperand(1));
16485 static SDValue LowerShift(SDValue Op, const X86Subtarget* Subtarget,
16486 SelectionDAG &DAG) {
16487 MVT VT = Op.getSimpleValueType();
16489 SDValue R = Op.getOperand(0);
16490 SDValue Amt = Op.getOperand(1);
16493 assert(VT.isVector() && "Custom lowering only for vector shifts!");
16494 assert(Subtarget->hasSSE2() && "Only custom lower when we have SSE2!");
16496 V = LowerScalarImmediateShift(Op, DAG, Subtarget);
16500 V = LowerScalarVariableShift(Op, DAG, Subtarget);
16504 if (Subtarget->hasAVX512() && (VT == MVT::v16i32 || VT == MVT::v8i64))
16506 // AVX2 has VPSLLV/VPSRAV/VPSRLV.
16507 if (Subtarget->hasInt256()) {
16508 if (Op.getOpcode() == ISD::SRL &&
16509 (VT == MVT::v2i64 || VT == MVT::v4i32 ||
16510 VT == MVT::v4i64 || VT == MVT::v8i32))
16512 if (Op.getOpcode() == ISD::SHL &&
16513 (VT == MVT::v2i64 || VT == MVT::v4i32 ||
16514 VT == MVT::v4i64 || VT == MVT::v8i32))
16516 if (Op.getOpcode() == ISD::SRA && (VT == MVT::v4i32 || VT == MVT::v8i32))
16520 // If possible, lower this packed shift into a vector multiply instead of
16521 // expanding it into a sequence of scalar shifts.
16522 // Do this only if the vector shift count is a constant build_vector.
16523 if (Op.getOpcode() == ISD::SHL &&
16524 (VT == MVT::v8i16 || VT == MVT::v4i32 ||
16525 (Subtarget->hasInt256() && VT == MVT::v16i16)) &&
16526 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
16527 SmallVector<SDValue, 8> Elts;
16528 EVT SVT = VT.getScalarType();
16529 unsigned SVTBits = SVT.getSizeInBits();
16530 const APInt &One = APInt(SVTBits, 1);
16531 unsigned NumElems = VT.getVectorNumElements();
16533 for (unsigned i=0; i !=NumElems; ++i) {
16534 SDValue Op = Amt->getOperand(i);
16535 if (Op->getOpcode() == ISD::UNDEF) {
16536 Elts.push_back(Op);
16540 ConstantSDNode *ND = cast<ConstantSDNode>(Op);
16541 const APInt &C = APInt(SVTBits, ND->getAPIntValue().getZExtValue());
16542 uint64_t ShAmt = C.getZExtValue();
16543 if (ShAmt >= SVTBits) {
16544 Elts.push_back(DAG.getUNDEF(SVT));
16547 Elts.push_back(DAG.getConstant(One.shl(ShAmt), SVT));
16549 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
16550 return DAG.getNode(ISD::MUL, dl, VT, R, BV);
16553 // Lower SHL with variable shift amount.
16554 if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) {
16555 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(23, VT));
16557 Op = DAG.getNode(ISD::ADD, dl, VT, Op, DAG.getConstant(0x3f800000U, VT));
16558 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, Op);
16559 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op);
16560 return DAG.getNode(ISD::MUL, dl, VT, Op, R);
16563 // If possible, lower this shift as a sequence of two shifts by
16564 // constant plus a MOVSS/MOVSD instead of scalarizing it.
16566 // (v4i32 (srl A, (build_vector < X, Y, Y, Y>)))
16568 // Could be rewritten as:
16569 // (v4i32 (MOVSS (srl A, <Y,Y,Y,Y>), (srl A, <X,X,X,X>)))
16571 // The advantage is that the two shifts from the example would be
16572 // lowered as X86ISD::VSRLI nodes. This would be cheaper than scalarizing
16573 // the vector shift into four scalar shifts plus four pairs of vector
16575 if ((VT == MVT::v8i16 || VT == MVT::v4i32) &&
16576 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
16577 unsigned TargetOpcode = X86ISD::MOVSS;
16578 bool CanBeSimplified;
16579 // The splat value for the first packed shift (the 'X' from the example).
16580 SDValue Amt1 = Amt->getOperand(0);
16581 // The splat value for the second packed shift (the 'Y' from the example).
16582 SDValue Amt2 = (VT == MVT::v4i32) ? Amt->getOperand(1) :
16583 Amt->getOperand(2);
16585 // See if it is possible to replace this node with a sequence of
16586 // two shifts followed by a MOVSS/MOVSD
16587 if (VT == MVT::v4i32) {
16588 // Check if it is legal to use a MOVSS.
16589 CanBeSimplified = Amt2 == Amt->getOperand(2) &&
16590 Amt2 == Amt->getOperand(3);
16591 if (!CanBeSimplified) {
16592 // Otherwise, check if we can still simplify this node using a MOVSD.
16593 CanBeSimplified = Amt1 == Amt->getOperand(1) &&
16594 Amt->getOperand(2) == Amt->getOperand(3);
16595 TargetOpcode = X86ISD::MOVSD;
16596 Amt2 = Amt->getOperand(2);
16599 // Do similar checks for the case where the machine value type
16601 CanBeSimplified = Amt1 == Amt->getOperand(1);
16602 for (unsigned i=3; i != 8 && CanBeSimplified; ++i)
16603 CanBeSimplified = Amt2 == Amt->getOperand(i);
16605 if (!CanBeSimplified) {
16606 TargetOpcode = X86ISD::MOVSD;
16607 CanBeSimplified = true;
16608 Amt2 = Amt->getOperand(4);
16609 for (unsigned i=0; i != 4 && CanBeSimplified; ++i)
16610 CanBeSimplified = Amt1 == Amt->getOperand(i);
16611 for (unsigned j=4; j != 8 && CanBeSimplified; ++j)
16612 CanBeSimplified = Amt2 == Amt->getOperand(j);
16616 if (CanBeSimplified && isa<ConstantSDNode>(Amt1) &&
16617 isa<ConstantSDNode>(Amt2)) {
16618 // Replace this node with two shifts followed by a MOVSS/MOVSD.
16619 EVT CastVT = MVT::v4i32;
16621 DAG.getConstant(cast<ConstantSDNode>(Amt1)->getAPIntValue(), VT);
16622 SDValue Shift1 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat1);
16624 DAG.getConstant(cast<ConstantSDNode>(Amt2)->getAPIntValue(), VT);
16625 SDValue Shift2 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat2);
16626 if (TargetOpcode == X86ISD::MOVSD)
16627 CastVT = MVT::v2i64;
16628 SDValue BitCast1 = DAG.getNode(ISD::BITCAST, dl, CastVT, Shift1);
16629 SDValue BitCast2 = DAG.getNode(ISD::BITCAST, dl, CastVT, Shift2);
16630 SDValue Result = getTargetShuffleNode(TargetOpcode, dl, CastVT, BitCast2,
16632 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
16636 if (VT == MVT::v16i8 && Op->getOpcode() == ISD::SHL) {
16637 assert(Subtarget->hasSSE2() && "Need SSE2 for pslli/pcmpeq.");
16640 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(5, VT));
16641 Op = DAG.getNode(ISD::BITCAST, dl, VT, Op);
16643 // Turn 'a' into a mask suitable for VSELECT
16644 SDValue VSelM = DAG.getConstant(0x80, VT);
16645 SDValue OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
16646 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
16648 SDValue CM1 = DAG.getConstant(0x0f, VT);
16649 SDValue CM2 = DAG.getConstant(0x3f, VT);
16651 // r = VSELECT(r, psllw(r & (char16)15, 4), a);
16652 SDValue M = DAG.getNode(ISD::AND, dl, VT, R, CM1);
16653 M = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, MVT::v8i16, M, 4, DAG);
16654 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
16655 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
16658 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
16659 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
16660 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
16662 // r = VSELECT(r, psllw(r & (char16)63, 2), a);
16663 M = DAG.getNode(ISD::AND, dl, VT, R, CM2);
16664 M = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, MVT::v8i16, M, 2, DAG);
16665 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
16666 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
16669 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
16670 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
16671 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
16673 // return VSELECT(r, r+r, a);
16674 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel,
16675 DAG.getNode(ISD::ADD, dl, VT, R, R), R);
16679 // It's worth extending once and using the v8i32 shifts for 16-bit types, but
16680 // the extra overheads to get from v16i8 to v8i32 make the existing SSE
16681 // solution better.
16682 if (Subtarget->hasInt256() && VT == MVT::v8i16) {
16683 MVT NewVT = VT == MVT::v8i16 ? MVT::v8i32 : MVT::v16i16;
16685 Op.getOpcode() == ISD::SRA ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
16686 R = DAG.getNode(ExtOpc, dl, NewVT, R);
16687 Amt = DAG.getNode(ISD::ANY_EXTEND, dl, NewVT, Amt);
16688 return DAG.getNode(ISD::TRUNCATE, dl, VT,
16689 DAG.getNode(Op.getOpcode(), dl, NewVT, R, Amt));
16692 // Decompose 256-bit shifts into smaller 128-bit shifts.
16693 if (VT.is256BitVector()) {
16694 unsigned NumElems = VT.getVectorNumElements();
16695 MVT EltVT = VT.getVectorElementType();
16696 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
16698 // Extract the two vectors
16699 SDValue V1 = Extract128BitVector(R, 0, DAG, dl);
16700 SDValue V2 = Extract128BitVector(R, NumElems/2, DAG, dl);
16702 // Recreate the shift amount vectors
16703 SDValue Amt1, Amt2;
16704 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
16705 // Constant shift amount
16706 SmallVector<SDValue, 4> Amt1Csts;
16707 SmallVector<SDValue, 4> Amt2Csts;
16708 for (unsigned i = 0; i != NumElems/2; ++i)
16709 Amt1Csts.push_back(Amt->getOperand(i));
16710 for (unsigned i = NumElems/2; i != NumElems; ++i)
16711 Amt2Csts.push_back(Amt->getOperand(i));
16713 Amt1 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt1Csts);
16714 Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt2Csts);
16716 // Variable shift amount
16717 Amt1 = Extract128BitVector(Amt, 0, DAG, dl);
16718 Amt2 = Extract128BitVector(Amt, NumElems/2, DAG, dl);
16721 // Issue new vector shifts for the smaller types
16722 V1 = DAG.getNode(Op.getOpcode(), dl, NewVT, V1, Amt1);
16723 V2 = DAG.getNode(Op.getOpcode(), dl, NewVT, V2, Amt2);
16725 // Concatenate the result back
16726 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, V1, V2);
16732 static SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) {
16733 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
16734 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
16735 // looks for this combo and may remove the "setcc" instruction if the "setcc"
16736 // has only one use.
16737 SDNode *N = Op.getNode();
16738 SDValue LHS = N->getOperand(0);
16739 SDValue RHS = N->getOperand(1);
16740 unsigned BaseOp = 0;
16743 switch (Op.getOpcode()) {
16744 default: llvm_unreachable("Unknown ovf instruction!");
16746 // A subtract of one will be selected as a INC. Note that INC doesn't
16747 // set CF, so we can't do this for UADDO.
16748 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
16750 BaseOp = X86ISD::INC;
16751 Cond = X86::COND_O;
16754 BaseOp = X86ISD::ADD;
16755 Cond = X86::COND_O;
16758 BaseOp = X86ISD::ADD;
16759 Cond = X86::COND_B;
16762 // A subtract of one will be selected as a DEC. Note that DEC doesn't
16763 // set CF, so we can't do this for USUBO.
16764 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
16766 BaseOp = X86ISD::DEC;
16767 Cond = X86::COND_O;
16770 BaseOp = X86ISD::SUB;
16771 Cond = X86::COND_O;
16774 BaseOp = X86ISD::SUB;
16775 Cond = X86::COND_B;
16778 BaseOp = X86ISD::SMUL;
16779 Cond = X86::COND_O;
16781 case ISD::UMULO: { // i64, i8 = umulo lhs, rhs --> i64, i64, i32 umul lhs,rhs
16782 SDVTList VTs = DAG.getVTList(N->getValueType(0), N->getValueType(0),
16784 SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS);
16787 DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
16788 DAG.getConstant(X86::COND_O, MVT::i32),
16789 SDValue(Sum.getNode(), 2));
16791 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
16795 // Also sets EFLAGS.
16796 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
16797 SDValue Sum = DAG.getNode(BaseOp, DL, VTs, LHS, RHS);
16800 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1),
16801 DAG.getConstant(Cond, MVT::i32),
16802 SDValue(Sum.getNode(), 1));
16804 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
16807 SDValue X86TargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
16808 SelectionDAG &DAG) const {
16810 EVT ExtraVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
16811 MVT VT = Op.getSimpleValueType();
16813 if (!Subtarget->hasSSE2() || !VT.isVector())
16816 unsigned BitsDiff = VT.getScalarType().getSizeInBits() -
16817 ExtraVT.getScalarType().getSizeInBits();
16819 switch (VT.SimpleTy) {
16820 default: return SDValue();
16823 if (!Subtarget->hasFp256())
16825 if (!Subtarget->hasInt256()) {
16826 // needs to be split
16827 unsigned NumElems = VT.getVectorNumElements();
16829 // Extract the LHS vectors
16830 SDValue LHS = Op.getOperand(0);
16831 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
16832 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
16834 MVT EltVT = VT.getVectorElementType();
16835 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
16837 EVT ExtraEltVT = ExtraVT.getVectorElementType();
16838 unsigned ExtraNumElems = ExtraVT.getVectorNumElements();
16839 ExtraVT = EVT::getVectorVT(*DAG.getContext(), ExtraEltVT,
16841 SDValue Extra = DAG.getValueType(ExtraVT);
16843 LHS1 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, Extra);
16844 LHS2 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, Extra);
16846 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, LHS1, LHS2);
16851 SDValue Op0 = Op.getOperand(0);
16852 SDValue Op00 = Op0.getOperand(0);
16854 // Hopefully, this VECTOR_SHUFFLE is just a VZEXT.
16855 if (Op0.getOpcode() == ISD::BITCAST &&
16856 Op00.getOpcode() == ISD::VECTOR_SHUFFLE) {
16857 // (sext (vzext x)) -> (vsext x)
16858 Tmp1 = LowerVectorIntExtend(Op00, Subtarget, DAG);
16859 if (Tmp1.getNode()) {
16860 EVT ExtraEltVT = ExtraVT.getVectorElementType();
16861 // This folding is only valid when the in-reg type is a vector of i8,
16863 if (ExtraEltVT == MVT::i8 || ExtraEltVT == MVT::i16 ||
16864 ExtraEltVT == MVT::i32) {
16865 SDValue Tmp1Op0 = Tmp1.getOperand(0);
16866 assert(Tmp1Op0.getOpcode() == X86ISD::VZEXT &&
16867 "This optimization is invalid without a VZEXT.");
16868 return DAG.getNode(X86ISD::VSEXT, dl, VT, Tmp1Op0.getOperand(0));
16874 // If the above didn't work, then just use Shift-Left + Shift-Right.
16875 Tmp1 = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, Op0, BitsDiff,
16877 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, Tmp1, BitsDiff,
16883 static SDValue LowerATOMIC_FENCE(SDValue Op, const X86Subtarget *Subtarget,
16884 SelectionDAG &DAG) {
16886 AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>(
16887 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue());
16888 SynchronizationScope FenceScope = static_cast<SynchronizationScope>(
16889 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
16891 // The only fence that needs an instruction is a sequentially-consistent
16892 // cross-thread fence.
16893 if (FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread) {
16894 // Use mfence if we have SSE2 or we're on x86-64 (even if we asked for
16895 // no-sse2). There isn't any reason to disable it if the target processor
16897 if (Subtarget->hasSSE2() || Subtarget->is64Bit())
16898 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
16900 SDValue Chain = Op.getOperand(0);
16901 SDValue Zero = DAG.getConstant(0, MVT::i32);
16903 DAG.getRegister(X86::ESP, MVT::i32), // Base
16904 DAG.getTargetConstant(1, MVT::i8), // Scale
16905 DAG.getRegister(0, MVT::i32), // Index
16906 DAG.getTargetConstant(0, MVT::i32), // Disp
16907 DAG.getRegister(0, MVT::i32), // Segment.
16911 SDNode *Res = DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops);
16912 return SDValue(Res, 0);
16915 // MEMBARRIER is a compiler barrier; it codegens to a no-op.
16916 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
16919 static SDValue LowerCMP_SWAP(SDValue Op, const X86Subtarget *Subtarget,
16920 SelectionDAG &DAG) {
16921 MVT T = Op.getSimpleValueType();
16925 switch(T.SimpleTy) {
16926 default: llvm_unreachable("Invalid value type!");
16927 case MVT::i8: Reg = X86::AL; size = 1; break;
16928 case MVT::i16: Reg = X86::AX; size = 2; break;
16929 case MVT::i32: Reg = X86::EAX; size = 4; break;
16931 assert(Subtarget->is64Bit() && "Node not type legal!");
16932 Reg = X86::RAX; size = 8;
16935 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg,
16936 Op.getOperand(2), SDValue());
16937 SDValue Ops[] = { cpIn.getValue(0),
16940 DAG.getTargetConstant(size, MVT::i8),
16941 cpIn.getValue(1) };
16942 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
16943 MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand();
16944 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys,
16948 DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1));
16949 SDValue EFLAGS = DAG.getCopyFromReg(cpOut.getValue(1), DL, X86::EFLAGS,
16950 MVT::i32, cpOut.getValue(2));
16951 SDValue Success = DAG.getNode(X86ISD::SETCC, DL, Op->getValueType(1),
16952 DAG.getConstant(X86::COND_E, MVT::i8), EFLAGS);
16954 DAG.ReplaceAllUsesOfValueWith(Op.getValue(0), cpOut);
16955 DAG.ReplaceAllUsesOfValueWith(Op.getValue(1), Success);
16956 DAG.ReplaceAllUsesOfValueWith(Op.getValue(2), EFLAGS.getValue(1));
16960 static SDValue LowerBITCAST(SDValue Op, const X86Subtarget *Subtarget,
16961 SelectionDAG &DAG) {
16962 MVT SrcVT = Op.getOperand(0).getSimpleValueType();
16963 MVT DstVT = Op.getSimpleValueType();
16965 if (SrcVT == MVT::v2i32 || SrcVT == MVT::v4i16 || SrcVT == MVT::v8i8) {
16966 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
16967 if (DstVT != MVT::f64)
16968 // This conversion needs to be expanded.
16971 SDValue InVec = Op->getOperand(0);
16973 unsigned NumElts = SrcVT.getVectorNumElements();
16974 EVT SVT = SrcVT.getVectorElementType();
16976 // Widen the vector in input in the case of MVT::v2i32.
16977 // Example: from MVT::v2i32 to MVT::v4i32.
16978 SmallVector<SDValue, 16> Elts;
16979 for (unsigned i = 0, e = NumElts; i != e; ++i)
16980 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT, InVec,
16981 DAG.getIntPtrConstant(i)));
16983 // Explicitly mark the extra elements as Undef.
16984 SDValue Undef = DAG.getUNDEF(SVT);
16985 for (unsigned i = NumElts, e = NumElts * 2; i != e; ++i)
16986 Elts.push_back(Undef);
16988 EVT NewVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
16989 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Elts);
16990 SDValue ToV2F64 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, BV);
16991 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, ToV2F64,
16992 DAG.getIntPtrConstant(0));
16995 assert(Subtarget->is64Bit() && !Subtarget->hasSSE2() &&
16996 Subtarget->hasMMX() && "Unexpected custom BITCAST");
16997 assert((DstVT == MVT::i64 ||
16998 (DstVT.isVector() && DstVT.getSizeInBits()==64)) &&
16999 "Unexpected custom BITCAST");
17000 // i64 <=> MMX conversions are Legal.
17001 if (SrcVT==MVT::i64 && DstVT.isVector())
17003 if (DstVT==MVT::i64 && SrcVT.isVector())
17005 // MMX <=> MMX conversions are Legal.
17006 if (SrcVT.isVector() && DstVT.isVector())
17008 // All other conversions need to be expanded.
17012 static SDValue LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) {
17013 SDNode *Node = Op.getNode();
17015 EVT T = Node->getValueType(0);
17016 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
17017 DAG.getConstant(0, T), Node->getOperand(2));
17018 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
17019 cast<AtomicSDNode>(Node)->getMemoryVT(),
17020 Node->getOperand(0),
17021 Node->getOperand(1), negOp,
17022 cast<AtomicSDNode>(Node)->getMemOperand(),
17023 cast<AtomicSDNode>(Node)->getOrdering(),
17024 cast<AtomicSDNode>(Node)->getSynchScope());
17027 static SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) {
17028 SDNode *Node = Op.getNode();
17030 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
17032 // Convert seq_cst store -> xchg
17033 // Convert wide store -> swap (-> cmpxchg8b/cmpxchg16b)
17034 // FIXME: On 32-bit, store -> fist or movq would be more efficient
17035 // (The only way to get a 16-byte store is cmpxchg16b)
17036 // FIXME: 16-byte ATOMIC_SWAP isn't actually hooked up at the moment.
17037 if (cast<AtomicSDNode>(Node)->getOrdering() == SequentiallyConsistent ||
17038 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
17039 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
17040 cast<AtomicSDNode>(Node)->getMemoryVT(),
17041 Node->getOperand(0),
17042 Node->getOperand(1), Node->getOperand(2),
17043 cast<AtomicSDNode>(Node)->getMemOperand(),
17044 cast<AtomicSDNode>(Node)->getOrdering(),
17045 cast<AtomicSDNode>(Node)->getSynchScope());
17046 return Swap.getValue(1);
17048 // Other atomic stores have a simple pattern.
17052 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
17053 EVT VT = Op.getNode()->getSimpleValueType(0);
17055 // Let legalize expand this if it isn't a legal type yet.
17056 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
17059 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
17062 bool ExtraOp = false;
17063 switch (Op.getOpcode()) {
17064 default: llvm_unreachable("Invalid code");
17065 case ISD::ADDC: Opc = X86ISD::ADD; break;
17066 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break;
17067 case ISD::SUBC: Opc = X86ISD::SUB; break;
17068 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break;
17072 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
17074 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
17075 Op.getOperand(1), Op.getOperand(2));
17078 static SDValue LowerFSINCOS(SDValue Op, const X86Subtarget *Subtarget,
17079 SelectionDAG &DAG) {
17080 assert(Subtarget->isTargetDarwin() && Subtarget->is64Bit());
17082 // For MacOSX, we want to call an alternative entry point: __sincos_stret,
17083 // which returns the values as { float, float } (in XMM0) or
17084 // { double, double } (which is returned in XMM0, XMM1).
17086 SDValue Arg = Op.getOperand(0);
17087 EVT ArgVT = Arg.getValueType();
17088 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
17090 TargetLowering::ArgListTy Args;
17091 TargetLowering::ArgListEntry Entry;
17095 Entry.isSExt = false;
17096 Entry.isZExt = false;
17097 Args.push_back(Entry);
17099 bool isF64 = ArgVT == MVT::f64;
17100 // Only optimize x86_64 for now. i386 is a bit messy. For f32,
17101 // the small struct {f32, f32} is returned in (eax, edx). For f64,
17102 // the results are returned via SRet in memory.
17103 const char *LibcallName = isF64 ? "__sincos_stret" : "__sincosf_stret";
17104 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
17105 SDValue Callee = DAG.getExternalSymbol(LibcallName, TLI.getPointerTy());
17107 Type *RetTy = isF64
17108 ? (Type*)StructType::get(ArgTy, ArgTy, NULL)
17109 : (Type*)VectorType::get(ArgTy, 4);
17111 TargetLowering::CallLoweringInfo CLI(DAG);
17112 CLI.setDebugLoc(dl).setChain(DAG.getEntryNode())
17113 .setCallee(CallingConv::C, RetTy, Callee, std::move(Args), 0);
17115 std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI);
17118 // Returned in xmm0 and xmm1.
17119 return CallResult.first;
17121 // Returned in bits 0:31 and 32:64 xmm0.
17122 SDValue SinVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
17123 CallResult.first, DAG.getIntPtrConstant(0));
17124 SDValue CosVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
17125 CallResult.first, DAG.getIntPtrConstant(1));
17126 SDVTList Tys = DAG.getVTList(ArgVT, ArgVT);
17127 return DAG.getNode(ISD::MERGE_VALUES, dl, Tys, SinVal, CosVal);
17130 /// LowerOperation - Provide custom lowering hooks for some operations.
17132 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
17133 switch (Op.getOpcode()) {
17134 default: llvm_unreachable("Should not custom lower this!");
17135 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op,DAG);
17136 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, Subtarget, DAG);
17137 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS:
17138 return LowerCMP_SWAP(Op, Subtarget, DAG);
17139 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
17140 case ISD::ATOMIC_STORE: return LowerATOMIC_STORE(Op,DAG);
17141 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
17142 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
17143 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
17144 case ISD::VSELECT: return LowerVSELECT(Op, DAG);
17145 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
17146 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
17147 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op,Subtarget,DAG);
17148 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, Subtarget,DAG);
17149 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
17150 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
17151 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
17152 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
17153 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
17154 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
17155 case ISD::SHL_PARTS:
17156 case ISD::SRA_PARTS:
17157 case ISD::SRL_PARTS: return LowerShiftParts(Op, DAG);
17158 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
17159 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
17160 case ISD::TRUNCATE: return LowerTRUNCATE(Op, DAG);
17161 case ISD::ZERO_EXTEND: return LowerZERO_EXTEND(Op, Subtarget, DAG);
17162 case ISD::SIGN_EXTEND: return LowerSIGN_EXTEND(Op, Subtarget, DAG);
17163 case ISD::ANY_EXTEND: return LowerANY_EXTEND(Op, Subtarget, DAG);
17164 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
17165 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
17166 case ISD::FP_EXTEND: return LowerFP_EXTEND(Op, DAG);
17167 case ISD::LOAD: return LowerExtendedLoad(Op, Subtarget, DAG);
17168 case ISD::FABS: return LowerFABS(Op, DAG);
17169 case ISD::FNEG: return LowerFNEG(Op, DAG);
17170 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
17171 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG);
17172 case ISD::SETCC: return LowerSETCC(Op, DAG);
17173 case ISD::SELECT: return LowerSELECT(Op, DAG);
17174 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
17175 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
17176 case ISD::VASTART: return LowerVASTART(Op, DAG);
17177 case ISD::VAARG: return LowerVAARG(Op, DAG);
17178 case ISD::VACOPY: return LowerVACOPY(Op, Subtarget, DAG);
17179 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
17180 case ISD::INTRINSIC_VOID:
17181 case ISD::INTRINSIC_W_CHAIN: return LowerINTRINSIC_W_CHAIN(Op, Subtarget, DAG);
17182 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
17183 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
17184 case ISD::FRAME_TO_ARGS_OFFSET:
17185 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
17186 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
17187 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
17188 case ISD::EH_SJLJ_SETJMP: return lowerEH_SJLJ_SETJMP(Op, DAG);
17189 case ISD::EH_SJLJ_LONGJMP: return lowerEH_SJLJ_LONGJMP(Op, DAG);
17190 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
17191 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
17192 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
17193 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
17194 case ISD::CTLZ_ZERO_UNDEF: return LowerCTLZ_ZERO_UNDEF(Op, DAG);
17195 case ISD::CTTZ: return LowerCTTZ(Op, DAG);
17196 case ISD::MUL: return LowerMUL(Op, Subtarget, DAG);
17197 case ISD::UMUL_LOHI:
17198 case ISD::SMUL_LOHI: return LowerMUL_LOHI(Op, Subtarget, DAG);
17201 case ISD::SHL: return LowerShift(Op, Subtarget, DAG);
17207 case ISD::UMULO: return LowerXALUO(Op, DAG);
17208 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, Subtarget,DAG);
17209 case ISD::BITCAST: return LowerBITCAST(Op, Subtarget, DAG);
17213 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
17214 case ISD::ADD: return LowerADD(Op, DAG);
17215 case ISD::SUB: return LowerSUB(Op, DAG);
17216 case ISD::FSINCOS: return LowerFSINCOS(Op, Subtarget, DAG);
17220 static void ReplaceATOMIC_LOAD(SDNode *Node,
17221 SmallVectorImpl<SDValue> &Results,
17222 SelectionDAG &DAG) {
17224 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
17226 // Convert wide load -> cmpxchg8b/cmpxchg16b
17227 // FIXME: On 32-bit, load -> fild or movq would be more efficient
17228 // (The only way to get a 16-byte load is cmpxchg16b)
17229 // FIXME: 16-byte ATOMIC_CMP_SWAP isn't actually hooked up at the moment.
17230 SDValue Zero = DAG.getConstant(0, VT);
17231 SDVTList VTs = DAG.getVTList(VT, MVT::i1, MVT::Other);
17233 DAG.getAtomicCmpSwap(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, dl, VT, VTs,
17234 Node->getOperand(0), Node->getOperand(1), Zero, Zero,
17235 cast<AtomicSDNode>(Node)->getMemOperand(),
17236 cast<AtomicSDNode>(Node)->getOrdering(),
17237 cast<AtomicSDNode>(Node)->getOrdering(),
17238 cast<AtomicSDNode>(Node)->getSynchScope());
17239 Results.push_back(Swap.getValue(0));
17240 Results.push_back(Swap.getValue(2));
17243 /// ReplaceNodeResults - Replace a node with an illegal result type
17244 /// with a new node built out of custom code.
17245 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
17246 SmallVectorImpl<SDValue>&Results,
17247 SelectionDAG &DAG) const {
17249 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
17250 switch (N->getOpcode()) {
17252 llvm_unreachable("Do not know how to custom type legalize this operation!");
17253 case ISD::SIGN_EXTEND_INREG:
17258 // We don't want to expand or promote these.
17265 case ISD::UDIVREM: {
17266 SDValue V = LowerWin64_i128OP(SDValue(N,0), DAG);
17267 Results.push_back(V);
17270 case ISD::FP_TO_SINT:
17271 case ISD::FP_TO_UINT: {
17272 bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT;
17274 if (!IsSigned && !isIntegerTypeFTOL(SDValue(N, 0).getValueType()))
17277 std::pair<SDValue,SDValue> Vals =
17278 FP_TO_INTHelper(SDValue(N, 0), DAG, IsSigned, /*IsReplace=*/ true);
17279 SDValue FIST = Vals.first, StackSlot = Vals.second;
17280 if (FIST.getNode()) {
17281 EVT VT = N->getValueType(0);
17282 // Return a load from the stack slot.
17283 if (StackSlot.getNode())
17284 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot,
17285 MachinePointerInfo(),
17286 false, false, false, 0));
17288 Results.push_back(FIST);
17292 case ISD::UINT_TO_FP: {
17293 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
17294 if (N->getOperand(0).getValueType() != MVT::v2i32 ||
17295 N->getValueType(0) != MVT::v2f32)
17297 SDValue ZExtIn = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v2i64,
17299 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
17301 SDValue VBias = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2f64, Bias, Bias);
17302 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64, ZExtIn,
17303 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, VBias));
17304 Or = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or);
17305 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, Or, VBias);
17306 Results.push_back(DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, Sub));
17309 case ISD::FP_ROUND: {
17310 if (!TLI.isTypeLegal(N->getOperand(0).getValueType()))
17312 SDValue V = DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, N->getOperand(0));
17313 Results.push_back(V);
17316 case ISD::INTRINSIC_W_CHAIN: {
17317 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
17319 default : llvm_unreachable("Do not know how to custom type "
17320 "legalize this intrinsic operation!");
17321 case Intrinsic::x86_rdtsc:
17322 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
17324 case Intrinsic::x86_rdtscp:
17325 return getReadTimeStampCounter(N, dl, X86ISD::RDTSCP_DAG, DAG, Subtarget,
17327 case Intrinsic::x86_rdpmc:
17328 return getReadPerformanceCounter(N, dl, DAG, Subtarget, Results);
17331 case ISD::READCYCLECOUNTER: {
17332 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
17335 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS: {
17336 EVT T = N->getValueType(0);
17337 assert((T == MVT::i64 || T == MVT::i128) && "can only expand cmpxchg pair");
17338 bool Regs64bit = T == MVT::i128;
17339 EVT HalfT = Regs64bit ? MVT::i64 : MVT::i32;
17340 SDValue cpInL, cpInH;
17341 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
17342 DAG.getConstant(0, HalfT));
17343 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
17344 DAG.getConstant(1, HalfT));
17345 cpInL = DAG.getCopyToReg(N->getOperand(0), dl,
17346 Regs64bit ? X86::RAX : X86::EAX,
17348 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl,
17349 Regs64bit ? X86::RDX : X86::EDX,
17350 cpInH, cpInL.getValue(1));
17351 SDValue swapInL, swapInH;
17352 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
17353 DAG.getConstant(0, HalfT));
17354 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
17355 DAG.getConstant(1, HalfT));
17356 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl,
17357 Regs64bit ? X86::RBX : X86::EBX,
17358 swapInL, cpInH.getValue(1));
17359 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl,
17360 Regs64bit ? X86::RCX : X86::ECX,
17361 swapInH, swapInL.getValue(1));
17362 SDValue Ops[] = { swapInH.getValue(0),
17364 swapInH.getValue(1) };
17365 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
17366 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand();
17367 unsigned Opcode = Regs64bit ? X86ISD::LCMPXCHG16_DAG :
17368 X86ISD::LCMPXCHG8_DAG;
17369 SDValue Result = DAG.getMemIntrinsicNode(Opcode, dl, Tys, Ops, T, MMO);
17370 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl,
17371 Regs64bit ? X86::RAX : X86::EAX,
17372 HalfT, Result.getValue(1));
17373 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl,
17374 Regs64bit ? X86::RDX : X86::EDX,
17375 HalfT, cpOutL.getValue(2));
17376 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
17378 SDValue EFLAGS = DAG.getCopyFromReg(cpOutH.getValue(1), dl, X86::EFLAGS,
17379 MVT::i32, cpOutH.getValue(2));
17381 DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
17382 DAG.getConstant(X86::COND_E, MVT::i8), EFLAGS);
17383 Success = DAG.getZExtOrTrunc(Success, dl, N->getValueType(1));
17385 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, T, OpsF));
17386 Results.push_back(Success);
17387 Results.push_back(EFLAGS.getValue(1));
17390 case ISD::ATOMIC_SWAP:
17391 case ISD::ATOMIC_LOAD_ADD:
17392 case ISD::ATOMIC_LOAD_SUB:
17393 case ISD::ATOMIC_LOAD_AND:
17394 case ISD::ATOMIC_LOAD_OR:
17395 case ISD::ATOMIC_LOAD_XOR:
17396 case ISD::ATOMIC_LOAD_NAND:
17397 case ISD::ATOMIC_LOAD_MIN:
17398 case ISD::ATOMIC_LOAD_MAX:
17399 case ISD::ATOMIC_LOAD_UMIN:
17400 case ISD::ATOMIC_LOAD_UMAX:
17401 // Delegate to generic TypeLegalization. Situations we can really handle
17402 // should have already been dealt with by X86AtomicExpandPass.cpp.
17404 case ISD::ATOMIC_LOAD: {
17405 ReplaceATOMIC_LOAD(N, Results, DAG);
17408 case ISD::BITCAST: {
17409 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
17410 EVT DstVT = N->getValueType(0);
17411 EVT SrcVT = N->getOperand(0)->getValueType(0);
17413 if (SrcVT != MVT::f64 ||
17414 (DstVT != MVT::v2i32 && DstVT != MVT::v4i16 && DstVT != MVT::v8i8))
17417 unsigned NumElts = DstVT.getVectorNumElements();
17418 EVT SVT = DstVT.getVectorElementType();
17419 EVT WiderVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
17420 SDValue Expanded = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
17421 MVT::v2f64, N->getOperand(0));
17422 SDValue ToVecInt = DAG.getNode(ISD::BITCAST, dl, WiderVT, Expanded);
17424 if (ExperimentalVectorWideningLegalization) {
17425 // If we are legalizing vectors by widening, we already have the desired
17426 // legal vector type, just return it.
17427 Results.push_back(ToVecInt);
17431 SmallVector<SDValue, 8> Elts;
17432 for (unsigned i = 0, e = NumElts; i != e; ++i)
17433 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT,
17434 ToVecInt, DAG.getIntPtrConstant(i)));
17436 Results.push_back(DAG.getNode(ISD::BUILD_VECTOR, dl, DstVT, Elts));
17441 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
17443 default: return nullptr;
17444 case X86ISD::BSF: return "X86ISD::BSF";
17445 case X86ISD::BSR: return "X86ISD::BSR";
17446 case X86ISD::SHLD: return "X86ISD::SHLD";
17447 case X86ISD::SHRD: return "X86ISD::SHRD";
17448 case X86ISD::FAND: return "X86ISD::FAND";
17449 case X86ISD::FANDN: return "X86ISD::FANDN";
17450 case X86ISD::FOR: return "X86ISD::FOR";
17451 case X86ISD::FXOR: return "X86ISD::FXOR";
17452 case X86ISD::FSRL: return "X86ISD::FSRL";
17453 case X86ISD::FILD: return "X86ISD::FILD";
17454 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
17455 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
17456 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
17457 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
17458 case X86ISD::FLD: return "X86ISD::FLD";
17459 case X86ISD::FST: return "X86ISD::FST";
17460 case X86ISD::CALL: return "X86ISD::CALL";
17461 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
17462 case X86ISD::RDTSCP_DAG: return "X86ISD::RDTSCP_DAG";
17463 case X86ISD::RDPMC_DAG: return "X86ISD::RDPMC_DAG";
17464 case X86ISD::BT: return "X86ISD::BT";
17465 case X86ISD::CMP: return "X86ISD::CMP";
17466 case X86ISD::COMI: return "X86ISD::COMI";
17467 case X86ISD::UCOMI: return "X86ISD::UCOMI";
17468 case X86ISD::CMPM: return "X86ISD::CMPM";
17469 case X86ISD::CMPMU: return "X86ISD::CMPMU";
17470 case X86ISD::SETCC: return "X86ISD::SETCC";
17471 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY";
17472 case X86ISD::FSETCC: return "X86ISD::FSETCC";
17473 case X86ISD::CMOV: return "X86ISD::CMOV";
17474 case X86ISD::BRCOND: return "X86ISD::BRCOND";
17475 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
17476 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
17477 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
17478 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
17479 case X86ISD::Wrapper: return "X86ISD::Wrapper";
17480 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
17481 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
17482 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
17483 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
17484 case X86ISD::PINSRB: return "X86ISD::PINSRB";
17485 case X86ISD::PINSRW: return "X86ISD::PINSRW";
17486 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
17487 case X86ISD::ANDNP: return "X86ISD::ANDNP";
17488 case X86ISD::PSIGN: return "X86ISD::PSIGN";
17489 case X86ISD::BLENDV: return "X86ISD::BLENDV";
17490 case X86ISD::BLENDI: return "X86ISD::BLENDI";
17491 case X86ISD::SUBUS: return "X86ISD::SUBUS";
17492 case X86ISD::HADD: return "X86ISD::HADD";
17493 case X86ISD::HSUB: return "X86ISD::HSUB";
17494 case X86ISD::FHADD: return "X86ISD::FHADD";
17495 case X86ISD::FHSUB: return "X86ISD::FHSUB";
17496 case X86ISD::UMAX: return "X86ISD::UMAX";
17497 case X86ISD::UMIN: return "X86ISD::UMIN";
17498 case X86ISD::SMAX: return "X86ISD::SMAX";
17499 case X86ISD::SMIN: return "X86ISD::SMIN";
17500 case X86ISD::FMAX: return "X86ISD::FMAX";
17501 case X86ISD::FMIN: return "X86ISD::FMIN";
17502 case X86ISD::FMAXC: return "X86ISD::FMAXC";
17503 case X86ISD::FMINC: return "X86ISD::FMINC";
17504 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
17505 case X86ISD::FRCP: return "X86ISD::FRCP";
17506 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
17507 case X86ISD::TLSBASEADDR: return "X86ISD::TLSBASEADDR";
17508 case X86ISD::TLSCALL: return "X86ISD::TLSCALL";
17509 case X86ISD::EH_SJLJ_SETJMP: return "X86ISD::EH_SJLJ_SETJMP";
17510 case X86ISD::EH_SJLJ_LONGJMP: return "X86ISD::EH_SJLJ_LONGJMP";
17511 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
17512 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
17513 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
17514 case X86ISD::FNSTSW16r: return "X86ISD::FNSTSW16r";
17515 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
17516 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
17517 case X86ISD::LCMPXCHG16_DAG: return "X86ISD::LCMPXCHG16_DAG";
17518 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
17519 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
17520 case X86ISD::VZEXT: return "X86ISD::VZEXT";
17521 case X86ISD::VSEXT: return "X86ISD::VSEXT";
17522 case X86ISD::VTRUNC: return "X86ISD::VTRUNC";
17523 case X86ISD::VTRUNCM: return "X86ISD::VTRUNCM";
17524 case X86ISD::VINSERT: return "X86ISD::VINSERT";
17525 case X86ISD::VFPEXT: return "X86ISD::VFPEXT";
17526 case X86ISD::VFPROUND: return "X86ISD::VFPROUND";
17527 case X86ISD::VSHLDQ: return "X86ISD::VSHLDQ";
17528 case X86ISD::VSRLDQ: return "X86ISD::VSRLDQ";
17529 case X86ISD::VSHL: return "X86ISD::VSHL";
17530 case X86ISD::VSRL: return "X86ISD::VSRL";
17531 case X86ISD::VSRA: return "X86ISD::VSRA";
17532 case X86ISD::VSHLI: return "X86ISD::VSHLI";
17533 case X86ISD::VSRLI: return "X86ISD::VSRLI";
17534 case X86ISD::VSRAI: return "X86ISD::VSRAI";
17535 case X86ISD::CMPP: return "X86ISD::CMPP";
17536 case X86ISD::PCMPEQ: return "X86ISD::PCMPEQ";
17537 case X86ISD::PCMPGT: return "X86ISD::PCMPGT";
17538 case X86ISD::PCMPEQM: return "X86ISD::PCMPEQM";
17539 case X86ISD::PCMPGTM: return "X86ISD::PCMPGTM";
17540 case X86ISD::ADD: return "X86ISD::ADD";
17541 case X86ISD::SUB: return "X86ISD::SUB";
17542 case X86ISD::ADC: return "X86ISD::ADC";
17543 case X86ISD::SBB: return "X86ISD::SBB";
17544 case X86ISD::SMUL: return "X86ISD::SMUL";
17545 case X86ISD::UMUL: return "X86ISD::UMUL";
17546 case X86ISD::INC: return "X86ISD::INC";
17547 case X86ISD::DEC: return "X86ISD::DEC";
17548 case X86ISD::OR: return "X86ISD::OR";
17549 case X86ISD::XOR: return "X86ISD::XOR";
17550 case X86ISD::AND: return "X86ISD::AND";
17551 case X86ISD::BEXTR: return "X86ISD::BEXTR";
17552 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
17553 case X86ISD::PTEST: return "X86ISD::PTEST";
17554 case X86ISD::TESTP: return "X86ISD::TESTP";
17555 case X86ISD::TESTM: return "X86ISD::TESTM";
17556 case X86ISD::TESTNM: return "X86ISD::TESTNM";
17557 case X86ISD::KORTEST: return "X86ISD::KORTEST";
17558 case X86ISD::PACKSS: return "X86ISD::PACKSS";
17559 case X86ISD::PACKUS: return "X86ISD::PACKUS";
17560 case X86ISD::PALIGNR: return "X86ISD::PALIGNR";
17561 case X86ISD::VALIGN: return "X86ISD::VALIGN";
17562 case X86ISD::PSHUFD: return "X86ISD::PSHUFD";
17563 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW";
17564 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW";
17565 case X86ISD::SHUFP: return "X86ISD::SHUFP";
17566 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS";
17567 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD";
17568 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS";
17569 case X86ISD::MOVLPS: return "X86ISD::MOVLPS";
17570 case X86ISD::MOVLPD: return "X86ISD::MOVLPD";
17571 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP";
17572 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP";
17573 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP";
17574 case X86ISD::MOVSD: return "X86ISD::MOVSD";
17575 case X86ISD::MOVSS: return "X86ISD::MOVSS";
17576 case X86ISD::UNPCKL: return "X86ISD::UNPCKL";
17577 case X86ISD::UNPCKH: return "X86ISD::UNPCKH";
17578 case X86ISD::VBROADCAST: return "X86ISD::VBROADCAST";
17579 case X86ISD::VBROADCASTM: return "X86ISD::VBROADCASTM";
17580 case X86ISD::VEXTRACT: return "X86ISD::VEXTRACT";
17581 case X86ISD::VPERMILP: return "X86ISD::VPERMILP";
17582 case X86ISD::VPERM2X128: return "X86ISD::VPERM2X128";
17583 case X86ISD::VPERMV: return "X86ISD::VPERMV";
17584 case X86ISD::VPERMV3: return "X86ISD::VPERMV3";
17585 case X86ISD::VPERMIV3: return "X86ISD::VPERMIV3";
17586 case X86ISD::VPERMI: return "X86ISD::VPERMI";
17587 case X86ISD::PMULUDQ: return "X86ISD::PMULUDQ";
17588 case X86ISD::PMULDQ: return "X86ISD::PMULDQ";
17589 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
17590 case X86ISD::VAARG_64: return "X86ISD::VAARG_64";
17591 case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA";
17592 case X86ISD::MEMBARRIER: return "X86ISD::MEMBARRIER";
17593 case X86ISD::SEG_ALLOCA: return "X86ISD::SEG_ALLOCA";
17594 case X86ISD::WIN_FTOL: return "X86ISD::WIN_FTOL";
17595 case X86ISD::SAHF: return "X86ISD::SAHF";
17596 case X86ISD::RDRAND: return "X86ISD::RDRAND";
17597 case X86ISD::RDSEED: return "X86ISD::RDSEED";
17598 case X86ISD::FMADD: return "X86ISD::FMADD";
17599 case X86ISD::FMSUB: return "X86ISD::FMSUB";
17600 case X86ISD::FNMADD: return "X86ISD::FNMADD";
17601 case X86ISD::FNMSUB: return "X86ISD::FNMSUB";
17602 case X86ISD::FMADDSUB: return "X86ISD::FMADDSUB";
17603 case X86ISD::FMSUBADD: return "X86ISD::FMSUBADD";
17604 case X86ISD::PCMPESTRI: return "X86ISD::PCMPESTRI";
17605 case X86ISD::PCMPISTRI: return "X86ISD::PCMPISTRI";
17606 case X86ISD::XTEST: return "X86ISD::XTEST";
17610 // isLegalAddressingMode - Return true if the addressing mode represented
17611 // by AM is legal for this target, for a load/store of the specified type.
17612 bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
17614 // X86 supports extremely general addressing modes.
17615 CodeModel::Model M = getTargetMachine().getCodeModel();
17616 Reloc::Model R = getTargetMachine().getRelocationModel();
17618 // X86 allows a sign-extended 32-bit immediate field as a displacement.
17619 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != nullptr))
17624 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
17626 // If a reference to this global requires an extra load, we can't fold it.
17627 if (isGlobalStubReference(GVFlags))
17630 // If BaseGV requires a register for the PIC base, we cannot also have a
17631 // BaseReg specified.
17632 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
17635 // If lower 4G is not available, then we must use rip-relative addressing.
17636 if ((M != CodeModel::Small || R != Reloc::Static) &&
17637 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
17641 switch (AM.Scale) {
17647 // These scales always work.
17652 // These scales are formed with basereg+scalereg. Only accept if there is
17657 default: // Other stuff never works.
17664 bool X86TargetLowering::isVectorShiftByScalarCheap(Type *Ty) const {
17665 unsigned Bits = Ty->getScalarSizeInBits();
17667 // 8-bit shifts are always expensive, but versions with a scalar amount aren't
17668 // particularly cheaper than those without.
17672 // On AVX2 there are new vpsllv[dq] instructions (and other shifts), that make
17673 // variable shifts just as cheap as scalar ones.
17674 if (Subtarget->hasInt256() && (Bits == 32 || Bits == 64))
17677 // Otherwise, it's significantly cheaper to shift by a scalar amount than by a
17678 // fully general vector.
17682 bool X86TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
17683 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
17685 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
17686 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
17687 return NumBits1 > NumBits2;
17690 bool X86TargetLowering::allowTruncateForTailCall(Type *Ty1, Type *Ty2) const {
17691 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
17694 if (!isTypeLegal(EVT::getEVT(Ty1)))
17697 assert(Ty1->getPrimitiveSizeInBits() <= 64 && "i128 is probably not a noop");
17699 // Assuming the caller doesn't have a zeroext or signext return parameter,
17700 // truncation all the way down to i1 is valid.
17704 bool X86TargetLowering::isLegalICmpImmediate(int64_t Imm) const {
17705 return isInt<32>(Imm);
17708 bool X86TargetLowering::isLegalAddImmediate(int64_t Imm) const {
17709 // Can also use sub to handle negated immediates.
17710 return isInt<32>(Imm);
17713 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
17714 if (!VT1.isInteger() || !VT2.isInteger())
17716 unsigned NumBits1 = VT1.getSizeInBits();
17717 unsigned NumBits2 = VT2.getSizeInBits();
17718 return NumBits1 > NumBits2;
17721 bool X86TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
17722 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
17723 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit();
17726 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
17727 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
17728 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
17731 bool X86TargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
17732 EVT VT1 = Val.getValueType();
17733 if (isZExtFree(VT1, VT2))
17736 if (Val.getOpcode() != ISD::LOAD)
17739 if (!VT1.isSimple() || !VT1.isInteger() ||
17740 !VT2.isSimple() || !VT2.isInteger())
17743 switch (VT1.getSimpleVT().SimpleTy) {
17748 // X86 has 8, 16, and 32-bit zero-extending loads.
17756 X86TargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
17757 if (!(Subtarget->hasFMA() || Subtarget->hasFMA4()))
17760 VT = VT.getScalarType();
17762 if (!VT.isSimple())
17765 switch (VT.getSimpleVT().SimpleTy) {
17776 bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
17777 // i16 instructions are longer (0x66 prefix) and potentially slower.
17778 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
17781 /// isShuffleMaskLegal - Targets can use this to indicate that they only
17782 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
17783 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
17784 /// are assumed to be legal.
17786 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
17788 if (!VT.isSimple())
17791 MVT SVT = VT.getSimpleVT();
17793 // Very little shuffling can be done for 64-bit vectors right now.
17794 if (VT.getSizeInBits() == 64)
17797 // If this is a single-input shuffle with no 128 bit lane crossings we can
17798 // lower it into pshufb.
17799 if ((SVT.is128BitVector() && Subtarget->hasSSSE3()) ||
17800 (SVT.is256BitVector() && Subtarget->hasInt256())) {
17801 bool isLegal = true;
17802 for (unsigned I = 0, E = M.size(); I != E; ++I) {
17803 if (M[I] >= (int)SVT.getVectorNumElements() ||
17804 ShuffleCrosses128bitLane(SVT, I, M[I])) {
17813 // FIXME: blends, shifts.
17814 return (SVT.getVectorNumElements() == 2 ||
17815 ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
17816 isMOVLMask(M, SVT) ||
17817 isMOVHLPSMask(M, SVT) ||
17818 isSHUFPMask(M, SVT) ||
17819 isPSHUFDMask(M, SVT) ||
17820 isPSHUFHWMask(M, SVT, Subtarget->hasInt256()) ||
17821 isPSHUFLWMask(M, SVT, Subtarget->hasInt256()) ||
17822 isPALIGNRMask(M, SVT, Subtarget) ||
17823 isUNPCKLMask(M, SVT, Subtarget->hasInt256()) ||
17824 isUNPCKHMask(M, SVT, Subtarget->hasInt256()) ||
17825 isUNPCKL_v_undef_Mask(M, SVT, Subtarget->hasInt256()) ||
17826 isUNPCKH_v_undef_Mask(M, SVT, Subtarget->hasInt256()) ||
17827 isBlendMask(M, SVT, Subtarget->hasSSE41(), Subtarget->hasInt256()));
17831 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
17833 if (!VT.isSimple())
17836 MVT SVT = VT.getSimpleVT();
17837 unsigned NumElts = SVT.getVectorNumElements();
17838 // FIXME: This collection of masks seems suspect.
17841 if (NumElts == 4 && SVT.is128BitVector()) {
17842 return (isMOVLMask(Mask, SVT) ||
17843 isCommutedMOVLMask(Mask, SVT, true) ||
17844 isSHUFPMask(Mask, SVT) ||
17845 isSHUFPMask(Mask, SVT, /* Commuted */ true));
17850 //===----------------------------------------------------------------------===//
17851 // X86 Scheduler Hooks
17852 //===----------------------------------------------------------------------===//
17854 /// Utility function to emit xbegin specifying the start of an RTM region.
17855 static MachineBasicBlock *EmitXBegin(MachineInstr *MI, MachineBasicBlock *MBB,
17856 const TargetInstrInfo *TII) {
17857 DebugLoc DL = MI->getDebugLoc();
17859 const BasicBlock *BB = MBB->getBasicBlock();
17860 MachineFunction::iterator I = MBB;
17863 // For the v = xbegin(), we generate
17874 MachineBasicBlock *thisMBB = MBB;
17875 MachineFunction *MF = MBB->getParent();
17876 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
17877 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
17878 MF->insert(I, mainMBB);
17879 MF->insert(I, sinkMBB);
17881 // Transfer the remainder of BB and its successor edges to sinkMBB.
17882 sinkMBB->splice(sinkMBB->begin(), MBB,
17883 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
17884 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
17888 // # fallthrough to mainMBB
17889 // # abortion to sinkMBB
17890 BuildMI(thisMBB, DL, TII->get(X86::XBEGIN_4)).addMBB(sinkMBB);
17891 thisMBB->addSuccessor(mainMBB);
17892 thisMBB->addSuccessor(sinkMBB);
17896 BuildMI(mainMBB, DL, TII->get(X86::MOV32ri), X86::EAX).addImm(-1);
17897 mainMBB->addSuccessor(sinkMBB);
17900 // EAX is live into the sinkMBB
17901 sinkMBB->addLiveIn(X86::EAX);
17902 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
17903 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
17906 MI->eraseFromParent();
17910 // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
17911 // or XMM0_V32I8 in AVX all of this code can be replaced with that
17912 // in the .td file.
17913 static MachineBasicBlock *EmitPCMPSTRM(MachineInstr *MI, MachineBasicBlock *BB,
17914 const TargetInstrInfo *TII) {
17916 switch (MI->getOpcode()) {
17917 default: llvm_unreachable("illegal opcode!");
17918 case X86::PCMPISTRM128REG: Opc = X86::PCMPISTRM128rr; break;
17919 case X86::VPCMPISTRM128REG: Opc = X86::VPCMPISTRM128rr; break;
17920 case X86::PCMPISTRM128MEM: Opc = X86::PCMPISTRM128rm; break;
17921 case X86::VPCMPISTRM128MEM: Opc = X86::VPCMPISTRM128rm; break;
17922 case X86::PCMPESTRM128REG: Opc = X86::PCMPESTRM128rr; break;
17923 case X86::VPCMPESTRM128REG: Opc = X86::VPCMPESTRM128rr; break;
17924 case X86::PCMPESTRM128MEM: Opc = X86::PCMPESTRM128rm; break;
17925 case X86::VPCMPESTRM128MEM: Opc = X86::VPCMPESTRM128rm; break;
17928 DebugLoc dl = MI->getDebugLoc();
17929 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
17931 unsigned NumArgs = MI->getNumOperands();
17932 for (unsigned i = 1; i < NumArgs; ++i) {
17933 MachineOperand &Op = MI->getOperand(i);
17934 if (!(Op.isReg() && Op.isImplicit()))
17935 MIB.addOperand(Op);
17937 if (MI->hasOneMemOperand())
17938 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
17940 BuildMI(*BB, MI, dl,
17941 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
17942 .addReg(X86::XMM0);
17944 MI->eraseFromParent();
17948 // FIXME: Custom handling because TableGen doesn't support multiple implicit
17949 // defs in an instruction pattern
17950 static MachineBasicBlock *EmitPCMPSTRI(MachineInstr *MI, MachineBasicBlock *BB,
17951 const TargetInstrInfo *TII) {
17953 switch (MI->getOpcode()) {
17954 default: llvm_unreachable("illegal opcode!");
17955 case X86::PCMPISTRIREG: Opc = X86::PCMPISTRIrr; break;
17956 case X86::VPCMPISTRIREG: Opc = X86::VPCMPISTRIrr; break;
17957 case X86::PCMPISTRIMEM: Opc = X86::PCMPISTRIrm; break;
17958 case X86::VPCMPISTRIMEM: Opc = X86::VPCMPISTRIrm; break;
17959 case X86::PCMPESTRIREG: Opc = X86::PCMPESTRIrr; break;
17960 case X86::VPCMPESTRIREG: Opc = X86::VPCMPESTRIrr; break;
17961 case X86::PCMPESTRIMEM: Opc = X86::PCMPESTRIrm; break;
17962 case X86::VPCMPESTRIMEM: Opc = X86::VPCMPESTRIrm; break;
17965 DebugLoc dl = MI->getDebugLoc();
17966 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
17968 unsigned NumArgs = MI->getNumOperands(); // remove the results
17969 for (unsigned i = 1; i < NumArgs; ++i) {
17970 MachineOperand &Op = MI->getOperand(i);
17971 if (!(Op.isReg() && Op.isImplicit()))
17972 MIB.addOperand(Op);
17974 if (MI->hasOneMemOperand())
17975 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
17977 BuildMI(*BB, MI, dl,
17978 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
17981 MI->eraseFromParent();
17985 static MachineBasicBlock * EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB,
17986 const TargetInstrInfo *TII,
17987 const X86Subtarget* Subtarget) {
17988 DebugLoc dl = MI->getDebugLoc();
17990 // Address into RAX/EAX, other two args into ECX, EDX.
17991 unsigned MemOpc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
17992 unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
17993 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg);
17994 for (int i = 0; i < X86::AddrNumOperands; ++i)
17995 MIB.addOperand(MI->getOperand(i));
17997 unsigned ValOps = X86::AddrNumOperands;
17998 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
17999 .addReg(MI->getOperand(ValOps).getReg());
18000 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EDX)
18001 .addReg(MI->getOperand(ValOps+1).getReg());
18003 // The instruction doesn't actually take any operands though.
18004 BuildMI(*BB, MI, dl, TII->get(X86::MONITORrrr));
18006 MI->eraseFromParent(); // The pseudo is gone now.
18010 MachineBasicBlock *
18011 X86TargetLowering::EmitVAARG64WithCustomInserter(
18013 MachineBasicBlock *MBB) const {
18014 // Emit va_arg instruction on X86-64.
18016 // Operands to this pseudo-instruction:
18017 // 0 ) Output : destination address (reg)
18018 // 1-5) Input : va_list address (addr, i64mem)
18019 // 6 ) ArgSize : Size (in bytes) of vararg type
18020 // 7 ) ArgMode : 0=overflow only, 1=use gp_offset, 2=use fp_offset
18021 // 8 ) Align : Alignment of type
18022 // 9 ) EFLAGS (implicit-def)
18024 assert(MI->getNumOperands() == 10 && "VAARG_64 should have 10 operands!");
18025 assert(X86::AddrNumOperands == 5 && "VAARG_64 assumes 5 address operands");
18027 unsigned DestReg = MI->getOperand(0).getReg();
18028 MachineOperand &Base = MI->getOperand(1);
18029 MachineOperand &Scale = MI->getOperand(2);
18030 MachineOperand &Index = MI->getOperand(3);
18031 MachineOperand &Disp = MI->getOperand(4);
18032 MachineOperand &Segment = MI->getOperand(5);
18033 unsigned ArgSize = MI->getOperand(6).getImm();
18034 unsigned ArgMode = MI->getOperand(7).getImm();
18035 unsigned Align = MI->getOperand(8).getImm();
18037 // Memory Reference
18038 assert(MI->hasOneMemOperand() && "Expected VAARG_64 to have one memoperand");
18039 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
18040 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
18042 // Machine Information
18043 const TargetInstrInfo *TII = MBB->getParent()->getSubtarget().getInstrInfo();
18044 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
18045 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64);
18046 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32);
18047 DebugLoc DL = MI->getDebugLoc();
18049 // struct va_list {
18052 // i64 overflow_area (address)
18053 // i64 reg_save_area (address)
18055 // sizeof(va_list) = 24
18056 // alignment(va_list) = 8
18058 unsigned TotalNumIntRegs = 6;
18059 unsigned TotalNumXMMRegs = 8;
18060 bool UseGPOffset = (ArgMode == 1);
18061 bool UseFPOffset = (ArgMode == 2);
18062 unsigned MaxOffset = TotalNumIntRegs * 8 +
18063 (UseFPOffset ? TotalNumXMMRegs * 16 : 0);
18065 /* Align ArgSize to a multiple of 8 */
18066 unsigned ArgSizeA8 = (ArgSize + 7) & ~7;
18067 bool NeedsAlign = (Align > 8);
18069 MachineBasicBlock *thisMBB = MBB;
18070 MachineBasicBlock *overflowMBB;
18071 MachineBasicBlock *offsetMBB;
18072 MachineBasicBlock *endMBB;
18074 unsigned OffsetDestReg = 0; // Argument address computed by offsetMBB
18075 unsigned OverflowDestReg = 0; // Argument address computed by overflowMBB
18076 unsigned OffsetReg = 0;
18078 if (!UseGPOffset && !UseFPOffset) {
18079 // If we only pull from the overflow region, we don't create a branch.
18080 // We don't need to alter control flow.
18081 OffsetDestReg = 0; // unused
18082 OverflowDestReg = DestReg;
18084 offsetMBB = nullptr;
18085 overflowMBB = thisMBB;
18088 // First emit code to check if gp_offset (or fp_offset) is below the bound.
18089 // If so, pull the argument from reg_save_area. (branch to offsetMBB)
18090 // If not, pull from overflow_area. (branch to overflowMBB)
18095 // offsetMBB overflowMBB
18100 // Registers for the PHI in endMBB
18101 OffsetDestReg = MRI.createVirtualRegister(AddrRegClass);
18102 OverflowDestReg = MRI.createVirtualRegister(AddrRegClass);
18104 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
18105 MachineFunction *MF = MBB->getParent();
18106 overflowMBB = MF->CreateMachineBasicBlock(LLVM_BB);
18107 offsetMBB = MF->CreateMachineBasicBlock(LLVM_BB);
18108 endMBB = MF->CreateMachineBasicBlock(LLVM_BB);
18110 MachineFunction::iterator MBBIter = MBB;
18113 // Insert the new basic blocks
18114 MF->insert(MBBIter, offsetMBB);
18115 MF->insert(MBBIter, overflowMBB);
18116 MF->insert(MBBIter, endMBB);
18118 // Transfer the remainder of MBB and its successor edges to endMBB.
18119 endMBB->splice(endMBB->begin(), thisMBB,
18120 std::next(MachineBasicBlock::iterator(MI)), thisMBB->end());
18121 endMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
18123 // Make offsetMBB and overflowMBB successors of thisMBB
18124 thisMBB->addSuccessor(offsetMBB);
18125 thisMBB->addSuccessor(overflowMBB);
18127 // endMBB is a successor of both offsetMBB and overflowMBB
18128 offsetMBB->addSuccessor(endMBB);
18129 overflowMBB->addSuccessor(endMBB);
18131 // Load the offset value into a register
18132 OffsetReg = MRI.createVirtualRegister(OffsetRegClass);
18133 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg)
18137 .addDisp(Disp, UseFPOffset ? 4 : 0)
18138 .addOperand(Segment)
18139 .setMemRefs(MMOBegin, MMOEnd);
18141 // Check if there is enough room left to pull this argument.
18142 BuildMI(thisMBB, DL, TII->get(X86::CMP32ri))
18144 .addImm(MaxOffset + 8 - ArgSizeA8);
18146 // Branch to "overflowMBB" if offset >= max
18147 // Fall through to "offsetMBB" otherwise
18148 BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE)))
18149 .addMBB(overflowMBB);
18152 // In offsetMBB, emit code to use the reg_save_area.
18154 assert(OffsetReg != 0);
18156 // Read the reg_save_area address.
18157 unsigned RegSaveReg = MRI.createVirtualRegister(AddrRegClass);
18158 BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg)
18163 .addOperand(Segment)
18164 .setMemRefs(MMOBegin, MMOEnd);
18166 // Zero-extend the offset
18167 unsigned OffsetReg64 = MRI.createVirtualRegister(AddrRegClass);
18168 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64)
18171 .addImm(X86::sub_32bit);
18173 // Add the offset to the reg_save_area to get the final address.
18174 BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg)
18175 .addReg(OffsetReg64)
18176 .addReg(RegSaveReg);
18178 // Compute the offset for the next argument
18179 unsigned NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass);
18180 BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg)
18182 .addImm(UseFPOffset ? 16 : 8);
18184 // Store it back into the va_list.
18185 BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr))
18189 .addDisp(Disp, UseFPOffset ? 4 : 0)
18190 .addOperand(Segment)
18191 .addReg(NextOffsetReg)
18192 .setMemRefs(MMOBegin, MMOEnd);
18195 BuildMI(offsetMBB, DL, TII->get(X86::JMP_4))
18200 // Emit code to use overflow area
18203 // Load the overflow_area address into a register.
18204 unsigned OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass);
18205 BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg)
18210 .addOperand(Segment)
18211 .setMemRefs(MMOBegin, MMOEnd);
18213 // If we need to align it, do so. Otherwise, just copy the address
18214 // to OverflowDestReg.
18216 // Align the overflow address
18217 assert((Align & (Align-1)) == 0 && "Alignment must be a power of 2");
18218 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass);
18220 // aligned_addr = (addr + (align-1)) & ~(align-1)
18221 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg)
18222 .addReg(OverflowAddrReg)
18225 BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg)
18227 .addImm(~(uint64_t)(Align-1));
18229 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg)
18230 .addReg(OverflowAddrReg);
18233 // Compute the next overflow address after this argument.
18234 // (the overflow address should be kept 8-byte aligned)
18235 unsigned NextAddrReg = MRI.createVirtualRegister(AddrRegClass);
18236 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg)
18237 .addReg(OverflowDestReg)
18238 .addImm(ArgSizeA8);
18240 // Store the new overflow address.
18241 BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr))
18246 .addOperand(Segment)
18247 .addReg(NextAddrReg)
18248 .setMemRefs(MMOBegin, MMOEnd);
18250 // If we branched, emit the PHI to the front of endMBB.
18252 BuildMI(*endMBB, endMBB->begin(), DL,
18253 TII->get(X86::PHI), DestReg)
18254 .addReg(OffsetDestReg).addMBB(offsetMBB)
18255 .addReg(OverflowDestReg).addMBB(overflowMBB);
18258 // Erase the pseudo instruction
18259 MI->eraseFromParent();
18264 MachineBasicBlock *
18265 X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
18267 MachineBasicBlock *MBB) const {
18268 // Emit code to save XMM registers to the stack. The ABI says that the
18269 // number of registers to save is given in %al, so it's theoretically
18270 // possible to do an indirect jump trick to avoid saving all of them,
18271 // however this code takes a simpler approach and just executes all
18272 // of the stores if %al is non-zero. It's less code, and it's probably
18273 // easier on the hardware branch predictor, and stores aren't all that
18274 // expensive anyway.
18276 // Create the new basic blocks. One block contains all the XMM stores,
18277 // and one block is the final destination regardless of whether any
18278 // stores were performed.
18279 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
18280 MachineFunction *F = MBB->getParent();
18281 MachineFunction::iterator MBBIter = MBB;
18283 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB);
18284 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB);
18285 F->insert(MBBIter, XMMSaveMBB);
18286 F->insert(MBBIter, EndMBB);
18288 // Transfer the remainder of MBB and its successor edges to EndMBB.
18289 EndMBB->splice(EndMBB->begin(), MBB,
18290 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
18291 EndMBB->transferSuccessorsAndUpdatePHIs(MBB);
18293 // The original block will now fall through to the XMM save block.
18294 MBB->addSuccessor(XMMSaveMBB);
18295 // The XMMSaveMBB will fall through to the end block.
18296 XMMSaveMBB->addSuccessor(EndMBB);
18298 // Now add the instructions.
18299 const TargetInstrInfo *TII = MBB->getParent()->getSubtarget().getInstrInfo();
18300 DebugLoc DL = MI->getDebugLoc();
18302 unsigned CountReg = MI->getOperand(0).getReg();
18303 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm();
18304 int64_t VarArgsFPOffset = MI->getOperand(2).getImm();
18306 if (!Subtarget->isTargetWin64()) {
18307 // If %al is 0, branch around the XMM save block.
18308 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
18309 BuildMI(MBB, DL, TII->get(X86::JE_4)).addMBB(EndMBB);
18310 MBB->addSuccessor(EndMBB);
18313 // Make sure the last operand is EFLAGS, which gets clobbered by the branch
18314 // that was just emitted, but clearly shouldn't be "saved".
18315 assert((MI->getNumOperands() <= 3 ||
18316 !MI->getOperand(MI->getNumOperands() - 1).isReg() ||
18317 MI->getOperand(MI->getNumOperands() - 1).getReg() == X86::EFLAGS)
18318 && "Expected last argument to be EFLAGS");
18319 unsigned MOVOpc = Subtarget->hasFp256() ? X86::VMOVAPSmr : X86::MOVAPSmr;
18320 // In the XMM save block, save all the XMM argument registers.
18321 for (int i = 3, e = MI->getNumOperands() - 1; i != e; ++i) {
18322 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
18323 MachineMemOperand *MMO =
18324 F->getMachineMemOperand(
18325 MachinePointerInfo::getFixedStack(RegSaveFrameIndex, Offset),
18326 MachineMemOperand::MOStore,
18327 /*Size=*/16, /*Align=*/16);
18328 BuildMI(XMMSaveMBB, DL, TII->get(MOVOpc))
18329 .addFrameIndex(RegSaveFrameIndex)
18330 .addImm(/*Scale=*/1)
18331 .addReg(/*IndexReg=*/0)
18332 .addImm(/*Disp=*/Offset)
18333 .addReg(/*Segment=*/0)
18334 .addReg(MI->getOperand(i).getReg())
18335 .addMemOperand(MMO);
18338 MI->eraseFromParent(); // The pseudo instruction is gone now.
18343 // The EFLAGS operand of SelectItr might be missing a kill marker
18344 // because there were multiple uses of EFLAGS, and ISel didn't know
18345 // which to mark. Figure out whether SelectItr should have had a
18346 // kill marker, and set it if it should. Returns the correct kill
18348 static bool checkAndUpdateEFLAGSKill(MachineBasicBlock::iterator SelectItr,
18349 MachineBasicBlock* BB,
18350 const TargetRegisterInfo* TRI) {
18351 // Scan forward through BB for a use/def of EFLAGS.
18352 MachineBasicBlock::iterator miI(std::next(SelectItr));
18353 for (MachineBasicBlock::iterator miE = BB->end(); miI != miE; ++miI) {
18354 const MachineInstr& mi = *miI;
18355 if (mi.readsRegister(X86::EFLAGS))
18357 if (mi.definesRegister(X86::EFLAGS))
18358 break; // Should have kill-flag - update below.
18361 // If we hit the end of the block, check whether EFLAGS is live into a
18363 if (miI == BB->end()) {
18364 for (MachineBasicBlock::succ_iterator sItr = BB->succ_begin(),
18365 sEnd = BB->succ_end();
18366 sItr != sEnd; ++sItr) {
18367 MachineBasicBlock* succ = *sItr;
18368 if (succ->isLiveIn(X86::EFLAGS))
18373 // We found a def, or hit the end of the basic block and EFLAGS wasn't live
18374 // out. SelectMI should have a kill flag on EFLAGS.
18375 SelectItr->addRegisterKilled(X86::EFLAGS, TRI);
18379 MachineBasicBlock *
18380 X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
18381 MachineBasicBlock *BB) const {
18382 const TargetInstrInfo *TII = BB->getParent()->getSubtarget().getInstrInfo();
18383 DebugLoc DL = MI->getDebugLoc();
18385 // To "insert" a SELECT_CC instruction, we actually have to insert the
18386 // diamond control-flow pattern. The incoming instruction knows the
18387 // destination vreg to set, the condition code register to branch on, the
18388 // true/false values to select between, and a branch opcode to use.
18389 const BasicBlock *LLVM_BB = BB->getBasicBlock();
18390 MachineFunction::iterator It = BB;
18396 // cmpTY ccX, r1, r2
18398 // fallthrough --> copy0MBB
18399 MachineBasicBlock *thisMBB = BB;
18400 MachineFunction *F = BB->getParent();
18401 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
18402 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
18403 F->insert(It, copy0MBB);
18404 F->insert(It, sinkMBB);
18406 // If the EFLAGS register isn't dead in the terminator, then claim that it's
18407 // live into the sink and copy blocks.
18408 const TargetRegisterInfo *TRI =
18409 BB->getParent()->getSubtarget().getRegisterInfo();
18410 if (!MI->killsRegister(X86::EFLAGS) &&
18411 !checkAndUpdateEFLAGSKill(MI, BB, TRI)) {
18412 copy0MBB->addLiveIn(X86::EFLAGS);
18413 sinkMBB->addLiveIn(X86::EFLAGS);
18416 // Transfer the remainder of BB and its successor edges to sinkMBB.
18417 sinkMBB->splice(sinkMBB->begin(), BB,
18418 std::next(MachineBasicBlock::iterator(MI)), BB->end());
18419 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
18421 // Add the true and fallthrough blocks as its successors.
18422 BB->addSuccessor(copy0MBB);
18423 BB->addSuccessor(sinkMBB);
18425 // Create the conditional branch instruction.
18427 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
18428 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
18431 // %FalseValue = ...
18432 // # fallthrough to sinkMBB
18433 copy0MBB->addSuccessor(sinkMBB);
18436 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
18438 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
18439 TII->get(X86::PHI), MI->getOperand(0).getReg())
18440 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
18441 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
18443 MI->eraseFromParent(); // The pseudo instruction is gone now.
18447 MachineBasicBlock *
18448 X86TargetLowering::EmitLoweredSegAlloca(MachineInstr *MI, MachineBasicBlock *BB,
18449 bool Is64Bit) const {
18450 MachineFunction *MF = BB->getParent();
18451 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
18452 DebugLoc DL = MI->getDebugLoc();
18453 const BasicBlock *LLVM_BB = BB->getBasicBlock();
18455 assert(MF->shouldSplitStack());
18457 unsigned TlsReg = Is64Bit ? X86::FS : X86::GS;
18458 unsigned TlsOffset = Is64Bit ? 0x70 : 0x30;
18461 // ... [Till the alloca]
18462 // If stacklet is not large enough, jump to mallocMBB
18465 // Allocate by subtracting from RSP
18466 // Jump to continueMBB
18469 // Allocate by call to runtime
18473 // [rest of original BB]
18476 MachineBasicBlock *mallocMBB = MF->CreateMachineBasicBlock(LLVM_BB);
18477 MachineBasicBlock *bumpMBB = MF->CreateMachineBasicBlock(LLVM_BB);
18478 MachineBasicBlock *continueMBB = MF->CreateMachineBasicBlock(LLVM_BB);
18480 MachineRegisterInfo &MRI = MF->getRegInfo();
18481 const TargetRegisterClass *AddrRegClass =
18482 getRegClassFor(Is64Bit ? MVT::i64:MVT::i32);
18484 unsigned mallocPtrVReg = MRI.createVirtualRegister(AddrRegClass),
18485 bumpSPPtrVReg = MRI.createVirtualRegister(AddrRegClass),
18486 tmpSPVReg = MRI.createVirtualRegister(AddrRegClass),
18487 SPLimitVReg = MRI.createVirtualRegister(AddrRegClass),
18488 sizeVReg = MI->getOperand(1).getReg(),
18489 physSPReg = Is64Bit ? X86::RSP : X86::ESP;
18491 MachineFunction::iterator MBBIter = BB;
18494 MF->insert(MBBIter, bumpMBB);
18495 MF->insert(MBBIter, mallocMBB);
18496 MF->insert(MBBIter, continueMBB);
18498 continueMBB->splice(continueMBB->begin(), BB,
18499 std::next(MachineBasicBlock::iterator(MI)), BB->end());
18500 continueMBB->transferSuccessorsAndUpdatePHIs(BB);
18502 // Add code to the main basic block to check if the stack limit has been hit,
18503 // and if so, jump to mallocMBB otherwise to bumpMBB.
18504 BuildMI(BB, DL, TII->get(TargetOpcode::COPY), tmpSPVReg).addReg(physSPReg);
18505 BuildMI(BB, DL, TII->get(Is64Bit ? X86::SUB64rr:X86::SUB32rr), SPLimitVReg)
18506 .addReg(tmpSPVReg).addReg(sizeVReg);
18507 BuildMI(BB, DL, TII->get(Is64Bit ? X86::CMP64mr:X86::CMP32mr))
18508 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg)
18509 .addReg(SPLimitVReg);
18510 BuildMI(BB, DL, TII->get(X86::JG_4)).addMBB(mallocMBB);
18512 // bumpMBB simply decreases the stack pointer, since we know the current
18513 // stacklet has enough space.
18514 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), physSPReg)
18515 .addReg(SPLimitVReg);
18516 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), bumpSPPtrVReg)
18517 .addReg(SPLimitVReg);
18518 BuildMI(bumpMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
18520 // Calls into a routine in libgcc to allocate more space from the heap.
18521 const uint32_t *RegMask = MF->getTarget()
18522 .getSubtargetImpl()
18523 ->getRegisterInfo()
18524 ->getCallPreservedMask(CallingConv::C);
18526 BuildMI(mallocMBB, DL, TII->get(X86::MOV64rr), X86::RDI)
18528 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
18529 .addExternalSymbol("__morestack_allocate_stack_space")
18530 .addRegMask(RegMask)
18531 .addReg(X86::RDI, RegState::Implicit)
18532 .addReg(X86::RAX, RegState::ImplicitDefine);
18534 BuildMI(mallocMBB, DL, TII->get(X86::SUB32ri), physSPReg).addReg(physSPReg)
18536 BuildMI(mallocMBB, DL, TII->get(X86::PUSH32r)).addReg(sizeVReg);
18537 BuildMI(mallocMBB, DL, TII->get(X86::CALLpcrel32))
18538 .addExternalSymbol("__morestack_allocate_stack_space")
18539 .addRegMask(RegMask)
18540 .addReg(X86::EAX, RegState::ImplicitDefine);
18544 BuildMI(mallocMBB, DL, TII->get(X86::ADD32ri), physSPReg).addReg(physSPReg)
18547 BuildMI(mallocMBB, DL, TII->get(TargetOpcode::COPY), mallocPtrVReg)
18548 .addReg(Is64Bit ? X86::RAX : X86::EAX);
18549 BuildMI(mallocMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
18551 // Set up the CFG correctly.
18552 BB->addSuccessor(bumpMBB);
18553 BB->addSuccessor(mallocMBB);
18554 mallocMBB->addSuccessor(continueMBB);
18555 bumpMBB->addSuccessor(continueMBB);
18557 // Take care of the PHI nodes.
18558 BuildMI(*continueMBB, continueMBB->begin(), DL, TII->get(X86::PHI),
18559 MI->getOperand(0).getReg())
18560 .addReg(mallocPtrVReg).addMBB(mallocMBB)
18561 .addReg(bumpSPPtrVReg).addMBB(bumpMBB);
18563 // Delete the original pseudo instruction.
18564 MI->eraseFromParent();
18567 return continueMBB;
18570 MachineBasicBlock *
18571 X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI,
18572 MachineBasicBlock *BB) const {
18573 const TargetInstrInfo *TII = BB->getParent()->getSubtarget().getInstrInfo();
18574 DebugLoc DL = MI->getDebugLoc();
18576 assert(!Subtarget->isTargetMacho());
18578 // The lowering is pretty easy: we're just emitting the call to _alloca. The
18579 // non-trivial part is impdef of ESP.
18581 if (Subtarget->isTargetWin64()) {
18582 if (Subtarget->isTargetCygMing()) {
18583 // ___chkstk(Mingw64):
18584 // Clobbers R10, R11, RAX and EFLAGS.
18586 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
18587 .addExternalSymbol("___chkstk")
18588 .addReg(X86::RAX, RegState::Implicit)
18589 .addReg(X86::RSP, RegState::Implicit)
18590 .addReg(X86::RAX, RegState::Define | RegState::Implicit)
18591 .addReg(X86::RSP, RegState::Define | RegState::Implicit)
18592 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
18594 // __chkstk(MSVCRT): does not update stack pointer.
18595 // Clobbers R10, R11 and EFLAGS.
18596 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
18597 .addExternalSymbol("__chkstk")
18598 .addReg(X86::RAX, RegState::Implicit)
18599 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
18600 // RAX has the offset to be subtracted from RSP.
18601 BuildMI(*BB, MI, DL, TII->get(X86::SUB64rr), X86::RSP)
18606 const char *StackProbeSymbol =
18607 Subtarget->isTargetKnownWindowsMSVC() ? "_chkstk" : "_alloca";
18609 BuildMI(*BB, MI, DL, TII->get(X86::CALLpcrel32))
18610 .addExternalSymbol(StackProbeSymbol)
18611 .addReg(X86::EAX, RegState::Implicit)
18612 .addReg(X86::ESP, RegState::Implicit)
18613 .addReg(X86::EAX, RegState::Define | RegState::Implicit)
18614 .addReg(X86::ESP, RegState::Define | RegState::Implicit)
18615 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
18618 MI->eraseFromParent(); // The pseudo instruction is gone now.
18622 MachineBasicBlock *
18623 X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI,
18624 MachineBasicBlock *BB) const {
18625 // This is pretty easy. We're taking the value that we received from
18626 // our load from the relocation, sticking it in either RDI (x86-64)
18627 // or EAX and doing an indirect call. The return value will then
18628 // be in the normal return register.
18629 MachineFunction *F = BB->getParent();
18630 const X86InstrInfo *TII =
18631 static_cast<const X86InstrInfo *>(F->getSubtarget().getInstrInfo());
18632 DebugLoc DL = MI->getDebugLoc();
18634 assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?");
18635 assert(MI->getOperand(3).isGlobal() && "This should be a global");
18637 // Get a register mask for the lowered call.
18638 // FIXME: The 32-bit calls have non-standard calling conventions. Use a
18639 // proper register mask.
18640 const uint32_t *RegMask = F->getTarget()
18641 .getSubtargetImpl()
18642 ->getRegisterInfo()
18643 ->getCallPreservedMask(CallingConv::C);
18644 if (Subtarget->is64Bit()) {
18645 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
18646 TII->get(X86::MOV64rm), X86::RDI)
18648 .addImm(0).addReg(0)
18649 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
18650 MI->getOperand(3).getTargetFlags())
18652 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m));
18653 addDirectMem(MIB, X86::RDI);
18654 MIB.addReg(X86::RAX, RegState::ImplicitDefine).addRegMask(RegMask);
18655 } else if (F->getTarget().getRelocationModel() != Reloc::PIC_) {
18656 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
18657 TII->get(X86::MOV32rm), X86::EAX)
18659 .addImm(0).addReg(0)
18660 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
18661 MI->getOperand(3).getTargetFlags())
18663 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
18664 addDirectMem(MIB, X86::EAX);
18665 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
18667 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
18668 TII->get(X86::MOV32rm), X86::EAX)
18669 .addReg(TII->getGlobalBaseReg(F))
18670 .addImm(0).addReg(0)
18671 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
18672 MI->getOperand(3).getTargetFlags())
18674 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
18675 addDirectMem(MIB, X86::EAX);
18676 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
18679 MI->eraseFromParent(); // The pseudo instruction is gone now.
18683 MachineBasicBlock *
18684 X86TargetLowering::emitEHSjLjSetJmp(MachineInstr *MI,
18685 MachineBasicBlock *MBB) const {
18686 DebugLoc DL = MI->getDebugLoc();
18687 MachineFunction *MF = MBB->getParent();
18688 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
18689 MachineRegisterInfo &MRI = MF->getRegInfo();
18691 const BasicBlock *BB = MBB->getBasicBlock();
18692 MachineFunction::iterator I = MBB;
18695 // Memory Reference
18696 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
18697 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
18700 unsigned MemOpndSlot = 0;
18702 unsigned CurOp = 0;
18704 DstReg = MI->getOperand(CurOp++).getReg();
18705 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
18706 assert(RC->hasType(MVT::i32) && "Invalid destination!");
18707 unsigned mainDstReg = MRI.createVirtualRegister(RC);
18708 unsigned restoreDstReg = MRI.createVirtualRegister(RC);
18710 MemOpndSlot = CurOp;
18712 MVT PVT = getPointerTy();
18713 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
18714 "Invalid Pointer Size!");
18716 // For v = setjmp(buf), we generate
18719 // buf[LabelOffset] = restoreMBB
18720 // SjLjSetup restoreMBB
18726 // v = phi(main, restore)
18731 MachineBasicBlock *thisMBB = MBB;
18732 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
18733 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
18734 MachineBasicBlock *restoreMBB = MF->CreateMachineBasicBlock(BB);
18735 MF->insert(I, mainMBB);
18736 MF->insert(I, sinkMBB);
18737 MF->push_back(restoreMBB);
18739 MachineInstrBuilder MIB;
18741 // Transfer the remainder of BB and its successor edges to sinkMBB.
18742 sinkMBB->splice(sinkMBB->begin(), MBB,
18743 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
18744 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
18747 unsigned PtrStoreOpc = 0;
18748 unsigned LabelReg = 0;
18749 const int64_t LabelOffset = 1 * PVT.getStoreSize();
18750 Reloc::Model RM = MF->getTarget().getRelocationModel();
18751 bool UseImmLabel = (MF->getTarget().getCodeModel() == CodeModel::Small) &&
18752 (RM == Reloc::Static || RM == Reloc::DynamicNoPIC);
18754 // Prepare IP either in reg or imm.
18755 if (!UseImmLabel) {
18756 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mr : X86::MOV32mr;
18757 const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
18758 LabelReg = MRI.createVirtualRegister(PtrRC);
18759 if (Subtarget->is64Bit()) {
18760 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA64r), LabelReg)
18764 .addMBB(restoreMBB)
18767 const X86InstrInfo *XII = static_cast<const X86InstrInfo*>(TII);
18768 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA32r), LabelReg)
18769 .addReg(XII->getGlobalBaseReg(MF))
18772 .addMBB(restoreMBB, Subtarget->ClassifyBlockAddressReference())
18776 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mi32 : X86::MOV32mi;
18778 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PtrStoreOpc));
18779 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
18780 if (i == X86::AddrDisp)
18781 MIB.addDisp(MI->getOperand(MemOpndSlot + i), LabelOffset);
18783 MIB.addOperand(MI->getOperand(MemOpndSlot + i));
18786 MIB.addReg(LabelReg);
18788 MIB.addMBB(restoreMBB);
18789 MIB.setMemRefs(MMOBegin, MMOEnd);
18791 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::EH_SjLj_Setup))
18792 .addMBB(restoreMBB);
18794 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
18795 MF->getSubtarget().getRegisterInfo());
18796 MIB.addRegMask(RegInfo->getNoPreservedMask());
18797 thisMBB->addSuccessor(mainMBB);
18798 thisMBB->addSuccessor(restoreMBB);
18802 BuildMI(mainMBB, DL, TII->get(X86::MOV32r0), mainDstReg);
18803 mainMBB->addSuccessor(sinkMBB);
18806 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
18807 TII->get(X86::PHI), DstReg)
18808 .addReg(mainDstReg).addMBB(mainMBB)
18809 .addReg(restoreDstReg).addMBB(restoreMBB);
18812 BuildMI(restoreMBB, DL, TII->get(X86::MOV32ri), restoreDstReg).addImm(1);
18813 BuildMI(restoreMBB, DL, TII->get(X86::JMP_4)).addMBB(sinkMBB);
18814 restoreMBB->addSuccessor(sinkMBB);
18816 MI->eraseFromParent();
18820 MachineBasicBlock *
18821 X86TargetLowering::emitEHSjLjLongJmp(MachineInstr *MI,
18822 MachineBasicBlock *MBB) const {
18823 DebugLoc DL = MI->getDebugLoc();
18824 MachineFunction *MF = MBB->getParent();
18825 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
18826 MachineRegisterInfo &MRI = MF->getRegInfo();
18828 // Memory Reference
18829 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
18830 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
18832 MVT PVT = getPointerTy();
18833 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
18834 "Invalid Pointer Size!");
18836 const TargetRegisterClass *RC =
18837 (PVT == MVT::i64) ? &X86::GR64RegClass : &X86::GR32RegClass;
18838 unsigned Tmp = MRI.createVirtualRegister(RC);
18839 // Since FP is only updated here but NOT referenced, it's treated as GPR.
18840 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
18841 MF->getSubtarget().getRegisterInfo());
18842 unsigned FP = (PVT == MVT::i64) ? X86::RBP : X86::EBP;
18843 unsigned SP = RegInfo->getStackRegister();
18845 MachineInstrBuilder MIB;
18847 const int64_t LabelOffset = 1 * PVT.getStoreSize();
18848 const int64_t SPOffset = 2 * PVT.getStoreSize();
18850 unsigned PtrLoadOpc = (PVT == MVT::i64) ? X86::MOV64rm : X86::MOV32rm;
18851 unsigned IJmpOpc = (PVT == MVT::i64) ? X86::JMP64r : X86::JMP32r;
18854 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), FP);
18855 for (unsigned i = 0; i < X86::AddrNumOperands; ++i)
18856 MIB.addOperand(MI->getOperand(i));
18857 MIB.setMemRefs(MMOBegin, MMOEnd);
18859 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), Tmp);
18860 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
18861 if (i == X86::AddrDisp)
18862 MIB.addDisp(MI->getOperand(i), LabelOffset);
18864 MIB.addOperand(MI->getOperand(i));
18866 MIB.setMemRefs(MMOBegin, MMOEnd);
18868 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), SP);
18869 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
18870 if (i == X86::AddrDisp)
18871 MIB.addDisp(MI->getOperand(i), SPOffset);
18873 MIB.addOperand(MI->getOperand(i));
18875 MIB.setMemRefs(MMOBegin, MMOEnd);
18877 BuildMI(*MBB, MI, DL, TII->get(IJmpOpc)).addReg(Tmp);
18879 MI->eraseFromParent();
18883 // Replace 213-type (isel default) FMA3 instructions with 231-type for
18884 // accumulator loops. Writing back to the accumulator allows the coalescer
18885 // to remove extra copies in the loop.
18886 MachineBasicBlock *
18887 X86TargetLowering::emitFMA3Instr(MachineInstr *MI,
18888 MachineBasicBlock *MBB) const {
18889 MachineOperand &AddendOp = MI->getOperand(3);
18891 // Bail out early if the addend isn't a register - we can't switch these.
18892 if (!AddendOp.isReg())
18895 MachineFunction &MF = *MBB->getParent();
18896 MachineRegisterInfo &MRI = MF.getRegInfo();
18898 // Check whether the addend is defined by a PHI:
18899 assert(MRI.hasOneDef(AddendOp.getReg()) && "Multiple defs in SSA?");
18900 MachineInstr &AddendDef = *MRI.def_instr_begin(AddendOp.getReg());
18901 if (!AddendDef.isPHI())
18904 // Look for the following pattern:
18906 // %addend = phi [%entry, 0], [%loop, %result]
18908 // %result<tied1> = FMA213 %m2<tied0>, %m1, %addend
18912 // %addend = phi [%entry, 0], [%loop, %result]
18914 // %result<tied1> = FMA231 %addend<tied0>, %m1, %m2
18916 for (unsigned i = 1, e = AddendDef.getNumOperands(); i < e; i += 2) {
18917 assert(AddendDef.getOperand(i).isReg());
18918 MachineOperand PHISrcOp = AddendDef.getOperand(i);
18919 MachineInstr &PHISrcInst = *MRI.def_instr_begin(PHISrcOp.getReg());
18920 if (&PHISrcInst == MI) {
18921 // Found a matching instruction.
18922 unsigned NewFMAOpc = 0;
18923 switch (MI->getOpcode()) {
18924 case X86::VFMADDPDr213r: NewFMAOpc = X86::VFMADDPDr231r; break;
18925 case X86::VFMADDPSr213r: NewFMAOpc = X86::VFMADDPSr231r; break;
18926 case X86::VFMADDSDr213r: NewFMAOpc = X86::VFMADDSDr231r; break;
18927 case X86::VFMADDSSr213r: NewFMAOpc = X86::VFMADDSSr231r; break;
18928 case X86::VFMSUBPDr213r: NewFMAOpc = X86::VFMSUBPDr231r; break;
18929 case X86::VFMSUBPSr213r: NewFMAOpc = X86::VFMSUBPSr231r; break;
18930 case X86::VFMSUBSDr213r: NewFMAOpc = X86::VFMSUBSDr231r; break;
18931 case X86::VFMSUBSSr213r: NewFMAOpc = X86::VFMSUBSSr231r; break;
18932 case X86::VFNMADDPDr213r: NewFMAOpc = X86::VFNMADDPDr231r; break;
18933 case X86::VFNMADDPSr213r: NewFMAOpc = X86::VFNMADDPSr231r; break;
18934 case X86::VFNMADDSDr213r: NewFMAOpc = X86::VFNMADDSDr231r; break;
18935 case X86::VFNMADDSSr213r: NewFMAOpc = X86::VFNMADDSSr231r; break;
18936 case X86::VFNMSUBPDr213r: NewFMAOpc = X86::VFNMSUBPDr231r; break;
18937 case X86::VFNMSUBPSr213r: NewFMAOpc = X86::VFNMSUBPSr231r; break;
18938 case X86::VFNMSUBSDr213r: NewFMAOpc = X86::VFNMSUBSDr231r; break;
18939 case X86::VFNMSUBSSr213r: NewFMAOpc = X86::VFNMSUBSSr231r; break;
18940 case X86::VFMADDPDr213rY: NewFMAOpc = X86::VFMADDPDr231rY; break;
18941 case X86::VFMADDPSr213rY: NewFMAOpc = X86::VFMADDPSr231rY; break;
18942 case X86::VFMSUBPDr213rY: NewFMAOpc = X86::VFMSUBPDr231rY; break;
18943 case X86::VFMSUBPSr213rY: NewFMAOpc = X86::VFMSUBPSr231rY; break;
18944 case X86::VFNMADDPDr213rY: NewFMAOpc = X86::VFNMADDPDr231rY; break;
18945 case X86::VFNMADDPSr213rY: NewFMAOpc = X86::VFNMADDPSr231rY; break;
18946 case X86::VFNMSUBPDr213rY: NewFMAOpc = X86::VFNMSUBPDr231rY; break;
18947 case X86::VFNMSUBPSr213rY: NewFMAOpc = X86::VFNMSUBPSr231rY; break;
18948 default: llvm_unreachable("Unrecognized FMA variant.");
18951 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
18952 MachineInstrBuilder MIB =
18953 BuildMI(MF, MI->getDebugLoc(), TII.get(NewFMAOpc))
18954 .addOperand(MI->getOperand(0))
18955 .addOperand(MI->getOperand(3))
18956 .addOperand(MI->getOperand(2))
18957 .addOperand(MI->getOperand(1));
18958 MBB->insert(MachineBasicBlock::iterator(MI), MIB);
18959 MI->eraseFromParent();
18966 MachineBasicBlock *
18967 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
18968 MachineBasicBlock *BB) const {
18969 switch (MI->getOpcode()) {
18970 default: llvm_unreachable("Unexpected instr type to insert");
18971 case X86::TAILJMPd64:
18972 case X86::TAILJMPr64:
18973 case X86::TAILJMPm64:
18974 llvm_unreachable("TAILJMP64 would not be touched here.");
18975 case X86::TCRETURNdi64:
18976 case X86::TCRETURNri64:
18977 case X86::TCRETURNmi64:
18979 case X86::WIN_ALLOCA:
18980 return EmitLoweredWinAlloca(MI, BB);
18981 case X86::SEG_ALLOCA_32:
18982 return EmitLoweredSegAlloca(MI, BB, false);
18983 case X86::SEG_ALLOCA_64:
18984 return EmitLoweredSegAlloca(MI, BB, true);
18985 case X86::TLSCall_32:
18986 case X86::TLSCall_64:
18987 return EmitLoweredTLSCall(MI, BB);
18988 case X86::CMOV_GR8:
18989 case X86::CMOV_FR32:
18990 case X86::CMOV_FR64:
18991 case X86::CMOV_V4F32:
18992 case X86::CMOV_V2F64:
18993 case X86::CMOV_V2I64:
18994 case X86::CMOV_V8F32:
18995 case X86::CMOV_V4F64:
18996 case X86::CMOV_V4I64:
18997 case X86::CMOV_V16F32:
18998 case X86::CMOV_V8F64:
18999 case X86::CMOV_V8I64:
19000 case X86::CMOV_GR16:
19001 case X86::CMOV_GR32:
19002 case X86::CMOV_RFP32:
19003 case X86::CMOV_RFP64:
19004 case X86::CMOV_RFP80:
19005 return EmitLoweredSelect(MI, BB);
19007 case X86::FP32_TO_INT16_IN_MEM:
19008 case X86::FP32_TO_INT32_IN_MEM:
19009 case X86::FP32_TO_INT64_IN_MEM:
19010 case X86::FP64_TO_INT16_IN_MEM:
19011 case X86::FP64_TO_INT32_IN_MEM:
19012 case X86::FP64_TO_INT64_IN_MEM:
19013 case X86::FP80_TO_INT16_IN_MEM:
19014 case X86::FP80_TO_INT32_IN_MEM:
19015 case X86::FP80_TO_INT64_IN_MEM: {
19016 MachineFunction *F = BB->getParent();
19017 const TargetInstrInfo *TII = F->getSubtarget().getInstrInfo();
19018 DebugLoc DL = MI->getDebugLoc();
19020 // Change the floating point control register to use "round towards zero"
19021 // mode when truncating to an integer value.
19022 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false);
19023 addFrameReference(BuildMI(*BB, MI, DL,
19024 TII->get(X86::FNSTCW16m)), CWFrameIdx);
19026 // Load the old value of the high byte of the control word...
19028 F->getRegInfo().createVirtualRegister(&X86::GR16RegClass);
19029 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW),
19032 // Set the high part to be round to zero...
19033 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
19036 // Reload the modified control word now...
19037 addFrameReference(BuildMI(*BB, MI, DL,
19038 TII->get(X86::FLDCW16m)), CWFrameIdx);
19040 // Restore the memory image of control word to original value
19041 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
19044 // Get the X86 opcode to use.
19046 switch (MI->getOpcode()) {
19047 default: llvm_unreachable("illegal opcode!");
19048 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
19049 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
19050 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
19051 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
19052 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
19053 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
19054 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
19055 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
19056 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
19060 MachineOperand &Op = MI->getOperand(0);
19062 AM.BaseType = X86AddressMode::RegBase;
19063 AM.Base.Reg = Op.getReg();
19065 AM.BaseType = X86AddressMode::FrameIndexBase;
19066 AM.Base.FrameIndex = Op.getIndex();
19068 Op = MI->getOperand(1);
19070 AM.Scale = Op.getImm();
19071 Op = MI->getOperand(2);
19073 AM.IndexReg = Op.getImm();
19074 Op = MI->getOperand(3);
19075 if (Op.isGlobal()) {
19076 AM.GV = Op.getGlobal();
19078 AM.Disp = Op.getImm();
19080 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM)
19081 .addReg(MI->getOperand(X86::AddrNumOperands).getReg());
19083 // Reload the original control word now.
19084 addFrameReference(BuildMI(*BB, MI, DL,
19085 TII->get(X86::FLDCW16m)), CWFrameIdx);
19087 MI->eraseFromParent(); // The pseudo instruction is gone now.
19090 // String/text processing lowering.
19091 case X86::PCMPISTRM128REG:
19092 case X86::VPCMPISTRM128REG:
19093 case X86::PCMPISTRM128MEM:
19094 case X86::VPCMPISTRM128MEM:
19095 case X86::PCMPESTRM128REG:
19096 case X86::VPCMPESTRM128REG:
19097 case X86::PCMPESTRM128MEM:
19098 case X86::VPCMPESTRM128MEM:
19099 assert(Subtarget->hasSSE42() &&
19100 "Target must have SSE4.2 or AVX features enabled");
19101 return EmitPCMPSTRM(MI, BB, BB->getParent()->getSubtarget().getInstrInfo());
19103 // String/text processing lowering.
19104 case X86::PCMPISTRIREG:
19105 case X86::VPCMPISTRIREG:
19106 case X86::PCMPISTRIMEM:
19107 case X86::VPCMPISTRIMEM:
19108 case X86::PCMPESTRIREG:
19109 case X86::VPCMPESTRIREG:
19110 case X86::PCMPESTRIMEM:
19111 case X86::VPCMPESTRIMEM:
19112 assert(Subtarget->hasSSE42() &&
19113 "Target must have SSE4.2 or AVX features enabled");
19114 return EmitPCMPSTRI(MI, BB, BB->getParent()->getSubtarget().getInstrInfo());
19116 // Thread synchronization.
19118 return EmitMonitor(MI, BB, BB->getParent()->getSubtarget().getInstrInfo(),
19123 return EmitXBegin(MI, BB, BB->getParent()->getSubtarget().getInstrInfo());
19125 case X86::VASTART_SAVE_XMM_REGS:
19126 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
19128 case X86::VAARG_64:
19129 return EmitVAARG64WithCustomInserter(MI, BB);
19131 case X86::EH_SjLj_SetJmp32:
19132 case X86::EH_SjLj_SetJmp64:
19133 return emitEHSjLjSetJmp(MI, BB);
19135 case X86::EH_SjLj_LongJmp32:
19136 case X86::EH_SjLj_LongJmp64:
19137 return emitEHSjLjLongJmp(MI, BB);
19139 case TargetOpcode::STACKMAP:
19140 case TargetOpcode::PATCHPOINT:
19141 return emitPatchPoint(MI, BB);
19143 case X86::VFMADDPDr213r:
19144 case X86::VFMADDPSr213r:
19145 case X86::VFMADDSDr213r:
19146 case X86::VFMADDSSr213r:
19147 case X86::VFMSUBPDr213r:
19148 case X86::VFMSUBPSr213r:
19149 case X86::VFMSUBSDr213r:
19150 case X86::VFMSUBSSr213r:
19151 case X86::VFNMADDPDr213r:
19152 case X86::VFNMADDPSr213r:
19153 case X86::VFNMADDSDr213r:
19154 case X86::VFNMADDSSr213r:
19155 case X86::VFNMSUBPDr213r:
19156 case X86::VFNMSUBPSr213r:
19157 case X86::VFNMSUBSDr213r:
19158 case X86::VFNMSUBSSr213r:
19159 case X86::VFMADDPDr213rY:
19160 case X86::VFMADDPSr213rY:
19161 case X86::VFMSUBPDr213rY:
19162 case X86::VFMSUBPSr213rY:
19163 case X86::VFNMADDPDr213rY:
19164 case X86::VFNMADDPSr213rY:
19165 case X86::VFNMSUBPDr213rY:
19166 case X86::VFNMSUBPSr213rY:
19167 return emitFMA3Instr(MI, BB);
19171 //===----------------------------------------------------------------------===//
19172 // X86 Optimization Hooks
19173 //===----------------------------------------------------------------------===//
19175 void X86TargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
19178 const SelectionDAG &DAG,
19179 unsigned Depth) const {
19180 unsigned BitWidth = KnownZero.getBitWidth();
19181 unsigned Opc = Op.getOpcode();
19182 assert((Opc >= ISD::BUILTIN_OP_END ||
19183 Opc == ISD::INTRINSIC_WO_CHAIN ||
19184 Opc == ISD::INTRINSIC_W_CHAIN ||
19185 Opc == ISD::INTRINSIC_VOID) &&
19186 "Should use MaskedValueIsZero if you don't know whether Op"
19187 " is a target node!");
19189 KnownZero = KnownOne = APInt(BitWidth, 0); // Don't know anything.
19203 // These nodes' second result is a boolean.
19204 if (Op.getResNo() == 0)
19207 case X86ISD::SETCC:
19208 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1);
19210 case ISD::INTRINSIC_WO_CHAIN: {
19211 unsigned IntId = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
19212 unsigned NumLoBits = 0;
19215 case Intrinsic::x86_sse_movmsk_ps:
19216 case Intrinsic::x86_avx_movmsk_ps_256:
19217 case Intrinsic::x86_sse2_movmsk_pd:
19218 case Intrinsic::x86_avx_movmsk_pd_256:
19219 case Intrinsic::x86_mmx_pmovmskb:
19220 case Intrinsic::x86_sse2_pmovmskb_128:
19221 case Intrinsic::x86_avx2_pmovmskb: {
19222 // High bits of movmskp{s|d}, pmovmskb are known zero.
19224 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
19225 case Intrinsic::x86_sse_movmsk_ps: NumLoBits = 4; break;
19226 case Intrinsic::x86_avx_movmsk_ps_256: NumLoBits = 8; break;
19227 case Intrinsic::x86_sse2_movmsk_pd: NumLoBits = 2; break;
19228 case Intrinsic::x86_avx_movmsk_pd_256: NumLoBits = 4; break;
19229 case Intrinsic::x86_mmx_pmovmskb: NumLoBits = 8; break;
19230 case Intrinsic::x86_sse2_pmovmskb_128: NumLoBits = 16; break;
19231 case Intrinsic::x86_avx2_pmovmskb: NumLoBits = 32; break;
19233 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - NumLoBits);
19242 unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(
19244 const SelectionDAG &,
19245 unsigned Depth) const {
19246 // SETCC_CARRY sets the dest to ~0 for true or 0 for false.
19247 if (Op.getOpcode() == X86ISD::SETCC_CARRY)
19248 return Op.getValueType().getScalarType().getSizeInBits();
19254 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
19255 /// node is a GlobalAddress + offset.
19256 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
19257 const GlobalValue* &GA,
19258 int64_t &Offset) const {
19259 if (N->getOpcode() == X86ISD::Wrapper) {
19260 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
19261 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
19262 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
19266 return TargetLowering::isGAPlusOffset(N, GA, Offset);
19269 /// isShuffleHigh128VectorInsertLow - Checks whether the shuffle node is the
19270 /// same as extracting the high 128-bit part of 256-bit vector and then
19271 /// inserting the result into the low part of a new 256-bit vector
19272 static bool isShuffleHigh128VectorInsertLow(ShuffleVectorSDNode *SVOp) {
19273 EVT VT = SVOp->getValueType(0);
19274 unsigned NumElems = VT.getVectorNumElements();
19276 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
19277 for (unsigned i = 0, j = NumElems/2; i != NumElems/2; ++i, ++j)
19278 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
19279 SVOp->getMaskElt(j) >= 0)
19285 /// isShuffleLow128VectorInsertHigh - Checks whether the shuffle node is the
19286 /// same as extracting the low 128-bit part of 256-bit vector and then
19287 /// inserting the result into the high part of a new 256-bit vector
19288 static bool isShuffleLow128VectorInsertHigh(ShuffleVectorSDNode *SVOp) {
19289 EVT VT = SVOp->getValueType(0);
19290 unsigned NumElems = VT.getVectorNumElements();
19292 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
19293 for (unsigned i = NumElems/2, j = 0; i != NumElems; ++i, ++j)
19294 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
19295 SVOp->getMaskElt(j) >= 0)
19301 /// PerformShuffleCombine256 - Performs shuffle combines for 256-bit vectors.
19302 static SDValue PerformShuffleCombine256(SDNode *N, SelectionDAG &DAG,
19303 TargetLowering::DAGCombinerInfo &DCI,
19304 const X86Subtarget* Subtarget) {
19306 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
19307 SDValue V1 = SVOp->getOperand(0);
19308 SDValue V2 = SVOp->getOperand(1);
19309 EVT VT = SVOp->getValueType(0);
19310 unsigned NumElems = VT.getVectorNumElements();
19312 if (V1.getOpcode() == ISD::CONCAT_VECTORS &&
19313 V2.getOpcode() == ISD::CONCAT_VECTORS) {
19317 // V UNDEF BUILD_VECTOR UNDEF
19319 // CONCAT_VECTOR CONCAT_VECTOR
19322 // RESULT: V + zero extended
19324 if (V2.getOperand(0).getOpcode() != ISD::BUILD_VECTOR ||
19325 V2.getOperand(1).getOpcode() != ISD::UNDEF ||
19326 V1.getOperand(1).getOpcode() != ISD::UNDEF)
19329 if (!ISD::isBuildVectorAllZeros(V2.getOperand(0).getNode()))
19332 // To match the shuffle mask, the first half of the mask should
19333 // be exactly the first vector, and all the rest a splat with the
19334 // first element of the second one.
19335 for (unsigned i = 0; i != NumElems/2; ++i)
19336 if (!isUndefOrEqual(SVOp->getMaskElt(i), i) ||
19337 !isUndefOrEqual(SVOp->getMaskElt(i+NumElems/2), NumElems))
19340 // If V1 is coming from a vector load then just fold to a VZEXT_LOAD.
19341 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(V1.getOperand(0))) {
19342 if (Ld->hasNUsesOfValue(1, 0)) {
19343 SDVTList Tys = DAG.getVTList(MVT::v4i64, MVT::Other);
19344 SDValue Ops[] = { Ld->getChain(), Ld->getBasePtr() };
19346 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops,
19348 Ld->getPointerInfo(),
19349 Ld->getAlignment(),
19350 false/*isVolatile*/, true/*ReadMem*/,
19351 false/*WriteMem*/);
19353 // Make sure the newly-created LOAD is in the same position as Ld in
19354 // terms of dependency. We create a TokenFactor for Ld and ResNode,
19355 // and update uses of Ld's output chain to use the TokenFactor.
19356 if (Ld->hasAnyUseOfValue(1)) {
19357 SDValue NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
19358 SDValue(Ld, 1), SDValue(ResNode.getNode(), 1));
19359 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), NewChain);
19360 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(Ld, 1),
19361 SDValue(ResNode.getNode(), 1));
19364 return DAG.getNode(ISD::BITCAST, dl, VT, ResNode);
19368 // Emit a zeroed vector and insert the desired subvector on its
19370 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
19371 SDValue InsV = Insert128BitVector(Zeros, V1.getOperand(0), 0, DAG, dl);
19372 return DCI.CombineTo(N, InsV);
19375 //===--------------------------------------------------------------------===//
19376 // Combine some shuffles into subvector extracts and inserts:
19379 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
19380 if (isShuffleHigh128VectorInsertLow(SVOp)) {
19381 SDValue V = Extract128BitVector(V1, NumElems/2, DAG, dl);
19382 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, 0, DAG, dl);
19383 return DCI.CombineTo(N, InsV);
19386 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
19387 if (isShuffleLow128VectorInsertHigh(SVOp)) {
19388 SDValue V = Extract128BitVector(V1, 0, DAG, dl);
19389 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, NumElems/2, DAG, dl);
19390 return DCI.CombineTo(N, InsV);
19396 /// \brief Combine an arbitrary chain of shuffles into a single instruction if
19399 /// This is the leaf of the recursive combinine below. When we have found some
19400 /// chain of single-use x86 shuffle instructions and accumulated the combined
19401 /// shuffle mask represented by them, this will try to pattern match that mask
19402 /// into either a single instruction if there is a special purpose instruction
19403 /// for this operation, or into a PSHUFB instruction which is a fully general
19404 /// instruction but should only be used to replace chains over a certain depth.
19405 static bool combineX86ShuffleChain(SDValue Op, SDValue Root, ArrayRef<int> Mask,
19406 int Depth, bool HasPSHUFB, SelectionDAG &DAG,
19407 TargetLowering::DAGCombinerInfo &DCI,
19408 const X86Subtarget *Subtarget) {
19409 assert(!Mask.empty() && "Cannot combine an empty shuffle mask!");
19411 // Find the operand that enters the chain. Note that multiple uses are OK
19412 // here, we're not going to remove the operand we find.
19413 SDValue Input = Op.getOperand(0);
19414 while (Input.getOpcode() == ISD::BITCAST)
19415 Input = Input.getOperand(0);
19417 MVT VT = Input.getSimpleValueType();
19418 MVT RootVT = Root.getSimpleValueType();
19421 // Just remove no-op shuffle masks.
19422 if (Mask.size() == 1) {
19423 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Input),
19428 // Use the float domain if the operand type is a floating point type.
19429 bool FloatDomain = VT.isFloatingPoint();
19431 // If we don't have access to VEX encodings, the generic PSHUF instructions
19432 // are preferable to some of the specialized forms despite requiring one more
19433 // byte to encode because they can implicitly copy.
19435 // IF we *do* have VEX encodings, than we can use shorter, more specific
19436 // shuffle instructions freely as they can copy due to the extra register
19438 if (Subtarget->hasAVX()) {
19439 // We have both floating point and integer variants of shuffles that dup
19440 // either the low or high half of the vector.
19441 if (Mask.equals(0, 0) || Mask.equals(1, 1)) {
19442 bool Lo = Mask.equals(0, 0);
19443 unsigned Shuffle = FloatDomain ? (Lo ? X86ISD::MOVLHPS : X86ISD::MOVHLPS)
19444 : (Lo ? X86ISD::UNPCKL : X86ISD::UNPCKH);
19445 if (Depth == 1 && Root->getOpcode() == Shuffle)
19446 return false; // Nothing to do!
19447 MVT ShuffleVT = FloatDomain ? MVT::v4f32 : MVT::v2i64;
19448 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
19449 DCI.AddToWorklist(Op.getNode());
19450 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
19451 DCI.AddToWorklist(Op.getNode());
19452 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
19457 // FIXME: We should match UNPCKLPS and UNPCKHPS here.
19459 // For the integer domain we have specialized instructions for duplicating
19460 // any element size from the low or high half.
19461 if (!FloatDomain &&
19462 (Mask.equals(0, 0, 1, 1) || Mask.equals(2, 2, 3, 3) ||
19463 Mask.equals(0, 0, 1, 1, 2, 2, 3, 3) ||
19464 Mask.equals(4, 4, 5, 5, 6, 6, 7, 7) ||
19465 Mask.equals(0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7) ||
19466 Mask.equals(8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15,
19468 bool Lo = Mask[0] == 0;
19469 unsigned Shuffle = Lo ? X86ISD::UNPCKL : X86ISD::UNPCKH;
19470 if (Depth == 1 && Root->getOpcode() == Shuffle)
19471 return false; // Nothing to do!
19473 switch (Mask.size()) {
19474 case 4: ShuffleVT = MVT::v4i32; break;
19475 case 8: ShuffleVT = MVT::v8i16; break;
19476 case 16: ShuffleVT = MVT::v16i8; break;
19478 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
19479 DCI.AddToWorklist(Op.getNode());
19480 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
19481 DCI.AddToWorklist(Op.getNode());
19482 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
19488 // Don't try to re-form single instruction chains under any circumstances now
19489 // that we've done encoding canonicalization for them.
19493 // If we have 3 or more shuffle instructions or a chain involving PSHUFB, we
19494 // can replace them with a single PSHUFB instruction profitably. Intel's
19495 // manuals suggest only using PSHUFB if doing so replacing 5 instructions, but
19496 // in practice PSHUFB tends to be *very* fast so we're more aggressive.
19497 if ((Depth >= 3 || HasPSHUFB) && Subtarget->hasSSSE3()) {
19498 SmallVector<SDValue, 16> PSHUFBMask;
19499 assert(Mask.size() <= 16 && "Can't shuffle elements smaller than bytes!");
19500 int Ratio = 16 / Mask.size();
19501 for (unsigned i = 0; i < 16; ++i) {
19502 int M = Mask[i / Ratio] != SM_SentinelZero
19503 ? Ratio * Mask[i / Ratio] + i % Ratio
19505 PSHUFBMask.push_back(DAG.getConstant(M, MVT::i8));
19507 Op = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Input);
19508 DCI.AddToWorklist(Op.getNode());
19509 SDValue PSHUFBMaskOp =
19510 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, PSHUFBMask);
19511 DCI.AddToWorklist(PSHUFBMaskOp.getNode());
19512 Op = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, Op, PSHUFBMaskOp);
19513 DCI.AddToWorklist(Op.getNode());
19514 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
19519 // Failed to find any combines.
19523 /// \brief Fully generic combining of x86 shuffle instructions.
19525 /// This should be the last combine run over the x86 shuffle instructions. Once
19526 /// they have been fully optimized, this will recursively consider all chains
19527 /// of single-use shuffle instructions, build a generic model of the cumulative
19528 /// shuffle operation, and check for simpler instructions which implement this
19529 /// operation. We use this primarily for two purposes:
19531 /// 1) Collapse generic shuffles to specialized single instructions when
19532 /// equivalent. In most cases, this is just an encoding size win, but
19533 /// sometimes we will collapse multiple generic shuffles into a single
19534 /// special-purpose shuffle.
19535 /// 2) Look for sequences of shuffle instructions with 3 or more total
19536 /// instructions, and replace them with the slightly more expensive SSSE3
19537 /// PSHUFB instruction if available. We do this as the last combining step
19538 /// to ensure we avoid using PSHUFB if we can implement the shuffle with
19539 /// a suitable short sequence of other instructions. The PHUFB will either
19540 /// use a register or have to read from memory and so is slightly (but only
19541 /// slightly) more expensive than the other shuffle instructions.
19543 /// Because this is inherently a quadratic operation (for each shuffle in
19544 /// a chain, we recurse up the chain), the depth is limited to 8 instructions.
19545 /// This should never be an issue in practice as the shuffle lowering doesn't
19546 /// produce sequences of more than 8 instructions.
19548 /// FIXME: We will currently miss some cases where the redundant shuffling
19549 /// would simplify under the threshold for PSHUFB formation because of
19550 /// combine-ordering. To fix this, we should do the redundant instruction
19551 /// combining in this recursive walk.
19552 static bool combineX86ShufflesRecursively(SDValue Op, SDValue Root,
19553 ArrayRef<int> RootMask,
19554 int Depth, bool HasPSHUFB,
19556 TargetLowering::DAGCombinerInfo &DCI,
19557 const X86Subtarget *Subtarget) {
19558 // Bound the depth of our recursive combine because this is ultimately
19559 // quadratic in nature.
19563 // Directly rip through bitcasts to find the underlying operand.
19564 while (Op.getOpcode() == ISD::BITCAST && Op.getOperand(0).hasOneUse())
19565 Op = Op.getOperand(0);
19567 MVT VT = Op.getSimpleValueType();
19568 if (!VT.isVector())
19569 return false; // Bail if we hit a non-vector.
19570 // FIXME: This routine should be taught about 256-bit shuffles, or a 256-bit
19571 // version should be added.
19572 if (VT.getSizeInBits() != 128)
19575 assert(Root.getSimpleValueType().isVector() &&
19576 "Shuffles operate on vector types!");
19577 assert(VT.getSizeInBits() == Root.getSimpleValueType().getSizeInBits() &&
19578 "Can only combine shuffles of the same vector register size.");
19580 if (!isTargetShuffle(Op.getOpcode()))
19582 SmallVector<int, 16> OpMask;
19584 bool HaveMask = getTargetShuffleMask(Op.getNode(), VT, OpMask, IsUnary);
19585 // We only can combine unary shuffles which we can decode the mask for.
19586 if (!HaveMask || !IsUnary)
19589 assert(VT.getVectorNumElements() == OpMask.size() &&
19590 "Different mask size from vector size!");
19591 assert(((RootMask.size() > OpMask.size() &&
19592 RootMask.size() % OpMask.size() == 0) ||
19593 (OpMask.size() > RootMask.size() &&
19594 OpMask.size() % RootMask.size() == 0) ||
19595 OpMask.size() == RootMask.size()) &&
19596 "The smaller number of elements must divide the larger.");
19597 int RootRatio = std::max<int>(1, OpMask.size() / RootMask.size());
19598 int OpRatio = std::max<int>(1, RootMask.size() / OpMask.size());
19599 assert(((RootRatio == 1 && OpRatio == 1) ||
19600 (RootRatio == 1) != (OpRatio == 1)) &&
19601 "Must not have a ratio for both incoming and op masks!");
19603 SmallVector<int, 16> Mask;
19604 Mask.reserve(std::max(OpMask.size(), RootMask.size()));
19606 // Merge this shuffle operation's mask into our accumulated mask. Note that
19607 // this shuffle's mask will be the first applied to the input, followed by the
19608 // root mask to get us all the way to the root value arrangement. The reason
19609 // for this order is that we are recursing up the operation chain.
19610 for (int i = 0, e = std::max(OpMask.size(), RootMask.size()); i < e; ++i) {
19611 int RootIdx = i / RootRatio;
19612 if (RootMask[RootIdx] == SM_SentinelZero) {
19613 // This is a zero-ed lane, we're done.
19614 Mask.push_back(SM_SentinelZero);
19618 int RootMaskedIdx = RootMask[RootIdx] * RootRatio + i % RootRatio;
19619 int OpIdx = RootMaskedIdx / OpRatio;
19620 if (OpMask[OpIdx] == SM_SentinelZero) {
19621 // The incoming lanes are zero, it doesn't matter which ones we are using.
19622 Mask.push_back(SM_SentinelZero);
19626 // Ok, we have non-zero lanes, map them through.
19627 Mask.push_back(OpMask[OpIdx] * OpRatio +
19628 RootMaskedIdx % OpRatio);
19631 // See if we can recurse into the operand to combine more things.
19632 switch (Op.getOpcode()) {
19633 case X86ISD::PSHUFB:
19635 case X86ISD::PSHUFD:
19636 case X86ISD::PSHUFHW:
19637 case X86ISD::PSHUFLW:
19638 if (Op.getOperand(0).hasOneUse() &&
19639 combineX86ShufflesRecursively(Op.getOperand(0), Root, Mask, Depth + 1,
19640 HasPSHUFB, DAG, DCI, Subtarget))
19644 case X86ISD::UNPCKL:
19645 case X86ISD::UNPCKH:
19646 assert(Op.getOperand(0) == Op.getOperand(1) && "We only combine unary shuffles!");
19647 // We can't check for single use, we have to check that this shuffle is the only user.
19648 if (Op->isOnlyUserOf(Op.getOperand(0).getNode()) &&
19649 combineX86ShufflesRecursively(Op.getOperand(0), Root, Mask, Depth + 1,
19650 HasPSHUFB, DAG, DCI, Subtarget))
19655 // Minor canonicalization of the accumulated shuffle mask to make it easier
19656 // to match below. All this does is detect masks with squential pairs of
19657 // elements, and shrink them to the half-width mask. It does this in a loop
19658 // so it will reduce the size of the mask to the minimal width mask which
19659 // performs an equivalent shuffle.
19660 while (Mask.size() > 1 && canWidenShuffleElements(Mask)) {
19661 for (int i = 0, e = Mask.size() / 2; i < e; ++i)
19662 Mask[i] = Mask[2 * i] / 2;
19663 Mask.resize(Mask.size() / 2);
19666 return combineX86ShuffleChain(Op, Root, Mask, Depth, HasPSHUFB, DAG, DCI,
19670 /// \brief Get the PSHUF-style mask from PSHUF node.
19672 /// This is a very minor wrapper around getTargetShuffleMask to easy forming v4
19673 /// PSHUF-style masks that can be reused with such instructions.
19674 static SmallVector<int, 4> getPSHUFShuffleMask(SDValue N) {
19675 SmallVector<int, 4> Mask;
19677 bool HaveMask = getTargetShuffleMask(N.getNode(), N.getSimpleValueType(), Mask, IsUnary);
19681 switch (N.getOpcode()) {
19682 case X86ISD::PSHUFD:
19684 case X86ISD::PSHUFLW:
19687 case X86ISD::PSHUFHW:
19688 Mask.erase(Mask.begin(), Mask.begin() + 4);
19689 for (int &M : Mask)
19693 llvm_unreachable("No valid shuffle instruction found!");
19697 /// \brief Search for a combinable shuffle across a chain ending in pshufd.
19699 /// We walk up the chain and look for a combinable shuffle, skipping over
19700 /// shuffles that we could hoist this shuffle's transformation past without
19701 /// altering anything.
19702 static bool combineRedundantDWordShuffle(SDValue N, MutableArrayRef<int> Mask,
19704 TargetLowering::DAGCombinerInfo &DCI) {
19705 assert(N.getOpcode() == X86ISD::PSHUFD &&
19706 "Called with something other than an x86 128-bit half shuffle!");
19709 // Walk up a single-use chain looking for a combinable shuffle.
19710 SDValue V = N.getOperand(0);
19711 for (; V.hasOneUse(); V = V.getOperand(0)) {
19712 switch (V.getOpcode()) {
19714 return false; // Nothing combined!
19717 // Skip bitcasts as we always know the type for the target specific
19721 case X86ISD::PSHUFD:
19722 // Found another dword shuffle.
19725 case X86ISD::PSHUFLW:
19726 // Check that the low words (being shuffled) are the identity in the
19727 // dword shuffle, and the high words are self-contained.
19728 if (Mask[0] != 0 || Mask[1] != 1 ||
19729 !(Mask[2] >= 2 && Mask[2] < 4 && Mask[3] >= 2 && Mask[3] < 4))
19734 case X86ISD::PSHUFHW:
19735 // Check that the high words (being shuffled) are the identity in the
19736 // dword shuffle, and the low words are self-contained.
19737 if (Mask[2] != 2 || Mask[3] != 3 ||
19738 !(Mask[0] >= 0 && Mask[0] < 2 && Mask[1] >= 0 && Mask[1] < 2))
19743 case X86ISD::UNPCKL:
19744 case X86ISD::UNPCKH:
19745 // For either i8 -> i16 or i16 -> i32 unpacks, we can combine a dword
19746 // shuffle into a preceding word shuffle.
19747 if (V.getValueType() != MVT::v16i8 && V.getValueType() != MVT::v8i16)
19750 // Search for a half-shuffle which we can combine with.
19751 unsigned CombineOp =
19752 V.getOpcode() == X86ISD::UNPCKL ? X86ISD::PSHUFLW : X86ISD::PSHUFHW;
19753 if (V.getOperand(0) != V.getOperand(1) ||
19754 !V->isOnlyUserOf(V.getOperand(0).getNode()))
19756 V = V.getOperand(0);
19758 switch (V.getOpcode()) {
19760 return false; // Nothing to combine.
19762 case X86ISD::PSHUFLW:
19763 case X86ISD::PSHUFHW:
19764 if (V.getOpcode() == CombineOp)
19769 V = V.getOperand(0);
19773 } while (V.hasOneUse());
19776 // Break out of the loop if we break out of the switch.
19780 if (!V.hasOneUse())
19781 // We fell out of the loop without finding a viable combining instruction.
19784 // Record the old value to use in RAUW-ing.
19787 // Merge this node's mask and our incoming mask.
19788 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
19789 for (int &M : Mask)
19791 V = DAG.getNode(V.getOpcode(), DL, V.getValueType(), V.getOperand(0),
19792 getV4X86ShuffleImm8ForMask(Mask, DAG));
19794 // It is possible that one of the combinable shuffles was completely absorbed
19795 // by the other, just replace it and revisit all users in that case.
19796 if (Old.getNode() == V.getNode()) {
19797 DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo=*/true);
19801 // Replace N with its operand as we're going to combine that shuffle away.
19802 DAG.ReplaceAllUsesWith(N, N.getOperand(0));
19804 // Replace the combinable shuffle with the combined one, updating all users
19805 // so that we re-evaluate the chain here.
19806 DCI.CombineTo(Old.getNode(), V, /*AddTo*/ true);
19810 /// \brief Search for a combinable shuffle across a chain ending in pshuflw or pshufhw.
19812 /// We walk up the chain, skipping shuffles of the other half and looking
19813 /// through shuffles which switch halves trying to find a shuffle of the same
19814 /// pair of dwords.
19815 static bool combineRedundantHalfShuffle(SDValue N, MutableArrayRef<int> Mask,
19817 TargetLowering::DAGCombinerInfo &DCI) {
19819 (N.getOpcode() == X86ISD::PSHUFLW || N.getOpcode() == X86ISD::PSHUFHW) &&
19820 "Called with something other than an x86 128-bit half shuffle!");
19822 unsigned CombineOpcode = N.getOpcode();
19824 // Walk up a single-use chain looking for a combinable shuffle.
19825 SDValue V = N.getOperand(0);
19826 for (; V.hasOneUse(); V = V.getOperand(0)) {
19827 switch (V.getOpcode()) {
19829 return false; // Nothing combined!
19832 // Skip bitcasts as we always know the type for the target specific
19836 case X86ISD::PSHUFLW:
19837 case X86ISD::PSHUFHW:
19838 if (V.getOpcode() == CombineOpcode)
19841 // Other-half shuffles are no-ops.
19844 // Break out of the loop if we break out of the switch.
19848 if (!V.hasOneUse())
19849 // We fell out of the loop without finding a viable combining instruction.
19852 // Combine away the bottom node as its shuffle will be accumulated into
19853 // a preceding shuffle.
19854 DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
19856 // Record the old value.
19859 // Merge this node's mask and our incoming mask (adjusted to account for all
19860 // the pshufd instructions encountered).
19861 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
19862 for (int &M : Mask)
19864 V = DAG.getNode(V.getOpcode(), DL, MVT::v8i16, V.getOperand(0),
19865 getV4X86ShuffleImm8ForMask(Mask, DAG));
19867 // Check that the shuffles didn't cancel each other out. If not, we need to
19868 // combine to the new one.
19870 // Replace the combinable shuffle with the combined one, updating all users
19871 // so that we re-evaluate the chain here.
19872 DCI.CombineTo(Old.getNode(), V, /*AddTo*/ true);
19877 /// \brief Try to combine x86 target specific shuffles.
19878 static SDValue PerformTargetShuffleCombine(SDValue N, SelectionDAG &DAG,
19879 TargetLowering::DAGCombinerInfo &DCI,
19880 const X86Subtarget *Subtarget) {
19882 MVT VT = N.getSimpleValueType();
19883 SmallVector<int, 4> Mask;
19885 switch (N.getOpcode()) {
19886 case X86ISD::PSHUFD:
19887 case X86ISD::PSHUFLW:
19888 case X86ISD::PSHUFHW:
19889 Mask = getPSHUFShuffleMask(N);
19890 assert(Mask.size() == 4);
19896 // Nuke no-op shuffles that show up after combining.
19897 if (isNoopShuffleMask(Mask))
19898 return DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
19900 // Look for simplifications involving one or two shuffle instructions.
19901 SDValue V = N.getOperand(0);
19902 switch (N.getOpcode()) {
19905 case X86ISD::PSHUFLW:
19906 case X86ISD::PSHUFHW:
19907 assert(VT == MVT::v8i16);
19910 if (combineRedundantHalfShuffle(N, Mask, DAG, DCI))
19911 return SDValue(); // We combined away this shuffle, so we're done.
19913 // See if this reduces to a PSHUFD which is no more expensive and can
19914 // combine with more operations.
19915 if (canWidenShuffleElements(Mask)) {
19916 int DMask[] = {-1, -1, -1, -1};
19917 int DOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 2;
19918 DMask[DOffset + 0] = DOffset + Mask[0] / 2;
19919 DMask[DOffset + 1] = DOffset + Mask[2] / 2;
19920 V = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V);
19921 DCI.AddToWorklist(V.getNode());
19922 V = DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V,
19923 getV4X86ShuffleImm8ForMask(DMask, DAG));
19924 DCI.AddToWorklist(V.getNode());
19925 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V);
19928 // Look for shuffle patterns which can be implemented as a single unpack.
19929 // FIXME: This doesn't handle the location of the PSHUFD generically, and
19930 // only works when we have a PSHUFD followed by two half-shuffles.
19931 if (Mask[0] == Mask[1] && Mask[2] == Mask[3] &&
19932 (V.getOpcode() == X86ISD::PSHUFLW ||
19933 V.getOpcode() == X86ISD::PSHUFHW) &&
19934 V.getOpcode() != N.getOpcode() &&
19936 SDValue D = V.getOperand(0);
19937 while (D.getOpcode() == ISD::BITCAST && D.hasOneUse())
19938 D = D.getOperand(0);
19939 if (D.getOpcode() == X86ISD::PSHUFD && D.hasOneUse()) {
19940 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
19941 SmallVector<int, 4> DMask = getPSHUFShuffleMask(D);
19942 int NOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
19943 int VOffset = V.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
19945 for (int i = 0; i < 4; ++i) {
19946 WordMask[i + NOffset] = Mask[i] + NOffset;
19947 WordMask[i + VOffset] = VMask[i] + VOffset;
19949 // Map the word mask through the DWord mask.
19951 for (int i = 0; i < 8; ++i)
19952 MappedMask[i] = 2 * DMask[WordMask[i] / 2] + WordMask[i] % 2;
19953 const int UnpackLoMask[] = {0, 0, 1, 1, 2, 2, 3, 3};
19954 const int UnpackHiMask[] = {4, 4, 5, 5, 6, 6, 7, 7};
19955 if (std::equal(std::begin(MappedMask), std::end(MappedMask),
19956 std::begin(UnpackLoMask)) ||
19957 std::equal(std::begin(MappedMask), std::end(MappedMask),
19958 std::begin(UnpackHiMask))) {
19959 // We can replace all three shuffles with an unpack.
19960 V = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, D.getOperand(0));
19961 DCI.AddToWorklist(V.getNode());
19962 return DAG.getNode(MappedMask[0] == 0 ? X86ISD::UNPCKL
19964 DL, MVT::v8i16, V, V);
19971 case X86ISD::PSHUFD:
19972 if (combineRedundantDWordShuffle(N, Mask, DAG, DCI))
19973 return SDValue(); // We combined away this shuffle.
19981 /// PerformShuffleCombine - Performs several different shuffle combines.
19982 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
19983 TargetLowering::DAGCombinerInfo &DCI,
19984 const X86Subtarget *Subtarget) {
19986 SDValue N0 = N->getOperand(0);
19987 SDValue N1 = N->getOperand(1);
19988 EVT VT = N->getValueType(0);
19990 // Don't create instructions with illegal types after legalize types has run.
19991 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
19992 if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType()))
19995 // Combine 256-bit vector shuffles. This is only profitable when in AVX mode
19996 if (Subtarget->hasFp256() && VT.is256BitVector() &&
19997 N->getOpcode() == ISD::VECTOR_SHUFFLE)
19998 return PerformShuffleCombine256(N, DAG, DCI, Subtarget);
20000 // During Type Legalization, when promoting illegal vector types,
20001 // the backend might introduce new shuffle dag nodes and bitcasts.
20003 // This code performs the following transformation:
20004 // fold: (shuffle (bitcast (BINOP A, B)), Undef, <Mask>) ->
20005 // (shuffle (BINOP (bitcast A), (bitcast B)), Undef, <Mask>)
20007 // We do this only if both the bitcast and the BINOP dag nodes have
20008 // one use. Also, perform this transformation only if the new binary
20009 // operation is legal. This is to avoid introducing dag nodes that
20010 // potentially need to be further expanded (or custom lowered) into a
20011 // less optimal sequence of dag nodes.
20012 if (!DCI.isBeforeLegalize() && DCI.isBeforeLegalizeOps() &&
20013 N1.getOpcode() == ISD::UNDEF && N0.hasOneUse() &&
20014 N0.getOpcode() == ISD::BITCAST) {
20015 SDValue BC0 = N0.getOperand(0);
20016 EVT SVT = BC0.getValueType();
20017 unsigned Opcode = BC0.getOpcode();
20018 unsigned NumElts = VT.getVectorNumElements();
20020 if (BC0.hasOneUse() && SVT.isVector() &&
20021 SVT.getVectorNumElements() * 2 == NumElts &&
20022 TLI.isOperationLegal(Opcode, VT)) {
20023 bool CanFold = false;
20035 unsigned SVTNumElts = SVT.getVectorNumElements();
20036 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
20037 for (unsigned i = 0, e = SVTNumElts; i != e && CanFold; ++i)
20038 CanFold = SVOp->getMaskElt(i) == (int)(i * 2);
20039 for (unsigned i = SVTNumElts, e = NumElts; i != e && CanFold; ++i)
20040 CanFold = SVOp->getMaskElt(i) < 0;
20043 SDValue BC00 = DAG.getNode(ISD::BITCAST, dl, VT, BC0.getOperand(0));
20044 SDValue BC01 = DAG.getNode(ISD::BITCAST, dl, VT, BC0.getOperand(1));
20045 SDValue NewBinOp = DAG.getNode(BC0.getOpcode(), dl, VT, BC00, BC01);
20046 return DAG.getVectorShuffle(VT, dl, NewBinOp, N1, &SVOp->getMask()[0]);
20051 // Only handle 128 wide vector from here on.
20052 if (!VT.is128BitVector())
20055 // Combine a vector_shuffle that is equal to build_vector load1, load2, load3,
20056 // load4, <0, 1, 2, 3> into a 128-bit load if the load addresses are
20057 // consecutive, non-overlapping, and in the right order.
20058 SmallVector<SDValue, 16> Elts;
20059 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
20060 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0));
20062 SDValue LD = EltsFromConsecutiveLoads(VT, Elts, dl, DAG, true);
20066 if (isTargetShuffle(N->getOpcode())) {
20068 PerformTargetShuffleCombine(SDValue(N, 0), DAG, DCI, Subtarget);
20069 if (Shuffle.getNode())
20072 // Try recursively combining arbitrary sequences of x86 shuffle
20073 // instructions into higher-order shuffles. We do this after combining
20074 // specific PSHUF instruction sequences into their minimal form so that we
20075 // can evaluate how many specialized shuffle instructions are involved in
20076 // a particular chain.
20077 SmallVector<int, 1> NonceMask; // Just a placeholder.
20078 NonceMask.push_back(0);
20079 if (combineX86ShufflesRecursively(SDValue(N, 0), SDValue(N, 0), NonceMask,
20080 /*Depth*/ 1, /*HasPSHUFB*/ false, DAG,
20082 return SDValue(); // This routine will use CombineTo to replace N.
20088 /// PerformTruncateCombine - Converts truncate operation to
20089 /// a sequence of vector shuffle operations.
20090 /// It is possible when we truncate 256-bit vector to 128-bit vector
20091 static SDValue PerformTruncateCombine(SDNode *N, SelectionDAG &DAG,
20092 TargetLowering::DAGCombinerInfo &DCI,
20093 const X86Subtarget *Subtarget) {
20097 /// XFormVExtractWithShuffleIntoLoad - Check if a vector extract from a target
20098 /// specific shuffle of a load can be folded into a single element load.
20099 /// Similar handling for VECTOR_SHUFFLE is performed by DAGCombiner, but
20100 /// shuffles have been customed lowered so we need to handle those here.
20101 static SDValue XFormVExtractWithShuffleIntoLoad(SDNode *N, SelectionDAG &DAG,
20102 TargetLowering::DAGCombinerInfo &DCI) {
20103 if (DCI.isBeforeLegalizeOps())
20106 SDValue InVec = N->getOperand(0);
20107 SDValue EltNo = N->getOperand(1);
20109 if (!isa<ConstantSDNode>(EltNo))
20112 EVT VT = InVec.getValueType();
20114 bool HasShuffleIntoBitcast = false;
20115 if (InVec.getOpcode() == ISD::BITCAST) {
20116 // Don't duplicate a load with other uses.
20117 if (!InVec.hasOneUse())
20119 EVT BCVT = InVec.getOperand(0).getValueType();
20120 if (BCVT.getVectorNumElements() != VT.getVectorNumElements())
20122 InVec = InVec.getOperand(0);
20123 HasShuffleIntoBitcast = true;
20126 if (!isTargetShuffle(InVec.getOpcode()))
20129 // Don't duplicate a load with other uses.
20130 if (!InVec.hasOneUse())
20133 SmallVector<int, 16> ShuffleMask;
20135 if (!getTargetShuffleMask(InVec.getNode(), VT.getSimpleVT(), ShuffleMask,
20139 // Select the input vector, guarding against out of range extract vector.
20140 unsigned NumElems = VT.getVectorNumElements();
20141 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
20142 int Idx = (Elt > (int)NumElems) ? -1 : ShuffleMask[Elt];
20143 SDValue LdNode = (Idx < (int)NumElems) ? InVec.getOperand(0)
20144 : InVec.getOperand(1);
20146 // If inputs to shuffle are the same for both ops, then allow 2 uses
20147 unsigned AllowedUses = InVec.getOperand(0) == InVec.getOperand(1) ? 2 : 1;
20149 if (LdNode.getOpcode() == ISD::BITCAST) {
20150 // Don't duplicate a load with other uses.
20151 if (!LdNode.getNode()->hasNUsesOfValue(AllowedUses, 0))
20154 AllowedUses = 1; // only allow 1 load use if we have a bitcast
20155 LdNode = LdNode.getOperand(0);
20158 if (!ISD::isNormalLoad(LdNode.getNode()))
20161 LoadSDNode *LN0 = cast<LoadSDNode>(LdNode);
20163 if (!LN0 ||!LN0->hasNUsesOfValue(AllowedUses, 0) || LN0->isVolatile())
20166 if (HasShuffleIntoBitcast) {
20167 // If there's a bitcast before the shuffle, check if the load type and
20168 // alignment is valid.
20169 unsigned Align = LN0->getAlignment();
20170 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
20171 unsigned NewAlign = TLI.getDataLayout()->
20172 getABITypeAlignment(VT.getTypeForEVT(*DAG.getContext()));
20174 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, VT))
20178 // All checks match so transform back to vector_shuffle so that DAG combiner
20179 // can finish the job
20182 // Create shuffle node taking into account the case that its a unary shuffle
20183 SDValue Shuffle = (UnaryShuffle) ? DAG.getUNDEF(VT) : InVec.getOperand(1);
20184 Shuffle = DAG.getVectorShuffle(InVec.getValueType(), dl,
20185 InVec.getOperand(0), Shuffle,
20187 Shuffle = DAG.getNode(ISD::BITCAST, dl, VT, Shuffle);
20188 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, N->getValueType(0), Shuffle,
20192 /// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index
20193 /// generation and convert it from being a bunch of shuffles and extracts
20194 /// to a simple store and scalar loads to extract the elements.
20195 static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG,
20196 TargetLowering::DAGCombinerInfo &DCI) {
20197 SDValue NewOp = XFormVExtractWithShuffleIntoLoad(N, DAG, DCI);
20198 if (NewOp.getNode())
20201 SDValue InputVector = N->getOperand(0);
20203 // Detect whether we are trying to convert from mmx to i32 and the bitcast
20204 // from mmx to v2i32 has a single usage.
20205 if (InputVector.getNode()->getOpcode() == llvm::ISD::BITCAST &&
20206 InputVector.getNode()->getOperand(0).getValueType() == MVT::x86mmx &&
20207 InputVector.hasOneUse() && N->getValueType(0) == MVT::i32)
20208 return DAG.getNode(X86ISD::MMX_MOVD2W, SDLoc(InputVector),
20209 N->getValueType(0),
20210 InputVector.getNode()->getOperand(0));
20212 // Only operate on vectors of 4 elements, where the alternative shuffling
20213 // gets to be more expensive.
20214 if (InputVector.getValueType() != MVT::v4i32)
20217 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a
20218 // single use which is a sign-extend or zero-extend, and all elements are
20220 SmallVector<SDNode *, 4> Uses;
20221 unsigned ExtractedElements = 0;
20222 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(),
20223 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) {
20224 if (UI.getUse().getResNo() != InputVector.getResNo())
20227 SDNode *Extract = *UI;
20228 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
20231 if (Extract->getValueType(0) != MVT::i32)
20233 if (!Extract->hasOneUse())
20235 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND &&
20236 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND)
20238 if (!isa<ConstantSDNode>(Extract->getOperand(1)))
20241 // Record which element was extracted.
20242 ExtractedElements |=
20243 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue();
20245 Uses.push_back(Extract);
20248 // If not all the elements were used, this may not be worthwhile.
20249 if (ExtractedElements != 15)
20252 // Ok, we've now decided to do the transformation.
20253 SDLoc dl(InputVector);
20255 // Store the value to a temporary stack slot.
20256 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType());
20257 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr,
20258 MachinePointerInfo(), false, false, 0);
20260 // Replace each use (extract) with a load of the appropriate element.
20261 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(),
20262 UE = Uses.end(); UI != UE; ++UI) {
20263 SDNode *Extract = *UI;
20265 // cOMpute the element's address.
20266 SDValue Idx = Extract->getOperand(1);
20268 InputVector.getValueType().getVectorElementType().getSizeInBits()/8;
20269 uint64_t Offset = EltSize * cast<ConstantSDNode>(Idx)->getZExtValue();
20270 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
20271 SDValue OffsetVal = DAG.getConstant(Offset, TLI.getPointerTy());
20273 SDValue ScalarAddr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(),
20274 StackPtr, OffsetVal);
20276 // Load the scalar.
20277 SDValue LoadScalar = DAG.getLoad(Extract->getValueType(0), dl, Ch,
20278 ScalarAddr, MachinePointerInfo(),
20279 false, false, false, 0);
20281 // Replace the exact with the load.
20282 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), LoadScalar);
20285 // The replacement was made in place; don't return anything.
20289 /// \brief Matches a VSELECT onto min/max or return 0 if the node doesn't match.
20290 static std::pair<unsigned, bool>
20291 matchIntegerMINMAX(SDValue Cond, EVT VT, SDValue LHS, SDValue RHS,
20292 SelectionDAG &DAG, const X86Subtarget *Subtarget) {
20293 if (!VT.isVector())
20294 return std::make_pair(0, false);
20296 bool NeedSplit = false;
20297 switch (VT.getSimpleVT().SimpleTy) {
20298 default: return std::make_pair(0, false);
20302 if (!Subtarget->hasAVX2())
20304 if (!Subtarget->hasAVX())
20305 return std::make_pair(0, false);
20310 if (!Subtarget->hasSSE2())
20311 return std::make_pair(0, false);
20314 // SSE2 has only a small subset of the operations.
20315 bool hasUnsigned = Subtarget->hasSSE41() ||
20316 (Subtarget->hasSSE2() && VT == MVT::v16i8);
20317 bool hasSigned = Subtarget->hasSSE41() ||
20318 (Subtarget->hasSSE2() && VT == MVT::v8i16);
20320 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
20323 // Check for x CC y ? x : y.
20324 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
20325 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
20330 Opc = hasUnsigned ? X86ISD::UMIN : 0; break;
20333 Opc = hasUnsigned ? X86ISD::UMAX : 0; break;
20336 Opc = hasSigned ? X86ISD::SMIN : 0; break;
20339 Opc = hasSigned ? X86ISD::SMAX : 0; break;
20341 // Check for x CC y ? y : x -- a min/max with reversed arms.
20342 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
20343 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
20348 Opc = hasUnsigned ? X86ISD::UMAX : 0; break;
20351 Opc = hasUnsigned ? X86ISD::UMIN : 0; break;
20354 Opc = hasSigned ? X86ISD::SMAX : 0; break;
20357 Opc = hasSigned ? X86ISD::SMIN : 0; break;
20361 return std::make_pair(Opc, NeedSplit);
20365 TransformVSELECTtoBlendVECTOR_SHUFFLE(SDNode *N, SelectionDAG &DAG,
20366 const X86Subtarget *Subtarget) {
20368 SDValue Cond = N->getOperand(0);
20369 SDValue LHS = N->getOperand(1);
20370 SDValue RHS = N->getOperand(2);
20372 if (Cond.getOpcode() == ISD::SIGN_EXTEND) {
20373 SDValue CondSrc = Cond->getOperand(0);
20374 if (CondSrc->getOpcode() == ISD::SIGN_EXTEND_INREG)
20375 Cond = CondSrc->getOperand(0);
20378 MVT VT = N->getSimpleValueType(0);
20379 MVT EltVT = VT.getVectorElementType();
20380 unsigned NumElems = VT.getVectorNumElements();
20381 // There is no blend with immediate in AVX-512.
20382 if (VT.is512BitVector())
20385 if (!Subtarget->hasSSE41() || EltVT == MVT::i8)
20387 if (!Subtarget->hasInt256() && VT == MVT::v16i16)
20390 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
20393 unsigned MaskValue = 0;
20394 if (!BUILD_VECTORtoBlendMask(cast<BuildVectorSDNode>(Cond), MaskValue))
20397 SmallVector<int, 8> ShuffleMask(NumElems, -1);
20398 for (unsigned i = 0; i < NumElems; ++i) {
20399 // Be sure we emit undef where we can.
20400 if (Cond.getOperand(i)->getOpcode() == ISD::UNDEF)
20401 ShuffleMask[i] = -1;
20403 ShuffleMask[i] = i + NumElems * ((MaskValue >> i) & 1);
20406 return DAG.getVectorShuffle(VT, dl, LHS, RHS, &ShuffleMask[0]);
20409 /// PerformSELECTCombine - Do target-specific dag combines on SELECT and VSELECT
20411 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
20412 TargetLowering::DAGCombinerInfo &DCI,
20413 const X86Subtarget *Subtarget) {
20415 SDValue Cond = N->getOperand(0);
20416 // Get the LHS/RHS of the select.
20417 SDValue LHS = N->getOperand(1);
20418 SDValue RHS = N->getOperand(2);
20419 EVT VT = LHS.getValueType();
20420 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
20422 // If we have SSE[12] support, try to form min/max nodes. SSE min/max
20423 // instructions match the semantics of the common C idiom x<y?x:y but not
20424 // x<=y?x:y, because of how they handle negative zero (which can be
20425 // ignored in unsafe-math mode).
20426 if (Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() &&
20427 VT != MVT::f80 && TLI.isTypeLegal(VT) &&
20428 (Subtarget->hasSSE2() ||
20429 (Subtarget->hasSSE1() && VT.getScalarType() == MVT::f32))) {
20430 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
20432 unsigned Opcode = 0;
20433 // Check for x CC y ? x : y.
20434 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
20435 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
20439 // Converting this to a min would handle NaNs incorrectly, and swapping
20440 // the operands would cause it to handle comparisons between positive
20441 // and negative zero incorrectly.
20442 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
20443 if (!DAG.getTarget().Options.UnsafeFPMath &&
20444 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
20446 std::swap(LHS, RHS);
20448 Opcode = X86ISD::FMIN;
20451 // Converting this to a min would handle comparisons between positive
20452 // and negative zero incorrectly.
20453 if (!DAG.getTarget().Options.UnsafeFPMath &&
20454 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
20456 Opcode = X86ISD::FMIN;
20459 // Converting this to a min would handle both negative zeros and NaNs
20460 // incorrectly, but we can swap the operands to fix both.
20461 std::swap(LHS, RHS);
20465 Opcode = X86ISD::FMIN;
20469 // Converting this to a max would handle comparisons between positive
20470 // and negative zero incorrectly.
20471 if (!DAG.getTarget().Options.UnsafeFPMath &&
20472 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
20474 Opcode = X86ISD::FMAX;
20477 // Converting this to a max would handle NaNs incorrectly, and swapping
20478 // the operands would cause it to handle comparisons between positive
20479 // and negative zero incorrectly.
20480 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
20481 if (!DAG.getTarget().Options.UnsafeFPMath &&
20482 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
20484 std::swap(LHS, RHS);
20486 Opcode = X86ISD::FMAX;
20489 // Converting this to a max would handle both negative zeros and NaNs
20490 // incorrectly, but we can swap the operands to fix both.
20491 std::swap(LHS, RHS);
20495 Opcode = X86ISD::FMAX;
20498 // Check for x CC y ? y : x -- a min/max with reversed arms.
20499 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
20500 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
20504 // Converting this to a min would handle comparisons between positive
20505 // and negative zero incorrectly, and swapping the operands would
20506 // cause it to handle NaNs incorrectly.
20507 if (!DAG.getTarget().Options.UnsafeFPMath &&
20508 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) {
20509 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
20511 std::swap(LHS, RHS);
20513 Opcode = X86ISD::FMIN;
20516 // Converting this to a min would handle NaNs incorrectly.
20517 if (!DAG.getTarget().Options.UnsafeFPMath &&
20518 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
20520 Opcode = X86ISD::FMIN;
20523 // Converting this to a min would handle both negative zeros and NaNs
20524 // incorrectly, but we can swap the operands to fix both.
20525 std::swap(LHS, RHS);
20529 Opcode = X86ISD::FMIN;
20533 // Converting this to a max would handle NaNs incorrectly.
20534 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
20536 Opcode = X86ISD::FMAX;
20539 // Converting this to a max would handle comparisons between positive
20540 // and negative zero incorrectly, and swapping the operands would
20541 // cause it to handle NaNs incorrectly.
20542 if (!DAG.getTarget().Options.UnsafeFPMath &&
20543 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) {
20544 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
20546 std::swap(LHS, RHS);
20548 Opcode = X86ISD::FMAX;
20551 // Converting this to a max would handle both negative zeros and NaNs
20552 // incorrectly, but we can swap the operands to fix both.
20553 std::swap(LHS, RHS);
20557 Opcode = X86ISD::FMAX;
20563 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
20566 EVT CondVT = Cond.getValueType();
20567 if (Subtarget->hasAVX512() && VT.isVector() && CondVT.isVector() &&
20568 CondVT.getVectorElementType() == MVT::i1) {
20569 // v16i8 (select v16i1, v16i8, v16i8) does not have a proper
20570 // lowering on AVX-512. In this case we convert it to
20571 // v16i8 (select v16i8, v16i8, v16i8) and use AVX instruction.
20572 // The same situation for all 128 and 256-bit vectors of i8 and i16
20573 EVT OpVT = LHS.getValueType();
20574 if ((OpVT.is128BitVector() || OpVT.is256BitVector()) &&
20575 (OpVT.getVectorElementType() == MVT::i8 ||
20576 OpVT.getVectorElementType() == MVT::i16)) {
20577 Cond = DAG.getNode(ISD::SIGN_EXTEND, DL, OpVT, Cond);
20578 DCI.AddToWorklist(Cond.getNode());
20579 return DAG.getNode(N->getOpcode(), DL, OpVT, Cond, LHS, RHS);
20582 // If this is a select between two integer constants, try to do some
20584 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
20585 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
20586 // Don't do this for crazy integer types.
20587 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
20588 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
20589 // so that TrueC (the true value) is larger than FalseC.
20590 bool NeedsCondInvert = false;
20592 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
20593 // Efficiently invertible.
20594 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
20595 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
20596 isa<ConstantSDNode>(Cond.getOperand(1))))) {
20597 NeedsCondInvert = true;
20598 std::swap(TrueC, FalseC);
20601 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
20602 if (FalseC->getAPIntValue() == 0 &&
20603 TrueC->getAPIntValue().isPowerOf2()) {
20604 if (NeedsCondInvert) // Invert the condition if needed.
20605 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
20606 DAG.getConstant(1, Cond.getValueType()));
20608 // Zero extend the condition if needed.
20609 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
20611 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
20612 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
20613 DAG.getConstant(ShAmt, MVT::i8));
20616 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
20617 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
20618 if (NeedsCondInvert) // Invert the condition if needed.
20619 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
20620 DAG.getConstant(1, Cond.getValueType()));
20622 // Zero extend the condition if needed.
20623 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
20624 FalseC->getValueType(0), Cond);
20625 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
20626 SDValue(FalseC, 0));
20629 // Optimize cases that will turn into an LEA instruction. This requires
20630 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
20631 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
20632 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
20633 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
20635 bool isFastMultiplier = false;
20637 switch ((unsigned char)Diff) {
20639 case 1: // result = add base, cond
20640 case 2: // result = lea base( , cond*2)
20641 case 3: // result = lea base(cond, cond*2)
20642 case 4: // result = lea base( , cond*4)
20643 case 5: // result = lea base(cond, cond*4)
20644 case 8: // result = lea base( , cond*8)
20645 case 9: // result = lea base(cond, cond*8)
20646 isFastMultiplier = true;
20651 if (isFastMultiplier) {
20652 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
20653 if (NeedsCondInvert) // Invert the condition if needed.
20654 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
20655 DAG.getConstant(1, Cond.getValueType()));
20657 // Zero extend the condition if needed.
20658 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
20660 // Scale the condition by the difference.
20662 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
20663 DAG.getConstant(Diff, Cond.getValueType()));
20665 // Add the base if non-zero.
20666 if (FalseC->getAPIntValue() != 0)
20667 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
20668 SDValue(FalseC, 0));
20675 // Canonicalize max and min:
20676 // (x > y) ? x : y -> (x >= y) ? x : y
20677 // (x < y) ? x : y -> (x <= y) ? x : y
20678 // This allows use of COND_S / COND_NS (see TranslateX86CC) which eliminates
20679 // the need for an extra compare
20680 // against zero. e.g.
20681 // (x - y) > 0 : (x - y) ? 0 -> (x - y) >= 0 : (x - y) ? 0
20683 // testl %edi, %edi
20685 // cmovgl %edi, %eax
20689 // cmovsl %eax, %edi
20690 if (N->getOpcode() == ISD::SELECT && Cond.getOpcode() == ISD::SETCC &&
20691 DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
20692 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
20693 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
20698 ISD::CondCode NewCC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGE;
20699 Cond = DAG.getSetCC(SDLoc(Cond), Cond.getValueType(),
20700 Cond.getOperand(0), Cond.getOperand(1), NewCC);
20701 return DAG.getNode(ISD::SELECT, DL, VT, Cond, LHS, RHS);
20706 // Early exit check
20707 if (!TLI.isTypeLegal(VT))
20710 // Match VSELECTs into subs with unsigned saturation.
20711 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC &&
20712 // psubus is available in SSE2 and AVX2 for i8 and i16 vectors.
20713 ((Subtarget->hasSSE2() && (VT == MVT::v16i8 || VT == MVT::v8i16)) ||
20714 (Subtarget->hasAVX2() && (VT == MVT::v32i8 || VT == MVT::v16i16)))) {
20715 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
20717 // Check if one of the arms of the VSELECT is a zero vector. If it's on the
20718 // left side invert the predicate to simplify logic below.
20720 if (ISD::isBuildVectorAllZeros(LHS.getNode())) {
20722 CC = ISD::getSetCCInverse(CC, true);
20723 } else if (ISD::isBuildVectorAllZeros(RHS.getNode())) {
20727 if (Other.getNode() && Other->getNumOperands() == 2 &&
20728 DAG.isEqualTo(Other->getOperand(0), Cond.getOperand(0))) {
20729 SDValue OpLHS = Other->getOperand(0), OpRHS = Other->getOperand(1);
20730 SDValue CondRHS = Cond->getOperand(1);
20732 // Look for a general sub with unsigned saturation first.
20733 // x >= y ? x-y : 0 --> subus x, y
20734 // x > y ? x-y : 0 --> subus x, y
20735 if ((CC == ISD::SETUGE || CC == ISD::SETUGT) &&
20736 Other->getOpcode() == ISD::SUB && DAG.isEqualTo(OpRHS, CondRHS))
20737 return DAG.getNode(X86ISD::SUBUS, DL, VT, OpLHS, OpRHS);
20739 if (auto *OpRHSBV = dyn_cast<BuildVectorSDNode>(OpRHS))
20740 if (auto *OpRHSConst = OpRHSBV->getConstantSplatNode()) {
20741 if (auto *CondRHSBV = dyn_cast<BuildVectorSDNode>(CondRHS))
20742 if (auto *CondRHSConst = CondRHSBV->getConstantSplatNode())
20743 // If the RHS is a constant we have to reverse the const
20744 // canonicalization.
20745 // x > C-1 ? x+-C : 0 --> subus x, C
20746 if (CC == ISD::SETUGT && Other->getOpcode() == ISD::ADD &&
20747 CondRHSConst->getAPIntValue() ==
20748 (-OpRHSConst->getAPIntValue() - 1))
20749 return DAG.getNode(
20750 X86ISD::SUBUS, DL, VT, OpLHS,
20751 DAG.getConstant(-OpRHSConst->getAPIntValue(), VT));
20753 // Another special case: If C was a sign bit, the sub has been
20754 // canonicalized into a xor.
20755 // FIXME: Would it be better to use computeKnownBits to determine
20756 // whether it's safe to decanonicalize the xor?
20757 // x s< 0 ? x^C : 0 --> subus x, C
20758 if (CC == ISD::SETLT && Other->getOpcode() == ISD::XOR &&
20759 ISD::isBuildVectorAllZeros(CondRHS.getNode()) &&
20760 OpRHSConst->getAPIntValue().isSignBit())
20761 // Note that we have to rebuild the RHS constant here to ensure we
20762 // don't rely on particular values of undef lanes.
20763 return DAG.getNode(
20764 X86ISD::SUBUS, DL, VT, OpLHS,
20765 DAG.getConstant(OpRHSConst->getAPIntValue(), VT));
20770 // Try to match a min/max vector operation.
20771 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC) {
20772 std::pair<unsigned, bool> ret = matchIntegerMINMAX(Cond, VT, LHS, RHS, DAG, Subtarget);
20773 unsigned Opc = ret.first;
20774 bool NeedSplit = ret.second;
20776 if (Opc && NeedSplit) {
20777 unsigned NumElems = VT.getVectorNumElements();
20778 // Extract the LHS vectors
20779 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, DL);
20780 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, DL);
20782 // Extract the RHS vectors
20783 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, DL);
20784 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, DL);
20786 // Create min/max for each subvector
20787 LHS = DAG.getNode(Opc, DL, LHS1.getValueType(), LHS1, RHS1);
20788 RHS = DAG.getNode(Opc, DL, LHS2.getValueType(), LHS2, RHS2);
20790 // Merge the result
20791 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LHS, RHS);
20793 return DAG.getNode(Opc, DL, VT, LHS, RHS);
20796 // Simplify vector selection if the selector will be produced by CMPP*/PCMP*.
20797 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC &&
20798 // Check if SETCC has already been promoted
20799 TLI.getSetCCResultType(*DAG.getContext(), VT) == CondVT &&
20800 // Check that condition value type matches vselect operand type
20803 assert(Cond.getValueType().isVector() &&
20804 "vector select expects a vector selector!");
20806 bool TValIsAllOnes = ISD::isBuildVectorAllOnes(LHS.getNode());
20807 bool FValIsAllZeros = ISD::isBuildVectorAllZeros(RHS.getNode());
20809 if (!TValIsAllOnes && !FValIsAllZeros) {
20810 // Try invert the condition if true value is not all 1s and false value
20812 bool TValIsAllZeros = ISD::isBuildVectorAllZeros(LHS.getNode());
20813 bool FValIsAllOnes = ISD::isBuildVectorAllOnes(RHS.getNode());
20815 if (TValIsAllZeros || FValIsAllOnes) {
20816 SDValue CC = Cond.getOperand(2);
20817 ISD::CondCode NewCC =
20818 ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
20819 Cond.getOperand(0).getValueType().isInteger());
20820 Cond = DAG.getSetCC(DL, CondVT, Cond.getOperand(0), Cond.getOperand(1), NewCC);
20821 std::swap(LHS, RHS);
20822 TValIsAllOnes = FValIsAllOnes;
20823 FValIsAllZeros = TValIsAllZeros;
20827 if (TValIsAllOnes || FValIsAllZeros) {
20830 if (TValIsAllOnes && FValIsAllZeros)
20832 else if (TValIsAllOnes)
20833 Ret = DAG.getNode(ISD::OR, DL, CondVT, Cond,
20834 DAG.getNode(ISD::BITCAST, DL, CondVT, RHS));
20835 else if (FValIsAllZeros)
20836 Ret = DAG.getNode(ISD::AND, DL, CondVT, Cond,
20837 DAG.getNode(ISD::BITCAST, DL, CondVT, LHS));
20839 return DAG.getNode(ISD::BITCAST, DL, VT, Ret);
20843 // Try to fold this VSELECT into a MOVSS/MOVSD
20844 if (N->getOpcode() == ISD::VSELECT &&
20845 Cond.getOpcode() == ISD::BUILD_VECTOR && !DCI.isBeforeLegalize()) {
20846 if (VT == MVT::v4i32 || VT == MVT::v4f32 ||
20847 (Subtarget->hasSSE2() && (VT == MVT::v2i64 || VT == MVT::v2f64))) {
20848 bool CanFold = false;
20849 unsigned NumElems = Cond.getNumOperands();
20853 if (isZero(Cond.getOperand(0))) {
20856 // fold (vselect <0,-1,-1,-1>, A, B) -> (movss A, B)
20857 // fold (vselect <0,-1> -> (movsd A, B)
20858 for (unsigned i = 1, e = NumElems; i != e && CanFold; ++i)
20859 CanFold = isAllOnes(Cond.getOperand(i));
20860 } else if (isAllOnes(Cond.getOperand(0))) {
20864 // fold (vselect <-1,0,0,0>, A, B) -> (movss B, A)
20865 // fold (vselect <-1,0> -> (movsd B, A)
20866 for (unsigned i = 1, e = NumElems; i != e && CanFold; ++i)
20867 CanFold = isZero(Cond.getOperand(i));
20871 if (VT == MVT::v4i32 || VT == MVT::v4f32)
20872 return getTargetShuffleNode(X86ISD::MOVSS, DL, VT, A, B, DAG);
20873 return getTargetShuffleNode(X86ISD::MOVSD, DL, VT, A, B, DAG);
20876 if (Subtarget->hasSSE2() && (VT == MVT::v4i32 || VT == MVT::v4f32)) {
20877 // fold (v4i32: vselect <0,0,-1,-1>, A, B) ->
20878 // (v4i32 (bitcast (movsd (v2i64 (bitcast A)),
20879 // (v2i64 (bitcast B)))))
20881 // fold (v4f32: vselect <0,0,-1,-1>, A, B) ->
20882 // (v4f32 (bitcast (movsd (v2f64 (bitcast A)),
20883 // (v2f64 (bitcast B)))))
20885 // fold (v4i32: vselect <-1,-1,0,0>, A, B) ->
20886 // (v4i32 (bitcast (movsd (v2i64 (bitcast B)),
20887 // (v2i64 (bitcast A)))))
20889 // fold (v4f32: vselect <-1,-1,0,0>, A, B) ->
20890 // (v4f32 (bitcast (movsd (v2f64 (bitcast B)),
20891 // (v2f64 (bitcast A)))))
20893 CanFold = (isZero(Cond.getOperand(0)) &&
20894 isZero(Cond.getOperand(1)) &&
20895 isAllOnes(Cond.getOperand(2)) &&
20896 isAllOnes(Cond.getOperand(3)));
20898 if (!CanFold && isAllOnes(Cond.getOperand(0)) &&
20899 isAllOnes(Cond.getOperand(1)) &&
20900 isZero(Cond.getOperand(2)) &&
20901 isZero(Cond.getOperand(3))) {
20903 std::swap(LHS, RHS);
20907 EVT NVT = (VT == MVT::v4i32) ? MVT::v2i64 : MVT::v2f64;
20908 SDValue NewA = DAG.getNode(ISD::BITCAST, DL, NVT, LHS);
20909 SDValue NewB = DAG.getNode(ISD::BITCAST, DL, NVT, RHS);
20910 SDValue Select = getTargetShuffleNode(X86ISD::MOVSD, DL, NVT, NewA,
20912 return DAG.getNode(ISD::BITCAST, DL, VT, Select);
20918 // If we know that this node is legal then we know that it is going to be
20919 // matched by one of the SSE/AVX BLEND instructions. These instructions only
20920 // depend on the highest bit in each word. Try to use SimplifyDemandedBits
20921 // to simplify previous instructions.
20922 if (N->getOpcode() == ISD::VSELECT && DCI.isBeforeLegalizeOps() &&
20923 !DCI.isBeforeLegalize() &&
20924 // We explicitly check against v8i16 and v16i16 because, although
20925 // they're marked as Custom, they might only be legal when Cond is a
20926 // build_vector of constants. This will be taken care in a later
20928 (TLI.isOperationLegalOrCustom(ISD::VSELECT, VT) && VT != MVT::v16i16 &&
20929 VT != MVT::v8i16)) {
20930 unsigned BitWidth = Cond.getValueType().getScalarType().getSizeInBits();
20932 // Don't optimize vector selects that map to mask-registers.
20936 // Check all uses of that condition operand to check whether it will be
20937 // consumed by non-BLEND instructions, which may depend on all bits are set
20939 for (SDNode::use_iterator I = Cond->use_begin(),
20940 E = Cond->use_end(); I != E; ++I)
20941 if (I->getOpcode() != ISD::VSELECT)
20942 // TODO: Add other opcodes eventually lowered into BLEND.
20945 assert(BitWidth >= 8 && BitWidth <= 64 && "Invalid mask size");
20946 APInt DemandedMask = APInt::getHighBitsSet(BitWidth, 1);
20948 APInt KnownZero, KnownOne;
20949 TargetLowering::TargetLoweringOpt TLO(DAG, DCI.isBeforeLegalize(),
20950 DCI.isBeforeLegalizeOps());
20951 if (TLO.ShrinkDemandedConstant(Cond, DemandedMask) ||
20952 TLI.SimplifyDemandedBits(Cond, DemandedMask, KnownZero, KnownOne, TLO))
20953 DCI.CommitTargetLoweringOpt(TLO);
20956 // We should generate an X86ISD::BLENDI from a vselect if its argument
20957 // is a sign_extend_inreg of an any_extend of a BUILD_VECTOR of
20958 // constants. This specific pattern gets generated when we split a
20959 // selector for a 512 bit vector in a machine without AVX512 (but with
20960 // 256-bit vectors), during legalization:
20962 // (vselect (sign_extend (any_extend (BUILD_VECTOR)) i1) LHS RHS)
20964 // Iff we find this pattern and the build_vectors are built from
20965 // constants, we translate the vselect into a shuffle_vector that we
20966 // know will be matched by LowerVECTOR_SHUFFLEtoBlend.
20967 if (N->getOpcode() == ISD::VSELECT && !DCI.isBeforeLegalize()) {
20968 SDValue Shuffle = TransformVSELECTtoBlendVECTOR_SHUFFLE(N, DAG, Subtarget);
20969 if (Shuffle.getNode())
20976 // Check whether a boolean test is testing a boolean value generated by
20977 // X86ISD::SETCC. If so, return the operand of that SETCC and proper condition
20980 // Simplify the following patterns:
20981 // (Op (CMP (SETCC Cond EFLAGS) 1) EQ) or
20982 // (Op (CMP (SETCC Cond EFLAGS) 0) NEQ)
20983 // to (Op EFLAGS Cond)
20985 // (Op (CMP (SETCC Cond EFLAGS) 0) EQ) or
20986 // (Op (CMP (SETCC Cond EFLAGS) 1) NEQ)
20987 // to (Op EFLAGS !Cond)
20989 // where Op could be BRCOND or CMOV.
20991 static SDValue checkBoolTestSetCCCombine(SDValue Cmp, X86::CondCode &CC) {
20992 // Quit if not CMP and SUB with its value result used.
20993 if (Cmp.getOpcode() != X86ISD::CMP &&
20994 (Cmp.getOpcode() != X86ISD::SUB || Cmp.getNode()->hasAnyUseOfValue(0)))
20997 // Quit if not used as a boolean value.
20998 if (CC != X86::COND_E && CC != X86::COND_NE)
21001 // Check CMP operands. One of them should be 0 or 1 and the other should be
21002 // an SetCC or extended from it.
21003 SDValue Op1 = Cmp.getOperand(0);
21004 SDValue Op2 = Cmp.getOperand(1);
21007 const ConstantSDNode* C = nullptr;
21008 bool needOppositeCond = (CC == X86::COND_E);
21009 bool checkAgainstTrue = false; // Is it a comparison against 1?
21011 if ((C = dyn_cast<ConstantSDNode>(Op1)))
21013 else if ((C = dyn_cast<ConstantSDNode>(Op2)))
21015 else // Quit if all operands are not constants.
21018 if (C->getZExtValue() == 1) {
21019 needOppositeCond = !needOppositeCond;
21020 checkAgainstTrue = true;
21021 } else if (C->getZExtValue() != 0)
21022 // Quit if the constant is neither 0 or 1.
21025 bool truncatedToBoolWithAnd = false;
21026 // Skip (zext $x), (trunc $x), or (and $x, 1) node.
21027 while (SetCC.getOpcode() == ISD::ZERO_EXTEND ||
21028 SetCC.getOpcode() == ISD::TRUNCATE ||
21029 SetCC.getOpcode() == ISD::AND) {
21030 if (SetCC.getOpcode() == ISD::AND) {
21032 ConstantSDNode *CS;
21033 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(0))) &&
21034 CS->getZExtValue() == 1)
21036 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(1))) &&
21037 CS->getZExtValue() == 1)
21041 SetCC = SetCC.getOperand(OpIdx);
21042 truncatedToBoolWithAnd = true;
21044 SetCC = SetCC.getOperand(0);
21047 switch (SetCC.getOpcode()) {
21048 case X86ISD::SETCC_CARRY:
21049 // Since SETCC_CARRY gives output based on R = CF ? ~0 : 0, it's unsafe to
21050 // simplify it if the result of SETCC_CARRY is not canonicalized to 0 or 1,
21051 // i.e. it's a comparison against true but the result of SETCC_CARRY is not
21052 // truncated to i1 using 'and'.
21053 if (checkAgainstTrue && !truncatedToBoolWithAnd)
21055 assert(X86::CondCode(SetCC.getConstantOperandVal(0)) == X86::COND_B &&
21056 "Invalid use of SETCC_CARRY!");
21058 case X86ISD::SETCC:
21059 // Set the condition code or opposite one if necessary.
21060 CC = X86::CondCode(SetCC.getConstantOperandVal(0));
21061 if (needOppositeCond)
21062 CC = X86::GetOppositeBranchCondition(CC);
21063 return SetCC.getOperand(1);
21064 case X86ISD::CMOV: {
21065 // Check whether false/true value has canonical one, i.e. 0 or 1.
21066 ConstantSDNode *FVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(0));
21067 ConstantSDNode *TVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(1));
21068 // Quit if true value is not a constant.
21071 // Quit if false value is not a constant.
21073 SDValue Op = SetCC.getOperand(0);
21074 // Skip 'zext' or 'trunc' node.
21075 if (Op.getOpcode() == ISD::ZERO_EXTEND ||
21076 Op.getOpcode() == ISD::TRUNCATE)
21077 Op = Op.getOperand(0);
21078 // A special case for rdrand/rdseed, where 0 is set if false cond is
21080 if ((Op.getOpcode() != X86ISD::RDRAND &&
21081 Op.getOpcode() != X86ISD::RDSEED) || Op.getResNo() != 0)
21084 // Quit if false value is not the constant 0 or 1.
21085 bool FValIsFalse = true;
21086 if (FVal && FVal->getZExtValue() != 0) {
21087 if (FVal->getZExtValue() != 1)
21089 // If FVal is 1, opposite cond is needed.
21090 needOppositeCond = !needOppositeCond;
21091 FValIsFalse = false;
21093 // Quit if TVal is not the constant opposite of FVal.
21094 if (FValIsFalse && TVal->getZExtValue() != 1)
21096 if (!FValIsFalse && TVal->getZExtValue() != 0)
21098 CC = X86::CondCode(SetCC.getConstantOperandVal(2));
21099 if (needOppositeCond)
21100 CC = X86::GetOppositeBranchCondition(CC);
21101 return SetCC.getOperand(3);
21108 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
21109 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
21110 TargetLowering::DAGCombinerInfo &DCI,
21111 const X86Subtarget *Subtarget) {
21114 // If the flag operand isn't dead, don't touch this CMOV.
21115 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
21118 SDValue FalseOp = N->getOperand(0);
21119 SDValue TrueOp = N->getOperand(1);
21120 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
21121 SDValue Cond = N->getOperand(3);
21123 if (CC == X86::COND_E || CC == X86::COND_NE) {
21124 switch (Cond.getOpcode()) {
21128 // If operand of BSR / BSF are proven never zero, then ZF cannot be set.
21129 if (DAG.isKnownNeverZero(Cond.getOperand(0)))
21130 return (CC == X86::COND_E) ? FalseOp : TrueOp;
21136 Flags = checkBoolTestSetCCCombine(Cond, CC);
21137 if (Flags.getNode() &&
21138 // Extra check as FCMOV only supports a subset of X86 cond.
21139 (FalseOp.getValueType() != MVT::f80 || hasFPCMov(CC))) {
21140 SDValue Ops[] = { FalseOp, TrueOp,
21141 DAG.getConstant(CC, MVT::i8), Flags };
21142 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), Ops);
21145 // If this is a select between two integer constants, try to do some
21146 // optimizations. Note that the operands are ordered the opposite of SELECT
21148 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(TrueOp)) {
21149 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(FalseOp)) {
21150 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
21151 // larger than FalseC (the false value).
21152 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
21153 CC = X86::GetOppositeBranchCondition(CC);
21154 std::swap(TrueC, FalseC);
21155 std::swap(TrueOp, FalseOp);
21158 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
21159 // This is efficient for any integer data type (including i8/i16) and
21161 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
21162 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
21163 DAG.getConstant(CC, MVT::i8), Cond);
21165 // Zero extend the condition if needed.
21166 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
21168 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
21169 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
21170 DAG.getConstant(ShAmt, MVT::i8));
21171 if (N->getNumValues() == 2) // Dead flag value?
21172 return DCI.CombineTo(N, Cond, SDValue());
21176 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
21177 // for any integer data type, including i8/i16.
21178 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
21179 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
21180 DAG.getConstant(CC, MVT::i8), Cond);
21182 // Zero extend the condition if needed.
21183 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
21184 FalseC->getValueType(0), Cond);
21185 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
21186 SDValue(FalseC, 0));
21188 if (N->getNumValues() == 2) // Dead flag value?
21189 return DCI.CombineTo(N, Cond, SDValue());
21193 // Optimize cases that will turn into an LEA instruction. This requires
21194 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
21195 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
21196 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
21197 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
21199 bool isFastMultiplier = false;
21201 switch ((unsigned char)Diff) {
21203 case 1: // result = add base, cond
21204 case 2: // result = lea base( , cond*2)
21205 case 3: // result = lea base(cond, cond*2)
21206 case 4: // result = lea base( , cond*4)
21207 case 5: // result = lea base(cond, cond*4)
21208 case 8: // result = lea base( , cond*8)
21209 case 9: // result = lea base(cond, cond*8)
21210 isFastMultiplier = true;
21215 if (isFastMultiplier) {
21216 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
21217 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
21218 DAG.getConstant(CC, MVT::i8), Cond);
21219 // Zero extend the condition if needed.
21220 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
21222 // Scale the condition by the difference.
21224 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
21225 DAG.getConstant(Diff, Cond.getValueType()));
21227 // Add the base if non-zero.
21228 if (FalseC->getAPIntValue() != 0)
21229 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
21230 SDValue(FalseC, 0));
21231 if (N->getNumValues() == 2) // Dead flag value?
21232 return DCI.CombineTo(N, Cond, SDValue());
21239 // Handle these cases:
21240 // (select (x != c), e, c) -> select (x != c), e, x),
21241 // (select (x == c), c, e) -> select (x == c), x, e)
21242 // where the c is an integer constant, and the "select" is the combination
21243 // of CMOV and CMP.
21245 // The rationale for this change is that the conditional-move from a constant
21246 // needs two instructions, however, conditional-move from a register needs
21247 // only one instruction.
21249 // CAVEAT: By replacing a constant with a symbolic value, it may obscure
21250 // some instruction-combining opportunities. This opt needs to be
21251 // postponed as late as possible.
21253 if (!DCI.isBeforeLegalize() && !DCI.isBeforeLegalizeOps()) {
21254 // the DCI.xxxx conditions are provided to postpone the optimization as
21255 // late as possible.
21257 ConstantSDNode *CmpAgainst = nullptr;
21258 if ((Cond.getOpcode() == X86ISD::CMP || Cond.getOpcode() == X86ISD::SUB) &&
21259 (CmpAgainst = dyn_cast<ConstantSDNode>(Cond.getOperand(1))) &&
21260 !isa<ConstantSDNode>(Cond.getOperand(0))) {
21262 if (CC == X86::COND_NE &&
21263 CmpAgainst == dyn_cast<ConstantSDNode>(FalseOp)) {
21264 CC = X86::GetOppositeBranchCondition(CC);
21265 std::swap(TrueOp, FalseOp);
21268 if (CC == X86::COND_E &&
21269 CmpAgainst == dyn_cast<ConstantSDNode>(TrueOp)) {
21270 SDValue Ops[] = { FalseOp, Cond.getOperand(0),
21271 DAG.getConstant(CC, MVT::i8), Cond };
21272 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList (), Ops);
21280 static SDValue PerformINTRINSIC_WO_CHAINCombine(SDNode *N, SelectionDAG &DAG,
21281 const X86Subtarget *Subtarget) {
21282 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
21284 default: return SDValue();
21285 // SSE/AVX/AVX2 blend intrinsics.
21286 case Intrinsic::x86_avx2_pblendvb:
21287 case Intrinsic::x86_avx2_pblendw:
21288 case Intrinsic::x86_avx2_pblendd_128:
21289 case Intrinsic::x86_avx2_pblendd_256:
21290 // Don't try to simplify this intrinsic if we don't have AVX2.
21291 if (!Subtarget->hasAVX2())
21294 case Intrinsic::x86_avx_blend_pd_256:
21295 case Intrinsic::x86_avx_blend_ps_256:
21296 case Intrinsic::x86_avx_blendv_pd_256:
21297 case Intrinsic::x86_avx_blendv_ps_256:
21298 // Don't try to simplify this intrinsic if we don't have AVX.
21299 if (!Subtarget->hasAVX())
21302 case Intrinsic::x86_sse41_pblendw:
21303 case Intrinsic::x86_sse41_blendpd:
21304 case Intrinsic::x86_sse41_blendps:
21305 case Intrinsic::x86_sse41_blendvps:
21306 case Intrinsic::x86_sse41_blendvpd:
21307 case Intrinsic::x86_sse41_pblendvb: {
21308 SDValue Op0 = N->getOperand(1);
21309 SDValue Op1 = N->getOperand(2);
21310 SDValue Mask = N->getOperand(3);
21312 // Don't try to simplify this intrinsic if we don't have SSE4.1.
21313 if (!Subtarget->hasSSE41())
21316 // fold (blend A, A, Mask) -> A
21319 // fold (blend A, B, allZeros) -> A
21320 if (ISD::isBuildVectorAllZeros(Mask.getNode()))
21322 // fold (blend A, B, allOnes) -> B
21323 if (ISD::isBuildVectorAllOnes(Mask.getNode()))
21326 // Simplify the case where the mask is a constant i32 value.
21327 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Mask)) {
21328 if (C->isNullValue())
21330 if (C->isAllOnesValue())
21337 // Packed SSE2/AVX2 arithmetic shift immediate intrinsics.
21338 case Intrinsic::x86_sse2_psrai_w:
21339 case Intrinsic::x86_sse2_psrai_d:
21340 case Intrinsic::x86_avx2_psrai_w:
21341 case Intrinsic::x86_avx2_psrai_d:
21342 case Intrinsic::x86_sse2_psra_w:
21343 case Intrinsic::x86_sse2_psra_d:
21344 case Intrinsic::x86_avx2_psra_w:
21345 case Intrinsic::x86_avx2_psra_d: {
21346 SDValue Op0 = N->getOperand(1);
21347 SDValue Op1 = N->getOperand(2);
21348 EVT VT = Op0.getValueType();
21349 assert(VT.isVector() && "Expected a vector type!");
21351 if (isa<BuildVectorSDNode>(Op1))
21352 Op1 = Op1.getOperand(0);
21354 if (!isa<ConstantSDNode>(Op1))
21357 EVT SVT = VT.getVectorElementType();
21358 unsigned SVTBits = SVT.getSizeInBits();
21360 ConstantSDNode *CND = cast<ConstantSDNode>(Op1);
21361 const APInt &C = APInt(SVTBits, CND->getAPIntValue().getZExtValue());
21362 uint64_t ShAmt = C.getZExtValue();
21364 // Don't try to convert this shift into a ISD::SRA if the shift
21365 // count is bigger than or equal to the element size.
21366 if (ShAmt >= SVTBits)
21369 // Trivial case: if the shift count is zero, then fold this
21370 // into the first operand.
21374 // Replace this packed shift intrinsic with a target independent
21376 SDValue Splat = DAG.getConstant(C, VT);
21377 return DAG.getNode(ISD::SRA, SDLoc(N), VT, Op0, Splat);
21382 /// PerformMulCombine - Optimize a single multiply with constant into two
21383 /// in order to implement it with two cheaper instructions, e.g.
21384 /// LEA + SHL, LEA + LEA.
21385 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
21386 TargetLowering::DAGCombinerInfo &DCI) {
21387 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
21390 EVT VT = N->getValueType(0);
21391 if (VT != MVT::i64)
21394 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
21397 uint64_t MulAmt = C->getZExtValue();
21398 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
21401 uint64_t MulAmt1 = 0;
21402 uint64_t MulAmt2 = 0;
21403 if ((MulAmt % 9) == 0) {
21405 MulAmt2 = MulAmt / 9;
21406 } else if ((MulAmt % 5) == 0) {
21408 MulAmt2 = MulAmt / 5;
21409 } else if ((MulAmt % 3) == 0) {
21411 MulAmt2 = MulAmt / 3;
21414 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
21417 if (isPowerOf2_64(MulAmt2) &&
21418 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
21419 // If second multiplifer is pow2, issue it first. We want the multiply by
21420 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
21422 std::swap(MulAmt1, MulAmt2);
21425 if (isPowerOf2_64(MulAmt1))
21426 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
21427 DAG.getConstant(Log2_64(MulAmt1), MVT::i8));
21429 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
21430 DAG.getConstant(MulAmt1, VT));
21432 if (isPowerOf2_64(MulAmt2))
21433 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
21434 DAG.getConstant(Log2_64(MulAmt2), MVT::i8));
21436 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
21437 DAG.getConstant(MulAmt2, VT));
21439 // Do not add new nodes to DAG combiner worklist.
21440 DCI.CombineTo(N, NewMul, false);
21445 static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) {
21446 SDValue N0 = N->getOperand(0);
21447 SDValue N1 = N->getOperand(1);
21448 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
21449 EVT VT = N0.getValueType();
21451 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2))
21452 // since the result of setcc_c is all zero's or all ones.
21453 if (VT.isInteger() && !VT.isVector() &&
21454 N1C && N0.getOpcode() == ISD::AND &&
21455 N0.getOperand(1).getOpcode() == ISD::Constant) {
21456 SDValue N00 = N0.getOperand(0);
21457 if (N00.getOpcode() == X86ISD::SETCC_CARRY ||
21458 ((N00.getOpcode() == ISD::ANY_EXTEND ||
21459 N00.getOpcode() == ISD::ZERO_EXTEND) &&
21460 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY)) {
21461 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
21462 APInt ShAmt = N1C->getAPIntValue();
21463 Mask = Mask.shl(ShAmt);
21465 return DAG.getNode(ISD::AND, SDLoc(N), VT,
21466 N00, DAG.getConstant(Mask, VT));
21470 // Hardware support for vector shifts is sparse which makes us scalarize the
21471 // vector operations in many cases. Also, on sandybridge ADD is faster than
21473 // (shl V, 1) -> add V,V
21474 if (auto *N1BV = dyn_cast<BuildVectorSDNode>(N1))
21475 if (auto *N1SplatC = N1BV->getConstantSplatNode()) {
21476 assert(N0.getValueType().isVector() && "Invalid vector shift type");
21477 // We shift all of the values by one. In many cases we do not have
21478 // hardware support for this operation. This is better expressed as an ADD
21480 if (N1SplatC->getZExtValue() == 1)
21481 return DAG.getNode(ISD::ADD, SDLoc(N), VT, N0, N0);
21487 /// \brief Returns a vector of 0s if the node in input is a vector logical
21488 /// shift by a constant amount which is known to be bigger than or equal
21489 /// to the vector element size in bits.
21490 static SDValue performShiftToAllZeros(SDNode *N, SelectionDAG &DAG,
21491 const X86Subtarget *Subtarget) {
21492 EVT VT = N->getValueType(0);
21494 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16 &&
21495 (!Subtarget->hasInt256() ||
21496 (VT != MVT::v4i64 && VT != MVT::v8i32 && VT != MVT::v16i16)))
21499 SDValue Amt = N->getOperand(1);
21501 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Amt))
21502 if (auto *AmtSplat = AmtBV->getConstantSplatNode()) {
21503 APInt ShiftAmt = AmtSplat->getAPIntValue();
21504 unsigned MaxAmount = VT.getVectorElementType().getSizeInBits();
21506 // SSE2/AVX2 logical shifts always return a vector of 0s
21507 // if the shift amount is bigger than or equal to
21508 // the element size. The constant shift amount will be
21509 // encoded as a 8-bit immediate.
21510 if (ShiftAmt.trunc(8).uge(MaxAmount))
21511 return getZeroVector(VT, Subtarget, DAG, DL);
21517 /// PerformShiftCombine - Combine shifts.
21518 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
21519 TargetLowering::DAGCombinerInfo &DCI,
21520 const X86Subtarget *Subtarget) {
21521 if (N->getOpcode() == ISD::SHL) {
21522 SDValue V = PerformSHLCombine(N, DAG);
21523 if (V.getNode()) return V;
21526 if (N->getOpcode() != ISD::SRA) {
21527 // Try to fold this logical shift into a zero vector.
21528 SDValue V = performShiftToAllZeros(N, DAG, Subtarget);
21529 if (V.getNode()) return V;
21535 // CMPEQCombine - Recognize the distinctive (AND (setcc ...) (setcc ..))
21536 // where both setccs reference the same FP CMP, and rewrite for CMPEQSS
21537 // and friends. Likewise for OR -> CMPNEQSS.
21538 static SDValue CMPEQCombine(SDNode *N, SelectionDAG &DAG,
21539 TargetLowering::DAGCombinerInfo &DCI,
21540 const X86Subtarget *Subtarget) {
21543 // SSE1 supports CMP{eq|ne}SS, and SSE2 added CMP{eq|ne}SD, but
21544 // we're requiring SSE2 for both.
21545 if (Subtarget->hasSSE2() && isAndOrOfSetCCs(SDValue(N, 0U), opcode)) {
21546 SDValue N0 = N->getOperand(0);
21547 SDValue N1 = N->getOperand(1);
21548 SDValue CMP0 = N0->getOperand(1);
21549 SDValue CMP1 = N1->getOperand(1);
21552 // The SETCCs should both refer to the same CMP.
21553 if (CMP0.getOpcode() != X86ISD::CMP || CMP0 != CMP1)
21556 SDValue CMP00 = CMP0->getOperand(0);
21557 SDValue CMP01 = CMP0->getOperand(1);
21558 EVT VT = CMP00.getValueType();
21560 if (VT == MVT::f32 || VT == MVT::f64) {
21561 bool ExpectingFlags = false;
21562 // Check for any users that want flags:
21563 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
21564 !ExpectingFlags && UI != UE; ++UI)
21565 switch (UI->getOpcode()) {
21570 ExpectingFlags = true;
21572 case ISD::CopyToReg:
21573 case ISD::SIGN_EXTEND:
21574 case ISD::ZERO_EXTEND:
21575 case ISD::ANY_EXTEND:
21579 if (!ExpectingFlags) {
21580 enum X86::CondCode cc0 = (enum X86::CondCode)N0.getConstantOperandVal(0);
21581 enum X86::CondCode cc1 = (enum X86::CondCode)N1.getConstantOperandVal(0);
21583 if (cc1 == X86::COND_E || cc1 == X86::COND_NE) {
21584 X86::CondCode tmp = cc0;
21589 if ((cc0 == X86::COND_E && cc1 == X86::COND_NP) ||
21590 (cc0 == X86::COND_NE && cc1 == X86::COND_P)) {
21591 // FIXME: need symbolic constants for these magic numbers.
21592 // See X86ATTInstPrinter.cpp:printSSECC().
21593 unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4;
21594 if (Subtarget->hasAVX512()) {
21595 SDValue FSetCC = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CMP00,
21596 CMP01, DAG.getConstant(x86cc, MVT::i8));
21597 if (N->getValueType(0) != MVT::i1)
21598 return DAG.getNode(ISD::ZERO_EXTEND, DL, N->getValueType(0),
21602 SDValue OnesOrZeroesF = DAG.getNode(X86ISD::FSETCC, DL,
21603 CMP00.getValueType(), CMP00, CMP01,
21604 DAG.getConstant(x86cc, MVT::i8));
21606 bool is64BitFP = (CMP00.getValueType() == MVT::f64);
21607 MVT IntVT = is64BitFP ? MVT::i64 : MVT::i32;
21609 if (is64BitFP && !Subtarget->is64Bit()) {
21610 // On a 32-bit target, we cannot bitcast the 64-bit float to a
21611 // 64-bit integer, since that's not a legal type. Since
21612 // OnesOrZeroesF is all ones of all zeroes, we don't need all the
21613 // bits, but can do this little dance to extract the lowest 32 bits
21614 // and work with those going forward.
21615 SDValue Vector64 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2f64,
21617 SDValue Vector32 = DAG.getNode(ISD::BITCAST, DL, MVT::v4f32,
21619 OnesOrZeroesF = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32,
21620 Vector32, DAG.getIntPtrConstant(0));
21624 SDValue OnesOrZeroesI = DAG.getNode(ISD::BITCAST, DL, IntVT, OnesOrZeroesF);
21625 SDValue ANDed = DAG.getNode(ISD::AND, DL, IntVT, OnesOrZeroesI,
21626 DAG.getConstant(1, IntVT));
21627 SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8, ANDed);
21628 return OneBitOfTruth;
21636 /// CanFoldXORWithAllOnes - Test whether the XOR operand is a AllOnes vector
21637 /// so it can be folded inside ANDNP.
21638 static bool CanFoldXORWithAllOnes(const SDNode *N) {
21639 EVT VT = N->getValueType(0);
21641 // Match direct AllOnes for 128 and 256-bit vectors
21642 if (ISD::isBuildVectorAllOnes(N))
21645 // Look through a bit convert.
21646 if (N->getOpcode() == ISD::BITCAST)
21647 N = N->getOperand(0).getNode();
21649 // Sometimes the operand may come from a insert_subvector building a 256-bit
21651 if (VT.is256BitVector() &&
21652 N->getOpcode() == ISD::INSERT_SUBVECTOR) {
21653 SDValue V1 = N->getOperand(0);
21654 SDValue V2 = N->getOperand(1);
21656 if (V1.getOpcode() == ISD::INSERT_SUBVECTOR &&
21657 V1.getOperand(0).getOpcode() == ISD::UNDEF &&
21658 ISD::isBuildVectorAllOnes(V1.getOperand(1).getNode()) &&
21659 ISD::isBuildVectorAllOnes(V2.getNode()))
21666 // On AVX/AVX2 the type v8i1 is legalized to v8i16, which is an XMM sized
21667 // register. In most cases we actually compare or select YMM-sized registers
21668 // and mixing the two types creates horrible code. This method optimizes
21669 // some of the transition sequences.
21670 static SDValue WidenMaskArithmetic(SDNode *N, SelectionDAG &DAG,
21671 TargetLowering::DAGCombinerInfo &DCI,
21672 const X86Subtarget *Subtarget) {
21673 EVT VT = N->getValueType(0);
21674 if (!VT.is256BitVector())
21677 assert((N->getOpcode() == ISD::ANY_EXTEND ||
21678 N->getOpcode() == ISD::ZERO_EXTEND ||
21679 N->getOpcode() == ISD::SIGN_EXTEND) && "Invalid Node");
21681 SDValue Narrow = N->getOperand(0);
21682 EVT NarrowVT = Narrow->getValueType(0);
21683 if (!NarrowVT.is128BitVector())
21686 if (Narrow->getOpcode() != ISD::XOR &&
21687 Narrow->getOpcode() != ISD::AND &&
21688 Narrow->getOpcode() != ISD::OR)
21691 SDValue N0 = Narrow->getOperand(0);
21692 SDValue N1 = Narrow->getOperand(1);
21695 // The Left side has to be a trunc.
21696 if (N0.getOpcode() != ISD::TRUNCATE)
21699 // The type of the truncated inputs.
21700 EVT WideVT = N0->getOperand(0)->getValueType(0);
21704 // The right side has to be a 'trunc' or a constant vector.
21705 bool RHSTrunc = N1.getOpcode() == ISD::TRUNCATE;
21706 ConstantSDNode *RHSConstSplat = nullptr;
21707 if (auto *RHSBV = dyn_cast<BuildVectorSDNode>(N1))
21708 RHSConstSplat = RHSBV->getConstantSplatNode();
21709 if (!RHSTrunc && !RHSConstSplat)
21712 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
21714 if (!TLI.isOperationLegalOrPromote(Narrow->getOpcode(), WideVT))
21717 // Set N0 and N1 to hold the inputs to the new wide operation.
21718 N0 = N0->getOperand(0);
21719 if (RHSConstSplat) {
21720 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, WideVT.getScalarType(),
21721 SDValue(RHSConstSplat, 0));
21722 SmallVector<SDValue, 8> C(WideVT.getVectorNumElements(), N1);
21723 N1 = DAG.getNode(ISD::BUILD_VECTOR, DL, WideVT, C);
21724 } else if (RHSTrunc) {
21725 N1 = N1->getOperand(0);
21728 // Generate the wide operation.
21729 SDValue Op = DAG.getNode(Narrow->getOpcode(), DL, WideVT, N0, N1);
21730 unsigned Opcode = N->getOpcode();
21732 case ISD::ANY_EXTEND:
21734 case ISD::ZERO_EXTEND: {
21735 unsigned InBits = NarrowVT.getScalarType().getSizeInBits();
21736 APInt Mask = APInt::getAllOnesValue(InBits);
21737 Mask = Mask.zext(VT.getScalarType().getSizeInBits());
21738 return DAG.getNode(ISD::AND, DL, VT,
21739 Op, DAG.getConstant(Mask, VT));
21741 case ISD::SIGN_EXTEND:
21742 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT,
21743 Op, DAG.getValueType(NarrowVT));
21745 llvm_unreachable("Unexpected opcode");
21749 static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG,
21750 TargetLowering::DAGCombinerInfo &DCI,
21751 const X86Subtarget *Subtarget) {
21752 EVT VT = N->getValueType(0);
21753 if (DCI.isBeforeLegalizeOps())
21756 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
21760 // Create BEXTR instructions
21761 // BEXTR is ((X >> imm) & (2**size-1))
21762 if (VT == MVT::i32 || VT == MVT::i64) {
21763 SDValue N0 = N->getOperand(0);
21764 SDValue N1 = N->getOperand(1);
21767 // Check for BEXTR.
21768 if ((Subtarget->hasBMI() || Subtarget->hasTBM()) &&
21769 (N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::SRL)) {
21770 ConstantSDNode *MaskNode = dyn_cast<ConstantSDNode>(N1);
21771 ConstantSDNode *ShiftNode = dyn_cast<ConstantSDNode>(N0.getOperand(1));
21772 if (MaskNode && ShiftNode) {
21773 uint64_t Mask = MaskNode->getZExtValue();
21774 uint64_t Shift = ShiftNode->getZExtValue();
21775 if (isMask_64(Mask)) {
21776 uint64_t MaskSize = CountPopulation_64(Mask);
21777 if (Shift + MaskSize <= VT.getSizeInBits())
21778 return DAG.getNode(X86ISD::BEXTR, DL, VT, N0.getOperand(0),
21779 DAG.getConstant(Shift | (MaskSize << 8), VT));
21787 // Want to form ANDNP nodes:
21788 // 1) In the hopes of then easily combining them with OR and AND nodes
21789 // to form PBLEND/PSIGN.
21790 // 2) To match ANDN packed intrinsics
21791 if (VT != MVT::v2i64 && VT != MVT::v4i64)
21794 SDValue N0 = N->getOperand(0);
21795 SDValue N1 = N->getOperand(1);
21798 // Check LHS for vnot
21799 if (N0.getOpcode() == ISD::XOR &&
21800 //ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode()))
21801 CanFoldXORWithAllOnes(N0.getOperand(1).getNode()))
21802 return DAG.getNode(X86ISD::ANDNP, DL, VT, N0.getOperand(0), N1);
21804 // Check RHS for vnot
21805 if (N1.getOpcode() == ISD::XOR &&
21806 //ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode()))
21807 CanFoldXORWithAllOnes(N1.getOperand(1).getNode()))
21808 return DAG.getNode(X86ISD::ANDNP, DL, VT, N1.getOperand(0), N0);
21813 static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
21814 TargetLowering::DAGCombinerInfo &DCI,
21815 const X86Subtarget *Subtarget) {
21816 if (DCI.isBeforeLegalizeOps())
21819 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
21823 SDValue N0 = N->getOperand(0);
21824 SDValue N1 = N->getOperand(1);
21825 EVT VT = N->getValueType(0);
21827 // look for psign/blend
21828 if (VT == MVT::v2i64 || VT == MVT::v4i64) {
21829 if (!Subtarget->hasSSSE3() ||
21830 (VT == MVT::v4i64 && !Subtarget->hasInt256()))
21833 // Canonicalize pandn to RHS
21834 if (N0.getOpcode() == X86ISD::ANDNP)
21836 // or (and (m, y), (pandn m, x))
21837 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::ANDNP) {
21838 SDValue Mask = N1.getOperand(0);
21839 SDValue X = N1.getOperand(1);
21841 if (N0.getOperand(0) == Mask)
21842 Y = N0.getOperand(1);
21843 if (N0.getOperand(1) == Mask)
21844 Y = N0.getOperand(0);
21846 // Check to see if the mask appeared in both the AND and ANDNP and
21850 // Validate that X, Y, and Mask are BIT_CONVERTS, and see through them.
21851 // Look through mask bitcast.
21852 if (Mask.getOpcode() == ISD::BITCAST)
21853 Mask = Mask.getOperand(0);
21854 if (X.getOpcode() == ISD::BITCAST)
21855 X = X.getOperand(0);
21856 if (Y.getOpcode() == ISD::BITCAST)
21857 Y = Y.getOperand(0);
21859 EVT MaskVT = Mask.getValueType();
21861 // Validate that the Mask operand is a vector sra node.
21862 // FIXME: what to do for bytes, since there is a psignb/pblendvb, but
21863 // there is no psrai.b
21864 unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits();
21865 unsigned SraAmt = ~0;
21866 if (Mask.getOpcode() == ISD::SRA) {
21867 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Mask.getOperand(1)))
21868 if (auto *AmtConst = AmtBV->getConstantSplatNode())
21869 SraAmt = AmtConst->getZExtValue();
21870 } else if (Mask.getOpcode() == X86ISD::VSRAI) {
21871 SDValue SraC = Mask.getOperand(1);
21872 SraAmt = cast<ConstantSDNode>(SraC)->getZExtValue();
21874 if ((SraAmt + 1) != EltBits)
21879 // Now we know we at least have a plendvb with the mask val. See if
21880 // we can form a psignb/w/d.
21881 // psign = x.type == y.type == mask.type && y = sub(0, x);
21882 if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X &&
21883 ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) &&
21884 X.getValueType() == MaskVT && Y.getValueType() == MaskVT) {
21885 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
21886 "Unsupported VT for PSIGN");
21887 Mask = DAG.getNode(X86ISD::PSIGN, DL, MaskVT, X, Mask.getOperand(0));
21888 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
21890 // PBLENDVB only available on SSE 4.1
21891 if (!Subtarget->hasSSE41())
21894 EVT BlendVT = (VT == MVT::v4i64) ? MVT::v32i8 : MVT::v16i8;
21896 X = DAG.getNode(ISD::BITCAST, DL, BlendVT, X);
21897 Y = DAG.getNode(ISD::BITCAST, DL, BlendVT, Y);
21898 Mask = DAG.getNode(ISD::BITCAST, DL, BlendVT, Mask);
21899 Mask = DAG.getNode(ISD::VSELECT, DL, BlendVT, Mask, Y, X);
21900 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
21904 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64)
21907 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
21908 MachineFunction &MF = DAG.getMachineFunction();
21909 bool OptForSize = MF.getFunction()->getAttributes().
21910 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
21912 // SHLD/SHRD instructions have lower register pressure, but on some
21913 // platforms they have higher latency than the equivalent
21914 // series of shifts/or that would otherwise be generated.
21915 // Don't fold (or (x << c) | (y >> (64 - c))) if SHLD/SHRD instructions
21916 // have higher latencies and we are not optimizing for size.
21917 if (!OptForSize && Subtarget->isSHLDSlow())
21920 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
21922 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
21924 if (!N0.hasOneUse() || !N1.hasOneUse())
21927 SDValue ShAmt0 = N0.getOperand(1);
21928 if (ShAmt0.getValueType() != MVT::i8)
21930 SDValue ShAmt1 = N1.getOperand(1);
21931 if (ShAmt1.getValueType() != MVT::i8)
21933 if (ShAmt0.getOpcode() == ISD::TRUNCATE)
21934 ShAmt0 = ShAmt0.getOperand(0);
21935 if (ShAmt1.getOpcode() == ISD::TRUNCATE)
21936 ShAmt1 = ShAmt1.getOperand(0);
21939 unsigned Opc = X86ISD::SHLD;
21940 SDValue Op0 = N0.getOperand(0);
21941 SDValue Op1 = N1.getOperand(0);
21942 if (ShAmt0.getOpcode() == ISD::SUB) {
21943 Opc = X86ISD::SHRD;
21944 std::swap(Op0, Op1);
21945 std::swap(ShAmt0, ShAmt1);
21948 unsigned Bits = VT.getSizeInBits();
21949 if (ShAmt1.getOpcode() == ISD::SUB) {
21950 SDValue Sum = ShAmt1.getOperand(0);
21951 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) {
21952 SDValue ShAmt1Op1 = ShAmt1.getOperand(1);
21953 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE)
21954 ShAmt1Op1 = ShAmt1Op1.getOperand(0);
21955 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0)
21956 return DAG.getNode(Opc, DL, VT,
21958 DAG.getNode(ISD::TRUNCATE, DL,
21961 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) {
21962 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0);
21964 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits)
21965 return DAG.getNode(Opc, DL, VT,
21966 N0.getOperand(0), N1.getOperand(0),
21967 DAG.getNode(ISD::TRUNCATE, DL,
21974 // Generate NEG and CMOV for integer abs.
21975 static SDValue performIntegerAbsCombine(SDNode *N, SelectionDAG &DAG) {
21976 EVT VT = N->getValueType(0);
21978 // Since X86 does not have CMOV for 8-bit integer, we don't convert
21979 // 8-bit integer abs to NEG and CMOV.
21980 if (VT.isInteger() && VT.getSizeInBits() == 8)
21983 SDValue N0 = N->getOperand(0);
21984 SDValue N1 = N->getOperand(1);
21987 // Check pattern of XOR(ADD(X,Y), Y) where Y is SRA(X, size(X)-1)
21988 // and change it to SUB and CMOV.
21989 if (VT.isInteger() && N->getOpcode() == ISD::XOR &&
21990 N0.getOpcode() == ISD::ADD &&
21991 N0.getOperand(1) == N1 &&
21992 N1.getOpcode() == ISD::SRA &&
21993 N1.getOperand(0) == N0.getOperand(0))
21994 if (ConstantSDNode *Y1C = dyn_cast<ConstantSDNode>(N1.getOperand(1)))
21995 if (Y1C->getAPIntValue() == VT.getSizeInBits()-1) {
21996 // Generate SUB & CMOV.
21997 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, DAG.getVTList(VT, MVT::i32),
21998 DAG.getConstant(0, VT), N0.getOperand(0));
22000 SDValue Ops[] = { N0.getOperand(0), Neg,
22001 DAG.getConstant(X86::COND_GE, MVT::i8),
22002 SDValue(Neg.getNode(), 1) };
22003 return DAG.getNode(X86ISD::CMOV, DL, DAG.getVTList(VT, MVT::Glue), Ops);
22008 // PerformXorCombine - Attempts to turn XOR nodes into BLSMSK nodes
22009 static SDValue PerformXorCombine(SDNode *N, SelectionDAG &DAG,
22010 TargetLowering::DAGCombinerInfo &DCI,
22011 const X86Subtarget *Subtarget) {
22012 if (DCI.isBeforeLegalizeOps())
22015 if (Subtarget->hasCMov()) {
22016 SDValue RV = performIntegerAbsCombine(N, DAG);
22024 /// PerformLOADCombine - Do target-specific dag combines on LOAD nodes.
22025 static SDValue PerformLOADCombine(SDNode *N, SelectionDAG &DAG,
22026 TargetLowering::DAGCombinerInfo &DCI,
22027 const X86Subtarget *Subtarget) {
22028 LoadSDNode *Ld = cast<LoadSDNode>(N);
22029 EVT RegVT = Ld->getValueType(0);
22030 EVT MemVT = Ld->getMemoryVT();
22032 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22034 // On Sandybridge unaligned 256bit loads are inefficient.
22035 ISD::LoadExtType Ext = Ld->getExtensionType();
22036 unsigned Alignment = Ld->getAlignment();
22037 bool IsAligned = Alignment == 0 || Alignment >= MemVT.getSizeInBits()/8;
22038 if (RegVT.is256BitVector() && !Subtarget->hasInt256() &&
22039 !DCI.isBeforeLegalizeOps() && !IsAligned && Ext == ISD::NON_EXTLOAD) {
22040 unsigned NumElems = RegVT.getVectorNumElements();
22044 SDValue Ptr = Ld->getBasePtr();
22045 SDValue Increment = DAG.getConstant(16, TLI.getPointerTy());
22047 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
22049 SDValue Load1 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
22050 Ld->getPointerInfo(), Ld->isVolatile(),
22051 Ld->isNonTemporal(), Ld->isInvariant(),
22053 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
22054 SDValue Load2 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
22055 Ld->getPointerInfo(), Ld->isVolatile(),
22056 Ld->isNonTemporal(), Ld->isInvariant(),
22057 std::min(16U, Alignment));
22058 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
22060 Load2.getValue(1));
22062 SDValue NewVec = DAG.getUNDEF(RegVT);
22063 NewVec = Insert128BitVector(NewVec, Load1, 0, DAG, dl);
22064 NewVec = Insert128BitVector(NewVec, Load2, NumElems/2, DAG, dl);
22065 return DCI.CombineTo(N, NewVec, TF, true);
22071 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
22072 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
22073 const X86Subtarget *Subtarget) {
22074 StoreSDNode *St = cast<StoreSDNode>(N);
22075 EVT VT = St->getValue().getValueType();
22076 EVT StVT = St->getMemoryVT();
22078 SDValue StoredVal = St->getOperand(1);
22079 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22081 // If we are saving a concatenation of two XMM registers, perform two stores.
22082 // On Sandy Bridge, 256-bit memory operations are executed by two
22083 // 128-bit ports. However, on Haswell it is better to issue a single 256-bit
22084 // memory operation.
22085 unsigned Alignment = St->getAlignment();
22086 bool IsAligned = Alignment == 0 || Alignment >= VT.getSizeInBits()/8;
22087 if (VT.is256BitVector() && !Subtarget->hasInt256() &&
22088 StVT == VT && !IsAligned) {
22089 unsigned NumElems = VT.getVectorNumElements();
22093 SDValue Value0 = Extract128BitVector(StoredVal, 0, DAG, dl);
22094 SDValue Value1 = Extract128BitVector(StoredVal, NumElems/2, DAG, dl);
22096 SDValue Stride = DAG.getConstant(16, TLI.getPointerTy());
22097 SDValue Ptr0 = St->getBasePtr();
22098 SDValue Ptr1 = DAG.getNode(ISD::ADD, dl, Ptr0.getValueType(), Ptr0, Stride);
22100 SDValue Ch0 = DAG.getStore(St->getChain(), dl, Value0, Ptr0,
22101 St->getPointerInfo(), St->isVolatile(),
22102 St->isNonTemporal(), Alignment);
22103 SDValue Ch1 = DAG.getStore(St->getChain(), dl, Value1, Ptr1,
22104 St->getPointerInfo(), St->isVolatile(),
22105 St->isNonTemporal(),
22106 std::min(16U, Alignment));
22107 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ch0, Ch1);
22110 // Optimize trunc store (of multiple scalars) to shuffle and store.
22111 // First, pack all of the elements in one place. Next, store to memory
22112 // in fewer chunks.
22113 if (St->isTruncatingStore() && VT.isVector()) {
22114 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22115 unsigned NumElems = VT.getVectorNumElements();
22116 assert(StVT != VT && "Cannot truncate to the same type");
22117 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
22118 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
22120 // From, To sizes and ElemCount must be pow of two
22121 if (!isPowerOf2_32(NumElems * FromSz * ToSz)) return SDValue();
22122 // We are going to use the original vector elt for storing.
22123 // Accumulated smaller vector elements must be a multiple of the store size.
22124 if (0 != (NumElems * FromSz) % ToSz) return SDValue();
22126 unsigned SizeRatio = FromSz / ToSz;
22128 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
22130 // Create a type on which we perform the shuffle
22131 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
22132 StVT.getScalarType(), NumElems*SizeRatio);
22134 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
22136 SDValue WideVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, St->getValue());
22137 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
22138 for (unsigned i = 0; i != NumElems; ++i)
22139 ShuffleVec[i] = i * SizeRatio;
22141 // Can't shuffle using an illegal type.
22142 if (!TLI.isTypeLegal(WideVecVT))
22145 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
22146 DAG.getUNDEF(WideVecVT),
22148 // At this point all of the data is stored at the bottom of the
22149 // register. We now need to save it to mem.
22151 // Find the largest store unit
22152 MVT StoreType = MVT::i8;
22153 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
22154 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
22155 MVT Tp = (MVT::SimpleValueType)tp;
22156 if (TLI.isTypeLegal(Tp) && Tp.getSizeInBits() <= NumElems * ToSz)
22160 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
22161 if (TLI.isTypeLegal(MVT::f64) && StoreType.getSizeInBits() < 64 &&
22162 (64 <= NumElems * ToSz))
22163 StoreType = MVT::f64;
22165 // Bitcast the original vector into a vector of store-size units
22166 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(),
22167 StoreType, VT.getSizeInBits()/StoreType.getSizeInBits());
22168 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits());
22169 SDValue ShuffWide = DAG.getNode(ISD::BITCAST, dl, StoreVecVT, Shuff);
22170 SmallVector<SDValue, 8> Chains;
22171 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits()/8,
22172 TLI.getPointerTy());
22173 SDValue Ptr = St->getBasePtr();
22175 // Perform one or more big stores into memory.
22176 for (unsigned i=0, e=(ToSz*NumElems)/StoreType.getSizeInBits(); i!=e; ++i) {
22177 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
22178 StoreType, ShuffWide,
22179 DAG.getIntPtrConstant(i));
22180 SDValue Ch = DAG.getStore(St->getChain(), dl, SubVec, Ptr,
22181 St->getPointerInfo(), St->isVolatile(),
22182 St->isNonTemporal(), St->getAlignment());
22183 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
22184 Chains.push_back(Ch);
22187 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
22190 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
22191 // the FP state in cases where an emms may be missing.
22192 // A preferable solution to the general problem is to figure out the right
22193 // places to insert EMMS. This qualifies as a quick hack.
22195 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
22196 if (VT.getSizeInBits() != 64)
22199 const Function *F = DAG.getMachineFunction().getFunction();
22200 bool NoImplicitFloatOps = F->getAttributes().
22201 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoImplicitFloat);
22202 bool F64IsLegal = !DAG.getTarget().Options.UseSoftFloat && !NoImplicitFloatOps
22203 && Subtarget->hasSSE2();
22204 if ((VT.isVector() ||
22205 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
22206 isa<LoadSDNode>(St->getValue()) &&
22207 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
22208 St->getChain().hasOneUse() && !St->isVolatile()) {
22209 SDNode* LdVal = St->getValue().getNode();
22210 LoadSDNode *Ld = nullptr;
22211 int TokenFactorIndex = -1;
22212 SmallVector<SDValue, 8> Ops;
22213 SDNode* ChainVal = St->getChain().getNode();
22214 // Must be a store of a load. We currently handle two cases: the load
22215 // is a direct child, and it's under an intervening TokenFactor. It is
22216 // possible to dig deeper under nested TokenFactors.
22217 if (ChainVal == LdVal)
22218 Ld = cast<LoadSDNode>(St->getChain());
22219 else if (St->getValue().hasOneUse() &&
22220 ChainVal->getOpcode() == ISD::TokenFactor) {
22221 for (unsigned i = 0, e = ChainVal->getNumOperands(); i != e; ++i) {
22222 if (ChainVal->getOperand(i).getNode() == LdVal) {
22223 TokenFactorIndex = i;
22224 Ld = cast<LoadSDNode>(St->getValue());
22226 Ops.push_back(ChainVal->getOperand(i));
22230 if (!Ld || !ISD::isNormalLoad(Ld))
22233 // If this is not the MMX case, i.e. we are just turning i64 load/store
22234 // into f64 load/store, avoid the transformation if there are multiple
22235 // uses of the loaded value.
22236 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
22241 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
22242 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
22244 if (Subtarget->is64Bit() || F64IsLegal) {
22245 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
22246 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(),
22247 Ld->getPointerInfo(), Ld->isVolatile(),
22248 Ld->isNonTemporal(), Ld->isInvariant(),
22249 Ld->getAlignment());
22250 SDValue NewChain = NewLd.getValue(1);
22251 if (TokenFactorIndex != -1) {
22252 Ops.push_back(NewChain);
22253 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
22255 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
22256 St->getPointerInfo(),
22257 St->isVolatile(), St->isNonTemporal(),
22258 St->getAlignment());
22261 // Otherwise, lower to two pairs of 32-bit loads / stores.
22262 SDValue LoAddr = Ld->getBasePtr();
22263 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
22264 DAG.getConstant(4, MVT::i32));
22266 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
22267 Ld->getPointerInfo(),
22268 Ld->isVolatile(), Ld->isNonTemporal(),
22269 Ld->isInvariant(), Ld->getAlignment());
22270 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
22271 Ld->getPointerInfo().getWithOffset(4),
22272 Ld->isVolatile(), Ld->isNonTemporal(),
22274 MinAlign(Ld->getAlignment(), 4));
22276 SDValue NewChain = LoLd.getValue(1);
22277 if (TokenFactorIndex != -1) {
22278 Ops.push_back(LoLd);
22279 Ops.push_back(HiLd);
22280 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
22283 LoAddr = St->getBasePtr();
22284 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
22285 DAG.getConstant(4, MVT::i32));
22287 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
22288 St->getPointerInfo(),
22289 St->isVolatile(), St->isNonTemporal(),
22290 St->getAlignment());
22291 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
22292 St->getPointerInfo().getWithOffset(4),
22294 St->isNonTemporal(),
22295 MinAlign(St->getAlignment(), 4));
22296 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
22301 /// isHorizontalBinOp - Return 'true' if this vector operation is "horizontal"
22302 /// and return the operands for the horizontal operation in LHS and RHS. A
22303 /// horizontal operation performs the binary operation on successive elements
22304 /// of its first operand, then on successive elements of its second operand,
22305 /// returning the resulting values in a vector. For example, if
22306 /// A = < float a0, float a1, float a2, float a3 >
22308 /// B = < float b0, float b1, float b2, float b3 >
22309 /// then the result of doing a horizontal operation on A and B is
22310 /// A horizontal-op B = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >.
22311 /// In short, LHS and RHS are inspected to see if LHS op RHS is of the form
22312 /// A horizontal-op B, for some already available A and B, and if so then LHS is
22313 /// set to A, RHS to B, and the routine returns 'true'.
22314 /// Note that the binary operation should have the property that if one of the
22315 /// operands is UNDEF then the result is UNDEF.
22316 static bool isHorizontalBinOp(SDValue &LHS, SDValue &RHS, bool IsCommutative) {
22317 // Look for the following pattern: if
22318 // A = < float a0, float a1, float a2, float a3 >
22319 // B = < float b0, float b1, float b2, float b3 >
22321 // LHS = VECTOR_SHUFFLE A, B, <0, 2, 4, 6>
22322 // RHS = VECTOR_SHUFFLE A, B, <1, 3, 5, 7>
22323 // then LHS op RHS = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >
22324 // which is A horizontal-op B.
22326 // At least one of the operands should be a vector shuffle.
22327 if (LHS.getOpcode() != ISD::VECTOR_SHUFFLE &&
22328 RHS.getOpcode() != ISD::VECTOR_SHUFFLE)
22331 MVT VT = LHS.getSimpleValueType();
22333 assert((VT.is128BitVector() || VT.is256BitVector()) &&
22334 "Unsupported vector type for horizontal add/sub");
22336 // Handle 128 and 256-bit vector lengths. AVX defines horizontal add/sub to
22337 // operate independently on 128-bit lanes.
22338 unsigned NumElts = VT.getVectorNumElements();
22339 unsigned NumLanes = VT.getSizeInBits()/128;
22340 unsigned NumLaneElts = NumElts / NumLanes;
22341 assert((NumLaneElts % 2 == 0) &&
22342 "Vector type should have an even number of elements in each lane");
22343 unsigned HalfLaneElts = NumLaneElts/2;
22345 // View LHS in the form
22346 // LHS = VECTOR_SHUFFLE A, B, LMask
22347 // If LHS is not a shuffle then pretend it is the shuffle
22348 // LHS = VECTOR_SHUFFLE LHS, undef, <0, 1, ..., N-1>
22349 // NOTE: in what follows a default initialized SDValue represents an UNDEF of
22352 SmallVector<int, 16> LMask(NumElts);
22353 if (LHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
22354 if (LHS.getOperand(0).getOpcode() != ISD::UNDEF)
22355 A = LHS.getOperand(0);
22356 if (LHS.getOperand(1).getOpcode() != ISD::UNDEF)
22357 B = LHS.getOperand(1);
22358 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(LHS.getNode())->getMask();
22359 std::copy(Mask.begin(), Mask.end(), LMask.begin());
22361 if (LHS.getOpcode() != ISD::UNDEF)
22363 for (unsigned i = 0; i != NumElts; ++i)
22367 // Likewise, view RHS in the form
22368 // RHS = VECTOR_SHUFFLE C, D, RMask
22370 SmallVector<int, 16> RMask(NumElts);
22371 if (RHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
22372 if (RHS.getOperand(0).getOpcode() != ISD::UNDEF)
22373 C = RHS.getOperand(0);
22374 if (RHS.getOperand(1).getOpcode() != ISD::UNDEF)
22375 D = RHS.getOperand(1);
22376 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(RHS.getNode())->getMask();
22377 std::copy(Mask.begin(), Mask.end(), RMask.begin());
22379 if (RHS.getOpcode() != ISD::UNDEF)
22381 for (unsigned i = 0; i != NumElts; ++i)
22385 // Check that the shuffles are both shuffling the same vectors.
22386 if (!(A == C && B == D) && !(A == D && B == C))
22389 // If everything is UNDEF then bail out: it would be better to fold to UNDEF.
22390 if (!A.getNode() && !B.getNode())
22393 // If A and B occur in reverse order in RHS, then "swap" them (which means
22394 // rewriting the mask).
22396 CommuteVectorShuffleMask(RMask, NumElts);
22398 // At this point LHS and RHS are equivalent to
22399 // LHS = VECTOR_SHUFFLE A, B, LMask
22400 // RHS = VECTOR_SHUFFLE A, B, RMask
22401 // Check that the masks correspond to performing a horizontal operation.
22402 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
22403 for (unsigned i = 0; i != NumLaneElts; ++i) {
22404 int LIdx = LMask[i+l], RIdx = RMask[i+l];
22406 // Ignore any UNDEF components.
22407 if (LIdx < 0 || RIdx < 0 ||
22408 (!A.getNode() && (LIdx < (int)NumElts || RIdx < (int)NumElts)) ||
22409 (!B.getNode() && (LIdx >= (int)NumElts || RIdx >= (int)NumElts)))
22412 // Check that successive elements are being operated on. If not, this is
22413 // not a horizontal operation.
22414 unsigned Src = (i/HalfLaneElts); // each lane is split between srcs
22415 int Index = 2*(i%HalfLaneElts) + NumElts*Src + l;
22416 if (!(LIdx == Index && RIdx == Index + 1) &&
22417 !(IsCommutative && LIdx == Index + 1 && RIdx == Index))
22422 LHS = A.getNode() ? A : B; // If A is 'UNDEF', use B for it.
22423 RHS = B.getNode() ? B : A; // If B is 'UNDEF', use A for it.
22427 /// PerformFADDCombine - Do target-specific dag combines on floating point adds.
22428 static SDValue PerformFADDCombine(SDNode *N, SelectionDAG &DAG,
22429 const X86Subtarget *Subtarget) {
22430 EVT VT = N->getValueType(0);
22431 SDValue LHS = N->getOperand(0);
22432 SDValue RHS = N->getOperand(1);
22434 // Try to synthesize horizontal adds from adds of shuffles.
22435 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
22436 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
22437 isHorizontalBinOp(LHS, RHS, true))
22438 return DAG.getNode(X86ISD::FHADD, SDLoc(N), VT, LHS, RHS);
22442 /// PerformFSUBCombine - Do target-specific dag combines on floating point subs.
22443 static SDValue PerformFSUBCombine(SDNode *N, SelectionDAG &DAG,
22444 const X86Subtarget *Subtarget) {
22445 EVT VT = N->getValueType(0);
22446 SDValue LHS = N->getOperand(0);
22447 SDValue RHS = N->getOperand(1);
22449 // Try to synthesize horizontal subs from subs of shuffles.
22450 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
22451 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
22452 isHorizontalBinOp(LHS, RHS, false))
22453 return DAG.getNode(X86ISD::FHSUB, SDLoc(N), VT, LHS, RHS);
22457 /// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and
22458 /// X86ISD::FXOR nodes.
22459 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
22460 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
22461 // F[X]OR(0.0, x) -> x
22462 // F[X]OR(x, 0.0) -> x
22463 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
22464 if (C->getValueAPF().isPosZero())
22465 return N->getOperand(1);
22466 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
22467 if (C->getValueAPF().isPosZero())
22468 return N->getOperand(0);
22472 /// PerformFMinFMaxCombine - Do target-specific dag combines on X86ISD::FMIN and
22473 /// X86ISD::FMAX nodes.
22474 static SDValue PerformFMinFMaxCombine(SDNode *N, SelectionDAG &DAG) {
22475 assert(N->getOpcode() == X86ISD::FMIN || N->getOpcode() == X86ISD::FMAX);
22477 // Only perform optimizations if UnsafeMath is used.
22478 if (!DAG.getTarget().Options.UnsafeFPMath)
22481 // If we run in unsafe-math mode, then convert the FMAX and FMIN nodes
22482 // into FMINC and FMAXC, which are Commutative operations.
22483 unsigned NewOp = 0;
22484 switch (N->getOpcode()) {
22485 default: llvm_unreachable("unknown opcode");
22486 case X86ISD::FMIN: NewOp = X86ISD::FMINC; break;
22487 case X86ISD::FMAX: NewOp = X86ISD::FMAXC; break;
22490 return DAG.getNode(NewOp, SDLoc(N), N->getValueType(0),
22491 N->getOperand(0), N->getOperand(1));
22494 /// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes.
22495 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
22496 // FAND(0.0, x) -> 0.0
22497 // FAND(x, 0.0) -> 0.0
22498 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
22499 if (C->getValueAPF().isPosZero())
22500 return N->getOperand(0);
22501 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
22502 if (C->getValueAPF().isPosZero())
22503 return N->getOperand(1);
22507 /// PerformFANDNCombine - Do target-specific dag combines on X86ISD::FANDN nodes
22508 static SDValue PerformFANDNCombine(SDNode *N, SelectionDAG &DAG) {
22509 // FANDN(x, 0.0) -> 0.0
22510 // FANDN(0.0, x) -> x
22511 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
22512 if (C->getValueAPF().isPosZero())
22513 return N->getOperand(1);
22514 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
22515 if (C->getValueAPF().isPosZero())
22516 return N->getOperand(1);
22520 static SDValue PerformBTCombine(SDNode *N,
22522 TargetLowering::DAGCombinerInfo &DCI) {
22523 // BT ignores high bits in the bit index operand.
22524 SDValue Op1 = N->getOperand(1);
22525 if (Op1.hasOneUse()) {
22526 unsigned BitWidth = Op1.getValueSizeInBits();
22527 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
22528 APInt KnownZero, KnownOne;
22529 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
22530 !DCI.isBeforeLegalizeOps());
22531 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22532 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
22533 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
22534 DCI.CommitTargetLoweringOpt(TLO);
22539 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
22540 SDValue Op = N->getOperand(0);
22541 if (Op.getOpcode() == ISD::BITCAST)
22542 Op = Op.getOperand(0);
22543 EVT VT = N->getValueType(0), OpVT = Op.getValueType();
22544 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
22545 VT.getVectorElementType().getSizeInBits() ==
22546 OpVT.getVectorElementType().getSizeInBits()) {
22547 return DAG.getNode(ISD::BITCAST, SDLoc(N), VT, Op);
22552 static SDValue PerformSIGN_EXTEND_INREGCombine(SDNode *N, SelectionDAG &DAG,
22553 const X86Subtarget *Subtarget) {
22554 EVT VT = N->getValueType(0);
22555 if (!VT.isVector())
22558 SDValue N0 = N->getOperand(0);
22559 SDValue N1 = N->getOperand(1);
22560 EVT ExtraVT = cast<VTSDNode>(N1)->getVT();
22563 // The SIGN_EXTEND_INREG to v4i64 is expensive operation on the
22564 // both SSE and AVX2 since there is no sign-extended shift right
22565 // operation on a vector with 64-bit elements.
22566 //(sext_in_reg (v4i64 anyext (v4i32 x )), ExtraVT) ->
22567 // (v4i64 sext (v4i32 sext_in_reg (v4i32 x , ExtraVT)))
22568 if (VT == MVT::v4i64 && (N0.getOpcode() == ISD::ANY_EXTEND ||
22569 N0.getOpcode() == ISD::SIGN_EXTEND)) {
22570 SDValue N00 = N0.getOperand(0);
22572 // EXTLOAD has a better solution on AVX2,
22573 // it may be replaced with X86ISD::VSEXT node.
22574 if (N00.getOpcode() == ISD::LOAD && Subtarget->hasInt256())
22575 if (!ISD::isNormalLoad(N00.getNode()))
22578 if (N00.getValueType() == MVT::v4i32 && ExtraVT.getSizeInBits() < 128) {
22579 SDValue Tmp = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v4i32,
22581 return DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i64, Tmp);
22587 static SDValue PerformSExtCombine(SDNode *N, SelectionDAG &DAG,
22588 TargetLowering::DAGCombinerInfo &DCI,
22589 const X86Subtarget *Subtarget) {
22590 if (!DCI.isBeforeLegalizeOps())
22593 if (!Subtarget->hasFp256())
22596 EVT VT = N->getValueType(0);
22597 if (VT.isVector() && VT.getSizeInBits() == 256) {
22598 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget);
22606 static SDValue PerformFMACombine(SDNode *N, SelectionDAG &DAG,
22607 const X86Subtarget* Subtarget) {
22609 EVT VT = N->getValueType(0);
22611 // Let legalize expand this if it isn't a legal type yet.
22612 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
22615 EVT ScalarVT = VT.getScalarType();
22616 if ((ScalarVT != MVT::f32 && ScalarVT != MVT::f64) ||
22617 (!Subtarget->hasFMA() && !Subtarget->hasFMA4()))
22620 SDValue A = N->getOperand(0);
22621 SDValue B = N->getOperand(1);
22622 SDValue C = N->getOperand(2);
22624 bool NegA = (A.getOpcode() == ISD::FNEG);
22625 bool NegB = (B.getOpcode() == ISD::FNEG);
22626 bool NegC = (C.getOpcode() == ISD::FNEG);
22628 // Negative multiplication when NegA xor NegB
22629 bool NegMul = (NegA != NegB);
22631 A = A.getOperand(0);
22633 B = B.getOperand(0);
22635 C = C.getOperand(0);
22639 Opcode = (!NegC) ? X86ISD::FMADD : X86ISD::FMSUB;
22641 Opcode = (!NegC) ? X86ISD::FNMADD : X86ISD::FNMSUB;
22643 return DAG.getNode(Opcode, dl, VT, A, B, C);
22646 static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG,
22647 TargetLowering::DAGCombinerInfo &DCI,
22648 const X86Subtarget *Subtarget) {
22649 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) ->
22650 // (and (i32 x86isd::setcc_carry), 1)
22651 // This eliminates the zext. This transformation is necessary because
22652 // ISD::SETCC is always legalized to i8.
22654 SDValue N0 = N->getOperand(0);
22655 EVT VT = N->getValueType(0);
22657 if (N0.getOpcode() == ISD::AND &&
22659 N0.getOperand(0).hasOneUse()) {
22660 SDValue N00 = N0.getOperand(0);
22661 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
22662 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
22663 if (!C || C->getZExtValue() != 1)
22665 return DAG.getNode(ISD::AND, dl, VT,
22666 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
22667 N00.getOperand(0), N00.getOperand(1)),
22668 DAG.getConstant(1, VT));
22672 if (N0.getOpcode() == ISD::TRUNCATE &&
22674 N0.getOperand(0).hasOneUse()) {
22675 SDValue N00 = N0.getOperand(0);
22676 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
22677 return DAG.getNode(ISD::AND, dl, VT,
22678 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
22679 N00.getOperand(0), N00.getOperand(1)),
22680 DAG.getConstant(1, VT));
22683 if (VT.is256BitVector()) {
22684 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget);
22692 // Optimize x == -y --> x+y == 0
22693 // x != -y --> x+y != 0
22694 static SDValue PerformISDSETCCCombine(SDNode *N, SelectionDAG &DAG,
22695 const X86Subtarget* Subtarget) {
22696 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
22697 SDValue LHS = N->getOperand(0);
22698 SDValue RHS = N->getOperand(1);
22699 EVT VT = N->getValueType(0);
22702 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && LHS.getOpcode() == ISD::SUB)
22703 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(LHS.getOperand(0)))
22704 if (C->getAPIntValue() == 0 && LHS.hasOneUse()) {
22705 SDValue addV = DAG.getNode(ISD::ADD, SDLoc(N),
22706 LHS.getValueType(), RHS, LHS.getOperand(1));
22707 return DAG.getSetCC(SDLoc(N), N->getValueType(0),
22708 addV, DAG.getConstant(0, addV.getValueType()), CC);
22710 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && RHS.getOpcode() == ISD::SUB)
22711 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS.getOperand(0)))
22712 if (C->getAPIntValue() == 0 && RHS.hasOneUse()) {
22713 SDValue addV = DAG.getNode(ISD::ADD, SDLoc(N),
22714 RHS.getValueType(), LHS, RHS.getOperand(1));
22715 return DAG.getSetCC(SDLoc(N), N->getValueType(0),
22716 addV, DAG.getConstant(0, addV.getValueType()), CC);
22719 if (VT.getScalarType() == MVT::i1) {
22720 bool IsSEXT0 = (LHS.getOpcode() == ISD::SIGN_EXTEND) &&
22721 (LHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
22722 bool IsVZero0 = ISD::isBuildVectorAllZeros(LHS.getNode());
22723 if (!IsSEXT0 && !IsVZero0)
22725 bool IsSEXT1 = (RHS.getOpcode() == ISD::SIGN_EXTEND) &&
22726 (RHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
22727 bool IsVZero1 = ISD::isBuildVectorAllZeros(RHS.getNode());
22729 if (!IsSEXT1 && !IsVZero1)
22732 if (IsSEXT0 && IsVZero1) {
22733 assert(VT == LHS.getOperand(0).getValueType() && "Uexpected operand type");
22734 if (CC == ISD::SETEQ)
22735 return DAG.getNOT(DL, LHS.getOperand(0), VT);
22736 return LHS.getOperand(0);
22738 if (IsSEXT1 && IsVZero0) {
22739 assert(VT == RHS.getOperand(0).getValueType() && "Uexpected operand type");
22740 if (CC == ISD::SETEQ)
22741 return DAG.getNOT(DL, RHS.getOperand(0), VT);
22742 return RHS.getOperand(0);
22749 static SDValue PerformINSERTPSCombine(SDNode *N, SelectionDAG &DAG,
22750 const X86Subtarget *Subtarget) {
22752 MVT VT = N->getOperand(1)->getSimpleValueType(0);
22753 assert((VT == MVT::v4f32 || VT == MVT::v4i32) &&
22754 "X86insertps is only defined for v4x32");
22756 SDValue Ld = N->getOperand(1);
22757 if (MayFoldLoad(Ld)) {
22758 // Extract the countS bits from the immediate so we can get the proper
22759 // address when narrowing the vector load to a specific element.
22760 // When the second source op is a memory address, interps doesn't use
22761 // countS and just gets an f32 from that address.
22762 unsigned DestIndex =
22763 cast<ConstantSDNode>(N->getOperand(2))->getZExtValue() >> 6;
22764 Ld = NarrowVectorLoadToElement(cast<LoadSDNode>(Ld), DestIndex, DAG);
22768 // Create this as a scalar to vector to match the instruction pattern.
22769 SDValue LoadScalarToVector = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Ld);
22770 // countS bits are ignored when loading from memory on insertps, which
22771 // means we don't need to explicitly set them to 0.
22772 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N->getOperand(0),
22773 LoadScalarToVector, N->getOperand(2));
22776 // Helper function of PerformSETCCCombine. It is to materialize "setb reg"
22777 // as "sbb reg,reg", since it can be extended without zext and produces
22778 // an all-ones bit which is more useful than 0/1 in some cases.
22779 static SDValue MaterializeSETB(SDLoc DL, SDValue EFLAGS, SelectionDAG &DAG,
22782 return DAG.getNode(ISD::AND, DL, VT,
22783 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
22784 DAG.getConstant(X86::COND_B, MVT::i8), EFLAGS),
22785 DAG.getConstant(1, VT));
22786 assert (VT == MVT::i1 && "Unexpected type for SECCC node");
22787 return DAG.getNode(ISD::TRUNCATE, DL, MVT::i1,
22788 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
22789 DAG.getConstant(X86::COND_B, MVT::i8), EFLAGS));
22792 // Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT
22793 static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG,
22794 TargetLowering::DAGCombinerInfo &DCI,
22795 const X86Subtarget *Subtarget) {
22797 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(0));
22798 SDValue EFLAGS = N->getOperand(1);
22800 if (CC == X86::COND_A) {
22801 // Try to convert COND_A into COND_B in an attempt to facilitate
22802 // materializing "setb reg".
22804 // Do not flip "e > c", where "c" is a constant, because Cmp instruction
22805 // cannot take an immediate as its first operand.
22807 if (EFLAGS.getOpcode() == X86ISD::SUB && EFLAGS.hasOneUse() &&
22808 EFLAGS.getValueType().isInteger() &&
22809 !isa<ConstantSDNode>(EFLAGS.getOperand(1))) {
22810 SDValue NewSub = DAG.getNode(X86ISD::SUB, SDLoc(EFLAGS),
22811 EFLAGS.getNode()->getVTList(),
22812 EFLAGS.getOperand(1), EFLAGS.getOperand(0));
22813 SDValue NewEFLAGS = SDValue(NewSub.getNode(), EFLAGS.getResNo());
22814 return MaterializeSETB(DL, NewEFLAGS, DAG, N->getSimpleValueType(0));
22818 // Materialize "setb reg" as "sbb reg,reg", since it can be extended without
22819 // a zext and produces an all-ones bit which is more useful than 0/1 in some
22821 if (CC == X86::COND_B)
22822 return MaterializeSETB(DL, EFLAGS, DAG, N->getSimpleValueType(0));
22826 Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
22827 if (Flags.getNode()) {
22828 SDValue Cond = DAG.getConstant(CC, MVT::i8);
22829 return DAG.getNode(X86ISD::SETCC, DL, N->getVTList(), Cond, Flags);
22835 // Optimize branch condition evaluation.
22837 static SDValue PerformBrCondCombine(SDNode *N, SelectionDAG &DAG,
22838 TargetLowering::DAGCombinerInfo &DCI,
22839 const X86Subtarget *Subtarget) {
22841 SDValue Chain = N->getOperand(0);
22842 SDValue Dest = N->getOperand(1);
22843 SDValue EFLAGS = N->getOperand(3);
22844 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(2));
22848 Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
22849 if (Flags.getNode()) {
22850 SDValue Cond = DAG.getConstant(CC, MVT::i8);
22851 return DAG.getNode(X86ISD::BRCOND, DL, N->getVTList(), Chain, Dest, Cond,
22858 static SDValue performVectorCompareAndMaskUnaryOpCombine(SDNode *N,
22859 SelectionDAG &DAG) {
22860 // Take advantage of vector comparisons producing 0 or -1 in each lane to
22861 // optimize away operation when it's from a constant.
22863 // The general transformation is:
22864 // UNARYOP(AND(VECTOR_CMP(x,y), constant)) -->
22865 // AND(VECTOR_CMP(x,y), constant2)
22866 // constant2 = UNARYOP(constant)
22868 // Early exit if this isn't a vector operation, the operand of the
22869 // unary operation isn't a bitwise AND, or if the sizes of the operations
22870 // aren't the same.
22871 EVT VT = N->getValueType(0);
22872 if (!VT.isVector() || N->getOperand(0)->getOpcode() != ISD::AND ||
22873 N->getOperand(0)->getOperand(0)->getOpcode() != ISD::SETCC ||
22874 VT.getSizeInBits() != N->getOperand(0)->getValueType(0).getSizeInBits())
22877 // Now check that the other operand of the AND is a constant. We could
22878 // make the transformation for non-constant splats as well, but it's unclear
22879 // that would be a benefit as it would not eliminate any operations, just
22880 // perform one more step in scalar code before moving to the vector unit.
22881 if (BuildVectorSDNode *BV =
22882 dyn_cast<BuildVectorSDNode>(N->getOperand(0)->getOperand(1))) {
22883 // Bail out if the vector isn't a constant.
22884 if (!BV->isConstant())
22887 // Everything checks out. Build up the new and improved node.
22889 EVT IntVT = BV->getValueType(0);
22890 // Create a new constant of the appropriate type for the transformed
22892 SDValue SourceConst = DAG.getNode(N->getOpcode(), DL, VT, SDValue(BV, 0));
22893 // The AND node needs bitcasts to/from an integer vector type around it.
22894 SDValue MaskConst = DAG.getNode(ISD::BITCAST, DL, IntVT, SourceConst);
22895 SDValue NewAnd = DAG.getNode(ISD::AND, DL, IntVT,
22896 N->getOperand(0)->getOperand(0), MaskConst);
22897 SDValue Res = DAG.getNode(ISD::BITCAST, DL, VT, NewAnd);
22904 static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
22905 const X86TargetLowering *XTLI) {
22906 // First try to optimize away the conversion entirely when it's
22907 // conditionally from a constant. Vectors only.
22908 SDValue Res = performVectorCompareAndMaskUnaryOpCombine(N, DAG);
22909 if (Res != SDValue())
22912 // Now move on to more general possibilities.
22913 SDValue Op0 = N->getOperand(0);
22914 EVT InVT = Op0->getValueType(0);
22916 // SINT_TO_FP(v4i8) -> SINT_TO_FP(SEXT(v4i8 to v4i32))
22917 if (InVT == MVT::v8i8 || InVT == MVT::v4i8) {
22919 MVT DstVT = InVT == MVT::v4i8 ? MVT::v4i32 : MVT::v8i32;
22920 SDValue P = DAG.getNode(ISD::SIGN_EXTEND, dl, DstVT, Op0);
22921 return DAG.getNode(ISD::SINT_TO_FP, dl, N->getValueType(0), P);
22924 // Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have
22925 // a 32-bit target where SSE doesn't support i64->FP operations.
22926 if (Op0.getOpcode() == ISD::LOAD) {
22927 LoadSDNode *Ld = cast<LoadSDNode>(Op0.getNode());
22928 EVT VT = Ld->getValueType(0);
22929 if (!Ld->isVolatile() && !N->getValueType(0).isVector() &&
22930 ISD::isNON_EXTLoad(Op0.getNode()) && Op0.hasOneUse() &&
22931 !XTLI->getSubtarget()->is64Bit() &&
22933 SDValue FILDChain = XTLI->BuildFILD(SDValue(N, 0), Ld->getValueType(0),
22934 Ld->getChain(), Op0, DAG);
22935 DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), FILDChain.getValue(1));
22942 // Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS
22943 static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG,
22944 X86TargetLowering::DAGCombinerInfo &DCI) {
22945 // If the LHS and RHS of the ADC node are zero, then it can't overflow and
22946 // the result is either zero or one (depending on the input carry bit).
22947 // Strength reduce this down to a "set on carry" aka SETCC_CARRY&1.
22948 if (X86::isZeroNode(N->getOperand(0)) &&
22949 X86::isZeroNode(N->getOperand(1)) &&
22950 // We don't have a good way to replace an EFLAGS use, so only do this when
22952 SDValue(N, 1).use_empty()) {
22954 EVT VT = N->getValueType(0);
22955 SDValue CarryOut = DAG.getConstant(0, N->getValueType(1));
22956 SDValue Res1 = DAG.getNode(ISD::AND, DL, VT,
22957 DAG.getNode(X86ISD::SETCC_CARRY, DL, VT,
22958 DAG.getConstant(X86::COND_B,MVT::i8),
22960 DAG.getConstant(1, VT));
22961 return DCI.CombineTo(N, Res1, CarryOut);
22967 // fold (add Y, (sete X, 0)) -> adc 0, Y
22968 // (add Y, (setne X, 0)) -> sbb -1, Y
22969 // (sub (sete X, 0), Y) -> sbb 0, Y
22970 // (sub (setne X, 0), Y) -> adc -1, Y
22971 static SDValue OptimizeConditionalInDecrement(SDNode *N, SelectionDAG &DAG) {
22974 // Look through ZExts.
22975 SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0);
22976 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse())
22979 SDValue SetCC = Ext.getOperand(0);
22980 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse())
22983 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0);
22984 if (CC != X86::COND_E && CC != X86::COND_NE)
22987 SDValue Cmp = SetCC.getOperand(1);
22988 if (Cmp.getOpcode() != X86ISD::CMP || !Cmp.hasOneUse() ||
22989 !X86::isZeroNode(Cmp.getOperand(1)) ||
22990 !Cmp.getOperand(0).getValueType().isInteger())
22993 SDValue CmpOp0 = Cmp.getOperand(0);
22994 SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, CmpOp0,
22995 DAG.getConstant(1, CmpOp0.getValueType()));
22997 SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1);
22998 if (CC == X86::COND_NE)
22999 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB,
23000 DL, OtherVal.getValueType(), OtherVal,
23001 DAG.getConstant(-1ULL, OtherVal.getValueType()), NewCmp);
23002 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC,
23003 DL, OtherVal.getValueType(), OtherVal,
23004 DAG.getConstant(0, OtherVal.getValueType()), NewCmp);
23007 /// PerformADDCombine - Do target-specific dag combines on integer adds.
23008 static SDValue PerformAddCombine(SDNode *N, SelectionDAG &DAG,
23009 const X86Subtarget *Subtarget) {
23010 EVT VT = N->getValueType(0);
23011 SDValue Op0 = N->getOperand(0);
23012 SDValue Op1 = N->getOperand(1);
23014 // Try to synthesize horizontal adds from adds of shuffles.
23015 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
23016 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
23017 isHorizontalBinOp(Op0, Op1, true))
23018 return DAG.getNode(X86ISD::HADD, SDLoc(N), VT, Op0, Op1);
23020 return OptimizeConditionalInDecrement(N, DAG);
23023 static SDValue PerformSubCombine(SDNode *N, SelectionDAG &DAG,
23024 const X86Subtarget *Subtarget) {
23025 SDValue Op0 = N->getOperand(0);
23026 SDValue Op1 = N->getOperand(1);
23028 // X86 can't encode an immediate LHS of a sub. See if we can push the
23029 // negation into a preceding instruction.
23030 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op0)) {
23031 // If the RHS of the sub is a XOR with one use and a constant, invert the
23032 // immediate. Then add one to the LHS of the sub so we can turn
23033 // X-Y -> X+~Y+1, saving one register.
23034 if (Op1->hasOneUse() && Op1.getOpcode() == ISD::XOR &&
23035 isa<ConstantSDNode>(Op1.getOperand(1))) {
23036 APInt XorC = cast<ConstantSDNode>(Op1.getOperand(1))->getAPIntValue();
23037 EVT VT = Op0.getValueType();
23038 SDValue NewXor = DAG.getNode(ISD::XOR, SDLoc(Op1), VT,
23040 DAG.getConstant(~XorC, VT));
23041 return DAG.getNode(ISD::ADD, SDLoc(N), VT, NewXor,
23042 DAG.getConstant(C->getAPIntValue()+1, VT));
23046 // Try to synthesize horizontal adds from adds of shuffles.
23047 EVT VT = N->getValueType(0);
23048 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
23049 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
23050 isHorizontalBinOp(Op0, Op1, true))
23051 return DAG.getNode(X86ISD::HSUB, SDLoc(N), VT, Op0, Op1);
23053 return OptimizeConditionalInDecrement(N, DAG);
23056 /// performVZEXTCombine - Performs build vector combines
23057 static SDValue performVZEXTCombine(SDNode *N, SelectionDAG &DAG,
23058 TargetLowering::DAGCombinerInfo &DCI,
23059 const X86Subtarget *Subtarget) {
23060 // (vzext (bitcast (vzext (x)) -> (vzext x)
23061 SDValue In = N->getOperand(0);
23062 while (In.getOpcode() == ISD::BITCAST)
23063 In = In.getOperand(0);
23065 if (In.getOpcode() != X86ISD::VZEXT)
23068 return DAG.getNode(X86ISD::VZEXT, SDLoc(N), N->getValueType(0),
23072 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
23073 DAGCombinerInfo &DCI) const {
23074 SelectionDAG &DAG = DCI.DAG;
23075 switch (N->getOpcode()) {
23077 case ISD::EXTRACT_VECTOR_ELT:
23078 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, DCI);
23080 case ISD::SELECT: return PerformSELECTCombine(N, DAG, DCI, Subtarget);
23081 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI, Subtarget);
23082 case ISD::ADD: return PerformAddCombine(N, DAG, Subtarget);
23083 case ISD::SUB: return PerformSubCombine(N, DAG, Subtarget);
23084 case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI);
23085 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
23088 case ISD::SRL: return PerformShiftCombine(N, DAG, DCI, Subtarget);
23089 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget);
23090 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget);
23091 case ISD::XOR: return PerformXorCombine(N, DAG, DCI, Subtarget);
23092 case ISD::LOAD: return PerformLOADCombine(N, DAG, DCI, Subtarget);
23093 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
23094 case ISD::SINT_TO_FP: return PerformSINT_TO_FPCombine(N, DAG, this);
23095 case ISD::FADD: return PerformFADDCombine(N, DAG, Subtarget);
23096 case ISD::FSUB: return PerformFSUBCombine(N, DAG, Subtarget);
23098 case X86ISD::FOR: return PerformFORCombine(N, DAG);
23100 case X86ISD::FMAX: return PerformFMinFMaxCombine(N, DAG);
23101 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
23102 case X86ISD::FANDN: return PerformFANDNCombine(N, DAG);
23103 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
23104 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
23105 case ISD::ANY_EXTEND:
23106 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG, DCI, Subtarget);
23107 case ISD::SIGN_EXTEND: return PerformSExtCombine(N, DAG, DCI, Subtarget);
23108 case ISD::SIGN_EXTEND_INREG:
23109 return PerformSIGN_EXTEND_INREGCombine(N, DAG, Subtarget);
23110 case ISD::TRUNCATE: return PerformTruncateCombine(N, DAG,DCI,Subtarget);
23111 case ISD::SETCC: return PerformISDSETCCCombine(N, DAG, Subtarget);
23112 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG, DCI, Subtarget);
23113 case X86ISD::BRCOND: return PerformBrCondCombine(N, DAG, DCI, Subtarget);
23114 case X86ISD::VZEXT: return performVZEXTCombine(N, DAG, DCI, Subtarget);
23115 case X86ISD::SHUFP: // Handle all target specific shuffles
23116 case X86ISD::PALIGNR:
23117 case X86ISD::UNPCKH:
23118 case X86ISD::UNPCKL:
23119 case X86ISD::MOVHLPS:
23120 case X86ISD::MOVLHPS:
23121 case X86ISD::PSHUFB:
23122 case X86ISD::PSHUFD:
23123 case X86ISD::PSHUFHW:
23124 case X86ISD::PSHUFLW:
23125 case X86ISD::MOVSS:
23126 case X86ISD::MOVSD:
23127 case X86ISD::VPERMILP:
23128 case X86ISD::VPERM2X128:
23129 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget);
23130 case ISD::FMA: return PerformFMACombine(N, DAG, Subtarget);
23131 case ISD::INTRINSIC_WO_CHAIN:
23132 return PerformINTRINSIC_WO_CHAINCombine(N, DAG, Subtarget);
23133 case X86ISD::INSERTPS:
23134 return PerformINSERTPSCombine(N, DAG, Subtarget);
23135 case ISD::BUILD_VECTOR: return PerformBUILD_VECTORCombine(N, DAG, Subtarget);
23141 /// isTypeDesirableForOp - Return true if the target has native support for
23142 /// the specified value type and it is 'desirable' to use the type for the
23143 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
23144 /// instruction encodings are longer and some i16 instructions are slow.
23145 bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const {
23146 if (!isTypeLegal(VT))
23148 if (VT != MVT::i16)
23155 case ISD::SIGN_EXTEND:
23156 case ISD::ZERO_EXTEND:
23157 case ISD::ANY_EXTEND:
23170 /// IsDesirableToPromoteOp - This method query the target whether it is
23171 /// beneficial for dag combiner to promote the specified node. If true, it
23172 /// should return the desired promotion type by reference.
23173 bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
23174 EVT VT = Op.getValueType();
23175 if (VT != MVT::i16)
23178 bool Promote = false;
23179 bool Commute = false;
23180 switch (Op.getOpcode()) {
23183 LoadSDNode *LD = cast<LoadSDNode>(Op);
23184 // If the non-extending load has a single use and it's not live out, then it
23185 // might be folded.
23186 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&&
23187 Op.hasOneUse()*/) {
23188 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
23189 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
23190 // The only case where we'd want to promote LOAD (rather then it being
23191 // promoted as an operand is when it's only use is liveout.
23192 if (UI->getOpcode() != ISD::CopyToReg)
23199 case ISD::SIGN_EXTEND:
23200 case ISD::ZERO_EXTEND:
23201 case ISD::ANY_EXTEND:
23206 SDValue N0 = Op.getOperand(0);
23207 // Look out for (store (shl (load), x)).
23208 if (MayFoldLoad(N0) && MayFoldIntoStore(Op))
23221 SDValue N0 = Op.getOperand(0);
23222 SDValue N1 = Op.getOperand(1);
23223 if (!Commute && MayFoldLoad(N1))
23225 // Avoid disabling potential load folding opportunities.
23226 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op)))
23228 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op)))
23238 //===----------------------------------------------------------------------===//
23239 // X86 Inline Assembly Support
23240 //===----------------------------------------------------------------------===//
23243 // Helper to match a string separated by whitespace.
23244 bool matchAsmImpl(StringRef s, ArrayRef<const StringRef *> args) {
23245 s = s.substr(s.find_first_not_of(" \t")); // Skip leading whitespace.
23247 for (unsigned i = 0, e = args.size(); i != e; ++i) {
23248 StringRef piece(*args[i]);
23249 if (!s.startswith(piece)) // Check if the piece matches.
23252 s = s.substr(piece.size());
23253 StringRef::size_type pos = s.find_first_not_of(" \t");
23254 if (pos == 0) // We matched a prefix.
23262 const VariadicFunction1<bool, StringRef, StringRef, matchAsmImpl> matchAsm={};
23265 static bool clobbersFlagRegisters(const SmallVector<StringRef, 4> &AsmPieces) {
23267 if (AsmPieces.size() == 3 || AsmPieces.size() == 4) {
23268 if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{cc}") &&
23269 std::count(AsmPieces.begin(), AsmPieces.end(), "~{flags}") &&
23270 std::count(AsmPieces.begin(), AsmPieces.end(), "~{fpsr}")) {
23272 if (AsmPieces.size() == 3)
23274 else if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{dirflag}"))
23281 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
23282 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
23284 std::string AsmStr = IA->getAsmString();
23286 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
23287 if (!Ty || Ty->getBitWidth() % 16 != 0)
23290 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
23291 SmallVector<StringRef, 4> AsmPieces;
23292 SplitString(AsmStr, AsmPieces, ";\n");
23294 switch (AsmPieces.size()) {
23295 default: return false;
23297 // FIXME: this should verify that we are targeting a 486 or better. If not,
23298 // we will turn this bswap into something that will be lowered to logical
23299 // ops instead of emitting the bswap asm. For now, we don't support 486 or
23300 // lower so don't worry about this.
23302 if (matchAsm(AsmPieces[0], "bswap", "$0") ||
23303 matchAsm(AsmPieces[0], "bswapl", "$0") ||
23304 matchAsm(AsmPieces[0], "bswapq", "$0") ||
23305 matchAsm(AsmPieces[0], "bswap", "${0:q}") ||
23306 matchAsm(AsmPieces[0], "bswapl", "${0:q}") ||
23307 matchAsm(AsmPieces[0], "bswapq", "${0:q}")) {
23308 // No need to check constraints, nothing other than the equivalent of
23309 // "=r,0" would be valid here.
23310 return IntrinsicLowering::LowerToByteSwap(CI);
23313 // rorw $$8, ${0:w} --> llvm.bswap.i16
23314 if (CI->getType()->isIntegerTy(16) &&
23315 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
23316 (matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") ||
23317 matchAsm(AsmPieces[0], "rolw", "$$8,", "${0:w}"))) {
23319 const std::string &ConstraintsStr = IA->getConstraintString();
23320 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
23321 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
23322 if (clobbersFlagRegisters(AsmPieces))
23323 return IntrinsicLowering::LowerToByteSwap(CI);
23327 if (CI->getType()->isIntegerTy(32) &&
23328 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
23329 matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") &&
23330 matchAsm(AsmPieces[1], "rorl", "$$16,", "$0") &&
23331 matchAsm(AsmPieces[2], "rorw", "$$8,", "${0:w}")) {
23333 const std::string &ConstraintsStr = IA->getConstraintString();
23334 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
23335 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
23336 if (clobbersFlagRegisters(AsmPieces))
23337 return IntrinsicLowering::LowerToByteSwap(CI);
23340 if (CI->getType()->isIntegerTy(64)) {
23341 InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints();
23342 if (Constraints.size() >= 2 &&
23343 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
23344 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
23345 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
23346 if (matchAsm(AsmPieces[0], "bswap", "%eax") &&
23347 matchAsm(AsmPieces[1], "bswap", "%edx") &&
23348 matchAsm(AsmPieces[2], "xchgl", "%eax,", "%edx"))
23349 return IntrinsicLowering::LowerToByteSwap(CI);
23357 /// getConstraintType - Given a constraint letter, return the type of
23358 /// constraint it is for this target.
23359 X86TargetLowering::ConstraintType
23360 X86TargetLowering::getConstraintType(const std::string &Constraint) const {
23361 if (Constraint.size() == 1) {
23362 switch (Constraint[0]) {
23373 return C_RegisterClass;
23397 return TargetLowering::getConstraintType(Constraint);
23400 /// Examine constraint type and operand type and determine a weight value.
23401 /// This object must already have been set up with the operand type
23402 /// and the current alternative constraint selected.
23403 TargetLowering::ConstraintWeight
23404 X86TargetLowering::getSingleConstraintMatchWeight(
23405 AsmOperandInfo &info, const char *constraint) const {
23406 ConstraintWeight weight = CW_Invalid;
23407 Value *CallOperandVal = info.CallOperandVal;
23408 // If we don't have a value, we can't do a match,
23409 // but allow it at the lowest weight.
23410 if (!CallOperandVal)
23412 Type *type = CallOperandVal->getType();
23413 // Look at the constraint type.
23414 switch (*constraint) {
23416 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
23427 if (CallOperandVal->getType()->isIntegerTy())
23428 weight = CW_SpecificReg;
23433 if (type->isFloatingPointTy())
23434 weight = CW_SpecificReg;
23437 if (type->isX86_MMXTy() && Subtarget->hasMMX())
23438 weight = CW_SpecificReg;
23442 if (((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasSSE1()) ||
23443 ((type->getPrimitiveSizeInBits() == 256) && Subtarget->hasFp256()))
23444 weight = CW_Register;
23447 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) {
23448 if (C->getZExtValue() <= 31)
23449 weight = CW_Constant;
23453 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
23454 if (C->getZExtValue() <= 63)
23455 weight = CW_Constant;
23459 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
23460 if ((C->getSExtValue() >= -0x80) && (C->getSExtValue() <= 0x7f))
23461 weight = CW_Constant;
23465 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
23466 if ((C->getZExtValue() == 0xff) || (C->getZExtValue() == 0xffff))
23467 weight = CW_Constant;
23471 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
23472 if (C->getZExtValue() <= 3)
23473 weight = CW_Constant;
23477 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
23478 if (C->getZExtValue() <= 0xff)
23479 weight = CW_Constant;
23484 if (dyn_cast<ConstantFP>(CallOperandVal)) {
23485 weight = CW_Constant;
23489 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
23490 if ((C->getSExtValue() >= -0x80000000LL) &&
23491 (C->getSExtValue() <= 0x7fffffffLL))
23492 weight = CW_Constant;
23496 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
23497 if (C->getZExtValue() <= 0xffffffff)
23498 weight = CW_Constant;
23505 /// LowerXConstraint - try to replace an X constraint, which matches anything,
23506 /// with another that has more specific requirements based on the type of the
23507 /// corresponding operand.
23508 const char *X86TargetLowering::
23509 LowerXConstraint(EVT ConstraintVT) const {
23510 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
23511 // 'f' like normal targets.
23512 if (ConstraintVT.isFloatingPoint()) {
23513 if (Subtarget->hasSSE2())
23515 if (Subtarget->hasSSE1())
23519 return TargetLowering::LowerXConstraint(ConstraintVT);
23522 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
23523 /// vector. If it is invalid, don't add anything to Ops.
23524 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
23525 std::string &Constraint,
23526 std::vector<SDValue>&Ops,
23527 SelectionDAG &DAG) const {
23530 // Only support length 1 constraints for now.
23531 if (Constraint.length() > 1) return;
23533 char ConstraintLetter = Constraint[0];
23534 switch (ConstraintLetter) {
23537 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
23538 if (C->getZExtValue() <= 31) {
23539 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
23545 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
23546 if (C->getZExtValue() <= 63) {
23547 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
23553 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
23554 if (isInt<8>(C->getSExtValue())) {
23555 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
23561 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
23562 if (C->getZExtValue() <= 255) {
23563 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
23569 // 32-bit signed value
23570 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
23571 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
23572 C->getSExtValue())) {
23573 // Widen to 64 bits here to get it sign extended.
23574 Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64);
23577 // FIXME gcc accepts some relocatable values here too, but only in certain
23578 // memory models; it's complicated.
23583 // 32-bit unsigned value
23584 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
23585 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
23586 C->getZExtValue())) {
23587 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
23591 // FIXME gcc accepts some relocatable values here too, but only in certain
23592 // memory models; it's complicated.
23596 // Literal immediates are always ok.
23597 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
23598 // Widen to 64 bits here to get it sign extended.
23599 Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64);
23603 // In any sort of PIC mode addresses need to be computed at runtime by
23604 // adding in a register or some sort of table lookup. These can't
23605 // be used as immediates.
23606 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC())
23609 // If we are in non-pic codegen mode, we allow the address of a global (with
23610 // an optional displacement) to be used with 'i'.
23611 GlobalAddressSDNode *GA = nullptr;
23612 int64_t Offset = 0;
23614 // Match either (GA), (GA+C), (GA+C1+C2), etc.
23616 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
23617 Offset += GA->getOffset();
23619 } else if (Op.getOpcode() == ISD::ADD) {
23620 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
23621 Offset += C->getZExtValue();
23622 Op = Op.getOperand(0);
23625 } else if (Op.getOpcode() == ISD::SUB) {
23626 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
23627 Offset += -C->getZExtValue();
23628 Op = Op.getOperand(0);
23633 // Otherwise, this isn't something we can handle, reject it.
23637 const GlobalValue *GV = GA->getGlobal();
23638 // If we require an extra load to get this address, as in PIC mode, we
23639 // can't accept it.
23640 if (isGlobalStubReference(
23641 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget())))
23644 Result = DAG.getTargetGlobalAddress(GV, SDLoc(Op),
23645 GA->getValueType(0), Offset);
23650 if (Result.getNode()) {
23651 Ops.push_back(Result);
23654 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
23657 std::pair<unsigned, const TargetRegisterClass*>
23658 X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
23660 // First, see if this is a constraint that directly corresponds to an LLVM
23662 if (Constraint.size() == 1) {
23663 // GCC Constraint Letters
23664 switch (Constraint[0]) {
23666 // TODO: Slight differences here in allocation order and leaving
23667 // RIP in the class. Do they matter any more here than they do
23668 // in the normal allocation?
23669 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
23670 if (Subtarget->is64Bit()) {
23671 if (VT == MVT::i32 || VT == MVT::f32)
23672 return std::make_pair(0U, &X86::GR32RegClass);
23673 if (VT == MVT::i16)
23674 return std::make_pair(0U, &X86::GR16RegClass);
23675 if (VT == MVT::i8 || VT == MVT::i1)
23676 return std::make_pair(0U, &X86::GR8RegClass);
23677 if (VT == MVT::i64 || VT == MVT::f64)
23678 return std::make_pair(0U, &X86::GR64RegClass);
23681 // 32-bit fallthrough
23682 case 'Q': // Q_REGS
23683 if (VT == MVT::i32 || VT == MVT::f32)
23684 return std::make_pair(0U, &X86::GR32_ABCDRegClass);
23685 if (VT == MVT::i16)
23686 return std::make_pair(0U, &X86::GR16_ABCDRegClass);
23687 if (VT == MVT::i8 || VT == MVT::i1)
23688 return std::make_pair(0U, &X86::GR8_ABCD_LRegClass);
23689 if (VT == MVT::i64)
23690 return std::make_pair(0U, &X86::GR64_ABCDRegClass);
23692 case 'r': // GENERAL_REGS
23693 case 'l': // INDEX_REGS
23694 if (VT == MVT::i8 || VT == MVT::i1)
23695 return std::make_pair(0U, &X86::GR8RegClass);
23696 if (VT == MVT::i16)
23697 return std::make_pair(0U, &X86::GR16RegClass);
23698 if (VT == MVT::i32 || VT == MVT::f32 || !Subtarget->is64Bit())
23699 return std::make_pair(0U, &X86::GR32RegClass);
23700 return std::make_pair(0U, &X86::GR64RegClass);
23701 case 'R': // LEGACY_REGS
23702 if (VT == MVT::i8 || VT == MVT::i1)
23703 return std::make_pair(0U, &X86::GR8_NOREXRegClass);
23704 if (VT == MVT::i16)
23705 return std::make_pair(0U, &X86::GR16_NOREXRegClass);
23706 if (VT == MVT::i32 || !Subtarget->is64Bit())
23707 return std::make_pair(0U, &X86::GR32_NOREXRegClass);
23708 return std::make_pair(0U, &X86::GR64_NOREXRegClass);
23709 case 'f': // FP Stack registers.
23710 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
23711 // value to the correct fpstack register class.
23712 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
23713 return std::make_pair(0U, &X86::RFP32RegClass);
23714 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
23715 return std::make_pair(0U, &X86::RFP64RegClass);
23716 return std::make_pair(0U, &X86::RFP80RegClass);
23717 case 'y': // MMX_REGS if MMX allowed.
23718 if (!Subtarget->hasMMX()) break;
23719 return std::make_pair(0U, &X86::VR64RegClass);
23720 case 'Y': // SSE_REGS if SSE2 allowed
23721 if (!Subtarget->hasSSE2()) break;
23723 case 'x': // SSE_REGS if SSE1 allowed or AVX_REGS if AVX allowed
23724 if (!Subtarget->hasSSE1()) break;
23726 switch (VT.SimpleTy) {
23728 // Scalar SSE types.
23731 return std::make_pair(0U, &X86::FR32RegClass);
23734 return std::make_pair(0U, &X86::FR64RegClass);
23742 return std::make_pair(0U, &X86::VR128RegClass);
23750 return std::make_pair(0U, &X86::VR256RegClass);
23755 return std::make_pair(0U, &X86::VR512RegClass);
23761 // Use the default implementation in TargetLowering to convert the register
23762 // constraint into a member of a register class.
23763 std::pair<unsigned, const TargetRegisterClass*> Res;
23764 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
23766 // Not found as a standard register?
23768 // Map st(0) -> st(7) -> ST0
23769 if (Constraint.size() == 7 && Constraint[0] == '{' &&
23770 tolower(Constraint[1]) == 's' &&
23771 tolower(Constraint[2]) == 't' &&
23772 Constraint[3] == '(' &&
23773 (Constraint[4] >= '0' && Constraint[4] <= '7') &&
23774 Constraint[5] == ')' &&
23775 Constraint[6] == '}') {
23777 Res.first = X86::FP0+Constraint[4]-'0';
23778 Res.second = &X86::RFP80RegClass;
23782 // GCC allows "st(0)" to be called just plain "st".
23783 if (StringRef("{st}").equals_lower(Constraint)) {
23784 Res.first = X86::FP0;
23785 Res.second = &X86::RFP80RegClass;
23790 if (StringRef("{flags}").equals_lower(Constraint)) {
23791 Res.first = X86::EFLAGS;
23792 Res.second = &X86::CCRRegClass;
23796 // 'A' means EAX + EDX.
23797 if (Constraint == "A") {
23798 Res.first = X86::EAX;
23799 Res.second = &X86::GR32_ADRegClass;
23805 // Otherwise, check to see if this is a register class of the wrong value
23806 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
23807 // turn into {ax},{dx}.
23808 if (Res.second->hasType(VT))
23809 return Res; // Correct type already, nothing to do.
23811 // All of the single-register GCC register classes map their values onto
23812 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
23813 // really want an 8-bit or 32-bit register, map to the appropriate register
23814 // class and return the appropriate register.
23815 if (Res.second == &X86::GR16RegClass) {
23816 if (VT == MVT::i8 || VT == MVT::i1) {
23817 unsigned DestReg = 0;
23818 switch (Res.first) {
23820 case X86::AX: DestReg = X86::AL; break;
23821 case X86::DX: DestReg = X86::DL; break;
23822 case X86::CX: DestReg = X86::CL; break;
23823 case X86::BX: DestReg = X86::BL; break;
23826 Res.first = DestReg;
23827 Res.second = &X86::GR8RegClass;
23829 } else if (VT == MVT::i32 || VT == MVT::f32) {
23830 unsigned DestReg = 0;
23831 switch (Res.first) {
23833 case X86::AX: DestReg = X86::EAX; break;
23834 case X86::DX: DestReg = X86::EDX; break;
23835 case X86::CX: DestReg = X86::ECX; break;
23836 case X86::BX: DestReg = X86::EBX; break;
23837 case X86::SI: DestReg = X86::ESI; break;
23838 case X86::DI: DestReg = X86::EDI; break;
23839 case X86::BP: DestReg = X86::EBP; break;
23840 case X86::SP: DestReg = X86::ESP; break;
23843 Res.first = DestReg;
23844 Res.second = &X86::GR32RegClass;
23846 } else if (VT == MVT::i64 || VT == MVT::f64) {
23847 unsigned DestReg = 0;
23848 switch (Res.first) {
23850 case X86::AX: DestReg = X86::RAX; break;
23851 case X86::DX: DestReg = X86::RDX; break;
23852 case X86::CX: DestReg = X86::RCX; break;
23853 case X86::BX: DestReg = X86::RBX; break;
23854 case X86::SI: DestReg = X86::RSI; break;
23855 case X86::DI: DestReg = X86::RDI; break;
23856 case X86::BP: DestReg = X86::RBP; break;
23857 case X86::SP: DestReg = X86::RSP; break;
23860 Res.first = DestReg;
23861 Res.second = &X86::GR64RegClass;
23864 } else if (Res.second == &X86::FR32RegClass ||
23865 Res.second == &X86::FR64RegClass ||
23866 Res.second == &X86::VR128RegClass ||
23867 Res.second == &X86::VR256RegClass ||
23868 Res.second == &X86::FR32XRegClass ||
23869 Res.second == &X86::FR64XRegClass ||
23870 Res.second == &X86::VR128XRegClass ||
23871 Res.second == &X86::VR256XRegClass ||
23872 Res.second == &X86::VR512RegClass) {
23873 // Handle references to XMM physical registers that got mapped into the
23874 // wrong class. This can happen with constraints like {xmm0} where the
23875 // target independent register mapper will just pick the first match it can
23876 // find, ignoring the required type.
23878 if (VT == MVT::f32 || VT == MVT::i32)
23879 Res.second = &X86::FR32RegClass;
23880 else if (VT == MVT::f64 || VT == MVT::i64)
23881 Res.second = &X86::FR64RegClass;
23882 else if (X86::VR128RegClass.hasType(VT))
23883 Res.second = &X86::VR128RegClass;
23884 else if (X86::VR256RegClass.hasType(VT))
23885 Res.second = &X86::VR256RegClass;
23886 else if (X86::VR512RegClass.hasType(VT))
23887 Res.second = &X86::VR512RegClass;
23893 int X86TargetLowering::getScalingFactorCost(const AddrMode &AM,
23895 // Scaling factors are not free at all.
23896 // An indexed folded instruction, i.e., inst (reg1, reg2, scale),
23897 // will take 2 allocations in the out of order engine instead of 1
23898 // for plain addressing mode, i.e. inst (reg1).
23900 // vaddps (%rsi,%drx), %ymm0, %ymm1
23901 // Requires two allocations (one for the load, one for the computation)
23903 // vaddps (%rsi), %ymm0, %ymm1
23904 // Requires just 1 allocation, i.e., freeing allocations for other operations
23905 // and having less micro operations to execute.
23907 // For some X86 architectures, this is even worse because for instance for
23908 // stores, the complex addressing mode forces the instruction to use the
23909 // "load" ports instead of the dedicated "store" port.
23910 // E.g., on Haswell:
23911 // vmovaps %ymm1, (%r8, %rdi) can use port 2 or 3.
23912 // vmovaps %ymm1, (%r8) can use port 2, 3, or 7.
23913 if (isLegalAddressingMode(AM, Ty))
23914 // Scale represents reg2 * scale, thus account for 1
23915 // as soon as we use a second register.
23916 return AM.Scale != 0;
23920 bool X86TargetLowering::isTargetFTOL() const {
23921 return Subtarget->isTargetKnownWindowsMSVC() && !Subtarget->is64Bit();