1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
16 #include "X86InstrBuilder.h"
17 #include "X86ISelLowering.h"
18 #include "X86TargetMachine.h"
19 #include "X86TargetObjectFile.h"
20 #include "llvm/CallingConv.h"
21 #include "llvm/Constants.h"
22 #include "llvm/DerivedTypes.h"
23 #include "llvm/GlobalAlias.h"
24 #include "llvm/GlobalVariable.h"
25 #include "llvm/Function.h"
26 #include "llvm/Instructions.h"
27 #include "llvm/Intrinsics.h"
28 #include "llvm/LLVMContext.h"
29 #include "llvm/ADT/BitVector.h"
30 #include "llvm/ADT/VectorExtras.h"
31 #include "llvm/CodeGen/MachineFrameInfo.h"
32 #include "llvm/CodeGen/MachineFunction.h"
33 #include "llvm/CodeGen/MachineInstrBuilder.h"
34 #include "llvm/CodeGen/MachineModuleInfo.h"
35 #include "llvm/CodeGen/MachineRegisterInfo.h"
36 #include "llvm/CodeGen/PseudoSourceValue.h"
37 #include "llvm/Support/MathExtras.h"
38 #include "llvm/Support/Debug.h"
39 #include "llvm/Support/ErrorHandling.h"
40 #include "llvm/Target/TargetOptions.h"
41 #include "llvm/ADT/SmallSet.h"
42 #include "llvm/ADT/StringExtras.h"
43 #include "llvm/Support/CommandLine.h"
44 #include "llvm/Support/raw_ostream.h"
48 DisableMMX("disable-mmx", cl::Hidden, cl::desc("Disable use of MMX"));
50 // Disable16Bit - 16-bit operations typically have a larger encoding than
51 // corresponding 32-bit instructions, and 16-bit code is slow on some
52 // processors. This is an experimental flag to disable 16-bit operations
53 // (which forces them to be Legalized to 32-bit operations).
55 Disable16Bit("disable-16bit", cl::Hidden,
56 cl::desc("Disable use of 16-bit instructions"));
58 // Forward declarations.
59 static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
62 static TargetLoweringObjectFile *createTLOF(X86TargetMachine &TM) {
63 switch (TM.getSubtarget<X86Subtarget>().TargetType) {
64 default: llvm_unreachable("unknown subtarget type");
65 case X86Subtarget::isDarwin:
66 if (TM.getSubtarget<X86Subtarget>().is64Bit())
67 return new X8664_MachoTargetObjectFile();
68 return new X8632_MachoTargetObjectFile();
69 case X86Subtarget::isELF:
70 return new TargetLoweringObjectFileELF();
71 case X86Subtarget::isMingw:
72 case X86Subtarget::isCygwin:
73 case X86Subtarget::isWindows:
74 return new TargetLoweringObjectFileCOFF();
79 X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
80 : TargetLowering(TM, createTLOF(TM)) {
81 Subtarget = &TM.getSubtarget<X86Subtarget>();
82 X86ScalarSSEf64 = Subtarget->hasSSE2();
83 X86ScalarSSEf32 = Subtarget->hasSSE1();
84 X86StackPtr = Subtarget->is64Bit() ? X86::RSP : X86::ESP;
86 RegInfo = TM.getRegisterInfo();
89 // Set up the TargetLowering object.
91 // X86 is weird, it always uses i8 for shift amounts and setcc results.
92 setShiftAmountType(MVT::i8);
93 setBooleanContents(ZeroOrOneBooleanContent);
94 setSchedulingPreference(SchedulingForRegPressure);
95 setStackPointerRegisterToSaveRestore(X86StackPtr);
97 if (Subtarget->isTargetDarwin()) {
98 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
99 setUseUnderscoreSetJmp(false);
100 setUseUnderscoreLongJmp(false);
101 } else if (Subtarget->isTargetMingw()) {
102 // MS runtime is weird: it exports _setjmp, but longjmp!
103 setUseUnderscoreSetJmp(true);
104 setUseUnderscoreLongJmp(false);
106 setUseUnderscoreSetJmp(true);
107 setUseUnderscoreLongJmp(true);
110 // Set up the register classes.
111 addRegisterClass(MVT::i8, X86::GR8RegisterClass);
113 addRegisterClass(MVT::i16, X86::GR16RegisterClass);
114 addRegisterClass(MVT::i32, X86::GR32RegisterClass);
115 if (Subtarget->is64Bit())
116 addRegisterClass(MVT::i64, X86::GR64RegisterClass);
118 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
120 // We don't accept any truncstore of integer registers.
121 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
123 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
124 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
126 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
127 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
128 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
130 // SETOEQ and SETUNE require checking two conditions.
131 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
132 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
133 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
134 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
135 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
136 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
138 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
140 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
141 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
142 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
144 if (Subtarget->is64Bit()) {
145 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
146 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Expand);
147 } else if (!UseSoftFloat) {
148 if (X86ScalarSSEf64) {
149 // We have an impenetrably clever algorithm for ui64->double only.
150 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
152 // We have an algorithm for SSE2, and we turn this into a 64-bit
153 // FILD for other targets.
154 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
157 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
159 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
160 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
163 // SSE has no i16 to fp conversion, only i32
164 if (X86ScalarSSEf32) {
165 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
166 // f32 and f64 cases are Legal, f80 case is not
167 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
169 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
170 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
173 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
174 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
177 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
178 // are Legal, f80 is custom lowered.
179 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
180 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
182 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
184 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
185 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
187 if (X86ScalarSSEf32) {
188 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
189 // f32 and f64 cases are Legal, f80 case is not
190 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
192 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
193 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
196 // Handle FP_TO_UINT by promoting the destination to a larger signed
198 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
199 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
200 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
202 if (Subtarget->is64Bit()) {
203 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
204 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
205 } else if (!UseSoftFloat) {
206 if (X86ScalarSSEf32 && !Subtarget->hasSSE3())
207 // Expand FP_TO_UINT into a select.
208 // FIXME: We would like to use a Custom expander here eventually to do
209 // the optimal thing for SSE vs. the default expansion in the legalizer.
210 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
212 // With SSE3 we can use fisttpll to convert to a signed i64; without
213 // SSE, we're stuck with a fistpll.
214 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
217 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
218 if (!X86ScalarSSEf64) {
219 setOperationAction(ISD::BIT_CONVERT , MVT::f32 , Expand);
220 setOperationAction(ISD::BIT_CONVERT , MVT::i32 , Expand);
223 // Scalar integer divide and remainder are lowered to use operations that
224 // produce two results, to match the available instructions. This exposes
225 // the two-result form to trivial CSE, which is able to combine x/y and x%y
226 // into a single instruction.
228 // Scalar integer multiply-high is also lowered to use two-result
229 // operations, to match the available instructions. However, plain multiply
230 // (low) operations are left as Legal, as there are single-result
231 // instructions for this in x86. Using the two-result multiply instructions
232 // when both high and low results are needed must be arranged by dagcombine.
233 setOperationAction(ISD::MULHS , MVT::i8 , Expand);
234 setOperationAction(ISD::MULHU , MVT::i8 , Expand);
235 setOperationAction(ISD::SDIV , MVT::i8 , Expand);
236 setOperationAction(ISD::UDIV , MVT::i8 , Expand);
237 setOperationAction(ISD::SREM , MVT::i8 , Expand);
238 setOperationAction(ISD::UREM , MVT::i8 , Expand);
239 setOperationAction(ISD::MULHS , MVT::i16 , Expand);
240 setOperationAction(ISD::MULHU , MVT::i16 , Expand);
241 setOperationAction(ISD::SDIV , MVT::i16 , Expand);
242 setOperationAction(ISD::UDIV , MVT::i16 , Expand);
243 setOperationAction(ISD::SREM , MVT::i16 , Expand);
244 setOperationAction(ISD::UREM , MVT::i16 , Expand);
245 setOperationAction(ISD::MULHS , MVT::i32 , Expand);
246 setOperationAction(ISD::MULHU , MVT::i32 , Expand);
247 setOperationAction(ISD::SDIV , MVT::i32 , Expand);
248 setOperationAction(ISD::UDIV , MVT::i32 , Expand);
249 setOperationAction(ISD::SREM , MVT::i32 , Expand);
250 setOperationAction(ISD::UREM , MVT::i32 , Expand);
251 setOperationAction(ISD::MULHS , MVT::i64 , Expand);
252 setOperationAction(ISD::MULHU , MVT::i64 , Expand);
253 setOperationAction(ISD::SDIV , MVT::i64 , Expand);
254 setOperationAction(ISD::UDIV , MVT::i64 , Expand);
255 setOperationAction(ISD::SREM , MVT::i64 , Expand);
256 setOperationAction(ISD::UREM , MVT::i64 , Expand);
258 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
259 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
260 setOperationAction(ISD::BR_CC , MVT::Other, Expand);
261 setOperationAction(ISD::SELECT_CC , MVT::Other, Expand);
262 if (Subtarget->is64Bit())
263 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
264 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
265 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
266 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
267 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
268 setOperationAction(ISD::FREM , MVT::f32 , Expand);
269 setOperationAction(ISD::FREM , MVT::f64 , Expand);
270 setOperationAction(ISD::FREM , MVT::f80 , Expand);
271 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
273 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
274 setOperationAction(ISD::CTTZ , MVT::i8 , Custom);
275 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
276 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
278 setOperationAction(ISD::CTTZ , MVT::i16 , Expand);
279 setOperationAction(ISD::CTLZ , MVT::i16 , Expand);
281 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
282 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
284 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
285 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
286 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
287 if (Subtarget->is64Bit()) {
288 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
289 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
290 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
293 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
294 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
296 // These should be promoted to a larger select which is supported.
297 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
298 // X86 wants to expand cmov itself.
299 setOperationAction(ISD::SELECT , MVT::i8 , Custom);
301 setOperationAction(ISD::SELECT , MVT::i16 , Expand);
303 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
304 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
305 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
306 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
307 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
308 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
310 setOperationAction(ISD::SETCC , MVT::i16 , Expand);
312 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
313 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
314 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
315 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
316 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
317 if (Subtarget->is64Bit()) {
318 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
319 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
321 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
324 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
325 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
326 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
327 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
328 if (Subtarget->is64Bit())
329 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
330 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
331 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom);
332 if (Subtarget->is64Bit()) {
333 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
334 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
335 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
336 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
337 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom);
339 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
340 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
341 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
342 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
343 if (Subtarget->is64Bit()) {
344 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
345 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
346 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
349 if (Subtarget->hasSSE1())
350 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
352 if (!Subtarget->hasSSE2())
353 setOperationAction(ISD::MEMBARRIER , MVT::Other, Expand);
355 // Expand certain atomics
356 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i8, Custom);
357 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i16, Custom);
358 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Custom);
359 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i64, Custom);
361 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i8, Custom);
362 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i16, Custom);
363 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i32, Custom);
364 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom);
366 if (!Subtarget->is64Bit()) {
367 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i64, Custom);
368 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom);
369 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i64, Custom);
370 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i64, Custom);
371 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i64, Custom);
372 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i64, Custom);
373 setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Custom);
376 // FIXME - use subtarget debug flags
377 if (!Subtarget->isTargetDarwin() &&
378 !Subtarget->isTargetELF() &&
379 !Subtarget->isTargetCygMing()) {
380 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
383 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand);
384 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand);
385 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
386 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
387 if (Subtarget->is64Bit()) {
388 setExceptionPointerRegister(X86::RAX);
389 setExceptionSelectorRegister(X86::RDX);
391 setExceptionPointerRegister(X86::EAX);
392 setExceptionSelectorRegister(X86::EDX);
394 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
395 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
397 setOperationAction(ISD::TRAMPOLINE, MVT::Other, Custom);
399 setOperationAction(ISD::TRAP, MVT::Other, Legal);
401 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
402 setOperationAction(ISD::VASTART , MVT::Other, Custom);
403 setOperationAction(ISD::VAEND , MVT::Other, Expand);
404 if (Subtarget->is64Bit()) {
405 setOperationAction(ISD::VAARG , MVT::Other, Custom);
406 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
408 setOperationAction(ISD::VAARG , MVT::Other, Expand);
409 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
412 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
413 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
414 if (Subtarget->is64Bit())
415 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand);
416 if (Subtarget->isTargetCygMing())
417 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom);
419 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
421 if (!UseSoftFloat && X86ScalarSSEf64) {
422 // f32 and f64 use SSE.
423 // Set up the FP register classes.
424 addRegisterClass(MVT::f32, X86::FR32RegisterClass);
425 addRegisterClass(MVT::f64, X86::FR64RegisterClass);
427 // Use ANDPD to simulate FABS.
428 setOperationAction(ISD::FABS , MVT::f64, Custom);
429 setOperationAction(ISD::FABS , MVT::f32, Custom);
431 // Use XORP to simulate FNEG.
432 setOperationAction(ISD::FNEG , MVT::f64, Custom);
433 setOperationAction(ISD::FNEG , MVT::f32, Custom);
435 // Use ANDPD and ORPD to simulate FCOPYSIGN.
436 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
437 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
439 // We don't support sin/cos/fmod
440 setOperationAction(ISD::FSIN , MVT::f64, Expand);
441 setOperationAction(ISD::FCOS , MVT::f64, Expand);
442 setOperationAction(ISD::FSIN , MVT::f32, Expand);
443 setOperationAction(ISD::FCOS , MVT::f32, Expand);
445 // Expand FP immediates into loads from the stack, except for the special
447 addLegalFPImmediate(APFloat(+0.0)); // xorpd
448 addLegalFPImmediate(APFloat(+0.0f)); // xorps
449 } else if (!UseSoftFloat && X86ScalarSSEf32) {
450 // Use SSE for f32, x87 for f64.
451 // Set up the FP register classes.
452 addRegisterClass(MVT::f32, X86::FR32RegisterClass);
453 addRegisterClass(MVT::f64, X86::RFP64RegisterClass);
455 // Use ANDPS to simulate FABS.
456 setOperationAction(ISD::FABS , MVT::f32, Custom);
458 // Use XORP to simulate FNEG.
459 setOperationAction(ISD::FNEG , MVT::f32, Custom);
461 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
463 // Use ANDPS and ORPS to simulate FCOPYSIGN.
464 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
465 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
467 // We don't support sin/cos/fmod
468 setOperationAction(ISD::FSIN , MVT::f32, Expand);
469 setOperationAction(ISD::FCOS , MVT::f32, Expand);
471 // Special cases we handle for FP constants.
472 addLegalFPImmediate(APFloat(+0.0f)); // xorps
473 addLegalFPImmediate(APFloat(+0.0)); // FLD0
474 addLegalFPImmediate(APFloat(+1.0)); // FLD1
475 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
476 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
479 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
480 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
482 } else if (!UseSoftFloat) {
483 // f32 and f64 in x87.
484 // Set up the FP register classes.
485 addRegisterClass(MVT::f64, X86::RFP64RegisterClass);
486 addRegisterClass(MVT::f32, X86::RFP32RegisterClass);
488 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
489 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
490 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
491 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
494 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
495 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
497 addLegalFPImmediate(APFloat(+0.0)); // FLD0
498 addLegalFPImmediate(APFloat(+1.0)); // FLD1
499 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
500 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
501 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
502 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
503 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
504 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
507 // Long double always uses X87.
509 addRegisterClass(MVT::f80, X86::RFP80RegisterClass);
510 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
511 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
514 APFloat TmpFlt(+0.0);
515 TmpFlt.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
517 addLegalFPImmediate(TmpFlt); // FLD0
519 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
520 APFloat TmpFlt2(+1.0);
521 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
523 addLegalFPImmediate(TmpFlt2); // FLD1
524 TmpFlt2.changeSign();
525 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
529 setOperationAction(ISD::FSIN , MVT::f80 , Expand);
530 setOperationAction(ISD::FCOS , MVT::f80 , Expand);
534 // Always use a library call for pow.
535 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
536 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
537 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
539 setOperationAction(ISD::FLOG, MVT::f80, Expand);
540 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
541 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
542 setOperationAction(ISD::FEXP, MVT::f80, Expand);
543 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
545 // First set operation action for all vector types to either promote
546 // (for widening) or expand (for scalarization). Then we will selectively
547 // turn on ones that can be effectively codegen'd.
548 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
549 VT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) {
550 setOperationAction(ISD::ADD , (MVT::SimpleValueType)VT, Expand);
551 setOperationAction(ISD::SUB , (MVT::SimpleValueType)VT, Expand);
552 setOperationAction(ISD::FADD, (MVT::SimpleValueType)VT, Expand);
553 setOperationAction(ISD::FNEG, (MVT::SimpleValueType)VT, Expand);
554 setOperationAction(ISD::FSUB, (MVT::SimpleValueType)VT, Expand);
555 setOperationAction(ISD::MUL , (MVT::SimpleValueType)VT, Expand);
556 setOperationAction(ISD::FMUL, (MVT::SimpleValueType)VT, Expand);
557 setOperationAction(ISD::SDIV, (MVT::SimpleValueType)VT, Expand);
558 setOperationAction(ISD::UDIV, (MVT::SimpleValueType)VT, Expand);
559 setOperationAction(ISD::FDIV, (MVT::SimpleValueType)VT, Expand);
560 setOperationAction(ISD::SREM, (MVT::SimpleValueType)VT, Expand);
561 setOperationAction(ISD::UREM, (MVT::SimpleValueType)VT, Expand);
562 setOperationAction(ISD::LOAD, (MVT::SimpleValueType)VT, Expand);
563 setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::SimpleValueType)VT, Expand);
564 setOperationAction(ISD::EXTRACT_VECTOR_ELT,(MVT::SimpleValueType)VT,Expand);
565 setOperationAction(ISD::EXTRACT_SUBVECTOR,(MVT::SimpleValueType)VT,Expand);
566 setOperationAction(ISD::INSERT_VECTOR_ELT,(MVT::SimpleValueType)VT, Expand);
567 setOperationAction(ISD::FABS, (MVT::SimpleValueType)VT, Expand);
568 setOperationAction(ISD::FSIN, (MVT::SimpleValueType)VT, Expand);
569 setOperationAction(ISD::FCOS, (MVT::SimpleValueType)VT, Expand);
570 setOperationAction(ISD::FREM, (MVT::SimpleValueType)VT, Expand);
571 setOperationAction(ISD::FPOWI, (MVT::SimpleValueType)VT, Expand);
572 setOperationAction(ISD::FSQRT, (MVT::SimpleValueType)VT, Expand);
573 setOperationAction(ISD::FCOPYSIGN, (MVT::SimpleValueType)VT, Expand);
574 setOperationAction(ISD::SMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
575 setOperationAction(ISD::UMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
576 setOperationAction(ISD::SDIVREM, (MVT::SimpleValueType)VT, Expand);
577 setOperationAction(ISD::UDIVREM, (MVT::SimpleValueType)VT, Expand);
578 setOperationAction(ISD::FPOW, (MVT::SimpleValueType)VT, Expand);
579 setOperationAction(ISD::CTPOP, (MVT::SimpleValueType)VT, Expand);
580 setOperationAction(ISD::CTTZ, (MVT::SimpleValueType)VT, Expand);
581 setOperationAction(ISD::CTLZ, (MVT::SimpleValueType)VT, Expand);
582 setOperationAction(ISD::SHL, (MVT::SimpleValueType)VT, Expand);
583 setOperationAction(ISD::SRA, (MVT::SimpleValueType)VT, Expand);
584 setOperationAction(ISD::SRL, (MVT::SimpleValueType)VT, Expand);
585 setOperationAction(ISD::ROTL, (MVT::SimpleValueType)VT, Expand);
586 setOperationAction(ISD::ROTR, (MVT::SimpleValueType)VT, Expand);
587 setOperationAction(ISD::BSWAP, (MVT::SimpleValueType)VT, Expand);
588 setOperationAction(ISD::VSETCC, (MVT::SimpleValueType)VT, Expand);
589 setOperationAction(ISD::FLOG, (MVT::SimpleValueType)VT, Expand);
590 setOperationAction(ISD::FLOG2, (MVT::SimpleValueType)VT, Expand);
591 setOperationAction(ISD::FLOG10, (MVT::SimpleValueType)VT, Expand);
592 setOperationAction(ISD::FEXP, (MVT::SimpleValueType)VT, Expand);
593 setOperationAction(ISD::FEXP2, (MVT::SimpleValueType)VT, Expand);
594 setOperationAction(ISD::FP_TO_UINT, (MVT::SimpleValueType)VT, Expand);
595 setOperationAction(ISD::FP_TO_SINT, (MVT::SimpleValueType)VT, Expand);
596 setOperationAction(ISD::UINT_TO_FP, (MVT::SimpleValueType)VT, Expand);
597 setOperationAction(ISD::SINT_TO_FP, (MVT::SimpleValueType)VT, Expand);
598 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,Expand);
599 setOperationAction(ISD::TRUNCATE, (MVT::SimpleValueType)VT, Expand);
600 setOperationAction(ISD::SIGN_EXTEND, (MVT::SimpleValueType)VT, Expand);
601 setOperationAction(ISD::ZERO_EXTEND, (MVT::SimpleValueType)VT, Expand);
602 setOperationAction(ISD::ANY_EXTEND, (MVT::SimpleValueType)VT, Expand);
603 for (unsigned InnerVT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
604 InnerVT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++InnerVT)
605 setTruncStoreAction((MVT::SimpleValueType)VT,
606 (MVT::SimpleValueType)InnerVT, Expand);
607 setLoadExtAction(ISD::SEXTLOAD, (MVT::SimpleValueType)VT, Expand);
608 setLoadExtAction(ISD::ZEXTLOAD, (MVT::SimpleValueType)VT, Expand);
609 setLoadExtAction(ISD::EXTLOAD, (MVT::SimpleValueType)VT, Expand);
612 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
613 // with -msoft-float, disable use of MMX as well.
614 if (!UseSoftFloat && !DisableMMX && Subtarget->hasMMX()) {
615 addRegisterClass(MVT::v8i8, X86::VR64RegisterClass);
616 addRegisterClass(MVT::v4i16, X86::VR64RegisterClass);
617 addRegisterClass(MVT::v2i32, X86::VR64RegisterClass);
618 addRegisterClass(MVT::v2f32, X86::VR64RegisterClass);
619 addRegisterClass(MVT::v1i64, X86::VR64RegisterClass);
621 setOperationAction(ISD::ADD, MVT::v8i8, Legal);
622 setOperationAction(ISD::ADD, MVT::v4i16, Legal);
623 setOperationAction(ISD::ADD, MVT::v2i32, Legal);
624 setOperationAction(ISD::ADD, MVT::v1i64, Legal);
626 setOperationAction(ISD::SUB, MVT::v8i8, Legal);
627 setOperationAction(ISD::SUB, MVT::v4i16, Legal);
628 setOperationAction(ISD::SUB, MVT::v2i32, Legal);
629 setOperationAction(ISD::SUB, MVT::v1i64, Legal);
631 setOperationAction(ISD::MULHS, MVT::v4i16, Legal);
632 setOperationAction(ISD::MUL, MVT::v4i16, Legal);
634 setOperationAction(ISD::AND, MVT::v8i8, Promote);
635 AddPromotedToType (ISD::AND, MVT::v8i8, MVT::v1i64);
636 setOperationAction(ISD::AND, MVT::v4i16, Promote);
637 AddPromotedToType (ISD::AND, MVT::v4i16, MVT::v1i64);
638 setOperationAction(ISD::AND, MVT::v2i32, Promote);
639 AddPromotedToType (ISD::AND, MVT::v2i32, MVT::v1i64);
640 setOperationAction(ISD::AND, MVT::v1i64, Legal);
642 setOperationAction(ISD::OR, MVT::v8i8, Promote);
643 AddPromotedToType (ISD::OR, MVT::v8i8, MVT::v1i64);
644 setOperationAction(ISD::OR, MVT::v4i16, Promote);
645 AddPromotedToType (ISD::OR, MVT::v4i16, MVT::v1i64);
646 setOperationAction(ISD::OR, MVT::v2i32, Promote);
647 AddPromotedToType (ISD::OR, MVT::v2i32, MVT::v1i64);
648 setOperationAction(ISD::OR, MVT::v1i64, Legal);
650 setOperationAction(ISD::XOR, MVT::v8i8, Promote);
651 AddPromotedToType (ISD::XOR, MVT::v8i8, MVT::v1i64);
652 setOperationAction(ISD::XOR, MVT::v4i16, Promote);
653 AddPromotedToType (ISD::XOR, MVT::v4i16, MVT::v1i64);
654 setOperationAction(ISD::XOR, MVT::v2i32, Promote);
655 AddPromotedToType (ISD::XOR, MVT::v2i32, MVT::v1i64);
656 setOperationAction(ISD::XOR, MVT::v1i64, Legal);
658 setOperationAction(ISD::LOAD, MVT::v8i8, Promote);
659 AddPromotedToType (ISD::LOAD, MVT::v8i8, MVT::v1i64);
660 setOperationAction(ISD::LOAD, MVT::v4i16, Promote);
661 AddPromotedToType (ISD::LOAD, MVT::v4i16, MVT::v1i64);
662 setOperationAction(ISD::LOAD, MVT::v2i32, Promote);
663 AddPromotedToType (ISD::LOAD, MVT::v2i32, MVT::v1i64);
664 setOperationAction(ISD::LOAD, MVT::v2f32, Promote);
665 AddPromotedToType (ISD::LOAD, MVT::v2f32, MVT::v1i64);
666 setOperationAction(ISD::LOAD, MVT::v1i64, Legal);
668 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i8, Custom);
669 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i16, Custom);
670 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i32, Custom);
671 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f32, Custom);
672 setOperationAction(ISD::BUILD_VECTOR, MVT::v1i64, Custom);
674 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i8, Custom);
675 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i16, Custom);
676 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i32, Custom);
677 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v1i64, Custom);
679 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2f32, Custom);
680 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Custom);
681 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Custom);
682 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Custom);
684 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i16, Custom);
686 setOperationAction(ISD::SELECT, MVT::v8i8, Promote);
687 setOperationAction(ISD::SELECT, MVT::v4i16, Promote);
688 setOperationAction(ISD::SELECT, MVT::v2i32, Promote);
689 setOperationAction(ISD::SELECT, MVT::v1i64, Custom);
690 setOperationAction(ISD::VSETCC, MVT::v8i8, Custom);
691 setOperationAction(ISD::VSETCC, MVT::v4i16, Custom);
692 setOperationAction(ISD::VSETCC, MVT::v2i32, Custom);
695 if (!UseSoftFloat && Subtarget->hasSSE1()) {
696 addRegisterClass(MVT::v4f32, X86::VR128RegisterClass);
698 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
699 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
700 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
701 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
702 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
703 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
704 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
705 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
706 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
707 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
708 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
709 setOperationAction(ISD::VSETCC, MVT::v4f32, Custom);
712 if (!UseSoftFloat && Subtarget->hasSSE2()) {
713 addRegisterClass(MVT::v2f64, X86::VR128RegisterClass);
715 // FIXME: Unfortunately -soft-float and -no-implicit-float means XMM
716 // registers cannot be used even for integer operations.
717 addRegisterClass(MVT::v16i8, X86::VR128RegisterClass);
718 addRegisterClass(MVT::v8i16, X86::VR128RegisterClass);
719 addRegisterClass(MVT::v4i32, X86::VR128RegisterClass);
720 addRegisterClass(MVT::v2i64, X86::VR128RegisterClass);
722 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
723 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
724 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
725 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
726 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
727 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
728 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
729 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
730 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
731 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
732 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
733 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
734 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
735 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
736 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
737 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
739 setOperationAction(ISD::VSETCC, MVT::v2f64, Custom);
740 setOperationAction(ISD::VSETCC, MVT::v16i8, Custom);
741 setOperationAction(ISD::VSETCC, MVT::v8i16, Custom);
742 setOperationAction(ISD::VSETCC, MVT::v4i32, Custom);
744 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
745 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
746 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
747 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
748 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
750 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
751 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; ++i) {
752 EVT VT = (MVT::SimpleValueType)i;
753 // Do not attempt to custom lower non-power-of-2 vectors
754 if (!isPowerOf2_32(VT.getVectorNumElements()))
756 // Do not attempt to custom lower non-128-bit vectors
757 if (!VT.is128BitVector())
759 setOperationAction(ISD::BUILD_VECTOR,
760 VT.getSimpleVT().SimpleTy, Custom);
761 setOperationAction(ISD::VECTOR_SHUFFLE,
762 VT.getSimpleVT().SimpleTy, Custom);
763 setOperationAction(ISD::EXTRACT_VECTOR_ELT,
764 VT.getSimpleVT().SimpleTy, Custom);
767 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
768 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
769 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
770 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
771 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
772 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
774 if (Subtarget->is64Bit()) {
775 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
776 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
779 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
780 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; i++) {
781 MVT::SimpleValueType SVT = (MVT::SimpleValueType)i;
784 // Do not attempt to promote non-128-bit vectors
785 if (!VT.is128BitVector()) {
788 setOperationAction(ISD::AND, SVT, Promote);
789 AddPromotedToType (ISD::AND, SVT, MVT::v2i64);
790 setOperationAction(ISD::OR, SVT, Promote);
791 AddPromotedToType (ISD::OR, SVT, MVT::v2i64);
792 setOperationAction(ISD::XOR, SVT, Promote);
793 AddPromotedToType (ISD::XOR, SVT, MVT::v2i64);
794 setOperationAction(ISD::LOAD, SVT, Promote);
795 AddPromotedToType (ISD::LOAD, SVT, MVT::v2i64);
796 setOperationAction(ISD::SELECT, SVT, Promote);
797 AddPromotedToType (ISD::SELECT, SVT, MVT::v2i64);
800 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
802 // Custom lower v2i64 and v2f64 selects.
803 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
804 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
805 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
806 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
808 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
809 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
810 if (!DisableMMX && Subtarget->hasMMX()) {
811 setOperationAction(ISD::FP_TO_SINT, MVT::v2i32, Custom);
812 setOperationAction(ISD::SINT_TO_FP, MVT::v2i32, Custom);
816 if (Subtarget->hasSSE41()) {
817 // FIXME: Do we need to handle scalar-to-vector here?
818 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
820 // i8 and i16 vectors are custom , because the source register and source
821 // source memory operand types are not the same width. f32 vectors are
822 // custom since the immediate controlling the insert encodes additional
824 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
825 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
826 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
827 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
829 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
830 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
831 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
832 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
834 if (Subtarget->is64Bit()) {
835 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Legal);
836 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Legal);
840 if (Subtarget->hasSSE42()) {
841 setOperationAction(ISD::VSETCC, MVT::v2i64, Custom);
844 if (!UseSoftFloat && Subtarget->hasAVX()) {
845 addRegisterClass(MVT::v8f32, X86::VR256RegisterClass);
846 addRegisterClass(MVT::v4f64, X86::VR256RegisterClass);
847 addRegisterClass(MVT::v8i32, X86::VR256RegisterClass);
848 addRegisterClass(MVT::v4i64, X86::VR256RegisterClass);
850 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
851 setOperationAction(ISD::LOAD, MVT::v8i32, Legal);
852 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
853 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
854 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
855 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
856 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
857 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
858 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
859 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
860 //setOperationAction(ISD::BUILD_VECTOR, MVT::v8f32, Custom);
861 //setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8f32, Custom);
862 //setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8f32, Custom);
863 //setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
864 //setOperationAction(ISD::VSETCC, MVT::v8f32, Custom);
866 // Operations to consider commented out -v16i16 v32i8
867 //setOperationAction(ISD::ADD, MVT::v16i16, Legal);
868 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
869 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
870 //setOperationAction(ISD::SUB, MVT::v32i8, Legal);
871 //setOperationAction(ISD::SUB, MVT::v16i16, Legal);
872 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
873 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
874 //setOperationAction(ISD::MUL, MVT::v16i16, Legal);
875 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
876 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
877 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
878 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
879 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
880 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
882 setOperationAction(ISD::VSETCC, MVT::v4f64, Custom);
883 // setOperationAction(ISD::VSETCC, MVT::v32i8, Custom);
884 // setOperationAction(ISD::VSETCC, MVT::v16i16, Custom);
885 setOperationAction(ISD::VSETCC, MVT::v8i32, Custom);
887 // setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v32i8, Custom);
888 // setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i16, Custom);
889 // setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i16, Custom);
890 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i32, Custom);
891 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8f32, Custom);
893 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f64, Custom);
894 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i64, Custom);
895 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f64, Custom);
896 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i64, Custom);
897 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f64, Custom);
898 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f64, Custom);
901 // Not sure we want to do this since there are no 256-bit integer
904 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
905 // This includes 256-bit vectors
906 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v4i64; ++i) {
907 EVT VT = (MVT::SimpleValueType)i;
909 // Do not attempt to custom lower non-power-of-2 vectors
910 if (!isPowerOf2_32(VT.getVectorNumElements()))
913 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
914 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
915 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
918 if (Subtarget->is64Bit()) {
919 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i64, Custom);
920 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i64, Custom);
925 // Not sure we want to do this since there are no 256-bit integer
928 // Promote v32i8, v16i16, v8i32 load, select, and, or, xor to v4i64.
929 // Including 256-bit vectors
930 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v4i64; i++) {
931 EVT VT = (MVT::SimpleValueType)i;
933 if (!VT.is256BitVector()) {
936 setOperationAction(ISD::AND, VT, Promote);
937 AddPromotedToType (ISD::AND, VT, MVT::v4i64);
938 setOperationAction(ISD::OR, VT, Promote);
939 AddPromotedToType (ISD::OR, VT, MVT::v4i64);
940 setOperationAction(ISD::XOR, VT, Promote);
941 AddPromotedToType (ISD::XOR, VT, MVT::v4i64);
942 setOperationAction(ISD::LOAD, VT, Promote);
943 AddPromotedToType (ISD::LOAD, VT, MVT::v4i64);
944 setOperationAction(ISD::SELECT, VT, Promote);
945 AddPromotedToType (ISD::SELECT, VT, MVT::v4i64);
948 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
952 // We want to custom lower some of our intrinsics.
953 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
955 // Add/Sub/Mul with overflow operations are custom lowered.
956 setOperationAction(ISD::SADDO, MVT::i32, Custom);
957 setOperationAction(ISD::SADDO, MVT::i64, Custom);
958 setOperationAction(ISD::UADDO, MVT::i32, Custom);
959 setOperationAction(ISD::UADDO, MVT::i64, Custom);
960 setOperationAction(ISD::SSUBO, MVT::i32, Custom);
961 setOperationAction(ISD::SSUBO, MVT::i64, Custom);
962 setOperationAction(ISD::USUBO, MVT::i32, Custom);
963 setOperationAction(ISD::USUBO, MVT::i64, Custom);
964 setOperationAction(ISD::SMULO, MVT::i32, Custom);
965 setOperationAction(ISD::SMULO, MVT::i64, Custom);
967 if (!Subtarget->is64Bit()) {
968 // These libcalls are not available in 32-bit.
969 setLibcallName(RTLIB::SHL_I128, 0);
970 setLibcallName(RTLIB::SRL_I128, 0);
971 setLibcallName(RTLIB::SRA_I128, 0);
974 // We have target-specific dag combine patterns for the following nodes:
975 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
976 setTargetDAGCombine(ISD::BUILD_VECTOR);
977 setTargetDAGCombine(ISD::SELECT);
978 setTargetDAGCombine(ISD::SHL);
979 setTargetDAGCombine(ISD::SRA);
980 setTargetDAGCombine(ISD::SRL);
981 setTargetDAGCombine(ISD::STORE);
982 setTargetDAGCombine(ISD::MEMBARRIER);
983 setTargetDAGCombine(ISD::ZERO_EXTEND);
984 if (Subtarget->is64Bit())
985 setTargetDAGCombine(ISD::MUL);
987 computeRegisterProperties();
989 // Divide and reminder operations have no vector equivalent and can
990 // trap. Do a custom widening for these operations in which we never
991 // generate more divides/remainder than the original vector width.
992 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
993 VT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) {
994 if (!isTypeLegal((MVT::SimpleValueType)VT)) {
995 setOperationAction(ISD::SDIV, (MVT::SimpleValueType) VT, Custom);
996 setOperationAction(ISD::UDIV, (MVT::SimpleValueType) VT, Custom);
997 setOperationAction(ISD::SREM, (MVT::SimpleValueType) VT, Custom);
998 setOperationAction(ISD::UREM, (MVT::SimpleValueType) VT, Custom);
1002 // FIXME: These should be based on subtarget info. Plus, the values should
1003 // be smaller when we are in optimizing for size mode.
1004 maxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
1005 maxStoresPerMemcpy = 16; // For @llvm.memcpy -> sequence of stores
1006 maxStoresPerMemmove = 3; // For @llvm.memmove -> sequence of stores
1007 setPrefLoopAlignment(16);
1008 benefitFromCodePlacementOpt = true;
1012 MVT::SimpleValueType X86TargetLowering::getSetCCResultType(EVT VT) const {
1017 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
1018 /// the desired ByVal argument alignment.
1019 static void getMaxByValAlign(const Type *Ty, unsigned &MaxAlign) {
1022 if (const VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1023 if (VTy->getBitWidth() == 128)
1025 } else if (const ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1026 unsigned EltAlign = 0;
1027 getMaxByValAlign(ATy->getElementType(), EltAlign);
1028 if (EltAlign > MaxAlign)
1029 MaxAlign = EltAlign;
1030 } else if (const StructType *STy = dyn_cast<StructType>(Ty)) {
1031 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
1032 unsigned EltAlign = 0;
1033 getMaxByValAlign(STy->getElementType(i), EltAlign);
1034 if (EltAlign > MaxAlign)
1035 MaxAlign = EltAlign;
1043 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1044 /// function arguments in the caller parameter area. For X86, aggregates
1045 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
1046 /// are at 4-byte boundaries.
1047 unsigned X86TargetLowering::getByValTypeAlignment(const Type *Ty) const {
1048 if (Subtarget->is64Bit()) {
1049 // Max of 8 and alignment of type.
1050 unsigned TyAlign = TD->getABITypeAlignment(Ty);
1057 if (Subtarget->hasSSE1())
1058 getMaxByValAlign(Ty, Align);
1062 /// getOptimalMemOpType - Returns the target specific optimal type for load
1063 /// and store operations as a result of memset, memcpy, and memmove
1064 /// lowering. It returns MVT::iAny if SelectionDAG should be responsible for
1067 X86TargetLowering::getOptimalMemOpType(uint64_t Size, unsigned Align,
1068 bool isSrcConst, bool isSrcStr,
1069 SelectionDAG &DAG) const {
1070 // FIXME: This turns off use of xmm stores for memset/memcpy on targets like
1071 // linux. This is because the stack realignment code can't handle certain
1072 // cases like PR2962. This should be removed when PR2962 is fixed.
1073 const Function *F = DAG.getMachineFunction().getFunction();
1074 bool NoImplicitFloatOps = F->hasFnAttr(Attribute::NoImplicitFloat);
1075 if (!NoImplicitFloatOps && Subtarget->getStackAlignment() >= 16) {
1076 if ((isSrcConst || isSrcStr) && Subtarget->hasSSE2() && Size >= 16)
1078 if ((isSrcConst || isSrcStr) && Subtarget->hasSSE1() && Size >= 16)
1081 if (Subtarget->is64Bit() && Size >= 8)
1086 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
1088 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
1089 SelectionDAG &DAG) const {
1090 if (usesGlobalOffsetTable())
1091 return DAG.getGLOBAL_OFFSET_TABLE(getPointerTy());
1092 if (!Subtarget->is64Bit())
1093 // This doesn't have DebugLoc associated with it, but is not really the
1094 // same as a Register.
1095 return DAG.getNode(X86ISD::GlobalBaseReg, DebugLoc::getUnknownLoc(),
1100 /// getFunctionAlignment - Return the Log2 alignment of this function.
1101 unsigned X86TargetLowering::getFunctionAlignment(const Function *F) const {
1102 return F->hasFnAttr(Attribute::OptimizeForSize) ? 0 : 4;
1105 //===----------------------------------------------------------------------===//
1106 // Return Value Calling Convention Implementation
1107 //===----------------------------------------------------------------------===//
1109 #include "X86GenCallingConv.inc"
1112 X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv, bool isVarArg,
1113 const SmallVectorImpl<EVT> &OutTys,
1114 const SmallVectorImpl<ISD::ArgFlagsTy> &ArgsFlags,
1115 SelectionDAG &DAG) {
1116 SmallVector<CCValAssign, 16> RVLocs;
1117 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1118 RVLocs, *DAG.getContext());
1119 return CCInfo.CheckReturn(OutTys, ArgsFlags, RetCC_X86);
1123 X86TargetLowering::LowerReturn(SDValue Chain,
1124 CallingConv::ID CallConv, bool isVarArg,
1125 const SmallVectorImpl<ISD::OutputArg> &Outs,
1126 DebugLoc dl, SelectionDAG &DAG) {
1128 SmallVector<CCValAssign, 16> RVLocs;
1129 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1130 RVLocs, *DAG.getContext());
1131 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
1133 // If this is the first return lowered for this function, add the regs to the
1134 // liveout set for the function.
1135 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
1136 for (unsigned i = 0; i != RVLocs.size(); ++i)
1137 if (RVLocs[i].isRegLoc())
1138 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
1143 SmallVector<SDValue, 6> RetOps;
1144 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
1145 // Operand #1 = Bytes To Pop
1146 RetOps.push_back(DAG.getTargetConstant(getBytesToPopOnReturn(), MVT::i16));
1148 // Copy the result values into the output registers.
1149 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1150 CCValAssign &VA = RVLocs[i];
1151 assert(VA.isRegLoc() && "Can only return in registers!");
1152 SDValue ValToCopy = Outs[i].Val;
1154 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
1155 // the RET instruction and handled by the FP Stackifier.
1156 if (VA.getLocReg() == X86::ST0 ||
1157 VA.getLocReg() == X86::ST1) {
1158 // If this is a copy from an xmm register to ST(0), use an FPExtend to
1159 // change the value to the FP stack register class.
1160 if (isScalarFPTypeInSSEReg(VA.getValVT()))
1161 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
1162 RetOps.push_back(ValToCopy);
1163 // Don't emit a copytoreg.
1167 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
1168 // which is returned in RAX / RDX.
1169 if (Subtarget->is64Bit()) {
1170 EVT ValVT = ValToCopy.getValueType();
1171 if (ValVT.isVector() && ValVT.getSizeInBits() == 64) {
1172 ValToCopy = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i64, ValToCopy);
1173 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1)
1174 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, ValToCopy);
1178 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
1179 Flag = Chain.getValue(1);
1182 // The x86-64 ABI for returning structs by value requires that we copy
1183 // the sret argument into %rax for the return. We saved the argument into
1184 // a virtual register in the entry block, so now we copy the value out
1186 if (Subtarget->is64Bit() &&
1187 DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
1188 MachineFunction &MF = DAG.getMachineFunction();
1189 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1190 unsigned Reg = FuncInfo->getSRetReturnReg();
1192 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64));
1193 FuncInfo->setSRetReturnReg(Reg);
1195 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
1197 Chain = DAG.getCopyToReg(Chain, dl, X86::RAX, Val, Flag);
1198 Flag = Chain.getValue(1);
1200 // RAX now acts like a return value.
1201 MF.getRegInfo().addLiveOut(X86::RAX);
1204 RetOps[0] = Chain; // Update chain.
1206 // Add the flag if we have it.
1208 RetOps.push_back(Flag);
1210 return DAG.getNode(X86ISD::RET_FLAG, dl,
1211 MVT::Other, &RetOps[0], RetOps.size());
1214 /// LowerCallResult - Lower the result values of a call into the
1215 /// appropriate copies out of appropriate physical registers.
1218 X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
1219 CallingConv::ID CallConv, bool isVarArg,
1220 const SmallVectorImpl<ISD::InputArg> &Ins,
1221 DebugLoc dl, SelectionDAG &DAG,
1222 SmallVectorImpl<SDValue> &InVals) {
1224 // Assign locations to each value returned by this call.
1225 SmallVector<CCValAssign, 16> RVLocs;
1226 bool Is64Bit = Subtarget->is64Bit();
1227 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1228 RVLocs, *DAG.getContext());
1229 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
1231 // Copy all of the result registers out of their specified physreg.
1232 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1233 CCValAssign &VA = RVLocs[i];
1234 EVT CopyVT = VA.getValVT();
1236 // If this is x86-64, and we disabled SSE, we can't return FP values
1237 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
1238 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) {
1239 llvm_report_error("SSE register return with SSE disabled");
1242 // If this is a call to a function that returns an fp value on the floating
1243 // point stack, but where we prefer to use the value in xmm registers, copy
1244 // it out as F80 and use a truncate to move it from fp stack reg to xmm reg.
1245 if ((VA.getLocReg() == X86::ST0 ||
1246 VA.getLocReg() == X86::ST1) &&
1247 isScalarFPTypeInSSEReg(VA.getValVT())) {
1252 if (Is64Bit && CopyVT.isVector() && CopyVT.getSizeInBits() == 64) {
1253 // For x86-64, MMX values are returned in XMM0 / XMM1 except for v1i64.
1254 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
1255 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
1256 MVT::v2i64, InFlag).getValue(1);
1257 Val = Chain.getValue(0);
1258 Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64,
1259 Val, DAG.getConstant(0, MVT::i64));
1261 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
1262 MVT::i64, InFlag).getValue(1);
1263 Val = Chain.getValue(0);
1265 Val = DAG.getNode(ISD::BIT_CONVERT, dl, CopyVT, Val);
1267 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
1268 CopyVT, InFlag).getValue(1);
1269 Val = Chain.getValue(0);
1271 InFlag = Chain.getValue(2);
1273 if (CopyVT != VA.getValVT()) {
1274 // Round the F80 the right size, which also moves to the appropriate xmm
1276 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
1277 // This truncation won't change the value.
1278 DAG.getIntPtrConstant(1));
1281 InVals.push_back(Val);
1288 //===----------------------------------------------------------------------===//
1289 // C & StdCall & Fast Calling Convention implementation
1290 //===----------------------------------------------------------------------===//
1291 // StdCall calling convention seems to be standard for many Windows' API
1292 // routines and around. It differs from C calling convention just a little:
1293 // callee should clean up the stack, not caller. Symbols should be also
1294 // decorated in some fancy way :) It doesn't support any vector arguments.
1295 // For info on fast calling convention see Fast Calling Convention (tail call)
1296 // implementation LowerX86_32FastCCCallTo.
1298 /// CallIsStructReturn - Determines whether a call uses struct return
1300 static bool CallIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
1304 return Outs[0].Flags.isSRet();
1307 /// ArgsAreStructReturn - Determines whether a function uses struct
1308 /// return semantics.
1310 ArgsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
1314 return Ins[0].Flags.isSRet();
1317 /// IsCalleePop - Determines whether the callee is required to pop its
1318 /// own arguments. Callee pop is necessary to support tail calls.
1319 bool X86TargetLowering::IsCalleePop(bool IsVarArg, CallingConv::ID CallingConv){
1323 switch (CallingConv) {
1326 case CallingConv::X86_StdCall:
1327 return !Subtarget->is64Bit();
1328 case CallingConv::X86_FastCall:
1329 return !Subtarget->is64Bit();
1330 case CallingConv::Fast:
1331 return PerformTailCallOpt;
1335 /// CCAssignFnForNode - Selects the correct CCAssignFn for a the
1336 /// given CallingConvention value.
1337 CCAssignFn *X86TargetLowering::CCAssignFnForNode(CallingConv::ID CC) const {
1338 if (Subtarget->is64Bit()) {
1339 if (Subtarget->isTargetWin64())
1340 return CC_X86_Win64_C;
1345 if (CC == CallingConv::X86_FastCall)
1346 return CC_X86_32_FastCall;
1347 else if (CC == CallingConv::Fast)
1348 return CC_X86_32_FastCC;
1353 /// NameDecorationForCallConv - Selects the appropriate decoration to
1354 /// apply to a MachineFunction containing a given calling convention.
1356 X86TargetLowering::NameDecorationForCallConv(CallingConv::ID CallConv) {
1357 if (CallConv == CallingConv::X86_FastCall)
1359 else if (CallConv == CallingConv::X86_StdCall)
1365 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
1366 /// by "Src" to address "Dst" with size and alignment information specified by
1367 /// the specific parameter attribute. The copy will be passed as a byval
1368 /// function parameter.
1370 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
1371 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
1373 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
1374 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
1375 /*AlwaysInline=*/true, NULL, 0, NULL, 0);
1379 X86TargetLowering::LowerMemArgument(SDValue Chain,
1380 CallingConv::ID CallConv,
1381 const SmallVectorImpl<ISD::InputArg> &Ins,
1382 DebugLoc dl, SelectionDAG &DAG,
1383 const CCValAssign &VA,
1384 MachineFrameInfo *MFI,
1387 // Create the nodes corresponding to a load from this parameter slot.
1388 ISD::ArgFlagsTy Flags = Ins[i].Flags;
1389 bool AlwaysUseMutable = (CallConv==CallingConv::Fast) && PerformTailCallOpt;
1390 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
1393 // If value is passed by pointer we have address passed instead of the value
1395 if (VA.getLocInfo() == CCValAssign::Indirect)
1396 ValVT = VA.getLocVT();
1398 ValVT = VA.getValVT();
1400 // FIXME: For now, all byval parameter objects are marked mutable. This can be
1401 // changed with more analysis.
1402 // In case of tail call optimization mark all arguments mutable. Since they
1403 // could be overwritten by lowering of arguments in case of a tail call.
1404 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
1405 VA.getLocMemOffset(), isImmutable, false);
1406 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
1407 if (Flags.isByVal())
1409 return DAG.getLoad(ValVT, dl, Chain, FIN,
1410 PseudoSourceValue::getFixedStack(FI), 0);
1414 X86TargetLowering::LowerFormalArguments(SDValue Chain,
1415 CallingConv::ID CallConv,
1417 const SmallVectorImpl<ISD::InputArg> &Ins,
1420 SmallVectorImpl<SDValue> &InVals) {
1422 MachineFunction &MF = DAG.getMachineFunction();
1423 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1425 const Function* Fn = MF.getFunction();
1426 if (Fn->hasExternalLinkage() &&
1427 Subtarget->isTargetCygMing() &&
1428 Fn->getName() == "main")
1429 FuncInfo->setForceFramePointer(true);
1431 // Decorate the function name.
1432 FuncInfo->setDecorationStyle(NameDecorationForCallConv(CallConv));
1434 MachineFrameInfo *MFI = MF.getFrameInfo();
1435 bool Is64Bit = Subtarget->is64Bit();
1436 bool IsWin64 = Subtarget->isTargetWin64();
1438 assert(!(isVarArg && CallConv == CallingConv::Fast) &&
1439 "Var args not supported with calling convention fastcc");
1441 // Assign locations to all of the incoming arguments.
1442 SmallVector<CCValAssign, 16> ArgLocs;
1443 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1444 ArgLocs, *DAG.getContext());
1445 CCInfo.AnalyzeFormalArguments(Ins, CCAssignFnForNode(CallConv));
1447 unsigned LastVal = ~0U;
1449 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1450 CCValAssign &VA = ArgLocs[i];
1451 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
1453 assert(VA.getValNo() != LastVal &&
1454 "Don't support value assigned to multiple locs yet");
1455 LastVal = VA.getValNo();
1457 if (VA.isRegLoc()) {
1458 EVT RegVT = VA.getLocVT();
1459 TargetRegisterClass *RC = NULL;
1460 if (RegVT == MVT::i32)
1461 RC = X86::GR32RegisterClass;
1462 else if (Is64Bit && RegVT == MVT::i64)
1463 RC = X86::GR64RegisterClass;
1464 else if (RegVT == MVT::f32)
1465 RC = X86::FR32RegisterClass;
1466 else if (RegVT == MVT::f64)
1467 RC = X86::FR64RegisterClass;
1468 else if (RegVT.isVector() && RegVT.getSizeInBits() == 128)
1469 RC = X86::VR128RegisterClass;
1470 else if (RegVT.isVector() && RegVT.getSizeInBits() == 64)
1471 RC = X86::VR64RegisterClass;
1473 llvm_unreachable("Unknown argument type!");
1475 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
1476 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
1478 // If this is an 8 or 16-bit value, it is really passed promoted to 32
1479 // bits. Insert an assert[sz]ext to capture this, then truncate to the
1481 if (VA.getLocInfo() == CCValAssign::SExt)
1482 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
1483 DAG.getValueType(VA.getValVT()));
1484 else if (VA.getLocInfo() == CCValAssign::ZExt)
1485 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
1486 DAG.getValueType(VA.getValVT()));
1487 else if (VA.getLocInfo() == CCValAssign::BCvt)
1488 ArgValue = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getValVT(), ArgValue);
1490 if (VA.isExtInLoc()) {
1491 // Handle MMX values passed in XMM regs.
1492 if (RegVT.isVector()) {
1493 ArgValue = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64,
1494 ArgValue, DAG.getConstant(0, MVT::i64));
1495 ArgValue = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getValVT(), ArgValue);
1497 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
1500 assert(VA.isMemLoc());
1501 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
1504 // If value is passed via pointer - do a load.
1505 if (VA.getLocInfo() == CCValAssign::Indirect)
1506 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue, NULL, 0);
1508 InVals.push_back(ArgValue);
1511 // The x86-64 ABI for returning structs by value requires that we copy
1512 // the sret argument into %rax for the return. Save the argument into
1513 // a virtual register so that we can access it from the return points.
1514 if (Is64Bit && MF.getFunction()->hasStructRetAttr()) {
1515 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1516 unsigned Reg = FuncInfo->getSRetReturnReg();
1518 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64));
1519 FuncInfo->setSRetReturnReg(Reg);
1521 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]);
1522 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
1525 unsigned StackSize = CCInfo.getNextStackOffset();
1526 // align stack specially for tail calls
1527 if (PerformTailCallOpt && CallConv == CallingConv::Fast)
1528 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
1530 // If the function takes variable number of arguments, make a frame index for
1531 // the start of the first vararg value... for expansion of llvm.va_start.
1533 if (Is64Bit || CallConv != CallingConv::X86_FastCall) {
1534 VarArgsFrameIndex = MFI->CreateFixedObject(1, StackSize, true, false);
1537 unsigned TotalNumIntRegs = 0, TotalNumXMMRegs = 0;
1539 // FIXME: We should really autogenerate these arrays
1540 static const unsigned GPR64ArgRegsWin64[] = {
1541 X86::RCX, X86::RDX, X86::R8, X86::R9
1543 static const unsigned XMMArgRegsWin64[] = {
1544 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
1546 static const unsigned GPR64ArgRegs64Bit[] = {
1547 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
1549 static const unsigned XMMArgRegs64Bit[] = {
1550 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
1551 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
1553 const unsigned *GPR64ArgRegs, *XMMArgRegs;
1556 TotalNumIntRegs = 4; TotalNumXMMRegs = 4;
1557 GPR64ArgRegs = GPR64ArgRegsWin64;
1558 XMMArgRegs = XMMArgRegsWin64;
1560 TotalNumIntRegs = 6; TotalNumXMMRegs = 8;
1561 GPR64ArgRegs = GPR64ArgRegs64Bit;
1562 XMMArgRegs = XMMArgRegs64Bit;
1564 unsigned NumIntRegs = CCInfo.getFirstUnallocated(GPR64ArgRegs,
1566 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs,
1569 bool NoImplicitFloatOps = Fn->hasFnAttr(Attribute::NoImplicitFloat);
1570 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) &&
1571 "SSE register cannot be used when SSE is disabled!");
1572 assert(!(NumXMMRegs && UseSoftFloat && NoImplicitFloatOps) &&
1573 "SSE register cannot be used when SSE is disabled!");
1574 if (UseSoftFloat || NoImplicitFloatOps || !Subtarget->hasSSE1())
1575 // Kernel mode asks for SSE to be disabled, so don't push them
1577 TotalNumXMMRegs = 0;
1579 // For X86-64, if there are vararg parameters that are passed via
1580 // registers, then we must store them to their spots on the stack so they
1581 // may be loaded by deferencing the result of va_next.
1582 VarArgsGPOffset = NumIntRegs * 8;
1583 VarArgsFPOffset = TotalNumIntRegs * 8 + NumXMMRegs * 16;
1584 RegSaveFrameIndex = MFI->CreateStackObject(TotalNumIntRegs * 8 +
1585 TotalNumXMMRegs * 16, 16,
1588 // Store the integer parameter registers.
1589 SmallVector<SDValue, 8> MemOps;
1590 SDValue RSFIN = DAG.getFrameIndex(RegSaveFrameIndex, getPointerTy());
1591 unsigned Offset = VarArgsGPOffset;
1592 for (; NumIntRegs != TotalNumIntRegs; ++NumIntRegs) {
1593 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN,
1594 DAG.getIntPtrConstant(Offset));
1595 unsigned VReg = MF.addLiveIn(GPR64ArgRegs[NumIntRegs],
1596 X86::GR64RegisterClass);
1597 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
1599 DAG.getStore(Val.getValue(1), dl, Val, FIN,
1600 PseudoSourceValue::getFixedStack(RegSaveFrameIndex),
1602 MemOps.push_back(Store);
1606 if (TotalNumXMMRegs != 0 && NumXMMRegs != TotalNumXMMRegs) {
1607 // Now store the XMM (fp + vector) parameter registers.
1608 SmallVector<SDValue, 11> SaveXMMOps;
1609 SaveXMMOps.push_back(Chain);
1611 unsigned AL = MF.addLiveIn(X86::AL, X86::GR8RegisterClass);
1612 SDValue ALVal = DAG.getCopyFromReg(DAG.getEntryNode(), dl, AL, MVT::i8);
1613 SaveXMMOps.push_back(ALVal);
1615 SaveXMMOps.push_back(DAG.getIntPtrConstant(RegSaveFrameIndex));
1616 SaveXMMOps.push_back(DAG.getIntPtrConstant(VarArgsFPOffset));
1618 for (; NumXMMRegs != TotalNumXMMRegs; ++NumXMMRegs) {
1619 unsigned VReg = MF.addLiveIn(XMMArgRegs[NumXMMRegs],
1620 X86::VR128RegisterClass);
1621 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::v4f32);
1622 SaveXMMOps.push_back(Val);
1624 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
1626 &SaveXMMOps[0], SaveXMMOps.size()));
1629 if (!MemOps.empty())
1630 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1631 &MemOps[0], MemOps.size());
1635 // Some CCs need callee pop.
1636 if (IsCalleePop(isVarArg, CallConv)) {
1637 BytesToPopOnReturn = StackSize; // Callee pops everything.
1638 BytesCallerReserves = 0;
1640 BytesToPopOnReturn = 0; // Callee pops nothing.
1641 // If this is an sret function, the return should pop the hidden pointer.
1642 if (!Is64Bit && CallConv != CallingConv::Fast && ArgsAreStructReturn(Ins))
1643 BytesToPopOnReturn = 4;
1644 BytesCallerReserves = StackSize;
1648 RegSaveFrameIndex = 0xAAAAAAA; // RegSaveFrameIndex is X86-64 only.
1649 if (CallConv == CallingConv::X86_FastCall)
1650 VarArgsFrameIndex = 0xAAAAAAA; // fastcc functions can't have varargs.
1653 FuncInfo->setBytesToPopOnReturn(BytesToPopOnReturn);
1659 X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
1660 SDValue StackPtr, SDValue Arg,
1661 DebugLoc dl, SelectionDAG &DAG,
1662 const CCValAssign &VA,
1663 ISD::ArgFlagsTy Flags) {
1664 const unsigned FirstStackArgOffset = (Subtarget->isTargetWin64() ? 32 : 0);
1665 unsigned LocMemOffset = FirstStackArgOffset + VA.getLocMemOffset();
1666 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
1667 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
1668 if (Flags.isByVal()) {
1669 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
1671 return DAG.getStore(Chain, dl, Arg, PtrOff,
1672 PseudoSourceValue::getStack(), LocMemOffset);
1675 /// EmitTailCallLoadRetAddr - Emit a load of return address if tail call
1676 /// optimization is performed and it is required.
1678 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
1679 SDValue &OutRetAddr,
1685 if (!IsTailCall || FPDiff==0) return Chain;
1687 // Adjust the Return address stack slot.
1688 EVT VT = getPointerTy();
1689 OutRetAddr = getReturnAddressFrameIndex(DAG);
1691 // Load the "old" Return address.
1692 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, NULL, 0);
1693 return SDValue(OutRetAddr.getNode(), 1);
1696 /// EmitTailCallStoreRetAddr - Emit a store of the return adress if tail call
1697 /// optimization is performed and it is required (FPDiff!=0).
1699 EmitTailCallStoreRetAddr(SelectionDAG & DAG, MachineFunction &MF,
1700 SDValue Chain, SDValue RetAddrFrIdx,
1701 bool Is64Bit, int FPDiff, DebugLoc dl) {
1702 // Store the return address to the appropriate stack slot.
1703 if (!FPDiff) return Chain;
1704 // Calculate the new stack slot for the return address.
1705 int SlotSize = Is64Bit ? 8 : 4;
1706 int NewReturnAddrFI =
1707 MF.getFrameInfo()->CreateFixedObject(SlotSize, FPDiff-SlotSize,
1709 EVT VT = Is64Bit ? MVT::i64 : MVT::i32;
1710 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, VT);
1711 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
1712 PseudoSourceValue::getFixedStack(NewReturnAddrFI), 0);
1717 X86TargetLowering::LowerCall(SDValue Chain, SDValue Callee,
1718 CallingConv::ID CallConv, bool isVarArg,
1720 const SmallVectorImpl<ISD::OutputArg> &Outs,
1721 const SmallVectorImpl<ISD::InputArg> &Ins,
1722 DebugLoc dl, SelectionDAG &DAG,
1723 SmallVectorImpl<SDValue> &InVals) {
1725 MachineFunction &MF = DAG.getMachineFunction();
1726 bool Is64Bit = Subtarget->is64Bit();
1727 bool IsStructRet = CallIsStructReturn(Outs);
1729 assert((!isTailCall ||
1730 (CallConv == CallingConv::Fast && PerformTailCallOpt)) &&
1731 "IsEligibleForTailCallOptimization missed a case!");
1732 assert(!(isVarArg && CallConv == CallingConv::Fast) &&
1733 "Var args not supported with calling convention fastcc");
1735 // Analyze operands of the call, assigning locations to each operand.
1736 SmallVector<CCValAssign, 16> ArgLocs;
1737 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1738 ArgLocs, *DAG.getContext());
1739 CCInfo.AnalyzeCallOperands(Outs, CCAssignFnForNode(CallConv));
1741 // Get a count of how many bytes are to be pushed on the stack.
1742 unsigned NumBytes = CCInfo.getNextStackOffset();
1743 if (PerformTailCallOpt && CallConv == CallingConv::Fast)
1744 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
1748 // Lower arguments at fp - stackoffset + fpdiff.
1749 unsigned NumBytesCallerPushed =
1750 MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn();
1751 FPDiff = NumBytesCallerPushed - NumBytes;
1753 // Set the delta of movement of the returnaddr stackslot.
1754 // But only set if delta is greater than previous delta.
1755 if (FPDiff < (MF.getInfo<X86MachineFunctionInfo>()->getTCReturnAddrDelta()))
1756 MF.getInfo<X86MachineFunctionInfo>()->setTCReturnAddrDelta(FPDiff);
1759 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
1761 SDValue RetAddrFrIdx;
1762 // Load return adress for tail calls.
1763 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall, Is64Bit,
1766 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
1767 SmallVector<SDValue, 8> MemOpChains;
1770 // Walk the register/memloc assignments, inserting copies/loads. In the case
1771 // of tail call optimization arguments are handle later.
1772 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1773 CCValAssign &VA = ArgLocs[i];
1774 EVT RegVT = VA.getLocVT();
1775 SDValue Arg = Outs[i].Val;
1776 ISD::ArgFlagsTy Flags = Outs[i].Flags;
1777 bool isByVal = Flags.isByVal();
1779 // Promote the value if needed.
1780 switch (VA.getLocInfo()) {
1781 default: llvm_unreachable("Unknown loc info!");
1782 case CCValAssign::Full: break;
1783 case CCValAssign::SExt:
1784 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
1786 case CCValAssign::ZExt:
1787 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
1789 case CCValAssign::AExt:
1790 if (RegVT.isVector() && RegVT.getSizeInBits() == 128) {
1791 // Special case: passing MMX values in XMM registers.
1792 Arg = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i64, Arg);
1793 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
1794 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
1796 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
1798 case CCValAssign::BCvt:
1799 Arg = DAG.getNode(ISD::BIT_CONVERT, dl, RegVT, Arg);
1801 case CCValAssign::Indirect: {
1802 // Store the argument.
1803 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
1804 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
1805 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot,
1806 PseudoSourceValue::getFixedStack(FI), 0);
1812 if (VA.isRegLoc()) {
1813 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
1815 if (!isTailCall || (isTailCall && isByVal)) {
1816 assert(VA.isMemLoc());
1817 if (StackPtr.getNode() == 0)
1818 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr, getPointerTy());
1820 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
1821 dl, DAG, VA, Flags));
1826 if (!MemOpChains.empty())
1827 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1828 &MemOpChains[0], MemOpChains.size());
1830 // Build a sequence of copy-to-reg nodes chained together with token chain
1831 // and flag operands which copy the outgoing args into registers.
1833 // Tail call byval lowering might overwrite argument registers so in case of
1834 // tail call optimization the copies to registers are lowered later.
1836 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1837 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
1838 RegsToPass[i].second, InFlag);
1839 InFlag = Chain.getValue(1);
1843 if (Subtarget->isPICStyleGOT()) {
1844 // ELF / PIC requires GOT in the EBX register before function calls via PLT
1847 Chain = DAG.getCopyToReg(Chain, dl, X86::EBX,
1848 DAG.getNode(X86ISD::GlobalBaseReg,
1849 DebugLoc::getUnknownLoc(),
1852 InFlag = Chain.getValue(1);
1854 // If we are tail calling and generating PIC/GOT style code load the
1855 // address of the callee into ECX. The value in ecx is used as target of
1856 // the tail jump. This is done to circumvent the ebx/callee-saved problem
1857 // for tail calls on PIC/GOT architectures. Normally we would just put the
1858 // address of GOT into ebx and then call target@PLT. But for tail calls
1859 // ebx would be restored (since ebx is callee saved) before jumping to the
1862 // Note: The actual moving to ECX is done further down.
1863 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
1864 if (G && !G->getGlobal()->hasHiddenVisibility() &&
1865 !G->getGlobal()->hasProtectedVisibility())
1866 Callee = LowerGlobalAddress(Callee, DAG);
1867 else if (isa<ExternalSymbolSDNode>(Callee))
1868 Callee = LowerExternalSymbol(Callee, DAG);
1872 if (Is64Bit && isVarArg) {
1873 // From AMD64 ABI document:
1874 // For calls that may call functions that use varargs or stdargs
1875 // (prototype-less calls or calls to functions containing ellipsis (...) in
1876 // the declaration) %al is used as hidden argument to specify the number
1877 // of SSE registers used. The contents of %al do not need to match exactly
1878 // the number of registers, but must be an ubound on the number of SSE
1879 // registers used and is in the range 0 - 8 inclusive.
1881 // FIXME: Verify this on Win64
1882 // Count the number of XMM registers allocated.
1883 static const unsigned XMMArgRegs[] = {
1884 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
1885 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
1887 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
1888 assert((Subtarget->hasSSE1() || !NumXMMRegs)
1889 && "SSE registers cannot be used when SSE is disabled");
1891 Chain = DAG.getCopyToReg(Chain, dl, X86::AL,
1892 DAG.getConstant(NumXMMRegs, MVT::i8), InFlag);
1893 InFlag = Chain.getValue(1);
1897 // For tail calls lower the arguments to the 'real' stack slot.
1899 // Force all the incoming stack arguments to be loaded from the stack
1900 // before any new outgoing arguments are stored to the stack, because the
1901 // outgoing stack slots may alias the incoming argument stack slots, and
1902 // the alias isn't otherwise explicit. This is slightly more conservative
1903 // than necessary, because it means that each store effectively depends
1904 // on every argument instead of just those arguments it would clobber.
1905 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
1907 SmallVector<SDValue, 8> MemOpChains2;
1910 // Do not flag preceeding copytoreg stuff together with the following stuff.
1912 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1913 CCValAssign &VA = ArgLocs[i];
1914 if (!VA.isRegLoc()) {
1915 assert(VA.isMemLoc());
1916 SDValue Arg = Outs[i].Val;
1917 ISD::ArgFlagsTy Flags = Outs[i].Flags;
1918 // Create frame index.
1919 int32_t Offset = VA.getLocMemOffset()+FPDiff;
1920 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
1921 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true, false);
1922 FIN = DAG.getFrameIndex(FI, getPointerTy());
1924 if (Flags.isByVal()) {
1925 // Copy relative to framepointer.
1926 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset());
1927 if (StackPtr.getNode() == 0)
1928 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr,
1930 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source);
1932 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
1936 // Store relative to framepointer.
1937 MemOpChains2.push_back(
1938 DAG.getStore(ArgChain, dl, Arg, FIN,
1939 PseudoSourceValue::getFixedStack(FI), 0));
1944 if (!MemOpChains2.empty())
1945 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1946 &MemOpChains2[0], MemOpChains2.size());
1948 // Copy arguments to their registers.
1949 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1950 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
1951 RegsToPass[i].second, InFlag);
1952 InFlag = Chain.getValue(1);
1956 // Store the return address to the appropriate stack slot.
1957 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx, Is64Bit,
1961 bool WasGlobalOrExternal = false;
1962 if (getTargetMachine().getCodeModel() == CodeModel::Large) {
1963 assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
1964 // In the 64-bit large code model, we have to make all calls
1965 // through a register, since the call instruction's 32-bit
1966 // pc-relative offset may not be large enough to hold the whole
1968 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1969 WasGlobalOrExternal = true;
1970 // If the callee is a GlobalAddress node (quite common, every direct call
1971 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
1974 // We should use extra load for direct calls to dllimported functions in
1976 GlobalValue *GV = G->getGlobal();
1977 if (!GV->hasDLLImportLinkage()) {
1978 unsigned char OpFlags = 0;
1980 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
1981 // external symbols most go through the PLT in PIC mode. If the symbol
1982 // has hidden or protected visibility, or if it is static or local, then
1983 // we don't need to use the PLT - we can directly call it.
1984 if (Subtarget->isTargetELF() &&
1985 getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1986 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
1987 OpFlags = X86II::MO_PLT;
1988 } else if (Subtarget->isPICStyleStubAny() &&
1989 (GV->isDeclaration() || GV->isWeakForLinker()) &&
1990 Subtarget->getDarwinVers() < 9) {
1991 // PC-relative references to external symbols should go through $stub,
1992 // unless we're building with the leopard linker or later, which
1993 // automatically synthesizes these stubs.
1994 OpFlags = X86II::MO_DARWIN_STUB;
1997 Callee = DAG.getTargetGlobalAddress(GV, getPointerTy(),
1998 G->getOffset(), OpFlags);
2000 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
2001 WasGlobalOrExternal = true;
2002 unsigned char OpFlags = 0;
2004 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to external
2005 // symbols should go through the PLT.
2006 if (Subtarget->isTargetELF() &&
2007 getTargetMachine().getRelocationModel() == Reloc::PIC_) {
2008 OpFlags = X86II::MO_PLT;
2009 } else if (Subtarget->isPICStyleStubAny() &&
2010 Subtarget->getDarwinVers() < 9) {
2011 // PC-relative references to external symbols should go through $stub,
2012 // unless we're building with the leopard linker or later, which
2013 // automatically synthesizes these stubs.
2014 OpFlags = X86II::MO_DARWIN_STUB;
2017 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(),
2021 if (isTailCall && !WasGlobalOrExternal) {
2022 unsigned Opc = Is64Bit ? X86::R11 : X86::EAX;
2024 Chain = DAG.getCopyToReg(Chain, dl,
2025 DAG.getRegister(Opc, getPointerTy()),
2027 Callee = DAG.getRegister(Opc, getPointerTy());
2028 // Add register as live out.
2029 MF.getRegInfo().addLiveOut(Opc);
2032 // Returns a chain & a flag for retval copy to use.
2033 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
2034 SmallVector<SDValue, 8> Ops;
2037 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
2038 DAG.getIntPtrConstant(0, true), InFlag);
2039 InFlag = Chain.getValue(1);
2042 Ops.push_back(Chain);
2043 Ops.push_back(Callee);
2046 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32));
2048 // Add argument registers to the end of the list so that they are known live
2050 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
2051 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
2052 RegsToPass[i].second.getValueType()));
2054 // Add an implicit use GOT pointer in EBX.
2055 if (!isTailCall && Subtarget->isPICStyleGOT())
2056 Ops.push_back(DAG.getRegister(X86::EBX, getPointerTy()));
2058 // Add an implicit use of AL for x86 vararg functions.
2059 if (Is64Bit && isVarArg)
2060 Ops.push_back(DAG.getRegister(X86::AL, MVT::i8));
2062 if (InFlag.getNode())
2063 Ops.push_back(InFlag);
2066 // If this is the first return lowered for this function, add the regs
2067 // to the liveout set for the function.
2068 if (MF.getRegInfo().liveout_empty()) {
2069 SmallVector<CCValAssign, 16> RVLocs;
2070 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), RVLocs,
2072 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
2073 for (unsigned i = 0; i != RVLocs.size(); ++i)
2074 if (RVLocs[i].isRegLoc())
2075 MF.getRegInfo().addLiveOut(RVLocs[i].getLocReg());
2078 assert(((Callee.getOpcode() == ISD::Register &&
2079 (cast<RegisterSDNode>(Callee)->getReg() == X86::EAX ||
2080 cast<RegisterSDNode>(Callee)->getReg() == X86::R9)) ||
2081 Callee.getOpcode() == ISD::TargetExternalSymbol ||
2082 Callee.getOpcode() == ISD::TargetGlobalAddress) &&
2083 "Expecting an global address, external symbol, or register");
2085 return DAG.getNode(X86ISD::TC_RETURN, dl,
2086 NodeTys, &Ops[0], Ops.size());
2089 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, &Ops[0], Ops.size());
2090 InFlag = Chain.getValue(1);
2092 // Create the CALLSEQ_END node.
2093 unsigned NumBytesForCalleeToPush;
2094 if (IsCalleePop(isVarArg, CallConv))
2095 NumBytesForCalleeToPush = NumBytes; // Callee pops everything
2096 else if (!Is64Bit && CallConv != CallingConv::Fast && IsStructRet)
2097 // If this is is a call to a struct-return function, the callee
2098 // pops the hidden struct pointer, so we have to push it back.
2099 // This is common for Darwin/X86, Linux & Mingw32 targets.
2100 NumBytesForCalleeToPush = 4;
2102 NumBytesForCalleeToPush = 0; // Callee pops nothing.
2104 // Returns a flag for retval copy to use.
2105 Chain = DAG.getCALLSEQ_END(Chain,
2106 DAG.getIntPtrConstant(NumBytes, true),
2107 DAG.getIntPtrConstant(NumBytesForCalleeToPush,
2110 InFlag = Chain.getValue(1);
2112 // Handle result values, copying them out of physregs into vregs that we
2114 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
2115 Ins, dl, DAG, InVals);
2119 //===----------------------------------------------------------------------===//
2120 // Fast Calling Convention (tail call) implementation
2121 //===----------------------------------------------------------------------===//
2123 // Like std call, callee cleans arguments, convention except that ECX is
2124 // reserved for storing the tail called function address. Only 2 registers are
2125 // free for argument passing (inreg). Tail call optimization is performed
2127 // * tailcallopt is enabled
2128 // * caller/callee are fastcc
2129 // On X86_64 architecture with GOT-style position independent code only local
2130 // (within module) calls are supported at the moment.
2131 // To keep the stack aligned according to platform abi the function
2132 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
2133 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
2134 // If a tail called function callee has more arguments than the caller the
2135 // caller needs to make sure that there is room to move the RETADDR to. This is
2136 // achieved by reserving an area the size of the argument delta right after the
2137 // original REtADDR, but before the saved framepointer or the spilled registers
2138 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
2150 /// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned
2151 /// for a 16 byte align requirement.
2152 unsigned X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
2153 SelectionDAG& DAG) {
2154 MachineFunction &MF = DAG.getMachineFunction();
2155 const TargetMachine &TM = MF.getTarget();
2156 const TargetFrameInfo &TFI = *TM.getFrameInfo();
2157 unsigned StackAlignment = TFI.getStackAlignment();
2158 uint64_t AlignMask = StackAlignment - 1;
2159 int64_t Offset = StackSize;
2160 uint64_t SlotSize = TD->getPointerSize();
2161 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
2162 // Number smaller than 12 so just add the difference.
2163 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
2165 // Mask out lower bits, add stackalignment once plus the 12 bytes.
2166 Offset = ((~AlignMask) & Offset) + StackAlignment +
2167 (StackAlignment-SlotSize);
2172 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
2173 /// for tail call optimization. Targets which want to do tail call
2174 /// optimization should implement this function.
2176 X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
2177 CallingConv::ID CalleeCC,
2179 const SmallVectorImpl<ISD::InputArg> &Ins,
2180 SelectionDAG& DAG) const {
2181 MachineFunction &MF = DAG.getMachineFunction();
2182 CallingConv::ID CallerCC = MF.getFunction()->getCallingConv();
2183 return CalleeCC == CallingConv::Fast && CallerCC == CalleeCC;
2187 X86TargetLowering::createFastISel(MachineFunction &mf,
2188 MachineModuleInfo *mmo,
2190 DenseMap<const Value *, unsigned> &vm,
2191 DenseMap<const BasicBlock *,
2192 MachineBasicBlock *> &bm,
2193 DenseMap<const AllocaInst *, int> &am
2195 , SmallSet<Instruction*, 8> &cil
2198 return X86::createFastISel(mf, mmo, dw, vm, bm, am
2206 //===----------------------------------------------------------------------===//
2207 // Other Lowering Hooks
2208 //===----------------------------------------------------------------------===//
2211 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) {
2212 MachineFunction &MF = DAG.getMachineFunction();
2213 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2214 int ReturnAddrIndex = FuncInfo->getRAIndex();
2216 if (ReturnAddrIndex == 0) {
2217 // Set up a frame object for the return address.
2218 uint64_t SlotSize = TD->getPointerSize();
2219 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize, -SlotSize,
2221 FuncInfo->setRAIndex(ReturnAddrIndex);
2224 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
2228 bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
2229 bool hasSymbolicDisplacement) {
2230 // Offset should fit into 32 bit immediate field.
2231 if (!isInt32(Offset))
2234 // If we don't have a symbolic displacement - we don't have any extra
2236 if (!hasSymbolicDisplacement)
2239 // FIXME: Some tweaks might be needed for medium code model.
2240 if (M != CodeModel::Small && M != CodeModel::Kernel)
2243 // For small code model we assume that latest object is 16MB before end of 31
2244 // bits boundary. We may also accept pretty large negative constants knowing
2245 // that all objects are in the positive half of address space.
2246 if (M == CodeModel::Small && Offset < 16*1024*1024)
2249 // For kernel code model we know that all object resist in the negative half
2250 // of 32bits address space. We may not accept negative offsets, since they may
2251 // be just off and we may accept pretty large positive ones.
2252 if (M == CodeModel::Kernel && Offset > 0)
2258 /// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86
2259 /// specific condition code, returning the condition code and the LHS/RHS of the
2260 /// comparison to make.
2261 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
2262 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
2264 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
2265 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
2266 // X > -1 -> X == 0, jump !sign.
2267 RHS = DAG.getConstant(0, RHS.getValueType());
2268 return X86::COND_NS;
2269 } else if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
2270 // X < 0 -> X == 0, jump on sign.
2272 } else if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
2274 RHS = DAG.getConstant(0, RHS.getValueType());
2275 return X86::COND_LE;
2279 switch (SetCCOpcode) {
2280 default: llvm_unreachable("Invalid integer condition!");
2281 case ISD::SETEQ: return X86::COND_E;
2282 case ISD::SETGT: return X86::COND_G;
2283 case ISD::SETGE: return X86::COND_GE;
2284 case ISD::SETLT: return X86::COND_L;
2285 case ISD::SETLE: return X86::COND_LE;
2286 case ISD::SETNE: return X86::COND_NE;
2287 case ISD::SETULT: return X86::COND_B;
2288 case ISD::SETUGT: return X86::COND_A;
2289 case ISD::SETULE: return X86::COND_BE;
2290 case ISD::SETUGE: return X86::COND_AE;
2294 // First determine if it is required or is profitable to flip the operands.
2296 // If LHS is a foldable load, but RHS is not, flip the condition.
2297 if ((ISD::isNON_EXTLoad(LHS.getNode()) && LHS.hasOneUse()) &&
2298 !(ISD::isNON_EXTLoad(RHS.getNode()) && RHS.hasOneUse())) {
2299 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
2300 std::swap(LHS, RHS);
2303 switch (SetCCOpcode) {
2309 std::swap(LHS, RHS);
2313 // On a floating point condition, the flags are set as follows:
2315 // 0 | 0 | 0 | X > Y
2316 // 0 | 0 | 1 | X < Y
2317 // 1 | 0 | 0 | X == Y
2318 // 1 | 1 | 1 | unordered
2319 switch (SetCCOpcode) {
2320 default: llvm_unreachable("Condcode should be pre-legalized away");
2322 case ISD::SETEQ: return X86::COND_E;
2323 case ISD::SETOLT: // flipped
2325 case ISD::SETGT: return X86::COND_A;
2326 case ISD::SETOLE: // flipped
2328 case ISD::SETGE: return X86::COND_AE;
2329 case ISD::SETUGT: // flipped
2331 case ISD::SETLT: return X86::COND_B;
2332 case ISD::SETUGE: // flipped
2334 case ISD::SETLE: return X86::COND_BE;
2336 case ISD::SETNE: return X86::COND_NE;
2337 case ISD::SETUO: return X86::COND_P;
2338 case ISD::SETO: return X86::COND_NP;
2340 case ISD::SETUNE: return X86::COND_INVALID;
2344 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
2345 /// code. Current x86 isa includes the following FP cmov instructions:
2346 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
2347 static bool hasFPCMov(unsigned X86CC) {
2363 /// isFPImmLegal - Returns true if the target can instruction select the
2364 /// specified FP immediate natively. If false, the legalizer will
2365 /// materialize the FP immediate as a load from a constant pool.
2366 bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
2367 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
2368 if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
2374 /// isUndefOrInRange - Return true if Val is undef or if its value falls within
2375 /// the specified range (L, H].
2376 static bool isUndefOrInRange(int Val, int Low, int Hi) {
2377 return (Val < 0) || (Val >= Low && Val < Hi);
2380 /// isUndefOrEqual - Val is either less than zero (undef) or equal to the
2381 /// specified value.
2382 static bool isUndefOrEqual(int Val, int CmpVal) {
2383 if (Val < 0 || Val == CmpVal)
2388 /// isPSHUFDMask - Return true if the node specifies a shuffle of elements that
2389 /// is suitable for input to PSHUFD or PSHUFW. That is, it doesn't reference
2390 /// the second operand.
2391 static bool isPSHUFDMask(const SmallVectorImpl<int> &Mask, EVT VT) {
2392 if (VT == MVT::v4f32 || VT == MVT::v4i32 || VT == MVT::v4i16)
2393 return (Mask[0] < 4 && Mask[1] < 4 && Mask[2] < 4 && Mask[3] < 4);
2394 if (VT == MVT::v2f64 || VT == MVT::v2i64)
2395 return (Mask[0] < 2 && Mask[1] < 2);
2399 bool X86::isPSHUFDMask(ShuffleVectorSDNode *N) {
2400 SmallVector<int, 8> M;
2402 return ::isPSHUFDMask(M, N->getValueType(0));
2405 /// isPSHUFHWMask - Return true if the node specifies a shuffle of elements that
2406 /// is suitable for input to PSHUFHW.
2407 static bool isPSHUFHWMask(const SmallVectorImpl<int> &Mask, EVT VT) {
2408 if (VT != MVT::v8i16)
2411 // Lower quadword copied in order or undef.
2412 for (int i = 0; i != 4; ++i)
2413 if (Mask[i] >= 0 && Mask[i] != i)
2416 // Upper quadword shuffled.
2417 for (int i = 4; i != 8; ++i)
2418 if (Mask[i] >= 0 && (Mask[i] < 4 || Mask[i] > 7))
2424 bool X86::isPSHUFHWMask(ShuffleVectorSDNode *N) {
2425 SmallVector<int, 8> M;
2427 return ::isPSHUFHWMask(M, N->getValueType(0));
2430 /// isPSHUFLWMask - Return true if the node specifies a shuffle of elements that
2431 /// is suitable for input to PSHUFLW.
2432 static bool isPSHUFLWMask(const SmallVectorImpl<int> &Mask, EVT VT) {
2433 if (VT != MVT::v8i16)
2436 // Upper quadword copied in order.
2437 for (int i = 4; i != 8; ++i)
2438 if (Mask[i] >= 0 && Mask[i] != i)
2441 // Lower quadword shuffled.
2442 for (int i = 0; i != 4; ++i)
2449 bool X86::isPSHUFLWMask(ShuffleVectorSDNode *N) {
2450 SmallVector<int, 8> M;
2452 return ::isPSHUFLWMask(M, N->getValueType(0));
2455 /// isPALIGNRMask - Return true if the node specifies a shuffle of elements that
2456 /// is suitable for input to PALIGNR.
2457 static bool isPALIGNRMask(const SmallVectorImpl<int> &Mask, EVT VT,
2459 int i, e = VT.getVectorNumElements();
2461 // Do not handle v2i64 / v2f64 shuffles with palignr.
2462 if (e < 4 || !hasSSSE3)
2465 for (i = 0; i != e; ++i)
2469 // All undef, not a palignr.
2473 // Determine if it's ok to perform a palignr with only the LHS, since we
2474 // don't have access to the actual shuffle elements to see if RHS is undef.
2475 bool Unary = Mask[i] < (int)e;
2476 bool NeedsUnary = false;
2478 int s = Mask[i] - i;
2480 // Check the rest of the elements to see if they are consecutive.
2481 for (++i; i != e; ++i) {
2486 Unary = Unary && (m < (int)e);
2487 NeedsUnary = NeedsUnary || (m < s);
2489 if (NeedsUnary && !Unary)
2491 if (Unary && m != ((s+i) & (e-1)))
2493 if (!Unary && m != (s+i))
2499 bool X86::isPALIGNRMask(ShuffleVectorSDNode *N) {
2500 SmallVector<int, 8> M;
2502 return ::isPALIGNRMask(M, N->getValueType(0), true);
2505 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
2506 /// specifies a shuffle of elements that is suitable for input to SHUFP*.
2507 static bool isSHUFPMask(const SmallVectorImpl<int> &Mask, EVT VT) {
2508 int NumElems = VT.getVectorNumElements();
2509 if (NumElems != 2 && NumElems != 4)
2512 int Half = NumElems / 2;
2513 for (int i = 0; i < Half; ++i)
2514 if (!isUndefOrInRange(Mask[i], 0, NumElems))
2516 for (int i = Half; i < NumElems; ++i)
2517 if (!isUndefOrInRange(Mask[i], NumElems, NumElems*2))
2523 bool X86::isSHUFPMask(ShuffleVectorSDNode *N) {
2524 SmallVector<int, 8> M;
2526 return ::isSHUFPMask(M, N->getValueType(0));
2529 /// isCommutedSHUFP - Returns true if the shuffle mask is exactly
2530 /// the reverse of what x86 shuffles want. x86 shuffles requires the lower
2531 /// half elements to come from vector 1 (which would equal the dest.) and
2532 /// the upper half to come from vector 2.
2533 static bool isCommutedSHUFPMask(const SmallVectorImpl<int> &Mask, EVT VT) {
2534 int NumElems = VT.getVectorNumElements();
2536 if (NumElems != 2 && NumElems != 4)
2539 int Half = NumElems / 2;
2540 for (int i = 0; i < Half; ++i)
2541 if (!isUndefOrInRange(Mask[i], NumElems, NumElems*2))
2543 for (int i = Half; i < NumElems; ++i)
2544 if (!isUndefOrInRange(Mask[i], 0, NumElems))
2549 static bool isCommutedSHUFP(ShuffleVectorSDNode *N) {
2550 SmallVector<int, 8> M;
2552 return isCommutedSHUFPMask(M, N->getValueType(0));
2555 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
2556 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
2557 bool X86::isMOVHLPSMask(ShuffleVectorSDNode *N) {
2558 if (N->getValueType(0).getVectorNumElements() != 4)
2561 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3
2562 return isUndefOrEqual(N->getMaskElt(0), 6) &&
2563 isUndefOrEqual(N->getMaskElt(1), 7) &&
2564 isUndefOrEqual(N->getMaskElt(2), 2) &&
2565 isUndefOrEqual(N->getMaskElt(3), 3);
2568 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
2569 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
2571 bool X86::isMOVHLPS_v_undef_Mask(ShuffleVectorSDNode *N) {
2572 unsigned NumElems = N->getValueType(0).getVectorNumElements();
2577 return isUndefOrEqual(N->getMaskElt(0), 2) &&
2578 isUndefOrEqual(N->getMaskElt(1), 3) &&
2579 isUndefOrEqual(N->getMaskElt(2), 2) &&
2580 isUndefOrEqual(N->getMaskElt(3), 3);
2583 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
2584 /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
2585 bool X86::isMOVLPMask(ShuffleVectorSDNode *N) {
2586 unsigned NumElems = N->getValueType(0).getVectorNumElements();
2588 if (NumElems != 2 && NumElems != 4)
2591 for (unsigned i = 0; i < NumElems/2; ++i)
2592 if (!isUndefOrEqual(N->getMaskElt(i), i + NumElems))
2595 for (unsigned i = NumElems/2; i < NumElems; ++i)
2596 if (!isUndefOrEqual(N->getMaskElt(i), i))
2602 /// isMOVLHPSMask - Return true if the specified VECTOR_SHUFFLE operand
2603 /// specifies a shuffle of elements that is suitable for input to MOVLHPS.
2604 bool X86::isMOVLHPSMask(ShuffleVectorSDNode *N) {
2605 unsigned NumElems = N->getValueType(0).getVectorNumElements();
2607 if (NumElems != 2 && NumElems != 4)
2610 for (unsigned i = 0; i < NumElems/2; ++i)
2611 if (!isUndefOrEqual(N->getMaskElt(i), i))
2614 for (unsigned i = 0; i < NumElems/2; ++i)
2615 if (!isUndefOrEqual(N->getMaskElt(i + NumElems/2), i + NumElems))
2621 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
2622 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
2623 static bool isUNPCKLMask(const SmallVectorImpl<int> &Mask, EVT VT,
2624 bool V2IsSplat = false) {
2625 int NumElts = VT.getVectorNumElements();
2626 if (NumElts != 2 && NumElts != 4 && NumElts != 8 && NumElts != 16)
2629 for (int i = 0, j = 0; i != NumElts; i += 2, ++j) {
2631 int BitI1 = Mask[i+1];
2632 if (!isUndefOrEqual(BitI, j))
2635 if (!isUndefOrEqual(BitI1, NumElts))
2638 if (!isUndefOrEqual(BitI1, j + NumElts))
2645 bool X86::isUNPCKLMask(ShuffleVectorSDNode *N, bool V2IsSplat) {
2646 SmallVector<int, 8> M;
2648 return ::isUNPCKLMask(M, N->getValueType(0), V2IsSplat);
2651 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
2652 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
2653 static bool isUNPCKHMask(const SmallVectorImpl<int> &Mask, EVT VT,
2654 bool V2IsSplat = false) {
2655 int NumElts = VT.getVectorNumElements();
2656 if (NumElts != 2 && NumElts != 4 && NumElts != 8 && NumElts != 16)
2659 for (int i = 0, j = 0; i != NumElts; i += 2, ++j) {
2661 int BitI1 = Mask[i+1];
2662 if (!isUndefOrEqual(BitI, j + NumElts/2))
2665 if (isUndefOrEqual(BitI1, NumElts))
2668 if (!isUndefOrEqual(BitI1, j + NumElts/2 + NumElts))
2675 bool X86::isUNPCKHMask(ShuffleVectorSDNode *N, bool V2IsSplat) {
2676 SmallVector<int, 8> M;
2678 return ::isUNPCKHMask(M, N->getValueType(0), V2IsSplat);
2681 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
2682 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
2684 static bool isUNPCKL_v_undef_Mask(const SmallVectorImpl<int> &Mask, EVT VT) {
2685 int NumElems = VT.getVectorNumElements();
2686 if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16)
2689 for (int i = 0, j = 0; i != NumElems; i += 2, ++j) {
2691 int BitI1 = Mask[i+1];
2692 if (!isUndefOrEqual(BitI, j))
2694 if (!isUndefOrEqual(BitI1, j))
2700 bool X86::isUNPCKL_v_undef_Mask(ShuffleVectorSDNode *N) {
2701 SmallVector<int, 8> M;
2703 return ::isUNPCKL_v_undef_Mask(M, N->getValueType(0));
2706 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
2707 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
2709 static bool isUNPCKH_v_undef_Mask(const SmallVectorImpl<int> &Mask, EVT VT) {
2710 int NumElems = VT.getVectorNumElements();
2711 if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16)
2714 for (int i = 0, j = NumElems / 2; i != NumElems; i += 2, ++j) {
2716 int BitI1 = Mask[i+1];
2717 if (!isUndefOrEqual(BitI, j))
2719 if (!isUndefOrEqual(BitI1, j))
2725 bool X86::isUNPCKH_v_undef_Mask(ShuffleVectorSDNode *N) {
2726 SmallVector<int, 8> M;
2728 return ::isUNPCKH_v_undef_Mask(M, N->getValueType(0));
2731 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
2732 /// specifies a shuffle of elements that is suitable for input to MOVSS,
2733 /// MOVSD, and MOVD, i.e. setting the lowest element.
2734 static bool isMOVLMask(const SmallVectorImpl<int> &Mask, EVT VT) {
2735 if (VT.getVectorElementType().getSizeInBits() < 32)
2738 int NumElts = VT.getVectorNumElements();
2740 if (!isUndefOrEqual(Mask[0], NumElts))
2743 for (int i = 1; i < NumElts; ++i)
2744 if (!isUndefOrEqual(Mask[i], i))
2750 bool X86::isMOVLMask(ShuffleVectorSDNode *N) {
2751 SmallVector<int, 8> M;
2753 return ::isMOVLMask(M, N->getValueType(0));
2756 /// isCommutedMOVL - Returns true if the shuffle mask is except the reverse
2757 /// of what x86 movss want. X86 movs requires the lowest element to be lowest
2758 /// element of vector 2 and the other elements to come from vector 1 in order.
2759 static bool isCommutedMOVLMask(const SmallVectorImpl<int> &Mask, EVT VT,
2760 bool V2IsSplat = false, bool V2IsUndef = false) {
2761 int NumOps = VT.getVectorNumElements();
2762 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16)
2765 if (!isUndefOrEqual(Mask[0], 0))
2768 for (int i = 1; i < NumOps; ++i)
2769 if (!(isUndefOrEqual(Mask[i], i+NumOps) ||
2770 (V2IsUndef && isUndefOrInRange(Mask[i], NumOps, NumOps*2)) ||
2771 (V2IsSplat && isUndefOrEqual(Mask[i], NumOps))))
2777 static bool isCommutedMOVL(ShuffleVectorSDNode *N, bool V2IsSplat = false,
2778 bool V2IsUndef = false) {
2779 SmallVector<int, 8> M;
2781 return isCommutedMOVLMask(M, N->getValueType(0), V2IsSplat, V2IsUndef);
2784 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
2785 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
2786 bool X86::isMOVSHDUPMask(ShuffleVectorSDNode *N) {
2787 if (N->getValueType(0).getVectorNumElements() != 4)
2790 // Expect 1, 1, 3, 3
2791 for (unsigned i = 0; i < 2; ++i) {
2792 int Elt = N->getMaskElt(i);
2793 if (Elt >= 0 && Elt != 1)
2798 for (unsigned i = 2; i < 4; ++i) {
2799 int Elt = N->getMaskElt(i);
2800 if (Elt >= 0 && Elt != 3)
2805 // Don't use movshdup if it can be done with a shufps.
2806 // FIXME: verify that matching u, u, 3, 3 is what we want.
2810 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
2811 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
2812 bool X86::isMOVSLDUPMask(ShuffleVectorSDNode *N) {
2813 if (N->getValueType(0).getVectorNumElements() != 4)
2816 // Expect 0, 0, 2, 2
2817 for (unsigned i = 0; i < 2; ++i)
2818 if (N->getMaskElt(i) > 0)
2822 for (unsigned i = 2; i < 4; ++i) {
2823 int Elt = N->getMaskElt(i);
2824 if (Elt >= 0 && Elt != 2)
2829 // Don't use movsldup if it can be done with a shufps.
2833 /// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand
2834 /// specifies a shuffle of elements that is suitable for input to MOVDDUP.
2835 bool X86::isMOVDDUPMask(ShuffleVectorSDNode *N) {
2836 int e = N->getValueType(0).getVectorNumElements() / 2;
2838 for (int i = 0; i < e; ++i)
2839 if (!isUndefOrEqual(N->getMaskElt(i), i))
2841 for (int i = 0; i < e; ++i)
2842 if (!isUndefOrEqual(N->getMaskElt(e+i), i))
2847 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
2848 /// the specified VECTOR_SHUFFLE mask with PSHUF* and SHUFP* instructions.
2849 unsigned X86::getShuffleSHUFImmediate(SDNode *N) {
2850 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
2851 int NumOperands = SVOp->getValueType(0).getVectorNumElements();
2853 unsigned Shift = (NumOperands == 4) ? 2 : 1;
2855 for (int i = 0; i < NumOperands; ++i) {
2856 int Val = SVOp->getMaskElt(NumOperands-i-1);
2857 if (Val < 0) Val = 0;
2858 if (Val >= NumOperands) Val -= NumOperands;
2860 if (i != NumOperands - 1)
2866 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
2867 /// the specified VECTOR_SHUFFLE mask with the PSHUFHW instruction.
2868 unsigned X86::getShufflePSHUFHWImmediate(SDNode *N) {
2869 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
2871 // 8 nodes, but we only care about the last 4.
2872 for (unsigned i = 7; i >= 4; --i) {
2873 int Val = SVOp->getMaskElt(i);
2882 /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
2883 /// the specified VECTOR_SHUFFLE mask with the PSHUFLW instruction.
2884 unsigned X86::getShufflePSHUFLWImmediate(SDNode *N) {
2885 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
2887 // 8 nodes, but we only care about the first 4.
2888 for (int i = 3; i >= 0; --i) {
2889 int Val = SVOp->getMaskElt(i);
2898 /// getShufflePALIGNRImmediate - Return the appropriate immediate to shuffle
2899 /// the specified VECTOR_SHUFFLE mask with the PALIGNR instruction.
2900 unsigned X86::getShufflePALIGNRImmediate(SDNode *N) {
2901 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
2902 EVT VVT = N->getValueType(0);
2903 unsigned EltSize = VVT.getVectorElementType().getSizeInBits() >> 3;
2907 for (i = 0, e = VVT.getVectorNumElements(); i != e; ++i) {
2908 Val = SVOp->getMaskElt(i);
2912 return (Val - i) * EltSize;
2915 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
2917 bool X86::isZeroNode(SDValue Elt) {
2918 return ((isa<ConstantSDNode>(Elt) &&
2919 cast<ConstantSDNode>(Elt)->getZExtValue() == 0) ||
2920 (isa<ConstantFPSDNode>(Elt) &&
2921 cast<ConstantFPSDNode>(Elt)->getValueAPF().isPosZero()));
2924 /// CommuteVectorShuffle - Swap vector_shuffle operands as well as values in
2925 /// their permute mask.
2926 static SDValue CommuteVectorShuffle(ShuffleVectorSDNode *SVOp,
2927 SelectionDAG &DAG) {
2928 EVT VT = SVOp->getValueType(0);
2929 unsigned NumElems = VT.getVectorNumElements();
2930 SmallVector<int, 8> MaskVec;
2932 for (unsigned i = 0; i != NumElems; ++i) {
2933 int idx = SVOp->getMaskElt(i);
2935 MaskVec.push_back(idx);
2936 else if (idx < (int)NumElems)
2937 MaskVec.push_back(idx + NumElems);
2939 MaskVec.push_back(idx - NumElems);
2941 return DAG.getVectorShuffle(VT, SVOp->getDebugLoc(), SVOp->getOperand(1),
2942 SVOp->getOperand(0), &MaskVec[0]);
2945 /// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming
2946 /// the two vector operands have swapped position.
2947 static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask, EVT VT) {
2948 unsigned NumElems = VT.getVectorNumElements();
2949 for (unsigned i = 0; i != NumElems; ++i) {
2953 else if (idx < (int)NumElems)
2954 Mask[i] = idx + NumElems;
2956 Mask[i] = idx - NumElems;
2960 /// ShouldXformToMOVHLPS - Return true if the node should be transformed to
2961 /// match movhlps. The lower half elements should come from upper half of
2962 /// V1 (and in order), and the upper half elements should come from the upper
2963 /// half of V2 (and in order).
2964 static bool ShouldXformToMOVHLPS(ShuffleVectorSDNode *Op) {
2965 if (Op->getValueType(0).getVectorNumElements() != 4)
2967 for (unsigned i = 0, e = 2; i != e; ++i)
2968 if (!isUndefOrEqual(Op->getMaskElt(i), i+2))
2970 for (unsigned i = 2; i != 4; ++i)
2971 if (!isUndefOrEqual(Op->getMaskElt(i), i+4))
2976 /// isScalarLoadToVector - Returns true if the node is a scalar load that
2977 /// is promoted to a vector. It also returns the LoadSDNode by reference if
2979 static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = NULL) {
2980 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR)
2982 N = N->getOperand(0).getNode();
2983 if (!ISD::isNON_EXTLoad(N))
2986 *LD = cast<LoadSDNode>(N);
2990 /// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to
2991 /// match movlp{s|d}. The lower half elements should come from lower half of
2992 /// V1 (and in order), and the upper half elements should come from the upper
2993 /// half of V2 (and in order). And since V1 will become the source of the
2994 /// MOVLP, it must be either a vector load or a scalar load to vector.
2995 static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2,
2996 ShuffleVectorSDNode *Op) {
2997 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1))
2999 // Is V2 is a vector load, don't do this transformation. We will try to use
3000 // load folding shufps op.
3001 if (ISD::isNON_EXTLoad(V2))
3004 unsigned NumElems = Op->getValueType(0).getVectorNumElements();
3006 if (NumElems != 2 && NumElems != 4)
3008 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
3009 if (!isUndefOrEqual(Op->getMaskElt(i), i))
3011 for (unsigned i = NumElems/2; i != NumElems; ++i)
3012 if (!isUndefOrEqual(Op->getMaskElt(i), i+NumElems))
3017 /// isSplatVector - Returns true if N is a BUILD_VECTOR node whose elements are
3019 static bool isSplatVector(SDNode *N) {
3020 if (N->getOpcode() != ISD::BUILD_VECTOR)
3023 SDValue SplatValue = N->getOperand(0);
3024 for (unsigned i = 1, e = N->getNumOperands(); i != e; ++i)
3025 if (N->getOperand(i) != SplatValue)
3030 /// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
3031 /// to an zero vector.
3032 /// FIXME: move to dag combiner / method on ShuffleVectorSDNode
3033 static bool isZeroShuffle(ShuffleVectorSDNode *N) {
3034 SDValue V1 = N->getOperand(0);
3035 SDValue V2 = N->getOperand(1);
3036 unsigned NumElems = N->getValueType(0).getVectorNumElements();
3037 for (unsigned i = 0; i != NumElems; ++i) {
3038 int Idx = N->getMaskElt(i);
3039 if (Idx >= (int)NumElems) {
3040 unsigned Opc = V2.getOpcode();
3041 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode()))
3043 if (Opc != ISD::BUILD_VECTOR ||
3044 !X86::isZeroNode(V2.getOperand(Idx-NumElems)))
3046 } else if (Idx >= 0) {
3047 unsigned Opc = V1.getOpcode();
3048 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode()))
3050 if (Opc != ISD::BUILD_VECTOR ||
3051 !X86::isZeroNode(V1.getOperand(Idx)))
3058 /// getZeroVector - Returns a vector of specified type with all zero elements.
3060 static SDValue getZeroVector(EVT VT, bool HasSSE2, SelectionDAG &DAG,
3062 assert(VT.isVector() && "Expected a vector type");
3064 // Always build zero vectors as <4 x i32> or <2 x i32> bitcasted to their dest
3065 // type. This ensures they get CSE'd.
3067 if (VT.getSizeInBits() == 64) { // MMX
3068 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
3069 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i32, Cst, Cst);
3070 } else if (HasSSE2) { // SSE2
3071 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
3072 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
3074 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
3075 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
3077 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vec);
3080 /// getOnesVector - Returns a vector of specified type with all bits set.
3082 static SDValue getOnesVector(EVT VT, SelectionDAG &DAG, DebugLoc dl) {
3083 assert(VT.isVector() && "Expected a vector type");
3085 // Always build ones vectors as <4 x i32> or <2 x i32> bitcasted to their dest
3086 // type. This ensures they get CSE'd.
3087 SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32);
3089 if (VT.getSizeInBits() == 64) // MMX
3090 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i32, Cst, Cst);
3092 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
3093 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vec);
3097 /// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements
3098 /// that point to V2 points to its first element.
3099 static SDValue NormalizeMask(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
3100 EVT VT = SVOp->getValueType(0);
3101 unsigned NumElems = VT.getVectorNumElements();
3103 bool Changed = false;
3104 SmallVector<int, 8> MaskVec;
3105 SVOp->getMask(MaskVec);
3107 for (unsigned i = 0; i != NumElems; ++i) {
3108 if (MaskVec[i] > (int)NumElems) {
3109 MaskVec[i] = NumElems;
3114 return DAG.getVectorShuffle(VT, SVOp->getDebugLoc(), SVOp->getOperand(0),
3115 SVOp->getOperand(1), &MaskVec[0]);
3116 return SDValue(SVOp, 0);
3119 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
3120 /// operation of specified width.
3121 static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
3123 unsigned NumElems = VT.getVectorNumElements();
3124 SmallVector<int, 8> Mask;
3125 Mask.push_back(NumElems);
3126 for (unsigned i = 1; i != NumElems; ++i)
3128 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
3131 /// getUnpackl - Returns a vector_shuffle node for an unpackl operation.
3132 static SDValue getUnpackl(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
3134 unsigned NumElems = VT.getVectorNumElements();
3135 SmallVector<int, 8> Mask;
3136 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
3138 Mask.push_back(i + NumElems);
3140 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
3143 /// getUnpackhMask - Returns a vector_shuffle node for an unpackh operation.
3144 static SDValue getUnpackh(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
3146 unsigned NumElems = VT.getVectorNumElements();
3147 unsigned Half = NumElems/2;
3148 SmallVector<int, 8> Mask;
3149 for (unsigned i = 0; i != Half; ++i) {
3150 Mask.push_back(i + Half);
3151 Mask.push_back(i + NumElems + Half);
3153 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
3156 /// PromoteSplat - Promote a splat of v4f32, v8i16 or v16i8 to v4i32.
3157 static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG,
3159 if (SV->getValueType(0).getVectorNumElements() <= 4)
3160 return SDValue(SV, 0);
3162 EVT PVT = MVT::v4f32;
3163 EVT VT = SV->getValueType(0);
3164 DebugLoc dl = SV->getDebugLoc();
3165 SDValue V1 = SV->getOperand(0);
3166 int NumElems = VT.getVectorNumElements();
3167 int EltNo = SV->getSplatIndex();
3169 // unpack elements to the correct location
3170 while (NumElems > 4) {
3171 if (EltNo < NumElems/2) {
3172 V1 = getUnpackl(DAG, dl, VT, V1, V1);
3174 V1 = getUnpackh(DAG, dl, VT, V1, V1);
3175 EltNo -= NumElems/2;
3180 // Perform the splat.
3181 int SplatMask[4] = { EltNo, EltNo, EltNo, EltNo };
3182 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, PVT, V1);
3183 V1 = DAG.getVectorShuffle(PVT, dl, V1, DAG.getUNDEF(PVT), &SplatMask[0]);
3184 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, V1);
3187 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
3188 /// vector of zero or undef vector. This produces a shuffle where the low
3189 /// element of V2 is swizzled into the zero/undef vector, landing at element
3190 /// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
3191 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
3192 bool isZero, bool HasSSE2,
3193 SelectionDAG &DAG) {
3194 EVT VT = V2.getValueType();
3196 ? getZeroVector(VT, HasSSE2, DAG, V2.getDebugLoc()) : DAG.getUNDEF(VT);
3197 unsigned NumElems = VT.getVectorNumElements();
3198 SmallVector<int, 16> MaskVec;
3199 for (unsigned i = 0; i != NumElems; ++i)
3200 // If this is the insertion idx, put the low elt of V2 here.
3201 MaskVec.push_back(i == Idx ? NumElems : i);
3202 return DAG.getVectorShuffle(VT, V2.getDebugLoc(), V1, V2, &MaskVec[0]);
3205 /// getNumOfConsecutiveZeros - Return the number of elements in a result of
3206 /// a shuffle that is zero.
3208 unsigned getNumOfConsecutiveZeros(ShuffleVectorSDNode *SVOp, int NumElems,
3209 bool Low, SelectionDAG &DAG) {
3210 unsigned NumZeros = 0;
3211 for (int i = 0; i < NumElems; ++i) {
3212 unsigned Index = Low ? i : NumElems-i-1;
3213 int Idx = SVOp->getMaskElt(Index);
3218 SDValue Elt = DAG.getShuffleScalarElt(SVOp, Index);
3219 if (Elt.getNode() && X86::isZeroNode(Elt))
3227 /// isVectorShift - Returns true if the shuffle can be implemented as a
3228 /// logical left or right shift of a vector.
3229 /// FIXME: split into pslldqi, psrldqi, palignr variants.
3230 static bool isVectorShift(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
3231 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
3232 int NumElems = SVOp->getValueType(0).getVectorNumElements();
3235 unsigned NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems, true, DAG);
3238 NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems, false, DAG);
3242 bool SeenV1 = false;
3243 bool SeenV2 = false;
3244 for (int i = NumZeros; i < NumElems; ++i) {
3245 int Val = isLeft ? (i - NumZeros) : i;
3246 int Idx = SVOp->getMaskElt(isLeft ? i : (i - NumZeros));
3258 if (SeenV1 && SeenV2)
3261 ShVal = SeenV1 ? SVOp->getOperand(0) : SVOp->getOperand(1);
3267 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
3269 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
3270 unsigned NumNonZero, unsigned NumZero,
3271 SelectionDAG &DAG, TargetLowering &TLI) {
3275 DebugLoc dl = Op.getDebugLoc();
3278 for (unsigned i = 0; i < 16; ++i) {
3279 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
3280 if (ThisIsNonZero && First) {
3282 V = getZeroVector(MVT::v8i16, true, DAG, dl);
3284 V = DAG.getUNDEF(MVT::v8i16);
3289 SDValue ThisElt(0, 0), LastElt(0, 0);
3290 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
3291 if (LastIsNonZero) {
3292 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
3293 MVT::i16, Op.getOperand(i-1));
3295 if (ThisIsNonZero) {
3296 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
3297 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
3298 ThisElt, DAG.getConstant(8, MVT::i8));
3300 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
3304 if (ThisElt.getNode())
3305 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
3306 DAG.getIntPtrConstant(i/2));
3310 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, V);
3313 /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
3315 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
3316 unsigned NumNonZero, unsigned NumZero,
3317 SelectionDAG &DAG, TargetLowering &TLI) {
3321 DebugLoc dl = Op.getDebugLoc();
3324 for (unsigned i = 0; i < 8; ++i) {
3325 bool isNonZero = (NonZeros & (1 << i)) != 0;
3329 V = getZeroVector(MVT::v8i16, true, DAG, dl);
3331 V = DAG.getUNDEF(MVT::v8i16);
3334 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
3335 MVT::v8i16, V, Op.getOperand(i),
3336 DAG.getIntPtrConstant(i));
3343 /// getVShift - Return a vector logical shift node.
3345 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
3346 unsigned NumBits, SelectionDAG &DAG,
3347 const TargetLowering &TLI, DebugLoc dl) {
3348 bool isMMX = VT.getSizeInBits() == 64;
3349 EVT ShVT = isMMX ? MVT::v1i64 : MVT::v2i64;
3350 unsigned Opc = isLeft ? X86ISD::VSHL : X86ISD::VSRL;
3351 SrcOp = DAG.getNode(ISD::BIT_CONVERT, dl, ShVT, SrcOp);
3352 return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
3353 DAG.getNode(Opc, dl, ShVT, SrcOp,
3354 DAG.getConstant(NumBits, TLI.getShiftAmountTy())));
3358 X86TargetLowering::LowerAsSplatVectorLoad(SDValue SrcOp, EVT VT, DebugLoc dl,
3359 SelectionDAG &DAG) {
3361 // Check if the scalar load can be widened into a vector load. And if
3362 // the address is "base + cst" see if the cst can be "absorbed" into
3363 // the shuffle mask.
3364 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) {
3365 SDValue Ptr = LD->getBasePtr();
3366 if (!ISD::isNormalLoad(LD) || LD->isVolatile())
3368 EVT PVT = LD->getValueType(0);
3369 if (PVT != MVT::i32 && PVT != MVT::f32)
3374 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) {
3375 FI = FINode->getIndex();
3377 } else if (Ptr.getOpcode() == ISD::ADD &&
3378 isa<ConstantSDNode>(Ptr.getOperand(1)) &&
3379 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
3380 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
3381 Offset = Ptr.getConstantOperandVal(1);
3382 Ptr = Ptr.getOperand(0);
3387 SDValue Chain = LD->getChain();
3388 // Make sure the stack object alignment is at least 16.
3389 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
3390 if (DAG.InferPtrAlignment(Ptr) < 16) {
3391 if (MFI->isFixedObjectIndex(FI)) {
3392 // Can't change the alignment. Reference stack + offset explicitly
3393 // if stack pointer is at least 16-byte aligned.
3394 unsigned StackAlign = Subtarget->getStackAlignment();
3395 if (StackAlign < 16)
3397 Offset = MFI->getObjectOffset(FI) + Offset;
3398 SDValue StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr,
3400 Ptr = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr,
3401 DAG.getConstant(Offset & ~15, getPointerTy()));
3404 MFI->setObjectAlignment(FI, 16);
3408 // (Offset % 16) must be multiple of 4. Then address is then
3409 // Ptr + (Offset & ~15).
3412 if ((Offset % 16) & 3)
3414 int64_t StartOffset = Offset & ~15;
3416 Ptr = DAG.getNode(ISD::ADD, Ptr.getDebugLoc(), Ptr.getValueType(),
3417 Ptr,DAG.getConstant(StartOffset, Ptr.getValueType()));
3419 int EltNo = (Offset - StartOffset) >> 2;
3420 int Mask[4] = { EltNo, EltNo, EltNo, EltNo };
3421 EVT VT = (PVT == MVT::i32) ? MVT::v4i32 : MVT::v4f32;
3422 SDValue V1 = DAG.getLoad(VT, dl, Chain, Ptr,LD->getSrcValue(),0);
3423 // Canonicalize it to a v4i32 shuffle.
3424 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v4i32, V1);
3425 return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
3426 DAG.getVectorShuffle(MVT::v4i32, dl, V1,
3427 DAG.getUNDEF(MVT::v4i32), &Mask[0]));
3434 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) {
3435 DebugLoc dl = Op.getDebugLoc();
3436 // All zero's are handled with pxor, all one's are handled with pcmpeqd.
3437 if (ISD::isBuildVectorAllZeros(Op.getNode())
3438 || ISD::isBuildVectorAllOnes(Op.getNode())) {
3439 // Canonicalize this to either <4 x i32> or <2 x i32> (SSE vs MMX) to
3440 // 1) ensure the zero vectors are CSE'd, and 2) ensure that i64 scalars are
3441 // eliminated on x86-32 hosts.
3442 if (Op.getValueType() == MVT::v4i32 || Op.getValueType() == MVT::v2i32)
3445 if (ISD::isBuildVectorAllOnes(Op.getNode()))
3446 return getOnesVector(Op.getValueType(), DAG, dl);
3447 return getZeroVector(Op.getValueType(), Subtarget->hasSSE2(), DAG, dl);
3450 EVT VT = Op.getValueType();
3451 EVT ExtVT = VT.getVectorElementType();
3452 unsigned EVTBits = ExtVT.getSizeInBits();
3454 unsigned NumElems = Op.getNumOperands();
3455 unsigned NumZero = 0;
3456 unsigned NumNonZero = 0;
3457 unsigned NonZeros = 0;
3458 bool IsAllConstants = true;
3459 SmallSet<SDValue, 8> Values;
3460 for (unsigned i = 0; i < NumElems; ++i) {
3461 SDValue Elt = Op.getOperand(i);
3462 if (Elt.getOpcode() == ISD::UNDEF)
3465 if (Elt.getOpcode() != ISD::Constant &&
3466 Elt.getOpcode() != ISD::ConstantFP)
3467 IsAllConstants = false;
3468 if (X86::isZeroNode(Elt))
3471 NonZeros |= (1 << i);
3476 if (NumNonZero == 0) {
3477 // All undef vector. Return an UNDEF. All zero vectors were handled above.
3478 return DAG.getUNDEF(VT);
3481 // Special case for single non-zero, non-undef, element.
3482 if (NumNonZero == 1) {
3483 unsigned Idx = CountTrailingZeros_32(NonZeros);
3484 SDValue Item = Op.getOperand(Idx);
3486 // If this is an insertion of an i64 value on x86-32, and if the top bits of
3487 // the value are obviously zero, truncate the value to i32 and do the
3488 // insertion that way. Only do this if the value is non-constant or if the
3489 // value is a constant being inserted into element 0. It is cheaper to do
3490 // a constant pool load than it is to do a movd + shuffle.
3491 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
3492 (!IsAllConstants || Idx == 0)) {
3493 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
3494 // Handle MMX and SSE both.
3495 EVT VecVT = VT == MVT::v2i64 ? MVT::v4i32 : MVT::v2i32;
3496 unsigned VecElts = VT == MVT::v2i64 ? 4 : 2;
3498 // Truncate the value (which may itself be a constant) to i32, and
3499 // convert it to a vector with movd (S2V+shuffle to zero extend).
3500 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
3501 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
3502 Item = getShuffleVectorZeroOrUndef(Item, 0, true,
3503 Subtarget->hasSSE2(), DAG);
3505 // Now we have our 32-bit value zero extended in the low element of
3506 // a vector. If Idx != 0, swizzle it into place.
3508 SmallVector<int, 4> Mask;
3509 Mask.push_back(Idx);
3510 for (unsigned i = 1; i != VecElts; ++i)
3512 Item = DAG.getVectorShuffle(VecVT, dl, Item,
3513 DAG.getUNDEF(Item.getValueType()),
3516 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Item);
3520 // If we have a constant or non-constant insertion into the low element of
3521 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
3522 // the rest of the elements. This will be matched as movd/movq/movss/movsd
3523 // depending on what the source datatype is.
3526 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
3527 } else if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
3528 (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
3529 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
3530 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
3531 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget->hasSSE2(),
3533 } else if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
3534 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
3535 EVT MiddleVT = VT.getSizeInBits() == 64 ? MVT::v2i32 : MVT::v4i32;
3536 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MiddleVT, Item);
3537 Item = getShuffleVectorZeroOrUndef(Item, 0, true,
3538 Subtarget->hasSSE2(), DAG);
3539 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Item);
3543 // Is it a vector logical left shift?
3544 if (NumElems == 2 && Idx == 1 &&
3545 X86::isZeroNode(Op.getOperand(0)) &&
3546 !X86::isZeroNode(Op.getOperand(1))) {
3547 unsigned NumBits = VT.getSizeInBits();
3548 return getVShift(true, VT,
3549 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
3550 VT, Op.getOperand(1)),
3551 NumBits/2, DAG, *this, dl);
3554 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
3557 // Otherwise, if this is a vector with i32 or f32 elements, and the element
3558 // is a non-constant being inserted into an element other than the low one,
3559 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
3560 // movd/movss) to move this into the low element, then shuffle it into
3562 if (EVTBits == 32) {
3563 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
3565 // Turn it into a shuffle of zero and zero-extended scalar to vector.
3566 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0,
3567 Subtarget->hasSSE2(), DAG);
3568 SmallVector<int, 8> MaskVec;
3569 for (unsigned i = 0; i < NumElems; i++)
3570 MaskVec.push_back(i == Idx ? 0 : 1);
3571 return DAG.getVectorShuffle(VT, dl, Item, DAG.getUNDEF(VT), &MaskVec[0]);
3575 // Splat is obviously ok. Let legalizer expand it to a shuffle.
3576 if (Values.size() == 1) {
3577 if (EVTBits == 32) {
3578 // Instead of a shuffle like this:
3579 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
3580 // Check if it's possible to issue this instead.
3581 // shuffle (vload ptr)), undef, <1, 1, 1, 1>
3582 unsigned Idx = CountTrailingZeros_32(NonZeros);
3583 SDValue Item = Op.getOperand(Idx);
3584 if (Op.getNode()->isOnlyUserOf(Item.getNode()))
3585 return LowerAsSplatVectorLoad(Item, VT, dl, DAG);
3590 // A vector full of immediates; various special cases are already
3591 // handled, so this is best done with a single constant-pool load.
3595 // Let legalizer expand 2-wide build_vectors.
3596 if (EVTBits == 64) {
3597 if (NumNonZero == 1) {
3598 // One half is zero or undef.
3599 unsigned Idx = CountTrailingZeros_32(NonZeros);
3600 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
3601 Op.getOperand(Idx));
3602 return getShuffleVectorZeroOrUndef(V2, Idx, true,
3603 Subtarget->hasSSE2(), DAG);
3608 // If element VT is < 32 bits, convert it to inserts into a zero vector.
3609 if (EVTBits == 8 && NumElems == 16) {
3610 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
3612 if (V.getNode()) return V;
3615 if (EVTBits == 16 && NumElems == 8) {
3616 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
3618 if (V.getNode()) return V;
3621 // If element VT is == 32 bits, turn it into a number of shuffles.
3622 SmallVector<SDValue, 8> V;
3624 if (NumElems == 4 && NumZero > 0) {
3625 for (unsigned i = 0; i < 4; ++i) {
3626 bool isZero = !(NonZeros & (1 << i));
3628 V[i] = getZeroVector(VT, Subtarget->hasSSE2(), DAG, dl);
3630 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
3633 for (unsigned i = 0; i < 2; ++i) {
3634 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
3637 V[i] = V[i*2]; // Must be a zero vector.
3640 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
3643 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
3646 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
3651 SmallVector<int, 8> MaskVec;
3652 bool Reverse = (NonZeros & 0x3) == 2;
3653 for (unsigned i = 0; i < 2; ++i)
3654 MaskVec.push_back(Reverse ? 1-i : i);
3655 Reverse = ((NonZeros & (0x3 << 2)) >> 2) == 2;
3656 for (unsigned i = 0; i < 2; ++i)
3657 MaskVec.push_back(Reverse ? 1-i+NumElems : i+NumElems);
3658 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
3661 if (Values.size() > 2) {
3662 // If we have SSE 4.1, Expand into a number of inserts unless the number of
3663 // values to be inserted is equal to the number of elements, in which case
3664 // use the unpack code below in the hopes of matching the consecutive elts
3665 // load merge pattern for shuffles.
3666 // FIXME: We could probably just check that here directly.
3667 if (Values.size() < NumElems && VT.getSizeInBits() == 128 &&
3668 getSubtarget()->hasSSE41()) {
3669 V[0] = DAG.getUNDEF(VT);
3670 for (unsigned i = 0; i < NumElems; ++i)
3671 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
3672 V[0] = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, V[0],
3673 Op.getOperand(i), DAG.getIntPtrConstant(i));
3676 // Expand into a number of unpckl*.
3678 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
3679 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
3680 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
3681 for (unsigned i = 0; i < NumElems; ++i)
3682 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
3684 while (NumElems != 0) {
3685 for (unsigned i = 0; i < NumElems; ++i)
3686 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + NumElems]);
3695 // v8i16 shuffles - Prefer shuffles in the following order:
3696 // 1. [all] pshuflw, pshufhw, optional move
3697 // 2. [ssse3] 1 x pshufb
3698 // 3. [ssse3] 2 x pshufb + 1 x por
3699 // 4. [all] mov + pshuflw + pshufhw + N x (pextrw + pinsrw)
3701 SDValue LowerVECTOR_SHUFFLEv8i16(ShuffleVectorSDNode *SVOp,
3702 SelectionDAG &DAG, X86TargetLowering &TLI) {
3703 SDValue V1 = SVOp->getOperand(0);
3704 SDValue V2 = SVOp->getOperand(1);
3705 DebugLoc dl = SVOp->getDebugLoc();
3706 SmallVector<int, 8> MaskVals;
3708 // Determine if more than 1 of the words in each of the low and high quadwords
3709 // of the result come from the same quadword of one of the two inputs. Undef
3710 // mask values count as coming from any quadword, for better codegen.
3711 SmallVector<unsigned, 4> LoQuad(4);
3712 SmallVector<unsigned, 4> HiQuad(4);
3713 BitVector InputQuads(4);
3714 for (unsigned i = 0; i < 8; ++i) {
3715 SmallVectorImpl<unsigned> &Quad = i < 4 ? LoQuad : HiQuad;
3716 int EltIdx = SVOp->getMaskElt(i);
3717 MaskVals.push_back(EltIdx);
3726 InputQuads.set(EltIdx / 4);
3729 int BestLoQuad = -1;
3730 unsigned MaxQuad = 1;
3731 for (unsigned i = 0; i < 4; ++i) {
3732 if (LoQuad[i] > MaxQuad) {
3734 MaxQuad = LoQuad[i];
3738 int BestHiQuad = -1;
3740 for (unsigned i = 0; i < 4; ++i) {
3741 if (HiQuad[i] > MaxQuad) {
3743 MaxQuad = HiQuad[i];
3747 // For SSSE3, If all 8 words of the result come from only 1 quadword of each
3748 // of the two input vectors, shuffle them into one input vector so only a
3749 // single pshufb instruction is necessary. If There are more than 2 input
3750 // quads, disable the next transformation since it does not help SSSE3.
3751 bool V1Used = InputQuads[0] || InputQuads[1];
3752 bool V2Used = InputQuads[2] || InputQuads[3];
3753 if (TLI.getSubtarget()->hasSSSE3()) {
3754 if (InputQuads.count() == 2 && V1Used && V2Used) {
3755 BestLoQuad = InputQuads.find_first();
3756 BestHiQuad = InputQuads.find_next(BestLoQuad);
3758 if (InputQuads.count() > 2) {
3764 // If BestLoQuad or BestHiQuad are set, shuffle the quads together and update
3765 // the shuffle mask. If a quad is scored as -1, that means that it contains
3766 // words from all 4 input quadwords.
3768 if (BestLoQuad >= 0 || BestHiQuad >= 0) {
3769 SmallVector<int, 8> MaskV;
3770 MaskV.push_back(BestLoQuad < 0 ? 0 : BestLoQuad);
3771 MaskV.push_back(BestHiQuad < 0 ? 1 : BestHiQuad);
3772 NewV = DAG.getVectorShuffle(MVT::v2i64, dl,
3773 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64, V1),
3774 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64, V2), &MaskV[0]);
3775 NewV = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, NewV);
3777 // Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the
3778 // source words for the shuffle, to aid later transformations.
3779 bool AllWordsInNewV = true;
3780 bool InOrder[2] = { true, true };
3781 for (unsigned i = 0; i != 8; ++i) {
3782 int idx = MaskVals[i];
3784 InOrder[i/4] = false;
3785 if (idx < 0 || (idx/4) == BestLoQuad || (idx/4) == BestHiQuad)
3787 AllWordsInNewV = false;
3791 bool pshuflw = AllWordsInNewV, pshufhw = AllWordsInNewV;
3792 if (AllWordsInNewV) {
3793 for (int i = 0; i != 8; ++i) {
3794 int idx = MaskVals[i];
3797 idx = MaskVals[i] = (idx / 4) == BestLoQuad ? (idx & 3) : (idx & 3) + 4;
3798 if ((idx != i) && idx < 4)
3800 if ((idx != i) && idx > 3)
3809 // If we've eliminated the use of V2, and the new mask is a pshuflw or
3810 // pshufhw, that's as cheap as it gets. Return the new shuffle.
3811 if ((pshufhw && InOrder[0]) || (pshuflw && InOrder[1])) {
3812 return DAG.getVectorShuffle(MVT::v8i16, dl, NewV,
3813 DAG.getUNDEF(MVT::v8i16), &MaskVals[0]);
3817 // If we have SSSE3, and all words of the result are from 1 input vector,
3818 // case 2 is generated, otherwise case 3 is generated. If no SSSE3
3819 // is present, fall back to case 4.
3820 if (TLI.getSubtarget()->hasSSSE3()) {
3821 SmallVector<SDValue,16> pshufbMask;
3823 // If we have elements from both input vectors, set the high bit of the
3824 // shuffle mask element to zero out elements that come from V2 in the V1
3825 // mask, and elements that come from V1 in the V2 mask, so that the two
3826 // results can be OR'd together.
3827 bool TwoInputs = V1Used && V2Used;
3828 for (unsigned i = 0; i != 8; ++i) {
3829 int EltIdx = MaskVals[i] * 2;
3830 if (TwoInputs && (EltIdx >= 16)) {
3831 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
3832 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
3835 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
3836 pshufbMask.push_back(DAG.getConstant(EltIdx+1, MVT::i8));
3838 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, V1);
3839 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
3840 DAG.getNode(ISD::BUILD_VECTOR, dl,
3841 MVT::v16i8, &pshufbMask[0], 16));
3843 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, V1);
3845 // Calculate the shuffle mask for the second input, shuffle it, and
3846 // OR it with the first shuffled input.
3848 for (unsigned i = 0; i != 8; ++i) {
3849 int EltIdx = MaskVals[i] * 2;
3851 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
3852 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
3855 pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8));
3856 pshufbMask.push_back(DAG.getConstant(EltIdx - 15, MVT::i8));
3858 V2 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, V2);
3859 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
3860 DAG.getNode(ISD::BUILD_VECTOR, dl,
3861 MVT::v16i8, &pshufbMask[0], 16));
3862 V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
3863 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, V1);
3866 // If BestLoQuad >= 0, generate a pshuflw to put the low elements in order,
3867 // and update MaskVals with new element order.
3868 BitVector InOrder(8);
3869 if (BestLoQuad >= 0) {
3870 SmallVector<int, 8> MaskV;
3871 for (int i = 0; i != 4; ++i) {
3872 int idx = MaskVals[i];
3874 MaskV.push_back(-1);
3876 } else if ((idx / 4) == BestLoQuad) {
3877 MaskV.push_back(idx & 3);
3880 MaskV.push_back(-1);
3883 for (unsigned i = 4; i != 8; ++i)
3885 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
3889 // If BestHi >= 0, generate a pshufhw to put the high elements in order,
3890 // and update MaskVals with the new element order.
3891 if (BestHiQuad >= 0) {
3892 SmallVector<int, 8> MaskV;
3893 for (unsigned i = 0; i != 4; ++i)
3895 for (unsigned i = 4; i != 8; ++i) {
3896 int idx = MaskVals[i];
3898 MaskV.push_back(-1);
3900 } else if ((idx / 4) == BestHiQuad) {
3901 MaskV.push_back((idx & 3) + 4);
3904 MaskV.push_back(-1);
3907 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
3911 // In case BestHi & BestLo were both -1, which means each quadword has a word
3912 // from each of the four input quadwords, calculate the InOrder bitvector now
3913 // before falling through to the insert/extract cleanup.
3914 if (BestLoQuad == -1 && BestHiQuad == -1) {
3916 for (int i = 0; i != 8; ++i)
3917 if (MaskVals[i] < 0 || MaskVals[i] == i)
3921 // The other elements are put in the right place using pextrw and pinsrw.
3922 for (unsigned i = 0; i != 8; ++i) {
3925 int EltIdx = MaskVals[i];
3928 SDValue ExtOp = (EltIdx < 8)
3929 ? DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1,
3930 DAG.getIntPtrConstant(EltIdx))
3931 : DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2,
3932 DAG.getIntPtrConstant(EltIdx - 8));
3933 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp,
3934 DAG.getIntPtrConstant(i));
3939 // v16i8 shuffles - Prefer shuffles in the following order:
3940 // 1. [ssse3] 1 x pshufb
3941 // 2. [ssse3] 2 x pshufb + 1 x por
3942 // 3. [all] v8i16 shuffle + N x pextrw + rotate + pinsrw
3944 SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp,
3945 SelectionDAG &DAG, X86TargetLowering &TLI) {
3946 SDValue V1 = SVOp->getOperand(0);
3947 SDValue V2 = SVOp->getOperand(1);
3948 DebugLoc dl = SVOp->getDebugLoc();
3949 SmallVector<int, 16> MaskVals;
3950 SVOp->getMask(MaskVals);
3952 // If we have SSSE3, case 1 is generated when all result bytes come from
3953 // one of the inputs. Otherwise, case 2 is generated. If no SSSE3 is
3954 // present, fall back to case 3.
3955 // FIXME: kill V2Only once shuffles are canonizalized by getNode.
3958 for (unsigned i = 0; i < 16; ++i) {
3959 int EltIdx = MaskVals[i];
3968 // If SSSE3, use 1 pshufb instruction per vector with elements in the result.
3969 if (TLI.getSubtarget()->hasSSSE3()) {
3970 SmallVector<SDValue,16> pshufbMask;
3972 // If all result elements are from one input vector, then only translate
3973 // undef mask values to 0x80 (zero out result) in the pshufb mask.
3975 // Otherwise, we have elements from both input vectors, and must zero out
3976 // elements that come from V2 in the first mask, and V1 in the second mask
3977 // so that we can OR them together.
3978 bool TwoInputs = !(V1Only || V2Only);
3979 for (unsigned i = 0; i != 16; ++i) {
3980 int EltIdx = MaskVals[i];
3981 if (EltIdx < 0 || (TwoInputs && EltIdx >= 16)) {
3982 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
3985 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
3987 // If all the elements are from V2, assign it to V1 and return after
3988 // building the first pshufb.
3991 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
3992 DAG.getNode(ISD::BUILD_VECTOR, dl,
3993 MVT::v16i8, &pshufbMask[0], 16));
3997 // Calculate the shuffle mask for the second input, shuffle it, and
3998 // OR it with the first shuffled input.
4000 for (unsigned i = 0; i != 16; ++i) {
4001 int EltIdx = MaskVals[i];
4003 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
4006 pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8));
4008 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
4009 DAG.getNode(ISD::BUILD_VECTOR, dl,
4010 MVT::v16i8, &pshufbMask[0], 16));
4011 return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
4014 // No SSSE3 - Calculate in place words and then fix all out of place words
4015 // With 0-16 extracts & inserts. Worst case is 16 bytes out of order from
4016 // the 16 different words that comprise the two doublequadword input vectors.
4017 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, V1);
4018 V2 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, V2);
4019 SDValue NewV = V2Only ? V2 : V1;
4020 for (int i = 0; i != 8; ++i) {
4021 int Elt0 = MaskVals[i*2];
4022 int Elt1 = MaskVals[i*2+1];
4024 // This word of the result is all undef, skip it.
4025 if (Elt0 < 0 && Elt1 < 0)
4028 // This word of the result is already in the correct place, skip it.
4029 if (V1Only && (Elt0 == i*2) && (Elt1 == i*2+1))
4031 if (V2Only && (Elt0 == i*2+16) && (Elt1 == i*2+17))
4034 SDValue Elt0Src = Elt0 < 16 ? V1 : V2;
4035 SDValue Elt1Src = Elt1 < 16 ? V1 : V2;
4038 // If Elt0 and Elt1 are defined, are consecutive, and can be load
4039 // using a single extract together, load it and store it.
4040 if ((Elt0 >= 0) && ((Elt0 + 1) == Elt1) && ((Elt0 & 1) == 0)) {
4041 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
4042 DAG.getIntPtrConstant(Elt1 / 2));
4043 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
4044 DAG.getIntPtrConstant(i));
4048 // If Elt1 is defined, extract it from the appropriate source. If the
4049 // source byte is not also odd, shift the extracted word left 8 bits
4050 // otherwise clear the bottom 8 bits if we need to do an or.
4052 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
4053 DAG.getIntPtrConstant(Elt1 / 2));
4054 if ((Elt1 & 1) == 0)
4055 InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt,
4056 DAG.getConstant(8, TLI.getShiftAmountTy()));
4058 InsElt = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt,
4059 DAG.getConstant(0xFF00, MVT::i16));
4061 // If Elt0 is defined, extract it from the appropriate source. If the
4062 // source byte is not also even, shift the extracted word right 8 bits. If
4063 // Elt1 was also defined, OR the extracted values together before
4064 // inserting them in the result.
4066 SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16,
4067 Elt0Src, DAG.getIntPtrConstant(Elt0 / 2));
4068 if ((Elt0 & 1) != 0)
4069 InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0,
4070 DAG.getConstant(8, TLI.getShiftAmountTy()));
4072 InsElt0 = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt0,
4073 DAG.getConstant(0x00FF, MVT::i16));
4074 InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0)
4077 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
4078 DAG.getIntPtrConstant(i));
4080 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, NewV);
4083 /// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide
4084 /// ones, or rewriting v4i32 / v2f32 as 2 wide ones if possible. This can be
4085 /// done when every pair / quad of shuffle mask elements point to elements in
4086 /// the right sequence. e.g.
4087 /// vector_shuffle <>, <>, < 3, 4, | 10, 11, | 0, 1, | 14, 15>
4089 SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp,
4091 TargetLowering &TLI, DebugLoc dl) {
4092 EVT VT = SVOp->getValueType(0);
4093 SDValue V1 = SVOp->getOperand(0);
4094 SDValue V2 = SVOp->getOperand(1);
4095 unsigned NumElems = VT.getVectorNumElements();
4096 unsigned NewWidth = (NumElems == 4) ? 2 : 4;
4097 EVT MaskVT = MVT::getIntVectorWithNumElements(NewWidth);
4098 EVT MaskEltVT = MaskVT.getVectorElementType();
4100 switch (VT.getSimpleVT().SimpleTy) {
4101 default: assert(false && "Unexpected!");
4102 case MVT::v4f32: NewVT = MVT::v2f64; break;
4103 case MVT::v4i32: NewVT = MVT::v2i64; break;
4104 case MVT::v8i16: NewVT = MVT::v4i32; break;
4105 case MVT::v16i8: NewVT = MVT::v4i32; break;
4108 if (NewWidth == 2) {
4114 int Scale = NumElems / NewWidth;
4115 SmallVector<int, 8> MaskVec;
4116 for (unsigned i = 0; i < NumElems; i += Scale) {
4118 for (int j = 0; j < Scale; ++j) {
4119 int EltIdx = SVOp->getMaskElt(i+j);
4123 StartIdx = EltIdx - (EltIdx % Scale);
4124 if (EltIdx != StartIdx + j)
4128 MaskVec.push_back(-1);
4130 MaskVec.push_back(StartIdx / Scale);
4133 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, NewVT, V1);
4134 V2 = DAG.getNode(ISD::BIT_CONVERT, dl, NewVT, V2);
4135 return DAG.getVectorShuffle(NewVT, dl, V1, V2, &MaskVec[0]);
4138 /// getVZextMovL - Return a zero-extending vector move low node.
4140 static SDValue getVZextMovL(EVT VT, EVT OpVT,
4141 SDValue SrcOp, SelectionDAG &DAG,
4142 const X86Subtarget *Subtarget, DebugLoc dl) {
4143 if (VT == MVT::v2f64 || VT == MVT::v4f32) {
4144 LoadSDNode *LD = NULL;
4145 if (!isScalarLoadToVector(SrcOp.getNode(), &LD))
4146 LD = dyn_cast<LoadSDNode>(SrcOp);
4148 // movssrr and movsdrr do not clear top bits. Try to use movd, movq
4150 MVT ExtVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32;
4151 if ((ExtVT.SimpleTy != MVT::i64 || Subtarget->is64Bit()) &&
4152 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR &&
4153 SrcOp.getOperand(0).getOpcode() == ISD::BIT_CONVERT &&
4154 SrcOp.getOperand(0).getOperand(0).getValueType() == ExtVT) {
4156 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32;
4157 return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
4158 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
4159 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
4167 return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
4168 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
4169 DAG.getNode(ISD::BIT_CONVERT, dl,
4173 /// LowerVECTOR_SHUFFLE_4wide - Handle all 4 wide cases with a number of
4176 LowerVECTOR_SHUFFLE_4wide(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
4177 SDValue V1 = SVOp->getOperand(0);
4178 SDValue V2 = SVOp->getOperand(1);
4179 DebugLoc dl = SVOp->getDebugLoc();
4180 EVT VT = SVOp->getValueType(0);
4182 SmallVector<std::pair<int, int>, 8> Locs;
4184 SmallVector<int, 8> Mask1(4U, -1);
4185 SmallVector<int, 8> PermMask;
4186 SVOp->getMask(PermMask);
4190 for (unsigned i = 0; i != 4; ++i) {
4191 int Idx = PermMask[i];
4193 Locs[i] = std::make_pair(-1, -1);
4195 assert(Idx < 8 && "Invalid VECTOR_SHUFFLE index!");
4197 Locs[i] = std::make_pair(0, NumLo);
4201 Locs[i] = std::make_pair(1, NumHi);
4203 Mask1[2+NumHi] = Idx;
4209 if (NumLo <= 2 && NumHi <= 2) {
4210 // If no more than two elements come from either vector. This can be
4211 // implemented with two shuffles. First shuffle gather the elements.
4212 // The second shuffle, which takes the first shuffle as both of its
4213 // vector operands, put the elements into the right order.
4214 V1 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
4216 SmallVector<int, 8> Mask2(4U, -1);
4218 for (unsigned i = 0; i != 4; ++i) {
4219 if (Locs[i].first == -1)
4222 unsigned Idx = (i < 2) ? 0 : 4;
4223 Idx += Locs[i].first * 2 + Locs[i].second;
4228 return DAG.getVectorShuffle(VT, dl, V1, V1, &Mask2[0]);
4229 } else if (NumLo == 3 || NumHi == 3) {
4230 // Otherwise, we must have three elements from one vector, call it X, and
4231 // one element from the other, call it Y. First, use a shufps to build an
4232 // intermediate vector with the one element from Y and the element from X
4233 // that will be in the same half in the final destination (the indexes don't
4234 // matter). Then, use a shufps to build the final vector, taking the half
4235 // containing the element from Y from the intermediate, and the other half
4238 // Normalize it so the 3 elements come from V1.
4239 CommuteVectorShuffleMask(PermMask, VT);
4243 // Find the element from V2.
4245 for (HiIndex = 0; HiIndex < 3; ++HiIndex) {
4246 int Val = PermMask[HiIndex];
4253 Mask1[0] = PermMask[HiIndex];
4255 Mask1[2] = PermMask[HiIndex^1];
4257 V2 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
4260 Mask1[0] = PermMask[0];
4261 Mask1[1] = PermMask[1];
4262 Mask1[2] = HiIndex & 1 ? 6 : 4;
4263 Mask1[3] = HiIndex & 1 ? 4 : 6;
4264 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
4266 Mask1[0] = HiIndex & 1 ? 2 : 0;
4267 Mask1[1] = HiIndex & 1 ? 0 : 2;
4268 Mask1[2] = PermMask[2];
4269 Mask1[3] = PermMask[3];
4274 return DAG.getVectorShuffle(VT, dl, V2, V1, &Mask1[0]);
4278 // Break it into (shuffle shuffle_hi, shuffle_lo).
4280 SmallVector<int,8> LoMask(4U, -1);
4281 SmallVector<int,8> HiMask(4U, -1);
4283 SmallVector<int,8> *MaskPtr = &LoMask;
4284 unsigned MaskIdx = 0;
4287 for (unsigned i = 0; i != 4; ++i) {
4294 int Idx = PermMask[i];
4296 Locs[i] = std::make_pair(-1, -1);
4297 } else if (Idx < 4) {
4298 Locs[i] = std::make_pair(MaskIdx, LoIdx);
4299 (*MaskPtr)[LoIdx] = Idx;
4302 Locs[i] = std::make_pair(MaskIdx, HiIdx);
4303 (*MaskPtr)[HiIdx] = Idx;
4308 SDValue LoShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &LoMask[0]);
4309 SDValue HiShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &HiMask[0]);
4310 SmallVector<int, 8> MaskOps;
4311 for (unsigned i = 0; i != 4; ++i) {
4312 if (Locs[i].first == -1) {
4313 MaskOps.push_back(-1);
4315 unsigned Idx = Locs[i].first * 4 + Locs[i].second;
4316 MaskOps.push_back(Idx);
4319 return DAG.getVectorShuffle(VT, dl, LoShuffle, HiShuffle, &MaskOps[0]);
4323 X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) {
4324 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
4325 SDValue V1 = Op.getOperand(0);
4326 SDValue V2 = Op.getOperand(1);
4327 EVT VT = Op.getValueType();
4328 DebugLoc dl = Op.getDebugLoc();
4329 unsigned NumElems = VT.getVectorNumElements();
4330 bool isMMX = VT.getSizeInBits() == 64;
4331 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
4332 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
4333 bool V1IsSplat = false;
4334 bool V2IsSplat = false;
4336 if (isZeroShuffle(SVOp))
4337 return getZeroVector(VT, Subtarget->hasSSE2(), DAG, dl);
4339 // Promote splats to v4f32.
4340 if (SVOp->isSplat()) {
4341 if (isMMX || NumElems < 4)
4343 return PromoteSplat(SVOp, DAG, Subtarget->hasSSE2());
4346 // If the shuffle can be profitably rewritten as a narrower shuffle, then
4348 if (VT == MVT::v8i16 || VT == MVT::v16i8) {
4349 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, *this, dl);
4350 if (NewOp.getNode())
4351 return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
4352 LowerVECTOR_SHUFFLE(NewOp, DAG));
4353 } else if ((VT == MVT::v4i32 || (VT == MVT::v4f32 && Subtarget->hasSSE2()))) {
4354 // FIXME: Figure out a cleaner way to do this.
4355 // Try to make use of movq to zero out the top part.
4356 if (ISD::isBuildVectorAllZeros(V2.getNode())) {
4357 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, *this, dl);
4358 if (NewOp.getNode()) {
4359 if (isCommutedMOVL(cast<ShuffleVectorSDNode>(NewOp), true, false))
4360 return getVZextMovL(VT, NewOp.getValueType(), NewOp.getOperand(0),
4361 DAG, Subtarget, dl);
4363 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) {
4364 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, *this, dl);
4365 if (NewOp.getNode() && X86::isMOVLMask(cast<ShuffleVectorSDNode>(NewOp)))
4366 return getVZextMovL(VT, NewOp.getValueType(), NewOp.getOperand(1),
4367 DAG, Subtarget, dl);
4371 if (X86::isPSHUFDMask(SVOp))
4374 // Check if this can be converted into a logical shift.
4375 bool isLeft = false;
4378 bool isShift = getSubtarget()->hasSSE2() &&
4379 isVectorShift(SVOp, DAG, isLeft, ShVal, ShAmt);
4380 if (isShift && ShVal.hasOneUse()) {
4381 // If the shifted value has multiple uses, it may be cheaper to use
4382 // v_set0 + movlhps or movhlps, etc.
4383 EVT EltVT = VT.getVectorElementType();
4384 ShAmt *= EltVT.getSizeInBits();
4385 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
4388 if (X86::isMOVLMask(SVOp)) {
4391 if (ISD::isBuildVectorAllZeros(V1.getNode()))
4392 return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl);
4397 // FIXME: fold these into legal mask.
4398 if (!isMMX && (X86::isMOVSHDUPMask(SVOp) ||
4399 X86::isMOVSLDUPMask(SVOp) ||
4400 X86::isMOVHLPSMask(SVOp) ||
4401 X86::isMOVLHPSMask(SVOp) ||
4402 X86::isMOVLPMask(SVOp)))
4405 if (ShouldXformToMOVHLPS(SVOp) ||
4406 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), SVOp))
4407 return CommuteVectorShuffle(SVOp, DAG);
4410 // No better options. Use a vshl / vsrl.
4411 EVT EltVT = VT.getVectorElementType();
4412 ShAmt *= EltVT.getSizeInBits();
4413 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
4416 bool Commuted = false;
4417 // FIXME: This should also accept a bitcast of a splat? Be careful, not
4418 // 1,1,1,1 -> v8i16 though.
4419 V1IsSplat = isSplatVector(V1.getNode());
4420 V2IsSplat = isSplatVector(V2.getNode());
4422 // Canonicalize the splat or undef, if present, to be on the RHS.
4423 if ((V1IsSplat || V1IsUndef) && !(V2IsSplat || V2IsUndef)) {
4424 Op = CommuteVectorShuffle(SVOp, DAG);
4425 SVOp = cast<ShuffleVectorSDNode>(Op);
4426 V1 = SVOp->getOperand(0);
4427 V2 = SVOp->getOperand(1);
4428 std::swap(V1IsSplat, V2IsSplat);
4429 std::swap(V1IsUndef, V2IsUndef);
4433 if (isCommutedMOVL(SVOp, V2IsSplat, V2IsUndef)) {
4434 // Shuffling low element of v1 into undef, just return v1.
4437 // If V2 is a splat, the mask may be malformed such as <4,3,3,3>, which
4438 // the instruction selector will not match, so get a canonical MOVL with
4439 // swapped operands to undo the commute.
4440 return getMOVL(DAG, dl, VT, V2, V1);
4443 if (X86::isUNPCKL_v_undef_Mask(SVOp) ||
4444 X86::isUNPCKH_v_undef_Mask(SVOp) ||
4445 X86::isUNPCKLMask(SVOp) ||
4446 X86::isUNPCKHMask(SVOp))
4450 // Normalize mask so all entries that point to V2 points to its first
4451 // element then try to match unpck{h|l} again. If match, return a
4452 // new vector_shuffle with the corrected mask.
4453 SDValue NewMask = NormalizeMask(SVOp, DAG);
4454 ShuffleVectorSDNode *NSVOp = cast<ShuffleVectorSDNode>(NewMask);
4455 if (NSVOp != SVOp) {
4456 if (X86::isUNPCKLMask(NSVOp, true)) {
4458 } else if (X86::isUNPCKHMask(NSVOp, true)) {
4465 // Commute is back and try unpck* again.
4466 // FIXME: this seems wrong.
4467 SDValue NewOp = CommuteVectorShuffle(SVOp, DAG);
4468 ShuffleVectorSDNode *NewSVOp = cast<ShuffleVectorSDNode>(NewOp);
4469 if (X86::isUNPCKL_v_undef_Mask(NewSVOp) ||
4470 X86::isUNPCKH_v_undef_Mask(NewSVOp) ||
4471 X86::isUNPCKLMask(NewSVOp) ||
4472 X86::isUNPCKHMask(NewSVOp))
4476 // FIXME: for mmx, bitcast v2i32 to v4i16 for shuffle.
4478 // Normalize the node to match x86 shuffle ops if needed
4479 if (!isMMX && V2.getOpcode() != ISD::UNDEF && isCommutedSHUFP(SVOp))
4480 return CommuteVectorShuffle(SVOp, DAG);
4482 // Check for legal shuffle and return?
4483 SmallVector<int, 16> PermMask;
4484 SVOp->getMask(PermMask);
4485 if (isShuffleMaskLegal(PermMask, VT))
4488 // Handle v8i16 specifically since SSE can do byte extraction and insertion.
4489 if (VT == MVT::v8i16) {
4490 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(SVOp, DAG, *this);
4491 if (NewOp.getNode())
4495 if (VT == MVT::v16i8) {
4496 SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(SVOp, DAG, *this);
4497 if (NewOp.getNode())
4501 // Handle all 4 wide cases with a number of shuffles except for MMX.
4502 if (NumElems == 4 && !isMMX)
4503 return LowerVECTOR_SHUFFLE_4wide(SVOp, DAG);
4509 X86TargetLowering::LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op,
4510 SelectionDAG &DAG) {
4511 EVT VT = Op.getValueType();
4512 DebugLoc dl = Op.getDebugLoc();
4513 if (VT.getSizeInBits() == 8) {
4514 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
4515 Op.getOperand(0), Op.getOperand(1));
4516 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
4517 DAG.getValueType(VT));
4518 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
4519 } else if (VT.getSizeInBits() == 16) {
4520 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
4521 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
4523 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
4524 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
4525 DAG.getNode(ISD::BIT_CONVERT, dl,
4529 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
4530 Op.getOperand(0), Op.getOperand(1));
4531 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
4532 DAG.getValueType(VT));
4533 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
4534 } else if (VT == MVT::f32) {
4535 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
4536 // the result back to FR32 register. It's only worth matching if the
4537 // result has a single use which is a store or a bitcast to i32. And in
4538 // the case of a store, it's not worth it if the index is a constant 0,
4539 // because a MOVSSmr can be used instead, which is smaller and faster.
4540 if (!Op.hasOneUse())
4542 SDNode *User = *Op.getNode()->use_begin();
4543 if ((User->getOpcode() != ISD::STORE ||
4544 (isa<ConstantSDNode>(Op.getOperand(1)) &&
4545 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
4546 (User->getOpcode() != ISD::BIT_CONVERT ||
4547 User->getValueType(0) != MVT::i32))
4549 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
4550 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v4i32,
4553 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, Extract);
4554 } else if (VT == MVT::i32) {
4555 // ExtractPS works with constant index.
4556 if (isa<ConstantSDNode>(Op.getOperand(1)))
4564 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) {
4565 if (!isa<ConstantSDNode>(Op.getOperand(1)))
4568 if (Subtarget->hasSSE41()) {
4569 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG);
4574 EVT VT = Op.getValueType();
4575 DebugLoc dl = Op.getDebugLoc();
4576 // TODO: handle v16i8.
4577 if (VT.getSizeInBits() == 16) {
4578 SDValue Vec = Op.getOperand(0);
4579 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
4581 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
4582 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
4583 DAG.getNode(ISD::BIT_CONVERT, dl,
4586 // Transform it so it match pextrw which produces a 32-bit result.
4587 EVT EltVT = MVT::i32;
4588 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
4589 Op.getOperand(0), Op.getOperand(1));
4590 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
4591 DAG.getValueType(VT));
4592 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
4593 } else if (VT.getSizeInBits() == 32) {
4594 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
4598 // SHUFPS the element to the lowest double word, then movss.
4599 int Mask[4] = { Idx, -1, -1, -1 };
4600 EVT VVT = Op.getOperand(0).getValueType();
4601 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
4602 DAG.getUNDEF(VVT), Mask);
4603 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
4604 DAG.getIntPtrConstant(0));
4605 } else if (VT.getSizeInBits() == 64) {
4606 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
4607 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
4608 // to match extract_elt for f64.
4609 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
4613 // UNPCKHPD the element to the lowest double word, then movsd.
4614 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
4615 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
4616 int Mask[2] = { 1, -1 };
4617 EVT VVT = Op.getOperand(0).getValueType();
4618 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
4619 DAG.getUNDEF(VVT), Mask);
4620 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
4621 DAG.getIntPtrConstant(0));
4628 X86TargetLowering::LowerINSERT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG){
4629 EVT VT = Op.getValueType();
4630 EVT EltVT = VT.getVectorElementType();
4631 DebugLoc dl = Op.getDebugLoc();
4633 SDValue N0 = Op.getOperand(0);
4634 SDValue N1 = Op.getOperand(1);
4635 SDValue N2 = Op.getOperand(2);
4637 if ((EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) &&
4638 isa<ConstantSDNode>(N2)) {
4639 unsigned Opc = (EltVT.getSizeInBits() == 8) ? X86ISD::PINSRB
4641 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
4643 if (N1.getValueType() != MVT::i32)
4644 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
4645 if (N2.getValueType() != MVT::i32)
4646 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
4647 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
4648 } else if (EltVT == MVT::f32 && isa<ConstantSDNode>(N2)) {
4649 // Bits [7:6] of the constant are the source select. This will always be
4650 // zero here. The DAG Combiner may combine an extract_elt index into these
4651 // bits. For example (insert (extract, 3), 2) could be matched by putting
4652 // the '3' into bits [7:6] of X86ISD::INSERTPS.
4653 // Bits [5:4] of the constant are the destination select. This is the
4654 // value of the incoming immediate.
4655 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
4656 // combine either bitwise AND or insert of float 0.0 to set these bits.
4657 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue() << 4);
4658 // Create this as a scalar to vector..
4659 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
4660 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
4661 } else if (EltVT == MVT::i32 && isa<ConstantSDNode>(N2)) {
4662 // PINSR* works with constant index.
4669 X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) {
4670 EVT VT = Op.getValueType();
4671 EVT EltVT = VT.getVectorElementType();
4673 if (Subtarget->hasSSE41())
4674 return LowerINSERT_VECTOR_ELT_SSE4(Op, DAG);
4676 if (EltVT == MVT::i8)
4679 DebugLoc dl = Op.getDebugLoc();
4680 SDValue N0 = Op.getOperand(0);
4681 SDValue N1 = Op.getOperand(1);
4682 SDValue N2 = Op.getOperand(2);
4684 if (EltVT.getSizeInBits() == 16 && isa<ConstantSDNode>(N2)) {
4685 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
4686 // as its second argument.
4687 if (N1.getValueType() != MVT::i32)
4688 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
4689 if (N2.getValueType() != MVT::i32)
4690 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
4691 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);
4697 X86TargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) {
4698 DebugLoc dl = Op.getDebugLoc();
4699 if (Op.getValueType() == MVT::v2f32)
4700 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f32,
4701 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i32,
4702 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32,
4703 Op.getOperand(0))));
4705 if (Op.getValueType() == MVT::v1i64 && Op.getOperand(0).getValueType() == MVT::i64)
4706 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
4708 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
4709 EVT VT = MVT::v2i32;
4710 switch (Op.getValueType().getSimpleVT().SimpleTy) {
4717 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(),
4718 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, AnyExt));
4721 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
4722 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
4723 // one of the above mentioned nodes. It has to be wrapped because otherwise
4724 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
4725 // be used to form addressing mode. These wrapped nodes will be selected
4728 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) {
4729 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
4731 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
4733 unsigned char OpFlag = 0;
4734 unsigned WrapperKind = X86ISD::Wrapper;
4735 CodeModel::Model M = getTargetMachine().getCodeModel();
4737 if (Subtarget->isPICStyleRIPRel() &&
4738 (M == CodeModel::Small || M == CodeModel::Kernel))
4739 WrapperKind = X86ISD::WrapperRIP;
4740 else if (Subtarget->isPICStyleGOT())
4741 OpFlag = X86II::MO_GOTOFF;
4742 else if (Subtarget->isPICStyleStubPIC())
4743 OpFlag = X86II::MO_PIC_BASE_OFFSET;
4745 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(),
4747 CP->getOffset(), OpFlag);
4748 DebugLoc DL = CP->getDebugLoc();
4749 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
4750 // With PIC, the address is actually $g + Offset.
4752 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
4753 DAG.getNode(X86ISD::GlobalBaseReg,
4754 DebugLoc::getUnknownLoc(), getPointerTy()),
4761 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) {
4762 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
4764 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
4766 unsigned char OpFlag = 0;
4767 unsigned WrapperKind = X86ISD::Wrapper;
4768 CodeModel::Model M = getTargetMachine().getCodeModel();
4770 if (Subtarget->isPICStyleRIPRel() &&
4771 (M == CodeModel::Small || M == CodeModel::Kernel))
4772 WrapperKind = X86ISD::WrapperRIP;
4773 else if (Subtarget->isPICStyleGOT())
4774 OpFlag = X86II::MO_GOTOFF;
4775 else if (Subtarget->isPICStyleStubPIC())
4776 OpFlag = X86II::MO_PIC_BASE_OFFSET;
4778 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(),
4780 DebugLoc DL = JT->getDebugLoc();
4781 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
4783 // With PIC, the address is actually $g + Offset.
4785 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
4786 DAG.getNode(X86ISD::GlobalBaseReg,
4787 DebugLoc::getUnknownLoc(), getPointerTy()),
4795 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) {
4796 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
4798 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
4800 unsigned char OpFlag = 0;
4801 unsigned WrapperKind = X86ISD::Wrapper;
4802 CodeModel::Model M = getTargetMachine().getCodeModel();
4804 if (Subtarget->isPICStyleRIPRel() &&
4805 (M == CodeModel::Small || M == CodeModel::Kernel))
4806 WrapperKind = X86ISD::WrapperRIP;
4807 else if (Subtarget->isPICStyleGOT())
4808 OpFlag = X86II::MO_GOTOFF;
4809 else if (Subtarget->isPICStyleStubPIC())
4810 OpFlag = X86II::MO_PIC_BASE_OFFSET;
4812 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag);
4814 DebugLoc DL = Op.getDebugLoc();
4815 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
4818 // With PIC, the address is actually $g + Offset.
4819 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
4820 !Subtarget->is64Bit()) {
4821 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
4822 DAG.getNode(X86ISD::GlobalBaseReg,
4823 DebugLoc::getUnknownLoc(),
4832 X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) {
4833 // Create the TargetBlockAddressAddress node.
4834 unsigned char OpFlags =
4835 Subtarget->ClassifyBlockAddressReference();
4836 CodeModel::Model M = getTargetMachine().getCodeModel();
4837 BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
4838 DebugLoc dl = Op.getDebugLoc();
4839 SDValue Result = DAG.getBlockAddress(BA, getPointerTy(),
4840 /*isTarget=*/true, OpFlags);
4842 if (Subtarget->isPICStyleRIPRel() &&
4843 (M == CodeModel::Small || M == CodeModel::Kernel))
4844 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
4846 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
4848 // With PIC, the address is actually $g + Offset.
4849 if (isGlobalRelativeToPICBase(OpFlags)) {
4850 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
4851 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
4859 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, DebugLoc dl,
4861 SelectionDAG &DAG) const {
4862 // Create the TargetGlobalAddress node, folding in the constant
4863 // offset if it is legal.
4864 unsigned char OpFlags =
4865 Subtarget->ClassifyGlobalReference(GV, getTargetMachine());
4866 CodeModel::Model M = getTargetMachine().getCodeModel();
4868 if (OpFlags == X86II::MO_NO_FLAG &&
4869 X86::isOffsetSuitableForCodeModel(Offset, M)) {
4870 // A direct static reference to a global.
4871 Result = DAG.getTargetGlobalAddress(GV, getPointerTy(), Offset);
4874 Result = DAG.getTargetGlobalAddress(GV, getPointerTy(), 0, OpFlags);
4877 if (Subtarget->isPICStyleRIPRel() &&
4878 (M == CodeModel::Small || M == CodeModel::Kernel))
4879 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
4881 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
4883 // With PIC, the address is actually $g + Offset.
4884 if (isGlobalRelativeToPICBase(OpFlags)) {
4885 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
4886 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
4890 // For globals that require a load from a stub to get the address, emit the
4892 if (isGlobalStubReference(OpFlags))
4893 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result,
4894 PseudoSourceValue::getGOT(), 0);
4896 // If there was a non-zero offset that we didn't fold, create an explicit
4899 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result,
4900 DAG.getConstant(Offset, getPointerTy()));
4906 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) {
4907 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
4908 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
4909 return LowerGlobalAddress(GV, Op.getDebugLoc(), Offset, DAG);
4913 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
4914 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg,
4915 unsigned char OperandFlags) {
4916 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
4917 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
4918 DebugLoc dl = GA->getDebugLoc();
4919 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(),
4920 GA->getValueType(0),
4924 SDValue Ops[] = { Chain, TGA, *InFlag };
4925 Chain = DAG.getNode(X86ISD::TLSADDR, dl, NodeTys, Ops, 3);
4927 SDValue Ops[] = { Chain, TGA };
4928 Chain = DAG.getNode(X86ISD::TLSADDR, dl, NodeTys, Ops, 2);
4931 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
4932 MFI->setHasCalls(true);
4934 SDValue Flag = Chain.getValue(1);
4935 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
4938 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
4940 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
4943 DebugLoc dl = GA->getDebugLoc(); // ? function entry point might be better
4944 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
4945 DAG.getNode(X86ISD::GlobalBaseReg,
4946 DebugLoc::getUnknownLoc(),
4948 InFlag = Chain.getValue(1);
4950 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
4953 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
4955 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
4957 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, NULL, PtrVT,
4958 X86::RAX, X86II::MO_TLSGD);
4961 // Lower ISD::GlobalTLSAddress using the "initial exec" (for no-pic) or
4962 // "local exec" model.
4963 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
4964 const EVT PtrVT, TLSModel::Model model,
4966 DebugLoc dl = GA->getDebugLoc();
4967 // Get the Thread Pointer
4968 SDValue Base = DAG.getNode(X86ISD::SegmentBaseAddress,
4969 DebugLoc::getUnknownLoc(), PtrVT,
4970 DAG.getRegister(is64Bit? X86::FS : X86::GS,
4973 SDValue ThreadPointer = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Base,
4976 unsigned char OperandFlags = 0;
4977 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
4979 unsigned WrapperKind = X86ISD::Wrapper;
4980 if (model == TLSModel::LocalExec) {
4981 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
4982 } else if (is64Bit) {
4983 assert(model == TLSModel::InitialExec);
4984 OperandFlags = X86II::MO_GOTTPOFF;
4985 WrapperKind = X86ISD::WrapperRIP;
4987 assert(model == TLSModel::InitialExec);
4988 OperandFlags = X86II::MO_INDNTPOFF;
4991 // emit "addl x@ntpoff,%eax" (local exec) or "addl x@indntpoff,%eax" (initial
4993 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), GA->getValueType(0),
4994 GA->getOffset(), OperandFlags);
4995 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
4997 if (model == TLSModel::InitialExec)
4998 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
4999 PseudoSourceValue::getGOT(), 0);
5001 // The address of the thread local variable is the add of the thread
5002 // pointer with the offset of the variable.
5003 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
5007 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) {
5008 // TODO: implement the "local dynamic" model
5009 // TODO: implement the "initial exec"model for pic executables
5010 assert(Subtarget->isTargetELF() &&
5011 "TLS not implemented for non-ELF targets");
5012 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
5013 const GlobalValue *GV = GA->getGlobal();
5015 // If GV is an alias then use the aliasee for determining
5016 // thread-localness.
5017 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV))
5018 GV = GA->resolveAliasedGlobal(false);
5020 TLSModel::Model model = getTLSModel(GV,
5021 getTargetMachine().getRelocationModel());
5024 case TLSModel::GeneralDynamic:
5025 case TLSModel::LocalDynamic: // not implemented
5026 if (Subtarget->is64Bit())
5027 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy());
5028 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy());
5030 case TLSModel::InitialExec:
5031 case TLSModel::LocalExec:
5032 return LowerToTLSExecModel(GA, DAG, getPointerTy(), model,
5033 Subtarget->is64Bit());
5036 llvm_unreachable("Unreachable");
5041 /// LowerShift - Lower SRA_PARTS and friends, which return two i32 values and
5042 /// take a 2 x i32 value to shift plus a shift amount.
5043 SDValue X86TargetLowering::LowerShift(SDValue Op, SelectionDAG &DAG) {
5044 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
5045 EVT VT = Op.getValueType();
5046 unsigned VTBits = VT.getSizeInBits();
5047 DebugLoc dl = Op.getDebugLoc();
5048 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
5049 SDValue ShOpLo = Op.getOperand(0);
5050 SDValue ShOpHi = Op.getOperand(1);
5051 SDValue ShAmt = Op.getOperand(2);
5052 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
5053 DAG.getConstant(VTBits - 1, MVT::i8))
5054 : DAG.getConstant(0, VT);
5057 if (Op.getOpcode() == ISD::SHL_PARTS) {
5058 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
5059 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
5061 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
5062 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, ShAmt);
5065 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
5066 DAG.getConstant(VTBits, MVT::i8));
5067 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, VT,
5068 AndNode, DAG.getConstant(0, MVT::i8));
5071 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8);
5072 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
5073 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
5075 if (Op.getOpcode() == ISD::SHL_PARTS) {
5076 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
5077 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
5079 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
5080 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
5083 SDValue Ops[2] = { Lo, Hi };
5084 return DAG.getMergeValues(Ops, 2, dl);
5087 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
5088 EVT SrcVT = Op.getOperand(0).getValueType();
5090 if (SrcVT.isVector()) {
5091 if (SrcVT == MVT::v2i32 && Op.getValueType() == MVT::v2f64) {
5097 assert(SrcVT.getSimpleVT() <= MVT::i64 && SrcVT.getSimpleVT() >= MVT::i16 &&
5098 "Unknown SINT_TO_FP to lower!");
5100 // These are really Legal; return the operand so the caller accepts it as
5102 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
5104 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
5105 Subtarget->is64Bit()) {
5109 DebugLoc dl = Op.getDebugLoc();
5110 unsigned Size = SrcVT.getSizeInBits()/8;
5111 MachineFunction &MF = DAG.getMachineFunction();
5112 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false);
5113 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
5114 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
5116 PseudoSourceValue::getFixedStack(SSFI), 0);
5117 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
5120 SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
5122 SelectionDAG &DAG) {
5124 DebugLoc dl = Op.getDebugLoc();
5126 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
5128 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Flag);
5130 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
5131 SmallVector<SDValue, 8> Ops;
5132 Ops.push_back(Chain);
5133 Ops.push_back(StackSlot);
5134 Ops.push_back(DAG.getValueType(SrcVT));
5135 SDValue Result = DAG.getNode(useSSE ? X86ISD::FILD_FLAG : X86ISD::FILD, dl,
5136 Tys, &Ops[0], Ops.size());
5139 Chain = Result.getValue(1);
5140 SDValue InFlag = Result.getValue(2);
5142 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
5143 // shouldn't be necessary except that RFP cannot be live across
5144 // multiple blocks. When stackifier is fixed, they can be uncoupled.
5145 MachineFunction &MF = DAG.getMachineFunction();
5146 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8, false);
5147 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
5148 Tys = DAG.getVTList(MVT::Other);
5149 SmallVector<SDValue, 8> Ops;
5150 Ops.push_back(Chain);
5151 Ops.push_back(Result);
5152 Ops.push_back(StackSlot);
5153 Ops.push_back(DAG.getValueType(Op.getValueType()));
5154 Ops.push_back(InFlag);
5155 Chain = DAG.getNode(X86ISD::FST, dl, Tys, &Ops[0], Ops.size());
5156 Result = DAG.getLoad(Op.getValueType(), dl, Chain, StackSlot,
5157 PseudoSourceValue::getFixedStack(SSFI), 0);
5163 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
5164 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op, SelectionDAG &DAG) {
5165 // This algorithm is not obvious. Here it is in C code, more or less:
5167 double uint64_to_double( uint32_t hi, uint32_t lo ) {
5168 static const __m128i exp = { 0x4330000045300000ULL, 0 };
5169 static const __m128d bias = { 0x1.0p84, 0x1.0p52 };
5171 // Copy ints to xmm registers.
5172 __m128i xh = _mm_cvtsi32_si128( hi );
5173 __m128i xl = _mm_cvtsi32_si128( lo );
5175 // Combine into low half of a single xmm register.
5176 __m128i x = _mm_unpacklo_epi32( xh, xl );
5180 // Merge in appropriate exponents to give the integer bits the right
5182 x = _mm_unpacklo_epi32( x, exp );
5184 // Subtract away the biases to deal with the IEEE-754 double precision
5186 d = _mm_sub_pd( (__m128d) x, bias );
5188 // All conversions up to here are exact. The correctly rounded result is
5189 // calculated using the current rounding mode using the following
5191 d = _mm_add_sd( d, _mm_unpackhi_pd( d, d ) );
5192 _mm_store_sd( &sd, d ); // Because we are returning doubles in XMM, this
5193 // store doesn't really need to be here (except
5194 // maybe to zero the other double)
5199 DebugLoc dl = Op.getDebugLoc();
5200 LLVMContext *Context = DAG.getContext();
5202 // Build some magic constants.
5203 std::vector<Constant*> CV0;
5204 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0x45300000)));
5205 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0x43300000)));
5206 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0)));
5207 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0)));
5208 Constant *C0 = ConstantVector::get(CV0);
5209 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16);
5211 std::vector<Constant*> CV1;
5213 ConstantFP::get(*Context, APFloat(APInt(64, 0x4530000000000000ULL))));
5215 ConstantFP::get(*Context, APFloat(APInt(64, 0x4330000000000000ULL))));
5216 Constant *C1 = ConstantVector::get(CV1);
5217 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16);
5219 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
5220 DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
5222 DAG.getIntPtrConstant(1)));
5223 SDValue XR2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
5224 DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
5226 DAG.getIntPtrConstant(0)));
5227 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32, XR1, XR2);
5228 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
5229 PseudoSourceValue::getConstantPool(), 0,
5231 SDValue Unpck2 = getUnpackl(DAG, dl, MVT::v4i32, Unpck1, CLod0);
5232 SDValue XR2F = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f64, Unpck2);
5233 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
5234 PseudoSourceValue::getConstantPool(), 0,
5236 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
5238 // Add the halves; easiest way is to swap them into another reg first.
5239 int ShufMask[2] = { 1, -1 };
5240 SDValue Shuf = DAG.getVectorShuffle(MVT::v2f64, dl, Sub,
5241 DAG.getUNDEF(MVT::v2f64), ShufMask);
5242 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::v2f64, Shuf, Sub);
5243 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Add,
5244 DAG.getIntPtrConstant(0));
5247 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
5248 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op, SelectionDAG &DAG) {
5249 DebugLoc dl = Op.getDebugLoc();
5250 // FP constant to bias correct the final result.
5251 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
5254 // Load the 32-bit value into an XMM register.
5255 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
5256 DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
5258 DAG.getIntPtrConstant(0)));
5260 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
5261 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f64, Load),
5262 DAG.getIntPtrConstant(0));
5264 // Or the load with the bias.
5265 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64,
5266 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64,
5267 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
5269 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64,
5270 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
5271 MVT::v2f64, Bias)));
5272 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
5273 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f64, Or),
5274 DAG.getIntPtrConstant(0));
5276 // Subtract the bias.
5277 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
5279 // Handle final rounding.
5280 EVT DestVT = Op.getValueType();
5282 if (DestVT.bitsLT(MVT::f64)) {
5283 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
5284 DAG.getIntPtrConstant(0));
5285 } else if (DestVT.bitsGT(MVT::f64)) {
5286 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
5289 // Handle final rounding.
5293 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
5294 SDValue N0 = Op.getOperand(0);
5295 DebugLoc dl = Op.getDebugLoc();
5297 // Now not UINT_TO_FP is legal (it's marked custom), dag combiner won't
5298 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
5299 // the optimization here.
5300 if (DAG.SignBitIsZero(N0))
5301 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
5303 EVT SrcVT = N0.getValueType();
5304 if (SrcVT == MVT::i64) {
5305 // We only handle SSE2 f64 target here; caller can expand the rest.
5306 if (Op.getValueType() != MVT::f64 || !X86ScalarSSEf64)
5309 return LowerUINT_TO_FP_i64(Op, DAG);
5310 } else if (SrcVT == MVT::i32 && X86ScalarSSEf64) {
5311 return LowerUINT_TO_FP_i32(Op, DAG);
5314 assert(SrcVT == MVT::i32 && "Unknown UINT_TO_FP to lower!");
5316 // Make a 64-bit buffer, and use it to build an FILD.
5317 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
5318 SDValue WordOff = DAG.getConstant(4, getPointerTy());
5319 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl,
5320 getPointerTy(), StackSlot, WordOff);
5321 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
5322 StackSlot, NULL, 0);
5323 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32),
5324 OffsetSlot, NULL, 0);
5325 return BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
5328 std::pair<SDValue,SDValue> X86TargetLowering::
5329 FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG, bool IsSigned) {
5330 DebugLoc dl = Op.getDebugLoc();
5332 EVT DstTy = Op.getValueType();
5335 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
5339 assert(DstTy.getSimpleVT() <= MVT::i64 &&
5340 DstTy.getSimpleVT() >= MVT::i16 &&
5341 "Unknown FP_TO_SINT to lower!");
5343 // These are really Legal.
5344 if (DstTy == MVT::i32 &&
5345 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
5346 return std::make_pair(SDValue(), SDValue());
5347 if (Subtarget->is64Bit() &&
5348 DstTy == MVT::i64 &&
5349 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
5350 return std::make_pair(SDValue(), SDValue());
5352 // We lower FP->sint64 into FISTP64, followed by a load, all to a temporary
5354 MachineFunction &MF = DAG.getMachineFunction();
5355 unsigned MemSize = DstTy.getSizeInBits()/8;
5356 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
5357 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
5360 switch (DstTy.getSimpleVT().SimpleTy) {
5361 default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
5362 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
5363 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
5364 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
5367 SDValue Chain = DAG.getEntryNode();
5368 SDValue Value = Op.getOperand(0);
5369 if (isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType())) {
5370 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
5371 Chain = DAG.getStore(Chain, dl, Value, StackSlot,
5372 PseudoSourceValue::getFixedStack(SSFI), 0);
5373 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
5375 Chain, StackSlot, DAG.getValueType(Op.getOperand(0).getValueType())
5377 Value = DAG.getNode(X86ISD::FLD, dl, Tys, Ops, 3);
5378 Chain = Value.getValue(1);
5379 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
5380 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
5383 // Build the FP_TO_INT*_IN_MEM
5384 SDValue Ops[] = { Chain, Value, StackSlot };
5385 SDValue FIST = DAG.getNode(Opc, dl, MVT::Other, Ops, 3);
5387 return std::make_pair(FIST, StackSlot);
5390 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) {
5391 if (Op.getValueType().isVector()) {
5392 if (Op.getValueType() == MVT::v2i32 &&
5393 Op.getOperand(0).getValueType() == MVT::v2f64) {
5399 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG, true);
5400 SDValue FIST = Vals.first, StackSlot = Vals.second;
5401 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
5402 if (FIST.getNode() == 0) return Op;
5405 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(),
5406 FIST, StackSlot, NULL, 0);
5409 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op, SelectionDAG &DAG) {
5410 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG, false);
5411 SDValue FIST = Vals.first, StackSlot = Vals.second;
5412 assert(FIST.getNode() && "Unexpected failure");
5415 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(),
5416 FIST, StackSlot, NULL, 0);
5419 SDValue X86TargetLowering::LowerFABS(SDValue Op, SelectionDAG &DAG) {
5420 LLVMContext *Context = DAG.getContext();
5421 DebugLoc dl = Op.getDebugLoc();
5422 EVT VT = Op.getValueType();
5425 EltVT = VT.getVectorElementType();
5426 std::vector<Constant*> CV;
5427 if (EltVT == MVT::f64) {
5428 Constant *C = ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63))));
5432 Constant *C = ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31))));
5438 Constant *C = ConstantVector::get(CV);
5439 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
5440 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
5441 PseudoSourceValue::getConstantPool(), 0,
5443 return DAG.getNode(X86ISD::FAND, dl, VT, Op.getOperand(0), Mask);
5446 SDValue X86TargetLowering::LowerFNEG(SDValue Op, SelectionDAG &DAG) {
5447 LLVMContext *Context = DAG.getContext();
5448 DebugLoc dl = Op.getDebugLoc();
5449 EVT VT = Op.getValueType();
5452 EltVT = VT.getVectorElementType();
5453 std::vector<Constant*> CV;
5454 if (EltVT == MVT::f64) {
5455 Constant *C = ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63)));
5459 Constant *C = ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31)));
5465 Constant *C = ConstantVector::get(CV);
5466 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
5467 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
5468 PseudoSourceValue::getConstantPool(), 0,
5470 if (VT.isVector()) {
5471 return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
5472 DAG.getNode(ISD::XOR, dl, MVT::v2i64,
5473 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64,
5475 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64, Mask)));
5477 return DAG.getNode(X86ISD::FXOR, dl, VT, Op.getOperand(0), Mask);
5481 SDValue X86TargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) {
5482 LLVMContext *Context = DAG.getContext();
5483 SDValue Op0 = Op.getOperand(0);
5484 SDValue Op1 = Op.getOperand(1);
5485 DebugLoc dl = Op.getDebugLoc();
5486 EVT VT = Op.getValueType();
5487 EVT SrcVT = Op1.getValueType();
5489 // If second operand is smaller, extend it first.
5490 if (SrcVT.bitsLT(VT)) {
5491 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
5494 // And if it is bigger, shrink it first.
5495 if (SrcVT.bitsGT(VT)) {
5496 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1));
5500 // At this point the operands and the result should have the same
5501 // type, and that won't be f80 since that is not custom lowered.
5503 // First get the sign bit of second operand.
5504 std::vector<Constant*> CV;
5505 if (SrcVT == MVT::f64) {
5506 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63))));
5507 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0))));
5509 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31))));
5510 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
5511 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
5512 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
5514 Constant *C = ConstantVector::get(CV);
5515 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
5516 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx,
5517 PseudoSourceValue::getConstantPool(), 0,
5519 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1);
5521 // Shift sign bit right or left if the two operands have different types.
5522 if (SrcVT.bitsGT(VT)) {
5523 // Op0 is MVT::f32, Op1 is MVT::f64.
5524 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, SignBit);
5525 SignBit = DAG.getNode(X86ISD::FSRL, dl, MVT::v2f64, SignBit,
5526 DAG.getConstant(32, MVT::i32));
5527 SignBit = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v4f32, SignBit);
5528 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, SignBit,
5529 DAG.getIntPtrConstant(0));
5532 // Clear first operand sign bit.
5534 if (VT == MVT::f64) {
5535 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63)))));
5536 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0))));
5538 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31)))));
5539 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
5540 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
5541 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
5543 C = ConstantVector::get(CV);
5544 CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
5545 SDValue Mask2 = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
5546 PseudoSourceValue::getConstantPool(), 0,
5548 SDValue Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Mask2);
5550 // Or the value with the sign bit.
5551 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit);
5554 /// Emit nodes that will be selected as "test Op0,Op0", or something
5556 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC,
5557 SelectionDAG &DAG) {
5558 DebugLoc dl = Op.getDebugLoc();
5560 // CF and OF aren't always set the way we want. Determine which
5561 // of these we need.
5562 bool NeedCF = false;
5563 bool NeedOF = false;
5565 case X86::COND_A: case X86::COND_AE:
5566 case X86::COND_B: case X86::COND_BE:
5569 case X86::COND_G: case X86::COND_GE:
5570 case X86::COND_L: case X86::COND_LE:
5571 case X86::COND_O: case X86::COND_NO:
5577 // See if we can use the EFLAGS value from the operand instead of
5578 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
5579 // we prove that the arithmetic won't overflow, we can't use OF or CF.
5580 if (Op.getResNo() == 0 && !NeedOF && !NeedCF) {
5581 unsigned Opcode = 0;
5582 unsigned NumOperands = 0;
5583 switch (Op.getNode()->getOpcode()) {
5585 // Due to an isel shortcoming, be conservative if this add is likely to
5586 // be selected as part of a load-modify-store instruction. When the root
5587 // node in a match is a store, isel doesn't know how to remap non-chain
5588 // non-flag uses of other nodes in the match, such as the ADD in this
5589 // case. This leads to the ADD being left around and reselected, with
5590 // the result being two adds in the output.
5591 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
5592 UE = Op.getNode()->use_end(); UI != UE; ++UI)
5593 if (UI->getOpcode() == ISD::STORE)
5595 if (ConstantSDNode *C =
5596 dyn_cast<ConstantSDNode>(Op.getNode()->getOperand(1))) {
5597 // An add of one will be selected as an INC.
5598 if (C->getAPIntValue() == 1) {
5599 Opcode = X86ISD::INC;
5603 // An add of negative one (subtract of one) will be selected as a DEC.
5604 if (C->getAPIntValue().isAllOnesValue()) {
5605 Opcode = X86ISD::DEC;
5610 // Otherwise use a regular EFLAGS-setting add.
5611 Opcode = X86ISD::ADD;
5615 // If the primary and result isn't used, don't bother using X86ISD::AND,
5616 // because a TEST instruction will be better.
5617 bool NonFlagUse = false;
5618 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
5619 UE = Op.getNode()->use_end(); UI != UE; ++UI)
5620 if (UI->getOpcode() != ISD::BRCOND &&
5621 UI->getOpcode() != ISD::SELECT &&
5622 UI->getOpcode() != ISD::SETCC) {
5633 // Due to the ISEL shortcoming noted above, be conservative if this op is
5634 // likely to be selected as part of a load-modify-store instruction.
5635 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
5636 UE = Op.getNode()->use_end(); UI != UE; ++UI)
5637 if (UI->getOpcode() == ISD::STORE)
5639 // Otherwise use a regular EFLAGS-setting instruction.
5640 switch (Op.getNode()->getOpcode()) {
5641 case ISD::SUB: Opcode = X86ISD::SUB; break;
5642 case ISD::OR: Opcode = X86ISD::OR; break;
5643 case ISD::XOR: Opcode = X86ISD::XOR; break;
5644 case ISD::AND: Opcode = X86ISD::AND; break;
5645 default: llvm_unreachable("unexpected operator!");
5656 return SDValue(Op.getNode(), 1);
5662 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
5663 SmallVector<SDValue, 4> Ops;
5664 for (unsigned i = 0; i != NumOperands; ++i)
5665 Ops.push_back(Op.getOperand(i));
5666 SDValue New = DAG.getNode(Opcode, dl, VTs, &Ops[0], NumOperands);
5667 DAG.ReplaceAllUsesWith(Op, New);
5668 return SDValue(New.getNode(), 1);
5672 // Otherwise just emit a CMP with 0, which is the TEST pattern.
5673 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
5674 DAG.getConstant(0, Op.getValueType()));
5677 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
5679 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
5680 SelectionDAG &DAG) {
5681 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1))
5682 if (C->getAPIntValue() == 0)
5683 return EmitTest(Op0, X86CC, DAG);
5685 DebugLoc dl = Op0.getDebugLoc();
5686 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
5689 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) {
5690 assert(Op.getValueType() == MVT::i8 && "SetCC type must be 8-bit integer");
5691 SDValue Op0 = Op.getOperand(0);
5692 SDValue Op1 = Op.getOperand(1);
5693 DebugLoc dl = Op.getDebugLoc();
5694 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
5696 // Lower (X & (1 << N)) == 0 to BT(X, N).
5697 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
5698 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
5699 if (Op0.getOpcode() == ISD::AND &&
5701 Op1.getOpcode() == ISD::Constant &&
5702 cast<ConstantSDNode>(Op1)->getZExtValue() == 0 &&
5703 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
5705 if (Op0.getOperand(1).getOpcode() == ISD::SHL) {
5706 if (ConstantSDNode *Op010C =
5707 dyn_cast<ConstantSDNode>(Op0.getOperand(1).getOperand(0)))
5708 if (Op010C->getZExtValue() == 1) {
5709 LHS = Op0.getOperand(0);
5710 RHS = Op0.getOperand(1).getOperand(1);
5712 } else if (Op0.getOperand(0).getOpcode() == ISD::SHL) {
5713 if (ConstantSDNode *Op000C =
5714 dyn_cast<ConstantSDNode>(Op0.getOperand(0).getOperand(0)))
5715 if (Op000C->getZExtValue() == 1) {
5716 LHS = Op0.getOperand(1);
5717 RHS = Op0.getOperand(0).getOperand(1);
5719 } else if (Op0.getOperand(1).getOpcode() == ISD::Constant) {
5720 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op0.getOperand(1));
5721 SDValue AndLHS = Op0.getOperand(0);
5722 if (AndRHS->getZExtValue() == 1 && AndLHS.getOpcode() == ISD::SRL) {
5723 LHS = AndLHS.getOperand(0);
5724 RHS = AndLHS.getOperand(1);
5728 if (LHS.getNode()) {
5729 // If LHS is i8, promote it to i16 with any_extend. There is no i8 BT
5730 // instruction. Since the shift amount is in-range-or-undefined, we know
5731 // that doing a bittest on the i16 value is ok. We extend to i32 because
5732 // the encoding for the i16 version is larger than the i32 version.
5733 if (LHS.getValueType() == MVT::i8)
5734 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
5736 // If the operand types disagree, extend the shift amount to match. Since
5737 // BT ignores high bits (like shifts) we can use anyextend.
5738 if (LHS.getValueType() != RHS.getValueType())
5739 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
5741 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
5742 unsigned Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
5743 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
5744 DAG.getConstant(Cond, MVT::i8), BT);
5748 bool isFP = Op.getOperand(1).getValueType().isFloatingPoint();
5749 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG);
5750 if (X86CC == X86::COND_INVALID)
5753 SDValue Cond = EmitCmp(Op0, Op1, X86CC, DAG);
5755 // Use sbb x, x to materialize carry bit into a GPR.
5756 if (X86CC == X86::COND_B)
5757 return DAG.getNode(ISD::AND, dl, MVT::i8,
5758 DAG.getNode(X86ISD::SETCC_CARRY, dl, MVT::i8,
5759 DAG.getConstant(X86CC, MVT::i8), Cond),
5760 DAG.getConstant(1, MVT::i8));
5762 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
5763 DAG.getConstant(X86CC, MVT::i8), Cond);
5766 SDValue X86TargetLowering::LowerVSETCC(SDValue Op, SelectionDAG &DAG) {
5768 SDValue Op0 = Op.getOperand(0);
5769 SDValue Op1 = Op.getOperand(1);
5770 SDValue CC = Op.getOperand(2);
5771 EVT VT = Op.getValueType();
5772 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
5773 bool isFP = Op.getOperand(1).getValueType().isFloatingPoint();
5774 DebugLoc dl = Op.getDebugLoc();
5778 EVT VT0 = Op0.getValueType();
5779 assert(VT0 == MVT::v4f32 || VT0 == MVT::v2f64);
5780 unsigned Opc = VT0 == MVT::v4f32 ? X86ISD::CMPPS : X86ISD::CMPPD;
5783 switch (SetCCOpcode) {
5786 case ISD::SETEQ: SSECC = 0; break;
5788 case ISD::SETGT: Swap = true; // Fallthrough
5790 case ISD::SETOLT: SSECC = 1; break;
5792 case ISD::SETGE: Swap = true; // Fallthrough
5794 case ISD::SETOLE: SSECC = 2; break;
5795 case ISD::SETUO: SSECC = 3; break;
5797 case ISD::SETNE: SSECC = 4; break;
5798 case ISD::SETULE: Swap = true;
5799 case ISD::SETUGE: SSECC = 5; break;
5800 case ISD::SETULT: Swap = true;
5801 case ISD::SETUGT: SSECC = 6; break;
5802 case ISD::SETO: SSECC = 7; break;
5805 std::swap(Op0, Op1);
5807 // In the two special cases we can't handle, emit two comparisons.
5809 if (SetCCOpcode == ISD::SETUEQ) {
5811 UNORD = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(3, MVT::i8));
5812 EQ = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(0, MVT::i8));
5813 return DAG.getNode(ISD::OR, dl, VT, UNORD, EQ);
5815 else if (SetCCOpcode == ISD::SETONE) {
5817 ORD = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(7, MVT::i8));
5818 NEQ = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(4, MVT::i8));
5819 return DAG.getNode(ISD::AND, dl, VT, ORD, NEQ);
5821 llvm_unreachable("Illegal FP comparison");
5823 // Handle all other FP comparisons here.
5824 return DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(SSECC, MVT::i8));
5827 // We are handling one of the integer comparisons here. Since SSE only has
5828 // GT and EQ comparisons for integer, swapping operands and multiple
5829 // operations may be required for some comparisons.
5830 unsigned Opc = 0, EQOpc = 0, GTOpc = 0;
5831 bool Swap = false, Invert = false, FlipSigns = false;
5833 switch (VT.getSimpleVT().SimpleTy) {
5836 case MVT::v16i8: EQOpc = X86ISD::PCMPEQB; GTOpc = X86ISD::PCMPGTB; break;
5838 case MVT::v8i16: EQOpc = X86ISD::PCMPEQW; GTOpc = X86ISD::PCMPGTW; break;
5840 case MVT::v4i32: EQOpc = X86ISD::PCMPEQD; GTOpc = X86ISD::PCMPGTD; break;
5841 case MVT::v2i64: EQOpc = X86ISD::PCMPEQQ; GTOpc = X86ISD::PCMPGTQ; break;
5844 switch (SetCCOpcode) {
5846 case ISD::SETNE: Invert = true;
5847 case ISD::SETEQ: Opc = EQOpc; break;
5848 case ISD::SETLT: Swap = true;
5849 case ISD::SETGT: Opc = GTOpc; break;
5850 case ISD::SETGE: Swap = true;
5851 case ISD::SETLE: Opc = GTOpc; Invert = true; break;
5852 case ISD::SETULT: Swap = true;
5853 case ISD::SETUGT: Opc = GTOpc; FlipSigns = true; break;
5854 case ISD::SETUGE: Swap = true;
5855 case ISD::SETULE: Opc = GTOpc; FlipSigns = true; Invert = true; break;
5858 std::swap(Op0, Op1);
5860 // Since SSE has no unsigned integer comparisons, we need to flip the sign
5861 // bits of the inputs before performing those operations.
5863 EVT EltVT = VT.getVectorElementType();
5864 SDValue SignBit = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()),
5866 std::vector<SDValue> SignBits(VT.getVectorNumElements(), SignBit);
5867 SDValue SignVec = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &SignBits[0],
5869 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SignVec);
5870 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SignVec);
5873 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
5875 // If the logical-not of the result is required, perform that now.
5877 Result = DAG.getNOT(dl, Result, VT);
5882 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
5883 static bool isX86LogicalCmp(SDValue Op) {
5884 unsigned Opc = Op.getNode()->getOpcode();
5885 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI)
5887 if (Op.getResNo() == 1 &&
5888 (Opc == X86ISD::ADD ||
5889 Opc == X86ISD::SUB ||
5890 Opc == X86ISD::SMUL ||
5891 Opc == X86ISD::UMUL ||
5892 Opc == X86ISD::INC ||
5893 Opc == X86ISD::DEC ||
5894 Opc == X86ISD::OR ||
5895 Opc == X86ISD::XOR ||
5896 Opc == X86ISD::AND))
5902 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) {
5903 bool addTest = true;
5904 SDValue Cond = Op.getOperand(0);
5905 DebugLoc dl = Op.getDebugLoc();
5908 if (Cond.getOpcode() == ISD::SETCC) {
5909 SDValue NewCond = LowerSETCC(Cond, DAG);
5910 if (NewCond.getNode())
5914 // Look pass (and (setcc_carry (cmp ...)), 1).
5915 if (Cond.getOpcode() == ISD::AND &&
5916 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
5917 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
5918 if (C && C->getAPIntValue() == 1)
5919 Cond = Cond.getOperand(0);
5922 // If condition flag is set by a X86ISD::CMP, then use it as the condition
5923 // setting operand in place of the X86ISD::SETCC.
5924 if (Cond.getOpcode() == X86ISD::SETCC ||
5925 Cond.getOpcode() == X86ISD::SETCC_CARRY) {
5926 CC = Cond.getOperand(0);
5928 SDValue Cmp = Cond.getOperand(1);
5929 unsigned Opc = Cmp.getOpcode();
5930 EVT VT = Op.getValueType();
5932 bool IllegalFPCMov = false;
5933 if (VT.isFloatingPoint() && !VT.isVector() &&
5934 !isScalarFPTypeInSSEReg(VT)) // FPStack?
5935 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
5937 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
5938 Opc == X86ISD::BT) { // FIXME
5945 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
5946 Cond = EmitTest(Cond, X86::COND_NE, DAG);
5949 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Flag);
5950 SmallVector<SDValue, 4> Ops;
5951 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
5952 // condition is true.
5953 Ops.push_back(Op.getOperand(2));
5954 Ops.push_back(Op.getOperand(1));
5956 Ops.push_back(Cond);
5957 return DAG.getNode(X86ISD::CMOV, dl, VTs, &Ops[0], Ops.size());
5960 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
5961 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
5962 // from the AND / OR.
5963 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
5964 Opc = Op.getOpcode();
5965 if (Opc != ISD::OR && Opc != ISD::AND)
5967 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
5968 Op.getOperand(0).hasOneUse() &&
5969 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
5970 Op.getOperand(1).hasOneUse());
5973 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
5974 // 1 and that the SETCC node has a single use.
5975 static bool isXor1OfSetCC(SDValue Op) {
5976 if (Op.getOpcode() != ISD::XOR)
5978 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
5979 if (N1C && N1C->getAPIntValue() == 1) {
5980 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
5981 Op.getOperand(0).hasOneUse();
5986 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) {
5987 bool addTest = true;
5988 SDValue Chain = Op.getOperand(0);
5989 SDValue Cond = Op.getOperand(1);
5990 SDValue Dest = Op.getOperand(2);
5991 DebugLoc dl = Op.getDebugLoc();
5994 if (Cond.getOpcode() == ISD::SETCC) {
5995 SDValue NewCond = LowerSETCC(Cond, DAG);
5996 if (NewCond.getNode())
6000 // FIXME: LowerXALUO doesn't handle these!!
6001 else if (Cond.getOpcode() == X86ISD::ADD ||
6002 Cond.getOpcode() == X86ISD::SUB ||
6003 Cond.getOpcode() == X86ISD::SMUL ||
6004 Cond.getOpcode() == X86ISD::UMUL)
6005 Cond = LowerXALUO(Cond, DAG);
6008 // Look pass (and (setcc_carry (cmp ...)), 1).
6009 if (Cond.getOpcode() == ISD::AND &&
6010 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
6011 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
6012 if (C && C->getAPIntValue() == 1)
6013 Cond = Cond.getOperand(0);
6016 // If condition flag is set by a X86ISD::CMP, then use it as the condition
6017 // setting operand in place of the X86ISD::SETCC.
6018 if (Cond.getOpcode() == X86ISD::SETCC ||
6019 Cond.getOpcode() == X86ISD::SETCC_CARRY) {
6020 CC = Cond.getOperand(0);
6022 SDValue Cmp = Cond.getOperand(1);
6023 unsigned Opc = Cmp.getOpcode();
6024 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
6025 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
6029 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
6033 // These can only come from an arithmetic instruction with overflow,
6034 // e.g. SADDO, UADDO.
6035 Cond = Cond.getNode()->getOperand(1);
6042 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
6043 SDValue Cmp = Cond.getOperand(0).getOperand(1);
6044 if (CondOpc == ISD::OR) {
6045 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
6046 // two branches instead of an explicit OR instruction with a
6048 if (Cmp == Cond.getOperand(1).getOperand(1) &&
6049 isX86LogicalCmp(Cmp)) {
6050 CC = Cond.getOperand(0).getOperand(0);
6051 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
6052 Chain, Dest, CC, Cmp);
6053 CC = Cond.getOperand(1).getOperand(0);
6057 } else { // ISD::AND
6058 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
6059 // two branches instead of an explicit AND instruction with a
6060 // separate test. However, we only do this if this block doesn't
6061 // have a fall-through edge, because this requires an explicit
6062 // jmp when the condition is false.
6063 if (Cmp == Cond.getOperand(1).getOperand(1) &&
6064 isX86LogicalCmp(Cmp) &&
6065 Op.getNode()->hasOneUse()) {
6066 X86::CondCode CCode =
6067 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
6068 CCode = X86::GetOppositeBranchCondition(CCode);
6069 CC = DAG.getConstant(CCode, MVT::i8);
6070 SDValue User = SDValue(*Op.getNode()->use_begin(), 0);
6071 // Look for an unconditional branch following this conditional branch.
6072 // We need this because we need to reverse the successors in order
6073 // to implement FCMP_OEQ.
6074 if (User.getOpcode() == ISD::BR) {
6075 SDValue FalseBB = User.getOperand(1);
6077 DAG.UpdateNodeOperands(User, User.getOperand(0), Dest);
6078 assert(NewBR == User);
6081 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
6082 Chain, Dest, CC, Cmp);
6083 X86::CondCode CCode =
6084 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
6085 CCode = X86::GetOppositeBranchCondition(CCode);
6086 CC = DAG.getConstant(CCode, MVT::i8);
6092 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
6093 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
6094 // It should be transformed during dag combiner except when the condition
6095 // is set by a arithmetics with overflow node.
6096 X86::CondCode CCode =
6097 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
6098 CCode = X86::GetOppositeBranchCondition(CCode);
6099 CC = DAG.getConstant(CCode, MVT::i8);
6100 Cond = Cond.getOperand(0).getOperand(1);
6106 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
6107 Cond = EmitTest(Cond, X86::COND_NE, DAG);
6109 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
6110 Chain, Dest, CC, Cond);
6114 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
6115 // Calls to _alloca is needed to probe the stack when allocating more than 4k
6116 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
6117 // that the guard pages used by the OS virtual memory manager are allocated in
6118 // correct sequence.
6120 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
6121 SelectionDAG &DAG) {
6122 assert(Subtarget->isTargetCygMing() &&
6123 "This should be used only on Cygwin/Mingw targets");
6124 DebugLoc dl = Op.getDebugLoc();
6127 SDValue Chain = Op.getOperand(0);
6128 SDValue Size = Op.getOperand(1);
6129 // FIXME: Ensure alignment here
6133 EVT IntPtr = getPointerTy();
6134 EVT SPTy = Subtarget->is64Bit() ? MVT::i64 : MVT::i32;
6136 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true));
6138 Chain = DAG.getCopyToReg(Chain, dl, X86::EAX, Size, Flag);
6139 Flag = Chain.getValue(1);
6141 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
6142 SDValue Ops[] = { Chain,
6143 DAG.getTargetExternalSymbol("_alloca", IntPtr),
6144 DAG.getRegister(X86::EAX, IntPtr),
6145 DAG.getRegister(X86StackPtr, SPTy),
6147 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, Ops, 5);
6148 Flag = Chain.getValue(1);
6150 Chain = DAG.getCALLSEQ_END(Chain,
6151 DAG.getIntPtrConstant(0, true),
6152 DAG.getIntPtrConstant(0, true),
6155 Chain = DAG.getCopyFromReg(Chain, dl, X86StackPtr, SPTy).getValue(1);
6157 SDValue Ops1[2] = { Chain.getValue(0), Chain };
6158 return DAG.getMergeValues(Ops1, 2, dl);
6162 X86TargetLowering::EmitTargetCodeForMemset(SelectionDAG &DAG, DebugLoc dl,
6164 SDValue Dst, SDValue Src,
6165 SDValue Size, unsigned Align,
6167 uint64_t DstSVOff) {
6168 ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size);
6170 // If not DWORD aligned or size is more than the threshold, call the library.
6171 // The libc version is likely to be faster for these cases. It can use the
6172 // address value and run time information about the CPU.
6173 if ((Align & 3) != 0 ||
6175 ConstantSize->getZExtValue() >
6176 getSubtarget()->getMaxInlineSizeThreshold()) {
6177 SDValue InFlag(0, 0);
6179 // Check to see if there is a specialized entry-point for memory zeroing.
6180 ConstantSDNode *V = dyn_cast<ConstantSDNode>(Src);
6182 if (const char *bzeroEntry = V &&
6183 V->isNullValue() ? Subtarget->getBZeroEntry() : 0) {
6184 EVT IntPtr = getPointerTy();
6185 const Type *IntPtrTy = TD->getIntPtrType(*DAG.getContext());
6186 TargetLowering::ArgListTy Args;
6187 TargetLowering::ArgListEntry Entry;
6189 Entry.Ty = IntPtrTy;
6190 Args.push_back(Entry);
6192 Args.push_back(Entry);
6193 std::pair<SDValue,SDValue> CallResult =
6194 LowerCallTo(Chain, Type::getVoidTy(*DAG.getContext()),
6195 false, false, false, false,
6196 0, CallingConv::C, false, /*isReturnValueUsed=*/false,
6197 DAG.getExternalSymbol(bzeroEntry, IntPtr), Args, DAG, dl,
6198 DAG.GetOrdering(Chain.getNode()));
6199 return CallResult.second;
6202 // Otherwise have the target-independent code call memset.
6206 uint64_t SizeVal = ConstantSize->getZExtValue();
6207 SDValue InFlag(0, 0);
6210 ConstantSDNode *ValC = dyn_cast<ConstantSDNode>(Src);
6211 unsigned BytesLeft = 0;
6212 bool TwoRepStos = false;
6215 uint64_t Val = ValC->getZExtValue() & 255;
6217 // If the value is a constant, then we can potentially use larger sets.
6218 switch (Align & 3) {
6219 case 2: // WORD aligned
6222 Val = (Val << 8) | Val;
6224 case 0: // DWORD aligned
6227 Val = (Val << 8) | Val;
6228 Val = (Val << 16) | Val;
6229 if (Subtarget->is64Bit() && ((Align & 0x7) == 0)) { // QWORD aligned
6232 Val = (Val << 32) | Val;
6235 default: // Byte aligned
6238 Count = DAG.getIntPtrConstant(SizeVal);
6242 if (AVT.bitsGT(MVT::i8)) {
6243 unsigned UBytes = AVT.getSizeInBits() / 8;
6244 Count = DAG.getIntPtrConstant(SizeVal / UBytes);
6245 BytesLeft = SizeVal % UBytes;
6248 Chain = DAG.getCopyToReg(Chain, dl, ValReg, DAG.getConstant(Val, AVT),
6250 InFlag = Chain.getValue(1);
6253 Count = DAG.getIntPtrConstant(SizeVal);
6254 Chain = DAG.getCopyToReg(Chain, dl, X86::AL, Src, InFlag);
6255 InFlag = Chain.getValue(1);
6258 Chain = DAG.getCopyToReg(Chain, dl, Subtarget->is64Bit() ? X86::RCX :
6261 InFlag = Chain.getValue(1);
6262 Chain = DAG.getCopyToReg(Chain, dl, Subtarget->is64Bit() ? X86::RDI :
6265 InFlag = Chain.getValue(1);
6267 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
6268 SmallVector<SDValue, 8> Ops;
6269 Ops.push_back(Chain);
6270 Ops.push_back(DAG.getValueType(AVT));
6271 Ops.push_back(InFlag);
6272 Chain = DAG.getNode(X86ISD::REP_STOS, dl, Tys, &Ops[0], Ops.size());
6275 InFlag = Chain.getValue(1);
6277 EVT CVT = Count.getValueType();
6278 SDValue Left = DAG.getNode(ISD::AND, dl, CVT, Count,
6279 DAG.getConstant((AVT == MVT::i64) ? 7 : 3, CVT));
6280 Chain = DAG.getCopyToReg(Chain, dl, (CVT == MVT::i64) ? X86::RCX :
6283 InFlag = Chain.getValue(1);
6284 Tys = DAG.getVTList(MVT::Other, MVT::Flag);
6286 Ops.push_back(Chain);
6287 Ops.push_back(DAG.getValueType(MVT::i8));
6288 Ops.push_back(InFlag);
6289 Chain = DAG.getNode(X86ISD::REP_STOS, dl, Tys, &Ops[0], Ops.size());
6290 } else if (BytesLeft) {
6291 // Handle the last 1 - 7 bytes.
6292 unsigned Offset = SizeVal - BytesLeft;
6293 EVT AddrVT = Dst.getValueType();
6294 EVT SizeVT = Size.getValueType();
6296 Chain = DAG.getMemset(Chain, dl,
6297 DAG.getNode(ISD::ADD, dl, AddrVT, Dst,
6298 DAG.getConstant(Offset, AddrVT)),
6300 DAG.getConstant(BytesLeft, SizeVT),
6301 Align, DstSV, DstSVOff + Offset);
6304 // TODO: Use a Tokenfactor, as in memcpy, instead of a single chain.
6309 X86TargetLowering::EmitTargetCodeForMemcpy(SelectionDAG &DAG, DebugLoc dl,
6310 SDValue Chain, SDValue Dst, SDValue Src,
6311 SDValue Size, unsigned Align,
6313 const Value *DstSV, uint64_t DstSVOff,
6314 const Value *SrcSV, uint64_t SrcSVOff) {
6315 // This requires the copy size to be a constant, preferrably
6316 // within a subtarget-specific limit.
6317 ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size);
6320 uint64_t SizeVal = ConstantSize->getZExtValue();
6321 if (!AlwaysInline && SizeVal > getSubtarget()->getMaxInlineSizeThreshold())
6324 /// If not DWORD aligned, call the library.
6325 if ((Align & 3) != 0)
6330 if (Subtarget->is64Bit() && ((Align & 0x7) == 0)) // QWORD aligned
6333 unsigned UBytes = AVT.getSizeInBits() / 8;
6334 unsigned CountVal = SizeVal / UBytes;
6335 SDValue Count = DAG.getIntPtrConstant(CountVal);
6336 unsigned BytesLeft = SizeVal % UBytes;
6338 SDValue InFlag(0, 0);
6339 Chain = DAG.getCopyToReg(Chain, dl, Subtarget->is64Bit() ? X86::RCX :
6342 InFlag = Chain.getValue(1);
6343 Chain = DAG.getCopyToReg(Chain, dl, Subtarget->is64Bit() ? X86::RDI :
6346 InFlag = Chain.getValue(1);
6347 Chain = DAG.getCopyToReg(Chain, dl, Subtarget->is64Bit() ? X86::RSI :
6350 InFlag = Chain.getValue(1);
6352 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
6353 SmallVector<SDValue, 8> Ops;
6354 Ops.push_back(Chain);
6355 Ops.push_back(DAG.getValueType(AVT));
6356 Ops.push_back(InFlag);
6357 SDValue RepMovs = DAG.getNode(X86ISD::REP_MOVS, dl, Tys, &Ops[0], Ops.size());
6359 SmallVector<SDValue, 4> Results;
6360 Results.push_back(RepMovs);
6362 // Handle the last 1 - 7 bytes.
6363 unsigned Offset = SizeVal - BytesLeft;
6364 EVT DstVT = Dst.getValueType();
6365 EVT SrcVT = Src.getValueType();
6366 EVT SizeVT = Size.getValueType();
6367 Results.push_back(DAG.getMemcpy(Chain, dl,
6368 DAG.getNode(ISD::ADD, dl, DstVT, Dst,
6369 DAG.getConstant(Offset, DstVT)),
6370 DAG.getNode(ISD::ADD, dl, SrcVT, Src,
6371 DAG.getConstant(Offset, SrcVT)),
6372 DAG.getConstant(BytesLeft, SizeVT),
6373 Align, AlwaysInline,
6374 DstSV, DstSVOff + Offset,
6375 SrcSV, SrcSVOff + Offset));
6378 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
6379 &Results[0], Results.size());
6382 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) {
6383 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
6384 DebugLoc dl = Op.getDebugLoc();
6386 if (!Subtarget->is64Bit()) {
6387 // vastart just stores the address of the VarArgsFrameIndex slot into the
6388 // memory location argument.
6389 SDValue FR = DAG.getFrameIndex(VarArgsFrameIndex, getPointerTy());
6390 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1), SV, 0);
6394 // gp_offset (0 - 6 * 8)
6395 // fp_offset (48 - 48 + 8 * 16)
6396 // overflow_arg_area (point to parameters coming in memory).
6398 SmallVector<SDValue, 8> MemOps;
6399 SDValue FIN = Op.getOperand(1);
6401 SDValue Store = DAG.getStore(Op.getOperand(0), dl,
6402 DAG.getConstant(VarArgsGPOffset, MVT::i32),
6404 MemOps.push_back(Store);
6407 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(),
6408 FIN, DAG.getIntPtrConstant(4));
6409 Store = DAG.getStore(Op.getOperand(0), dl,
6410 DAG.getConstant(VarArgsFPOffset, MVT::i32),
6412 MemOps.push_back(Store);
6414 // Store ptr to overflow_arg_area
6415 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(),
6416 FIN, DAG.getIntPtrConstant(4));
6417 SDValue OVFIN = DAG.getFrameIndex(VarArgsFrameIndex, getPointerTy());
6418 Store = DAG.getStore(Op.getOperand(0), dl, OVFIN, FIN, SV, 0);
6419 MemOps.push_back(Store);
6421 // Store ptr to reg_save_area.
6422 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(),
6423 FIN, DAG.getIntPtrConstant(8));
6424 SDValue RSFIN = DAG.getFrameIndex(RegSaveFrameIndex, getPointerTy());
6425 Store = DAG.getStore(Op.getOperand(0), dl, RSFIN, FIN, SV, 0);
6426 MemOps.push_back(Store);
6427 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
6428 &MemOps[0], MemOps.size());
6431 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) {
6432 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
6433 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_arg!");
6434 SDValue Chain = Op.getOperand(0);
6435 SDValue SrcPtr = Op.getOperand(1);
6436 SDValue SrcSV = Op.getOperand(2);
6438 llvm_report_error("VAArgInst is not yet implemented for x86-64!");
6442 SDValue X86TargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG) {
6443 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
6444 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
6445 SDValue Chain = Op.getOperand(0);
6446 SDValue DstPtr = Op.getOperand(1);
6447 SDValue SrcPtr = Op.getOperand(2);
6448 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
6449 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
6450 DebugLoc dl = Op.getDebugLoc();
6452 return DAG.getMemcpy(Chain, dl, DstPtr, SrcPtr,
6453 DAG.getIntPtrConstant(24), 8, false,
6454 DstSV, 0, SrcSV, 0);
6458 X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) {
6459 DebugLoc dl = Op.getDebugLoc();
6460 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
6462 default: return SDValue(); // Don't custom lower most intrinsics.
6463 // Comparison intrinsics.
6464 case Intrinsic::x86_sse_comieq_ss:
6465 case Intrinsic::x86_sse_comilt_ss:
6466 case Intrinsic::x86_sse_comile_ss:
6467 case Intrinsic::x86_sse_comigt_ss:
6468 case Intrinsic::x86_sse_comige_ss:
6469 case Intrinsic::x86_sse_comineq_ss:
6470 case Intrinsic::x86_sse_ucomieq_ss:
6471 case Intrinsic::x86_sse_ucomilt_ss:
6472 case Intrinsic::x86_sse_ucomile_ss:
6473 case Intrinsic::x86_sse_ucomigt_ss:
6474 case Intrinsic::x86_sse_ucomige_ss:
6475 case Intrinsic::x86_sse_ucomineq_ss:
6476 case Intrinsic::x86_sse2_comieq_sd:
6477 case Intrinsic::x86_sse2_comilt_sd:
6478 case Intrinsic::x86_sse2_comile_sd:
6479 case Intrinsic::x86_sse2_comigt_sd:
6480 case Intrinsic::x86_sse2_comige_sd:
6481 case Intrinsic::x86_sse2_comineq_sd:
6482 case Intrinsic::x86_sse2_ucomieq_sd:
6483 case Intrinsic::x86_sse2_ucomilt_sd:
6484 case Intrinsic::x86_sse2_ucomile_sd:
6485 case Intrinsic::x86_sse2_ucomigt_sd:
6486 case Intrinsic::x86_sse2_ucomige_sd:
6487 case Intrinsic::x86_sse2_ucomineq_sd: {
6489 ISD::CondCode CC = ISD::SETCC_INVALID;
6492 case Intrinsic::x86_sse_comieq_ss:
6493 case Intrinsic::x86_sse2_comieq_sd:
6497 case Intrinsic::x86_sse_comilt_ss:
6498 case Intrinsic::x86_sse2_comilt_sd:
6502 case Intrinsic::x86_sse_comile_ss:
6503 case Intrinsic::x86_sse2_comile_sd:
6507 case Intrinsic::x86_sse_comigt_ss:
6508 case Intrinsic::x86_sse2_comigt_sd:
6512 case Intrinsic::x86_sse_comige_ss:
6513 case Intrinsic::x86_sse2_comige_sd:
6517 case Intrinsic::x86_sse_comineq_ss:
6518 case Intrinsic::x86_sse2_comineq_sd:
6522 case Intrinsic::x86_sse_ucomieq_ss:
6523 case Intrinsic::x86_sse2_ucomieq_sd:
6524 Opc = X86ISD::UCOMI;
6527 case Intrinsic::x86_sse_ucomilt_ss:
6528 case Intrinsic::x86_sse2_ucomilt_sd:
6529 Opc = X86ISD::UCOMI;
6532 case Intrinsic::x86_sse_ucomile_ss:
6533 case Intrinsic::x86_sse2_ucomile_sd:
6534 Opc = X86ISD::UCOMI;
6537 case Intrinsic::x86_sse_ucomigt_ss:
6538 case Intrinsic::x86_sse2_ucomigt_sd:
6539 Opc = X86ISD::UCOMI;
6542 case Intrinsic::x86_sse_ucomige_ss:
6543 case Intrinsic::x86_sse2_ucomige_sd:
6544 Opc = X86ISD::UCOMI;
6547 case Intrinsic::x86_sse_ucomineq_ss:
6548 case Intrinsic::x86_sse2_ucomineq_sd:
6549 Opc = X86ISD::UCOMI;
6554 SDValue LHS = Op.getOperand(1);
6555 SDValue RHS = Op.getOperand(2);
6556 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG);
6557 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!");
6558 SDValue Cond = DAG.getNode(Opc, dl, MVT::i32, LHS, RHS);
6559 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
6560 DAG.getConstant(X86CC, MVT::i8), Cond);
6561 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
6563 // ptest intrinsics. The intrinsic these come from are designed to return
6564 // an integer value, not just an instruction so lower it to the ptest
6565 // pattern and a setcc for the result.
6566 case Intrinsic::x86_sse41_ptestz:
6567 case Intrinsic::x86_sse41_ptestc:
6568 case Intrinsic::x86_sse41_ptestnzc:{
6571 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
6572 case Intrinsic::x86_sse41_ptestz:
6574 X86CC = X86::COND_E;
6576 case Intrinsic::x86_sse41_ptestc:
6578 X86CC = X86::COND_B;
6580 case Intrinsic::x86_sse41_ptestnzc:
6582 X86CC = X86::COND_A;
6586 SDValue LHS = Op.getOperand(1);
6587 SDValue RHS = Op.getOperand(2);
6588 SDValue Test = DAG.getNode(X86ISD::PTEST, dl, MVT::i32, LHS, RHS);
6589 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
6590 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
6591 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
6594 // Fix vector shift instructions where the last operand is a non-immediate
6596 case Intrinsic::x86_sse2_pslli_w:
6597 case Intrinsic::x86_sse2_pslli_d:
6598 case Intrinsic::x86_sse2_pslli_q:
6599 case Intrinsic::x86_sse2_psrli_w:
6600 case Intrinsic::x86_sse2_psrli_d:
6601 case Intrinsic::x86_sse2_psrli_q:
6602 case Intrinsic::x86_sse2_psrai_w:
6603 case Intrinsic::x86_sse2_psrai_d:
6604 case Intrinsic::x86_mmx_pslli_w:
6605 case Intrinsic::x86_mmx_pslli_d:
6606 case Intrinsic::x86_mmx_pslli_q:
6607 case Intrinsic::x86_mmx_psrli_w:
6608 case Intrinsic::x86_mmx_psrli_d:
6609 case Intrinsic::x86_mmx_psrli_q:
6610 case Intrinsic::x86_mmx_psrai_w:
6611 case Intrinsic::x86_mmx_psrai_d: {
6612 SDValue ShAmt = Op.getOperand(2);
6613 if (isa<ConstantSDNode>(ShAmt))
6616 unsigned NewIntNo = 0;
6617 EVT ShAmtVT = MVT::v4i32;
6619 case Intrinsic::x86_sse2_pslli_w:
6620 NewIntNo = Intrinsic::x86_sse2_psll_w;
6622 case Intrinsic::x86_sse2_pslli_d:
6623 NewIntNo = Intrinsic::x86_sse2_psll_d;
6625 case Intrinsic::x86_sse2_pslli_q:
6626 NewIntNo = Intrinsic::x86_sse2_psll_q;
6628 case Intrinsic::x86_sse2_psrli_w:
6629 NewIntNo = Intrinsic::x86_sse2_psrl_w;
6631 case Intrinsic::x86_sse2_psrli_d:
6632 NewIntNo = Intrinsic::x86_sse2_psrl_d;
6634 case Intrinsic::x86_sse2_psrli_q:
6635 NewIntNo = Intrinsic::x86_sse2_psrl_q;
6637 case Intrinsic::x86_sse2_psrai_w:
6638 NewIntNo = Intrinsic::x86_sse2_psra_w;
6640 case Intrinsic::x86_sse2_psrai_d:
6641 NewIntNo = Intrinsic::x86_sse2_psra_d;
6644 ShAmtVT = MVT::v2i32;
6646 case Intrinsic::x86_mmx_pslli_w:
6647 NewIntNo = Intrinsic::x86_mmx_psll_w;
6649 case Intrinsic::x86_mmx_pslli_d:
6650 NewIntNo = Intrinsic::x86_mmx_psll_d;
6652 case Intrinsic::x86_mmx_pslli_q:
6653 NewIntNo = Intrinsic::x86_mmx_psll_q;
6655 case Intrinsic::x86_mmx_psrli_w:
6656 NewIntNo = Intrinsic::x86_mmx_psrl_w;
6658 case Intrinsic::x86_mmx_psrli_d:
6659 NewIntNo = Intrinsic::x86_mmx_psrl_d;
6661 case Intrinsic::x86_mmx_psrli_q:
6662 NewIntNo = Intrinsic::x86_mmx_psrl_q;
6664 case Intrinsic::x86_mmx_psrai_w:
6665 NewIntNo = Intrinsic::x86_mmx_psra_w;
6667 case Intrinsic::x86_mmx_psrai_d:
6668 NewIntNo = Intrinsic::x86_mmx_psra_d;
6670 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
6676 // The vector shift intrinsics with scalars uses 32b shift amounts but
6677 // the sse2/mmx shift instructions reads 64 bits. Set the upper 32 bits
6681 ShOps[1] = DAG.getConstant(0, MVT::i32);
6682 if (ShAmtVT == MVT::v4i32) {
6683 ShOps[2] = DAG.getUNDEF(MVT::i32);
6684 ShOps[3] = DAG.getUNDEF(MVT::i32);
6685 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, ShAmtVT, &ShOps[0], 4);
6687 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, ShAmtVT, &ShOps[0], 2);
6690 EVT VT = Op.getValueType();
6691 ShAmt = DAG.getNode(ISD::BIT_CONVERT, dl, VT, ShAmt);
6692 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
6693 DAG.getConstant(NewIntNo, MVT::i32),
6694 Op.getOperand(1), ShAmt);
6699 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) {
6700 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
6701 DebugLoc dl = Op.getDebugLoc();
6704 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
6706 DAG.getConstant(TD->getPointerSize(),
6707 Subtarget->is64Bit() ? MVT::i64 : MVT::i32);
6708 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
6709 DAG.getNode(ISD::ADD, dl, getPointerTy(),
6714 // Just load the return address.
6715 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
6716 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
6717 RetAddrFI, NULL, 0);
6720 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) {
6721 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
6722 MFI->setFrameAddressIsTaken(true);
6723 EVT VT = Op.getValueType();
6724 DebugLoc dl = Op.getDebugLoc(); // FIXME probably not meaningful
6725 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
6726 unsigned FrameReg = Subtarget->is64Bit() ? X86::RBP : X86::EBP;
6727 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
6729 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr, NULL, 0);
6733 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
6734 SelectionDAG &DAG) {
6735 return DAG.getIntPtrConstant(2*TD->getPointerSize());
6738 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG)
6740 MachineFunction &MF = DAG.getMachineFunction();
6741 SDValue Chain = Op.getOperand(0);
6742 SDValue Offset = Op.getOperand(1);
6743 SDValue Handler = Op.getOperand(2);
6744 DebugLoc dl = Op.getDebugLoc();
6746 SDValue Frame = DAG.getRegister(Subtarget->is64Bit() ? X86::RBP : X86::EBP,
6748 unsigned StoreAddrReg = (Subtarget->is64Bit() ? X86::RCX : X86::ECX);
6750 SDValue StoreAddr = DAG.getNode(ISD::SUB, dl, getPointerTy(), Frame,
6751 DAG.getIntPtrConstant(-TD->getPointerSize()));
6752 StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), StoreAddr, Offset);
6753 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, NULL, 0);
6754 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
6755 MF.getRegInfo().addLiveOut(StoreAddrReg);
6757 return DAG.getNode(X86ISD::EH_RETURN, dl,
6759 Chain, DAG.getRegister(StoreAddrReg, getPointerTy()));
6762 SDValue X86TargetLowering::LowerTRAMPOLINE(SDValue Op,
6763 SelectionDAG &DAG) {
6764 SDValue Root = Op.getOperand(0);
6765 SDValue Trmp = Op.getOperand(1); // trampoline
6766 SDValue FPtr = Op.getOperand(2); // nested function
6767 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
6768 DebugLoc dl = Op.getDebugLoc();
6770 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
6772 const X86InstrInfo *TII =
6773 ((X86TargetMachine&)getTargetMachine()).getInstrInfo();
6775 if (Subtarget->is64Bit()) {
6776 SDValue OutChains[6];
6778 // Large code-model.
6780 const unsigned char JMP64r = TII->getBaseOpcodeFor(X86::JMP64r);
6781 const unsigned char MOV64ri = TII->getBaseOpcodeFor(X86::MOV64ri);
6783 const unsigned char N86R10 = RegInfo->getX86RegNum(X86::R10);
6784 const unsigned char N86R11 = RegInfo->getX86RegNum(X86::R11);
6786 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
6788 // Load the pointer to the nested function into R11.
6789 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
6790 SDValue Addr = Trmp;
6791 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
6794 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
6795 DAG.getConstant(2, MVT::i64));
6796 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr, TrmpAddr, 2, false, 2);
6798 // Load the 'nest' parameter value into R10.
6799 // R10 is specified in X86CallingConv.td
6800 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
6801 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
6802 DAG.getConstant(10, MVT::i64));
6803 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
6804 Addr, TrmpAddr, 10);
6806 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
6807 DAG.getConstant(12, MVT::i64));
6808 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr, TrmpAddr, 12, false, 2);
6810 // Jump to the nested function.
6811 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
6812 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
6813 DAG.getConstant(20, MVT::i64));
6814 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
6815 Addr, TrmpAddr, 20);
6817 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
6818 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
6819 DAG.getConstant(22, MVT::i64));
6820 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr,
6824 { Trmp, DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 6) };
6825 return DAG.getMergeValues(Ops, 2, dl);
6827 const Function *Func =
6828 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
6829 CallingConv::ID CC = Func->getCallingConv();
6834 llvm_unreachable("Unsupported calling convention");
6835 case CallingConv::C:
6836 case CallingConv::X86_StdCall: {
6837 // Pass 'nest' parameter in ECX.
6838 // Must be kept in sync with X86CallingConv.td
6841 // Check that ECX wasn't needed by an 'inreg' parameter.
6842 const FunctionType *FTy = Func->getFunctionType();
6843 const AttrListPtr &Attrs = Func->getAttributes();
6845 if (!Attrs.isEmpty() && !Func->isVarArg()) {
6846 unsigned InRegCount = 0;
6849 for (FunctionType::param_iterator I = FTy->param_begin(),
6850 E = FTy->param_end(); I != E; ++I, ++Idx)
6851 if (Attrs.paramHasAttr(Idx, Attribute::InReg))
6852 // FIXME: should only count parameters that are lowered to integers.
6853 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32;
6855 if (InRegCount > 2) {
6856 llvm_report_error("Nest register in use - reduce number of inreg parameters!");
6861 case CallingConv::X86_FastCall:
6862 case CallingConv::Fast:
6863 // Pass 'nest' parameter in EAX.
6864 // Must be kept in sync with X86CallingConv.td
6869 SDValue OutChains[4];
6872 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
6873 DAG.getConstant(10, MVT::i32));
6874 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
6876 const unsigned char MOV32ri = TII->getBaseOpcodeFor(X86::MOV32ri);
6877 const unsigned char N86Reg = RegInfo->getX86RegNum(NestReg);
6878 OutChains[0] = DAG.getStore(Root, dl,
6879 DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
6882 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
6883 DAG.getConstant(1, MVT::i32));
6884 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr, TrmpAddr, 1, false, 1);
6886 const unsigned char JMP = TII->getBaseOpcodeFor(X86::JMP);
6887 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
6888 DAG.getConstant(5, MVT::i32));
6889 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr,
6890 TrmpAddr, 5, false, 1);
6892 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
6893 DAG.getConstant(6, MVT::i32));
6894 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr, TrmpAddr, 6, false, 1);
6897 { Trmp, DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 4) };
6898 return DAG.getMergeValues(Ops, 2, dl);
6902 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) {
6904 The rounding mode is in bits 11:10 of FPSR, and has the following
6911 FLT_ROUNDS, on the other hand, expects the following:
6918 To perform the conversion, we do:
6919 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
6922 MachineFunction &MF = DAG.getMachineFunction();
6923 const TargetMachine &TM = MF.getTarget();
6924 const TargetFrameInfo &TFI = *TM.getFrameInfo();
6925 unsigned StackAlignment = TFI.getStackAlignment();
6926 EVT VT = Op.getValueType();
6927 DebugLoc dl = Op.getDebugLoc();
6929 // Save FP Control Word to stack slot
6930 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false);
6931 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
6933 SDValue Chain = DAG.getNode(X86ISD::FNSTCW16m, dl, MVT::Other,
6934 DAG.getEntryNode(), StackSlot);
6936 // Load FP Control Word from stack slot
6937 SDValue CWD = DAG.getLoad(MVT::i16, dl, Chain, StackSlot, NULL, 0);
6939 // Transform as necessary
6941 DAG.getNode(ISD::SRL, dl, MVT::i16,
6942 DAG.getNode(ISD::AND, dl, MVT::i16,
6943 CWD, DAG.getConstant(0x800, MVT::i16)),
6944 DAG.getConstant(11, MVT::i8));
6946 DAG.getNode(ISD::SRL, dl, MVT::i16,
6947 DAG.getNode(ISD::AND, dl, MVT::i16,
6948 CWD, DAG.getConstant(0x400, MVT::i16)),
6949 DAG.getConstant(9, MVT::i8));
6952 DAG.getNode(ISD::AND, dl, MVT::i16,
6953 DAG.getNode(ISD::ADD, dl, MVT::i16,
6954 DAG.getNode(ISD::OR, dl, MVT::i16, CWD1, CWD2),
6955 DAG.getConstant(1, MVT::i16)),
6956 DAG.getConstant(3, MVT::i16));
6959 return DAG.getNode((VT.getSizeInBits() < 16 ?
6960 ISD::TRUNCATE : ISD::ZERO_EXTEND), dl, VT, RetVal);
6963 SDValue X86TargetLowering::LowerCTLZ(SDValue Op, SelectionDAG &DAG) {
6964 EVT VT = Op.getValueType();
6966 unsigned NumBits = VT.getSizeInBits();
6967 DebugLoc dl = Op.getDebugLoc();
6969 Op = Op.getOperand(0);
6970 if (VT == MVT::i8) {
6971 // Zero extend to i32 since there is not an i8 bsr.
6973 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
6976 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
6977 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
6978 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
6980 // If src is zero (i.e. bsr sets ZF), returns NumBits.
6981 SmallVector<SDValue, 4> Ops;
6983 Ops.push_back(DAG.getConstant(NumBits+NumBits-1, OpVT));
6984 Ops.push_back(DAG.getConstant(X86::COND_E, MVT::i8));
6985 Ops.push_back(Op.getValue(1));
6986 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, &Ops[0], 4);
6988 // Finally xor with NumBits-1.
6989 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
6992 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
6996 SDValue X86TargetLowering::LowerCTTZ(SDValue Op, SelectionDAG &DAG) {
6997 EVT VT = Op.getValueType();
6999 unsigned NumBits = VT.getSizeInBits();
7000 DebugLoc dl = Op.getDebugLoc();
7002 Op = Op.getOperand(0);
7003 if (VT == MVT::i8) {
7005 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
7008 // Issue a bsf (scan bits forward) which also sets EFLAGS.
7009 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
7010 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op);
7012 // If src is zero (i.e. bsf sets ZF), returns NumBits.
7013 SmallVector<SDValue, 4> Ops;
7015 Ops.push_back(DAG.getConstant(NumBits, OpVT));
7016 Ops.push_back(DAG.getConstant(X86::COND_E, MVT::i8));
7017 Ops.push_back(Op.getValue(1));
7018 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, &Ops[0], 4);
7021 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
7025 SDValue X86TargetLowering::LowerMUL_V2I64(SDValue Op, SelectionDAG &DAG) {
7026 EVT VT = Op.getValueType();
7027 assert(VT == MVT::v2i64 && "Only know how to lower V2I64 multiply");
7028 DebugLoc dl = Op.getDebugLoc();
7030 // ulong2 Ahi = __builtin_ia32_psrlqi128( a, 32);
7031 // ulong2 Bhi = __builtin_ia32_psrlqi128( b, 32);
7032 // ulong2 AloBlo = __builtin_ia32_pmuludq128( a, b );
7033 // ulong2 AloBhi = __builtin_ia32_pmuludq128( a, Bhi );
7034 // ulong2 AhiBlo = __builtin_ia32_pmuludq128( Ahi, b );
7036 // AloBhi = __builtin_ia32_psllqi128( AloBhi, 32 );
7037 // AhiBlo = __builtin_ia32_psllqi128( AhiBlo, 32 );
7038 // return AloBlo + AloBhi + AhiBlo;
7040 SDValue A = Op.getOperand(0);
7041 SDValue B = Op.getOperand(1);
7043 SDValue Ahi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
7044 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32),
7045 A, DAG.getConstant(32, MVT::i32));
7046 SDValue Bhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
7047 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32),
7048 B, DAG.getConstant(32, MVT::i32));
7049 SDValue AloBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
7050 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32),
7052 SDValue AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
7053 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32),
7055 SDValue AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
7056 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32),
7058 AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
7059 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32),
7060 AloBhi, DAG.getConstant(32, MVT::i32));
7061 AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
7062 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32),
7063 AhiBlo, DAG.getConstant(32, MVT::i32));
7064 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
7065 Res = DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
7070 SDValue X86TargetLowering::LowerXALUO(SDValue Op, SelectionDAG &DAG) {
7071 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
7072 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
7073 // looks for this combo and may remove the "setcc" instruction if the "setcc"
7074 // has only one use.
7075 SDNode *N = Op.getNode();
7076 SDValue LHS = N->getOperand(0);
7077 SDValue RHS = N->getOperand(1);
7078 unsigned BaseOp = 0;
7080 DebugLoc dl = Op.getDebugLoc();
7082 switch (Op.getOpcode()) {
7083 default: llvm_unreachable("Unknown ovf instruction!");
7085 // A subtract of one will be selected as a INC. Note that INC doesn't
7086 // set CF, so we can't do this for UADDO.
7087 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op))
7088 if (C->getAPIntValue() == 1) {
7089 BaseOp = X86ISD::INC;
7093 BaseOp = X86ISD::ADD;
7097 BaseOp = X86ISD::ADD;
7101 // A subtract of one will be selected as a DEC. Note that DEC doesn't
7102 // set CF, so we can't do this for USUBO.
7103 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op))
7104 if (C->getAPIntValue() == 1) {
7105 BaseOp = X86ISD::DEC;
7109 BaseOp = X86ISD::SUB;
7113 BaseOp = X86ISD::SUB;
7117 BaseOp = X86ISD::SMUL;
7121 BaseOp = X86ISD::UMUL;
7126 // Also sets EFLAGS.
7127 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
7128 SDValue Sum = DAG.getNode(BaseOp, dl, VTs, LHS, RHS);
7131 DAG.getNode(X86ISD::SETCC, dl, N->getValueType(1),
7132 DAG.getConstant(Cond, MVT::i32), SDValue(Sum.getNode(), 1));
7134 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), SetCC);
7138 SDValue X86TargetLowering::LowerCMP_SWAP(SDValue Op, SelectionDAG &DAG) {
7139 EVT T = Op.getValueType();
7140 DebugLoc dl = Op.getDebugLoc();
7143 switch(T.getSimpleVT().SimpleTy) {
7145 assert(false && "Invalid value type!");
7146 case MVT::i8: Reg = X86::AL; size = 1; break;
7147 case MVT::i16: Reg = X86::AX; size = 2; break;
7148 case MVT::i32: Reg = X86::EAX; size = 4; break;
7150 assert(Subtarget->is64Bit() && "Node not type legal!");
7151 Reg = X86::RAX; size = 8;
7154 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), dl, Reg,
7155 Op.getOperand(2), SDValue());
7156 SDValue Ops[] = { cpIn.getValue(0),
7159 DAG.getTargetConstant(size, MVT::i8),
7161 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
7162 SDValue Result = DAG.getNode(X86ISD::LCMPXCHG_DAG, dl, Tys, Ops, 5);
7164 DAG.getCopyFromReg(Result.getValue(0), dl, Reg, T, Result.getValue(1));
7168 SDValue X86TargetLowering::LowerREADCYCLECOUNTER(SDValue Op,
7169 SelectionDAG &DAG) {
7170 assert(Subtarget->is64Bit() && "Result not type legalized?");
7171 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
7172 SDValue TheChain = Op.getOperand(0);
7173 DebugLoc dl = Op.getDebugLoc();
7174 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
7175 SDValue rax = DAG.getCopyFromReg(rd, dl, X86::RAX, MVT::i64, rd.getValue(1));
7176 SDValue rdx = DAG.getCopyFromReg(rax.getValue(1), dl, X86::RDX, MVT::i64,
7178 SDValue Tmp = DAG.getNode(ISD::SHL, dl, MVT::i64, rdx,
7179 DAG.getConstant(32, MVT::i8));
7181 DAG.getNode(ISD::OR, dl, MVT::i64, rax, Tmp),
7184 return DAG.getMergeValues(Ops, 2, dl);
7187 SDValue X86TargetLowering::LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) {
7188 SDNode *Node = Op.getNode();
7189 DebugLoc dl = Node->getDebugLoc();
7190 EVT T = Node->getValueType(0);
7191 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
7192 DAG.getConstant(0, T), Node->getOperand(2));
7193 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
7194 cast<AtomicSDNode>(Node)->getMemoryVT(),
7195 Node->getOperand(0),
7196 Node->getOperand(1), negOp,
7197 cast<AtomicSDNode>(Node)->getSrcValue(),
7198 cast<AtomicSDNode>(Node)->getAlignment());
7201 /// LowerOperation - Provide custom lowering hooks for some operations.
7203 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
7204 switch (Op.getOpcode()) {
7205 default: llvm_unreachable("Should not custom lower this!");
7206 case ISD::ATOMIC_CMP_SWAP: return LowerCMP_SWAP(Op,DAG);
7207 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
7208 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
7209 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
7210 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
7211 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
7212 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
7213 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
7214 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
7215 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
7216 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
7217 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
7218 case ISD::SHL_PARTS:
7219 case ISD::SRA_PARTS:
7220 case ISD::SRL_PARTS: return LowerShift(Op, DAG);
7221 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
7222 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
7223 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
7224 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
7225 case ISD::FABS: return LowerFABS(Op, DAG);
7226 case ISD::FNEG: return LowerFNEG(Op, DAG);
7227 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
7228 case ISD::SETCC: return LowerSETCC(Op, DAG);
7229 case ISD::VSETCC: return LowerVSETCC(Op, DAG);
7230 case ISD::SELECT: return LowerSELECT(Op, DAG);
7231 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
7232 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
7233 case ISD::VASTART: return LowerVASTART(Op, DAG);
7234 case ISD::VAARG: return LowerVAARG(Op, DAG);
7235 case ISD::VACOPY: return LowerVACOPY(Op, DAG);
7236 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
7237 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
7238 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
7239 case ISD::FRAME_TO_ARGS_OFFSET:
7240 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
7241 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
7242 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
7243 case ISD::TRAMPOLINE: return LowerTRAMPOLINE(Op, DAG);
7244 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
7245 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
7246 case ISD::CTTZ: return LowerCTTZ(Op, DAG);
7247 case ISD::MUL: return LowerMUL_V2I64(Op, DAG);
7253 case ISD::UMULO: return LowerXALUO(Op, DAG);
7254 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, DAG);
7258 void X86TargetLowering::
7259 ReplaceATOMIC_BINARY_64(SDNode *Node, SmallVectorImpl<SDValue>&Results,
7260 SelectionDAG &DAG, unsigned NewOp) {
7261 EVT T = Node->getValueType(0);
7262 DebugLoc dl = Node->getDebugLoc();
7263 assert (T == MVT::i64 && "Only know how to expand i64 atomics");
7265 SDValue Chain = Node->getOperand(0);
7266 SDValue In1 = Node->getOperand(1);
7267 SDValue In2L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
7268 Node->getOperand(2), DAG.getIntPtrConstant(0));
7269 SDValue In2H = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
7270 Node->getOperand(2), DAG.getIntPtrConstant(1));
7271 SDValue Ops[] = { Chain, In1, In2L, In2H };
7272 SDVTList Tys = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other);
7274 DAG.getMemIntrinsicNode(NewOp, dl, Tys, Ops, 4, MVT::i64,
7275 cast<MemSDNode>(Node)->getMemOperand());
7276 SDValue OpsF[] = { Result.getValue(0), Result.getValue(1)};
7277 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2));
7278 Results.push_back(Result.getValue(2));
7281 /// ReplaceNodeResults - Replace a node with an illegal result type
7282 /// with a new node built out of custom code.
7283 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
7284 SmallVectorImpl<SDValue>&Results,
7285 SelectionDAG &DAG) {
7286 DebugLoc dl = N->getDebugLoc();
7287 switch (N->getOpcode()) {
7289 assert(false && "Do not know how to custom type legalize this operation!");
7291 case ISD::FP_TO_SINT: {
7292 std::pair<SDValue,SDValue> Vals =
7293 FP_TO_INTHelper(SDValue(N, 0), DAG, true);
7294 SDValue FIST = Vals.first, StackSlot = Vals.second;
7295 if (FIST.getNode() != 0) {
7296 EVT VT = N->getValueType(0);
7297 // Return a load from the stack slot.
7298 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot, NULL, 0));
7302 case ISD::READCYCLECOUNTER: {
7303 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
7304 SDValue TheChain = N->getOperand(0);
7305 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
7306 SDValue eax = DAG.getCopyFromReg(rd, dl, X86::EAX, MVT::i32,
7308 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), dl, X86::EDX, MVT::i32,
7310 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
7311 SDValue Ops[] = { eax, edx };
7312 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Ops, 2));
7313 Results.push_back(edx.getValue(1));
7320 EVT WidenVT = getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
7321 Results.push_back(DAG.UnrollVectorOp(N, WidenVT.getVectorNumElements()));
7324 case ISD::ATOMIC_CMP_SWAP: {
7325 EVT T = N->getValueType(0);
7326 assert (T == MVT::i64 && "Only know how to expand i64 Cmp and Swap");
7327 SDValue cpInL, cpInH;
7328 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(2),
7329 DAG.getConstant(0, MVT::i32));
7330 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(2),
7331 DAG.getConstant(1, MVT::i32));
7332 cpInL = DAG.getCopyToReg(N->getOperand(0), dl, X86::EAX, cpInL, SDValue());
7333 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl, X86::EDX, cpInH,
7335 SDValue swapInL, swapInH;
7336 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(3),
7337 DAG.getConstant(0, MVT::i32));
7338 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(3),
7339 DAG.getConstant(1, MVT::i32));
7340 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl, X86::EBX, swapInL,
7342 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl, X86::ECX, swapInH,
7343 swapInL.getValue(1));
7344 SDValue Ops[] = { swapInH.getValue(0),
7346 swapInH.getValue(1) };
7347 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
7348 SDValue Result = DAG.getNode(X86ISD::LCMPXCHG8_DAG, dl, Tys, Ops, 3);
7349 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl, X86::EAX,
7350 MVT::i32, Result.getValue(1));
7351 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl, X86::EDX,
7352 MVT::i32, cpOutL.getValue(2));
7353 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
7354 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2));
7355 Results.push_back(cpOutH.getValue(1));
7358 case ISD::ATOMIC_LOAD_ADD:
7359 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMADD64_DAG);
7361 case ISD::ATOMIC_LOAD_AND:
7362 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMAND64_DAG);
7364 case ISD::ATOMIC_LOAD_NAND:
7365 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMNAND64_DAG);
7367 case ISD::ATOMIC_LOAD_OR:
7368 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMOR64_DAG);
7370 case ISD::ATOMIC_LOAD_SUB:
7371 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSUB64_DAG);
7373 case ISD::ATOMIC_LOAD_XOR:
7374 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMXOR64_DAG);
7376 case ISD::ATOMIC_SWAP:
7377 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSWAP64_DAG);
7382 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
7384 default: return NULL;
7385 case X86ISD::BSF: return "X86ISD::BSF";
7386 case X86ISD::BSR: return "X86ISD::BSR";
7387 case X86ISD::SHLD: return "X86ISD::SHLD";
7388 case X86ISD::SHRD: return "X86ISD::SHRD";
7389 case X86ISD::FAND: return "X86ISD::FAND";
7390 case X86ISD::FOR: return "X86ISD::FOR";
7391 case X86ISD::FXOR: return "X86ISD::FXOR";
7392 case X86ISD::FSRL: return "X86ISD::FSRL";
7393 case X86ISD::FILD: return "X86ISD::FILD";
7394 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
7395 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
7396 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
7397 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
7398 case X86ISD::FLD: return "X86ISD::FLD";
7399 case X86ISD::FST: return "X86ISD::FST";
7400 case X86ISD::CALL: return "X86ISD::CALL";
7401 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
7402 case X86ISD::BT: return "X86ISD::BT";
7403 case X86ISD::CMP: return "X86ISD::CMP";
7404 case X86ISD::COMI: return "X86ISD::COMI";
7405 case X86ISD::UCOMI: return "X86ISD::UCOMI";
7406 case X86ISD::SETCC: return "X86ISD::SETCC";
7407 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY";
7408 case X86ISD::CMOV: return "X86ISD::CMOV";
7409 case X86ISD::BRCOND: return "X86ISD::BRCOND";
7410 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
7411 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
7412 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
7413 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
7414 case X86ISD::Wrapper: return "X86ISD::Wrapper";
7415 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
7416 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
7417 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
7418 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
7419 case X86ISD::PINSRB: return "X86ISD::PINSRB";
7420 case X86ISD::PINSRW: return "X86ISD::PINSRW";
7421 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
7422 case X86ISD::FMAX: return "X86ISD::FMAX";
7423 case X86ISD::FMIN: return "X86ISD::FMIN";
7424 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
7425 case X86ISD::FRCP: return "X86ISD::FRCP";
7426 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
7427 case X86ISD::SegmentBaseAddress: return "X86ISD::SegmentBaseAddress";
7428 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
7429 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
7430 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
7431 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
7432 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
7433 case X86ISD::ATOMADD64_DAG: return "X86ISD::ATOMADD64_DAG";
7434 case X86ISD::ATOMSUB64_DAG: return "X86ISD::ATOMSUB64_DAG";
7435 case X86ISD::ATOMOR64_DAG: return "X86ISD::ATOMOR64_DAG";
7436 case X86ISD::ATOMXOR64_DAG: return "X86ISD::ATOMXOR64_DAG";
7437 case X86ISD::ATOMAND64_DAG: return "X86ISD::ATOMAND64_DAG";
7438 case X86ISD::ATOMNAND64_DAG: return "X86ISD::ATOMNAND64_DAG";
7439 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
7440 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
7441 case X86ISD::VSHL: return "X86ISD::VSHL";
7442 case X86ISD::VSRL: return "X86ISD::VSRL";
7443 case X86ISD::CMPPD: return "X86ISD::CMPPD";
7444 case X86ISD::CMPPS: return "X86ISD::CMPPS";
7445 case X86ISD::PCMPEQB: return "X86ISD::PCMPEQB";
7446 case X86ISD::PCMPEQW: return "X86ISD::PCMPEQW";
7447 case X86ISD::PCMPEQD: return "X86ISD::PCMPEQD";
7448 case X86ISD::PCMPEQQ: return "X86ISD::PCMPEQQ";
7449 case X86ISD::PCMPGTB: return "X86ISD::PCMPGTB";
7450 case X86ISD::PCMPGTW: return "X86ISD::PCMPGTW";
7451 case X86ISD::PCMPGTD: return "X86ISD::PCMPGTD";
7452 case X86ISD::PCMPGTQ: return "X86ISD::PCMPGTQ";
7453 case X86ISD::ADD: return "X86ISD::ADD";
7454 case X86ISD::SUB: return "X86ISD::SUB";
7455 case X86ISD::SMUL: return "X86ISD::SMUL";
7456 case X86ISD::UMUL: return "X86ISD::UMUL";
7457 case X86ISD::INC: return "X86ISD::INC";
7458 case X86ISD::DEC: return "X86ISD::DEC";
7459 case X86ISD::OR: return "X86ISD::OR";
7460 case X86ISD::XOR: return "X86ISD::XOR";
7461 case X86ISD::AND: return "X86ISD::AND";
7462 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
7463 case X86ISD::PTEST: return "X86ISD::PTEST";
7464 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
7468 // isLegalAddressingMode - Return true if the addressing mode represented
7469 // by AM is legal for this target, for a load/store of the specified type.
7470 bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
7471 const Type *Ty) const {
7472 // X86 supports extremely general addressing modes.
7473 CodeModel::Model M = getTargetMachine().getCodeModel();
7475 // X86 allows a sign-extended 32-bit immediate field as a displacement.
7476 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != NULL))
7481 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
7483 // If a reference to this global requires an extra load, we can't fold it.
7484 if (isGlobalStubReference(GVFlags))
7487 // If BaseGV requires a register for the PIC base, we cannot also have a
7488 // BaseReg specified.
7489 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
7492 // If lower 4G is not available, then we must use rip-relative addressing.
7493 if (Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
7503 // These scales always work.
7508 // These scales are formed with basereg+scalereg. Only accept if there is
7513 default: // Other stuff never works.
7521 bool X86TargetLowering::isTruncateFree(const Type *Ty1, const Type *Ty2) const {
7522 if (!Ty1->isInteger() || !Ty2->isInteger())
7524 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
7525 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
7526 if (NumBits1 <= NumBits2)
7528 return Subtarget->is64Bit() || NumBits1 < 64;
7531 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
7532 if (!VT1.isInteger() || !VT2.isInteger())
7534 unsigned NumBits1 = VT1.getSizeInBits();
7535 unsigned NumBits2 = VT2.getSizeInBits();
7536 if (NumBits1 <= NumBits2)
7538 return Subtarget->is64Bit() || NumBits1 < 64;
7541 bool X86TargetLowering::isZExtFree(const Type *Ty1, const Type *Ty2) const {
7542 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
7543 return Ty1 == Type::getInt32Ty(Ty1->getContext()) &&
7544 Ty2 == Type::getInt64Ty(Ty1->getContext()) && Subtarget->is64Bit();
7547 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
7548 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
7549 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
7552 bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
7553 // i16 instructions are longer (0x66 prefix) and potentially slower.
7554 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
7557 /// isShuffleMaskLegal - Targets can use this to indicate that they only
7558 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
7559 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
7560 /// are assumed to be legal.
7562 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
7564 // Only do shuffles on 128-bit vector types for now.
7565 if (VT.getSizeInBits() == 64)
7568 // FIXME: pshufb, blends, shifts.
7569 return (VT.getVectorNumElements() == 2 ||
7570 ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
7571 isMOVLMask(M, VT) ||
7572 isSHUFPMask(M, VT) ||
7573 isPSHUFDMask(M, VT) ||
7574 isPSHUFHWMask(M, VT) ||
7575 isPSHUFLWMask(M, VT) ||
7576 isPALIGNRMask(M, VT, Subtarget->hasSSSE3()) ||
7577 isUNPCKLMask(M, VT) ||
7578 isUNPCKHMask(M, VT) ||
7579 isUNPCKL_v_undef_Mask(M, VT) ||
7580 isUNPCKH_v_undef_Mask(M, VT));
7584 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
7586 unsigned NumElts = VT.getVectorNumElements();
7587 // FIXME: This collection of masks seems suspect.
7590 if (NumElts == 4 && VT.getSizeInBits() == 128) {
7591 return (isMOVLMask(Mask, VT) ||
7592 isCommutedMOVLMask(Mask, VT, true) ||
7593 isSHUFPMask(Mask, VT) ||
7594 isCommutedSHUFPMask(Mask, VT));
7599 //===----------------------------------------------------------------------===//
7600 // X86 Scheduler Hooks
7601 //===----------------------------------------------------------------------===//
7603 // private utility function
7605 X86TargetLowering::EmitAtomicBitwiseWithCustomInserter(MachineInstr *bInstr,
7606 MachineBasicBlock *MBB,
7614 TargetRegisterClass *RC,
7615 bool invSrc) const {
7616 // For the atomic bitwise operator, we generate
7619 // ld t1 = [bitinstr.addr]
7620 // op t2 = t1, [bitinstr.val]
7622 // lcs dest = [bitinstr.addr], t2 [EAX is implicit]
7624 // fallthrough -->nextMBB
7625 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
7626 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
7627 MachineFunction::iterator MBBIter = MBB;
7630 /// First build the CFG
7631 MachineFunction *F = MBB->getParent();
7632 MachineBasicBlock *thisMBB = MBB;
7633 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
7634 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
7635 F->insert(MBBIter, newMBB);
7636 F->insert(MBBIter, nextMBB);
7638 // Move all successors to thisMBB to nextMBB
7639 nextMBB->transferSuccessors(thisMBB);
7641 // Update thisMBB to fall through to newMBB
7642 thisMBB->addSuccessor(newMBB);
7644 // newMBB jumps to itself and fall through to nextMBB
7645 newMBB->addSuccessor(nextMBB);
7646 newMBB->addSuccessor(newMBB);
7648 // Insert instructions into newMBB based on incoming instruction
7649 assert(bInstr->getNumOperands() < X86AddrNumOperands + 4 &&
7650 "unexpected number of operands");
7651 DebugLoc dl = bInstr->getDebugLoc();
7652 MachineOperand& destOper = bInstr->getOperand(0);
7653 MachineOperand* argOpers[2 + X86AddrNumOperands];
7654 int numArgs = bInstr->getNumOperands() - 1;
7655 for (int i=0; i < numArgs; ++i)
7656 argOpers[i] = &bInstr->getOperand(i+1);
7658 // x86 address has 4 operands: base, index, scale, and displacement
7659 int lastAddrIndx = X86AddrNumOperands - 1; // [0,3]
7660 int valArgIndx = lastAddrIndx + 1;
7662 unsigned t1 = F->getRegInfo().createVirtualRegister(RC);
7663 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(LoadOpc), t1);
7664 for (int i=0; i <= lastAddrIndx; ++i)
7665 (*MIB).addOperand(*argOpers[i]);
7667 unsigned tt = F->getRegInfo().createVirtualRegister(RC);
7669 MIB = BuildMI(newMBB, dl, TII->get(notOpc), tt).addReg(t1);
7674 unsigned t2 = F->getRegInfo().createVirtualRegister(RC);
7675 assert((argOpers[valArgIndx]->isReg() ||
7676 argOpers[valArgIndx]->isImm()) &&
7678 if (argOpers[valArgIndx]->isReg())
7679 MIB = BuildMI(newMBB, dl, TII->get(regOpc), t2);
7681 MIB = BuildMI(newMBB, dl, TII->get(immOpc), t2);
7683 (*MIB).addOperand(*argOpers[valArgIndx]);
7685 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), EAXreg);
7688 MIB = BuildMI(newMBB, dl, TII->get(CXchgOpc));
7689 for (int i=0; i <= lastAddrIndx; ++i)
7690 (*MIB).addOperand(*argOpers[i]);
7692 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand");
7693 (*MIB).setMemRefs(bInstr->memoperands_begin(),
7694 bInstr->memoperands_end());
7696 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), destOper.getReg());
7700 BuildMI(newMBB, dl, TII->get(X86::JNE)).addMBB(newMBB);
7702 F->DeleteMachineInstr(bInstr); // The pseudo instruction is gone now.
7706 // private utility function: 64 bit atomics on 32 bit host.
7708 X86TargetLowering::EmitAtomicBit6432WithCustomInserter(MachineInstr *bInstr,
7709 MachineBasicBlock *MBB,
7714 bool invSrc) const {
7715 // For the atomic bitwise operator, we generate
7716 // thisMBB (instructions are in pairs, except cmpxchg8b)
7717 // ld t1,t2 = [bitinstr.addr]
7719 // out1, out2 = phi (thisMBB, t1/t2) (newMBB, t3/t4)
7720 // op t5, t6 <- out1, out2, [bitinstr.val]
7721 // (for SWAP, substitute: mov t5, t6 <- [bitinstr.val])
7722 // mov ECX, EBX <- t5, t6
7723 // mov EAX, EDX <- t1, t2
7724 // cmpxchg8b [bitinstr.addr] [EAX, EDX, EBX, ECX implicit]
7725 // mov t3, t4 <- EAX, EDX
7727 // result in out1, out2
7728 // fallthrough -->nextMBB
7730 const TargetRegisterClass *RC = X86::GR32RegisterClass;
7731 const unsigned LoadOpc = X86::MOV32rm;
7732 const unsigned copyOpc = X86::MOV32rr;
7733 const unsigned NotOpc = X86::NOT32r;
7734 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
7735 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
7736 MachineFunction::iterator MBBIter = MBB;
7739 /// First build the CFG
7740 MachineFunction *F = MBB->getParent();
7741 MachineBasicBlock *thisMBB = MBB;
7742 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
7743 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
7744 F->insert(MBBIter, newMBB);
7745 F->insert(MBBIter, nextMBB);
7747 // Move all successors to thisMBB to nextMBB
7748 nextMBB->transferSuccessors(thisMBB);
7750 // Update thisMBB to fall through to newMBB
7751 thisMBB->addSuccessor(newMBB);
7753 // newMBB jumps to itself and fall through to nextMBB
7754 newMBB->addSuccessor(nextMBB);
7755 newMBB->addSuccessor(newMBB);
7757 DebugLoc dl = bInstr->getDebugLoc();
7758 // Insert instructions into newMBB based on incoming instruction
7759 // There are 8 "real" operands plus 9 implicit def/uses, ignored here.
7760 assert(bInstr->getNumOperands() < X86AddrNumOperands + 14 &&
7761 "unexpected number of operands");
7762 MachineOperand& dest1Oper = bInstr->getOperand(0);
7763 MachineOperand& dest2Oper = bInstr->getOperand(1);
7764 MachineOperand* argOpers[2 + X86AddrNumOperands];
7765 for (int i=0; i < 2 + X86AddrNumOperands; ++i)
7766 argOpers[i] = &bInstr->getOperand(i+2);
7768 // x86 address has 4 operands: base, index, scale, and displacement
7769 int lastAddrIndx = X86AddrNumOperands - 1; // [0,3]
7771 unsigned t1 = F->getRegInfo().createVirtualRegister(RC);
7772 MachineInstrBuilder MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t1);
7773 for (int i=0; i <= lastAddrIndx; ++i)
7774 (*MIB).addOperand(*argOpers[i]);
7775 unsigned t2 = F->getRegInfo().createVirtualRegister(RC);
7776 MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t2);
7777 // add 4 to displacement.
7778 for (int i=0; i <= lastAddrIndx-2; ++i)
7779 (*MIB).addOperand(*argOpers[i]);
7780 MachineOperand newOp3 = *(argOpers[3]);
7782 newOp3.setImm(newOp3.getImm()+4);
7784 newOp3.setOffset(newOp3.getOffset()+4);
7785 (*MIB).addOperand(newOp3);
7786 (*MIB).addOperand(*argOpers[lastAddrIndx]);
7788 // t3/4 are defined later, at the bottom of the loop
7789 unsigned t3 = F->getRegInfo().createVirtualRegister(RC);
7790 unsigned t4 = F->getRegInfo().createVirtualRegister(RC);
7791 BuildMI(newMBB, dl, TII->get(X86::PHI), dest1Oper.getReg())
7792 .addReg(t1).addMBB(thisMBB).addReg(t3).addMBB(newMBB);
7793 BuildMI(newMBB, dl, TII->get(X86::PHI), dest2Oper.getReg())
7794 .addReg(t2).addMBB(thisMBB).addReg(t4).addMBB(newMBB);
7796 unsigned tt1 = F->getRegInfo().createVirtualRegister(RC);
7797 unsigned tt2 = F->getRegInfo().createVirtualRegister(RC);
7799 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), tt1).addReg(t1);
7800 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), tt2).addReg(t2);
7806 int valArgIndx = lastAddrIndx + 1;
7807 assert((argOpers[valArgIndx]->isReg() ||
7808 argOpers[valArgIndx]->isImm()) &&
7810 unsigned t5 = F->getRegInfo().createVirtualRegister(RC);
7811 unsigned t6 = F->getRegInfo().createVirtualRegister(RC);
7812 if (argOpers[valArgIndx]->isReg())
7813 MIB = BuildMI(newMBB, dl, TII->get(regOpcL), t5);
7815 MIB = BuildMI(newMBB, dl, TII->get(immOpcL), t5);
7816 if (regOpcL != X86::MOV32rr)
7818 (*MIB).addOperand(*argOpers[valArgIndx]);
7819 assert(argOpers[valArgIndx + 1]->isReg() ==
7820 argOpers[valArgIndx]->isReg());
7821 assert(argOpers[valArgIndx + 1]->isImm() ==
7822 argOpers[valArgIndx]->isImm());
7823 if (argOpers[valArgIndx + 1]->isReg())
7824 MIB = BuildMI(newMBB, dl, TII->get(regOpcH), t6);
7826 MIB = BuildMI(newMBB, dl, TII->get(immOpcH), t6);
7827 if (regOpcH != X86::MOV32rr)
7829 (*MIB).addOperand(*argOpers[valArgIndx + 1]);
7831 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), X86::EAX);
7833 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), X86::EDX);
7836 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), X86::EBX);
7838 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), X86::ECX);
7841 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG8B));
7842 for (int i=0; i <= lastAddrIndx; ++i)
7843 (*MIB).addOperand(*argOpers[i]);
7845 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand");
7846 (*MIB).setMemRefs(bInstr->memoperands_begin(),
7847 bInstr->memoperands_end());
7849 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), t3);
7850 MIB.addReg(X86::EAX);
7851 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), t4);
7852 MIB.addReg(X86::EDX);
7855 BuildMI(newMBB, dl, TII->get(X86::JNE)).addMBB(newMBB);
7857 F->DeleteMachineInstr(bInstr); // The pseudo instruction is gone now.
7861 // private utility function
7863 X86TargetLowering::EmitAtomicMinMaxWithCustomInserter(MachineInstr *mInstr,
7864 MachineBasicBlock *MBB,
7865 unsigned cmovOpc) const {
7866 // For the atomic min/max operator, we generate
7869 // ld t1 = [min/max.addr]
7870 // mov t2 = [min/max.val]
7872 // cmov[cond] t2 = t1
7874 // lcs dest = [bitinstr.addr], t2 [EAX is implicit]
7876 // fallthrough -->nextMBB
7878 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
7879 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
7880 MachineFunction::iterator MBBIter = MBB;
7883 /// First build the CFG
7884 MachineFunction *F = MBB->getParent();
7885 MachineBasicBlock *thisMBB = MBB;
7886 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
7887 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
7888 F->insert(MBBIter, newMBB);
7889 F->insert(MBBIter, nextMBB);
7891 // Move all successors of thisMBB to nextMBB
7892 nextMBB->transferSuccessors(thisMBB);
7894 // Update thisMBB to fall through to newMBB
7895 thisMBB->addSuccessor(newMBB);
7897 // newMBB jumps to newMBB and fall through to nextMBB
7898 newMBB->addSuccessor(nextMBB);
7899 newMBB->addSuccessor(newMBB);
7901 DebugLoc dl = mInstr->getDebugLoc();
7902 // Insert instructions into newMBB based on incoming instruction
7903 assert(mInstr->getNumOperands() < X86AddrNumOperands + 4 &&
7904 "unexpected number of operands");
7905 MachineOperand& destOper = mInstr->getOperand(0);
7906 MachineOperand* argOpers[2 + X86AddrNumOperands];
7907 int numArgs = mInstr->getNumOperands() - 1;
7908 for (int i=0; i < numArgs; ++i)
7909 argOpers[i] = &mInstr->getOperand(i+1);
7911 // x86 address has 4 operands: base, index, scale, and displacement
7912 int lastAddrIndx = X86AddrNumOperands - 1; // [0,3]
7913 int valArgIndx = lastAddrIndx + 1;
7915 unsigned t1 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
7916 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rm), t1);
7917 for (int i=0; i <= lastAddrIndx; ++i)
7918 (*MIB).addOperand(*argOpers[i]);
7920 // We only support register and immediate values
7921 assert((argOpers[valArgIndx]->isReg() ||
7922 argOpers[valArgIndx]->isImm()) &&
7925 unsigned t2 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
7926 if (argOpers[valArgIndx]->isReg())
7927 MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), t2);
7929 MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), t2);
7930 (*MIB).addOperand(*argOpers[valArgIndx]);
7932 MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), X86::EAX);
7935 MIB = BuildMI(newMBB, dl, TII->get(X86::CMP32rr));
7940 unsigned t3 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
7941 MIB = BuildMI(newMBB, dl, TII->get(cmovOpc),t3);
7945 // Cmp and exchange if none has modified the memory location
7946 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG32));
7947 for (int i=0; i <= lastAddrIndx; ++i)
7948 (*MIB).addOperand(*argOpers[i]);
7950 assert(mInstr->hasOneMemOperand() && "Unexpected number of memoperand");
7951 (*MIB).setMemRefs(mInstr->memoperands_begin(),
7952 mInstr->memoperands_end());
7954 MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), destOper.getReg());
7955 MIB.addReg(X86::EAX);
7958 BuildMI(newMBB, dl, TII->get(X86::JNE)).addMBB(newMBB);
7960 F->DeleteMachineInstr(mInstr); // The pseudo instruction is gone now.
7964 // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
7965 // all of this code can be replaced with that in the .td file.
7967 X86TargetLowering::EmitPCMP(MachineInstr *MI, MachineBasicBlock *BB,
7968 unsigned numArgs, bool memArg) const {
7970 MachineFunction *F = BB->getParent();
7971 DebugLoc dl = MI->getDebugLoc();
7972 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
7976 Opc = numArgs == 3 ? X86::PCMPISTRM128rm : X86::PCMPESTRM128rm;
7978 Opc = numArgs == 3 ? X86::PCMPISTRM128rr : X86::PCMPESTRM128rr;
7980 MachineInstrBuilder MIB = BuildMI(BB, dl, TII->get(Opc));
7982 for (unsigned i = 0; i < numArgs; ++i) {
7983 MachineOperand &Op = MI->getOperand(i+1);
7985 if (!(Op.isReg() && Op.isImplicit()))
7989 BuildMI(BB, dl, TII->get(X86::MOVAPSrr), MI->getOperand(0).getReg())
7992 F->DeleteMachineInstr(MI);
7998 X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
8000 MachineBasicBlock *MBB) const {
8001 // Emit code to save XMM registers to the stack. The ABI says that the
8002 // number of registers to save is given in %al, so it's theoretically
8003 // possible to do an indirect jump trick to avoid saving all of them,
8004 // however this code takes a simpler approach and just executes all
8005 // of the stores if %al is non-zero. It's less code, and it's probably
8006 // easier on the hardware branch predictor, and stores aren't all that
8007 // expensive anyway.
8009 // Create the new basic blocks. One block contains all the XMM stores,
8010 // and one block is the final destination regardless of whether any
8011 // stores were performed.
8012 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
8013 MachineFunction *F = MBB->getParent();
8014 MachineFunction::iterator MBBIter = MBB;
8016 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB);
8017 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB);
8018 F->insert(MBBIter, XMMSaveMBB);
8019 F->insert(MBBIter, EndMBB);
8022 // Move any original successors of MBB to the end block.
8023 EndMBB->transferSuccessors(MBB);
8024 // The original block will now fall through to the XMM save block.
8025 MBB->addSuccessor(XMMSaveMBB);
8026 // The XMMSaveMBB will fall through to the end block.
8027 XMMSaveMBB->addSuccessor(EndMBB);
8029 // Now add the instructions.
8030 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
8031 DebugLoc DL = MI->getDebugLoc();
8033 unsigned CountReg = MI->getOperand(0).getReg();
8034 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm();
8035 int64_t VarArgsFPOffset = MI->getOperand(2).getImm();
8037 if (!Subtarget->isTargetWin64()) {
8038 // If %al is 0, branch around the XMM save block.
8039 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
8040 BuildMI(MBB, DL, TII->get(X86::JE)).addMBB(EndMBB);
8041 MBB->addSuccessor(EndMBB);
8044 // In the XMM save block, save all the XMM argument registers.
8045 for (int i = 3, e = MI->getNumOperands(); i != e; ++i) {
8046 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
8047 MachineMemOperand *MMO =
8048 F->getMachineMemOperand(
8049 PseudoSourceValue::getFixedStack(RegSaveFrameIndex),
8050 MachineMemOperand::MOStore, Offset,
8051 /*Size=*/16, /*Align=*/16);
8052 BuildMI(XMMSaveMBB, DL, TII->get(X86::MOVAPSmr))
8053 .addFrameIndex(RegSaveFrameIndex)
8054 .addImm(/*Scale=*/1)
8055 .addReg(/*IndexReg=*/0)
8056 .addImm(/*Disp=*/Offset)
8057 .addReg(/*Segment=*/0)
8058 .addReg(MI->getOperand(i).getReg())
8059 .addMemOperand(MMO);
8062 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
8068 X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
8069 MachineBasicBlock *BB,
8070 DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) const {
8071 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
8072 DebugLoc DL = MI->getDebugLoc();
8074 // To "insert" a SELECT_CC instruction, we actually have to insert the
8075 // diamond control-flow pattern. The incoming instruction knows the
8076 // destination vreg to set, the condition code register to branch on, the
8077 // true/false values to select between, and a branch opcode to use.
8078 const BasicBlock *LLVM_BB = BB->getBasicBlock();
8079 MachineFunction::iterator It = BB;
8085 // cmpTY ccX, r1, r2
8087 // fallthrough --> copy0MBB
8088 MachineBasicBlock *thisMBB = BB;
8089 MachineFunction *F = BB->getParent();
8090 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
8091 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
8093 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
8094 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
8095 F->insert(It, copy0MBB);
8096 F->insert(It, sinkMBB);
8097 // Update machine-CFG edges by first adding all successors of the current
8098 // block to the new block which will contain the Phi node for the select.
8099 // Also inform sdisel of the edge changes.
8100 for (MachineBasicBlock::succ_iterator I = BB->succ_begin(),
8101 E = BB->succ_end(); I != E; ++I) {
8102 EM->insert(std::make_pair(*I, sinkMBB));
8103 sinkMBB->addSuccessor(*I);
8105 // Next, remove all successors of the current block, and add the true
8106 // and fallthrough blocks as its successors.
8107 while (!BB->succ_empty())
8108 BB->removeSuccessor(BB->succ_begin());
8109 // Add the true and fallthrough blocks as its successors.
8110 BB->addSuccessor(copy0MBB);
8111 BB->addSuccessor(sinkMBB);
8114 // %FalseValue = ...
8115 // # fallthrough to sinkMBB
8118 // Update machine-CFG edges
8119 BB->addSuccessor(sinkMBB);
8122 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
8125 BuildMI(BB, DL, TII->get(X86::PHI), MI->getOperand(0).getReg())
8126 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
8127 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
8129 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
8135 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
8136 MachineBasicBlock *BB,
8137 DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) const {
8138 switch (MI->getOpcode()) {
8139 default: assert(false && "Unexpected instr type to insert");
8141 case X86::CMOV_V1I64:
8142 case X86::CMOV_FR32:
8143 case X86::CMOV_FR64:
8144 case X86::CMOV_V4F32:
8145 case X86::CMOV_V2F64:
8146 case X86::CMOV_V2I64:
8147 return EmitLoweredSelect(MI, BB, EM);
8149 case X86::FP32_TO_INT16_IN_MEM:
8150 case X86::FP32_TO_INT32_IN_MEM:
8151 case X86::FP32_TO_INT64_IN_MEM:
8152 case X86::FP64_TO_INT16_IN_MEM:
8153 case X86::FP64_TO_INT32_IN_MEM:
8154 case X86::FP64_TO_INT64_IN_MEM:
8155 case X86::FP80_TO_INT16_IN_MEM:
8156 case X86::FP80_TO_INT32_IN_MEM:
8157 case X86::FP80_TO_INT64_IN_MEM: {
8158 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
8159 DebugLoc DL = MI->getDebugLoc();
8161 // Change the floating point control register to use "round towards zero"
8162 // mode when truncating to an integer value.
8163 MachineFunction *F = BB->getParent();
8164 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false);
8165 addFrameReference(BuildMI(BB, DL, TII->get(X86::FNSTCW16m)), CWFrameIdx);
8167 // Load the old value of the high byte of the control word...
8169 F->getRegInfo().createVirtualRegister(X86::GR16RegisterClass);
8170 addFrameReference(BuildMI(BB, DL, TII->get(X86::MOV16rm), OldCW),
8173 // Set the high part to be round to zero...
8174 addFrameReference(BuildMI(BB, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
8177 // Reload the modified control word now...
8178 addFrameReference(BuildMI(BB, DL, TII->get(X86::FLDCW16m)), CWFrameIdx);
8180 // Restore the memory image of control word to original value
8181 addFrameReference(BuildMI(BB, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
8184 // Get the X86 opcode to use.
8186 switch (MI->getOpcode()) {
8187 default: llvm_unreachable("illegal opcode!");
8188 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
8189 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
8190 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
8191 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
8192 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
8193 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
8194 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
8195 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
8196 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
8200 MachineOperand &Op = MI->getOperand(0);
8202 AM.BaseType = X86AddressMode::RegBase;
8203 AM.Base.Reg = Op.getReg();
8205 AM.BaseType = X86AddressMode::FrameIndexBase;
8206 AM.Base.FrameIndex = Op.getIndex();
8208 Op = MI->getOperand(1);
8210 AM.Scale = Op.getImm();
8211 Op = MI->getOperand(2);
8213 AM.IndexReg = Op.getImm();
8214 Op = MI->getOperand(3);
8215 if (Op.isGlobal()) {
8216 AM.GV = Op.getGlobal();
8218 AM.Disp = Op.getImm();
8220 addFullAddress(BuildMI(BB, DL, TII->get(Opc)), AM)
8221 .addReg(MI->getOperand(X86AddrNumOperands).getReg());
8223 // Reload the original control word now.
8224 addFrameReference(BuildMI(BB, DL, TII->get(X86::FLDCW16m)), CWFrameIdx);
8226 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
8229 // String/text processing lowering.
8230 case X86::PCMPISTRM128REG:
8231 return EmitPCMP(MI, BB, 3, false /* in-mem */);
8232 case X86::PCMPISTRM128MEM:
8233 return EmitPCMP(MI, BB, 3, true /* in-mem */);
8234 case X86::PCMPESTRM128REG:
8235 return EmitPCMP(MI, BB, 5, false /* in mem */);
8236 case X86::PCMPESTRM128MEM:
8237 return EmitPCMP(MI, BB, 5, true /* in mem */);
8240 case X86::ATOMAND32:
8241 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr,
8242 X86::AND32ri, X86::MOV32rm,
8243 X86::LCMPXCHG32, X86::MOV32rr,
8244 X86::NOT32r, X86::EAX,
8245 X86::GR32RegisterClass);
8247 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR32rr,
8248 X86::OR32ri, X86::MOV32rm,
8249 X86::LCMPXCHG32, X86::MOV32rr,
8250 X86::NOT32r, X86::EAX,
8251 X86::GR32RegisterClass);
8252 case X86::ATOMXOR32:
8253 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR32rr,
8254 X86::XOR32ri, X86::MOV32rm,
8255 X86::LCMPXCHG32, X86::MOV32rr,
8256 X86::NOT32r, X86::EAX,
8257 X86::GR32RegisterClass);
8258 case X86::ATOMNAND32:
8259 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr,
8260 X86::AND32ri, X86::MOV32rm,
8261 X86::LCMPXCHG32, X86::MOV32rr,
8262 X86::NOT32r, X86::EAX,
8263 X86::GR32RegisterClass, true);
8264 case X86::ATOMMIN32:
8265 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL32rr);
8266 case X86::ATOMMAX32:
8267 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG32rr);
8268 case X86::ATOMUMIN32:
8269 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB32rr);
8270 case X86::ATOMUMAX32:
8271 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA32rr);
8273 case X86::ATOMAND16:
8274 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr,
8275 X86::AND16ri, X86::MOV16rm,
8276 X86::LCMPXCHG16, X86::MOV16rr,
8277 X86::NOT16r, X86::AX,
8278 X86::GR16RegisterClass);
8280 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR16rr,
8281 X86::OR16ri, X86::MOV16rm,
8282 X86::LCMPXCHG16, X86::MOV16rr,
8283 X86::NOT16r, X86::AX,
8284 X86::GR16RegisterClass);
8285 case X86::ATOMXOR16:
8286 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR16rr,
8287 X86::XOR16ri, X86::MOV16rm,
8288 X86::LCMPXCHG16, X86::MOV16rr,
8289 X86::NOT16r, X86::AX,
8290 X86::GR16RegisterClass);
8291 case X86::ATOMNAND16:
8292 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr,
8293 X86::AND16ri, X86::MOV16rm,
8294 X86::LCMPXCHG16, X86::MOV16rr,
8295 X86::NOT16r, X86::AX,
8296 X86::GR16RegisterClass, true);
8297 case X86::ATOMMIN16:
8298 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL16rr);
8299 case X86::ATOMMAX16:
8300 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG16rr);
8301 case X86::ATOMUMIN16:
8302 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB16rr);
8303 case X86::ATOMUMAX16:
8304 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA16rr);
8307 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr,
8308 X86::AND8ri, X86::MOV8rm,
8309 X86::LCMPXCHG8, X86::MOV8rr,
8310 X86::NOT8r, X86::AL,
8311 X86::GR8RegisterClass);
8313 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR8rr,
8314 X86::OR8ri, X86::MOV8rm,
8315 X86::LCMPXCHG8, X86::MOV8rr,
8316 X86::NOT8r, X86::AL,
8317 X86::GR8RegisterClass);
8319 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR8rr,
8320 X86::XOR8ri, X86::MOV8rm,
8321 X86::LCMPXCHG8, X86::MOV8rr,
8322 X86::NOT8r, X86::AL,
8323 X86::GR8RegisterClass);
8324 case X86::ATOMNAND8:
8325 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr,
8326 X86::AND8ri, X86::MOV8rm,
8327 X86::LCMPXCHG8, X86::MOV8rr,
8328 X86::NOT8r, X86::AL,
8329 X86::GR8RegisterClass, true);
8330 // FIXME: There are no CMOV8 instructions; MIN/MAX need some other way.
8331 // This group is for 64-bit host.
8332 case X86::ATOMAND64:
8333 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr,
8334 X86::AND64ri32, X86::MOV64rm,
8335 X86::LCMPXCHG64, X86::MOV64rr,
8336 X86::NOT64r, X86::RAX,
8337 X86::GR64RegisterClass);
8339 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR64rr,
8340 X86::OR64ri32, X86::MOV64rm,
8341 X86::LCMPXCHG64, X86::MOV64rr,
8342 X86::NOT64r, X86::RAX,
8343 X86::GR64RegisterClass);
8344 case X86::ATOMXOR64:
8345 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR64rr,
8346 X86::XOR64ri32, X86::MOV64rm,
8347 X86::LCMPXCHG64, X86::MOV64rr,
8348 X86::NOT64r, X86::RAX,
8349 X86::GR64RegisterClass);
8350 case X86::ATOMNAND64:
8351 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr,
8352 X86::AND64ri32, X86::MOV64rm,
8353 X86::LCMPXCHG64, X86::MOV64rr,
8354 X86::NOT64r, X86::RAX,
8355 X86::GR64RegisterClass, true);
8356 case X86::ATOMMIN64:
8357 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL64rr);
8358 case X86::ATOMMAX64:
8359 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG64rr);
8360 case X86::ATOMUMIN64:
8361 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB64rr);
8362 case X86::ATOMUMAX64:
8363 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA64rr);
8365 // This group does 64-bit operations on a 32-bit host.
8366 case X86::ATOMAND6432:
8367 return EmitAtomicBit6432WithCustomInserter(MI, BB,
8368 X86::AND32rr, X86::AND32rr,
8369 X86::AND32ri, X86::AND32ri,
8371 case X86::ATOMOR6432:
8372 return EmitAtomicBit6432WithCustomInserter(MI, BB,
8373 X86::OR32rr, X86::OR32rr,
8374 X86::OR32ri, X86::OR32ri,
8376 case X86::ATOMXOR6432:
8377 return EmitAtomicBit6432WithCustomInserter(MI, BB,
8378 X86::XOR32rr, X86::XOR32rr,
8379 X86::XOR32ri, X86::XOR32ri,
8381 case X86::ATOMNAND6432:
8382 return EmitAtomicBit6432WithCustomInserter(MI, BB,
8383 X86::AND32rr, X86::AND32rr,
8384 X86::AND32ri, X86::AND32ri,
8386 case X86::ATOMADD6432:
8387 return EmitAtomicBit6432WithCustomInserter(MI, BB,
8388 X86::ADD32rr, X86::ADC32rr,
8389 X86::ADD32ri, X86::ADC32ri,
8391 case X86::ATOMSUB6432:
8392 return EmitAtomicBit6432WithCustomInserter(MI, BB,
8393 X86::SUB32rr, X86::SBB32rr,
8394 X86::SUB32ri, X86::SBB32ri,
8396 case X86::ATOMSWAP6432:
8397 return EmitAtomicBit6432WithCustomInserter(MI, BB,
8398 X86::MOV32rr, X86::MOV32rr,
8399 X86::MOV32ri, X86::MOV32ri,
8401 case X86::VASTART_SAVE_XMM_REGS:
8402 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
8406 //===----------------------------------------------------------------------===//
8407 // X86 Optimization Hooks
8408 //===----------------------------------------------------------------------===//
8410 void X86TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
8414 const SelectionDAG &DAG,
8415 unsigned Depth) const {
8416 unsigned Opc = Op.getOpcode();
8417 assert((Opc >= ISD::BUILTIN_OP_END ||
8418 Opc == ISD::INTRINSIC_WO_CHAIN ||
8419 Opc == ISD::INTRINSIC_W_CHAIN ||
8420 Opc == ISD::INTRINSIC_VOID) &&
8421 "Should use MaskedValueIsZero if you don't know whether Op"
8422 " is a target node!");
8424 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0); // Don't know anything.
8436 // These nodes' second result is a boolean.
8437 if (Op.getResNo() == 0)
8441 KnownZero |= APInt::getHighBitsSet(Mask.getBitWidth(),
8442 Mask.getBitWidth() - 1);
8447 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
8448 /// node is a GlobalAddress + offset.
8449 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
8450 GlobalValue* &GA, int64_t &Offset) const{
8451 if (N->getOpcode() == X86ISD::Wrapper) {
8452 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
8453 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
8454 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
8458 return TargetLowering::isGAPlusOffset(N, GA, Offset);
8461 static bool EltsFromConsecutiveLoads(ShuffleVectorSDNode *N, unsigned NumElems,
8462 EVT EltVT, LoadSDNode *&LDBase,
8463 unsigned &LastLoadedElt,
8464 SelectionDAG &DAG, MachineFrameInfo *MFI,
8465 const TargetLowering &TLI) {
8467 LastLoadedElt = -1U;
8468 for (unsigned i = 0; i < NumElems; ++i) {
8469 if (N->getMaskElt(i) < 0) {
8475 SDValue Elt = DAG.getShuffleScalarElt(N, i);
8476 if (!Elt.getNode() ||
8477 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
8480 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
8482 LDBase = cast<LoadSDNode>(Elt.getNode());
8486 if (Elt.getOpcode() == ISD::UNDEF)
8489 LoadSDNode *LD = cast<LoadSDNode>(Elt);
8490 if (!DAG.isConsecutiveLoad(LD, LDBase, EltVT.getSizeInBits()/8, i))
8497 /// PerformShuffleCombine - Combine a vector_shuffle that is equal to
8498 /// build_vector load1, load2, load3, load4, <0, 1, 2, 3> into a 128-bit load
8499 /// if the load addresses are consecutive, non-overlapping, and in the right
8500 /// order. In the case of v2i64, it will see if it can rewrite the
8501 /// shuffle to be an appropriate build vector so it can take advantage of
8502 // performBuildVectorCombine.
8503 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
8504 const TargetLowering &TLI) {
8505 DebugLoc dl = N->getDebugLoc();
8506 EVT VT = N->getValueType(0);
8507 EVT EltVT = VT.getVectorElementType();
8508 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(N);
8509 unsigned NumElems = VT.getVectorNumElements();
8511 if (VT.getSizeInBits() != 128)
8514 // Try to combine a vector_shuffle into a 128-bit load.
8515 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
8516 LoadSDNode *LD = NULL;
8517 unsigned LastLoadedElt;
8518 if (!EltsFromConsecutiveLoads(SVN, NumElems, EltVT, LD, LastLoadedElt, DAG,
8522 if (LastLoadedElt == NumElems - 1) {
8523 if (DAG.InferPtrAlignment(LD->getBasePtr()) >= 16)
8524 return DAG.getLoad(VT, dl, LD->getChain(), LD->getBasePtr(),
8525 LD->getSrcValue(), LD->getSrcValueOffset(),
8527 return DAG.getLoad(VT, dl, LD->getChain(), LD->getBasePtr(),
8528 LD->getSrcValue(), LD->getSrcValueOffset(),
8529 LD->isVolatile(), LD->getAlignment());
8530 } else if (NumElems == 4 && LastLoadedElt == 1) {
8531 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
8532 SDValue Ops[] = { LD->getChain(), LD->getBasePtr() };
8533 SDValue ResNode = DAG.getNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops, 2);
8534 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, ResNode);
8539 /// PerformSELECTCombine - Do target-specific dag combines on SELECT nodes.
8540 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
8541 const X86Subtarget *Subtarget) {
8542 DebugLoc DL = N->getDebugLoc();
8543 SDValue Cond = N->getOperand(0);
8544 // Get the LHS/RHS of the select.
8545 SDValue LHS = N->getOperand(1);
8546 SDValue RHS = N->getOperand(2);
8548 // If we have SSE[12] support, try to form min/max nodes. SSE min/max
8549 // instructions have the peculiarity that if either operand is a NaN,
8550 // they chose what we call the RHS operand (and as such are not symmetric).
8551 // It happens that this matches the semantics of the common C idiom
8552 // x<y?x:y and related forms, so we can recognize these cases.
8553 if (Subtarget->hasSSE2() &&
8554 (LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64) &&
8555 Cond.getOpcode() == ISD::SETCC) {
8556 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
8558 unsigned Opcode = 0;
8559 // Check for x CC y ? x : y.
8560 if (LHS == Cond.getOperand(0) && RHS == Cond.getOperand(1)) {
8564 // This can be a min if we can prove that at least one of the operands
8566 if (!FiniteOnlyFPMath()) {
8567 if (DAG.isKnownNeverNaN(RHS)) {
8568 // Put the potential NaN in the RHS so that SSE will preserve it.
8569 std::swap(LHS, RHS);
8570 } else if (!DAG.isKnownNeverNaN(LHS))
8573 Opcode = X86ISD::FMIN;
8576 // This can be a min if we can prove that at least one of the operands
8578 if (!FiniteOnlyFPMath()) {
8579 if (DAG.isKnownNeverNaN(LHS)) {
8580 // Put the potential NaN in the RHS so that SSE will preserve it.
8581 std::swap(LHS, RHS);
8582 } else if (!DAG.isKnownNeverNaN(RHS))
8585 Opcode = X86ISD::FMIN;
8588 // This can be a min, but if either operand is a NaN we need it to
8589 // preserve the original LHS.
8590 std::swap(LHS, RHS);
8594 Opcode = X86ISD::FMIN;
8598 // This can be a max if we can prove that at least one of the operands
8600 if (!FiniteOnlyFPMath()) {
8601 if (DAG.isKnownNeverNaN(LHS)) {
8602 // Put the potential NaN in the RHS so that SSE will preserve it.
8603 std::swap(LHS, RHS);
8604 } else if (!DAG.isKnownNeverNaN(RHS))
8607 Opcode = X86ISD::FMAX;
8610 // This can be a max if we can prove that at least one of the operands
8612 if (!FiniteOnlyFPMath()) {
8613 if (DAG.isKnownNeverNaN(RHS)) {
8614 // Put the potential NaN in the RHS so that SSE will preserve it.
8615 std::swap(LHS, RHS);
8616 } else if (!DAG.isKnownNeverNaN(LHS))
8619 Opcode = X86ISD::FMAX;
8622 // This can be a max, but if either operand is a NaN we need it to
8623 // preserve the original LHS.
8624 std::swap(LHS, RHS);
8628 Opcode = X86ISD::FMAX;
8631 // Check for x CC y ? y : x -- a min/max with reversed arms.
8632 } else if (LHS == Cond.getOperand(1) && RHS == Cond.getOperand(0)) {
8636 // This can be a min if we can prove that at least one of the operands
8638 if (!FiniteOnlyFPMath()) {
8639 if (DAG.isKnownNeverNaN(RHS)) {
8640 // Put the potential NaN in the RHS so that SSE will preserve it.
8641 std::swap(LHS, RHS);
8642 } else if (!DAG.isKnownNeverNaN(LHS))
8645 Opcode = X86ISD::FMIN;
8648 // This can be a min if we can prove that at least one of the operands
8650 if (!FiniteOnlyFPMath()) {
8651 if (DAG.isKnownNeverNaN(LHS)) {
8652 // Put the potential NaN in the RHS so that SSE will preserve it.
8653 std::swap(LHS, RHS);
8654 } else if (!DAG.isKnownNeverNaN(RHS))
8657 Opcode = X86ISD::FMIN;
8660 // This can be a min, but if either operand is a NaN we need it to
8661 // preserve the original LHS.
8662 std::swap(LHS, RHS);
8666 Opcode = X86ISD::FMIN;
8670 // This can be a max if we can prove that at least one of the operands
8672 if (!FiniteOnlyFPMath()) {
8673 if (DAG.isKnownNeverNaN(LHS)) {
8674 // Put the potential NaN in the RHS so that SSE will preserve it.
8675 std::swap(LHS, RHS);
8676 } else if (!DAG.isKnownNeverNaN(RHS))
8679 Opcode = X86ISD::FMAX;
8682 // This can be a max if we can prove that at least one of the operands
8684 if (!FiniteOnlyFPMath()) {
8685 if (DAG.isKnownNeverNaN(RHS)) {
8686 // Put the potential NaN in the RHS so that SSE will preserve it.
8687 std::swap(LHS, RHS);
8688 } else if (!DAG.isKnownNeverNaN(LHS))
8691 Opcode = X86ISD::FMAX;
8694 // This can be a max, but if either operand is a NaN we need it to
8695 // preserve the original LHS.
8696 std::swap(LHS, RHS);
8700 Opcode = X86ISD::FMAX;
8706 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
8709 // If this is a select between two integer constants, try to do some
8711 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
8712 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
8713 // Don't do this for crazy integer types.
8714 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
8715 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
8716 // so that TrueC (the true value) is larger than FalseC.
8717 bool NeedsCondInvert = false;
8719 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
8720 // Efficiently invertible.
8721 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
8722 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
8723 isa<ConstantSDNode>(Cond.getOperand(1))))) {
8724 NeedsCondInvert = true;
8725 std::swap(TrueC, FalseC);
8728 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
8729 if (FalseC->getAPIntValue() == 0 &&
8730 TrueC->getAPIntValue().isPowerOf2()) {
8731 if (NeedsCondInvert) // Invert the condition if needed.
8732 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
8733 DAG.getConstant(1, Cond.getValueType()));
8735 // Zero extend the condition if needed.
8736 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
8738 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
8739 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
8740 DAG.getConstant(ShAmt, MVT::i8));
8743 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
8744 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
8745 if (NeedsCondInvert) // Invert the condition if needed.
8746 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
8747 DAG.getConstant(1, Cond.getValueType()));
8749 // Zero extend the condition if needed.
8750 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
8751 FalseC->getValueType(0), Cond);
8752 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
8753 SDValue(FalseC, 0));
8756 // Optimize cases that will turn into an LEA instruction. This requires
8757 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
8758 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
8759 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
8760 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
8762 bool isFastMultiplier = false;
8764 switch ((unsigned char)Diff) {
8766 case 1: // result = add base, cond
8767 case 2: // result = lea base( , cond*2)
8768 case 3: // result = lea base(cond, cond*2)
8769 case 4: // result = lea base( , cond*4)
8770 case 5: // result = lea base(cond, cond*4)
8771 case 8: // result = lea base( , cond*8)
8772 case 9: // result = lea base(cond, cond*8)
8773 isFastMultiplier = true;
8778 if (isFastMultiplier) {
8779 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
8780 if (NeedsCondInvert) // Invert the condition if needed.
8781 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
8782 DAG.getConstant(1, Cond.getValueType()));
8784 // Zero extend the condition if needed.
8785 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
8787 // Scale the condition by the difference.
8789 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
8790 DAG.getConstant(Diff, Cond.getValueType()));
8792 // Add the base if non-zero.
8793 if (FalseC->getAPIntValue() != 0)
8794 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
8795 SDValue(FalseC, 0));
8805 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
8806 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
8807 TargetLowering::DAGCombinerInfo &DCI) {
8808 DebugLoc DL = N->getDebugLoc();
8810 // If the flag operand isn't dead, don't touch this CMOV.
8811 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
8814 // If this is a select between two integer constants, try to do some
8815 // optimizations. Note that the operands are ordered the opposite of SELECT
8817 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(N->getOperand(1))) {
8818 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
8819 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
8820 // larger than FalseC (the false value).
8821 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
8823 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
8824 CC = X86::GetOppositeBranchCondition(CC);
8825 std::swap(TrueC, FalseC);
8828 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
8829 // This is efficient for any integer data type (including i8/i16) and
8831 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
8832 SDValue Cond = N->getOperand(3);
8833 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
8834 DAG.getConstant(CC, MVT::i8), Cond);
8836 // Zero extend the condition if needed.
8837 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
8839 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
8840 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
8841 DAG.getConstant(ShAmt, MVT::i8));
8842 if (N->getNumValues() == 2) // Dead flag value?
8843 return DCI.CombineTo(N, Cond, SDValue());
8847 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
8848 // for any integer data type, including i8/i16.
8849 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
8850 SDValue Cond = N->getOperand(3);
8851 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
8852 DAG.getConstant(CC, MVT::i8), Cond);
8854 // Zero extend the condition if needed.
8855 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
8856 FalseC->getValueType(0), Cond);
8857 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
8858 SDValue(FalseC, 0));
8860 if (N->getNumValues() == 2) // Dead flag value?
8861 return DCI.CombineTo(N, Cond, SDValue());
8865 // Optimize cases that will turn into an LEA instruction. This requires
8866 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
8867 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
8868 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
8869 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
8871 bool isFastMultiplier = false;
8873 switch ((unsigned char)Diff) {
8875 case 1: // result = add base, cond
8876 case 2: // result = lea base( , cond*2)
8877 case 3: // result = lea base(cond, cond*2)
8878 case 4: // result = lea base( , cond*4)
8879 case 5: // result = lea base(cond, cond*4)
8880 case 8: // result = lea base( , cond*8)
8881 case 9: // result = lea base(cond, cond*8)
8882 isFastMultiplier = true;
8887 if (isFastMultiplier) {
8888 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
8889 SDValue Cond = N->getOperand(3);
8890 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
8891 DAG.getConstant(CC, MVT::i8), Cond);
8892 // Zero extend the condition if needed.
8893 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
8895 // Scale the condition by the difference.
8897 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
8898 DAG.getConstant(Diff, Cond.getValueType()));
8900 // Add the base if non-zero.
8901 if (FalseC->getAPIntValue() != 0)
8902 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
8903 SDValue(FalseC, 0));
8904 if (N->getNumValues() == 2) // Dead flag value?
8905 return DCI.CombineTo(N, Cond, SDValue());
8915 /// PerformMulCombine - Optimize a single multiply with constant into two
8916 /// in order to implement it with two cheaper instructions, e.g.
8917 /// LEA + SHL, LEA + LEA.
8918 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
8919 TargetLowering::DAGCombinerInfo &DCI) {
8920 if (DAG.getMachineFunction().
8921 getFunction()->hasFnAttr(Attribute::OptimizeForSize))
8924 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
8927 EVT VT = N->getValueType(0);
8931 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
8934 uint64_t MulAmt = C->getZExtValue();
8935 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
8938 uint64_t MulAmt1 = 0;
8939 uint64_t MulAmt2 = 0;
8940 if ((MulAmt % 9) == 0) {
8942 MulAmt2 = MulAmt / 9;
8943 } else if ((MulAmt % 5) == 0) {
8945 MulAmt2 = MulAmt / 5;
8946 } else if ((MulAmt % 3) == 0) {
8948 MulAmt2 = MulAmt / 3;
8951 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
8952 DebugLoc DL = N->getDebugLoc();
8954 if (isPowerOf2_64(MulAmt2) &&
8955 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
8956 // If second multiplifer is pow2, issue it first. We want the multiply by
8957 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
8959 std::swap(MulAmt1, MulAmt2);
8962 if (isPowerOf2_64(MulAmt1))
8963 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
8964 DAG.getConstant(Log2_64(MulAmt1), MVT::i8));
8966 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
8967 DAG.getConstant(MulAmt1, VT));
8969 if (isPowerOf2_64(MulAmt2))
8970 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
8971 DAG.getConstant(Log2_64(MulAmt2), MVT::i8));
8973 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
8974 DAG.getConstant(MulAmt2, VT));
8976 // Do not add new nodes to DAG combiner worklist.
8977 DCI.CombineTo(N, NewMul, false);
8982 static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) {
8983 SDValue N0 = N->getOperand(0);
8984 SDValue N1 = N->getOperand(1);
8985 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
8986 EVT VT = N0.getValueType();
8988 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2))
8989 // since the result of setcc_c is all zero's or all ones.
8990 if (N1C && N0.getOpcode() == ISD::AND &&
8991 N0.getOperand(1).getOpcode() == ISD::Constant) {
8992 SDValue N00 = N0.getOperand(0);
8993 if (N00.getOpcode() == X86ISD::SETCC_CARRY ||
8994 ((N00.getOpcode() == ISD::ANY_EXTEND ||
8995 N00.getOpcode() == ISD::ZERO_EXTEND) &&
8996 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY)) {
8997 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
8998 APInt ShAmt = N1C->getAPIntValue();
8999 Mask = Mask.shl(ShAmt);
9001 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
9002 N00, DAG.getConstant(Mask, VT));
9009 /// PerformShiftCombine - Transforms vector shift nodes to use vector shifts
9011 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
9012 const X86Subtarget *Subtarget) {
9013 EVT VT = N->getValueType(0);
9014 if (!VT.isVector() && VT.isInteger() &&
9015 N->getOpcode() == ISD::SHL)
9016 return PerformSHLCombine(N, DAG);
9018 // On X86 with SSE2 support, we can transform this to a vector shift if
9019 // all elements are shifted by the same amount. We can't do this in legalize
9020 // because the a constant vector is typically transformed to a constant pool
9021 // so we have no knowledge of the shift amount.
9022 if (!Subtarget->hasSSE2())
9025 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16)
9028 SDValue ShAmtOp = N->getOperand(1);
9029 EVT EltVT = VT.getVectorElementType();
9030 DebugLoc DL = N->getDebugLoc();
9031 SDValue BaseShAmt = SDValue();
9032 if (ShAmtOp.getOpcode() == ISD::BUILD_VECTOR) {
9033 unsigned NumElts = VT.getVectorNumElements();
9035 for (; i != NumElts; ++i) {
9036 SDValue Arg = ShAmtOp.getOperand(i);
9037 if (Arg.getOpcode() == ISD::UNDEF) continue;
9041 for (; i != NumElts; ++i) {
9042 SDValue Arg = ShAmtOp.getOperand(i);
9043 if (Arg.getOpcode() == ISD::UNDEF) continue;
9044 if (Arg != BaseShAmt) {
9048 } else if (ShAmtOp.getOpcode() == ISD::VECTOR_SHUFFLE &&
9049 cast<ShuffleVectorSDNode>(ShAmtOp)->isSplat()) {
9050 SDValue InVec = ShAmtOp.getOperand(0);
9051 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
9052 unsigned NumElts = InVec.getValueType().getVectorNumElements();
9054 for (; i != NumElts; ++i) {
9055 SDValue Arg = InVec.getOperand(i);
9056 if (Arg.getOpcode() == ISD::UNDEF) continue;
9060 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
9061 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
9062 unsigned SplatIdx = cast<ShuffleVectorSDNode>(ShAmtOp)->getSplatIndex();
9063 if (C->getZExtValue() == SplatIdx)
9064 BaseShAmt = InVec.getOperand(1);
9067 if (BaseShAmt.getNode() == 0)
9068 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, ShAmtOp,
9069 DAG.getIntPtrConstant(0));
9073 // The shift amount is an i32.
9074 if (EltVT.bitsGT(MVT::i32))
9075 BaseShAmt = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, BaseShAmt);
9076 else if (EltVT.bitsLT(MVT::i32))
9077 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, BaseShAmt);
9079 // The shift amount is identical so we can do a vector shift.
9080 SDValue ValOp = N->getOperand(0);
9081 switch (N->getOpcode()) {
9083 llvm_unreachable("Unknown shift opcode!");
9086 if (VT == MVT::v2i64)
9087 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
9088 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32),
9090 if (VT == MVT::v4i32)
9091 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
9092 DAG.getConstant(Intrinsic::x86_sse2_pslli_d, MVT::i32),
9094 if (VT == MVT::v8i16)
9095 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
9096 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32),
9100 if (VT == MVT::v4i32)
9101 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
9102 DAG.getConstant(Intrinsic::x86_sse2_psrai_d, MVT::i32),
9104 if (VT == MVT::v8i16)
9105 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
9106 DAG.getConstant(Intrinsic::x86_sse2_psrai_w, MVT::i32),
9110 if (VT == MVT::v2i64)
9111 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
9112 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32),
9114 if (VT == MVT::v4i32)
9115 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
9116 DAG.getConstant(Intrinsic::x86_sse2_psrli_d, MVT::i32),
9118 if (VT == MVT::v8i16)
9119 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
9120 DAG.getConstant(Intrinsic::x86_sse2_psrli_w, MVT::i32),
9127 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
9128 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
9129 const X86Subtarget *Subtarget) {
9130 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
9131 // the FP state in cases where an emms may be missing.
9132 // A preferable solution to the general problem is to figure out the right
9133 // places to insert EMMS. This qualifies as a quick hack.
9135 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
9136 StoreSDNode *St = cast<StoreSDNode>(N);
9137 EVT VT = St->getValue().getValueType();
9138 if (VT.getSizeInBits() != 64)
9141 const Function *F = DAG.getMachineFunction().getFunction();
9142 bool NoImplicitFloatOps = F->hasFnAttr(Attribute::NoImplicitFloat);
9143 bool F64IsLegal = !UseSoftFloat && !NoImplicitFloatOps
9144 && Subtarget->hasSSE2();
9145 if ((VT.isVector() ||
9146 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
9147 isa<LoadSDNode>(St->getValue()) &&
9148 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
9149 St->getChain().hasOneUse() && !St->isVolatile()) {
9150 SDNode* LdVal = St->getValue().getNode();
9152 int TokenFactorIndex = -1;
9153 SmallVector<SDValue, 8> Ops;
9154 SDNode* ChainVal = St->getChain().getNode();
9155 // Must be a store of a load. We currently handle two cases: the load
9156 // is a direct child, and it's under an intervening TokenFactor. It is
9157 // possible to dig deeper under nested TokenFactors.
9158 if (ChainVal == LdVal)
9159 Ld = cast<LoadSDNode>(St->getChain());
9160 else if (St->getValue().hasOneUse() &&
9161 ChainVal->getOpcode() == ISD::TokenFactor) {
9162 for (unsigned i=0, e = ChainVal->getNumOperands(); i != e; ++i) {
9163 if (ChainVal->getOperand(i).getNode() == LdVal) {
9164 TokenFactorIndex = i;
9165 Ld = cast<LoadSDNode>(St->getValue());
9167 Ops.push_back(ChainVal->getOperand(i));
9171 if (!Ld || !ISD::isNormalLoad(Ld))
9174 // If this is not the MMX case, i.e. we are just turning i64 load/store
9175 // into f64 load/store, avoid the transformation if there are multiple
9176 // uses of the loaded value.
9177 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
9180 DebugLoc LdDL = Ld->getDebugLoc();
9181 DebugLoc StDL = N->getDebugLoc();
9182 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
9183 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
9185 if (Subtarget->is64Bit() || F64IsLegal) {
9186 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
9187 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(),
9188 Ld->getBasePtr(), Ld->getSrcValue(),
9189 Ld->getSrcValueOffset(), Ld->isVolatile(),
9190 Ld->getAlignment());
9191 SDValue NewChain = NewLd.getValue(1);
9192 if (TokenFactorIndex != -1) {
9193 Ops.push_back(NewChain);
9194 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
9197 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
9198 St->getSrcValue(), St->getSrcValueOffset(),
9199 St->isVolatile(), St->getAlignment());
9202 // Otherwise, lower to two pairs of 32-bit loads / stores.
9203 SDValue LoAddr = Ld->getBasePtr();
9204 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
9205 DAG.getConstant(4, MVT::i32));
9207 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
9208 Ld->getSrcValue(), Ld->getSrcValueOffset(),
9209 Ld->isVolatile(), Ld->getAlignment());
9210 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
9211 Ld->getSrcValue(), Ld->getSrcValueOffset()+4,
9213 MinAlign(Ld->getAlignment(), 4));
9215 SDValue NewChain = LoLd.getValue(1);
9216 if (TokenFactorIndex != -1) {
9217 Ops.push_back(LoLd);
9218 Ops.push_back(HiLd);
9219 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
9223 LoAddr = St->getBasePtr();
9224 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
9225 DAG.getConstant(4, MVT::i32));
9227 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
9228 St->getSrcValue(), St->getSrcValueOffset(),
9229 St->isVolatile(), St->getAlignment());
9230 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
9232 St->getSrcValueOffset() + 4,
9234 MinAlign(St->getAlignment(), 4));
9235 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
9240 /// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and
9241 /// X86ISD::FXOR nodes.
9242 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
9243 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
9244 // F[X]OR(0.0, x) -> x
9245 // F[X]OR(x, 0.0) -> x
9246 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
9247 if (C->getValueAPF().isPosZero())
9248 return N->getOperand(1);
9249 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
9250 if (C->getValueAPF().isPosZero())
9251 return N->getOperand(0);
9255 /// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes.
9256 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
9257 // FAND(0.0, x) -> 0.0
9258 // FAND(x, 0.0) -> 0.0
9259 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
9260 if (C->getValueAPF().isPosZero())
9261 return N->getOperand(0);
9262 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
9263 if (C->getValueAPF().isPosZero())
9264 return N->getOperand(1);
9268 static SDValue PerformBTCombine(SDNode *N,
9270 TargetLowering::DAGCombinerInfo &DCI) {
9271 // BT ignores high bits in the bit index operand.
9272 SDValue Op1 = N->getOperand(1);
9273 if (Op1.hasOneUse()) {
9274 unsigned BitWidth = Op1.getValueSizeInBits();
9275 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
9276 APInt KnownZero, KnownOne;
9277 TargetLowering::TargetLoweringOpt TLO(DAG);
9278 TargetLowering &TLI = DAG.getTargetLoweringInfo();
9279 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
9280 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
9281 DCI.CommitTargetLoweringOpt(TLO);
9286 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
9287 SDValue Op = N->getOperand(0);
9288 if (Op.getOpcode() == ISD::BIT_CONVERT)
9289 Op = Op.getOperand(0);
9290 EVT VT = N->getValueType(0), OpVT = Op.getValueType();
9291 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
9292 VT.getVectorElementType().getSizeInBits() ==
9293 OpVT.getVectorElementType().getSizeInBits()) {
9294 return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(), VT, Op);
9299 // On X86 and X86-64, atomic operations are lowered to locked instructions.
9300 // Locked instructions, in turn, have implicit fence semantics (all memory
9301 // operations are flushed before issuing the locked instruction, and the
9302 // are not buffered), so we can fold away the common pattern of
9303 // fence-atomic-fence.
9304 static SDValue PerformMEMBARRIERCombine(SDNode* N, SelectionDAG &DAG) {
9305 SDValue atomic = N->getOperand(0);
9306 switch (atomic.getOpcode()) {
9307 case ISD::ATOMIC_CMP_SWAP:
9308 case ISD::ATOMIC_SWAP:
9309 case ISD::ATOMIC_LOAD_ADD:
9310 case ISD::ATOMIC_LOAD_SUB:
9311 case ISD::ATOMIC_LOAD_AND:
9312 case ISD::ATOMIC_LOAD_OR:
9313 case ISD::ATOMIC_LOAD_XOR:
9314 case ISD::ATOMIC_LOAD_NAND:
9315 case ISD::ATOMIC_LOAD_MIN:
9316 case ISD::ATOMIC_LOAD_MAX:
9317 case ISD::ATOMIC_LOAD_UMIN:
9318 case ISD::ATOMIC_LOAD_UMAX:
9324 SDValue fence = atomic.getOperand(0);
9325 if (fence.getOpcode() != ISD::MEMBARRIER)
9328 switch (atomic.getOpcode()) {
9329 case ISD::ATOMIC_CMP_SWAP:
9330 return DAG.UpdateNodeOperands(atomic, fence.getOperand(0),
9331 atomic.getOperand(1), atomic.getOperand(2),
9332 atomic.getOperand(3));
9333 case ISD::ATOMIC_SWAP:
9334 case ISD::ATOMIC_LOAD_ADD:
9335 case ISD::ATOMIC_LOAD_SUB:
9336 case ISD::ATOMIC_LOAD_AND:
9337 case ISD::ATOMIC_LOAD_OR:
9338 case ISD::ATOMIC_LOAD_XOR:
9339 case ISD::ATOMIC_LOAD_NAND:
9340 case ISD::ATOMIC_LOAD_MIN:
9341 case ISD::ATOMIC_LOAD_MAX:
9342 case ISD::ATOMIC_LOAD_UMIN:
9343 case ISD::ATOMIC_LOAD_UMAX:
9344 return DAG.UpdateNodeOperands(atomic, fence.getOperand(0),
9345 atomic.getOperand(1), atomic.getOperand(2));
9351 static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG) {
9352 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) ->
9353 // (and (i32 x86isd::setcc_carry), 1)
9354 // This eliminates the zext. This transformation is necessary because
9355 // ISD::SETCC is always legalized to i8.
9356 DebugLoc dl = N->getDebugLoc();
9357 SDValue N0 = N->getOperand(0);
9358 EVT VT = N->getValueType(0);
9359 if (N0.getOpcode() == ISD::AND &&
9361 N0.getOperand(0).hasOneUse()) {
9362 SDValue N00 = N0.getOperand(0);
9363 if (N00.getOpcode() != X86ISD::SETCC_CARRY)
9365 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
9366 if (!C || C->getZExtValue() != 1)
9368 return DAG.getNode(ISD::AND, dl, VT,
9369 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
9370 N00.getOperand(0), N00.getOperand(1)),
9371 DAG.getConstant(1, VT));
9377 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
9378 DAGCombinerInfo &DCI) const {
9379 SelectionDAG &DAG = DCI.DAG;
9380 switch (N->getOpcode()) {
9382 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, *this);
9383 case ISD::SELECT: return PerformSELECTCombine(N, DAG, Subtarget);
9384 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI);
9385 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
9388 case ISD::SRL: return PerformShiftCombine(N, DAG, Subtarget);
9389 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
9391 case X86ISD::FOR: return PerformFORCombine(N, DAG);
9392 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
9393 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
9394 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
9395 case ISD::MEMBARRIER: return PerformMEMBARRIERCombine(N, DAG);
9396 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG);
9402 //===----------------------------------------------------------------------===//
9403 // X86 Inline Assembly Support
9404 //===----------------------------------------------------------------------===//
9406 static bool LowerToBSwap(CallInst *CI) {
9407 // FIXME: this should verify that we are targetting a 486 or better. If not,
9408 // we will turn this bswap into something that will be lowered to logical ops
9409 // instead of emitting the bswap asm. For now, we don't support 486 or lower
9410 // so don't worry about this.
9412 // Verify this is a simple bswap.
9413 if (CI->getNumOperands() != 2 ||
9414 CI->getType() != CI->getOperand(1)->getType() ||
9415 !CI->getType()->isInteger())
9418 const IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
9419 if (!Ty || Ty->getBitWidth() % 16 != 0)
9422 // Okay, we can do this xform, do so now.
9423 const Type *Tys[] = { Ty };
9424 Module *M = CI->getParent()->getParent()->getParent();
9425 Constant *Int = Intrinsic::getDeclaration(M, Intrinsic::bswap, Tys, 1);
9427 Value *Op = CI->getOperand(1);
9428 Op = CallInst::Create(Int, Op, CI->getName(), CI);
9430 CI->replaceAllUsesWith(Op);
9431 CI->eraseFromParent();
9435 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
9436 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
9437 std::vector<InlineAsm::ConstraintInfo> Constraints = IA->ParseConstraints();
9439 std::string AsmStr = IA->getAsmString();
9441 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
9442 std::vector<std::string> AsmPieces;
9443 SplitString(AsmStr, AsmPieces, "\n"); // ; as separator?
9445 switch (AsmPieces.size()) {
9446 default: return false;
9448 AsmStr = AsmPieces[0];
9450 SplitString(AsmStr, AsmPieces, " \t"); // Split with whitespace.
9453 if (AsmPieces.size() == 2 &&
9454 (AsmPieces[0] == "bswap" ||
9455 AsmPieces[0] == "bswapq" ||
9456 AsmPieces[0] == "bswapl") &&
9457 (AsmPieces[1] == "$0" ||
9458 AsmPieces[1] == "${0:q}")) {
9459 // No need to check constraints, nothing other than the equivalent of
9460 // "=r,0" would be valid here.
9461 return LowerToBSwap(CI);
9463 // rorw $$8, ${0:w} --> llvm.bswap.i16
9464 if (CI->getType() == Type::getInt16Ty(CI->getContext()) &&
9465 AsmPieces.size() == 3 &&
9466 AsmPieces[0] == "rorw" &&
9467 AsmPieces[1] == "$$8," &&
9468 AsmPieces[2] == "${0:w}" &&
9469 IA->getConstraintString() == "=r,0,~{dirflag},~{fpsr},~{flags},~{cc}") {
9470 return LowerToBSwap(CI);
9474 if (CI->getType() == Type::getInt64Ty(CI->getContext()) &&
9475 Constraints.size() >= 2 &&
9476 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
9477 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
9478 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
9479 std::vector<std::string> Words;
9480 SplitString(AsmPieces[0], Words, " \t");
9481 if (Words.size() == 2 && Words[0] == "bswap" && Words[1] == "%eax") {
9483 SplitString(AsmPieces[1], Words, " \t");
9484 if (Words.size() == 2 && Words[0] == "bswap" && Words[1] == "%edx") {
9486 SplitString(AsmPieces[2], Words, " \t,");
9487 if (Words.size() == 3 && Words[0] == "xchgl" && Words[1] == "%eax" &&
9488 Words[2] == "%edx") {
9489 return LowerToBSwap(CI);
9501 /// getConstraintType - Given a constraint letter, return the type of
9502 /// constraint it is for this target.
9503 X86TargetLowering::ConstraintType
9504 X86TargetLowering::getConstraintType(const std::string &Constraint) const {
9505 if (Constraint.size() == 1) {
9506 switch (Constraint[0]) {
9518 return C_RegisterClass;
9526 return TargetLowering::getConstraintType(Constraint);
9529 /// LowerXConstraint - try to replace an X constraint, which matches anything,
9530 /// with another that has more specific requirements based on the type of the
9531 /// corresponding operand.
9532 const char *X86TargetLowering::
9533 LowerXConstraint(EVT ConstraintVT) const {
9534 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
9535 // 'f' like normal targets.
9536 if (ConstraintVT.isFloatingPoint()) {
9537 if (Subtarget->hasSSE2())
9539 if (Subtarget->hasSSE1())
9543 return TargetLowering::LowerXConstraint(ConstraintVT);
9546 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
9547 /// vector. If it is invalid, don't add anything to Ops.
9548 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
9551 std::vector<SDValue>&Ops,
9552 SelectionDAG &DAG) const {
9553 SDValue Result(0, 0);
9555 switch (Constraint) {
9558 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
9559 if (C->getZExtValue() <= 31) {
9560 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
9566 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
9567 if (C->getZExtValue() <= 63) {
9568 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
9574 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
9575 if ((int8_t)C->getSExtValue() == C->getSExtValue()) {
9576 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
9582 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
9583 if (C->getZExtValue() <= 255) {
9584 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
9590 // 32-bit signed value
9591 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
9592 const ConstantInt *CI = C->getConstantIntValue();
9593 if (CI->isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
9594 C->getSExtValue())) {
9595 // Widen to 64 bits here to get it sign extended.
9596 Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64);
9599 // FIXME gcc accepts some relocatable values here too, but only in certain
9600 // memory models; it's complicated.
9605 // 32-bit unsigned value
9606 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
9607 const ConstantInt *CI = C->getConstantIntValue();
9608 if (CI->isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
9609 C->getZExtValue())) {
9610 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
9614 // FIXME gcc accepts some relocatable values here too, but only in certain
9615 // memory models; it's complicated.
9619 // Literal immediates are always ok.
9620 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
9621 // Widen to 64 bits here to get it sign extended.
9622 Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64);
9626 // If we are in non-pic codegen mode, we allow the address of a global (with
9627 // an optional displacement) to be used with 'i'.
9628 GlobalAddressSDNode *GA = 0;
9631 // Match either (GA), (GA+C), (GA+C1+C2), etc.
9633 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
9634 Offset += GA->getOffset();
9636 } else if (Op.getOpcode() == ISD::ADD) {
9637 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
9638 Offset += C->getZExtValue();
9639 Op = Op.getOperand(0);
9642 } else if (Op.getOpcode() == ISD::SUB) {
9643 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
9644 Offset += -C->getZExtValue();
9645 Op = Op.getOperand(0);
9650 // Otherwise, this isn't something we can handle, reject it.
9654 GlobalValue *GV = GA->getGlobal();
9655 // If we require an extra load to get this address, as in PIC mode, we
9657 if (isGlobalStubReference(Subtarget->ClassifyGlobalReference(GV,
9658 getTargetMachine())))
9662 Op = LowerGlobalAddress(GV, Op.getDebugLoc(), Offset, DAG);
9664 Op = DAG.getTargetGlobalAddress(GV, GA->getValueType(0), Offset);
9670 if (Result.getNode()) {
9671 Ops.push_back(Result);
9674 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, hasMemory,
9678 std::vector<unsigned> X86TargetLowering::
9679 getRegClassForInlineAsmConstraint(const std::string &Constraint,
9681 if (Constraint.size() == 1) {
9682 // FIXME: not handling fp-stack yet!
9683 switch (Constraint[0]) { // GCC X86 Constraint Letters
9684 default: break; // Unknown constraint letter
9685 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
9686 if (Subtarget->is64Bit()) {
9688 return make_vector<unsigned>(X86::EAX, X86::EDX, X86::ECX, X86::EBX,
9689 X86::ESI, X86::EDI, X86::R8D, X86::R9D,
9690 X86::R10D,X86::R11D,X86::R12D,
9691 X86::R13D,X86::R14D,X86::R15D,
9692 X86::EBP, X86::ESP, 0);
9693 else if (VT == MVT::i16)
9694 return make_vector<unsigned>(X86::AX, X86::DX, X86::CX, X86::BX,
9695 X86::SI, X86::DI, X86::R8W,X86::R9W,
9696 X86::R10W,X86::R11W,X86::R12W,
9697 X86::R13W,X86::R14W,X86::R15W,
9698 X86::BP, X86::SP, 0);
9699 else if (VT == MVT::i8)
9700 return make_vector<unsigned>(X86::AL, X86::DL, X86::CL, X86::BL,
9701 X86::SIL, X86::DIL, X86::R8B,X86::R9B,
9702 X86::R10B,X86::R11B,X86::R12B,
9703 X86::R13B,X86::R14B,X86::R15B,
9704 X86::BPL, X86::SPL, 0);
9706 else if (VT == MVT::i64)
9707 return make_vector<unsigned>(X86::RAX, X86::RDX, X86::RCX, X86::RBX,
9708 X86::RSI, X86::RDI, X86::R8, X86::R9,
9709 X86::R10, X86::R11, X86::R12,
9710 X86::R13, X86::R14, X86::R15,
9711 X86::RBP, X86::RSP, 0);
9715 // 32-bit fallthrough
9718 return make_vector<unsigned>(X86::EAX, X86::EDX, X86::ECX, X86::EBX, 0);
9719 else if (VT == MVT::i16)
9720 return make_vector<unsigned>(X86::AX, X86::DX, X86::CX, X86::BX, 0);
9721 else if (VT == MVT::i8)
9722 return make_vector<unsigned>(X86::AL, X86::DL, X86::CL, X86::BL, 0);
9723 else if (VT == MVT::i64)
9724 return make_vector<unsigned>(X86::RAX, X86::RDX, X86::RCX, X86::RBX, 0);
9729 return std::vector<unsigned>();
9732 std::pair<unsigned, const TargetRegisterClass*>
9733 X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
9735 // First, see if this is a constraint that directly corresponds to an LLVM
9737 if (Constraint.size() == 1) {
9738 // GCC Constraint Letters
9739 switch (Constraint[0]) {
9741 case 'r': // GENERAL_REGS
9742 case 'l': // INDEX_REGS
9744 return std::make_pair(0U, X86::GR8RegisterClass);
9746 return std::make_pair(0U, X86::GR16RegisterClass);
9747 if (VT == MVT::i32 || !Subtarget->is64Bit())
9748 return std::make_pair(0U, X86::GR32RegisterClass);
9749 return std::make_pair(0U, X86::GR64RegisterClass);
9750 case 'R': // LEGACY_REGS
9752 return std::make_pair(0U, X86::GR8_NOREXRegisterClass);
9754 return std::make_pair(0U, X86::GR16_NOREXRegisterClass);
9755 if (VT == MVT::i32 || !Subtarget->is64Bit())
9756 return std::make_pair(0U, X86::GR32_NOREXRegisterClass);
9757 return std::make_pair(0U, X86::GR64_NOREXRegisterClass);
9758 case 'f': // FP Stack registers.
9759 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
9760 // value to the correct fpstack register class.
9761 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
9762 return std::make_pair(0U, X86::RFP32RegisterClass);
9763 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
9764 return std::make_pair(0U, X86::RFP64RegisterClass);
9765 return std::make_pair(0U, X86::RFP80RegisterClass);
9766 case 'y': // MMX_REGS if MMX allowed.
9767 if (!Subtarget->hasMMX()) break;
9768 return std::make_pair(0U, X86::VR64RegisterClass);
9769 case 'Y': // SSE_REGS if SSE2 allowed
9770 if (!Subtarget->hasSSE2()) break;
9772 case 'x': // SSE_REGS if SSE1 allowed
9773 if (!Subtarget->hasSSE1()) break;
9775 switch (VT.getSimpleVT().SimpleTy) {
9777 // Scalar SSE types.
9780 return std::make_pair(0U, X86::FR32RegisterClass);
9783 return std::make_pair(0U, X86::FR64RegisterClass);
9791 return std::make_pair(0U, X86::VR128RegisterClass);
9797 // Use the default implementation in TargetLowering to convert the register
9798 // constraint into a member of a register class.
9799 std::pair<unsigned, const TargetRegisterClass*> Res;
9800 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
9802 // Not found as a standard register?
9803 if (Res.second == 0) {
9804 // Map st(0) -> st(7) -> ST0
9805 if (Constraint.size() == 7 && Constraint[0] == '{' &&
9806 tolower(Constraint[1]) == 's' &&
9807 tolower(Constraint[2]) == 't' &&
9808 Constraint[3] == '(' &&
9809 (Constraint[4] >= '0' && Constraint[4] <= '7') &&
9810 Constraint[5] == ')' &&
9811 Constraint[6] == '}') {
9813 Res.first = X86::ST0+Constraint[4]-'0';
9814 Res.second = X86::RFP80RegisterClass;
9818 // GCC allows "st(0)" to be called just plain "st".
9819 if (StringRef("{st}").equals_lower(Constraint)) {
9820 Res.first = X86::ST0;
9821 Res.second = X86::RFP80RegisterClass;
9826 if (StringRef("{flags}").equals_lower(Constraint)) {
9827 Res.first = X86::EFLAGS;
9828 Res.second = X86::CCRRegisterClass;
9832 // 'A' means EAX + EDX.
9833 if (Constraint == "A") {
9834 Res.first = X86::EAX;
9835 Res.second = X86::GR32_ADRegisterClass;
9841 // Otherwise, check to see if this is a register class of the wrong value
9842 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
9843 // turn into {ax},{dx}.
9844 if (Res.second->hasType(VT))
9845 return Res; // Correct type already, nothing to do.
9847 // All of the single-register GCC register classes map their values onto
9848 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
9849 // really want an 8-bit or 32-bit register, map to the appropriate register
9850 // class and return the appropriate register.
9851 if (Res.second == X86::GR16RegisterClass) {
9852 if (VT == MVT::i8) {
9853 unsigned DestReg = 0;
9854 switch (Res.first) {
9856 case X86::AX: DestReg = X86::AL; break;
9857 case X86::DX: DestReg = X86::DL; break;
9858 case X86::CX: DestReg = X86::CL; break;
9859 case X86::BX: DestReg = X86::BL; break;
9862 Res.first = DestReg;
9863 Res.second = X86::GR8RegisterClass;
9865 } else if (VT == MVT::i32) {
9866 unsigned DestReg = 0;
9867 switch (Res.first) {
9869 case X86::AX: DestReg = X86::EAX; break;
9870 case X86::DX: DestReg = X86::EDX; break;
9871 case X86::CX: DestReg = X86::ECX; break;
9872 case X86::BX: DestReg = X86::EBX; break;
9873 case X86::SI: DestReg = X86::ESI; break;
9874 case X86::DI: DestReg = X86::EDI; break;
9875 case X86::BP: DestReg = X86::EBP; break;
9876 case X86::SP: DestReg = X86::ESP; break;
9879 Res.first = DestReg;
9880 Res.second = X86::GR32RegisterClass;
9882 } else if (VT == MVT::i64) {
9883 unsigned DestReg = 0;
9884 switch (Res.first) {
9886 case X86::AX: DestReg = X86::RAX; break;
9887 case X86::DX: DestReg = X86::RDX; break;
9888 case X86::CX: DestReg = X86::RCX; break;
9889 case X86::BX: DestReg = X86::RBX; break;
9890 case X86::SI: DestReg = X86::RSI; break;
9891 case X86::DI: DestReg = X86::RDI; break;
9892 case X86::BP: DestReg = X86::RBP; break;
9893 case X86::SP: DestReg = X86::RSP; break;
9896 Res.first = DestReg;
9897 Res.second = X86::GR64RegisterClass;
9900 } else if (Res.second == X86::FR32RegisterClass ||
9901 Res.second == X86::FR64RegisterClass ||
9902 Res.second == X86::VR128RegisterClass) {
9903 // Handle references to XMM physical registers that got mapped into the
9904 // wrong class. This can happen with constraints like {xmm0} where the
9905 // target independent register mapper will just pick the first match it can
9906 // find, ignoring the required type.
9908 Res.second = X86::FR32RegisterClass;
9909 else if (VT == MVT::f64)
9910 Res.second = X86::FR64RegisterClass;
9911 else if (X86::VR128RegisterClass->hasType(VT))
9912 Res.second = X86::VR128RegisterClass;
9918 //===----------------------------------------------------------------------===//
9919 // X86 Widen vector type
9920 //===----------------------------------------------------------------------===//
9922 /// getWidenVectorType: given a vector type, returns the type to widen
9923 /// to (e.g., v7i8 to v8i8). If the vector type is legal, it returns itself.
9924 /// If there is no vector type that we want to widen to, returns MVT::Other
9925 /// When and where to widen is target dependent based on the cost of
9926 /// scalarizing vs using the wider vector type.
9928 EVT X86TargetLowering::getWidenVectorType(EVT VT) const {
9929 assert(VT.isVector());
9930 if (isTypeLegal(VT))
9933 // TODO: In computeRegisterProperty, we can compute the list of legal vector
9934 // type based on element type. This would speed up our search (though
9935 // it may not be worth it since the size of the list is relatively
9937 EVT EltVT = VT.getVectorElementType();
9938 unsigned NElts = VT.getVectorNumElements();
9940 // On X86, it make sense to widen any vector wider than 1
9944 for (unsigned nVT = MVT::FIRST_VECTOR_VALUETYPE;
9945 nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) {
9946 EVT SVT = (MVT::SimpleValueType)nVT;
9948 if (isTypeLegal(SVT) &&
9949 SVT.getVectorElementType() == EltVT &&
9950 SVT.getVectorNumElements() > NElts)