1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "x86-isel"
17 #include "X86InstrBuilder.h"
18 #include "X86ISelLowering.h"
19 #include "X86ShuffleDecode.h"
20 #include "X86TargetMachine.h"
21 #include "X86TargetObjectFile.h"
22 #include "llvm/CallingConv.h"
23 #include "llvm/Constants.h"
24 #include "llvm/DerivedTypes.h"
25 #include "llvm/GlobalAlias.h"
26 #include "llvm/GlobalVariable.h"
27 #include "llvm/Function.h"
28 #include "llvm/Instructions.h"
29 #include "llvm/Intrinsics.h"
30 #include "llvm/LLVMContext.h"
31 #include "llvm/CodeGen/MachineFrameInfo.h"
32 #include "llvm/CodeGen/MachineFunction.h"
33 #include "llvm/CodeGen/MachineInstrBuilder.h"
34 #include "llvm/CodeGen/MachineJumpTableInfo.h"
35 #include "llvm/CodeGen/MachineModuleInfo.h"
36 #include "llvm/CodeGen/MachineRegisterInfo.h"
37 #include "llvm/CodeGen/PseudoSourceValue.h"
38 #include "llvm/MC/MCAsmInfo.h"
39 #include "llvm/MC/MCContext.h"
40 #include "llvm/MC/MCExpr.h"
41 #include "llvm/MC/MCSymbol.h"
42 #include "llvm/ADT/BitVector.h"
43 #include "llvm/ADT/SmallSet.h"
44 #include "llvm/ADT/Statistic.h"
45 #include "llvm/ADT/StringExtras.h"
46 #include "llvm/ADT/VectorExtras.h"
47 #include "llvm/Support/CommandLine.h"
48 #include "llvm/Support/Debug.h"
49 #include "llvm/Support/Dwarf.h"
50 #include "llvm/Support/ErrorHandling.h"
51 #include "llvm/Support/MathExtras.h"
52 #include "llvm/Support/raw_ostream.h"
54 using namespace dwarf;
56 STATISTIC(NumTailCalls, "Number of tail calls");
59 DisableMMX("disable-mmx", cl::Hidden, cl::desc("Disable use of MMX"));
61 // Forward declarations.
62 static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
65 static TargetLoweringObjectFile *createTLOF(X86TargetMachine &TM) {
67 bool is64Bit = TM.getSubtarget<X86Subtarget>().is64Bit();
69 if (TM.getSubtarget<X86Subtarget>().isTargetDarwin()) {
70 if (is64Bit) return new X8664_MachoTargetObjectFile();
71 return new TargetLoweringObjectFileMachO();
72 } else if (TM.getSubtarget<X86Subtarget>().isTargetELF() ){
73 if (is64Bit) return new X8664_ELFTargetObjectFile(TM);
74 return new X8632_ELFTargetObjectFile(TM);
75 } else if (TM.getSubtarget<X86Subtarget>().isTargetCOFF()) {
76 return new TargetLoweringObjectFileCOFF();
78 llvm_unreachable("unknown subtarget type");
81 X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
82 : TargetLowering(TM, createTLOF(TM)) {
83 Subtarget = &TM.getSubtarget<X86Subtarget>();
84 X86ScalarSSEf64 = Subtarget->hasSSE2();
85 X86ScalarSSEf32 = Subtarget->hasSSE1();
86 X86StackPtr = Subtarget->is64Bit() ? X86::RSP : X86::ESP;
88 RegInfo = TM.getRegisterInfo();
91 // Set up the TargetLowering object.
93 // X86 is weird, it always uses i8 for shift amounts and setcc results.
94 setShiftAmountType(MVT::i8);
95 setBooleanContents(ZeroOrOneBooleanContent);
96 setSchedulingPreference(Sched::RegPressure);
97 setStackPointerRegisterToSaveRestore(X86StackPtr);
99 if (Subtarget->isTargetWindows() && !Subtarget->isTargetCygMing()) {
100 // Setup Windows compiler runtime calls.
101 setLibcallName(RTLIB::SDIV_I64, "_alldiv");
102 setLibcallName(RTLIB::UDIV_I64, "_aulldiv");
103 setLibcallName(RTLIB::FPTOUINT_F64_I64, "_ftol2");
104 setLibcallName(RTLIB::FPTOUINT_F32_I64, "_ftol2");
105 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall);
106 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall);
107 setLibcallCallingConv(RTLIB::FPTOUINT_F64_I64, CallingConv::C);
108 setLibcallCallingConv(RTLIB::FPTOUINT_F32_I64, CallingConv::C);
111 if (Subtarget->isTargetDarwin()) {
112 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
113 setUseUnderscoreSetJmp(false);
114 setUseUnderscoreLongJmp(false);
115 } else if (Subtarget->isTargetMingw()) {
116 // MS runtime is weird: it exports _setjmp, but longjmp!
117 setUseUnderscoreSetJmp(true);
118 setUseUnderscoreLongJmp(false);
120 setUseUnderscoreSetJmp(true);
121 setUseUnderscoreLongJmp(true);
124 // Set up the register classes.
125 addRegisterClass(MVT::i8, X86::GR8RegisterClass);
126 addRegisterClass(MVT::i16, X86::GR16RegisterClass);
127 addRegisterClass(MVT::i32, X86::GR32RegisterClass);
128 if (Subtarget->is64Bit())
129 addRegisterClass(MVT::i64, X86::GR64RegisterClass);
131 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
133 // We don't accept any truncstore of integer registers.
134 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
135 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
136 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
137 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
138 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
139 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
141 // SETOEQ and SETUNE require checking two conditions.
142 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
143 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
144 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
145 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
146 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
147 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
149 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
151 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
152 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
153 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
155 if (Subtarget->is64Bit()) {
156 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
157 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Expand);
158 } else if (!UseSoftFloat) {
159 // We have an algorithm for SSE2->double, and we turn this into a
160 // 64-bit FILD followed by conditional FADD for other targets.
161 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
162 // We have an algorithm for SSE2, and we turn this into a 64-bit
163 // FILD for other targets.
164 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
167 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
169 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
170 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
173 // SSE has no i16 to fp conversion, only i32
174 if (X86ScalarSSEf32) {
175 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
176 // f32 and f64 cases are Legal, f80 case is not
177 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
179 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
180 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
183 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
184 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
187 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
188 // are Legal, f80 is custom lowered.
189 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
190 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
192 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
194 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
195 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
197 if (X86ScalarSSEf32) {
198 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
199 // f32 and f64 cases are Legal, f80 case is not
200 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
202 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
203 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
206 // Handle FP_TO_UINT by promoting the destination to a larger signed
208 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
209 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
210 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
212 if (Subtarget->is64Bit()) {
213 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
214 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
215 } else if (!UseSoftFloat) {
216 if (X86ScalarSSEf32 && !Subtarget->hasSSE3())
217 // Expand FP_TO_UINT into a select.
218 // FIXME: We would like to use a Custom expander here eventually to do
219 // the optimal thing for SSE vs. the default expansion in the legalizer.
220 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
222 // With SSE3 we can use fisttpll to convert to a signed i64; without
223 // SSE, we're stuck with a fistpll.
224 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
227 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
228 if (!X86ScalarSSEf64) {
229 setOperationAction(ISD::BIT_CONVERT , MVT::f32 , Expand);
230 setOperationAction(ISD::BIT_CONVERT , MVT::i32 , Expand);
231 if (Subtarget->is64Bit()) {
232 setOperationAction(ISD::BIT_CONVERT , MVT::f64 , Expand);
233 // Without SSE, i64->f64 goes through memory.
234 setOperationAction(ISD::BIT_CONVERT , MVT::i64 , Expand);
238 // Scalar integer divide and remainder are lowered to use operations that
239 // produce two results, to match the available instructions. This exposes
240 // the two-result form to trivial CSE, which is able to combine x/y and x%y
241 // into a single instruction.
243 // Scalar integer multiply-high is also lowered to use two-result
244 // operations, to match the available instructions. However, plain multiply
245 // (low) operations are left as Legal, as there are single-result
246 // instructions for this in x86. Using the two-result multiply instructions
247 // when both high and low results are needed must be arranged by dagcombine.
248 setOperationAction(ISD::MULHS , MVT::i8 , Expand);
249 setOperationAction(ISD::MULHU , MVT::i8 , Expand);
250 setOperationAction(ISD::SDIV , MVT::i8 , Expand);
251 setOperationAction(ISD::UDIV , MVT::i8 , Expand);
252 setOperationAction(ISD::SREM , MVT::i8 , Expand);
253 setOperationAction(ISD::UREM , MVT::i8 , Expand);
254 setOperationAction(ISD::MULHS , MVT::i16 , Expand);
255 setOperationAction(ISD::MULHU , MVT::i16 , Expand);
256 setOperationAction(ISD::SDIV , MVT::i16 , Expand);
257 setOperationAction(ISD::UDIV , MVT::i16 , Expand);
258 setOperationAction(ISD::SREM , MVT::i16 , Expand);
259 setOperationAction(ISD::UREM , MVT::i16 , Expand);
260 setOperationAction(ISD::MULHS , MVT::i32 , Expand);
261 setOperationAction(ISD::MULHU , MVT::i32 , Expand);
262 setOperationAction(ISD::SDIV , MVT::i32 , Expand);
263 setOperationAction(ISD::UDIV , MVT::i32 , Expand);
264 setOperationAction(ISD::SREM , MVT::i32 , Expand);
265 setOperationAction(ISD::UREM , MVT::i32 , Expand);
266 setOperationAction(ISD::MULHS , MVT::i64 , Expand);
267 setOperationAction(ISD::MULHU , MVT::i64 , Expand);
268 setOperationAction(ISD::SDIV , MVT::i64 , Expand);
269 setOperationAction(ISD::UDIV , MVT::i64 , Expand);
270 setOperationAction(ISD::SREM , MVT::i64 , Expand);
271 setOperationAction(ISD::UREM , MVT::i64 , Expand);
273 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
274 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
275 setOperationAction(ISD::BR_CC , MVT::Other, Expand);
276 setOperationAction(ISD::SELECT_CC , MVT::Other, Expand);
277 if (Subtarget->is64Bit())
278 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
279 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
280 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
281 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
282 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
283 setOperationAction(ISD::FREM , MVT::f32 , Expand);
284 setOperationAction(ISD::FREM , MVT::f64 , Expand);
285 setOperationAction(ISD::FREM , MVT::f80 , Expand);
286 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
288 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
289 setOperationAction(ISD::CTTZ , MVT::i8 , Custom);
290 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
291 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
292 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
293 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
294 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
295 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
296 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
297 if (Subtarget->is64Bit()) {
298 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
299 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
300 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
303 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
304 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
306 // These should be promoted to a larger select which is supported.
307 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
308 // X86 wants to expand cmov itself.
309 setOperationAction(ISD::SELECT , MVT::i8 , Custom);
310 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
311 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
312 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
313 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
314 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
315 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
316 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
317 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
318 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
319 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
320 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
321 if (Subtarget->is64Bit()) {
322 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
323 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
325 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
328 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
329 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
330 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
331 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
332 if (Subtarget->is64Bit())
333 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
334 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
335 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom);
336 if (Subtarget->is64Bit()) {
337 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
338 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
339 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
340 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
341 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom);
343 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
344 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
345 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
346 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
347 if (Subtarget->is64Bit()) {
348 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
349 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
350 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
353 if (Subtarget->hasSSE1())
354 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
356 // We may not have a libcall for MEMBARRIER so we should lower this.
357 setOperationAction(ISD::MEMBARRIER , MVT::Other, Custom);
359 // On X86 and X86-64, atomic operations are lowered to locked instructions.
360 // Locked instructions, in turn, have implicit fence semantics (all memory
361 // operations are flushed before issuing the locked instruction, and they
362 // are not buffered), so we can fold away the common pattern of
363 // fence-atomic-fence.
364 setShouldFoldAtomicFences(true);
366 // Expand certain atomics
367 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i8, Custom);
368 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i16, Custom);
369 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Custom);
370 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i64, Custom);
372 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i8, Custom);
373 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i16, Custom);
374 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i32, Custom);
375 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom);
377 if (!Subtarget->is64Bit()) {
378 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i64, Custom);
379 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom);
380 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i64, Custom);
381 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i64, Custom);
382 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i64, Custom);
383 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i64, Custom);
384 setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Custom);
387 // FIXME - use subtarget debug flags
388 if (!Subtarget->isTargetDarwin() &&
389 !Subtarget->isTargetELF() &&
390 !Subtarget->isTargetCygMing()) {
391 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
394 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand);
395 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand);
396 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
397 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
398 if (Subtarget->is64Bit()) {
399 setExceptionPointerRegister(X86::RAX);
400 setExceptionSelectorRegister(X86::RDX);
402 setExceptionPointerRegister(X86::EAX);
403 setExceptionSelectorRegister(X86::EDX);
405 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
406 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
408 setOperationAction(ISD::TRAMPOLINE, MVT::Other, Custom);
410 setOperationAction(ISD::TRAP, MVT::Other, Legal);
412 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
413 setOperationAction(ISD::VASTART , MVT::Other, Custom);
414 setOperationAction(ISD::VAEND , MVT::Other, Expand);
415 if (Subtarget->is64Bit()) {
416 setOperationAction(ISD::VAARG , MVT::Other, Custom);
417 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
419 setOperationAction(ISD::VAARG , MVT::Other, Expand);
420 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
423 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
424 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
425 if (Subtarget->is64Bit())
426 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand);
427 if (Subtarget->isTargetCygMing() || Subtarget->isTargetWindows())
428 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom);
430 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
432 if (!UseSoftFloat && X86ScalarSSEf64) {
433 // f32 and f64 use SSE.
434 // Set up the FP register classes.
435 addRegisterClass(MVT::f32, X86::FR32RegisterClass);
436 addRegisterClass(MVT::f64, X86::FR64RegisterClass);
438 // Use ANDPD to simulate FABS.
439 setOperationAction(ISD::FABS , MVT::f64, Custom);
440 setOperationAction(ISD::FABS , MVT::f32, Custom);
442 // Use XORP to simulate FNEG.
443 setOperationAction(ISD::FNEG , MVT::f64, Custom);
444 setOperationAction(ISD::FNEG , MVT::f32, Custom);
446 // Use ANDPD and ORPD to simulate FCOPYSIGN.
447 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
448 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
450 // We don't support sin/cos/fmod
451 setOperationAction(ISD::FSIN , MVT::f64, Expand);
452 setOperationAction(ISD::FCOS , MVT::f64, Expand);
453 setOperationAction(ISD::FSIN , MVT::f32, Expand);
454 setOperationAction(ISD::FCOS , MVT::f32, Expand);
456 // Expand FP immediates into loads from the stack, except for the special
458 addLegalFPImmediate(APFloat(+0.0)); // xorpd
459 addLegalFPImmediate(APFloat(+0.0f)); // xorps
460 } else if (!UseSoftFloat && X86ScalarSSEf32) {
461 // Use SSE for f32, x87 for f64.
462 // Set up the FP register classes.
463 addRegisterClass(MVT::f32, X86::FR32RegisterClass);
464 addRegisterClass(MVT::f64, X86::RFP64RegisterClass);
466 // Use ANDPS to simulate FABS.
467 setOperationAction(ISD::FABS , MVT::f32, Custom);
469 // Use XORP to simulate FNEG.
470 setOperationAction(ISD::FNEG , MVT::f32, Custom);
472 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
474 // Use ANDPS and ORPS to simulate FCOPYSIGN.
475 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
476 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
478 // We don't support sin/cos/fmod
479 setOperationAction(ISD::FSIN , MVT::f32, Expand);
480 setOperationAction(ISD::FCOS , MVT::f32, Expand);
482 // Special cases we handle for FP constants.
483 addLegalFPImmediate(APFloat(+0.0f)); // xorps
484 addLegalFPImmediate(APFloat(+0.0)); // FLD0
485 addLegalFPImmediate(APFloat(+1.0)); // FLD1
486 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
487 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
490 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
491 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
493 } else if (!UseSoftFloat) {
494 // f32 and f64 in x87.
495 // Set up the FP register classes.
496 addRegisterClass(MVT::f64, X86::RFP64RegisterClass);
497 addRegisterClass(MVT::f32, X86::RFP32RegisterClass);
499 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
500 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
501 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
502 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
505 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
506 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
508 addLegalFPImmediate(APFloat(+0.0)); // FLD0
509 addLegalFPImmediate(APFloat(+1.0)); // FLD1
510 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
511 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
512 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
513 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
514 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
515 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
518 // Long double always uses X87.
520 addRegisterClass(MVT::f80, X86::RFP80RegisterClass);
521 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
522 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
525 APFloat TmpFlt(+0.0);
526 TmpFlt.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
528 addLegalFPImmediate(TmpFlt); // FLD0
530 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
531 APFloat TmpFlt2(+1.0);
532 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
534 addLegalFPImmediate(TmpFlt2); // FLD1
535 TmpFlt2.changeSign();
536 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
540 setOperationAction(ISD::FSIN , MVT::f80 , Expand);
541 setOperationAction(ISD::FCOS , MVT::f80 , Expand);
545 // Always use a library call for pow.
546 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
547 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
548 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
550 setOperationAction(ISD::FLOG, MVT::f80, Expand);
551 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
552 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
553 setOperationAction(ISD::FEXP, MVT::f80, Expand);
554 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
556 // First set operation action for all vector types to either promote
557 // (for widening) or expand (for scalarization). Then we will selectively
558 // turn on ones that can be effectively codegen'd.
559 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
560 VT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) {
561 setOperationAction(ISD::ADD , (MVT::SimpleValueType)VT, Expand);
562 setOperationAction(ISD::SUB , (MVT::SimpleValueType)VT, Expand);
563 setOperationAction(ISD::FADD, (MVT::SimpleValueType)VT, Expand);
564 setOperationAction(ISD::FNEG, (MVT::SimpleValueType)VT, Expand);
565 setOperationAction(ISD::FSUB, (MVT::SimpleValueType)VT, Expand);
566 setOperationAction(ISD::MUL , (MVT::SimpleValueType)VT, Expand);
567 setOperationAction(ISD::FMUL, (MVT::SimpleValueType)VT, Expand);
568 setOperationAction(ISD::SDIV, (MVT::SimpleValueType)VT, Expand);
569 setOperationAction(ISD::UDIV, (MVT::SimpleValueType)VT, Expand);
570 setOperationAction(ISD::FDIV, (MVT::SimpleValueType)VT, Expand);
571 setOperationAction(ISD::SREM, (MVT::SimpleValueType)VT, Expand);
572 setOperationAction(ISD::UREM, (MVT::SimpleValueType)VT, Expand);
573 setOperationAction(ISD::LOAD, (MVT::SimpleValueType)VT, Expand);
574 setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::SimpleValueType)VT, Expand);
575 setOperationAction(ISD::EXTRACT_VECTOR_ELT,(MVT::SimpleValueType)VT,Expand);
576 setOperationAction(ISD::EXTRACT_SUBVECTOR,(MVT::SimpleValueType)VT,Expand);
577 setOperationAction(ISD::INSERT_VECTOR_ELT,(MVT::SimpleValueType)VT, Expand);
578 setOperationAction(ISD::FABS, (MVT::SimpleValueType)VT, Expand);
579 setOperationAction(ISD::FSIN, (MVT::SimpleValueType)VT, Expand);
580 setOperationAction(ISD::FCOS, (MVT::SimpleValueType)VT, Expand);
581 setOperationAction(ISD::FREM, (MVT::SimpleValueType)VT, Expand);
582 setOperationAction(ISD::FPOWI, (MVT::SimpleValueType)VT, Expand);
583 setOperationAction(ISD::FSQRT, (MVT::SimpleValueType)VT, Expand);
584 setOperationAction(ISD::FCOPYSIGN, (MVT::SimpleValueType)VT, Expand);
585 setOperationAction(ISD::SMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
586 setOperationAction(ISD::UMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
587 setOperationAction(ISD::SDIVREM, (MVT::SimpleValueType)VT, Expand);
588 setOperationAction(ISD::UDIVREM, (MVT::SimpleValueType)VT, Expand);
589 setOperationAction(ISD::FPOW, (MVT::SimpleValueType)VT, Expand);
590 setOperationAction(ISD::CTPOP, (MVT::SimpleValueType)VT, Expand);
591 setOperationAction(ISD::CTTZ, (MVT::SimpleValueType)VT, Expand);
592 setOperationAction(ISD::CTLZ, (MVT::SimpleValueType)VT, Expand);
593 setOperationAction(ISD::SHL, (MVT::SimpleValueType)VT, Expand);
594 setOperationAction(ISD::SRA, (MVT::SimpleValueType)VT, Expand);
595 setOperationAction(ISD::SRL, (MVT::SimpleValueType)VT, Expand);
596 setOperationAction(ISD::ROTL, (MVT::SimpleValueType)VT, Expand);
597 setOperationAction(ISD::ROTR, (MVT::SimpleValueType)VT, Expand);
598 setOperationAction(ISD::BSWAP, (MVT::SimpleValueType)VT, Expand);
599 setOperationAction(ISD::VSETCC, (MVT::SimpleValueType)VT, Expand);
600 setOperationAction(ISD::FLOG, (MVT::SimpleValueType)VT, Expand);
601 setOperationAction(ISD::FLOG2, (MVT::SimpleValueType)VT, Expand);
602 setOperationAction(ISD::FLOG10, (MVT::SimpleValueType)VT, Expand);
603 setOperationAction(ISD::FEXP, (MVT::SimpleValueType)VT, Expand);
604 setOperationAction(ISD::FEXP2, (MVT::SimpleValueType)VT, Expand);
605 setOperationAction(ISD::FP_TO_UINT, (MVT::SimpleValueType)VT, Expand);
606 setOperationAction(ISD::FP_TO_SINT, (MVT::SimpleValueType)VT, Expand);
607 setOperationAction(ISD::UINT_TO_FP, (MVT::SimpleValueType)VT, Expand);
608 setOperationAction(ISD::SINT_TO_FP, (MVT::SimpleValueType)VT, Expand);
609 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,Expand);
610 setOperationAction(ISD::TRUNCATE, (MVT::SimpleValueType)VT, Expand);
611 setOperationAction(ISD::SIGN_EXTEND, (MVT::SimpleValueType)VT, Expand);
612 setOperationAction(ISD::ZERO_EXTEND, (MVT::SimpleValueType)VT, Expand);
613 setOperationAction(ISD::ANY_EXTEND, (MVT::SimpleValueType)VT, Expand);
614 for (unsigned InnerVT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
615 InnerVT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++InnerVT)
616 setTruncStoreAction((MVT::SimpleValueType)VT,
617 (MVT::SimpleValueType)InnerVT, Expand);
618 setLoadExtAction(ISD::SEXTLOAD, (MVT::SimpleValueType)VT, Expand);
619 setLoadExtAction(ISD::ZEXTLOAD, (MVT::SimpleValueType)VT, Expand);
620 setLoadExtAction(ISD::EXTLOAD, (MVT::SimpleValueType)VT, Expand);
623 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
624 // with -msoft-float, disable use of MMX as well.
625 if (!UseSoftFloat && !DisableMMX && Subtarget->hasMMX()) {
626 addRegisterClass(MVT::x86mmx, X86::VR64RegisterClass);
627 // No operations on x86mmx supported, everything uses intrinsics.
630 // MMX-sized vectors (other than x86mmx) are expected to be expanded
631 // into smaller operations.
632 setOperationAction(ISD::MULHS, MVT::v8i8, Expand);
633 setOperationAction(ISD::MULHS, MVT::v4i16, Expand);
634 setOperationAction(ISD::MULHS, MVT::v2i32, Expand);
635 setOperationAction(ISD::MULHS, MVT::v1i64, Expand);
636 setOperationAction(ISD::AND, MVT::v8i8, Expand);
637 setOperationAction(ISD::AND, MVT::v4i16, Expand);
638 setOperationAction(ISD::AND, MVT::v2i32, Expand);
639 setOperationAction(ISD::AND, MVT::v1i64, Expand);
640 setOperationAction(ISD::OR, MVT::v8i8, Expand);
641 setOperationAction(ISD::OR, MVT::v4i16, Expand);
642 setOperationAction(ISD::OR, MVT::v2i32, Expand);
643 setOperationAction(ISD::OR, MVT::v1i64, Expand);
644 setOperationAction(ISD::XOR, MVT::v8i8, Expand);
645 setOperationAction(ISD::XOR, MVT::v4i16, Expand);
646 setOperationAction(ISD::XOR, MVT::v2i32, Expand);
647 setOperationAction(ISD::XOR, MVT::v1i64, Expand);
648 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Expand);
649 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Expand);
650 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i32, Expand);
651 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Expand);
652 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand);
653 setOperationAction(ISD::SELECT, MVT::v8i8, Expand);
654 setOperationAction(ISD::SELECT, MVT::v4i16, Expand);
655 setOperationAction(ISD::SELECT, MVT::v2i32, Expand);
656 setOperationAction(ISD::SELECT, MVT::v1i64, Expand);
657 setOperationAction(ISD::BIT_CONVERT, MVT::v8i8, Expand);
658 setOperationAction(ISD::BIT_CONVERT, MVT::v4i16, Expand);
659 setOperationAction(ISD::BIT_CONVERT, MVT::v2i32, Expand);
660 setOperationAction(ISD::BIT_CONVERT, MVT::v1i64, Expand);
662 if (!UseSoftFloat && Subtarget->hasSSE1()) {
663 addRegisterClass(MVT::v4f32, X86::VR128RegisterClass);
665 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
666 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
667 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
668 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
669 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
670 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
671 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
672 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
673 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
674 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
675 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
676 setOperationAction(ISD::VSETCC, MVT::v4f32, Custom);
679 if (!UseSoftFloat && Subtarget->hasSSE2()) {
680 addRegisterClass(MVT::v2f64, X86::VR128RegisterClass);
682 // FIXME: Unfortunately -soft-float and -no-implicit-float means XMM
683 // registers cannot be used even for integer operations.
684 addRegisterClass(MVT::v16i8, X86::VR128RegisterClass);
685 addRegisterClass(MVT::v8i16, X86::VR128RegisterClass);
686 addRegisterClass(MVT::v4i32, X86::VR128RegisterClass);
687 addRegisterClass(MVT::v2i64, X86::VR128RegisterClass);
689 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
690 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
691 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
692 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
693 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
694 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
695 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
696 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
697 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
698 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
699 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
700 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
701 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
702 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
703 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
704 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
706 setOperationAction(ISD::VSETCC, MVT::v2f64, Custom);
707 setOperationAction(ISD::VSETCC, MVT::v16i8, Custom);
708 setOperationAction(ISD::VSETCC, MVT::v8i16, Custom);
709 setOperationAction(ISD::VSETCC, MVT::v4i32, Custom);
711 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
712 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
713 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
714 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
715 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
717 setOperationAction(ISD::CONCAT_VECTORS, MVT::v2f64, Custom);
718 setOperationAction(ISD::CONCAT_VECTORS, MVT::v2i64, Custom);
719 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i8, Custom);
720 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i16, Custom);
721 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i32, Custom);
723 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
724 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; ++i) {
725 EVT VT = (MVT::SimpleValueType)i;
726 // Do not attempt to custom lower non-power-of-2 vectors
727 if (!isPowerOf2_32(VT.getVectorNumElements()))
729 // Do not attempt to custom lower non-128-bit vectors
730 if (!VT.is128BitVector())
732 setOperationAction(ISD::BUILD_VECTOR,
733 VT.getSimpleVT().SimpleTy, Custom);
734 setOperationAction(ISD::VECTOR_SHUFFLE,
735 VT.getSimpleVT().SimpleTy, Custom);
736 setOperationAction(ISD::EXTRACT_VECTOR_ELT,
737 VT.getSimpleVT().SimpleTy, Custom);
740 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
741 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
742 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
743 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
744 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
745 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
747 if (Subtarget->is64Bit()) {
748 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
749 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
752 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
753 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; i++) {
754 MVT::SimpleValueType SVT = (MVT::SimpleValueType)i;
757 // Do not attempt to promote non-128-bit vectors
758 if (!VT.is128BitVector())
761 setOperationAction(ISD::AND, SVT, Promote);
762 AddPromotedToType (ISD::AND, SVT, MVT::v2i64);
763 setOperationAction(ISD::OR, SVT, Promote);
764 AddPromotedToType (ISD::OR, SVT, MVT::v2i64);
765 setOperationAction(ISD::XOR, SVT, Promote);
766 AddPromotedToType (ISD::XOR, SVT, MVT::v2i64);
767 setOperationAction(ISD::LOAD, SVT, Promote);
768 AddPromotedToType (ISD::LOAD, SVT, MVT::v2i64);
769 setOperationAction(ISD::SELECT, SVT, Promote);
770 AddPromotedToType (ISD::SELECT, SVT, MVT::v2i64);
773 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
775 // Custom lower v2i64 and v2f64 selects.
776 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
777 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
778 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
779 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
781 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
782 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
785 if (Subtarget->hasSSE41()) {
786 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
787 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
788 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
789 setOperationAction(ISD::FRINT, MVT::f32, Legal);
790 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
791 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
792 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
793 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
794 setOperationAction(ISD::FRINT, MVT::f64, Legal);
795 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
797 // FIXME: Do we need to handle scalar-to-vector here?
798 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
800 // Can turn SHL into an integer multiply.
801 setOperationAction(ISD::SHL, MVT::v4i32, Custom);
802 setOperationAction(ISD::SHL, MVT::v16i8, Custom);
804 // i8 and i16 vectors are custom , because the source register and source
805 // source memory operand types are not the same width. f32 vectors are
806 // custom since the immediate controlling the insert encodes additional
808 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
809 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
810 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
811 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
813 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
814 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
815 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
816 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
818 if (Subtarget->is64Bit()) {
819 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Legal);
820 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Legal);
824 if (Subtarget->hasSSE42()) {
825 setOperationAction(ISD::VSETCC, MVT::v2i64, Custom);
828 if (!UseSoftFloat && Subtarget->hasAVX()) {
829 addRegisterClass(MVT::v8f32, X86::VR256RegisterClass);
830 addRegisterClass(MVT::v4f64, X86::VR256RegisterClass);
831 addRegisterClass(MVT::v8i32, X86::VR256RegisterClass);
832 addRegisterClass(MVT::v4i64, X86::VR256RegisterClass);
833 addRegisterClass(MVT::v32i8, X86::VR256RegisterClass);
835 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
836 setOperationAction(ISD::LOAD, MVT::v8i32, Legal);
837 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
838 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
839 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
840 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
841 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
842 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
843 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
844 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
845 setOperationAction(ISD::BUILD_VECTOR, MVT::v8f32, Custom);
846 //setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8f32, Custom);
847 //setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8f32, Custom);
848 //setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
849 //setOperationAction(ISD::VSETCC, MVT::v8f32, Custom);
851 // Operations to consider commented out -v16i16 v32i8
852 //setOperationAction(ISD::ADD, MVT::v16i16, Legal);
853 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
854 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
855 //setOperationAction(ISD::SUB, MVT::v32i8, Legal);
856 //setOperationAction(ISD::SUB, MVT::v16i16, Legal);
857 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
858 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
859 //setOperationAction(ISD::MUL, MVT::v16i16, Legal);
860 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
861 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
862 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
863 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
864 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
865 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
867 setOperationAction(ISD::VSETCC, MVT::v4f64, Custom);
868 // setOperationAction(ISD::VSETCC, MVT::v32i8, Custom);
869 // setOperationAction(ISD::VSETCC, MVT::v16i16, Custom);
870 setOperationAction(ISD::VSETCC, MVT::v8i32, Custom);
872 // setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v32i8, Custom);
873 // setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i16, Custom);
874 // setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i16, Custom);
875 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i32, Custom);
876 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8f32, Custom);
878 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f64, Custom);
879 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i64, Custom);
880 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f64, Custom);
881 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i64, Custom);
882 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f64, Custom);
883 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f64, Custom);
886 // Not sure we want to do this since there are no 256-bit integer
889 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
890 // This includes 256-bit vectors
891 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v4i64; ++i) {
892 EVT VT = (MVT::SimpleValueType)i;
894 // Do not attempt to custom lower non-power-of-2 vectors
895 if (!isPowerOf2_32(VT.getVectorNumElements()))
898 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
899 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
900 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
903 if (Subtarget->is64Bit()) {
904 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i64, Custom);
905 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i64, Custom);
910 // Not sure we want to do this since there are no 256-bit integer
913 // Promote v32i8, v16i16, v8i32 load, select, and, or, xor to v4i64.
914 // Including 256-bit vectors
915 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v4i64; i++) {
916 EVT VT = (MVT::SimpleValueType)i;
918 if (!VT.is256BitVector()) {
921 setOperationAction(ISD::AND, VT, Promote);
922 AddPromotedToType (ISD::AND, VT, MVT::v4i64);
923 setOperationAction(ISD::OR, VT, Promote);
924 AddPromotedToType (ISD::OR, VT, MVT::v4i64);
925 setOperationAction(ISD::XOR, VT, Promote);
926 AddPromotedToType (ISD::XOR, VT, MVT::v4i64);
927 setOperationAction(ISD::LOAD, VT, Promote);
928 AddPromotedToType (ISD::LOAD, VT, MVT::v4i64);
929 setOperationAction(ISD::SELECT, VT, Promote);
930 AddPromotedToType (ISD::SELECT, VT, MVT::v4i64);
933 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
937 // We want to custom lower some of our intrinsics.
938 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
940 // Add/Sub/Mul with overflow operations are custom lowered.
941 setOperationAction(ISD::SADDO, MVT::i32, Custom);
942 setOperationAction(ISD::UADDO, MVT::i32, Custom);
943 setOperationAction(ISD::SSUBO, MVT::i32, Custom);
944 setOperationAction(ISD::USUBO, MVT::i32, Custom);
945 setOperationAction(ISD::SMULO, MVT::i32, Custom);
947 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't
948 // handle type legalization for these operations here.
950 // FIXME: We really should do custom legalization for addition and
951 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better
952 // than generic legalization for 64-bit multiplication-with-overflow, though.
953 if (Subtarget->is64Bit()) {
954 setOperationAction(ISD::SADDO, MVT::i64, Custom);
955 setOperationAction(ISD::UADDO, MVT::i64, Custom);
956 setOperationAction(ISD::SSUBO, MVT::i64, Custom);
957 setOperationAction(ISD::USUBO, MVT::i64, Custom);
958 setOperationAction(ISD::SMULO, MVT::i64, Custom);
961 if (!Subtarget->is64Bit()) {
962 // These libcalls are not available in 32-bit.
963 setLibcallName(RTLIB::SHL_I128, 0);
964 setLibcallName(RTLIB::SRL_I128, 0);
965 setLibcallName(RTLIB::SRA_I128, 0);
968 // We have target-specific dag combine patterns for the following nodes:
969 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
970 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
971 setTargetDAGCombine(ISD::BUILD_VECTOR);
972 setTargetDAGCombine(ISD::SELECT);
973 setTargetDAGCombine(ISD::SHL);
974 setTargetDAGCombine(ISD::SRA);
975 setTargetDAGCombine(ISD::SRL);
976 setTargetDAGCombine(ISD::OR);
977 setTargetDAGCombine(ISD::STORE);
978 setTargetDAGCombine(ISD::ZERO_EXTEND);
979 if (Subtarget->is64Bit())
980 setTargetDAGCombine(ISD::MUL);
982 computeRegisterProperties();
984 // FIXME: These should be based on subtarget info. Plus, the values should
985 // be smaller when we are in optimizing for size mode.
986 maxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
987 maxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores
988 maxStoresPerMemmove = 3; // For @llvm.memmove -> sequence of stores
989 setPrefLoopAlignment(16);
990 benefitFromCodePlacementOpt = true;
994 MVT::SimpleValueType X86TargetLowering::getSetCCResultType(EVT VT) const {
999 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
1000 /// the desired ByVal argument alignment.
1001 static void getMaxByValAlign(const Type *Ty, unsigned &MaxAlign) {
1004 if (const VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1005 if (VTy->getBitWidth() == 128)
1007 } else if (const ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1008 unsigned EltAlign = 0;
1009 getMaxByValAlign(ATy->getElementType(), EltAlign);
1010 if (EltAlign > MaxAlign)
1011 MaxAlign = EltAlign;
1012 } else if (const StructType *STy = dyn_cast<StructType>(Ty)) {
1013 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
1014 unsigned EltAlign = 0;
1015 getMaxByValAlign(STy->getElementType(i), EltAlign);
1016 if (EltAlign > MaxAlign)
1017 MaxAlign = EltAlign;
1025 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1026 /// function arguments in the caller parameter area. For X86, aggregates
1027 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
1028 /// are at 4-byte boundaries.
1029 unsigned X86TargetLowering::getByValTypeAlignment(const Type *Ty) const {
1030 if (Subtarget->is64Bit()) {
1031 // Max of 8 and alignment of type.
1032 unsigned TyAlign = TD->getABITypeAlignment(Ty);
1039 if (Subtarget->hasSSE1())
1040 getMaxByValAlign(Ty, Align);
1044 /// getOptimalMemOpType - Returns the target specific optimal type for load
1045 /// and store operations as a result of memset, memcpy, and memmove
1046 /// lowering. If DstAlign is zero that means it's safe to destination
1047 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
1048 /// means there isn't a need to check it against alignment requirement,
1049 /// probably because the source does not need to be loaded. If
1050 /// 'NonScalarIntSafe' is true, that means it's safe to return a
1051 /// non-scalar-integer type, e.g. empty string source, constant, or loaded
1052 /// from memory. 'MemcpyStrSrc' indicates whether the memcpy source is
1053 /// constant so it does not need to be loaded.
1054 /// It returns EVT::Other if the type should be determined using generic
1055 /// target-independent logic.
1057 X86TargetLowering::getOptimalMemOpType(uint64_t Size,
1058 unsigned DstAlign, unsigned SrcAlign,
1059 bool NonScalarIntSafe,
1061 MachineFunction &MF) const {
1062 // FIXME: This turns off use of xmm stores for memset/memcpy on targets like
1063 // linux. This is because the stack realignment code can't handle certain
1064 // cases like PR2962. This should be removed when PR2962 is fixed.
1065 const Function *F = MF.getFunction();
1066 if (NonScalarIntSafe &&
1067 !F->hasFnAttr(Attribute::NoImplicitFloat)) {
1069 (Subtarget->isUnalignedMemAccessFast() ||
1070 ((DstAlign == 0 || DstAlign >= 16) &&
1071 (SrcAlign == 0 || SrcAlign >= 16))) &&
1072 Subtarget->getStackAlignment() >= 16) {
1073 if (Subtarget->hasSSE2())
1075 if (Subtarget->hasSSE1())
1077 } else if (!MemcpyStrSrc && Size >= 8 &&
1078 !Subtarget->is64Bit() &&
1079 Subtarget->getStackAlignment() >= 8 &&
1080 Subtarget->hasSSE2()) {
1081 // Do not use f64 to lower memcpy if source is string constant. It's
1082 // better to use i32 to avoid the loads.
1086 if (Subtarget->is64Bit() && Size >= 8)
1091 /// getJumpTableEncoding - Return the entry encoding for a jump table in the
1092 /// current function. The returned value is a member of the
1093 /// MachineJumpTableInfo::JTEntryKind enum.
1094 unsigned X86TargetLowering::getJumpTableEncoding() const {
1095 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
1097 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1098 Subtarget->isPICStyleGOT())
1099 return MachineJumpTableInfo::EK_Custom32;
1101 // Otherwise, use the normal jump table encoding heuristics.
1102 return TargetLowering::getJumpTableEncoding();
1106 X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
1107 const MachineBasicBlock *MBB,
1108 unsigned uid,MCContext &Ctx) const{
1109 assert(getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1110 Subtarget->isPICStyleGOT());
1111 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
1113 return MCSymbolRefExpr::Create(MBB->getSymbol(),
1114 MCSymbolRefExpr::VK_GOTOFF, Ctx);
1117 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
1119 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
1120 SelectionDAG &DAG) const {
1121 if (!Subtarget->is64Bit())
1122 // This doesn't have DebugLoc associated with it, but is not really the
1123 // same as a Register.
1124 return DAG.getNode(X86ISD::GlobalBaseReg, DebugLoc(), getPointerTy());
1128 /// getPICJumpTableRelocBaseExpr - This returns the relocation base for the
1129 /// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an
1131 const MCExpr *X86TargetLowering::
1132 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
1133 MCContext &Ctx) const {
1134 // X86-64 uses RIP relative addressing based on the jump table label.
1135 if (Subtarget->isPICStyleRIPRel())
1136 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
1138 // Otherwise, the reference is relative to the PIC base.
1139 return MCSymbolRefExpr::Create(MF->getPICBaseSymbol(), Ctx);
1142 /// getFunctionAlignment - Return the Log2 alignment of this function.
1143 unsigned X86TargetLowering::getFunctionAlignment(const Function *F) const {
1144 return F->hasFnAttr(Attribute::OptimizeForSize) ? 0 : 4;
1147 std::pair<const TargetRegisterClass*, uint8_t>
1148 X86TargetLowering::findRepresentativeClass(EVT VT) const{
1149 const TargetRegisterClass *RRC = 0;
1151 switch (VT.getSimpleVT().SimpleTy) {
1153 return TargetLowering::findRepresentativeClass(VT);
1154 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
1155 RRC = (Subtarget->is64Bit()
1156 ? X86::GR64RegisterClass : X86::GR32RegisterClass);
1159 RRC = X86::VR64RegisterClass;
1161 case MVT::f32: case MVT::f64:
1162 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
1163 case MVT::v4f32: case MVT::v2f64:
1164 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32:
1166 RRC = X86::VR128RegisterClass;
1169 return std::make_pair(RRC, Cost);
1173 X86TargetLowering::getRegPressureLimit(const TargetRegisterClass *RC,
1174 MachineFunction &MF) const {
1175 unsigned FPDiff = RegInfo->hasFP(MF) ? 1 : 0;
1176 switch (RC->getID()) {
1179 case X86::GR32RegClassID:
1181 case X86::GR64RegClassID:
1183 case X86::VR128RegClassID:
1184 return Subtarget->is64Bit() ? 10 : 4;
1185 case X86::VR64RegClassID:
1190 bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace,
1191 unsigned &Offset) const {
1192 if (!Subtarget->isTargetLinux())
1195 if (Subtarget->is64Bit()) {
1196 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs:
1198 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
1211 //===----------------------------------------------------------------------===//
1212 // Return Value Calling Convention Implementation
1213 //===----------------------------------------------------------------------===//
1215 #include "X86GenCallingConv.inc"
1218 X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv, bool isVarArg,
1219 const SmallVectorImpl<ISD::OutputArg> &Outs,
1220 LLVMContext &Context) const {
1221 SmallVector<CCValAssign, 16> RVLocs;
1222 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1224 return CCInfo.CheckReturn(Outs, RetCC_X86);
1228 X86TargetLowering::LowerReturn(SDValue Chain,
1229 CallingConv::ID CallConv, bool isVarArg,
1230 const SmallVectorImpl<ISD::OutputArg> &Outs,
1231 const SmallVectorImpl<SDValue> &OutVals,
1232 DebugLoc dl, SelectionDAG &DAG) const {
1233 MachineFunction &MF = DAG.getMachineFunction();
1234 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1236 SmallVector<CCValAssign, 16> RVLocs;
1237 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1238 RVLocs, *DAG.getContext());
1239 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
1241 // Add the regs to the liveout set for the function.
1242 MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
1243 for (unsigned i = 0; i != RVLocs.size(); ++i)
1244 if (RVLocs[i].isRegLoc() && !MRI.isLiveOut(RVLocs[i].getLocReg()))
1245 MRI.addLiveOut(RVLocs[i].getLocReg());
1249 SmallVector<SDValue, 6> RetOps;
1250 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
1251 // Operand #1 = Bytes To Pop
1252 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(),
1255 // Copy the result values into the output registers.
1256 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1257 CCValAssign &VA = RVLocs[i];
1258 assert(VA.isRegLoc() && "Can only return in registers!");
1259 SDValue ValToCopy = OutVals[i];
1260 EVT ValVT = ValToCopy.getValueType();
1262 // If this is x86-64, and we disabled SSE, we can't return FP values,
1263 // or SSE or MMX vectors.
1264 if ((ValVT == MVT::f32 || ValVT == MVT::f64 ||
1265 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) &&
1266 (Subtarget->is64Bit() && !Subtarget->hasSSE1())) {
1267 report_fatal_error("SSE register return with SSE disabled");
1269 // Likewise we can't return F64 values with SSE1 only. gcc does so, but
1270 // llvm-gcc has never done it right and no one has noticed, so this
1271 // should be OK for now.
1272 if (ValVT == MVT::f64 &&
1273 (Subtarget->is64Bit() && !Subtarget->hasSSE2()))
1274 report_fatal_error("SSE2 register return with SSE2 disabled");
1276 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
1277 // the RET instruction and handled by the FP Stackifier.
1278 if (VA.getLocReg() == X86::ST0 ||
1279 VA.getLocReg() == X86::ST1) {
1280 // If this is a copy from an xmm register to ST(0), use an FPExtend to
1281 // change the value to the FP stack register class.
1282 if (isScalarFPTypeInSSEReg(VA.getValVT()))
1283 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
1284 RetOps.push_back(ValToCopy);
1285 // Don't emit a copytoreg.
1289 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
1290 // which is returned in RAX / RDX.
1291 if (Subtarget->is64Bit()) {
1292 if (ValVT == MVT::x86mmx) {
1293 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
1294 ValToCopy = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i64, ValToCopy);
1295 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
1297 // If we don't have SSE2 available, convert to v4f32 so the generated
1298 // register is legal.
1299 if (!Subtarget->hasSSE2())
1300 ValToCopy = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v4f32,ValToCopy);
1305 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
1306 Flag = Chain.getValue(1);
1309 // The x86-64 ABI for returning structs by value requires that we copy
1310 // the sret argument into %rax for the return. We saved the argument into
1311 // a virtual register in the entry block, so now we copy the value out
1313 if (Subtarget->is64Bit() &&
1314 DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
1315 MachineFunction &MF = DAG.getMachineFunction();
1316 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1317 unsigned Reg = FuncInfo->getSRetReturnReg();
1319 "SRetReturnReg should have been set in LowerFormalArguments().");
1320 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
1322 Chain = DAG.getCopyToReg(Chain, dl, X86::RAX, Val, Flag);
1323 Flag = Chain.getValue(1);
1325 // RAX now acts like a return value.
1326 MRI.addLiveOut(X86::RAX);
1329 RetOps[0] = Chain; // Update chain.
1331 // Add the flag if we have it.
1333 RetOps.push_back(Flag);
1335 return DAG.getNode(X86ISD::RET_FLAG, dl,
1336 MVT::Other, &RetOps[0], RetOps.size());
1339 /// LowerCallResult - Lower the result values of a call into the
1340 /// appropriate copies out of appropriate physical registers.
1343 X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
1344 CallingConv::ID CallConv, bool isVarArg,
1345 const SmallVectorImpl<ISD::InputArg> &Ins,
1346 DebugLoc dl, SelectionDAG &DAG,
1347 SmallVectorImpl<SDValue> &InVals) const {
1349 // Assign locations to each value returned by this call.
1350 SmallVector<CCValAssign, 16> RVLocs;
1351 bool Is64Bit = Subtarget->is64Bit();
1352 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1353 RVLocs, *DAG.getContext());
1354 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
1356 // Copy all of the result registers out of their specified physreg.
1357 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1358 CCValAssign &VA = RVLocs[i];
1359 EVT CopyVT = VA.getValVT();
1361 // If this is x86-64, and we disabled SSE, we can't return FP values
1362 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
1363 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) {
1364 report_fatal_error("SSE register return with SSE disabled");
1369 // If this is a call to a function that returns an fp value on the floating
1370 // point stack, we must guarantee the the value is popped from the stack, so
1371 // a CopyFromReg is not good enough - the copy instruction may be eliminated
1372 // if the return value is not used. We use the FpGET_ST0 instructions
1374 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1) {
1375 // If we prefer to use the value in xmm registers, copy it out as f80 and
1376 // use a truncate to move it from fp stack reg to xmm reg.
1377 if (isScalarFPTypeInSSEReg(VA.getValVT())) CopyVT = MVT::f80;
1378 bool isST0 = VA.getLocReg() == X86::ST0;
1380 if (CopyVT == MVT::f32) Opc = isST0 ? X86::FpGET_ST0_32:X86::FpGET_ST1_32;
1381 if (CopyVT == MVT::f64) Opc = isST0 ? X86::FpGET_ST0_64:X86::FpGET_ST1_64;
1382 if (CopyVT == MVT::f80) Opc = isST0 ? X86::FpGET_ST0_80:X86::FpGET_ST1_80;
1383 SDValue Ops[] = { Chain, InFlag };
1384 Chain = SDValue(DAG.getMachineNode(Opc, dl, CopyVT, MVT::Other, MVT::Flag,
1386 Val = Chain.getValue(0);
1388 // Round the f80 to the right size, which also moves it to the appropriate
1390 if (CopyVT != VA.getValVT())
1391 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
1392 // This truncation won't change the value.
1393 DAG.getIntPtrConstant(1));
1394 } else if (Is64Bit && CopyVT.isVector() && CopyVT.getSizeInBits() == 64) {
1395 // For x86-64, MMX values are returned in XMM0 / XMM1 except for v1i64.
1396 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
1397 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
1398 MVT::v2i64, InFlag).getValue(1);
1399 Val = Chain.getValue(0);
1400 Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64,
1401 Val, DAG.getConstant(0, MVT::i64));
1403 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
1404 MVT::i64, InFlag).getValue(1);
1405 Val = Chain.getValue(0);
1407 Val = DAG.getNode(ISD::BIT_CONVERT, dl, CopyVT, Val);
1409 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
1410 CopyVT, InFlag).getValue(1);
1411 Val = Chain.getValue(0);
1413 InFlag = Chain.getValue(2);
1414 InVals.push_back(Val);
1421 //===----------------------------------------------------------------------===//
1422 // C & StdCall & Fast Calling Convention implementation
1423 //===----------------------------------------------------------------------===//
1424 // StdCall calling convention seems to be standard for many Windows' API
1425 // routines and around. It differs from C calling convention just a little:
1426 // callee should clean up the stack, not caller. Symbols should be also
1427 // decorated in some fancy way :) It doesn't support any vector arguments.
1428 // For info on fast calling convention see Fast Calling Convention (tail call)
1429 // implementation LowerX86_32FastCCCallTo.
1431 /// CallIsStructReturn - Determines whether a call uses struct return
1433 static bool CallIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
1437 return Outs[0].Flags.isSRet();
1440 /// ArgsAreStructReturn - Determines whether a function uses struct
1441 /// return semantics.
1443 ArgsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
1447 return Ins[0].Flags.isSRet();
1450 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
1451 /// by "Src" to address "Dst" with size and alignment information specified by
1452 /// the specific parameter attribute. The copy will be passed as a byval
1453 /// function parameter.
1455 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
1456 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
1458 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
1460 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
1461 /*isVolatile*/false, /*AlwaysInline=*/true,
1462 MachinePointerInfo(), MachinePointerInfo());
1465 /// IsTailCallConvention - Return true if the calling convention is one that
1466 /// supports tail call optimization.
1467 static bool IsTailCallConvention(CallingConv::ID CC) {
1468 return (CC == CallingConv::Fast || CC == CallingConv::GHC);
1471 /// FuncIsMadeTailCallSafe - Return true if the function is being made into
1472 /// a tailcall target by changing its ABI.
1473 static bool FuncIsMadeTailCallSafe(CallingConv::ID CC) {
1474 return GuaranteedTailCallOpt && IsTailCallConvention(CC);
1478 X86TargetLowering::LowerMemArgument(SDValue Chain,
1479 CallingConv::ID CallConv,
1480 const SmallVectorImpl<ISD::InputArg> &Ins,
1481 DebugLoc dl, SelectionDAG &DAG,
1482 const CCValAssign &VA,
1483 MachineFrameInfo *MFI,
1485 // Create the nodes corresponding to a load from this parameter slot.
1486 ISD::ArgFlagsTy Flags = Ins[i].Flags;
1487 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(CallConv);
1488 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
1491 // If value is passed by pointer we have address passed instead of the value
1493 if (VA.getLocInfo() == CCValAssign::Indirect)
1494 ValVT = VA.getLocVT();
1496 ValVT = VA.getValVT();
1498 // FIXME: For now, all byval parameter objects are marked mutable. This can be
1499 // changed with more analysis.
1500 // In case of tail call optimization mark all arguments mutable. Since they
1501 // could be overwritten by lowering of arguments in case of a tail call.
1502 if (Flags.isByVal()) {
1503 int FI = MFI->CreateFixedObject(Flags.getByValSize(),
1504 VA.getLocMemOffset(), isImmutable);
1505 return DAG.getFrameIndex(FI, getPointerTy());
1507 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
1508 VA.getLocMemOffset(), isImmutable);
1509 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
1510 return DAG.getLoad(ValVT, dl, Chain, FIN,
1511 MachinePointerInfo::getFixedStack(FI),
1517 X86TargetLowering::LowerFormalArguments(SDValue Chain,
1518 CallingConv::ID CallConv,
1520 const SmallVectorImpl<ISD::InputArg> &Ins,
1523 SmallVectorImpl<SDValue> &InVals)
1525 MachineFunction &MF = DAG.getMachineFunction();
1526 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1528 const Function* Fn = MF.getFunction();
1529 if (Fn->hasExternalLinkage() &&
1530 Subtarget->isTargetCygMing() &&
1531 Fn->getName() == "main")
1532 FuncInfo->setForceFramePointer(true);
1534 MachineFrameInfo *MFI = MF.getFrameInfo();
1535 bool Is64Bit = Subtarget->is64Bit();
1536 bool IsWin64 = Subtarget->isTargetWin64();
1538 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
1539 "Var args not supported with calling convention fastcc or ghc");
1541 // Assign locations to all of the incoming arguments.
1542 SmallVector<CCValAssign, 16> ArgLocs;
1543 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1544 ArgLocs, *DAG.getContext());
1545 CCInfo.AnalyzeFormalArguments(Ins, CC_X86);
1547 unsigned LastVal = ~0U;
1549 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1550 CCValAssign &VA = ArgLocs[i];
1551 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
1553 assert(VA.getValNo() != LastVal &&
1554 "Don't support value assigned to multiple locs yet");
1555 LastVal = VA.getValNo();
1557 if (VA.isRegLoc()) {
1558 EVT RegVT = VA.getLocVT();
1559 TargetRegisterClass *RC = NULL;
1560 if (RegVT == MVT::i32)
1561 RC = X86::GR32RegisterClass;
1562 else if (Is64Bit && RegVT == MVT::i64)
1563 RC = X86::GR64RegisterClass;
1564 else if (RegVT == MVT::f32)
1565 RC = X86::FR32RegisterClass;
1566 else if (RegVT == MVT::f64)
1567 RC = X86::FR64RegisterClass;
1568 else if (RegVT.isVector() && RegVT.getSizeInBits() == 256)
1569 RC = X86::VR256RegisterClass;
1570 else if (RegVT.isVector() && RegVT.getSizeInBits() == 128)
1571 RC = X86::VR128RegisterClass;
1572 else if (RegVT == MVT::x86mmx)
1573 RC = X86::VR64RegisterClass;
1575 llvm_unreachable("Unknown argument type!");
1577 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
1578 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
1580 // If this is an 8 or 16-bit value, it is really passed promoted to 32
1581 // bits. Insert an assert[sz]ext to capture this, then truncate to the
1583 if (VA.getLocInfo() == CCValAssign::SExt)
1584 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
1585 DAG.getValueType(VA.getValVT()));
1586 else if (VA.getLocInfo() == CCValAssign::ZExt)
1587 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
1588 DAG.getValueType(VA.getValVT()));
1589 else if (VA.getLocInfo() == CCValAssign::BCvt)
1590 ArgValue = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getValVT(), ArgValue);
1592 if (VA.isExtInLoc()) {
1593 // Handle MMX values passed in XMM regs.
1594 if (RegVT.isVector()) {
1595 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(),
1598 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
1601 assert(VA.isMemLoc());
1602 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
1605 // If value is passed via pointer - do a load.
1606 if (VA.getLocInfo() == CCValAssign::Indirect)
1607 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue,
1608 MachinePointerInfo(), false, false, 0);
1610 InVals.push_back(ArgValue);
1613 // The x86-64 ABI for returning structs by value requires that we copy
1614 // the sret argument into %rax for the return. Save the argument into
1615 // a virtual register so that we can access it from the return points.
1616 if (Is64Bit && MF.getFunction()->hasStructRetAttr()) {
1617 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1618 unsigned Reg = FuncInfo->getSRetReturnReg();
1620 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64));
1621 FuncInfo->setSRetReturnReg(Reg);
1623 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]);
1624 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
1627 unsigned StackSize = CCInfo.getNextStackOffset();
1628 // Align stack specially for tail calls.
1629 if (FuncIsMadeTailCallSafe(CallConv))
1630 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
1632 // If the function takes variable number of arguments, make a frame index for
1633 // the start of the first vararg value... for expansion of llvm.va_start.
1635 if (!IsWin64 && (Is64Bit || (CallConv != CallingConv::X86_FastCall &&
1636 CallConv != CallingConv::X86_ThisCall))) {
1637 FuncInfo->setVarArgsFrameIndex(MFI->CreateFixedObject(1, StackSize,true));
1640 unsigned TotalNumIntRegs = 0, TotalNumXMMRegs = 0;
1642 // FIXME: We should really autogenerate these arrays
1643 static const unsigned GPR64ArgRegsWin64[] = {
1644 X86::RCX, X86::RDX, X86::R8, X86::R9
1646 static const unsigned GPR64ArgRegs64Bit[] = {
1647 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
1649 static const unsigned XMMArgRegs64Bit[] = {
1650 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
1651 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
1653 const unsigned *GPR64ArgRegs;
1654 unsigned NumXMMRegs = 0;
1657 // The XMM registers which might contain var arg parameters are shadowed
1658 // in their paired GPR. So we only need to save the GPR to their home
1660 TotalNumIntRegs = 4;
1661 GPR64ArgRegs = GPR64ArgRegsWin64;
1663 TotalNumIntRegs = 6; TotalNumXMMRegs = 8;
1664 GPR64ArgRegs = GPR64ArgRegs64Bit;
1666 NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs64Bit, TotalNumXMMRegs);
1668 unsigned NumIntRegs = CCInfo.getFirstUnallocated(GPR64ArgRegs,
1671 bool NoImplicitFloatOps = Fn->hasFnAttr(Attribute::NoImplicitFloat);
1672 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) &&
1673 "SSE register cannot be used when SSE is disabled!");
1674 assert(!(NumXMMRegs && UseSoftFloat && NoImplicitFloatOps) &&
1675 "SSE register cannot be used when SSE is disabled!");
1676 if (UseSoftFloat || NoImplicitFloatOps || !Subtarget->hasSSE1())
1677 // Kernel mode asks for SSE to be disabled, so don't push them
1679 TotalNumXMMRegs = 0;
1682 const TargetFrameInfo &TFI = *getTargetMachine().getFrameInfo();
1683 // Get to the caller-allocated home save location. Add 8 to account
1684 // for the return address.
1685 int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
1686 FuncInfo->setRegSaveFrameIndex(
1687 MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false));
1688 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex());
1690 // For X86-64, if there are vararg parameters that are passed via
1691 // registers, then we must store them to their spots on the stack so they
1692 // may be loaded by deferencing the result of va_next.
1693 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8);
1694 FuncInfo->setVarArgsFPOffset(TotalNumIntRegs * 8 + NumXMMRegs * 16);
1695 FuncInfo->setRegSaveFrameIndex(
1696 MFI->CreateStackObject(TotalNumIntRegs * 8 + TotalNumXMMRegs * 16, 16,
1700 // Store the integer parameter registers.
1701 SmallVector<SDValue, 8> MemOps;
1702 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
1704 unsigned Offset = FuncInfo->getVarArgsGPOffset();
1705 for (; NumIntRegs != TotalNumIntRegs; ++NumIntRegs) {
1706 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN,
1707 DAG.getIntPtrConstant(Offset));
1708 unsigned VReg = MF.addLiveIn(GPR64ArgRegs[NumIntRegs],
1709 X86::GR64RegisterClass);
1710 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
1712 DAG.getStore(Val.getValue(1), dl, Val, FIN,
1713 MachinePointerInfo::getFixedStack(
1714 FuncInfo->getRegSaveFrameIndex(), Offset),
1716 MemOps.push_back(Store);
1720 if (TotalNumXMMRegs != 0 && NumXMMRegs != TotalNumXMMRegs) {
1721 // Now store the XMM (fp + vector) parameter registers.
1722 SmallVector<SDValue, 11> SaveXMMOps;
1723 SaveXMMOps.push_back(Chain);
1725 unsigned AL = MF.addLiveIn(X86::AL, X86::GR8RegisterClass);
1726 SDValue ALVal = DAG.getCopyFromReg(DAG.getEntryNode(), dl, AL, MVT::i8);
1727 SaveXMMOps.push_back(ALVal);
1729 SaveXMMOps.push_back(DAG.getIntPtrConstant(
1730 FuncInfo->getRegSaveFrameIndex()));
1731 SaveXMMOps.push_back(DAG.getIntPtrConstant(
1732 FuncInfo->getVarArgsFPOffset()));
1734 for (; NumXMMRegs != TotalNumXMMRegs; ++NumXMMRegs) {
1735 unsigned VReg = MF.addLiveIn(XMMArgRegs64Bit[NumXMMRegs],
1736 X86::VR128RegisterClass);
1737 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::v4f32);
1738 SaveXMMOps.push_back(Val);
1740 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
1742 &SaveXMMOps[0], SaveXMMOps.size()));
1745 if (!MemOps.empty())
1746 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1747 &MemOps[0], MemOps.size());
1751 // Some CCs need callee pop.
1752 if (Subtarget->IsCalleePop(isVarArg, CallConv)) {
1753 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything.
1755 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing.
1756 // If this is an sret function, the return should pop the hidden pointer.
1757 if (!Is64Bit && !IsTailCallConvention(CallConv) && ArgsAreStructReturn(Ins))
1758 FuncInfo->setBytesToPopOnReturn(4);
1762 // RegSaveFrameIndex is X86-64 only.
1763 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
1764 if (CallConv == CallingConv::X86_FastCall ||
1765 CallConv == CallingConv::X86_ThisCall)
1766 // fastcc functions can't have varargs.
1767 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA);
1774 X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
1775 SDValue StackPtr, SDValue Arg,
1776 DebugLoc dl, SelectionDAG &DAG,
1777 const CCValAssign &VA,
1778 ISD::ArgFlagsTy Flags) const {
1779 const unsigned FirstStackArgOffset = (Subtarget->isTargetWin64() ? 32 : 0);
1780 unsigned LocMemOffset = FirstStackArgOffset + VA.getLocMemOffset();
1781 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
1782 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
1783 if (Flags.isByVal())
1784 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
1786 return DAG.getStore(Chain, dl, Arg, PtrOff,
1787 MachinePointerInfo::getStack(LocMemOffset),
1791 /// EmitTailCallLoadRetAddr - Emit a load of return address if tail call
1792 /// optimization is performed and it is required.
1794 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
1795 SDValue &OutRetAddr, SDValue Chain,
1796 bool IsTailCall, bool Is64Bit,
1797 int FPDiff, DebugLoc dl) const {
1798 // Adjust the Return address stack slot.
1799 EVT VT = getPointerTy();
1800 OutRetAddr = getReturnAddressFrameIndex(DAG);
1802 // Load the "old" Return address.
1803 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(),
1805 return SDValue(OutRetAddr.getNode(), 1);
1808 /// EmitTailCallStoreRetAddr - Emit a store of the return adress if tail call
1809 /// optimization is performed and it is required (FPDiff!=0).
1811 EmitTailCallStoreRetAddr(SelectionDAG & DAG, MachineFunction &MF,
1812 SDValue Chain, SDValue RetAddrFrIdx,
1813 bool Is64Bit, int FPDiff, DebugLoc dl) {
1814 // Store the return address to the appropriate stack slot.
1815 if (!FPDiff) return Chain;
1816 // Calculate the new stack slot for the return address.
1817 int SlotSize = Is64Bit ? 8 : 4;
1818 int NewReturnAddrFI =
1819 MF.getFrameInfo()->CreateFixedObject(SlotSize, FPDiff-SlotSize, false);
1820 EVT VT = Is64Bit ? MVT::i64 : MVT::i32;
1821 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, VT);
1822 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
1823 MachinePointerInfo::getFixedStack(NewReturnAddrFI),
1829 X86TargetLowering::LowerCall(SDValue Chain, SDValue Callee,
1830 CallingConv::ID CallConv, bool isVarArg,
1832 const SmallVectorImpl<ISD::OutputArg> &Outs,
1833 const SmallVectorImpl<SDValue> &OutVals,
1834 const SmallVectorImpl<ISD::InputArg> &Ins,
1835 DebugLoc dl, SelectionDAG &DAG,
1836 SmallVectorImpl<SDValue> &InVals) const {
1837 MachineFunction &MF = DAG.getMachineFunction();
1838 bool Is64Bit = Subtarget->is64Bit();
1839 bool IsStructRet = CallIsStructReturn(Outs);
1840 bool IsSibcall = false;
1843 // Check if it's really possible to do a tail call.
1844 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
1845 isVarArg, IsStructRet, MF.getFunction()->hasStructRetAttr(),
1846 Outs, OutVals, Ins, DAG);
1848 // Sibcalls are automatically detected tailcalls which do not require
1850 if (!GuaranteedTailCallOpt && isTailCall)
1857 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
1858 "Var args not supported with calling convention fastcc or ghc");
1860 // Analyze operands of the call, assigning locations to each operand.
1861 SmallVector<CCValAssign, 16> ArgLocs;
1862 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1863 ArgLocs, *DAG.getContext());
1864 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
1866 // Get a count of how many bytes are to be pushed on the stack.
1867 unsigned NumBytes = CCInfo.getNextStackOffset();
1869 // This is a sibcall. The memory operands are available in caller's
1870 // own caller's stack.
1872 else if (GuaranteedTailCallOpt && IsTailCallConvention(CallConv))
1873 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
1876 if (isTailCall && !IsSibcall) {
1877 // Lower arguments at fp - stackoffset + fpdiff.
1878 unsigned NumBytesCallerPushed =
1879 MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn();
1880 FPDiff = NumBytesCallerPushed - NumBytes;
1882 // Set the delta of movement of the returnaddr stackslot.
1883 // But only set if delta is greater than previous delta.
1884 if (FPDiff < (MF.getInfo<X86MachineFunctionInfo>()->getTCReturnAddrDelta()))
1885 MF.getInfo<X86MachineFunctionInfo>()->setTCReturnAddrDelta(FPDiff);
1889 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
1891 SDValue RetAddrFrIdx;
1892 // Load return adress for tail calls.
1893 if (isTailCall && FPDiff)
1894 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall,
1895 Is64Bit, FPDiff, dl);
1897 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
1898 SmallVector<SDValue, 8> MemOpChains;
1901 // Walk the register/memloc assignments, inserting copies/loads. In the case
1902 // of tail call optimization arguments are handle later.
1903 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1904 CCValAssign &VA = ArgLocs[i];
1905 EVT RegVT = VA.getLocVT();
1906 SDValue Arg = OutVals[i];
1907 ISD::ArgFlagsTy Flags = Outs[i].Flags;
1908 bool isByVal = Flags.isByVal();
1910 // Promote the value if needed.
1911 switch (VA.getLocInfo()) {
1912 default: llvm_unreachable("Unknown loc info!");
1913 case CCValAssign::Full: break;
1914 case CCValAssign::SExt:
1915 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
1917 case CCValAssign::ZExt:
1918 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
1920 case CCValAssign::AExt:
1921 if (RegVT.isVector() && RegVT.getSizeInBits() == 128) {
1922 // Special case: passing MMX values in XMM registers.
1923 Arg = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i64, Arg);
1924 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
1925 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
1927 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
1929 case CCValAssign::BCvt:
1930 Arg = DAG.getNode(ISD::BIT_CONVERT, dl, RegVT, Arg);
1932 case CCValAssign::Indirect: {
1933 // Store the argument.
1934 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
1935 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
1936 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot,
1937 MachinePointerInfo::getFixedStack(FI),
1944 if (VA.isRegLoc()) {
1945 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
1946 if (isVarArg && Subtarget->isTargetWin64()) {
1947 // Win64 ABI requires argument XMM reg to be copied to the corresponding
1948 // shadow reg if callee is a varargs function.
1949 unsigned ShadowReg = 0;
1950 switch (VA.getLocReg()) {
1951 case X86::XMM0: ShadowReg = X86::RCX; break;
1952 case X86::XMM1: ShadowReg = X86::RDX; break;
1953 case X86::XMM2: ShadowReg = X86::R8; break;
1954 case X86::XMM3: ShadowReg = X86::R9; break;
1957 RegsToPass.push_back(std::make_pair(ShadowReg, Arg));
1959 } else if (!IsSibcall && (!isTailCall || isByVal)) {
1960 assert(VA.isMemLoc());
1961 if (StackPtr.getNode() == 0)
1962 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr, getPointerTy());
1963 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
1964 dl, DAG, VA, Flags));
1968 if (!MemOpChains.empty())
1969 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1970 &MemOpChains[0], MemOpChains.size());
1972 // Build a sequence of copy-to-reg nodes chained together with token chain
1973 // and flag operands which copy the outgoing args into registers.
1975 // Tail call byval lowering might overwrite argument registers so in case of
1976 // tail call optimization the copies to registers are lowered later.
1978 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1979 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
1980 RegsToPass[i].second, InFlag);
1981 InFlag = Chain.getValue(1);
1984 if (Subtarget->isPICStyleGOT()) {
1985 // ELF / PIC requires GOT in the EBX register before function calls via PLT
1988 Chain = DAG.getCopyToReg(Chain, dl, X86::EBX,
1989 DAG.getNode(X86ISD::GlobalBaseReg,
1990 DebugLoc(), getPointerTy()),
1992 InFlag = Chain.getValue(1);
1994 // If we are tail calling and generating PIC/GOT style code load the
1995 // address of the callee into ECX. The value in ecx is used as target of
1996 // the tail jump. This is done to circumvent the ebx/callee-saved problem
1997 // for tail calls on PIC/GOT architectures. Normally we would just put the
1998 // address of GOT into ebx and then call target@PLT. But for tail calls
1999 // ebx would be restored (since ebx is callee saved) before jumping to the
2002 // Note: The actual moving to ECX is done further down.
2003 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
2004 if (G && !G->getGlobal()->hasHiddenVisibility() &&
2005 !G->getGlobal()->hasProtectedVisibility())
2006 Callee = LowerGlobalAddress(Callee, DAG);
2007 else if (isa<ExternalSymbolSDNode>(Callee))
2008 Callee = LowerExternalSymbol(Callee, DAG);
2012 if (Is64Bit && isVarArg && !Subtarget->isTargetWin64()) {
2013 // From AMD64 ABI document:
2014 // For calls that may call functions that use varargs or stdargs
2015 // (prototype-less calls or calls to functions containing ellipsis (...) in
2016 // the declaration) %al is used as hidden argument to specify the number
2017 // of SSE registers used. The contents of %al do not need to match exactly
2018 // the number of registers, but must be an ubound on the number of SSE
2019 // registers used and is in the range 0 - 8 inclusive.
2021 // Count the number of XMM registers allocated.
2022 static const unsigned XMMArgRegs[] = {
2023 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2024 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2026 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
2027 assert((Subtarget->hasSSE1() || !NumXMMRegs)
2028 && "SSE registers cannot be used when SSE is disabled");
2030 Chain = DAG.getCopyToReg(Chain, dl, X86::AL,
2031 DAG.getConstant(NumXMMRegs, MVT::i8), InFlag);
2032 InFlag = Chain.getValue(1);
2036 // For tail calls lower the arguments to the 'real' stack slot.
2038 // Force all the incoming stack arguments to be loaded from the stack
2039 // before any new outgoing arguments are stored to the stack, because the
2040 // outgoing stack slots may alias the incoming argument stack slots, and
2041 // the alias isn't otherwise explicit. This is slightly more conservative
2042 // than necessary, because it means that each store effectively depends
2043 // on every argument instead of just those arguments it would clobber.
2044 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
2046 SmallVector<SDValue, 8> MemOpChains2;
2049 // Do not flag preceeding copytoreg stuff together with the following stuff.
2051 if (GuaranteedTailCallOpt) {
2052 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2053 CCValAssign &VA = ArgLocs[i];
2056 assert(VA.isMemLoc());
2057 SDValue Arg = OutVals[i];
2058 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2059 // Create frame index.
2060 int32_t Offset = VA.getLocMemOffset()+FPDiff;
2061 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
2062 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
2063 FIN = DAG.getFrameIndex(FI, getPointerTy());
2065 if (Flags.isByVal()) {
2066 // Copy relative to framepointer.
2067 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset());
2068 if (StackPtr.getNode() == 0)
2069 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr,
2071 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source);
2073 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
2077 // Store relative to framepointer.
2078 MemOpChains2.push_back(
2079 DAG.getStore(ArgChain, dl, Arg, FIN,
2080 MachinePointerInfo::getFixedStack(FI),
2086 if (!MemOpChains2.empty())
2087 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2088 &MemOpChains2[0], MemOpChains2.size());
2090 // Copy arguments to their registers.
2091 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2092 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
2093 RegsToPass[i].second, InFlag);
2094 InFlag = Chain.getValue(1);
2098 // Store the return address to the appropriate stack slot.
2099 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx, Is64Bit,
2103 if (getTargetMachine().getCodeModel() == CodeModel::Large) {
2104 assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
2105 // In the 64-bit large code model, we have to make all calls
2106 // through a register, since the call instruction's 32-bit
2107 // pc-relative offset may not be large enough to hold the whole
2109 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2110 // If the callee is a GlobalAddress node (quite common, every direct call
2111 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
2114 // We should use extra load for direct calls to dllimported functions in
2116 const GlobalValue *GV = G->getGlobal();
2117 if (!GV->hasDLLImportLinkage()) {
2118 unsigned char OpFlags = 0;
2120 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
2121 // external symbols most go through the PLT in PIC mode. If the symbol
2122 // has hidden or protected visibility, or if it is static or local, then
2123 // we don't need to use the PLT - we can directly call it.
2124 if (Subtarget->isTargetELF() &&
2125 getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
2126 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
2127 OpFlags = X86II::MO_PLT;
2128 } else if (Subtarget->isPICStyleStubAny() &&
2129 (GV->isDeclaration() || GV->isWeakForLinker()) &&
2130 Subtarget->getDarwinVers() < 9) {
2131 // PC-relative references to external symbols should go through $stub,
2132 // unless we're building with the leopard linker or later, which
2133 // automatically synthesizes these stubs.
2134 OpFlags = X86II::MO_DARWIN_STUB;
2137 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(),
2138 G->getOffset(), OpFlags);
2140 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
2141 unsigned char OpFlags = 0;
2143 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to external
2144 // symbols should go through the PLT.
2145 if (Subtarget->isTargetELF() &&
2146 getTargetMachine().getRelocationModel() == Reloc::PIC_) {
2147 OpFlags = X86II::MO_PLT;
2148 } else if (Subtarget->isPICStyleStubAny() &&
2149 Subtarget->getDarwinVers() < 9) {
2150 // PC-relative references to external symbols should go through $stub,
2151 // unless we're building with the leopard linker or later, which
2152 // automatically synthesizes these stubs.
2153 OpFlags = X86II::MO_DARWIN_STUB;
2156 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(),
2160 // Returns a chain & a flag for retval copy to use.
2161 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
2162 SmallVector<SDValue, 8> Ops;
2164 if (!IsSibcall && isTailCall) {
2165 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
2166 DAG.getIntPtrConstant(0, true), InFlag);
2167 InFlag = Chain.getValue(1);
2170 Ops.push_back(Chain);
2171 Ops.push_back(Callee);
2174 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32));
2176 // Add argument registers to the end of the list so that they are known live
2178 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
2179 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
2180 RegsToPass[i].second.getValueType()));
2182 // Add an implicit use GOT pointer in EBX.
2183 if (!isTailCall && Subtarget->isPICStyleGOT())
2184 Ops.push_back(DAG.getRegister(X86::EBX, getPointerTy()));
2186 // Add an implicit use of AL for non-Windows x86 64-bit vararg functions.
2187 if (Is64Bit && isVarArg && !Subtarget->isTargetWin64())
2188 Ops.push_back(DAG.getRegister(X86::AL, MVT::i8));
2190 if (InFlag.getNode())
2191 Ops.push_back(InFlag);
2195 //// If this is the first return lowered for this function, add the regs
2196 //// to the liveout set for the function.
2197 // This isn't right, although it's probably harmless on x86; liveouts
2198 // should be computed from returns not tail calls. Consider a void
2199 // function making a tail call to a function returning int.
2200 return DAG.getNode(X86ISD::TC_RETURN, dl,
2201 NodeTys, &Ops[0], Ops.size());
2204 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, &Ops[0], Ops.size());
2205 InFlag = Chain.getValue(1);
2207 // Create the CALLSEQ_END node.
2208 unsigned NumBytesForCalleeToPush;
2209 if (Subtarget->IsCalleePop(isVarArg, CallConv))
2210 NumBytesForCalleeToPush = NumBytes; // Callee pops everything
2211 else if (!Is64Bit && !IsTailCallConvention(CallConv) && IsStructRet)
2212 // If this is a call to a struct-return function, the callee
2213 // pops the hidden struct pointer, so we have to push it back.
2214 // This is common for Darwin/X86, Linux & Mingw32 targets.
2215 NumBytesForCalleeToPush = 4;
2217 NumBytesForCalleeToPush = 0; // Callee pops nothing.
2219 // Returns a flag for retval copy to use.
2221 Chain = DAG.getCALLSEQ_END(Chain,
2222 DAG.getIntPtrConstant(NumBytes, true),
2223 DAG.getIntPtrConstant(NumBytesForCalleeToPush,
2226 InFlag = Chain.getValue(1);
2229 // Handle result values, copying them out of physregs into vregs that we
2231 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
2232 Ins, dl, DAG, InVals);
2236 //===----------------------------------------------------------------------===//
2237 // Fast Calling Convention (tail call) implementation
2238 //===----------------------------------------------------------------------===//
2240 // Like std call, callee cleans arguments, convention except that ECX is
2241 // reserved for storing the tail called function address. Only 2 registers are
2242 // free for argument passing (inreg). Tail call optimization is performed
2244 // * tailcallopt is enabled
2245 // * caller/callee are fastcc
2246 // On X86_64 architecture with GOT-style position independent code only local
2247 // (within module) calls are supported at the moment.
2248 // To keep the stack aligned according to platform abi the function
2249 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
2250 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
2251 // If a tail called function callee has more arguments than the caller the
2252 // caller needs to make sure that there is room to move the RETADDR to. This is
2253 // achieved by reserving an area the size of the argument delta right after the
2254 // original REtADDR, but before the saved framepointer or the spilled registers
2255 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
2267 /// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned
2268 /// for a 16 byte align requirement.
2270 X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
2271 SelectionDAG& DAG) const {
2272 MachineFunction &MF = DAG.getMachineFunction();
2273 const TargetMachine &TM = MF.getTarget();
2274 const TargetFrameInfo &TFI = *TM.getFrameInfo();
2275 unsigned StackAlignment = TFI.getStackAlignment();
2276 uint64_t AlignMask = StackAlignment - 1;
2277 int64_t Offset = StackSize;
2278 uint64_t SlotSize = TD->getPointerSize();
2279 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
2280 // Number smaller than 12 so just add the difference.
2281 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
2283 // Mask out lower bits, add stackalignment once plus the 12 bytes.
2284 Offset = ((~AlignMask) & Offset) + StackAlignment +
2285 (StackAlignment-SlotSize);
2290 /// MatchingStackOffset - Return true if the given stack call argument is
2291 /// already available in the same position (relatively) of the caller's
2292 /// incoming argument stack.
2294 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
2295 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
2296 const X86InstrInfo *TII) {
2297 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
2299 if (Arg.getOpcode() == ISD::CopyFromReg) {
2300 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
2301 if (!VR || TargetRegisterInfo::isPhysicalRegister(VR))
2303 MachineInstr *Def = MRI->getVRegDef(VR);
2306 if (!Flags.isByVal()) {
2307 if (!TII->isLoadFromStackSlot(Def, FI))
2310 unsigned Opcode = Def->getOpcode();
2311 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r) &&
2312 Def->getOperand(1).isFI()) {
2313 FI = Def->getOperand(1).getIndex();
2314 Bytes = Flags.getByValSize();
2318 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
2319 if (Flags.isByVal())
2320 // ByVal argument is passed in as a pointer but it's now being
2321 // dereferenced. e.g.
2322 // define @foo(%struct.X* %A) {
2323 // tail call @bar(%struct.X* byval %A)
2326 SDValue Ptr = Ld->getBasePtr();
2327 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
2330 FI = FINode->getIndex();
2334 assert(FI != INT_MAX);
2335 if (!MFI->isFixedObjectIndex(FI))
2337 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
2340 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
2341 /// for tail call optimization. Targets which want to do tail call
2342 /// optimization should implement this function.
2344 X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
2345 CallingConv::ID CalleeCC,
2347 bool isCalleeStructRet,
2348 bool isCallerStructRet,
2349 const SmallVectorImpl<ISD::OutputArg> &Outs,
2350 const SmallVectorImpl<SDValue> &OutVals,
2351 const SmallVectorImpl<ISD::InputArg> &Ins,
2352 SelectionDAG& DAG) const {
2353 if (!IsTailCallConvention(CalleeCC) &&
2354 CalleeCC != CallingConv::C)
2357 // If -tailcallopt is specified, make fastcc functions tail-callable.
2358 const MachineFunction &MF = DAG.getMachineFunction();
2359 const Function *CallerF = DAG.getMachineFunction().getFunction();
2360 CallingConv::ID CallerCC = CallerF->getCallingConv();
2361 bool CCMatch = CallerCC == CalleeCC;
2363 if (GuaranteedTailCallOpt) {
2364 if (IsTailCallConvention(CalleeCC) && CCMatch)
2369 // Look for obvious safe cases to perform tail call optimization that do not
2370 // require ABI changes. This is what gcc calls sibcall.
2372 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
2373 // emit a special epilogue.
2374 if (RegInfo->needsStackRealignment(MF))
2377 // Do not sibcall optimize vararg calls unless the call site is not passing
2379 if (isVarArg && !Outs.empty())
2382 // Also avoid sibcall optimization if either caller or callee uses struct
2383 // return semantics.
2384 if (isCalleeStructRet || isCallerStructRet)
2387 // If the call result is in ST0 / ST1, it needs to be popped off the x87 stack.
2388 // Therefore if it's not used by the call it is not safe to optimize this into
2390 bool Unused = false;
2391 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
2398 SmallVector<CCValAssign, 16> RVLocs;
2399 CCState CCInfo(CalleeCC, false, getTargetMachine(),
2400 RVLocs, *DAG.getContext());
2401 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
2402 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
2403 CCValAssign &VA = RVLocs[i];
2404 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1)
2409 // If the calling conventions do not match, then we'd better make sure the
2410 // results are returned in the same way as what the caller expects.
2412 SmallVector<CCValAssign, 16> RVLocs1;
2413 CCState CCInfo1(CalleeCC, false, getTargetMachine(),
2414 RVLocs1, *DAG.getContext());
2415 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86);
2417 SmallVector<CCValAssign, 16> RVLocs2;
2418 CCState CCInfo2(CallerCC, false, getTargetMachine(),
2419 RVLocs2, *DAG.getContext());
2420 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86);
2422 if (RVLocs1.size() != RVLocs2.size())
2424 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
2425 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
2427 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
2429 if (RVLocs1[i].isRegLoc()) {
2430 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
2433 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
2439 // If the callee takes no arguments then go on to check the results of the
2441 if (!Outs.empty()) {
2442 // Check if stack adjustment is needed. For now, do not do this if any
2443 // argument is passed on the stack.
2444 SmallVector<CCValAssign, 16> ArgLocs;
2445 CCState CCInfo(CalleeCC, isVarArg, getTargetMachine(),
2446 ArgLocs, *DAG.getContext());
2447 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2448 if (CCInfo.getNextStackOffset()) {
2449 MachineFunction &MF = DAG.getMachineFunction();
2450 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn())
2452 if (Subtarget->isTargetWin64())
2453 // Win64 ABI has additional complications.
2456 // Check if the arguments are already laid out in the right way as
2457 // the caller's fixed stack objects.
2458 MachineFrameInfo *MFI = MF.getFrameInfo();
2459 const MachineRegisterInfo *MRI = &MF.getRegInfo();
2460 const X86InstrInfo *TII =
2461 ((X86TargetMachine&)getTargetMachine()).getInstrInfo();
2462 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2463 CCValAssign &VA = ArgLocs[i];
2464 SDValue Arg = OutVals[i];
2465 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2466 if (VA.getLocInfo() == CCValAssign::Indirect)
2468 if (!VA.isRegLoc()) {
2469 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
2476 // If the tailcall address may be in a register, then make sure it's
2477 // possible to register allocate for it. In 32-bit, the call address can
2478 // only target EAX, EDX, or ECX since the tail call must be scheduled after
2479 // callee-saved registers are restored. These happen to be the same
2480 // registers used to pass 'inreg' arguments so watch out for those.
2481 if (!Subtarget->is64Bit() &&
2482 !isa<GlobalAddressSDNode>(Callee) &&
2483 !isa<ExternalSymbolSDNode>(Callee)) {
2484 unsigned NumInRegs = 0;
2485 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2486 CCValAssign &VA = ArgLocs[i];
2489 unsigned Reg = VA.getLocReg();
2492 case X86::EAX: case X86::EDX: case X86::ECX:
2493 if (++NumInRegs == 3)
2501 // An stdcall caller is expected to clean up its arguments; the callee
2502 // isn't going to do that.
2503 if (!CCMatch && CallerCC==CallingConv::X86_StdCall)
2510 X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo) const {
2511 return X86::createFastISel(funcInfo);
2515 //===----------------------------------------------------------------------===//
2516 // Other Lowering Hooks
2517 //===----------------------------------------------------------------------===//
2519 static bool MayFoldLoad(SDValue Op) {
2520 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode());
2523 static bool MayFoldIntoStore(SDValue Op) {
2524 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin());
2527 static bool isTargetShuffle(unsigned Opcode) {
2529 default: return false;
2530 case X86ISD::PSHUFD:
2531 case X86ISD::PSHUFHW:
2532 case X86ISD::PSHUFLW:
2533 case X86ISD::SHUFPD:
2534 case X86ISD::PALIGN:
2535 case X86ISD::SHUFPS:
2536 case X86ISD::MOVLHPS:
2537 case X86ISD::MOVLHPD:
2538 case X86ISD::MOVHLPS:
2539 case X86ISD::MOVLPS:
2540 case X86ISD::MOVLPD:
2541 case X86ISD::MOVSHDUP:
2542 case X86ISD::MOVSLDUP:
2543 case X86ISD::MOVDDUP:
2546 case X86ISD::UNPCKLPS:
2547 case X86ISD::UNPCKLPD:
2548 case X86ISD::PUNPCKLWD:
2549 case X86ISD::PUNPCKLBW:
2550 case X86ISD::PUNPCKLDQ:
2551 case X86ISD::PUNPCKLQDQ:
2552 case X86ISD::UNPCKHPS:
2553 case X86ISD::UNPCKHPD:
2554 case X86ISD::PUNPCKHWD:
2555 case X86ISD::PUNPCKHBW:
2556 case X86ISD::PUNPCKHDQ:
2557 case X86ISD::PUNPCKHQDQ:
2563 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
2564 SDValue V1, SelectionDAG &DAG) {
2566 default: llvm_unreachable("Unknown x86 shuffle node");
2567 case X86ISD::MOVSHDUP:
2568 case X86ISD::MOVSLDUP:
2569 case X86ISD::MOVDDUP:
2570 return DAG.getNode(Opc, dl, VT, V1);
2576 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
2577 SDValue V1, unsigned TargetMask, SelectionDAG &DAG) {
2579 default: llvm_unreachable("Unknown x86 shuffle node");
2580 case X86ISD::PSHUFD:
2581 case X86ISD::PSHUFHW:
2582 case X86ISD::PSHUFLW:
2583 return DAG.getNode(Opc, dl, VT, V1, DAG.getConstant(TargetMask, MVT::i8));
2589 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
2590 SDValue V1, SDValue V2, unsigned TargetMask, SelectionDAG &DAG) {
2592 default: llvm_unreachable("Unknown x86 shuffle node");
2593 case X86ISD::PALIGN:
2594 case X86ISD::SHUFPD:
2595 case X86ISD::SHUFPS:
2596 return DAG.getNode(Opc, dl, VT, V1, V2,
2597 DAG.getConstant(TargetMask, MVT::i8));
2602 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
2603 SDValue V1, SDValue V2, SelectionDAG &DAG) {
2605 default: llvm_unreachable("Unknown x86 shuffle node");
2606 case X86ISD::MOVLHPS:
2607 case X86ISD::MOVLHPD:
2608 case X86ISD::MOVHLPS:
2609 case X86ISD::MOVLPS:
2610 case X86ISD::MOVLPD:
2613 case X86ISD::UNPCKLPS:
2614 case X86ISD::UNPCKLPD:
2615 case X86ISD::PUNPCKLWD:
2616 case X86ISD::PUNPCKLBW:
2617 case X86ISD::PUNPCKLDQ:
2618 case X86ISD::PUNPCKLQDQ:
2619 case X86ISD::UNPCKHPS:
2620 case X86ISD::UNPCKHPD:
2621 case X86ISD::PUNPCKHWD:
2622 case X86ISD::PUNPCKHBW:
2623 case X86ISD::PUNPCKHDQ:
2624 case X86ISD::PUNPCKHQDQ:
2625 return DAG.getNode(Opc, dl, VT, V1, V2);
2630 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
2631 MachineFunction &MF = DAG.getMachineFunction();
2632 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2633 int ReturnAddrIndex = FuncInfo->getRAIndex();
2635 if (ReturnAddrIndex == 0) {
2636 // Set up a frame object for the return address.
2637 uint64_t SlotSize = TD->getPointerSize();
2638 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize, -SlotSize,
2640 FuncInfo->setRAIndex(ReturnAddrIndex);
2643 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
2647 bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
2648 bool hasSymbolicDisplacement) {
2649 // Offset should fit into 32 bit immediate field.
2650 if (!isInt<32>(Offset))
2653 // If we don't have a symbolic displacement - we don't have any extra
2655 if (!hasSymbolicDisplacement)
2658 // FIXME: Some tweaks might be needed for medium code model.
2659 if (M != CodeModel::Small && M != CodeModel::Kernel)
2662 // For small code model we assume that latest object is 16MB before end of 31
2663 // bits boundary. We may also accept pretty large negative constants knowing
2664 // that all objects are in the positive half of address space.
2665 if (M == CodeModel::Small && Offset < 16*1024*1024)
2668 // For kernel code model we know that all object resist in the negative half
2669 // of 32bits address space. We may not accept negative offsets, since they may
2670 // be just off and we may accept pretty large positive ones.
2671 if (M == CodeModel::Kernel && Offset > 0)
2677 /// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86
2678 /// specific condition code, returning the condition code and the LHS/RHS of the
2679 /// comparison to make.
2680 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
2681 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
2683 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
2684 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
2685 // X > -1 -> X == 0, jump !sign.
2686 RHS = DAG.getConstant(0, RHS.getValueType());
2687 return X86::COND_NS;
2688 } else if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
2689 // X < 0 -> X == 0, jump on sign.
2691 } else if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
2693 RHS = DAG.getConstant(0, RHS.getValueType());
2694 return X86::COND_LE;
2698 switch (SetCCOpcode) {
2699 default: llvm_unreachable("Invalid integer condition!");
2700 case ISD::SETEQ: return X86::COND_E;
2701 case ISD::SETGT: return X86::COND_G;
2702 case ISD::SETGE: return X86::COND_GE;
2703 case ISD::SETLT: return X86::COND_L;
2704 case ISD::SETLE: return X86::COND_LE;
2705 case ISD::SETNE: return X86::COND_NE;
2706 case ISD::SETULT: return X86::COND_B;
2707 case ISD::SETUGT: return X86::COND_A;
2708 case ISD::SETULE: return X86::COND_BE;
2709 case ISD::SETUGE: return X86::COND_AE;
2713 // First determine if it is required or is profitable to flip the operands.
2715 // If LHS is a foldable load, but RHS is not, flip the condition.
2716 if ((ISD::isNON_EXTLoad(LHS.getNode()) && LHS.hasOneUse()) &&
2717 !(ISD::isNON_EXTLoad(RHS.getNode()) && RHS.hasOneUse())) {
2718 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
2719 std::swap(LHS, RHS);
2722 switch (SetCCOpcode) {
2728 std::swap(LHS, RHS);
2732 // On a floating point condition, the flags are set as follows:
2734 // 0 | 0 | 0 | X > Y
2735 // 0 | 0 | 1 | X < Y
2736 // 1 | 0 | 0 | X == Y
2737 // 1 | 1 | 1 | unordered
2738 switch (SetCCOpcode) {
2739 default: llvm_unreachable("Condcode should be pre-legalized away");
2741 case ISD::SETEQ: return X86::COND_E;
2742 case ISD::SETOLT: // flipped
2744 case ISD::SETGT: return X86::COND_A;
2745 case ISD::SETOLE: // flipped
2747 case ISD::SETGE: return X86::COND_AE;
2748 case ISD::SETUGT: // flipped
2750 case ISD::SETLT: return X86::COND_B;
2751 case ISD::SETUGE: // flipped
2753 case ISD::SETLE: return X86::COND_BE;
2755 case ISD::SETNE: return X86::COND_NE;
2756 case ISD::SETUO: return X86::COND_P;
2757 case ISD::SETO: return X86::COND_NP;
2759 case ISD::SETUNE: return X86::COND_INVALID;
2763 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
2764 /// code. Current x86 isa includes the following FP cmov instructions:
2765 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
2766 static bool hasFPCMov(unsigned X86CC) {
2782 /// isFPImmLegal - Returns true if the target can instruction select the
2783 /// specified FP immediate natively. If false, the legalizer will
2784 /// materialize the FP immediate as a load from a constant pool.
2785 bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
2786 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
2787 if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
2793 /// isUndefOrInRange - Return true if Val is undef or if its value falls within
2794 /// the specified range (L, H].
2795 static bool isUndefOrInRange(int Val, int Low, int Hi) {
2796 return (Val < 0) || (Val >= Low && Val < Hi);
2799 /// isUndefOrEqual - Val is either less than zero (undef) or equal to the
2800 /// specified value.
2801 static bool isUndefOrEqual(int Val, int CmpVal) {
2802 if (Val < 0 || Val == CmpVal)
2807 /// isPSHUFDMask - Return true if the node specifies a shuffle of elements that
2808 /// is suitable for input to PSHUFD or PSHUFW. That is, it doesn't reference
2809 /// the second operand.
2810 static bool isPSHUFDMask(const SmallVectorImpl<int> &Mask, EVT VT) {
2811 if (VT == MVT::v4f32 || VT == MVT::v4i32 )
2812 return (Mask[0] < 4 && Mask[1] < 4 && Mask[2] < 4 && Mask[3] < 4);
2813 if (VT == MVT::v2f64 || VT == MVT::v2i64)
2814 return (Mask[0] < 2 && Mask[1] < 2);
2818 bool X86::isPSHUFDMask(ShuffleVectorSDNode *N) {
2819 SmallVector<int, 8> M;
2821 return ::isPSHUFDMask(M, N->getValueType(0));
2824 /// isPSHUFHWMask - Return true if the node specifies a shuffle of elements that
2825 /// is suitable for input to PSHUFHW.
2826 static bool isPSHUFHWMask(const SmallVectorImpl<int> &Mask, EVT VT) {
2827 if (VT != MVT::v8i16)
2830 // Lower quadword copied in order or undef.
2831 for (int i = 0; i != 4; ++i)
2832 if (Mask[i] >= 0 && Mask[i] != i)
2835 // Upper quadword shuffled.
2836 for (int i = 4; i != 8; ++i)
2837 if (Mask[i] >= 0 && (Mask[i] < 4 || Mask[i] > 7))
2843 bool X86::isPSHUFHWMask(ShuffleVectorSDNode *N) {
2844 SmallVector<int, 8> M;
2846 return ::isPSHUFHWMask(M, N->getValueType(0));
2849 /// isPSHUFLWMask - Return true if the node specifies a shuffle of elements that
2850 /// is suitable for input to PSHUFLW.
2851 static bool isPSHUFLWMask(const SmallVectorImpl<int> &Mask, EVT VT) {
2852 if (VT != MVT::v8i16)
2855 // Upper quadword copied in order.
2856 for (int i = 4; i != 8; ++i)
2857 if (Mask[i] >= 0 && Mask[i] != i)
2860 // Lower quadword shuffled.
2861 for (int i = 0; i != 4; ++i)
2868 bool X86::isPSHUFLWMask(ShuffleVectorSDNode *N) {
2869 SmallVector<int, 8> M;
2871 return ::isPSHUFLWMask(M, N->getValueType(0));
2874 /// isPALIGNRMask - Return true if the node specifies a shuffle of elements that
2875 /// is suitable for input to PALIGNR.
2876 static bool isPALIGNRMask(const SmallVectorImpl<int> &Mask, EVT VT,
2878 int i, e = VT.getVectorNumElements();
2880 // Do not handle v2i64 / v2f64 shuffles with palignr.
2881 if (e < 4 || !hasSSSE3)
2884 for (i = 0; i != e; ++i)
2888 // All undef, not a palignr.
2892 // Determine if it's ok to perform a palignr with only the LHS, since we
2893 // don't have access to the actual shuffle elements to see if RHS is undef.
2894 bool Unary = Mask[i] < (int)e;
2895 bool NeedsUnary = false;
2897 int s = Mask[i] - i;
2899 // Check the rest of the elements to see if they are consecutive.
2900 for (++i; i != e; ++i) {
2905 Unary = Unary && (m < (int)e);
2906 NeedsUnary = NeedsUnary || (m < s);
2908 if (NeedsUnary && !Unary)
2910 if (Unary && m != ((s+i) & (e-1)))
2912 if (!Unary && m != (s+i))
2918 bool X86::isPALIGNRMask(ShuffleVectorSDNode *N) {
2919 SmallVector<int, 8> M;
2921 return ::isPALIGNRMask(M, N->getValueType(0), true);
2924 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
2925 /// specifies a shuffle of elements that is suitable for input to SHUFP*.
2926 static bool isSHUFPMask(const SmallVectorImpl<int> &Mask, EVT VT) {
2927 int NumElems = VT.getVectorNumElements();
2928 if (NumElems != 2 && NumElems != 4)
2931 int Half = NumElems / 2;
2932 for (int i = 0; i < Half; ++i)
2933 if (!isUndefOrInRange(Mask[i], 0, NumElems))
2935 for (int i = Half; i < NumElems; ++i)
2936 if (!isUndefOrInRange(Mask[i], NumElems, NumElems*2))
2942 bool X86::isSHUFPMask(ShuffleVectorSDNode *N) {
2943 SmallVector<int, 8> M;
2945 return ::isSHUFPMask(M, N->getValueType(0));
2948 /// isCommutedSHUFP - Returns true if the shuffle mask is exactly
2949 /// the reverse of what x86 shuffles want. x86 shuffles requires the lower
2950 /// half elements to come from vector 1 (which would equal the dest.) and
2951 /// the upper half to come from vector 2.
2952 static bool isCommutedSHUFPMask(const SmallVectorImpl<int> &Mask, EVT VT) {
2953 int NumElems = VT.getVectorNumElements();
2955 if (NumElems != 2 && NumElems != 4)
2958 int Half = NumElems / 2;
2959 for (int i = 0; i < Half; ++i)
2960 if (!isUndefOrInRange(Mask[i], NumElems, NumElems*2))
2962 for (int i = Half; i < NumElems; ++i)
2963 if (!isUndefOrInRange(Mask[i], 0, NumElems))
2968 static bool isCommutedSHUFP(ShuffleVectorSDNode *N) {
2969 SmallVector<int, 8> M;
2971 return isCommutedSHUFPMask(M, N->getValueType(0));
2974 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
2975 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
2976 bool X86::isMOVHLPSMask(ShuffleVectorSDNode *N) {
2977 if (N->getValueType(0).getVectorNumElements() != 4)
2980 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3
2981 return isUndefOrEqual(N->getMaskElt(0), 6) &&
2982 isUndefOrEqual(N->getMaskElt(1), 7) &&
2983 isUndefOrEqual(N->getMaskElt(2), 2) &&
2984 isUndefOrEqual(N->getMaskElt(3), 3);
2987 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
2988 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
2990 bool X86::isMOVHLPS_v_undef_Mask(ShuffleVectorSDNode *N) {
2991 unsigned NumElems = N->getValueType(0).getVectorNumElements();
2996 return isUndefOrEqual(N->getMaskElt(0), 2) &&
2997 isUndefOrEqual(N->getMaskElt(1), 3) &&
2998 isUndefOrEqual(N->getMaskElt(2), 2) &&
2999 isUndefOrEqual(N->getMaskElt(3), 3);
3002 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
3003 /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
3004 bool X86::isMOVLPMask(ShuffleVectorSDNode *N) {
3005 unsigned NumElems = N->getValueType(0).getVectorNumElements();
3007 if (NumElems != 2 && NumElems != 4)
3010 for (unsigned i = 0; i < NumElems/2; ++i)
3011 if (!isUndefOrEqual(N->getMaskElt(i), i + NumElems))
3014 for (unsigned i = NumElems/2; i < NumElems; ++i)
3015 if (!isUndefOrEqual(N->getMaskElt(i), i))
3021 /// isMOVLHPSMask - Return true if the specified VECTOR_SHUFFLE operand
3022 /// specifies a shuffle of elements that is suitable for input to MOVLHPS.
3023 bool X86::isMOVLHPSMask(ShuffleVectorSDNode *N) {
3024 unsigned NumElems = N->getValueType(0).getVectorNumElements();
3026 if (NumElems != 2 && NumElems != 4)
3029 for (unsigned i = 0; i < NumElems/2; ++i)
3030 if (!isUndefOrEqual(N->getMaskElt(i), i))
3033 for (unsigned i = 0; i < NumElems/2; ++i)
3034 if (!isUndefOrEqual(N->getMaskElt(i + NumElems/2), i + NumElems))
3040 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
3041 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
3042 static bool isUNPCKLMask(const SmallVectorImpl<int> &Mask, EVT VT,
3043 bool V2IsSplat = false) {
3044 int NumElts = VT.getVectorNumElements();
3045 if (NumElts != 2 && NumElts != 4 && NumElts != 8 && NumElts != 16)
3048 for (int i = 0, j = 0; i != NumElts; i += 2, ++j) {
3050 int BitI1 = Mask[i+1];
3051 if (!isUndefOrEqual(BitI, j))
3054 if (!isUndefOrEqual(BitI1, NumElts))
3057 if (!isUndefOrEqual(BitI1, j + NumElts))
3064 bool X86::isUNPCKLMask(ShuffleVectorSDNode *N, bool V2IsSplat) {
3065 SmallVector<int, 8> M;
3067 return ::isUNPCKLMask(M, N->getValueType(0), V2IsSplat);
3070 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
3071 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
3072 static bool isUNPCKHMask(const SmallVectorImpl<int> &Mask, EVT VT,
3073 bool V2IsSplat = false) {
3074 int NumElts = VT.getVectorNumElements();
3075 if (NumElts != 2 && NumElts != 4 && NumElts != 8 && NumElts != 16)
3078 for (int i = 0, j = 0; i != NumElts; i += 2, ++j) {
3080 int BitI1 = Mask[i+1];
3081 if (!isUndefOrEqual(BitI, j + NumElts/2))
3084 if (isUndefOrEqual(BitI1, NumElts))
3087 if (!isUndefOrEqual(BitI1, j + NumElts/2 + NumElts))
3094 bool X86::isUNPCKHMask(ShuffleVectorSDNode *N, bool V2IsSplat) {
3095 SmallVector<int, 8> M;
3097 return ::isUNPCKHMask(M, N->getValueType(0), V2IsSplat);
3100 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
3101 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
3103 static bool isUNPCKL_v_undef_Mask(const SmallVectorImpl<int> &Mask, EVT VT) {
3104 int NumElems = VT.getVectorNumElements();
3105 if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16)
3108 for (int i = 0, j = 0; i != NumElems; i += 2, ++j) {
3110 int BitI1 = Mask[i+1];
3111 if (!isUndefOrEqual(BitI, j))
3113 if (!isUndefOrEqual(BitI1, j))
3119 bool X86::isUNPCKL_v_undef_Mask(ShuffleVectorSDNode *N) {
3120 SmallVector<int, 8> M;
3122 return ::isUNPCKL_v_undef_Mask(M, N->getValueType(0));
3125 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
3126 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
3128 static bool isUNPCKH_v_undef_Mask(const SmallVectorImpl<int> &Mask, EVT VT) {
3129 int NumElems = VT.getVectorNumElements();
3130 if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16)
3133 for (int i = 0, j = NumElems / 2; i != NumElems; i += 2, ++j) {
3135 int BitI1 = Mask[i+1];
3136 if (!isUndefOrEqual(BitI, j))
3138 if (!isUndefOrEqual(BitI1, j))
3144 bool X86::isUNPCKH_v_undef_Mask(ShuffleVectorSDNode *N) {
3145 SmallVector<int, 8> M;
3147 return ::isUNPCKH_v_undef_Mask(M, N->getValueType(0));
3150 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
3151 /// specifies a shuffle of elements that is suitable for input to MOVSS,
3152 /// MOVSD, and MOVD, i.e. setting the lowest element.
3153 static bool isMOVLMask(const SmallVectorImpl<int> &Mask, EVT VT) {
3154 if (VT.getVectorElementType().getSizeInBits() < 32)
3157 int NumElts = VT.getVectorNumElements();
3159 if (!isUndefOrEqual(Mask[0], NumElts))
3162 for (int i = 1; i < NumElts; ++i)
3163 if (!isUndefOrEqual(Mask[i], i))
3169 bool X86::isMOVLMask(ShuffleVectorSDNode *N) {
3170 SmallVector<int, 8> M;
3172 return ::isMOVLMask(M, N->getValueType(0));
3175 /// isCommutedMOVL - Returns true if the shuffle mask is except the reverse
3176 /// of what x86 movss want. X86 movs requires the lowest element to be lowest
3177 /// element of vector 2 and the other elements to come from vector 1 in order.
3178 static bool isCommutedMOVLMask(const SmallVectorImpl<int> &Mask, EVT VT,
3179 bool V2IsSplat = false, bool V2IsUndef = false) {
3180 int NumOps = VT.getVectorNumElements();
3181 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16)
3184 if (!isUndefOrEqual(Mask[0], 0))
3187 for (int i = 1; i < NumOps; ++i)
3188 if (!(isUndefOrEqual(Mask[i], i+NumOps) ||
3189 (V2IsUndef && isUndefOrInRange(Mask[i], NumOps, NumOps*2)) ||
3190 (V2IsSplat && isUndefOrEqual(Mask[i], NumOps))))
3196 static bool isCommutedMOVL(ShuffleVectorSDNode *N, bool V2IsSplat = false,
3197 bool V2IsUndef = false) {
3198 SmallVector<int, 8> M;
3200 return isCommutedMOVLMask(M, N->getValueType(0), V2IsSplat, V2IsUndef);
3203 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
3204 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
3205 bool X86::isMOVSHDUPMask(ShuffleVectorSDNode *N) {
3206 if (N->getValueType(0).getVectorNumElements() != 4)
3209 // Expect 1, 1, 3, 3
3210 for (unsigned i = 0; i < 2; ++i) {
3211 int Elt = N->getMaskElt(i);
3212 if (Elt >= 0 && Elt != 1)
3217 for (unsigned i = 2; i < 4; ++i) {
3218 int Elt = N->getMaskElt(i);
3219 if (Elt >= 0 && Elt != 3)
3224 // Don't use movshdup if it can be done with a shufps.
3225 // FIXME: verify that matching u, u, 3, 3 is what we want.
3229 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
3230 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
3231 bool X86::isMOVSLDUPMask(ShuffleVectorSDNode *N) {
3232 if (N->getValueType(0).getVectorNumElements() != 4)
3235 // Expect 0, 0, 2, 2
3236 for (unsigned i = 0; i < 2; ++i)
3237 if (N->getMaskElt(i) > 0)
3241 for (unsigned i = 2; i < 4; ++i) {
3242 int Elt = N->getMaskElt(i);
3243 if (Elt >= 0 && Elt != 2)
3248 // Don't use movsldup if it can be done with a shufps.
3252 /// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand
3253 /// specifies a shuffle of elements that is suitable for input to MOVDDUP.
3254 bool X86::isMOVDDUPMask(ShuffleVectorSDNode *N) {
3255 int e = N->getValueType(0).getVectorNumElements() / 2;
3257 for (int i = 0; i < e; ++i)
3258 if (!isUndefOrEqual(N->getMaskElt(i), i))
3260 for (int i = 0; i < e; ++i)
3261 if (!isUndefOrEqual(N->getMaskElt(e+i), i))
3266 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
3267 /// the specified VECTOR_SHUFFLE mask with PSHUF* and SHUFP* instructions.
3268 unsigned X86::getShuffleSHUFImmediate(SDNode *N) {
3269 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
3270 int NumOperands = SVOp->getValueType(0).getVectorNumElements();
3272 unsigned Shift = (NumOperands == 4) ? 2 : 1;
3274 for (int i = 0; i < NumOperands; ++i) {
3275 int Val = SVOp->getMaskElt(NumOperands-i-1);
3276 if (Val < 0) Val = 0;
3277 if (Val >= NumOperands) Val -= NumOperands;
3279 if (i != NumOperands - 1)
3285 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
3286 /// the specified VECTOR_SHUFFLE mask with the PSHUFHW instruction.
3287 unsigned X86::getShufflePSHUFHWImmediate(SDNode *N) {
3288 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
3290 // 8 nodes, but we only care about the last 4.
3291 for (unsigned i = 7; i >= 4; --i) {
3292 int Val = SVOp->getMaskElt(i);
3301 /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
3302 /// the specified VECTOR_SHUFFLE mask with the PSHUFLW instruction.
3303 unsigned X86::getShufflePSHUFLWImmediate(SDNode *N) {
3304 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
3306 // 8 nodes, but we only care about the first 4.
3307 for (int i = 3; i >= 0; --i) {
3308 int Val = SVOp->getMaskElt(i);
3317 /// getShufflePALIGNRImmediate - Return the appropriate immediate to shuffle
3318 /// the specified VECTOR_SHUFFLE mask with the PALIGNR instruction.
3319 unsigned X86::getShufflePALIGNRImmediate(SDNode *N) {
3320 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
3321 EVT VVT = N->getValueType(0);
3322 unsigned EltSize = VVT.getVectorElementType().getSizeInBits() >> 3;
3326 for (i = 0, e = VVT.getVectorNumElements(); i != e; ++i) {
3327 Val = SVOp->getMaskElt(i);
3331 return (Val - i) * EltSize;
3334 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
3336 bool X86::isZeroNode(SDValue Elt) {
3337 return ((isa<ConstantSDNode>(Elt) &&
3338 cast<ConstantSDNode>(Elt)->isNullValue()) ||
3339 (isa<ConstantFPSDNode>(Elt) &&
3340 cast<ConstantFPSDNode>(Elt)->getValueAPF().isPosZero()));
3343 /// CommuteVectorShuffle - Swap vector_shuffle operands as well as values in
3344 /// their permute mask.
3345 static SDValue CommuteVectorShuffle(ShuffleVectorSDNode *SVOp,
3346 SelectionDAG &DAG) {
3347 EVT VT = SVOp->getValueType(0);
3348 unsigned NumElems = VT.getVectorNumElements();
3349 SmallVector<int, 8> MaskVec;
3351 for (unsigned i = 0; i != NumElems; ++i) {
3352 int idx = SVOp->getMaskElt(i);
3354 MaskVec.push_back(idx);
3355 else if (idx < (int)NumElems)
3356 MaskVec.push_back(idx + NumElems);
3358 MaskVec.push_back(idx - NumElems);
3360 return DAG.getVectorShuffle(VT, SVOp->getDebugLoc(), SVOp->getOperand(1),
3361 SVOp->getOperand(0), &MaskVec[0]);
3364 /// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming
3365 /// the two vector operands have swapped position.
3366 static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask, EVT VT) {
3367 unsigned NumElems = VT.getVectorNumElements();
3368 for (unsigned i = 0; i != NumElems; ++i) {
3372 else if (idx < (int)NumElems)
3373 Mask[i] = idx + NumElems;
3375 Mask[i] = idx - NumElems;
3379 /// ShouldXformToMOVHLPS - Return true if the node should be transformed to
3380 /// match movhlps. The lower half elements should come from upper half of
3381 /// V1 (and in order), and the upper half elements should come from the upper
3382 /// half of V2 (and in order).
3383 static bool ShouldXformToMOVHLPS(ShuffleVectorSDNode *Op) {
3384 if (Op->getValueType(0).getVectorNumElements() != 4)
3386 for (unsigned i = 0, e = 2; i != e; ++i)
3387 if (!isUndefOrEqual(Op->getMaskElt(i), i+2))
3389 for (unsigned i = 2; i != 4; ++i)
3390 if (!isUndefOrEqual(Op->getMaskElt(i), i+4))
3395 /// isScalarLoadToVector - Returns true if the node is a scalar load that
3396 /// is promoted to a vector. It also returns the LoadSDNode by reference if
3398 static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = NULL) {
3399 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR)
3401 N = N->getOperand(0).getNode();
3402 if (!ISD::isNON_EXTLoad(N))
3405 *LD = cast<LoadSDNode>(N);
3409 /// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to
3410 /// match movlp{s|d}. The lower half elements should come from lower half of
3411 /// V1 (and in order), and the upper half elements should come from the upper
3412 /// half of V2 (and in order). And since V1 will become the source of the
3413 /// MOVLP, it must be either a vector load or a scalar load to vector.
3414 static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2,
3415 ShuffleVectorSDNode *Op) {
3416 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1))
3418 // Is V2 is a vector load, don't do this transformation. We will try to use
3419 // load folding shufps op.
3420 if (ISD::isNON_EXTLoad(V2))
3423 unsigned NumElems = Op->getValueType(0).getVectorNumElements();
3425 if (NumElems != 2 && NumElems != 4)
3427 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
3428 if (!isUndefOrEqual(Op->getMaskElt(i), i))
3430 for (unsigned i = NumElems/2; i != NumElems; ++i)
3431 if (!isUndefOrEqual(Op->getMaskElt(i), i+NumElems))
3436 /// isSplatVector - Returns true if N is a BUILD_VECTOR node whose elements are
3438 static bool isSplatVector(SDNode *N) {
3439 if (N->getOpcode() != ISD::BUILD_VECTOR)
3442 SDValue SplatValue = N->getOperand(0);
3443 for (unsigned i = 1, e = N->getNumOperands(); i != e; ++i)
3444 if (N->getOperand(i) != SplatValue)
3449 /// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
3450 /// to an zero vector.
3451 /// FIXME: move to dag combiner / method on ShuffleVectorSDNode
3452 static bool isZeroShuffle(ShuffleVectorSDNode *N) {
3453 SDValue V1 = N->getOperand(0);
3454 SDValue V2 = N->getOperand(1);
3455 unsigned NumElems = N->getValueType(0).getVectorNumElements();
3456 for (unsigned i = 0; i != NumElems; ++i) {
3457 int Idx = N->getMaskElt(i);
3458 if (Idx >= (int)NumElems) {
3459 unsigned Opc = V2.getOpcode();
3460 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode()))
3462 if (Opc != ISD::BUILD_VECTOR ||
3463 !X86::isZeroNode(V2.getOperand(Idx-NumElems)))
3465 } else if (Idx >= 0) {
3466 unsigned Opc = V1.getOpcode();
3467 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode()))
3469 if (Opc != ISD::BUILD_VECTOR ||
3470 !X86::isZeroNode(V1.getOperand(Idx)))
3477 /// getZeroVector - Returns a vector of specified type with all zero elements.
3479 static SDValue getZeroVector(EVT VT, bool HasSSE2, SelectionDAG &DAG,
3481 assert(VT.isVector() && "Expected a vector type");
3483 // Always build SSE zero vectors as <4 x i32> bitcasted
3484 // to their dest type. This ensures they get CSE'd.
3486 if (VT.getSizeInBits() == 128) { // SSE
3487 if (HasSSE2) { // SSE2
3488 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
3489 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
3491 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
3492 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
3494 } else if (VT.getSizeInBits() == 256) { // AVX
3495 // 256-bit logic and arithmetic instructions in AVX are
3496 // all floating-point, no support for integer ops. Default
3497 // to emitting fp zeroed vectors then.
3498 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
3499 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
3500 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops, 8);
3502 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vec);
3505 /// getOnesVector - Returns a vector of specified type with all bits set.
3507 static SDValue getOnesVector(EVT VT, SelectionDAG &DAG, DebugLoc dl) {
3508 assert(VT.isVector() && "Expected a vector type");
3510 // Always build ones vectors as <4 x i32> or <2 x i32> bitcasted to their dest
3511 // type. This ensures they get CSE'd.
3512 SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32);
3514 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
3515 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vec);
3519 /// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements
3520 /// that point to V2 points to its first element.
3521 static SDValue NormalizeMask(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
3522 EVT VT = SVOp->getValueType(0);
3523 unsigned NumElems = VT.getVectorNumElements();
3525 bool Changed = false;
3526 SmallVector<int, 8> MaskVec;
3527 SVOp->getMask(MaskVec);
3529 for (unsigned i = 0; i != NumElems; ++i) {
3530 if (MaskVec[i] > (int)NumElems) {
3531 MaskVec[i] = NumElems;
3536 return DAG.getVectorShuffle(VT, SVOp->getDebugLoc(), SVOp->getOperand(0),
3537 SVOp->getOperand(1), &MaskVec[0]);
3538 return SDValue(SVOp, 0);
3541 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
3542 /// operation of specified width.
3543 static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
3545 unsigned NumElems = VT.getVectorNumElements();
3546 SmallVector<int, 8> Mask;
3547 Mask.push_back(NumElems);
3548 for (unsigned i = 1; i != NumElems; ++i)
3550 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
3553 /// getUnpackl - Returns a vector_shuffle node for an unpackl operation.
3554 static SDValue getUnpackl(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
3556 unsigned NumElems = VT.getVectorNumElements();
3557 SmallVector<int, 8> Mask;
3558 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
3560 Mask.push_back(i + NumElems);
3562 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
3565 /// getUnpackhMask - Returns a vector_shuffle node for an unpackh operation.
3566 static SDValue getUnpackh(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
3568 unsigned NumElems = VT.getVectorNumElements();
3569 unsigned Half = NumElems/2;
3570 SmallVector<int, 8> Mask;
3571 for (unsigned i = 0; i != Half; ++i) {
3572 Mask.push_back(i + Half);
3573 Mask.push_back(i + NumElems + Half);
3575 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
3578 /// PromoteSplat - Promote a splat of v4i32, v8i16 or v16i8 to v4f32.
3579 static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG) {
3580 EVT PVT = MVT::v4f32;
3581 EVT VT = SV->getValueType(0);
3582 DebugLoc dl = SV->getDebugLoc();
3583 SDValue V1 = SV->getOperand(0);
3584 int NumElems = VT.getVectorNumElements();
3585 int EltNo = SV->getSplatIndex();
3587 // unpack elements to the correct location
3588 while (NumElems > 4) {
3589 if (EltNo < NumElems/2) {
3590 V1 = getUnpackl(DAG, dl, VT, V1, V1);
3592 V1 = getUnpackh(DAG, dl, VT, V1, V1);
3593 EltNo -= NumElems/2;
3598 // Perform the splat.
3599 int SplatMask[4] = { EltNo, EltNo, EltNo, EltNo };
3600 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, PVT, V1);
3601 V1 = DAG.getVectorShuffle(PVT, dl, V1, DAG.getUNDEF(PVT), &SplatMask[0]);
3602 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, V1);
3605 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
3606 /// vector of zero or undef vector. This produces a shuffle where the low
3607 /// element of V2 is swizzled into the zero/undef vector, landing at element
3608 /// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
3609 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
3610 bool isZero, bool HasSSE2,
3611 SelectionDAG &DAG) {
3612 EVT VT = V2.getValueType();
3614 ? getZeroVector(VT, HasSSE2, DAG, V2.getDebugLoc()) : DAG.getUNDEF(VT);
3615 unsigned NumElems = VT.getVectorNumElements();
3616 SmallVector<int, 16> MaskVec;
3617 for (unsigned i = 0; i != NumElems; ++i)
3618 // If this is the insertion idx, put the low elt of V2 here.
3619 MaskVec.push_back(i == Idx ? NumElems : i);
3620 return DAG.getVectorShuffle(VT, V2.getDebugLoc(), V1, V2, &MaskVec[0]);
3623 /// getShuffleScalarElt - Returns the scalar element that will make up the ith
3624 /// element of the result of the vector shuffle.
3625 SDValue getShuffleScalarElt(SDNode *N, int Index, SelectionDAG &DAG,
3628 return SDValue(); // Limit search depth.
3630 SDValue V = SDValue(N, 0);
3631 EVT VT = V.getValueType();
3632 unsigned Opcode = V.getOpcode();
3634 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars.
3635 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) {
3636 Index = SV->getMaskElt(Index);
3639 return DAG.getUNDEF(VT.getVectorElementType());
3641 int NumElems = VT.getVectorNumElements();
3642 SDValue NewV = (Index < NumElems) ? SV->getOperand(0) : SV->getOperand(1);
3643 return getShuffleScalarElt(NewV.getNode(), Index % NumElems, DAG, Depth+1);
3646 // Recurse into target specific vector shuffles to find scalars.
3647 if (isTargetShuffle(Opcode)) {
3648 int NumElems = VT.getVectorNumElements();
3649 SmallVector<unsigned, 16> ShuffleMask;
3653 case X86ISD::SHUFPS:
3654 case X86ISD::SHUFPD:
3655 ImmN = N->getOperand(N->getNumOperands()-1);
3656 DecodeSHUFPSMask(NumElems,
3657 cast<ConstantSDNode>(ImmN)->getZExtValue(),
3660 case X86ISD::PUNPCKHBW:
3661 case X86ISD::PUNPCKHWD:
3662 case X86ISD::PUNPCKHDQ:
3663 case X86ISD::PUNPCKHQDQ:
3664 DecodePUNPCKHMask(NumElems, ShuffleMask);
3666 case X86ISD::UNPCKHPS:
3667 case X86ISD::UNPCKHPD:
3668 DecodeUNPCKHPMask(NumElems, ShuffleMask);
3670 case X86ISD::PUNPCKLBW:
3671 case X86ISD::PUNPCKLWD:
3672 case X86ISD::PUNPCKLDQ:
3673 case X86ISD::PUNPCKLQDQ:
3674 DecodePUNPCKLMask(NumElems, ShuffleMask);
3676 case X86ISD::UNPCKLPS:
3677 case X86ISD::UNPCKLPD:
3678 DecodeUNPCKLPMask(NumElems, ShuffleMask);
3680 case X86ISD::MOVHLPS:
3681 DecodeMOVHLPSMask(NumElems, ShuffleMask);
3683 case X86ISD::MOVLHPS:
3684 DecodeMOVLHPSMask(NumElems, ShuffleMask);
3686 case X86ISD::PSHUFD:
3687 ImmN = N->getOperand(N->getNumOperands()-1);
3688 DecodePSHUFMask(NumElems,
3689 cast<ConstantSDNode>(ImmN)->getZExtValue(),
3692 case X86ISD::PSHUFHW:
3693 ImmN = N->getOperand(N->getNumOperands()-1);
3694 DecodePSHUFHWMask(cast<ConstantSDNode>(ImmN)->getZExtValue(),
3697 case X86ISD::PSHUFLW:
3698 ImmN = N->getOperand(N->getNumOperands()-1);
3699 DecodePSHUFLWMask(cast<ConstantSDNode>(ImmN)->getZExtValue(),
3703 case X86ISD::MOVSD: {
3704 // The index 0 always comes from the first element of the second source,
3705 // this is why MOVSS and MOVSD are used in the first place. The other
3706 // elements come from the other positions of the first source vector.
3707 unsigned OpNum = (Index == 0) ? 1 : 0;
3708 return getShuffleScalarElt(V.getOperand(OpNum).getNode(), Index, DAG,
3712 assert("not implemented for target shuffle node");
3716 Index = ShuffleMask[Index];
3718 return DAG.getUNDEF(VT.getVectorElementType());
3720 SDValue NewV = (Index < NumElems) ? N->getOperand(0) : N->getOperand(1);
3721 return getShuffleScalarElt(NewV.getNode(), Index % NumElems, DAG,
3725 // Actual nodes that may contain scalar elements
3726 if (Opcode == ISD::BIT_CONVERT) {
3727 V = V.getOperand(0);
3728 EVT SrcVT = V.getValueType();
3729 unsigned NumElems = VT.getVectorNumElements();
3731 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems)
3735 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR)
3736 return (Index == 0) ? V.getOperand(0)
3737 : DAG.getUNDEF(VT.getVectorElementType());
3739 if (V.getOpcode() == ISD::BUILD_VECTOR)
3740 return V.getOperand(Index);
3745 /// getNumOfConsecutiveZeros - Return the number of elements of a vector
3746 /// shuffle operation which come from a consecutively from a zero. The
3747 /// search can start in two diferent directions, from left or right.
3749 unsigned getNumOfConsecutiveZeros(SDNode *N, int NumElems,
3750 bool ZerosFromLeft, SelectionDAG &DAG) {
3753 while (i < NumElems) {
3754 unsigned Index = ZerosFromLeft ? i : NumElems-i-1;
3755 SDValue Elt = getShuffleScalarElt(N, Index, DAG, 0);
3756 if (!(Elt.getNode() &&
3757 (Elt.getOpcode() == ISD::UNDEF || X86::isZeroNode(Elt))))
3765 /// isShuffleMaskConsecutive - Check if the shuffle mask indicies from MaskI to
3766 /// MaskE correspond consecutively to elements from one of the vector operands,
3767 /// starting from its index OpIdx. Also tell OpNum which source vector operand.
3769 bool isShuffleMaskConsecutive(ShuffleVectorSDNode *SVOp, int MaskI, int MaskE,
3770 int OpIdx, int NumElems, unsigned &OpNum) {
3771 bool SeenV1 = false;
3772 bool SeenV2 = false;
3774 for (int i = MaskI; i <= MaskE; ++i, ++OpIdx) {
3775 int Idx = SVOp->getMaskElt(i);
3776 // Ignore undef indicies
3785 // Only accept consecutive elements from the same vector
3786 if ((Idx % NumElems != OpIdx) || (SeenV1 && SeenV2))
3790 OpNum = SeenV1 ? 0 : 1;
3794 /// isVectorShiftRight - Returns true if the shuffle can be implemented as a
3795 /// logical left shift of a vector.
3796 static bool isVectorShiftRight(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
3797 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
3798 unsigned NumElems = SVOp->getValueType(0).getVectorNumElements();
3799 unsigned NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems,
3800 false /* check zeros from right */, DAG);
3806 // Considering the elements in the mask that are not consecutive zeros,
3807 // check if they consecutively come from only one of the source vectors.
3809 // V1 = {X, A, B, C} 0
3811 // vector_shuffle V1, V2 <1, 2, 3, X>
3813 if (!isShuffleMaskConsecutive(SVOp,
3814 0, // Mask Start Index
3815 NumElems-NumZeros-1, // Mask End Index
3816 NumZeros, // Where to start looking in the src vector
3817 NumElems, // Number of elements in vector
3818 OpSrc)) // Which source operand ?
3823 ShVal = SVOp->getOperand(OpSrc);
3827 /// isVectorShiftLeft - Returns true if the shuffle can be implemented as a
3828 /// logical left shift of a vector.
3829 static bool isVectorShiftLeft(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
3830 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
3831 unsigned NumElems = SVOp->getValueType(0).getVectorNumElements();
3832 unsigned NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems,
3833 true /* check zeros from left */, DAG);
3839 // Considering the elements in the mask that are not consecutive zeros,
3840 // check if they consecutively come from only one of the source vectors.
3842 // 0 { A, B, X, X } = V2
3844 // vector_shuffle V1, V2 <X, X, 4, 5>
3846 if (!isShuffleMaskConsecutive(SVOp,
3847 NumZeros, // Mask Start Index
3848 NumElems-1, // Mask End Index
3849 0, // Where to start looking in the src vector
3850 NumElems, // Number of elements in vector
3851 OpSrc)) // Which source operand ?
3856 ShVal = SVOp->getOperand(OpSrc);
3860 /// isVectorShift - Returns true if the shuffle can be implemented as a
3861 /// logical left or right shift of a vector.
3862 static bool isVectorShift(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
3863 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
3864 if (isVectorShiftLeft(SVOp, DAG, isLeft, ShVal, ShAmt) ||
3865 isVectorShiftRight(SVOp, DAG, isLeft, ShVal, ShAmt))
3871 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
3873 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
3874 unsigned NumNonZero, unsigned NumZero,
3876 const TargetLowering &TLI) {
3880 DebugLoc dl = Op.getDebugLoc();
3883 for (unsigned i = 0; i < 16; ++i) {
3884 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
3885 if (ThisIsNonZero && First) {
3887 V = getZeroVector(MVT::v8i16, true, DAG, dl);
3889 V = DAG.getUNDEF(MVT::v8i16);
3894 SDValue ThisElt(0, 0), LastElt(0, 0);
3895 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
3896 if (LastIsNonZero) {
3897 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
3898 MVT::i16, Op.getOperand(i-1));
3900 if (ThisIsNonZero) {
3901 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
3902 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
3903 ThisElt, DAG.getConstant(8, MVT::i8));
3905 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
3909 if (ThisElt.getNode())
3910 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
3911 DAG.getIntPtrConstant(i/2));
3915 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, V);
3918 /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
3920 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
3921 unsigned NumNonZero, unsigned NumZero,
3923 const TargetLowering &TLI) {
3927 DebugLoc dl = Op.getDebugLoc();
3930 for (unsigned i = 0; i < 8; ++i) {
3931 bool isNonZero = (NonZeros & (1 << i)) != 0;
3935 V = getZeroVector(MVT::v8i16, true, DAG, dl);
3937 V = DAG.getUNDEF(MVT::v8i16);
3940 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
3941 MVT::v8i16, V, Op.getOperand(i),
3942 DAG.getIntPtrConstant(i));
3949 /// getVShift - Return a vector logical shift node.
3951 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
3952 unsigned NumBits, SelectionDAG &DAG,
3953 const TargetLowering &TLI, DebugLoc dl) {
3954 EVT ShVT = MVT::v2i64;
3955 unsigned Opc = isLeft ? X86ISD::VSHL : X86ISD::VSRL;
3956 SrcOp = DAG.getNode(ISD::BIT_CONVERT, dl, ShVT, SrcOp);
3957 return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
3958 DAG.getNode(Opc, dl, ShVT, SrcOp,
3959 DAG.getConstant(NumBits, TLI.getShiftAmountTy())));
3963 X86TargetLowering::LowerAsSplatVectorLoad(SDValue SrcOp, EVT VT, DebugLoc dl,
3964 SelectionDAG &DAG) const {
3966 // Check if the scalar load can be widened into a vector load. And if
3967 // the address is "base + cst" see if the cst can be "absorbed" into
3968 // the shuffle mask.
3969 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) {
3970 SDValue Ptr = LD->getBasePtr();
3971 if (!ISD::isNormalLoad(LD) || LD->isVolatile())
3973 EVT PVT = LD->getValueType(0);
3974 if (PVT != MVT::i32 && PVT != MVT::f32)
3979 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) {
3980 FI = FINode->getIndex();
3982 } else if (Ptr.getOpcode() == ISD::ADD &&
3983 isa<ConstantSDNode>(Ptr.getOperand(1)) &&
3984 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
3985 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
3986 Offset = Ptr.getConstantOperandVal(1);
3987 Ptr = Ptr.getOperand(0);
3992 SDValue Chain = LD->getChain();
3993 // Make sure the stack object alignment is at least 16.
3994 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
3995 if (DAG.InferPtrAlignment(Ptr) < 16) {
3996 if (MFI->isFixedObjectIndex(FI)) {
3997 // Can't change the alignment. FIXME: It's possible to compute
3998 // the exact stack offset and reference FI + adjust offset instead.
3999 // If someone *really* cares about this. That's the way to implement it.
4002 MFI->setObjectAlignment(FI, 16);
4006 // (Offset % 16) must be multiple of 4. Then address is then
4007 // Ptr + (Offset & ~15).
4010 if ((Offset % 16) & 3)
4012 int64_t StartOffset = Offset & ~15;
4014 Ptr = DAG.getNode(ISD::ADD, Ptr.getDebugLoc(), Ptr.getValueType(),
4015 Ptr,DAG.getConstant(StartOffset, Ptr.getValueType()));
4017 int EltNo = (Offset - StartOffset) >> 2;
4018 int Mask[4] = { EltNo, EltNo, EltNo, EltNo };
4019 EVT VT = (PVT == MVT::i32) ? MVT::v4i32 : MVT::v4f32;
4020 SDValue V1 = DAG.getLoad(VT, dl, Chain, Ptr,
4021 LD->getPointerInfo().getWithOffset(StartOffset),
4023 // Canonicalize it to a v4i32 shuffle.
4024 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v4i32, V1);
4025 return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
4026 DAG.getVectorShuffle(MVT::v4i32, dl, V1,
4027 DAG.getUNDEF(MVT::v4i32),&Mask[0]));
4033 /// EltsFromConsecutiveLoads - Given the initializing elements 'Elts' of a
4034 /// vector of type 'VT', see if the elements can be replaced by a single large
4035 /// load which has the same value as a build_vector whose operands are 'elts'.
4037 /// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a
4039 /// FIXME: we'd also like to handle the case where the last elements are zero
4040 /// rather than undef via VZEXT_LOAD, but we do not detect that case today.
4041 /// There's even a handy isZeroNode for that purpose.
4042 static SDValue EltsFromConsecutiveLoads(EVT VT, SmallVectorImpl<SDValue> &Elts,
4043 DebugLoc &DL, SelectionDAG &DAG) {
4044 EVT EltVT = VT.getVectorElementType();
4045 unsigned NumElems = Elts.size();
4047 LoadSDNode *LDBase = NULL;
4048 unsigned LastLoadedElt = -1U;
4050 // For each element in the initializer, see if we've found a load or an undef.
4051 // If we don't find an initial load element, or later load elements are
4052 // non-consecutive, bail out.
4053 for (unsigned i = 0; i < NumElems; ++i) {
4054 SDValue Elt = Elts[i];
4056 if (!Elt.getNode() ||
4057 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
4060 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
4062 LDBase = cast<LoadSDNode>(Elt.getNode());
4066 if (Elt.getOpcode() == ISD::UNDEF)
4069 LoadSDNode *LD = cast<LoadSDNode>(Elt);
4070 if (!DAG.isConsecutiveLoad(LD, LDBase, EltVT.getSizeInBits()/8, i))
4075 // If we have found an entire vector of loads and undefs, then return a large
4076 // load of the entire vector width starting at the base pointer. If we found
4077 // consecutive loads for the low half, generate a vzext_load node.
4078 if (LastLoadedElt == NumElems - 1) {
4079 if (DAG.InferPtrAlignment(LDBase->getBasePtr()) >= 16)
4080 return DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
4081 LDBase->getPointerInfo(),
4082 LDBase->isVolatile(), LDBase->isNonTemporal(), 0);
4083 return DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
4084 LDBase->getPointerInfo(),
4085 LDBase->isVolatile(), LDBase->isNonTemporal(),
4086 LDBase->getAlignment());
4087 } else if (NumElems == 4 && LastLoadedElt == 1) {
4088 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
4089 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() };
4090 SDValue ResNode = DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys,
4092 LDBase->getMemOperand());
4093 return DAG.getNode(ISD::BIT_CONVERT, DL, VT, ResNode);
4099 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
4100 DebugLoc dl = Op.getDebugLoc();
4101 // All zero's are handled with pxor in SSE2 and above, xorps in SSE1.
4102 // All one's are handled with pcmpeqd. In AVX, zero's are handled with
4103 // vpxor in 128-bit and xor{pd,ps} in 256-bit, but no 256 version of pcmpeqd
4104 // is present, so AllOnes is ignored.
4105 if (ISD::isBuildVectorAllZeros(Op.getNode()) ||
4106 (Op.getValueType().getSizeInBits() != 256 &&
4107 ISD::isBuildVectorAllOnes(Op.getNode()))) {
4108 // Canonicalize this to <4 x i32> (SSE) to
4109 // 1) ensure the zero vectors are CSE'd, and 2) ensure that i64 scalars are
4110 // eliminated on x86-32 hosts.
4111 if (Op.getValueType() == MVT::v4i32)
4114 if (ISD::isBuildVectorAllOnes(Op.getNode()))
4115 return getOnesVector(Op.getValueType(), DAG, dl);
4116 return getZeroVector(Op.getValueType(), Subtarget->hasSSE2(), DAG, dl);
4119 EVT VT = Op.getValueType();
4120 EVT ExtVT = VT.getVectorElementType();
4121 unsigned EVTBits = ExtVT.getSizeInBits();
4123 unsigned NumElems = Op.getNumOperands();
4124 unsigned NumZero = 0;
4125 unsigned NumNonZero = 0;
4126 unsigned NonZeros = 0;
4127 bool IsAllConstants = true;
4128 SmallSet<SDValue, 8> Values;
4129 for (unsigned i = 0; i < NumElems; ++i) {
4130 SDValue Elt = Op.getOperand(i);
4131 if (Elt.getOpcode() == ISD::UNDEF)
4134 if (Elt.getOpcode() != ISD::Constant &&
4135 Elt.getOpcode() != ISD::ConstantFP)
4136 IsAllConstants = false;
4137 if (X86::isZeroNode(Elt))
4140 NonZeros |= (1 << i);
4145 // All undef vector. Return an UNDEF. All zero vectors were handled above.
4146 if (NumNonZero == 0)
4147 return DAG.getUNDEF(VT);
4149 // Special case for single non-zero, non-undef, element.
4150 if (NumNonZero == 1) {
4151 unsigned Idx = CountTrailingZeros_32(NonZeros);
4152 SDValue Item = Op.getOperand(Idx);
4154 // If this is an insertion of an i64 value on x86-32, and if the top bits of
4155 // the value are obviously zero, truncate the value to i32 and do the
4156 // insertion that way. Only do this if the value is non-constant or if the
4157 // value is a constant being inserted into element 0. It is cheaper to do
4158 // a constant pool load than it is to do a movd + shuffle.
4159 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
4160 (!IsAllConstants || Idx == 0)) {
4161 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
4163 assert(VT == MVT::v2i64 && "Expected an SSE value type!");
4164 EVT VecVT = MVT::v4i32;
4165 unsigned VecElts = 4;
4167 // Truncate the value (which may itself be a constant) to i32, and
4168 // convert it to a vector with movd (S2V+shuffle to zero extend).
4169 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
4170 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
4171 Item = getShuffleVectorZeroOrUndef(Item, 0, true,
4172 Subtarget->hasSSE2(), DAG);
4174 // Now we have our 32-bit value zero extended in the low element of
4175 // a vector. If Idx != 0, swizzle it into place.
4177 SmallVector<int, 4> Mask;
4178 Mask.push_back(Idx);
4179 for (unsigned i = 1; i != VecElts; ++i)
4181 Item = DAG.getVectorShuffle(VecVT, dl, Item,
4182 DAG.getUNDEF(Item.getValueType()),
4185 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Item);
4189 // If we have a constant or non-constant insertion into the low element of
4190 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
4191 // the rest of the elements. This will be matched as movd/movq/movss/movsd
4192 // depending on what the source datatype is.
4195 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
4196 } else if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
4197 (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
4198 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
4199 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
4200 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget->hasSSE2(),
4202 } else if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
4203 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
4204 assert(VT.getSizeInBits() == 128 && "Expected an SSE value type!");
4205 EVT MiddleVT = MVT::v4i32;
4206 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MiddleVT, Item);
4207 Item = getShuffleVectorZeroOrUndef(Item, 0, true,
4208 Subtarget->hasSSE2(), DAG);
4209 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Item);
4213 // Is it a vector logical left shift?
4214 if (NumElems == 2 && Idx == 1 &&
4215 X86::isZeroNode(Op.getOperand(0)) &&
4216 !X86::isZeroNode(Op.getOperand(1))) {
4217 unsigned NumBits = VT.getSizeInBits();
4218 return getVShift(true, VT,
4219 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
4220 VT, Op.getOperand(1)),
4221 NumBits/2, DAG, *this, dl);
4224 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
4227 // Otherwise, if this is a vector with i32 or f32 elements, and the element
4228 // is a non-constant being inserted into an element other than the low one,
4229 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
4230 // movd/movss) to move this into the low element, then shuffle it into
4232 if (EVTBits == 32) {
4233 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
4235 // Turn it into a shuffle of zero and zero-extended scalar to vector.
4236 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0,
4237 Subtarget->hasSSE2(), DAG);
4238 SmallVector<int, 8> MaskVec;
4239 for (unsigned i = 0; i < NumElems; i++)
4240 MaskVec.push_back(i == Idx ? 0 : 1);
4241 return DAG.getVectorShuffle(VT, dl, Item, DAG.getUNDEF(VT), &MaskVec[0]);
4245 // Splat is obviously ok. Let legalizer expand it to a shuffle.
4246 if (Values.size() == 1) {
4247 if (EVTBits == 32) {
4248 // Instead of a shuffle like this:
4249 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
4250 // Check if it's possible to issue this instead.
4251 // shuffle (vload ptr)), undef, <1, 1, 1, 1>
4252 unsigned Idx = CountTrailingZeros_32(NonZeros);
4253 SDValue Item = Op.getOperand(Idx);
4254 if (Op.getNode()->isOnlyUserOf(Item.getNode()))
4255 return LowerAsSplatVectorLoad(Item, VT, dl, DAG);
4260 // A vector full of immediates; various special cases are already
4261 // handled, so this is best done with a single constant-pool load.
4265 // Let legalizer expand 2-wide build_vectors.
4266 if (EVTBits == 64) {
4267 if (NumNonZero == 1) {
4268 // One half is zero or undef.
4269 unsigned Idx = CountTrailingZeros_32(NonZeros);
4270 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
4271 Op.getOperand(Idx));
4272 return getShuffleVectorZeroOrUndef(V2, Idx, true,
4273 Subtarget->hasSSE2(), DAG);
4278 // If element VT is < 32 bits, convert it to inserts into a zero vector.
4279 if (EVTBits == 8 && NumElems == 16) {
4280 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
4282 if (V.getNode()) return V;
4285 if (EVTBits == 16 && NumElems == 8) {
4286 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
4288 if (V.getNode()) return V;
4291 // If element VT is == 32 bits, turn it into a number of shuffles.
4292 SmallVector<SDValue, 8> V;
4294 if (NumElems == 4 && NumZero > 0) {
4295 for (unsigned i = 0; i < 4; ++i) {
4296 bool isZero = !(NonZeros & (1 << i));
4298 V[i] = getZeroVector(VT, Subtarget->hasSSE2(), DAG, dl);
4300 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
4303 for (unsigned i = 0; i < 2; ++i) {
4304 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
4307 V[i] = V[i*2]; // Must be a zero vector.
4310 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
4313 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
4316 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
4321 SmallVector<int, 8> MaskVec;
4322 bool Reverse = (NonZeros & 0x3) == 2;
4323 for (unsigned i = 0; i < 2; ++i)
4324 MaskVec.push_back(Reverse ? 1-i : i);
4325 Reverse = ((NonZeros & (0x3 << 2)) >> 2) == 2;
4326 for (unsigned i = 0; i < 2; ++i)
4327 MaskVec.push_back(Reverse ? 1-i+NumElems : i+NumElems);
4328 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
4331 if (Values.size() > 1 && VT.getSizeInBits() == 128) {
4332 // Check for a build vector of consecutive loads.
4333 for (unsigned i = 0; i < NumElems; ++i)
4334 V[i] = Op.getOperand(i);
4336 // Check for elements which are consecutive loads.
4337 SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG);
4341 // For SSE 4.1, use insertps to put the high elements into the low element.
4342 if (getSubtarget()->hasSSE41()) {
4344 if (Op.getOperand(0).getOpcode() != ISD::UNDEF)
4345 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0));
4347 Result = DAG.getUNDEF(VT);
4349 for (unsigned i = 1; i < NumElems; ++i) {
4350 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue;
4351 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result,
4352 Op.getOperand(i), DAG.getIntPtrConstant(i));
4357 // Otherwise, expand into a number of unpckl*, start by extending each of
4358 // our (non-undef) elements to the full vector width with the element in the
4359 // bottom slot of the vector (which generates no code for SSE).
4360 for (unsigned i = 0; i < NumElems; ++i) {
4361 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
4362 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
4364 V[i] = DAG.getUNDEF(VT);
4367 // Next, we iteratively mix elements, e.g. for v4f32:
4368 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
4369 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
4370 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
4371 unsigned EltStride = NumElems >> 1;
4372 while (EltStride != 0) {
4373 for (unsigned i = 0; i < EltStride; ++i) {
4374 // If V[i+EltStride] is undef and this is the first round of mixing,
4375 // then it is safe to just drop this shuffle: V[i] is already in the
4376 // right place, the one element (since it's the first round) being
4377 // inserted as undef can be dropped. This isn't safe for successive
4378 // rounds because they will permute elements within both vectors.
4379 if (V[i+EltStride].getOpcode() == ISD::UNDEF &&
4380 EltStride == NumElems/2)
4383 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]);
4393 X86TargetLowering::LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const {
4394 // We support concatenate two MMX registers and place them in a MMX
4395 // register. This is better than doing a stack convert.
4396 DebugLoc dl = Op.getDebugLoc();
4397 EVT ResVT = Op.getValueType();
4398 assert(Op.getNumOperands() == 2);
4399 assert(ResVT == MVT::v2i64 || ResVT == MVT::v4i32 ||
4400 ResVT == MVT::v8i16 || ResVT == MVT::v16i8);
4402 SDValue InVec = DAG.getNode(ISD::BIT_CONVERT,dl, MVT::v1i64, Op.getOperand(0));
4403 SDValue VecOp = DAG.getNode(X86ISD::MOVQ2DQ, dl, MVT::v2i64, InVec);
4404 InVec = Op.getOperand(1);
4405 if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR) {
4406 unsigned NumElts = ResVT.getVectorNumElements();
4407 VecOp = DAG.getNode(ISD::BIT_CONVERT, dl, ResVT, VecOp);
4408 VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ResVT, VecOp,
4409 InVec.getOperand(0), DAG.getIntPtrConstant(NumElts/2+1));
4411 InVec = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v1i64, InVec);
4412 SDValue VecOp2 = DAG.getNode(X86ISD::MOVQ2DQ, dl, MVT::v2i64, InVec);
4413 Mask[0] = 0; Mask[1] = 2;
4414 VecOp = DAG.getVectorShuffle(MVT::v2i64, dl, VecOp, VecOp2, Mask);
4416 return DAG.getNode(ISD::BIT_CONVERT, dl, ResVT, VecOp);
4419 // v8i16 shuffles - Prefer shuffles in the following order:
4420 // 1. [all] pshuflw, pshufhw, optional move
4421 // 2. [ssse3] 1 x pshufb
4422 // 3. [ssse3] 2 x pshufb + 1 x por
4423 // 4. [all] mov + pshuflw + pshufhw + N x (pextrw + pinsrw)
4425 X86TargetLowering::LowerVECTOR_SHUFFLEv8i16(SDValue Op,
4426 SelectionDAG &DAG) const {
4427 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
4428 SDValue V1 = SVOp->getOperand(0);
4429 SDValue V2 = SVOp->getOperand(1);
4430 DebugLoc dl = SVOp->getDebugLoc();
4431 SmallVector<int, 8> MaskVals;
4433 // Determine if more than 1 of the words in each of the low and high quadwords
4434 // of the result come from the same quadword of one of the two inputs. Undef
4435 // mask values count as coming from any quadword, for better codegen.
4436 SmallVector<unsigned, 4> LoQuad(4);
4437 SmallVector<unsigned, 4> HiQuad(4);
4438 BitVector InputQuads(4);
4439 for (unsigned i = 0; i < 8; ++i) {
4440 SmallVectorImpl<unsigned> &Quad = i < 4 ? LoQuad : HiQuad;
4441 int EltIdx = SVOp->getMaskElt(i);
4442 MaskVals.push_back(EltIdx);
4451 InputQuads.set(EltIdx / 4);
4454 int BestLoQuad = -1;
4455 unsigned MaxQuad = 1;
4456 for (unsigned i = 0; i < 4; ++i) {
4457 if (LoQuad[i] > MaxQuad) {
4459 MaxQuad = LoQuad[i];
4463 int BestHiQuad = -1;
4465 for (unsigned i = 0; i < 4; ++i) {
4466 if (HiQuad[i] > MaxQuad) {
4468 MaxQuad = HiQuad[i];
4472 // For SSSE3, If all 8 words of the result come from only 1 quadword of each
4473 // of the two input vectors, shuffle them into one input vector so only a
4474 // single pshufb instruction is necessary. If There are more than 2 input
4475 // quads, disable the next transformation since it does not help SSSE3.
4476 bool V1Used = InputQuads[0] || InputQuads[1];
4477 bool V2Used = InputQuads[2] || InputQuads[3];
4478 if (Subtarget->hasSSSE3()) {
4479 if (InputQuads.count() == 2 && V1Used && V2Used) {
4480 BestLoQuad = InputQuads.find_first();
4481 BestHiQuad = InputQuads.find_next(BestLoQuad);
4483 if (InputQuads.count() > 2) {
4489 // If BestLoQuad or BestHiQuad are set, shuffle the quads together and update
4490 // the shuffle mask. If a quad is scored as -1, that means that it contains
4491 // words from all 4 input quadwords.
4493 if (BestLoQuad >= 0 || BestHiQuad >= 0) {
4494 SmallVector<int, 8> MaskV;
4495 MaskV.push_back(BestLoQuad < 0 ? 0 : BestLoQuad);
4496 MaskV.push_back(BestHiQuad < 0 ? 1 : BestHiQuad);
4497 NewV = DAG.getVectorShuffle(MVT::v2i64, dl,
4498 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64, V1),
4499 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64, V2), &MaskV[0]);
4500 NewV = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, NewV);
4502 // Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the
4503 // source words for the shuffle, to aid later transformations.
4504 bool AllWordsInNewV = true;
4505 bool InOrder[2] = { true, true };
4506 for (unsigned i = 0; i != 8; ++i) {
4507 int idx = MaskVals[i];
4509 InOrder[i/4] = false;
4510 if (idx < 0 || (idx/4) == BestLoQuad || (idx/4) == BestHiQuad)
4512 AllWordsInNewV = false;
4516 bool pshuflw = AllWordsInNewV, pshufhw = AllWordsInNewV;
4517 if (AllWordsInNewV) {
4518 for (int i = 0; i != 8; ++i) {
4519 int idx = MaskVals[i];
4522 idx = MaskVals[i] = (idx / 4) == BestLoQuad ? (idx & 3) : (idx & 3) + 4;
4523 if ((idx != i) && idx < 4)
4525 if ((idx != i) && idx > 3)
4534 // If we've eliminated the use of V2, and the new mask is a pshuflw or
4535 // pshufhw, that's as cheap as it gets. Return the new shuffle.
4536 if ((pshufhw && InOrder[0]) || (pshuflw && InOrder[1])) {
4537 unsigned Opc = pshufhw ? X86ISD::PSHUFHW : X86ISD::PSHUFLW;
4538 unsigned TargetMask = 0;
4539 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV,
4540 DAG.getUNDEF(MVT::v8i16), &MaskVals[0]);
4541 TargetMask = pshufhw ? X86::getShufflePSHUFHWImmediate(NewV.getNode()):
4542 X86::getShufflePSHUFLWImmediate(NewV.getNode());
4543 V1 = NewV.getOperand(0);
4544 return getTargetShuffleNode(Opc, dl, MVT::v8i16, V1, TargetMask, DAG);
4548 // If we have SSSE3, and all words of the result are from 1 input vector,
4549 // case 2 is generated, otherwise case 3 is generated. If no SSSE3
4550 // is present, fall back to case 4.
4551 if (Subtarget->hasSSSE3()) {
4552 SmallVector<SDValue,16> pshufbMask;
4554 // If we have elements from both input vectors, set the high bit of the
4555 // shuffle mask element to zero out elements that come from V2 in the V1
4556 // mask, and elements that come from V1 in the V2 mask, so that the two
4557 // results can be OR'd together.
4558 bool TwoInputs = V1Used && V2Used;
4559 for (unsigned i = 0; i != 8; ++i) {
4560 int EltIdx = MaskVals[i] * 2;
4561 if (TwoInputs && (EltIdx >= 16)) {
4562 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
4563 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
4566 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
4567 pshufbMask.push_back(DAG.getConstant(EltIdx+1, MVT::i8));
4569 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, V1);
4570 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
4571 DAG.getNode(ISD::BUILD_VECTOR, dl,
4572 MVT::v16i8, &pshufbMask[0], 16));
4574 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, V1);
4576 // Calculate the shuffle mask for the second input, shuffle it, and
4577 // OR it with the first shuffled input.
4579 for (unsigned i = 0; i != 8; ++i) {
4580 int EltIdx = MaskVals[i] * 2;
4582 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
4583 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
4586 pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8));
4587 pshufbMask.push_back(DAG.getConstant(EltIdx - 15, MVT::i8));
4589 V2 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, V2);
4590 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
4591 DAG.getNode(ISD::BUILD_VECTOR, dl,
4592 MVT::v16i8, &pshufbMask[0], 16));
4593 V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
4594 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, V1);
4597 // If BestLoQuad >= 0, generate a pshuflw to put the low elements in order,
4598 // and update MaskVals with new element order.
4599 BitVector InOrder(8);
4600 if (BestLoQuad >= 0) {
4601 SmallVector<int, 8> MaskV;
4602 for (int i = 0; i != 4; ++i) {
4603 int idx = MaskVals[i];
4605 MaskV.push_back(-1);
4607 } else if ((idx / 4) == BestLoQuad) {
4608 MaskV.push_back(idx & 3);
4611 MaskV.push_back(-1);
4614 for (unsigned i = 4; i != 8; ++i)
4616 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
4619 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSSE3())
4620 NewV = getTargetShuffleNode(X86ISD::PSHUFLW, dl, MVT::v8i16,
4622 X86::getShufflePSHUFLWImmediate(NewV.getNode()),
4626 // If BestHi >= 0, generate a pshufhw to put the high elements in order,
4627 // and update MaskVals with the new element order.
4628 if (BestHiQuad >= 0) {
4629 SmallVector<int, 8> MaskV;
4630 for (unsigned i = 0; i != 4; ++i)
4632 for (unsigned i = 4; i != 8; ++i) {
4633 int idx = MaskVals[i];
4635 MaskV.push_back(-1);
4637 } else if ((idx / 4) == BestHiQuad) {
4638 MaskV.push_back((idx & 3) + 4);
4641 MaskV.push_back(-1);
4644 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
4647 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSSE3())
4648 NewV = getTargetShuffleNode(X86ISD::PSHUFHW, dl, MVT::v8i16,
4650 X86::getShufflePSHUFHWImmediate(NewV.getNode()),
4654 // In case BestHi & BestLo were both -1, which means each quadword has a word
4655 // from each of the four input quadwords, calculate the InOrder bitvector now
4656 // before falling through to the insert/extract cleanup.
4657 if (BestLoQuad == -1 && BestHiQuad == -1) {
4659 for (int i = 0; i != 8; ++i)
4660 if (MaskVals[i] < 0 || MaskVals[i] == i)
4664 // The other elements are put in the right place using pextrw and pinsrw.
4665 for (unsigned i = 0; i != 8; ++i) {
4668 int EltIdx = MaskVals[i];
4671 SDValue ExtOp = (EltIdx < 8)
4672 ? DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1,
4673 DAG.getIntPtrConstant(EltIdx))
4674 : DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2,
4675 DAG.getIntPtrConstant(EltIdx - 8));
4676 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp,
4677 DAG.getIntPtrConstant(i));
4682 // v16i8 shuffles - Prefer shuffles in the following order:
4683 // 1. [ssse3] 1 x pshufb
4684 // 2. [ssse3] 2 x pshufb + 1 x por
4685 // 3. [all] v8i16 shuffle + N x pextrw + rotate + pinsrw
4687 SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp,
4689 const X86TargetLowering &TLI) {
4690 SDValue V1 = SVOp->getOperand(0);
4691 SDValue V2 = SVOp->getOperand(1);
4692 DebugLoc dl = SVOp->getDebugLoc();
4693 SmallVector<int, 16> MaskVals;
4694 SVOp->getMask(MaskVals);
4696 // If we have SSSE3, case 1 is generated when all result bytes come from
4697 // one of the inputs. Otherwise, case 2 is generated. If no SSSE3 is
4698 // present, fall back to case 3.
4699 // FIXME: kill V2Only once shuffles are canonizalized by getNode.
4702 for (unsigned i = 0; i < 16; ++i) {
4703 int EltIdx = MaskVals[i];
4712 // If SSSE3, use 1 pshufb instruction per vector with elements in the result.
4713 if (TLI.getSubtarget()->hasSSSE3()) {
4714 SmallVector<SDValue,16> pshufbMask;
4716 // If all result elements are from one input vector, then only translate
4717 // undef mask values to 0x80 (zero out result) in the pshufb mask.
4719 // Otherwise, we have elements from both input vectors, and must zero out
4720 // elements that come from V2 in the first mask, and V1 in the second mask
4721 // so that we can OR them together.
4722 bool TwoInputs = !(V1Only || V2Only);
4723 for (unsigned i = 0; i != 16; ++i) {
4724 int EltIdx = MaskVals[i];
4725 if (EltIdx < 0 || (TwoInputs && EltIdx >= 16)) {
4726 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
4729 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
4731 // If all the elements are from V2, assign it to V1 and return after
4732 // building the first pshufb.
4735 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
4736 DAG.getNode(ISD::BUILD_VECTOR, dl,
4737 MVT::v16i8, &pshufbMask[0], 16));
4741 // Calculate the shuffle mask for the second input, shuffle it, and
4742 // OR it with the first shuffled input.
4744 for (unsigned i = 0; i != 16; ++i) {
4745 int EltIdx = MaskVals[i];
4747 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
4750 pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8));
4752 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
4753 DAG.getNode(ISD::BUILD_VECTOR, dl,
4754 MVT::v16i8, &pshufbMask[0], 16));
4755 return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
4758 // No SSSE3 - Calculate in place words and then fix all out of place words
4759 // With 0-16 extracts & inserts. Worst case is 16 bytes out of order from
4760 // the 16 different words that comprise the two doublequadword input vectors.
4761 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, V1);
4762 V2 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, V2);
4763 SDValue NewV = V2Only ? V2 : V1;
4764 for (int i = 0; i != 8; ++i) {
4765 int Elt0 = MaskVals[i*2];
4766 int Elt1 = MaskVals[i*2+1];
4768 // This word of the result is all undef, skip it.
4769 if (Elt0 < 0 && Elt1 < 0)
4772 // This word of the result is already in the correct place, skip it.
4773 if (V1Only && (Elt0 == i*2) && (Elt1 == i*2+1))
4775 if (V2Only && (Elt0 == i*2+16) && (Elt1 == i*2+17))
4778 SDValue Elt0Src = Elt0 < 16 ? V1 : V2;
4779 SDValue Elt1Src = Elt1 < 16 ? V1 : V2;
4782 // If Elt0 and Elt1 are defined, are consecutive, and can be load
4783 // using a single extract together, load it and store it.
4784 if ((Elt0 >= 0) && ((Elt0 + 1) == Elt1) && ((Elt0 & 1) == 0)) {
4785 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
4786 DAG.getIntPtrConstant(Elt1 / 2));
4787 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
4788 DAG.getIntPtrConstant(i));
4792 // If Elt1 is defined, extract it from the appropriate source. If the
4793 // source byte is not also odd, shift the extracted word left 8 bits
4794 // otherwise clear the bottom 8 bits if we need to do an or.
4796 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
4797 DAG.getIntPtrConstant(Elt1 / 2));
4798 if ((Elt1 & 1) == 0)
4799 InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt,
4800 DAG.getConstant(8, TLI.getShiftAmountTy()));
4802 InsElt = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt,
4803 DAG.getConstant(0xFF00, MVT::i16));
4805 // If Elt0 is defined, extract it from the appropriate source. If the
4806 // source byte is not also even, shift the extracted word right 8 bits. If
4807 // Elt1 was also defined, OR the extracted values together before
4808 // inserting them in the result.
4810 SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16,
4811 Elt0Src, DAG.getIntPtrConstant(Elt0 / 2));
4812 if ((Elt0 & 1) != 0)
4813 InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0,
4814 DAG.getConstant(8, TLI.getShiftAmountTy()));
4816 InsElt0 = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt0,
4817 DAG.getConstant(0x00FF, MVT::i16));
4818 InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0)
4821 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
4822 DAG.getIntPtrConstant(i));
4824 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, NewV);
4827 /// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide
4828 /// ones, or rewriting v4i32 / v4f32 as 2 wide ones if possible. This can be
4829 /// done when every pair / quad of shuffle mask elements point to elements in
4830 /// the right sequence. e.g.
4831 /// vector_shuffle X, Y, <2, 3, | 10, 11, | 0, 1, | 14, 15>
4833 SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp,
4834 SelectionDAG &DAG, DebugLoc dl) {
4835 EVT VT = SVOp->getValueType(0);
4836 SDValue V1 = SVOp->getOperand(0);
4837 SDValue V2 = SVOp->getOperand(1);
4838 unsigned NumElems = VT.getVectorNumElements();
4839 unsigned NewWidth = (NumElems == 4) ? 2 : 4;
4841 switch (VT.getSimpleVT().SimpleTy) {
4842 default: assert(false && "Unexpected!");
4843 case MVT::v4f32: NewVT = MVT::v2f64; break;
4844 case MVT::v4i32: NewVT = MVT::v2i64; break;
4845 case MVT::v8i16: NewVT = MVT::v4i32; break;
4846 case MVT::v16i8: NewVT = MVT::v4i32; break;
4849 int Scale = NumElems / NewWidth;
4850 SmallVector<int, 8> MaskVec;
4851 for (unsigned i = 0; i < NumElems; i += Scale) {
4853 for (int j = 0; j < Scale; ++j) {
4854 int EltIdx = SVOp->getMaskElt(i+j);
4858 StartIdx = EltIdx - (EltIdx % Scale);
4859 if (EltIdx != StartIdx + j)
4863 MaskVec.push_back(-1);
4865 MaskVec.push_back(StartIdx / Scale);
4868 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, NewVT, V1);
4869 V2 = DAG.getNode(ISD::BIT_CONVERT, dl, NewVT, V2);
4870 return DAG.getVectorShuffle(NewVT, dl, V1, V2, &MaskVec[0]);
4873 /// getVZextMovL - Return a zero-extending vector move low node.
4875 static SDValue getVZextMovL(EVT VT, EVT OpVT,
4876 SDValue SrcOp, SelectionDAG &DAG,
4877 const X86Subtarget *Subtarget, DebugLoc dl) {
4878 if (VT == MVT::v2f64 || VT == MVT::v4f32) {
4879 LoadSDNode *LD = NULL;
4880 if (!isScalarLoadToVector(SrcOp.getNode(), &LD))
4881 LD = dyn_cast<LoadSDNode>(SrcOp);
4883 // movssrr and movsdrr do not clear top bits. Try to use movd, movq
4885 MVT ExtVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32;
4886 if ((ExtVT != MVT::i64 || Subtarget->is64Bit()) &&
4887 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR &&
4888 SrcOp.getOperand(0).getOpcode() == ISD::BIT_CONVERT &&
4889 SrcOp.getOperand(0).getOperand(0).getValueType() == ExtVT) {
4891 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32;
4892 return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
4893 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
4894 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
4902 return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
4903 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
4904 DAG.getNode(ISD::BIT_CONVERT, dl,
4908 /// LowerVECTOR_SHUFFLE_4wide - Handle all 4 wide cases with a number of
4911 LowerVECTOR_SHUFFLE_4wide(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
4912 SDValue V1 = SVOp->getOperand(0);
4913 SDValue V2 = SVOp->getOperand(1);
4914 DebugLoc dl = SVOp->getDebugLoc();
4915 EVT VT = SVOp->getValueType(0);
4917 SmallVector<std::pair<int, int>, 8> Locs;
4919 SmallVector<int, 8> Mask1(4U, -1);
4920 SmallVector<int, 8> PermMask;
4921 SVOp->getMask(PermMask);
4925 for (unsigned i = 0; i != 4; ++i) {
4926 int Idx = PermMask[i];
4928 Locs[i] = std::make_pair(-1, -1);
4930 assert(Idx < 8 && "Invalid VECTOR_SHUFFLE index!");
4932 Locs[i] = std::make_pair(0, NumLo);
4936 Locs[i] = std::make_pair(1, NumHi);
4938 Mask1[2+NumHi] = Idx;
4944 if (NumLo <= 2 && NumHi <= 2) {
4945 // If no more than two elements come from either vector. This can be
4946 // implemented with two shuffles. First shuffle gather the elements.
4947 // The second shuffle, which takes the first shuffle as both of its
4948 // vector operands, put the elements into the right order.
4949 V1 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
4951 SmallVector<int, 8> Mask2(4U, -1);
4953 for (unsigned i = 0; i != 4; ++i) {
4954 if (Locs[i].first == -1)
4957 unsigned Idx = (i < 2) ? 0 : 4;
4958 Idx += Locs[i].first * 2 + Locs[i].second;
4963 return DAG.getVectorShuffle(VT, dl, V1, V1, &Mask2[0]);
4964 } else if (NumLo == 3 || NumHi == 3) {
4965 // Otherwise, we must have three elements from one vector, call it X, and
4966 // one element from the other, call it Y. First, use a shufps to build an
4967 // intermediate vector with the one element from Y and the element from X
4968 // that will be in the same half in the final destination (the indexes don't
4969 // matter). Then, use a shufps to build the final vector, taking the half
4970 // containing the element from Y from the intermediate, and the other half
4973 // Normalize it so the 3 elements come from V1.
4974 CommuteVectorShuffleMask(PermMask, VT);
4978 // Find the element from V2.
4980 for (HiIndex = 0; HiIndex < 3; ++HiIndex) {
4981 int Val = PermMask[HiIndex];
4988 Mask1[0] = PermMask[HiIndex];
4990 Mask1[2] = PermMask[HiIndex^1];
4992 V2 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
4995 Mask1[0] = PermMask[0];
4996 Mask1[1] = PermMask[1];
4997 Mask1[2] = HiIndex & 1 ? 6 : 4;
4998 Mask1[3] = HiIndex & 1 ? 4 : 6;
4999 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
5001 Mask1[0] = HiIndex & 1 ? 2 : 0;
5002 Mask1[1] = HiIndex & 1 ? 0 : 2;
5003 Mask1[2] = PermMask[2];
5004 Mask1[3] = PermMask[3];
5009 return DAG.getVectorShuffle(VT, dl, V2, V1, &Mask1[0]);
5013 // Break it into (shuffle shuffle_hi, shuffle_lo).
5015 SmallVector<int,8> LoMask(4U, -1);
5016 SmallVector<int,8> HiMask(4U, -1);
5018 SmallVector<int,8> *MaskPtr = &LoMask;
5019 unsigned MaskIdx = 0;
5022 for (unsigned i = 0; i != 4; ++i) {
5029 int Idx = PermMask[i];
5031 Locs[i] = std::make_pair(-1, -1);
5032 } else if (Idx < 4) {
5033 Locs[i] = std::make_pair(MaskIdx, LoIdx);
5034 (*MaskPtr)[LoIdx] = Idx;
5037 Locs[i] = std::make_pair(MaskIdx, HiIdx);
5038 (*MaskPtr)[HiIdx] = Idx;
5043 SDValue LoShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &LoMask[0]);
5044 SDValue HiShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &HiMask[0]);
5045 SmallVector<int, 8> MaskOps;
5046 for (unsigned i = 0; i != 4; ++i) {
5047 if (Locs[i].first == -1) {
5048 MaskOps.push_back(-1);
5050 unsigned Idx = Locs[i].first * 4 + Locs[i].second;
5051 MaskOps.push_back(Idx);
5054 return DAG.getVectorShuffle(VT, dl, LoShuffle, HiShuffle, &MaskOps[0]);
5057 static bool MayFoldVectorLoad(SDValue V) {
5058 if (V.hasOneUse() && V.getOpcode() == ISD::BIT_CONVERT)
5059 V = V.getOperand(0);
5060 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR)
5061 V = V.getOperand(0);
5067 // FIXME: the version above should always be used. Since there's
5068 // a bug where several vector shuffles can't be folded because the
5069 // DAG is not updated during lowering and a node claims to have two
5070 // uses while it only has one, use this version, and let isel match
5071 // another instruction if the load really happens to have more than
5072 // one use. Remove this version after this bug get fixed.
5073 // rdar://8434668, PR8156
5074 static bool RelaxedMayFoldVectorLoad(SDValue V) {
5075 if (V.hasOneUse() && V.getOpcode() == ISD::BIT_CONVERT)
5076 V = V.getOperand(0);
5077 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR)
5078 V = V.getOperand(0);
5079 if (ISD::isNormalLoad(V.getNode()))
5084 /// CanFoldShuffleIntoVExtract - Check if the current shuffle is used by
5085 /// a vector extract, and if both can be later optimized into a single load.
5086 /// This is done in visitEXTRACT_VECTOR_ELT and the conditions are checked
5087 /// here because otherwise a target specific shuffle node is going to be
5088 /// emitted for this shuffle, and the optimization not done.
5089 /// FIXME: This is probably not the best approach, but fix the problem
5090 /// until the right path is decided.
5092 bool CanXFormVExtractWithShuffleIntoLoad(SDValue V, SelectionDAG &DAG,
5093 const TargetLowering &TLI) {
5094 EVT VT = V.getValueType();
5095 ShuffleVectorSDNode *SVOp = dyn_cast<ShuffleVectorSDNode>(V);
5097 // Be sure that the vector shuffle is present in a pattern like this:
5098 // (vextract (v4f32 shuffle (load $addr), <1,u,u,u>), c) -> (f32 load $addr)
5102 SDNode *N = *V.getNode()->use_begin();
5103 if (N->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
5106 SDValue EltNo = N->getOperand(1);
5107 if (!isa<ConstantSDNode>(EltNo))
5110 // If the bit convert changed the number of elements, it is unsafe
5111 // to examine the mask.
5112 bool HasShuffleIntoBitcast = false;
5113 if (V.getOpcode() == ISD::BIT_CONVERT) {
5114 EVT SrcVT = V.getOperand(0).getValueType();
5115 if (SrcVT.getVectorNumElements() != VT.getVectorNumElements())
5117 V = V.getOperand(0);
5118 HasShuffleIntoBitcast = true;
5121 // Select the input vector, guarding against out of range extract vector.
5122 unsigned NumElems = VT.getVectorNumElements();
5123 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
5124 int Idx = (Elt > NumElems) ? -1 : SVOp->getMaskElt(Elt);
5125 V = (Idx < (int)NumElems) ? V.getOperand(0) : V.getOperand(1);
5127 // Skip one more bit_convert if necessary
5128 if (V.getOpcode() == ISD::BIT_CONVERT)
5129 V = V.getOperand(0);
5131 if (ISD::isNormalLoad(V.getNode())) {
5132 // Is the original load suitable?
5133 LoadSDNode *LN0 = cast<LoadSDNode>(V);
5135 // FIXME: avoid the multi-use bug that is preventing lots of
5136 // of foldings to be detected, this is still wrong of course, but
5137 // give the temporary desired behavior, and if it happens that
5138 // the load has real more uses, during isel it will not fold, and
5139 // will generate poor code.
5140 if (!LN0 || LN0->isVolatile()) // || !LN0->hasOneUse()
5143 if (!HasShuffleIntoBitcast)
5146 // If there's a bitcast before the shuffle, check if the load type and
5147 // alignment is valid.
5148 unsigned Align = LN0->getAlignment();
5150 TLI.getTargetData()->getABITypeAlignment(
5151 VT.getTypeForEVT(*DAG.getContext()));
5153 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, VT))
5161 SDValue getMOVDDup(SDValue &Op, DebugLoc &dl, SDValue V1, SelectionDAG &DAG) {
5162 EVT VT = Op.getValueType();
5164 // Canonizalize to v2f64.
5165 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f64, V1);
5166 return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
5167 getTargetShuffleNode(X86ISD::MOVDDUP, dl, MVT::v2f64,
5172 SDValue getMOVLowToHigh(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG,
5174 SDValue V1 = Op.getOperand(0);
5175 SDValue V2 = Op.getOperand(1);
5176 EVT VT = Op.getValueType();
5178 assert(VT != MVT::v2i64 && "unsupported shuffle type");
5180 if (HasSSE2 && VT == MVT::v2f64)
5181 return getTargetShuffleNode(X86ISD::MOVLHPD, dl, VT, V1, V2, DAG);
5184 return getTargetShuffleNode(X86ISD::MOVLHPS, dl, VT, V1, V2, DAG);
5188 SDValue getMOVHighToLow(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG) {
5189 SDValue V1 = Op.getOperand(0);
5190 SDValue V2 = Op.getOperand(1);
5191 EVT VT = Op.getValueType();
5193 assert((VT == MVT::v4i32 || VT == MVT::v4f32) &&
5194 "unsupported shuffle type");
5196 if (V2.getOpcode() == ISD::UNDEF)
5200 return getTargetShuffleNode(X86ISD::MOVHLPS, dl, VT, V1, V2, DAG);
5204 SDValue getMOVLP(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG, bool HasSSE2) {
5205 SDValue V1 = Op.getOperand(0);
5206 SDValue V2 = Op.getOperand(1);
5207 EVT VT = Op.getValueType();
5208 unsigned NumElems = VT.getVectorNumElements();
5210 // Use MOVLPS and MOVLPD in case V1 or V2 are loads. During isel, the second
5211 // operand of these instructions is only memory, so check if there's a
5212 // potencial load folding here, otherwise use SHUFPS or MOVSD to match the
5214 bool CanFoldLoad = false;
5216 // Trivial case, when V2 comes from a load.
5217 if (MayFoldVectorLoad(V2))
5220 // When V1 is a load, it can be folded later into a store in isel, example:
5221 // (store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)), addr:$src1)
5223 // (MOVLPSmr addr:$src1, VR128:$src2)
5224 // So, recognize this potential and also use MOVLPS or MOVLPD
5225 if (MayFoldVectorLoad(V1) && MayFoldIntoStore(Op))
5229 if (HasSSE2 && NumElems == 2)
5230 return getTargetShuffleNode(X86ISD::MOVLPD, dl, VT, V1, V2, DAG);
5233 return getTargetShuffleNode(X86ISD::MOVLPS, dl, VT, V1, V2, DAG);
5236 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
5237 // movl and movlp will both match v2i64, but v2i64 is never matched by
5238 // movl earlier because we make it strict to avoid messing with the movlp load
5239 // folding logic (see the code above getMOVLP call). Match it here then,
5240 // this is horrible, but will stay like this until we move all shuffle
5241 // matching to x86 specific nodes. Note that for the 1st condition all
5242 // types are matched with movsd.
5243 if ((HasSSE2 && NumElems == 2) || !X86::isMOVLMask(SVOp))
5244 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
5246 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
5249 assert(VT != MVT::v4i32 && "unsupported shuffle type");
5251 // Invert the operand order and use SHUFPS to match it.
5252 return getTargetShuffleNode(X86ISD::SHUFPS, dl, VT, V2, V1,
5253 X86::getShuffleSHUFImmediate(SVOp), DAG);
5256 static inline unsigned getUNPCKLOpcode(EVT VT) {
5257 switch(VT.getSimpleVT().SimpleTy) {
5258 case MVT::v4i32: return X86ISD::PUNPCKLDQ;
5259 case MVT::v2i64: return X86ISD::PUNPCKLQDQ;
5260 case MVT::v4f32: return X86ISD::UNPCKLPS;
5261 case MVT::v2f64: return X86ISD::UNPCKLPD;
5262 case MVT::v16i8: return X86ISD::PUNPCKLBW;
5263 case MVT::v8i16: return X86ISD::PUNPCKLWD;
5265 llvm_unreachable("Unknow type for unpckl");
5270 static inline unsigned getUNPCKHOpcode(EVT VT) {
5271 switch(VT.getSimpleVT().SimpleTy) {
5272 case MVT::v4i32: return X86ISD::PUNPCKHDQ;
5273 case MVT::v2i64: return X86ISD::PUNPCKHQDQ;
5274 case MVT::v4f32: return X86ISD::UNPCKHPS;
5275 case MVT::v2f64: return X86ISD::UNPCKHPD;
5276 case MVT::v16i8: return X86ISD::PUNPCKHBW;
5277 case MVT::v8i16: return X86ISD::PUNPCKHWD;
5279 llvm_unreachable("Unknow type for unpckh");
5285 SDValue NormalizeVectorShuffle(SDValue Op, SelectionDAG &DAG,
5286 const TargetLowering &TLI,
5287 const X86Subtarget *Subtarget) {
5288 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
5289 EVT VT = Op.getValueType();
5290 DebugLoc dl = Op.getDebugLoc();
5291 SDValue V1 = Op.getOperand(0);
5292 SDValue V2 = Op.getOperand(1);
5294 if (isZeroShuffle(SVOp))
5295 return getZeroVector(VT, Subtarget->hasSSE2(), DAG, dl);
5297 // Handle splat operations
5298 if (SVOp->isSplat()) {
5299 // Special case, this is the only place now where it's
5300 // allowed to return a vector_shuffle operation without
5301 // using a target specific node, because *hopefully* it
5302 // will be optimized away by the dag combiner.
5303 if (VT.getVectorNumElements() <= 4 &&
5304 CanXFormVExtractWithShuffleIntoLoad(Op, DAG, TLI))
5307 // Handle splats by matching through known masks
5308 if (VT.getVectorNumElements() <= 4)
5311 // Canonicalize all of the remaining to v4f32.
5312 return PromoteSplat(SVOp, DAG);
5315 // If the shuffle can be profitably rewritten as a narrower shuffle, then
5317 if (VT == MVT::v8i16 || VT == MVT::v16i8) {
5318 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl);
5319 if (NewOp.getNode())
5320 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, NewOp);
5321 } else if ((VT == MVT::v4i32 || (VT == MVT::v4f32 && Subtarget->hasSSE2()))) {
5322 // FIXME: Figure out a cleaner way to do this.
5323 // Try to make use of movq to zero out the top part.
5324 if (ISD::isBuildVectorAllZeros(V2.getNode())) {
5325 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl);
5326 if (NewOp.getNode()) {
5327 if (isCommutedMOVL(cast<ShuffleVectorSDNode>(NewOp), true, false))
5328 return getVZextMovL(VT, NewOp.getValueType(), NewOp.getOperand(0),
5329 DAG, Subtarget, dl);
5331 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) {
5332 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl);
5333 if (NewOp.getNode() && X86::isMOVLMask(cast<ShuffleVectorSDNode>(NewOp)))
5334 return getVZextMovL(VT, NewOp.getValueType(), NewOp.getOperand(1),
5335 DAG, Subtarget, dl);
5342 X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const {
5343 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
5344 SDValue V1 = Op.getOperand(0);
5345 SDValue V2 = Op.getOperand(1);
5346 EVT VT = Op.getValueType();
5347 DebugLoc dl = Op.getDebugLoc();
5348 unsigned NumElems = VT.getVectorNumElements();
5349 bool isMMX = VT.getSizeInBits() == 64;
5350 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
5351 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
5352 bool V1IsSplat = false;
5353 bool V2IsSplat = false;
5354 bool HasSSE2 = Subtarget->hasSSE2() || Subtarget->hasAVX();
5355 bool HasSSE3 = Subtarget->hasSSE3() || Subtarget->hasAVX();
5356 bool HasSSSE3 = Subtarget->hasSSSE3() || Subtarget->hasAVX();
5357 MachineFunction &MF = DAG.getMachineFunction();
5358 bool OptForSize = MF.getFunction()->hasFnAttr(Attribute::OptimizeForSize);
5360 // Shuffle operations on MMX not supported.
5364 // Vector shuffle lowering takes 3 steps:
5366 // 1) Normalize the input vectors. Here splats, zeroed vectors, profitable
5367 // narrowing and commutation of operands should be handled.
5368 // 2) Matching of shuffles with known shuffle masks to x86 target specific
5370 // 3) Rewriting of unmatched masks into new generic shuffle operations,
5371 // so the shuffle can be broken into other shuffles and the legalizer can
5372 // try the lowering again.
5374 // The general ideia is that no vector_shuffle operation should be left to
5375 // be matched during isel, all of them must be converted to a target specific
5378 // Normalize the input vectors. Here splats, zeroed vectors, profitable
5379 // narrowing and commutation of operands should be handled. The actual code
5380 // doesn't include all of those, work in progress...
5381 SDValue NewOp = NormalizeVectorShuffle(Op, DAG, *this, Subtarget);
5382 if (NewOp.getNode())
5385 // NOTE: isPSHUFDMask can also match both masks below (unpckl_undef and
5386 // unpckh_undef). Only use pshufd if speed is more important than size.
5387 if (OptForSize && X86::isUNPCKL_v_undef_Mask(SVOp))
5388 if (VT != MVT::v2i64 && VT != MVT::v2f64)
5389 return getTargetShuffleNode(getUNPCKLOpcode(VT), dl, VT, V1, V1, DAG);
5390 if (OptForSize && X86::isUNPCKH_v_undef_Mask(SVOp))
5391 if (VT != MVT::v2i64 && VT != MVT::v2f64)
5392 return getTargetShuffleNode(getUNPCKHOpcode(VT), dl, VT, V1, V1, DAG);
5394 if (X86::isMOVDDUPMask(SVOp) && HasSSE3 && V2IsUndef &&
5395 RelaxedMayFoldVectorLoad(V1))
5396 return getMOVDDup(Op, dl, V1, DAG);
5398 if (X86::isMOVHLPS_v_undef_Mask(SVOp))
5399 return getMOVHighToLow(Op, dl, DAG);
5401 // Use to match splats
5402 if (HasSSE2 && X86::isUNPCKHMask(SVOp) && V2IsUndef &&
5403 (VT == MVT::v2f64 || VT == MVT::v2i64))
5404 return getTargetShuffleNode(getUNPCKHOpcode(VT), dl, VT, V1, V1, DAG);
5406 if (X86::isPSHUFDMask(SVOp)) {
5407 // The actual implementation will match the mask in the if above and then
5408 // during isel it can match several different instructions, not only pshufd
5409 // as its name says, sad but true, emulate the behavior for now...
5410 if (X86::isMOVDDUPMask(SVOp) && ((VT == MVT::v4f32 || VT == MVT::v2i64)))
5411 return getTargetShuffleNode(X86ISD::MOVLHPS, dl, VT, V1, V1, DAG);
5413 unsigned TargetMask = X86::getShuffleSHUFImmediate(SVOp);
5415 if (HasSSE2 && (VT == MVT::v4f32 || VT == MVT::v4i32))
5416 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1, TargetMask, DAG);
5418 if (HasSSE2 && (VT == MVT::v2i64 || VT == MVT::v2f64))
5419 return getTargetShuffleNode(X86ISD::SHUFPD, dl, VT, V1, V1,
5422 if (VT == MVT::v4f32)
5423 return getTargetShuffleNode(X86ISD::SHUFPS, dl, VT, V1, V1,
5427 // Check if this can be converted into a logical shift.
5428 bool isLeft = false;
5431 bool isShift = getSubtarget()->hasSSE2() &&
5432 isVectorShift(SVOp, DAG, isLeft, ShVal, ShAmt);
5433 if (isShift && ShVal.hasOneUse()) {
5434 // If the shifted value has multiple uses, it may be cheaper to use
5435 // v_set0 + movlhps or movhlps, etc.
5436 EVT EltVT = VT.getVectorElementType();
5437 ShAmt *= EltVT.getSizeInBits();
5438 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
5441 if (X86::isMOVLMask(SVOp)) {
5444 if (ISD::isBuildVectorAllZeros(V1.getNode()))
5445 return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl);
5446 if (!X86::isMOVLPMask(SVOp)) {
5447 if (HasSSE2 && (VT == MVT::v2i64 || VT == MVT::v2f64))
5448 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
5450 if (VT == MVT::v4i32 || VT == MVT::v4f32)
5451 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
5455 // FIXME: fold these into legal mask.
5456 if (X86::isMOVLHPSMask(SVOp) && !X86::isUNPCKLMask(SVOp))
5457 return getMOVLowToHigh(Op, dl, DAG, HasSSE2);
5459 if (X86::isMOVHLPSMask(SVOp))
5460 return getMOVHighToLow(Op, dl, DAG);
5462 if (X86::isMOVSHDUPMask(SVOp) && HasSSE3 && V2IsUndef && NumElems == 4)
5463 return getTargetShuffleNode(X86ISD::MOVSHDUP, dl, VT, V1, DAG);
5465 if (X86::isMOVSLDUPMask(SVOp) && HasSSE3 && V2IsUndef && NumElems == 4)
5466 return getTargetShuffleNode(X86ISD::MOVSLDUP, dl, VT, V1, DAG);
5468 if (X86::isMOVLPMask(SVOp))
5469 return getMOVLP(Op, dl, DAG, HasSSE2);
5471 if (ShouldXformToMOVHLPS(SVOp) ||
5472 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), SVOp))
5473 return CommuteVectorShuffle(SVOp, DAG);
5476 // No better options. Use a vshl / vsrl.
5477 EVT EltVT = VT.getVectorElementType();
5478 ShAmt *= EltVT.getSizeInBits();
5479 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
5482 bool Commuted = false;
5483 // FIXME: This should also accept a bitcast of a splat? Be careful, not
5484 // 1,1,1,1 -> v8i16 though.
5485 V1IsSplat = isSplatVector(V1.getNode());
5486 V2IsSplat = isSplatVector(V2.getNode());
5488 // Canonicalize the splat or undef, if present, to be on the RHS.
5489 if ((V1IsSplat || V1IsUndef) && !(V2IsSplat || V2IsUndef)) {
5490 Op = CommuteVectorShuffle(SVOp, DAG);
5491 SVOp = cast<ShuffleVectorSDNode>(Op);
5492 V1 = SVOp->getOperand(0);
5493 V2 = SVOp->getOperand(1);
5494 std::swap(V1IsSplat, V2IsSplat);
5495 std::swap(V1IsUndef, V2IsUndef);
5499 if (isCommutedMOVL(SVOp, V2IsSplat, V2IsUndef)) {
5500 // Shuffling low element of v1 into undef, just return v1.
5503 // If V2 is a splat, the mask may be malformed such as <4,3,3,3>, which
5504 // the instruction selector will not match, so get a canonical MOVL with
5505 // swapped operands to undo the commute.
5506 return getMOVL(DAG, dl, VT, V2, V1);
5509 if (X86::isUNPCKLMask(SVOp))
5510 return getTargetShuffleNode(getUNPCKLOpcode(VT), dl, VT, V1, V2, DAG);
5512 if (X86::isUNPCKHMask(SVOp))
5513 return getTargetShuffleNode(getUNPCKHOpcode(VT), dl, VT, V1, V2, DAG);
5516 // Normalize mask so all entries that point to V2 points to its first
5517 // element then try to match unpck{h|l} again. If match, return a
5518 // new vector_shuffle with the corrected mask.
5519 SDValue NewMask = NormalizeMask(SVOp, DAG);
5520 ShuffleVectorSDNode *NSVOp = cast<ShuffleVectorSDNode>(NewMask);
5521 if (NSVOp != SVOp) {
5522 if (X86::isUNPCKLMask(NSVOp, true)) {
5524 } else if (X86::isUNPCKHMask(NSVOp, true)) {
5531 // Commute is back and try unpck* again.
5532 // FIXME: this seems wrong.
5533 SDValue NewOp = CommuteVectorShuffle(SVOp, DAG);
5534 ShuffleVectorSDNode *NewSVOp = cast<ShuffleVectorSDNode>(NewOp);
5536 if (X86::isUNPCKLMask(NewSVOp))
5537 return getTargetShuffleNode(getUNPCKLOpcode(VT), dl, VT, V2, V1, DAG);
5539 if (X86::isUNPCKHMask(NewSVOp))
5540 return getTargetShuffleNode(getUNPCKHOpcode(VT), dl, VT, V2, V1, DAG);
5543 // Normalize the node to match x86 shuffle ops if needed
5544 if (V2.getOpcode() != ISD::UNDEF && isCommutedSHUFP(SVOp))
5545 return CommuteVectorShuffle(SVOp, DAG);
5547 // The checks below are all present in isShuffleMaskLegal, but they are
5548 // inlined here right now to enable us to directly emit target specific
5549 // nodes, and remove one by one until they don't return Op anymore.
5550 SmallVector<int, 16> M;
5553 if (isPALIGNRMask(M, VT, HasSSSE3))
5554 return getTargetShuffleNode(X86ISD::PALIGN, dl, VT, V1, V2,
5555 X86::getShufflePALIGNRImmediate(SVOp),
5558 if (ShuffleVectorSDNode::isSplatMask(&M[0], VT) &&
5559 SVOp->getSplatIndex() == 0 && V2IsUndef) {
5560 if (VT == MVT::v2f64)
5561 return getTargetShuffleNode(X86ISD::UNPCKLPD, dl, VT, V1, V1, DAG);
5562 if (VT == MVT::v2i64)
5563 return getTargetShuffleNode(X86ISD::PUNPCKLQDQ, dl, VT, V1, V1, DAG);
5566 if (isPSHUFHWMask(M, VT))
5567 return getTargetShuffleNode(X86ISD::PSHUFHW, dl, VT, V1,
5568 X86::getShufflePSHUFHWImmediate(SVOp),
5571 if (isPSHUFLWMask(M, VT))
5572 return getTargetShuffleNode(X86ISD::PSHUFLW, dl, VT, V1,
5573 X86::getShufflePSHUFLWImmediate(SVOp),
5576 if (isSHUFPMask(M, VT)) {
5577 unsigned TargetMask = X86::getShuffleSHUFImmediate(SVOp);
5578 if (VT == MVT::v4f32 || VT == MVT::v4i32)
5579 return getTargetShuffleNode(X86ISD::SHUFPS, dl, VT, V1, V2,
5581 if (VT == MVT::v2f64 || VT == MVT::v2i64)
5582 return getTargetShuffleNode(X86ISD::SHUFPD, dl, VT, V1, V2,
5586 if (X86::isUNPCKL_v_undef_Mask(SVOp))
5587 if (VT != MVT::v2i64 && VT != MVT::v2f64)
5588 return getTargetShuffleNode(getUNPCKLOpcode(VT), dl, VT, V1, V1, DAG);
5589 if (X86::isUNPCKH_v_undef_Mask(SVOp))
5590 if (VT != MVT::v2i64 && VT != MVT::v2f64)
5591 return getTargetShuffleNode(getUNPCKHOpcode(VT), dl, VT, V1, V1, DAG);
5593 // Handle v8i16 specifically since SSE can do byte extraction and insertion.
5594 if (VT == MVT::v8i16) {
5595 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(Op, DAG);
5596 if (NewOp.getNode())
5600 if (VT == MVT::v16i8) {
5601 SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(SVOp, DAG, *this);
5602 if (NewOp.getNode())
5606 // Handle all 4 wide cases with a number of shuffles.
5608 return LowerVECTOR_SHUFFLE_4wide(SVOp, DAG);
5614 X86TargetLowering::LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op,
5615 SelectionDAG &DAG) const {
5616 EVT VT = Op.getValueType();
5617 DebugLoc dl = Op.getDebugLoc();
5618 if (VT.getSizeInBits() == 8) {
5619 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
5620 Op.getOperand(0), Op.getOperand(1));
5621 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
5622 DAG.getValueType(VT));
5623 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
5624 } else if (VT.getSizeInBits() == 16) {
5625 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
5626 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
5628 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
5629 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
5630 DAG.getNode(ISD::BIT_CONVERT, dl,
5634 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
5635 Op.getOperand(0), Op.getOperand(1));
5636 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
5637 DAG.getValueType(VT));
5638 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
5639 } else if (VT == MVT::f32) {
5640 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
5641 // the result back to FR32 register. It's only worth matching if the
5642 // result has a single use which is a store or a bitcast to i32. And in
5643 // the case of a store, it's not worth it if the index is a constant 0,
5644 // because a MOVSSmr can be used instead, which is smaller and faster.
5645 if (!Op.hasOneUse())
5647 SDNode *User = *Op.getNode()->use_begin();
5648 if ((User->getOpcode() != ISD::STORE ||
5649 (isa<ConstantSDNode>(Op.getOperand(1)) &&
5650 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
5651 (User->getOpcode() != ISD::BIT_CONVERT ||
5652 User->getValueType(0) != MVT::i32))
5654 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
5655 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v4i32,
5658 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, Extract);
5659 } else if (VT == MVT::i32) {
5660 // ExtractPS works with constant index.
5661 if (isa<ConstantSDNode>(Op.getOperand(1)))
5669 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
5670 SelectionDAG &DAG) const {
5671 if (!isa<ConstantSDNode>(Op.getOperand(1)))
5674 if (Subtarget->hasSSE41()) {
5675 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG);
5680 EVT VT = Op.getValueType();
5681 DebugLoc dl = Op.getDebugLoc();
5682 // TODO: handle v16i8.
5683 if (VT.getSizeInBits() == 16) {
5684 SDValue Vec = Op.getOperand(0);
5685 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
5687 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
5688 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
5689 DAG.getNode(ISD::BIT_CONVERT, dl,
5692 // Transform it so it match pextrw which produces a 32-bit result.
5693 EVT EltVT = MVT::i32;
5694 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
5695 Op.getOperand(0), Op.getOperand(1));
5696 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
5697 DAG.getValueType(VT));
5698 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
5699 } else if (VT.getSizeInBits() == 32) {
5700 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
5704 // SHUFPS the element to the lowest double word, then movss.
5705 int Mask[4] = { Idx, -1, -1, -1 };
5706 EVT VVT = Op.getOperand(0).getValueType();
5707 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
5708 DAG.getUNDEF(VVT), Mask);
5709 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
5710 DAG.getIntPtrConstant(0));
5711 } else if (VT.getSizeInBits() == 64) {
5712 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
5713 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
5714 // to match extract_elt for f64.
5715 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
5719 // UNPCKHPD the element to the lowest double word, then movsd.
5720 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
5721 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
5722 int Mask[2] = { 1, -1 };
5723 EVT VVT = Op.getOperand(0).getValueType();
5724 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
5725 DAG.getUNDEF(VVT), Mask);
5726 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
5727 DAG.getIntPtrConstant(0));
5734 X86TargetLowering::LowerINSERT_VECTOR_ELT_SSE4(SDValue Op,
5735 SelectionDAG &DAG) const {
5736 EVT VT = Op.getValueType();
5737 EVT EltVT = VT.getVectorElementType();
5738 DebugLoc dl = Op.getDebugLoc();
5740 SDValue N0 = Op.getOperand(0);
5741 SDValue N1 = Op.getOperand(1);
5742 SDValue N2 = Op.getOperand(2);
5744 if ((EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) &&
5745 isa<ConstantSDNode>(N2)) {
5747 if (VT == MVT::v8i16)
5748 Opc = X86ISD::PINSRW;
5749 else if (VT == MVT::v16i8)
5750 Opc = X86ISD::PINSRB;
5752 Opc = X86ISD::PINSRB;
5754 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
5756 if (N1.getValueType() != MVT::i32)
5757 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
5758 if (N2.getValueType() != MVT::i32)
5759 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
5760 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
5761 } else if (EltVT == MVT::f32 && isa<ConstantSDNode>(N2)) {
5762 // Bits [7:6] of the constant are the source select. This will always be
5763 // zero here. The DAG Combiner may combine an extract_elt index into these
5764 // bits. For example (insert (extract, 3), 2) could be matched by putting
5765 // the '3' into bits [7:6] of X86ISD::INSERTPS.
5766 // Bits [5:4] of the constant are the destination select. This is the
5767 // value of the incoming immediate.
5768 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
5769 // combine either bitwise AND or insert of float 0.0 to set these bits.
5770 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue() << 4);
5771 // Create this as a scalar to vector..
5772 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
5773 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
5774 } else if (EltVT == MVT::i32 && isa<ConstantSDNode>(N2)) {
5775 // PINSR* works with constant index.
5782 X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const {
5783 EVT VT = Op.getValueType();
5784 EVT EltVT = VT.getVectorElementType();
5786 if (Subtarget->hasSSE41())
5787 return LowerINSERT_VECTOR_ELT_SSE4(Op, DAG);
5789 if (EltVT == MVT::i8)
5792 DebugLoc dl = Op.getDebugLoc();
5793 SDValue N0 = Op.getOperand(0);
5794 SDValue N1 = Op.getOperand(1);
5795 SDValue N2 = Op.getOperand(2);
5797 if (EltVT.getSizeInBits() == 16 && isa<ConstantSDNode>(N2)) {
5798 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
5799 // as its second argument.
5800 if (N1.getValueType() != MVT::i32)
5801 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
5802 if (N2.getValueType() != MVT::i32)
5803 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
5804 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);
5810 X86TargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const {
5811 DebugLoc dl = Op.getDebugLoc();
5813 if (Op.getValueType() == MVT::v1i64 &&
5814 Op.getOperand(0).getValueType() == MVT::i64)
5815 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
5817 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
5818 assert(Op.getValueType().getSimpleVT().getSizeInBits() == 128 &&
5819 "Expected an SSE type!");
5820 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(),
5821 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,AnyExt));
5824 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
5825 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
5826 // one of the above mentioned nodes. It has to be wrapped because otherwise
5827 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
5828 // be used to form addressing mode. These wrapped nodes will be selected
5831 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
5832 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
5834 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
5836 unsigned char OpFlag = 0;
5837 unsigned WrapperKind = X86ISD::Wrapper;
5838 CodeModel::Model M = getTargetMachine().getCodeModel();
5840 if (Subtarget->isPICStyleRIPRel() &&
5841 (M == CodeModel::Small || M == CodeModel::Kernel))
5842 WrapperKind = X86ISD::WrapperRIP;
5843 else if (Subtarget->isPICStyleGOT())
5844 OpFlag = X86II::MO_GOTOFF;
5845 else if (Subtarget->isPICStyleStubPIC())
5846 OpFlag = X86II::MO_PIC_BASE_OFFSET;
5848 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(),
5850 CP->getOffset(), OpFlag);
5851 DebugLoc DL = CP->getDebugLoc();
5852 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
5853 // With PIC, the address is actually $g + Offset.
5855 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
5856 DAG.getNode(X86ISD::GlobalBaseReg,
5857 DebugLoc(), getPointerTy()),
5864 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
5865 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
5867 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
5869 unsigned char OpFlag = 0;
5870 unsigned WrapperKind = X86ISD::Wrapper;
5871 CodeModel::Model M = getTargetMachine().getCodeModel();
5873 if (Subtarget->isPICStyleRIPRel() &&
5874 (M == CodeModel::Small || M == CodeModel::Kernel))
5875 WrapperKind = X86ISD::WrapperRIP;
5876 else if (Subtarget->isPICStyleGOT())
5877 OpFlag = X86II::MO_GOTOFF;
5878 else if (Subtarget->isPICStyleStubPIC())
5879 OpFlag = X86II::MO_PIC_BASE_OFFSET;
5881 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(),
5883 DebugLoc DL = JT->getDebugLoc();
5884 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
5886 // With PIC, the address is actually $g + Offset.
5888 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
5889 DAG.getNode(X86ISD::GlobalBaseReg,
5890 DebugLoc(), getPointerTy()),
5897 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const {
5898 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
5900 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
5902 unsigned char OpFlag = 0;
5903 unsigned WrapperKind = X86ISD::Wrapper;
5904 CodeModel::Model M = getTargetMachine().getCodeModel();
5906 if (Subtarget->isPICStyleRIPRel() &&
5907 (M == CodeModel::Small || M == CodeModel::Kernel))
5908 WrapperKind = X86ISD::WrapperRIP;
5909 else if (Subtarget->isPICStyleGOT())
5910 OpFlag = X86II::MO_GOTOFF;
5911 else if (Subtarget->isPICStyleStubPIC())
5912 OpFlag = X86II::MO_PIC_BASE_OFFSET;
5914 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag);
5916 DebugLoc DL = Op.getDebugLoc();
5917 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
5920 // With PIC, the address is actually $g + Offset.
5921 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
5922 !Subtarget->is64Bit()) {
5923 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
5924 DAG.getNode(X86ISD::GlobalBaseReg,
5925 DebugLoc(), getPointerTy()),
5933 X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
5934 // Create the TargetBlockAddressAddress node.
5935 unsigned char OpFlags =
5936 Subtarget->ClassifyBlockAddressReference();
5937 CodeModel::Model M = getTargetMachine().getCodeModel();
5938 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
5939 DebugLoc dl = Op.getDebugLoc();
5940 SDValue Result = DAG.getBlockAddress(BA, getPointerTy(),
5941 /*isTarget=*/true, OpFlags);
5943 if (Subtarget->isPICStyleRIPRel() &&
5944 (M == CodeModel::Small || M == CodeModel::Kernel))
5945 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
5947 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
5949 // With PIC, the address is actually $g + Offset.
5950 if (isGlobalRelativeToPICBase(OpFlags)) {
5951 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
5952 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
5960 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, DebugLoc dl,
5962 SelectionDAG &DAG) const {
5963 // Create the TargetGlobalAddress node, folding in the constant
5964 // offset if it is legal.
5965 unsigned char OpFlags =
5966 Subtarget->ClassifyGlobalReference(GV, getTargetMachine());
5967 CodeModel::Model M = getTargetMachine().getCodeModel();
5969 if (OpFlags == X86II::MO_NO_FLAG &&
5970 X86::isOffsetSuitableForCodeModel(Offset, M)) {
5971 // A direct static reference to a global.
5972 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), Offset);
5975 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags);
5978 if (Subtarget->isPICStyleRIPRel() &&
5979 (M == CodeModel::Small || M == CodeModel::Kernel))
5980 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
5982 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
5984 // With PIC, the address is actually $g + Offset.
5985 if (isGlobalRelativeToPICBase(OpFlags)) {
5986 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
5987 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
5991 // For globals that require a load from a stub to get the address, emit the
5993 if (isGlobalStubReference(OpFlags))
5994 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result,
5995 MachinePointerInfo::getGOT(), false, false, 0);
5997 // If there was a non-zero offset that we didn't fold, create an explicit
6000 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result,
6001 DAG.getConstant(Offset, getPointerTy()));
6007 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
6008 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
6009 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
6010 return LowerGlobalAddress(GV, Op.getDebugLoc(), Offset, DAG);
6014 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
6015 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg,
6016 unsigned char OperandFlags) {
6017 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
6018 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
6019 DebugLoc dl = GA->getDebugLoc();
6020 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
6021 GA->getValueType(0),
6025 SDValue Ops[] = { Chain, TGA, *InFlag };
6026 Chain = DAG.getNode(X86ISD::TLSADDR, dl, NodeTys, Ops, 3);
6028 SDValue Ops[] = { Chain, TGA };
6029 Chain = DAG.getNode(X86ISD::TLSADDR, dl, NodeTys, Ops, 2);
6032 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
6033 MFI->setAdjustsStack(true);
6035 SDValue Flag = Chain.getValue(1);
6036 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
6039 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
6041 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
6044 DebugLoc dl = GA->getDebugLoc(); // ? function entry point might be better
6045 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
6046 DAG.getNode(X86ISD::GlobalBaseReg,
6047 DebugLoc(), PtrVT), InFlag);
6048 InFlag = Chain.getValue(1);
6050 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
6053 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
6055 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
6057 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, NULL, PtrVT,
6058 X86::RAX, X86II::MO_TLSGD);
6061 // Lower ISD::GlobalTLSAddress using the "initial exec" (for no-pic) or
6062 // "local exec" model.
6063 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
6064 const EVT PtrVT, TLSModel::Model model,
6066 DebugLoc dl = GA->getDebugLoc();
6068 // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit).
6069 Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(*DAG.getContext(),
6070 is64Bit ? 257 : 256));
6072 SDValue ThreadPointer = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
6073 DAG.getIntPtrConstant(0),
6074 MachinePointerInfo(Ptr), false, false, 0);
6076 unsigned char OperandFlags = 0;
6077 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
6079 unsigned WrapperKind = X86ISD::Wrapper;
6080 if (model == TLSModel::LocalExec) {
6081 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
6082 } else if (is64Bit) {
6083 assert(model == TLSModel::InitialExec);
6084 OperandFlags = X86II::MO_GOTTPOFF;
6085 WrapperKind = X86ISD::WrapperRIP;
6087 assert(model == TLSModel::InitialExec);
6088 OperandFlags = X86II::MO_INDNTPOFF;
6091 // emit "addl x@ntpoff,%eax" (local exec) or "addl x@indntpoff,%eax" (initial
6093 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
6094 GA->getValueType(0),
6095 GA->getOffset(), OperandFlags);
6096 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
6098 if (model == TLSModel::InitialExec)
6099 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
6100 MachinePointerInfo::getGOT(), false, false, 0);
6102 // The address of the thread local variable is the add of the thread
6103 // pointer with the offset of the variable.
6104 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
6108 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
6110 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
6111 const GlobalValue *GV = GA->getGlobal();
6113 if (Subtarget->isTargetELF()) {
6114 // TODO: implement the "local dynamic" model
6115 // TODO: implement the "initial exec"model for pic executables
6117 // If GV is an alias then use the aliasee for determining
6118 // thread-localness.
6119 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV))
6120 GV = GA->resolveAliasedGlobal(false);
6122 TLSModel::Model model
6123 = getTLSModel(GV, getTargetMachine().getRelocationModel());
6126 case TLSModel::GeneralDynamic:
6127 case TLSModel::LocalDynamic: // not implemented
6128 if (Subtarget->is64Bit())
6129 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy());
6130 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy());
6132 case TLSModel::InitialExec:
6133 case TLSModel::LocalExec:
6134 return LowerToTLSExecModel(GA, DAG, getPointerTy(), model,
6135 Subtarget->is64Bit());
6137 } else if (Subtarget->isTargetDarwin()) {
6138 // Darwin only has one model of TLS. Lower to that.
6139 unsigned char OpFlag = 0;
6140 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ?
6141 X86ISD::WrapperRIP : X86ISD::Wrapper;
6143 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
6145 bool PIC32 = (getTargetMachine().getRelocationModel() == Reloc::PIC_) &&
6146 !Subtarget->is64Bit();
6148 OpFlag = X86II::MO_TLVP_PIC_BASE;
6150 OpFlag = X86II::MO_TLVP;
6151 DebugLoc DL = Op.getDebugLoc();
6152 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL,
6154 GA->getOffset(), OpFlag);
6155 SDValue Offset = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
6157 // With PIC32, the address is actually $g + Offset.
6159 Offset = DAG.getNode(ISD::ADD, DL, getPointerTy(),
6160 DAG.getNode(X86ISD::GlobalBaseReg,
6161 DebugLoc(), getPointerTy()),
6164 // Lowering the machine isd will make sure everything is in the right
6166 SDValue Args[] = { Offset };
6167 SDValue Chain = DAG.getNode(X86ISD::TLSCALL, DL, MVT::Other, Args, 1);
6169 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls.
6170 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
6171 MFI->setAdjustsStack(true);
6173 // And our return value (tls address) is in the standard call return value
6175 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
6176 return DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy());
6180 "TLS not implemented for this target.");
6182 llvm_unreachable("Unreachable");
6187 /// LowerShift - Lower SRA_PARTS and friends, which return two i32 values and
6188 /// take a 2 x i32 value to shift plus a shift amount.
6189 SDValue X86TargetLowering::LowerShift(SDValue Op, SelectionDAG &DAG) const {
6190 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
6191 EVT VT = Op.getValueType();
6192 unsigned VTBits = VT.getSizeInBits();
6193 DebugLoc dl = Op.getDebugLoc();
6194 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
6195 SDValue ShOpLo = Op.getOperand(0);
6196 SDValue ShOpHi = Op.getOperand(1);
6197 SDValue ShAmt = Op.getOperand(2);
6198 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
6199 DAG.getConstant(VTBits - 1, MVT::i8))
6200 : DAG.getConstant(0, VT);
6203 if (Op.getOpcode() == ISD::SHL_PARTS) {
6204 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
6205 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
6207 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
6208 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, ShAmt);
6211 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
6212 DAG.getConstant(VTBits, MVT::i8));
6213 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
6214 AndNode, DAG.getConstant(0, MVT::i8));
6217 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8);
6218 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
6219 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
6221 if (Op.getOpcode() == ISD::SHL_PARTS) {
6222 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
6223 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
6225 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
6226 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
6229 SDValue Ops[2] = { Lo, Hi };
6230 return DAG.getMergeValues(Ops, 2, dl);
6233 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op,
6234 SelectionDAG &DAG) const {
6235 EVT SrcVT = Op.getOperand(0).getValueType();
6237 if (SrcVT.isVector())
6240 assert(SrcVT.getSimpleVT() <= MVT::i64 && SrcVT.getSimpleVT() >= MVT::i16 &&
6241 "Unknown SINT_TO_FP to lower!");
6243 // These are really Legal; return the operand so the caller accepts it as
6245 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
6247 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
6248 Subtarget->is64Bit()) {
6252 DebugLoc dl = Op.getDebugLoc();
6253 unsigned Size = SrcVT.getSizeInBits()/8;
6254 MachineFunction &MF = DAG.getMachineFunction();
6255 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false);
6256 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
6257 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
6259 MachinePointerInfo::getFixedStack(SSFI),
6261 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
6264 SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
6266 SelectionDAG &DAG) const {
6268 DebugLoc DL = Op.getDebugLoc();
6270 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
6272 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Flag);
6274 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
6276 unsigned ByteSize = SrcVT.getSizeInBits()/8;
6278 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex();
6279 MachineMemOperand *MMO =
6280 DAG.getMachineFunction()
6281 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
6282 MachineMemOperand::MOLoad, ByteSize, ByteSize);
6284 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) };
6285 SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG :
6287 Tys, Ops, array_lengthof(Ops),
6291 Chain = Result.getValue(1);
6292 SDValue InFlag = Result.getValue(2);
6294 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
6295 // shouldn't be necessary except that RFP cannot be live across
6296 // multiple blocks. When stackifier is fixed, they can be uncoupled.
6297 MachineFunction &MF = DAG.getMachineFunction();
6298 unsigned SSFISize = Op.getValueType().getSizeInBits()/8;
6299 int SSFI = MF.getFrameInfo()->CreateStackObject(SSFISize, SSFISize, false);
6300 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
6301 Tys = DAG.getVTList(MVT::Other);
6303 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag
6305 MachineMemOperand *MMO =
6306 DAG.getMachineFunction()
6307 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
6308 MachineMemOperand::MOStore, SSFISize, SSFISize);
6310 Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys,
6311 Ops, array_lengthof(Ops),
6312 Op.getValueType(), MMO);
6313 Result = DAG.getLoad(Op.getValueType(), DL, Chain, StackSlot,
6314 MachinePointerInfo::getFixedStack(SSFI),
6321 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
6322 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op,
6323 SelectionDAG &DAG) const {
6324 // This algorithm is not obvious. Here it is in C code, more or less:
6326 double uint64_to_double( uint32_t hi, uint32_t lo ) {
6327 static const __m128i exp = { 0x4330000045300000ULL, 0 };
6328 static const __m128d bias = { 0x1.0p84, 0x1.0p52 };
6330 // Copy ints to xmm registers.
6331 __m128i xh = _mm_cvtsi32_si128( hi );
6332 __m128i xl = _mm_cvtsi32_si128( lo );
6334 // Combine into low half of a single xmm register.
6335 __m128i x = _mm_unpacklo_epi32( xh, xl );
6339 // Merge in appropriate exponents to give the integer bits the right
6341 x = _mm_unpacklo_epi32( x, exp );
6343 // Subtract away the biases to deal with the IEEE-754 double precision
6345 d = _mm_sub_pd( (__m128d) x, bias );
6347 // All conversions up to here are exact. The correctly rounded result is
6348 // calculated using the current rounding mode using the following
6350 d = _mm_add_sd( d, _mm_unpackhi_pd( d, d ) );
6351 _mm_store_sd( &sd, d ); // Because we are returning doubles in XMM, this
6352 // store doesn't really need to be here (except
6353 // maybe to zero the other double)
6358 DebugLoc dl = Op.getDebugLoc();
6359 LLVMContext *Context = DAG.getContext();
6361 // Build some magic constants.
6362 std::vector<Constant*> CV0;
6363 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0x45300000)));
6364 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0x43300000)));
6365 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0)));
6366 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0)));
6367 Constant *C0 = ConstantVector::get(CV0);
6368 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16);
6370 std::vector<Constant*> CV1;
6372 ConstantFP::get(*Context, APFloat(APInt(64, 0x4530000000000000ULL))));
6374 ConstantFP::get(*Context, APFloat(APInt(64, 0x4330000000000000ULL))));
6375 Constant *C1 = ConstantVector::get(CV1);
6376 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16);
6378 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
6379 DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
6381 DAG.getIntPtrConstant(1)));
6382 SDValue XR2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
6383 DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
6385 DAG.getIntPtrConstant(0)));
6386 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32, XR1, XR2);
6387 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
6388 MachinePointerInfo::getConstantPool(),
6390 SDValue Unpck2 = getUnpackl(DAG, dl, MVT::v4i32, Unpck1, CLod0);
6391 SDValue XR2F = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f64, Unpck2);
6392 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
6393 MachinePointerInfo::getConstantPool(),
6395 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
6397 // Add the halves; easiest way is to swap them into another reg first.
6398 int ShufMask[2] = { 1, -1 };
6399 SDValue Shuf = DAG.getVectorShuffle(MVT::v2f64, dl, Sub,
6400 DAG.getUNDEF(MVT::v2f64), ShufMask);
6401 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::v2f64, Shuf, Sub);
6402 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Add,
6403 DAG.getIntPtrConstant(0));
6406 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
6407 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op,
6408 SelectionDAG &DAG) const {
6409 DebugLoc dl = Op.getDebugLoc();
6410 // FP constant to bias correct the final result.
6411 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
6414 // Load the 32-bit value into an XMM register.
6415 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
6416 DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
6418 DAG.getIntPtrConstant(0)));
6420 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
6421 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f64, Load),
6422 DAG.getIntPtrConstant(0));
6424 // Or the load with the bias.
6425 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64,
6426 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64,
6427 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
6429 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64,
6430 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
6431 MVT::v2f64, Bias)));
6432 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
6433 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f64, Or),
6434 DAG.getIntPtrConstant(0));
6436 // Subtract the bias.
6437 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
6439 // Handle final rounding.
6440 EVT DestVT = Op.getValueType();
6442 if (DestVT.bitsLT(MVT::f64)) {
6443 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
6444 DAG.getIntPtrConstant(0));
6445 } else if (DestVT.bitsGT(MVT::f64)) {
6446 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
6449 // Handle final rounding.
6453 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op,
6454 SelectionDAG &DAG) const {
6455 SDValue N0 = Op.getOperand(0);
6456 DebugLoc dl = Op.getDebugLoc();
6458 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't
6459 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
6460 // the optimization here.
6461 if (DAG.SignBitIsZero(N0))
6462 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
6464 EVT SrcVT = N0.getValueType();
6465 EVT DstVT = Op.getValueType();
6466 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64)
6467 return LowerUINT_TO_FP_i64(Op, DAG);
6468 else if (SrcVT == MVT::i32 && X86ScalarSSEf64)
6469 return LowerUINT_TO_FP_i32(Op, DAG);
6471 // Make a 64-bit buffer, and use it to build an FILD.
6472 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
6473 if (SrcVT == MVT::i32) {
6474 SDValue WordOff = DAG.getConstant(4, getPointerTy());
6475 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl,
6476 getPointerTy(), StackSlot, WordOff);
6477 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
6478 StackSlot, MachinePointerInfo(),
6480 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32),
6481 OffsetSlot, MachinePointerInfo(),
6483 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
6487 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP");
6488 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
6489 StackSlot, MachinePointerInfo(),
6491 // For i64 source, we need to add the appropriate power of 2 if the input
6492 // was negative. This is the same as the optimization in
6493 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here,
6494 // we must be careful to do the computation in x87 extended precision, not
6495 // in SSE. (The generic code can't know it's OK to do this, or how to.)
6496 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex();
6497 MachineMemOperand *MMO =
6498 DAG.getMachineFunction()
6499 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
6500 MachineMemOperand::MOLoad, 8, 8);
6502 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other);
6503 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) };
6504 SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops, 3,
6507 APInt FF(32, 0x5F800000ULL);
6509 // Check whether the sign bit is set.
6510 SDValue SignSet = DAG.getSetCC(dl, getSetCCResultType(MVT::i64),
6511 Op.getOperand(0), DAG.getConstant(0, MVT::i64),
6514 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
6515 SDValue FudgePtr = DAG.getConstantPool(
6516 ConstantInt::get(*DAG.getContext(), FF.zext(64)),
6519 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
6520 SDValue Zero = DAG.getIntPtrConstant(0);
6521 SDValue Four = DAG.getIntPtrConstant(4);
6522 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
6524 FudgePtr = DAG.getNode(ISD::ADD, dl, getPointerTy(), FudgePtr, Offset);
6526 // Load the value out, extending it from f32 to f80.
6527 // FIXME: Avoid the extend by constructing the right constant pool?
6528 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, MVT::f80, dl, DAG.getEntryNode(),
6529 FudgePtr, MachinePointerInfo::getConstantPool(),
6530 MVT::f32, false, false, 4);
6531 // Extend everything to 80 bits to force it to be done on x87.
6532 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge);
6533 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add, DAG.getIntPtrConstant(0));
6536 std::pair<SDValue,SDValue> X86TargetLowering::
6537 FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG, bool IsSigned) const {
6538 DebugLoc DL = Op.getDebugLoc();
6540 EVT DstTy = Op.getValueType();
6543 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
6547 assert(DstTy.getSimpleVT() <= MVT::i64 &&
6548 DstTy.getSimpleVT() >= MVT::i16 &&
6549 "Unknown FP_TO_SINT to lower!");
6551 // These are really Legal.
6552 if (DstTy == MVT::i32 &&
6553 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
6554 return std::make_pair(SDValue(), SDValue());
6555 if (Subtarget->is64Bit() &&
6556 DstTy == MVT::i64 &&
6557 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
6558 return std::make_pair(SDValue(), SDValue());
6560 // We lower FP->sint64 into FISTP64, followed by a load, all to a temporary
6562 MachineFunction &MF = DAG.getMachineFunction();
6563 unsigned MemSize = DstTy.getSizeInBits()/8;
6564 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
6565 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
6570 switch (DstTy.getSimpleVT().SimpleTy) {
6571 default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
6572 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
6573 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
6574 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
6577 SDValue Chain = DAG.getEntryNode();
6578 SDValue Value = Op.getOperand(0);
6579 EVT TheVT = Op.getOperand(0).getValueType();
6580 if (isScalarFPTypeInSSEReg(TheVT)) {
6581 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
6582 Chain = DAG.getStore(Chain, DL, Value, StackSlot,
6583 MachinePointerInfo::getFixedStack(SSFI),
6585 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
6587 Chain, StackSlot, DAG.getValueType(TheVT)
6590 MachineMemOperand *MMO =
6591 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
6592 MachineMemOperand::MOLoad, MemSize, MemSize);
6593 Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops, 3,
6595 Chain = Value.getValue(1);
6596 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
6597 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
6600 MachineMemOperand *MMO =
6601 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
6602 MachineMemOperand::MOStore, MemSize, MemSize);
6604 // Build the FP_TO_INT*_IN_MEM
6605 SDValue Ops[] = { Chain, Value, StackSlot };
6606 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
6607 Ops, 3, DstTy, MMO);
6609 return std::make_pair(FIST, StackSlot);
6612 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op,
6613 SelectionDAG &DAG) const {
6614 if (Op.getValueType().isVector())
6617 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG, true);
6618 SDValue FIST = Vals.first, StackSlot = Vals.second;
6619 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
6620 if (FIST.getNode() == 0) return Op;
6623 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(),
6624 FIST, StackSlot, MachinePointerInfo(), false, false, 0);
6627 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op,
6628 SelectionDAG &DAG) const {
6629 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG, false);
6630 SDValue FIST = Vals.first, StackSlot = Vals.second;
6631 assert(FIST.getNode() && "Unexpected failure");
6634 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(),
6635 FIST, StackSlot, MachinePointerInfo(), false, false, 0);
6638 SDValue X86TargetLowering::LowerFABS(SDValue Op,
6639 SelectionDAG &DAG) const {
6640 LLVMContext *Context = DAG.getContext();
6641 DebugLoc dl = Op.getDebugLoc();
6642 EVT VT = Op.getValueType();
6645 EltVT = VT.getVectorElementType();
6646 std::vector<Constant*> CV;
6647 if (EltVT == MVT::f64) {
6648 Constant *C = ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63))));
6652 Constant *C = ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31))));
6658 Constant *C = ConstantVector::get(CV);
6659 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
6660 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
6661 MachinePointerInfo::getConstantPool(),
6663 return DAG.getNode(X86ISD::FAND, dl, VT, Op.getOperand(0), Mask);
6666 SDValue X86TargetLowering::LowerFNEG(SDValue Op, SelectionDAG &DAG) const {
6667 LLVMContext *Context = DAG.getContext();
6668 DebugLoc dl = Op.getDebugLoc();
6669 EVT VT = Op.getValueType();
6672 EltVT = VT.getVectorElementType();
6673 std::vector<Constant*> CV;
6674 if (EltVT == MVT::f64) {
6675 Constant *C = ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63)));
6679 Constant *C = ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31)));
6685 Constant *C = ConstantVector::get(CV);
6686 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
6687 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
6688 MachinePointerInfo::getConstantPool(),
6690 if (VT.isVector()) {
6691 return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
6692 DAG.getNode(ISD::XOR, dl, MVT::v2i64,
6693 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64,
6695 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64, Mask)));
6697 return DAG.getNode(X86ISD::FXOR, dl, VT, Op.getOperand(0), Mask);
6701 SDValue X86TargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {
6702 LLVMContext *Context = DAG.getContext();
6703 SDValue Op0 = Op.getOperand(0);
6704 SDValue Op1 = Op.getOperand(1);
6705 DebugLoc dl = Op.getDebugLoc();
6706 EVT VT = Op.getValueType();
6707 EVT SrcVT = Op1.getValueType();
6709 // If second operand is smaller, extend it first.
6710 if (SrcVT.bitsLT(VT)) {
6711 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
6714 // And if it is bigger, shrink it first.
6715 if (SrcVT.bitsGT(VT)) {
6716 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1));
6720 // At this point the operands and the result should have the same
6721 // type, and that won't be f80 since that is not custom lowered.
6723 // First get the sign bit of second operand.
6724 std::vector<Constant*> CV;
6725 if (SrcVT == MVT::f64) {
6726 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63))));
6727 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0))));
6729 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31))));
6730 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
6731 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
6732 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
6734 Constant *C = ConstantVector::get(CV);
6735 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
6736 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx,
6737 MachinePointerInfo::getConstantPool(),
6739 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1);
6741 // Shift sign bit right or left if the two operands have different types.
6742 if (SrcVT.bitsGT(VT)) {
6743 // Op0 is MVT::f32, Op1 is MVT::f64.
6744 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, SignBit);
6745 SignBit = DAG.getNode(X86ISD::FSRL, dl, MVT::v2f64, SignBit,
6746 DAG.getConstant(32, MVT::i32));
6747 SignBit = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v4f32, SignBit);
6748 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, SignBit,
6749 DAG.getIntPtrConstant(0));
6752 // Clear first operand sign bit.
6754 if (VT == MVT::f64) {
6755 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63)))));
6756 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0))));
6758 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31)))));
6759 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
6760 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
6761 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
6763 C = ConstantVector::get(CV);
6764 CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
6765 SDValue Mask2 = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
6766 MachinePointerInfo::getConstantPool(),
6768 SDValue Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Mask2);
6770 // Or the value with the sign bit.
6771 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit);
6774 /// Emit nodes that will be selected as "test Op0,Op0", or something
6776 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC,
6777 SelectionDAG &DAG) const {
6778 DebugLoc dl = Op.getDebugLoc();
6780 // CF and OF aren't always set the way we want. Determine which
6781 // of these we need.
6782 bool NeedCF = false;
6783 bool NeedOF = false;
6786 case X86::COND_A: case X86::COND_AE:
6787 case X86::COND_B: case X86::COND_BE:
6790 case X86::COND_G: case X86::COND_GE:
6791 case X86::COND_L: case X86::COND_LE:
6792 case X86::COND_O: case X86::COND_NO:
6797 // See if we can use the EFLAGS value from the operand instead of
6798 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
6799 // we prove that the arithmetic won't overflow, we can't use OF or CF.
6800 if (Op.getResNo() != 0 || NeedOF || NeedCF)
6801 // Emit a CMP with 0, which is the TEST pattern.
6802 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
6803 DAG.getConstant(0, Op.getValueType()));
6805 unsigned Opcode = 0;
6806 unsigned NumOperands = 0;
6807 switch (Op.getNode()->getOpcode()) {
6809 // Due to an isel shortcoming, be conservative if this add is likely to be
6810 // selected as part of a load-modify-store instruction. When the root node
6811 // in a match is a store, isel doesn't know how to remap non-chain non-flag
6812 // uses of other nodes in the match, such as the ADD in this case. This
6813 // leads to the ADD being left around and reselected, with the result being
6814 // two adds in the output. Alas, even if none our users are stores, that
6815 // doesn't prove we're O.K. Ergo, if we have any parents that aren't
6816 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require
6817 // climbing the DAG back to the root, and it doesn't seem to be worth the
6819 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
6820 UE = Op.getNode()->use_end(); UI != UE; ++UI)
6821 if (UI->getOpcode() != ISD::CopyToReg && UI->getOpcode() != ISD::SETCC)
6824 if (ConstantSDNode *C =
6825 dyn_cast<ConstantSDNode>(Op.getNode()->getOperand(1))) {
6826 // An add of one will be selected as an INC.
6827 if (C->getAPIntValue() == 1) {
6828 Opcode = X86ISD::INC;
6833 // An add of negative one (subtract of one) will be selected as a DEC.
6834 if (C->getAPIntValue().isAllOnesValue()) {
6835 Opcode = X86ISD::DEC;
6841 // Otherwise use a regular EFLAGS-setting add.
6842 Opcode = X86ISD::ADD;
6846 // If the primary and result isn't used, don't bother using X86ISD::AND,
6847 // because a TEST instruction will be better.
6848 bool NonFlagUse = false;
6849 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
6850 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
6852 unsigned UOpNo = UI.getOperandNo();
6853 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
6854 // Look pass truncate.
6855 UOpNo = User->use_begin().getOperandNo();
6856 User = *User->use_begin();
6859 if (User->getOpcode() != ISD::BRCOND &&
6860 User->getOpcode() != ISD::SETCC &&
6861 (User->getOpcode() != ISD::SELECT || UOpNo != 0)) {
6874 // Due to the ISEL shortcoming noted above, be conservative if this op is
6875 // likely to be selected as part of a load-modify-store instruction.
6876 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
6877 UE = Op.getNode()->use_end(); UI != UE; ++UI)
6878 if (UI->getOpcode() == ISD::STORE)
6881 // Otherwise use a regular EFLAGS-setting instruction.
6882 switch (Op.getNode()->getOpcode()) {
6883 default: llvm_unreachable("unexpected operator!");
6884 case ISD::SUB: Opcode = X86ISD::SUB; break;
6885 case ISD::OR: Opcode = X86ISD::OR; break;
6886 case ISD::XOR: Opcode = X86ISD::XOR; break;
6887 case ISD::AND: Opcode = X86ISD::AND; break;
6899 return SDValue(Op.getNode(), 1);
6906 // Emit a CMP with 0, which is the TEST pattern.
6907 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
6908 DAG.getConstant(0, Op.getValueType()));
6910 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
6911 SmallVector<SDValue, 4> Ops;
6912 for (unsigned i = 0; i != NumOperands; ++i)
6913 Ops.push_back(Op.getOperand(i));
6915 SDValue New = DAG.getNode(Opcode, dl, VTs, &Ops[0], NumOperands);
6916 DAG.ReplaceAllUsesWith(Op, New);
6917 return SDValue(New.getNode(), 1);
6920 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
6922 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
6923 SelectionDAG &DAG) const {
6924 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1))
6925 if (C->getAPIntValue() == 0)
6926 return EmitTest(Op0, X86CC, DAG);
6928 DebugLoc dl = Op0.getDebugLoc();
6929 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
6932 /// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node
6933 /// if it's possible.
6934 SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC,
6935 DebugLoc dl, SelectionDAG &DAG) const {
6936 SDValue Op0 = And.getOperand(0);
6937 SDValue Op1 = And.getOperand(1);
6938 if (Op0.getOpcode() == ISD::TRUNCATE)
6939 Op0 = Op0.getOperand(0);
6940 if (Op1.getOpcode() == ISD::TRUNCATE)
6941 Op1 = Op1.getOperand(0);
6944 if (Op1.getOpcode() == ISD::SHL)
6945 std::swap(Op0, Op1);
6946 if (Op0.getOpcode() == ISD::SHL) {
6947 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0)))
6948 if (And00C->getZExtValue() == 1) {
6949 // If we looked past a truncate, check that it's only truncating away
6951 unsigned BitWidth = Op0.getValueSizeInBits();
6952 unsigned AndBitWidth = And.getValueSizeInBits();
6953 if (BitWidth > AndBitWidth) {
6954 APInt Mask = APInt::getAllOnesValue(BitWidth), Zeros, Ones;
6955 DAG.ComputeMaskedBits(Op0, Mask, Zeros, Ones);
6956 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth)
6960 RHS = Op0.getOperand(1);
6962 } else if (Op1.getOpcode() == ISD::Constant) {
6963 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1);
6964 SDValue AndLHS = Op0;
6965 if (AndRHS->getZExtValue() == 1 && AndLHS.getOpcode() == ISD::SRL) {
6966 LHS = AndLHS.getOperand(0);
6967 RHS = AndLHS.getOperand(1);
6971 if (LHS.getNode()) {
6972 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT
6973 // instruction. Since the shift amount is in-range-or-undefined, we know
6974 // that doing a bittest on the i32 value is ok. We extend to i32 because
6975 // the encoding for the i16 version is larger than the i32 version.
6976 // Also promote i16 to i32 for performance / code size reason.
6977 if (LHS.getValueType() == MVT::i8 ||
6978 LHS.getValueType() == MVT::i16)
6979 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
6981 // If the operand types disagree, extend the shift amount to match. Since
6982 // BT ignores high bits (like shifts) we can use anyextend.
6983 if (LHS.getValueType() != RHS.getValueType())
6984 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
6986 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
6987 unsigned Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
6988 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
6989 DAG.getConstant(Cond, MVT::i8), BT);
6995 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
6996 assert(Op.getValueType() == MVT::i8 && "SetCC type must be 8-bit integer");
6997 SDValue Op0 = Op.getOperand(0);
6998 SDValue Op1 = Op.getOperand(1);
6999 DebugLoc dl = Op.getDebugLoc();
7000 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
7002 // Optimize to BT if possible.
7003 // Lower (X & (1 << N)) == 0 to BT(X, N).
7004 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
7005 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
7006 if (Op0.getOpcode() == ISD::AND &&
7008 Op1.getOpcode() == ISD::Constant &&
7009 cast<ConstantSDNode>(Op1)->isNullValue() &&
7010 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
7011 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG);
7012 if (NewSetCC.getNode())
7016 // Look for "(setcc) == / != 1" to avoid unncessary setcc.
7017 if (Op0.getOpcode() == X86ISD::SETCC &&
7018 Op1.getOpcode() == ISD::Constant &&
7019 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 ||
7020 cast<ConstantSDNode>(Op1)->isNullValue()) &&
7021 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
7022 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0);
7023 bool Invert = (CC == ISD::SETNE) ^
7024 cast<ConstantSDNode>(Op1)->isNullValue();
7026 CCode = X86::GetOppositeBranchCondition(CCode);
7027 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
7028 DAG.getConstant(CCode, MVT::i8), Op0.getOperand(1));
7031 bool isFP = Op1.getValueType().isFloatingPoint();
7032 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG);
7033 if (X86CC == X86::COND_INVALID)
7036 SDValue Cond = EmitCmp(Op0, Op1, X86CC, DAG);
7038 // Use sbb x, x to materialize carry bit into a GPR.
7039 if (X86CC == X86::COND_B)
7040 return DAG.getNode(ISD::AND, dl, MVT::i8,
7041 DAG.getNode(X86ISD::SETCC_CARRY, dl, MVT::i8,
7042 DAG.getConstant(X86CC, MVT::i8), Cond),
7043 DAG.getConstant(1, MVT::i8));
7045 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
7046 DAG.getConstant(X86CC, MVT::i8), Cond);
7049 SDValue X86TargetLowering::LowerVSETCC(SDValue Op, SelectionDAG &DAG) const {
7051 SDValue Op0 = Op.getOperand(0);
7052 SDValue Op1 = Op.getOperand(1);
7053 SDValue CC = Op.getOperand(2);
7054 EVT VT = Op.getValueType();
7055 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
7056 bool isFP = Op.getOperand(1).getValueType().isFloatingPoint();
7057 DebugLoc dl = Op.getDebugLoc();
7061 EVT VT0 = Op0.getValueType();
7062 assert(VT0 == MVT::v4f32 || VT0 == MVT::v2f64);
7063 unsigned Opc = VT0 == MVT::v4f32 ? X86ISD::CMPPS : X86ISD::CMPPD;
7066 switch (SetCCOpcode) {
7069 case ISD::SETEQ: SSECC = 0; break;
7071 case ISD::SETGT: Swap = true; // Fallthrough
7073 case ISD::SETOLT: SSECC = 1; break;
7075 case ISD::SETGE: Swap = true; // Fallthrough
7077 case ISD::SETOLE: SSECC = 2; break;
7078 case ISD::SETUO: SSECC = 3; break;
7080 case ISD::SETNE: SSECC = 4; break;
7081 case ISD::SETULE: Swap = true;
7082 case ISD::SETUGE: SSECC = 5; break;
7083 case ISD::SETULT: Swap = true;
7084 case ISD::SETUGT: SSECC = 6; break;
7085 case ISD::SETO: SSECC = 7; break;
7088 std::swap(Op0, Op1);
7090 // In the two special cases we can't handle, emit two comparisons.
7092 if (SetCCOpcode == ISD::SETUEQ) {
7094 UNORD = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(3, MVT::i8));
7095 EQ = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(0, MVT::i8));
7096 return DAG.getNode(ISD::OR, dl, VT, UNORD, EQ);
7098 else if (SetCCOpcode == ISD::SETONE) {
7100 ORD = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(7, MVT::i8));
7101 NEQ = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(4, MVT::i8));
7102 return DAG.getNode(ISD::AND, dl, VT, ORD, NEQ);
7104 llvm_unreachable("Illegal FP comparison");
7106 // Handle all other FP comparisons here.
7107 return DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(SSECC, MVT::i8));
7110 // We are handling one of the integer comparisons here. Since SSE only has
7111 // GT and EQ comparisons for integer, swapping operands and multiple
7112 // operations may be required for some comparisons.
7113 unsigned Opc = 0, EQOpc = 0, GTOpc = 0;
7114 bool Swap = false, Invert = false, FlipSigns = false;
7116 switch (VT.getSimpleVT().SimpleTy) {
7118 case MVT::v16i8: EQOpc = X86ISD::PCMPEQB; GTOpc = X86ISD::PCMPGTB; break;
7119 case MVT::v8i16: EQOpc = X86ISD::PCMPEQW; GTOpc = X86ISD::PCMPGTW; break;
7120 case MVT::v4i32: EQOpc = X86ISD::PCMPEQD; GTOpc = X86ISD::PCMPGTD; break;
7121 case MVT::v2i64: EQOpc = X86ISD::PCMPEQQ; GTOpc = X86ISD::PCMPGTQ; break;
7124 switch (SetCCOpcode) {
7126 case ISD::SETNE: Invert = true;
7127 case ISD::SETEQ: Opc = EQOpc; break;
7128 case ISD::SETLT: Swap = true;
7129 case ISD::SETGT: Opc = GTOpc; break;
7130 case ISD::SETGE: Swap = true;
7131 case ISD::SETLE: Opc = GTOpc; Invert = true; break;
7132 case ISD::SETULT: Swap = true;
7133 case ISD::SETUGT: Opc = GTOpc; FlipSigns = true; break;
7134 case ISD::SETUGE: Swap = true;
7135 case ISD::SETULE: Opc = GTOpc; FlipSigns = true; Invert = true; break;
7138 std::swap(Op0, Op1);
7140 // Since SSE has no unsigned integer comparisons, we need to flip the sign
7141 // bits of the inputs before performing those operations.
7143 EVT EltVT = VT.getVectorElementType();
7144 SDValue SignBit = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()),
7146 std::vector<SDValue> SignBits(VT.getVectorNumElements(), SignBit);
7147 SDValue SignVec = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &SignBits[0],
7149 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SignVec);
7150 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SignVec);
7153 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
7155 // If the logical-not of the result is required, perform that now.
7157 Result = DAG.getNOT(dl, Result, VT);
7162 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
7163 static bool isX86LogicalCmp(SDValue Op) {
7164 unsigned Opc = Op.getNode()->getOpcode();
7165 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI)
7167 if (Op.getResNo() == 1 &&
7168 (Opc == X86ISD::ADD ||
7169 Opc == X86ISD::SUB ||
7170 Opc == X86ISD::SMUL ||
7171 Opc == X86ISD::UMUL ||
7172 Opc == X86ISD::INC ||
7173 Opc == X86ISD::DEC ||
7174 Opc == X86ISD::OR ||
7175 Opc == X86ISD::XOR ||
7176 Opc == X86ISD::AND))
7182 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
7183 bool addTest = true;
7184 SDValue Cond = Op.getOperand(0);
7185 DebugLoc dl = Op.getDebugLoc();
7188 if (Cond.getOpcode() == ISD::SETCC) {
7189 SDValue NewCond = LowerSETCC(Cond, DAG);
7190 if (NewCond.getNode())
7194 // (select (x == 0), -1, 0) -> (sign_bit (x - 1))
7195 SDValue Op1 = Op.getOperand(1);
7196 SDValue Op2 = Op.getOperand(2);
7197 if (Cond.getOpcode() == X86ISD::SETCC &&
7198 cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue() == X86::COND_E) {
7199 SDValue Cmp = Cond.getOperand(1);
7200 if (Cmp.getOpcode() == X86ISD::CMP) {
7201 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op1);
7202 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2);
7203 ConstantSDNode *RHSC =
7204 dyn_cast<ConstantSDNode>(Cmp.getOperand(1).getNode());
7205 if (N1C && N1C->isAllOnesValue() &&
7206 N2C && N2C->isNullValue() &&
7207 RHSC && RHSC->isNullValue()) {
7208 SDValue CmpOp0 = Cmp.getOperand(0);
7209 Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
7210 CmpOp0, DAG.getConstant(1, CmpOp0.getValueType()));
7211 return DAG.getNode(X86ISD::SETCC_CARRY, dl, Op.getValueType(),
7212 DAG.getConstant(X86::COND_B, MVT::i8), Cmp);
7217 // Look pass (and (setcc_carry (cmp ...)), 1).
7218 if (Cond.getOpcode() == ISD::AND &&
7219 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
7220 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
7221 if (C && C->getAPIntValue() == 1)
7222 Cond = Cond.getOperand(0);
7225 // If condition flag is set by a X86ISD::CMP, then use it as the condition
7226 // setting operand in place of the X86ISD::SETCC.
7227 if (Cond.getOpcode() == X86ISD::SETCC ||
7228 Cond.getOpcode() == X86ISD::SETCC_CARRY) {
7229 CC = Cond.getOperand(0);
7231 SDValue Cmp = Cond.getOperand(1);
7232 unsigned Opc = Cmp.getOpcode();
7233 EVT VT = Op.getValueType();
7235 bool IllegalFPCMov = false;
7236 if (VT.isFloatingPoint() && !VT.isVector() &&
7237 !isScalarFPTypeInSSEReg(VT)) // FPStack?
7238 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
7240 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
7241 Opc == X86ISD::BT) { // FIXME
7248 // Look pass the truncate.
7249 if (Cond.getOpcode() == ISD::TRUNCATE)
7250 Cond = Cond.getOperand(0);
7252 // We know the result of AND is compared against zero. Try to match
7254 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
7255 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
7256 if (NewSetCC.getNode()) {
7257 CC = NewSetCC.getOperand(0);
7258 Cond = NewSetCC.getOperand(1);
7265 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
7266 Cond = EmitTest(Cond, X86::COND_NE, DAG);
7269 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
7270 // condition is true.
7271 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Flag);
7272 SDValue Ops[] = { Op2, Op1, CC, Cond };
7273 return DAG.getNode(X86ISD::CMOV, dl, VTs, Ops, array_lengthof(Ops));
7276 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
7277 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
7278 // from the AND / OR.
7279 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
7280 Opc = Op.getOpcode();
7281 if (Opc != ISD::OR && Opc != ISD::AND)
7283 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
7284 Op.getOperand(0).hasOneUse() &&
7285 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
7286 Op.getOperand(1).hasOneUse());
7289 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
7290 // 1 and that the SETCC node has a single use.
7291 static bool isXor1OfSetCC(SDValue Op) {
7292 if (Op.getOpcode() != ISD::XOR)
7294 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
7295 if (N1C && N1C->getAPIntValue() == 1) {
7296 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
7297 Op.getOperand(0).hasOneUse();
7302 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
7303 bool addTest = true;
7304 SDValue Chain = Op.getOperand(0);
7305 SDValue Cond = Op.getOperand(1);
7306 SDValue Dest = Op.getOperand(2);
7307 DebugLoc dl = Op.getDebugLoc();
7310 if (Cond.getOpcode() == ISD::SETCC) {
7311 SDValue NewCond = LowerSETCC(Cond, DAG);
7312 if (NewCond.getNode())
7316 // FIXME: LowerXALUO doesn't handle these!!
7317 else if (Cond.getOpcode() == X86ISD::ADD ||
7318 Cond.getOpcode() == X86ISD::SUB ||
7319 Cond.getOpcode() == X86ISD::SMUL ||
7320 Cond.getOpcode() == X86ISD::UMUL)
7321 Cond = LowerXALUO(Cond, DAG);
7324 // Look pass (and (setcc_carry (cmp ...)), 1).
7325 if (Cond.getOpcode() == ISD::AND &&
7326 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
7327 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
7328 if (C && C->getAPIntValue() == 1)
7329 Cond = Cond.getOperand(0);
7332 // If condition flag is set by a X86ISD::CMP, then use it as the condition
7333 // setting operand in place of the X86ISD::SETCC.
7334 if (Cond.getOpcode() == X86ISD::SETCC ||
7335 Cond.getOpcode() == X86ISD::SETCC_CARRY) {
7336 CC = Cond.getOperand(0);
7338 SDValue Cmp = Cond.getOperand(1);
7339 unsigned Opc = Cmp.getOpcode();
7340 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
7341 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
7345 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
7349 // These can only come from an arithmetic instruction with overflow,
7350 // e.g. SADDO, UADDO.
7351 Cond = Cond.getNode()->getOperand(1);
7358 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
7359 SDValue Cmp = Cond.getOperand(0).getOperand(1);
7360 if (CondOpc == ISD::OR) {
7361 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
7362 // two branches instead of an explicit OR instruction with a
7364 if (Cmp == Cond.getOperand(1).getOperand(1) &&
7365 isX86LogicalCmp(Cmp)) {
7366 CC = Cond.getOperand(0).getOperand(0);
7367 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
7368 Chain, Dest, CC, Cmp);
7369 CC = Cond.getOperand(1).getOperand(0);
7373 } else { // ISD::AND
7374 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
7375 // two branches instead of an explicit AND instruction with a
7376 // separate test. However, we only do this if this block doesn't
7377 // have a fall-through edge, because this requires an explicit
7378 // jmp when the condition is false.
7379 if (Cmp == Cond.getOperand(1).getOperand(1) &&
7380 isX86LogicalCmp(Cmp) &&
7381 Op.getNode()->hasOneUse()) {
7382 X86::CondCode CCode =
7383 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
7384 CCode = X86::GetOppositeBranchCondition(CCode);
7385 CC = DAG.getConstant(CCode, MVT::i8);
7386 SDNode *User = *Op.getNode()->use_begin();
7387 // Look for an unconditional branch following this conditional branch.
7388 // We need this because we need to reverse the successors in order
7389 // to implement FCMP_OEQ.
7390 if (User->getOpcode() == ISD::BR) {
7391 SDValue FalseBB = User->getOperand(1);
7393 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
7394 assert(NewBR == User);
7398 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
7399 Chain, Dest, CC, Cmp);
7400 X86::CondCode CCode =
7401 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
7402 CCode = X86::GetOppositeBranchCondition(CCode);
7403 CC = DAG.getConstant(CCode, MVT::i8);
7409 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
7410 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
7411 // It should be transformed during dag combiner except when the condition
7412 // is set by a arithmetics with overflow node.
7413 X86::CondCode CCode =
7414 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
7415 CCode = X86::GetOppositeBranchCondition(CCode);
7416 CC = DAG.getConstant(CCode, MVT::i8);
7417 Cond = Cond.getOperand(0).getOperand(1);
7423 // Look pass the truncate.
7424 if (Cond.getOpcode() == ISD::TRUNCATE)
7425 Cond = Cond.getOperand(0);
7427 // We know the result of AND is compared against zero. Try to match
7429 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
7430 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
7431 if (NewSetCC.getNode()) {
7432 CC = NewSetCC.getOperand(0);
7433 Cond = NewSetCC.getOperand(1);
7440 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
7441 Cond = EmitTest(Cond, X86::COND_NE, DAG);
7443 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
7444 Chain, Dest, CC, Cond);
7448 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
7449 // Calls to _alloca is needed to probe the stack when allocating more than 4k
7450 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
7451 // that the guard pages used by the OS virtual memory manager are allocated in
7452 // correct sequence.
7454 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
7455 SelectionDAG &DAG) const {
7456 assert((Subtarget->isTargetCygMing() || Subtarget->isTargetWindows()) &&
7457 "This should be used only on Windows targets");
7458 DebugLoc dl = Op.getDebugLoc();
7461 SDValue Chain = Op.getOperand(0);
7462 SDValue Size = Op.getOperand(1);
7463 // FIXME: Ensure alignment here
7467 EVT SPTy = Subtarget->is64Bit() ? MVT::i64 : MVT::i32;
7469 Chain = DAG.getCopyToReg(Chain, dl, X86::EAX, Size, Flag);
7470 Flag = Chain.getValue(1);
7472 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
7474 Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag);
7475 Flag = Chain.getValue(1);
7477 Chain = DAG.getCopyFromReg(Chain, dl, X86StackPtr, SPTy).getValue(1);
7479 SDValue Ops1[2] = { Chain.getValue(0), Chain };
7480 return DAG.getMergeValues(Ops1, 2, dl);
7483 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
7484 MachineFunction &MF = DAG.getMachineFunction();
7485 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
7487 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
7488 DebugLoc DL = Op.getDebugLoc();
7490 if (!Subtarget->is64Bit() || Subtarget->isTargetWin64()) {
7491 // vastart just stores the address of the VarArgsFrameIndex slot into the
7492 // memory location argument.
7493 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
7495 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
7496 MachinePointerInfo(SV), false, false, 0);
7500 // gp_offset (0 - 6 * 8)
7501 // fp_offset (48 - 48 + 8 * 16)
7502 // overflow_arg_area (point to parameters coming in memory).
7504 SmallVector<SDValue, 8> MemOps;
7505 SDValue FIN = Op.getOperand(1);
7507 SDValue Store = DAG.getStore(Op.getOperand(0), DL,
7508 DAG.getConstant(FuncInfo->getVarArgsGPOffset(),
7510 FIN, MachinePointerInfo(SV), false, false, 0);
7511 MemOps.push_back(Store);
7514 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7515 FIN, DAG.getIntPtrConstant(4));
7516 Store = DAG.getStore(Op.getOperand(0), DL,
7517 DAG.getConstant(FuncInfo->getVarArgsFPOffset(),
7519 FIN, MachinePointerInfo(SV, 4), false, false, 0);
7520 MemOps.push_back(Store);
7522 // Store ptr to overflow_arg_area
7523 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7524 FIN, DAG.getIntPtrConstant(4));
7525 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
7527 Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN,
7528 MachinePointerInfo(SV, 8),
7530 MemOps.push_back(Store);
7532 // Store ptr to reg_save_area.
7533 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7534 FIN, DAG.getIntPtrConstant(8));
7535 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
7537 Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN,
7538 MachinePointerInfo(SV, 16), false, false, 0);
7539 MemOps.push_back(Store);
7540 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
7541 &MemOps[0], MemOps.size());
7544 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
7545 assert(Subtarget->is64Bit() &&
7546 "LowerVAARG only handles 64-bit va_arg!");
7547 assert((Subtarget->isTargetLinux() ||
7548 Subtarget->isTargetDarwin()) &&
7549 "Unhandled target in LowerVAARG");
7550 assert(Op.getNode()->getNumOperands() == 4);
7551 SDValue Chain = Op.getOperand(0);
7552 SDValue SrcPtr = Op.getOperand(1);
7553 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
7554 unsigned Align = Op.getConstantOperandVal(3);
7555 DebugLoc dl = Op.getDebugLoc();
7557 EVT ArgVT = Op.getNode()->getValueType(0);
7558 const Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
7559 uint32_t ArgSize = getTargetData()->getTypeAllocSize(ArgTy);
7562 // Decide which area this value should be read from.
7563 // TODO: Implement the AMD64 ABI in its entirety. This simple
7564 // selection mechanism works only for the basic types.
7565 if (ArgVT == MVT::f80) {
7566 llvm_unreachable("va_arg for f80 not yet implemented");
7567 } else if (ArgVT.isFloatingPoint() && ArgSize <= 16 /*bytes*/) {
7568 ArgMode = 2; // Argument passed in XMM register. Use fp_offset.
7569 } else if (ArgVT.isInteger() && ArgSize <= 32 /*bytes*/) {
7570 ArgMode = 1; // Argument passed in GPR64 register(s). Use gp_offset.
7572 llvm_unreachable("Unhandled argument type in LowerVAARG");
7576 // Sanity Check: Make sure using fp_offset makes sense.
7577 assert(!UseSoftFloat &&
7578 !(DAG.getMachineFunction()
7579 .getFunction()->hasFnAttr(Attribute::NoImplicitFloat)) &&
7580 Subtarget->hasSSE1());
7583 // Insert VAARG_64 node into the DAG
7584 // VAARG_64 returns two values: Variable Argument Address, Chain
7585 SmallVector<SDValue, 11> InstOps;
7586 InstOps.push_back(Chain);
7587 InstOps.push_back(SrcPtr);
7588 InstOps.push_back(DAG.getConstant(ArgSize, MVT::i32));
7589 InstOps.push_back(DAG.getConstant(ArgMode, MVT::i8));
7590 InstOps.push_back(DAG.getConstant(Align, MVT::i32));
7591 SDVTList VTs = DAG.getVTList(getPointerTy(), MVT::Other);
7592 SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl,
7593 VTs, &InstOps[0], InstOps.size(),
7595 MachinePointerInfo(SV),
7600 Chain = VAARG.getValue(1);
7602 // Load the next argument and return it
7603 return DAG.getLoad(ArgVT, dl,
7606 MachinePointerInfo(),
7610 SDValue X86TargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG) const {
7611 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
7612 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
7613 SDValue Chain = Op.getOperand(0);
7614 SDValue DstPtr = Op.getOperand(1);
7615 SDValue SrcPtr = Op.getOperand(2);
7616 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
7617 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
7618 DebugLoc DL = Op.getDebugLoc();
7620 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr,
7621 DAG.getIntPtrConstant(24), 8, /*isVolatile*/false,
7623 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
7627 X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const {
7628 DebugLoc dl = Op.getDebugLoc();
7629 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
7631 default: return SDValue(); // Don't custom lower most intrinsics.
7632 // Comparison intrinsics.
7633 case Intrinsic::x86_sse_comieq_ss:
7634 case Intrinsic::x86_sse_comilt_ss:
7635 case Intrinsic::x86_sse_comile_ss:
7636 case Intrinsic::x86_sse_comigt_ss:
7637 case Intrinsic::x86_sse_comige_ss:
7638 case Intrinsic::x86_sse_comineq_ss:
7639 case Intrinsic::x86_sse_ucomieq_ss:
7640 case Intrinsic::x86_sse_ucomilt_ss:
7641 case Intrinsic::x86_sse_ucomile_ss:
7642 case Intrinsic::x86_sse_ucomigt_ss:
7643 case Intrinsic::x86_sse_ucomige_ss:
7644 case Intrinsic::x86_sse_ucomineq_ss:
7645 case Intrinsic::x86_sse2_comieq_sd:
7646 case Intrinsic::x86_sse2_comilt_sd:
7647 case Intrinsic::x86_sse2_comile_sd:
7648 case Intrinsic::x86_sse2_comigt_sd:
7649 case Intrinsic::x86_sse2_comige_sd:
7650 case Intrinsic::x86_sse2_comineq_sd:
7651 case Intrinsic::x86_sse2_ucomieq_sd:
7652 case Intrinsic::x86_sse2_ucomilt_sd:
7653 case Intrinsic::x86_sse2_ucomile_sd:
7654 case Intrinsic::x86_sse2_ucomigt_sd:
7655 case Intrinsic::x86_sse2_ucomige_sd:
7656 case Intrinsic::x86_sse2_ucomineq_sd: {
7658 ISD::CondCode CC = ISD::SETCC_INVALID;
7661 case Intrinsic::x86_sse_comieq_ss:
7662 case Intrinsic::x86_sse2_comieq_sd:
7666 case Intrinsic::x86_sse_comilt_ss:
7667 case Intrinsic::x86_sse2_comilt_sd:
7671 case Intrinsic::x86_sse_comile_ss:
7672 case Intrinsic::x86_sse2_comile_sd:
7676 case Intrinsic::x86_sse_comigt_ss:
7677 case Intrinsic::x86_sse2_comigt_sd:
7681 case Intrinsic::x86_sse_comige_ss:
7682 case Intrinsic::x86_sse2_comige_sd:
7686 case Intrinsic::x86_sse_comineq_ss:
7687 case Intrinsic::x86_sse2_comineq_sd:
7691 case Intrinsic::x86_sse_ucomieq_ss:
7692 case Intrinsic::x86_sse2_ucomieq_sd:
7693 Opc = X86ISD::UCOMI;
7696 case Intrinsic::x86_sse_ucomilt_ss:
7697 case Intrinsic::x86_sse2_ucomilt_sd:
7698 Opc = X86ISD::UCOMI;
7701 case Intrinsic::x86_sse_ucomile_ss:
7702 case Intrinsic::x86_sse2_ucomile_sd:
7703 Opc = X86ISD::UCOMI;
7706 case Intrinsic::x86_sse_ucomigt_ss:
7707 case Intrinsic::x86_sse2_ucomigt_sd:
7708 Opc = X86ISD::UCOMI;
7711 case Intrinsic::x86_sse_ucomige_ss:
7712 case Intrinsic::x86_sse2_ucomige_sd:
7713 Opc = X86ISD::UCOMI;
7716 case Intrinsic::x86_sse_ucomineq_ss:
7717 case Intrinsic::x86_sse2_ucomineq_sd:
7718 Opc = X86ISD::UCOMI;
7723 SDValue LHS = Op.getOperand(1);
7724 SDValue RHS = Op.getOperand(2);
7725 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG);
7726 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!");
7727 SDValue Cond = DAG.getNode(Opc, dl, MVT::i32, LHS, RHS);
7728 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
7729 DAG.getConstant(X86CC, MVT::i8), Cond);
7730 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
7732 // ptest and testp intrinsics. The intrinsic these come from are designed to
7733 // return an integer value, not just an instruction so lower it to the ptest
7734 // or testp pattern and a setcc for the result.
7735 case Intrinsic::x86_sse41_ptestz:
7736 case Intrinsic::x86_sse41_ptestc:
7737 case Intrinsic::x86_sse41_ptestnzc:
7738 case Intrinsic::x86_avx_ptestz_256:
7739 case Intrinsic::x86_avx_ptestc_256:
7740 case Intrinsic::x86_avx_ptestnzc_256:
7741 case Intrinsic::x86_avx_vtestz_ps:
7742 case Intrinsic::x86_avx_vtestc_ps:
7743 case Intrinsic::x86_avx_vtestnzc_ps:
7744 case Intrinsic::x86_avx_vtestz_pd:
7745 case Intrinsic::x86_avx_vtestc_pd:
7746 case Intrinsic::x86_avx_vtestnzc_pd:
7747 case Intrinsic::x86_avx_vtestz_ps_256:
7748 case Intrinsic::x86_avx_vtestc_ps_256:
7749 case Intrinsic::x86_avx_vtestnzc_ps_256:
7750 case Intrinsic::x86_avx_vtestz_pd_256:
7751 case Intrinsic::x86_avx_vtestc_pd_256:
7752 case Intrinsic::x86_avx_vtestnzc_pd_256: {
7753 bool IsTestPacked = false;
7756 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
7757 case Intrinsic::x86_avx_vtestz_ps:
7758 case Intrinsic::x86_avx_vtestz_pd:
7759 case Intrinsic::x86_avx_vtestz_ps_256:
7760 case Intrinsic::x86_avx_vtestz_pd_256:
7761 IsTestPacked = true; // Fallthrough
7762 case Intrinsic::x86_sse41_ptestz:
7763 case Intrinsic::x86_avx_ptestz_256:
7765 X86CC = X86::COND_E;
7767 case Intrinsic::x86_avx_vtestc_ps:
7768 case Intrinsic::x86_avx_vtestc_pd:
7769 case Intrinsic::x86_avx_vtestc_ps_256:
7770 case Intrinsic::x86_avx_vtestc_pd_256:
7771 IsTestPacked = true; // Fallthrough
7772 case Intrinsic::x86_sse41_ptestc:
7773 case Intrinsic::x86_avx_ptestc_256:
7775 X86CC = X86::COND_B;
7777 case Intrinsic::x86_avx_vtestnzc_ps:
7778 case Intrinsic::x86_avx_vtestnzc_pd:
7779 case Intrinsic::x86_avx_vtestnzc_ps_256:
7780 case Intrinsic::x86_avx_vtestnzc_pd_256:
7781 IsTestPacked = true; // Fallthrough
7782 case Intrinsic::x86_sse41_ptestnzc:
7783 case Intrinsic::x86_avx_ptestnzc_256:
7785 X86CC = X86::COND_A;
7789 SDValue LHS = Op.getOperand(1);
7790 SDValue RHS = Op.getOperand(2);
7791 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST;
7792 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS);
7793 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
7794 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
7795 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
7798 // Fix vector shift instructions where the last operand is a non-immediate
7800 case Intrinsic::x86_sse2_pslli_w:
7801 case Intrinsic::x86_sse2_pslli_d:
7802 case Intrinsic::x86_sse2_pslli_q:
7803 case Intrinsic::x86_sse2_psrli_w:
7804 case Intrinsic::x86_sse2_psrli_d:
7805 case Intrinsic::x86_sse2_psrli_q:
7806 case Intrinsic::x86_sse2_psrai_w:
7807 case Intrinsic::x86_sse2_psrai_d:
7808 case Intrinsic::x86_mmx_pslli_w:
7809 case Intrinsic::x86_mmx_pslli_d:
7810 case Intrinsic::x86_mmx_pslli_q:
7811 case Intrinsic::x86_mmx_psrli_w:
7812 case Intrinsic::x86_mmx_psrli_d:
7813 case Intrinsic::x86_mmx_psrli_q:
7814 case Intrinsic::x86_mmx_psrai_w:
7815 case Intrinsic::x86_mmx_psrai_d: {
7816 SDValue ShAmt = Op.getOperand(2);
7817 if (isa<ConstantSDNode>(ShAmt))
7820 unsigned NewIntNo = 0;
7821 EVT ShAmtVT = MVT::v4i32;
7823 case Intrinsic::x86_sse2_pslli_w:
7824 NewIntNo = Intrinsic::x86_sse2_psll_w;
7826 case Intrinsic::x86_sse2_pslli_d:
7827 NewIntNo = Intrinsic::x86_sse2_psll_d;
7829 case Intrinsic::x86_sse2_pslli_q:
7830 NewIntNo = Intrinsic::x86_sse2_psll_q;
7832 case Intrinsic::x86_sse2_psrli_w:
7833 NewIntNo = Intrinsic::x86_sse2_psrl_w;
7835 case Intrinsic::x86_sse2_psrli_d:
7836 NewIntNo = Intrinsic::x86_sse2_psrl_d;
7838 case Intrinsic::x86_sse2_psrli_q:
7839 NewIntNo = Intrinsic::x86_sse2_psrl_q;
7841 case Intrinsic::x86_sse2_psrai_w:
7842 NewIntNo = Intrinsic::x86_sse2_psra_w;
7844 case Intrinsic::x86_sse2_psrai_d:
7845 NewIntNo = Intrinsic::x86_sse2_psra_d;
7848 ShAmtVT = MVT::v2i32;
7850 case Intrinsic::x86_mmx_pslli_w:
7851 NewIntNo = Intrinsic::x86_mmx_psll_w;
7853 case Intrinsic::x86_mmx_pslli_d:
7854 NewIntNo = Intrinsic::x86_mmx_psll_d;
7856 case Intrinsic::x86_mmx_pslli_q:
7857 NewIntNo = Intrinsic::x86_mmx_psll_q;
7859 case Intrinsic::x86_mmx_psrli_w:
7860 NewIntNo = Intrinsic::x86_mmx_psrl_w;
7862 case Intrinsic::x86_mmx_psrli_d:
7863 NewIntNo = Intrinsic::x86_mmx_psrl_d;
7865 case Intrinsic::x86_mmx_psrli_q:
7866 NewIntNo = Intrinsic::x86_mmx_psrl_q;
7868 case Intrinsic::x86_mmx_psrai_w:
7869 NewIntNo = Intrinsic::x86_mmx_psra_w;
7871 case Intrinsic::x86_mmx_psrai_d:
7872 NewIntNo = Intrinsic::x86_mmx_psra_d;
7874 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
7880 // The vector shift intrinsics with scalars uses 32b shift amounts but
7881 // the sse2/mmx shift instructions reads 64 bits. Set the upper 32 bits
7885 ShOps[1] = DAG.getConstant(0, MVT::i32);
7886 if (ShAmtVT == MVT::v4i32) {
7887 ShOps[2] = DAG.getUNDEF(MVT::i32);
7888 ShOps[3] = DAG.getUNDEF(MVT::i32);
7889 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, ShAmtVT, &ShOps[0], 4);
7891 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, ShAmtVT, &ShOps[0], 2);
7892 // FIXME this must be lowered to get rid of the invalid type.
7895 EVT VT = Op.getValueType();
7896 ShAmt = DAG.getNode(ISD::BIT_CONVERT, dl, VT, ShAmt);
7897 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
7898 DAG.getConstant(NewIntNo, MVT::i32),
7899 Op.getOperand(1), ShAmt);
7904 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op,
7905 SelectionDAG &DAG) const {
7906 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
7907 MFI->setReturnAddressIsTaken(true);
7909 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
7910 DebugLoc dl = Op.getDebugLoc();
7913 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
7915 DAG.getConstant(TD->getPointerSize(),
7916 Subtarget->is64Bit() ? MVT::i64 : MVT::i32);
7917 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
7918 DAG.getNode(ISD::ADD, dl, getPointerTy(),
7920 MachinePointerInfo(), false, false, 0);
7923 // Just load the return address.
7924 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
7925 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
7926 RetAddrFI, MachinePointerInfo(), false, false, 0);
7929 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
7930 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
7931 MFI->setFrameAddressIsTaken(true);
7933 EVT VT = Op.getValueType();
7934 DebugLoc dl = Op.getDebugLoc(); // FIXME probably not meaningful
7935 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
7936 unsigned FrameReg = Subtarget->is64Bit() ? X86::RBP : X86::EBP;
7937 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
7939 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
7940 MachinePointerInfo(),
7945 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
7946 SelectionDAG &DAG) const {
7947 return DAG.getIntPtrConstant(2*TD->getPointerSize());
7950 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
7951 MachineFunction &MF = DAG.getMachineFunction();
7952 SDValue Chain = Op.getOperand(0);
7953 SDValue Offset = Op.getOperand(1);
7954 SDValue Handler = Op.getOperand(2);
7955 DebugLoc dl = Op.getDebugLoc();
7957 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl,
7958 Subtarget->is64Bit() ? X86::RBP : X86::EBP,
7960 unsigned StoreAddrReg = (Subtarget->is64Bit() ? X86::RCX : X86::ECX);
7962 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), Frame,
7963 DAG.getIntPtrConstant(TD->getPointerSize()));
7964 StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), StoreAddr, Offset);
7965 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(),
7967 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
7968 MF.getRegInfo().addLiveOut(StoreAddrReg);
7970 return DAG.getNode(X86ISD::EH_RETURN, dl,
7972 Chain, DAG.getRegister(StoreAddrReg, getPointerTy()));
7975 SDValue X86TargetLowering::LowerTRAMPOLINE(SDValue Op,
7976 SelectionDAG &DAG) const {
7977 SDValue Root = Op.getOperand(0);
7978 SDValue Trmp = Op.getOperand(1); // trampoline
7979 SDValue FPtr = Op.getOperand(2); // nested function
7980 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
7981 DebugLoc dl = Op.getDebugLoc();
7983 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
7985 if (Subtarget->is64Bit()) {
7986 SDValue OutChains[6];
7988 // Large code-model.
7989 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode.
7990 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode.
7992 const unsigned char N86R10 = RegInfo->getX86RegNum(X86::R10);
7993 const unsigned char N86R11 = RegInfo->getX86RegNum(X86::R11);
7995 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
7997 // Load the pointer to the nested function into R11.
7998 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
7999 SDValue Addr = Trmp;
8000 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
8001 Addr, MachinePointerInfo(TrmpAddr),
8004 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
8005 DAG.getConstant(2, MVT::i64));
8006 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr,
8007 MachinePointerInfo(TrmpAddr, 2),
8010 // Load the 'nest' parameter value into R10.
8011 // R10 is specified in X86CallingConv.td
8012 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
8013 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
8014 DAG.getConstant(10, MVT::i64));
8015 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
8016 Addr, MachinePointerInfo(TrmpAddr, 10),
8019 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
8020 DAG.getConstant(12, MVT::i64));
8021 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr,
8022 MachinePointerInfo(TrmpAddr, 12),
8025 // Jump to the nested function.
8026 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
8027 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
8028 DAG.getConstant(20, MVT::i64));
8029 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
8030 Addr, MachinePointerInfo(TrmpAddr, 20),
8033 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
8034 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
8035 DAG.getConstant(22, MVT::i64));
8036 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr,
8037 MachinePointerInfo(TrmpAddr, 22),
8041 { Trmp, DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 6) };
8042 return DAG.getMergeValues(Ops, 2, dl);
8044 const Function *Func =
8045 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
8046 CallingConv::ID CC = Func->getCallingConv();
8051 llvm_unreachable("Unsupported calling convention");
8052 case CallingConv::C:
8053 case CallingConv::X86_StdCall: {
8054 // Pass 'nest' parameter in ECX.
8055 // Must be kept in sync with X86CallingConv.td
8058 // Check that ECX wasn't needed by an 'inreg' parameter.
8059 const FunctionType *FTy = Func->getFunctionType();
8060 const AttrListPtr &Attrs = Func->getAttributes();
8062 if (!Attrs.isEmpty() && !Func->isVarArg()) {
8063 unsigned InRegCount = 0;
8066 for (FunctionType::param_iterator I = FTy->param_begin(),
8067 E = FTy->param_end(); I != E; ++I, ++Idx)
8068 if (Attrs.paramHasAttr(Idx, Attribute::InReg))
8069 // FIXME: should only count parameters that are lowered to integers.
8070 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32;
8072 if (InRegCount > 2) {
8073 report_fatal_error("Nest register in use - reduce number of inreg"
8079 case CallingConv::X86_FastCall:
8080 case CallingConv::X86_ThisCall:
8081 case CallingConv::Fast:
8082 // Pass 'nest' parameter in EAX.
8083 // Must be kept in sync with X86CallingConv.td
8088 SDValue OutChains[4];
8091 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
8092 DAG.getConstant(10, MVT::i32));
8093 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
8095 // This is storing the opcode for MOV32ri.
8096 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte.
8097 const unsigned char N86Reg = RegInfo->getX86RegNum(NestReg);
8098 OutChains[0] = DAG.getStore(Root, dl,
8099 DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
8100 Trmp, MachinePointerInfo(TrmpAddr),
8103 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
8104 DAG.getConstant(1, MVT::i32));
8105 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr,
8106 MachinePointerInfo(TrmpAddr, 1),
8109 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode.
8110 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
8111 DAG.getConstant(5, MVT::i32));
8112 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr,
8113 MachinePointerInfo(TrmpAddr, 5),
8116 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
8117 DAG.getConstant(6, MVT::i32));
8118 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr,
8119 MachinePointerInfo(TrmpAddr, 6),
8123 { Trmp, DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 4) };
8124 return DAG.getMergeValues(Ops, 2, dl);
8128 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op,
8129 SelectionDAG &DAG) const {
8131 The rounding mode is in bits 11:10 of FPSR, and has the following
8138 FLT_ROUNDS, on the other hand, expects the following:
8145 To perform the conversion, we do:
8146 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
8149 MachineFunction &MF = DAG.getMachineFunction();
8150 const TargetMachine &TM = MF.getTarget();
8151 const TargetFrameInfo &TFI = *TM.getFrameInfo();
8152 unsigned StackAlignment = TFI.getStackAlignment();
8153 EVT VT = Op.getValueType();
8154 DebugLoc DL = Op.getDebugLoc();
8156 // Save FP Control Word to stack slot
8157 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false);
8158 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
8161 MachineMemOperand *MMO =
8162 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
8163 MachineMemOperand::MOStore, 2, 2);
8165 SDValue Ops[] = { DAG.getEntryNode(), StackSlot };
8166 SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL,
8167 DAG.getVTList(MVT::Other),
8168 Ops, 2, MVT::i16, MMO);
8170 // Load FP Control Word from stack slot
8171 SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot,
8172 MachinePointerInfo(), false, false, 0);
8174 // Transform as necessary
8176 DAG.getNode(ISD::SRL, DL, MVT::i16,
8177 DAG.getNode(ISD::AND, DL, MVT::i16,
8178 CWD, DAG.getConstant(0x800, MVT::i16)),
8179 DAG.getConstant(11, MVT::i8));
8181 DAG.getNode(ISD::SRL, DL, MVT::i16,
8182 DAG.getNode(ISD::AND, DL, MVT::i16,
8183 CWD, DAG.getConstant(0x400, MVT::i16)),
8184 DAG.getConstant(9, MVT::i8));
8187 DAG.getNode(ISD::AND, DL, MVT::i16,
8188 DAG.getNode(ISD::ADD, DL, MVT::i16,
8189 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2),
8190 DAG.getConstant(1, MVT::i16)),
8191 DAG.getConstant(3, MVT::i16));
8194 return DAG.getNode((VT.getSizeInBits() < 16 ?
8195 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal);
8198 SDValue X86TargetLowering::LowerCTLZ(SDValue Op, SelectionDAG &DAG) const {
8199 EVT VT = Op.getValueType();
8201 unsigned NumBits = VT.getSizeInBits();
8202 DebugLoc dl = Op.getDebugLoc();
8204 Op = Op.getOperand(0);
8205 if (VT == MVT::i8) {
8206 // Zero extend to i32 since there is not an i8 bsr.
8208 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
8211 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
8212 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
8213 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
8215 // If src is zero (i.e. bsr sets ZF), returns NumBits.
8218 DAG.getConstant(NumBits+NumBits-1, OpVT),
8219 DAG.getConstant(X86::COND_E, MVT::i8),
8222 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops, array_lengthof(Ops));
8224 // Finally xor with NumBits-1.
8225 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
8228 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
8232 SDValue X86TargetLowering::LowerCTTZ(SDValue Op, SelectionDAG &DAG) const {
8233 EVT VT = Op.getValueType();
8235 unsigned NumBits = VT.getSizeInBits();
8236 DebugLoc dl = Op.getDebugLoc();
8238 Op = Op.getOperand(0);
8239 if (VT == MVT::i8) {
8241 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
8244 // Issue a bsf (scan bits forward) which also sets EFLAGS.
8245 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
8246 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op);
8248 // If src is zero (i.e. bsf sets ZF), returns NumBits.
8251 DAG.getConstant(NumBits, OpVT),
8252 DAG.getConstant(X86::COND_E, MVT::i8),
8255 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops, array_lengthof(Ops));
8258 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
8262 SDValue X86TargetLowering::LowerMUL_V2I64(SDValue Op, SelectionDAG &DAG) const {
8263 EVT VT = Op.getValueType();
8264 assert(VT == MVT::v2i64 && "Only know how to lower V2I64 multiply");
8265 DebugLoc dl = Op.getDebugLoc();
8267 // ulong2 Ahi = __builtin_ia32_psrlqi128( a, 32);
8268 // ulong2 Bhi = __builtin_ia32_psrlqi128( b, 32);
8269 // ulong2 AloBlo = __builtin_ia32_pmuludq128( a, b );
8270 // ulong2 AloBhi = __builtin_ia32_pmuludq128( a, Bhi );
8271 // ulong2 AhiBlo = __builtin_ia32_pmuludq128( Ahi, b );
8273 // AloBhi = __builtin_ia32_psllqi128( AloBhi, 32 );
8274 // AhiBlo = __builtin_ia32_psllqi128( AhiBlo, 32 );
8275 // return AloBlo + AloBhi + AhiBlo;
8277 SDValue A = Op.getOperand(0);
8278 SDValue B = Op.getOperand(1);
8280 SDValue Ahi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
8281 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32),
8282 A, DAG.getConstant(32, MVT::i32));
8283 SDValue Bhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
8284 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32),
8285 B, DAG.getConstant(32, MVT::i32));
8286 SDValue AloBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
8287 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32),
8289 SDValue AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
8290 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32),
8292 SDValue AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
8293 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32),
8295 AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
8296 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32),
8297 AloBhi, DAG.getConstant(32, MVT::i32));
8298 AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
8299 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32),
8300 AhiBlo, DAG.getConstant(32, MVT::i32));
8301 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
8302 Res = DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
8306 SDValue X86TargetLowering::LowerSHL(SDValue Op, SelectionDAG &DAG) const {
8307 EVT VT = Op.getValueType();
8308 DebugLoc dl = Op.getDebugLoc();
8309 SDValue R = Op.getOperand(0);
8311 LLVMContext *Context = DAG.getContext();
8313 assert(Subtarget->hasSSE41() && "Cannot lower SHL without SSE4.1 or later");
8315 if (VT == MVT::v4i32) {
8316 Op = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
8317 DAG.getConstant(Intrinsic::x86_sse2_pslli_d, MVT::i32),
8318 Op.getOperand(1), DAG.getConstant(23, MVT::i32));
8320 ConstantInt *CI = ConstantInt::get(*Context, APInt(32, 0x3f800000U));
8322 std::vector<Constant*> CV(4, CI);
8323 Constant *C = ConstantVector::get(CV);
8324 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
8325 SDValue Addend = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
8326 MachinePointerInfo::getConstantPool(),
8329 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Addend);
8330 Op = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v4f32, Op);
8331 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op);
8332 return DAG.getNode(ISD::MUL, dl, VT, Op, R);
8334 if (VT == MVT::v16i8) {
8336 Op = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
8337 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32),
8338 Op.getOperand(1), DAG.getConstant(5, MVT::i32));
8340 ConstantInt *CM1 = ConstantInt::get(*Context, APInt(8, 15));
8341 ConstantInt *CM2 = ConstantInt::get(*Context, APInt(8, 63));
8343 std::vector<Constant*> CVM1(16, CM1);
8344 std::vector<Constant*> CVM2(16, CM2);
8345 Constant *C = ConstantVector::get(CVM1);
8346 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
8347 SDValue M = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
8348 MachinePointerInfo::getConstantPool(),
8351 // r = pblendv(r, psllw(r & (char16)15, 4), a);
8352 M = DAG.getNode(ISD::AND, dl, VT, R, M);
8353 M = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
8354 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32), M,
8355 DAG.getConstant(4, MVT::i32));
8356 R = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
8357 DAG.getConstant(Intrinsic::x86_sse41_pblendvb, MVT::i32),
8360 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
8362 C = ConstantVector::get(CVM2);
8363 CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
8364 M = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
8365 MachinePointerInfo::getConstantPool(),
8368 // r = pblendv(r, psllw(r & (char16)63, 2), a);
8369 M = DAG.getNode(ISD::AND, dl, VT, R, M);
8370 M = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
8371 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32), M,
8372 DAG.getConstant(2, MVT::i32));
8373 R = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
8374 DAG.getConstant(Intrinsic::x86_sse41_pblendvb, MVT::i32),
8377 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
8379 // return pblendv(r, r+r, a);
8380 R = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
8381 DAG.getConstant(Intrinsic::x86_sse41_pblendvb, MVT::i32),
8382 R, DAG.getNode(ISD::ADD, dl, VT, R, R), Op);
8388 SDValue X86TargetLowering::LowerXALUO(SDValue Op, SelectionDAG &DAG) const {
8389 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
8390 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
8391 // looks for this combo and may remove the "setcc" instruction if the "setcc"
8392 // has only one use.
8393 SDNode *N = Op.getNode();
8394 SDValue LHS = N->getOperand(0);
8395 SDValue RHS = N->getOperand(1);
8396 unsigned BaseOp = 0;
8398 DebugLoc dl = Op.getDebugLoc();
8400 switch (Op.getOpcode()) {
8401 default: llvm_unreachable("Unknown ovf instruction!");
8403 // A subtract of one will be selected as a INC. Note that INC doesn't
8404 // set CF, so we can't do this for UADDO.
8405 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op))
8406 if (C->getAPIntValue() == 1) {
8407 BaseOp = X86ISD::INC;
8411 BaseOp = X86ISD::ADD;
8415 BaseOp = X86ISD::ADD;
8419 // A subtract of one will be selected as a DEC. Note that DEC doesn't
8420 // set CF, so we can't do this for USUBO.
8421 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op))
8422 if (C->getAPIntValue() == 1) {
8423 BaseOp = X86ISD::DEC;
8427 BaseOp = X86ISD::SUB;
8431 BaseOp = X86ISD::SUB;
8435 BaseOp = X86ISD::SMUL;
8439 BaseOp = X86ISD::UMUL;
8444 // Also sets EFLAGS.
8445 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
8446 SDValue Sum = DAG.getNode(BaseOp, dl, VTs, LHS, RHS);
8449 DAG.getNode(X86ISD::SETCC, dl, N->getValueType(1),
8450 DAG.getConstant(Cond, MVT::i32), SDValue(Sum.getNode(), 1));
8452 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), SetCC);
8456 SDValue X86TargetLowering::LowerMEMBARRIER(SDValue Op, SelectionDAG &DAG) const{
8457 DebugLoc dl = Op.getDebugLoc();
8459 if (!Subtarget->hasSSE2()) {
8460 SDValue Chain = Op.getOperand(0);
8461 SDValue Zero = DAG.getConstant(0,
8462 Subtarget->is64Bit() ? MVT::i64 : MVT::i32);
8464 DAG.getRegister(X86::ESP, MVT::i32), // Base
8465 DAG.getTargetConstant(1, MVT::i8), // Scale
8466 DAG.getRegister(0, MVT::i32), // Index
8467 DAG.getTargetConstant(0, MVT::i32), // Disp
8468 DAG.getRegister(0, MVT::i32), // Segment.
8473 DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops,
8474 array_lengthof(Ops));
8475 return SDValue(Res, 0);
8478 unsigned isDev = cast<ConstantSDNode>(Op.getOperand(5))->getZExtValue();
8480 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
8482 unsigned Op1 = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
8483 unsigned Op2 = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
8484 unsigned Op3 = cast<ConstantSDNode>(Op.getOperand(3))->getZExtValue();
8485 unsigned Op4 = cast<ConstantSDNode>(Op.getOperand(4))->getZExtValue();
8487 // def : Pat<(membarrier (i8 0), (i8 0), (i8 0), (i8 1), (i8 1)), (SFENCE)>;
8488 if (!Op1 && !Op2 && !Op3 && Op4)
8489 return DAG.getNode(X86ISD::SFENCE, dl, MVT::Other, Op.getOperand(0));
8491 // def : Pat<(membarrier (i8 1), (i8 0), (i8 0), (i8 0), (i8 1)), (LFENCE)>;
8492 if (Op1 && !Op2 && !Op3 && !Op4)
8493 return DAG.getNode(X86ISD::LFENCE, dl, MVT::Other, Op.getOperand(0));
8495 // def : Pat<(membarrier (i8 imm), (i8 imm), (i8 imm), (i8 imm), (i8 1)),
8497 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
8500 SDValue X86TargetLowering::LowerCMP_SWAP(SDValue Op, SelectionDAG &DAG) const {
8501 EVT T = Op.getValueType();
8502 DebugLoc DL = Op.getDebugLoc();
8505 switch(T.getSimpleVT().SimpleTy) {
8507 assert(false && "Invalid value type!");
8508 case MVT::i8: Reg = X86::AL; size = 1; break;
8509 case MVT::i16: Reg = X86::AX; size = 2; break;
8510 case MVT::i32: Reg = X86::EAX; size = 4; break;
8512 assert(Subtarget->is64Bit() && "Node not type legal!");
8513 Reg = X86::RAX; size = 8;
8516 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg,
8517 Op.getOperand(2), SDValue());
8518 SDValue Ops[] = { cpIn.getValue(0),
8521 DAG.getTargetConstant(size, MVT::i8),
8523 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
8524 MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand();
8525 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys,
8528 DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1));
8532 SDValue X86TargetLowering::LowerREADCYCLECOUNTER(SDValue Op,
8533 SelectionDAG &DAG) const {
8534 assert(Subtarget->is64Bit() && "Result not type legalized?");
8535 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
8536 SDValue TheChain = Op.getOperand(0);
8537 DebugLoc dl = Op.getDebugLoc();
8538 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
8539 SDValue rax = DAG.getCopyFromReg(rd, dl, X86::RAX, MVT::i64, rd.getValue(1));
8540 SDValue rdx = DAG.getCopyFromReg(rax.getValue(1), dl, X86::RDX, MVT::i64,
8542 SDValue Tmp = DAG.getNode(ISD::SHL, dl, MVT::i64, rdx,
8543 DAG.getConstant(32, MVT::i8));
8545 DAG.getNode(ISD::OR, dl, MVT::i64, rax, Tmp),
8548 return DAG.getMergeValues(Ops, 2, dl);
8551 SDValue X86TargetLowering::LowerBIT_CONVERT(SDValue Op,
8552 SelectionDAG &DAG) const {
8553 EVT SrcVT = Op.getOperand(0).getValueType();
8554 EVT DstVT = Op.getValueType();
8555 assert((Subtarget->is64Bit() && !Subtarget->hasSSE2() &&
8556 Subtarget->hasMMX() && !DisableMMX) &&
8557 "Unexpected custom BIT_CONVERT");
8558 assert((DstVT == MVT::i64 ||
8559 (DstVT.isVector() && DstVT.getSizeInBits()==64)) &&
8560 "Unexpected custom BIT_CONVERT");
8561 // i64 <=> MMX conversions are Legal.
8562 if (SrcVT==MVT::i64 && DstVT.isVector())
8564 if (DstVT==MVT::i64 && SrcVT.isVector())
8566 // MMX <=> MMX conversions are Legal.
8567 if (SrcVT.isVector() && DstVT.isVector())
8569 // All other conversions need to be expanded.
8572 SDValue X86TargetLowering::LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) const {
8573 SDNode *Node = Op.getNode();
8574 DebugLoc dl = Node->getDebugLoc();
8575 EVT T = Node->getValueType(0);
8576 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
8577 DAG.getConstant(0, T), Node->getOperand(2));
8578 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
8579 cast<AtomicSDNode>(Node)->getMemoryVT(),
8580 Node->getOperand(0),
8581 Node->getOperand(1), negOp,
8582 cast<AtomicSDNode>(Node)->getSrcValue(),
8583 cast<AtomicSDNode>(Node)->getAlignment());
8586 /// LowerOperation - Provide custom lowering hooks for some operations.
8588 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
8589 switch (Op.getOpcode()) {
8590 default: llvm_unreachable("Should not custom lower this!");
8591 case ISD::MEMBARRIER: return LowerMEMBARRIER(Op,DAG);
8592 case ISD::ATOMIC_CMP_SWAP: return LowerCMP_SWAP(Op,DAG);
8593 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
8594 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
8595 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
8596 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
8597 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
8598 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
8599 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
8600 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
8601 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
8602 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
8603 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
8604 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
8605 case ISD::SHL_PARTS:
8606 case ISD::SRA_PARTS:
8607 case ISD::SRL_PARTS: return LowerShift(Op, DAG);
8608 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
8609 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
8610 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
8611 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
8612 case ISD::FABS: return LowerFABS(Op, DAG);
8613 case ISD::FNEG: return LowerFNEG(Op, DAG);
8614 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
8615 case ISD::SETCC: return LowerSETCC(Op, DAG);
8616 case ISD::VSETCC: return LowerVSETCC(Op, DAG);
8617 case ISD::SELECT: return LowerSELECT(Op, DAG);
8618 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
8619 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
8620 case ISD::VASTART: return LowerVASTART(Op, DAG);
8621 case ISD::VAARG: return LowerVAARG(Op, DAG);
8622 case ISD::VACOPY: return LowerVACOPY(Op, DAG);
8623 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
8624 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
8625 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
8626 case ISD::FRAME_TO_ARGS_OFFSET:
8627 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
8628 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
8629 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
8630 case ISD::TRAMPOLINE: return LowerTRAMPOLINE(Op, DAG);
8631 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
8632 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
8633 case ISD::CTTZ: return LowerCTTZ(Op, DAG);
8634 case ISD::MUL: return LowerMUL_V2I64(Op, DAG);
8635 case ISD::SHL: return LowerSHL(Op, DAG);
8641 case ISD::UMULO: return LowerXALUO(Op, DAG);
8642 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, DAG);
8643 case ISD::BIT_CONVERT: return LowerBIT_CONVERT(Op, DAG);
8647 void X86TargetLowering::
8648 ReplaceATOMIC_BINARY_64(SDNode *Node, SmallVectorImpl<SDValue>&Results,
8649 SelectionDAG &DAG, unsigned NewOp) const {
8650 EVT T = Node->getValueType(0);
8651 DebugLoc dl = Node->getDebugLoc();
8652 assert (T == MVT::i64 && "Only know how to expand i64 atomics");
8654 SDValue Chain = Node->getOperand(0);
8655 SDValue In1 = Node->getOperand(1);
8656 SDValue In2L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
8657 Node->getOperand(2), DAG.getIntPtrConstant(0));
8658 SDValue In2H = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
8659 Node->getOperand(2), DAG.getIntPtrConstant(1));
8660 SDValue Ops[] = { Chain, In1, In2L, In2H };
8661 SDVTList Tys = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other);
8663 DAG.getMemIntrinsicNode(NewOp, dl, Tys, Ops, 4, MVT::i64,
8664 cast<MemSDNode>(Node)->getMemOperand());
8665 SDValue OpsF[] = { Result.getValue(0), Result.getValue(1)};
8666 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2));
8667 Results.push_back(Result.getValue(2));
8670 /// ReplaceNodeResults - Replace a node with an illegal result type
8671 /// with a new node built out of custom code.
8672 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
8673 SmallVectorImpl<SDValue>&Results,
8674 SelectionDAG &DAG) const {
8675 DebugLoc dl = N->getDebugLoc();
8676 switch (N->getOpcode()) {
8678 assert(false && "Do not know how to custom type legalize this operation!");
8680 case ISD::FP_TO_SINT: {
8681 std::pair<SDValue,SDValue> Vals =
8682 FP_TO_INTHelper(SDValue(N, 0), DAG, true);
8683 SDValue FIST = Vals.first, StackSlot = Vals.second;
8684 if (FIST.getNode() != 0) {
8685 EVT VT = N->getValueType(0);
8686 // Return a load from the stack slot.
8687 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot,
8688 MachinePointerInfo(), false, false, 0));
8692 case ISD::READCYCLECOUNTER: {
8693 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
8694 SDValue TheChain = N->getOperand(0);
8695 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
8696 SDValue eax = DAG.getCopyFromReg(rd, dl, X86::EAX, MVT::i32,
8698 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), dl, X86::EDX, MVT::i32,
8700 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
8701 SDValue Ops[] = { eax, edx };
8702 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Ops, 2));
8703 Results.push_back(edx.getValue(1));
8706 case ISD::ATOMIC_CMP_SWAP: {
8707 EVT T = N->getValueType(0);
8708 assert (T == MVT::i64 && "Only know how to expand i64 Cmp and Swap");
8709 SDValue cpInL, cpInH;
8710 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(2),
8711 DAG.getConstant(0, MVT::i32));
8712 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(2),
8713 DAG.getConstant(1, MVT::i32));
8714 cpInL = DAG.getCopyToReg(N->getOperand(0), dl, X86::EAX, cpInL, SDValue());
8715 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl, X86::EDX, cpInH,
8717 SDValue swapInL, swapInH;
8718 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(3),
8719 DAG.getConstant(0, MVT::i32));
8720 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(3),
8721 DAG.getConstant(1, MVT::i32));
8722 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl, X86::EBX, swapInL,
8724 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl, X86::ECX, swapInH,
8725 swapInL.getValue(1));
8726 SDValue Ops[] = { swapInH.getValue(0),
8728 swapInH.getValue(1) };
8729 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
8730 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand();
8731 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG8_DAG, dl, Tys,
8733 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl, X86::EAX,
8734 MVT::i32, Result.getValue(1));
8735 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl, X86::EDX,
8736 MVT::i32, cpOutL.getValue(2));
8737 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
8738 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2));
8739 Results.push_back(cpOutH.getValue(1));
8742 case ISD::ATOMIC_LOAD_ADD:
8743 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMADD64_DAG);
8745 case ISD::ATOMIC_LOAD_AND:
8746 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMAND64_DAG);
8748 case ISD::ATOMIC_LOAD_NAND:
8749 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMNAND64_DAG);
8751 case ISD::ATOMIC_LOAD_OR:
8752 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMOR64_DAG);
8754 case ISD::ATOMIC_LOAD_SUB:
8755 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSUB64_DAG);
8757 case ISD::ATOMIC_LOAD_XOR:
8758 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMXOR64_DAG);
8760 case ISD::ATOMIC_SWAP:
8761 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSWAP64_DAG);
8766 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
8768 default: return NULL;
8769 case X86ISD::BSF: return "X86ISD::BSF";
8770 case X86ISD::BSR: return "X86ISD::BSR";
8771 case X86ISD::SHLD: return "X86ISD::SHLD";
8772 case X86ISD::SHRD: return "X86ISD::SHRD";
8773 case X86ISD::FAND: return "X86ISD::FAND";
8774 case X86ISD::FOR: return "X86ISD::FOR";
8775 case X86ISD::FXOR: return "X86ISD::FXOR";
8776 case X86ISD::FSRL: return "X86ISD::FSRL";
8777 case X86ISD::FILD: return "X86ISD::FILD";
8778 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
8779 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
8780 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
8781 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
8782 case X86ISD::FLD: return "X86ISD::FLD";
8783 case X86ISD::FST: return "X86ISD::FST";
8784 case X86ISD::CALL: return "X86ISD::CALL";
8785 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
8786 case X86ISD::BT: return "X86ISD::BT";
8787 case X86ISD::CMP: return "X86ISD::CMP";
8788 case X86ISD::COMI: return "X86ISD::COMI";
8789 case X86ISD::UCOMI: return "X86ISD::UCOMI";
8790 case X86ISD::SETCC: return "X86ISD::SETCC";
8791 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY";
8792 case X86ISD::CMOV: return "X86ISD::CMOV";
8793 case X86ISD::BRCOND: return "X86ISD::BRCOND";
8794 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
8795 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
8796 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
8797 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
8798 case X86ISD::Wrapper: return "X86ISD::Wrapper";
8799 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
8800 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
8801 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
8802 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
8803 case X86ISD::PINSRB: return "X86ISD::PINSRB";
8804 case X86ISD::PINSRW: return "X86ISD::PINSRW";
8805 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
8806 case X86ISD::FMAX: return "X86ISD::FMAX";
8807 case X86ISD::FMIN: return "X86ISD::FMIN";
8808 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
8809 case X86ISD::FRCP: return "X86ISD::FRCP";
8810 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
8811 case X86ISD::TLSCALL: return "X86ISD::TLSCALL";
8812 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
8813 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
8814 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
8815 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
8816 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
8817 case X86ISD::ATOMADD64_DAG: return "X86ISD::ATOMADD64_DAG";
8818 case X86ISD::ATOMSUB64_DAG: return "X86ISD::ATOMSUB64_DAG";
8819 case X86ISD::ATOMOR64_DAG: return "X86ISD::ATOMOR64_DAG";
8820 case X86ISD::ATOMXOR64_DAG: return "X86ISD::ATOMXOR64_DAG";
8821 case X86ISD::ATOMAND64_DAG: return "X86ISD::ATOMAND64_DAG";
8822 case X86ISD::ATOMNAND64_DAG: return "X86ISD::ATOMNAND64_DAG";
8823 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
8824 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
8825 case X86ISD::VSHL: return "X86ISD::VSHL";
8826 case X86ISD::VSRL: return "X86ISD::VSRL";
8827 case X86ISD::CMPPD: return "X86ISD::CMPPD";
8828 case X86ISD::CMPPS: return "X86ISD::CMPPS";
8829 case X86ISD::PCMPEQB: return "X86ISD::PCMPEQB";
8830 case X86ISD::PCMPEQW: return "X86ISD::PCMPEQW";
8831 case X86ISD::PCMPEQD: return "X86ISD::PCMPEQD";
8832 case X86ISD::PCMPEQQ: return "X86ISD::PCMPEQQ";
8833 case X86ISD::PCMPGTB: return "X86ISD::PCMPGTB";
8834 case X86ISD::PCMPGTW: return "X86ISD::PCMPGTW";
8835 case X86ISD::PCMPGTD: return "X86ISD::PCMPGTD";
8836 case X86ISD::PCMPGTQ: return "X86ISD::PCMPGTQ";
8837 case X86ISD::ADD: return "X86ISD::ADD";
8838 case X86ISD::SUB: return "X86ISD::SUB";
8839 case X86ISD::SMUL: return "X86ISD::SMUL";
8840 case X86ISD::UMUL: return "X86ISD::UMUL";
8841 case X86ISD::INC: return "X86ISD::INC";
8842 case X86ISD::DEC: return "X86ISD::DEC";
8843 case X86ISD::OR: return "X86ISD::OR";
8844 case X86ISD::XOR: return "X86ISD::XOR";
8845 case X86ISD::AND: return "X86ISD::AND";
8846 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
8847 case X86ISD::PTEST: return "X86ISD::PTEST";
8848 case X86ISD::TESTP: return "X86ISD::TESTP";
8849 case X86ISD::PALIGN: return "X86ISD::PALIGN";
8850 case X86ISD::PSHUFD: return "X86ISD::PSHUFD";
8851 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW";
8852 case X86ISD::PSHUFHW_LD: return "X86ISD::PSHUFHW_LD";
8853 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW";
8854 case X86ISD::PSHUFLW_LD: return "X86ISD::PSHUFLW_LD";
8855 case X86ISD::SHUFPS: return "X86ISD::SHUFPS";
8856 case X86ISD::SHUFPD: return "X86ISD::SHUFPD";
8857 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS";
8858 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD";
8859 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS";
8860 case X86ISD::MOVHLPD: return "X86ISD::MOVHLPD";
8861 case X86ISD::MOVLPS: return "X86ISD::MOVLPS";
8862 case X86ISD::MOVLPD: return "X86ISD::MOVLPD";
8863 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP";
8864 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP";
8865 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP";
8866 case X86ISD::MOVSHDUP_LD: return "X86ISD::MOVSHDUP_LD";
8867 case X86ISD::MOVSLDUP_LD: return "X86ISD::MOVSLDUP_LD";
8868 case X86ISD::MOVSD: return "X86ISD::MOVSD";
8869 case X86ISD::MOVSS: return "X86ISD::MOVSS";
8870 case X86ISD::UNPCKLPS: return "X86ISD::UNPCKLPS";
8871 case X86ISD::UNPCKLPD: return "X86ISD::UNPCKLPD";
8872 case X86ISD::UNPCKHPS: return "X86ISD::UNPCKHPS";
8873 case X86ISD::UNPCKHPD: return "X86ISD::UNPCKHPD";
8874 case X86ISD::PUNPCKLBW: return "X86ISD::PUNPCKLBW";
8875 case X86ISD::PUNPCKLWD: return "X86ISD::PUNPCKLWD";
8876 case X86ISD::PUNPCKLDQ: return "X86ISD::PUNPCKLDQ";
8877 case X86ISD::PUNPCKLQDQ: return "X86ISD::PUNPCKLQDQ";
8878 case X86ISD::PUNPCKHBW: return "X86ISD::PUNPCKHBW";
8879 case X86ISD::PUNPCKHWD: return "X86ISD::PUNPCKHWD";
8880 case X86ISD::PUNPCKHDQ: return "X86ISD::PUNPCKHDQ";
8881 case X86ISD::PUNPCKHQDQ: return "X86ISD::PUNPCKHQDQ";
8882 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
8883 case X86ISD::VAARG_64: return "X86ISD::VAARG_64";
8884 case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA";
8888 // isLegalAddressingMode - Return true if the addressing mode represented
8889 // by AM is legal for this target, for a load/store of the specified type.
8890 bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
8891 const Type *Ty) const {
8892 // X86 supports extremely general addressing modes.
8893 CodeModel::Model M = getTargetMachine().getCodeModel();
8894 Reloc::Model R = getTargetMachine().getRelocationModel();
8896 // X86 allows a sign-extended 32-bit immediate field as a displacement.
8897 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != NULL))
8902 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
8904 // If a reference to this global requires an extra load, we can't fold it.
8905 if (isGlobalStubReference(GVFlags))
8908 // If BaseGV requires a register for the PIC base, we cannot also have a
8909 // BaseReg specified.
8910 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
8913 // If lower 4G is not available, then we must use rip-relative addressing.
8914 if ((M != CodeModel::Small || R != Reloc::Static) &&
8915 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
8925 // These scales always work.
8930 // These scales are formed with basereg+scalereg. Only accept if there is
8935 default: // Other stuff never works.
8943 bool X86TargetLowering::isTruncateFree(const Type *Ty1, const Type *Ty2) const {
8944 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
8946 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
8947 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
8948 if (NumBits1 <= NumBits2)
8953 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
8954 if (!VT1.isInteger() || !VT2.isInteger())
8956 unsigned NumBits1 = VT1.getSizeInBits();
8957 unsigned NumBits2 = VT2.getSizeInBits();
8958 if (NumBits1 <= NumBits2)
8963 bool X86TargetLowering::isZExtFree(const Type *Ty1, const Type *Ty2) const {
8964 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
8965 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit();
8968 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
8969 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
8970 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
8973 bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
8974 // i16 instructions are longer (0x66 prefix) and potentially slower.
8975 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
8978 /// isShuffleMaskLegal - Targets can use this to indicate that they only
8979 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
8980 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
8981 /// are assumed to be legal.
8983 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
8985 // Very little shuffling can be done for 64-bit vectors right now.
8986 if (VT.getSizeInBits() == 64)
8987 return isPALIGNRMask(M, VT, Subtarget->hasSSSE3());
8989 // FIXME: pshufb, blends, shifts.
8990 return (VT.getVectorNumElements() == 2 ||
8991 ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
8992 isMOVLMask(M, VT) ||
8993 isSHUFPMask(M, VT) ||
8994 isPSHUFDMask(M, VT) ||
8995 isPSHUFHWMask(M, VT) ||
8996 isPSHUFLWMask(M, VT) ||
8997 isPALIGNRMask(M, VT, Subtarget->hasSSSE3()) ||
8998 isUNPCKLMask(M, VT) ||
8999 isUNPCKHMask(M, VT) ||
9000 isUNPCKL_v_undef_Mask(M, VT) ||
9001 isUNPCKH_v_undef_Mask(M, VT));
9005 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
9007 unsigned NumElts = VT.getVectorNumElements();
9008 // FIXME: This collection of masks seems suspect.
9011 if (NumElts == 4 && VT.getSizeInBits() == 128) {
9012 return (isMOVLMask(Mask, VT) ||
9013 isCommutedMOVLMask(Mask, VT, true) ||
9014 isSHUFPMask(Mask, VT) ||
9015 isCommutedSHUFPMask(Mask, VT));
9020 //===----------------------------------------------------------------------===//
9021 // X86 Scheduler Hooks
9022 //===----------------------------------------------------------------------===//
9024 // private utility function
9026 X86TargetLowering::EmitAtomicBitwiseWithCustomInserter(MachineInstr *bInstr,
9027 MachineBasicBlock *MBB,
9034 TargetRegisterClass *RC,
9035 bool invSrc) const {
9036 // For the atomic bitwise operator, we generate
9039 // ld t1 = [bitinstr.addr]
9040 // op t2 = t1, [bitinstr.val]
9042 // lcs dest = [bitinstr.addr], t2 [EAX is implicit]
9044 // fallthrough -->nextMBB
9045 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
9046 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
9047 MachineFunction::iterator MBBIter = MBB;
9050 /// First build the CFG
9051 MachineFunction *F = MBB->getParent();
9052 MachineBasicBlock *thisMBB = MBB;
9053 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
9054 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
9055 F->insert(MBBIter, newMBB);
9056 F->insert(MBBIter, nextMBB);
9058 // Transfer the remainder of thisMBB and its successor edges to nextMBB.
9059 nextMBB->splice(nextMBB->begin(), thisMBB,
9060 llvm::next(MachineBasicBlock::iterator(bInstr)),
9062 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
9064 // Update thisMBB to fall through to newMBB
9065 thisMBB->addSuccessor(newMBB);
9067 // newMBB jumps to itself and fall through to nextMBB
9068 newMBB->addSuccessor(nextMBB);
9069 newMBB->addSuccessor(newMBB);
9071 // Insert instructions into newMBB based on incoming instruction
9072 assert(bInstr->getNumOperands() < X86::AddrNumOperands + 4 &&
9073 "unexpected number of operands");
9074 DebugLoc dl = bInstr->getDebugLoc();
9075 MachineOperand& destOper = bInstr->getOperand(0);
9076 MachineOperand* argOpers[2 + X86::AddrNumOperands];
9077 int numArgs = bInstr->getNumOperands() - 1;
9078 for (int i=0; i < numArgs; ++i)
9079 argOpers[i] = &bInstr->getOperand(i+1);
9081 // x86 address has 4 operands: base, index, scale, and displacement
9082 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3]
9083 int valArgIndx = lastAddrIndx + 1;
9085 unsigned t1 = F->getRegInfo().createVirtualRegister(RC);
9086 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(LoadOpc), t1);
9087 for (int i=0; i <= lastAddrIndx; ++i)
9088 (*MIB).addOperand(*argOpers[i]);
9090 unsigned tt = F->getRegInfo().createVirtualRegister(RC);
9092 MIB = BuildMI(newMBB, dl, TII->get(notOpc), tt).addReg(t1);
9097 unsigned t2 = F->getRegInfo().createVirtualRegister(RC);
9098 assert((argOpers[valArgIndx]->isReg() ||
9099 argOpers[valArgIndx]->isImm()) &&
9101 if (argOpers[valArgIndx]->isReg())
9102 MIB = BuildMI(newMBB, dl, TII->get(regOpc), t2);
9104 MIB = BuildMI(newMBB, dl, TII->get(immOpc), t2);
9106 (*MIB).addOperand(*argOpers[valArgIndx]);
9108 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), EAXreg);
9111 MIB = BuildMI(newMBB, dl, TII->get(CXchgOpc));
9112 for (int i=0; i <= lastAddrIndx; ++i)
9113 (*MIB).addOperand(*argOpers[i]);
9115 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand");
9116 (*MIB).setMemRefs(bInstr->memoperands_begin(),
9117 bInstr->memoperands_end());
9119 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), destOper.getReg());
9123 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB);
9125 bInstr->eraseFromParent(); // The pseudo instruction is gone now.
9129 // private utility function: 64 bit atomics on 32 bit host.
9131 X86TargetLowering::EmitAtomicBit6432WithCustomInserter(MachineInstr *bInstr,
9132 MachineBasicBlock *MBB,
9137 bool invSrc) const {
9138 // For the atomic bitwise operator, we generate
9139 // thisMBB (instructions are in pairs, except cmpxchg8b)
9140 // ld t1,t2 = [bitinstr.addr]
9142 // out1, out2 = phi (thisMBB, t1/t2) (newMBB, t3/t4)
9143 // op t5, t6 <- out1, out2, [bitinstr.val]
9144 // (for SWAP, substitute: mov t5, t6 <- [bitinstr.val])
9145 // mov ECX, EBX <- t5, t6
9146 // mov EAX, EDX <- t1, t2
9147 // cmpxchg8b [bitinstr.addr] [EAX, EDX, EBX, ECX implicit]
9148 // mov t3, t4 <- EAX, EDX
9150 // result in out1, out2
9151 // fallthrough -->nextMBB
9153 const TargetRegisterClass *RC = X86::GR32RegisterClass;
9154 const unsigned LoadOpc = X86::MOV32rm;
9155 const unsigned NotOpc = X86::NOT32r;
9156 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
9157 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
9158 MachineFunction::iterator MBBIter = MBB;
9161 /// First build the CFG
9162 MachineFunction *F = MBB->getParent();
9163 MachineBasicBlock *thisMBB = MBB;
9164 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
9165 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
9166 F->insert(MBBIter, newMBB);
9167 F->insert(MBBIter, nextMBB);
9169 // Transfer the remainder of thisMBB and its successor edges to nextMBB.
9170 nextMBB->splice(nextMBB->begin(), thisMBB,
9171 llvm::next(MachineBasicBlock::iterator(bInstr)),
9173 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
9175 // Update thisMBB to fall through to newMBB
9176 thisMBB->addSuccessor(newMBB);
9178 // newMBB jumps to itself and fall through to nextMBB
9179 newMBB->addSuccessor(nextMBB);
9180 newMBB->addSuccessor(newMBB);
9182 DebugLoc dl = bInstr->getDebugLoc();
9183 // Insert instructions into newMBB based on incoming instruction
9184 // There are 8 "real" operands plus 9 implicit def/uses, ignored here.
9185 assert(bInstr->getNumOperands() < X86::AddrNumOperands + 14 &&
9186 "unexpected number of operands");
9187 MachineOperand& dest1Oper = bInstr->getOperand(0);
9188 MachineOperand& dest2Oper = bInstr->getOperand(1);
9189 MachineOperand* argOpers[2 + X86::AddrNumOperands];
9190 for (int i=0; i < 2 + X86::AddrNumOperands; ++i) {
9191 argOpers[i] = &bInstr->getOperand(i+2);
9193 // We use some of the operands multiple times, so conservatively just
9194 // clear any kill flags that might be present.
9195 if (argOpers[i]->isReg() && argOpers[i]->isUse())
9196 argOpers[i]->setIsKill(false);
9199 // x86 address has 5 operands: base, index, scale, displacement, and segment.
9200 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3]
9202 unsigned t1 = F->getRegInfo().createVirtualRegister(RC);
9203 MachineInstrBuilder MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t1);
9204 for (int i=0; i <= lastAddrIndx; ++i)
9205 (*MIB).addOperand(*argOpers[i]);
9206 unsigned t2 = F->getRegInfo().createVirtualRegister(RC);
9207 MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t2);
9208 // add 4 to displacement.
9209 for (int i=0; i <= lastAddrIndx-2; ++i)
9210 (*MIB).addOperand(*argOpers[i]);
9211 MachineOperand newOp3 = *(argOpers[3]);
9213 newOp3.setImm(newOp3.getImm()+4);
9215 newOp3.setOffset(newOp3.getOffset()+4);
9216 (*MIB).addOperand(newOp3);
9217 (*MIB).addOperand(*argOpers[lastAddrIndx]);
9219 // t3/4 are defined later, at the bottom of the loop
9220 unsigned t3 = F->getRegInfo().createVirtualRegister(RC);
9221 unsigned t4 = F->getRegInfo().createVirtualRegister(RC);
9222 BuildMI(newMBB, dl, TII->get(X86::PHI), dest1Oper.getReg())
9223 .addReg(t1).addMBB(thisMBB).addReg(t3).addMBB(newMBB);
9224 BuildMI(newMBB, dl, TII->get(X86::PHI), dest2Oper.getReg())
9225 .addReg(t2).addMBB(thisMBB).addReg(t4).addMBB(newMBB);
9227 // The subsequent operations should be using the destination registers of
9228 //the PHI instructions.
9230 t1 = F->getRegInfo().createVirtualRegister(RC);
9231 t2 = F->getRegInfo().createVirtualRegister(RC);
9232 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), t1).addReg(dest1Oper.getReg());
9233 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), t2).addReg(dest2Oper.getReg());
9235 t1 = dest1Oper.getReg();
9236 t2 = dest2Oper.getReg();
9239 int valArgIndx = lastAddrIndx + 1;
9240 assert((argOpers[valArgIndx]->isReg() ||
9241 argOpers[valArgIndx]->isImm()) &&
9243 unsigned t5 = F->getRegInfo().createVirtualRegister(RC);
9244 unsigned t6 = F->getRegInfo().createVirtualRegister(RC);
9245 if (argOpers[valArgIndx]->isReg())
9246 MIB = BuildMI(newMBB, dl, TII->get(regOpcL), t5);
9248 MIB = BuildMI(newMBB, dl, TII->get(immOpcL), t5);
9249 if (regOpcL != X86::MOV32rr)
9251 (*MIB).addOperand(*argOpers[valArgIndx]);
9252 assert(argOpers[valArgIndx + 1]->isReg() ==
9253 argOpers[valArgIndx]->isReg());
9254 assert(argOpers[valArgIndx + 1]->isImm() ==
9255 argOpers[valArgIndx]->isImm());
9256 if (argOpers[valArgIndx + 1]->isReg())
9257 MIB = BuildMI(newMBB, dl, TII->get(regOpcH), t6);
9259 MIB = BuildMI(newMBB, dl, TII->get(immOpcH), t6);
9260 if (regOpcH != X86::MOV32rr)
9262 (*MIB).addOperand(*argOpers[valArgIndx + 1]);
9264 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EAX);
9266 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EDX);
9269 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EBX);
9271 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::ECX);
9274 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG8B));
9275 for (int i=0; i <= lastAddrIndx; ++i)
9276 (*MIB).addOperand(*argOpers[i]);
9278 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand");
9279 (*MIB).setMemRefs(bInstr->memoperands_begin(),
9280 bInstr->memoperands_end());
9282 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t3);
9283 MIB.addReg(X86::EAX);
9284 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t4);
9285 MIB.addReg(X86::EDX);
9288 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB);
9290 bInstr->eraseFromParent(); // The pseudo instruction is gone now.
9294 // private utility function
9296 X86TargetLowering::EmitAtomicMinMaxWithCustomInserter(MachineInstr *mInstr,
9297 MachineBasicBlock *MBB,
9298 unsigned cmovOpc) const {
9299 // For the atomic min/max operator, we generate
9302 // ld t1 = [min/max.addr]
9303 // mov t2 = [min/max.val]
9305 // cmov[cond] t2 = t1
9307 // lcs dest = [bitinstr.addr], t2 [EAX is implicit]
9309 // fallthrough -->nextMBB
9311 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
9312 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
9313 MachineFunction::iterator MBBIter = MBB;
9316 /// First build the CFG
9317 MachineFunction *F = MBB->getParent();
9318 MachineBasicBlock *thisMBB = MBB;
9319 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
9320 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
9321 F->insert(MBBIter, newMBB);
9322 F->insert(MBBIter, nextMBB);
9324 // Transfer the remainder of thisMBB and its successor edges to nextMBB.
9325 nextMBB->splice(nextMBB->begin(), thisMBB,
9326 llvm::next(MachineBasicBlock::iterator(mInstr)),
9328 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
9330 // Update thisMBB to fall through to newMBB
9331 thisMBB->addSuccessor(newMBB);
9333 // newMBB jumps to newMBB and fall through to nextMBB
9334 newMBB->addSuccessor(nextMBB);
9335 newMBB->addSuccessor(newMBB);
9337 DebugLoc dl = mInstr->getDebugLoc();
9338 // Insert instructions into newMBB based on incoming instruction
9339 assert(mInstr->getNumOperands() < X86::AddrNumOperands + 4 &&
9340 "unexpected number of operands");
9341 MachineOperand& destOper = mInstr->getOperand(0);
9342 MachineOperand* argOpers[2 + X86::AddrNumOperands];
9343 int numArgs = mInstr->getNumOperands() - 1;
9344 for (int i=0; i < numArgs; ++i)
9345 argOpers[i] = &mInstr->getOperand(i+1);
9347 // x86 address has 4 operands: base, index, scale, and displacement
9348 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3]
9349 int valArgIndx = lastAddrIndx + 1;
9351 unsigned t1 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
9352 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rm), t1);
9353 for (int i=0; i <= lastAddrIndx; ++i)
9354 (*MIB).addOperand(*argOpers[i]);
9356 // We only support register and immediate values
9357 assert((argOpers[valArgIndx]->isReg() ||
9358 argOpers[valArgIndx]->isImm()) &&
9361 unsigned t2 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
9362 if (argOpers[valArgIndx]->isReg())
9363 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t2);
9365 MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), t2);
9366 (*MIB).addOperand(*argOpers[valArgIndx]);
9368 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EAX);
9371 MIB = BuildMI(newMBB, dl, TII->get(X86::CMP32rr));
9376 unsigned t3 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
9377 MIB = BuildMI(newMBB, dl, TII->get(cmovOpc),t3);
9381 // Cmp and exchange if none has modified the memory location
9382 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG32));
9383 for (int i=0; i <= lastAddrIndx; ++i)
9384 (*MIB).addOperand(*argOpers[i]);
9386 assert(mInstr->hasOneMemOperand() && "Unexpected number of memoperand");
9387 (*MIB).setMemRefs(mInstr->memoperands_begin(),
9388 mInstr->memoperands_end());
9390 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), destOper.getReg());
9391 MIB.addReg(X86::EAX);
9394 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB);
9396 mInstr->eraseFromParent(); // The pseudo instruction is gone now.
9400 // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
9401 // or XMM0_V32I8 in AVX all of this code can be replaced with that
9404 X86TargetLowering::EmitPCMP(MachineInstr *MI, MachineBasicBlock *BB,
9405 unsigned numArgs, bool memArg) const {
9407 assert((Subtarget->hasSSE42() || Subtarget->hasAVX()) &&
9408 "Target must have SSE4.2 or AVX features enabled");
9410 DebugLoc dl = MI->getDebugLoc();
9411 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
9415 if (!Subtarget->hasAVX()) {
9417 Opc = numArgs == 3 ? X86::PCMPISTRM128rm : X86::PCMPESTRM128rm;
9419 Opc = numArgs == 3 ? X86::PCMPISTRM128rr : X86::PCMPESTRM128rr;
9422 Opc = numArgs == 3 ? X86::VPCMPISTRM128rm : X86::VPCMPESTRM128rm;
9424 Opc = numArgs == 3 ? X86::VPCMPISTRM128rr : X86::VPCMPESTRM128rr;
9427 MachineInstrBuilder MIB = BuildMI(BB, dl, TII->get(Opc));
9429 for (unsigned i = 0; i < numArgs; ++i) {
9430 MachineOperand &Op = MI->getOperand(i+1);
9432 if (!(Op.isReg() && Op.isImplicit()))
9436 BuildMI(BB, dl, TII->get(X86::MOVAPSrr), MI->getOperand(0).getReg())
9439 MI->eraseFromParent();
9445 X86TargetLowering::EmitVAARG64WithCustomInserter(
9447 MachineBasicBlock *MBB) const {
9448 // Emit va_arg instruction on X86-64.
9450 // Operands to this pseudo-instruction:
9451 // 0 ) Output : destination address (reg)
9452 // 1-5) Input : va_list address (addr, i64mem)
9453 // 6 ) ArgSize : Size (in bytes) of vararg type
9454 // 7 ) ArgMode : 0=overflow only, 1=use gp_offset, 2=use fp_offset
9455 // 8 ) Align : Alignment of type
9456 // 9 ) EFLAGS (implicit-def)
9458 assert(MI->getNumOperands() == 10 && "VAARG_64 should have 10 operands!");
9459 assert(X86::AddrNumOperands == 5 && "VAARG_64 assumes 5 address operands");
9461 unsigned DestReg = MI->getOperand(0).getReg();
9462 MachineOperand &Base = MI->getOperand(1);
9463 MachineOperand &Scale = MI->getOperand(2);
9464 MachineOperand &Index = MI->getOperand(3);
9465 MachineOperand &Disp = MI->getOperand(4);
9466 MachineOperand &Segment = MI->getOperand(5);
9467 unsigned ArgSize = MI->getOperand(6).getImm();
9468 unsigned ArgMode = MI->getOperand(7).getImm();
9469 unsigned Align = MI->getOperand(8).getImm();
9472 assert(MI->hasOneMemOperand() && "Expected VAARG_64 to have one memoperand");
9473 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
9474 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
9476 // Machine Information
9477 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
9478 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
9479 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64);
9480 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32);
9481 DebugLoc DL = MI->getDebugLoc();
9486 // i64 overflow_area (address)
9487 // i64 reg_save_area (address)
9489 // sizeof(va_list) = 24
9490 // alignment(va_list) = 8
9492 unsigned TotalNumIntRegs = 6;
9493 unsigned TotalNumXMMRegs = 8;
9494 bool UseGPOffset = (ArgMode == 1);
9495 bool UseFPOffset = (ArgMode == 2);
9496 unsigned MaxOffset = TotalNumIntRegs * 8 +
9497 (UseFPOffset ? TotalNumXMMRegs * 16 : 0);
9499 /* Align ArgSize to a multiple of 8 */
9500 unsigned ArgSizeA8 = (ArgSize + 7) & ~7;
9501 bool NeedsAlign = (Align > 8);
9503 MachineBasicBlock *thisMBB = MBB;
9504 MachineBasicBlock *overflowMBB;
9505 MachineBasicBlock *offsetMBB;
9506 MachineBasicBlock *endMBB;
9508 unsigned OffsetDestReg = 0; // Argument address computed by offsetMBB
9509 unsigned OverflowDestReg = 0; // Argument address computed by overflowMBB
9510 unsigned OffsetReg = 0;
9512 if (!UseGPOffset && !UseFPOffset) {
9513 // If we only pull from the overflow region, we don't create a branch.
9514 // We don't need to alter control flow.
9515 OffsetDestReg = 0; // unused
9516 OverflowDestReg = DestReg;
9519 overflowMBB = thisMBB;
9522 // First emit code to check if gp_offset (or fp_offset) is below the bound.
9523 // If so, pull the argument from reg_save_area. (branch to offsetMBB)
9524 // If not, pull from overflow_area. (branch to overflowMBB)
9529 // offsetMBB overflowMBB
9534 // Registers for the PHI in endMBB
9535 OffsetDestReg = MRI.createVirtualRegister(AddrRegClass);
9536 OverflowDestReg = MRI.createVirtualRegister(AddrRegClass);
9538 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
9539 MachineFunction *MF = MBB->getParent();
9540 overflowMBB = MF->CreateMachineBasicBlock(LLVM_BB);
9541 offsetMBB = MF->CreateMachineBasicBlock(LLVM_BB);
9542 endMBB = MF->CreateMachineBasicBlock(LLVM_BB);
9544 MachineFunction::iterator MBBIter = MBB;
9547 // Insert the new basic blocks
9548 MF->insert(MBBIter, offsetMBB);
9549 MF->insert(MBBIter, overflowMBB);
9550 MF->insert(MBBIter, endMBB);
9552 // Transfer the remainder of MBB and its successor edges to endMBB.
9553 endMBB->splice(endMBB->begin(), thisMBB,
9554 llvm::next(MachineBasicBlock::iterator(MI)),
9556 endMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
9558 // Make offsetMBB and overflowMBB successors of thisMBB
9559 thisMBB->addSuccessor(offsetMBB);
9560 thisMBB->addSuccessor(overflowMBB);
9562 // endMBB is a successor of both offsetMBB and overflowMBB
9563 offsetMBB->addSuccessor(endMBB);
9564 overflowMBB->addSuccessor(endMBB);
9566 // Load the offset value into a register
9567 OffsetReg = MRI.createVirtualRegister(OffsetRegClass);
9568 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg)
9572 .addDisp(Disp, UseFPOffset ? 4 : 0)
9573 .addOperand(Segment)
9574 .setMemRefs(MMOBegin, MMOEnd);
9576 // Check if there is enough room left to pull this argument.
9577 BuildMI(thisMBB, DL, TII->get(X86::CMP32ri))
9579 .addImm(MaxOffset + 8 - ArgSizeA8);
9581 // Branch to "overflowMBB" if offset >= max
9582 // Fall through to "offsetMBB" otherwise
9583 BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE)))
9584 .addMBB(overflowMBB);
9587 // In offsetMBB, emit code to use the reg_save_area.
9589 assert(OffsetReg != 0);
9591 // Read the reg_save_area address.
9592 unsigned RegSaveReg = MRI.createVirtualRegister(AddrRegClass);
9593 BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg)
9598 .addOperand(Segment)
9599 .setMemRefs(MMOBegin, MMOEnd);
9601 // Zero-extend the offset
9602 unsigned OffsetReg64 = MRI.createVirtualRegister(AddrRegClass);
9603 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64)
9606 .addImm(X86::sub_32bit);
9608 // Add the offset to the reg_save_area to get the final address.
9609 BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg)
9610 .addReg(OffsetReg64)
9611 .addReg(RegSaveReg);
9613 // Compute the offset for the next argument
9614 unsigned NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass);
9615 BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg)
9617 .addImm(UseFPOffset ? 16 : 8);
9619 // Store it back into the va_list.
9620 BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr))
9624 .addDisp(Disp, UseFPOffset ? 4 : 0)
9625 .addOperand(Segment)
9626 .addReg(NextOffsetReg)
9627 .setMemRefs(MMOBegin, MMOEnd);
9630 BuildMI(offsetMBB, DL, TII->get(X86::JMP_4))
9635 // Emit code to use overflow area
9638 // Load the overflow_area address into a register.
9639 unsigned OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass);
9640 BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg)
9645 .addOperand(Segment)
9646 .setMemRefs(MMOBegin, MMOEnd);
9648 // If we need to align it, do so. Otherwise, just copy the address
9649 // to OverflowDestReg.
9651 // Align the overflow address
9652 assert((Align & (Align-1)) == 0 && "Alignment must be a power of 2");
9653 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass);
9655 // aligned_addr = (addr + (align-1)) & ~(align-1)
9656 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg)
9657 .addReg(OverflowAddrReg)
9660 BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg)
9662 .addImm(~(uint64_t)(Align-1));
9664 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg)
9665 .addReg(OverflowAddrReg);
9668 // Compute the next overflow address after this argument.
9669 // (the overflow address should be kept 8-byte aligned)
9670 unsigned NextAddrReg = MRI.createVirtualRegister(AddrRegClass);
9671 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg)
9672 .addReg(OverflowDestReg)
9675 // Store the new overflow address.
9676 BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr))
9681 .addOperand(Segment)
9682 .addReg(NextAddrReg)
9683 .setMemRefs(MMOBegin, MMOEnd);
9685 // If we branched, emit the PHI to the front of endMBB.
9687 BuildMI(*endMBB, endMBB->begin(), DL,
9688 TII->get(X86::PHI), DestReg)
9689 .addReg(OffsetDestReg).addMBB(offsetMBB)
9690 .addReg(OverflowDestReg).addMBB(overflowMBB);
9693 // Erase the pseudo instruction
9694 MI->eraseFromParent();
9700 X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
9702 MachineBasicBlock *MBB) const {
9703 // Emit code to save XMM registers to the stack. The ABI says that the
9704 // number of registers to save is given in %al, so it's theoretically
9705 // possible to do an indirect jump trick to avoid saving all of them,
9706 // however this code takes a simpler approach and just executes all
9707 // of the stores if %al is non-zero. It's less code, and it's probably
9708 // easier on the hardware branch predictor, and stores aren't all that
9709 // expensive anyway.
9711 // Create the new basic blocks. One block contains all the XMM stores,
9712 // and one block is the final destination regardless of whether any
9713 // stores were performed.
9714 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
9715 MachineFunction *F = MBB->getParent();
9716 MachineFunction::iterator MBBIter = MBB;
9718 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB);
9719 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB);
9720 F->insert(MBBIter, XMMSaveMBB);
9721 F->insert(MBBIter, EndMBB);
9723 // Transfer the remainder of MBB and its successor edges to EndMBB.
9724 EndMBB->splice(EndMBB->begin(), MBB,
9725 llvm::next(MachineBasicBlock::iterator(MI)),
9727 EndMBB->transferSuccessorsAndUpdatePHIs(MBB);
9729 // The original block will now fall through to the XMM save block.
9730 MBB->addSuccessor(XMMSaveMBB);
9731 // The XMMSaveMBB will fall through to the end block.
9732 XMMSaveMBB->addSuccessor(EndMBB);
9734 // Now add the instructions.
9735 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
9736 DebugLoc DL = MI->getDebugLoc();
9738 unsigned CountReg = MI->getOperand(0).getReg();
9739 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm();
9740 int64_t VarArgsFPOffset = MI->getOperand(2).getImm();
9742 if (!Subtarget->isTargetWin64()) {
9743 // If %al is 0, branch around the XMM save block.
9744 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
9745 BuildMI(MBB, DL, TII->get(X86::JE_4)).addMBB(EndMBB);
9746 MBB->addSuccessor(EndMBB);
9749 // In the XMM save block, save all the XMM argument registers.
9750 for (int i = 3, e = MI->getNumOperands(); i != e; ++i) {
9751 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
9752 MachineMemOperand *MMO =
9753 F->getMachineMemOperand(
9754 MachinePointerInfo::getFixedStack(RegSaveFrameIndex, Offset),
9755 MachineMemOperand::MOStore,
9756 /*Size=*/16, /*Align=*/16);
9757 BuildMI(XMMSaveMBB, DL, TII->get(X86::MOVAPSmr))
9758 .addFrameIndex(RegSaveFrameIndex)
9759 .addImm(/*Scale=*/1)
9760 .addReg(/*IndexReg=*/0)
9761 .addImm(/*Disp=*/Offset)
9762 .addReg(/*Segment=*/0)
9763 .addReg(MI->getOperand(i).getReg())
9764 .addMemOperand(MMO);
9767 MI->eraseFromParent(); // The pseudo instruction is gone now.
9773 X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
9774 MachineBasicBlock *BB) const {
9775 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
9776 DebugLoc DL = MI->getDebugLoc();
9778 // To "insert" a SELECT_CC instruction, we actually have to insert the
9779 // diamond control-flow pattern. The incoming instruction knows the
9780 // destination vreg to set, the condition code register to branch on, the
9781 // true/false values to select between, and a branch opcode to use.
9782 const BasicBlock *LLVM_BB = BB->getBasicBlock();
9783 MachineFunction::iterator It = BB;
9789 // cmpTY ccX, r1, r2
9791 // fallthrough --> copy0MBB
9792 MachineBasicBlock *thisMBB = BB;
9793 MachineFunction *F = BB->getParent();
9794 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
9795 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
9796 F->insert(It, copy0MBB);
9797 F->insert(It, sinkMBB);
9799 // If the EFLAGS register isn't dead in the terminator, then claim that it's
9800 // live into the sink and copy blocks.
9801 const MachineFunction *MF = BB->getParent();
9802 const TargetRegisterInfo *TRI = MF->getTarget().getRegisterInfo();
9803 BitVector ReservedRegs = TRI->getReservedRegs(*MF);
9805 for (unsigned I = 0, E = MI->getNumOperands(); I != E; ++I) {
9806 const MachineOperand &MO = MI->getOperand(I);
9807 if (!MO.isReg() || !MO.isUse() || MO.isKill()) continue;
9808 unsigned Reg = MO.getReg();
9809 if (Reg != X86::EFLAGS) continue;
9810 copy0MBB->addLiveIn(Reg);
9811 sinkMBB->addLiveIn(Reg);
9814 // Transfer the remainder of BB and its successor edges to sinkMBB.
9815 sinkMBB->splice(sinkMBB->begin(), BB,
9816 llvm::next(MachineBasicBlock::iterator(MI)),
9818 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
9820 // Add the true and fallthrough blocks as its successors.
9821 BB->addSuccessor(copy0MBB);
9822 BB->addSuccessor(sinkMBB);
9824 // Create the conditional branch instruction.
9826 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
9827 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
9830 // %FalseValue = ...
9831 // # fallthrough to sinkMBB
9832 copy0MBB->addSuccessor(sinkMBB);
9835 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
9837 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
9838 TII->get(X86::PHI), MI->getOperand(0).getReg())
9839 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
9840 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
9842 MI->eraseFromParent(); // The pseudo instruction is gone now.
9847 X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI,
9848 MachineBasicBlock *BB) const {
9849 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
9850 DebugLoc DL = MI->getDebugLoc();
9852 // The lowering is pretty easy: we're just emitting the call to _alloca. The
9853 // non-trivial part is impdef of ESP.
9854 // FIXME: The code should be tweaked as soon as we'll try to do codegen for
9857 const char *StackProbeSymbol =
9858 Subtarget->isTargetWindows() ? "_chkstk" : "_alloca";
9860 BuildMI(*BB, MI, DL, TII->get(X86::CALLpcrel32))
9861 .addExternalSymbol(StackProbeSymbol)
9862 .addReg(X86::EAX, RegState::Implicit)
9863 .addReg(X86::ESP, RegState::Implicit)
9864 .addReg(X86::EAX, RegState::Define | RegState::Implicit)
9865 .addReg(X86::ESP, RegState::Define | RegState::Implicit)
9866 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
9868 MI->eraseFromParent(); // The pseudo instruction is gone now.
9873 X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI,
9874 MachineBasicBlock *BB) const {
9875 // This is pretty easy. We're taking the value that we received from
9876 // our load from the relocation, sticking it in either RDI (x86-64)
9877 // or EAX and doing an indirect call. The return value will then
9878 // be in the normal return register.
9879 const X86InstrInfo *TII
9880 = static_cast<const X86InstrInfo*>(getTargetMachine().getInstrInfo());
9881 DebugLoc DL = MI->getDebugLoc();
9882 MachineFunction *F = BB->getParent();
9884 assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?");
9885 assert(MI->getOperand(3).isGlobal() && "This should be a global");
9887 if (Subtarget->is64Bit()) {
9888 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
9889 TII->get(X86::MOV64rm), X86::RDI)
9891 .addImm(0).addReg(0)
9892 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
9893 MI->getOperand(3).getTargetFlags())
9895 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m));
9896 addDirectMem(MIB, X86::RDI);
9897 } else if (getTargetMachine().getRelocationModel() != Reloc::PIC_) {
9898 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
9899 TII->get(X86::MOV32rm), X86::EAX)
9901 .addImm(0).addReg(0)
9902 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
9903 MI->getOperand(3).getTargetFlags())
9905 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
9906 addDirectMem(MIB, X86::EAX);
9908 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
9909 TII->get(X86::MOV32rm), X86::EAX)
9910 .addReg(TII->getGlobalBaseReg(F))
9911 .addImm(0).addReg(0)
9912 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
9913 MI->getOperand(3).getTargetFlags())
9915 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
9916 addDirectMem(MIB, X86::EAX);
9919 MI->eraseFromParent(); // The pseudo instruction is gone now.
9924 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
9925 MachineBasicBlock *BB) const {
9926 switch (MI->getOpcode()) {
9927 default: assert(false && "Unexpected instr type to insert");
9928 case X86::WIN_ALLOCA:
9929 return EmitLoweredWinAlloca(MI, BB);
9930 case X86::TLSCall_32:
9931 case X86::TLSCall_64:
9932 return EmitLoweredTLSCall(MI, BB);
9934 case X86::CMOV_FR32:
9935 case X86::CMOV_FR64:
9936 case X86::CMOV_V4F32:
9937 case X86::CMOV_V2F64:
9938 case X86::CMOV_V2I64:
9939 case X86::CMOV_GR16:
9940 case X86::CMOV_GR32:
9941 case X86::CMOV_RFP32:
9942 case X86::CMOV_RFP64:
9943 case X86::CMOV_RFP80:
9944 return EmitLoweredSelect(MI, BB);
9946 case X86::FP32_TO_INT16_IN_MEM:
9947 case X86::FP32_TO_INT32_IN_MEM:
9948 case X86::FP32_TO_INT64_IN_MEM:
9949 case X86::FP64_TO_INT16_IN_MEM:
9950 case X86::FP64_TO_INT32_IN_MEM:
9951 case X86::FP64_TO_INT64_IN_MEM:
9952 case X86::FP80_TO_INT16_IN_MEM:
9953 case X86::FP80_TO_INT32_IN_MEM:
9954 case X86::FP80_TO_INT64_IN_MEM: {
9955 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
9956 DebugLoc DL = MI->getDebugLoc();
9958 // Change the floating point control register to use "round towards zero"
9959 // mode when truncating to an integer value.
9960 MachineFunction *F = BB->getParent();
9961 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false);
9962 addFrameReference(BuildMI(*BB, MI, DL,
9963 TII->get(X86::FNSTCW16m)), CWFrameIdx);
9965 // Load the old value of the high byte of the control word...
9967 F->getRegInfo().createVirtualRegister(X86::GR16RegisterClass);
9968 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW),
9971 // Set the high part to be round to zero...
9972 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
9975 // Reload the modified control word now...
9976 addFrameReference(BuildMI(*BB, MI, DL,
9977 TII->get(X86::FLDCW16m)), CWFrameIdx);
9979 // Restore the memory image of control word to original value
9980 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
9983 // Get the X86 opcode to use.
9985 switch (MI->getOpcode()) {
9986 default: llvm_unreachable("illegal opcode!");
9987 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
9988 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
9989 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
9990 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
9991 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
9992 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
9993 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
9994 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
9995 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
9999 MachineOperand &Op = MI->getOperand(0);
10001 AM.BaseType = X86AddressMode::RegBase;
10002 AM.Base.Reg = Op.getReg();
10004 AM.BaseType = X86AddressMode::FrameIndexBase;
10005 AM.Base.FrameIndex = Op.getIndex();
10007 Op = MI->getOperand(1);
10009 AM.Scale = Op.getImm();
10010 Op = MI->getOperand(2);
10012 AM.IndexReg = Op.getImm();
10013 Op = MI->getOperand(3);
10014 if (Op.isGlobal()) {
10015 AM.GV = Op.getGlobal();
10017 AM.Disp = Op.getImm();
10019 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM)
10020 .addReg(MI->getOperand(X86::AddrNumOperands).getReg());
10022 // Reload the original control word now.
10023 addFrameReference(BuildMI(*BB, MI, DL,
10024 TII->get(X86::FLDCW16m)), CWFrameIdx);
10026 MI->eraseFromParent(); // The pseudo instruction is gone now.
10029 // String/text processing lowering.
10030 case X86::PCMPISTRM128REG:
10031 case X86::VPCMPISTRM128REG:
10032 return EmitPCMP(MI, BB, 3, false /* in-mem */);
10033 case X86::PCMPISTRM128MEM:
10034 case X86::VPCMPISTRM128MEM:
10035 return EmitPCMP(MI, BB, 3, true /* in-mem */);
10036 case X86::PCMPESTRM128REG:
10037 case X86::VPCMPESTRM128REG:
10038 return EmitPCMP(MI, BB, 5, false /* in mem */);
10039 case X86::PCMPESTRM128MEM:
10040 case X86::VPCMPESTRM128MEM:
10041 return EmitPCMP(MI, BB, 5, true /* in mem */);
10043 // Atomic Lowering.
10044 case X86::ATOMAND32:
10045 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr,
10046 X86::AND32ri, X86::MOV32rm,
10048 X86::NOT32r, X86::EAX,
10049 X86::GR32RegisterClass);
10050 case X86::ATOMOR32:
10051 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR32rr,
10052 X86::OR32ri, X86::MOV32rm,
10054 X86::NOT32r, X86::EAX,
10055 X86::GR32RegisterClass);
10056 case X86::ATOMXOR32:
10057 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR32rr,
10058 X86::XOR32ri, X86::MOV32rm,
10060 X86::NOT32r, X86::EAX,
10061 X86::GR32RegisterClass);
10062 case X86::ATOMNAND32:
10063 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr,
10064 X86::AND32ri, X86::MOV32rm,
10066 X86::NOT32r, X86::EAX,
10067 X86::GR32RegisterClass, true);
10068 case X86::ATOMMIN32:
10069 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL32rr);
10070 case X86::ATOMMAX32:
10071 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG32rr);
10072 case X86::ATOMUMIN32:
10073 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB32rr);
10074 case X86::ATOMUMAX32:
10075 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA32rr);
10077 case X86::ATOMAND16:
10078 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr,
10079 X86::AND16ri, X86::MOV16rm,
10081 X86::NOT16r, X86::AX,
10082 X86::GR16RegisterClass);
10083 case X86::ATOMOR16:
10084 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR16rr,
10085 X86::OR16ri, X86::MOV16rm,
10087 X86::NOT16r, X86::AX,
10088 X86::GR16RegisterClass);
10089 case X86::ATOMXOR16:
10090 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR16rr,
10091 X86::XOR16ri, X86::MOV16rm,
10093 X86::NOT16r, X86::AX,
10094 X86::GR16RegisterClass);
10095 case X86::ATOMNAND16:
10096 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr,
10097 X86::AND16ri, X86::MOV16rm,
10099 X86::NOT16r, X86::AX,
10100 X86::GR16RegisterClass, true);
10101 case X86::ATOMMIN16:
10102 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL16rr);
10103 case X86::ATOMMAX16:
10104 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG16rr);
10105 case X86::ATOMUMIN16:
10106 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB16rr);
10107 case X86::ATOMUMAX16:
10108 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA16rr);
10110 case X86::ATOMAND8:
10111 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr,
10112 X86::AND8ri, X86::MOV8rm,
10114 X86::NOT8r, X86::AL,
10115 X86::GR8RegisterClass);
10117 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR8rr,
10118 X86::OR8ri, X86::MOV8rm,
10120 X86::NOT8r, X86::AL,
10121 X86::GR8RegisterClass);
10122 case X86::ATOMXOR8:
10123 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR8rr,
10124 X86::XOR8ri, X86::MOV8rm,
10126 X86::NOT8r, X86::AL,
10127 X86::GR8RegisterClass);
10128 case X86::ATOMNAND8:
10129 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr,
10130 X86::AND8ri, X86::MOV8rm,
10132 X86::NOT8r, X86::AL,
10133 X86::GR8RegisterClass, true);
10134 // FIXME: There are no CMOV8 instructions; MIN/MAX need some other way.
10135 // This group is for 64-bit host.
10136 case X86::ATOMAND64:
10137 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr,
10138 X86::AND64ri32, X86::MOV64rm,
10140 X86::NOT64r, X86::RAX,
10141 X86::GR64RegisterClass);
10142 case X86::ATOMOR64:
10143 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR64rr,
10144 X86::OR64ri32, X86::MOV64rm,
10146 X86::NOT64r, X86::RAX,
10147 X86::GR64RegisterClass);
10148 case X86::ATOMXOR64:
10149 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR64rr,
10150 X86::XOR64ri32, X86::MOV64rm,
10152 X86::NOT64r, X86::RAX,
10153 X86::GR64RegisterClass);
10154 case X86::ATOMNAND64:
10155 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr,
10156 X86::AND64ri32, X86::MOV64rm,
10158 X86::NOT64r, X86::RAX,
10159 X86::GR64RegisterClass, true);
10160 case X86::ATOMMIN64:
10161 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL64rr);
10162 case X86::ATOMMAX64:
10163 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG64rr);
10164 case X86::ATOMUMIN64:
10165 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB64rr);
10166 case X86::ATOMUMAX64:
10167 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA64rr);
10169 // This group does 64-bit operations on a 32-bit host.
10170 case X86::ATOMAND6432:
10171 return EmitAtomicBit6432WithCustomInserter(MI, BB,
10172 X86::AND32rr, X86::AND32rr,
10173 X86::AND32ri, X86::AND32ri,
10175 case X86::ATOMOR6432:
10176 return EmitAtomicBit6432WithCustomInserter(MI, BB,
10177 X86::OR32rr, X86::OR32rr,
10178 X86::OR32ri, X86::OR32ri,
10180 case X86::ATOMXOR6432:
10181 return EmitAtomicBit6432WithCustomInserter(MI, BB,
10182 X86::XOR32rr, X86::XOR32rr,
10183 X86::XOR32ri, X86::XOR32ri,
10185 case X86::ATOMNAND6432:
10186 return EmitAtomicBit6432WithCustomInserter(MI, BB,
10187 X86::AND32rr, X86::AND32rr,
10188 X86::AND32ri, X86::AND32ri,
10190 case X86::ATOMADD6432:
10191 return EmitAtomicBit6432WithCustomInserter(MI, BB,
10192 X86::ADD32rr, X86::ADC32rr,
10193 X86::ADD32ri, X86::ADC32ri,
10195 case X86::ATOMSUB6432:
10196 return EmitAtomicBit6432WithCustomInserter(MI, BB,
10197 X86::SUB32rr, X86::SBB32rr,
10198 X86::SUB32ri, X86::SBB32ri,
10200 case X86::ATOMSWAP6432:
10201 return EmitAtomicBit6432WithCustomInserter(MI, BB,
10202 X86::MOV32rr, X86::MOV32rr,
10203 X86::MOV32ri, X86::MOV32ri,
10205 case X86::VASTART_SAVE_XMM_REGS:
10206 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
10208 case X86::VAARG_64:
10209 return EmitVAARG64WithCustomInserter(MI, BB);
10213 //===----------------------------------------------------------------------===//
10214 // X86 Optimization Hooks
10215 //===----------------------------------------------------------------------===//
10217 void X86TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
10221 const SelectionDAG &DAG,
10222 unsigned Depth) const {
10223 unsigned Opc = Op.getOpcode();
10224 assert((Opc >= ISD::BUILTIN_OP_END ||
10225 Opc == ISD::INTRINSIC_WO_CHAIN ||
10226 Opc == ISD::INTRINSIC_W_CHAIN ||
10227 Opc == ISD::INTRINSIC_VOID) &&
10228 "Should use MaskedValueIsZero if you don't know whether Op"
10229 " is a target node!");
10231 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0); // Don't know anything.
10243 // These nodes' second result is a boolean.
10244 if (Op.getResNo() == 0)
10247 case X86ISD::SETCC:
10248 KnownZero |= APInt::getHighBitsSet(Mask.getBitWidth(),
10249 Mask.getBitWidth() - 1);
10254 unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(SDValue Op,
10255 unsigned Depth) const {
10256 // SETCC_CARRY sets the dest to ~0 for true or 0 for false.
10257 if (Op.getOpcode() == X86ISD::SETCC_CARRY)
10258 return Op.getValueType().getScalarType().getSizeInBits();
10264 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
10265 /// node is a GlobalAddress + offset.
10266 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
10267 const GlobalValue* &GA,
10268 int64_t &Offset) const {
10269 if (N->getOpcode() == X86ISD::Wrapper) {
10270 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
10271 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
10272 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
10276 return TargetLowering::isGAPlusOffset(N, GA, Offset);
10279 /// PerformShuffleCombine - Combine a vector_shuffle that is equal to
10280 /// build_vector load1, load2, load3, load4, <0, 1, 2, 3> into a 128-bit load
10281 /// if the load addresses are consecutive, non-overlapping, and in the right
10283 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
10284 const TargetLowering &TLI) {
10285 DebugLoc dl = N->getDebugLoc();
10286 EVT VT = N->getValueType(0);
10288 if (VT.getSizeInBits() != 128)
10291 SmallVector<SDValue, 16> Elts;
10292 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
10293 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0));
10295 return EltsFromConsecutiveLoads(VT, Elts, dl, DAG);
10298 /// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index
10299 /// generation and convert it from being a bunch of shuffles and extracts
10300 /// to a simple store and scalar loads to extract the elements.
10301 static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG,
10302 const TargetLowering &TLI) {
10303 SDValue InputVector = N->getOperand(0);
10305 // Only operate on vectors of 4 elements, where the alternative shuffling
10306 // gets to be more expensive.
10307 if (InputVector.getValueType() != MVT::v4i32)
10310 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a
10311 // single use which is a sign-extend or zero-extend, and all elements are
10313 SmallVector<SDNode *, 4> Uses;
10314 unsigned ExtractedElements = 0;
10315 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(),
10316 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) {
10317 if (UI.getUse().getResNo() != InputVector.getResNo())
10320 SDNode *Extract = *UI;
10321 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
10324 if (Extract->getValueType(0) != MVT::i32)
10326 if (!Extract->hasOneUse())
10328 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND &&
10329 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND)
10331 if (!isa<ConstantSDNode>(Extract->getOperand(1)))
10334 // Record which element was extracted.
10335 ExtractedElements |=
10336 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue();
10338 Uses.push_back(Extract);
10341 // If not all the elements were used, this may not be worthwhile.
10342 if (ExtractedElements != 15)
10345 // Ok, we've now decided to do the transformation.
10346 DebugLoc dl = InputVector.getDebugLoc();
10348 // Store the value to a temporary stack slot.
10349 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType());
10350 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr,
10351 MachinePointerInfo(), false, false, 0);
10353 // Replace each use (extract) with a load of the appropriate element.
10354 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(),
10355 UE = Uses.end(); UI != UE; ++UI) {
10356 SDNode *Extract = *UI;
10358 // Compute the element's address.
10359 SDValue Idx = Extract->getOperand(1);
10361 InputVector.getValueType().getVectorElementType().getSizeInBits()/8;
10362 uint64_t Offset = EltSize * cast<ConstantSDNode>(Idx)->getZExtValue();
10363 SDValue OffsetVal = DAG.getConstant(Offset, TLI.getPointerTy());
10365 SDValue ScalarAddr = DAG.getNode(ISD::ADD, dl, Idx.getValueType(),
10366 StackPtr, OffsetVal);
10368 // Load the scalar.
10369 SDValue LoadScalar = DAG.getLoad(Extract->getValueType(0), dl, Ch,
10370 ScalarAddr, MachinePointerInfo(),
10373 // Replace the exact with the load.
10374 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), LoadScalar);
10377 // The replacement was made in place; don't return anything.
10381 /// PerformSELECTCombine - Do target-specific dag combines on SELECT nodes.
10382 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
10383 const X86Subtarget *Subtarget) {
10384 DebugLoc DL = N->getDebugLoc();
10385 SDValue Cond = N->getOperand(0);
10386 // Get the LHS/RHS of the select.
10387 SDValue LHS = N->getOperand(1);
10388 SDValue RHS = N->getOperand(2);
10390 // If we have SSE[12] support, try to form min/max nodes. SSE min/max
10391 // instructions match the semantics of the common C idiom x<y?x:y but not
10392 // x<=y?x:y, because of how they handle negative zero (which can be
10393 // ignored in unsafe-math mode).
10394 if (Subtarget->hasSSE2() &&
10395 (LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64) &&
10396 Cond.getOpcode() == ISD::SETCC) {
10397 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
10399 unsigned Opcode = 0;
10400 // Check for x CC y ? x : y.
10401 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
10402 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
10406 // Converting this to a min would handle NaNs incorrectly, and swapping
10407 // the operands would cause it to handle comparisons between positive
10408 // and negative zero incorrectly.
10409 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
10410 if (!UnsafeFPMath &&
10411 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
10413 std::swap(LHS, RHS);
10415 Opcode = X86ISD::FMIN;
10418 // Converting this to a min would handle comparisons between positive
10419 // and negative zero incorrectly.
10420 if (!UnsafeFPMath &&
10421 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
10423 Opcode = X86ISD::FMIN;
10426 // Converting this to a min would handle both negative zeros and NaNs
10427 // incorrectly, but we can swap the operands to fix both.
10428 std::swap(LHS, RHS);
10432 Opcode = X86ISD::FMIN;
10436 // Converting this to a max would handle comparisons between positive
10437 // and negative zero incorrectly.
10438 if (!UnsafeFPMath &&
10439 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(LHS))
10441 Opcode = X86ISD::FMAX;
10444 // Converting this to a max would handle NaNs incorrectly, and swapping
10445 // the operands would cause it to handle comparisons between positive
10446 // and negative zero incorrectly.
10447 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
10448 if (!UnsafeFPMath &&
10449 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
10451 std::swap(LHS, RHS);
10453 Opcode = X86ISD::FMAX;
10456 // Converting this to a max would handle both negative zeros and NaNs
10457 // incorrectly, but we can swap the operands to fix both.
10458 std::swap(LHS, RHS);
10462 Opcode = X86ISD::FMAX;
10465 // Check for x CC y ? y : x -- a min/max with reversed arms.
10466 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
10467 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
10471 // Converting this to a min would handle comparisons between positive
10472 // and negative zero incorrectly, and swapping the operands would
10473 // cause it to handle NaNs incorrectly.
10474 if (!UnsafeFPMath &&
10475 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) {
10476 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
10478 std::swap(LHS, RHS);
10480 Opcode = X86ISD::FMIN;
10483 // Converting this to a min would handle NaNs incorrectly.
10484 if (!UnsafeFPMath &&
10485 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
10487 Opcode = X86ISD::FMIN;
10490 // Converting this to a min would handle both negative zeros and NaNs
10491 // incorrectly, but we can swap the operands to fix both.
10492 std::swap(LHS, RHS);
10496 Opcode = X86ISD::FMIN;
10500 // Converting this to a max would handle NaNs incorrectly.
10501 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
10503 Opcode = X86ISD::FMAX;
10506 // Converting this to a max would handle comparisons between positive
10507 // and negative zero incorrectly, and swapping the operands would
10508 // cause it to handle NaNs incorrectly.
10509 if (!UnsafeFPMath &&
10510 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) {
10511 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
10513 std::swap(LHS, RHS);
10515 Opcode = X86ISD::FMAX;
10518 // Converting this to a max would handle both negative zeros and NaNs
10519 // incorrectly, but we can swap the operands to fix both.
10520 std::swap(LHS, RHS);
10524 Opcode = X86ISD::FMAX;
10530 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
10533 // If this is a select between two integer constants, try to do some
10535 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
10536 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
10537 // Don't do this for crazy integer types.
10538 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
10539 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
10540 // so that TrueC (the true value) is larger than FalseC.
10541 bool NeedsCondInvert = false;
10543 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
10544 // Efficiently invertible.
10545 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
10546 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
10547 isa<ConstantSDNode>(Cond.getOperand(1))))) {
10548 NeedsCondInvert = true;
10549 std::swap(TrueC, FalseC);
10552 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
10553 if (FalseC->getAPIntValue() == 0 &&
10554 TrueC->getAPIntValue().isPowerOf2()) {
10555 if (NeedsCondInvert) // Invert the condition if needed.
10556 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
10557 DAG.getConstant(1, Cond.getValueType()));
10559 // Zero extend the condition if needed.
10560 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
10562 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
10563 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
10564 DAG.getConstant(ShAmt, MVT::i8));
10567 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
10568 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
10569 if (NeedsCondInvert) // Invert the condition if needed.
10570 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
10571 DAG.getConstant(1, Cond.getValueType()));
10573 // Zero extend the condition if needed.
10574 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
10575 FalseC->getValueType(0), Cond);
10576 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
10577 SDValue(FalseC, 0));
10580 // Optimize cases that will turn into an LEA instruction. This requires
10581 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
10582 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
10583 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
10584 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
10586 bool isFastMultiplier = false;
10588 switch ((unsigned char)Diff) {
10590 case 1: // result = add base, cond
10591 case 2: // result = lea base( , cond*2)
10592 case 3: // result = lea base(cond, cond*2)
10593 case 4: // result = lea base( , cond*4)
10594 case 5: // result = lea base(cond, cond*4)
10595 case 8: // result = lea base( , cond*8)
10596 case 9: // result = lea base(cond, cond*8)
10597 isFastMultiplier = true;
10602 if (isFastMultiplier) {
10603 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
10604 if (NeedsCondInvert) // Invert the condition if needed.
10605 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
10606 DAG.getConstant(1, Cond.getValueType()));
10608 // Zero extend the condition if needed.
10609 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
10611 // Scale the condition by the difference.
10613 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
10614 DAG.getConstant(Diff, Cond.getValueType()));
10616 // Add the base if non-zero.
10617 if (FalseC->getAPIntValue() != 0)
10618 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
10619 SDValue(FalseC, 0));
10629 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
10630 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
10631 TargetLowering::DAGCombinerInfo &DCI) {
10632 DebugLoc DL = N->getDebugLoc();
10634 // If the flag operand isn't dead, don't touch this CMOV.
10635 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
10638 // If this is a select between two integer constants, try to do some
10639 // optimizations. Note that the operands are ordered the opposite of SELECT
10641 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(N->getOperand(1))) {
10642 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
10643 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
10644 // larger than FalseC (the false value).
10645 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
10647 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
10648 CC = X86::GetOppositeBranchCondition(CC);
10649 std::swap(TrueC, FalseC);
10652 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
10653 // This is efficient for any integer data type (including i8/i16) and
10655 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
10656 SDValue Cond = N->getOperand(3);
10657 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
10658 DAG.getConstant(CC, MVT::i8), Cond);
10660 // Zero extend the condition if needed.
10661 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
10663 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
10664 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
10665 DAG.getConstant(ShAmt, MVT::i8));
10666 if (N->getNumValues() == 2) // Dead flag value?
10667 return DCI.CombineTo(N, Cond, SDValue());
10671 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
10672 // for any integer data type, including i8/i16.
10673 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
10674 SDValue Cond = N->getOperand(3);
10675 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
10676 DAG.getConstant(CC, MVT::i8), Cond);
10678 // Zero extend the condition if needed.
10679 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
10680 FalseC->getValueType(0), Cond);
10681 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
10682 SDValue(FalseC, 0));
10684 if (N->getNumValues() == 2) // Dead flag value?
10685 return DCI.CombineTo(N, Cond, SDValue());
10689 // Optimize cases that will turn into an LEA instruction. This requires
10690 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
10691 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
10692 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
10693 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
10695 bool isFastMultiplier = false;
10697 switch ((unsigned char)Diff) {
10699 case 1: // result = add base, cond
10700 case 2: // result = lea base( , cond*2)
10701 case 3: // result = lea base(cond, cond*2)
10702 case 4: // result = lea base( , cond*4)
10703 case 5: // result = lea base(cond, cond*4)
10704 case 8: // result = lea base( , cond*8)
10705 case 9: // result = lea base(cond, cond*8)
10706 isFastMultiplier = true;
10711 if (isFastMultiplier) {
10712 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
10713 SDValue Cond = N->getOperand(3);
10714 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
10715 DAG.getConstant(CC, MVT::i8), Cond);
10716 // Zero extend the condition if needed.
10717 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
10719 // Scale the condition by the difference.
10721 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
10722 DAG.getConstant(Diff, Cond.getValueType()));
10724 // Add the base if non-zero.
10725 if (FalseC->getAPIntValue() != 0)
10726 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
10727 SDValue(FalseC, 0));
10728 if (N->getNumValues() == 2) // Dead flag value?
10729 return DCI.CombineTo(N, Cond, SDValue());
10739 /// PerformMulCombine - Optimize a single multiply with constant into two
10740 /// in order to implement it with two cheaper instructions, e.g.
10741 /// LEA + SHL, LEA + LEA.
10742 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
10743 TargetLowering::DAGCombinerInfo &DCI) {
10744 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
10747 EVT VT = N->getValueType(0);
10748 if (VT != MVT::i64)
10751 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
10754 uint64_t MulAmt = C->getZExtValue();
10755 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
10758 uint64_t MulAmt1 = 0;
10759 uint64_t MulAmt2 = 0;
10760 if ((MulAmt % 9) == 0) {
10762 MulAmt2 = MulAmt / 9;
10763 } else if ((MulAmt % 5) == 0) {
10765 MulAmt2 = MulAmt / 5;
10766 } else if ((MulAmt % 3) == 0) {
10768 MulAmt2 = MulAmt / 3;
10771 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
10772 DebugLoc DL = N->getDebugLoc();
10774 if (isPowerOf2_64(MulAmt2) &&
10775 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
10776 // If second multiplifer is pow2, issue it first. We want the multiply by
10777 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
10779 std::swap(MulAmt1, MulAmt2);
10782 if (isPowerOf2_64(MulAmt1))
10783 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
10784 DAG.getConstant(Log2_64(MulAmt1), MVT::i8));
10786 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
10787 DAG.getConstant(MulAmt1, VT));
10789 if (isPowerOf2_64(MulAmt2))
10790 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
10791 DAG.getConstant(Log2_64(MulAmt2), MVT::i8));
10793 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
10794 DAG.getConstant(MulAmt2, VT));
10796 // Do not add new nodes to DAG combiner worklist.
10797 DCI.CombineTo(N, NewMul, false);
10802 static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) {
10803 SDValue N0 = N->getOperand(0);
10804 SDValue N1 = N->getOperand(1);
10805 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
10806 EVT VT = N0.getValueType();
10808 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2))
10809 // since the result of setcc_c is all zero's or all ones.
10810 if (N1C && N0.getOpcode() == ISD::AND &&
10811 N0.getOperand(1).getOpcode() == ISD::Constant) {
10812 SDValue N00 = N0.getOperand(0);
10813 if (N00.getOpcode() == X86ISD::SETCC_CARRY ||
10814 ((N00.getOpcode() == ISD::ANY_EXTEND ||
10815 N00.getOpcode() == ISD::ZERO_EXTEND) &&
10816 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY)) {
10817 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
10818 APInt ShAmt = N1C->getAPIntValue();
10819 Mask = Mask.shl(ShAmt);
10821 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
10822 N00, DAG.getConstant(Mask, VT));
10829 /// PerformShiftCombine - Transforms vector shift nodes to use vector shifts
10831 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
10832 const X86Subtarget *Subtarget) {
10833 EVT VT = N->getValueType(0);
10834 if (!VT.isVector() && VT.isInteger() &&
10835 N->getOpcode() == ISD::SHL)
10836 return PerformSHLCombine(N, DAG);
10838 // On X86 with SSE2 support, we can transform this to a vector shift if
10839 // all elements are shifted by the same amount. We can't do this in legalize
10840 // because the a constant vector is typically transformed to a constant pool
10841 // so we have no knowledge of the shift amount.
10842 if (!Subtarget->hasSSE2())
10845 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16)
10848 SDValue ShAmtOp = N->getOperand(1);
10849 EVT EltVT = VT.getVectorElementType();
10850 DebugLoc DL = N->getDebugLoc();
10851 SDValue BaseShAmt = SDValue();
10852 if (ShAmtOp.getOpcode() == ISD::BUILD_VECTOR) {
10853 unsigned NumElts = VT.getVectorNumElements();
10855 for (; i != NumElts; ++i) {
10856 SDValue Arg = ShAmtOp.getOperand(i);
10857 if (Arg.getOpcode() == ISD::UNDEF) continue;
10861 for (; i != NumElts; ++i) {
10862 SDValue Arg = ShAmtOp.getOperand(i);
10863 if (Arg.getOpcode() == ISD::UNDEF) continue;
10864 if (Arg != BaseShAmt) {
10868 } else if (ShAmtOp.getOpcode() == ISD::VECTOR_SHUFFLE &&
10869 cast<ShuffleVectorSDNode>(ShAmtOp)->isSplat()) {
10870 SDValue InVec = ShAmtOp.getOperand(0);
10871 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
10872 unsigned NumElts = InVec.getValueType().getVectorNumElements();
10874 for (; i != NumElts; ++i) {
10875 SDValue Arg = InVec.getOperand(i);
10876 if (Arg.getOpcode() == ISD::UNDEF) continue;
10880 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
10881 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
10882 unsigned SplatIdx= cast<ShuffleVectorSDNode>(ShAmtOp)->getSplatIndex();
10883 if (C->getZExtValue() == SplatIdx)
10884 BaseShAmt = InVec.getOperand(1);
10887 if (BaseShAmt.getNode() == 0)
10888 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, ShAmtOp,
10889 DAG.getIntPtrConstant(0));
10893 // The shift amount is an i32.
10894 if (EltVT.bitsGT(MVT::i32))
10895 BaseShAmt = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, BaseShAmt);
10896 else if (EltVT.bitsLT(MVT::i32))
10897 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, BaseShAmt);
10899 // The shift amount is identical so we can do a vector shift.
10900 SDValue ValOp = N->getOperand(0);
10901 switch (N->getOpcode()) {
10903 llvm_unreachable("Unknown shift opcode!");
10906 if (VT == MVT::v2i64)
10907 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
10908 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32),
10910 if (VT == MVT::v4i32)
10911 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
10912 DAG.getConstant(Intrinsic::x86_sse2_pslli_d, MVT::i32),
10914 if (VT == MVT::v8i16)
10915 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
10916 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32),
10920 if (VT == MVT::v4i32)
10921 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
10922 DAG.getConstant(Intrinsic::x86_sse2_psrai_d, MVT::i32),
10924 if (VT == MVT::v8i16)
10925 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
10926 DAG.getConstant(Intrinsic::x86_sse2_psrai_w, MVT::i32),
10930 if (VT == MVT::v2i64)
10931 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
10932 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32),
10934 if (VT == MVT::v4i32)
10935 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
10936 DAG.getConstant(Intrinsic::x86_sse2_psrli_d, MVT::i32),
10938 if (VT == MVT::v8i16)
10939 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
10940 DAG.getConstant(Intrinsic::x86_sse2_psrli_w, MVT::i32),
10947 static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
10948 TargetLowering::DAGCombinerInfo &DCI,
10949 const X86Subtarget *Subtarget) {
10950 if (DCI.isBeforeLegalizeOps())
10953 EVT VT = N->getValueType(0);
10954 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64)
10957 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
10958 SDValue N0 = N->getOperand(0);
10959 SDValue N1 = N->getOperand(1);
10960 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
10962 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
10964 if (!N0.hasOneUse() || !N1.hasOneUse())
10967 SDValue ShAmt0 = N0.getOperand(1);
10968 if (ShAmt0.getValueType() != MVT::i8)
10970 SDValue ShAmt1 = N1.getOperand(1);
10971 if (ShAmt1.getValueType() != MVT::i8)
10973 if (ShAmt0.getOpcode() == ISD::TRUNCATE)
10974 ShAmt0 = ShAmt0.getOperand(0);
10975 if (ShAmt1.getOpcode() == ISD::TRUNCATE)
10976 ShAmt1 = ShAmt1.getOperand(0);
10978 DebugLoc DL = N->getDebugLoc();
10979 unsigned Opc = X86ISD::SHLD;
10980 SDValue Op0 = N0.getOperand(0);
10981 SDValue Op1 = N1.getOperand(0);
10982 if (ShAmt0.getOpcode() == ISD::SUB) {
10983 Opc = X86ISD::SHRD;
10984 std::swap(Op0, Op1);
10985 std::swap(ShAmt0, ShAmt1);
10988 unsigned Bits = VT.getSizeInBits();
10989 if (ShAmt1.getOpcode() == ISD::SUB) {
10990 SDValue Sum = ShAmt1.getOperand(0);
10991 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) {
10992 SDValue ShAmt1Op1 = ShAmt1.getOperand(1);
10993 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE)
10994 ShAmt1Op1 = ShAmt1Op1.getOperand(0);
10995 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0)
10996 return DAG.getNode(Opc, DL, VT,
10998 DAG.getNode(ISD::TRUNCATE, DL,
11001 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) {
11002 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0);
11004 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits)
11005 return DAG.getNode(Opc, DL, VT,
11006 N0.getOperand(0), N1.getOperand(0),
11007 DAG.getNode(ISD::TRUNCATE, DL,
11014 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
11015 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
11016 const X86Subtarget *Subtarget) {
11017 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
11018 // the FP state in cases where an emms may be missing.
11019 // A preferable solution to the general problem is to figure out the right
11020 // places to insert EMMS. This qualifies as a quick hack.
11022 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
11023 StoreSDNode *St = cast<StoreSDNode>(N);
11024 EVT VT = St->getValue().getValueType();
11025 if (VT.getSizeInBits() != 64)
11028 const Function *F = DAG.getMachineFunction().getFunction();
11029 bool NoImplicitFloatOps = F->hasFnAttr(Attribute::NoImplicitFloat);
11030 bool F64IsLegal = !UseSoftFloat && !NoImplicitFloatOps
11031 && Subtarget->hasSSE2();
11032 if ((VT.isVector() ||
11033 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
11034 isa<LoadSDNode>(St->getValue()) &&
11035 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
11036 St->getChain().hasOneUse() && !St->isVolatile()) {
11037 SDNode* LdVal = St->getValue().getNode();
11038 LoadSDNode *Ld = 0;
11039 int TokenFactorIndex = -1;
11040 SmallVector<SDValue, 8> Ops;
11041 SDNode* ChainVal = St->getChain().getNode();
11042 // Must be a store of a load. We currently handle two cases: the load
11043 // is a direct child, and it's under an intervening TokenFactor. It is
11044 // possible to dig deeper under nested TokenFactors.
11045 if (ChainVal == LdVal)
11046 Ld = cast<LoadSDNode>(St->getChain());
11047 else if (St->getValue().hasOneUse() &&
11048 ChainVal->getOpcode() == ISD::TokenFactor) {
11049 for (unsigned i=0, e = ChainVal->getNumOperands(); i != e; ++i) {
11050 if (ChainVal->getOperand(i).getNode() == LdVal) {
11051 TokenFactorIndex = i;
11052 Ld = cast<LoadSDNode>(St->getValue());
11054 Ops.push_back(ChainVal->getOperand(i));
11058 if (!Ld || !ISD::isNormalLoad(Ld))
11061 // If this is not the MMX case, i.e. we are just turning i64 load/store
11062 // into f64 load/store, avoid the transformation if there are multiple
11063 // uses of the loaded value.
11064 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
11067 DebugLoc LdDL = Ld->getDebugLoc();
11068 DebugLoc StDL = N->getDebugLoc();
11069 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
11070 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
11072 if (Subtarget->is64Bit() || F64IsLegal) {
11073 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
11074 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(),
11075 Ld->getPointerInfo(), Ld->isVolatile(),
11076 Ld->isNonTemporal(), Ld->getAlignment());
11077 SDValue NewChain = NewLd.getValue(1);
11078 if (TokenFactorIndex != -1) {
11079 Ops.push_back(NewChain);
11080 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
11083 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
11084 St->getPointerInfo(),
11085 St->isVolatile(), St->isNonTemporal(),
11086 St->getAlignment());
11089 // Otherwise, lower to two pairs of 32-bit loads / stores.
11090 SDValue LoAddr = Ld->getBasePtr();
11091 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
11092 DAG.getConstant(4, MVT::i32));
11094 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
11095 Ld->getPointerInfo(),
11096 Ld->isVolatile(), Ld->isNonTemporal(),
11097 Ld->getAlignment());
11098 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
11099 Ld->getPointerInfo().getWithOffset(4),
11100 Ld->isVolatile(), Ld->isNonTemporal(),
11101 MinAlign(Ld->getAlignment(), 4));
11103 SDValue NewChain = LoLd.getValue(1);
11104 if (TokenFactorIndex != -1) {
11105 Ops.push_back(LoLd);
11106 Ops.push_back(HiLd);
11107 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
11111 LoAddr = St->getBasePtr();
11112 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
11113 DAG.getConstant(4, MVT::i32));
11115 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
11116 St->getPointerInfo(),
11117 St->isVolatile(), St->isNonTemporal(),
11118 St->getAlignment());
11119 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
11120 St->getPointerInfo().getWithOffset(4),
11122 St->isNonTemporal(),
11123 MinAlign(St->getAlignment(), 4));
11124 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
11129 /// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and
11130 /// X86ISD::FXOR nodes.
11131 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
11132 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
11133 // F[X]OR(0.0, x) -> x
11134 // F[X]OR(x, 0.0) -> x
11135 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
11136 if (C->getValueAPF().isPosZero())
11137 return N->getOperand(1);
11138 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
11139 if (C->getValueAPF().isPosZero())
11140 return N->getOperand(0);
11144 /// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes.
11145 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
11146 // FAND(0.0, x) -> 0.0
11147 // FAND(x, 0.0) -> 0.0
11148 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
11149 if (C->getValueAPF().isPosZero())
11150 return N->getOperand(0);
11151 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
11152 if (C->getValueAPF().isPosZero())
11153 return N->getOperand(1);
11157 static SDValue PerformBTCombine(SDNode *N,
11159 TargetLowering::DAGCombinerInfo &DCI) {
11160 // BT ignores high bits in the bit index operand.
11161 SDValue Op1 = N->getOperand(1);
11162 if (Op1.hasOneUse()) {
11163 unsigned BitWidth = Op1.getValueSizeInBits();
11164 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
11165 APInt KnownZero, KnownOne;
11166 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
11167 !DCI.isBeforeLegalizeOps());
11168 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
11169 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
11170 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
11171 DCI.CommitTargetLoweringOpt(TLO);
11176 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
11177 SDValue Op = N->getOperand(0);
11178 if (Op.getOpcode() == ISD::BIT_CONVERT)
11179 Op = Op.getOperand(0);
11180 EVT VT = N->getValueType(0), OpVT = Op.getValueType();
11181 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
11182 VT.getVectorElementType().getSizeInBits() ==
11183 OpVT.getVectorElementType().getSizeInBits()) {
11184 return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(), VT, Op);
11189 static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG) {
11190 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) ->
11191 // (and (i32 x86isd::setcc_carry), 1)
11192 // This eliminates the zext. This transformation is necessary because
11193 // ISD::SETCC is always legalized to i8.
11194 DebugLoc dl = N->getDebugLoc();
11195 SDValue N0 = N->getOperand(0);
11196 EVT VT = N->getValueType(0);
11197 if (N0.getOpcode() == ISD::AND &&
11199 N0.getOperand(0).hasOneUse()) {
11200 SDValue N00 = N0.getOperand(0);
11201 if (N00.getOpcode() != X86ISD::SETCC_CARRY)
11203 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
11204 if (!C || C->getZExtValue() != 1)
11206 return DAG.getNode(ISD::AND, dl, VT,
11207 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
11208 N00.getOperand(0), N00.getOperand(1)),
11209 DAG.getConstant(1, VT));
11215 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
11216 DAGCombinerInfo &DCI) const {
11217 SelectionDAG &DAG = DCI.DAG;
11218 switch (N->getOpcode()) {
11220 case ISD::EXTRACT_VECTOR_ELT:
11221 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, *this);
11222 case ISD::SELECT: return PerformSELECTCombine(N, DAG, Subtarget);
11223 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI);
11224 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
11227 case ISD::SRL: return PerformShiftCombine(N, DAG, Subtarget);
11228 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget);
11229 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
11231 case X86ISD::FOR: return PerformFORCombine(N, DAG);
11232 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
11233 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
11234 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
11235 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG);
11236 case X86ISD::SHUFPS: // Handle all target specific shuffles
11237 case X86ISD::SHUFPD:
11238 case X86ISD::PALIGN:
11239 case X86ISD::PUNPCKHBW:
11240 case X86ISD::PUNPCKHWD:
11241 case X86ISD::PUNPCKHDQ:
11242 case X86ISD::PUNPCKHQDQ:
11243 case X86ISD::UNPCKHPS:
11244 case X86ISD::UNPCKHPD:
11245 case X86ISD::PUNPCKLBW:
11246 case X86ISD::PUNPCKLWD:
11247 case X86ISD::PUNPCKLDQ:
11248 case X86ISD::PUNPCKLQDQ:
11249 case X86ISD::UNPCKLPS:
11250 case X86ISD::UNPCKLPD:
11251 case X86ISD::MOVHLPS:
11252 case X86ISD::MOVLHPS:
11253 case X86ISD::PSHUFD:
11254 case X86ISD::PSHUFHW:
11255 case X86ISD::PSHUFLW:
11256 case X86ISD::MOVSS:
11257 case X86ISD::MOVSD:
11258 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, *this);
11264 /// isTypeDesirableForOp - Return true if the target has native support for
11265 /// the specified value type and it is 'desirable' to use the type for the
11266 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
11267 /// instruction encodings are longer and some i16 instructions are slow.
11268 bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const {
11269 if (!isTypeLegal(VT))
11271 if (VT != MVT::i16)
11278 case ISD::SIGN_EXTEND:
11279 case ISD::ZERO_EXTEND:
11280 case ISD::ANY_EXTEND:
11293 /// IsDesirableToPromoteOp - This method query the target whether it is
11294 /// beneficial for dag combiner to promote the specified node. If true, it
11295 /// should return the desired promotion type by reference.
11296 bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
11297 EVT VT = Op.getValueType();
11298 if (VT != MVT::i16)
11301 bool Promote = false;
11302 bool Commute = false;
11303 switch (Op.getOpcode()) {
11306 LoadSDNode *LD = cast<LoadSDNode>(Op);
11307 // If the non-extending load has a single use and it's not live out, then it
11308 // might be folded.
11309 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&&
11310 Op.hasOneUse()*/) {
11311 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
11312 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
11313 // The only case where we'd want to promote LOAD (rather then it being
11314 // promoted as an operand is when it's only use is liveout.
11315 if (UI->getOpcode() != ISD::CopyToReg)
11322 case ISD::SIGN_EXTEND:
11323 case ISD::ZERO_EXTEND:
11324 case ISD::ANY_EXTEND:
11329 SDValue N0 = Op.getOperand(0);
11330 // Look out for (store (shl (load), x)).
11331 if (MayFoldLoad(N0) && MayFoldIntoStore(Op))
11344 SDValue N0 = Op.getOperand(0);
11345 SDValue N1 = Op.getOperand(1);
11346 if (!Commute && MayFoldLoad(N1))
11348 // Avoid disabling potential load folding opportunities.
11349 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op)))
11351 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op)))
11361 //===----------------------------------------------------------------------===//
11362 // X86 Inline Assembly Support
11363 //===----------------------------------------------------------------------===//
11365 static bool LowerToBSwap(CallInst *CI) {
11366 // FIXME: this should verify that we are targetting a 486 or better. If not,
11367 // we will turn this bswap into something that will be lowered to logical ops
11368 // instead of emitting the bswap asm. For now, we don't support 486 or lower
11369 // so don't worry about this.
11371 // Verify this is a simple bswap.
11372 if (CI->getNumArgOperands() != 1 ||
11373 CI->getType() != CI->getArgOperand(0)->getType() ||
11374 !CI->getType()->isIntegerTy())
11377 const IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
11378 if (!Ty || Ty->getBitWidth() % 16 != 0)
11381 // Okay, we can do this xform, do so now.
11382 const Type *Tys[] = { Ty };
11383 Module *M = CI->getParent()->getParent()->getParent();
11384 Constant *Int = Intrinsic::getDeclaration(M, Intrinsic::bswap, Tys, 1);
11386 Value *Op = CI->getArgOperand(0);
11387 Op = CallInst::Create(Int, Op, CI->getName(), CI);
11389 CI->replaceAllUsesWith(Op);
11390 CI->eraseFromParent();
11394 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
11395 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
11396 InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints();
11398 std::string AsmStr = IA->getAsmString();
11400 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
11401 SmallVector<StringRef, 4> AsmPieces;
11402 SplitString(AsmStr, AsmPieces, ";\n");
11404 switch (AsmPieces.size()) {
11405 default: return false;
11407 AsmStr = AsmPieces[0];
11409 SplitString(AsmStr, AsmPieces, " \t"); // Split with whitespace.
11412 if (AsmPieces.size() == 2 &&
11413 (AsmPieces[0] == "bswap" ||
11414 AsmPieces[0] == "bswapq" ||
11415 AsmPieces[0] == "bswapl") &&
11416 (AsmPieces[1] == "$0" ||
11417 AsmPieces[1] == "${0:q}")) {
11418 // No need to check constraints, nothing other than the equivalent of
11419 // "=r,0" would be valid here.
11420 return LowerToBSwap(CI);
11422 // rorw $$8, ${0:w} --> llvm.bswap.i16
11423 if (CI->getType()->isIntegerTy(16) &&
11424 AsmPieces.size() == 3 &&
11425 (AsmPieces[0] == "rorw" || AsmPieces[0] == "rolw") &&
11426 AsmPieces[1] == "$$8," &&
11427 AsmPieces[2] == "${0:w}" &&
11428 IA->getConstraintString().compare(0, 5, "=r,0,") == 0) {
11430 const std::string &Constraints = IA->getConstraintString();
11431 SplitString(StringRef(Constraints).substr(5), AsmPieces, ",");
11432 std::sort(AsmPieces.begin(), AsmPieces.end());
11433 if (AsmPieces.size() == 4 &&
11434 AsmPieces[0] == "~{cc}" &&
11435 AsmPieces[1] == "~{dirflag}" &&
11436 AsmPieces[2] == "~{flags}" &&
11437 AsmPieces[3] == "~{fpsr}") {
11438 return LowerToBSwap(CI);
11443 if (CI->getType()->isIntegerTy(32) &&
11444 IA->getConstraintString().compare(0, 5, "=r,0,") == 0) {
11445 SmallVector<StringRef, 4> Words;
11446 SplitString(AsmPieces[0], Words, " \t,");
11447 if (Words.size() == 3 && Words[0] == "rorw" && Words[1] == "$$8" &&
11448 Words[2] == "${0:w}") {
11450 SplitString(AsmPieces[1], Words, " \t,");
11451 if (Words.size() == 3 && Words[0] == "rorl" && Words[1] == "$$16" &&
11452 Words[2] == "$0") {
11454 SplitString(AsmPieces[2], Words, " \t,");
11455 if (Words.size() == 3 && Words[0] == "rorw" && Words[1] == "$$8" &&
11456 Words[2] == "${0:w}") {
11458 const std::string &Constraints = IA->getConstraintString();
11459 SplitString(StringRef(Constraints).substr(5), AsmPieces, ",");
11460 std::sort(AsmPieces.begin(), AsmPieces.end());
11461 if (AsmPieces.size() == 4 &&
11462 AsmPieces[0] == "~{cc}" &&
11463 AsmPieces[1] == "~{dirflag}" &&
11464 AsmPieces[2] == "~{flags}" &&
11465 AsmPieces[3] == "~{fpsr}") {
11466 return LowerToBSwap(CI);
11472 if (CI->getType()->isIntegerTy(64) &&
11473 Constraints.size() >= 2 &&
11474 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
11475 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
11476 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
11477 SmallVector<StringRef, 4> Words;
11478 SplitString(AsmPieces[0], Words, " \t");
11479 if (Words.size() == 2 && Words[0] == "bswap" && Words[1] == "%eax") {
11481 SplitString(AsmPieces[1], Words, " \t");
11482 if (Words.size() == 2 && Words[0] == "bswap" && Words[1] == "%edx") {
11484 SplitString(AsmPieces[2], Words, " \t,");
11485 if (Words.size() == 3 && Words[0] == "xchgl" && Words[1] == "%eax" &&
11486 Words[2] == "%edx") {
11487 return LowerToBSwap(CI);
11499 /// getConstraintType - Given a constraint letter, return the type of
11500 /// constraint it is for this target.
11501 X86TargetLowering::ConstraintType
11502 X86TargetLowering::getConstraintType(const std::string &Constraint) const {
11503 if (Constraint.size() == 1) {
11504 switch (Constraint[0]) {
11514 return C_RegisterClass;
11538 return TargetLowering::getConstraintType(Constraint);
11541 /// Examine constraint type and operand type and determine a weight value.
11542 /// This object must already have been set up with the operand type
11543 /// and the current alternative constraint selected.
11544 TargetLowering::ConstraintWeight
11545 X86TargetLowering::getSingleConstraintMatchWeight(
11546 AsmOperandInfo &info, const char *constraint) const {
11547 ConstraintWeight weight = CW_Invalid;
11548 Value *CallOperandVal = info.CallOperandVal;
11549 // If we don't have a value, we can't do a match,
11550 // but allow it at the lowest weight.
11551 if (CallOperandVal == NULL)
11553 const Type *type = CallOperandVal->getType();
11554 // Look at the constraint type.
11555 switch (*constraint) {
11557 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
11568 if (CallOperandVal->getType()->isIntegerTy())
11569 weight = CW_SpecificReg;
11574 if (type->isFloatingPointTy())
11575 weight = CW_SpecificReg;
11578 if (type->isX86_MMXTy() && !DisableMMX && Subtarget->hasMMX())
11579 weight = CW_SpecificReg;
11583 if ((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasSSE1())
11584 weight = CW_Register;
11587 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) {
11588 if (C->getZExtValue() <= 31)
11589 weight = CW_Constant;
11593 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
11594 if (C->getZExtValue() <= 63)
11595 weight = CW_Constant;
11599 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
11600 if ((C->getSExtValue() >= -0x80) && (C->getSExtValue() <= 0x7f))
11601 weight = CW_Constant;
11605 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
11606 if ((C->getZExtValue() == 0xff) || (C->getZExtValue() == 0xffff))
11607 weight = CW_Constant;
11611 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
11612 if (C->getZExtValue() <= 3)
11613 weight = CW_Constant;
11617 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
11618 if (C->getZExtValue() <= 0xff)
11619 weight = CW_Constant;
11624 if (dyn_cast<ConstantFP>(CallOperandVal)) {
11625 weight = CW_Constant;
11629 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
11630 if ((C->getSExtValue() >= -0x80000000LL) &&
11631 (C->getSExtValue() <= 0x7fffffffLL))
11632 weight = CW_Constant;
11636 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
11637 if (C->getZExtValue() <= 0xffffffff)
11638 weight = CW_Constant;
11645 /// LowerXConstraint - try to replace an X constraint, which matches anything,
11646 /// with another that has more specific requirements based on the type of the
11647 /// corresponding operand.
11648 const char *X86TargetLowering::
11649 LowerXConstraint(EVT ConstraintVT) const {
11650 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
11651 // 'f' like normal targets.
11652 if (ConstraintVT.isFloatingPoint()) {
11653 if (Subtarget->hasSSE2())
11655 if (Subtarget->hasSSE1())
11659 return TargetLowering::LowerXConstraint(ConstraintVT);
11662 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
11663 /// vector. If it is invalid, don't add anything to Ops.
11664 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
11666 std::vector<SDValue>&Ops,
11667 SelectionDAG &DAG) const {
11668 SDValue Result(0, 0);
11670 switch (Constraint) {
11673 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
11674 if (C->getZExtValue() <= 31) {
11675 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
11681 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
11682 if (C->getZExtValue() <= 63) {
11683 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
11689 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
11690 if ((int8_t)C->getSExtValue() == C->getSExtValue()) {
11691 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
11697 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
11698 if (C->getZExtValue() <= 255) {
11699 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
11705 // 32-bit signed value
11706 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
11707 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
11708 C->getSExtValue())) {
11709 // Widen to 64 bits here to get it sign extended.
11710 Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64);
11713 // FIXME gcc accepts some relocatable values here too, but only in certain
11714 // memory models; it's complicated.
11719 // 32-bit unsigned value
11720 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
11721 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
11722 C->getZExtValue())) {
11723 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
11727 // FIXME gcc accepts some relocatable values here too, but only in certain
11728 // memory models; it's complicated.
11732 // Literal immediates are always ok.
11733 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
11734 // Widen to 64 bits here to get it sign extended.
11735 Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64);
11739 // In any sort of PIC mode addresses need to be computed at runtime by
11740 // adding in a register or some sort of table lookup. These can't
11741 // be used as immediates.
11742 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC())
11745 // If we are in non-pic codegen mode, we allow the address of a global (with
11746 // an optional displacement) to be used with 'i'.
11747 GlobalAddressSDNode *GA = 0;
11748 int64_t Offset = 0;
11750 // Match either (GA), (GA+C), (GA+C1+C2), etc.
11752 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
11753 Offset += GA->getOffset();
11755 } else if (Op.getOpcode() == ISD::ADD) {
11756 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
11757 Offset += C->getZExtValue();
11758 Op = Op.getOperand(0);
11761 } else if (Op.getOpcode() == ISD::SUB) {
11762 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
11763 Offset += -C->getZExtValue();
11764 Op = Op.getOperand(0);
11769 // Otherwise, this isn't something we can handle, reject it.
11773 const GlobalValue *GV = GA->getGlobal();
11774 // If we require an extra load to get this address, as in PIC mode, we
11775 // can't accept it.
11776 if (isGlobalStubReference(Subtarget->ClassifyGlobalReference(GV,
11777 getTargetMachine())))
11780 Result = DAG.getTargetGlobalAddress(GV, Op.getDebugLoc(),
11781 GA->getValueType(0), Offset);
11786 if (Result.getNode()) {
11787 Ops.push_back(Result);
11790 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
11793 std::vector<unsigned> X86TargetLowering::
11794 getRegClassForInlineAsmConstraint(const std::string &Constraint,
11796 if (Constraint.size() == 1) {
11797 // FIXME: not handling fp-stack yet!
11798 switch (Constraint[0]) { // GCC X86 Constraint Letters
11799 default: break; // Unknown constraint letter
11800 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
11801 if (Subtarget->is64Bit()) {
11802 if (VT == MVT::i32)
11803 return make_vector<unsigned>(X86::EAX, X86::EDX, X86::ECX, X86::EBX,
11804 X86::ESI, X86::EDI, X86::R8D, X86::R9D,
11805 X86::R10D,X86::R11D,X86::R12D,
11806 X86::R13D,X86::R14D,X86::R15D,
11807 X86::EBP, X86::ESP, 0);
11808 else if (VT == MVT::i16)
11809 return make_vector<unsigned>(X86::AX, X86::DX, X86::CX, X86::BX,
11810 X86::SI, X86::DI, X86::R8W,X86::R9W,
11811 X86::R10W,X86::R11W,X86::R12W,
11812 X86::R13W,X86::R14W,X86::R15W,
11813 X86::BP, X86::SP, 0);
11814 else if (VT == MVT::i8)
11815 return make_vector<unsigned>(X86::AL, X86::DL, X86::CL, X86::BL,
11816 X86::SIL, X86::DIL, X86::R8B,X86::R9B,
11817 X86::R10B,X86::R11B,X86::R12B,
11818 X86::R13B,X86::R14B,X86::R15B,
11819 X86::BPL, X86::SPL, 0);
11821 else if (VT == MVT::i64)
11822 return make_vector<unsigned>(X86::RAX, X86::RDX, X86::RCX, X86::RBX,
11823 X86::RSI, X86::RDI, X86::R8, X86::R9,
11824 X86::R10, X86::R11, X86::R12,
11825 X86::R13, X86::R14, X86::R15,
11826 X86::RBP, X86::RSP, 0);
11830 // 32-bit fallthrough
11831 case 'Q': // Q_REGS
11832 if (VT == MVT::i32)
11833 return make_vector<unsigned>(X86::EAX, X86::EDX, X86::ECX, X86::EBX, 0);
11834 else if (VT == MVT::i16)
11835 return make_vector<unsigned>(X86::AX, X86::DX, X86::CX, X86::BX, 0);
11836 else if (VT == MVT::i8)
11837 return make_vector<unsigned>(X86::AL, X86::DL, X86::CL, X86::BL, 0);
11838 else if (VT == MVT::i64)
11839 return make_vector<unsigned>(X86::RAX, X86::RDX, X86::RCX, X86::RBX, 0);
11844 return std::vector<unsigned>();
11847 std::pair<unsigned, const TargetRegisterClass*>
11848 X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
11850 // First, see if this is a constraint that directly corresponds to an LLVM
11852 if (Constraint.size() == 1) {
11853 // GCC Constraint Letters
11854 switch (Constraint[0]) {
11856 case 'r': // GENERAL_REGS
11857 case 'l': // INDEX_REGS
11859 return std::make_pair(0U, X86::GR8RegisterClass);
11860 if (VT == MVT::i16)
11861 return std::make_pair(0U, X86::GR16RegisterClass);
11862 if (VT == MVT::i32 || !Subtarget->is64Bit())
11863 return std::make_pair(0U, X86::GR32RegisterClass);
11864 return std::make_pair(0U, X86::GR64RegisterClass);
11865 case 'R': // LEGACY_REGS
11867 return std::make_pair(0U, X86::GR8_NOREXRegisterClass);
11868 if (VT == MVT::i16)
11869 return std::make_pair(0U, X86::GR16_NOREXRegisterClass);
11870 if (VT == MVT::i32 || !Subtarget->is64Bit())
11871 return std::make_pair(0U, X86::GR32_NOREXRegisterClass);
11872 return std::make_pair(0U, X86::GR64_NOREXRegisterClass);
11873 case 'f': // FP Stack registers.
11874 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
11875 // value to the correct fpstack register class.
11876 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
11877 return std::make_pair(0U, X86::RFP32RegisterClass);
11878 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
11879 return std::make_pair(0U, X86::RFP64RegisterClass);
11880 return std::make_pair(0U, X86::RFP80RegisterClass);
11881 case 'y': // MMX_REGS if MMX allowed.
11882 if (!Subtarget->hasMMX()) break;
11883 return std::make_pair(0U, X86::VR64RegisterClass);
11884 case 'Y': // SSE_REGS if SSE2 allowed
11885 if (!Subtarget->hasSSE2()) break;
11887 case 'x': // SSE_REGS if SSE1 allowed
11888 if (!Subtarget->hasSSE1()) break;
11890 switch (VT.getSimpleVT().SimpleTy) {
11892 // Scalar SSE types.
11895 return std::make_pair(0U, X86::FR32RegisterClass);
11898 return std::make_pair(0U, X86::FR64RegisterClass);
11906 return std::make_pair(0U, X86::VR128RegisterClass);
11912 // Use the default implementation in TargetLowering to convert the register
11913 // constraint into a member of a register class.
11914 std::pair<unsigned, const TargetRegisterClass*> Res;
11915 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
11917 // Not found as a standard register?
11918 if (Res.second == 0) {
11919 // Map st(0) -> st(7) -> ST0
11920 if (Constraint.size() == 7 && Constraint[0] == '{' &&
11921 tolower(Constraint[1]) == 's' &&
11922 tolower(Constraint[2]) == 't' &&
11923 Constraint[3] == '(' &&
11924 (Constraint[4] >= '0' && Constraint[4] <= '7') &&
11925 Constraint[5] == ')' &&
11926 Constraint[6] == '}') {
11928 Res.first = X86::ST0+Constraint[4]-'0';
11929 Res.second = X86::RFP80RegisterClass;
11933 // GCC allows "st(0)" to be called just plain "st".
11934 if (StringRef("{st}").equals_lower(Constraint)) {
11935 Res.first = X86::ST0;
11936 Res.second = X86::RFP80RegisterClass;
11941 if (StringRef("{flags}").equals_lower(Constraint)) {
11942 Res.first = X86::EFLAGS;
11943 Res.second = X86::CCRRegisterClass;
11947 // 'A' means EAX + EDX.
11948 if (Constraint == "A") {
11949 Res.first = X86::EAX;
11950 Res.second = X86::GR32_ADRegisterClass;
11956 // Otherwise, check to see if this is a register class of the wrong value
11957 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
11958 // turn into {ax},{dx}.
11959 if (Res.second->hasType(VT))
11960 return Res; // Correct type already, nothing to do.
11962 // All of the single-register GCC register classes map their values onto
11963 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
11964 // really want an 8-bit or 32-bit register, map to the appropriate register
11965 // class and return the appropriate register.
11966 if (Res.second == X86::GR16RegisterClass) {
11967 if (VT == MVT::i8) {
11968 unsigned DestReg = 0;
11969 switch (Res.first) {
11971 case X86::AX: DestReg = X86::AL; break;
11972 case X86::DX: DestReg = X86::DL; break;
11973 case X86::CX: DestReg = X86::CL; break;
11974 case X86::BX: DestReg = X86::BL; break;
11977 Res.first = DestReg;
11978 Res.second = X86::GR8RegisterClass;
11980 } else if (VT == MVT::i32) {
11981 unsigned DestReg = 0;
11982 switch (Res.first) {
11984 case X86::AX: DestReg = X86::EAX; break;
11985 case X86::DX: DestReg = X86::EDX; break;
11986 case X86::CX: DestReg = X86::ECX; break;
11987 case X86::BX: DestReg = X86::EBX; break;
11988 case X86::SI: DestReg = X86::ESI; break;
11989 case X86::DI: DestReg = X86::EDI; break;
11990 case X86::BP: DestReg = X86::EBP; break;
11991 case X86::SP: DestReg = X86::ESP; break;
11994 Res.first = DestReg;
11995 Res.second = X86::GR32RegisterClass;
11997 } else if (VT == MVT::i64) {
11998 unsigned DestReg = 0;
11999 switch (Res.first) {
12001 case X86::AX: DestReg = X86::RAX; break;
12002 case X86::DX: DestReg = X86::RDX; break;
12003 case X86::CX: DestReg = X86::RCX; break;
12004 case X86::BX: DestReg = X86::RBX; break;
12005 case X86::SI: DestReg = X86::RSI; break;
12006 case X86::DI: DestReg = X86::RDI; break;
12007 case X86::BP: DestReg = X86::RBP; break;
12008 case X86::SP: DestReg = X86::RSP; break;
12011 Res.first = DestReg;
12012 Res.second = X86::GR64RegisterClass;
12015 } else if (Res.second == X86::FR32RegisterClass ||
12016 Res.second == X86::FR64RegisterClass ||
12017 Res.second == X86::VR128RegisterClass) {
12018 // Handle references to XMM physical registers that got mapped into the
12019 // wrong class. This can happen with constraints like {xmm0} where the
12020 // target independent register mapper will just pick the first match it can
12021 // find, ignoring the required type.
12022 if (VT == MVT::f32)
12023 Res.second = X86::FR32RegisterClass;
12024 else if (VT == MVT::f64)
12025 Res.second = X86::FR64RegisterClass;
12026 else if (X86::VR128RegisterClass->hasType(VT))
12027 Res.second = X86::VR128RegisterClass;