1 //===-- X86ISelLowering.h - X86 DAG Lowering Interface ----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Chris Lattner and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
16 #include "X86InstrBuilder.h"
17 #include "X86ISelLowering.h"
18 #include "X86TargetMachine.h"
19 #include "llvm/CallingConv.h"
20 #include "llvm/Function.h"
21 #include "llvm/CodeGen/MachineFrameInfo.h"
22 #include "llvm/CodeGen/MachineFunction.h"
23 #include "llvm/CodeGen/MachineInstrBuilder.h"
24 #include "llvm/CodeGen/SelectionDAG.h"
25 #include "llvm/CodeGen/SSARegMap.h"
26 #include "llvm/Target/TargetOptions.h"
30 #include "llvm/Support/CommandLine.h"
31 static cl::opt<bool> EnableFastCC("enable-x86-fastcc", cl::Hidden,
32 cl::desc("Enable fastcc on X86"));
34 X86TargetLowering::X86TargetLowering(TargetMachine &TM)
35 : TargetLowering(TM) {
36 // Set up the TargetLowering object.
38 // X86 is weird, it always uses i8 for shift amounts and setcc results.
39 setShiftAmountType(MVT::i8);
40 setSetCCResultType(MVT::i8);
41 setSetCCResultContents(ZeroOrOneSetCCResult);
42 setShiftAmountFlavor(Mask); // shl X, 32 == shl X, 0
43 setStackPointerRegisterToSaveRestore(X86::ESP);
45 // Set up the register classes.
46 addRegisterClass(MVT::i8, X86::R8RegisterClass);
47 addRegisterClass(MVT::i16, X86::R16RegisterClass);
48 addRegisterClass(MVT::i32, X86::R32RegisterClass);
50 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
52 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
53 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
54 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
57 // No SSE i64 SINT_TO_FP, so expand i32 UINT_TO_FP instead.
58 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Expand);
60 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
62 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
64 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
65 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
68 // We can handle SINT_TO_FP and FP_TO_SINT from/TO i64 even though i64
70 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
71 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
72 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
73 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
76 // Handle FP_TO_UINT by promoting the destination to a larger signed
78 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
79 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
80 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
83 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
85 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
87 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
88 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
89 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
91 setOperationAction(ISD::BIT_CONVERT, MVT::f32, Expand);
92 setOperationAction(ISD::BIT_CONVERT, MVT::i32, Expand);
95 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
97 setOperationAction(ISD::BRCONDTWOWAY , MVT::Other, Expand);
98 setOperationAction(ISD::BRTWOWAY_CC , MVT::Other, Expand);
99 setOperationAction(ISD::MEMMOVE , MVT::Other, Expand);
100 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Expand);
101 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Expand);
102 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
103 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
104 setOperationAction(ISD::SEXTLOAD , MVT::i1 , Expand);
105 setOperationAction(ISD::FREM , MVT::f64 , Expand);
106 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
107 setOperationAction(ISD::CTTZ , MVT::i8 , Expand);
108 setOperationAction(ISD::CTLZ , MVT::i8 , Expand);
109 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
110 setOperationAction(ISD::CTTZ , MVT::i16 , Expand);
111 setOperationAction(ISD::CTLZ , MVT::i16 , Expand);
112 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
113 setOperationAction(ISD::CTTZ , MVT::i32 , Expand);
114 setOperationAction(ISD::CTLZ , MVT::i32 , Expand);
115 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
118 setOperationAction(ISD::BSWAP , MVT::i32 , Expand);
119 setOperationAction(ISD::ROTL , MVT::i8 , Expand);
120 setOperationAction(ISD::ROTR , MVT::i8 , Expand);
121 setOperationAction(ISD::ROTL , MVT::i16 , Expand);
122 setOperationAction(ISD::ROTR , MVT::i16 , Expand);
123 setOperationAction(ISD::ROTL , MVT::i32 , Expand);
124 setOperationAction(ISD::ROTR , MVT::i32 , Expand);
126 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
128 setOperationAction(ISD::READIO , MVT::i1 , Expand);
129 setOperationAction(ISD::READIO , MVT::i8 , Expand);
130 setOperationAction(ISD::READIO , MVT::i16 , Expand);
131 setOperationAction(ISD::READIO , MVT::i32 , Expand);
132 setOperationAction(ISD::WRITEIO , MVT::i1 , Expand);
133 setOperationAction(ISD::WRITEIO , MVT::i8 , Expand);
134 setOperationAction(ISD::WRITEIO , MVT::i16 , Expand);
135 setOperationAction(ISD::WRITEIO , MVT::i32 , Expand);
137 // These should be promoted to a larger select which is supported.
138 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
139 setOperationAction(ISD::SELECT , MVT::i8 , Promote);
141 // X86 wants to expand cmov itself.
142 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
143 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
144 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
145 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
146 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
147 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
148 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
149 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
150 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
151 // X86 ret instruction may pop stack.
152 setOperationAction(ISD::RET , MVT::Other, Custom);
154 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
155 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
156 setOperationAction(ISD::ADD_PARTS , MVT::i32 , Custom);
157 setOperationAction(ISD::SUB_PARTS , MVT::i32 , Custom);
158 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
159 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
160 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
161 // X86 wants to expand memset / memcpy itself.
162 setOperationAction(ISD::MEMSET , MVT::Other, Custom);
163 setOperationAction(ISD::MEMCPY , MVT::Other, Custom);
166 // We don't have line number support yet.
167 setOperationAction(ISD::LOCATION, MVT::Other, Expand);
168 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
169 setOperationAction(ISD::DEBUG_LABEL, MVT::Other, Expand);
171 // Expand to the default code.
172 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
173 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
174 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Expand);
177 // Set up the FP register classes.
178 addRegisterClass(MVT::f32, X86::FR32RegisterClass);
179 addRegisterClass(MVT::f64, X86::FR64RegisterClass);
181 // SSE has no load+extend ops
182 setOperationAction(ISD::EXTLOAD, MVT::f32, Expand);
183 setOperationAction(ISD::ZEXTLOAD, MVT::f32, Expand);
185 // SSE has no i16 to fp conversion, only i32
186 setOperationAction(ISD::SINT_TO_FP, MVT::i16, Promote);
187 setOperationAction(ISD::FP_TO_SINT, MVT::i16, Promote);
189 // Expand FP_TO_UINT into a select.
190 // FIXME: We would like to use a Custom expander here eventually to do
191 // the optimal thing for SSE vs. the default expansion in the legalizer.
192 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
194 // We don't support sin/cos/sqrt/fmod
195 setOperationAction(ISD::FSIN , MVT::f64, Expand);
196 setOperationAction(ISD::FCOS , MVT::f64, Expand);
197 setOperationAction(ISD::FABS , MVT::f64, Expand);
198 setOperationAction(ISD::FNEG , MVT::f64, Expand);
199 setOperationAction(ISD::FREM , MVT::f64, Expand);
200 setOperationAction(ISD::FSIN , MVT::f32, Expand);
201 setOperationAction(ISD::FCOS , MVT::f32, Expand);
202 setOperationAction(ISD::FABS , MVT::f32, Expand);
203 setOperationAction(ISD::FNEG , MVT::f32, Expand);
204 setOperationAction(ISD::FREM , MVT::f32, Expand);
206 addLegalFPImmediate(+0.0); // xorps / xorpd
208 // Set up the FP register classes.
209 addRegisterClass(MVT::f64, X86::RFPRegisterClass);
212 setOperationAction(ISD::SINT_TO_FP, MVT::i16, Custom);
213 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
217 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
218 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
221 addLegalFPImmediate(+0.0); // FLD0
222 addLegalFPImmediate(+1.0); // FLD1
223 addLegalFPImmediate(-0.0); // FLD0/FCHS
224 addLegalFPImmediate(-1.0); // FLD1/FCHS
226 computeRegisterProperties();
228 maxStoresPerMemSet = 8; // For %llvm.memset -> sequence of stores
229 maxStoresPerMemCpy = 8; // For %llvm.memcpy -> sequence of stores
230 maxStoresPerMemMove = 8; // For %llvm.memmove -> sequence of stores
231 allowUnalignedMemoryAccesses = true; // x86 supports it!
234 std::vector<SDOperand>
235 X86TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
236 if (F.getCallingConv() == CallingConv::Fast && EnableFastCC)
237 return LowerFastCCArguments(F, DAG);
238 return LowerCCCArguments(F, DAG);
241 std::pair<SDOperand, SDOperand>
242 X86TargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy,
243 bool isVarArg, unsigned CallingConv,
245 SDOperand Callee, ArgListTy &Args,
247 assert((!isVarArg || CallingConv == CallingConv::C) &&
248 "Only C takes varargs!");
250 // If the callee is a GlobalAddress node (quite common, every direct call is)
251 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
252 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
253 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), getPointerTy());
254 else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee))
255 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy());
257 if (CallingConv == CallingConv::Fast && EnableFastCC)
258 return LowerFastCCCallTo(Chain, RetTy, isTailCall, Callee, Args, DAG);
259 return LowerCCCCallTo(Chain, RetTy, isVarArg, isTailCall, Callee, Args, DAG);
262 SDOperand X86TargetLowering::LowerReturnTo(SDOperand Chain, SDOperand Op,
265 return DAG.getNode(ISD::RET, MVT::Other, Chain, Op);
268 MVT::ValueType OpVT = Op.getValueType();
270 default: assert(0 && "Unknown type to return!");
272 Copy = DAG.getCopyToReg(Chain, X86::EAX, Op, SDOperand());
275 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op,
276 DAG.getConstant(1, MVT::i32));
277 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op,
278 DAG.getConstant(0, MVT::i32));
279 Copy = DAG.getCopyToReg(Chain, X86::EDX, Hi, SDOperand());
280 Copy = DAG.getCopyToReg(Copy, X86::EAX, Lo, Copy.getValue(1));
286 if (OpVT == MVT::f32)
287 Op = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Op);
288 std::vector<MVT::ValueType> Tys;
289 Tys.push_back(MVT::Other);
290 Tys.push_back(MVT::Flag);
291 std::vector<SDOperand> Ops;
292 Ops.push_back(Chain);
294 Copy = DAG.getNode(X86ISD::FP_SET_RESULT, Tys, Ops);
296 // Spill the value to memory and reload it into top of stack.
297 unsigned Size = MVT::getSizeInBits(OpVT)/8;
298 MachineFunction &MF = DAG.getMachineFunction();
299 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size);
300 SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
301 Chain = DAG.getNode(ISD::STORE, MVT::Other, Chain, Op,
302 StackSlot, DAG.getSrcValue(NULL));
303 std::vector<MVT::ValueType> Tys;
304 Tys.push_back(MVT::f64);
305 Tys.push_back(MVT::Other);
306 std::vector<SDOperand> Ops;
307 Ops.push_back(Chain);
308 Ops.push_back(StackSlot);
309 Ops.push_back(DAG.getValueType(OpVT));
310 Copy = DAG.getNode(X86ISD::FLD, Tys, Ops);
312 Tys.push_back(MVT::Other);
313 Tys.push_back(MVT::Flag);
315 Ops.push_back(Copy.getValue(1));
317 Copy = DAG.getNode(X86ISD::FP_SET_RESULT, Tys, Ops);
322 return DAG.getNode(X86ISD::RET_FLAG, MVT::Other,
323 Copy, DAG.getConstant(getBytesToPopOnReturn(), MVT::i16),
327 //===----------------------------------------------------------------------===//
328 // C Calling Convention implementation
329 //===----------------------------------------------------------------------===//
331 std::vector<SDOperand>
332 X86TargetLowering::LowerCCCArguments(Function &F, SelectionDAG &DAG) {
333 std::vector<SDOperand> ArgValues;
335 MachineFunction &MF = DAG.getMachineFunction();
336 MachineFrameInfo *MFI = MF.getFrameInfo();
338 // Add DAG nodes to load the arguments... On entry to a function on the X86,
339 // the stack frame looks like this:
341 // [ESP] -- return address
342 // [ESP + 4] -- first argument (leftmost lexically)
343 // [ESP + 8] -- second argument, if first argument is four bytes in size
346 unsigned ArgOffset = 0; // Frame mechanisms handle retaddr slot
347 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I) {
348 MVT::ValueType ObjectVT = getValueType(I->getType());
349 unsigned ArgIncrement = 4;
352 default: assert(0 && "Unhandled argument type!");
354 case MVT::i8: ObjSize = 1; break;
355 case MVT::i16: ObjSize = 2; break;
356 case MVT::i32: ObjSize = 4; break;
357 case MVT::i64: ObjSize = ArgIncrement = 8; break;
358 case MVT::f32: ObjSize = 4; break;
359 case MVT::f64: ObjSize = ArgIncrement = 8; break;
361 // Create the frame index object for this incoming parameter...
362 int FI = MFI->CreateFixedObject(ObjSize, ArgOffset);
364 // Create the SelectionDAG nodes corresponding to a load from this parameter
365 SDOperand FIN = DAG.getFrameIndex(FI, MVT::i32);
367 // Don't codegen dead arguments. FIXME: remove this check when we can nuke
371 ArgValue = DAG.getLoad(ObjectVT, DAG.getEntryNode(), FIN,
372 DAG.getSrcValue(NULL));
374 if (MVT::isInteger(ObjectVT))
375 ArgValue = DAG.getConstant(0, ObjectVT);
377 ArgValue = DAG.getConstantFP(0, ObjectVT);
379 ArgValues.push_back(ArgValue);
381 ArgOffset += ArgIncrement; // Move on to the next argument...
384 // If the function takes variable number of arguments, make a frame index for
385 // the start of the first vararg value... for expansion of llvm.va_start.
387 VarArgsFrameIndex = MFI->CreateFixedObject(1, ArgOffset);
388 ReturnAddrIndex = 0; // No return address slot generated yet.
389 BytesToPopOnReturn = 0; // Callee pops nothing.
390 BytesCallerReserves = ArgOffset;
392 // Finally, inform the code generator which regs we return values in.
393 switch (getValueType(F.getReturnType())) {
394 default: assert(0 && "Unknown type!");
395 case MVT::isVoid: break;
400 MF.addLiveOut(X86::EAX);
403 MF.addLiveOut(X86::EAX);
404 MF.addLiveOut(X86::EDX);
408 MF.addLiveOut(X86::ST0);
414 std::pair<SDOperand, SDOperand>
415 X86TargetLowering::LowerCCCCallTo(SDOperand Chain, const Type *RetTy,
416 bool isVarArg, bool isTailCall,
417 SDOperand Callee, ArgListTy &Args,
419 // Count how many bytes are to be pushed on the stack.
420 unsigned NumBytes = 0;
424 Chain = DAG.getNode(ISD::CALLSEQ_START, MVT::Other, Chain,
425 DAG.getConstant(0, getPointerTy()));
427 for (unsigned i = 0, e = Args.size(); i != e; ++i)
428 switch (getValueType(Args[i].second)) {
429 default: assert(0 && "Unknown value type!");
443 Chain = DAG.getNode(ISD::CALLSEQ_START, MVT::Other, Chain,
444 DAG.getConstant(NumBytes, getPointerTy()));
446 // Arguments go on the stack in reverse order, as specified by the ABI.
447 unsigned ArgOffset = 0;
448 SDOperand StackPtr = DAG.getRegister(X86::ESP, MVT::i32);
449 std::vector<SDOperand> Stores;
451 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
452 SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
453 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
455 switch (getValueType(Args[i].second)) {
456 default: assert(0 && "Unexpected ValueType for argument!");
460 // Promote the integer to 32 bits. If the input type is signed use a
461 // sign extend, otherwise use a zero extend.
462 if (Args[i].second->isSigned())
463 Args[i].first =DAG.getNode(ISD::SIGN_EXTEND, MVT::i32, Args[i].first);
465 Args[i].first =DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Args[i].first);
470 Stores.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
471 Args[i].first, PtrOff,
472 DAG.getSrcValue(NULL)));
477 Stores.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
478 Args[i].first, PtrOff,
479 DAG.getSrcValue(NULL)));
484 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, Stores);
487 std::vector<MVT::ValueType> RetVals;
488 MVT::ValueType RetTyVT = getValueType(RetTy);
489 RetVals.push_back(MVT::Other);
491 // The result values produced have to be legal. Promote the result.
493 case MVT::isVoid: break;
495 RetVals.push_back(RetTyVT);
500 RetVals.push_back(MVT::i32);
504 RetVals.push_back(MVT::f32);
506 RetVals.push_back(MVT::f64);
509 RetVals.push_back(MVT::i32);
510 RetVals.push_back(MVT::i32);
515 std::vector<MVT::ValueType> NodeTys;
516 NodeTys.push_back(MVT::Other); // Returns a chain
517 NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use.
518 std::vector<SDOperand> Ops;
519 Ops.push_back(Chain);
520 Ops.push_back(Callee);
522 // FIXME: Do not generate X86ISD::TAILCALL for now.
523 Chain = DAG.getNode(X86ISD::CALL, NodeTys, Ops);
524 SDOperand InFlag = Chain.getValue(1);
527 if (RetTyVT != MVT::isVoid) {
529 default: assert(0 && "Unknown value type to return!");
532 RetVal = DAG.getCopyFromReg(Chain, X86::AL, MVT::i8, InFlag);
533 Chain = RetVal.getValue(1);
534 if (RetTyVT == MVT::i1)
535 RetVal = DAG.getNode(ISD::TRUNCATE, MVT::i1, RetVal);
538 RetVal = DAG.getCopyFromReg(Chain, X86::AX, MVT::i16, InFlag);
539 Chain = RetVal.getValue(1);
542 RetVal = DAG.getCopyFromReg(Chain, X86::EAX, MVT::i32, InFlag);
543 Chain = RetVal.getValue(1);
546 SDOperand Lo = DAG.getCopyFromReg(Chain, X86::EAX, MVT::i32, InFlag);
547 SDOperand Hi = DAG.getCopyFromReg(Lo.getValue(1), X86::EDX, MVT::i32,
549 RetVal = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Lo, Hi);
550 Chain = Hi.getValue(1);
555 std::vector<MVT::ValueType> Tys;
556 Tys.push_back(MVT::f64);
557 Tys.push_back(MVT::Other);
558 Tys.push_back(MVT::Flag);
559 std::vector<SDOperand> Ops;
560 Ops.push_back(Chain);
561 Ops.push_back(InFlag);
562 RetVal = DAG.getNode(X86ISD::FP_GET_RESULT, Tys, Ops);
563 Chain = RetVal.getValue(1);
564 InFlag = RetVal.getValue(2);
566 // FIXME:Currently the FST is flagged to the FP_GET_RESULT. This
567 // shouldn't be necessary except for RFP cannot be live across
568 // multiple blocks. When stackifier is fixed, they can be uncoupled.
569 unsigned Size = MVT::getSizeInBits(MVT::f64)/8;
570 MachineFunction &MF = DAG.getMachineFunction();
571 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size);
572 SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
574 Tys.push_back(MVT::Other);
576 Ops.push_back(Chain);
577 Ops.push_back(RetVal);
578 Ops.push_back(StackSlot);
579 Ops.push_back(DAG.getValueType(RetTyVT));
580 Ops.push_back(InFlag);
581 Chain = DAG.getNode(X86ISD::FST, Tys, Ops);
582 RetVal = DAG.getLoad(RetTyVT, Chain, StackSlot,
583 DAG.getSrcValue(NULL));
584 Chain = RetVal.getValue(1);
587 if (RetTyVT == MVT::f32 && !X86ScalarSSE)
588 // FIXME: we would really like to remember that this FP_ROUND
589 // operation is okay to eliminate if we allow excess FP precision.
590 RetVal = DAG.getNode(ISD::FP_ROUND, MVT::f32, RetVal);
596 Chain = DAG.getNode(ISD::CALLSEQ_END, MVT::Other, Chain,
597 DAG.getConstant(NumBytes, getPointerTy()),
598 DAG.getConstant(0, getPointerTy()));
599 return std::make_pair(RetVal, Chain);
601 std::vector<SDOperand> Ops;
602 Ops.push_back(Chain);
603 Ops.push_back(Callee);
604 Ops.push_back(DAG.getConstant(NumBytes, getPointerTy()));
605 Ops.push_back(DAG.getConstant(0, getPointerTy()));
607 SDOperand TheCall = DAG.getNode(isTailCall ? X86ISD::TAILCALL : X86ISD::CALL,
612 case MVT::isVoid: break;
614 ResultVal = TheCall.getValue(1);
619 ResultVal = DAG.getNode(ISD::TRUNCATE, RetTyVT, TheCall.getValue(1));
622 // FIXME: we would really like to remember that this FP_ROUND operation is
623 // okay to eliminate if we allow excess FP precision.
624 ResultVal = DAG.getNode(ISD::FP_ROUND, MVT::f32, TheCall.getValue(1));
627 ResultVal = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, TheCall.getValue(1),
628 TheCall.getValue(2));
632 Chain = DAG.getNode(ISD::CALLSEQ_END, MVT::Other, TheCall);
633 return std::make_pair(ResultVal, Chain);
638 X86TargetLowering::LowerVAStart(SDOperand Chain, SDOperand VAListP,
639 Value *VAListV, SelectionDAG &DAG) {
640 // vastart just stores the address of the VarArgsFrameIndex slot.
641 SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, MVT::i32);
642 return DAG.getNode(ISD::STORE, MVT::Other, Chain, FR, VAListP,
643 DAG.getSrcValue(VAListV));
647 std::pair<SDOperand,SDOperand>
648 X86TargetLowering::LowerVAArg(SDOperand Chain, SDOperand VAListP,
649 Value *VAListV, const Type *ArgTy,
651 MVT::ValueType ArgVT = getValueType(ArgTy);
652 SDOperand Val = DAG.getLoad(MVT::i32, Chain,
653 VAListP, DAG.getSrcValue(VAListV));
654 SDOperand Result = DAG.getLoad(ArgVT, Chain, Val,
655 DAG.getSrcValue(NULL));
657 if (ArgVT == MVT::i32)
660 assert((ArgVT == MVT::i64 || ArgVT == MVT::f64) &&
661 "Other types should have been promoted for varargs!");
664 Val = DAG.getNode(ISD::ADD, Val.getValueType(), Val,
665 DAG.getConstant(Amt, Val.getValueType()));
666 Chain = DAG.getNode(ISD::STORE, MVT::Other, Chain,
667 Val, VAListP, DAG.getSrcValue(VAListV));
668 return std::make_pair(Result, Chain);
671 //===----------------------------------------------------------------------===//
672 // Fast Calling Convention implementation
673 //===----------------------------------------------------------------------===//
675 // The X86 'fast' calling convention passes up to two integer arguments in
676 // registers (an appropriate portion of EAX/EDX), passes arguments in C order,
677 // and requires that the callee pop its arguments off the stack (allowing proper
678 // tail calls), and has the same return value conventions as C calling convs.
680 // This calling convention always arranges for the callee pop value to be 8n+4
681 // bytes, which is needed for tail recursion elimination and stack alignment
684 // Note that this can be enhanced in the future to pass fp vals in registers
685 // (when we have a global fp allocator) and do other tricks.
688 /// AddLiveIn - This helper function adds the specified physical register to the
689 /// MachineFunction as a live in value. It also creates a corresponding virtual
691 static unsigned AddLiveIn(MachineFunction &MF, unsigned PReg,
692 TargetRegisterClass *RC) {
693 assert(RC->contains(PReg) && "Not the correct regclass!");
694 unsigned VReg = MF.getSSARegMap()->createVirtualRegister(RC);
695 MF.addLiveIn(PReg, VReg);
700 std::vector<SDOperand>
701 X86TargetLowering::LowerFastCCArguments(Function &F, SelectionDAG &DAG) {
702 std::vector<SDOperand> ArgValues;
704 MachineFunction &MF = DAG.getMachineFunction();
705 MachineFrameInfo *MFI = MF.getFrameInfo();
707 // Add DAG nodes to load the arguments... On entry to a function the stack
708 // frame looks like this:
710 // [ESP] -- return address
711 // [ESP + 4] -- first nonreg argument (leftmost lexically)
712 // [ESP + 8] -- second nonreg argument, if first argument is 4 bytes in size
714 unsigned ArgOffset = 0; // Frame mechanisms handle retaddr slot
716 // Keep track of the number of integer regs passed so far. This can be either
717 // 0 (neither EAX or EDX used), 1 (EAX is used) or 2 (EAX and EDX are both
719 unsigned NumIntRegs = 0;
721 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I) {
722 MVT::ValueType ObjectVT = getValueType(I->getType());
723 unsigned ArgIncrement = 4;
724 unsigned ObjSize = 0;
728 default: assert(0 && "Unhandled argument type!");
731 if (NumIntRegs < 2) {
732 if (!I->use_empty()) {
733 unsigned VReg = AddLiveIn(MF, NumIntRegs ? X86::DL : X86::AL,
734 X86::R8RegisterClass);
735 ArgValue = DAG.getCopyFromReg(DAG.getRoot(), VReg, MVT::i8);
736 DAG.setRoot(ArgValue.getValue(1));
737 if (ObjectVT == MVT::i1)
738 // FIXME: Should insert a assertzext here.
739 ArgValue = DAG.getNode(ISD::TRUNCATE, MVT::i1, ArgValue);
748 if (NumIntRegs < 2) {
749 if (!I->use_empty()) {
750 unsigned VReg = AddLiveIn(MF, NumIntRegs ? X86::DX : X86::AX,
751 X86::R16RegisterClass);
752 ArgValue = DAG.getCopyFromReg(DAG.getRoot(), VReg, MVT::i16);
753 DAG.setRoot(ArgValue.getValue(1));
761 if (NumIntRegs < 2) {
762 if (!I->use_empty()) {
763 unsigned VReg = AddLiveIn(MF,NumIntRegs ? X86::EDX : X86::EAX,
764 X86::R32RegisterClass);
765 ArgValue = DAG.getCopyFromReg(DAG.getRoot(), VReg, MVT::i32);
766 DAG.setRoot(ArgValue.getValue(1));
774 if (NumIntRegs == 0) {
775 if (!I->use_empty()) {
776 unsigned BotReg = AddLiveIn(MF, X86::EAX, X86::R32RegisterClass);
777 unsigned TopReg = AddLiveIn(MF, X86::EDX, X86::R32RegisterClass);
779 SDOperand Low = DAG.getCopyFromReg(DAG.getRoot(), BotReg, MVT::i32);
780 SDOperand Hi = DAG.getCopyFromReg(Low.getValue(1), TopReg, MVT::i32);
781 DAG.setRoot(Hi.getValue(1));
783 ArgValue = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Low, Hi);
787 } else if (NumIntRegs == 1) {
788 if (!I->use_empty()) {
789 unsigned BotReg = AddLiveIn(MF, X86::EDX, X86::R32RegisterClass);
790 SDOperand Low = DAG.getCopyFromReg(DAG.getRoot(), BotReg, MVT::i32);
791 DAG.setRoot(Low.getValue(1));
793 // Load the high part from memory.
794 // Create the frame index object for this incoming parameter...
795 int FI = MFI->CreateFixedObject(4, ArgOffset);
796 SDOperand FIN = DAG.getFrameIndex(FI, MVT::i32);
797 SDOperand Hi = DAG.getLoad(MVT::i32, DAG.getEntryNode(), FIN,
798 DAG.getSrcValue(NULL));
799 ArgValue = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Low, Hi);
805 ObjSize = ArgIncrement = 8;
807 case MVT::f32: ObjSize = 4; break;
808 case MVT::f64: ObjSize = ArgIncrement = 8; break;
811 // Don't codegen dead arguments. FIXME: remove this check when we can nuke
813 if (ObjSize && !I->use_empty()) {
814 // Create the frame index object for this incoming parameter...
815 int FI = MFI->CreateFixedObject(ObjSize, ArgOffset);
817 // Create the SelectionDAG nodes corresponding to a load from this
819 SDOperand FIN = DAG.getFrameIndex(FI, MVT::i32);
821 ArgValue = DAG.getLoad(ObjectVT, DAG.getEntryNode(), FIN,
822 DAG.getSrcValue(NULL));
823 } else if (ArgValue.Val == 0) {
824 if (MVT::isInteger(ObjectVT))
825 ArgValue = DAG.getConstant(0, ObjectVT);
827 ArgValue = DAG.getConstantFP(0, ObjectVT);
829 ArgValues.push_back(ArgValue);
832 ArgOffset += ArgIncrement; // Move on to the next argument.
835 // Make sure the instruction takes 8n+4 bytes to make sure the start of the
836 // arguments and the arguments after the retaddr has been pushed are aligned.
837 if ((ArgOffset & 7) == 0)
840 VarArgsFrameIndex = 0xAAAAAAA; // fastcc functions can't have varargs.
841 ReturnAddrIndex = 0; // No return address slot generated yet.
842 BytesToPopOnReturn = ArgOffset; // Callee pops all stack arguments.
843 BytesCallerReserves = 0;
845 // Finally, inform the code generator which regs we return values in.
846 switch (getValueType(F.getReturnType())) {
847 default: assert(0 && "Unknown type!");
848 case MVT::isVoid: break;
853 MF.addLiveOut(X86::EAX);
856 MF.addLiveOut(X86::EAX);
857 MF.addLiveOut(X86::EDX);
861 MF.addLiveOut(X86::ST0);
867 std::pair<SDOperand, SDOperand>
868 X86TargetLowering::LowerFastCCCallTo(SDOperand Chain, const Type *RetTy,
869 bool isTailCall, SDOperand Callee,
870 ArgListTy &Args, SelectionDAG &DAG) {
871 // Count how many bytes are to be pushed on the stack.
872 unsigned NumBytes = 0;
874 // Keep track of the number of integer regs passed so far. This can be either
875 // 0 (neither EAX or EDX used), 1 (EAX is used) or 2 (EAX and EDX are both
877 unsigned NumIntRegs = 0;
879 for (unsigned i = 0, e = Args.size(); i != e; ++i)
880 switch (getValueType(Args[i].second)) {
881 default: assert(0 && "Unknown value type!");
886 if (NumIntRegs < 2) {
895 if (NumIntRegs == 0) {
898 } else if (NumIntRegs == 1) {
910 // Make sure the instruction takes 8n+4 bytes to make sure the start of the
911 // arguments and the arguments after the retaddr has been pushed are aligned.
912 if ((NumBytes & 7) == 0)
915 Chain = DAG.getNode(ISD::CALLSEQ_START, MVT::Other, Chain,
916 DAG.getConstant(NumBytes, getPointerTy()));
918 // Arguments go on the stack in reverse order, as specified by the ABI.
919 unsigned ArgOffset = 0;
920 SDOperand StackPtr = DAG.getCopyFromReg(DAG.getEntryNode(),
923 std::vector<SDOperand> Stores;
924 std::vector<SDOperand> RegValuesToPass;
925 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
926 switch (getValueType(Args[i].second)) {
927 default: assert(0 && "Unexpected ValueType for argument!");
929 Args[i].first = DAG.getNode(ISD::ANY_EXTEND, MVT::i8, Args[i].first);
934 if (NumIntRegs < 2) {
935 RegValuesToPass.push_back(Args[i].first);
941 SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
942 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
943 Stores.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
944 Args[i].first, PtrOff,
945 DAG.getSrcValue(NULL)));
950 if (NumIntRegs < 2) { // Can pass part of it in regs?
951 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32,
952 Args[i].first, DAG.getConstant(1, MVT::i32));
953 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32,
954 Args[i].first, DAG.getConstant(0, MVT::i32));
955 RegValuesToPass.push_back(Lo);
957 if (NumIntRegs < 2) { // Pass both parts in regs?
958 RegValuesToPass.push_back(Hi);
961 // Pass the high part in memory.
962 SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
963 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
964 Stores.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
965 Hi, PtrOff, DAG.getSrcValue(NULL)));
972 SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
973 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
974 Stores.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
975 Args[i].first, PtrOff,
976 DAG.getSrcValue(NULL)));
982 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, Stores);
984 // Make sure the instruction takes 8n+4 bytes to make sure the start of the
985 // arguments and the arguments after the retaddr has been pushed are aligned.
986 if ((ArgOffset & 7) == 0)
989 std::vector<MVT::ValueType> RetVals;
990 MVT::ValueType RetTyVT = getValueType(RetTy);
992 RetVals.push_back(MVT::Other);
994 // The result values produced have to be legal. Promote the result.
996 case MVT::isVoid: break;
998 RetVals.push_back(RetTyVT);
1003 RetVals.push_back(MVT::i32);
1007 RetVals.push_back(MVT::f32);
1009 RetVals.push_back(MVT::f64);
1012 RetVals.push_back(MVT::i32);
1013 RetVals.push_back(MVT::i32);
1018 // Build a sequence of copy-to-reg nodes chained together with token chain
1019 // and flag operands which copy the outgoing args into registers.
1021 for (unsigned i = 0, e = RegValuesToPass.size(); i != e; ++i) {
1023 SDOperand RegToPass = RegValuesToPass[i];
1024 switch (RegToPass.getValueType()) {
1025 default: assert(0 && "Bad thing to pass in regs");
1027 CCReg = (i == 0) ? X86::AL : X86::DL;
1030 CCReg = (i == 0) ? X86::AX : X86::DX;
1033 CCReg = (i == 0) ? X86::EAX : X86::EDX;
1037 Chain = DAG.getCopyToReg(Chain, CCReg, RegToPass, InFlag);
1038 InFlag = Chain.getValue(1);
1041 std::vector<MVT::ValueType> NodeTys;
1042 NodeTys.push_back(MVT::Other); // Returns a chain
1043 NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use.
1044 std::vector<SDOperand> Ops;
1045 Ops.push_back(Chain);
1046 Ops.push_back(Callee);
1048 Ops.push_back(InFlag);
1050 // FIXME: Do not generate X86ISD::TAILCALL for now.
1051 Chain = DAG.getNode(X86ISD::CALL, NodeTys, Ops);
1052 InFlag = Chain.getValue(1);
1055 if (RetTyVT != MVT::isVoid) {
1057 default: assert(0 && "Unknown value type to return!");
1060 RetVal = DAG.getCopyFromReg(Chain, X86::AL, MVT::i8, InFlag);
1061 Chain = RetVal.getValue(1);
1062 if (RetTyVT == MVT::i1)
1063 RetVal = DAG.getNode(ISD::TRUNCATE, MVT::i1, RetVal);
1066 RetVal = DAG.getCopyFromReg(Chain, X86::AX, MVT::i16, InFlag);
1067 Chain = RetVal.getValue(1);
1070 RetVal = DAG.getCopyFromReg(Chain, X86::EAX, MVT::i32, InFlag);
1071 Chain = RetVal.getValue(1);
1074 SDOperand Lo = DAG.getCopyFromReg(Chain, X86::EAX, MVT::i32, InFlag);
1075 SDOperand Hi = DAG.getCopyFromReg(Lo.getValue(1), X86::EDX, MVT::i32,
1077 RetVal = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Lo, Hi);
1078 Chain = Hi.getValue(1);
1083 std::vector<MVT::ValueType> Tys;
1084 Tys.push_back(MVT::f64);
1085 Tys.push_back(MVT::Other);
1086 Tys.push_back(MVT::Flag);
1087 std::vector<SDOperand> Ops;
1088 Ops.push_back(Chain);
1089 Ops.push_back(InFlag);
1090 RetVal = DAG.getNode(X86ISD::FP_GET_RESULT, Tys, Ops);
1091 Chain = RetVal.getValue(1);
1092 InFlag = RetVal.getValue(2);
1094 // FIXME:Currently the FST is flagged to the FP_GET_RESULT. This
1095 // shouldn't be necessary except for RFP cannot be live across
1096 // multiple blocks. When stackifier is fixed, they can be uncoupled.
1097 unsigned Size = MVT::getSizeInBits(MVT::f64)/8;
1098 MachineFunction &MF = DAG.getMachineFunction();
1099 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size);
1100 SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
1102 Tys.push_back(MVT::Other);
1104 Ops.push_back(Chain);
1105 Ops.push_back(RetVal);
1106 Ops.push_back(StackSlot);
1107 Ops.push_back(DAG.getValueType(RetTyVT));
1108 Ops.push_back(InFlag);
1109 Chain = DAG.getNode(X86ISD::FST, Tys, Ops);
1110 RetVal = DAG.getLoad(RetTyVT, Chain, StackSlot,
1111 DAG.getSrcValue(NULL));
1112 Chain = RetVal.getValue(1);
1115 if (RetTyVT == MVT::f32 && !X86ScalarSSE)
1116 // FIXME: we would really like to remember that this FP_ROUND
1117 // operation is okay to eliminate if we allow excess FP precision.
1118 RetVal = DAG.getNode(ISD::FP_ROUND, MVT::f32, RetVal);
1124 Chain = DAG.getNode(ISD::CALLSEQ_END, MVT::Other, Chain,
1125 DAG.getConstant(ArgOffset, getPointerTy()),
1126 DAG.getConstant(ArgOffset, getPointerTy()));
1127 return std::make_pair(RetVal, Chain);
1129 std::vector<SDOperand> Ops;
1130 Ops.push_back(Chain);
1131 Ops.push_back(Callee);
1132 Ops.push_back(DAG.getConstant(ArgOffset, getPointerTy()));
1133 // Callee pops all arg values on the stack.
1134 Ops.push_back(DAG.getConstant(ArgOffset, getPointerTy()));
1136 // Pass register arguments as needed.
1137 Ops.insert(Ops.end(), RegValuesToPass.begin(), RegValuesToPass.end());
1139 SDOperand TheCall = DAG.getNode(isTailCall ? X86ISD::TAILCALL : X86ISD::CALL,
1141 Chain = DAG.getNode(ISD::CALLSEQ_END, MVT::Other, TheCall);
1143 SDOperand ResultVal;
1145 case MVT::isVoid: break;
1147 ResultVal = TheCall.getValue(1);
1152 ResultVal = DAG.getNode(ISD::TRUNCATE, RetTyVT, TheCall.getValue(1));
1155 // FIXME: we would really like to remember that this FP_ROUND operation is
1156 // okay to eliminate if we allow excess FP precision.
1157 ResultVal = DAG.getNode(ISD::FP_ROUND, MVT::f32, TheCall.getValue(1));
1160 ResultVal = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, TheCall.getValue(1),
1161 TheCall.getValue(2));
1165 return std::make_pair(ResultVal, Chain);
1169 SDOperand X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) {
1170 if (ReturnAddrIndex == 0) {
1171 // Set up a frame object for the return address.
1172 MachineFunction &MF = DAG.getMachineFunction();
1173 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(4, -4);
1176 return DAG.getFrameIndex(ReturnAddrIndex, MVT::i32);
1181 std::pair<SDOperand, SDOperand> X86TargetLowering::
1182 LowerFrameReturnAddress(bool isFrameAddress, SDOperand Chain, unsigned Depth,
1183 SelectionDAG &DAG) {
1185 if (Depth) // Depths > 0 not supported yet!
1186 Result = DAG.getConstant(0, getPointerTy());
1188 SDOperand RetAddrFI = getReturnAddressFrameIndex(DAG);
1189 if (!isFrameAddress)
1190 // Just load the return address
1191 Result = DAG.getLoad(MVT::i32, DAG.getEntryNode(), RetAddrFI,
1192 DAG.getSrcValue(NULL));
1194 Result = DAG.getNode(ISD::SUB, MVT::i32, RetAddrFI,
1195 DAG.getConstant(4, MVT::i32));
1197 return std::make_pair(Result, Chain);
1200 /// getCondBrOpcodeForX86CC - Returns the X86 conditional branch opcode
1201 /// which corresponds to the condition code.
1202 static unsigned getCondBrOpcodeForX86CC(unsigned X86CC) {
1204 default: assert(0 && "Unknown X86 conditional code!");
1205 case X86ISD::COND_A: return X86::JA;
1206 case X86ISD::COND_AE: return X86::JAE;
1207 case X86ISD::COND_B: return X86::JB;
1208 case X86ISD::COND_BE: return X86::JBE;
1209 case X86ISD::COND_E: return X86::JE;
1210 case X86ISD::COND_G: return X86::JG;
1211 case X86ISD::COND_GE: return X86::JGE;
1212 case X86ISD::COND_L: return X86::JL;
1213 case X86ISD::COND_LE: return X86::JLE;
1214 case X86ISD::COND_NE: return X86::JNE;
1215 case X86ISD::COND_NO: return X86::JNO;
1216 case X86ISD::COND_NP: return X86::JNP;
1217 case X86ISD::COND_NS: return X86::JNS;
1218 case X86ISD::COND_O: return X86::JO;
1219 case X86ISD::COND_P: return X86::JP;
1220 case X86ISD::COND_S: return X86::JS;
1224 /// getX86CC - do a one to one translation of a ISD::CondCode to the X86
1225 /// specific condition code. It returns a X86ISD::COND_INVALID if it cannot
1226 /// do a direct translation.
1227 static unsigned getX86CC(SDOperand CC, bool isFP) {
1228 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
1229 unsigned X86CC = X86ISD::COND_INVALID;
1231 switch (SetCCOpcode) {
1233 case ISD::SETEQ: X86CC = X86ISD::COND_E; break;
1234 case ISD::SETGT: X86CC = X86ISD::COND_G; break;
1235 case ISD::SETGE: X86CC = X86ISD::COND_GE; break;
1236 case ISD::SETLT: X86CC = X86ISD::COND_L; break;
1237 case ISD::SETLE: X86CC = X86ISD::COND_LE; break;
1238 case ISD::SETNE: X86CC = X86ISD::COND_NE; break;
1239 case ISD::SETULT: X86CC = X86ISD::COND_B; break;
1240 case ISD::SETUGT: X86CC = X86ISD::COND_A; break;
1241 case ISD::SETULE: X86CC = X86ISD::COND_BE; break;
1242 case ISD::SETUGE: X86CC = X86ISD::COND_AE; break;
1245 // On a floating point condition, the flags are set as follows:
1247 // 0 | 0 | 0 | X > Y
1248 // 0 | 0 | 1 | X < Y
1249 // 1 | 0 | 0 | X == Y
1250 // 1 | 1 | 1 | unordered
1251 switch (SetCCOpcode) {
1254 case ISD::SETEQ: X86CC = X86ISD::COND_E; break;
1256 case ISD::SETGT: X86CC = X86ISD::COND_A; break;
1258 case ISD::SETGE: X86CC = X86ISD::COND_AE; break;
1260 case ISD::SETLT: X86CC = X86ISD::COND_B; break;
1262 case ISD::SETLE: X86CC = X86ISD::COND_BE; break;
1264 case ISD::SETNE: X86CC = X86ISD::COND_NE; break;
1265 case ISD::SETUO: X86CC = X86ISD::COND_P; break;
1266 case ISD::SETO: X86CC = X86ISD::COND_NP; break;
1272 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
1273 /// code. Current x86 isa includes the following FP cmov instructions:
1274 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
1275 static bool hasFPCMov(unsigned X86CC) {
1279 case X86ISD::COND_B:
1280 case X86ISD::COND_BE:
1281 case X86ISD::COND_E:
1282 case X86ISD::COND_P:
1283 case X86ISD::COND_A:
1284 case X86ISD::COND_AE:
1285 case X86ISD::COND_NE:
1286 case X86ISD::COND_NP:
1292 X86TargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI,
1293 MachineBasicBlock *BB) {
1294 switch (MI->getOpcode()) {
1295 default: assert(false && "Unexpected instr type to insert");
1296 case X86::CMOV_FR32:
1297 case X86::CMOV_FR64: {
1298 // To "insert" a SELECT_CC instruction, we actually have to insert the diamond
1299 // control-flow pattern. The incoming instruction knows the destination vreg
1300 // to set, the condition code register to branch on, the true/false values to
1301 // select between, and a branch opcode to use.
1302 const BasicBlock *LLVM_BB = BB->getBasicBlock();
1303 ilist<MachineBasicBlock>::iterator It = BB;
1309 // cmpTY ccX, r1, r2
1311 // fallthrough --> copy0MBB
1312 MachineBasicBlock *thisMBB = BB;
1313 MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB);
1314 MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB);
1315 unsigned Opc = getCondBrOpcodeForX86CC(MI->getOperand(3).getImmedValue());
1316 BuildMI(BB, Opc, 1).addMBB(sinkMBB);
1317 MachineFunction *F = BB->getParent();
1318 F->getBasicBlockList().insert(It, copy0MBB);
1319 F->getBasicBlockList().insert(It, sinkMBB);
1320 // Update machine-CFG edges
1321 BB->addSuccessor(copy0MBB);
1322 BB->addSuccessor(sinkMBB);
1325 // %FalseValue = ...
1326 // # fallthrough to sinkMBB
1329 // Update machine-CFG edges
1330 BB->addSuccessor(sinkMBB);
1333 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
1336 BuildMI(BB, X86::PHI, 4, MI->getOperand(0).getReg())
1337 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
1338 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
1340 delete MI; // The pseudo instruction is gone now.
1344 case X86::FP_TO_INT16_IN_MEM:
1345 case X86::FP_TO_INT32_IN_MEM:
1346 case X86::FP_TO_INT64_IN_MEM: {
1347 // Change the floating point control register to use "round towards zero"
1348 // mode when truncating to an integer value.
1349 MachineFunction *F = BB->getParent();
1350 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2);
1351 addFrameReference(BuildMI(BB, X86::FNSTCW16m, 4), CWFrameIdx);
1353 // Load the old value of the high byte of the control word...
1355 F->getSSARegMap()->createVirtualRegister(X86::R16RegisterClass);
1356 addFrameReference(BuildMI(BB, X86::MOV16rm, 4, OldCW), CWFrameIdx);
1358 // Set the high part to be round to zero...
1359 addFrameReference(BuildMI(BB, X86::MOV16mi, 5), CWFrameIdx).addImm(0xC7F);
1361 // Reload the modified control word now...
1362 addFrameReference(BuildMI(BB, X86::FLDCW16m, 4), CWFrameIdx);
1364 // Restore the memory image of control word to original value
1365 addFrameReference(BuildMI(BB, X86::MOV16mr, 5), CWFrameIdx).addReg(OldCW);
1367 // Get the X86 opcode to use.
1369 switch (MI->getOpcode()) {
1370 case X86::FP_TO_INT16_IN_MEM: Opc = X86::FpIST16m; break;
1371 case X86::FP_TO_INT32_IN_MEM: Opc = X86::FpIST32m; break;
1372 case X86::FP_TO_INT64_IN_MEM: Opc = X86::FpIST64m; break;
1376 MachineOperand &Op = MI->getOperand(0);
1377 if (Op.isRegister()) {
1378 AM.BaseType = X86AddressMode::RegBase;
1379 AM.Base.Reg = Op.getReg();
1381 AM.BaseType = X86AddressMode::FrameIndexBase;
1382 AM.Base.FrameIndex = Op.getFrameIndex();
1384 Op = MI->getOperand(1);
1385 if (Op.isImmediate())
1386 AM.Scale = Op.getImmedValue();
1387 Op = MI->getOperand(2);
1388 if (Op.isImmediate())
1389 AM.IndexReg = Op.getImmedValue();
1390 Op = MI->getOperand(3);
1391 if (Op.isGlobalAddress()) {
1392 AM.GV = Op.getGlobal();
1394 AM.Disp = Op.getImmedValue();
1396 addFullAddress(BuildMI(BB, Opc, 5), AM).addReg(MI->getOperand(4).getReg());
1398 // Reload the original control word now.
1399 addFrameReference(BuildMI(BB, X86::FLDCW16m, 4), CWFrameIdx);
1401 delete MI; // The pseudo instruction is gone now.
1408 //===----------------------------------------------------------------------===//
1409 // X86 Custom Lowering Hooks
1410 //===----------------------------------------------------------------------===//
1412 /// LowerOperation - Provide custom lowering hooks for some operations.
1414 SDOperand X86TargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
1415 switch (Op.getOpcode()) {
1416 default: assert(0 && "Should not custom lower this!");
1417 case ISD::ADD_PARTS:
1418 case ISD::SUB_PARTS: {
1419 assert(Op.getNumOperands() == 4 && Op.getValueType() == MVT::i32 &&
1420 "Not an i64 add/sub!");
1421 bool isAdd = Op.getOpcode() == ISD::ADD_PARTS;
1422 std::vector<MVT::ValueType> Tys;
1423 Tys.push_back(MVT::i32);
1424 Tys.push_back(MVT::Flag);
1425 std::vector<SDOperand> Ops;
1426 Ops.push_back(Op.getOperand(0));
1427 Ops.push_back(Op.getOperand(2));
1428 SDOperand Lo = DAG.getNode(isAdd ? X86ISD::ADD_FLAG : X86ISD::SUB_FLAG,
1430 SDOperand Hi = DAG.getNode(isAdd ? X86ISD::ADC : X86ISD::SBB, MVT::i32,
1431 Op.getOperand(1), Op.getOperand(3),
1434 Tys.push_back(MVT::i32);
1435 Tys.push_back(MVT::i32);
1439 return DAG.getNode(ISD::MERGE_VALUES, Tys, Ops);
1441 case ISD::SHL_PARTS:
1442 case ISD::SRA_PARTS:
1443 case ISD::SRL_PARTS: {
1444 assert(Op.getNumOperands() == 3 && Op.getValueType() == MVT::i32 &&
1445 "Not an i64 shift!");
1446 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
1447 SDOperand ShOpLo = Op.getOperand(0);
1448 SDOperand ShOpHi = Op.getOperand(1);
1449 SDOperand ShAmt = Op.getOperand(2);
1450 SDOperand Tmp1 = isSRA ? DAG.getNode(ISD::SRA, MVT::i32, ShOpHi,
1451 DAG.getConstant(31, MVT::i32))
1452 : DAG.getConstant(0, MVT::i32);
1454 SDOperand Tmp2, Tmp3;
1455 if (Op.getOpcode() == ISD::SHL_PARTS) {
1456 Tmp2 = DAG.getNode(X86ISD::SHLD, MVT::i32, ShOpHi, ShOpLo, ShAmt);
1457 Tmp3 = DAG.getNode(ISD::SHL, MVT::i32, ShOpLo, ShAmt);
1459 Tmp2 = DAG.getNode(X86ISD::SHRD, MVT::i32, ShOpLo, ShOpHi, ShAmt);
1460 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SHL, MVT::i32, ShOpHi, ShAmt);
1463 SDOperand InFlag = DAG.getNode(X86ISD::TEST, MVT::Flag,
1464 ShAmt, DAG.getConstant(32, MVT::i8));
1467 SDOperand CC = DAG.getConstant(X86ISD::COND_NE, MVT::i8);
1469 std::vector<MVT::ValueType> Tys;
1470 Tys.push_back(MVT::i32);
1471 Tys.push_back(MVT::Flag);
1472 std::vector<SDOperand> Ops;
1473 if (Op.getOpcode() == ISD::SHL_PARTS) {
1474 Ops.push_back(Tmp2);
1475 Ops.push_back(Tmp3);
1477 Ops.push_back(InFlag);
1478 Hi = DAG.getNode(X86ISD::CMOV, Tys, Ops);
1479 InFlag = Hi.getValue(1);
1482 Ops.push_back(Tmp3);
1483 Ops.push_back(Tmp1);
1485 Ops.push_back(InFlag);
1486 Lo = DAG.getNode(X86ISD::CMOV, Tys, Ops);
1488 Ops.push_back(Tmp2);
1489 Ops.push_back(Tmp3);
1491 Ops.push_back(InFlag);
1492 Lo = DAG.getNode(X86ISD::CMOV, Tys, Ops);
1493 InFlag = Lo.getValue(1);
1496 Ops.push_back(Tmp3);
1497 Ops.push_back(Tmp1);
1499 Ops.push_back(InFlag);
1500 Hi = DAG.getNode(X86ISD::CMOV, Tys, Ops);
1504 Tys.push_back(MVT::i32);
1505 Tys.push_back(MVT::i32);
1509 return DAG.getNode(ISD::MERGE_VALUES, Tys, Ops);
1511 case ISD::SINT_TO_FP: {
1512 assert(Op.getValueType() == MVT::f64 &&
1513 Op.getOperand(0).getValueType() <= MVT::i64 &&
1514 Op.getOperand(0).getValueType() >= MVT::i16 &&
1515 "Unknown SINT_TO_FP to lower!");
1518 MVT::ValueType SrcVT = Op.getOperand(0).getValueType();
1519 unsigned Size = MVT::getSizeInBits(SrcVT)/8;
1520 MachineFunction &MF = DAG.getMachineFunction();
1521 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size);
1522 SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
1523 SDOperand Chain = DAG.getNode(ISD::STORE, MVT::Other,
1524 DAG.getEntryNode(), Op.getOperand(0),
1525 StackSlot, DAG.getSrcValue(NULL));
1528 std::vector<MVT::ValueType> Tys;
1529 Tys.push_back(MVT::f64);
1530 Tys.push_back(MVT::Flag);
1531 std::vector<SDOperand> Ops;
1532 Ops.push_back(Chain);
1533 Ops.push_back(StackSlot);
1534 Ops.push_back(DAG.getValueType(SrcVT));
1535 Result = DAG.getNode(X86ISD::FILD, Tys, Ops);
1538 case ISD::FP_TO_SINT: {
1539 assert(Op.getValueType() <= MVT::i64 && Op.getValueType() >= MVT::i16 &&
1540 Op.getOperand(0).getValueType() == MVT::f64 &&
1541 "Unknown FP_TO_SINT to lower!");
1542 // We lower FP->sint64 into FISTP64, followed by a load, all to a temporary
1544 MachineFunction &MF = DAG.getMachineFunction();
1545 unsigned MemSize = MVT::getSizeInBits(Op.getValueType())/8;
1546 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize);
1547 SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
1550 switch (Op.getValueType()) {
1551 default: assert(0 && "Invalid FP_TO_SINT to lower!");
1552 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
1553 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
1554 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
1557 // Build the FP_TO_INT*_IN_MEM
1558 std::vector<SDOperand> Ops;
1559 Ops.push_back(DAG.getEntryNode());
1560 Ops.push_back(Op.getOperand(0));
1561 Ops.push_back(StackSlot);
1562 SDOperand FIST = DAG.getNode(Opc, MVT::Other, Ops);
1565 return DAG.getLoad(Op.getValueType(), FIST, StackSlot,
1566 DAG.getSrcValue(NULL));
1568 case ISD::READCYCLECOUNTER: {
1569 std::vector<MVT::ValueType> Tys;
1570 Tys.push_back(MVT::Other);
1571 Tys.push_back(MVT::Flag);
1572 std::vector<SDOperand> Ops;
1573 Ops.push_back(Op.getOperand(0));
1574 SDOperand rd = DAG.getNode(X86ISD::RDTSC_DAG, Tys, Ops);
1576 Ops.push_back(DAG.getCopyFromReg(rd, X86::EAX, MVT::i32, rd.getValue(1)));
1577 Ops.push_back(DAG.getCopyFromReg(Ops[0].getValue(1), X86::EDX,
1578 MVT::i32, Ops[0].getValue(2)));
1579 Ops.push_back(Ops[1].getValue(1));
1580 Tys[0] = Tys[1] = MVT::i32;
1581 Tys.push_back(MVT::Other);
1582 return DAG.getNode(ISD::MERGE_VALUES, Tys, Ops);
1585 assert(Op.getValueType() == MVT::i8 && "SetCC type must be 8-bit integer");
1586 SDOperand CC = Op.getOperand(2);
1587 SDOperand Cond = DAG.getNode(X86ISD::CMP, MVT::Flag,
1588 Op.getOperand(0), Op.getOperand(1));
1589 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
1590 bool isFP = MVT::isFloatingPoint(Op.getOperand(1).getValueType());
1591 unsigned X86CC = getX86CC(CC, isFP);
1592 if (X86CC != X86ISD::COND_INVALID) {
1593 return DAG.getNode(X86ISD::SETCC, MVT::i8,
1594 DAG.getConstant(X86CC, MVT::i8), Cond);
1596 assert(isFP && "Illegal integer SetCC!");
1598 std::vector<MVT::ValueType> Tys;
1599 std::vector<SDOperand> Ops;
1600 switch (SetCCOpcode) {
1601 default: assert(false && "Illegal floating point SetCC!");
1602 case ISD::SETOEQ: { // !PF & ZF
1603 Tys.push_back(MVT::i8);
1604 Tys.push_back(MVT::Flag);
1605 Ops.push_back(DAG.getConstant(X86ISD::COND_NP, MVT::i8));
1606 Ops.push_back(Cond);
1607 SDOperand Tmp1 = DAG.getNode(X86ISD::SETCC, Tys, Ops);
1608 SDOperand Tmp2 = DAG.getNode(X86ISD::SETCC, MVT::i8,
1609 DAG.getConstant(X86ISD::COND_E, MVT::i8),
1611 return DAG.getNode(ISD::AND, MVT::i8, Tmp1, Tmp2);
1613 case ISD::SETOLT: { // !PF & CF
1614 Tys.push_back(MVT::i8);
1615 Tys.push_back(MVT::Flag);
1616 Ops.push_back(DAG.getConstant(X86ISD::COND_NP, MVT::i8));
1617 Ops.push_back(Cond);
1618 SDOperand Tmp1 = DAG.getNode(X86ISD::SETCC, Tys, Ops);
1619 SDOperand Tmp2 = DAG.getNode(X86ISD::SETCC, MVT::i8,
1620 DAG.getConstant(X86ISD::COND_B, MVT::i8),
1622 return DAG.getNode(ISD::AND, MVT::i8, Tmp1, Tmp2);
1624 case ISD::SETOLE: { // !PF & (CF || ZF)
1625 Tys.push_back(MVT::i8);
1626 Tys.push_back(MVT::Flag);
1627 Ops.push_back(DAG.getConstant(X86ISD::COND_NP, MVT::i8));
1628 Ops.push_back(Cond);
1629 SDOperand Tmp1 = DAG.getNode(X86ISD::SETCC, Tys, Ops);
1630 SDOperand Tmp2 = DAG.getNode(X86ISD::SETCC, MVT::i8,
1631 DAG.getConstant(X86ISD::COND_BE, MVT::i8),
1633 return DAG.getNode(ISD::AND, MVT::i8, Tmp1, Tmp2);
1635 case ISD::SETUGT: { // PF | (!ZF & !CF)
1636 Tys.push_back(MVT::i8);
1637 Tys.push_back(MVT::Flag);
1638 Ops.push_back(DAG.getConstant(X86ISD::COND_P, MVT::i8));
1639 Ops.push_back(Cond);
1640 SDOperand Tmp1 = DAG.getNode(X86ISD::SETCC, Tys, Ops);
1641 SDOperand Tmp2 = DAG.getNode(X86ISD::SETCC, MVT::i8,
1642 DAG.getConstant(X86ISD::COND_A, MVT::i8),
1644 return DAG.getNode(ISD::OR, MVT::i8, Tmp1, Tmp2);
1646 case ISD::SETUGE: { // PF | !CF
1647 Tys.push_back(MVT::i8);
1648 Tys.push_back(MVT::Flag);
1649 Ops.push_back(DAG.getConstant(X86ISD::COND_P, MVT::i8));
1650 Ops.push_back(Cond);
1651 SDOperand Tmp1 = DAG.getNode(X86ISD::SETCC, Tys, Ops);
1652 SDOperand Tmp2 = DAG.getNode(X86ISD::SETCC, MVT::i8,
1653 DAG.getConstant(X86ISD::COND_AE, MVT::i8),
1655 return DAG.getNode(ISD::OR, MVT::i8, Tmp1, Tmp2);
1657 case ISD::SETUNE: { // PF | !ZF
1658 Tys.push_back(MVT::i8);
1659 Tys.push_back(MVT::Flag);
1660 Ops.push_back(DAG.getConstant(X86ISD::COND_P, MVT::i8));
1661 Ops.push_back(Cond);
1662 SDOperand Tmp1 = DAG.getNode(X86ISD::SETCC, Tys, Ops);
1663 SDOperand Tmp2 = DAG.getNode(X86ISD::SETCC, MVT::i8,
1664 DAG.getConstant(X86ISD::COND_NE, MVT::i8),
1666 return DAG.getNode(ISD::OR, MVT::i8, Tmp1, Tmp2);
1672 MVT::ValueType VT = Op.getValueType();
1673 bool isFP = MVT::isFloatingPoint(VT);
1674 bool isFPStack = isFP && (X86Vector < SSE2);
1675 bool isFPSSE = isFP && (X86Vector >= SSE2);
1676 bool addTest = false;
1677 SDOperand Op0 = Op.getOperand(0);
1679 if (Op0.getOpcode() == X86ISD::SETCC) {
1680 // If condition flag is set by a X86ISD::CMP, then make a copy of it
1681 // (since flag operand cannot be shared). If the X86ISD::SETCC does not
1682 // have another use it will be eliminated.
1683 // If the X86ISD::SETCC has more than one use, then it's probably better
1684 // to use a test instead of duplicating the X86ISD::CMP (for register
1685 // pressure reason).
1686 if (Op0.hasOneUse() && Op0.getOperand(1).getOpcode() == X86ISD::CMP) {
1687 CC = Op0.getOperand(0);
1688 Cond = Op0.getOperand(1);
1690 isFPStack && !hasFPCMov(cast<ConstantSDNode>(CC)->getSignExtended());
1693 } else if (Op0.getOpcode() == ISD::SETCC) {
1694 CC = Op0.getOperand(2);
1695 bool isFP = MVT::isFloatingPoint(Op0.getOperand(1).getValueType());
1696 unsigned X86CC = getX86CC(CC, isFP);
1697 CC = DAG.getConstant(X86CC, MVT::i8);
1698 Cond = DAG.getNode(X86ISD::CMP, MVT::Flag,
1699 Op0.getOperand(0), Op0.getOperand(1));
1705 CC = DAG.getConstant(X86ISD::COND_NE, MVT::i8);
1706 Cond = DAG.getNode(X86ISD::TEST, MVT::Flag, Op0, Op0);
1709 std::vector<MVT::ValueType> Tys;
1710 Tys.push_back(Op.getValueType());
1711 Tys.push_back(MVT::Flag);
1712 std::vector<SDOperand> Ops;
1713 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
1714 // condition is true.
1715 Ops.push_back(Op.getOperand(2));
1716 Ops.push_back(Op.getOperand(1));
1718 Ops.push_back(Cond);
1719 return DAG.getNode(X86ISD::CMOV, Tys, Ops);
1722 bool addTest = false;
1723 SDOperand Cond = Op.getOperand(1);
1724 SDOperand Dest = Op.getOperand(2);
1726 if (Cond.getOpcode() == X86ISD::SETCC) {
1727 // If condition flag is set by a X86ISD::CMP, then make a copy of it
1728 // (since flag operand cannot be shared). If the X86ISD::SETCC does not
1729 // have another use it will be eliminated.
1730 // If the X86ISD::SETCC has more than one use, then it's probably better
1731 // to use a test instead of duplicating the X86ISD::CMP (for register
1732 // pressure reason).
1733 if (Cond.hasOneUse() && Cond.getOperand(1).getOpcode() == X86ISD::CMP) {
1734 CC = Cond.getOperand(0);
1735 Cond = DAG.getNode(X86ISD::CMP, MVT::Flag,
1736 Cond.getOperand(1).getOperand(0),
1737 Cond.getOperand(1).getOperand(1));
1740 } else if (Cond.getOpcode() == ISD::SETCC) {
1741 CC = Cond.getOperand(2);
1742 bool isFP = MVT::isFloatingPoint(Cond.getOperand(1).getValueType());
1743 unsigned X86CC = getX86CC(CC, isFP);
1744 CC = DAG.getConstant(X86CC, MVT::i8);
1745 Cond = DAG.getNode(X86ISD::CMP, MVT::Flag,
1746 Cond.getOperand(0), Cond.getOperand(1));
1751 CC = DAG.getConstant(X86ISD::COND_NE, MVT::i8);
1752 Cond = DAG.getNode(X86ISD::TEST, MVT::Flag, Cond, Cond);
1754 return DAG.getNode(X86ISD::BRCOND, Op.getValueType(),
1755 Op.getOperand(0), Op.getOperand(2), CC, Cond);
1758 // Can only be return void.
1759 return DAG.getNode(X86ISD::RET_FLAG, MVT::Other, Op.getOperand(0),
1760 DAG.getConstant(getBytesToPopOnReturn(), MVT::i16));
1764 SDOperand Chain = Op.getOperand(0);
1766 (unsigned)cast<ConstantSDNode>(Op.getOperand(4))->getValue();
1767 if (Align == 0) Align = 1;
1771 if (ConstantSDNode *ValC = dyn_cast<ConstantSDNode>(Op.getOperand(2))) {
1773 unsigned Val = ValC->getValue() & 255;
1775 // If the value is a constant, then we can potentially use larger sets.
1776 switch (Align & 3) {
1777 case 2: // WORD aligned
1779 if (ConstantSDNode *I = dyn_cast<ConstantSDNode>(Op.getOperand(3)))
1780 Count = DAG.getConstant(I->getValue() / 2, MVT::i32);
1782 Count = DAG.getNode(ISD::SRL, MVT::i32, Op.getOperand(3),
1783 DAG.getConstant(1, MVT::i8));
1784 Val = (Val << 8) | Val;
1787 case 0: // DWORD aligned
1789 if (ConstantSDNode *I = dyn_cast<ConstantSDNode>(Op.getOperand(3)))
1790 Count = DAG.getConstant(I->getValue() / 4, MVT::i32);
1792 Count = DAG.getNode(ISD::SRL, MVT::i32, Op.getOperand(3),
1793 DAG.getConstant(2, MVT::i8));
1794 Val = (Val << 8) | Val;
1795 Val = (Val << 16) | Val;
1798 default: // Byte aligned
1800 Count = Op.getOperand(3);
1805 Chain = DAG.getCopyToReg(Chain, ValReg, DAG.getConstant(Val, AVT),
1807 InFlag = Chain.getValue(1);
1810 Count = Op.getOperand(3);
1811 Chain = DAG.getCopyToReg(Chain, X86::AL, Op.getOperand(2), InFlag);
1812 InFlag = Chain.getValue(1);
1815 Chain = DAG.getCopyToReg(Chain, X86::ECX, Count, InFlag);
1816 InFlag = Chain.getValue(1);
1817 Chain = DAG.getCopyToReg(Chain, X86::EDI, Op.getOperand(1), InFlag);
1818 InFlag = Chain.getValue(1);
1820 return DAG.getNode(X86ISD::REP_STOS, MVT::Other, Chain,
1821 DAG.getValueType(AVT), InFlag);
1824 SDOperand Chain = Op.getOperand(0);
1826 (unsigned)cast<ConstantSDNode>(Op.getOperand(4))->getValue();
1827 if (Align == 0) Align = 1;
1831 switch (Align & 3) {
1832 case 2: // WORD aligned
1834 if (ConstantSDNode *I = dyn_cast<ConstantSDNode>(Op.getOperand(3)))
1835 Count = DAG.getConstant(I->getValue() / 2, MVT::i32);
1837 Count = DAG.getNode(ISD::SRL, MVT::i32, Op.getOperand(3),
1838 DAG.getConstant(1, MVT::i8));
1840 case 0: // DWORD aligned
1842 if (ConstantSDNode *I = dyn_cast<ConstantSDNode>(Op.getOperand(3)))
1843 Count = DAG.getConstant(I->getValue() / 4, MVT::i32);
1845 Count = DAG.getNode(ISD::SRL, MVT::i32, Op.getOperand(3),
1846 DAG.getConstant(2, MVT::i8));
1848 default: // Byte aligned
1850 Count = Op.getOperand(3);
1855 Chain = DAG.getCopyToReg(Chain, X86::ECX, Count, InFlag);
1856 InFlag = Chain.getValue(1);
1857 Chain = DAG.getCopyToReg(Chain, X86::EDI, Op.getOperand(1), InFlag);
1858 InFlag = Chain.getValue(1);
1859 Chain = DAG.getCopyToReg(Chain, X86::ESI, Op.getOperand(2), InFlag);
1860 InFlag = Chain.getValue(1);
1862 return DAG.getNode(X86ISD::REP_MOVS, MVT::Other, Chain,
1863 DAG.getValueType(AVT), InFlag);
1865 case ISD::GlobalAddress: {
1867 GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
1868 // For Darwin, external and weak symbols are indirect, so we want to load
1869 // the value at address GV, not the value of GV itself. This means that
1870 // the GlobalAddress must be in the base or index register of the address,
1871 // not the GV offset field.
1872 if (getTargetMachine().
1873 getSubtarget<X86Subtarget>().getIndirectExternAndWeakGlobals() &&
1874 (GV->hasWeakLinkage() || GV->isExternal()))
1875 Result = DAG.getLoad(MVT::i32, DAG.getEntryNode(),
1876 DAG.getTargetGlobalAddress(GV, getPointerTy()),
1877 DAG.getSrcValue(NULL));
1883 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
1885 default: return NULL;
1886 case X86ISD::ADD_FLAG: return "X86ISD::ADD_FLAG";
1887 case X86ISD::SUB_FLAG: return "X86ISD::SUB_FLAG";
1888 case X86ISD::ADC: return "X86ISD::ADC";
1889 case X86ISD::SBB: return "X86ISD::SBB";
1890 case X86ISD::SHLD: return "X86ISD::SHLD";
1891 case X86ISD::SHRD: return "X86ISD::SHRD";
1892 case X86ISD::FILD: return "X86ISD::FILD";
1893 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
1894 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
1895 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
1896 case X86ISD::FLD: return "X86ISD::FLD";
1897 case X86ISD::FST: return "X86ISD::FST";
1898 case X86ISD::FP_GET_RESULT: return "X86ISD::FP_GET_RESULT";
1899 case X86ISD::FP_SET_RESULT: return "X86ISD::FP_SET_RESULT";
1900 case X86ISD::CALL: return "X86ISD::CALL";
1901 case X86ISD::TAILCALL: return "X86ISD::TAILCALL";
1902 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
1903 case X86ISD::CMP: return "X86ISD::CMP";
1904 case X86ISD::TEST: return "X86ISD::TEST";
1905 case X86ISD::SETCC: return "X86ISD::SETCC";
1906 case X86ISD::CMOV: return "X86ISD::CMOV";
1907 case X86ISD::BRCOND: return "X86ISD::BRCOND";
1908 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
1909 case X86ISD::REP_STOS: return "X86ISD::RET_STOS";
1910 case X86ISD::REP_MOVS: return "X86ISD::RET_MOVS";
1914 bool X86TargetLowering::isMaskedValueZeroForTargetNode(const SDOperand &Op,
1915 uint64_t Mask) const {
1917 unsigned Opc = Op.getOpcode();
1921 assert(Opc >= ISD::BUILTIN_OP_END && "Expected a target specific node");
1923 case X86ISD::SETCC: return (Mask & 1) == 0;