1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "x86-isel"
16 #include "X86ISelLowering.h"
17 #include "Utils/X86ShuffleDecode.h"
19 #include "X86CallingConv.h"
20 #include "X86InstrBuilder.h"
21 #include "X86TargetMachine.h"
22 #include "X86TargetObjectFile.h"
23 #include "llvm/ADT/SmallSet.h"
24 #include "llvm/ADT/Statistic.h"
25 #include "llvm/ADT/StringExtras.h"
26 #include "llvm/ADT/VariadicFunction.h"
27 #include "llvm/CodeGen/IntrinsicLowering.h"
28 #include "llvm/CodeGen/MachineFrameInfo.h"
29 #include "llvm/CodeGen/MachineFunction.h"
30 #include "llvm/CodeGen/MachineInstrBuilder.h"
31 #include "llvm/CodeGen/MachineJumpTableInfo.h"
32 #include "llvm/CodeGen/MachineModuleInfo.h"
33 #include "llvm/CodeGen/MachineRegisterInfo.h"
34 #include "llvm/IR/CallingConv.h"
35 #include "llvm/IR/Constants.h"
36 #include "llvm/IR/DerivedTypes.h"
37 #include "llvm/IR/Function.h"
38 #include "llvm/IR/GlobalAlias.h"
39 #include "llvm/IR/GlobalVariable.h"
40 #include "llvm/IR/Instructions.h"
41 #include "llvm/IR/Intrinsics.h"
42 #include "llvm/IR/LLVMContext.h"
43 #include "llvm/MC/MCAsmInfo.h"
44 #include "llvm/MC/MCContext.h"
45 #include "llvm/MC/MCExpr.h"
46 #include "llvm/MC/MCSymbol.h"
47 #include "llvm/Support/CallSite.h"
48 #include "llvm/Support/Debug.h"
49 #include "llvm/Support/ErrorHandling.h"
50 #include "llvm/Support/MathExtras.h"
51 #include "llvm/Target/TargetOptions.h"
56 STATISTIC(NumTailCalls, "Number of tail calls");
58 // Forward declarations.
59 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
62 static SDValue ExtractSubVector(SDValue Vec, unsigned IdxVal,
63 SelectionDAG &DAG, SDLoc dl,
64 unsigned vectorWidth) {
65 assert((vectorWidth == 128 || vectorWidth == 256) &&
66 "Unsupported vector width");
67 EVT VT = Vec.getValueType();
68 EVT ElVT = VT.getVectorElementType();
69 unsigned Factor = VT.getSizeInBits()/vectorWidth;
70 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT,
71 VT.getVectorNumElements()/Factor);
73 // Extract from UNDEF is UNDEF.
74 if (Vec.getOpcode() == ISD::UNDEF)
75 return DAG.getUNDEF(ResultVT);
77 // Extract the relevant vectorWidth bits. Generate an EXTRACT_SUBVECTOR
78 unsigned ElemsPerChunk = vectorWidth / ElVT.getSizeInBits();
80 // This is the index of the first element of the vectorWidth-bit chunk
82 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits()) / vectorWidth)
85 // If the input is a buildvector just emit a smaller one.
86 if (Vec.getOpcode() == ISD::BUILD_VECTOR)
87 return DAG.getNode(ISD::BUILD_VECTOR, dl, ResultVT,
88 Vec->op_begin()+NormalizedIdxVal, ElemsPerChunk);
90 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal);
91 SDValue Result = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec,
97 /// Generate a DAG to grab 128-bits from a vector > 128 bits. This
98 /// sets things up to match to an AVX VEXTRACTF128 / VEXTRACTI128
99 /// or AVX-512 VEXTRACTF32x4 / VEXTRACTI32x4
100 /// instructions or a simple subregister reference. Idx is an index in the
101 /// 128 bits we want. It need not be aligned to a 128-bit bounday. That makes
102 /// lowering EXTRACT_VECTOR_ELT operations easier.
103 static SDValue Extract128BitVector(SDValue Vec, unsigned IdxVal,
104 SelectionDAG &DAG, SDLoc dl) {
105 assert((Vec.getValueType().is256BitVector() ||
106 Vec.getValueType().is512BitVector()) && "Unexpected vector size!");
107 return ExtractSubVector(Vec, IdxVal, DAG, dl, 128);
110 /// Generate a DAG to grab 256-bits from a 512-bit vector.
111 static SDValue Extract256BitVector(SDValue Vec, unsigned IdxVal,
112 SelectionDAG &DAG, SDLoc dl) {
113 assert(Vec.getValueType().is512BitVector() && "Unexpected vector size!");
114 return ExtractSubVector(Vec, IdxVal, DAG, dl, 256);
117 static SDValue InsertSubVector(SDValue Result, SDValue Vec,
118 unsigned IdxVal, SelectionDAG &DAG,
119 SDLoc dl, unsigned vectorWidth) {
120 assert((vectorWidth == 128 || vectorWidth == 256) &&
121 "Unsupported vector width");
122 // Inserting UNDEF is Result
123 if (Vec.getOpcode() == ISD::UNDEF)
125 EVT VT = Vec.getValueType();
126 EVT ElVT = VT.getVectorElementType();
127 EVT ResultVT = Result.getValueType();
129 // Insert the relevant vectorWidth bits.
130 unsigned ElemsPerChunk = vectorWidth/ElVT.getSizeInBits();
132 // This is the index of the first element of the vectorWidth-bit chunk
134 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits())/vectorWidth)
137 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal);
138 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec,
141 /// Generate a DAG to put 128-bits into a vector > 128 bits. This
142 /// sets things up to match to an AVX VINSERTF128/VINSERTI128 or
143 /// AVX-512 VINSERTF32x4/VINSERTI32x4 instructions or a
144 /// simple superregister reference. Idx is an index in the 128 bits
145 /// we want. It need not be aligned to a 128-bit bounday. That makes
146 /// lowering INSERT_VECTOR_ELT operations easier.
147 static SDValue Insert128BitVector(SDValue Result, SDValue Vec,
148 unsigned IdxVal, SelectionDAG &DAG,
150 assert(Vec.getValueType().is128BitVector() && "Unexpected vector size!");
151 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 128);
154 static SDValue Insert256BitVector(SDValue Result, SDValue Vec,
155 unsigned IdxVal, SelectionDAG &DAG,
157 assert(Vec.getValueType().is256BitVector() && "Unexpected vector size!");
158 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 256);
161 /// Concat two 128-bit vectors into a 256 bit vector using VINSERTF128
162 /// instructions. This is used because creating CONCAT_VECTOR nodes of
163 /// BUILD_VECTORS returns a larger BUILD_VECTOR while we're trying to lower
164 /// large BUILD_VECTORS.
165 static SDValue Concat128BitVectors(SDValue V1, SDValue V2, EVT VT,
166 unsigned NumElems, SelectionDAG &DAG,
168 SDValue V = Insert128BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
169 return Insert128BitVector(V, V2, NumElems/2, DAG, dl);
172 static SDValue Concat256BitVectors(SDValue V1, SDValue V2, EVT VT,
173 unsigned NumElems, SelectionDAG &DAG,
175 SDValue V = Insert256BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
176 return Insert256BitVector(V, V2, NumElems/2, DAG, dl);
179 static TargetLoweringObjectFile *createTLOF(X86TargetMachine &TM) {
180 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
181 bool is64Bit = Subtarget->is64Bit();
183 if (Subtarget->isTargetEnvMacho()) {
185 return new X86_64MachoTargetObjectFile();
186 return new TargetLoweringObjectFileMachO();
189 if (Subtarget->isTargetLinux())
190 return new X86LinuxTargetObjectFile();
191 if (Subtarget->isTargetELF())
192 return new TargetLoweringObjectFileELF();
193 if (Subtarget->isTargetCOFF() && !Subtarget->isTargetEnvMacho())
194 return new TargetLoweringObjectFileCOFF();
195 llvm_unreachable("unknown subtarget type");
198 X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
199 : TargetLowering(TM, createTLOF(TM)) {
200 Subtarget = &TM.getSubtarget<X86Subtarget>();
201 X86ScalarSSEf64 = Subtarget->hasSSE2();
202 X86ScalarSSEf32 = Subtarget->hasSSE1();
203 TD = getDataLayout();
205 resetOperationActions();
208 void X86TargetLowering::resetOperationActions() {
209 const TargetMachine &TM = getTargetMachine();
210 static bool FirstTimeThrough = true;
212 // If none of the target options have changed, then we don't need to reset the
213 // operation actions.
214 if (!FirstTimeThrough && TO == TM.Options) return;
216 if (!FirstTimeThrough) {
217 // Reinitialize the actions.
219 FirstTimeThrough = false;
224 // Set up the TargetLowering object.
225 static const MVT IntVTs[] = { MVT::i8, MVT::i16, MVT::i32, MVT::i64 };
227 // X86 is weird, it always uses i8 for shift amounts and setcc results.
228 setBooleanContents(ZeroOrOneBooleanContent);
229 // X86-SSE is even stranger. It uses -1 or 0 for vector masks.
230 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
232 // For 64-bit since we have so many registers use the ILP scheduler, for
233 // 32-bit code use the register pressure specific scheduling.
234 // For Atom, always use ILP scheduling.
235 if (Subtarget->isAtom())
236 setSchedulingPreference(Sched::ILP);
237 else if (Subtarget->is64Bit())
238 setSchedulingPreference(Sched::ILP);
240 setSchedulingPreference(Sched::RegPressure);
241 const X86RegisterInfo *RegInfo =
242 static_cast<const X86RegisterInfo*>(TM.getRegisterInfo());
243 setStackPointerRegisterToSaveRestore(RegInfo->getStackRegister());
245 // Bypass expensive divides on Atom when compiling with O2
246 if (Subtarget->hasSlowDivide() && TM.getOptLevel() >= CodeGenOpt::Default) {
247 addBypassSlowDiv(32, 8);
248 if (Subtarget->is64Bit())
249 addBypassSlowDiv(64, 16);
252 if (Subtarget->isTargetWindows() && !Subtarget->isTargetCygMing()) {
253 // Setup Windows compiler runtime calls.
254 setLibcallName(RTLIB::SDIV_I64, "_alldiv");
255 setLibcallName(RTLIB::UDIV_I64, "_aulldiv");
256 setLibcallName(RTLIB::SREM_I64, "_allrem");
257 setLibcallName(RTLIB::UREM_I64, "_aullrem");
258 setLibcallName(RTLIB::MUL_I64, "_allmul");
259 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall);
260 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall);
261 setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::X86_StdCall);
262 setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::X86_StdCall);
263 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::X86_StdCall);
265 // The _ftol2 runtime function has an unusual calling conv, which
266 // is modeled by a special pseudo-instruction.
267 setLibcallName(RTLIB::FPTOUINT_F64_I64, 0);
268 setLibcallName(RTLIB::FPTOUINT_F32_I64, 0);
269 setLibcallName(RTLIB::FPTOUINT_F64_I32, 0);
270 setLibcallName(RTLIB::FPTOUINT_F32_I32, 0);
273 if (Subtarget->isTargetDarwin()) {
274 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
275 setUseUnderscoreSetJmp(false);
276 setUseUnderscoreLongJmp(false);
277 } else if (Subtarget->isTargetMingw()) {
278 // MS runtime is weird: it exports _setjmp, but longjmp!
279 setUseUnderscoreSetJmp(true);
280 setUseUnderscoreLongJmp(false);
282 setUseUnderscoreSetJmp(true);
283 setUseUnderscoreLongJmp(true);
286 // Set up the register classes.
287 addRegisterClass(MVT::i8, &X86::GR8RegClass);
288 addRegisterClass(MVT::i16, &X86::GR16RegClass);
289 addRegisterClass(MVT::i32, &X86::GR32RegClass);
290 if (Subtarget->is64Bit())
291 addRegisterClass(MVT::i64, &X86::GR64RegClass);
293 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
295 // We don't accept any truncstore of integer registers.
296 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
297 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
298 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
299 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
300 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
301 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
303 // SETOEQ and SETUNE require checking two conditions.
304 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
305 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
306 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
307 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
308 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
309 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
311 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
313 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
314 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
315 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
317 if (Subtarget->is64Bit()) {
318 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
319 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
320 } else if (!TM.Options.UseSoftFloat) {
321 // We have an algorithm for SSE2->double, and we turn this into a
322 // 64-bit FILD followed by conditional FADD for other targets.
323 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
324 // We have an algorithm for SSE2, and we turn this into a 64-bit
325 // FILD for other targets.
326 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
329 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
331 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
332 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
334 if (!TM.Options.UseSoftFloat) {
335 // SSE has no i16 to fp conversion, only i32
336 if (X86ScalarSSEf32) {
337 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
338 // f32 and f64 cases are Legal, f80 case is not
339 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
341 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
342 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
345 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
346 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
349 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
350 // are Legal, f80 is custom lowered.
351 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
352 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
354 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
356 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
357 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
359 if (X86ScalarSSEf32) {
360 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
361 // f32 and f64 cases are Legal, f80 case is not
362 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
364 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
365 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
368 // Handle FP_TO_UINT by promoting the destination to a larger signed
370 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
371 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
372 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
374 if (Subtarget->is64Bit()) {
375 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
376 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
377 } else if (!TM.Options.UseSoftFloat) {
378 // Since AVX is a superset of SSE3, only check for SSE here.
379 if (Subtarget->hasSSE1() && !Subtarget->hasSSE3())
380 // Expand FP_TO_UINT into a select.
381 // FIXME: We would like to use a Custom expander here eventually to do
382 // the optimal thing for SSE vs. the default expansion in the legalizer.
383 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
385 // With SSE3 we can use fisttpll to convert to a signed i64; without
386 // SSE, we're stuck with a fistpll.
387 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
390 if (isTargetFTOL()) {
391 // Use the _ftol2 runtime function, which has a pseudo-instruction
392 // to handle its weird calling convention.
393 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Custom);
396 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
397 if (!X86ScalarSSEf64) {
398 setOperationAction(ISD::BITCAST , MVT::f32 , Expand);
399 setOperationAction(ISD::BITCAST , MVT::i32 , Expand);
400 if (Subtarget->is64Bit()) {
401 setOperationAction(ISD::BITCAST , MVT::f64 , Expand);
402 // Without SSE, i64->f64 goes through memory.
403 setOperationAction(ISD::BITCAST , MVT::i64 , Expand);
407 // Scalar integer divide and remainder are lowered to use operations that
408 // produce two results, to match the available instructions. This exposes
409 // the two-result form to trivial CSE, which is able to combine x/y and x%y
410 // into a single instruction.
412 // Scalar integer multiply-high is also lowered to use two-result
413 // operations, to match the available instructions. However, plain multiply
414 // (low) operations are left as Legal, as there are single-result
415 // instructions for this in x86. Using the two-result multiply instructions
416 // when both high and low results are needed must be arranged by dagcombine.
417 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
419 setOperationAction(ISD::MULHS, VT, Expand);
420 setOperationAction(ISD::MULHU, VT, Expand);
421 setOperationAction(ISD::SDIV, VT, Expand);
422 setOperationAction(ISD::UDIV, VT, Expand);
423 setOperationAction(ISD::SREM, VT, Expand);
424 setOperationAction(ISD::UREM, VT, Expand);
426 // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences.
427 setOperationAction(ISD::ADDC, VT, Custom);
428 setOperationAction(ISD::ADDE, VT, Custom);
429 setOperationAction(ISD::SUBC, VT, Custom);
430 setOperationAction(ISD::SUBE, VT, Custom);
433 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
434 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
435 setOperationAction(ISD::BR_CC , MVT::f32, Expand);
436 setOperationAction(ISD::BR_CC , MVT::f64, Expand);
437 setOperationAction(ISD::BR_CC , MVT::f80, Expand);
438 setOperationAction(ISD::BR_CC , MVT::i8, Expand);
439 setOperationAction(ISD::BR_CC , MVT::i16, Expand);
440 setOperationAction(ISD::BR_CC , MVT::i32, Expand);
441 setOperationAction(ISD::BR_CC , MVT::i64, Expand);
442 setOperationAction(ISD::SELECT_CC , MVT::Other, Expand);
443 if (Subtarget->is64Bit())
444 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
445 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
446 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
447 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
448 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
449 setOperationAction(ISD::FREM , MVT::f32 , Expand);
450 setOperationAction(ISD::FREM , MVT::f64 , Expand);
451 setOperationAction(ISD::FREM , MVT::f80 , Expand);
452 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
454 // Promote the i8 variants and force them on up to i32 which has a shorter
456 setOperationAction(ISD::CTTZ , MVT::i8 , Promote);
457 AddPromotedToType (ISD::CTTZ , MVT::i8 , MVT::i32);
458 setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i8 , Promote);
459 AddPromotedToType (ISD::CTTZ_ZERO_UNDEF , MVT::i8 , MVT::i32);
460 if (Subtarget->hasBMI()) {
461 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16 , Expand);
462 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32 , Expand);
463 if (Subtarget->is64Bit())
464 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
466 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
467 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
468 if (Subtarget->is64Bit())
469 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
472 if (Subtarget->hasLZCNT()) {
473 // When promoting the i8 variants, force them to i32 for a shorter
475 setOperationAction(ISD::CTLZ , MVT::i8 , Promote);
476 AddPromotedToType (ISD::CTLZ , MVT::i8 , MVT::i32);
477 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Promote);
478 AddPromotedToType (ISD::CTLZ_ZERO_UNDEF, MVT::i8 , MVT::i32);
479 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Expand);
480 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Expand);
481 if (Subtarget->is64Bit())
482 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
484 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
485 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
486 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
487 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Custom);
488 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Custom);
489 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Custom);
490 if (Subtarget->is64Bit()) {
491 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
492 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom);
496 if (Subtarget->hasPOPCNT()) {
497 setOperationAction(ISD::CTPOP , MVT::i8 , Promote);
499 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
500 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
501 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
502 if (Subtarget->is64Bit())
503 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
506 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
507 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
509 // These should be promoted to a larger select which is supported.
510 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
511 // X86 wants to expand cmov itself.
512 setOperationAction(ISD::SELECT , MVT::i8 , Custom);
513 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
514 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
515 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
516 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
517 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
518 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
519 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
520 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
521 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
522 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
523 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
524 if (Subtarget->is64Bit()) {
525 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
526 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
528 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
529 // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support
530 // SjLj exception handling but a light-weight setjmp/longjmp replacement to
531 // support continuation, user-level threading, and etc.. As a result, no
532 // other SjLj exception interfaces are implemented and please don't build
533 // your own exception handling based on them.
534 // LLVM/Clang supports zero-cost DWARF exception handling.
535 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
536 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
539 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
540 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
541 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
542 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
543 if (Subtarget->is64Bit())
544 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
545 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
546 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom);
547 if (Subtarget->is64Bit()) {
548 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
549 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
550 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
551 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
552 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom);
554 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
555 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
556 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
557 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
558 if (Subtarget->is64Bit()) {
559 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
560 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
561 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
564 if (Subtarget->hasSSE1())
565 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
567 setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom);
569 // Expand certain atomics
570 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
572 setOperationAction(ISD::ATOMIC_CMP_SWAP, VT, Custom);
573 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom);
574 setOperationAction(ISD::ATOMIC_STORE, VT, Custom);
577 if (!Subtarget->is64Bit()) {
578 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Custom);
579 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i64, Custom);
580 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom);
581 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i64, Custom);
582 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i64, Custom);
583 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i64, Custom);
584 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i64, Custom);
585 setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Custom);
586 setOperationAction(ISD::ATOMIC_LOAD_MAX, MVT::i64, Custom);
587 setOperationAction(ISD::ATOMIC_LOAD_MIN, MVT::i64, Custom);
588 setOperationAction(ISD::ATOMIC_LOAD_UMAX, MVT::i64, Custom);
589 setOperationAction(ISD::ATOMIC_LOAD_UMIN, MVT::i64, Custom);
592 if (Subtarget->hasCmpxchg16b()) {
593 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i128, Custom);
596 // FIXME - use subtarget debug flags
597 if (!Subtarget->isTargetDarwin() &&
598 !Subtarget->isTargetELF() &&
599 !Subtarget->isTargetCygMing()) {
600 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
603 if (Subtarget->is64Bit()) {
604 setExceptionPointerRegister(X86::RAX);
605 setExceptionSelectorRegister(X86::RDX);
607 setExceptionPointerRegister(X86::EAX);
608 setExceptionSelectorRegister(X86::EDX);
610 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
611 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
613 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
614 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
616 setOperationAction(ISD::TRAP, MVT::Other, Legal);
617 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Legal);
619 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
620 setOperationAction(ISD::VASTART , MVT::Other, Custom);
621 setOperationAction(ISD::VAEND , MVT::Other, Expand);
622 if (Subtarget->is64Bit() && !Subtarget->isTargetWin64()) {
623 // TargetInfo::X86_64ABIBuiltinVaList
624 setOperationAction(ISD::VAARG , MVT::Other, Custom);
625 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
627 // TargetInfo::CharPtrBuiltinVaList
628 setOperationAction(ISD::VAARG , MVT::Other, Expand);
629 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
632 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
633 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
635 if (Subtarget->isOSWindows() && !Subtarget->isTargetEnvMacho())
636 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ?
637 MVT::i64 : MVT::i32, Custom);
638 else if (TM.Options.EnableSegmentedStacks)
639 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ?
640 MVT::i64 : MVT::i32, Custom);
642 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ?
643 MVT::i64 : MVT::i32, Expand);
645 if (!TM.Options.UseSoftFloat && X86ScalarSSEf64) {
646 // f32 and f64 use SSE.
647 // Set up the FP register classes.
648 addRegisterClass(MVT::f32, &X86::FR32RegClass);
649 addRegisterClass(MVT::f64, &X86::FR64RegClass);
651 // Use ANDPD to simulate FABS.
652 setOperationAction(ISD::FABS , MVT::f64, Custom);
653 setOperationAction(ISD::FABS , MVT::f32, Custom);
655 // Use XORP to simulate FNEG.
656 setOperationAction(ISD::FNEG , MVT::f64, Custom);
657 setOperationAction(ISD::FNEG , MVT::f32, Custom);
659 // Use ANDPD and ORPD to simulate FCOPYSIGN.
660 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
661 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
663 // Lower this to FGETSIGNx86 plus an AND.
664 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom);
665 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom);
667 // We don't support sin/cos/fmod
668 setOperationAction(ISD::FSIN , MVT::f64, Expand);
669 setOperationAction(ISD::FCOS , MVT::f64, Expand);
670 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
671 setOperationAction(ISD::FSIN , MVT::f32, Expand);
672 setOperationAction(ISD::FCOS , MVT::f32, Expand);
673 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
675 // Expand FP immediates into loads from the stack, except for the special
677 addLegalFPImmediate(APFloat(+0.0)); // xorpd
678 addLegalFPImmediate(APFloat(+0.0f)); // xorps
679 } else if (!TM.Options.UseSoftFloat && X86ScalarSSEf32) {
680 // Use SSE for f32, x87 for f64.
681 // Set up the FP register classes.
682 addRegisterClass(MVT::f32, &X86::FR32RegClass);
683 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
685 // Use ANDPS to simulate FABS.
686 setOperationAction(ISD::FABS , MVT::f32, Custom);
688 // Use XORP to simulate FNEG.
689 setOperationAction(ISD::FNEG , MVT::f32, Custom);
691 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
693 // Use ANDPS and ORPS to simulate FCOPYSIGN.
694 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
695 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
697 // We don't support sin/cos/fmod
698 setOperationAction(ISD::FSIN , MVT::f32, Expand);
699 setOperationAction(ISD::FCOS , MVT::f32, Expand);
700 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
702 // Special cases we handle for FP constants.
703 addLegalFPImmediate(APFloat(+0.0f)); // xorps
704 addLegalFPImmediate(APFloat(+0.0)); // FLD0
705 addLegalFPImmediate(APFloat(+1.0)); // FLD1
706 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
707 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
709 if (!TM.Options.UnsafeFPMath) {
710 setOperationAction(ISD::FSIN , MVT::f64, Expand);
711 setOperationAction(ISD::FCOS , MVT::f64, Expand);
712 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
714 } else if (!TM.Options.UseSoftFloat) {
715 // f32 and f64 in x87.
716 // Set up the FP register classes.
717 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
718 addRegisterClass(MVT::f32, &X86::RFP32RegClass);
720 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
721 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
722 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
723 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
725 if (!TM.Options.UnsafeFPMath) {
726 setOperationAction(ISD::FSIN , MVT::f64, Expand);
727 setOperationAction(ISD::FSIN , MVT::f32, Expand);
728 setOperationAction(ISD::FCOS , MVT::f64, Expand);
729 setOperationAction(ISD::FCOS , MVT::f32, Expand);
730 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
731 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
733 addLegalFPImmediate(APFloat(+0.0)); // FLD0
734 addLegalFPImmediate(APFloat(+1.0)); // FLD1
735 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
736 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
737 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
738 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
739 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
740 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
743 // We don't support FMA.
744 setOperationAction(ISD::FMA, MVT::f64, Expand);
745 setOperationAction(ISD::FMA, MVT::f32, Expand);
747 // Long double always uses X87.
748 if (!TM.Options.UseSoftFloat) {
749 addRegisterClass(MVT::f80, &X86::RFP80RegClass);
750 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
751 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
753 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended);
754 addLegalFPImmediate(TmpFlt); // FLD0
756 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
759 APFloat TmpFlt2(+1.0);
760 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
762 addLegalFPImmediate(TmpFlt2); // FLD1
763 TmpFlt2.changeSign();
764 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
767 if (!TM.Options.UnsafeFPMath) {
768 setOperationAction(ISD::FSIN , MVT::f80, Expand);
769 setOperationAction(ISD::FCOS , MVT::f80, Expand);
770 setOperationAction(ISD::FSINCOS, MVT::f80, Expand);
773 setOperationAction(ISD::FFLOOR, MVT::f80, Expand);
774 setOperationAction(ISD::FCEIL, MVT::f80, Expand);
775 setOperationAction(ISD::FTRUNC, MVT::f80, Expand);
776 setOperationAction(ISD::FRINT, MVT::f80, Expand);
777 setOperationAction(ISD::FNEARBYINT, MVT::f80, Expand);
778 setOperationAction(ISD::FMA, MVT::f80, Expand);
781 // Always use a library call for pow.
782 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
783 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
784 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
786 setOperationAction(ISD::FLOG, MVT::f80, Expand);
787 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
788 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
789 setOperationAction(ISD::FEXP, MVT::f80, Expand);
790 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
792 // First set operation action for all vector types to either promote
793 // (for widening) or expand (for scalarization). Then we will selectively
794 // turn on ones that can be effectively codegen'd.
795 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
796 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
797 MVT VT = (MVT::SimpleValueType)i;
798 setOperationAction(ISD::ADD , VT, Expand);
799 setOperationAction(ISD::SUB , VT, Expand);
800 setOperationAction(ISD::FADD, VT, Expand);
801 setOperationAction(ISD::FNEG, VT, Expand);
802 setOperationAction(ISD::FSUB, VT, Expand);
803 setOperationAction(ISD::MUL , VT, Expand);
804 setOperationAction(ISD::FMUL, VT, Expand);
805 setOperationAction(ISD::SDIV, VT, Expand);
806 setOperationAction(ISD::UDIV, VT, Expand);
807 setOperationAction(ISD::FDIV, VT, Expand);
808 setOperationAction(ISD::SREM, VT, Expand);
809 setOperationAction(ISD::UREM, VT, Expand);
810 setOperationAction(ISD::LOAD, VT, Expand);
811 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);
812 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT,Expand);
813 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
814 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT,Expand);
815 setOperationAction(ISD::INSERT_SUBVECTOR, VT,Expand);
816 setOperationAction(ISD::FABS, VT, Expand);
817 setOperationAction(ISD::FSIN, VT, Expand);
818 setOperationAction(ISD::FSINCOS, VT, Expand);
819 setOperationAction(ISD::FCOS, VT, Expand);
820 setOperationAction(ISD::FSINCOS, VT, Expand);
821 setOperationAction(ISD::FREM, VT, Expand);
822 setOperationAction(ISD::FMA, VT, Expand);
823 setOperationAction(ISD::FPOWI, VT, Expand);
824 setOperationAction(ISD::FSQRT, VT, Expand);
825 setOperationAction(ISD::FCOPYSIGN, VT, Expand);
826 setOperationAction(ISD::FFLOOR, VT, Expand);
827 setOperationAction(ISD::FCEIL, VT, Expand);
828 setOperationAction(ISD::FTRUNC, VT, Expand);
829 setOperationAction(ISD::FRINT, VT, Expand);
830 setOperationAction(ISD::FNEARBYINT, VT, Expand);
831 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
832 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
833 setOperationAction(ISD::SDIVREM, VT, Expand);
834 setOperationAction(ISD::UDIVREM, VT, Expand);
835 setOperationAction(ISD::FPOW, VT, Expand);
836 setOperationAction(ISD::CTPOP, VT, Expand);
837 setOperationAction(ISD::CTTZ, VT, Expand);
838 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
839 setOperationAction(ISD::CTLZ, VT, Expand);
840 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
841 setOperationAction(ISD::SHL, VT, Expand);
842 setOperationAction(ISD::SRA, VT, Expand);
843 setOperationAction(ISD::SRL, VT, Expand);
844 setOperationAction(ISD::ROTL, VT, Expand);
845 setOperationAction(ISD::ROTR, VT, Expand);
846 setOperationAction(ISD::BSWAP, VT, Expand);
847 setOperationAction(ISD::SETCC, VT, Expand);
848 setOperationAction(ISD::FLOG, VT, Expand);
849 setOperationAction(ISD::FLOG2, VT, Expand);
850 setOperationAction(ISD::FLOG10, VT, Expand);
851 setOperationAction(ISD::FEXP, VT, Expand);
852 setOperationAction(ISD::FEXP2, VT, Expand);
853 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
854 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
855 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
856 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
857 setOperationAction(ISD::SIGN_EXTEND_INREG, VT,Expand);
858 setOperationAction(ISD::TRUNCATE, VT, Expand);
859 setOperationAction(ISD::SIGN_EXTEND, VT, Expand);
860 setOperationAction(ISD::ZERO_EXTEND, VT, Expand);
861 setOperationAction(ISD::ANY_EXTEND, VT, Expand);
862 setOperationAction(ISD::VSELECT, VT, Expand);
863 for (int InnerVT = MVT::FIRST_VECTOR_VALUETYPE;
864 InnerVT <= MVT::LAST_VECTOR_VALUETYPE; ++InnerVT)
865 setTruncStoreAction(VT,
866 (MVT::SimpleValueType)InnerVT, Expand);
867 setLoadExtAction(ISD::SEXTLOAD, VT, Expand);
868 setLoadExtAction(ISD::ZEXTLOAD, VT, Expand);
869 setLoadExtAction(ISD::EXTLOAD, VT, Expand);
872 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
873 // with -msoft-float, disable use of MMX as well.
874 if (!TM.Options.UseSoftFloat && Subtarget->hasMMX()) {
875 addRegisterClass(MVT::x86mmx, &X86::VR64RegClass);
876 // No operations on x86mmx supported, everything uses intrinsics.
879 // MMX-sized vectors (other than x86mmx) are expected to be expanded
880 // into smaller operations.
881 setOperationAction(ISD::MULHS, MVT::v8i8, Expand);
882 setOperationAction(ISD::MULHS, MVT::v4i16, Expand);
883 setOperationAction(ISD::MULHS, MVT::v2i32, Expand);
884 setOperationAction(ISD::MULHS, MVT::v1i64, Expand);
885 setOperationAction(ISD::AND, MVT::v8i8, Expand);
886 setOperationAction(ISD::AND, MVT::v4i16, Expand);
887 setOperationAction(ISD::AND, MVT::v2i32, Expand);
888 setOperationAction(ISD::AND, MVT::v1i64, Expand);
889 setOperationAction(ISD::OR, MVT::v8i8, Expand);
890 setOperationAction(ISD::OR, MVT::v4i16, Expand);
891 setOperationAction(ISD::OR, MVT::v2i32, Expand);
892 setOperationAction(ISD::OR, MVT::v1i64, Expand);
893 setOperationAction(ISD::XOR, MVT::v8i8, Expand);
894 setOperationAction(ISD::XOR, MVT::v4i16, Expand);
895 setOperationAction(ISD::XOR, MVT::v2i32, Expand);
896 setOperationAction(ISD::XOR, MVT::v1i64, Expand);
897 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Expand);
898 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Expand);
899 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i32, Expand);
900 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Expand);
901 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand);
902 setOperationAction(ISD::SELECT, MVT::v8i8, Expand);
903 setOperationAction(ISD::SELECT, MVT::v4i16, Expand);
904 setOperationAction(ISD::SELECT, MVT::v2i32, Expand);
905 setOperationAction(ISD::SELECT, MVT::v1i64, Expand);
906 setOperationAction(ISD::BITCAST, MVT::v8i8, Expand);
907 setOperationAction(ISD::BITCAST, MVT::v4i16, Expand);
908 setOperationAction(ISD::BITCAST, MVT::v2i32, Expand);
909 setOperationAction(ISD::BITCAST, MVT::v1i64, Expand);
911 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE1()) {
912 addRegisterClass(MVT::v4f32, &X86::VR128RegClass);
914 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
915 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
916 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
917 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
918 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
919 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
920 setOperationAction(ISD::FABS, MVT::v4f32, Custom);
921 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
922 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
923 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
924 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
925 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
928 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE2()) {
929 addRegisterClass(MVT::v2f64, &X86::VR128RegClass);
931 // FIXME: Unfortunately -soft-float and -no-implicit-float means XMM
932 // registers cannot be used even for integer operations.
933 addRegisterClass(MVT::v16i8, &X86::VR128RegClass);
934 addRegisterClass(MVT::v8i16, &X86::VR128RegClass);
935 addRegisterClass(MVT::v4i32, &X86::VR128RegClass);
936 addRegisterClass(MVT::v2i64, &X86::VR128RegClass);
938 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
939 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
940 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
941 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
942 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
943 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
944 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
945 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
946 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
947 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
948 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
949 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
950 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
951 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
952 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
953 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
954 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
955 setOperationAction(ISD::FABS, MVT::v2f64, Custom);
957 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
958 setOperationAction(ISD::SETCC, MVT::v16i8, Custom);
959 setOperationAction(ISD::SETCC, MVT::v8i16, Custom);
960 setOperationAction(ISD::SETCC, MVT::v4i32, Custom);
962 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
963 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
964 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
965 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
966 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
968 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
969 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
970 MVT VT = (MVT::SimpleValueType)i;
971 // Do not attempt to custom lower non-power-of-2 vectors
972 if (!isPowerOf2_32(VT.getVectorNumElements()))
974 // Do not attempt to custom lower non-128-bit vectors
975 if (!VT.is128BitVector())
977 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
978 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
979 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
982 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
983 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
984 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
985 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
986 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
987 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
989 if (Subtarget->is64Bit()) {
990 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
991 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
994 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
995 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
996 MVT VT = (MVT::SimpleValueType)i;
998 // Do not attempt to promote non-128-bit vectors
999 if (!VT.is128BitVector())
1002 setOperationAction(ISD::AND, VT, Promote);
1003 AddPromotedToType (ISD::AND, VT, MVT::v2i64);
1004 setOperationAction(ISD::OR, VT, Promote);
1005 AddPromotedToType (ISD::OR, VT, MVT::v2i64);
1006 setOperationAction(ISD::XOR, VT, Promote);
1007 AddPromotedToType (ISD::XOR, VT, MVT::v2i64);
1008 setOperationAction(ISD::LOAD, VT, Promote);
1009 AddPromotedToType (ISD::LOAD, VT, MVT::v2i64);
1010 setOperationAction(ISD::SELECT, VT, Promote);
1011 AddPromotedToType (ISD::SELECT, VT, MVT::v2i64);
1014 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
1016 // Custom lower v2i64 and v2f64 selects.
1017 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
1018 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
1019 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
1020 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
1022 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
1023 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
1025 setOperationAction(ISD::UINT_TO_FP, MVT::v4i8, Custom);
1026 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);
1027 // As there is no 64-bit GPR available, we need build a special custom
1028 // sequence to convert from v2i32 to v2f32.
1029 if (!Subtarget->is64Bit())
1030 setOperationAction(ISD::UINT_TO_FP, MVT::v2f32, Custom);
1032 setOperationAction(ISD::FP_EXTEND, MVT::v2f32, Custom);
1033 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Custom);
1035 setLoadExtAction(ISD::EXTLOAD, MVT::v2f32, Legal);
1038 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE41()) {
1039 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
1040 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
1041 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
1042 setOperationAction(ISD::FRINT, MVT::f32, Legal);
1043 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
1044 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
1045 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
1046 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
1047 setOperationAction(ISD::FRINT, MVT::f64, Legal);
1048 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
1050 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal);
1051 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal);
1052 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal);
1053 setOperationAction(ISD::FRINT, MVT::v4f32, Legal);
1054 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal);
1055 setOperationAction(ISD::FFLOOR, MVT::v2f64, Legal);
1056 setOperationAction(ISD::FCEIL, MVT::v2f64, Legal);
1057 setOperationAction(ISD::FTRUNC, MVT::v2f64, Legal);
1058 setOperationAction(ISD::FRINT, MVT::v2f64, Legal);
1059 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Legal);
1061 // FIXME: Do we need to handle scalar-to-vector here?
1062 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
1064 setOperationAction(ISD::VSELECT, MVT::v2f64, Legal);
1065 setOperationAction(ISD::VSELECT, MVT::v2i64, Legal);
1066 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
1067 setOperationAction(ISD::VSELECT, MVT::v4i32, Legal);
1068 setOperationAction(ISD::VSELECT, MVT::v4f32, Legal);
1070 // i8 and i16 vectors are custom , because the source register and source
1071 // source memory operand types are not the same width. f32 vectors are
1072 // custom since the immediate controlling the insert encodes additional
1074 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
1075 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
1076 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
1077 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
1079 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
1080 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
1081 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
1082 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
1084 // FIXME: these should be Legal but thats only for the case where
1085 // the index is constant. For now custom expand to deal with that.
1086 if (Subtarget->is64Bit()) {
1087 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
1088 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
1092 if (Subtarget->hasSSE2()) {
1093 setOperationAction(ISD::SRL, MVT::v8i16, Custom);
1094 setOperationAction(ISD::SRL, MVT::v16i8, Custom);
1096 setOperationAction(ISD::SHL, MVT::v8i16, Custom);
1097 setOperationAction(ISD::SHL, MVT::v16i8, Custom);
1099 setOperationAction(ISD::SRA, MVT::v8i16, Custom);
1100 setOperationAction(ISD::SRA, MVT::v16i8, Custom);
1102 // In the customized shift lowering, the legal cases in AVX2 will be
1104 setOperationAction(ISD::SRL, MVT::v2i64, Custom);
1105 setOperationAction(ISD::SRL, MVT::v4i32, Custom);
1107 setOperationAction(ISD::SHL, MVT::v2i64, Custom);
1108 setOperationAction(ISD::SHL, MVT::v4i32, Custom);
1110 setOperationAction(ISD::SRA, MVT::v4i32, Custom);
1112 setOperationAction(ISD::SDIV, MVT::v8i16, Custom);
1113 setOperationAction(ISD::SDIV, MVT::v4i32, Custom);
1116 if (!TM.Options.UseSoftFloat && Subtarget->hasFp256()) {
1117 addRegisterClass(MVT::v32i8, &X86::VR256RegClass);
1118 addRegisterClass(MVT::v16i16, &X86::VR256RegClass);
1119 addRegisterClass(MVT::v8i32, &X86::VR256RegClass);
1120 addRegisterClass(MVT::v8f32, &X86::VR256RegClass);
1121 addRegisterClass(MVT::v4i64, &X86::VR256RegClass);
1122 addRegisterClass(MVT::v4f64, &X86::VR256RegClass);
1124 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
1125 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
1126 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
1128 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
1129 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
1130 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
1131 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
1132 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
1133 setOperationAction(ISD::FFLOOR, MVT::v8f32, Legal);
1134 setOperationAction(ISD::FCEIL, MVT::v8f32, Legal);
1135 setOperationAction(ISD::FTRUNC, MVT::v8f32, Legal);
1136 setOperationAction(ISD::FRINT, MVT::v8f32, Legal);
1137 setOperationAction(ISD::FNEARBYINT, MVT::v8f32, Legal);
1138 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
1139 setOperationAction(ISD::FABS, MVT::v8f32, Custom);
1141 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
1142 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
1143 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
1144 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
1145 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
1146 setOperationAction(ISD::FFLOOR, MVT::v4f64, Legal);
1147 setOperationAction(ISD::FCEIL, MVT::v4f64, Legal);
1148 setOperationAction(ISD::FTRUNC, MVT::v4f64, Legal);
1149 setOperationAction(ISD::FRINT, MVT::v4f64, Legal);
1150 setOperationAction(ISD::FNEARBYINT, MVT::v4f64, Legal);
1151 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
1152 setOperationAction(ISD::FABS, MVT::v4f64, Custom);
1154 setOperationAction(ISD::FP_TO_SINT, MVT::v8i16, Custom);
1156 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
1157 setOperationAction(ISD::SINT_TO_FP, MVT::v8i16, Promote);
1158 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
1159 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal);
1161 setOperationAction(ISD::UINT_TO_FP, MVT::v8i8, Custom);
1162 setOperationAction(ISD::UINT_TO_FP, MVT::v8i16, Custom);
1164 setLoadExtAction(ISD::EXTLOAD, MVT::v4f32, Legal);
1166 setOperationAction(ISD::SRL, MVT::v16i16, Custom);
1167 setOperationAction(ISD::SRL, MVT::v32i8, Custom);
1169 setOperationAction(ISD::SHL, MVT::v16i16, Custom);
1170 setOperationAction(ISD::SHL, MVT::v32i8, Custom);
1172 setOperationAction(ISD::SRA, MVT::v16i16, Custom);
1173 setOperationAction(ISD::SRA, MVT::v32i8, Custom);
1175 setOperationAction(ISD::SDIV, MVT::v16i16, Custom);
1177 setOperationAction(ISD::SETCC, MVT::v32i8, Custom);
1178 setOperationAction(ISD::SETCC, MVT::v16i16, Custom);
1179 setOperationAction(ISD::SETCC, MVT::v8i32, Custom);
1180 setOperationAction(ISD::SETCC, MVT::v4i64, Custom);
1182 setOperationAction(ISD::SELECT, MVT::v4f64, Custom);
1183 setOperationAction(ISD::SELECT, MVT::v4i64, Custom);
1184 setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
1186 setOperationAction(ISD::VSELECT, MVT::v4f64, Legal);
1187 setOperationAction(ISD::VSELECT, MVT::v4i64, Legal);
1188 setOperationAction(ISD::VSELECT, MVT::v8i32, Legal);
1189 setOperationAction(ISD::VSELECT, MVT::v8f32, Legal);
1191 setOperationAction(ISD::SIGN_EXTEND, MVT::v4i64, Custom);
1192 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i32, Custom);
1193 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1194 setOperationAction(ISD::ZERO_EXTEND, MVT::v4i64, Custom);
1195 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i32, Custom);
1196 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i16, Custom);
1197 setOperationAction(ISD::ANY_EXTEND, MVT::v4i64, Custom);
1198 setOperationAction(ISD::ANY_EXTEND, MVT::v8i32, Custom);
1199 setOperationAction(ISD::ANY_EXTEND, MVT::v16i16, Custom);
1200 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1201 setOperationAction(ISD::TRUNCATE, MVT::v8i16, Custom);
1202 setOperationAction(ISD::TRUNCATE, MVT::v4i32, Custom);
1204 if (Subtarget->hasFMA() || Subtarget->hasFMA4()) {
1205 setOperationAction(ISD::FMA, MVT::v8f32, Legal);
1206 setOperationAction(ISD::FMA, MVT::v4f64, Legal);
1207 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
1208 setOperationAction(ISD::FMA, MVT::v2f64, Legal);
1209 setOperationAction(ISD::FMA, MVT::f32, Legal);
1210 setOperationAction(ISD::FMA, MVT::f64, Legal);
1213 if (Subtarget->hasInt256()) {
1214 setOperationAction(ISD::ADD, MVT::v4i64, Legal);
1215 setOperationAction(ISD::ADD, MVT::v8i32, Legal);
1216 setOperationAction(ISD::ADD, MVT::v16i16, Legal);
1217 setOperationAction(ISD::ADD, MVT::v32i8, Legal);
1219 setOperationAction(ISD::SUB, MVT::v4i64, Legal);
1220 setOperationAction(ISD::SUB, MVT::v8i32, Legal);
1221 setOperationAction(ISD::SUB, MVT::v16i16, Legal);
1222 setOperationAction(ISD::SUB, MVT::v32i8, Legal);
1224 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1225 setOperationAction(ISD::MUL, MVT::v8i32, Legal);
1226 setOperationAction(ISD::MUL, MVT::v16i16, Legal);
1227 // Don't lower v32i8 because there is no 128-bit byte mul
1229 setOperationAction(ISD::VSELECT, MVT::v32i8, Legal);
1231 setOperationAction(ISD::SDIV, MVT::v8i32, Custom);
1233 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
1234 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
1235 setOperationAction(ISD::ADD, MVT::v16i16, Custom);
1236 setOperationAction(ISD::ADD, MVT::v32i8, Custom);
1238 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
1239 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
1240 setOperationAction(ISD::SUB, MVT::v16i16, Custom);
1241 setOperationAction(ISD::SUB, MVT::v32i8, Custom);
1243 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1244 setOperationAction(ISD::MUL, MVT::v8i32, Custom);
1245 setOperationAction(ISD::MUL, MVT::v16i16, Custom);
1246 // Don't lower v32i8 because there is no 128-bit byte mul
1249 // In the customized shift lowering, the legal cases in AVX2 will be
1251 setOperationAction(ISD::SRL, MVT::v4i64, Custom);
1252 setOperationAction(ISD::SRL, MVT::v8i32, Custom);
1254 setOperationAction(ISD::SHL, MVT::v4i64, Custom);
1255 setOperationAction(ISD::SHL, MVT::v8i32, Custom);
1257 setOperationAction(ISD::SRA, MVT::v8i32, Custom);
1259 // Custom lower several nodes for 256-bit types.
1260 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
1261 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
1262 MVT VT = (MVT::SimpleValueType)i;
1264 // Extract subvector is special because the value type
1265 // (result) is 128-bit but the source is 256-bit wide.
1266 if (VT.is128BitVector())
1267 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1269 // Do not attempt to custom lower other non-256-bit vectors
1270 if (!VT.is256BitVector())
1273 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1274 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1275 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1276 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1277 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1278 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1279 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom);
1282 // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64.
1283 for (int i = MVT::v32i8; i != MVT::v4i64; ++i) {
1284 MVT VT = (MVT::SimpleValueType)i;
1286 // Do not attempt to promote non-256-bit vectors
1287 if (!VT.is256BitVector())
1290 setOperationAction(ISD::AND, VT, Promote);
1291 AddPromotedToType (ISD::AND, VT, MVT::v4i64);
1292 setOperationAction(ISD::OR, VT, Promote);
1293 AddPromotedToType (ISD::OR, VT, MVT::v4i64);
1294 setOperationAction(ISD::XOR, VT, Promote);
1295 AddPromotedToType (ISD::XOR, VT, MVT::v4i64);
1296 setOperationAction(ISD::LOAD, VT, Promote);
1297 AddPromotedToType (ISD::LOAD, VT, MVT::v4i64);
1298 setOperationAction(ISD::SELECT, VT, Promote);
1299 AddPromotedToType (ISD::SELECT, VT, MVT::v4i64);
1303 if (!TM.Options.UseSoftFloat && Subtarget->hasAVX512()) {
1304 addRegisterClass(MVT::v16i32, &X86::VR512RegClass);
1305 addRegisterClass(MVT::v16f32, &X86::VR512RegClass);
1306 addRegisterClass(MVT::v8i64, &X86::VR512RegClass);
1307 addRegisterClass(MVT::v8f64, &X86::VR512RegClass);
1309 addRegisterClass(MVT::v8i1, &X86::VK8RegClass);
1310 addRegisterClass(MVT::v16i1, &X86::VK16RegClass);
1312 setLoadExtAction(ISD::EXTLOAD, MVT::v8f32, Legal);
1313 setOperationAction(ISD::LOAD, MVT::v16f32, Legal);
1314 setOperationAction(ISD::LOAD, MVT::v8f64, Legal);
1315 setOperationAction(ISD::LOAD, MVT::v8i64, Legal);
1316 setOperationAction(ISD::LOAD, MVT::v16i32, Legal);
1317 setOperationAction(ISD::LOAD, MVT::v16i1, Legal);
1319 setOperationAction(ISD::FADD, MVT::v16f32, Legal);
1320 setOperationAction(ISD::FSUB, MVT::v16f32, Legal);
1321 setOperationAction(ISD::FMUL, MVT::v16f32, Legal);
1322 setOperationAction(ISD::FDIV, MVT::v16f32, Legal);
1323 setOperationAction(ISD::FSQRT, MVT::v16f32, Legal);
1324 setOperationAction(ISD::FNEG, MVT::v16f32, Custom);
1326 setOperationAction(ISD::FADD, MVT::v8f64, Legal);
1327 setOperationAction(ISD::FSUB, MVT::v8f64, Legal);
1328 setOperationAction(ISD::FMUL, MVT::v8f64, Legal);
1329 setOperationAction(ISD::FDIV, MVT::v8f64, Legal);
1330 setOperationAction(ISD::FSQRT, MVT::v8f64, Legal);
1331 setOperationAction(ISD::FNEG, MVT::v8f64, Custom);
1332 setOperationAction(ISD::FMA, MVT::v8f64, Legal);
1333 setOperationAction(ISD::FMA, MVT::v16f32, Legal);
1334 setOperationAction(ISD::SDIV, MVT::v16i32, Custom);
1336 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Legal);
1337 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Legal);
1338 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Legal);
1339 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Legal);
1340 if (Subtarget->is64Bit()) {
1341 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Legal);
1342 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Legal);
1343 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Legal);
1344 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Legal);
1346 setOperationAction(ISD::FP_TO_SINT, MVT::v16i32, Legal);
1347 setOperationAction(ISD::FP_TO_UINT, MVT::v16i32, Legal);
1348 setOperationAction(ISD::FP_TO_UINT, MVT::v8i32, Legal);
1349 setOperationAction(ISD::SINT_TO_FP, MVT::v16i32, Legal);
1350 setOperationAction(ISD::UINT_TO_FP, MVT::v16i32, Legal);
1351 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Legal);
1352 setOperationAction(ISD::FP_ROUND, MVT::v8f32, Legal);
1353 setOperationAction(ISD::FP_EXTEND, MVT::v8f32, Legal);
1355 setOperationAction(ISD::TRUNCATE, MVT::i1, Legal);
1356 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1357 setOperationAction(ISD::TRUNCATE, MVT::v8i32, Custom);
1358 setOperationAction(ISD::TRUNCATE, MVT::v8i1, Custom);
1359 setOperationAction(ISD::TRUNCATE, MVT::v16i1, Custom);
1360 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i32, Custom);
1361 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i64, Custom);
1362 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i32, Custom);
1363 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i64, Custom);
1364 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i8, Custom);
1365 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i16, Custom);
1366 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1368 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f64, Custom);
1369 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i64, Custom);
1370 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16f32, Custom);
1371 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i32, Custom);
1372 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i1, Custom);
1374 setOperationAction(ISD::SETCC, MVT::v16i1, Custom);
1375 setOperationAction(ISD::SETCC, MVT::v8i1, Custom);
1377 setOperationAction(ISD::MUL, MVT::v8i64, Custom);
1379 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i1, Custom);
1380 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i1, Custom);
1381 setOperationAction(ISD::SELECT, MVT::v8f64, Custom);
1382 setOperationAction(ISD::SELECT, MVT::v8i64, Custom);
1383 setOperationAction(ISD::SELECT, MVT::v16f32, Custom);
1385 setOperationAction(ISD::ADD, MVT::v8i64, Legal);
1386 setOperationAction(ISD::ADD, MVT::v16i32, Legal);
1388 setOperationAction(ISD::SUB, MVT::v8i64, Legal);
1389 setOperationAction(ISD::SUB, MVT::v16i32, Legal);
1391 setOperationAction(ISD::MUL, MVT::v16i32, Legal);
1393 setOperationAction(ISD::SRL, MVT::v8i64, Custom);
1394 setOperationAction(ISD::SRL, MVT::v16i32, Custom);
1396 setOperationAction(ISD::SHL, MVT::v8i64, Custom);
1397 setOperationAction(ISD::SHL, MVT::v16i32, Custom);
1399 setOperationAction(ISD::SRA, MVT::v8i64, Custom);
1400 setOperationAction(ISD::SRA, MVT::v16i32, Custom);
1402 setOperationAction(ISD::AND, MVT::v8i64, Legal);
1403 setOperationAction(ISD::OR, MVT::v8i64, Legal);
1404 setOperationAction(ISD::XOR, MVT::v8i64, Legal);
1405 setOperationAction(ISD::AND, MVT::v16i32, Legal);
1406 setOperationAction(ISD::OR, MVT::v16i32, Legal);
1407 setOperationAction(ISD::XOR, MVT::v16i32, Legal);
1409 // Custom lower several nodes.
1410 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
1411 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
1412 MVT VT = (MVT::SimpleValueType)i;
1414 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1415 // Extract subvector is special because the value type
1416 // (result) is 256/128-bit but the source is 512-bit wide.
1417 if (VT.is128BitVector() || VT.is256BitVector())
1418 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1420 if (VT.getVectorElementType() == MVT::i1)
1421 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal);
1423 // Do not attempt to custom lower other non-512-bit vectors
1424 if (!VT.is512BitVector())
1427 if ( EltSize >= 32) {
1428 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1429 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1430 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1431 setOperationAction(ISD::VSELECT, VT, Legal);
1432 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1433 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1434 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1437 for (int i = MVT::v32i8; i != MVT::v8i64; ++i) {
1438 MVT VT = (MVT::SimpleValueType)i;
1440 // Do not attempt to promote non-256-bit vectors
1441 if (!VT.is512BitVector())
1444 setOperationAction(ISD::SELECT, VT, Promote);
1445 AddPromotedToType (ISD::SELECT, VT, MVT::v8i64);
1449 // SIGN_EXTEND_INREGs are evaluated by the extend type. Handle the expansion
1450 // of this type with custom code.
1451 for (int VT = MVT::FIRST_VECTOR_VALUETYPE;
1452 VT != MVT::LAST_VECTOR_VALUETYPE; VT++) {
1453 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,
1457 // We want to custom lower some of our intrinsics.
1458 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
1459 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
1460 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
1462 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't
1463 // handle type legalization for these operations here.
1465 // FIXME: We really should do custom legalization for addition and
1466 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better
1467 // than generic legalization for 64-bit multiplication-with-overflow, though.
1468 for (unsigned i = 0, e = 3+Subtarget->is64Bit(); i != e; ++i) {
1469 // Add/Sub/Mul with overflow operations are custom lowered.
1471 setOperationAction(ISD::SADDO, VT, Custom);
1472 setOperationAction(ISD::UADDO, VT, Custom);
1473 setOperationAction(ISD::SSUBO, VT, Custom);
1474 setOperationAction(ISD::USUBO, VT, Custom);
1475 setOperationAction(ISD::SMULO, VT, Custom);
1476 setOperationAction(ISD::UMULO, VT, Custom);
1479 // There are no 8-bit 3-address imul/mul instructions
1480 setOperationAction(ISD::SMULO, MVT::i8, Expand);
1481 setOperationAction(ISD::UMULO, MVT::i8, Expand);
1483 if (!Subtarget->is64Bit()) {
1484 // These libcalls are not available in 32-bit.
1485 setLibcallName(RTLIB::SHL_I128, 0);
1486 setLibcallName(RTLIB::SRL_I128, 0);
1487 setLibcallName(RTLIB::SRA_I128, 0);
1490 // Combine sin / cos into one node or libcall if possible.
1491 if (Subtarget->hasSinCos()) {
1492 setLibcallName(RTLIB::SINCOS_F32, "sincosf");
1493 setLibcallName(RTLIB::SINCOS_F64, "sincos");
1494 if (Subtarget->isTargetDarwin()) {
1495 // For MacOSX, we don't want to the normal expansion of a libcall to
1496 // sincos. We want to issue a libcall to __sincos_stret to avoid memory
1498 setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
1499 setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
1503 // We have target-specific dag combine patterns for the following nodes:
1504 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
1505 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
1506 setTargetDAGCombine(ISD::VSELECT);
1507 setTargetDAGCombine(ISD::SELECT);
1508 setTargetDAGCombine(ISD::SHL);
1509 setTargetDAGCombine(ISD::SRA);
1510 setTargetDAGCombine(ISD::SRL);
1511 setTargetDAGCombine(ISD::OR);
1512 setTargetDAGCombine(ISD::AND);
1513 setTargetDAGCombine(ISD::ADD);
1514 setTargetDAGCombine(ISD::FADD);
1515 setTargetDAGCombine(ISD::FSUB);
1516 setTargetDAGCombine(ISD::FMA);
1517 setTargetDAGCombine(ISD::SUB);
1518 setTargetDAGCombine(ISD::LOAD);
1519 setTargetDAGCombine(ISD::STORE);
1520 setTargetDAGCombine(ISD::ZERO_EXTEND);
1521 setTargetDAGCombine(ISD::ANY_EXTEND);
1522 setTargetDAGCombine(ISD::SIGN_EXTEND);
1523 setTargetDAGCombine(ISD::SIGN_EXTEND_INREG);
1524 setTargetDAGCombine(ISD::TRUNCATE);
1525 setTargetDAGCombine(ISD::SINT_TO_FP);
1526 setTargetDAGCombine(ISD::SETCC);
1527 if (Subtarget->is64Bit())
1528 setTargetDAGCombine(ISD::MUL);
1529 setTargetDAGCombine(ISD::XOR);
1531 computeRegisterProperties();
1533 // On Darwin, -Os means optimize for size without hurting performance,
1534 // do not reduce the limit.
1535 MaxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
1536 MaxStoresPerMemsetOptSize = Subtarget->isTargetDarwin() ? 16 : 8;
1537 MaxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores
1538 MaxStoresPerMemcpyOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1539 MaxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores
1540 MaxStoresPerMemmoveOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1541 setPrefLoopAlignment(4); // 2^4 bytes.
1543 // Predictable cmov don't hurt on atom because it's in-order.
1544 PredictableSelectIsExpensive = !Subtarget->isAtom();
1546 setPrefFunctionAlignment(4); // 2^4 bytes.
1549 EVT X86TargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
1553 const TargetMachine &TM = getTargetMachine();
1554 if (!TM.Options.UseSoftFloat && Subtarget->hasAVX512())
1555 switch(VT.getVectorNumElements()) {
1556 case 8: return MVT::v8i1;
1557 case 16: return MVT::v16i1;
1560 return VT.changeVectorElementTypeToInteger();
1563 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
1564 /// the desired ByVal argument alignment.
1565 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) {
1568 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1569 if (VTy->getBitWidth() == 128)
1571 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1572 unsigned EltAlign = 0;
1573 getMaxByValAlign(ATy->getElementType(), EltAlign);
1574 if (EltAlign > MaxAlign)
1575 MaxAlign = EltAlign;
1576 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
1577 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
1578 unsigned EltAlign = 0;
1579 getMaxByValAlign(STy->getElementType(i), EltAlign);
1580 if (EltAlign > MaxAlign)
1581 MaxAlign = EltAlign;
1588 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1589 /// function arguments in the caller parameter area. For X86, aggregates
1590 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
1591 /// are at 4-byte boundaries.
1592 unsigned X86TargetLowering::getByValTypeAlignment(Type *Ty) const {
1593 if (Subtarget->is64Bit()) {
1594 // Max of 8 and alignment of type.
1595 unsigned TyAlign = TD->getABITypeAlignment(Ty);
1602 if (Subtarget->hasSSE1())
1603 getMaxByValAlign(Ty, Align);
1607 /// getOptimalMemOpType - Returns the target specific optimal type for load
1608 /// and store operations as a result of memset, memcpy, and memmove
1609 /// lowering. If DstAlign is zero that means it's safe to destination
1610 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
1611 /// means there isn't a need to check it against alignment requirement,
1612 /// probably because the source does not need to be loaded. If 'IsMemset' is
1613 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
1614 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
1615 /// source is constant so it does not need to be loaded.
1616 /// It returns EVT::Other if the type should be determined using generic
1617 /// target-independent logic.
1619 X86TargetLowering::getOptimalMemOpType(uint64_t Size,
1620 unsigned DstAlign, unsigned SrcAlign,
1621 bool IsMemset, bool ZeroMemset,
1623 MachineFunction &MF) const {
1624 const Function *F = MF.getFunction();
1625 if ((!IsMemset || ZeroMemset) &&
1626 !F->getAttributes().hasAttribute(AttributeSet::FunctionIndex,
1627 Attribute::NoImplicitFloat)) {
1629 (Subtarget->isUnalignedMemAccessFast() ||
1630 ((DstAlign == 0 || DstAlign >= 16) &&
1631 (SrcAlign == 0 || SrcAlign >= 16)))) {
1633 if (Subtarget->hasInt256())
1635 if (Subtarget->hasFp256())
1638 if (Subtarget->hasSSE2())
1640 if (Subtarget->hasSSE1())
1642 } else if (!MemcpyStrSrc && Size >= 8 &&
1643 !Subtarget->is64Bit() &&
1644 Subtarget->hasSSE2()) {
1645 // Do not use f64 to lower memcpy if source is string constant. It's
1646 // better to use i32 to avoid the loads.
1650 if (Subtarget->is64Bit() && Size >= 8)
1655 bool X86TargetLowering::isSafeMemOpType(MVT VT) const {
1657 return X86ScalarSSEf32;
1658 else if (VT == MVT::f64)
1659 return X86ScalarSSEf64;
1664 X86TargetLowering::allowsUnalignedMemoryAccesses(EVT VT, bool *Fast) const {
1666 *Fast = Subtarget->isUnalignedMemAccessFast();
1670 /// getJumpTableEncoding - Return the entry encoding for a jump table in the
1671 /// current function. The returned value is a member of the
1672 /// MachineJumpTableInfo::JTEntryKind enum.
1673 unsigned X86TargetLowering::getJumpTableEncoding() const {
1674 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
1676 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1677 Subtarget->isPICStyleGOT())
1678 return MachineJumpTableInfo::EK_Custom32;
1680 // Otherwise, use the normal jump table encoding heuristics.
1681 return TargetLowering::getJumpTableEncoding();
1685 X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
1686 const MachineBasicBlock *MBB,
1687 unsigned uid,MCContext &Ctx) const{
1688 assert(getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1689 Subtarget->isPICStyleGOT());
1690 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
1692 return MCSymbolRefExpr::Create(MBB->getSymbol(),
1693 MCSymbolRefExpr::VK_GOTOFF, Ctx);
1696 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
1698 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
1699 SelectionDAG &DAG) const {
1700 if (!Subtarget->is64Bit())
1701 // This doesn't have SDLoc associated with it, but is not really the
1702 // same as a Register.
1703 return DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), getPointerTy());
1707 /// getPICJumpTableRelocBaseExpr - This returns the relocation base for the
1708 /// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an
1710 const MCExpr *X86TargetLowering::
1711 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
1712 MCContext &Ctx) const {
1713 // X86-64 uses RIP relative addressing based on the jump table label.
1714 if (Subtarget->isPICStyleRIPRel())
1715 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
1717 // Otherwise, the reference is relative to the PIC base.
1718 return MCSymbolRefExpr::Create(MF->getPICBaseSymbol(), Ctx);
1721 // FIXME: Why this routine is here? Move to RegInfo!
1722 std::pair<const TargetRegisterClass*, uint8_t>
1723 X86TargetLowering::findRepresentativeClass(MVT VT) const{
1724 const TargetRegisterClass *RRC = 0;
1726 switch (VT.SimpleTy) {
1728 return TargetLowering::findRepresentativeClass(VT);
1729 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
1730 RRC = Subtarget->is64Bit() ?
1731 (const TargetRegisterClass*)&X86::GR64RegClass :
1732 (const TargetRegisterClass*)&X86::GR32RegClass;
1735 RRC = &X86::VR64RegClass;
1737 case MVT::f32: case MVT::f64:
1738 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
1739 case MVT::v4f32: case MVT::v2f64:
1740 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32:
1742 RRC = &X86::VR128RegClass;
1745 return std::make_pair(RRC, Cost);
1748 bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace,
1749 unsigned &Offset) const {
1750 if (!Subtarget->isTargetLinux())
1753 if (Subtarget->is64Bit()) {
1754 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs:
1756 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
1768 bool X86TargetLowering::isNoopAddrSpaceCast(unsigned SrcAS,
1769 unsigned DestAS) const {
1770 assert(SrcAS != DestAS && "Expected different address spaces!");
1772 return SrcAS < 256 && DestAS < 256;
1775 //===----------------------------------------------------------------------===//
1776 // Return Value Calling Convention Implementation
1777 //===----------------------------------------------------------------------===//
1779 #include "X86GenCallingConv.inc"
1782 X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv,
1783 MachineFunction &MF, bool isVarArg,
1784 const SmallVectorImpl<ISD::OutputArg> &Outs,
1785 LLVMContext &Context) const {
1786 SmallVector<CCValAssign, 16> RVLocs;
1787 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
1789 return CCInfo.CheckReturn(Outs, RetCC_X86);
1792 const uint16_t *X86TargetLowering::getScratchRegisters(CallingConv::ID) const {
1793 static const uint16_t ScratchRegs[] = { X86::R11, 0 };
1798 X86TargetLowering::LowerReturn(SDValue Chain,
1799 CallingConv::ID CallConv, bool isVarArg,
1800 const SmallVectorImpl<ISD::OutputArg> &Outs,
1801 const SmallVectorImpl<SDValue> &OutVals,
1802 SDLoc dl, SelectionDAG &DAG) const {
1803 MachineFunction &MF = DAG.getMachineFunction();
1804 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1806 SmallVector<CCValAssign, 16> RVLocs;
1807 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
1808 RVLocs, *DAG.getContext());
1809 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
1812 SmallVector<SDValue, 6> RetOps;
1813 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
1814 // Operand #1 = Bytes To Pop
1815 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(),
1818 // Copy the result values into the output registers.
1819 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1820 CCValAssign &VA = RVLocs[i];
1821 assert(VA.isRegLoc() && "Can only return in registers!");
1822 SDValue ValToCopy = OutVals[i];
1823 EVT ValVT = ValToCopy.getValueType();
1825 // Promote values to the appropriate types
1826 if (VA.getLocInfo() == CCValAssign::SExt)
1827 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy);
1828 else if (VA.getLocInfo() == CCValAssign::ZExt)
1829 ValToCopy = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ValToCopy);
1830 else if (VA.getLocInfo() == CCValAssign::AExt)
1831 ValToCopy = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ValToCopy);
1832 else if (VA.getLocInfo() == CCValAssign::BCvt)
1833 ValToCopy = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), ValToCopy);
1835 // If this is x86-64, and we disabled SSE, we can't return FP values,
1836 // or SSE or MMX vectors.
1837 if ((ValVT == MVT::f32 || ValVT == MVT::f64 ||
1838 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) &&
1839 (Subtarget->is64Bit() && !Subtarget->hasSSE1())) {
1840 report_fatal_error("SSE register return with SSE disabled");
1842 // Likewise we can't return F64 values with SSE1 only. gcc does so, but
1843 // llvm-gcc has never done it right and no one has noticed, so this
1844 // should be OK for now.
1845 if (ValVT == MVT::f64 &&
1846 (Subtarget->is64Bit() && !Subtarget->hasSSE2()))
1847 report_fatal_error("SSE2 register return with SSE2 disabled");
1849 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
1850 // the RET instruction and handled by the FP Stackifier.
1851 if (VA.getLocReg() == X86::ST0 ||
1852 VA.getLocReg() == X86::ST1) {
1853 // If this is a copy from an xmm register to ST(0), use an FPExtend to
1854 // change the value to the FP stack register class.
1855 if (isScalarFPTypeInSSEReg(VA.getValVT()))
1856 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
1857 RetOps.push_back(ValToCopy);
1858 // Don't emit a copytoreg.
1862 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
1863 // which is returned in RAX / RDX.
1864 if (Subtarget->is64Bit()) {
1865 if (ValVT == MVT::x86mmx) {
1866 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
1867 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ValToCopy);
1868 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
1870 // If we don't have SSE2 available, convert to v4f32 so the generated
1871 // register is legal.
1872 if (!Subtarget->hasSSE2())
1873 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32,ValToCopy);
1878 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
1879 Flag = Chain.getValue(1);
1880 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
1883 // The x86-64 ABIs require that for returning structs by value we copy
1884 // the sret argument into %rax/%eax (depending on ABI) for the return.
1885 // Win32 requires us to put the sret argument to %eax as well.
1886 // We saved the argument into a virtual register in the entry block,
1887 // so now we copy the value out and into %rax/%eax.
1888 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr() &&
1889 (Subtarget->is64Bit() || Subtarget->isTargetWindows())) {
1890 MachineFunction &MF = DAG.getMachineFunction();
1891 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1892 unsigned Reg = FuncInfo->getSRetReturnReg();
1894 "SRetReturnReg should have been set in LowerFormalArguments().");
1895 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
1898 = (Subtarget->is64Bit() && !Subtarget->isTarget64BitILP32()) ?
1899 X86::RAX : X86::EAX;
1900 Chain = DAG.getCopyToReg(Chain, dl, RetValReg, Val, Flag);
1901 Flag = Chain.getValue(1);
1903 // RAX/EAX now acts like a return value.
1904 RetOps.push_back(DAG.getRegister(RetValReg, getPointerTy()));
1907 RetOps[0] = Chain; // Update chain.
1909 // Add the flag if we have it.
1911 RetOps.push_back(Flag);
1913 return DAG.getNode(X86ISD::RET_FLAG, dl,
1914 MVT::Other, &RetOps[0], RetOps.size());
1917 bool X86TargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
1918 if (N->getNumValues() != 1)
1920 if (!N->hasNUsesOfValue(1, 0))
1923 SDValue TCChain = Chain;
1924 SDNode *Copy = *N->use_begin();
1925 if (Copy->getOpcode() == ISD::CopyToReg) {
1926 // If the copy has a glue operand, we conservatively assume it isn't safe to
1927 // perform a tail call.
1928 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
1930 TCChain = Copy->getOperand(0);
1931 } else if (Copy->getOpcode() != ISD::FP_EXTEND)
1934 bool HasRet = false;
1935 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
1937 if (UI->getOpcode() != X86ISD::RET_FLAG)
1950 X86TargetLowering::getTypeForExtArgOrReturn(MVT VT,
1951 ISD::NodeType ExtendKind) const {
1953 // TODO: Is this also valid on 32-bit?
1954 if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND)
1955 ReturnMVT = MVT::i8;
1957 ReturnMVT = MVT::i32;
1959 MVT MinVT = getRegisterType(ReturnMVT);
1960 return VT.bitsLT(MinVT) ? MinVT : VT;
1963 /// LowerCallResult - Lower the result values of a call into the
1964 /// appropriate copies out of appropriate physical registers.
1967 X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
1968 CallingConv::ID CallConv, bool isVarArg,
1969 const SmallVectorImpl<ISD::InputArg> &Ins,
1970 SDLoc dl, SelectionDAG &DAG,
1971 SmallVectorImpl<SDValue> &InVals) const {
1973 // Assign locations to each value returned by this call.
1974 SmallVector<CCValAssign, 16> RVLocs;
1975 bool Is64Bit = Subtarget->is64Bit();
1976 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
1977 getTargetMachine(), RVLocs, *DAG.getContext());
1978 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
1980 // Copy all of the result registers out of their specified physreg.
1981 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
1982 CCValAssign &VA = RVLocs[i];
1983 EVT CopyVT = VA.getValVT();
1985 // If this is x86-64, and we disabled SSE, we can't return FP values
1986 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
1987 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) {
1988 report_fatal_error("SSE register return with SSE disabled");
1993 // If this is a call to a function that returns an fp value on the floating
1994 // point stack, we must guarantee the value is popped from the stack, so
1995 // a CopyFromReg is not good enough - the copy instruction may be eliminated
1996 // if the return value is not used. We use the FpPOP_RETVAL instruction
1998 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1) {
1999 // If we prefer to use the value in xmm registers, copy it out as f80 and
2000 // use a truncate to move it from fp stack reg to xmm reg.
2001 if (isScalarFPTypeInSSEReg(VA.getValVT())) CopyVT = MVT::f80;
2002 SDValue Ops[] = { Chain, InFlag };
2003 Chain = SDValue(DAG.getMachineNode(X86::FpPOP_RETVAL, dl, CopyVT,
2004 MVT::Other, MVT::Glue, Ops), 1);
2005 Val = Chain.getValue(0);
2007 // Round the f80 to the right size, which also moves it to the appropriate
2009 if (CopyVT != VA.getValVT())
2010 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
2011 // This truncation won't change the value.
2012 DAG.getIntPtrConstant(1));
2014 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
2015 CopyVT, InFlag).getValue(1);
2016 Val = Chain.getValue(0);
2018 InFlag = Chain.getValue(2);
2019 InVals.push_back(Val);
2025 //===----------------------------------------------------------------------===//
2026 // C & StdCall & Fast Calling Convention implementation
2027 //===----------------------------------------------------------------------===//
2028 // StdCall calling convention seems to be standard for many Windows' API
2029 // routines and around. It differs from C calling convention just a little:
2030 // callee should clean up the stack, not caller. Symbols should be also
2031 // decorated in some fancy way :) It doesn't support any vector arguments.
2032 // For info on fast calling convention see Fast Calling Convention (tail call)
2033 // implementation LowerX86_32FastCCCallTo.
2035 /// CallIsStructReturn - Determines whether a call uses struct return
2037 enum StructReturnType {
2042 static StructReturnType
2043 callIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
2045 return NotStructReturn;
2047 const ISD::ArgFlagsTy &Flags = Outs[0].Flags;
2048 if (!Flags.isSRet())
2049 return NotStructReturn;
2050 if (Flags.isInReg())
2051 return RegStructReturn;
2052 return StackStructReturn;
2055 /// ArgsAreStructReturn - Determines whether a function uses struct
2056 /// return semantics.
2057 static StructReturnType
2058 argsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
2060 return NotStructReturn;
2062 const ISD::ArgFlagsTy &Flags = Ins[0].Flags;
2063 if (!Flags.isSRet())
2064 return NotStructReturn;
2065 if (Flags.isInReg())
2066 return RegStructReturn;
2067 return StackStructReturn;
2070 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
2071 /// by "Src" to address "Dst" with size and alignment information specified by
2072 /// the specific parameter attribute. The copy will be passed as a byval
2073 /// function parameter.
2075 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
2076 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
2078 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
2080 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
2081 /*isVolatile*/false, /*AlwaysInline=*/true,
2082 MachinePointerInfo(), MachinePointerInfo());
2085 /// IsTailCallConvention - Return true if the calling convention is one that
2086 /// supports tail call optimization.
2087 static bool IsTailCallConvention(CallingConv::ID CC) {
2088 return (CC == CallingConv::Fast || CC == CallingConv::GHC ||
2089 CC == CallingConv::HiPE);
2092 /// \brief Return true if the calling convention is a C calling convention.
2093 static bool IsCCallConvention(CallingConv::ID CC) {
2094 return (CC == CallingConv::C || CC == CallingConv::X86_64_Win64 ||
2095 CC == CallingConv::X86_64_SysV);
2098 bool X86TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
2099 if (!CI->isTailCall() || getTargetMachine().Options.DisableTailCalls)
2103 CallingConv::ID CalleeCC = CS.getCallingConv();
2104 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
2110 /// FuncIsMadeTailCallSafe - Return true if the function is being made into
2111 /// a tailcall target by changing its ABI.
2112 static bool FuncIsMadeTailCallSafe(CallingConv::ID CC,
2113 bool GuaranteedTailCallOpt) {
2114 return GuaranteedTailCallOpt && IsTailCallConvention(CC);
2118 X86TargetLowering::LowerMemArgument(SDValue Chain,
2119 CallingConv::ID CallConv,
2120 const SmallVectorImpl<ISD::InputArg> &Ins,
2121 SDLoc dl, SelectionDAG &DAG,
2122 const CCValAssign &VA,
2123 MachineFrameInfo *MFI,
2125 // Create the nodes corresponding to a load from this parameter slot.
2126 ISD::ArgFlagsTy Flags = Ins[i].Flags;
2127 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(CallConv,
2128 getTargetMachine().Options.GuaranteedTailCallOpt);
2129 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
2132 // If value is passed by pointer we have address passed instead of the value
2134 if (VA.getLocInfo() == CCValAssign::Indirect)
2135 ValVT = VA.getLocVT();
2137 ValVT = VA.getValVT();
2139 // FIXME: For now, all byval parameter objects are marked mutable. This can be
2140 // changed with more analysis.
2141 // In case of tail call optimization mark all arguments mutable. Since they
2142 // could be overwritten by lowering of arguments in case of a tail call.
2143 if (Flags.isByVal()) {
2144 unsigned Bytes = Flags.getByValSize();
2145 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects.
2146 int FI = MFI->CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable);
2147 return DAG.getFrameIndex(FI, getPointerTy());
2149 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
2150 VA.getLocMemOffset(), isImmutable);
2151 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2152 return DAG.getLoad(ValVT, dl, Chain, FIN,
2153 MachinePointerInfo::getFixedStack(FI),
2154 false, false, false, 0);
2159 X86TargetLowering::LowerFormalArguments(SDValue Chain,
2160 CallingConv::ID CallConv,
2162 const SmallVectorImpl<ISD::InputArg> &Ins,
2165 SmallVectorImpl<SDValue> &InVals)
2167 MachineFunction &MF = DAG.getMachineFunction();
2168 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2170 const Function* Fn = MF.getFunction();
2171 if (Fn->hasExternalLinkage() &&
2172 Subtarget->isTargetCygMing() &&
2173 Fn->getName() == "main")
2174 FuncInfo->setForceFramePointer(true);
2176 MachineFrameInfo *MFI = MF.getFrameInfo();
2177 bool Is64Bit = Subtarget->is64Bit();
2178 bool IsWindows = Subtarget->isTargetWindows();
2179 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2181 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2182 "Var args not supported with calling convention fastcc, ghc or hipe");
2184 // Assign locations to all of the incoming arguments.
2185 SmallVector<CCValAssign, 16> ArgLocs;
2186 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
2187 ArgLocs, *DAG.getContext());
2189 // Allocate shadow area for Win64
2191 CCInfo.AllocateStack(32, 8);
2193 CCInfo.AnalyzeFormalArguments(Ins, CC_X86);
2195 unsigned LastVal = ~0U;
2197 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2198 CCValAssign &VA = ArgLocs[i];
2199 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
2201 assert(VA.getValNo() != LastVal &&
2202 "Don't support value assigned to multiple locs yet");
2204 LastVal = VA.getValNo();
2206 if (VA.isRegLoc()) {
2207 EVT RegVT = VA.getLocVT();
2208 const TargetRegisterClass *RC;
2209 if (RegVT == MVT::i32)
2210 RC = &X86::GR32RegClass;
2211 else if (Is64Bit && RegVT == MVT::i64)
2212 RC = &X86::GR64RegClass;
2213 else if (RegVT == MVT::f32)
2214 RC = &X86::FR32RegClass;
2215 else if (RegVT == MVT::f64)
2216 RC = &X86::FR64RegClass;
2217 else if (RegVT.is512BitVector())
2218 RC = &X86::VR512RegClass;
2219 else if (RegVT.is256BitVector())
2220 RC = &X86::VR256RegClass;
2221 else if (RegVT.is128BitVector())
2222 RC = &X86::VR128RegClass;
2223 else if (RegVT == MVT::x86mmx)
2224 RC = &X86::VR64RegClass;
2225 else if (RegVT == MVT::v8i1)
2226 RC = &X86::VK8RegClass;
2227 else if (RegVT == MVT::v16i1)
2228 RC = &X86::VK16RegClass;
2230 llvm_unreachable("Unknown argument type!");
2232 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2233 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
2235 // If this is an 8 or 16-bit value, it is really passed promoted to 32
2236 // bits. Insert an assert[sz]ext to capture this, then truncate to the
2238 if (VA.getLocInfo() == CCValAssign::SExt)
2239 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
2240 DAG.getValueType(VA.getValVT()));
2241 else if (VA.getLocInfo() == CCValAssign::ZExt)
2242 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
2243 DAG.getValueType(VA.getValVT()));
2244 else if (VA.getLocInfo() == CCValAssign::BCvt)
2245 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
2247 if (VA.isExtInLoc()) {
2248 // Handle MMX values passed in XMM regs.
2249 if (RegVT.isVector())
2250 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(), ArgValue);
2252 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
2255 assert(VA.isMemLoc());
2256 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
2259 // If value is passed via pointer - do a load.
2260 if (VA.getLocInfo() == CCValAssign::Indirect)
2261 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue,
2262 MachinePointerInfo(), false, false, false, 0);
2264 InVals.push_back(ArgValue);
2267 // The x86-64 ABIs require that for returning structs by value we copy
2268 // the sret argument into %rax/%eax (depending on ABI) for the return.
2269 // Win32 requires us to put the sret argument to %eax as well.
2270 // Save the argument into a virtual register so that we can access it
2271 // from the return points.
2272 if (MF.getFunction()->hasStructRetAttr() &&
2273 (Subtarget->is64Bit() || Subtarget->isTargetWindows())) {
2274 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2275 unsigned Reg = FuncInfo->getSRetReturnReg();
2277 MVT PtrTy = getPointerTy();
2278 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(PtrTy));
2279 FuncInfo->setSRetReturnReg(Reg);
2281 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]);
2282 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
2285 unsigned StackSize = CCInfo.getNextStackOffset();
2286 // Align stack specially for tail calls.
2287 if (FuncIsMadeTailCallSafe(CallConv,
2288 MF.getTarget().Options.GuaranteedTailCallOpt))
2289 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
2291 // If the function takes variable number of arguments, make a frame index for
2292 // the start of the first vararg value... for expansion of llvm.va_start.
2294 if (Is64Bit || (CallConv != CallingConv::X86_FastCall &&
2295 CallConv != CallingConv::X86_ThisCall)) {
2296 FuncInfo->setVarArgsFrameIndex(MFI->CreateFixedObject(1, StackSize,true));
2299 unsigned TotalNumIntRegs = 0, TotalNumXMMRegs = 0;
2301 // FIXME: We should really autogenerate these arrays
2302 static const uint16_t GPR64ArgRegsWin64[] = {
2303 X86::RCX, X86::RDX, X86::R8, X86::R9
2305 static const uint16_t GPR64ArgRegs64Bit[] = {
2306 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
2308 static const uint16_t XMMArgRegs64Bit[] = {
2309 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2310 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2312 const uint16_t *GPR64ArgRegs;
2313 unsigned NumXMMRegs = 0;
2316 // The XMM registers which might contain var arg parameters are shadowed
2317 // in their paired GPR. So we only need to save the GPR to their home
2319 TotalNumIntRegs = 4;
2320 GPR64ArgRegs = GPR64ArgRegsWin64;
2322 TotalNumIntRegs = 6; TotalNumXMMRegs = 8;
2323 GPR64ArgRegs = GPR64ArgRegs64Bit;
2325 NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs64Bit,
2328 unsigned NumIntRegs = CCInfo.getFirstUnallocated(GPR64ArgRegs,
2331 bool NoImplicitFloatOps = Fn->getAttributes().
2332 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoImplicitFloat);
2333 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) &&
2334 "SSE register cannot be used when SSE is disabled!");
2335 assert(!(NumXMMRegs && MF.getTarget().Options.UseSoftFloat &&
2336 NoImplicitFloatOps) &&
2337 "SSE register cannot be used when SSE is disabled!");
2338 if (MF.getTarget().Options.UseSoftFloat || NoImplicitFloatOps ||
2339 !Subtarget->hasSSE1())
2340 // Kernel mode asks for SSE to be disabled, so don't push them
2342 TotalNumXMMRegs = 0;
2345 const TargetFrameLowering &TFI = *getTargetMachine().getFrameLowering();
2346 // Get to the caller-allocated home save location. Add 8 to account
2347 // for the return address.
2348 int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
2349 FuncInfo->setRegSaveFrameIndex(
2350 MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false));
2351 // Fixup to set vararg frame on shadow area (4 x i64).
2353 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex());
2355 // For X86-64, if there are vararg parameters that are passed via
2356 // registers, then we must store them to their spots on the stack so
2357 // they may be loaded by deferencing the result of va_next.
2358 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8);
2359 FuncInfo->setVarArgsFPOffset(TotalNumIntRegs * 8 + NumXMMRegs * 16);
2360 FuncInfo->setRegSaveFrameIndex(
2361 MFI->CreateStackObject(TotalNumIntRegs * 8 + TotalNumXMMRegs * 16, 16,
2365 // Store the integer parameter registers.
2366 SmallVector<SDValue, 8> MemOps;
2367 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
2369 unsigned Offset = FuncInfo->getVarArgsGPOffset();
2370 for (; NumIntRegs != TotalNumIntRegs; ++NumIntRegs) {
2371 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN,
2372 DAG.getIntPtrConstant(Offset));
2373 unsigned VReg = MF.addLiveIn(GPR64ArgRegs[NumIntRegs],
2374 &X86::GR64RegClass);
2375 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
2377 DAG.getStore(Val.getValue(1), dl, Val, FIN,
2378 MachinePointerInfo::getFixedStack(
2379 FuncInfo->getRegSaveFrameIndex(), Offset),
2381 MemOps.push_back(Store);
2385 if (TotalNumXMMRegs != 0 && NumXMMRegs != TotalNumXMMRegs) {
2386 // Now store the XMM (fp + vector) parameter registers.
2387 SmallVector<SDValue, 11> SaveXMMOps;
2388 SaveXMMOps.push_back(Chain);
2390 unsigned AL = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
2391 SDValue ALVal = DAG.getCopyFromReg(DAG.getEntryNode(), dl, AL, MVT::i8);
2392 SaveXMMOps.push_back(ALVal);
2394 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2395 FuncInfo->getRegSaveFrameIndex()));
2396 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2397 FuncInfo->getVarArgsFPOffset()));
2399 for (; NumXMMRegs != TotalNumXMMRegs; ++NumXMMRegs) {
2400 unsigned VReg = MF.addLiveIn(XMMArgRegs64Bit[NumXMMRegs],
2401 &X86::VR128RegClass);
2402 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::v4f32);
2403 SaveXMMOps.push_back(Val);
2405 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
2407 &SaveXMMOps[0], SaveXMMOps.size()));
2410 if (!MemOps.empty())
2411 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2412 &MemOps[0], MemOps.size());
2416 // Some CCs need callee pop.
2417 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2418 MF.getTarget().Options.GuaranteedTailCallOpt)) {
2419 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything.
2421 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing.
2422 // If this is an sret function, the return should pop the hidden pointer.
2423 if (!Is64Bit && !IsTailCallConvention(CallConv) && !IsWindows &&
2424 argsAreStructReturn(Ins) == StackStructReturn)
2425 FuncInfo->setBytesToPopOnReturn(4);
2429 // RegSaveFrameIndex is X86-64 only.
2430 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
2431 if (CallConv == CallingConv::X86_FastCall ||
2432 CallConv == CallingConv::X86_ThisCall)
2433 // fastcc functions can't have varargs.
2434 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA);
2437 FuncInfo->setArgumentStackSize(StackSize);
2443 X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
2444 SDValue StackPtr, SDValue Arg,
2445 SDLoc dl, SelectionDAG &DAG,
2446 const CCValAssign &VA,
2447 ISD::ArgFlagsTy Flags) const {
2448 unsigned LocMemOffset = VA.getLocMemOffset();
2449 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
2450 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
2451 if (Flags.isByVal())
2452 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
2454 return DAG.getStore(Chain, dl, Arg, PtrOff,
2455 MachinePointerInfo::getStack(LocMemOffset),
2459 /// EmitTailCallLoadRetAddr - Emit a load of return address if tail call
2460 /// optimization is performed and it is required.
2462 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
2463 SDValue &OutRetAddr, SDValue Chain,
2464 bool IsTailCall, bool Is64Bit,
2465 int FPDiff, SDLoc dl) const {
2466 // Adjust the Return address stack slot.
2467 EVT VT = getPointerTy();
2468 OutRetAddr = getReturnAddressFrameIndex(DAG);
2470 // Load the "old" Return address.
2471 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(),
2472 false, false, false, 0);
2473 return SDValue(OutRetAddr.getNode(), 1);
2476 /// EmitTailCallStoreRetAddr - Emit a store of the return address if tail call
2477 /// optimization is performed and it is required (FPDiff!=0).
2479 EmitTailCallStoreRetAddr(SelectionDAG & DAG, MachineFunction &MF,
2480 SDValue Chain, SDValue RetAddrFrIdx, EVT PtrVT,
2481 unsigned SlotSize, int FPDiff, SDLoc dl) {
2482 // Store the return address to the appropriate stack slot.
2483 if (!FPDiff) return Chain;
2484 // Calculate the new stack slot for the return address.
2485 int NewReturnAddrFI =
2486 MF.getFrameInfo()->CreateFixedObject(SlotSize, (int64_t)FPDiff - SlotSize,
2488 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, PtrVT);
2489 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
2490 MachinePointerInfo::getFixedStack(NewReturnAddrFI),
2496 X86TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
2497 SmallVectorImpl<SDValue> &InVals) const {
2498 SelectionDAG &DAG = CLI.DAG;
2500 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
2501 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
2502 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
2503 SDValue Chain = CLI.Chain;
2504 SDValue Callee = CLI.Callee;
2505 CallingConv::ID CallConv = CLI.CallConv;
2506 bool &isTailCall = CLI.IsTailCall;
2507 bool isVarArg = CLI.IsVarArg;
2509 MachineFunction &MF = DAG.getMachineFunction();
2510 bool Is64Bit = Subtarget->is64Bit();
2511 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2512 bool IsWindows = Subtarget->isTargetWindows();
2513 StructReturnType SR = callIsStructReturn(Outs);
2514 bool IsSibcall = false;
2516 if (MF.getTarget().Options.DisableTailCalls)
2520 // Check if it's really possible to do a tail call.
2521 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
2522 isVarArg, SR != NotStructReturn,
2523 MF.getFunction()->hasStructRetAttr(), CLI.RetTy,
2524 Outs, OutVals, Ins, DAG);
2526 // Sibcalls are automatically detected tailcalls which do not require
2528 if (!MF.getTarget().Options.GuaranteedTailCallOpt && isTailCall)
2535 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2536 "Var args not supported with calling convention fastcc, ghc or hipe");
2538 // Analyze operands of the call, assigning locations to each operand.
2539 SmallVector<CCValAssign, 16> ArgLocs;
2540 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
2541 ArgLocs, *DAG.getContext());
2543 // Allocate shadow area for Win64
2545 CCInfo.AllocateStack(32, 8);
2547 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2549 // Get a count of how many bytes are to be pushed on the stack.
2550 unsigned NumBytes = CCInfo.getNextStackOffset();
2552 // This is a sibcall. The memory operands are available in caller's
2553 // own caller's stack.
2555 else if (getTargetMachine().Options.GuaranteedTailCallOpt &&
2556 IsTailCallConvention(CallConv))
2557 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
2560 if (isTailCall && !IsSibcall) {
2561 // Lower arguments at fp - stackoffset + fpdiff.
2562 X86MachineFunctionInfo *X86Info = MF.getInfo<X86MachineFunctionInfo>();
2563 unsigned NumBytesCallerPushed = X86Info->getBytesToPopOnReturn();
2565 FPDiff = NumBytesCallerPushed - NumBytes;
2567 // Set the delta of movement of the returnaddr stackslot.
2568 // But only set if delta is greater than previous delta.
2569 if (FPDiff < X86Info->getTCReturnAddrDelta())
2570 X86Info->setTCReturnAddrDelta(FPDiff);
2574 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true),
2577 SDValue RetAddrFrIdx;
2578 // Load return address for tail calls.
2579 if (isTailCall && FPDiff)
2580 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall,
2581 Is64Bit, FPDiff, dl);
2583 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
2584 SmallVector<SDValue, 8> MemOpChains;
2587 // Walk the register/memloc assignments, inserting copies/loads. In the case
2588 // of tail call optimization arguments are handle later.
2589 const X86RegisterInfo *RegInfo =
2590 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
2591 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2592 CCValAssign &VA = ArgLocs[i];
2593 EVT RegVT = VA.getLocVT();
2594 SDValue Arg = OutVals[i];
2595 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2596 bool isByVal = Flags.isByVal();
2598 // Promote the value if needed.
2599 switch (VA.getLocInfo()) {
2600 default: llvm_unreachable("Unknown loc info!");
2601 case CCValAssign::Full: break;
2602 case CCValAssign::SExt:
2603 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
2605 case CCValAssign::ZExt:
2606 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
2608 case CCValAssign::AExt:
2609 if (RegVT.is128BitVector()) {
2610 // Special case: passing MMX values in XMM registers.
2611 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg);
2612 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
2613 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
2615 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
2617 case CCValAssign::BCvt:
2618 Arg = DAG.getNode(ISD::BITCAST, dl, RegVT, Arg);
2620 case CCValAssign::Indirect: {
2621 // Store the argument.
2622 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
2623 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
2624 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot,
2625 MachinePointerInfo::getFixedStack(FI),
2632 if (VA.isRegLoc()) {
2633 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2634 if (isVarArg && IsWin64) {
2635 // Win64 ABI requires argument XMM reg to be copied to the corresponding
2636 // shadow reg if callee is a varargs function.
2637 unsigned ShadowReg = 0;
2638 switch (VA.getLocReg()) {
2639 case X86::XMM0: ShadowReg = X86::RCX; break;
2640 case X86::XMM1: ShadowReg = X86::RDX; break;
2641 case X86::XMM2: ShadowReg = X86::R8; break;
2642 case X86::XMM3: ShadowReg = X86::R9; break;
2645 RegsToPass.push_back(std::make_pair(ShadowReg, Arg));
2647 } else if (!IsSibcall && (!isTailCall || isByVal)) {
2648 assert(VA.isMemLoc());
2649 if (StackPtr.getNode() == 0)
2650 StackPtr = DAG.getCopyFromReg(Chain, dl, RegInfo->getStackRegister(),
2652 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
2653 dl, DAG, VA, Flags));
2657 if (!MemOpChains.empty())
2658 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2659 &MemOpChains[0], MemOpChains.size());
2661 if (Subtarget->isPICStyleGOT()) {
2662 // ELF / PIC requires GOT in the EBX register before function calls via PLT
2665 RegsToPass.push_back(std::make_pair(unsigned(X86::EBX),
2666 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), getPointerTy())));
2668 // If we are tail calling and generating PIC/GOT style code load the
2669 // address of the callee into ECX. The value in ecx is used as target of
2670 // the tail jump. This is done to circumvent the ebx/callee-saved problem
2671 // for tail calls on PIC/GOT architectures. Normally we would just put the
2672 // address of GOT into ebx and then call target@PLT. But for tail calls
2673 // ebx would be restored (since ebx is callee saved) before jumping to the
2676 // Note: The actual moving to ECX is done further down.
2677 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
2678 if (G && !G->getGlobal()->hasHiddenVisibility() &&
2679 !G->getGlobal()->hasProtectedVisibility())
2680 Callee = LowerGlobalAddress(Callee, DAG);
2681 else if (isa<ExternalSymbolSDNode>(Callee))
2682 Callee = LowerExternalSymbol(Callee, DAG);
2686 if (Is64Bit && isVarArg && !IsWin64) {
2687 // From AMD64 ABI document:
2688 // For calls that may call functions that use varargs or stdargs
2689 // (prototype-less calls or calls to functions containing ellipsis (...) in
2690 // the declaration) %al is used as hidden argument to specify the number
2691 // of SSE registers used. The contents of %al do not need to match exactly
2692 // the number of registers, but must be an ubound on the number of SSE
2693 // registers used and is in the range 0 - 8 inclusive.
2695 // Count the number of XMM registers allocated.
2696 static const uint16_t XMMArgRegs[] = {
2697 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2698 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2700 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
2701 assert((Subtarget->hasSSE1() || !NumXMMRegs)
2702 && "SSE registers cannot be used when SSE is disabled");
2704 RegsToPass.push_back(std::make_pair(unsigned(X86::AL),
2705 DAG.getConstant(NumXMMRegs, MVT::i8)));
2708 // For tail calls lower the arguments to the 'real' stack slot.
2710 // Force all the incoming stack arguments to be loaded from the stack
2711 // before any new outgoing arguments are stored to the stack, because the
2712 // outgoing stack slots may alias the incoming argument stack slots, and
2713 // the alias isn't otherwise explicit. This is slightly more conservative
2714 // than necessary, because it means that each store effectively depends
2715 // on every argument instead of just those arguments it would clobber.
2716 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
2718 SmallVector<SDValue, 8> MemOpChains2;
2721 if (getTargetMachine().Options.GuaranteedTailCallOpt) {
2722 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2723 CCValAssign &VA = ArgLocs[i];
2726 assert(VA.isMemLoc());
2727 SDValue Arg = OutVals[i];
2728 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2729 // Create frame index.
2730 int32_t Offset = VA.getLocMemOffset()+FPDiff;
2731 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
2732 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
2733 FIN = DAG.getFrameIndex(FI, getPointerTy());
2735 if (Flags.isByVal()) {
2736 // Copy relative to framepointer.
2737 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset());
2738 if (StackPtr.getNode() == 0)
2739 StackPtr = DAG.getCopyFromReg(Chain, dl,
2740 RegInfo->getStackRegister(),
2742 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source);
2744 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
2748 // Store relative to framepointer.
2749 MemOpChains2.push_back(
2750 DAG.getStore(ArgChain, dl, Arg, FIN,
2751 MachinePointerInfo::getFixedStack(FI),
2757 if (!MemOpChains2.empty())
2758 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2759 &MemOpChains2[0], MemOpChains2.size());
2761 // Store the return address to the appropriate stack slot.
2762 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx,
2763 getPointerTy(), RegInfo->getSlotSize(),
2767 // Build a sequence of copy-to-reg nodes chained together with token chain
2768 // and flag operands which copy the outgoing args into registers.
2770 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2771 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
2772 RegsToPass[i].second, InFlag);
2773 InFlag = Chain.getValue(1);
2776 if (getTargetMachine().getCodeModel() == CodeModel::Large) {
2777 assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
2778 // In the 64-bit large code model, we have to make all calls
2779 // through a register, since the call instruction's 32-bit
2780 // pc-relative offset may not be large enough to hold the whole
2782 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2783 // If the callee is a GlobalAddress node (quite common, every direct call
2784 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
2787 // We should use extra load for direct calls to dllimported functions in
2789 const GlobalValue *GV = G->getGlobal();
2790 if (!GV->hasDLLImportLinkage()) {
2791 unsigned char OpFlags = 0;
2792 bool ExtraLoad = false;
2793 unsigned WrapperKind = ISD::DELETED_NODE;
2795 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
2796 // external symbols most go through the PLT in PIC mode. If the symbol
2797 // has hidden or protected visibility, or if it is static or local, then
2798 // we don't need to use the PLT - we can directly call it.
2799 if (Subtarget->isTargetELF() &&
2800 getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
2801 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
2802 OpFlags = X86II::MO_PLT;
2803 } else if (Subtarget->isPICStyleStubAny() &&
2804 (GV->isDeclaration() || GV->isWeakForLinker()) &&
2805 (!Subtarget->getTargetTriple().isMacOSX() ||
2806 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
2807 // PC-relative references to external symbols should go through $stub,
2808 // unless we're building with the leopard linker or later, which
2809 // automatically synthesizes these stubs.
2810 OpFlags = X86II::MO_DARWIN_STUB;
2811 } else if (Subtarget->isPICStyleRIPRel() &&
2812 isa<Function>(GV) &&
2813 cast<Function>(GV)->getAttributes().
2814 hasAttribute(AttributeSet::FunctionIndex,
2815 Attribute::NonLazyBind)) {
2816 // If the function is marked as non-lazy, generate an indirect call
2817 // which loads from the GOT directly. This avoids runtime overhead
2818 // at the cost of eager binding (and one extra byte of encoding).
2819 OpFlags = X86II::MO_GOTPCREL;
2820 WrapperKind = X86ISD::WrapperRIP;
2824 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(),
2825 G->getOffset(), OpFlags);
2827 // Add a wrapper if needed.
2828 if (WrapperKind != ISD::DELETED_NODE)
2829 Callee = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Callee);
2830 // Add extra indirection if needed.
2832 Callee = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Callee,
2833 MachinePointerInfo::getGOT(),
2834 false, false, false, 0);
2836 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
2837 unsigned char OpFlags = 0;
2839 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to
2840 // external symbols should go through the PLT.
2841 if (Subtarget->isTargetELF() &&
2842 getTargetMachine().getRelocationModel() == Reloc::PIC_) {
2843 OpFlags = X86II::MO_PLT;
2844 } else if (Subtarget->isPICStyleStubAny() &&
2845 (!Subtarget->getTargetTriple().isMacOSX() ||
2846 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
2847 // PC-relative references to external symbols should go through $stub,
2848 // unless we're building with the leopard linker or later, which
2849 // automatically synthesizes these stubs.
2850 OpFlags = X86II::MO_DARWIN_STUB;
2853 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(),
2857 // Returns a chain & a flag for retval copy to use.
2858 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
2859 SmallVector<SDValue, 8> Ops;
2861 if (!IsSibcall && isTailCall) {
2862 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
2863 DAG.getIntPtrConstant(0, true), InFlag, dl);
2864 InFlag = Chain.getValue(1);
2867 Ops.push_back(Chain);
2868 Ops.push_back(Callee);
2871 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32));
2873 // Add argument registers to the end of the list so that they are known live
2875 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
2876 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
2877 RegsToPass[i].second.getValueType()));
2879 // Add a register mask operand representing the call-preserved registers.
2880 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
2881 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv);
2882 assert(Mask && "Missing call preserved mask for calling convention");
2883 Ops.push_back(DAG.getRegisterMask(Mask));
2885 if (InFlag.getNode())
2886 Ops.push_back(InFlag);
2890 //// If this is the first return lowered for this function, add the regs
2891 //// to the liveout set for the function.
2892 // This isn't right, although it's probably harmless on x86; liveouts
2893 // should be computed from returns not tail calls. Consider a void
2894 // function making a tail call to a function returning int.
2895 return DAG.getNode(X86ISD::TC_RETURN, dl, NodeTys, &Ops[0], Ops.size());
2898 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, &Ops[0], Ops.size());
2899 InFlag = Chain.getValue(1);
2901 // Create the CALLSEQ_END node.
2902 unsigned NumBytesForCalleeToPush;
2903 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2904 getTargetMachine().Options.GuaranteedTailCallOpt))
2905 NumBytesForCalleeToPush = NumBytes; // Callee pops everything
2906 else if (!Is64Bit && !IsTailCallConvention(CallConv) && !IsWindows &&
2907 SR == StackStructReturn)
2908 // If this is a call to a struct-return function, the callee
2909 // pops the hidden struct pointer, so we have to push it back.
2910 // This is common for Darwin/X86, Linux & Mingw32 targets.
2911 // For MSVC Win32 targets, the caller pops the hidden struct pointer.
2912 NumBytesForCalleeToPush = 4;
2914 NumBytesForCalleeToPush = 0; // Callee pops nothing.
2916 // Returns a flag for retval copy to use.
2918 Chain = DAG.getCALLSEQ_END(Chain,
2919 DAG.getIntPtrConstant(NumBytes, true),
2920 DAG.getIntPtrConstant(NumBytesForCalleeToPush,
2923 InFlag = Chain.getValue(1);
2926 // Handle result values, copying them out of physregs into vregs that we
2928 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
2929 Ins, dl, DAG, InVals);
2932 //===----------------------------------------------------------------------===//
2933 // Fast Calling Convention (tail call) implementation
2934 //===----------------------------------------------------------------------===//
2936 // Like std call, callee cleans arguments, convention except that ECX is
2937 // reserved for storing the tail called function address. Only 2 registers are
2938 // free for argument passing (inreg). Tail call optimization is performed
2940 // * tailcallopt is enabled
2941 // * caller/callee are fastcc
2942 // On X86_64 architecture with GOT-style position independent code only local
2943 // (within module) calls are supported at the moment.
2944 // To keep the stack aligned according to platform abi the function
2945 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
2946 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
2947 // If a tail called function callee has more arguments than the caller the
2948 // caller needs to make sure that there is room to move the RETADDR to. This is
2949 // achieved by reserving an area the size of the argument delta right after the
2950 // original REtADDR, but before the saved framepointer or the spilled registers
2951 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
2963 /// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned
2964 /// for a 16 byte align requirement.
2966 X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
2967 SelectionDAG& DAG) const {
2968 MachineFunction &MF = DAG.getMachineFunction();
2969 const TargetMachine &TM = MF.getTarget();
2970 const X86RegisterInfo *RegInfo =
2971 static_cast<const X86RegisterInfo*>(TM.getRegisterInfo());
2972 const TargetFrameLowering &TFI = *TM.getFrameLowering();
2973 unsigned StackAlignment = TFI.getStackAlignment();
2974 uint64_t AlignMask = StackAlignment - 1;
2975 int64_t Offset = StackSize;
2976 unsigned SlotSize = RegInfo->getSlotSize();
2977 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
2978 // Number smaller than 12 so just add the difference.
2979 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
2981 // Mask out lower bits, add stackalignment once plus the 12 bytes.
2982 Offset = ((~AlignMask) & Offset) + StackAlignment +
2983 (StackAlignment-SlotSize);
2988 /// MatchingStackOffset - Return true if the given stack call argument is
2989 /// already available in the same position (relatively) of the caller's
2990 /// incoming argument stack.
2992 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
2993 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
2994 const X86InstrInfo *TII) {
2995 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
2997 if (Arg.getOpcode() == ISD::CopyFromReg) {
2998 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
2999 if (!TargetRegisterInfo::isVirtualRegister(VR))
3001 MachineInstr *Def = MRI->getVRegDef(VR);
3004 if (!Flags.isByVal()) {
3005 if (!TII->isLoadFromStackSlot(Def, FI))
3008 unsigned Opcode = Def->getOpcode();
3009 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r) &&
3010 Def->getOperand(1).isFI()) {
3011 FI = Def->getOperand(1).getIndex();
3012 Bytes = Flags.getByValSize();
3016 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
3017 if (Flags.isByVal())
3018 // ByVal argument is passed in as a pointer but it's now being
3019 // dereferenced. e.g.
3020 // define @foo(%struct.X* %A) {
3021 // tail call @bar(%struct.X* byval %A)
3024 SDValue Ptr = Ld->getBasePtr();
3025 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
3028 FI = FINode->getIndex();
3029 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) {
3030 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg);
3031 FI = FINode->getIndex();
3032 Bytes = Flags.getByValSize();
3036 assert(FI != INT_MAX);
3037 if (!MFI->isFixedObjectIndex(FI))
3039 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
3042 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
3043 /// for tail call optimization. Targets which want to do tail call
3044 /// optimization should implement this function.
3046 X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
3047 CallingConv::ID CalleeCC,
3049 bool isCalleeStructRet,
3050 bool isCallerStructRet,
3052 const SmallVectorImpl<ISD::OutputArg> &Outs,
3053 const SmallVectorImpl<SDValue> &OutVals,
3054 const SmallVectorImpl<ISD::InputArg> &Ins,
3055 SelectionDAG &DAG) const {
3056 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
3059 // If -tailcallopt is specified, make fastcc functions tail-callable.
3060 const MachineFunction &MF = DAG.getMachineFunction();
3061 const Function *CallerF = MF.getFunction();
3063 // If the function return type is x86_fp80 and the callee return type is not,
3064 // then the FP_EXTEND of the call result is not a nop. It's not safe to
3065 // perform a tailcall optimization here.
3066 if (CallerF->getReturnType()->isX86_FP80Ty() && !RetTy->isX86_FP80Ty())
3069 CallingConv::ID CallerCC = CallerF->getCallingConv();
3070 bool CCMatch = CallerCC == CalleeCC;
3071 bool IsCalleeWin64 = Subtarget->isCallingConvWin64(CalleeCC);
3072 bool IsCallerWin64 = Subtarget->isCallingConvWin64(CallerCC);
3074 if (getTargetMachine().Options.GuaranteedTailCallOpt) {
3075 if (IsTailCallConvention(CalleeCC) && CCMatch)
3080 // Look for obvious safe cases to perform tail call optimization that do not
3081 // require ABI changes. This is what gcc calls sibcall.
3083 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
3084 // emit a special epilogue.
3085 const X86RegisterInfo *RegInfo =
3086 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
3087 if (RegInfo->needsStackRealignment(MF))
3090 // Also avoid sibcall optimization if either caller or callee uses struct
3091 // return semantics.
3092 if (isCalleeStructRet || isCallerStructRet)
3095 // An stdcall/thiscall caller is expected to clean up its arguments; the
3096 // callee isn't going to do that.
3097 // FIXME: this is more restrictive than needed. We could produce a tailcall
3098 // when the stack adjustment matches. For example, with a thiscall that takes
3099 // only one argument.
3100 if (!CCMatch && (CallerCC == CallingConv::X86_StdCall ||
3101 CallerCC == CallingConv::X86_ThisCall))
3104 // Do not sibcall optimize vararg calls unless all arguments are passed via
3106 if (isVarArg && !Outs.empty()) {
3108 // Optimizing for varargs on Win64 is unlikely to be safe without
3109 // additional testing.
3110 if (IsCalleeWin64 || IsCallerWin64)
3113 SmallVector<CCValAssign, 16> ArgLocs;
3114 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(),
3115 getTargetMachine(), ArgLocs, *DAG.getContext());
3117 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3118 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
3119 if (!ArgLocs[i].isRegLoc())
3123 // If the call result is in ST0 / ST1, it needs to be popped off the x87
3124 // stack. Therefore, if it's not used by the call it is not safe to optimize
3125 // this into a sibcall.
3126 bool Unused = false;
3127 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
3134 SmallVector<CCValAssign, 16> RVLocs;
3135 CCState CCInfo(CalleeCC, false, DAG.getMachineFunction(),
3136 getTargetMachine(), RVLocs, *DAG.getContext());
3137 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
3138 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
3139 CCValAssign &VA = RVLocs[i];
3140 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1)
3145 // If the calling conventions do not match, then we'd better make sure the
3146 // results are returned in the same way as what the caller expects.
3148 SmallVector<CCValAssign, 16> RVLocs1;
3149 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(),
3150 getTargetMachine(), RVLocs1, *DAG.getContext());
3151 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86);
3153 SmallVector<CCValAssign, 16> RVLocs2;
3154 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(),
3155 getTargetMachine(), RVLocs2, *DAG.getContext());
3156 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86);
3158 if (RVLocs1.size() != RVLocs2.size())
3160 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
3161 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
3163 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
3165 if (RVLocs1[i].isRegLoc()) {
3166 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
3169 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
3175 // If the callee takes no arguments then go on to check the results of the
3177 if (!Outs.empty()) {
3178 // Check if stack adjustment is needed. For now, do not do this if any
3179 // argument is passed on the stack.
3180 SmallVector<CCValAssign, 16> ArgLocs;
3181 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(),
3182 getTargetMachine(), ArgLocs, *DAG.getContext());
3184 // Allocate shadow area for Win64
3186 CCInfo.AllocateStack(32, 8);
3188 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3189 if (CCInfo.getNextStackOffset()) {
3190 MachineFunction &MF = DAG.getMachineFunction();
3191 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn())
3194 // Check if the arguments are already laid out in the right way as
3195 // the caller's fixed stack objects.
3196 MachineFrameInfo *MFI = MF.getFrameInfo();
3197 const MachineRegisterInfo *MRI = &MF.getRegInfo();
3198 const X86InstrInfo *TII =
3199 ((const X86TargetMachine&)getTargetMachine()).getInstrInfo();
3200 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3201 CCValAssign &VA = ArgLocs[i];
3202 SDValue Arg = OutVals[i];
3203 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3204 if (VA.getLocInfo() == CCValAssign::Indirect)
3206 if (!VA.isRegLoc()) {
3207 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
3214 // If the tailcall address may be in a register, then make sure it's
3215 // possible to register allocate for it. In 32-bit, the call address can
3216 // only target EAX, EDX, or ECX since the tail call must be scheduled after
3217 // callee-saved registers are restored. These happen to be the same
3218 // registers used to pass 'inreg' arguments so watch out for those.
3219 if (!Subtarget->is64Bit() &&
3220 ((!isa<GlobalAddressSDNode>(Callee) &&
3221 !isa<ExternalSymbolSDNode>(Callee)) ||
3222 getTargetMachine().getRelocationModel() == Reloc::PIC_)) {
3223 unsigned NumInRegs = 0;
3224 // In PIC we need an extra register to formulate the address computation
3226 unsigned MaxInRegs =
3227 (getTargetMachine().getRelocationModel() == Reloc::PIC_) ? 2 : 3;
3229 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3230 CCValAssign &VA = ArgLocs[i];
3233 unsigned Reg = VA.getLocReg();
3236 case X86::EAX: case X86::EDX: case X86::ECX:
3237 if (++NumInRegs == MaxInRegs)
3249 X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
3250 const TargetLibraryInfo *libInfo) const {
3251 return X86::createFastISel(funcInfo, libInfo);
3254 //===----------------------------------------------------------------------===//
3255 // Other Lowering Hooks
3256 //===----------------------------------------------------------------------===//
3258 static bool MayFoldLoad(SDValue Op) {
3259 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode());
3262 static bool MayFoldIntoStore(SDValue Op) {
3263 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin());
3266 static bool isTargetShuffle(unsigned Opcode) {
3268 default: return false;
3269 case X86ISD::PSHUFD:
3270 case X86ISD::PSHUFHW:
3271 case X86ISD::PSHUFLW:
3273 case X86ISD::PALIGNR:
3274 case X86ISD::MOVLHPS:
3275 case X86ISD::MOVLHPD:
3276 case X86ISD::MOVHLPS:
3277 case X86ISD::MOVLPS:
3278 case X86ISD::MOVLPD:
3279 case X86ISD::MOVSHDUP:
3280 case X86ISD::MOVSLDUP:
3281 case X86ISD::MOVDDUP:
3284 case X86ISD::UNPCKL:
3285 case X86ISD::UNPCKH:
3286 case X86ISD::VPERMILP:
3287 case X86ISD::VPERM2X128:
3288 case X86ISD::VPERMI:
3293 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3294 SDValue V1, SelectionDAG &DAG) {
3296 default: llvm_unreachable("Unknown x86 shuffle node");
3297 case X86ISD::MOVSHDUP:
3298 case X86ISD::MOVSLDUP:
3299 case X86ISD::MOVDDUP:
3300 return DAG.getNode(Opc, dl, VT, V1);
3304 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3305 SDValue V1, unsigned TargetMask,
3306 SelectionDAG &DAG) {
3308 default: llvm_unreachable("Unknown x86 shuffle node");
3309 case X86ISD::PSHUFD:
3310 case X86ISD::PSHUFHW:
3311 case X86ISD::PSHUFLW:
3312 case X86ISD::VPERMILP:
3313 case X86ISD::VPERMI:
3314 return DAG.getNode(Opc, dl, VT, V1, DAG.getConstant(TargetMask, MVT::i8));
3318 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3319 SDValue V1, SDValue V2, unsigned TargetMask,
3320 SelectionDAG &DAG) {
3322 default: llvm_unreachable("Unknown x86 shuffle node");
3323 case X86ISD::PALIGNR:
3325 case X86ISD::VPERM2X128:
3326 return DAG.getNode(Opc, dl, VT, V1, V2,
3327 DAG.getConstant(TargetMask, MVT::i8));
3331 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3332 SDValue V1, SDValue V2, SelectionDAG &DAG) {
3334 default: llvm_unreachable("Unknown x86 shuffle node");
3335 case X86ISD::MOVLHPS:
3336 case X86ISD::MOVLHPD:
3337 case X86ISD::MOVHLPS:
3338 case X86ISD::MOVLPS:
3339 case X86ISD::MOVLPD:
3342 case X86ISD::UNPCKL:
3343 case X86ISD::UNPCKH:
3344 return DAG.getNode(Opc, dl, VT, V1, V2);
3348 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
3349 MachineFunction &MF = DAG.getMachineFunction();
3350 const X86RegisterInfo *RegInfo =
3351 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
3352 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
3353 int ReturnAddrIndex = FuncInfo->getRAIndex();
3355 if (ReturnAddrIndex == 0) {
3356 // Set up a frame object for the return address.
3357 unsigned SlotSize = RegInfo->getSlotSize();
3358 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize,
3361 FuncInfo->setRAIndex(ReturnAddrIndex);
3364 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
3367 bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
3368 bool hasSymbolicDisplacement) {
3369 // Offset should fit into 32 bit immediate field.
3370 if (!isInt<32>(Offset))
3373 // If we don't have a symbolic displacement - we don't have any extra
3375 if (!hasSymbolicDisplacement)
3378 // FIXME: Some tweaks might be needed for medium code model.
3379 if (M != CodeModel::Small && M != CodeModel::Kernel)
3382 // For small code model we assume that latest object is 16MB before end of 31
3383 // bits boundary. We may also accept pretty large negative constants knowing
3384 // that all objects are in the positive half of address space.
3385 if (M == CodeModel::Small && Offset < 16*1024*1024)
3388 // For kernel code model we know that all object resist in the negative half
3389 // of 32bits address space. We may not accept negative offsets, since they may
3390 // be just off and we may accept pretty large positive ones.
3391 if (M == CodeModel::Kernel && Offset > 0)
3397 /// isCalleePop - Determines whether the callee is required to pop its
3398 /// own arguments. Callee pop is necessary to support tail calls.
3399 bool X86::isCalleePop(CallingConv::ID CallingConv,
3400 bool is64Bit, bool IsVarArg, bool TailCallOpt) {
3404 switch (CallingConv) {
3407 case CallingConv::X86_StdCall:
3409 case CallingConv::X86_FastCall:
3411 case CallingConv::X86_ThisCall:
3413 case CallingConv::Fast:
3415 case CallingConv::GHC:
3417 case CallingConv::HiPE:
3422 /// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86
3423 /// specific condition code, returning the condition code and the LHS/RHS of the
3424 /// comparison to make.
3425 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
3426 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
3428 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
3429 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
3430 // X > -1 -> X == 0, jump !sign.
3431 RHS = DAG.getConstant(0, RHS.getValueType());
3432 return X86::COND_NS;
3434 if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
3435 // X < 0 -> X == 0, jump on sign.
3438 if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
3440 RHS = DAG.getConstant(0, RHS.getValueType());
3441 return X86::COND_LE;
3445 switch (SetCCOpcode) {
3446 default: llvm_unreachable("Invalid integer condition!");
3447 case ISD::SETEQ: return X86::COND_E;
3448 case ISD::SETGT: return X86::COND_G;
3449 case ISD::SETGE: return X86::COND_GE;
3450 case ISD::SETLT: return X86::COND_L;
3451 case ISD::SETLE: return X86::COND_LE;
3452 case ISD::SETNE: return X86::COND_NE;
3453 case ISD::SETULT: return X86::COND_B;
3454 case ISD::SETUGT: return X86::COND_A;
3455 case ISD::SETULE: return X86::COND_BE;
3456 case ISD::SETUGE: return X86::COND_AE;
3460 // First determine if it is required or is profitable to flip the operands.
3462 // If LHS is a foldable load, but RHS is not, flip the condition.
3463 if (ISD::isNON_EXTLoad(LHS.getNode()) &&
3464 !ISD::isNON_EXTLoad(RHS.getNode())) {
3465 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
3466 std::swap(LHS, RHS);
3469 switch (SetCCOpcode) {
3475 std::swap(LHS, RHS);
3479 // On a floating point condition, the flags are set as follows:
3481 // 0 | 0 | 0 | X > Y
3482 // 0 | 0 | 1 | X < Y
3483 // 1 | 0 | 0 | X == Y
3484 // 1 | 1 | 1 | unordered
3485 switch (SetCCOpcode) {
3486 default: llvm_unreachable("Condcode should be pre-legalized away");
3488 case ISD::SETEQ: return X86::COND_E;
3489 case ISD::SETOLT: // flipped
3491 case ISD::SETGT: return X86::COND_A;
3492 case ISD::SETOLE: // flipped
3494 case ISD::SETGE: return X86::COND_AE;
3495 case ISD::SETUGT: // flipped
3497 case ISD::SETLT: return X86::COND_B;
3498 case ISD::SETUGE: // flipped
3500 case ISD::SETLE: return X86::COND_BE;
3502 case ISD::SETNE: return X86::COND_NE;
3503 case ISD::SETUO: return X86::COND_P;
3504 case ISD::SETO: return X86::COND_NP;
3506 case ISD::SETUNE: return X86::COND_INVALID;
3510 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
3511 /// code. Current x86 isa includes the following FP cmov instructions:
3512 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
3513 static bool hasFPCMov(unsigned X86CC) {
3529 /// isFPImmLegal - Returns true if the target can instruction select the
3530 /// specified FP immediate natively. If false, the legalizer will
3531 /// materialize the FP immediate as a load from a constant pool.
3532 bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
3533 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
3534 if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
3540 /// isUndefOrInRange - Return true if Val is undef or if its value falls within
3541 /// the specified range (L, H].
3542 static bool isUndefOrInRange(int Val, int Low, int Hi) {
3543 return (Val < 0) || (Val >= Low && Val < Hi);
3546 /// isUndefOrEqual - Val is either less than zero (undef) or equal to the
3547 /// specified value.
3548 static bool isUndefOrEqual(int Val, int CmpVal) {
3549 return (Val < 0 || Val == CmpVal);
3552 /// isSequentialOrUndefInRange - Return true if every element in Mask, beginning
3553 /// from position Pos and ending in Pos+Size, falls within the specified
3554 /// sequential range (L, L+Pos]. or is undef.
3555 static bool isSequentialOrUndefInRange(ArrayRef<int> Mask,
3556 unsigned Pos, unsigned Size, int Low) {
3557 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low)
3558 if (!isUndefOrEqual(Mask[i], Low))
3563 /// isPSHUFDMask - Return true if the node specifies a shuffle of elements that
3564 /// is suitable for input to PSHUFD or PSHUFW. That is, it doesn't reference
3565 /// the second operand.
3566 static bool isPSHUFDMask(ArrayRef<int> Mask, MVT VT) {
3567 if (VT == MVT::v4f32 || VT == MVT::v4i32 )
3568 return (Mask[0] < 4 && Mask[1] < 4 && Mask[2] < 4 && Mask[3] < 4);
3569 if (VT == MVT::v2f64 || VT == MVT::v2i64)
3570 return (Mask[0] < 2 && Mask[1] < 2);
3574 /// isPSHUFHWMask - Return true if the node specifies a shuffle of elements that
3575 /// is suitable for input to PSHUFHW.
3576 static bool isPSHUFHWMask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
3577 if (VT != MVT::v8i16 && (!HasInt256 || VT != MVT::v16i16))
3580 // Lower quadword copied in order or undef.
3581 if (!isSequentialOrUndefInRange(Mask, 0, 4, 0))
3584 // Upper quadword shuffled.
3585 for (unsigned i = 4; i != 8; ++i)
3586 if (!isUndefOrInRange(Mask[i], 4, 8))
3589 if (VT == MVT::v16i16) {
3590 // Lower quadword copied in order or undef.
3591 if (!isSequentialOrUndefInRange(Mask, 8, 4, 8))
3594 // Upper quadword shuffled.
3595 for (unsigned i = 12; i != 16; ++i)
3596 if (!isUndefOrInRange(Mask[i], 12, 16))
3603 /// isPSHUFLWMask - Return true if the node specifies a shuffle of elements that
3604 /// is suitable for input to PSHUFLW.
3605 static bool isPSHUFLWMask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
3606 if (VT != MVT::v8i16 && (!HasInt256 || VT != MVT::v16i16))
3609 // Upper quadword copied in order.
3610 if (!isSequentialOrUndefInRange(Mask, 4, 4, 4))
3613 // Lower quadword shuffled.
3614 for (unsigned i = 0; i != 4; ++i)
3615 if (!isUndefOrInRange(Mask[i], 0, 4))
3618 if (VT == MVT::v16i16) {
3619 // Upper quadword copied in order.
3620 if (!isSequentialOrUndefInRange(Mask, 12, 4, 12))
3623 // Lower quadword shuffled.
3624 for (unsigned i = 8; i != 12; ++i)
3625 if (!isUndefOrInRange(Mask[i], 8, 12))
3632 /// isPALIGNRMask - Return true if the node specifies a shuffle of elements that
3633 /// is suitable for input to PALIGNR.
3634 static bool isPALIGNRMask(ArrayRef<int> Mask, MVT VT,
3635 const X86Subtarget *Subtarget) {
3636 if ((VT.is128BitVector() && !Subtarget->hasSSSE3()) ||
3637 (VT.is256BitVector() && !Subtarget->hasInt256()))
3640 unsigned NumElts = VT.getVectorNumElements();
3641 unsigned NumLanes = VT.is512BitVector() ? 1: VT.getSizeInBits()/128;
3642 unsigned NumLaneElts = NumElts/NumLanes;
3644 // Do not handle 64-bit element shuffles with palignr.
3645 if (NumLaneElts == 2)
3648 for (unsigned l = 0; l != NumElts; l+=NumLaneElts) {
3650 for (i = 0; i != NumLaneElts; ++i) {
3655 // Lane is all undef, go to next lane
3656 if (i == NumLaneElts)
3659 int Start = Mask[i+l];
3661 // Make sure its in this lane in one of the sources
3662 if (!isUndefOrInRange(Start, l, l+NumLaneElts) &&
3663 !isUndefOrInRange(Start, l+NumElts, l+NumElts+NumLaneElts))
3666 // If not lane 0, then we must match lane 0
3667 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Start, Mask[i]+l))
3670 // Correct second source to be contiguous with first source
3671 if (Start >= (int)NumElts)
3672 Start -= NumElts - NumLaneElts;
3674 // Make sure we're shifting in the right direction.
3675 if (Start <= (int)(i+l))
3680 // Check the rest of the elements to see if they are consecutive.
3681 for (++i; i != NumLaneElts; ++i) {
3682 int Idx = Mask[i+l];
3684 // Make sure its in this lane
3685 if (!isUndefOrInRange(Idx, l, l+NumLaneElts) &&
3686 !isUndefOrInRange(Idx, l+NumElts, l+NumElts+NumLaneElts))
3689 // If not lane 0, then we must match lane 0
3690 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Idx, Mask[i]+l))
3693 if (Idx >= (int)NumElts)
3694 Idx -= NumElts - NumLaneElts;
3696 if (!isUndefOrEqual(Idx, Start+i))
3705 /// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming
3706 /// the two vector operands have swapped position.
3707 static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask,
3708 unsigned NumElems) {
3709 for (unsigned i = 0; i != NumElems; ++i) {
3713 else if (idx < (int)NumElems)
3714 Mask[i] = idx + NumElems;
3716 Mask[i] = idx - NumElems;
3720 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
3721 /// specifies a shuffle of elements that is suitable for input to 128/256-bit
3722 /// SHUFPS and SHUFPD. If Commuted is true, then it checks for sources to be
3723 /// reverse of what x86 shuffles want.
3724 static bool isSHUFPMask(ArrayRef<int> Mask, MVT VT, bool Commuted = false) {
3726 unsigned NumElems = VT.getVectorNumElements();
3727 unsigned NumLanes = VT.getSizeInBits()/128;
3728 unsigned NumLaneElems = NumElems/NumLanes;
3730 if (NumLaneElems != 2 && NumLaneElems != 4)
3733 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
3734 bool symetricMaskRequired =
3735 (VT.getSizeInBits() >= 256) && (EltSize == 32);
3737 // VSHUFPSY divides the resulting vector into 4 chunks.
3738 // The sources are also splitted into 4 chunks, and each destination
3739 // chunk must come from a different source chunk.
3741 // SRC1 => X7 X6 X5 X4 X3 X2 X1 X0
3742 // SRC2 => Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y9
3744 // DST => Y7..Y4, Y7..Y4, X7..X4, X7..X4,
3745 // Y3..Y0, Y3..Y0, X3..X0, X3..X0
3747 // VSHUFPDY divides the resulting vector into 4 chunks.
3748 // The sources are also splitted into 4 chunks, and each destination
3749 // chunk must come from a different source chunk.
3751 // SRC1 => X3 X2 X1 X0
3752 // SRC2 => Y3 Y2 Y1 Y0
3754 // DST => Y3..Y2, X3..X2, Y1..Y0, X1..X0
3756 SmallVector<int, 4> MaskVal(NumLaneElems, -1);
3757 unsigned HalfLaneElems = NumLaneElems/2;
3758 for (unsigned l = 0; l != NumElems; l += NumLaneElems) {
3759 for (unsigned i = 0; i != NumLaneElems; ++i) {
3760 int Idx = Mask[i+l];
3761 unsigned RngStart = l + ((Commuted == (i<HalfLaneElems)) ? NumElems : 0);
3762 if (!isUndefOrInRange(Idx, RngStart, RngStart+NumLaneElems))
3764 // For VSHUFPSY, the mask of the second half must be the same as the
3765 // first but with the appropriate offsets. This works in the same way as
3766 // VPERMILPS works with masks.
3767 if (!symetricMaskRequired || Idx < 0)
3769 if (MaskVal[i] < 0) {
3770 MaskVal[i] = Idx - l;
3773 if ((signed)(Idx - l) != MaskVal[i])
3781 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
3782 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
3783 static bool isMOVHLPSMask(ArrayRef<int> Mask, MVT VT) {
3784 if (!VT.is128BitVector())
3787 unsigned NumElems = VT.getVectorNumElements();
3792 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3
3793 return isUndefOrEqual(Mask[0], 6) &&
3794 isUndefOrEqual(Mask[1], 7) &&
3795 isUndefOrEqual(Mask[2], 2) &&
3796 isUndefOrEqual(Mask[3], 3);
3799 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
3800 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
3802 static bool isMOVHLPS_v_undef_Mask(ArrayRef<int> Mask, MVT VT) {
3803 if (!VT.is128BitVector())
3806 unsigned NumElems = VT.getVectorNumElements();
3811 return isUndefOrEqual(Mask[0], 2) &&
3812 isUndefOrEqual(Mask[1], 3) &&
3813 isUndefOrEqual(Mask[2], 2) &&
3814 isUndefOrEqual(Mask[3], 3);
3817 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
3818 /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
3819 static bool isMOVLPMask(ArrayRef<int> Mask, MVT VT) {
3820 if (!VT.is128BitVector())
3823 unsigned NumElems = VT.getVectorNumElements();
3825 if (NumElems != 2 && NumElems != 4)
3828 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
3829 if (!isUndefOrEqual(Mask[i], i + NumElems))
3832 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i)
3833 if (!isUndefOrEqual(Mask[i], i))
3839 /// isMOVLHPSMask - Return true if the specified VECTOR_SHUFFLE operand
3840 /// specifies a shuffle of elements that is suitable for input to MOVLHPS.
3841 static bool isMOVLHPSMask(ArrayRef<int> Mask, MVT VT) {
3842 if (!VT.is128BitVector())
3845 unsigned NumElems = VT.getVectorNumElements();
3847 if (NumElems != 2 && NumElems != 4)
3850 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
3851 if (!isUndefOrEqual(Mask[i], i))
3854 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
3855 if (!isUndefOrEqual(Mask[i + e], i + NumElems))
3862 // Some special combinations that can be optimized.
3865 SDValue Compact8x32ShuffleNode(ShuffleVectorSDNode *SVOp,
3866 SelectionDAG &DAG) {
3867 MVT VT = SVOp->getSimpleValueType(0);
3870 if (VT != MVT::v8i32 && VT != MVT::v8f32)
3873 ArrayRef<int> Mask = SVOp->getMask();
3875 // These are the special masks that may be optimized.
3876 static const int MaskToOptimizeEven[] = {0, 8, 2, 10, 4, 12, 6, 14};
3877 static const int MaskToOptimizeOdd[] = {1, 9, 3, 11, 5, 13, 7, 15};
3878 bool MatchEvenMask = true;
3879 bool MatchOddMask = true;
3880 for (int i=0; i<8; ++i) {
3881 if (!isUndefOrEqual(Mask[i], MaskToOptimizeEven[i]))
3882 MatchEvenMask = false;
3883 if (!isUndefOrEqual(Mask[i], MaskToOptimizeOdd[i]))
3884 MatchOddMask = false;
3887 if (!MatchEvenMask && !MatchOddMask)
3890 SDValue UndefNode = DAG.getNode(ISD::UNDEF, dl, VT);
3892 SDValue Op0 = SVOp->getOperand(0);
3893 SDValue Op1 = SVOp->getOperand(1);
3895 if (MatchEvenMask) {
3896 // Shift the second operand right to 32 bits.
3897 static const int ShiftRightMask[] = {-1, 0, -1, 2, -1, 4, -1, 6 };
3898 Op1 = DAG.getVectorShuffle(VT, dl, Op1, UndefNode, ShiftRightMask);
3900 // Shift the first operand left to 32 bits.
3901 static const int ShiftLeftMask[] = {1, -1, 3, -1, 5, -1, 7, -1 };
3902 Op0 = DAG.getVectorShuffle(VT, dl, Op0, UndefNode, ShiftLeftMask);
3904 static const int BlendMask[] = {0, 9, 2, 11, 4, 13, 6, 15};
3905 return DAG.getVectorShuffle(VT, dl, Op0, Op1, BlendMask);
3908 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
3909 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
3910 static bool isUNPCKLMask(ArrayRef<int> Mask, MVT VT,
3911 bool HasInt256, bool V2IsSplat = false) {
3913 assert(VT.getSizeInBits() >= 128 &&
3914 "Unsupported vector type for unpckl");
3916 // AVX defines UNPCK* to operate independently on 128-bit lanes.
3918 unsigned NumOf256BitLanes;
3919 unsigned NumElts = VT.getVectorNumElements();
3920 if (VT.is256BitVector()) {
3921 if (NumElts != 4 && NumElts != 8 &&
3922 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
3925 NumOf256BitLanes = 1;
3926 } else if (VT.is512BitVector()) {
3927 assert(VT.getScalarType().getSizeInBits() >= 32 &&
3928 "Unsupported vector type for unpckh");
3930 NumOf256BitLanes = 2;
3933 NumOf256BitLanes = 1;
3936 unsigned NumEltsInStride = NumElts/NumOf256BitLanes;
3937 unsigned NumLaneElts = NumEltsInStride/NumLanes;
3939 for (unsigned l256 = 0; l256 < NumOf256BitLanes; l256 += 1) {
3940 for (unsigned l = 0; l != NumEltsInStride; l += NumLaneElts) {
3941 for (unsigned i = 0, j = l; i != NumLaneElts; i += 2, ++j) {
3942 int BitI = Mask[l256*NumEltsInStride+l+i];
3943 int BitI1 = Mask[l256*NumEltsInStride+l+i+1];
3944 if (!isUndefOrEqual(BitI, j+l256*NumElts))
3946 if (V2IsSplat && !isUndefOrEqual(BitI1, NumElts))
3948 if (!isUndefOrEqual(BitI1, j+l256*NumElts+NumEltsInStride))
3956 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
3957 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
3958 static bool isUNPCKHMask(ArrayRef<int> Mask, MVT VT,
3959 bool HasInt256, bool V2IsSplat = false) {
3960 assert(VT.getSizeInBits() >= 128 &&
3961 "Unsupported vector type for unpckh");
3963 // AVX defines UNPCK* to operate independently on 128-bit lanes.
3965 unsigned NumOf256BitLanes;
3966 unsigned NumElts = VT.getVectorNumElements();
3967 if (VT.is256BitVector()) {
3968 if (NumElts != 4 && NumElts != 8 &&
3969 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
3972 NumOf256BitLanes = 1;
3973 } else if (VT.is512BitVector()) {
3974 assert(VT.getScalarType().getSizeInBits() >= 32 &&
3975 "Unsupported vector type for unpckh");
3977 NumOf256BitLanes = 2;
3980 NumOf256BitLanes = 1;
3983 unsigned NumEltsInStride = NumElts/NumOf256BitLanes;
3984 unsigned NumLaneElts = NumEltsInStride/NumLanes;
3986 for (unsigned l256 = 0; l256 < NumOf256BitLanes; l256 += 1) {
3987 for (unsigned l = 0; l != NumEltsInStride; l += NumLaneElts) {
3988 for (unsigned i = 0, j = l+NumLaneElts/2; i != NumLaneElts; i += 2, ++j) {
3989 int BitI = Mask[l256*NumEltsInStride+l+i];
3990 int BitI1 = Mask[l256*NumEltsInStride+l+i+1];
3991 if (!isUndefOrEqual(BitI, j+l256*NumElts))
3993 if (V2IsSplat && !isUndefOrEqual(BitI1, NumElts))
3995 if (!isUndefOrEqual(BitI1, j+l256*NumElts+NumEltsInStride))
4003 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
4004 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
4006 static bool isUNPCKL_v_undef_Mask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
4007 unsigned NumElts = VT.getVectorNumElements();
4008 bool Is256BitVec = VT.is256BitVector();
4010 if (VT.is512BitVector())
4012 assert((VT.is128BitVector() || VT.is256BitVector()) &&
4013 "Unsupported vector type for unpckh");
4015 if (Is256BitVec && NumElts != 4 && NumElts != 8 &&
4016 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4019 // For 256-bit i64/f64, use MOVDDUPY instead, so reject the matching pattern
4020 // FIXME: Need a better way to get rid of this, there's no latency difference
4021 // between UNPCKLPD and MOVDDUP, the later should always be checked first and
4022 // the former later. We should also remove the "_undef" special mask.
4023 if (NumElts == 4 && Is256BitVec)
4026 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
4027 // independently on 128-bit lanes.
4028 unsigned NumLanes = VT.getSizeInBits()/128;
4029 unsigned NumLaneElts = NumElts/NumLanes;
4031 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4032 for (unsigned i = 0, j = l; i != NumLaneElts; i += 2, ++j) {
4033 int BitI = Mask[l+i];
4034 int BitI1 = Mask[l+i+1];
4036 if (!isUndefOrEqual(BitI, j))
4038 if (!isUndefOrEqual(BitI1, j))
4046 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
4047 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
4049 static bool isUNPCKH_v_undef_Mask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
4050 unsigned NumElts = VT.getVectorNumElements();
4052 if (VT.is512BitVector())
4055 assert((VT.is128BitVector() || VT.is256BitVector()) &&
4056 "Unsupported vector type for unpckh");
4058 if (VT.is256BitVector() && NumElts != 4 && NumElts != 8 &&
4059 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4062 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
4063 // independently on 128-bit lanes.
4064 unsigned NumLanes = VT.getSizeInBits()/128;
4065 unsigned NumLaneElts = NumElts/NumLanes;
4067 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4068 for (unsigned i = 0, j = l+NumLaneElts/2; i != NumLaneElts; i += 2, ++j) {
4069 int BitI = Mask[l+i];
4070 int BitI1 = Mask[l+i+1];
4071 if (!isUndefOrEqual(BitI, j))
4073 if (!isUndefOrEqual(BitI1, j))
4080 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
4081 /// specifies a shuffle of elements that is suitable for input to MOVSS,
4082 /// MOVSD, and MOVD, i.e. setting the lowest element.
4083 static bool isMOVLMask(ArrayRef<int> Mask, EVT VT) {
4084 if (VT.getVectorElementType().getSizeInBits() < 32)
4086 if (!VT.is128BitVector())
4089 unsigned NumElts = VT.getVectorNumElements();
4091 if (!isUndefOrEqual(Mask[0], NumElts))
4094 for (unsigned i = 1; i != NumElts; ++i)
4095 if (!isUndefOrEqual(Mask[i], i))
4101 /// isVPERM2X128Mask - Match 256-bit shuffles where the elements are considered
4102 /// as permutations between 128-bit chunks or halves. As an example: this
4104 /// vector_shuffle <4, 5, 6, 7, 12, 13, 14, 15>
4105 /// The first half comes from the second half of V1 and the second half from the
4106 /// the second half of V2.
4107 static bool isVPERM2X128Mask(ArrayRef<int> Mask, MVT VT, bool HasFp256) {
4108 if (!HasFp256 || !VT.is256BitVector())
4111 // The shuffle result is divided into half A and half B. In total the two
4112 // sources have 4 halves, namely: C, D, E, F. The final values of A and
4113 // B must come from C, D, E or F.
4114 unsigned HalfSize = VT.getVectorNumElements()/2;
4115 bool MatchA = false, MatchB = false;
4117 // Check if A comes from one of C, D, E, F.
4118 for (unsigned Half = 0; Half != 4; ++Half) {
4119 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, Half*HalfSize)) {
4125 // Check if B comes from one of C, D, E, F.
4126 for (unsigned Half = 0; Half != 4; ++Half) {
4127 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, Half*HalfSize)) {
4133 return MatchA && MatchB;
4136 /// getShuffleVPERM2X128Immediate - Return the appropriate immediate to shuffle
4137 /// the specified VECTOR_MASK mask with VPERM2F128/VPERM2I128 instructions.
4138 static unsigned getShuffleVPERM2X128Immediate(ShuffleVectorSDNode *SVOp) {
4139 MVT VT = SVOp->getSimpleValueType(0);
4141 unsigned HalfSize = VT.getVectorNumElements()/2;
4143 unsigned FstHalf = 0, SndHalf = 0;
4144 for (unsigned i = 0; i < HalfSize; ++i) {
4145 if (SVOp->getMaskElt(i) > 0) {
4146 FstHalf = SVOp->getMaskElt(i)/HalfSize;
4150 for (unsigned i = HalfSize; i < HalfSize*2; ++i) {
4151 if (SVOp->getMaskElt(i) > 0) {
4152 SndHalf = SVOp->getMaskElt(i)/HalfSize;
4157 return (FstHalf | (SndHalf << 4));
4160 // Symetric in-lane mask. Each lane has 4 elements (for imm8)
4161 static bool isPermImmMask(ArrayRef<int> Mask, MVT VT, unsigned& Imm8) {
4162 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4166 unsigned NumElts = VT.getVectorNumElements();
4168 if (VT.is128BitVector() || (VT.is256BitVector() && EltSize == 64)) {
4169 for (unsigned i = 0; i != NumElts; ++i) {
4172 Imm8 |= Mask[i] << (i*2);
4177 unsigned LaneSize = 4;
4178 SmallVector<int, 4> MaskVal(LaneSize, -1);
4180 for (unsigned l = 0; l != NumElts; l += LaneSize) {
4181 for (unsigned i = 0; i != LaneSize; ++i) {
4182 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize))
4186 if (MaskVal[i] < 0) {
4187 MaskVal[i] = Mask[i+l] - l;
4188 Imm8 |= MaskVal[i] << (i*2);
4191 if (Mask[i+l] != (signed)(MaskVal[i]+l))
4198 /// isVPERMILPMask - Return true if the specified VECTOR_SHUFFLE operand
4199 /// specifies a shuffle of elements that is suitable for input to VPERMILPD*.
4200 /// Note that VPERMIL mask matching is different depending whether theunderlying
4201 /// type is 32 or 64. In the VPERMILPS the high half of the mask should point
4202 /// to the same elements of the low, but to the higher half of the source.
4203 /// In VPERMILPD the two lanes could be shuffled independently of each other
4204 /// with the same restriction that lanes can't be crossed. Also handles PSHUFDY.
4205 static bool isVPERMILPMask(ArrayRef<int> Mask, MVT VT) {
4206 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4207 if (VT.getSizeInBits() < 256 || EltSize < 32)
4209 bool symetricMaskRequired = (EltSize == 32);
4210 unsigned NumElts = VT.getVectorNumElements();
4212 unsigned NumLanes = VT.getSizeInBits()/128;
4213 unsigned LaneSize = NumElts/NumLanes;
4214 // 2 or 4 elements in one lane
4216 SmallVector<int, 4> ExpectedMaskVal(LaneSize, -1);
4217 for (unsigned l = 0; l != NumElts; l += LaneSize) {
4218 for (unsigned i = 0; i != LaneSize; ++i) {
4219 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize))
4221 if (symetricMaskRequired) {
4222 if (ExpectedMaskVal[i] < 0 && Mask[i+l] >= 0) {
4223 ExpectedMaskVal[i] = Mask[i+l] - l;
4226 if (!isUndefOrEqual(Mask[i+l], ExpectedMaskVal[i]+l))
4234 /// isCommutedMOVLMask - Returns true if the shuffle mask is except the reverse
4235 /// of what x86 movss want. X86 movs requires the lowest element to be lowest
4236 /// element of vector 2 and the other elements to come from vector 1 in order.
4237 static bool isCommutedMOVLMask(ArrayRef<int> Mask, MVT VT,
4238 bool V2IsSplat = false, bool V2IsUndef = false) {
4239 if (!VT.is128BitVector())
4242 unsigned NumOps = VT.getVectorNumElements();
4243 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16)
4246 if (!isUndefOrEqual(Mask[0], 0))
4249 for (unsigned i = 1; i != NumOps; ++i)
4250 if (!(isUndefOrEqual(Mask[i], i+NumOps) ||
4251 (V2IsUndef && isUndefOrInRange(Mask[i], NumOps, NumOps*2)) ||
4252 (V2IsSplat && isUndefOrEqual(Mask[i], NumOps))))
4258 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4259 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
4260 /// Masks to match: <1, 1, 3, 3> or <1, 1, 3, 3, 5, 5, 7, 7>
4261 static bool isMOVSHDUPMask(ArrayRef<int> Mask, MVT VT,
4262 const X86Subtarget *Subtarget) {
4263 if (!Subtarget->hasSSE3())
4266 unsigned NumElems = VT.getVectorNumElements();
4268 if ((VT.is128BitVector() && NumElems != 4) ||
4269 (VT.is256BitVector() && NumElems != 8) ||
4270 (VT.is512BitVector() && NumElems != 16))
4273 // "i+1" is the value the indexed mask element must have
4274 for (unsigned i = 0; i != NumElems; i += 2)
4275 if (!isUndefOrEqual(Mask[i], i+1) ||
4276 !isUndefOrEqual(Mask[i+1], i+1))
4282 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4283 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
4284 /// Masks to match: <0, 0, 2, 2> or <0, 0, 2, 2, 4, 4, 6, 6>
4285 static bool isMOVSLDUPMask(ArrayRef<int> Mask, MVT VT,
4286 const X86Subtarget *Subtarget) {
4287 if (!Subtarget->hasSSE3())
4290 unsigned NumElems = VT.getVectorNumElements();
4292 if ((VT.is128BitVector() && NumElems != 4) ||
4293 (VT.is256BitVector() && NumElems != 8) ||
4294 (VT.is512BitVector() && NumElems != 16))
4297 // "i" is the value the indexed mask element must have
4298 for (unsigned i = 0; i != NumElems; i += 2)
4299 if (!isUndefOrEqual(Mask[i], i) ||
4300 !isUndefOrEqual(Mask[i+1], i))
4306 /// isMOVDDUPYMask - Return true if the specified VECTOR_SHUFFLE operand
4307 /// specifies a shuffle of elements that is suitable for input to 256-bit
4308 /// version of MOVDDUP.
4309 static bool isMOVDDUPYMask(ArrayRef<int> Mask, MVT VT, bool HasFp256) {
4310 if (!HasFp256 || !VT.is256BitVector())
4313 unsigned NumElts = VT.getVectorNumElements();
4317 for (unsigned i = 0; i != NumElts/2; ++i)
4318 if (!isUndefOrEqual(Mask[i], 0))
4320 for (unsigned i = NumElts/2; i != NumElts; ++i)
4321 if (!isUndefOrEqual(Mask[i], NumElts/2))
4326 /// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4327 /// specifies a shuffle of elements that is suitable for input to 128-bit
4328 /// version of MOVDDUP.
4329 static bool isMOVDDUPMask(ArrayRef<int> Mask, MVT VT) {
4330 if (!VT.is128BitVector())
4333 unsigned e = VT.getVectorNumElements() / 2;
4334 for (unsigned i = 0; i != e; ++i)
4335 if (!isUndefOrEqual(Mask[i], i))
4337 for (unsigned i = 0; i != e; ++i)
4338 if (!isUndefOrEqual(Mask[e+i], i))
4343 /// isVEXTRACTIndex - Return true if the specified
4344 /// EXTRACT_SUBVECTOR operand specifies a vector extract that is
4345 /// suitable for instruction that extract 128 or 256 bit vectors
4346 static bool isVEXTRACTIndex(SDNode *N, unsigned vecWidth) {
4347 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4348 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4351 // The index should be aligned on a vecWidth-bit boundary.
4353 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4355 MVT VT = N->getSimpleValueType(0);
4356 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4357 bool Result = (Index * ElSize) % vecWidth == 0;
4362 /// isVINSERTIndex - Return true if the specified INSERT_SUBVECTOR
4363 /// operand specifies a subvector insert that is suitable for input to
4364 /// insertion of 128 or 256-bit subvectors
4365 static bool isVINSERTIndex(SDNode *N, unsigned vecWidth) {
4366 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4367 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4369 // The index should be aligned on a vecWidth-bit boundary.
4371 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4373 MVT VT = N->getSimpleValueType(0);
4374 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4375 bool Result = (Index * ElSize) % vecWidth == 0;
4380 bool X86::isVINSERT128Index(SDNode *N) {
4381 return isVINSERTIndex(N, 128);
4384 bool X86::isVINSERT256Index(SDNode *N) {
4385 return isVINSERTIndex(N, 256);
4388 bool X86::isVEXTRACT128Index(SDNode *N) {
4389 return isVEXTRACTIndex(N, 128);
4392 bool X86::isVEXTRACT256Index(SDNode *N) {
4393 return isVEXTRACTIndex(N, 256);
4396 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
4397 /// the specified VECTOR_SHUFFLE mask with PSHUF* and SHUFP* instructions.
4398 /// Handles 128-bit and 256-bit.
4399 static unsigned getShuffleSHUFImmediate(ShuffleVectorSDNode *N) {
4400 MVT VT = N->getSimpleValueType(0);
4402 assert((VT.getSizeInBits() >= 128) &&
4403 "Unsupported vector type for PSHUF/SHUFP");
4405 // Handle 128 and 256-bit vector lengths. AVX defines PSHUF/SHUFP to operate
4406 // independently on 128-bit lanes.
4407 unsigned NumElts = VT.getVectorNumElements();
4408 unsigned NumLanes = VT.getSizeInBits()/128;
4409 unsigned NumLaneElts = NumElts/NumLanes;
4411 assert((NumLaneElts == 2 || NumLaneElts == 4 || NumLaneElts == 8) &&
4412 "Only supports 2, 4 or 8 elements per lane");
4414 unsigned Shift = (NumLaneElts >= 4) ? 1 : 0;
4416 for (unsigned i = 0; i != NumElts; ++i) {
4417 int Elt = N->getMaskElt(i);
4418 if (Elt < 0) continue;
4419 Elt &= NumLaneElts - 1;
4420 unsigned ShAmt = (i << Shift) % 8;
4421 Mask |= Elt << ShAmt;
4427 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
4428 /// the specified VECTOR_SHUFFLE mask with the PSHUFHW instruction.
4429 static unsigned getShufflePSHUFHWImmediate(ShuffleVectorSDNode *N) {
4430 MVT VT = N->getSimpleValueType(0);
4432 assert((VT == MVT::v8i16 || VT == MVT::v16i16) &&
4433 "Unsupported vector type for PSHUFHW");
4435 unsigned NumElts = VT.getVectorNumElements();
4438 for (unsigned l = 0; l != NumElts; l += 8) {
4439 // 8 nodes per lane, but we only care about the last 4.
4440 for (unsigned i = 0; i < 4; ++i) {
4441 int Elt = N->getMaskElt(l+i+4);
4442 if (Elt < 0) continue;
4443 Elt &= 0x3; // only 2-bits.
4444 Mask |= Elt << (i * 2);
4451 /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
4452 /// the specified VECTOR_SHUFFLE mask with the PSHUFLW instruction.
4453 static unsigned getShufflePSHUFLWImmediate(ShuffleVectorSDNode *N) {
4454 MVT VT = N->getSimpleValueType(0);
4456 assert((VT == MVT::v8i16 || VT == MVT::v16i16) &&
4457 "Unsupported vector type for PSHUFHW");
4459 unsigned NumElts = VT.getVectorNumElements();
4462 for (unsigned l = 0; l != NumElts; l += 8) {
4463 // 8 nodes per lane, but we only care about the first 4.
4464 for (unsigned i = 0; i < 4; ++i) {
4465 int Elt = N->getMaskElt(l+i);
4466 if (Elt < 0) continue;
4467 Elt &= 0x3; // only 2-bits
4468 Mask |= Elt << (i * 2);
4475 /// getShufflePALIGNRImmediate - Return the appropriate immediate to shuffle
4476 /// the specified VECTOR_SHUFFLE mask with the PALIGNR instruction.
4477 static unsigned getShufflePALIGNRImmediate(ShuffleVectorSDNode *SVOp) {
4478 MVT VT = SVOp->getSimpleValueType(0);
4479 unsigned EltSize = VT.is512BitVector() ? 1 :
4480 VT.getVectorElementType().getSizeInBits() >> 3;
4482 unsigned NumElts = VT.getVectorNumElements();
4483 unsigned NumLanes = VT.is512BitVector() ? 1 : VT.getSizeInBits()/128;
4484 unsigned NumLaneElts = NumElts/NumLanes;
4488 for (i = 0; i != NumElts; ++i) {
4489 Val = SVOp->getMaskElt(i);
4493 if (Val >= (int)NumElts)
4494 Val -= NumElts - NumLaneElts;
4496 assert(Val - i > 0 && "PALIGNR imm should be positive");
4497 return (Val - i) * EltSize;
4500 static unsigned getExtractVEXTRACTImmediate(SDNode *N, unsigned vecWidth) {
4501 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4502 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4503 llvm_unreachable("Illegal extract subvector for VEXTRACT");
4506 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4508 MVT VecVT = N->getOperand(0).getSimpleValueType();
4509 MVT ElVT = VecVT.getVectorElementType();
4511 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4512 return Index / NumElemsPerChunk;
4515 static unsigned getInsertVINSERTImmediate(SDNode *N, unsigned vecWidth) {
4516 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4517 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4518 llvm_unreachable("Illegal insert subvector for VINSERT");
4521 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4523 MVT VecVT = N->getSimpleValueType(0);
4524 MVT ElVT = VecVT.getVectorElementType();
4526 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4527 return Index / NumElemsPerChunk;
4530 /// getExtractVEXTRACT128Immediate - Return the appropriate immediate
4531 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF128
4532 /// and VINSERTI128 instructions.
4533 unsigned X86::getExtractVEXTRACT128Immediate(SDNode *N) {
4534 return getExtractVEXTRACTImmediate(N, 128);
4537 /// getExtractVEXTRACT256Immediate - Return the appropriate immediate
4538 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF64x4
4539 /// and VINSERTI64x4 instructions.
4540 unsigned X86::getExtractVEXTRACT256Immediate(SDNode *N) {
4541 return getExtractVEXTRACTImmediate(N, 256);
4544 /// getInsertVINSERT128Immediate - Return the appropriate immediate
4545 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF128
4546 /// and VINSERTI128 instructions.
4547 unsigned X86::getInsertVINSERT128Immediate(SDNode *N) {
4548 return getInsertVINSERTImmediate(N, 128);
4551 /// getInsertVINSERT256Immediate - Return the appropriate immediate
4552 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF46x4
4553 /// and VINSERTI64x4 instructions.
4554 unsigned X86::getInsertVINSERT256Immediate(SDNode *N) {
4555 return getInsertVINSERTImmediate(N, 256);
4558 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
4560 bool X86::isZeroNode(SDValue Elt) {
4561 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Elt))
4562 return CN->isNullValue();
4563 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Elt))
4564 return CFP->getValueAPF().isPosZero();
4568 /// CommuteVectorShuffle - Swap vector_shuffle operands as well as values in
4569 /// their permute mask.
4570 static SDValue CommuteVectorShuffle(ShuffleVectorSDNode *SVOp,
4571 SelectionDAG &DAG) {
4572 MVT VT = SVOp->getSimpleValueType(0);
4573 unsigned NumElems = VT.getVectorNumElements();
4574 SmallVector<int, 8> MaskVec;
4576 for (unsigned i = 0; i != NumElems; ++i) {
4577 int Idx = SVOp->getMaskElt(i);
4579 if (Idx < (int)NumElems)
4584 MaskVec.push_back(Idx);
4586 return DAG.getVectorShuffle(VT, SDLoc(SVOp), SVOp->getOperand(1),
4587 SVOp->getOperand(0), &MaskVec[0]);
4590 /// ShouldXformToMOVHLPS - Return true if the node should be transformed to
4591 /// match movhlps. The lower half elements should come from upper half of
4592 /// V1 (and in order), and the upper half elements should come from the upper
4593 /// half of V2 (and in order).
4594 static bool ShouldXformToMOVHLPS(ArrayRef<int> Mask, MVT VT) {
4595 if (!VT.is128BitVector())
4597 if (VT.getVectorNumElements() != 4)
4599 for (unsigned i = 0, e = 2; i != e; ++i)
4600 if (!isUndefOrEqual(Mask[i], i+2))
4602 for (unsigned i = 2; i != 4; ++i)
4603 if (!isUndefOrEqual(Mask[i], i+4))
4608 /// isScalarLoadToVector - Returns true if the node is a scalar load that
4609 /// is promoted to a vector. It also returns the LoadSDNode by reference if
4611 static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = NULL) {
4612 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR)
4614 N = N->getOperand(0).getNode();
4615 if (!ISD::isNON_EXTLoad(N))
4618 *LD = cast<LoadSDNode>(N);
4622 // Test whether the given value is a vector value which will be legalized
4624 static bool WillBeConstantPoolLoad(SDNode *N) {
4625 if (N->getOpcode() != ISD::BUILD_VECTOR)
4628 // Check for any non-constant elements.
4629 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
4630 switch (N->getOperand(i).getNode()->getOpcode()) {
4632 case ISD::ConstantFP:
4639 // Vectors of all-zeros and all-ones are materialized with special
4640 // instructions rather than being loaded.
4641 return !ISD::isBuildVectorAllZeros(N) &&
4642 !ISD::isBuildVectorAllOnes(N);
4645 /// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to
4646 /// match movlp{s|d}. The lower half elements should come from lower half of
4647 /// V1 (and in order), and the upper half elements should come from the upper
4648 /// half of V2 (and in order). And since V1 will become the source of the
4649 /// MOVLP, it must be either a vector load or a scalar load to vector.
4650 static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2,
4651 ArrayRef<int> Mask, MVT VT) {
4652 if (!VT.is128BitVector())
4655 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1))
4657 // Is V2 is a vector load, don't do this transformation. We will try to use
4658 // load folding shufps op.
4659 if (ISD::isNON_EXTLoad(V2) || WillBeConstantPoolLoad(V2))
4662 unsigned NumElems = VT.getVectorNumElements();
4664 if (NumElems != 2 && NumElems != 4)
4666 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4667 if (!isUndefOrEqual(Mask[i], i))
4669 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i)
4670 if (!isUndefOrEqual(Mask[i], i+NumElems))
4675 /// isSplatVector - Returns true if N is a BUILD_VECTOR node whose elements are
4677 static bool isSplatVector(SDNode *N) {
4678 if (N->getOpcode() != ISD::BUILD_VECTOR)
4681 SDValue SplatValue = N->getOperand(0);
4682 for (unsigned i = 1, e = N->getNumOperands(); i != e; ++i)
4683 if (N->getOperand(i) != SplatValue)
4688 /// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
4689 /// to an zero vector.
4690 /// FIXME: move to dag combiner / method on ShuffleVectorSDNode
4691 static bool isZeroShuffle(ShuffleVectorSDNode *N) {
4692 SDValue V1 = N->getOperand(0);
4693 SDValue V2 = N->getOperand(1);
4694 unsigned NumElems = N->getValueType(0).getVectorNumElements();
4695 for (unsigned i = 0; i != NumElems; ++i) {
4696 int Idx = N->getMaskElt(i);
4697 if (Idx >= (int)NumElems) {
4698 unsigned Opc = V2.getOpcode();
4699 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode()))
4701 if (Opc != ISD::BUILD_VECTOR ||
4702 !X86::isZeroNode(V2.getOperand(Idx-NumElems)))
4704 } else if (Idx >= 0) {
4705 unsigned Opc = V1.getOpcode();
4706 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode()))
4708 if (Opc != ISD::BUILD_VECTOR ||
4709 !X86::isZeroNode(V1.getOperand(Idx)))
4716 /// getZeroVector - Returns a vector of specified type with all zero elements.
4718 static SDValue getZeroVector(EVT VT, const X86Subtarget *Subtarget,
4719 SelectionDAG &DAG, SDLoc dl) {
4720 assert(VT.isVector() && "Expected a vector type");
4722 // Always build SSE zero vectors as <4 x i32> bitcasted
4723 // to their dest type. This ensures they get CSE'd.
4725 if (VT.is128BitVector()) { // SSE
4726 if (Subtarget->hasSSE2()) { // SSE2
4727 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
4728 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4730 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
4731 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
4733 } else if (VT.is256BitVector()) { // AVX
4734 if (Subtarget->hasInt256()) { // AVX2
4735 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
4736 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4737 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops,
4738 array_lengthof(Ops));
4740 // 256-bit logic and arithmetic instructions in AVX are all
4741 // floating-point, no support for integer ops. Emit fp zeroed vectors.
4742 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
4743 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4744 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops,
4745 array_lengthof(Ops));
4747 } else if (VT.is512BitVector()) { // AVX-512
4748 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
4749 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst,
4750 Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4751 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i32, Ops, 16);
4753 llvm_unreachable("Unexpected vector type");
4755 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
4758 /// getOnesVector - Returns a vector of specified type with all bits set.
4759 /// Always build ones vectors as <4 x i32> or <8 x i32>. For 256-bit types with
4760 /// no AVX2 supprt, use two <4 x i32> inserted in a <8 x i32> appropriately.
4761 /// Then bitcast to their original type, ensuring they get CSE'd.
4762 static SDValue getOnesVector(MVT VT, bool HasInt256, SelectionDAG &DAG,
4764 assert(VT.isVector() && "Expected a vector type");
4766 SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32);
4768 if (VT.is256BitVector()) {
4769 if (HasInt256) { // AVX2
4770 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4771 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops,
4772 array_lengthof(Ops));
4774 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4775 Vec = Concat128BitVectors(Vec, Vec, MVT::v8i32, 8, DAG, dl);
4777 } else if (VT.is128BitVector()) {
4778 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4780 llvm_unreachable("Unexpected vector type");
4782 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
4785 /// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements
4786 /// that point to V2 points to its first element.
4787 static void NormalizeMask(SmallVectorImpl<int> &Mask, unsigned NumElems) {
4788 for (unsigned i = 0; i != NumElems; ++i) {
4789 if (Mask[i] > (int)NumElems) {
4795 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
4796 /// operation of specified width.
4797 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
4799 unsigned NumElems = VT.getVectorNumElements();
4800 SmallVector<int, 8> Mask;
4801 Mask.push_back(NumElems);
4802 for (unsigned i = 1; i != NumElems; ++i)
4804 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4807 /// getUnpackl - Returns a vector_shuffle node for an unpackl operation.
4808 static SDValue getUnpackl(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
4810 unsigned NumElems = VT.getVectorNumElements();
4811 SmallVector<int, 8> Mask;
4812 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
4814 Mask.push_back(i + NumElems);
4816 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4819 /// getUnpackh - Returns a vector_shuffle node for an unpackh operation.
4820 static SDValue getUnpackh(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
4822 unsigned NumElems = VT.getVectorNumElements();
4823 SmallVector<int, 8> Mask;
4824 for (unsigned i = 0, Half = NumElems/2; i != Half; ++i) {
4825 Mask.push_back(i + Half);
4826 Mask.push_back(i + NumElems + Half);
4828 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4831 // PromoteSplati8i16 - All i16 and i8 vector types can't be used directly by
4832 // a generic shuffle instruction because the target has no such instructions.
4833 // Generate shuffles which repeat i16 and i8 several times until they can be
4834 // represented by v4f32 and then be manipulated by target suported shuffles.
4835 static SDValue PromoteSplati8i16(SDValue V, SelectionDAG &DAG, int &EltNo) {
4836 MVT VT = V.getSimpleValueType();
4837 int NumElems = VT.getVectorNumElements();
4840 while (NumElems > 4) {
4841 if (EltNo < NumElems/2) {
4842 V = getUnpackl(DAG, dl, VT, V, V);
4844 V = getUnpackh(DAG, dl, VT, V, V);
4845 EltNo -= NumElems/2;
4852 /// getLegalSplat - Generate a legal splat with supported x86 shuffles
4853 static SDValue getLegalSplat(SelectionDAG &DAG, SDValue V, int EltNo) {
4854 MVT VT = V.getSimpleValueType();
4857 if (VT.is128BitVector()) {
4858 V = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V);
4859 int SplatMask[4] = { EltNo, EltNo, EltNo, EltNo };
4860 V = DAG.getVectorShuffle(MVT::v4f32, dl, V, DAG.getUNDEF(MVT::v4f32),
4862 } else if (VT.is256BitVector()) {
4863 // To use VPERMILPS to splat scalars, the second half of indicies must
4864 // refer to the higher part, which is a duplication of the lower one,
4865 // because VPERMILPS can only handle in-lane permutations.
4866 int SplatMask[8] = { EltNo, EltNo, EltNo, EltNo,
4867 EltNo+4, EltNo+4, EltNo+4, EltNo+4 };
4869 V = DAG.getNode(ISD::BITCAST, dl, MVT::v8f32, V);
4870 V = DAG.getVectorShuffle(MVT::v8f32, dl, V, DAG.getUNDEF(MVT::v8f32),
4873 llvm_unreachable("Vector size not supported");
4875 return DAG.getNode(ISD::BITCAST, dl, VT, V);
4878 /// PromoteSplat - Splat is promoted to target supported vector shuffles.
4879 static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG) {
4880 MVT SrcVT = SV->getSimpleValueType(0);
4881 SDValue V1 = SV->getOperand(0);
4884 int EltNo = SV->getSplatIndex();
4885 int NumElems = SrcVT.getVectorNumElements();
4886 bool Is256BitVec = SrcVT.is256BitVector();
4888 assert(((SrcVT.is128BitVector() && NumElems > 4) || Is256BitVec) &&
4889 "Unknown how to promote splat for type");
4891 // Extract the 128-bit part containing the splat element and update
4892 // the splat element index when it refers to the higher register.
4894 V1 = Extract128BitVector(V1, EltNo, DAG, dl);
4895 if (EltNo >= NumElems/2)
4896 EltNo -= NumElems/2;
4899 // All i16 and i8 vector types can't be used directly by a generic shuffle
4900 // instruction because the target has no such instruction. Generate shuffles
4901 // which repeat i16 and i8 several times until they fit in i32, and then can
4902 // be manipulated by target suported shuffles.
4903 MVT EltVT = SrcVT.getVectorElementType();
4904 if (EltVT == MVT::i8 || EltVT == MVT::i16)
4905 V1 = PromoteSplati8i16(V1, DAG, EltNo);
4907 // Recreate the 256-bit vector and place the same 128-bit vector
4908 // into the low and high part. This is necessary because we want
4909 // to use VPERM* to shuffle the vectors
4911 V1 = DAG.getNode(ISD::CONCAT_VECTORS, dl, SrcVT, V1, V1);
4914 return getLegalSplat(DAG, V1, EltNo);
4917 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
4918 /// vector of zero or undef vector. This produces a shuffle where the low
4919 /// element of V2 is swizzled into the zero/undef vector, landing at element
4920 /// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
4921 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
4923 const X86Subtarget *Subtarget,
4924 SelectionDAG &DAG) {
4925 MVT VT = V2.getSimpleValueType();
4927 ? getZeroVector(VT, Subtarget, DAG, SDLoc(V2)) : DAG.getUNDEF(VT);
4928 unsigned NumElems = VT.getVectorNumElements();
4929 SmallVector<int, 16> MaskVec;
4930 for (unsigned i = 0; i != NumElems; ++i)
4931 // If this is the insertion idx, put the low elt of V2 here.
4932 MaskVec.push_back(i == Idx ? NumElems : i);
4933 return DAG.getVectorShuffle(VT, SDLoc(V2), V1, V2, &MaskVec[0]);
4936 /// getTargetShuffleMask - Calculates the shuffle mask corresponding to the
4937 /// target specific opcode. Returns true if the Mask could be calculated.
4938 /// Sets IsUnary to true if only uses one source.
4939 static bool getTargetShuffleMask(SDNode *N, MVT VT,
4940 SmallVectorImpl<int> &Mask, bool &IsUnary) {
4941 unsigned NumElems = VT.getVectorNumElements();
4945 switch(N->getOpcode()) {
4947 ImmN = N->getOperand(N->getNumOperands()-1);
4948 DecodeSHUFPMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4950 case X86ISD::UNPCKH:
4951 DecodeUNPCKHMask(VT, Mask);
4953 case X86ISD::UNPCKL:
4954 DecodeUNPCKLMask(VT, Mask);
4956 case X86ISD::MOVHLPS:
4957 DecodeMOVHLPSMask(NumElems, Mask);
4959 case X86ISD::MOVLHPS:
4960 DecodeMOVLHPSMask(NumElems, Mask);
4962 case X86ISD::PALIGNR:
4963 ImmN = N->getOperand(N->getNumOperands()-1);
4964 DecodePALIGNRMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4966 case X86ISD::PSHUFD:
4967 case X86ISD::VPERMILP:
4968 ImmN = N->getOperand(N->getNumOperands()-1);
4969 DecodePSHUFMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4972 case X86ISD::PSHUFHW:
4973 ImmN = N->getOperand(N->getNumOperands()-1);
4974 DecodePSHUFHWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4977 case X86ISD::PSHUFLW:
4978 ImmN = N->getOperand(N->getNumOperands()-1);
4979 DecodePSHUFLWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4982 case X86ISD::VPERMI:
4983 ImmN = N->getOperand(N->getNumOperands()-1);
4984 DecodeVPERMMask(cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4988 case X86ISD::MOVSD: {
4989 // The index 0 always comes from the first element of the second source,
4990 // this is why MOVSS and MOVSD are used in the first place. The other
4991 // elements come from the other positions of the first source vector
4992 Mask.push_back(NumElems);
4993 for (unsigned i = 1; i != NumElems; ++i) {
4998 case X86ISD::VPERM2X128:
4999 ImmN = N->getOperand(N->getNumOperands()-1);
5000 DecodeVPERM2X128Mask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5001 if (Mask.empty()) return false;
5003 case X86ISD::MOVDDUP:
5004 case X86ISD::MOVLHPD:
5005 case X86ISD::MOVLPD:
5006 case X86ISD::MOVLPS:
5007 case X86ISD::MOVSHDUP:
5008 case X86ISD::MOVSLDUP:
5009 // Not yet implemented
5011 default: llvm_unreachable("unknown target shuffle node");
5017 /// getShuffleScalarElt - Returns the scalar element that will make up the ith
5018 /// element of the result of the vector shuffle.
5019 static SDValue getShuffleScalarElt(SDNode *N, unsigned Index, SelectionDAG &DAG,
5022 return SDValue(); // Limit search depth.
5024 SDValue V = SDValue(N, 0);
5025 EVT VT = V.getValueType();
5026 unsigned Opcode = V.getOpcode();
5028 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars.
5029 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) {
5030 int Elt = SV->getMaskElt(Index);
5033 return DAG.getUNDEF(VT.getVectorElementType());
5035 unsigned NumElems = VT.getVectorNumElements();
5036 SDValue NewV = (Elt < (int)NumElems) ? SV->getOperand(0)
5037 : SV->getOperand(1);
5038 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG, Depth+1);
5041 // Recurse into target specific vector shuffles to find scalars.
5042 if (isTargetShuffle(Opcode)) {
5043 MVT ShufVT = V.getSimpleValueType();
5044 unsigned NumElems = ShufVT.getVectorNumElements();
5045 SmallVector<int, 16> ShuffleMask;
5048 if (!getTargetShuffleMask(N, ShufVT, ShuffleMask, IsUnary))
5051 int Elt = ShuffleMask[Index];
5053 return DAG.getUNDEF(ShufVT.getVectorElementType());
5055 SDValue NewV = (Elt < (int)NumElems) ? N->getOperand(0)
5057 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG,
5061 // Actual nodes that may contain scalar elements
5062 if (Opcode == ISD::BITCAST) {
5063 V = V.getOperand(0);
5064 EVT SrcVT = V.getValueType();
5065 unsigned NumElems = VT.getVectorNumElements();
5067 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems)
5071 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR)
5072 return (Index == 0) ? V.getOperand(0)
5073 : DAG.getUNDEF(VT.getVectorElementType());
5075 if (V.getOpcode() == ISD::BUILD_VECTOR)
5076 return V.getOperand(Index);
5081 /// getNumOfConsecutiveZeros - Return the number of elements of a vector
5082 /// shuffle operation which come from a consecutively from a zero. The
5083 /// search can start in two different directions, from left or right.
5084 /// We count undefs as zeros until PreferredNum is reached.
5085 static unsigned getNumOfConsecutiveZeros(ShuffleVectorSDNode *SVOp,
5086 unsigned NumElems, bool ZerosFromLeft,
5088 unsigned PreferredNum = -1U) {
5089 unsigned NumZeros = 0;
5090 for (unsigned i = 0; i != NumElems; ++i) {
5091 unsigned Index = ZerosFromLeft ? i : NumElems - i - 1;
5092 SDValue Elt = getShuffleScalarElt(SVOp, Index, DAG, 0);
5096 if (X86::isZeroNode(Elt))
5098 else if (Elt.getOpcode() == ISD::UNDEF) // Undef as zero up to PreferredNum.
5099 NumZeros = std::min(NumZeros + 1, PreferredNum);
5107 /// isShuffleMaskConsecutive - Check if the shuffle mask indicies [MaskI, MaskE)
5108 /// correspond consecutively to elements from one of the vector operands,
5109 /// starting from its index OpIdx. Also tell OpNum which source vector operand.
5111 bool isShuffleMaskConsecutive(ShuffleVectorSDNode *SVOp,
5112 unsigned MaskI, unsigned MaskE, unsigned OpIdx,
5113 unsigned NumElems, unsigned &OpNum) {
5114 bool SeenV1 = false;
5115 bool SeenV2 = false;
5117 for (unsigned i = MaskI; i != MaskE; ++i, ++OpIdx) {
5118 int Idx = SVOp->getMaskElt(i);
5119 // Ignore undef indicies
5123 if (Idx < (int)NumElems)
5128 // Only accept consecutive elements from the same vector
5129 if ((Idx % NumElems != OpIdx) || (SeenV1 && SeenV2))
5133 OpNum = SeenV1 ? 0 : 1;
5137 /// isVectorShiftRight - Returns true if the shuffle can be implemented as a
5138 /// logical left shift of a vector.
5139 static bool isVectorShiftRight(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5140 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5142 SVOp->getSimpleValueType(0).getVectorNumElements();
5143 unsigned NumZeros = getNumOfConsecutiveZeros(
5144 SVOp, NumElems, false /* check zeros from right */, DAG,
5145 SVOp->getMaskElt(0));
5151 // Considering the elements in the mask that are not consecutive zeros,
5152 // check if they consecutively come from only one of the source vectors.
5154 // V1 = {X, A, B, C} 0
5156 // vector_shuffle V1, V2 <1, 2, 3, X>
5158 if (!isShuffleMaskConsecutive(SVOp,
5159 0, // Mask Start Index
5160 NumElems-NumZeros, // Mask End Index(exclusive)
5161 NumZeros, // Where to start looking in the src vector
5162 NumElems, // Number of elements in vector
5163 OpSrc)) // Which source operand ?
5168 ShVal = SVOp->getOperand(OpSrc);
5172 /// isVectorShiftLeft - Returns true if the shuffle can be implemented as a
5173 /// logical left shift of a vector.
5174 static bool isVectorShiftLeft(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5175 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5177 SVOp->getSimpleValueType(0).getVectorNumElements();
5178 unsigned NumZeros = getNumOfConsecutiveZeros(
5179 SVOp, NumElems, true /* check zeros from left */, DAG,
5180 NumElems - SVOp->getMaskElt(NumElems - 1) - 1);
5186 // Considering the elements in the mask that are not consecutive zeros,
5187 // check if they consecutively come from only one of the source vectors.
5189 // 0 { A, B, X, X } = V2
5191 // vector_shuffle V1, V2 <X, X, 4, 5>
5193 if (!isShuffleMaskConsecutive(SVOp,
5194 NumZeros, // Mask Start Index
5195 NumElems, // Mask End Index(exclusive)
5196 0, // Where to start looking in the src vector
5197 NumElems, // Number of elements in vector
5198 OpSrc)) // Which source operand ?
5203 ShVal = SVOp->getOperand(OpSrc);
5207 /// isVectorShift - Returns true if the shuffle can be implemented as a
5208 /// logical left or right shift of a vector.
5209 static bool isVectorShift(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5210 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5211 // Although the logic below support any bitwidth size, there are no
5212 // shift instructions which handle more than 128-bit vectors.
5213 if (!SVOp->getSimpleValueType(0).is128BitVector())
5216 if (isVectorShiftLeft(SVOp, DAG, isLeft, ShVal, ShAmt) ||
5217 isVectorShiftRight(SVOp, DAG, isLeft, ShVal, ShAmt))
5223 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
5225 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
5226 unsigned NumNonZero, unsigned NumZero,
5228 const X86Subtarget* Subtarget,
5229 const TargetLowering &TLI) {
5236 for (unsigned i = 0; i < 16; ++i) {
5237 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
5238 if (ThisIsNonZero && First) {
5240 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
5242 V = DAG.getUNDEF(MVT::v8i16);
5247 SDValue ThisElt(0, 0), LastElt(0, 0);
5248 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
5249 if (LastIsNonZero) {
5250 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
5251 MVT::i16, Op.getOperand(i-1));
5253 if (ThisIsNonZero) {
5254 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
5255 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
5256 ThisElt, DAG.getConstant(8, MVT::i8));
5258 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
5262 if (ThisElt.getNode())
5263 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
5264 DAG.getIntPtrConstant(i/2));
5268 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V);
5271 /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
5273 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
5274 unsigned NumNonZero, unsigned NumZero,
5276 const X86Subtarget* Subtarget,
5277 const TargetLowering &TLI) {
5284 for (unsigned i = 0; i < 8; ++i) {
5285 bool isNonZero = (NonZeros & (1 << i)) != 0;
5289 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
5291 V = DAG.getUNDEF(MVT::v8i16);
5294 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
5295 MVT::v8i16, V, Op.getOperand(i),
5296 DAG.getIntPtrConstant(i));
5303 /// getVShift - Return a vector logical shift node.
5305 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
5306 unsigned NumBits, SelectionDAG &DAG,
5307 const TargetLowering &TLI, SDLoc dl) {
5308 assert(VT.is128BitVector() && "Unknown type for VShift");
5309 EVT ShVT = MVT::v2i64;
5310 unsigned Opc = isLeft ? X86ISD::VSHLDQ : X86ISD::VSRLDQ;
5311 SrcOp = DAG.getNode(ISD::BITCAST, dl, ShVT, SrcOp);
5312 return DAG.getNode(ISD::BITCAST, dl, VT,
5313 DAG.getNode(Opc, dl, ShVT, SrcOp,
5314 DAG.getConstant(NumBits,
5315 TLI.getScalarShiftAmountTy(SrcOp.getValueType()))));
5319 LowerAsSplatVectorLoad(SDValue SrcOp, MVT VT, SDLoc dl, SelectionDAG &DAG) {
5321 // Check if the scalar load can be widened into a vector load. And if
5322 // the address is "base + cst" see if the cst can be "absorbed" into
5323 // the shuffle mask.
5324 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) {
5325 SDValue Ptr = LD->getBasePtr();
5326 if (!ISD::isNormalLoad(LD) || LD->isVolatile())
5328 EVT PVT = LD->getValueType(0);
5329 if (PVT != MVT::i32 && PVT != MVT::f32)
5334 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) {
5335 FI = FINode->getIndex();
5337 } else if (DAG.isBaseWithConstantOffset(Ptr) &&
5338 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
5339 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
5340 Offset = Ptr.getConstantOperandVal(1);
5341 Ptr = Ptr.getOperand(0);
5346 // FIXME: 256-bit vector instructions don't require a strict alignment,
5347 // improve this code to support it better.
5348 unsigned RequiredAlign = VT.getSizeInBits()/8;
5349 SDValue Chain = LD->getChain();
5350 // Make sure the stack object alignment is at least 16 or 32.
5351 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
5352 if (DAG.InferPtrAlignment(Ptr) < RequiredAlign) {
5353 if (MFI->isFixedObjectIndex(FI)) {
5354 // Can't change the alignment. FIXME: It's possible to compute
5355 // the exact stack offset and reference FI + adjust offset instead.
5356 // If someone *really* cares about this. That's the way to implement it.
5359 MFI->setObjectAlignment(FI, RequiredAlign);
5363 // (Offset % 16 or 32) must be multiple of 4. Then address is then
5364 // Ptr + (Offset & ~15).
5367 if ((Offset % RequiredAlign) & 3)
5369 int64_t StartOffset = Offset & ~(RequiredAlign-1);
5371 Ptr = DAG.getNode(ISD::ADD, SDLoc(Ptr), Ptr.getValueType(),
5372 Ptr,DAG.getConstant(StartOffset, Ptr.getValueType()));
5374 int EltNo = (Offset - StartOffset) >> 2;
5375 unsigned NumElems = VT.getVectorNumElements();
5377 EVT NVT = EVT::getVectorVT(*DAG.getContext(), PVT, NumElems);
5378 SDValue V1 = DAG.getLoad(NVT, dl, Chain, Ptr,
5379 LD->getPointerInfo().getWithOffset(StartOffset),
5380 false, false, false, 0);
5382 SmallVector<int, 8> Mask;
5383 for (unsigned i = 0; i != NumElems; ++i)
5384 Mask.push_back(EltNo);
5386 return DAG.getVectorShuffle(NVT, dl, V1, DAG.getUNDEF(NVT), &Mask[0]);
5392 /// EltsFromConsecutiveLoads - Given the initializing elements 'Elts' of a
5393 /// vector of type 'VT', see if the elements can be replaced by a single large
5394 /// load which has the same value as a build_vector whose operands are 'elts'.
5396 /// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a
5398 /// FIXME: we'd also like to handle the case where the last elements are zero
5399 /// rather than undef via VZEXT_LOAD, but we do not detect that case today.
5400 /// There's even a handy isZeroNode for that purpose.
5401 static SDValue EltsFromConsecutiveLoads(EVT VT, SmallVectorImpl<SDValue> &Elts,
5402 SDLoc &DL, SelectionDAG &DAG) {
5403 EVT EltVT = VT.getVectorElementType();
5404 unsigned NumElems = Elts.size();
5406 LoadSDNode *LDBase = NULL;
5407 unsigned LastLoadedElt = -1U;
5409 // For each element in the initializer, see if we've found a load or an undef.
5410 // If we don't find an initial load element, or later load elements are
5411 // non-consecutive, bail out.
5412 for (unsigned i = 0; i < NumElems; ++i) {
5413 SDValue Elt = Elts[i];
5415 if (!Elt.getNode() ||
5416 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
5419 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
5421 LDBase = cast<LoadSDNode>(Elt.getNode());
5425 if (Elt.getOpcode() == ISD::UNDEF)
5428 LoadSDNode *LD = cast<LoadSDNode>(Elt);
5429 if (!DAG.isConsecutiveLoad(LD, LDBase, EltVT.getSizeInBits()/8, i))
5434 // If we have found an entire vector of loads and undefs, then return a large
5435 // load of the entire vector width starting at the base pointer. If we found
5436 // consecutive loads for the low half, generate a vzext_load node.
5437 if (LastLoadedElt == NumElems - 1) {
5438 SDValue NewLd = SDValue();
5439 if (DAG.InferPtrAlignment(LDBase->getBasePtr()) >= 16)
5440 NewLd = DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
5441 LDBase->getPointerInfo(),
5442 LDBase->isVolatile(), LDBase->isNonTemporal(),
5443 LDBase->isInvariant(), 0);
5444 NewLd = DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
5445 LDBase->getPointerInfo(),
5446 LDBase->isVolatile(), LDBase->isNonTemporal(),
5447 LDBase->isInvariant(), LDBase->getAlignment());
5449 if (LDBase->hasAnyUseOfValue(1)) {
5450 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
5452 SDValue(NewLd.getNode(), 1));
5453 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
5454 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
5455 SDValue(NewLd.getNode(), 1));
5460 if (NumElems == 4 && LastLoadedElt == 1 &&
5461 DAG.getTargetLoweringInfo().isTypeLegal(MVT::v2i64)) {
5462 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
5463 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() };
5465 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys, Ops,
5466 array_lengthof(Ops), MVT::i64,
5467 LDBase->getPointerInfo(),
5468 LDBase->getAlignment(),
5469 false/*isVolatile*/, true/*ReadMem*/,
5472 // Make sure the newly-created LOAD is in the same position as LDBase in
5473 // terms of dependency. We create a TokenFactor for LDBase and ResNode, and
5474 // update uses of LDBase's output chain to use the TokenFactor.
5475 if (LDBase->hasAnyUseOfValue(1)) {
5476 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
5477 SDValue(LDBase, 1), SDValue(ResNode.getNode(), 1));
5478 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
5479 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
5480 SDValue(ResNode.getNode(), 1));
5483 return DAG.getNode(ISD::BITCAST, DL, VT, ResNode);
5488 /// LowerVectorBroadcast - Attempt to use the vbroadcast instruction
5489 /// to generate a splat value for the following cases:
5490 /// 1. A splat BUILD_VECTOR which uses a single scalar load, or a constant.
5491 /// 2. A splat shuffle which uses a scalar_to_vector node which comes from
5492 /// a scalar load, or a constant.
5493 /// The VBROADCAST node is returned when a pattern is found,
5494 /// or SDValue() otherwise.
5495 static SDValue LowerVectorBroadcast(SDValue Op, const X86Subtarget* Subtarget,
5496 SelectionDAG &DAG) {
5497 if (!Subtarget->hasFp256())
5500 MVT VT = Op.getSimpleValueType();
5503 assert((VT.is128BitVector() || VT.is256BitVector() || VT.is512BitVector()) &&
5504 "Unsupported vector type for broadcast.");
5509 switch (Op.getOpcode()) {
5511 // Unknown pattern found.
5514 case ISD::BUILD_VECTOR: {
5515 // The BUILD_VECTOR node must be a splat.
5516 if (!isSplatVector(Op.getNode()))
5519 Ld = Op.getOperand(0);
5520 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
5521 Ld.getOpcode() == ISD::ConstantFP);
5523 // The suspected load node has several users. Make sure that all
5524 // of its users are from the BUILD_VECTOR node.
5525 // Constants may have multiple users.
5526 if (!ConstSplatVal && !Ld->hasNUsesOfValue(VT.getVectorNumElements(), 0))
5531 case ISD::VECTOR_SHUFFLE: {
5532 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
5534 // Shuffles must have a splat mask where the first element is
5536 if ((!SVOp->isSplat()) || SVOp->getMaskElt(0) != 0)
5539 SDValue Sc = Op.getOperand(0);
5540 if (Sc.getOpcode() != ISD::SCALAR_TO_VECTOR &&
5541 Sc.getOpcode() != ISD::BUILD_VECTOR) {
5543 if (!Subtarget->hasInt256())
5546 // Use the register form of the broadcast instruction available on AVX2.
5547 if (VT.getSizeInBits() >= 256)
5548 Sc = Extract128BitVector(Sc, 0, DAG, dl);
5549 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Sc);
5552 Ld = Sc.getOperand(0);
5553 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
5554 Ld.getOpcode() == ISD::ConstantFP);
5556 // The scalar_to_vector node and the suspected
5557 // load node must have exactly one user.
5558 // Constants may have multiple users.
5560 // AVX-512 has register version of the broadcast
5561 bool hasRegVer = Subtarget->hasAVX512() && VT.is512BitVector() &&
5562 Ld.getValueType().getSizeInBits() >= 32;
5563 if (!ConstSplatVal && ((!Sc.hasOneUse() || !Ld.hasOneUse()) &&
5570 bool IsGE256 = (VT.getSizeInBits() >= 256);
5572 // Handle the broadcasting a single constant scalar from the constant pool
5573 // into a vector. On Sandybridge it is still better to load a constant vector
5574 // from the constant pool and not to broadcast it from a scalar.
5575 if (ConstSplatVal && Subtarget->hasInt256()) {
5576 EVT CVT = Ld.getValueType();
5577 assert(!CVT.isVector() && "Must not broadcast a vector type");
5578 unsigned ScalarSize = CVT.getSizeInBits();
5580 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64)) {
5581 const Constant *C = 0;
5582 if (ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Ld))
5583 C = CI->getConstantIntValue();
5584 else if (ConstantFPSDNode *CF = dyn_cast<ConstantFPSDNode>(Ld))
5585 C = CF->getConstantFPValue();
5587 assert(C && "Invalid constant type");
5589 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5590 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
5591 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
5592 Ld = DAG.getLoad(CVT, dl, DAG.getEntryNode(), CP,
5593 MachinePointerInfo::getConstantPool(),
5594 false, false, false, Alignment);
5596 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5600 bool IsLoad = ISD::isNormalLoad(Ld.getNode());
5601 unsigned ScalarSize = Ld.getValueType().getSizeInBits();
5603 // Handle AVX2 in-register broadcasts.
5604 if (!IsLoad && Subtarget->hasInt256() &&
5605 (ScalarSize == 32 || (IsGE256 && ScalarSize == 64)))
5606 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5608 // The scalar source must be a normal load.
5612 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64))
5613 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5615 // The integer check is needed for the 64-bit into 128-bit so it doesn't match
5616 // double since there is no vbroadcastsd xmm
5617 if (Subtarget->hasInt256() && Ld.getValueType().isInteger()) {
5618 if (ScalarSize == 8 || ScalarSize == 16 || ScalarSize == 64)
5619 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5622 // Unsupported broadcast.
5626 static SDValue buildFromShuffleMostly(SDValue Op, SelectionDAG &DAG) {
5627 MVT VT = Op.getSimpleValueType();
5629 // Skip if insert_vec_elt is not supported.
5630 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5631 if (!TLI.isOperationLegalOrCustom(ISD::INSERT_VECTOR_ELT, VT))
5635 unsigned NumElems = Op.getNumOperands();
5639 SmallVector<unsigned, 4> InsertIndices;
5640 SmallVector<int, 8> Mask(NumElems, -1);
5642 for (unsigned i = 0; i != NumElems; ++i) {
5643 unsigned Opc = Op.getOperand(i).getOpcode();
5645 if (Opc == ISD::UNDEF)
5648 if (Opc != ISD::EXTRACT_VECTOR_ELT) {
5649 // Quit if more than 1 elements need inserting.
5650 if (InsertIndices.size() > 1)
5653 InsertIndices.push_back(i);
5657 SDValue ExtractedFromVec = Op.getOperand(i).getOperand(0);
5658 SDValue ExtIdx = Op.getOperand(i).getOperand(1);
5660 // Quit if extracted from vector of different type.
5661 if (ExtractedFromVec.getValueType() != VT)
5664 // Quit if non-constant index.
5665 if (!isa<ConstantSDNode>(ExtIdx))
5668 if (VecIn1.getNode() == 0)
5669 VecIn1 = ExtractedFromVec;
5670 else if (VecIn1 != ExtractedFromVec) {
5671 if (VecIn2.getNode() == 0)
5672 VecIn2 = ExtractedFromVec;
5673 else if (VecIn2 != ExtractedFromVec)
5674 // Quit if more than 2 vectors to shuffle
5678 unsigned Idx = cast<ConstantSDNode>(ExtIdx)->getZExtValue();
5680 if (ExtractedFromVec == VecIn1)
5682 else if (ExtractedFromVec == VecIn2)
5683 Mask[i] = Idx + NumElems;
5686 if (VecIn1.getNode() == 0)
5689 VecIn2 = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT);
5690 SDValue NV = DAG.getVectorShuffle(VT, DL, VecIn1, VecIn2, &Mask[0]);
5691 for (unsigned i = 0, e = InsertIndices.size(); i != e; ++i) {
5692 unsigned Idx = InsertIndices[i];
5693 NV = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VT, NV, Op.getOperand(Idx),
5694 DAG.getIntPtrConstant(Idx));
5700 // Lower BUILD_VECTOR operation for v8i1 and v16i1 types.
5702 X86TargetLowering::LowerBUILD_VECTORvXi1(SDValue Op, SelectionDAG &DAG) const {
5704 MVT VT = Op.getSimpleValueType();
5705 assert((VT.getVectorElementType() == MVT::i1) && (VT.getSizeInBits() <= 16) &&
5706 "Unexpected type in LowerBUILD_VECTORvXi1!");
5709 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
5710 SDValue Cst = DAG.getTargetConstant(0, MVT::i1);
5711 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst,
5712 Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5713 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT,
5714 Ops, VT.getVectorNumElements());
5717 if (ISD::isBuildVectorAllOnes(Op.getNode())) {
5718 SDValue Cst = DAG.getTargetConstant(1, MVT::i1);
5719 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst,
5720 Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5721 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT,
5722 Ops, VT.getVectorNumElements());
5725 bool AllContants = true;
5726 uint64_t Immediate = 0;
5727 for (unsigned idx = 0, e = Op.getNumOperands(); idx < e; ++idx) {
5728 SDValue In = Op.getOperand(idx);
5729 if (In.getOpcode() == ISD::UNDEF)
5731 if (!isa<ConstantSDNode>(In)) {
5732 AllContants = false;
5735 if (cast<ConstantSDNode>(In)->getZExtValue())
5736 Immediate |= (1ULL << idx);
5740 SDValue FullMask = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1,
5741 DAG.getConstant(Immediate, MVT::i16));
5742 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, FullMask,
5743 DAG.getIntPtrConstant(0));
5746 // Splat vector (with undefs)
5747 SDValue In = Op.getOperand(0);
5748 for (unsigned i = 1, e = Op.getNumOperands(); i != e; ++i) {
5749 if (Op.getOperand(i) != In && Op.getOperand(i).getOpcode() != ISD::UNDEF)
5750 llvm_unreachable("Unsupported predicate operation");
5753 SDValue EFLAGS, X86CC;
5754 if (In.getOpcode() == ISD::SETCC) {
5755 SDValue Op0 = In.getOperand(0);
5756 SDValue Op1 = In.getOperand(1);
5757 ISD::CondCode CC = cast<CondCodeSDNode>(In.getOperand(2))->get();
5758 bool isFP = Op1.getValueType().isFloatingPoint();
5759 unsigned X86CCVal = TranslateX86CC(CC, isFP, Op0, Op1, DAG);
5761 assert(X86CCVal != X86::COND_INVALID && "Unsupported predicate operation");
5763 X86CC = DAG.getConstant(X86CCVal, MVT::i8);
5764 EFLAGS = EmitCmp(Op0, Op1, X86CCVal, DAG);
5765 EFLAGS = ConvertCmpIfNecessary(EFLAGS, DAG);
5766 } else if (In.getOpcode() == X86ISD::SETCC) {
5767 X86CC = In.getOperand(0);
5768 EFLAGS = In.getOperand(1);
5777 // res = allOnes ### CMOVNE -1, %res
5780 MVT InVT = In.getSimpleValueType();
5781 SDValue Bit1 = DAG.getNode(ISD::AND, dl, InVT, In, DAG.getConstant(1, InVT));
5782 EFLAGS = EmitTest(Bit1, X86::COND_NE, DAG);
5783 X86CC = DAG.getConstant(X86::COND_NE, MVT::i8);
5786 if (VT == MVT::v16i1) {
5787 SDValue Cst1 = DAG.getConstant(-1, MVT::i16);
5788 SDValue Cst0 = DAG.getConstant(0, MVT::i16);
5789 SDValue CmovOp = DAG.getNode(X86ISD::CMOV, dl, MVT::i16,
5790 Cst0, Cst1, X86CC, EFLAGS);
5791 return DAG.getNode(ISD::BITCAST, dl, VT, CmovOp);
5794 if (VT == MVT::v8i1) {
5795 SDValue Cst1 = DAG.getConstant(-1, MVT::i32);
5796 SDValue Cst0 = DAG.getConstant(0, MVT::i32);
5797 SDValue CmovOp = DAG.getNode(X86ISD::CMOV, dl, MVT::i32,
5798 Cst0, Cst1, X86CC, EFLAGS);
5799 CmovOp = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, CmovOp);
5800 return DAG.getNode(ISD::BITCAST, dl, VT, CmovOp);
5802 llvm_unreachable("Unsupported predicate operation");
5806 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
5809 MVT VT = Op.getSimpleValueType();
5810 MVT ExtVT = VT.getVectorElementType();
5811 unsigned NumElems = Op.getNumOperands();
5813 // Generate vectors for predicate vectors.
5814 if (VT.getScalarType() == MVT::i1 && Subtarget->hasAVX512())
5815 return LowerBUILD_VECTORvXi1(Op, DAG);
5817 // Vectors containing all zeros can be matched by pxor and xorps later
5818 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
5819 // Canonicalize this to <4 x i32> to 1) ensure the zero vectors are CSE'd
5820 // and 2) ensure that i64 scalars are eliminated on x86-32 hosts.
5821 if (VT == MVT::v4i32 || VT == MVT::v8i32 || VT == MVT::v16i32)
5824 return getZeroVector(VT, Subtarget, DAG, dl);
5827 // Vectors containing all ones can be matched by pcmpeqd on 128-bit width
5828 // vectors or broken into v4i32 operations on 256-bit vectors. AVX2 can use
5829 // vpcmpeqd on 256-bit vectors.
5830 if (Subtarget->hasSSE2() && ISD::isBuildVectorAllOnes(Op.getNode())) {
5831 if (VT == MVT::v4i32 || (VT == MVT::v8i32 && Subtarget->hasInt256()))
5834 if (!VT.is512BitVector())
5835 return getOnesVector(VT, Subtarget->hasInt256(), DAG, dl);
5838 SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG);
5839 if (Broadcast.getNode())
5842 unsigned EVTBits = ExtVT.getSizeInBits();
5844 unsigned NumZero = 0;
5845 unsigned NumNonZero = 0;
5846 unsigned NonZeros = 0;
5847 bool IsAllConstants = true;
5848 SmallSet<SDValue, 8> Values;
5849 for (unsigned i = 0; i < NumElems; ++i) {
5850 SDValue Elt = Op.getOperand(i);
5851 if (Elt.getOpcode() == ISD::UNDEF)
5854 if (Elt.getOpcode() != ISD::Constant &&
5855 Elt.getOpcode() != ISD::ConstantFP)
5856 IsAllConstants = false;
5857 if (X86::isZeroNode(Elt))
5860 NonZeros |= (1 << i);
5865 // All undef vector. Return an UNDEF. All zero vectors were handled above.
5866 if (NumNonZero == 0)
5867 return DAG.getUNDEF(VT);
5869 // Special case for single non-zero, non-undef, element.
5870 if (NumNonZero == 1) {
5871 unsigned Idx = countTrailingZeros(NonZeros);
5872 SDValue Item = Op.getOperand(Idx);
5874 // If this is an insertion of an i64 value on x86-32, and if the top bits of
5875 // the value are obviously zero, truncate the value to i32 and do the
5876 // insertion that way. Only do this if the value is non-constant or if the
5877 // value is a constant being inserted into element 0. It is cheaper to do
5878 // a constant pool load than it is to do a movd + shuffle.
5879 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
5880 (!IsAllConstants || Idx == 0)) {
5881 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
5883 assert(VT == MVT::v2i64 && "Expected an SSE value type!");
5884 EVT VecVT = MVT::v4i32;
5885 unsigned VecElts = 4;
5887 // Truncate the value (which may itself be a constant) to i32, and
5888 // convert it to a vector with movd (S2V+shuffle to zero extend).
5889 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
5890 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
5891 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
5893 // Now we have our 32-bit value zero extended in the low element of
5894 // a vector. If Idx != 0, swizzle it into place.
5896 SmallVector<int, 4> Mask;
5897 Mask.push_back(Idx);
5898 for (unsigned i = 1; i != VecElts; ++i)
5900 Item = DAG.getVectorShuffle(VecVT, dl, Item, DAG.getUNDEF(VecVT),
5903 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
5907 // If we have a constant or non-constant insertion into the low element of
5908 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
5909 // the rest of the elements. This will be matched as movd/movq/movss/movsd
5910 // depending on what the source datatype is.
5913 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5915 if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
5916 (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
5917 if (VT.is256BitVector() || VT.is512BitVector()) {
5918 SDValue ZeroVec = getZeroVector(VT, Subtarget, DAG, dl);
5919 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, ZeroVec,
5920 Item, DAG.getIntPtrConstant(0));
5922 assert(VT.is128BitVector() && "Expected an SSE value type!");
5923 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5924 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
5925 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
5928 if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
5929 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
5930 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
5931 if (VT.is256BitVector()) {
5932 SDValue ZeroVec = getZeroVector(MVT::v8i32, Subtarget, DAG, dl);
5933 Item = Insert128BitVector(ZeroVec, Item, 0, DAG, dl);
5935 assert(VT.is128BitVector() && "Expected an SSE value type!");
5936 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
5938 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
5942 // Is it a vector logical left shift?
5943 if (NumElems == 2 && Idx == 1 &&
5944 X86::isZeroNode(Op.getOperand(0)) &&
5945 !X86::isZeroNode(Op.getOperand(1))) {
5946 unsigned NumBits = VT.getSizeInBits();
5947 return getVShift(true, VT,
5948 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
5949 VT, Op.getOperand(1)),
5950 NumBits/2, DAG, *this, dl);
5953 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
5956 // Otherwise, if this is a vector with i32 or f32 elements, and the element
5957 // is a non-constant being inserted into an element other than the low one,
5958 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
5959 // movd/movss) to move this into the low element, then shuffle it into
5961 if (EVTBits == 32) {
5962 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5964 // Turn it into a shuffle of zero and zero-extended scalar to vector.
5965 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0, Subtarget, DAG);
5966 SmallVector<int, 8> MaskVec;
5967 for (unsigned i = 0; i != NumElems; ++i)
5968 MaskVec.push_back(i == Idx ? 0 : 1);
5969 return DAG.getVectorShuffle(VT, dl, Item, DAG.getUNDEF(VT), &MaskVec[0]);
5973 // Splat is obviously ok. Let legalizer expand it to a shuffle.
5974 if (Values.size() == 1) {
5975 if (EVTBits == 32) {
5976 // Instead of a shuffle like this:
5977 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
5978 // Check if it's possible to issue this instead.
5979 // shuffle (vload ptr)), undef, <1, 1, 1, 1>
5980 unsigned Idx = countTrailingZeros(NonZeros);
5981 SDValue Item = Op.getOperand(Idx);
5982 if (Op.getNode()->isOnlyUserOf(Item.getNode()))
5983 return LowerAsSplatVectorLoad(Item, VT, dl, DAG);
5988 // A vector full of immediates; various special cases are already
5989 // handled, so this is best done with a single constant-pool load.
5993 // For AVX-length vectors, build the individual 128-bit pieces and use
5994 // shuffles to put them in place.
5995 if (VT.is256BitVector()) {
5996 SmallVector<SDValue, 32> V;
5997 for (unsigned i = 0; i != NumElems; ++i)
5998 V.push_back(Op.getOperand(i));
6000 EVT HVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems/2);
6002 // Build both the lower and upper subvector.
6003 SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT, &V[0], NumElems/2);
6004 SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT, &V[NumElems / 2],
6007 // Recreate the wider vector with the lower and upper part.
6008 return Concat128BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
6011 // Let legalizer expand 2-wide build_vectors.
6012 if (EVTBits == 64) {
6013 if (NumNonZero == 1) {
6014 // One half is zero or undef.
6015 unsigned Idx = countTrailingZeros(NonZeros);
6016 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
6017 Op.getOperand(Idx));
6018 return getShuffleVectorZeroOrUndef(V2, Idx, true, Subtarget, DAG);
6023 // If element VT is < 32 bits, convert it to inserts into a zero vector.
6024 if (EVTBits == 8 && NumElems == 16) {
6025 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
6027 if (V.getNode()) return V;
6030 if (EVTBits == 16 && NumElems == 8) {
6031 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
6033 if (V.getNode()) return V;
6036 // If element VT is == 32 bits, turn it into a number of shuffles.
6037 SmallVector<SDValue, 8> V(NumElems);
6038 if (NumElems == 4 && NumZero > 0) {
6039 for (unsigned i = 0; i < 4; ++i) {
6040 bool isZero = !(NonZeros & (1 << i));
6042 V[i] = getZeroVector(VT, Subtarget, DAG, dl);
6044 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
6047 for (unsigned i = 0; i < 2; ++i) {
6048 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
6051 V[i] = V[i*2]; // Must be a zero vector.
6054 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
6057 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
6060 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
6065 bool Reverse1 = (NonZeros & 0x3) == 2;
6066 bool Reverse2 = ((NonZeros & (0x3 << 2)) >> 2) == 2;
6070 static_cast<int>(Reverse2 ? NumElems+1 : NumElems),
6071 static_cast<int>(Reverse2 ? NumElems : NumElems+1)
6073 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
6076 if (Values.size() > 1 && VT.is128BitVector()) {
6077 // Check for a build vector of consecutive loads.
6078 for (unsigned i = 0; i < NumElems; ++i)
6079 V[i] = Op.getOperand(i);
6081 // Check for elements which are consecutive loads.
6082 SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG);
6086 // Check for a build vector from mostly shuffle plus few inserting.
6087 SDValue Sh = buildFromShuffleMostly(Op, DAG);
6091 // For SSE 4.1, use insertps to put the high elements into the low element.
6092 if (getSubtarget()->hasSSE41()) {
6094 if (Op.getOperand(0).getOpcode() != ISD::UNDEF)
6095 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0));
6097 Result = DAG.getUNDEF(VT);
6099 for (unsigned i = 1; i < NumElems; ++i) {
6100 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue;
6101 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result,
6102 Op.getOperand(i), DAG.getIntPtrConstant(i));
6107 // Otherwise, expand into a number of unpckl*, start by extending each of
6108 // our (non-undef) elements to the full vector width with the element in the
6109 // bottom slot of the vector (which generates no code for SSE).
6110 for (unsigned i = 0; i < NumElems; ++i) {
6111 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
6112 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
6114 V[i] = DAG.getUNDEF(VT);
6117 // Next, we iteratively mix elements, e.g. for v4f32:
6118 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
6119 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
6120 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
6121 unsigned EltStride = NumElems >> 1;
6122 while (EltStride != 0) {
6123 for (unsigned i = 0; i < EltStride; ++i) {
6124 // If V[i+EltStride] is undef and this is the first round of mixing,
6125 // then it is safe to just drop this shuffle: V[i] is already in the
6126 // right place, the one element (since it's the first round) being
6127 // inserted as undef can be dropped. This isn't safe for successive
6128 // rounds because they will permute elements within both vectors.
6129 if (V[i+EltStride].getOpcode() == ISD::UNDEF &&
6130 EltStride == NumElems/2)
6133 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]);
6142 // LowerAVXCONCAT_VECTORS - 256-bit AVX can use the vinsertf128 instruction
6143 // to create 256-bit vectors from two other 128-bit ones.
6144 static SDValue LowerAVXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
6146 MVT ResVT = Op.getSimpleValueType();
6148 assert((ResVT.is256BitVector() ||
6149 ResVT.is512BitVector()) && "Value type must be 256-/512-bit wide");
6151 SDValue V1 = Op.getOperand(0);
6152 SDValue V2 = Op.getOperand(1);
6153 unsigned NumElems = ResVT.getVectorNumElements();
6154 if(ResVT.is256BitVector())
6155 return Concat128BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
6157 if (Op.getNumOperands() == 4) {
6158 MVT HalfVT = MVT::getVectorVT(ResVT.getScalarType(),
6159 ResVT.getVectorNumElements()/2);
6160 SDValue V3 = Op.getOperand(2);
6161 SDValue V4 = Op.getOperand(3);
6162 return Concat256BitVectors(Concat128BitVectors(V1, V2, HalfVT, NumElems/2, DAG, dl),
6163 Concat128BitVectors(V3, V4, HalfVT, NumElems/2, DAG, dl), ResVT, NumElems, DAG, dl);
6165 return Concat256BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
6168 static SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
6169 MVT LLVM_ATTRIBUTE_UNUSED VT = Op.getSimpleValueType();
6170 assert((VT.is256BitVector() && Op.getNumOperands() == 2) ||
6171 (VT.is512BitVector() && (Op.getNumOperands() == 2 ||
6172 Op.getNumOperands() == 4)));
6174 // AVX can use the vinsertf128 instruction to create 256-bit vectors
6175 // from two other 128-bit ones.
6177 // 512-bit vector may contain 2 256-bit vectors or 4 128-bit vectors
6178 return LowerAVXCONCAT_VECTORS(Op, DAG);
6181 // Try to lower a shuffle node into a simple blend instruction.
6183 LowerVECTOR_SHUFFLEtoBlend(ShuffleVectorSDNode *SVOp,
6184 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
6185 SDValue V1 = SVOp->getOperand(0);
6186 SDValue V2 = SVOp->getOperand(1);
6188 MVT VT = SVOp->getSimpleValueType(0);
6189 MVT EltVT = VT.getVectorElementType();
6190 unsigned NumElems = VT.getVectorNumElements();
6192 // There is no blend with immediate in AVX-512.
6193 if (VT.is512BitVector())
6196 if (!Subtarget->hasSSE41() || EltVT == MVT::i8)
6198 if (!Subtarget->hasInt256() && VT == MVT::v16i16)
6201 // Check the mask for BLEND and build the value.
6202 unsigned MaskValue = 0;
6203 // There are 2 lanes if (NumElems > 8), and 1 lane otherwise.
6204 unsigned NumLanes = (NumElems-1)/8 + 1;
6205 unsigned NumElemsInLane = NumElems / NumLanes;
6207 // Blend for v16i16 should be symetric for the both lanes.
6208 for (unsigned i = 0; i < NumElemsInLane; ++i) {
6210 int SndLaneEltIdx = (NumLanes == 2) ?
6211 SVOp->getMaskElt(i + NumElemsInLane) : -1;
6212 int EltIdx = SVOp->getMaskElt(i);
6214 if ((EltIdx < 0 || EltIdx == (int)i) &&
6215 (SndLaneEltIdx < 0 || SndLaneEltIdx == (int)(i + NumElemsInLane)))
6218 if (((unsigned)EltIdx == (i + NumElems)) &&
6219 (SndLaneEltIdx < 0 ||
6220 (unsigned)SndLaneEltIdx == i + NumElems + NumElemsInLane))
6221 MaskValue |= (1<<i);
6226 // Convert i32 vectors to floating point if it is not AVX2.
6227 // AVX2 introduced VPBLENDD instruction for 128 and 256-bit vectors.
6229 if (EltVT == MVT::i64 || (EltVT == MVT::i32 && !Subtarget->hasInt256())) {
6230 BlendVT = MVT::getVectorVT(MVT::getFloatingPointVT(EltVT.getSizeInBits()),
6232 V1 = DAG.getNode(ISD::BITCAST, dl, VT, V1);
6233 V2 = DAG.getNode(ISD::BITCAST, dl, VT, V2);
6236 SDValue Ret = DAG.getNode(X86ISD::BLENDI, dl, BlendVT, V1, V2,
6237 DAG.getConstant(MaskValue, MVT::i32));
6238 return DAG.getNode(ISD::BITCAST, dl, VT, Ret);
6241 // v8i16 shuffles - Prefer shuffles in the following order:
6242 // 1. [all] pshuflw, pshufhw, optional move
6243 // 2. [ssse3] 1 x pshufb
6244 // 3. [ssse3] 2 x pshufb + 1 x por
6245 // 4. [all] mov + pshuflw + pshufhw + N x (pextrw + pinsrw)
6247 LowerVECTOR_SHUFFLEv8i16(SDValue Op, const X86Subtarget *Subtarget,
6248 SelectionDAG &DAG) {
6249 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6250 SDValue V1 = SVOp->getOperand(0);
6251 SDValue V2 = SVOp->getOperand(1);
6253 SmallVector<int, 8> MaskVals;
6255 // Determine if more than 1 of the words in each of the low and high quadwords
6256 // of the result come from the same quadword of one of the two inputs. Undef
6257 // mask values count as coming from any quadword, for better codegen.
6258 unsigned LoQuad[] = { 0, 0, 0, 0 };
6259 unsigned HiQuad[] = { 0, 0, 0, 0 };
6260 std::bitset<4> InputQuads;
6261 for (unsigned i = 0; i < 8; ++i) {
6262 unsigned *Quad = i < 4 ? LoQuad : HiQuad;
6263 int EltIdx = SVOp->getMaskElt(i);
6264 MaskVals.push_back(EltIdx);
6273 InputQuads.set(EltIdx / 4);
6276 int BestLoQuad = -1;
6277 unsigned MaxQuad = 1;
6278 for (unsigned i = 0; i < 4; ++i) {
6279 if (LoQuad[i] > MaxQuad) {
6281 MaxQuad = LoQuad[i];
6285 int BestHiQuad = -1;
6287 for (unsigned i = 0; i < 4; ++i) {
6288 if (HiQuad[i] > MaxQuad) {
6290 MaxQuad = HiQuad[i];
6294 // For SSSE3, If all 8 words of the result come from only 1 quadword of each
6295 // of the two input vectors, shuffle them into one input vector so only a
6296 // single pshufb instruction is necessary. If There are more than 2 input
6297 // quads, disable the next transformation since it does not help SSSE3.
6298 bool V1Used = InputQuads[0] || InputQuads[1];
6299 bool V2Used = InputQuads[2] || InputQuads[3];
6300 if (Subtarget->hasSSSE3()) {
6301 if (InputQuads.count() == 2 && V1Used && V2Used) {
6302 BestLoQuad = InputQuads[0] ? 0 : 1;
6303 BestHiQuad = InputQuads[2] ? 2 : 3;
6305 if (InputQuads.count() > 2) {
6311 // If BestLoQuad or BestHiQuad are set, shuffle the quads together and update
6312 // the shuffle mask. If a quad is scored as -1, that means that it contains
6313 // words from all 4 input quadwords.
6315 if (BestLoQuad >= 0 || BestHiQuad >= 0) {
6317 BestLoQuad < 0 ? 0 : BestLoQuad,
6318 BestHiQuad < 0 ? 1 : BestHiQuad
6320 NewV = DAG.getVectorShuffle(MVT::v2i64, dl,
6321 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V1),
6322 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V2), &MaskV[0]);
6323 NewV = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, NewV);
6325 // Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the
6326 // source words for the shuffle, to aid later transformations.
6327 bool AllWordsInNewV = true;
6328 bool InOrder[2] = { true, true };
6329 for (unsigned i = 0; i != 8; ++i) {
6330 int idx = MaskVals[i];
6332 InOrder[i/4] = false;
6333 if (idx < 0 || (idx/4) == BestLoQuad || (idx/4) == BestHiQuad)
6335 AllWordsInNewV = false;
6339 bool pshuflw = AllWordsInNewV, pshufhw = AllWordsInNewV;
6340 if (AllWordsInNewV) {
6341 for (int i = 0; i != 8; ++i) {
6342 int idx = MaskVals[i];
6345 idx = MaskVals[i] = (idx / 4) == BestLoQuad ? (idx & 3) : (idx & 3) + 4;
6346 if ((idx != i) && idx < 4)
6348 if ((idx != i) && idx > 3)
6357 // If we've eliminated the use of V2, and the new mask is a pshuflw or
6358 // pshufhw, that's as cheap as it gets. Return the new shuffle.
6359 if ((pshufhw && InOrder[0]) || (pshuflw && InOrder[1])) {
6360 unsigned Opc = pshufhw ? X86ISD::PSHUFHW : X86ISD::PSHUFLW;
6361 unsigned TargetMask = 0;
6362 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV,
6363 DAG.getUNDEF(MVT::v8i16), &MaskVals[0]);
6364 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
6365 TargetMask = pshufhw ? getShufflePSHUFHWImmediate(SVOp):
6366 getShufflePSHUFLWImmediate(SVOp);
6367 V1 = NewV.getOperand(0);
6368 return getTargetShuffleNode(Opc, dl, MVT::v8i16, V1, TargetMask, DAG);
6372 // Promote splats to a larger type which usually leads to more efficient code.
6373 // FIXME: Is this true if pshufb is available?
6374 if (SVOp->isSplat())
6375 return PromoteSplat(SVOp, DAG);
6377 // If we have SSSE3, and all words of the result are from 1 input vector,
6378 // case 2 is generated, otherwise case 3 is generated. If no SSSE3
6379 // is present, fall back to case 4.
6380 if (Subtarget->hasSSSE3()) {
6381 SmallVector<SDValue,16> pshufbMask;
6383 // If we have elements from both input vectors, set the high bit of the
6384 // shuffle mask element to zero out elements that come from V2 in the V1
6385 // mask, and elements that come from V1 in the V2 mask, so that the two
6386 // results can be OR'd together.
6387 bool TwoInputs = V1Used && V2Used;
6388 for (unsigned i = 0; i != 8; ++i) {
6389 int EltIdx = MaskVals[i] * 2;
6390 int Idx0 = (TwoInputs && (EltIdx >= 16)) ? 0x80 : EltIdx;
6391 int Idx1 = (TwoInputs && (EltIdx >= 16)) ? 0x80 : EltIdx+1;
6392 pshufbMask.push_back(DAG.getConstant(Idx0, MVT::i8));
6393 pshufbMask.push_back(DAG.getConstant(Idx1, MVT::i8));
6395 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V1);
6396 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
6397 DAG.getNode(ISD::BUILD_VECTOR, dl,
6398 MVT::v16i8, &pshufbMask[0], 16));
6400 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
6402 // Calculate the shuffle mask for the second input, shuffle it, and
6403 // OR it with the first shuffled input.
6405 for (unsigned i = 0; i != 8; ++i) {
6406 int EltIdx = MaskVals[i] * 2;
6407 int Idx0 = (EltIdx < 16) ? 0x80 : EltIdx - 16;
6408 int Idx1 = (EltIdx < 16) ? 0x80 : EltIdx - 15;
6409 pshufbMask.push_back(DAG.getConstant(Idx0, MVT::i8));
6410 pshufbMask.push_back(DAG.getConstant(Idx1, MVT::i8));
6412 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V2);
6413 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
6414 DAG.getNode(ISD::BUILD_VECTOR, dl,
6415 MVT::v16i8, &pshufbMask[0], 16));
6416 V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
6417 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
6420 // If BestLoQuad >= 0, generate a pshuflw to put the low elements in order,
6421 // and update MaskVals with new element order.
6422 std::bitset<8> InOrder;
6423 if (BestLoQuad >= 0) {
6424 int MaskV[] = { -1, -1, -1, -1, 4, 5, 6, 7 };
6425 for (int i = 0; i != 4; ++i) {
6426 int idx = MaskVals[i];
6429 } else if ((idx / 4) == BestLoQuad) {
6434 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
6437 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSSE3()) {
6438 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
6439 NewV = getTargetShuffleNode(X86ISD::PSHUFLW, dl, MVT::v8i16,
6441 getShufflePSHUFLWImmediate(SVOp), DAG);
6445 // If BestHi >= 0, generate a pshufhw to put the high elements in order,
6446 // and update MaskVals with the new element order.
6447 if (BestHiQuad >= 0) {
6448 int MaskV[] = { 0, 1, 2, 3, -1, -1, -1, -1 };
6449 for (unsigned i = 4; i != 8; ++i) {
6450 int idx = MaskVals[i];
6453 } else if ((idx / 4) == BestHiQuad) {
6454 MaskV[i] = (idx & 3) + 4;
6458 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
6461 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSSE3()) {
6462 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
6463 NewV = getTargetShuffleNode(X86ISD::PSHUFHW, dl, MVT::v8i16,
6465 getShufflePSHUFHWImmediate(SVOp), DAG);
6469 // In case BestHi & BestLo were both -1, which means each quadword has a word
6470 // from each of the four input quadwords, calculate the InOrder bitvector now
6471 // before falling through to the insert/extract cleanup.
6472 if (BestLoQuad == -1 && BestHiQuad == -1) {
6474 for (int i = 0; i != 8; ++i)
6475 if (MaskVals[i] < 0 || MaskVals[i] == i)
6479 // The other elements are put in the right place using pextrw and pinsrw.
6480 for (unsigned i = 0; i != 8; ++i) {
6483 int EltIdx = MaskVals[i];
6486 SDValue ExtOp = (EltIdx < 8) ?
6487 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1,
6488 DAG.getIntPtrConstant(EltIdx)) :
6489 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2,
6490 DAG.getIntPtrConstant(EltIdx - 8));
6491 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp,
6492 DAG.getIntPtrConstant(i));
6497 // v16i8 shuffles - Prefer shuffles in the following order:
6498 // 1. [ssse3] 1 x pshufb
6499 // 2. [ssse3] 2 x pshufb + 1 x por
6500 // 3. [all] v8i16 shuffle + N x pextrw + rotate + pinsrw
6501 static SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp,
6502 const X86Subtarget* Subtarget,
6503 SelectionDAG &DAG) {
6504 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6505 SDValue V1 = SVOp->getOperand(0);
6506 SDValue V2 = SVOp->getOperand(1);
6508 ArrayRef<int> MaskVals = SVOp->getMask();
6510 // Promote splats to a larger type which usually leads to more efficient code.
6511 // FIXME: Is this true if pshufb is available?
6512 if (SVOp->isSplat())
6513 return PromoteSplat(SVOp, DAG);
6515 // If we have SSSE3, case 1 is generated when all result bytes come from
6516 // one of the inputs. Otherwise, case 2 is generated. If no SSSE3 is
6517 // present, fall back to case 3.
6519 // If SSSE3, use 1 pshufb instruction per vector with elements in the result.
6520 if (Subtarget->hasSSSE3()) {
6521 SmallVector<SDValue,16> pshufbMask;
6523 // If all result elements are from one input vector, then only translate
6524 // undef mask values to 0x80 (zero out result) in the pshufb mask.
6526 // Otherwise, we have elements from both input vectors, and must zero out
6527 // elements that come from V2 in the first mask, and V1 in the second mask
6528 // so that we can OR them together.
6529 for (unsigned i = 0; i != 16; ++i) {
6530 int EltIdx = MaskVals[i];
6531 if (EltIdx < 0 || EltIdx >= 16)
6533 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
6535 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
6536 DAG.getNode(ISD::BUILD_VECTOR, dl,
6537 MVT::v16i8, &pshufbMask[0], 16));
6539 // As PSHUFB will zero elements with negative indices, it's safe to ignore
6540 // the 2nd operand if it's undefined or zero.
6541 if (V2.getOpcode() == ISD::UNDEF ||
6542 ISD::isBuildVectorAllZeros(V2.getNode()))
6545 // Calculate the shuffle mask for the second input, shuffle it, and
6546 // OR it with the first shuffled input.
6548 for (unsigned i = 0; i != 16; ++i) {
6549 int EltIdx = MaskVals[i];
6550 EltIdx = (EltIdx < 16) ? 0x80 : EltIdx - 16;
6551 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
6553 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
6554 DAG.getNode(ISD::BUILD_VECTOR, dl,
6555 MVT::v16i8, &pshufbMask[0], 16));
6556 return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
6559 // No SSSE3 - Calculate in place words and then fix all out of place words
6560 // With 0-16 extracts & inserts. Worst case is 16 bytes out of order from
6561 // the 16 different words that comprise the two doublequadword input vectors.
6562 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
6563 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V2);
6565 for (int i = 0; i != 8; ++i) {
6566 int Elt0 = MaskVals[i*2];
6567 int Elt1 = MaskVals[i*2+1];
6569 // This word of the result is all undef, skip it.
6570 if (Elt0 < 0 && Elt1 < 0)
6573 // This word of the result is already in the correct place, skip it.
6574 if ((Elt0 == i*2) && (Elt1 == i*2+1))
6577 SDValue Elt0Src = Elt0 < 16 ? V1 : V2;
6578 SDValue Elt1Src = Elt1 < 16 ? V1 : V2;
6581 // If Elt0 and Elt1 are defined, are consecutive, and can be load
6582 // using a single extract together, load it and store it.
6583 if ((Elt0 >= 0) && ((Elt0 + 1) == Elt1) && ((Elt0 & 1) == 0)) {
6584 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
6585 DAG.getIntPtrConstant(Elt1 / 2));
6586 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
6587 DAG.getIntPtrConstant(i));
6591 // If Elt1 is defined, extract it from the appropriate source. If the
6592 // source byte is not also odd, shift the extracted word left 8 bits
6593 // otherwise clear the bottom 8 bits if we need to do an or.
6595 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
6596 DAG.getIntPtrConstant(Elt1 / 2));
6597 if ((Elt1 & 1) == 0)
6598 InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt,
6600 TLI.getShiftAmountTy(InsElt.getValueType())));
6602 InsElt = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt,
6603 DAG.getConstant(0xFF00, MVT::i16));
6605 // If Elt0 is defined, extract it from the appropriate source. If the
6606 // source byte is not also even, shift the extracted word right 8 bits. If
6607 // Elt1 was also defined, OR the extracted values together before
6608 // inserting them in the result.
6610 SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16,
6611 Elt0Src, DAG.getIntPtrConstant(Elt0 / 2));
6612 if ((Elt0 & 1) != 0)
6613 InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0,
6615 TLI.getShiftAmountTy(InsElt0.getValueType())));
6617 InsElt0 = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt0,
6618 DAG.getConstant(0x00FF, MVT::i16));
6619 InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0)
6622 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
6623 DAG.getIntPtrConstant(i));
6625 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, NewV);
6628 // v32i8 shuffles - Translate to VPSHUFB if possible.
6630 SDValue LowerVECTOR_SHUFFLEv32i8(ShuffleVectorSDNode *SVOp,
6631 const X86Subtarget *Subtarget,
6632 SelectionDAG &DAG) {
6633 MVT VT = SVOp->getSimpleValueType(0);
6634 SDValue V1 = SVOp->getOperand(0);
6635 SDValue V2 = SVOp->getOperand(1);
6637 SmallVector<int, 32> MaskVals(SVOp->getMask().begin(), SVOp->getMask().end());
6639 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
6640 bool V1IsAllZero = ISD::isBuildVectorAllZeros(V1.getNode());
6641 bool V2IsAllZero = ISD::isBuildVectorAllZeros(V2.getNode());
6643 // VPSHUFB may be generated if
6644 // (1) one of input vector is undefined or zeroinitializer.
6645 // The mask value 0x80 puts 0 in the corresponding slot of the vector.
6646 // And (2) the mask indexes don't cross the 128-bit lane.
6647 if (VT != MVT::v32i8 || !Subtarget->hasInt256() ||
6648 (!V2IsUndef && !V2IsAllZero && !V1IsAllZero))
6651 if (V1IsAllZero && !V2IsAllZero) {
6652 CommuteVectorShuffleMask(MaskVals, 32);
6655 SmallVector<SDValue, 32> pshufbMask;
6656 for (unsigned i = 0; i != 32; i++) {
6657 int EltIdx = MaskVals[i];
6658 if (EltIdx < 0 || EltIdx >= 32)
6661 if ((EltIdx >= 16 && i < 16) || (EltIdx < 16 && i >= 16))
6662 // Cross lane is not allowed.
6666 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
6668 return DAG.getNode(X86ISD::PSHUFB, dl, MVT::v32i8, V1,
6669 DAG.getNode(ISD::BUILD_VECTOR, dl,
6670 MVT::v32i8, &pshufbMask[0], 32));
6673 /// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide
6674 /// ones, or rewriting v4i32 / v4f32 as 2 wide ones if possible. This can be
6675 /// done when every pair / quad of shuffle mask elements point to elements in
6676 /// the right sequence. e.g.
6677 /// vector_shuffle X, Y, <2, 3, | 10, 11, | 0, 1, | 14, 15>
6679 SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp,
6680 SelectionDAG &DAG) {
6681 MVT VT = SVOp->getSimpleValueType(0);
6683 unsigned NumElems = VT.getVectorNumElements();
6686 switch (VT.SimpleTy) {
6687 default: llvm_unreachable("Unexpected!");
6688 case MVT::v4f32: NewVT = MVT::v2f64; Scale = 2; break;
6689 case MVT::v4i32: NewVT = MVT::v2i64; Scale = 2; break;
6690 case MVT::v8i16: NewVT = MVT::v4i32; Scale = 2; break;
6691 case MVT::v16i8: NewVT = MVT::v4i32; Scale = 4; break;
6692 case MVT::v16i16: NewVT = MVT::v8i32; Scale = 2; break;
6693 case MVT::v32i8: NewVT = MVT::v8i32; Scale = 4; break;
6696 SmallVector<int, 8> MaskVec;
6697 for (unsigned i = 0; i != NumElems; i += Scale) {
6699 for (unsigned j = 0; j != Scale; ++j) {
6700 int EltIdx = SVOp->getMaskElt(i+j);
6704 StartIdx = (EltIdx / Scale);
6705 if (EltIdx != (int)(StartIdx*Scale + j))
6708 MaskVec.push_back(StartIdx);
6711 SDValue V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(0));
6712 SDValue V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(1));
6713 return DAG.getVectorShuffle(NewVT, dl, V1, V2, &MaskVec[0]);
6716 /// getVZextMovL - Return a zero-extending vector move low node.
6718 static SDValue getVZextMovL(MVT VT, MVT OpVT,
6719 SDValue SrcOp, SelectionDAG &DAG,
6720 const X86Subtarget *Subtarget, SDLoc dl) {
6721 if (VT == MVT::v2f64 || VT == MVT::v4f32) {
6722 LoadSDNode *LD = NULL;
6723 if (!isScalarLoadToVector(SrcOp.getNode(), &LD))
6724 LD = dyn_cast<LoadSDNode>(SrcOp);
6726 // movssrr and movsdrr do not clear top bits. Try to use movd, movq
6728 MVT ExtVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32;
6729 if ((ExtVT != MVT::i64 || Subtarget->is64Bit()) &&
6730 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR &&
6731 SrcOp.getOperand(0).getOpcode() == ISD::BITCAST &&
6732 SrcOp.getOperand(0).getOperand(0).getValueType() == ExtVT) {
6734 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32;
6735 return DAG.getNode(ISD::BITCAST, dl, VT,
6736 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
6737 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
6745 return DAG.getNode(ISD::BITCAST, dl, VT,
6746 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
6747 DAG.getNode(ISD::BITCAST, dl,
6751 /// LowerVECTOR_SHUFFLE_256 - Handle all 256-bit wide vectors shuffles
6752 /// which could not be matched by any known target speficic shuffle
6754 LowerVECTOR_SHUFFLE_256(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
6756 SDValue NewOp = Compact8x32ShuffleNode(SVOp, DAG);
6757 if (NewOp.getNode())
6760 MVT VT = SVOp->getSimpleValueType(0);
6762 unsigned NumElems = VT.getVectorNumElements();
6763 unsigned NumLaneElems = NumElems / 2;
6766 MVT EltVT = VT.getVectorElementType();
6767 MVT NVT = MVT::getVectorVT(EltVT, NumLaneElems);
6770 SmallVector<int, 16> Mask;
6771 for (unsigned l = 0; l < 2; ++l) {
6772 // Build a shuffle mask for the output, discovering on the fly which
6773 // input vectors to use as shuffle operands (recorded in InputUsed).
6774 // If building a suitable shuffle vector proves too hard, then bail
6775 // out with UseBuildVector set.
6776 bool UseBuildVector = false;
6777 int InputUsed[2] = { -1, -1 }; // Not yet discovered.
6778 unsigned LaneStart = l * NumLaneElems;
6779 for (unsigned i = 0; i != NumLaneElems; ++i) {
6780 // The mask element. This indexes into the input.
6781 int Idx = SVOp->getMaskElt(i+LaneStart);
6783 // the mask element does not index into any input vector.
6788 // The input vector this mask element indexes into.
6789 int Input = Idx / NumLaneElems;
6791 // Turn the index into an offset from the start of the input vector.
6792 Idx -= Input * NumLaneElems;
6794 // Find or create a shuffle vector operand to hold this input.
6796 for (OpNo = 0; OpNo < array_lengthof(InputUsed); ++OpNo) {
6797 if (InputUsed[OpNo] == Input)
6798 // This input vector is already an operand.
6800 if (InputUsed[OpNo] < 0) {
6801 // Create a new operand for this input vector.
6802 InputUsed[OpNo] = Input;
6807 if (OpNo >= array_lengthof(InputUsed)) {
6808 // More than two input vectors used! Give up on trying to create a
6809 // shuffle vector. Insert all elements into a BUILD_VECTOR instead.
6810 UseBuildVector = true;
6814 // Add the mask index for the new shuffle vector.
6815 Mask.push_back(Idx + OpNo * NumLaneElems);
6818 if (UseBuildVector) {
6819 SmallVector<SDValue, 16> SVOps;
6820 for (unsigned i = 0; i != NumLaneElems; ++i) {
6821 // The mask element. This indexes into the input.
6822 int Idx = SVOp->getMaskElt(i+LaneStart);
6824 SVOps.push_back(DAG.getUNDEF(EltVT));
6828 // The input vector this mask element indexes into.
6829 int Input = Idx / NumElems;
6831 // Turn the index into an offset from the start of the input vector.
6832 Idx -= Input * NumElems;
6834 // Extract the vector element by hand.
6835 SVOps.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
6836 SVOp->getOperand(Input),
6837 DAG.getIntPtrConstant(Idx)));
6840 // Construct the output using a BUILD_VECTOR.
6841 Output[l] = DAG.getNode(ISD::BUILD_VECTOR, dl, NVT, &SVOps[0],
6843 } else if (InputUsed[0] < 0) {
6844 // No input vectors were used! The result is undefined.
6845 Output[l] = DAG.getUNDEF(NVT);
6847 SDValue Op0 = Extract128BitVector(SVOp->getOperand(InputUsed[0] / 2),
6848 (InputUsed[0] % 2) * NumLaneElems,
6850 // If only one input was used, use an undefined vector for the other.
6851 SDValue Op1 = (InputUsed[1] < 0) ? DAG.getUNDEF(NVT) :
6852 Extract128BitVector(SVOp->getOperand(InputUsed[1] / 2),
6853 (InputUsed[1] % 2) * NumLaneElems, DAG, dl);
6854 // At least one input vector was used. Create a new shuffle vector.
6855 Output[l] = DAG.getVectorShuffle(NVT, dl, Op0, Op1, &Mask[0]);
6861 // Concatenate the result back
6862 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, Output[0], Output[1]);
6865 /// LowerVECTOR_SHUFFLE_128v4 - Handle all 128-bit wide vectors with
6866 /// 4 elements, and match them with several different shuffle types.
6868 LowerVECTOR_SHUFFLE_128v4(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
6869 SDValue V1 = SVOp->getOperand(0);
6870 SDValue V2 = SVOp->getOperand(1);
6872 MVT VT = SVOp->getSimpleValueType(0);
6874 assert(VT.is128BitVector() && "Unsupported vector size");
6876 std::pair<int, int> Locs[4];
6877 int Mask1[] = { -1, -1, -1, -1 };
6878 SmallVector<int, 8> PermMask(SVOp->getMask().begin(), SVOp->getMask().end());
6882 for (unsigned i = 0; i != 4; ++i) {
6883 int Idx = PermMask[i];
6885 Locs[i] = std::make_pair(-1, -1);
6887 assert(Idx < 8 && "Invalid VECTOR_SHUFFLE index!");
6889 Locs[i] = std::make_pair(0, NumLo);
6893 Locs[i] = std::make_pair(1, NumHi);
6895 Mask1[2+NumHi] = Idx;
6901 if (NumLo <= 2 && NumHi <= 2) {
6902 // If no more than two elements come from either vector. This can be
6903 // implemented with two shuffles. First shuffle gather the elements.
6904 // The second shuffle, which takes the first shuffle as both of its
6905 // vector operands, put the elements into the right order.
6906 V1 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
6908 int Mask2[] = { -1, -1, -1, -1 };
6910 for (unsigned i = 0; i != 4; ++i)
6911 if (Locs[i].first != -1) {
6912 unsigned Idx = (i < 2) ? 0 : 4;
6913 Idx += Locs[i].first * 2 + Locs[i].second;
6917 return DAG.getVectorShuffle(VT, dl, V1, V1, &Mask2[0]);
6920 if (NumLo == 3 || NumHi == 3) {
6921 // Otherwise, we must have three elements from one vector, call it X, and
6922 // one element from the other, call it Y. First, use a shufps to build an
6923 // intermediate vector with the one element from Y and the element from X
6924 // that will be in the same half in the final destination (the indexes don't
6925 // matter). Then, use a shufps to build the final vector, taking the half
6926 // containing the element from Y from the intermediate, and the other half
6929 // Normalize it so the 3 elements come from V1.
6930 CommuteVectorShuffleMask(PermMask, 4);
6934 // Find the element from V2.
6936 for (HiIndex = 0; HiIndex < 3; ++HiIndex) {
6937 int Val = PermMask[HiIndex];
6944 Mask1[0] = PermMask[HiIndex];
6946 Mask1[2] = PermMask[HiIndex^1];
6948 V2 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
6951 Mask1[0] = PermMask[0];
6952 Mask1[1] = PermMask[1];
6953 Mask1[2] = HiIndex & 1 ? 6 : 4;
6954 Mask1[3] = HiIndex & 1 ? 4 : 6;
6955 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
6958 Mask1[0] = HiIndex & 1 ? 2 : 0;
6959 Mask1[1] = HiIndex & 1 ? 0 : 2;
6960 Mask1[2] = PermMask[2];
6961 Mask1[3] = PermMask[3];
6966 return DAG.getVectorShuffle(VT, dl, V2, V1, &Mask1[0]);
6969 // Break it into (shuffle shuffle_hi, shuffle_lo).
6970 int LoMask[] = { -1, -1, -1, -1 };
6971 int HiMask[] = { -1, -1, -1, -1 };
6973 int *MaskPtr = LoMask;
6974 unsigned MaskIdx = 0;
6977 for (unsigned i = 0; i != 4; ++i) {
6984 int Idx = PermMask[i];
6986 Locs[i] = std::make_pair(-1, -1);
6987 } else if (Idx < 4) {
6988 Locs[i] = std::make_pair(MaskIdx, LoIdx);
6989 MaskPtr[LoIdx] = Idx;
6992 Locs[i] = std::make_pair(MaskIdx, HiIdx);
6993 MaskPtr[HiIdx] = Idx;
6998 SDValue LoShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &LoMask[0]);
6999 SDValue HiShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &HiMask[0]);
7000 int MaskOps[] = { -1, -1, -1, -1 };
7001 for (unsigned i = 0; i != 4; ++i)
7002 if (Locs[i].first != -1)
7003 MaskOps[i] = Locs[i].first * 4 + Locs[i].second;
7004 return DAG.getVectorShuffle(VT, dl, LoShuffle, HiShuffle, &MaskOps[0]);
7007 static bool MayFoldVectorLoad(SDValue V) {
7008 while (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
7009 V = V.getOperand(0);
7011 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR)
7012 V = V.getOperand(0);
7013 if (V.hasOneUse() && V.getOpcode() == ISD::BUILD_VECTOR &&
7014 V.getNumOperands() == 2 && V.getOperand(1).getOpcode() == ISD::UNDEF)
7015 // BUILD_VECTOR (load), undef
7016 V = V.getOperand(0);
7018 return MayFoldLoad(V);
7022 SDValue getMOVDDup(SDValue &Op, SDLoc &dl, SDValue V1, SelectionDAG &DAG) {
7023 MVT VT = Op.getSimpleValueType();
7025 // Canonizalize to v2f64.
7026 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, V1);
7027 return DAG.getNode(ISD::BITCAST, dl, VT,
7028 getTargetShuffleNode(X86ISD::MOVDDUP, dl, MVT::v2f64,
7033 SDValue getMOVLowToHigh(SDValue &Op, SDLoc &dl, SelectionDAG &DAG,
7035 SDValue V1 = Op.getOperand(0);
7036 SDValue V2 = Op.getOperand(1);
7037 MVT VT = Op.getSimpleValueType();
7039 assert(VT != MVT::v2i64 && "unsupported shuffle type");
7041 if (HasSSE2 && VT == MVT::v2f64)
7042 return getTargetShuffleNode(X86ISD::MOVLHPD, dl, VT, V1, V2, DAG);
7044 // v4f32 or v4i32: canonizalized to v4f32 (which is legal for SSE1)
7045 return DAG.getNode(ISD::BITCAST, dl, VT,
7046 getTargetShuffleNode(X86ISD::MOVLHPS, dl, MVT::v4f32,
7047 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V1),
7048 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V2), DAG));
7052 SDValue getMOVHighToLow(SDValue &Op, SDLoc &dl, SelectionDAG &DAG) {
7053 SDValue V1 = Op.getOperand(0);
7054 SDValue V2 = Op.getOperand(1);
7055 MVT VT = Op.getSimpleValueType();
7057 assert((VT == MVT::v4i32 || VT == MVT::v4f32) &&
7058 "unsupported shuffle type");
7060 if (V2.getOpcode() == ISD::UNDEF)
7064 return getTargetShuffleNode(X86ISD::MOVHLPS, dl, VT, V1, V2, DAG);
7068 SDValue getMOVLP(SDValue &Op, SDLoc &dl, SelectionDAG &DAG, bool HasSSE2) {
7069 SDValue V1 = Op.getOperand(0);
7070 SDValue V2 = Op.getOperand(1);
7071 MVT VT = Op.getSimpleValueType();
7072 unsigned NumElems = VT.getVectorNumElements();
7074 // Use MOVLPS and MOVLPD in case V1 or V2 are loads. During isel, the second
7075 // operand of these instructions is only memory, so check if there's a
7076 // potencial load folding here, otherwise use SHUFPS or MOVSD to match the
7078 bool CanFoldLoad = false;
7080 // Trivial case, when V2 comes from a load.
7081 if (MayFoldVectorLoad(V2))
7084 // When V1 is a load, it can be folded later into a store in isel, example:
7085 // (store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)), addr:$src1)
7087 // (MOVLPSmr addr:$src1, VR128:$src2)
7088 // So, recognize this potential and also use MOVLPS or MOVLPD
7089 else if (MayFoldVectorLoad(V1) && MayFoldIntoStore(Op))
7092 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7094 if (HasSSE2 && NumElems == 2)
7095 return getTargetShuffleNode(X86ISD::MOVLPD, dl, VT, V1, V2, DAG);
7098 // If we don't care about the second element, proceed to use movss.
7099 if (SVOp->getMaskElt(1) != -1)
7100 return getTargetShuffleNode(X86ISD::MOVLPS, dl, VT, V1, V2, DAG);
7103 // movl and movlp will both match v2i64, but v2i64 is never matched by
7104 // movl earlier because we make it strict to avoid messing with the movlp load
7105 // folding logic (see the code above getMOVLP call). Match it here then,
7106 // this is horrible, but will stay like this until we move all shuffle
7107 // matching to x86 specific nodes. Note that for the 1st condition all
7108 // types are matched with movsd.
7110 // FIXME: isMOVLMask should be checked and matched before getMOVLP,
7111 // as to remove this logic from here, as much as possible
7112 if (NumElems == 2 || !isMOVLMask(SVOp->getMask(), VT))
7113 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
7114 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
7117 assert(VT != MVT::v4i32 && "unsupported shuffle type");
7119 // Invert the operand order and use SHUFPS to match it.
7120 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V2, V1,
7121 getShuffleSHUFImmediate(SVOp), DAG);
7124 // Reduce a vector shuffle to zext.
7125 static SDValue LowerVectorIntExtend(SDValue Op, const X86Subtarget *Subtarget,
7126 SelectionDAG &DAG) {
7127 // PMOVZX is only available from SSE41.
7128 if (!Subtarget->hasSSE41())
7131 MVT VT = Op.getSimpleValueType();
7133 // Only AVX2 support 256-bit vector integer extending.
7134 if (!Subtarget->hasInt256() && VT.is256BitVector())
7137 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7139 SDValue V1 = Op.getOperand(0);
7140 SDValue V2 = Op.getOperand(1);
7141 unsigned NumElems = VT.getVectorNumElements();
7143 // Extending is an unary operation and the element type of the source vector
7144 // won't be equal to or larger than i64.
7145 if (V2.getOpcode() != ISD::UNDEF || !VT.isInteger() ||
7146 VT.getVectorElementType() == MVT::i64)
7149 // Find the expansion ratio, e.g. expanding from i8 to i32 has a ratio of 4.
7150 unsigned Shift = 1; // Start from 2, i.e. 1 << 1.
7151 while ((1U << Shift) < NumElems) {
7152 if (SVOp->getMaskElt(1U << Shift) == 1)
7155 // The maximal ratio is 8, i.e. from i8 to i64.
7160 // Check the shuffle mask.
7161 unsigned Mask = (1U << Shift) - 1;
7162 for (unsigned i = 0; i != NumElems; ++i) {
7163 int EltIdx = SVOp->getMaskElt(i);
7164 if ((i & Mask) != 0 && EltIdx != -1)
7166 if ((i & Mask) == 0 && (unsigned)EltIdx != (i >> Shift))
7170 unsigned NBits = VT.getVectorElementType().getSizeInBits() << Shift;
7171 MVT NeVT = MVT::getIntegerVT(NBits);
7172 MVT NVT = MVT::getVectorVT(NeVT, NumElems >> Shift);
7174 if (!DAG.getTargetLoweringInfo().isTypeLegal(NVT))
7177 // Simplify the operand as it's prepared to be fed into shuffle.
7178 unsigned SignificantBits = NVT.getSizeInBits() >> Shift;
7179 if (V1.getOpcode() == ISD::BITCAST &&
7180 V1.getOperand(0).getOpcode() == ISD::SCALAR_TO_VECTOR &&
7181 V1.getOperand(0).getOperand(0).getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
7182 V1.getOperand(0).getOperand(0)
7183 .getSimpleValueType().getSizeInBits() == SignificantBits) {
7184 // (bitcast (sclr2vec (ext_vec_elt x))) -> (bitcast x)
7185 SDValue V = V1.getOperand(0).getOperand(0).getOperand(0);
7186 ConstantSDNode *CIdx =
7187 dyn_cast<ConstantSDNode>(V1.getOperand(0).getOperand(0).getOperand(1));
7188 // If it's foldable, i.e. normal load with single use, we will let code
7189 // selection to fold it. Otherwise, we will short the conversion sequence.
7190 if (CIdx && CIdx->getZExtValue() == 0 &&
7191 (!ISD::isNormalLoad(V.getNode()) || !V.hasOneUse())) {
7192 MVT FullVT = V.getSimpleValueType();
7193 MVT V1VT = V1.getSimpleValueType();
7194 if (FullVT.getSizeInBits() > V1VT.getSizeInBits()) {
7195 // The "ext_vec_elt" node is wider than the result node.
7196 // In this case we should extract subvector from V.
7197 // (bitcast (sclr2vec (ext_vec_elt x))) -> (bitcast (extract_subvector x)).
7198 unsigned Ratio = FullVT.getSizeInBits() / V1VT.getSizeInBits();
7199 MVT SubVecVT = MVT::getVectorVT(FullVT.getVectorElementType(),
7200 FullVT.getVectorNumElements()/Ratio);
7201 V = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVecVT, V,
7202 DAG.getIntPtrConstant(0));
7204 V1 = DAG.getNode(ISD::BITCAST, DL, V1VT, V);
7208 return DAG.getNode(ISD::BITCAST, DL, VT,
7209 DAG.getNode(X86ISD::VZEXT, DL, NVT, V1));
7213 NormalizeVectorShuffle(SDValue Op, const X86Subtarget *Subtarget,
7214 SelectionDAG &DAG) {
7215 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7216 MVT VT = Op.getSimpleValueType();
7218 SDValue V1 = Op.getOperand(0);
7219 SDValue V2 = Op.getOperand(1);
7221 if (isZeroShuffle(SVOp))
7222 return getZeroVector(VT, Subtarget, DAG, dl);
7224 // Handle splat operations
7225 if (SVOp->isSplat()) {
7226 // Use vbroadcast whenever the splat comes from a foldable load
7227 SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG);
7228 if (Broadcast.getNode())
7232 // Check integer expanding shuffles.
7233 SDValue NewOp = LowerVectorIntExtend(Op, Subtarget, DAG);
7234 if (NewOp.getNode())
7237 // If the shuffle can be profitably rewritten as a narrower shuffle, then
7239 if (VT == MVT::v8i16 || VT == MVT::v16i8 ||
7240 VT == MVT::v16i16 || VT == MVT::v32i8) {
7241 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
7242 if (NewOp.getNode())
7243 return DAG.getNode(ISD::BITCAST, dl, VT, NewOp);
7244 } else if ((VT == MVT::v4i32 ||
7245 (VT == MVT::v4f32 && Subtarget->hasSSE2()))) {
7246 // FIXME: Figure out a cleaner way to do this.
7247 // Try to make use of movq to zero out the top part.
7248 if (ISD::isBuildVectorAllZeros(V2.getNode())) {
7249 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
7250 if (NewOp.getNode()) {
7251 MVT NewVT = NewOp.getSimpleValueType();
7252 if (isCommutedMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(),
7253 NewVT, true, false))
7254 return getVZextMovL(VT, NewVT, NewOp.getOperand(0),
7255 DAG, Subtarget, dl);
7257 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) {
7258 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
7259 if (NewOp.getNode()) {
7260 MVT NewVT = NewOp.getSimpleValueType();
7261 if (isMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(), NewVT))
7262 return getVZextMovL(VT, NewVT, NewOp.getOperand(1),
7263 DAG, Subtarget, dl);
7271 X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const {
7272 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7273 SDValue V1 = Op.getOperand(0);
7274 SDValue V2 = Op.getOperand(1);
7275 MVT VT = Op.getSimpleValueType();
7277 unsigned NumElems = VT.getVectorNumElements();
7278 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
7279 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
7280 bool V1IsSplat = false;
7281 bool V2IsSplat = false;
7282 bool HasSSE2 = Subtarget->hasSSE2();
7283 bool HasFp256 = Subtarget->hasFp256();
7284 bool HasInt256 = Subtarget->hasInt256();
7285 MachineFunction &MF = DAG.getMachineFunction();
7286 bool OptForSize = MF.getFunction()->getAttributes().
7287 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
7289 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
7291 if (V1IsUndef && V2IsUndef)
7292 return DAG.getUNDEF(VT);
7294 assert(!V1IsUndef && "Op 1 of shuffle should not be undef");
7296 // Vector shuffle lowering takes 3 steps:
7298 // 1) Normalize the input vectors. Here splats, zeroed vectors, profitable
7299 // narrowing and commutation of operands should be handled.
7300 // 2) Matching of shuffles with known shuffle masks to x86 target specific
7302 // 3) Rewriting of unmatched masks into new generic shuffle operations,
7303 // so the shuffle can be broken into other shuffles and the legalizer can
7304 // try the lowering again.
7306 // The general idea is that no vector_shuffle operation should be left to
7307 // be matched during isel, all of them must be converted to a target specific
7310 // Normalize the input vectors. Here splats, zeroed vectors, profitable
7311 // narrowing and commutation of operands should be handled. The actual code
7312 // doesn't include all of those, work in progress...
7313 SDValue NewOp = NormalizeVectorShuffle(Op, Subtarget, DAG);
7314 if (NewOp.getNode())
7317 SmallVector<int, 8> M(SVOp->getMask().begin(), SVOp->getMask().end());
7319 // NOTE: isPSHUFDMask can also match both masks below (unpckl_undef and
7320 // unpckh_undef). Only use pshufd if speed is more important than size.
7321 if (OptForSize && isUNPCKL_v_undef_Mask(M, VT, HasInt256))
7322 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
7323 if (OptForSize && isUNPCKH_v_undef_Mask(M, VT, HasInt256))
7324 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
7326 if (isMOVDDUPMask(M, VT) && Subtarget->hasSSE3() &&
7327 V2IsUndef && MayFoldVectorLoad(V1))
7328 return getMOVDDup(Op, dl, V1, DAG);
7330 if (isMOVHLPS_v_undef_Mask(M, VT))
7331 return getMOVHighToLow(Op, dl, DAG);
7333 // Use to match splats
7334 if (HasSSE2 && isUNPCKHMask(M, VT, HasInt256) && V2IsUndef &&
7335 (VT == MVT::v2f64 || VT == MVT::v2i64))
7336 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
7338 if (isPSHUFDMask(M, VT)) {
7339 // The actual implementation will match the mask in the if above and then
7340 // during isel it can match several different instructions, not only pshufd
7341 // as its name says, sad but true, emulate the behavior for now...
7342 if (isMOVDDUPMask(M, VT) && ((VT == MVT::v4f32 || VT == MVT::v2i64)))
7343 return getTargetShuffleNode(X86ISD::MOVLHPS, dl, VT, V1, V1, DAG);
7345 unsigned TargetMask = getShuffleSHUFImmediate(SVOp);
7347 if (HasSSE2 && (VT == MVT::v4f32 || VT == MVT::v4i32))
7348 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1, TargetMask, DAG);
7350 if (HasFp256 && (VT == MVT::v4f32 || VT == MVT::v2f64))
7351 return getTargetShuffleNode(X86ISD::VPERMILP, dl, VT, V1, TargetMask,
7354 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V1,
7358 if (isPALIGNRMask(M, VT, Subtarget))
7359 return getTargetShuffleNode(X86ISD::PALIGNR, dl, VT, V1, V2,
7360 getShufflePALIGNRImmediate(SVOp),
7363 // Check if this can be converted into a logical shift.
7364 bool isLeft = false;
7367 bool isShift = HasSSE2 && isVectorShift(SVOp, DAG, isLeft, ShVal, ShAmt);
7368 if (isShift && ShVal.hasOneUse()) {
7369 // If the shifted value has multiple uses, it may be cheaper to use
7370 // v_set0 + movlhps or movhlps, etc.
7371 MVT EltVT = VT.getVectorElementType();
7372 ShAmt *= EltVT.getSizeInBits();
7373 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
7376 if (isMOVLMask(M, VT)) {
7377 if (ISD::isBuildVectorAllZeros(V1.getNode()))
7378 return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl);
7379 if (!isMOVLPMask(M, VT)) {
7380 if (HasSSE2 && (VT == MVT::v2i64 || VT == MVT::v2f64))
7381 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
7383 if (VT == MVT::v4i32 || VT == MVT::v4f32)
7384 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
7388 // FIXME: fold these into legal mask.
7389 if (isMOVLHPSMask(M, VT) && !isUNPCKLMask(M, VT, HasInt256))
7390 return getMOVLowToHigh(Op, dl, DAG, HasSSE2);
7392 if (isMOVHLPSMask(M, VT))
7393 return getMOVHighToLow(Op, dl, DAG);
7395 if (V2IsUndef && isMOVSHDUPMask(M, VT, Subtarget))
7396 return getTargetShuffleNode(X86ISD::MOVSHDUP, dl, VT, V1, DAG);
7398 if (V2IsUndef && isMOVSLDUPMask(M, VT, Subtarget))
7399 return getTargetShuffleNode(X86ISD::MOVSLDUP, dl, VT, V1, DAG);
7401 if (isMOVLPMask(M, VT))
7402 return getMOVLP(Op, dl, DAG, HasSSE2);
7404 if (ShouldXformToMOVHLPS(M, VT) ||
7405 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), M, VT))
7406 return CommuteVectorShuffle(SVOp, DAG);
7409 // No better options. Use a vshldq / vsrldq.
7410 MVT EltVT = VT.getVectorElementType();
7411 ShAmt *= EltVT.getSizeInBits();
7412 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
7415 bool Commuted = false;
7416 // FIXME: This should also accept a bitcast of a splat? Be careful, not
7417 // 1,1,1,1 -> v8i16 though.
7418 V1IsSplat = isSplatVector(V1.getNode());
7419 V2IsSplat = isSplatVector(V2.getNode());
7421 // Canonicalize the splat or undef, if present, to be on the RHS.
7422 if (!V2IsUndef && V1IsSplat && !V2IsSplat) {
7423 CommuteVectorShuffleMask(M, NumElems);
7425 std::swap(V1IsSplat, V2IsSplat);
7429 if (isCommutedMOVLMask(M, VT, V2IsSplat, V2IsUndef)) {
7430 // Shuffling low element of v1 into undef, just return v1.
7433 // If V2 is a splat, the mask may be malformed such as <4,3,3,3>, which
7434 // the instruction selector will not match, so get a canonical MOVL with
7435 // swapped operands to undo the commute.
7436 return getMOVL(DAG, dl, VT, V2, V1);
7439 if (isUNPCKLMask(M, VT, HasInt256))
7440 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
7442 if (isUNPCKHMask(M, VT, HasInt256))
7443 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
7446 // Normalize mask so all entries that point to V2 points to its first
7447 // element then try to match unpck{h|l} again. If match, return a
7448 // new vector_shuffle with the corrected mask.p
7449 SmallVector<int, 8> NewMask(M.begin(), M.end());
7450 NormalizeMask(NewMask, NumElems);
7451 if (isUNPCKLMask(NewMask, VT, HasInt256, true))
7452 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
7453 if (isUNPCKHMask(NewMask, VT, HasInt256, true))
7454 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
7458 // Commute is back and try unpck* again.
7459 // FIXME: this seems wrong.
7460 CommuteVectorShuffleMask(M, NumElems);
7462 std::swap(V1IsSplat, V2IsSplat);
7465 if (isUNPCKLMask(M, VT, HasInt256))
7466 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
7468 if (isUNPCKHMask(M, VT, HasInt256))
7469 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
7472 // Normalize the node to match x86 shuffle ops if needed
7473 if (!V2IsUndef && (isSHUFPMask(M, VT, /* Commuted */ true)))
7474 return CommuteVectorShuffle(SVOp, DAG);
7476 // The checks below are all present in isShuffleMaskLegal, but they are
7477 // inlined here right now to enable us to directly emit target specific
7478 // nodes, and remove one by one until they don't return Op anymore.
7480 if (ShuffleVectorSDNode::isSplatMask(&M[0], VT) &&
7481 SVOp->getSplatIndex() == 0 && V2IsUndef) {
7482 if (VT == MVT::v2f64 || VT == MVT::v2i64)
7483 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
7486 if (isPSHUFHWMask(M, VT, HasInt256))
7487 return getTargetShuffleNode(X86ISD::PSHUFHW, dl, VT, V1,
7488 getShufflePSHUFHWImmediate(SVOp),
7491 if (isPSHUFLWMask(M, VT, HasInt256))
7492 return getTargetShuffleNode(X86ISD::PSHUFLW, dl, VT, V1,
7493 getShufflePSHUFLWImmediate(SVOp),
7496 if (isSHUFPMask(M, VT))
7497 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V2,
7498 getShuffleSHUFImmediate(SVOp), DAG);
7500 if (isUNPCKL_v_undef_Mask(M, VT, HasInt256))
7501 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
7502 if (isUNPCKH_v_undef_Mask(M, VT, HasInt256))
7503 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
7505 //===--------------------------------------------------------------------===//
7506 // Generate target specific nodes for 128 or 256-bit shuffles only
7507 // supported in the AVX instruction set.
7510 // Handle VMOVDDUPY permutations
7511 if (V2IsUndef && isMOVDDUPYMask(M, VT, HasFp256))
7512 return getTargetShuffleNode(X86ISD::MOVDDUP, dl, VT, V1, DAG);
7514 // Handle VPERMILPS/D* permutations
7515 if (isVPERMILPMask(M, VT)) {
7516 if ((HasInt256 && VT == MVT::v8i32) || VT == MVT::v16i32)
7517 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1,
7518 getShuffleSHUFImmediate(SVOp), DAG);
7519 return getTargetShuffleNode(X86ISD::VPERMILP, dl, VT, V1,
7520 getShuffleSHUFImmediate(SVOp), DAG);
7523 // Handle VPERM2F128/VPERM2I128 permutations
7524 if (isVPERM2X128Mask(M, VT, HasFp256))
7525 return getTargetShuffleNode(X86ISD::VPERM2X128, dl, VT, V1,
7526 V2, getShuffleVPERM2X128Immediate(SVOp), DAG);
7528 SDValue BlendOp = LowerVECTOR_SHUFFLEtoBlend(SVOp, Subtarget, DAG);
7529 if (BlendOp.getNode())
7533 if (V2IsUndef && HasInt256 && isPermImmMask(M, VT, Imm8))
7534 return getTargetShuffleNode(X86ISD::VPERMI, dl, VT, V1, Imm8, DAG);
7536 if ((V2IsUndef && HasInt256 && VT.is256BitVector() && NumElems == 8) ||
7537 VT.is512BitVector()) {
7538 MVT MaskEltVT = MVT::getIntegerVT(VT.getVectorElementType().getSizeInBits());
7539 MVT MaskVectorVT = MVT::getVectorVT(MaskEltVT, NumElems);
7540 SmallVector<SDValue, 16> permclMask;
7541 for (unsigned i = 0; i != NumElems; ++i) {
7542 permclMask.push_back(DAG.getConstant((M[i]>=0) ? M[i] : 0, MaskEltVT));
7545 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVectorVT,
7546 &permclMask[0], NumElems);
7548 // Bitcast is for VPERMPS since mask is v8i32 but node takes v8f32
7549 return DAG.getNode(X86ISD::VPERMV, dl, VT,
7550 DAG.getNode(ISD::BITCAST, dl, VT, Mask), V1);
7551 return DAG.getNode(X86ISD::VPERMV3, dl, VT,
7552 DAG.getNode(ISD::BITCAST, dl, VT, Mask), V1, V2);
7555 //===--------------------------------------------------------------------===//
7556 // Since no target specific shuffle was selected for this generic one,
7557 // lower it into other known shuffles. FIXME: this isn't true yet, but
7558 // this is the plan.
7561 // Handle v8i16 specifically since SSE can do byte extraction and insertion.
7562 if (VT == MVT::v8i16) {
7563 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(Op, Subtarget, DAG);
7564 if (NewOp.getNode())
7568 if (VT == MVT::v16i8) {
7569 SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(SVOp, Subtarget, DAG);
7570 if (NewOp.getNode())
7574 if (VT == MVT::v32i8) {
7575 SDValue NewOp = LowerVECTOR_SHUFFLEv32i8(SVOp, Subtarget, DAG);
7576 if (NewOp.getNode())
7580 // Handle all 128-bit wide vectors with 4 elements, and match them with
7581 // several different shuffle types.
7582 if (NumElems == 4 && VT.is128BitVector())
7583 return LowerVECTOR_SHUFFLE_128v4(SVOp, DAG);
7585 // Handle general 256-bit shuffles
7586 if (VT.is256BitVector())
7587 return LowerVECTOR_SHUFFLE_256(SVOp, DAG);
7592 static SDValue LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) {
7593 MVT VT = Op.getSimpleValueType();
7596 if (!Op.getOperand(0).getSimpleValueType().is128BitVector())
7599 if (VT.getSizeInBits() == 8) {
7600 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
7601 Op.getOperand(0), Op.getOperand(1));
7602 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
7603 DAG.getValueType(VT));
7604 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
7607 if (VT.getSizeInBits() == 16) {
7608 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
7609 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
7611 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
7612 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
7613 DAG.getNode(ISD::BITCAST, dl,
7617 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
7618 Op.getOperand(0), Op.getOperand(1));
7619 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
7620 DAG.getValueType(VT));
7621 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
7624 if (VT == MVT::f32) {
7625 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
7626 // the result back to FR32 register. It's only worth matching if the
7627 // result has a single use which is a store or a bitcast to i32. And in
7628 // the case of a store, it's not worth it if the index is a constant 0,
7629 // because a MOVSSmr can be used instead, which is smaller and faster.
7630 if (!Op.hasOneUse())
7632 SDNode *User = *Op.getNode()->use_begin();
7633 if ((User->getOpcode() != ISD::STORE ||
7634 (isa<ConstantSDNode>(Op.getOperand(1)) &&
7635 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
7636 (User->getOpcode() != ISD::BITCAST ||
7637 User->getValueType(0) != MVT::i32))
7639 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
7640 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32,
7643 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, Extract);
7646 if (VT == MVT::i32 || VT == MVT::i64) {
7647 // ExtractPS/pextrq works with constant index.
7648 if (isa<ConstantSDNode>(Op.getOperand(1)))
7655 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
7656 SelectionDAG &DAG) const {
7658 SDValue Vec = Op.getOperand(0);
7659 MVT VecVT = Vec.getSimpleValueType();
7660 SDValue Idx = Op.getOperand(1);
7661 if (!isa<ConstantSDNode>(Idx)) {
7662 if (VecVT.is512BitVector() ||
7663 (VecVT.is256BitVector() && Subtarget->hasInt256() &&
7664 VecVT.getVectorElementType().getSizeInBits() == 32)) {
7667 MVT::getIntegerVT(VecVT.getVectorElementType().getSizeInBits());
7668 MVT MaskVT = MVT::getVectorVT(MaskEltVT, VecVT.getSizeInBits() /
7669 MaskEltVT.getSizeInBits());
7671 Idx = DAG.getZExtOrTrunc(Idx, dl, MaskEltVT);
7672 SDValue Mask = DAG.getNode(X86ISD::VINSERT, dl, MaskVT,
7673 getZeroVector(MaskVT, Subtarget, DAG, dl),
7674 Idx, DAG.getConstant(0, getPointerTy()));
7675 SDValue Perm = DAG.getNode(X86ISD::VPERMV, dl, VecVT, Mask, Vec);
7676 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(),
7677 Perm, DAG.getConstant(0, getPointerTy()));
7682 // If this is a 256-bit vector result, first extract the 128-bit vector and
7683 // then extract the element from the 128-bit vector.
7684 if (VecVT.is256BitVector() || VecVT.is512BitVector()) {
7686 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
7687 // Get the 128-bit vector.
7688 Vec = Extract128BitVector(Vec, IdxVal, DAG, dl);
7689 MVT EltVT = VecVT.getVectorElementType();
7691 unsigned ElemsPerChunk = 128 / EltVT.getSizeInBits();
7693 //if (IdxVal >= NumElems/2)
7694 // IdxVal -= NumElems/2;
7695 IdxVal -= (IdxVal/ElemsPerChunk)*ElemsPerChunk;
7696 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec,
7697 DAG.getConstant(IdxVal, MVT::i32));
7700 assert(VecVT.is128BitVector() && "Unexpected vector length");
7702 if (Subtarget->hasSSE41()) {
7703 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG);
7708 MVT VT = Op.getSimpleValueType();
7709 // TODO: handle v16i8.
7710 if (VT.getSizeInBits() == 16) {
7711 SDValue Vec = Op.getOperand(0);
7712 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
7714 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
7715 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
7716 DAG.getNode(ISD::BITCAST, dl,
7719 // Transform it so it match pextrw which produces a 32-bit result.
7720 MVT EltVT = MVT::i32;
7721 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
7722 Op.getOperand(0), Op.getOperand(1));
7723 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
7724 DAG.getValueType(VT));
7725 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
7728 if (VT.getSizeInBits() == 32) {
7729 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
7733 // SHUFPS the element to the lowest double word, then movss.
7734 int Mask[4] = { static_cast<int>(Idx), -1, -1, -1 };
7735 MVT VVT = Op.getOperand(0).getSimpleValueType();
7736 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
7737 DAG.getUNDEF(VVT), Mask);
7738 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
7739 DAG.getIntPtrConstant(0));
7742 if (VT.getSizeInBits() == 64) {
7743 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
7744 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
7745 // to match extract_elt for f64.
7746 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
7750 // UNPCKHPD the element to the lowest double word, then movsd.
7751 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
7752 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
7753 int Mask[2] = { 1, -1 };
7754 MVT VVT = Op.getOperand(0).getSimpleValueType();
7755 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
7756 DAG.getUNDEF(VVT), Mask);
7757 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
7758 DAG.getIntPtrConstant(0));
7764 static SDValue LowerINSERT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) {
7765 MVT VT = Op.getSimpleValueType();
7766 MVT EltVT = VT.getVectorElementType();
7769 SDValue N0 = Op.getOperand(0);
7770 SDValue N1 = Op.getOperand(1);
7771 SDValue N2 = Op.getOperand(2);
7773 if (!VT.is128BitVector())
7776 if ((EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) &&
7777 isa<ConstantSDNode>(N2)) {
7779 if (VT == MVT::v8i16)
7780 Opc = X86ISD::PINSRW;
7781 else if (VT == MVT::v16i8)
7782 Opc = X86ISD::PINSRB;
7784 Opc = X86ISD::PINSRB;
7786 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
7788 if (N1.getValueType() != MVT::i32)
7789 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
7790 if (N2.getValueType() != MVT::i32)
7791 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
7792 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
7795 if (EltVT == MVT::f32 && isa<ConstantSDNode>(N2)) {
7796 // Bits [7:6] of the constant are the source select. This will always be
7797 // zero here. The DAG Combiner may combine an extract_elt index into these
7798 // bits. For example (insert (extract, 3), 2) could be matched by putting
7799 // the '3' into bits [7:6] of X86ISD::INSERTPS.
7800 // Bits [5:4] of the constant are the destination select. This is the
7801 // value of the incoming immediate.
7802 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
7803 // combine either bitwise AND or insert of float 0.0 to set these bits.
7804 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue() << 4);
7805 // Create this as a scalar to vector..
7806 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
7807 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
7810 if ((EltVT == MVT::i32 || EltVT == MVT::i64) && isa<ConstantSDNode>(N2)) {
7811 // PINSR* works with constant index.
7818 X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const {
7819 MVT VT = Op.getSimpleValueType();
7820 MVT EltVT = VT.getVectorElementType();
7823 SDValue N0 = Op.getOperand(0);
7824 SDValue N1 = Op.getOperand(1);
7825 SDValue N2 = Op.getOperand(2);
7827 // If this is a 256-bit vector result, first extract the 128-bit vector,
7828 // insert the element into the extracted half and then place it back.
7829 if (VT.is256BitVector() || VT.is512BitVector()) {
7830 if (!isa<ConstantSDNode>(N2))
7833 // Get the desired 128-bit vector half.
7834 unsigned IdxVal = cast<ConstantSDNode>(N2)->getZExtValue();
7835 SDValue V = Extract128BitVector(N0, IdxVal, DAG, dl);
7837 // Insert the element into the desired half.
7838 unsigned NumEltsIn128 = 128/EltVT.getSizeInBits();
7839 unsigned IdxIn128 = IdxVal - (IdxVal/NumEltsIn128) * NumEltsIn128;
7841 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V, N1,
7842 DAG.getConstant(IdxIn128, MVT::i32));
7844 // Insert the changed part back to the 256-bit vector
7845 return Insert128BitVector(N0, V, IdxVal, DAG, dl);
7848 if (Subtarget->hasSSE41())
7849 return LowerINSERT_VECTOR_ELT_SSE4(Op, DAG);
7851 if (EltVT == MVT::i8)
7854 if (EltVT.getSizeInBits() == 16 && isa<ConstantSDNode>(N2)) {
7855 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
7856 // as its second argument.
7857 if (N1.getValueType() != MVT::i32)
7858 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
7859 if (N2.getValueType() != MVT::i32)
7860 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
7861 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);
7866 static SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) {
7868 MVT OpVT = Op.getSimpleValueType();
7870 // If this is a 256-bit vector result, first insert into a 128-bit
7871 // vector and then insert into the 256-bit vector.
7872 if (!OpVT.is128BitVector()) {
7873 // Insert into a 128-bit vector.
7874 unsigned SizeFactor = OpVT.getSizeInBits()/128;
7875 MVT VT128 = MVT::getVectorVT(OpVT.getVectorElementType(),
7876 OpVT.getVectorNumElements() / SizeFactor);
7878 Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Op.getOperand(0));
7880 // Insert the 128-bit vector.
7881 return Insert128BitVector(DAG.getUNDEF(OpVT), Op, 0, DAG, dl);
7884 if (OpVT == MVT::v1i64 &&
7885 Op.getOperand(0).getValueType() == MVT::i64)
7886 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
7888 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
7889 assert(OpVT.is128BitVector() && "Expected an SSE type!");
7890 return DAG.getNode(ISD::BITCAST, dl, OpVT,
7891 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,AnyExt));
7894 // Lower a node with an EXTRACT_SUBVECTOR opcode. This may result in
7895 // a simple subregister reference or explicit instructions to grab
7896 // upper bits of a vector.
7897 static SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
7898 SelectionDAG &DAG) {
7900 SDValue In = Op.getOperand(0);
7901 SDValue Idx = Op.getOperand(1);
7902 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
7903 MVT ResVT = Op.getSimpleValueType();
7904 MVT InVT = In.getSimpleValueType();
7906 if (Subtarget->hasFp256()) {
7907 if (ResVT.is128BitVector() &&
7908 (InVT.is256BitVector() || InVT.is512BitVector()) &&
7909 isa<ConstantSDNode>(Idx)) {
7910 return Extract128BitVector(In, IdxVal, DAG, dl);
7912 if (ResVT.is256BitVector() && InVT.is512BitVector() &&
7913 isa<ConstantSDNode>(Idx)) {
7914 return Extract256BitVector(In, IdxVal, DAG, dl);
7920 // Lower a node with an INSERT_SUBVECTOR opcode. This may result in a
7921 // simple superregister reference or explicit instructions to insert
7922 // the upper bits of a vector.
7923 static SDValue LowerINSERT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
7924 SelectionDAG &DAG) {
7925 if (Subtarget->hasFp256()) {
7926 SDLoc dl(Op.getNode());
7927 SDValue Vec = Op.getNode()->getOperand(0);
7928 SDValue SubVec = Op.getNode()->getOperand(1);
7929 SDValue Idx = Op.getNode()->getOperand(2);
7931 if ((Op.getNode()->getSimpleValueType(0).is256BitVector() ||
7932 Op.getNode()->getSimpleValueType(0).is512BitVector()) &&
7933 SubVec.getNode()->getSimpleValueType(0).is128BitVector() &&
7934 isa<ConstantSDNode>(Idx)) {
7935 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
7936 return Insert128BitVector(Vec, SubVec, IdxVal, DAG, dl);
7939 if (Op.getNode()->getSimpleValueType(0).is512BitVector() &&
7940 SubVec.getNode()->getSimpleValueType(0).is256BitVector() &&
7941 isa<ConstantSDNode>(Idx)) {
7942 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
7943 return Insert256BitVector(Vec, SubVec, IdxVal, DAG, dl);
7949 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
7950 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
7951 // one of the above mentioned nodes. It has to be wrapped because otherwise
7952 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
7953 // be used to form addressing mode. These wrapped nodes will be selected
7956 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
7957 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
7959 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
7961 unsigned char OpFlag = 0;
7962 unsigned WrapperKind = X86ISD::Wrapper;
7963 CodeModel::Model M = getTargetMachine().getCodeModel();
7965 if (Subtarget->isPICStyleRIPRel() &&
7966 (M == CodeModel::Small || M == CodeModel::Kernel))
7967 WrapperKind = X86ISD::WrapperRIP;
7968 else if (Subtarget->isPICStyleGOT())
7969 OpFlag = X86II::MO_GOTOFF;
7970 else if (Subtarget->isPICStyleStubPIC())
7971 OpFlag = X86II::MO_PIC_BASE_OFFSET;
7973 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(),
7975 CP->getOffset(), OpFlag);
7977 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
7978 // With PIC, the address is actually $g + Offset.
7980 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7981 DAG.getNode(X86ISD::GlobalBaseReg,
7982 SDLoc(), getPointerTy()),
7989 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
7990 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
7992 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
7994 unsigned char OpFlag = 0;
7995 unsigned WrapperKind = X86ISD::Wrapper;
7996 CodeModel::Model M = getTargetMachine().getCodeModel();
7998 if (Subtarget->isPICStyleRIPRel() &&
7999 (M == CodeModel::Small || M == CodeModel::Kernel))
8000 WrapperKind = X86ISD::WrapperRIP;
8001 else if (Subtarget->isPICStyleGOT())
8002 OpFlag = X86II::MO_GOTOFF;
8003 else if (Subtarget->isPICStyleStubPIC())
8004 OpFlag = X86II::MO_PIC_BASE_OFFSET;
8006 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(),
8009 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
8011 // With PIC, the address is actually $g + Offset.
8013 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
8014 DAG.getNode(X86ISD::GlobalBaseReg,
8015 SDLoc(), getPointerTy()),
8022 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const {
8023 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
8025 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
8027 unsigned char OpFlag = 0;
8028 unsigned WrapperKind = X86ISD::Wrapper;
8029 CodeModel::Model M = getTargetMachine().getCodeModel();
8031 if (Subtarget->isPICStyleRIPRel() &&
8032 (M == CodeModel::Small || M == CodeModel::Kernel)) {
8033 if (Subtarget->isTargetDarwin() || Subtarget->isTargetELF())
8034 OpFlag = X86II::MO_GOTPCREL;
8035 WrapperKind = X86ISD::WrapperRIP;
8036 } else if (Subtarget->isPICStyleGOT()) {
8037 OpFlag = X86II::MO_GOT;
8038 } else if (Subtarget->isPICStyleStubPIC()) {
8039 OpFlag = X86II::MO_DARWIN_NONLAZY_PIC_BASE;
8040 } else if (Subtarget->isPICStyleStubNoDynamic()) {
8041 OpFlag = X86II::MO_DARWIN_NONLAZY;
8044 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag);
8047 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
8049 // With PIC, the address is actually $g + Offset.
8050 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
8051 !Subtarget->is64Bit()) {
8052 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
8053 DAG.getNode(X86ISD::GlobalBaseReg,
8054 SDLoc(), getPointerTy()),
8058 // For symbols that require a load from a stub to get the address, emit the
8060 if (isGlobalStubReference(OpFlag))
8061 Result = DAG.getLoad(getPointerTy(), DL, DAG.getEntryNode(), Result,
8062 MachinePointerInfo::getGOT(), false, false, false, 0);
8068 X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
8069 // Create the TargetBlockAddressAddress node.
8070 unsigned char OpFlags =
8071 Subtarget->ClassifyBlockAddressReference();
8072 CodeModel::Model M = getTargetMachine().getCodeModel();
8073 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
8074 int64_t Offset = cast<BlockAddressSDNode>(Op)->getOffset();
8076 SDValue Result = DAG.getTargetBlockAddress(BA, getPointerTy(), Offset,
8079 if (Subtarget->isPICStyleRIPRel() &&
8080 (M == CodeModel::Small || M == CodeModel::Kernel))
8081 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
8083 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
8085 // With PIC, the address is actually $g + Offset.
8086 if (isGlobalRelativeToPICBase(OpFlags)) {
8087 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
8088 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
8096 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, SDLoc dl,
8097 int64_t Offset, SelectionDAG &DAG) const {
8098 // Create the TargetGlobalAddress node, folding in the constant
8099 // offset if it is legal.
8100 unsigned char OpFlags =
8101 Subtarget->ClassifyGlobalReference(GV, getTargetMachine());
8102 CodeModel::Model M = getTargetMachine().getCodeModel();
8104 if (OpFlags == X86II::MO_NO_FLAG &&
8105 X86::isOffsetSuitableForCodeModel(Offset, M)) {
8106 // A direct static reference to a global.
8107 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), Offset);
8110 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags);
8113 if (Subtarget->isPICStyleRIPRel() &&
8114 (M == CodeModel::Small || M == CodeModel::Kernel))
8115 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
8117 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
8119 // With PIC, the address is actually $g + Offset.
8120 if (isGlobalRelativeToPICBase(OpFlags)) {
8121 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
8122 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
8126 // For globals that require a load from a stub to get the address, emit the
8128 if (isGlobalStubReference(OpFlags))
8129 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result,
8130 MachinePointerInfo::getGOT(), false, false, false, 0);
8132 // If there was a non-zero offset that we didn't fold, create an explicit
8135 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result,
8136 DAG.getConstant(Offset, getPointerTy()));
8142 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
8143 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
8144 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
8145 return LowerGlobalAddress(GV, SDLoc(Op), Offset, DAG);
8149 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
8150 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg,
8151 unsigned char OperandFlags, bool LocalDynamic = false) {
8152 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
8153 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
8155 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
8156 GA->getValueType(0),
8160 X86ISD::NodeType CallType = LocalDynamic ? X86ISD::TLSBASEADDR
8164 SDValue Ops[] = { Chain, TGA, *InFlag };
8165 Chain = DAG.getNode(CallType, dl, NodeTys, Ops, array_lengthof(Ops));
8167 SDValue Ops[] = { Chain, TGA };
8168 Chain = DAG.getNode(CallType, dl, NodeTys, Ops, array_lengthof(Ops));
8171 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
8172 MFI->setAdjustsStack(true);
8174 SDValue Flag = Chain.getValue(1);
8175 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
8178 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
8180 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
8183 SDLoc dl(GA); // ? function entry point might be better
8184 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
8185 DAG.getNode(X86ISD::GlobalBaseReg,
8186 SDLoc(), PtrVT), InFlag);
8187 InFlag = Chain.getValue(1);
8189 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
8192 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
8194 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
8196 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, NULL, PtrVT,
8197 X86::RAX, X86II::MO_TLSGD);
8200 static SDValue LowerToTLSLocalDynamicModel(GlobalAddressSDNode *GA,
8206 // Get the start address of the TLS block for this module.
8207 X86MachineFunctionInfo* MFI = DAG.getMachineFunction()
8208 .getInfo<X86MachineFunctionInfo>();
8209 MFI->incNumLocalDynamicTLSAccesses();
8213 Base = GetTLSADDR(DAG, DAG.getEntryNode(), GA, NULL, PtrVT, X86::RAX,
8214 X86II::MO_TLSLD, /*LocalDynamic=*/true);
8217 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
8218 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), InFlag);
8219 InFlag = Chain.getValue(1);
8220 Base = GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX,
8221 X86II::MO_TLSLDM, /*LocalDynamic=*/true);
8224 // Note: the CleanupLocalDynamicTLSPass will remove redundant computations
8228 unsigned char OperandFlags = X86II::MO_DTPOFF;
8229 unsigned WrapperKind = X86ISD::Wrapper;
8230 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
8231 GA->getValueType(0),
8232 GA->getOffset(), OperandFlags);
8233 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
8235 // Add x@dtpoff with the base.
8236 return DAG.getNode(ISD::ADD, dl, PtrVT, Offset, Base);
8239 // Lower ISD::GlobalTLSAddress using the "initial exec" or "local exec" model.
8240 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
8241 const EVT PtrVT, TLSModel::Model model,
8242 bool is64Bit, bool isPIC) {
8245 // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit).
8246 Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(*DAG.getContext(),
8247 is64Bit ? 257 : 256));
8249 SDValue ThreadPointer =
8250 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), DAG.getIntPtrConstant(0),
8251 MachinePointerInfo(Ptr), false, false, false, 0);
8253 unsigned char OperandFlags = 0;
8254 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
8256 unsigned WrapperKind = X86ISD::Wrapper;
8257 if (model == TLSModel::LocalExec) {
8258 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
8259 } else if (model == TLSModel::InitialExec) {
8261 OperandFlags = X86II::MO_GOTTPOFF;
8262 WrapperKind = X86ISD::WrapperRIP;
8264 OperandFlags = isPIC ? X86II::MO_GOTNTPOFF : X86II::MO_INDNTPOFF;
8267 llvm_unreachable("Unexpected model");
8270 // emit "addl x@ntpoff,%eax" (local exec)
8271 // or "addl x@indntpoff,%eax" (initial exec)
8272 // or "addl x@gotntpoff(%ebx) ,%eax" (initial exec, 32-bit pic)
8274 DAG.getTargetGlobalAddress(GA->getGlobal(), dl, GA->getValueType(0),
8275 GA->getOffset(), OperandFlags);
8276 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
8278 if (model == TLSModel::InitialExec) {
8279 if (isPIC && !is64Bit) {
8280 Offset = DAG.getNode(ISD::ADD, dl, PtrVT,
8281 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT),
8285 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
8286 MachinePointerInfo::getGOT(), false, false, false, 0);
8289 // The address of the thread local variable is the add of the thread
8290 // pointer with the offset of the variable.
8291 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
8295 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
8297 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
8298 const GlobalValue *GV = GA->getGlobal();
8300 if (Subtarget->isTargetELF()) {
8301 TLSModel::Model model = getTargetMachine().getTLSModel(GV);
8304 case TLSModel::GeneralDynamic:
8305 if (Subtarget->is64Bit())
8306 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy());
8307 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy());
8308 case TLSModel::LocalDynamic:
8309 return LowerToTLSLocalDynamicModel(GA, DAG, getPointerTy(),
8310 Subtarget->is64Bit());
8311 case TLSModel::InitialExec:
8312 case TLSModel::LocalExec:
8313 return LowerToTLSExecModel(GA, DAG, getPointerTy(), model,
8314 Subtarget->is64Bit(),
8315 getTargetMachine().getRelocationModel() == Reloc::PIC_);
8317 llvm_unreachable("Unknown TLS model.");
8320 if (Subtarget->isTargetDarwin()) {
8321 // Darwin only has one model of TLS. Lower to that.
8322 unsigned char OpFlag = 0;
8323 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ?
8324 X86ISD::WrapperRIP : X86ISD::Wrapper;
8326 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
8328 bool PIC32 = (getTargetMachine().getRelocationModel() == Reloc::PIC_) &&
8329 !Subtarget->is64Bit();
8331 OpFlag = X86II::MO_TLVP_PIC_BASE;
8333 OpFlag = X86II::MO_TLVP;
8335 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL,
8336 GA->getValueType(0),
8337 GA->getOffset(), OpFlag);
8338 SDValue Offset = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
8340 // With PIC32, the address is actually $g + Offset.
8342 Offset = DAG.getNode(ISD::ADD, DL, getPointerTy(),
8343 DAG.getNode(X86ISD::GlobalBaseReg,
8344 SDLoc(), getPointerTy()),
8347 // Lowering the machine isd will make sure everything is in the right
8349 SDValue Chain = DAG.getEntryNode();
8350 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
8351 SDValue Args[] = { Chain, Offset };
8352 Chain = DAG.getNode(X86ISD::TLSCALL, DL, NodeTys, Args, 2);
8354 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls.
8355 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
8356 MFI->setAdjustsStack(true);
8358 // And our return value (tls address) is in the standard call return value
8360 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
8361 return DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(),
8365 if (Subtarget->isTargetWindows() || Subtarget->isTargetMingw()) {
8366 // Just use the implicit TLS architecture
8367 // Need to generate someting similar to:
8368 // mov rdx, qword [gs:abs 58H]; Load pointer to ThreadLocalStorage
8370 // mov ecx, dword [rel _tls_index]: Load index (from C runtime)
8371 // mov rcx, qword [rdx+rcx*8]
8372 // mov eax, .tls$:tlsvar
8373 // [rax+rcx] contains the address
8374 // Windows 64bit: gs:0x58
8375 // Windows 32bit: fs:__tls_array
8377 // If GV is an alias then use the aliasee for determining
8378 // thread-localness.
8379 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV))
8380 GV = GA->resolveAliasedGlobal(false);
8382 SDValue Chain = DAG.getEntryNode();
8384 // Get the Thread Pointer, which is %fs:__tls_array (32-bit) or
8385 // %gs:0x58 (64-bit). On MinGW, __tls_array is not available, so directly
8386 // use its literal value of 0x2C.
8387 Value *Ptr = Constant::getNullValue(Subtarget->is64Bit()
8388 ? Type::getInt8PtrTy(*DAG.getContext(),
8390 : Type::getInt32PtrTy(*DAG.getContext(),
8393 SDValue TlsArray = Subtarget->is64Bit() ? DAG.getIntPtrConstant(0x58) :
8394 (Subtarget->isTargetMingw() ? DAG.getIntPtrConstant(0x2C) :
8395 DAG.getExternalSymbol("_tls_array", getPointerTy()));
8397 SDValue ThreadPointer = DAG.getLoad(getPointerTy(), dl, Chain, TlsArray,
8398 MachinePointerInfo(Ptr),
8399 false, false, false, 0);
8401 // Load the _tls_index variable
8402 SDValue IDX = DAG.getExternalSymbol("_tls_index", getPointerTy());
8403 if (Subtarget->is64Bit())
8404 IDX = DAG.getExtLoad(ISD::ZEXTLOAD, dl, getPointerTy(), Chain,
8405 IDX, MachinePointerInfo(), MVT::i32,
8408 IDX = DAG.getLoad(getPointerTy(), dl, Chain, IDX, MachinePointerInfo(),
8409 false, false, false, 0);
8411 SDValue Scale = DAG.getConstant(Log2_64_Ceil(TD->getPointerSize()),
8413 IDX = DAG.getNode(ISD::SHL, dl, getPointerTy(), IDX, Scale);
8415 SDValue res = DAG.getNode(ISD::ADD, dl, getPointerTy(), ThreadPointer, IDX);
8416 res = DAG.getLoad(getPointerTy(), dl, Chain, res, MachinePointerInfo(),
8417 false, false, false, 0);
8419 // Get the offset of start of .tls section
8420 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
8421 GA->getValueType(0),
8422 GA->getOffset(), X86II::MO_SECREL);
8423 SDValue Offset = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), TGA);
8425 // The address of the thread local variable is the add of the thread
8426 // pointer with the offset of the variable.
8427 return DAG.getNode(ISD::ADD, dl, getPointerTy(), res, Offset);
8430 llvm_unreachable("TLS not implemented for this target.");
8433 /// LowerShiftParts - Lower SRA_PARTS and friends, which return two i32 values
8434 /// and take a 2 x i32 value to shift plus a shift amount.
8435 SDValue X86TargetLowering::LowerShiftParts(SDValue Op, SelectionDAG &DAG) const{
8436 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
8437 EVT VT = Op.getValueType();
8438 unsigned VTBits = VT.getSizeInBits();
8440 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
8441 SDValue ShOpLo = Op.getOperand(0);
8442 SDValue ShOpHi = Op.getOperand(1);
8443 SDValue ShAmt = Op.getOperand(2);
8444 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
8445 DAG.getConstant(VTBits - 1, MVT::i8))
8446 : DAG.getConstant(0, VT);
8449 if (Op.getOpcode() == ISD::SHL_PARTS) {
8450 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
8451 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
8453 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
8454 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, ShAmt);
8457 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
8458 DAG.getConstant(VTBits, MVT::i8));
8459 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
8460 AndNode, DAG.getConstant(0, MVT::i8));
8463 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8);
8464 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
8465 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
8467 if (Op.getOpcode() == ISD::SHL_PARTS) {
8468 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
8469 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
8471 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
8472 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
8475 SDValue Ops[2] = { Lo, Hi };
8476 return DAG.getMergeValues(Ops, array_lengthof(Ops), dl);
8479 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op,
8480 SelectionDAG &DAG) const {
8481 EVT SrcVT = Op.getOperand(0).getValueType();
8483 if (SrcVT.isVector())
8486 assert(SrcVT.getSimpleVT() <= MVT::i64 && SrcVT.getSimpleVT() >= MVT::i16 &&
8487 "Unknown SINT_TO_FP to lower!");
8489 // These are really Legal; return the operand so the caller accepts it as
8491 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
8493 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
8494 Subtarget->is64Bit()) {
8499 unsigned Size = SrcVT.getSizeInBits()/8;
8500 MachineFunction &MF = DAG.getMachineFunction();
8501 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false);
8502 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
8503 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
8505 MachinePointerInfo::getFixedStack(SSFI),
8507 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
8510 SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
8512 SelectionDAG &DAG) const {
8516 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
8518 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Glue);
8520 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
8522 unsigned ByteSize = SrcVT.getSizeInBits()/8;
8524 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(StackSlot);
8525 MachineMemOperand *MMO;
8527 int SSFI = FI->getIndex();
8529 DAG.getMachineFunction()
8530 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
8531 MachineMemOperand::MOLoad, ByteSize, ByteSize);
8533 MMO = cast<LoadSDNode>(StackSlot)->getMemOperand();
8534 StackSlot = StackSlot.getOperand(1);
8536 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) };
8537 SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG :
8539 Tys, Ops, array_lengthof(Ops),
8543 Chain = Result.getValue(1);
8544 SDValue InFlag = Result.getValue(2);
8546 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
8547 // shouldn't be necessary except that RFP cannot be live across
8548 // multiple blocks. When stackifier is fixed, they can be uncoupled.
8549 MachineFunction &MF = DAG.getMachineFunction();
8550 unsigned SSFISize = Op.getValueType().getSizeInBits()/8;
8551 int SSFI = MF.getFrameInfo()->CreateStackObject(SSFISize, SSFISize, false);
8552 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
8553 Tys = DAG.getVTList(MVT::Other);
8555 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag
8557 MachineMemOperand *MMO =
8558 DAG.getMachineFunction()
8559 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
8560 MachineMemOperand::MOStore, SSFISize, SSFISize);
8562 Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys,
8563 Ops, array_lengthof(Ops),
8564 Op.getValueType(), MMO);
8565 Result = DAG.getLoad(Op.getValueType(), DL, Chain, StackSlot,
8566 MachinePointerInfo::getFixedStack(SSFI),
8567 false, false, false, 0);
8573 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
8574 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op,
8575 SelectionDAG &DAG) const {
8576 // This algorithm is not obvious. Here it is what we're trying to output:
8579 punpckldq (c0), %xmm0 // c0: (uint4){ 0x43300000U, 0x45300000U, 0U, 0U }
8580 subpd (c1), %xmm0 // c1: (double2){ 0x1.0p52, 0x1.0p52 * 0x1.0p32 }
8584 pshufd $0x4e, %xmm0, %xmm1
8590 LLVMContext *Context = DAG.getContext();
8592 // Build some magic constants.
8593 static const uint32_t CV0[] = { 0x43300000, 0x45300000, 0, 0 };
8594 Constant *C0 = ConstantDataVector::get(*Context, CV0);
8595 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16);
8597 SmallVector<Constant*,2> CV1;
8599 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
8600 APInt(64, 0x4330000000000000ULL))));
8602 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
8603 APInt(64, 0x4530000000000000ULL))));
8604 Constant *C1 = ConstantVector::get(CV1);
8605 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16);
8607 // Load the 64-bit value into an XMM register.
8608 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
8610 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
8611 MachinePointerInfo::getConstantPool(),
8612 false, false, false, 16);
8613 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32,
8614 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, XR1),
8617 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
8618 MachinePointerInfo::getConstantPool(),
8619 false, false, false, 16);
8620 SDValue XR2F = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Unpck1);
8621 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
8624 if (Subtarget->hasSSE3()) {
8625 // FIXME: The 'haddpd' instruction may be slower than 'movhlps + addsd'.
8626 Result = DAG.getNode(X86ISD::FHADD, dl, MVT::v2f64, Sub, Sub);
8628 SDValue S2F = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Sub);
8629 SDValue Shuffle = getTargetShuffleNode(X86ISD::PSHUFD, dl, MVT::v4i32,
8631 Result = DAG.getNode(ISD::FADD, dl, MVT::v2f64,
8632 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Shuffle),
8636 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Result,
8637 DAG.getIntPtrConstant(0));
8640 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
8641 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op,
8642 SelectionDAG &DAG) const {
8644 // FP constant to bias correct the final result.
8645 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
8648 // Load the 32-bit value into an XMM register.
8649 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
8652 // Zero out the upper parts of the register.
8653 Load = getShuffleVectorZeroOrUndef(Load, 0, true, Subtarget, DAG);
8655 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
8656 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Load),
8657 DAG.getIntPtrConstant(0));
8659 // Or the load with the bias.
8660 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64,
8661 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
8662 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
8664 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
8665 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
8666 MVT::v2f64, Bias)));
8667 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
8668 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or),
8669 DAG.getIntPtrConstant(0));
8671 // Subtract the bias.
8672 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
8674 // Handle final rounding.
8675 EVT DestVT = Op.getValueType();
8677 if (DestVT.bitsLT(MVT::f64))
8678 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
8679 DAG.getIntPtrConstant(0));
8680 if (DestVT.bitsGT(MVT::f64))
8681 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
8683 // Handle final rounding.
8687 SDValue X86TargetLowering::lowerUINT_TO_FP_vec(SDValue Op,
8688 SelectionDAG &DAG) const {
8689 SDValue N0 = Op.getOperand(0);
8690 EVT SVT = N0.getValueType();
8693 assert((SVT == MVT::v4i8 || SVT == MVT::v4i16 ||
8694 SVT == MVT::v8i8 || SVT == MVT::v8i16) &&
8695 "Custom UINT_TO_FP is not supported!");
8697 EVT NVT = EVT::getVectorVT(*DAG.getContext(), MVT::i32,
8698 SVT.getVectorNumElements());
8699 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
8700 DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, N0));
8703 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op,
8704 SelectionDAG &DAG) const {
8705 SDValue N0 = Op.getOperand(0);
8708 if (Op.getValueType().isVector())
8709 return lowerUINT_TO_FP_vec(Op, DAG);
8711 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't
8712 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
8713 // the optimization here.
8714 if (DAG.SignBitIsZero(N0))
8715 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
8717 EVT SrcVT = N0.getValueType();
8718 EVT DstVT = Op.getValueType();
8719 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64)
8720 return LowerUINT_TO_FP_i64(Op, DAG);
8721 if (SrcVT == MVT::i32 && X86ScalarSSEf64)
8722 return LowerUINT_TO_FP_i32(Op, DAG);
8723 if (Subtarget->is64Bit() && SrcVT == MVT::i64 && DstVT == MVT::f32)
8726 // Make a 64-bit buffer, and use it to build an FILD.
8727 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
8728 if (SrcVT == MVT::i32) {
8729 SDValue WordOff = DAG.getConstant(4, getPointerTy());
8730 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl,
8731 getPointerTy(), StackSlot, WordOff);
8732 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
8733 StackSlot, MachinePointerInfo(),
8735 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32),
8736 OffsetSlot, MachinePointerInfo(),
8738 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
8742 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP");
8743 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
8744 StackSlot, MachinePointerInfo(),
8746 // For i64 source, we need to add the appropriate power of 2 if the input
8747 // was negative. This is the same as the optimization in
8748 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here,
8749 // we must be careful to do the computation in x87 extended precision, not
8750 // in SSE. (The generic code can't know it's OK to do this, or how to.)
8751 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex();
8752 MachineMemOperand *MMO =
8753 DAG.getMachineFunction()
8754 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
8755 MachineMemOperand::MOLoad, 8, 8);
8757 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other);
8758 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) };
8759 SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops,
8760 array_lengthof(Ops), MVT::i64, MMO);
8762 APInt FF(32, 0x5F800000ULL);
8764 // Check whether the sign bit is set.
8765 SDValue SignSet = DAG.getSetCC(dl,
8766 getSetCCResultType(*DAG.getContext(), MVT::i64),
8767 Op.getOperand(0), DAG.getConstant(0, MVT::i64),
8770 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
8771 SDValue FudgePtr = DAG.getConstantPool(
8772 ConstantInt::get(*DAG.getContext(), FF.zext(64)),
8775 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
8776 SDValue Zero = DAG.getIntPtrConstant(0);
8777 SDValue Four = DAG.getIntPtrConstant(4);
8778 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
8780 FudgePtr = DAG.getNode(ISD::ADD, dl, getPointerTy(), FudgePtr, Offset);
8782 // Load the value out, extending it from f32 to f80.
8783 // FIXME: Avoid the extend by constructing the right constant pool?
8784 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, MVT::f80, DAG.getEntryNode(),
8785 FudgePtr, MachinePointerInfo::getConstantPool(),
8786 MVT::f32, false, false, 4);
8787 // Extend everything to 80 bits to force it to be done on x87.
8788 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge);
8789 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add, DAG.getIntPtrConstant(0));
8792 std::pair<SDValue,SDValue>
8793 X86TargetLowering:: FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG,
8794 bool IsSigned, bool IsReplace) const {
8797 EVT DstTy = Op.getValueType();
8799 if (!IsSigned && !isIntegerTypeFTOL(DstTy)) {
8800 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
8804 assert(DstTy.getSimpleVT() <= MVT::i64 &&
8805 DstTy.getSimpleVT() >= MVT::i16 &&
8806 "Unknown FP_TO_INT to lower!");
8808 // These are really Legal.
8809 if (DstTy == MVT::i32 &&
8810 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
8811 return std::make_pair(SDValue(), SDValue());
8812 if (Subtarget->is64Bit() &&
8813 DstTy == MVT::i64 &&
8814 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
8815 return std::make_pair(SDValue(), SDValue());
8817 // We lower FP->int64 either into FISTP64 followed by a load from a temporary
8818 // stack slot, or into the FTOL runtime function.
8819 MachineFunction &MF = DAG.getMachineFunction();
8820 unsigned MemSize = DstTy.getSizeInBits()/8;
8821 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
8822 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
8825 if (!IsSigned && isIntegerTypeFTOL(DstTy))
8826 Opc = X86ISD::WIN_FTOL;
8828 switch (DstTy.getSimpleVT().SimpleTy) {
8829 default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
8830 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
8831 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
8832 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
8835 SDValue Chain = DAG.getEntryNode();
8836 SDValue Value = Op.getOperand(0);
8837 EVT TheVT = Op.getOperand(0).getValueType();
8838 // FIXME This causes a redundant load/store if the SSE-class value is already
8839 // in memory, such as if it is on the callstack.
8840 if (isScalarFPTypeInSSEReg(TheVT)) {
8841 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
8842 Chain = DAG.getStore(Chain, DL, Value, StackSlot,
8843 MachinePointerInfo::getFixedStack(SSFI),
8845 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
8847 Chain, StackSlot, DAG.getValueType(TheVT)
8850 MachineMemOperand *MMO =
8851 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
8852 MachineMemOperand::MOLoad, MemSize, MemSize);
8853 Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops,
8854 array_lengthof(Ops), DstTy, MMO);
8855 Chain = Value.getValue(1);
8856 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
8857 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
8860 MachineMemOperand *MMO =
8861 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
8862 MachineMemOperand::MOStore, MemSize, MemSize);
8864 if (Opc != X86ISD::WIN_FTOL) {
8865 // Build the FP_TO_INT*_IN_MEM
8866 SDValue Ops[] = { Chain, Value, StackSlot };
8867 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
8868 Ops, array_lengthof(Ops), DstTy,
8870 return std::make_pair(FIST, StackSlot);
8872 SDValue ftol = DAG.getNode(X86ISD::WIN_FTOL, DL,
8873 DAG.getVTList(MVT::Other, MVT::Glue),
8875 SDValue eax = DAG.getCopyFromReg(ftol, DL, X86::EAX,
8876 MVT::i32, ftol.getValue(1));
8877 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), DL, X86::EDX,
8878 MVT::i32, eax.getValue(2));
8879 SDValue Ops[] = { eax, edx };
8880 SDValue pair = IsReplace
8881 ? DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops, array_lengthof(Ops))
8882 : DAG.getMergeValues(Ops, array_lengthof(Ops), DL);
8883 return std::make_pair(pair, SDValue());
8887 static SDValue LowerAVXExtend(SDValue Op, SelectionDAG &DAG,
8888 const X86Subtarget *Subtarget) {
8889 MVT VT = Op->getSimpleValueType(0);
8890 SDValue In = Op->getOperand(0);
8891 MVT InVT = In.getSimpleValueType();
8894 // Optimize vectors in AVX mode:
8897 // Use vpunpcklwd for 4 lower elements v8i16 -> v4i32.
8898 // Use vpunpckhwd for 4 upper elements v8i16 -> v4i32.
8899 // Concat upper and lower parts.
8902 // Use vpunpckldq for 4 lower elements v4i32 -> v2i64.
8903 // Use vpunpckhdq for 4 upper elements v4i32 -> v2i64.
8904 // Concat upper and lower parts.
8907 if (((VT != MVT::v16i16) || (InVT != MVT::v16i8)) &&
8908 ((VT != MVT::v8i32) || (InVT != MVT::v8i16)) &&
8909 ((VT != MVT::v4i64) || (InVT != MVT::v4i32)))
8912 if (Subtarget->hasInt256())
8913 return DAG.getNode(X86ISD::VZEXT_MOVL, dl, VT, In);
8915 SDValue ZeroVec = getZeroVector(InVT, Subtarget, DAG, dl);
8916 SDValue Undef = DAG.getUNDEF(InVT);
8917 bool NeedZero = Op.getOpcode() == ISD::ZERO_EXTEND;
8918 SDValue OpLo = getUnpackl(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
8919 SDValue OpHi = getUnpackh(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
8921 MVT HVT = MVT::getVectorVT(VT.getVectorElementType(),
8922 VT.getVectorNumElements()/2);
8924 OpLo = DAG.getNode(ISD::BITCAST, dl, HVT, OpLo);
8925 OpHi = DAG.getNode(ISD::BITCAST, dl, HVT, OpHi);
8927 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
8930 static SDValue LowerZERO_EXTEND_AVX512(SDValue Op,
8931 SelectionDAG &DAG) {
8932 MVT VT = Op->getValueType(0).getSimpleVT();
8933 SDValue In = Op->getOperand(0);
8934 MVT InVT = In.getValueType().getSimpleVT();
8936 unsigned int NumElts = VT.getVectorNumElements();
8937 if (NumElts != 8 && NumElts != 16)
8940 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1)
8941 return DAG.getNode(X86ISD::VZEXT, DL, VT, In);
8943 EVT ExtVT = (NumElts == 8)? MVT::v8i64 : MVT::v16i32;
8944 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
8945 // Now we have only mask extension
8946 assert(InVT.getVectorElementType() == MVT::i1);
8947 SDValue Cst = DAG.getTargetConstant(1, ExtVT.getScalarType());
8948 const Constant *C = (dyn_cast<ConstantSDNode>(Cst))->getConstantIntValue();
8949 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
8950 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
8951 SDValue Ld = DAG.getLoad(Cst.getValueType(), DL, DAG.getEntryNode(), CP,
8952 MachinePointerInfo::getConstantPool(),
8953 false, false, false, Alignment);
8955 SDValue Brcst = DAG.getNode(X86ISD::VBROADCASTM, DL, ExtVT, In, Ld);
8956 if (VT.is512BitVector())
8958 return DAG.getNode(X86ISD::VTRUNC, DL, VT, Brcst);
8961 static SDValue LowerANY_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
8962 SelectionDAG &DAG) {
8963 if (Subtarget->hasFp256()) {
8964 SDValue Res = LowerAVXExtend(Op, DAG, Subtarget);
8972 static SDValue LowerZERO_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
8973 SelectionDAG &DAG) {
8975 MVT VT = Op.getSimpleValueType();
8976 SDValue In = Op.getOperand(0);
8977 MVT SVT = In.getSimpleValueType();
8979 if (VT.is512BitVector() || SVT.getVectorElementType() == MVT::i1)
8980 return LowerZERO_EXTEND_AVX512(Op, DAG);
8982 if (Subtarget->hasFp256()) {
8983 SDValue Res = LowerAVXExtend(Op, DAG, Subtarget);
8988 assert(!VT.is256BitVector() || !SVT.is128BitVector() ||
8989 VT.getVectorNumElements() != SVT.getVectorNumElements());
8993 SDValue X86TargetLowering::LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const {
8995 MVT VT = Op.getSimpleValueType();
8996 SDValue In = Op.getOperand(0);
8997 MVT InVT = In.getSimpleValueType();
8998 assert(VT.getVectorNumElements() == InVT.getVectorNumElements() &&
8999 "Invalid TRUNCATE operation");
9001 if (InVT.is512BitVector() || VT.getVectorElementType() == MVT::i1) {
9002 if (VT.getVectorElementType().getSizeInBits() >=8)
9003 return DAG.getNode(X86ISD::VTRUNC, DL, VT, In);
9005 assert(VT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
9006 unsigned NumElts = InVT.getVectorNumElements();
9007 assert ((NumElts == 8 || NumElts == 16) && "Unexpected vector type");
9008 if (InVT.getSizeInBits() < 512) {
9009 MVT ExtVT = (NumElts == 16)? MVT::v16i32 : MVT::v8i64;
9010 In = DAG.getNode(ISD::SIGN_EXTEND, DL, ExtVT, In);
9013 SDValue Cst = DAG.getTargetConstant(1, InVT.getVectorElementType());
9014 const Constant *C = (dyn_cast<ConstantSDNode>(Cst))->getConstantIntValue();
9015 SDValue CP = DAG.getConstantPool(C, getPointerTy());
9016 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
9017 SDValue Ld = DAG.getLoad(Cst.getValueType(), DL, DAG.getEntryNode(), CP,
9018 MachinePointerInfo::getConstantPool(),
9019 false, false, false, Alignment);
9020 SDValue OneV = DAG.getNode(X86ISD::VBROADCAST, DL, InVT, Ld);
9021 SDValue And = DAG.getNode(ISD::AND, DL, InVT, OneV, In);
9022 return DAG.getNode(X86ISD::TESTM, DL, VT, And, And);
9025 if ((VT == MVT::v4i32) && (InVT == MVT::v4i64)) {
9026 // On AVX2, v4i64 -> v4i32 becomes VPERMD.
9027 if (Subtarget->hasInt256()) {
9028 static const int ShufMask[] = {0, 2, 4, 6, -1, -1, -1, -1};
9029 In = DAG.getNode(ISD::BITCAST, DL, MVT::v8i32, In);
9030 In = DAG.getVectorShuffle(MVT::v8i32, DL, In, DAG.getUNDEF(MVT::v8i32),
9032 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, In,
9033 DAG.getIntPtrConstant(0));
9036 // On AVX, v4i64 -> v4i32 becomes a sequence that uses PSHUFD and MOVLHPS.
9037 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
9038 DAG.getIntPtrConstant(0));
9039 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
9040 DAG.getIntPtrConstant(2));
9042 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo);
9043 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi);
9046 static const int ShufMask1[] = {0, 2, 0, 0};
9047 SDValue Undef = DAG.getUNDEF(VT);
9048 OpLo = DAG.getVectorShuffle(VT, DL, OpLo, Undef, ShufMask1);
9049 OpHi = DAG.getVectorShuffle(VT, DL, OpHi, Undef, ShufMask1);
9051 // The MOVLHPS mask:
9052 static const int ShufMask2[] = {0, 1, 4, 5};
9053 return DAG.getVectorShuffle(VT, DL, OpLo, OpHi, ShufMask2);
9056 if ((VT == MVT::v8i16) && (InVT == MVT::v8i32)) {
9057 // On AVX2, v8i32 -> v8i16 becomed PSHUFB.
9058 if (Subtarget->hasInt256()) {
9059 In = DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, In);
9061 SmallVector<SDValue,32> pshufbMask;
9062 for (unsigned i = 0; i < 2; ++i) {
9063 pshufbMask.push_back(DAG.getConstant(0x0, MVT::i8));
9064 pshufbMask.push_back(DAG.getConstant(0x1, MVT::i8));
9065 pshufbMask.push_back(DAG.getConstant(0x4, MVT::i8));
9066 pshufbMask.push_back(DAG.getConstant(0x5, MVT::i8));
9067 pshufbMask.push_back(DAG.getConstant(0x8, MVT::i8));
9068 pshufbMask.push_back(DAG.getConstant(0x9, MVT::i8));
9069 pshufbMask.push_back(DAG.getConstant(0xc, MVT::i8));
9070 pshufbMask.push_back(DAG.getConstant(0xd, MVT::i8));
9071 for (unsigned j = 0; j < 8; ++j)
9072 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
9074 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8,
9075 &pshufbMask[0], 32);
9076 In = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v32i8, In, BV);
9077 In = DAG.getNode(ISD::BITCAST, DL, MVT::v4i64, In);
9079 static const int ShufMask[] = {0, 2, -1, -1};
9080 In = DAG.getVectorShuffle(MVT::v4i64, DL, In, DAG.getUNDEF(MVT::v4i64),
9082 In = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
9083 DAG.getIntPtrConstant(0));
9084 return DAG.getNode(ISD::BITCAST, DL, VT, In);
9087 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
9088 DAG.getIntPtrConstant(0));
9090 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
9091 DAG.getIntPtrConstant(4));
9093 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpLo);
9094 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpHi);
9097 static const int ShufMask1[] = {0, 1, 4, 5, 8, 9, 12, 13,
9098 -1, -1, -1, -1, -1, -1, -1, -1};
9100 SDValue Undef = DAG.getUNDEF(MVT::v16i8);
9101 OpLo = DAG.getVectorShuffle(MVT::v16i8, DL, OpLo, Undef, ShufMask1);
9102 OpHi = DAG.getVectorShuffle(MVT::v16i8, DL, OpHi, Undef, ShufMask1);
9104 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo);
9105 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi);
9107 // The MOVLHPS Mask:
9108 static const int ShufMask2[] = {0, 1, 4, 5};
9109 SDValue res = DAG.getVectorShuffle(MVT::v4i32, DL, OpLo, OpHi, ShufMask2);
9110 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, res);
9113 // Handle truncation of V256 to V128 using shuffles.
9114 if (!VT.is128BitVector() || !InVT.is256BitVector())
9117 assert(Subtarget->hasFp256() && "256-bit vector without AVX!");
9119 unsigned NumElems = VT.getVectorNumElements();
9120 EVT NVT = EVT::getVectorVT(*DAG.getContext(), VT.getVectorElementType(),
9123 SmallVector<int, 16> MaskVec(NumElems * 2, -1);
9124 // Prepare truncation shuffle mask
9125 for (unsigned i = 0; i != NumElems; ++i)
9127 SDValue V = DAG.getVectorShuffle(NVT, DL,
9128 DAG.getNode(ISD::BITCAST, DL, NVT, In),
9129 DAG.getUNDEF(NVT), &MaskVec[0]);
9130 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, V,
9131 DAG.getIntPtrConstant(0));
9134 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op,
9135 SelectionDAG &DAG) const {
9136 MVT VT = Op.getSimpleValueType();
9137 if (VT.isVector()) {
9138 if (VT == MVT::v8i16)
9139 return DAG.getNode(ISD::TRUNCATE, SDLoc(Op), VT,
9140 DAG.getNode(ISD::FP_TO_SINT, SDLoc(Op),
9141 MVT::v8i32, Op.getOperand(0)));
9145 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
9146 /*IsSigned=*/ true, /*IsReplace=*/ false);
9147 SDValue FIST = Vals.first, StackSlot = Vals.second;
9148 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
9149 if (FIST.getNode() == 0) return Op;
9151 if (StackSlot.getNode())
9153 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
9154 FIST, StackSlot, MachinePointerInfo(),
9155 false, false, false, 0);
9157 // The node is the result.
9161 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op,
9162 SelectionDAG &DAG) const {
9163 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
9164 /*IsSigned=*/ false, /*IsReplace=*/ false);
9165 SDValue FIST = Vals.first, StackSlot = Vals.second;
9166 assert(FIST.getNode() && "Unexpected failure");
9168 if (StackSlot.getNode())
9170 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
9171 FIST, StackSlot, MachinePointerInfo(),
9172 false, false, false, 0);
9174 // The node is the result.
9178 static SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) {
9180 MVT VT = Op.getSimpleValueType();
9181 SDValue In = Op.getOperand(0);
9182 MVT SVT = In.getSimpleValueType();
9184 assert(SVT == MVT::v2f32 && "Only customize MVT::v2f32 type legalization!");
9186 return DAG.getNode(X86ISD::VFPEXT, DL, VT,
9187 DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v4f32,
9188 In, DAG.getUNDEF(SVT)));
9191 SDValue X86TargetLowering::LowerFABS(SDValue Op, SelectionDAG &DAG) const {
9192 LLVMContext *Context = DAG.getContext();
9194 MVT VT = Op.getSimpleValueType();
9196 unsigned NumElts = VT == MVT::f64 ? 2 : 4;
9197 if (VT.isVector()) {
9198 EltVT = VT.getVectorElementType();
9199 NumElts = VT.getVectorNumElements();
9202 if (EltVT == MVT::f64)
9203 C = ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
9204 APInt(64, ~(1ULL << 63))));
9206 C = ConstantFP::get(*Context, APFloat(APFloat::IEEEsingle,
9207 APInt(32, ~(1U << 31))));
9208 C = ConstantVector::getSplat(NumElts, C);
9209 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy());
9210 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
9211 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
9212 MachinePointerInfo::getConstantPool(),
9213 false, false, false, Alignment);
9214 if (VT.isVector()) {
9215 MVT ANDVT = VT.is128BitVector() ? MVT::v2i64 : MVT::v4i64;
9216 return DAG.getNode(ISD::BITCAST, dl, VT,
9217 DAG.getNode(ISD::AND, dl, ANDVT,
9218 DAG.getNode(ISD::BITCAST, dl, ANDVT,
9220 DAG.getNode(ISD::BITCAST, dl, ANDVT, Mask)));
9222 return DAG.getNode(X86ISD::FAND, dl, VT, Op.getOperand(0), Mask);
9225 SDValue X86TargetLowering::LowerFNEG(SDValue Op, SelectionDAG &DAG) const {
9226 LLVMContext *Context = DAG.getContext();
9228 MVT VT = Op.getSimpleValueType();
9230 unsigned NumElts = VT == MVT::f64 ? 2 : 4;
9231 if (VT.isVector()) {
9232 EltVT = VT.getVectorElementType();
9233 NumElts = VT.getVectorNumElements();
9236 if (EltVT == MVT::f64)
9237 C = ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
9238 APInt(64, 1ULL << 63)));
9240 C = ConstantFP::get(*Context, APFloat(APFloat::IEEEsingle,
9241 APInt(32, 1U << 31)));
9242 C = ConstantVector::getSplat(NumElts, C);
9243 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy());
9244 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
9245 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
9246 MachinePointerInfo::getConstantPool(),
9247 false, false, false, Alignment);
9248 if (VT.isVector()) {
9249 MVT XORVT = MVT::getVectorVT(MVT::i64, VT.getSizeInBits()/64);
9250 return DAG.getNode(ISD::BITCAST, dl, VT,
9251 DAG.getNode(ISD::XOR, dl, XORVT,
9252 DAG.getNode(ISD::BITCAST, dl, XORVT,
9254 DAG.getNode(ISD::BITCAST, dl, XORVT, Mask)));
9257 return DAG.getNode(X86ISD::FXOR, dl, VT, Op.getOperand(0), Mask);
9260 SDValue X86TargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {
9261 LLVMContext *Context = DAG.getContext();
9262 SDValue Op0 = Op.getOperand(0);
9263 SDValue Op1 = Op.getOperand(1);
9265 MVT VT = Op.getSimpleValueType();
9266 MVT SrcVT = Op1.getSimpleValueType();
9268 // If second operand is smaller, extend it first.
9269 if (SrcVT.bitsLT(VT)) {
9270 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
9273 // And if it is bigger, shrink it first.
9274 if (SrcVT.bitsGT(VT)) {
9275 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1));
9279 // At this point the operands and the result should have the same
9280 // type, and that won't be f80 since that is not custom lowered.
9282 // First get the sign bit of second operand.
9283 SmallVector<Constant*,4> CV;
9284 if (SrcVT == MVT::f64) {
9285 const fltSemantics &Sem = APFloat::IEEEdouble;
9286 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 1ULL << 63))));
9287 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 0))));
9289 const fltSemantics &Sem = APFloat::IEEEsingle;
9290 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 1U << 31))));
9291 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
9292 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
9293 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
9295 Constant *C = ConstantVector::get(CV);
9296 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
9297 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx,
9298 MachinePointerInfo::getConstantPool(),
9299 false, false, false, 16);
9300 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1);
9302 // Shift sign bit right or left if the two operands have different types.
9303 if (SrcVT.bitsGT(VT)) {
9304 // Op0 is MVT::f32, Op1 is MVT::f64.
9305 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, SignBit);
9306 SignBit = DAG.getNode(X86ISD::FSRL, dl, MVT::v2f64, SignBit,
9307 DAG.getConstant(32, MVT::i32));
9308 SignBit = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, SignBit);
9309 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, SignBit,
9310 DAG.getIntPtrConstant(0));
9313 // Clear first operand sign bit.
9315 if (VT == MVT::f64) {
9316 const fltSemantics &Sem = APFloat::IEEEdouble;
9317 CV.push_back(ConstantFP::get(*Context, APFloat(Sem,
9318 APInt(64, ~(1ULL << 63)))));
9319 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 0))));
9321 const fltSemantics &Sem = APFloat::IEEEsingle;
9322 CV.push_back(ConstantFP::get(*Context, APFloat(Sem,
9323 APInt(32, ~(1U << 31)))));
9324 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
9325 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
9326 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
9328 C = ConstantVector::get(CV);
9329 CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
9330 SDValue Mask2 = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
9331 MachinePointerInfo::getConstantPool(),
9332 false, false, false, 16);
9333 SDValue Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Mask2);
9335 // Or the value with the sign bit.
9336 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit);
9339 static SDValue LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) {
9340 SDValue N0 = Op.getOperand(0);
9342 MVT VT = Op.getSimpleValueType();
9344 // Lower ISD::FGETSIGN to (AND (X86ISD::FGETSIGNx86 ...) 1).
9345 SDValue xFGETSIGN = DAG.getNode(X86ISD::FGETSIGNx86, dl, VT, N0,
9346 DAG.getConstant(1, VT));
9347 return DAG.getNode(ISD::AND, dl, VT, xFGETSIGN, DAG.getConstant(1, VT));
9350 // LowerVectorAllZeroTest - Check whether an OR'd tree is PTEST-able.
9352 static SDValue LowerVectorAllZeroTest(SDValue Op, const X86Subtarget *Subtarget,
9353 SelectionDAG &DAG) {
9354 assert(Op.getOpcode() == ISD::OR && "Only check OR'd tree.");
9356 if (!Subtarget->hasSSE41())
9359 if (!Op->hasOneUse())
9362 SDNode *N = Op.getNode();
9365 SmallVector<SDValue, 8> Opnds;
9366 DenseMap<SDValue, unsigned> VecInMap;
9367 EVT VT = MVT::Other;
9369 // Recognize a special case where a vector is casted into wide integer to
9371 Opnds.push_back(N->getOperand(0));
9372 Opnds.push_back(N->getOperand(1));
9374 for (unsigned Slot = 0, e = Opnds.size(); Slot < e; ++Slot) {
9375 SmallVectorImpl<SDValue>::const_iterator I = Opnds.begin() + Slot;
9376 // BFS traverse all OR'd operands.
9377 if (I->getOpcode() == ISD::OR) {
9378 Opnds.push_back(I->getOperand(0));
9379 Opnds.push_back(I->getOperand(1));
9380 // Re-evaluate the number of nodes to be traversed.
9381 e += 2; // 2 more nodes (LHS and RHS) are pushed.
9385 // Quit if a non-EXTRACT_VECTOR_ELT
9386 if (I->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
9389 // Quit if without a constant index.
9390 SDValue Idx = I->getOperand(1);
9391 if (!isa<ConstantSDNode>(Idx))
9394 SDValue ExtractedFromVec = I->getOperand(0);
9395 DenseMap<SDValue, unsigned>::iterator M = VecInMap.find(ExtractedFromVec);
9396 if (M == VecInMap.end()) {
9397 VT = ExtractedFromVec.getValueType();
9398 // Quit if not 128/256-bit vector.
9399 if (!VT.is128BitVector() && !VT.is256BitVector())
9401 // Quit if not the same type.
9402 if (VecInMap.begin() != VecInMap.end() &&
9403 VT != VecInMap.begin()->first.getValueType())
9405 M = VecInMap.insert(std::make_pair(ExtractedFromVec, 0)).first;
9407 M->second |= 1U << cast<ConstantSDNode>(Idx)->getZExtValue();
9410 assert((VT.is128BitVector() || VT.is256BitVector()) &&
9411 "Not extracted from 128-/256-bit vector.");
9413 unsigned FullMask = (1U << VT.getVectorNumElements()) - 1U;
9414 SmallVector<SDValue, 8> VecIns;
9416 for (DenseMap<SDValue, unsigned>::const_iterator
9417 I = VecInMap.begin(), E = VecInMap.end(); I != E; ++I) {
9418 // Quit if not all elements are used.
9419 if (I->second != FullMask)
9421 VecIns.push_back(I->first);
9424 EVT TestVT = VT.is128BitVector() ? MVT::v2i64 : MVT::v4i64;
9426 // Cast all vectors into TestVT for PTEST.
9427 for (unsigned i = 0, e = VecIns.size(); i < e; ++i)
9428 VecIns[i] = DAG.getNode(ISD::BITCAST, DL, TestVT, VecIns[i]);
9430 // If more than one full vectors are evaluated, OR them first before PTEST.
9431 for (unsigned Slot = 0, e = VecIns.size(); e - Slot > 1; Slot += 2, e += 1) {
9432 // Each iteration will OR 2 nodes and append the result until there is only
9433 // 1 node left, i.e. the final OR'd value of all vectors.
9434 SDValue LHS = VecIns[Slot];
9435 SDValue RHS = VecIns[Slot + 1];
9436 VecIns.push_back(DAG.getNode(ISD::OR, DL, TestVT, LHS, RHS));
9439 return DAG.getNode(X86ISD::PTEST, DL, MVT::i32,
9440 VecIns.back(), VecIns.back());
9443 /// Emit nodes that will be selected as "test Op0,Op0", or something
9445 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC,
9446 SelectionDAG &DAG) const {
9449 // CF and OF aren't always set the way we want. Determine which
9450 // of these we need.
9451 bool NeedCF = false;
9452 bool NeedOF = false;
9455 case X86::COND_A: case X86::COND_AE:
9456 case X86::COND_B: case X86::COND_BE:
9459 case X86::COND_G: case X86::COND_GE:
9460 case X86::COND_L: case X86::COND_LE:
9461 case X86::COND_O: case X86::COND_NO:
9466 // See if we can use the EFLAGS value from the operand instead of
9467 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
9468 // we prove that the arithmetic won't overflow, we can't use OF or CF.
9469 if (Op.getResNo() != 0 || NeedOF || NeedCF)
9470 // Emit a CMP with 0, which is the TEST pattern.
9471 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
9472 DAG.getConstant(0, Op.getValueType()));
9474 unsigned Opcode = 0;
9475 unsigned NumOperands = 0;
9477 // Truncate operations may prevent the merge of the SETCC instruction
9478 // and the arithmetic instruction before it. Attempt to truncate the operands
9479 // of the arithmetic instruction and use a reduced bit-width instruction.
9480 bool NeedTruncation = false;
9481 SDValue ArithOp = Op;
9482 if (Op->getOpcode() == ISD::TRUNCATE && Op->hasOneUse()) {
9483 SDValue Arith = Op->getOperand(0);
9484 // Both the trunc and the arithmetic op need to have one user each.
9485 if (Arith->hasOneUse())
9486 switch (Arith.getOpcode()) {
9493 NeedTruncation = true;
9499 // NOTICE: In the code below we use ArithOp to hold the arithmetic operation
9500 // which may be the result of a CAST. We use the variable 'Op', which is the
9501 // non-casted variable when we check for possible users.
9502 switch (ArithOp.getOpcode()) {
9504 // Due to an isel shortcoming, be conservative if this add is likely to be
9505 // selected as part of a load-modify-store instruction. When the root node
9506 // in a match is a store, isel doesn't know how to remap non-chain non-flag
9507 // uses of other nodes in the match, such as the ADD in this case. This
9508 // leads to the ADD being left around and reselected, with the result being
9509 // two adds in the output. Alas, even if none our users are stores, that
9510 // doesn't prove we're O.K. Ergo, if we have any parents that aren't
9511 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require
9512 // climbing the DAG back to the root, and it doesn't seem to be worth the
9514 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
9515 UE = Op.getNode()->use_end(); UI != UE; ++UI)
9516 if (UI->getOpcode() != ISD::CopyToReg &&
9517 UI->getOpcode() != ISD::SETCC &&
9518 UI->getOpcode() != ISD::STORE)
9521 if (ConstantSDNode *C =
9522 dyn_cast<ConstantSDNode>(ArithOp.getNode()->getOperand(1))) {
9523 // An add of one will be selected as an INC.
9524 if (C->getAPIntValue() == 1) {
9525 Opcode = X86ISD::INC;
9530 // An add of negative one (subtract of one) will be selected as a DEC.
9531 if (C->getAPIntValue().isAllOnesValue()) {
9532 Opcode = X86ISD::DEC;
9538 // Otherwise use a regular EFLAGS-setting add.
9539 Opcode = X86ISD::ADD;
9543 // If the primary and result isn't used, don't bother using X86ISD::AND,
9544 // because a TEST instruction will be better.
9545 bool NonFlagUse = false;
9546 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
9547 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
9549 unsigned UOpNo = UI.getOperandNo();
9550 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
9551 // Look pass truncate.
9552 UOpNo = User->use_begin().getOperandNo();
9553 User = *User->use_begin();
9556 if (User->getOpcode() != ISD::BRCOND &&
9557 User->getOpcode() != ISD::SETCC &&
9558 !(User->getOpcode() == ISD::SELECT && UOpNo == 0)) {
9571 // Due to the ISEL shortcoming noted above, be conservative if this op is
9572 // likely to be selected as part of a load-modify-store instruction.
9573 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
9574 UE = Op.getNode()->use_end(); UI != UE; ++UI)
9575 if (UI->getOpcode() == ISD::STORE)
9578 // Otherwise use a regular EFLAGS-setting instruction.
9579 switch (ArithOp.getOpcode()) {
9580 default: llvm_unreachable("unexpected operator!");
9581 case ISD::SUB: Opcode = X86ISD::SUB; break;
9582 case ISD::XOR: Opcode = X86ISD::XOR; break;
9583 case ISD::AND: Opcode = X86ISD::AND; break;
9585 if (!NeedTruncation && (X86CC == X86::COND_E || X86CC == X86::COND_NE)) {
9586 SDValue EFLAGS = LowerVectorAllZeroTest(Op, Subtarget, DAG);
9587 if (EFLAGS.getNode())
9590 Opcode = X86ISD::OR;
9604 return SDValue(Op.getNode(), 1);
9610 // If we found that truncation is beneficial, perform the truncation and
9612 if (NeedTruncation) {
9613 EVT VT = Op.getValueType();
9614 SDValue WideVal = Op->getOperand(0);
9615 EVT WideVT = WideVal.getValueType();
9616 unsigned ConvertedOp = 0;
9617 // Use a target machine opcode to prevent further DAGCombine
9618 // optimizations that may separate the arithmetic operations
9619 // from the setcc node.
9620 switch (WideVal.getOpcode()) {
9622 case ISD::ADD: ConvertedOp = X86ISD::ADD; break;
9623 case ISD::SUB: ConvertedOp = X86ISD::SUB; break;
9624 case ISD::AND: ConvertedOp = X86ISD::AND; break;
9625 case ISD::OR: ConvertedOp = X86ISD::OR; break;
9626 case ISD::XOR: ConvertedOp = X86ISD::XOR; break;
9630 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
9631 if (TLI.isOperationLegal(WideVal.getOpcode(), WideVT)) {
9632 SDValue V0 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(0));
9633 SDValue V1 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(1));
9634 Op = DAG.getNode(ConvertedOp, dl, VT, V0, V1);
9640 // Emit a CMP with 0, which is the TEST pattern.
9641 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
9642 DAG.getConstant(0, Op.getValueType()));
9644 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
9645 SmallVector<SDValue, 4> Ops;
9646 for (unsigned i = 0; i != NumOperands; ++i)
9647 Ops.push_back(Op.getOperand(i));
9649 SDValue New = DAG.getNode(Opcode, dl, VTs, &Ops[0], NumOperands);
9650 DAG.ReplaceAllUsesWith(Op, New);
9651 return SDValue(New.getNode(), 1);
9654 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
9656 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
9657 SelectionDAG &DAG) const {
9658 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1))
9659 if (C->getAPIntValue() == 0)
9660 return EmitTest(Op0, X86CC, DAG);
9663 if ((Op0.getValueType() == MVT::i8 || Op0.getValueType() == MVT::i16 ||
9664 Op0.getValueType() == MVT::i32 || Op0.getValueType() == MVT::i64)) {
9665 // Use SUB instead of CMP to enable CSE between SUB and CMP.
9666 SDVTList VTs = DAG.getVTList(Op0.getValueType(), MVT::i32);
9667 SDValue Sub = DAG.getNode(X86ISD::SUB, dl, VTs,
9669 return SDValue(Sub.getNode(), 1);
9671 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
9674 /// Convert a comparison if required by the subtarget.
9675 SDValue X86TargetLowering::ConvertCmpIfNecessary(SDValue Cmp,
9676 SelectionDAG &DAG) const {
9677 // If the subtarget does not support the FUCOMI instruction, floating-point
9678 // comparisons have to be converted.
9679 if (Subtarget->hasCMov() ||
9680 Cmp.getOpcode() != X86ISD::CMP ||
9681 !Cmp.getOperand(0).getValueType().isFloatingPoint() ||
9682 !Cmp.getOperand(1).getValueType().isFloatingPoint())
9685 // The instruction selector will select an FUCOM instruction instead of
9686 // FUCOMI, which writes the comparison result to FPSW instead of EFLAGS. Hence
9687 // build an SDNode sequence that transfers the result from FPSW into EFLAGS:
9688 // (X86sahf (trunc (srl (X86fp_stsw (trunc (X86cmp ...)), 8))))
9690 SDValue TruncFPSW = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, Cmp);
9691 SDValue FNStSW = DAG.getNode(X86ISD::FNSTSW16r, dl, MVT::i16, TruncFPSW);
9692 SDValue Srl = DAG.getNode(ISD::SRL, dl, MVT::i16, FNStSW,
9693 DAG.getConstant(8, MVT::i8));
9694 SDValue TruncSrl = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Srl);
9695 return DAG.getNode(X86ISD::SAHF, dl, MVT::i32, TruncSrl);
9698 static bool isAllOnes(SDValue V) {
9699 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
9700 return C && C->isAllOnesValue();
9703 /// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node
9704 /// if it's possible.
9705 SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC,
9706 SDLoc dl, SelectionDAG &DAG) const {
9707 SDValue Op0 = And.getOperand(0);
9708 SDValue Op1 = And.getOperand(1);
9709 if (Op0.getOpcode() == ISD::TRUNCATE)
9710 Op0 = Op0.getOperand(0);
9711 if (Op1.getOpcode() == ISD::TRUNCATE)
9712 Op1 = Op1.getOperand(0);
9715 if (Op1.getOpcode() == ISD::SHL)
9716 std::swap(Op0, Op1);
9717 if (Op0.getOpcode() == ISD::SHL) {
9718 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0)))
9719 if (And00C->getZExtValue() == 1) {
9720 // If we looked past a truncate, check that it's only truncating away
9722 unsigned BitWidth = Op0.getValueSizeInBits();
9723 unsigned AndBitWidth = And.getValueSizeInBits();
9724 if (BitWidth > AndBitWidth) {
9726 DAG.ComputeMaskedBits(Op0, Zeros, Ones);
9727 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth)
9731 RHS = Op0.getOperand(1);
9733 } else if (Op1.getOpcode() == ISD::Constant) {
9734 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1);
9735 uint64_t AndRHSVal = AndRHS->getZExtValue();
9736 SDValue AndLHS = Op0;
9738 if (AndRHSVal == 1 && AndLHS.getOpcode() == ISD::SRL) {
9739 LHS = AndLHS.getOperand(0);
9740 RHS = AndLHS.getOperand(1);
9743 // Use BT if the immediate can't be encoded in a TEST instruction.
9744 if (!isUInt<32>(AndRHSVal) && isPowerOf2_64(AndRHSVal)) {
9746 RHS = DAG.getConstant(Log2_64_Ceil(AndRHSVal), LHS.getValueType());
9750 if (LHS.getNode()) {
9751 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT
9752 // instruction. Since the shift amount is in-range-or-undefined, we know
9753 // that doing a bittest on the i32 value is ok. We extend to i32 because
9754 // the encoding for the i16 version is larger than the i32 version.
9755 // Also promote i16 to i32 for performance / code size reason.
9756 if (LHS.getValueType() == MVT::i8 ||
9757 LHS.getValueType() == MVT::i16)
9758 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
9760 // If the operand types disagree, extend the shift amount to match. Since
9761 // BT ignores high bits (like shifts) we can use anyextend.
9762 if (LHS.getValueType() != RHS.getValueType())
9763 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
9765 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
9766 X86::CondCode Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
9767 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
9768 DAG.getConstant(Cond, MVT::i8), BT);
9774 /// \brief - Turns an ISD::CondCode into a value suitable for SSE floating point
9776 static int translateX86FSETCC(ISD::CondCode SetCCOpcode, SDValue &Op0,
9781 // SSE Condition code mapping:
9790 switch (SetCCOpcode) {
9791 default: llvm_unreachable("Unexpected SETCC condition");
9793 case ISD::SETEQ: SSECC = 0; break;
9795 case ISD::SETGT: Swap = true; // Fallthrough
9797 case ISD::SETOLT: SSECC = 1; break;
9799 case ISD::SETGE: Swap = true; // Fallthrough
9801 case ISD::SETOLE: SSECC = 2; break;
9802 case ISD::SETUO: SSECC = 3; break;
9804 case ISD::SETNE: SSECC = 4; break;
9805 case ISD::SETULE: Swap = true; // Fallthrough
9806 case ISD::SETUGE: SSECC = 5; break;
9807 case ISD::SETULT: Swap = true; // Fallthrough
9808 case ISD::SETUGT: SSECC = 6; break;
9809 case ISD::SETO: SSECC = 7; break;
9811 case ISD::SETONE: SSECC = 8; break;
9814 std::swap(Op0, Op1);
9819 // Lower256IntVSETCC - Break a VSETCC 256-bit integer VSETCC into two new 128
9820 // ones, and then concatenate the result back.
9821 static SDValue Lower256IntVSETCC(SDValue Op, SelectionDAG &DAG) {
9822 MVT VT = Op.getSimpleValueType();
9824 assert(VT.is256BitVector() && Op.getOpcode() == ISD::SETCC &&
9825 "Unsupported value type for operation");
9827 unsigned NumElems = VT.getVectorNumElements();
9829 SDValue CC = Op.getOperand(2);
9831 // Extract the LHS vectors
9832 SDValue LHS = Op.getOperand(0);
9833 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
9834 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
9836 // Extract the RHS vectors
9837 SDValue RHS = Op.getOperand(1);
9838 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
9839 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
9841 // Issue the operation on the smaller types and concatenate the result back
9842 MVT EltVT = VT.getVectorElementType();
9843 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
9844 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
9845 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1, CC),
9846 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC));
9849 static SDValue LowerIntVSETCC_AVX512(SDValue Op, SelectionDAG &DAG) {
9850 SDValue Op0 = Op.getOperand(0);
9851 SDValue Op1 = Op.getOperand(1);
9852 SDValue CC = Op.getOperand(2);
9853 MVT VT = Op.getSimpleValueType();
9855 assert(Op0.getValueType().getVectorElementType().getSizeInBits() >= 32 &&
9856 Op.getValueType().getScalarType() == MVT::i1 &&
9857 "Cannot set masked compare for this operation");
9859 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
9862 bool Unsigned = false;
9864 switch (SetCCOpcode) {
9865 default: llvm_unreachable("Unexpected SETCC condition");
9866 case ISD::SETNE: SSECC = 4; break;
9867 case ISD::SETEQ: SSECC = 0; break;
9868 case ISD::SETUGT: Unsigned = true;
9869 case ISD::SETGT: SSECC = 6; break; // NLE
9870 case ISD::SETULT: Unsigned = true;
9871 case ISD::SETLT: SSECC = 1; break;
9872 case ISD::SETUGE: Unsigned = true;
9873 case ISD::SETGE: SSECC = 5; break; // NLT
9874 case ISD::SETULE: Unsigned = true;
9875 case ISD::SETLE: SSECC = 2; break;
9877 unsigned Opc = Unsigned ? X86ISD::CMPMU: X86ISD::CMPM;
9878 return DAG.getNode(Opc, dl, VT, Op0, Op1,
9879 DAG.getConstant(SSECC, MVT::i8));
9883 static SDValue LowerVSETCC(SDValue Op, const X86Subtarget *Subtarget,
9884 SelectionDAG &DAG) {
9885 SDValue Op0 = Op.getOperand(0);
9886 SDValue Op1 = Op.getOperand(1);
9887 SDValue CC = Op.getOperand(2);
9888 MVT VT = Op.getSimpleValueType();
9889 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
9890 bool isFP = Op.getOperand(1).getSimpleValueType().isFloatingPoint();
9895 MVT EltVT = Op0.getSimpleValueType().getVectorElementType();
9896 assert(EltVT == MVT::f32 || EltVT == MVT::f64);
9899 unsigned SSECC = translateX86FSETCC(SetCCOpcode, Op0, Op1);
9900 unsigned Opc = X86ISD::CMPP;
9901 if (Subtarget->hasAVX512() && VT.getVectorElementType() == MVT::i1) {
9902 assert(VT.getVectorNumElements() <= 16);
9905 // In the two special cases we can't handle, emit two comparisons.
9908 unsigned CombineOpc;
9909 if (SetCCOpcode == ISD::SETUEQ) {
9910 CC0 = 3; CC1 = 0; CombineOpc = ISD::OR;
9912 assert(SetCCOpcode == ISD::SETONE);
9913 CC0 = 7; CC1 = 4; CombineOpc = ISD::AND;
9916 SDValue Cmp0 = DAG.getNode(Opc, dl, VT, Op0, Op1,
9917 DAG.getConstant(CC0, MVT::i8));
9918 SDValue Cmp1 = DAG.getNode(Opc, dl, VT, Op0, Op1,
9919 DAG.getConstant(CC1, MVT::i8));
9920 return DAG.getNode(CombineOpc, dl, VT, Cmp0, Cmp1);
9922 // Handle all other FP comparisons here.
9923 return DAG.getNode(Opc, dl, VT, Op0, Op1,
9924 DAG.getConstant(SSECC, MVT::i8));
9927 // Break 256-bit integer vector compare into smaller ones.
9928 if (VT.is256BitVector() && !Subtarget->hasInt256())
9929 return Lower256IntVSETCC(Op, DAG);
9931 bool MaskResult = (VT.getVectorElementType() == MVT::i1);
9932 EVT OpVT = Op1.getValueType();
9933 if (Subtarget->hasAVX512()) {
9934 if (Op1.getValueType().is512BitVector() ||
9935 (MaskResult && OpVT.getVectorElementType().getSizeInBits() >= 32))
9936 return LowerIntVSETCC_AVX512(Op, DAG);
9938 // In AVX-512 architecture setcc returns mask with i1 elements,
9939 // But there is no compare instruction for i8 and i16 elements.
9940 // We are not talking about 512-bit operands in this case, these
9941 // types are illegal.
9943 (OpVT.getVectorElementType().getSizeInBits() < 32 &&
9944 OpVT.getVectorElementType().getSizeInBits() >= 8))
9945 return DAG.getNode(ISD::TRUNCATE, dl, VT,
9946 DAG.getNode(ISD::SETCC, dl, OpVT, Op0, Op1, CC));
9949 // We are handling one of the integer comparisons here. Since SSE only has
9950 // GT and EQ comparisons for integer, swapping operands and multiple
9951 // operations may be required for some comparisons.
9953 bool Swap = false, Invert = false, FlipSigns = false, MinMax = false;
9955 switch (SetCCOpcode) {
9956 default: llvm_unreachable("Unexpected SETCC condition");
9957 case ISD::SETNE: Invert = true;
9958 case ISD::SETEQ: Opc = MaskResult? X86ISD::PCMPEQM: X86ISD::PCMPEQ; break;
9959 case ISD::SETLT: Swap = true;
9960 case ISD::SETGT: Opc = MaskResult? X86ISD::PCMPGTM: X86ISD::PCMPGT; break;
9961 case ISD::SETGE: Swap = true;
9962 case ISD::SETLE: Opc = MaskResult? X86ISD::PCMPGTM: X86ISD::PCMPGT;
9963 Invert = true; break;
9964 case ISD::SETULT: Swap = true;
9965 case ISD::SETUGT: Opc = MaskResult? X86ISD::PCMPGTM: X86ISD::PCMPGT;
9966 FlipSigns = true; break;
9967 case ISD::SETUGE: Swap = true;
9968 case ISD::SETULE: Opc = MaskResult? X86ISD::PCMPGTM: X86ISD::PCMPGT;
9969 FlipSigns = true; Invert = true; break;
9972 // Special case: Use min/max operations for SETULE/SETUGE
9973 MVT VET = VT.getVectorElementType();
9975 (Subtarget->hasSSE41() && (VET >= MVT::i8 && VET <= MVT::i32))
9976 || (Subtarget->hasSSE2() && (VET == MVT::i8));
9979 switch (SetCCOpcode) {
9981 case ISD::SETULE: Opc = X86ISD::UMIN; MinMax = true; break;
9982 case ISD::SETUGE: Opc = X86ISD::UMAX; MinMax = true; break;
9985 if (MinMax) { Swap = false; Invert = false; FlipSigns = false; }
9989 std::swap(Op0, Op1);
9991 // Check that the operation in question is available (most are plain SSE2,
9992 // but PCMPGTQ and PCMPEQQ have different requirements).
9993 if (VT == MVT::v2i64) {
9994 if (Opc == X86ISD::PCMPGT && !Subtarget->hasSSE42()) {
9995 assert(Subtarget->hasSSE2() && "Don't know how to lower!");
9997 // First cast everything to the right type.
9998 Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0);
9999 Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1);
10001 // Since SSE has no unsigned integer comparisons, we need to flip the sign
10002 // bits of the inputs before performing those operations. The lower
10003 // compare is always unsigned.
10006 SB = DAG.getConstant(0x80000000U, MVT::v4i32);
10008 SDValue Sign = DAG.getConstant(0x80000000U, MVT::i32);
10009 SDValue Zero = DAG.getConstant(0x00000000U, MVT::i32);
10010 SB = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
10011 Sign, Zero, Sign, Zero);
10013 Op0 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op0, SB);
10014 Op1 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op1, SB);
10016 // Emulate PCMPGTQ with (hi1 > hi2) | ((hi1 == hi2) & (lo1 > lo2))
10017 SDValue GT = DAG.getNode(X86ISD::PCMPGT, dl, MVT::v4i32, Op0, Op1);
10018 SDValue EQ = DAG.getNode(X86ISD::PCMPEQ, dl, MVT::v4i32, Op0, Op1);
10020 // Create masks for only the low parts/high parts of the 64 bit integers.
10021 static const int MaskHi[] = { 1, 1, 3, 3 };
10022 static const int MaskLo[] = { 0, 0, 2, 2 };
10023 SDValue EQHi = DAG.getVectorShuffle(MVT::v4i32, dl, EQ, EQ, MaskHi);
10024 SDValue GTLo = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskLo);
10025 SDValue GTHi = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskHi);
10027 SDValue Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, EQHi, GTLo);
10028 Result = DAG.getNode(ISD::OR, dl, MVT::v4i32, Result, GTHi);
10031 Result = DAG.getNOT(dl, Result, MVT::v4i32);
10033 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
10036 if (Opc == X86ISD::PCMPEQ && !Subtarget->hasSSE41()) {
10037 // If pcmpeqq is missing but pcmpeqd is available synthesize pcmpeqq with
10038 // pcmpeqd + pshufd + pand.
10039 assert(Subtarget->hasSSE2() && !FlipSigns && "Don't know how to lower!");
10041 // First cast everything to the right type.
10042 Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0);
10043 Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1);
10046 SDValue Result = DAG.getNode(Opc, dl, MVT::v4i32, Op0, Op1);
10048 // Make sure the lower and upper halves are both all-ones.
10049 static const int Mask[] = { 1, 0, 3, 2 };
10050 SDValue Shuf = DAG.getVectorShuffle(MVT::v4i32, dl, Result, Result, Mask);
10051 Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, Result, Shuf);
10054 Result = DAG.getNOT(dl, Result, MVT::v4i32);
10056 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
10060 // Since SSE has no unsigned integer comparisons, we need to flip the sign
10061 // bits of the inputs before performing those operations.
10063 EVT EltVT = VT.getVectorElementType();
10064 SDValue SB = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()), VT);
10065 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SB);
10066 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SB);
10069 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
10071 // If the logical-not of the result is required, perform that now.
10073 Result = DAG.getNOT(dl, Result, VT);
10076 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Op0, Result);
10081 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
10083 MVT VT = Op.getSimpleValueType();
10085 if (VT.isVector()) return LowerVSETCC(Op, Subtarget, DAG);
10087 assert(VT == MVT::i8 && "SetCC type must be 8-bit integer");
10088 SDValue Op0 = Op.getOperand(0);
10089 SDValue Op1 = Op.getOperand(1);
10091 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
10093 // Optimize to BT if possible.
10094 // Lower (X & (1 << N)) == 0 to BT(X, N).
10095 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
10096 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
10097 if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() &&
10098 Op1.getOpcode() == ISD::Constant &&
10099 cast<ConstantSDNode>(Op1)->isNullValue() &&
10100 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
10101 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG);
10102 if (NewSetCC.getNode())
10106 // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of
10108 if (Op1.getOpcode() == ISD::Constant &&
10109 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 ||
10110 cast<ConstantSDNode>(Op1)->isNullValue()) &&
10111 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
10113 // If the input is a setcc, then reuse the input setcc or use a new one with
10114 // the inverted condition.
10115 if (Op0.getOpcode() == X86ISD::SETCC) {
10116 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0);
10117 bool Invert = (CC == ISD::SETNE) ^
10118 cast<ConstantSDNode>(Op1)->isNullValue();
10119 if (!Invert) return Op0;
10121 CCode = X86::GetOppositeBranchCondition(CCode);
10122 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
10123 DAG.getConstant(CCode, MVT::i8), Op0.getOperand(1));
10127 bool isFP = Op1.getSimpleValueType().isFloatingPoint();
10128 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG);
10129 if (X86CC == X86::COND_INVALID)
10132 SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, DAG);
10133 EFLAGS = ConvertCmpIfNecessary(EFLAGS, DAG);
10134 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
10135 DAG.getConstant(X86CC, MVT::i8), EFLAGS);
10138 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
10139 static bool isX86LogicalCmp(SDValue Op) {
10140 unsigned Opc = Op.getNode()->getOpcode();
10141 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI ||
10142 Opc == X86ISD::SAHF)
10144 if (Op.getResNo() == 1 &&
10145 (Opc == X86ISD::ADD ||
10146 Opc == X86ISD::SUB ||
10147 Opc == X86ISD::ADC ||
10148 Opc == X86ISD::SBB ||
10149 Opc == X86ISD::SMUL ||
10150 Opc == X86ISD::UMUL ||
10151 Opc == X86ISD::INC ||
10152 Opc == X86ISD::DEC ||
10153 Opc == X86ISD::OR ||
10154 Opc == X86ISD::XOR ||
10155 Opc == X86ISD::AND))
10158 if (Op.getResNo() == 2 && Opc == X86ISD::UMUL)
10164 static bool isZero(SDValue V) {
10165 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
10166 return C && C->isNullValue();
10169 static bool isTruncWithZeroHighBitsInput(SDValue V, SelectionDAG &DAG) {
10170 if (V.getOpcode() != ISD::TRUNCATE)
10173 SDValue VOp0 = V.getOperand(0);
10174 unsigned InBits = VOp0.getValueSizeInBits();
10175 unsigned Bits = V.getValueSizeInBits();
10176 return DAG.MaskedValueIsZero(VOp0, APInt::getHighBitsSet(InBits,InBits-Bits));
10179 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
10180 bool addTest = true;
10181 SDValue Cond = Op.getOperand(0);
10182 SDValue Op1 = Op.getOperand(1);
10183 SDValue Op2 = Op.getOperand(2);
10185 EVT VT = Op1.getValueType();
10188 // Lower fp selects into a CMP/AND/ANDN/OR sequence when the necessary SSE ops
10189 // are available. Otherwise fp cmovs get lowered into a less efficient branch
10190 // sequence later on.
10191 if (Cond.getOpcode() == ISD::SETCC &&
10192 ((Subtarget->hasSSE2() && (VT == MVT::f32 || VT == MVT::f64)) ||
10193 (Subtarget->hasSSE1() && VT == MVT::f32)) &&
10194 VT == Cond.getOperand(0).getValueType() && Cond->hasOneUse()) {
10195 SDValue CondOp0 = Cond.getOperand(0), CondOp1 = Cond.getOperand(1);
10196 int SSECC = translateX86FSETCC(
10197 cast<CondCodeSDNode>(Cond.getOperand(2))->get(), CondOp0, CondOp1);
10200 unsigned Opcode = VT == MVT::f32 ? X86ISD::FSETCCss : X86ISD::FSETCCsd;
10201 SDValue Cmp = DAG.getNode(Opcode, DL, VT, CondOp0, CondOp1,
10202 DAG.getConstant(SSECC, MVT::i8));
10203 SDValue AndN = DAG.getNode(X86ISD::FANDN, DL, VT, Cmp, Op2);
10204 SDValue And = DAG.getNode(X86ISD::FAND, DL, VT, Cmp, Op1);
10205 return DAG.getNode(X86ISD::FOR, DL, VT, AndN, And);
10209 if (Cond.getOpcode() == ISD::SETCC) {
10210 SDValue NewCond = LowerSETCC(Cond, DAG);
10211 if (NewCond.getNode())
10215 // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y
10216 // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y
10217 // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y
10218 // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y
10219 if (Cond.getOpcode() == X86ISD::SETCC &&
10220 Cond.getOperand(1).getOpcode() == X86ISD::CMP &&
10221 isZero(Cond.getOperand(1).getOperand(1))) {
10222 SDValue Cmp = Cond.getOperand(1);
10224 unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue();
10226 if ((isAllOnes(Op1) || isAllOnes(Op2)) &&
10227 (CondCode == X86::COND_E || CondCode == X86::COND_NE)) {
10228 SDValue Y = isAllOnes(Op2) ? Op1 : Op2;
10230 SDValue CmpOp0 = Cmp.getOperand(0);
10231 // Apply further optimizations for special cases
10232 // (select (x != 0), -1, 0) -> neg & sbb
10233 // (select (x == 0), 0, -1) -> neg & sbb
10234 if (ConstantSDNode *YC = dyn_cast<ConstantSDNode>(Y))
10235 if (YC->isNullValue() &&
10236 (isAllOnes(Op1) == (CondCode == X86::COND_NE))) {
10237 SDVTList VTs = DAG.getVTList(CmpOp0.getValueType(), MVT::i32);
10238 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, VTs,
10239 DAG.getConstant(0, CmpOp0.getValueType()),
10241 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
10242 DAG.getConstant(X86::COND_B, MVT::i8),
10243 SDValue(Neg.getNode(), 1));
10247 Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32,
10248 CmpOp0, DAG.getConstant(1, CmpOp0.getValueType()));
10249 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
10251 SDValue Res = // Res = 0 or -1.
10252 DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
10253 DAG.getConstant(X86::COND_B, MVT::i8), Cmp);
10255 if (isAllOnes(Op1) != (CondCode == X86::COND_E))
10256 Res = DAG.getNOT(DL, Res, Res.getValueType());
10258 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2);
10259 if (N2C == 0 || !N2C->isNullValue())
10260 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y);
10265 // Look past (and (setcc_carry (cmp ...)), 1).
10266 if (Cond.getOpcode() == ISD::AND &&
10267 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
10268 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
10269 if (C && C->getAPIntValue() == 1)
10270 Cond = Cond.getOperand(0);
10273 // If condition flag is set by a X86ISD::CMP, then use it as the condition
10274 // setting operand in place of the X86ISD::SETCC.
10275 unsigned CondOpcode = Cond.getOpcode();
10276 if (CondOpcode == X86ISD::SETCC ||
10277 CondOpcode == X86ISD::SETCC_CARRY) {
10278 CC = Cond.getOperand(0);
10280 SDValue Cmp = Cond.getOperand(1);
10281 unsigned Opc = Cmp.getOpcode();
10282 MVT VT = Op.getSimpleValueType();
10284 bool IllegalFPCMov = false;
10285 if (VT.isFloatingPoint() && !VT.isVector() &&
10286 !isScalarFPTypeInSSEReg(VT)) // FPStack?
10287 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
10289 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
10290 Opc == X86ISD::BT) { // FIXME
10294 } else if (CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
10295 CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
10296 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
10297 Cond.getOperand(0).getValueType() != MVT::i8)) {
10298 SDValue LHS = Cond.getOperand(0);
10299 SDValue RHS = Cond.getOperand(1);
10300 unsigned X86Opcode;
10303 switch (CondOpcode) {
10304 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
10305 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
10306 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
10307 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
10308 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
10309 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
10310 default: llvm_unreachable("unexpected overflowing operator");
10312 if (CondOpcode == ISD::UMULO)
10313 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
10316 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
10318 SDValue X86Op = DAG.getNode(X86Opcode, DL, VTs, LHS, RHS);
10320 if (CondOpcode == ISD::UMULO)
10321 Cond = X86Op.getValue(2);
10323 Cond = X86Op.getValue(1);
10325 CC = DAG.getConstant(X86Cond, MVT::i8);
10330 // Look pass the truncate if the high bits are known zero.
10331 if (isTruncWithZeroHighBitsInput(Cond, DAG))
10332 Cond = Cond.getOperand(0);
10334 // We know the result of AND is compared against zero. Try to match
10336 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
10337 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG);
10338 if (NewSetCC.getNode()) {
10339 CC = NewSetCC.getOperand(0);
10340 Cond = NewSetCC.getOperand(1);
10347 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
10348 Cond = EmitTest(Cond, X86::COND_NE, DAG);
10351 // a < b ? -1 : 0 -> RES = ~setcc_carry
10352 // a < b ? 0 : -1 -> RES = setcc_carry
10353 // a >= b ? -1 : 0 -> RES = setcc_carry
10354 // a >= b ? 0 : -1 -> RES = ~setcc_carry
10355 if (Cond.getOpcode() == X86ISD::SUB) {
10356 Cond = ConvertCmpIfNecessary(Cond, DAG);
10357 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue();
10359 if ((CondCode == X86::COND_AE || CondCode == X86::COND_B) &&
10360 (isAllOnes(Op1) || isAllOnes(Op2)) && (isZero(Op1) || isZero(Op2))) {
10361 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
10362 DAG.getConstant(X86::COND_B, MVT::i8), Cond);
10363 if (isAllOnes(Op1) != (CondCode == X86::COND_B))
10364 return DAG.getNOT(DL, Res, Res.getValueType());
10369 // X86 doesn't have an i8 cmov. If both operands are the result of a truncate
10370 // widen the cmov and push the truncate through. This avoids introducing a new
10371 // branch during isel and doesn't add any extensions.
10372 if (Op.getValueType() == MVT::i8 &&
10373 Op1.getOpcode() == ISD::TRUNCATE && Op2.getOpcode() == ISD::TRUNCATE) {
10374 SDValue T1 = Op1.getOperand(0), T2 = Op2.getOperand(0);
10375 if (T1.getValueType() == T2.getValueType() &&
10376 // Blacklist CopyFromReg to avoid partial register stalls.
10377 T1.getOpcode() != ISD::CopyFromReg && T2.getOpcode()!=ISD::CopyFromReg){
10378 SDVTList VTs = DAG.getVTList(T1.getValueType(), MVT::Glue);
10379 SDValue Cmov = DAG.getNode(X86ISD::CMOV, DL, VTs, T2, T1, CC, Cond);
10380 return DAG.getNode(ISD::TRUNCATE, DL, Op.getValueType(), Cmov);
10384 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
10385 // condition is true.
10386 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
10387 SDValue Ops[] = { Op2, Op1, CC, Cond };
10388 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops, array_lengthof(Ops));
10391 static SDValue LowerSIGN_EXTEND_AVX512(SDValue Op, SelectionDAG &DAG) {
10392 MVT VT = Op->getSimpleValueType(0);
10393 SDValue In = Op->getOperand(0);
10394 MVT InVT = In.getSimpleValueType();
10397 unsigned int NumElts = VT.getVectorNumElements();
10398 if (NumElts != 8 && NumElts != 16)
10401 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1)
10402 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
10404 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
10405 assert (InVT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
10407 MVT ExtVT = (NumElts == 8) ? MVT::v8i64 : MVT::v16i32;
10408 Constant *C = ConstantInt::get(*DAG.getContext(),
10409 APInt::getAllOnesValue(ExtVT.getScalarType().getSizeInBits()));
10411 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
10412 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
10413 SDValue Ld = DAG.getLoad(ExtVT.getScalarType(), dl, DAG.getEntryNode(), CP,
10414 MachinePointerInfo::getConstantPool(),
10415 false, false, false, Alignment);
10416 SDValue Brcst = DAG.getNode(X86ISD::VBROADCASTM, dl, ExtVT, In, Ld);
10417 if (VT.is512BitVector())
10419 return DAG.getNode(X86ISD::VTRUNC, dl, VT, Brcst);
10422 static SDValue LowerSIGN_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
10423 SelectionDAG &DAG) {
10424 MVT VT = Op->getSimpleValueType(0);
10425 SDValue In = Op->getOperand(0);
10426 MVT InVT = In.getSimpleValueType();
10429 if (VT.is512BitVector() || InVT.getVectorElementType() == MVT::i1)
10430 return LowerSIGN_EXTEND_AVX512(Op, DAG);
10432 if ((VT != MVT::v4i64 || InVT != MVT::v4i32) &&
10433 (VT != MVT::v8i32 || InVT != MVT::v8i16) &&
10434 (VT != MVT::v16i16 || InVT != MVT::v16i8))
10437 if (Subtarget->hasInt256())
10438 return DAG.getNode(X86ISD::VSEXT_MOVL, dl, VT, In);
10440 // Optimize vectors in AVX mode
10441 // Sign extend v8i16 to v8i32 and
10444 // Divide input vector into two parts
10445 // for v4i32 the shuffle mask will be { 0, 1, -1, -1} {2, 3, -1, -1}
10446 // use vpmovsx instruction to extend v4i32 -> v2i64; v8i16 -> v4i32
10447 // concat the vectors to original VT
10449 unsigned NumElems = InVT.getVectorNumElements();
10450 SDValue Undef = DAG.getUNDEF(InVT);
10452 SmallVector<int,8> ShufMask1(NumElems, -1);
10453 for (unsigned i = 0; i != NumElems/2; ++i)
10456 SDValue OpLo = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask1[0]);
10458 SmallVector<int,8> ShufMask2(NumElems, -1);
10459 for (unsigned i = 0; i != NumElems/2; ++i)
10460 ShufMask2[i] = i + NumElems/2;
10462 SDValue OpHi = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask2[0]);
10464 MVT HalfVT = MVT::getVectorVT(VT.getScalarType(),
10465 VT.getVectorNumElements()/2);
10467 OpLo = DAG.getNode(X86ISD::VSEXT_MOVL, dl, HalfVT, OpLo);
10468 OpHi = DAG.getNode(X86ISD::VSEXT_MOVL, dl, HalfVT, OpHi);
10470 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
10473 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
10474 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
10475 // from the AND / OR.
10476 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
10477 Opc = Op.getOpcode();
10478 if (Opc != ISD::OR && Opc != ISD::AND)
10480 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
10481 Op.getOperand(0).hasOneUse() &&
10482 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
10483 Op.getOperand(1).hasOneUse());
10486 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
10487 // 1 and that the SETCC node has a single use.
10488 static bool isXor1OfSetCC(SDValue Op) {
10489 if (Op.getOpcode() != ISD::XOR)
10491 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
10492 if (N1C && N1C->getAPIntValue() == 1) {
10493 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
10494 Op.getOperand(0).hasOneUse();
10499 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
10500 bool addTest = true;
10501 SDValue Chain = Op.getOperand(0);
10502 SDValue Cond = Op.getOperand(1);
10503 SDValue Dest = Op.getOperand(2);
10506 bool Inverted = false;
10508 if (Cond.getOpcode() == ISD::SETCC) {
10509 // Check for setcc([su]{add,sub,mul}o == 0).
10510 if (cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETEQ &&
10511 isa<ConstantSDNode>(Cond.getOperand(1)) &&
10512 cast<ConstantSDNode>(Cond.getOperand(1))->isNullValue() &&
10513 Cond.getOperand(0).getResNo() == 1 &&
10514 (Cond.getOperand(0).getOpcode() == ISD::SADDO ||
10515 Cond.getOperand(0).getOpcode() == ISD::UADDO ||
10516 Cond.getOperand(0).getOpcode() == ISD::SSUBO ||
10517 Cond.getOperand(0).getOpcode() == ISD::USUBO ||
10518 Cond.getOperand(0).getOpcode() == ISD::SMULO ||
10519 Cond.getOperand(0).getOpcode() == ISD::UMULO)) {
10521 Cond = Cond.getOperand(0);
10523 SDValue NewCond = LowerSETCC(Cond, DAG);
10524 if (NewCond.getNode())
10529 // FIXME: LowerXALUO doesn't handle these!!
10530 else if (Cond.getOpcode() == X86ISD::ADD ||
10531 Cond.getOpcode() == X86ISD::SUB ||
10532 Cond.getOpcode() == X86ISD::SMUL ||
10533 Cond.getOpcode() == X86ISD::UMUL)
10534 Cond = LowerXALUO(Cond, DAG);
10537 // Look pass (and (setcc_carry (cmp ...)), 1).
10538 if (Cond.getOpcode() == ISD::AND &&
10539 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
10540 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
10541 if (C && C->getAPIntValue() == 1)
10542 Cond = Cond.getOperand(0);
10545 // If condition flag is set by a X86ISD::CMP, then use it as the condition
10546 // setting operand in place of the X86ISD::SETCC.
10547 unsigned CondOpcode = Cond.getOpcode();
10548 if (CondOpcode == X86ISD::SETCC ||
10549 CondOpcode == X86ISD::SETCC_CARRY) {
10550 CC = Cond.getOperand(0);
10552 SDValue Cmp = Cond.getOperand(1);
10553 unsigned Opc = Cmp.getOpcode();
10554 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
10555 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
10559 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
10563 // These can only come from an arithmetic instruction with overflow,
10564 // e.g. SADDO, UADDO.
10565 Cond = Cond.getNode()->getOperand(1);
10571 CondOpcode = Cond.getOpcode();
10572 if (CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
10573 CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
10574 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
10575 Cond.getOperand(0).getValueType() != MVT::i8)) {
10576 SDValue LHS = Cond.getOperand(0);
10577 SDValue RHS = Cond.getOperand(1);
10578 unsigned X86Opcode;
10581 switch (CondOpcode) {
10582 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
10583 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
10584 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
10585 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
10586 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
10587 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
10588 default: llvm_unreachable("unexpected overflowing operator");
10591 X86Cond = X86::GetOppositeBranchCondition((X86::CondCode)X86Cond);
10592 if (CondOpcode == ISD::UMULO)
10593 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
10596 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
10598 SDValue X86Op = DAG.getNode(X86Opcode, dl, VTs, LHS, RHS);
10600 if (CondOpcode == ISD::UMULO)
10601 Cond = X86Op.getValue(2);
10603 Cond = X86Op.getValue(1);
10605 CC = DAG.getConstant(X86Cond, MVT::i8);
10609 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
10610 SDValue Cmp = Cond.getOperand(0).getOperand(1);
10611 if (CondOpc == ISD::OR) {
10612 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
10613 // two branches instead of an explicit OR instruction with a
10615 if (Cmp == Cond.getOperand(1).getOperand(1) &&
10616 isX86LogicalCmp(Cmp)) {
10617 CC = Cond.getOperand(0).getOperand(0);
10618 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
10619 Chain, Dest, CC, Cmp);
10620 CC = Cond.getOperand(1).getOperand(0);
10624 } else { // ISD::AND
10625 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
10626 // two branches instead of an explicit AND instruction with a
10627 // separate test. However, we only do this if this block doesn't
10628 // have a fall-through edge, because this requires an explicit
10629 // jmp when the condition is false.
10630 if (Cmp == Cond.getOperand(1).getOperand(1) &&
10631 isX86LogicalCmp(Cmp) &&
10632 Op.getNode()->hasOneUse()) {
10633 X86::CondCode CCode =
10634 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
10635 CCode = X86::GetOppositeBranchCondition(CCode);
10636 CC = DAG.getConstant(CCode, MVT::i8);
10637 SDNode *User = *Op.getNode()->use_begin();
10638 // Look for an unconditional branch following this conditional branch.
10639 // We need this because we need to reverse the successors in order
10640 // to implement FCMP_OEQ.
10641 if (User->getOpcode() == ISD::BR) {
10642 SDValue FalseBB = User->getOperand(1);
10644 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
10645 assert(NewBR == User);
10649 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
10650 Chain, Dest, CC, Cmp);
10651 X86::CondCode CCode =
10652 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
10653 CCode = X86::GetOppositeBranchCondition(CCode);
10654 CC = DAG.getConstant(CCode, MVT::i8);
10660 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
10661 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
10662 // It should be transformed during dag combiner except when the condition
10663 // is set by a arithmetics with overflow node.
10664 X86::CondCode CCode =
10665 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
10666 CCode = X86::GetOppositeBranchCondition(CCode);
10667 CC = DAG.getConstant(CCode, MVT::i8);
10668 Cond = Cond.getOperand(0).getOperand(1);
10670 } else if (Cond.getOpcode() == ISD::SETCC &&
10671 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETOEQ) {
10672 // For FCMP_OEQ, we can emit
10673 // two branches instead of an explicit AND instruction with a
10674 // separate test. However, we only do this if this block doesn't
10675 // have a fall-through edge, because this requires an explicit
10676 // jmp when the condition is false.
10677 if (Op.getNode()->hasOneUse()) {
10678 SDNode *User = *Op.getNode()->use_begin();
10679 // Look for an unconditional branch following this conditional branch.
10680 // We need this because we need to reverse the successors in order
10681 // to implement FCMP_OEQ.
10682 if (User->getOpcode() == ISD::BR) {
10683 SDValue FalseBB = User->getOperand(1);
10685 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
10686 assert(NewBR == User);
10690 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
10691 Cond.getOperand(0), Cond.getOperand(1));
10692 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
10693 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
10694 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
10695 Chain, Dest, CC, Cmp);
10696 CC = DAG.getConstant(X86::COND_P, MVT::i8);
10701 } else if (Cond.getOpcode() == ISD::SETCC &&
10702 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETUNE) {
10703 // For FCMP_UNE, we can emit
10704 // two branches instead of an explicit AND instruction with a
10705 // separate test. However, we only do this if this block doesn't
10706 // have a fall-through edge, because this requires an explicit
10707 // jmp when the condition is false.
10708 if (Op.getNode()->hasOneUse()) {
10709 SDNode *User = *Op.getNode()->use_begin();
10710 // Look for an unconditional branch following this conditional branch.
10711 // We need this because we need to reverse the successors in order
10712 // to implement FCMP_UNE.
10713 if (User->getOpcode() == ISD::BR) {
10714 SDValue FalseBB = User->getOperand(1);
10716 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
10717 assert(NewBR == User);
10720 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
10721 Cond.getOperand(0), Cond.getOperand(1));
10722 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
10723 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
10724 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
10725 Chain, Dest, CC, Cmp);
10726 CC = DAG.getConstant(X86::COND_NP, MVT::i8);
10736 // Look pass the truncate if the high bits are known zero.
10737 if (isTruncWithZeroHighBitsInput(Cond, DAG))
10738 Cond = Cond.getOperand(0);
10740 // We know the result of AND is compared against zero. Try to match
10742 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
10743 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
10744 if (NewSetCC.getNode()) {
10745 CC = NewSetCC.getOperand(0);
10746 Cond = NewSetCC.getOperand(1);
10753 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
10754 Cond = EmitTest(Cond, X86::COND_NE, DAG);
10756 Cond = ConvertCmpIfNecessary(Cond, DAG);
10757 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
10758 Chain, Dest, CC, Cond);
10761 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
10762 // Calls to _alloca is needed to probe the stack when allocating more than 4k
10763 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
10764 // that the guard pages used by the OS virtual memory manager are allocated in
10765 // correct sequence.
10767 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
10768 SelectionDAG &DAG) const {
10769 assert((Subtarget->isTargetCygMing() || Subtarget->isTargetWindows() ||
10770 getTargetMachine().Options.EnableSegmentedStacks) &&
10771 "This should be used only on Windows targets or when segmented stacks "
10773 assert(!Subtarget->isTargetEnvMacho() && "Not implemented");
10777 SDValue Chain = Op.getOperand(0);
10778 SDValue Size = Op.getOperand(1);
10779 unsigned Align = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
10780 EVT VT = Op.getNode()->getValueType(0);
10782 bool Is64Bit = Subtarget->is64Bit();
10783 EVT SPTy = Is64Bit ? MVT::i64 : MVT::i32;
10785 if (getTargetMachine().Options.EnableSegmentedStacks) {
10786 MachineFunction &MF = DAG.getMachineFunction();
10787 MachineRegisterInfo &MRI = MF.getRegInfo();
10790 // The 64 bit implementation of segmented stacks needs to clobber both r10
10791 // r11. This makes it impossible to use it along with nested parameters.
10792 const Function *F = MF.getFunction();
10794 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
10796 if (I->hasNestAttr())
10797 report_fatal_error("Cannot use segmented stacks with functions that "
10798 "have nested arguments.");
10801 const TargetRegisterClass *AddrRegClass =
10802 getRegClassFor(Subtarget->is64Bit() ? MVT::i64:MVT::i32);
10803 unsigned Vreg = MRI.createVirtualRegister(AddrRegClass);
10804 Chain = DAG.getCopyToReg(Chain, dl, Vreg, Size);
10805 SDValue Value = DAG.getNode(X86ISD::SEG_ALLOCA, dl, SPTy, Chain,
10806 DAG.getRegister(Vreg, SPTy));
10807 SDValue Ops1[2] = { Value, Chain };
10808 return DAG.getMergeValues(Ops1, 2, dl);
10811 unsigned Reg = (Subtarget->is64Bit() ? X86::RAX : X86::EAX);
10813 Chain = DAG.getCopyToReg(Chain, dl, Reg, Size, Flag);
10814 Flag = Chain.getValue(1);
10815 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
10817 Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag);
10819 const X86RegisterInfo *RegInfo =
10820 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
10821 unsigned SPReg = RegInfo->getStackRegister();
10822 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, SPTy);
10823 Chain = SP.getValue(1);
10826 SP = DAG.getNode(ISD::AND, dl, VT, SP.getValue(0),
10827 DAG.getConstant(-(uint64_t)Align, VT));
10828 Chain = DAG.getCopyToReg(Chain, dl, SPReg, SP);
10831 SDValue Ops1[2] = { SP, Chain };
10832 return DAG.getMergeValues(Ops1, 2, dl);
10836 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
10837 MachineFunction &MF = DAG.getMachineFunction();
10838 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
10840 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
10843 if (!Subtarget->is64Bit() || Subtarget->isTargetWin64()) {
10844 // vastart just stores the address of the VarArgsFrameIndex slot into the
10845 // memory location argument.
10846 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
10848 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
10849 MachinePointerInfo(SV), false, false, 0);
10853 // gp_offset (0 - 6 * 8)
10854 // fp_offset (48 - 48 + 8 * 16)
10855 // overflow_arg_area (point to parameters coming in memory).
10857 SmallVector<SDValue, 8> MemOps;
10858 SDValue FIN = Op.getOperand(1);
10860 SDValue Store = DAG.getStore(Op.getOperand(0), DL,
10861 DAG.getConstant(FuncInfo->getVarArgsGPOffset(),
10863 FIN, MachinePointerInfo(SV), false, false, 0);
10864 MemOps.push_back(Store);
10867 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
10868 FIN, DAG.getIntPtrConstant(4));
10869 Store = DAG.getStore(Op.getOperand(0), DL,
10870 DAG.getConstant(FuncInfo->getVarArgsFPOffset(),
10872 FIN, MachinePointerInfo(SV, 4), false, false, 0);
10873 MemOps.push_back(Store);
10875 // Store ptr to overflow_arg_area
10876 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
10877 FIN, DAG.getIntPtrConstant(4));
10878 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
10880 Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN,
10881 MachinePointerInfo(SV, 8),
10883 MemOps.push_back(Store);
10885 // Store ptr to reg_save_area.
10886 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
10887 FIN, DAG.getIntPtrConstant(8));
10888 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
10890 Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN,
10891 MachinePointerInfo(SV, 16), false, false, 0);
10892 MemOps.push_back(Store);
10893 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
10894 &MemOps[0], MemOps.size());
10897 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
10898 assert(Subtarget->is64Bit() &&
10899 "LowerVAARG only handles 64-bit va_arg!");
10900 assert((Subtarget->isTargetLinux() ||
10901 Subtarget->isTargetDarwin()) &&
10902 "Unhandled target in LowerVAARG");
10903 assert(Op.getNode()->getNumOperands() == 4);
10904 SDValue Chain = Op.getOperand(0);
10905 SDValue SrcPtr = Op.getOperand(1);
10906 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
10907 unsigned Align = Op.getConstantOperandVal(3);
10910 EVT ArgVT = Op.getNode()->getValueType(0);
10911 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
10912 uint32_t ArgSize = getDataLayout()->getTypeAllocSize(ArgTy);
10915 // Decide which area this value should be read from.
10916 // TODO: Implement the AMD64 ABI in its entirety. This simple
10917 // selection mechanism works only for the basic types.
10918 if (ArgVT == MVT::f80) {
10919 llvm_unreachable("va_arg for f80 not yet implemented");
10920 } else if (ArgVT.isFloatingPoint() && ArgSize <= 16 /*bytes*/) {
10921 ArgMode = 2; // Argument passed in XMM register. Use fp_offset.
10922 } else if (ArgVT.isInteger() && ArgSize <= 32 /*bytes*/) {
10923 ArgMode = 1; // Argument passed in GPR64 register(s). Use gp_offset.
10925 llvm_unreachable("Unhandled argument type in LowerVAARG");
10928 if (ArgMode == 2) {
10929 // Sanity Check: Make sure using fp_offset makes sense.
10930 assert(!getTargetMachine().Options.UseSoftFloat &&
10931 !(DAG.getMachineFunction()
10932 .getFunction()->getAttributes()
10933 .hasAttribute(AttributeSet::FunctionIndex,
10934 Attribute::NoImplicitFloat)) &&
10935 Subtarget->hasSSE1());
10938 // Insert VAARG_64 node into the DAG
10939 // VAARG_64 returns two values: Variable Argument Address, Chain
10940 SmallVector<SDValue, 11> InstOps;
10941 InstOps.push_back(Chain);
10942 InstOps.push_back(SrcPtr);
10943 InstOps.push_back(DAG.getConstant(ArgSize, MVT::i32));
10944 InstOps.push_back(DAG.getConstant(ArgMode, MVT::i8));
10945 InstOps.push_back(DAG.getConstant(Align, MVT::i32));
10946 SDVTList VTs = DAG.getVTList(getPointerTy(), MVT::Other);
10947 SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl,
10948 VTs, &InstOps[0], InstOps.size(),
10950 MachinePointerInfo(SV),
10952 /*Volatile=*/false,
10954 /*WriteMem=*/true);
10955 Chain = VAARG.getValue(1);
10957 // Load the next argument and return it
10958 return DAG.getLoad(ArgVT, dl,
10961 MachinePointerInfo(),
10962 false, false, false, 0);
10965 static SDValue LowerVACOPY(SDValue Op, const X86Subtarget *Subtarget,
10966 SelectionDAG &DAG) {
10967 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
10968 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
10969 SDValue Chain = Op.getOperand(0);
10970 SDValue DstPtr = Op.getOperand(1);
10971 SDValue SrcPtr = Op.getOperand(2);
10972 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
10973 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
10976 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr,
10977 DAG.getIntPtrConstant(24), 8, /*isVolatile*/false,
10979 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
10982 // getTargetVShiftByConstNode - Handle vector element shifts where the shift
10983 // amount is a constant. Takes immediate version of shift as input.
10984 static SDValue getTargetVShiftByConstNode(unsigned Opc, SDLoc dl, EVT VT,
10985 SDValue SrcOp, uint64_t ShiftAmt,
10986 SelectionDAG &DAG) {
10988 // Check for ShiftAmt >= element width
10989 if (ShiftAmt >= VT.getVectorElementType().getSizeInBits()) {
10990 if (Opc == X86ISD::VSRAI)
10991 ShiftAmt = VT.getVectorElementType().getSizeInBits() - 1;
10993 return DAG.getConstant(0, VT);
10996 assert((Opc == X86ISD::VSHLI || Opc == X86ISD::VSRLI || Opc == X86ISD::VSRAI)
10997 && "Unknown target vector shift-by-constant node");
10999 return DAG.getNode(Opc, dl, VT, SrcOp, DAG.getConstant(ShiftAmt, MVT::i8));
11002 // getTargetVShiftNode - Handle vector element shifts where the shift amount
11003 // may or may not be a constant. Takes immediate version of shift as input.
11004 static SDValue getTargetVShiftNode(unsigned Opc, SDLoc dl, EVT VT,
11005 SDValue SrcOp, SDValue ShAmt,
11006 SelectionDAG &DAG) {
11007 assert(ShAmt.getValueType() == MVT::i32 && "ShAmt is not i32");
11009 // Catch shift-by-constant.
11010 if (ConstantSDNode *CShAmt = dyn_cast<ConstantSDNode>(ShAmt))
11011 return getTargetVShiftByConstNode(Opc, dl, VT, SrcOp,
11012 CShAmt->getZExtValue(), DAG);
11014 // Change opcode to non-immediate version
11016 default: llvm_unreachable("Unknown target vector shift node");
11017 case X86ISD::VSHLI: Opc = X86ISD::VSHL; break;
11018 case X86ISD::VSRLI: Opc = X86ISD::VSRL; break;
11019 case X86ISD::VSRAI: Opc = X86ISD::VSRA; break;
11022 // Need to build a vector containing shift amount
11023 // Shift amount is 32-bits, but SSE instructions read 64-bit, so fill with 0
11026 ShOps[1] = DAG.getConstant(0, MVT::i32);
11027 ShOps[2] = ShOps[3] = DAG.getUNDEF(MVT::i32);
11028 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, &ShOps[0], 4);
11030 // The return type has to be a 128-bit type with the same element
11031 // type as the input type.
11032 MVT EltVT = VT.getVectorElementType().getSimpleVT();
11033 EVT ShVT = MVT::getVectorVT(EltVT, 128/EltVT.getSizeInBits());
11035 ShAmt = DAG.getNode(ISD::BITCAST, dl, ShVT, ShAmt);
11036 return DAG.getNode(Opc, dl, VT, SrcOp, ShAmt);
11039 static SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) {
11041 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
11043 default: return SDValue(); // Don't custom lower most intrinsics.
11044 // Comparison intrinsics.
11045 case Intrinsic::x86_sse_comieq_ss:
11046 case Intrinsic::x86_sse_comilt_ss:
11047 case Intrinsic::x86_sse_comile_ss:
11048 case Intrinsic::x86_sse_comigt_ss:
11049 case Intrinsic::x86_sse_comige_ss:
11050 case Intrinsic::x86_sse_comineq_ss:
11051 case Intrinsic::x86_sse_ucomieq_ss:
11052 case Intrinsic::x86_sse_ucomilt_ss:
11053 case Intrinsic::x86_sse_ucomile_ss:
11054 case Intrinsic::x86_sse_ucomigt_ss:
11055 case Intrinsic::x86_sse_ucomige_ss:
11056 case Intrinsic::x86_sse_ucomineq_ss:
11057 case Intrinsic::x86_sse2_comieq_sd:
11058 case Intrinsic::x86_sse2_comilt_sd:
11059 case Intrinsic::x86_sse2_comile_sd:
11060 case Intrinsic::x86_sse2_comigt_sd:
11061 case Intrinsic::x86_sse2_comige_sd:
11062 case Intrinsic::x86_sse2_comineq_sd:
11063 case Intrinsic::x86_sse2_ucomieq_sd:
11064 case Intrinsic::x86_sse2_ucomilt_sd:
11065 case Intrinsic::x86_sse2_ucomile_sd:
11066 case Intrinsic::x86_sse2_ucomigt_sd:
11067 case Intrinsic::x86_sse2_ucomige_sd:
11068 case Intrinsic::x86_sse2_ucomineq_sd: {
11072 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
11073 case Intrinsic::x86_sse_comieq_ss:
11074 case Intrinsic::x86_sse2_comieq_sd:
11075 Opc = X86ISD::COMI;
11078 case Intrinsic::x86_sse_comilt_ss:
11079 case Intrinsic::x86_sse2_comilt_sd:
11080 Opc = X86ISD::COMI;
11083 case Intrinsic::x86_sse_comile_ss:
11084 case Intrinsic::x86_sse2_comile_sd:
11085 Opc = X86ISD::COMI;
11088 case Intrinsic::x86_sse_comigt_ss:
11089 case Intrinsic::x86_sse2_comigt_sd:
11090 Opc = X86ISD::COMI;
11093 case Intrinsic::x86_sse_comige_ss:
11094 case Intrinsic::x86_sse2_comige_sd:
11095 Opc = X86ISD::COMI;
11098 case Intrinsic::x86_sse_comineq_ss:
11099 case Intrinsic::x86_sse2_comineq_sd:
11100 Opc = X86ISD::COMI;
11103 case Intrinsic::x86_sse_ucomieq_ss:
11104 case Intrinsic::x86_sse2_ucomieq_sd:
11105 Opc = X86ISD::UCOMI;
11108 case Intrinsic::x86_sse_ucomilt_ss:
11109 case Intrinsic::x86_sse2_ucomilt_sd:
11110 Opc = X86ISD::UCOMI;
11113 case Intrinsic::x86_sse_ucomile_ss:
11114 case Intrinsic::x86_sse2_ucomile_sd:
11115 Opc = X86ISD::UCOMI;
11118 case Intrinsic::x86_sse_ucomigt_ss:
11119 case Intrinsic::x86_sse2_ucomigt_sd:
11120 Opc = X86ISD::UCOMI;
11123 case Intrinsic::x86_sse_ucomige_ss:
11124 case Intrinsic::x86_sse2_ucomige_sd:
11125 Opc = X86ISD::UCOMI;
11128 case Intrinsic::x86_sse_ucomineq_ss:
11129 case Intrinsic::x86_sse2_ucomineq_sd:
11130 Opc = X86ISD::UCOMI;
11135 SDValue LHS = Op.getOperand(1);
11136 SDValue RHS = Op.getOperand(2);
11137 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG);
11138 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!");
11139 SDValue Cond = DAG.getNode(Opc, dl, MVT::i32, LHS, RHS);
11140 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
11141 DAG.getConstant(X86CC, MVT::i8), Cond);
11142 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
11145 // Arithmetic intrinsics.
11146 case Intrinsic::x86_sse2_pmulu_dq:
11147 case Intrinsic::x86_avx2_pmulu_dq:
11148 return DAG.getNode(X86ISD::PMULUDQ, dl, Op.getValueType(),
11149 Op.getOperand(1), Op.getOperand(2));
11151 // SSE2/AVX2 sub with unsigned saturation intrinsics
11152 case Intrinsic::x86_sse2_psubus_b:
11153 case Intrinsic::x86_sse2_psubus_w:
11154 case Intrinsic::x86_avx2_psubus_b:
11155 case Intrinsic::x86_avx2_psubus_w:
11156 return DAG.getNode(X86ISD::SUBUS, dl, Op.getValueType(),
11157 Op.getOperand(1), Op.getOperand(2));
11159 // SSE3/AVX horizontal add/sub intrinsics
11160 case Intrinsic::x86_sse3_hadd_ps:
11161 case Intrinsic::x86_sse3_hadd_pd:
11162 case Intrinsic::x86_avx_hadd_ps_256:
11163 case Intrinsic::x86_avx_hadd_pd_256:
11164 case Intrinsic::x86_sse3_hsub_ps:
11165 case Intrinsic::x86_sse3_hsub_pd:
11166 case Intrinsic::x86_avx_hsub_ps_256:
11167 case Intrinsic::x86_avx_hsub_pd_256:
11168 case Intrinsic::x86_ssse3_phadd_w_128:
11169 case Intrinsic::x86_ssse3_phadd_d_128:
11170 case Intrinsic::x86_avx2_phadd_w:
11171 case Intrinsic::x86_avx2_phadd_d:
11172 case Intrinsic::x86_ssse3_phsub_w_128:
11173 case Intrinsic::x86_ssse3_phsub_d_128:
11174 case Intrinsic::x86_avx2_phsub_w:
11175 case Intrinsic::x86_avx2_phsub_d: {
11178 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
11179 case Intrinsic::x86_sse3_hadd_ps:
11180 case Intrinsic::x86_sse3_hadd_pd:
11181 case Intrinsic::x86_avx_hadd_ps_256:
11182 case Intrinsic::x86_avx_hadd_pd_256:
11183 Opcode = X86ISD::FHADD;
11185 case Intrinsic::x86_sse3_hsub_ps:
11186 case Intrinsic::x86_sse3_hsub_pd:
11187 case Intrinsic::x86_avx_hsub_ps_256:
11188 case Intrinsic::x86_avx_hsub_pd_256:
11189 Opcode = X86ISD::FHSUB;
11191 case Intrinsic::x86_ssse3_phadd_w_128:
11192 case Intrinsic::x86_ssse3_phadd_d_128:
11193 case Intrinsic::x86_avx2_phadd_w:
11194 case Intrinsic::x86_avx2_phadd_d:
11195 Opcode = X86ISD::HADD;
11197 case Intrinsic::x86_ssse3_phsub_w_128:
11198 case Intrinsic::x86_ssse3_phsub_d_128:
11199 case Intrinsic::x86_avx2_phsub_w:
11200 case Intrinsic::x86_avx2_phsub_d:
11201 Opcode = X86ISD::HSUB;
11204 return DAG.getNode(Opcode, dl, Op.getValueType(),
11205 Op.getOperand(1), Op.getOperand(2));
11208 // SSE2/SSE41/AVX2 integer max/min intrinsics.
11209 case Intrinsic::x86_sse2_pmaxu_b:
11210 case Intrinsic::x86_sse41_pmaxuw:
11211 case Intrinsic::x86_sse41_pmaxud:
11212 case Intrinsic::x86_avx2_pmaxu_b:
11213 case Intrinsic::x86_avx2_pmaxu_w:
11214 case Intrinsic::x86_avx2_pmaxu_d:
11215 case Intrinsic::x86_avx512_pmaxu_d:
11216 case Intrinsic::x86_avx512_pmaxu_q:
11217 case Intrinsic::x86_sse2_pminu_b:
11218 case Intrinsic::x86_sse41_pminuw:
11219 case Intrinsic::x86_sse41_pminud:
11220 case Intrinsic::x86_avx2_pminu_b:
11221 case Intrinsic::x86_avx2_pminu_w:
11222 case Intrinsic::x86_avx2_pminu_d:
11223 case Intrinsic::x86_avx512_pminu_d:
11224 case Intrinsic::x86_avx512_pminu_q:
11225 case Intrinsic::x86_sse41_pmaxsb:
11226 case Intrinsic::x86_sse2_pmaxs_w:
11227 case Intrinsic::x86_sse41_pmaxsd:
11228 case Intrinsic::x86_avx2_pmaxs_b:
11229 case Intrinsic::x86_avx2_pmaxs_w:
11230 case Intrinsic::x86_avx2_pmaxs_d:
11231 case Intrinsic::x86_avx512_pmaxs_d:
11232 case Intrinsic::x86_avx512_pmaxs_q:
11233 case Intrinsic::x86_sse41_pminsb:
11234 case Intrinsic::x86_sse2_pmins_w:
11235 case Intrinsic::x86_sse41_pminsd:
11236 case Intrinsic::x86_avx2_pmins_b:
11237 case Intrinsic::x86_avx2_pmins_w:
11238 case Intrinsic::x86_avx2_pmins_d:
11239 case Intrinsic::x86_avx512_pmins_d:
11240 case Intrinsic::x86_avx512_pmins_q: {
11243 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
11244 case Intrinsic::x86_sse2_pmaxu_b:
11245 case Intrinsic::x86_sse41_pmaxuw:
11246 case Intrinsic::x86_sse41_pmaxud:
11247 case Intrinsic::x86_avx2_pmaxu_b:
11248 case Intrinsic::x86_avx2_pmaxu_w:
11249 case Intrinsic::x86_avx2_pmaxu_d:
11250 case Intrinsic::x86_avx512_pmaxu_d:
11251 case Intrinsic::x86_avx512_pmaxu_q:
11252 Opcode = X86ISD::UMAX;
11254 case Intrinsic::x86_sse2_pminu_b:
11255 case Intrinsic::x86_sse41_pminuw:
11256 case Intrinsic::x86_sse41_pminud:
11257 case Intrinsic::x86_avx2_pminu_b:
11258 case Intrinsic::x86_avx2_pminu_w:
11259 case Intrinsic::x86_avx2_pminu_d:
11260 case Intrinsic::x86_avx512_pminu_d:
11261 case Intrinsic::x86_avx512_pminu_q:
11262 Opcode = X86ISD::UMIN;
11264 case Intrinsic::x86_sse41_pmaxsb:
11265 case Intrinsic::x86_sse2_pmaxs_w:
11266 case Intrinsic::x86_sse41_pmaxsd:
11267 case Intrinsic::x86_avx2_pmaxs_b:
11268 case Intrinsic::x86_avx2_pmaxs_w:
11269 case Intrinsic::x86_avx2_pmaxs_d:
11270 case Intrinsic::x86_avx512_pmaxs_d:
11271 case Intrinsic::x86_avx512_pmaxs_q:
11272 Opcode = X86ISD::SMAX;
11274 case Intrinsic::x86_sse41_pminsb:
11275 case Intrinsic::x86_sse2_pmins_w:
11276 case Intrinsic::x86_sse41_pminsd:
11277 case Intrinsic::x86_avx2_pmins_b:
11278 case Intrinsic::x86_avx2_pmins_w:
11279 case Intrinsic::x86_avx2_pmins_d:
11280 case Intrinsic::x86_avx512_pmins_d:
11281 case Intrinsic::x86_avx512_pmins_q:
11282 Opcode = X86ISD::SMIN;
11285 return DAG.getNode(Opcode, dl, Op.getValueType(),
11286 Op.getOperand(1), Op.getOperand(2));
11289 // SSE/SSE2/AVX floating point max/min intrinsics.
11290 case Intrinsic::x86_sse_max_ps:
11291 case Intrinsic::x86_sse2_max_pd:
11292 case Intrinsic::x86_avx_max_ps_256:
11293 case Intrinsic::x86_avx_max_pd_256:
11294 case Intrinsic::x86_avx512_max_ps_512:
11295 case Intrinsic::x86_avx512_max_pd_512:
11296 case Intrinsic::x86_sse_min_ps:
11297 case Intrinsic::x86_sse2_min_pd:
11298 case Intrinsic::x86_avx_min_ps_256:
11299 case Intrinsic::x86_avx_min_pd_256:
11300 case Intrinsic::x86_avx512_min_ps_512:
11301 case Intrinsic::x86_avx512_min_pd_512: {
11304 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
11305 case Intrinsic::x86_sse_max_ps:
11306 case Intrinsic::x86_sse2_max_pd:
11307 case Intrinsic::x86_avx_max_ps_256:
11308 case Intrinsic::x86_avx_max_pd_256:
11309 case Intrinsic::x86_avx512_max_ps_512:
11310 case Intrinsic::x86_avx512_max_pd_512:
11311 Opcode = X86ISD::FMAX;
11313 case Intrinsic::x86_sse_min_ps:
11314 case Intrinsic::x86_sse2_min_pd:
11315 case Intrinsic::x86_avx_min_ps_256:
11316 case Intrinsic::x86_avx_min_pd_256:
11317 case Intrinsic::x86_avx512_min_ps_512:
11318 case Intrinsic::x86_avx512_min_pd_512:
11319 Opcode = X86ISD::FMIN;
11322 return DAG.getNode(Opcode, dl, Op.getValueType(),
11323 Op.getOperand(1), Op.getOperand(2));
11326 // AVX2 variable shift intrinsics
11327 case Intrinsic::x86_avx2_psllv_d:
11328 case Intrinsic::x86_avx2_psllv_q:
11329 case Intrinsic::x86_avx2_psllv_d_256:
11330 case Intrinsic::x86_avx2_psllv_q_256:
11331 case Intrinsic::x86_avx2_psrlv_d:
11332 case Intrinsic::x86_avx2_psrlv_q:
11333 case Intrinsic::x86_avx2_psrlv_d_256:
11334 case Intrinsic::x86_avx2_psrlv_q_256:
11335 case Intrinsic::x86_avx2_psrav_d:
11336 case Intrinsic::x86_avx2_psrav_d_256: {
11339 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
11340 case Intrinsic::x86_avx2_psllv_d:
11341 case Intrinsic::x86_avx2_psllv_q:
11342 case Intrinsic::x86_avx2_psllv_d_256:
11343 case Intrinsic::x86_avx2_psllv_q_256:
11346 case Intrinsic::x86_avx2_psrlv_d:
11347 case Intrinsic::x86_avx2_psrlv_q:
11348 case Intrinsic::x86_avx2_psrlv_d_256:
11349 case Intrinsic::x86_avx2_psrlv_q_256:
11352 case Intrinsic::x86_avx2_psrav_d:
11353 case Intrinsic::x86_avx2_psrav_d_256:
11357 return DAG.getNode(Opcode, dl, Op.getValueType(),
11358 Op.getOperand(1), Op.getOperand(2));
11361 case Intrinsic::x86_ssse3_pshuf_b_128:
11362 case Intrinsic::x86_avx2_pshuf_b:
11363 return DAG.getNode(X86ISD::PSHUFB, dl, Op.getValueType(),
11364 Op.getOperand(1), Op.getOperand(2));
11366 case Intrinsic::x86_ssse3_psign_b_128:
11367 case Intrinsic::x86_ssse3_psign_w_128:
11368 case Intrinsic::x86_ssse3_psign_d_128:
11369 case Intrinsic::x86_avx2_psign_b:
11370 case Intrinsic::x86_avx2_psign_w:
11371 case Intrinsic::x86_avx2_psign_d:
11372 return DAG.getNode(X86ISD::PSIGN, dl, Op.getValueType(),
11373 Op.getOperand(1), Op.getOperand(2));
11375 case Intrinsic::x86_sse41_insertps:
11376 return DAG.getNode(X86ISD::INSERTPS, dl, Op.getValueType(),
11377 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
11379 case Intrinsic::x86_avx_vperm2f128_ps_256:
11380 case Intrinsic::x86_avx_vperm2f128_pd_256:
11381 case Intrinsic::x86_avx_vperm2f128_si_256:
11382 case Intrinsic::x86_avx2_vperm2i128:
11383 return DAG.getNode(X86ISD::VPERM2X128, dl, Op.getValueType(),
11384 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
11386 case Intrinsic::x86_avx2_permd:
11387 case Intrinsic::x86_avx2_permps:
11388 // Operands intentionally swapped. Mask is last operand to intrinsic,
11389 // but second operand for node/instruction.
11390 return DAG.getNode(X86ISD::VPERMV, dl, Op.getValueType(),
11391 Op.getOperand(2), Op.getOperand(1));
11393 case Intrinsic::x86_sse_sqrt_ps:
11394 case Intrinsic::x86_sse2_sqrt_pd:
11395 case Intrinsic::x86_avx_sqrt_ps_256:
11396 case Intrinsic::x86_avx_sqrt_pd_256:
11397 return DAG.getNode(ISD::FSQRT, dl, Op.getValueType(), Op.getOperand(1));
11399 // ptest and testp intrinsics. The intrinsic these come from are designed to
11400 // return an integer value, not just an instruction so lower it to the ptest
11401 // or testp pattern and a setcc for the result.
11402 case Intrinsic::x86_sse41_ptestz:
11403 case Intrinsic::x86_sse41_ptestc:
11404 case Intrinsic::x86_sse41_ptestnzc:
11405 case Intrinsic::x86_avx_ptestz_256:
11406 case Intrinsic::x86_avx_ptestc_256:
11407 case Intrinsic::x86_avx_ptestnzc_256:
11408 case Intrinsic::x86_avx_vtestz_ps:
11409 case Intrinsic::x86_avx_vtestc_ps:
11410 case Intrinsic::x86_avx_vtestnzc_ps:
11411 case Intrinsic::x86_avx_vtestz_pd:
11412 case Intrinsic::x86_avx_vtestc_pd:
11413 case Intrinsic::x86_avx_vtestnzc_pd:
11414 case Intrinsic::x86_avx_vtestz_ps_256:
11415 case Intrinsic::x86_avx_vtestc_ps_256:
11416 case Intrinsic::x86_avx_vtestnzc_ps_256:
11417 case Intrinsic::x86_avx_vtestz_pd_256:
11418 case Intrinsic::x86_avx_vtestc_pd_256:
11419 case Intrinsic::x86_avx_vtestnzc_pd_256: {
11420 bool IsTestPacked = false;
11423 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
11424 case Intrinsic::x86_avx_vtestz_ps:
11425 case Intrinsic::x86_avx_vtestz_pd:
11426 case Intrinsic::x86_avx_vtestz_ps_256:
11427 case Intrinsic::x86_avx_vtestz_pd_256:
11428 IsTestPacked = true; // Fallthrough
11429 case Intrinsic::x86_sse41_ptestz:
11430 case Intrinsic::x86_avx_ptestz_256:
11432 X86CC = X86::COND_E;
11434 case Intrinsic::x86_avx_vtestc_ps:
11435 case Intrinsic::x86_avx_vtestc_pd:
11436 case Intrinsic::x86_avx_vtestc_ps_256:
11437 case Intrinsic::x86_avx_vtestc_pd_256:
11438 IsTestPacked = true; // Fallthrough
11439 case Intrinsic::x86_sse41_ptestc:
11440 case Intrinsic::x86_avx_ptestc_256:
11442 X86CC = X86::COND_B;
11444 case Intrinsic::x86_avx_vtestnzc_ps:
11445 case Intrinsic::x86_avx_vtestnzc_pd:
11446 case Intrinsic::x86_avx_vtestnzc_ps_256:
11447 case Intrinsic::x86_avx_vtestnzc_pd_256:
11448 IsTestPacked = true; // Fallthrough
11449 case Intrinsic::x86_sse41_ptestnzc:
11450 case Intrinsic::x86_avx_ptestnzc_256:
11452 X86CC = X86::COND_A;
11456 SDValue LHS = Op.getOperand(1);
11457 SDValue RHS = Op.getOperand(2);
11458 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST;
11459 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS);
11460 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
11461 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
11462 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
11464 case Intrinsic::x86_avx512_kortestz:
11465 case Intrinsic::x86_avx512_kortestc: {
11466 unsigned X86CC = (IntNo == Intrinsic::x86_avx512_kortestz)? X86::COND_E: X86::COND_B;
11467 SDValue LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1, Op.getOperand(1));
11468 SDValue RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1, Op.getOperand(2));
11469 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
11470 SDValue Test = DAG.getNode(X86ISD::KORTEST, dl, MVT::i32, LHS, RHS);
11471 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
11472 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
11475 // SSE/AVX shift intrinsics
11476 case Intrinsic::x86_sse2_psll_w:
11477 case Intrinsic::x86_sse2_psll_d:
11478 case Intrinsic::x86_sse2_psll_q:
11479 case Intrinsic::x86_avx2_psll_w:
11480 case Intrinsic::x86_avx2_psll_d:
11481 case Intrinsic::x86_avx2_psll_q:
11482 case Intrinsic::x86_sse2_psrl_w:
11483 case Intrinsic::x86_sse2_psrl_d:
11484 case Intrinsic::x86_sse2_psrl_q:
11485 case Intrinsic::x86_avx2_psrl_w:
11486 case Intrinsic::x86_avx2_psrl_d:
11487 case Intrinsic::x86_avx2_psrl_q:
11488 case Intrinsic::x86_sse2_psra_w:
11489 case Intrinsic::x86_sse2_psra_d:
11490 case Intrinsic::x86_avx2_psra_w:
11491 case Intrinsic::x86_avx2_psra_d: {
11494 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
11495 case Intrinsic::x86_sse2_psll_w:
11496 case Intrinsic::x86_sse2_psll_d:
11497 case Intrinsic::x86_sse2_psll_q:
11498 case Intrinsic::x86_avx2_psll_w:
11499 case Intrinsic::x86_avx2_psll_d:
11500 case Intrinsic::x86_avx2_psll_q:
11501 Opcode = X86ISD::VSHL;
11503 case Intrinsic::x86_sse2_psrl_w:
11504 case Intrinsic::x86_sse2_psrl_d:
11505 case Intrinsic::x86_sse2_psrl_q:
11506 case Intrinsic::x86_avx2_psrl_w:
11507 case Intrinsic::x86_avx2_psrl_d:
11508 case Intrinsic::x86_avx2_psrl_q:
11509 Opcode = X86ISD::VSRL;
11511 case Intrinsic::x86_sse2_psra_w:
11512 case Intrinsic::x86_sse2_psra_d:
11513 case Intrinsic::x86_avx2_psra_w:
11514 case Intrinsic::x86_avx2_psra_d:
11515 Opcode = X86ISD::VSRA;
11518 return DAG.getNode(Opcode, dl, Op.getValueType(),
11519 Op.getOperand(1), Op.getOperand(2));
11522 // SSE/AVX immediate shift intrinsics
11523 case Intrinsic::x86_sse2_pslli_w:
11524 case Intrinsic::x86_sse2_pslli_d:
11525 case Intrinsic::x86_sse2_pslli_q:
11526 case Intrinsic::x86_avx2_pslli_w:
11527 case Intrinsic::x86_avx2_pslli_d:
11528 case Intrinsic::x86_avx2_pslli_q:
11529 case Intrinsic::x86_sse2_psrli_w:
11530 case Intrinsic::x86_sse2_psrli_d:
11531 case Intrinsic::x86_sse2_psrli_q:
11532 case Intrinsic::x86_avx2_psrli_w:
11533 case Intrinsic::x86_avx2_psrli_d:
11534 case Intrinsic::x86_avx2_psrli_q:
11535 case Intrinsic::x86_sse2_psrai_w:
11536 case Intrinsic::x86_sse2_psrai_d:
11537 case Intrinsic::x86_avx2_psrai_w:
11538 case Intrinsic::x86_avx2_psrai_d: {
11541 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
11542 case Intrinsic::x86_sse2_pslli_w:
11543 case Intrinsic::x86_sse2_pslli_d:
11544 case Intrinsic::x86_sse2_pslli_q:
11545 case Intrinsic::x86_avx2_pslli_w:
11546 case Intrinsic::x86_avx2_pslli_d:
11547 case Intrinsic::x86_avx2_pslli_q:
11548 Opcode = X86ISD::VSHLI;
11550 case Intrinsic::x86_sse2_psrli_w:
11551 case Intrinsic::x86_sse2_psrli_d:
11552 case Intrinsic::x86_sse2_psrli_q:
11553 case Intrinsic::x86_avx2_psrli_w:
11554 case Intrinsic::x86_avx2_psrli_d:
11555 case Intrinsic::x86_avx2_psrli_q:
11556 Opcode = X86ISD::VSRLI;
11558 case Intrinsic::x86_sse2_psrai_w:
11559 case Intrinsic::x86_sse2_psrai_d:
11560 case Intrinsic::x86_avx2_psrai_w:
11561 case Intrinsic::x86_avx2_psrai_d:
11562 Opcode = X86ISD::VSRAI;
11565 return getTargetVShiftNode(Opcode, dl, Op.getValueType(),
11566 Op.getOperand(1), Op.getOperand(2), DAG);
11569 case Intrinsic::x86_sse42_pcmpistria128:
11570 case Intrinsic::x86_sse42_pcmpestria128:
11571 case Intrinsic::x86_sse42_pcmpistric128:
11572 case Intrinsic::x86_sse42_pcmpestric128:
11573 case Intrinsic::x86_sse42_pcmpistrio128:
11574 case Intrinsic::x86_sse42_pcmpestrio128:
11575 case Intrinsic::x86_sse42_pcmpistris128:
11576 case Intrinsic::x86_sse42_pcmpestris128:
11577 case Intrinsic::x86_sse42_pcmpistriz128:
11578 case Intrinsic::x86_sse42_pcmpestriz128: {
11582 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
11583 case Intrinsic::x86_sse42_pcmpistria128:
11584 Opcode = X86ISD::PCMPISTRI;
11585 X86CC = X86::COND_A;
11587 case Intrinsic::x86_sse42_pcmpestria128:
11588 Opcode = X86ISD::PCMPESTRI;
11589 X86CC = X86::COND_A;
11591 case Intrinsic::x86_sse42_pcmpistric128:
11592 Opcode = X86ISD::PCMPISTRI;
11593 X86CC = X86::COND_B;
11595 case Intrinsic::x86_sse42_pcmpestric128:
11596 Opcode = X86ISD::PCMPESTRI;
11597 X86CC = X86::COND_B;
11599 case Intrinsic::x86_sse42_pcmpistrio128:
11600 Opcode = X86ISD::PCMPISTRI;
11601 X86CC = X86::COND_O;
11603 case Intrinsic::x86_sse42_pcmpestrio128:
11604 Opcode = X86ISD::PCMPESTRI;
11605 X86CC = X86::COND_O;
11607 case Intrinsic::x86_sse42_pcmpistris128:
11608 Opcode = X86ISD::PCMPISTRI;
11609 X86CC = X86::COND_S;
11611 case Intrinsic::x86_sse42_pcmpestris128:
11612 Opcode = X86ISD::PCMPESTRI;
11613 X86CC = X86::COND_S;
11615 case Intrinsic::x86_sse42_pcmpistriz128:
11616 Opcode = X86ISD::PCMPISTRI;
11617 X86CC = X86::COND_E;
11619 case Intrinsic::x86_sse42_pcmpestriz128:
11620 Opcode = X86ISD::PCMPESTRI;
11621 X86CC = X86::COND_E;
11624 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
11625 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
11626 SDValue PCMP = DAG.getNode(Opcode, dl, VTs, NewOps.data(), NewOps.size());
11627 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
11628 DAG.getConstant(X86CC, MVT::i8),
11629 SDValue(PCMP.getNode(), 1));
11630 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
11633 case Intrinsic::x86_sse42_pcmpistri128:
11634 case Intrinsic::x86_sse42_pcmpestri128: {
11636 if (IntNo == Intrinsic::x86_sse42_pcmpistri128)
11637 Opcode = X86ISD::PCMPISTRI;
11639 Opcode = X86ISD::PCMPESTRI;
11641 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
11642 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
11643 return DAG.getNode(Opcode, dl, VTs, NewOps.data(), NewOps.size());
11645 case Intrinsic::x86_fma_vfmadd_ps:
11646 case Intrinsic::x86_fma_vfmadd_pd:
11647 case Intrinsic::x86_fma_vfmsub_ps:
11648 case Intrinsic::x86_fma_vfmsub_pd:
11649 case Intrinsic::x86_fma_vfnmadd_ps:
11650 case Intrinsic::x86_fma_vfnmadd_pd:
11651 case Intrinsic::x86_fma_vfnmsub_ps:
11652 case Intrinsic::x86_fma_vfnmsub_pd:
11653 case Intrinsic::x86_fma_vfmaddsub_ps:
11654 case Intrinsic::x86_fma_vfmaddsub_pd:
11655 case Intrinsic::x86_fma_vfmsubadd_ps:
11656 case Intrinsic::x86_fma_vfmsubadd_pd:
11657 case Intrinsic::x86_fma_vfmadd_ps_256:
11658 case Intrinsic::x86_fma_vfmadd_pd_256:
11659 case Intrinsic::x86_fma_vfmsub_ps_256:
11660 case Intrinsic::x86_fma_vfmsub_pd_256:
11661 case Intrinsic::x86_fma_vfnmadd_ps_256:
11662 case Intrinsic::x86_fma_vfnmadd_pd_256:
11663 case Intrinsic::x86_fma_vfnmsub_ps_256:
11664 case Intrinsic::x86_fma_vfnmsub_pd_256:
11665 case Intrinsic::x86_fma_vfmaddsub_ps_256:
11666 case Intrinsic::x86_fma_vfmaddsub_pd_256:
11667 case Intrinsic::x86_fma_vfmsubadd_ps_256:
11668 case Intrinsic::x86_fma_vfmsubadd_pd_256:
11669 case Intrinsic::x86_fma_vfmadd_ps_512:
11670 case Intrinsic::x86_fma_vfmadd_pd_512:
11671 case Intrinsic::x86_fma_vfmsub_ps_512:
11672 case Intrinsic::x86_fma_vfmsub_pd_512:
11673 case Intrinsic::x86_fma_vfnmadd_ps_512:
11674 case Intrinsic::x86_fma_vfnmadd_pd_512:
11675 case Intrinsic::x86_fma_vfnmsub_ps_512:
11676 case Intrinsic::x86_fma_vfnmsub_pd_512:
11677 case Intrinsic::x86_fma_vfmaddsub_ps_512:
11678 case Intrinsic::x86_fma_vfmaddsub_pd_512:
11679 case Intrinsic::x86_fma_vfmsubadd_ps_512:
11680 case Intrinsic::x86_fma_vfmsubadd_pd_512: {
11683 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
11684 case Intrinsic::x86_fma_vfmadd_ps:
11685 case Intrinsic::x86_fma_vfmadd_pd:
11686 case Intrinsic::x86_fma_vfmadd_ps_256:
11687 case Intrinsic::x86_fma_vfmadd_pd_256:
11688 case Intrinsic::x86_fma_vfmadd_ps_512:
11689 case Intrinsic::x86_fma_vfmadd_pd_512:
11690 Opc = X86ISD::FMADD;
11692 case Intrinsic::x86_fma_vfmsub_ps:
11693 case Intrinsic::x86_fma_vfmsub_pd:
11694 case Intrinsic::x86_fma_vfmsub_ps_256:
11695 case Intrinsic::x86_fma_vfmsub_pd_256:
11696 case Intrinsic::x86_fma_vfmsub_ps_512:
11697 case Intrinsic::x86_fma_vfmsub_pd_512:
11698 Opc = X86ISD::FMSUB;
11700 case Intrinsic::x86_fma_vfnmadd_ps:
11701 case Intrinsic::x86_fma_vfnmadd_pd:
11702 case Intrinsic::x86_fma_vfnmadd_ps_256:
11703 case Intrinsic::x86_fma_vfnmadd_pd_256:
11704 case Intrinsic::x86_fma_vfnmadd_ps_512:
11705 case Intrinsic::x86_fma_vfnmadd_pd_512:
11706 Opc = X86ISD::FNMADD;
11708 case Intrinsic::x86_fma_vfnmsub_ps:
11709 case Intrinsic::x86_fma_vfnmsub_pd:
11710 case Intrinsic::x86_fma_vfnmsub_ps_256:
11711 case Intrinsic::x86_fma_vfnmsub_pd_256:
11712 case Intrinsic::x86_fma_vfnmsub_ps_512:
11713 case Intrinsic::x86_fma_vfnmsub_pd_512:
11714 Opc = X86ISD::FNMSUB;
11716 case Intrinsic::x86_fma_vfmaddsub_ps:
11717 case Intrinsic::x86_fma_vfmaddsub_pd:
11718 case Intrinsic::x86_fma_vfmaddsub_ps_256:
11719 case Intrinsic::x86_fma_vfmaddsub_pd_256:
11720 case Intrinsic::x86_fma_vfmaddsub_ps_512:
11721 case Intrinsic::x86_fma_vfmaddsub_pd_512:
11722 Opc = X86ISD::FMADDSUB;
11724 case Intrinsic::x86_fma_vfmsubadd_ps:
11725 case Intrinsic::x86_fma_vfmsubadd_pd:
11726 case Intrinsic::x86_fma_vfmsubadd_ps_256:
11727 case Intrinsic::x86_fma_vfmsubadd_pd_256:
11728 case Intrinsic::x86_fma_vfmsubadd_ps_512:
11729 case Intrinsic::x86_fma_vfmsubadd_pd_512:
11730 Opc = X86ISD::FMSUBADD;
11734 return DAG.getNode(Opc, dl, Op.getValueType(), Op.getOperand(1),
11735 Op.getOperand(2), Op.getOperand(3));
11740 static SDValue getGatherNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
11741 SDValue Base, SDValue Index,
11742 SDValue ScaleOp, SDValue Chain,
11743 const X86Subtarget * Subtarget) {
11745 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
11746 assert(C && "Invalid scale type");
11747 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
11748 SDValue Src = getZeroVector(Op.getValueType(), Subtarget, DAG, dl);
11749 EVT MaskVT = MVT::getVectorVT(MVT::i1,
11750 Index.getValueType().getVectorNumElements());
11751 SDValue MaskInReg = DAG.getConstant(~0, MaskVT);
11752 SDVTList VTs = DAG.getVTList(Op.getValueType(), MaskVT, MVT::Other);
11753 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
11754 SDValue Segment = DAG.getRegister(0, MVT::i32);
11755 SDValue Ops[] = {Src, MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
11756 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
11757 SDValue RetOps[] = { SDValue(Res, 0), SDValue(Res, 2) };
11758 return DAG.getMergeValues(RetOps, array_lengthof(RetOps), dl);
11761 static SDValue getMGatherNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
11762 SDValue Src, SDValue Mask, SDValue Base,
11763 SDValue Index, SDValue ScaleOp, SDValue Chain,
11764 const X86Subtarget * Subtarget) {
11766 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
11767 assert(C && "Invalid scale type");
11768 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
11769 EVT MaskVT = MVT::getVectorVT(MVT::i1,
11770 Index.getValueType().getVectorNumElements());
11771 SDValue MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
11772 SDVTList VTs = DAG.getVTList(Op.getValueType(), MaskVT, MVT::Other);
11773 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
11774 SDValue Segment = DAG.getRegister(0, MVT::i32);
11775 if (Src.getOpcode() == ISD::UNDEF)
11776 Src = getZeroVector(Op.getValueType(), Subtarget, DAG, dl);
11777 SDValue Ops[] = {Src, MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
11778 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
11779 SDValue RetOps[] = { SDValue(Res, 0), SDValue(Res, 2) };
11780 return DAG.getMergeValues(RetOps, array_lengthof(RetOps), dl);
11783 static SDValue getScatterNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
11784 SDValue Src, SDValue Base, SDValue Index,
11785 SDValue ScaleOp, SDValue Chain) {
11787 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
11788 assert(C && "Invalid scale type");
11789 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
11790 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
11791 SDValue Segment = DAG.getRegister(0, MVT::i32);
11792 EVT MaskVT = MVT::getVectorVT(MVT::i1,
11793 Index.getValueType().getVectorNumElements());
11794 SDValue MaskInReg = DAG.getConstant(~0, MaskVT);
11795 SDVTList VTs = DAG.getVTList(MaskVT, MVT::Other);
11796 SDValue Ops[] = {Base, Scale, Index, Disp, Segment, MaskInReg, Src, Chain};
11797 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
11798 return SDValue(Res, 1);
11801 static SDValue getMScatterNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
11802 SDValue Src, SDValue Mask, SDValue Base,
11803 SDValue Index, SDValue ScaleOp, SDValue Chain) {
11805 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
11806 assert(C && "Invalid scale type");
11807 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
11808 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
11809 SDValue Segment = DAG.getRegister(0, MVT::i32);
11810 EVT MaskVT = MVT::getVectorVT(MVT::i1,
11811 Index.getValueType().getVectorNumElements());
11812 SDValue MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
11813 SDVTList VTs = DAG.getVTList(MaskVT, MVT::Other);
11814 SDValue Ops[] = {Base, Scale, Index, Disp, Segment, MaskInReg, Src, Chain};
11815 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
11816 return SDValue(Res, 1);
11819 static SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
11820 SelectionDAG &DAG) {
11822 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
11824 default: return SDValue(); // Don't custom lower most intrinsics.
11826 // RDRAND/RDSEED intrinsics.
11827 case Intrinsic::x86_rdrand_16:
11828 case Intrinsic::x86_rdrand_32:
11829 case Intrinsic::x86_rdrand_64:
11830 case Intrinsic::x86_rdseed_16:
11831 case Intrinsic::x86_rdseed_32:
11832 case Intrinsic::x86_rdseed_64: {
11833 unsigned Opcode = (IntNo == Intrinsic::x86_rdseed_16 ||
11834 IntNo == Intrinsic::x86_rdseed_32 ||
11835 IntNo == Intrinsic::x86_rdseed_64) ? X86ISD::RDSEED :
11837 // Emit the node with the right value type.
11838 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Glue, MVT::Other);
11839 SDValue Result = DAG.getNode(Opcode, dl, VTs, Op.getOperand(0));
11841 // If the value returned by RDRAND/RDSEED was valid (CF=1), return 1.
11842 // Otherwise return the value from Rand, which is always 0, casted to i32.
11843 SDValue Ops[] = { DAG.getZExtOrTrunc(Result, dl, Op->getValueType(1)),
11844 DAG.getConstant(1, Op->getValueType(1)),
11845 DAG.getConstant(X86::COND_B, MVT::i32),
11846 SDValue(Result.getNode(), 1) };
11847 SDValue isValid = DAG.getNode(X86ISD::CMOV, dl,
11848 DAG.getVTList(Op->getValueType(1), MVT::Glue),
11849 Ops, array_lengthof(Ops));
11851 // Return { result, isValid, chain }.
11852 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(), Result, isValid,
11853 SDValue(Result.getNode(), 2));
11855 //int_gather(index, base, scale);
11856 case Intrinsic::x86_avx512_gather_qpd_512:
11857 case Intrinsic::x86_avx512_gather_qps_512:
11858 case Intrinsic::x86_avx512_gather_dpd_512:
11859 case Intrinsic::x86_avx512_gather_qpi_512:
11860 case Intrinsic::x86_avx512_gather_qpq_512:
11861 case Intrinsic::x86_avx512_gather_dpq_512:
11862 case Intrinsic::x86_avx512_gather_dps_512:
11863 case Intrinsic::x86_avx512_gather_dpi_512: {
11866 default: llvm_unreachable("Unexpected intrinsic!");
11867 case Intrinsic::x86_avx512_gather_qps_512: Opc = X86::VGATHERQPSZrm; break;
11868 case Intrinsic::x86_avx512_gather_qpd_512: Opc = X86::VGATHERQPDZrm; break;
11869 case Intrinsic::x86_avx512_gather_dpd_512: Opc = X86::VGATHERDPDZrm; break;
11870 case Intrinsic::x86_avx512_gather_dps_512: Opc = X86::VGATHERDPSZrm; break;
11871 case Intrinsic::x86_avx512_gather_qpi_512: Opc = X86::VPGATHERQDZrm; break;
11872 case Intrinsic::x86_avx512_gather_qpq_512: Opc = X86::VPGATHERQQZrm; break;
11873 case Intrinsic::x86_avx512_gather_dpi_512: Opc = X86::VPGATHERDDZrm; break;
11874 case Intrinsic::x86_avx512_gather_dpq_512: Opc = X86::VPGATHERDQZrm; break;
11876 SDValue Chain = Op.getOperand(0);
11877 SDValue Index = Op.getOperand(2);
11878 SDValue Base = Op.getOperand(3);
11879 SDValue Scale = Op.getOperand(4);
11880 return getGatherNode(Opc, Op, DAG, Base, Index, Scale, Chain, Subtarget);
11882 //int_gather_mask(v1, mask, index, base, scale);
11883 case Intrinsic::x86_avx512_gather_qps_mask_512:
11884 case Intrinsic::x86_avx512_gather_qpd_mask_512:
11885 case Intrinsic::x86_avx512_gather_dpd_mask_512:
11886 case Intrinsic::x86_avx512_gather_dps_mask_512:
11887 case Intrinsic::x86_avx512_gather_qpi_mask_512:
11888 case Intrinsic::x86_avx512_gather_qpq_mask_512:
11889 case Intrinsic::x86_avx512_gather_dpi_mask_512:
11890 case Intrinsic::x86_avx512_gather_dpq_mask_512: {
11893 default: llvm_unreachable("Unexpected intrinsic!");
11894 case Intrinsic::x86_avx512_gather_qps_mask_512:
11895 Opc = X86::VGATHERQPSZrm; break;
11896 case Intrinsic::x86_avx512_gather_qpd_mask_512:
11897 Opc = X86::VGATHERQPDZrm; break;
11898 case Intrinsic::x86_avx512_gather_dpd_mask_512:
11899 Opc = X86::VGATHERDPDZrm; break;
11900 case Intrinsic::x86_avx512_gather_dps_mask_512:
11901 Opc = X86::VGATHERDPSZrm; break;
11902 case Intrinsic::x86_avx512_gather_qpi_mask_512:
11903 Opc = X86::VPGATHERQDZrm; break;
11904 case Intrinsic::x86_avx512_gather_qpq_mask_512:
11905 Opc = X86::VPGATHERQQZrm; break;
11906 case Intrinsic::x86_avx512_gather_dpi_mask_512:
11907 Opc = X86::VPGATHERDDZrm; break;
11908 case Intrinsic::x86_avx512_gather_dpq_mask_512:
11909 Opc = X86::VPGATHERDQZrm; break;
11911 SDValue Chain = Op.getOperand(0);
11912 SDValue Src = Op.getOperand(2);
11913 SDValue Mask = Op.getOperand(3);
11914 SDValue Index = Op.getOperand(4);
11915 SDValue Base = Op.getOperand(5);
11916 SDValue Scale = Op.getOperand(6);
11917 return getMGatherNode(Opc, Op, DAG, Src, Mask, Base, Index, Scale, Chain,
11920 //int_scatter(base, index, v1, scale);
11921 case Intrinsic::x86_avx512_scatter_qpd_512:
11922 case Intrinsic::x86_avx512_scatter_qps_512:
11923 case Intrinsic::x86_avx512_scatter_dpd_512:
11924 case Intrinsic::x86_avx512_scatter_qpi_512:
11925 case Intrinsic::x86_avx512_scatter_qpq_512:
11926 case Intrinsic::x86_avx512_scatter_dpq_512:
11927 case Intrinsic::x86_avx512_scatter_dps_512:
11928 case Intrinsic::x86_avx512_scatter_dpi_512: {
11931 default: llvm_unreachable("Unexpected intrinsic!");
11932 case Intrinsic::x86_avx512_scatter_qpd_512:
11933 Opc = X86::VSCATTERQPDZmr; break;
11934 case Intrinsic::x86_avx512_scatter_qps_512:
11935 Opc = X86::VSCATTERQPSZmr; break;
11936 case Intrinsic::x86_avx512_scatter_dpd_512:
11937 Opc = X86::VSCATTERDPDZmr; break;
11938 case Intrinsic::x86_avx512_scatter_dps_512:
11939 Opc = X86::VSCATTERDPSZmr; break;
11940 case Intrinsic::x86_avx512_scatter_qpi_512:
11941 Opc = X86::VPSCATTERQDZmr; break;
11942 case Intrinsic::x86_avx512_scatter_qpq_512:
11943 Opc = X86::VPSCATTERQQZmr; break;
11944 case Intrinsic::x86_avx512_scatter_dpq_512:
11945 Opc = X86::VPSCATTERDQZmr; break;
11946 case Intrinsic::x86_avx512_scatter_dpi_512:
11947 Opc = X86::VPSCATTERDDZmr; break;
11949 SDValue Chain = Op.getOperand(0);
11950 SDValue Base = Op.getOperand(2);
11951 SDValue Index = Op.getOperand(3);
11952 SDValue Src = Op.getOperand(4);
11953 SDValue Scale = Op.getOperand(5);
11954 return getScatterNode(Opc, Op, DAG, Src, Base, Index, Scale, Chain);
11956 //int_scatter_mask(base, mask, index, v1, scale);
11957 case Intrinsic::x86_avx512_scatter_qps_mask_512:
11958 case Intrinsic::x86_avx512_scatter_qpd_mask_512:
11959 case Intrinsic::x86_avx512_scatter_dpd_mask_512:
11960 case Intrinsic::x86_avx512_scatter_dps_mask_512:
11961 case Intrinsic::x86_avx512_scatter_qpi_mask_512:
11962 case Intrinsic::x86_avx512_scatter_qpq_mask_512:
11963 case Intrinsic::x86_avx512_scatter_dpi_mask_512:
11964 case Intrinsic::x86_avx512_scatter_dpq_mask_512: {
11967 default: llvm_unreachable("Unexpected intrinsic!");
11968 case Intrinsic::x86_avx512_scatter_qpd_mask_512:
11969 Opc = X86::VSCATTERQPDZmr; break;
11970 case Intrinsic::x86_avx512_scatter_qps_mask_512:
11971 Opc = X86::VSCATTERQPSZmr; break;
11972 case Intrinsic::x86_avx512_scatter_dpd_mask_512:
11973 Opc = X86::VSCATTERDPDZmr; break;
11974 case Intrinsic::x86_avx512_scatter_dps_mask_512:
11975 Opc = X86::VSCATTERDPSZmr; break;
11976 case Intrinsic::x86_avx512_scatter_qpi_mask_512:
11977 Opc = X86::VPSCATTERQDZmr; break;
11978 case Intrinsic::x86_avx512_scatter_qpq_mask_512:
11979 Opc = X86::VPSCATTERQQZmr; break;
11980 case Intrinsic::x86_avx512_scatter_dpq_mask_512:
11981 Opc = X86::VPSCATTERDQZmr; break;
11982 case Intrinsic::x86_avx512_scatter_dpi_mask_512:
11983 Opc = X86::VPSCATTERDDZmr; break;
11985 SDValue Chain = Op.getOperand(0);
11986 SDValue Base = Op.getOperand(2);
11987 SDValue Mask = Op.getOperand(3);
11988 SDValue Index = Op.getOperand(4);
11989 SDValue Src = Op.getOperand(5);
11990 SDValue Scale = Op.getOperand(6);
11991 return getMScatterNode(Opc, Op, DAG, Src, Mask, Base, Index, Scale, Chain);
11993 // XTEST intrinsics.
11994 case Intrinsic::x86_xtest: {
11995 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
11996 SDValue InTrans = DAG.getNode(X86ISD::XTEST, dl, VTs, Op.getOperand(0));
11997 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
11998 DAG.getConstant(X86::COND_NE, MVT::i8),
12000 SDValue Ret = DAG.getNode(ISD::ZERO_EXTEND, dl, Op->getValueType(0), SetCC);
12001 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(),
12002 Ret, SDValue(InTrans.getNode(), 1));
12007 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op,
12008 SelectionDAG &DAG) const {
12009 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
12010 MFI->setReturnAddressIsTaken(true);
12012 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
12014 EVT PtrVT = getPointerTy();
12017 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
12018 const X86RegisterInfo *RegInfo =
12019 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
12020 SDValue Offset = DAG.getConstant(RegInfo->getSlotSize(), PtrVT);
12021 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
12022 DAG.getNode(ISD::ADD, dl, PtrVT,
12023 FrameAddr, Offset),
12024 MachinePointerInfo(), false, false, false, 0);
12027 // Just load the return address.
12028 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
12029 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
12030 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
12033 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
12034 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
12035 MFI->setFrameAddressIsTaken(true);
12037 EVT VT = Op.getValueType();
12038 SDLoc dl(Op); // FIXME probably not meaningful
12039 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
12040 const X86RegisterInfo *RegInfo =
12041 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
12042 unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction());
12043 assert(((FrameReg == X86::RBP && VT == MVT::i64) ||
12044 (FrameReg == X86::EBP && VT == MVT::i32)) &&
12045 "Invalid Frame Register!");
12046 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
12048 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
12049 MachinePointerInfo(),
12050 false, false, false, 0);
12054 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
12055 SelectionDAG &DAG) const {
12056 const X86RegisterInfo *RegInfo =
12057 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
12058 return DAG.getIntPtrConstant(2 * RegInfo->getSlotSize());
12061 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
12062 SDValue Chain = Op.getOperand(0);
12063 SDValue Offset = Op.getOperand(1);
12064 SDValue Handler = Op.getOperand(2);
12067 EVT PtrVT = getPointerTy();
12068 const X86RegisterInfo *RegInfo =
12069 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
12070 unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction());
12071 assert(((FrameReg == X86::RBP && PtrVT == MVT::i64) ||
12072 (FrameReg == X86::EBP && PtrVT == MVT::i32)) &&
12073 "Invalid Frame Register!");
12074 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, PtrVT);
12075 unsigned StoreAddrReg = (PtrVT == MVT::i64) ? X86::RCX : X86::ECX;
12077 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, Frame,
12078 DAG.getIntPtrConstant(RegInfo->getSlotSize()));
12079 StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, StoreAddr, Offset);
12080 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(),
12082 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
12084 return DAG.getNode(X86ISD::EH_RETURN, dl, MVT::Other, Chain,
12085 DAG.getRegister(StoreAddrReg, PtrVT));
12088 SDValue X86TargetLowering::lowerEH_SJLJ_SETJMP(SDValue Op,
12089 SelectionDAG &DAG) const {
12091 return DAG.getNode(X86ISD::EH_SJLJ_SETJMP, DL,
12092 DAG.getVTList(MVT::i32, MVT::Other),
12093 Op.getOperand(0), Op.getOperand(1));
12096 SDValue X86TargetLowering::lowerEH_SJLJ_LONGJMP(SDValue Op,
12097 SelectionDAG &DAG) const {
12099 return DAG.getNode(X86ISD::EH_SJLJ_LONGJMP, DL, MVT::Other,
12100 Op.getOperand(0), Op.getOperand(1));
12103 static SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) {
12104 return Op.getOperand(0);
12107 SDValue X86TargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
12108 SelectionDAG &DAG) const {
12109 SDValue Root = Op.getOperand(0);
12110 SDValue Trmp = Op.getOperand(1); // trampoline
12111 SDValue FPtr = Op.getOperand(2); // nested function
12112 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
12115 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
12116 const TargetRegisterInfo* TRI = getTargetMachine().getRegisterInfo();
12118 if (Subtarget->is64Bit()) {
12119 SDValue OutChains[6];
12121 // Large code-model.
12122 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode.
12123 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode.
12125 const unsigned char N86R10 = TRI->getEncodingValue(X86::R10) & 0x7;
12126 const unsigned char N86R11 = TRI->getEncodingValue(X86::R11) & 0x7;
12128 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
12130 // Load the pointer to the nested function into R11.
12131 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
12132 SDValue Addr = Trmp;
12133 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
12134 Addr, MachinePointerInfo(TrmpAddr),
12137 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
12138 DAG.getConstant(2, MVT::i64));
12139 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr,
12140 MachinePointerInfo(TrmpAddr, 2),
12143 // Load the 'nest' parameter value into R10.
12144 // R10 is specified in X86CallingConv.td
12145 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
12146 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
12147 DAG.getConstant(10, MVT::i64));
12148 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
12149 Addr, MachinePointerInfo(TrmpAddr, 10),
12152 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
12153 DAG.getConstant(12, MVT::i64));
12154 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr,
12155 MachinePointerInfo(TrmpAddr, 12),
12158 // Jump to the nested function.
12159 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
12160 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
12161 DAG.getConstant(20, MVT::i64));
12162 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
12163 Addr, MachinePointerInfo(TrmpAddr, 20),
12166 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
12167 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
12168 DAG.getConstant(22, MVT::i64));
12169 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr,
12170 MachinePointerInfo(TrmpAddr, 22),
12173 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 6);
12175 const Function *Func =
12176 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
12177 CallingConv::ID CC = Func->getCallingConv();
12182 llvm_unreachable("Unsupported calling convention");
12183 case CallingConv::C:
12184 case CallingConv::X86_StdCall: {
12185 // Pass 'nest' parameter in ECX.
12186 // Must be kept in sync with X86CallingConv.td
12187 NestReg = X86::ECX;
12189 // Check that ECX wasn't needed by an 'inreg' parameter.
12190 FunctionType *FTy = Func->getFunctionType();
12191 const AttributeSet &Attrs = Func->getAttributes();
12193 if (!Attrs.isEmpty() && !Func->isVarArg()) {
12194 unsigned InRegCount = 0;
12197 for (FunctionType::param_iterator I = FTy->param_begin(),
12198 E = FTy->param_end(); I != E; ++I, ++Idx)
12199 if (Attrs.hasAttribute(Idx, Attribute::InReg))
12200 // FIXME: should only count parameters that are lowered to integers.
12201 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32;
12203 if (InRegCount > 2) {
12204 report_fatal_error("Nest register in use - reduce number of inreg"
12210 case CallingConv::X86_FastCall:
12211 case CallingConv::X86_ThisCall:
12212 case CallingConv::Fast:
12213 // Pass 'nest' parameter in EAX.
12214 // Must be kept in sync with X86CallingConv.td
12215 NestReg = X86::EAX;
12219 SDValue OutChains[4];
12220 SDValue Addr, Disp;
12222 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
12223 DAG.getConstant(10, MVT::i32));
12224 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
12226 // This is storing the opcode for MOV32ri.
12227 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte.
12228 const unsigned char N86Reg = TRI->getEncodingValue(NestReg) & 0x7;
12229 OutChains[0] = DAG.getStore(Root, dl,
12230 DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
12231 Trmp, MachinePointerInfo(TrmpAddr),
12234 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
12235 DAG.getConstant(1, MVT::i32));
12236 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr,
12237 MachinePointerInfo(TrmpAddr, 1),
12240 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode.
12241 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
12242 DAG.getConstant(5, MVT::i32));
12243 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr,
12244 MachinePointerInfo(TrmpAddr, 5),
12247 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
12248 DAG.getConstant(6, MVT::i32));
12249 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr,
12250 MachinePointerInfo(TrmpAddr, 6),
12253 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 4);
12257 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op,
12258 SelectionDAG &DAG) const {
12260 The rounding mode is in bits 11:10 of FPSR, and has the following
12262 00 Round to nearest
12267 FLT_ROUNDS, on the other hand, expects the following:
12274 To perform the conversion, we do:
12275 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
12278 MachineFunction &MF = DAG.getMachineFunction();
12279 const TargetMachine &TM = MF.getTarget();
12280 const TargetFrameLowering &TFI = *TM.getFrameLowering();
12281 unsigned StackAlignment = TFI.getStackAlignment();
12282 EVT VT = Op.getValueType();
12285 // Save FP Control Word to stack slot
12286 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false);
12287 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
12289 MachineMemOperand *MMO =
12290 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
12291 MachineMemOperand::MOStore, 2, 2);
12293 SDValue Ops[] = { DAG.getEntryNode(), StackSlot };
12294 SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL,
12295 DAG.getVTList(MVT::Other),
12296 Ops, array_lengthof(Ops), MVT::i16,
12299 // Load FP Control Word from stack slot
12300 SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot,
12301 MachinePointerInfo(), false, false, false, 0);
12303 // Transform as necessary
12305 DAG.getNode(ISD::SRL, DL, MVT::i16,
12306 DAG.getNode(ISD::AND, DL, MVT::i16,
12307 CWD, DAG.getConstant(0x800, MVT::i16)),
12308 DAG.getConstant(11, MVT::i8));
12310 DAG.getNode(ISD::SRL, DL, MVT::i16,
12311 DAG.getNode(ISD::AND, DL, MVT::i16,
12312 CWD, DAG.getConstant(0x400, MVT::i16)),
12313 DAG.getConstant(9, MVT::i8));
12316 DAG.getNode(ISD::AND, DL, MVT::i16,
12317 DAG.getNode(ISD::ADD, DL, MVT::i16,
12318 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2),
12319 DAG.getConstant(1, MVT::i16)),
12320 DAG.getConstant(3, MVT::i16));
12322 return DAG.getNode((VT.getSizeInBits() < 16 ?
12323 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal);
12326 static SDValue LowerCTLZ(SDValue Op, SelectionDAG &DAG) {
12327 EVT VT = Op.getValueType();
12329 unsigned NumBits = VT.getSizeInBits();
12332 Op = Op.getOperand(0);
12333 if (VT == MVT::i8) {
12334 // Zero extend to i32 since there is not an i8 bsr.
12336 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
12339 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
12340 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
12341 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
12343 // If src is zero (i.e. bsr sets ZF), returns NumBits.
12346 DAG.getConstant(NumBits+NumBits-1, OpVT),
12347 DAG.getConstant(X86::COND_E, MVT::i8),
12350 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops, array_lengthof(Ops));
12352 // Finally xor with NumBits-1.
12353 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
12356 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
12360 static SDValue LowerCTLZ_ZERO_UNDEF(SDValue Op, SelectionDAG &DAG) {
12361 EVT VT = Op.getValueType();
12363 unsigned NumBits = VT.getSizeInBits();
12366 Op = Op.getOperand(0);
12367 if (VT == MVT::i8) {
12368 // Zero extend to i32 since there is not an i8 bsr.
12370 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
12373 // Issue a bsr (scan bits in reverse).
12374 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
12375 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
12377 // And xor with NumBits-1.
12378 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
12381 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
12385 static SDValue LowerCTTZ(SDValue Op, SelectionDAG &DAG) {
12386 EVT VT = Op.getValueType();
12387 unsigned NumBits = VT.getSizeInBits();
12389 Op = Op.getOperand(0);
12391 // Issue a bsf (scan bits forward) which also sets EFLAGS.
12392 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
12393 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op);
12395 // If src is zero (i.e. bsf sets ZF), returns NumBits.
12398 DAG.getConstant(NumBits, VT),
12399 DAG.getConstant(X86::COND_E, MVT::i8),
12402 return DAG.getNode(X86ISD::CMOV, dl, VT, Ops, array_lengthof(Ops));
12405 // Lower256IntArith - Break a 256-bit integer operation into two new 128-bit
12406 // ones, and then concatenate the result back.
12407 static SDValue Lower256IntArith(SDValue Op, SelectionDAG &DAG) {
12408 EVT VT = Op.getValueType();
12410 assert(VT.is256BitVector() && VT.isInteger() &&
12411 "Unsupported value type for operation");
12413 unsigned NumElems = VT.getVectorNumElements();
12416 // Extract the LHS vectors
12417 SDValue LHS = Op.getOperand(0);
12418 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
12419 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
12421 // Extract the RHS vectors
12422 SDValue RHS = Op.getOperand(1);
12423 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
12424 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
12426 MVT EltVT = VT.getVectorElementType().getSimpleVT();
12427 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
12429 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
12430 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1),
12431 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2));
12434 static SDValue LowerADD(SDValue Op, SelectionDAG &DAG) {
12435 assert(Op.getValueType().is256BitVector() &&
12436 Op.getValueType().isInteger() &&
12437 "Only handle AVX 256-bit vector integer operation");
12438 return Lower256IntArith(Op, DAG);
12441 static SDValue LowerSUB(SDValue Op, SelectionDAG &DAG) {
12442 assert(Op.getValueType().is256BitVector() &&
12443 Op.getValueType().isInteger() &&
12444 "Only handle AVX 256-bit vector integer operation");
12445 return Lower256IntArith(Op, DAG);
12448 static SDValue LowerMUL(SDValue Op, const X86Subtarget *Subtarget,
12449 SelectionDAG &DAG) {
12451 EVT VT = Op.getValueType();
12453 // Decompose 256-bit ops into smaller 128-bit ops.
12454 if (VT.is256BitVector() && !Subtarget->hasInt256())
12455 return Lower256IntArith(Op, DAG);
12457 SDValue A = Op.getOperand(0);
12458 SDValue B = Op.getOperand(1);
12460 // Lower v4i32 mul as 2x shuffle, 2x pmuludq, 2x shuffle.
12461 if (VT == MVT::v4i32) {
12462 assert(Subtarget->hasSSE2() && !Subtarget->hasSSE41() &&
12463 "Should not custom lower when pmuldq is available!");
12465 // Extract the odd parts.
12466 static const int UnpackMask[] = { 1, -1, 3, -1 };
12467 SDValue Aodds = DAG.getVectorShuffle(VT, dl, A, A, UnpackMask);
12468 SDValue Bodds = DAG.getVectorShuffle(VT, dl, B, B, UnpackMask);
12470 // Multiply the even parts.
12471 SDValue Evens = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, A, B);
12472 // Now multiply odd parts.
12473 SDValue Odds = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, Aodds, Bodds);
12475 Evens = DAG.getNode(ISD::BITCAST, dl, VT, Evens);
12476 Odds = DAG.getNode(ISD::BITCAST, dl, VT, Odds);
12478 // Merge the two vectors back together with a shuffle. This expands into 2
12480 static const int ShufMask[] = { 0, 4, 2, 6 };
12481 return DAG.getVectorShuffle(VT, dl, Evens, Odds, ShufMask);
12484 assert((VT == MVT::v2i64 || VT == MVT::v4i64 || VT == MVT::v8i64) &&
12485 "Only know how to lower V2I64/V4I64/V8I64 multiply");
12487 // Ahi = psrlqi(a, 32);
12488 // Bhi = psrlqi(b, 32);
12490 // AloBlo = pmuludq(a, b);
12491 // AloBhi = pmuludq(a, Bhi);
12492 // AhiBlo = pmuludq(Ahi, b);
12494 // AloBhi = psllqi(AloBhi, 32);
12495 // AhiBlo = psllqi(AhiBlo, 32);
12496 // return AloBlo + AloBhi + AhiBlo;
12498 SDValue Ahi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, A, 32, DAG);
12499 SDValue Bhi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, B, 32, DAG);
12501 // Bit cast to 32-bit vectors for MULUDQ
12502 EVT MulVT = (VT == MVT::v2i64) ? MVT::v4i32 :
12503 (VT == MVT::v4i64) ? MVT::v8i32 : MVT::v16i32;
12504 A = DAG.getNode(ISD::BITCAST, dl, MulVT, A);
12505 B = DAG.getNode(ISD::BITCAST, dl, MulVT, B);
12506 Ahi = DAG.getNode(ISD::BITCAST, dl, MulVT, Ahi);
12507 Bhi = DAG.getNode(ISD::BITCAST, dl, MulVT, Bhi);
12509 SDValue AloBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, B);
12510 SDValue AloBhi = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, Bhi);
12511 SDValue AhiBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, Ahi, B);
12513 AloBhi = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AloBhi, 32, DAG);
12514 AhiBlo = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AhiBlo, 32, DAG);
12516 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
12517 return DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
12520 static SDValue LowerSDIV(SDValue Op, SelectionDAG &DAG) {
12521 EVT VT = Op.getValueType();
12522 EVT EltTy = VT.getVectorElementType();
12523 unsigned NumElts = VT.getVectorNumElements();
12524 SDValue N0 = Op.getOperand(0);
12527 // Lower sdiv X, pow2-const.
12528 BuildVectorSDNode *C = dyn_cast<BuildVectorSDNode>(Op.getOperand(1));
12532 APInt SplatValue, SplatUndef;
12533 unsigned SplatBitSize;
12535 if (!C->isConstantSplat(SplatValue, SplatUndef, SplatBitSize,
12537 EltTy.getSizeInBits() < SplatBitSize)
12540 if ((SplatValue != 0) &&
12541 (SplatValue.isPowerOf2() || (-SplatValue).isPowerOf2())) {
12542 unsigned Lg2 = SplatValue.countTrailingZeros();
12543 // Splat the sign bit.
12544 SmallVector<SDValue, 16> Sz(NumElts,
12545 DAG.getConstant(EltTy.getSizeInBits() - 1,
12547 SDValue SGN = DAG.getNode(ISD::SRA, dl, VT, N0,
12548 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Sz[0],
12550 // Add (N0 < 0) ? abs2 - 1 : 0;
12551 SmallVector<SDValue, 16> Amt(NumElts,
12552 DAG.getConstant(EltTy.getSizeInBits() - Lg2,
12554 SDValue SRL = DAG.getNode(ISD::SRL, dl, VT, SGN,
12555 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Amt[0],
12557 SDValue ADD = DAG.getNode(ISD::ADD, dl, VT, N0, SRL);
12558 SmallVector<SDValue, 16> Lg2Amt(NumElts, DAG.getConstant(Lg2, EltTy));
12559 SDValue SRA = DAG.getNode(ISD::SRA, dl, VT, ADD,
12560 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Lg2Amt[0],
12563 // If we're dividing by a positive value, we're done. Otherwise, we must
12564 // negate the result.
12565 if (SplatValue.isNonNegative())
12568 SmallVector<SDValue, 16> V(NumElts, DAG.getConstant(0, EltTy));
12569 SDValue Zero = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], NumElts);
12570 return DAG.getNode(ISD::SUB, dl, VT, Zero, SRA);
12575 static SDValue LowerScalarImmediateShift(SDValue Op, SelectionDAG &DAG,
12576 const X86Subtarget *Subtarget) {
12577 EVT VT = Op.getValueType();
12579 SDValue R = Op.getOperand(0);
12580 SDValue Amt = Op.getOperand(1);
12582 // Optimize shl/srl/sra with constant shift amount.
12583 if (isSplatVector(Amt.getNode())) {
12584 SDValue SclrAmt = Amt->getOperand(0);
12585 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(SclrAmt)) {
12586 uint64_t ShiftAmt = C->getZExtValue();
12588 if (VT == MVT::v2i64 || VT == MVT::v4i32 || VT == MVT::v8i16 ||
12589 (Subtarget->hasInt256() &&
12590 (VT == MVT::v4i64 || VT == MVT::v8i32 || VT == MVT::v16i16)) ||
12591 (Subtarget->hasAVX512() &&
12592 (VT == MVT::v8i64 || VT == MVT::v16i32))) {
12593 if (Op.getOpcode() == ISD::SHL)
12594 return getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, R, ShiftAmt,
12596 if (Op.getOpcode() == ISD::SRL)
12597 return getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, R, ShiftAmt,
12599 if (Op.getOpcode() == ISD::SRA && VT != MVT::v2i64 && VT != MVT::v4i64)
12600 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, R, ShiftAmt,
12604 if (VT == MVT::v16i8) {
12605 if (Op.getOpcode() == ISD::SHL) {
12606 // Make a large shift.
12607 SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl,
12608 MVT::v8i16, R, ShiftAmt,
12610 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
12611 // Zero out the rightmost bits.
12612 SmallVector<SDValue, 16> V(16,
12613 DAG.getConstant(uint8_t(-1U << ShiftAmt),
12615 return DAG.getNode(ISD::AND, dl, VT, SHL,
12616 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16));
12618 if (Op.getOpcode() == ISD::SRL) {
12619 // Make a large shift.
12620 SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl,
12621 MVT::v8i16, R, ShiftAmt,
12623 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
12624 // Zero out the leftmost bits.
12625 SmallVector<SDValue, 16> V(16,
12626 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
12628 return DAG.getNode(ISD::AND, dl, VT, SRL,
12629 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16));
12631 if (Op.getOpcode() == ISD::SRA) {
12632 if (ShiftAmt == 7) {
12633 // R s>> 7 === R s< 0
12634 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
12635 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
12638 // R s>> a === ((R u>> a) ^ m) - m
12639 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
12640 SmallVector<SDValue, 16> V(16, DAG.getConstant(128 >> ShiftAmt,
12642 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16);
12643 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
12644 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
12647 llvm_unreachable("Unknown shift opcode.");
12650 if (Subtarget->hasInt256() && VT == MVT::v32i8) {
12651 if (Op.getOpcode() == ISD::SHL) {
12652 // Make a large shift.
12653 SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl,
12654 MVT::v16i16, R, ShiftAmt,
12656 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
12657 // Zero out the rightmost bits.
12658 SmallVector<SDValue, 32> V(32,
12659 DAG.getConstant(uint8_t(-1U << ShiftAmt),
12661 return DAG.getNode(ISD::AND, dl, VT, SHL,
12662 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32));
12664 if (Op.getOpcode() == ISD::SRL) {
12665 // Make a large shift.
12666 SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl,
12667 MVT::v16i16, R, ShiftAmt,
12669 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
12670 // Zero out the leftmost bits.
12671 SmallVector<SDValue, 32> V(32,
12672 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
12674 return DAG.getNode(ISD::AND, dl, VT, SRL,
12675 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32));
12677 if (Op.getOpcode() == ISD::SRA) {
12678 if (ShiftAmt == 7) {
12679 // R s>> 7 === R s< 0
12680 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
12681 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
12684 // R s>> a === ((R u>> a) ^ m) - m
12685 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
12686 SmallVector<SDValue, 32> V(32, DAG.getConstant(128 >> ShiftAmt,
12688 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32);
12689 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
12690 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
12693 llvm_unreachable("Unknown shift opcode.");
12698 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
12699 if (!Subtarget->is64Bit() &&
12700 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64)) &&
12701 Amt.getOpcode() == ISD::BITCAST &&
12702 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
12703 Amt = Amt.getOperand(0);
12704 unsigned Ratio = Amt.getValueType().getVectorNumElements() /
12705 VT.getVectorNumElements();
12706 unsigned RatioInLog2 = Log2_32_Ceil(Ratio);
12707 uint64_t ShiftAmt = 0;
12708 for (unsigned i = 0; i != Ratio; ++i) {
12709 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Amt.getOperand(i));
12713 ShiftAmt |= C->getZExtValue() << (i * (1 << (6 - RatioInLog2)));
12715 // Check remaining shift amounts.
12716 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
12717 uint64_t ShAmt = 0;
12718 for (unsigned j = 0; j != Ratio; ++j) {
12719 ConstantSDNode *C =
12720 dyn_cast<ConstantSDNode>(Amt.getOperand(i + j));
12724 ShAmt |= C->getZExtValue() << (j * (1 << (6 - RatioInLog2)));
12726 if (ShAmt != ShiftAmt)
12729 switch (Op.getOpcode()) {
12731 llvm_unreachable("Unknown shift opcode!");
12733 return getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, R, ShiftAmt,
12736 return getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, R, ShiftAmt,
12739 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, R, ShiftAmt,
12747 static SDValue LowerScalarVariableShift(SDValue Op, SelectionDAG &DAG,
12748 const X86Subtarget* Subtarget) {
12749 EVT VT = Op.getValueType();
12751 SDValue R = Op.getOperand(0);
12752 SDValue Amt = Op.getOperand(1);
12754 if ((VT == MVT::v2i64 && Op.getOpcode() != ISD::SRA) ||
12755 VT == MVT::v4i32 || VT == MVT::v8i16 ||
12756 (Subtarget->hasInt256() &&
12757 ((VT == MVT::v4i64 && Op.getOpcode() != ISD::SRA) ||
12758 VT == MVT::v8i32 || VT == MVT::v16i16)) ||
12759 (Subtarget->hasAVX512() && (VT == MVT::v8i64 || VT == MVT::v16i32))) {
12761 EVT EltVT = VT.getVectorElementType();
12763 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
12764 unsigned NumElts = VT.getVectorNumElements();
12766 for (i = 0; i != NumElts; ++i) {
12767 if (Amt.getOperand(i).getOpcode() == ISD::UNDEF)
12771 for (j = i; j != NumElts; ++j) {
12772 SDValue Arg = Amt.getOperand(j);
12773 if (Arg.getOpcode() == ISD::UNDEF) continue;
12774 if (Arg != Amt.getOperand(i))
12777 if (i != NumElts && j == NumElts)
12778 BaseShAmt = Amt.getOperand(i);
12780 if (Amt.getOpcode() == ISD::EXTRACT_SUBVECTOR)
12781 Amt = Amt.getOperand(0);
12782 if (Amt.getOpcode() == ISD::VECTOR_SHUFFLE &&
12783 cast<ShuffleVectorSDNode>(Amt)->isSplat()) {
12784 SDValue InVec = Amt.getOperand(0);
12785 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
12786 unsigned NumElts = InVec.getValueType().getVectorNumElements();
12788 for (; i != NumElts; ++i) {
12789 SDValue Arg = InVec.getOperand(i);
12790 if (Arg.getOpcode() == ISD::UNDEF) continue;
12794 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
12795 if (ConstantSDNode *C =
12796 dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
12797 unsigned SplatIdx =
12798 cast<ShuffleVectorSDNode>(Amt)->getSplatIndex();
12799 if (C->getZExtValue() == SplatIdx)
12800 BaseShAmt = InVec.getOperand(1);
12803 if (BaseShAmt.getNode() == 0)
12804 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Amt,
12805 DAG.getIntPtrConstant(0));
12809 if (BaseShAmt.getNode()) {
12810 if (EltVT.bitsGT(MVT::i32))
12811 BaseShAmt = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, BaseShAmt);
12812 else if (EltVT.bitsLT(MVT::i32))
12813 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, BaseShAmt);
12815 switch (Op.getOpcode()) {
12817 llvm_unreachable("Unknown shift opcode!");
12819 switch (VT.getSimpleVT().SimpleTy) {
12820 default: return SDValue();
12829 return getTargetVShiftNode(X86ISD::VSHLI, dl, VT, R, BaseShAmt, DAG);
12832 switch (VT.getSimpleVT().SimpleTy) {
12833 default: return SDValue();
12840 return getTargetVShiftNode(X86ISD::VSRAI, dl, VT, R, BaseShAmt, DAG);
12843 switch (VT.getSimpleVT().SimpleTy) {
12844 default: return SDValue();
12853 return getTargetVShiftNode(X86ISD::VSRLI, dl, VT, R, BaseShAmt, DAG);
12859 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
12860 if (!Subtarget->is64Bit() &&
12861 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64) ||
12862 (Subtarget->hasAVX512() && VT == MVT::v8i64)) &&
12863 Amt.getOpcode() == ISD::BITCAST &&
12864 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
12865 Amt = Amt.getOperand(0);
12866 unsigned Ratio = Amt.getValueType().getVectorNumElements() /
12867 VT.getVectorNumElements();
12868 std::vector<SDValue> Vals(Ratio);
12869 for (unsigned i = 0; i != Ratio; ++i)
12870 Vals[i] = Amt.getOperand(i);
12871 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
12872 for (unsigned j = 0; j != Ratio; ++j)
12873 if (Vals[j] != Amt.getOperand(i + j))
12876 switch (Op.getOpcode()) {
12878 llvm_unreachable("Unknown shift opcode!");
12880 return DAG.getNode(X86ISD::VSHL, dl, VT, R, Op.getOperand(1));
12882 return DAG.getNode(X86ISD::VSRL, dl, VT, R, Op.getOperand(1));
12884 return DAG.getNode(X86ISD::VSRA, dl, VT, R, Op.getOperand(1));
12891 static SDValue LowerShift(SDValue Op, const X86Subtarget* Subtarget,
12892 SelectionDAG &DAG) {
12894 EVT VT = Op.getValueType();
12896 SDValue R = Op.getOperand(0);
12897 SDValue Amt = Op.getOperand(1);
12900 if (!Subtarget->hasSSE2())
12903 V = LowerScalarImmediateShift(Op, DAG, Subtarget);
12907 V = LowerScalarVariableShift(Op, DAG, Subtarget);
12911 if (Subtarget->hasAVX512() && (VT == MVT::v16i32 || VT == MVT::v8i64))
12913 // AVX2 has VPSLLV/VPSRAV/VPSRLV.
12914 if (Subtarget->hasInt256()) {
12915 if (Op.getOpcode() == ISD::SRL &&
12916 (VT == MVT::v2i64 || VT == MVT::v4i32 ||
12917 VT == MVT::v4i64 || VT == MVT::v8i32))
12919 if (Op.getOpcode() == ISD::SHL &&
12920 (VT == MVT::v2i64 || VT == MVT::v4i32 ||
12921 VT == MVT::v4i64 || VT == MVT::v8i32))
12923 if (Op.getOpcode() == ISD::SRA && (VT == MVT::v4i32 || VT == MVT::v8i32))
12927 // Lower SHL with variable shift amount.
12928 if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) {
12929 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(23, VT));
12931 Op = DAG.getNode(ISD::ADD, dl, VT, Op, DAG.getConstant(0x3f800000U, VT));
12932 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, Op);
12933 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op);
12934 return DAG.getNode(ISD::MUL, dl, VT, Op, R);
12936 if (VT == MVT::v16i8 && Op->getOpcode() == ISD::SHL) {
12937 assert(Subtarget->hasSSE2() && "Need SSE2 for pslli/pcmpeq.");
12940 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(5, VT));
12941 Op = DAG.getNode(ISD::BITCAST, dl, VT, Op);
12943 // Turn 'a' into a mask suitable for VSELECT
12944 SDValue VSelM = DAG.getConstant(0x80, VT);
12945 SDValue OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
12946 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
12948 SDValue CM1 = DAG.getConstant(0x0f, VT);
12949 SDValue CM2 = DAG.getConstant(0x3f, VT);
12951 // r = VSELECT(r, psllw(r & (char16)15, 4), a);
12952 SDValue M = DAG.getNode(ISD::AND, dl, VT, R, CM1);
12953 M = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, MVT::v8i16, M, 4, DAG);
12954 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
12955 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
12958 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
12959 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
12960 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
12962 // r = VSELECT(r, psllw(r & (char16)63, 2), a);
12963 M = DAG.getNode(ISD::AND, dl, VT, R, CM2);
12964 M = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, MVT::v8i16, M, 2, DAG);
12965 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
12966 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
12969 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
12970 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
12971 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
12973 // return VSELECT(r, r+r, a);
12974 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel,
12975 DAG.getNode(ISD::ADD, dl, VT, R, R), R);
12979 // Decompose 256-bit shifts into smaller 128-bit shifts.
12980 if (VT.is256BitVector()) {
12981 unsigned NumElems = VT.getVectorNumElements();
12982 MVT EltVT = VT.getVectorElementType().getSimpleVT();
12983 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
12985 // Extract the two vectors
12986 SDValue V1 = Extract128BitVector(R, 0, DAG, dl);
12987 SDValue V2 = Extract128BitVector(R, NumElems/2, DAG, dl);
12989 // Recreate the shift amount vectors
12990 SDValue Amt1, Amt2;
12991 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
12992 // Constant shift amount
12993 SmallVector<SDValue, 4> Amt1Csts;
12994 SmallVector<SDValue, 4> Amt2Csts;
12995 for (unsigned i = 0; i != NumElems/2; ++i)
12996 Amt1Csts.push_back(Amt->getOperand(i));
12997 for (unsigned i = NumElems/2; i != NumElems; ++i)
12998 Amt2Csts.push_back(Amt->getOperand(i));
13000 Amt1 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT,
13001 &Amt1Csts[0], NumElems/2);
13002 Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT,
13003 &Amt2Csts[0], NumElems/2);
13005 // Variable shift amount
13006 Amt1 = Extract128BitVector(Amt, 0, DAG, dl);
13007 Amt2 = Extract128BitVector(Amt, NumElems/2, DAG, dl);
13010 // Issue new vector shifts for the smaller types
13011 V1 = DAG.getNode(Op.getOpcode(), dl, NewVT, V1, Amt1);
13012 V2 = DAG.getNode(Op.getOpcode(), dl, NewVT, V2, Amt2);
13014 // Concatenate the result back
13015 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, V1, V2);
13021 static SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) {
13022 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
13023 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
13024 // looks for this combo and may remove the "setcc" instruction if the "setcc"
13025 // has only one use.
13026 SDNode *N = Op.getNode();
13027 SDValue LHS = N->getOperand(0);
13028 SDValue RHS = N->getOperand(1);
13029 unsigned BaseOp = 0;
13032 switch (Op.getOpcode()) {
13033 default: llvm_unreachable("Unknown ovf instruction!");
13035 // A subtract of one will be selected as a INC. Note that INC doesn't
13036 // set CF, so we can't do this for UADDO.
13037 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
13039 BaseOp = X86ISD::INC;
13040 Cond = X86::COND_O;
13043 BaseOp = X86ISD::ADD;
13044 Cond = X86::COND_O;
13047 BaseOp = X86ISD::ADD;
13048 Cond = X86::COND_B;
13051 // A subtract of one will be selected as a DEC. Note that DEC doesn't
13052 // set CF, so we can't do this for USUBO.
13053 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
13055 BaseOp = X86ISD::DEC;
13056 Cond = X86::COND_O;
13059 BaseOp = X86ISD::SUB;
13060 Cond = X86::COND_O;
13063 BaseOp = X86ISD::SUB;
13064 Cond = X86::COND_B;
13067 BaseOp = X86ISD::SMUL;
13068 Cond = X86::COND_O;
13070 case ISD::UMULO: { // i64, i8 = umulo lhs, rhs --> i64, i64, i32 umul lhs,rhs
13071 SDVTList VTs = DAG.getVTList(N->getValueType(0), N->getValueType(0),
13073 SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS);
13076 DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
13077 DAG.getConstant(X86::COND_O, MVT::i32),
13078 SDValue(Sum.getNode(), 2));
13080 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
13084 // Also sets EFLAGS.
13085 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
13086 SDValue Sum = DAG.getNode(BaseOp, DL, VTs, LHS, RHS);
13089 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1),
13090 DAG.getConstant(Cond, MVT::i32),
13091 SDValue(Sum.getNode(), 1));
13093 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
13096 SDValue X86TargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
13097 SelectionDAG &DAG) const {
13099 EVT ExtraVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
13100 EVT VT = Op.getValueType();
13102 if (!Subtarget->hasSSE2() || !VT.isVector())
13105 unsigned BitsDiff = VT.getScalarType().getSizeInBits() -
13106 ExtraVT.getScalarType().getSizeInBits();
13108 switch (VT.getSimpleVT().SimpleTy) {
13109 default: return SDValue();
13112 if (!Subtarget->hasFp256())
13114 if (!Subtarget->hasInt256()) {
13115 // needs to be split
13116 unsigned NumElems = VT.getVectorNumElements();
13118 // Extract the LHS vectors
13119 SDValue LHS = Op.getOperand(0);
13120 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
13121 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
13123 MVT EltVT = VT.getVectorElementType().getSimpleVT();
13124 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
13126 EVT ExtraEltVT = ExtraVT.getVectorElementType();
13127 unsigned ExtraNumElems = ExtraVT.getVectorNumElements();
13128 ExtraVT = EVT::getVectorVT(*DAG.getContext(), ExtraEltVT,
13130 SDValue Extra = DAG.getValueType(ExtraVT);
13132 LHS1 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, Extra);
13133 LHS2 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, Extra);
13135 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, LHS1, LHS2);
13140 // (sext (vzext x)) -> (vsext x)
13141 SDValue Op0 = Op.getOperand(0);
13142 SDValue Op00 = Op0.getOperand(0);
13144 // Hopefully, this VECTOR_SHUFFLE is just a VZEXT.
13145 if (Op0.getOpcode() == ISD::BITCAST &&
13146 Op00.getOpcode() == ISD::VECTOR_SHUFFLE)
13147 Tmp1 = LowerVectorIntExtend(Op00, Subtarget, DAG);
13148 if (Tmp1.getNode()) {
13149 SDValue Tmp1Op0 = Tmp1.getOperand(0);
13150 assert(Tmp1Op0.getOpcode() == X86ISD::VZEXT &&
13151 "This optimization is invalid without a VZEXT.");
13152 return DAG.getNode(X86ISD::VSEXT, dl, VT, Tmp1Op0.getOperand(0));
13155 // If the above didn't work, then just use Shift-Left + Shift-Right.
13156 Tmp1 = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, Op0, BitsDiff,
13158 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, Tmp1, BitsDiff,
13164 static SDValue LowerATOMIC_FENCE(SDValue Op, const X86Subtarget *Subtarget,
13165 SelectionDAG &DAG) {
13167 AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>(
13168 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue());
13169 SynchronizationScope FenceScope = static_cast<SynchronizationScope>(
13170 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
13172 // The only fence that needs an instruction is a sequentially-consistent
13173 // cross-thread fence.
13174 if (FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread) {
13175 // Use mfence if we have SSE2 or we're on x86-64 (even if we asked for
13176 // no-sse2). There isn't any reason to disable it if the target processor
13178 if (Subtarget->hasSSE2() || Subtarget->is64Bit())
13179 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
13181 SDValue Chain = Op.getOperand(0);
13182 SDValue Zero = DAG.getConstant(0, MVT::i32);
13184 DAG.getRegister(X86::ESP, MVT::i32), // Base
13185 DAG.getTargetConstant(1, MVT::i8), // Scale
13186 DAG.getRegister(0, MVT::i32), // Index
13187 DAG.getTargetConstant(0, MVT::i32), // Disp
13188 DAG.getRegister(0, MVT::i32), // Segment.
13192 SDNode *Res = DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops);
13193 return SDValue(Res, 0);
13196 // MEMBARRIER is a compiler barrier; it codegens to a no-op.
13197 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
13200 static SDValue LowerCMP_SWAP(SDValue Op, const X86Subtarget *Subtarget,
13201 SelectionDAG &DAG) {
13202 EVT T = Op.getValueType();
13206 switch(T.getSimpleVT().SimpleTy) {
13207 default: llvm_unreachable("Invalid value type!");
13208 case MVT::i8: Reg = X86::AL; size = 1; break;
13209 case MVT::i16: Reg = X86::AX; size = 2; break;
13210 case MVT::i32: Reg = X86::EAX; size = 4; break;
13212 assert(Subtarget->is64Bit() && "Node not type legal!");
13213 Reg = X86::RAX; size = 8;
13216 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg,
13217 Op.getOperand(2), SDValue());
13218 SDValue Ops[] = { cpIn.getValue(0),
13221 DAG.getTargetConstant(size, MVT::i8),
13222 cpIn.getValue(1) };
13223 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
13224 MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand();
13225 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys,
13226 Ops, array_lengthof(Ops), T, MMO);
13228 DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1));
13232 static SDValue LowerREADCYCLECOUNTER(SDValue Op, const X86Subtarget *Subtarget,
13233 SelectionDAG &DAG) {
13234 assert(Subtarget->is64Bit() && "Result not type legalized?");
13235 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
13236 SDValue TheChain = Op.getOperand(0);
13238 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
13239 SDValue rax = DAG.getCopyFromReg(rd, dl, X86::RAX, MVT::i64, rd.getValue(1));
13240 SDValue rdx = DAG.getCopyFromReg(rax.getValue(1), dl, X86::RDX, MVT::i64,
13242 SDValue Tmp = DAG.getNode(ISD::SHL, dl, MVT::i64, rdx,
13243 DAG.getConstant(32, MVT::i8));
13245 DAG.getNode(ISD::OR, dl, MVT::i64, rax, Tmp),
13248 return DAG.getMergeValues(Ops, array_lengthof(Ops), dl);
13251 static SDValue LowerBITCAST(SDValue Op, const X86Subtarget *Subtarget,
13252 SelectionDAG &DAG) {
13253 MVT SrcVT = Op.getOperand(0).getSimpleValueType();
13254 MVT DstVT = Op.getSimpleValueType();
13255 assert(Subtarget->is64Bit() && !Subtarget->hasSSE2() &&
13256 Subtarget->hasMMX() && "Unexpected custom BITCAST");
13257 assert((DstVT == MVT::i64 ||
13258 (DstVT.isVector() && DstVT.getSizeInBits()==64)) &&
13259 "Unexpected custom BITCAST");
13260 // i64 <=> MMX conversions are Legal.
13261 if (SrcVT==MVT::i64 && DstVT.isVector())
13263 if (DstVT==MVT::i64 && SrcVT.isVector())
13265 // MMX <=> MMX conversions are Legal.
13266 if (SrcVT.isVector() && DstVT.isVector())
13268 // All other conversions need to be expanded.
13272 static SDValue LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) {
13273 SDNode *Node = Op.getNode();
13275 EVT T = Node->getValueType(0);
13276 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
13277 DAG.getConstant(0, T), Node->getOperand(2));
13278 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
13279 cast<AtomicSDNode>(Node)->getMemoryVT(),
13280 Node->getOperand(0),
13281 Node->getOperand(1), negOp,
13282 cast<AtomicSDNode>(Node)->getSrcValue(),
13283 cast<AtomicSDNode>(Node)->getAlignment(),
13284 cast<AtomicSDNode>(Node)->getOrdering(),
13285 cast<AtomicSDNode>(Node)->getSynchScope());
13288 static SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) {
13289 SDNode *Node = Op.getNode();
13291 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
13293 // Convert seq_cst store -> xchg
13294 // Convert wide store -> swap (-> cmpxchg8b/cmpxchg16b)
13295 // FIXME: On 32-bit, store -> fist or movq would be more efficient
13296 // (The only way to get a 16-byte store is cmpxchg16b)
13297 // FIXME: 16-byte ATOMIC_SWAP isn't actually hooked up at the moment.
13298 if (cast<AtomicSDNode>(Node)->getOrdering() == SequentiallyConsistent ||
13299 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
13300 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
13301 cast<AtomicSDNode>(Node)->getMemoryVT(),
13302 Node->getOperand(0),
13303 Node->getOperand(1), Node->getOperand(2),
13304 cast<AtomicSDNode>(Node)->getMemOperand(),
13305 cast<AtomicSDNode>(Node)->getOrdering(),
13306 cast<AtomicSDNode>(Node)->getSynchScope());
13307 return Swap.getValue(1);
13309 // Other atomic stores have a simple pattern.
13313 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
13314 EVT VT = Op.getNode()->getValueType(0);
13316 // Let legalize expand this if it isn't a legal type yet.
13317 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
13320 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
13323 bool ExtraOp = false;
13324 switch (Op.getOpcode()) {
13325 default: llvm_unreachable("Invalid code");
13326 case ISD::ADDC: Opc = X86ISD::ADD; break;
13327 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break;
13328 case ISD::SUBC: Opc = X86ISD::SUB; break;
13329 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break;
13333 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
13335 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
13336 Op.getOperand(1), Op.getOperand(2));
13339 static SDValue LowerFSINCOS(SDValue Op, const X86Subtarget *Subtarget,
13340 SelectionDAG &DAG) {
13341 assert(Subtarget->isTargetDarwin() && Subtarget->is64Bit());
13343 // For MacOSX, we want to call an alternative entry point: __sincos_stret,
13344 // which returns the values as { float, float } (in XMM0) or
13345 // { double, double } (which is returned in XMM0, XMM1).
13347 SDValue Arg = Op.getOperand(0);
13348 EVT ArgVT = Arg.getValueType();
13349 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
13351 TargetLowering::ArgListTy Args;
13352 TargetLowering::ArgListEntry Entry;
13356 Entry.isSExt = false;
13357 Entry.isZExt = false;
13358 Args.push_back(Entry);
13360 bool isF64 = ArgVT == MVT::f64;
13361 // Only optimize x86_64 for now. i386 is a bit messy. For f32,
13362 // the small struct {f32, f32} is returned in (eax, edx). For f64,
13363 // the results are returned via SRet in memory.
13364 const char *LibcallName = isF64 ? "__sincos_stret" : "__sincosf_stret";
13365 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13366 SDValue Callee = DAG.getExternalSymbol(LibcallName, TLI.getPointerTy());
13368 Type *RetTy = isF64
13369 ? (Type*)StructType::get(ArgTy, ArgTy, NULL)
13370 : (Type*)VectorType::get(ArgTy, 4);
13372 CallLoweringInfo CLI(DAG.getEntryNode(), RetTy,
13373 false, false, false, false, 0,
13374 CallingConv::C, /*isTaillCall=*/false,
13375 /*doesNotRet=*/false, /*isReturnValueUsed*/true,
13376 Callee, Args, DAG, dl);
13377 std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI);
13380 // Returned in xmm0 and xmm1.
13381 return CallResult.first;
13383 // Returned in bits 0:31 and 32:64 xmm0.
13384 SDValue SinVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
13385 CallResult.first, DAG.getIntPtrConstant(0));
13386 SDValue CosVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
13387 CallResult.first, DAG.getIntPtrConstant(1));
13388 SDVTList Tys = DAG.getVTList(ArgVT, ArgVT);
13389 return DAG.getNode(ISD::MERGE_VALUES, dl, Tys, SinVal, CosVal);
13392 /// LowerOperation - Provide custom lowering hooks for some operations.
13394 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
13395 switch (Op.getOpcode()) {
13396 default: llvm_unreachable("Should not custom lower this!");
13397 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op,DAG);
13398 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, Subtarget, DAG);
13399 case ISD::ATOMIC_CMP_SWAP: return LowerCMP_SWAP(Op, Subtarget, DAG);
13400 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
13401 case ISD::ATOMIC_STORE: return LowerATOMIC_STORE(Op,DAG);
13402 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
13403 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
13404 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
13405 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
13406 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
13407 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op,Subtarget,DAG);
13408 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, Subtarget,DAG);
13409 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
13410 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
13411 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
13412 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
13413 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
13414 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
13415 case ISD::SHL_PARTS:
13416 case ISD::SRA_PARTS:
13417 case ISD::SRL_PARTS: return LowerShiftParts(Op, DAG);
13418 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
13419 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
13420 case ISD::TRUNCATE: return LowerTRUNCATE(Op, DAG);
13421 case ISD::ZERO_EXTEND: return LowerZERO_EXTEND(Op, Subtarget, DAG);
13422 case ISD::SIGN_EXTEND: return LowerSIGN_EXTEND(Op, Subtarget, DAG);
13423 case ISD::ANY_EXTEND: return LowerANY_EXTEND(Op, Subtarget, DAG);
13424 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
13425 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
13426 case ISD::FP_EXTEND: return LowerFP_EXTEND(Op, DAG);
13427 case ISD::FABS: return LowerFABS(Op, DAG);
13428 case ISD::FNEG: return LowerFNEG(Op, DAG);
13429 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
13430 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG);
13431 case ISD::SETCC: return LowerSETCC(Op, DAG);
13432 case ISD::SELECT: return LowerSELECT(Op, DAG);
13433 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
13434 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
13435 case ISD::VASTART: return LowerVASTART(Op, DAG);
13436 case ISD::VAARG: return LowerVAARG(Op, DAG);
13437 case ISD::VACOPY: return LowerVACOPY(Op, Subtarget, DAG);
13438 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
13439 case ISD::INTRINSIC_VOID:
13440 case ISD::INTRINSIC_W_CHAIN: return LowerINTRINSIC_W_CHAIN(Op, Subtarget, DAG);
13441 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
13442 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
13443 case ISD::FRAME_TO_ARGS_OFFSET:
13444 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
13445 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
13446 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
13447 case ISD::EH_SJLJ_SETJMP: return lowerEH_SJLJ_SETJMP(Op, DAG);
13448 case ISD::EH_SJLJ_LONGJMP: return lowerEH_SJLJ_LONGJMP(Op, DAG);
13449 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
13450 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
13451 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
13452 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
13453 case ISD::CTLZ_ZERO_UNDEF: return LowerCTLZ_ZERO_UNDEF(Op, DAG);
13454 case ISD::CTTZ: return LowerCTTZ(Op, DAG);
13455 case ISD::MUL: return LowerMUL(Op, Subtarget, DAG);
13458 case ISD::SHL: return LowerShift(Op, Subtarget, DAG);
13464 case ISD::UMULO: return LowerXALUO(Op, DAG);
13465 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, Subtarget,DAG);
13466 case ISD::BITCAST: return LowerBITCAST(Op, Subtarget, DAG);
13470 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
13471 case ISD::ADD: return LowerADD(Op, DAG);
13472 case ISD::SUB: return LowerSUB(Op, DAG);
13473 case ISD::SDIV: return LowerSDIV(Op, DAG);
13474 case ISD::FSINCOS: return LowerFSINCOS(Op, Subtarget, DAG);
13478 static void ReplaceATOMIC_LOAD(SDNode *Node,
13479 SmallVectorImpl<SDValue> &Results,
13480 SelectionDAG &DAG) {
13482 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
13484 // Convert wide load -> cmpxchg8b/cmpxchg16b
13485 // FIXME: On 32-bit, load -> fild or movq would be more efficient
13486 // (The only way to get a 16-byte load is cmpxchg16b)
13487 // FIXME: 16-byte ATOMIC_CMP_SWAP isn't actually hooked up at the moment.
13488 SDValue Zero = DAG.getConstant(0, VT);
13489 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, dl, VT,
13490 Node->getOperand(0),
13491 Node->getOperand(1), Zero, Zero,
13492 cast<AtomicSDNode>(Node)->getMemOperand(),
13493 cast<AtomicSDNode>(Node)->getOrdering(),
13494 cast<AtomicSDNode>(Node)->getSynchScope());
13495 Results.push_back(Swap.getValue(0));
13496 Results.push_back(Swap.getValue(1));
13500 ReplaceATOMIC_BINARY_64(SDNode *Node, SmallVectorImpl<SDValue>&Results,
13501 SelectionDAG &DAG, unsigned NewOp) {
13503 assert (Node->getValueType(0) == MVT::i64 &&
13504 "Only know how to expand i64 atomics");
13506 SDValue Chain = Node->getOperand(0);
13507 SDValue In1 = Node->getOperand(1);
13508 SDValue In2L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
13509 Node->getOperand(2), DAG.getIntPtrConstant(0));
13510 SDValue In2H = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
13511 Node->getOperand(2), DAG.getIntPtrConstant(1));
13512 SDValue Ops[] = { Chain, In1, In2L, In2H };
13513 SDVTList Tys = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other);
13515 DAG.getMemIntrinsicNode(NewOp, dl, Tys, Ops, array_lengthof(Ops), MVT::i64,
13516 cast<MemSDNode>(Node)->getMemOperand());
13517 SDValue OpsF[] = { Result.getValue(0), Result.getValue(1)};
13518 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2));
13519 Results.push_back(Result.getValue(2));
13522 /// ReplaceNodeResults - Replace a node with an illegal result type
13523 /// with a new node built out of custom code.
13524 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
13525 SmallVectorImpl<SDValue>&Results,
13526 SelectionDAG &DAG) const {
13528 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13529 switch (N->getOpcode()) {
13531 llvm_unreachable("Do not know how to custom type legalize this operation!");
13532 case ISD::SIGN_EXTEND_INREG:
13537 // We don't want to expand or promote these.
13539 case ISD::FP_TO_SINT:
13540 case ISD::FP_TO_UINT: {
13541 bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT;
13543 if (!IsSigned && !isIntegerTypeFTOL(SDValue(N, 0).getValueType()))
13546 std::pair<SDValue,SDValue> Vals =
13547 FP_TO_INTHelper(SDValue(N, 0), DAG, IsSigned, /*IsReplace=*/ true);
13548 SDValue FIST = Vals.first, StackSlot = Vals.second;
13549 if (FIST.getNode() != 0) {
13550 EVT VT = N->getValueType(0);
13551 // Return a load from the stack slot.
13552 if (StackSlot.getNode() != 0)
13553 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot,
13554 MachinePointerInfo(),
13555 false, false, false, 0));
13557 Results.push_back(FIST);
13561 case ISD::UINT_TO_FP: {
13562 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
13563 if (N->getOperand(0).getValueType() != MVT::v2i32 ||
13564 N->getValueType(0) != MVT::v2f32)
13566 SDValue ZExtIn = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v2i64,
13568 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
13570 SDValue VBias = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2f64, Bias, Bias);
13571 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64, ZExtIn,
13572 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, VBias));
13573 Or = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or);
13574 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, Or, VBias);
13575 Results.push_back(DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, Sub));
13578 case ISD::FP_ROUND: {
13579 if (!TLI.isTypeLegal(N->getOperand(0).getValueType()))
13581 SDValue V = DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, N->getOperand(0));
13582 Results.push_back(V);
13585 case ISD::READCYCLECOUNTER: {
13586 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
13587 SDValue TheChain = N->getOperand(0);
13588 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
13589 SDValue eax = DAG.getCopyFromReg(rd, dl, X86::EAX, MVT::i32,
13591 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), dl, X86::EDX, MVT::i32,
13593 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
13594 SDValue Ops[] = { eax, edx };
13595 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Ops,
13596 array_lengthof(Ops)));
13597 Results.push_back(edx.getValue(1));
13600 case ISD::ATOMIC_CMP_SWAP: {
13601 EVT T = N->getValueType(0);
13602 assert((T == MVT::i64 || T == MVT::i128) && "can only expand cmpxchg pair");
13603 bool Regs64bit = T == MVT::i128;
13604 EVT HalfT = Regs64bit ? MVT::i64 : MVT::i32;
13605 SDValue cpInL, cpInH;
13606 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
13607 DAG.getConstant(0, HalfT));
13608 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
13609 DAG.getConstant(1, HalfT));
13610 cpInL = DAG.getCopyToReg(N->getOperand(0), dl,
13611 Regs64bit ? X86::RAX : X86::EAX,
13613 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl,
13614 Regs64bit ? X86::RDX : X86::EDX,
13615 cpInH, cpInL.getValue(1));
13616 SDValue swapInL, swapInH;
13617 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
13618 DAG.getConstant(0, HalfT));
13619 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
13620 DAG.getConstant(1, HalfT));
13621 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl,
13622 Regs64bit ? X86::RBX : X86::EBX,
13623 swapInL, cpInH.getValue(1));
13624 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl,
13625 Regs64bit ? X86::RCX : X86::ECX,
13626 swapInH, swapInL.getValue(1));
13627 SDValue Ops[] = { swapInH.getValue(0),
13629 swapInH.getValue(1) };
13630 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
13631 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand();
13632 unsigned Opcode = Regs64bit ? X86ISD::LCMPXCHG16_DAG :
13633 X86ISD::LCMPXCHG8_DAG;
13634 SDValue Result = DAG.getMemIntrinsicNode(Opcode, dl, Tys,
13635 Ops, array_lengthof(Ops), T, MMO);
13636 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl,
13637 Regs64bit ? X86::RAX : X86::EAX,
13638 HalfT, Result.getValue(1));
13639 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl,
13640 Regs64bit ? X86::RDX : X86::EDX,
13641 HalfT, cpOutL.getValue(2));
13642 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
13643 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, T, OpsF, 2));
13644 Results.push_back(cpOutH.getValue(1));
13647 case ISD::ATOMIC_LOAD_ADD:
13648 case ISD::ATOMIC_LOAD_AND:
13649 case ISD::ATOMIC_LOAD_NAND:
13650 case ISD::ATOMIC_LOAD_OR:
13651 case ISD::ATOMIC_LOAD_SUB:
13652 case ISD::ATOMIC_LOAD_XOR:
13653 case ISD::ATOMIC_LOAD_MAX:
13654 case ISD::ATOMIC_LOAD_MIN:
13655 case ISD::ATOMIC_LOAD_UMAX:
13656 case ISD::ATOMIC_LOAD_UMIN:
13657 case ISD::ATOMIC_SWAP: {
13659 switch (N->getOpcode()) {
13660 default: llvm_unreachable("Unexpected opcode");
13661 case ISD::ATOMIC_LOAD_ADD:
13662 Opc = X86ISD::ATOMADD64_DAG;
13664 case ISD::ATOMIC_LOAD_AND:
13665 Opc = X86ISD::ATOMAND64_DAG;
13667 case ISD::ATOMIC_LOAD_NAND:
13668 Opc = X86ISD::ATOMNAND64_DAG;
13670 case ISD::ATOMIC_LOAD_OR:
13671 Opc = X86ISD::ATOMOR64_DAG;
13673 case ISD::ATOMIC_LOAD_SUB:
13674 Opc = X86ISD::ATOMSUB64_DAG;
13676 case ISD::ATOMIC_LOAD_XOR:
13677 Opc = X86ISD::ATOMXOR64_DAG;
13679 case ISD::ATOMIC_LOAD_MAX:
13680 Opc = X86ISD::ATOMMAX64_DAG;
13682 case ISD::ATOMIC_LOAD_MIN:
13683 Opc = X86ISD::ATOMMIN64_DAG;
13685 case ISD::ATOMIC_LOAD_UMAX:
13686 Opc = X86ISD::ATOMUMAX64_DAG;
13688 case ISD::ATOMIC_LOAD_UMIN:
13689 Opc = X86ISD::ATOMUMIN64_DAG;
13691 case ISD::ATOMIC_SWAP:
13692 Opc = X86ISD::ATOMSWAP64_DAG;
13695 ReplaceATOMIC_BINARY_64(N, Results, DAG, Opc);
13698 case ISD::ATOMIC_LOAD:
13699 ReplaceATOMIC_LOAD(N, Results, DAG);
13703 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
13705 default: return NULL;
13706 case X86ISD::BSF: return "X86ISD::BSF";
13707 case X86ISD::BSR: return "X86ISD::BSR";
13708 case X86ISD::SHLD: return "X86ISD::SHLD";
13709 case X86ISD::SHRD: return "X86ISD::SHRD";
13710 case X86ISD::FAND: return "X86ISD::FAND";
13711 case X86ISD::FANDN: return "X86ISD::FANDN";
13712 case X86ISD::FOR: return "X86ISD::FOR";
13713 case X86ISD::FXOR: return "X86ISD::FXOR";
13714 case X86ISD::FSRL: return "X86ISD::FSRL";
13715 case X86ISD::FILD: return "X86ISD::FILD";
13716 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
13717 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
13718 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
13719 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
13720 case X86ISD::FLD: return "X86ISD::FLD";
13721 case X86ISD::FST: return "X86ISD::FST";
13722 case X86ISD::CALL: return "X86ISD::CALL";
13723 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
13724 case X86ISD::BT: return "X86ISD::BT";
13725 case X86ISD::CMP: return "X86ISD::CMP";
13726 case X86ISD::COMI: return "X86ISD::COMI";
13727 case X86ISD::UCOMI: return "X86ISD::UCOMI";
13728 case X86ISD::CMPM: return "X86ISD::CMPM";
13729 case X86ISD::CMPMU: return "X86ISD::CMPMU";
13730 case X86ISD::SETCC: return "X86ISD::SETCC";
13731 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY";
13732 case X86ISD::FSETCCsd: return "X86ISD::FSETCCsd";
13733 case X86ISD::FSETCCss: return "X86ISD::FSETCCss";
13734 case X86ISD::CMOV: return "X86ISD::CMOV";
13735 case X86ISD::BRCOND: return "X86ISD::BRCOND";
13736 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
13737 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
13738 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
13739 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
13740 case X86ISD::Wrapper: return "X86ISD::Wrapper";
13741 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
13742 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
13743 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
13744 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
13745 case X86ISD::PINSRB: return "X86ISD::PINSRB";
13746 case X86ISD::PINSRW: return "X86ISD::PINSRW";
13747 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
13748 case X86ISD::ANDNP: return "X86ISD::ANDNP";
13749 case X86ISD::PSIGN: return "X86ISD::PSIGN";
13750 case X86ISD::BLENDV: return "X86ISD::BLENDV";
13751 case X86ISD::BLENDI: return "X86ISD::BLENDI";
13752 case X86ISD::SUBUS: return "X86ISD::SUBUS";
13753 case X86ISD::HADD: return "X86ISD::HADD";
13754 case X86ISD::HSUB: return "X86ISD::HSUB";
13755 case X86ISD::FHADD: return "X86ISD::FHADD";
13756 case X86ISD::FHSUB: return "X86ISD::FHSUB";
13757 case X86ISD::UMAX: return "X86ISD::UMAX";
13758 case X86ISD::UMIN: return "X86ISD::UMIN";
13759 case X86ISD::SMAX: return "X86ISD::SMAX";
13760 case X86ISD::SMIN: return "X86ISD::SMIN";
13761 case X86ISD::FMAX: return "X86ISD::FMAX";
13762 case X86ISD::FMIN: return "X86ISD::FMIN";
13763 case X86ISD::FMAXC: return "X86ISD::FMAXC";
13764 case X86ISD::FMINC: return "X86ISD::FMINC";
13765 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
13766 case X86ISD::FRCP: return "X86ISD::FRCP";
13767 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
13768 case X86ISD::TLSBASEADDR: return "X86ISD::TLSBASEADDR";
13769 case X86ISD::TLSCALL: return "X86ISD::TLSCALL";
13770 case X86ISD::EH_SJLJ_SETJMP: return "X86ISD::EH_SJLJ_SETJMP";
13771 case X86ISD::EH_SJLJ_LONGJMP: return "X86ISD::EH_SJLJ_LONGJMP";
13772 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
13773 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
13774 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
13775 case X86ISD::FNSTSW16r: return "X86ISD::FNSTSW16r";
13776 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
13777 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
13778 case X86ISD::ATOMADD64_DAG: return "X86ISD::ATOMADD64_DAG";
13779 case X86ISD::ATOMSUB64_DAG: return "X86ISD::ATOMSUB64_DAG";
13780 case X86ISD::ATOMOR64_DAG: return "X86ISD::ATOMOR64_DAG";
13781 case X86ISD::ATOMXOR64_DAG: return "X86ISD::ATOMXOR64_DAG";
13782 case X86ISD::ATOMAND64_DAG: return "X86ISD::ATOMAND64_DAG";
13783 case X86ISD::ATOMNAND64_DAG: return "X86ISD::ATOMNAND64_DAG";
13784 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
13785 case X86ISD::VSEXT_MOVL: return "X86ISD::VSEXT_MOVL";
13786 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
13787 case X86ISD::VZEXT: return "X86ISD::VZEXT";
13788 case X86ISD::VSEXT: return "X86ISD::VSEXT";
13789 case X86ISD::VTRUNC: return "X86ISD::VTRUNC";
13790 case X86ISD::VTRUNCM: return "X86ISD::VTRUNCM";
13791 case X86ISD::VINSERT: return "X86ISD::VINSERT";
13792 case X86ISD::VFPEXT: return "X86ISD::VFPEXT";
13793 case X86ISD::VFPROUND: return "X86ISD::VFPROUND";
13794 case X86ISD::VSHLDQ: return "X86ISD::VSHLDQ";
13795 case X86ISD::VSRLDQ: return "X86ISD::VSRLDQ";
13796 case X86ISD::VSHL: return "X86ISD::VSHL";
13797 case X86ISD::VSRL: return "X86ISD::VSRL";
13798 case X86ISD::VSRA: return "X86ISD::VSRA";
13799 case X86ISD::VSHLI: return "X86ISD::VSHLI";
13800 case X86ISD::VSRLI: return "X86ISD::VSRLI";
13801 case X86ISD::VSRAI: return "X86ISD::VSRAI";
13802 case X86ISD::CMPP: return "X86ISD::CMPP";
13803 case X86ISD::PCMPEQ: return "X86ISD::PCMPEQ";
13804 case X86ISD::PCMPGT: return "X86ISD::PCMPGT";
13805 case X86ISD::PCMPEQM: return "X86ISD::PCMPEQM";
13806 case X86ISD::PCMPGTM: return "X86ISD::PCMPGTM";
13807 case X86ISD::ADD: return "X86ISD::ADD";
13808 case X86ISD::SUB: return "X86ISD::SUB";
13809 case X86ISD::ADC: return "X86ISD::ADC";
13810 case X86ISD::SBB: return "X86ISD::SBB";
13811 case X86ISD::SMUL: return "X86ISD::SMUL";
13812 case X86ISD::UMUL: return "X86ISD::UMUL";
13813 case X86ISD::INC: return "X86ISD::INC";
13814 case X86ISD::DEC: return "X86ISD::DEC";
13815 case X86ISD::OR: return "X86ISD::OR";
13816 case X86ISD::XOR: return "X86ISD::XOR";
13817 case X86ISD::AND: return "X86ISD::AND";
13818 case X86ISD::BLSI: return "X86ISD::BLSI";
13819 case X86ISD::BLSMSK: return "X86ISD::BLSMSK";
13820 case X86ISD::BLSR: return "X86ISD::BLSR";
13821 case X86ISD::BZHI: return "X86ISD::BZHI";
13822 case X86ISD::BEXTR: return "X86ISD::BEXTR";
13823 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
13824 case X86ISD::PTEST: return "X86ISD::PTEST";
13825 case X86ISD::TESTP: return "X86ISD::TESTP";
13826 case X86ISD::TESTM: return "X86ISD::TESTM";
13827 case X86ISD::KORTEST: return "X86ISD::KORTEST";
13828 case X86ISD::KTEST: return "X86ISD::KTEST";
13829 case X86ISD::PALIGNR: return "X86ISD::PALIGNR";
13830 case X86ISD::PSHUFD: return "X86ISD::PSHUFD";
13831 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW";
13832 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW";
13833 case X86ISD::SHUFP: return "X86ISD::SHUFP";
13834 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS";
13835 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD";
13836 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS";
13837 case X86ISD::MOVLPS: return "X86ISD::MOVLPS";
13838 case X86ISD::MOVLPD: return "X86ISD::MOVLPD";
13839 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP";
13840 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP";
13841 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP";
13842 case X86ISD::MOVSD: return "X86ISD::MOVSD";
13843 case X86ISD::MOVSS: return "X86ISD::MOVSS";
13844 case X86ISD::UNPCKL: return "X86ISD::UNPCKL";
13845 case X86ISD::UNPCKH: return "X86ISD::UNPCKH";
13846 case X86ISD::VBROADCAST: return "X86ISD::VBROADCAST";
13847 case X86ISD::VBROADCASTM: return "X86ISD::VBROADCASTM";
13848 case X86ISD::VPERMILP: return "X86ISD::VPERMILP";
13849 case X86ISD::VPERM2X128: return "X86ISD::VPERM2X128";
13850 case X86ISD::VPERMV: return "X86ISD::VPERMV";
13851 case X86ISD::VPERMV3: return "X86ISD::VPERMV3";
13852 case X86ISD::VPERMI: return "X86ISD::VPERMI";
13853 case X86ISD::PMULUDQ: return "X86ISD::PMULUDQ";
13854 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
13855 case X86ISD::VAARG_64: return "X86ISD::VAARG_64";
13856 case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA";
13857 case X86ISD::MEMBARRIER: return "X86ISD::MEMBARRIER";
13858 case X86ISD::SEG_ALLOCA: return "X86ISD::SEG_ALLOCA";
13859 case X86ISD::WIN_FTOL: return "X86ISD::WIN_FTOL";
13860 case X86ISD::SAHF: return "X86ISD::SAHF";
13861 case X86ISD::RDRAND: return "X86ISD::RDRAND";
13862 case X86ISD::RDSEED: return "X86ISD::RDSEED";
13863 case X86ISD::FMADD: return "X86ISD::FMADD";
13864 case X86ISD::FMSUB: return "X86ISD::FMSUB";
13865 case X86ISD::FNMADD: return "X86ISD::FNMADD";
13866 case X86ISD::FNMSUB: return "X86ISD::FNMSUB";
13867 case X86ISD::FMADDSUB: return "X86ISD::FMADDSUB";
13868 case X86ISD::FMSUBADD: return "X86ISD::FMSUBADD";
13869 case X86ISD::PCMPESTRI: return "X86ISD::PCMPESTRI";
13870 case X86ISD::PCMPISTRI: return "X86ISD::PCMPISTRI";
13871 case X86ISD::XTEST: return "X86ISD::XTEST";
13875 // isLegalAddressingMode - Return true if the addressing mode represented
13876 // by AM is legal for this target, for a load/store of the specified type.
13877 bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
13879 // X86 supports extremely general addressing modes.
13880 CodeModel::Model M = getTargetMachine().getCodeModel();
13881 Reloc::Model R = getTargetMachine().getRelocationModel();
13883 // X86 allows a sign-extended 32-bit immediate field as a displacement.
13884 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != NULL))
13889 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
13891 // If a reference to this global requires an extra load, we can't fold it.
13892 if (isGlobalStubReference(GVFlags))
13895 // If BaseGV requires a register for the PIC base, we cannot also have a
13896 // BaseReg specified.
13897 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
13900 // If lower 4G is not available, then we must use rip-relative addressing.
13901 if ((M != CodeModel::Small || R != Reloc::Static) &&
13902 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
13906 switch (AM.Scale) {
13912 // These scales always work.
13917 // These scales are formed with basereg+scalereg. Only accept if there is
13922 default: // Other stuff never works.
13929 bool X86TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
13930 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
13932 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
13933 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
13934 return NumBits1 > NumBits2;
13937 bool X86TargetLowering::allowTruncateForTailCall(Type *Ty1, Type *Ty2) const {
13938 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
13941 if (!isTypeLegal(EVT::getEVT(Ty1)))
13944 assert(Ty1->getPrimitiveSizeInBits() <= 64 && "i128 is probably not a noop");
13946 // Assuming the caller doesn't have a zeroext or signext return parameter,
13947 // truncation all the way down to i1 is valid.
13951 bool X86TargetLowering::isLegalICmpImmediate(int64_t Imm) const {
13952 return isInt<32>(Imm);
13955 bool X86TargetLowering::isLegalAddImmediate(int64_t Imm) const {
13956 // Can also use sub to handle negated immediates.
13957 return isInt<32>(Imm);
13960 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
13961 if (!VT1.isInteger() || !VT2.isInteger())
13963 unsigned NumBits1 = VT1.getSizeInBits();
13964 unsigned NumBits2 = VT2.getSizeInBits();
13965 return NumBits1 > NumBits2;
13968 bool X86TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
13969 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
13970 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit();
13973 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
13974 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
13975 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
13978 bool X86TargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
13979 EVT VT1 = Val.getValueType();
13980 if (isZExtFree(VT1, VT2))
13983 if (Val.getOpcode() != ISD::LOAD)
13986 if (!VT1.isSimple() || !VT1.isInteger() ||
13987 !VT2.isSimple() || !VT2.isInteger())
13990 switch (VT1.getSimpleVT().SimpleTy) {
13995 // X86 has 8, 16, and 32-bit zero-extending loads.
14003 X86TargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
14004 if (!(Subtarget->hasFMA() || Subtarget->hasFMA4()))
14007 VT = VT.getScalarType();
14009 if (!VT.isSimple())
14012 switch (VT.getSimpleVT().SimpleTy) {
14023 bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
14024 // i16 instructions are longer (0x66 prefix) and potentially slower.
14025 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
14028 /// isShuffleMaskLegal - Targets can use this to indicate that they only
14029 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
14030 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
14031 /// are assumed to be legal.
14033 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
14035 if (!VT.isSimple())
14038 MVT SVT = VT.getSimpleVT();
14040 // Very little shuffling can be done for 64-bit vectors right now.
14041 if (VT.getSizeInBits() == 64)
14044 // FIXME: pshufb, blends, shifts.
14045 return (SVT.getVectorNumElements() == 2 ||
14046 ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
14047 isMOVLMask(M, SVT) ||
14048 isSHUFPMask(M, SVT) ||
14049 isPSHUFDMask(M, SVT) ||
14050 isPSHUFHWMask(M, SVT, Subtarget->hasInt256()) ||
14051 isPSHUFLWMask(M, SVT, Subtarget->hasInt256()) ||
14052 isPALIGNRMask(M, SVT, Subtarget) ||
14053 isUNPCKLMask(M, SVT, Subtarget->hasInt256()) ||
14054 isUNPCKHMask(M, SVT, Subtarget->hasInt256()) ||
14055 isUNPCKL_v_undef_Mask(M, SVT, Subtarget->hasInt256()) ||
14056 isUNPCKH_v_undef_Mask(M, SVT, Subtarget->hasInt256()));
14060 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
14062 if (!VT.isSimple())
14065 MVT SVT = VT.getSimpleVT();
14066 unsigned NumElts = SVT.getVectorNumElements();
14067 // FIXME: This collection of masks seems suspect.
14070 if (NumElts == 4 && SVT.is128BitVector()) {
14071 return (isMOVLMask(Mask, SVT) ||
14072 isCommutedMOVLMask(Mask, SVT, true) ||
14073 isSHUFPMask(Mask, SVT) ||
14074 isSHUFPMask(Mask, SVT, /* Commuted */ true));
14079 //===----------------------------------------------------------------------===//
14080 // X86 Scheduler Hooks
14081 //===----------------------------------------------------------------------===//
14083 /// Utility function to emit xbegin specifying the start of an RTM region.
14084 static MachineBasicBlock *EmitXBegin(MachineInstr *MI, MachineBasicBlock *MBB,
14085 const TargetInstrInfo *TII) {
14086 DebugLoc DL = MI->getDebugLoc();
14088 const BasicBlock *BB = MBB->getBasicBlock();
14089 MachineFunction::iterator I = MBB;
14092 // For the v = xbegin(), we generate
14103 MachineBasicBlock *thisMBB = MBB;
14104 MachineFunction *MF = MBB->getParent();
14105 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
14106 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
14107 MF->insert(I, mainMBB);
14108 MF->insert(I, sinkMBB);
14110 // Transfer the remainder of BB and its successor edges to sinkMBB.
14111 sinkMBB->splice(sinkMBB->begin(), MBB,
14112 llvm::next(MachineBasicBlock::iterator(MI)), MBB->end());
14113 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
14117 // # fallthrough to mainMBB
14118 // # abortion to sinkMBB
14119 BuildMI(thisMBB, DL, TII->get(X86::XBEGIN_4)).addMBB(sinkMBB);
14120 thisMBB->addSuccessor(mainMBB);
14121 thisMBB->addSuccessor(sinkMBB);
14125 BuildMI(mainMBB, DL, TII->get(X86::MOV32ri), X86::EAX).addImm(-1);
14126 mainMBB->addSuccessor(sinkMBB);
14129 // EAX is live into the sinkMBB
14130 sinkMBB->addLiveIn(X86::EAX);
14131 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
14132 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
14135 MI->eraseFromParent();
14139 // Get CMPXCHG opcode for the specified data type.
14140 static unsigned getCmpXChgOpcode(EVT VT) {
14141 switch (VT.getSimpleVT().SimpleTy) {
14142 case MVT::i8: return X86::LCMPXCHG8;
14143 case MVT::i16: return X86::LCMPXCHG16;
14144 case MVT::i32: return X86::LCMPXCHG32;
14145 case MVT::i64: return X86::LCMPXCHG64;
14149 llvm_unreachable("Invalid operand size!");
14152 // Get LOAD opcode for the specified data type.
14153 static unsigned getLoadOpcode(EVT VT) {
14154 switch (VT.getSimpleVT().SimpleTy) {
14155 case MVT::i8: return X86::MOV8rm;
14156 case MVT::i16: return X86::MOV16rm;
14157 case MVT::i32: return X86::MOV32rm;
14158 case MVT::i64: return X86::MOV64rm;
14162 llvm_unreachable("Invalid operand size!");
14165 // Get opcode of the non-atomic one from the specified atomic instruction.
14166 static unsigned getNonAtomicOpcode(unsigned Opc) {
14168 case X86::ATOMAND8: return X86::AND8rr;
14169 case X86::ATOMAND16: return X86::AND16rr;
14170 case X86::ATOMAND32: return X86::AND32rr;
14171 case X86::ATOMAND64: return X86::AND64rr;
14172 case X86::ATOMOR8: return X86::OR8rr;
14173 case X86::ATOMOR16: return X86::OR16rr;
14174 case X86::ATOMOR32: return X86::OR32rr;
14175 case X86::ATOMOR64: return X86::OR64rr;
14176 case X86::ATOMXOR8: return X86::XOR8rr;
14177 case X86::ATOMXOR16: return X86::XOR16rr;
14178 case X86::ATOMXOR32: return X86::XOR32rr;
14179 case X86::ATOMXOR64: return X86::XOR64rr;
14181 llvm_unreachable("Unhandled atomic-load-op opcode!");
14184 // Get opcode of the non-atomic one from the specified atomic instruction with
14186 static unsigned getNonAtomicOpcodeWithExtraOpc(unsigned Opc,
14187 unsigned &ExtraOpc) {
14189 case X86::ATOMNAND8: ExtraOpc = X86::NOT8r; return X86::AND8rr;
14190 case X86::ATOMNAND16: ExtraOpc = X86::NOT16r; return X86::AND16rr;
14191 case X86::ATOMNAND32: ExtraOpc = X86::NOT32r; return X86::AND32rr;
14192 case X86::ATOMNAND64: ExtraOpc = X86::NOT64r; return X86::AND64rr;
14193 case X86::ATOMMAX8: ExtraOpc = X86::CMP8rr; return X86::CMOVL32rr;
14194 case X86::ATOMMAX16: ExtraOpc = X86::CMP16rr; return X86::CMOVL16rr;
14195 case X86::ATOMMAX32: ExtraOpc = X86::CMP32rr; return X86::CMOVL32rr;
14196 case X86::ATOMMAX64: ExtraOpc = X86::CMP64rr; return X86::CMOVL64rr;
14197 case X86::ATOMMIN8: ExtraOpc = X86::CMP8rr; return X86::CMOVG32rr;
14198 case X86::ATOMMIN16: ExtraOpc = X86::CMP16rr; return X86::CMOVG16rr;
14199 case X86::ATOMMIN32: ExtraOpc = X86::CMP32rr; return X86::CMOVG32rr;
14200 case X86::ATOMMIN64: ExtraOpc = X86::CMP64rr; return X86::CMOVG64rr;
14201 case X86::ATOMUMAX8: ExtraOpc = X86::CMP8rr; return X86::CMOVB32rr;
14202 case X86::ATOMUMAX16: ExtraOpc = X86::CMP16rr; return X86::CMOVB16rr;
14203 case X86::ATOMUMAX32: ExtraOpc = X86::CMP32rr; return X86::CMOVB32rr;
14204 case X86::ATOMUMAX64: ExtraOpc = X86::CMP64rr; return X86::CMOVB64rr;
14205 case X86::ATOMUMIN8: ExtraOpc = X86::CMP8rr; return X86::CMOVA32rr;
14206 case X86::ATOMUMIN16: ExtraOpc = X86::CMP16rr; return X86::CMOVA16rr;
14207 case X86::ATOMUMIN32: ExtraOpc = X86::CMP32rr; return X86::CMOVA32rr;
14208 case X86::ATOMUMIN64: ExtraOpc = X86::CMP64rr; return X86::CMOVA64rr;
14210 llvm_unreachable("Unhandled atomic-load-op opcode!");
14213 // Get opcode of the non-atomic one from the specified atomic instruction for
14214 // 64-bit data type on 32-bit target.
14215 static unsigned getNonAtomic6432Opcode(unsigned Opc, unsigned &HiOpc) {
14217 case X86::ATOMAND6432: HiOpc = X86::AND32rr; return X86::AND32rr;
14218 case X86::ATOMOR6432: HiOpc = X86::OR32rr; return X86::OR32rr;
14219 case X86::ATOMXOR6432: HiOpc = X86::XOR32rr; return X86::XOR32rr;
14220 case X86::ATOMADD6432: HiOpc = X86::ADC32rr; return X86::ADD32rr;
14221 case X86::ATOMSUB6432: HiOpc = X86::SBB32rr; return X86::SUB32rr;
14222 case X86::ATOMSWAP6432: HiOpc = X86::MOV32rr; return X86::MOV32rr;
14223 case X86::ATOMMAX6432: HiOpc = X86::SETLr; return X86::SETLr;
14224 case X86::ATOMMIN6432: HiOpc = X86::SETGr; return X86::SETGr;
14225 case X86::ATOMUMAX6432: HiOpc = X86::SETBr; return X86::SETBr;
14226 case X86::ATOMUMIN6432: HiOpc = X86::SETAr; return X86::SETAr;
14228 llvm_unreachable("Unhandled atomic-load-op opcode!");
14231 // Get opcode of the non-atomic one from the specified atomic instruction for
14232 // 64-bit data type on 32-bit target with extra opcode.
14233 static unsigned getNonAtomic6432OpcodeWithExtraOpc(unsigned Opc,
14235 unsigned &ExtraOpc) {
14237 case X86::ATOMNAND6432:
14238 ExtraOpc = X86::NOT32r;
14239 HiOpc = X86::AND32rr;
14240 return X86::AND32rr;
14242 llvm_unreachable("Unhandled atomic-load-op opcode!");
14245 // Get pseudo CMOV opcode from the specified data type.
14246 static unsigned getPseudoCMOVOpc(EVT VT) {
14247 switch (VT.getSimpleVT().SimpleTy) {
14248 case MVT::i8: return X86::CMOV_GR8;
14249 case MVT::i16: return X86::CMOV_GR16;
14250 case MVT::i32: return X86::CMOV_GR32;
14254 llvm_unreachable("Unknown CMOV opcode!");
14257 // EmitAtomicLoadArith - emit the code sequence for pseudo atomic instructions.
14258 // They will be translated into a spin-loop or compare-exchange loop from
14261 // dst = atomic-fetch-op MI.addr, MI.val
14267 // t1 = LOAD MI.addr
14269 // t4 = phi(t1, t3 / loop)
14270 // t2 = OP MI.val, t4
14272 // LCMPXCHG [MI.addr], t2, [EAX is implicitly used & defined]
14278 MachineBasicBlock *
14279 X86TargetLowering::EmitAtomicLoadArith(MachineInstr *MI,
14280 MachineBasicBlock *MBB) const {
14281 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
14282 DebugLoc DL = MI->getDebugLoc();
14284 MachineFunction *MF = MBB->getParent();
14285 MachineRegisterInfo &MRI = MF->getRegInfo();
14287 const BasicBlock *BB = MBB->getBasicBlock();
14288 MachineFunction::iterator I = MBB;
14291 assert(MI->getNumOperands() <= X86::AddrNumOperands + 4 &&
14292 "Unexpected number of operands");
14294 assert(MI->hasOneMemOperand() &&
14295 "Expected atomic-load-op to have one memoperand");
14297 // Memory Reference
14298 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
14299 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
14301 unsigned DstReg, SrcReg;
14302 unsigned MemOpndSlot;
14304 unsigned CurOp = 0;
14306 DstReg = MI->getOperand(CurOp++).getReg();
14307 MemOpndSlot = CurOp;
14308 CurOp += X86::AddrNumOperands;
14309 SrcReg = MI->getOperand(CurOp++).getReg();
14311 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
14312 MVT::SimpleValueType VT = *RC->vt_begin();
14313 unsigned t1 = MRI.createVirtualRegister(RC);
14314 unsigned t2 = MRI.createVirtualRegister(RC);
14315 unsigned t3 = MRI.createVirtualRegister(RC);
14316 unsigned t4 = MRI.createVirtualRegister(RC);
14317 unsigned PhyReg = getX86SubSuperRegister(X86::EAX, VT);
14319 unsigned LCMPXCHGOpc = getCmpXChgOpcode(VT);
14320 unsigned LOADOpc = getLoadOpcode(VT);
14322 // For the atomic load-arith operator, we generate
14325 // t1 = LOAD [MI.addr]
14327 // t4 = phi(t1 / thisMBB, t3 / mainMBB)
14328 // t1 = OP MI.val, EAX
14330 // LCMPXCHG [MI.addr], t1, [EAX is implicitly used & defined]
14336 MachineBasicBlock *thisMBB = MBB;
14337 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
14338 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
14339 MF->insert(I, mainMBB);
14340 MF->insert(I, sinkMBB);
14342 MachineInstrBuilder MIB;
14344 // Transfer the remainder of BB and its successor edges to sinkMBB.
14345 sinkMBB->splice(sinkMBB->begin(), MBB,
14346 llvm::next(MachineBasicBlock::iterator(MI)), MBB->end());
14347 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
14350 MIB = BuildMI(thisMBB, DL, TII->get(LOADOpc), t1);
14351 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
14352 MachineOperand NewMO = MI->getOperand(MemOpndSlot + i);
14354 NewMO.setIsKill(false);
14355 MIB.addOperand(NewMO);
14357 for (MachineInstr::mmo_iterator MMOI = MMOBegin; MMOI != MMOEnd; ++MMOI) {
14358 unsigned flags = (*MMOI)->getFlags();
14359 flags = (flags & ~MachineMemOperand::MOStore) | MachineMemOperand::MOLoad;
14360 MachineMemOperand *MMO =
14361 MF->getMachineMemOperand((*MMOI)->getPointerInfo(), flags,
14362 (*MMOI)->getSize(),
14363 (*MMOI)->getBaseAlignment(),
14364 (*MMOI)->getTBAAInfo(),
14365 (*MMOI)->getRanges());
14366 MIB.addMemOperand(MMO);
14369 thisMBB->addSuccessor(mainMBB);
14372 MachineBasicBlock *origMainMBB = mainMBB;
14375 MachineInstr *Phi = BuildMI(mainMBB, DL, TII->get(X86::PHI), t4)
14376 .addReg(t1).addMBB(thisMBB).addReg(t3).addMBB(mainMBB);
14378 unsigned Opc = MI->getOpcode();
14381 llvm_unreachable("Unhandled atomic-load-op opcode!");
14382 case X86::ATOMAND8:
14383 case X86::ATOMAND16:
14384 case X86::ATOMAND32:
14385 case X86::ATOMAND64:
14387 case X86::ATOMOR16:
14388 case X86::ATOMOR32:
14389 case X86::ATOMOR64:
14390 case X86::ATOMXOR8:
14391 case X86::ATOMXOR16:
14392 case X86::ATOMXOR32:
14393 case X86::ATOMXOR64: {
14394 unsigned ARITHOpc = getNonAtomicOpcode(Opc);
14395 BuildMI(mainMBB, DL, TII->get(ARITHOpc), t2).addReg(SrcReg)
14399 case X86::ATOMNAND8:
14400 case X86::ATOMNAND16:
14401 case X86::ATOMNAND32:
14402 case X86::ATOMNAND64: {
14403 unsigned Tmp = MRI.createVirtualRegister(RC);
14405 unsigned ANDOpc = getNonAtomicOpcodeWithExtraOpc(Opc, NOTOpc);
14406 BuildMI(mainMBB, DL, TII->get(ANDOpc), Tmp).addReg(SrcReg)
14408 BuildMI(mainMBB, DL, TII->get(NOTOpc), t2).addReg(Tmp);
14411 case X86::ATOMMAX8:
14412 case X86::ATOMMAX16:
14413 case X86::ATOMMAX32:
14414 case X86::ATOMMAX64:
14415 case X86::ATOMMIN8:
14416 case X86::ATOMMIN16:
14417 case X86::ATOMMIN32:
14418 case X86::ATOMMIN64:
14419 case X86::ATOMUMAX8:
14420 case X86::ATOMUMAX16:
14421 case X86::ATOMUMAX32:
14422 case X86::ATOMUMAX64:
14423 case X86::ATOMUMIN8:
14424 case X86::ATOMUMIN16:
14425 case X86::ATOMUMIN32:
14426 case X86::ATOMUMIN64: {
14428 unsigned CMOVOpc = getNonAtomicOpcodeWithExtraOpc(Opc, CMPOpc);
14430 BuildMI(mainMBB, DL, TII->get(CMPOpc))
14434 if (Subtarget->hasCMov()) {
14435 if (VT != MVT::i8) {
14437 BuildMI(mainMBB, DL, TII->get(CMOVOpc), t2)
14441 // Promote i8 to i32 to use CMOV32
14442 const TargetRegisterInfo* TRI = getTargetMachine().getRegisterInfo();
14443 const TargetRegisterClass *RC32 =
14444 TRI->getSubClassWithSubReg(getRegClassFor(MVT::i32), X86::sub_8bit);
14445 unsigned SrcReg32 = MRI.createVirtualRegister(RC32);
14446 unsigned AccReg32 = MRI.createVirtualRegister(RC32);
14447 unsigned Tmp = MRI.createVirtualRegister(RC32);
14449 unsigned Undef = MRI.createVirtualRegister(RC32);
14450 BuildMI(mainMBB, DL, TII->get(TargetOpcode::IMPLICIT_DEF), Undef);
14452 BuildMI(mainMBB, DL, TII->get(TargetOpcode::INSERT_SUBREG), SrcReg32)
14455 .addImm(X86::sub_8bit);
14456 BuildMI(mainMBB, DL, TII->get(TargetOpcode::INSERT_SUBREG), AccReg32)
14459 .addImm(X86::sub_8bit);
14461 BuildMI(mainMBB, DL, TII->get(CMOVOpc), Tmp)
14465 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), t2)
14466 .addReg(Tmp, 0, X86::sub_8bit);
14469 // Use pseudo select and lower them.
14470 assert((VT == MVT::i8 || VT == MVT::i16 || VT == MVT::i32) &&
14471 "Invalid atomic-load-op transformation!");
14472 unsigned SelOpc = getPseudoCMOVOpc(VT);
14473 X86::CondCode CC = X86::getCondFromCMovOpc(CMOVOpc);
14474 assert(CC != X86::COND_INVALID && "Invalid atomic-load-op transformation!");
14475 MIB = BuildMI(mainMBB, DL, TII->get(SelOpc), t2)
14476 .addReg(SrcReg).addReg(t4)
14478 mainMBB = EmitLoweredSelect(MIB, mainMBB);
14479 // Replace the original PHI node as mainMBB is changed after CMOV
14481 BuildMI(*origMainMBB, Phi, DL, TII->get(X86::PHI), t4)
14482 .addReg(t1).addMBB(thisMBB).addReg(t3).addMBB(mainMBB);
14483 Phi->eraseFromParent();
14489 // Copy PhyReg back from virtual register.
14490 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), PhyReg)
14493 MIB = BuildMI(mainMBB, DL, TII->get(LCMPXCHGOpc));
14494 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
14495 MachineOperand NewMO = MI->getOperand(MemOpndSlot + i);
14497 NewMO.setIsKill(false);
14498 MIB.addOperand(NewMO);
14501 MIB.setMemRefs(MMOBegin, MMOEnd);
14503 // Copy PhyReg back to virtual register.
14504 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), t3)
14507 BuildMI(mainMBB, DL, TII->get(X86::JNE_4)).addMBB(origMainMBB);
14509 mainMBB->addSuccessor(origMainMBB);
14510 mainMBB->addSuccessor(sinkMBB);
14513 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
14514 TII->get(TargetOpcode::COPY), DstReg)
14517 MI->eraseFromParent();
14521 // EmitAtomicLoadArith6432 - emit the code sequence for pseudo atomic
14522 // instructions. They will be translated into a spin-loop or compare-exchange
14526 // dst = atomic-fetch-op MI.addr, MI.val
14532 // t1L = LOAD [MI.addr + 0]
14533 // t1H = LOAD [MI.addr + 4]
14535 // t4L = phi(t1L, t3L / loop)
14536 // t4H = phi(t1H, t3H / loop)
14537 // t2L = OP MI.val.lo, t4L
14538 // t2H = OP MI.val.hi, t4H
14543 // LCMPXCHG8B [MI.addr], [ECX:EBX & EDX:EAX are implicitly used and EDX:EAX is implicitly defined]
14551 MachineBasicBlock *
14552 X86TargetLowering::EmitAtomicLoadArith6432(MachineInstr *MI,
14553 MachineBasicBlock *MBB) const {
14554 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
14555 DebugLoc DL = MI->getDebugLoc();
14557 MachineFunction *MF = MBB->getParent();
14558 MachineRegisterInfo &MRI = MF->getRegInfo();
14560 const BasicBlock *BB = MBB->getBasicBlock();
14561 MachineFunction::iterator I = MBB;
14564 assert(MI->getNumOperands() <= X86::AddrNumOperands + 7 &&
14565 "Unexpected number of operands");
14567 assert(MI->hasOneMemOperand() &&
14568 "Expected atomic-load-op32 to have one memoperand");
14570 // Memory Reference
14571 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
14572 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
14574 unsigned DstLoReg, DstHiReg;
14575 unsigned SrcLoReg, SrcHiReg;
14576 unsigned MemOpndSlot;
14578 unsigned CurOp = 0;
14580 DstLoReg = MI->getOperand(CurOp++).getReg();
14581 DstHiReg = MI->getOperand(CurOp++).getReg();
14582 MemOpndSlot = CurOp;
14583 CurOp += X86::AddrNumOperands;
14584 SrcLoReg = MI->getOperand(CurOp++).getReg();
14585 SrcHiReg = MI->getOperand(CurOp++).getReg();
14587 const TargetRegisterClass *RC = &X86::GR32RegClass;
14588 const TargetRegisterClass *RC8 = &X86::GR8RegClass;
14590 unsigned t1L = MRI.createVirtualRegister(RC);
14591 unsigned t1H = MRI.createVirtualRegister(RC);
14592 unsigned t2L = MRI.createVirtualRegister(RC);
14593 unsigned t2H = MRI.createVirtualRegister(RC);
14594 unsigned t3L = MRI.createVirtualRegister(RC);
14595 unsigned t3H = MRI.createVirtualRegister(RC);
14596 unsigned t4L = MRI.createVirtualRegister(RC);
14597 unsigned t4H = MRI.createVirtualRegister(RC);
14599 unsigned LCMPXCHGOpc = X86::LCMPXCHG8B;
14600 unsigned LOADOpc = X86::MOV32rm;
14602 // For the atomic load-arith operator, we generate
14605 // t1L = LOAD [MI.addr + 0]
14606 // t1H = LOAD [MI.addr + 4]
14608 // t4L = phi(t1L / thisMBB, t3L / mainMBB)
14609 // t4H = phi(t1H / thisMBB, t3H / mainMBB)
14610 // t2L = OP MI.val.lo, t4L
14611 // t2H = OP MI.val.hi, t4H
14614 // LCMPXCHG8B [MI.addr], [ECX:EBX & EDX:EAX are implicitly used and EDX:EAX is implicitly defined]
14622 MachineBasicBlock *thisMBB = MBB;
14623 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
14624 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
14625 MF->insert(I, mainMBB);
14626 MF->insert(I, sinkMBB);
14628 MachineInstrBuilder MIB;
14630 // Transfer the remainder of BB and its successor edges to sinkMBB.
14631 sinkMBB->splice(sinkMBB->begin(), MBB,
14632 llvm::next(MachineBasicBlock::iterator(MI)), MBB->end());
14633 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
14637 MIB = BuildMI(thisMBB, DL, TII->get(LOADOpc), t1L);
14638 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
14639 MachineOperand NewMO = MI->getOperand(MemOpndSlot + i);
14641 NewMO.setIsKill(false);
14642 MIB.addOperand(NewMO);
14644 for (MachineInstr::mmo_iterator MMOI = MMOBegin; MMOI != MMOEnd; ++MMOI) {
14645 unsigned flags = (*MMOI)->getFlags();
14646 flags = (flags & ~MachineMemOperand::MOStore) | MachineMemOperand::MOLoad;
14647 MachineMemOperand *MMO =
14648 MF->getMachineMemOperand((*MMOI)->getPointerInfo(), flags,
14649 (*MMOI)->getSize(),
14650 (*MMOI)->getBaseAlignment(),
14651 (*MMOI)->getTBAAInfo(),
14652 (*MMOI)->getRanges());
14653 MIB.addMemOperand(MMO);
14655 MachineInstr *LowMI = MIB;
14658 MIB = BuildMI(thisMBB, DL, TII->get(LOADOpc), t1H);
14659 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
14660 if (i == X86::AddrDisp) {
14661 MIB.addDisp(MI->getOperand(MemOpndSlot + i), 4); // 4 == sizeof(i32)
14663 MachineOperand NewMO = MI->getOperand(MemOpndSlot + i);
14665 NewMO.setIsKill(false);
14666 MIB.addOperand(NewMO);
14669 MIB.setMemRefs(LowMI->memoperands_begin(), LowMI->memoperands_end());
14671 thisMBB->addSuccessor(mainMBB);
14674 MachineBasicBlock *origMainMBB = mainMBB;
14677 MachineInstr *PhiL = BuildMI(mainMBB, DL, TII->get(X86::PHI), t4L)
14678 .addReg(t1L).addMBB(thisMBB).addReg(t3L).addMBB(mainMBB);
14679 MachineInstr *PhiH = BuildMI(mainMBB, DL, TII->get(X86::PHI), t4H)
14680 .addReg(t1H).addMBB(thisMBB).addReg(t3H).addMBB(mainMBB);
14682 unsigned Opc = MI->getOpcode();
14685 llvm_unreachable("Unhandled atomic-load-op6432 opcode!");
14686 case X86::ATOMAND6432:
14687 case X86::ATOMOR6432:
14688 case X86::ATOMXOR6432:
14689 case X86::ATOMADD6432:
14690 case X86::ATOMSUB6432: {
14692 unsigned LoOpc = getNonAtomic6432Opcode(Opc, HiOpc);
14693 BuildMI(mainMBB, DL, TII->get(LoOpc), t2L).addReg(t4L)
14695 BuildMI(mainMBB, DL, TII->get(HiOpc), t2H).addReg(t4H)
14699 case X86::ATOMNAND6432: {
14700 unsigned HiOpc, NOTOpc;
14701 unsigned LoOpc = getNonAtomic6432OpcodeWithExtraOpc(Opc, HiOpc, NOTOpc);
14702 unsigned TmpL = MRI.createVirtualRegister(RC);
14703 unsigned TmpH = MRI.createVirtualRegister(RC);
14704 BuildMI(mainMBB, DL, TII->get(LoOpc), TmpL).addReg(SrcLoReg)
14706 BuildMI(mainMBB, DL, TII->get(HiOpc), TmpH).addReg(SrcHiReg)
14708 BuildMI(mainMBB, DL, TII->get(NOTOpc), t2L).addReg(TmpL);
14709 BuildMI(mainMBB, DL, TII->get(NOTOpc), t2H).addReg(TmpH);
14712 case X86::ATOMMAX6432:
14713 case X86::ATOMMIN6432:
14714 case X86::ATOMUMAX6432:
14715 case X86::ATOMUMIN6432: {
14717 unsigned LoOpc = getNonAtomic6432Opcode(Opc, HiOpc);
14718 unsigned cL = MRI.createVirtualRegister(RC8);
14719 unsigned cH = MRI.createVirtualRegister(RC8);
14720 unsigned cL32 = MRI.createVirtualRegister(RC);
14721 unsigned cH32 = MRI.createVirtualRegister(RC);
14722 unsigned cc = MRI.createVirtualRegister(RC);
14723 // cl := cmp src_lo, lo
14724 BuildMI(mainMBB, DL, TII->get(X86::CMP32rr))
14725 .addReg(SrcLoReg).addReg(t4L);
14726 BuildMI(mainMBB, DL, TII->get(LoOpc), cL);
14727 BuildMI(mainMBB, DL, TII->get(X86::MOVZX32rr8), cL32).addReg(cL);
14728 // ch := cmp src_hi, hi
14729 BuildMI(mainMBB, DL, TII->get(X86::CMP32rr))
14730 .addReg(SrcHiReg).addReg(t4H);
14731 BuildMI(mainMBB, DL, TII->get(HiOpc), cH);
14732 BuildMI(mainMBB, DL, TII->get(X86::MOVZX32rr8), cH32).addReg(cH);
14733 // cc := if (src_hi == hi) ? cl : ch;
14734 if (Subtarget->hasCMov()) {
14735 BuildMI(mainMBB, DL, TII->get(X86::CMOVE32rr), cc)
14736 .addReg(cH32).addReg(cL32);
14738 MIB = BuildMI(mainMBB, DL, TII->get(X86::CMOV_GR32), cc)
14739 .addReg(cH32).addReg(cL32)
14740 .addImm(X86::COND_E);
14741 mainMBB = EmitLoweredSelect(MIB, mainMBB);
14743 BuildMI(mainMBB, DL, TII->get(X86::TEST32rr)).addReg(cc).addReg(cc);
14744 if (Subtarget->hasCMov()) {
14745 BuildMI(mainMBB, DL, TII->get(X86::CMOVNE32rr), t2L)
14746 .addReg(SrcLoReg).addReg(t4L);
14747 BuildMI(mainMBB, DL, TII->get(X86::CMOVNE32rr), t2H)
14748 .addReg(SrcHiReg).addReg(t4H);
14750 MIB = BuildMI(mainMBB, DL, TII->get(X86::CMOV_GR32), t2L)
14751 .addReg(SrcLoReg).addReg(t4L)
14752 .addImm(X86::COND_NE);
14753 mainMBB = EmitLoweredSelect(MIB, mainMBB);
14754 // As the lowered CMOV won't clobber EFLAGS, we could reuse it for the
14755 // 2nd CMOV lowering.
14756 mainMBB->addLiveIn(X86::EFLAGS);
14757 MIB = BuildMI(mainMBB, DL, TII->get(X86::CMOV_GR32), t2H)
14758 .addReg(SrcHiReg).addReg(t4H)
14759 .addImm(X86::COND_NE);
14760 mainMBB = EmitLoweredSelect(MIB, mainMBB);
14761 // Replace the original PHI node as mainMBB is changed after CMOV
14763 BuildMI(*origMainMBB, PhiL, DL, TII->get(X86::PHI), t4L)
14764 .addReg(t1L).addMBB(thisMBB).addReg(t3L).addMBB(mainMBB);
14765 BuildMI(*origMainMBB, PhiH, DL, TII->get(X86::PHI), t4H)
14766 .addReg(t1H).addMBB(thisMBB).addReg(t3H).addMBB(mainMBB);
14767 PhiL->eraseFromParent();
14768 PhiH->eraseFromParent();
14772 case X86::ATOMSWAP6432: {
14774 unsigned LoOpc = getNonAtomic6432Opcode(Opc, HiOpc);
14775 BuildMI(mainMBB, DL, TII->get(LoOpc), t2L).addReg(SrcLoReg);
14776 BuildMI(mainMBB, DL, TII->get(HiOpc), t2H).addReg(SrcHiReg);
14781 // Copy EDX:EAX back from HiReg:LoReg
14782 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), X86::EAX).addReg(t4L);
14783 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), X86::EDX).addReg(t4H);
14784 // Copy ECX:EBX from t1H:t1L
14785 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), X86::EBX).addReg(t2L);
14786 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), X86::ECX).addReg(t2H);
14788 MIB = BuildMI(mainMBB, DL, TII->get(LCMPXCHGOpc));
14789 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
14790 MachineOperand NewMO = MI->getOperand(MemOpndSlot + i);
14792 NewMO.setIsKill(false);
14793 MIB.addOperand(NewMO);
14795 MIB.setMemRefs(MMOBegin, MMOEnd);
14797 // Copy EDX:EAX back to t3H:t3L
14798 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), t3L).addReg(X86::EAX);
14799 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), t3H).addReg(X86::EDX);
14801 BuildMI(mainMBB, DL, TII->get(X86::JNE_4)).addMBB(origMainMBB);
14803 mainMBB->addSuccessor(origMainMBB);
14804 mainMBB->addSuccessor(sinkMBB);
14807 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
14808 TII->get(TargetOpcode::COPY), DstLoReg)
14810 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
14811 TII->get(TargetOpcode::COPY), DstHiReg)
14814 MI->eraseFromParent();
14818 // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
14819 // or XMM0_V32I8 in AVX all of this code can be replaced with that
14820 // in the .td file.
14821 static MachineBasicBlock *EmitPCMPSTRM(MachineInstr *MI, MachineBasicBlock *BB,
14822 const TargetInstrInfo *TII) {
14824 switch (MI->getOpcode()) {
14825 default: llvm_unreachable("illegal opcode!");
14826 case X86::PCMPISTRM128REG: Opc = X86::PCMPISTRM128rr; break;
14827 case X86::VPCMPISTRM128REG: Opc = X86::VPCMPISTRM128rr; break;
14828 case X86::PCMPISTRM128MEM: Opc = X86::PCMPISTRM128rm; break;
14829 case X86::VPCMPISTRM128MEM: Opc = X86::VPCMPISTRM128rm; break;
14830 case X86::PCMPESTRM128REG: Opc = X86::PCMPESTRM128rr; break;
14831 case X86::VPCMPESTRM128REG: Opc = X86::VPCMPESTRM128rr; break;
14832 case X86::PCMPESTRM128MEM: Opc = X86::PCMPESTRM128rm; break;
14833 case X86::VPCMPESTRM128MEM: Opc = X86::VPCMPESTRM128rm; break;
14836 DebugLoc dl = MI->getDebugLoc();
14837 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
14839 unsigned NumArgs = MI->getNumOperands();
14840 for (unsigned i = 1; i < NumArgs; ++i) {
14841 MachineOperand &Op = MI->getOperand(i);
14842 if (!(Op.isReg() && Op.isImplicit()))
14843 MIB.addOperand(Op);
14845 if (MI->hasOneMemOperand())
14846 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
14848 BuildMI(*BB, MI, dl,
14849 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
14850 .addReg(X86::XMM0);
14852 MI->eraseFromParent();
14856 // FIXME: Custom handling because TableGen doesn't support multiple implicit
14857 // defs in an instruction pattern
14858 static MachineBasicBlock *EmitPCMPSTRI(MachineInstr *MI, MachineBasicBlock *BB,
14859 const TargetInstrInfo *TII) {
14861 switch (MI->getOpcode()) {
14862 default: llvm_unreachable("illegal opcode!");
14863 case X86::PCMPISTRIREG: Opc = X86::PCMPISTRIrr; break;
14864 case X86::VPCMPISTRIREG: Opc = X86::VPCMPISTRIrr; break;
14865 case X86::PCMPISTRIMEM: Opc = X86::PCMPISTRIrm; break;
14866 case X86::VPCMPISTRIMEM: Opc = X86::VPCMPISTRIrm; break;
14867 case X86::PCMPESTRIREG: Opc = X86::PCMPESTRIrr; break;
14868 case X86::VPCMPESTRIREG: Opc = X86::VPCMPESTRIrr; break;
14869 case X86::PCMPESTRIMEM: Opc = X86::PCMPESTRIrm; break;
14870 case X86::VPCMPESTRIMEM: Opc = X86::VPCMPESTRIrm; break;
14873 DebugLoc dl = MI->getDebugLoc();
14874 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
14876 unsigned NumArgs = MI->getNumOperands(); // remove the results
14877 for (unsigned i = 1; i < NumArgs; ++i) {
14878 MachineOperand &Op = MI->getOperand(i);
14879 if (!(Op.isReg() && Op.isImplicit()))
14880 MIB.addOperand(Op);
14882 if (MI->hasOneMemOperand())
14883 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
14885 BuildMI(*BB, MI, dl,
14886 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
14889 MI->eraseFromParent();
14893 static MachineBasicBlock * EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB,
14894 const TargetInstrInfo *TII,
14895 const X86Subtarget* Subtarget) {
14896 DebugLoc dl = MI->getDebugLoc();
14898 // Address into RAX/EAX, other two args into ECX, EDX.
14899 unsigned MemOpc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
14900 unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
14901 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg);
14902 for (int i = 0; i < X86::AddrNumOperands; ++i)
14903 MIB.addOperand(MI->getOperand(i));
14905 unsigned ValOps = X86::AddrNumOperands;
14906 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
14907 .addReg(MI->getOperand(ValOps).getReg());
14908 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EDX)
14909 .addReg(MI->getOperand(ValOps+1).getReg());
14911 // The instruction doesn't actually take any operands though.
14912 BuildMI(*BB, MI, dl, TII->get(X86::MONITORrrr));
14914 MI->eraseFromParent(); // The pseudo is gone now.
14918 MachineBasicBlock *
14919 X86TargetLowering::EmitVAARG64WithCustomInserter(
14921 MachineBasicBlock *MBB) const {
14922 // Emit va_arg instruction on X86-64.
14924 // Operands to this pseudo-instruction:
14925 // 0 ) Output : destination address (reg)
14926 // 1-5) Input : va_list address (addr, i64mem)
14927 // 6 ) ArgSize : Size (in bytes) of vararg type
14928 // 7 ) ArgMode : 0=overflow only, 1=use gp_offset, 2=use fp_offset
14929 // 8 ) Align : Alignment of type
14930 // 9 ) EFLAGS (implicit-def)
14932 assert(MI->getNumOperands() == 10 && "VAARG_64 should have 10 operands!");
14933 assert(X86::AddrNumOperands == 5 && "VAARG_64 assumes 5 address operands");
14935 unsigned DestReg = MI->getOperand(0).getReg();
14936 MachineOperand &Base = MI->getOperand(1);
14937 MachineOperand &Scale = MI->getOperand(2);
14938 MachineOperand &Index = MI->getOperand(3);
14939 MachineOperand &Disp = MI->getOperand(4);
14940 MachineOperand &Segment = MI->getOperand(5);
14941 unsigned ArgSize = MI->getOperand(6).getImm();
14942 unsigned ArgMode = MI->getOperand(7).getImm();
14943 unsigned Align = MI->getOperand(8).getImm();
14945 // Memory Reference
14946 assert(MI->hasOneMemOperand() && "Expected VAARG_64 to have one memoperand");
14947 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
14948 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
14950 // Machine Information
14951 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
14952 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
14953 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64);
14954 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32);
14955 DebugLoc DL = MI->getDebugLoc();
14957 // struct va_list {
14960 // i64 overflow_area (address)
14961 // i64 reg_save_area (address)
14963 // sizeof(va_list) = 24
14964 // alignment(va_list) = 8
14966 unsigned TotalNumIntRegs = 6;
14967 unsigned TotalNumXMMRegs = 8;
14968 bool UseGPOffset = (ArgMode == 1);
14969 bool UseFPOffset = (ArgMode == 2);
14970 unsigned MaxOffset = TotalNumIntRegs * 8 +
14971 (UseFPOffset ? TotalNumXMMRegs * 16 : 0);
14973 /* Align ArgSize to a multiple of 8 */
14974 unsigned ArgSizeA8 = (ArgSize + 7) & ~7;
14975 bool NeedsAlign = (Align > 8);
14977 MachineBasicBlock *thisMBB = MBB;
14978 MachineBasicBlock *overflowMBB;
14979 MachineBasicBlock *offsetMBB;
14980 MachineBasicBlock *endMBB;
14982 unsigned OffsetDestReg = 0; // Argument address computed by offsetMBB
14983 unsigned OverflowDestReg = 0; // Argument address computed by overflowMBB
14984 unsigned OffsetReg = 0;
14986 if (!UseGPOffset && !UseFPOffset) {
14987 // If we only pull from the overflow region, we don't create a branch.
14988 // We don't need to alter control flow.
14989 OffsetDestReg = 0; // unused
14990 OverflowDestReg = DestReg;
14993 overflowMBB = thisMBB;
14996 // First emit code to check if gp_offset (or fp_offset) is below the bound.
14997 // If so, pull the argument from reg_save_area. (branch to offsetMBB)
14998 // If not, pull from overflow_area. (branch to overflowMBB)
15003 // offsetMBB overflowMBB
15008 // Registers for the PHI in endMBB
15009 OffsetDestReg = MRI.createVirtualRegister(AddrRegClass);
15010 OverflowDestReg = MRI.createVirtualRegister(AddrRegClass);
15012 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
15013 MachineFunction *MF = MBB->getParent();
15014 overflowMBB = MF->CreateMachineBasicBlock(LLVM_BB);
15015 offsetMBB = MF->CreateMachineBasicBlock(LLVM_BB);
15016 endMBB = MF->CreateMachineBasicBlock(LLVM_BB);
15018 MachineFunction::iterator MBBIter = MBB;
15021 // Insert the new basic blocks
15022 MF->insert(MBBIter, offsetMBB);
15023 MF->insert(MBBIter, overflowMBB);
15024 MF->insert(MBBIter, endMBB);
15026 // Transfer the remainder of MBB and its successor edges to endMBB.
15027 endMBB->splice(endMBB->begin(), thisMBB,
15028 llvm::next(MachineBasicBlock::iterator(MI)),
15030 endMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
15032 // Make offsetMBB and overflowMBB successors of thisMBB
15033 thisMBB->addSuccessor(offsetMBB);
15034 thisMBB->addSuccessor(overflowMBB);
15036 // endMBB is a successor of both offsetMBB and overflowMBB
15037 offsetMBB->addSuccessor(endMBB);
15038 overflowMBB->addSuccessor(endMBB);
15040 // Load the offset value into a register
15041 OffsetReg = MRI.createVirtualRegister(OffsetRegClass);
15042 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg)
15046 .addDisp(Disp, UseFPOffset ? 4 : 0)
15047 .addOperand(Segment)
15048 .setMemRefs(MMOBegin, MMOEnd);
15050 // Check if there is enough room left to pull this argument.
15051 BuildMI(thisMBB, DL, TII->get(X86::CMP32ri))
15053 .addImm(MaxOffset + 8 - ArgSizeA8);
15055 // Branch to "overflowMBB" if offset >= max
15056 // Fall through to "offsetMBB" otherwise
15057 BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE)))
15058 .addMBB(overflowMBB);
15061 // In offsetMBB, emit code to use the reg_save_area.
15063 assert(OffsetReg != 0);
15065 // Read the reg_save_area address.
15066 unsigned RegSaveReg = MRI.createVirtualRegister(AddrRegClass);
15067 BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg)
15072 .addOperand(Segment)
15073 .setMemRefs(MMOBegin, MMOEnd);
15075 // Zero-extend the offset
15076 unsigned OffsetReg64 = MRI.createVirtualRegister(AddrRegClass);
15077 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64)
15080 .addImm(X86::sub_32bit);
15082 // Add the offset to the reg_save_area to get the final address.
15083 BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg)
15084 .addReg(OffsetReg64)
15085 .addReg(RegSaveReg);
15087 // Compute the offset for the next argument
15088 unsigned NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass);
15089 BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg)
15091 .addImm(UseFPOffset ? 16 : 8);
15093 // Store it back into the va_list.
15094 BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr))
15098 .addDisp(Disp, UseFPOffset ? 4 : 0)
15099 .addOperand(Segment)
15100 .addReg(NextOffsetReg)
15101 .setMemRefs(MMOBegin, MMOEnd);
15104 BuildMI(offsetMBB, DL, TII->get(X86::JMP_4))
15109 // Emit code to use overflow area
15112 // Load the overflow_area address into a register.
15113 unsigned OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass);
15114 BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg)
15119 .addOperand(Segment)
15120 .setMemRefs(MMOBegin, MMOEnd);
15122 // If we need to align it, do so. Otherwise, just copy the address
15123 // to OverflowDestReg.
15125 // Align the overflow address
15126 assert((Align & (Align-1)) == 0 && "Alignment must be a power of 2");
15127 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass);
15129 // aligned_addr = (addr + (align-1)) & ~(align-1)
15130 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg)
15131 .addReg(OverflowAddrReg)
15134 BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg)
15136 .addImm(~(uint64_t)(Align-1));
15138 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg)
15139 .addReg(OverflowAddrReg);
15142 // Compute the next overflow address after this argument.
15143 // (the overflow address should be kept 8-byte aligned)
15144 unsigned NextAddrReg = MRI.createVirtualRegister(AddrRegClass);
15145 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg)
15146 .addReg(OverflowDestReg)
15147 .addImm(ArgSizeA8);
15149 // Store the new overflow address.
15150 BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr))
15155 .addOperand(Segment)
15156 .addReg(NextAddrReg)
15157 .setMemRefs(MMOBegin, MMOEnd);
15159 // If we branched, emit the PHI to the front of endMBB.
15161 BuildMI(*endMBB, endMBB->begin(), DL,
15162 TII->get(X86::PHI), DestReg)
15163 .addReg(OffsetDestReg).addMBB(offsetMBB)
15164 .addReg(OverflowDestReg).addMBB(overflowMBB);
15167 // Erase the pseudo instruction
15168 MI->eraseFromParent();
15173 MachineBasicBlock *
15174 X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
15176 MachineBasicBlock *MBB) const {
15177 // Emit code to save XMM registers to the stack. The ABI says that the
15178 // number of registers to save is given in %al, so it's theoretically
15179 // possible to do an indirect jump trick to avoid saving all of them,
15180 // however this code takes a simpler approach and just executes all
15181 // of the stores if %al is non-zero. It's less code, and it's probably
15182 // easier on the hardware branch predictor, and stores aren't all that
15183 // expensive anyway.
15185 // Create the new basic blocks. One block contains all the XMM stores,
15186 // and one block is the final destination regardless of whether any
15187 // stores were performed.
15188 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
15189 MachineFunction *F = MBB->getParent();
15190 MachineFunction::iterator MBBIter = MBB;
15192 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB);
15193 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB);
15194 F->insert(MBBIter, XMMSaveMBB);
15195 F->insert(MBBIter, EndMBB);
15197 // Transfer the remainder of MBB and its successor edges to EndMBB.
15198 EndMBB->splice(EndMBB->begin(), MBB,
15199 llvm::next(MachineBasicBlock::iterator(MI)),
15201 EndMBB->transferSuccessorsAndUpdatePHIs(MBB);
15203 // The original block will now fall through to the XMM save block.
15204 MBB->addSuccessor(XMMSaveMBB);
15205 // The XMMSaveMBB will fall through to the end block.
15206 XMMSaveMBB->addSuccessor(EndMBB);
15208 // Now add the instructions.
15209 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
15210 DebugLoc DL = MI->getDebugLoc();
15212 unsigned CountReg = MI->getOperand(0).getReg();
15213 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm();
15214 int64_t VarArgsFPOffset = MI->getOperand(2).getImm();
15216 if (!Subtarget->isTargetWin64()) {
15217 // If %al is 0, branch around the XMM save block.
15218 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
15219 BuildMI(MBB, DL, TII->get(X86::JE_4)).addMBB(EndMBB);
15220 MBB->addSuccessor(EndMBB);
15223 unsigned MOVOpc = Subtarget->hasFp256() ? X86::VMOVAPSmr : X86::MOVAPSmr;
15224 // In the XMM save block, save all the XMM argument registers.
15225 for (int i = 3, e = MI->getNumOperands(); i != e; ++i) {
15226 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
15227 MachineMemOperand *MMO =
15228 F->getMachineMemOperand(
15229 MachinePointerInfo::getFixedStack(RegSaveFrameIndex, Offset),
15230 MachineMemOperand::MOStore,
15231 /*Size=*/16, /*Align=*/16);
15232 BuildMI(XMMSaveMBB, DL, TII->get(MOVOpc))
15233 .addFrameIndex(RegSaveFrameIndex)
15234 .addImm(/*Scale=*/1)
15235 .addReg(/*IndexReg=*/0)
15236 .addImm(/*Disp=*/Offset)
15237 .addReg(/*Segment=*/0)
15238 .addReg(MI->getOperand(i).getReg())
15239 .addMemOperand(MMO);
15242 MI->eraseFromParent(); // The pseudo instruction is gone now.
15247 // The EFLAGS operand of SelectItr might be missing a kill marker
15248 // because there were multiple uses of EFLAGS, and ISel didn't know
15249 // which to mark. Figure out whether SelectItr should have had a
15250 // kill marker, and set it if it should. Returns the correct kill
15252 static bool checkAndUpdateEFLAGSKill(MachineBasicBlock::iterator SelectItr,
15253 MachineBasicBlock* BB,
15254 const TargetRegisterInfo* TRI) {
15255 // Scan forward through BB for a use/def of EFLAGS.
15256 MachineBasicBlock::iterator miI(llvm::next(SelectItr));
15257 for (MachineBasicBlock::iterator miE = BB->end(); miI != miE; ++miI) {
15258 const MachineInstr& mi = *miI;
15259 if (mi.readsRegister(X86::EFLAGS))
15261 if (mi.definesRegister(X86::EFLAGS))
15262 break; // Should have kill-flag - update below.
15265 // If we hit the end of the block, check whether EFLAGS is live into a
15267 if (miI == BB->end()) {
15268 for (MachineBasicBlock::succ_iterator sItr = BB->succ_begin(),
15269 sEnd = BB->succ_end();
15270 sItr != sEnd; ++sItr) {
15271 MachineBasicBlock* succ = *sItr;
15272 if (succ->isLiveIn(X86::EFLAGS))
15277 // We found a def, or hit the end of the basic block and EFLAGS wasn't live
15278 // out. SelectMI should have a kill flag on EFLAGS.
15279 SelectItr->addRegisterKilled(X86::EFLAGS, TRI);
15283 MachineBasicBlock *
15284 X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
15285 MachineBasicBlock *BB) const {
15286 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
15287 DebugLoc DL = MI->getDebugLoc();
15289 // To "insert" a SELECT_CC instruction, we actually have to insert the
15290 // diamond control-flow pattern. The incoming instruction knows the
15291 // destination vreg to set, the condition code register to branch on, the
15292 // true/false values to select between, and a branch opcode to use.
15293 const BasicBlock *LLVM_BB = BB->getBasicBlock();
15294 MachineFunction::iterator It = BB;
15300 // cmpTY ccX, r1, r2
15302 // fallthrough --> copy0MBB
15303 MachineBasicBlock *thisMBB = BB;
15304 MachineFunction *F = BB->getParent();
15305 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
15306 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
15307 F->insert(It, copy0MBB);
15308 F->insert(It, sinkMBB);
15310 // If the EFLAGS register isn't dead in the terminator, then claim that it's
15311 // live into the sink and copy blocks.
15312 const TargetRegisterInfo* TRI = getTargetMachine().getRegisterInfo();
15313 if (!MI->killsRegister(X86::EFLAGS) &&
15314 !checkAndUpdateEFLAGSKill(MI, BB, TRI)) {
15315 copy0MBB->addLiveIn(X86::EFLAGS);
15316 sinkMBB->addLiveIn(X86::EFLAGS);
15319 // Transfer the remainder of BB and its successor edges to sinkMBB.
15320 sinkMBB->splice(sinkMBB->begin(), BB,
15321 llvm::next(MachineBasicBlock::iterator(MI)),
15323 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
15325 // Add the true and fallthrough blocks as its successors.
15326 BB->addSuccessor(copy0MBB);
15327 BB->addSuccessor(sinkMBB);
15329 // Create the conditional branch instruction.
15331 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
15332 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
15335 // %FalseValue = ...
15336 // # fallthrough to sinkMBB
15337 copy0MBB->addSuccessor(sinkMBB);
15340 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
15342 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
15343 TII->get(X86::PHI), MI->getOperand(0).getReg())
15344 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
15345 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
15347 MI->eraseFromParent(); // The pseudo instruction is gone now.
15351 MachineBasicBlock *
15352 X86TargetLowering::EmitLoweredSegAlloca(MachineInstr *MI, MachineBasicBlock *BB,
15353 bool Is64Bit) const {
15354 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
15355 DebugLoc DL = MI->getDebugLoc();
15356 MachineFunction *MF = BB->getParent();
15357 const BasicBlock *LLVM_BB = BB->getBasicBlock();
15359 assert(getTargetMachine().Options.EnableSegmentedStacks);
15361 unsigned TlsReg = Is64Bit ? X86::FS : X86::GS;
15362 unsigned TlsOffset = Is64Bit ? 0x70 : 0x30;
15365 // ... [Till the alloca]
15366 // If stacklet is not large enough, jump to mallocMBB
15369 // Allocate by subtracting from RSP
15370 // Jump to continueMBB
15373 // Allocate by call to runtime
15377 // [rest of original BB]
15380 MachineBasicBlock *mallocMBB = MF->CreateMachineBasicBlock(LLVM_BB);
15381 MachineBasicBlock *bumpMBB = MF->CreateMachineBasicBlock(LLVM_BB);
15382 MachineBasicBlock *continueMBB = MF->CreateMachineBasicBlock(LLVM_BB);
15384 MachineRegisterInfo &MRI = MF->getRegInfo();
15385 const TargetRegisterClass *AddrRegClass =
15386 getRegClassFor(Is64Bit ? MVT::i64:MVT::i32);
15388 unsigned mallocPtrVReg = MRI.createVirtualRegister(AddrRegClass),
15389 bumpSPPtrVReg = MRI.createVirtualRegister(AddrRegClass),
15390 tmpSPVReg = MRI.createVirtualRegister(AddrRegClass),
15391 SPLimitVReg = MRI.createVirtualRegister(AddrRegClass),
15392 sizeVReg = MI->getOperand(1).getReg(),
15393 physSPReg = Is64Bit ? X86::RSP : X86::ESP;
15395 MachineFunction::iterator MBBIter = BB;
15398 MF->insert(MBBIter, bumpMBB);
15399 MF->insert(MBBIter, mallocMBB);
15400 MF->insert(MBBIter, continueMBB);
15402 continueMBB->splice(continueMBB->begin(), BB, llvm::next
15403 (MachineBasicBlock::iterator(MI)), BB->end());
15404 continueMBB->transferSuccessorsAndUpdatePHIs(BB);
15406 // Add code to the main basic block to check if the stack limit has been hit,
15407 // and if so, jump to mallocMBB otherwise to bumpMBB.
15408 BuildMI(BB, DL, TII->get(TargetOpcode::COPY), tmpSPVReg).addReg(physSPReg);
15409 BuildMI(BB, DL, TII->get(Is64Bit ? X86::SUB64rr:X86::SUB32rr), SPLimitVReg)
15410 .addReg(tmpSPVReg).addReg(sizeVReg);
15411 BuildMI(BB, DL, TII->get(Is64Bit ? X86::CMP64mr:X86::CMP32mr))
15412 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg)
15413 .addReg(SPLimitVReg);
15414 BuildMI(BB, DL, TII->get(X86::JG_4)).addMBB(mallocMBB);
15416 // bumpMBB simply decreases the stack pointer, since we know the current
15417 // stacklet has enough space.
15418 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), physSPReg)
15419 .addReg(SPLimitVReg);
15420 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), bumpSPPtrVReg)
15421 .addReg(SPLimitVReg);
15422 BuildMI(bumpMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
15424 // Calls into a routine in libgcc to allocate more space from the heap.
15425 const uint32_t *RegMask =
15426 getTargetMachine().getRegisterInfo()->getCallPreservedMask(CallingConv::C);
15428 BuildMI(mallocMBB, DL, TII->get(X86::MOV64rr), X86::RDI)
15430 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
15431 .addExternalSymbol("__morestack_allocate_stack_space")
15432 .addRegMask(RegMask)
15433 .addReg(X86::RDI, RegState::Implicit)
15434 .addReg(X86::RAX, RegState::ImplicitDefine);
15436 BuildMI(mallocMBB, DL, TII->get(X86::SUB32ri), physSPReg).addReg(physSPReg)
15438 BuildMI(mallocMBB, DL, TII->get(X86::PUSH32r)).addReg(sizeVReg);
15439 BuildMI(mallocMBB, DL, TII->get(X86::CALLpcrel32))
15440 .addExternalSymbol("__morestack_allocate_stack_space")
15441 .addRegMask(RegMask)
15442 .addReg(X86::EAX, RegState::ImplicitDefine);
15446 BuildMI(mallocMBB, DL, TII->get(X86::ADD32ri), physSPReg).addReg(physSPReg)
15449 BuildMI(mallocMBB, DL, TII->get(TargetOpcode::COPY), mallocPtrVReg)
15450 .addReg(Is64Bit ? X86::RAX : X86::EAX);
15451 BuildMI(mallocMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
15453 // Set up the CFG correctly.
15454 BB->addSuccessor(bumpMBB);
15455 BB->addSuccessor(mallocMBB);
15456 mallocMBB->addSuccessor(continueMBB);
15457 bumpMBB->addSuccessor(continueMBB);
15459 // Take care of the PHI nodes.
15460 BuildMI(*continueMBB, continueMBB->begin(), DL, TII->get(X86::PHI),
15461 MI->getOperand(0).getReg())
15462 .addReg(mallocPtrVReg).addMBB(mallocMBB)
15463 .addReg(bumpSPPtrVReg).addMBB(bumpMBB);
15465 // Delete the original pseudo instruction.
15466 MI->eraseFromParent();
15469 return continueMBB;
15472 MachineBasicBlock *
15473 X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI,
15474 MachineBasicBlock *BB) const {
15475 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
15476 DebugLoc DL = MI->getDebugLoc();
15478 assert(!Subtarget->isTargetEnvMacho());
15480 // The lowering is pretty easy: we're just emitting the call to _alloca. The
15481 // non-trivial part is impdef of ESP.
15483 if (Subtarget->isTargetWin64()) {
15484 if (Subtarget->isTargetCygMing()) {
15485 // ___chkstk(Mingw64):
15486 // Clobbers R10, R11, RAX and EFLAGS.
15488 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
15489 .addExternalSymbol("___chkstk")
15490 .addReg(X86::RAX, RegState::Implicit)
15491 .addReg(X86::RSP, RegState::Implicit)
15492 .addReg(X86::RAX, RegState::Define | RegState::Implicit)
15493 .addReg(X86::RSP, RegState::Define | RegState::Implicit)
15494 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
15496 // __chkstk(MSVCRT): does not update stack pointer.
15497 // Clobbers R10, R11 and EFLAGS.
15498 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
15499 .addExternalSymbol("__chkstk")
15500 .addReg(X86::RAX, RegState::Implicit)
15501 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
15502 // RAX has the offset to be subtracted from RSP.
15503 BuildMI(*BB, MI, DL, TII->get(X86::SUB64rr), X86::RSP)
15508 const char *StackProbeSymbol =
15509 Subtarget->isTargetWindows() ? "_chkstk" : "_alloca";
15511 BuildMI(*BB, MI, DL, TII->get(X86::CALLpcrel32))
15512 .addExternalSymbol(StackProbeSymbol)
15513 .addReg(X86::EAX, RegState::Implicit)
15514 .addReg(X86::ESP, RegState::Implicit)
15515 .addReg(X86::EAX, RegState::Define | RegState::Implicit)
15516 .addReg(X86::ESP, RegState::Define | RegState::Implicit)
15517 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
15520 MI->eraseFromParent(); // The pseudo instruction is gone now.
15524 MachineBasicBlock *
15525 X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI,
15526 MachineBasicBlock *BB) const {
15527 // This is pretty easy. We're taking the value that we received from
15528 // our load from the relocation, sticking it in either RDI (x86-64)
15529 // or EAX and doing an indirect call. The return value will then
15530 // be in the normal return register.
15531 const X86InstrInfo *TII
15532 = static_cast<const X86InstrInfo*>(getTargetMachine().getInstrInfo());
15533 DebugLoc DL = MI->getDebugLoc();
15534 MachineFunction *F = BB->getParent();
15536 assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?");
15537 assert(MI->getOperand(3).isGlobal() && "This should be a global");
15539 // Get a register mask for the lowered call.
15540 // FIXME: The 32-bit calls have non-standard calling conventions. Use a
15541 // proper register mask.
15542 const uint32_t *RegMask =
15543 getTargetMachine().getRegisterInfo()->getCallPreservedMask(CallingConv::C);
15544 if (Subtarget->is64Bit()) {
15545 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
15546 TII->get(X86::MOV64rm), X86::RDI)
15548 .addImm(0).addReg(0)
15549 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
15550 MI->getOperand(3).getTargetFlags())
15552 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m));
15553 addDirectMem(MIB, X86::RDI);
15554 MIB.addReg(X86::RAX, RegState::ImplicitDefine).addRegMask(RegMask);
15555 } else if (getTargetMachine().getRelocationModel() != Reloc::PIC_) {
15556 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
15557 TII->get(X86::MOV32rm), X86::EAX)
15559 .addImm(0).addReg(0)
15560 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
15561 MI->getOperand(3).getTargetFlags())
15563 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
15564 addDirectMem(MIB, X86::EAX);
15565 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
15567 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
15568 TII->get(X86::MOV32rm), X86::EAX)
15569 .addReg(TII->getGlobalBaseReg(F))
15570 .addImm(0).addReg(0)
15571 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
15572 MI->getOperand(3).getTargetFlags())
15574 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
15575 addDirectMem(MIB, X86::EAX);
15576 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
15579 MI->eraseFromParent(); // The pseudo instruction is gone now.
15583 MachineBasicBlock *
15584 X86TargetLowering::emitEHSjLjSetJmp(MachineInstr *MI,
15585 MachineBasicBlock *MBB) const {
15586 DebugLoc DL = MI->getDebugLoc();
15587 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
15589 MachineFunction *MF = MBB->getParent();
15590 MachineRegisterInfo &MRI = MF->getRegInfo();
15592 const BasicBlock *BB = MBB->getBasicBlock();
15593 MachineFunction::iterator I = MBB;
15596 // Memory Reference
15597 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
15598 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
15601 unsigned MemOpndSlot = 0;
15603 unsigned CurOp = 0;
15605 DstReg = MI->getOperand(CurOp++).getReg();
15606 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
15607 assert(RC->hasType(MVT::i32) && "Invalid destination!");
15608 unsigned mainDstReg = MRI.createVirtualRegister(RC);
15609 unsigned restoreDstReg = MRI.createVirtualRegister(RC);
15611 MemOpndSlot = CurOp;
15613 MVT PVT = getPointerTy();
15614 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
15615 "Invalid Pointer Size!");
15617 // For v = setjmp(buf), we generate
15620 // buf[LabelOffset] = restoreMBB
15621 // SjLjSetup restoreMBB
15627 // v = phi(main, restore)
15632 MachineBasicBlock *thisMBB = MBB;
15633 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
15634 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
15635 MachineBasicBlock *restoreMBB = MF->CreateMachineBasicBlock(BB);
15636 MF->insert(I, mainMBB);
15637 MF->insert(I, sinkMBB);
15638 MF->push_back(restoreMBB);
15640 MachineInstrBuilder MIB;
15642 // Transfer the remainder of BB and its successor edges to sinkMBB.
15643 sinkMBB->splice(sinkMBB->begin(), MBB,
15644 llvm::next(MachineBasicBlock::iterator(MI)), MBB->end());
15645 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
15648 unsigned PtrStoreOpc = 0;
15649 unsigned LabelReg = 0;
15650 const int64_t LabelOffset = 1 * PVT.getStoreSize();
15651 Reloc::Model RM = getTargetMachine().getRelocationModel();
15652 bool UseImmLabel = (getTargetMachine().getCodeModel() == CodeModel::Small) &&
15653 (RM == Reloc::Static || RM == Reloc::DynamicNoPIC);
15655 // Prepare IP either in reg or imm.
15656 if (!UseImmLabel) {
15657 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mr : X86::MOV32mr;
15658 const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
15659 LabelReg = MRI.createVirtualRegister(PtrRC);
15660 if (Subtarget->is64Bit()) {
15661 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA64r), LabelReg)
15665 .addMBB(restoreMBB)
15668 const X86InstrInfo *XII = static_cast<const X86InstrInfo*>(TII);
15669 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA32r), LabelReg)
15670 .addReg(XII->getGlobalBaseReg(MF))
15673 .addMBB(restoreMBB, Subtarget->ClassifyBlockAddressReference())
15677 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mi32 : X86::MOV32mi;
15679 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PtrStoreOpc));
15680 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
15681 if (i == X86::AddrDisp)
15682 MIB.addDisp(MI->getOperand(MemOpndSlot + i), LabelOffset);
15684 MIB.addOperand(MI->getOperand(MemOpndSlot + i));
15687 MIB.addReg(LabelReg);
15689 MIB.addMBB(restoreMBB);
15690 MIB.setMemRefs(MMOBegin, MMOEnd);
15692 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::EH_SjLj_Setup))
15693 .addMBB(restoreMBB);
15695 const X86RegisterInfo *RegInfo =
15696 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
15697 MIB.addRegMask(RegInfo->getNoPreservedMask());
15698 thisMBB->addSuccessor(mainMBB);
15699 thisMBB->addSuccessor(restoreMBB);
15703 BuildMI(mainMBB, DL, TII->get(X86::MOV32r0), mainDstReg);
15704 mainMBB->addSuccessor(sinkMBB);
15707 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
15708 TII->get(X86::PHI), DstReg)
15709 .addReg(mainDstReg).addMBB(mainMBB)
15710 .addReg(restoreDstReg).addMBB(restoreMBB);
15713 BuildMI(restoreMBB, DL, TII->get(X86::MOV32ri), restoreDstReg).addImm(1);
15714 BuildMI(restoreMBB, DL, TII->get(X86::JMP_4)).addMBB(sinkMBB);
15715 restoreMBB->addSuccessor(sinkMBB);
15717 MI->eraseFromParent();
15721 MachineBasicBlock *
15722 X86TargetLowering::emitEHSjLjLongJmp(MachineInstr *MI,
15723 MachineBasicBlock *MBB) const {
15724 DebugLoc DL = MI->getDebugLoc();
15725 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
15727 MachineFunction *MF = MBB->getParent();
15728 MachineRegisterInfo &MRI = MF->getRegInfo();
15730 // Memory Reference
15731 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
15732 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
15734 MVT PVT = getPointerTy();
15735 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
15736 "Invalid Pointer Size!");
15738 const TargetRegisterClass *RC =
15739 (PVT == MVT::i64) ? &X86::GR64RegClass : &X86::GR32RegClass;
15740 unsigned Tmp = MRI.createVirtualRegister(RC);
15741 // Since FP is only updated here but NOT referenced, it's treated as GPR.
15742 const X86RegisterInfo *RegInfo =
15743 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
15744 unsigned FP = (PVT == MVT::i64) ? X86::RBP : X86::EBP;
15745 unsigned SP = RegInfo->getStackRegister();
15747 MachineInstrBuilder MIB;
15749 const int64_t LabelOffset = 1 * PVT.getStoreSize();
15750 const int64_t SPOffset = 2 * PVT.getStoreSize();
15752 unsigned PtrLoadOpc = (PVT == MVT::i64) ? X86::MOV64rm : X86::MOV32rm;
15753 unsigned IJmpOpc = (PVT == MVT::i64) ? X86::JMP64r : X86::JMP32r;
15756 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), FP);
15757 for (unsigned i = 0; i < X86::AddrNumOperands; ++i)
15758 MIB.addOperand(MI->getOperand(i));
15759 MIB.setMemRefs(MMOBegin, MMOEnd);
15761 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), Tmp);
15762 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
15763 if (i == X86::AddrDisp)
15764 MIB.addDisp(MI->getOperand(i), LabelOffset);
15766 MIB.addOperand(MI->getOperand(i));
15768 MIB.setMemRefs(MMOBegin, MMOEnd);
15770 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), SP);
15771 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
15772 if (i == X86::AddrDisp)
15773 MIB.addDisp(MI->getOperand(i), SPOffset);
15775 MIB.addOperand(MI->getOperand(i));
15777 MIB.setMemRefs(MMOBegin, MMOEnd);
15779 BuildMI(*MBB, MI, DL, TII->get(IJmpOpc)).addReg(Tmp);
15781 MI->eraseFromParent();
15785 MachineBasicBlock *
15786 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
15787 MachineBasicBlock *BB) const {
15788 switch (MI->getOpcode()) {
15789 default: llvm_unreachable("Unexpected instr type to insert");
15790 case X86::TAILJMPd64:
15791 case X86::TAILJMPr64:
15792 case X86::TAILJMPm64:
15793 llvm_unreachable("TAILJMP64 would not be touched here.");
15794 case X86::TCRETURNdi64:
15795 case X86::TCRETURNri64:
15796 case X86::TCRETURNmi64:
15798 case X86::WIN_ALLOCA:
15799 return EmitLoweredWinAlloca(MI, BB);
15800 case X86::SEG_ALLOCA_32:
15801 return EmitLoweredSegAlloca(MI, BB, false);
15802 case X86::SEG_ALLOCA_64:
15803 return EmitLoweredSegAlloca(MI, BB, true);
15804 case X86::TLSCall_32:
15805 case X86::TLSCall_64:
15806 return EmitLoweredTLSCall(MI, BB);
15807 case X86::CMOV_GR8:
15808 case X86::CMOV_FR32:
15809 case X86::CMOV_FR64:
15810 case X86::CMOV_V4F32:
15811 case X86::CMOV_V2F64:
15812 case X86::CMOV_V2I64:
15813 case X86::CMOV_V8F32:
15814 case X86::CMOV_V4F64:
15815 case X86::CMOV_V4I64:
15816 case X86::CMOV_V16F32:
15817 case X86::CMOV_V8F64:
15818 case X86::CMOV_V8I64:
15819 case X86::CMOV_GR16:
15820 case X86::CMOV_GR32:
15821 case X86::CMOV_RFP32:
15822 case X86::CMOV_RFP64:
15823 case X86::CMOV_RFP80:
15824 return EmitLoweredSelect(MI, BB);
15826 case X86::FP32_TO_INT16_IN_MEM:
15827 case X86::FP32_TO_INT32_IN_MEM:
15828 case X86::FP32_TO_INT64_IN_MEM:
15829 case X86::FP64_TO_INT16_IN_MEM:
15830 case X86::FP64_TO_INT32_IN_MEM:
15831 case X86::FP64_TO_INT64_IN_MEM:
15832 case X86::FP80_TO_INT16_IN_MEM:
15833 case X86::FP80_TO_INT32_IN_MEM:
15834 case X86::FP80_TO_INT64_IN_MEM: {
15835 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
15836 DebugLoc DL = MI->getDebugLoc();
15838 // Change the floating point control register to use "round towards zero"
15839 // mode when truncating to an integer value.
15840 MachineFunction *F = BB->getParent();
15841 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false);
15842 addFrameReference(BuildMI(*BB, MI, DL,
15843 TII->get(X86::FNSTCW16m)), CWFrameIdx);
15845 // Load the old value of the high byte of the control word...
15847 F->getRegInfo().createVirtualRegister(&X86::GR16RegClass);
15848 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW),
15851 // Set the high part to be round to zero...
15852 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
15855 // Reload the modified control word now...
15856 addFrameReference(BuildMI(*BB, MI, DL,
15857 TII->get(X86::FLDCW16m)), CWFrameIdx);
15859 // Restore the memory image of control word to original value
15860 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
15863 // Get the X86 opcode to use.
15865 switch (MI->getOpcode()) {
15866 default: llvm_unreachable("illegal opcode!");
15867 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
15868 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
15869 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
15870 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
15871 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
15872 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
15873 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
15874 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
15875 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
15879 MachineOperand &Op = MI->getOperand(0);
15881 AM.BaseType = X86AddressMode::RegBase;
15882 AM.Base.Reg = Op.getReg();
15884 AM.BaseType = X86AddressMode::FrameIndexBase;
15885 AM.Base.FrameIndex = Op.getIndex();
15887 Op = MI->getOperand(1);
15889 AM.Scale = Op.getImm();
15890 Op = MI->getOperand(2);
15892 AM.IndexReg = Op.getImm();
15893 Op = MI->getOperand(3);
15894 if (Op.isGlobal()) {
15895 AM.GV = Op.getGlobal();
15897 AM.Disp = Op.getImm();
15899 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM)
15900 .addReg(MI->getOperand(X86::AddrNumOperands).getReg());
15902 // Reload the original control word now.
15903 addFrameReference(BuildMI(*BB, MI, DL,
15904 TII->get(X86::FLDCW16m)), CWFrameIdx);
15906 MI->eraseFromParent(); // The pseudo instruction is gone now.
15909 // String/text processing lowering.
15910 case X86::PCMPISTRM128REG:
15911 case X86::VPCMPISTRM128REG:
15912 case X86::PCMPISTRM128MEM:
15913 case X86::VPCMPISTRM128MEM:
15914 case X86::PCMPESTRM128REG:
15915 case X86::VPCMPESTRM128REG:
15916 case X86::PCMPESTRM128MEM:
15917 case X86::VPCMPESTRM128MEM:
15918 assert(Subtarget->hasSSE42() &&
15919 "Target must have SSE4.2 or AVX features enabled");
15920 return EmitPCMPSTRM(MI, BB, getTargetMachine().getInstrInfo());
15922 // String/text processing lowering.
15923 case X86::PCMPISTRIREG:
15924 case X86::VPCMPISTRIREG:
15925 case X86::PCMPISTRIMEM:
15926 case X86::VPCMPISTRIMEM:
15927 case X86::PCMPESTRIREG:
15928 case X86::VPCMPESTRIREG:
15929 case X86::PCMPESTRIMEM:
15930 case X86::VPCMPESTRIMEM:
15931 assert(Subtarget->hasSSE42() &&
15932 "Target must have SSE4.2 or AVX features enabled");
15933 return EmitPCMPSTRI(MI, BB, getTargetMachine().getInstrInfo());
15935 // Thread synchronization.
15937 return EmitMonitor(MI, BB, getTargetMachine().getInstrInfo(), Subtarget);
15941 return EmitXBegin(MI, BB, getTargetMachine().getInstrInfo());
15943 // Atomic Lowering.
15944 case X86::ATOMAND8:
15945 case X86::ATOMAND16:
15946 case X86::ATOMAND32:
15947 case X86::ATOMAND64:
15950 case X86::ATOMOR16:
15951 case X86::ATOMOR32:
15952 case X86::ATOMOR64:
15954 case X86::ATOMXOR16:
15955 case X86::ATOMXOR8:
15956 case X86::ATOMXOR32:
15957 case X86::ATOMXOR64:
15959 case X86::ATOMNAND8:
15960 case X86::ATOMNAND16:
15961 case X86::ATOMNAND32:
15962 case X86::ATOMNAND64:
15964 case X86::ATOMMAX8:
15965 case X86::ATOMMAX16:
15966 case X86::ATOMMAX32:
15967 case X86::ATOMMAX64:
15969 case X86::ATOMMIN8:
15970 case X86::ATOMMIN16:
15971 case X86::ATOMMIN32:
15972 case X86::ATOMMIN64:
15974 case X86::ATOMUMAX8:
15975 case X86::ATOMUMAX16:
15976 case X86::ATOMUMAX32:
15977 case X86::ATOMUMAX64:
15979 case X86::ATOMUMIN8:
15980 case X86::ATOMUMIN16:
15981 case X86::ATOMUMIN32:
15982 case X86::ATOMUMIN64:
15983 return EmitAtomicLoadArith(MI, BB);
15985 // This group does 64-bit operations on a 32-bit host.
15986 case X86::ATOMAND6432:
15987 case X86::ATOMOR6432:
15988 case X86::ATOMXOR6432:
15989 case X86::ATOMNAND6432:
15990 case X86::ATOMADD6432:
15991 case X86::ATOMSUB6432:
15992 case X86::ATOMMAX6432:
15993 case X86::ATOMMIN6432:
15994 case X86::ATOMUMAX6432:
15995 case X86::ATOMUMIN6432:
15996 case X86::ATOMSWAP6432:
15997 return EmitAtomicLoadArith6432(MI, BB);
15999 case X86::VASTART_SAVE_XMM_REGS:
16000 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
16002 case X86::VAARG_64:
16003 return EmitVAARG64WithCustomInserter(MI, BB);
16005 case X86::EH_SjLj_SetJmp32:
16006 case X86::EH_SjLj_SetJmp64:
16007 return emitEHSjLjSetJmp(MI, BB);
16009 case X86::EH_SjLj_LongJmp32:
16010 case X86::EH_SjLj_LongJmp64:
16011 return emitEHSjLjLongJmp(MI, BB);
16015 //===----------------------------------------------------------------------===//
16016 // X86 Optimization Hooks
16017 //===----------------------------------------------------------------------===//
16019 void X86TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
16022 const SelectionDAG &DAG,
16023 unsigned Depth) const {
16024 unsigned BitWidth = KnownZero.getBitWidth();
16025 unsigned Opc = Op.getOpcode();
16026 assert((Opc >= ISD::BUILTIN_OP_END ||
16027 Opc == ISD::INTRINSIC_WO_CHAIN ||
16028 Opc == ISD::INTRINSIC_W_CHAIN ||
16029 Opc == ISD::INTRINSIC_VOID) &&
16030 "Should use MaskedValueIsZero if you don't know whether Op"
16031 " is a target node!");
16033 KnownZero = KnownOne = APInt(BitWidth, 0); // Don't know anything.
16047 // These nodes' second result is a boolean.
16048 if (Op.getResNo() == 0)
16051 case X86ISD::SETCC:
16052 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1);
16054 case ISD::INTRINSIC_WO_CHAIN: {
16055 unsigned IntId = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
16056 unsigned NumLoBits = 0;
16059 case Intrinsic::x86_sse_movmsk_ps:
16060 case Intrinsic::x86_avx_movmsk_ps_256:
16061 case Intrinsic::x86_sse2_movmsk_pd:
16062 case Intrinsic::x86_avx_movmsk_pd_256:
16063 case Intrinsic::x86_mmx_pmovmskb:
16064 case Intrinsic::x86_sse2_pmovmskb_128:
16065 case Intrinsic::x86_avx2_pmovmskb: {
16066 // High bits of movmskp{s|d}, pmovmskb are known zero.
16068 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
16069 case Intrinsic::x86_sse_movmsk_ps: NumLoBits = 4; break;
16070 case Intrinsic::x86_avx_movmsk_ps_256: NumLoBits = 8; break;
16071 case Intrinsic::x86_sse2_movmsk_pd: NumLoBits = 2; break;
16072 case Intrinsic::x86_avx_movmsk_pd_256: NumLoBits = 4; break;
16073 case Intrinsic::x86_mmx_pmovmskb: NumLoBits = 8; break;
16074 case Intrinsic::x86_sse2_pmovmskb_128: NumLoBits = 16; break;
16075 case Intrinsic::x86_avx2_pmovmskb: NumLoBits = 32; break;
16077 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - NumLoBits);
16086 unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(SDValue Op,
16087 unsigned Depth) const {
16088 // SETCC_CARRY sets the dest to ~0 for true or 0 for false.
16089 if (Op.getOpcode() == X86ISD::SETCC_CARRY)
16090 return Op.getValueType().getScalarType().getSizeInBits();
16096 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
16097 /// node is a GlobalAddress + offset.
16098 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
16099 const GlobalValue* &GA,
16100 int64_t &Offset) const {
16101 if (N->getOpcode() == X86ISD::Wrapper) {
16102 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
16103 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
16104 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
16108 return TargetLowering::isGAPlusOffset(N, GA, Offset);
16111 /// isShuffleHigh128VectorInsertLow - Checks whether the shuffle node is the
16112 /// same as extracting the high 128-bit part of 256-bit vector and then
16113 /// inserting the result into the low part of a new 256-bit vector
16114 static bool isShuffleHigh128VectorInsertLow(ShuffleVectorSDNode *SVOp) {
16115 EVT VT = SVOp->getValueType(0);
16116 unsigned NumElems = VT.getVectorNumElements();
16118 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
16119 for (unsigned i = 0, j = NumElems/2; i != NumElems/2; ++i, ++j)
16120 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
16121 SVOp->getMaskElt(j) >= 0)
16127 /// isShuffleLow128VectorInsertHigh - Checks whether the shuffle node is the
16128 /// same as extracting the low 128-bit part of 256-bit vector and then
16129 /// inserting the result into the high part of a new 256-bit vector
16130 static bool isShuffleLow128VectorInsertHigh(ShuffleVectorSDNode *SVOp) {
16131 EVT VT = SVOp->getValueType(0);
16132 unsigned NumElems = VT.getVectorNumElements();
16134 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
16135 for (unsigned i = NumElems/2, j = 0; i != NumElems; ++i, ++j)
16136 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
16137 SVOp->getMaskElt(j) >= 0)
16143 /// PerformShuffleCombine256 - Performs shuffle combines for 256-bit vectors.
16144 static SDValue PerformShuffleCombine256(SDNode *N, SelectionDAG &DAG,
16145 TargetLowering::DAGCombinerInfo &DCI,
16146 const X86Subtarget* Subtarget) {
16148 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
16149 SDValue V1 = SVOp->getOperand(0);
16150 SDValue V2 = SVOp->getOperand(1);
16151 EVT VT = SVOp->getValueType(0);
16152 unsigned NumElems = VT.getVectorNumElements();
16154 if (V1.getOpcode() == ISD::CONCAT_VECTORS &&
16155 V2.getOpcode() == ISD::CONCAT_VECTORS) {
16159 // V UNDEF BUILD_VECTOR UNDEF
16161 // CONCAT_VECTOR CONCAT_VECTOR
16164 // RESULT: V + zero extended
16166 if (V2.getOperand(0).getOpcode() != ISD::BUILD_VECTOR ||
16167 V2.getOperand(1).getOpcode() != ISD::UNDEF ||
16168 V1.getOperand(1).getOpcode() != ISD::UNDEF)
16171 if (!ISD::isBuildVectorAllZeros(V2.getOperand(0).getNode()))
16174 // To match the shuffle mask, the first half of the mask should
16175 // be exactly the first vector, and all the rest a splat with the
16176 // first element of the second one.
16177 for (unsigned i = 0; i != NumElems/2; ++i)
16178 if (!isUndefOrEqual(SVOp->getMaskElt(i), i) ||
16179 !isUndefOrEqual(SVOp->getMaskElt(i+NumElems/2), NumElems))
16182 // If V1 is coming from a vector load then just fold to a VZEXT_LOAD.
16183 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(V1.getOperand(0))) {
16184 if (Ld->hasNUsesOfValue(1, 0)) {
16185 SDVTList Tys = DAG.getVTList(MVT::v4i64, MVT::Other);
16186 SDValue Ops[] = { Ld->getChain(), Ld->getBasePtr() };
16188 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops,
16189 array_lengthof(Ops),
16191 Ld->getPointerInfo(),
16192 Ld->getAlignment(),
16193 false/*isVolatile*/, true/*ReadMem*/,
16194 false/*WriteMem*/);
16196 // Make sure the newly-created LOAD is in the same position as Ld in
16197 // terms of dependency. We create a TokenFactor for Ld and ResNode,
16198 // and update uses of Ld's output chain to use the TokenFactor.
16199 if (Ld->hasAnyUseOfValue(1)) {
16200 SDValue NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
16201 SDValue(Ld, 1), SDValue(ResNode.getNode(), 1));
16202 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), NewChain);
16203 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(Ld, 1),
16204 SDValue(ResNode.getNode(), 1));
16207 return DAG.getNode(ISD::BITCAST, dl, VT, ResNode);
16211 // Emit a zeroed vector and insert the desired subvector on its
16213 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
16214 SDValue InsV = Insert128BitVector(Zeros, V1.getOperand(0), 0, DAG, dl);
16215 return DCI.CombineTo(N, InsV);
16218 //===--------------------------------------------------------------------===//
16219 // Combine some shuffles into subvector extracts and inserts:
16222 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
16223 if (isShuffleHigh128VectorInsertLow(SVOp)) {
16224 SDValue V = Extract128BitVector(V1, NumElems/2, DAG, dl);
16225 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, 0, DAG, dl);
16226 return DCI.CombineTo(N, InsV);
16229 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
16230 if (isShuffleLow128VectorInsertHigh(SVOp)) {
16231 SDValue V = Extract128BitVector(V1, 0, DAG, dl);
16232 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, NumElems/2, DAG, dl);
16233 return DCI.CombineTo(N, InsV);
16239 /// PerformShuffleCombine - Performs several different shuffle combines.
16240 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
16241 TargetLowering::DAGCombinerInfo &DCI,
16242 const X86Subtarget *Subtarget) {
16244 EVT VT = N->getValueType(0);
16246 // Don't create instructions with illegal types after legalize types has run.
16247 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
16248 if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType()))
16251 // Combine 256-bit vector shuffles. This is only profitable when in AVX mode
16252 if (Subtarget->hasFp256() && VT.is256BitVector() &&
16253 N->getOpcode() == ISD::VECTOR_SHUFFLE)
16254 return PerformShuffleCombine256(N, DAG, DCI, Subtarget);
16256 // Only handle 128 wide vector from here on.
16257 if (!VT.is128BitVector())
16260 // Combine a vector_shuffle that is equal to build_vector load1, load2, load3,
16261 // load4, <0, 1, 2, 3> into a 128-bit load if the load addresses are
16262 // consecutive, non-overlapping, and in the right order.
16263 SmallVector<SDValue, 16> Elts;
16264 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
16265 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0));
16267 return EltsFromConsecutiveLoads(VT, Elts, dl, DAG);
16270 /// PerformTruncateCombine - Converts truncate operation to
16271 /// a sequence of vector shuffle operations.
16272 /// It is possible when we truncate 256-bit vector to 128-bit vector
16273 static SDValue PerformTruncateCombine(SDNode *N, SelectionDAG &DAG,
16274 TargetLowering::DAGCombinerInfo &DCI,
16275 const X86Subtarget *Subtarget) {
16279 /// XFormVExtractWithShuffleIntoLoad - Check if a vector extract from a target
16280 /// specific shuffle of a load can be folded into a single element load.
16281 /// Similar handling for VECTOR_SHUFFLE is performed by DAGCombiner, but
16282 /// shuffles have been customed lowered so we need to handle those here.
16283 static SDValue XFormVExtractWithShuffleIntoLoad(SDNode *N, SelectionDAG &DAG,
16284 TargetLowering::DAGCombinerInfo &DCI) {
16285 if (DCI.isBeforeLegalizeOps())
16288 SDValue InVec = N->getOperand(0);
16289 SDValue EltNo = N->getOperand(1);
16291 if (!isa<ConstantSDNode>(EltNo))
16294 EVT VT = InVec.getValueType();
16296 bool HasShuffleIntoBitcast = false;
16297 if (InVec.getOpcode() == ISD::BITCAST) {
16298 // Don't duplicate a load with other uses.
16299 if (!InVec.hasOneUse())
16301 EVT BCVT = InVec.getOperand(0).getValueType();
16302 if (BCVT.getVectorNumElements() != VT.getVectorNumElements())
16304 InVec = InVec.getOperand(0);
16305 HasShuffleIntoBitcast = true;
16308 if (!isTargetShuffle(InVec.getOpcode()))
16311 // Don't duplicate a load with other uses.
16312 if (!InVec.hasOneUse())
16315 SmallVector<int, 16> ShuffleMask;
16317 if (!getTargetShuffleMask(InVec.getNode(), VT.getSimpleVT(), ShuffleMask,
16321 // Select the input vector, guarding against out of range extract vector.
16322 unsigned NumElems = VT.getVectorNumElements();
16323 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
16324 int Idx = (Elt > (int)NumElems) ? -1 : ShuffleMask[Elt];
16325 SDValue LdNode = (Idx < (int)NumElems) ? InVec.getOperand(0)
16326 : InVec.getOperand(1);
16328 // If inputs to shuffle are the same for both ops, then allow 2 uses
16329 unsigned AllowedUses = InVec.getOperand(0) == InVec.getOperand(1) ? 2 : 1;
16331 if (LdNode.getOpcode() == ISD::BITCAST) {
16332 // Don't duplicate a load with other uses.
16333 if (!LdNode.getNode()->hasNUsesOfValue(AllowedUses, 0))
16336 AllowedUses = 1; // only allow 1 load use if we have a bitcast
16337 LdNode = LdNode.getOperand(0);
16340 if (!ISD::isNormalLoad(LdNode.getNode()))
16343 LoadSDNode *LN0 = cast<LoadSDNode>(LdNode);
16345 if (!LN0 ||!LN0->hasNUsesOfValue(AllowedUses, 0) || LN0->isVolatile())
16348 if (HasShuffleIntoBitcast) {
16349 // If there's a bitcast before the shuffle, check if the load type and
16350 // alignment is valid.
16351 unsigned Align = LN0->getAlignment();
16352 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
16353 unsigned NewAlign = TLI.getDataLayout()->
16354 getABITypeAlignment(VT.getTypeForEVT(*DAG.getContext()));
16356 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, VT))
16360 // All checks match so transform back to vector_shuffle so that DAG combiner
16361 // can finish the job
16364 // Create shuffle node taking into account the case that its a unary shuffle
16365 SDValue Shuffle = (UnaryShuffle) ? DAG.getUNDEF(VT) : InVec.getOperand(1);
16366 Shuffle = DAG.getVectorShuffle(InVec.getValueType(), dl,
16367 InVec.getOperand(0), Shuffle,
16369 Shuffle = DAG.getNode(ISD::BITCAST, dl, VT, Shuffle);
16370 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, N->getValueType(0), Shuffle,
16374 /// Extract one bit from mask vector, like v16i1 or v8i1.
16375 /// AVX-512 feature.
16376 static SDValue ExtractBitFromMaskVector(SDNode *N, SelectionDAG &DAG) {
16377 SDValue Vec = N->getOperand(0);
16379 MVT VecVT = Vec.getSimpleValueType();
16380 SDValue Idx = N->getOperand(1);
16381 MVT EltVT = N->getSimpleValueType(0);
16383 assert((VecVT.getVectorElementType() == MVT::i1 && EltVT == MVT::i8) ||
16384 "Unexpected operands in ExtractBitFromMaskVector");
16387 if (!isa<ConstantSDNode>(Idx)) {
16388 MVT ExtVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
16389 SDValue Ext = DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVT, Vec);
16390 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
16391 ExtVT.getVectorElementType(), Ext);
16392 return DAG.getNode(ISD::TRUNCATE, dl, EltVT, Elt);
16395 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
16397 MVT ScalarVT = MVT::getIntegerVT(VecVT.getSizeInBits());
16398 unsigned MaxShift = VecVT.getSizeInBits() - 1;
16399 Vec = DAG.getNode(ISD::BITCAST, dl, ScalarVT, Vec);
16400 Vec = DAG.getNode(ISD::SHL, dl, ScalarVT, Vec,
16401 DAG.getConstant(MaxShift - IdxVal, ScalarVT));
16402 Vec = DAG.getNode(ISD::SRL, dl, ScalarVT, Vec,
16403 DAG.getConstant(MaxShift, ScalarVT));
16405 if (VecVT == MVT::v16i1) {
16406 Vec = DAG.getNode(ISD::BITCAST, dl, MVT::i16, Vec);
16407 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Vec);
16409 return DAG.getNode(ISD::BITCAST, dl, MVT::i8, Vec);
16412 /// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index
16413 /// generation and convert it from being a bunch of shuffles and extracts
16414 /// to a simple store and scalar loads to extract the elements.
16415 static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG,
16416 TargetLowering::DAGCombinerInfo &DCI) {
16417 SDValue NewOp = XFormVExtractWithShuffleIntoLoad(N, DAG, DCI);
16418 if (NewOp.getNode())
16421 SDValue InputVector = N->getOperand(0);
16423 if (InputVector.getValueType().getVectorElementType() == MVT::i1 &&
16424 !DCI.isBeforeLegalize())
16425 return ExtractBitFromMaskVector(N, DAG);
16427 // Detect whether we are trying to convert from mmx to i32 and the bitcast
16428 // from mmx to v2i32 has a single usage.
16429 if (InputVector.getNode()->getOpcode() == llvm::ISD::BITCAST &&
16430 InputVector.getNode()->getOperand(0).getValueType() == MVT::x86mmx &&
16431 InputVector.hasOneUse() && N->getValueType(0) == MVT::i32)
16432 return DAG.getNode(X86ISD::MMX_MOVD2W, SDLoc(InputVector),
16433 N->getValueType(0),
16434 InputVector.getNode()->getOperand(0));
16436 // Only operate on vectors of 4 elements, where the alternative shuffling
16437 // gets to be more expensive.
16438 if (InputVector.getValueType() != MVT::v4i32)
16441 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a
16442 // single use which is a sign-extend or zero-extend, and all elements are
16444 SmallVector<SDNode *, 4> Uses;
16445 unsigned ExtractedElements = 0;
16446 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(),
16447 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) {
16448 if (UI.getUse().getResNo() != InputVector.getResNo())
16451 SDNode *Extract = *UI;
16452 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
16455 if (Extract->getValueType(0) != MVT::i32)
16457 if (!Extract->hasOneUse())
16459 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND &&
16460 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND)
16462 if (!isa<ConstantSDNode>(Extract->getOperand(1)))
16465 // Record which element was extracted.
16466 ExtractedElements |=
16467 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue();
16469 Uses.push_back(Extract);
16472 // If not all the elements were used, this may not be worthwhile.
16473 if (ExtractedElements != 15)
16476 // Ok, we've now decided to do the transformation.
16477 SDLoc dl(InputVector);
16479 // Store the value to a temporary stack slot.
16480 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType());
16481 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr,
16482 MachinePointerInfo(), false, false, 0);
16484 // Replace each use (extract) with a load of the appropriate element.
16485 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(),
16486 UE = Uses.end(); UI != UE; ++UI) {
16487 SDNode *Extract = *UI;
16489 // cOMpute the element's address.
16490 SDValue Idx = Extract->getOperand(1);
16492 InputVector.getValueType().getVectorElementType().getSizeInBits()/8;
16493 uint64_t Offset = EltSize * cast<ConstantSDNode>(Idx)->getZExtValue();
16494 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
16495 SDValue OffsetVal = DAG.getConstant(Offset, TLI.getPointerTy());
16497 SDValue ScalarAddr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(),
16498 StackPtr, OffsetVal);
16500 // Load the scalar.
16501 SDValue LoadScalar = DAG.getLoad(Extract->getValueType(0), dl, Ch,
16502 ScalarAddr, MachinePointerInfo(),
16503 false, false, false, 0);
16505 // Replace the exact with the load.
16506 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), LoadScalar);
16509 // The replacement was made in place; don't return anything.
16513 /// \brief Matches a VSELECT onto min/max or return 0 if the node doesn't match.
16514 static std::pair<unsigned, bool>
16515 matchIntegerMINMAX(SDValue Cond, EVT VT, SDValue LHS, SDValue RHS,
16516 SelectionDAG &DAG, const X86Subtarget *Subtarget) {
16517 if (!VT.isVector())
16518 return std::make_pair(0, false);
16520 bool NeedSplit = false;
16521 switch (VT.getSimpleVT().SimpleTy) {
16522 default: return std::make_pair(0, false);
16526 if (!Subtarget->hasAVX2())
16528 if (!Subtarget->hasAVX())
16529 return std::make_pair(0, false);
16534 if (!Subtarget->hasSSE2())
16535 return std::make_pair(0, false);
16538 // SSE2 has only a small subset of the operations.
16539 bool hasUnsigned = Subtarget->hasSSE41() ||
16540 (Subtarget->hasSSE2() && VT == MVT::v16i8);
16541 bool hasSigned = Subtarget->hasSSE41() ||
16542 (Subtarget->hasSSE2() && VT == MVT::v8i16);
16544 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
16547 // Check for x CC y ? x : y.
16548 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
16549 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
16554 Opc = hasUnsigned ? X86ISD::UMIN : 0; break;
16557 Opc = hasUnsigned ? X86ISD::UMAX : 0; break;
16560 Opc = hasSigned ? X86ISD::SMIN : 0; break;
16563 Opc = hasSigned ? X86ISD::SMAX : 0; break;
16565 // Check for x CC y ? y : x -- a min/max with reversed arms.
16566 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
16567 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
16572 Opc = hasUnsigned ? X86ISD::UMAX : 0; break;
16575 Opc = hasUnsigned ? X86ISD::UMIN : 0; break;
16578 Opc = hasSigned ? X86ISD::SMAX : 0; break;
16581 Opc = hasSigned ? X86ISD::SMIN : 0; break;
16585 return std::make_pair(Opc, NeedSplit);
16588 /// PerformSELECTCombine - Do target-specific dag combines on SELECT and VSELECT
16590 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
16591 TargetLowering::DAGCombinerInfo &DCI,
16592 const X86Subtarget *Subtarget) {
16594 SDValue Cond = N->getOperand(0);
16595 // Get the LHS/RHS of the select.
16596 SDValue LHS = N->getOperand(1);
16597 SDValue RHS = N->getOperand(2);
16598 EVT VT = LHS.getValueType();
16599 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
16601 // If we have SSE[12] support, try to form min/max nodes. SSE min/max
16602 // instructions match the semantics of the common C idiom x<y?x:y but not
16603 // x<=y?x:y, because of how they handle negative zero (which can be
16604 // ignored in unsafe-math mode).
16605 if (Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() &&
16606 VT != MVT::f80 && TLI.isTypeLegal(VT) &&
16607 (Subtarget->hasSSE2() ||
16608 (Subtarget->hasSSE1() && VT.getScalarType() == MVT::f32))) {
16609 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
16611 unsigned Opcode = 0;
16612 // Check for x CC y ? x : y.
16613 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
16614 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
16618 // Converting this to a min would handle NaNs incorrectly, and swapping
16619 // the operands would cause it to handle comparisons between positive
16620 // and negative zero incorrectly.
16621 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
16622 if (!DAG.getTarget().Options.UnsafeFPMath &&
16623 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
16625 std::swap(LHS, RHS);
16627 Opcode = X86ISD::FMIN;
16630 // Converting this to a min would handle comparisons between positive
16631 // and negative zero incorrectly.
16632 if (!DAG.getTarget().Options.UnsafeFPMath &&
16633 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
16635 Opcode = X86ISD::FMIN;
16638 // Converting this to a min would handle both negative zeros and NaNs
16639 // incorrectly, but we can swap the operands to fix both.
16640 std::swap(LHS, RHS);
16644 Opcode = X86ISD::FMIN;
16648 // Converting this to a max would handle comparisons between positive
16649 // and negative zero incorrectly.
16650 if (!DAG.getTarget().Options.UnsafeFPMath &&
16651 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
16653 Opcode = X86ISD::FMAX;
16656 // Converting this to a max would handle NaNs incorrectly, and swapping
16657 // the operands would cause it to handle comparisons between positive
16658 // and negative zero incorrectly.
16659 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
16660 if (!DAG.getTarget().Options.UnsafeFPMath &&
16661 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
16663 std::swap(LHS, RHS);
16665 Opcode = X86ISD::FMAX;
16668 // Converting this to a max would handle both negative zeros and NaNs
16669 // incorrectly, but we can swap the operands to fix both.
16670 std::swap(LHS, RHS);
16674 Opcode = X86ISD::FMAX;
16677 // Check for x CC y ? y : x -- a min/max with reversed arms.
16678 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
16679 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
16683 // Converting this to a min would handle comparisons between positive
16684 // and negative zero incorrectly, and swapping the operands would
16685 // cause it to handle NaNs incorrectly.
16686 if (!DAG.getTarget().Options.UnsafeFPMath &&
16687 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) {
16688 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
16690 std::swap(LHS, RHS);
16692 Opcode = X86ISD::FMIN;
16695 // Converting this to a min would handle NaNs incorrectly.
16696 if (!DAG.getTarget().Options.UnsafeFPMath &&
16697 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
16699 Opcode = X86ISD::FMIN;
16702 // Converting this to a min would handle both negative zeros and NaNs
16703 // incorrectly, but we can swap the operands to fix both.
16704 std::swap(LHS, RHS);
16708 Opcode = X86ISD::FMIN;
16712 // Converting this to a max would handle NaNs incorrectly.
16713 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
16715 Opcode = X86ISD::FMAX;
16718 // Converting this to a max would handle comparisons between positive
16719 // and negative zero incorrectly, and swapping the operands would
16720 // cause it to handle NaNs incorrectly.
16721 if (!DAG.getTarget().Options.UnsafeFPMath &&
16722 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) {
16723 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
16725 std::swap(LHS, RHS);
16727 Opcode = X86ISD::FMAX;
16730 // Converting this to a max would handle both negative zeros and NaNs
16731 // incorrectly, but we can swap the operands to fix both.
16732 std::swap(LHS, RHS);
16736 Opcode = X86ISD::FMAX;
16742 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
16745 EVT CondVT = Cond.getValueType();
16746 if (Subtarget->hasAVX512() && VT.isVector() && CondVT.isVector() &&
16747 CondVT.getVectorElementType() == MVT::i1) {
16748 // v16i8 (select v16i1, v16i8, v16i8) does not have a proper
16749 // lowering on AVX-512. In this case we convert it to
16750 // v16i8 (select v16i8, v16i8, v16i8) and use AVX instruction.
16751 // The same situation for all 128 and 256-bit vectors of i8 and i16
16752 EVT OpVT = LHS.getValueType();
16753 if ((OpVT.is128BitVector() || OpVT.is256BitVector()) &&
16754 (OpVT.getVectorElementType() == MVT::i8 ||
16755 OpVT.getVectorElementType() == MVT::i16)) {
16756 Cond = DAG.getNode(ISD::SIGN_EXTEND, DL, OpVT, Cond);
16757 DCI.AddToWorklist(Cond.getNode());
16758 return DAG.getNode(N->getOpcode(), DL, OpVT, Cond, LHS, RHS);
16761 // If this is a select between two integer constants, try to do some
16763 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
16764 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
16765 // Don't do this for crazy integer types.
16766 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
16767 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
16768 // so that TrueC (the true value) is larger than FalseC.
16769 bool NeedsCondInvert = false;
16771 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
16772 // Efficiently invertible.
16773 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
16774 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
16775 isa<ConstantSDNode>(Cond.getOperand(1))))) {
16776 NeedsCondInvert = true;
16777 std::swap(TrueC, FalseC);
16780 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
16781 if (FalseC->getAPIntValue() == 0 &&
16782 TrueC->getAPIntValue().isPowerOf2()) {
16783 if (NeedsCondInvert) // Invert the condition if needed.
16784 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
16785 DAG.getConstant(1, Cond.getValueType()));
16787 // Zero extend the condition if needed.
16788 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
16790 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
16791 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
16792 DAG.getConstant(ShAmt, MVT::i8));
16795 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
16796 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
16797 if (NeedsCondInvert) // Invert the condition if needed.
16798 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
16799 DAG.getConstant(1, Cond.getValueType()));
16801 // Zero extend the condition if needed.
16802 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
16803 FalseC->getValueType(0), Cond);
16804 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
16805 SDValue(FalseC, 0));
16808 // Optimize cases that will turn into an LEA instruction. This requires
16809 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
16810 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
16811 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
16812 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
16814 bool isFastMultiplier = false;
16816 switch ((unsigned char)Diff) {
16818 case 1: // result = add base, cond
16819 case 2: // result = lea base( , cond*2)
16820 case 3: // result = lea base(cond, cond*2)
16821 case 4: // result = lea base( , cond*4)
16822 case 5: // result = lea base(cond, cond*4)
16823 case 8: // result = lea base( , cond*8)
16824 case 9: // result = lea base(cond, cond*8)
16825 isFastMultiplier = true;
16830 if (isFastMultiplier) {
16831 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
16832 if (NeedsCondInvert) // Invert the condition if needed.
16833 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
16834 DAG.getConstant(1, Cond.getValueType()));
16836 // Zero extend the condition if needed.
16837 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
16839 // Scale the condition by the difference.
16841 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
16842 DAG.getConstant(Diff, Cond.getValueType()));
16844 // Add the base if non-zero.
16845 if (FalseC->getAPIntValue() != 0)
16846 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
16847 SDValue(FalseC, 0));
16854 // Canonicalize max and min:
16855 // (x > y) ? x : y -> (x >= y) ? x : y
16856 // (x < y) ? x : y -> (x <= y) ? x : y
16857 // This allows use of COND_S / COND_NS (see TranslateX86CC) which eliminates
16858 // the need for an extra compare
16859 // against zero. e.g.
16860 // (x - y) > 0 : (x - y) ? 0 -> (x - y) >= 0 : (x - y) ? 0
16862 // testl %edi, %edi
16864 // cmovgl %edi, %eax
16868 // cmovsl %eax, %edi
16869 if (N->getOpcode() == ISD::SELECT && Cond.getOpcode() == ISD::SETCC &&
16870 DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
16871 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
16872 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
16877 ISD::CondCode NewCC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGE;
16878 Cond = DAG.getSetCC(SDLoc(Cond), Cond.getValueType(),
16879 Cond.getOperand(0), Cond.getOperand(1), NewCC);
16880 return DAG.getNode(ISD::SELECT, DL, VT, Cond, LHS, RHS);
16885 // Early exit check
16886 if (!TLI.isTypeLegal(VT))
16889 // Match VSELECTs into subs with unsigned saturation.
16890 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC &&
16891 // psubus is available in SSE2 and AVX2 for i8 and i16 vectors.
16892 ((Subtarget->hasSSE2() && (VT == MVT::v16i8 || VT == MVT::v8i16)) ||
16893 (Subtarget->hasAVX2() && (VT == MVT::v32i8 || VT == MVT::v16i16)))) {
16894 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
16896 // Check if one of the arms of the VSELECT is a zero vector. If it's on the
16897 // left side invert the predicate to simplify logic below.
16899 if (ISD::isBuildVectorAllZeros(LHS.getNode())) {
16901 CC = ISD::getSetCCInverse(CC, true);
16902 } else if (ISD::isBuildVectorAllZeros(RHS.getNode())) {
16906 if (Other.getNode() && Other->getNumOperands() == 2 &&
16907 DAG.isEqualTo(Other->getOperand(0), Cond.getOperand(0))) {
16908 SDValue OpLHS = Other->getOperand(0), OpRHS = Other->getOperand(1);
16909 SDValue CondRHS = Cond->getOperand(1);
16911 // Look for a general sub with unsigned saturation first.
16912 // x >= y ? x-y : 0 --> subus x, y
16913 // x > y ? x-y : 0 --> subus x, y
16914 if ((CC == ISD::SETUGE || CC == ISD::SETUGT) &&
16915 Other->getOpcode() == ISD::SUB && DAG.isEqualTo(OpRHS, CondRHS))
16916 return DAG.getNode(X86ISD::SUBUS, DL, VT, OpLHS, OpRHS);
16918 // If the RHS is a constant we have to reverse the const canonicalization.
16919 // x > C-1 ? x+-C : 0 --> subus x, C
16920 if (CC == ISD::SETUGT && Other->getOpcode() == ISD::ADD &&
16921 isSplatVector(CondRHS.getNode()) && isSplatVector(OpRHS.getNode())) {
16922 APInt A = cast<ConstantSDNode>(OpRHS.getOperand(0))->getAPIntValue();
16923 if (CondRHS.getConstantOperandVal(0) == -A-1)
16924 return DAG.getNode(X86ISD::SUBUS, DL, VT, OpLHS,
16925 DAG.getConstant(-A, VT));
16928 // Another special case: If C was a sign bit, the sub has been
16929 // canonicalized into a xor.
16930 // FIXME: Would it be better to use ComputeMaskedBits to determine whether
16931 // it's safe to decanonicalize the xor?
16932 // x s< 0 ? x^C : 0 --> subus x, C
16933 if (CC == ISD::SETLT && Other->getOpcode() == ISD::XOR &&
16934 ISD::isBuildVectorAllZeros(CondRHS.getNode()) &&
16935 isSplatVector(OpRHS.getNode())) {
16936 APInt A = cast<ConstantSDNode>(OpRHS.getOperand(0))->getAPIntValue();
16938 return DAG.getNode(X86ISD::SUBUS, DL, VT, OpLHS, OpRHS);
16943 // Try to match a min/max vector operation.
16944 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC) {
16945 std::pair<unsigned, bool> ret = matchIntegerMINMAX(Cond, VT, LHS, RHS, DAG, Subtarget);
16946 unsigned Opc = ret.first;
16947 bool NeedSplit = ret.second;
16949 if (Opc && NeedSplit) {
16950 unsigned NumElems = VT.getVectorNumElements();
16951 // Extract the LHS vectors
16952 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, DL);
16953 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, DL);
16955 // Extract the RHS vectors
16956 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, DL);
16957 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, DL);
16959 // Create min/max for each subvector
16960 LHS = DAG.getNode(Opc, DL, LHS1.getValueType(), LHS1, RHS1);
16961 RHS = DAG.getNode(Opc, DL, LHS2.getValueType(), LHS2, RHS2);
16963 // Merge the result
16964 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LHS, RHS);
16966 return DAG.getNode(Opc, DL, VT, LHS, RHS);
16969 // Simplify vector selection if the selector will be produced by CMPP*/PCMP*.
16970 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC &&
16971 // Check if SETCC has already been promoted
16972 TLI.getSetCCResultType(*DAG.getContext(), VT) == Cond.getValueType()) {
16974 assert(Cond.getValueType().isVector() &&
16975 "vector select expects a vector selector!");
16977 EVT IntVT = Cond.getValueType();
16978 bool TValIsAllOnes = ISD::isBuildVectorAllOnes(LHS.getNode());
16979 bool FValIsAllZeros = ISD::isBuildVectorAllZeros(RHS.getNode());
16981 if (!TValIsAllOnes && !FValIsAllZeros) {
16982 // Try invert the condition if true value is not all 1s and false value
16984 bool TValIsAllZeros = ISD::isBuildVectorAllZeros(LHS.getNode());
16985 bool FValIsAllOnes = ISD::isBuildVectorAllOnes(RHS.getNode());
16987 if (TValIsAllZeros || FValIsAllOnes) {
16988 SDValue CC = Cond.getOperand(2);
16989 ISD::CondCode NewCC =
16990 ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
16991 Cond.getOperand(0).getValueType().isInteger());
16992 Cond = DAG.getSetCC(DL, IntVT, Cond.getOperand(0), Cond.getOperand(1), NewCC);
16993 std::swap(LHS, RHS);
16994 TValIsAllOnes = FValIsAllOnes;
16995 FValIsAllZeros = TValIsAllZeros;
16999 if (TValIsAllOnes || FValIsAllZeros) {
17002 if (TValIsAllOnes && FValIsAllZeros)
17004 else if (TValIsAllOnes)
17005 Ret = DAG.getNode(ISD::OR, DL, IntVT, Cond,
17006 DAG.getNode(ISD::BITCAST, DL, IntVT, RHS));
17007 else if (FValIsAllZeros)
17008 Ret = DAG.getNode(ISD::AND, DL, IntVT, Cond,
17009 DAG.getNode(ISD::BITCAST, DL, IntVT, LHS));
17011 return DAG.getNode(ISD::BITCAST, DL, VT, Ret);
17015 // If we know that this node is legal then we know that it is going to be
17016 // matched by one of the SSE/AVX BLEND instructions. These instructions only
17017 // depend on the highest bit in each word. Try to use SimplifyDemandedBits
17018 // to simplify previous instructions.
17019 if (N->getOpcode() == ISD::VSELECT && DCI.isBeforeLegalizeOps() &&
17020 !DCI.isBeforeLegalize() && TLI.isOperationLegal(ISD::VSELECT, VT)) {
17021 unsigned BitWidth = Cond.getValueType().getScalarType().getSizeInBits();
17023 // Don't optimize vector selects that map to mask-registers.
17027 // Check all uses of that condition operand to check whether it will be
17028 // consumed by non-BLEND instructions, which may depend on all bits are set
17030 for (SDNode::use_iterator I = Cond->use_begin(),
17031 E = Cond->use_end(); I != E; ++I)
17032 if (I->getOpcode() != ISD::VSELECT)
17033 // TODO: Add other opcodes eventually lowered into BLEND.
17036 assert(BitWidth >= 8 && BitWidth <= 64 && "Invalid mask size");
17037 APInt DemandedMask = APInt::getHighBitsSet(BitWidth, 1);
17039 APInt KnownZero, KnownOne;
17040 TargetLowering::TargetLoweringOpt TLO(DAG, DCI.isBeforeLegalize(),
17041 DCI.isBeforeLegalizeOps());
17042 if (TLO.ShrinkDemandedConstant(Cond, DemandedMask) ||
17043 TLI.SimplifyDemandedBits(Cond, DemandedMask, KnownZero, KnownOne, TLO))
17044 DCI.CommitTargetLoweringOpt(TLO);
17050 // Check whether a boolean test is testing a boolean value generated by
17051 // X86ISD::SETCC. If so, return the operand of that SETCC and proper condition
17054 // Simplify the following patterns:
17055 // (Op (CMP (SETCC Cond EFLAGS) 1) EQ) or
17056 // (Op (CMP (SETCC Cond EFLAGS) 0) NEQ)
17057 // to (Op EFLAGS Cond)
17059 // (Op (CMP (SETCC Cond EFLAGS) 0) EQ) or
17060 // (Op (CMP (SETCC Cond EFLAGS) 1) NEQ)
17061 // to (Op EFLAGS !Cond)
17063 // where Op could be BRCOND or CMOV.
17065 static SDValue checkBoolTestSetCCCombine(SDValue Cmp, X86::CondCode &CC) {
17066 // Quit if not CMP and SUB with its value result used.
17067 if (Cmp.getOpcode() != X86ISD::CMP &&
17068 (Cmp.getOpcode() != X86ISD::SUB || Cmp.getNode()->hasAnyUseOfValue(0)))
17071 // Quit if not used as a boolean value.
17072 if (CC != X86::COND_E && CC != X86::COND_NE)
17075 // Check CMP operands. One of them should be 0 or 1 and the other should be
17076 // an SetCC or extended from it.
17077 SDValue Op1 = Cmp.getOperand(0);
17078 SDValue Op2 = Cmp.getOperand(1);
17081 const ConstantSDNode* C = 0;
17082 bool needOppositeCond = (CC == X86::COND_E);
17083 bool checkAgainstTrue = false; // Is it a comparison against 1?
17085 if ((C = dyn_cast<ConstantSDNode>(Op1)))
17087 else if ((C = dyn_cast<ConstantSDNode>(Op2)))
17089 else // Quit if all operands are not constants.
17092 if (C->getZExtValue() == 1) {
17093 needOppositeCond = !needOppositeCond;
17094 checkAgainstTrue = true;
17095 } else if (C->getZExtValue() != 0)
17096 // Quit if the constant is neither 0 or 1.
17099 bool truncatedToBoolWithAnd = false;
17100 // Skip (zext $x), (trunc $x), or (and $x, 1) node.
17101 while (SetCC.getOpcode() == ISD::ZERO_EXTEND ||
17102 SetCC.getOpcode() == ISD::TRUNCATE ||
17103 SetCC.getOpcode() == ISD::AND) {
17104 if (SetCC.getOpcode() == ISD::AND) {
17106 ConstantSDNode *CS;
17107 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(0))) &&
17108 CS->getZExtValue() == 1)
17110 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(1))) &&
17111 CS->getZExtValue() == 1)
17115 SetCC = SetCC.getOperand(OpIdx);
17116 truncatedToBoolWithAnd = true;
17118 SetCC = SetCC.getOperand(0);
17121 switch (SetCC.getOpcode()) {
17122 case X86ISD::SETCC_CARRY:
17123 // Since SETCC_CARRY gives output based on R = CF ? ~0 : 0, it's unsafe to
17124 // simplify it if the result of SETCC_CARRY is not canonicalized to 0 or 1,
17125 // i.e. it's a comparison against true but the result of SETCC_CARRY is not
17126 // truncated to i1 using 'and'.
17127 if (checkAgainstTrue && !truncatedToBoolWithAnd)
17129 assert(X86::CondCode(SetCC.getConstantOperandVal(0)) == X86::COND_B &&
17130 "Invalid use of SETCC_CARRY!");
17132 case X86ISD::SETCC:
17133 // Set the condition code or opposite one if necessary.
17134 CC = X86::CondCode(SetCC.getConstantOperandVal(0));
17135 if (needOppositeCond)
17136 CC = X86::GetOppositeBranchCondition(CC);
17137 return SetCC.getOperand(1);
17138 case X86ISD::CMOV: {
17139 // Check whether false/true value has canonical one, i.e. 0 or 1.
17140 ConstantSDNode *FVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(0));
17141 ConstantSDNode *TVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(1));
17142 // Quit if true value is not a constant.
17145 // Quit if false value is not a constant.
17147 SDValue Op = SetCC.getOperand(0);
17148 // Skip 'zext' or 'trunc' node.
17149 if (Op.getOpcode() == ISD::ZERO_EXTEND ||
17150 Op.getOpcode() == ISD::TRUNCATE)
17151 Op = Op.getOperand(0);
17152 // A special case for rdrand/rdseed, where 0 is set if false cond is
17154 if ((Op.getOpcode() != X86ISD::RDRAND &&
17155 Op.getOpcode() != X86ISD::RDSEED) || Op.getResNo() != 0)
17158 // Quit if false value is not the constant 0 or 1.
17159 bool FValIsFalse = true;
17160 if (FVal && FVal->getZExtValue() != 0) {
17161 if (FVal->getZExtValue() != 1)
17163 // If FVal is 1, opposite cond is needed.
17164 needOppositeCond = !needOppositeCond;
17165 FValIsFalse = false;
17167 // Quit if TVal is not the constant opposite of FVal.
17168 if (FValIsFalse && TVal->getZExtValue() != 1)
17170 if (!FValIsFalse && TVal->getZExtValue() != 0)
17172 CC = X86::CondCode(SetCC.getConstantOperandVal(2));
17173 if (needOppositeCond)
17174 CC = X86::GetOppositeBranchCondition(CC);
17175 return SetCC.getOperand(3);
17182 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
17183 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
17184 TargetLowering::DAGCombinerInfo &DCI,
17185 const X86Subtarget *Subtarget) {
17188 // If the flag operand isn't dead, don't touch this CMOV.
17189 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
17192 SDValue FalseOp = N->getOperand(0);
17193 SDValue TrueOp = N->getOperand(1);
17194 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
17195 SDValue Cond = N->getOperand(3);
17197 if (CC == X86::COND_E || CC == X86::COND_NE) {
17198 switch (Cond.getOpcode()) {
17202 // If operand of BSR / BSF are proven never zero, then ZF cannot be set.
17203 if (DAG.isKnownNeverZero(Cond.getOperand(0)))
17204 return (CC == X86::COND_E) ? FalseOp : TrueOp;
17210 Flags = checkBoolTestSetCCCombine(Cond, CC);
17211 if (Flags.getNode() &&
17212 // Extra check as FCMOV only supports a subset of X86 cond.
17213 (FalseOp.getValueType() != MVT::f80 || hasFPCMov(CC))) {
17214 SDValue Ops[] = { FalseOp, TrueOp,
17215 DAG.getConstant(CC, MVT::i8), Flags };
17216 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList(),
17217 Ops, array_lengthof(Ops));
17220 // If this is a select between two integer constants, try to do some
17221 // optimizations. Note that the operands are ordered the opposite of SELECT
17223 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(TrueOp)) {
17224 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(FalseOp)) {
17225 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
17226 // larger than FalseC (the false value).
17227 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
17228 CC = X86::GetOppositeBranchCondition(CC);
17229 std::swap(TrueC, FalseC);
17230 std::swap(TrueOp, FalseOp);
17233 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
17234 // This is efficient for any integer data type (including i8/i16) and
17236 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
17237 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
17238 DAG.getConstant(CC, MVT::i8), Cond);
17240 // Zero extend the condition if needed.
17241 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
17243 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
17244 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
17245 DAG.getConstant(ShAmt, MVT::i8));
17246 if (N->getNumValues() == 2) // Dead flag value?
17247 return DCI.CombineTo(N, Cond, SDValue());
17251 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
17252 // for any integer data type, including i8/i16.
17253 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
17254 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
17255 DAG.getConstant(CC, MVT::i8), Cond);
17257 // Zero extend the condition if needed.
17258 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
17259 FalseC->getValueType(0), Cond);
17260 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
17261 SDValue(FalseC, 0));
17263 if (N->getNumValues() == 2) // Dead flag value?
17264 return DCI.CombineTo(N, Cond, SDValue());
17268 // Optimize cases that will turn into an LEA instruction. This requires
17269 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
17270 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
17271 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
17272 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
17274 bool isFastMultiplier = false;
17276 switch ((unsigned char)Diff) {
17278 case 1: // result = add base, cond
17279 case 2: // result = lea base( , cond*2)
17280 case 3: // result = lea base(cond, cond*2)
17281 case 4: // result = lea base( , cond*4)
17282 case 5: // result = lea base(cond, cond*4)
17283 case 8: // result = lea base( , cond*8)
17284 case 9: // result = lea base(cond, cond*8)
17285 isFastMultiplier = true;
17290 if (isFastMultiplier) {
17291 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
17292 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
17293 DAG.getConstant(CC, MVT::i8), Cond);
17294 // Zero extend the condition if needed.
17295 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
17297 // Scale the condition by the difference.
17299 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
17300 DAG.getConstant(Diff, Cond.getValueType()));
17302 // Add the base if non-zero.
17303 if (FalseC->getAPIntValue() != 0)
17304 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
17305 SDValue(FalseC, 0));
17306 if (N->getNumValues() == 2) // Dead flag value?
17307 return DCI.CombineTo(N, Cond, SDValue());
17314 // Handle these cases:
17315 // (select (x != c), e, c) -> select (x != c), e, x),
17316 // (select (x == c), c, e) -> select (x == c), x, e)
17317 // where the c is an integer constant, and the "select" is the combination
17318 // of CMOV and CMP.
17320 // The rationale for this change is that the conditional-move from a constant
17321 // needs two instructions, however, conditional-move from a register needs
17322 // only one instruction.
17324 // CAVEAT: By replacing a constant with a symbolic value, it may obscure
17325 // some instruction-combining opportunities. This opt needs to be
17326 // postponed as late as possible.
17328 if (!DCI.isBeforeLegalize() && !DCI.isBeforeLegalizeOps()) {
17329 // the DCI.xxxx conditions are provided to postpone the optimization as
17330 // late as possible.
17332 ConstantSDNode *CmpAgainst = 0;
17333 if ((Cond.getOpcode() == X86ISD::CMP || Cond.getOpcode() == X86ISD::SUB) &&
17334 (CmpAgainst = dyn_cast<ConstantSDNode>(Cond.getOperand(1))) &&
17335 !isa<ConstantSDNode>(Cond.getOperand(0))) {
17337 if (CC == X86::COND_NE &&
17338 CmpAgainst == dyn_cast<ConstantSDNode>(FalseOp)) {
17339 CC = X86::GetOppositeBranchCondition(CC);
17340 std::swap(TrueOp, FalseOp);
17343 if (CC == X86::COND_E &&
17344 CmpAgainst == dyn_cast<ConstantSDNode>(TrueOp)) {
17345 SDValue Ops[] = { FalseOp, Cond.getOperand(0),
17346 DAG.getConstant(CC, MVT::i8), Cond };
17347 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList (), Ops,
17348 array_lengthof(Ops));
17356 /// PerformMulCombine - Optimize a single multiply with constant into two
17357 /// in order to implement it with two cheaper instructions, e.g.
17358 /// LEA + SHL, LEA + LEA.
17359 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
17360 TargetLowering::DAGCombinerInfo &DCI) {
17361 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
17364 EVT VT = N->getValueType(0);
17365 if (VT != MVT::i64)
17368 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
17371 uint64_t MulAmt = C->getZExtValue();
17372 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
17375 uint64_t MulAmt1 = 0;
17376 uint64_t MulAmt2 = 0;
17377 if ((MulAmt % 9) == 0) {
17379 MulAmt2 = MulAmt / 9;
17380 } else if ((MulAmt % 5) == 0) {
17382 MulAmt2 = MulAmt / 5;
17383 } else if ((MulAmt % 3) == 0) {
17385 MulAmt2 = MulAmt / 3;
17388 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
17391 if (isPowerOf2_64(MulAmt2) &&
17392 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
17393 // If second multiplifer is pow2, issue it first. We want the multiply by
17394 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
17396 std::swap(MulAmt1, MulAmt2);
17399 if (isPowerOf2_64(MulAmt1))
17400 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
17401 DAG.getConstant(Log2_64(MulAmt1), MVT::i8));
17403 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
17404 DAG.getConstant(MulAmt1, VT));
17406 if (isPowerOf2_64(MulAmt2))
17407 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
17408 DAG.getConstant(Log2_64(MulAmt2), MVT::i8));
17410 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
17411 DAG.getConstant(MulAmt2, VT));
17413 // Do not add new nodes to DAG combiner worklist.
17414 DCI.CombineTo(N, NewMul, false);
17419 static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) {
17420 SDValue N0 = N->getOperand(0);
17421 SDValue N1 = N->getOperand(1);
17422 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
17423 EVT VT = N0.getValueType();
17425 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2))
17426 // since the result of setcc_c is all zero's or all ones.
17427 if (VT.isInteger() && !VT.isVector() &&
17428 N1C && N0.getOpcode() == ISD::AND &&
17429 N0.getOperand(1).getOpcode() == ISD::Constant) {
17430 SDValue N00 = N0.getOperand(0);
17431 if (N00.getOpcode() == X86ISD::SETCC_CARRY ||
17432 ((N00.getOpcode() == ISD::ANY_EXTEND ||
17433 N00.getOpcode() == ISD::ZERO_EXTEND) &&
17434 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY)) {
17435 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
17436 APInt ShAmt = N1C->getAPIntValue();
17437 Mask = Mask.shl(ShAmt);
17439 return DAG.getNode(ISD::AND, SDLoc(N), VT,
17440 N00, DAG.getConstant(Mask, VT));
17444 // Hardware support for vector shifts is sparse which makes us scalarize the
17445 // vector operations in many cases. Also, on sandybridge ADD is faster than
17447 // (shl V, 1) -> add V,V
17448 if (isSplatVector(N1.getNode())) {
17449 assert(N0.getValueType().isVector() && "Invalid vector shift type");
17450 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1->getOperand(0));
17451 // We shift all of the values by one. In many cases we do not have
17452 // hardware support for this operation. This is better expressed as an ADD
17454 if (N1C && (1 == N1C->getZExtValue())) {
17455 return DAG.getNode(ISD::ADD, SDLoc(N), VT, N0, N0);
17462 /// \brief Returns a vector of 0s if the node in input is a vector logical
17463 /// shift by a constant amount which is known to be bigger than or equal
17464 /// to the vector element size in bits.
17465 static SDValue performShiftToAllZeros(SDNode *N, SelectionDAG &DAG,
17466 const X86Subtarget *Subtarget) {
17467 EVT VT = N->getValueType(0);
17469 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16 &&
17470 (!Subtarget->hasInt256() ||
17471 (VT != MVT::v4i64 && VT != MVT::v8i32 && VT != MVT::v16i16)))
17474 SDValue Amt = N->getOperand(1);
17476 if (isSplatVector(Amt.getNode())) {
17477 SDValue SclrAmt = Amt->getOperand(0);
17478 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(SclrAmt)) {
17479 APInt ShiftAmt = C->getAPIntValue();
17480 unsigned MaxAmount = VT.getVectorElementType().getSizeInBits();
17482 // SSE2/AVX2 logical shifts always return a vector of 0s
17483 // if the shift amount is bigger than or equal to
17484 // the element size. The constant shift amount will be
17485 // encoded as a 8-bit immediate.
17486 if (ShiftAmt.trunc(8).uge(MaxAmount))
17487 return getZeroVector(VT, Subtarget, DAG, DL);
17494 /// PerformShiftCombine - Combine shifts.
17495 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
17496 TargetLowering::DAGCombinerInfo &DCI,
17497 const X86Subtarget *Subtarget) {
17498 if (N->getOpcode() == ISD::SHL) {
17499 SDValue V = PerformSHLCombine(N, DAG);
17500 if (V.getNode()) return V;
17503 if (N->getOpcode() != ISD::SRA) {
17504 // Try to fold this logical shift into a zero vector.
17505 SDValue V = performShiftToAllZeros(N, DAG, Subtarget);
17506 if (V.getNode()) return V;
17512 // CMPEQCombine - Recognize the distinctive (AND (setcc ...) (setcc ..))
17513 // where both setccs reference the same FP CMP, and rewrite for CMPEQSS
17514 // and friends. Likewise for OR -> CMPNEQSS.
17515 static SDValue CMPEQCombine(SDNode *N, SelectionDAG &DAG,
17516 TargetLowering::DAGCombinerInfo &DCI,
17517 const X86Subtarget *Subtarget) {
17520 // SSE1 supports CMP{eq|ne}SS, and SSE2 added CMP{eq|ne}SD, but
17521 // we're requiring SSE2 for both.
17522 if (Subtarget->hasSSE2() && isAndOrOfSetCCs(SDValue(N, 0U), opcode)) {
17523 SDValue N0 = N->getOperand(0);
17524 SDValue N1 = N->getOperand(1);
17525 SDValue CMP0 = N0->getOperand(1);
17526 SDValue CMP1 = N1->getOperand(1);
17529 // The SETCCs should both refer to the same CMP.
17530 if (CMP0.getOpcode() != X86ISD::CMP || CMP0 != CMP1)
17533 SDValue CMP00 = CMP0->getOperand(0);
17534 SDValue CMP01 = CMP0->getOperand(1);
17535 EVT VT = CMP00.getValueType();
17537 if (VT == MVT::f32 || VT == MVT::f64) {
17538 bool ExpectingFlags = false;
17539 // Check for any users that want flags:
17540 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
17541 !ExpectingFlags && UI != UE; ++UI)
17542 switch (UI->getOpcode()) {
17547 ExpectingFlags = true;
17549 case ISD::CopyToReg:
17550 case ISD::SIGN_EXTEND:
17551 case ISD::ZERO_EXTEND:
17552 case ISD::ANY_EXTEND:
17556 if (!ExpectingFlags) {
17557 enum X86::CondCode cc0 = (enum X86::CondCode)N0.getConstantOperandVal(0);
17558 enum X86::CondCode cc1 = (enum X86::CondCode)N1.getConstantOperandVal(0);
17560 if (cc1 == X86::COND_E || cc1 == X86::COND_NE) {
17561 X86::CondCode tmp = cc0;
17566 if ((cc0 == X86::COND_E && cc1 == X86::COND_NP) ||
17567 (cc0 == X86::COND_NE && cc1 == X86::COND_P)) {
17568 bool is64BitFP = (CMP00.getValueType() == MVT::f64);
17569 X86ISD::NodeType NTOperator = is64BitFP ?
17570 X86ISD::FSETCCsd : X86ISD::FSETCCss;
17571 // FIXME: need symbolic constants for these magic numbers.
17572 // See X86ATTInstPrinter.cpp:printSSECC().
17573 unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4;
17574 SDValue OnesOrZeroesF = DAG.getNode(NTOperator, DL, MVT::f32, CMP00, CMP01,
17575 DAG.getConstant(x86cc, MVT::i8));
17576 SDValue OnesOrZeroesI = DAG.getNode(ISD::BITCAST, DL, MVT::i32,
17578 SDValue ANDed = DAG.getNode(ISD::AND, DL, MVT::i32, OnesOrZeroesI,
17579 DAG.getConstant(1, MVT::i32));
17580 SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8, ANDed);
17581 return OneBitOfTruth;
17589 /// CanFoldXORWithAllOnes - Test whether the XOR operand is a AllOnes vector
17590 /// so it can be folded inside ANDNP.
17591 static bool CanFoldXORWithAllOnes(const SDNode *N) {
17592 EVT VT = N->getValueType(0);
17594 // Match direct AllOnes for 128 and 256-bit vectors
17595 if (ISD::isBuildVectorAllOnes(N))
17598 // Look through a bit convert.
17599 if (N->getOpcode() == ISD::BITCAST)
17600 N = N->getOperand(0).getNode();
17602 // Sometimes the operand may come from a insert_subvector building a 256-bit
17604 if (VT.is256BitVector() &&
17605 N->getOpcode() == ISD::INSERT_SUBVECTOR) {
17606 SDValue V1 = N->getOperand(0);
17607 SDValue V2 = N->getOperand(1);
17609 if (V1.getOpcode() == ISD::INSERT_SUBVECTOR &&
17610 V1.getOperand(0).getOpcode() == ISD::UNDEF &&
17611 ISD::isBuildVectorAllOnes(V1.getOperand(1).getNode()) &&
17612 ISD::isBuildVectorAllOnes(V2.getNode()))
17619 // On AVX/AVX2 the type v8i1 is legalized to v8i16, which is an XMM sized
17620 // register. In most cases we actually compare or select YMM-sized registers
17621 // and mixing the two types creates horrible code. This method optimizes
17622 // some of the transition sequences.
17623 static SDValue WidenMaskArithmetic(SDNode *N, SelectionDAG &DAG,
17624 TargetLowering::DAGCombinerInfo &DCI,
17625 const X86Subtarget *Subtarget) {
17626 EVT VT = N->getValueType(0);
17627 if (!VT.is256BitVector())
17630 assert((N->getOpcode() == ISD::ANY_EXTEND ||
17631 N->getOpcode() == ISD::ZERO_EXTEND ||
17632 N->getOpcode() == ISD::SIGN_EXTEND) && "Invalid Node");
17634 SDValue Narrow = N->getOperand(0);
17635 EVT NarrowVT = Narrow->getValueType(0);
17636 if (!NarrowVT.is128BitVector())
17639 if (Narrow->getOpcode() != ISD::XOR &&
17640 Narrow->getOpcode() != ISD::AND &&
17641 Narrow->getOpcode() != ISD::OR)
17644 SDValue N0 = Narrow->getOperand(0);
17645 SDValue N1 = Narrow->getOperand(1);
17648 // The Left side has to be a trunc.
17649 if (N0.getOpcode() != ISD::TRUNCATE)
17652 // The type of the truncated inputs.
17653 EVT WideVT = N0->getOperand(0)->getValueType(0);
17657 // The right side has to be a 'trunc' or a constant vector.
17658 bool RHSTrunc = N1.getOpcode() == ISD::TRUNCATE;
17659 bool RHSConst = (isSplatVector(N1.getNode()) &&
17660 isa<ConstantSDNode>(N1->getOperand(0)));
17661 if (!RHSTrunc && !RHSConst)
17664 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
17666 if (!TLI.isOperationLegalOrPromote(Narrow->getOpcode(), WideVT))
17669 // Set N0 and N1 to hold the inputs to the new wide operation.
17670 N0 = N0->getOperand(0);
17672 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, WideVT.getScalarType(),
17673 N1->getOperand(0));
17674 SmallVector<SDValue, 8> C(WideVT.getVectorNumElements(), N1);
17675 N1 = DAG.getNode(ISD::BUILD_VECTOR, DL, WideVT, &C[0], C.size());
17676 } else if (RHSTrunc) {
17677 N1 = N1->getOperand(0);
17680 // Generate the wide operation.
17681 SDValue Op = DAG.getNode(Narrow->getOpcode(), DL, WideVT, N0, N1);
17682 unsigned Opcode = N->getOpcode();
17684 case ISD::ANY_EXTEND:
17686 case ISD::ZERO_EXTEND: {
17687 unsigned InBits = NarrowVT.getScalarType().getSizeInBits();
17688 APInt Mask = APInt::getAllOnesValue(InBits);
17689 Mask = Mask.zext(VT.getScalarType().getSizeInBits());
17690 return DAG.getNode(ISD::AND, DL, VT,
17691 Op, DAG.getConstant(Mask, VT));
17693 case ISD::SIGN_EXTEND:
17694 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT,
17695 Op, DAG.getValueType(NarrowVT));
17697 llvm_unreachable("Unexpected opcode");
17701 static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG,
17702 TargetLowering::DAGCombinerInfo &DCI,
17703 const X86Subtarget *Subtarget) {
17704 EVT VT = N->getValueType(0);
17705 if (DCI.isBeforeLegalizeOps())
17708 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
17712 // Create BLSI, BLSR, and BZHI instructions
17713 // BLSI is X & (-X)
17714 // BLSR is X & (X-1)
17715 // BZHI is X & ((1 << Y) - 1)
17716 // BEXTR is ((X >> imm) & (2**size-1))
17717 if (VT == MVT::i32 || VT == MVT::i64) {
17718 SDValue N0 = N->getOperand(0);
17719 SDValue N1 = N->getOperand(1);
17722 if (Subtarget->hasBMI()) {
17723 // Check LHS for neg
17724 if (N0.getOpcode() == ISD::SUB && N0.getOperand(1) == N1 &&
17725 isZero(N0.getOperand(0)))
17726 return DAG.getNode(X86ISD::BLSI, DL, VT, N1);
17728 // Check RHS for neg
17729 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1) == N0 &&
17730 isZero(N1.getOperand(0)))
17731 return DAG.getNode(X86ISD::BLSI, DL, VT, N0);
17733 // Check LHS for X-1
17734 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1 &&
17735 isAllOnes(N0.getOperand(1)))
17736 return DAG.getNode(X86ISD::BLSR, DL, VT, N1);
17738 // Check RHS for X-1
17739 if (N1.getOpcode() == ISD::ADD && N1.getOperand(0) == N0 &&
17740 isAllOnes(N1.getOperand(1)))
17741 return DAG.getNode(X86ISD::BLSR, DL, VT, N0);
17744 if (Subtarget->hasBMI2()) {
17745 // Check for (and (add (shl 1, Y), -1), X)
17746 if (N0.getOpcode() == ISD::ADD && isAllOnes(N0.getOperand(1))) {
17747 SDValue N00 = N0.getOperand(0);
17748 if (N00.getOpcode() == ISD::SHL) {
17749 SDValue N001 = N00.getOperand(1);
17750 assert(N001.getValueType() == MVT::i8 && "unexpected type");
17751 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N00.getOperand(0));
17752 if (C && C->getZExtValue() == 1)
17753 return DAG.getNode(X86ISD::BZHI, DL, VT, N1, N001);
17757 // Check for (and X, (add (shl 1, Y), -1))
17758 if (N1.getOpcode() == ISD::ADD && isAllOnes(N1.getOperand(1))) {
17759 SDValue N10 = N1.getOperand(0);
17760 if (N10.getOpcode() == ISD::SHL) {
17761 SDValue N101 = N10.getOperand(1);
17762 assert(N101.getValueType() == MVT::i8 && "unexpected type");
17763 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N10.getOperand(0));
17764 if (C && C->getZExtValue() == 1)
17765 return DAG.getNode(X86ISD::BZHI, DL, VT, N0, N101);
17770 // Check for BEXTR.
17771 if ((Subtarget->hasBMI() || Subtarget->hasTBM()) &&
17772 (N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::SRL)) {
17773 ConstantSDNode *MaskNode = dyn_cast<ConstantSDNode>(N1);
17774 ConstantSDNode *ShiftNode = dyn_cast<ConstantSDNode>(N0.getOperand(1));
17775 if (MaskNode && ShiftNode) {
17776 uint64_t Mask = MaskNode->getZExtValue();
17777 uint64_t Shift = ShiftNode->getZExtValue();
17778 if (isMask_64(Mask)) {
17779 uint64_t MaskSize = CountPopulation_64(Mask);
17780 if (Shift + MaskSize <= VT.getSizeInBits())
17781 return DAG.getNode(X86ISD::BEXTR, DL, VT, N0.getOperand(0),
17782 DAG.getConstant(Shift | (MaskSize << 8), VT));
17790 // Want to form ANDNP nodes:
17791 // 1) In the hopes of then easily combining them with OR and AND nodes
17792 // to form PBLEND/PSIGN.
17793 // 2) To match ANDN packed intrinsics
17794 if (VT != MVT::v2i64 && VT != MVT::v4i64)
17797 SDValue N0 = N->getOperand(0);
17798 SDValue N1 = N->getOperand(1);
17801 // Check LHS for vnot
17802 if (N0.getOpcode() == ISD::XOR &&
17803 //ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode()))
17804 CanFoldXORWithAllOnes(N0.getOperand(1).getNode()))
17805 return DAG.getNode(X86ISD::ANDNP, DL, VT, N0.getOperand(0), N1);
17807 // Check RHS for vnot
17808 if (N1.getOpcode() == ISD::XOR &&
17809 //ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode()))
17810 CanFoldXORWithAllOnes(N1.getOperand(1).getNode()))
17811 return DAG.getNode(X86ISD::ANDNP, DL, VT, N1.getOperand(0), N0);
17816 static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
17817 TargetLowering::DAGCombinerInfo &DCI,
17818 const X86Subtarget *Subtarget) {
17819 EVT VT = N->getValueType(0);
17820 if (DCI.isBeforeLegalizeOps())
17823 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
17827 SDValue N0 = N->getOperand(0);
17828 SDValue N1 = N->getOperand(1);
17830 // look for psign/blend
17831 if (VT == MVT::v2i64 || VT == MVT::v4i64) {
17832 if (!Subtarget->hasSSSE3() ||
17833 (VT == MVT::v4i64 && !Subtarget->hasInt256()))
17836 // Canonicalize pandn to RHS
17837 if (N0.getOpcode() == X86ISD::ANDNP)
17839 // or (and (m, y), (pandn m, x))
17840 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::ANDNP) {
17841 SDValue Mask = N1.getOperand(0);
17842 SDValue X = N1.getOperand(1);
17844 if (N0.getOperand(0) == Mask)
17845 Y = N0.getOperand(1);
17846 if (N0.getOperand(1) == Mask)
17847 Y = N0.getOperand(0);
17849 // Check to see if the mask appeared in both the AND and ANDNP and
17853 // Validate that X, Y, and Mask are BIT_CONVERTS, and see through them.
17854 // Look through mask bitcast.
17855 if (Mask.getOpcode() == ISD::BITCAST)
17856 Mask = Mask.getOperand(0);
17857 if (X.getOpcode() == ISD::BITCAST)
17858 X = X.getOperand(0);
17859 if (Y.getOpcode() == ISD::BITCAST)
17860 Y = Y.getOperand(0);
17862 EVT MaskVT = Mask.getValueType();
17864 // Validate that the Mask operand is a vector sra node.
17865 // FIXME: what to do for bytes, since there is a psignb/pblendvb, but
17866 // there is no psrai.b
17867 unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits();
17868 unsigned SraAmt = ~0;
17869 if (Mask.getOpcode() == ISD::SRA) {
17870 SDValue Amt = Mask.getOperand(1);
17871 if (isSplatVector(Amt.getNode())) {
17872 SDValue SclrAmt = Amt->getOperand(0);
17873 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(SclrAmt))
17874 SraAmt = C->getZExtValue();
17876 } else if (Mask.getOpcode() == X86ISD::VSRAI) {
17877 SDValue SraC = Mask.getOperand(1);
17878 SraAmt = cast<ConstantSDNode>(SraC)->getZExtValue();
17880 if ((SraAmt + 1) != EltBits)
17885 // Now we know we at least have a plendvb with the mask val. See if
17886 // we can form a psignb/w/d.
17887 // psign = x.type == y.type == mask.type && y = sub(0, x);
17888 if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X &&
17889 ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) &&
17890 X.getValueType() == MaskVT && Y.getValueType() == MaskVT) {
17891 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
17892 "Unsupported VT for PSIGN");
17893 Mask = DAG.getNode(X86ISD::PSIGN, DL, MaskVT, X, Mask.getOperand(0));
17894 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
17896 // PBLENDVB only available on SSE 4.1
17897 if (!Subtarget->hasSSE41())
17900 EVT BlendVT = (VT == MVT::v4i64) ? MVT::v32i8 : MVT::v16i8;
17902 X = DAG.getNode(ISD::BITCAST, DL, BlendVT, X);
17903 Y = DAG.getNode(ISD::BITCAST, DL, BlendVT, Y);
17904 Mask = DAG.getNode(ISD::BITCAST, DL, BlendVT, Mask);
17905 Mask = DAG.getNode(ISD::VSELECT, DL, BlendVT, Mask, Y, X);
17906 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
17910 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64)
17913 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
17914 MachineFunction &MF = DAG.getMachineFunction();
17915 bool OptForSize = MF.getFunction()->getAttributes().
17916 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
17918 // SHLD/SHRD instructions have lower register pressure, but on some
17919 // platforms they have higher latency than the equivalent
17920 // series of shifts/or that would otherwise be generated.
17921 // Don't fold (or (x << c) | (y >> (64 - c))) if SHLD/SHRD instructions
17922 // have higer latencies and we are not optimizing for size.
17923 if (!OptForSize && Subtarget->isSHLDSlow())
17926 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
17928 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
17930 if (!N0.hasOneUse() || !N1.hasOneUse())
17933 SDValue ShAmt0 = N0.getOperand(1);
17934 if (ShAmt0.getValueType() != MVT::i8)
17936 SDValue ShAmt1 = N1.getOperand(1);
17937 if (ShAmt1.getValueType() != MVT::i8)
17939 if (ShAmt0.getOpcode() == ISD::TRUNCATE)
17940 ShAmt0 = ShAmt0.getOperand(0);
17941 if (ShAmt1.getOpcode() == ISD::TRUNCATE)
17942 ShAmt1 = ShAmt1.getOperand(0);
17945 unsigned Opc = X86ISD::SHLD;
17946 SDValue Op0 = N0.getOperand(0);
17947 SDValue Op1 = N1.getOperand(0);
17948 if (ShAmt0.getOpcode() == ISD::SUB) {
17949 Opc = X86ISD::SHRD;
17950 std::swap(Op0, Op1);
17951 std::swap(ShAmt0, ShAmt1);
17954 unsigned Bits = VT.getSizeInBits();
17955 if (ShAmt1.getOpcode() == ISD::SUB) {
17956 SDValue Sum = ShAmt1.getOperand(0);
17957 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) {
17958 SDValue ShAmt1Op1 = ShAmt1.getOperand(1);
17959 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE)
17960 ShAmt1Op1 = ShAmt1Op1.getOperand(0);
17961 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0)
17962 return DAG.getNode(Opc, DL, VT,
17964 DAG.getNode(ISD::TRUNCATE, DL,
17967 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) {
17968 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0);
17970 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits)
17971 return DAG.getNode(Opc, DL, VT,
17972 N0.getOperand(0), N1.getOperand(0),
17973 DAG.getNode(ISD::TRUNCATE, DL,
17980 // Generate NEG and CMOV for integer abs.
17981 static SDValue performIntegerAbsCombine(SDNode *N, SelectionDAG &DAG) {
17982 EVT VT = N->getValueType(0);
17984 // Since X86 does not have CMOV for 8-bit integer, we don't convert
17985 // 8-bit integer abs to NEG and CMOV.
17986 if (VT.isInteger() && VT.getSizeInBits() == 8)
17989 SDValue N0 = N->getOperand(0);
17990 SDValue N1 = N->getOperand(1);
17993 // Check pattern of XOR(ADD(X,Y), Y) where Y is SRA(X, size(X)-1)
17994 // and change it to SUB and CMOV.
17995 if (VT.isInteger() && N->getOpcode() == ISD::XOR &&
17996 N0.getOpcode() == ISD::ADD &&
17997 N0.getOperand(1) == N1 &&
17998 N1.getOpcode() == ISD::SRA &&
17999 N1.getOperand(0) == N0.getOperand(0))
18000 if (ConstantSDNode *Y1C = dyn_cast<ConstantSDNode>(N1.getOperand(1)))
18001 if (Y1C->getAPIntValue() == VT.getSizeInBits()-1) {
18002 // Generate SUB & CMOV.
18003 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, DAG.getVTList(VT, MVT::i32),
18004 DAG.getConstant(0, VT), N0.getOperand(0));
18006 SDValue Ops[] = { N0.getOperand(0), Neg,
18007 DAG.getConstant(X86::COND_GE, MVT::i8),
18008 SDValue(Neg.getNode(), 1) };
18009 return DAG.getNode(X86ISD::CMOV, DL, DAG.getVTList(VT, MVT::Glue),
18010 Ops, array_lengthof(Ops));
18015 // PerformXorCombine - Attempts to turn XOR nodes into BLSMSK nodes
18016 static SDValue PerformXorCombine(SDNode *N, SelectionDAG &DAG,
18017 TargetLowering::DAGCombinerInfo &DCI,
18018 const X86Subtarget *Subtarget) {
18019 EVT VT = N->getValueType(0);
18020 if (DCI.isBeforeLegalizeOps())
18023 if (Subtarget->hasCMov()) {
18024 SDValue RV = performIntegerAbsCombine(N, DAG);
18029 // Try forming BMI if it is available.
18030 if (!Subtarget->hasBMI())
18033 if (VT != MVT::i32 && VT != MVT::i64)
18036 assert(Subtarget->hasBMI() && "Creating BLSMSK requires BMI instructions");
18038 // Create BLSMSK instructions by finding X ^ (X-1)
18039 SDValue N0 = N->getOperand(0);
18040 SDValue N1 = N->getOperand(1);
18043 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1 &&
18044 isAllOnes(N0.getOperand(1)))
18045 return DAG.getNode(X86ISD::BLSMSK, DL, VT, N1);
18047 if (N1.getOpcode() == ISD::ADD && N1.getOperand(0) == N0 &&
18048 isAllOnes(N1.getOperand(1)))
18049 return DAG.getNode(X86ISD::BLSMSK, DL, VT, N0);
18054 /// PerformLOADCombine - Do target-specific dag combines on LOAD nodes.
18055 static SDValue PerformLOADCombine(SDNode *N, SelectionDAG &DAG,
18056 TargetLowering::DAGCombinerInfo &DCI,
18057 const X86Subtarget *Subtarget) {
18058 LoadSDNode *Ld = cast<LoadSDNode>(N);
18059 EVT RegVT = Ld->getValueType(0);
18060 EVT MemVT = Ld->getMemoryVT();
18062 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
18063 unsigned RegSz = RegVT.getSizeInBits();
18065 // On Sandybridge unaligned 256bit loads are inefficient.
18066 ISD::LoadExtType Ext = Ld->getExtensionType();
18067 unsigned Alignment = Ld->getAlignment();
18068 bool IsAligned = Alignment == 0 || Alignment >= MemVT.getSizeInBits()/8;
18069 if (RegVT.is256BitVector() && !Subtarget->hasInt256() &&
18070 !DCI.isBeforeLegalizeOps() && !IsAligned && Ext == ISD::NON_EXTLOAD) {
18071 unsigned NumElems = RegVT.getVectorNumElements();
18075 SDValue Ptr = Ld->getBasePtr();
18076 SDValue Increment = DAG.getConstant(16, TLI.getPointerTy());
18078 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
18080 SDValue Load1 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
18081 Ld->getPointerInfo(), Ld->isVolatile(),
18082 Ld->isNonTemporal(), Ld->isInvariant(),
18084 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
18085 SDValue Load2 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
18086 Ld->getPointerInfo(), Ld->isVolatile(),
18087 Ld->isNonTemporal(), Ld->isInvariant(),
18088 std::min(16U, Alignment));
18089 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
18091 Load2.getValue(1));
18093 SDValue NewVec = DAG.getUNDEF(RegVT);
18094 NewVec = Insert128BitVector(NewVec, Load1, 0, DAG, dl);
18095 NewVec = Insert128BitVector(NewVec, Load2, NumElems/2, DAG, dl);
18096 return DCI.CombineTo(N, NewVec, TF, true);
18099 // If this is a vector EXT Load then attempt to optimize it using a
18100 // shuffle. If SSSE3 is not available we may emit an illegal shuffle but the
18101 // expansion is still better than scalar code.
18102 // We generate X86ISD::VSEXT for SEXTLOADs if it's available, otherwise we'll
18103 // emit a shuffle and a arithmetic shift.
18104 // TODO: It is possible to support ZExt by zeroing the undef values
18105 // during the shuffle phase or after the shuffle.
18106 if (RegVT.isVector() && RegVT.isInteger() && Subtarget->hasSSE2() &&
18107 (Ext == ISD::EXTLOAD || Ext == ISD::SEXTLOAD)) {
18108 assert(MemVT != RegVT && "Cannot extend to the same type");
18109 assert(MemVT.isVector() && "Must load a vector from memory");
18111 unsigned NumElems = RegVT.getVectorNumElements();
18112 unsigned MemSz = MemVT.getSizeInBits();
18113 assert(RegSz > MemSz && "Register size must be greater than the mem size");
18115 if (Ext == ISD::SEXTLOAD && RegSz == 256 && !Subtarget->hasInt256())
18118 // All sizes must be a power of two.
18119 if (!isPowerOf2_32(RegSz * MemSz * NumElems))
18122 // Attempt to load the original value using scalar loads.
18123 // Find the largest scalar type that divides the total loaded size.
18124 MVT SclrLoadTy = MVT::i8;
18125 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
18126 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
18127 MVT Tp = (MVT::SimpleValueType)tp;
18128 if (TLI.isTypeLegal(Tp) && ((MemSz % Tp.getSizeInBits()) == 0)) {
18133 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
18134 if (TLI.isTypeLegal(MVT::f64) && SclrLoadTy.getSizeInBits() < 64 &&
18136 SclrLoadTy = MVT::f64;
18138 // Calculate the number of scalar loads that we need to perform
18139 // in order to load our vector from memory.
18140 unsigned NumLoads = MemSz / SclrLoadTy.getSizeInBits();
18141 if (Ext == ISD::SEXTLOAD && NumLoads > 1)
18144 unsigned loadRegZize = RegSz;
18145 if (Ext == ISD::SEXTLOAD && RegSz == 256)
18148 // Represent our vector as a sequence of elements which are the
18149 // largest scalar that we can load.
18150 EVT LoadUnitVecVT = EVT::getVectorVT(*DAG.getContext(), SclrLoadTy,
18151 loadRegZize/SclrLoadTy.getSizeInBits());
18153 // Represent the data using the same element type that is stored in
18154 // memory. In practice, we ''widen'' MemVT.
18156 EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
18157 loadRegZize/MemVT.getScalarType().getSizeInBits());
18159 assert(WideVecVT.getSizeInBits() == LoadUnitVecVT.getSizeInBits() &&
18160 "Invalid vector type");
18162 // We can't shuffle using an illegal type.
18163 if (!TLI.isTypeLegal(WideVecVT))
18166 SmallVector<SDValue, 8> Chains;
18167 SDValue Ptr = Ld->getBasePtr();
18168 SDValue Increment = DAG.getConstant(SclrLoadTy.getSizeInBits()/8,
18169 TLI.getPointerTy());
18170 SDValue Res = DAG.getUNDEF(LoadUnitVecVT);
18172 for (unsigned i = 0; i < NumLoads; ++i) {
18173 // Perform a single load.
18174 SDValue ScalarLoad = DAG.getLoad(SclrLoadTy, dl, Ld->getChain(),
18175 Ptr, Ld->getPointerInfo(),
18176 Ld->isVolatile(), Ld->isNonTemporal(),
18177 Ld->isInvariant(), Ld->getAlignment());
18178 Chains.push_back(ScalarLoad.getValue(1));
18179 // Create the first element type using SCALAR_TO_VECTOR in order to avoid
18180 // another round of DAGCombining.
18182 Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LoadUnitVecVT, ScalarLoad);
18184 Res = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, LoadUnitVecVT, Res,
18185 ScalarLoad, DAG.getIntPtrConstant(i));
18187 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
18190 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0],
18193 // Bitcast the loaded value to a vector of the original element type, in
18194 // the size of the target vector type.
18195 SDValue SlicedVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, Res);
18196 unsigned SizeRatio = RegSz/MemSz;
18198 if (Ext == ISD::SEXTLOAD) {
18199 // If we have SSE4.1 we can directly emit a VSEXT node.
18200 if (Subtarget->hasSSE41()) {
18201 SDValue Sext = DAG.getNode(X86ISD::VSEXT, dl, RegVT, SlicedVec);
18202 return DCI.CombineTo(N, Sext, TF, true);
18205 // Otherwise we'll shuffle the small elements in the high bits of the
18206 // larger type and perform an arithmetic shift. If the shift is not legal
18207 // it's better to scalarize.
18208 if (!TLI.isOperationLegalOrCustom(ISD::SRA, RegVT))
18211 // Redistribute the loaded elements into the different locations.
18212 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
18213 for (unsigned i = 0; i != NumElems; ++i)
18214 ShuffleVec[i*SizeRatio + SizeRatio-1] = i;
18216 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec,
18217 DAG.getUNDEF(WideVecVT),
18220 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
18222 // Build the arithmetic shift.
18223 unsigned Amt = RegVT.getVectorElementType().getSizeInBits() -
18224 MemVT.getVectorElementType().getSizeInBits();
18225 Shuff = DAG.getNode(ISD::SRA, dl, RegVT, Shuff,
18226 DAG.getConstant(Amt, RegVT));
18228 return DCI.CombineTo(N, Shuff, TF, true);
18231 // Redistribute the loaded elements into the different locations.
18232 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
18233 for (unsigned i = 0; i != NumElems; ++i)
18234 ShuffleVec[i*SizeRatio] = i;
18236 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec,
18237 DAG.getUNDEF(WideVecVT),
18240 // Bitcast to the requested type.
18241 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
18242 // Replace the original load with the new sequence
18243 // and return the new chain.
18244 return DCI.CombineTo(N, Shuff, TF, true);
18250 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
18251 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
18252 const X86Subtarget *Subtarget) {
18253 StoreSDNode *St = cast<StoreSDNode>(N);
18254 EVT VT = St->getValue().getValueType();
18255 EVT StVT = St->getMemoryVT();
18257 SDValue StoredVal = St->getOperand(1);
18258 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
18260 // If we are saving a concatenation of two XMM registers, perform two stores.
18261 // On Sandy Bridge, 256-bit memory operations are executed by two
18262 // 128-bit ports. However, on Haswell it is better to issue a single 256-bit
18263 // memory operation.
18264 unsigned Alignment = St->getAlignment();
18265 bool IsAligned = Alignment == 0 || Alignment >= VT.getSizeInBits()/8;
18266 if (VT.is256BitVector() && !Subtarget->hasInt256() &&
18267 StVT == VT && !IsAligned) {
18268 unsigned NumElems = VT.getVectorNumElements();
18272 SDValue Value0 = Extract128BitVector(StoredVal, 0, DAG, dl);
18273 SDValue Value1 = Extract128BitVector(StoredVal, NumElems/2, DAG, dl);
18275 SDValue Stride = DAG.getConstant(16, TLI.getPointerTy());
18276 SDValue Ptr0 = St->getBasePtr();
18277 SDValue Ptr1 = DAG.getNode(ISD::ADD, dl, Ptr0.getValueType(), Ptr0, Stride);
18279 SDValue Ch0 = DAG.getStore(St->getChain(), dl, Value0, Ptr0,
18280 St->getPointerInfo(), St->isVolatile(),
18281 St->isNonTemporal(), Alignment);
18282 SDValue Ch1 = DAG.getStore(St->getChain(), dl, Value1, Ptr1,
18283 St->getPointerInfo(), St->isVolatile(),
18284 St->isNonTemporal(),
18285 std::min(16U, Alignment));
18286 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ch0, Ch1);
18289 // Optimize trunc store (of multiple scalars) to shuffle and store.
18290 // First, pack all of the elements in one place. Next, store to memory
18291 // in fewer chunks.
18292 if (St->isTruncatingStore() && VT.isVector()) {
18293 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
18294 unsigned NumElems = VT.getVectorNumElements();
18295 assert(StVT != VT && "Cannot truncate to the same type");
18296 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
18297 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
18299 // From, To sizes and ElemCount must be pow of two
18300 if (!isPowerOf2_32(NumElems * FromSz * ToSz)) return SDValue();
18301 // We are going to use the original vector elt for storing.
18302 // Accumulated smaller vector elements must be a multiple of the store size.
18303 if (0 != (NumElems * FromSz) % ToSz) return SDValue();
18305 unsigned SizeRatio = FromSz / ToSz;
18307 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
18309 // Create a type on which we perform the shuffle
18310 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
18311 StVT.getScalarType(), NumElems*SizeRatio);
18313 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
18315 SDValue WideVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, St->getValue());
18316 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
18317 for (unsigned i = 0; i != NumElems; ++i)
18318 ShuffleVec[i] = i * SizeRatio;
18320 // Can't shuffle using an illegal type.
18321 if (!TLI.isTypeLegal(WideVecVT))
18324 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
18325 DAG.getUNDEF(WideVecVT),
18327 // At this point all of the data is stored at the bottom of the
18328 // register. We now need to save it to mem.
18330 // Find the largest store unit
18331 MVT StoreType = MVT::i8;
18332 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
18333 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
18334 MVT Tp = (MVT::SimpleValueType)tp;
18335 if (TLI.isTypeLegal(Tp) && Tp.getSizeInBits() <= NumElems * ToSz)
18339 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
18340 if (TLI.isTypeLegal(MVT::f64) && StoreType.getSizeInBits() < 64 &&
18341 (64 <= NumElems * ToSz))
18342 StoreType = MVT::f64;
18344 // Bitcast the original vector into a vector of store-size units
18345 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(),
18346 StoreType, VT.getSizeInBits()/StoreType.getSizeInBits());
18347 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits());
18348 SDValue ShuffWide = DAG.getNode(ISD::BITCAST, dl, StoreVecVT, Shuff);
18349 SmallVector<SDValue, 8> Chains;
18350 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits()/8,
18351 TLI.getPointerTy());
18352 SDValue Ptr = St->getBasePtr();
18354 // Perform one or more big stores into memory.
18355 for (unsigned i=0, e=(ToSz*NumElems)/StoreType.getSizeInBits(); i!=e; ++i) {
18356 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
18357 StoreType, ShuffWide,
18358 DAG.getIntPtrConstant(i));
18359 SDValue Ch = DAG.getStore(St->getChain(), dl, SubVec, Ptr,
18360 St->getPointerInfo(), St->isVolatile(),
18361 St->isNonTemporal(), St->getAlignment());
18362 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
18363 Chains.push_back(Ch);
18366 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0],
18370 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
18371 // the FP state in cases where an emms may be missing.
18372 // A preferable solution to the general problem is to figure out the right
18373 // places to insert EMMS. This qualifies as a quick hack.
18375 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
18376 if (VT.getSizeInBits() != 64)
18379 const Function *F = DAG.getMachineFunction().getFunction();
18380 bool NoImplicitFloatOps = F->getAttributes().
18381 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoImplicitFloat);
18382 bool F64IsLegal = !DAG.getTarget().Options.UseSoftFloat && !NoImplicitFloatOps
18383 && Subtarget->hasSSE2();
18384 if ((VT.isVector() ||
18385 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
18386 isa<LoadSDNode>(St->getValue()) &&
18387 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
18388 St->getChain().hasOneUse() && !St->isVolatile()) {
18389 SDNode* LdVal = St->getValue().getNode();
18390 LoadSDNode *Ld = 0;
18391 int TokenFactorIndex = -1;
18392 SmallVector<SDValue, 8> Ops;
18393 SDNode* ChainVal = St->getChain().getNode();
18394 // Must be a store of a load. We currently handle two cases: the load
18395 // is a direct child, and it's under an intervening TokenFactor. It is
18396 // possible to dig deeper under nested TokenFactors.
18397 if (ChainVal == LdVal)
18398 Ld = cast<LoadSDNode>(St->getChain());
18399 else if (St->getValue().hasOneUse() &&
18400 ChainVal->getOpcode() == ISD::TokenFactor) {
18401 for (unsigned i = 0, e = ChainVal->getNumOperands(); i != e; ++i) {
18402 if (ChainVal->getOperand(i).getNode() == LdVal) {
18403 TokenFactorIndex = i;
18404 Ld = cast<LoadSDNode>(St->getValue());
18406 Ops.push_back(ChainVal->getOperand(i));
18410 if (!Ld || !ISD::isNormalLoad(Ld))
18413 // If this is not the MMX case, i.e. we are just turning i64 load/store
18414 // into f64 load/store, avoid the transformation if there are multiple
18415 // uses of the loaded value.
18416 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
18421 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
18422 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
18424 if (Subtarget->is64Bit() || F64IsLegal) {
18425 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
18426 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(),
18427 Ld->getPointerInfo(), Ld->isVolatile(),
18428 Ld->isNonTemporal(), Ld->isInvariant(),
18429 Ld->getAlignment());
18430 SDValue NewChain = NewLd.getValue(1);
18431 if (TokenFactorIndex != -1) {
18432 Ops.push_back(NewChain);
18433 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
18436 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
18437 St->getPointerInfo(),
18438 St->isVolatile(), St->isNonTemporal(),
18439 St->getAlignment());
18442 // Otherwise, lower to two pairs of 32-bit loads / stores.
18443 SDValue LoAddr = Ld->getBasePtr();
18444 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
18445 DAG.getConstant(4, MVT::i32));
18447 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
18448 Ld->getPointerInfo(),
18449 Ld->isVolatile(), Ld->isNonTemporal(),
18450 Ld->isInvariant(), Ld->getAlignment());
18451 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
18452 Ld->getPointerInfo().getWithOffset(4),
18453 Ld->isVolatile(), Ld->isNonTemporal(),
18455 MinAlign(Ld->getAlignment(), 4));
18457 SDValue NewChain = LoLd.getValue(1);
18458 if (TokenFactorIndex != -1) {
18459 Ops.push_back(LoLd);
18460 Ops.push_back(HiLd);
18461 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
18465 LoAddr = St->getBasePtr();
18466 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
18467 DAG.getConstant(4, MVT::i32));
18469 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
18470 St->getPointerInfo(),
18471 St->isVolatile(), St->isNonTemporal(),
18472 St->getAlignment());
18473 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
18474 St->getPointerInfo().getWithOffset(4),
18476 St->isNonTemporal(),
18477 MinAlign(St->getAlignment(), 4));
18478 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
18483 /// isHorizontalBinOp - Return 'true' if this vector operation is "horizontal"
18484 /// and return the operands for the horizontal operation in LHS and RHS. A
18485 /// horizontal operation performs the binary operation on successive elements
18486 /// of its first operand, then on successive elements of its second operand,
18487 /// returning the resulting values in a vector. For example, if
18488 /// A = < float a0, float a1, float a2, float a3 >
18490 /// B = < float b0, float b1, float b2, float b3 >
18491 /// then the result of doing a horizontal operation on A and B is
18492 /// A horizontal-op B = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >.
18493 /// In short, LHS and RHS are inspected to see if LHS op RHS is of the form
18494 /// A horizontal-op B, for some already available A and B, and if so then LHS is
18495 /// set to A, RHS to B, and the routine returns 'true'.
18496 /// Note that the binary operation should have the property that if one of the
18497 /// operands is UNDEF then the result is UNDEF.
18498 static bool isHorizontalBinOp(SDValue &LHS, SDValue &RHS, bool IsCommutative) {
18499 // Look for the following pattern: if
18500 // A = < float a0, float a1, float a2, float a3 >
18501 // B = < float b0, float b1, float b2, float b3 >
18503 // LHS = VECTOR_SHUFFLE A, B, <0, 2, 4, 6>
18504 // RHS = VECTOR_SHUFFLE A, B, <1, 3, 5, 7>
18505 // then LHS op RHS = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >
18506 // which is A horizontal-op B.
18508 // At least one of the operands should be a vector shuffle.
18509 if (LHS.getOpcode() != ISD::VECTOR_SHUFFLE &&
18510 RHS.getOpcode() != ISD::VECTOR_SHUFFLE)
18513 MVT VT = LHS.getSimpleValueType();
18515 assert((VT.is128BitVector() || VT.is256BitVector()) &&
18516 "Unsupported vector type for horizontal add/sub");
18518 // Handle 128 and 256-bit vector lengths. AVX defines horizontal add/sub to
18519 // operate independently on 128-bit lanes.
18520 unsigned NumElts = VT.getVectorNumElements();
18521 unsigned NumLanes = VT.getSizeInBits()/128;
18522 unsigned NumLaneElts = NumElts / NumLanes;
18523 assert((NumLaneElts % 2 == 0) &&
18524 "Vector type should have an even number of elements in each lane");
18525 unsigned HalfLaneElts = NumLaneElts/2;
18527 // View LHS in the form
18528 // LHS = VECTOR_SHUFFLE A, B, LMask
18529 // If LHS is not a shuffle then pretend it is the shuffle
18530 // LHS = VECTOR_SHUFFLE LHS, undef, <0, 1, ..., N-1>
18531 // NOTE: in what follows a default initialized SDValue represents an UNDEF of
18534 SmallVector<int, 16> LMask(NumElts);
18535 if (LHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
18536 if (LHS.getOperand(0).getOpcode() != ISD::UNDEF)
18537 A = LHS.getOperand(0);
18538 if (LHS.getOperand(1).getOpcode() != ISD::UNDEF)
18539 B = LHS.getOperand(1);
18540 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(LHS.getNode())->getMask();
18541 std::copy(Mask.begin(), Mask.end(), LMask.begin());
18543 if (LHS.getOpcode() != ISD::UNDEF)
18545 for (unsigned i = 0; i != NumElts; ++i)
18549 // Likewise, view RHS in the form
18550 // RHS = VECTOR_SHUFFLE C, D, RMask
18552 SmallVector<int, 16> RMask(NumElts);
18553 if (RHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
18554 if (RHS.getOperand(0).getOpcode() != ISD::UNDEF)
18555 C = RHS.getOperand(0);
18556 if (RHS.getOperand(1).getOpcode() != ISD::UNDEF)
18557 D = RHS.getOperand(1);
18558 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(RHS.getNode())->getMask();
18559 std::copy(Mask.begin(), Mask.end(), RMask.begin());
18561 if (RHS.getOpcode() != ISD::UNDEF)
18563 for (unsigned i = 0; i != NumElts; ++i)
18567 // Check that the shuffles are both shuffling the same vectors.
18568 if (!(A == C && B == D) && !(A == D && B == C))
18571 // If everything is UNDEF then bail out: it would be better to fold to UNDEF.
18572 if (!A.getNode() && !B.getNode())
18575 // If A and B occur in reverse order in RHS, then "swap" them (which means
18576 // rewriting the mask).
18578 CommuteVectorShuffleMask(RMask, NumElts);
18580 // At this point LHS and RHS are equivalent to
18581 // LHS = VECTOR_SHUFFLE A, B, LMask
18582 // RHS = VECTOR_SHUFFLE A, B, RMask
18583 // Check that the masks correspond to performing a horizontal operation.
18584 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
18585 for (unsigned i = 0; i != NumLaneElts; ++i) {
18586 int LIdx = LMask[i+l], RIdx = RMask[i+l];
18588 // Ignore any UNDEF components.
18589 if (LIdx < 0 || RIdx < 0 ||
18590 (!A.getNode() && (LIdx < (int)NumElts || RIdx < (int)NumElts)) ||
18591 (!B.getNode() && (LIdx >= (int)NumElts || RIdx >= (int)NumElts)))
18594 // Check that successive elements are being operated on. If not, this is
18595 // not a horizontal operation.
18596 unsigned Src = (i/HalfLaneElts); // each lane is split between srcs
18597 int Index = 2*(i%HalfLaneElts) + NumElts*Src + l;
18598 if (!(LIdx == Index && RIdx == Index + 1) &&
18599 !(IsCommutative && LIdx == Index + 1 && RIdx == Index))
18604 LHS = A.getNode() ? A : B; // If A is 'UNDEF', use B for it.
18605 RHS = B.getNode() ? B : A; // If B is 'UNDEF', use A for it.
18609 /// PerformFADDCombine - Do target-specific dag combines on floating point adds.
18610 static SDValue PerformFADDCombine(SDNode *N, SelectionDAG &DAG,
18611 const X86Subtarget *Subtarget) {
18612 EVT VT = N->getValueType(0);
18613 SDValue LHS = N->getOperand(0);
18614 SDValue RHS = N->getOperand(1);
18616 // Try to synthesize horizontal adds from adds of shuffles.
18617 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
18618 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
18619 isHorizontalBinOp(LHS, RHS, true))
18620 return DAG.getNode(X86ISD::FHADD, SDLoc(N), VT, LHS, RHS);
18624 /// PerformFSUBCombine - Do target-specific dag combines on floating point subs.
18625 static SDValue PerformFSUBCombine(SDNode *N, SelectionDAG &DAG,
18626 const X86Subtarget *Subtarget) {
18627 EVT VT = N->getValueType(0);
18628 SDValue LHS = N->getOperand(0);
18629 SDValue RHS = N->getOperand(1);
18631 // Try to synthesize horizontal subs from subs of shuffles.
18632 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
18633 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
18634 isHorizontalBinOp(LHS, RHS, false))
18635 return DAG.getNode(X86ISD::FHSUB, SDLoc(N), VT, LHS, RHS);
18639 /// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and
18640 /// X86ISD::FXOR nodes.
18641 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
18642 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
18643 // F[X]OR(0.0, x) -> x
18644 // F[X]OR(x, 0.0) -> x
18645 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
18646 if (C->getValueAPF().isPosZero())
18647 return N->getOperand(1);
18648 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
18649 if (C->getValueAPF().isPosZero())
18650 return N->getOperand(0);
18654 /// PerformFMinFMaxCombine - Do target-specific dag combines on X86ISD::FMIN and
18655 /// X86ISD::FMAX nodes.
18656 static SDValue PerformFMinFMaxCombine(SDNode *N, SelectionDAG &DAG) {
18657 assert(N->getOpcode() == X86ISD::FMIN || N->getOpcode() == X86ISD::FMAX);
18659 // Only perform optimizations if UnsafeMath is used.
18660 if (!DAG.getTarget().Options.UnsafeFPMath)
18663 // If we run in unsafe-math mode, then convert the FMAX and FMIN nodes
18664 // into FMINC and FMAXC, which are Commutative operations.
18665 unsigned NewOp = 0;
18666 switch (N->getOpcode()) {
18667 default: llvm_unreachable("unknown opcode");
18668 case X86ISD::FMIN: NewOp = X86ISD::FMINC; break;
18669 case X86ISD::FMAX: NewOp = X86ISD::FMAXC; break;
18672 return DAG.getNode(NewOp, SDLoc(N), N->getValueType(0),
18673 N->getOperand(0), N->getOperand(1));
18676 /// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes.
18677 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
18678 // FAND(0.0, x) -> 0.0
18679 // FAND(x, 0.0) -> 0.0
18680 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
18681 if (C->getValueAPF().isPosZero())
18682 return N->getOperand(0);
18683 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
18684 if (C->getValueAPF().isPosZero())
18685 return N->getOperand(1);
18689 /// PerformFANDNCombine - Do target-specific dag combines on X86ISD::FANDN nodes
18690 static SDValue PerformFANDNCombine(SDNode *N, SelectionDAG &DAG) {
18691 // FANDN(x, 0.0) -> 0.0
18692 // FANDN(0.0, x) -> x
18693 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
18694 if (C->getValueAPF().isPosZero())
18695 return N->getOperand(1);
18696 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
18697 if (C->getValueAPF().isPosZero())
18698 return N->getOperand(1);
18702 static SDValue PerformBTCombine(SDNode *N,
18704 TargetLowering::DAGCombinerInfo &DCI) {
18705 // BT ignores high bits in the bit index operand.
18706 SDValue Op1 = N->getOperand(1);
18707 if (Op1.hasOneUse()) {
18708 unsigned BitWidth = Op1.getValueSizeInBits();
18709 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
18710 APInt KnownZero, KnownOne;
18711 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
18712 !DCI.isBeforeLegalizeOps());
18713 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
18714 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
18715 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
18716 DCI.CommitTargetLoweringOpt(TLO);
18721 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
18722 SDValue Op = N->getOperand(0);
18723 if (Op.getOpcode() == ISD::BITCAST)
18724 Op = Op.getOperand(0);
18725 EVT VT = N->getValueType(0), OpVT = Op.getValueType();
18726 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
18727 VT.getVectorElementType().getSizeInBits() ==
18728 OpVT.getVectorElementType().getSizeInBits()) {
18729 return DAG.getNode(ISD::BITCAST, SDLoc(N), VT, Op);
18734 static SDValue PerformSIGN_EXTEND_INREGCombine(SDNode *N, SelectionDAG &DAG,
18735 const X86Subtarget *Subtarget) {
18736 EVT VT = N->getValueType(0);
18737 if (!VT.isVector())
18740 SDValue N0 = N->getOperand(0);
18741 SDValue N1 = N->getOperand(1);
18742 EVT ExtraVT = cast<VTSDNode>(N1)->getVT();
18745 // The SIGN_EXTEND_INREG to v4i64 is expensive operation on the
18746 // both SSE and AVX2 since there is no sign-extended shift right
18747 // operation on a vector with 64-bit elements.
18748 //(sext_in_reg (v4i64 anyext (v4i32 x )), ExtraVT) ->
18749 // (v4i64 sext (v4i32 sext_in_reg (v4i32 x , ExtraVT)))
18750 if (VT == MVT::v4i64 && (N0.getOpcode() == ISD::ANY_EXTEND ||
18751 N0.getOpcode() == ISD::SIGN_EXTEND)) {
18752 SDValue N00 = N0.getOperand(0);
18754 // EXTLOAD has a better solution on AVX2,
18755 // it may be replaced with X86ISD::VSEXT node.
18756 if (N00.getOpcode() == ISD::LOAD && Subtarget->hasInt256())
18757 if (!ISD::isNormalLoad(N00.getNode()))
18760 if (N00.getValueType() == MVT::v4i32 && ExtraVT.getSizeInBits() < 128) {
18761 SDValue Tmp = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v4i32,
18763 return DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i64, Tmp);
18769 static SDValue PerformSExtCombine(SDNode *N, SelectionDAG &DAG,
18770 TargetLowering::DAGCombinerInfo &DCI,
18771 const X86Subtarget *Subtarget) {
18772 if (!DCI.isBeforeLegalizeOps())
18775 if (!Subtarget->hasFp256())
18778 EVT VT = N->getValueType(0);
18779 if (VT.isVector() && VT.getSizeInBits() == 256) {
18780 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget);
18788 static SDValue PerformFMACombine(SDNode *N, SelectionDAG &DAG,
18789 const X86Subtarget* Subtarget) {
18791 EVT VT = N->getValueType(0);
18793 // Let legalize expand this if it isn't a legal type yet.
18794 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
18797 EVT ScalarVT = VT.getScalarType();
18798 if ((ScalarVT != MVT::f32 && ScalarVT != MVT::f64) ||
18799 (!Subtarget->hasFMA() && !Subtarget->hasFMA4()))
18802 SDValue A = N->getOperand(0);
18803 SDValue B = N->getOperand(1);
18804 SDValue C = N->getOperand(2);
18806 bool NegA = (A.getOpcode() == ISD::FNEG);
18807 bool NegB = (B.getOpcode() == ISD::FNEG);
18808 bool NegC = (C.getOpcode() == ISD::FNEG);
18810 // Negative multiplication when NegA xor NegB
18811 bool NegMul = (NegA != NegB);
18813 A = A.getOperand(0);
18815 B = B.getOperand(0);
18817 C = C.getOperand(0);
18821 Opcode = (!NegC) ? X86ISD::FMADD : X86ISD::FMSUB;
18823 Opcode = (!NegC) ? X86ISD::FNMADD : X86ISD::FNMSUB;
18825 return DAG.getNode(Opcode, dl, VT, A, B, C);
18828 static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG,
18829 TargetLowering::DAGCombinerInfo &DCI,
18830 const X86Subtarget *Subtarget) {
18831 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) ->
18832 // (and (i32 x86isd::setcc_carry), 1)
18833 // This eliminates the zext. This transformation is necessary because
18834 // ISD::SETCC is always legalized to i8.
18836 SDValue N0 = N->getOperand(0);
18837 EVT VT = N->getValueType(0);
18839 if (N0.getOpcode() == ISD::AND &&
18841 N0.getOperand(0).hasOneUse()) {
18842 SDValue N00 = N0.getOperand(0);
18843 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
18844 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
18845 if (!C || C->getZExtValue() != 1)
18847 return DAG.getNode(ISD::AND, dl, VT,
18848 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
18849 N00.getOperand(0), N00.getOperand(1)),
18850 DAG.getConstant(1, VT));
18854 if (VT.is256BitVector()) {
18855 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget);
18863 // Optimize x == -y --> x+y == 0
18864 // x != -y --> x+y != 0
18865 static SDValue PerformISDSETCCCombine(SDNode *N, SelectionDAG &DAG) {
18866 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
18867 SDValue LHS = N->getOperand(0);
18868 SDValue RHS = N->getOperand(1);
18870 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && LHS.getOpcode() == ISD::SUB)
18871 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(LHS.getOperand(0)))
18872 if (C->getAPIntValue() == 0 && LHS.hasOneUse()) {
18873 SDValue addV = DAG.getNode(ISD::ADD, SDLoc(N),
18874 LHS.getValueType(), RHS, LHS.getOperand(1));
18875 return DAG.getSetCC(SDLoc(N), N->getValueType(0),
18876 addV, DAG.getConstant(0, addV.getValueType()), CC);
18878 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && RHS.getOpcode() == ISD::SUB)
18879 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS.getOperand(0)))
18880 if (C->getAPIntValue() == 0 && RHS.hasOneUse()) {
18881 SDValue addV = DAG.getNode(ISD::ADD, SDLoc(N),
18882 RHS.getValueType(), LHS, RHS.getOperand(1));
18883 return DAG.getSetCC(SDLoc(N), N->getValueType(0),
18884 addV, DAG.getConstant(0, addV.getValueType()), CC);
18889 // Helper function of PerformSETCCCombine. It is to materialize "setb reg"
18890 // as "sbb reg,reg", since it can be extended without zext and produces
18891 // an all-ones bit which is more useful than 0/1 in some cases.
18892 static SDValue MaterializeSETB(SDLoc DL, SDValue EFLAGS, SelectionDAG &DAG) {
18893 return DAG.getNode(ISD::AND, DL, MVT::i8,
18894 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
18895 DAG.getConstant(X86::COND_B, MVT::i8), EFLAGS),
18896 DAG.getConstant(1, MVT::i8));
18899 // Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT
18900 static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG,
18901 TargetLowering::DAGCombinerInfo &DCI,
18902 const X86Subtarget *Subtarget) {
18904 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(0));
18905 SDValue EFLAGS = N->getOperand(1);
18907 if (CC == X86::COND_A) {
18908 // Try to convert COND_A into COND_B in an attempt to facilitate
18909 // materializing "setb reg".
18911 // Do not flip "e > c", where "c" is a constant, because Cmp instruction
18912 // cannot take an immediate as its first operand.
18914 if (EFLAGS.getOpcode() == X86ISD::SUB && EFLAGS.hasOneUse() &&
18915 EFLAGS.getValueType().isInteger() &&
18916 !isa<ConstantSDNode>(EFLAGS.getOperand(1))) {
18917 SDValue NewSub = DAG.getNode(X86ISD::SUB, SDLoc(EFLAGS),
18918 EFLAGS.getNode()->getVTList(),
18919 EFLAGS.getOperand(1), EFLAGS.getOperand(0));
18920 SDValue NewEFLAGS = SDValue(NewSub.getNode(), EFLAGS.getResNo());
18921 return MaterializeSETB(DL, NewEFLAGS, DAG);
18925 // Materialize "setb reg" as "sbb reg,reg", since it can be extended without
18926 // a zext and produces an all-ones bit which is more useful than 0/1 in some
18928 if (CC == X86::COND_B)
18929 return MaterializeSETB(DL, EFLAGS, DAG);
18933 Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
18934 if (Flags.getNode()) {
18935 SDValue Cond = DAG.getConstant(CC, MVT::i8);
18936 return DAG.getNode(X86ISD::SETCC, DL, N->getVTList(), Cond, Flags);
18942 // Optimize branch condition evaluation.
18944 static SDValue PerformBrCondCombine(SDNode *N, SelectionDAG &DAG,
18945 TargetLowering::DAGCombinerInfo &DCI,
18946 const X86Subtarget *Subtarget) {
18948 SDValue Chain = N->getOperand(0);
18949 SDValue Dest = N->getOperand(1);
18950 SDValue EFLAGS = N->getOperand(3);
18951 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(2));
18955 Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
18956 if (Flags.getNode()) {
18957 SDValue Cond = DAG.getConstant(CC, MVT::i8);
18958 return DAG.getNode(X86ISD::BRCOND, DL, N->getVTList(), Chain, Dest, Cond,
18965 static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
18966 const X86TargetLowering *XTLI) {
18967 SDValue Op0 = N->getOperand(0);
18968 EVT InVT = Op0->getValueType(0);
18970 // SINT_TO_FP(v4i8) -> SINT_TO_FP(SEXT(v4i8 to v4i32))
18971 if (InVT == MVT::v8i8 || InVT == MVT::v4i8) {
18973 MVT DstVT = InVT == MVT::v4i8 ? MVT::v4i32 : MVT::v8i32;
18974 SDValue P = DAG.getNode(ISD::SIGN_EXTEND, dl, DstVT, Op0);
18975 return DAG.getNode(ISD::SINT_TO_FP, dl, N->getValueType(0), P);
18978 // Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have
18979 // a 32-bit target where SSE doesn't support i64->FP operations.
18980 if (Op0.getOpcode() == ISD::LOAD) {
18981 LoadSDNode *Ld = cast<LoadSDNode>(Op0.getNode());
18982 EVT VT = Ld->getValueType(0);
18983 if (!Ld->isVolatile() && !N->getValueType(0).isVector() &&
18984 ISD::isNON_EXTLoad(Op0.getNode()) && Op0.hasOneUse() &&
18985 !XTLI->getSubtarget()->is64Bit() &&
18987 SDValue FILDChain = XTLI->BuildFILD(SDValue(N, 0), Ld->getValueType(0),
18988 Ld->getChain(), Op0, DAG);
18989 DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), FILDChain.getValue(1));
18996 // Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS
18997 static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG,
18998 X86TargetLowering::DAGCombinerInfo &DCI) {
18999 // If the LHS and RHS of the ADC node are zero, then it can't overflow and
19000 // the result is either zero or one (depending on the input carry bit).
19001 // Strength reduce this down to a "set on carry" aka SETCC_CARRY&1.
19002 if (X86::isZeroNode(N->getOperand(0)) &&
19003 X86::isZeroNode(N->getOperand(1)) &&
19004 // We don't have a good way to replace an EFLAGS use, so only do this when
19006 SDValue(N, 1).use_empty()) {
19008 EVT VT = N->getValueType(0);
19009 SDValue CarryOut = DAG.getConstant(0, N->getValueType(1));
19010 SDValue Res1 = DAG.getNode(ISD::AND, DL, VT,
19011 DAG.getNode(X86ISD::SETCC_CARRY, DL, VT,
19012 DAG.getConstant(X86::COND_B,MVT::i8),
19014 DAG.getConstant(1, VT));
19015 return DCI.CombineTo(N, Res1, CarryOut);
19021 // fold (add Y, (sete X, 0)) -> adc 0, Y
19022 // (add Y, (setne X, 0)) -> sbb -1, Y
19023 // (sub (sete X, 0), Y) -> sbb 0, Y
19024 // (sub (setne X, 0), Y) -> adc -1, Y
19025 static SDValue OptimizeConditionalInDecrement(SDNode *N, SelectionDAG &DAG) {
19028 // Look through ZExts.
19029 SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0);
19030 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse())
19033 SDValue SetCC = Ext.getOperand(0);
19034 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse())
19037 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0);
19038 if (CC != X86::COND_E && CC != X86::COND_NE)
19041 SDValue Cmp = SetCC.getOperand(1);
19042 if (Cmp.getOpcode() != X86ISD::CMP || !Cmp.hasOneUse() ||
19043 !X86::isZeroNode(Cmp.getOperand(1)) ||
19044 !Cmp.getOperand(0).getValueType().isInteger())
19047 SDValue CmpOp0 = Cmp.getOperand(0);
19048 SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, CmpOp0,
19049 DAG.getConstant(1, CmpOp0.getValueType()));
19051 SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1);
19052 if (CC == X86::COND_NE)
19053 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB,
19054 DL, OtherVal.getValueType(), OtherVal,
19055 DAG.getConstant(-1ULL, OtherVal.getValueType()), NewCmp);
19056 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC,
19057 DL, OtherVal.getValueType(), OtherVal,
19058 DAG.getConstant(0, OtherVal.getValueType()), NewCmp);
19061 /// PerformADDCombine - Do target-specific dag combines on integer adds.
19062 static SDValue PerformAddCombine(SDNode *N, SelectionDAG &DAG,
19063 const X86Subtarget *Subtarget) {
19064 EVT VT = N->getValueType(0);
19065 SDValue Op0 = N->getOperand(0);
19066 SDValue Op1 = N->getOperand(1);
19068 // Try to synthesize horizontal adds from adds of shuffles.
19069 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
19070 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
19071 isHorizontalBinOp(Op0, Op1, true))
19072 return DAG.getNode(X86ISD::HADD, SDLoc(N), VT, Op0, Op1);
19074 return OptimizeConditionalInDecrement(N, DAG);
19077 static SDValue PerformSubCombine(SDNode *N, SelectionDAG &DAG,
19078 const X86Subtarget *Subtarget) {
19079 SDValue Op0 = N->getOperand(0);
19080 SDValue Op1 = N->getOperand(1);
19082 // X86 can't encode an immediate LHS of a sub. See if we can push the
19083 // negation into a preceding instruction.
19084 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op0)) {
19085 // If the RHS of the sub is a XOR with one use and a constant, invert the
19086 // immediate. Then add one to the LHS of the sub so we can turn
19087 // X-Y -> X+~Y+1, saving one register.
19088 if (Op1->hasOneUse() && Op1.getOpcode() == ISD::XOR &&
19089 isa<ConstantSDNode>(Op1.getOperand(1))) {
19090 APInt XorC = cast<ConstantSDNode>(Op1.getOperand(1))->getAPIntValue();
19091 EVT VT = Op0.getValueType();
19092 SDValue NewXor = DAG.getNode(ISD::XOR, SDLoc(Op1), VT,
19094 DAG.getConstant(~XorC, VT));
19095 return DAG.getNode(ISD::ADD, SDLoc(N), VT, NewXor,
19096 DAG.getConstant(C->getAPIntValue()+1, VT));
19100 // Try to synthesize horizontal adds from adds of shuffles.
19101 EVT VT = N->getValueType(0);
19102 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
19103 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
19104 isHorizontalBinOp(Op0, Op1, true))
19105 return DAG.getNode(X86ISD::HSUB, SDLoc(N), VT, Op0, Op1);
19107 return OptimizeConditionalInDecrement(N, DAG);
19110 /// performVZEXTCombine - Performs build vector combines
19111 static SDValue performVZEXTCombine(SDNode *N, SelectionDAG &DAG,
19112 TargetLowering::DAGCombinerInfo &DCI,
19113 const X86Subtarget *Subtarget) {
19114 // (vzext (bitcast (vzext (x)) -> (vzext x)
19115 SDValue In = N->getOperand(0);
19116 while (In.getOpcode() == ISD::BITCAST)
19117 In = In.getOperand(0);
19119 if (In.getOpcode() != X86ISD::VZEXT)
19122 return DAG.getNode(X86ISD::VZEXT, SDLoc(N), N->getValueType(0),
19126 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
19127 DAGCombinerInfo &DCI) const {
19128 SelectionDAG &DAG = DCI.DAG;
19129 switch (N->getOpcode()) {
19131 case ISD::EXTRACT_VECTOR_ELT:
19132 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, DCI);
19134 case ISD::SELECT: return PerformSELECTCombine(N, DAG, DCI, Subtarget);
19135 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI, Subtarget);
19136 case ISD::ADD: return PerformAddCombine(N, DAG, Subtarget);
19137 case ISD::SUB: return PerformSubCombine(N, DAG, Subtarget);
19138 case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI);
19139 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
19142 case ISD::SRL: return PerformShiftCombine(N, DAG, DCI, Subtarget);
19143 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget);
19144 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget);
19145 case ISD::XOR: return PerformXorCombine(N, DAG, DCI, Subtarget);
19146 case ISD::LOAD: return PerformLOADCombine(N, DAG, DCI, Subtarget);
19147 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
19148 case ISD::SINT_TO_FP: return PerformSINT_TO_FPCombine(N, DAG, this);
19149 case ISD::FADD: return PerformFADDCombine(N, DAG, Subtarget);
19150 case ISD::FSUB: return PerformFSUBCombine(N, DAG, Subtarget);
19152 case X86ISD::FOR: return PerformFORCombine(N, DAG);
19154 case X86ISD::FMAX: return PerformFMinFMaxCombine(N, DAG);
19155 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
19156 case X86ISD::FANDN: return PerformFANDNCombine(N, DAG);
19157 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
19158 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
19159 case ISD::ANY_EXTEND:
19160 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG, DCI, Subtarget);
19161 case ISD::SIGN_EXTEND: return PerformSExtCombine(N, DAG, DCI, Subtarget);
19162 case ISD::SIGN_EXTEND_INREG: return PerformSIGN_EXTEND_INREGCombine(N, DAG, Subtarget);
19163 case ISD::TRUNCATE: return PerformTruncateCombine(N, DAG,DCI,Subtarget);
19164 case ISD::SETCC: return PerformISDSETCCCombine(N, DAG);
19165 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG, DCI, Subtarget);
19166 case X86ISD::BRCOND: return PerformBrCondCombine(N, DAG, DCI, Subtarget);
19167 case X86ISD::VZEXT: return performVZEXTCombine(N, DAG, DCI, Subtarget);
19168 case X86ISD::SHUFP: // Handle all target specific shuffles
19169 case X86ISD::PALIGNR:
19170 case X86ISD::UNPCKH:
19171 case X86ISD::UNPCKL:
19172 case X86ISD::MOVHLPS:
19173 case X86ISD::MOVLHPS:
19174 case X86ISD::PSHUFD:
19175 case X86ISD::PSHUFHW:
19176 case X86ISD::PSHUFLW:
19177 case X86ISD::MOVSS:
19178 case X86ISD::MOVSD:
19179 case X86ISD::VPERMILP:
19180 case X86ISD::VPERM2X128:
19181 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget);
19182 case ISD::FMA: return PerformFMACombine(N, DAG, Subtarget);
19188 /// isTypeDesirableForOp - Return true if the target has native support for
19189 /// the specified value type and it is 'desirable' to use the type for the
19190 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
19191 /// instruction encodings are longer and some i16 instructions are slow.
19192 bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const {
19193 if (!isTypeLegal(VT))
19195 if (VT != MVT::i16)
19202 case ISD::SIGN_EXTEND:
19203 case ISD::ZERO_EXTEND:
19204 case ISD::ANY_EXTEND:
19217 /// IsDesirableToPromoteOp - This method query the target whether it is
19218 /// beneficial for dag combiner to promote the specified node. If true, it
19219 /// should return the desired promotion type by reference.
19220 bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
19221 EVT VT = Op.getValueType();
19222 if (VT != MVT::i16)
19225 bool Promote = false;
19226 bool Commute = false;
19227 switch (Op.getOpcode()) {
19230 LoadSDNode *LD = cast<LoadSDNode>(Op);
19231 // If the non-extending load has a single use and it's not live out, then it
19232 // might be folded.
19233 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&&
19234 Op.hasOneUse()*/) {
19235 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
19236 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
19237 // The only case where we'd want to promote LOAD (rather then it being
19238 // promoted as an operand is when it's only use is liveout.
19239 if (UI->getOpcode() != ISD::CopyToReg)
19246 case ISD::SIGN_EXTEND:
19247 case ISD::ZERO_EXTEND:
19248 case ISD::ANY_EXTEND:
19253 SDValue N0 = Op.getOperand(0);
19254 // Look out for (store (shl (load), x)).
19255 if (MayFoldLoad(N0) && MayFoldIntoStore(Op))
19268 SDValue N0 = Op.getOperand(0);
19269 SDValue N1 = Op.getOperand(1);
19270 if (!Commute && MayFoldLoad(N1))
19272 // Avoid disabling potential load folding opportunities.
19273 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op)))
19275 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op)))
19285 //===----------------------------------------------------------------------===//
19286 // X86 Inline Assembly Support
19287 //===----------------------------------------------------------------------===//
19290 // Helper to match a string separated by whitespace.
19291 bool matchAsmImpl(StringRef s, ArrayRef<const StringRef *> args) {
19292 s = s.substr(s.find_first_not_of(" \t")); // Skip leading whitespace.
19294 for (unsigned i = 0, e = args.size(); i != e; ++i) {
19295 StringRef piece(*args[i]);
19296 if (!s.startswith(piece)) // Check if the piece matches.
19299 s = s.substr(piece.size());
19300 StringRef::size_type pos = s.find_first_not_of(" \t");
19301 if (pos == 0) // We matched a prefix.
19309 const VariadicFunction1<bool, StringRef, StringRef, matchAsmImpl> matchAsm={};
19312 static bool clobbersFlagRegisters(const SmallVector<StringRef, 4> &AsmPieces) {
19314 if (AsmPieces.size() == 3 || AsmPieces.size() == 4) {
19315 if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{cc}") &&
19316 std::count(AsmPieces.begin(), AsmPieces.end(), "~{flags}") &&
19317 std::count(AsmPieces.begin(), AsmPieces.end(), "~{fpsr}")) {
19319 if (AsmPieces.size() == 3)
19321 else if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{dirflag}"))
19328 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
19329 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
19331 std::string AsmStr = IA->getAsmString();
19333 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
19334 if (!Ty || Ty->getBitWidth() % 16 != 0)
19337 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
19338 SmallVector<StringRef, 4> AsmPieces;
19339 SplitString(AsmStr, AsmPieces, ";\n");
19341 switch (AsmPieces.size()) {
19342 default: return false;
19344 // FIXME: this should verify that we are targeting a 486 or better. If not,
19345 // we will turn this bswap into something that will be lowered to logical
19346 // ops instead of emitting the bswap asm. For now, we don't support 486 or
19347 // lower so don't worry about this.
19349 if (matchAsm(AsmPieces[0], "bswap", "$0") ||
19350 matchAsm(AsmPieces[0], "bswapl", "$0") ||
19351 matchAsm(AsmPieces[0], "bswapq", "$0") ||
19352 matchAsm(AsmPieces[0], "bswap", "${0:q}") ||
19353 matchAsm(AsmPieces[0], "bswapl", "${0:q}") ||
19354 matchAsm(AsmPieces[0], "bswapq", "${0:q}")) {
19355 // No need to check constraints, nothing other than the equivalent of
19356 // "=r,0" would be valid here.
19357 return IntrinsicLowering::LowerToByteSwap(CI);
19360 // rorw $$8, ${0:w} --> llvm.bswap.i16
19361 if (CI->getType()->isIntegerTy(16) &&
19362 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
19363 (matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") ||
19364 matchAsm(AsmPieces[0], "rolw", "$$8,", "${0:w}"))) {
19366 const std::string &ConstraintsStr = IA->getConstraintString();
19367 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
19368 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
19369 if (clobbersFlagRegisters(AsmPieces))
19370 return IntrinsicLowering::LowerToByteSwap(CI);
19374 if (CI->getType()->isIntegerTy(32) &&
19375 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
19376 matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") &&
19377 matchAsm(AsmPieces[1], "rorl", "$$16,", "$0") &&
19378 matchAsm(AsmPieces[2], "rorw", "$$8,", "${0:w}")) {
19380 const std::string &ConstraintsStr = IA->getConstraintString();
19381 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
19382 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
19383 if (clobbersFlagRegisters(AsmPieces))
19384 return IntrinsicLowering::LowerToByteSwap(CI);
19387 if (CI->getType()->isIntegerTy(64)) {
19388 InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints();
19389 if (Constraints.size() >= 2 &&
19390 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
19391 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
19392 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
19393 if (matchAsm(AsmPieces[0], "bswap", "%eax") &&
19394 matchAsm(AsmPieces[1], "bswap", "%edx") &&
19395 matchAsm(AsmPieces[2], "xchgl", "%eax,", "%edx"))
19396 return IntrinsicLowering::LowerToByteSwap(CI);
19404 /// getConstraintType - Given a constraint letter, return the type of
19405 /// constraint it is for this target.
19406 X86TargetLowering::ConstraintType
19407 X86TargetLowering::getConstraintType(const std::string &Constraint) const {
19408 if (Constraint.size() == 1) {
19409 switch (Constraint[0]) {
19420 return C_RegisterClass;
19444 return TargetLowering::getConstraintType(Constraint);
19447 /// Examine constraint type and operand type and determine a weight value.
19448 /// This object must already have been set up with the operand type
19449 /// and the current alternative constraint selected.
19450 TargetLowering::ConstraintWeight
19451 X86TargetLowering::getSingleConstraintMatchWeight(
19452 AsmOperandInfo &info, const char *constraint) const {
19453 ConstraintWeight weight = CW_Invalid;
19454 Value *CallOperandVal = info.CallOperandVal;
19455 // If we don't have a value, we can't do a match,
19456 // but allow it at the lowest weight.
19457 if (CallOperandVal == NULL)
19459 Type *type = CallOperandVal->getType();
19460 // Look at the constraint type.
19461 switch (*constraint) {
19463 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
19474 if (CallOperandVal->getType()->isIntegerTy())
19475 weight = CW_SpecificReg;
19480 if (type->isFloatingPointTy())
19481 weight = CW_SpecificReg;
19484 if (type->isX86_MMXTy() && Subtarget->hasMMX())
19485 weight = CW_SpecificReg;
19489 if (((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasSSE1()) ||
19490 ((type->getPrimitiveSizeInBits() == 256) && Subtarget->hasFp256()))
19491 weight = CW_Register;
19494 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) {
19495 if (C->getZExtValue() <= 31)
19496 weight = CW_Constant;
19500 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
19501 if (C->getZExtValue() <= 63)
19502 weight = CW_Constant;
19506 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
19507 if ((C->getSExtValue() >= -0x80) && (C->getSExtValue() <= 0x7f))
19508 weight = CW_Constant;
19512 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
19513 if ((C->getZExtValue() == 0xff) || (C->getZExtValue() == 0xffff))
19514 weight = CW_Constant;
19518 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
19519 if (C->getZExtValue() <= 3)
19520 weight = CW_Constant;
19524 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
19525 if (C->getZExtValue() <= 0xff)
19526 weight = CW_Constant;
19531 if (dyn_cast<ConstantFP>(CallOperandVal)) {
19532 weight = CW_Constant;
19536 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
19537 if ((C->getSExtValue() >= -0x80000000LL) &&
19538 (C->getSExtValue() <= 0x7fffffffLL))
19539 weight = CW_Constant;
19543 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
19544 if (C->getZExtValue() <= 0xffffffff)
19545 weight = CW_Constant;
19552 /// LowerXConstraint - try to replace an X constraint, which matches anything,
19553 /// with another that has more specific requirements based on the type of the
19554 /// corresponding operand.
19555 const char *X86TargetLowering::
19556 LowerXConstraint(EVT ConstraintVT) const {
19557 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
19558 // 'f' like normal targets.
19559 if (ConstraintVT.isFloatingPoint()) {
19560 if (Subtarget->hasSSE2())
19562 if (Subtarget->hasSSE1())
19566 return TargetLowering::LowerXConstraint(ConstraintVT);
19569 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
19570 /// vector. If it is invalid, don't add anything to Ops.
19571 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
19572 std::string &Constraint,
19573 std::vector<SDValue>&Ops,
19574 SelectionDAG &DAG) const {
19575 SDValue Result(0, 0);
19577 // Only support length 1 constraints for now.
19578 if (Constraint.length() > 1) return;
19580 char ConstraintLetter = Constraint[0];
19581 switch (ConstraintLetter) {
19584 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
19585 if (C->getZExtValue() <= 31) {
19586 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
19592 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
19593 if (C->getZExtValue() <= 63) {
19594 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
19600 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
19601 if (isInt<8>(C->getSExtValue())) {
19602 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
19608 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
19609 if (C->getZExtValue() <= 255) {
19610 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
19616 // 32-bit signed value
19617 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
19618 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
19619 C->getSExtValue())) {
19620 // Widen to 64 bits here to get it sign extended.
19621 Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64);
19624 // FIXME gcc accepts some relocatable values here too, but only in certain
19625 // memory models; it's complicated.
19630 // 32-bit unsigned value
19631 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
19632 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
19633 C->getZExtValue())) {
19634 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
19638 // FIXME gcc accepts some relocatable values here too, but only in certain
19639 // memory models; it's complicated.
19643 // Literal immediates are always ok.
19644 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
19645 // Widen to 64 bits here to get it sign extended.
19646 Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64);
19650 // In any sort of PIC mode addresses need to be computed at runtime by
19651 // adding in a register or some sort of table lookup. These can't
19652 // be used as immediates.
19653 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC())
19656 // If we are in non-pic codegen mode, we allow the address of a global (with
19657 // an optional displacement) to be used with 'i'.
19658 GlobalAddressSDNode *GA = 0;
19659 int64_t Offset = 0;
19661 // Match either (GA), (GA+C), (GA+C1+C2), etc.
19663 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
19664 Offset += GA->getOffset();
19666 } else if (Op.getOpcode() == ISD::ADD) {
19667 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
19668 Offset += C->getZExtValue();
19669 Op = Op.getOperand(0);
19672 } else if (Op.getOpcode() == ISD::SUB) {
19673 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
19674 Offset += -C->getZExtValue();
19675 Op = Op.getOperand(0);
19680 // Otherwise, this isn't something we can handle, reject it.
19684 const GlobalValue *GV = GA->getGlobal();
19685 // If we require an extra load to get this address, as in PIC mode, we
19686 // can't accept it.
19687 if (isGlobalStubReference(Subtarget->ClassifyGlobalReference(GV,
19688 getTargetMachine())))
19691 Result = DAG.getTargetGlobalAddress(GV, SDLoc(Op),
19692 GA->getValueType(0), Offset);
19697 if (Result.getNode()) {
19698 Ops.push_back(Result);
19701 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
19704 std::pair<unsigned, const TargetRegisterClass*>
19705 X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
19707 // First, see if this is a constraint that directly corresponds to an LLVM
19709 if (Constraint.size() == 1) {
19710 // GCC Constraint Letters
19711 switch (Constraint[0]) {
19713 // TODO: Slight differences here in allocation order and leaving
19714 // RIP in the class. Do they matter any more here than they do
19715 // in the normal allocation?
19716 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
19717 if (Subtarget->is64Bit()) {
19718 if (VT == MVT::i32 || VT == MVT::f32)
19719 return std::make_pair(0U, &X86::GR32RegClass);
19720 if (VT == MVT::i16)
19721 return std::make_pair(0U, &X86::GR16RegClass);
19722 if (VT == MVT::i8 || VT == MVT::i1)
19723 return std::make_pair(0U, &X86::GR8RegClass);
19724 if (VT == MVT::i64 || VT == MVT::f64)
19725 return std::make_pair(0U, &X86::GR64RegClass);
19728 // 32-bit fallthrough
19729 case 'Q': // Q_REGS
19730 if (VT == MVT::i32 || VT == MVT::f32)
19731 return std::make_pair(0U, &X86::GR32_ABCDRegClass);
19732 if (VT == MVT::i16)
19733 return std::make_pair(0U, &X86::GR16_ABCDRegClass);
19734 if (VT == MVT::i8 || VT == MVT::i1)
19735 return std::make_pair(0U, &X86::GR8_ABCD_LRegClass);
19736 if (VT == MVT::i64)
19737 return std::make_pair(0U, &X86::GR64_ABCDRegClass);
19739 case 'r': // GENERAL_REGS
19740 case 'l': // INDEX_REGS
19741 if (VT == MVT::i8 || VT == MVT::i1)
19742 return std::make_pair(0U, &X86::GR8RegClass);
19743 if (VT == MVT::i16)
19744 return std::make_pair(0U, &X86::GR16RegClass);
19745 if (VT == MVT::i32 || VT == MVT::f32 || !Subtarget->is64Bit())
19746 return std::make_pair(0U, &X86::GR32RegClass);
19747 return std::make_pair(0U, &X86::GR64RegClass);
19748 case 'R': // LEGACY_REGS
19749 if (VT == MVT::i8 || VT == MVT::i1)
19750 return std::make_pair(0U, &X86::GR8_NOREXRegClass);
19751 if (VT == MVT::i16)
19752 return std::make_pair(0U, &X86::GR16_NOREXRegClass);
19753 if (VT == MVT::i32 || !Subtarget->is64Bit())
19754 return std::make_pair(0U, &X86::GR32_NOREXRegClass);
19755 return std::make_pair(0U, &X86::GR64_NOREXRegClass);
19756 case 'f': // FP Stack registers.
19757 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
19758 // value to the correct fpstack register class.
19759 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
19760 return std::make_pair(0U, &X86::RFP32RegClass);
19761 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
19762 return std::make_pair(0U, &X86::RFP64RegClass);
19763 return std::make_pair(0U, &X86::RFP80RegClass);
19764 case 'y': // MMX_REGS if MMX allowed.
19765 if (!Subtarget->hasMMX()) break;
19766 return std::make_pair(0U, &X86::VR64RegClass);
19767 case 'Y': // SSE_REGS if SSE2 allowed
19768 if (!Subtarget->hasSSE2()) break;
19770 case 'x': // SSE_REGS if SSE1 allowed or AVX_REGS if AVX allowed
19771 if (!Subtarget->hasSSE1()) break;
19773 switch (VT.SimpleTy) {
19775 // Scalar SSE types.
19778 return std::make_pair(0U, &X86::FR32RegClass);
19781 return std::make_pair(0U, &X86::FR64RegClass);
19789 return std::make_pair(0U, &X86::VR128RegClass);
19797 return std::make_pair(0U, &X86::VR256RegClass);
19802 return std::make_pair(0U, &X86::VR512RegClass);
19808 // Use the default implementation in TargetLowering to convert the register
19809 // constraint into a member of a register class.
19810 std::pair<unsigned, const TargetRegisterClass*> Res;
19811 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
19813 // Not found as a standard register?
19814 if (Res.second == 0) {
19815 // Map st(0) -> st(7) -> ST0
19816 if (Constraint.size() == 7 && Constraint[0] == '{' &&
19817 tolower(Constraint[1]) == 's' &&
19818 tolower(Constraint[2]) == 't' &&
19819 Constraint[3] == '(' &&
19820 (Constraint[4] >= '0' && Constraint[4] <= '7') &&
19821 Constraint[5] == ')' &&
19822 Constraint[6] == '}') {
19824 Res.first = X86::ST0+Constraint[4]-'0';
19825 Res.second = &X86::RFP80RegClass;
19829 // GCC allows "st(0)" to be called just plain "st".
19830 if (StringRef("{st}").equals_lower(Constraint)) {
19831 Res.first = X86::ST0;
19832 Res.second = &X86::RFP80RegClass;
19837 if (StringRef("{flags}").equals_lower(Constraint)) {
19838 Res.first = X86::EFLAGS;
19839 Res.second = &X86::CCRRegClass;
19843 // 'A' means EAX + EDX.
19844 if (Constraint == "A") {
19845 Res.first = X86::EAX;
19846 Res.second = &X86::GR32_ADRegClass;
19852 // Otherwise, check to see if this is a register class of the wrong value
19853 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
19854 // turn into {ax},{dx}.
19855 if (Res.second->hasType(VT))
19856 return Res; // Correct type already, nothing to do.
19858 // All of the single-register GCC register classes map their values onto
19859 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
19860 // really want an 8-bit or 32-bit register, map to the appropriate register
19861 // class and return the appropriate register.
19862 if (Res.second == &X86::GR16RegClass) {
19863 if (VT == MVT::i8 || VT == MVT::i1) {
19864 unsigned DestReg = 0;
19865 switch (Res.first) {
19867 case X86::AX: DestReg = X86::AL; break;
19868 case X86::DX: DestReg = X86::DL; break;
19869 case X86::CX: DestReg = X86::CL; break;
19870 case X86::BX: DestReg = X86::BL; break;
19873 Res.first = DestReg;
19874 Res.second = &X86::GR8RegClass;
19876 } else if (VT == MVT::i32 || VT == MVT::f32) {
19877 unsigned DestReg = 0;
19878 switch (Res.first) {
19880 case X86::AX: DestReg = X86::EAX; break;
19881 case X86::DX: DestReg = X86::EDX; break;
19882 case X86::CX: DestReg = X86::ECX; break;
19883 case X86::BX: DestReg = X86::EBX; break;
19884 case X86::SI: DestReg = X86::ESI; break;
19885 case X86::DI: DestReg = X86::EDI; break;
19886 case X86::BP: DestReg = X86::EBP; break;
19887 case X86::SP: DestReg = X86::ESP; break;
19890 Res.first = DestReg;
19891 Res.second = &X86::GR32RegClass;
19893 } else if (VT == MVT::i64 || VT == MVT::f64) {
19894 unsigned DestReg = 0;
19895 switch (Res.first) {
19897 case X86::AX: DestReg = X86::RAX; break;
19898 case X86::DX: DestReg = X86::RDX; break;
19899 case X86::CX: DestReg = X86::RCX; break;
19900 case X86::BX: DestReg = X86::RBX; break;
19901 case X86::SI: DestReg = X86::RSI; break;
19902 case X86::DI: DestReg = X86::RDI; break;
19903 case X86::BP: DestReg = X86::RBP; break;
19904 case X86::SP: DestReg = X86::RSP; break;
19907 Res.first = DestReg;
19908 Res.second = &X86::GR64RegClass;
19911 } else if (Res.second == &X86::FR32RegClass ||
19912 Res.second == &X86::FR64RegClass ||
19913 Res.second == &X86::VR128RegClass ||
19914 Res.second == &X86::VR256RegClass ||
19915 Res.second == &X86::FR32XRegClass ||
19916 Res.second == &X86::FR64XRegClass ||
19917 Res.second == &X86::VR128XRegClass ||
19918 Res.second == &X86::VR256XRegClass ||
19919 Res.second == &X86::VR512RegClass) {
19920 // Handle references to XMM physical registers that got mapped into the
19921 // wrong class. This can happen with constraints like {xmm0} where the
19922 // target independent register mapper will just pick the first match it can
19923 // find, ignoring the required type.
19925 if (VT == MVT::f32 || VT == MVT::i32)
19926 Res.second = &X86::FR32RegClass;
19927 else if (VT == MVT::f64 || VT == MVT::i64)
19928 Res.second = &X86::FR64RegClass;
19929 else if (X86::VR128RegClass.hasType(VT))
19930 Res.second = &X86::VR128RegClass;
19931 else if (X86::VR256RegClass.hasType(VT))
19932 Res.second = &X86::VR256RegClass;
19933 else if (X86::VR512RegClass.hasType(VT))
19934 Res.second = &X86::VR512RegClass;